[gcc.git] / gcc / config / rl78 / rl78-real.md

;;  Machine Description for Renesas RL78 processors
;;  Copyright (C) 2011-2015 Free Software Foundation, Inc.
;;  Contributed by Red Hat.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.

;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.
\f
;; The insns in this file correspond to the actual opcodes the RL78
;; can issue with real registers.  All insns in here should be
;; conditional on rl78_real_insns_ok() returning true, and should
;; allow virtual registers in their predicates - the reorg pass that
;; allocates physical registers uses the constraints to select
;; registers, but insns with virtual registers MUST match one of these
;; patterns - other than the constraints - so that the operand info is
;; properly set up for the alloc pass.

;;---------- Moving ------------------------

(define_insn "movqi_es"
  [(set (reg:QI ES_REG)
	(match_operand:QI 0 "register_operand" "a"))]
  ""
  "mov\tes, %0"
)

(define_insn "movqi_from_es"
  [(set (match_operand:QI 0 "register_operand" "=a")
	(reg:QI ES_REG))]
  ""
  "mov\t%0, es"
)

(define_insn "movqi_cs"
  [(set (reg:QI CS_REG)
	(match_operand:QI 0 "register_operand" "a"))]
  ""
  "mov\tcs, %0"
)

(define_insn "*movqi_real"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=g,RaxbcWab,RaxbcWab,a,                          bcx,R, WabWd2WhlWh1WhbWbcWs1v, bcx")
	(match_operand    1 "general_operand"      "0,K,        M,       RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a,                      R"))]
  "rl78_real_insns_ok ()"
  "@
   ; mov\t%0, %1
   oneb\t%0
   clrb\t%0
   mov\t%0, %1
   mov\t%0, %1
   mov\t%0, %1
   mov\t%0, %1
   mov\t%0, %S1"
)

(define_insn "*movhi_real"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=g,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
	(match_operand:HI 1 "general_operand"      " 0,K, M, i,  BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS,  ABDT"))]
  "rl78_real_insns_ok ()"
  "@
   ; movw\t%0, %1
   onew\t%0
   clrw\t%0
   movw\t%0, %1
   movw\t%0, %1
   movw\t%0, %1
   movw\t%0, %S1
   movw\t%0, %1
   movw\t%0, %1"
)

;;---------- Conversions ------------------------

(define_insn "*zero_extendqihi2_real"
  [(set (match_operand:HI                 0 "nonimmediate_operand" "=rv,A")
	(zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))]
  "rl78_real_insns_ok ()"
  "@
   mov\t%Q0, #0
   mov\tx, a \;mov\ta, #0"
  )

(define_insn "*extendqihi2_real"
  [(set (match_operand:HI                 0 "nonimmediate_operand" "=A,A")
	(sign_extend:HI (match_operand:QI 1 "general_operand" "x,a")))]
  "rl78_real_insns_ok ()"
  "@
   shlw\t%0, 8 \;sarw\t%0, 8
   sarw\t%0, 8"
  )

;;---------- Arithmetic ------------------------

(define_insn "*addqi3_real"
  [(set (match_operand:QI          0 "nonimmediate_operand"  "=rvWabWhlWh1,rvWabWhlWh1,a,*bcdehl")
	(plus:QI (match_operand:QI 1 "general_operand"  "%0,0,0,0")
		 (match_operand:QI 2 "general_operand" "K,L,RWhlWh1Wabi,a")))
   ]
  "rl78_real_insns_ok ()"
  "@
    inc\t%0
    dec\t%0
    add\t%0, %2
    add\t%0, %2"
)

(define_insn "*addhi3_real"
  [(set (match_operand:HI          0 "nonimmediate_operand"  "=vABDTWh1Wab,vABDTWh1Wab,v,v,A,S,S,A")
	(plus:HI (match_operand:HI 1 "general_operand"  "%0,0,0,0,0,0,0,S")
		 (match_operand:HI 2 "general_operand" "K,L,N,O,RWh1WhlWabiv,Int8,J,Ri")))
   ]
  "rl78_real_insns_ok ()"
  "@
   incw\t%0
   decw\t%0
   incw\t%0 \;incw\t%0
   decw\t%0 \;decw\t%0
   addw\t%0, %p2
   addw\t%0, %2
   subw\t%0, %m2
   movw\t%0, %1 \;addw\t%0, %2"
)

(define_insn "*addqihi3a_real"
  [(set (match_operand:HI                          0 "register_operand" "=r")
	(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand"  "r"))
		 (match_operand:HI                 2 "register_operand"  "0")))
   ]
  "rl78_real_insns_ok ()"
  "add\t%q0, %q1 \;addc\t%Q0, #0"
)

(define_insn "*subqi3_real"
  [(set (match_operand:QI           0 "nonimmediate_operand"  "=a,R,v")
	(minus:QI (match_operand:QI 1 "general_operand"  "0,0,0")
		  (match_operand:QI 2 "general_operand" "RiWabWhbWh1Whl,a,i")))
   ]
  "rl78_real_insns_ok ()"
  "sub\t%0, %2"
)

(define_insn "*subhi3_real"
  [(set (match_operand:HI           0 "nonimmediate_operand"  "=A,S")
	(minus:HI (match_operand:HI 1 "general_operand"  "0,0")
		  (match_operand:HI 2 "general_operand" "iBDTWabWh1v,i")))
   ]
  "rl78_real_insns_ok ()"
  "subw\t%0, %2"
)

(define_insn "*umulhi3_shift_real"
  [(set (match_operand:HI 0 "register_operand" "=A,A")
        (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "0,0")
                 (match_operand:HI 2 "rl78_24_operand" "N,i")))]
  "rl78_real_insns_ok () && !TARGET_G10"
  "@
   shlw\t%0, 1
   shlw\t%0, 2"
)

(define_insn "*umulqihi3_real"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=A")
        (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%a"))
                 (zero_extend:HI (match_operand:QI 2 "general_operand" "x"))))]
  "rl78_real_insns_ok () && !TARGET_G10"
  "mulu\t%2"
)

(define_insn "*andqi3_real"
  [(set (match_operand:QI         0 "nonimmediate_operand"  "=A,R,v")
	(and:QI (match_operand:QI 1 "general_operand"       "%0,0,0")
		(match_operand:QI 2 "general_operand"       "iRvWabWhbWh1Whl,A,i")))
   ]
  "rl78_real_insns_ok ()"
  "and\t%0, %2"
)

(define_insn "*iorqi3_real"
  [(set (match_operand:QI         0 "nonimmediate_operand"  "=A,R,v")
	(ior:QI (match_operand:QI 1 "general_operand"       "%0,0,0")
		(match_operand:QI 2 "general_operand"       "iRvWabWhbWh1Whl,A,i")))
   ]
  "rl78_real_insns_ok ()"
  "or\t%0, %2"
)

(define_insn "*xorqi3_real"
  [(set (match_operand:QI         0 "nonimmediate_operand"  "=A,R,v")
	(xor:QI (match_operand:QI 1 "general_operand"       "%0,0,0")
		(match_operand    2 "general_operand"       "iRvWabWhbWh1Whl,A,i")))
   ]
  "rl78_real_insns_ok ()"
  "xor\t%0, %2"
)

;;---------- Shifts ------------------------

(define_insn "*ashlqi3_real"
  [(set (match_operand:QI            0 "nonimmediate_operand"  "=abc,a,a")
	(ashift:QI (match_operand:QI 1 "general_operand"  "0,0,0")
		   (match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   shl\t%0, %u2
   cmp0 %2\; bz $2f\; 1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:"
)

(define_insn "*ashlhi3_real"
  [(set (match_operand:HI            0 "nonimmediate_operand"  "=AB,A,A")
	(ashift:HI (match_operand:HI 1 "general_operand"  "0,0,0")
		   (match_operand:QI 2 "general_operand" "P,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   shlw\t%0, %u2
   cmp0 %2\; bz $2f\; 1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:"
)

;;----------

(define_insn "*ashrqi3_real"
  [(set (match_operand:QI              0 "nonimmediate_operand"  "=abc,a,a")
	(ashiftrt:QI (match_operand:QI 1 "general_operand"  "0,0,0")
		     (match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   sar\t%0, %u2
   cmp0 %2\; bz $2f\; 1: sar\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: sar\t%0, 1\;dec %2 \;bnz $1b\;2:"
)

(define_insn "*ashrhi3_real"
  [(set (match_operand:HI              0 "nonimmediate_operand"  "=AB,A,A")
	(ashiftrt:HI (match_operand:HI 1 "general_operand"  "0,0,0")
		     (match_operand:QI 2 "general_operand" "P,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   sarw\t%0, %u2
   cmp0 %2\; bz $2f\; 1: sarw\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: sarw\t%0, 1\;dec %2\;bnz $1b\;2:"
)

;;----------

(define_insn "*lshrqi3_real"
  [(set (match_operand:QI              0 "nonimmediate_operand"  "=abc,a,a")
	(lshiftrt:QI (match_operand:QI 1 "general_operand"  "0,0,0")
		     (match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   shr\t%0, %u2
   cmp0 %2\; bz $2f\; 1: shr\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: shr\t%0, 1\;dec %2\;bnz $1b\;2:"
)

(define_insn "*lshrhi3_real"
  [(set (match_operand:HI              0 "nonimmediate_operand"  "=AB,A,A")
	(lshiftrt:HI (match_operand:HI 1 "general_operand"  "0,0,0")
		     (match_operand:QI 2 "general_operand" "P,bc,dehl")))
   ]
  "rl78_real_insns_ok ()"
  "@
   shrw\t%0, %u2
   cmp0 %2\; bz $2f\; 1: shrw\t%0, 1 \;dec %2 \;bnz $1b\;2:
   inc %2\;dec %2\;bz $2f\;1: shrw\t%0, 1\;dec %2\;bnz $1b\;2:"
)

;;---------- Branching ------------------------

(define_insn "*indirect_jump_real"
  [(set (pc)
	(match_operand:HI 0 "nonimmediate_operand" "A"))]
  "rl78_real_insns_ok ()"
  "br\t%0"
)

(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  ;; $rel8, $!rel16, !abs16, !!abs20
  "br\t!!%0"
)

(define_insn "*call_real"
  [(call (match_operand:HI 0 "memory_operand" "Wab,Wca")
	 (match_operand 1 "" ""))]
  "rl78_real_insns_ok ()"
  "@
   call\t!!%A0
   call\t%A0"
  )

(define_insn "*call_value_real"
  [(set (match_operand 0 "register_operand" "=v,v")
	(call (match_operand:HI 1 "memory_operand" "Wab,Wca")
	      (match_operand 2 "" "")))]
  "rl78_real_insns_ok ()"
  "@
   call\t!!%A1
   call\t%A1"
  )

(define_insn "*cbranchqi4_real_signed"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_signed"
			      [(match_operand:QI 1 "general_operand" "A,A,A")
			       (match_operand:QI 2 "general_operand" "ISqi,i,v")])
              (label_ref (match_operand 3 "" ""))
	      (pc)))]
  "rl78_real_insns_ok ()"
  "@
   cmp\t%1, %2 \;xor1 CY,%1.7\;not1 CY\;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;xor1 CY,%1.7\;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;xor1 CY,%1.7\;xor1 CY,%2.7\;sk%C0 \;br\t!!%3"
  )

(define_insn "*cbranchqi4_real"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_real"
			      [(match_operand:QI 1 "general_operand" "Wabvaxbc,a,              v,bcdehl")
			       (match_operand:QI 2 "general_operand" "M,       irvWabWhlWh1Whb,i,a")])
              (label_ref (match_operand 3 "" ""))
	      (pc)))]
  "rl78_real_insns_ok ()"
  "@
   cmp0\t%1 \;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;sk%C0 \;br\t!!%3
   cmp\t%1, %2 \;sk%C0 \;br\t!!%3"
  )

(define_insn "*cbranchhi4_real_signed"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_signed"
			      [(match_operand:HI 1 "general_operand" "A,A,A,vR")
			       (match_operand:HI 2 "general_operand" "IShi,i,v,1")])
              (label_ref (match_operand 3))
	      (pc)))]
  "rl78_real_insns_ok ()"
  "@
   cmpw\t%1, %2 \;xor1 CY,%Q1.7\;not1 CY\;sk%C0 \;br\t!!%3
   cmpw\t%1, %2 \;xor1 CY,%Q1.7\;sk%C0 \;br\t!!%3
   cmpw\t%1, %2 \;xor1 CY,%Q1.7\;xor1 CY,%Q2.7\;sk%C0 \;br\t!!%3
   %z0\t!!%3"
  )

(define_insn "cbranchhi4_real"
  [(set (pc) (if_then_else
	      (match_operator                    0 "rl78_cmp_operator_real"
			      [(match_operand:HI 1 "general_operand" "A,vR")
			       (match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1,1")])
              (label_ref (match_operand          3 "" ""))
	      (pc)))]
  "rl78_real_insns_ok ()"
  "@
  cmpw\t%1, %2 \;sk%C0 \;br\t!!%3
  %z0\t!!%3"
  )

(define_insn "cbranchhi4_real_inverted"  
  [(set (pc) (if_then_else
	      (match_operator                    0 "rl78_cmp_operator_real"
			      [(match_operand:HI 1 "general_operand" "A")
			       (match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1")])
	      (pc)
              (label_ref (match_operand          3 "" ""))))]
  "rl78_real_insns_ok ()"
  "cmpw\t%1, %2 \;sk%C0 \;br\t!!%3"
  )

(define_insn "*cbranchsi4_real_lt"
  [(set (pc) (if_then_else
	      (lt (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
		  (const_int 0))
              (label_ref (match_operand 1 "" ""))
	      (pc)))
   (clobber (reg:HI AX_REG))
   ]
  "rl78_real_insns_ok ()"
  "@
   mov a, %E0 \;mov1 CY,a.7 \;sknc \;br\t!!%1
   mov1 CY,%E0.7 \;sknc \;br\t!!%1"
  )

(define_insn "*cbranchsi4_real_ge"
  [(set (pc) (if_then_else
	      (ge (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
		  (const_int 0))
              (label_ref (match_operand 1 "" ""))
	      (pc)))
   (clobber (reg:HI AX_REG))
   ]
  "rl78_real_insns_ok ()"
  "@
   mov a, %E0 \;mov1 CY,a.7 \;skc \;br\t!!%1
   mov1 CY,%E0.7 \;skc \;br\t!!%1"
  )

(define_insn "*cbranchsi4_real_signed"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_signed"
			      [(match_operand:SI 1 "general_operand"   "vU,vU,vU,i,i")
			       (match_operand:SI 2 "nonmemory_operand" "ISsi,i,v,S,v")])
              (label_ref (match_operand 3 "" ""))
	      (pc)))
   (clobber (reg:HI AX_REG))
   ]
  "rl78_real_insns_ok ()"
  "@
   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;not1 CY\;      movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3
   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;               movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3
   movw ax,%H1 \;cmpw  ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3
   movw ax, %H1\; cmpw  ax, %H2\; xor1 CY, a.7\; not1 CY\; movw ax, %h1 \;sknz\; cmpw  ax, %h2 \;sk%0 \;br\t!!%3
   movw ax, %H1\; cmpw  ax, %H2\; xor1 CY, a.7\; movw ax, %h1\; sknz\; cmpw ax, %h2\; sk%0\; br\t!!%3"
  )

(define_insn "*cbranchsi4_real"
  [(set (pc) (if_then_else
	      (match_operator 0 "rl78_cmp_operator_real"
			      [(match_operand:SI 1 "general_operand" "vUi")
			       (match_operand:SI 2 "general_operand" "iWhlWh1v")])
              (label_ref (match_operand 3 "" ""))
	      (pc)))
   (clobber (reg:HI AX_REG))
   ]
  "rl78_real_insns_ok ()"
  "movw ax,%H1 \;cmpw  ax, %H2 \;movw ax,%h1 \;sknz \;cmpw  ax, %h2 \;sk%C0 \;br\t!!%3"
  )

;; Peephole to match:
;;
;;     (set (mem (sp)) (ax))
;;     (set (ax) (mem (sp)))
;; or:
;;     (set (mem (plus (sp) (const)) (ax))
;;     (set (ax) (mem (plus (sp) (const))))
;;
;; which can be generated as the last instruction of the conversion
;; of one virtual insn into a real insn and the first instruction of
;; the conversion of the following virtual insn.

(define_peephole2
  [(set (match_operand:HI 0 "rl78_stack_based_mem")
	(reg:HI AX_REG))
   (set (reg:HI AX_REG)
	(match_dup 0))]
  ""
  [(set (match_dup 0) (reg:HI AX_REG))]
  )

;; Bit test and branch insns.

;; NOTE: These patterns will work for bits in other places, not just A.

(define_insn "bf"
  [(set (pc)
	(if_then_else (eq (and (reg:QI A_REG)
			       (match_operand 0 "immediate_operand" "n"))
			  (const_int 0))
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "bf\tA.%B0, $%1"
)

(define_insn "bt"
  [(set (pc)
	(if_then_else (ne (and (reg:QI A_REG)
			       (match_operand 0 "immediate_operand" "n"))
			  (const_int 0))
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "bt\tA.%B0, $%1"
)

;; NOTE: These peepholes are fragile.  They rely upon GCC generating
;; a specific sequence on insns, based upon examination of test code.
;; Improvements to GCC or using code other than the test code can result
;; in the peephole not matching and the optimization being missed.

(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (pc) (if_then_else (eq (match_dup 0) (const_int 0))
			   (label_ref (match_operand 2 ""))
			   (pc)))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))
   && exact_log2 (INTVAL (operands[1])) >= 0"
  [(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
			   (label_ref (match_dup 2))
			   (pc)))]
  )

(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
			   (label_ref (match_operand 2 ""))
			   (pc)))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))
   && exact_log2 (INTVAL (operands[1])) >= 0"
  [(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
			   (label_ref (match_dup 2))
			   (pc)))]
  )

;; Eliminate needless register copies.
(define_peephole2
  [(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand"))
   (set (match_operand:HI 2 "register_operand") (match_dup 0))]
  "peep2_regno_dead_p (2, REGNO (operands[0]))
   && (REGNO (operands[1]) < 8 || REGNO (operands[2]) < 8)"
  [(set (match_dup 2) (match_dup 1))]
  )

;; Eliminate needless register copying when performing bit manipulations.
(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (ior:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (reg:QI A_REG) (match_dup 0))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))"
  [(set (reg:QI A_REG) (ior:QI (reg:QI A_REG) (match_dup 1)))]
  )

(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (xor:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (reg:QI A_REG) (match_dup 0))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))"
  [(set (reg:QI A_REG) (xor:QI (reg:QI A_REG) (match_dup 1)))]
  )

(define_peephole2
  [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
   (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
   (set (reg:QI A_REG) (match_dup 0))]
  "peep2_regno_dead_p (3, REGNO (operands[0]))"
  [(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))]
  )

(define_insn "*negandhi3_real"
  [(set (match_operand:HI                 0 "register_operand"  "=A")
	(and:HI (neg:HI (match_operand:HI 1 "register_operand"  "0"))
		(match_operand:HI         2 "immediate_operand" "n")))
   ]
  "rl78_real_insns_ok ()"
  "xor a, #0xff @ xch a, x @ xor a, #0xff @ xch a, x @ addw ax, #1 @ and a, %Q2 @ xch a, x @ and a, %q2 @ xch a, x"
)
Commit	Line	Data
85b8555e	1	;; Machine Description for Renesas RL78 processors
5624e564	2	;; Copyright (C) 2011-2015 Free Software Foundation, Inc.
85b8555e DD	3	;; Contributed by Red Hat.
	4
	5	;; This file is part of GCC.
	6
	7	;; GCC is free software; you can redistribute it and/or modify
	8	;; it under the terms of the GNU General Public License as published by
	9	;; the Free Software Foundation; either version 3, or (at your option)
	10	;; any later version.
	11
	12	;; GCC is distributed in the hope that it will be useful,
	13	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	;; GNU General Public License for more details.
	16
	17	;; You should have received a copy of the GNU General Public License
	18	;; along with GCC; see the file COPYING3. If not see
	19	;; <http://www.gnu.org/licenses/>.
	20	\f
	21	;; The insns in this file correspond to the actual opcodes the RL78
	22	;; can issue with real registers. All insns in here should be
	23	;; conditional on rl78_real_insns_ok() returning true, and should
	24	;; allow virtual registers in their predicates - the reorg pass that
	25	;; allocates physical registers uses the constraints to select
	26	;; registers, but insns with virtual registers MUST match one of these
	27	;; patterns - other than the constraints - so that the operand info is
	28	;; properly set up for the alloc pass.
	29
	30	;;---------- Moving ------------------------
	31
	32	(define_insn "movqi_es"
	33	[(set (reg:QI ES_REG)
	34	(match_operand:QI 0 "register_operand" "a"))]
	35	""
	36	"mov\tes, %0"
	37	)
	38
7bbf5a3d NC	39	(define_insn "movqi_from_es"
	40	[(set (match_operand:QI 0 "register_operand" "=a")
	41	(reg:QI ES_REG))]
	42	""
	43	"mov\t%0, es"
	44	)
	45
85b8555e DD	46	(define_insn "movqi_cs"
	47	[(set (reg:QI CS_REG)
	48	(match_operand:QI 0 "register_operand" "a"))]
	49	""
	50	"mov\tcs, %0"
	51	)
	52
	53	(define_insn "*movqi_real"
	54	[(set (match_operand:QI 0 "nonimmediate_operand" "=g,RaxbcWab,RaxbcWab,a, bcx,R, WabWd2WhlWh1WhbWbcWs1v, bcx")
	55	(match_operand 1 "general_operand" "0,K, M, RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a, R"))]
	56	"rl78_real_insns_ok ()"
	57	"@
	58	; mov\t%0, %1
	59	oneb\t%0
	60	clrb\t%0
	61	mov\t%0, %1
	62	mov\t%0, %1
	63	mov\t%0, %1
	64	mov\t%0, %1
	65	mov\t%0, %S1"
	66	)
	67
	68	(define_insn "*movhi_real"
	69	[(set (match_operand:HI 0 "nonimmediate_operand" "=g,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
	70	(match_operand:HI 1 "general_operand" " 0,K, M, i, BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS, ABDT"))]
	71	"rl78_real_insns_ok ()"
	72	"@
	73	; movw\t%0, %1
	74	onew\t%0
	75	clrw\t%0
	76	movw\t%0, %1
	77	movw\t%0, %1
	78	movw\t%0, %1
	79	movw\t%0, %S1
	80	movw\t%0, %1
	81	movw\t%0, %1"
	82	)
	83
	84	;;---------- Conversions ------------------------
	85
	86	(define_insn "*zero_extendqihi2_real"
	87	[(set (match_operand:HI 0 "nonimmediate_operand" "=rv,A")
	88	(zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))]
	89	"rl78_real_insns_ok ()"
	90	"@
	91	mov\t%Q0, #0
	92	mov\tx, a \;mov\ta, #0"
	93	)
	94
	95	(define_insn "*extendqihi2_real"
	96	[(set (match_operand:HI 0 "nonimmediate_operand" "=A,A")
	97	(sign_extend:HI (match_operand:QI 1 "general_operand" "x,a")))]
	98	"rl78_real_insns_ok ()"
	99	"@
	100	shlw\t%0, 8 \;sarw\t%0, 8
	101	sarw\t%0, 8"
	102	)
	103
	104	;;---------- Arithmetic ------------------------
	105
	106	(define_insn "*addqi3_real"
	107	[(set (match_operand:QI 0 "nonimmediate_operand" "=rvWabWhlWh1,rvWabWhlWh1,a,*bcdehl")
	108	(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
d50b463e	109	(match_operand:QI 2 "general_operand" "K,L,RWhlWh1Wabi,a")))
85b8555e DD	110	]
	111	"rl78_real_insns_ok ()"
	112	"@
	113	inc\t%0
	114	dec\t%0
	115	add\t%0, %2
	116	add\t%0, %2"
	117	)
	118
	119	(define_insn "*addhi3_real"
	120	[(set (match_operand:HI 0 "nonimmediate_operand" "=vABDTWh1Wab,vABDTWh1Wab,v,v,A,S,S,A")
	121	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0,0,0,S")
	122	(match_operand:HI 2 "general_operand" "K,L,N,O,RWh1WhlWabiv,Int8,J,Ri")))
	123	]
	124	"rl78_real_insns_ok ()"
	125	"@
	126	incw\t%0
	127	decw\t%0
	128	incw\t%0 \;incw\t%0
	129	decw\t%0 \;decw\t%0
	130	addw\t%0, %p2
	131	addw\t%0, %2
	132	subw\t%0, %m2
	133	movw\t%0, %1 \;addw\t%0, %2"
	134	)
	135
	136	(define_insn "*addqihi3a_real"
c6f709ec NC	137	[(set (match_operand:HI 0 "register_operand" "=r")
	138	(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
	139	(match_operand:HI 2 "register_operand" "0")))
85b8555e DD	140	]
	141	"rl78_real_insns_ok ()"
	142	"add\t%q0, %q1 \;addc\t%Q0, #0"
	143	)
	144
	145	(define_insn "*subqi3_real"
	146	[(set (match_operand:QI 0 "nonimmediate_operand" "=a,R,v")
	147	(minus:QI (match_operand:QI 1 "general_operand" "0,0,0")
	148	(match_operand:QI 2 "general_operand" "RiWabWhbWh1Whl,a,i")))
	149	]
	150	"rl78_real_insns_ok ()"
	151	"sub\t%0, %2"
	152	)
	153
	154	(define_insn "*subhi3_real"
	155	[(set (match_operand:HI 0 "nonimmediate_operand" "=A,S")
	156	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
	157	(match_operand:HI 2 "general_operand" "iBDTWabWh1v,i")))
	158	]
	159	"rl78_real_insns_ok ()"
	160	"subw\t%0, %2"
	161	)
	162
	163	(define_insn "*umulhi3_shift_real"
	164	[(set (match_operand:HI 0 "register_operand" "=A,A")
	165	(mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "0,0")
	166	(match_operand:HI 2 "rl78_24_operand" "N,i")))]
e33a3cf3	167	"rl78_real_insns_ok () && !TARGET_G10"
85b8555e DD	168	"@
	169	shlw\t%0, 1
	170	shlw\t%0, 2"
	171	)
	172
	173	(define_insn "*umulqihi3_real"
	174	[(set (match_operand:HI 0 "nonimmediate_operand" "=A")
	175	(mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%a"))
	176	(zero_extend:HI (match_operand:QI 2 "general_operand" "x"))))]
e33a3cf3	177	"rl78_real_insns_ok () && !TARGET_G10"
85b8555e DD	178	"mulu\t%2"
	179	)
	180
	181	(define_insn "*andqi3_real"
	182	[(set (match_operand:QI 0 "nonimmediate_operand" "=A,R,v")
	183	(and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
	184	(match_operand:QI 2 "general_operand" "iRvWabWhbWh1Whl,A,i")))
	185	]
	186	"rl78_real_insns_ok ()"
	187	"and\t%0, %2"
	188	)
	189
	190	(define_insn "*iorqi3_real"
	191	[(set (match_operand:QI 0 "nonimmediate_operand" "=A,R,v")
	192	(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0")
	193	(match_operand:QI 2 "general_operand" "iRvWabWhbWh1Whl,A,i")))
	194	]
	195	"rl78_real_insns_ok ()"
	196	"or\t%0, %2"
	197	)
	198
	199	(define_insn "*xorqi3_real"
	200	[(set (match_operand:QI 0 "nonimmediate_operand" "=A,R,v")
	201	(xor:QI (match_operand:QI 1 "general_operand" "%0,0,0")
	202	(match_operand 2 "general_operand" "iRvWabWhbWh1Whl,A,i")))
	203	]
	204	"rl78_real_insns_ok ()"
	205	"xor\t%0, %2"
	206	)
	207
	208	;;---------- Shifts ------------------------
	209
	210	(define_insn "*ashlqi3_real"
	211	[(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
	212	(ashift:QI (match_operand:QI 1 "general_operand" "0,0,0")
	213	(match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
	214	]
	215	"rl78_real_insns_ok ()"
	216	"@
	217	shl\t%0, %u2
	218	cmp0 %2\; bz $2f\; 1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:
	219	inc %2\;dec %2\;bz $2f\;1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:"
	220	)
	221
	222	(define_insn "*ashlhi3_real"
	223	[(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
	224	(ashift:HI (match_operand:HI 1 "general_operand" "0,0,0")
	225	(match_operand:QI 2 "general_operand" "P,bc,dehl")))
	226	]
	227	"rl78_real_insns_ok ()"
	228	"@
	229	shlw\t%0, %u2
	230	cmp0 %2\; bz $2f\; 1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:
	231	inc %2\;dec %2\;bz $2f\;1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:"
	232	)
	233
	234	;;----------
	235
	236	(define_insn "*ashrqi3_real"
	237	[(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
	238	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0")
	239	(match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
	240	]
	241	"rl78_real_insns_ok ()"
242	"@
243	sar\t%0, %u2
244	cmp0 %2\; bz $2f\; 1: sar\t%0, 1 \;dec %2 \;bnz $1b\;2:
245	inc %2\;dec %2\;bz $2f\;1: sar\t%0, 1\;dec %2 \;bnz $1b\;2:"
246	)
247
248	(define_insn "*ashrhi3_real"
249	[(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
250	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0")
251	(match_operand:QI 2 "general_operand" "P,bc,dehl")))
252	]
253	"rl78_real_insns_ok ()"
254	"@
255	sarw\t%0, %u2
256	cmp0 %2\; bz $2f\; 1: sarw\t%0, 1 \;dec %2 \;bnz $1b\;2:
257	inc %2\;dec %2\;bz $2f\;1: sarw\t%0, 1\;dec %2\;bnz $1b\;2:"
258	)
259
260	;;----------
261
262	(define_insn "*lshrqi3_real"
263	[(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
264	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0")
265	(match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
266	]
267	"rl78_real_insns_ok ()"
268	"@
269	shr\t%0, %u2
270	cmp0 %2\; bz $2f\; 1: shr\t%0, 1 \;dec %2 \;bnz $1b\;2:
271	inc %2\;dec %2\;bz $2f\;1: shr\t%0, 1\;dec %2\;bnz $1b\;2:"
272	)
273
274	(define_insn "*lshrhi3_real"
275	[(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
276	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0")
277	(match_operand:QI 2 "general_operand" "P,bc,dehl")))
278	]
279	"rl78_real_insns_ok ()"
280	"@
281	shrw\t%0, %u2
282	cmp0 %2\; bz $2f\; 1: shrw\t%0, 1 \;dec %2 \;bnz $1b\;2:
283	inc %2\;dec %2\;bz $2f\;1: shrw\t%0, 1\;dec %2\;bnz $1b\;2:"
284	)
285
286	;;---------- Branching ------------------------
287
288	(define_insn "*indirect_jump_real"
289	[(set (pc)
290	(match_operand:HI 0 "nonimmediate_operand" "A"))]
291	"rl78_real_insns_ok ()"
292	"br\t%0"
293	)
294
295	(define_insn "jump"
296	[(set (pc)
297	(label_ref (match_operand 0 "" "")))]
298	""
299	;; $rel8, $!rel16, !abs16, !!abs20
300	"br\t!!%0"
301	)
302
303	(define_insn "*call_real"
304	[(call (match_operand:HI 0 "memory_operand" "Wab,Wca")
305	(match_operand 1 "" ""))]
306	"rl78_real_insns_ok ()"
307	"@
308	call\t!!%A0
309	call\t%A0"
310	)
311
312	(define_insn "*call_value_real"
313	[(set (match_operand 0 "register_operand" "=v,v")
314	(call (match_operand:HI 1 "memory_operand" "Wab,Wca")
315	(match_operand 2 "" "")))]
316	"rl78_real_insns_ok ()"
317	"@
318	call\t!!%A1
319	call\t%A1"
320	)
321
6fcd3a13	322	(define_insn "*cbranchqi4_real_signed"
3e3d9d17 DD	323	[(set (pc) (if_then_else
	324	(match_operator 0 "rl78_cmp_operator_signed"
	325	[(match_operand:QI 1 "general_operand" "A,A,A")
	326	(match_operand:QI 2 "general_operand" "ISqi,i,v")])
	327	(label_ref (match_operand 3 "" ""))
	328	(pc)))]
	329	"rl78_real_insns_ok ()"
	330	"@
59d96342 DD	331	cmp\t%1, %2 \;xor1 CY,%1.7\;not1 CY\;sk%C0 \;br\t!!%3
	332	cmp\t%1, %2 \;xor1 CY,%1.7\;sk%C0 \;br\t!!%3
	333	cmp\t%1, %2 \;xor1 CY,%1.7\;xor1 CY,%2.7\;sk%C0 \;br\t!!%3"
3e3d9d17 DD	334	)
3e3d9d17 DD	335
85b8555e DD	336	(define_insn "*cbranchqi4_real"
	337	[(set (pc) (if_then_else
	338	(match_operator 0 "rl78_cmp_operator_real"
3e3d9d17 DD	339	[(match_operand:QI 1 "general_operand" "Wabvaxbc,a, v,bcdehl")
3e3d9d17 DD	340	(match_operand:QI 2 "general_operand" "M, irvWabWhlWh1Whb,i,a")])
85b8555e DD	341	(label_ref (match_operand 3 "" ""))
	342	(pc)))]
	343	"rl78_real_insns_ok ()"
	344	"@
59d96342 DD	345	cmp0\t%1 \;sk%C0 \;br\t!!%3
	346	cmp\t%1, %2 \;sk%C0 \;br\t!!%3
	347	cmp\t%1, %2 \;sk%C0 \;br\t!!%3
	348	cmp\t%1, %2 \;sk%C0 \;br\t!!%3"
85b8555e DD	349	)
85b8555e DD	350
6fcd3a13	351	(define_insn "*cbranchhi4_real_signed"
85b8555e	352	[(set (pc) (if_then_else
3e3d9d17 DD	353	(match_operator 0 "rl78_cmp_operator_signed"
	354	[(match_operand:HI 1 "general_operand" "A,A,A,vR")
	355	(match_operand:HI 2 "general_operand" "IShi,i,v,1")])
	356	(label_ref (match_operand 3))
85b8555e DD	357	(pc)))]
85b8555e DD	358	"rl78_real_insns_ok ()"
3e3d9d17	359	"@
59d96342 DD	360	cmpw\t%1, %2 \;xor1 CY,%Q1.7\;not1 CY\;sk%C0 \;br\t!!%3
	361	cmpw\t%1, %2 \;xor1 CY,%Q1.7\;sk%C0 \;br\t!!%3
	362	cmpw\t%1, %2 \;xor1 CY,%Q1.7\;xor1 CY,%Q2.7\;sk%C0 \;br\t!!%3
3e3d9d17 DD	363	%z0\t!!%3"
	364	)
	365
	366	(define_insn "cbranchhi4_real"
	367	[(set (pc) (if_then_else
	368	(match_operator 0 "rl78_cmp_operator_real"
	369	[(match_operand:HI 1 "general_operand" "A,vR")
	370	(match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1,1")])
	371	(label_ref (match_operand 3 "" ""))
	372	(pc)))]
	373	"rl78_real_insns_ok ()"
	374	"@
59d96342	375	cmpw\t%1, %2 \;sk%C0 \;br\t!!%3
3e3d9d17 DD	376	%z0\t!!%3"
	377	)
	378
	379	(define_insn "cbranchhi4_real_inverted"
	380	[(set (pc) (if_then_else
	381	(match_operator 0 "rl78_cmp_operator_real"
	382	[(match_operand:HI 1 "general_operand" "A")
	383	(match_operand:HI 2 "general_operand" "iBDTvWabWhlWh1")])
	384	(pc)
	385	(label_ref (match_operand 3 "" ""))))]
	386	"rl78_real_insns_ok ()"
59d96342	387	"cmpw\t%1, %2 \;sk%C0 \;br\t!!%3"
85b8555e	388	)
3e3d9d17	389
6fcd3a13	390	(define_insn "*cbranchsi4_real_lt"
3e3d9d17 DD	391	[(set (pc) (if_then_else
	392	(lt (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
	393	(const_int 0))
	394	(label_ref (match_operand 1 "" ""))
	395	(pc)))
	396	(clobber (reg:HI AX_REG))
	397	]
	398	"rl78_real_insns_ok ()"
	399	"@
	400	mov a, %E0 \;mov1 CY,a.7 \;sknc \;br\t!!%1
	401	mov1 CY,%E0.7 \;sknc \;br\t!!%1"
	402	)
	403
6fcd3a13	404	(define_insn "*cbranchsi4_real_ge"
3e3d9d17 DD	405	[(set (pc) (if_then_else
	406	(ge (match_operand:SI 0 "general_operand" "U,vWabWhlWh1")
	407	(const_int 0))
	408	(label_ref (match_operand 1 "" ""))
	409	(pc)))
	410	(clobber (reg:HI AX_REG))
	411	]
	412	"rl78_real_insns_ok ()"
	413	"@
	414	mov a, %E0 \;mov1 CY,a.7 \;skc \;br\t!!%1
	415	mov1 CY,%E0.7 \;skc \;br\t!!%1"
	416	)
	417
6fcd3a13	418	(define_insn "*cbranchsi4_real_signed"
3e3d9d17 DD	419	[(set (pc) (if_then_else
3e3d9d17 DD	420	(match_operator 0 "rl78_cmp_operator_signed"
c6f709ec NC	421	[(match_operand:SI 1 "general_operand" "vU,vU,vU,i,i")
c6f709ec NC	422	(match_operand:SI 2 "nonmemory_operand" "ISsi,i,v,S,v")])
3e3d9d17 DD	423	(label_ref (match_operand 3 "" ""))
	424	(pc)))
	425	(clobber (reg:HI AX_REG))
	426	]
	427	"rl78_real_insns_ok ()"
	428	"@
59d96342 DD	429	movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;not1 CY\; movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3
59d96342 DD	430	movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\; movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3
c6f709ec NC	431	movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3
	432	movw ax, %H1\; cmpw ax, %H2\; xor1 CY, a.7\; not1 CY\; movw ax, %h1 \;sknz\; cmpw ax, %h2 \;sk%0 \;br\t!!%3
	433	movw ax, %H1\; cmpw ax, %H2\; xor1 CY, a.7\; movw ax, %h1\; sknz\; cmpw ax, %h2\; sk%0\; br\t!!%3"
3e3d9d17 DD	434	)
3e3d9d17 DD	435
6fcd3a13	436	(define_insn "*cbranchsi4_real"
3e3d9d17 DD	437	[(set (pc) (if_then_else
	438	(match_operator 0 "rl78_cmp_operator_real"
	439	[(match_operand:SI 1 "general_operand" "vUi")
	440	(match_operand:SI 2 "general_operand" "iWhlWh1v")])
	441	(label_ref (match_operand 3 "" ""))
	442	(pc)))
	443	(clobber (reg:HI AX_REG))
	444	]
	445	"rl78_real_insns_ok ()"
59d96342	446	"movw ax,%H1 \;cmpw ax, %H2 \;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3"
3e3d9d17 DD	447	)
	448
	449	;; Peephole to match:
	450	;;
	451	;; (set (mem (sp)) (ax))
	452	;; (set (ax) (mem (sp)))
	453	;; or:
	454	;; (set (mem (plus (sp) (const)) (ax))
	455	;; (set (ax) (mem (plus (sp) (const))))
	456	;;
	457	;; which can be generated as the last instruction of the conversion
	458	;; of one virtual insn into a real insn and the first instruction of
	459	;; the conversion of the following virtual insn.
	460
	461	(define_peephole2
	462	[(set (match_operand:HI 0 "rl78_stack_based_mem")
	463	(reg:HI AX_REG))
	464	(set (reg:HI AX_REG)
	465	(match_dup 0))]
	466	""
	467	[(set (match_dup 0) (reg:HI AX_REG))]
	468	)
	469
b5ba3a9b NC	470	;; Bit test and branch insns.
	471
	472	;; NOTE: These patterns will work for bits in other places, not just A.
	473
	474	(define_insn "bf"
	475	[(set (pc)
	476	(if_then_else (eq (and (reg:QI A_REG)
	477	(match_operand 0 "immediate_operand" "n"))
	478	(const_int 0))
	479	(label_ref (match_operand 1 "" ""))
	480	(pc)))]
	481	""
	482	"bf\tA.%B0, $%1"
	483	)
	484
	485	(define_insn "bt"
	486	[(set (pc)
	487	(if_then_else (ne (and (reg:QI A_REG)
	488	(match_operand 0 "immediate_operand" "n"))
	489	(const_int 0))
	490	(label_ref (match_operand 1 "" ""))
	491	(pc)))]
	492	""
	493	"bt\tA.%B0, $%1"
	494	)
	495
	496	;; NOTE: These peepholes are fragile. They rely upon GCC generating
	497	;; a specific sequence on insns, based upon examination of test code.
	498	;; Improvements to GCC or using code other than the test code can result
	499	;; in the peephole not matching and the optimization being missed.
	500
	501	(define_peephole2
6fcd3a13 DD	502	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	503	(set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	504	(set (pc) (if_then_else (eq (match_dup 0) (const_int 0))
	505	(label_ref (match_operand 2 ""))
	506	(pc)))]
	507	"peep2_regno_dead_p (3, REGNO (operands[0]))
	508	&& exact_log2 (INTVAL (operands[1])) >= 0"
	509	[(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
	510	(label_ref (match_dup 2))
b5ba3a9b	511	(pc)))]
b5ba3a9b NC	512	)
	513
	514	(define_peephole2
6fcd3a13 DD	515	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	516	(set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	517	(set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
	518	(label_ref (match_operand 2 ""))
b5ba3a9b	519	(pc)))]
6fcd3a13 DD	520	"peep2_regno_dead_p (3, REGNO (operands[0]))
	521	&& exact_log2 (INTVAL (operands[1])) >= 0"
	522	[(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
	523	(label_ref (match_dup 2))
	524	(pc)))]
	525	)
	526
	527	;; Eliminate needless register copies.
	528	(define_peephole2
	529	[(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand"))
	530	(set (match_operand:HI 2 "register_operand") (match_dup 0))]
	531	"peep2_regno_dead_p (2, REGNO (operands[0]))
	532	&& (REGNO (operands[1]) < 8 \|\| REGNO (operands[2]) < 8)"
	533	[(set (match_dup 2) (match_dup 1))]
	534	)
	535
	536	;; Eliminate needless register copying when performing bit manipulations.
	537	(define_peephole2
	538	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	539	(set (match_dup 0) (ior:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	540	(set (reg:QI A_REG) (match_dup 0))]
	541	"peep2_regno_dead_p (3, REGNO (operands[0]))"
	542	[(set (reg:QI A_REG) (ior:QI (reg:QI A_REG) (match_dup 1)))]
	543	)
	544
	545	(define_peephole2
	546	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	547	(set (match_dup 0) (xor:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	548	(set (reg:QI A_REG) (match_dup 0))]
	549	"peep2_regno_dead_p (3, REGNO (operands[0]))"
	550	[(set (reg:QI A_REG) (xor:QI (reg:QI A_REG) (match_dup 1)))]
	551	)
	552
	553	(define_peephole2
	554	[(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
	555	(set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
	556	(set (reg:QI A_REG) (match_dup 0))]
	557	"peep2_regno_dead_p (3, REGNO (operands[0]))"
	558	[(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))]
b5ba3a9b NC	559	)
b5ba3a9b NC	560
c6f709ec NC	561	(define_insn "*negandhi3_real"
	562	[(set (match_operand:HI 0 "register_operand" "=A")
	563	(and:HI (neg:HI (match_operand:HI 1 "register_operand" "0"))
	564	(match_operand:HI 2 "immediate_operand" "n")))
	565	]
	566	"rl78_real_insns_ok ()"
	567	"xor a, #0xff @ xch a, x @ xor a, #0xff @ xch a, x @ addw ax, #1 @ and a, %Q2 @ xch a, x @ and a, %q2 @ xch a, x"
	568	)