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2c9c2489 | 1 | /* Definitions of target machine for GNU compiler, for the pdp-11 |
cf011243 | 2 | Copyright (C) 1994, 1995, 1996, 1998, 1999, 2000, 2001 |
2398fb2a | 3 | Free Software Foundation, Inc. |
2c9c2489 RK |
4 | Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
2f9b4377 | 10 | the Free Software Foundation; either version 2, or (at your option) |
2c9c2489 RK |
11 | any later version. |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
b0f95773 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
2c9c2489 RK |
22 | |
23 | ||
ddd5a7c1 | 24 | /* check whether load_fpu_reg or not */ |
2c9c2489 RK |
25 | #define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11) |
26 | #define NO_LOAD_FPU_REG_P(x) ((x)==12 || (x)==13) | |
27 | #define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x)) | |
28 | #define CPU_REG_P(x) ((x)<8) | |
29 | ||
30 | /* Names to predefine in the preprocessor for this target machine. */ | |
31 | ||
32 | #define CPP_PREDEFINES "-Dpdp11" | |
33 | ||
34 | /* Print subsidiary information on the compiler version in use. */ | |
35 | #define TARGET_VERSION fprintf (stderr, " (pdp11)"); | |
36 | ||
37 | ||
38 | /* Generate DBX debugging information. */ | |
39 | ||
40 | /* #define DBX_DEBUGGING_INFO */ | |
41 | ||
42 | /* Run-time compilation parameters selecting different hardware subsets. | |
43 | */ | |
44 | ||
45 | extern int target_flags; | |
46 | ||
47 | /* Macro to define tables used to set the flags. | |
ed03c6cd JM |
48 | This is a list in braces of triplets in braces, |
49 | each triplet being { "NAME", VALUE, DOC } | |
50 | where VALUE is the bits to set or minus the bits to clear and DOC | |
51 | is the documentation for --help (NULL if intentionally undocumented). | |
2c9c2489 RK |
52 | An empty string NAME is used to identify the default VALUE. */ |
53 | ||
54 | #define TARGET_SWITCHES \ | |
047142d3 PT |
55 | { { "fpu", 1, N_("Use hardware floating point") }, \ |
56 | { "soft-float", -1, N_("Do not use hardware floating point") }, \ | |
57 | /* return float result in ac0 */ \ | |
58 | { "ac0", 2, N_("Return floating point results in ac0") }, \ | |
59 | { "no-ac0", -2, N_("Return floating point results in memory") }, \ | |
60 | /* is 11/40 */ \ | |
61 | { "40", 4, N_("Generate code for an 11/40") }, \ | |
62 | { "no-40", -4, "" }, \ | |
63 | /* is 11/45 */ \ | |
64 | { "45", 8, N_("Generate code for an 11/45") }, \ | |
65 | { "no-45", -8, "" }, \ | |
66 | /* is 11/10 */ \ | |
67 | { "10", -12, N_("Generate code for an 11/10") }, \ | |
68 | /* use movstrhi for bcopy */ \ | |
69 | { "bcopy", 16, NULL }, \ | |
70 | { "bcopy-builtin", -16, NULL }, \ | |
71 | /* use 32 bit for int */ \ | |
72 | { "int32", 32, N_("Use 32 bit int") }, \ | |
73 | { "no-int16", 32, N_("Use 32 bit int") }, \ | |
74 | { "int16", -32, N_("Use 16 bit int") }, \ | |
75 | { "no-int32", -32, N_("Use 16 bit int") }, \ | |
76 | /* use 32 bit for float */ \ | |
77 | { "float32", 64, N_("Use 32 bit float") }, \ | |
78 | { "no-float64", 64, N_("Use 32 bit float") }, \ | |
79 | { "float64", -64, N_("Use 64 bit float") }, \ | |
80 | { "no-float32", -64, N_("Use 64 bit float") }, \ | |
2c9c2489 | 81 | /* allow abshi pattern? - can trigger "optimizations" which make code SLOW! */\ |
047142d3 PT |
82 | { "abshi", 128, NULL }, \ |
83 | { "no-abshi", -128, NULL }, \ | |
2c9c2489 | 84 | /* is branching expensive - on a PDP, it's actually really cheap */ \ |
ddd5a7c1 | 85 | /* this is just to play around and check what code gcc generates */ \ |
047142d3 PT |
86 | { "branch-expensive", 256, NULL }, \ |
87 | { "branch-cheap", -256, NULL }, \ | |
88 | /* split instruction and data memory? */ \ | |
89 | { "split", 1024, N_("Target has split I&D") }, \ | |
90 | { "no-split", -1024, N_("Target does not have split I&D") }, \ | |
91 | /* UNIX assembler syntax? */ \ | |
92 | { "unix-asm", 2048, N_("Use UNIX assembler syntax") }, \ | |
93 | { "dec-asm", -2048, N_("Use DEC assembler syntax") }, \ | |
2c9c2489 | 94 | /* default */ \ |
ed03c6cd | 95 | { "", TARGET_DEFAULT, NULL} \ |
2c9c2489 RK |
96 | } |
97 | ||
d14ff9bd | 98 | #define TARGET_DEFAULT (1 | 8 | 128 | TARGET_UNIX_ASM_DEFAULT) |
2c9c2489 RK |
99 | |
100 | #define TARGET_FPU (target_flags & 1) | |
101 | #define TARGET_SOFT_FLOAT (!TARGET_FPU) | |
102 | ||
103 | #define TARGET_AC0 ((target_flags & 2) && TARGET_FPU) | |
104 | #define TARGET_NO_AC0 (! TARGET_AC0) | |
105 | ||
106 | #define TARGET_45 (target_flags & 8) | |
9f643ff8 | 107 | #define TARGET_40_PLUS ((target_flags & 4) || (target_flags & 8)) |
2c9c2489 RK |
108 | #define TARGET_10 (! TARGET_40_PLUS) |
109 | ||
110 | #define TARGET_BCOPY_BUILTIN (! (target_flags & 16)) | |
111 | ||
112 | #define TARGET_INT16 (! TARGET_INT32) | |
113 | #define TARGET_INT32 (target_flags & 32) | |
114 | ||
115 | #define TARGET_FLOAT32 (target_flags & 64) | |
116 | #define TARGET_FLOAT64 (! TARGET_FLOAT32) | |
117 | ||
118 | #define TARGET_ABSHI_BUILTIN (target_flags & 128) | |
119 | ||
120 | #define TARGET_BRANCH_EXPENSIVE (target_flags & 256) | |
121 | #define TARGET_BRANCH_CHEAP (!TARGET_BRANCH_EXPENSIVE) | |
122 | ||
fea1b650 RK |
123 | #define TARGET_SPLIT (target_flags & 1024) |
124 | #define TARGET_NOSPLIT (! TARGET_SPLIT) | |
d14ff9bd JM |
125 | |
126 | #define TARGET_UNIX_ASM (target_flags & 2048) | |
127 | #define TARGET_UNIX_ASM_DEFAULT 0 | |
128 | ||
af36a4d2 JM |
129 | #define ASSEMBLER_DIALECT (TARGET_UNIX_ASM ? 1 : 0) |
130 | ||
2c9c2489 RK |
131 | \f |
132 | ||
133 | /* TYPE SIZES */ | |
134 | #define CHAR_TYPE_SIZE 8 | |
135 | #define SHORT_TYPE_SIZE 16 | |
136 | #define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32) | |
137 | #define LONG_TYPE_SIZE 32 | |
138 | #define LONG_LONG_TYPE_SIZE 64 | |
139 | ||
140 | /* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit | |
141 | of saving core for huge arrays - the definitions are | |
142 | already in md - but floats can never reside in | |
143 | an FPU register - we keep the FPU in double float mode | |
144 | all the time !! */ | |
145 | #define FLOAT_TYPE_SIZE (TARGET_FLOAT32 ? 32 : 64) | |
146 | #define DOUBLE_TYPE_SIZE 64 | |
147 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
148 | ||
149 | /* machine types from ansi */ | |
150 | #define SIZE_TYPE "unsigned int" /* definition of size_t */ | |
2c9c2489 RK |
151 | #define WCHAR_TYPE "int" /* or long int???? */ |
152 | #define WCHAR_TYPE_SIZE 16 | |
153 | ||
154 | #define PTRDIFF_TYPE "int" | |
155 | ||
156 | /* target machine storage layout */ | |
157 | ||
158 | /* Define this if most significant bit is lowest numbered | |
159 | in instructions that operate on numbered bit-fields. */ | |
160 | #define BITS_BIG_ENDIAN 0 | |
161 | ||
162 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
163 | #define BYTES_BIG_ENDIAN 0 | |
164 | ||
165 | /* Define this if most significant word of a multiword number is numbered. */ | |
166 | #define WORDS_BIG_ENDIAN 1 | |
167 | ||
ddd5a7c1 | 168 | /* number of bits in an addressable storage unit */ |
2c9c2489 RK |
169 | #define BITS_PER_UNIT 8 |
170 | ||
171 | /* Width in bits of a "word", which is the contents of a machine register. | |
172 | Note that this is not necessarily the width of data type `int'; | |
173 | if using 16-bit ints on a 68000, this would still be 32. | |
174 | But on a machine with 16-bit registers, this would be 16. */ | |
175 | /* This is a machine with 16-bit registers */ | |
176 | #define BITS_PER_WORD 16 | |
177 | ||
178 | /* Width of a word, in units (bytes). | |
179 | ||
180 | UNITS OR BYTES - seems like units */ | |
181 | #define UNITS_PER_WORD 2 | |
182 | ||
183 | /* Maximum sized of reasonable data type | |
184 | DImode or Dfmode ...*/ | |
185 | #define MAX_FIXED_MODE_SIZE 64 | |
186 | ||
187 | /* Width in bits of a pointer. | |
188 | See also the macro `Pmode' defined below. */ | |
189 | #define POINTER_SIZE 16 | |
190 | ||
191 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ | |
192 | #define POINTER_BOUNDARY 16 | |
193 | ||
194 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
195 | #define PARM_BOUNDARY 16 | |
196 | ||
53e2d849 LB |
197 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
198 | #define STACK_BOUNDARY 16 | |
199 | ||
2c9c2489 RK |
200 | /* Allocation boundary (in *bits*) for the code of a function. */ |
201 | #define FUNCTION_BOUNDARY 16 | |
202 | ||
203 | /* Alignment of field after `int : 0' in a structure. */ | |
204 | #define EMPTY_FIELD_BOUNDARY 16 | |
205 | ||
206 | /* No data type wants to be aligned rounder than this. */ | |
207 | #define BIGGEST_ALIGNMENT 16 | |
208 | ||
209 | /* Define this if move instructions will actually fail to work | |
210 | when given unaligned data. */ | |
211 | #define STRICT_ALIGNMENT 1 | |
212 | \f | |
213 | /* Standard register usage. */ | |
214 | ||
215 | /* Number of actual hardware registers. | |
216 | The hardware registers are assigned numbers for the compiler | |
217 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
218 | All registers that the compiler knows about must be given numbers, | |
219 | even those that are not normally considered general registers. | |
220 | ||
221 | we have 8 integer registers, plus 6 float | |
222 | (don't use scratch float !) */ | |
223 | ||
224 | #define FIRST_PSEUDO_REGISTER 14 | |
225 | ||
226 | /* 1 for registers that have pervasive standard uses | |
227 | and are not available for the register allocator. | |
228 | ||
229 | On the pdp, these are: | |
230 | Reg 7 = pc; | |
231 | reg 6 = sp; | |
232 | reg 5 = fp; not necessarily! | |
233 | */ | |
234 | ||
235 | /* don't let them touch fp regs for the time being !*/ | |
236 | ||
237 | #define FIXED_REGISTERS \ | |
238 | {0, 0, 0, 0, 0, 0, 1, 1, \ | |
239 | 0, 0, 0, 0, 0, 0 } | |
240 | ||
241 | ||
242 | ||
243 | /* 1 for registers not available across function calls. | |
244 | These must include the FIXED_REGISTERS and also any | |
245 | registers that can be used without being saved. | |
246 | The latter must include the registers where values are returned | |
247 | and the register where structure-value addresses are passed. | |
248 | Aside from that, you can include as many other registers as you like. */ | |
249 | ||
250 | /* don't know about fp */ | |
251 | #define CALL_USED_REGISTERS \ | |
252 | {1, 1, 0, 0, 0, 0, 1, 1, \ | |
253 | 0, 0, 0, 0, 0, 0 } | |
254 | ||
255 | ||
256 | /* Make sure everything's fine if we *don't* have an FPU. | |
257 | This assumes that putting a register in fixed_regs will keep the | |
258 | compiler's mitts completely off it. We don't bother to zero it out | |
af36a4d2 JM |
259 | of register classes. Also fix incompatible register naming with |
260 | the UNIX assembler. | |
2c9c2489 RK |
261 | */ |
262 | #define CONDITIONAL_REGISTER_USAGE \ | |
263 | { \ | |
264 | int i; \ | |
265 | HARD_REG_SET x; \ | |
266 | if (!TARGET_FPU) \ | |
267 | { \ | |
268 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); \ | |
269 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
270 | if (TEST_HARD_REG_BIT (x, i)) \ | |
271 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
272 | } \ | |
273 | \ | |
274 | if (TARGET_AC0) \ | |
275 | call_used_regs[8] = 1; \ | |
af36a4d2 JM |
276 | if (TARGET_UNIX_ASM) \ |
277 | { \ | |
278 | /* Change names of FPU registers for the UNIX assembler. */ \ | |
279 | reg_names[8] = "fr0"; \ | |
280 | reg_names[9] = "fr1"; \ | |
281 | reg_names[10] = "fr2"; \ | |
282 | reg_names[11] = "fr3"; \ | |
283 | reg_names[12] = "fr4"; \ | |
284 | reg_names[13] = "fr5"; \ | |
285 | } \ | |
2c9c2489 RK |
286 | } |
287 | ||
288 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
289 | to hold something of mode MODE. | |
290 | This is ordinarily the length in words of a value of mode MODE | |
291 | but can be less for certain modes in special long registers. | |
292 | */ | |
293 | ||
294 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
295 | ((REGNO < 8)? \ | |
296 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \ | |
297 | :1) | |
298 | ||
299 | ||
300 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
301 | On the pdp, the cpu registers can hold any mode - check alignment | |
302 | ||
303 | FPU can only hold DF - simplifies life! | |
304 | */ | |
305 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
09b893bb | 306 | (((REGNO) < 8)? \ |
2c9c2489 | 307 | ((GET_MODE_BITSIZE(MODE) <= 16) \ |
09b893bb | 308 | || (GET_MODE_BITSIZE(MODE) == 32 && !((REGNO) & 1))) \ |
2c9c2489 RK |
309 | :(MODE) == DFmode) |
310 | ||
311 | ||
312 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
313 | when one has mode MODE1 and one has mode MODE2. | |
314 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
315 | for any hard reg, then this must be 0 for correct output. */ | |
316 | #define MODES_TIEABLE_P(MODE1, MODE2) 0 | |
317 | ||
318 | /* Specify the registers used for certain standard purposes. | |
319 | The values of these macros are register numbers. */ | |
320 | ||
321 | /* the pdp11 pc overloaded on a register that the compiler knows about. */ | |
322 | #define PC_REGNUM 7 | |
323 | ||
324 | /* Register to use for pushing function arguments. */ | |
325 | #define STACK_POINTER_REGNUM 6 | |
326 | ||
327 | /* Base register for access to local variables of the function. */ | |
328 | #define FRAME_POINTER_REGNUM 5 | |
329 | ||
330 | /* Value should be nonzero if functions must have frame pointers. | |
331 | Zero means the frame pointer need not be set up (and parms | |
332 | may be accessed via the stack pointer) in functions that seem suitable. | |
333 | This is computed in `reload', in reload1.c. | |
334 | */ | |
335 | ||
336 | #define FRAME_POINTER_REQUIRED 0 | |
337 | ||
338 | /* Base register for access to arguments of the function. */ | |
339 | #define ARG_POINTER_REGNUM 5 | |
340 | ||
341 | /* Register in which static-chain is passed to a function. */ | |
342 | /* ??? - i don't want to give up a reg for this! */ | |
343 | #define STATIC_CHAIN_REGNUM 4 | |
344 | ||
345 | /* Register in which address to store a structure value | |
346 | is passed to a function. | |
347 | let's make it an invisible first argument!!! */ | |
348 | ||
349 | #define STRUCT_VALUE 0 | |
350 | ||
351 | \f | |
352 | /* Define the classes of registers for register constraints in the | |
353 | machine description. Also define ranges of constants. | |
354 | ||
355 | One of the classes must always be named ALL_REGS and include all hard regs. | |
356 | If there is more than one class, another class must be named NO_REGS | |
357 | and contain no registers. | |
358 | ||
359 | The name GENERAL_REGS must be the name of a class (or an alias for | |
360 | another name such as ALL_REGS). This is the class of registers | |
361 | that is allowed by "g" or "r" in a register constraint. | |
362 | Also, registers outside this class are allocated only when | |
363 | instructions express preferences for them. | |
364 | ||
365 | The classes must be numbered in nondecreasing order; that is, | |
366 | a larger-numbered class must never be contained completely | |
367 | in a smaller-numbered class. | |
368 | ||
369 | For any two classes, it is very desirable that there be another | |
370 | class that represents their union. */ | |
371 | ||
372 | /* The pdp has a couple of classes: | |
373 | ||
374 | MUL_REGS are used for odd numbered regs, to use in 16 bit multiplication | |
375 | (even numbered do 32 bit multiply) | |
376 | LMUL_REGS long multiply registers (even numbered regs ) | |
377 | (don't need them, all 32 bit regs are even numbered!) | |
378 | GENERAL_REGS is all cpu | |
379 | LOAD_FPU_REGS is the first four cpu regs, they are easier to load | |
380 | NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them | |
381 | FPU_REGS is all fpu regs | |
382 | */ | |
383 | ||
384 | enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES }; | |
385 | ||
386 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
387 | ||
388 | /* have to allow this till cmpsi/tstsi are fixed in a better way !! */ | |
2922fe9e | 389 | #define SMALL_REGISTER_CLASSES 1 |
2c9c2489 RK |
390 | |
391 | /* Since GENERAL_REGS is the same class as ALL_REGS, | |
392 | don't give it a different class number; just make it an alias. */ | |
393 | ||
394 | /* #define GENERAL_REGS ALL_REGS */ | |
395 | ||
396 | /* Give names of register classes as strings for dump file. */ | |
397 | ||
398 | #define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" } | |
399 | ||
400 | /* Define which registers fit in which classes. | |
401 | This is an initializer for a vector of HARD_REG_SET | |
402 | of length N_REG_CLASSES. */ | |
403 | ||
ed03c6cd | 404 | #define REG_CLASS_CONTENTS {{0}, {0x00aa}, {0x00ff}, {0x0f00}, {0x3000}, {0x3f00}, {0x3fff}} |
2c9c2489 RK |
405 | |
406 | /* The same information, inverted: | |
407 | Return the class number of the smallest class containing | |
408 | reg number REGNO. This could be a conditional expression | |
409 | or could index an array. */ | |
410 | ||
411 | #define REGNO_REG_CLASS(REGNO) \ | |
09b893bb | 412 | ((REGNO)>=8?((REGNO)<=11?LOAD_FPU_REGS:NO_LOAD_FPU_REGS):(((REGNO)&1)?MUL_REGS:GENERAL_REGS)) |
2c9c2489 RK |
413 | |
414 | ||
415 | /* The class value for index registers, and the one for base regs. */ | |
416 | #define INDEX_REG_CLASS GENERAL_REGS | |
417 | #define BASE_REG_CLASS GENERAL_REGS | |
418 | ||
419 | /* Get reg_class from a letter such as appears in the machine description. */ | |
420 | ||
421 | #define REG_CLASS_FROM_LETTER(C) \ | |
422 | ((C) == 'f' ? FPU_REGS : \ | |
423 | ((C) == 'd' ? MUL_REGS : \ | |
424 | ((C) == 'a' ? LOAD_FPU_REGS : NO_REGS))) | |
425 | ||
426 | ||
427 | /* The letters I, J, K, L and M in a register constraint string | |
428 | can be used to stand for particular ranges of immediate operands. | |
429 | This macro defines what the ranges are. | |
430 | C is the letter, and VALUE is a constant value. | |
431 | Return 1 if VALUE is in the range specified by C. | |
432 | ||
433 | I bits 31-16 0000 | |
434 | J bits 15-00 0000 | |
435 | K completely random 32 bit | |
436 | L,M,N -1,1,0 respectively | |
437 | O where doing shifts in sequence is faster than | |
438 | one big shift | |
439 | */ | |
440 | ||
441 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
442 | ((C) == 'I' ? ((VALUE) & 0xffff0000) == 0 \ | |
443 | : (C) == 'J' ? ((VALUE) & 0x0000ffff) == 0 \ | |
444 | : (C) == 'K' ? (((VALUE) & 0xffff0000) != 0 \ | |
445 | && ((VALUE) & 0x0000ffff) != 0) \ | |
446 | : (C) == 'L' ? ((VALUE) == 1) \ | |
447 | : (C) == 'M' ? ((VALUE) == -1) \ | |
448 | : (C) == 'N' ? ((VALUE) == 0) \ | |
449 | : (C) == 'O' ? (abs(VALUE) >1 && abs(VALUE) <= 4) \ | |
450 | : 0) | |
451 | ||
452 | /* Similar, but for floating constants, and defining letters G and H. | |
453 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
454 | ||
455 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
456 | ((C) == 'G' && XINT (VALUE, 0) == 0 && XINT (VALUE, 1) == 0) | |
457 | ||
458 | ||
459 | /* Letters in the range `Q' through `U' may be defined in a | |
460 | machine-dependent fashion to stand for arbitrary operand types. | |
461 | The machine description macro `EXTRA_CONSTRAINT' is passed the | |
462 | operand as its first argument and the constraint letter as its | |
463 | second operand. | |
464 | ||
ddd5a7c1 RK |
465 | `Q' is for memory references using take more than 1 instruction. |
466 | `R' is for memory references which take 1 word for the instruction. */ | |
2c9c2489 RK |
467 | |
468 | #define EXTRA_CONSTRAINT(OP,CODE) \ | |
469 | ((GET_CODE (OP) != MEM) ? 0 \ | |
470 | : !legitimate_address_p (GET_MODE (OP), XEXP (OP, 0)) ? 0 \ | |
471 | : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \ | |
472 | : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \ | |
473 | : 0) | |
474 | ||
475 | /* Given an rtx X being reloaded into a reg required to be | |
476 | in class CLASS, return the class of reg to actually use. | |
477 | In general this is just CLASS; but on some machines | |
478 | in some cases it is preferable to use a more restrictive class. | |
479 | ||
480 | loading is easier into LOAD_FPU_REGS than FPU_REGS! */ | |
481 | ||
482 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
483 | (((CLASS) != FPU_REGS)?(CLASS):LOAD_FPU_REGS) | |
484 | ||
485 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,x) \ | |
486 | (((CLASS) == NO_LOAD_FPU_REGS && !(REG_P(x) && LOAD_FPU_REG_P(REGNO(x))))?LOAD_FPU_REGS:NO_REGS) | |
487 | ||
488 | /* Return the maximum number of consecutive registers | |
489 | needed to represent mode MODE in a register of class CLASS. */ | |
490 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
491 | ((CLASS == GENERAL_REGS || CLASS == MUL_REGS)? \ | |
492 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \ | |
493 | 1 \ | |
494 | ) | |
495 | ||
496 | \f | |
497 | /* Stack layout; function entry, exit and calling. */ | |
498 | ||
499 | /* Define this if pushing a word on the stack | |
500 | makes the stack pointer a smaller address. */ | |
501 | #define STACK_GROWS_DOWNWARD | |
502 | ||
503 | /* Define this if the nominal address of the stack frame | |
504 | is at the high-address end of the local variables; | |
505 | that is, each additional local variable allocated | |
506 | goes at a more negative offset in the frame. | |
507 | */ | |
508 | #define FRAME_GROWS_DOWNWARD | |
509 | ||
510 | /* Offset within stack frame to start allocating local variables at. | |
511 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
512 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
513 | of the first local allocated. */ | |
514 | #define STARTING_FRAME_OFFSET 0 | |
515 | ||
516 | /* If we generate an insn to push BYTES bytes, | |
517 | this says how many the stack pointer really advances by. | |
518 | On the pdp11, the stack is on an even boundary */ | |
519 | #define PUSH_ROUNDING(BYTES) ((BYTES + 1) & ~1) | |
520 | ||
521 | /* current_first_parm_offset stores the # of registers pushed on the | |
522 | stack */ | |
523 | extern int current_first_parm_offset; | |
524 | ||
525 | /* Offset of first parameter from the argument pointer register value. | |
526 | For the pdp11, this is non-zero to account for the return address. | |
527 | 1 - return address | |
528 | 2 - frame pointer (always saved, even when not used!!!!) | |
529 | -- chnage some day !!!:q! | |
530 | ||
531 | */ | |
532 | #define FIRST_PARM_OFFSET(FNDECL) 4 | |
533 | ||
534 | /* Value is 1 if returning from a function call automatically | |
535 | pops the arguments described by the number-of-args field in the call. | |
8b109b37 | 536 | FUNDECL is the declaration node of the function (as a tree), |
2c9c2489 RK |
537 | FUNTYPE is the data type of the function (as a tree), |
538 | or for a library call it is an identifier node for the subroutine name. */ | |
539 | ||
8b109b37 | 540 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
2c9c2489 RK |
541 | |
542 | /* Define how to find the value returned by a function. | |
543 | VALTYPE is the data type of the value (as a tree). | |
544 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
545 | otherwise, FUNC is 0. */ | |
546 | #define BASE_RETURN_VALUE_REG(MODE) \ | |
547 | ((MODE) == DFmode ? 8 : 0) | |
548 | ||
549 | /* On the pdp11 the value is found in R0 (or ac0??? | |
550 | not without FPU!!!! ) */ | |
551 | ||
552 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
c5c76735 | 553 | gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE))) |
2c9c2489 RK |
554 | |
555 | /* and the called function leaves it in the first register. | |
556 | Difference only on machines with register windows. */ | |
557 | ||
558 | #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ | |
c5c76735 | 559 | gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE))) |
2c9c2489 RK |
560 | |
561 | /* Define how to find the value returned by a library function | |
562 | assuming the value has mode MODE. */ | |
563 | ||
c5c76735 | 564 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, BASE_RETURN_VALUE_REG(MODE)) |
2c9c2489 RK |
565 | |
566 | /* 1 if N is a possible register number for a function value | |
567 | as seen by the caller. | |
568 | On the pdp, the first "output" reg is the only register thus used. | |
569 | ||
570 | maybe ac0 ? - as option someday! */ | |
571 | ||
572 | #define FUNCTION_VALUE_REGNO_P(N) (((N) == 0) || (TARGET_AC0 && (N) == 8)) | |
573 | ||
574 | /* should probably return DImode and DFmode in memory,lest | |
575 | we fill up all regs! | |
576 | ||
abc95ed3 | 577 | have to, else we crash - exception: maybe return result in |
2c9c2489 RK |
578 | ac0 if DFmode and FPU present - compatibility problem with |
579 | libraries for non-floating point ... | |
580 | */ | |
581 | ||
582 | #define RETURN_IN_MEMORY(TYPE) \ | |
583 | (TYPE_MODE(TYPE) == DImode || (TYPE_MODE(TYPE) == DFmode && ! TARGET_AC0)) | |
584 | ||
585 | ||
586 | /* 1 if N is a possible register number for function argument passing. | |
587 | - not used on pdp */ | |
588 | ||
589 | #define FUNCTION_ARG_REGNO_P(N) 0 | |
590 | \f | |
591 | /* Define a data type for recording info about an argument list | |
592 | during the scan of that argument list. This data type should | |
593 | hold all necessary information about the function itself | |
594 | and about the args processed so far, enough to enable macros | |
595 | such as FUNCTION_ARG to determine where the next arg should go. | |
596 | ||
597 | */ | |
598 | ||
599 | #define CUMULATIVE_ARGS int | |
600 | ||
601 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
602 | for a call to a function whose data type is FNTYPE. | |
603 | For a library call, FNTYPE is 0. | |
604 | ||
605 | ...., the offset normally starts at 0, but starts at 1 word | |
606 | when the function gets a structure-value-address as an | |
607 | invisible first argument. */ | |
608 | ||
2c7ee1a6 | 609 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
2c9c2489 RK |
610 | ((CUM) = 0) |
611 | ||
612 | /* Update the data in CUM to advance over an argument | |
613 | of mode MODE and data type TYPE. | |
614 | (TYPE is null for libcalls where that information may not be available.) | |
615 | ||
616 | */ | |
617 | ||
618 | ||
619 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
620 | ((CUM) += ((MODE) != BLKmode \ | |
621 | ? (GET_MODE_SIZE (MODE)) \ | |
622 | : (int_size_in_bytes (TYPE)))) | |
623 | ||
624 | /* Determine where to put an argument to a function. | |
625 | Value is zero to push the argument on the stack, | |
626 | or a hard register in which to store the argument. | |
627 | ||
628 | MODE is the argument's machine mode. | |
629 | TYPE is the data type of the argument (as a tree). | |
630 | This is null for libcalls where that information may | |
631 | not be available. | |
632 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
633 | the preceding args and about the function being called. | |
634 | NAMED is nonzero if this argument is a named parameter | |
635 | (otherwise it is an extra parameter matching an ellipsis). */ | |
636 | ||
637 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 | |
638 | ||
639 | /* Define where a function finds its arguments. | |
640 | This would be different from FUNCTION_ARG if we had register windows. */ | |
641 | /* | |
642 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
643 | FUNCTION_ARG (CUM, MODE, TYPE, NAMED) | |
644 | */ | |
645 | ||
646 | /* For an arg passed partly in registers and partly in memory, | |
647 | this is the number of registers used. | |
648 | For args passed entirely in registers or entirely in memory, zero. */ | |
649 | ||
650 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 | |
651 | ||
2c9c2489 RK |
652 | /* Output assembler code to FILE to increment profiler label # LABELNO |
653 | for profiling a function entry. */ | |
654 | ||
655 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
656 | abort (); | |
657 | ||
658 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
659 | the stack pointer does not matter. The value is tested only in | |
660 | functions that have frame pointers. | |
661 | No definition is equivalent to always zero. */ | |
662 | ||
663 | extern int may_call_alloca; | |
2c9c2489 RK |
664 | |
665 | #define EXIT_IGNORE_STACK 1 | |
666 | ||
2c9c2489 RK |
667 | #define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) \ |
668 | { \ | |
669 | int offset, regno; \ | |
670 | offset = get_frame_size(); \ | |
671 | for (regno = 0; regno < 8; regno++) \ | |
672 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
673 | offset += 2; \ | |
674 | for (regno = 8; regno < 14; regno++) \ | |
675 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
676 | offset += 8; \ | |
677 | /* offset -= 2; no fp on stack frame */ \ | |
678 | (DEPTH_VAR) = offset; \ | |
679 | } | |
680 | ||
681 | \f | |
682 | /* Addressing modes, and classification of registers for them. */ | |
683 | ||
940da324 JL |
684 | #define HAVE_POST_INCREMENT 1 |
685 | /* #define HAVE_POST_DECREMENT 0 */ | |
2c9c2489 | 686 | |
940da324 JL |
687 | #define HAVE_PRE_DECREMENT 1 |
688 | /* #define HAVE_PRE_INCREMENT 0 */ | |
2c9c2489 RK |
689 | |
690 | /* Macros to check register numbers against specific register classes. */ | |
691 | ||
692 | /* These assume that REGNO is a hard or pseudo reg number. | |
693 | They give nonzero only if REGNO is a hard reg of the suitable class | |
694 | or a pseudo reg currently allocated to a suitable hard reg. | |
695 | Since they use reg_renumber, they are safe only once reg_renumber | |
696 | has been allocated, which happens in local-alloc.c. */ | |
697 | ||
698 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
699 | ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) | |
700 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
701 | ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) | |
702 | ||
703 | /* Now macros that check whether X is a register and also, | |
704 | strictly, whether it is in a specified class. | |
705 | */ | |
706 | ||
707 | ||
708 | \f | |
709 | /* Maximum number of registers that can appear in a valid memory address. */ | |
710 | ||
711 | #define MAX_REGS_PER_ADDRESS 2 | |
712 | ||
713 | /* Recognize any constant value that is a valid address. */ | |
714 | ||
715 | #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X) | |
716 | ||
717 | /* Nonzero if the constant value X is a legitimate general operand. | |
718 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
719 | ||
720 | #define LEGITIMATE_CONSTANT_P(X) (1) | |
721 | ||
722 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
723 | and check its validity for a certain class. | |
724 | We have two alternate definitions for each of them. | |
725 | The usual definition accepts all pseudo regs; the other rejects | |
726 | them unless they have been allocated suitable hard regs. | |
727 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
728 | ||
729 | Most source files want to accept pseudo regs in the hope that | |
730 | they will get allocated to the class that the insn wants them to be in. | |
731 | Source files for reload pass need to be strict. | |
732 | After reload, it makes no difference, since pseudo regs have | |
733 | been eliminated by then. */ | |
734 | ||
735 | #ifndef REG_OK_STRICT | |
736 | ||
737 | /* Nonzero if X is a hard reg that can be used as an index | |
738 | or if it is a pseudo reg. */ | |
739 | #define REG_OK_FOR_INDEX_P(X) (1) | |
740 | /* Nonzero if X is a hard reg that can be used as a base reg | |
741 | or if it is a pseudo reg. */ | |
742 | #define REG_OK_FOR_BASE_P(X) (1) | |
743 | ||
744 | #else | |
745 | ||
746 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
747 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
748 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
749 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
750 | ||
751 | #endif | |
752 | \f | |
753 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
754 | that is a valid memory address for an instruction. | |
755 | The MODE argument is the machine mode for the MEM expression | |
756 | that wants to use this address. | |
757 | ||
758 | */ | |
759 | ||
760 | #define GO_IF_LEGITIMATE_ADDRESS(mode, operand, ADDR) \ | |
761 | { \ | |
762 | rtx xfoob; \ | |
763 | \ | |
764 | /* accept (R0) */ \ | |
765 | if (GET_CODE (operand) == REG \ | |
766 | && REG_OK_FOR_BASE_P(operand)) \ | |
767 | goto ADDR; \ | |
768 | \ | |
769 | /* accept @#address */ \ | |
770 | if (CONSTANT_ADDRESS_P (operand)) \ | |
771 | goto ADDR; \ | |
772 | \ | |
773 | /* accept X(R0) */ \ | |
774 | if (GET_CODE (operand) == PLUS \ | |
775 | && GET_CODE (XEXP (operand, 0)) == REG \ | |
776 | && REG_OK_FOR_BASE_P (XEXP (operand, 0)) \ | |
777 | && CONSTANT_ADDRESS_P (XEXP (operand, 1))) \ | |
778 | goto ADDR; \ | |
779 | \ | |
780 | /* accept -(R0) */ \ | |
781 | if (GET_CODE (operand) == PRE_DEC \ | |
782 | && GET_CODE (XEXP (operand, 0)) == REG \ | |
783 | && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \ | |
784 | goto ADDR; \ | |
785 | \ | |
786 | /* accept (R0)+ */ \ | |
787 | if (GET_CODE (operand) == POST_INC \ | |
788 | && GET_CODE (XEXP (operand, 0)) == REG \ | |
789 | && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \ | |
790 | goto ADDR; \ | |
791 | \ | |
792 | /* handle another level of indirection ! */ \ | |
793 | if (GET_CODE(operand) != MEM) \ | |
794 | goto fail; \ | |
795 | \ | |
796 | xfoob = XEXP (operand, 0); \ | |
797 | \ | |
798 | /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently */ \ | |
799 | /* also forbidden for float, because we have to handle this */ \ | |
800 | /* in output_move_double and/or output_move_quad() - we could */ \ | |
801 | /* do it, but currently it's not worth it!!! */ \ | |
802 | /* now that DFmode cannot go into CPU register file, */ \ | |
803 | /* maybe I should allow float ... */ \ | |
804 | /* but then I have to handle memory-to-memory moves in movdf ?? */ \ | |
805 | \ | |
806 | if (GET_MODE_BITSIZE(mode) > 16) \ | |
807 | goto fail; \ | |
808 | \ | |
809 | /* accept @(R0) - which is @0(R0) */ \ | |
810 | if (GET_CODE (xfoob) == REG \ | |
811 | && REG_OK_FOR_BASE_P(xfoob)) \ | |
812 | goto ADDR; \ | |
813 | \ | |
814 | /* accept @address */ \ | |
815 | if (CONSTANT_ADDRESS_P (xfoob)) \ | |
816 | goto ADDR; \ | |
817 | \ | |
818 | /* accept @X(R0) */ \ | |
819 | if (GET_CODE (xfoob) == PLUS \ | |
820 | && GET_CODE (XEXP (xfoob, 0)) == REG \ | |
821 | && REG_OK_FOR_BASE_P (XEXP (xfoob, 0)) \ | |
822 | && CONSTANT_ADDRESS_P (XEXP (xfoob, 1))) \ | |
823 | goto ADDR; \ | |
824 | \ | |
825 | /* accept @-(R0) */ \ | |
826 | if (GET_CODE (xfoob) == PRE_DEC \ | |
827 | && GET_CODE (XEXP (xfoob, 0)) == REG \ | |
828 | && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \ | |
829 | goto ADDR; \ | |
830 | \ | |
831 | /* accept @(R0)+ */ \ | |
832 | if (GET_CODE (xfoob) == POST_INC \ | |
833 | && GET_CODE (XEXP (xfoob, 0)) == REG \ | |
834 | && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \ | |
835 | goto ADDR; \ | |
836 | \ | |
a882392b | 837 | /* anything else is invalid */ \ |
2c9c2489 RK |
838 | fail: ; \ |
839 | } | |
840 | ||
841 | \f | |
842 | /* Try machine-dependent ways of modifying an illegitimate address | |
843 | to be legitimate. If we find one, return the new, valid address. | |
844 | This macro is used in only one place: `memory_address' in explow.c. | |
845 | ||
846 | OLDX is the address as it was before break_out_memory_refs was called. | |
847 | In some cases it is useful to look at this to decide what needs to be done. | |
848 | ||
849 | MODE and WIN are passed so that this macro can use | |
850 | GO_IF_LEGITIMATE_ADDRESS. | |
851 | ||
852 | It is always safe for this macro to do nothing. It exists to recognize | |
853 | opportunities to optimize the output. */ | |
854 | ||
855 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} | |
856 | ||
857 | ||
858 | /* Go to LABEL if ADDR (a legitimate address expression) | |
859 | has an effect that depends on the machine mode it is used for. | |
38e01259 | 860 | On the pdp this is for predec/postinc */ |
2c9c2489 RK |
861 | |
862 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
863 | { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \ | |
864 | goto LABEL; \ | |
865 | } | |
866 | ||
867 | \f | |
868 | /* Specify the machine mode that this machine uses | |
869 | for the index in the tablejump instruction. */ | |
870 | #define CASE_VECTOR_MODE HImode | |
871 | ||
872 | /* Define this if a raw index is all that is needed for a | |
873 | `tablejump' insn. */ | |
874 | #define CASE_TAKES_INDEX_RAW | |
875 | ||
18543a22 ILT |
876 | /* Define as C expression which evaluates to nonzero if the tablejump |
877 | instruction expects the table to contain offsets from the address of the | |
878 | table. | |
879 | Do not define this if the table should contain absolute addresses. */ | |
880 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
2c9c2489 RK |
881 | |
882 | /* Specify the tree operation to be used to convert reals to integers. */ | |
883 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
884 | ||
885 | /* This is the kind of divide that is easiest to do in the general case. */ | |
886 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
887 | ||
888 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
889 | #define DEFAULT_SIGNED_CHAR 1 | |
890 | ||
891 | /* Max number of bytes we can move from memory to memory | |
892 | in one reasonably fast instruction. | |
893 | */ | |
894 | ||
895 | #define MOVE_MAX 2 | |
896 | ||
897 | /* Zero extension is faster if the target is known to be zero */ | |
898 | /* #define SLOW_ZERO_EXTEND */ | |
899 | ||
900 | /* Nonzero if access to memory by byte is slow and undesirable. - | |
901 | */ | |
902 | #define SLOW_BYTE_ACCESS 0 | |
903 | ||
904 | /* Do not break .stabs pseudos into continuations. */ | |
905 | #define DBX_CONTIN_LENGTH 0 | |
906 | ||
907 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
908 | is done just by pretending it is already truncated. */ | |
909 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
910 | ||
911 | ||
912 | /* Add any extra modes needed to represent the condition code. | |
913 | ||
914 | CCFPmode is used for FPU, but should we use a separate reg? */ | |
aa0b4465 | 915 | #define EXTRA_CC_MODES CC(CCFPmode, "CCFP") |
2c9c2489 RK |
916 | |
917 | /* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE, | |
918 | return the mode to be used for the comparison. For floating-point, CCFPmode | |
919 | should be used. */ | |
920 | ||
921 | #define SELECT_CC_MODE(OP,X,Y) \ | |
922 | (GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode) | |
923 | ||
924 | /* We assume that the store-condition-codes instructions store 0 for false | |
925 | and some other value for true. This is the value stored for true. */ | |
926 | ||
927 | /* #define STORE_FLAG_VALUE 1 */ | |
928 | ||
929 | /* Specify the machine mode that pointers have. | |
930 | After generation of rtl, the compiler makes no further distinction | |
931 | between pointers and any other objects of this machine mode. */ | |
932 | #define Pmode HImode | |
933 | ||
934 | /* A function address in a call instruction | |
935 | is a word address (for indexing purposes) | |
936 | so give the MEM rtx a word's mode. */ | |
937 | #define FUNCTION_MODE HImode | |
938 | ||
939 | /* Define this if addresses of constant functions | |
940 | shouldn't be put through pseudo regs where they can be cse'd. | |
941 | Desirable on machines where ordinary constants are expensive | |
942 | but a CALL with constant address is cheap. */ | |
943 | /* #define NO_FUNCTION_CSE */ | |
944 | ||
945 | /* Compute the cost of computing a constant rtl expression RTX | |
946 | whose rtx-code is CODE. The body of this macro is a portion | |
947 | of a switch statement. If the code is computed here, | |
948 | return it with a return statement. Otherwise, break from the switch. | |
949 | ||
950 | -1, 0, 1 are cheaper for add, sub ... | |
951 | */ | |
952 | ||
953 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ | |
954 | case CONST_INT: \ | |
955 | if (INTVAL(RTX) == 0 \ | |
956 | || INTVAL(RTX) == -1 \ | |
957 | || INTVAL(RTX) == 1) \ | |
958 | return 0; \ | |
959 | case CONST: \ | |
960 | case LABEL_REF: \ | |
961 | case SYMBOL_REF: \ | |
962 | /* twice as expensive as REG */ \ | |
963 | return 2; \ | |
964 | case CONST_DOUBLE: \ | |
965 | /* twice (or 4 times) as expensive as 16 bit */ \ | |
966 | return 4; | |
967 | \f | |
968 | /* cost of moving one register class to another */ | |
cf011243 AO |
969 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
970 | register_move_cost (CLASS1, CLASS2) | |
2c9c2489 RK |
971 | |
972 | /* Tell emit-rtl.c how to initialize special values on a per-function base. */ | |
973 | extern int optimize; | |
974 | extern struct rtx_def *cc0_reg_rtx; | |
975 | ||
976 | #define CC_STATUS_MDEP rtx | |
977 | ||
978 | #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) | |
979 | \f | |
980 | /* Tell final.c how to eliminate redundant test instructions. */ | |
981 | ||
982 | /* Here we define machine-dependent flags and fields in cc_status | |
983 | (see `conditions.h'). */ | |
984 | ||
985 | #define CC_IN_FPU 04000 | |
986 | ||
987 | /* Do UPDATE_CC if EXP is a set, used in | |
988 | NOTICE_UPDATE_CC | |
989 | ||
990 | floats only do compare correctly, else nullify ... | |
991 | ||
992 | get cc0 out soon ... | |
993 | */ | |
994 | ||
995 | /* Store in cc_status the expressions | |
996 | that the condition codes will describe | |
997 | after execution of an instruction whose pattern is EXP. | |
998 | Do not alter them if the instruction would not alter the cc's. */ | |
999 | ||
1000 | #define NOTICE_UPDATE_CC(EXP, INSN) \ | |
1001 | { if (GET_CODE (EXP) == SET) \ | |
1002 | { \ | |
1003 | notice_update_cc_on_set(EXP, INSN); \ | |
1004 | } \ | |
1005 | else if (GET_CODE (EXP) == PARALLEL \ | |
1006 | && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ | |
1007 | { \ | |
1008 | notice_update_cc_on_set(XVECEXP (EXP, 0, 0), INSN); \ | |
1009 | } \ | |
1010 | else if (GET_CODE (EXP) == CALL) \ | |
1011 | { /* all bets are off */ CC_STATUS_INIT; } \ | |
1012 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ | |
1013 | && cc_status.value2 \ | |
ed03c6cd JM |
1014 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ |
1015 | { \ | |
1016 | printf ("here!\n"); \ | |
1017 | cc_status.value2 = 0; \ | |
1018 | } \ | |
2c9c2489 RK |
1019 | } |
1020 | \f | |
1021 | /* Control the assembler format that we output. */ | |
1022 | ||
1023 | /* Output at beginning of assembler file. */ | |
1024 | ||
1025 | #if 0 | |
1026 | #define ASM_FILE_START(FILE) \ | |
1027 | ( \ | |
1028 | fprintf (FILE, "\t.data\n"), \ | |
1029 | fprintf (FILE, "$help$: . = .+8 ; space for tmp moves!\n") \ | |
1030 | /* do we need reg def's R0 = %0 etc ??? */ \ | |
1031 | ) | |
1032 | #else | |
b0106b24 | 1033 | #define ASM_FILE_START(FILE) |
2c9c2489 RK |
1034 | #endif |
1035 | ||
1036 | ||
1037 | /* Output to assembler file text saying following lines | |
1038 | may contain character constants, extra white space, comments, etc. */ | |
1039 | ||
1040 | #define ASM_APP_ON "" | |
1041 | ||
1042 | /* Output to assembler file text saying following lines | |
1043 | no longer contain unusual constructs. */ | |
1044 | ||
1045 | #define ASM_APP_OFF "" | |
1046 | ||
1047 | /* Output before read-only data. */ | |
1048 | ||
1049 | #define TEXT_SECTION_ASM_OP "\t.text\n" | |
1050 | ||
1051 | /* Output before writable data. */ | |
1052 | ||
1053 | #define DATA_SECTION_ASM_OP "\t.data\n" | |
1054 | ||
1055 | /* How to refer to registers in assembler output. | |
1056 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1057 | ||
1058 | #define REGISTER_NAMES \ | |
d14ff9bd | 1059 | {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \ |
2c9c2489 RK |
1060 | "ac0", "ac1", "ac2", "ac3", "ac4", "ac5" } |
1061 | ||
1062 | /* How to renumber registers for dbx and gdb. */ | |
1063 | ||
1064 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1065 | ||
1066 | /* This is how to output the definition of a user-level label named NAME, | |
1067 | such as the label on a static function or variable NAME. */ | |
1068 | ||
1069 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1070 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1071 | ||
1072 | /* This is how to output a command to make the user-level label named NAME | |
1073 | defined for reference from other files. */ | |
1074 | ||
1075 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
1076 | do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs("\n", FILE); } while (0) | |
1077 | ||
4e0c8ad2 | 1078 | /* The prefix to add to user-visible assembler symbols. */ |
2c9c2489 | 1079 | |
4e0c8ad2 | 1080 | #define USER_LABEL_PREFIX "_" |
2c9c2489 RK |
1081 | |
1082 | /* This is how to output an internal numbered label where | |
1083 | PREFIX is the class of label and NUM is the number within the class. */ | |
1084 | ||
1085 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
1086 | fprintf (FILE, "%s_%d:\n", PREFIX, NUM) | |
1087 | ||
1088 | /* This is how to store into the string LABEL | |
1089 | the symbol_ref name of an internal numbered label where | |
1090 | PREFIX is the class of label and NUM is the number within the class. | |
1091 | This is suitable for output with `assemble_name'. */ | |
1092 | ||
1093 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
1094 | sprintf (LABEL, "*%s_%d", PREFIX, NUM) | |
1095 | ||
1096 | /* This is how to output an assembler line defining a `double' constant. */ | |
1097 | ||
1098 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ | |
1099 | fprintf (FILE, "\tdouble %.20e\n", (VALUE)) | |
1100 | ||
1101 | /* This is how to output an assembler line defining a `float' constant. */ | |
1102 | ||
1103 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ | |
1104 | fprintf (FILE, "\tfloat %.12e\n", (VALUE)) | |
1105 | ||
2c9c2489 RK |
1106 | /* Likewise for `short' and `char' constants. */ |
1107 | ||
1108 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
af36a4d2 JM |
1109 | ( fprintf (FILE, TARGET_UNIX_ASM ? "\t" : "\t.word "), \ |
1110 | output_addr_const_pdp11 (FILE, (VALUE)), \ | |
2c9c2489 RK |
1111 | fprintf (FILE, " /*short*/\n")) |
1112 | ||
1113 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
1114 | ( fprintf (FILE, "\t.byte "), \ | |
af36a4d2 | 1115 | output_addr_const_pdp11 (FILE, (VALUE)), \ |
2c9c2489 RK |
1116 | fprintf (FILE, " /* char */\n")) |
1117 | ||
af36a4d2 JM |
1118 | /* This is how to output an assembler line for a numeric constant byte. |
1119 | This won't actually be used since we define ASM_OUTPUT_CHAR. | |
2c9c2489 RK |
1120 | */ |
1121 | ||
1122 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
af36a4d2 | 1123 | fprintf (FILE, "\t.byte %o\n", (VALUE)) |
2c9c2489 RK |
1124 | |
1125 | #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ | |
1126 | output_ascii (FILE, P, SIZE) | |
1127 | ||
2c9c2489 RK |
1128 | /* This is how to output an element of a case-vector that is absolute. */ |
1129 | ||
1130 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
af36a4d2 | 1131 | fprintf (FILE, "\t%sL_%d\n", TARGET_UNIX_ASM ? "" : ".word ", VALUE) |
2c9c2489 RK |
1132 | |
1133 | /* This is how to output an element of a case-vector that is relative. | |
3d3ff202 | 1134 | Don't define this if it is not supported. */ |
2c9c2489 | 1135 | |
3d3ff202 | 1136 | /* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */ |
2c9c2489 RK |
1137 | |
1138 | /* This is how to output an assembler line | |
1139 | that says to advance the location counter | |
1140 | to a multiple of 2**LOG bytes. | |
1141 | ||
1142 | who needs this???? | |
1143 | */ | |
1144 | ||
1145 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
d14ff9bd JM |
1146 | switch (LOG) \ |
1147 | { \ | |
1148 | case 0: \ | |
1149 | break; \ | |
1150 | case 1: \ | |
1151 | fprintf (FILE, "\t.even\n"); \ | |
1152 | break; \ | |
1153 | default: \ | |
1154 | abort (); \ | |
1155 | } | |
2c9c2489 RK |
1156 | |
1157 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
af36a4d2 | 1158 | fprintf (FILE, "\t.=.+ %o\n", (SIZE)) |
2c9c2489 RK |
1159 | |
1160 | /* This says how to output an assembler line | |
1161 | to define a global common symbol. */ | |
1162 | ||
1163 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1164 | ( fprintf ((FILE), ".globl "), \ | |
1165 | assemble_name ((FILE), (NAME)), \ | |
1166 | fprintf ((FILE), "\n"), \ | |
1167 | assemble_name ((FILE), (NAME)), \ | |
af36a4d2 | 1168 | fprintf ((FILE), ": .=.+ %o\n", (ROUNDED)) \ |
2c9c2489 RK |
1169 | ) |
1170 | ||
1171 | /* This says how to output an assembler line | |
1172 | to define a local common symbol. */ | |
1173 | ||
1174 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1175 | ( assemble_name ((FILE), (NAME)), \ | |
af36a4d2 | 1176 | fprintf ((FILE), ":\t.=.+ %o\n", (ROUNDED))) |
2c9c2489 RK |
1177 | |
1178 | /* Store in OUTPUT a string (made with alloca) containing | |
1179 | an assembler-name for a local static variable named NAME. | |
1180 | LABELNO is an integer which is different for each call. */ | |
1181 | ||
1182 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1183 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
1184 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
1185 | ||
2c9c2489 RK |
1186 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
1187 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1188 | For `%' followed by punctuation, CODE is the punctuation and X is null. | |
1189 | ||
1190 | */ | |
1191 | ||
1192 | ||
1193 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
1194 | { if (CODE == '#') fprintf (FILE, "#"); \ | |
1195 | else if (GET_CODE (X) == REG) \ | |
1196 | fprintf (FILE, "%s", reg_names[REGNO (X)]); \ | |
1197 | else if (GET_CODE (X) == MEM) \ | |
1198 | output_address (XEXP (X, 0)); \ | |
1199 | else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != SImode) \ | |
1200 | { union { double d; int i[2]; } u; \ | |
1201 | u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ | |
1202 | fprintf (FILE, "#%.20e", u.d); } \ | |
af36a4d2 | 1203 | else { putc ('$', FILE); output_addr_const_pdp11 (FILE, X); }} |
2c9c2489 RK |
1204 | \f |
1205 | /* Print a memory address as an operand to reference that memory location. */ | |
1206 | ||
1207 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
1208 | print_operand_address (FILE, ADDR) | |
1209 | ||
1210 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
1211 | ( \ | |
1212 | fprintf (FILE, "\tmov %s, -(sp)\n", reg_names[REGNO]) \ | |
1213 | ) | |
1214 | ||
1215 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
1216 | ( \ | |
1217 | fprintf (FILE, "\tmov (sp)+, %s\n", reg_names[REGNO]) \ | |
1218 | ) | |
1219 | ||
d06cca55 RK |
1220 | /* trampoline - how should i do it in separate i+d ? |
1221 | have some allocate_trampoline magic??? | |
2c9c2489 | 1222 | |
d06cca55 RK |
1223 | the following should work for shared I/D: */ |
1224 | ||
1225 | /* lets see whether this works as trampoline: | |
1226 | MV #STATIC, $4 0x940Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM | |
1227 | JMP FUNCTION 0x0058 0x0000 <- FUNCTION | |
1228 | */ | |
1229 | ||
1230 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
2c9c2489 | 1231 | { \ |
fea1b650 RK |
1232 | if (TARGET_SPLIT) \ |
1233 | abort(); \ | |
1234 | \ | |
af36a4d2 JM |
1235 | ASM_OUTPUT_SHORT (FILE, GEN_INT (0x9400+STATIC_CHAIN_REGNUM)); \ |
1236 | ASM_OUTPUT_SHORT (FILE, const0_rtx); \ | |
1237 | ASM_OUTPUT_SHORT (FILE, GEN_INT(0x0058)); \ | |
1238 | ASM_OUTPUT_SHORT (FILE, const0_rtx); \ | |
2c9c2489 RK |
1239 | } |
1240 | ||
d06cca55 RK |
1241 | #define TRAMPOLINE_SIZE 8 |
1242 | #define TRAMPOLINE_ALIGN 16 | |
1243 | ||
1244 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1245 | FNADDR is an RTX for the address of the function's pure code. | |
1246 | CXT is an RTX for the static chain value for the function. */ | |
1247 | ||
1248 | #define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT) \ | |
2c9c2489 | 1249 | { \ |
fea1b650 RK |
1250 | if (TARGET_SPLIT) \ |
1251 | abort(); \ | |
1252 | \ | |
c5c76735 JL |
1253 | emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 2)), CXT); \ |
1254 | emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), FNADDR); \ | |
2c9c2489 RK |
1255 | } |
1256 | ||
d06cca55 | 1257 | |
2c9c2489 RK |
1258 | /* Some machines may desire to change what optimizations are |
1259 | performed for various optimization levels. This macro, if | |
1260 | defined, is executed once just after the optimization level is | |
1261 | determined and before the remainder of the command options have | |
1262 | been parsed. Values set in this macro are used as the default | |
1263 | values for the other command line options. | |
1264 | ||
1265 | LEVEL is the optimization level specified; 2 if -O2 is | |
1266 | specified, 1 if -O is specified, and 0 if neither is specified. */ | |
1267 | ||
c6aded7c | 1268 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ |
2c9c2489 RK |
1269 | { \ |
1270 | if (LEVEL >= 3) \ | |
1271 | { \ | |
c6aded7c AG |
1272 | if (! SIZE) \ |
1273 | flag_inline_functions = 1; \ | |
2c9c2489 RK |
1274 | flag_omit_frame_pointer = 1; \ |
1275 | /* flag_unroll_loops = 1; */ \ | |
1276 | } \ | |
1277 | } | |
1278 | ||
1279 | ||
1280 | /* Provide the costs of a rtl expression. This is in the body of a | |
1281 | switch on CODE. | |
1282 | ||
1283 | we don't say how expensive SImode is - pretty expensive!!! | |
1284 | ||
1285 | there is something wrong in MULT because MULT is not | |
1286 | as cheap as total = 2 even if we can shift! | |
1287 | ||
f4190acc | 1288 | if optimizing for size make mult etc cheap, but not 1, so when |
2c9c2489 RK |
1289 | in doubt the faster insn is chosen. |
1290 | */ | |
1291 | ||
1292 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ | |
1293 | case MULT: \ | |
f4190acc | 1294 | if (optimize_size) \ |
2c9c2489 RK |
1295 | total = COSTS_N_INSNS(2); \ |
1296 | else \ | |
1297 | total = COSTS_N_INSNS (11); \ | |
1298 | break; \ | |
1299 | case DIV: \ | |
f4190acc | 1300 | if (optimize_size) \ |
2c9c2489 RK |
1301 | total = COSTS_N_INSNS(2); \ |
1302 | else \ | |
1303 | total = COSTS_N_INSNS (25); \ | |
1304 | break; \ | |
1305 | case MOD: \ | |
f4190acc | 1306 | if (optimize_size) \ |
2c9c2489 RK |
1307 | total = COSTS_N_INSNS(2); \ |
1308 | else \ | |
1309 | total = COSTS_N_INSNS (26); \ | |
1310 | break; \ | |
1311 | case ABS: \ | |
f4190acc | 1312 | /* equivalent to length, so same for optimize_size */ \ |
2c9c2489 RK |
1313 | total = COSTS_N_INSNS (3); \ |
1314 | break; \ | |
1315 | case ZERO_EXTEND: \ | |
1316 | /* only used for: qi->hi */ \ | |
1317 | total = COSTS_N_INSNS(1); \ | |
1318 | break; \ | |
1319 | case SIGN_EXTEND: \ | |
1320 | if (GET_MODE(X) == HImode) \ | |
1321 | total = COSTS_N_INSNS(1); \ | |
1322 | else if (GET_MODE(X) == SImode) \ | |
1323 | total = COSTS_N_INSNS(6); \ | |
1324 | else \ | |
7e476021 | 1325 | total = COSTS_N_INSNS(2); \ |
2c9c2489 RK |
1326 | break; \ |
1327 | /* case LSHIFT: */ \ | |
1328 | case ASHIFT: \ | |
1329 | case LSHIFTRT: \ | |
1330 | case ASHIFTRT: \ | |
f4190acc | 1331 | if (optimize_size) \ |
2c9c2489 RK |
1332 | total = COSTS_N_INSNS(1); \ |
1333 | else if (GET_MODE(X) == QImode) \ | |
1334 | { \ | |
1335 | if (GET_CODE(XEXP (X,1)) != CONST_INT) \ | |
7e476021 RK |
1336 | total = COSTS_N_INSNS(8); /* worst case */ \ |
1337 | else \ | |
2c9c2489 RK |
1338 | total = COSTS_N_INSNS(INTVAL(XEXP (X,1))); \ |
1339 | } \ | |
1340 | else if (GET_MODE(X) == HImode) \ | |
1341 | { \ | |
1342 | if (GET_CODE(XEXP (X,1)) == CONST_INT) \ | |
1343 | { \ | |
1344 | if (abs (INTVAL (XEXP (X, 1))) == 1) \ | |
1345 | total = COSTS_N_INSNS(1); \ | |
1346 | else \ | |
1347 | total = COSTS_N_INSNS(2.5 + 0.5 *INTVAL(XEXP(X,1))); \ | |
1348 | } \ | |
1349 | else /* worst case */ \ | |
1350 | total = COSTS_N_INSNS (10); \ | |
1351 | } \ | |
1352 | else if (GET_MODE(X) == SImode) \ | |
1353 | { \ | |
1354 | if (GET_CODE(XEXP (X,1)) == CONST_INT) \ | |
1355 | total = COSTS_N_INSNS(2.5 + 0.5 *INTVAL(XEXP(X,1))); \ | |
1356 | else /* worst case */ \ | |
1357 | total = COSTS_N_INSNS(18); \ | |
1358 | } \ | |
1359 | break; | |
1360 | ||
1361 | ||
1362 | /* there is no point in avoiding branches on a pdp, | |
1363 | since branches are really cheap - I just want to find out | |
1364 | how much difference the BRANCH_COST macro makes in code */ | |
1365 | #define BRANCH_COST (TARGET_BRANCH_CHEAP ? 0 : 1) | |
1366 | ||
1367 | ||
1368 | #define COMPARE_FLAG_MODE HImode |