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231ddcb7 | 1 | /* Definitions of target machine for GNU compiler. NS32000 version. |
cf011243 | 2 | Copyright (C) 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
2001a5cf | 3 | 2001, 2002, 2004 Free Software Foundation, Inc. |
879cad45 | 4 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
231ddcb7 | 5 | |
7ec022b2 | 6 | This file is part of GCC. |
231ddcb7 | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
231ddcb7 RS |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
231ddcb7 RS |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 19 | along with GCC; see the file COPYING. If not, write to |
0e29e3c9 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
231ddcb7 RS |
22 | |
23 | ||
a782515b JT |
24 | #define TARGET_CPU_CPP_BUILTINS() \ |
25 | do \ | |
26 | { \ | |
27 | builtin_define ("__ns32000__"); \ | |
28 | \ | |
29 | /* CPU type */ \ | |
30 | if (TARGET_32532) \ | |
31 | builtin_define ("__ns32532__"); \ | |
32 | else if (TARGET_32332) \ | |
33 | builtin_define ("__ns32332__"); \ | |
34 | else \ | |
35 | builtin_define ("__ns32032__"); \ | |
36 | \ | |
37 | /* FPU type */ \ | |
38 | if (TARGET_32381) \ | |
39 | builtin_define ("__ns32381__"); \ | |
40 | else if (TARGET_32081) \ | |
41 | builtin_define ("__ns32081__"); \ | |
42 | \ | |
43 | /* Misc. */ \ | |
44 | if (TARGET_RTD) \ | |
45 | builtin_define ("__RTD__"); \ | |
46 | \ | |
47 | builtin_assert ("cpu=ns32k"); \ | |
48 | builtin_assert ("machine=ns32k"); \ | |
49 | } \ | |
50 | while (0) | |
231ddcb7 RS |
51 | |
52 | /* Print subsidiary information on the compiler version in use. */ | |
53 | #define TARGET_VERSION fprintf (stderr, " (32000, GAS syntax)"); | |
54 | ||
55 | \f | |
56 | /* ABSOLUTE PREFIX, IMMEDIATE_PREFIX and EXTERNAL_PREFIX can be defined | |
57 | to cover most NS32k addressing syntax variations. This way we don't | |
58 | need to redefine long macros in all the tm.h files for just slight | |
59 | variations in assembler syntax. */ | |
60 | ||
61 | #ifndef ABSOLUTE_PREFIX | |
62 | #define ABSOLUTE_PREFIX '@' | |
63 | #endif | |
64 | ||
65 | #if defined(IMMEDIATE_PREFIX) && IMMEDIATE_PREFIX | |
66 | #define PUT_IMMEDIATE_PREFIX(FILE) putc(IMMEDIATE_PREFIX, FILE) | |
67 | #else | |
68 | #define PUT_IMMEDIATE_PREFIX(FILE) | |
69 | #endif | |
70 | #if defined(ABSOLUTE_PREFIX) && ABSOLUTE_PREFIX | |
71 | #define PUT_ABSOLUTE_PREFIX(FILE) putc(ABSOLUTE_PREFIX, FILE) | |
72 | #else | |
73 | #define PUT_ABSOLUTE_PREFIX(FILE) | |
74 | #endif | |
75 | #if defined(EXTERNAL_PREFIX) && EXTERNAL_PREFIX | |
76 | #define PUT_EXTERNAL_PREFIX(FILE) putc(EXTERNAL_PREFIX, FILE) | |
77 | #else | |
78 | #define PUT_EXTERNAL_PREFIX(FILE) | |
79 | #endif | |
80 | ||
81 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
82 | ||
83 | extern int target_flags; | |
84 | ||
5d7c2819 | 85 | /* Masks for target_flags */ |
2eb2901a JT |
86 | #define MASK_32081 1 |
87 | #define MASK_RTD 2 | |
88 | #define MASK_REGPARM 4 | |
89 | #define MASK_32532 8 | |
90 | #define MASK_32332 16 | |
91 | #define MASK_NO_SB 32 | |
92 | #define MASK_NO_BITFIELD 64 | |
93 | #define MASK_HIMEM 128 | |
94 | #define MASK_32381 256 | |
95 | #define MASK_MULT_ADD 512 | |
96 | #define MASK_SRC 1024 | |
5d7c2819 | 97 | #define MASK_IEEE_COMPARE 2048 |
2eb2901a | 98 | |
231ddcb7 RS |
99 | /* Macros used in the machine description to test the flags. */ |
100 | ||
101 | /* Compile 32081 insns for floating point (not library calls). */ | |
2eb2901a JT |
102 | #define TARGET_32081 (target_flags & MASK_32081) |
103 | #define TARGET_32381 (target_flags & MASK_32381) | |
83575957 | 104 | |
4c54e4e4 ID |
105 | /* The use of multiply-add instructions is optional because there may |
106 | * be cases where it produces worse code. | |
83575957 ID |
107 | */ |
108 | ||
2eb2901a | 109 | #define TARGET_MULT_ADD (target_flags & MASK_MULT_ADD) |
231ddcb7 RS |
110 | |
111 | /* Compile using rtd insn calling sequence. | |
112 | This will not work unless you use prototypes at least | |
113 | for all functions that can take varying numbers of args. */ | |
2eb2901a | 114 | #define TARGET_RTD (target_flags & MASK_RTD) |
231ddcb7 RS |
115 | |
116 | /* Compile passing first two args in regs 0 and 1. */ | |
2eb2901a | 117 | #define TARGET_REGPARM (target_flags & MASK_REGPARM) |
231ddcb7 RS |
118 | |
119 | /* Options to select type of CPU, for better optimization. | |
120 | The output is correct for any kind of 32000 regardless of these options. */ | |
2eb2901a JT |
121 | #define TARGET_32532 (target_flags & MASK_32532) |
122 | #define TARGET_32332 (target_flags & MASK_32332) | |
231ddcb7 RS |
123 | |
124 | /* Ok to use the static base register (and presume it's 0) */ | |
2eb2901a | 125 | #define TARGET_SB ((target_flags & MASK_NO_SB) == 0) |
5d7c2819 | 126 | |
2eb2901a | 127 | #define TARGET_HIMEM (target_flags & MASK_HIMEM) |
231ddcb7 | 128 | |
43a88a8c | 129 | /* Compile using bit-field insns. */ |
2eb2901a | 130 | #define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0) |
879cad45 | 131 | |
ac14c725 | 132 | #define TARGET_IEEE_COMPARE (target_flags & MASK_IEEE_COMPARE) |
5d7c2819 | 133 | |
231ddcb7 RS |
134 | /* Macro to define tables used to set the flags. |
135 | This is a list in braces of pairs in braces, | |
136 | each pair being { "NAME", VALUE } | |
137 | where VALUE is the bits to set or minus the bits to clear. | |
138 | An empty string NAME is used to identify the default VALUE. */ | |
047142d3 | 139 | #define TARGET_SWITCHES \ |
2eb2901a JT |
140 | { { "32081", MASK_32081, N_("Use hardware fp")}, \ |
141 | { "soft-float", -(MASK_32081|MASK_32381), \ | |
142 | N_("Don't use hardware fp")}, \ | |
143 | { "rtd", MASK_RTD, N_("Alternative calling convention")}, \ | |
144 | { "nortd", -MASK_RTD, N_("Use normal calling convention")}, \ | |
145 | { "regparm", MASK_REGPARM, N_("Pass some arguments in registers")}, \ | |
146 | { "noregparm", -MASK_REGPARM, N_("Pass all arguments on stack")}, \ | |
147 | { "32532", MASK_32532|MASK_32332, N_("Optimize for 32532 cpu")}, \ | |
148 | { "32332", MASK_32332, N_("Optimize for 32332 cpu")}, \ | |
149 | { "32332", -MASK_32532, 0}, \ | |
150 | { "32032", -(MASK_32532|MASK_32332), N_("Optimize for 32032")}, \ | |
151 | { "sb", -MASK_NO_SB, \ | |
047142d3 | 152 | N_("Register sb is zero. Use for absolute addressing")}, \ |
2eb2901a JT |
153 | { "nosb", MASK_NO_SB, N_("Do not use register sb")}, \ |
154 | { "bitfield", -MASK_NO_BITFIELD, \ | |
5d7c2819 ID |
155 | N_("Use bit-field instructions")}, \ |
156 | { "nobitfield", MASK_NO_BITFIELD, \ | |
2eb2901a | 157 | N_("Do not use bit-field instructions")}, \ |
2eb2901a JT |
158 | { "himem", MASK_HIMEM, N_("Generate code for high memory")}, \ |
159 | { "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \ | |
160 | { "32381", MASK_32381, N_("32381 fpu")}, \ | |
161 | { "mult-add", MASK_MULT_ADD, \ | |
162 | N_("Use multiply-accumulate fp instructions")}, \ | |
163 | { "nomult-add", -MASK_MULT_ADD, \ | |
5d7c2819 | 164 | N_("Do not use multiply-accumulate fp instructions") }, \ |
2eb2901a JT |
165 | { "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \ |
166 | { "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \ | |
5d7c2819 ID |
167 | { "ieee-compare", MASK_IEEE_COMPARE, N_("Use IEEE math for fp comparisons")}, \ |
168 | { "noieee-compare", -MASK_IEEE_COMPARE, \ | |
169 | N_("Do not use IEEE math for fp comparisons")}, \ | |
4c54e4e4 | 170 | { "", TARGET_DEFAULT, 0}} |
83575957 | 171 | |
231ddcb7 | 172 | /* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */ |
666b023e RK |
173 | |
174 | /* When we are generating PIC, the sb is used as a pointer | |
83575957 | 175 | to the GOT. 32381 is a superset of 32081 */ |
666b023e | 176 | |
5d7c2819 ID |
177 | #define OVERRIDE_OPTIONS \ |
178 | { \ | |
179 | if (target_flags & MASK_32532) \ | |
180 | target_flags |= MASK_32332; \ | |
181 | if (flag_pic || TARGET_HIMEM) \ | |
182 | target_flags |= MASK_NO_SB; \ | |
183 | if (TARGET_32381) \ | |
184 | target_flags |= MASK_32081; \ | |
185 | else \ | |
186 | target_flags &= ~MASK_MULT_ADD; \ | |
187 | if (flag_unsafe_math_optimizations) \ | |
188 | target_flags &= ~MASK_IEEE_COMPARE; \ | |
666b023e RK |
189 | } |
190 | ||
83575957 ID |
191 | /* Zero or more C statements that may conditionally modify two |
192 | variables `fixed_regs' and `call_used_regs' (both of type `char | |
193 | []') after they have been initialized from the two preceding | |
194 | macros. | |
195 | ||
196 | This is necessary in case the fixed or call-clobbered registers | |
197 | depend on target flags. | |
198 | ||
199 | You need not define this macro if it has no work to do. | |
200 | ||
201 | If the usage of an entire class of registers depends on the target | |
202 | flags, you may indicate this to GCC by using this macro to modify | |
203 | `fixed_regs' and `call_used_regs' to 1 for each of the registers in | |
204 | the classes which should not be used by GCC. Also define the macro | |
205 | `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a | |
206 | letter for a class that shouldn't be used. | |
207 | ||
208 | (However, if this class is not included in `GENERAL_REGS' and all | |
209 | of the insn patterns whose constraints permit this class are | |
210 | controlled by target switches, then GCC will automatically avoid | |
211 | using these registers when the target switches are opposed to | |
212 | them.) */ | |
213 | ||
214 | #define CONDITIONAL_REGISTER_USAGE \ | |
215 | do \ | |
216 | { \ | |
217 | if (!TARGET_32081) \ | |
218 | { \ | |
219 | int regno; \ | |
220 | \ | |
221 | for (regno = F0_REGNUM; regno <= F0_REGNUM + 8; regno++) \ | |
222 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
223 | } \ | |
224 | if (!TARGET_32381) \ | |
225 | { \ | |
226 | int regno; \ | |
227 | \ | |
228 | for (regno = L1_REGNUM; regno <= L1_REGNUM + 8; regno++) \ | |
229 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
230 | } \ | |
231 | } \ | |
232 | while (0) | |
233 | ||
231ddcb7 RS |
234 | \f |
235 | /* target machine storage layout */ | |
236 | ||
237 | /* Define this if most significant bit is lowest numbered | |
238 | in instructions that operate on numbered bit-fields. | |
239 | This is not true on the ns32k. */ | |
240 | #define BITS_BIG_ENDIAN 0 | |
241 | ||
242 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
243 | /* That is not true on the ns32k. */ | |
244 | #define BYTES_BIG_ENDIAN 0 | |
245 | ||
246 | /* Define this if most significant word of a multiword number is lowest | |
247 | numbered. This is not true on the ns32k. */ | |
248 | #define WORDS_BIG_ENDIAN 0 | |
249 | ||
231ddcb7 RS |
250 | /* Width of a word, in units (bytes). */ |
251 | #define UNITS_PER_WORD 4 | |
252 | ||
231ddcb7 RS |
253 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
254 | #define PARM_BOUNDARY 32 | |
255 | ||
256 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
257 | #define STACK_BOUNDARY 32 | |
258 | ||
259 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
260 | #define FUNCTION_BOUNDARY 16 | |
261 | ||
262 | /* Alignment of field after `int : 0' in a structure. */ | |
263 | #define EMPTY_FIELD_BOUNDARY 32 | |
264 | ||
265 | /* Every structure's size must be a multiple of this. */ | |
266 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
267 | ||
268 | /* No data type wants to be aligned rounder than this. */ | |
269 | #define BIGGEST_ALIGNMENT 32 | |
270 | ||
dfbe1b2f | 271 | /* Set this nonzero if move instructions will actually fail to work |
231ddcb7 RS |
272 | when given unaligned data. National claims that the NS32032 |
273 | works without strict alignment, but rumor has it that operands | |
274 | crossing a page boundary cause unpredictable results. */ | |
dfbe1b2f | 275 | #define STRICT_ALIGNMENT 1 |
231ddcb7 | 276 | |
f710504c | 277 | /* If bit field type is int, don't let it cross an int, |
231ddcb7 | 278 | and give entire struct the alignment of an int. */ |
43a88a8c | 279 | /* Required on the 386 since it doesn't have a full set of bit-field insns. |
231ddcb7 RS |
280 | (There is no signed extv insn.) */ |
281 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
282 | \f | |
283 | /* Standard register usage. */ | |
284 | ||
285 | /* Number of actual hardware registers. | |
286 | The hardware registers are assigned numbers for the compiler | |
287 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
288 | All registers that the compiler knows about must be given numbers, | |
289 | even those that are not normally considered general registers. */ | |
83575957 | 290 | #define FIRST_PSEUDO_REGISTER 26 |
231ddcb7 RS |
291 | |
292 | /* 1 for registers that have pervasive standard uses | |
293 | and are not available for the register allocator. | |
294 | On the ns32k, these are the FP, SP, (SB and PC are not included here). */ | |
295 | #define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, \ | |
296 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
83575957 | 297 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
231ddcb7 RS |
298 | 1, 1} |
299 | ||
300 | /* 1 for registers not available across function calls. | |
301 | These must include the FIXED_REGISTERS and also any | |
302 | registers that can be used without being saved. | |
303 | The latter must include the registers where values are returned | |
304 | and the register where structure-value addresses are passed. | |
305 | Aside from that, you can include as many other registers as you like. */ | |
306 | #define CALL_USED_REGISTERS {1, 1, 1, 0, 0, 0, 0, 0, \ | |
307 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
83575957 | 308 | 1, 1, 0, 0, 0, 0, 0, 0, \ |
231ddcb7 RS |
309 | 1, 1} |
310 | ||
83575957 ID |
311 | /* How to refer to registers in assembler output. |
312 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
313 | ||
314 | #define REGISTER_NAMES \ | |
315 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
316 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
317 | "l1", "l1h","l3", "l3h","l5", "l5h","l7", "l7h", \ | |
318 | "fp", "sp"} | |
319 | ||
320 | ||
321 | #define ADDITIONAL_REGISTER_NAMES \ | |
322 | {{"l0", 8}, {"l2", 10}, {"l4", 12}, {"l6", 14}} | |
323 | ||
324 | /* l0-7 are not recognized by the assembler. These are the names to use, | |
325 | * but we don't want ambiguous names in REGISTER_NAMES | |
326 | */ | |
327 | #define OUTPUT_REGISTER_NAMES \ | |
328 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
329 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
330 | "f1", "l1h","f3", "l3h","f5", "l5h","f7", "f7h", \ | |
331 | "fp", "sp"} | |
332 | ||
333 | #define REG_ALLOC_ORDER \ | |
334 | {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 10, 11, 18, 12, 13, 20, 14, 15, 22, 24, 25, 17, 19, 23} | |
335 | ||
336 | /* How to renumber registers for dbx and gdb. | |
337 | NS32000 may need more change in the numeration. XXX */ | |
338 | ||
339 | #define DBX_REGISTER_NUMBER(REGNO) \ | |
340 | ((REGNO) < L1_REGNUM? (REGNO) \ | |
341 | : (REGNO) < FRAME_POINTER_REGNUM? (REGNO) - L1_REGNUM + 22 \ | |
342 | : (REGNO) == FRAME_POINTER_REGNUM? 17 \ | |
343 | : 16) | |
344 | ||
4c54e4e4 ID |
345 | /* dwarf2out.c can't understand the funny DBX register numbering. |
346 | * We use dwarf2out.c for exception handling even though we use DBX | |
347 | * for debugging | |
348 | */ | |
349 | #define DWARF_FRAME_REGNUM(REGNO) (REGNO) | |
83575957 ID |
350 | |
351 | ||
352 | ||
353 | #define R0_REGNUM 0 | |
354 | #define F0_REGNUM 8 | |
355 | #define L1_REGNUM 16 | |
356 | ||
357 | /* Specify the registers used for certain standard purposes. | |
358 | The values of these macros are register numbers. */ | |
359 | ||
360 | /* NS32000 pc is not overloaded on a register. */ | |
361 | /* #define PC_REGNUM */ | |
362 | ||
363 | /* Register to use for pushing function arguments. */ | |
364 | #define STACK_POINTER_REGNUM 25 | |
365 | ||
366 | /* Base register for access to local variables of the function. */ | |
367 | #define FRAME_POINTER_REGNUM 24 | |
368 | ||
369 | ||
231ddcb7 RS |
370 | /* Return number of consecutive hard regs needed starting at reg REGNO |
371 | to hold something of mode MODE. | |
372 | This is ordinarily the length in words of a value of mode MODE | |
373 | but can be less for certain modes in special long registers. | |
83575957 ID |
374 | On the ns32k, all registers are 32 bits long except for the 32381 "long" |
375 | registers but we treat those as pairs */ | |
376 | #define LONG_FP_REGS_P(REGNO) ((REGNO) >= L1_REGNUM && (REGNO) < L1_REGNUM + 8) | |
231ddcb7 RS |
377 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
378 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
379 | ||
380 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ | |
381 | #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok (REGNO, MODE) | |
382 | ||
383 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
384 | when one has mode MODE1 and one has mode MODE2. | |
385 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
e2657a67 | 386 | for any hard reg, then this must be 0 for correct output. */ |
231ddcb7 | 387 | |
83575957 ID |
388 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
389 | ((FLOAT_MODE_P(MODE1) && FLOAT_MODE_P(MODE2) \ | |
390 | && (GET_MODE_UNIT_SIZE(MODE1) == GET_MODE_UNIT_SIZE(MODE2))) \ | |
391 | || (!FLOAT_MODE_P(MODE1) && !FLOAT_MODE_P(MODE2))) | |
231ddcb7 RS |
392 | |
393 | /* Value should be nonzero if functions must have frame pointers. | |
394 | Zero means the frame pointer need not be set up (and parms | |
395 | may be accessed via the stack pointer) in functions that seem suitable. | |
396 | This is computed in `reload', in reload1.c. */ | |
397 | #define FRAME_POINTER_REQUIRED 0 | |
398 | ||
399 | /* Base register for access to arguments of the function. */ | |
83575957 | 400 | #define ARG_POINTER_REGNUM 24 |
231ddcb7 RS |
401 | |
402 | /* Register in which static-chain is passed to a function. */ | |
403 | #define STATIC_CHAIN_REGNUM 1 | |
404 | ||
405 | /* Register in which address to store a structure value | |
406 | is passed to a function. */ | |
2001a5cf | 407 | #define NS32K_STRUCT_VALUE_REGNUM 2 |
231ddcb7 RS |
408 | \f |
409 | /* Define the classes of registers for register constraints in the | |
410 | machine description. Also define ranges of constants. | |
411 | ||
412 | One of the classes must always be named ALL_REGS and include all hard regs. | |
413 | If there is more than one class, another class must be named NO_REGS | |
414 | and contain no registers. | |
415 | ||
416 | The name GENERAL_REGS must be the name of a class (or an alias for | |
417 | another name such as ALL_REGS). This is the class of registers | |
418 | that is allowed by "g" or "r" in a register constraint. | |
419 | Also, registers outside this class are allocated only when | |
420 | instructions express preferences for them. | |
421 | ||
422 | The classes must be numbered in nondecreasing order; that is, | |
423 | a larger-numbered class must never be contained completely | |
424 | in a smaller-numbered class. | |
425 | ||
426 | For any two classes, it is very desirable that there be another | |
427 | class that represents their union. */ | |
83575957 ID |
428 | |
429 | enum reg_class | |
430 | { NO_REGS, GENERAL_REGS, FLOAT_REG0, LONG_FLOAT_REG0, FLOAT_REGS, | |
8056c5f2 ID |
431 | LONG_REGS, FP_REGS, GEN_AND_FP_REGS, FRAME_POINTER_REG, |
432 | STACK_POINTER_REG, GEN_AND_MEM_REGS, ALL_REGS, LIM_REG_CLASSES }; | |
231ddcb7 RS |
433 | |
434 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
435 | ||
436 | /* Give names of register classes as strings for dump file. */ | |
437 | ||
8056c5f2 | 438 | #define REG_CLASS_NAMES \ |
83575957 | 439 | {"NO_REGS", "GENERAL_REGS", "FLOAT_REG0", "LONG_FLOAT_REG0", "FLOAT_REGS", \ |
8056c5f2 ID |
440 | "LONG_REGS", "FP_REGS", "GEN_AND_FP_REGS", "FRAME_POINTER_REG", \ |
441 | "STACK_POINTER_REG", "GEN_AND_MEM_REGS", "ALL_REGS" } | |
231ddcb7 RS |
442 | |
443 | /* Define which registers fit in which classes. | |
444 | This is an initializer for a vector of HARD_REG_SET | |
445 | of length N_REG_CLASSES. */ | |
446 | ||
4c54e4e4 ID |
447 | #define REG_CLASS_CONTENTS \ |
448 | {{0}, /* NO_REGS */ \ | |
449 | {0x00ff}, /* GENERAL_REGS */ \ | |
450 | {0x100}, /* FLOAT_REG0 */ \ | |
451 | {0x300}, /* LONG_FLOAT_REG0 */ \ | |
452 | {0xff00}, /* FLOAT_REGS */ \ | |
8056c5f2 | 453 | {0xff0000}, /* LONG_REGS */ \ |
4c54e4e4 ID |
454 | {0xffff00}, /* FP_REGS */ \ |
455 | {0xffffff}, /* GEN_AND_FP_REGS */ \ | |
456 | {0x1000000}, /* FRAME_POINTER_REG */ \ | |
457 | {0x2000000}, /* STACK_POINTER_REG */ \ | |
458 | {0x30000ff}, /* GEN_AND_MEM_REGS */ \ | |
459 | {0x3ffffff} /* ALL_REGS */ \ | |
460 | } | |
461 | ||
462 | #define SUBSET_P(CLASS1, CLASS2) \ | |
463 | ((ns32k_reg_class_contents[CLASS1][0] \ | |
464 | & ~ns32k_reg_class_contents[CLASS2][0]) == 0) | |
231ddcb7 | 465 | |
8056c5f2 ID |
466 | |
467 | /* LONG_REGS are registers which can only hold double precision floats | |
2a43945f | 468 | * and can only be accessible by long float instructions. |
8056c5f2 | 469 | */ |
e95ef187 RH |
470 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
471 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
472 | ? reg_classes_intersect_p (LONG_REGS, CLASS) : 0) | |
8056c5f2 | 473 | |
231ddcb7 RS |
474 | /* The same information, inverted: |
475 | Return the class number of the smallest class containing | |
476 | reg number REGNO. This could be a conditional expression | |
477 | or could index an array. */ | |
478 | ||
83575957 | 479 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
231ddcb7 RS |
480 | |
481 | /* The class value for index registers, and the one for base regs. */ | |
482 | ||
483 | #define INDEX_REG_CLASS GENERAL_REGS | |
484 | #define BASE_REG_CLASS GEN_AND_MEM_REGS | |
485 | ||
486 | /* Get reg_class from a letter such as appears in the machine description. */ | |
487 | ||
83575957 ID |
488 | #define REG_CLASS_FROM_LETTER(C) \ |
489 | ((C) == 'u' ? FLOAT_REG0 \ | |
490 | : (C) == 'v' ? LONG_FLOAT_REG0 \ | |
491 | : (C) == 'f' ? FLOAT_REGS \ | |
492 | : (C) == 'l' ? FP_REGS \ | |
493 | : (C) == 'x' ? FRAME_POINTER_REG \ | |
494 | : (C) == 'y' ? STACK_POINTER_REG \ | |
231ddcb7 RS |
495 | : NO_REGS) |
496 | ||
497 | /* The letters I, J, K, L and M in a register constraint string | |
498 | can be used to stand for particular ranges of immediate operands. | |
499 | This macro defines what the ranges are. | |
500 | C is the letter, and VALUE is a constant value. | |
501 | Return 1 if VALUE is in the range specified by C. | |
502 | ||
503 | On the ns32k, these letters are used as follows: | |
504 | ||
505 | I : Matches integers which are valid shift amounts for scaled indexing. | |
506 | These are 0, 1, 2, 3 for byte, word, double, and quadword. | |
507 | Used for matching arithmetic shifts only on 32032 & 32332. | |
508 | J : Matches integers which fit a "quick" operand. | |
509 | K : Matches integers 0 to 7 (for inss and exts instructions). | |
510 | */ | |
511 | ||
512 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
513 | ((VALUE) < 8 && (VALUE) + 8 >= 0 ? \ | |
514 | ((C) == 'I' ? (!TARGET_32532 && 0 <= (VALUE) && (VALUE) <= 3) : \ | |
515 | (C) == 'J' ? (VALUE) <= 7 : \ | |
516 | (C) == 'K' ? 0 <= (VALUE) : 0) : 0) | |
517 | ||
518 | /* Similar, but for floating constants, and defining letters G and H. | |
519 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
520 | ||
521 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 | |
522 | ||
523 | /* Given an rtx X being reloaded into a reg required to be | |
524 | in class CLASS, return the class of reg to actually use. | |
525 | In general this is just CLASS; but on some machines | |
526 | in some cases it is preferable to use a more restrictive class. */ | |
527 | ||
1b6c8b12 RS |
528 | /* We return GENERAL_REGS instead of GEN_AND_MEM_REGS. |
529 | The latter offers no real additional possibilities | |
83575957 ID |
530 | and can cause spurious secondary reloading. */ |
531 | ||
1b6c8b12 RS |
532 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
533 | ((CLASS) == GEN_AND_MEM_REGS ? GENERAL_REGS : (CLASS)) | |
231ddcb7 RS |
534 | |
535 | /* Return the maximum number of consecutive registers | |
536 | needed to represent mode MODE in a register of class CLASS. */ | |
537 | /* On the 32000, this is the size of MODE in words */ | |
83575957 | 538 | |
231ddcb7 RS |
539 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
540 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
541 | \f | |
542 | /* Stack layout; function entry, exit and calling. */ | |
543 | ||
544 | /* Define this if pushing a word on the stack | |
545 | makes the stack pointer a smaller address. */ | |
546 | #define STACK_GROWS_DOWNWARD | |
547 | ||
548 | /* Define this if the nominal address of the stack frame | |
549 | is at the high-address end of the local variables; | |
550 | that is, each additional local variable allocated | |
551 | goes at a more negative offset in the frame. */ | |
552 | #define FRAME_GROWS_DOWNWARD | |
553 | ||
554 | /* Offset within stack frame to start allocating local variables at. | |
555 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
556 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
557 | of the first local allocated. */ | |
558 | #define STARTING_FRAME_OFFSET 0 | |
559 | ||
83575957 ID |
560 | /* A C expression whose value is RTL representing the location of the |
561 | incoming return address at the beginning of any function, before | |
562 | the prologue. This RTL is either a `REG', indicating that the | |
563 | return value is saved in `REG', or a `MEM' representing a location | |
564 | in the stack. | |
565 | ||
566 | You only need to define this macro if you want to support call | |
567 | frame debugging information like that provided by DWARF 2. | |
568 | ||
569 | Before the prologue, RA is at 0(sp). */ | |
570 | ||
571 | #define INCOMING_RETURN_ADDR_RTX \ | |
f1c25d3b | 572 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
83575957 ID |
573 | |
574 | /* A C expression whose value is RTL representing the value of the | |
575 | return address for the frame COUNT steps up from the current frame, | |
576 | after the prologue. FRAMEADDR is the frame pointer of the COUNT | |
577 | frame, or the frame pointer of the COUNT - 1 frame if | |
578 | `RETURN_ADDR_IN_PREVIOUS_FRAME' is defined. | |
579 | ||
580 | After the prologue, RA is at 4(fp) in the current frame. */ | |
581 | ||
582 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
ac14c725 | 583 | ((COUNT> 0 && flag_omit_frame_pointer)? NULL_RTX \ |
f1c25d3b | 584 | : gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, (FRAME), GEN_INT(4)))) |
83575957 ID |
585 | |
586 | /* A C expression whose value is an integer giving the offset, in | |
587 | bytes, from the value of the stack pointer register to the top of | |
588 | the stack frame at the beginning of any function, before the | |
589 | prologue. The top of the frame is defined to be the value of the | |
590 | stack pointer in the previous frame, just before the call | |
591 | instruction. | |
592 | ||
593 | You only need to define this macro if you want to support call | |
594 | frame debugging information like that provided by DWARF 2. */ | |
595 | ||
596 | #define INCOMING_FRAME_SP_OFFSET 4 | |
597 | ||
231ddcb7 RS |
598 | /* If we generate an insn to push BYTES bytes, |
599 | this says how many the stack pointer really advances by. | |
600 | On the 32000, sp@- in a byte insn really pushes a BYTE. */ | |
601 | #define PUSH_ROUNDING(BYTES) (BYTES) | |
602 | ||
603 | /* Offset of first parameter from the argument pointer register value. */ | |
604 | #define FIRST_PARM_OFFSET(FNDECL) 8 | |
605 | ||
606 | /* Value is the number of byte of arguments automatically | |
607 | popped when returning from a subroutine call. | |
8b109b37 | 608 | FUNDECL is the declaration node of the function (as a tree), |
231ddcb7 RS |
609 | FUNTYPE is the data type of the function (as a tree), |
610 | or for a library call it is an identifier node for the subroutine name. | |
611 | SIZE is the number of bytes of arguments passed on the stack. | |
612 | ||
613 | On the 32000, the RET insn may be used to pop them if the number | |
614 | of args is fixed, but if the number is variable then the caller | |
615 | must pop them all. RET can't be used for library calls now | |
616 | because the library is compiled with the Unix compiler. | |
617 | Use of RET is a selectable option, since it is incompatible with | |
618 | standard Unix calling sequences. If the option is not selected, | |
83575957 ID |
619 | the caller must always pop the args. |
620 | ||
621 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
231ddcb7 | 622 | |
83575957 ID |
623 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ |
624 | (ns32k_return_pops_args (FUNDECL, FUNTYPE, SIZE)) | |
231ddcb7 RS |
625 | |
626 | /* Define how to find the value returned by a function. | |
627 | VALTYPE is the data type of the value (as a tree). | |
628 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
629 | otherwise, FUNC is 0. */ | |
630 | ||
631 | /* On the 32000 the return value is in R0, | |
83575957 | 632 | or perhaps in F0 if there is fp support. */ |
231ddcb7 | 633 | |
83575957 | 634 | #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE(TYPE_MODE (VALTYPE)) |
231ddcb7 RS |
635 | |
636 | /* Define how to find the value returned by a library function | |
637 | assuming the value has mode MODE. */ | |
638 | ||
639 | /* On the 32000 the return value is in R0, | |
83575957 | 640 | or perhaps F0 is there is fp support. */ |
231ddcb7 RS |
641 | |
642 | #define LIBCALL_VALUE(MODE) \ | |
c5c76735 JL |
643 | gen_rtx_REG (MODE, \ |
644 | FLOAT_MODE_P(MODE) && TARGET_32081 ? F0_REGNUM: R0_REGNUM) | |
231ddcb7 RS |
645 | |
646 | /* Define this if PCC uses the nonreentrant convention for returning | |
647 | structure and union values. */ | |
648 | ||
649 | #define PCC_STATIC_STRUCT_RETURN | |
650 | ||
651 | /* 1 if N is a possible register number for a function value. | |
652 | On the 32000, R0 and F0 are the only registers thus used. */ | |
653 | ||
654 | #define FUNCTION_VALUE_REGNO_P(N) (((N) & ~8) == 0) | |
655 | ||
656 | /* 1 if N is a possible register number for function argument passing. | |
657 | On the 32000, no registers are used in this way. */ | |
658 | ||
659 | #define FUNCTION_ARG_REGNO_P(N) 0 | |
660 | \f | |
661 | /* Define a data type for recording info about an argument list | |
662 | during the scan of that argument list. This data type should | |
663 | hold all necessary information about the function itself | |
664 | and about the args processed so far, enough to enable macros | |
665 | such as FUNCTION_ARG to determine where the next arg should go. | |
666 | ||
667 | On the ns32k, this is a single integer, which is a number of bytes | |
668 | of arguments scanned so far. */ | |
669 | ||
670 | #define CUMULATIVE_ARGS int | |
671 | ||
672 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
673 | for a call to a function whose data type is FNTYPE. | |
674 | For a library call, FNTYPE is 0. | |
675 | ||
676 | On the ns32k, the offset starts at 0. */ | |
677 | ||
2c7ee1a6 | 678 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
231ddcb7 RS |
679 | ((CUM) = 0) |
680 | ||
681 | /* Update the data in CUM to advance over an argument | |
682 | of mode MODE and data type TYPE. | |
683 | (TYPE is null for libcalls where that information may not be available.) */ | |
684 | ||
685 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
686 | ((CUM) += ((MODE) != BLKmode \ | |
687 | ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ | |
688 | : (int_size_in_bytes (TYPE) + 3) & ~3)) | |
689 | ||
690 | /* Define where to put the arguments to a function. | |
691 | Value is zero to push the argument on the stack, | |
692 | or a hard register in which to store the argument. | |
693 | ||
694 | MODE is the argument's machine mode. | |
695 | TYPE is the data type of the argument (as a tree). | |
696 | This is null for libcalls where that information may | |
697 | not be available. | |
698 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
699 | the preceding args and about the function being called. | |
700 | NAMED is nonzero if this argument is a named parameter | |
701 | (otherwise it is an extra parameter matching an ellipsis). */ | |
702 | ||
703 | /* On the 32000 all args are pushed, except if -mregparm is specified | |
704 | then the first two words of arguments are passed in r0, r1. | |
705 | *NOTE* -mregparm does not work. | |
706 | It exists only to test register calling conventions. */ | |
707 | ||
708 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
c5c76735 | 709 | ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0) |
231ddcb7 RS |
710 | |
711 | /* For an arg passed partly in registers and partly in memory, | |
712 | this is the number of registers used. | |
713 | For args passed entirely in registers or entirely in memory, zero. */ | |
714 | ||
715 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
716 | ((TARGET_REGPARM && (CUM) < 8 \ | |
717 | && 8 < ((CUM) + ((MODE) == BLKmode \ | |
718 | ? int_size_in_bytes (TYPE) \ | |
719 | : GET_MODE_SIZE (MODE)))) \ | |
720 | ? 2 - (CUM) / 4 : 0) | |
721 | ||
231ddcb7 RS |
722 | /* Output assembler code to FILE to increment profiler label # LABELNO |
723 | for profiling a function entry. | |
724 | ||
725 | THIS DEFINITION FOR THE 32000 IS A GUESS. IT HAS NOT BEEN TESTED. */ | |
726 | ||
727 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
728 | fprintf (FILE, "\taddr LP%d,r0\n\tbsr mcount\n", (LABELNO)) | |
729 | ||
730 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
731 | the stack pointer does not matter. The value is tested only in | |
732 | functions that have frame pointers. | |
733 | No definition is equivalent to always zero. | |
734 | ||
08c148a8 | 735 | We use 0, because using 1 requires hair in output_function_epilogue() |
231ddcb7 RS |
736 | that is worse than the stack adjust we could save. */ |
737 | ||
738 | /* #define EXIT_IGNORE_STACK 1 */ | |
739 | ||
231ddcb7 RS |
740 | /* Store in the variable DEPTH the initial difference between the |
741 | frame pointer reg contents and the stack pointer reg contents, | |
742 | as of the start of the function body. This depends on the layout | |
743 | of the fixed parts of the stack frame and on how registers are saved. */ | |
744 | ||
745 | #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ | |
746 | { \ | |
747 | int regno; \ | |
748 | int offset = -4; \ | |
ac14c725 | 749 | for (regno = 0; regno < FRAME_POINTER_REGNUM; regno++) \ |
231ddcb7 RS |
750 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ |
751 | offset += 4; \ | |
666b023e RK |
752 | if (flag_pic && current_function_uses_pic_offset_table) \ |
753 | offset += 4; \ | |
7f2ab886 RS |
754 | (DEPTH) = (offset + get_frame_size () \ |
755 | + (get_frame_size () == 0 ? 0 : 4)); \ | |
231ddcb7 RS |
756 | } |
757 | \f | |
758 | ||
759 | /* Output assembler code for a block containing the constant parts | |
760 | of a trampoline, leaving space for the variable parts. */ | |
761 | ||
762 | /* On the 32k, the trampoline looks like this: | |
6cb64c6a | 763 | addr 0(pc),r2 |
231ddcb7 RS |
764 | jump @__trampoline |
765 | .int STATIC | |
766 | .int FUNCTION | |
767 | Doing trampolines with a library assist function is easier than figuring | |
768 | out how to do stores to memory in reverse byte order (the way immediate | |
769 | operands on the 32k are stored). */ | |
770 | ||
771 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
772 | { \ | |
6cb64c6a | 773 | fprintf (FILE, "\taddr 0(pc),r2\n" ); \ |
e2ca2fab RS |
774 | fprintf (FILE, "\tjump " ); \ |
775 | PUT_ABSOLUTE_PREFIX (FILE); \ | |
776 | fprintf (FILE, "__trampoline\n" ); \ | |
301d03af RS |
777 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ |
778 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ | |
231ddcb7 RS |
779 | } |
780 | ||
781 | /* Length in units of the trampoline for entering a nested function. */ | |
782 | ||
783 | #define TRAMPOLINE_SIZE 20 | |
784 | ||
785 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
786 | FNADDR is an RTX for the address of the function's pure code. | |
787 | CXT is an RTX for the static chain value for the function. */ | |
788 | ||
789 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
790 | { \ | |
c5c76735 JL |
791 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), CXT); \ |
792 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), FNADDR); \ | |
231ddcb7 RS |
793 | } |
794 | ||
795 | /* This is the library routine that is used | |
796 | to transfer control from the trampoline | |
797 | to the actual nested function. */ | |
798 | ||
799 | /* The function name __transfer_from_trampoline is not actually used. | |
800 | The function definition just permits use of "asm with operands" | |
801 | (though the operand list is empty). */ | |
802 | #define TRANSFER_FROM_TRAMPOLINE \ | |
803 | void \ | |
804 | __transfer_from_trampoline () \ | |
805 | { \ | |
6cb64c6a RK |
806 | asm (".globl __trampoline"); \ |
807 | asm ("__trampoline:"); \ | |
231ddcb7 | 808 | asm ("movd 16(r2),tos"); \ |
6cb64c6a | 809 | asm ("movd 12(r2),r1"); \ |
b4ac57ab | 810 | asm ("ret 0"); \ |
231ddcb7 | 811 | } |
231ddcb7 RS |
812 | \f |
813 | /* Addressing modes, and classification of registers for them. */ | |
814 | ||
231ddcb7 RS |
815 | /* Macros to check register numbers against specific register classes. */ |
816 | ||
817 | /* These assume that REGNO is a hard or pseudo reg number. | |
818 | They give nonzero only if REGNO is a hard reg of the suitable class | |
819 | or a pseudo reg currently allocated to a suitable hard reg. | |
820 | Since they use reg_renumber, they are safe only once reg_renumber | |
821 | has been allocated, which happens in local-alloc.c. */ | |
822 | ||
823 | /* note that FP and SP cannot be used as an index. What about PC? */ | |
824 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
83575957 | 825 | ((REGNO) < F0_REGNUM || (unsigned)reg_renumber[REGNO] < F0_REGNUM) |
231ddcb7 | 826 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
83575957 | 827 | ((REGNO) < F0_REGNUM || (unsigned)reg_renumber[REGNO] < F0_REGNUM \ |
231ddcb7 RS |
828 | || (REGNO) == FRAME_POINTER_REGNUM || (REGNO) == STACK_POINTER_REGNUM) |
829 | ||
83575957 ID |
830 | #define FP_REG_P(X) \ |
831 | (GET_CODE (X) == REG && REGNO (X) >= F0_REGNUM && REGNO (X) < FRAME_POINTER_REGNUM) | |
231ddcb7 RS |
832 | \f |
833 | /* Maximum number of registers that can appear in a valid memory address. */ | |
834 | ||
835 | #define MAX_REGS_PER_ADDRESS 2 | |
836 | ||
837 | /* Recognize any constant value that is a valid address. | |
838 | This might not work on future ns32k processors as negative | |
839 | displacements are not officially allowed but a mode reserved | |
83575957 ID |
840 | to National. This works on processors up to 32532, though, |
841 | and we don't expect any new ones in the series ;-( */ | |
231ddcb7 RS |
842 | |
843 | #define CONSTANT_ADDRESS_P(X) \ | |
844 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
845 | || GET_CODE (X) == CONST \ | |
846 | || (GET_CODE (X) == CONST_INT \ | |
83575957 | 847 | && NS32K_DISPLACEMENT_P (INTVAL (X)))) |
231ddcb7 RS |
848 | |
849 | #define CONSTANT_ADDRESS_NO_LABEL_P(X) \ | |
850 | (GET_CODE (X) == CONST_INT \ | |
83575957 | 851 | && NS32K_DISPLACEMENT_P (INTVAL (X))) |
231ddcb7 RS |
852 | |
853 | /* Return the register class of a scratch register needed to copy IN into | |
854 | or out of a register in CLASS in MODE. If it can be done directly, | |
855 | NO_REGS is returned. */ | |
856 | ||
857 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
858 | secondary_reload_class (CLASS, MODE, IN) | |
859 | ||
83575957 ID |
860 | /* Certain machines have the property that some registers cannot be |
861 | copied to some other registers without using memory. Define this | |
a0ab749a | 862 | macro on those machines to be a C expression that is nonzero if |
83575957 ID |
863 | objects of mode M in registers of CLASS1 can only be copied to |
864 | registers of class CLASS2 by storing a register of CLASS1 into | |
865 | memory and loading that memory location into a register of CLASS2. | |
866 | ||
867 | On the ns32k, floating point regs can only be loaded through memory | |
868 | ||
869 | The movdf and movsf insns in ns32k.md copy between general and | |
870 | floating registers using the stack. In principle, we could get | |
871 | better code not allowing that case in the constraints and defining | |
872 | SECONDARY_MEMORY_NEEDED in practice, though the stack slots used | |
873 | are not available for optimization. */ | |
874 | ||
875 | #if 0 | |
876 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, M) \ | |
877 | secondary_memory_needed(CLASS1, CLASS2, M) | |
878 | #endif | |
879 | ||
4c54e4e4 | 880 | /* SMALL_REGISTER_CLASSES is a run time option. This should no longer |
2a43945f | 881 | be necessary and should go when we have confidence that we won't run |
4c54e4e4 | 882 | out of spill registers */ |
2eb2901a | 883 | #define SMALL_REGISTER_CLASSES (target_flags & MASK_SRC) |
83575957 ID |
884 | |
885 | /* A C expression whose value is nonzero if pseudos that have been | |
886 | assigned to registers of class CLASS would likely be spilled | |
887 | because registers of CLASS are needed for spill registers. | |
888 | ||
889 | The default definition won't do because class LONG_FLOAT_REG0 has two | |
f5143c46 | 890 | registers which are always accessed as a pair */ |
83575957 ID |
891 | |
892 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
893 | (reg_class_size[(int) (CLASS)] == 1 || (CLASS) == LONG_FLOAT_REG0) | |
894 | ||
895 | ||
231ddcb7 RS |
896 | /* Nonzero if the constant value X is a legitimate general operand. |
897 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
898 | ||
1ed37bfd | 899 | #define LEGITIMATE_CONSTANT_P(X) 1 |
231ddcb7 RS |
900 | |
901 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
902 | and check its validity for a certain class. | |
903 | We have two alternate definitions for each of them. | |
904 | The usual definition accepts all pseudo regs; the other rejects | |
905 | them unless they have been allocated suitable hard regs. | |
906 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
907 | ||
908 | Most source files want to accept pseudo regs in the hope that | |
909 | they will get allocated to the class that the insn wants them to be in. | |
910 | Source files for reload pass need to be strict. | |
911 | After reload, it makes no difference, since pseudo regs have | |
912 | been eliminated by then. */ | |
913 | ||
914 | #ifndef REG_OK_STRICT | |
915 | ||
916 | /* Nonzero if X is a hard reg that can be used as an index | |
917 | or if it is a pseudo reg. */ | |
918 | #define REG_OK_FOR_INDEX_P(X) \ | |
83575957 | 919 | (REGNO (X) < F0_REGNUM || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
231ddcb7 RS |
920 | /* Nonzero if X is a hard reg that can be used as a base reg |
921 | of if it is a pseudo reg. */ | |
83575957 | 922 | #define REG_OK_FOR_BASE_P(X) (REGNO (X) < F0_REGNUM || REGNO (X) >= FRAME_POINTER_REGNUM) |
231ddcb7 RS |
923 | /* Nonzero if X is a floating point reg or a pseudo reg. */ |
924 | ||
925 | #else | |
926 | ||
927 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
928 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
929 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
930 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
931 | ||
932 | #endif | |
933 | \f | |
934 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
935 | that is a valid memory address for an instruction. | |
936 | The MODE argument is the machine mode for the MEM expression | |
937 | that wants to use this address. | |
938 | ||
939 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
940 | ||
941 | /* 1 if X is an address that we could indirect through. */ | |
942 | /***** NOTE ***** There is a bug in the Sequent assembler which fails | |
943 | to fixup addressing information for symbols used as offsets | |
944 | from registers which are not FP or SP (or SB or PC). This | |
945 | makes _x(fp) valid, while _x(r0) is invalid. */ | |
946 | ||
947 | #define INDIRECTABLE_1_ADDRESS_P(X) \ | |
948 | (CONSTANT_ADDRESS_P (X) \ | |
949 | || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
950 | || (GET_CODE (X) == PLUS \ | |
951 | && GET_CODE (XEXP (X, 0)) == REG \ | |
952 | && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ | |
2d33065a | 953 | && ((flag_pic || TARGET_HIMEM) ? \ |
1ed37bfd RK |
954 | CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1)) \ |
955 | : \ | |
956 | CONSTANT_ADDRESS_P (XEXP (X, 1))) \ | |
b8168f0d RS |
957 | && (GET_CODE (X) != CONST_INT || NS32K_DISPLACEMENT_P (INTVAL (X))))) |
958 | ||
959 | /* 1 if integer I will fit in a 4 byte displacement field. | |
960 | Strictly speaking, we can't be sure that a symbol will fit this range. | |
961 | But, in practice, it always will. */ | |
962 | ||
d24eed4d RS |
963 | /* idall@eleceng.adelaide.edu.au says that the 32016 and 32032 |
964 | can handle the full range of displacements--it is only the addresses | |
965 | that have a limited range. So the following was deleted: | |
966 | (((i) <= 16777215 && (i) >= -16777216) | |
967 | || ((TARGET_32532 || TARGET_32332) && ...)) */ | |
50babe84 | 968 | #define NS32K_DISPLACEMENT_P(i) \ |
0b6d0e8b | 969 | ((i) < (1 << 29) && (i) >= - (1 << 29)) |
231ddcb7 | 970 | |
47c95231 | 971 | /* Check for frame pointer or stack pointer. */ |
231ddcb7 | 972 | #define MEM_REG(X) \ |
83575957 ID |
973 | (GET_CODE (X) == REG && (REGNO (X) == FRAME_POINTER_REGNUM \ |
974 | || REGNO(X) == STACK_POINTER_REGNUM)) | |
231ddcb7 | 975 | |
47c95231 RS |
976 | /* A memory ref whose address is the FP or SP, with optional integer offset, |
977 | or (on certain machines) a constant address. */ | |
231ddcb7 RS |
978 | #define INDIRECTABLE_2_ADDRESS_P(X) \ |
979 | (GET_CODE (X) == MEM \ | |
980 | && (((xfoo0 = XEXP (X, 0), MEM_REG (xfoo0)) \ | |
981 | || (GET_CODE (xfoo0) == PLUS \ | |
231ddcb7 RS |
982 | && MEM_REG (XEXP (xfoo0, 0)) \ |
983 | && CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfoo0, 1)))) \ | |
984 | || (TARGET_SB && CONSTANT_ADDRESS_P (xfoo0)))) | |
985 | ||
231ddcb7 RS |
986 | /* Go to ADDR if X is a valid address not using indexing. |
987 | (This much is the easy part.) */ | |
4c54e4e4 ID |
988 | #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ |
989 | { \ | |
990 | if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; \ | |
991 | if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \ | |
992 | if (GET_CODE (X) == PLUS) \ | |
993 | if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1))) \ | |
994 | if (INDIRECTABLE_2_ADDRESS_P (XEXP (X, 0))) \ | |
995 | goto ADDR; \ | |
231ddcb7 RS |
996 | } |
997 | ||
47c95231 RS |
998 | /* Go to ADDR if X is a valid address not using indexing. |
999 | (This much is the easy part.) */ | |
fbaef11f | 1000 | #define GO_IF_INDEXING(X, MODE, ADDR) \ |
47c95231 | 1001 | { register rtx xfoob = (X); \ |
fbaef11f | 1002 | if (GET_CODE (xfoob) == PLUS && INDEX_TERM_P (XEXP (xfoob, 0), MODE)) \ |
47c95231 | 1003 | GO_IF_INDEXABLE_ADDRESS (XEXP (xfoob, 1), ADDR); \ |
fbaef11f | 1004 | if (GET_CODE (xfoob) == PLUS && INDEX_TERM_P (XEXP (xfoob, 1), MODE)) \ |
47c95231 RS |
1005 | GO_IF_INDEXABLE_ADDRESS (XEXP (xfoob, 0), ADDR); } \ |
1006 | ||
1007 | #define GO_IF_INDEXABLE_ADDRESS(X, ADDR) \ | |
1008 | { if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; \ | |
1009 | if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \ | |
1ed37bfd | 1010 | if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; \ |
47c95231 RS |
1011 | } |
1012 | ||
231ddcb7 RS |
1013 | /* 1 if PROD is either a reg times size of mode MODE |
1014 | or just a reg, if MODE is just one byte. Actually, on the ns32k, | |
1015 | since the index mode is independent of the operand size, | |
1016 | we can match more stuff... | |
1017 | ||
1018 | This macro's expansion uses the temporary variables xfoo0, xfoo1 | |
1019 | and xfoo2 that must be declared in the surrounding context. */ | |
1020 | #define INDEX_TERM_P(PROD, MODE) \ | |
1021 | ((GET_CODE (PROD) == REG && REG_OK_FOR_INDEX_P (PROD)) \ | |
1022 | || (GET_CODE (PROD) == MULT \ | |
1023 | && (xfoo0 = XEXP (PROD, 0), xfoo1 = XEXP (PROD, 1), \ | |
1024 | (GET_CODE (xfoo1) == CONST_INT \ | |
1025 | && GET_CODE (xfoo0) == REG \ | |
1026 | && FITS_INDEX_RANGE (INTVAL (xfoo1)) \ | |
1027 | && REG_OK_FOR_INDEX_P (xfoo0))))) | |
1028 | ||
1029 | #define FITS_INDEX_RANGE(X) \ | |
1030 | ((xfoo2 = (unsigned)(X)-1), \ | |
1031 | ((xfoo2 < 4 && xfoo2 != 2) || xfoo2 == 7)) | |
1032 | ||
47c95231 | 1033 | /* Note that xfoo0, xfoo1, xfoo2 are used in some of the submacros above. */ |
4c54e4e4 | 1034 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
47c95231 | 1035 | { register rtx xfooy, xfoo0, xfoo1; \ |
231ddcb7 RS |
1036 | unsigned xfoo2; \ |
1037 | xfooy = X; \ | |
4c54e4e4 | 1038 | if (flag_pic && cfun && ! current_function_uses_pic_offset_table \ |
1ed37bfd | 1039 | && global_symbolic_reference_mentioned_p (X, 1)) \ |
666b023e | 1040 | current_function_uses_pic_offset_table = 1; \ |
231ddcb7 RS |
1041 | GO_IF_NONINDEXED_ADDRESS (xfooy, ADDR); \ |
1042 | if (GET_CODE (xfooy) == PLUS) \ | |
1043 | { \ | |
1044 | if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfooy, 1)) \ | |
1045 | && GET_CODE (XEXP (xfooy, 0)) == PLUS) \ | |
1046 | xfooy = XEXP (xfooy, 0); \ | |
1047 | else if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfooy, 0)) \ | |
1048 | && GET_CODE (XEXP (xfooy, 1)) == PLUS) \ | |
1049 | xfooy = XEXP (xfooy, 1); \ | |
fbaef11f | 1050 | GO_IF_INDEXING (xfooy, MODE, ADDR); \ |
231ddcb7 RS |
1051 | } \ |
1052 | else if (INDEX_TERM_P (xfooy, MODE)) \ | |
1053 | goto ADDR; \ | |
1054 | else if (GET_CODE (xfooy) == PRE_DEC) \ | |
fabf04b6 KG |
1055 | { \ |
1056 | if (REGNO (XEXP (xfooy, 0)) == STACK_POINTER_REGNUM) goto ADDR; \ | |
1057 | } \ | |
231ddcb7 RS |
1058 | } |
1059 | ||
1060 | /* Try machine-dependent ways of modifying an illegitimate address | |
1061 | to be legitimate. If we find one, return the new, valid address. | |
1062 | This macro is used in only one place: `memory_address' in explow.c. | |
1063 | ||
1064 | OLDX is the address as it was before break_out_memory_refs was called. | |
1065 | In some cases it is useful to look at this to decide what needs to be done. | |
1066 | ||
1067 | MODE and WIN are passed so that this macro can use | |
1068 | GO_IF_LEGITIMATE_ADDRESS. | |
1069 | ||
1070 | It is always safe for this macro to do nothing. It exists to recognize | |
1071 | opportunities to optimize the output. | |
1072 | ||
1073 | For the ns32k, we do nothing */ | |
1074 | ||
1075 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} | |
1076 | ||
1ed37bfd | 1077 | /* Nonzero if the constant value X is a legitimate general operand |
83575957 | 1078 | when generating PIC code. It is given that flag_pic is on and |
1ed37bfd RK |
1079 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1080 | ||
1ed37bfd RK |
1081 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1082 | (((! current_function_uses_pic_offset_table \ | |
83575957 | 1083 | && symbolic_reference_mentioned_p (X))? \ |
1ed37bfd | 1084 | (current_function_uses_pic_offset_table = 1):0 \ |
83575957 ID |
1085 | ), (! SYMBOLIC_CONST (X) \ |
1086 | || GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) | |
1087 | ||
1088 | #define SYMBOLIC_CONST(X) \ | |
1089 | (GET_CODE (X) == SYMBOL_REF \ | |
1090 | || GET_CODE (X) == LABEL_REF \ | |
1091 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
1ed37bfd | 1092 | |
231ddcb7 RS |
1093 | /* Go to LABEL if ADDR (a legitimate address expression) |
1094 | has an effect that depends on the machine mode it is used for. | |
1095 | On the ns32k, only predecrement and postincrement address depend thus | |
1096 | (the amount of decrement or increment being the length of the operand). */ | |
1097 | ||
1098 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1099 | { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \ | |
1100 | goto LABEL;} | |
1101 | \f | |
1102 | /* Specify the machine mode that this machine uses | |
1103 | for the index in the tablejump instruction. | |
386d1816 RK |
1104 | HI mode is more efficient but the range is not wide enough for |
1105 | all programs. */ | |
1106 | #define CASE_VECTOR_MODE SImode | |
231ddcb7 | 1107 | |
18543a22 ILT |
1108 | /* Define as C expression which evaluates to nonzero if the tablejump |
1109 | instruction expects the table to contain offsets from the address of the | |
1110 | table. | |
1111 | Do not define this if the table should contain absolute addresses. */ | |
1112 | #define CASE_VECTOR_PC_RELATIVE 1 | |
231ddcb7 | 1113 | |
231ddcb7 RS |
1114 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1115 | #define DEFAULT_SIGNED_CHAR 1 | |
1116 | ||
1117 | /* Max number of bytes we can move from memory to memory | |
1118 | in one reasonably fast instruction. */ | |
1119 | #define MOVE_MAX 4 | |
1120 | ||
83575957 ID |
1121 | /* The number of scalar move insns which should be generated instead |
1122 | of a string move insn or a library call. | |
1123 | ||
1124 | We have a smart movstrsi insn */ | |
1125 | #define MOVE_RATIO 0 | |
1126 | ||
8056c5f2 ID |
1127 | #define STORE_RATIO (optimize_size ? 3 : 15) |
1128 | #define STORE_BY_PIECES_P(SIZE, ALIGN) \ | |
1129 | (move_by_pieces_ninsns (SIZE, ALIGN) < (unsigned int) STORE_RATIO) | |
1130 | ||
1131 | ||
231ddcb7 RS |
1132 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
1133 | #define SLOW_BYTE_ACCESS 0 | |
1134 | ||
1135 | /* Define if shifts truncate the shift count | |
1136 | which implies one can omit a sign-extension or zero-extension | |
1137 | of a shift count. */ | |
1138 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1139 | ||
1140 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1141 | is done just by pretending it is already truncated. */ | |
1142 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1143 | ||
231ddcb7 RS |
1144 | /* Specify the machine mode that pointers have. |
1145 | After generation of rtl, the compiler makes no further distinction | |
1146 | between pointers and any other objects of this machine mode. */ | |
1147 | #define Pmode SImode | |
1148 | ||
1149 | /* A function address in a call instruction | |
1150 | is a byte address (for indexing purposes) | |
1151 | so give the MEM rtx a byte's mode. */ | |
1152 | #define FUNCTION_MODE QImode | |
231ddcb7 RS |
1153 | \f |
1154 | /* Tell final.c how to eliminate redundant test instructions. */ | |
1155 | ||
1156 | /* Here we define machine-dependent flags and fields in cc_status | |
1157 | (see `conditions.h'). */ | |
1158 | ||
1159 | /* This bit means that what ought to be in the Z bit | |
1160 | should be tested in the F bit. */ | |
1161 | #define CC_Z_IN_F 04000 | |
1162 | ||
1163 | /* This bit means that what ought to be in the Z bit | |
1164 | is complemented in the F bit. */ | |
1165 | #define CC_Z_IN_NOT_F 010000 | |
1166 | ||
5d7c2819 ID |
1167 | /* This bit means that the L bit indicates unordered (IEEE) comparison. |
1168 | */ | |
1169 | #define CC_UNORD 020000 | |
1170 | ||
231ddcb7 RS |
1171 | /* Store in cc_status the expressions |
1172 | that the condition codes will describe | |
1173 | after execution of an instruction whose pattern is EXP. | |
1174 | Do not alter them if the instruction would not alter the cc's. */ | |
1175 | ||
1176 | #define NOTICE_UPDATE_CC(EXP, INSN) \ | |
1177 | { if (GET_CODE (EXP) == SET) \ | |
1178 | { if (GET_CODE (SET_DEST (EXP)) == CC0) \ | |
1179 | { cc_status.flags = 0; \ | |
1180 | cc_status.value1 = SET_DEST (EXP); \ | |
1181 | cc_status.value2 = SET_SRC (EXP); \ | |
1182 | } \ | |
1183 | else if (GET_CODE (SET_SRC (EXP)) == CALL) \ | |
1184 | { CC_STATUS_INIT; } \ | |
1185 | else if (GET_CODE (SET_DEST (EXP)) == REG) \ | |
1186 | { if (cc_status.value1 \ | |
1187 | && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \ | |
1188 | cc_status.value1 = 0; \ | |
1189 | if (cc_status.value2 \ | |
1190 | && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \ | |
1191 | cc_status.value2 = 0; \ | |
1192 | } \ | |
1193 | else if (GET_CODE (SET_DEST (EXP)) == MEM) \ | |
1194 | { CC_STATUS_INIT; } \ | |
1195 | } \ | |
1196 | else if (GET_CODE (EXP) == PARALLEL \ | |
1197 | && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ | |
1198 | { if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == CC0) \ | |
1199 | { cc_status.flags = 0; \ | |
1200 | cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0)); \ | |
1201 | cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); \ | |
1202 | } \ | |
1203 | else if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == REG) \ | |
1204 | { if (cc_status.value1 \ | |
1205 | && reg_overlap_mentioned_p (SET_DEST (XVECEXP (EXP, 0, 0)), cc_status.value1)) \ | |
1206 | cc_status.value1 = 0; \ | |
1207 | if (cc_status.value2 \ | |
1208 | && reg_overlap_mentioned_p (SET_DEST (XVECEXP (EXP, 0, 0)), cc_status.value2)) \ | |
1209 | cc_status.value2 = 0; \ | |
1210 | } \ | |
1211 | else if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == MEM) \ | |
1212 | { CC_STATUS_INIT; } \ | |
1213 | } \ | |
1214 | else if (GET_CODE (EXP) == CALL) \ | |
1215 | { /* all bets are off */ CC_STATUS_INIT; } \ | |
1216 | else { /* nothing happens? CC_STATUS_INIT; */} \ | |
1217 | if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ | |
1218 | && cc_status.value2 \ | |
1219 | && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ | |
1220 | abort (); \ | |
1221 | } | |
1222 | ||
1223 | /* Describe the costs of the following register moves which are discouraged: | |
1224 | 1.) Moves between the Floating point registers and the frame pointer and stack pointer | |
1225 | 2.) Moves between the stack pointer and the frame pointer | |
83575957 ID |
1226 | 3.) Moves between the floating point and general registers |
1227 | ||
1228 | These all involve two memory references. This is worse than a memory | |
1229 | to memory move (default cost 4) | |
1230 | */ | |
231ddcb7 | 1231 | |
cf011243 AO |
1232 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
1233 | register_move_cost (CLASS1, CLASS2) | |
231ddcb7 RS |
1234 | |
1235 | #define OUTPUT_JUMP(NORMAL, NO_OV) \ | |
1236 | { if (cc_status.flags & CC_NO_OVERFLOW) \ | |
1237 | return NO_OV; \ | |
1238 | return NORMAL; } | |
1239 | \f | |
1240 | /* Dividing the output into sections */ | |
1241 | ||
1242 | /* Output before read-only data. */ | |
1243 | ||
76bbee81 | 1244 | #define TEXT_SECTION_ASM_OP "\t.text" |
231ddcb7 RS |
1245 | |
1246 | /* Output before writable data. */ | |
1247 | ||
76bbee81 | 1248 | #define DATA_SECTION_ASM_OP "\t.data" |
231ddcb7 RS |
1249 | |
1250 | /* Define the output Assembly Language */ | |
1251 | ||
231ddcb7 RS |
1252 | /* Output to assembler file text saying following lines |
1253 | may contain character constants, extra white space, comments, etc. */ | |
1254 | ||
1255 | #define ASM_APP_ON "#APP\n" | |
1256 | ||
1257 | /* Output to assembler file text saying following lines | |
1258 | no longer contain unusual constructs. */ | |
1259 | ||
1260 | #define ASM_APP_OFF "#NO_APP\n" | |
1261 | ||
1262 | /* Output of Data */ | |
1263 | ||
231ddcb7 RS |
1264 | /* This is how to output an assembler line defining an external/static |
1265 | address which is not in tree format (for collect.c). */ | |
1266 | ||
83575957 ID |
1267 | /* The prefix to add to user-visible assembler symbols. */ |
1268 | #define USER_LABEL_PREFIX "_" | |
231ddcb7 RS |
1269 | |
1270 | /* This is how to output an insn to push a register on the stack. | |
1271 | It need not be very fast code. */ | |
1272 | ||
1273 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
1274 | fprintf (FILE, "\tmovd %s,tos\n", reg_names[REGNO]) | |
1275 | ||
1276 | /* This is how to output an insn to pop a register from the stack. | |
1277 | It need not be very fast code. */ | |
1278 | ||
1279 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
1280 | fprintf (FILE, "\tmovd tos,%s\n", reg_names[REGNO]) | |
1281 | ||
231ddcb7 RS |
1282 | /* This is how to output a command to make the user-level label named NAME |
1283 | defined for reference from other files. */ | |
1284 | ||
506a61b1 KG |
1285 | /* Globalizing directive for a label. */ |
1286 | #define GLOBAL_ASM_OP ".globl " | |
231ddcb7 | 1287 | |
231ddcb7 RS |
1288 | /* This is how to store into the string LABEL |
1289 | the symbol_ref name of an internal numbered label where | |
1290 | PREFIX is the class of label and NUM is the number within the class. | |
1291 | This is suitable for output with `assemble_name'. */ | |
1292 | ||
1293 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
fabf04b6 | 1294 | sprintf (LABEL, "*%s%ld", PREFIX, (long) NUM) |
231ddcb7 | 1295 | |
fc470718 | 1296 | /* This is how to align the code that follows an unconditional branch. */ |
231ddcb7 | 1297 | |
fc470718 | 1298 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (2) |
231ddcb7 RS |
1299 | |
1300 | /* This is how to output an element of a case-vector that is absolute. | |
1301 | (The ns32k does not use such vectors, | |
1302 | but we must define this macro anyway.) */ | |
1303 | ||
1304 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1305 | fprintf (FILE, "\t.long L%d\n", VALUE) | |
1306 | ||
1307 | /* This is how to output an element of a case-vector that is relative. */ | |
a74853cb | 1308 | /* ** Notice that the second element is LI format! */ |
33f7f353 | 1309 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
a74853cb | 1310 | fprintf (FILE, "\t.long L%d-LI%d\n", VALUE, REL) |
231ddcb7 RS |
1311 | |
1312 | /* This is how to output an assembler line | |
1313 | that says to advance the location counter | |
1314 | to a multiple of 2**LOG bytes. */ | |
1315 | ||
1316 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1317 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
1318 | ||
1319 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
58e15542 | 1320 | fprintf (FILE, "\t.space %u\n", (int)(SIZE)) |
231ddcb7 RS |
1321 | |
1322 | /* This says how to output an assembler line | |
1323 | to define a global common symbol. */ | |
1324 | ||
1325 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1326 | ( fputs (".comm ", (FILE)), \ | |
1327 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 1328 | fprintf ((FILE), ",%u\n", (int)(ROUNDED))) |
231ddcb7 RS |
1329 | |
1330 | /* This says how to output an assembler line | |
1331 | to define a local common symbol. */ | |
1332 | ||
1333 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1334 | ( fputs (".lcomm ", (FILE)), \ | |
1335 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 1336 | fprintf ((FILE), ",%u\n", (int)(ROUNDED))) |
231ddcb7 | 1337 | |
231ddcb7 RS |
1338 | /* Print an instruction operand X on file FILE. |
1339 | CODE is the code from the %-spec that requested printing this operand; | |
1340 | if `%z3' was used to print operand 3, then CODE is 'z'. */ | |
1341 | ||
1342 | /* %$ means print the prefix for an immediate operand. */ | |
1343 | ||
1344 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
1345 | ((CODE) == '$' || (CODE) == '?') | |
1346 | ||
1347 | #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) | |
1348 | ||
1349 | /* Print a memory operand whose address is X, on file FILE. */ | |
1350 | ||
1351 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR) | |
1352 | ||
0139adca KG |
1353 | extern const unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1]; |
1354 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smallest class containing REGNO */ | |
231ddcb7 RS |
1355 | |
1356 | /* | |
1357 | Local variables: | |
1358 | version-control: t | |
1359 | End: | |
1360 | */ |