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9304f876 | 1 | /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler |
83ffe9cd | 2 | Copyright (C) 2012-2023 Free Software Foundation, Inc. |
9304f876 CJW |
3 | Contributed by Andes Technology Corporation. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
19ac960a | 21 | /* ------------------------------------------------------------------------ */ |
9304f876 | 22 | |
8fcc61f8 RS |
23 | #define IN_TARGET_CODE 1 |
24 | ||
9304f876 CJW |
25 | #include "config.h" |
26 | #include "system.h" | |
27 | #include "coretypes.h" | |
c7131fb2 | 28 | #include "backend.h" |
e11c4407 | 29 | #include "target.h" |
c7131fb2 | 30 | #include "rtl.h" |
e11c4407 | 31 | #include "tree.h" |
c4d8d050 | 32 | #include "tree-pass.h" |
314e6352 ML |
33 | #include "stringpool.h" |
34 | #include "attribs.h" | |
c7131fb2 | 35 | #include "df.h" |
4d0cdd0c | 36 | #include "memmodel.h" |
e11c4407 AM |
37 | #include "tm_p.h" |
38 | #include "optabs.h" /* For GEN_FCN. */ | |
39 | #include "regs.h" | |
40 | #include "emit-rtl.h" | |
41 | #include "recog.h" | |
42 | #include "diagnostic-core.h" | |
d8a2d370 DN |
43 | #include "stor-layout.h" |
44 | #include "varasm.h" | |
45 | #include "calls.h" | |
9304f876 | 46 | #include "output.h" |
36566b39 | 47 | #include "explow.h" |
9304f876 | 48 | #include "expr.h" |
9304f876 | 49 | #include "tm-constrs.h" |
9b2b7279 | 50 | #include "builtins.h" |
72b7e5e1 | 51 | #include "cpplib.h" |
c4d8d050 | 52 | #include "context.h" |
9304f876 | 53 | |
994c5d85 | 54 | /* This file should be included last. */ |
d58627a0 RS |
55 | #include "target-def.h" |
56 | ||
9304f876 CJW |
57 | /* ------------------------------------------------------------------------ */ |
58 | ||
59 | /* This file is divided into five parts: | |
60 | ||
61 | PART 1: Auxiliary static variable definitions and | |
62 | target hook static variable definitions. | |
63 | ||
64 | PART 2: Auxiliary static function definitions. | |
65 | ||
66 | PART 3: Implement target hook stuff definitions. | |
67 | ||
68 | PART 4: Implemet extern function definitions, | |
69 | the prototype is in nds32-protos.h. | |
70 | ||
71 | PART 5: Initialize target hook structure and definitions. */ | |
72 | ||
73 | /* ------------------------------------------------------------------------ */ | |
74 | ||
75 | /* PART 1: Auxiliary static variable definitions and | |
76 | target hook static variable definitions. */ | |
77 | ||
9304f876 CJW |
78 | /* Define intrinsic register names. |
79 | Please refer to nds32_intrinsic.h file, the index is corresponding to | |
80 | 'enum nds32_intrinsic_registers' data type values. | |
81 | NOTE that the base value starting from 1024. */ | |
82 | static const char * const nds32_intrinsic_register_names[] = | |
83 | { | |
2095a9d5 MC |
84 | "$CPU_VER", |
85 | "$ICM_CFG", | |
86 | "$DCM_CFG", | |
87 | "$MMU_CFG", | |
88 | "$MSC_CFG", | |
89 | "$MSC_CFG2", | |
90 | "$CORE_ID", | |
91 | "$FUCOP_EXIST", | |
92 | ||
93 | "$PSW", | |
94 | "$IPSW", | |
95 | "$P_IPSW", | |
96 | "$IVB", | |
97 | "$EVA", | |
98 | "$P_EVA", | |
99 | "$ITYPE", | |
100 | "$P_ITYPE", | |
101 | ||
102 | "$MERR", | |
103 | "$IPC", | |
104 | "$P_IPC", | |
105 | "$OIPC", | |
106 | "$P_P0", | |
107 | "$P_P1", | |
108 | ||
109 | "$INT_MASK", | |
110 | "$INT_MASK2", | |
111 | "$INT_MASK3", | |
112 | "$INT_PEND", | |
113 | "$INT_PEND2", | |
114 | "$INT_PEND3", | |
115 | "$SP_USR", | |
116 | "$SP_PRIV", | |
117 | "$INT_PRI", | |
118 | "$INT_PRI2", | |
119 | "$INT_PRI3", | |
120 | "$INT_PRI4", | |
121 | "$INT_CTRL", | |
122 | "$INT_TRIGGER", | |
123 | "$INT_TRIGGER2", | |
124 | "$INT_GPR_PUSH_DIS", | |
125 | ||
126 | "$MMU_CTL", | |
127 | "$L1_PPTB", | |
128 | "$TLB_VPN", | |
129 | "$TLB_DATA", | |
130 | "$TLB_MISC", | |
131 | "$VLPT_IDX", | |
132 | "$ILMB", | |
133 | "$DLMB", | |
134 | ||
135 | "$CACHE_CTL", | |
136 | "$HSMP_SADDR", | |
137 | "$HSMP_EADDR", | |
138 | "$SDZ_CTL", | |
139 | "$N12MISC_CTL", | |
140 | "$MISC_CTL", | |
141 | "$ECC_MISC", | |
142 | ||
143 | "$BPC0", | |
144 | "$BPC1", | |
145 | "$BPC2", | |
146 | "$BPC3", | |
147 | "$BPC4", | |
148 | "$BPC5", | |
149 | "$BPC6", | |
150 | "$BPC7", | |
151 | ||
152 | "$BPA0", | |
153 | "$BPA1", | |
154 | "$BPA2", | |
155 | "$BPA3", | |
156 | "$BPA4", | |
157 | "$BPA5", | |
158 | "$BPA6", | |
159 | "$BPA7", | |
160 | ||
161 | "$BPAM0", | |
162 | "$BPAM1", | |
163 | "$BPAM2", | |
164 | "$BPAM3", | |
165 | "$BPAM4", | |
166 | "$BPAM5", | |
167 | "$BPAM6", | |
168 | "$BPAM7", | |
169 | ||
170 | "$BPV0", | |
171 | "$BPV1", | |
172 | "$BPV2", | |
173 | "$BPV3", | |
174 | "$BPV4", | |
175 | "$BPV5", | |
176 | "$BPV6", | |
177 | "$BPV7", | |
178 | ||
179 | "$BPCID0", | |
180 | "$BPCID1", | |
181 | "$BPCID2", | |
182 | "$BPCID3", | |
183 | "$BPCID4", | |
184 | "$BPCID5", | |
185 | "$BPCID6", | |
186 | "$BPCID7", | |
187 | ||
188 | "$EDM_CFG", | |
189 | "$EDMSW", | |
190 | "$EDM_CTL", | |
191 | "$EDM_DTR", | |
192 | "$BPMTC", | |
193 | "$DIMBR", | |
194 | ||
195 | "$TECR0", | |
196 | "$TECR1", | |
197 | "$PFMC0", | |
198 | "$PFMC1", | |
199 | "$PFMC2", | |
200 | "$PFM_CTL", | |
201 | "$PFT_CTL", | |
202 | "$HSP_CTL", | |
203 | "$SP_BOUND", | |
204 | "$SP_BOUND_PRIV", | |
205 | "$SP_BASE", | |
206 | "$SP_BASE_PRIV", | |
207 | "$FUCOP_CTL", | |
208 | "$PRUSR_ACC_CTL", | |
209 | ||
210 | "$DMA_CFG", | |
211 | "$DMA_GCSW", | |
212 | "$DMA_CHNSEL", | |
213 | "$DMA_ACT", | |
214 | "$DMA_SETUP", | |
215 | "$DMA_ISADDR", | |
216 | "$DMA_ESADDR", | |
217 | "$DMA_TCNT", | |
218 | "$DMA_STATUS", | |
219 | "$DMA_2DSET", | |
220 | "$DMA_2DSCTL", | |
221 | "$DMA_RCNT", | |
222 | "$DMA_HSTATUS", | |
223 | ||
224 | "$PC", | |
225 | "$SP_USR1", | |
226 | "$SP_USR2", | |
227 | "$SP_USR3", | |
228 | "$SP_PRIV1", | |
229 | "$SP_PRIV2", | |
230 | "$SP_PRIV3", | |
231 | "$BG_REGION", | |
232 | "$SFCR", | |
233 | "$SIGN", | |
234 | "$ISIGN", | |
235 | "$P_ISIGN", | |
236 | "$IFC_LP", | |
237 | "$ITB" | |
9304f876 CJW |
238 | }; |
239 | ||
f1a0afe2 MC |
240 | /* Define instrinsic cctl names. */ |
241 | static const char * const nds32_cctl_names[] = | |
242 | { | |
243 | "L1D_VA_FILLCK", | |
244 | "L1D_VA_ULCK", | |
245 | "L1I_VA_FILLCK", | |
246 | "L1I_VA_ULCK", | |
247 | ||
248 | "L1D_IX_WBINVAL", | |
249 | "L1D_IX_INVAL", | |
250 | "L1D_IX_WB", | |
251 | "L1I_IX_INVAL", | |
252 | ||
253 | "L1D_VA_INVAL", | |
254 | "L1D_VA_WB", | |
255 | "L1D_VA_WBINVAL", | |
256 | "L1I_VA_INVAL", | |
257 | ||
258 | "L1D_IX_RTAG", | |
259 | "L1D_IX_RWD", | |
260 | "L1I_IX_RTAG", | |
261 | "L1I_IX_RWD", | |
262 | ||
263 | "L1D_IX_WTAG", | |
264 | "L1D_IX_WWD", | |
265 | "L1I_IX_WTAG", | |
266 | "L1I_IX_WWD" | |
267 | }; | |
5e6ae0cc | 268 | |
57aaf0cc MC |
269 | static const char * const nds32_dpref_names[] = |
270 | { | |
271 | "SRD", | |
272 | "MRD", | |
273 | "SWR", | |
274 | "MWR", | |
275 | "PTE", | |
276 | "CLWR" | |
277 | }; | |
278 | ||
5e6ae0cc CJW |
279 | /* Defining register allocation order for performance. |
280 | We want to allocate callee-saved registers after others. | |
281 | It may be used by nds32_adjust_reg_alloc_order(). */ | |
282 | static const int nds32_reg_alloc_order_for_speed[] = | |
283 | { | |
284 | 0, 1, 2, 3, 4, 5, 16, 17, | |
285 | 18, 19, 20, 21, 22, 23, 24, 25, | |
286 | 26, 27, 6, 7, 8, 9, 10, 11, | |
287 | 12, 13, 14, 15 | |
288 | }; | |
289 | ||
9304f876 | 290 | /* Defining target-specific uses of __attribute__. */ |
7fa24687 | 291 | TARGET_GNU_ATTRIBUTES (nds32_attribute_table, |
9304f876 CJW |
292 | { |
293 | /* Syntax: { name, min_len, max_len, decl_required, type_required, | |
4849deb1 JJ |
294 | function_type_required, affects_type_identity, handler, |
295 | exclude } */ | |
9304f876 CJW |
296 | |
297 | /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */ | |
4849deb1 | 298 | { "interrupt", 1, 64, false, false, false, false, NULL, NULL }, |
9304f876 | 299 | /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */ |
4849deb1 | 300 | { "exception", 1, 8, false, false, false, false, NULL, NULL }, |
9304f876 | 301 | /* Argument is user's interrupt numbers. The vector number is always 0. */ |
4849deb1 | 302 | { "reset", 1, 1, false, false, false, false, NULL, NULL }, |
9304f876 CJW |
303 | |
304 | /* The attributes describing isr nested type. */ | |
4849deb1 JJ |
305 | { "nested", 0, 0, false, false, false, false, NULL, NULL }, |
306 | { "not_nested", 0, 0, false, false, false, false, NULL, NULL }, | |
307 | { "nested_ready", 0, 0, false, false, false, false, NULL, NULL }, | |
a4931745 | 308 | { "critical", 0, 0, false, false, false, false, NULL, NULL }, |
9304f876 CJW |
309 | |
310 | /* The attributes describing isr register save scheme. */ | |
4849deb1 JJ |
311 | { "save_all", 0, 0, false, false, false, false, NULL, NULL }, |
312 | { "partial_save", 0, 0, false, false, false, false, NULL, NULL }, | |
9304f876 CJW |
313 | |
314 | /* The attributes used by reset attribute. */ | |
4849deb1 JJ |
315 | { "nmi", 1, 1, false, false, false, false, NULL, NULL }, |
316 | { "warm", 1, 1, false, false, false, false, NULL, NULL }, | |
9304f876 | 317 | |
a4931745 CJW |
318 | /* The attributes describing isr security level. */ |
319 | { "secure", 1, 1, false, false, false, false, NULL, NULL }, | |
320 | ||
9304f876 | 321 | /* The attribute telling no prologue/epilogue. */ |
4849deb1 | 322 | { "naked", 0, 0, false, false, false, false, NULL, NULL }, |
9304f876 | 323 | |
85a98076 KLC |
324 | /* The attribute is used to tell this function to be ROM patch. */ |
325 | { "indirect_call",0, 0, false, false, false, false, NULL, NULL }, | |
326 | ||
54c537e6 CJW |
327 | /* FOR BACKWARD COMPATIBILITY, |
328 | this attribute also tells no prologue/epilogue. */ | |
7fa24687 RS |
329 | { "no_prologue", 0, 0, false, false, false, false, NULL, NULL } |
330 | }); | |
9304f876 CJW |
331 | |
332 | ||
333 | /* ------------------------------------------------------------------------ */ | |
334 | ||
335 | /* PART 2: Auxiliary static function definitions. */ | |
336 | ||
337 | /* Function to save and restore machine-specific function data. */ | |
338 | static struct machine_function * | |
339 | nds32_init_machine_status (void) | |
340 | { | |
341 | struct machine_function *machine; | |
766090c2 | 342 | machine = ggc_cleared_alloc<machine_function> (); |
9304f876 | 343 | |
ca3a4a55 CJW |
344 | /* Initially assume this function does not use __builtin_eh_return. */ |
345 | machine->use_eh_return_p = 0; | |
346 | ||
9304f876 CJW |
347 | /* Initially assume this function needs prologue/epilogue. */ |
348 | machine->naked_p = 0; | |
349 | ||
350 | /* Initially assume this function does NOT use fp_as_gp optimization. */ | |
351 | machine->fp_as_gp_p = 0; | |
352 | ||
5f2a98c3 CJW |
353 | /* Initially this function is not under strictly aligned situation. */ |
354 | machine->strict_aligned_p = 0; | |
355 | ||
54c537e6 CJW |
356 | /* Initially this function has no naked and no_prologue attributes. */ |
357 | machine->attr_naked_p = 0; | |
358 | machine->attr_no_prologue_p = 0; | |
359 | ||
9304f876 CJW |
360 | return machine; |
361 | } | |
362 | ||
363 | /* Function to compute stack frame size and | |
364 | store into cfun->machine structure. */ | |
365 | static void | |
366 | nds32_compute_stack_frame (void) | |
367 | { | |
368 | int r; | |
369 | int block_size; | |
a6c7e777 | 370 | bool v3pushpop_p; |
9304f876 CJW |
371 | |
372 | /* Because nds32_compute_stack_frame() will be called from different place, | |
373 | everytime we enter this function, we have to assume this function | |
374 | needs prologue/epilogue. */ | |
375 | cfun->machine->naked_p = 0; | |
376 | ||
54c537e6 CJW |
377 | /* We need to mark whether this function has naked and no_prologue |
378 | attribute so that we can distinguish the difference if users applies | |
379 | -mret-in-naked-func option. */ | |
380 | cfun->machine->attr_naked_p | |
381 | = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) | |
382 | ? 1 : 0; | |
383 | cfun->machine->attr_no_prologue_p | |
384 | = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) | |
385 | ? 1 : 0; | |
ca3a4a55 CJW |
386 | |
387 | /* If __builtin_eh_return is used, we better have frame pointer needed | |
388 | so that we can easily locate the stack slot of return address. */ | |
389 | if (crtl->calls_eh_return) | |
390 | { | |
391 | frame_pointer_needed = 1; | |
392 | ||
393 | /* We need to mark eh data registers that need to be saved | |
394 | in the stack. */ | |
395 | cfun->machine->eh_return_data_first_regno = EH_RETURN_DATA_REGNO (0); | |
396 | for (r = 0; EH_RETURN_DATA_REGNO (r) != INVALID_REGNUM; r++) | |
397 | cfun->machine->eh_return_data_last_regno = r; | |
398 | ||
399 | cfun->machine->eh_return_data_regs_size | |
400 | = 4 * (cfun->machine->eh_return_data_last_regno | |
401 | - cfun->machine->eh_return_data_first_regno | |
402 | + 1); | |
403 | cfun->machine->use_eh_return_p = 1; | |
404 | } | |
405 | else | |
406 | { | |
407 | /* Assigning SP_REGNUM to eh_first_regno and eh_last_regno means we | |
408 | do not need to handle __builtin_eh_return case in this function. */ | |
409 | cfun->machine->eh_return_data_first_regno = SP_REGNUM; | |
410 | cfun->machine->eh_return_data_last_regno = SP_REGNUM; | |
411 | ||
412 | cfun->machine->eh_return_data_regs_size = 0; | |
413 | cfun->machine->use_eh_return_p = 0; | |
414 | } | |
415 | ||
9304f876 | 416 | /* Get variadic arguments size to prepare pretend arguments and |
35da54a6 CJW |
417 | we will push them into stack at prologue by ourself. */ |
418 | cfun->machine->va_args_size = crtl->args.pretend_args_size; | |
419 | if (cfun->machine->va_args_size != 0) | |
420 | { | |
421 | cfun->machine->va_args_first_regno | |
8a498f99 CJW |
422 | = NDS32_GPR_ARG_FIRST_REGNUM |
423 | + NDS32_MAX_GPR_REGS_FOR_ARGS | |
424 | - (crtl->args.pretend_args_size / UNITS_PER_WORD); | |
35da54a6 | 425 | cfun->machine->va_args_last_regno |
8a498f99 | 426 | = NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - 1; |
35da54a6 CJW |
427 | } |
428 | else | |
429 | { | |
430 | cfun->machine->va_args_first_regno = SP_REGNUM; | |
431 | cfun->machine->va_args_last_regno = SP_REGNUM; | |
432 | } | |
433 | ||
434 | /* Important: We need to make sure that varargs area is 8-byte alignment. */ | |
435 | block_size = cfun->machine->va_args_size; | |
436 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) | |
437 | { | |
438 | cfun->machine->va_args_area_padding_bytes | |
439 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; | |
440 | } | |
9304f876 CJW |
441 | |
442 | /* Get local variables, incoming variables, and temporary variables size. | |
443 | Note that we need to make sure it is 8-byte alignment because | |
444 | there may be no padding bytes if we are using LRA. */ | |
445 | cfun->machine->local_size = NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ()); | |
446 | ||
447 | /* Get outgoing arguments size. */ | |
448 | cfun->machine->out_args_size = crtl->outgoing_args_size; | |
449 | ||
450 | /* If $fp value is required to be saved on stack, it needs 4 bytes space. | |
451 | Check whether $fp is ever live. */ | |
452 | cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0; | |
453 | ||
454 | /* If $gp value is required to be saved on stack, it needs 4 bytes space. | |
455 | Check whether we are using PIC code genration. */ | |
b26fa4f9 KLC |
456 | cfun->machine->gp_size = |
457 | (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ? 4 : 0; | |
9304f876 CJW |
458 | |
459 | /* If $lp value is required to be saved on stack, it needs 4 bytes space. | |
460 | Check whether $lp is ever live. */ | |
13116651 CJW |
461 | cfun->machine->lp_size |
462 | = (flag_always_save_lp || df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0; | |
9304f876 CJW |
463 | |
464 | /* Initially there is no padding bytes. */ | |
c457f751 | 465 | cfun->machine->callee_saved_area_gpr_padding_bytes = 0; |
9304f876 CJW |
466 | |
467 | /* Calculate the bytes of saving callee-saved registers on stack. */ | |
c457f751 CJW |
468 | cfun->machine->callee_saved_gpr_regs_size = 0; |
469 | cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM; | |
470 | cfun->machine->callee_saved_last_gpr_regno = SP_REGNUM; | |
e2286268 MC |
471 | cfun->machine->callee_saved_fpr_regs_size = 0; |
472 | cfun->machine->callee_saved_first_fpr_regno = SP_REGNUM; | |
473 | cfun->machine->callee_saved_last_fpr_regno = SP_REGNUM; | |
474 | ||
9304f876 CJW |
475 | /* Currently, there is no need to check $r28~$r31 |
476 | because we will save them in another way. */ | |
477 | for (r = 0; r < 28; r++) | |
478 | { | |
479 | if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) | |
480 | { | |
481 | /* Mark the first required callee-saved register | |
482 | (only need to set it once). | |
483 | If first regno == SP_REGNUM, we can tell that | |
484 | it is the first time to be here. */ | |
c457f751 CJW |
485 | if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) |
486 | cfun->machine->callee_saved_first_gpr_regno = r; | |
9304f876 | 487 | /* Mark the last required callee-saved register. */ |
c457f751 | 488 | cfun->machine->callee_saved_last_gpr_regno = r; |
9304f876 CJW |
489 | } |
490 | } | |
491 | ||
e2286268 MC |
492 | /* Recording fpu callee-saved register. */ |
493 | if (TARGET_HARD_FLOAT) | |
494 | { | |
495 | for (r = NDS32_FIRST_FPR_REGNUM; r < NDS32_LAST_FPR_REGNUM; r++) | |
496 | { | |
497 | if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) | |
498 | { | |
499 | /* Mark the first required callee-saved register. */ | |
500 | if (cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM) | |
501 | { | |
502 | /* Make first callee-saved number is even, | |
503 | bacause we use doubleword access, and this way | |
504 | promise 8-byte alignemt. */ | |
505 | if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r)) | |
506 | cfun->machine->callee_saved_first_fpr_regno = r - 1; | |
507 | else | |
508 | cfun->machine->callee_saved_first_fpr_regno = r; | |
509 | } | |
510 | cfun->machine->callee_saved_last_fpr_regno = r; | |
511 | } | |
512 | } | |
513 | ||
514 | /* Make last callee-saved register number is odd, | |
515 | we hope callee-saved register is even. */ | |
516 | int last_fpr = cfun->machine->callee_saved_last_fpr_regno; | |
517 | if (NDS32_FPR_REGNO_OK_FOR_DOUBLE (last_fpr)) | |
518 | cfun->machine->callee_saved_last_fpr_regno++; | |
519 | } | |
520 | ||
9304f876 | 521 | /* Check if this function can omit prologue/epilogue code fragment. |
a4931745 | 522 | If there is 'no_prologue'/'naked'/'secure' attribute in this function, |
9304f876 CJW |
523 | we can set 'naked_p' flag to indicate that |
524 | we do not have to generate prologue/epilogue. | |
525 | Or, if all the following conditions succeed, | |
526 | we can set this function 'naked_p' as well: | |
527 | condition 1: first_regno == last_regno == SP_REGNUM, | |
8a498f99 CJW |
528 | which means we do not have to save |
529 | any callee-saved registers. | |
9304f876 | 530 | condition 2: Both $lp and $fp are NOT live in this function, |
8a498f99 CJW |
531 | which means we do not need to save them and there |
532 | is no outgoing size. | |
9304f876 | 533 | condition 3: There is no local_size, which means |
8a498f99 | 534 | we do not need to adjust $sp. */ |
54c537e6 CJW |
535 | if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) |
536 | || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) | |
a4931745 | 537 | || lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl)) |
c457f751 CJW |
538 | || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM |
539 | && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM | |
e2286268 MC |
540 | && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM |
541 | && cfun->machine->callee_saved_last_fpr_regno == SP_REGNUM | |
9304f876 CJW |
542 | && !df_regs_ever_live_p (FP_REGNUM) |
543 | && !df_regs_ever_live_p (LP_REGNUM) | |
b26fa4f9 KLC |
544 | && cfun->machine->local_size == 0 |
545 | && !flag_pic)) | |
9304f876 | 546 | { |
2da1e7c0 | 547 | /* Set this function 'naked_p' and other functions can check this flag. |
8a498f99 CJW |
548 | Note that in nds32 port, the 'naked_p = 1' JUST means there is no |
549 | callee-saved, local size, and outgoing size. | |
550 | The varargs space and ret instruction may still present in | |
551 | the prologue/epilogue expanding. */ | |
9304f876 CJW |
552 | cfun->machine->naked_p = 1; |
553 | ||
554 | /* No need to save $fp, $gp, and $lp. | |
8a498f99 CJW |
555 | We should set these value to be zero |
556 | so that nds32_initial_elimination_offset() can work properly. */ | |
9304f876 CJW |
557 | cfun->machine->fp_size = 0; |
558 | cfun->machine->gp_size = 0; | |
559 | cfun->machine->lp_size = 0; | |
560 | ||
561 | /* If stack usage computation is required, | |
8a498f99 | 562 | we need to provide the static stack size. */ |
9304f876 CJW |
563 | if (flag_stack_usage_info) |
564 | current_function_static_stack_size = 0; | |
565 | ||
566 | /* No need to do following adjustment, return immediately. */ | |
567 | return; | |
568 | } | |
569 | ||
a6c7e777 MC |
570 | v3pushpop_p = NDS32_V3PUSH_AVAILABLE_P; |
571 | ||
9304f876 CJW |
572 | /* Adjustment for v3push instructions: |
573 | If we are using v3push (push25/pop25) instructions, | |
574 | we need to make sure Rb is $r6 and Re is | |
575 | located on $r6, $r8, $r10, or $r14. | |
576 | Some results above will be discarded and recomputed. | |
2da1e7c0 CJW |
577 | Note that it is only available under V3/V3M ISA and we |
578 | DO NOT setup following stuff for isr or variadic function. */ | |
a6c7e777 | 579 | if (v3pushpop_p) |
9304f876 CJW |
580 | { |
581 | /* Recompute: | |
8a498f99 CJW |
582 | cfun->machine->fp_size |
583 | cfun->machine->gp_size | |
584 | cfun->machine->lp_size | |
585 | cfun->machine->callee_saved_first_gpr_regno | |
586 | cfun->machine->callee_saved_last_gpr_regno */ | |
9304f876 CJW |
587 | |
588 | /* For v3push instructions, $fp, $gp, and $lp are always saved. */ | |
589 | cfun->machine->fp_size = 4; | |
590 | cfun->machine->gp_size = 4; | |
591 | cfun->machine->lp_size = 4; | |
592 | ||
593 | /* Remember to set Rb = $r6. */ | |
c457f751 | 594 | cfun->machine->callee_saved_first_gpr_regno = 6; |
9304f876 | 595 | |
c457f751 | 596 | if (cfun->machine->callee_saved_last_gpr_regno <= 6) |
9304f876 CJW |
597 | { |
598 | /* Re = $r6 */ | |
c457f751 | 599 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 | 600 | } |
c457f751 | 601 | else if (cfun->machine->callee_saved_last_gpr_regno <= 8) |
9304f876 CJW |
602 | { |
603 | /* Re = $r8 */ | |
c457f751 | 604 | cfun->machine->callee_saved_last_gpr_regno = 8; |
9304f876 | 605 | } |
c457f751 | 606 | else if (cfun->machine->callee_saved_last_gpr_regno <= 10) |
9304f876 CJW |
607 | { |
608 | /* Re = $r10 */ | |
c457f751 | 609 | cfun->machine->callee_saved_last_gpr_regno = 10; |
9304f876 | 610 | } |
c457f751 | 611 | else if (cfun->machine->callee_saved_last_gpr_regno <= 14) |
9304f876 CJW |
612 | { |
613 | /* Re = $r14 */ | |
c457f751 | 614 | cfun->machine->callee_saved_last_gpr_regno = 14; |
9304f876 | 615 | } |
c457f751 | 616 | else if (cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM) |
9304f876 CJW |
617 | { |
618 | /* If last_regno is SP_REGNUM, which means | |
619 | it is never changed, so set it to Re = $r6. */ | |
c457f751 | 620 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 CJW |
621 | } |
622 | else | |
623 | { | |
624 | /* The program flow should not go here. */ | |
625 | gcc_unreachable (); | |
626 | } | |
627 | } | |
628 | ||
a6c7e777 MC |
629 | int sp_adjust = cfun->machine->local_size |
630 | + cfun->machine->out_args_size | |
e2286268 MC |
631 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
632 | + cfun->machine->callee_saved_fpr_regs_size; | |
a6c7e777 MC |
633 | |
634 | if (!v3pushpop_p | |
635 | && sp_adjust == 0 | |
636 | && !frame_pointer_needed) | |
637 | { | |
638 | block_size = cfun->machine->fp_size | |
639 | + cfun->machine->gp_size | |
361292be CJW |
640 | + cfun->machine->lp_size; |
641 | ||
642 | if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) | |
643 | block_size += (4 * (cfun->machine->callee_saved_last_gpr_regno | |
644 | - cfun->machine->callee_saved_first_gpr_regno | |
645 | + 1)); | |
a6c7e777 MC |
646 | |
647 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) | |
648 | { | |
649 | /* $r14 is last callee save register. */ | |
650 | if (cfun->machine->callee_saved_last_gpr_regno | |
651 | < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM) | |
652 | { | |
653 | cfun->machine->callee_saved_last_gpr_regno++; | |
654 | } | |
655 | else if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) | |
656 | { | |
657 | cfun->machine->callee_saved_first_gpr_regno | |
658 | = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; | |
659 | cfun->machine->callee_saved_last_gpr_regno | |
660 | = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; | |
661 | } | |
662 | } | |
663 | } | |
664 | ||
8a498f99 CJW |
665 | /* We have correctly set callee_saved_first_gpr_regno |
666 | and callee_saved_last_gpr_regno. | |
667 | Initially, the callee_saved_gpr_regs_size is supposed to be 0. | |
668 | As long as callee_saved_last_gpr_regno is not SP_REGNUM, | |
669 | we can update callee_saved_gpr_regs_size with new size. */ | |
c457f751 | 670 | if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) |
9304f876 CJW |
671 | { |
672 | /* Compute pushed size of callee-saved registers. */ | |
c457f751 CJW |
673 | cfun->machine->callee_saved_gpr_regs_size |
674 | = 4 * (cfun->machine->callee_saved_last_gpr_regno | |
675 | - cfun->machine->callee_saved_first_gpr_regno | |
9304f876 CJW |
676 | + 1); |
677 | } | |
678 | ||
e2286268 MC |
679 | if (TARGET_HARD_FLOAT) |
680 | { | |
681 | /* Compute size of callee svaed floating-point registers. */ | |
682 | if (cfun->machine->callee_saved_last_fpr_regno != SP_REGNUM) | |
683 | { | |
684 | cfun->machine->callee_saved_fpr_regs_size | |
685 | = 4 * (cfun->machine->callee_saved_last_fpr_regno | |
686 | - cfun->machine->callee_saved_first_fpr_regno | |
687 | + 1); | |
688 | } | |
689 | } | |
690 | ||
9304f876 | 691 | /* Important: We need to make sure that |
8a498f99 CJW |
692 | (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size) |
693 | is 8-byte alignment. | |
694 | If it is not, calculate the padding bytes. */ | |
35da54a6 | 695 | block_size = cfun->machine->fp_size |
9304f876 CJW |
696 | + cfun->machine->gp_size |
697 | + cfun->machine->lp_size | |
c457f751 | 698 | + cfun->machine->callee_saved_gpr_regs_size; |
9304f876 CJW |
699 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) |
700 | { | |
c457f751 | 701 | cfun->machine->callee_saved_area_gpr_padding_bytes |
9304f876 CJW |
702 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; |
703 | } | |
704 | ||
705 | /* If stack usage computation is required, | |
706 | we need to provide the static stack size. */ | |
707 | if (flag_stack_usage_info) | |
708 | { | |
709 | current_function_static_stack_size | |
710 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) | |
711 | + cfun->machine->local_size | |
712 | + cfun->machine->out_args_size; | |
713 | } | |
714 | } | |
715 | ||
716 | /* Function to create a parallel rtx pattern | |
717 | which presents stack push multiple behavior. | |
718 | The overall concept are: | |
719 | "push registers to memory", | |
720 | "adjust stack pointer". */ | |
4e9a2848 | 721 | static void |
a6c7e777 MC |
722 | nds32_emit_stack_push_multiple (unsigned Rb, unsigned Re, |
723 | bool save_fp_p, bool save_gp_p, bool save_lp_p, | |
724 | bool vaarg_p) | |
9304f876 | 725 | { |
a6c7e777 | 726 | unsigned regno; |
9304f876 CJW |
727 | int extra_count; |
728 | int num_use_regs; | |
729 | int par_index; | |
730 | int offset; | |
731 | ||
732 | rtx reg; | |
733 | rtx mem; | |
734 | rtx push_rtx; | |
735 | rtx adjust_sp_rtx; | |
736 | rtx parallel_insn; | |
47e0e7d2 | 737 | rtx dwarf; |
9304f876 CJW |
738 | |
739 | /* We need to provide a customized rtx which contains | |
740 | necessary information for data analysis, | |
741 | so we create a parallel rtx like this: | |
742 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) | |
8a498f99 CJW |
743 | (reg:SI Rb)) |
744 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
745 | (reg:SI Rb+1)) | |
746 | ... | |
747 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
748 | (reg:SI Re)) | |
749 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
750 | (reg:SI FP_REGNUM)) | |
751 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
752 | (reg:SI GP_REGNUM)) | |
753 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
754 | (reg:SI LP_REGNUM)) | |
755 | (set (reg:SI SP_REGNUM) | |
756 | (plus (reg:SI SP_REGNUM) (const_int -32)))]) */ | |
9304f876 CJW |
757 | |
758 | /* Calculate the number of registers that will be pushed. */ | |
759 | extra_count = 0; | |
a6c7e777 | 760 | if (save_fp_p) |
9304f876 | 761 | extra_count++; |
a6c7e777 | 762 | if (save_gp_p) |
9304f876 | 763 | extra_count++; |
a6c7e777 | 764 | if (save_lp_p) |
9304f876 CJW |
765 | extra_count++; |
766 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
a6c7e777 | 767 | if (Rb == SP_REGNUM && Re == SP_REGNUM) |
9304f876 CJW |
768 | num_use_regs = extra_count; |
769 | else | |
a6c7e777 | 770 | num_use_regs = Re - Rb + 1 + extra_count; |
9304f876 CJW |
771 | |
772 | /* In addition to used registers, | |
773 | we need one more space for (set sp sp-x) rtx. */ | |
774 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
775 | rtvec_alloc (num_use_regs + 1)); | |
776 | par_index = 0; | |
777 | ||
778 | /* Initialize offset and start to create push behavior. */ | |
779 | offset = -(num_use_regs * 4); | |
780 | ||
781 | /* Create (set mem regX) from Rb, Rb+1 up to Re. */ | |
a6c7e777 | 782 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
783 | { |
784 | /* Rb and Re may be SP_REGNUM. | |
8a498f99 | 785 | We need to break this loop immediately. */ |
9304f876 | 786 | if (regno == SP_REGNUM) |
4e9a2848 | 787 | break; |
9304f876 CJW |
788 | |
789 | reg = gen_rtx_REG (SImode, regno); | |
790 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
791 | stack_pointer_rtx, | |
792 | offset)); | |
f7df4a84 | 793 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
794 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
795 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
796 | offset = offset + 4; | |
797 | par_index++; | |
798 | } | |
799 | ||
800 | /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */ | |
a6c7e777 | 801 | if (save_fp_p) |
9304f876 CJW |
802 | { |
803 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
804 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
805 | stack_pointer_rtx, | |
806 | offset)); | |
f7df4a84 | 807 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
808 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
809 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
810 | offset = offset + 4; | |
811 | par_index++; | |
812 | } | |
a6c7e777 | 813 | if (save_gp_p) |
9304f876 CJW |
814 | { |
815 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
816 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
817 | stack_pointer_rtx, | |
818 | offset)); | |
f7df4a84 | 819 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
820 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
821 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
822 | offset = offset + 4; | |
823 | par_index++; | |
824 | } | |
a6c7e777 | 825 | if (save_lp_p) |
9304f876 CJW |
826 | { |
827 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
828 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
829 | stack_pointer_rtx, | |
830 | offset)); | |
f7df4a84 | 831 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
832 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
833 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
834 | offset = offset + 4; | |
835 | par_index++; | |
836 | } | |
837 | ||
838 | /* Create (set sp sp-x). */ | |
839 | ||
840 | /* We need to re-calculate the offset value again for adjustment. */ | |
841 | offset = -(num_use_regs * 4); | |
842 | adjust_sp_rtx | |
f7df4a84 | 843 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
844 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
845 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
846 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
847 | ||
4e9a2848 CJW |
848 | parallel_insn = emit_insn (parallel_insn); |
849 | ||
850 | /* The insn rtx 'parallel_insn' will change frame layout. | |
851 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
852 | generate CFI (Call Frame Information) stuff. */ | |
853 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
47e0e7d2 CJW |
854 | |
855 | /* Don't use GCC's logic for CFI info if we are generate a push for VAARG | |
856 | since we will not restore those register at epilogue. */ | |
857 | if (vaarg_p) | |
858 | { | |
859 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, | |
860 | copy_rtx (adjust_sp_rtx), NULL_RTX); | |
861 | REG_NOTES (parallel_insn) = dwarf; | |
862 | } | |
9304f876 CJW |
863 | } |
864 | ||
865 | /* Function to create a parallel rtx pattern | |
866 | which presents stack pop multiple behavior. | |
867 | The overall concept are: | |
868 | "pop registers from memory", | |
869 | "adjust stack pointer". */ | |
4e9a2848 | 870 | static void |
a6c7e777 MC |
871 | nds32_emit_stack_pop_multiple (unsigned Rb, unsigned Re, |
872 | bool save_fp_p, bool save_gp_p, bool save_lp_p) | |
9304f876 | 873 | { |
a6c7e777 | 874 | unsigned regno; |
9304f876 CJW |
875 | int extra_count; |
876 | int num_use_regs; | |
877 | int par_index; | |
878 | int offset; | |
879 | ||
880 | rtx reg; | |
881 | rtx mem; | |
882 | rtx pop_rtx; | |
883 | rtx adjust_sp_rtx; | |
884 | rtx parallel_insn; | |
4e9a2848 | 885 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
886 | |
887 | /* We need to provide a customized rtx which contains | |
888 | necessary information for data analysis, | |
889 | so we create a parallel rtx like this: | |
890 | (parallel [(set (reg:SI Rb) | |
8a498f99 CJW |
891 | (mem (reg:SI SP_REGNUM))) |
892 | (set (reg:SI Rb+1) | |
893 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
894 | ... | |
895 | (set (reg:SI Re) | |
896 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
897 | (set (reg:SI FP_REGNUM) | |
898 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
899 | (set (reg:SI GP_REGNUM) | |
900 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
901 | (set (reg:SI LP_REGNUM) | |
902 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
903 | (set (reg:SI SP_REGNUM) | |
904 | (plus (reg:SI SP_REGNUM) (const_int 32)))]) */ | |
9304f876 CJW |
905 | |
906 | /* Calculate the number of registers that will be poped. */ | |
907 | extra_count = 0; | |
a6c7e777 | 908 | if (save_fp_p) |
9304f876 | 909 | extra_count++; |
a6c7e777 | 910 | if (save_gp_p) |
9304f876 | 911 | extra_count++; |
a6c7e777 | 912 | if (save_lp_p) |
9304f876 CJW |
913 | extra_count++; |
914 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
a6c7e777 | 915 | if (Rb == SP_REGNUM && Re == SP_REGNUM) |
9304f876 CJW |
916 | num_use_regs = extra_count; |
917 | else | |
a6c7e777 | 918 | num_use_regs = Re - Rb + 1 + extra_count; |
9304f876 CJW |
919 | |
920 | /* In addition to used registers, | |
921 | we need one more space for (set sp sp+x) rtx. */ | |
922 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
923 | rtvec_alloc (num_use_regs + 1)); | |
924 | par_index = 0; | |
925 | ||
926 | /* Initialize offset and start to create pop behavior. */ | |
927 | offset = 0; | |
928 | ||
929 | /* Create (set regX mem) from Rb, Rb+1 up to Re. */ | |
a6c7e777 | 930 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
931 | { |
932 | /* Rb and Re may be SP_REGNUM. | |
8a498f99 | 933 | We need to break this loop immediately. */ |
9304f876 | 934 | if (regno == SP_REGNUM) |
4e9a2848 | 935 | break; |
9304f876 CJW |
936 | |
937 | reg = gen_rtx_REG (SImode, regno); | |
938 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
939 | stack_pointer_rtx, | |
940 | offset)); | |
f7df4a84 | 941 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
942 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
943 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
944 | offset = offset + 4; | |
945 | par_index++; | |
4e9a2848 CJW |
946 | |
947 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
948 | } |
949 | ||
950 | /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */ | |
a6c7e777 | 951 | if (save_fp_p) |
9304f876 CJW |
952 | { |
953 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
954 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
955 | stack_pointer_rtx, | |
956 | offset)); | |
f7df4a84 | 957 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
958 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
959 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
960 | offset = offset + 4; | |
961 | par_index++; | |
4e9a2848 CJW |
962 | |
963 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 964 | } |
a6c7e777 | 965 | if (save_gp_p) |
9304f876 CJW |
966 | { |
967 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
968 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
969 | stack_pointer_rtx, | |
970 | offset)); | |
f7df4a84 | 971 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
972 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
973 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
974 | offset = offset + 4; | |
975 | par_index++; | |
4e9a2848 CJW |
976 | |
977 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 978 | } |
a6c7e777 | 979 | if (save_lp_p) |
9304f876 CJW |
980 | { |
981 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
982 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
983 | stack_pointer_rtx, | |
984 | offset)); | |
f7df4a84 | 985 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
986 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
987 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
988 | offset = offset + 4; | |
989 | par_index++; | |
4e9a2848 CJW |
990 | |
991 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
992 | } |
993 | ||
994 | /* Create (set sp sp+x). */ | |
995 | ||
996 | /* The offset value is already in place. No need to re-calculate it. */ | |
997 | adjust_sp_rtx | |
f7df4a84 | 998 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
999 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
1000 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
9304f876 | 1001 | |
4e9a2848 CJW |
1002 | /* Tell gcc we adjust SP in this insn. */ |
1003 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf); | |
1004 | ||
1005 | parallel_insn = emit_insn (parallel_insn); | |
1006 | ||
1007 | /* The insn rtx 'parallel_insn' will change frame layout. | |
1008 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1009 | generate CFI (Call Frame Information) stuff. */ | |
1010 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
1011 | ||
1012 | /* Add CFI info by manual. */ | |
1013 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
1014 | } |
1015 | ||
1016 | /* Function to create a parallel rtx pattern | |
1017 | which presents stack v3push behavior. | |
1018 | The overall concept are: | |
1019 | "push registers to memory", | |
1020 | "adjust stack pointer". */ | |
88437f39 | 1021 | static void |
a6c7e777 MC |
1022 | nds32_emit_stack_v3push (unsigned Rb, |
1023 | unsigned Re, | |
1024 | unsigned imm8u) | |
9304f876 | 1025 | { |
a6c7e777 | 1026 | unsigned regno; |
9304f876 CJW |
1027 | int num_use_regs; |
1028 | int par_index; | |
1029 | int offset; | |
1030 | ||
1031 | rtx reg; | |
1032 | rtx mem; | |
1033 | rtx push_rtx; | |
1034 | rtx adjust_sp_rtx; | |
1035 | rtx parallel_insn; | |
1036 | ||
1037 | /* We need to provide a customized rtx which contains | |
1038 | necessary information for data analysis, | |
1039 | so we create a parallel rtx like this: | |
88437f39 | 1040 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) |
8a498f99 CJW |
1041 | (reg:SI Rb)) |
1042 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
1043 | (reg:SI Rb+1)) | |
1044 | ... | |
1045 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
1046 | (reg:SI Re)) | |
1047 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
1048 | (reg:SI FP_REGNUM)) | |
1049 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
1050 | (reg:SI GP_REGNUM)) | |
1051 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
1052 | (reg:SI LP_REGNUM)) | |
1053 | (set (reg:SI SP_REGNUM) | |
1054 | (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */ | |
9304f876 CJW |
1055 | |
1056 | /* Calculate the number of registers that will be pushed. | |
1057 | Since $fp, $gp, and $lp is always pushed with v3push instruction, | |
1058 | we need to count these three registers. | |
1059 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1060 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1061 | num_use_regs = Re - Rb + 1 + 3; |
9304f876 CJW |
1062 | |
1063 | /* In addition to used registers, | |
1064 | we need one more space for (set sp sp-x-imm8u) rtx. */ | |
1065 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
1066 | rtvec_alloc (num_use_regs + 1)); | |
1067 | par_index = 0; | |
1068 | ||
1069 | /* Initialize offset and start to create push behavior. */ | |
1070 | offset = -(num_use_regs * 4); | |
1071 | ||
1072 | /* Create (set mem regX) from Rb, Rb+1 up to Re. | |
1073 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1074 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1075 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
1076 | { |
1077 | reg = gen_rtx_REG (SImode, regno); | |
1078 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1079 | stack_pointer_rtx, | |
1080 | offset)); | |
f7df4a84 | 1081 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1082 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1083 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1084 | offset = offset + 4; | |
1085 | par_index++; | |
1086 | } | |
1087 | ||
1088 | /* Create (set mem fp). */ | |
1089 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
1090 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1091 | stack_pointer_rtx, | |
1092 | offset)); | |
f7df4a84 | 1093 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1094 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1095 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1096 | offset = offset + 4; | |
1097 | par_index++; | |
1098 | /* Create (set mem gp). */ | |
1099 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
1100 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1101 | stack_pointer_rtx, | |
1102 | offset)); | |
f7df4a84 | 1103 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1104 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1105 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1106 | offset = offset + 4; | |
1107 | par_index++; | |
1108 | /* Create (set mem lp). */ | |
1109 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
1110 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1111 | stack_pointer_rtx, | |
1112 | offset)); | |
f7df4a84 | 1113 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1114 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1115 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1116 | offset = offset + 4; | |
1117 | par_index++; | |
1118 | ||
1119 | /* Create (set sp sp-x-imm8u). */ | |
1120 | ||
1121 | /* We need to re-calculate the offset value again for adjustment. */ | |
1122 | offset = -(num_use_regs * 4); | |
1123 | adjust_sp_rtx | |
f7df4a84 | 1124 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
1125 | plus_constant (Pmode, |
1126 | stack_pointer_rtx, | |
a6c7e777 | 1127 | offset - imm8u)); |
9304f876 CJW |
1128 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; |
1129 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
1130 | ||
88437f39 CJW |
1131 | parallel_insn = emit_insn (parallel_insn); |
1132 | ||
1133 | /* The insn rtx 'parallel_insn' will change frame layout. | |
1134 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1135 | generate CFI (Call Frame Information) stuff. */ | |
1136 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
9304f876 CJW |
1137 | } |
1138 | ||
1139 | /* Function to create a parallel rtx pattern | |
1140 | which presents stack v3pop behavior. | |
1141 | The overall concept are: | |
1142 | "pop registers from memory", | |
1143 | "adjust stack pointer". */ | |
88437f39 | 1144 | static void |
a6c7e777 MC |
1145 | nds32_emit_stack_v3pop (unsigned Rb, |
1146 | unsigned Re, | |
1147 | unsigned imm8u) | |
9304f876 | 1148 | { |
a6c7e777 | 1149 | unsigned regno; |
9304f876 CJW |
1150 | int num_use_regs; |
1151 | int par_index; | |
1152 | int offset; | |
1153 | ||
1154 | rtx reg; | |
1155 | rtx mem; | |
1156 | rtx pop_rtx; | |
1157 | rtx adjust_sp_rtx; | |
1158 | rtx parallel_insn; | |
88437f39 | 1159 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
1160 | |
1161 | /* We need to provide a customized rtx which contains | |
1162 | necessary information for data analysis, | |
1163 | so we create a parallel rtx like this: | |
1164 | (parallel [(set (reg:SI Rb) | |
8a498f99 CJW |
1165 | (mem (reg:SI SP_REGNUM))) |
1166 | (set (reg:SI Rb+1) | |
1167 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
1168 | ... | |
1169 | (set (reg:SI Re) | |
1170 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
1171 | (set (reg:SI FP_REGNUM) | |
1172 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
1173 | (set (reg:SI GP_REGNUM) | |
1174 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
1175 | (set (reg:SI LP_REGNUM) | |
1176 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
1177 | (set (reg:SI SP_REGNUM) | |
1178 | (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */ | |
9304f876 CJW |
1179 | |
1180 | /* Calculate the number of registers that will be poped. | |
1181 | Since $fp, $gp, and $lp is always poped with v3pop instruction, | |
1182 | we need to count these three registers. | |
1183 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1184 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1185 | num_use_regs = Re - Rb + 1 + 3; |
9304f876 CJW |
1186 | |
1187 | /* In addition to used registers, | |
1188 | we need one more space for (set sp sp+x+imm8u) rtx. */ | |
1189 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
1190 | rtvec_alloc (num_use_regs + 1)); | |
1191 | par_index = 0; | |
1192 | ||
1193 | /* Initialize offset and start to create pop behavior. */ | |
1194 | offset = 0; | |
1195 | ||
1196 | /* Create (set regX mem) from Rb, Rb+1 up to Re. | |
1197 | Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1198 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1199 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
1200 | { |
1201 | reg = gen_rtx_REG (SImode, regno); | |
1202 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1203 | stack_pointer_rtx, | |
1204 | offset)); | |
f7df4a84 | 1205 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1206 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1207 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1208 | offset = offset + 4; | |
1209 | par_index++; | |
88437f39 CJW |
1210 | |
1211 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
1212 | } |
1213 | ||
1214 | /* Create (set fp mem). */ | |
1215 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
1216 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1217 | stack_pointer_rtx, | |
1218 | offset)); | |
f7df4a84 | 1219 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1220 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1221 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1222 | offset = offset + 4; | |
1223 | par_index++; | |
88437f39 CJW |
1224 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
1225 | ||
9304f876 CJW |
1226 | /* Create (set gp mem). */ |
1227 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
1228 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1229 | stack_pointer_rtx, | |
1230 | offset)); | |
f7df4a84 | 1231 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1232 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1233 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1234 | offset = offset + 4; | |
1235 | par_index++; | |
88437f39 CJW |
1236 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
1237 | ||
9304f876 CJW |
1238 | /* Create (set lp mem ). */ |
1239 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
1240 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1241 | stack_pointer_rtx, | |
1242 | offset)); | |
f7df4a84 | 1243 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1244 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1245 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1246 | offset = offset + 4; | |
1247 | par_index++; | |
88437f39 | 1248 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
9304f876 CJW |
1249 | |
1250 | /* Create (set sp sp+x+imm8u). */ | |
1251 | ||
1252 | /* The offset value is already in place. No need to re-calculate it. */ | |
1253 | adjust_sp_rtx | |
f7df4a84 | 1254 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
1255 | plus_constant (Pmode, |
1256 | stack_pointer_rtx, | |
a6c7e777 | 1257 | offset + imm8u)); |
9304f876 | 1258 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; |
9304f876 | 1259 | |
a6c7e777 MC |
1260 | if (frame_pointer_needed) |
1261 | { | |
1262 | /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp) | |
1263 | (const_int 0)) | |
1264 | mean reset frame pointer to $sp and reset to offset 0. */ | |
1265 | rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
1266 | const0_rtx); | |
1267 | dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); | |
1268 | } | |
1269 | else | |
1270 | { | |
1271 | /* Tell gcc we adjust SP in this insn. */ | |
1272 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, | |
1273 | copy_rtx (adjust_sp_rtx), dwarf); | |
1274 | } | |
88437f39 CJW |
1275 | |
1276 | parallel_insn = emit_insn (parallel_insn); | |
1277 | ||
1278 | /* The insn rtx 'parallel_insn' will change frame layout. | |
1279 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1280 | generate CFI (Call Frame Information) stuff. */ | |
1281 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
1282 | ||
1283 | /* Add CFI info by manual. */ | |
1284 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
1285 | } |
1286 | ||
b26fa4f9 KLC |
1287 | static void |
1288 | nds32_emit_load_gp (void) | |
1289 | { | |
1290 | rtx got_symbol, pat; | |
1291 | ||
1292 | /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ | |
1293 | emit_insn (gen_blockage ()); | |
1294 | ||
1295 | got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
1296 | /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */ | |
1297 | pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); | |
1298 | pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-8))); | |
1299 | emit_insn (gen_sethi (pic_offset_table_rtx,pat)); | |
1300 | ||
1301 | /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */ | |
1302 | pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); | |
1303 | pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-4))); | |
1304 | emit_insn (gen_lo_sum (pic_offset_table_rtx, pic_offset_table_rtx, pat)); | |
1305 | ||
1306 | /* add5.pc $gp */ | |
1307 | emit_insn (gen_add_pc (pic_offset_table_rtx, pic_offset_table_rtx)); | |
1308 | ||
1309 | /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ | |
1310 | emit_insn (gen_blockage ()); | |
1311 | } | |
1312 | ||
9304f876 CJW |
1313 | /* Function that may creates more instructions |
1314 | for large value on adjusting stack pointer. | |
1315 | ||
1316 | In nds32 target, 'addi' can be used for stack pointer | |
1317 | adjustment in prologue/epilogue stage. | |
1318 | However, sometimes there are too many local variables so that | |
1319 | the adjustment value is not able to be fit in the 'addi' instruction. | |
1320 | One solution is to move value into a register | |
1321 | and then use 'add' instruction. | |
a6c7e777 MC |
1322 | In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */ |
1323 | static void | |
1324 | nds32_emit_adjust_frame (rtx to_reg, rtx from_reg, int adjust_value) | |
9304f876 | 1325 | { |
9304f876 | 1326 | rtx tmp_reg; |
a6c7e777 MC |
1327 | rtx frame_adjust_insn; |
1328 | rtx adjust_value_rtx = GEN_INT (adjust_value); | |
9304f876 | 1329 | |
a6c7e777 MC |
1330 | if (adjust_value == 0) |
1331 | return; | |
1332 | ||
1333 | if (!satisfies_constraint_Is15 (adjust_value_rtx)) | |
9304f876 CJW |
1334 | { |
1335 | /* The value is not able to fit in single addi instruction. | |
8a498f99 CJW |
1336 | Create more instructions of moving value into a register |
1337 | and then add stack pointer with it. */ | |
9304f876 CJW |
1338 | |
1339 | /* $r15 is going to be temporary register to hold the value. */ | |
1340 | tmp_reg = gen_rtx_REG (SImode, TA_REGNUM); | |
1341 | ||
1342 | /* Create one more instruction to move value | |
8a498f99 | 1343 | into the temporary register. */ |
a6c7e777 | 1344 | emit_move_insn (tmp_reg, adjust_value_rtx); |
9304f876 CJW |
1345 | |
1346 | /* Create new 'add' rtx. */ | |
a6c7e777 MC |
1347 | frame_adjust_insn = gen_addsi3 (to_reg, |
1348 | from_reg, | |
1349 | tmp_reg); | |
9304f876 | 1350 | /* Emit rtx into insn list and receive its transformed insn rtx. */ |
a6c7e777 | 1351 | frame_adjust_insn = emit_insn (frame_adjust_insn); |
9304f876 | 1352 | |
a6c7e777 | 1353 | /* Because (tmp_reg <- full_value) may be split into two |
67914693 | 1354 | rtl patterns, we cannot set its RTX_FRAME_RELATED_P. |
a6c7e777 MC |
1355 | We need to construct another (sp <- sp + full_value) |
1356 | and then insert it into sp_adjust_insn's reg note to | |
1357 | represent a frame related expression. | |
1358 | GCC knows how to refer it and output debug information. */ | |
9304f876 | 1359 | |
a6c7e777 MC |
1360 | rtx plus_rtx; |
1361 | rtx set_rtx; | |
9304f876 | 1362 | |
a6c7e777 MC |
1363 | plus_rtx = plus_constant (Pmode, from_reg, adjust_value); |
1364 | set_rtx = gen_rtx_SET (to_reg, plus_rtx); | |
1365 | add_reg_note (frame_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx); | |
9304f876 CJW |
1366 | } |
1367 | else | |
1368 | { | |
a6c7e777 MC |
1369 | /* Generate sp adjustment instruction if and only if sp_adjust != 0. */ |
1370 | frame_adjust_insn = gen_addsi3 (to_reg, | |
1371 | from_reg, | |
1372 | adjust_value_rtx); | |
1373 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
1374 | frame_adjust_insn = emit_insn (frame_adjust_insn); | |
9304f876 | 1375 | } |
a6c7e777 MC |
1376 | |
1377 | /* The insn rtx 'sp_adjust_insn' will change frame layout. | |
1378 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1379 | generate CFI (Call Frame Information) stuff. */ | |
1380 | RTX_FRAME_RELATED_P (frame_adjust_insn) = 1; | |
9304f876 CJW |
1381 | } |
1382 | ||
1383 | /* Return true if MODE/TYPE need double word alignment. */ | |
1384 | static bool | |
ef4bddc2 | 1385 | nds32_needs_double_word_align (machine_mode mode, const_tree type) |
9304f876 CJW |
1386 | { |
1387 | unsigned int align; | |
1388 | ||
634bdae9 CJW |
1389 | /* Pick up the alignment according to the mode or type. */ |
1390 | align = NDS32_MODE_TYPE_ALIGN (mode, type); | |
9304f876 CJW |
1391 | |
1392 | return (align > PARM_BOUNDARY); | |
1393 | } | |
1394 | ||
1395 | /* Return true if FUNC is a naked function. */ | |
2140297c | 1396 | bool |
810f736f | 1397 | nds32_naked_function_p (tree func) |
9304f876 | 1398 | { |
54c537e6 CJW |
1399 | /* FOR BACKWARD COMPATIBILITY, |
1400 | we need to support 'no_prologue' attribute as well. */ | |
1401 | tree t_naked; | |
1402 | tree t_no_prologue; | |
9304f876 CJW |
1403 | |
1404 | if (TREE_CODE (func) != FUNCTION_DECL) | |
1405 | abort (); | |
1406 | ||
54c537e6 CJW |
1407 | /* We have to use lookup_attribute() to check attributes. |
1408 | Because attr_naked_p and attr_no_prologue_p are set in | |
1409 | nds32_compute_stack_frame() and the function has not been | |
1410 | invoked yet. */ | |
1411 | t_naked = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); | |
1412 | t_no_prologue = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func)); | |
9304f876 | 1413 | |
54c537e6 | 1414 | return ((t_naked != NULL_TREE) || (t_no_prologue != NULL_TREE)); |
9304f876 CJW |
1415 | } |
1416 | ||
c411e9aa SC |
1417 | /* Function that determine whether a load postincrement is a good thing to use |
1418 | for a given mode. */ | |
1419 | bool | |
1420 | nds32_use_load_post_increment (machine_mode mode) | |
1421 | { | |
1422 | return (GET_MODE_SIZE (mode) <= GET_MODE_SIZE(E_DImode)); | |
1423 | } | |
1424 | ||
9304f876 CJW |
1425 | /* Function that check if 'X' is a valid address register. |
1426 | The variable 'STRICT' is very important to | |
1427 | make decision for register number. | |
1428 | ||
1429 | STRICT : true | |
1430 | => We are in reload pass or after reload pass. | |
8a498f99 | 1431 | The register number should be strictly limited in general registers. |
9304f876 CJW |
1432 | |
1433 | STRICT : false | |
1434 | => Before reload pass, we are free to use any register number. */ | |
1435 | static bool | |
1436 | nds32_address_register_rtx_p (rtx x, bool strict) | |
1437 | { | |
1438 | int regno; | |
1439 | ||
1440 | if (GET_CODE (x) != REG) | |
1441 | return false; | |
1442 | ||
1443 | regno = REGNO (x); | |
1444 | ||
1445 | if (strict) | |
1446 | return REGNO_OK_FOR_BASE_P (regno); | |
1447 | else | |
1448 | return true; | |
1449 | } | |
1450 | ||
1451 | /* Function that check if 'INDEX' is valid to be a index rtx for address. | |
1452 | ||
1453 | OUTER_MODE : Machine mode of outer address rtx. | |
8a498f99 | 1454 | INDEX : Check if this rtx is valid to be a index for address. |
9304f876 CJW |
1455 | STRICT : If it is true, we are in reload pass or after reload pass. */ |
1456 | static bool | |
ef4bddc2 | 1457 | nds32_legitimate_index_p (machine_mode outer_mode, |
9304f876 CJW |
1458 | rtx index, |
1459 | bool strict) | |
1460 | { | |
1461 | int regno; | |
1462 | rtx op0; | |
1463 | rtx op1; | |
1464 | ||
1465 | switch (GET_CODE (index)) | |
1466 | { | |
1467 | case REG: | |
1468 | regno = REGNO (index); | |
1469 | /* If we are in reload pass or after reload pass, | |
8a498f99 | 1470 | we need to limit it to general register. */ |
9304f876 CJW |
1471 | if (strict) |
1472 | return REGNO_OK_FOR_INDEX_P (regno); | |
1473 | else | |
1474 | return true; | |
1475 | ||
1476 | case CONST_INT: | |
1477 | /* The alignment of the integer value is determined by 'outer_mode'. */ | |
e2286268 | 1478 | switch (GET_MODE_SIZE (outer_mode)) |
9304f876 | 1479 | { |
e2286268 | 1480 | case 1: |
9304f876 | 1481 | /* Further check if the value is legal for the 'outer_mode'. */ |
e2286268 MC |
1482 | if (satisfies_constraint_Is15 (index)) |
1483 | return true; | |
1484 | break; | |
9304f876 | 1485 | |
e2286268 | 1486 | case 2: |
9304f876 | 1487 | /* Further check if the value is legal for the 'outer_mode'. */ |
e2286268 MC |
1488 | if (satisfies_constraint_Is16 (index)) |
1489 | { | |
5f2a98c3 CJW |
1490 | /* If it is not under strictly aligned situation, |
1491 | we can return true without checking alignment. */ | |
1492 | if (!cfun->machine->strict_aligned_p) | |
1493 | return true; | |
e2286268 | 1494 | /* Make sure address is half word alignment. */ |
5f2a98c3 | 1495 | else if (NDS32_HALF_WORD_ALIGN_P (INTVAL (index))) |
e2286268 MC |
1496 | return true; |
1497 | } | |
1498 | break; | |
9304f876 | 1499 | |
e2286268 | 1500 | case 4: |
9304f876 | 1501 | /* Further check if the value is legal for the 'outer_mode'. */ |
e2286268 MC |
1502 | if (satisfies_constraint_Is17 (index)) |
1503 | { | |
1504 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) | |
1505 | { | |
1506 | if (!satisfies_constraint_Is14 (index)) | |
1507 | return false; | |
1508 | } | |
1509 | ||
5f2a98c3 CJW |
1510 | /* If it is not under strictly aligned situation, |
1511 | we can return true without checking alignment. */ | |
1512 | if (!cfun->machine->strict_aligned_p) | |
1513 | return true; | |
e2286268 | 1514 | /* Make sure address is word alignment. */ |
5f2a98c3 | 1515 | else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) |
e2286268 MC |
1516 | return true; |
1517 | } | |
1518 | break; | |
9304f876 | 1519 | |
e2286268 MC |
1520 | case 8: |
1521 | if (satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4, | |
1522 | SImode))) | |
1523 | { | |
1524 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) | |
1525 | { | |
1526 | if (!satisfies_constraint_Is14 (index)) | |
1527 | return false; | |
1528 | } | |
1529 | ||
5f2a98c3 CJW |
1530 | /* If it is not under strictly aligned situation, |
1531 | we can return true without checking alignment. */ | |
1532 | if (!cfun->machine->strict_aligned_p) | |
1533 | return true; | |
e2286268 MC |
1534 | /* Make sure address is word alignment. |
1535 | Currently we do not have 64-bit load/store yet, | |
1536 | so we will use two 32-bit load/store instructions to do | |
1537 | memory access and they are single word alignment. */ | |
5f2a98c3 | 1538 | else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) |
e2286268 MC |
1539 | return true; |
1540 | } | |
1541 | break; | |
9304f876 | 1542 | |
e2286268 MC |
1543 | default: |
1544 | return false; | |
9304f876 CJW |
1545 | } |
1546 | ||
1547 | return false; | |
1548 | ||
1549 | case MULT: | |
1550 | op0 = XEXP (index, 0); | |
1551 | op1 = XEXP (index, 1); | |
1552 | ||
1553 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1554 | { | |
1555 | int multiplier; | |
1556 | multiplier = INTVAL (op1); | |
1557 | ||
f62a2af5 CJW |
1558 | /* We only allow (mult reg const_int_1), (mult reg const_int_2), |
1559 | (mult reg const_int_4) or (mult reg const_int_8). */ | |
1560 | if (multiplier != 1 && multiplier != 2 | |
1561 | && multiplier != 4 && multiplier != 8) | |
9304f876 CJW |
1562 | return false; |
1563 | ||
1564 | regno = REGNO (op0); | |
1565 | /* Limit it in general registers if we are | |
1566 | in reload pass or after reload pass. */ | |
1567 | if(strict) | |
1568 | return REGNO_OK_FOR_INDEX_P (regno); | |
1569 | else | |
1570 | return true; | |
1571 | } | |
1572 | ||
1573 | return false; | |
1574 | ||
1575 | case ASHIFT: | |
1576 | op0 = XEXP (index, 0); | |
1577 | op1 = XEXP (index, 1); | |
1578 | ||
1579 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1580 | { | |
1581 | int sv; | |
1582 | /* op1 is already the sv value for use to do left shift. */ | |
1583 | sv = INTVAL (op1); | |
1584 | ||
1585 | /* We only allow (ashift reg const_int_0) | |
f62a2af5 CJW |
1586 | or (ashift reg const_int_1) or (ashift reg const_int_2) or |
1587 | (ashift reg const_int_3). */ | |
1588 | if (sv != 0 && sv != 1 && sv !=2 && sv != 3) | |
9304f876 CJW |
1589 | return false; |
1590 | ||
1591 | regno = REGNO (op0); | |
1592 | /* Limit it in general registers if we are | |
1593 | in reload pass or after reload pass. */ | |
1594 | if(strict) | |
1595 | return REGNO_OK_FOR_INDEX_P (regno); | |
1596 | else | |
1597 | return true; | |
1598 | } | |
1599 | ||
1600 | return false; | |
1601 | ||
1602 | default: | |
1603 | return false; | |
1604 | } | |
1605 | } | |
1606 | ||
c4d8d050 CJW |
1607 | static void |
1608 | nds32_register_pass ( | |
1609 | rtl_opt_pass *(*make_pass_func) (gcc::context *), | |
1610 | enum pass_positioning_ops pass_pos, | |
1611 | const char *ref_pass_name) | |
1612 | { | |
1613 | opt_pass *new_opt_pass = make_pass_func (g); | |
1614 | ||
1615 | struct register_pass_info insert_pass = | |
1616 | { | |
1617 | new_opt_pass, /* pass */ | |
1618 | ref_pass_name, /* reference_pass_name */ | |
1619 | 1, /* ref_pass_instance_number */ | |
1620 | pass_pos /* po_op */ | |
1621 | }; | |
1622 | ||
1623 | register_pass (&insert_pass); | |
1624 | } | |
1625 | ||
1626 | /* This function is called from nds32_option_override (). | |
1627 | All new passes should be registered here. */ | |
1628 | static void | |
1629 | nds32_register_passes (void) | |
1630 | { | |
2140297c CJW |
1631 | nds32_register_pass ( |
1632 | make_pass_nds32_fp_as_gp, | |
1633 | PASS_POS_INSERT_BEFORE, | |
1634 | "ira"); | |
1635 | ||
c4d8d050 CJW |
1636 | nds32_register_pass ( |
1637 | make_pass_nds32_relax_opt, | |
1638 | PASS_POS_INSERT_AFTER, | |
1639 | "mach"); | |
1640 | } | |
1641 | ||
9304f876 CJW |
1642 | /* ------------------------------------------------------------------------ */ |
1643 | ||
1644 | /* PART 3: Implement target hook stuff definitions. */ | |
e2286268 MC |
1645 | \f |
1646 | ||
a5876228 CJW |
1647 | /* Computing the Length of an Insn. |
1648 | Modifies the length assigned to instruction INSN. | |
1649 | LEN is the initially computed length of the insn. */ | |
1650 | int | |
1651 | nds32_adjust_insn_length (rtx_insn *insn, int length) | |
1652 | { | |
1653 | int adjust_value = 0; | |
1654 | switch (recog_memoized (insn)) | |
1655 | { | |
1656 | case CODE_FOR_call_internal: | |
1657 | case CODE_FOR_call_value_internal: | |
1658 | { | |
43fa41c1 CJW |
1659 | if (NDS32_ALIGN_P ()) |
1660 | { | |
1661 | rtx_insn *next_insn = next_active_insn (insn); | |
1662 | if (next_insn && get_attr_length (next_insn) != 2) | |
1663 | adjust_value += 2; | |
1664 | } | |
a5876228 CJW |
1665 | /* We need insert a nop after a noretun function call |
1666 | to prevent software breakpoint corrupt the next function. */ | |
1667 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
1668 | { | |
1669 | if (TARGET_16_BIT) | |
1670 | adjust_value += 2; | |
1671 | else | |
1672 | adjust_value += 4; | |
1673 | } | |
1674 | } | |
1675 | return length + adjust_value; | |
1676 | ||
1677 | default: | |
1678 | return length; | |
1679 | } | |
1680 | } | |
1681 | ||
5f2a98c3 CJW |
1682 | /* Storage Layout. */ |
1683 | ||
1684 | /* This function will be called just before expansion into rtl. */ | |
1685 | static void | |
1686 | nds32_expand_to_rtl_hook (void) | |
1687 | { | |
1688 | /* We need to set strictly aligned situation. | |
1689 | After that, the memory address checking in nds32_legitimate_address_p() | |
1690 | will take alignment offset into consideration so that it will not create | |
1691 | unaligned [base + offset] access during the rtl optimization. */ | |
1692 | cfun->machine->strict_aligned_p = 1; | |
1693 | } | |
1694 | ||
1695 | \f | |
e2286268 MC |
1696 | /* Register Usage. */ |
1697 | ||
1698 | static void | |
1699 | nds32_conditional_register_usage (void) | |
1700 | { | |
1701 | int regno; | |
1702 | ||
cf3cd43d CJW |
1703 | if (TARGET_LINUX_ABI) |
1704 | fixed_regs[TP_REGNUM] = 1; | |
1705 | ||
e2286268 MC |
1706 | if (TARGET_HARD_FLOAT) |
1707 | { | |
1708 | for (regno = NDS32_FIRST_FPR_REGNUM; | |
1709 | regno <= NDS32_LAST_FPR_REGNUM; regno++) | |
1710 | { | |
1711 | fixed_regs[regno] = 0; | |
1712 | if (regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS) | |
1713 | call_used_regs[regno] = 1; | |
1714 | else if (regno >= NDS32_FIRST_FPR_REGNUM + 22 | |
1715 | && regno < NDS32_FIRST_FPR_REGNUM + 48) | |
1716 | call_used_regs[regno] = 1; | |
1717 | else | |
1718 | call_used_regs[regno] = 0; | |
1719 | } | |
1720 | } | |
1721 | else if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
1722 | { | |
1723 | for (regno = NDS32_FIRST_FPR_REGNUM; | |
1724 | regno <= NDS32_LAST_FPR_REGNUM; | |
1725 | regno++) | |
1726 | fixed_regs[regno] = 0; | |
1727 | } | |
1728 | } | |
1729 | ||
9304f876 CJW |
1730 | \f |
1731 | /* Register Classes. */ | |
1732 | ||
1733 | static unsigned char | |
1734 | nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED, | |
ef4bddc2 | 1735 | machine_mode mode) |
9304f876 CJW |
1736 | { |
1737 | /* Return the maximum number of consecutive registers | |
1738 | needed to represent "mode" in a register of "rclass". */ | |
1739 | return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); | |
1740 | } | |
1741 | ||
1742 | static int | |
1743 | nds32_register_priority (int hard_regno) | |
1744 | { | |
1745 | /* Encourage to use r0-r7 for LRA when optimize for size. */ | |
6a5a7ee3 CJW |
1746 | if (optimize_size) |
1747 | { | |
1748 | if (hard_regno < 8) | |
1749 | return 4; | |
1750 | else if (hard_regno < 16) | |
1751 | return 3; | |
1752 | else if (hard_regno < 28) | |
1753 | return 2; | |
1754 | else | |
1755 | return 1; | |
1756 | } | |
1757 | else | |
1758 | { | |
1759 | if (hard_regno > 27) | |
1760 | return 1; | |
1761 | else | |
1762 | return 4; | |
1763 | } | |
9304f876 CJW |
1764 | } |
1765 | ||
e2286268 MC |
1766 | static bool |
1767 | nds32_can_change_mode_class (machine_mode from, | |
1768 | machine_mode to, | |
1769 | reg_class_t rclass) | |
1770 | { | |
1771 | /* Don't spill double-precision register to two singal-precision | |
1772 | registers */ | |
1773 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
1774 | && GET_MODE_SIZE (from) != GET_MODE_SIZE (to)) | |
1775 | { | |
1776 | return !reg_classes_intersect_p (rclass, FP_REGS); | |
1777 | } | |
1778 | ||
1779 | return true; | |
1780 | } | |
1781 | ||
9304f876 CJW |
1782 | \f |
1783 | /* Stack Layout and Calling Conventions. */ | |
1784 | ||
1785 | /* There are three kinds of pointer concepts using in GCC compiler: | |
1786 | ||
1787 | frame pointer: A pointer to the first location of local variables. | |
1788 | stack pointer: A pointer to the top of a stack frame. | |
1789 | argument pointer: A pointer to the incoming arguments. | |
1790 | ||
1791 | In nds32 target calling convention, we are using 8-byte alignment. | |
1792 | Besides, we would like to have each stack frame of a function includes: | |
1793 | ||
1794 | [Block A] | |
1795 | 1. previous hard frame pointer | |
1796 | 2. return address | |
1797 | 3. callee-saved registers | |
1798 | 4. <padding bytes> (we will calculte in nds32_compute_stack_frame() | |
8a498f99 CJW |
1799 | and save it at |
1800 | cfun->machine->callee_saved_area_padding_bytes) | |
9304f876 CJW |
1801 | |
1802 | [Block B] | |
1803 | 1. local variables | |
1804 | 2. spilling location | |
1805 | 3. <padding bytes> (it will be calculated by GCC itself) | |
1806 | 4. incoming arguments | |
1807 | 5. <padding bytes> (it will be calculated by GCC itself) | |
1808 | ||
1809 | [Block C] | |
1810 | 1. <padding bytes> (it will be calculated by GCC itself) | |
1811 | 2. outgoing arguments | |
1812 | ||
1813 | We 'wrap' these blocks together with | |
1814 | hard frame pointer ($r28) and stack pointer ($r31). | |
1815 | By applying the basic frame/stack/argument pointers concept, | |
1816 | the layout of a stack frame shoule be like this: | |
1817 | ||
8a498f99 | 1818 | | | |
9304f876 | 1819 | old stack pointer -> ---- |
8a498f99 CJW |
1820 | | | \ |
1821 | | | saved arguments for | |
1822 | | | vararg functions | |
1823 | | | / | |
9304f876 CJW |
1824 | hard frame pointer -> -- |
1825 | & argument pointer | | \ | |
8a498f99 CJW |
1826 | | | previous hardware frame pointer |
1827 | | | return address | |
1828 | | | callee-saved registers | |
1829 | | | / | |
1830 | frame pointer -> -- | |
1831 | | | \ | |
1832 | | | local variables | |
1833 | | | and incoming arguments | |
1834 | | | / | |
1835 | -- | |
1836 | | | \ | |
1837 | | | outgoing | |
1838 | | | arguments | |
1839 | | | / | |
1840 | stack pointer -> ---- | |
9304f876 CJW |
1841 | |
1842 | $SFP and $AP are used to represent frame pointer and arguments pointer, | |
1843 | which will be both eliminated as hard frame pointer. */ | |
1844 | ||
1845 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
1846 | ||
19ac960a CJW |
1847 | static bool |
1848 | nds32_can_eliminate (const int from_reg, const int to_reg) | |
9304f876 CJW |
1849 | { |
1850 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1851 | return true; | |
1852 | ||
1853 | if (from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1854 | return true; | |
1855 | ||
1856 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1857 | return true; | |
1858 | ||
1859 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1860 | return true; | |
1861 | ||
1862 | return false; | |
1863 | } | |
1864 | ||
1865 | /* -- Passing Arguments in Registers. */ | |
1866 | ||
1867 | static rtx | |
6783fdb7 | 1868 | nds32_function_arg (cumulative_args_t ca, const function_arg_info &arg) |
9304f876 | 1869 | { |
7f6cd86b | 1870 | unsigned int regno; |
9304f876 | 1871 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); |
6783fdb7 RS |
1872 | tree type = arg.type; |
1873 | machine_mode mode = arg.mode; | |
9304f876 CJW |
1874 | |
1875 | /* The last time this hook is called, | |
6783fdb7 RS |
1876 | it is called with an end marker. */ |
1877 | if (arg.end_marker_p ()) | |
9304f876 CJW |
1878 | return NULL_RTX; |
1879 | ||
7f6cd86b | 1880 | /* For nameless arguments, we need to take care it individually. */ |
6783fdb7 | 1881 | if (!arg.named) |
9304f876 | 1882 | { |
7f6cd86b | 1883 | /* If we are under hard float abi, we have arguments passed on the |
8a498f99 | 1884 | stack and all situation can be handled by GCC itself. */ |
7f6cd86b CJW |
1885 | if (TARGET_HARD_FLOAT) |
1886 | return NULL_RTX; | |
1887 | ||
1888 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) | |
1889 | { | |
1890 | /* If we still have enough registers to pass argument, pick up | |
1891 | next available register number. */ | |
1892 | regno | |
1893 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1894 | return gen_rtx_REG (mode, regno); | |
1895 | } | |
634bdae9 | 1896 | |
9304f876 | 1897 | /* No register available, return NULL_RTX. |
8a498f99 | 1898 | The compiler will use stack to pass argument instead. */ |
9304f876 CJW |
1899 | return NULL_RTX; |
1900 | } | |
7f6cd86b CJW |
1901 | |
1902 | /* The following is to handle named argument. | |
1903 | Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT | |
1904 | are different. */ | |
1905 | if (TARGET_HARD_FLOAT) | |
1906 | { | |
e2286268 MC |
1907 | /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR |
1908 | to pass argument. We have to further check TYPE and MODE so | |
1909 | that we can determine which kind of register we shall use. */ | |
1910 | ||
1911 | /* Note that we need to pass argument entirely in registers under | |
1912 | hard float abi. */ | |
1913 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1914 | && NDS32_ARG_ENTIRE_IN_FPR_REG_P (cum->fpr_offset, mode, type)) | |
1915 | { | |
1916 | /* Pick up the next available FPR register number. */ | |
1917 | regno | |
1918 | = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type); | |
1919 | return gen_rtx_REG (mode, regno); | |
1920 | } | |
1921 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
1922 | && NDS32_ARG_ENTIRE_IN_GPR_REG_P (cum->gpr_offset, mode, type)) | |
1923 | { | |
1924 | /* Pick up the next available GPR register number. */ | |
1925 | regno | |
1926 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1927 | return gen_rtx_REG (mode, regno); | |
1928 | } | |
7f6cd86b CJW |
1929 | } |
1930 | else | |
1931 | { | |
1932 | /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass | |
8a498f99 CJW |
1933 | argument. Since we allow to pass argument partially in registers, |
1934 | we can just return it if there are still registers available. */ | |
7f6cd86b CJW |
1935 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) |
1936 | { | |
1937 | /* Pick up the next available register number. */ | |
1938 | regno | |
1939 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1940 | return gen_rtx_REG (mode, regno); | |
1941 | } | |
1942 | ||
1943 | } | |
1944 | ||
1945 | /* No register available, return NULL_RTX. | |
1946 | The compiler will use stack to pass argument instead. */ | |
1947 | return NULL_RTX; | |
9304f876 CJW |
1948 | } |
1949 | ||
d40f3c40 | 1950 | static bool |
0ffef200 | 1951 | nds32_must_pass_in_stack (const function_arg_info &arg) |
d40f3c40 CJW |
1952 | { |
1953 | /* Return true if a type must be passed in memory. | |
1954 | If it is NOT using hard float abi, small aggregates can be | |
1955 | passed in a register even we are calling a variadic function. | |
1956 | So there is no need to take padding into consideration. */ | |
1957 | if (TARGET_HARD_FLOAT) | |
0ffef200 | 1958 | return must_pass_in_stack_var_size_or_pad (arg); |
d40f3c40 | 1959 | else |
0ffef200 | 1960 | return must_pass_in_stack_var_size (arg); |
d40f3c40 CJW |
1961 | } |
1962 | ||
650fc469 | 1963 | static int |
a7c81bc1 | 1964 | nds32_arg_partial_bytes (cumulative_args_t ca, const function_arg_info &arg) |
650fc469 CJW |
1965 | { |
1966 | /* Returns the number of bytes at the beginning of an argument that | |
1967 | must be put in registers. The value must be zero for arguments that are | |
1968 | passed entirely in registers or that are entirely pushed on the stack. | |
1969 | Besides, TARGET_FUNCTION_ARG for these arguments should return the | |
1970 | first register to be used by the caller for this argument. */ | |
1971 | unsigned int needed_reg_count; | |
1972 | unsigned int remaining_reg_count; | |
1973 | CUMULATIVE_ARGS *cum; | |
1974 | ||
1975 | cum = get_cumulative_args (ca); | |
1976 | ||
1977 | /* Under hard float abi, we better have argument entirely passed in | |
1978 | registers or pushed on the stack so that we can reduce the complexity | |
1979 | of dealing with cum->gpr_offset and cum->fpr_offset. */ | |
1980 | if (TARGET_HARD_FLOAT) | |
1981 | return 0; | |
1982 | ||
1983 | /* If we have already runned out of argument registers, return zero | |
1984 | so that the argument will be entirely pushed on the stack. */ | |
a7c81bc1 | 1985 | if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, arg.mode, arg.type) |
650fc469 CJW |
1986 | >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) |
1987 | return 0; | |
1988 | ||
1989 | /* Calculate how many registers do we need for this argument. */ | |
a7c81bc1 | 1990 | needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG (arg.mode, arg.type); |
650fc469 CJW |
1991 | |
1992 | /* Calculate how many argument registers have left for passing argument. | |
1993 | Note that we should count it from next available register number. */ | |
1994 | remaining_reg_count | |
1995 | = NDS32_MAX_GPR_REGS_FOR_ARGS | |
a7c81bc1 RS |
1996 | - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, |
1997 | arg.mode, arg.type) | |
8a498f99 | 1998 | - NDS32_GPR_ARG_FIRST_REGNUM); |
650fc469 CJW |
1999 | |
2000 | /* Note that we have to return the nubmer of bytes, not registers count. */ | |
2001 | if (needed_reg_count > remaining_reg_count) | |
2002 | return remaining_reg_count * UNITS_PER_WORD; | |
2003 | ||
2004 | return 0; | |
2005 | } | |
2006 | ||
9304f876 | 2007 | static void |
6930c98c RS |
2008 | nds32_function_arg_advance (cumulative_args_t ca, |
2009 | const function_arg_info &arg) | |
9304f876 CJW |
2010 | { |
2011 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); | |
6930c98c RS |
2012 | tree type = arg.type; |
2013 | machine_mode mode = arg.mode; | |
9304f876 | 2014 | |
6930c98c | 2015 | if (arg.named) |
9304f876 | 2016 | { |
7f6cd86b | 2017 | /* We need to further check TYPE and MODE so that we can determine |
e2286268 | 2018 | which kind of register we shall advance. */ |
7f6cd86b CJW |
2019 | |
2020 | /* Under hard float abi, we may advance FPR registers. */ | |
e2286268 | 2021 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) |
7f6cd86b | 2022 | { |
e2286268 MC |
2023 | cum->fpr_offset |
2024 | = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type) | |
2025 | - NDS32_FPR_ARG_FIRST_REGNUM | |
2026 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
7f6cd86b CJW |
2027 | } |
2028 | else | |
2029 | { | |
2030 | cum->gpr_offset | |
2031 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
2032 | - NDS32_GPR_ARG_FIRST_REGNUM | |
2033 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
2034 | } | |
2035 | } | |
2036 | else | |
2037 | { | |
2038 | /* If this nameless argument is NOT under TARGET_HARD_FLOAT, | |
8a498f99 CJW |
2039 | we can advance next register as well so that caller is |
2040 | able to pass arguments in registers and callee must be | |
2041 | in charge of pushing all of them into stack. */ | |
7f6cd86b CJW |
2042 | if (!TARGET_HARD_FLOAT) |
2043 | { | |
2044 | cum->gpr_offset | |
2045 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
2046 | - NDS32_GPR_ARG_FIRST_REGNUM | |
2047 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
2048 | } | |
9304f876 CJW |
2049 | } |
2050 | } | |
2051 | ||
2052 | static unsigned int | |
ef4bddc2 | 2053 | nds32_function_arg_boundary (machine_mode mode, const_tree type) |
9304f876 CJW |
2054 | { |
2055 | return (nds32_needs_double_word_align (mode, type) | |
2056 | ? NDS32_DOUBLE_WORD_ALIGNMENT | |
2057 | : PARM_BOUNDARY); | |
2058 | } | |
2059 | ||
7c32ef41 MC |
2060 | bool |
2061 | nds32_vector_mode_supported_p (machine_mode mode) | |
2062 | { | |
2063 | if (mode == V4QImode | |
2064 | || mode == V2HImode) | |
2065 | return NDS32_EXT_DSP_P (); | |
2066 | ||
2067 | return false; | |
2068 | } | |
2069 | ||
9304f876 CJW |
2070 | /* -- How Scalar Function Values Are Returned. */ |
2071 | ||
2072 | static rtx | |
2073 | nds32_function_value (const_tree ret_type, | |
2074 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
2075 | bool outgoing ATTRIBUTE_UNUSED) | |
2076 | { | |
ef4bddc2 | 2077 | machine_mode mode; |
9304f876 CJW |
2078 | int unsignedp; |
2079 | ||
2080 | mode = TYPE_MODE (ret_type); | |
2081 | unsignedp = TYPE_UNSIGNED (ret_type); | |
2082 | ||
e2286268 MC |
2083 | if (INTEGRAL_TYPE_P (ret_type)) |
2084 | mode = promote_mode (ret_type, mode, &unsignedp); | |
9304f876 | 2085 | |
e2286268 MC |
2086 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) |
2087 | return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); | |
2088 | else | |
2089 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); | |
9304f876 CJW |
2090 | } |
2091 | ||
2092 | static rtx | |
ef4bddc2 | 2093 | nds32_libcall_value (machine_mode mode, |
9304f876 CJW |
2094 | const_rtx fun ATTRIBUTE_UNUSED) |
2095 | { | |
e2286268 MC |
2096 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) |
2097 | return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); | |
2098 | ||
9304f876 CJW |
2099 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); |
2100 | } | |
2101 | ||
2102 | static bool | |
2103 | nds32_function_value_regno_p (const unsigned int regno) | |
2104 | { | |
e2286268 MC |
2105 | if (regno == NDS32_GPR_RET_FIRST_REGNUM |
2106 | || (TARGET_HARD_FLOAT | |
2107 | && regno == NDS32_FPR_RET_FIRST_REGNUM)) | |
2108 | return true; | |
2109 | ||
2110 | return false; | |
2111 | } | |
2112 | ||
2113 | /* -- How Large Values Are Returned. */ | |
2114 | ||
2115 | static bool | |
2116 | nds32_return_in_memory (const_tree type, | |
2117 | const_tree fntype ATTRIBUTE_UNUSED) | |
2118 | { | |
2119 | /* Note that int_size_in_bytes can return -1 if the size can vary | |
2120 | or is larger than an integer. */ | |
2121 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
2122 | ||
2123 | /* For COMPLEX_TYPE, if the total size cannot be hold within two registers, | |
2124 | the return value is supposed to be in memory. We need to be aware of | |
2125 | that the size may be -1. */ | |
2126 | if (TREE_CODE (type) == COMPLEX_TYPE) | |
2127 | if (size < 0 || size > 2 * UNITS_PER_WORD) | |
2128 | return true; | |
2129 | ||
2130 | /* If it is BLKmode and the total size cannot be hold within two registers, | |
2131 | the return value is supposed to be in memory. We need to be aware of | |
2132 | that the size may be -1. */ | |
2133 | if (TYPE_MODE (type) == BLKmode) | |
2134 | if (size < 0 || size > 2 * UNITS_PER_WORD) | |
2135 | return true; | |
2136 | ||
2137 | /* For other cases, having result in memory is unnecessary. */ | |
2138 | return false; | |
9304f876 CJW |
2139 | } |
2140 | ||
2141 | /* -- Function Entry and Exit. */ | |
2142 | ||
2143 | /* The content produced from this function | |
2144 | will be placed before prologue body. */ | |
2145 | static void | |
42776416 | 2146 | nds32_asm_function_prologue (FILE *file) |
9304f876 CJW |
2147 | { |
2148 | int r; | |
2149 | const char *func_name; | |
2150 | tree attrs; | |
2151 | tree name; | |
2152 | ||
2153 | /* All stack frame information is supposed to be | |
2154 | already computed when expanding prologue. | |
2155 | The result is in cfun->machine. | |
2156 | DO NOT call nds32_compute_stack_frame() here | |
2157 | because it may corrupt the essential information. */ | |
2158 | ||
2159 | fprintf (file, "\t! BEGIN PROLOGUE\n"); | |
2160 | fprintf (file, "\t! fp needed: %d\n", frame_pointer_needed); | |
2161 | fprintf (file, "\t! pretend_args: %d\n", cfun->machine->va_args_size); | |
2162 | fprintf (file, "\t! local_size: %d\n", cfun->machine->local_size); | |
2163 | fprintf (file, "\t! out_args_size: %d\n", cfun->machine->out_args_size); | |
2164 | ||
2165 | /* Use df_regs_ever_live_p() to detect if the register | |
2166 | is ever used in the current function. */ | |
2167 | fprintf (file, "\t! registers ever_live: "); | |
e2286268 | 2168 | for (r = 0; r < 65; r++) |
9304f876 CJW |
2169 | { |
2170 | if (df_regs_ever_live_p (r)) | |
2171 | fprintf (file, "%s, ", reg_names[r]); | |
2172 | } | |
2173 | fputc ('\n', file); | |
2174 | ||
2175 | /* Display the attributes of this function. */ | |
2176 | fprintf (file, "\t! function attributes: "); | |
f2dafb91 CJW |
2177 | /* Get the attributes tree list. |
2178 | Note that GCC builds attributes list with reverse order. */ | |
2179 | attrs = DECL_ATTRIBUTES (current_function_decl); | |
9304f876 CJW |
2180 | |
2181 | /* If there is no any attribute, print out "None". */ | |
2182 | if (!attrs) | |
2183 | fprintf (file, "None"); | |
2184 | ||
2185 | /* If there are some attributes, try if we need to | |
2186 | construct isr vector information. */ | |
2187 | func_name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl)); | |
2188 | nds32_construct_isr_vectors_information (attrs, func_name); | |
2189 | ||
2190 | /* Display all attributes of this function. */ | |
2191 | while (attrs) | |
2192 | { | |
2193 | name = TREE_PURPOSE (attrs); | |
2194 | fprintf (file, "%s ", IDENTIFIER_POINTER (name)); | |
2195 | ||
2196 | /* Pick up the next attribute. */ | |
2197 | attrs = TREE_CHAIN (attrs); | |
2198 | } | |
2199 | fputc ('\n', file); | |
2200 | } | |
2201 | ||
2202 | /* After rtl prologue has been expanded, this function is used. */ | |
2203 | static void | |
2204 | nds32_asm_function_end_prologue (FILE *file) | |
2205 | { | |
2206 | fprintf (file, "\t! END PROLOGUE\n"); | |
9304f876 CJW |
2207 | } |
2208 | ||
2209 | /* Before rtl epilogue has been expanded, this function is used. */ | |
2210 | static void | |
2211 | nds32_asm_function_begin_epilogue (FILE *file) | |
2212 | { | |
9304f876 CJW |
2213 | fprintf (file, "\t! BEGIN EPILOGUE\n"); |
2214 | } | |
2215 | ||
2216 | /* The content produced from this function | |
2217 | will be placed after epilogue body. */ | |
2218 | static void | |
42776416 | 2219 | nds32_asm_function_epilogue (FILE *file) |
9304f876 CJW |
2220 | { |
2221 | fprintf (file, "\t! END EPILOGUE\n"); | |
2222 | } | |
2223 | ||
2224 | static void | |
2225 | nds32_asm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, | |
2226 | HOST_WIDE_INT delta, | |
2227 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2228 | tree function) | |
2229 | { | |
f7430263 | 2230 | const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk)); |
9304f876 CJW |
2231 | int this_regno; |
2232 | ||
f7430263 | 2233 | assemble_start_function (thunk, fnname); |
9304f876 CJW |
2234 | /* Make sure unwind info is emitted for the thunk if needed. */ |
2235 | final_start_function (emit_barrier (), file, 1); | |
2236 | ||
2237 | this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) | |
2238 | ? 1 | |
2239 | : 0); | |
2240 | ||
b26fa4f9 KLC |
2241 | if (flag_pic) |
2242 | { | |
2243 | fprintf (file, "\tsmw.adm\t$r31, [$r31], $r31, 4\n"); | |
2244 | fprintf (file, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n", | |
2245 | reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
2246 | fprintf (file, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n", | |
2247 | reg_names [PIC_OFFSET_TABLE_REGNUM], | |
2248 | reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
2249 | ||
2250 | if (TARGET_ISA_V3) | |
2251 | fprintf (file, "\tadd5.pc\t$gp\n"); | |
2252 | else | |
2253 | { | |
2254 | fprintf (file, "\tmfusr\t$ta, $pc\n"); | |
2255 | fprintf (file, "\tadd\t%s, $ta, %s\n", | |
2256 | reg_names [PIC_OFFSET_TABLE_REGNUM], | |
2257 | reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
2258 | } | |
2259 | } | |
2260 | ||
9304f876 CJW |
2261 | if (delta != 0) |
2262 | { | |
2263 | if (satisfies_constraint_Is15 (GEN_INT (delta))) | |
2264 | { | |
5af50159 | 2265 | fprintf (file, "\taddi\t$r%d, $r%d, " HOST_WIDE_INT_PRINT_DEC "\n", |
9304f876 CJW |
2266 | this_regno, this_regno, delta); |
2267 | } | |
2268 | else if (satisfies_constraint_Is20 (GEN_INT (delta))) | |
2269 | { | |
5af50159 | 2270 | fprintf (file, "\tmovi\t$ta, " HOST_WIDE_INT_PRINT_DEC "\n", delta); |
9304f876 CJW |
2271 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); |
2272 | } | |
2273 | else | |
2274 | { | |
5af50159 KC |
2275 | fprintf (file, |
2276 | "\tsethi\t$ta, hi20(" HOST_WIDE_INT_PRINT_DEC ")\n", | |
2277 | delta); | |
2278 | fprintf (file, | |
2279 | "\tori\t$ta, $ta, lo12(" HOST_WIDE_INT_PRINT_DEC ")\n", | |
2280 | delta); | |
9304f876 CJW |
2281 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); |
2282 | } | |
2283 | } | |
2284 | ||
b26fa4f9 KLC |
2285 | if (flag_pic) |
2286 | { | |
2287 | fprintf (file, "\tla\t$ta, "); | |
2288 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2289 | fprintf (file, "@PLT\n"); | |
2290 | fprintf (file, "\t! epilogue\n"); | |
2291 | fprintf (file, "\tlwi.bi\t%s, [%s], 4\n", | |
2292 | reg_names[PIC_OFFSET_TABLE_REGNUM], | |
2293 | reg_names[STACK_POINTER_REGNUM]); | |
2294 | fprintf (file, "\tbr\t$ta\n"); | |
2295 | } | |
2296 | else | |
2297 | { | |
2298 | fprintf (file, "\tb\t"); | |
2299 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2300 | fprintf (file, "\n"); | |
2301 | } | |
9304f876 CJW |
2302 | |
2303 | final_end_function (); | |
f7430263 | 2304 | assemble_end_function (thunk, fnname); |
9304f876 CJW |
2305 | } |
2306 | ||
2307 | /* -- Permitting tail calls. */ | |
2308 | ||
cc48a87f CJW |
2309 | /* Return true if it is ok to do sibling call optimization. */ |
2310 | static bool | |
2311 | nds32_function_ok_for_sibcall (tree decl, | |
2312 | tree exp ATTRIBUTE_UNUSED) | |
2313 | { | |
2314 | /* The DECL is NULL if it is an indirect call. */ | |
2315 | ||
2316 | /* 1. Do not apply sibling call if -mv3push is enabled, | |
2317 | because pop25 instruction also represents return behavior. | |
a4931745 CJW |
2318 | 2. If this function is a isr function, do not apply sibling call |
2319 | because it may perform the behavior that user does not expect. | |
2320 | 3. If this function is a variadic function, do not apply sibling call | |
cc48a87f | 2321 | because the stack layout may be a mess. |
a4931745 | 2322 | 4. We don't want to apply sibling call optimization for indirect |
cc48a87f CJW |
2323 | sibcall because the pop behavior in epilogue may pollute the |
2324 | content of caller-saved regsiter when the register is used for | |
b26fa4f9 | 2325 | indirect sibcall. |
a4931745 | 2326 | 5. In pic mode, it may use some registers for PLT call. */ |
cc48a87f | 2327 | return (!TARGET_V3PUSH |
a4931745 | 2328 | && !nds32_isr_function_p (current_function_decl) |
cc48a87f | 2329 | && (cfun->machine->va_args_size == 0) |
b26fa4f9 KLC |
2330 | && decl |
2331 | && !flag_pic); | |
cc48a87f CJW |
2332 | } |
2333 | ||
9304f876 CJW |
2334 | /* Determine whether we need to enable warning for function return check. */ |
2335 | static bool | |
2336 | nds32_warn_func_return (tree decl) | |
2337 | { | |
8a498f99 CJW |
2338 | /* Naked functions are implemented entirely in assembly, including the |
2339 | return sequence, so suppress warnings about this. */ | |
9304f876 CJW |
2340 | return !nds32_naked_function_p (decl); |
2341 | } | |
2342 | ||
2343 | \f | |
2344 | /* Implementing the Varargs Macros. */ | |
2345 | ||
d4a6a4d9 CJW |
2346 | static void |
2347 | nds32_setup_incoming_varargs (cumulative_args_t ca, | |
e7056ca4 | 2348 | const function_arg_info &arg, |
d4a6a4d9 CJW |
2349 | int *pretend_args_size, |
2350 | int second_time ATTRIBUTE_UNUSED) | |
2351 | { | |
2352 | unsigned int total_args_regs; | |
2353 | unsigned int num_of_used_regs; | |
2354 | unsigned int remaining_reg_count; | |
2355 | CUMULATIVE_ARGS *cum; | |
2356 | ||
2357 | /* If we are under hard float abi, we do not need to set *pretend_args_size. | |
2358 | So that all nameless arguments are pushed by caller and all situation | |
2359 | can be handled by GCC itself. */ | |
2360 | if (TARGET_HARD_FLOAT) | |
2361 | return; | |
2362 | ||
2363 | /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers, | |
2364 | counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments. | |
2365 | However, for nameless(anonymous) arguments, we should push them on the | |
2366 | stack so that all the nameless arguments appear to have been passed | |
2367 | consecutively in the memory for accessing. Hence, we need to check and | |
2368 | exclude the registers that are used for named arguments. */ | |
2369 | ||
2370 | cum = get_cumulative_args (ca); | |
2371 | ||
e7056ca4 | 2372 | /* ARG describes the last argument. |
d4a6a4d9 CJW |
2373 | We need those information to determine the remaining registers |
2374 | for varargs. */ | |
2375 | total_args_regs | |
2376 | = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM; | |
4fe34cdc JM |
2377 | if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))) |
2378 | num_of_used_regs | |
2379 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, arg.mode, arg.type) | |
2380 | + NDS32_NEED_N_REGS_FOR_ARG (arg.mode, arg.type); | |
2381 | else | |
2382 | num_of_used_regs = cum->gpr_offset + NDS32_GPR_ARG_FIRST_REGNUM; | |
d4a6a4d9 CJW |
2383 | |
2384 | remaining_reg_count = total_args_regs - num_of_used_regs; | |
2385 | *pretend_args_size = remaining_reg_count * UNITS_PER_WORD; | |
2386 | ||
2387 | return; | |
2388 | } | |
2389 | ||
9304f876 CJW |
2390 | static bool |
2391 | nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) | |
2392 | { | |
d4a6a4d9 CJW |
2393 | /* If this hook returns true, the named argument of FUNCTION_ARG is always |
2394 | true for named arguments, and false for unnamed arguments. */ | |
9304f876 CJW |
2395 | return true; |
2396 | } | |
2397 | ||
2398 | \f | |
2399 | /* Trampolines for Nested Functions. */ | |
2400 | ||
2401 | static void | |
2402 | nds32_asm_trampoline_template (FILE *f) | |
2403 | { | |
2404 | if (TARGET_REDUCED_REGS) | |
2405 | { | |
2406 | /* Trampoline is not supported on reduced-set registers yet. */ | |
2407 | sorry ("a nested function is not supported for reduced registers"); | |
2408 | } | |
2409 | else | |
2410 | { | |
2411 | asm_fprintf (f, "\t! Trampoline code template\n"); | |
2412 | asm_fprintf (f, "\t! This code fragment will be copied " | |
2413 | "into stack on demand\n"); | |
2414 | ||
2415 | asm_fprintf (f, "\tmfusr\t$r16,$pc\n"); | |
2416 | asm_fprintf (f, "\tlwi\t$r15,[$r16 + 20] " | |
2417 | "! load nested function address\n"); | |
2418 | asm_fprintf (f, "\tlwi\t$r16,[$r16 + 16] " | |
2419 | "! load chain_value\n"); | |
2420 | asm_fprintf (f, "\tjr\t$r15\n"); | |
2421 | } | |
2422 | ||
2423 | /* Preserve space ($pc + 16) for saving chain_value, | |
2424 | nds32_trampoline_init will fill the value in this slot. */ | |
2425 | asm_fprintf (f, "\t! space for saving chain_value\n"); | |
2426 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2427 | ||
2428 | /* Preserve space ($pc + 20) for saving nested function address, | |
2429 | nds32_trampoline_init will fill the value in this slot. */ | |
2430 | asm_fprintf (f, "\t! space for saving nested function address\n"); | |
2431 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2432 | } | |
2433 | ||
2434 | /* Emit RTL insns to initialize the variable parts of a trampoline. */ | |
2435 | static void | |
2436 | nds32_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2437 | { | |
2438 | int i; | |
2439 | ||
2440 | /* Nested function address. */ | |
2441 | rtx fnaddr; | |
2442 | /* The memory rtx that is going to | |
2443 | be filled with chain_value. */ | |
2444 | rtx chain_value_mem; | |
2445 | /* The memory rtx that is going to | |
2446 | be filled with nested function address. */ | |
2447 | rtx nested_func_mem; | |
2448 | ||
2449 | /* Start address of trampoline code in stack, for doing cache sync. */ | |
2450 | rtx sync_cache_addr; | |
2451 | /* Temporary register for sync instruction. */ | |
2452 | rtx tmp_reg; | |
2453 | /* Instruction-cache sync instruction, | |
2454 | requesting an argument as starting address. */ | |
2455 | rtx isync_insn; | |
2456 | /* For convenience reason of doing comparison. */ | |
2457 | int tramp_align_in_bytes; | |
2458 | ||
2459 | /* Trampoline is not supported on reduced-set registers yet. */ | |
2460 | if (TARGET_REDUCED_REGS) | |
2461 | sorry ("a nested function is not supported for reduced registers"); | |
2462 | ||
2463 | /* STEP 1: Copy trampoline code template into stack, | |
8a498f99 | 2464 | fill up essential data into stack. */ |
9304f876 CJW |
2465 | |
2466 | /* Extract nested function address rtx. */ | |
2467 | fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2468 | ||
2469 | /* m_tramp is memory rtx that is going to be filled with trampoline code. | |
2470 | We have nds32_asm_trampoline_template() to emit template pattern. */ | |
2471 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2472 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2473 | ||
2474 | /* After copying trampoline code into stack, | |
2475 | fill chain_value into stack. */ | |
2476 | chain_value_mem = adjust_address (m_tramp, SImode, 16); | |
2477 | emit_move_insn (chain_value_mem, chain_value); | |
2478 | /* After copying trampoline code int stack, | |
2479 | fill nested function address into stack. */ | |
2480 | nested_func_mem = adjust_address (m_tramp, SImode, 20); | |
2481 | emit_move_insn (nested_func_mem, fnaddr); | |
2482 | ||
2483 | /* STEP 2: Sync instruction-cache. */ | |
2484 | ||
2485 | /* We have successfully filled trampoline code into stack. | |
2486 | However, in order to execute code in stack correctly, | |
2487 | we must sync instruction cache. */ | |
2488 | sync_cache_addr = XEXP (m_tramp, 0); | |
2489 | tmp_reg = gen_reg_rtx (SImode); | |
2490 | isync_insn = gen_unspec_volatile_isync (tmp_reg); | |
2491 | ||
2492 | /* Because nds32_cache_block_size is in bytes, | |
2493 | we get trampoline alignment in bytes for convenient comparison. */ | |
2494 | tramp_align_in_bytes = TRAMPOLINE_ALIGNMENT / BITS_PER_UNIT; | |
2495 | ||
2496 | if (tramp_align_in_bytes >= nds32_cache_block_size | |
2497 | && (tramp_align_in_bytes % nds32_cache_block_size) == 0) | |
2498 | { | |
2499 | /* Under this condition, the starting address of trampoline | |
8a498f99 CJW |
2500 | must be aligned to the starting address of each cache block |
2501 | and we do not have to worry about cross-boundary issue. */ | |
9304f876 CJW |
2502 | for (i = 0; |
2503 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
2504 | / nds32_cache_block_size; | |
2505 | i++) | |
2506 | { | |
2507 | emit_move_insn (tmp_reg, | |
2508 | plus_constant (Pmode, sync_cache_addr, | |
2509 | nds32_cache_block_size * i)); | |
2510 | emit_insn (isync_insn); | |
2511 | } | |
2512 | } | |
2513 | else if (TRAMPOLINE_SIZE > nds32_cache_block_size) | |
2514 | { | |
2515 | /* The starting address of trampoline code | |
8a498f99 CJW |
2516 | may not be aligned to the cache block, |
2517 | so the trampoline code may be across two cache block. | |
2518 | We need to sync the last element, which is 4-byte size, | |
2519 | of trampoline template. */ | |
9304f876 CJW |
2520 | for (i = 0; |
2521 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
2522 | / nds32_cache_block_size; | |
2523 | i++) | |
2524 | { | |
2525 | emit_move_insn (tmp_reg, | |
2526 | plus_constant (Pmode, sync_cache_addr, | |
2527 | nds32_cache_block_size * i)); | |
2528 | emit_insn (isync_insn); | |
2529 | } | |
2530 | ||
2531 | /* The last element of trampoline template is 4-byte size. */ | |
2532 | emit_move_insn (tmp_reg, | |
2533 | plus_constant (Pmode, sync_cache_addr, | |
2534 | TRAMPOLINE_SIZE - 4)); | |
2535 | emit_insn (isync_insn); | |
2536 | } | |
2537 | else | |
2538 | { | |
2539 | /* This is the simplest case. | |
8a498f99 CJW |
2540 | Because TRAMPOLINE_SIZE is less than or |
2541 | equal to nds32_cache_block_size, | |
2542 | we can just sync start address and | |
2543 | the last element of trampoline code. */ | |
9304f876 CJW |
2544 | |
2545 | /* Sync starting address of tampoline code. */ | |
2546 | emit_move_insn (tmp_reg, sync_cache_addr); | |
2547 | emit_insn (isync_insn); | |
2548 | /* Sync the last element, which is 4-byte size, | |
8a498f99 | 2549 | of trampoline template. */ |
9304f876 CJW |
2550 | emit_move_insn (tmp_reg, |
2551 | plus_constant (Pmode, sync_cache_addr, | |
2552 | TRAMPOLINE_SIZE - 4)); | |
2553 | emit_insn (isync_insn); | |
2554 | } | |
2555 | ||
2556 | /* Set instruction serialization barrier | |
2557 | to guarantee the correct operations. */ | |
2558 | emit_insn (gen_unspec_volatile_isb ()); | |
2559 | } | |
2560 | ||
2561 | \f | |
2562 | /* Addressing Modes. */ | |
2563 | ||
2564 | static bool | |
165b1f6a KL |
2565 | nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict, |
2566 | code_helper = ERROR_MARK) | |
9304f876 | 2567 | { |
e2286268 MC |
2568 | if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) |
2569 | { | |
2570 | /* When using floating-point instructions, | |
2571 | we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */ | |
2572 | if ((mode == DFmode || mode == SFmode) | |
2573 | && (GET_CODE (x) == SYMBOL_REF | |
2574 | || GET_CODE(x) == CONST)) | |
2575 | return false; | |
2576 | ||
2577 | /* Allow [post_modify] addressing mode, when using FPU instructions. */ | |
2578 | if (GET_CODE (x) == POST_MODIFY | |
2579 | && mode == DFmode) | |
2580 | { | |
2581 | if (GET_CODE (XEXP (x, 0)) == REG | |
2582 | && GET_CODE (XEXP (x, 1)) == PLUS) | |
2583 | { | |
2584 | rtx plus_op = XEXP (x, 1); | |
2585 | rtx op0 = XEXP (plus_op, 0); | |
2586 | rtx op1 = XEXP (plus_op, 1); | |
2587 | ||
2588 | if (nds32_address_register_rtx_p (op0, strict) | |
2589 | && CONST_INT_P (op1)) | |
2590 | { | |
2591 | if (satisfies_constraint_Is14 (op1)) | |
2592 | { | |
5f2a98c3 CJW |
2593 | /* If it is not under strictly aligned situation, |
2594 | we can return true without checking alignment. */ | |
2595 | if (!cfun->machine->strict_aligned_p) | |
2596 | return true; | |
e2286268 MC |
2597 | /* Make sure address is word alignment. |
2598 | Currently we do not have 64-bit load/store yet, | |
2599 | so we will use two 32-bit load/store instructions to do | |
2600 | memory access and they are single word alignment. */ | |
5f2a98c3 | 2601 | else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (op1))) |
e2286268 MC |
2602 | return true; |
2603 | } | |
2604 | } | |
2605 | } | |
2606 | } | |
2607 | } | |
2608 | ||
9304f876 CJW |
2609 | /* For (mem:DI addr) or (mem:DF addr) case, |
2610 | we only allow 'addr' to be [reg], [symbol_ref], | |
8a498f99 | 2611 | [const], or [reg + const_int] pattern. */ |
9304f876 CJW |
2612 | if (mode == DImode || mode == DFmode) |
2613 | { | |
2614 | /* Allow [Reg + const_int] addressing mode. */ | |
2615 | if (GET_CODE (x) == PLUS) | |
2616 | { | |
2617 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) | |
2618 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict) | |
2619 | && CONST_INT_P (XEXP (x, 1))) | |
2620 | return true; | |
9304f876 CJW |
2621 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) |
2622 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict) | |
2623 | && CONST_INT_P (XEXP (x, 0))) | |
2624 | return true; | |
2625 | } | |
2626 | ||
e2286268 MC |
2627 | /* Allow [post_inc] and [post_dec] addressing mode. */ |
2628 | if (GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) | |
2629 | { | |
2630 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) | |
2631 | return true; | |
2632 | } | |
2633 | ||
9304f876 CJW |
2634 | /* Now check [reg], [symbol_ref], and [const]. */ |
2635 | if (GET_CODE (x) != REG | |
2636 | && GET_CODE (x) != SYMBOL_REF | |
2637 | && GET_CODE (x) != CONST) | |
2638 | return false; | |
2639 | } | |
2640 | ||
2641 | /* Check if 'x' is a valid address. */ | |
2642 | switch (GET_CODE (x)) | |
2643 | { | |
2644 | case REG: | |
2645 | /* (mem (reg A)) => [Ra] */ | |
2646 | return nds32_address_register_rtx_p (x, strict); | |
2647 | ||
2648 | case SYMBOL_REF: | |
4855be84 | 2649 | /* (mem (symbol_ref A)) => [symbol_ref] */ |
b26fa4f9 KLC |
2650 | |
2651 | if (flag_pic || SYMBOL_REF_TLS_MODEL (x)) | |
2652 | return false; | |
2653 | ||
85a98076 KLC |
2654 | if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) |
2655 | return false; | |
2656 | ||
4855be84 | 2657 | /* If -mcmodel=large, the 'symbol_ref' is not a valid address |
8a498f99 | 2658 | during or after LRA/reload phase. */ |
4855be84 | 2659 | if (TARGET_CMODEL_LARGE |
9304f876 CJW |
2660 | && (reload_completed |
2661 | || reload_in_progress | |
2662 | || lra_in_progress)) | |
2663 | return false; | |
4855be84 | 2664 | /* If -mcmodel=medium and the symbol references to rodata section, |
8a498f99 CJW |
2665 | the 'symbol_ref' is not a valid address during or after |
2666 | LRA/reload phase. */ | |
4855be84 | 2667 | if (TARGET_CMODEL_MEDIUM |
b26fa4f9 KLC |
2668 | && (NDS32_SYMBOL_REF_RODATA_P (x) |
2669 | || CONSTANT_POOL_ADDRESS_P (x)) | |
9304f876 CJW |
2670 | && (reload_completed |
2671 | || reload_in_progress | |
2672 | || lra_in_progress)) | |
2673 | return false; | |
2674 | ||
4855be84 CJW |
2675 | return true; |
2676 | ||
2677 | case CONST: | |
9304f876 | 2678 | /* (mem (const (...))) |
8a498f99 | 2679 | => [ + const_addr ], where const_addr = symbol_ref + const_int */ |
9304f876 CJW |
2680 | if (GET_CODE (XEXP (x, 0)) == PLUS) |
2681 | { | |
2682 | rtx plus_op = XEXP (x, 0); | |
2683 | ||
2684 | rtx op0 = XEXP (plus_op, 0); | |
2685 | rtx op1 = XEXP (plus_op, 1); | |
2686 | ||
2687 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
4855be84 CJW |
2688 | { |
2689 | /* Now we see the [ + const_addr ] pattern, but we need | |
8a498f99 | 2690 | some further checking. */ |
b26fa4f9 | 2691 | |
4a7df256 | 2692 | if (flag_pic || SYMBOL_REF_TLS_MODEL (op0)) |
b26fa4f9 KLC |
2693 | return false; |
2694 | ||
4855be84 | 2695 | /* If -mcmodel=large, the 'const_addr' is not a valid address |
8a498f99 | 2696 | during or after LRA/reload phase. */ |
4855be84 CJW |
2697 | if (TARGET_CMODEL_LARGE |
2698 | && (reload_completed | |
2699 | || reload_in_progress | |
2700 | || lra_in_progress)) | |
2701 | return false; | |
2702 | /* If -mcmodel=medium and the symbol references to rodata section, | |
8a498f99 CJW |
2703 | the 'const_addr' is not a valid address during or after |
2704 | LRA/reload phase. */ | |
4855be84 CJW |
2705 | if (TARGET_CMODEL_MEDIUM |
2706 | && NDS32_SYMBOL_REF_RODATA_P (op0) | |
2707 | && (reload_completed | |
2708 | || reload_in_progress | |
2709 | || lra_in_progress)) | |
2710 | return false; | |
2711 | ||
2712 | /* At this point we can make sure 'const_addr' is a | |
2713 | valid address. */ | |
2714 | return true; | |
2715 | } | |
9304f876 CJW |
2716 | } |
2717 | ||
2718 | return false; | |
2719 | ||
2720 | case POST_MODIFY: | |
2721 | /* (mem (post_modify (reg) (plus (reg) (reg)))) | |
8a498f99 | 2722 | => [Ra], Rb */ |
9304f876 | 2723 | /* (mem (post_modify (reg) (plus (reg) (const_int)))) |
8a498f99 | 2724 | => [Ra], const_int */ |
9304f876 CJW |
2725 | if (GET_CODE (XEXP (x, 0)) == REG |
2726 | && GET_CODE (XEXP (x, 1)) == PLUS) | |
2727 | { | |
2728 | rtx plus_op = XEXP (x, 1); | |
2729 | ||
2730 | rtx op0 = XEXP (plus_op, 0); | |
2731 | rtx op1 = XEXP (plus_op, 1); | |
2732 | ||
2733 | if (nds32_address_register_rtx_p (op0, strict) | |
2734 | && nds32_legitimate_index_p (mode, op1, strict)) | |
2735 | return true; | |
2736 | else | |
2737 | return false; | |
2738 | } | |
2739 | ||
2740 | return false; | |
2741 | ||
2742 | case POST_INC: | |
2743 | case POST_DEC: | |
2744 | /* (mem (post_inc reg)) => [Ra], 1/2/4 */ | |
2745 | /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */ | |
2746 | /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
8a498f99 | 2747 | We only need to deal with register Ra. */ |
9304f876 CJW |
2748 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) |
2749 | return true; | |
2750 | else | |
2751 | return false; | |
2752 | ||
2753 | case PLUS: | |
2754 | /* (mem (plus reg const_int)) | |
8a498f99 | 2755 | => [Ra + imm] */ |
9304f876 | 2756 | /* (mem (plus reg reg)) |
8a498f99 | 2757 | => [Ra + Rb] */ |
9304f876 | 2758 | /* (mem (plus (mult reg const_int) reg)) |
8a498f99 | 2759 | => [Ra + Rb << sv] */ |
9304f876 CJW |
2760 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) |
2761 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)) | |
2762 | return true; | |
2763 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) | |
2764 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)) | |
2765 | return true; | |
2766 | else | |
2767 | return false; | |
2768 | ||
2769 | case LO_SUM: | |
34425025 | 2770 | /* (mem (lo_sum (reg) (symbol_ref))) */ |
85a98076 | 2771 | /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */ |
b26fa4f9 KLC |
2772 | /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */ |
2773 | /* The LO_SUM is a valid address if and only if we would like to | |
2774 | generate 32-bit full address memory access with any of following | |
2775 | circumstance: | |
2776 | 1. -mcmodel=large. | |
2777 | 2. -mcmodel=medium and the symbol_ref references to rodata. */ | |
85a98076 KLC |
2778 | { |
2779 | rtx sym = NULL_RTX; | |
2780 | ||
b26fa4f9 KLC |
2781 | if (flag_pic) |
2782 | return false; | |
2783 | ||
85a98076 KLC |
2784 | if (!REG_P (XEXP (x, 0))) |
2785 | return false; | |
2786 | ||
2787 | if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
2788 | sym = XEXP (x, 1); | |
2789 | else if (GET_CODE (XEXP (x, 1)) == CONST) | |
2790 | { | |
2791 | rtx plus = XEXP(XEXP (x, 1), 0); | |
2792 | if (GET_CODE (plus) == PLUS) | |
2793 | sym = XEXP (plus, 0); | |
2794 | else if (GET_CODE (plus) == UNSPEC) | |
2795 | sym = XVECEXP (plus, 0, 0); | |
2796 | } | |
2797 | else | |
2798 | return false; | |
2799 | ||
2800 | gcc_assert (GET_CODE (sym) == SYMBOL_REF); | |
2801 | ||
2802 | if (TARGET_ICT_MODEL_LARGE | |
2803 | && nds32_indirect_call_referenced_p (sym)) | |
2804 | return true; | |
2805 | ||
2806 | if (TARGET_CMODEL_LARGE) | |
2807 | return true; | |
2808 | else if (TARGET_CMODEL_MEDIUM | |
2809 | && NDS32_SYMBOL_REF_RODATA_P (sym)) | |
2810 | return true; | |
2811 | else | |
2812 | return false; | |
2813 | } | |
9304f876 CJW |
2814 | |
2815 | default: | |
2816 | return false; | |
2817 | } | |
2818 | } | |
2819 | ||
85a98076 KLC |
2820 | static rtx |
2821 | nds32_legitimize_address (rtx x, | |
2822 | rtx oldx ATTRIBUTE_UNUSED, | |
2823 | machine_mode mode ATTRIBUTE_UNUSED) | |
2824 | { | |
b26fa4f9 KLC |
2825 | if (nds32_tls_referenced_p (x)) |
2826 | x = nds32_legitimize_tls_address (x); | |
2827 | else if (flag_pic && SYMBOLIC_CONST_P (x)) | |
2828 | x = nds32_legitimize_pic_address (x); | |
2829 | else if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) | |
85a98076 KLC |
2830 | x = nds32_legitimize_ict_address (x); |
2831 | ||
2832 | return x; | |
2833 | } | |
2834 | ||
2835 | static bool | |
2836 | nds32_legitimate_constant_p (machine_mode mode, rtx x) | |
2837 | { | |
2838 | switch (GET_CODE (x)) | |
2839 | { | |
2840 | case CONST_DOUBLE: | |
2841 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
2842 | && (mode == DFmode || mode == SFmode)) | |
2843 | return false; | |
2844 | break; | |
2845 | case CONST: | |
2846 | x = XEXP (x, 0); | |
2847 | ||
2848 | if (GET_CODE (x) == PLUS) | |
2849 | { | |
2850 | if (!CONST_INT_P (XEXP (x, 1))) | |
2851 | return false; | |
2852 | x = XEXP (x, 0); | |
2853 | } | |
2854 | ||
2855 | if (GET_CODE (x) == UNSPEC) | |
2856 | { | |
2857 | switch (XINT (x, 1)) | |
2858 | { | |
b26fa4f9 KLC |
2859 | case UNSPEC_GOT: |
2860 | case UNSPEC_GOTOFF: | |
2861 | case UNSPEC_PLT: | |
2862 | case UNSPEC_TLSGD: | |
2863 | case UNSPEC_TLSLD: | |
2864 | case UNSPEC_TLSIE: | |
2865 | case UNSPEC_TLSLE: | |
85a98076 KLC |
2866 | case UNSPEC_ICT: |
2867 | return false; | |
2868 | default: | |
2869 | return true; | |
2870 | } | |
2871 | } | |
2872 | break; | |
b26fa4f9 KLC |
2873 | case SYMBOL_REF: |
2874 | /* TLS symbols need a call to resolve in | |
2875 | precompute_register_parameters. */ | |
2876 | if (SYMBOL_REF_TLS_MODEL (x)) | |
2877 | return false; | |
2878 | break; | |
85a98076 KLC |
2879 | default: |
2880 | return true; | |
2881 | } | |
2882 | ||
2883 | return true; | |
2884 | } | |
2885 | ||
2886 | /* Reorgnize the UNSPEC CONST and return its direct symbol. */ | |
2887 | static rtx | |
2888 | nds32_delegitimize_address (rtx x) | |
2889 | { | |
2890 | x = delegitimize_mem_from_attrs (x); | |
2891 | ||
2892 | if (GET_CODE(x) == CONST) | |
2893 | { | |
2894 | rtx inner = XEXP (x, 0); | |
2895 | ||
2896 | /* Handle for GOTOFF. */ | |
2897 | if (GET_CODE (inner) == PLUS) | |
2898 | inner = XEXP (inner, 0); | |
2899 | ||
2900 | if (GET_CODE (inner) == UNSPEC) | |
2901 | { | |
2902 | switch (XINT (inner, 1)) | |
2903 | { | |
b26fa4f9 KLC |
2904 | case UNSPEC_GOTINIT: |
2905 | case UNSPEC_GOT: | |
2906 | case UNSPEC_GOTOFF: | |
2907 | case UNSPEC_PLT: | |
2908 | case UNSPEC_TLSGD: | |
2909 | case UNSPEC_TLSLD: | |
2910 | case UNSPEC_TLSIE: | |
2911 | case UNSPEC_TLSLE: | |
85a98076 KLC |
2912 | case UNSPEC_ICT: |
2913 | x = XVECEXP (inner, 0, 0); | |
2914 | break; | |
2915 | default: | |
2916 | break; | |
2917 | } | |
2918 | } | |
2919 | } | |
2920 | return x; | |
2921 | } | |
2922 | ||
7c32ef41 MC |
2923 | static machine_mode |
2924 | nds32_vectorize_preferred_simd_mode (scalar_mode mode) | |
2925 | { | |
2926 | if (!NDS32_EXT_DSP_P ()) | |
2927 | return word_mode; | |
2928 | ||
2929 | switch (mode) | |
2930 | { | |
2931 | case E_QImode: | |
2932 | return V4QImode; | |
2933 | case E_HImode: | |
2934 | return V2HImode; | |
2935 | default: | |
2936 | return word_mode; | |
2937 | } | |
2938 | } | |
2939 | ||
85a98076 KLC |
2940 | static bool |
2941 | nds32_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
2942 | { | |
2943 | switch (GET_CODE (x)) | |
2944 | { | |
2945 | case CONST: | |
2946 | return !nds32_legitimate_constant_p (mode, x); | |
2947 | case SYMBOL_REF: | |
2948 | /* All symbols have to be accessed through gp-relative in PIC mode. */ | |
2949 | /* We don't want to force symbol as constant pool in .text section, | |
2950 | because we use the gp-relatived instruction to load in small | |
2951 | or medium model. */ | |
b26fa4f9 KLC |
2952 | if (flag_pic |
2953 | || SYMBOL_REF_TLS_MODEL (x) | |
85a98076 KLC |
2954 | || TARGET_CMODEL_SMALL |
2955 | || TARGET_CMODEL_MEDIUM) | |
2956 | return true; | |
2957 | break; | |
b26fa4f9 KLC |
2958 | case CONST_INT: |
2959 | case CONST_DOUBLE: | |
2960 | if (flag_pic && (lra_in_progress || reload_completed)) | |
2961 | return true; | |
2962 | break; | |
85a98076 KLC |
2963 | default: |
2964 | return false; | |
2965 | } | |
2966 | return false; | |
2967 | } | |
2968 | ||
5b6f2bf3 CJW |
2969 | \f |
2970 | /* Condition Code Status. */ | |
2971 | ||
2972 | /* -- Representation of condition codes using registers. */ | |
2973 | ||
2974 | static void | |
2975 | nds32_canonicalize_comparison (int *code, | |
2976 | rtx *op0 ATTRIBUTE_UNUSED, | |
2977 | rtx *op1, | |
2978 | bool op0_preserve_value ATTRIBUTE_UNUSED) | |
2979 | { | |
2980 | /* When the instruction combination pass tries to combine a comparison insn | |
2981 | with its previous insns, it also transforms the operator in order to | |
2982 | minimize its constant field. For example, it tries to transform a | |
2983 | comparison insn from | |
2984 | (set (reg:SI 54) | |
2985 | (ltu:SI (reg:SI 52) | |
2986 | (const_int 10 [0xa]))) | |
2987 | to | |
2988 | (set (reg:SI 54) | |
2989 | (leu:SI (reg:SI 52) | |
2990 | (const_int 9 [0x9]))) | |
2991 | ||
2992 | However, the nds32 target only provides instructions supporting the LTU | |
2993 | operation directly, and the implementation of the pattern "cbranchsi4" | |
2994 | only expands the LTU form. In order to handle the non-LTU operations | |
2995 | generated from passes other than the RTL expansion pass, we have to | |
2996 | implement this hook to revert those changes. Since we only expand the LTU | |
2997 | operator in the RTL expansion pass, we might only need to handle the LEU | |
2998 | case, unless we find other optimization passes perform more aggressive | |
2999 | transformations. */ | |
3000 | ||
3001 | if (*code == LEU && CONST_INT_P (*op1)) | |
3002 | { | |
3003 | *op1 = gen_int_mode (INTVAL (*op1) + 1, SImode); | |
3004 | *code = LTU; | |
3005 | } | |
3006 | } | |
3007 | ||
9304f876 CJW |
3008 | \f |
3009 | /* Describing Relative Costs of Operations. */ | |
3010 | ||
19ac960a | 3011 | static int |
69e7672a | 3012 | nds32_register_move_cost (machine_mode mode, |
19ac960a CJW |
3013 | reg_class_t from, |
3014 | reg_class_t to) | |
9304f876 | 3015 | { |
69e7672a KC |
3016 | /* In garywolf cpu, FPR to GPR is chaper than other cpu. */ |
3017 | if (TARGET_PIPELINE_GRAYWOLF) | |
3018 | { | |
3019 | if (GET_MODE_SIZE (mode) == 8) | |
3020 | { | |
3021 | /* DPR to GPR. */ | |
3022 | if (from == FP_REGS && to != FP_REGS) | |
3023 | return 3; | |
3024 | /* GPR to DPR. */ | |
3025 | if (from != FP_REGS && to == FP_REGS) | |
3026 | return 2; | |
3027 | } | |
3028 | else | |
3029 | { | |
3030 | if ((from == FP_REGS && to != FP_REGS) | |
3031 | || (from != FP_REGS && to == FP_REGS)) | |
3032 | return 2; | |
3033 | } | |
3034 | } | |
3035 | ||
e2286268 MC |
3036 | if ((from == FP_REGS && to != FP_REGS) |
3037 | || (from != FP_REGS && to == FP_REGS)) | |
69e7672a | 3038 | return 3; |
e2286268 MC |
3039 | else if (from == HIGH_REGS || to == HIGH_REGS) |
3040 | return optimize_size ? 6 : 2; | |
3041 | else | |
3042 | return 2; | |
9304f876 CJW |
3043 | } |
3044 | ||
19ac960a | 3045 | static int |
ef4bddc2 | 3046 | nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
19ac960a CJW |
3047 | reg_class_t rclass ATTRIBUTE_UNUSED, |
3048 | bool in ATTRIBUTE_UNUSED) | |
9304f876 CJW |
3049 | { |
3050 | return 8; | |
3051 | } | |
3052 | ||
3053 | /* This target hook describes the relative costs of RTL expressions. | |
3054 | Return 'true' when all subexpressions of x have been processed. | |
3055 | Return 'false' to sum the costs of sub-rtx, plus cost of this operation. | |
e53b6e56 | 3056 | Refer to gcc/rtlanal.cc for more information. */ |
9304f876 CJW |
3057 | static bool |
3058 | nds32_rtx_costs (rtx x, | |
e548c9df | 3059 | machine_mode mode, |
9304f876 | 3060 | int outer_code, |
89a4b547 | 3061 | int opno, |
9304f876 CJW |
3062 | int *total, |
3063 | bool speed) | |
3064 | { | |
e548c9df | 3065 | return nds32_rtx_costs_impl (x, mode, outer_code, opno, total, speed); |
9304f876 CJW |
3066 | } |
3067 | ||
19ac960a CJW |
3068 | static int |
3069 | nds32_address_cost (rtx address, | |
ef4bddc2 | 3070 | machine_mode mode, |
19ac960a CJW |
3071 | addr_space_t as, |
3072 | bool speed) | |
9304f876 | 3073 | { |
89a4b547 | 3074 | return nds32_address_cost_impl (address, mode, as, speed); |
9304f876 CJW |
3075 | } |
3076 | ||
511a41d7 CJW |
3077 | \f |
3078 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
3079 | ||
3080 | /* If references to a symbol or a constant must be treated differently | |
3081 | depending on something about the variable or function named by the symbol | |
3082 | (such as what section it is in), we use this hook to store flags | |
3083 | in symbol_ref rtx. */ | |
3084 | static void | |
3085 | nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p) | |
3086 | { | |
3087 | default_encode_section_info (decl, rtl, new_decl_p); | |
3088 | ||
3089 | /* For the memory rtx, if it references to rodata section, we can store | |
3090 | NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the | |
3091 | nds32_legitimate_address_p() can determine how to treat such symbol_ref | |
3092 | based on -mcmodel=X and this information. */ | |
3093 | if (MEM_P (rtl) && MEM_READONLY_P (rtl)) | |
3094 | { | |
3095 | rtx addr = XEXP (rtl, 0); | |
3096 | ||
3097 | if (GET_CODE (addr) == SYMBOL_REF) | |
3098 | { | |
3099 | /* For (mem (symbol_ref X)) case. */ | |
3100 | SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA; | |
3101 | } | |
3102 | else if (GET_CODE (addr) == CONST | |
3103 | && GET_CODE (XEXP (addr, 0)) == PLUS) | |
3104 | { | |
3105 | /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */ | |
3106 | rtx plus_op = XEXP (addr, 0); | |
3107 | rtx op0 = XEXP (plus_op, 0); | |
3108 | rtx op1 = XEXP (plus_op, 1); | |
3109 | ||
3110 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
3111 | SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA; | |
3112 | } | |
3113 | } | |
3114 | } | |
3115 | ||
9304f876 CJW |
3116 | \f |
3117 | /* Defining the Output Assembler Language. */ | |
3118 | ||
3119 | /* -- The Overall Framework of an Assembler File. */ | |
3120 | ||
3121 | static void | |
3122 | nds32_asm_file_start (void) | |
3123 | { | |
9304f876 CJW |
3124 | default_file_start (); |
3125 | ||
b26fa4f9 KLC |
3126 | if (flag_pic) |
3127 | fprintf (asm_out_file, "\t.pic\n"); | |
3128 | ||
9304f876 CJW |
3129 | /* Tell assembler which ABI we are using. */ |
3130 | fprintf (asm_out_file, "\t! ABI version\n"); | |
e2286268 MC |
3131 | if (TARGET_HARD_FLOAT) |
3132 | fprintf (asm_out_file, "\t.abi_2fp_plus\n"); | |
3133 | else | |
3134 | fprintf (asm_out_file, "\t.abi_2\n"); | |
9304f876 CJW |
3135 | |
3136 | /* Tell assembler that this asm code is generated by compiler. */ | |
3137 | fprintf (asm_out_file, "\t! This asm file is generated by compiler\n"); | |
3138 | fprintf (asm_out_file, "\t.flag\tverbatim\n"); | |
85a98076 | 3139 | |
cf3cd43d CJW |
3140 | /* Insert directive for linker to distinguish object's ict flag. */ |
3141 | if (!TARGET_LINUX_ABI) | |
3142 | { | |
3143 | if (TARGET_ICT_MODEL_LARGE) | |
3144 | fprintf (asm_out_file, "\t.ict_model\tlarge\n"); | |
3145 | else | |
3146 | fprintf (asm_out_file, "\t.ict_model\tsmall\n"); | |
3147 | } | |
3148 | ||
3149 | /* We need to provide the size of each vector for interrupt handler | |
3150 | under elf toolchain. */ | |
3151 | if (!TARGET_LINUX_ABI) | |
3152 | { | |
3153 | fprintf (asm_out_file, "\t! This vector size directive is required " | |
3154 | "for checking inconsistency on interrupt handler\n"); | |
3155 | fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); | |
3156 | } | |
9304f876 | 3157 | |
2140297c CJW |
3158 | /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os, |
3159 | the compiler may produce 'la $fp,_FP_BASE_' instruction | |
3160 | at prologue for fp-as-gp optimization. | |
3161 | We should emit weak reference of _FP_BASE_ to avoid undefined reference | |
3162 | in case user does not pass '--relax' option to linker. */ | |
cf3cd43d | 3163 | if (!TARGET_LINUX_ABI && (TARGET_FORCE_FP_AS_GP || optimize_size)) |
2140297c CJW |
3164 | { |
3165 | fprintf (asm_out_file, "\t! This weak reference is required to do " | |
3166 | "fp-as-gp link time optimization\n"); | |
3167 | fprintf (asm_out_file, "\t.weak\t_FP_BASE_\n"); | |
3168 | } | |
3169 | ||
9304f876 CJW |
3170 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
3171 | ||
3172 | if (TARGET_ISA_V2) | |
3173 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V2"); | |
3174 | if (TARGET_ISA_V3) | |
3175 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3"); | |
3176 | if (TARGET_ISA_V3M) | |
3177 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M"); | |
3178 | ||
dd000841 CJW |
3179 | switch (nds32_cpu_option) |
3180 | { | |
3181 | case CPU_N6: | |
3182 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N6"); | |
3183 | break; | |
3184 | ||
3185 | case CPU_N7: | |
3186 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N7"); | |
3187 | break; | |
3188 | ||
3189 | case CPU_N8: | |
3190 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N8"); | |
3191 | break; | |
3192 | ||
3193 | case CPU_E8: | |
3194 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "E8"); | |
3195 | break; | |
3196 | ||
3197 | case CPU_N9: | |
3198 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N9"); | |
3199 | break; | |
3200 | ||
3201 | case CPU_N10: | |
3202 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N10"); | |
3203 | break; | |
3204 | ||
3205 | case CPU_GRAYWOLF: | |
3206 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "Graywolf"); | |
3207 | break; | |
3208 | ||
3209 | case CPU_N12: | |
3210 | case CPU_N13: | |
3211 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N13"); | |
3212 | break; | |
3213 | ||
3214 | case CPU_SIMPLE: | |
3215 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "SIMPLE"); | |
3216 | break; | |
3217 | ||
3218 | default: | |
3219 | gcc_unreachable (); | |
3220 | } | |
3221 | ||
77b7a1ca CJW |
3222 | if (TARGET_CMODEL_SMALL) |
3223 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL"); | |
3224 | if (TARGET_CMODEL_MEDIUM) | |
3225 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "MEDIUM"); | |
3226 | if (TARGET_CMODEL_LARGE) | |
3227 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "LARGE"); | |
3228 | ||
9304f876 CJW |
3229 | fprintf (asm_out_file, "\t! Endian setting\t: %s\n", |
3230 | ((TARGET_BIG_ENDIAN) ? "big-endian" | |
3231 | : "little-endian")); | |
e2286268 MC |
3232 | fprintf (asm_out_file, "\t! Use SP floating-point instruction\t: %s\n", |
3233 | ((TARGET_FPU_SINGLE) ? "Yes" | |
3234 | : "No")); | |
3235 | fprintf (asm_out_file, "\t! Use DP floating-point instruction\t: %s\n", | |
3236 | ((TARGET_FPU_DOUBLE) ? "Yes" | |
3237 | : "No")); | |
3238 | fprintf (asm_out_file, "\t! ABI version\t\t: %s\n", | |
3239 | ((TARGET_HARD_FLOAT) ? "ABI2FP+" | |
3240 | : "ABI2")); | |
9304f876 CJW |
3241 | |
3242 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3243 | ||
3244 | fprintf (asm_out_file, "\t! Use conditional move\t\t: %s\n", | |
3245 | ((TARGET_CMOV) ? "Yes" | |
3246 | : "No")); | |
3247 | fprintf (asm_out_file, "\t! Use performance extension\t: %s\n", | |
aa4b851c | 3248 | ((TARGET_EXT_PERF) ? "Yes" |
9304f876 | 3249 | : "No")); |
aa4b851c CJW |
3250 | fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n", |
3251 | ((TARGET_EXT_PERF2) ? "Yes" | |
3252 | : "No")); | |
3253 | fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n", | |
3254 | ((TARGET_EXT_STRING) ? "Yes" | |
3255 | : "No")); | |
9304f876 CJW |
3256 | |
3257 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3258 | ||
3259 | fprintf (asm_out_file, "\t! V3PUSH instructions\t: %s\n", | |
3260 | ((TARGET_V3PUSH) ? "Yes" | |
3261 | : "No")); | |
3262 | fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n", | |
3263 | ((TARGET_16_BIT) ? "Yes" | |
3264 | : "No")); | |
9304f876 CJW |
3265 | fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n", |
3266 | ((TARGET_REDUCED_REGS) ? "Yes" | |
3267 | : "No")); | |
3268 | ||
bc8a8810 MC |
3269 | fprintf (asm_out_file, "\t! Support unaligned access\t\t: %s\n", |
3270 | (flag_unaligned_access ? "Yes" | |
3271 | : "No")); | |
3272 | ||
9304f876 CJW |
3273 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
3274 | ||
3275 | if (optimize_size) | |
3276 | fprintf (asm_out_file, "\t! Optimization level\t: -Os\n"); | |
10c8bd03 CJW |
3277 | else if (optimize_fast) |
3278 | fprintf (asm_out_file, "\t! Optimization level\t: -Ofast\n"); | |
3279 | else if (optimize_debug) | |
3280 | fprintf (asm_out_file, "\t! Optimization level\t: -Og\n"); | |
9304f876 CJW |
3281 | else |
3282 | fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize); | |
3283 | ||
3284 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3285 | ||
3286 | fprintf (asm_out_file, "\t! Cache block size\t: %d\n", | |
3287 | nds32_cache_block_size); | |
3288 | ||
3289 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3290 | ||
c23a919b | 3291 | nds32_asm_file_start_for_isr (); |
9304f876 CJW |
3292 | } |
3293 | ||
3294 | static void | |
3295 | nds32_asm_file_end (void) | |
3296 | { | |
c23a919b | 3297 | nds32_asm_file_end_for_isr (); |
9304f876 | 3298 | |
cf3cd43d CJW |
3299 | /* The NDS32 Linux stack is mapped non-executable by default, so add a |
3300 | .note.GNU-stack section. */ | |
3301 | if (TARGET_LINUX_ABI) | |
3302 | file_end_indicate_exec_stack (); | |
3303 | ||
9304f876 CJW |
3304 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
3305 | } | |
3306 | ||
85a98076 KLC |
3307 | static bool |
3308 | nds32_asm_output_addr_const_extra (FILE *file, rtx x) | |
3309 | { | |
3310 | if (GET_CODE (x) == UNSPEC) | |
3311 | { | |
3312 | switch (XINT (x, 1)) | |
3313 | { | |
b26fa4f9 KLC |
3314 | case UNSPEC_GOTINIT: |
3315 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3316 | break; | |
3317 | case UNSPEC_GOTOFF: | |
3318 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3319 | fputs ("@GOTOFF", file); | |
3320 | break; | |
3321 | case UNSPEC_GOT: | |
3322 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3323 | fputs ("@GOT", file); | |
3324 | break; | |
3325 | case UNSPEC_PLT: | |
3326 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3327 | fputs ("@PLT", file); | |
3328 | break; | |
3329 | case UNSPEC_TLSGD: | |
3330 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3331 | fputs ("@TLSDESC", file); | |
3332 | break; | |
3333 | case UNSPEC_TLSLD: | |
3334 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3335 | fputs ("@TLSDESC", file); | |
3336 | break; | |
3337 | case UNSPEC_TLSIE: | |
3338 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3339 | fputs ("@GOTTPOFF", file); | |
3340 | break; | |
3341 | case UNSPEC_TLSLE: | |
3342 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3343 | fputs ("@TPOFF", file); | |
3344 | break; | |
85a98076 KLC |
3345 | case UNSPEC_ICT: |
3346 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3347 | fputs ("@ICT", file); | |
3348 | break; | |
3349 | default: | |
3350 | return false; | |
3351 | } | |
3352 | return true; | |
3353 | } | |
3354 | else | |
3355 | return false; | |
3356 | } | |
3357 | ||
9304f876 CJW |
3358 | /* -- Output and Generation of Labels. */ |
3359 | ||
3360 | static void | |
3361 | nds32_asm_globalize_label (FILE *stream, const char *name) | |
3362 | { | |
3363 | fputs ("\t.global\t", stream); | |
3364 | assemble_name (stream, name); | |
3365 | fputs ("\n", stream); | |
3366 | } | |
3367 | ||
3368 | /* -- Output of Assembler Instructions. */ | |
3369 | ||
3370 | static void | |
3371 | nds32_print_operand (FILE *stream, rtx x, int code) | |
3372 | { | |
bfeb6685 | 3373 | HOST_WIDE_INT op_value = 0; |
a3b13564 KC |
3374 | HOST_WIDE_INT one_position; |
3375 | HOST_WIDE_INT zero_position; | |
e2286268 MC |
3376 | bool pick_lsb_p = false; |
3377 | bool pick_msb_p = false; | |
3378 | int regno; | |
3379 | ||
bfeb6685 CJW |
3380 | if (CONST_INT_P (x)) |
3381 | op_value = INTVAL (x); | |
9304f876 CJW |
3382 | |
3383 | switch (code) | |
3384 | { | |
3385 | case 0 : | |
3386 | /* Do nothing special. */ | |
3387 | break; | |
3388 | ||
a3b13564 KC |
3389 | case 'b': |
3390 | /* Use exact_log2() to search the 0-bit position. */ | |
3391 | gcc_assert (CONST_INT_P (x)); | |
3392 | zero_position = exact_log2 (~UINTVAL (x) & GET_MODE_MASK (SImode)); | |
3393 | gcc_assert (zero_position != -1); | |
3394 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, zero_position); | |
3395 | ||
3396 | /* No need to handle following process, so return immediately. */ | |
3397 | return; | |
3398 | ||
8656bbcf SC |
3399 | case 'e': |
3400 | gcc_assert (MEM_P (x) | |
3401 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3402 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT); | |
3403 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (XEXP (x, 0), 1))); | |
3404 | ||
3405 | /* No need to handle following process, so return immediately. */ | |
3406 | return; | |
7c32ef41 MC |
3407 | |
3408 | case 'v': | |
3409 | gcc_assert (CONST_INT_P (x) | |
3410 | && (INTVAL (x) == 0 | |
3411 | || INTVAL (x) == 8 | |
3412 | || INTVAL (x) == 16 | |
3413 | || INTVAL (x) == 24)); | |
3414 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8); | |
3415 | ||
3416 | /* No need to handle following process, so return immediately. */ | |
3417 | return; | |
3418 | ||
a3b13564 KC |
3419 | case 'B': |
3420 | /* Use exact_log2() to search the 1-bit position. */ | |
3421 | gcc_assert (CONST_INT_P (x)); | |
3422 | one_position = exact_log2 (UINTVAL (x) & GET_MODE_MASK (SImode)); | |
3423 | gcc_assert (one_position != -1); | |
3424 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, one_position); | |
3425 | ||
3426 | /* No need to handle following process, so return immediately. */ | |
3427 | return; | |
3428 | ||
e2286268 MC |
3429 | case 'L': |
3430 | /* X is supposed to be REG rtx. */ | |
3431 | gcc_assert (REG_P (x)); | |
3432 | /* Claim that we are going to pick LSB part of X. */ | |
3433 | pick_lsb_p = true; | |
3434 | break; | |
3435 | ||
3436 | case 'H': | |
3437 | /* X is supposed to be REG rtx. */ | |
3438 | gcc_assert (REG_P (x)); | |
3439 | /* Claim that we are going to pick MSB part of X. */ | |
3440 | pick_msb_p = true; | |
3441 | break; | |
3442 | ||
9304f876 CJW |
3443 | case 'V': |
3444 | /* 'x' is supposed to be CONST_INT, get the value. */ | |
3445 | gcc_assert (CONST_INT_P (x)); | |
9304f876 CJW |
3446 | |
3447 | /* According to the Andes architecture, | |
8a498f99 CJW |
3448 | the system/user register index range is 0 ~ 1023. |
3449 | In order to avoid conflict between user-specified-integer value | |
3450 | and enum-specified-register value, | |
3451 | the 'enum nds32_intrinsic_registers' value | |
3452 | in nds32_intrinsic.h starts from 1024. */ | |
9304f876 CJW |
3453 | if (op_value < 1024 && op_value >= 0) |
3454 | { | |
3455 | /* If user gives integer value directly (0~1023), | |
3456 | we just print out the value. */ | |
5af50159 | 3457 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, op_value); |
9304f876 CJW |
3458 | } |
3459 | else if (op_value < 0 | |
3460 | || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names) | |
3461 | + 1024)) | |
3462 | { | |
3463 | /* The enum index value for array size is out of range. */ | |
3464 | error ("intrinsic register index is out of range"); | |
3465 | } | |
3466 | else | |
3467 | { | |
3468 | /* If user applies normal way with __NDS32_REG_XXX__ enum data, | |
3469 | we can print out register name. Remember to substract 1024. */ | |
3470 | fprintf (stream, "%s", | |
3471 | nds32_intrinsic_register_names[op_value - 1024]); | |
3472 | } | |
3473 | ||
3474 | /* No need to handle following process, so return immediately. */ | |
3475 | return; | |
3476 | ||
f1a0afe2 MC |
3477 | case 'R': /* cctl valck */ |
3478 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3479 | if (op_value < 0 || op_value > 4) | |
67f84a80 | 3480 | error ("CCTL intrinsic function subtype out of range"); |
f1a0afe2 MC |
3481 | fprintf (stream, "%s", nds32_cctl_names[op_value]); |
3482 | return; | |
3483 | ||
3484 | case 'T': /* cctl idxwbinv */ | |
3485 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3486 | if (op_value < 0 || op_value > 4) | |
67f84a80 | 3487 | error ("CCTL intrinsic function subtype out of range"); |
f1a0afe2 MC |
3488 | fprintf (stream, "%s", nds32_cctl_names[op_value + 4]); |
3489 | return; | |
3490 | ||
3491 | case 'U': /* cctl vawbinv */ | |
3492 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3493 | if (op_value < 0 || op_value > 4) | |
67f84a80 | 3494 | error ("CCTL intrinsic function subtype out of range"); |
f1a0afe2 MC |
3495 | fprintf (stream, "%s", nds32_cctl_names[op_value + 8]); |
3496 | return; | |
3497 | ||
3498 | case 'X': /* cctl idxread */ | |
3499 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3500 | if (op_value < 0 || op_value > 4) | |
67f84a80 | 3501 | error ("CCTL intrinsic function subtype out of range"); |
f1a0afe2 MC |
3502 | fprintf (stream, "%s", nds32_cctl_names[op_value + 12]); |
3503 | return; | |
3504 | ||
3505 | case 'W': /* cctl idxwitre */ | |
3506 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3507 | if (op_value < 0 || op_value > 4) | |
67f84a80 | 3508 | error ("CCTL intrinsic function subtype out of range"); |
f1a0afe2 MC |
3509 | fprintf (stream, "%s", nds32_cctl_names[op_value + 16]); |
3510 | return; | |
3511 | ||
57aaf0cc MC |
3512 | case 'Z': /* dpref */ |
3513 | fprintf (stream, "%s", nds32_dpref_names[op_value]); | |
3514 | return; | |
3515 | ||
9304f876 CJW |
3516 | default : |
3517 | /* Unknown flag. */ | |
3518 | output_operand_lossage ("invalid operand output code"); | |
3519 | break; | |
3520 | } | |
3521 | ||
3522 | switch (GET_CODE (x)) | |
3523 | { | |
3524 | case LABEL_REF: | |
85a98076 KLC |
3525 | output_addr_const (stream, x); |
3526 | break; | |
3527 | ||
9304f876 CJW |
3528 | case SYMBOL_REF: |
3529 | output_addr_const (stream, x); | |
85a98076 | 3530 | |
cf3cd43d | 3531 | if (!TARGET_LINUX_ABI && nds32_indirect_call_referenced_p (x)) |
85a98076 KLC |
3532 | fprintf (stream, "@ICT"); |
3533 | ||
9304f876 CJW |
3534 | break; |
3535 | ||
3536 | case REG: | |
e2286268 MC |
3537 | /* Print a Double-precision register name. */ |
3538 | if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) | |
3539 | && NDS32_IS_FPR_REGNUM (REGNO (x))) | |
3540 | { | |
3541 | regno = REGNO (x); | |
3542 | if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno)) | |
3543 | { | |
3544 | output_operand_lossage ("invalid operand for code '%c'", code); | |
3545 | break; | |
3546 | } | |
3547 | fprintf (stream, "$fd%d", (regno - NDS32_FIRST_FPR_REGNUM) >> 1); | |
3548 | break; | |
3549 | } | |
3550 | ||
3551 | /* Print LSB or MSB part of register pair if the | |
3552 | constraint modifier 'L' or 'H' is specified. */ | |
3553 | if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) | |
3554 | && NDS32_IS_GPR_REGNUM (REGNO (x))) | |
3555 | { | |
3556 | if ((pick_lsb_p && WORDS_BIG_ENDIAN) | |
3557 | || (pick_msb_p && !WORDS_BIG_ENDIAN)) | |
3558 | { | |
3559 | /* If we would like to print out LSB register under big-endian, | |
3560 | or print out MSB register under little-endian, we need to | |
3561 | increase register number. */ | |
3562 | regno = REGNO (x); | |
3563 | regno++; | |
3564 | fputs (reg_names[regno], stream); | |
3565 | break; | |
3566 | } | |
3567 | } | |
3568 | ||
9304f876 | 3569 | /* Forbid using static chain register ($r16) |
8a498f99 | 3570 | on reduced-set registers configuration. */ |
9304f876 CJW |
3571 | if (TARGET_REDUCED_REGS |
3572 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
3573 | sorry ("a nested function is not supported for reduced registers"); | |
3574 | ||
3575 | /* Normal cases, print out register name. */ | |
3576 | fputs (reg_names[REGNO (x)], stream); | |
3577 | break; | |
3578 | ||
3579 | case MEM: | |
cc8ca59e | 3580 | output_address (GET_MODE (x), XEXP (x, 0)); |
9304f876 CJW |
3581 | break; |
3582 | ||
e2286268 MC |
3583 | case HIGH: |
3584 | if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE) | |
3585 | { | |
3586 | const REAL_VALUE_TYPE *rv; | |
3587 | long val; | |
3588 | gcc_assert (GET_MODE (x) == SFmode); | |
3589 | ||
3590 | rv = CONST_DOUBLE_REAL_VALUE (XEXP (x, 0)); | |
3591 | REAL_VALUE_TO_TARGET_SINGLE (*rv, val); | |
3592 | ||
3593 | fprintf (stream, "hi20(0x%lx)", val); | |
3594 | } | |
3595 | else | |
3596 | gcc_unreachable (); | |
3597 | break; | |
3598 | ||
3599 | case CONST_DOUBLE: | |
3600 | const REAL_VALUE_TYPE *rv; | |
3601 | long val; | |
3602 | gcc_assert (GET_MODE (x) == SFmode); | |
3603 | ||
3604 | rv = CONST_DOUBLE_REAL_VALUE (x); | |
3605 | REAL_VALUE_TO_TARGET_SINGLE (*rv, val); | |
3606 | ||
3607 | fprintf (stream, "0x%lx", val); | |
3608 | break; | |
3609 | ||
9304f876 CJW |
3610 | case CODE_LABEL: |
3611 | case CONST_INT: | |
3612 | case CONST: | |
3613 | output_addr_const (stream, x); | |
3614 | break; | |
3615 | ||
7c32ef41 MC |
3616 | case CONST_VECTOR: |
3617 | fprintf (stream, HOST_WIDE_INT_PRINT_HEX, const_vector_to_hwint (x)); | |
3618 | break; | |
3619 | ||
85a98076 KLC |
3620 | case LO_SUM: |
3621 | /* This is a special case for inline assembly using memory address 'p'. | |
3622 | The inline assembly code is expected to use pesudo instruction | |
3623 | for the operand. EX: la */ | |
3624 | output_addr_const (stream, XEXP(x, 1)); | |
3625 | break; | |
3626 | ||
9304f876 CJW |
3627 | default: |
3628 | /* Generally, output_addr_const () is able to handle most cases. | |
8a498f99 CJW |
3629 | We want to see what CODE could appear, |
3630 | so we use gcc_unreachable() to stop it. */ | |
9304f876 CJW |
3631 | debug_rtx (x); |
3632 | gcc_unreachable (); | |
3633 | break; | |
3634 | } | |
3635 | } | |
3636 | ||
3637 | static void | |
85a98076 KLC |
3638 | nds32_print_operand_address (FILE *stream, |
3639 | machine_mode mode ATTRIBUTE_UNUSED, | |
3640 | rtx x) | |
9304f876 CJW |
3641 | { |
3642 | rtx op0, op1; | |
3643 | ||
3644 | switch (GET_CODE (x)) | |
3645 | { | |
3646 | case SYMBOL_REF: | |
3647 | case CONST: | |
3648 | /* [ + symbol_ref] */ | |
3649 | /* [ + const_addr], where const_addr = symbol_ref + const_int */ | |
3650 | fputs ("[ + ", stream); | |
3651 | output_addr_const (stream, x); | |
3652 | fputs ("]", stream); | |
3653 | break; | |
3654 | ||
85a98076 KLC |
3655 | case LO_SUM: |
3656 | /* This is a special case for inline assembly using memory operand 'm'. | |
3657 | The inline assembly code is expected to use pesudo instruction | |
3658 | for the operand. EX: [ls].[bhw] */ | |
3659 | fputs ("[ + ", stream); | |
3660 | op1 = XEXP (x, 1); | |
3661 | output_addr_const (stream, op1); | |
3662 | fputs ("]", stream); | |
3663 | break; | |
3664 | ||
9304f876 CJW |
3665 | case REG: |
3666 | /* Forbid using static chain register ($r16) | |
8a498f99 | 3667 | on reduced-set registers configuration. */ |
9304f876 CJW |
3668 | if (TARGET_REDUCED_REGS |
3669 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
3670 | sorry ("a nested function is not supported for reduced registers"); | |
3671 | ||
3672 | /* [Ra] */ | |
3673 | fprintf (stream, "[%s]", reg_names[REGNO (x)]); | |
3674 | break; | |
3675 | ||
3676 | case PLUS: | |
3677 | op0 = XEXP (x, 0); | |
3678 | op1 = XEXP (x, 1); | |
3679 | ||
3680 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 3681 | on reduced-set registers configuration. */ |
9304f876 CJW |
3682 | if (TARGET_REDUCED_REGS |
3683 | && REG_P (op0) | |
3684 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
3685 | sorry ("a nested function is not supported for reduced registers"); | |
3686 | /* Checking op1, forbid using static chain register ($r16) | |
8a498f99 | 3687 | on reduced-set registers configuration. */ |
9304f876 CJW |
3688 | if (TARGET_REDUCED_REGS |
3689 | && REG_P (op1) | |
3690 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
3691 | sorry ("a nested function is not supported for reduced registers"); | |
3692 | ||
3693 | if (REG_P (op0) && CONST_INT_P (op1)) | |
3694 | { | |
3695 | /* [Ra + imm] */ | |
5af50159 KC |
3696 | fprintf (stream, "[%s + (" HOST_WIDE_INT_PRINT_DEC ")]", |
3697 | reg_names[REGNO (op0)], INTVAL (op1)); | |
9304f876 CJW |
3698 | } |
3699 | else if (REG_P (op0) && REG_P (op1)) | |
3700 | { | |
3701 | /* [Ra + Rb] */ | |
3702 | fprintf (stream, "[%s + %s]", | |
3703 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
3704 | } | |
3705 | else if (GET_CODE (op0) == MULT && REG_P (op1)) | |
3706 | { | |
3707 | /* [Ra + Rb << sv] | |
3708 | From observation, the pattern looks like: | |
3709 | (plus:SI (mult:SI (reg:SI 58) | |
8a498f99 CJW |
3710 | (const_int 4 [0x4])) |
3711 | (reg/f:SI 57)) */ | |
9304f876 CJW |
3712 | int sv; |
3713 | ||
3714 | /* We need to set sv to output shift value. */ | |
3715 | if (INTVAL (XEXP (op0, 1)) == 1) | |
3716 | sv = 0; | |
3717 | else if (INTVAL (XEXP (op0, 1)) == 2) | |
3718 | sv = 1; | |
3719 | else if (INTVAL (XEXP (op0, 1)) == 4) | |
3720 | sv = 2; | |
f62a2af5 CJW |
3721 | else if (INTVAL (XEXP (op0, 1)) == 8) |
3722 | sv = 3; | |
9304f876 CJW |
3723 | else |
3724 | gcc_unreachable (); | |
3725 | ||
3726 | fprintf (stream, "[%s + %s << %d]", | |
3727 | reg_names[REGNO (op1)], | |
3728 | reg_names[REGNO (XEXP (op0, 0))], | |
3729 | sv); | |
3730 | } | |
7c32ef41 MC |
3731 | else if (GET_CODE (op0) == ASHIFT && REG_P (op1)) |
3732 | { | |
3733 | /* [Ra + Rb << sv] | |
3734 | In normal, ASHIFT can be converted to MULT like above case. | |
3735 | But when the address rtx does not go through canonicalize_address | |
3736 | defined in fwprop, we'll need this case. */ | |
3737 | int sv = INTVAL (XEXP (op0, 1)); | |
3738 | gcc_assert (sv <= 3 && sv >=0); | |
3739 | ||
3740 | fprintf (stream, "[%s + %s << %d]", | |
3741 | reg_names[REGNO (op1)], | |
3742 | reg_names[REGNO (XEXP (op0, 0))], | |
3743 | sv); | |
3744 | } | |
9304f876 CJW |
3745 | else |
3746 | { | |
3747 | /* The control flow is not supposed to be here. */ | |
3748 | debug_rtx (x); | |
3749 | gcc_unreachable (); | |
3750 | } | |
3751 | ||
3752 | break; | |
3753 | ||
3754 | case POST_MODIFY: | |
3755 | /* (post_modify (regA) (plus (regA) (regB))) | |
8a498f99 CJW |
3756 | (post_modify (regA) (plus (regA) (const_int))) |
3757 | We would like to extract | |
3758 | regA and regB (or const_int) from plus rtx. */ | |
9304f876 CJW |
3759 | op0 = XEXP (XEXP (x, 1), 0); |
3760 | op1 = XEXP (XEXP (x, 1), 1); | |
3761 | ||
3762 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 3763 | on reduced-set registers configuration. */ |
9304f876 CJW |
3764 | if (TARGET_REDUCED_REGS |
3765 | && REG_P (op0) | |
3766 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
3767 | sorry ("a nested function is not supported for reduced registers"); | |
3768 | /* Checking op1, forbid using static chain register ($r16) | |
8a498f99 | 3769 | on reduced-set registers configuration. */ |
9304f876 CJW |
3770 | if (TARGET_REDUCED_REGS |
3771 | && REG_P (op1) | |
3772 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
3773 | sorry ("a nested function is not supported for reduced registers"); | |
3774 | ||
3775 | if (REG_P (op0) && REG_P (op1)) | |
3776 | { | |
3777 | /* [Ra], Rb */ | |
3778 | fprintf (stream, "[%s], %s", | |
3779 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
3780 | } | |
3781 | else if (REG_P (op0) && CONST_INT_P (op1)) | |
3782 | { | |
3783 | /* [Ra], imm */ | |
5af50159 KC |
3784 | fprintf (stream, "[%s], " HOST_WIDE_INT_PRINT_DEC, |
3785 | reg_names[REGNO (op0)], INTVAL (op1)); | |
9304f876 CJW |
3786 | } |
3787 | else | |
3788 | { | |
3789 | /* The control flow is not supposed to be here. */ | |
3790 | debug_rtx (x); | |
3791 | gcc_unreachable (); | |
3792 | } | |
3793 | ||
3794 | break; | |
3795 | ||
3796 | case POST_INC: | |
3797 | case POST_DEC: | |
3798 | op0 = XEXP (x, 0); | |
3799 | ||
3800 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 3801 | on reduced-set registers configuration. */ |
9304f876 CJW |
3802 | if (TARGET_REDUCED_REGS |
3803 | && REG_P (op0) | |
3804 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
3805 | sorry ("a nested function is not supported for reduced registers"); | |
3806 | ||
3807 | if (REG_P (op0)) | |
3808 | { | |
3809 | /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4" | |
3810 | The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
3811 | We only need to deal with register Ra. */ | |
3812 | fprintf (stream, "[%s]", reg_names[REGNO (op0)]); | |
3813 | } | |
3814 | else | |
3815 | { | |
3816 | /* The control flow is not supposed to be here. */ | |
3817 | debug_rtx (x); | |
3818 | gcc_unreachable (); | |
3819 | } | |
3820 | ||
3821 | break; | |
3822 | ||
3823 | default : | |
3824 | /* Generally, output_addr_const () is able to handle most cases. | |
8a498f99 CJW |
3825 | We want to see what CODE could appear, |
3826 | so we use gcc_unreachable() to stop it. */ | |
9304f876 CJW |
3827 | debug_rtx (x); |
3828 | gcc_unreachable (); | |
3829 | break; | |
3830 | } | |
3831 | } | |
3832 | ||
e2286268 MC |
3833 | /* -- Assembler Commands for Exception Regions. */ |
3834 | ||
3835 | static rtx | |
3836 | nds32_dwarf_register_span (rtx reg) | |
3837 | { | |
3838 | rtx dwarf_high, dwarf_low; | |
3839 | rtx dwarf_single; | |
3840 | machine_mode mode; | |
3841 | int regno; | |
3842 | ||
3843 | mode = GET_MODE (reg); | |
3844 | regno = REGNO (reg); | |
3845 | ||
3846 | /* We need to adjust dwarf register information for floating-point registers | |
3847 | rather than using default register number mapping. */ | |
3848 | if (regno >= NDS32_FIRST_FPR_REGNUM | |
3849 | && regno <= NDS32_LAST_FPR_REGNUM) | |
3850 | { | |
3851 | if (mode == DFmode || mode == SCmode) | |
3852 | { | |
3853 | /* By default, GCC maps increasing register numbers to increasing | |
3854 | memory locations, but paired FPRs in NDS32 target are always | |
3855 | big-endian, i.e.: | |
3856 | ||
3857 | fd0 : fs0 fs1 | |
3858 | (MSB) (LSB) | |
3859 | ||
3860 | We must return parallel rtx to represent such layout. */ | |
3861 | dwarf_high = gen_rtx_REG (word_mode, regno); | |
3862 | dwarf_low = gen_rtx_REG (word_mode, regno + 1); | |
3863 | return gen_rtx_PARALLEL (VOIDmode, | |
3864 | gen_rtvec (2, dwarf_low, dwarf_high)); | |
3865 | } | |
3866 | else if (mode == DCmode) | |
3867 | { | |
3868 | rtx dwarf_high_re = gen_rtx_REG (word_mode, regno); | |
3869 | rtx dwarf_low_re = gen_rtx_REG (word_mode, regno + 1); | |
3870 | rtx dwarf_high_im = gen_rtx_REG (word_mode, regno); | |
3871 | rtx dwarf_low_im = gen_rtx_REG (word_mode, regno + 1); | |
3872 | return gen_rtx_PARALLEL (VOIDmode, | |
3873 | gen_rtvec (4, dwarf_low_re, dwarf_high_re, | |
3874 | dwarf_high_im, dwarf_low_im)); | |
3875 | } | |
4b23af6d | 3876 | else if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) |
e2286268 | 3877 | { |
4b23af6d | 3878 | return NULL_RTX; |
e2286268 MC |
3879 | } |
3880 | else | |
3881 | { | |
3882 | /* We should not be here. */ | |
3883 | gcc_unreachable (); | |
3884 | } | |
3885 | } | |
3886 | ||
3887 | return NULL_RTX; | |
3888 | } | |
3889 | ||
3890 | /* Map internal gcc register numbers to DWARF2 register numbers. */ | |
3891 | ||
3892 | unsigned int | |
ca60bd93 | 3893 | nds32_debugger_regno (unsigned int regno) |
e2286268 MC |
3894 | { |
3895 | /* The nds32 port in GDB maintains a mapping between dwarf register | |
3896 | number and displayed register name. For backward compatibility to | |
3897 | previous toolchain, currently our gdb still has four registers | |
3898 | (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler | |
3899 | does not count those four registers in its register number table. | |
3900 | So we have to add 4 on its register number and then create new | |
3901 | dwarf information. Hopefully we can discard such workaround | |
3902 | in the future. */ | |
3903 | if (NDS32_IS_FPR_REGNUM (regno)) | |
3904 | return regno + 4; | |
3905 | ||
3906 | return regno; | |
3907 | } | |
3908 | ||
9304f876 CJW |
3909 | \f |
3910 | /* Defining target-specific uses of __attribute__. */ | |
3911 | ||
3912 | /* Add some checking after merging attributes. */ | |
3913 | static tree | |
3914 | nds32_merge_decl_attributes (tree olddecl, tree newdecl) | |
3915 | { | |
3916 | tree combined_attrs; | |
3917 | ||
3918 | /* Create combined attributes. */ | |
3919 | combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), | |
3920 | DECL_ATTRIBUTES (newdecl)); | |
3921 | ||
59043e75 | 3922 | /* Since newdecl is acutally a duplicate of olddecl, |
9304f876 CJW |
3923 | we can take olddecl for some operations. */ |
3924 | if (TREE_CODE (olddecl) == FUNCTION_DECL) | |
3925 | { | |
3926 | /* Check isr-specific attributes conflict. */ | |
3927 | nds32_check_isr_attrs_conflict (olddecl, combined_attrs); | |
3928 | } | |
3929 | ||
3930 | return combined_attrs; | |
3931 | } | |
3932 | ||
3933 | /* Add some checking when inserting attributes. */ | |
3934 | static void | |
3935 | nds32_insert_attributes (tree decl, tree *attributes) | |
3936 | { | |
85a98076 KLC |
3937 | /* A "indirect_call" function attribute implies "noinline" and "noclone" |
3938 | for elf toolchain to support ROM patch mechanism. */ | |
3939 | if (TREE_CODE (decl) == FUNCTION_DECL | |
3940 | && lookup_attribute ("indirect_call", *attributes) != NULL) | |
3941 | { | |
3942 | tree new_attrs = *attributes; | |
3943 | ||
cf3cd43d | 3944 | if (TARGET_LINUX_ABI) |
67f84a80 | 3945 | error ("cannot use %<indirect_call%> attribute under linux toolchain"); |
cf3cd43d | 3946 | |
85a98076 KLC |
3947 | if (lookup_attribute ("noinline", new_attrs) == NULL) |
3948 | new_attrs = tree_cons (get_identifier ("noinline"), NULL, new_attrs); | |
3949 | if (lookup_attribute ("noclone", new_attrs) == NULL) | |
3950 | new_attrs = tree_cons (get_identifier ("noclone"), NULL, new_attrs); | |
3951 | ||
3952 | if (!TREE_PUBLIC (decl)) | |
67f84a80 | 3953 | error ("%<indirect_call%> attribute cannot apply for static function"); |
85a98076 KLC |
3954 | |
3955 | *attributes = new_attrs; | |
3956 | } | |
3957 | ||
9304f876 CJW |
3958 | /* For function declaration, we need to check isr-specific attributes: |
3959 | 1. Call nds32_check_isr_attrs_conflict() to check any conflict. | |
3960 | 2. Check valid integer value for interrupt/exception. | |
3961 | 3. Check valid integer value for reset. | |
3962 | 4. Check valid function for nmi/warm. */ | |
3963 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
3964 | { | |
3965 | tree func_attrs; | |
3966 | tree intr, excp, reset; | |
3967 | ||
3968 | /* Pick up function attributes. */ | |
3969 | func_attrs = *attributes; | |
3970 | ||
3971 | /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */ | |
3972 | nds32_check_isr_attrs_conflict (decl, func_attrs); | |
3973 | ||
3974 | /* Now we are starting to check valid id value | |
8a498f99 CJW |
3975 | for interrupt/exception/reset. |
3976 | Note that we ONLY check its validity here. | |
3977 | To construct isr vector information, it is still performed | |
3978 | by nds32_construct_isr_vectors_information(). */ | |
9304f876 CJW |
3979 | intr = lookup_attribute ("interrupt", func_attrs); |
3980 | excp = lookup_attribute ("exception", func_attrs); | |
3981 | reset = lookup_attribute ("reset", func_attrs); | |
3982 | ||
a4931745 CJW |
3983 | /* The following code may use attribute arguments. If there is no |
3984 | argument from source code, it will cause segmentation fault. | |
3985 | Therefore, return dircetly and report error message later. */ | |
3986 | if ((intr && TREE_VALUE (intr) == NULL) | |
3987 | || (excp && TREE_VALUE (excp) == NULL) | |
3988 | || (reset && TREE_VALUE (reset) == NULL)) | |
3989 | return; | |
3990 | ||
3991 | /* ------------------------------------------------------------- */ | |
3992 | /* FIXME: | |
3993 | FOR BACKWARD COMPATIBILITY, we need to support following patterns: | |
3994 | ||
3995 | __attribute__((interrupt("XXX;YYY;id=ZZZ"))) | |
3996 | __attribute__((exception("XXX;YYY;id=ZZZ"))) | |
3997 | __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) | |
3998 | ||
3999 | If interrupt/exception/reset appears and its argument is a | |
4000 | STRING_CST, we will use other functions to parse string in the | |
4001 | nds32_construct_isr_vectors_information() and then set necessary | |
4002 | isr information in the nds32_isr_vectors[] array. Here we can | |
4003 | just return immediately to avoid new-syntax checking. */ | |
4004 | if (intr != NULL_TREE | |
4005 | && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) | |
4006 | return; | |
4007 | if (excp != NULL_TREE | |
4008 | && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) | |
4009 | return; | |
4010 | if (reset != NULL_TREE | |
4011 | && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) | |
4012 | return; | |
4013 | /* ------------------------------------------------------------- */ | |
4014 | ||
9304f876 CJW |
4015 | if (intr || excp) |
4016 | { | |
4017 | /* Deal with interrupt/exception. */ | |
4018 | tree id_list; | |
4019 | unsigned int lower_bound, upper_bound; | |
4020 | ||
4021 | /* The way to handle interrupt or exception is the same, | |
4022 | we just need to take care of actual vector number. | |
4023 | For interrupt(0..63), the actual vector number is (9..72). | |
4024 | For exception(1..8), the actual vector number is (1..8). */ | |
4025 | lower_bound = (intr) ? (0) : (1); | |
4026 | upper_bound = (intr) ? (63) : (8); | |
4027 | ||
4028 | /* Prepare id list so that we can traverse id value. */ | |
4029 | id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp)); | |
4030 | ||
4031 | /* 2. Check valid integer value for interrupt/exception. */ | |
4032 | while (id_list) | |
4033 | { | |
4034 | tree id; | |
4035 | ||
4036 | /* Pick up each vector id value. */ | |
4037 | id = TREE_VALUE (id_list); | |
4038 | /* Issue error if it is not a valid integer value. */ | |
4039 | if (TREE_CODE (id) != INTEGER_CST | |
8e6cdc90 RS |
4040 | || wi::ltu_p (wi::to_wide (id), lower_bound) |
4041 | || wi::gtu_p (wi::to_wide (id), upper_bound)) | |
9304f876 CJW |
4042 | error ("invalid id value for interrupt/exception attribute"); |
4043 | ||
4044 | /* Advance to next id. */ | |
4045 | id_list = TREE_CHAIN (id_list); | |
4046 | } | |
4047 | } | |
4048 | else if (reset) | |
4049 | { | |
4050 | /* Deal with reset. */ | |
4051 | tree id_list; | |
4052 | tree id; | |
4053 | tree nmi, warm; | |
4054 | unsigned int lower_bound; | |
4055 | unsigned int upper_bound; | |
4056 | ||
4057 | /* Prepare id_list and identify id value so that | |
4058 | we can check if total number of vectors is valid. */ | |
4059 | id_list = TREE_VALUE (reset); | |
4060 | id = TREE_VALUE (id_list); | |
4061 | ||
4062 | /* The maximum numbers for user's interrupt is 64. */ | |
4063 | lower_bound = 0; | |
4064 | upper_bound = 64; | |
4065 | ||
4066 | /* 3. Check valid integer value for reset. */ | |
4067 | if (TREE_CODE (id) != INTEGER_CST | |
8e6cdc90 RS |
4068 | || wi::ltu_p (wi::to_wide (id), lower_bound) |
4069 | || wi::gtu_p (wi::to_wide (id), upper_bound)) | |
9304f876 CJW |
4070 | error ("invalid id value for reset attribute"); |
4071 | ||
4072 | /* 4. Check valid function for nmi/warm. */ | |
4073 | nmi = lookup_attribute ("nmi", func_attrs); | |
4074 | warm = lookup_attribute ("warm", func_attrs); | |
4075 | ||
4076 | if (nmi != NULL_TREE) | |
4077 | { | |
4078 | tree nmi_func_list; | |
4079 | tree nmi_func; | |
4080 | ||
4081 | nmi_func_list = TREE_VALUE (nmi); | |
4082 | nmi_func = TREE_VALUE (nmi_func_list); | |
4083 | ||
4084 | /* Issue error if it is not a valid nmi function. */ | |
4085 | if (TREE_CODE (nmi_func) != IDENTIFIER_NODE) | |
4086 | error ("invalid nmi function for reset attribute"); | |
4087 | } | |
4088 | ||
4089 | if (warm != NULL_TREE) | |
4090 | { | |
4091 | tree warm_func_list; | |
4092 | tree warm_func; | |
4093 | ||
4094 | warm_func_list = TREE_VALUE (warm); | |
4095 | warm_func = TREE_VALUE (warm_func_list); | |
4096 | ||
4097 | /* Issue error if it is not a valid warm function. */ | |
4098 | if (TREE_CODE (warm_func) != IDENTIFIER_NODE) | |
4099 | error ("invalid warm function for reset attribute"); | |
4100 | } | |
4101 | } | |
4102 | else | |
4103 | { | |
4104 | /* No interrupt, exception, or reset attribute is set. */ | |
4105 | return; | |
4106 | } | |
4107 | } | |
4108 | } | |
4109 | ||
4110 | static bool | |
4111 | nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED, | |
4112 | tree pop_target ATTRIBUTE_UNUSED) | |
4113 | { | |
4114 | /* Currently, we do not parse any pragma target by ourself, | |
4115 | so just simply return false. */ | |
4116 | return false; | |
4117 | } | |
4118 | ||
4119 | static void | |
4120 | nds32_option_override (void) | |
4121 | { | |
4122 | /* After all the command options have been parsed, | |
4123 | we shall deal with some flags for changing compiler settings. */ | |
4124 | ||
4125 | /* At first, we check if we have to strictly | |
4126 | set some flags based on ISA family. */ | |
4127 | if (TARGET_ISA_V2) | |
4128 | { | |
4129 | /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */ | |
4130 | target_flags &= ~MASK_V3PUSH; | |
4131 | } | |
4132 | if (TARGET_ISA_V3) | |
4133 | { | |
37d8f611 CJW |
4134 | /* If this is ARCH_V3J, we need to enable TARGET_REDUCED_REGS. */ |
4135 | if (nds32_arch_option == ARCH_V3J) | |
4136 | target_flags |= MASK_REDUCED_REGS; | |
9304f876 CJW |
4137 | } |
4138 | if (TARGET_ISA_V3M) | |
4139 | { | |
4140 | /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */ | |
4141 | target_flags |= MASK_REDUCED_REGS; | |
aa4b851c CJW |
4142 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */ |
4143 | target_flags &= ~MASK_EXT_PERF; | |
4144 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */ | |
4145 | target_flags &= ~MASK_EXT_PERF2; | |
4146 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */ | |
4147 | target_flags &= ~MASK_EXT_STRING; | |
b26fa4f9 KLC |
4148 | |
4149 | if (flag_pic) | |
a3f9f006 | 4150 | error ("not support %<-fpic%> option for v3m toolchain"); |
9304f876 CJW |
4151 | } |
4152 | ||
4153 | /* See if we are using reduced-set registers: | |
4154 | $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31 | |
4155 | If so, we must forbid using $r11~$r14, $r16~$r27. */ | |
4156 | if (TARGET_REDUCED_REGS) | |
4157 | { | |
4158 | int r; | |
4159 | ||
4160 | /* Prevent register allocator from | |
8a498f99 | 4161 | choosing it as doing register allocation. */ |
9304f876 CJW |
4162 | for (r = 11; r <= 14; r++) |
4163 | fixed_regs[r] = call_used_regs[r] = 1; | |
4164 | for (r = 16; r <= 27; r++) | |
4165 | fixed_regs[r] = call_used_regs[r] = 1; | |
4166 | } | |
4167 | ||
2140297c CJW |
4168 | /* See if user explicitly would like to use fp-as-gp optimization. |
4169 | If so, we must prevent $fp from being allocated | |
4170 | during register allocation. */ | |
4171 | if (TARGET_FORCE_FP_AS_GP) | |
4172 | fixed_regs[FP_REGNUM] = call_used_regs[FP_REGNUM] = 1; | |
4173 | ||
9304f876 CJW |
4174 | if (!TARGET_16_BIT) |
4175 | { | |
4176 | /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */ | |
4177 | target_flags &= ~MASK_V3PUSH; | |
4178 | } | |
4179 | ||
e2286268 MC |
4180 | if (TARGET_HARD_FLOAT && !(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) |
4181 | { | |
4182 | if (nds32_arch_option == ARCH_V3S || nds32_arch_option == ARCH_V3F) | |
4183 | error ("Disable FPU ISA, " | |
904f3daa | 4184 | "the ABI option must be enable %<-mfloat-abi=soft%>"); |
e2286268 | 4185 | else |
904f3daa ML |
4186 | error ("%<-mabi=2fp+%> option only support when FPU available, " |
4187 | "must be enable %<-mext-fpu-sp%> or %<-mext-fpu-dp%>"); | |
e2286268 MC |
4188 | } |
4189 | ||
19c93809 | 4190 | nds32_init_rtx_costs (); |
c4d8d050 CJW |
4191 | |
4192 | nds32_register_passes (); | |
9304f876 CJW |
4193 | } |
4194 | ||
4195 | \f | |
4196 | /* Miscellaneous Parameters. */ | |
4197 | ||
823835a9 CJW |
4198 | static rtx_insn * |
4199 | nds32_md_asm_adjust (vec<rtx> &outputs ATTRIBUTE_UNUSED, | |
4200 | vec<rtx> &inputs ATTRIBUTE_UNUSED, | |
e52ef6e6 | 4201 | vec<machine_mode> &input_modes ATTRIBUTE_UNUSED, |
823835a9 | 4202 | vec<const char *> &constraints ATTRIBUTE_UNUSED, |
414d795d RS |
4203 | vec<rtx> &/*uses*/, vec<rtx> &clobbers, |
4204 | HARD_REG_SET &clobbered_regs, location_t /*loc*/) | |
823835a9 | 4205 | { |
b28c01ab CJW |
4206 | if (!flag_inline_asm_r15) |
4207 | { | |
4208 | clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); | |
4209 | SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); | |
4210 | } | |
823835a9 CJW |
4211 | return NULL; |
4212 | } | |
4213 | ||
9304f876 CJW |
4214 | static void |
4215 | nds32_init_builtins (void) | |
4216 | { | |
aaa44d2d | 4217 | nds32_init_builtins_impl (); |
9304f876 CJW |
4218 | } |
4219 | ||
7a12ea32 MC |
4220 | static tree |
4221 | nds32_builtin_decl (unsigned code, bool initialize_p) | |
4222 | { | |
e53b6e56 | 4223 | /* Implement in nds32-intrinsic.cc. */ |
7a12ea32 MC |
4224 | return nds32_builtin_decl_impl (code, initialize_p); |
4225 | } | |
4226 | ||
9304f876 CJW |
4227 | static rtx |
4228 | nds32_expand_builtin (tree exp, | |
4229 | rtx target, | |
aaa44d2d | 4230 | rtx subtarget, |
ef4bddc2 | 4231 | machine_mode mode, |
aaa44d2d | 4232 | int ignore) |
9304f876 | 4233 | { |
aaa44d2d | 4234 | return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore); |
9304f876 CJW |
4235 | } |
4236 | ||
cf3cd43d CJW |
4237 | /* Implement TARGET_INIT_LIBFUNCS. */ |
4238 | static void | |
4239 | nds32_init_libfuncs (void) | |
4240 | { | |
4241 | if (TARGET_LINUX_ABI) | |
4242 | init_sync_libfuncs (UNITS_PER_WORD); | |
4243 | } | |
9304f876 CJW |
4244 | |
4245 | /* ------------------------------------------------------------------------ */ | |
4246 | ||
4247 | /* PART 4: Implemet extern function definitions, | |
4248 | the prototype is in nds32-protos.h. */ | |
72b7e5e1 KC |
4249 | \f |
4250 | /* Run-time Target Specification. */ | |
4251 | ||
4252 | void | |
4253 | nds32_cpu_cpp_builtins(struct cpp_reader *pfile) | |
4254 | { | |
4255 | #define builtin_define(TXT) cpp_define (pfile, TXT) | |
4256 | #define builtin_assert(TXT) cpp_assert (pfile, TXT) | |
4257 | builtin_define ("__nds32__"); | |
4258 | builtin_define ("__NDS32__"); | |
4259 | ||
a4931745 CJW |
4260 | /* We need to provide builtin macro to describe the size of |
4261 | each vector for interrupt handler under elf toolchain. */ | |
4262 | if (!TARGET_LINUX_ABI) | |
4263 | { | |
4264 | if (TARGET_ISR_VECTOR_SIZE_4_BYTE) | |
4265 | builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__"); | |
4266 | else | |
4267 | builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__"); | |
4268 | } | |
4269 | ||
e2286268 MC |
4270 | if (TARGET_HARD_FLOAT) |
4271 | builtin_define ("__NDS32_ABI_2FP_PLUS__"); | |
4272 | else | |
4273 | builtin_define ("__NDS32_ABI_2__"); | |
4274 | ||
72b7e5e1 KC |
4275 | if (TARGET_ISA_V2) |
4276 | builtin_define ("__NDS32_ISA_V2__"); | |
4277 | if (TARGET_ISA_V3) | |
4278 | builtin_define ("__NDS32_ISA_V3__"); | |
4279 | if (TARGET_ISA_V3M) | |
4280 | builtin_define ("__NDS32_ISA_V3M__"); | |
4281 | ||
e2286268 MC |
4282 | if (TARGET_FPU_SINGLE) |
4283 | builtin_define ("__NDS32_EXT_FPU_SP__"); | |
4284 | if (TARGET_FPU_DOUBLE) | |
4285 | builtin_define ("__NDS32_EXT_FPU_DP__"); | |
4286 | ||
4287 | if (TARGET_EXT_FPU_FMA) | |
4288 | builtin_define ("__NDS32_EXT_FPU_FMA__"); | |
4289 | if (NDS32_EXT_FPU_DOT_E) | |
4290 | builtin_define ("__NDS32_EXT_FPU_DOT_E__"); | |
4291 | if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
4292 | { | |
4293 | switch (nds32_fp_regnum) | |
4294 | { | |
4295 | case 0: | |
4296 | case 4: | |
4297 | builtin_define ("__NDS32_EXT_FPU_CONFIG_0__"); | |
4298 | break; | |
4299 | case 1: | |
4300 | case 5: | |
4301 | builtin_define ("__NDS32_EXT_FPU_CONFIG_1__"); | |
4302 | break; | |
4303 | case 2: | |
4304 | case 6: | |
4305 | builtin_define ("__NDS32_EXT_FPU_CONFIG_2__"); | |
4306 | break; | |
4307 | case 3: | |
4308 | case 7: | |
4309 | builtin_define ("__NDS32_EXT_FPU_CONFIG_3__"); | |
4310 | break; | |
4311 | default: | |
4312 | abort (); | |
4313 | } | |
4314 | } | |
4315 | ||
72b7e5e1 KC |
4316 | if (TARGET_BIG_ENDIAN) |
4317 | builtin_define ("__NDS32_EB__"); | |
4318 | else | |
4319 | builtin_define ("__NDS32_EL__"); | |
4320 | ||
4321 | if (TARGET_REDUCED_REGS) | |
4322 | builtin_define ("__NDS32_REDUCED_REGS__"); | |
4323 | if (TARGET_CMOV) | |
4324 | builtin_define ("__NDS32_CMOV__"); | |
4325 | if (TARGET_EXT_PERF) | |
4326 | builtin_define ("__NDS32_EXT_PERF__"); | |
4327 | if (TARGET_EXT_PERF2) | |
4328 | builtin_define ("__NDS32_EXT_PERF2__"); | |
4329 | if (TARGET_EXT_STRING) | |
4330 | builtin_define ("__NDS32_EXT_STRING__"); | |
4331 | if (TARGET_16_BIT) | |
4332 | builtin_define ("__NDS32_16_BIT__"); | |
4333 | if (TARGET_GP_DIRECT) | |
4334 | builtin_define ("__NDS32_GP_DIRECT__"); | |
ff77f6e8 KC |
4335 | if (TARGET_VH) |
4336 | builtin_define ("__NDS32_VH__"); | |
7c32ef41 MC |
4337 | if (NDS32_EXT_DSP_P ()) |
4338 | builtin_define ("__NDS32_EXT_DSP__"); | |
72b7e5e1 KC |
4339 | |
4340 | if (TARGET_BIG_ENDIAN) | |
4341 | builtin_define ("__big_endian__"); | |
4342 | ||
4343 | builtin_assert ("cpu=nds32"); | |
4344 | builtin_assert ("machine=nds32"); | |
e2286268 MC |
4345 | |
4346 | if (TARGET_HARD_FLOAT) | |
4347 | builtin_define ("__NDS32_ABI_2FP_PLUS"); | |
4348 | else | |
4349 | builtin_define ("__NDS32_ABI_2"); | |
4350 | ||
72b7e5e1 KC |
4351 | #undef builtin_define |
4352 | #undef builtin_assert | |
4353 | } | |
4354 | ||
9304f876 CJW |
4355 | \f |
4356 | /* Defining Data Structures for Per-function Information. */ | |
4357 | ||
4358 | void | |
4359 | nds32_init_expanders (void) | |
4360 | { | |
4361 | /* Arrange to initialize and mark the machine per-function status. */ | |
4362 | init_machine_status = nds32_init_machine_status; | |
4363 | } | |
4364 | ||
4365 | \f | |
4366 | /* Register Usage. */ | |
4367 | ||
5e6ae0cc CJW |
4368 | /* -- Order of Allocation of Registers. */ |
4369 | ||
4370 | void | |
4371 | nds32_adjust_reg_alloc_order (void) | |
4372 | { | |
4373 | const int nds32_reg_alloc_order[] = REG_ALLOC_ORDER; | |
4374 | ||
4375 | /* Copy the default register allocation order, which is designed | |
4376 | to optimize for code size. */ | |
4377 | memcpy(reg_alloc_order, nds32_reg_alloc_order, sizeof (reg_alloc_order)); | |
4378 | ||
4379 | /* Adjust few register allocation order when optimizing for speed. */ | |
4380 | if (!optimize_size) | |
4381 | { | |
4382 | memcpy (reg_alloc_order, nds32_reg_alloc_order_for_speed, | |
4383 | sizeof (nds32_reg_alloc_order_for_speed)); | |
4384 | } | |
4385 | } | |
4386 | ||
9304f876 CJW |
4387 | /* -- How Values Fit in Registers. */ |
4388 | ||
e2286268 MC |
4389 | static unsigned |
4390 | nds32_hard_regno_nregs (unsigned regno ATTRIBUTE_UNUSED, | |
4391 | machine_mode mode) | |
4392 | { | |
4393 | return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); | |
4394 | } | |
4395 | ||
f939c3e6 RS |
4396 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ |
4397 | ||
4398 | static bool | |
4399 | nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
9304f876 | 4400 | { |
65e87462 | 4401 | if (regno >= FIRST_PSEUDO_REGISTER) |
f939c3e6 | 4402 | return true; |
9304f876 | 4403 | |
e2286268 MC |
4404 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) && NDS32_IS_FPR_REGNUM (regno)) |
4405 | { | |
4406 | if (NDS32_IS_EXT_FPR_REGNUM(regno)) | |
4407 | return (NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) && (mode == DFmode)); | |
4408 | else if (mode == SFmode || mode == SImode) | |
4409 | return NDS32_FPR_REGNO_OK_FOR_SINGLE (regno); | |
4410 | else if (mode == DFmode) | |
4411 | return NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno); | |
4412 | ||
4413 | return false; | |
4414 | } | |
4415 | ||
4416 | /* Restrict double-word quantities to even register pairs. */ | |
4417 | if (regno <= NDS32_LAST_GPR_REGNUM) | |
4418 | return (targetm.hard_regno_nregs (regno, mode) == 1 | |
4419 | || !((regno) & 1)); | |
4420 | ||
f939c3e6 | 4421 | return false; |
9304f876 CJW |
4422 | } |
4423 | ||
99e1629f RS |
4424 | /* Implement TARGET_MODES_TIEABLE_P. We can use general registers to |
4425 | tie QI/HI/SI modes together. */ | |
4426 | ||
4427 | static bool | |
4428 | nds32_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
4429 | { | |
e2286268 MC |
4430 | if ((GET_MODE_CLASS (mode1) == MODE_INT |
4431 | && GET_MODE_CLASS (mode2) == MODE_INT) | |
4432 | && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD | |
4433 | && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD) | |
4434 | return true; | |
4435 | ||
4436 | if (GET_MODE_SIZE (mode1) == GET_MODE_SIZE (mode2)) | |
4437 | { | |
4438 | if ((TARGET_FPU_SINGLE && !TARGET_FPU_DOUBLE) | |
4439 | && (mode1 == DFmode || mode2 == DFmode)) | |
4440 | return false; | |
4441 | else | |
4442 | return true; | |
4443 | } | |
4444 | ||
4445 | return false; | |
99e1629f | 4446 | } |
9304f876 CJW |
4447 | \f |
4448 | /* Register Classes. */ | |
4449 | ||
4450 | enum reg_class | |
4451 | nds32_regno_reg_class (int regno) | |
4452 | { | |
4453 | /* Refer to nds32.h for more register class details. */ | |
4454 | ||
4455 | if (regno >= 0 && regno <= 7) | |
4456 | return LOW_REGS; | |
4457 | else if (regno >= 8 && regno <= 11) | |
4458 | return MIDDLE_REGS; | |
4459 | else if (regno >= 12 && regno <= 14) | |
4460 | return HIGH_REGS; | |
4461 | else if (regno == 15) | |
4462 | return R15_TA_REG; | |
4463 | else if (regno >= 16 && regno <= 19) | |
4464 | return MIDDLE_REGS; | |
4465 | else if (regno >= 20 && regno <= 31) | |
4466 | return HIGH_REGS; | |
4467 | else if (regno == 32 || regno == 33) | |
e2286268 MC |
4468 | { |
4469 | /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't | |
4470 | know how to allocate register for $SFP and $AP, just tell IRA they | |
4471 | are GENERAL_REGS, and ARM do this hack too. */ | |
4472 | return GENERAL_REGS; | |
4473 | } | |
4474 | else if (regno >= 34 && regno <= 97) | |
4475 | return FP_REGS; | |
9304f876 CJW |
4476 | else |
4477 | return NO_REGS; | |
4478 | } | |
4479 | ||
4480 | \f | |
4481 | /* Stack Layout and Calling Conventions. */ | |
4482 | ||
4483 | /* -- Basic Stack Layout. */ | |
4484 | ||
ca3a4a55 CJW |
4485 | rtx |
4486 | nds32_dynamic_chain_address (rtx frameaddr) | |
4487 | { | |
4488 | if (TARGET_V3PUSH) | |
4489 | { | |
4490 | /* If -mv3push is specified, we push $fp, $gp, and $lp into stack. | |
4491 | We can access dynamic chain address from stack by [$fp - 12]. */ | |
4492 | return plus_constant (Pmode, frameaddr, -12); | |
4493 | } | |
4494 | else | |
4495 | { | |
4496 | /* For general case we push $fp and $lp into stack at prologue. | |
4497 | We can access dynamic chain address from stack by [$fp - 8]. */ | |
4498 | return plus_constant (Pmode, frameaddr, -8); | |
4499 | } | |
4500 | } | |
4501 | ||
9304f876 CJW |
4502 | rtx |
4503 | nds32_return_addr_rtx (int count, | |
ca3a4a55 | 4504 | rtx frameaddr) |
9304f876 | 4505 | { |
ca3a4a55 CJW |
4506 | int offset; |
4507 | rtx addr; | |
4508 | ||
9304f876 | 4509 | if (count != 0) |
ca3a4a55 CJW |
4510 | { |
4511 | /* In nds32 ABI design, we can expect that $lp is always available | |
4512 | from stack by [$fp - 4] location. */ | |
4513 | offset = -4; | |
4514 | addr = plus_constant (Pmode, frameaddr, offset); | |
4515 | addr = memory_address (Pmode, addr); | |
4516 | ||
4517 | return gen_rtx_MEM (Pmode, addr); | |
4518 | } | |
9304f876 CJW |
4519 | |
4520 | /* If count == 0, it means we are at current frame, | |
4521 | the return address is $r30 ($lp). */ | |
4522 | return get_hard_reg_initial_val (Pmode, LP_REGNUM); | |
4523 | } | |
4524 | ||
4525 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
4526 | ||
4527 | HOST_WIDE_INT | |
4528 | nds32_initial_elimination_offset (unsigned int from_reg, unsigned int to_reg) | |
4529 | { | |
4530 | HOST_WIDE_INT offset; | |
4531 | ||
4532 | /* Compute and setup stack frame size. | |
4533 | The result will be in cfun->machine. */ | |
4534 | nds32_compute_stack_frame (); | |
4535 | ||
4536 | /* Remember to consider | |
ca3a4a55 CJW |
4537 | cfun->machine->callee_saved_area_gpr_padding_bytes and |
4538 | cfun->machine->eh_return_data_regs_size | |
9304f876 CJW |
4539 | when calculating offset. */ |
4540 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
4541 | { | |
4542 | offset = (cfun->machine->fp_size | |
8a498f99 | 4543 | + cfun->machine->gp_size |
9304f876 | 4544 | + cfun->machine->lp_size |
c457f751 CJW |
4545 | + cfun->machine->callee_saved_gpr_regs_size |
4546 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
e2286268 | 4547 | + cfun->machine->callee_saved_fpr_regs_size |
ca3a4a55 | 4548 | + cfun->machine->eh_return_data_regs_size |
9304f876 CJW |
4549 | + cfun->machine->local_size |
4550 | + cfun->machine->out_args_size); | |
4551 | } | |
4552 | else if (from_reg == ARG_POINTER_REGNUM | |
4553 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
4554 | { | |
4555 | offset = 0; | |
4556 | } | |
4557 | else if (from_reg == FRAME_POINTER_REGNUM | |
4558 | && to_reg == STACK_POINTER_REGNUM) | |
4559 | { | |
4560 | offset = (cfun->machine->local_size + cfun->machine->out_args_size); | |
4561 | } | |
4562 | else if (from_reg == FRAME_POINTER_REGNUM | |
4563 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
4564 | { | |
4565 | offset = (-1) * (cfun->machine->fp_size | |
4566 | + cfun->machine->gp_size | |
4567 | + cfun->machine->lp_size | |
c457f751 | 4568 | + cfun->machine->callee_saved_gpr_regs_size |
e2286268 | 4569 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
ca3a4a55 CJW |
4570 | + cfun->machine->callee_saved_fpr_regs_size |
4571 | + cfun->machine->eh_return_data_regs_size); | |
9304f876 CJW |
4572 | } |
4573 | else | |
4574 | { | |
4575 | gcc_unreachable (); | |
4576 | } | |
4577 | ||
4578 | return offset; | |
4579 | } | |
4580 | ||
4581 | /* -- Passing Arguments in Registers. */ | |
4582 | ||
4583 | void | |
4584 | nds32_init_cumulative_args (CUMULATIVE_ARGS *cum, | |
4585 | tree fntype ATTRIBUTE_UNUSED, | |
4586 | rtx libname ATTRIBUTE_UNUSED, | |
4587 | tree fndecl ATTRIBUTE_UNUSED, | |
4588 | int n_named_args ATTRIBUTE_UNUSED) | |
4589 | { | |
e2286268 MC |
4590 | /* Initial available registers. The values are offset against |
4591 | NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM | |
9304f876 | 4592 | for passing arguments. */ |
9d93cc24 | 4593 | cum->gpr_offset = 0; |
e2286268 | 4594 | cum->fpr_offset = 0; |
9304f876 CJW |
4595 | } |
4596 | ||
4597 | /* -- Function Entry and Exit. */ | |
4598 | ||
4599 | /* Function for normal multiple push prologue. */ | |
4600 | void | |
4601 | nds32_expand_prologue (void) | |
4602 | { | |
4603 | int fp_adjust; | |
4604 | int sp_adjust; | |
a6c7e777 | 4605 | unsigned Rb, Re; |
9304f876 | 4606 | |
9304f876 CJW |
4607 | /* Compute and setup stack frame size. |
4608 | The result will be in cfun->machine. */ | |
4609 | nds32_compute_stack_frame (); | |
4610 | ||
2140297c CJW |
4611 | /* Check frame_pointer_needed again to prevent fp is need after reload. */ |
4612 | if (frame_pointer_needed) | |
4613 | cfun->machine->fp_as_gp_p = false; | |
4614 | ||
557430f1 CJW |
4615 | /* If this is a variadic function, first we need to push argument |
4616 | registers that hold the unnamed argument value. */ | |
4617 | if (cfun->machine->va_args_size != 0) | |
4618 | { | |
a6c7e777 MC |
4619 | Rb = cfun->machine->va_args_first_regno; |
4620 | Re = cfun->machine->va_args_last_regno; | |
4621 | /* No need to push $fp, $gp, or $lp. */ | |
4622 | nds32_emit_stack_push_multiple (Rb, Re, false, false, false, true); | |
557430f1 CJW |
4623 | |
4624 | /* We may also need to adjust stack pointer for padding bytes | |
4625 | because varargs may cause $sp not 8-byte aligned. */ | |
4626 | if (cfun->machine->va_args_area_padding_bytes) | |
4627 | { | |
4628 | /* Generate sp adjustment instruction. */ | |
4629 | sp_adjust = cfun->machine->va_args_area_padding_bytes; | |
557430f1 | 4630 | |
a6c7e777 MC |
4631 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4632 | stack_pointer_rtx, | |
4633 | -1 * sp_adjust); | |
557430f1 CJW |
4634 | } |
4635 | } | |
4636 | ||
9304f876 CJW |
4637 | /* If the function is 'naked', |
4638 | we do not have to generate prologue code fragment. */ | |
b26fa4f9 | 4639 | if (cfun->machine->naked_p && !flag_pic) |
9304f876 CJW |
4640 | return; |
4641 | ||
4642 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
4643 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
4644 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
4645 | |
4646 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
4647 | to be saved, we don't have to create multiple push instruction. | |
4648 | Otherwise, a multiple push instruction is needed. */ | |
a6c7e777 MC |
4649 | if (!(Rb == SP_REGNUM && Re == SP_REGNUM |
4650 | && cfun->machine->fp_size == 0 | |
4651 | && cfun->machine->gp_size == 0 | |
4652 | && cfun->machine->lp_size == 0)) | |
9304f876 CJW |
4653 | { |
4654 | /* Create multiple push instruction rtx. */ | |
a6c7e777 MC |
4655 | nds32_emit_stack_push_multiple ( |
4656 | Rb, Re, | |
4657 | cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size, | |
4658 | false); | |
9304f876 CJW |
4659 | } |
4660 | ||
ca3a4a55 CJW |
4661 | /* Save eh data registers. */ |
4662 | if (cfun->machine->use_eh_return_p) | |
4663 | { | |
4664 | Rb = cfun->machine->eh_return_data_first_regno; | |
4665 | Re = cfun->machine->eh_return_data_last_regno; | |
4666 | ||
4667 | /* No need to push $fp, $gp, or $lp. | |
4668 | Also, this is not variadic arguments push. */ | |
4669 | nds32_emit_stack_push_multiple (Rb, Re, false, false, false, false); | |
4670 | } | |
4671 | ||
9304f876 CJW |
4672 | /* Check frame_pointer_needed to see |
4673 | if we shall emit fp adjustment instruction. */ | |
4674 | if (frame_pointer_needed) | |
4675 | { | |
4676 | /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size) | |
8a498f99 | 4677 | + (4 * callee-saved-registers) |
ca3a4a55 | 4678 | + (4 * exception-handling-data-registers) |
8a498f99 CJW |
4679 | Note: No need to adjust |
4680 | cfun->machine->callee_saved_area_gpr_padding_bytes, | |
4681 | because, at this point, stack pointer is just | |
4682 | at the position after push instruction. */ | |
9304f876 CJW |
4683 | fp_adjust = cfun->machine->fp_size |
4684 | + cfun->machine->gp_size | |
4685 | + cfun->machine->lp_size | |
ca3a4a55 CJW |
4686 | + cfun->machine->callee_saved_gpr_regs_size |
4687 | + cfun->machine->eh_return_data_regs_size; | |
7064dcad | 4688 | |
a6c7e777 MC |
4689 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, |
4690 | stack_pointer_rtx, | |
4691 | fp_adjust); | |
9304f876 CJW |
4692 | } |
4693 | ||
e2286268 MC |
4694 | /* Save fpu registers. */ |
4695 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4696 | { | |
4697 | /* When $sp moved to bottom of stack, we need to check whether | |
4698 | the range of offset in the FPU instruction. */ | |
4699 | int fpr_offset = cfun->machine->local_size | |
4700 | + cfun->machine->out_args_size | |
4701 | + cfun->machine->callee_saved_fpr_regs_size; | |
4702 | ||
4703 | /* Check FPU instruction offset imm14s. */ | |
4704 | if (!satisfies_constraint_Is14 (GEN_INT (fpr_offset))) | |
4705 | { | |
4706 | int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes | |
4707 | + cfun->machine->callee_saved_fpr_regs_size; | |
4708 | ||
4709 | /* Save fpu registers, need to allocate stack space | |
4710 | for fpu callee registers. And now $sp position | |
4711 | on callee saved fpr registers. */ | |
4712 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4713 | stack_pointer_rtx, | |
4714 | -1 * fpr_space); | |
4715 | ||
4716 | /* Emit fpu store instruction, using [$sp + offset] store | |
4717 | fpu registers. */ | |
4718 | nds32_emit_push_fpr_callee_saved (0); | |
4719 | ||
4720 | /* Adjust $sp = $sp - local_size - out_args_size. */ | |
4721 | sp_adjust = cfun->machine->local_size | |
4722 | + cfun->machine->out_args_size; | |
4723 | ||
4724 | /* Allocate stack space for local size and out args size. */ | |
4725 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4726 | stack_pointer_rtx, | |
4727 | -1 * sp_adjust); | |
4728 | } | |
4729 | else | |
4730 | { | |
4731 | /* Offset range in Is14, so $sp moved to bottom of stack. */ | |
4732 | ||
4733 | /* Adjust $sp = $sp - local_size - out_args_size | |
4734 | - callee_saved_area_gpr_padding_bytes | |
4735 | - callee_saved_fpr_regs_size. */ | |
4736 | sp_adjust = cfun->machine->local_size | |
4737 | + cfun->machine->out_args_size | |
4738 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
4739 | + cfun->machine->callee_saved_fpr_regs_size; | |
4740 | ||
4741 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4742 | stack_pointer_rtx, | |
4743 | -1 * sp_adjust); | |
4744 | ||
4745 | /* Emit fpu store instruction, using [$sp + offset] store | |
4746 | fpu registers. */ | |
4747 | int fpr_position = cfun->machine->out_args_size | |
4748 | + cfun->machine->local_size; | |
4749 | nds32_emit_push_fpr_callee_saved (fpr_position); | |
4750 | } | |
4751 | } | |
4752 | else | |
4753 | { | |
4754 | /* Adjust $sp = $sp - local_size - out_args_size | |
4755 | - callee_saved_area_gpr_padding_bytes. */ | |
4756 | sp_adjust = cfun->machine->local_size | |
4757 | + cfun->machine->out_args_size | |
4758 | + cfun->machine->callee_saved_area_gpr_padding_bytes; | |
4759 | ||
4760 | /* sp_adjust value may be out of range of the addi instruction, | |
4761 | create alternative add behavior with TA_REGNUM if necessary, | |
4762 | using NEGATIVE value to tell that we are decreasing address. */ | |
4763 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4764 | stack_pointer_rtx, | |
4765 | -1 * sp_adjust); | |
4766 | } | |
9304f876 | 4767 | |
b26fa4f9 KLC |
4768 | /* Emit gp setup instructions for -fpic. */ |
4769 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) | |
4770 | nds32_emit_load_gp (); | |
4771 | ||
d057a470 CJW |
4772 | /* If user applies -mno-sched-prolog-epilog option, |
4773 | we need to prevent instructions of function body from being | |
4774 | scheduled with stack adjustment in prologue. */ | |
4775 | if (!flag_sched_prolog_epilog) | |
4776 | emit_insn (gen_blockage ()); | |
9304f876 CJW |
4777 | } |
4778 | ||
4779 | /* Function for normal multiple pop epilogue. */ | |
4780 | void | |
d6529176 | 4781 | nds32_expand_epilogue (bool sibcall_p) |
9304f876 CJW |
4782 | { |
4783 | int sp_adjust; | |
a6c7e777 | 4784 | unsigned Rb, Re; |
9304f876 CJW |
4785 | |
4786 | /* Compute and setup stack frame size. | |
4787 | The result will be in cfun->machine. */ | |
4788 | nds32_compute_stack_frame (); | |
4789 | ||
d057a470 CJW |
4790 | /* If user applies -mno-sched-prolog-epilog option, |
4791 | we need to prevent instructions of function body from being | |
4792 | scheduled with stack adjustment in epilogue. */ | |
4793 | if (!flag_sched_prolog_epilog) | |
4794 | emit_insn (gen_blockage ()); | |
9304f876 CJW |
4795 | |
4796 | /* If the function is 'naked', we do not have to generate | |
557430f1 CJW |
4797 | epilogue code fragment BUT 'ret' instruction. |
4798 | However, if this function is also a variadic function, | |
4799 | we need to create adjust stack pointer before 'ret' instruction. */ | |
9304f876 CJW |
4800 | if (cfun->machine->naked_p) |
4801 | { | |
557430f1 | 4802 | /* If this is a variadic function, we do not have to restore argument |
8a498f99 CJW |
4803 | registers but need to adjust stack pointer back to previous stack |
4804 | frame location before return. */ | |
557430f1 CJW |
4805 | if (cfun->machine->va_args_size != 0) |
4806 | { | |
4807 | /* Generate sp adjustment instruction. | |
4808 | We need to consider padding bytes here. */ | |
4809 | sp_adjust = cfun->machine->va_args_size | |
4810 | + cfun->machine->va_args_area_padding_bytes; | |
a6c7e777 MC |
4811 | |
4812 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4813 | stack_pointer_rtx, | |
4814 | sp_adjust); | |
557430f1 CJW |
4815 | } |
4816 | ||
03390cda | 4817 | /* Generate return instruction by using 'return_internal' pattern. |
8a498f99 | 4818 | Make sure this instruction is after gen_blockage(). */ |
d6529176 | 4819 | if (!sibcall_p) |
54c537e6 CJW |
4820 | { |
4821 | /* We need to further check attributes to determine whether | |
4822 | there should be return instruction at epilogue. | |
4823 | If the attribute naked exists but -mno-ret-in-naked-func | |
4824 | is issued, there is NO need to generate return instruction. */ | |
4825 | if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) | |
4826 | return; | |
4827 | ||
4828 | emit_jump_insn (gen_return_internal ()); | |
4829 | } | |
9304f876 CJW |
4830 | return; |
4831 | } | |
4832 | ||
4833 | if (frame_pointer_needed) | |
4834 | { | |
e2286268 MC |
4835 | /* Restore fpu registers. */ |
4836 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4837 | { | |
4838 | int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; | |
4839 | ||
4840 | /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) | |
4841 | - (4 * callee-saved-registers) | |
4842 | - (4 * exception-handling-data-registers) | |
4843 | - (4 * callee-saved-gpr-registers padding byte) | |
4844 | - (4 * callee-saved-fpr-registers) | |
4845 | Note: we want to adjust stack pointer | |
4846 | to the position for callee-saved fpr register, | |
4847 | And restore fpu register use .bi instruction to adjust $sp | |
4848 | from callee-saved fpr register to pop instruction. */ | |
4849 | sp_adjust = cfun->machine->fp_size | |
4850 | + cfun->machine->gp_size | |
4851 | + cfun->machine->lp_size | |
4852 | + cfun->machine->callee_saved_gpr_regs_size | |
ca3a4a55 | 4853 | + cfun->machine->eh_return_data_regs_size |
e2286268 MC |
4854 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
4855 | + cfun->machine->callee_saved_fpr_regs_size; | |
557430f1 | 4856 | |
e2286268 MC |
4857 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4858 | hard_frame_pointer_rtx, | |
4859 | -1 * sp_adjust); | |
4860 | ||
4861 | /* Emit fpu load instruction, using .bi instruction | |
4862 | load fpu registers. */ | |
4863 | nds32_emit_pop_fpr_callee_saved (gpr_padding); | |
4864 | } | |
4865 | else | |
4866 | { | |
4867 | /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) | |
4868 | - (4 * callee-saved-registers) | |
4869 | - (4 * exception-handling-data-registers) | |
4870 | Note: No need to adjust | |
4871 | cfun->machine->callee_saved_area_gpr_padding_bytes, | |
4872 | because we want to adjust stack pointer | |
4873 | to the position for pop instruction. */ | |
4874 | sp_adjust = cfun->machine->fp_size | |
4875 | + cfun->machine->gp_size | |
4876 | + cfun->machine->lp_size | |
ca3a4a55 CJW |
4877 | + cfun->machine->callee_saved_gpr_regs_size |
4878 | + cfun->machine->eh_return_data_regs_size; | |
e2286268 MC |
4879 | |
4880 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4881 | hard_frame_pointer_rtx, | |
4882 | -1 * sp_adjust); | |
4883 | } | |
9304f876 CJW |
4884 | } |
4885 | else | |
4886 | { | |
e2286268 MC |
4887 | /* Restore fpu registers. */ |
4888 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4889 | { | |
4890 | int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; | |
9304f876 | 4891 | |
e2286268 MC |
4892 | /* Adjust $sp = $sp + local_size + out_args_size. */ |
4893 | sp_adjust = cfun->machine->local_size | |
4894 | + cfun->machine->out_args_size; | |
a6c7e777 | 4895 | |
e2286268 MC |
4896 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4897 | stack_pointer_rtx, | |
4898 | sp_adjust); | |
4899 | ||
4900 | /* Emit fpu load instruction, using .bi instruction | |
4901 | load fpu registers, and adjust $sp from callee-saved fpr register | |
4902 | to callee-saved gpr register. */ | |
4903 | nds32_emit_pop_fpr_callee_saved (gpr_padding); | |
4904 | } | |
4905 | else | |
4906 | { | |
4907 | /* If frame pointer is NOT needed, | |
4908 | we cannot calculate the sp adjustment from frame pointer. | |
4909 | Instead, we calculate the adjustment by local_size, | |
4910 | out_args_size, and callee_saved_area_gpr_padding_bytes. | |
4911 | Notice that such sp adjustment value may be out of range, | |
4912 | so we have to deal with it as well. */ | |
4913 | ||
4914 | /* Adjust $sp = $sp + local_size + out_args_size | |
4915 | + callee_saved_area_gpr_padding_bytes. */ | |
4916 | sp_adjust = cfun->machine->local_size | |
4917 | + cfun->machine->out_args_size | |
4918 | + cfun->machine->callee_saved_area_gpr_padding_bytes; | |
4919 | ||
4920 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4921 | stack_pointer_rtx, | |
4922 | sp_adjust); | |
4923 | } | |
9304f876 CJW |
4924 | } |
4925 | ||
ca3a4a55 CJW |
4926 | /* Restore eh data registers. */ |
4927 | if (cfun->machine->use_eh_return_p) | |
4928 | { | |
4929 | Rb = cfun->machine->eh_return_data_first_regno; | |
4930 | Re = cfun->machine->eh_return_data_last_regno; | |
4931 | ||
4932 | /* No need to pop $fp, $gp, or $lp. */ | |
4933 | nds32_emit_stack_pop_multiple (Rb, Re, false, false, false); | |
4934 | } | |
4935 | ||
9304f876 | 4936 | /* Get callee_first_regno and callee_last_regno. */ |
a6c7e777 MC |
4937 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
4938 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
4939 | |
4940 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
4941 | to be saved, we don't have to create multiple pop instruction. | |
4942 | Otherwise, a multiple pop instruction is needed. */ | |
a6c7e777 MC |
4943 | if (!(Rb == SP_REGNUM && Re == SP_REGNUM |
4944 | && cfun->machine->fp_size == 0 | |
4945 | && cfun->machine->gp_size == 0 | |
4946 | && cfun->machine->lp_size == 0)) | |
9304f876 CJW |
4947 | { |
4948 | /* Create multiple pop instruction rtx. */ | |
a6c7e777 MC |
4949 | nds32_emit_stack_pop_multiple ( |
4950 | Rb, Re, | |
4951 | cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size); | |
9304f876 CJW |
4952 | } |
4953 | ||
557430f1 CJW |
4954 | /* If this is a variadic function, we do not have to restore argument |
4955 | registers but need to adjust stack pointer back to previous stack | |
4956 | frame location before return. */ | |
4957 | if (cfun->machine->va_args_size != 0) | |
4958 | { | |
4959 | /* Generate sp adjustment instruction. | |
8a498f99 | 4960 | We need to consider padding bytes here. */ |
557430f1 CJW |
4961 | sp_adjust = cfun->machine->va_args_size |
4962 | + cfun->machine->va_args_area_padding_bytes; | |
557430f1 | 4963 | |
a6c7e777 MC |
4964 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4965 | stack_pointer_rtx, | |
4966 | sp_adjust); | |
557430f1 CJW |
4967 | } |
4968 | ||
ca3a4a55 CJW |
4969 | /* If this function uses __builtin_eh_return, make stack adjustment |
4970 | for exception handler. */ | |
4971 | if (cfun->machine->use_eh_return_p) | |
4972 | { | |
4973 | /* We need to unwind the stack by the offset computed by | |
4974 | EH_RETURN_STACKADJ_RTX. However, at this point the CFA is | |
4975 | based on SP. Ideally we would update the SP and define the | |
4976 | CFA along the lines of: | |
4977 | ||
4978 | SP = SP + EH_RETURN_STACKADJ_RTX | |
4979 | (regnote CFA = SP - EH_RETURN_STACKADJ_RTX) | |
4980 | ||
4981 | However the dwarf emitter only understands a constant | |
4982 | register offset. | |
4983 | ||
4984 | The solution chosen here is to use the otherwise $ta ($r15) | |
4985 | as a temporary register to hold the current SP value. The | |
4986 | CFA is described using $ta then SP is modified. */ | |
4987 | ||
4988 | rtx ta_reg; | |
4989 | rtx insn; | |
4990 | ||
4991 | ta_reg = gen_rtx_REG (SImode, TA_REGNUM); | |
4992 | ||
4993 | insn = emit_move_insn (ta_reg, stack_pointer_rtx); | |
4994 | add_reg_note (insn, REG_CFA_DEF_CFA, ta_reg); | |
4995 | RTX_FRAME_RELATED_P (insn) = 1; | |
4996 | ||
4997 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
4998 | stack_pointer_rtx, | |
4999 | EH_RETURN_STACKADJ_RTX)); | |
5000 | ||
5001 | /* Ensure the assignment to $ta does not get optimized away. */ | |
5002 | emit_use (ta_reg); | |
5003 | } | |
5004 | ||
03390cda | 5005 | /* Generate return instruction. */ |
d6529176 CJW |
5006 | if (!sibcall_p) |
5007 | emit_jump_insn (gen_return_internal ()); | |
9304f876 CJW |
5008 | } |
5009 | ||
5010 | /* Function for v3push prologue. */ | |
5011 | void | |
5012 | nds32_expand_prologue_v3push (void) | |
5013 | { | |
5014 | int fp_adjust; | |
5015 | int sp_adjust; | |
e2286268 | 5016 | int fpr_space = 0; |
a6c7e777 | 5017 | unsigned Rb, Re; |
9304f876 | 5018 | |
9304f876 CJW |
5019 | /* Compute and setup stack frame size. |
5020 | The result will be in cfun->machine. */ | |
5021 | nds32_compute_stack_frame (); | |
5022 | ||
a6c7e777 MC |
5023 | if (cfun->machine->callee_saved_gpr_regs_size > 0) |
5024 | df_set_regs_ever_live (FP_REGNUM, 1); | |
5025 | ||
2140297c CJW |
5026 | /* Check frame_pointer_needed again to prevent fp is need after reload. */ |
5027 | if (frame_pointer_needed) | |
5028 | cfun->machine->fp_as_gp_p = false; | |
5029 | ||
9304f876 CJW |
5030 | /* If the function is 'naked', |
5031 | we do not have to generate prologue code fragment. */ | |
b26fa4f9 | 5032 | if (cfun->machine->naked_p && !flag_pic) |
9304f876 CJW |
5033 | return; |
5034 | ||
5035 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
5036 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
5037 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
5038 | |
5039 | /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available, | |
5040 | where imm8u has to be 8-byte alignment. */ | |
5041 | sp_adjust = cfun->machine->local_size | |
5042 | + cfun->machine->out_args_size | |
e2286268 MC |
5043 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
5044 | + cfun->machine->callee_saved_fpr_regs_size; | |
9304f876 CJW |
5045 | |
5046 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
5047 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)) | |
5048 | { | |
5049 | /* We can use 'push25 Re,imm8u'. */ | |
5050 | ||
88437f39 | 5051 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
a6c7e777 MC |
5052 | the pattern 'stack_v3push' is implemented in nds32.md. */ |
5053 | nds32_emit_stack_v3push (Rb, Re, sp_adjust); | |
e2286268 MC |
5054 | |
5055 | /* Save fpu registers. */ | |
5056 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5057 | { | |
5058 | /* Calculate fpr position. */ | |
5059 | int fpr_position = cfun->machine->local_size | |
5060 | + cfun->machine->out_args_size; | |
5061 | /* Emit fpu store instruction, using [$sp + offset] store | |
5062 | fpu registers. */ | |
5063 | nds32_emit_push_fpr_callee_saved (fpr_position); | |
5064 | } | |
5065 | ||
9304f876 | 5066 | /* Check frame_pointer_needed to see |
8a498f99 | 5067 | if we shall emit fp adjustment instruction. */ |
9304f876 CJW |
5068 | if (frame_pointer_needed) |
5069 | { | |
5070 | /* adjust $fp = $sp + 4 ($fp size) | |
8a498f99 CJW |
5071 | + 4 ($gp size) |
5072 | + 4 ($lp size) | |
5073 | + (4 * n) (callee-saved registers) | |
5074 | + sp_adjust ('push25 Re,imm8u') | |
9304f876 | 5075 | Note: Since we use 'push25 Re,imm8u', |
8a498f99 CJW |
5076 | the position of stack pointer is further |
5077 | changed after push instruction. | |
5078 | Hence, we need to take sp_adjust value | |
5079 | into consideration. */ | |
9304f876 CJW |
5080 | fp_adjust = cfun->machine->fp_size |
5081 | + cfun->machine->gp_size | |
5082 | + cfun->machine->lp_size | |
c457f751 | 5083 | + cfun->machine->callee_saved_gpr_regs_size |
9304f876 | 5084 | + sp_adjust; |
a6c7e777 MC |
5085 | |
5086 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, | |
5087 | stack_pointer_rtx, | |
5088 | fp_adjust); | |
9304f876 CJW |
5089 | } |
5090 | } | |
5091 | else | |
5092 | { | |
e2286268 MC |
5093 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5094 | { | |
5095 | /* Calculate fpr space. */ | |
5096 | fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes | |
5097 | + cfun->machine->callee_saved_fpr_regs_size; | |
5098 | ||
5099 | /* We have to use 'push25 Re, fpr_space', to pre-allocate | |
5100 | callee saved fpr registers space. */ | |
5101 | nds32_emit_stack_v3push (Rb, Re, fpr_space); | |
5102 | nds32_emit_push_fpr_callee_saved (0); | |
5103 | } | |
5104 | else | |
5105 | { | |
5106 | /* We have to use 'push25 Re,0' and | |
5107 | expand one more instruction to adjust $sp later. */ | |
9304f876 | 5108 | |
e2286268 MC |
5109 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
5110 | the pattern 'stack_v3push' is implemented in nds32.md. */ | |
5111 | nds32_emit_stack_v3push (Rb, Re, 0); | |
5112 | } | |
9304f876 CJW |
5113 | |
5114 | /* Check frame_pointer_needed to see | |
8a498f99 | 5115 | if we shall emit fp adjustment instruction. */ |
9304f876 CJW |
5116 | if (frame_pointer_needed) |
5117 | { | |
5118 | /* adjust $fp = $sp + 4 ($fp size) | |
8a498f99 CJW |
5119 | + 4 ($gp size) |
5120 | + 4 ($lp size) | |
5121 | + (4 * n) (callee-saved registers) | |
9304f876 | 5122 | Note: Since we use 'push25 Re,0', |
8a498f99 CJW |
5123 | the stack pointer is just at the position |
5124 | after push instruction. | |
5125 | No need to take sp_adjust into consideration. */ | |
9304f876 CJW |
5126 | fp_adjust = cfun->machine->fp_size |
5127 | + cfun->machine->gp_size | |
5128 | + cfun->machine->lp_size | |
c457f751 | 5129 | + cfun->machine->callee_saved_gpr_regs_size; |
a6c7e777 | 5130 | |
e2286268 MC |
5131 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5132 | { | |
5133 | /* We use 'push25 Re, fpr_space', the $sp is | |
5134 | on callee saved fpr position, so need to consider | |
5135 | fpr space. */ | |
5136 | fp_adjust = fp_adjust + fpr_space; | |
5137 | } | |
5138 | ||
a6c7e777 MC |
5139 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, |
5140 | stack_pointer_rtx, | |
5141 | fp_adjust); | |
9304f876 CJW |
5142 | } |
5143 | ||
e2286268 MC |
5144 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5145 | { | |
5146 | /* We use 'push25 Re, fpr_space', | |
5147 | the $sp is on callee saved fpr position, | |
5148 | no need to consider fpr space. */ | |
5149 | sp_adjust = sp_adjust - fpr_space; | |
5150 | } | |
5151 | ||
9304f876 | 5152 | /* Because we use 'push25 Re,0', |
8a498f99 | 5153 | we need to expand one more instruction to adjust $sp. |
8a498f99 | 5154 | using NEGATIVE value to tell that we are decreasing address. */ |
a6c7e777 MC |
5155 | nds32_emit_adjust_frame (stack_pointer_rtx, |
5156 | stack_pointer_rtx, | |
5157 | -1 * sp_adjust); | |
9304f876 CJW |
5158 | } |
5159 | ||
b26fa4f9 KLC |
5160 | /* Emit gp setup instructions for -fpic. */ |
5161 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) | |
5162 | nds32_emit_load_gp (); | |
5163 | ||
9304f876 CJW |
5164 | /* Prevent the instruction scheduler from |
5165 | moving instructions across the boundary. */ | |
5166 | emit_insn (gen_blockage ()); | |
5167 | } | |
5168 | ||
5169 | /* Function for v3pop epilogue. */ | |
5170 | void | |
d6529176 | 5171 | nds32_expand_epilogue_v3pop (bool sibcall_p) |
9304f876 CJW |
5172 | { |
5173 | int sp_adjust; | |
a6c7e777 | 5174 | unsigned Rb, Re; |
9304f876 CJW |
5175 | |
5176 | /* Compute and setup stack frame size. | |
5177 | The result will be in cfun->machine. */ | |
5178 | nds32_compute_stack_frame (); | |
5179 | ||
5180 | /* Prevent the instruction scheduler from | |
5181 | moving instructions across the boundary. */ | |
5182 | emit_insn (gen_blockage ()); | |
5183 | ||
5184 | /* If the function is 'naked', we do not have to generate | |
5185 | epilogue code fragment BUT 'ret' instruction. */ | |
5186 | if (cfun->machine->naked_p) | |
5187 | { | |
03390cda | 5188 | /* Generate return instruction by using 'return_internal' pattern. |
54c537e6 CJW |
5189 | Make sure this instruction is after gen_blockage(). |
5190 | First we need to check this is a function without sibling call. */ | |
d6529176 | 5191 | if (!sibcall_p) |
54c537e6 CJW |
5192 | { |
5193 | /* We need to further check attributes to determine whether | |
5194 | there should be return instruction at epilogue. | |
5195 | If the attribute naked exists but -mno-ret-in-naked-func | |
5196 | is issued, there is NO need to generate return instruction. */ | |
5197 | if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) | |
5198 | return; | |
5199 | ||
5200 | emit_jump_insn (gen_return_internal ()); | |
5201 | } | |
9304f876 CJW |
5202 | return; |
5203 | } | |
5204 | ||
5205 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
5206 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
5207 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
5208 | |
5209 | /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available, | |
5210 | where imm8u has to be 8-byte alignment. */ | |
5211 | sp_adjust = cfun->machine->local_size | |
5212 | + cfun->machine->out_args_size | |
e2286268 MC |
5213 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
5214 | + cfun->machine->callee_saved_fpr_regs_size; | |
9304f876 CJW |
5215 | |
5216 | /* We have to consider alloca issue as well. | |
5217 | If the function does call alloca(), the stack pointer is not fixed. | |
5218 | In that case, we cannot use 'pop25 Re,imm8u' directly. | |
5219 | We have to caculate stack pointer from frame pointer | |
5220 | and then use 'pop25 Re,0'. | |
5221 | Of course, the frame_pointer_needed should be nonzero | |
5222 | if the function calls alloca(). */ | |
5223 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
5224 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) | |
5225 | && !cfun->calls_alloca) | |
5226 | { | |
e2286268 MC |
5227 | /* Restore fpu registers. */ |
5228 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5229 | { | |
5230 | int fpr_position = cfun->machine->local_size | |
5231 | + cfun->machine->out_args_size; | |
5232 | /* Emit fpu load instruction, using [$sp + offset] restore | |
5233 | fpu registers. */ | |
5234 | nds32_emit_v3pop_fpr_callee_saved (fpr_position); | |
5235 | } | |
5236 | ||
9304f876 CJW |
5237 | /* We can use 'pop25 Re,imm8u'. */ |
5238 | ||
88437f39 | 5239 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), |
a6c7e777 MC |
5240 | the pattern 'stack_v3pop' is implementad in nds32.md. */ |
5241 | nds32_emit_stack_v3pop (Rb, Re, sp_adjust); | |
9304f876 CJW |
5242 | } |
5243 | else | |
5244 | { | |
5245 | /* We have to use 'pop25 Re,0', and prior to it, | |
8a498f99 | 5246 | we must expand one more instruction to adjust $sp. */ |
9304f876 CJW |
5247 | |
5248 | if (frame_pointer_needed) | |
5249 | { | |
5250 | /* adjust $sp = $fp - 4 ($fp size) | |
8a498f99 CJW |
5251 | - 4 ($gp size) |
5252 | - 4 ($lp size) | |
5253 | - (4 * n) (callee-saved registers) | |
9304f876 | 5254 | Note: No need to adjust |
8a498f99 CJW |
5255 | cfun->machine->callee_saved_area_gpr_padding_bytes, |
5256 | because we want to adjust stack pointer | |
5257 | to the position for pop instruction. */ | |
9304f876 CJW |
5258 | sp_adjust = cfun->machine->fp_size |
5259 | + cfun->machine->gp_size | |
5260 | + cfun->machine->lp_size | |
c457f751 | 5261 | + cfun->machine->callee_saved_gpr_regs_size; |
a6c7e777 | 5262 | |
e2286268 MC |
5263 | /* Restore fpu registers. */ |
5264 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5265 | { | |
5266 | /* Set $sp to callee saved fpr position, we need to restore | |
5267 | fpr registers. */ | |
5268 | sp_adjust = sp_adjust | |
5269 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
5270 | + cfun->machine->callee_saved_fpr_regs_size; | |
5271 | ||
5272 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5273 | hard_frame_pointer_rtx, | |
5274 | -1 * sp_adjust); | |
5275 | ||
5276 | /* Emit fpu load instruction, using [$sp + offset] restore | |
5277 | fpu registers. */ | |
5278 | nds32_emit_v3pop_fpr_callee_saved (0); | |
5279 | } | |
5280 | else | |
5281 | { | |
5282 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5283 | hard_frame_pointer_rtx, | |
5284 | -1 * sp_adjust); | |
5285 | } | |
9304f876 CJW |
5286 | } |
5287 | else | |
5288 | { | |
5289 | /* If frame pointer is NOT needed, | |
5290 | we cannot calculate the sp adjustment from frame pointer. | |
5291 | Instead, we calculate the adjustment by local_size, | |
5292 | out_args_size, and callee_saved_area_padding_bytes. | |
5293 | Notice that such sp adjustment value may be out of range, | |
5294 | so we have to deal with it as well. */ | |
5295 | ||
5296 | /* Adjust $sp = $sp + local_size + out_args_size | |
e2286268 MC |
5297 | + callee_saved_area_gpr_padding_bytes |
5298 | + callee_saved_fpr_regs_size. */ | |
9304f876 CJW |
5299 | sp_adjust = cfun->machine->local_size |
5300 | + cfun->machine->out_args_size | |
e2286268 MC |
5301 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
5302 | + cfun->machine->callee_saved_fpr_regs_size; | |
5303 | ||
5304 | /* Restore fpu registers. */ | |
5305 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5306 | { | |
5307 | /* Set $sp to callee saved fpr position, we need to restore | |
5308 | fpr registers. */ | |
5309 | sp_adjust = sp_adjust | |
5310 | - cfun->machine->callee_saved_area_gpr_padding_bytes | |
5311 | - cfun->machine->callee_saved_fpr_regs_size; | |
5312 | ||
5313 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5314 | stack_pointer_rtx, | |
5315 | sp_adjust); | |
5316 | ||
5317 | /* Emit fpu load instruction, using [$sp + offset] restore | |
5318 | fpu registers. */ | |
5319 | nds32_emit_v3pop_fpr_callee_saved (0); | |
5320 | } | |
5321 | else | |
5322 | { | |
5323 | /* sp_adjust value may be out of range of the addi instruction, | |
5324 | create alternative add behavior with TA_REGNUM if necessary, | |
5325 | using POSITIVE value to tell that we are increasing | |
5326 | address. */ | |
5327 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5328 | stack_pointer_rtx, | |
5329 | sp_adjust); | |
5330 | } | |
9304f876 CJW |
5331 | } |
5332 | ||
e2286268 MC |
5333 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5334 | { | |
5335 | /* We have fpr need to restore, so $sp is set on callee saved fpr | |
5336 | position. And we use 'pop25 Re, fpr_space' to adjust $sp. */ | |
5337 | int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes | |
5338 | + cfun->machine->callee_saved_fpr_regs_size; | |
5339 | nds32_emit_stack_v3pop (Rb, Re, fpr_space); | |
5340 | } | |
5341 | else | |
5342 | { | |
5343 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), | |
5344 | the pattern 'stack_v3pop' is implementad in nds32.md. */ | |
5345 | nds32_emit_stack_v3pop (Rb, Re, 0); | |
5346 | } | |
9304f876 | 5347 | } |
aa2642ef CJW |
5348 | /* Generate return instruction. */ |
5349 | emit_jump_insn (gen_pop25return ()); | |
9304f876 CJW |
5350 | } |
5351 | ||
03390cda CJW |
5352 | /* Return nonzero if this function is known to have a null epilogue. |
5353 | This allows the optimizer to omit jumps to jumps if no stack | |
5354 | was created. */ | |
5355 | int | |
5356 | nds32_can_use_return_insn (void) | |
5357 | { | |
e2286268 MC |
5358 | int sp_adjust; |
5359 | ||
03390cda | 5360 | /* Prior to reloading, we can't tell how many registers must be saved. |
67914693 | 5361 | Thus we cannot determine whether this function has null epilogue. */ |
03390cda CJW |
5362 | if (!reload_completed) |
5363 | return 0; | |
5364 | ||
54c537e6 CJW |
5365 | /* If attribute 'naked' appears but -mno-ret-in-naked-func is used, |
5366 | we cannot use return instruction. */ | |
5367 | if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) | |
5368 | return 0; | |
5369 | ||
e2286268 MC |
5370 | sp_adjust = cfun->machine->local_size |
5371 | + cfun->machine->out_args_size | |
5372 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
5373 | + cfun->machine->callee_saved_fpr_regs_size; | |
5374 | if (!cfun->machine->fp_as_gp_p | |
5375 | && satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
5376 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) | |
5377 | && !cfun->calls_alloca | |
5378 | && NDS32_V3PUSH_AVAILABLE_P | |
5379 | && !(TARGET_HARD_FLOAT | |
5380 | && (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM))) | |
5381 | return 1; | |
5382 | ||
03390cda CJW |
5383 | /* If no stack was created, two conditions must be satisfied: |
5384 | 1. This is a naked function. | |
8a498f99 | 5385 | So there is no callee-saved, local size, or outgoing size. |
03390cda | 5386 | 2. This is NOT a variadic function. |
8a498f99 | 5387 | So there is no pushing arguement registers into the stack. */ |
03390cda CJW |
5388 | return (cfun->machine->naked_p && (cfun->machine->va_args_size == 0)); |
5389 | } | |
5390 | ||
2f1bb3ca SC |
5391 | scalar_int_mode |
5392 | nds32_case_vector_shorten_mode (int min_offset, int max_offset, | |
5393 | rtx body ATTRIBUTE_UNUSED) | |
5394 | { | |
5395 | if (min_offset < 0 || max_offset >= 0x2000) | |
5396 | return SImode; | |
5397 | else | |
5398 | { | |
5399 | /* The jump table maybe need to 2 byte alignment, | |
5400 | so reserved 1 byte for check max_offset. */ | |
5401 | if (max_offset >= 0xff) | |
5402 | return HImode; | |
5403 | else | |
5404 | return QImode; | |
5405 | } | |
5406 | } | |
5407 | ||
9304f876 CJW |
5408 | /* ------------------------------------------------------------------------ */ |
5409 | ||
43fa41c1 CJW |
5410 | /* Return alignment for the label. */ |
5411 | int | |
5412 | nds32_target_alignment (rtx_insn *label) | |
5413 | { | |
5414 | rtx_insn *insn; | |
5415 | ||
5416 | if (!NDS32_ALIGN_P ()) | |
5417 | return 0; | |
5418 | ||
5419 | insn = next_active_insn (label); | |
5420 | ||
5421 | /* Always align to 4 byte when first instruction after label is jump | |
5422 | instruction since length for that might changed, so let's always align | |
5423 | it for make sure we don't lose any perfomance here. */ | |
5424 | if (insn == 0 | |
5425 | || (get_attr_length (insn) == 2 | |
5426 | && !JUMP_P (insn) && !CALL_P (insn))) | |
5427 | return 0; | |
5428 | else | |
5429 | return 2; | |
5430 | } | |
5431 | ||
79498ad8 CJW |
5432 | /* Return alignment for data. */ |
5433 | unsigned int | |
5434 | nds32_data_alignment (tree data, | |
5435 | unsigned int basic_align) | |
5436 | { | |
5437 | if ((basic_align < BITS_PER_WORD) | |
5438 | && (TREE_CODE (data) == ARRAY_TYPE | |
5439 | || TREE_CODE (data) == UNION_TYPE | |
5440 | || TREE_CODE (data) == RECORD_TYPE)) | |
5441 | return BITS_PER_WORD; | |
5442 | else | |
5443 | return basic_align; | |
5444 | } | |
5445 | ||
5446 | /* Return alignment for constant value. */ | |
5447 | static HOST_WIDE_INT | |
5448 | nds32_constant_alignment (const_tree constant, | |
5449 | HOST_WIDE_INT basic_align) | |
5450 | { | |
5451 | /* Make string literal and constant for constructor to word align. */ | |
5452 | if (((TREE_CODE (constant) == STRING_CST | |
5453 | || TREE_CODE (constant) == CONSTRUCTOR | |
5454 | || TREE_CODE (constant) == UNION_TYPE | |
5455 | || TREE_CODE (constant) == RECORD_TYPE | |
5456 | || TREE_CODE (constant) == ARRAY_TYPE) | |
5457 | && basic_align < BITS_PER_WORD)) | |
5458 | return BITS_PER_WORD; | |
5459 | else | |
5460 | return basic_align; | |
5461 | } | |
5462 | ||
5463 | /* Return alignment for local variable. */ | |
5464 | unsigned int | |
5465 | nds32_local_alignment (tree local ATTRIBUTE_UNUSED, | |
5466 | unsigned int basic_align) | |
5467 | { | |
5468 | bool at_least_align_to_word = false; | |
5469 | /* Make local array, struct and union at least align to word for make | |
5470 | sure it can unroll memcpy when initialize by constant. */ | |
5471 | switch (TREE_CODE (local)) | |
5472 | { | |
5473 | case ARRAY_TYPE: | |
5474 | case RECORD_TYPE: | |
5475 | case UNION_TYPE: | |
5476 | at_least_align_to_word = true; | |
5477 | break; | |
5478 | default: | |
5479 | at_least_align_to_word = false; | |
5480 | break; | |
5481 | } | |
5482 | if (at_least_align_to_word | |
5483 | && (basic_align < BITS_PER_WORD)) | |
5484 | return BITS_PER_WORD; | |
5485 | else | |
5486 | return basic_align; | |
5487 | } | |
5488 | ||
e2286268 MC |
5489 | bool |
5490 | nds32_split_double_word_load_store_p(rtx *operands, bool load_p) | |
5491 | { | |
5492 | rtx mem = load_p ? operands[1] : operands[0]; | |
5493 | /* Do split at split2 if -O0 or schedule 2 not enable. */ | |
5494 | if (optimize == 0 || !flag_schedule_insns_after_reload) | |
5495 | return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); | |
5496 | ||
5497 | /* Split double word load store after copy propgation. */ | |
5498 | if (current_pass == NULL) | |
5499 | return false; | |
5500 | ||
5501 | const char *pass_name = current_pass->name; | |
f4777088 | 5502 | if (pass_name && ((strcmp (pass_name, "split3") == 0) |
e2286268 MC |
5503 | || (strcmp (pass_name, "split5") == 0))) |
5504 | return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); | |
5505 | ||
5506 | return false; | |
5507 | } | |
5508 | ||
5509 | static bool | |
5510 | nds32_use_blocks_for_constant_p (machine_mode mode, | |
5511 | const_rtx x ATTRIBUTE_UNUSED) | |
5512 | { | |
5513 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
5514 | && (mode == DFmode || mode == SFmode)) | |
5515 | return true; | |
5516 | else | |
5517 | return false; | |
5518 | } | |
9304f876 | 5519 | |
9304f876 CJW |
5520 | /* ------------------------------------------------------------------------ */ |
5521 | ||
5522 | /* PART 5: Initialize target hook structure and definitions. */ | |
5523 | \f | |
5524 | /* Controlling the Compilation Driver. */ | |
5525 | ||
5526 | \f | |
5527 | /* Run-time Target Specification. */ | |
5528 | ||
5529 | \f | |
5530 | /* Defining Data Structures for Per-function Information. */ | |
5531 | ||
5532 | \f | |
5533 | /* Storage Layout. */ | |
5534 | ||
5535 | #undef TARGET_PROMOTE_FUNCTION_MODE | |
5536 | #define TARGET_PROMOTE_FUNCTION_MODE \ | |
5537 | default_promote_function_mode_always_promote | |
5538 | ||
5f2a98c3 CJW |
5539 | #undef TARGET_EXPAND_TO_RTL_HOOK |
5540 | #define TARGET_EXPAND_TO_RTL_HOOK nds32_expand_to_rtl_hook | |
5541 | ||
79498ad8 CJW |
5542 | #undef TARGET_CONSTANT_ALIGNMENT |
5543 | #define TARGET_CONSTANT_ALIGNMENT nds32_constant_alignment | |
5544 | ||
9304f876 CJW |
5545 | \f |
5546 | /* Layout of Source Language Data Types. */ | |
5547 | ||
5548 | \f | |
5549 | /* Register Usage. */ | |
5550 | ||
5551 | /* -- Basic Characteristics of Registers. */ | |
5552 | ||
e2286268 MC |
5553 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
5554 | #define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage | |
5555 | ||
9304f876 CJW |
5556 | /* -- Order of Allocation of Registers. */ |
5557 | ||
5558 | /* -- How Values Fit in Registers. */ | |
5559 | ||
e2286268 MC |
5560 | #undef TARGET_HARD_REGNO_NREGS |
5561 | #define TARGET_HARD_REGNO_NREGS nds32_hard_regno_nregs | |
5562 | ||
50256c75 CJW |
5563 | #undef TARGET_HARD_REGNO_MODE_OK |
5564 | #define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok | |
5565 | ||
5566 | #undef TARGET_MODES_TIEABLE_P | |
5567 | #define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p | |
5568 | ||
9304f876 CJW |
5569 | /* -- Handling Leaf Functions. */ |
5570 | ||
5571 | /* -- Registers That Form a Stack. */ | |
5572 | ||
5573 | \f | |
5574 | /* Register Classes. */ | |
5575 | ||
5576 | #undef TARGET_CLASS_MAX_NREGS | |
5577 | #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs | |
5578 | ||
9304f876 CJW |
5579 | #undef TARGET_REGISTER_PRIORITY |
5580 | #define TARGET_REGISTER_PRIORITY nds32_register_priority | |
5581 | ||
e2286268 MC |
5582 | #undef TARGET_CAN_CHANGE_MODE_CLASS |
5583 | #define TARGET_CAN_CHANGE_MODE_CLASS nds32_can_change_mode_class | |
5584 | ||
9304f876 CJW |
5585 | \f |
5586 | /* Obsolete Macros for Defining Constraints. */ | |
5587 | ||
5588 | \f | |
5589 | /* Stack Layout and Calling Conventions. */ | |
5590 | ||
5591 | /* -- Basic Stack Layout. */ | |
5592 | ||
5593 | /* -- Exception Handling Support. */ | |
5594 | ||
5595 | /* -- Specifying How Stack Checking is Done. */ | |
5596 | ||
5597 | /* -- Registers That Address the Stack Frame. */ | |
5598 | ||
5599 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
5600 | ||
5601 | #undef TARGET_CAN_ELIMINATE | |
5602 | #define TARGET_CAN_ELIMINATE nds32_can_eliminate | |
5603 | ||
5604 | /* -- Passing Function Arguments on the Stack. */ | |
5605 | ||
5606 | /* -- Passing Arguments in Registers. */ | |
5607 | ||
5608 | #undef TARGET_FUNCTION_ARG | |
5609 | #define TARGET_FUNCTION_ARG nds32_function_arg | |
5610 | ||
d40f3c40 CJW |
5611 | #undef TARGET_MUST_PASS_IN_STACK |
5612 | #define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack | |
5613 | ||
650fc469 CJW |
5614 | #undef TARGET_ARG_PARTIAL_BYTES |
5615 | #define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes | |
5616 | ||
9304f876 CJW |
5617 | #undef TARGET_FUNCTION_ARG_ADVANCE |
5618 | #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance | |
5619 | ||
5620 | #undef TARGET_FUNCTION_ARG_BOUNDARY | |
5621 | #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary | |
5622 | ||
7c32ef41 MC |
5623 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
5624 | #define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p | |
5625 | ||
9304f876 CJW |
5626 | /* -- How Scalar Function Values Are Returned. */ |
5627 | ||
5628 | #undef TARGET_FUNCTION_VALUE | |
5629 | #define TARGET_FUNCTION_VALUE nds32_function_value | |
5630 | ||
5631 | #undef TARGET_LIBCALL_VALUE | |
5632 | #define TARGET_LIBCALL_VALUE nds32_libcall_value | |
5633 | ||
5634 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
5635 | #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p | |
5636 | ||
5637 | /* -- How Large Values Are Returned. */ | |
5638 | ||
e2286268 MC |
5639 | #undef TARGET_RETURN_IN_MEMORY |
5640 | #define TARGET_RETURN_IN_MEMORY nds32_return_in_memory | |
5641 | ||
9304f876 CJW |
5642 | /* -- Caller-Saves Register Allocation. */ |
5643 | ||
5644 | /* -- Function Entry and Exit. */ | |
5645 | ||
5646 | #undef TARGET_ASM_FUNCTION_PROLOGUE | |
5647 | #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue | |
5648 | ||
5649 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE | |
5650 | #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue | |
5651 | ||
5652 | #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE | |
5653 | #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue | |
5654 | ||
5655 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
5656 | #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue | |
5657 | ||
5658 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
5659 | #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk | |
5660 | ||
5661 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
5662 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
5663 | ||
5664 | /* -- Generating Code for Profiling. */ | |
5665 | ||
5666 | /* -- Permitting tail calls. */ | |
5667 | ||
cc48a87f CJW |
5668 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
5669 | #define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall | |
5670 | ||
9304f876 CJW |
5671 | #undef TARGET_WARN_FUNC_RETURN |
5672 | #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return | |
5673 | ||
5674 | /* Stack smashing protection. */ | |
5675 | ||
5676 | \f | |
5677 | /* Implementing the Varargs Macros. */ | |
5678 | ||
d4a6a4d9 CJW |
5679 | #undef TARGET_SETUP_INCOMING_VARARGS |
5680 | #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs | |
5681 | ||
9304f876 CJW |
5682 | #undef TARGET_STRICT_ARGUMENT_NAMING |
5683 | #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming | |
5684 | ||
5685 | \f | |
5686 | /* Trampolines for Nested Functions. */ | |
5687 | ||
5688 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE | |
5689 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template | |
5690 | ||
5691 | #undef TARGET_TRAMPOLINE_INIT | |
5692 | #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init | |
5693 | ||
5694 | \f | |
5695 | /* Implicit Calls to Library Routines. */ | |
5696 | ||
5697 | \f | |
5698 | /* Addressing Modes. */ | |
5699 | ||
5700 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
5701 | #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p | |
5702 | ||
85a98076 KLC |
5703 | #undef TARGET_LEGITIMIZE_ADDRESS |
5704 | #define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address | |
5705 | ||
5706 | #undef TARGET_LEGITIMATE_CONSTANT_P | |
5707 | #define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p | |
5708 | ||
7c32ef41 MC |
5709 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE |
5710 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode | |
5711 | ||
85a98076 KLC |
5712 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
5713 | #define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem | |
5714 | ||
5715 | #undef TARGET_DELEGITIMIZE_ADDRESS | |
5716 | #define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address | |
5717 | ||
9304f876 CJW |
5718 | \f |
5719 | /* Anchored Addresses. */ | |
5720 | ||
5721 | \f | |
5722 | /* Condition Code Status. */ | |
5723 | ||
5724 | /* -- Representation of condition codes using (cc0). */ | |
5725 | ||
5726 | /* -- Representation of condition codes using registers. */ | |
5727 | ||
5b6f2bf3 CJW |
5728 | #undef TARGET_CANONICALIZE_COMPARISON |
5729 | #define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison | |
5730 | ||
9304f876 CJW |
5731 | /* -- Macros to control conditional execution. */ |
5732 | ||
5733 | \f | |
5734 | /* Describing Relative Costs of Operations. */ | |
5735 | ||
5736 | #undef TARGET_REGISTER_MOVE_COST | |
5737 | #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost | |
5738 | ||
5739 | #undef TARGET_MEMORY_MOVE_COST | |
5740 | #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost | |
5741 | ||
5742 | #undef TARGET_RTX_COSTS | |
5743 | #define TARGET_RTX_COSTS nds32_rtx_costs | |
5744 | ||
5745 | #undef TARGET_ADDRESS_COST | |
5746 | #define TARGET_ADDRESS_COST nds32_address_cost | |
5747 | ||
5748 | \f | |
5749 | /* Adjusting the Instruction Scheduler. */ | |
5750 | ||
5751 | \f | |
5752 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
5753 | ||
511a41d7 CJW |
5754 | #undef TARGET_ENCODE_SECTION_INFO |
5755 | #define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info | |
5756 | ||
9304f876 CJW |
5757 | \f |
5758 | /* Position Independent Code. */ | |
5759 | ||
5760 | \f | |
5761 | /* Defining the Output Assembler Language. */ | |
5762 | ||
5763 | /* -- The Overall Framework of an Assembler File. */ | |
5764 | ||
5765 | #undef TARGET_ASM_FILE_START | |
5766 | #define TARGET_ASM_FILE_START nds32_asm_file_start | |
5767 | #undef TARGET_ASM_FILE_END | |
5768 | #define TARGET_ASM_FILE_END nds32_asm_file_end | |
5769 | ||
5770 | /* -- Output of Data. */ | |
5771 | ||
5772 | #undef TARGET_ASM_ALIGNED_HI_OP | |
5773 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
5774 | ||
5775 | #undef TARGET_ASM_ALIGNED_SI_OP | |
5776 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
5777 | ||
85a98076 KLC |
5778 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
5779 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra | |
5780 | ||
9304f876 CJW |
5781 | /* -- Output of Uninitialized Variables. */ |
5782 | ||
5783 | /* -- Output and Generation of Labels. */ | |
5784 | ||
5785 | #undef TARGET_ASM_GLOBALIZE_LABEL | |
5786 | #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label | |
5787 | ||
5788 | /* -- How Initialization Functions Are Handled. */ | |
5789 | ||
5790 | /* -- Macros Controlling Initialization Routines. */ | |
5791 | ||
5792 | /* -- Output of Assembler Instructions. */ | |
5793 | ||
5794 | #undef TARGET_PRINT_OPERAND | |
5795 | #define TARGET_PRINT_OPERAND nds32_print_operand | |
5796 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
5797 | #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address | |
5798 | ||
5799 | /* -- Output of Dispatch Tables. */ | |
5800 | ||
5801 | /* -- Assembler Commands for Exception Regions. */ | |
5802 | ||
e2286268 MC |
5803 | #undef TARGET_DWARF_REGISTER_SPAN |
5804 | #define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span | |
5805 | ||
9304f876 CJW |
5806 | /* -- Assembler Commands for Alignment. */ |
5807 | ||
5808 | \f | |
5809 | /* Controlling Debugging Information Format. */ | |
5810 | ||
5811 | /* -- Macros Affecting All Debugging Formats. */ | |
5812 | ||
180295ed | 5813 | /* -- Macros for DWARF Output. */ |
9304f876 CJW |
5814 | |
5815 | /* -- Macros for VMS Debug Format. */ | |
5816 | ||
5817 | \f | |
5818 | /* Cross Compilation and Floating Point. */ | |
5819 | ||
5820 | \f | |
5821 | /* Mode Switching Instructions. */ | |
5822 | ||
5823 | \f | |
5824 | /* Defining target-specific uses of __attribute__. */ | |
5825 | ||
5826 | #undef TARGET_ATTRIBUTE_TABLE | |
5827 | #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table | |
5828 | ||
5829 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
5830 | #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes | |
5831 | ||
5832 | #undef TARGET_INSERT_ATTRIBUTES | |
5833 | #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes | |
5834 | ||
5835 | #undef TARGET_OPTION_PRAGMA_PARSE | |
5836 | #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse | |
5837 | ||
5838 | #undef TARGET_OPTION_OVERRIDE | |
5839 | #define TARGET_OPTION_OVERRIDE nds32_option_override | |
5840 | ||
5841 | \f | |
5842 | /* Emulating TLS. */ | |
5843 | ||
cf3cd43d CJW |
5844 | #undef TARGET_HAVE_TLS |
5845 | #define TARGET_HAVE_TLS TARGET_LINUX_ABI | |
5846 | ||
9304f876 CJW |
5847 | \f |
5848 | /* Defining coprocessor specifics for MIPS targets. */ | |
5849 | ||
5850 | \f | |
5851 | /* Parameters for Precompiled Header Validity Checking. */ | |
5852 | ||
5853 | \f | |
5854 | /* C++ ABI parameters. */ | |
5855 | ||
5856 | \f | |
5857 | /* Adding support for named address spaces. */ | |
5858 | ||
5859 | \f | |
5860 | /* Miscellaneous Parameters. */ | |
5861 | ||
823835a9 CJW |
5862 | #undef TARGET_MD_ASM_ADJUST |
5863 | #define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust | |
5864 | ||
9304f876 CJW |
5865 | #undef TARGET_INIT_BUILTINS |
5866 | #define TARGET_INIT_BUILTINS nds32_init_builtins | |
5867 | ||
7a12ea32 MC |
5868 | #undef TARGET_BUILTIN_DECL |
5869 | #define TARGET_BUILTIN_DECL nds32_builtin_decl | |
5870 | ||
9304f876 CJW |
5871 | #undef TARGET_EXPAND_BUILTIN |
5872 | #define TARGET_EXPAND_BUILTIN nds32_expand_builtin | |
5873 | ||
cf3cd43d CJW |
5874 | #undef TARGET_INIT_LIBFUNCS |
5875 | #define TARGET_INIT_LIBFUNCS nds32_init_libfuncs | |
e2286268 MC |
5876 | |
5877 | #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P | |
5878 | #define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p | |
5879 | ||
091a8640 CJW |
5880 | #undef TARGET_HAVE_SPECULATION_SAFE_VALUE |
5881 | #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed | |
5882 | ||
9304f876 CJW |
5883 | \f |
5884 | /* ------------------------------------------------------------------------ */ | |
5885 | ||
5886 | /* Initialize the GCC target structure. */ | |
5887 | ||
5888 | struct gcc_target targetm = TARGET_INITIALIZER; | |
5889 | ||
5890 | /* ------------------------------------------------------------------------ */ |