]> gcc.gnu.org Git - gcc.git/blame - gcc/config/mips/mips.md
git://gcc.gnu.org / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
(main): Unlimit stack size.
[gcc.git] / gcc / config / mips / mips.md
CommitLineData
8ef30996
MM		 1;; Mips.md Machine Description for MIPS based processors
2;; Contributed by A. Lichnewsky, lich@inria.inria.fr
3;; Changes by Michael Meissner, meissner@osf.org
4;; Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc.
5
6;; This file is part of GNU CC.
7
8;; GNU CC is free software; you can redistribute it and/or modify
9;; it under the terms of the GNU General Public License as published by
10;; the Free Software Foundation; either version 2, or (at your option)
11;; any later version.
12
13;; GNU CC is distributed in the hope that it will be useful,
14;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16;; GNU General Public License for more details.
17
18;; You should have received a copy of the GNU General Public License
19;; along with GNU CC; see the file COPYING. If not, write to
20;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22\f
23
24;; ....................
25;;
26;; Attributes
27;;
28;; ....................
29
30;; Classification of each insn.
31;; branch conditional branch
32;; jump unconditional jump
33;; call unconditional call
34;; load load instruction(s)
35;; store store instruction(s)
36;; move data movement within same register set
37;; xfer transfer to/from coprocessor
38;; hilo transfer of hi/lo registers
39;; arith integer arithmetic instruction
40;; darith double precision integer arithmetic instructions
41;; imul integer multiply
42;; idiv integer divide
43;; icmp integer compare
44;; fadd floating point add/subtract
45;; fmul floating point multiply
46;; fdiv floating point divide
47;; fabs floating point absolute value
48;; fneg floating point negation
49;; fcmp floating point compare
50;; fcvt floating point convert
51;; fsqrt floating point square root
52;; multi multiword sequence (or user asm statements)
53;; nop no operation
8ef30996
MM		 54
55(define_attr "type"
c7343333 56 "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
8ef30996
MM		 57 (const_string "unknown"))
58
59;; Main data type used by the insn
34b650b3 60(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
8ef30996
MM		 61
62;; # instructions (4 bytes each)
63(define_attr "length" "" (const_int 1))
64
6d518002 65;; whether or not an instruction has a mandatory delay slot
8ef30996 66(define_attr "dslot" "no,yes"
c7343333 67 (if_then_else (eq_attr "type" "branch,jump,call,load,xfer,hilo,fcmp")
8ef30996
MM		 68 (const_string "yes")
69 (const_string "no")))
70
ddd8ab48
MM		 71;; Attribute describing the processor. This attribute must match exactly
72;; with the processor_type enumeration in mips.h.
73
8ef30996 74;; Attribute describing the processor
ddd8ab48
MM		 75;; (define_attr "cpu" "default,r3000,r6000,r4000"
76;; (const
77;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
78;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
79;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
80;; (const_string "default"))))
81
82(define_attr "cpu" "default,r3000,r6000,r4000"
83 (const (symbol_ref "mips_cpu_attr")))
8ef30996
MM		 84
85;; Attribute defining whether or not we can use the branch-likely instructions
86;; (MIPS ISA level 2)
87
88(define_attr "branch_likely" "no,yes"
6d518002 89 (const
8ef30996
MM		 90 (if_then_else (ge (symbol_ref "mips_isa") (const_int 2))
91 (const_string "yes")
6d518002 92 (const_string "no"))))
8ef30996
MM		 93
94
95;; Describe a user's asm statement.
96(define_asm_attributes
97 [(set_attr "type" "multi")])
98
99\f
100
101;; .........................
102;;
103;; Delay slots, can't describe load/fcmp/xfer delay slots here
104;;
105;; .........................
106
107(define_delay (eq_attr "type" "branch")
108 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
109 (nil)
bbdb5552 110 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))])
8ef30996
MM		 111
112(define_delay (eq_attr "type" "call,jump")
113 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
114 (nil)
115 (nil)])
116
117\f
118
119;; .........................
120;;
121;; Functional units
122;;
123;; .........................
124
125; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
c8e18a2b 126; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
8ef30996
MM		 127
128;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
129
130(define_function_unit "memory" 1 0
c7343333 131 (and (eq_attr "type" "load") (eq_attr "cpu" "!r3000"))
8ef30996
MM		 132 3 0)
133
134(define_function_unit "memory" 1 0
c7343333 135 (and (eq_attr "type" "load") (eq_attr "cpu" "r3000"))
8ef30996
MM		 136 2 0)
137
ddd8ab48 138(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
8ef30996 139
c3f3d7e1 140(define_function_unit "addr" 1 0 (eq_attr "type" "fcmp") 2 0)
34b650b3 141
c3f3d7e1
MM		 142(define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
143(define_function_unit "memory" 1 0 (eq_attr "type" "hilo") 3 0)
8ef30996
MM		 144
145(define_function_unit "imuldiv" 1 1
146 (and (eq_attr "type" "imul") (eq_attr "cpu" "!r3000,r4000"))
c8e18a2b 147 17 0)
8ef30996
MM		 148
149(define_function_unit "imuldiv" 1 1
150 (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000"))
c8e18a2b 151 12 0)
8ef30996
MM		 152
153(define_function_unit "imuldiv" 1 1
154 (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000"))
c8e18a2b 155 10 0)
8ef30996
MM		 156
157(define_function_unit "imuldiv" 1 1
158 (and (eq_attr "type" "idiv") (eq_attr "cpu" "!r3000,r4000"))
c8e18a2b 159 38 0)
8ef30996
MM		 160
161(define_function_unit "imuldiv" 1 1
162 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000"))
c8e18a2b 163 35 0)
8ef30996
MM		 164
165(define_function_unit "imuldiv" 1 1
166 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
c8e18a2b 167 69 0)
8ef30996
MM		 168
169(define_function_unit "adder" 1 1
170 (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r6000"))
c8e18a2b 171 4 0)
8ef30996
MM		 172
173(define_function_unit "adder" 1 1
174 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000"))
c8e18a2b 175 2 0)
8ef30996
MM		 176
177(define_function_unit "adder" 1 1
178 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
c8e18a2b 179 3 0)
8ef30996 180
ddd8ab48 181(define_function_unit "adder" 1 1
8ef30996 182 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "!r3000"))
c8e18a2b 183 2 0)
8ef30996 184
ddd8ab48 185(define_function_unit "adder" 1 1
8ef30996 186 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000"))
c8e18a2b 187 1 0)
8ef30996
MM		 188
189(define_function_unit "mult" 1 1
190 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r3000,r6000")))
c8e18a2b 191 7 0)
8ef30996
MM		 192
193(define_function_unit "mult" 1 1
194 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
c8e18a2b 195 4 0)
8ef30996
MM		 196
197(define_function_unit "mult" 1 1
198 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
c8e18a2b 199 5 0)
8ef30996
MM		 200
201(define_function_unit "mult" 1 1
202 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r6000")))
c8e18a2b 203 8 0)
8ef30996
MM		 204
205(define_function_unit "mult" 1 1
206 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
c8e18a2b 207 5 0)
8ef30996
MM		 208
209(define_function_unit "mult" 1 1
210 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
c8e18a2b 211 6 0)
8ef30996
MM		 212
213(define_function_unit "divide" 1 1
214 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r3000,r6000")))
c8e18a2b 215 23 0)
8ef30996
MM		 216
217(define_function_unit "divide" 1 1
218 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
c8e18a2b 219 12 0)
8ef30996
MM		 220
221(define_function_unit "divide" 1 1
222 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
c8e18a2b 223 15 0)
8ef30996
MM		 224
225(define_function_unit "divide" 1 1
226 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r6000")))
c8e18a2b 227 36 0)
8ef30996
MM		 228
229(define_function_unit "divide" 1 1
230 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
c8e18a2b 231 19 0)
8ef30996
MM		 232
233(define_function_unit "divide" 1 1
234 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
c8e18a2b 235 16 0)
8ef30996 236
c8e18a2b
TW		 237(define_function_unit "divide" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
238(define_function_unit "divide" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
8ef30996 239
ddd8ab48
MM		 240\f
241;; The following functional units do not use the cpu type, and use
242;; much less memory in genattrtab.c.
243
c8e18a2b
TW		 244;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
245;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
ddd8ab48 246;;
c8e18a2b 247;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
ddd8ab48 248;;
c8e18a2b
TW		 249;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
250;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
ddd8ab48 251;;
c8e18a2b
TW		 252;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
253;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
ddd8ab48 254;;
c8e18a2b
TW		 255;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
256;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
ddd8ab48 257;;
c8e18a2b
TW		 258;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
259;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
ddd8ab48 260;;
c8e18a2b
TW		 261;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
262;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
ddd8ab48 263;;
c8e18a2b
TW		 264;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
265;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
ddd8ab48 266
8ef30996
MM		 267\f
268;;
269;; ....................
270;;
271;; ADDITION
272;;
273;; ....................
274;;
275
276(define_insn "adddf3"
277 [(set (match_operand:DF 0 "register_operand" "=f")
278 (plus:DF (match_operand:DF 1 "register_operand" "f")
279 (match_operand:DF 2 "register_operand" "f")))]
280 "TARGET_HARD_FLOAT"
281 "add.d\\t%0,%1,%2"
282 [(set_attr "type" "fadd")
283 (set_attr "mode" "DF")
284 (set_attr "length" "1")])
285
286(define_insn "addsf3"
287 [(set (match_operand:SF 0 "register_operand" "=f")
288 (plus:SF (match_operand:SF 1 "register_operand" "f")
289 (match_operand:SF 2 "register_operand" "f")))]
290 "TARGET_HARD_FLOAT"
291 "add.s\\t%0,%1,%2"
292 [(set_attr "type" "fadd")
293 (set_attr "mode" "SF")
294 (set_attr "length" "1")])
295
71cd5224 296(define_expand "addsi3"
8ef30996 297 [(set (match_operand:SI 0 "register_operand" "=d")
71cd5224 298 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
8ef30996
MM		 299 (match_operand:SI 2 "arith_operand" "dI")))]
300 ""
71cd5224
RS		 301 "
302{
303 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
304 operands[2] = force_reg (SImode, operands[2]);
305}")
306
307(define_insn "addsi3_internal"
308 [(set (match_operand:SI 0 "register_operand" "=d")
309 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
310 (match_operand:SI 2 "arith_operand" "dI")))]
311 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768"
8ef30996
MM		 312 "*
313{
314 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
71cd5224
RS		 315 ? \"subu\\t%0,%z1,%n2\"
316 : \"addu\\t%0,%z1,%2\";
8ef30996
MM		 317}"
318 [(set_attr "type" "arith")
319 (set_attr "mode" "SI")
320 (set_attr "length" "1")])
321
322(define_expand "adddi3"
323 [(parallel [(set (match_operand:DI 0 "register_operand" "")
324 (plus:DI (match_operand:DI 1 "register_operand" "")
325 (match_operand:DI 2 "arith_operand" "")))
326 (clobber (match_dup 3))])]
327 "!TARGET_DEBUG_G_MODE"
92b4cee1
MM		 328 "
329{
330 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
331 operands[2] = force_reg (SImode, operands[2]);
332
333 operands[3] = gen_reg_rtx (SImode);
334}")
8ef30996
MM		 335
336(define_insn "adddi3_internal_1"
337 [(set (match_operand:DI 0 "register_operand" "=d,&d")
338 (plus:DI (match_operand:DI 1 "register_operand" "0,d")
339 (match_operand:DI 2 "register_operand" "d,d")))
340 (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
341 "!TARGET_DEBUG_G_MODE"
342 "*
343{
344 return (REGNO (operands[0]) == REGNO (operands[1])
345 && REGNO (operands[0]) == REGNO (operands[2]))
346 ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
347 : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
348}"
92b4cee1
MM		 349 [(set_attr "type" "darith")
350 (set_attr "mode" "DI")
351 (set_attr "length" "4")])
8ef30996
MM		 352
353(define_split
354 [(set (match_operand:DI 0 "register_operand" "")
355 (plus:DI (match_operand:DI 1 "register_operand" "")
356 (match_operand:DI 2 "register_operand" "")))
357 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 358 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 359 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
360 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
361 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
362 && (REGNO (operands[0]) != REGNO (operands[1])
363 || REGNO (operands[0]) != REGNO (operands[2]))"
364
365 [(set (subreg:SI (match_dup 0) 0)
366 (plus:SI (subreg:SI (match_dup 1) 0)
367 (subreg:SI (match_dup 2) 0)))
368
369 (set (match_dup 3)
34b650b3 370 (ltu:SI (subreg:SI (match_dup 0) 0)
8ef30996
MM		 371 (subreg:SI (match_dup 2) 0)))
372
373 (set (subreg:SI (match_dup 0) 1)
374 (plus:SI (subreg:SI (match_dup 1) 1)
375 (subreg:SI (match_dup 2) 1)))
376
377 (set (subreg:SI (match_dup 0) 1)
378 (plus:SI (subreg:SI (match_dup 0) 1)
379 (match_dup 3)))]
380 "")
381
382(define_split
383 [(set (match_operand:DI 0 "register_operand" "")
384 (plus:DI (match_operand:DI 1 "register_operand" "")
385 (match_operand:DI 2 "register_operand" "")))
386 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 387 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 388 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
389 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
390 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
391 && (REGNO (operands[0]) != REGNO (operands[1])
392 || REGNO (operands[0]) != REGNO (operands[2]))"
393
394 [(set (subreg:SI (match_dup 0) 1)
395 (plus:SI (subreg:SI (match_dup 1) 1)
396 (subreg:SI (match_dup 2) 1)))
397
398 (set (match_dup 3)
34b650b3 399 (ltu:SI (subreg:SI (match_dup 0) 1)
8ef30996
MM		 400 (subreg:SI (match_dup 2) 1)))
401
402 (set (subreg:SI (match_dup 0) 0)
403 (plus:SI (subreg:SI (match_dup 1) 0)
404 (subreg:SI (match_dup 2) 0)))
405
406 (set (subreg:SI (match_dup 0) 0)
407 (plus:SI (subreg:SI (match_dup 0) 0)
408 (match_dup 3)))]
409 "")
410
411(define_insn "adddi3_internal_2"
412 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
413 (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
414 (match_operand:DI 2 "small_int" "P,J,N")))
415 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
416 "!TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
417 "@
418 addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
419 move\\t%L0,%L1\;move\\t%M0,%M1
420 subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
92b4cee1
MM		 421 [(set_attr "type" "darith")
422 (set_attr "mode" "DI")
8ef30996
MM		 423 (set_attr "length" "3,2,4")])
424
425(define_split
426 [(set (match_operand:DI 0 "register_operand" "")
427 (plus:DI (match_operand:DI 1 "register_operand" "")
428 (match_operand:DI 2 "small_int" "")))
429 (clobber (match_operand:SI 3 "register_operand" "=d"))]
26b8e6e5 430 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 431 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
432 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
433 && INTVAL (operands[2]) > 0"
434
435 [(set (subreg:SI (match_dup 0) 0)
436 (plus:SI (subreg:SI (match_dup 1) 0)
437 (match_dup 2)))
438
439 (set (match_dup 3)
34b650b3 440 (ltu:SI (subreg:SI (match_dup 0) 0)
8ef30996
MM		 441 (match_dup 2)))
442
443 (set (subreg:SI (match_dup 0) 1)
444 (plus:SI (subreg:SI (match_dup 1) 1)
445 (match_dup 3)))]
446 "")
447
448(define_split
449 [(set (match_operand:DI 0 "register_operand" "")
450 (plus:DI (match_operand:DI 1 "register_operand" "")
451 (match_operand:DI 2 "small_int" "")))
452 (clobber (match_operand:SI 3 "register_operand" "=d"))]
26b8e6e5 453 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 454 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
455 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
456 && INTVAL (operands[2]) > 0"
457
458 [(set (subreg:SI (match_dup 0) 1)
459 (plus:SI (subreg:SI (match_dup 1) 1)
460 (match_dup 2)))
461
462 (set (match_dup 3)
34b650b3 463 (ltu:SI (subreg:SI (match_dup 0) 1)
8ef30996
MM		 464 (match_dup 2)))
465
466 (set (subreg:SI (match_dup 0) 0)
467 (plus:SI (subreg:SI (match_dup 1) 0)
468 (match_dup 3)))]
469 "")
470\f
471;;
472;; ....................
473;;
474;; SUBTRACTION
475;;
476;; ....................
477;;
478
479(define_insn "subdf3"
480 [(set (match_operand:DF 0 "register_operand" "=f")
481 (minus:DF (match_operand:DF 1 "register_operand" "f")
482 (match_operand:DF 2 "register_operand" "f")))]
483 "TARGET_HARD_FLOAT"
484 "sub.d\\t%0,%1,%2"
485 [(set_attr "type" "fadd")
486 (set_attr "mode" "DF")
487 (set_attr "length" "1")])
488
489(define_insn "subsf3"
490 [(set (match_operand:SF 0 "register_operand" "=f")
491 (minus:SF (match_operand:SF 1 "register_operand" "f")
492 (match_operand:SF 2 "register_operand" "f")))]
493 "TARGET_HARD_FLOAT"
494 "sub.s\\t%0,%1,%2"
495 [(set_attr "type" "fadd")
496 (set_attr "mode" "SF")
497 (set_attr "length" "1")])
498
71cd5224 499(define_expand "subsi3"
8ef30996
MM		 500 [(set (match_operand:SI 0 "register_operand" "=d")
501 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
502 (match_operand:SI 2 "arith_operand" "dI")))]
503 ""
71cd5224
RS		 504 "
505{
506 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
507 operands[2] = force_reg (SImode, operands[2]);
508}")
509
510(define_insn "subsi3_internal"
511 [(set (match_operand:SI 0 "register_operand" "=d")
512 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
513 (match_operand:SI 2 "arith_operand" "dI")))]
514 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768"
8ef30996
MM		 515 "*
516{
517 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
518 ? \"addu\\t%0,%z1,%n2\"
519 : \"subu\\t%0,%z1,%2\";
520}"
521 [(set_attr "type" "arith")
522 (set_attr "mode" "SI")
523 (set_attr "length" "1")])
524
525(define_expand "subdi3"
526 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
527 (minus:DI (match_operand:DI 1 "register_operand" "d")
528 (match_operand:DI 2 "register_operand" "d")))
529 (clobber (match_dup 3))])]
530 "!TARGET_DEBUG_G_MODE"
531 "operands[3] = gen_reg_rtx (SImode);")
532
533(define_insn "subdi3_internal"
534 [(set (match_operand:DI 0 "register_operand" "=d")
535 (minus:DI (match_operand:DI 1 "register_operand" "d")
536 (match_operand:DI 2 "register_operand" "d")))
537 (clobber (match_operand:SI 3 "register_operand" "=d"))]
538 "!TARGET_DEBUG_G_MODE"
539 "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
540 [(set_attr "type" "darith")
541 (set_attr "mode" "DI")
542 (set_attr "length" "4")])
543
544(define_split
545 [(set (match_operand:DI 0 "register_operand" "")
546 (minus:DI (match_operand:DI 1 "register_operand" "")
547 (match_operand:DI 2 "register_operand" "")))
548 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 549 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 550 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
551 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
552 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
553
554 [(set (match_dup 3)
34b650b3 555 (ltu:SI (subreg:SI (match_dup 1) 0)
6d518002 556 (subreg:SI (match_dup 2) 0)))
8ef30996
MM		 557
558 (set (subreg:SI (match_dup 0) 0)
559 (minus:SI (subreg:SI (match_dup 1) 0)
560 (subreg:SI (match_dup 2) 0)))
561
562 (set (subreg:SI (match_dup 0) 1)
563 (minus:SI (subreg:SI (match_dup 1) 1)
564 (subreg:SI (match_dup 2) 1)))
565
566 (set (subreg:SI (match_dup 0) 1)
567 (minus:SI (subreg:SI (match_dup 0) 1)
568 (match_dup 3)))]
569 "")
570
571(define_split
572 [(set (match_operand:DI 0 "register_operand" "")
573 (minus:DI (match_operand:DI 1 "register_operand" "")
574 (match_operand:DI 2 "register_operand" "")))
575 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 576 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 577 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
578 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
579 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
580
581 [(set (match_dup 3)
34b650b3 582 (ltu:SI (subreg:SI (match_dup 1) 1)
6d518002 583 (subreg:SI (match_dup 2) 1)))
8ef30996
MM		 584
585 (set (subreg:SI (match_dup 0) 1)
586 (minus:SI (subreg:SI (match_dup 1) 1)
587 (subreg:SI (match_dup 2) 1)))
588
589 (set (subreg:SI (match_dup 0) 0)
590 (minus:SI (subreg:SI (match_dup 1) 0)
591 (subreg:SI (match_dup 2) 0)))
592
593 (set (subreg:SI (match_dup 0) 0)
594 (minus:SI (subreg:SI (match_dup 0) 0)
595 (match_dup 3)))]
596 "")
597
598(define_insn "subdi3_internal_2"
599 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
600 (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
601 (match_operand:DI 2 "small_int" "P,J,N")))
602 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
603 "!TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
604 "@
605 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
606 move\\t%L0,%L1\;move\\t%M0,%M1
607 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
92b4cee1
MM		 608 [(set_attr "type" "darith")
609 (set_attr "mode" "DI")
8ef30996
MM		 610 (set_attr "length" "3,2,4")])
611
612(define_split
613 [(set (match_operand:DI 0 "register_operand" "")
614 (minus:DI (match_operand:DI 1 "register_operand" "")
615 (match_operand:DI 2 "small_int" "")))
616 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 617 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 618 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
619 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
620 && INTVAL (operands[2]) > 0"
621
622 [(set (match_dup 3)
34b650b3 623 (ltu:SI (subreg:SI (match_dup 1) 0)
8ef30996
MM		 624 (match_dup 2)))
625
626 (set (subreg:SI (match_dup 0) 0)
627 (minus:SI (subreg:SI (match_dup 1) 0)
628 (match_dup 2)))
629
630 (set (subreg:SI (match_dup 0) 1)
631 (minus:SI (subreg:SI (match_dup 1) 1)
632 (match_dup 3)))]
633 "")
634
635(define_split
636 [(set (match_operand:DI 0 "register_operand" "")
637 (minus:DI (match_operand:DI 1 "register_operand" "")
638 (match_operand:DI 2 "small_int" "")))
639 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 640 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 641 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
642 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
643 && INTVAL (operands[2]) > 0"
644
645 [(set (match_dup 3)
34b650b3 646 (ltu:SI (subreg:SI (match_dup 1) 1)
8ef30996
MM		 647 (match_dup 2)))
648
649 (set (subreg:SI (match_dup 0) 1)
650 (minus:SI (subreg:SI (match_dup 1) 1)
651 (match_dup 2)))
652
653 (set (subreg:SI (match_dup 0) 0)
654 (minus:SI (subreg:SI (match_dup 1) 0)
655 (match_dup 3)))]
656 "")
657
658\f
659;;
660;; ....................
661;;
662;; MULTIPLICATION
663;;
664;; ....................
665;;
666
667(define_insn "muldf3"
668 [(set (match_operand:DF 0 "register_operand" "=f")
669 (mult:DF (match_operand:DF 1 "register_operand" "f")
670 (match_operand:DF 2 "register_operand" "f")))]
671 "TARGET_HARD_FLOAT"
672 "mul.d\\t%0,%1,%2"
673 [(set_attr "type" "fmul")
674 (set_attr "mode" "DF")
675 (set_attr "length" "1")])
676
677(define_insn "mulsf3"
678 [(set (match_operand:SF 0 "register_operand" "=f")
679 (mult:SF (match_operand:SF 1 "register_operand" "f")
680 (match_operand:SF 2 "register_operand" "f")))]
681 "TARGET_HARD_FLOAT"
682 "mul.s\\t%0,%1,%2"
683 [(set_attr "type" "fmul")
684 (set_attr "mode" "SF")
685 (set_attr "length" "1")])
686
687(define_insn "mulsi3"
688 [(set (match_operand:SI 0 "register_operand" "=d")
689 (mult:SI (match_operand:SI 1 "register_operand" "d")
690 (match_operand:SI 2 "register_operand" "d")))
691 (clobber (reg:SI 64))
692 (clobber (reg:SI 65))]
693 ""
694 "*
695{
696 rtx xoperands[10];
697
698 xoperands[0] = operands[0];
699 xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM);
700
701 output_asm_insn (\"mult\\t%1,%2\", operands);
702 output_asm_insn (mips_move_1word (xoperands, insn), xoperands);
703 return \"\";
704}"
705 [(set_attr "type" "imul")
706 (set_attr "mode" "SI")
707 (set_attr "length" "3")]) ;; mult + mflo + delay
708
709(define_split
710 [(set (match_operand:SI 0 "register_operand" "")
711 (mult:SI (match_operand:SI 1 "register_operand" "")
712 (match_operand:SI 2 "register_operand" "")))
713 (clobber (reg:SI 64))
714 (clobber (reg:SI 65))]
26b8e6e5 715 "!TARGET_DEBUG_D_MODE"
8ef30996
MM		 716 [(parallel [(set (reg:SI 65) ;; low register
717 (mult:SI (match_dup 1)
718 (match_dup 2)))
719 (clobber (reg:SI 64))])
720 (set (match_dup 0)
721 (reg:SI 65))]
722 "")
723
724(define_insn "mulsi3_internal"
725 [(set (reg:SI 65) ;; low register
726 (mult:SI (match_operand:SI 0 "register_operand" "d")
727 (match_operand:SI 1 "register_operand" "d")))
728 (clobber (reg:SI 64))]
729 ""
730 "mult\\t%0,%1"
731 [(set_attr "type" "imul")
732 (set_attr "mode" "SI")
733 (set_attr "length" "1")])
734
735(define_insn "mulsidi3"
736 [(set (match_operand:DI 0 "register_operand" "=d")
737 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
738 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
739 (clobber (reg:DI 64))]
740 ""
741 "*
742{
743 rtx xoperands[10];
744
745 xoperands[0] = operands[0];
746 xoperands[1] = gen_rtx (REG, DImode, MD_REG_FIRST);
747
748 output_asm_insn (\"mult\\t%1,%2\", operands);
749 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
750 return \"\";
751}"
752 [(set_attr "type" "imul")
753 (set_attr "mode" "SI")
754 (set_attr "length" "4")]) ;; mult + mflo + mfhi + delay
755
756(define_insn "umulsidi3"
757 [(set (match_operand:DI 0 "register_operand" "=d")
758 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
759 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))
760 (clobber (reg:DI 64))]
761 ""
762 "*
763{
764 rtx xoperands[10];
765
766 xoperands[0] = operands[0];
767 xoperands[1] = gen_rtx (REG, DImode, MD_REG_FIRST);
768
769 output_asm_insn (\"multu\\t%1,%2\", operands);
770 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
771 return \"\";
772}"
773 [(set_attr "type" "imul")
774 (set_attr "mode" "SI")
775 (set_attr "length" "4")]) ;; mult + mflo + mfhi + delay
776
777\f
778;;
779;; ....................
780;;
781;; DIVISION and REMAINDER
782;;
783;; ....................
784;;
785
786(define_insn "divdf3"
787 [(set (match_operand:DF 0 "register_operand" "=f")
788 (div:DF (match_operand:DF 1 "register_operand" "f")
789 (match_operand:DF 2 "register_operand" "f")))]
790 "TARGET_HARD_FLOAT"
791 "div.d\\t%0,%1,%2"
792 [(set_attr "type" "fdiv")
793 (set_attr "mode" "DF")
794 (set_attr "length" "1")])
795
796(define_insn "divsf3"
797 [(set (match_operand:SF 0 "register_operand" "=f")
798 (div:SF (match_operand:SF 1 "register_operand" "f")
799 (match_operand:SF 2 "register_operand" "f")))]
800 "TARGET_HARD_FLOAT"
801 "div.s\\t%0,%1,%2"
802 [(set_attr "type" "fdiv")
803 (set_attr "mode" "SF")
804 (set_attr "length" "1")])
805
806;; If optimizing, prefer the divmod functions over separate div and
807;; mod functions, since this will allow using one instruction for both
808;; the quotient and remainder. At present, the divmod is not moved out
809;; of loops if it is constant within the loop, so allow -mdebugc to
810;; use the old method of doing things.
811
812;; 64 is the multiply/divide hi register
813;; 65 is the multiply/divide lo register
814
815(define_insn "divmodsi4"
70252580
MM		 816 [(set (match_operand:SI 0 "register_operand" "=d")
817 (div:SI (match_operand:SI 1 "register_operand" "d")
818 (match_operand:SI 2 "register_operand" "d")))
819 (set (match_operand:SI 3 "register_operand" "=d")
820 (mod:SI (match_dup 1)
821 (match_dup 2)))
822 (clobber (reg:SI 64))
823 (clobber (reg:SI 65))]
34b650b3 824 "optimize"
8ef30996
MM		 825 "*
826{
827 if (find_reg_note (insn, REG_UNUSED, operands[3]))
828 return \"div\\t%0,%1,%2\";
829
830 if (find_reg_note (insn, REG_UNUSED, operands[0]))
831 return \"rem\\t%3,%1,%2\";
832
833 return \"div\\t%0,%1,%2\;mfhi\\t%3\";
834}"
835 [(set_attr "type" "idiv")
836 (set_attr "mode" "SI")
837 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
838
839(define_insn "udivmodsi4"
70252580
MM		 840 [(set (match_operand:SI 0 "register_operand" "=d")
841 (udiv:SI (match_operand:SI 1 "register_operand" "d")
842 (match_operand:SI 2 "register_operand" "d")))
843 (set (match_operand:SI 3 "register_operand" "=d")
844 (umod:SI (match_dup 1)
845 (match_dup 2)))
846 (clobber (reg:SI 64))
847 (clobber (reg:SI 65))]
34b650b3 848 "optimize"
8ef30996
MM		 849 "*
850{
851 if (find_reg_note (insn, REG_UNUSED, operands[3]))
852 return \"divu\\t%0,%1,%2\";
853
854 if (find_reg_note (insn, REG_UNUSED, operands[0]))
855 return \"remu\\t%3,%1,%2\";
856
857 return \"divu\\t%0,%1,%2\;mfhi\\t%3\";
858}"
859 [(set_attr "type" "idiv")
860 (set_attr "mode" "SI")
861 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
862
863(define_insn "divsi3"
864 [(set (match_operand:SI 0 "register_operand" "=d")
865 (div:SI (match_operand:SI 1 "register_operand" "d")
866 (match_operand:SI 2 "register_operand" "d")))
867 (clobber (reg:SI 64))
868 (clobber (reg:SI 65))]
34b650b3 869 "!optimize"
8ef30996
MM		 870 "div\\t%0,%1,%2"
871 [(set_attr "type" "idiv")
872 (set_attr "mode" "SI")
873 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
874
875(define_insn "modsi3"
876 [(set (match_operand:SI 0 "register_operand" "=d")
877 (mod:SI (match_operand:SI 1 "register_operand" "d")
878 (match_operand:SI 2 "register_operand" "d")))
879 (clobber (reg:SI 64))
880 (clobber (reg:SI 65))]
34b650b3 881 "!optimize"
8ef30996
MM		 882 "rem\\t%0,%1,%2"
883 [(set_attr "type" "idiv")
884 (set_attr "mode" "SI")
885 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
886
887(define_insn "udivsi3"
888 [(set (match_operand:SI 0 "register_operand" "=d")
889 (udiv:SI (match_operand:SI 1 "register_operand" "d")
890 (match_operand:SI 2 "register_operand" "d")))
891 (clobber (reg:SI 64))
892 (clobber (reg:SI 65))]
34b650b3 893 "!optimize"
8ef30996
MM		 894 "divu\\t%0,%1,%2"
895 [(set_attr "type" "idiv")
896 (set_attr "mode" "SI")
897 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
898
899(define_insn "umodsi3"
900 [(set (match_operand:SI 0 "register_operand" "=d")
901 (umod:SI (match_operand:SI 1 "register_operand" "d")
902 (match_operand:SI 2 "register_operand" "d")))
903 (clobber (reg:SI 64))
904 (clobber (reg:SI 65))]
34b650b3 905 "!optimize"
8ef30996
MM		 906 "remu\\t%0,%1,%2"
907 [(set_attr "type" "idiv")
908 (set_attr "mode" "SI")
909 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
910
911\f
912;;
913;; ....................
914;;
915;; SQUARE ROOT
916;;
917;; ....................
918
919(define_insn "sqrtdf2"
920 [(set (match_operand:DF 0 "register_operand" "=f")
921 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
922 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
923 "sqrt.d\\t%0,%1"
924 [(set_attr "type" "fabs")
925 (set_attr "mode" "DF")
926 (set_attr "length" "1")])
927
928(define_insn "sqrtsf2"
929 [(set (match_operand:SF 0 "register_operand" "=f")
930 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
931 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
932 "sqrt.s\\t%0,%1"
933 [(set_attr "type" "fabs")
934 (set_attr "mode" "SF")
935 (set_attr "length" "1")])
936
937\f
938;;
939;; ....................
940;;
941;; ABSOLUTE VALUE
942;;
943;; ....................
944
945;; Do not use the integer abs macro instruction, since that signals an
946;; exception on -2147483648 (sigh).
947
948(define_insn "abssi2"
949 [(set (match_operand:SI 0 "register_operand" "=d")
950 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
951 ""
952 "*
953{
954 dslots_jump_total++;
955 dslots_jump_filled++;
956 operands[2] = const0_rtx;
957
958 return (REGNO (operands[0]) == REGNO (operands[1]))
959 ? \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n1:\"
960 : \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
961}"
962 [(set_attr "type" "multi")
963 (set_attr "mode" "SI")
964 (set_attr "length" "3")])
965
966(define_insn "absdf2"
967 [(set (match_operand:DF 0 "register_operand" "=f")
968 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
969 "TARGET_HARD_FLOAT"
970 "abs.d\\t%0,%1"
971 [(set_attr "type" "fabs")
972 (set_attr "mode" "DF")
973 (set_attr "length" "1")])
974
975(define_insn "abssf2"
976 [(set (match_operand:SF 0 "register_operand" "=f")
977 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
978 "TARGET_HARD_FLOAT"
979 "abs.s\\t%0,%1"
980 [(set_attr "type" "fabs")
981 (set_attr "mode" "SF")
982 (set_attr "length" "1")])
983
984\f
985;;
986;; ....................
987;;
988;; FIND FIRST BIT INSTRUCTION
989;;
990;; ....................
991;;
992
993(define_insn "ffssi2"
994 [(set (match_operand:SI 0 "register_operand" "=&d")
995 (ffs:SI (match_operand:SI 1 "register_operand" "d")))
996 (clobber (match_scratch:SI 2 "d"))
997 (clobber (match_scratch:SI 3 "d"))]
998 ""
999 "*
1000{
1001 dslots_jump_total += 2;
1002 dslots_jump_filled += 2;
1003 operands[4] = const0_rtx;
1004
1005 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
1006 return \"%(\\
1007move\\t%0,%z4\\n\\
1008\\tbeq\\t%1,%z4,2f\\n\\
10091:\\tand\\t%2,%1,0x0001\\n\\
1010\\taddu\\t%0,%0,1\\n\\
1011\\tbeq\\t%2,%z4,1b\\n\\
1012\\tsrl\\t%1,%1,1\\n\\
10132:%)\";
1014
1015 return \"%(\\
1016move\\t%0,%z4\\n\\
1017\\tmove\\t%3,%1\\n\\
1018\\tbeq\\t%3,%z4,2f\\n\\
10191:\\tand\\t%2,%3,0x0001\\n\\
1020\\taddu\\t%0,%0,1\\n\\
1021\\tbeq\\t%2,%z4,1b\\n\\
1022\\tsrl\\t%3,%3,1\\n\\
10232:%)\";
1024}"
1025 [(set_attr "type" "multi")
1026 (set_attr "mode" "SI")
1027 (set_attr "length" "6")])
1028
1029\f
1030;;
1031;; ....................
1032;;
1033;; NEGATION and ONE'S COMPLEMENT
1034;;
1035;; ....................
1036
1037(define_insn "negsi2"
1038 [(set (match_operand:SI 0 "register_operand" "=d")
1039 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1040 ""
1041 "*
1042{
1043 operands[2] = const0_rtx;
1044 return \"subu\\t%0,%z2,%1\";
1045}"
1046 [(set_attr "type" "arith")
1047 (set_attr "mode" "SI")
1048 (set_attr "length" "1")])
1049
1050(define_expand "negdi3"
1051 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
1052 (neg:DI (match_operand:DI 1 "register_operand" "d")))
1053 (clobber (match_dup 2))])]
1054 "!TARGET_DEBUG_G_MODE"
1055 "operands[2] = gen_reg_rtx (SImode);")
1056
1057(define_insn "negdi3_internal"
1058 [(set (match_operand:DI 0 "register_operand" "=d")
1059 (neg:DI (match_operand:DI 1 "register_operand" "d")))
1060 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1061 "!TARGET_DEBUG_G_MODE"
1062 "*
1063{
1064 operands[3] = const0_rtx;
1065 return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
1066}"
1067 [(set_attr "type" "darith")
1068 (set_attr "mode" "DI")
1069 (set_attr "length" "4")])
1070
1071(define_insn "negdf2"
1072 [(set (match_operand:DF 0 "register_operand" "=f")
1073 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
1074 "TARGET_HARD_FLOAT"
1075 "neg.d\\t%0,%1"
1076 [(set_attr "type" "fneg")
1077 (set_attr "mode" "DF")
1078 (set_attr "length" "1")])
1079
1080(define_insn "negsf2"
1081 [(set (match_operand:SF 0 "register_operand" "=f")
1082 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
1083 "TARGET_HARD_FLOAT"
1084 "neg.s\\t%0,%1"
1085 [(set_attr "type" "fneg")
1086 (set_attr "mode" "SF")
1087 (set_attr "length" "1")])
1088
1089(define_insn "one_cmplsi2"
1090 [(set (match_operand:SI 0 "register_operand" "=d")
1091 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1092 ""
1093 "*
1094{
1095 operands[2] = const0_rtx;
1096 return \"nor\\t%0,%z2,%1\";
1097}"
1098 [(set_attr "type" "arith")
1099 (set_attr "mode" "SI")
1100 (set_attr "length" "1")])
1101
1102(define_insn "one_cmpldi2"
1103 [(set (match_operand:DI 0 "register_operand" "=d")
1104 (not:SI (match_operand:DI 1 "register_operand" "d")))]
1105 ""
1106 "*
1107{
1108 operands[2] = const0_rtx;
1109 return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
1110}"
1111 [(set_attr "type" "darith")
1112 (set_attr "mode" "DI")
1113 (set_attr "length" "2")])
1114
1115(define_split
1116 [(set (match_operand:DI 0 "register_operand" "")
1117 (not:DI (match_operand:DI 1 "register_operand" "")))]
26b8e6e5 1118 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1119 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1120 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
1121
1122 [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
1123 (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))]
1124 "")
1125
1126;; Simple hack to recognize the "nor" instruction on the MIPS
1127;; This must appear before the normal or patterns, so that the
1128;; combiner will correctly fold things.
1129
1130(define_insn "norsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=d")
1132 (not:SI (ior:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1133 (match_operand:SI 2 "reg_or_0_operand" "dJ"))))]
1134 ""
1135 "nor\\t%0,%z1,%z2"
1136 [(set_attr "type" "arith")
1137 (set_attr "mode" "SI")
1138 (set_attr "length" "1")])
1139
1140(define_insn "nordi3"
1141 [(set (match_operand:DI 0 "register_operand" "=d")
1142 (not:DI (ior:DI (match_operand:DI 1 "register_operand" "d")
1143 (match_operand:DI 2 "register_operand" "d"))))]
1144 ""
1145 "nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2"
1146 [(set_attr "type" "darith")
1147 (set_attr "mode" "DI")
1148 (set_attr "length" "2")])
1149
1150(define_split
1151 [(set (match_operand:DI 0 "register_operand" "")
1152 (not:DI (ior:DI (match_operand:DI 1 "register_operand" "")
1153 (match_operand:DI 2 "register_operand" ""))))]
26b8e6e5 1154 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1155 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1156 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1157 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1158
1159 [(set (subreg:SI (match_dup 0) 0) (not:SI (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))))
1160 (set (subreg:SI (match_dup 0) 1) (not:SI (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1))))]
1161 "")
1162
1163\f
1164;;
1165;; ....................
1166;;
1167;; LOGICAL
1168;;
1169;; ....................
1170;;
1171
3e89ed5f 1172(define_insn "andsi3"
65437fe8 1173 [(set (match_operand:SI 0 "register_operand" "=d,d")
e2f2127c
MM		 1174 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
1175 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
65437fe8
MM		 1176 ""
1177 "@
1178 and\\t%0,%1,%2
1179 andi\\t%0,%1,%x2"
1180 [(set_attr "type" "arith")
1181 (set_attr "mode" "SI")
1182 (set_attr "length" "1")])
1183
8ef30996
MM		 1184(define_insn "anddi3"
1185 [(set (match_operand:DI 0 "register_operand" "=d")
1186 (and:DI (match_operand:DI 1 "register_operand" "d")
1187 (match_operand:DI 2 "register_operand" "d")))]
1188 "!TARGET_DEBUG_G_MODE"
1189 "and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2"
1190 [(set_attr "type" "darith")
1191 (set_attr "mode" "DI")
1192 (set_attr "length" "2")])
1193
1194(define_split
1195 [(set (match_operand:DI 0 "register_operand" "")
1196 (and:DI (match_operand:DI 1 "register_operand" "")
1197 (match_operand:DI 2 "register_operand" "")))]
26b8e6e5 1198 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1199 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1200 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1201 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1202
1203 [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1204 (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1205 "")
1206
3e89ed5f 1207(define_insn "iorsi3"
65437fe8 1208 [(set (match_operand:SI 0 "register_operand" "=d,d")
e2f2127c
MM		 1209 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
1210 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
65437fe8
MM		 1211 ""
1212 "@
1213 or\\t%0,%1,%2
1214 ori\\t%0,%1,%x2"
1215 [(set_attr "type" "arith")
1216 (set_attr "mode" "SI")
1217 (set_attr "length" "1")])
1218
8ef30996
MM		 1219(define_insn "iordi3"
1220 [(set (match_operand:DI 0 "register_operand" "=d")
1221 (ior:DI (match_operand:DI 1 "register_operand" "d")
1222 (match_operand:DI 2 "register_operand" "d")))]
1223 "!TARGET_DEBUG_G_MODE"
1224 "or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2"
1225 [(set_attr "type" "darith")
1226 (set_attr "mode" "DI")
1227 (set_attr "length" "2")])
1228
1229(define_split
1230 [(set (match_operand:DI 0 "register_operand" "")
1231 (ior:DI (match_operand:DI 1 "register_operand" "")
1232 (match_operand:DI 2 "register_operand" "")))]
26b8e6e5 1233 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1234 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1235 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1236 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1237
1238 [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1239 (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1240 "")
1241
3e89ed5f 1242(define_insn "xorsi3"
65437fe8 1243 [(set (match_operand:SI 0 "register_operand" "=d,d")
e2f2127c
MM		 1244 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
1245 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
65437fe8
MM		 1246 ""
1247 "@
1248 xor\\t%0,%1,%2
1249 xori\\t%0,%1,%x2"
1250 [(set_attr "type" "arith")
1251 (set_attr "mode" "SI")
1252 (set_attr "length" "1")])
1253
8ef30996
MM		 1254(define_insn "xordi3"
1255 [(set (match_operand:DI 0 "register_operand" "=d")
1256 (xor:DI (match_operand:DI 1 "register_operand" "d")
1257 (match_operand:DI 2 "register_operand" "d")))]
1258 "!TARGET_DEBUG_G_MODE"
1259 "xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2"
1260 [(set_attr "type" "darith")
1261 (set_attr "mode" "DI")
1262 (set_attr "length" "2")])
1263
1264(define_split
1265 [(set (match_operand:DI 0 "register_operand" "")
1266 (xor:DI (match_operand:DI 1 "register_operand" "")
1267 (match_operand:DI 2 "register_operand" "")))]
26b8e6e5 1268 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1269 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1270 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1271 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1272
1273 [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1274 (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1275 "")
1276
1277\f
1278;;
1279;; ....................
1280;;
1281;; TRUNCATION
1282;;
1283;; ....................
1284
1285(define_insn "truncdfsf2"
1286 [(set (match_operand:SF 0 "register_operand" "=f")
1287 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
1288 "TARGET_HARD_FLOAT"
1289 "cvt.s.d\\t%0,%1"
1290 [(set_attr "type" "fcvt")
1291 (set_attr "mode" "SF")
1292 (set_attr "length" "1")])
1293
1294\f
1295;;
1296;; ....................
1297;;
1298;; ZERO EXTENSION
1299;;
1300;; ....................
1301
1302;; Extension insns.
1303;; Those for integer source operand
1304;; are ordered widest source type first.
1305
1306(define_insn "zero_extendhisi2"
1307 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
1308 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
1309 ""
1310 "*
1311{
1312 if (which_alternative == 0)
1313 return \"andi\\t%0,%1,0xffff\";
1314 else
1315 return mips_move_1word (operands, insn, TRUE);
1316}"
1317 [(set_attr "type" "arith,load,load")
92b4cee1 1318 (set_attr "mode" "SI")
8ef30996
MM		 1319 (set_attr "length" "1,1,2")])
1320
1321(define_insn "zero_extendqihi2"
1322 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
1323 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
1324 ""
1325 "*
1326{
1327 if (which_alternative == 0)
1328 return \"andi\\t%0,%1,0x00ff\";
1329 else
1330 return mips_move_1word (operands, insn, TRUE);
1331}"
1332 [(set_attr "type" "arith,load,load")
92b4cee1 1333 (set_attr "mode" "HI")
8ef30996
MM		 1334 (set_attr "length" "1,1,2")])
1335
1336(define_insn "zero_extendqisi2"
1337 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
1338 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
1339 ""
1340 "*
1341{
1342 if (which_alternative == 0)
1343 return \"andi\\t%0,%1,0x00ff\";
1344 else
1345 return mips_move_1word (operands, insn, TRUE);
1346}"
1347 [(set_attr "type" "arith,load,load")
92b4cee1 1348 (set_attr "mode" "SI")
8ef30996
MM		 1349 (set_attr "length" "1,1,2")])
1350
1351\f
1352;;
1353;; ....................
1354;;
1355;; SIGN EXTENSION
1356;;
1357;; ....................
1358
1359;; Extension insns.
1360;; Those for integer source operand
1361;; are ordered widest source type first.
1362
1363;; These patterns originally accepted general_operands, however, slightly
1364;; better code is generated by only accepting register_operands, and then
1365;; letting combine generate the lh and lb insns.
1366
1367(define_expand "extendhisi2"
1368 [(set (match_operand:SI 0 "register_operand" "")
1369 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1370 ""
1371 "
1372{
1373 if (optimize && GET_CODE (operands[1]) == MEM)
1374 operands[1] = force_not_mem (operands[1]);
1375
1376 if (GET_CODE (operands[1]) != MEM)
1377 {
1378 rtx op1 = gen_lowpart (SImode, operands[1]);
1379 rtx temp = gen_reg_rtx (SImode);
1380 rtx shift = gen_rtx (CONST_INT, VOIDmode, 16);
1381
1382 emit_insn (gen_ashlsi3 (temp, op1, shift));
1383 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
1384 DONE;
1385 }
1386}")
1387
1388(define_insn "extendhisi2_internal"
1389 [(set (match_operand:SI 0 "register_operand" "=d,d")
1390 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
1391 ""
1392 "* return mips_move_1word (operands, insn, FALSE);"
92b4cee1
MM		 1393 [(set_attr "type" "load")
1394 (set_attr "mode" "SI")
8ef30996
MM		 1395 (set_attr "length" "1,2")])
1396
1397(define_expand "extendqihi2"
1398 [(set (match_operand:HI 0 "register_operand" "")
1399 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1400 ""
1401 "
1402{
1403 if (optimize && GET_CODE (operands[1]) == MEM)
1404 operands[1] = force_not_mem (operands[1]);
1405
1406 if (GET_CODE (operands[1]) != MEM)
1407 {
1408 rtx op0 = gen_lowpart (SImode, operands[0]);
1409 rtx op1 = gen_lowpart (SImode, operands[1]);
1410 rtx temp = gen_reg_rtx (SImode);
1411 rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
1412
1413 emit_insn (gen_ashlsi3 (temp, op1, shift));
1414 emit_insn (gen_ashrsi3 (op0, temp, shift));
1415 DONE;
1416 }
1417}")
1418
1419(define_insn "extendqihi2_internal"
1420 [(set (match_operand:HI 0 "register_operand" "=d,d")
1421 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
1422 ""
1423 "* return mips_move_1word (operands, insn, FALSE);"
92b4cee1
MM		 1424 [(set_attr "type" "load")
1425 (set_attr "mode" "SI")
8ef30996
MM		 1426 (set_attr "length" "1,2")])
1427
1428
1429(define_expand "extendqisi2"
1430 [(set (match_operand:SI 0 "register_operand" "")
1431 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1432 ""
1433 "
1434{
1435 if (optimize && GET_CODE (operands[1]) == MEM)
1436 operands[1] = force_not_mem (operands[1]);
1437
1438 if (GET_CODE (operands[1]) != MEM)
1439 {
1440 rtx op1 = gen_lowpart (SImode, operands[1]);
1441 rtx temp = gen_reg_rtx (SImode);
1442 rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
1443
1444 emit_insn (gen_ashlsi3 (temp, op1, shift));
1445 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
1446 DONE;
1447 }
1448}")
1449
1450(define_insn "extendqisi2_insn"
1451 [(set (match_operand:SI 0 "register_operand" "=d,d")
1452 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
1453 ""
1454 "* return mips_move_1word (operands, insn, FALSE);"
92b4cee1
MM		 1455 [(set_attr "type" "load")
1456 (set_attr "mode" "SI")
8ef30996
MM		 1457 (set_attr "length" "1,2")])
1458
1459
1460(define_insn "extendsfdf2"
1461 [(set (match_operand:DF 0 "register_operand" "=f")
1462 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
1463 "TARGET_HARD_FLOAT"
1464 "cvt.d.s\\t%0,%1"
1465 [(set_attr "type" "fcvt")
1466 (set_attr "mode" "DF")
1467 (set_attr "length" "1")])
1468
1469\f
1470
1471;;
1472;; ....................
1473;;
1474;; CONVERSIONS
1475;;
1476;; ....................
1477
c7343333 1478(define_insn "fix_truncdfsi2"
8ef30996
MM		 1479 [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
1480 (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
c7343333
MM		 1481 (clobber (match_scratch:SI 2 "=d,*d,d,d"))
1482 (clobber (match_scratch:DF 3 "=f,*X,f,f"))]
8ef30996
MM		 1483 "TARGET_HARD_FLOAT"
1484 "*
1485{
1486 rtx xoperands[10];
1487
1488 if (which_alternative == 1)
1489 return \"trunc.w.d %0,%1,%2\";
1490
1491 output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
1492
1493 xoperands[0] = operands[0];
1494 xoperands[1] = operands[3];
1495 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1496 return \"\";
1497}"
92b4cee1
MM		 1498 [(set_attr "type" "fcvt")
1499 (set_attr "mode" "DF")
c7343333 1500 (set_attr "length" "11,9,10,11")])
8ef30996
MM		 1501
1502
c7343333 1503(define_insn "fix_truncsfsi2"
8ef30996
MM		 1504 [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
1505 (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
c7343333
MM		 1506 (clobber (match_scratch:SI 2 "=d,*d,d,d"))
1507 (clobber (match_scratch:SF 3 "=f,*X,f,f"))]
8ef30996
MM		 1508 "TARGET_HARD_FLOAT"
1509 "*
1510{
1511 rtx xoperands[10];
1512
1513 if (which_alternative == 1)
1514 return \"trunc.w.s %0,%1,%2\";
1515
1516 output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
1517
1518 xoperands[0] = operands[0];
1519 xoperands[1] = operands[3];
1520 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1521 return \"\";
1522}"
92b4cee1
MM		 1523 [(set_attr "type" "fcvt")
1524 (set_attr "mode" "SF")
c7343333 1525 (set_attr "length" "11,9,10,11")])
8ef30996
MM		 1526
1527
1528(define_insn "floatsidf2"
bbdb5552
MM		 1529 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
1530 (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
8ef30996 1531 "TARGET_HARD_FLOAT"
bbdb5552
MM		 1532 "*
1533{
1534 dslots_load_total++;
1535 if (GET_CODE (operands[1]) == MEM)
5cccf78f 1536 return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
bbdb5552
MM		 1537
1538 return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
1539}"
92b4cee1
MM		 1540 [(set_attr "type" "fcvt")
1541 (set_attr "mode" "DF")
bbdb5552 1542 (set_attr "length" "3,4,3")])
8ef30996 1543
c7343333 1544
8ef30996 1545(define_insn "floatsisf2"
bbdb5552
MM		 1546 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
1547 (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
8ef30996 1548 "TARGET_HARD_FLOAT"
bbdb5552
MM		 1549 "*
1550{
1551 dslots_load_total++;
1552 if (GET_CODE (operands[1]) == MEM)
5cccf78f 1553 return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
bbdb5552
MM		 1554
1555 return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
1556}"
92b4cee1
MM		 1557 [(set_attr "type" "fcvt")
1558 (set_attr "mode" "SF")
bbdb5552
MM		 1559 (set_attr "length" "3,4,3")])
1560
8ef30996
MM		 1561
1562(define_expand "fixuns_truncdfsi2"
1563 [(set (match_operand:SI 0 "register_operand" "")
1564 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
1565 "TARGET_HARD_FLOAT"
1566 "
1567{
1568 rtx reg1 = gen_reg_rtx (DFmode);
1569 rtx reg2 = gen_reg_rtx (DFmode);
1570 rtx reg3 = gen_reg_rtx (SImode);
1571 rtx label1 = gen_label_rtx ();
1572 rtx label2 = gen_label_rtx ();
1573 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
1574
1575 if (reg1) /* turn off complaints about unreached code */
1576 {
8ef30996
MM		 1577 emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
1578 do_pending_stack_adjust ();
1579
1580 emit_insn (gen_cmpdf (operands[1], reg1));
1581 emit_jump_insn (gen_bge (label1));
1582
1583 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
1584 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
1585 gen_rtx (LABEL_REF, VOIDmode, label2)));
1586 emit_barrier ();
1587
1588 emit_label (label1);
1589 emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
1590 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
1591
1592 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
1593 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
1594
1595 emit_label (label2);
1596
1597 /* allow REG_NOTES to be set on last insn (labels don't have enough
1598 fields, and can't be used for REG_NOTES anyway). */
1599 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
1600 DONE;
1601 }
1602}")
1603
c7343333 1604
8ef30996
MM		 1605(define_expand "fixuns_truncsfsi2"
1606 [(set (match_operand:SI 0 "register_operand" "")
1607 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
1608 "TARGET_HARD_FLOAT"
1609 "
1610{
1611 rtx reg1 = gen_reg_rtx (SFmode);
1612 rtx reg2 = gen_reg_rtx (SFmode);
1613 rtx reg3 = gen_reg_rtx (SImode);
1614 rtx label1 = gen_label_rtx ();
1615 rtx label2 = gen_label_rtx ();
1616 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
1617
1618 if (reg1) /* turn off complaints about unreached code */
1619 {
8ef30996
MM		 1620 emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
1621 do_pending_stack_adjust ();
1622
1623 emit_insn (gen_cmpsf (operands[1], reg1));
1624 emit_jump_insn (gen_bge (label1));
1625
1626 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
1627 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
1628 gen_rtx (LABEL_REF, VOIDmode, label2)));
1629 emit_barrier ();
1630
1631 emit_label (label1);
1632 emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
1633 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
1634
1635 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
1636 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
1637
1638 emit_label (label2);
1639
1640 /* allow REG_NOTES to be set on last insn (labels don't have enough
1641 fields, and can't be used for REG_NOTES anyway). */
1642 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
1643 DONE;
1644 }
1645}")
1646
1647\f
1648;;
1649;; ....................
1650;;
1651;; DATA MOVEMENT
1652;;
1653;; ....................
1654
1655;; unaligned word moves generated by the block moves.
8ef30996
MM		 1656
1657(define_expand "movsi_unaligned"
6d518002
MM		 1658 [(set (match_operand:SI 0 "general_operand" "")
1659 (unspec [(match_operand:SI 1 "general_operand" "")] 0))]
8ef30996
MM		 1660 ""
1661 "
1662{
842eb20e
MM		 1663 /* Handle loads. */
1664 if (GET_CODE (operands[0]) == MEM)
8ef30996
MM		 1665 {
1666 rtx reg = gen_reg_rtx (SImode);
842eb20e
MM		 1667 rtx insn = emit_insn (gen_movsi_ulw (reg, operands[1]));
1668 rtx addr = XEXP (operands[0], 0);
1669 if (CONSTANT_P (addr))
1670 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUIV, addr, REG_NOTES (insn));
1671
1672 if (reg_or_0_operand (operands[1], SImode))
1673 DONE;
8ef30996 1674
8ef30996
MM		 1675 operands[1] = reg;
1676 }
1677
1678 /* Generate appropriate load, store. If not a load or store,
1679 do a normal movsi. */
1680 if (GET_CODE (operands[0]) != MEM && GET_CODE (operands[1]) != MEM)
1681 {
1682 emit_insn (gen_movsi (operands[0], operands[1]));
1683 DONE;
1684 }
1685
1686 /* Fall through and generate normal code. */
1687}")
1688
1689(define_insn "movsi_ulw"
1690 [(set (match_operand:SI 0 "register_operand" "=&d,&d,d,d")
6d518002 1691 (unspec [(match_operand:SI 1 "general_operand" "R,o,dIKL,M")] 0))]
8ef30996
MM		 1692 ""
1693 "*
1694{
8ef30996
MM		 1695 enum rtx_code code;
1696 char *ret;
6d518002 1697 rtx offset;
8ef30996
MM		 1698 rtx addr;
1699 rtx mem_addr;
1700
1701 if (which_alternative != 0)
1702 return mips_move_1word (operands, insn, FALSE);
1703
1704 if (TARGET_STATS)
1705 mips_count_memory_refs (operands[1], 2);
1706
1707 /* The stack/frame pointers are always aligned, so we can convert
1708 to the faster lw if we are referencing an aligned stack location. */
1709
6d518002 1710 offset = const0_rtx;
8ef30996
MM		 1711 addr = XEXP (operands[1], 0);
1712 mem_addr = eliminate_constant_term (addr, &offset);
1713
6d518002 1714 if ((INTVAL (offset) & (UNITS_PER_WORD-1)) == 0
8ef30996
MM		 1715 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
1716 ret = \"lw\\t%0,%1\";
1717
1718 else
1719 {
1720 ret = \"ulw\\t%0,%1\";
1721 if (TARGET_GAS)
1722 {
1723 enum rtx_code code = GET_CODE (addr);
1724
1725 if (code == CONST || code == SYMBOL_REF || code == LABEL_REF)
1726 {
1727 operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 1);
1728 ret = \"%[la\\t%2,%1\;ulw\\t%0,0(%2)%]\";
1729 }
1730 }
1731 }
1732
1733 return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
1734}"
1735 [(set_attr "type" "load,load,move,arith")
92b4cee1 1736 (set_attr "mode" "SI")
8ef30996
MM		 1737 (set_attr "length" "2,4,1,2")])
1738
1739(define_insn "movsi_usw"
1740 [(set (match_operand:SI 0 "memory_operand" "=R,o")
6d518002 1741 (unspec [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 0))]
8ef30996
MM		 1742 ""
1743 "*
1744{
6d518002 1745 rtx offset = const0_rtx;
8ef30996
MM		 1746 rtx addr = XEXP (operands[0], 0);
1747 rtx mem_addr = eliminate_constant_term (addr, &offset);
1748
1749 if (TARGET_STATS)
1750 mips_count_memory_refs (operands[0], 2);
1751
1752 /* The stack/frame pointers are always aligned, so we can convert
1753 to the faster sw if we are referencing an aligned stack location. */
1754
6d518002 1755 if ((INTVAL (offset) & (UNITS_PER_WORD-1)) == 0
8ef30996
MM		 1756 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
1757 return \"sw\\t%1,%0\";
1758
1759
1760 if (TARGET_GAS)
1761 {
1762 enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
1763
1764 if (code == CONST || code == SYMBOL_REF || code == LABEL_REF)
1765 {
1766 operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 1);
1767 return \"%[la\\t%2,%0\;usw\\t%z1,0(%2)%]\";
1768 }
1769 }
1770
1771 return \"usw\\t%z1,%0\";
1772}"
92b4cee1
MM		 1773 [(set_attr "type" "store")
1774 (set_attr "mode" "SI")
8ef30996
MM		 1775 (set_attr "length" "2,4")])
1776
ed50ab35 1777
8ef30996
MM		 1778;; 64-bit integer moves
1779
1780;; Unlike most other insns, the move insns can't be split with
1781;; different predicates, because register spilling and other parts of
1782;; the compiler, have memoized the insn number already.
1783
ed50ab35
MM		 1784(define_expand "movdi"
1785 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1786 (match_operand:DI 1 "general_operand" ""))]
1787 ""
1788 "
1789{
1790 if ((reload_in_progress | reload_completed) == 0
1791 && !register_operand (operands[0], DImode)
1792 && !register_operand (operands[1], DImode)
1793 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
1794 && operands[1] != CONST0_RTX (DImode))
1795 {
1796 rtx temp = force_reg (DImode, operands[1]);
1797 emit_move_insn (operands[0], temp);
1798 DONE;
1799 }
1800}")
1801
1802(define_insn "movdi_internal"
6d518002
MM		 1803 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*d,*x")
1804 (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,*x,*d"))]
ed50ab35
MM		 1805 "register_operand (operands[0], DImode)
1806 || register_operand (operands[1], DImode)
1807 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
1808 || operands[1] == CONST0_RTX (DImode)"
8ef30996 1809 "* return mips_move_2words (operands, insn); "
6d518002 1810 [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo")
92b4cee1 1811 (set_attr "mode" "DI")
6d518002 1812 (set_attr "length" "2,4,2,4,2,4,2,2")])
8ef30996
MM		 1813
1814(define_split
1815 [(set (match_operand:DI 0 "register_operand" "")
1816 (match_operand:DI 1 "register_operand" ""))]
26b8e6e5 1817 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1818 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1819 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
1820
1821 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
1822 (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
1823 "")
1824
1825
1826;; 32-bit Integer moves
1827
1828(define_split
1829 [(set (match_operand:SI 0 "register_operand" "")
1830 (match_operand:SI 1 "large_int" ""))]
26b8e6e5 1831 "!TARGET_DEBUG_D_MODE"
8ef30996
MM		 1832 [(set (match_dup 0)
1833 (match_dup 2))
1834 (set (match_dup 0)
1835 (ior:SI (match_dup 0)
1836 (match_dup 3)))]
1837 "
1838{
1839 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff0000);
1840 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0x0000ffff);
1841}")
1842
1843;; Unlike most other insns, the move insns can't be split with
1844;; different predicates, because register spilling and other parts of
1845;; the compiler, have memoized the insn number already.
1846
f3b39eba
MM		 1847(define_expand "movsi"
1848 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1849 (match_operand:SI 1 "general_operand" ""))]
1850 ""
ed50ab35
MM		 1851 "
1852{
1853 if ((reload_in_progress | reload_completed) == 0
1854 && !register_operand (operands[0], SImode)
1855 && !register_operand (operands[1], SImode)
1856 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
1857 {
1858 rtx temp = force_reg (SImode, operands[1]);
1859 emit_move_insn (operands[0], temp);
1860 DONE;
1861 }
1862}")
f3b39eba 1863
0fb5ac6f
MM		 1864;; The difference between these two is whether or not ints are allowed
1865;; in FP registers (off by default, use -mdebugh to enable).
1866
1867(define_insn "movsi_internal1"
252e25c6
MM		 1868 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*d")
1869 (match_operand:SI 1 "general_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,*d,*x"))]
ed50ab35
MM		 1870 "TARGET_DEBUG_H_MODE
1871 && (register_operand (operands[0], SImode)
1872 || register_operand (operands[1], SImode)
1873 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
8ef30996 1874 "* return mips_move_1word (operands, insn, TRUE);"
c7343333 1875 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo")
92b4cee1 1876 (set_attr "mode" "SI")
c7343333 1877 (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1")])
8ef30996 1878
0fb5ac6f
MM		 1879(define_insn "movsi_internal2"
1880 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*d,*x")
1881 (match_operand:SI 1 "general_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,*x,*d"))]
ed50ab35
MM		 1882 "!TARGET_DEBUG_H_MODE
1883 && (register_operand (operands[0], SImode)
1884 || register_operand (operands[1], SImode)
1885 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
0fb5ac6f 1886 "* return mips_move_1word (operands, insn, TRUE);"
c7343333 1887 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo")
0fb5ac6f 1888 (set_attr "mode" "SI")
c7343333 1889 (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1")])
0fb5ac6f
MM		 1890
1891
8ef30996
MM		 1892;; 16-bit Integer moves
1893
1894;; Unlike most other insns, the move insns can't be split with
1895;; different predicates, because register spilling and other parts of
1896;; the compiler, have memoized the insn number already.
1897;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
1898
0fb5ac6f
MM		 1899(define_expand "movhi"
1900 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1901 (match_operand:HI 1 "general_operand" ""))]
8ef30996 1902 ""
ed50ab35
MM		 1903 "
1904{
1905 if ((reload_in_progress | reload_completed) == 0
1906 && !register_operand (operands[0], HImode)
1907 && !register_operand (operands[1], HImode)
1908 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
1909 {
1910 rtx temp = force_reg (HImode, operands[1]);
1911 emit_move_insn (operands[0], temp);
1912 DONE;
1913 }
1914}")
0fb5ac6f
MM		 1915
1916;; The difference between these two is whether or not ints are allowed
1917;; in FP registers (off by default, use -mdebugh to enable).
1918
1919(define_insn "movhi_internal1"
252e25c6
MM		 1920 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
1921 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
ed50ab35
MM		 1922 "TARGET_DEBUG_H_MODE
1923 && (register_operand (operands[0], HImode)
1924 || register_operand (operands[1], HImode)
1925 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
8ef30996
MM		 1926 "* return mips_move_1word (operands, insn, TRUE);"
1927 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
92b4cee1 1928 (set_attr "mode" "HI")
8ef30996
MM		 1929 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
1930
0fb5ac6f
MM		 1931(define_insn "movhi_internal2"
1932 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
1933 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
ed50ab35
MM		 1934 "!TARGET_DEBUG_H_MODE
1935 && (register_operand (operands[0], HImode)
1936 || register_operand (operands[1], HImode)
1937 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
0fb5ac6f
MM		 1938 "* return mips_move_1word (operands, insn, TRUE);"
1939 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
1940 (set_attr "mode" "HI")
1941 (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
1942
1943
8ef30996
MM		 1944;; 8-bit Integer moves
1945
1946;; Unlike most other insns, the move insns can't be split with
1947;; different predicates, because register spilling and other parts of
1948;; the compiler, have memoized the insn number already.
1949;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
1950
0fb5ac6f
MM		 1951(define_expand "movqi"
1952 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1953 (match_operand:QI 1 "general_operand" ""))]
8ef30996 1954 ""
ed50ab35
MM		 1955 "
1956{
1957 if ((reload_in_progress | reload_completed) == 0
1958 && !register_operand (operands[0], QImode)
1959 && !register_operand (operands[1], QImode)
1960 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
1961 {
1962 rtx temp = force_reg (QImode, operands[1]);
1963 emit_move_insn (operands[0], temp);
1964 DONE;
1965 }
1966}")
0fb5ac6f
MM		 1967
1968;; The difference between these two is whether or not ints are allowed
1969;; in FP registers (off by default, use -mdebugh to enable).
1970
1971(define_insn "movqi_internal1"
252e25c6
MM		 1972 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
1973 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
ed50ab35
MM		 1974 "TARGET_DEBUG_H_MODE
1975 && (register_operand (operands[0], QImode)
1976 || register_operand (operands[1], QImode)
1977 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
8ef30996
MM		 1978 "* return mips_move_1word (operands, insn, TRUE);"
1979 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
92b4cee1 1980 (set_attr "mode" "QI")
8ef30996
MM		 1981 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
1982
0fb5ac6f
MM		 1983(define_insn "movqi_internal2"
1984 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
1985 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
ed50ab35
MM		 1986 "!TARGET_DEBUG_H_MODE
1987 && (register_operand (operands[0], QImode)
1988 || register_operand (operands[1], QImode)
1989 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
0fb5ac6f
MM		 1990 "* return mips_move_1word (operands, insn, TRUE);"
1991 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
1992 (set_attr "mode" "QI")
1993 (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
1994
8ef30996
MM		 1995
1996;; 32-bit floating point moves
1997
ed50ab35
MM		 1998(define_expand "movsf"
1999 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2000 (match_operand:SF 1 "general_operand" ""))]
2001 ""
2002 "
2003{
2004 if ((reload_in_progress | reload_completed) == 0
2005 && !register_operand (operands[0], SFmode)
2006 && !register_operand (operands[1], SFmode)
2007 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
2008 && operands[1] != CONST0_RTX (SFmode))
2009 {
2010 rtx temp = force_reg (SFmode, operands[1]);
2011 emit_move_insn (operands[0], temp);
2012 DONE;
2013 }
2014}")
2015
2016(define_insn "movsf_internal"
8ef30996 2017 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
252e25c6 2018 (match_operand:SF 1 "general_operand" "f,G,R,Em,fG,fG,*d,*f,*G*d,*R,*E*m,*d,*d"))]
ed50ab35
MM		 2019 "register_operand (operands[0], SFmode)
2020 || register_operand (operands[1], SFmode)
2021 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
2022 || operands[1] == CONST0_RTX (SFmode)"
8ef30996
MM		 2023 "* return mips_move_1word (operands, insn, FALSE);"
2024 [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
92b4cee1 2025 (set_attr "mode" "SF")
8ef30996
MM		 2026 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")])
2027
ed50ab35 2028
8ef30996
MM		 2029;; 64-bit floating point moves
2030
ed50ab35
MM		 2031(define_expand "movdf"
2032 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2033 (match_operand:DF 1 "general_operand" ""))]
2034 ""
2035 "
2036{
2037 if ((reload_in_progress | reload_completed) == 0
2038 && !register_operand (operands[0], DFmode)
2039 && !register_operand (operands[1], DFmode)
2040 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
2041 && operands[1] != CONST0_RTX (DFmode))
2042 {
2043 rtx temp = force_reg (DFmode, operands[1]);
2044 emit_move_insn (operands[0], temp);
2045 DONE;
2046 }
2047}")
2048
2049(define_insn "movdf_internal"
8ef30996 2050 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,o,f,*f,*d,*d,*d,*d,*R,*o")
252e25c6 2051 (match_operand:DF 1 "general_operand" "f,R,o,fG,fG,E,*d,*f,*d*G,*R,*o*E,*d,*d"))]
ed50ab35
MM		 2052 "register_operand (operands[0], DFmode)
2053 || register_operand (operands[1], DFmode)
2054 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
2055 || operands[1] == CONST0_RTX (DFmode)"
8ef30996
MM		 2056 "* return mips_move_2words (operands, insn); "
2057 [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
92b4cee1 2058 (set_attr "mode" "DF")
8ef30996
MM		 2059 (set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")])
2060
2061(define_split
2062 [(set (match_operand:DF 0 "register_operand" "")
2063 (match_operand:DF 1 "register_operand" ""))]
26b8e6e5 2064 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2065 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2066 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
2067
2068 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
2069 (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
2070 "")
2071
26b8e6e5 2072\f
8ef30996
MM		 2073;; Block moves, see mips.c for more details.
2074;; Argument 0 is the destination
2075;; Argument 1 is the source
2076;; Argument 2 is the length
2077;; Argument 3 is the alignment
2078
2079(define_expand "movstrsi"
2080 [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
2081 (mem:BLK (match_operand:BLK 1 "general_operand" "")))
2082 (use (match_operand:SI 2 "arith32_operand" ""))
2083 (use (match_operand:SI 3 "immediate_operand" ""))])]
2084 ""
2085 "
2086{
2087 if (operands[0]) /* avoid unused code messages */
2088 {
2089 expand_block_move (operands);
2090 DONE;
2091 }
2092}")
2093
842eb20e
MM		 2094;; Insn generated by block moves
2095
2096(define_insn "movstrsi_internal"
26b8e6e5
MM		 2097 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
2098 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
2099 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
2100 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
2101 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
2102 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
2103 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
2104 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
2105 (use (const_int 0))] ;; normal block move
2106 ""
2107 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
842eb20e
MM		 2108 [(set_attr "type" "multi")
2109 (set_attr "mode" "none")
2110 (set_attr "length" "20")])
2111
26b8e6e5
MM		 2112;; Split a block move into 2 parts, the first part is everything
2113;; except for the last move, and the second part is just the last
2114;; store, which is exactly 1 instruction (ie, not a usw), so it can
2115;; fill a delay slot. This also prevents a bug in delayed branches
2116;; from showing up, which reuses one of the registers in our clobbers.
2117
2118(define_split
2119 [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
2120 (mem:BLK (match_operand:SI 1 "register_operand" "")))
2121 (clobber (match_operand:SI 4 "register_operand" ""))
2122 (clobber (match_operand:SI 5 "register_operand" ""))
2123 (clobber (match_operand:SI 6 "register_operand" ""))
2124 (clobber (match_operand:SI 7 "register_operand" ""))
2125 (use (match_operand:SI 2 "small_int" ""))
2126 (use (match_operand:SI 3 "small_int" ""))
2127 (use (const_int 0))]
2128
2129 "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
2130
2131 ;; All but the last move
2132 [(parallel [(set (mem:BLK (match_dup 0))
2133 (mem:BLK (match_dup 1)))
2134 (clobber (match_dup 4))
2135 (clobber (match_dup 5))
2136 (clobber (match_dup 6))
2137 (clobber (match_dup 7))
2138 (use (match_dup 2))
2139 (use (match_dup 3))
2140 (use (const_int 1))])
2141
2142 ;; The last store, so it can fill a delay slot
2143 (parallel [(set (mem:BLK (match_dup 0))
2144 (mem:BLK (match_dup 1)))
2145 (clobber (match_dup 4))
2146 (clobber (match_dup 5))
2147 (clobber (match_dup 6))
2148 (clobber (match_dup 7))
2149 (use (match_dup 2))
2150 (use (match_dup 3))
2151 (use (const_int 2))])]
2152
2153 "")
2154
2155(define_insn "movstrsi_internal2"
2156 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
2157 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
2158 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
2159 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
2160 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
2161 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
2162 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
2163 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
2164 (use (const_int 1))] ;; all but last store
2165 ""
2166 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
2167 [(set_attr "type" "multi")
2168 (set_attr "mode" "none")
2169 (set_attr "length" "20")])
2170
2171(define_insn "movstrsi_internal3"
2172 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
2173 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
2174 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
2175 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
2176 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
2177 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
2178 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
2179 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
2180 (use (const_int 2))] ;; just last store of block mvoe
2181 ""
2182 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
2183 [(set_attr "type" "store")
2184 (set_attr "mode" "none")
2185 (set_attr "length" "1")])
2186
8ef30996
MM		 2187\f
2188;;
2189;; ....................
2190;;
2191;; SHIFTS
2192;;
2193;; ....................
2194
2195(define_insn "ashlsi3"
2196 [(set (match_operand:SI 0 "register_operand" "=d")
2197 (ashift:SI (match_operand:SI 1 "register_operand" "d")
2198 (match_operand:SI 2 "arith_operand" "dI")))]
2199 ""
2200 "*
2201{
2202 if (GET_CODE (operands[2]) == CONST_INT)
2203 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2204
2205 return \"sll\\t%0,%1,%2\";
2206}"
2207 [(set_attr "type" "arith")
2208 (set_attr "mode" "SI")
2209 (set_attr "length" "1")])
2210
2211
2212(define_expand "ashldi3"
2213 [(parallel [(set (match_operand:DI 0 "register_operand" "")
2214 (ashift:DI (match_operand:DI 1 "register_operand" "")
2215 (match_operand:SI 2 "arith_operand" "")))
2216 (clobber (match_dup 3))])]
2217 "!TARGET_DEBUG_G_MODE"
2218 "operands[3] = gen_reg_rtx (SImode);")
2219
2220
2221(define_insn "ashldi3_internal"
0fb5ac6f 2222 [(set (match_operand:DI 0 "register_operand" "=&d")
8ef30996
MM		 2223 (ashift:DI (match_operand:DI 1 "register_operand" "d")
2224 (match_operand:SI 2 "register_operand" "d")))
2225 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2226 "!TARGET_DEBUG_G_MODE"
2227 "*
2228{
2229 operands[4] = const0_rtx;
2230 dslots_jump_total += 3;
2231 dslots_jump_filled += 2;
2232
2233 return \"sll\\t%3,%2,26\\n\\
2234\\tbgez\\t%3,1f\\n\\
2235\\tsll\\t%M0,%L1,%2\\n\\
2236\\t%(b\\t3f\\n\\
2237\\tmove\\t%L0,%z4%)\\n\\
2238\\n\\
22391:\\n\\
2240\\t%(beq\\t%3,%z4,2f\\n\\
2241\\tsll\\t%M0,%M1,%2%)\\n\\
2242\\n\\
2243\\tsubu\\t%3,%z4,%2\\n\\
2244\\tsrl\\t%3,%L1,%3\\n\\
2245\\tor\\t%M0,%M0,%3\\n\\
22462:\\n\\
2247\\tsll\\t%L0,%L1,%2\\n\\
22483:\";
2249}"
2250 [(set_attr "type" "darith")
2251 (set_attr "mode" "SI")
2252 (set_attr "length" "12")])
2253
2254
2255(define_insn "ashldi3_internal2"
2256 [(set (match_operand:DI 0 "register_operand" "=d")
2257 (ashift:DI (match_operand:DI 1 "register_operand" "d")
2258 (match_operand:SI 2 "small_int" "IJK")))
2259 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2260 "!TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
2261 "*
2262{
2263 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2264 operands[4] = const0_rtx;
2265 return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
2266}"
2267 [(set_attr "type" "darith")
2268 (set_attr "mode" "DI")
2269 (set_attr "length" "2")])
2270
2271
2272(define_split
2273 [(set (match_operand:DI 0 "register_operand" "")
2274 (ashift:DI (match_operand:DI 1 "register_operand" "")
2275 (match_operand:SI 2 "small_int" "")))
2276 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2277 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2278 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2279 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2280 && (INTVAL (operands[2]) & 32) != 0"
2281
2282 [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
2283 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
2284
2285 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2286
2287
2288(define_split
2289 [(set (match_operand:DI 0 "register_operand" "")
2290 (ashift:DI (match_operand:DI 1 "register_operand" "")
2291 (match_operand:SI 2 "small_int" "")))
2292 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2293 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2294 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2295 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2296 && (INTVAL (operands[2]) & 32) != 0"
2297
2298 [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
2299 (set (subreg:SI (match_dup 0) 1) (const_int 0))]
2300
2301 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2302
2303
2304(define_insn "ashldi3_internal3"
2305 [(set (match_operand:DI 0 "register_operand" "=d")
2306 (ashift:DI (match_operand:DI 1 "register_operand" "d")
2307 (match_operand:SI 2 "small_int" "IJK")))
2308 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2309 "!TARGET_DEBUG_G_MODE
2310 && (INTVAL (operands[2]) & 63) < 32
2311 && (INTVAL (operands[2]) & 63) != 0"
2312 "*
2313{
2314 int amount = INTVAL (operands[2]);
2315
2316 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2317 operands[4] = const0_rtx;
2318 operands[5] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2319
2320 return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
2321}"
2322 [(set_attr "type" "darith")
2323 (set_attr "mode" "DI")
2324 (set_attr "length" "4")])
2325
2326
2327(define_split
2328 [(set (match_operand:DI 0 "register_operand" "")
2329 (ashift:DI (match_operand:DI 1 "register_operand" "")
2330 (match_operand:SI 2 "small_int" "")))
2331 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2332 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2333 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2334 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2335 && (INTVAL (operands[2]) & 63) < 32
2336 && (INTVAL (operands[2]) & 63) != 0"
2337
2338 [(set (subreg:SI (match_dup 0) 1)
2339 (ashift:SI (subreg:SI (match_dup 1) 1)
2340 (match_dup 2)))
2341
2342 (set (match_dup 3)
2343 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
2344 (match_dup 4)))
2345
2346 (set (subreg:SI (match_dup 0) 1)
2347 (ior:SI (subreg:SI (match_dup 0) 1)
2348 (match_dup 3)))
2349
2350 (set (subreg:SI (match_dup 0) 0)
2351 (ashift:SI (subreg:SI (match_dup 1) 0)
2352 (match_dup 2)))]
2353 "
2354{
2355 int amount = INTVAL (operands[2]);
2356 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2357 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2358}")
2359
2360
2361(define_split
2362 [(set (match_operand:DI 0 "register_operand" "")
2363 (ashift:DI (match_operand:DI 1 "register_operand" "")
2364 (match_operand:SI 2 "small_int" "")))
2365 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2366 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2367 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2368 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2369 && (INTVAL (operands[2]) & 63) < 32
2370 && (INTVAL (operands[2]) & 63) != 0"
2371
2372 [(set (subreg:SI (match_dup 0) 0)
2373 (ashift:SI (subreg:SI (match_dup 1) 0)
2374 (match_dup 2)))
2375
2376 (set (match_dup 3)
2377 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
2378 (match_dup 4)))
2379
2380 (set (subreg:SI (match_dup 0) 0)
2381 (ior:SI (subreg:SI (match_dup 0) 0)
2382 (match_dup 3)))
2383
2384 (set (subreg:SI (match_dup 0) 1)
2385 (ashift:SI (subreg:SI (match_dup 1) 1)
2386 (match_dup 2)))]
2387 "
2388{
2389 int amount = INTVAL (operands[2]);
2390 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2391 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2392}")
2393
2394
2395(define_insn "ashrsi3"
2396 [(set (match_operand:SI 0 "register_operand" "=d")
2397 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
2398 (match_operand:SI 2 "arith_operand" "dI")))]
2399 ""
2400 "*
2401{
2402 if (GET_CODE (operands[2]) == CONST_INT)
2403 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2404
2405 return \"sra\\t%0,%1,%2\";
2406}"
2407 [(set_attr "type" "arith")
2408 (set_attr "mode" "SI")
2409 (set_attr "length" "1")])
2410
2411
2412(define_expand "ashrdi3"
2413 [(parallel [(set (match_operand:DI 0 "register_operand" "")
2414 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2415 (match_operand:SI 2 "arith_operand" "")))
2416 (clobber (match_dup 3))])]
2417 "!TARGET_DEBUG_G_MODE"
2418 "operands[3] = gen_reg_rtx (SImode);")
2419
2420
2421(define_insn "ashrdi3_internal"
0fb5ac6f 2422 [(set (match_operand:DI 0 "register_operand" "=&d")
8ef30996
MM		 2423 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2424 (match_operand:SI 2 "register_operand" "d")))
2425 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2426 "!TARGET_DEBUG_G_MODE"
2427 "*
2428{
2429 operands[4] = const0_rtx;
2430 dslots_jump_total += 3;
2431 dslots_jump_filled += 2;
2432
2433 return \"sll\\t%3,%2,26\\n\\
2434\\tbgez\\t%3,1f\\n\\
2435\\tsra\\t%L0,%M1,%2\\n\\
2436\\t%(b\\t3f\\n\\
2437\\tsra\\t%M0,%M1,31%)\\n\\
2438\\n\\
24391:\\n\\
2440\\t%(beq\\t%3,%z4,2f\\n\\
2441\\tsrl\\t%L0,%L1,%2%)\\n\\
2442\\n\\
2443\\tsubu\\t%3,%z4,%2\\n\\
2444\\tsll\\t%3,%M1,%3\\n\\
2445\\tor\\t%L0,%L0,%3\\n\\
24462:\\n\\
2447\\tsra\\t%M0,%M1,%2\\n\\
24483:\";
2449}"
2450 [(set_attr "type" "darith")
2451 (set_attr "mode" "DI")
2452 (set_attr "length" "12")])
2453
2454
2455(define_insn "ashrdi3_internal2"
2456 [(set (match_operand:DI 0 "register_operand" "=d")
2457 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2458 (match_operand:SI 2 "small_int" "IJK")))
2459 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2460 "!TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
2461 "*
2462{
2463 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2464 return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
2465}"
2466 [(set_attr "type" "darith")
2467 (set_attr "mode" "DI")
2468 (set_attr "length" "2")])
2469
2470
2471(define_split
2472 [(set (match_operand:DI 0 "register_operand" "")
2473 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2474 (match_operand:SI 2 "small_int" "")))
2475 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2476 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2477 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2478 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2479 && (INTVAL (operands[2]) & 32) != 0"
2480
2481 [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
2482 (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))]
2483
2484 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2485
2486
2487(define_split
2488 [(set (match_operand:DI 0 "register_operand" "")
2489 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2490 (match_operand:SI 2 "small_int" "")))
2491 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2492 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2493 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2494 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2495 && (INTVAL (operands[2]) & 32) != 0"
2496
2497 [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
2498 (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
2499
2500 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2501
2502
2503(define_insn "ashrdi3_internal3"
2504 [(set (match_operand:DI 0 "register_operand" "=d")
2505 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2506 (match_operand:SI 2 "small_int" "IJK")))
2507 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2508 "!TARGET_DEBUG_G_MODE
2509 && (INTVAL (operands[2]) & 63) < 32
2510 && (INTVAL (operands[2]) & 63) != 0"
2511 "*
2512{
2513 int amount = INTVAL (operands[2]);
2514
2515 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2516 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2517
2518 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
2519}"
2520 [(set_attr "type" "darith")
2521 (set_attr "mode" "DI")
2522 (set_attr "length" "4")])
2523
2524
2525(define_split
2526 [(set (match_operand:DI 0 "register_operand" "")
2527 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2528 (match_operand:SI 2 "small_int" "")))
2529 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2530 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2531 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2532 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2533 && (INTVAL (operands[2]) & 63) < 32
2534 && (INTVAL (operands[2]) & 63) != 0"
2535
2536 [(set (subreg:SI (match_dup 0) 0)
2537 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
2538 (match_dup 2)))
2539
2540 (set (match_dup 3)
2541 (ashift:SI (subreg:SI (match_dup 1) 1)
2542 (match_dup 4)))
2543
2544 (set (subreg:SI (match_dup 0) 0)
2545 (ior:SI (subreg:SI (match_dup 0) 0)
2546 (match_dup 3)))
2547
2548 (set (subreg:SI (match_dup 0) 1)
2549 (ashiftrt:SI (subreg:SI (match_dup 1) 1)
2550 (match_dup 2)))]
2551 "
2552{
2553 int amount = INTVAL (operands[2]);
2554 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2555 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2556}")
2557
2558
2559(define_split
2560 [(set (match_operand:DI 0 "register_operand" "")
2561 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2562 (match_operand:SI 2 "small_int" "")))
2563 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2564 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2565 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2566 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2567 && (INTVAL (operands[2]) & 63) < 32
2568 && (INTVAL (operands[2]) & 63) != 0"
2569
2570 [(set (subreg:SI (match_dup 0) 1)
2571 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
2572 (match_dup 2)))
2573
2574 (set (match_dup 3)
2575 (ashift:SI (subreg:SI (match_dup 1) 0)
2576 (match_dup 4)))
2577
2578 (set (subreg:SI (match_dup 0) 1)
2579 (ior:SI (subreg:SI (match_dup 0) 1)
2580 (match_dup 3)))
2581
2582 (set (subreg:SI (match_dup 0) 0)
2583 (ashiftrt:SI (subreg:SI (match_dup 1) 0)
2584 (match_dup 2)))]
2585 "
2586{
2587 int amount = INTVAL (operands[2]);
2588 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2589 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2590}")
2591
2592
2593(define_insn "lshrsi3"
2594 [(set (match_operand:SI 0 "register_operand" "=d")
2595 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
2596 (match_operand:SI 2 "arith_operand" "dI")))]
2597 ""
2598 "*
2599{
2600 if (GET_CODE (operands[2]) == CONST_INT)
2601 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2602
2603 return \"srl\\t%0,%1,%2\";
2604}"
2605 [(set_attr "type" "arith")
2606 (set_attr "mode" "SI")
2607 (set_attr "length" "1")])
2608
2609
2610(define_expand "lshrdi3"
2611 [(parallel [(set (match_operand:DI 0 "register_operand" "")
2612 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2613 (match_operand:SI 2 "arith_operand" "")))
2614 (clobber (match_dup 3))])]
2615 "!TARGET_DEBUG_G_MODE"
2616 "operands[3] = gen_reg_rtx (SImode);")
2617
2618
2619(define_insn "lshrdi3_internal"
2620 [(set (match_operand:DI 0 "register_operand" "=&d")
2621 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2622 (match_operand:SI 2 "register_operand" "d")))
2623 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2624 "!TARGET_DEBUG_G_MODE"
2625 "*
2626{
2627 operands[4] = const0_rtx;
2628 dslots_jump_total += 3;
2629 dslots_jump_filled += 2;
2630
2631 return \"sll\\t%3,%2,26\\n\\
2632\\tbgez\\t%3,1f\\n\\
2633\\tsrl\\t%L0,%M1,%2\\n\\
2634\\t%(b\\t3f\\n\\
2635\\tmove\\t%M0,%z4%)\\n\\
2636\\n\\
26371:\\n\\
2638\\t%(beq\\t%3,%z4,2f\\n\\
2639\\tsrl\\t%L0,%L1,%2%)\\n\\
2640\\n\\
2641\\tsubu\\t%3,%z4,%2\\n\\
2642\\tsll\\t%3,%M1,%3\\n\\
2643\\tor\\t%L0,%L0,%3\\n\\
26442:\\n\\
2645\\tsrl\\t%M0,%M1,%2\\n\\
26463:\";
2647}"
2648 [(set_attr "type" "darith")
2649 (set_attr "mode" "DI")
2650 (set_attr "length" "12")])
2651
2652
2653(define_insn "lshrdi3_internal2"
2654 [(set (match_operand:DI 0 "register_operand" "=d")
2655 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2656 (match_operand:SI 2 "small_int" "IJK")))
2657 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2658 "!TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
2659 "*
2660{
2661 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2662 operands[4] = const0_rtx;
2663 return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
2664}"
2665 [(set_attr "type" "darith")
2666 (set_attr "mode" "DI")
2667 (set_attr "length" "2")])
2668
2669
2670(define_split
2671 [(set (match_operand:DI 0 "register_operand" "")
2672 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2673 (match_operand:SI 2 "small_int" "")))
2674 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2675 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2676 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2677 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2678 && (INTVAL (operands[2]) & 32) != 0"
2679
2680 [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
2681 (set (subreg:SI (match_dup 0) 1) (const_int 0))]
2682
2683 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2684
2685
2686(define_split
2687 [(set (match_operand:DI 0 "register_operand" "")
2688 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2689 (match_operand:SI 2 "small_int" "")))
2690 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2691 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2692 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2693 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2694 && (INTVAL (operands[2]) & 32) != 0"
2695
2696 [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
2697 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
2698
2699 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2700
2701
2702(define_insn "lshrdi3_internal3"
2703 [(set (match_operand:DI 0 "register_operand" "=d")
2704 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2705 (match_operand:SI 2 "small_int" "IJK")))
2706 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2707 "!TARGET_DEBUG_G_MODE
2708 && (INTVAL (operands[2]) & 63) < 32
2709 && (INTVAL (operands[2]) & 63) != 0"
2710 "*
2711{
2712 int amount = INTVAL (operands[2]);
2713
2714 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2715 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2716
2717 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
2718}"
2719 [(set_attr "type" "darith")
2720 (set_attr "mode" "DI")
2721 (set_attr "length" "4")])
2722
2723
2724(define_split
2725 [(set (match_operand:DI 0 "register_operand" "")
2726 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2727 (match_operand:SI 2 "small_int" "")))
2728 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2729 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2730 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2731 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2732 && (INTVAL (operands[2]) & 63) < 32
2733 && (INTVAL (operands[2]) & 63) != 0"
2734
2735 [(set (subreg:SI (match_dup 0) 0)
2736 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
2737 (match_dup 2)))
2738
2739 (set (match_dup 3)
2740 (ashift:SI (subreg:SI (match_dup 1) 1)
2741 (match_dup 4)))
2742
2743 (set (subreg:SI (match_dup 0) 0)
2744 (ior:SI (subreg:SI (match_dup 0) 0)
2745 (match_dup 3)))
2746
2747 (set (subreg:SI (match_dup 0) 1)
2748 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
2749 (match_dup 2)))]
2750 "
2751{
2752 int amount = INTVAL (operands[2]);
2753 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2754 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2755}")
2756
2757
2758(define_split
2759 [(set (match_operand:DI 0 "register_operand" "")
2760 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2761 (match_operand:SI 2 "small_int" "")))
2762 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2763 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2764 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2765 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2766 && (INTVAL (operands[2]) & 63) < 32
2767 && (INTVAL (operands[2]) & 63) != 0"
2768
2769 [(set (subreg:SI (match_dup 0) 1)
2770 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
2771 (match_dup 2)))
2772
2773 (set (match_dup 3)
2774 (ashift:SI (subreg:SI (match_dup 1) 0)
2775 (match_dup 4)))
2776
2777 (set (subreg:SI (match_dup 0) 1)
2778 (ior:SI (subreg:SI (match_dup 0) 1)
2779 (match_dup 3)))
2780
2781 (set (subreg:SI (match_dup 0) 0)
2782 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
2783 (match_dup 2)))]
2784 "
2785{
2786 int amount = INTVAL (operands[2]);
2787 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2788 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2789}")
2790
2791\f
2792;;
2793;; ....................
2794;;
2795;; COMPARISONS
2796;;
2797;; ....................
2798
2799;; Flow here is rather complex:
2800;;
2801;; 1) The cmp{si,sf,df} routine is called. It deposits the
2802;; arguments into the branch_cmp array, and the type into
2803;; branch_type. No RTL is generated.
2804;;
2805;; 2) The appropriate branch define_expand is called, which then
2806;; creates the appropriate RTL for the comparison and branch.
2807;; Different CC modes are used, based on what type of branch is
2808;; done, so that we can constrain things appropriately. There
2809;; are assumptions in the rest of GCC that break if we fold the
2810;; operands into the branchs for integer operations, and use cc0
34b650b3
MM		 2811;; for floating point, so we use the fp status register instead.
2812;; If needed, an appropriate temporary is created to hold the
2813;; of the integer compare.
8ef30996
MM		 2814
2815(define_expand "cmpsi"
2816 [(set (cc0)
2817 (compare:CC (match_operand:SI 0 "register_operand" "")
2818 (match_operand:SI 1 "arith_operand" "")))]
2819 ""
2820 "
2821{
2822 if (operands[0]) /* avoid unused code message */
2823 {
2824 branch_cmp[0] = operands[0];
2825 branch_cmp[1] = operands[1];
2826 branch_type = CMP_SI;
2827 DONE;
2828 }
2829}")
2830
2831(define_expand "tstsi"
2832 [(set (cc0)
2833 (match_operand:SI 0 "register_operand" ""))]
2834 ""
2835 "
2836{
2837 if (operands[0]) /* avoid unused code message */
2838 {
2839 branch_cmp[0] = operands[0];
2840 branch_cmp[1] = const0_rtx;
2841 branch_type = CMP_SI;
2842 DONE;
2843 }
2844}")
2845
8ef30996
MM		 2846(define_expand "cmpdf"
2847 [(set (cc0)
2848 (compare:CC_FP (match_operand:DF 0 "register_operand" "")
2849 (match_operand:DF 1 "register_operand" "")))]
2850 "TARGET_HARD_FLOAT"
2851 "
2852{
2853 if (operands[0]) /* avoid unused code message */
2854 {
2855 branch_cmp[0] = operands[0];
2856 branch_cmp[1] = operands[1];
2857 branch_type = CMP_DF;
2858 DONE;
2859 }
2860}")
2861
8ef30996
MM		 2862(define_expand "cmpsf"
2863 [(set (cc0)
2864 (compare:CC_FP (match_operand:SF 0 "register_operand" "")
2865 (match_operand:SF 1 "register_operand" "")))]
2866 "TARGET_HARD_FLOAT"
2867 "
2868{
2869 if (operands[0]) /* avoid unused code message */
2870 {
2871 branch_cmp[0] = operands[0];
2872 branch_cmp[1] = operands[1];
2873 branch_type = CMP_SF;
2874 DONE;
2875 }
2876}")
2877
8ef30996
MM		 2878\f
2879;;
2880;; ....................
2881;;
2882;; CONDITIONAL BRANCHES
2883;;
2884;; ....................
2885
34b650b3 2886(define_insn "branch_fp_ne"
8ef30996 2887 [(set (pc)
34b650b3
MM		 2888 (if_then_else (ne:CC_FP (reg:CC_FP 66)
2889 (const_int 0))
2890 (match_operand 0 "pc_or_label_operand" "")
2891 (match_operand 1 "pc_or_label_operand" "")))]
8ef30996
MM		 2892 ""
2893 "*
2894{
8ef30996 2895 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 2896 return (operands[0] != pc_rtx) ? \"%*bc1t%?\\t%0\" : \"%*bc1f%?\\t%1\";
8ef30996
MM		 2897}"
2898 [(set_attr "type" "branch")
2899 (set_attr "mode" "none")
34b650b3 2900 (set_attr "length" "1")])
8ef30996 2901
34b650b3 2902(define_insn "branch_fp_ne_rev"
8ef30996 2903 [(set (pc)
34b650b3
MM		 2904 (if_then_else (ne:CC_REV_FP (reg:CC_REV_FP 66)
2905 (const_int 0))
2906 (match_operand 0 "pc_or_label_operand" "")
2907 (match_operand 1 "pc_or_label_operand" "")))]
8ef30996
MM		 2908 ""
2909 "*
2910{
8ef30996 2911 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 2912 return (operands[0] != pc_rtx) ? \"%*bc1f%?\\t%0\" : \"%*bc1t%?\\t%1\";
8ef30996
MM		 2913}"
2914 [(set_attr "type" "branch")
2915 (set_attr "mode" "none")
34b650b3 2916 (set_attr "length" "1")])
8ef30996 2917
34b650b3 2918(define_insn "branch_fp_eq"
8ef30996 2919 [(set (pc)
34b650b3
MM		 2920 (if_then_else (eq:CC_FP (reg:CC_FP 66)
2921 (const_int 0))
2922 (match_operand 0 "pc_or_label_operand" "")
2923 (match_operand 1 "pc_or_label_operand" "")))]
8ef30996
MM		 2924 ""
2925 "*
2926{
2927 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 2928 return (operands[0] != pc_rtx) ? \"%*bc1f%?\\t%0\" : \"%*bc1t%?\\t%1\";
8ef30996
MM		 2929}"
2930 [(set_attr "type" "branch")
2931 (set_attr "mode" "none")
2932 (set_attr "length" "1")])
2933
34b650b3 2934(define_insn "branch_fp_eq_rev"
8ef30996 2935 [(set (pc)
34b650b3
MM		 2936 (if_then_else (eq:CC_REV_FP (reg:CC_REV_FP 66)
2937 (const_int 0))
2938 (match_operand 0 "pc_or_label_operand" "")
2939 (match_operand 1 "pc_or_label_operand" "")))]
8ef30996
MM		 2940 ""
2941 "*
2942{
2943 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 2944 return (operands[0] != pc_rtx) ? \"%*bc1t%?\\t%0\" : \"%*bc1f%?\\t%1\";
8ef30996
MM		 2945}"
2946 [(set_attr "type" "branch")
2947 (set_attr "mode" "none")
2948 (set_attr "length" "1")])
2949
34b650b3
MM		 2950
2951(define_insn "branch_zero"
8ef30996 2952 [(set (pc)
34b650b3 2953 (if_then_else (match_operator:SI 0 "cmp_op"
81723db9 2954 [(match_operand:SI 1 "register_operand" "d")
34b650b3
MM		 2955 (const_int 0)])
2956 (match_operand 2 "pc_or_label_operand" "")
2957 (match_operand 3 "pc_or_label_operand" "")))]
8ef30996
MM		 2958 ""
2959 "*
2960{
2961 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3
MM		 2962 if (operands[2] != pc_rtx)
2963 { /* normal jump */
2964 switch (GET_CODE (operands[0]))
2965 {
2966 case EQ: return \"%*beq%?\\t%z1,%.,%2\";
2967 case NE: return \"%*bne%?\\t%z1,%.,%2\";
2968 case GTU: return \"%*bne%?\\t%z1,%.,%2\";
2969 case LEU: return \"%*beq%?\\t%z1,%.,%2\";
2970 case GEU: return \"%*j\\t%2\";
81723db9 2971 case LTU: return \"%*bne%?\\t%.,%.,%2\";
34b650b3 2972 }
8ef30996 2973
34b650b3 2974 return \"%*b%C0z%?\\t%z1,%2\";
8ef30996 2975 }
34b650b3
MM		 2976 else
2977 { /* inverted jump */
2978 switch (GET_CODE (operands[0]))
2979 {
2980 case EQ: return \"%*bne%?\\t%z1,%.,%3\";
2981 case NE: return \"%*beq%?\\t%z1,%.,%3\";
2982 case GTU: return \"%*beq%?\\t%z1,%.,%3\";
2983 case LEU: return \"%*bne%?\\t%z1,%.,%3\";
81723db9 2984 case GEU: return \"%*beq%?\\t%.,%.,%3\";
34b650b3
MM		 2985 case LTU: return \"%*j\\t%3\";
2986 }
8ef30996 2987
34b650b3
MM		 2988 return \"%*b%N0z%?\\t%z1,%3\";
2989 }
8ef30996
MM		 2990}"
2991 [(set_attr "type" "branch")
2992 (set_attr "mode" "none")
2993 (set_attr "length" "1")])
2994
8ef30996 2995
34b650b3 2996(define_insn "branch_equality"
8ef30996 2997 [(set (pc)
34b650b3
MM		 2998 (if_then_else (match_operator:SI 0 "equality_op"
2999 [(match_operand:SI 1 "register_operand" "d")
3000 (match_operand:SI 2 "register_operand" "d")])
3001 (match_operand 3 "pc_or_label_operand" "")
3002 (match_operand 4 "pc_or_label_operand" "")))]
8ef30996
MM		 3003 ""
3004 "*
3005{
3006 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3
MM		 3007 return (operands[3] != pc_rtx)
3008 ? \"%*b%C0%?\\t%z1,%z2,%3\"
3009 : \"%*b%N0%?\\t%z1,%z2,%4\";
8ef30996
MM		 3010}"
3011 [(set_attr "type" "branch")
3012 (set_attr "mode" "none")
34b650b3
MM		 3013 (set_attr "length" "1")])
3014
8ef30996
MM		 3015
3016(define_expand "beq"
3017 [(set (pc)
3018 (if_then_else (eq:CC_EQ (cc0)
3019 (const_int 0))
3020 (label_ref (match_operand 0 "" ""))
3021 (pc)))]
3022 ""
3023 "
3024{
3025 if (operands[0]) /* avoid unused code warning */
3026 {
3027 gen_conditional_branch (operands, EQ);
3028 DONE;
3029 }
3030}")
3031
3032(define_expand "bne"
3033 [(set (pc)
3034 (if_then_else (ne:CC_EQ (cc0)
3035 (const_int 0))
3036 (label_ref (match_operand 0 "" ""))
3037 (pc)))]
3038 ""
3039 "
3040{
3041 if (operands[0]) /* avoid unused code warning */
3042 {
3043 gen_conditional_branch (operands, NE);
3044 DONE;
3045 }
3046}")
3047
3048(define_expand "bgt"
3049 [(set (pc)
3050 (if_then_else (gt:CC (cc0)
3051 (const_int 0))
3052 (label_ref (match_operand 0 "" ""))
3053 (pc)))]
3054 ""
3055 "
3056{
3057 if (operands[0]) /* avoid unused code warning */
3058 {
3059 gen_conditional_branch (operands, GT);
3060 DONE;
3061 }
3062}")
3063
3064(define_expand "bge"
3065 [(set (pc)
3066 (if_then_else (ge:CC (cc0)
3067 (const_int 0))
3068 (label_ref (match_operand 0 "" ""))
3069 (pc)))]
3070 ""
3071 "
3072{
3073 if (operands[0]) /* avoid unused code warning */
3074 {
3075 gen_conditional_branch (operands, GE);
3076 DONE;
3077 }
3078}")
3079
3080(define_expand "blt"
3081 [(set (pc)
3082 (if_then_else (lt:CC (cc0)
3083 (const_int 0))
3084 (label_ref (match_operand 0 "" ""))
3085 (pc)))]
3086 ""
3087 "
3088{
3089 if (operands[0]) /* avoid unused code warning */
3090 {
3091 gen_conditional_branch (operands, LT);
3092 DONE;
3093 }
3094}")
3095
3096(define_expand "ble"
3097 [(set (pc)
3098 (if_then_else (le:CC (cc0)
3099 (const_int 0))
3100 (label_ref (match_operand 0 "" ""))
3101 (pc)))]
3102 ""
3103 "
3104{
3105 if (operands[0]) /* avoid unused code warning */
3106 {
3107 gen_conditional_branch (operands, LE);
3108 DONE;
3109 }
3110}")
3111
3112(define_expand "bgtu"
3113 [(set (pc)
3114 (if_then_else (gtu:CC (cc0)
3115 (const_int 0))
3116 (label_ref (match_operand 0 "" ""))
3117 (pc)))]
3118 ""
3119 "
3120{
3121 if (operands[0]) /* avoid unused code warning */
3122 {
3123 gen_conditional_branch (operands, GTU);
3124 DONE;
3125 }
3126}")
3127
3128(define_expand "bgeu"
3129 [(set (pc)
3130 (if_then_else (geu:CC (cc0)
3131 (const_int 0))
3132 (label_ref (match_operand 0 "" ""))
3133 (pc)))]
3134 ""
3135 "
3136{
3137 if (operands[0]) /* avoid unused code warning */
3138 {
3139 gen_conditional_branch (operands, GEU);
3140 DONE;
3141 }
3142}")
3143
3144
3145(define_expand "bltu"
3146 [(set (pc)
3147 (if_then_else (ltu:CC (cc0)
3148 (const_int 0))
3149 (label_ref (match_operand 0 "" ""))
3150 (pc)))]
3151 ""
3152 "
3153{
3154 if (operands[0]) /* avoid unused code warning */
3155 {
3156 gen_conditional_branch (operands, LTU);
3157 DONE;
3158 }
3159}")
3160
3161(define_expand "bleu"
3162 [(set (pc)
3163 (if_then_else (leu:CC (cc0)
3164 (const_int 0))
3165 (label_ref (match_operand 0 "" ""))
3166 (pc)))]
3167 ""
3168 "
3169{
3170 if (operands[0]) /* avoid unused code warning */
3171 {
3172 gen_conditional_branch (operands, LEU);
3173 DONE;
3174 }
3175}")
3176
3177\f
3178;;
3179;; ....................
3180;;
3181;; SETTING A REGISTER FROM A COMPARISON
3182;;
3183;; ....................
3184
3185(define_expand "seq"
3186 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3
MM		 3187 (eq:SI (match_dup 1)
3188 (match_dup 2)))]
8ef30996
MM		 3189 ""
3190 "
3191{
8ef30996
MM		 3192 if (branch_type != CMP_SI)
3193 FAIL;
3194
3195 /* set up operands from compare. */
3196 operands[1] = branch_cmp[0];
3197 operands[2] = branch_cmp[1];
3198
bbdb5552 3199 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3200 {
3201 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
3202 DONE;
3203 }
3204
8ef30996
MM		 3205 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3206 operands[2] = force_reg (SImode, operands[2]);
3207
3208 /* fall through and generate default code */
3209}")
3210
34b650b3
MM		 3211
3212(define_insn "seq_si_zero"
3213 [(set (match_operand:SI 0 "register_operand" "=d")
3214 (eq:SI (match_operand:SI 1 "register_operand" "d")
3215 (const_int 0)))]
8ef30996 3216 ""
34b650b3
MM		 3217 "sltu\\t%0,%1,1"
3218 [(set_attr "type" "arith")
3219 (set_attr "mode" "SI")
3220 (set_attr "length" "1")])
3221
3222(define_insn "seq_si"
3223 [(set (match_operand:SI 0 "register_operand" "=d,d")
3224 (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
3225 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
bbdb5552 3226 "TARGET_DEBUG_C_MODE"
8ef30996 3227 "@
8ef30996 3228 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
34b650b3 3229 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
92b4cee1
MM		 3230 [(set_attr "type" "arith")
3231 (set_attr "mode" "SI")
3232 (set_attr "length" "2")])
8ef30996
MM		 3233
3234(define_split
3235 [(set (match_operand:SI 0 "register_operand" "")
34b650b3
MM		 3236 (eq:SI (match_operand:SI 1 "register_operand" "")
3237 (match_operand:SI 2 "uns_arith_operand" "")))]
bbdb5552 3238 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
26b8e6e5 3239 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8ef30996
MM		 3240 [(set (match_dup 0)
3241 (xor:SI (match_dup 1)
3242 (match_dup 2)))
3243 (set (match_dup 0)
34b650b3 3244 (ltu:SI (match_dup 0)
8ef30996
MM		 3245 (const_int 1)))]
3246 "")
3247
3248(define_expand "sne"
3249 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3
MM		 3250 (ne:SI (match_dup 1)
3251 (match_dup 2)))]
8ef30996
MM		 3252 ""
3253 "
3254{
8ef30996
MM		 3255 if (branch_type != CMP_SI)
3256 FAIL;
3257
3258 /* set up operands from compare. */
3259 operands[1] = branch_cmp[0];
3260 operands[2] = branch_cmp[1];
3261
bbdb5552 3262 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3263 {
3264 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
3265 DONE;
3266 }
3267
8ef30996
MM		 3268 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3269 operands[2] = force_reg (SImode, operands[2]);
3270
3271 /* fall through and generate default code */
3272}")
3273
34b650b3
MM		 3274(define_insn "sne_si_zero"
3275 [(set (match_operand:SI 0 "register_operand" "=d")
3276 (ne:SI (match_operand:SI 1 "register_operand" "d")
3277 (const_int 0)))]
8ef30996 3278 ""
34b650b3
MM		 3279 "sltu\\t%0,%.,%1"
3280 [(set_attr "type" "arith")
3281 (set_attr "mode" "SI")
3282 (set_attr "length" "1")])
8ef30996 3283
34b650b3
MM		 3284(define_insn "sne_si"
3285 [(set (match_operand:SI 0 "register_operand" "=d,d")
3286 (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
3287 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
bbdb5552 3288 "TARGET_DEBUG_C_MODE"
34b650b3
MM		 3289 "@
3290 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
3291 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
92b4cee1
MM		 3292 [(set_attr "type" "arith")
3293 (set_attr "mode" "SI")
3294 (set_attr "length" "2")])
8ef30996
MM		 3295
3296(define_split
3297 [(set (match_operand:SI 0 "register_operand" "")
34b650b3
MM		 3298 (ne:SI (match_operand:SI 1 "register_operand" "")
3299 (match_operand:SI 2 "uns_arith_operand" "")))]
bbdb5552 3300 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
26b8e6e5 3301 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8ef30996
MM		 3302 [(set (match_dup 0)
3303 (xor:SI (match_dup 1)
3304 (match_dup 2)))
3305 (set (match_dup 0)
34b650b3 3306 (gtu:SI (match_dup 0)
8ef30996
MM		 3307 (const_int 0)))]
3308 "")
3309
3310(define_expand "sgt"
3311 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3312 (gt:SI (match_dup 1)
8ef30996
MM		 3313 (match_dup 2)))]
3314 ""
3315 "
3316{
8ef30996
MM		 3317 if (branch_type != CMP_SI)
3318 FAIL;
3319
3320 /* set up operands from compare. */
3321 operands[1] = branch_cmp[0];
3322 operands[2] = branch_cmp[1];
3323
bbdb5552 3324 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3325 {
3326 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
3327 DONE;
3328 }
3329
8ef30996
MM		 3330 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3331 operands[2] = force_reg (SImode, operands[2]);
3332
3333 /* fall through and generate default code */
3334}")
3335
3336(define_insn "sgt_si"
3337 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3338 (gt:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 3339 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
3340 ""
3341 "slt\\t%0,%z2,%1"
3342 [(set_attr "type" "arith")
3343 (set_attr "mode" "SI")
3344 (set_attr "length" "1")])
3345
3346(define_expand "sge"
3347 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3348 (ge:SI (match_dup 1)
8ef30996
MM		 3349 (match_dup 2)))]
3350 ""
3351 "
3352{
3353 if (branch_type != CMP_SI)
3354 FAIL;
3355
3356 /* set up operands from compare. */
3357 operands[1] = branch_cmp[0];
3358 operands[2] = branch_cmp[1];
3359
bbdb5552 3360 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3361 {
3362 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
3363 DONE;
3364 }
3365
8ef30996
MM		 3366 /* fall through and generate default code */
3367}")
3368
3369(define_insn "sge_si"
3370 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3371 (ge:SI (match_operand:SI 1 "register_operand" "d")
8ef30996 3372 (match_operand:SI 2 "arith_operand" "dI")))]
bbdb5552 3373 "TARGET_DEBUG_C_MODE"
8ef30996
MM		 3374 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
3375 [(set_attr "type" "arith")
3376 (set_attr "mode" "SI")
3377 (set_attr "length" "2")])
3378
3379(define_split
3380 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 3381 (ge:SI (match_operand:SI 1 "register_operand" "")
8ef30996 3382 (match_operand:SI 2 "arith_operand" "")))]
bbdb5552 3383 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 3384 [(set (match_dup 0)
34b650b3 3385 (lt:SI (match_dup 1)
8ef30996
MM		 3386 (match_dup 2)))
3387 (set (match_dup 0)
3388 (xor:SI (match_dup 0)
3389 (const_int 1)))]
3390 "")
3391
3392(define_expand "slt"
3393 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3394 (lt:SI (match_dup 1)
8ef30996
MM		 3395 (match_dup 2)))]
3396 ""
3397 "
3398{
3399 if (branch_type != CMP_SI)
3400 FAIL;
3401
3402 /* set up operands from compare. */
3403 operands[1] = branch_cmp[0];
3404 operands[2] = branch_cmp[1];
3405
bbdb5552 3406 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3407 {
3408 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
3409 DONE;
3410 }
3411
8ef30996
MM		 3412 /* fall through and generate default code */
3413}")
3414
3415(define_insn "slt_si"
3416 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3417 (lt:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 3418 (match_operand:SI 2 "arith_operand" "dI")))]
3419 ""
3420 "slt\\t%0,%1,%2"
3421 [(set_attr "type" "arith")
3422 (set_attr "mode" "SI")
3423 (set_attr "length" "1")])
3424
3425(define_expand "sle"
3426 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3427 (le:SI (match_dup 1)
8ef30996
MM		 3428 (match_dup 2)))]
3429 ""
3430 "
3431{
8ef30996
MM		 3432 if (branch_type != CMP_SI)
3433 FAIL;
3434
3435 /* set up operands from compare. */
3436 operands[1] = branch_cmp[0];
3437 operands[2] = branch_cmp[1];
3438
bbdb5552 3439 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3440 {
3441 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
3442 DONE;
3443 }
3444
8ef30996
MM		 3445 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
3446 operands[2] = force_reg (SImode, operands[2]);
3447
3448 /* fall through and generate default code */
3449}")
3450
34b650b3
MM		 3451(define_insn "sle_si_const"
3452 [(set (match_operand:SI 0 "register_operand" "=d")
3453 (le:SI (match_operand:SI 1 "register_operand" "d")
3454 (match_operand:SI 2 "small_int" "I")))]
3455 "INTVAL (operands[2]) < 32767"
3456 "*
3457{
3458 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
3459 return \"slt\\t%0,%1,%2\";
3460}"
3461 [(set_attr "type" "arith")
3462 (set_attr "mode" "SI")
3463 (set_attr "length" "1")])
3464
3465(define_insn "sle_si_reg"
3466 [(set (match_operand:SI 0 "register_operand" "=d")
3467 (le:SI (match_operand:SI 1 "register_operand" "d")
3468 (match_operand:SI 2 "register_operand" "d")))]
bbdb5552 3469 "TARGET_DEBUG_C_MODE"
34b650b3
MM		 3470 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
3471 [(set_attr "type" "arith")
3472 (set_attr "mode" "SI")
3473 (set_attr "length" "2")])
8ef30996
MM		 3474
3475(define_split
3476 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 3477 (le:SI (match_operand:SI 1 "register_operand" "")
8ef30996 3478 (match_operand:SI 2 "register_operand" "")))]
bbdb5552 3479 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 3480 [(set (match_dup 0)
34b650b3 3481 (lt:SI (match_dup 2)
8ef30996
MM		 3482 (match_dup 1)))
3483 (set (match_dup 0)
3484 (xor:SI (match_dup 0)
3485 (const_int 1)))]
3486 "")
3487
3488(define_expand "sgtu"
3489 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3490 (gtu:SI (match_dup 1)
8ef30996
MM		 3491 (match_dup 2)))]
3492 ""
3493 "
3494{
8ef30996
MM		 3495 if (branch_type != CMP_SI)
3496 FAIL;
3497
3498 /* set up operands from compare. */
3499 operands[1] = branch_cmp[0];
3500 operands[2] = branch_cmp[1];
3501
bbdb5552 3502 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3503 {
3504 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
3505 DONE;
3506 }
3507
8ef30996
MM		 3508 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3509 operands[2] = force_reg (SImode, operands[2]);
3510
3511 /* fall through and generate default code */
3512}")
3513
3514(define_insn "sgtu_si"
3515 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3516 (gtu:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 3517 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
3518 ""
3519 "sltu\\t%0,%z2,%1"
3520 [(set_attr "type" "arith")
3521 (set_attr "mode" "SI")
3522 (set_attr "length" "1")])
3523
3524(define_expand "sgeu"
3525 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3526 (geu:SI (match_dup 1)
8ef30996
MM		 3527 (match_dup 2)))]
3528 ""
3529 "
3530{
3531 if (branch_type != CMP_SI)
3532 FAIL;
3533
3534 /* set up operands from compare. */
3535 operands[1] = branch_cmp[0];
3536 operands[2] = branch_cmp[1];
3537
bbdb5552 3538 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3539 {
3540 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
3541 DONE;
3542 }
3543
8ef30996
MM		 3544 /* fall through and generate default code */
3545}")
3546
3547(define_insn "sgeu_si"
3548 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3549 (geu:SI (match_operand:SI 1 "register_operand" "d")
8ef30996 3550 (match_operand:SI 2 "arith_operand" "dI")))]
bbdb5552 3551 "TARGET_DEBUG_C_MODE"
8ef30996
MM		 3552 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
3553 [(set_attr "type" "arith")
3554 (set_attr "mode" "SI")
3555 (set_attr "length" "2")])
3556
3557(define_split
3558 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 3559 (geu:SI (match_operand:SI 1 "register_operand" "")
8ef30996 3560 (match_operand:SI 2 "arith_operand" "")))]
bbdb5552 3561 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 3562 [(set (match_dup 0)
34b650b3 3563 (ltu:SI (match_dup 1)
8ef30996
MM		 3564 (match_dup 2)))
3565 (set (match_dup 0)
3566 (xor:SI (match_dup 0)
3567 (const_int 1)))]
3568 "")
3569
3570(define_expand "sltu"
3571 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3572 (ltu:SI (match_dup 1)
8ef30996
MM		 3573 (match_dup 2)))]
3574 ""
3575 "
3576{
3577 if (branch_type != CMP_SI)
3578 FAIL;
3579
3580 /* set up operands from compare. */
3581 operands[1] = branch_cmp[0];
3582 operands[2] = branch_cmp[1];
3583
bbdb5552 3584 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3585 {
3586 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
3587 DONE;
3588 }
3589
8ef30996
MM		 3590 /* fall through and generate default code */
3591}")
3592
3593(define_insn "sltu_si"
3594 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3595 (ltu:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 3596 (match_operand:SI 2 "arith_operand" "dI")))]
3597 ""
3598 "sltu\\t%0,%1,%2"
3599 [(set_attr "type" "arith")
3600 (set_attr "mode" "SI")
3601 (set_attr "length" "1")])
3602
3603(define_expand "sleu"
3604 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3605 (leu:SI (match_dup 1)
8ef30996
MM		 3606 (match_dup 2)))]
3607 ""
3608 "
3609{
8ef30996
MM		 3610 if (branch_type != CMP_SI)
3611 FAIL;
3612
3613 /* set up operands from compare. */
3614 operands[1] = branch_cmp[0];
3615 operands[2] = branch_cmp[1];
3616
bbdb5552 3617 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3618 {
3619 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
3620 DONE;
3621 }
3622
8ef30996
MM		 3623 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
3624 operands[2] = force_reg (SImode, operands[2]);
3625
3626 /* fall through and generate default code */
3627}")
3628
34b650b3
MM		 3629(define_insn "sleu_si_const"
3630 [(set (match_operand:SI 0 "register_operand" "=d")
3631 (leu:SI (match_operand:SI 1 "register_operand" "d")
3632 (match_operand:SI 2 "small_int" "I")))]
3633 "INTVAL (operands[2]) < 32767"
3634 "*
3635{
3636 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
3637 return \"sltu\\t%0,%1,%2\";
3638}"
3639 [(set_attr "type" "arith")
3640 (set_attr "mode" "SI")
3641 (set_attr "length" "1")])
3642
3643(define_insn "sleu_si_reg"
3644 [(set (match_operand:SI 0 "register_operand" "=d")
3645 (leu:SI (match_operand:SI 1 "register_operand" "d")
3646 (match_operand:SI 2 "register_operand" "d")))]
bbdb5552 3647 "TARGET_DEBUG_C_MODE"
34b650b3
MM		 3648 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
3649 [(set_attr "type" "arith")
3650 (set_attr "mode" "SI")
3651 (set_attr "length" "2")])
8ef30996
MM		 3652
3653(define_split
3654 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 3655 (leu:SI (match_operand:SI 1 "register_operand" "")
8ef30996 3656 (match_operand:SI 2 "register_operand" "")))]
bbdb5552 3657 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 3658 [(set (match_dup 0)
34b650b3 3659 (ltu:SI (match_dup 2)
8ef30996
MM		 3660 (match_dup 1)))
3661 (set (match_dup 0)
3662 (xor:SI (match_dup 0)
3663 (const_int 1)))]
3664 "")
3665
34b650b3
MM		 3666\f
3667;;
3668;; ....................
3669;;
3670;; FLOATING POINT COMPARISONS
3671;;
3672;; ....................
3673
3674(define_insn "seq_df"
3675 [(set (reg:CC_FP 66)
3676 (eq:CC_FP (match_operand:DF 0 "register_operand" "f")
3677 (match_operand:DF 1 "register_operand" "f")))]
3678 ""
3679 "*
3680{
3681 rtx xoperands[10];
3682 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3683 xoperands[1] = operands[0];
3684 xoperands[2] = operands[1];
3685
3686 return mips_fill_delay_slot (\"c.eq.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3687}"
3688 [(set_attr "type" "fcmp")
3689 (set_attr "mode" "FPSW")
3690 (set_attr "length" "1")])
3691
3692(define_insn "sne_df"
3693 [(set (reg:CC_REV_FP 66)
3694 (ne:CC_REV_FP (match_operand:DF 0 "register_operand" "f")
3695 (match_operand:DF 1 "register_operand" "f")))]
3696 ""
3697 "*
3698{
3699 rtx xoperands[10];
3700 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3701 xoperands[1] = operands[0];
3702 xoperands[2] = operands[1];
3703
3704 return mips_fill_delay_slot (\"c.eq.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3705}"
3706 [(set_attr "type" "fcmp")
3707 (set_attr "mode" "FPSW")
3708 (set_attr "length" "1")])
3709
3710(define_insn "slt_df"
3711 [(set (reg:CC_FP 66)
3712 (lt:CC_FP (match_operand:DF 0 "register_operand" "f")
3713 (match_operand:DF 1 "register_operand" "f")))]
3714 ""
3715 "*
3716{
3717 rtx xoperands[10];
3718 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3719 xoperands[1] = operands[0];
3720 xoperands[2] = operands[1];
3721
3722 return mips_fill_delay_slot (\"c.lt.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3723}"
3724 [(set_attr "type" "fcmp")
3725 (set_attr "mode" "FPSW")
3726 (set_attr "length" "1")])
3727
3728(define_insn "sle_df"
3729 [(set (reg:CC_FP 66)
3730 (le:CC_FP (match_operand:DF 0 "register_operand" "f")
3731 (match_operand:DF 1 "register_operand" "f")))]
3732 ""
3733 "*
3734{
3735 rtx xoperands[10];
3736 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3737 xoperands[1] = operands[0];
3738 xoperands[2] = operands[1];
3739
3740 return mips_fill_delay_slot (\"c.le.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3741}"
3742 [(set_attr "type" "fcmp")
3743 (set_attr "mode" "FPSW")
3744 (set_attr "length" "1")])
3745
3746(define_insn "sgt_df"
3747 [(set (reg:CC_FP 66)
3748 (gt:CC_FP (match_operand:DF 0 "register_operand" "f")
3749 (match_operand:DF 1 "register_operand" "f")))]
3750 ""
3751 "*
3752{
3753 rtx xoperands[10];
3754 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3755 xoperands[1] = operands[0];
3756 xoperands[2] = operands[1];
3757
3758 return mips_fill_delay_slot (\"c.lt.d\\t%1,%0\", DELAY_FCMP, xoperands, insn);
3759}"
3760 [(set_attr "type" "fcmp")
3761 (set_attr "mode" "FPSW")
3762 (set_attr "length" "1")])
3763
3764(define_insn "sge_df"
3765 [(set (reg:CC_FP 66)
3766 (ge:CC_FP (match_operand:DF 0 "register_operand" "f")
3767 (match_operand:DF 1 "register_operand" "f")))]
3768 ""
3769 "*
3770{
3771 rtx xoperands[10];
3772 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3773 xoperands[1] = operands[0];
3774 xoperands[2] = operands[1];
3775
3776 return mips_fill_delay_slot (\"c.le.d\\t%1,%0\", DELAY_FCMP, xoperands, insn);
3777}"
3778 [(set_attr "type" "fcmp")
3779 (set_attr "mode" "FPSW")
3780 (set_attr "length" "1")])
3781
3782(define_insn "seq_sf"
3783 [(set (reg:CC_FP 66)
3784 (eq:CC_FP (match_operand:SF 0 "register_operand" "f")
3785 (match_operand:SF 1 "register_operand" "f")))]
3786 ""
3787 "*
3788{
3789 rtx xoperands[10];
3790 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3791 xoperands[1] = operands[0];
3792 xoperands[2] = operands[1];
3793
3794 return mips_fill_delay_slot (\"c.eq.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3795}"
3796 [(set_attr "type" "fcmp")
3797 (set_attr "mode" "FPSW")
3798 (set_attr "length" "1")])
3799
3800(define_insn "sne_sf"
3801 [(set (reg:CC_REV_FP 66)
3802 (ne:CC_REV_FP (match_operand:SF 0 "register_operand" "f")
3803 (match_operand:SF 1 "register_operand" "f")))]
3804 ""
3805 "*
3806{
3807 rtx xoperands[10];
3808 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3809 xoperands[1] = operands[0];
3810 xoperands[2] = operands[1];
3811
3812 return mips_fill_delay_slot (\"c.eq.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3813}"
3814 [(set_attr "type" "fcmp")
3815 (set_attr "mode" "FPSW")
3816 (set_attr "length" "1")])
3817
3818(define_insn "slt_sf"
3819 [(set (reg:CC_FP 66)
3820 (lt:CC_FP (match_operand:SF 0 "register_operand" "f")
3821 (match_operand:SF 1 "register_operand" "f")))]
3822 ""
3823 "*
3824{
3825 rtx xoperands[10];
3826 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3827 xoperands[1] = operands[0];
3828 xoperands[2] = operands[1];
3829
3830 return mips_fill_delay_slot (\"c.lt.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3831}"
3832 [(set_attr "type" "fcmp")
3833 (set_attr "mode" "FPSW")
3834 (set_attr "length" "1")])
3835
3836(define_insn "sle_sf"
3837 [(set (reg:CC_FP 66)
3838 (le:CC_FP (match_operand:SF 0 "register_operand" "f")
3839 (match_operand:SF 1 "register_operand" "f")))]
3840 ""
3841 "*
3842{
3843 rtx xoperands[10];
3844 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3845 xoperands[1] = operands[0];
3846 xoperands[2] = operands[1];
3847
3848 return mips_fill_delay_slot (\"c.le.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3849}"
3850 [(set_attr "type" "fcmp")
3851 (set_attr "mode" "FPSW")
3852 (set_attr "length" "1")])
3853
3854(define_insn "sgt_sf"
3855 [(set (reg:CC_FP 66)
3856 (gt:CC_FP (match_operand:SF 0 "register_operand" "f")
3857 (match_operand:SF 1 "register_operand" "f")))]
3858 ""
3859 "*
3860{
3861 rtx xoperands[10];
3862 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3863 xoperands[1] = operands[0];
3864 xoperands[2] = operands[1];
3865
3866 return mips_fill_delay_slot (\"c.lt.s\\t%1,%0\", DELAY_FCMP, xoperands, insn);
3867}"
3868 [(set_attr "type" "fcmp")
3869 (set_attr "mode" "FPSW")
3870 (set_attr "length" "1")])
3871
3872(define_insn "sge_sf"
3873 [(set (reg:CC_FP 66)
3874 (ge:CC_FP (match_operand:SF 0 "register_operand" "f")
3875 (match_operand:SF 1 "register_operand" "f")))]
3876 ""
3877 "*
3878{
3879 rtx xoperands[10];
3880 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3881 xoperands[1] = operands[0];
3882 xoperands[2] = operands[1];
3883
3884 return mips_fill_delay_slot (\"c.le.s\\t%1,%0\", DELAY_FCMP, xoperands, insn);
3885}"
3886 [(set_attr "type" "fcmp")
3887 (set_attr "mode" "FPSW")
3888 (set_attr "length" "1")])
3889
8ef30996
MM		 3890\f
3891;;
3892;; ....................
3893;;
3894;; UNCONDITIONAL BRANCHES
3895;;
3896;; ....................
3897
3898;; Unconditional branches.
3899
3900(define_insn "jump"
3901 [(set (pc)
3902 (label_ref (match_operand 0 "" "")))]
3903 ""
3904 "*
3905{
3906 if (GET_CODE (operands[0]) == REG)
3907 return \"%*j\\t%0\";
3908 else
3909 return \"%*j\\t%l0\";
3910}"
3911 [(set_attr "type" "jump")
3912 (set_attr "mode" "none")
3913 (set_attr "length" "1")])
3914
3915(define_insn "indirect_jump"
3916 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
3917 ""
3918 "%*j\\t%0"
3919 [(set_attr "type" "jump")
3920 (set_attr "mode" "none")
3921 (set_attr "length" "1")])
3922
3923(define_insn "tablejump"
3924 [(set (pc)
3925 (match_operand:SI 0 "register_operand" "d"))
3926 (use (label_ref (match_operand 1 "" "")))]
3927 ""
3928 "%*j\\t%0"
3929 [(set_attr "type" "jump")
3930 (set_attr "mode" "none")
3931 (set_attr "length" "1")])
3932
3933;; Function return, only allow after optimization, so that we can
3934;; eliminate jumps to jumps if no stack space is used.
3935
0fb5ac6f
MM		 3936;; (define_expand "return"
3937;; [(set (pc) (reg:SI 31))]
3938;; "simple_epilogue_p ()"
3939;; "")
3940
3941(define_expand "return"
3942 [(parallel [(return)
3943 (use (reg:SI 31))])]
3944 "simple_epilogue_p ()"
3945 "")
3946
3947(define_insn "return_internal"
3948 [(parallel [(return)
3949 (use (match_operand:SI 0 "register_operand" "d"))])]
3950 ""
3951 "%*j\\t%0"
8ef30996
MM		 3952 [(set_attr "type" "jump")
3953 (set_attr "mode" "none")
3954 (set_attr "length" "1")])
3955
0fb5ac6f
MM		 3956\f
3957;;
3958;; ....................
3959;;
3960;; Function prologue/epilogue
3961;;
3962;; ....................
3963;;
3964
3965(define_expand "prologue"
3966 [(const_int 1)]
3967 ""
3968 "
3969{
3970 if (mips_isa >= 0) /* avoid unused code warnings */
3971 {
3972 mips_expand_prologue ();
3973 DONE;
3974 }
3975}")
3976
3977;; At present, don't expand the epilogue, reorg.c will clobber the
3978;; return register in compiling gen_lowpart (emit-rtl.c).
3979;;
3980;; (define_expand "epilogue"
3981;; [(const_int 2)]
3982;; ""
3983;; "
3984;; {
3985;; if (mips_isa >= 0) /* avoid unused code warnings */
3986;; {
3987;; mips_expand_epilogue ();
3988;; DONE;
3989;; }
3990;; }")
3991
8ef30996
MM		 3992\f
3993;;
3994;; ....................
3995;;
3996;; FUNCTION CALLS
3997;;
3998;; ....................
3999
4000;; calls.c now passes a third argument, make saber happy
4001
4002(define_expand "call"
af4a697f 4003 [(parallel [(call (match_operand 0 "memory_operand" "m")
8ef30996
MM		 4004 (match_operand 1 "" "i"))
4005 (clobber (match_operand 2 "" ""))])] ;; overwrite op2 with $31
4006 ""
4007 "
4008{
4009 rtx addr;
4010
4011 operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4012
4013 addr = XEXP (operands[0], 0);
af4a697f 4014 if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
8ef30996
MM		 4015 XEXP (operands[0], 0) = force_reg (FUNCTION_MODE, addr);
4016}")
4017
4018(define_insn "call_internal"
af4a697f 4019 [(call (match_operand 0 "memory_operand" "m")
8ef30996
MM		 4020 (match_operand 1 "" "i"))
4021 (clobber (match_operand:SI 2 "register_operand" "=d"))]
4022 ""
4023 "*
4024{
4025 register rtx target = XEXP (operands[0], 0);
4026
4027 if (GET_CODE (target) == SYMBOL_REF)
4028 return \"%*jal\\t%0\";
4029
2bba3a75
MM		 4030 else if (GET_CODE (target) == CONST_INT)
4031 {
4032 operands[0] = target;
4033 operands[1] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4034 return \"%*%[li\\t%@,%0\\n\\tjal\\t%1,%@%]\";
4035 }
4036
8ef30996
MM		 4037 else
4038 {
4039 operands[0] = target;
4040 operands[1] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4041 return \"%*jal\\t%1,%0\";
4042 }
4043}"
4044 [(set_attr "type" "call")
4045 (set_attr "mode" "none")
4046 (set_attr "length" "1")])
4047
4048;; calls.c now passes a fourth argument, make saber happy
4049
4050(define_expand "call_value"
4051 [(parallel [(set (match_operand 0 "register_operand" "=df")
af4a697f 4052 (call (match_operand 1 "memory_operand" "m")
8ef30996
MM		 4053 (match_operand 2 "" "i")))
4054 (clobber (match_operand 3 "" ""))])] ;; overwrite op3 with $31
4055 ""
4056 "
4057{
4058 rtx addr;
4059
4060 operands[3] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4061
4062 addr = XEXP (operands[1], 0);
af4a697f 4063 if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
8ef30996
MM		 4064 XEXP (operands[1], 0) = force_reg (FUNCTION_MODE, addr);
4065}")
4066
4067(define_insn "call_value_internal"
4068 [(set (match_operand 0 "register_operand" "=df")
af4a697f 4069 (call (match_operand 1 "memory_operand" "m")
8ef30996
MM		 4070 (match_operand 2 "" "i")))
4071 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4072 ""
4073 "*
4074{
4075 register rtx target = XEXP (operands[1], 0);
4076
4077 if (GET_CODE (target) == SYMBOL_REF)
4078 return \"%*jal\\t%1\";
4079
2bba3a75
MM		 4080 else if (GET_CODE (target) == CONST_INT)
4081 {
4082 operands[1] = target;
4083 operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4084 return \"%*%[li\\t%@,%1\\n\\tjal\\t%2,%@%]\";
4085 }
4086
8ef30996
MM		 4087 else
4088 {
4089 operands[1] = target;
4090 operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4091 return \"%*jal\\t%2,%1\";
4092 }
4093}"
4094 [(set_attr "type" "call")
4095 (set_attr "mode" "none")
4096 (set_attr "length" "1")])
4097
4098\f
4099;;
4100;; ....................
4101;;
4102;; MISC.
4103;;
4104;; ....................
4105;;
4106
4107(define_insn "nop"
4108 [(const_int 0)]
4109 ""
4110 "%(nop%)"
4111 [(set_attr "type" "nop")
4112 (set_attr "mode" "none")
4113 (set_attr "length" "1")])
4114
4115(define_expand "probe"
4116 [(set (match_dup 0)
4117 (match_dup 1))]
4118 ""
4119 "
4120{
4121 operands[0] = gen_reg_rtx (SImode);
4122 operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx);
4123 MEM_VOLATILE_P (operands[1]) = TRUE;
4124
4125 /* fall through and generate default code */
4126}")
4127
4128\f
4129;;
4130;; Local variables:
4131;; mode:emacs-lisp
4132;; comment-start: ";; "
4133;; eval: (set-syntax-table (copy-sequence (syntax-table)))
4134;; eval: (modify-syntax-entry ?[ "(]")
4135;; eval: (modify-syntax-entry ?] ")[")
4136;; eval: (modify-syntax-entry ?{ "(}")
4137;; eval: (modify-syntax-entry ?} "){")
4138;; End:
GNU Compiler Collection
This page took 0.70233 seconds and 5 git commands to generate.