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Add #undef for everything we define; a few were missing.
[gcc.git] / gcc / config / mips / mips.md
CommitLineData
8ef30996
MM		 1;; Mips.md Machine Description for MIPS based processors
2;; Contributed by A. Lichnewsky, lich@inria.inria.fr
3;; Changes by Michael Meissner, meissner@osf.org
bb621ad7
JW		 4;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
5;; Brendan Eich, brendan@microunity.com.
6;; Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
8ef30996
MM		 7
8;; This file is part of GNU CC.
9
10;; GNU CC is free software; you can redistribute it and/or modify
11;; it under the terms of the GNU General Public License as published by
12;; the Free Software Foundation; either version 2, or (at your option)
13;; any later version.
14
15;; GNU CC is distributed in the hope that it will be useful,
16;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18;; GNU General Public License for more details.
19
20;; You should have received a copy of the GNU General Public License
21;; along with GNU CC; see the file COPYING. If not, write to
22;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23
24\f
25
26;; ....................
27;;
28;; Attributes
29;;
30;; ....................
31
32;; Classification of each insn.
33;; branch conditional branch
34;; jump unconditional jump
35;; call unconditional call
36;; load load instruction(s)
37;; store store instruction(s)
38;; move data movement within same register set
39;; xfer transfer to/from coprocessor
40;; hilo transfer of hi/lo registers
41;; arith integer arithmetic instruction
42;; darith double precision integer arithmetic instructions
43;; imul integer multiply
44;; idiv integer divide
45;; icmp integer compare
46;; fadd floating point add/subtract
47;; fmul floating point multiply
48;; fdiv floating point divide
49;; fabs floating point absolute value
50;; fneg floating point negation
51;; fcmp floating point compare
52;; fcvt floating point convert
53;; fsqrt floating point square root
54;; multi multiword sequence (or user asm statements)
55;; nop no operation
8ef30996
MM		 56
57(define_attr "type"
c7343333 58 "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
8ef30996
MM		 59 (const_string "unknown"))
60
61;; Main data type used by the insn
34b650b3 62(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
8ef30996
MM		 63
64;; # instructions (4 bytes each)
65(define_attr "length" "" (const_int 1))
66
6d518002 67;; whether or not an instruction has a mandatory delay slot
8ef30996 68(define_attr "dslot" "no,yes"
c7343333 69 (if_then_else (eq_attr "type" "branch,jump,call,load,xfer,hilo,fcmp")
8ef30996
MM		 70 (const_string "yes")
71 (const_string "no")))
72
ddd8ab48
MM		 73;; Attribute describing the processor. This attribute must match exactly
74;; with the processor_type enumeration in mips.h.
75
8ef30996 76;; Attribute describing the processor
ddd8ab48
MM		 77;; (define_attr "cpu" "default,r3000,r6000,r4000"
78;; (const
79;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
80;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
81;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
82;; (const_string "default"))))
83
bb621ad7 84(define_attr "cpu" "default,r3000,r6000,r4000,r4600"
ddd8ab48 85 (const (symbol_ref "mips_cpu_attr")))
8ef30996
MM		 86
87;; Attribute defining whether or not we can use the branch-likely instructions
88;; (MIPS ISA level 2)
89
90(define_attr "branch_likely" "no,yes"
6d518002 91 (const
8ef30996
MM		 92 (if_then_else (ge (symbol_ref "mips_isa") (const_int 2))
93 (const_string "yes")
6d518002 94 (const_string "no"))))
8ef30996
MM		 95
96
97;; Describe a user's asm statement.
98(define_asm_attributes
99 [(set_attr "type" "multi")])
100
84a92af4
JW		 101;; whether or not generating calls to position independent functions
102(define_attr "abicalls" "no,yes"
e0a4e5a5 103 (const (symbol_ref "mips_abicalls_attr")))
84a92af4 104
8ef30996
MM		 105\f
106
107;; .........................
108;;
109;; Delay slots, can't describe load/fcmp/xfer delay slots here
110;;
111;; .........................
112
113(define_delay (eq_attr "type" "branch")
114 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
115 (nil)
bbdb5552 116 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))])
8ef30996 117
84a92af4
JW		 118(define_delay (eq_attr "type" "jump")
119 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
120 (nil)
121 (nil)])
122
123(define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no"))
8ef30996
MM		 124 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
125 (nil)
126 (nil)])
127
128\f
129
130;; .........................
131;;
132;; Functional units
133;;
134;; .........................
135
136; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
c8e18a2b 137; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
8ef30996
MM		 138
139;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
140
141(define_function_unit "memory" 1 0
c7343333 142 (and (eq_attr "type" "load") (eq_attr "cpu" "!r3000"))
8ef30996
MM		 143 3 0)
144
145(define_function_unit "memory" 1 0
bb621ad7 146 (and (eq_attr "type" "load") (eq_attr "cpu" "r3000,r4600"))
8ef30996
MM		 147 2 0)
148
ddd8ab48 149(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
8ef30996 150
c3f3d7e1 151(define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
8ef30996 152
bb621ad7
JW		 153(define_function_unit "imuldiv" 1 0
154 (eq_attr "type" "hilo")
155 1 3)
156
157(define_function_unit "imuldiv" 1 0
158 (and (eq_attr "type" "imul") (eq_attr "cpu" "!r3000,r4000,r4600"))
159 17 17)
8ef30996 160
bb621ad7 161(define_function_unit "imuldiv" 1 0
8ef30996 162 (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000"))
bb621ad7 163 12 12)
8ef30996 164
bb621ad7
JW		 165(define_function_unit "imuldiv" 1 0
166 (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000,r4600"))
167 10 10)
8ef30996 168
bb621ad7
JW		 169(define_function_unit "imuldiv" 1 0
170 (and (eq_attr "type" "idiv") (eq_attr "cpu" "!r3000,r4000,r4600"))
171 38 38)
8ef30996 172
bb621ad7 173(define_function_unit "imuldiv" 1 0
8ef30996 174 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000"))
bb621ad7
JW		 175 35 35)
176
177(define_function_unit "imuldiv" 1 0
178 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
179 42 42)
8ef30996 180
bb621ad7 181(define_function_unit "imuldiv" 1 0
8ef30996 182 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
bb621ad7
JW		 183 69 69)
184
185(define_function_unit "adder" 1 1
186 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r6000"))
187 3 0)
188
189(define_function_unit "adder" 1 1
190 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r6000"))
191 2 0)
8ef30996
MM		 192
193(define_function_unit "adder" 1 1
194 (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r6000"))
c8e18a2b 195 4 0)
8ef30996
MM		 196
197(define_function_unit "adder" 1 1
198 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000"))
c8e18a2b 199 2 0)
8ef30996
MM		 200
201(define_function_unit "adder" 1 1
202 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
c8e18a2b 203 3 0)
8ef30996 204
ddd8ab48 205(define_function_unit "adder" 1 1
bb621ad7 206 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "!r3000,r4600"))
c8e18a2b 207 2 0)
8ef30996 208
ddd8ab48 209(define_function_unit "adder" 1 1
bb621ad7 210 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r4600"))
c8e18a2b 211 1 0)
8ef30996
MM		 212
213(define_function_unit "mult" 1 1
bb621ad7 214 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r3000,r6000,r4600")))
c8e18a2b 215 7 0)
8ef30996
MM		 216
217(define_function_unit "mult" 1 1
218 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
c8e18a2b 219 4 0)
8ef30996
MM		 220
221(define_function_unit "mult" 1 1
222 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
c8e18a2b 223 5 0)
8ef30996 224
bb621ad7
JW		 225(define_function_unit "mult" 1 1
226 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
227 8 0)
228
8ef30996
MM		 229(define_function_unit "mult" 1 1
230 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r6000")))
c8e18a2b 231 8 0)
8ef30996
MM		 232
233(define_function_unit "mult" 1 1
234 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
c8e18a2b 235 5 0)
8ef30996
MM		 236
237(define_function_unit "mult" 1 1
238 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
c8e18a2b 239 6 0)
8ef30996
MM		 240
241(define_function_unit "divide" 1 1
bb621ad7 242 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r3000,r6000,r4600")))
c8e18a2b 243 23 0)
8ef30996
MM		 244
245(define_function_unit "divide" 1 1
246 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
c8e18a2b 247 12 0)
8ef30996
MM		 248
249(define_function_unit "divide" 1 1
250 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
c8e18a2b 251 15 0)
8ef30996
MM		 252
253(define_function_unit "divide" 1 1
bb621ad7
JW		 254 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
255 32 0)
256
257(define_function_unit "divide" 1 1
258 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r6000,r4600")))
c8e18a2b 259 36 0)
8ef30996
MM		 260
261(define_function_unit "divide" 1 1
262 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
c8e18a2b 263 19 0)
8ef30996
MM		 264
265(define_function_unit "divide" 1 1
266 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
c8e18a2b 267 16 0)
8ef30996 268
bb621ad7
JW		 269(define_function_unit "divide" 1 1
270 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600")))
271 61 0)
272
273;;; ??? Is this number right?
274(define_function_unit "divide" 1 1
275 (and (eq_attr "type" "fsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600")))
276 54 0)
277(define_function_unit "divide" 1 1
278 (and (eq_attr "type" "fsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
279 31 0)
280
281;;; ??? Is this number right?
282(define_function_unit "divide" 1 1
283 (and (eq_attr "type" "fsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600")))
284 112 0)
285(define_function_unit "divide" 1 1
286 (and (eq_attr "type" "fsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600")))
287 60 0)
8ef30996 288
ddd8ab48
MM		 289\f
290;; The following functional units do not use the cpu type, and use
291;; much less memory in genattrtab.c.
292
c8e18a2b
TW		 293;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
294;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
ddd8ab48 295;;
c8e18a2b 296;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
ddd8ab48 297;;
c8e18a2b
TW		 298;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
299;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
ddd8ab48 300;;
c8e18a2b
TW		 301;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
302;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
ddd8ab48 303;;
c8e18a2b
TW		 304;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
305;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
ddd8ab48 306;;
c8e18a2b
TW		 307;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
308;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
ddd8ab48 309;;
c8e18a2b
TW		 310;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
311;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
ddd8ab48 312;;
c8e18a2b
TW		 313;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
314;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
ddd8ab48 315
8ef30996
MM		 316\f
317;;
318;; ....................
319;;
320;; ADDITION
321;;
322;; ....................
323;;
324
325(define_insn "adddf3"
326 [(set (match_operand:DF 0 "register_operand" "=f")
327 (plus:DF (match_operand:DF 1 "register_operand" "f")
328 (match_operand:DF 2 "register_operand" "f")))]
329 "TARGET_HARD_FLOAT"
330 "add.d\\t%0,%1,%2"
331 [(set_attr "type" "fadd")
332 (set_attr "mode" "DF")
333 (set_attr "length" "1")])
334
335(define_insn "addsf3"
336 [(set (match_operand:SF 0 "register_operand" "=f")
337 (plus:SF (match_operand:SF 1 "register_operand" "f")
338 (match_operand:SF 2 "register_operand" "f")))]
339 "TARGET_HARD_FLOAT"
340 "add.s\\t%0,%1,%2"
341 [(set_attr "type" "fadd")
342 (set_attr "mode" "SF")
343 (set_attr "length" "1")])
344
71cd5224 345(define_expand "addsi3"
8ef30996 346 [(set (match_operand:SI 0 "register_operand" "=d")
71cd5224 347 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
8ef30996
MM		 348 (match_operand:SI 2 "arith_operand" "dI")))]
349 ""
71cd5224
RS		 350 "
351{
352 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
353 operands[2] = force_reg (SImode, operands[2]);
354}")
355
356(define_insn "addsi3_internal"
357 [(set (match_operand:SI 0 "register_operand" "=d")
358 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
359 (match_operand:SI 2 "arith_operand" "dI")))]
360 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768"
9b190d1c 361 "addu\\t%0,%z1,%2"
8ef30996
MM		 362 [(set_attr "type" "arith")
363 (set_attr "mode" "SI")
364 (set_attr "length" "1")])
365
366(define_expand "adddi3"
367 [(parallel [(set (match_operand:DI 0 "register_operand" "")
368 (plus:DI (match_operand:DI 1 "register_operand" "")
369 (match_operand:DI 2 "arith_operand" "")))
370 (clobber (match_dup 3))])]
bb621ad7 371 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
92b4cee1
MM		 372 "
373{
374 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
b0565769 375 operands[2] = force_reg (DImode, operands[2]);
92b4cee1 376
bb621ad7
JW		 377 if (TARGET_64BIT)
378 {
379 emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
380 operands[2]));
381 DONE;
382 }
383
92b4cee1
MM		 384 operands[3] = gen_reg_rtx (SImode);
385}")
8ef30996
MM		 386
387(define_insn "adddi3_internal_1"
388 [(set (match_operand:DI 0 "register_operand" "=d,&d")
389 (plus:DI (match_operand:DI 1 "register_operand" "0,d")
390 (match_operand:DI 2 "register_operand" "d,d")))
391 (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
bb621ad7 392 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
8ef30996
MM		 393 "*
394{
395 return (REGNO (operands[0]) == REGNO (operands[1])
396 && REGNO (operands[0]) == REGNO (operands[2]))
397 ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
398 : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
399}"
92b4cee1
MM		 400 [(set_attr "type" "darith")
401 (set_attr "mode" "DI")
402 (set_attr "length" "4")])
8ef30996
MM		 403
404(define_split
405 [(set (match_operand:DI 0 "register_operand" "")
406 (plus:DI (match_operand:DI 1 "register_operand" "")
407 (match_operand:DI 2 "register_operand" "")))
408 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 409 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 410 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
411 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
412 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
413 && (REGNO (operands[0]) != REGNO (operands[1])
414 || REGNO (operands[0]) != REGNO (operands[2]))"
415
416 [(set (subreg:SI (match_dup 0) 0)
417 (plus:SI (subreg:SI (match_dup 1) 0)
418 (subreg:SI (match_dup 2) 0)))
419
420 (set (match_dup 3)
34b650b3 421 (ltu:SI (subreg:SI (match_dup 0) 0)
8ef30996
MM		 422 (subreg:SI (match_dup 2) 0)))
423
424 (set (subreg:SI (match_dup 0) 1)
425 (plus:SI (subreg:SI (match_dup 1) 1)
426 (subreg:SI (match_dup 2) 1)))
427
428 (set (subreg:SI (match_dup 0) 1)
429 (plus:SI (subreg:SI (match_dup 0) 1)
430 (match_dup 3)))]
431 "")
432
433(define_split
434 [(set (match_operand:DI 0 "register_operand" "")
435 (plus:DI (match_operand:DI 1 "register_operand" "")
436 (match_operand:DI 2 "register_operand" "")))
437 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 438 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 439 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
440 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
441 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
442 && (REGNO (operands[0]) != REGNO (operands[1])
443 || REGNO (operands[0]) != REGNO (operands[2]))"
444
445 [(set (subreg:SI (match_dup 0) 1)
446 (plus:SI (subreg:SI (match_dup 1) 1)
447 (subreg:SI (match_dup 2) 1)))
448
449 (set (match_dup 3)
34b650b3 450 (ltu:SI (subreg:SI (match_dup 0) 1)
8ef30996
MM		 451 (subreg:SI (match_dup 2) 1)))
452
453 (set (subreg:SI (match_dup 0) 0)
454 (plus:SI (subreg:SI (match_dup 1) 0)
455 (subreg:SI (match_dup 2) 0)))
456
457 (set (subreg:SI (match_dup 0) 0)
458 (plus:SI (subreg:SI (match_dup 0) 0)
459 (match_dup 3)))]
460 "")
461
462(define_insn "adddi3_internal_2"
463 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
464 (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
465 (match_operand:DI 2 "small_int" "P,J,N")))
466 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
bb621ad7 467 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
8ef30996
MM		 468 "@
469 addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
470 move\\t%L0,%L1\;move\\t%M0,%M1
471 subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
92b4cee1
MM		 472 [(set_attr "type" "darith")
473 (set_attr "mode" "DI")
8ef30996
MM		 474 (set_attr "length" "3,2,4")])
475
476(define_split
477 [(set (match_operand:DI 0 "register_operand" "")
478 (plus:DI (match_operand:DI 1 "register_operand" "")
479 (match_operand:DI 2 "small_int" "")))
480 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 481 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 482 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
483 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
484 && INTVAL (operands[2]) > 0"
485
486 [(set (subreg:SI (match_dup 0) 0)
487 (plus:SI (subreg:SI (match_dup 1) 0)
488 (match_dup 2)))
489
490 (set (match_dup 3)
34b650b3 491 (ltu:SI (subreg:SI (match_dup 0) 0)
8ef30996
MM		 492 (match_dup 2)))
493
494 (set (subreg:SI (match_dup 0) 1)
495 (plus:SI (subreg:SI (match_dup 1) 1)
496 (match_dup 3)))]
497 "")
498
499(define_split
500 [(set (match_operand:DI 0 "register_operand" "")
501 (plus:DI (match_operand:DI 1 "register_operand" "")
502 (match_operand:DI 2 "small_int" "")))
503 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 504 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 505 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
506 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
507 && INTVAL (operands[2]) > 0"
508
509 [(set (subreg:SI (match_dup 0) 1)
510 (plus:SI (subreg:SI (match_dup 1) 1)
511 (match_dup 2)))
512
513 (set (match_dup 3)
34b650b3 514 (ltu:SI (subreg:SI (match_dup 0) 1)
8ef30996
MM		 515 (match_dup 2)))
516
517 (set (subreg:SI (match_dup 0) 0)
518 (plus:SI (subreg:SI (match_dup 1) 0)
519 (match_dup 3)))]
520 "")
bb621ad7
JW		 521
522(define_insn "adddi3_internal_3"
523 [(set (match_operand:DI 0 "register_operand" "=d")
524 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ")
525 (match_operand:DI 2 "arith_operand" "dI")))]
526 "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
527 "*
528{
529 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
530 ? \"dsubu\\t%0,%z1,%n2\"
531 : \"daddu\\t%0,%z1,%2\";
532}"
533 [(set_attr "type" "darith")
534 (set_attr "mode" "DI")
535 (set_attr "length" "1")])
536
537
538(define_insn "addsi3_internal_2"
539 [(set (match_operand:DI 0 "register_operand" "=d")
540 (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
541 (match_operand:SI 2 "arith_operand" "dI"))))]
542 "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
543 "*
544{
545 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
546 ? \"subu\\t%0,%z1,%n2\"
547 : \"addu\\t%0,%z1,%2\";
548}"
549 [(set_attr "type" "arith")
550 (set_attr "mode" "SI")
551 (set_attr "length" "1")])
552
8ef30996
MM		 553\f
554;;
555;; ....................
556;;
557;; SUBTRACTION
558;;
559;; ....................
560;;
561
562(define_insn "subdf3"
563 [(set (match_operand:DF 0 "register_operand" "=f")
564 (minus:DF (match_operand:DF 1 "register_operand" "f")
565 (match_operand:DF 2 "register_operand" "f")))]
566 "TARGET_HARD_FLOAT"
567 "sub.d\\t%0,%1,%2"
568 [(set_attr "type" "fadd")
569 (set_attr "mode" "DF")
570 (set_attr "length" "1")])
571
572(define_insn "subsf3"
573 [(set (match_operand:SF 0 "register_operand" "=f")
574 (minus:SF (match_operand:SF 1 "register_operand" "f")
575 (match_operand:SF 2 "register_operand" "f")))]
576 "TARGET_HARD_FLOAT"
577 "sub.s\\t%0,%1,%2"
578 [(set_attr "type" "fadd")
579 (set_attr "mode" "SF")
580 (set_attr "length" "1")])
581
71cd5224 582(define_expand "subsi3"
8ef30996
MM		 583 [(set (match_operand:SI 0 "register_operand" "=d")
584 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
585 (match_operand:SI 2 "arith_operand" "dI")))]
586 ""
71cd5224
RS		 587 "
588{
589 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
590 operands[2] = force_reg (SImode, operands[2]);
591}")
592
593(define_insn "subsi3_internal"
594 [(set (match_operand:SI 0 "register_operand" "=d")
595 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
596 (match_operand:SI 2 "arith_operand" "dI")))]
597 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768"
9b190d1c 598 "subu\\t%0,%z1,%2"
8ef30996
MM		 599 [(set_attr "type" "arith")
600 (set_attr "mode" "SI")
601 (set_attr "length" "1")])
602
603(define_expand "subdi3"
604 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
605 (minus:DI (match_operand:DI 1 "register_operand" "d")
606 (match_operand:DI 2 "register_operand" "d")))
607 (clobber (match_dup 3))])]
bb621ad7
JW		 608 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
609 "
610{
611 if (TARGET_64BIT)
612 {
613 emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
614 operands[2]));
615 DONE;
616 }
617
618 operands[3] = gen_reg_rtx (SImode);
619}")
8ef30996
MM		 620
621(define_insn "subdi3_internal"
622 [(set (match_operand:DI 0 "register_operand" "=d")
623 (minus:DI (match_operand:DI 1 "register_operand" "d")
624 (match_operand:DI 2 "register_operand" "d")))
625 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 626 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
8ef30996
MM		 627 "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
628 [(set_attr "type" "darith")
629 (set_attr "mode" "DI")
630 (set_attr "length" "4")])
631
632(define_split
633 [(set (match_operand:DI 0 "register_operand" "")
634 (minus:DI (match_operand:DI 1 "register_operand" "")
635 (match_operand:DI 2 "register_operand" "")))
636 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 637 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 638 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
639 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
640 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
641
642 [(set (match_dup 3)
34b650b3 643 (ltu:SI (subreg:SI (match_dup 1) 0)
6d518002 644 (subreg:SI (match_dup 2) 0)))
8ef30996
MM		 645
646 (set (subreg:SI (match_dup 0) 0)
647 (minus:SI (subreg:SI (match_dup 1) 0)
648 (subreg:SI (match_dup 2) 0)))
649
650 (set (subreg:SI (match_dup 0) 1)
651 (minus:SI (subreg:SI (match_dup 1) 1)
652 (subreg:SI (match_dup 2) 1)))
653
654 (set (subreg:SI (match_dup 0) 1)
655 (minus:SI (subreg:SI (match_dup 0) 1)
656 (match_dup 3)))]
657 "")
658
659(define_split
660 [(set (match_operand:DI 0 "register_operand" "")
661 (minus:DI (match_operand:DI 1 "register_operand" "")
662 (match_operand:DI 2 "register_operand" "")))
663 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 664 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 665 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
666 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
667 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
668
669 [(set (match_dup 3)
34b650b3 670 (ltu:SI (subreg:SI (match_dup 1) 1)
6d518002 671 (subreg:SI (match_dup 2) 1)))
8ef30996
MM		 672
673 (set (subreg:SI (match_dup 0) 1)
674 (minus:SI (subreg:SI (match_dup 1) 1)
675 (subreg:SI (match_dup 2) 1)))
676
677 (set (subreg:SI (match_dup 0) 0)
678 (minus:SI (subreg:SI (match_dup 1) 0)
679 (subreg:SI (match_dup 2) 0)))
680
681 (set (subreg:SI (match_dup 0) 0)
682 (minus:SI (subreg:SI (match_dup 0) 0)
683 (match_dup 3)))]
684 "")
685
686(define_insn "subdi3_internal_2"
687 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
688 (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
689 (match_operand:DI 2 "small_int" "P,J,N")))
690 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
bb621ad7 691 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
8ef30996
MM		 692 "@
693 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
694 move\\t%L0,%L1\;move\\t%M0,%M1
695 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
92b4cee1
MM		 696 [(set_attr "type" "darith")
697 (set_attr "mode" "DI")
8ef30996
MM		 698 (set_attr "length" "3,2,4")])
699
700(define_split
701 [(set (match_operand:DI 0 "register_operand" "")
702 (minus:DI (match_operand:DI 1 "register_operand" "")
703 (match_operand:DI 2 "small_int" "")))
704 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 705 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 706 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
707 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
708 && INTVAL (operands[2]) > 0"
709
710 [(set (match_dup 3)
34b650b3 711 (ltu:SI (subreg:SI (match_dup 1) 0)
8ef30996
MM		 712 (match_dup 2)))
713
714 (set (subreg:SI (match_dup 0) 0)
715 (minus:SI (subreg:SI (match_dup 1) 0)
716 (match_dup 2)))
717
718 (set (subreg:SI (match_dup 0) 1)
719 (minus:SI (subreg:SI (match_dup 1) 1)
720 (match_dup 3)))]
721 "")
722
723(define_split
724 [(set (match_operand:DI 0 "register_operand" "")
725 (minus:DI (match_operand:DI 1 "register_operand" "")
726 (match_operand:DI 2 "small_int" "")))
727 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 728 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 729 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
730 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
731 && INTVAL (operands[2]) > 0"
732
733 [(set (match_dup 3)
34b650b3 734 (ltu:SI (subreg:SI (match_dup 1) 1)
8ef30996
MM		 735 (match_dup 2)))
736
737 (set (subreg:SI (match_dup 0) 1)
738 (minus:SI (subreg:SI (match_dup 1) 1)
739 (match_dup 2)))
740
741 (set (subreg:SI (match_dup 0) 0)
742 (minus:SI (subreg:SI (match_dup 1) 0)
743 (match_dup 3)))]
744 "")
745
bb621ad7
JW		 746(define_insn "subdi3_internal_3"
747 [(set (match_operand:DI 0 "register_operand" "=d")
748 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ")
749 (match_operand:DI 2 "arith_operand" "dI")))]
750 "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
751 "*
752{
753 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
754 ? \"daddu\\t%0,%z1,%n2\"
755 : \"dsubu\\t%0,%z1,%2\";
756}"
757 [(set_attr "type" "darith")
758 (set_attr "mode" "DI")
759 (set_attr "length" "1")])
760
761
762(define_insn "subsi3_internal_2"
763 [(set (match_operand:DI 0 "register_operand" "=d")
764 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
765 (match_operand:SI 2 "arith_operand" "dI"))))]
766 "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
767 "*
768{
769 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
770 ? \"addu\\t%0,%z1,%n2\"
771 : \"subu\\t%0,%z1,%2\";
772}"
773 [(set_attr "type" "arith")
774 (set_attr "mode" "DI")
775 (set_attr "length" "1")])
776
8ef30996
MM		 777\f
778;;
779;; ....................
780;;
781;; MULTIPLICATION
782;;
783;; ....................
784;;
785
786(define_insn "muldf3"
787 [(set (match_operand:DF 0 "register_operand" "=f")
788 (mult:DF (match_operand:DF 1 "register_operand" "f")
789 (match_operand:DF 2 "register_operand" "f")))]
790 "TARGET_HARD_FLOAT"
791 "mul.d\\t%0,%1,%2"
792 [(set_attr "type" "fmul")
793 (set_attr "mode" "DF")
794 (set_attr "length" "1")])
795
796(define_insn "mulsf3"
797 [(set (match_operand:SF 0 "register_operand" "=f")
798 (mult:SF (match_operand:SF 1 "register_operand" "f")
799 (match_operand:SF 2 "register_operand" "f")))]
800 "TARGET_HARD_FLOAT"
801 "mul.s\\t%0,%1,%2"
802 [(set_attr "type" "fmul")
803 (set_attr "mode" "SF")
804 (set_attr "length" "1")])
805
806(define_insn "mulsi3"
807 [(set (match_operand:SI 0 "register_operand" "=d")
808 (mult:SI (match_operand:SI 1 "register_operand" "d")
809 (match_operand:SI 2 "register_operand" "d")))
810 (clobber (reg:SI 64))
811 (clobber (reg:SI 65))]
812 ""
813 "*
814{
815 rtx xoperands[10];
816
817 xoperands[0] = operands[0];
818 xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM);
819
820 output_asm_insn (\"mult\\t%1,%2\", operands);
bb621ad7 821 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
8ef30996
MM		 822 return \"\";
823}"
824 [(set_attr "type" "imul")
825 (set_attr "mode" "SI")
826 (set_attr "length" "3")]) ;; mult + mflo + delay
827
bb621ad7
JW		 828;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
829;; a multiply is in progress, it may give an incorrect result. We solve
830;; this by not splitting on the r4000.
831
8ef30996
MM		 832(define_split
833 [(set (match_operand:SI 0 "register_operand" "")
834 (mult:SI (match_operand:SI 1 "register_operand" "")
835 (match_operand:SI 2 "register_operand" "")))
836 (clobber (reg:SI 64))
837 (clobber (reg:SI 65))]
bb621ad7 838 "!TARGET_DEBUG_D_MODE && mips_cpu != PROCESSOR_R4000"
8ef30996
MM		 839 [(parallel [(set (reg:SI 65) ;; low register
840 (mult:SI (match_dup 1)
841 (match_dup 2)))
842 (clobber (reg:SI 64))])
843 (set (match_dup 0)
844 (reg:SI 65))]
845 "")
846
847(define_insn "mulsi3_internal"
848 [(set (reg:SI 65) ;; low register
849 (mult:SI (match_operand:SI 0 "register_operand" "d")
850 (match_operand:SI 1 "register_operand" "d")))
851 (clobber (reg:SI 64))]
852 ""
853 "mult\\t%0,%1"
854 [(set_attr "type" "imul")
855 (set_attr "mode" "SI")
856 (set_attr "length" "1")])
857
bb621ad7
JW		 858(define_insn "muldi3"
859 [(set (match_operand:DI 0 "register_operand" "=d")
860 (mult:DI (match_operand:DI 1 "register_operand" "d")
861 (match_operand:DI 2 "register_operand" "d")))
862 (clobber (reg:DI 64))
863 (clobber (reg:DI 65))]
864 "TARGET_64BIT"
865 "*
866{
867 rtx xoperands[10];
868
869 xoperands[0] = operands[0];
870 xoperands[1] = gen_rtx (REG, DImode, LO_REGNUM);
871
872 output_asm_insn (\"dmult\\t%1,%2\", operands);
873 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
874 return \"\";
875}"
876 [(set_attr "type" "imul")
877 (set_attr "mode" "DI")
878 (set_attr "length" "3")]) ;; mult + mflo + delay
879
880;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
881;; a multiply is in progress, it may give an incorrect result. We solve
882;; this by not splitting on the r4000.
883
884(define_split
885 [(set (match_operand:DI 0 "register_operand" "")
886 (mult:DI (match_operand:DI 1 "register_operand" "")
887 (match_operand:DI 2 "register_operand" "")))
888 (clobber (reg:DI 64))
889 (clobber (reg:DI 65))]
890 "TARGET_64BIT && !TARGET_DEBUG_D_MODE && mips_cpu != PROCESSOR_R4000"
891 [(parallel [(set (reg:DI 65) ;; low register
892 (mult:DI (match_dup 1)
893 (match_dup 2)))
894 (clobber (reg:DI 64))])
895 (set (match_dup 0)
896 (reg:DI 65))]
897 "")
898
899(define_insn "muldi3_internal"
900 [(set (reg:DI 65) ;; low register
901 (mult:DI (match_operand:DI 0 "register_operand" "d")
902 (match_operand:DI 1 "register_operand" "d")))
903 (clobber (reg:DI 64))]
904 "TARGET_64BIT"
905 "dmult\\t%0,%1"
906 [(set_attr "type" "imul")
907 (set_attr "mode" "DI")
908 (set_attr "length" "1")])
909
910;; In 64 bit mode the mult instruction still writes 32 bits each to HI
911;; and LO, so to do mulsidi3 and umultsidi3 we need to pull the values
912;; out and combine them by hand into the single output register. Not
913;; supported for now.
914
915;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
916
8ef30996
MM		 917(define_insn "mulsidi3"
918 [(set (match_operand:DI 0 "register_operand" "=d")
919 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
920 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
bb621ad7
JW		 921 (clobber (reg:SI 64))
922 (clobber (reg:SI 65))]
923 "!TARGET_64BIT"
8ef30996
MM		 924 "*
925{
926 rtx xoperands[10];
927
928 xoperands[0] = operands[0];
929 xoperands[1] = gen_rtx (REG, DImode, MD_REG_FIRST);
930
931 output_asm_insn (\"mult\\t%1,%2\", operands);
932 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
933 return \"\";
934}"
935 [(set_attr "type" "imul")
936 (set_attr "mode" "SI")
937 (set_attr "length" "4")]) ;; mult + mflo + mfhi + delay
938
903df3fe
JW		 939(define_insn "smulsi3_highpart"
940 [(set (match_operand:SI 0 "register_operand" "=d")
941 (truncate:SI
942 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
943 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
944 (const_int 32))))
945 (clobber (reg:SI 64))
946 (clobber (reg:SI 65))]
947 ""
948 "*
949{
950 rtx xoperands[10];
951
952 xoperands[0] = operands[0];
953 xoperands[1] = gen_rtx (REG, SImode, HI_REGNUM);
954
955 output_asm_insn (\"mult\\t%1,%2\", operands);
9b190d1c 956 output_asm_insn (mips_move_1word (xoperands, insn, TRUE), xoperands);
903df3fe
JW		 957 return \"\";
958}"
959 [(set_attr "type" "imul")
960 (set_attr "mode" "SI")
961 (set_attr "length" "3")]) ;; mult + mfhi + delay
962
963(define_split
964 [(set (match_operand:SI 0 "register_operand" "")
965 (truncate:SI
966 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
967 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
968 (const_int 32))))
969 (clobber (reg:SI 64))
970 (clobber (reg:SI 65))]
971 "!TARGET_DEBUG_D_MODE"
972 [(parallel [(set (reg:SI 64) ;; high register
973 (truncate:SI
974 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
975 (sign_extend:DI (match_dup 2)))
976 (const_int 32))))
977 (clobber (reg:SI 65))])
978 (set (match_dup 0)
979 (reg:SI 64))]
980 "")
981
982(define_insn "smulsi3_highpart_internal"
983 [(set (reg:SI 64) ;; high register
984 (truncate:SI
985 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "register_operand" "d"))
986 (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))
987 (const_int 32))))
988 (clobber (reg:SI 65))]
989 ""
990 "mult\\t%0,%1"
991 [(set_attr "type" "imul")
992 (set_attr "mode" "SI")
993 (set_attr "length" "1")])
994
8ef30996
MM		 995(define_insn "umulsidi3"
996 [(set (match_operand:DI 0 "register_operand" "=d")
997 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
998 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))
bb621ad7
JW		 999 (clobber (reg:SI 64))
1000 (clobber (reg:SI 65))]
1001 "!TARGET_64BIT"
8ef30996
MM		 1002 "*
1003{
1004 rtx xoperands[10];
1005
1006 xoperands[0] = operands[0];
1007 xoperands[1] = gen_rtx (REG, DImode, MD_REG_FIRST);
1008
1009 output_asm_insn (\"multu\\t%1,%2\", operands);
1010 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
1011 return \"\";
1012}"
1013 [(set_attr "type" "imul")
1014 (set_attr "mode" "SI")
1015 (set_attr "length" "4")]) ;; mult + mflo + mfhi + delay
1016
903df3fe
JW		 1017(define_insn "umulsi3_highpart"
1018 [(set (match_operand:SI 0 "register_operand" "=d")
1019 (truncate:SI
1020 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1021 (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
1022 (const_int 32))))
1023 (clobber (reg:SI 64))
1024 (clobber (reg:SI 65))]
1025 ""
1026 "*
1027{
1028 rtx xoperands[10];
1029
1030 xoperands[0] = operands[0];
1031 xoperands[1] = gen_rtx (REG, SImode, HI_REGNUM);
1032
1033 output_asm_insn (\"multu\\t%1,%2\", operands);
9b190d1c 1034 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
903df3fe
JW		 1035 return \"\";
1036}"
1037 [(set_attr "type" "imul")
1038 (set_attr "mode" "SI")
1039 (set_attr "length" "3")]) ;; multu + mfhi + delay
1040
1041(define_split
1042 [(set (match_operand:SI 0 "register_operand" "")
1043 (truncate:SI
1044 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1045 (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
1046 (const_int 32))))
1047 (clobber (reg:SI 64))
1048 (clobber (reg:SI 65))]
1049 "!TARGET_DEBUG_D_MODE"
1050 [(parallel [(set (reg:SI 64) ;; high register
1051 (truncate:SI
1052 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
1053 (zero_extend:DI (match_dup 2)))
1054 (const_int 32))))
1055 (clobber (reg:SI 65))])
1056 (set (match_dup 0)
1057 (reg:SI 64))]
1058 "")
1059
1060(define_insn "umulsi3_highpart_internal"
1061 [(set (reg:SI 64) ;; high register
1062 (truncate:SI
1063 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "register_operand" "d"))
1064 (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))
1065 (const_int 32))))
1066 (clobber (reg:SI 65))]
1067 ""
1068 "multu\\t%0,%1"
1069 [(set_attr "type" "imul")
1070 (set_attr "mode" "SI")
1071 (set_attr "length" "1")])
48199e32
JW		 1072
1073(define_insn "smuldi3_highpart"
1074 [(set (match_operand:DI 0 "register_operand" "=d")
1075 (truncate:DI
1076 (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "d"))
1077 (sign_extend:TI (match_operand:DI 2 "register_operand" "d")))
1078 (const_int 64))))
1079 (clobber (reg:DI 64))
1080 (clobber (reg:DI 65))]
1081 "TARGET_64BIT"
1082 "*
1083{
1084 rtx xoperands[10];
1085
1086 xoperands[0] = operands[0];
1087 xoperands[1] = gen_rtx (REG, DImode, HI_REGNUM);
1088
1089 output_asm_insn (\"dmult\\t%1,%2\", operands);
1090 output_asm_insn (mips_move_1word (xoperands, insn, TRUE), xoperands);
1091 return \"\";
1092}"
1093 [(set_attr "type" "imul")
1094 (set_attr "mode" "DI")
1095 (set_attr "length" "3")]) ;; mult + mfhi + delay
1096
1097(define_split
1098 [(set (match_operand:DI 0 "register_operand" "")
1099 (truncate:DI
1100 (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "d"))
1101 (sign_extend:TI (match_operand:DI 2 "register_operand" "d")))
1102 (const_int 64))))
1103 (clobber (reg:DI 64))
1104 (clobber (reg:DI 65))]
1105 "TARGET_64BIT && !TARGET_DEBUG_D_MODE"
1106 [(parallel [(set (reg:DI 64) ;; high register
1107 (truncate:DI
1108 (lshiftrt:TI (mult:TI (sign_extend:TI (match_dup 1))
1109 (sign_extend:TI (match_dup 2)))
1110 (const_int 64))))
1111 (clobber (reg:DI 65))])
1112 (set (match_dup 0)
1113 (reg:DI 64))]
1114 "")
1115
1116(define_insn "smuldi3_highpart_internal"
1117 [(set (reg:DI 64) ;; high register
1118 (truncate:DI
1119 (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 0 "register_operand" "d"))
1120 (sign_extend:TI (match_operand:DI 1 "register_operand" "d")))
1121 (const_int 64))))
1122 (clobber (reg:DI 65))]
1123 "TARGET_64BIT"
1124 "dmult\\t%0,%1"
1125 [(set_attr "type" "imul")
1126 (set_attr "mode" "DI")
1127 (set_attr "length" "1")])
1128
1129(define_insn "umuldi3_highpart"
1130 [(set (match_operand:DI 0 "register_operand" "=d")
1131 (truncate:DI
1132 (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "d"))
1133 (zero_extend:TI (match_operand:DI 2 "register_operand" "d")))
1134 (const_int 64))))
1135 (clobber (reg:DI 64))
1136 (clobber (reg:DI 65))]
1137 "TARGET_64BIT"
1138 "*
1139{
1140 rtx xoperands[10];
1141
1142 xoperands[0] = operands[0];
1143 xoperands[1] = gen_rtx (REG, DImode, HI_REGNUM);
1144
1145 output_asm_insn (\"dmultu\\t%1,%2\", operands);
1146 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1147 return \"\";
1148}"
1149 [(set_attr "type" "imul")
1150 (set_attr "mode" "DI")
1151 (set_attr "length" "3")]) ;; multu + mfhi + delay
1152
1153(define_split
1154 [(set (match_operand:DI 0 "register_operand" "")
1155 (truncate:DI
1156 (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "d"))
1157 (zero_extend:TI (match_operand:DI 2 "register_operand" "d")))
1158 (const_int 64))))
1159 (clobber (reg:DI 64))
1160 (clobber (reg:DI 65))]
1161 "TARGET_64BIT && !TARGET_DEBUG_D_MODE"
1162 [(parallel [(set (reg:DI 64) ;; high register
1163 (truncate:DI
1164 (lshiftrt:TI (mult:TI (zero_extend:TI (match_dup 1))
1165 (zero_extend:TI (match_dup 2)))
1166 (const_int 64))))
1167 (clobber (reg:DI 65))])
1168 (set (match_dup 0)
1169 (reg:DI 64))]
1170 "")
1171
1172(define_insn "umuldi3_highpart_internal"
1173 [(set (reg:DI 64) ;; high register
1174 (truncate:DI
1175 (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 0 "register_operand" "d"))
1176 (zero_extend:TI (match_operand:DI 1 "register_operand" "d")))
1177 (const_int 64))))
1178 (clobber (reg:DI 65))]
1179 "TARGET_64BIT"
1180 "dmultu\\t%0,%1"
1181 [(set_attr "type" "imul")
1182 (set_attr "mode" "DI")
1183 (set_attr "length" "1")])
8ef30996
MM		 1184\f
1185;;
1186;; ....................
1187;;
1188;; DIVISION and REMAINDER
1189;;
1190;; ....................
1191;;
1192
1193(define_insn "divdf3"
1194 [(set (match_operand:DF 0 "register_operand" "=f")
1195 (div:DF (match_operand:DF 1 "register_operand" "f")
1196 (match_operand:DF 2 "register_operand" "f")))]
1197 "TARGET_HARD_FLOAT"
1198 "div.d\\t%0,%1,%2"
1199 [(set_attr "type" "fdiv")
1200 (set_attr "mode" "DF")
1201 (set_attr "length" "1")])
1202
1203(define_insn "divsf3"
1204 [(set (match_operand:SF 0 "register_operand" "=f")
1205 (div:SF (match_operand:SF 1 "register_operand" "f")
1206 (match_operand:SF 2 "register_operand" "f")))]
1207 "TARGET_HARD_FLOAT"
1208 "div.s\\t%0,%1,%2"
1209 [(set_attr "type" "fdiv")
1210 (set_attr "mode" "SF")
1211 (set_attr "length" "1")])
1212
1213;; If optimizing, prefer the divmod functions over separate div and
1214;; mod functions, since this will allow using one instruction for both
1215;; the quotient and remainder. At present, the divmod is not moved out
1216;; of loops if it is constant within the loop, so allow -mdebugc to
1217;; use the old method of doing things.
1218
1219;; 64 is the multiply/divide hi register
1220;; 65 is the multiply/divide lo register
1221
bb621ad7
JW		 1222;; ??? We can't accept constants here, because the MIPS assembler will replace
1223;; a divide by power of 2 with a shift, and then the remainder is no longer
1224;; available.
1225
8ef30996 1226(define_insn "divmodsi4"
70252580
MM		 1227 [(set (match_operand:SI 0 "register_operand" "=d")
1228 (div:SI (match_operand:SI 1 "register_operand" "d")
1229 (match_operand:SI 2 "register_operand" "d")))
1230 (set (match_operand:SI 3 "register_operand" "=d")
1231 (mod:SI (match_dup 1)
1232 (match_dup 2)))
1233 (clobber (reg:SI 64))
1234 (clobber (reg:SI 65))]
34b650b3 1235 "optimize"
8ef30996
MM		 1236 "*
1237{
1238 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1239 return \"div\\t%0,%1,%2\";
1240
1241 if (find_reg_note (insn, REG_UNUSED, operands[0]))
1242 return \"rem\\t%3,%1,%2\";
1243
1244 return \"div\\t%0,%1,%2\;mfhi\\t%3\";
1245}"
1246 [(set_attr "type" "idiv")
1247 (set_attr "mode" "SI")
bb621ad7
JW		 1248 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
1249
1250(define_insn "divmoddi4"
1251 [(set (match_operand:DI 0 "register_operand" "=d")
1252 (div:DI (match_operand:DI 1 "register_operand" "d")
1253 (match_operand:DI 2 "register_operand" "d")))
1254 (set (match_operand:DI 3 "register_operand" "=d")
1255 (mod:DI (match_dup 1)
1256 (match_dup 2)))
1257 (clobber (reg:DI 64))
1258 (clobber (reg:DI 65))]
1259 "TARGET_64BIT && optimize"
1260 "*
1261{
1262 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1263 return \"ddiv\\t%0,%1,%2\";
1264
1265 if (find_reg_note (insn, REG_UNUSED, operands[0]))
1266 return \"drem\\t%3,%1,%2\";
1267
1268 return \"ddiv\\t%0,%1,%2\;mfhi\\t%3\";
1269}"
1270 [(set_attr "type" "idiv")
1271 (set_attr "mode" "DI")
1272 (set_attr "length" "15")]) ;; various tests for dividing by 0 and such
8ef30996
MM		 1273
1274(define_insn "udivmodsi4"
70252580
MM		 1275 [(set (match_operand:SI 0 "register_operand" "=d")
1276 (udiv:SI (match_operand:SI 1 "register_operand" "d")
1277 (match_operand:SI 2 "register_operand" "d")))
1278 (set (match_operand:SI 3 "register_operand" "=d")
1279 (umod:SI (match_dup 1)
1280 (match_dup 2)))
1281 (clobber (reg:SI 64))
1282 (clobber (reg:SI 65))]
34b650b3 1283 "optimize"
8ef30996
MM		 1284 "*
1285{
1286 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1287 return \"divu\\t%0,%1,%2\";
1288
1289 if (find_reg_note (insn, REG_UNUSED, operands[0]))
1290 return \"remu\\t%3,%1,%2\";
1291
1292 return \"divu\\t%0,%1,%2\;mfhi\\t%3\";
1293}"
1294 [(set_attr "type" "idiv")
1295 (set_attr "mode" "SI")
bb621ad7
JW		 1296 (set_attr "length" "8")]) ;; various tests for dividing by 0 and such
1297
1298(define_insn "udivmoddi4"
1299 [(set (match_operand:DI 0 "register_operand" "=d")
1300 (udiv:DI (match_operand:DI 1 "register_operand" "d")
1301 (match_operand:DI 2 "register_operand" "d")))
1302 (set (match_operand:DI 3 "register_operand" "=d")
1303 (umod:DI (match_dup 1)
1304 (match_dup 2)))
1305 (clobber (reg:DI 64))
1306 (clobber (reg:DI 65))]
1307 "TARGET_64BIT && optimize"
1308 "*
1309{
1310 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1311 return \"ddivu\\t%0,%1,%2\";
1312
1313 if (find_reg_note (insn, REG_UNUSED, operands[0]))
1314 return \"dremu\\t%3,%1,%2\";
1315
1316 return \"ddivu\\t%0,%1,%2\;mfhi\\t%3\";
1317}"
1318 [(set_attr "type" "idiv")
1319 (set_attr "mode" "DI")
1320 (set_attr "length" "8")]) ;; various tests for dividing by 0 and such
8ef30996
MM		 1321
1322(define_insn "divsi3"
1323 [(set (match_operand:SI 0 "register_operand" "=d")
1324 (div:SI (match_operand:SI 1 "register_operand" "d")
bb621ad7 1325 (match_operand:SI 2 "nonmemory_operand" "di")))
8ef30996
MM		 1326 (clobber (reg:SI 64))
1327 (clobber (reg:SI 65))]
34b650b3 1328 "!optimize"
8ef30996
MM		 1329 "div\\t%0,%1,%2"
1330 [(set_attr "type" "idiv")
1331 (set_attr "mode" "SI")
1332 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
1333
bb621ad7
JW		 1334(define_insn "divdi3"
1335 [(set (match_operand:DI 0 "register_operand" "=d")
1336 (div:DI (match_operand:DI 1 "register_operand" "d")
1337 (match_operand:DI 2 "nonmemory_operand" "di")))
1338 (clobber (reg:DI 64))
1339 (clobber (reg:DI 65))]
1340 "TARGET_64BIT && !optimize"
1341 "ddiv\\t%0,%1,%2"
1342 [(set_attr "type" "idiv")
1343 (set_attr "mode" "DI")
1344 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
1345
8ef30996
MM		 1346(define_insn "modsi3"
1347 [(set (match_operand:SI 0 "register_operand" "=d")
1348 (mod:SI (match_operand:SI 1 "register_operand" "d")
bb621ad7 1349 (match_operand:SI 2 "nonmemory_operand" "di")))
8ef30996
MM		 1350 (clobber (reg:SI 64))
1351 (clobber (reg:SI 65))]
34b650b3 1352 "!optimize"
8ef30996
MM		 1353 "rem\\t%0,%1,%2"
1354 [(set_attr "type" "idiv")
1355 (set_attr "mode" "SI")
bb621ad7
JW		 1356 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
1357
1358(define_insn "moddi3"
1359 [(set (match_operand:DI 0 "register_operand" "=d")
1360 (mod:DI (match_operand:DI 1 "register_operand" "d")
1361 (match_operand:DI 2 "nonmemory_operand" "di")))
1362 (clobber (reg:DI 64))
1363 (clobber (reg:DI 65))]
1364 "TARGET_64BIT && !optimize"
1365 "drem\\t%0,%1,%2"
1366 [(set_attr "type" "idiv")
1367 (set_attr "mode" "DI")
8ef30996
MM		 1368 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
1369
1370(define_insn "udivsi3"
1371 [(set (match_operand:SI 0 "register_operand" "=d")
1372 (udiv:SI (match_operand:SI 1 "register_operand" "d")
bb621ad7 1373 (match_operand:SI 2 "nonmemory_operand" "di")))
8ef30996
MM		 1374 (clobber (reg:SI 64))
1375 (clobber (reg:SI 65))]
34b650b3 1376 "!optimize"
8ef30996
MM		 1377 "divu\\t%0,%1,%2"
1378 [(set_attr "type" "idiv")
1379 (set_attr "mode" "SI")
bb621ad7
JW		 1380 (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
1381
1382(define_insn "udivdi3"
1383 [(set (match_operand:DI 0 "register_operand" "=d")
1384 (udiv:DI (match_operand:DI 1 "register_operand" "d")
1385 (match_operand:DI 2 "nonmemory_operand" "di")))
1386 (clobber (reg:DI 64))
1387 (clobber (reg:DI 65))]
1388 "TARGET_64BIT && !optimize"
1389 "ddivu\\t%0,%1,%2"
1390 [(set_attr "type" "idiv")
1391 (set_attr "mode" "DI")
1392 (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
8ef30996
MM		 1393
1394(define_insn "umodsi3"
1395 [(set (match_operand:SI 0 "register_operand" "=d")
1396 (umod:SI (match_operand:SI 1 "register_operand" "d")
bb621ad7 1397 (match_operand:SI 2 "nonmemory_operand" "di")))
8ef30996
MM		 1398 (clobber (reg:SI 64))
1399 (clobber (reg:SI 65))]
34b650b3 1400 "!optimize"
8ef30996
MM		 1401 "remu\\t%0,%1,%2"
1402 [(set_attr "type" "idiv")
1403 (set_attr "mode" "SI")
bb621ad7
JW		 1404 (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
1405
1406(define_insn "umoddi3"
1407 [(set (match_operand:DI 0 "register_operand" "=d")
1408 (umod:DI (match_operand:DI 1 "register_operand" "d")
1409 (match_operand:DI 2 "nonmemory_operand" "di")))
1410 (clobber (reg:DI 64))
1411 (clobber (reg:DI 65))]
1412 "TARGET_64BIT && !optimize"
1413 "dremu\\t%0,%1,%2"
1414 [(set_attr "type" "idiv")
1415 (set_attr "mode" "DI")
1416 (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
8ef30996
MM		 1417
1418\f
1419;;
1420;; ....................
1421;;
1422;; SQUARE ROOT
1423;;
1424;; ....................
1425
1426(define_insn "sqrtdf2"
1427 [(set (match_operand:DF 0 "register_operand" "=f")
1428 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
1429 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
1430 "sqrt.d\\t%0,%1"
bb621ad7 1431 [(set_attr "type" "fsqrt")
8ef30996
MM		 1432 (set_attr "mode" "DF")
1433 (set_attr "length" "1")])
1434
1435(define_insn "sqrtsf2"
1436 [(set (match_operand:SF 0 "register_operand" "=f")
1437 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
1438 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
1439 "sqrt.s\\t%0,%1"
bb621ad7 1440 [(set_attr "type" "fsqrt")
8ef30996
MM		 1441 (set_attr "mode" "SF")
1442 (set_attr "length" "1")])
1443
1444\f
1445;;
1446;; ....................
1447;;
1448;; ABSOLUTE VALUE
1449;;
1450;; ....................
1451
1452;; Do not use the integer abs macro instruction, since that signals an
1453;; exception on -2147483648 (sigh).
1454
1455(define_insn "abssi2"
1456 [(set (match_operand:SI 0 "register_operand" "=d")
1457 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1458 ""
1459 "*
1460{
1461 dslots_jump_total++;
1462 dslots_jump_filled++;
1463 operands[2] = const0_rtx;
1464
bb621ad7
JW		 1465 if (REGNO (operands[0]) == REGNO (operands[1]))
1466 {
1467 if (mips_isa >= 2)
1468 return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
1469 else
1470 return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n1:\";
1471 }
1472 else
1473 return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
8ef30996
MM		 1474}"
1475 [(set_attr "type" "multi")
1476 (set_attr "mode" "SI")
1477 (set_attr "length" "3")])
1478
bb621ad7
JW		 1479(define_insn "absdi2"
1480 [(set (match_operand:DI 0 "register_operand" "=d")
1481 (abs:DI (match_operand:DI 1 "register_operand" "d")))]
1482 "TARGET_64BIT"
1483 "*
1484{
1485 dslots_jump_total++;
1486 dslots_jump_filled++;
1487 operands[2] = const0_rtx;
1488
1489 if (REGNO (operands[0]) == REGNO (operands[1]))
1490 return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
1491 else
1492 return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
1493}"
1494 [(set_attr "type" "multi")
1495 (set_attr "mode" "DI")
1496 (set_attr "length" "3")])
1497
8ef30996
MM		 1498(define_insn "absdf2"
1499 [(set (match_operand:DF 0 "register_operand" "=f")
1500 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
1501 "TARGET_HARD_FLOAT"
1502 "abs.d\\t%0,%1"
1503 [(set_attr "type" "fabs")
1504 (set_attr "mode" "DF")
1505 (set_attr "length" "1")])
1506
1507(define_insn "abssf2"
1508 [(set (match_operand:SF 0 "register_operand" "=f")
1509 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
1510 "TARGET_HARD_FLOAT"
1511 "abs.s\\t%0,%1"
1512 [(set_attr "type" "fabs")
1513 (set_attr "mode" "SF")
1514 (set_attr "length" "1")])
1515
1516\f
1517;;
1518;; ....................
1519;;
1520;; FIND FIRST BIT INSTRUCTION
1521;;
1522;; ....................
1523;;
1524
1525(define_insn "ffssi2"
1526 [(set (match_operand:SI 0 "register_operand" "=&d")
1527 (ffs:SI (match_operand:SI 1 "register_operand" "d")))
7d87c851
MM		 1528 (clobber (match_scratch:SI 2 "=&d"))
1529 (clobber (match_scratch:SI 3 "=&d"))]
8ef30996
MM		 1530 ""
1531 "*
1532{
1533 dslots_jump_total += 2;
1534 dslots_jump_filled += 2;
1535 operands[4] = const0_rtx;
1536
1537 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
1538 return \"%(\\
1539move\\t%0,%z4\\n\\
1540\\tbeq\\t%1,%z4,2f\\n\\
15411:\\tand\\t%2,%1,0x0001\\n\\
1542\\taddu\\t%0,%0,1\\n\\
1543\\tbeq\\t%2,%z4,1b\\n\\
1544\\tsrl\\t%1,%1,1\\n\\
15452:%)\";
1546
1547 return \"%(\\
1548move\\t%0,%z4\\n\\
1549\\tmove\\t%3,%1\\n\\
1550\\tbeq\\t%3,%z4,2f\\n\\
15511:\\tand\\t%2,%3,0x0001\\n\\
1552\\taddu\\t%0,%0,1\\n\\
1553\\tbeq\\t%2,%z4,1b\\n\\
1554\\tsrl\\t%3,%3,1\\n\\
15552:%)\";
1556}"
1557 [(set_attr "type" "multi")
1558 (set_attr "mode" "SI")
1559 (set_attr "length" "6")])
1560
bb621ad7
JW		 1561(define_insn "ffsdi2"
1562 [(set (match_operand:DI 0 "register_operand" "=&d")
1563 (ffs:DI (match_operand:DI 1 "register_operand" "d")))
1564 (clobber (match_scratch:DI 2 "=&d"))
1565 (clobber (match_scratch:DI 3 "=&d"))]
1566 "TARGET_64BIT"
1567 "*
1568{
1569 dslots_jump_total += 2;
1570 dslots_jump_filled += 2;
1571 operands[4] = const0_rtx;
1572
1573 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
1574 return \"%(\\
1575move\\t%0,%z4\\n\\
1576\\tbeq\\t%1,%z4,2f\\n\\
15771:\\tand\\t%2,%1,0x0001\\n\\
1578\\tdaddu\\t%0,%0,1\\n\\
1579\\tbeq\\t%2,%z4,1b\\n\\
1580\\tdsrl\\t%1,%1,1\\n\\
15812:%)\";
1582
1583 return \"%(\\
1584move\\t%0,%z4\\n\\
1585\\tmove\\t%3,%1\\n\\
1586\\tbeq\\t%3,%z4,2f\\n\\
15871:\\tand\\t%2,%3,0x0001\\n\\
1588\\tdaddu\\t%0,%0,1\\n\\
1589\\tbeq\\t%2,%z4,1b\\n\\
1590\\tdsrl\\t%3,%3,1\\n\\
15912:%)\";
1592}"
1593 [(set_attr "type" "multi")
1594 (set_attr "mode" "DI")
1595 (set_attr "length" "6")])
1596
8ef30996
MM		 1597\f
1598;;
1599;; ....................
1600;;
1601;; NEGATION and ONE'S COMPLEMENT
1602;;
1603;; ....................
1604
1605(define_insn "negsi2"
1606 [(set (match_operand:SI 0 "register_operand" "=d")
1607 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1608 ""
1609 "*
1610{
1611 operands[2] = const0_rtx;
1612 return \"subu\\t%0,%z2,%1\";
1613}"
1614 [(set_attr "type" "arith")
1615 (set_attr "mode" "SI")
1616 (set_attr "length" "1")])
1617
e7d7b3dc 1618(define_expand "negdi2"
8ef30996
MM		 1619 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
1620 (neg:DI (match_operand:DI 1 "register_operand" "d")))
1621 (clobber (match_dup 2))])]
bb621ad7
JW		 1622 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
1623 "
1624{
1625 if (TARGET_64BIT)
1626 {
1627 emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
1628 DONE;
1629 }
1630
1631 operands[2] = gen_reg_rtx (SImode);
1632}")
8ef30996 1633
e7d7b3dc 1634(define_insn "negdi2_internal"
8ef30996
MM		 1635 [(set (match_operand:DI 0 "register_operand" "=d")
1636 (neg:DI (match_operand:DI 1 "register_operand" "d")))
1637 (clobber (match_operand:SI 2 "register_operand" "=d"))]
bb621ad7 1638 "! TARGET_64BIT && !TARGET_DEBUG_G_MODE"
8ef30996
MM		 1639 "*
1640{
1641 operands[3] = const0_rtx;
1642 return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
1643}"
1644 [(set_attr "type" "darith")
1645 (set_attr "mode" "DI")
1646 (set_attr "length" "4")])
1647
bb621ad7
JW		 1648(define_insn "negdi2_internal_2"
1649 [(set (match_operand:DI 0 "register_operand" "=d")
1650 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
1651 "TARGET_64BIT"
1652 "*
1653{
1654 operands[2] = const0_rtx;
1655 return \"dsubu\\t%0,%z2,%1\";
1656}"
1657 [(set_attr "type" "arith")
1658 (set_attr "mode" "DI")
1659 (set_attr "length" "1")])
1660
8ef30996
MM		 1661(define_insn "negdf2"
1662 [(set (match_operand:DF 0 "register_operand" "=f")
1663 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
1664 "TARGET_HARD_FLOAT"
1665 "neg.d\\t%0,%1"
1666 [(set_attr "type" "fneg")
1667 (set_attr "mode" "DF")
1668 (set_attr "length" "1")])
1669
1670(define_insn "negsf2"
1671 [(set (match_operand:SF 0 "register_operand" "=f")
1672 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
1673 "TARGET_HARD_FLOAT"
1674 "neg.s\\t%0,%1"
1675 [(set_attr "type" "fneg")
1676 (set_attr "mode" "SF")
1677 (set_attr "length" "1")])
1678
1679(define_insn "one_cmplsi2"
1680 [(set (match_operand:SI 0 "register_operand" "=d")
1681 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1682 ""
1683 "*
1684{
1685 operands[2] = const0_rtx;
1686 return \"nor\\t%0,%z2,%1\";
1687}"
1688 [(set_attr "type" "arith")
1689 (set_attr "mode" "SI")
1690 (set_attr "length" "1")])
1691
1692(define_insn "one_cmpldi2"
1693 [(set (match_operand:DI 0 "register_operand" "=d")
bb621ad7 1694 (not:DI (match_operand:DI 1 "register_operand" "d")))]
8ef30996
MM		 1695 ""
1696 "*
1697{
1698 operands[2] = const0_rtx;
bb621ad7
JW		 1699 if (TARGET_64BIT)
1700 return \"nor\\t%0,%z2,%1\";
8ef30996
MM		 1701 return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
1702}"
1703 [(set_attr "type" "darith")
1704 (set_attr "mode" "DI")
bb621ad7
JW		 1705 (set (attr "length")
1706 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
1707 (const_int 1)
1708 (const_int 2)))])
8ef30996
MM		 1709
1710(define_split
1711 [(set (match_operand:DI 0 "register_operand" "")
1712 (not:DI (match_operand:DI 1 "register_operand" "")))]
bb621ad7 1713 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1714 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1715 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
1716
1717 [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
1718 (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))]
1719 "")
1720
1721;; Simple hack to recognize the "nor" instruction on the MIPS
1722;; This must appear before the normal or patterns, so that the
1723;; combiner will correctly fold things.
1724
1725(define_insn "norsi3"
1726 [(set (match_operand:SI 0 "register_operand" "=d")
1727 (not:SI (ior:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1728 (match_operand:SI 2 "reg_or_0_operand" "dJ"))))]
1729 ""
1730 "nor\\t%0,%z1,%z2"
1731 [(set_attr "type" "arith")
1732 (set_attr "mode" "SI")
1733 (set_attr "length" "1")])
1734
1735(define_insn "nordi3"
1736 [(set (match_operand:DI 0 "register_operand" "=d")
1737 (not:DI (ior:DI (match_operand:DI 1 "register_operand" "d")
1738 (match_operand:DI 2 "register_operand" "d"))))]
1739 ""
bb621ad7
JW		 1740 "*
1741{
1742 if (TARGET_64BIT)
1743 return \"nor\\t%0,%z1,%z2\";
1744 return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\";
1745}"
8ef30996
MM		 1746 [(set_attr "type" "darith")
1747 (set_attr "mode" "DI")
bb621ad7
JW		 1748 (set (attr "length")
1749 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
1750 (const_int 1)
1751 (const_int 2)))])
8ef30996
MM		 1752
1753(define_split
1754 [(set (match_operand:DI 0 "register_operand" "")
1755 (not:DI (ior:DI (match_operand:DI 1 "register_operand" "")
1756 (match_operand:DI 2 "register_operand" ""))))]
bb621ad7 1757 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1758 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1759 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1760 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1761
1762 [(set (subreg:SI (match_dup 0) 0) (not:SI (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))))
1763 (set (subreg:SI (match_dup 0) 1) (not:SI (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1))))]
1764 "")
1765
1766\f
1767;;
1768;; ....................
1769;;
1770;; LOGICAL
1771;;
1772;; ....................
1773;;
1774
3e89ed5f 1775(define_insn "andsi3"
65437fe8 1776 [(set (match_operand:SI 0 "register_operand" "=d,d")
e2f2127c
MM		 1777 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
1778 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
65437fe8
MM		 1779 ""
1780 "@
1781 and\\t%0,%1,%2
1782 andi\\t%0,%1,%x2"
1783 [(set_attr "type" "arith")
1784 (set_attr "mode" "SI")
1785 (set_attr "length" "1")])
1786
8ef30996
MM		 1787(define_insn "anddi3"
1788 [(set (match_operand:DI 0 "register_operand" "=d")
1789 (and:DI (match_operand:DI 1 "register_operand" "d")
1790 (match_operand:DI 2 "register_operand" "d")))]
bb621ad7
JW		 1791 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
1792 "*
1793{
1794 if (TARGET_64BIT)
1795 return \"and\\t%0,%1,%2\";
1796 return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\";
1797}"
8ef30996
MM		 1798 [(set_attr "type" "darith")
1799 (set_attr "mode" "DI")
bb621ad7
JW		 1800 (set (attr "length")
1801 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
1802 (const_int 1)
1803 (const_int 2)))])
8ef30996
MM		 1804
1805(define_split
1806 [(set (match_operand:DI 0 "register_operand" "")
1807 (and:DI (match_operand:DI 1 "register_operand" "")
1808 (match_operand:DI 2 "register_operand" "")))]
bb621ad7 1809 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1810 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1811 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1812 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1813
1814 [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1815 (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1816 "")
1817
bb621ad7
JW		 1818(define_insn "anddi3_internal1"
1819 [(set (match_operand:DI 0 "register_operand" "=d,d")
1820 (and:DI (match_operand:DI 1 "register_operand" "%d,d")
1821 (match_operand:DI 2 "uns_arith_operand" "d,K")))]
1822 "TARGET_64BIT"
1823 "@
1824 and\\t%0,%1,%2
1825 andi\\t%0,%1,%x2"
1826 [(set_attr "type" "arith")
1827 (set_attr "mode" "DI")
1828 (set_attr "length" "1")])
1829
3e89ed5f 1830(define_insn "iorsi3"
65437fe8 1831 [(set (match_operand:SI 0 "register_operand" "=d,d")
e2f2127c
MM		 1832 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
1833 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
65437fe8
MM		 1834 ""
1835 "@
1836 or\\t%0,%1,%2
1837 ori\\t%0,%1,%x2"
1838 [(set_attr "type" "arith")
1839 (set_attr "mode" "SI")
1840 (set_attr "length" "1")])
1841
bb621ad7
JW		 1842;;; ??? There is no iordi3 pattern which accepts 'K' constants when
1843;;; TARGET_64BIT
1844
8ef30996
MM		 1845(define_insn "iordi3"
1846 [(set (match_operand:DI 0 "register_operand" "=d")
1847 (ior:DI (match_operand:DI 1 "register_operand" "d")
1848 (match_operand:DI 2 "register_operand" "d")))]
bb621ad7
JW		 1849 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
1850 "*
1851{
1852 if (TARGET_64BIT)
1853 return \"or\\t%0,%1,%2\";
1854 return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\";
1855}"
8ef30996
MM		 1856 [(set_attr "type" "darith")
1857 (set_attr "mode" "DI")
bb621ad7
JW		 1858 (set (attr "length")
1859 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
1860 (const_int 1)
1861 (const_int 2)))])
8ef30996
MM		 1862
1863(define_split
1864 [(set (match_operand:DI 0 "register_operand" "")
1865 (ior:DI (match_operand:DI 1 "register_operand" "")
1866 (match_operand:DI 2 "register_operand" "")))]
bb621ad7 1867 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1868 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1869 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1870 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1871
1872 [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1873 (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1874 "")
1875
3e89ed5f 1876(define_insn "xorsi3"
65437fe8 1877 [(set (match_operand:SI 0 "register_operand" "=d,d")
e2f2127c
MM		 1878 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
1879 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
65437fe8
MM		 1880 ""
1881 "@
1882 xor\\t%0,%1,%2
1883 xori\\t%0,%1,%x2"
1884 [(set_attr "type" "arith")
1885 (set_attr "mode" "SI")
1886 (set_attr "length" "1")])
1887
bb621ad7
JW		 1888;; ??? If delete the 32-bit long long patterns, then could merge this with
1889;; the following xordi3_internal pattern.
8ef30996
MM		 1890(define_insn "xordi3"
1891 [(set (match_operand:DI 0 "register_operand" "=d")
1892 (xor:DI (match_operand:DI 1 "register_operand" "d")
1893 (match_operand:DI 2 "register_operand" "d")))]
bb621ad7
JW		 1894 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
1895 "*
1896{
1897 if (TARGET_64BIT)
1898 return \"xor\\t%0,%1,%2\";
1899 return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\";
1900}"
1901 [(set_attr "type" "darith")
8ef30996 1902 (set_attr "mode" "DI")
bb621ad7
JW		 1903 (set (attr "length")
1904 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
1905 (const_int 1)
1906 (const_int 2)))])
8ef30996
MM		 1907
1908(define_split
1909 [(set (match_operand:DI 0 "register_operand" "")
1910 (xor:DI (match_operand:DI 1 "register_operand" "")
1911 (match_operand:DI 2 "register_operand" "")))]
bb621ad7 1912 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1913 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1914 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1915 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1916
1917 [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1918 (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1919 "")
1920
bb621ad7
JW		 1921(define_insn "xordi3_immed"
1922 [(set (match_operand:DI 0 "register_operand" "d")
1923 (xor:DI (match_operand:DI 1 "register_operand" "d")
1924 (match_operand:DI 2 "uns_arith_operand" "K")))]
1925 "TARGET_64BIT"
1926 "xori\\t%0,%1,%x2"
1927 [(set_attr "type" "arith")
1928 (set_attr "mode" "DI")
1929 (set_attr "length" "1")])
1930
8ef30996
MM		 1931\f
1932;;
1933;; ....................
1934;;
1935;; TRUNCATION
1936;;
1937;; ....................
1938
1939(define_insn "truncdfsf2"
1940 [(set (match_operand:SF 0 "register_operand" "=f")
1941 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
1942 "TARGET_HARD_FLOAT"
1943 "cvt.s.d\\t%0,%1"
1944 [(set_attr "type" "fcvt")
1945 (set_attr "mode" "SF")
1946 (set_attr "length" "1")])
1947
abdf3eea
JW		 1948
1949;; The optimizer doesn't deal well with truncate operators, so we completely
1950;; avoid them by using define expands here.
1951
1952(define_expand "truncdisi2"
1953 [(set (match_operand:DI 2 "register_operand" "=d")
1954 (ashift:DI (match_operand:DI 1 "register_operand" "d")
1955 (const_int 32)))
1956 (set (match_operand:DI 3 "register_operand" "=d")
1957 (ashiftrt:DI (match_dup 2)
1958 (const_int 32)))
1959 (set (match_operand:SI 0 "register_operand" "=d")
1960 (subreg:SI (match_dup 3) 0))]
bb621ad7 1961 "TARGET_64BIT"
abdf3eea
JW		 1962 "
1963{
1964 operands[2] = gen_reg_rtx (DImode);
1965 operands[3] = gen_reg_rtx (DImode);
1966}")
bb621ad7 1967
abdf3eea
JW		 1968(define_expand "truncdihi2"
1969 [(set (match_operand:DI 2 "register_operand" "=d")
1970 (and:DI (match_operand:DI 1 "register_operand" "d")
1971 (const_int 65535)))
1972 (set (match_operand:HI 0 "register_operand" "=d")
1973 (subreg:HI (match_dup 2) 0))]
bb621ad7 1974 "TARGET_64BIT"
abdf3eea
JW		 1975 "
1976{
1977 operands[2] = gen_reg_rtx (DImode);
1978}")
bb621ad7 1979
abdf3eea
JW		 1980(define_expand "truncdiqi2"
1981 [(set (match_operand:DI 2 "register_operand" "=d")
1982 (and:DI (match_operand:DI 1 "register_operand" "d")
1983 (const_int 255)))
1984 (set (match_operand:QI 0 "register_operand" "=d")
1985 (subreg:QI (match_dup 2) 0))]
bb621ad7 1986 "TARGET_64BIT"
abdf3eea
JW		 1987 "
1988{
1989 operands[2] = gen_reg_rtx (DImode);
1990}")
8ef30996
MM		 1991\f
1992;;
1993;; ....................
1994;;
1995;; ZERO EXTENSION
1996;;
1997;; ....................
1998
1999;; Extension insns.
abdf3eea 2000;; Those for integer source operand are ordered widest source type first.
8ef30996 2001
bb621ad7
JW		 2002(define_expand "zero_extendsidi2"
2003 [(set (match_operand:DI 0 "register_operand" "")
2004 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2005 "TARGET_64BIT"
2006 "
2007{
2008 if (optimize && GET_CODE (operands[1]) == MEM)
2009 operands[1] = force_not_mem (operands[1]);
2010
2011 if (GET_CODE (operands[1]) != MEM)
2012 {
2013 rtx op1 = gen_lowpart (DImode, operands[1]);
2014 rtx temp = gen_reg_rtx (DImode);
2015 rtx shift = gen_rtx (CONST_INT, VOIDmode, 32);
2016
2017 emit_insn (gen_ashldi3 (temp, op1, shift));
2018 emit_insn (gen_lshrdi3 (operands[0], temp, shift));
2019 DONE;
2020 }
2021}")
2022
2023(define_insn "zero_extendsidi2_internal"
2024 [(set (match_operand:DI 0 "register_operand" "=d,d")
2025 (zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
2026 "TARGET_64BIT"
2027 "* return mips_move_1word (operands, insn, TRUE);"
2028 [(set_attr "type" "load")
2029 (set_attr "mode" "DI")
2030 (set_attr "length" "1,2")])
2031
8ef30996
MM		 2032(define_insn "zero_extendhisi2"
2033 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2034 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
2035 ""
2036 "*
2037{
2038 if (which_alternative == 0)
2039 return \"andi\\t%0,%1,0xffff\";
2040 else
2041 return mips_move_1word (operands, insn, TRUE);
2042}"
2043 [(set_attr "type" "arith,load,load")
92b4cee1 2044 (set_attr "mode" "SI")
8ef30996
MM		 2045 (set_attr "length" "1,1,2")])
2046
bb621ad7
JW		 2047(define_insn "zero_extendhidi2"
2048 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2049 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
2050 "TARGET_64BIT"
2051 "*
2052{
2053 if (which_alternative == 0)
2054 return \"andi\\t%0,%1,0xffff\";
2055 else
2056 return mips_move_1word (operands, insn, TRUE);
2057}"
2058 [(set_attr "type" "arith,load,load")
2059 (set_attr "mode" "DI")
2060 (set_attr "length" "1,1,2")])
2061
8ef30996
MM		 2062(define_insn "zero_extendqihi2"
2063 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2064 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
2065 ""
2066 "*
2067{
2068 if (which_alternative == 0)
2069 return \"andi\\t%0,%1,0x00ff\";
2070 else
2071 return mips_move_1word (operands, insn, TRUE);
2072}"
2073 [(set_attr "type" "arith,load,load")
92b4cee1 2074 (set_attr "mode" "HI")
8ef30996
MM		 2075 (set_attr "length" "1,1,2")])
2076
2077(define_insn "zero_extendqisi2"
2078 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2079 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
2080 ""
2081 "*
2082{
2083 if (which_alternative == 0)
2084 return \"andi\\t%0,%1,0x00ff\";
2085 else
2086 return mips_move_1word (operands, insn, TRUE);
2087}"
2088 [(set_attr "type" "arith,load,load")
92b4cee1 2089 (set_attr "mode" "SI")
8ef30996
MM		 2090 (set_attr "length" "1,1,2")])
2091
bb621ad7
JW		 2092(define_insn "zero_extendqidi2"
2093 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2094 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
2095 "TARGET_64BIT"
2096 "*
2097{
2098 if (which_alternative == 0)
2099 return \"andi\\t%0,%1,0x00ff\";
2100 else
2101 return mips_move_1word (operands, insn, TRUE);
2102}"
2103 [(set_attr "type" "arith,load,load")
2104 (set_attr "mode" "DI")
2105 (set_attr "length" "1,1,2")])
2106
8ef30996
MM		 2107\f
2108;;
2109;; ....................
2110;;
2111;; SIGN EXTENSION
2112;;
2113;; ....................
2114
2115;; Extension insns.
abdf3eea 2116;; Those for integer source operand are ordered widest source type first.
8ef30996 2117
abdf3eea
JW		 2118(define_expand "extendsidi2"
2119 [(set (match_operand:DI 0 "register_operand" "")
2120 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
bb621ad7 2121 "TARGET_64BIT"
abdf3eea 2122 "
bb621ad7 2123{
abdf3eea
JW		 2124 if (optimize && GET_CODE (operands[1]) == MEM)
2125 operands[1] = force_not_mem (operands[1]);
2126
2127 if (GET_CODE (operands[1]) != MEM)
2128 {
2129 rtx op1 = gen_lowpart (DImode, operands[1]);
2130 rtx temp = gen_reg_rtx (DImode);
2131 rtx shift = gen_rtx (CONST_INT, VOIDmode, 32);
2132
2133 emit_insn (gen_ashldi3 (temp, op1, shift));
2134 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
2135 DONE;
2136 }
2137}")
2138
2139(define_insn "extendsidi2_internal"
2140 [(set (match_operand:DI 0 "register_operand" "=d,d")
2141 (sign_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
2142 "TARGET_64BIT"
2143 "* return mips_move_1word (operands, insn, FALSE);"
2144 [(set_attr "type" "load")
bb621ad7 2145 (set_attr "mode" "DI")
abdf3eea 2146 (set_attr "length" "1,2")])
bb621ad7 2147
8ef30996
MM		 2148;; These patterns originally accepted general_operands, however, slightly
2149;; better code is generated by only accepting register_operands, and then
2150;; letting combine generate the lh and lb insns.
2151
bb621ad7
JW		 2152(define_expand "extendhidi2"
2153 [(set (match_operand:DI 0 "register_operand" "")
2154 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
2155 "TARGET_64BIT"
2156 "
2157{
2158 if (optimize && GET_CODE (operands[1]) == MEM)
2159 operands[1] = force_not_mem (operands[1]);
2160
2161 if (GET_CODE (operands[1]) != MEM)
2162 {
2163 rtx op1 = gen_lowpart (DImode, operands[1]);
2164 rtx temp = gen_reg_rtx (DImode);
2165 rtx shift = gen_rtx (CONST_INT, VOIDmode, 48);
2166
2167 emit_insn (gen_ashldi3 (temp, op1, shift));
2168 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
2169 DONE;
2170 }
2171}")
2172
2173(define_insn "extendhidi2_internal"
2174 [(set (match_operand:DI 0 "register_operand" "=d,d")
2175 (sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
2176 "TARGET_64BIT"
2177 "* return mips_move_1word (operands, insn, FALSE);"
2178 [(set_attr "type" "load")
2179 (set_attr "mode" "DI")
2180 (set_attr "length" "1,2")])
2181
8ef30996
MM		 2182(define_expand "extendhisi2"
2183 [(set (match_operand:SI 0 "register_operand" "")
2184 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2185 ""
2186 "
2187{
2188 if (optimize && GET_CODE (operands[1]) == MEM)
2189 operands[1] = force_not_mem (operands[1]);
2190
2191 if (GET_CODE (operands[1]) != MEM)
2192 {
2193 rtx op1 = gen_lowpart (SImode, operands[1]);
2194 rtx temp = gen_reg_rtx (SImode);
2195 rtx shift = gen_rtx (CONST_INT, VOIDmode, 16);
2196
2197 emit_insn (gen_ashlsi3 (temp, op1, shift));
2198 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
2199 DONE;
2200 }
2201}")
2202
2203(define_insn "extendhisi2_internal"
2204 [(set (match_operand:SI 0 "register_operand" "=d,d")
2205 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
2206 ""
2207 "* return mips_move_1word (operands, insn, FALSE);"
92b4cee1
MM		 2208 [(set_attr "type" "load")
2209 (set_attr "mode" "SI")
8ef30996
MM		 2210 (set_attr "length" "1,2")])
2211
2212(define_expand "extendqihi2"
2213 [(set (match_operand:HI 0 "register_operand" "")
2214 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
2215 ""
2216 "
2217{
2218 if (optimize && GET_CODE (operands[1]) == MEM)
2219 operands[1] = force_not_mem (operands[1]);
2220
2221 if (GET_CODE (operands[1]) != MEM)
2222 {
2223 rtx op0 = gen_lowpart (SImode, operands[0]);
2224 rtx op1 = gen_lowpart (SImode, operands[1]);
2225 rtx temp = gen_reg_rtx (SImode);
2226 rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
2227
2228 emit_insn (gen_ashlsi3 (temp, op1, shift));
2229 emit_insn (gen_ashrsi3 (op0, temp, shift));
2230 DONE;
2231 }
2232}")
2233
2234(define_insn "extendqihi2_internal"
2235 [(set (match_operand:HI 0 "register_operand" "=d,d")
2236 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
2237 ""
2238 "* return mips_move_1word (operands, insn, FALSE);"
92b4cee1
MM		 2239 [(set_attr "type" "load")
2240 (set_attr "mode" "SI")
8ef30996
MM		 2241 (set_attr "length" "1,2")])
2242
2243
2244(define_expand "extendqisi2"
2245 [(set (match_operand:SI 0 "register_operand" "")
2246 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
2247 ""
2248 "
2249{
2250 if (optimize && GET_CODE (operands[1]) == MEM)
2251 operands[1] = force_not_mem (operands[1]);
2252
2253 if (GET_CODE (operands[1]) != MEM)
2254 {
2255 rtx op1 = gen_lowpart (SImode, operands[1]);
2256 rtx temp = gen_reg_rtx (SImode);
2257 rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
2258
2259 emit_insn (gen_ashlsi3 (temp, op1, shift));
2260 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
2261 DONE;
2262 }
2263}")
2264
2265(define_insn "extendqisi2_insn"
2266 [(set (match_operand:SI 0 "register_operand" "=d,d")
2267 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
2268 ""
2269 "* return mips_move_1word (operands, insn, FALSE);"
92b4cee1
MM		 2270 [(set_attr "type" "load")
2271 (set_attr "mode" "SI")
8ef30996
MM		 2272 (set_attr "length" "1,2")])
2273
bb621ad7
JW		 2274(define_expand "extendqidi2"
2275 [(set (match_operand:DI 0 "register_operand" "")
2276 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
2277 "TARGET_64BIT"
2278 "
2279{
2280 if (optimize && GET_CODE (operands[1]) == MEM)
2281 operands[1] = force_not_mem (operands[1]);
2282
2283 if (GET_CODE (operands[1]) != MEM)
2284 {
2285 rtx op1 = gen_lowpart (DImode, operands[1]);
2286 rtx temp = gen_reg_rtx (DImode);
2287 rtx shift = gen_rtx (CONST_INT, VOIDmode, 56);
2288
2289 emit_insn (gen_ashldi3 (temp, op1, shift));
2290 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
2291 DONE;
2292 }
2293}")
2294
2295(define_insn "extendqidi2_insn"
2296 [(set (match_operand:DI 0 "register_operand" "=d,d")
2297 (sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
2298 "TARGET_64BIT"
2299 "* return mips_move_1word (operands, insn, FALSE);"
2300 [(set_attr "type" "load")
2301 (set_attr "mode" "DI")
2302 (set_attr "length" "1,2")])
2303
8ef30996
MM		 2304
2305(define_insn "extendsfdf2"
2306 [(set (match_operand:DF 0 "register_operand" "=f")
2307 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2308 "TARGET_HARD_FLOAT"
2309 "cvt.d.s\\t%0,%1"
2310 [(set_attr "type" "fcvt")
2311 (set_attr "mode" "DF")
2312 (set_attr "length" "1")])
2313
2314\f
2315
2316;;
2317;; ....................
2318;;
2319;; CONVERSIONS
2320;;
2321;; ....................
2322
d1460eef
JW		 2323;; The SImode scratch register can not be shared with address regs used for
2324;; operand zero, because then the address in the move instruction will be
2325;; clobbered. We mark the scratch register as early clobbered to prevent this.
2326
c7343333 2327(define_insn "fix_truncdfsi2"
8ef30996
MM		 2328 [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
2329 (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
d1460eef 2330 (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
c7343333 2331 (clobber (match_scratch:DF 3 "=f,*X,f,f"))]
8ef30996
MM		 2332 "TARGET_HARD_FLOAT"
2333 "*
2334{
2335 rtx xoperands[10];
2336
2337 if (which_alternative == 1)
2338 return \"trunc.w.d %0,%1,%2\";
2339
2340 output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
2341
2342 xoperands[0] = operands[0];
2343 xoperands[1] = operands[3];
2344 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
2345 return \"\";
2346}"
92b4cee1
MM		 2347 [(set_attr "type" "fcvt")
2348 (set_attr "mode" "DF")
c7343333 2349 (set_attr "length" "11,9,10,11")])
8ef30996
MM		 2350
2351
c7343333 2352(define_insn "fix_truncsfsi2"
8ef30996
MM		 2353 [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
2354 (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
d1460eef 2355 (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
c7343333 2356 (clobber (match_scratch:SF 3 "=f,*X,f,f"))]
8ef30996
MM		 2357 "TARGET_HARD_FLOAT"
2358 "*
2359{
2360 rtx xoperands[10];
2361
2362 if (which_alternative == 1)
2363 return \"trunc.w.s %0,%1,%2\";
2364
2365 output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
2366
2367 xoperands[0] = operands[0];
2368 xoperands[1] = operands[3];
2369 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
2370 return \"\";
2371}"
92b4cee1
MM		 2372 [(set_attr "type" "fcvt")
2373 (set_attr "mode" "SF")
c7343333 2374 (set_attr "length" "11,9,10,11")])
8ef30996
MM		 2375
2376
bb621ad7
JW		 2377;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
2378;;; but not in the chapter that describes the FPU. It is not mentioned at all
2379;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
2380
2381;;; Deleting this means that we now need two libgcc2.a libraries. One for
2382;;; the 32 bit calling convention and one for the 64 bit calling convention.
2383
2384;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
2385
2386(define_insn "fix_truncdfdi2"
2387 [(set (match_operand:DI 0 "general_operand" "=d,*f,R,o")
2388 (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
2389 (clobber (match_scratch:DF 2 "=f,*X,f,f"))]
2390 "TARGET_HARD_FLOAT && TARGET_64BIT"
2391 "*
2392{
2393 rtx xoperands[10];
2394
2395 if (which_alternative == 1)
2396 return \"trunc.l.d %0,%1\";
2397
2398 output_asm_insn (\"trunc.l.d %2,%1\", operands);
2399
2400 xoperands[0] = operands[0];
2401 xoperands[1] = operands[2];
2402 output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
2403 return \"\";
2404}"
2405 [(set_attr "type" "fcvt")
2406 (set_attr "mode" "DF")
2407 (set_attr "length" "2,1,2,3")])
2408
2409
2410;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
2411;;; but not in the chapter that describes the FPU. It is not mentioned at all
2412;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
2413(define_insn "fix_truncsfdi2"
2414 [(set (match_operand:DI 0 "general_operand" "=d,*f,R,o")
2415 (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
2416 (clobber (match_scratch:DF 2 "=f,*X,f,f"))]
2417 "TARGET_HARD_FLOAT && TARGET_64BIT"
2418 "*
2419{
2420 rtx xoperands[10];
2421
2422 if (which_alternative == 1)
2423 return \"trunc.l.s %0,%1\";
2424
2425 output_asm_insn (\"trunc.l.s %2,%1\", operands);
2426
2427 xoperands[0] = operands[0];
2428 xoperands[1] = operands[2];
2429 output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
2430 return \"\";
2431}"
2432 [(set_attr "type" "fcvt")
2433 (set_attr "mode" "SF")
2434 (set_attr "length" "2,1,2,3")])
2435
2436
8ef30996 2437(define_insn "floatsidf2"
bbdb5552
MM		 2438 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
2439 (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
8ef30996 2440 "TARGET_HARD_FLOAT"
bbdb5552
MM		 2441 "*
2442{
2443 dslots_load_total++;
2444 if (GET_CODE (operands[1]) == MEM)
5cccf78f 2445 return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
bbdb5552
MM		 2446
2447 return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
2448}"
92b4cee1
MM		 2449 [(set_attr "type" "fcvt")
2450 (set_attr "mode" "DF")
bbdb5552 2451 (set_attr "length" "3,4,3")])
8ef30996 2452
c7343333 2453
bb621ad7
JW		 2454(define_insn "floatdidf2"
2455 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
2456 (float:DF (match_operand:DI 1 "nonimmediate_operand" "d,R,m")))]
2457 "TARGET_HARD_FLOAT && TARGET_64BIT"
2458 "*
2459{
2460 dslots_load_total++;
2461 if (GET_CODE (operands[1]) == MEM)
2462 return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
2463
2464 return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
2465}"
2466 [(set_attr "type" "fcvt")
2467 (set_attr "mode" "DF")
2468 (set_attr "length" "3,4,3")])
2469
2470
8ef30996 2471(define_insn "floatsisf2"
bbdb5552
MM		 2472 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
2473 (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
8ef30996 2474 "TARGET_HARD_FLOAT"
bbdb5552
MM		 2475 "*
2476{
2477 dslots_load_total++;
2478 if (GET_CODE (operands[1]) == MEM)
5cccf78f 2479 return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
bbdb5552
MM		 2480
2481 return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
2482}"
92b4cee1
MM		 2483 [(set_attr "type" "fcvt")
2484 (set_attr "mode" "SF")
bbdb5552
MM		 2485 (set_attr "length" "3,4,3")])
2486
8ef30996 2487
bb621ad7
JW		 2488(define_insn "floatdisf2"
2489 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
2490 (float:SF (match_operand:DI 1 "nonimmediate_operand" "d,R,m")))]
2491 "TARGET_HARD_FLOAT && TARGET_64BIT"
2492 "*
2493{
2494 dslots_load_total++;
2495 if (GET_CODE (operands[1]) == MEM)
2496 return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
2497
2498 return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
2499}"
2500 [(set_attr "type" "fcvt")
2501 (set_attr "mode" "SF")
2502 (set_attr "length" "3,4,3")])
2503
2504
8ef30996
MM		 2505(define_expand "fixuns_truncdfsi2"
2506 [(set (match_operand:SI 0 "register_operand" "")
2507 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2508 "TARGET_HARD_FLOAT"
2509 "
2510{
2511 rtx reg1 = gen_reg_rtx (DFmode);
2512 rtx reg2 = gen_reg_rtx (DFmode);
2513 rtx reg3 = gen_reg_rtx (SImode);
2514 rtx label1 = gen_label_rtx ();
2515 rtx label2 = gen_label_rtx ();
2516 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
2517
2518 if (reg1) /* turn off complaints about unreached code */
2519 {
8ef30996
MM		 2520 emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
2521 do_pending_stack_adjust ();
2522
2523 emit_insn (gen_cmpdf (operands[1], reg1));
2524 emit_jump_insn (gen_bge (label1));
2525
2526 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2527 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2528 gen_rtx (LABEL_REF, VOIDmode, label2)));
2529 emit_barrier ();
2530
2531 emit_label (label1);
2532 emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
2533 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
2534
2535 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2536 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2537
2538 emit_label (label2);
2539
2540 /* allow REG_NOTES to be set on last insn (labels don't have enough
2541 fields, and can't be used for REG_NOTES anyway). */
2542 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
2543 DONE;
2544 }
2545}")
2546
c7343333 2547
bb621ad7
JW		 2548(define_expand "fixuns_truncdfdi2"
2549 [(set (match_operand:DI 0 "register_operand" "")
2550 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2551 "TARGET_HARD_FLOAT && TARGET_64BIT"
2552 "
2553{
2554 rtx reg1 = gen_reg_rtx (DFmode);
2555 rtx reg2 = gen_reg_rtx (DFmode);
2556 rtx reg3 = gen_reg_rtx (DImode);
2557 rtx label1 = gen_label_rtx ();
2558 rtx label2 = gen_label_rtx ();
2559 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
2560
2561 if (reg1) /* turn off complaints about unreached code */
2562 {
2563 emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
2564 do_pending_stack_adjust ();
2565
2566 emit_insn (gen_cmpdf (operands[1], reg1));
2567 emit_jump_insn (gen_bge (label1));
2568
2569 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2570 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2571 gen_rtx (LABEL_REF, VOIDmode, label2)));
2572 emit_barrier ();
2573
2574 emit_label (label1);
2575 emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
2576 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
2577 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2578
2579 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2580 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2581
2582 emit_label (label2);
2583
2584 /* allow REG_NOTES to be set on last insn (labels don't have enough
2585 fields, and can't be used for REG_NOTES anyway). */
2586 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
2587 DONE;
2588 }
2589}")
2590
2591
8ef30996
MM		 2592(define_expand "fixuns_truncsfsi2"
2593 [(set (match_operand:SI 0 "register_operand" "")
2594 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2595 "TARGET_HARD_FLOAT"
2596 "
2597{
2598 rtx reg1 = gen_reg_rtx (SFmode);
2599 rtx reg2 = gen_reg_rtx (SFmode);
2600 rtx reg3 = gen_reg_rtx (SImode);
2601 rtx label1 = gen_label_rtx ();
2602 rtx label2 = gen_label_rtx ();
2603 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
2604
2605 if (reg1) /* turn off complaints about unreached code */
2606 {
8ef30996
MM		 2607 emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
2608 do_pending_stack_adjust ();
2609
2610 emit_insn (gen_cmpsf (operands[1], reg1));
2611 emit_jump_insn (gen_bge (label1));
2612
2613 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2614 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2615 gen_rtx (LABEL_REF, VOIDmode, label2)));
2616 emit_barrier ();
2617
2618 emit_label (label1);
2619 emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
2620 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
2621
2622 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2623 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2624
2625 emit_label (label2);
2626
2627 /* allow REG_NOTES to be set on last insn (labels don't have enough
2628 fields, and can't be used for REG_NOTES anyway). */
2629 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
2630 DONE;
2631 }
2632}")
2633
8ef30996 2634
bb621ad7
JW		 2635(define_expand "fixuns_truncsfdi2"
2636 [(set (match_operand:DI 0 "register_operand" "")
2637 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2638 "TARGET_HARD_FLOAT && TARGET_64BIT"
8ef30996
MM		 2639 "
2640{
bb621ad7
JW		 2641 rtx reg1 = gen_reg_rtx (SFmode);
2642 rtx reg2 = gen_reg_rtx (SFmode);
2643 rtx reg3 = gen_reg_rtx (DImode);
2644 rtx label1 = gen_label_rtx ();
2645 rtx label2 = gen_label_rtx ();
2646 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
8ef30996 2647
bb621ad7 2648 if (reg1) /* turn off complaints about unreached code */
8ef30996 2649 {
bb621ad7
JW		 2650 emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
2651 do_pending_stack_adjust ();
8ef30996 2652
bb621ad7
JW		 2653 emit_insn (gen_cmpsf (operands[1], reg1));
2654 emit_jump_insn (gen_bge (label1));
8ef30996 2655
bb621ad7
JW		 2656 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2657 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2658 gen_rtx (LABEL_REF, VOIDmode, label2)));
2659 emit_barrier ();
8ef30996 2660
bb621ad7
JW		 2661 emit_label (label1);
2662 emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
2663 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
2664 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
8ef30996 2665
bb621ad7
JW		 2666 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2667 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
8ef30996 2668
bb621ad7 2669 emit_label (label2);
8ef30996 2670
bb621ad7
JW		 2671 /* allow REG_NOTES to be set on last insn (labels don't have enough
2672 fields, and can't be used for REG_NOTES anyway). */
2673 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
2674 DONE;
8ef30996 2675 }
bb621ad7 2676}")
8ef30996 2677
bb621ad7
JW		 2678\f
2679;;
2680;; ....................
2681;;
2682;; DATA MOVEMENT
2683;;
2684;; ....................
8ef30996 2685
c5563e11
JW		 2686;; Bit field extract patterns which use lwl/lwr.
2687
2688;; ??? There should be DImode variants for 64 bit code, but the current
2689;; bitfield scheme can't handle that. We would need to add new optabs
2690;; in order to make that work.
2691
2692;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
2693;; It isn't clear whether this will give better code.
2694
2695(define_expand "extv"
2696 [(set (match_operand:SI 0 "register_operand" "")
2697 (sign_extract:SI (match_operand:QI 1 "memory_operand" "")
2698 (match_operand:SI 2 "immediate_operand" "")
2699 (match_operand:SI 3 "immediate_operand" "")))]
2700 ""
2701 "
2702{
2703 /* If this isn't a 32 bit field, and it doesn't start on a byte boundary
2704 then fail. */
2705 if (INTVAL (operands[2]) != 32 || (INTVAL (operands[3]) % 8) != 0)
2706 FAIL;
2707
2708 /* This can happen for a 64 bit target, when extracting a value from
2709 a 64 bit union member. extract_bit_field doesn't verify that our
2710 source matches the predicate, so we force it to be a MEM here. */
2711 if (GET_CODE (operands[1]) != MEM)
2712 FAIL;
8ef30996 2713
c5563e11
JW		 2714 /* Otherwise, emit a lwl/lwr pair to load the value. */
2715 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
2716 DONE;
2717}")
2718
2719(define_expand "extzv"
2720 [(set (match_operand:SI 0 "register_operand" "")
2721 (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
2722 (match_operand:SI 2 "immediate_operand" "")
2723 (match_operand:SI 3 "immediate_operand" "")))]
2724 ""
2725 "
2726{
2727 /* If this isn't a 32 bit field, and it doesn't start on a byte boundary
2728 then fail. */
2729 if (INTVAL (operands[2]) != 32 || (INTVAL (operands[3]) % 8) != 0)
2730 FAIL;
2731
2732 /* This can happen for a 64 bit target, when extracting a value from
2733 a 64 bit union member. extract_bit_field doesn't verify that our
2734 source matches the predicate, so we force it to be a MEM here. */
2735 if (GET_CODE (operands[1]) != MEM)
2736 FAIL;
2737
2738 /* Otherwise, emit a lwl/lwr pair to load the value. */
2739 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
2740 DONE;
2741}")
2742
2743(define_expand "insv"
2744 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
2745 (match_operand:SI 1 "immediate_operand" "")
2746 (match_operand:SI 2 "immediate_operand" ""))
2747 (match_operand:SI 3 "register_operand" ""))]
2748 ""
2749 "
2750{
2751 /* If this isn't a 32 bit field, and it doesn't start on a byte boundary
2752 then fail. */
2753 if (INTVAL (operands[1]) != 32 || (INTVAL (operands[2]) % 8) != 0)
2754 FAIL;
2755
2756 /* This can happen for a 64 bit target, when storing into a 32 bit union
2757 member. store_bit_field doesn't verify that our target matches the
2758 predicate, so we force it to be a MEM here. */
2759 if (GET_CODE (operands[0]) != MEM)
2760 FAIL;
2761
2762 /* Otherwise, emit a swl/swr pair to load the value. */
2763 emit_insn (gen_movsi_usw (operands[0], operands[3]));
2764 DONE;
2765}")
2766
2767;; unaligned word moves generated by the bit field patterns
2768
2769(define_insn "movsi_ulw"
2770 [(set (match_operand:SI 0 "register_operand" "=&d,&d")
2771 (unspec [(match_operand:QI 1 "general_operand" "R,o")] 0))]
2772 ""
2773 "*
2774{
2775 rtx offset = const0_rtx;
2776 rtx addr = XEXP (operands[1], 0);
2777 rtx mem_addr = eliminate_constant_term (addr, &offset);
2778 char *ret;
2779
2780 if (TARGET_STATS)
2781 mips_count_memory_refs (operands[1], 2);
2782
2783 /* The stack/frame pointers are always aligned, so we can convert
2784 to the faster lw if we are referencing an aligned stack location. */
2785
2786 if ((INTVAL (offset) & 3) == 0
2787 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
2788 ret = \"lw\\t%0,%1\";
2789 else
2790 ret = \"ulw\\t%0,%1\";
2791
2792 return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
2793}"
2794 [(set_attr "type" "load,load")
2795 (set_attr "mode" "SI")
2796 (set_attr "length" "2,4")])
2797
2798(define_insn "movsi_usw"
2799 [(set (match_operand:QI 0 "memory_operand" "=R,o")
2800 (unspec [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
2801 ""
2802 "*
2803{
2804 rtx offset = const0_rtx;
2805 rtx addr = XEXP (operands[0], 0);
2806 rtx mem_addr = eliminate_constant_term (addr, &offset);
2807
2808 if (TARGET_STATS)
2809 mips_count_memory_refs (operands[0], 2);
2810
2811 /* The stack/frame pointers are always aligned, so we can convert
2812 to the faster sw if we are referencing an aligned stack location. */
2813
2814 if ((INTVAL (offset) & 3) == 0
2815 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
2816 return \"sw\\t%1,%0\";
2817
2818 return \"usw\\t%z1,%0\";
2819}"
2820 [(set_attr "type" "store")
2821 (set_attr "mode" "SI")
2822 (set_attr "length" "2,4")])
ed50ab35 2823
8ef30996
MM		 2824;; 64-bit integer moves
2825
2826;; Unlike most other insns, the move insns can't be split with
2827;; different predicates, because register spilling and other parts of
2828;; the compiler, have memoized the insn number already.
2829
ed50ab35
MM		 2830(define_expand "movdi"
2831 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2832 (match_operand:DI 1 "general_operand" ""))]
2833 ""
2834 "
2835{
2836 if ((reload_in_progress | reload_completed) == 0
2837 && !register_operand (operands[0], DImode)
2838 && !register_operand (operands[1], DImode)
2839 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
2840 && operands[1] != CONST0_RTX (DImode))
2841 {
2842 rtx temp = force_reg (DImode, operands[1]);
2843 emit_move_insn (operands[0], temp);
2844 DONE;
2845 }
2846}")
2847
2848(define_insn "movdi_internal"
6d518002
MM		 2849 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*d,*x")
2850 (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,*x,*d"))]
bb621ad7
JW		 2851 "!TARGET_64BIT
2852 && (register_operand (operands[0], DImode)
2853 || register_operand (operands[1], DImode)
2854 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
2855 || operands[1] == CONST0_RTX (DImode))"
8ef30996 2856 "* return mips_move_2words (operands, insn); "
6d518002 2857 [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo")
92b4cee1 2858 (set_attr "mode" "DI")
bb621ad7 2859 (set_attr "length" "2,4,2,4,2,4,2,2")])
8ef30996
MM		 2860
2861(define_split
2862 [(set (match_operand:DI 0 "register_operand" "")
2863 (match_operand:DI 1 "register_operand" ""))]
bb621ad7 2864 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2865 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2866 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
2867
2868 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
2869 (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
2870 "")
2871
bb621ad7
JW		 2872(define_insn "movdi_internal2"
2873 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*x")
2874 (match_operand:DI 1 "general_operand" " d,S,IKL,Mnis,R,m,dJ,dJ,*x,*d"))]
2875 "TARGET_64BIT
2876 && (register_operand (operands[0], DImode)
2877 || register_operand (operands[1], DImode)
2878 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
2879 || operands[1] == CONST0_RTX (DImode))"
2880 "* return mips_move_2words (operands, insn); "
2881 [(set_attr "type" "move,load,arith,arith,load,load,store,store,hilo,hilo")
2882 (set_attr "mode" "DI")
2883 (set_attr "length" "1,2,1,2,1,2,1,2,1,1")])
2884
8ef30996
MM		 2885
2886;; 32-bit Integer moves
2887
2888(define_split
2889 [(set (match_operand:SI 0 "register_operand" "")
2890 (match_operand:SI 1 "large_int" ""))]
26b8e6e5 2891 "!TARGET_DEBUG_D_MODE"
8ef30996
MM		 2892 [(set (match_dup 0)
2893 (match_dup 2))
2894 (set (match_dup 0)
2895 (ior:SI (match_dup 0)
2896 (match_dup 3)))]
2897 "
2898{
2899 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff0000);
2900 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0x0000ffff);
2901}")
2902
2903;; Unlike most other insns, the move insns can't be split with
2904;; different predicates, because register spilling and other parts of
2905;; the compiler, have memoized the insn number already.
2906
f3b39eba
MM		 2907(define_expand "movsi"
2908 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2909 (match_operand:SI 1 "general_operand" ""))]
2910 ""
ed50ab35
MM		 2911 "
2912{
92544bdf
ILT		 2913 /* If we are generating embedded PIC code, and we are referring to a
2914 symbol in the .text section, we must use an offset from the start
2915 of the function. */
2916 if (TARGET_EMBEDDED_PIC
2917 && (GET_CODE (operands[1]) == LABEL_REF
2918 || (GET_CODE (operands[1]) == SYMBOL_REF
2919 && ! SYMBOL_REF_FLAG (operands[1]))))
2920 {
2921 rtx temp;
2922
2923 temp = embedded_pic_offset (operands[1]);
2924 temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
2925 force_reg (SImode, temp));
2926 emit_move_insn (operands[0], force_reg (SImode, temp));
2927 DONE;
2928 }
2929
5a5b76a2
JW		 2930 /* If operands[1] is a constant address illegal for pic, then we need to
2931 handle it just like LEGITIMIZE_ADDRESS does. */
2932 if (flag_pic && pic_address_needs_scratch (operands[1]))
2933 {
2934 rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
2935 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
2936
2937 if (! SMALL_INT (temp2))
2938 temp2 = force_reg (SImode, temp2);
2939
2940 emit_move_insn (operands[0], gen_rtx (PLUS, SImode, temp, temp2));
2941 DONE;
2942 }
2943
ed50ab35
MM		 2944 if ((reload_in_progress | reload_completed) == 0
2945 && !register_operand (operands[0], SImode)
2946 && !register_operand (operands[1], SImode)
2947 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
2948 {
2949 rtx temp = force_reg (SImode, operands[1]);
2950 emit_move_insn (operands[0], temp);
2951 DONE;
2952 }
2953}")
f3b39eba 2954
0fb5ac6f
MM		 2955;; The difference between these two is whether or not ints are allowed
2956;; in FP registers (off by default, use -mdebugh to enable).
2957
2958(define_insn "movsi_internal1"
252e25c6
MM		 2959 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*d")
2960 (match_operand:SI 1 "general_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,*d,*x"))]
ed50ab35
MM		 2961 "TARGET_DEBUG_H_MODE
2962 && (register_operand (operands[0], SImode)
2963 || register_operand (operands[1], SImode)
2964 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
bb621ad7 2965 "* return mips_move_1word (operands, insn, FALSE);"
c7343333 2966 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo")
92b4cee1 2967 (set_attr "mode" "SI")
c7343333 2968 (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1")])
8ef30996 2969
0fb5ac6f
MM		 2970(define_insn "movsi_internal2"
2971 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*d,*x")
2972 (match_operand:SI 1 "general_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,*x,*d"))]
ed50ab35
MM		 2973 "!TARGET_DEBUG_H_MODE
2974 && (register_operand (operands[0], SImode)
2975 || register_operand (operands[1], SImode)
2976 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
bb621ad7 2977 "* return mips_move_1word (operands, insn, FALSE);"
c7343333 2978 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo")
0fb5ac6f 2979 (set_attr "mode" "SI")
c7343333 2980 (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1")])
0fb5ac6f
MM		 2981
2982
8ef30996
MM		 2983;; 16-bit Integer moves
2984
2985;; Unlike most other insns, the move insns can't be split with
2986;; different predicates, because register spilling and other parts of
2987;; the compiler, have memoized the insn number already.
2988;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
2989
0fb5ac6f
MM		 2990(define_expand "movhi"
2991 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2992 (match_operand:HI 1 "general_operand" ""))]
8ef30996 2993 ""
ed50ab35
MM		 2994 "
2995{
2996 if ((reload_in_progress | reload_completed) == 0
2997 && !register_operand (operands[0], HImode)
2998 && !register_operand (operands[1], HImode)
2999 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
3000 {
3001 rtx temp = force_reg (HImode, operands[1]);
3002 emit_move_insn (operands[0], temp);
3003 DONE;
3004 }
3005}")
0fb5ac6f
MM		 3006
3007;; The difference between these two is whether or not ints are allowed
3008;; in FP registers (off by default, use -mdebugh to enable).
3009
3010(define_insn "movhi_internal1"
252e25c6
MM		 3011 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
3012 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
ed50ab35
MM		 3013 "TARGET_DEBUG_H_MODE
3014 && (register_operand (operands[0], HImode)
3015 || register_operand (operands[1], HImode)
3016 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
8ef30996
MM		 3017 "* return mips_move_1word (operands, insn, TRUE);"
3018 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
92b4cee1 3019 (set_attr "mode" "HI")
8ef30996
MM		 3020 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
3021
0fb5ac6f
MM		 3022(define_insn "movhi_internal2"
3023 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
3024 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
ed50ab35
MM		 3025 "!TARGET_DEBUG_H_MODE
3026 && (register_operand (operands[0], HImode)
3027 || register_operand (operands[1], HImode)
3028 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
0fb5ac6f
MM		 3029 "* return mips_move_1word (operands, insn, TRUE);"
3030 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
3031 (set_attr "mode" "HI")
3032 (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
3033
3034
8ef30996
MM		 3035;; 8-bit Integer moves
3036
3037;; Unlike most other insns, the move insns can't be split with
3038;; different predicates, because register spilling and other parts of
3039;; the compiler, have memoized the insn number already.
3040;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
3041
0fb5ac6f
MM		 3042(define_expand "movqi"
3043 [(set (match_operand:QI 0 "nonimmediate_operand" "")
3044 (match_operand:QI 1 "general_operand" ""))]
8ef30996 3045 ""
ed50ab35
MM		 3046 "
3047{
3048 if ((reload_in_progress | reload_completed) == 0
3049 && !register_operand (operands[0], QImode)
3050 && !register_operand (operands[1], QImode)
3051 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
3052 {
3053 rtx temp = force_reg (QImode, operands[1]);
3054 emit_move_insn (operands[0], temp);
3055 DONE;
3056 }
3057}")
0fb5ac6f
MM		 3058
3059;; The difference between these two is whether or not ints are allowed
3060;; in FP registers (off by default, use -mdebugh to enable).
3061
3062(define_insn "movqi_internal1"
252e25c6
MM		 3063 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
3064 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
ed50ab35
MM		 3065 "TARGET_DEBUG_H_MODE
3066 && (register_operand (operands[0], QImode)
3067 || register_operand (operands[1], QImode)
3068 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
8ef30996
MM		 3069 "* return mips_move_1word (operands, insn, TRUE);"
3070 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
92b4cee1 3071 (set_attr "mode" "QI")
8ef30996
MM		 3072 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
3073
0fb5ac6f
MM		 3074(define_insn "movqi_internal2"
3075 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
3076 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
ed50ab35
MM		 3077 "!TARGET_DEBUG_H_MODE
3078 && (register_operand (operands[0], QImode)
3079 || register_operand (operands[1], QImode)
3080 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
0fb5ac6f
MM		 3081 "* return mips_move_1word (operands, insn, TRUE);"
3082 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
3083 (set_attr "mode" "QI")
3084 (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
3085
8ef30996
MM		 3086
3087;; 32-bit floating point moves
3088
ed50ab35
MM		 3089(define_expand "movsf"
3090 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3091 (match_operand:SF 1 "general_operand" ""))]
3092 ""
3093 "
3094{
3095 if ((reload_in_progress | reload_completed) == 0
3096 && !register_operand (operands[0], SFmode)
3097 && !register_operand (operands[1], SFmode)
3098 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
3099 && operands[1] != CONST0_RTX (SFmode))
3100 {
3101 rtx temp = force_reg (SFmode, operands[1]);
3102 emit_move_insn (operands[0], temp);
3103 DONE;
3104 }
3105}")
3106
b0193a92 3107(define_insn "movsf_internal1"
8ef30996 3108 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
bb621ad7 3109 (match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))]
b0193a92
MM		 3110 "TARGET_HARD_FLOAT
3111 && (register_operand (operands[0], SFmode)
3112 || register_operand (operands[1], SFmode)
3113 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3114 || operands[1] == CONST0_RTX (SFmode))"
8ef30996
MM		 3115 "* return mips_move_1word (operands, insn, FALSE);"
3116 [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
92b4cee1 3117 (set_attr "mode" "SF")
8ef30996
MM		 3118 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")])
3119
ed50ab35 3120
b0193a92
MM		 3121(define_insn "movsf_internal2"
3122 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
bb621ad7 3123 (match_operand:SF 1 "general_operand" " Gd,R,Fm,d,d"))]
b0193a92
MM		 3124 "TARGET_SOFT_FLOAT
3125 && (register_operand (operands[0], SFmode)
3126 || register_operand (operands[1], SFmode)
3127 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3128 || operands[1] == CONST0_RTX (SFmode))"
3129 "* return mips_move_1word (operands, insn, FALSE);"
3130 [(set_attr "type" "move,load,load,store,store")
3131 (set_attr "mode" "SF")
3132 (set_attr "length" "1,1,2,1,2")])
3133
3134
8ef30996
MM		 3135;; 64-bit floating point moves
3136
ed50ab35
MM		 3137(define_expand "movdf"
3138 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3139 (match_operand:DF 1 "general_operand" ""))]
3140 ""
3141 "
3142{
3143 if ((reload_in_progress | reload_completed) == 0
3144 && !register_operand (operands[0], DFmode)
3145 && !register_operand (operands[1], DFmode)
3146 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
3147 && operands[1] != CONST0_RTX (DFmode))
3148 {
3149 rtx temp = force_reg (DFmode, operands[1]);
3150 emit_move_insn (operands[0], temp);
3151 DONE;
3152 }
3153}")
3154
b0193a92 3155(define_insn "movdf_internal1"
8ef30996 3156 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,o,f,*f,*d,*d,*d,*d,*R,*o")
bb621ad7 3157 (match_operand:DF 1 "general_operand" "f,R,o,fG,fG,F,*d,*f,*d*G,*R,*o*F,*d,*d"))]
64d8baf9 3158 "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT)
b0193a92
MM		 3159 && (register_operand (operands[0], DFmode)
3160 || register_operand (operands[1], DFmode)
3161 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3162 || operands[1] == CONST0_RTX (DFmode))"
8ef30996
MM		 3163 "* return mips_move_2words (operands, insn); "
3164 [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
92b4cee1 3165 (set_attr "mode" "DF")
8ef30996
MM		 3166 (set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")])
3167
64d8baf9
JW		 3168(define_insn "movdf_internal1a"
3169 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,o,o,f,*d,*d,*d,*o,*R")
3170 (match_operand:DF 1 "general_operand" " f,o,f,G,f,G,F,*F,*o,*R,*d,*d"))]
3171 "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT)
3172 && (register_operand (operands[0], DFmode)
3173 || register_operand (operands[1], DFmode))
3174 || (GET_CODE (operands [0]) == MEM
3175 && ((GET_CODE (operands[1]) == CONST_INT
3176 && INTVAL (operands[1]) == 0)
3177 || operands[1] == CONST0_RTX (DFmode)))"
3178 "* return mips_move_2words (operands, insn); "
3179 [(set_attr "type" "move,load,store,store,store,store,load,load,load,load,store,store")
3180 (set_attr "mode" "DF")
3181 (set_attr "length" "1,2,1,1,2,2,2,2,2,1,2,1")])
3182
b0193a92
MM		 3183(define_insn "movdf_internal2"
3184 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,o")
bb621ad7 3185 (match_operand:DF 1 "general_operand" "dG,R,oF,d,d"))]
b0193a92
MM		 3186 "TARGET_SOFT_FLOAT
3187 && (register_operand (operands[0], DFmode)
3188 || register_operand (operands[1], DFmode)
3189 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3190 || operands[1] == CONST0_RTX (DFmode))"
3191 "* return mips_move_2words (operands, insn); "
3192 [(set_attr "type" "move,load,load,store,store")
3193 (set_attr "mode" "DF")
3194 (set_attr "length" "2,2,4,2,4")])
3195
8ef30996
MM		 3196(define_split
3197 [(set (match_operand:DF 0 "register_operand" "")
3198 (match_operand:DF 1 "register_operand" ""))]
26b8e6e5 3199 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3200 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3201 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
3202
3203 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
3204 (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
3205 "")
3206
26b8e6e5 3207\f
8ef30996
MM		 3208;; Block moves, see mips.c for more details.
3209;; Argument 0 is the destination
3210;; Argument 1 is the source
3211;; Argument 2 is the length
3212;; Argument 3 is the alignment
3213
3214(define_expand "movstrsi"
3215 [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
3216 (mem:BLK (match_operand:BLK 1 "general_operand" "")))
3217 (use (match_operand:SI 2 "arith32_operand" ""))
3218 (use (match_operand:SI 3 "immediate_operand" ""))])]
3219 ""
3220 "
3221{
3222 if (operands[0]) /* avoid unused code messages */
3223 {
3224 expand_block_move (operands);
3225 DONE;
3226 }
3227}")
3228
842eb20e
MM		 3229;; Insn generated by block moves
3230
3231(define_insn "movstrsi_internal"
26b8e6e5
MM		 3232 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
3233 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
3234 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
3235 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
3236 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
3237 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
3238 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
3239 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
3240 (use (const_int 0))] ;; normal block move
3241 ""
3242 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
842eb20e
MM		 3243 [(set_attr "type" "multi")
3244 (set_attr "mode" "none")
3245 (set_attr "length" "20")])
3246
26b8e6e5
MM		 3247;; Split a block move into 2 parts, the first part is everything
3248;; except for the last move, and the second part is just the last
3249;; store, which is exactly 1 instruction (ie, not a usw), so it can
3250;; fill a delay slot. This also prevents a bug in delayed branches
3251;; from showing up, which reuses one of the registers in our clobbers.
3252
3253(define_split
3254 [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3255 (mem:BLK (match_operand:SI 1 "register_operand" "")))
3256 (clobber (match_operand:SI 4 "register_operand" ""))
3257 (clobber (match_operand:SI 5 "register_operand" ""))
3258 (clobber (match_operand:SI 6 "register_operand" ""))
3259 (clobber (match_operand:SI 7 "register_operand" ""))
3260 (use (match_operand:SI 2 "small_int" ""))
3261 (use (match_operand:SI 3 "small_int" ""))
3262 (use (const_int 0))]
3263
3264 "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
3265
3266 ;; All but the last move
3267 [(parallel [(set (mem:BLK (match_dup 0))
3268 (mem:BLK (match_dup 1)))
3269 (clobber (match_dup 4))
3270 (clobber (match_dup 5))
3271 (clobber (match_dup 6))
3272 (clobber (match_dup 7))
3273 (use (match_dup 2))
3274 (use (match_dup 3))
3275 (use (const_int 1))])
3276
3277 ;; The last store, so it can fill a delay slot
3278 (parallel [(set (mem:BLK (match_dup 0))
3279 (mem:BLK (match_dup 1)))
3280 (clobber (match_dup 4))
3281 (clobber (match_dup 5))
3282 (clobber (match_dup 6))
3283 (clobber (match_dup 7))
3284 (use (match_dup 2))
3285 (use (match_dup 3))
3286 (use (const_int 2))])]
3287
3288 "")
3289
3290(define_insn "movstrsi_internal2"
3291 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
3292 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
3293 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
3294 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
3295 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
3296 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
3297 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
3298 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
3299 (use (const_int 1))] ;; all but last store
3300 ""
3301 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
3302 [(set_attr "type" "multi")
3303 (set_attr "mode" "none")
3304 (set_attr "length" "20")])
3305
3306(define_insn "movstrsi_internal3"
3307 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
3308 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
3309 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
3310 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
3311 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
3312 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
3313 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
3314 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
bb621ad7 3315 (use (const_int 2))] ;; just last store of block move
26b8e6e5
MM		 3316 ""
3317 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
3318 [(set_attr "type" "store")
3319 (set_attr "mode" "none")
3320 (set_attr "length" "1")])
3321
8ef30996
MM		 3322\f
3323;;
3324;; ....................
3325;;
3326;; SHIFTS
3327;;
3328;; ....................
3329
3330(define_insn "ashlsi3"
3331 [(set (match_operand:SI 0 "register_operand" "=d")
3332 (ashift:SI (match_operand:SI 1 "register_operand" "d")
3333 (match_operand:SI 2 "arith_operand" "dI")))]
3334 ""
3335 "*
3336{
3337 if (GET_CODE (operands[2]) == CONST_INT)
3338 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3339
3340 return \"sll\\t%0,%1,%2\";
3341}"
3342 [(set_attr "type" "arith")
3343 (set_attr "mode" "SI")
3344 (set_attr "length" "1")])
3345
3346
3347(define_expand "ashldi3"
3348 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3349 (ashift:DI (match_operand:DI 1 "register_operand" "")
3350 (match_operand:SI 2 "arith_operand" "")))
3351 (clobber (match_dup 3))])]
bb621ad7
JW		 3352 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
3353 "
3354{
3355 if (TARGET_64BIT)
3356 {
3357 emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
3358 operands[2]));
3359 DONE;
3360 }
3361
3362 operands[3] = gen_reg_rtx (SImode);
3363}")
8ef30996
MM		 3364
3365
3366(define_insn "ashldi3_internal"
0fb5ac6f 3367 [(set (match_operand:DI 0 "register_operand" "=&d")
8ef30996
MM		 3368 (ashift:DI (match_operand:DI 1 "register_operand" "d")
3369 (match_operand:SI 2 "register_operand" "d")))
3370 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 3371 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
8ef30996
MM		 3372 "*
3373{
3374 operands[4] = const0_rtx;
3375 dslots_jump_total += 3;
3376 dslots_jump_filled += 2;
3377
3378 return \"sll\\t%3,%2,26\\n\\
3379\\tbgez\\t%3,1f\\n\\
3380\\tsll\\t%M0,%L1,%2\\n\\
3381\\t%(b\\t3f\\n\\
3382\\tmove\\t%L0,%z4%)\\n\\
3383\\n\\
33841:\\n\\
3385\\t%(beq\\t%3,%z4,2f\\n\\
3386\\tsll\\t%M0,%M1,%2%)\\n\\
3387\\n\\
3388\\tsubu\\t%3,%z4,%2\\n\\
3389\\tsrl\\t%3,%L1,%3\\n\\
3390\\tor\\t%M0,%M0,%3\\n\\
33912:\\n\\
3392\\tsll\\t%L0,%L1,%2\\n\\
33933:\";
3394}"
3395 [(set_attr "type" "darith")
3396 (set_attr "mode" "SI")
3397 (set_attr "length" "12")])
3398
3399
3400(define_insn "ashldi3_internal2"
3401 [(set (match_operand:DI 0 "register_operand" "=d")
3402 (ashift:DI (match_operand:DI 1 "register_operand" "d")
3403 (match_operand:SI 2 "small_int" "IJK")))
3404 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 3405 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
8ef30996
MM		 3406 "*
3407{
3408 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3409 operands[4] = const0_rtx;
3410 return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
3411}"
3412 [(set_attr "type" "darith")
3413 (set_attr "mode" "DI")
3414 (set_attr "length" "2")])
3415
3416
3417(define_split
3418 [(set (match_operand:DI 0 "register_operand" "")
3419 (ashift:DI (match_operand:DI 1 "register_operand" "")
3420 (match_operand:SI 2 "small_int" "")))
3421 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3422 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3423 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3424 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3425 && (INTVAL (operands[2]) & 32) != 0"
3426
3427 [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
3428 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
3429
3430 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3431
3432
3433(define_split
3434 [(set (match_operand:DI 0 "register_operand" "")
3435 (ashift:DI (match_operand:DI 1 "register_operand" "")
3436 (match_operand:SI 2 "small_int" "")))
3437 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3438 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3439 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3440 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3441 && (INTVAL (operands[2]) & 32) != 0"
3442
3443 [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
3444 (set (subreg:SI (match_dup 0) 1) (const_int 0))]
3445
3446 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3447
3448
3449(define_insn "ashldi3_internal3"
3450 [(set (match_operand:DI 0 "register_operand" "=d")
3451 (ashift:DI (match_operand:DI 1 "register_operand" "d")
3452 (match_operand:SI 2 "small_int" "IJK")))
3453 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 3454 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3455 && (INTVAL (operands[2]) & 63) < 32
3456 && (INTVAL (operands[2]) & 63) != 0"
3457 "*
3458{
3459 int amount = INTVAL (operands[2]);
3460
3461 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3462 operands[4] = const0_rtx;
3463 operands[5] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3464
3465 return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
3466}"
3467 [(set_attr "type" "darith")
3468 (set_attr "mode" "DI")
3469 (set_attr "length" "4")])
3470
3471
3472(define_split
3473 [(set (match_operand:DI 0 "register_operand" "")
3474 (ashift:DI (match_operand:DI 1 "register_operand" "")
3475 (match_operand:SI 2 "small_int" "")))
3476 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3477 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3478 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3479 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3480 && (INTVAL (operands[2]) & 63) < 32
3481 && (INTVAL (operands[2]) & 63) != 0"
3482
3483 [(set (subreg:SI (match_dup 0) 1)
3484 (ashift:SI (subreg:SI (match_dup 1) 1)
3485 (match_dup 2)))
3486
3487 (set (match_dup 3)
3488 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
3489 (match_dup 4)))
3490
3491 (set (subreg:SI (match_dup 0) 1)
3492 (ior:SI (subreg:SI (match_dup 0) 1)
3493 (match_dup 3)))
3494
3495 (set (subreg:SI (match_dup 0) 0)
3496 (ashift:SI (subreg:SI (match_dup 1) 0)
3497 (match_dup 2)))]
3498 "
3499{
3500 int amount = INTVAL (operands[2]);
3501 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3502 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3503}")
3504
3505
3506(define_split
3507 [(set (match_operand:DI 0 "register_operand" "")
3508 (ashift:DI (match_operand:DI 1 "register_operand" "")
3509 (match_operand:SI 2 "small_int" "")))
3510 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3511 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3512 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3513 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3514 && (INTVAL (operands[2]) & 63) < 32
3515 && (INTVAL (operands[2]) & 63) != 0"
3516
3517 [(set (subreg:SI (match_dup 0) 0)
3518 (ashift:SI (subreg:SI (match_dup 1) 0)
3519 (match_dup 2)))
3520
3521 (set (match_dup 3)
3522 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
3523 (match_dup 4)))
3524
3525 (set (subreg:SI (match_dup 0) 0)
3526 (ior:SI (subreg:SI (match_dup 0) 0)
3527 (match_dup 3)))
3528
3529 (set (subreg:SI (match_dup 0) 1)
3530 (ashift:SI (subreg:SI (match_dup 1) 1)
3531 (match_dup 2)))]
3532 "
3533{
3534 int amount = INTVAL (operands[2]);
3535 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3536 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3537}")
3538
3539
bb621ad7
JW		 3540(define_insn "ashldi3_internal4"
3541 [(set (match_operand:DI 0 "register_operand" "=d")
3542 (ashift:DI (match_operand:DI 1 "register_operand" "d")
3543 (match_operand:SI 2 "arith_operand" "dI")))]
3544 "TARGET_64BIT"
3545 "*
3546{
3547 if (GET_CODE (operands[2]) == CONST_INT)
3548 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
3549
3550 return \"dsll\\t%0,%1,%2\";
3551}"
3552 [(set_attr "type" "arith")
3553 (set_attr "mode" "DI")
3554 (set_attr "length" "1")])
3555
3556
8ef30996
MM		 3557(define_insn "ashrsi3"
3558 [(set (match_operand:SI 0 "register_operand" "=d")
3559 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
3560 (match_operand:SI 2 "arith_operand" "dI")))]
3561 ""
3562 "*
3563{
3564 if (GET_CODE (operands[2]) == CONST_INT)
3565 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3566
3567 return \"sra\\t%0,%1,%2\";
3568}"
3569 [(set_attr "type" "arith")
3570 (set_attr "mode" "SI")
3571 (set_attr "length" "1")])
3572
3573
3574(define_expand "ashrdi3"
3575 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3576 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3577 (match_operand:SI 2 "arith_operand" "")))
3578 (clobber (match_dup 3))])]
bb621ad7
JW		 3579 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
3580 "
3581{
3582 if (TARGET_64BIT)
3583 {
3584 emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
3585 operands[2]));
3586 DONE;
3587 }
3588
3589 operands[3] = gen_reg_rtx (SImode);
3590}")
8ef30996
MM		 3591
3592
3593(define_insn "ashrdi3_internal"
0fb5ac6f 3594 [(set (match_operand:DI 0 "register_operand" "=&d")
8ef30996
MM		 3595 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3596 (match_operand:SI 2 "register_operand" "d")))
3597 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 3598 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
8ef30996
MM		 3599 "*
3600{
3601 operands[4] = const0_rtx;
3602 dslots_jump_total += 3;
3603 dslots_jump_filled += 2;
3604
3605 return \"sll\\t%3,%2,26\\n\\
3606\\tbgez\\t%3,1f\\n\\
3607\\tsra\\t%L0,%M1,%2\\n\\
3608\\t%(b\\t3f\\n\\
3609\\tsra\\t%M0,%M1,31%)\\n\\
3610\\n\\
36111:\\n\\
3612\\t%(beq\\t%3,%z4,2f\\n\\
3613\\tsrl\\t%L0,%L1,%2%)\\n\\
3614\\n\\
3615\\tsubu\\t%3,%z4,%2\\n\\
3616\\tsll\\t%3,%M1,%3\\n\\
3617\\tor\\t%L0,%L0,%3\\n\\
36182:\\n\\
3619\\tsra\\t%M0,%M1,%2\\n\\
36203:\";
3621}"
3622 [(set_attr "type" "darith")
3623 (set_attr "mode" "DI")
3624 (set_attr "length" "12")])
3625
3626
3627(define_insn "ashrdi3_internal2"
3628 [(set (match_operand:DI 0 "register_operand" "=d")
3629 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3630 (match_operand:SI 2 "small_int" "IJK")))
3631 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 3632 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
8ef30996
MM		 3633 "*
3634{
3635 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3636 return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
3637}"
3638 [(set_attr "type" "darith")
3639 (set_attr "mode" "DI")
3640 (set_attr "length" "2")])
3641
3642
3643(define_split
3644 [(set (match_operand:DI 0 "register_operand" "")
3645 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3646 (match_operand:SI 2 "small_int" "")))
3647 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3648 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3649 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3650 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3651 && (INTVAL (operands[2]) & 32) != 0"
3652
3653 [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
3654 (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))]
3655
3656 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3657
3658
3659(define_split
3660 [(set (match_operand:DI 0 "register_operand" "")
3661 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3662 (match_operand:SI 2 "small_int" "")))
3663 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3664 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3665 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3666 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3667 && (INTVAL (operands[2]) & 32) != 0"
3668
3669 [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
3670 (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
3671
3672 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3673
3674
3675(define_insn "ashrdi3_internal3"
3676 [(set (match_operand:DI 0 "register_operand" "=d")
3677 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3678 (match_operand:SI 2 "small_int" "IJK")))
3679 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 3680 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3681 && (INTVAL (operands[2]) & 63) < 32
3682 && (INTVAL (operands[2]) & 63) != 0"
3683 "*
3684{
3685 int amount = INTVAL (operands[2]);
3686
3687 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3688 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3689
3690 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
3691}"
3692 [(set_attr "type" "darith")
3693 (set_attr "mode" "DI")
3694 (set_attr "length" "4")])
3695
3696
3697(define_split
3698 [(set (match_operand:DI 0 "register_operand" "")
3699 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3700 (match_operand:SI 2 "small_int" "")))
3701 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3702 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3703 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3704 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3705 && (INTVAL (operands[2]) & 63) < 32
3706 && (INTVAL (operands[2]) & 63) != 0"
3707
3708 [(set (subreg:SI (match_dup 0) 0)
3709 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
3710 (match_dup 2)))
3711
3712 (set (match_dup 3)
3713 (ashift:SI (subreg:SI (match_dup 1) 1)
3714 (match_dup 4)))
3715
3716 (set (subreg:SI (match_dup 0) 0)
3717 (ior:SI (subreg:SI (match_dup 0) 0)
3718 (match_dup 3)))
3719
3720 (set (subreg:SI (match_dup 0) 1)
3721 (ashiftrt:SI (subreg:SI (match_dup 1) 1)
3722 (match_dup 2)))]
3723 "
3724{
3725 int amount = INTVAL (operands[2]);
3726 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3727 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3728}")
3729
3730
3731(define_split
3732 [(set (match_operand:DI 0 "register_operand" "")
3733 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3734 (match_operand:SI 2 "small_int" "")))
3735 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3736 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3737 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3738 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3739 && (INTVAL (operands[2]) & 63) < 32
3740 && (INTVAL (operands[2]) & 63) != 0"
3741
3742 [(set (subreg:SI (match_dup 0) 1)
3743 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
3744 (match_dup 2)))
3745
3746 (set (match_dup 3)
3747 (ashift:SI (subreg:SI (match_dup 1) 0)
3748 (match_dup 4)))
3749
3750 (set (subreg:SI (match_dup 0) 1)
3751 (ior:SI (subreg:SI (match_dup 0) 1)
3752 (match_dup 3)))
3753
3754 (set (subreg:SI (match_dup 0) 0)
3755 (ashiftrt:SI (subreg:SI (match_dup 1) 0)
3756 (match_dup 2)))]
3757 "
3758{
3759 int amount = INTVAL (operands[2]);
3760 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3761 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3762}")
3763
3764
bb621ad7
JW		 3765(define_insn "ashrdi3_internal4"
3766 [(set (match_operand:DI 0 "register_operand" "=d")
3767 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3768 (match_operand:SI 2 "arith_operand" "dI")))]
3769 "TARGET_64BIT"
3770 "*
3771{
3772 if (GET_CODE (operands[2]) == CONST_INT)
3773 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
3774
3775 return \"dsra\\t%0,%1,%2\";
3776}"
3777 [(set_attr "type" "arith")
3778 (set_attr "mode" "DI")
3779 (set_attr "length" "1")])
3780
3781
8ef30996
MM		 3782(define_insn "lshrsi3"
3783 [(set (match_operand:SI 0 "register_operand" "=d")
3784 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
3785 (match_operand:SI 2 "arith_operand" "dI")))]
3786 ""
3787 "*
3788{
3789 if (GET_CODE (operands[2]) == CONST_INT)
3790 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3791
3792 return \"srl\\t%0,%1,%2\";
3793}"
3794 [(set_attr "type" "arith")
3795 (set_attr "mode" "SI")
3796 (set_attr "length" "1")])
3797
3798
3799(define_expand "lshrdi3"
3800 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3801 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3802 (match_operand:SI 2 "arith_operand" "")))
3803 (clobber (match_dup 3))])]
bb621ad7
JW		 3804 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
3805 "
3806{
3807 if (TARGET_64BIT)
3808 {
3809 emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
3810 operands[2]));
3811 DONE;
3812 }
3813
3814 operands[3] = gen_reg_rtx (SImode);
3815}")
8ef30996
MM		 3816
3817
3818(define_insn "lshrdi3_internal"
3819 [(set (match_operand:DI 0 "register_operand" "=&d")
3820 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3821 (match_operand:SI 2 "register_operand" "d")))
3822 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 3823 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
8ef30996
MM		 3824 "*
3825{
3826 operands[4] = const0_rtx;
3827 dslots_jump_total += 3;
3828 dslots_jump_filled += 2;
3829
3830 return \"sll\\t%3,%2,26\\n\\
3831\\tbgez\\t%3,1f\\n\\
3832\\tsrl\\t%L0,%M1,%2\\n\\
3833\\t%(b\\t3f\\n\\
3834\\tmove\\t%M0,%z4%)\\n\\
3835\\n\\
38361:\\n\\
3837\\t%(beq\\t%3,%z4,2f\\n\\
3838\\tsrl\\t%L0,%L1,%2%)\\n\\
3839\\n\\
3840\\tsubu\\t%3,%z4,%2\\n\\
3841\\tsll\\t%3,%M1,%3\\n\\
3842\\tor\\t%L0,%L0,%3\\n\\
38432:\\n\\
3844\\tsrl\\t%M0,%M1,%2\\n\\
38453:\";
3846}"
3847 [(set_attr "type" "darith")
3848 (set_attr "mode" "DI")
3849 (set_attr "length" "12")])
3850
3851
3852(define_insn "lshrdi3_internal2"
3853 [(set (match_operand:DI 0 "register_operand" "=d")
3854 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3855 (match_operand:SI 2 "small_int" "IJK")))
3856 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 3857 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
8ef30996
MM		 3858 "*
3859{
3860 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3861 operands[4] = const0_rtx;
3862 return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
3863}"
3864 [(set_attr "type" "darith")
3865 (set_attr "mode" "DI")
3866 (set_attr "length" "2")])
3867
3868
3869(define_split
3870 [(set (match_operand:DI 0 "register_operand" "")
3871 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3872 (match_operand:SI 2 "small_int" "")))
3873 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3874 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3875 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3876 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3877 && (INTVAL (operands[2]) & 32) != 0"
3878
3879 [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
3880 (set (subreg:SI (match_dup 0) 1) (const_int 0))]
3881
3882 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3883
3884
3885(define_split
3886 [(set (match_operand:DI 0 "register_operand" "")
3887 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3888 (match_operand:SI 2 "small_int" "")))
3889 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3890 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3891 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3892 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3893 && (INTVAL (operands[2]) & 32) != 0"
3894
3895 [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
3896 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
3897
3898 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3899
3900
3901(define_insn "lshrdi3_internal3"
3902 [(set (match_operand:DI 0 "register_operand" "=d")
3903 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3904 (match_operand:SI 2 "small_int" "IJK")))
3905 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7 3906 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3907 && (INTVAL (operands[2]) & 63) < 32
3908 && (INTVAL (operands[2]) & 63) != 0"
3909 "*
3910{
3911 int amount = INTVAL (operands[2]);
3912
3913 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3914 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3915
3916 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
3917}"
3918 [(set_attr "type" "darith")
3919 (set_attr "mode" "DI")
3920 (set_attr "length" "4")])
3921
3922
3923(define_split
3924 [(set (match_operand:DI 0 "register_operand" "")
3925 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3926 (match_operand:SI 2 "small_int" "")))
3927 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3928 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3929 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3930 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3931 && (INTVAL (operands[2]) & 63) < 32
3932 && (INTVAL (operands[2]) & 63) != 0"
3933
3934 [(set (subreg:SI (match_dup 0) 0)
3935 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
3936 (match_dup 2)))
3937
3938 (set (match_dup 3)
3939 (ashift:SI (subreg:SI (match_dup 1) 1)
3940 (match_dup 4)))
3941
3942 (set (subreg:SI (match_dup 0) 0)
3943 (ior:SI (subreg:SI (match_dup 0) 0)
3944 (match_dup 3)))
3945
3946 (set (subreg:SI (match_dup 0) 1)
3947 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
3948 (match_dup 2)))]
3949 "
3950{
3951 int amount = INTVAL (operands[2]);
3952 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3953 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3954}")
3955
3956
3957(define_split
3958 [(set (match_operand:DI 0 "register_operand" "")
3959 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3960 (match_operand:SI 2 "small_int" "")))
3961 (clobber (match_operand:SI 3 "register_operand" ""))]
bb621ad7 3962 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 3963 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3964 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3965 && (INTVAL (operands[2]) & 63) < 32
3966 && (INTVAL (operands[2]) & 63) != 0"
3967
3968 [(set (subreg:SI (match_dup 0) 1)
3969 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
3970 (match_dup 2)))
3971
3972 (set (match_dup 3)
3973 (ashift:SI (subreg:SI (match_dup 1) 0)
3974 (match_dup 4)))
3975
3976 (set (subreg:SI (match_dup 0) 1)
3977 (ior:SI (subreg:SI (match_dup 0) 1)
3978 (match_dup 3)))
3979
3980 (set (subreg:SI (match_dup 0) 0)
3981 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
3982 (match_dup 2)))]
3983 "
3984{
3985 int amount = INTVAL (operands[2]);
3986 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3987 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3988}")
3989
bb621ad7
JW		 3990
3991(define_insn "lshrdi3_internal4"
3992 [(set (match_operand:DI 0 "register_operand" "=d")
3993 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3994 (match_operand:SI 2 "arith_operand" "dI")))]
3995 "TARGET_64BIT"
3996 "*
3997{
3998 if (GET_CODE (operands[2]) == CONST_INT)
3999 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4000
4001 return \"dsrl\\t%0,%1,%2\";
4002}"
4003 [(set_attr "type" "arith")
4004 (set_attr "mode" "DI")
4005 (set_attr "length" "1")])
4006
8ef30996
MM		 4007\f
4008;;
4009;; ....................
4010;;
4011;; COMPARISONS
4012;;
4013;; ....................
4014
4015;; Flow here is rather complex:
4016;;
bb621ad7 4017;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
8ef30996
MM		 4018;; arguments into the branch_cmp array, and the type into
4019;; branch_type. No RTL is generated.
4020;;
4021;; 2) The appropriate branch define_expand is called, which then
4022;; creates the appropriate RTL for the comparison and branch.
4023;; Different CC modes are used, based on what type of branch is
4024;; done, so that we can constrain things appropriately. There
4025;; are assumptions in the rest of GCC that break if we fold the
4026;; operands into the branchs for integer operations, and use cc0
34b650b3
MM		 4027;; for floating point, so we use the fp status register instead.
4028;; If needed, an appropriate temporary is created to hold the
4029;; of the integer compare.
8ef30996
MM		 4030
4031(define_expand "cmpsi"
4032 [(set (cc0)
4033 (compare:CC (match_operand:SI 0 "register_operand" "")
4034 (match_operand:SI 1 "arith_operand" "")))]
4035 ""
4036 "
4037{
4038 if (operands[0]) /* avoid unused code message */
4039 {
4040 branch_cmp[0] = operands[0];
4041 branch_cmp[1] = operands[1];
4042 branch_type = CMP_SI;
4043 DONE;
4044 }
4045}")
4046
4047(define_expand "tstsi"
4048 [(set (cc0)
4049 (match_operand:SI 0 "register_operand" ""))]
4050 ""
4051 "
4052{
4053 if (operands[0]) /* avoid unused code message */
4054 {
4055 branch_cmp[0] = operands[0];
4056 branch_cmp[1] = const0_rtx;
4057 branch_type = CMP_SI;
4058 DONE;
4059 }
4060}")
4061
bb621ad7
JW		 4062(define_expand "cmpdi"
4063 [(set (cc0)
4064 (compare:CC (match_operand:DI 0 "register_operand" "")
4065 (match_operand:DI 1 "arith_operand" "")))]
4066 "TARGET_64BIT"
4067 "
4068{
4069 if (operands[0]) /* avoid unused code message */
4070 {
4071 branch_cmp[0] = operands[0];
4072 branch_cmp[1] = operands[1];
4073 branch_type = CMP_DI;
4074 DONE;
4075 }
4076}")
4077
4078(define_expand "tstdi"
4079 [(set (cc0)
4080 (match_operand:DI 0 "register_operand" ""))]
4081 "TARGET_64BIT"
4082 "
4083{
4084 if (operands[0]) /* avoid unused code message */
4085 {
4086 branch_cmp[0] = operands[0];
4087 branch_cmp[1] = const0_rtx;
4088 branch_type = CMP_DI;
4089 DONE;
4090 }
4091}")
4092
8ef30996
MM		 4093(define_expand "cmpdf"
4094 [(set (cc0)
4095 (compare:CC_FP (match_operand:DF 0 "register_operand" "")
4096 (match_operand:DF 1 "register_operand" "")))]
4097 "TARGET_HARD_FLOAT"
4098 "
4099{
4100 if (operands[0]) /* avoid unused code message */
4101 {
4102 branch_cmp[0] = operands[0];
4103 branch_cmp[1] = operands[1];
4104 branch_type = CMP_DF;
4105 DONE;
4106 }
4107}")
4108
8ef30996
MM		 4109(define_expand "cmpsf"
4110 [(set (cc0)
4111 (compare:CC_FP (match_operand:SF 0 "register_operand" "")
4112 (match_operand:SF 1 "register_operand" "")))]
4113 "TARGET_HARD_FLOAT"
4114 "
4115{
4116 if (operands[0]) /* avoid unused code message */
4117 {
4118 branch_cmp[0] = operands[0];
4119 branch_cmp[1] = operands[1];
4120 branch_type = CMP_SF;
4121 DONE;
4122 }
4123}")
4124
8ef30996
MM		 4125\f
4126;;
4127;; ....................
4128;;
4129;; CONDITIONAL BRANCHES
4130;;
4131;; ....................
4132
34b650b3 4133(define_insn "branch_fp_ne"
8ef30996 4134 [(set (pc)
34b650b3
MM		 4135 (if_then_else (ne:CC_FP (reg:CC_FP 66)
4136 (const_int 0))
4137 (match_operand 0 "pc_or_label_operand" "")
4138 (match_operand 1 "pc_or_label_operand" "")))]
bb621ad7 4139 "TARGET_HARD_FLOAT"
8ef30996
MM		 4140 "*
4141{
8ef30996 4142 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 4143 return (operands[0] != pc_rtx) ? \"%*bc1t%?\\t%0\" : \"%*bc1f%?\\t%1\";
8ef30996
MM		 4144}"
4145 [(set_attr "type" "branch")
4146 (set_attr "mode" "none")
34b650b3 4147 (set_attr "length" "1")])
8ef30996 4148
34b650b3 4149(define_insn "branch_fp_ne_rev"
8ef30996 4150 [(set (pc)
34b650b3
MM		 4151 (if_then_else (ne:CC_REV_FP (reg:CC_REV_FP 66)
4152 (const_int 0))
4153 (match_operand 0 "pc_or_label_operand" "")
4154 (match_operand 1 "pc_or_label_operand" "")))]
bb621ad7 4155 "TARGET_HARD_FLOAT"
8ef30996
MM		 4156 "*
4157{
8ef30996 4158 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 4159 return (operands[0] != pc_rtx) ? \"%*bc1f%?\\t%0\" : \"%*bc1t%?\\t%1\";
8ef30996
MM		 4160}"
4161 [(set_attr "type" "branch")
4162 (set_attr "mode" "none")
34b650b3 4163 (set_attr "length" "1")])
8ef30996 4164
34b650b3 4165(define_insn "branch_fp_eq"
8ef30996 4166 [(set (pc)
34b650b3
MM		 4167 (if_then_else (eq:CC_FP (reg:CC_FP 66)
4168 (const_int 0))
4169 (match_operand 0 "pc_or_label_operand" "")
4170 (match_operand 1 "pc_or_label_operand" "")))]
bb621ad7 4171 "TARGET_HARD_FLOAT"
8ef30996
MM		 4172 "*
4173{
4174 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 4175 return (operands[0] != pc_rtx) ? \"%*bc1f%?\\t%0\" : \"%*bc1t%?\\t%1\";
8ef30996
MM		 4176}"
4177 [(set_attr "type" "branch")
4178 (set_attr "mode" "none")
4179 (set_attr "length" "1")])
4180
34b650b3 4181(define_insn "branch_fp_eq_rev"
8ef30996 4182 [(set (pc)
34b650b3
MM		 4183 (if_then_else (eq:CC_REV_FP (reg:CC_REV_FP 66)
4184 (const_int 0))
4185 (match_operand 0 "pc_or_label_operand" "")
4186 (match_operand 1 "pc_or_label_operand" "")))]
bb621ad7 4187 "TARGET_HARD_FLOAT"
8ef30996
MM		 4188 "*
4189{
4190 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 4191 return (operands[0] != pc_rtx) ? \"%*bc1t%?\\t%0\" : \"%*bc1f%?\\t%1\";
8ef30996
MM		 4192}"
4193 [(set_attr "type" "branch")
4194 (set_attr "mode" "none")
4195 (set_attr "length" "1")])
4196
34b650b3
MM		 4197
4198(define_insn "branch_zero"
8ef30996 4199 [(set (pc)
34b650b3 4200 (if_then_else (match_operator:SI 0 "cmp_op"
81723db9 4201 [(match_operand:SI 1 "register_operand" "d")
34b650b3
MM		 4202 (const_int 0)])
4203 (match_operand 2 "pc_or_label_operand" "")
4204 (match_operand 3 "pc_or_label_operand" "")))]
8ef30996
MM		 4205 ""
4206 "*
4207{
4208 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3
MM		 4209 if (operands[2] != pc_rtx)
4210 { /* normal jump */
4211 switch (GET_CODE (operands[0]))
4212 {
4213 case EQ: return \"%*beq%?\\t%z1,%.,%2\";
4214 case NE: return \"%*bne%?\\t%z1,%.,%2\";
4215 case GTU: return \"%*bne%?\\t%z1,%.,%2\";
4216 case LEU: return \"%*beq%?\\t%z1,%.,%2\";
4217 case GEU: return \"%*j\\t%2\";
81723db9 4218 case LTU: return \"%*bne%?\\t%.,%.,%2\";
34b650b3 4219 }
8ef30996 4220
34b650b3 4221 return \"%*b%C0z%?\\t%z1,%2\";
8ef30996 4222 }
34b650b3
MM		 4223 else
4224 { /* inverted jump */
4225 switch (GET_CODE (operands[0]))
4226 {
4227 case EQ: return \"%*bne%?\\t%z1,%.,%3\";
4228 case NE: return \"%*beq%?\\t%z1,%.,%3\";
4229 case GTU: return \"%*beq%?\\t%z1,%.,%3\";
4230 case LEU: return \"%*bne%?\\t%z1,%.,%3\";
81723db9 4231 case GEU: return \"%*beq%?\\t%.,%.,%3\";
34b650b3
MM		 4232 case LTU: return \"%*j\\t%3\";
4233 }
8ef30996 4234
34b650b3
MM		 4235 return \"%*b%N0z%?\\t%z1,%3\";
4236 }
8ef30996
MM		 4237}"
4238 [(set_attr "type" "branch")
4239 (set_attr "mode" "none")
4240 (set_attr "length" "1")])
4241
8ef30996 4242
bb621ad7
JW		 4243(define_insn "branch_zero_di"
4244 [(set (pc)
4245 (if_then_else (match_operator:DI 0 "cmp_op"
4246 [(match_operand:DI 1 "register_operand" "d")
4247 (const_int 0)])
4248 (match_operand 2 "pc_or_label_operand" "")
4249 (match_operand 3 "pc_or_label_operand" "")))]
4250 ""
4251 "*
4252{
4253 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
4254 if (operands[2] != pc_rtx)
4255 { /* normal jump */
4256 switch (GET_CODE (operands[0]))
4257 {
4258 case EQ: return \"%*beq%?\\t%z1,%.,%2\";
4259 case NE: return \"%*bne%?\\t%z1,%.,%2\";
4260 case GTU: return \"%*bne%?\\t%z1,%.,%2\";
4261 case LEU: return \"%*beq%?\\t%z1,%.,%2\";
4262 case GEU: return \"%*j\\t%2\";
4263 case LTU: return \"%*bne%?\\t%.,%.,%2\";
4264 }
4265
4266 return \"%*b%C0z%?\\t%z1,%2\";
4267 }
4268 else
4269 { /* inverted jump */
4270 switch (GET_CODE (operands[0]))
4271 {
4272 case EQ: return \"%*bne%?\\t%z1,%.,%3\";
4273 case NE: return \"%*beq%?\\t%z1,%.,%3\";
4274 case GTU: return \"%*beq%?\\t%z1,%.,%3\";
4275 case LEU: return \"%*bne%?\\t%z1,%.,%3\";
4276 case GEU: return \"%*beq%?\\t%.,%.,%3\";
4277 case LTU: return \"%*j\\t%3\";
4278 }
4279
4280 return \"%*b%N0z%?\\t%z1,%3\";
4281 }
4282}"
4283 [(set_attr "type" "branch")
4284 (set_attr "mode" "none")
4285 (set_attr "length" "1")])
4286
4287
34b650b3 4288(define_insn "branch_equality"
8ef30996 4289 [(set (pc)
34b650b3
MM		 4290 (if_then_else (match_operator:SI 0 "equality_op"
4291 [(match_operand:SI 1 "register_operand" "d")
4292 (match_operand:SI 2 "register_operand" "d")])
4293 (match_operand 3 "pc_or_label_operand" "")
4294 (match_operand 4 "pc_or_label_operand" "")))]
8ef30996
MM		 4295 ""
4296 "*
4297{
4298 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3
MM		 4299 return (operands[3] != pc_rtx)
4300 ? \"%*b%C0%?\\t%z1,%z2,%3\"
4301 : \"%*b%N0%?\\t%z1,%z2,%4\";
8ef30996
MM		 4302}"
4303 [(set_attr "type" "branch")
4304 (set_attr "mode" "none")
34b650b3
MM		 4305 (set_attr "length" "1")])
4306
8ef30996 4307
bb621ad7
JW		 4308(define_insn "branch_equality_di"
4309 [(set (pc)
4310 (if_then_else (match_operator:DI 0 "equality_op"
4311 [(match_operand:DI 1 "register_operand" "d")
4312 (match_operand:DI 2 "register_operand" "d")])
4313 (match_operand 3 "pc_or_label_operand" "")
4314 (match_operand 4 "pc_or_label_operand" "")))]
4315 ""
4316 "*
4317{
4318 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
4319 return (operands[3] != pc_rtx)
4320 ? \"%*b%C0%?\\t%z1,%z2,%3\"
4321 : \"%*b%N0%?\\t%z1,%z2,%4\";
4322}"
4323 [(set_attr "type" "branch")
4324 (set_attr "mode" "none")
4325 (set_attr "length" "1")])
4326
4327
8ef30996
MM		 4328(define_expand "beq"
4329 [(set (pc)
4330 (if_then_else (eq:CC_EQ (cc0)
4331 (const_int 0))
4332 (label_ref (match_operand 0 "" ""))
4333 (pc)))]
4334 ""
4335 "
4336{
4337 if (operands[0]) /* avoid unused code warning */
4338 {
4339 gen_conditional_branch (operands, EQ);
4340 DONE;
4341 }
4342}")
4343
4344(define_expand "bne"
4345 [(set (pc)
4346 (if_then_else (ne:CC_EQ (cc0)
4347 (const_int 0))
4348 (label_ref (match_operand 0 "" ""))
4349 (pc)))]
4350 ""
4351 "
4352{
4353 if (operands[0]) /* avoid unused code warning */
4354 {
4355 gen_conditional_branch (operands, NE);
4356 DONE;
4357 }
4358}")
4359
4360(define_expand "bgt"
4361 [(set (pc)
4362 (if_then_else (gt:CC (cc0)
4363 (const_int 0))
4364 (label_ref (match_operand 0 "" ""))
4365 (pc)))]
4366 ""
4367 "
4368{
4369 if (operands[0]) /* avoid unused code warning */
4370 {
4371 gen_conditional_branch (operands, GT);
4372 DONE;
4373 }
4374}")
4375
4376(define_expand "bge"
4377 [(set (pc)
4378 (if_then_else (ge:CC (cc0)
4379 (const_int 0))
4380 (label_ref (match_operand 0 "" ""))
4381 (pc)))]
4382 ""
4383 "
4384{
4385 if (operands[0]) /* avoid unused code warning */
4386 {
4387 gen_conditional_branch (operands, GE);
4388 DONE;
4389 }
4390}")
4391
4392(define_expand "blt"
4393 [(set (pc)
4394 (if_then_else (lt:CC (cc0)
4395 (const_int 0))
4396 (label_ref (match_operand 0 "" ""))
4397 (pc)))]
4398 ""
4399 "
4400{
4401 if (operands[0]) /* avoid unused code warning */
4402 {
4403 gen_conditional_branch (operands, LT);
4404 DONE;
4405 }
4406}")
4407
4408(define_expand "ble"
4409 [(set (pc)
4410 (if_then_else (le:CC (cc0)
4411 (const_int 0))
4412 (label_ref (match_operand 0 "" ""))
4413 (pc)))]
4414 ""
4415 "
4416{
4417 if (operands[0]) /* avoid unused code warning */
4418 {
4419 gen_conditional_branch (operands, LE);
4420 DONE;
4421 }
4422}")
4423
4424(define_expand "bgtu"
4425 [(set (pc)
4426 (if_then_else (gtu:CC (cc0)
4427 (const_int 0))
4428 (label_ref (match_operand 0 "" ""))
4429 (pc)))]
4430 ""
4431 "
4432{
4433 if (operands[0]) /* avoid unused code warning */
4434 {
4435 gen_conditional_branch (operands, GTU);
4436 DONE;
4437 }
4438}")
4439
4440(define_expand "bgeu"
4441 [(set (pc)
4442 (if_then_else (geu:CC (cc0)
4443 (const_int 0))
4444 (label_ref (match_operand 0 "" ""))
4445 (pc)))]
4446 ""
4447 "
4448{
4449 if (operands[0]) /* avoid unused code warning */
4450 {
4451 gen_conditional_branch (operands, GEU);
4452 DONE;
4453 }
4454}")
4455
4456
4457(define_expand "bltu"
4458 [(set (pc)
4459 (if_then_else (ltu:CC (cc0)
4460 (const_int 0))
4461 (label_ref (match_operand 0 "" ""))
4462 (pc)))]
4463 ""
4464 "
4465{
4466 if (operands[0]) /* avoid unused code warning */
4467 {
4468 gen_conditional_branch (operands, LTU);
4469 DONE;
4470 }
4471}")
4472
4473(define_expand "bleu"
4474 [(set (pc)
4475 (if_then_else (leu:CC (cc0)
4476 (const_int 0))
4477 (label_ref (match_operand 0 "" ""))
4478 (pc)))]
4479 ""
4480 "
4481{
4482 if (operands[0]) /* avoid unused code warning */
4483 {
4484 gen_conditional_branch (operands, LEU);
4485 DONE;
4486 }
4487}")
4488
4489\f
4490;;
4491;; ....................
4492;;
4493;; SETTING A REGISTER FROM A COMPARISON
4494;;
4495;; ....................
4496
4497(define_expand "seq"
4498 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3
MM		 4499 (eq:SI (match_dup 1)
4500 (match_dup 2)))]
8ef30996
MM		 4501 ""
4502 "
4503{
bb621ad7 4504 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 4505 FAIL;
4506
4507 /* set up operands from compare. */
4508 operands[1] = branch_cmp[0];
4509 operands[2] = branch_cmp[1];
4510
bb621ad7 4511 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 4512 {
4513 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
4514 DONE;
4515 }
4516
8ef30996
MM		 4517 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4518 operands[2] = force_reg (SImode, operands[2]);
4519
4520 /* fall through and generate default code */
4521}")
4522
34b650b3
MM		 4523
4524(define_insn "seq_si_zero"
4525 [(set (match_operand:SI 0 "register_operand" "=d")
4526 (eq:SI (match_operand:SI 1 "register_operand" "d")
4527 (const_int 0)))]
8ef30996 4528 ""
34b650b3 4529 "sltu\\t%0,%1,1"
bb621ad7 4530 [(set_attr "type" "arith")
34b650b3
MM		 4531 (set_attr "mode" "SI")
4532 (set_attr "length" "1")])
4533
bb621ad7
JW		 4534(define_insn "seq_di_zero"
4535 [(set (match_operand:DI 0 "register_operand" "=d")
4536 (eq:DI (match_operand:DI 1 "register_operand" "d")
4537 (const_int 0)))]
4538 "TARGET_64BIT"
4539 "sltu\\t%0,%1,1"
4540 [(set_attr "type" "arith")
4541 (set_attr "mode" "DI")
4542 (set_attr "length" "1")])
4543
34b650b3
MM		 4544(define_insn "seq_si"
4545 [(set (match_operand:SI 0 "register_operand" "=d,d")
4546 (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
4547 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
bbdb5552 4548 "TARGET_DEBUG_C_MODE"
8ef30996 4549 "@
8ef30996 4550 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
34b650b3 4551 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
bb621ad7
JW		 4552 [(set_attr "type" "arith")
4553 (set_attr "mode" "SI")
4554 (set_attr "length" "2")])
4555
4556(define_split
4557 [(set (match_operand:SI 0 "register_operand" "")
4558 (eq:SI (match_operand:SI 1 "register_operand" "")
4559 (match_operand:SI 2 "uns_arith_operand" "")))]
4560 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
4561 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
4562 [(set (match_dup 0)
4563 (xor:SI (match_dup 1)
4564 (match_dup 2)))
4565 (set (match_dup 0)
4566 (ltu:SI (match_dup 0)
4567 (const_int 1)))]
4568 "")
4569
4570(define_insn "seq_di"
4571 [(set (match_operand:DI 0 "register_operand" "=d,d")
4572 (eq:DI (match_operand:DI 1 "register_operand" "%d,d")
4573 (match_operand:DI 2 "uns_arith_operand" "d,K")))]
4574 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
4575 "@
4576 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
4577 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
4578 [(set_attr "type" "arith")
4579 (set_attr "mode" "DI")
92b4cee1 4580 (set_attr "length" "2")])
8ef30996
MM		 4581
4582(define_split
bb621ad7
JW		 4583 [(set (match_operand:DI 0 "register_operand" "")
4584 (eq:DI (match_operand:DI 1 "register_operand" "")
4585 (match_operand:DI 2 "uns_arith_operand" "")))]
4586 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
26b8e6e5 4587 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8ef30996 4588 [(set (match_dup 0)
bb621ad7 4589 (xor:DI (match_dup 1)
8ef30996
MM		 4590 (match_dup 2)))
4591 (set (match_dup 0)
bb621ad7 4592 (ltu:DI (match_dup 0)
8ef30996
MM		 4593 (const_int 1)))]
4594 "")
4595
4596(define_expand "sne"
4597 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3
MM		 4598 (ne:SI (match_dup 1)
4599 (match_dup 2)))]
8ef30996
MM		 4600 ""
4601 "
4602{
bb621ad7 4603 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 4604 FAIL;
4605
4606 /* set up operands from compare. */
4607 operands[1] = branch_cmp[0];
4608 operands[2] = branch_cmp[1];
4609
bb621ad7 4610 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 4611 {
4612 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
4613 DONE;
4614 }
4615
8ef30996
MM		 4616 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4617 operands[2] = force_reg (SImode, operands[2]);
4618
4619 /* fall through and generate default code */
4620}")
4621
34b650b3
MM		 4622(define_insn "sne_si_zero"
4623 [(set (match_operand:SI 0 "register_operand" "=d")
4624 (ne:SI (match_operand:SI 1 "register_operand" "d")
4625 (const_int 0)))]
8ef30996 4626 ""
34b650b3 4627 "sltu\\t%0,%.,%1"
bb621ad7 4628 [(set_attr "type" "arith")
34b650b3
MM		 4629 (set_attr "mode" "SI")
4630 (set_attr "length" "1")])
8ef30996 4631
bb621ad7
JW		 4632(define_insn "sne_di_zero"
4633 [(set (match_operand:DI 0 "register_operand" "=d")
4634 (ne:DI (match_operand:DI 1 "register_operand" "d")
4635 (const_int 0)))]
4636 "TARGET_64BIT"
4637 "sltu\\t%0,%.,%1"
4638 [(set_attr "type" "arith")
4639 (set_attr "mode" "DI")
4640 (set_attr "length" "1")])
4641
34b650b3
MM		 4642(define_insn "sne_si"
4643 [(set (match_operand:SI 0 "register_operand" "=d,d")
4644 (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
4645 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
bbdb5552 4646 "TARGET_DEBUG_C_MODE"
34b650b3
MM		 4647 "@
4648 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
4649 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
bb621ad7 4650 [(set_attr "type" "arith")
92b4cee1
MM		 4651 (set_attr "mode" "SI")
4652 (set_attr "length" "2")])
8ef30996
MM		 4653
4654(define_split
4655 [(set (match_operand:SI 0 "register_operand" "")
34b650b3
MM		 4656 (ne:SI (match_operand:SI 1 "register_operand" "")
4657 (match_operand:SI 2 "uns_arith_operand" "")))]
bbdb5552 4658 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
26b8e6e5 4659 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8ef30996
MM		 4660 [(set (match_dup 0)
4661 (xor:SI (match_dup 1)
4662 (match_dup 2)))
4663 (set (match_dup 0)
34b650b3 4664 (gtu:SI (match_dup 0)
8ef30996
MM		 4665 (const_int 0)))]
4666 "")
4667
bb621ad7
JW		 4668(define_insn "sne_di"
4669 [(set (match_operand:DI 0 "register_operand" "=d,d")
4670 (ne:DI (match_operand:DI 1 "register_operand" "%d,d")
4671 (match_operand:DI 2 "uns_arith_operand" "d,K")))]
4672 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
4673 "@
4674 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
4675 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
4676 [(set_attr "type" "arith")
4677 (set_attr "mode" "DI")
4678 (set_attr "length" "2")])
4679
4680(define_split
4681 [(set (match_operand:DI 0 "register_operand" "")
4682 (ne:DI (match_operand:DI 1 "register_operand" "")
4683 (match_operand:DI 2 "uns_arith_operand" "")))]
4684 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
4685 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
4686 [(set (match_dup 0)
4687 (xor:DI (match_dup 1)
4688 (match_dup 2)))
4689 (set (match_dup 0)
4690 (gtu:DI (match_dup 0)
4691 (const_int 0)))]
4692 "")
4693
8ef30996
MM		 4694(define_expand "sgt"
4695 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 4696 (gt:SI (match_dup 1)
8ef30996
MM		 4697 (match_dup 2)))]
4698 ""
4699 "
4700{
bb621ad7 4701 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 4702 FAIL;
4703
4704 /* set up operands from compare. */
4705 operands[1] = branch_cmp[0];
4706 operands[2] = branch_cmp[1];
4707
bb621ad7 4708 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 4709 {
4710 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
4711 DONE;
4712 }
4713
8ef30996
MM		 4714 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
4715 operands[2] = force_reg (SImode, operands[2]);
4716
4717 /* fall through and generate default code */
4718}")
4719
4720(define_insn "sgt_si"
4721 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 4722 (gt:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 4723 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
4724 ""
4725 "slt\\t%0,%z2,%1"
bb621ad7 4726 [(set_attr "type" "arith")
8ef30996
MM		 4727 (set_attr "mode" "SI")
4728 (set_attr "length" "1")])
4729
bb621ad7
JW		 4730(define_insn "sgt_di"
4731 [(set (match_operand:DI 0 "register_operand" "=d")
4732 (gt:DI (match_operand:DI 1 "register_operand" "d")
4733 (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
4734 "TARGET_64BIT"
4735 "slt\\t%0,%z2,%1"
4736 [(set_attr "type" "arith")
4737 (set_attr "mode" "DI")
4738 (set_attr "length" "1")])
4739
8ef30996
MM		 4740(define_expand "sge"
4741 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 4742 (ge:SI (match_dup 1)
8ef30996
MM		 4743 (match_dup 2)))]
4744 ""
4745 "
4746{
bb621ad7 4747 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 4748 FAIL;
4749
4750 /* set up operands from compare. */
4751 operands[1] = branch_cmp[0];
4752 operands[2] = branch_cmp[1];
4753
bb621ad7 4754 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 4755 {
4756 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
4757 DONE;
4758 }
4759
8ef30996
MM		 4760 /* fall through and generate default code */
4761}")
4762
4763(define_insn "sge_si"
4764 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 4765 (ge:SI (match_operand:SI 1 "register_operand" "d")
8ef30996 4766 (match_operand:SI 2 "arith_operand" "dI")))]
bbdb5552 4767 "TARGET_DEBUG_C_MODE"
8ef30996 4768 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
bb621ad7 4769 [(set_attr "type" "arith")
8ef30996
MM		 4770 (set_attr "mode" "SI")
4771 (set_attr "length" "2")])
4772
4773(define_split
4774 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 4775 (ge:SI (match_operand:SI 1 "register_operand" "")
8ef30996 4776 (match_operand:SI 2 "arith_operand" "")))]
bbdb5552 4777 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 4778 [(set (match_dup 0)
34b650b3 4779 (lt:SI (match_dup 1)
8ef30996
MM		 4780 (match_dup 2)))
4781 (set (match_dup 0)
4782 (xor:SI (match_dup 0)
4783 (const_int 1)))]
4784 "")
4785
bb621ad7
JW		 4786(define_insn "sge_di"
4787 [(set (match_operand:DI 0 "register_operand" "=d")
4788 (ge:DI (match_operand:DI 1 "register_operand" "d")
4789 (match_operand:DI 2 "arith_operand" "dI")))]
4790 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
4791 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
4792 [(set_attr "type" "arith")
4793 (set_attr "mode" "DI")
4794 (set_attr "length" "2")])
4795
4796(define_split
4797 [(set (match_operand:DI 0 "register_operand" "")
4798 (ge:DI (match_operand:DI 1 "register_operand" "")
4799 (match_operand:DI 2 "arith_operand" "")))]
4800 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
4801 [(set (match_dup 0)
4802 (lt:DI (match_dup 1)
4803 (match_dup 2)))
4804 (set (match_dup 0)
4805 (xor:DI (match_dup 0)
4806 (const_int 1)))]
4807 "")
4808
8ef30996
MM		 4809(define_expand "slt"
4810 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 4811 (lt:SI (match_dup 1)
8ef30996
MM		 4812 (match_dup 2)))]
4813 ""
4814 "
4815{
bb621ad7 4816 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 4817 FAIL;
4818
4819 /* set up operands from compare. */
4820 operands[1] = branch_cmp[0];
4821 operands[2] = branch_cmp[1];
4822
bb621ad7 4823 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 4824 {
4825 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
4826 DONE;
4827 }
4828
8ef30996
MM		 4829 /* fall through and generate default code */
4830}")
4831
4832(define_insn "slt_si"
4833 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 4834 (lt:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 4835 (match_operand:SI 2 "arith_operand" "dI")))]
4836 ""
4837 "slt\\t%0,%1,%2"
bb621ad7 4838 [(set_attr "type" "arith")
8ef30996
MM		 4839 (set_attr "mode" "SI")
4840 (set_attr "length" "1")])
4841
bb621ad7
JW		 4842(define_insn "slt_di"
4843 [(set (match_operand:DI 0 "register_operand" "=d")
4844 (lt:DI (match_operand:DI 1 "register_operand" "d")
4845 (match_operand:DI 2 "arith_operand" "dI")))]
4846 "TARGET_64BIT"
4847 "slt\\t%0,%1,%2"
4848 [(set_attr "type" "arith")
4849 (set_attr "mode" "DI")
4850 (set_attr "length" "1")])
4851
8ef30996
MM		 4852(define_expand "sle"
4853 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 4854 (le:SI (match_dup 1)
8ef30996
MM		 4855 (match_dup 2)))]
4856 ""
4857 "
4858{
bb621ad7 4859 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 4860 FAIL;
4861
4862 /* set up operands from compare. */
4863 operands[1] = branch_cmp[0];
4864 operands[2] = branch_cmp[1];
4865
bb621ad7 4866 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 4867 {
4868 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
4869 DONE;
4870 }
4871
8ef30996
MM		 4872 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
4873 operands[2] = force_reg (SImode, operands[2]);
4874
4875 /* fall through and generate default code */
4876}")
4877
34b650b3
MM		 4878(define_insn "sle_si_const"
4879 [(set (match_operand:SI 0 "register_operand" "=d")
4880 (le:SI (match_operand:SI 1 "register_operand" "d")
4881 (match_operand:SI 2 "small_int" "I")))]
4882 "INTVAL (operands[2]) < 32767"
4883 "*
4884{
4885 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
4886 return \"slt\\t%0,%1,%2\";
4887}"
bb621ad7 4888 [(set_attr "type" "arith")
34b650b3
MM		 4889 (set_attr "mode" "SI")
4890 (set_attr "length" "1")])
4891
bb621ad7
JW		 4892(define_insn "sle_di_const"
4893 [(set (match_operand:DI 0 "register_operand" "=d")
4894 (le:DI (match_operand:DI 1 "register_operand" "d")
4895 (match_operand:DI 2 "small_int" "I")))]
4896 "TARGET_64BIT && INTVAL (operands[2]) < 32767"
4897 "*
4898{
4899 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
4900 return \"slt\\t%0,%1,%2\";
4901}"
4902 [(set_attr "type" "arith")
4903 (set_attr "mode" "DI")
4904 (set_attr "length" "1")])
4905
34b650b3
MM		 4906(define_insn "sle_si_reg"
4907 [(set (match_operand:SI 0 "register_operand" "=d")
4908 (le:SI (match_operand:SI 1 "register_operand" "d")
4909 (match_operand:SI 2 "register_operand" "d")))]
bbdb5552 4910 "TARGET_DEBUG_C_MODE"
34b650b3 4911 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
bb621ad7 4912 [(set_attr "type" "arith")
34b650b3
MM		 4913 (set_attr "mode" "SI")
4914 (set_attr "length" "2")])
8ef30996
MM		 4915
4916(define_split
4917 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 4918 (le:SI (match_operand:SI 1 "register_operand" "")
8ef30996 4919 (match_operand:SI 2 "register_operand" "")))]
bbdb5552 4920 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 4921 [(set (match_dup 0)
34b650b3 4922 (lt:SI (match_dup 2)
8ef30996
MM		 4923 (match_dup 1)))
4924 (set (match_dup 0)
4925 (xor:SI (match_dup 0)
4926 (const_int 1)))]
4927 "")
4928
bb621ad7
JW		 4929(define_insn "sle_di_reg"
4930 [(set (match_operand:DI 0 "register_operand" "=d")
4931 (le:DI (match_operand:DI 1 "register_operand" "d")
4932 (match_operand:DI 2 "register_operand" "d")))]
4933 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
4934 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
4935 [(set_attr "type" "arith")
4936 (set_attr "mode" "DI")
4937 (set_attr "length" "2")])
4938
4939(define_split
4940 [(set (match_operand:DI 0 "register_operand" "")
4941 (le:DI (match_operand:DI 1 "register_operand" "")
4942 (match_operand:DI 2 "register_operand" "")))]
4943 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
4944 [(set (match_dup 0)
4945 (lt:DI (match_dup 2)
4946 (match_dup 1)))
4947 (set (match_dup 0)
4948 (xor:DI (match_dup 0)
4949 (const_int 1)))]
4950 "")
4951
8ef30996
MM		 4952(define_expand "sgtu"
4953 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 4954 (gtu:SI (match_dup 1)
8ef30996
MM		 4955 (match_dup 2)))]
4956 ""
4957 "
4958{
bb621ad7 4959 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 4960 FAIL;
4961
4962 /* set up operands from compare. */
4963 operands[1] = branch_cmp[0];
4964 operands[2] = branch_cmp[1];
4965
bb621ad7 4966 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 4967 {
4968 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
4969 DONE;
4970 }
4971
8ef30996
MM		 4972 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
4973 operands[2] = force_reg (SImode, operands[2]);
4974
4975 /* fall through and generate default code */
4976}")
4977
4978(define_insn "sgtu_si"
4979 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 4980 (gtu:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 4981 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
4982 ""
4983 "sltu\\t%0,%z2,%1"
bb621ad7 4984 [(set_attr "type" "arith")
8ef30996
MM		 4985 (set_attr "mode" "SI")
4986 (set_attr "length" "1")])
4987
bb621ad7
JW		 4988(define_insn "sgtu_di"
4989 [(set (match_operand:DI 0 "register_operand" "=d")
4990 (gtu:DI (match_operand:DI 1 "register_operand" "d")
4991 (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
4992 "TARGET_64BIT"
4993 "sltu\\t%0,%z2,%1"
4994 [(set_attr "type" "arith")
4995 (set_attr "mode" "DI")
4996 (set_attr "length" "1")])
4997
8ef30996
MM		 4998(define_expand "sgeu"
4999 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 5000 (geu:SI (match_dup 1)
8ef30996
MM		 5001 (match_dup 2)))]
5002 ""
5003 "
5004{
bb621ad7 5005 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 5006 FAIL;
5007
5008 /* set up operands from compare. */
5009 operands[1] = branch_cmp[0];
5010 operands[2] = branch_cmp[1];
5011
bb621ad7 5012 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 5013 {
5014 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
5015 DONE;
5016 }
5017
8ef30996
MM		 5018 /* fall through and generate default code */
5019}")
5020
5021(define_insn "sgeu_si"
5022 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 5023 (geu:SI (match_operand:SI 1 "register_operand" "d")
8ef30996 5024 (match_operand:SI 2 "arith_operand" "dI")))]
bbdb5552 5025 "TARGET_DEBUG_C_MODE"
8ef30996 5026 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
bb621ad7 5027 [(set_attr "type" "arith")
8ef30996
MM		 5028 (set_attr "mode" "SI")
5029 (set_attr "length" "2")])
5030
5031(define_split
5032 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 5033 (geu:SI (match_operand:SI 1 "register_operand" "")
8ef30996 5034 (match_operand:SI 2 "arith_operand" "")))]
bbdb5552 5035 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 5036 [(set (match_dup 0)
34b650b3 5037 (ltu:SI (match_dup 1)
8ef30996
MM		 5038 (match_dup 2)))
5039 (set (match_dup 0)
5040 (xor:SI (match_dup 0)
5041 (const_int 1)))]
5042 "")
5043
bb621ad7
JW		 5044(define_insn "sgeu_di"
5045 [(set (match_operand:DI 0 "register_operand" "=d")
5046 (geu:DI (match_operand:DI 1 "register_operand" "d")
5047 (match_operand:DI 2 "arith_operand" "dI")))]
5048 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
5049 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
5050 [(set_attr "type" "arith")
5051 (set_attr "mode" "DI")
5052 (set_attr "length" "2")])
5053
5054(define_split
5055 [(set (match_operand:DI 0 "register_operand" "")
5056 (geu:DI (match_operand:DI 1 "register_operand" "")
5057 (match_operand:DI 2 "arith_operand" "")))]
5058 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5059 [(set (match_dup 0)
5060 (ltu:DI (match_dup 1)
5061 (match_dup 2)))
5062 (set (match_dup 0)
5063 (xor:DI (match_dup 0)
5064 (const_int 1)))]
5065 "")
5066
8ef30996
MM		 5067(define_expand "sltu"
5068 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 5069 (ltu:SI (match_dup 1)
8ef30996
MM		 5070 (match_dup 2)))]
5071 ""
5072 "
5073{
bb621ad7 5074 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 5075 FAIL;
5076
5077 /* set up operands from compare. */
5078 operands[1] = branch_cmp[0];
5079 operands[2] = branch_cmp[1];
5080
bb621ad7 5081 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 5082 {
5083 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
5084 DONE;
5085 }
5086
8ef30996
MM		 5087 /* fall through and generate default code */
5088}")
5089
5090(define_insn "sltu_si"
5091 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 5092 (ltu:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 5093 (match_operand:SI 2 "arith_operand" "dI")))]
5094 ""
5095 "sltu\\t%0,%1,%2"
bb621ad7 5096 [(set_attr "type" "arith")
8ef30996
MM		 5097 (set_attr "mode" "SI")
5098 (set_attr "length" "1")])
5099
bb621ad7
JW		 5100(define_insn "sltu_di"
5101 [(set (match_operand:DI 0 "register_operand" "=d")
5102 (ltu:DI (match_operand:DI 1 "register_operand" "d")
5103 (match_operand:DI 2 "arith_operand" "dI")))]
5104 "TARGET_64BIT"
5105 "sltu\\t%0,%1,%2"
5106 [(set_attr "type" "arith")
5107 (set_attr "mode" "DI")
5108 (set_attr "length" "1")])
5109
8ef30996
MM		 5110(define_expand "sleu"
5111 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 5112 (leu:SI (match_dup 1)
8ef30996
MM		 5113 (match_dup 2)))]
5114 ""
5115 "
5116{
bb621ad7 5117 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8ef30996
MM		 5118 FAIL;
5119
5120 /* set up operands from compare. */
5121 operands[1] = branch_cmp[0];
5122 operands[2] = branch_cmp[1];
5123
bb621ad7 5124 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
34b650b3
MM		 5125 {
5126 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
5127 DONE;
5128 }
5129
8ef30996
MM		 5130 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
5131 operands[2] = force_reg (SImode, operands[2]);
5132
5133 /* fall through and generate default code */
5134}")
5135
34b650b3
MM		 5136(define_insn "sleu_si_const"
5137 [(set (match_operand:SI 0 "register_operand" "=d")
5138 (leu:SI (match_operand:SI 1 "register_operand" "d")
5139 (match_operand:SI 2 "small_int" "I")))]
5140 "INTVAL (operands[2]) < 32767"
5141 "*
5142{
5143 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
5144 return \"sltu\\t%0,%1,%2\";
5145}"
bb621ad7 5146 [(set_attr "type" "arith")
34b650b3
MM		 5147 (set_attr "mode" "SI")
5148 (set_attr "length" "1")])
5149
bb621ad7
JW		 5150(define_insn "sleu_di_const"
5151 [(set (match_operand:DI 0 "register_operand" "=d")
5152 (leu:DI (match_operand:DI 1 "register_operand" "d")
5153 (match_operand:DI 2 "small_int" "I")))]
5154 "TARGET_64BIT && INTVAL (operands[2]) < 32767"
5155 "*
5156{
5157 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
5158 return \"sltu\\t%0,%1,%2\";
5159}"
5160 [(set_attr "type" "arith")
5161 (set_attr "mode" "DI")
5162 (set_attr "length" "1")])
5163
34b650b3
MM		 5164(define_insn "sleu_si_reg"
5165 [(set (match_operand:SI 0 "register_operand" "=d")
5166 (leu:SI (match_operand:SI 1 "register_operand" "d")
5167 (match_operand:SI 2 "register_operand" "d")))]
bbdb5552 5168 "TARGET_DEBUG_C_MODE"
34b650b3 5169 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
bb621ad7 5170 [(set_attr "type" "arith")
34b650b3
MM		 5171 (set_attr "mode" "SI")
5172 (set_attr "length" "2")])
8ef30996
MM		 5173
5174(define_split
5175 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 5176 (leu:SI (match_operand:SI 1 "register_operand" "")
8ef30996 5177 (match_operand:SI 2 "register_operand" "")))]
bbdb5552 5178 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 5179 [(set (match_dup 0)
34b650b3 5180 (ltu:SI (match_dup 2)
8ef30996
MM		 5181 (match_dup 1)))
5182 (set (match_dup 0)
5183 (xor:SI (match_dup 0)
5184 (const_int 1)))]
5185 "")
5186
bb621ad7
JW		 5187(define_insn "sleu_di_reg"
5188 [(set (match_operand:DI 0 "register_operand" "=d")
5189 (leu:DI (match_operand:DI 1 "register_operand" "d")
5190 (match_operand:DI 2 "register_operand" "d")))]
5191 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
5192 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
5193 [(set_attr "type" "arith")
5194 (set_attr "mode" "DI")
5195 (set_attr "length" "2")])
5196
5197(define_split
5198 [(set (match_operand:DI 0 "register_operand" "")
5199 (leu:DI (match_operand:DI 1 "register_operand" "")
5200 (match_operand:DI 2 "register_operand" "")))]
5201 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5202 [(set (match_dup 0)
5203 (ltu:DI (match_dup 2)
5204 (match_dup 1)))
5205 (set (match_dup 0)
5206 (xor:DI (match_dup 0)
5207 (const_int 1)))]
5208 "")
5209
34b650b3
MM		 5210\f
5211;;
5212;; ....................
5213;;
5214;; FLOATING POINT COMPARISONS
5215;;
5216;; ....................
5217
5218(define_insn "seq_df"
5219 [(set (reg:CC_FP 66)
5220 (eq:CC_FP (match_operand:DF 0 "register_operand" "f")
5221 (match_operand:DF 1 "register_operand" "f")))]
bb621ad7 5222 "TARGET_HARD_FLOAT"
34b650b3
MM		 5223 "*
5224{
5225 rtx xoperands[10];
5226 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5227 xoperands[1] = operands[0];
5228 xoperands[2] = operands[1];
5229
5230 return mips_fill_delay_slot (\"c.eq.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5231}"
5232 [(set_attr "type" "fcmp")
5233 (set_attr "mode" "FPSW")
5234 (set_attr "length" "1")])
5235
5236(define_insn "sne_df"
5237 [(set (reg:CC_REV_FP 66)
5238 (ne:CC_REV_FP (match_operand:DF 0 "register_operand" "f")
5239 (match_operand:DF 1 "register_operand" "f")))]
bb621ad7 5240 "TARGET_HARD_FLOAT"
34b650b3
MM		 5241 "*
5242{
5243 rtx xoperands[10];
5244 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5245 xoperands[1] = operands[0];
5246 xoperands[2] = operands[1];
5247
5248 return mips_fill_delay_slot (\"c.eq.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5249}"
5250 [(set_attr "type" "fcmp")
5251 (set_attr "mode" "FPSW")
5252 (set_attr "length" "1")])
5253
5254(define_insn "slt_df"
5255 [(set (reg:CC_FP 66)
5256 (lt:CC_FP (match_operand:DF 0 "register_operand" "f")
5257 (match_operand:DF 1 "register_operand" "f")))]
bb621ad7 5258 "TARGET_HARD_FLOAT"
34b650b3
MM		 5259 "*
5260{
5261 rtx xoperands[10];
5262 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5263 xoperands[1] = operands[0];
5264 xoperands[2] = operands[1];
5265
5266 return mips_fill_delay_slot (\"c.lt.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5267}"
5268 [(set_attr "type" "fcmp")
5269 (set_attr "mode" "FPSW")
5270 (set_attr "length" "1")])
5271
5272(define_insn "sle_df"
5273 [(set (reg:CC_FP 66)
5274 (le:CC_FP (match_operand:DF 0 "register_operand" "f")
5275 (match_operand:DF 1 "register_operand" "f")))]
bb621ad7 5276 "TARGET_HARD_FLOAT"
34b650b3
MM		 5277 "*
5278{
5279 rtx xoperands[10];
5280 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5281 xoperands[1] = operands[0];
5282 xoperands[2] = operands[1];
5283
5284 return mips_fill_delay_slot (\"c.le.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5285}"
5286 [(set_attr "type" "fcmp")
5287 (set_attr "mode" "FPSW")
5288 (set_attr "length" "1")])
5289
5290(define_insn "sgt_df"
5291 [(set (reg:CC_FP 66)
5292 (gt:CC_FP (match_operand:DF 0 "register_operand" "f")
5293 (match_operand:DF 1 "register_operand" "f")))]
bb621ad7 5294 "TARGET_HARD_FLOAT"
34b650b3
MM		 5295 "*
5296{
5297 rtx xoperands[10];
5298 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5299 xoperands[1] = operands[0];
5300 xoperands[2] = operands[1];
5301
5302 return mips_fill_delay_slot (\"c.lt.d\\t%1,%0\", DELAY_FCMP, xoperands, insn);
5303}"
5304 [(set_attr "type" "fcmp")
5305 (set_attr "mode" "FPSW")
5306 (set_attr "length" "1")])
5307
5308(define_insn "sge_df"
5309 [(set (reg:CC_FP 66)
5310 (ge:CC_FP (match_operand:DF 0 "register_operand" "f")
5311 (match_operand:DF 1 "register_operand" "f")))]
bb621ad7 5312 "TARGET_HARD_FLOAT"
34b650b3
MM		 5313 "*
5314{
5315 rtx xoperands[10];
5316 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5317 xoperands[1] = operands[0];
5318 xoperands[2] = operands[1];
5319
5320 return mips_fill_delay_slot (\"c.le.d\\t%1,%0\", DELAY_FCMP, xoperands, insn);
5321}"
5322 [(set_attr "type" "fcmp")
5323 (set_attr "mode" "FPSW")
5324 (set_attr "length" "1")])
5325
5326(define_insn "seq_sf"
5327 [(set (reg:CC_FP 66)
5328 (eq:CC_FP (match_operand:SF 0 "register_operand" "f")
5329 (match_operand:SF 1 "register_operand" "f")))]
bb621ad7 5330 "TARGET_HARD_FLOAT"
34b650b3
MM		 5331 "*
5332{
5333 rtx xoperands[10];
5334 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5335 xoperands[1] = operands[0];
5336 xoperands[2] = operands[1];
5337
5338 return mips_fill_delay_slot (\"c.eq.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5339}"
5340 [(set_attr "type" "fcmp")
5341 (set_attr "mode" "FPSW")
5342 (set_attr "length" "1")])
5343
5344(define_insn "sne_sf"
5345 [(set (reg:CC_REV_FP 66)
5346 (ne:CC_REV_FP (match_operand:SF 0 "register_operand" "f")
5347 (match_operand:SF 1 "register_operand" "f")))]
bb621ad7 5348 "TARGET_HARD_FLOAT"
34b650b3
MM		 5349 "*
5350{
5351 rtx xoperands[10];
5352 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5353 xoperands[1] = operands[0];
5354 xoperands[2] = operands[1];
5355
5356 return mips_fill_delay_slot (\"c.eq.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5357}"
5358 [(set_attr "type" "fcmp")
5359 (set_attr "mode" "FPSW")
5360 (set_attr "length" "1")])
5361
5362(define_insn "slt_sf"
5363 [(set (reg:CC_FP 66)
5364 (lt:CC_FP (match_operand:SF 0 "register_operand" "f")
5365 (match_operand:SF 1 "register_operand" "f")))]
bb621ad7 5366 "TARGET_HARD_FLOAT"
34b650b3
MM		 5367 "*
5368{
5369 rtx xoperands[10];
5370 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5371 xoperands[1] = operands[0];
5372 xoperands[2] = operands[1];
5373
5374 return mips_fill_delay_slot (\"c.lt.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5375}"
5376 [(set_attr "type" "fcmp")
5377 (set_attr "mode" "FPSW")
5378 (set_attr "length" "1")])
5379
5380(define_insn "sle_sf"
5381 [(set (reg:CC_FP 66)
5382 (le:CC_FP (match_operand:SF 0 "register_operand" "f")
5383 (match_operand:SF 1 "register_operand" "f")))]
bb621ad7 5384 "TARGET_HARD_FLOAT"
34b650b3
MM		 5385 "*
5386{
5387 rtx xoperands[10];
5388 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5389 xoperands[1] = operands[0];
5390 xoperands[2] = operands[1];
5391
5392 return mips_fill_delay_slot (\"c.le.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5393}"
5394 [(set_attr "type" "fcmp")
5395 (set_attr "mode" "FPSW")
5396 (set_attr "length" "1")])
5397
5398(define_insn "sgt_sf"
5399 [(set (reg:CC_FP 66)
5400 (gt:CC_FP (match_operand:SF 0 "register_operand" "f")
5401 (match_operand:SF 1 "register_operand" "f")))]
bb621ad7 5402 "TARGET_HARD_FLOAT"
34b650b3
MM		 5403 "*
5404{
5405 rtx xoperands[10];
5406 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5407 xoperands[1] = operands[0];
5408 xoperands[2] = operands[1];
5409
5410 return mips_fill_delay_slot (\"c.lt.s\\t%1,%0\", DELAY_FCMP, xoperands, insn);
5411}"
5412 [(set_attr "type" "fcmp")
5413 (set_attr "mode" "FPSW")
5414 (set_attr "length" "1")])
5415
5416(define_insn "sge_sf"
5417 [(set (reg:CC_FP 66)
5418 (ge:CC_FP (match_operand:SF 0 "register_operand" "f")
5419 (match_operand:SF 1 "register_operand" "f")))]
bb621ad7 5420 "TARGET_HARD_FLOAT"
34b650b3
MM		 5421 "*
5422{
5423 rtx xoperands[10];
5424 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5425 xoperands[1] = operands[0];
5426 xoperands[2] = operands[1];
5427
5428 return mips_fill_delay_slot (\"c.le.s\\t%1,%0\", DELAY_FCMP, xoperands, insn);
5429}"
5430 [(set_attr "type" "fcmp")
5431 (set_attr "mode" "FPSW")
5432 (set_attr "length" "1")])
5433
8ef30996
MM		 5434\f
5435;;
5436;; ....................
5437;;
5438;; UNCONDITIONAL BRANCHES
5439;;
5440;; ....................
5441
5442;; Unconditional branches.
5443
5444(define_insn "jump"
5445 [(set (pc)
5446 (label_ref (match_operand 0 "" "")))]
5447 ""
5448 "*
5449{
5450 if (GET_CODE (operands[0]) == REG)
5451 return \"%*j\\t%0\";
5452 else
5453 return \"%*j\\t%l0\";
5454}"
5455 [(set_attr "type" "jump")
5456 (set_attr "mode" "none")
5457 (set_attr "length" "1")])
5458
bb621ad7
JW		 5459(define_expand "indirect_jump"
5460 [(set (pc) (match_operand 0 "register_operand" "d"))]
8ef30996 5461 ""
bb621ad7
JW		 5462 "
5463{
5464 rtx dest;
5465
5466 if (operands[0]) /* eliminate unused code warnings */
5467 {
5468 dest = operands[0];
5469 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
5470 operands[0] = copy_to_mode_reg (Pmode, dest);
5471
5472 if (!TARGET_LONG64)
5473 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
5474 else
5475 emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
5476
5477 DONE;
5478 }
5479}")
5480
5481(define_insn "indirect_jump_internal1"
5482 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
5483 "!TARGET_LONG64"
5484 "%*j\\t%0"
5485 [(set_attr "type" "jump")
5486 (set_attr "mode" "none")
5487 (set_attr "length" "1")])
5488
5489(define_insn "indirect_jump_internal2"
5490 [(set (pc) (match_operand:DI 0 "register_operand" "d"))]
5491 "TARGET_LONG64"
8ef30996
MM		 5492 "%*j\\t%0"
5493 [(set_attr "type" "jump")
5494 (set_attr "mode" "none")
5495 (set_attr "length" "1")])
5496
bb621ad7 5497(define_expand "tablejump"
8ef30996 5498 [(set (pc)
bb621ad7 5499 (match_operand 0 "register_operand" "d"))
8ef30996
MM		 5500 (use (label_ref (match_operand 1 "" "")))]
5501 ""
bb621ad7
JW		 5502 "
5503{
5504 rtx dest;
5505
5506 if (operands[0]) /* eliminate unused code warnings */
5507 {
5508 if (GET_MODE (operands[0]) != Pmode)
5509 abort ();
5510
5511 if (!TARGET_LONG64)
5512 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
5513 else
5514 emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
5515
5516 DONE;
5517 }
5518}")
5519
5520(define_insn "tablejump_internal1"
5521 [(set (pc)
5522 (match_operand:SI 0 "register_operand" "d"))
5523 (use (label_ref (match_operand 1 "" "")))]
5524 "!TARGET_LONG64"
5a5b76a2
JW		 5525 "*
5526{
5527 /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic. */
5528 if (TARGET_ABICALLS)
5529 output_asm_insn (\".cpadd\\t%0\", operands);
5530 return \"%*j\\t%0\";
5531}"
bb621ad7
JW		 5532 [(set_attr "type" "jump")
5533 (set_attr "mode" "none")
5a5b76a2
JW		 5534 (set (attr "length")
5535 (if_then_else (eq_attr "abicalls" "yes")
5536 (const_int 2)
5537 (const_int 1)))])
bb621ad7
JW		 5538
5539(define_insn "tablejump_internal2"
5540 [(set (pc)
5541 (match_operand:DI 0 "register_operand" "d"))
5542 (use (label_ref (match_operand 1 "" "")))]
5543 "TARGET_LONG64"
5a5b76a2
JW		 5544 "*
5545{
5546 /* .cpdadd expands to dadd REG,REG,$gp when pic, and nothing when not pic. */
5547 if (TARGET_ABICALLS)
5548 output_asm_insn (\".cpdadd\\t%0\", operands);
5549 return \"%*j\\t%0\";
5550}"
8ef30996
MM		 5551 [(set_attr "type" "jump")
5552 (set_attr "mode" "none")
5a5b76a2
JW		 5553 (set (attr "length")
5554 (if_then_else (eq_attr "abicalls" "yes")
5555 (const_int 2)
5556 (const_int 1)))])
8ef30996
MM		 5557
5558;; Function return, only allow after optimization, so that we can
5559;; eliminate jumps to jumps if no stack space is used.
5560
0fb5ac6f
MM		 5561;; (define_expand "return"
5562;; [(set (pc) (reg:SI 31))]
5563;; "simple_epilogue_p ()"
5564;; "")
5565
5566(define_expand "return"
5567 [(parallel [(return)
5568 (use (reg:SI 31))])]
5569 "simple_epilogue_p ()"
5570 "")
5571
5572(define_insn "return_internal"
5573 [(parallel [(return)
5574 (use (match_operand:SI 0 "register_operand" "d"))])]
5575 ""
5576 "%*j\\t%0"
8ef30996
MM		 5577 [(set_attr "type" "jump")
5578 (set_attr "mode" "none")
5579 (set_attr "length" "1")])
5580
e0bfcea5
ILT		 5581;; Implement a switch statement when generating embedded PIC code.
5582;; Switches are implemented by `tablejump' when not using -membedded-pic.
5583
5584(define_expand "casesi"
5585 [(set (match_dup 5)
5586 (minus:SI (match_operand:SI 0 "register_operand" "d")
5587 (match_operand:SI 1 "arith_operand" "dI")))
5588 (set (cc0)
5589 (compare:CC (match_dup 5)
5590 (match_operand:SI 2 "arith_operand" "")))
5591 (set (pc)
5592 (if_then_else (gtu (cc0)
5593 (const_int 0))
5594 (label_ref (match_operand 4 "" ""))
5595 (pc)))
5596 (parallel
5597 [(set (pc)
5598 (mem:SI (plus:SI (mult:SI (match_dup 5)
5599 (const_int 4))
5600 (label_ref (match_operand 3 "" "")))))
5601 (clobber (match_scratch:SI 6 ""))
5602 (clobber (reg:SI 31))])]
5603 "TARGET_EMBEDDED_PIC"
5604 "
5605{
5606 /* We need slightly different code for eight byte table entries. */
5607 if (TARGET_LONG64)
5608 abort ();
5609
5610 if (operands[0])
5611 {
5612 rtx reg = gen_reg_rtx (SImode);
5613
e0bfcea5
ILT		 5614 /* If the index is too large, go to the default label. */
5615 emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
5616 emit_insn (gen_cmpsi (reg, operands[2]));
5617 emit_insn (gen_bgtu (operands[4]));
5618
5619 /* Do the PIC jump. */
5620 emit_insn (gen_casesi_internal (reg, operands[3], gen_reg_rtx (SImode)));
5621
5622 DONE;
5623 }
5624}")
5625
5626;; An embedded PIC switch statement looks like this:
5627;; bal $LS1
5628;; sll $reg,$index,2
5629;; $LS1:
5630;; addu $reg,$reg,$31
5631;; lw $reg,$L1-$LS1($reg)
5632;; addu $reg,$reg,$31
5633;; j $reg
5634;; $L1:
5635;; .word case1-$LS1
5636;; .word case2-$LS1
5637;; ...
5638
5639(define_insn "casesi_internal"
5640 [(set (pc)
5641 (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
5642 (const_int 4))
5643 (label_ref (match_operand 1 "" "")))))
5644 (clobber (match_operand:SI 2 "register_operand" "d"))
5645 (clobber (reg:SI 31))]
5646 "TARGET_EMBEDDED_PIC"
5647 "*
5648{
5649 output_asm_insn (\"%(bal\\t%S1\;sll\\t%0,2\\n%S1:\", operands);
5650 output_asm_insn (\"addu\\t%0,%0,$31%)\", operands);
5651 output_asm_insn (\"lw\\t%0,%1-%S1(%0)\;addu\\t%0,%0,$31\", operands);
5652 return \"j\\t%0\";
5653}"
5654 [(set_attr "type" "jump")
5655 (set_attr "mode" "none")
5656 (set_attr "length" "6")])
5657
0fb5ac6f
MM		 5658\f
5659;;
5660;; ....................
5661;;
5662;; Function prologue/epilogue
5663;;
5664;; ....................
5665;;
5666
5667(define_expand "prologue"
5668 [(const_int 1)]
5669 ""
5670 "
5671{
5672 if (mips_isa >= 0) /* avoid unused code warnings */
5673 {
5674 mips_expand_prologue ();
5675 DONE;
5676 }
5677}")
5678
d8d5b1e1
MM		 5679;; Block any insns from being moved before this point, since the
5680;; profiling call to mcount can use various registers that aren't
5681;; saved or used to pass arguments.
5682
5683(define_insn "blockage"
5684 [(unspec_volatile [(const_int 0)] 0)]
5685 ""
5686 ""
5687 [(set_attr "type" "unknown")
5688 (set_attr "mode" "none")
5689 (set_attr "length" "0")])
5690
0fb5ac6f
MM		 5691;; At present, don't expand the epilogue, reorg.c will clobber the
5692;; return register in compiling gen_lowpart (emit-rtl.c).
5693;;
5694;; (define_expand "epilogue"
5695;; [(const_int 2)]
5696;; ""
5697;; "
5698;; {
5699;; if (mips_isa >= 0) /* avoid unused code warnings */
5700;; {
5701;; mips_expand_epilogue ();
5702;; DONE;
5703;; }
5704;; }")
5705
92544bdf
ILT		 5706;; When generating embedded PIC code we need to get the address of the
5707;; current function. This specialized instruction does just that.
5708
5709(define_insn "get_fnaddr"
5710 [(set (match_operand 0 "register_operand" "d")
5711 (unspec [(match_operand 1 "" "")] 1))
5712 (clobber (reg:SI 31))]
5713 "TARGET_EMBEDDED_PIC
5714 && GET_CODE (operands[1]) == SYMBOL_REF"
5715 "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
5716 [(set_attr "type" "call")
5717 (set_attr "mode" "none")
5718 (set_attr "length" "4")])
5719
8ef30996
MM		 5720\f
5721;;
5722;; ....................
5723;;
5724;; FUNCTION CALLS
5725;;
5726;; ....................
5727
5728;; calls.c now passes a third argument, make saber happy
5729
5730(define_expand "call"
af4a697f 5731 [(parallel [(call (match_operand 0 "memory_operand" "m")
8ef30996 5732 (match_operand 1 "" "i"))
3f1f8d8c
MM		 5733 (clobber (reg:SI 31))
5734 (use (match_operand 2 "" "")) ;; next_arg_reg
5735 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
8ef30996
MM		 5736 ""
5737 "
5738{
5739 rtx addr;
5740
3f1f8d8c
MM		 5741 if (operands[0]) /* eliminate unused code warnings */
5742 {
5743 addr = XEXP (operands[0], 0);
322dce45
RS		 5744 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
5745 || ! call_insn_operand (operands[0], VOIDmode))
5746 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
3f1f8d8c
MM		 5747
5748 /* In order to pass small structures by value in registers
5749 compatibly with the MIPS compiler, we need to shift the value
5750 into the high part of the register. Function_arg has encoded
5751 a PARALLEL rtx, holding a vector of adjustments to be made
5752 as the next_arg_reg variable, so we split up the insns,
5753 and emit them separately. */
5754
5755 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
5756 {
5757 rtvec adjust = XVEC (operands[2], 0);
5758 int num = GET_NUM_ELEM (adjust);
5759 int i;
5760
5761 for (i = 0; i < num; i++)
5762 emit_insn (RTVEC_ELT (adjust, i));
5763 }
8ef30996 5764
d1399bd0 5765 emit_call_insn (gen_call_internal1 (operands[0], operands[1],
bb621ad7 5766 gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
3f1f8d8c
MM		 5767 DONE;
5768 }
8ef30996
MM		 5769}")
5770
d1399bd0 5771(define_insn "call_internal1"
322dce45 5772 [(call (match_operand 0 "call_insn_operand" "m")
8ef30996
MM		 5773 (match_operand 1 "" "i"))
5774 (clobber (match_operand:SI 2 "register_operand" "=d"))]
84a92af4 5775 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
8ef30996
MM		 5776 "*
5777{
5778 register rtx target = XEXP (operands[0], 0);
5779
5780 if (GET_CODE (target) == SYMBOL_REF)
5781 return \"%*jal\\t%0\";
5782
2bba3a75
MM		 5783 else if (GET_CODE (target) == CONST_INT)
5784 {
5785 operands[0] = target;
3f1f8d8c 5786 return \"%*%[li\\t%@,%0\\n\\tjal\\t%2,%@%]\";
2bba3a75
MM		 5787 }
5788
8ef30996
MM		 5789 else
5790 {
5791 operands[0] = target;
3f1f8d8c 5792 return \"%*jal\\t%2,%0\";
8ef30996
MM		 5793 }
5794}"
5795 [(set_attr "type" "call")
5796 (set_attr "mode" "none")
5797 (set_attr "length" "1")])
5798
d1399bd0 5799(define_insn "call_internal2"
84a92af4
JW		 5800 [(call (match_operand 0 "call_insn_operand" "m")
5801 (match_operand 1 "" "i"))
5802 (clobber (match_operand:SI 2 "register_operand" "=d"))]
5803 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
5804 "*
5805{
5806 register rtx target = XEXP (operands[0], 0);
5807
5808 if (GET_CODE (target) == SYMBOL_REF)
5809 return \"jal\\t%0\";
5810
5811 else if (GET_CODE (target) == CONST_INT)
5812 {
5813 operands[0] = target;
5814 return \"li\\t%^,%0\\n\\tjal\\t%2,%^\";
5815 }
5816
5817 else
5818 {
5819 operands[0] = target;
5820 if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
5821 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
5822 else
5823 return \"jal\\t%2,%0\";
5824 }
5825}"
5826 [(set_attr "type" "call")
5827 (set_attr "mode" "none")
5828 (set_attr "length" "2")])
5829
bb621ad7 5830(define_insn "call_internal3a"
d1399bd0
MM		 5831 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
5832 (match_operand 1 "" "i"))
5833 (clobber (match_operand:SI 2 "register_operand" "=d"))]
bb621ad7
JW		 5834 "!TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
5835 "%*jal\\t%2,%0"
5836 [(set_attr "type" "call")
5837 (set_attr "mode" "none")
5838 (set_attr "length" "1")])
5839
5840(define_insn "call_internal3b"
5841 [(call (mem:DI (match_operand:DI 0 "register_operand" "r"))
5842 (match_operand 1 "" "i"))
5843 (clobber (match_operand:SI 2 "register_operand" "=d"))]
5844 "TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
d1399bd0
MM		 5845 "%*jal\\t%2,%0"
5846 [(set_attr "type" "call")
5847 (set_attr "mode" "none")
5848 (set_attr "length" "1")])
5849
bb621ad7 5850(define_insn "call_internal4a"
84a92af4
JW		 5851 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
5852 (match_operand 1 "" "i"))
5853 (clobber (match_operand:SI 2 "register_operand" "=d"))]
bb621ad7 5854 "!TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
84a92af4
JW		 5855 "*
5856{
5857 if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
5858 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
5859 else
5860 return \"jal\\t%2,%0\";
5861}"
5862 [(set_attr "type" "call")
5863 (set_attr "mode" "none")
5864 (set_attr "length" "2")])
5865
bb621ad7
JW		 5866(define_insn "call_internal4b"
5867 [(call (mem:DI (match_operand:DI 0 "register_operand" "r"))
5868 (match_operand 1 "" "i"))
5869 (clobber (match_operand:SI 2 "register_operand" "=d"))]
5870 "TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
5871 "*
5872{
5873 if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
5874 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
5875 else
5876 return \"jal\\t%2,%0\";
5877}"
5878 [(set_attr "type" "call")
5879 (set_attr "mode" "none")
5880 (set_attr "length" "2")])
d1399bd0 5881
8ef30996
MM		 5882;; calls.c now passes a fourth argument, make saber happy
5883
5884(define_expand "call_value"
5885 [(parallel [(set (match_operand 0 "register_operand" "=df")
af4a697f 5886 (call (match_operand 1 "memory_operand" "m")
8ef30996 5887 (match_operand 2 "" "i")))
3f1f8d8c
MM		 5888 (clobber (reg:SI 31))
5889 (use (match_operand 3 "" ""))])] ;; next_arg_reg
8ef30996
MM		 5890 ""
5891 "
5892{
5893 rtx addr;
5894
3f1f8d8c
MM		 5895 if (operands[0]) /* eliminate unused code warning */
5896 {
5897 addr = XEXP (operands[1], 0);
322dce45
RS		 5898 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
5899 || ! call_insn_operand (operands[1], VOIDmode))
5900 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
3f1f8d8c
MM		 5901
5902 /* In order to pass small structures by value in registers
5903 compatibly with the MIPS compiler, we need to shift the value
5904 into the high part of the register. Function_arg has encoded
5905 a PARALLEL rtx, holding a vector of adjustments to be made
5906 as the next_arg_reg variable, so we split up the insns,
5907 and emit them separately. */
5908
5909 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
5910 {
5911 rtvec adjust = XVEC (operands[3], 0);
5912 int num = GET_NUM_ELEM (adjust);
5913 int i;
5914
5915 for (i = 0; i < num; i++)
5916 emit_insn (RTVEC_ELT (adjust, i));
5917 }
5918
d1399bd0 5919 emit_call_insn (gen_call_value_internal1 (operands[0], operands[1], operands[2],
bb621ad7 5920 gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
3f1f8d8c
MM		 5921
5922 DONE;
5923 }
8ef30996 5924
8ef30996
MM		 5925}")
5926
d1399bd0 5927(define_insn "call_value_internal1"
8ef30996 5928 [(set (match_operand 0 "register_operand" "=df")
322dce45 5929 (call (match_operand 1 "call_insn_operand" "m")
8ef30996
MM		 5930 (match_operand 2 "" "i")))
5931 (clobber (match_operand:SI 3 "register_operand" "=d"))]
84a92af4 5932 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
8ef30996
MM		 5933 "*
5934{
5935 register rtx target = XEXP (operands[1], 0);
5936
5937 if (GET_CODE (target) == SYMBOL_REF)
5938 return \"%*jal\\t%1\";
5939
2bba3a75
MM		 5940 else if (GET_CODE (target) == CONST_INT)
5941 {
5942 operands[1] = target;
3f1f8d8c 5943 return \"%*%[li\\t%@,%1\\n\\tjal\\t%3,%@%]\";
2bba3a75
MM		 5944 }
5945
8ef30996
MM		 5946 else
5947 {
5948 operands[1] = target;
3f1f8d8c 5949 return \"%*jal\\t%3,%1\";
8ef30996
MM		 5950 }
5951}"
5952 [(set_attr "type" "call")
5953 (set_attr "mode" "none")
5954 (set_attr "length" "1")])
5955
d1399bd0 5956(define_insn "call_value_internal2"
84a92af4
JW		 5957 [(set (match_operand 0 "register_operand" "=df")
5958 (call (match_operand 1 "call_insn_operand" "m")
5959 (match_operand 2 "" "i")))
5960 (clobber (match_operand:SI 3 "register_operand" "=d"))]
5961 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
5962 "*
5963{
5964 register rtx target = XEXP (operands[1], 0);
5965
5966 if (GET_CODE (target) == SYMBOL_REF)
5967 return \"jal\\t%1\";
5968
5969 else if (GET_CODE (target) == CONST_INT)
5970 {
5971 operands[1] = target;
5972 return \"li\\t%^,%1\\n\\tjal\\t%3,%^\";
5973 }
5974
5975 else
5976 {
5977 operands[1] = target;
5978 if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
5979 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
5980 else
5981 return \"jal\\t%3,%1\";
5982 }
5983}"
5984 [(set_attr "type" "call")
5985 (set_attr "mode" "none")
5986 (set_attr "length" "2")])
5987
bb621ad7 5988(define_insn "call_value_internal3a"
d1399bd0
MM		 5989 [(set (match_operand 0 "register_operand" "=df")
5990 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
5991 (match_operand 2 "" "i")))
5992 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7
JW		 5993 "!TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
5994 "%*jal\\t%3,%1"
5995 [(set_attr "type" "call")
5996 (set_attr "mode" "none")
5997 (set_attr "length" "1")])
5998
5999(define_insn "call_value_internal3b"
6000 [(set (match_operand 0 "register_operand" "=df")
6001 (call (mem:DI (match_operand:DI 1 "register_operand" "r"))
6002 (match_operand 2 "" "i")))
6003 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6004 "TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
d1399bd0
MM		 6005 "%*jal\\t%3,%1"
6006 [(set_attr "type" "call")
6007 (set_attr "mode" "none")
6008 (set_attr "length" "1")])
6009
bb621ad7 6010(define_insn "call_value_internal4a"
84a92af4
JW		 6011 [(set (match_operand 0 "register_operand" "=df")
6012 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
6013 (match_operand 2 "" "i")))
6014 (clobber (match_operand:SI 3 "register_operand" "=d"))]
bb621ad7
JW		 6015 "!TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
6016 "*
6017{
6018 if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
6019 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
6020 else
6021 return \"jal\\t%3,%1\";
6022}"
6023 [(set_attr "type" "call")
6024 (set_attr "mode" "none")
6025 (set_attr "length" "2")])
6026
6027(define_insn "call_value_internal4b"
6028 [(set (match_operand 0 "register_operand" "=df")
6029 (call (mem:DI (match_operand:DI 1 "register_operand" "r"))
6030 (match_operand 2 "" "i")))
6031 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6032 "TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
84a92af4
JW		 6033 "*
6034{
6035 if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
6036 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
6037 else
6038 return \"jal\\t%3,%1\";
6039}"
6040 [(set_attr "type" "call")
6041 (set_attr "mode" "none")
6042 (set_attr "length" "2")])
6043
a93821e9
TW		 6044;; Call subroutine returning any type.
6045
6046(define_expand "untyped_call"
6047 [(parallel [(call (match_operand 0 "" "")
6048 (const_int 0))
6049 (match_operand 1 "" "")
6050 (match_operand 2 "" "")])]
6051 ""
6052 "
6053{
740b4585 6054 if (operands[0]) /* silence statement not reached warnings */
a93821e9 6055 {
740b4585
MM		 6056 int i;
6057
6058 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
a93821e9 6059
740b4585
MM		 6060 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6061 {
6062 rtx set = XVECEXP (operands[2], 0, i);
6063 emit_move_insn (SET_DEST (set), SET_SRC (set));
6064 }
a93821e9 6065
740b4585
MM		 6066 emit_insn (gen_blockage ());
6067 DONE;
6068 }
a93821e9 6069}")
8ef30996
MM		 6070\f
6071;;
6072;; ....................
6073;;
6074;; MISC.
6075;;
6076;; ....................
6077;;
6078
6079(define_insn "nop"
6080 [(const_int 0)]
6081 ""
6082 "%(nop%)"
6083 [(set_attr "type" "nop")
6084 (set_attr "mode" "none")
6085 (set_attr "length" "1")])
6086
6087(define_expand "probe"
6088 [(set (match_dup 0)
6089 (match_dup 1))]
6090 ""
6091 "
6092{
6093 operands[0] = gen_reg_rtx (SImode);
6094 operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx);
6095 MEM_VOLATILE_P (operands[1]) = TRUE;
6096
6097 /* fall through and generate default code */
6098}")
GNU Compiler Collection
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