git://gcc.gnu.org / gcc.git / blame
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| 8ef30996 MM |
1 | ;; Mips.md Machine Description for MIPS based processors |
| 2 | ;; Contributed by A. Lichnewsky, lich@inria.inria.fr | |
| 3 | ;; Changes by Michael Meissner, meissner@osf.org | |
| bb621ad7 JW |
4 | ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and |
| 5 | ;; Brendan Eich, brendan@microunity.com. | |
| b8eb88d0 | 6 | ;; Copyright (C) 1989, 90-5, 1996 Free Software Foundation, Inc. |
| 8ef30996 MM |
7 | |
| 8 | ;; This file is part of GNU CC. | |
| 9 | ||
| 10 | ;; GNU CC is free software; you can redistribute it and/or modify | |
| 11 | ;; it under the terms of the GNU General Public License as published by | |
| 12 | ;; the Free Software Foundation; either version 2, or (at your option) | |
| 13 | ;; any later version. | |
| 14 | ||
| 15 | ;; GNU CC is distributed in the hope that it will be useful, | |
| 16 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | ;; GNU General Public License for more details. | |
| 19 | ||
| 20 | ;; You should have received a copy of the GNU General Public License | |
| 21 | ;; along with GNU CC; see the file COPYING. If not, write to | |
| 3f63df56 RK |
22 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
| 23 | ;; Boston, MA 02111-1307, USA. | |
| 8ef30996 | 24 | |
| e19ff60f JW |
25 | ;; ??? Currently does not have define_function_unit support for the R8000. |
| 26 | ;; Must include new entries for fmadd in addition to existing entries. | |
| 27 | ||
| 8ef30996 MM |
28 | \f |
| 29 | ||
| 30 | ;; .................... | |
| 31 | ;; | |
| 32 | ;; Attributes | |
| 33 | ;; | |
| 34 | ;; .................... | |
| 35 | ||
| 36 | ;; Classification of each insn. | |
| 37 | ;; branch conditional branch | |
| 38 | ;; jump unconditional jump | |
| 39 | ;; call unconditional call | |
| 40 | ;; load load instruction(s) | |
| 41 | ;; store store instruction(s) | |
| 42 | ;; move data movement within same register set | |
| 43 | ;; xfer transfer to/from coprocessor | |
| 44 | ;; hilo transfer of hi/lo registers | |
| 45 | ;; arith integer arithmetic instruction | |
| 46 | ;; darith double precision integer arithmetic instructions | |
| 47 | ;; imul integer multiply | |
| 48 | ;; idiv integer divide | |
| 49 | ;; icmp integer compare | |
| 50 | ;; fadd floating point add/subtract | |
| 51 | ;; fmul floating point multiply | |
| e19ff60f | 52 | ;; fmadd floating point multiply-add |
| 8ef30996 MM |
53 | ;; fdiv floating point divide |
| 54 | ;; fabs floating point absolute value | |
| 55 | ;; fneg floating point negation | |
| 56 | ;; fcmp floating point compare | |
| 57 | ;; fcvt floating point convert | |
| 58 | ;; fsqrt floating point square root | |
| 59 | ;; multi multiword sequence (or user asm statements) | |
| 60 | ;; nop no operation | |
| 8ef30996 MM |
61 | |
| 62 | (define_attr "type" | |
| e19ff60f | 63 | "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop" |
| 8ef30996 MM |
64 | (const_string "unknown")) |
| 65 | ||
| 66 | ;; Main data type used by the insn | |
| 34b650b3 | 67 | (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown")) |
| 8ef30996 MM |
68 | |
| 69 | ;; # instructions (4 bytes each) | |
| 70 | (define_attr "length" "" (const_int 1)) | |
| 71 | ||
| 6d518002 | 72 | ;; whether or not an instruction has a mandatory delay slot |
| 8ef30996 | 73 | (define_attr "dslot" "no,yes" |
| c7343333 | 74 | (if_then_else (eq_attr "type" "branch,jump,call,load,xfer,hilo,fcmp") |
| 8ef30996 MM |
75 | (const_string "yes") |
| 76 | (const_string "no"))) | |
| 77 | ||
| ddd8ab48 MM |
78 | ;; Attribute describing the processor. This attribute must match exactly |
| 79 | ;; with the processor_type enumeration in mips.h. | |
| 80 | ||
| 8ef30996 | 81 | ;; Attribute describing the processor |
| ddd8ab48 MM |
82 | ;; (define_attr "cpu" "default,r3000,r6000,r4000" |
| 83 | ;; (const | |
| 84 | ;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000") | |
| 85 | ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000") | |
| 86 | ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")] | |
| 87 | ;; (const_string "default")))) | |
| 88 | ||
| e19ff60f | 89 | ;; ??? Fix everything that tests this attribute. |
| b8eb88d0 ILT |
90 | (define_attr "cpu" |
| 91 | "default,r3000,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000" | |
| ddd8ab48 | 92 | (const (symbol_ref "mips_cpu_attr"))) |
| 8ef30996 MM |
93 | |
| 94 | ;; Attribute defining whether or not we can use the branch-likely instructions | |
| 95 | ;; (MIPS ISA level 2) | |
| 96 | ||
| 97 | (define_attr "branch_likely" "no,yes" | |
| 6d518002 | 98 | (const |
| 8ef30996 MM |
99 | (if_then_else (ge (symbol_ref "mips_isa") (const_int 2)) |
| 100 | (const_string "yes") | |
| 6d518002 | 101 | (const_string "no")))) |
| 8ef30996 MM |
102 | |
| 103 | ||
| 104 | ;; Describe a user's asm statement. | |
| 105 | (define_asm_attributes | |
| 106 | [(set_attr "type" "multi")]) | |
| 107 | ||
| 84a92af4 JW |
108 | ;; whether or not generating calls to position independent functions |
| 109 | (define_attr "abicalls" "no,yes" | |
| e0a4e5a5 | 110 | (const (symbol_ref "mips_abicalls_attr"))) |
| 84a92af4 | 111 | |
| 8ef30996 MM |
112 | \f |
| 113 | ||
| 114 | ;; ......................... | |
| 115 | ;; | |
| 116 | ;; Delay slots, can't describe load/fcmp/xfer delay slots here | |
| 117 | ;; | |
| 118 | ;; ......................... | |
| 119 | ||
| 120 | (define_delay (eq_attr "type" "branch") | |
| 121 | [(and (eq_attr "dslot" "no") (eq_attr "length" "1")) | |
| 122 | (nil) | |
| bbdb5552 | 123 | (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))]) |
| 8ef30996 | 124 | |
| 84a92af4 JW |
125 | (define_delay (eq_attr "type" "jump") |
| 126 | [(and (eq_attr "dslot" "no") (eq_attr "length" "1")) | |
| 127 | (nil) | |
| 128 | (nil)]) | |
| 129 | ||
| 130 | (define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no")) | |
| 8ef30996 MM |
131 | [(and (eq_attr "dslot" "no") (eq_attr "length" "1")) |
| 132 | (nil) | |
| 133 | (nil)]) | |
| 134 | ||
| 135 | \f | |
| 136 | ||
| 137 | ;; ......................... | |
| 138 | ;; | |
| 139 | ;; Functional units | |
| 140 | ;; | |
| 141 | ;; ......................... | |
| 142 | ||
| 143 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
| c8e18a2b | 144 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) |
| 8ef30996 MM |
145 | |
| 146 | ;; Make the default case (PROCESSOR_DEFAULT) handle the worst case | |
| 147 | ||
| 148 | (define_function_unit "memory" 1 0 | |
| b8eb88d0 ILT |
149 | (and (eq_attr "type" "load") |
| 150 | (eq_attr "cpu" "!r3000,r4600,r4650,r4100,r4300,r5000")) | |
| 8ef30996 MM |
151 | 3 0) |
| 152 | ||
| 153 | (define_function_unit "memory" 1 0 | |
| b8eb88d0 ILT |
154 | (and (eq_attr "type" "load") |
| 155 | (eq_attr "cpu" "r3000,r4600,r4650,r4100,r4300,r5000")) | |
| 8ef30996 MM |
156 | 2 0) |
| 157 | ||
| ddd8ab48 | 158 | (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0) |
| 8ef30996 | 159 | |
| c3f3d7e1 | 160 | (define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0) |
| 8ef30996 | 161 | |
| bb621ad7 JW |
162 | (define_function_unit "imuldiv" 1 0 |
| 163 | (eq_attr "type" "hilo") | |
| 164 | 1 3) | |
| 165 | ||
| 166 | (define_function_unit "imuldiv" 1 0 | |
| b8eb88d0 ILT |
167 | (and (eq_attr "type" "imul") |
| 168 | (eq_attr "cpu" "!r3000,r4000,r4600,r4650,r4100,r4300,r5000")) | |
| bb621ad7 | 169 | 17 17) |
| 8ef30996 | 170 | |
| bb621ad7 | 171 | (define_function_unit "imuldiv" 1 0 |
| 8ef30996 | 172 | (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000")) |
| bb621ad7 | 173 | 12 12) |
| 8ef30996 | 174 | |
| bb621ad7 JW |
175 | (define_function_unit "imuldiv" 1 0 |
| 176 | (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000,r4600")) | |
| 177 | 10 10) | |
| 8ef30996 | 178 | |
| bb621ad7 | 179 | (define_function_unit "imuldiv" 1 0 |
| 053665d7 ILT |
180 | (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650")) |
| 181 | 4 4) | |
| 182 | ||
| 183 | (define_function_unit "imuldiv" 1 0 | |
| b8eb88d0 ILT |
184 | (and (eq_attr "type" "imul") |
| 185 | (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100"))) | |
| 8fbaea49 JW |
186 | 1 1) |
| 187 | ||
| 188 | (define_function_unit "imuldiv" 1 0 | |
| b8eb88d0 ILT |
189 | (and (eq_attr "type" "imul") |
| 190 | (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100"))) | |
| 8fbaea49 JW |
191 | 4 4) |
| 192 | ||
| 193 | (define_function_unit "imuldiv" 1 0 | |
| b8eb88d0 ILT |
194 | (and (eq_attr "type" "imul") |
| 195 | (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000"))) | |
| 8fbaea49 JW |
196 | 5 5) |
| 197 | ||
| 198 | (define_function_unit "imuldiv" 1 0 | |
| b8eb88d0 ILT |
199 | (and (eq_attr "type" "imul") |
| 200 | (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300"))) | |
| 8fbaea49 JW |
201 | 8 8) |
| 202 | ||
| 203 | (define_function_unit "imuldiv" 1 0 | |
| b8eb88d0 ILT |
204 | (and (eq_attr "type" "imul") |
| 205 | (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000"))) | |
| 206 | 9 9) | |
| 207 | ||
| 208 | (define_function_unit "imuldiv" 1 0 | |
| 209 | (and (eq_attr "type" "idiv") | |
| 210 | (eq_attr "cpu" "!r3000,r4000,r4600,r4650,r4100,r4300,r5000")) | |
| bb621ad7 | 211 | 38 38) |
| 8ef30996 | 212 | |
| bb621ad7 | 213 | (define_function_unit "imuldiv" 1 0 |
| 8ef30996 | 214 | (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000")) |
| bb621ad7 JW |
215 | 35 35) |
| 216 | ||
| 217 | (define_function_unit "imuldiv" 1 0 | |
| 218 | (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600")) | |
| 219 | 42 42) | |
| 8ef30996 | 220 | |
| 053665d7 ILT |
221 | (define_function_unit "imuldiv" 1 0 |
| 222 | (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650")) | |
| 223 | 36 36) | |
| 224 | ||
| bb621ad7 | 225 | (define_function_unit "imuldiv" 1 0 |
| 8ef30996 | 226 | (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000")) |
| bb621ad7 JW |
227 | 69 69) |
| 228 | ||
| 8fbaea49 | 229 | (define_function_unit "imuldiv" 1 0 |
| b8eb88d0 ILT |
230 | (and (eq_attr "type" "idiv") |
| 231 | (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100"))) | |
| 8fbaea49 JW |
232 | 35 35) |
| 233 | ||
| 234 | (define_function_unit "imuldiv" 1 0 | |
| b8eb88d0 ILT |
235 | (and (eq_attr "type" "idiv") |
| 236 | (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100"))) | |
| 8fbaea49 JW |
237 | 67 67) |
| 238 | ||
| 239 | (define_function_unit "imuldiv" 1 0 | |
| b8eb88d0 ILT |
240 | (and (eq_attr "type" "idiv") |
| 241 | (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300"))) | |
| 8fbaea49 JW |
242 | 37 37) |
| 243 | ||
| 244 | (define_function_unit "imuldiv" 1 0 | |
| b8eb88d0 ILT |
245 | (and (eq_attr "type" "idiv") |
| 246 | (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300"))) | |
| 8fbaea49 JW |
247 | 69 69) |
| 248 | ||
| b8eb88d0 ILT |
249 | (define_function_unit "imuldiv" 1 0 |
| 250 | (and (eq_attr "type" "idiv") | |
| 251 | (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000"))) | |
| 252 | 36 36) | |
| 253 | ||
| 254 | (define_function_unit "imuldiv" 1 0 | |
| 255 | (and (eq_attr "type" "idiv") | |
| 256 | (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000"))) | |
| 257 | 68 68) | |
| 258 | ||
| 8fbaea49 JW |
259 | ;; The R4300 does *NOT* have a seperate Floating Point Unit, instead |
| 260 | ;; the FP hardware is part of the normal ALU circuitry. This means FP | |
| 261 | ;; instructions affect the pipe-line, and no functional unit | |
| 262 | ;; parallelism can occur on R4300 processors. To force GCC into coding | |
| 263 | ;; for only a single functional unit, we force the R4300 FP | |
| 264 | ;; instructions to be processed in the "imuldiv" unit. | |
| 265 | ||
| bb621ad7 | 266 | (define_function_unit "adder" 1 1 |
| b8eb88d0 | 267 | (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r6000,r4300,r5000")) |
| bb621ad7 JW |
268 | 3 0) |
| 269 | ||
| 270 | (define_function_unit "adder" 1 1 | |
| 271 | (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r6000")) | |
| 272 | 2 0) | |
| 8ef30996 | 273 | |
| b8eb88d0 ILT |
274 | (define_function_unit "adder" 1 1 |
| 275 | (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000")) | |
| 276 | 1 0) | |
| 277 | ||
| 8ef30996 | 278 | (define_function_unit "adder" 1 1 |
| 8fbaea49 | 279 | (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r6000,r4300")) |
| c8e18a2b | 280 | 4 0) |
| 8ef30996 MM |
281 | |
| 282 | (define_function_unit "adder" 1 1 | |
| 283 | (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000")) | |
| c8e18a2b | 284 | 2 0) |
| 8ef30996 MM |
285 | |
| 286 | (define_function_unit "adder" 1 1 | |
| 287 | (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000")) | |
| c8e18a2b | 288 | 3 0) |
| 8ef30996 | 289 | |
| ddd8ab48 | 290 | (define_function_unit "adder" 1 1 |
| b8eb88d0 ILT |
291 | (and (eq_attr "type" "fabs,fneg") |
| 292 | (eq_attr "cpu" "!r3000,r4600,r4650,r4300,r5000")) | |
| c8e18a2b | 293 | 2 0) |
| 8ef30996 | 294 | |
| ddd8ab48 | 295 | (define_function_unit "adder" 1 1 |
| b8eb88d0 | 296 | (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r4600,r4650,r5000")) |
| c8e18a2b | 297 | 1 0) |
| 8ef30996 MM |
298 | |
| 299 | (define_function_unit "mult" 1 1 | |
| b8eb88d0 ILT |
300 | (and (eq_attr "type" "fmul") |
| 301 | (and (eq_attr "mode" "SF") | |
| 302 | (eq_attr "cpu" "!r3000,r6000,r4600,r4650,r4300,r5000"))) | |
| c8e18a2b | 303 | 7 0) |
| 8ef30996 MM |
304 | |
| 305 | (define_function_unit "mult" 1 1 | |
| b8eb88d0 ILT |
306 | (and (eq_attr "type" "fmul") |
| 307 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r5000"))) | |
| c8e18a2b | 308 | 4 0) |
| 8ef30996 MM |
309 | |
| 310 | (define_function_unit "mult" 1 1 | |
| b8eb88d0 ILT |
311 | (and (eq_attr "type" "fmul") |
| 312 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000"))) | |
| c8e18a2b | 313 | 5 0) |
| 8ef30996 | 314 | |
| bb621ad7 | 315 | (define_function_unit "mult" 1 1 |
| b8eb88d0 ILT |
316 | (and (eq_attr "type" "fmul") |
| 317 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650"))) | |
| bb621ad7 JW |
318 | 8 0) |
| 319 | ||
| 8ef30996 | 320 | (define_function_unit "mult" 1 1 |
| b8eb88d0 ILT |
321 | (and (eq_attr "type" "fmul") |
| 322 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r6000,r4300,r5000"))) | |
| c8e18a2b | 323 | 8 0) |
| 8ef30996 MM |
324 | |
| 325 | (define_function_unit "mult" 1 1 | |
| b8eb88d0 ILT |
326 | (and (eq_attr "type" "fmul") |
| 327 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r5000"))) | |
| c8e18a2b | 328 | 5 0) |
| 8ef30996 MM |
329 | |
| 330 | (define_function_unit "mult" 1 1 | |
| b8eb88d0 ILT |
331 | (and (eq_attr "type" "fmul") |
| 332 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000"))) | |
| c8e18a2b | 333 | 6 0) |
| 8ef30996 MM |
334 | |
| 335 | (define_function_unit "divide" 1 1 | |
| b8eb88d0 ILT |
336 | (and (eq_attr "type" "fdiv") |
| 337 | (and (eq_attr "mode" "SF") | |
| 338 | (eq_attr "cpu" "!r3000,r6000,r4600,r4650,r4300,r5000"))) | |
| c8e18a2b | 339 | 23 0) |
| 8ef30996 MM |
340 | |
| 341 | (define_function_unit "divide" 1 1 | |
| b8eb88d0 ILT |
342 | (and (eq_attr "type" "fdiv") |
| 343 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000"))) | |
| c8e18a2b | 344 | 12 0) |
| 8ef30996 MM |
345 | |
| 346 | (define_function_unit "divide" 1 1 | |
| b8eb88d0 ILT |
347 | (and (eq_attr "type" "fdiv") |
| 348 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000"))) | |
| c8e18a2b | 349 | 15 0) |
| 8ef30996 MM |
350 | |
| 351 | (define_function_unit "divide" 1 1 | |
| b8eb88d0 ILT |
352 | (and (eq_attr "type" "fdiv") |
| 353 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650"))) | |
| bb621ad7 JW |
354 | 32 0) |
| 355 | ||
| 356 | (define_function_unit "divide" 1 1 | |
| b8eb88d0 ILT |
357 | (and (eq_attr "type" "fdiv") |
| 358 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000"))) | |
| 359 | 21 0) | |
| 360 | ||
| 361 | (define_function_unit "divide" 1 1 | |
| 362 | (and (eq_attr "type" "fdiv") | |
| 363 | (and (eq_attr "mode" "DF") | |
| 364 | (eq_attr "cpu" "!r3000,r6000,r4600,r4650,r4300"))) | |
| c8e18a2b | 365 | 36 0) |
| 8ef30996 MM |
366 | |
| 367 | (define_function_unit "divide" 1 1 | |
| b8eb88d0 ILT |
368 | (and (eq_attr "type" "fdiv") |
| 369 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000"))) | |
| c8e18a2b | 370 | 19 0) |
| 8ef30996 MM |
371 | |
| 372 | (define_function_unit "divide" 1 1 | |
| b8eb88d0 ILT |
373 | (and (eq_attr "type" "fdiv") |
| 374 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000"))) | |
| c8e18a2b | 375 | 16 0) |
| 8ef30996 | 376 | |
| bb621ad7 | 377 | (define_function_unit "divide" 1 1 |
| b8eb88d0 ILT |
378 | (and (eq_attr "type" "fdiv") |
| 379 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650"))) | |
| bb621ad7 JW |
380 | 61 0) |
| 381 | ||
| 382 | ;;; ??? Is this number right? | |
| 383 | (define_function_unit "divide" 1 1 | |
| b8eb88d0 ILT |
384 | (and (eq_attr "type" "fsqrt") |
| 385 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000"))) | |
| bb621ad7 | 386 | 54 0) |
| b8eb88d0 | 387 | |
| bb621ad7 | 388 | (define_function_unit "divide" 1 1 |
| b8eb88d0 ILT |
389 | (and (eq_attr "type" "fsqrt") |
| 390 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650"))) | |
| bb621ad7 JW |
391 | 31 0) |
| 392 | ||
| b8eb88d0 ILT |
393 | (define_function_unit "divide" 1 1 |
| 394 | (and (eq_attr "type" "fsqrt") | |
| 395 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000"))) | |
| 396 | 21 0) | |
| 397 | ||
| bb621ad7 JW |
398 | ;;; ??? Is this number right? |
| 399 | (define_function_unit "divide" 1 1 | |
| b8eb88d0 ILT |
400 | (and (eq_attr "type" "fsqrt") |
| 401 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000"))) | |
| bb621ad7 | 402 | 112 0) |
| b8eb88d0 | 403 | |
| bb621ad7 | 404 | (define_function_unit "divide" 1 1 |
| b8eb88d0 ILT |
405 | (and (eq_attr "type" "fsqrt") |
| 406 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650"))) | |
| bb621ad7 | 407 | 60 0) |
| 8ef30996 | 408 | |
| b8eb88d0 ILT |
409 | (define_function_unit "divide" 1 1 |
| 410 | (and (eq_attr "type" "fsqrt") | |
| 411 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000"))) | |
| 412 | 36 0) | |
| 413 | ||
| 8fbaea49 JW |
414 | ;; R4300 FP instruction classes treated as part of the "imuldiv" |
| 415 | ;; functional unit: | |
| 416 | ||
| 417 | (define_function_unit "imuldiv" 1 0 | |
| 418 | (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300")) | |
| 419 | 3 3) | |
| 420 | ||
| aa4e54c4 JW |
421 | (define_function_unit "imuldiv" 1 0 |
| 422 | (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300")) | |
| 423 | 1 1) | |
| 424 | ||
| 8fbaea49 JW |
425 | (define_function_unit "imuldiv" 1 0 |
| 426 | (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300"))) | |
| 427 | 5 5) | |
| 428 | (define_function_unit "imuldiv" 1 0 | |
| 429 | (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300"))) | |
| 430 | 8 8) | |
| 431 | ||
| 432 | (define_function_unit "imuldiv" 1 0 | |
| 433 | (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt")) | |
| 434 | (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300"))) | |
| 435 | 29 29) | |
| 436 | (define_function_unit "imuldiv" 1 0 | |
| 437 | (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt")) | |
| 438 | (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300"))) | |
| 439 | 58 58) | |
| ddd8ab48 MM |
440 | \f |
| 441 | ;; The following functional units do not use the cpu type, and use | |
| 442 | ;; much less memory in genattrtab.c. | |
| 443 | ||
| c8e18a2b TW |
444 | ;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0) |
| 445 | ;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0) | |
| ddd8ab48 | 446 | ;; |
| c8e18a2b | 447 | ;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0) |
| ddd8ab48 | 448 | ;; |
| c8e18a2b TW |
449 | ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0) |
| 450 | ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0) | |
| ddd8ab48 | 451 | ;; |
| c8e18a2b TW |
452 | ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0) |
| 453 | ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0) | |
| ddd8ab48 | 454 | ;; |
| c8e18a2b TW |
455 | ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0) |
| 456 | ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0) | |
| ddd8ab48 | 457 | ;; |
| c8e18a2b TW |
458 | ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0) |
| 459 | ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0) | |
| ddd8ab48 | 460 | ;; |
| c8e18a2b TW |
461 | ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0) |
| 462 | ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0) | |
| ddd8ab48 | 463 | ;; |
| c8e18a2b TW |
464 | ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0) |
| 465 | ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0) | |
| ddd8ab48 | 466 | |
| 8ef30996 MM |
467 | \f |
| 468 | ;; | |
| 469 | ;; .................... | |
| 470 | ;; | |
| 471 | ;; ADDITION | |
| 472 | ;; | |
| 473 | ;; .................... | |
| 474 | ;; | |
| 475 | ||
| 476 | (define_insn "adddf3" | |
| 477 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 478 | (plus:DF (match_operand:DF 1 "register_operand" "f") | |
| 479 | (match_operand:DF 2 "register_operand" "f")))] | |
| 46299de9 | 480 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
481 | "add.d\\t%0,%1,%2" |
| 482 | [(set_attr "type" "fadd") | |
| 483 | (set_attr "mode" "DF") | |
| 484 | (set_attr "length" "1")]) | |
| 485 | ||
| 486 | (define_insn "addsf3" | |
| 487 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 488 | (plus:SF (match_operand:SF 1 "register_operand" "f") | |
| 489 | (match_operand:SF 2 "register_operand" "f")))] | |
| 490 | "TARGET_HARD_FLOAT" | |
| 491 | "add.s\\t%0,%1,%2" | |
| 492 | [(set_attr "type" "fadd") | |
| 493 | (set_attr "mode" "SF") | |
| 494 | (set_attr "length" "1")]) | |
| 495 | ||
| 71cd5224 | 496 | (define_expand "addsi3" |
| 8ef30996 | 497 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 71cd5224 | 498 | (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") |
| 8ef30996 MM |
499 | (match_operand:SI 2 "arith_operand" "dI")))] |
| 500 | "" | |
| 71cd5224 RS |
501 | " |
| 502 | { | |
| 503 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768) | |
| 504 | operands[2] = force_reg (SImode, operands[2]); | |
| 505 | }") | |
| 506 | ||
| 507 | (define_insn "addsi3_internal" | |
| 508 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 509 | (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 510 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 511 | "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768" | |
| 9b190d1c | 512 | "addu\\t%0,%z1,%2" |
| 8ef30996 MM |
513 | [(set_attr "type" "arith") |
| 514 | (set_attr "mode" "SI") | |
| 515 | (set_attr "length" "1")]) | |
| 516 | ||
| 517 | (define_expand "adddi3" | |
| 518 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
| 519 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
| 520 | (match_operand:DI 2 "arith_operand" ""))) | |
| 521 | (clobber (match_dup 3))])] | |
| bb621ad7 | 522 | "TARGET_64BIT || !TARGET_DEBUG_G_MODE" |
| 92b4cee1 MM |
523 | " |
| 524 | { | |
| 525 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768) | |
| b0565769 | 526 | operands[2] = force_reg (DImode, operands[2]); |
| 92b4cee1 | 527 | |
| bb621ad7 JW |
528 | if (TARGET_64BIT) |
| 529 | { | |
| 530 | emit_insn (gen_adddi3_internal_3 (operands[0], operands[1], | |
| 531 | operands[2])); | |
| 532 | DONE; | |
| 533 | } | |
| 534 | ||
| 92b4cee1 MM |
535 | operands[3] = gen_reg_rtx (SImode); |
| 536 | }") | |
| 8ef30996 MM |
537 | |
| 538 | (define_insn "adddi3_internal_1" | |
| 539 | [(set (match_operand:DI 0 "register_operand" "=d,&d") | |
| 540 | (plus:DI (match_operand:DI 1 "register_operand" "0,d") | |
| 541 | (match_operand:DI 2 "register_operand" "d,d"))) | |
| 542 | (clobber (match_operand:SI 3 "register_operand" "=d,d"))] | |
| bb621ad7 | 543 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE" |
| 8ef30996 MM |
544 | "* |
| 545 | { | |
| 546 | return (REGNO (operands[0]) == REGNO (operands[1]) | |
| 547 | && REGNO (operands[0]) == REGNO (operands[2])) | |
| 548 | ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\" | |
| 549 | : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\"; | |
| 550 | }" | |
| 92b4cee1 MM |
551 | [(set_attr "type" "darith") |
| 552 | (set_attr "mode" "DI") | |
| 553 | (set_attr "length" "4")]) | |
| 8ef30996 MM |
554 | |
| 555 | (define_split | |
| 556 | [(set (match_operand:DI 0 "register_operand" "") | |
| 557 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
| 558 | (match_operand:DI 2 "register_operand" ""))) | |
| 559 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 560 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
561 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 562 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 563 | && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2])) | |
| 564 | && (REGNO (operands[0]) != REGNO (operands[1]) | |
| 565 | || REGNO (operands[0]) != REGNO (operands[2]))" | |
| 566 | ||
| 567 | [(set (subreg:SI (match_dup 0) 0) | |
| 568 | (plus:SI (subreg:SI (match_dup 1) 0) | |
| 569 | (subreg:SI (match_dup 2) 0))) | |
| 570 | ||
| 571 | (set (match_dup 3) | |
| 34b650b3 | 572 | (ltu:SI (subreg:SI (match_dup 0) 0) |
| 8ef30996 MM |
573 | (subreg:SI (match_dup 2) 0))) |
| 574 | ||
| 575 | (set (subreg:SI (match_dup 0) 1) | |
| 576 | (plus:SI (subreg:SI (match_dup 1) 1) | |
| 577 | (subreg:SI (match_dup 2) 1))) | |
| 578 | ||
| 579 | (set (subreg:SI (match_dup 0) 1) | |
| 580 | (plus:SI (subreg:SI (match_dup 0) 1) | |
| 581 | (match_dup 3)))] | |
| 582 | "") | |
| 583 | ||
| 584 | (define_split | |
| 585 | [(set (match_operand:DI 0 "register_operand" "") | |
| 586 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
| 587 | (match_operand:DI 2 "register_operand" ""))) | |
| 588 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 589 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
590 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 591 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 592 | && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2])) | |
| 593 | && (REGNO (operands[0]) != REGNO (operands[1]) | |
| 594 | || REGNO (operands[0]) != REGNO (operands[2]))" | |
| 595 | ||
| 596 | [(set (subreg:SI (match_dup 0) 1) | |
| 597 | (plus:SI (subreg:SI (match_dup 1) 1) | |
| 598 | (subreg:SI (match_dup 2) 1))) | |
| 599 | ||
| 600 | (set (match_dup 3) | |
| 34b650b3 | 601 | (ltu:SI (subreg:SI (match_dup 0) 1) |
| 8ef30996 MM |
602 | (subreg:SI (match_dup 2) 1))) |
| 603 | ||
| 604 | (set (subreg:SI (match_dup 0) 0) | |
| 605 | (plus:SI (subreg:SI (match_dup 1) 0) | |
| 606 | (subreg:SI (match_dup 2) 0))) | |
| 607 | ||
| 608 | (set (subreg:SI (match_dup 0) 0) | |
| 609 | (plus:SI (subreg:SI (match_dup 0) 0) | |
| 610 | (match_dup 3)))] | |
| 611 | "") | |
| 612 | ||
| 613 | (define_insn "adddi3_internal_2" | |
| 614 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
| 615 | (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d") | |
| 616 | (match_operand:DI 2 "small_int" "P,J,N"))) | |
| 617 | (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))] | |
| bb621ad7 | 618 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768" |
| 8ef30996 MM |
619 | "@ |
| 620 | addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3 | |
| 621 | move\\t%L0,%L1\;move\\t%M0,%M1 | |
| 622 | subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3" | |
| 92b4cee1 MM |
623 | [(set_attr "type" "darith") |
| 624 | (set_attr "mode" "DI") | |
| 8ef30996 MM |
625 | (set_attr "length" "3,2,4")]) |
| 626 | ||
| 627 | (define_split | |
| 628 | [(set (match_operand:DI 0 "register_operand" "") | |
| 629 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
| 630 | (match_operand:DI 2 "small_int" ""))) | |
| 631 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 632 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
633 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 634 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 635 | && INTVAL (operands[2]) > 0" | |
| 636 | ||
| 637 | [(set (subreg:SI (match_dup 0) 0) | |
| 638 | (plus:SI (subreg:SI (match_dup 1) 0) | |
| 639 | (match_dup 2))) | |
| 640 | ||
| 641 | (set (match_dup 3) | |
| 34b650b3 | 642 | (ltu:SI (subreg:SI (match_dup 0) 0) |
| 8ef30996 MM |
643 | (match_dup 2))) |
| 644 | ||
| 645 | (set (subreg:SI (match_dup 0) 1) | |
| 646 | (plus:SI (subreg:SI (match_dup 1) 1) | |
| 647 | (match_dup 3)))] | |
| 648 | "") | |
| 649 | ||
| 650 | (define_split | |
| 651 | [(set (match_operand:DI 0 "register_operand" "") | |
| 652 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
| 653 | (match_operand:DI 2 "small_int" ""))) | |
| 654 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 655 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
656 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 657 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 658 | && INTVAL (operands[2]) > 0" | |
| 659 | ||
| 660 | [(set (subreg:SI (match_dup 0) 1) | |
| 661 | (plus:SI (subreg:SI (match_dup 1) 1) | |
| 662 | (match_dup 2))) | |
| 663 | ||
| 664 | (set (match_dup 3) | |
| 34b650b3 | 665 | (ltu:SI (subreg:SI (match_dup 0) 1) |
| 8ef30996 MM |
666 | (match_dup 2))) |
| 667 | ||
| 668 | (set (subreg:SI (match_dup 0) 0) | |
| 669 | (plus:SI (subreg:SI (match_dup 1) 0) | |
| 670 | (match_dup 3)))] | |
| 671 | "") | |
| bb621ad7 JW |
672 | |
| 673 | (define_insn "adddi3_internal_3" | |
| 674 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 675 | (plus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ") | |
| 676 | (match_operand:DI 2 "arith_operand" "dI")))] | |
| 677 | "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" | |
| 678 | "* | |
| 679 | { | |
| 680 | return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
| 681 | ? \"dsubu\\t%0,%z1,%n2\" | |
| 682 | : \"daddu\\t%0,%z1,%2\"; | |
| 683 | }" | |
| 684 | [(set_attr "type" "darith") | |
| 685 | (set_attr "mode" "DI") | |
| 686 | (set_attr "length" "1")]) | |
| 687 | ||
| 688 | ||
| 689 | (define_insn "addsi3_internal_2" | |
| 690 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 691 | (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 692 | (match_operand:SI 2 "arith_operand" "dI"))))] | |
| 693 | "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" | |
| 694 | "* | |
| 695 | { | |
| 696 | return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
| 697 | ? \"subu\\t%0,%z1,%n2\" | |
| 698 | : \"addu\\t%0,%z1,%2\"; | |
| 699 | }" | |
| 700 | [(set_attr "type" "arith") | |
| 701 | (set_attr "mode" "SI") | |
| 702 | (set_attr "length" "1")]) | |
| 703 | ||
| 8ef30996 MM |
704 | \f |
| 705 | ;; | |
| 706 | ;; .................... | |
| 707 | ;; | |
| 708 | ;; SUBTRACTION | |
| 709 | ;; | |
| 710 | ;; .................... | |
| 711 | ;; | |
| 712 | ||
| 713 | (define_insn "subdf3" | |
| 714 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 715 | (minus:DF (match_operand:DF 1 "register_operand" "f") | |
| 716 | (match_operand:DF 2 "register_operand" "f")))] | |
| 46299de9 | 717 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
718 | "sub.d\\t%0,%1,%2" |
| 719 | [(set_attr "type" "fadd") | |
| 720 | (set_attr "mode" "DF") | |
| 721 | (set_attr "length" "1")]) | |
| 722 | ||
| 723 | (define_insn "subsf3" | |
| 724 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 725 | (minus:SF (match_operand:SF 1 "register_operand" "f") | |
| 726 | (match_operand:SF 2 "register_operand" "f")))] | |
| 727 | "TARGET_HARD_FLOAT" | |
| 728 | "sub.s\\t%0,%1,%2" | |
| 729 | [(set_attr "type" "fadd") | |
| 730 | (set_attr "mode" "SF") | |
| 731 | (set_attr "length" "1")]) | |
| 732 | ||
| 71cd5224 | 733 | (define_expand "subsi3" |
| 8ef30996 MM |
734 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 735 | (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 736 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 737 | "" | |
| 71cd5224 RS |
738 | " |
| 739 | { | |
| 740 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768) | |
| 741 | operands[2] = force_reg (SImode, operands[2]); | |
| 742 | }") | |
| 743 | ||
| 744 | (define_insn "subsi3_internal" | |
| 745 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 746 | (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 747 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 748 | "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768" | |
| 9b190d1c | 749 | "subu\\t%0,%z1,%2" |
| 8ef30996 MM |
750 | [(set_attr "type" "arith") |
| 751 | (set_attr "mode" "SI") | |
| 752 | (set_attr "length" "1")]) | |
| 753 | ||
| 754 | (define_expand "subdi3" | |
| 755 | [(parallel [(set (match_operand:DI 0 "register_operand" "=d") | |
| 756 | (minus:DI (match_operand:DI 1 "register_operand" "d") | |
| 757 | (match_operand:DI 2 "register_operand" "d"))) | |
| 758 | (clobber (match_dup 3))])] | |
| bb621ad7 JW |
759 | "TARGET_64BIT || !TARGET_DEBUG_G_MODE" |
| 760 | " | |
| 761 | { | |
| 762 | if (TARGET_64BIT) | |
| 763 | { | |
| 764 | emit_insn (gen_subdi3_internal_3 (operands[0], operands[1], | |
| 765 | operands[2])); | |
| 766 | DONE; | |
| 767 | } | |
| 768 | ||
| 769 | operands[3] = gen_reg_rtx (SImode); | |
| 770 | }") | |
| 8ef30996 MM |
771 | |
| 772 | (define_insn "subdi3_internal" | |
| 773 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 774 | (minus:DI (match_operand:DI 1 "register_operand" "d") | |
| 775 | (match_operand:DI 2 "register_operand" "d"))) | |
| 776 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 777 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE" |
| 8ef30996 MM |
778 | "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3" |
| 779 | [(set_attr "type" "darith") | |
| 780 | (set_attr "mode" "DI") | |
| 781 | (set_attr "length" "4")]) | |
| 782 | ||
| 783 | (define_split | |
| 784 | [(set (match_operand:DI 0 "register_operand" "") | |
| 785 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
| 786 | (match_operand:DI 2 "register_operand" ""))) | |
| 787 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 788 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
789 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 790 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 791 | && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" | |
| 792 | ||
| 793 | [(set (match_dup 3) | |
| 34b650b3 | 794 | (ltu:SI (subreg:SI (match_dup 1) 0) |
| 6d518002 | 795 | (subreg:SI (match_dup 2) 0))) |
| 8ef30996 MM |
796 | |
| 797 | (set (subreg:SI (match_dup 0) 0) | |
| 798 | (minus:SI (subreg:SI (match_dup 1) 0) | |
| 799 | (subreg:SI (match_dup 2) 0))) | |
| 800 | ||
| 801 | (set (subreg:SI (match_dup 0) 1) | |
| 802 | (minus:SI (subreg:SI (match_dup 1) 1) | |
| 803 | (subreg:SI (match_dup 2) 1))) | |
| 804 | ||
| 805 | (set (subreg:SI (match_dup 0) 1) | |
| 806 | (minus:SI (subreg:SI (match_dup 0) 1) | |
| 807 | (match_dup 3)))] | |
| 808 | "") | |
| 809 | ||
| 810 | (define_split | |
| 811 | [(set (match_operand:DI 0 "register_operand" "") | |
| 812 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
| 813 | (match_operand:DI 2 "register_operand" ""))) | |
| 814 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 815 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
816 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 817 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 818 | && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" | |
| 819 | ||
| 820 | [(set (match_dup 3) | |
| 34b650b3 | 821 | (ltu:SI (subreg:SI (match_dup 1) 1) |
| 6d518002 | 822 | (subreg:SI (match_dup 2) 1))) |
| 8ef30996 MM |
823 | |
| 824 | (set (subreg:SI (match_dup 0) 1) | |
| 825 | (minus:SI (subreg:SI (match_dup 1) 1) | |
| 826 | (subreg:SI (match_dup 2) 1))) | |
| 827 | ||
| 828 | (set (subreg:SI (match_dup 0) 0) | |
| 829 | (minus:SI (subreg:SI (match_dup 1) 0) | |
| 830 | (subreg:SI (match_dup 2) 0))) | |
| 831 | ||
| 832 | (set (subreg:SI (match_dup 0) 0) | |
| 833 | (minus:SI (subreg:SI (match_dup 0) 0) | |
| 834 | (match_dup 3)))] | |
| 835 | "") | |
| 836 | ||
| 837 | (define_insn "subdi3_internal_2" | |
| 838 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
| 839 | (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
| 840 | (match_operand:DI 2 "small_int" "P,J,N"))) | |
| 841 | (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))] | |
| bb621ad7 | 842 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768" |
| 8ef30996 MM |
843 | "@ |
| 844 | sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3 | |
| 845 | move\\t%L0,%L1\;move\\t%M0,%M1 | |
| 846 | sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3" | |
| 92b4cee1 MM |
847 | [(set_attr "type" "darith") |
| 848 | (set_attr "mode" "DI") | |
| 8ef30996 MM |
849 | (set_attr "length" "3,2,4")]) |
| 850 | ||
| 851 | (define_split | |
| 852 | [(set (match_operand:DI 0 "register_operand" "") | |
| 853 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
| 854 | (match_operand:DI 2 "small_int" ""))) | |
| 855 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 856 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
857 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 858 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 859 | && INTVAL (operands[2]) > 0" | |
| 860 | ||
| 861 | [(set (match_dup 3) | |
| 34b650b3 | 862 | (ltu:SI (subreg:SI (match_dup 1) 0) |
| 8ef30996 MM |
863 | (match_dup 2))) |
| 864 | ||
| 865 | (set (subreg:SI (match_dup 0) 0) | |
| 866 | (minus:SI (subreg:SI (match_dup 1) 0) | |
| 867 | (match_dup 2))) | |
| 868 | ||
| 869 | (set (subreg:SI (match_dup 0) 1) | |
| 870 | (minus:SI (subreg:SI (match_dup 1) 1) | |
| 871 | (match_dup 3)))] | |
| 872 | "") | |
| 873 | ||
| 874 | (define_split | |
| 875 | [(set (match_operand:DI 0 "register_operand" "") | |
| 876 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
| 877 | (match_operand:DI 2 "small_int" ""))) | |
| 878 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 879 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
880 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 881 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 882 | && INTVAL (operands[2]) > 0" | |
| 883 | ||
| 884 | [(set (match_dup 3) | |
| 34b650b3 | 885 | (ltu:SI (subreg:SI (match_dup 1) 1) |
| 8ef30996 MM |
886 | (match_dup 2))) |
| 887 | ||
| 888 | (set (subreg:SI (match_dup 0) 1) | |
| 889 | (minus:SI (subreg:SI (match_dup 1) 1) | |
| 890 | (match_dup 2))) | |
| 891 | ||
| 892 | (set (subreg:SI (match_dup 0) 0) | |
| 893 | (minus:SI (subreg:SI (match_dup 1) 0) | |
| 894 | (match_dup 3)))] | |
| 895 | "") | |
| 896 | ||
| bb621ad7 JW |
897 | (define_insn "subdi3_internal_3" |
| 898 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 899 | (minus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ") | |
| 900 | (match_operand:DI 2 "arith_operand" "dI")))] | |
| 901 | "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" | |
| 902 | "* | |
| 903 | { | |
| 904 | return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
| 905 | ? \"daddu\\t%0,%z1,%n2\" | |
| 906 | : \"dsubu\\t%0,%z1,%2\"; | |
| 907 | }" | |
| 908 | [(set_attr "type" "darith") | |
| 909 | (set_attr "mode" "DI") | |
| 910 | (set_attr "length" "1")]) | |
| 911 | ||
| 912 | ||
| 913 | (define_insn "subsi3_internal_2" | |
| 914 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 915 | (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 916 | (match_operand:SI 2 "arith_operand" "dI"))))] | |
| 917 | "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" | |
| 918 | "* | |
| 919 | { | |
| 920 | return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
| 921 | ? \"addu\\t%0,%z1,%n2\" | |
| 922 | : \"subu\\t%0,%z1,%2\"; | |
| 923 | }" | |
| 924 | [(set_attr "type" "arith") | |
| 925 | (set_attr "mode" "DI") | |
| 926 | (set_attr "length" "1")]) | |
| 927 | ||
| 8ef30996 MM |
928 | \f |
| 929 | ;; | |
| 930 | ;; .................... | |
| 931 | ;; | |
| 932 | ;; MULTIPLICATION | |
| 933 | ;; | |
| 934 | ;; .................... | |
| 935 | ;; | |
| 936 | ||
| aa4e54c4 JW |
937 | ;; Early Vr4300 silicon has a CPU bug where multiplies with certain |
| 938 | ;; operands may corrupt immediately following multiplies. This is a | |
| 939 | ;; simple fix to insert NOPs. | |
| 8fbaea49 JW |
940 | |
| 941 | (define_expand "muldf3" | |
| 8ef30996 MM |
942 | [(set (match_operand:DF 0 "register_operand" "=f") |
| 943 | (mult:DF (match_operand:DF 1 "register_operand" "f") | |
| 944 | (match_operand:DF 2 "register_operand" "f")))] | |
| 46299de9 | 945 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8fbaea49 JW |
946 | " |
| 947 | { | |
| 948 | if (mips_cpu != PROCESSOR_R4300) | |
| 949 | emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2])); | |
| 950 | else | |
| 951 | emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2])); | |
| 952 | DONE; | |
| 953 | }") | |
| 954 | ||
| 955 | (define_insn "muldf3_internal" | |
| 956 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 957 | (mult:DF (match_operand:DF 1 "register_operand" "f") | |
| 958 | (match_operand:DF 2 "register_operand" "f")))] | |
| 959 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300" | |
| 8ef30996 MM |
960 | "mul.d\\t%0,%1,%2" |
| 961 | [(set_attr "type" "fmul") | |
| 962 | (set_attr "mode" "DF") | |
| 963 | (set_attr "length" "1")]) | |
| 964 | ||
| 8fbaea49 JW |
965 | (define_insn "muldf3_r4300" |
| 966 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 967 | (mult:DF (match_operand:DF 1 "register_operand" "f") | |
| 968 | (match_operand:DF 2 "register_operand" "f")))] | |
| 969 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300" | |
| 970 | "* | |
| 971 | { | |
| 972 | output_asm_insn (\"mul.d\\t%0,%1,%2\", operands); | |
| 973 | if (TARGET_4300_MUL_FIX) | |
| 974 | output_asm_insn (\"nop\", operands); | |
| 975 | return \"\"; | |
| 976 | }" | |
| 977 | [(set_attr "type" "fmul") | |
| 978 | (set_attr "mode" "DF") | |
| 979 | (set_attr "length" "2")]) ;; mul.d + nop | |
| 980 | ||
| 981 | (define_expand "mulsf3" | |
| 8ef30996 MM |
982 | [(set (match_operand:SF 0 "register_operand" "=f") |
| 983 | (mult:SF (match_operand:SF 1 "register_operand" "f") | |
| 984 | (match_operand:SF 2 "register_operand" "f")))] | |
| 985 | "TARGET_HARD_FLOAT" | |
| 8fbaea49 JW |
986 | " |
| 987 | { | |
| 988 | if (mips_cpu != PROCESSOR_R4300) | |
| 989 | emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2])); | |
| 990 | else | |
| 991 | emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2])); | |
| 992 | DONE; | |
| 993 | }") | |
| 994 | ||
| 995 | (define_insn "mulsf3_internal" | |
| 996 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 997 | (mult:SF (match_operand:SF 1 "register_operand" "f") | |
| 998 | (match_operand:SF 2 "register_operand" "f")))] | |
| 999 | "TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300" | |
| 8ef30996 MM |
1000 | "mul.s\\t%0,%1,%2" |
| 1001 | [(set_attr "type" "fmul") | |
| 1002 | (set_attr "mode" "SF") | |
| 1003 | (set_attr "length" "1")]) | |
| 1004 | ||
| 8fbaea49 JW |
1005 | (define_insn "mulsf3_r4300" |
| 1006 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1007 | (mult:SF (match_operand:SF 1 "register_operand" "f") | |
| 1008 | (match_operand:SF 2 "register_operand" "f")))] | |
| 1009 | "TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300" | |
| 1010 | "* | |
| 1011 | { | |
| 1012 | output_asm_insn (\"mul.s\\t%0,%1,%2\", operands); | |
| 1013 | if (TARGET_4300_MUL_FIX) | |
| 1014 | output_asm_insn (\"nop\", operands); | |
| 1015 | return \"\"; | |
| 1016 | }" | |
| 1017 | [(set_attr "type" "fmul") | |
| 1018 | (set_attr "mode" "SF") | |
| 1019 | (set_attr "length" "2")]) ;; mul.s + nop | |
| 1020 | ||
| 46299de9 ILT |
1021 | ;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while |
| 1022 | ;; a multiply is in progress, it may give an incorrect result. Avoid | |
| 1023 | ;; this by keeping the mflo with the mult on the R4000. | |
| 1024 | ||
| 1025 | (define_expand "mulsi3" | |
| 1026 | [(set (match_operand:SI 0 "register_operand" "=l") | |
| 8ef30996 MM |
1027 | (mult:SI (match_operand:SI 1 "register_operand" "d") |
| 1028 | (match_operand:SI 2 "register_operand" "d"))) | |
| 225b8835 ILT |
1029 | (clobber (match_scratch:SI 3 "=h")) |
| 1030 | (clobber (match_scratch:SI 4 "=a"))] | |
| 8ef30996 | 1031 | "" |
| 46299de9 ILT |
1032 | " |
| 1033 | { | |
| 053665d7 ILT |
1034 | if (TARGET_MAD) |
| 1035 | emit_insn (gen_mulsi3_r4650 (operands[0], operands[1], operands[2])); | |
| 1036 | else if (mips_cpu != PROCESSOR_R4000) | |
| 46299de9 ILT |
1037 | emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2])); |
| 1038 | else | |
| 1039 | emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2])); | |
| 1040 | DONE; | |
| 1041 | }") | |
| 1042 | ||
| 1043 | (define_insn "mulsi3_internal" | |
| 1044 | [(set (match_operand:SI 0 "register_operand" "=l") | |
| 1045 | (mult:SI (match_operand:SI 1 "register_operand" "d") | |
| 1046 | (match_operand:SI 2 "register_operand" "d"))) | |
| 225b8835 ILT |
1047 | (clobber (match_scratch:SI 3 "=h")) |
| 1048 | (clobber (match_scratch:SI 4 "=a"))] | |
| 46299de9 ILT |
1049 | "mips_cpu != PROCESSOR_R4000" |
| 1050 | "mult\\t%1,%2" | |
| 1051 | [(set_attr "type" "imul") | |
| 1052 | (set_attr "mode" "SI") | |
| 1053 | (set_attr "length" "1")]) | |
| 1054 | ||
| 1055 | (define_insn "mulsi3_r4000" | |
| 1056 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1057 | (mult:SI (match_operand:SI 1 "register_operand" "d") | |
| 1058 | (match_operand:SI 2 "register_operand" "d"))) | |
| 1059 | (clobber (match_scratch:SI 3 "=h")) | |
| 225b8835 ILT |
1060 | (clobber (match_scratch:SI 4 "=l")) |
| 1061 | (clobber (match_scratch:SI 5 "=a"))] | |
| 46299de9 | 1062 | "mips_cpu == PROCESSOR_R4000" |
| 8ef30996 MM |
1063 | "* |
| 1064 | { | |
| 1065 | rtx xoperands[10]; | |
| 1066 | ||
| 1067 | xoperands[0] = operands[0]; | |
| 1068 | xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM); | |
| 1069 | ||
| 1070 | output_asm_insn (\"mult\\t%1,%2\", operands); | |
| bb621ad7 | 1071 | output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands); |
| 8ef30996 MM |
1072 | return \"\"; |
| 1073 | }" | |
| 1074 | [(set_attr "type" "imul") | |
| 1075 | (set_attr "mode" "SI") | |
| 1076 | (set_attr "length" "3")]) ;; mult + mflo + delay | |
| 1077 | ||
| 053665d7 ILT |
1078 | (define_insn "mulsi3_r4650" |
| 1079 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1080 | (mult:SI (match_operand:SI 1 "register_operand" "d") | |
| 1081 | (match_operand:SI 2 "register_operand" "d"))) | |
| 1082 | (clobber (match_scratch:SI 3 "=h")) | |
| 225b8835 ILT |
1083 | (clobber (match_scratch:SI 4 "=l")) |
| 1084 | (clobber (match_scratch:SI 5 "=a"))] | |
| 053665d7 ILT |
1085 | "TARGET_MAD" |
| 1086 | "mul\\t%0,%1,%2" | |
| 1087 | [(set_attr "type" "imul") | |
| 1088 | (set_attr "mode" "SI") | |
| 1089 | (set_attr "length" "1")]) | |
| 1090 | ||
| 46299de9 ILT |
1091 | (define_expand "muldi3" |
| 1092 | [(set (match_operand:DI 0 "register_operand" "=l") | |
| 1093 | (mult:DI (match_operand:DI 1 "register_operand" "d") | |
| 1094 | (match_operand:DI 2 "register_operand" "d"))) | |
| 225b8835 ILT |
1095 | (clobber (match_scratch:DI 3 "=h")) |
| 1096 | (clobber (match_scratch:DI 4 "=a"))] | |
| 46299de9 ILT |
1097 | "TARGET_64BIT" |
| 1098 | " | |
| 1099 | { | |
| 1100 | if (mips_cpu != PROCESSOR_R4000) | |
| 1101 | emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2])); | |
| 1102 | else | |
| 1103 | emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2])); | |
| 1104 | DONE; | |
| 1105 | }") | |
| 8ef30996 | 1106 | |
| 46299de9 ILT |
1107 | (define_insn "muldi3_internal" |
| 1108 | [(set (match_operand:DI 0 "register_operand" "=l") | |
| 1109 | (mult:DI (match_operand:DI 1 "register_operand" "d") | |
| 1110 | (match_operand:DI 2 "register_operand" "d"))) | |
| 225b8835 ILT |
1111 | (clobber (match_scratch:DI 3 "=h")) |
| 1112 | (clobber (match_scratch:DI 4 "=a"))] | |
| 46299de9 | 1113 | "TARGET_64BIT && mips_cpu != PROCESSOR_R4000" |
| e7faa2f6 | 1114 | "dmult\\t%1,%2" |
| 8ef30996 | 1115 | [(set_attr "type" "imul") |
| 46299de9 | 1116 | (set_attr "mode" "DI") |
| 8ef30996 MM |
1117 | (set_attr "length" "1")]) |
| 1118 | ||
| 46299de9 | 1119 | (define_insn "muldi3_r4000" |
| bb621ad7 JW |
1120 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 1121 | (mult:DI (match_operand:DI 1 "register_operand" "d") | |
| 1122 | (match_operand:DI 2 "register_operand" "d"))) | |
| 46299de9 | 1123 | (clobber (match_scratch:DI 3 "=h")) |
| 225b8835 ILT |
1124 | (clobber (match_scratch:DI 4 "=l")) |
| 1125 | (clobber (match_scratch:DI 5 "=a"))] | |
| 46299de9 | 1126 | "TARGET_64BIT && mips_cpu == PROCESSOR_R4000" |
| bb621ad7 JW |
1127 | "* |
| 1128 | { | |
| 1129 | rtx xoperands[10]; | |
| 1130 | ||
| 1131 | xoperands[0] = operands[0]; | |
| 1132 | xoperands[1] = gen_rtx (REG, DImode, LO_REGNUM); | |
| 1133 | ||
| 1134 | output_asm_insn (\"dmult\\t%1,%2\", operands); | |
| 1135 | output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands); | |
| 1136 | return \"\"; | |
| 1137 | }" | |
| 1138 | [(set_attr "type" "imul") | |
| 1139 | (set_attr "mode" "DI") | |
| 1140 | (set_attr "length" "3")]) ;; mult + mflo + delay | |
| 1141 | ||
| bb621ad7 JW |
1142 | ;; ??? We could define a mulditi3 pattern when TARGET_64BIT. |
| 1143 | ||
| 225b8835 | 1144 | (define_expand "mulsidi3" |
| 46299de9 | 1145 | [(set (match_operand:DI 0 "register_operand" "=x") |
| 8ef30996 | 1146 | (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) |
| 46299de9 | 1147 | (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] |
| 225b8835 ILT |
1148 | "" |
| 1149 | " | |
| 1150 | { | |
| 1151 | if (TARGET_64BIT) | |
| 1152 | emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2])); | |
| 1153 | else | |
| 1154 | emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2])); | |
| 1155 | DONE; | |
| 1156 | }") | |
| 1157 | ||
| 1158 | (define_insn "mulsidi3_internal" | |
| 1159 | [(set (match_operand:DI 0 "register_operand" "=x") | |
| 1160 | (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) | |
| 1161 | (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))) | |
| 1162 | (clobber (match_scratch:SI 3 "=a"))] | |
| bb621ad7 | 1163 | "!TARGET_64BIT" |
| 46299de9 | 1164 | "mult\\t%1,%2" |
| 8ef30996 MM |
1165 | [(set_attr "type" "imul") |
| 1166 | (set_attr "mode" "SI") | |
| 46299de9 | 1167 | (set_attr "length" "1")]) |
| 8ef30996 | 1168 | |
| 225b8835 ILT |
1169 | (define_insn "mulsidi3_64bit" |
| 1170 | [(set (match_operand:DI 0 "register_operand" "=a") | |
| 1171 | (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) | |
| 1172 | (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))) | |
| 1173 | (clobber (match_scratch:DI 3 "=l")) | |
| 1174 | (clobber (match_scratch:DI 4 "=h"))] | |
| 1175 | "TARGET_64BIT" | |
| 1176 | "mult\\t%1,%2" | |
| 1177 | [(set_attr "type" "imul") | |
| 1178 | (set_attr "mode" "SI") | |
| 1179 | (set_attr "length" "1")]) | |
| 1180 | ||
| 903df3fe | 1181 | (define_insn "smulsi3_highpart" |
| 46299de9 | 1182 | [(set (match_operand:SI 0 "register_operand" "=h") |
| 903df3fe JW |
1183 | (truncate:SI |
| 1184 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) | |
| 1185 | (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))) | |
| 1186 | (const_int 32)))) | |
| 225b8835 ILT |
1187 | (clobber (match_scratch:SI 3 "=l")) |
| 1188 | (clobber (match_scratch:SI 4 "=a"))] | |
| 903df3fe | 1189 | "" |
| 46299de9 | 1190 | "mult\\t%1,%2" |
| 903df3fe JW |
1191 | [(set_attr "type" "imul") |
| 1192 | (set_attr "mode" "SI") | |
| 1193 | (set_attr "length" "1")]) | |
| 1194 | ||
| 225b8835 | 1195 | (define_expand "umulsidi3" |
| 46299de9 | 1196 | [(set (match_operand:DI 0 "register_operand" "=x") |
| 8ef30996 | 1197 | (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) |
| 46299de9 | 1198 | (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] |
| 225b8835 ILT |
1199 | "" |
| 1200 | " | |
| 1201 | { | |
| 1202 | if (TARGET_64BIT) | |
| 1203 | emit_insn (gen_umulsidi3_64bit (operands[0], operands[1], operands[2])); | |
| 1204 | else | |
| 1205 | emit_insn (gen_umulsidi3_internal (operands[0], operands[1], operands[2])); | |
| 1206 | DONE; | |
| 1207 | }") | |
| 1208 | ||
| 1209 | (define_insn "umulsidi3_internal" | |
| 1210 | [(set (match_operand:DI 0 "register_operand" "=x") | |
| 1211 | (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) | |
| 1212 | (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))) | |
| 1213 | (clobber (match_scratch:SI 3 "=a"))] | |
| bb621ad7 | 1214 | "!TARGET_64BIT" |
| 46299de9 | 1215 | "multu\\t%1,%2" |
| 8ef30996 MM |
1216 | [(set_attr "type" "imul") |
| 1217 | (set_attr "mode" "SI") | |
| 46299de9 | 1218 | (set_attr "length" "1")]) |
| 8ef30996 | 1219 | |
| 225b8835 ILT |
1220 | (define_insn "umulsidi3_64bit" |
| 1221 | [(set (match_operand:DI 0 "register_operand" "=a") | |
| 1222 | (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) | |
| 1223 | (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))) | |
| 1224 | (clobber (match_scratch:DI 3 "=l")) | |
| 1225 | (clobber (match_scratch:DI 4 "=h"))] | |
| 1226 | "TARGET_64BIT" | |
| 1227 | "multu\\t%1,%2" | |
| 1228 | [(set_attr "type" "imul") | |
| 1229 | (set_attr "mode" "SI") | |
| 1230 | (set_attr "length" "1")]) | |
| 1231 | ||
| 903df3fe | 1232 | (define_insn "umulsi3_highpart" |
| 46299de9 | 1233 | [(set (match_operand:SI 0 "register_operand" "=h") |
| 903df3fe JW |
1234 | (truncate:SI |
| 1235 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) | |
| 1236 | (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))) | |
| 1237 | (const_int 32)))) | |
| 225b8835 ILT |
1238 | (clobber (match_scratch:SI 3 "=l")) |
| 1239 | (clobber (match_scratch:SI 4 "=a"))] | |
| 903df3fe | 1240 | "" |
| 46299de9 | 1241 | "multu\\t%1,%2" |
| 903df3fe JW |
1242 | [(set_attr "type" "imul") |
| 1243 | (set_attr "mode" "SI") | |
| 1244 | (set_attr "length" "1")]) | |
| 48199e32 JW |
1245 | |
| 1246 | (define_insn "smuldi3_highpart" | |
| 46299de9 | 1247 | [(set (match_operand:DI 0 "register_operand" "=h") |
| 48199e32 JW |
1248 | (truncate:DI |
| 1249 | (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "d")) | |
| 1250 | (sign_extend:TI (match_operand:DI 2 "register_operand" "d"))) | |
| 1251 | (const_int 64)))) | |
| 225b8835 ILT |
1252 | (clobber (match_scratch:DI 3 "=l")) |
| 1253 | (clobber (match_scratch:DI 4 "=a"))] | |
| 48199e32 | 1254 | "TARGET_64BIT" |
| 46299de9 | 1255 | "dmult\\t%1,%2" |
| 48199e32 JW |
1256 | [(set_attr "type" "imul") |
| 1257 | (set_attr "mode" "DI") | |
| 1258 | (set_attr "length" "1")]) | |
| 1259 | ||
| 1260 | (define_insn "umuldi3_highpart" | |
| 46299de9 | 1261 | [(set (match_operand:DI 0 "register_operand" "=h") |
| 48199e32 JW |
1262 | (truncate:DI |
| 1263 | (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "d")) | |
| 1264 | (zero_extend:TI (match_operand:DI 2 "register_operand" "d"))) | |
| 1265 | (const_int 64)))) | |
| 225b8835 ILT |
1266 | (clobber (match_scratch:DI 3 "=l")) |
| 1267 | (clobber (match_scratch:DI 4 "=a"))] | |
| 48199e32 | 1268 | "TARGET_64BIT" |
| 46299de9 | 1269 | "dmultu\\t%1,%2" |
| 48199e32 JW |
1270 | [(set_attr "type" "imul") |
| 1271 | (set_attr "mode" "DI") | |
| 46299de9 | 1272 | (set_attr "length" "1")]) |
| 48199e32 | 1273 | |
| 46299de9 ILT |
1274 | ;; The R4650 supports a 32 bit multiply/ 64 bit accumulate |
| 1275 | ;; instruction. The HI/LO registers are used as a 64 bit accumulator. | |
| 1276 | ||
| 1277 | (define_insn "madsi" | |
| 1278 | [(set (match_operand:SI 0 "register_operand" "+l") | |
| 1279 | (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") | |
| 1280 | (match_operand:SI 2 "register_operand" "d")) | |
| 1281 | (match_dup 0))) | |
| 225b8835 ILT |
1282 | (clobber (match_scratch:SI 3 "=h")) |
| 1283 | (clobber (match_scratch:SI 4 "=a"))] | |
| 46299de9 ILT |
1284 | "TARGET_MAD" |
| 1285 | "mad\\t%1,%2" | |
| 1286 | [(set_attr "type" "imul") | |
| 1287 | (set_attr "mode" "SI") | |
| 1288 | (set_attr "length" "1")]) | |
| 1289 | ||
| 46299de9 ILT |
1290 | (define_insn "maddi" |
| 1291 | [(set (match_operand:DI 0 "register_operand" "+x") | |
| 1292 | (plus:DI (mult:DI (sign_extend:DI | |
| 1293 | (match_operand:SI 1 "register_operand" "d")) | |
| 1294 | (sign_extend:DI | |
| 1295 | (match_operand:SI 2 "register_operand" "d"))) | |
| 225b8835 ILT |
1296 | (match_dup 0))) |
| 1297 | (clobber (match_scratch:SI 3 "=a"))] | |
| 46299de9 ILT |
1298 | "TARGET_MAD && ! TARGET_64BIT" |
| 1299 | "mad\\t%1,%2" | |
| 1300 | [(set_attr "type" "imul") | |
| 1301 | (set_attr "mode" "SI") | |
| 1302 | (set_attr "length" "1")]) | |
| 1303 | ||
| 225b8835 ILT |
1304 | (define_insn "maddi_64bit" |
| 1305 | [(set (match_operand:DI 0 "register_operand" "+a") | |
| 1306 | (plus:DI (mult:DI (sign_extend:DI | |
| 1307 | (match_operand:SI 1 "register_operand" "d")) | |
| 1308 | (sign_extend:DI | |
| 1309 | (match_operand:SI 2 "register_operand" "d"))) | |
| 1310 | (match_dup 0))) | |
| 1311 | (clobber (match_scratch:DI 3 "=l")) | |
| 1312 | (clobber (match_scratch:DI 4 "=h"))] | |
| 1313 | "TARGET_MAD && TARGET_64BIT" | |
| 1314 | "mad\\t%1,%2" | |
| 1315 | [(set_attr "type" "imul") | |
| 1316 | (set_attr "mode" "SI") | |
| 1317 | (set_attr "length" "1")]) | |
| 1318 | ||
| 46299de9 ILT |
1319 | (define_insn "umaddi" |
| 1320 | [(set (match_operand:DI 0 "register_operand" "+x") | |
| 1321 | (plus:DI (mult:DI (zero_extend:DI | |
| 1322 | (match_operand:SI 1 "register_operand" "d")) | |
| 1323 | (zero_extend:DI | |
| 1324 | (match_operand:SI 2 "register_operand" "d"))) | |
| 225b8835 ILT |
1325 | (match_dup 0))) |
| 1326 | (clobber (match_scratch:SI 3 "=a"))] | |
| 46299de9 ILT |
1327 | "TARGET_MAD && ! TARGET_64BIT" |
| 1328 | "madu\\t%1,%2" | |
| 1329 | [(set_attr "type" "imul") | |
| 1330 | (set_attr "mode" "SI") | |
| 1331 | (set_attr "length" "1")]) | |
| e19ff60f | 1332 | |
| 225b8835 ILT |
1333 | (define_insn "umaddi_64bit" |
| 1334 | [(set (match_operand:DI 0 "register_operand" "+a") | |
| 1335 | (plus:DI (mult:DI (zero_extend:DI | |
| 1336 | (match_operand:SI 1 "register_operand" "d")) | |
| 1337 | (zero_extend:DI | |
| 1338 | (match_operand:SI 2 "register_operand" "d"))) | |
| 1339 | (match_dup 0))) | |
| 1340 | (clobber (match_scratch:DI 3 "=l")) | |
| 1341 | (clobber (match_scratch:DI 4 "=h"))] | |
| 1342 | "TARGET_MAD && TARGET_64BIT" | |
| 1343 | "madu\\t%1,%2" | |
| 1344 | [(set_attr "type" "imul") | |
| 1345 | (set_attr "mode" "SI") | |
| 1346 | (set_attr "length" "1")]) | |
| 1347 | ||
| e19ff60f JW |
1348 | ;; Floating point multiply accumulate instructions. |
| 1349 | ||
| 1350 | (define_insn "" | |
| 1351 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1352 | (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") | |
| 1353 | (match_operand:DF 2 "register_operand" "f")) | |
| 1354 | (match_operand:DF 3 "register_operand" "f")))] | |
| b8eb88d0 | 1355 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| e19ff60f JW |
1356 | "madd.d\\t%0,%3,%1,%2" |
| 1357 | [(set_attr "type" "fmadd") | |
| 1358 | (set_attr "mode" "DF") | |
| 1359 | (set_attr "length" "1")]) | |
| 1360 | ||
| 1361 | (define_insn "" | |
| 1362 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1363 | (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") | |
| 1364 | (match_operand:SF 2 "register_operand" "f")) | |
| 1365 | (match_operand:SF 3 "register_operand" "f")))] | |
| 1366 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 1367 | "madd.s\\t%0,%3,%1,%2" | |
| 1368 | [(set_attr "type" "fmadd") | |
| 1369 | (set_attr "mode" "SF") | |
| 1370 | (set_attr "length" "1")]) | |
| 1371 | ||
| 1372 | (define_insn "" | |
| 1373 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1374 | (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") | |
| 1375 | (match_operand:DF 2 "register_operand" "f")) | |
| 1376 | (match_operand:DF 3 "register_operand" "f")))] | |
| b8eb88d0 | 1377 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| e19ff60f JW |
1378 | "msub.d\\t%0,%3,%1,%2" |
| 1379 | [(set_attr "type" "fmadd") | |
| 1380 | (set_attr "mode" "DF") | |
| 1381 | (set_attr "length" "1")]) | |
| 1382 | ||
| 1383 | (define_insn "" | |
| 1384 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1385 | (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") | |
| 1386 | (match_operand:SF 2 "register_operand" "f")) | |
| 1387 | (match_operand:SF 3 "register_operand" "f")))] | |
| 1388 | ||
| 1389 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 1390 | "msub.s\\t%0,%3,%1,%2" | |
| 1391 | [(set_attr "type" "fmadd") | |
| 1392 | (set_attr "mode" "SF") | |
| 1393 | (set_attr "length" "1")]) | |
| 1394 | ||
| 1395 | (define_insn "" | |
| 1396 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1397 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") | |
| 1398 | (match_operand:DF 2 "register_operand" "f")) | |
| 1399 | (match_operand:DF 3 "register_operand" "f"))))] | |
| b8eb88d0 | 1400 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| e19ff60f JW |
1401 | "nmadd.d\\t%0,%3,%1,%2" |
| 1402 | [(set_attr "type" "fmadd") | |
| 1403 | (set_attr "mode" "DF") | |
| 1404 | (set_attr "length" "1")]) | |
| 1405 | ||
| 1406 | (define_insn "" | |
| 1407 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1408 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") | |
| 1409 | (match_operand:SF 2 "register_operand" "f")) | |
| 1410 | (match_operand:SF 3 "register_operand" "f"))))] | |
| 1411 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 1412 | "nmadd.s\\t%0,%3,%1,%2" | |
| 1413 | [(set_attr "type" "fmadd") | |
| 1414 | (set_attr "mode" "SF") | |
| 1415 | (set_attr "length" "1")]) | |
| 1416 | ||
| 1417 | (define_insn "" | |
| 1418 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1419 | (minus:DF (match_operand:DF 1 "register_operand" "f") | |
| 1420 | (mult:DF (match_operand:DF 2 "register_operand" "f") | |
| 1421 | (match_operand:DF 3 "register_operand" "f"))))] | |
| b8eb88d0 | 1422 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| e19ff60f JW |
1423 | "nmsub.d\\t%0,%1,%2,%3" |
| 1424 | [(set_attr "type" "fmadd") | |
| 1425 | (set_attr "mode" "DF") | |
| 1426 | (set_attr "length" "1")]) | |
| 1427 | ||
| 1428 | (define_insn "" | |
| 1429 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1430 | (minus:SF (match_operand:SF 1 "register_operand" "f") | |
| 1431 | (mult:SF (match_operand:SF 2 "register_operand" "f") | |
| 1432 | (match_operand:SF 3 "register_operand" "f"))))] | |
| 1433 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 1434 | "nmsub.s\\t%0,%1,%2,%3" | |
| 1435 | [(set_attr "type" "fmadd") | |
| 1436 | (set_attr "mode" "SF") | |
| 1437 | (set_attr "length" "1")]) | |
| 8ef30996 MM |
1438 | \f |
| 1439 | ;; | |
| 1440 | ;; .................... | |
| 1441 | ;; | |
| 1442 | ;; DIVISION and REMAINDER | |
| 1443 | ;; | |
| 1444 | ;; .................... | |
| 1445 | ;; | |
| 1446 | ||
| 1447 | (define_insn "divdf3" | |
| 1448 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1449 | (div:DF (match_operand:DF 1 "register_operand" "f") | |
| 1450 | (match_operand:DF 2 "register_operand" "f")))] | |
| 46299de9 | 1451 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
1452 | "div.d\\t%0,%1,%2" |
| 1453 | [(set_attr "type" "fdiv") | |
| 1454 | (set_attr "mode" "DF") | |
| 1455 | (set_attr "length" "1")]) | |
| 1456 | ||
| 1457 | (define_insn "divsf3" | |
| 1458 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1459 | (div:SF (match_operand:SF 1 "register_operand" "f") | |
| 1460 | (match_operand:SF 2 "register_operand" "f")))] | |
| 1461 | "TARGET_HARD_FLOAT" | |
| 1462 | "div.s\\t%0,%1,%2" | |
| 1463 | [(set_attr "type" "fdiv") | |
| 1464 | (set_attr "mode" "SF") | |
| 1465 | (set_attr "length" "1")]) | |
| 1466 | ||
| b8eb88d0 ILT |
1467 | (define_insn "" |
| 1468 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1469 | (div:DF (match_operand:DF 1 "const_float_1_operand" "") | |
| 1470 | (match_operand:DF 2 "register_operand" "f")))] | |
| 1471 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math" | |
| 1472 | "recip.d\\t%0,%2" | |
| 1473 | [(set_attr "type" "fdiv") | |
| 1474 | (set_attr "mode" "DF") | |
| 1475 | (set_attr "length" "1")]) | |
| 1476 | ||
| 1477 | (define_insn "" | |
| 1478 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1479 | (div:SF (match_operand:SF 1 "const_float_1_operand" "") | |
| 1480 | (match_operand:SF 2 "register_operand" "f")))] | |
| 1481 | "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math" | |
| 1482 | "recip.s\\t%0,%2" | |
| 1483 | [(set_attr "type" "fdiv") | |
| 1484 | (set_attr "mode" "SF") | |
| 1485 | (set_attr "length" "1")]) | |
| 1486 | ||
| 8ef30996 MM |
1487 | ;; If optimizing, prefer the divmod functions over separate div and |
| 1488 | ;; mod functions, since this will allow using one instruction for both | |
| 1489 | ;; the quotient and remainder. At present, the divmod is not moved out | |
| 1490 | ;; of loops if it is constant within the loop, so allow -mdebugc to | |
| 1491 | ;; use the old method of doing things. | |
| 1492 | ||
| 1493 | ;; 64 is the multiply/divide hi register | |
| 1494 | ;; 65 is the multiply/divide lo register | |
| 1495 | ||
| bb621ad7 JW |
1496 | ;; ??? We can't accept constants here, because the MIPS assembler will replace |
| 1497 | ;; a divide by power of 2 with a shift, and then the remainder is no longer | |
| 1498 | ;; available. | |
| 1499 | ||
| 8ef30996 | 1500 | (define_insn "divmodsi4" |
| 70252580 MM |
1501 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 1502 | (div:SI (match_operand:SI 1 "register_operand" "d") | |
| 1503 | (match_operand:SI 2 "register_operand" "d"))) | |
| 1504 | (set (match_operand:SI 3 "register_operand" "=d") | |
| 1505 | (mod:SI (match_dup 1) | |
| 1506 | (match_dup 2))) | |
| 46299de9 | 1507 | (clobber (match_scratch:SI 4 "=l")) |
| 225b8835 ILT |
1508 | (clobber (match_scratch:SI 5 "=h")) |
| 1509 | (clobber (match_scratch:SI 6 "=a"))] | |
| 34b650b3 | 1510 | "optimize" |
| 8ef30996 MM |
1511 | "* |
| 1512 | { | |
| 1513 | if (find_reg_note (insn, REG_UNUSED, operands[3])) | |
| 1514 | return \"div\\t%0,%1,%2\"; | |
| 1515 | ||
| 1516 | if (find_reg_note (insn, REG_UNUSED, operands[0])) | |
| 1517 | return \"rem\\t%3,%1,%2\"; | |
| 1518 | ||
| 1519 | return \"div\\t%0,%1,%2\;mfhi\\t%3\"; | |
| 1520 | }" | |
| 1521 | [(set_attr "type" "idiv") | |
| 1522 | (set_attr "mode" "SI") | |
| bb621ad7 JW |
1523 | (set_attr "length" "14")]) ;; various tests for dividing by 0 and such |
| 1524 | ||
| 1525 | (define_insn "divmoddi4" | |
| 1526 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 1527 | (div:DI (match_operand:DI 1 "register_operand" "d") | |
| 1528 | (match_operand:DI 2 "register_operand" "d"))) | |
| 1529 | (set (match_operand:DI 3 "register_operand" "=d") | |
| 1530 | (mod:DI (match_dup 1) | |
| 1531 | (match_dup 2))) | |
| 46299de9 | 1532 | (clobber (match_scratch:DI 4 "=l")) |
| 225b8835 ILT |
1533 | (clobber (match_scratch:DI 5 "=h")) |
| 1534 | (clobber (match_scratch:DI 6 "=a"))] | |
| bb621ad7 JW |
1535 | "TARGET_64BIT && optimize" |
| 1536 | "* | |
| 1537 | { | |
| 1538 | if (find_reg_note (insn, REG_UNUSED, operands[3])) | |
| 1539 | return \"ddiv\\t%0,%1,%2\"; | |
| 1540 | ||
| 1541 | if (find_reg_note (insn, REG_UNUSED, operands[0])) | |
| 1542 | return \"drem\\t%3,%1,%2\"; | |
| 1543 | ||
| 1544 | return \"ddiv\\t%0,%1,%2\;mfhi\\t%3\"; | |
| 1545 | }" | |
| 1546 | [(set_attr "type" "idiv") | |
| 1547 | (set_attr "mode" "DI") | |
| 1548 | (set_attr "length" "15")]) ;; various tests for dividing by 0 and such | |
| 8ef30996 MM |
1549 | |
| 1550 | (define_insn "udivmodsi4" | |
| 70252580 MM |
1551 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 1552 | (udiv:SI (match_operand:SI 1 "register_operand" "d") | |
| 1553 | (match_operand:SI 2 "register_operand" "d"))) | |
| 1554 | (set (match_operand:SI 3 "register_operand" "=d") | |
| 1555 | (umod:SI (match_dup 1) | |
| 1556 | (match_dup 2))) | |
| 46299de9 | 1557 | (clobber (match_scratch:SI 4 "=l")) |
| 225b8835 ILT |
1558 | (clobber (match_scratch:SI 5 "=h")) |
| 1559 | (clobber (match_scratch:SI 6 "=a"))] | |
| 34b650b3 | 1560 | "optimize" |
| 8ef30996 MM |
1561 | "* |
| 1562 | { | |
| 1563 | if (find_reg_note (insn, REG_UNUSED, operands[3])) | |
| 1564 | return \"divu\\t%0,%1,%2\"; | |
| 1565 | ||
| 1566 | if (find_reg_note (insn, REG_UNUSED, operands[0])) | |
| 1567 | return \"remu\\t%3,%1,%2\"; | |
| 1568 | ||
| 1569 | return \"divu\\t%0,%1,%2\;mfhi\\t%3\"; | |
| 1570 | }" | |
| 1571 | [(set_attr "type" "idiv") | |
| 1572 | (set_attr "mode" "SI") | |
| bb621ad7 JW |
1573 | (set_attr "length" "8")]) ;; various tests for dividing by 0 and such |
| 1574 | ||
| 1575 | (define_insn "udivmoddi4" | |
| 1576 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 1577 | (udiv:DI (match_operand:DI 1 "register_operand" "d") | |
| 1578 | (match_operand:DI 2 "register_operand" "d"))) | |
| 1579 | (set (match_operand:DI 3 "register_operand" "=d") | |
| 1580 | (umod:DI (match_dup 1) | |
| 1581 | (match_dup 2))) | |
| 46299de9 | 1582 | (clobber (match_scratch:DI 4 "=l")) |
| 225b8835 ILT |
1583 | (clobber (match_scratch:DI 5 "=h")) |
| 1584 | (clobber (match_scratch:DI 6 "=a"))] | |
| bb621ad7 JW |
1585 | "TARGET_64BIT && optimize" |
| 1586 | "* | |
| 1587 | { | |
| 1588 | if (find_reg_note (insn, REG_UNUSED, operands[3])) | |
| 1589 | return \"ddivu\\t%0,%1,%2\"; | |
| 1590 | ||
| 1591 | if (find_reg_note (insn, REG_UNUSED, operands[0])) | |
| 1592 | return \"dremu\\t%3,%1,%2\"; | |
| 1593 | ||
| 1594 | return \"ddivu\\t%0,%1,%2\;mfhi\\t%3\"; | |
| 1595 | }" | |
| 1596 | [(set_attr "type" "idiv") | |
| 1597 | (set_attr "mode" "DI") | |
| 1598 | (set_attr "length" "8")]) ;; various tests for dividing by 0 and such | |
| 8ef30996 MM |
1599 | |
| 1600 | (define_insn "divsi3" | |
| 1601 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1602 | (div:SI (match_operand:SI 1 "register_operand" "d") | |
| bb621ad7 | 1603 | (match_operand:SI 2 "nonmemory_operand" "di"))) |
| 46299de9 | 1604 | (clobber (match_scratch:SI 3 "=l")) |
| 225b8835 ILT |
1605 | (clobber (match_scratch:SI 4 "=h")) |
| 1606 | (clobber (match_scratch:SI 6 "=a"))] | |
| 34b650b3 | 1607 | "!optimize" |
| 8ef30996 MM |
1608 | "div\\t%0,%1,%2" |
| 1609 | [(set_attr "type" "idiv") | |
| 1610 | (set_attr "mode" "SI") | |
| 1611 | (set_attr "length" "13")]) ;; various tests for dividing by 0 and such | |
| 1612 | ||
| bb621ad7 JW |
1613 | (define_insn "divdi3" |
| 1614 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 1615 | (div:DI (match_operand:DI 1 "register_operand" "d") | |
| 1616 | (match_operand:DI 2 "nonmemory_operand" "di"))) | |
| 46299de9 | 1617 | (clobber (match_scratch:DI 3 "=l")) |
| 225b8835 ILT |
1618 | (clobber (match_scratch:DI 4 "=h")) |
| 1619 | (clobber (match_scratch:DI 6 "=a"))] | |
| bb621ad7 JW |
1620 | "TARGET_64BIT && !optimize" |
| 1621 | "ddiv\\t%0,%1,%2" | |
| 1622 | [(set_attr "type" "idiv") | |
| 1623 | (set_attr "mode" "DI") | |
| 1624 | (set_attr "length" "14")]) ;; various tests for dividing by 0 and such | |
| 1625 | ||
| 8ef30996 MM |
1626 | (define_insn "modsi3" |
| 1627 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1628 | (mod:SI (match_operand:SI 1 "register_operand" "d") | |
| bb621ad7 | 1629 | (match_operand:SI 2 "nonmemory_operand" "di"))) |
| 46299de9 | 1630 | (clobber (match_scratch:SI 3 "=l")) |
| 225b8835 ILT |
1631 | (clobber (match_scratch:SI 4 "=h")) |
| 1632 | (clobber (match_scratch:SI 6 "=a"))] | |
| 34b650b3 | 1633 | "!optimize" |
| 8ef30996 MM |
1634 | "rem\\t%0,%1,%2" |
| 1635 | [(set_attr "type" "idiv") | |
| 1636 | (set_attr "mode" "SI") | |
| bb621ad7 JW |
1637 | (set_attr "length" "13")]) ;; various tests for dividing by 0 and such |
| 1638 | ||
| 1639 | (define_insn "moddi3" | |
| 1640 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 1641 | (mod:DI (match_operand:DI 1 "register_operand" "d") | |
| 1642 | (match_operand:DI 2 "nonmemory_operand" "di"))) | |
| 46299de9 | 1643 | (clobber (match_scratch:DI 3 "=l")) |
| 225b8835 ILT |
1644 | (clobber (match_scratch:DI 4 "=h")) |
| 1645 | (clobber (match_scratch:DI 6 "=a"))] | |
| bb621ad7 JW |
1646 | "TARGET_64BIT && !optimize" |
| 1647 | "drem\\t%0,%1,%2" | |
| 1648 | [(set_attr "type" "idiv") | |
| 1649 | (set_attr "mode" "DI") | |
| 8ef30996 MM |
1650 | (set_attr "length" "14")]) ;; various tests for dividing by 0 and such |
| 1651 | ||
| 1652 | (define_insn "udivsi3" | |
| 1653 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1654 | (udiv:SI (match_operand:SI 1 "register_operand" "d") | |
| bb621ad7 | 1655 | (match_operand:SI 2 "nonmemory_operand" "di"))) |
| 46299de9 | 1656 | (clobber (match_scratch:SI 3 "=l")) |
| 225b8835 ILT |
1657 | (clobber (match_scratch:SI 4 "=h")) |
| 1658 | (clobber (match_scratch:SI 6 "=a"))] | |
| 34b650b3 | 1659 | "!optimize" |
| 8ef30996 MM |
1660 | "divu\\t%0,%1,%2" |
| 1661 | [(set_attr "type" "idiv") | |
| 1662 | (set_attr "mode" "SI") | |
| bb621ad7 JW |
1663 | (set_attr "length" "7")]) ;; various tests for dividing by 0 and such |
| 1664 | ||
| 1665 | (define_insn "udivdi3" | |
| 1666 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 1667 | (udiv:DI (match_operand:DI 1 "register_operand" "d") | |
| 1668 | (match_operand:DI 2 "nonmemory_operand" "di"))) | |
| 46299de9 | 1669 | (clobber (match_scratch:DI 3 "=l")) |
| 225b8835 ILT |
1670 | (clobber (match_scratch:DI 4 "=h")) |
| 1671 | (clobber (match_scratch:DI 6 "=a"))] | |
| bb621ad7 JW |
1672 | "TARGET_64BIT && !optimize" |
| 1673 | "ddivu\\t%0,%1,%2" | |
| 1674 | [(set_attr "type" "idiv") | |
| 1675 | (set_attr "mode" "DI") | |
| 1676 | (set_attr "length" "7")]) ;; various tests for dividing by 0 and such | |
| 8ef30996 MM |
1677 | |
| 1678 | (define_insn "umodsi3" | |
| 1679 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1680 | (umod:SI (match_operand:SI 1 "register_operand" "d") | |
| bb621ad7 | 1681 | (match_operand:SI 2 "nonmemory_operand" "di"))) |
| 46299de9 | 1682 | (clobber (match_scratch:SI 3 "=l")) |
| 225b8835 ILT |
1683 | (clobber (match_scratch:SI 4 "=h")) |
| 1684 | (clobber (match_scratch:SI 6 "=a"))] | |
| 34b650b3 | 1685 | "!optimize" |
| 8ef30996 MM |
1686 | "remu\\t%0,%1,%2" |
| 1687 | [(set_attr "type" "idiv") | |
| 1688 | (set_attr "mode" "SI") | |
| bb621ad7 JW |
1689 | (set_attr "length" "7")]) ;; various tests for dividing by 0 and such |
| 1690 | ||
| 1691 | (define_insn "umoddi3" | |
| 1692 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 1693 | (umod:DI (match_operand:DI 1 "register_operand" "d") | |
| 1694 | (match_operand:DI 2 "nonmemory_operand" "di"))) | |
| 46299de9 | 1695 | (clobber (match_scratch:DI 3 "=l")) |
| 225b8835 ILT |
1696 | (clobber (match_scratch:DI 4 "=h")) |
| 1697 | (clobber (match_scratch:DI 6 "=a"))] | |
| bb621ad7 JW |
1698 | "TARGET_64BIT && !optimize" |
| 1699 | "dremu\\t%0,%1,%2" | |
| 1700 | [(set_attr "type" "idiv") | |
| 1701 | (set_attr "mode" "DI") | |
| 1702 | (set_attr "length" "7")]) ;; various tests for dividing by 0 and such | |
| 8ef30996 MM |
1703 | |
| 1704 | \f | |
| 1705 | ;; | |
| 1706 | ;; .................... | |
| 1707 | ;; | |
| 1708 | ;; SQUARE ROOT | |
| 1709 | ;; | |
| 1710 | ;; .................... | |
| 1711 | ||
| 1712 | (define_insn "sqrtdf2" | |
| 1713 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1714 | (sqrt:DF (match_operand:DF 1 "register_operand" "f")))] | |
| 46299de9 | 1715 | "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT" |
| 8ef30996 | 1716 | "sqrt.d\\t%0,%1" |
| bb621ad7 | 1717 | [(set_attr "type" "fsqrt") |
| 8ef30996 MM |
1718 | (set_attr "mode" "DF") |
| 1719 | (set_attr "length" "1")]) | |
| 1720 | ||
| 1721 | (define_insn "sqrtsf2" | |
| 1722 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1723 | (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] | |
| 1724 | "TARGET_HARD_FLOAT && HAVE_SQRT_P()" | |
| 1725 | "sqrt.s\\t%0,%1" | |
| bb621ad7 | 1726 | [(set_attr "type" "fsqrt") |
| 8ef30996 MM |
1727 | (set_attr "mode" "SF") |
| 1728 | (set_attr "length" "1")]) | |
| 1729 | ||
| b8eb88d0 ILT |
1730 | (define_insn "" |
| 1731 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1732 | (div:DF (match_operand:DF 1 "const_float_1_operand" "") | |
| 1733 | (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))] | |
| 1734 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math" | |
| 1735 | "rsqrt.d\\t%0,%2" | |
| 1736 | [(set_attr "type" "fsqrt") | |
| 1737 | (set_attr "mode" "DF") | |
| 1738 | (set_attr "length" "1")]) | |
| 1739 | ||
| 1740 | (define_insn "" | |
| 1741 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1742 | (div:SF (match_operand:SF 1 "const_float_1_operand" "") | |
| 1743 | (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))] | |
| 1744 | "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math" | |
| 1745 | "rsqrt.s\\t%0,%2" | |
| 1746 | [(set_attr "type" "fsqrt") | |
| 1747 | (set_attr "mode" "SF") | |
| 1748 | (set_attr "length" "1")]) | |
| 1749 | ||
| 8ef30996 MM |
1750 | \f |
| 1751 | ;; | |
| 1752 | ;; .................... | |
| 1753 | ;; | |
| 1754 | ;; ABSOLUTE VALUE | |
| 1755 | ;; | |
| 1756 | ;; .................... | |
| 1757 | ||
| 1758 | ;; Do not use the integer abs macro instruction, since that signals an | |
| 1759 | ;; exception on -2147483648 (sigh). | |
| 1760 | ||
| 1761 | (define_insn "abssi2" | |
| 1762 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1763 | (abs:SI (match_operand:SI 1 "register_operand" "d")))] | |
| 1764 | "" | |
| 1765 | "* | |
| 1766 | { | |
| 1767 | dslots_jump_total++; | |
| 1768 | dslots_jump_filled++; | |
| 1769 | operands[2] = const0_rtx; | |
| 1770 | ||
| bb621ad7 JW |
1771 | if (REGNO (operands[0]) == REGNO (operands[1])) |
| 1772 | { | |
| 1773 | if (mips_isa >= 2) | |
| 1774 | return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n1:%)\"; | |
| 1775 | else | |
| 1776 | return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n1:\"; | |
| 1777 | } | |
| 1778 | else | |
| 1779 | return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n1:%)\"; | |
| 8ef30996 MM |
1780 | }" |
| 1781 | [(set_attr "type" "multi") | |
| 1782 | (set_attr "mode" "SI") | |
| 1783 | (set_attr "length" "3")]) | |
| 1784 | ||
| bb621ad7 JW |
1785 | (define_insn "absdi2" |
| 1786 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 1787 | (abs:DI (match_operand:DI 1 "register_operand" "d")))] | |
| 1788 | "TARGET_64BIT" | |
| 1789 | "* | |
| 1790 | { | |
| 1791 | dslots_jump_total++; | |
| 1792 | dslots_jump_filled++; | |
| 1793 | operands[2] = const0_rtx; | |
| 1794 | ||
| 1795 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
| 1796 | return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\"; | |
| 1797 | else | |
| 1798 | return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\"; | |
| 1799 | }" | |
| 1800 | [(set_attr "type" "multi") | |
| 1801 | (set_attr "mode" "DI") | |
| 1802 | (set_attr "length" "3")]) | |
| 1803 | ||
| 8ef30996 MM |
1804 | (define_insn "absdf2" |
| 1805 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1806 | (abs:DF (match_operand:DF 1 "register_operand" "f")))] | |
| 46299de9 | 1807 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
1808 | "abs.d\\t%0,%1" |
| 1809 | [(set_attr "type" "fabs") | |
| 1810 | (set_attr "mode" "DF") | |
| 1811 | (set_attr "length" "1")]) | |
| 1812 | ||
| 1813 | (define_insn "abssf2" | |
| 1814 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1815 | (abs:SF (match_operand:SF 1 "register_operand" "f")))] | |
| 1816 | "TARGET_HARD_FLOAT" | |
| 1817 | "abs.s\\t%0,%1" | |
| 1818 | [(set_attr "type" "fabs") | |
| 1819 | (set_attr "mode" "SF") | |
| 1820 | (set_attr "length" "1")]) | |
| 1821 | ||
| 1822 | \f | |
| 1823 | ;; | |
| 1824 | ;; .................... | |
| 1825 | ;; | |
| 1826 | ;; FIND FIRST BIT INSTRUCTION | |
| 1827 | ;; | |
| 1828 | ;; .................... | |
| 1829 | ;; | |
| 1830 | ||
| 1831 | (define_insn "ffssi2" | |
| 1832 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
| 1833 | (ffs:SI (match_operand:SI 1 "register_operand" "d"))) | |
| 7d87c851 MM |
1834 | (clobber (match_scratch:SI 2 "=&d")) |
| 1835 | (clobber (match_scratch:SI 3 "=&d"))] | |
| 8ef30996 MM |
1836 | "" |
| 1837 | "* | |
| 1838 | { | |
| 1839 | dslots_jump_total += 2; | |
| 1840 | dslots_jump_filled += 2; | |
| 1841 | operands[4] = const0_rtx; | |
| 1842 | ||
| 1843 | if (optimize && find_reg_note (insn, REG_DEAD, operands[1])) | |
| 1844 | return \"%(\\ | |
| 1845 | move\\t%0,%z4\\n\\ | |
| 1846 | \\tbeq\\t%1,%z4,2f\\n\\ | |
| 1847 | 1:\\tand\\t%2,%1,0x0001\\n\\ | |
| 1848 | \\taddu\\t%0,%0,1\\n\\ | |
| 1849 | \\tbeq\\t%2,%z4,1b\\n\\ | |
| 1850 | \\tsrl\\t%1,%1,1\\n\\ | |
| 1851 | 2:%)\"; | |
| 1852 | ||
| 1853 | return \"%(\\ | |
| 1854 | move\\t%0,%z4\\n\\ | |
| 1855 | \\tmove\\t%3,%1\\n\\ | |
| 1856 | \\tbeq\\t%3,%z4,2f\\n\\ | |
| 1857 | 1:\\tand\\t%2,%3,0x0001\\n\\ | |
| 1858 | \\taddu\\t%0,%0,1\\n\\ | |
| 1859 | \\tbeq\\t%2,%z4,1b\\n\\ | |
| 1860 | \\tsrl\\t%3,%3,1\\n\\ | |
| 1861 | 2:%)\"; | |
| 1862 | }" | |
| 1863 | [(set_attr "type" "multi") | |
| 1864 | (set_attr "mode" "SI") | |
| 1865 | (set_attr "length" "6")]) | |
| 1866 | ||
| bb621ad7 JW |
1867 | (define_insn "ffsdi2" |
| 1868 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
| 1869 | (ffs:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 1870 | (clobber (match_scratch:DI 2 "=&d")) | |
| 1871 | (clobber (match_scratch:DI 3 "=&d"))] | |
| 1872 | "TARGET_64BIT" | |
| 1873 | "* | |
| 1874 | { | |
| 1875 | dslots_jump_total += 2; | |
| 1876 | dslots_jump_filled += 2; | |
| 1877 | operands[4] = const0_rtx; | |
| 1878 | ||
| 1879 | if (optimize && find_reg_note (insn, REG_DEAD, operands[1])) | |
| 1880 | return \"%(\\ | |
| 1881 | move\\t%0,%z4\\n\\ | |
| 1882 | \\tbeq\\t%1,%z4,2f\\n\\ | |
| 1883 | 1:\\tand\\t%2,%1,0x0001\\n\\ | |
| 1884 | \\tdaddu\\t%0,%0,1\\n\\ | |
| 1885 | \\tbeq\\t%2,%z4,1b\\n\\ | |
| 1886 | \\tdsrl\\t%1,%1,1\\n\\ | |
| 1887 | 2:%)\"; | |
| 1888 | ||
| 1889 | return \"%(\\ | |
| 1890 | move\\t%0,%z4\\n\\ | |
| 1891 | \\tmove\\t%3,%1\\n\\ | |
| 1892 | \\tbeq\\t%3,%z4,2f\\n\\ | |
| 1893 | 1:\\tand\\t%2,%3,0x0001\\n\\ | |
| 1894 | \\tdaddu\\t%0,%0,1\\n\\ | |
| 1895 | \\tbeq\\t%2,%z4,1b\\n\\ | |
| 1896 | \\tdsrl\\t%3,%3,1\\n\\ | |
| 1897 | 2:%)\"; | |
| 1898 | }" | |
| 1899 | [(set_attr "type" "multi") | |
| 1900 | (set_attr "mode" "DI") | |
| 1901 | (set_attr "length" "6")]) | |
| 1902 | ||
| 8ef30996 MM |
1903 | \f |
| 1904 | ;; | |
| 1905 | ;; .................... | |
| 1906 | ;; | |
| 1907 | ;; NEGATION and ONE'S COMPLEMENT | |
| 1908 | ;; | |
| 1909 | ;; .................... | |
| 1910 | ||
| 1911 | (define_insn "negsi2" | |
| 1912 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1913 | (neg:SI (match_operand:SI 1 "register_operand" "d")))] | |
| 1914 | "" | |
| 1915 | "* | |
| 1916 | { | |
| 1917 | operands[2] = const0_rtx; | |
| 1918 | return \"subu\\t%0,%z2,%1\"; | |
| 1919 | }" | |
| 1920 | [(set_attr "type" "arith") | |
| 1921 | (set_attr "mode" "SI") | |
| 1922 | (set_attr "length" "1")]) | |
| 1923 | ||
| e7d7b3dc | 1924 | (define_expand "negdi2" |
| 8ef30996 MM |
1925 | [(parallel [(set (match_operand:DI 0 "register_operand" "=d") |
| 1926 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 1927 | (clobber (match_dup 2))])] | |
| bb621ad7 JW |
1928 | "TARGET_64BIT || !TARGET_DEBUG_G_MODE" |
| 1929 | " | |
| 1930 | { | |
| 1931 | if (TARGET_64BIT) | |
| 1932 | { | |
| 1933 | emit_insn (gen_negdi2_internal_2 (operands[0], operands[1])); | |
| 1934 | DONE; | |
| 1935 | } | |
| 1936 | ||
| 1937 | operands[2] = gen_reg_rtx (SImode); | |
| 1938 | }") | |
| 8ef30996 | 1939 | |
| e7d7b3dc | 1940 | (define_insn "negdi2_internal" |
| 8ef30996 MM |
1941 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 1942 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 1943 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| bb621ad7 | 1944 | "! TARGET_64BIT && !TARGET_DEBUG_G_MODE" |
| 8ef30996 MM |
1945 | "* |
| 1946 | { | |
| 1947 | operands[3] = const0_rtx; | |
| 1948 | return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\"; | |
| 1949 | }" | |
| 1950 | [(set_attr "type" "darith") | |
| 1951 | (set_attr "mode" "DI") | |
| 1952 | (set_attr "length" "4")]) | |
| 1953 | ||
| bb621ad7 JW |
1954 | (define_insn "negdi2_internal_2" |
| 1955 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 1956 | (neg:DI (match_operand:DI 1 "register_operand" "d")))] | |
| 1957 | "TARGET_64BIT" | |
| 1958 | "* | |
| 1959 | { | |
| 1960 | operands[2] = const0_rtx; | |
| 1961 | return \"dsubu\\t%0,%z2,%1\"; | |
| 1962 | }" | |
| 1963 | [(set_attr "type" "arith") | |
| 1964 | (set_attr "mode" "DI") | |
| 1965 | (set_attr "length" "1")]) | |
| 1966 | ||
| 8ef30996 MM |
1967 | (define_insn "negdf2" |
| 1968 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 1969 | (neg:DF (match_operand:DF 1 "register_operand" "f")))] | |
| 46299de9 | 1970 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
1971 | "neg.d\\t%0,%1" |
| 1972 | [(set_attr "type" "fneg") | |
| 1973 | (set_attr "mode" "DF") | |
| 1974 | (set_attr "length" "1")]) | |
| 1975 | ||
| 1976 | (define_insn "negsf2" | |
| 1977 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 1978 | (neg:SF (match_operand:SF 1 "register_operand" "f")))] | |
| 1979 | "TARGET_HARD_FLOAT" | |
| 1980 | "neg.s\\t%0,%1" | |
| 1981 | [(set_attr "type" "fneg") | |
| 1982 | (set_attr "mode" "SF") | |
| 1983 | (set_attr "length" "1")]) | |
| 1984 | ||
| 1985 | (define_insn "one_cmplsi2" | |
| 1986 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1987 | (not:SI (match_operand:SI 1 "register_operand" "d")))] | |
| 1988 | "" | |
| 1989 | "* | |
| 1990 | { | |
| 1991 | operands[2] = const0_rtx; | |
| 1992 | return \"nor\\t%0,%z2,%1\"; | |
| 1993 | }" | |
| 1994 | [(set_attr "type" "arith") | |
| 1995 | (set_attr "mode" "SI") | |
| 1996 | (set_attr "length" "1")]) | |
| 1997 | ||
| 1998 | (define_insn "one_cmpldi2" | |
| 1999 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| bb621ad7 | 2000 | (not:DI (match_operand:DI 1 "register_operand" "d")))] |
| 8ef30996 MM |
2001 | "" |
| 2002 | "* | |
| 2003 | { | |
| 2004 | operands[2] = const0_rtx; | |
| bb621ad7 JW |
2005 | if (TARGET_64BIT) |
| 2006 | return \"nor\\t%0,%z2,%1\"; | |
| 8ef30996 MM |
2007 | return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\"; |
| 2008 | }" | |
| 2009 | [(set_attr "type" "darith") | |
| 2010 | (set_attr "mode" "DI") | |
| bb621ad7 JW |
2011 | (set (attr "length") |
| 2012 | (if_then_else (ge (symbol_ref "mips_isa") (const_int 3)) | |
| 2013 | (const_int 1) | |
| 2014 | (const_int 2)))]) | |
| 8ef30996 MM |
2015 | |
| 2016 | (define_split | |
| 2017 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2018 | (not:DI (match_operand:DI 1 "register_operand" "")))] | |
| bb621ad7 | 2019 | "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
2020 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 2021 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" | |
| 2022 | ||
| 2023 | [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) | |
| 2024 | (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))] | |
| 2025 | "") | |
| 2026 | ||
| 2027 | ;; Simple hack to recognize the "nor" instruction on the MIPS | |
| 2028 | ;; This must appear before the normal or patterns, so that the | |
| 2029 | ;; combiner will correctly fold things. | |
| 2030 | ||
| 2031 | (define_insn "norsi3" | |
| 2032 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2033 | (not:SI (ior:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 2034 | (match_operand:SI 2 "reg_or_0_operand" "dJ"))))] | |
| 2035 | "" | |
| 2036 | "nor\\t%0,%z1,%z2" | |
| 2037 | [(set_attr "type" "arith") | |
| 2038 | (set_attr "mode" "SI") | |
| 2039 | (set_attr "length" "1")]) | |
| 2040 | ||
| 2041 | (define_insn "nordi3" | |
| 2042 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2043 | (not:DI (ior:DI (match_operand:DI 1 "register_operand" "d") | |
| 2044 | (match_operand:DI 2 "register_operand" "d"))))] | |
| 2045 | "" | |
| bb621ad7 JW |
2046 | "* |
| 2047 | { | |
| 2048 | if (TARGET_64BIT) | |
| 2049 | return \"nor\\t%0,%z1,%z2\"; | |
| 2050 | return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\"; | |
| 2051 | }" | |
| 8ef30996 MM |
2052 | [(set_attr "type" "darith") |
| 2053 | (set_attr "mode" "DI") | |
| bb621ad7 JW |
2054 | (set (attr "length") |
| 2055 | (if_then_else (ge (symbol_ref "mips_isa") (const_int 3)) | |
| 2056 | (const_int 1) | |
| 2057 | (const_int 2)))]) | |
| 8ef30996 MM |
2058 | |
| 2059 | (define_split | |
| 2060 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2061 | (not:DI (ior:DI (match_operand:DI 1 "register_operand" "") | |
| 2062 | (match_operand:DI 2 "register_operand" ""))))] | |
| bb621ad7 | 2063 | "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
2064 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 2065 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 2066 | && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" | |
| 2067 | ||
| 2068 | [(set (subreg:SI (match_dup 0) 0) (not:SI (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))) | |
| 2069 | (set (subreg:SI (match_dup 0) 1) (not:SI (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1))))] | |
| 2070 | "") | |
| 2071 | ||
| 2072 | \f | |
| 2073 | ;; | |
| 2074 | ;; .................... | |
| 2075 | ;; | |
| 2076 | ;; LOGICAL | |
| 2077 | ;; | |
| 2078 | ;; .................... | |
| 2079 | ;; | |
| 2080 | ||
| 3e89ed5f | 2081 | (define_insn "andsi3" |
| 65437fe8 | 2082 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| e2f2127c MM |
2083 | (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") |
| 2084 | (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 65437fe8 MM |
2085 | "" |
| 2086 | "@ | |
| 2087 | and\\t%0,%1,%2 | |
| 2088 | andi\\t%0,%1,%x2" | |
| 2089 | [(set_attr "type" "arith") | |
| 2090 | (set_attr "mode" "SI") | |
| 2091 | (set_attr "length" "1")]) | |
| 2092 | ||
| 8ef30996 MM |
2093 | (define_insn "anddi3" |
| 2094 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2095 | (and:DI (match_operand:DI 1 "register_operand" "d") | |
| 2096 | (match_operand:DI 2 "register_operand" "d")))] | |
| bb621ad7 JW |
2097 | "TARGET_64BIT || !TARGET_DEBUG_G_MODE" |
| 2098 | "* | |
| 2099 | { | |
| 2100 | if (TARGET_64BIT) | |
| 2101 | return \"and\\t%0,%1,%2\"; | |
| 2102 | return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\"; | |
| 2103 | }" | |
| 8ef30996 MM |
2104 | [(set_attr "type" "darith") |
| 2105 | (set_attr "mode" "DI") | |
| bb621ad7 JW |
2106 | (set (attr "length") |
| 2107 | (if_then_else (ge (symbol_ref "mips_isa") (const_int 3)) | |
| 2108 | (const_int 1) | |
| 2109 | (const_int 2)))]) | |
| 8ef30996 MM |
2110 | |
| 2111 | (define_split | |
| 2112 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2113 | (and:DI (match_operand:DI 1 "register_operand" "") | |
| 2114 | (match_operand:DI 2 "register_operand" "")))] | |
| bb621ad7 | 2115 | "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
2116 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 2117 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 2118 | && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" | |
| 2119 | ||
| 2120 | [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) | |
| 2121 | (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))] | |
| 2122 | "") | |
| 2123 | ||
| bb621ad7 JW |
2124 | (define_insn "anddi3_internal1" |
| 2125 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 2126 | (and:DI (match_operand:DI 1 "register_operand" "%d,d") | |
| 2127 | (match_operand:DI 2 "uns_arith_operand" "d,K")))] | |
| 2128 | "TARGET_64BIT" | |
| 2129 | "@ | |
| 2130 | and\\t%0,%1,%2 | |
| 2131 | andi\\t%0,%1,%x2" | |
| 2132 | [(set_attr "type" "arith") | |
| 2133 | (set_attr "mode" "DI") | |
| 2134 | (set_attr "length" "1")]) | |
| 2135 | ||
| 3e89ed5f | 2136 | (define_insn "iorsi3" |
| 65437fe8 | 2137 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| e2f2127c MM |
2138 | (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") |
| 2139 | (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 65437fe8 MM |
2140 | "" |
| 2141 | "@ | |
| 2142 | or\\t%0,%1,%2 | |
| 2143 | ori\\t%0,%1,%x2" | |
| 2144 | [(set_attr "type" "arith") | |
| 2145 | (set_attr "mode" "SI") | |
| 2146 | (set_attr "length" "1")]) | |
| 2147 | ||
| bb621ad7 JW |
2148 | ;;; ??? There is no iordi3 pattern which accepts 'K' constants when |
| 2149 | ;;; TARGET_64BIT | |
| 2150 | ||
| 8ef30996 MM |
2151 | (define_insn "iordi3" |
| 2152 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2153 | (ior:DI (match_operand:DI 1 "register_operand" "d") | |
| 2154 | (match_operand:DI 2 "register_operand" "d")))] | |
| bb621ad7 JW |
2155 | "TARGET_64BIT || !TARGET_DEBUG_G_MODE" |
| 2156 | "* | |
| 2157 | { | |
| 2158 | if (TARGET_64BIT) | |
| 2159 | return \"or\\t%0,%1,%2\"; | |
| 2160 | return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\"; | |
| 2161 | }" | |
| 8ef30996 MM |
2162 | [(set_attr "type" "darith") |
| 2163 | (set_attr "mode" "DI") | |
| bb621ad7 JW |
2164 | (set (attr "length") |
| 2165 | (if_then_else (ge (symbol_ref "mips_isa") (const_int 3)) | |
| 2166 | (const_int 1) | |
| 2167 | (const_int 2)))]) | |
| 8ef30996 MM |
2168 | |
| 2169 | (define_split | |
| 2170 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2171 | (ior:DI (match_operand:DI 1 "register_operand" "") | |
| 2172 | (match_operand:DI 2 "register_operand" "")))] | |
| bb621ad7 | 2173 | "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
2174 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 2175 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 2176 | && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" | |
| 2177 | ||
| 2178 | [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) | |
| 2179 | (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))] | |
| 2180 | "") | |
| 2181 | ||
| 3e89ed5f | 2182 | (define_insn "xorsi3" |
| 65437fe8 | 2183 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| e2f2127c MM |
2184 | (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") |
| 2185 | (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 65437fe8 MM |
2186 | "" |
| 2187 | "@ | |
| 2188 | xor\\t%0,%1,%2 | |
| 2189 | xori\\t%0,%1,%x2" | |
| 2190 | [(set_attr "type" "arith") | |
| 2191 | (set_attr "mode" "SI") | |
| 2192 | (set_attr "length" "1")]) | |
| 2193 | ||
| bb621ad7 JW |
2194 | ;; ??? If delete the 32-bit long long patterns, then could merge this with |
| 2195 | ;; the following xordi3_internal pattern. | |
| 8ef30996 MM |
2196 | (define_insn "xordi3" |
| 2197 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2198 | (xor:DI (match_operand:DI 1 "register_operand" "d") | |
| 2199 | (match_operand:DI 2 "register_operand" "d")))] | |
| bb621ad7 JW |
2200 | "TARGET_64BIT || !TARGET_DEBUG_G_MODE" |
| 2201 | "* | |
| 2202 | { | |
| 2203 | if (TARGET_64BIT) | |
| 2204 | return \"xor\\t%0,%1,%2\"; | |
| 2205 | return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\"; | |
| 2206 | }" | |
| 2207 | [(set_attr "type" "darith") | |
| 8ef30996 | 2208 | (set_attr "mode" "DI") |
| bb621ad7 JW |
2209 | (set (attr "length") |
| 2210 | (if_then_else (ge (symbol_ref "mips_isa") (const_int 3)) | |
| 2211 | (const_int 1) | |
| 2212 | (const_int 2)))]) | |
| 8ef30996 MM |
2213 | |
| 2214 | (define_split | |
| 2215 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2216 | (xor:DI (match_operand:DI 1 "register_operand" "") | |
| 2217 | (match_operand:DI 2 "register_operand" "")))] | |
| bb621ad7 | 2218 | "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
2219 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 2220 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | |
| 2221 | && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" | |
| 2222 | ||
| 2223 | [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) | |
| 2224 | (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))] | |
| 2225 | "") | |
| 2226 | ||
| bb621ad7 JW |
2227 | (define_insn "xordi3_immed" |
| 2228 | [(set (match_operand:DI 0 "register_operand" "d") | |
| 2229 | (xor:DI (match_operand:DI 1 "register_operand" "d") | |
| 2230 | (match_operand:DI 2 "uns_arith_operand" "K")))] | |
| 2231 | "TARGET_64BIT" | |
| 2232 | "xori\\t%0,%1,%x2" | |
| 2233 | [(set_attr "type" "arith") | |
| 2234 | (set_attr "mode" "DI") | |
| 2235 | (set_attr "length" "1")]) | |
| 2236 | ||
| 8ef30996 MM |
2237 | \f |
| 2238 | ;; | |
| 2239 | ;; .................... | |
| 2240 | ;; | |
| 2241 | ;; TRUNCATION | |
| 2242 | ;; | |
| 2243 | ;; .................... | |
| 2244 | ||
| 2245 | (define_insn "truncdfsf2" | |
| 2246 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 2247 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] | |
| 46299de9 | 2248 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
2249 | "cvt.s.d\\t%0,%1" |
| 2250 | [(set_attr "type" "fcvt") | |
| 2251 | (set_attr "mode" "SF") | |
| 2252 | (set_attr "length" "1")]) | |
| 2253 | ||
| 8894cf34 JW |
2254 | (define_insn "truncdisi2" |
| 2255 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2256 | (truncate:SI (match_operand:DI 1 "register_operand" "d")))] | |
| bb621ad7 | 2257 | "TARGET_64BIT" |
| 8894cf34 JW |
2258 | "dsll\\t%0,%1,32\;dsra\\t%0,%0,32" |
| 2259 | [(set_attr "type" "darith") | |
| 2260 | (set_attr "mode" "SI") | |
| 2261 | (set_attr "length" "2")]) | |
| bb621ad7 | 2262 | |
| 8894cf34 JW |
2263 | (define_insn "truncdihi2" |
| 2264 | [(set (match_operand:HI 0 "register_operand" "=d") | |
| 2265 | (truncate:HI (match_operand:DI 1 "register_operand" "d")))] | |
| bb621ad7 | 2266 | "TARGET_64BIT" |
| 8894cf34 JW |
2267 | "andi\\t%0,%1,0xffff" |
| 2268 | [(set_attr "type" "darith") | |
| 2269 | (set_attr "mode" "HI") | |
| 2270 | (set_attr "length" "1")]) | |
| bb621ad7 | 2271 | |
| 8894cf34 JW |
2272 | (define_insn "truncdiqi2" |
| 2273 | [(set (match_operand:QI 0 "register_operand" "=d") | |
| 2274 | (truncate:QI (match_operand:DI 1 "register_operand" "d")))] | |
| bb621ad7 | 2275 | "TARGET_64BIT" |
| 8894cf34 JW |
2276 | "andi\\t%0,%1,0x00ff" |
| 2277 | [(set_attr "type" "darith") | |
| 2278 | (set_attr "mode" "QI") | |
| 2279 | (set_attr "length" "1")]) | |
| a67f7692 JW |
2280 | |
| 2281 | ;; Combiner patterns to optimize shift/truncate combinations. | |
| 2282 | (define_insn "" | |
| 2283 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2284 | (truncate:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 2285 | (match_operand:DI 2 "small_int" "I"))))] | |
| 2286 | "TARGET_64BIT" | |
| 2287 | "* | |
| 2288 | { | |
| 2289 | int shift_amt = INTVAL (operands[2]) & 0x3f; | |
| 2290 | ||
| 2291 | if (shift_amt < 32) | |
| 2292 | { | |
| 2293 | operands[2] = GEN_INT (32 - shift_amt); | |
| 2294 | return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\"; | |
| 2295 | } | |
| 2296 | else | |
| 2297 | { | |
| 2298 | operands[2] = GEN_INT (shift_amt); | |
| 2299 | return \"dsra\\t%0,%1,%2\"; | |
| 2300 | } | |
| 2301 | }" | |
| 2302 | [(set_attr "type" "darith") | |
| 2303 | (set_attr "mode" "SI") | |
| 2304 | (set_attr "length" "2")]) | |
| 2305 | ||
| 2306 | (define_insn "" | |
| 2307 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2308 | (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 2309 | (match_operand:DI 2 "small_int" "I"))))] | |
| 2310 | "TARGET_64BIT" | |
| 2311 | "* | |
| 2312 | { | |
| 2313 | int shift_amt = INTVAL (operands[2]) & 0x3f; | |
| 2314 | ||
| 2315 | if (shift_amt < 32) | |
| 2316 | { | |
| 2317 | operands[2] = GEN_INT (32 - shift_amt); | |
| 2318 | return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\"; | |
| 2319 | } | |
| 2320 | else if (shift_amt == 32) | |
| 2321 | return \"dsra\\t%0,%1,32\"; | |
| 2322 | else | |
| 2323 | { | |
| 2324 | operands[2] = GEN_INT (shift_amt); | |
| 2325 | return \"dsrl\\t%0,%1,%2\"; | |
| 2326 | } | |
| 2327 | }" | |
| 2328 | [(set_attr "type" "darith") | |
| 2329 | (set_attr "mode" "SI") | |
| 2330 | (set_attr "length" "2")]) | |
| 2331 | ||
| 2332 | (define_insn "" | |
| 2333 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2334 | (truncate:SI (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
| 2335 | (match_operand:DI 2 "small_int" "I"))))] | |
| 2336 | "TARGET_64BIT" | |
| 2337 | "* | |
| 2338 | { | |
| 2339 | int shift_amt = INTVAL (operands[2]) & 0x3f; | |
| 2340 | ||
| 2341 | if (shift_amt < 32) | |
| 2342 | { | |
| 2343 | operands[2] = GEN_INT (32 + shift_amt); | |
| 2344 | return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\"; | |
| 2345 | } | |
| 2346 | else | |
| 2347 | return \"move\\t%0,%.\"; | |
| 2348 | }" | |
| 2349 | [(set_attr "type" "darith") | |
| 2350 | (set_attr "mode" "SI") | |
| 2351 | (set_attr "length" "2")]) | |
| 99f762bf JW |
2352 | |
| 2353 | ;; Combiner patterns to optimize truncate/zero_extend combinations. | |
| 2354 | ||
| 2355 | (define_insn "" | |
| 2356 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2357 | (zero_extend:SI (truncate:HI | |
| 2358 | (match_operand:DI 1 "register_operand" "d"))))] | |
| 2359 | "TARGET_64BIT" | |
| 2360 | "andi\\t%0,%1,0xffff" | |
| 2361 | [(set_attr "type" "darith") | |
| 2362 | (set_attr "mode" "SI") | |
| 2363 | (set_attr "length" "1")]) | |
| 2364 | ||
| 2365 | (define_insn "" | |
| 2366 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2367 | (zero_extend:SI (truncate:QI | |
| 2368 | (match_operand:DI 1 "register_operand" "d"))))] | |
| 2369 | "TARGET_64BIT" | |
| 2370 | "andi\\t%0,%1,0xff" | |
| 2371 | [(set_attr "type" "darith") | |
| 2372 | (set_attr "mode" "SI") | |
| 2373 | (set_attr "length" "1")]) | |
| 2374 | ||
| 2375 | (define_insn "" | |
| 2376 | [(set (match_operand:HI 0 "register_operand" "=d") | |
| 2377 | (zero_extend:HI (truncate:QI | |
| 2378 | (match_operand:DI 1 "register_operand" "d"))))] | |
| 2379 | "TARGET_64BIT" | |
| 2380 | "andi\\t%0,%1,0xff" | |
| 2381 | [(set_attr "type" "darith") | |
| 2382 | (set_attr "mode" "HI") | |
| 2383 | (set_attr "length" "1")]) | |
| 8ef30996 MM |
2384 | \f |
| 2385 | ;; | |
| 2386 | ;; .................... | |
| 2387 | ;; | |
| 2388 | ;; ZERO EXTENSION | |
| 2389 | ;; | |
| 2390 | ;; .................... | |
| 2391 | ||
| 2392 | ;; Extension insns. | |
| abdf3eea | 2393 | ;; Those for integer source operand are ordered widest source type first. |
| 8ef30996 | 2394 | |
| bb621ad7 JW |
2395 | (define_expand "zero_extendsidi2" |
| 2396 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2397 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
| 2398 | "TARGET_64BIT" | |
| 2399 | " | |
| 2400 | { | |
| 2401 | if (optimize && GET_CODE (operands[1]) == MEM) | |
| 2402 | operands[1] = force_not_mem (operands[1]); | |
| 2403 | ||
| 2404 | if (GET_CODE (operands[1]) != MEM) | |
| 2405 | { | |
| 2406 | rtx op1 = gen_lowpart (DImode, operands[1]); | |
| 2407 | rtx temp = gen_reg_rtx (DImode); | |
| 2408 | rtx shift = gen_rtx (CONST_INT, VOIDmode, 32); | |
| 2409 | ||
| 2410 | emit_insn (gen_ashldi3 (temp, op1, shift)); | |
| 2411 | emit_insn (gen_lshrdi3 (operands[0], temp, shift)); | |
| 2412 | DONE; | |
| 2413 | } | |
| 2414 | }") | |
| 2415 | ||
| 2416 | (define_insn "zero_extendsidi2_internal" | |
| 2417 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 2418 | (zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))] | |
| 2419 | "TARGET_64BIT" | |
| 2420 | "* return mips_move_1word (operands, insn, TRUE);" | |
| 2421 | [(set_attr "type" "load") | |
| 2422 | (set_attr "mode" "DI") | |
| 2423 | (set_attr "length" "1,2")]) | |
| 2424 | ||
| 8ef30996 MM |
2425 | (define_insn "zero_extendhisi2" |
| 2426 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 2427 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))] | |
| 2428 | "" | |
| 2429 | "* | |
| 2430 | { | |
| 2431 | if (which_alternative == 0) | |
| 2432 | return \"andi\\t%0,%1,0xffff\"; | |
| 2433 | else | |
| 2434 | return mips_move_1word (operands, insn, TRUE); | |
| 2435 | }" | |
| 2436 | [(set_attr "type" "arith,load,load") | |
| 92b4cee1 | 2437 | (set_attr "mode" "SI") |
| 8ef30996 MM |
2438 | (set_attr "length" "1,1,2")]) |
| 2439 | ||
| bb621ad7 JW |
2440 | (define_insn "zero_extendhidi2" |
| 2441 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
| 2442 | (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))] | |
| 2443 | "TARGET_64BIT" | |
| 2444 | "* | |
| 2445 | { | |
| 2446 | if (which_alternative == 0) | |
| 2447 | return \"andi\\t%0,%1,0xffff\"; | |
| 2448 | else | |
| 2449 | return mips_move_1word (operands, insn, TRUE); | |
| 2450 | }" | |
| 2451 | [(set_attr "type" "arith,load,load") | |
| 2452 | (set_attr "mode" "DI") | |
| 2453 | (set_attr "length" "1,1,2")]) | |
| 2454 | ||
| 8ef30996 MM |
2455 | (define_insn "zero_extendqihi2" |
| 2456 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
| 2457 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] | |
| 2458 | "" | |
| 2459 | "* | |
| 2460 | { | |
| 2461 | if (which_alternative == 0) | |
| 2462 | return \"andi\\t%0,%1,0x00ff\"; | |
| 2463 | else | |
| 2464 | return mips_move_1word (operands, insn, TRUE); | |
| 2465 | }" | |
| 2466 | [(set_attr "type" "arith,load,load") | |
| 92b4cee1 | 2467 | (set_attr "mode" "HI") |
| 8ef30996 MM |
2468 | (set_attr "length" "1,1,2")]) |
| 2469 | ||
| 2470 | (define_insn "zero_extendqisi2" | |
| 2471 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 2472 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] | |
| 2473 | "" | |
| 2474 | "* | |
| 2475 | { | |
| 2476 | if (which_alternative == 0) | |
| 2477 | return \"andi\\t%0,%1,0x00ff\"; | |
| 2478 | else | |
| 2479 | return mips_move_1word (operands, insn, TRUE); | |
| 2480 | }" | |
| 2481 | [(set_attr "type" "arith,load,load") | |
| 92b4cee1 | 2482 | (set_attr "mode" "SI") |
| 8ef30996 MM |
2483 | (set_attr "length" "1,1,2")]) |
| 2484 | ||
| bb621ad7 JW |
2485 | (define_insn "zero_extendqidi2" |
| 2486 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
| 2487 | (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] | |
| 2488 | "TARGET_64BIT" | |
| 2489 | "* | |
| 2490 | { | |
| 2491 | if (which_alternative == 0) | |
| 2492 | return \"andi\\t%0,%1,0x00ff\"; | |
| 2493 | else | |
| 2494 | return mips_move_1word (operands, insn, TRUE); | |
| 2495 | }" | |
| 2496 | [(set_attr "type" "arith,load,load") | |
| 2497 | (set_attr "mode" "DI") | |
| 2498 | (set_attr "length" "1,1,2")]) | |
| 2499 | ||
| 8ef30996 MM |
2500 | \f |
| 2501 | ;; | |
| 2502 | ;; .................... | |
| 2503 | ;; | |
| 2504 | ;; SIGN EXTENSION | |
| 2505 | ;; | |
| 2506 | ;; .................... | |
| 2507 | ||
| 2508 | ;; Extension insns. | |
| abdf3eea | 2509 | ;; Those for integer source operand are ordered widest source type first. |
| 8ef30996 | 2510 | |
| abdf3eea JW |
2511 | (define_expand "extendsidi2" |
| 2512 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2513 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
| bb621ad7 | 2514 | "TARGET_64BIT" |
| abdf3eea | 2515 | " |
| bb621ad7 | 2516 | { |
| abdf3eea JW |
2517 | if (optimize && GET_CODE (operands[1]) == MEM) |
| 2518 | operands[1] = force_not_mem (operands[1]); | |
| 2519 | ||
| 2520 | if (GET_CODE (operands[1]) != MEM) | |
| 2521 | { | |
| 2522 | rtx op1 = gen_lowpart (DImode, operands[1]); | |
| 2523 | rtx temp = gen_reg_rtx (DImode); | |
| 2524 | rtx shift = gen_rtx (CONST_INT, VOIDmode, 32); | |
| 2525 | ||
| 2526 | emit_insn (gen_ashldi3 (temp, op1, shift)); | |
| 2527 | emit_insn (gen_ashrdi3 (operands[0], temp, shift)); | |
| 2528 | DONE; | |
| 2529 | } | |
| 2530 | }") | |
| 2531 | ||
| 2532 | (define_insn "extendsidi2_internal" | |
| 2533 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 2534 | (sign_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))] | |
| 2535 | "TARGET_64BIT" | |
| 2536 | "* return mips_move_1word (operands, insn, FALSE);" | |
| 2537 | [(set_attr "type" "load") | |
| bb621ad7 | 2538 | (set_attr "mode" "DI") |
| abdf3eea | 2539 | (set_attr "length" "1,2")]) |
| bb621ad7 | 2540 | |
| 8ef30996 MM |
2541 | ;; These patterns originally accepted general_operands, however, slightly |
| 2542 | ;; better code is generated by only accepting register_operands, and then | |
| 2543 | ;; letting combine generate the lh and lb insns. | |
| 2544 | ||
| bb621ad7 JW |
2545 | (define_expand "extendhidi2" |
| 2546 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2547 | (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
| 2548 | "TARGET_64BIT" | |
| 2549 | " | |
| 2550 | { | |
| 2551 | if (optimize && GET_CODE (operands[1]) == MEM) | |
| 2552 | operands[1] = force_not_mem (operands[1]); | |
| 2553 | ||
| 2554 | if (GET_CODE (operands[1]) != MEM) | |
| 2555 | { | |
| 2556 | rtx op1 = gen_lowpart (DImode, operands[1]); | |
| 2557 | rtx temp = gen_reg_rtx (DImode); | |
| 2558 | rtx shift = gen_rtx (CONST_INT, VOIDmode, 48); | |
| 2559 | ||
| 2560 | emit_insn (gen_ashldi3 (temp, op1, shift)); | |
| 2561 | emit_insn (gen_ashrdi3 (operands[0], temp, shift)); | |
| 2562 | DONE; | |
| 2563 | } | |
| 2564 | }") | |
| 2565 | ||
| 2566 | (define_insn "extendhidi2_internal" | |
| 2567 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 2568 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))] | |
| 2569 | "TARGET_64BIT" | |
| 2570 | "* return mips_move_1word (operands, insn, FALSE);" | |
| 2571 | [(set_attr "type" "load") | |
| 2572 | (set_attr "mode" "DI") | |
| 2573 | (set_attr "length" "1,2")]) | |
| 2574 | ||
| 8ef30996 MM |
2575 | (define_expand "extendhisi2" |
| 2576 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2577 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
| 2578 | "" | |
| 2579 | " | |
| 2580 | { | |
| 2581 | if (optimize && GET_CODE (operands[1]) == MEM) | |
| 2582 | operands[1] = force_not_mem (operands[1]); | |
| 2583 | ||
| 2584 | if (GET_CODE (operands[1]) != MEM) | |
| 2585 | { | |
| 2586 | rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 2587 | rtx temp = gen_reg_rtx (SImode); | |
| 2588 | rtx shift = gen_rtx (CONST_INT, VOIDmode, 16); | |
| 2589 | ||
| 2590 | emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 2591 | emit_insn (gen_ashrsi3 (operands[0], temp, shift)); | |
| 2592 | DONE; | |
| 2593 | } | |
| 2594 | }") | |
| 2595 | ||
| 2596 | (define_insn "extendhisi2_internal" | |
| 2597 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 2598 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))] | |
| 2599 | "" | |
| 2600 | "* return mips_move_1word (operands, insn, FALSE);" | |
| 92b4cee1 MM |
2601 | [(set_attr "type" "load") |
| 2602 | (set_attr "mode" "SI") | |
| 8ef30996 MM |
2603 | (set_attr "length" "1,2")]) |
| 2604 | ||
| 2605 | (define_expand "extendqihi2" | |
| 2606 | [(set (match_operand:HI 0 "register_operand" "") | |
| 2607 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 2608 | "" | |
| 2609 | " | |
| 2610 | { | |
| 2611 | if (optimize && GET_CODE (operands[1]) == MEM) | |
| 2612 | operands[1] = force_not_mem (operands[1]); | |
| 2613 | ||
| 2614 | if (GET_CODE (operands[1]) != MEM) | |
| 2615 | { | |
| 2616 | rtx op0 = gen_lowpart (SImode, operands[0]); | |
| 2617 | rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 2618 | rtx temp = gen_reg_rtx (SImode); | |
| 2619 | rtx shift = gen_rtx (CONST_INT, VOIDmode, 24); | |
| 2620 | ||
| 2621 | emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 2622 | emit_insn (gen_ashrsi3 (op0, temp, shift)); | |
| 2623 | DONE; | |
| 2624 | } | |
| 2625 | }") | |
| 2626 | ||
| 2627 | (define_insn "extendqihi2_internal" | |
| 2628 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
| 2629 | (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))] | |
| 2630 | "" | |
| 2631 | "* return mips_move_1word (operands, insn, FALSE);" | |
| 92b4cee1 MM |
2632 | [(set_attr "type" "load") |
| 2633 | (set_attr "mode" "SI") | |
| 8ef30996 MM |
2634 | (set_attr "length" "1,2")]) |
| 2635 | ||
| 2636 | ||
| 2637 | (define_expand "extendqisi2" | |
| 2638 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2639 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 2640 | "" | |
| 2641 | " | |
| 2642 | { | |
| 2643 | if (optimize && GET_CODE (operands[1]) == MEM) | |
| 2644 | operands[1] = force_not_mem (operands[1]); | |
| 2645 | ||
| 2646 | if (GET_CODE (operands[1]) != MEM) | |
| 2647 | { | |
| 2648 | rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 2649 | rtx temp = gen_reg_rtx (SImode); | |
| 2650 | rtx shift = gen_rtx (CONST_INT, VOIDmode, 24); | |
| 2651 | ||
| 2652 | emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 2653 | emit_insn (gen_ashrsi3 (operands[0], temp, shift)); | |
| 2654 | DONE; | |
| 2655 | } | |
| 2656 | }") | |
| 2657 | ||
| 2658 | (define_insn "extendqisi2_insn" | |
| 2659 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 2660 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))] | |
| 2661 | "" | |
| 2662 | "* return mips_move_1word (operands, insn, FALSE);" | |
| 92b4cee1 MM |
2663 | [(set_attr "type" "load") |
| 2664 | (set_attr "mode" "SI") | |
| 8ef30996 MM |
2665 | (set_attr "length" "1,2")]) |
| 2666 | ||
| bb621ad7 JW |
2667 | (define_expand "extendqidi2" |
| 2668 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2669 | (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 2670 | "TARGET_64BIT" | |
| 2671 | " | |
| 2672 | { | |
| 2673 | if (optimize && GET_CODE (operands[1]) == MEM) | |
| 2674 | operands[1] = force_not_mem (operands[1]); | |
| 2675 | ||
| 2676 | if (GET_CODE (operands[1]) != MEM) | |
| 2677 | { | |
| 2678 | rtx op1 = gen_lowpart (DImode, operands[1]); | |
| 2679 | rtx temp = gen_reg_rtx (DImode); | |
| 2680 | rtx shift = gen_rtx (CONST_INT, VOIDmode, 56); | |
| 2681 | ||
| 2682 | emit_insn (gen_ashldi3 (temp, op1, shift)); | |
| 2683 | emit_insn (gen_ashrdi3 (operands[0], temp, shift)); | |
| 2684 | DONE; | |
| 2685 | } | |
| 2686 | }") | |
| 2687 | ||
| 2688 | (define_insn "extendqidi2_insn" | |
| 2689 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 2690 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))] | |
| 2691 | "TARGET_64BIT" | |
| 2692 | "* return mips_move_1word (operands, insn, FALSE);" | |
| 2693 | [(set_attr "type" "load") | |
| 2694 | (set_attr "mode" "DI") | |
| 2695 | (set_attr "length" "1,2")]) | |
| 2696 | ||
| 8ef30996 MM |
2697 | |
| 2698 | (define_insn "extendsfdf2" | |
| 2699 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 2700 | (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] | |
| 46299de9 | 2701 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
2702 | "cvt.d.s\\t%0,%1" |
| 2703 | [(set_attr "type" "fcvt") | |
| 2704 | (set_attr "mode" "DF") | |
| 2705 | (set_attr "length" "1")]) | |
| 2706 | ||
| 2707 | \f | |
| 2708 | ||
| 2709 | ;; | |
| 2710 | ;; .................... | |
| 2711 | ;; | |
| 2712 | ;; CONVERSIONS | |
| 2713 | ;; | |
| 2714 | ;; .................... | |
| 2715 | ||
| d1460eef JW |
2716 | ;; The SImode scratch register can not be shared with address regs used for |
| 2717 | ;; operand zero, because then the address in the move instruction will be | |
| 2718 | ;; clobbered. We mark the scratch register as early clobbered to prevent this. | |
| 2719 | ||
| c7343333 | 2720 | (define_insn "fix_truncdfsi2" |
| 8ef30996 MM |
2721 | [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o") |
| 2722 | (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f"))) | |
| d1460eef | 2723 | (clobber (match_scratch:SI 2 "=d,*d,&d,&d")) |
| c7343333 | 2724 | (clobber (match_scratch:DF 3 "=f,*X,f,f"))] |
| 46299de9 | 2725 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
2726 | "* |
| 2727 | { | |
| 2728 | rtx xoperands[10]; | |
| 2729 | ||
| 2730 | if (which_alternative == 1) | |
| 2731 | return \"trunc.w.d %0,%1,%2\"; | |
| 2732 | ||
| 2733 | output_asm_insn (\"trunc.w.d %3,%1,%2\", operands); | |
| 2734 | ||
| 2735 | xoperands[0] = operands[0]; | |
| 2736 | xoperands[1] = operands[3]; | |
| 2737 | output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands); | |
| 2738 | return \"\"; | |
| 2739 | }" | |
| 92b4cee1 MM |
2740 | [(set_attr "type" "fcvt") |
| 2741 | (set_attr "mode" "DF") | |
| c7343333 | 2742 | (set_attr "length" "11,9,10,11")]) |
| 8ef30996 MM |
2743 | |
| 2744 | ||
| c7343333 | 2745 | (define_insn "fix_truncsfsi2" |
| 8ef30996 MM |
2746 | [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o") |
| 2747 | (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f"))) | |
| d1460eef | 2748 | (clobber (match_scratch:SI 2 "=d,*d,&d,&d")) |
| c7343333 | 2749 | (clobber (match_scratch:SF 3 "=f,*X,f,f"))] |
| 8ef30996 MM |
2750 | "TARGET_HARD_FLOAT" |
| 2751 | "* | |
| 2752 | { | |
| 2753 | rtx xoperands[10]; | |
| 2754 | ||
| 2755 | if (which_alternative == 1) | |
| 2756 | return \"trunc.w.s %0,%1,%2\"; | |
| 2757 | ||
| 2758 | output_asm_insn (\"trunc.w.s %3,%1,%2\", operands); | |
| 2759 | ||
| 2760 | xoperands[0] = operands[0]; | |
| 2761 | xoperands[1] = operands[3]; | |
| 2762 | output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands); | |
| 2763 | return \"\"; | |
| 2764 | }" | |
| 92b4cee1 MM |
2765 | [(set_attr "type" "fcvt") |
| 2766 | (set_attr "mode" "SF") | |
| c7343333 | 2767 | (set_attr "length" "11,9,10,11")]) |
| 8ef30996 MM |
2768 | |
| 2769 | ||
| bb621ad7 JW |
2770 | ;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals |
| 2771 | ;;; but not in the chapter that describes the FPU. It is not mentioned at all | |
| 2772 | ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction. | |
| 2773 | ||
| 2774 | ;;; Deleting this means that we now need two libgcc2.a libraries. One for | |
| 2775 | ;;; the 32 bit calling convention and one for the 64 bit calling convention. | |
| 2776 | ||
| 2777 | ;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also. | |
| 2778 | ||
| 2779 | (define_insn "fix_truncdfdi2" | |
| 2780 | [(set (match_operand:DI 0 "general_operand" "=d,*f,R,o") | |
| 2781 | (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f"))) | |
| 2782 | (clobber (match_scratch:DF 2 "=f,*X,f,f"))] | |
| 46299de9 | 2783 | "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" |
| bb621ad7 JW |
2784 | "* |
| 2785 | { | |
| 2786 | rtx xoperands[10]; | |
| 2787 | ||
| 2788 | if (which_alternative == 1) | |
| 2789 | return \"trunc.l.d %0,%1\"; | |
| 2790 | ||
| 2791 | output_asm_insn (\"trunc.l.d %2,%1\", operands); | |
| 2792 | ||
| 2793 | xoperands[0] = operands[0]; | |
| 2794 | xoperands[1] = operands[2]; | |
| 2795 | output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands); | |
| 2796 | return \"\"; | |
| 2797 | }" | |
| 2798 | [(set_attr "type" "fcvt") | |
| 2799 | (set_attr "mode" "DF") | |
| 2800 | (set_attr "length" "2,1,2,3")]) | |
| 2801 | ||
| 2802 | ||
| 2803 | ;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals | |
| 2804 | ;;; but not in the chapter that describes the FPU. It is not mentioned at all | |
| 2805 | ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction. | |
| 2806 | (define_insn "fix_truncsfdi2" | |
| 2807 | [(set (match_operand:DI 0 "general_operand" "=d,*f,R,o") | |
| 2808 | (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f"))) | |
| 2809 | (clobber (match_scratch:DF 2 "=f,*X,f,f"))] | |
| 46299de9 | 2810 | "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" |
| bb621ad7 JW |
2811 | "* |
| 2812 | { | |
| 2813 | rtx xoperands[10]; | |
| 2814 | ||
| 2815 | if (which_alternative == 1) | |
| 2816 | return \"trunc.l.s %0,%1\"; | |
| 2817 | ||
| 2818 | output_asm_insn (\"trunc.l.s %2,%1\", operands); | |
| 2819 | ||
| 2820 | xoperands[0] = operands[0]; | |
| 2821 | xoperands[1] = operands[2]; | |
| 2822 | output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands); | |
| 2823 | return \"\"; | |
| 2824 | }" | |
| 2825 | [(set_attr "type" "fcvt") | |
| 2826 | (set_attr "mode" "SF") | |
| 2827 | (set_attr "length" "2,1,2,3")]) | |
| 2828 | ||
| 2829 | ||
| 8ef30996 | 2830 | (define_insn "floatsidf2" |
| bbdb5552 MM |
2831 | [(set (match_operand:DF 0 "register_operand" "=f,f,f") |
| 2832 | (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] | |
| 46299de9 | 2833 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| bbdb5552 MM |
2834 | "* |
| 2835 | { | |
| 2836 | dslots_load_total++; | |
| 2837 | if (GET_CODE (operands[1]) == MEM) | |
| 5cccf78f | 2838 | return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\"; |
| bbdb5552 MM |
2839 | |
| 2840 | return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\"; | |
| 2841 | }" | |
| 92b4cee1 MM |
2842 | [(set_attr "type" "fcvt") |
| 2843 | (set_attr "mode" "DF") | |
| bbdb5552 | 2844 | (set_attr "length" "3,4,3")]) |
| 8ef30996 | 2845 | |
| c7343333 | 2846 | |
| bb621ad7 JW |
2847 | (define_insn "floatdidf2" |
| 2848 | [(set (match_operand:DF 0 "register_operand" "=f,f,f") | |
| 2849 | (float:DF (match_operand:DI 1 "nonimmediate_operand" "d,R,m")))] | |
| 46299de9 | 2850 | "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" |
| bb621ad7 JW |
2851 | "* |
| 2852 | { | |
| 2853 | dslots_load_total++; | |
| 2854 | if (GET_CODE (operands[1]) == MEM) | |
| 2855 | return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\"; | |
| 2856 | ||
| 2857 | return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\"; | |
| 2858 | }" | |
| 2859 | [(set_attr "type" "fcvt") | |
| 2860 | (set_attr "mode" "DF") | |
| 2861 | (set_attr "length" "3,4,3")]) | |
| 2862 | ||
| 2863 | ||
| 8ef30996 | 2864 | (define_insn "floatsisf2" |
| bbdb5552 MM |
2865 | [(set (match_operand:SF 0 "register_operand" "=f,f,f") |
| 2866 | (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] | |
| 8ef30996 | 2867 | "TARGET_HARD_FLOAT" |
| bbdb5552 MM |
2868 | "* |
| 2869 | { | |
| 2870 | dslots_load_total++; | |
| 2871 | if (GET_CODE (operands[1]) == MEM) | |
| 5cccf78f | 2872 | return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\"; |
| bbdb5552 MM |
2873 | |
| 2874 | return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\"; | |
| 2875 | }" | |
| 92b4cee1 MM |
2876 | [(set_attr "type" "fcvt") |
| 2877 | (set_attr "mode" "SF") | |
| bbdb5552 MM |
2878 | (set_attr "length" "3,4,3")]) |
| 2879 | ||
| 8ef30996 | 2880 | |
| bb621ad7 JW |
2881 | (define_insn "floatdisf2" |
| 2882 | [(set (match_operand:SF 0 "register_operand" "=f,f,f") | |
| 2883 | (float:SF (match_operand:DI 1 "nonimmediate_operand" "d,R,m")))] | |
| 46299de9 | 2884 | "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" |
| bb621ad7 JW |
2885 | "* |
| 2886 | { | |
| 2887 | dslots_load_total++; | |
| 2888 | if (GET_CODE (operands[1]) == MEM) | |
| 2889 | return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\"; | |
| 2890 | ||
| 2891 | return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\"; | |
| 2892 | }" | |
| 2893 | [(set_attr "type" "fcvt") | |
| 2894 | (set_attr "mode" "SF") | |
| 2895 | (set_attr "length" "3,4,3")]) | |
| 2896 | ||
| 2897 | ||
| 8ef30996 MM |
2898 | (define_expand "fixuns_truncdfsi2" |
| 2899 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2900 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
| 46299de9 | 2901 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
2902 | " |
| 2903 | { | |
| 2904 | rtx reg1 = gen_reg_rtx (DFmode); | |
| 2905 | rtx reg2 = gen_reg_rtx (DFmode); | |
| 2906 | rtx reg3 = gen_reg_rtx (SImode); | |
| 2907 | rtx label1 = gen_label_rtx (); | |
| 2908 | rtx label2 = gen_label_rtx (); | |
| 2909 | REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31); | |
| 2910 | ||
| 2911 | if (reg1) /* turn off complaints about unreached code */ | |
| 2912 | { | |
| 8ef30996 MM |
2913 | emit_move_insn (reg1, immed_real_const_1 (offset, DFmode)); |
| 2914 | do_pending_stack_adjust (); | |
| 2915 | ||
| 2916 | emit_insn (gen_cmpdf (operands[1], reg1)); | |
| 2917 | emit_jump_insn (gen_bge (label1)); | |
| 2918 | ||
| 2919 | emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1])); | |
| 2920 | emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, | |
| 2921 | gen_rtx (LABEL_REF, VOIDmode, label2))); | |
| 2922 | emit_barrier (); | |
| 2923 | ||
| 2924 | emit_label (label1); | |
| 2925 | emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1)); | |
| 2926 | emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000)); | |
| 2927 | ||
| 2928 | emit_insn (gen_fix_truncdfsi2 (operands[0], reg2)); | |
| 2929 | emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); | |
| 2930 | ||
| 2931 | emit_label (label2); | |
| 2932 | ||
| 2933 | /* allow REG_NOTES to be set on last insn (labels don't have enough | |
| 2934 | fields, and can't be used for REG_NOTES anyway). */ | |
| 2935 | emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); | |
| 2936 | DONE; | |
| 2937 | } | |
| 2938 | }") | |
| 2939 | ||
| c7343333 | 2940 | |
| bb621ad7 JW |
2941 | (define_expand "fixuns_truncdfdi2" |
| 2942 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2943 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
| 46299de9 | 2944 | "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" |
| bb621ad7 JW |
2945 | " |
| 2946 | { | |
| 2947 | rtx reg1 = gen_reg_rtx (DFmode); | |
| 2948 | rtx reg2 = gen_reg_rtx (DFmode); | |
| 2949 | rtx reg3 = gen_reg_rtx (DImode); | |
| 2950 | rtx label1 = gen_label_rtx (); | |
| 2951 | rtx label2 = gen_label_rtx (); | |
| 2952 | REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63); | |
| 2953 | ||
| 2954 | if (reg1) /* turn off complaints about unreached code */ | |
| 2955 | { | |
| 2956 | emit_move_insn (reg1, immed_real_const_1 (offset, DFmode)); | |
| 2957 | do_pending_stack_adjust (); | |
| 2958 | ||
| 2959 | emit_insn (gen_cmpdf (operands[1], reg1)); | |
| 2960 | emit_jump_insn (gen_bge (label1)); | |
| 2961 | ||
| 2962 | emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1])); | |
| 2963 | emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, | |
| 2964 | gen_rtx (LABEL_REF, VOIDmode, label2))); | |
| 2965 | emit_barrier (); | |
| 2966 | ||
| 2967 | emit_label (label1); | |
| 2968 | emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1)); | |
| 2969 | emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000)); | |
| 2970 | emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); | |
| 2971 | ||
| 2972 | emit_insn (gen_fix_truncdfdi2 (operands[0], reg2)); | |
| 2973 | emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); | |
| 2974 | ||
| 2975 | emit_label (label2); | |
| 2976 | ||
| 2977 | /* allow REG_NOTES to be set on last insn (labels don't have enough | |
| 2978 | fields, and can't be used for REG_NOTES anyway). */ | |
| 2979 | emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); | |
| 2980 | DONE; | |
| 2981 | } | |
| 2982 | }") | |
| 2983 | ||
| 2984 | ||
| 8ef30996 MM |
2985 | (define_expand "fixuns_truncsfsi2" |
| 2986 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2987 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
| 2988 | "TARGET_HARD_FLOAT" | |
| 2989 | " | |
| 2990 | { | |
| 2991 | rtx reg1 = gen_reg_rtx (SFmode); | |
| 2992 | rtx reg2 = gen_reg_rtx (SFmode); | |
| 2993 | rtx reg3 = gen_reg_rtx (SImode); | |
| 2994 | rtx label1 = gen_label_rtx (); | |
| 2995 | rtx label2 = gen_label_rtx (); | |
| 2996 | REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31); | |
| 2997 | ||
| 2998 | if (reg1) /* turn off complaints about unreached code */ | |
| 2999 | { | |
| 8ef30996 MM |
3000 | emit_move_insn (reg1, immed_real_const_1 (offset, SFmode)); |
| 3001 | do_pending_stack_adjust (); | |
| 3002 | ||
| 3003 | emit_insn (gen_cmpsf (operands[1], reg1)); | |
| 3004 | emit_jump_insn (gen_bge (label1)); | |
| 3005 | ||
| 3006 | emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1])); | |
| 3007 | emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, | |
| 3008 | gen_rtx (LABEL_REF, VOIDmode, label2))); | |
| 3009 | emit_barrier (); | |
| 3010 | ||
| 3011 | emit_label (label1); | |
| 3012 | emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1)); | |
| 3013 | emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000)); | |
| 3014 | ||
| 3015 | emit_insn (gen_fix_truncsfsi2 (operands[0], reg2)); | |
| 3016 | emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); | |
| 3017 | ||
| 3018 | emit_label (label2); | |
| 3019 | ||
| 3020 | /* allow REG_NOTES to be set on last insn (labels don't have enough | |
| 3021 | fields, and can't be used for REG_NOTES anyway). */ | |
| 3022 | emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); | |
| 3023 | DONE; | |
| 3024 | } | |
| 3025 | }") | |
| 3026 | ||
| 8ef30996 | 3027 | |
| bb621ad7 JW |
3028 | (define_expand "fixuns_truncsfdi2" |
| 3029 | [(set (match_operand:DI 0 "register_operand" "") | |
| 3030 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
| 46299de9 | 3031 | "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
3032 | " |
| 3033 | { | |
| bb621ad7 JW |
3034 | rtx reg1 = gen_reg_rtx (SFmode); |
| 3035 | rtx reg2 = gen_reg_rtx (SFmode); | |
| 3036 | rtx reg3 = gen_reg_rtx (DImode); | |
| 3037 | rtx label1 = gen_label_rtx (); | |
| 3038 | rtx label2 = gen_label_rtx (); | |
| 3039 | REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63); | |
| 8ef30996 | 3040 | |
| bb621ad7 | 3041 | if (reg1) /* turn off complaints about unreached code */ |
| 8ef30996 | 3042 | { |
| bb621ad7 JW |
3043 | emit_move_insn (reg1, immed_real_const_1 (offset, SFmode)); |
| 3044 | do_pending_stack_adjust (); | |
| 8ef30996 | 3045 | |
| bb621ad7 JW |
3046 | emit_insn (gen_cmpsf (operands[1], reg1)); |
| 3047 | emit_jump_insn (gen_bge (label1)); | |
| 8ef30996 | 3048 | |
| bb621ad7 JW |
3049 | emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1])); |
| 3050 | emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, | |
| 3051 | gen_rtx (LABEL_REF, VOIDmode, label2))); | |
| 3052 | emit_barrier (); | |
| 8ef30996 | 3053 | |
| bb621ad7 JW |
3054 | emit_label (label1); |
| 3055 | emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1)); | |
| 3056 | emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000)); | |
| 3057 | emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); | |
| 8ef30996 | 3058 | |
| bb621ad7 JW |
3059 | emit_insn (gen_fix_truncsfdi2 (operands[0], reg2)); |
| 3060 | emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); | |
| 8ef30996 | 3061 | |
| bb621ad7 | 3062 | emit_label (label2); |
| 8ef30996 | 3063 | |
| bb621ad7 JW |
3064 | /* allow REG_NOTES to be set on last insn (labels don't have enough |
| 3065 | fields, and can't be used for REG_NOTES anyway). */ | |
| 3066 | emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); | |
| 3067 | DONE; | |
| 8ef30996 | 3068 | } |
| bb621ad7 | 3069 | }") |
| 8ef30996 | 3070 | |
| bb621ad7 JW |
3071 | \f |
| 3072 | ;; | |
| 3073 | ;; .................... | |
| 3074 | ;; | |
| 3075 | ;; DATA MOVEMENT | |
| 3076 | ;; | |
| 3077 | ;; .................... | |
| 8ef30996 | 3078 | |
| c5563e11 JW |
3079 | ;; Bit field extract patterns which use lwl/lwr. |
| 3080 | ||
| 3081 | ;; ??? There should be DImode variants for 64 bit code, but the current | |
| 3082 | ;; bitfield scheme can't handle that. We would need to add new optabs | |
| 3083 | ;; in order to make that work. | |
| 3084 | ||
| 3085 | ;; ??? There could be HImode variants for the ulh/ulhu/ush macros. | |
| 3086 | ;; It isn't clear whether this will give better code. | |
| 3087 | ||
| 3088 | (define_expand "extv" | |
| 3089 | [(set (match_operand:SI 0 "register_operand" "") | |
| 3090 | (sign_extract:SI (match_operand:QI 1 "memory_operand" "") | |
| 3091 | (match_operand:SI 2 "immediate_operand" "") | |
| 3092 | (match_operand:SI 3 "immediate_operand" "")))] | |
| 3093 | "" | |
| 3094 | " | |
| 3095 | { | |
| 3096 | /* If this isn't a 32 bit field, and it doesn't start on a byte boundary | |
| 3097 | then fail. */ | |
| 3098 | if (INTVAL (operands[2]) != 32 || (INTVAL (operands[3]) % 8) != 0) | |
| 3099 | FAIL; | |
| 3100 | ||
| 3101 | /* This can happen for a 64 bit target, when extracting a value from | |
| 3102 | a 64 bit union member. extract_bit_field doesn't verify that our | |
| 3103 | source matches the predicate, so we force it to be a MEM here. */ | |
| 3104 | if (GET_CODE (operands[1]) != MEM) | |
| 3105 | FAIL; | |
| 8ef30996 | 3106 | |
| c5563e11 JW |
3107 | /* Otherwise, emit a lwl/lwr pair to load the value. */ |
| 3108 | emit_insn (gen_movsi_ulw (operands[0], operands[1])); | |
| 3109 | DONE; | |
| 3110 | }") | |
| 3111 | ||
| 3112 | (define_expand "extzv" | |
| 3113 | [(set (match_operand:SI 0 "register_operand" "") | |
| 3114 | (zero_extract:SI (match_operand:QI 1 "memory_operand" "") | |
| 3115 | (match_operand:SI 2 "immediate_operand" "") | |
| 3116 | (match_operand:SI 3 "immediate_operand" "")))] | |
| 3117 | "" | |
| 3118 | " | |
| 3119 | { | |
| 3120 | /* If this isn't a 32 bit field, and it doesn't start on a byte boundary | |
| 3121 | then fail. */ | |
| 3122 | if (INTVAL (operands[2]) != 32 || (INTVAL (operands[3]) % 8) != 0) | |
| 3123 | FAIL; | |
| 3124 | ||
| 3125 | /* This can happen for a 64 bit target, when extracting a value from | |
| 3126 | a 64 bit union member. extract_bit_field doesn't verify that our | |
| 3127 | source matches the predicate, so we force it to be a MEM here. */ | |
| 3128 | if (GET_CODE (operands[1]) != MEM) | |
| 3129 | FAIL; | |
| 3130 | ||
| 3131 | /* Otherwise, emit a lwl/lwr pair to load the value. */ | |
| 3132 | emit_insn (gen_movsi_ulw (operands[0], operands[1])); | |
| 3133 | DONE; | |
| 3134 | }") | |
| 3135 | ||
| 3136 | (define_expand "insv" | |
| 3137 | [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "") | |
| 3138 | (match_operand:SI 1 "immediate_operand" "") | |
| 3139 | (match_operand:SI 2 "immediate_operand" "")) | |
| 3140 | (match_operand:SI 3 "register_operand" ""))] | |
| 3141 | "" | |
| 3142 | " | |
| 3143 | { | |
| 3144 | /* If this isn't a 32 bit field, and it doesn't start on a byte boundary | |
| 3145 | then fail. */ | |
| 3146 | if (INTVAL (operands[1]) != 32 || (INTVAL (operands[2]) % 8) != 0) | |
| 3147 | FAIL; | |
| 3148 | ||
| 3149 | /* This can happen for a 64 bit target, when storing into a 32 bit union | |
| 3150 | member. store_bit_field doesn't verify that our target matches the | |
| 3151 | predicate, so we force it to be a MEM here. */ | |
| 3152 | if (GET_CODE (operands[0]) != MEM) | |
| 3153 | FAIL; | |
| 3154 | ||
| 3155 | /* Otherwise, emit a swl/swr pair to load the value. */ | |
| 3156 | emit_insn (gen_movsi_usw (operands[0], operands[3])); | |
| 3157 | DONE; | |
| 3158 | }") | |
| 3159 | ||
| 3160 | ;; unaligned word moves generated by the bit field patterns | |
| 3161 | ||
| 3162 | (define_insn "movsi_ulw" | |
| 3163 | [(set (match_operand:SI 0 "register_operand" "=&d,&d") | |
| 3164 | (unspec [(match_operand:QI 1 "general_operand" "R,o")] 0))] | |
| 3165 | "" | |
| 3166 | "* | |
| 3167 | { | |
| 3168 | rtx offset = const0_rtx; | |
| 3169 | rtx addr = XEXP (operands[1], 0); | |
| 3170 | rtx mem_addr = eliminate_constant_term (addr, &offset); | |
| 3171 | char *ret; | |
| 3172 | ||
| 3173 | if (TARGET_STATS) | |
| 3174 | mips_count_memory_refs (operands[1], 2); | |
| 3175 | ||
| 3176 | /* The stack/frame pointers are always aligned, so we can convert | |
| 3177 | to the faster lw if we are referencing an aligned stack location. */ | |
| 3178 | ||
| 3179 | if ((INTVAL (offset) & 3) == 0 | |
| 3180 | && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) | |
| 3181 | ret = \"lw\\t%0,%1\"; | |
| 3182 | else | |
| 3183 | ret = \"ulw\\t%0,%1\"; | |
| 3184 | ||
| 3185 | return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn); | |
| 3186 | }" | |
| 3187 | [(set_attr "type" "load,load") | |
| 3188 | (set_attr "mode" "SI") | |
| 3189 | (set_attr "length" "2,4")]) | |
| 3190 | ||
| 3191 | (define_insn "movsi_usw" | |
| 3192 | [(set (match_operand:QI 0 "memory_operand" "=R,o") | |
| 3193 | (unspec [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))] | |
| 3194 | "" | |
| 3195 | "* | |
| 3196 | { | |
| 3197 | rtx offset = const0_rtx; | |
| 3198 | rtx addr = XEXP (operands[0], 0); | |
| 3199 | rtx mem_addr = eliminate_constant_term (addr, &offset); | |
| 3200 | ||
| 3201 | if (TARGET_STATS) | |
| 3202 | mips_count_memory_refs (operands[0], 2); | |
| 3203 | ||
| 3204 | /* The stack/frame pointers are always aligned, so we can convert | |
| 3205 | to the faster sw if we are referencing an aligned stack location. */ | |
| 3206 | ||
| 3207 | if ((INTVAL (offset) & 3) == 0 | |
| 3208 | && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) | |
| 3209 | return \"sw\\t%1,%0\"; | |
| 3210 | ||
| 3211 | return \"usw\\t%z1,%0\"; | |
| 3212 | }" | |
| 3213 | [(set_attr "type" "store") | |
| 3214 | (set_attr "mode" "SI") | |
| 3215 | (set_attr "length" "2,4")]) | |
| ed50ab35 | 3216 | |
| aa4e54c4 JW |
3217 | ;; These two patterns support loading addresses with two instructions instead |
| 3218 | ;; of using the macro instruction la. | |
| 3219 | ||
| 3220 | ;; ??? mips_move_1word has support for HIGH, so this pattern may be | |
| 3221 | ;; unnecessary. | |
| 3222 | ||
| 3223 | (define_insn "high" | |
| 3224 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 3225 | (high:SI (match_operand:SI 1 "immediate_operand" "")))] | |
| 3226 | "mips_split_addresses" | |
| 3227 | "lui\\t%0,%%hi(%1) # high" | |
| 3228 | [(set_attr "type" "move") | |
| 3229 | (set_attr "length" "1")]) | |
| 3230 | ||
| 3231 | (define_insn "low" | |
| 3232 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 3233 | (lo_sum:SI (match_operand:SI 1 "register_operand" "r") | |
| 3234 | (match_operand:SI 2 "immediate_operand" "")))] | |
| 3235 | "mips_split_addresses" | |
| 3236 | "addiu\\t%0,%1,%%lo(%2) # low" | |
| 3237 | [(set_attr "type" "arith") | |
| 3238 | (set_attr "mode" "SI") | |
| 3239 | (set_attr "length" "1")]) | |
| 3240 | ||
| 8ef30996 MM |
3241 | ;; 64-bit integer moves |
| 3242 | ||
| 3243 | ;; Unlike most other insns, the move insns can't be split with | |
| 3244 | ;; different predicates, because register spilling and other parts of | |
| 3245 | ;; the compiler, have memoized the insn number already. | |
| 3246 | ||
| ed50ab35 MM |
3247 | (define_expand "movdi" |
| 3248 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
| 3249 | (match_operand:DI 1 "general_operand" ""))] | |
| 3250 | "" | |
| 3251 | " | |
| 3252 | { | |
| aa4e54c4 JW |
3253 | if (mips_split_addresses && mips_check_split (operands[1], DImode)) |
| 3254 | { | |
| 3255 | enum machine_mode mode = GET_MODE (operands[0]); | |
| 3256 | rtx tem = ((reload_in_progress | reload_completed) | |
| 3257 | ? operands[0] : gen_reg_rtx (mode)); | |
| 3258 | ||
| 3259 | emit_insn (gen_rtx (SET, VOIDmode, tem, | |
| 3260 | gen_rtx (HIGH, mode, operands[1]))); | |
| 3261 | ||
| 3262 | operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]); | |
| 3263 | } | |
| 3264 | ||
| e19ff60f JW |
3265 | /* If we are generating embedded PIC code, and we are referring to a |
| 3266 | symbol in the .text section, we must use an offset from the start | |
| 3267 | of the function. */ | |
| 3268 | if (TARGET_EMBEDDED_PIC | |
| 3269 | && (GET_CODE (operands[1]) == LABEL_REF | |
| 3270 | || (GET_CODE (operands[1]) == SYMBOL_REF | |
| 3271 | && ! SYMBOL_REF_FLAG (operands[1])))) | |
| 3272 | { | |
| 3273 | rtx temp; | |
| 3274 | ||
| 3275 | temp = embedded_pic_offset (operands[1]); | |
| 3276 | temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx, | |
| 3277 | force_reg (DImode, temp)); | |
| 3278 | emit_move_insn (operands[0], force_reg (DImode, temp)); | |
| 3279 | DONE; | |
| 3280 | } | |
| 3281 | ||
| 3282 | /* If operands[1] is a constant address illegal for pic, then we need to | |
| 3283 | handle it just like LEGITIMIZE_ADDRESS does. */ | |
| 3284 | if (flag_pic && pic_address_needs_scratch (operands[1])) | |
| 3285 | { | |
| 3286 | rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0)); | |
| 3287 | rtx temp2 = XEXP (XEXP (operands[1], 0), 1); | |
| 3288 | ||
| 3289 | if (! SMALL_INT (temp2)) | |
| 3290 | temp2 = force_reg (DImode, temp2); | |
| 3291 | ||
| 3292 | emit_move_insn (operands[0], gen_rtx (PLUS, DImode, temp, temp2)); | |
| 3293 | DONE; | |
| 3294 | } | |
| 3295 | ||
| ed50ab35 MM |
3296 | if ((reload_in_progress | reload_completed) == 0 |
| 3297 | && !register_operand (operands[0], DImode) | |
| 3298 | && !register_operand (operands[1], DImode) | |
| 3299 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) | |
| 3300 | && operands[1] != CONST0_RTX (DImode)) | |
| 3301 | { | |
| 3302 | rtx temp = force_reg (DImode, operands[1]); | |
| 3303 | emit_move_insn (operands[0], temp); | |
| 3304 | DONE; | |
| 3305 | } | |
| 3306 | }") | |
| 3307 | ||
| 3308 | (define_insn "movdi_internal" | |
| 6d518002 MM |
3309 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*d,*x") |
| 3310 | (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,*x,*d"))] | |
| bb621ad7 JW |
3311 | "!TARGET_64BIT |
| 3312 | && (register_operand (operands[0], DImode) | |
| 3313 | || register_operand (operands[1], DImode) | |
| 3314 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) | |
| 3315 | || operands[1] == CONST0_RTX (DImode))" | |
| 8ef30996 | 3316 | "* return mips_move_2words (operands, insn); " |
| 6d518002 | 3317 | [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo") |
| 92b4cee1 | 3318 | (set_attr "mode" "DI") |
| bb621ad7 | 3319 | (set_attr "length" "2,4,2,4,2,4,2,2")]) |
| 8ef30996 MM |
3320 | |
| 3321 | (define_split | |
| 3322 | [(set (match_operand:DI 0 "register_operand" "") | |
| 3323 | (match_operand:DI 1 "register_operand" ""))] | |
| bb621ad7 | 3324 | "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
3325 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 3326 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" | |
| 3327 | ||
| 3328 | [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) | |
| 3329 | (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))] | |
| 3330 | "") | |
| 3331 | ||
| bb621ad7 | 3332 | (define_insn "movdi_internal2" |
| 225b8835 ILT |
3333 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*x,*a") |
| 3334 | (match_operand:DI 1 "general_operand" " d,S,IKL,Mnis,R,m,dJ,dJ,*x,*d,*I"))] | |
| bb621ad7 JW |
3335 | "TARGET_64BIT |
| 3336 | && (register_operand (operands[0], DImode) | |
| 3337 | || register_operand (operands[1], DImode) | |
| 3338 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) | |
| 3339 | || operands[1] == CONST0_RTX (DImode))" | |
| 3340 | "* return mips_move_2words (operands, insn); " | |
| 225b8835 | 3341 | [(set_attr "type" "move,load,arith,arith,load,load,store,store,hilo,hilo,hilo") |
| bb621ad7 | 3342 | (set_attr "mode" "DI") |
| 225b8835 ILT |
3343 | (set_attr "length" "1,2,1,2,1,2,1,2,1,1,2")]) |
| 3344 | ||
| 3345 | ;; Handle input reloads in DImode. | |
| 3346 | ;; This is mainly to handle reloading HILO_REGNUM. Note that we may | |
| 3347 | ;; see it as the source or the destination, depending upon which way | |
| 3348 | ;; reload handles the instruction. | |
| 3349 | ;; Making the second operand TImode is a trick. The compiler may | |
| 3350 | ;; reuse the same register for operand 0 and operand 2. Using TImode | |
| 3351 | ;; gives us two registers, so we can always use the one which is not | |
| 3352 | ;; used. | |
| 3353 | ||
| 3354 | (define_expand "reload_indi" | |
| 3355 | [(set (match_operand:DI 0 "register_operand" "=b") | |
| 3356 | (match_operand:DI 1 "general_operand" "b")) | |
| 3357 | (clobber (match_operand:TI 2 "register_operand" "=&d"))] | |
| 3358 | "TARGET_64BIT" | |
| 3359 | " | |
| 3360 | { | |
| 3361 | rtx scratch = gen_rtx (REG, DImode, | |
| 3362 | (REGNO (operands[0]) == REGNO (operands[2]) | |
| 3363 | ? REGNO (operands[2]) + 1 | |
| 3364 | : REGNO (operands[2]))); | |
| 3365 | ||
| 3366 | if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM) | |
| 3367 | { | |
| 3368 | if (GET_CODE (operands[1]) == MEM) | |
| 3369 | { | |
| 3370 | rtx memword, offword, hiword, loword; | |
| 3371 | ||
| 3372 | scratch = gen_rtx (REG, SImode, REGNO (scratch)); | |
| 3373 | memword = change_address (operands[1], SImode, NULL_RTX); | |
| 3374 | offword = change_address (adj_offsettable_operand (operands[1], 4), | |
| 3375 | SImode, NULL_RTX); | |
| 3376 | if (BYTES_BIG_ENDIAN) | |
| 3377 | { | |
| 3378 | hiword = memword; | |
| 3379 | loword = offword; | |
| 3380 | } | |
| 3381 | else | |
| 3382 | { | |
| 3383 | hiword = offword; | |
| 3384 | loword = memword; | |
| 3385 | } | |
| 3386 | emit_move_insn (scratch, hiword); | |
| 3387 | emit_move_insn (gen_rtx (REG, SImode, 64), scratch); | |
| 3388 | emit_move_insn (scratch, loword); | |
| 3389 | emit_move_insn (gen_rtx (REG, SImode, 65), scratch); | |
| 3390 | } | |
| 3391 | else | |
| 3392 | { | |
| 3393 | emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32))); | |
| 3394 | emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch)); | |
| 3395 | emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32))); | |
| 3396 | emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32))); | |
| 3397 | emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch)); | |
| 3398 | } | |
| 3399 | DONE; | |
| 3400 | } | |
| 3401 | if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM) | |
| 3402 | { | |
| 3403 | emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65))); | |
| 3404 | emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32))); | |
| 3405 | emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32))); | |
| 3406 | emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64))); | |
| 3407 | emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32))); | |
| 3408 | emit_insn (gen_iordi3 (operands[0], operands[0], scratch)); | |
| 3409 | DONE; | |
| 3410 | } | |
| 3411 | /* This handles moves between a float register and HI/LO. */ | |
| 3412 | emit_move_insn (scratch, operands[1]); | |
| 3413 | emit_move_insn (operands[0], scratch); | |
| 3414 | DONE; | |
| 3415 | }") | |
| bb621ad7 | 3416 | |
| 225b8835 ILT |
3417 | ;; Handle output reloads in DImode. |
| 3418 | ||
| 3419 | (define_expand "reload_outdi" | |
| 3420 | [(set (match_operand:DI 0 "general_operand" "=b") | |
| 3421 | (match_operand:DI 1 "register_operand" "b")) | |
| 3422 | (clobber (match_operand:DI 2 "register_operand" "=&d"))] | |
| 3423 | "TARGET_64BIT" | |
| 3424 | " | |
| 3425 | { | |
| 3426 | if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM) | |
| 3427 | { | |
| 3428 | emit_insn (gen_ashrdi3 (operands[2], operands[1], GEN_INT (32))); | |
| 3429 | emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), operands[2])); | |
| 3430 | emit_insn (gen_ashldi3 (operands[2], operands[1], GEN_INT (32))); | |
| 3431 | emit_insn (gen_ashrdi3 (operands[2], operands[2], GEN_INT (32))); | |
| 3432 | emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), operands[2])); | |
| 3433 | DONE; | |
| 3434 | } | |
| 3435 | if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM) | |
| 3436 | { | |
| 3437 | if (GET_CODE (operands[0]) == MEM) | |
| 3438 | { | |
| 3439 | rtx scratch, memword, offword, hiword, loword; | |
| 3440 | ||
| 3441 | scratch = gen_rtx (REG, SImode, REGNO (operands[2])); | |
| 3442 | memword = change_address (operands[0], SImode, NULL_RTX); | |
| 3443 | offword = change_address (adj_offsettable_operand (operands[0], 4), | |
| 3444 | SImode, NULL_RTX); | |
| 3445 | if (BYTES_BIG_ENDIAN) | |
| 3446 | { | |
| 3447 | hiword = memword; | |
| 3448 | loword = offword; | |
| 3449 | } | |
| 3450 | else | |
| 3451 | { | |
| 3452 | hiword = offword; | |
| 3453 | loword = memword; | |
| 3454 | } | |
| 3455 | emit_move_insn (scratch, gen_rtx (REG, SImode, 64)); | |
| 3456 | emit_move_insn (hiword, scratch); | |
| 3457 | emit_move_insn (scratch, gen_rtx (REG, SImode, 65)); | |
| 3458 | emit_move_insn (loword, scratch); | |
| 3459 | } | |
| 3460 | else | |
| 3461 | { | |
| 3462 | emit_insn (gen_movdi (operands[2], gen_rtx (REG, DImode, 65))); | |
| 3463 | emit_insn (gen_ashldi3 (operands[2], operands[2], GEN_INT (32))); | |
| 3464 | emit_insn (gen_lshrdi3 (operands[2], operands[2], GEN_INT (32))); | |
| 3465 | emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64))); | |
| 3466 | emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32))); | |
| 3467 | emit_insn (gen_iordi3 (operands[0], operands[0], operands[2])); | |
| 3468 | } | |
| 3469 | DONE; | |
| 3470 | } | |
| 3471 | /* This handles moves between a float register and HI/LO. */ | |
| 3472 | emit_move_insn (operands[2], operands[1]); | |
| 3473 | emit_move_insn (operands[0], operands[2]); | |
| 3474 | DONE; | |
| 3475 | }") | |
| 8ef30996 MM |
3476 | |
| 3477 | ;; 32-bit Integer moves | |
| 3478 | ||
| 3479 | (define_split | |
| 3480 | [(set (match_operand:SI 0 "register_operand" "") | |
| 3481 | (match_operand:SI 1 "large_int" ""))] | |
| 26b8e6e5 | 3482 | "!TARGET_DEBUG_D_MODE" |
| 8ef30996 MM |
3483 | [(set (match_dup 0) |
| 3484 | (match_dup 2)) | |
| 3485 | (set (match_dup 0) | |
| 3486 | (ior:SI (match_dup 0) | |
| 3487 | (match_dup 3)))] | |
| 3488 | " | |
| 3489 | { | |
| 3490 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff0000); | |
| 3491 | operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0x0000ffff); | |
| 3492 | }") | |
| 3493 | ||
| 3494 | ;; Unlike most other insns, the move insns can't be split with | |
| 3495 | ;; different predicates, because register spilling and other parts of | |
| 3496 | ;; the compiler, have memoized the insn number already. | |
| 3497 | ||
| f3b39eba MM |
3498 | (define_expand "movsi" |
| 3499 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
| 3500 | (match_operand:SI 1 "general_operand" ""))] | |
| 3501 | "" | |
| ed50ab35 MM |
3502 | " |
| 3503 | { | |
| aa4e54c4 JW |
3504 | if (mips_split_addresses && mips_check_split (operands[1], SImode)) |
| 3505 | { | |
| 3506 | enum machine_mode mode = GET_MODE (operands[0]); | |
| 3507 | rtx tem = ((reload_in_progress | reload_completed) | |
| 3508 | ? operands[0] : gen_reg_rtx (mode)); | |
| 3509 | ||
| 3510 | emit_insn (gen_rtx (SET, VOIDmode, tem, | |
| 3511 | gen_rtx (HIGH, mode, operands[1]))); | |
| 3512 | ||
| 3513 | operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]); | |
| 3514 | } | |
| 3515 | ||
| 92544bdf ILT |
3516 | /* If we are generating embedded PIC code, and we are referring to a |
| 3517 | symbol in the .text section, we must use an offset from the start | |
| 3518 | of the function. */ | |
| 3519 | if (TARGET_EMBEDDED_PIC | |
| 3520 | && (GET_CODE (operands[1]) == LABEL_REF | |
| 3521 | || (GET_CODE (operands[1]) == SYMBOL_REF | |
| 3522 | && ! SYMBOL_REF_FLAG (operands[1])))) | |
| 3523 | { | |
| 3524 | rtx temp; | |
| 3525 | ||
| 3526 | temp = embedded_pic_offset (operands[1]); | |
| 3527 | temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx, | |
| 3528 | force_reg (SImode, temp)); | |
| 3529 | emit_move_insn (operands[0], force_reg (SImode, temp)); | |
| 3530 | DONE; | |
| 3531 | } | |
| 3532 | ||
| 3826a3da | 3533 | /* If operands[1] is a constant address invalid for pic, then we need to |
| 5a5b76a2 JW |
3534 | handle it just like LEGITIMIZE_ADDRESS does. */ |
| 3535 | if (flag_pic && pic_address_needs_scratch (operands[1])) | |
| 3536 | { | |
| 3537 | rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0)); | |
| 3538 | rtx temp2 = XEXP (XEXP (operands[1], 0), 1); | |
| 3539 | ||
| 3540 | if (! SMALL_INT (temp2)) | |
| 3541 | temp2 = force_reg (SImode, temp2); | |
| 3542 | ||
| 3543 | emit_move_insn (operands[0], gen_rtx (PLUS, SImode, temp, temp2)); | |
| 3544 | DONE; | |
| 3545 | } | |
| 3546 | ||
| ed50ab35 MM |
3547 | if ((reload_in_progress | reload_completed) == 0 |
| 3548 | && !register_operand (operands[0], SImode) | |
| 3549 | && !register_operand (operands[1], SImode) | |
| 3550 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)) | |
| 3551 | { | |
| 3552 | rtx temp = force_reg (SImode, operands[1]); | |
| 3553 | emit_move_insn (operands[0], temp); | |
| 3554 | DONE; | |
| 3555 | } | |
| 3556 | }") | |
| f3b39eba | 3557 | |
| 0fb5ac6f MM |
3558 | ;; The difference between these two is whether or not ints are allowed |
| 3559 | ;; in FP registers (off by default, use -mdebugh to enable). | |
| 3560 | ||
| 3561 | (define_insn "movsi_internal1" | |
| 225b8835 | 3562 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d") |
| aa4e54c4 | 3563 | (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,I,*d,*x,*a"))] |
| ed50ab35 MM |
3564 | "TARGET_DEBUG_H_MODE |
| 3565 | && (register_operand (operands[0], SImode) | |
| 3566 | || register_operand (operands[1], SImode) | |
| 3567 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| bb621ad7 | 3568 | "* return mips_move_1word (operands, insn, FALSE);" |
| 225b8835 | 3569 | [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo") |
| 92b4cee1 | 3570 | (set_attr "mode" "SI") |
| 225b8835 | 3571 | (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1,1,1")]) |
| 8ef30996 | 3572 | |
| 0fb5ac6f | 3573 | (define_insn "movsi_internal2" |
| 225b8835 | 3574 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d") |
| aa4e54c4 | 3575 | (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,I,*x,*d,*a"))] |
| ed50ab35 MM |
3576 | "!TARGET_DEBUG_H_MODE |
| 3577 | && (register_operand (operands[0], SImode) | |
| 3578 | || register_operand (operands[1], SImode) | |
| 3579 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| bb621ad7 | 3580 | "* return mips_move_1word (operands, insn, FALSE);" |
| 225b8835 | 3581 | [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo") |
| 0fb5ac6f | 3582 | (set_attr "mode" "SI") |
| 225b8835 | 3583 | (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,1,1")]) |
| 0fb5ac6f | 3584 | |
| 225b8835 ILT |
3585 | ;; Reload HILO_REGNUM in SI mode. This needs a scratch register in |
| 3586 | ;; order to set the sign bit correctly in the HI register. | |
| 3587 | ||
| 3588 | (define_expand "reload_outsi" | |
| 3589 | [(set (match_operand:SI 0 "general_operand" "=b") | |
| 3590 | (match_operand:SI 1 "register_operand" "d")) | |
| 3591 | (clobber (match_operand:SI 2 "register_operand" "=&d"))] | |
| 3592 | "TARGET_64BIT" | |
| 3593 | " | |
| 3594 | { | |
| 3595 | if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM) | |
| 3596 | { | |
| 3597 | emit_insn (gen_movsi (gen_rtx (REG, SImode, 65), operands[1])); | |
| 3598 | emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31))); | |
| 3599 | emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2])); | |
| 3600 | DONE; | |
| 3601 | } | |
| 3602 | /* This handles moves between a float register and HI/LO. */ | |
| 3603 | emit_move_insn (operands[2], operands[1]); | |
| 3604 | emit_move_insn (operands[0], operands[2]); | |
| 3605 | DONE; | |
| 3606 | }") | |
| 0fb5ac6f | 3607 | |
| b8eb88d0 ILT |
3608 | ;; This insn handles moving CCmode values. It's really just a |
| 3609 | ;; slightly simplified copy of movsi_internal2, with additional cases | |
| 3610 | ;; to move a condition register to a general register and to move | |
| 3611 | ;; between the general registers and the floating point registers. | |
| 3612 | ||
| 3613 | (define_insn "movcc" | |
| 3614 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m") | |
| 3615 | (match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))] | |
| 3616 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 3617 | "* return mips_move_1word (operands, insn, FALSE);" | |
| 3618 | [(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store") | |
| 3619 | (set_attr "mode" "SI") | |
| 3620 | (set_attr "length" "2,1,1,2,1,2,1,1,1,1,2,1,2")]) | |
| 3621 | ||
| 3622 | ;; Reload condition code registers. These need scratch registers. | |
| 3623 | ||
| 3624 | (define_expand "reload_incc" | |
| 3625 | [(set (match_operand:CC 0 "register_operand" "=z") | |
| 3626 | (match_operand:CC 1 "general_operand" "z")) | |
| 3627 | (clobber (match_operand:TF 2 "register_operand" "=&f"))] | |
| 3628 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 3629 | " | |
| 3630 | { | |
| 3631 | rtx source; | |
| 3632 | rtx fp1, fp2; | |
| 3633 | ||
| 3634 | /* This is called when are copying some value into a condition code | |
| 3635 | register. Operand 0 is the condition code register. Operand 1 | |
| 3636 | is the source. Operand 2 is a scratch register; we use TFmode | |
| 3637 | because we actually need two floating point registers. */ | |
| 3638 | if (! ST_REG_P (true_regnum (operands[0])) | |
| 3639 | || ! FP_REG_P (true_regnum (operands[2]))) | |
| 3640 | abort (); | |
| 3641 | ||
| 3642 | /* We need to get the source in SFmode so that the insn is | |
| 3643 | recognized. */ | |
| 3644 | if (GET_CODE (operands[1]) == MEM) | |
| 3645 | source = change_address (operands[1], SFmode, NULL_RTX); | |
| 3646 | else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG) | |
| 3647 | source = gen_rtx (REG, SFmode, true_regnum (operands[1])); | |
| 3648 | else | |
| 3649 | source = operands[1]; | |
| 3650 | ||
| 3651 | fp1 = gen_rtx (REG, SFmode, REGNO (operands[2])); | |
| 3652 | fp2 = gen_rtx (REG, SFmode, REGNO (operands[2]) + 1); | |
| 3653 | ||
| 3654 | emit_insn (gen_move_insn (fp1, source)); | |
| 3655 | emit_insn (gen_move_insn (fp2, gen_rtx (REG, SFmode, 0))); | |
| 3656 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
| 3657 | gen_rtx (LT, CCmode, fp2, fp1))); | |
| 3658 | ||
| 3659 | DONE; | |
| 3660 | }") | |
| 3661 | ||
| 3662 | (define_expand "reload_outcc" | |
| 3663 | [(set (match_operand:CC 0 "general_operand" "=z") | |
| 3664 | (match_operand:CC 1 "register_operand" "z")) | |
| 3665 | (clobber (match_operand:CC 2 "register_operand" "=&d"))] | |
| 3666 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 3667 | " | |
| 3668 | { | |
| 3669 | /* This is called when we are copying a condition code register out | |
| 3670 | to save it somewhere. Operand 0 should be the location we are | |
| 3671 | going to save it to. Operand 1 should be the condition code | |
| 3672 | register. Operand 2 should be a scratch general purpose register | |
| 3673 | created for us by reload. The mips_secondary_reload_class | |
| 3674 | function should have told reload that we don't need a scratch | |
| 3675 | register if the destination is a general purpose register anyhow. */ | |
| 3676 | if (ST_REG_P (true_regnum (operands[0])) | |
| 3677 | || GP_REG_P (true_regnum (operands[0])) | |
| 3678 | || ! ST_REG_P (true_regnum (operands[1])) | |
| 3679 | || ! GP_REG_P (true_regnum (operands[2]))) | |
| 3680 | abort (); | |
| 3681 | ||
| 3682 | /* All we have to do is copy the value from the condition code to | |
| 3683 | the data register, which movcc can handle, and then store the | |
| 3684 | value into the real final destination. */ | |
| 3685 | emit_insn (gen_move_insn (operands[2], operands[1])); | |
| 3686 | emit_insn (gen_move_insn (operands[0], operands[2])); | |
| 3687 | ||
| 3688 | DONE; | |
| 3689 | }") | |
| 3690 | ||
| 3691 | ;; MIPS4 supports loading and storing a floating point register from | |
| 3692 | ;; the sum of two general registers. We use two versions for each of | |
| 3693 | ;; these four instructions: one where the two general registers are | |
| 3694 | ;; SImode, and one where they are DImode. This is because general | |
| 3695 | ;; registers will be in SImode when they hold 32 bit values, but, | |
| 3696 | ;; since the 32 bit values are always sign extended, the [ls][wd]xc1 | |
| 3697 | ;; instructions will still work correctly. | |
| 3698 | ||
| 3699 | ;; ??? Perhaps it would be better to support these instructions by | |
| 3700 | ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since | |
| 3701 | ;; these instructions can only be used to load and store floating | |
| 3702 | ;; point registers, that would probably cause trouble in reload. | |
| 3703 | ||
| 3704 | (define_insn "" | |
| 3705 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 3706 | (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d") | |
| 3707 | (match_operand:SI 2 "register_operand" "d"))))] | |
| 3708 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 3709 | "lwxc1\\t%0,%1(%2)" | |
| 3710 | [(set_attr "type" "load") | |
| 3711 | (set_attr "mode" "SF") | |
| 3712 | (set_attr "length" "1")]) | |
| 3713 | ||
| 3714 | (define_insn "" | |
| 3715 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 3716 | (mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d") | |
| 3717 | (match_operand:DI 2 "register_operand" "d"))))] | |
| 3718 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 3719 | "lwxc1\\t%0,%1(%2)" | |
| 3720 | [(set_attr "type" "load") | |
| 3721 | (set_attr "mode" "SF") | |
| 3722 | (set_attr "length" "1")]) | |
| 3723 | ||
| 3724 | (define_insn "" | |
| 3725 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 3726 | (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") | |
| 3727 | (match_operand:SI 2 "register_operand" "d"))))] | |
| 3728 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" | |
| 3729 | "ldxc1\\t%0,%1(%2)" | |
| 3730 | [(set_attr "type" "load") | |
| 3731 | (set_attr "mode" "DF") | |
| 3732 | (set_attr "length" "1")]) | |
| 3733 | ||
| 3734 | (define_insn "" | |
| 3735 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 3736 | (mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d") | |
| 3737 | (match_operand:DI 2 "register_operand" "d"))))] | |
| 3738 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" | |
| 3739 | "ldxc1\\t%0,%1(%2)" | |
| 3740 | [(set_attr "type" "load") | |
| 3741 | (set_attr "mode" "DF") | |
| 3742 | (set_attr "length" "1")]) | |
| 3743 | ||
| 3744 | (define_insn "" | |
| 3745 | [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d") | |
| 3746 | (match_operand:SI 2 "register_operand" "d"))) | |
| 3747 | (match_operand:SF 0 "register_operand" "=f"))] | |
| 3748 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 3749 | "swxc1\\t%0,%1(%2)" | |
| 3750 | [(set_attr "type" "store") | |
| 3751 | (set_attr "mode" "SF") | |
| 3752 | (set_attr "length" "1")]) | |
| 3753 | ||
| 3754 | (define_insn "" | |
| 3755 | [(set (mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d") | |
| 3756 | (match_operand:DI 2 "register_operand" "d"))) | |
| 3757 | (match_operand:SF 0 "register_operand" "=f"))] | |
| 3758 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 3759 | "swxc1\\t%0,%1(%2)" | |
| 3760 | [(set_attr "type" "store") | |
| 3761 | (set_attr "mode" "SF") | |
| 3762 | (set_attr "length" "1")]) | |
| 3763 | ||
| 3764 | (define_insn "" | |
| 3765 | [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") | |
| 3766 | (match_operand:SI 2 "register_operand" "d"))) | |
| 3767 | (match_operand:DF 0 "register_operand" "=f"))] | |
| 3768 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" | |
| 3769 | "sdxc1\\t%0,%1(%2)" | |
| 3770 | [(set_attr "type" "store") | |
| 3771 | (set_attr "mode" "DF") | |
| 3772 | (set_attr "length" "1")]) | |
| 3773 | ||
| 3774 | (define_insn "" | |
| 3775 | [(set (mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d") | |
| 3776 | (match_operand:DI 2 "register_operand" "d"))) | |
| 3777 | (match_operand:DF 0 "register_operand" "=f"))] | |
| 3778 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" | |
| 3779 | "sdxc1\\t%0,%1(%2)" | |
| 3780 | [(set_attr "type" "store") | |
| 3781 | (set_attr "mode" "DF") | |
| 3782 | (set_attr "length" "1")]) | |
| 3783 | ||
| 8ef30996 MM |
3784 | ;; 16-bit Integer moves |
| 3785 | ||
| 3786 | ;; Unlike most other insns, the move insns can't be split with | |
| 3787 | ;; different predicates, because register spilling and other parts of | |
| 3788 | ;; the compiler, have memoized the insn number already. | |
| 3789 | ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined | |
| 3790 | ||
| 0fb5ac6f MM |
3791 | (define_expand "movhi" |
| 3792 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
| 3793 | (match_operand:HI 1 "general_operand" ""))] | |
| 8ef30996 | 3794 | "" |
| ed50ab35 MM |
3795 | " |
| 3796 | { | |
| 3797 | if ((reload_in_progress | reload_completed) == 0 | |
| 3798 | && !register_operand (operands[0], HImode) | |
| 3799 | && !register_operand (operands[1], HImode) | |
| 3800 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)) | |
| 3801 | { | |
| 3802 | rtx temp = force_reg (HImode, operands[1]); | |
| 3803 | emit_move_insn (operands[0], temp); | |
| 3804 | DONE; | |
| 3805 | } | |
| 3806 | }") | |
| 0fb5ac6f MM |
3807 | |
| 3808 | ;; The difference between these two is whether or not ints are allowed | |
| 3809 | ;; in FP registers (off by default, use -mdebugh to enable). | |
| 3810 | ||
| 3811 | (define_insn "movhi_internal1" | |
| 252e25c6 MM |
3812 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d") |
| 3813 | (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))] | |
| ed50ab35 MM |
3814 | "TARGET_DEBUG_H_MODE |
| 3815 | && (register_operand (operands[0], HImode) | |
| 3816 | || register_operand (operands[1], HImode) | |
| 3817 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 8ef30996 MM |
3818 | "* return mips_move_1word (operands, insn, TRUE);" |
| 3819 | [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo") | |
| 92b4cee1 | 3820 | (set_attr "mode" "HI") |
| 8ef30996 MM |
3821 | (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")]) |
| 3822 | ||
| 0fb5ac6f MM |
3823 | (define_insn "movhi_internal2" |
| 3824 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d") | |
| 3825 | (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))] | |
| ed50ab35 MM |
3826 | "!TARGET_DEBUG_H_MODE |
| 3827 | && (register_operand (operands[0], HImode) | |
| 3828 | || register_operand (operands[1], HImode) | |
| 3829 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 0fb5ac6f MM |
3830 | "* return mips_move_1word (operands, insn, TRUE);" |
| 3831 | [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo") | |
| 3832 | (set_attr "mode" "HI") | |
| 3833 | (set_attr "length" "1,1,1,2,1,2,1,1,1,1")]) | |
| 3834 | ||
| 3835 | ||
| 8ef30996 MM |
3836 | ;; 8-bit Integer moves |
| 3837 | ||
| 3838 | ;; Unlike most other insns, the move insns can't be split with | |
| 3839 | ;; different predicates, because register spilling and other parts of | |
| 3840 | ;; the compiler, have memoized the insn number already. | |
| 3841 | ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined | |
| 3842 | ||
| 0fb5ac6f MM |
3843 | (define_expand "movqi" |
| 3844 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 3845 | (match_operand:QI 1 "general_operand" ""))] | |
| 8ef30996 | 3846 | "" |
| ed50ab35 MM |
3847 | " |
| 3848 | { | |
| 3849 | if ((reload_in_progress | reload_completed) == 0 | |
| 3850 | && !register_operand (operands[0], QImode) | |
| 3851 | && !register_operand (operands[1], QImode) | |
| 3852 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)) | |
| 3853 | { | |
| 3854 | rtx temp = force_reg (QImode, operands[1]); | |
| 3855 | emit_move_insn (operands[0], temp); | |
| 3856 | DONE; | |
| 3857 | } | |
| 3858 | }") | |
| 0fb5ac6f MM |
3859 | |
| 3860 | ;; The difference between these two is whether or not ints are allowed | |
| 3861 | ;; in FP registers (off by default, use -mdebugh to enable). | |
| 3862 | ||
| 3863 | (define_insn "movqi_internal1" | |
| 252e25c6 MM |
3864 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d") |
| 3865 | (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))] | |
| ed50ab35 MM |
3866 | "TARGET_DEBUG_H_MODE |
| 3867 | && (register_operand (operands[0], QImode) | |
| 3868 | || register_operand (operands[1], QImode) | |
| 3869 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 8ef30996 MM |
3870 | "* return mips_move_1word (operands, insn, TRUE);" |
| 3871 | [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo") | |
| 92b4cee1 | 3872 | (set_attr "mode" "QI") |
| 8ef30996 MM |
3873 | (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")]) |
| 3874 | ||
| 0fb5ac6f MM |
3875 | (define_insn "movqi_internal2" |
| 3876 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d") | |
| 3877 | (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))] | |
| ed50ab35 MM |
3878 | "!TARGET_DEBUG_H_MODE |
| 3879 | && (register_operand (operands[0], QImode) | |
| 3880 | || register_operand (operands[1], QImode) | |
| 3881 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 0fb5ac6f MM |
3882 | "* return mips_move_1word (operands, insn, TRUE);" |
| 3883 | [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo") | |
| 3884 | (set_attr "mode" "QI") | |
| 3885 | (set_attr "length" "1,1,1,2,1,2,1,1,1,1")]) | |
| 3886 | ||
| 8ef30996 MM |
3887 | |
| 3888 | ;; 32-bit floating point moves | |
| 3889 | ||
| ed50ab35 MM |
3890 | (define_expand "movsf" |
| 3891 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
| 3892 | (match_operand:SF 1 "general_operand" ""))] | |
| 3893 | "" | |
| 3894 | " | |
| 3895 | { | |
| 3896 | if ((reload_in_progress | reload_completed) == 0 | |
| 3897 | && !register_operand (operands[0], SFmode) | |
| 3898 | && !register_operand (operands[1], SFmode) | |
| 3899 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) | |
| 3900 | && operands[1] != CONST0_RTX (SFmode)) | |
| 3901 | { | |
| 3902 | rtx temp = force_reg (SFmode, operands[1]); | |
| 3903 | emit_move_insn (operands[0], temp); | |
| 3904 | DONE; | |
| 3905 | } | |
| 3906 | }") | |
| 3907 | ||
| b0193a92 | 3908 | (define_insn "movsf_internal1" |
| 8ef30996 | 3909 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m") |
| bb621ad7 | 3910 | (match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))] |
| b0193a92 MM |
3911 | "TARGET_HARD_FLOAT |
| 3912 | && (register_operand (operands[0], SFmode) | |
| 3913 | || register_operand (operands[1], SFmode) | |
| 3914 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) | |
| 3915 | || operands[1] == CONST0_RTX (SFmode))" | |
| 8ef30996 MM |
3916 | "* return mips_move_1word (operands, insn, FALSE);" |
| 3917 | [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store") | |
| 92b4cee1 | 3918 | (set_attr "mode" "SF") |
| 8ef30996 MM |
3919 | (set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")]) |
| 3920 | ||
| ed50ab35 | 3921 | |
| b0193a92 MM |
3922 | (define_insn "movsf_internal2" |
| 3923 | [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m") | |
| bb621ad7 | 3924 | (match_operand:SF 1 "general_operand" " Gd,R,Fm,d,d"))] |
| b0193a92 MM |
3925 | "TARGET_SOFT_FLOAT |
| 3926 | && (register_operand (operands[0], SFmode) | |
| 3927 | || register_operand (operands[1], SFmode) | |
| 3928 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) | |
| 3929 | || operands[1] == CONST0_RTX (SFmode))" | |
| 3930 | "* return mips_move_1word (operands, insn, FALSE);" | |
| 3931 | [(set_attr "type" "move,load,load,store,store") | |
| 3932 | (set_attr "mode" "SF") | |
| 3933 | (set_attr "length" "1,1,2,1,2")]) | |
| 3934 | ||
| 3935 | ||
| 8ef30996 MM |
3936 | ;; 64-bit floating point moves |
| 3937 | ||
| ed50ab35 MM |
3938 | (define_expand "movdf" |
| 3939 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
| 3940 | (match_operand:DF 1 "general_operand" ""))] | |
| 3941 | "" | |
| 3942 | " | |
| 3943 | { | |
| 3944 | if ((reload_in_progress | reload_completed) == 0 | |
| 3945 | && !register_operand (operands[0], DFmode) | |
| 3946 | && !register_operand (operands[1], DFmode) | |
| 3947 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) | |
| 3948 | && operands[1] != CONST0_RTX (DFmode)) | |
| 3949 | { | |
| 3950 | rtx temp = force_reg (DFmode, operands[1]); | |
| 3951 | emit_move_insn (operands[0], temp); | |
| 3952 | DONE; | |
| 3953 | } | |
| 3954 | }") | |
| 3955 | ||
| b0193a92 | 3956 | (define_insn "movdf_internal1" |
| 8ef30996 | 3957 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,o,f,*f,*d,*d,*d,*d,*R,*o") |
| bb621ad7 | 3958 | (match_operand:DF 1 "general_operand" "f,R,o,fG,fG,F,*d,*f,*d*G,*R,*o*F,*d,*d"))] |
| 64d8baf9 | 3959 | "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT) |
| 46299de9 | 3960 | && TARGET_DOUBLE_FLOAT |
| b0193a92 MM |
3961 | && (register_operand (operands[0], DFmode) |
| 3962 | || register_operand (operands[1], DFmode) | |
| 3963 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) | |
| 3964 | || operands[1] == CONST0_RTX (DFmode))" | |
| 8ef30996 MM |
3965 | "* return mips_move_2words (operands, insn); " |
| 3966 | [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store") | |
| 92b4cee1 | 3967 | (set_attr "mode" "DF") |
| 8ef30996 MM |
3968 | (set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")]) |
| 3969 | ||
| 64d8baf9 JW |
3970 | (define_insn "movdf_internal1a" |
| 3971 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,o,o,f,*d,*d,*d,*o,*R") | |
| 3972 | (match_operand:DF 1 "general_operand" " f,o,f,G,f,G,F,*F,*o,*R,*d,*d"))] | |
| 3973 | "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT) | |
| 46299de9 | 3974 | && TARGET_DOUBLE_FLOAT |
| 64d8baf9 JW |
3975 | && (register_operand (operands[0], DFmode) |
| 3976 | || register_operand (operands[1], DFmode)) | |
| 3977 | || (GET_CODE (operands [0]) == MEM | |
| 3978 | && ((GET_CODE (operands[1]) == CONST_INT | |
| 3979 | && INTVAL (operands[1]) == 0) | |
| 3980 | || operands[1] == CONST0_RTX (DFmode)))" | |
| 3981 | "* return mips_move_2words (operands, insn); " | |
| 3982 | [(set_attr "type" "move,load,store,store,store,store,load,load,load,load,store,store") | |
| 3983 | (set_attr "mode" "DF") | |
| 3984 | (set_attr "length" "1,2,1,1,2,2,2,2,2,1,2,1")]) | |
| 3985 | ||
| b0193a92 MM |
3986 | (define_insn "movdf_internal2" |
| 3987 | [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,o") | |
| bb621ad7 | 3988 | (match_operand:DF 1 "general_operand" "dG,R,oF,d,d"))] |
| 46299de9 | 3989 | "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) |
| b0193a92 MM |
3990 | && (register_operand (operands[0], DFmode) |
| 3991 | || register_operand (operands[1], DFmode) | |
| 3992 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) | |
| 3993 | || operands[1] == CONST0_RTX (DFmode))" | |
| 3994 | "* return mips_move_2words (operands, insn); " | |
| 3995 | [(set_attr "type" "move,load,load,store,store") | |
| 3996 | (set_attr "mode" "DF") | |
| 3997 | (set_attr "length" "2,2,4,2,4")]) | |
| 3998 | ||
| 8ef30996 MM |
3999 | (define_split |
| 4000 | [(set (match_operand:DF 0 "register_operand" "") | |
| 4001 | (match_operand:DF 1 "register_operand" ""))] | |
| 2c14c928 | 4002 | "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4003 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
| 4004 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" | |
| 8ef30996 MM |
4005 | [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) |
| 4006 | (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))] | |
| 4007 | "") | |
| 4008 | ||
| e19ff60f JW |
4009 | ;; Instructions to load the global pointer register. |
| 4010 | ;; This is volatile to make sure that the scheduler won't move any symbol_ref | |
| 4011 | ;; uses in front of it. All symbol_refs implicitly use the gp reg. | |
| 4012 | ||
| 4013 | (define_insn "loadgp" | |
| 4014 | [(set (reg:DI 28) | |
| 4015 | (unspec_volatile [(match_operand:DI 0 "address_operand" "")] 2)) | |
| 4016 | (clobber (reg:DI 1))] | |
| 4017 | "" | |
| 4018 | "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,$25%]" | |
| 4019 | [(set_attr "type" "move") | |
| 4020 | (set_attr "mode" "DI") | |
| 4021 | (set_attr "length" "3")]) | |
| 26b8e6e5 | 4022 | \f |
| 8ef30996 MM |
4023 | ;; Block moves, see mips.c for more details. |
| 4024 | ;; Argument 0 is the destination | |
| 4025 | ;; Argument 1 is the source | |
| 4026 | ;; Argument 2 is the length | |
| 4027 | ;; Argument 3 is the alignment | |
| 4028 | ||
| 4029 | (define_expand "movstrsi" | |
| 4030 | [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "")) | |
| 4031 | (mem:BLK (match_operand:BLK 1 "general_operand" ""))) | |
| 4032 | (use (match_operand:SI 2 "arith32_operand" "")) | |
| 4033 | (use (match_operand:SI 3 "immediate_operand" ""))])] | |
| 4034 | "" | |
| 4035 | " | |
| 4036 | { | |
| 4037 | if (operands[0]) /* avoid unused code messages */ | |
| 4038 | { | |
| 4039 | expand_block_move (operands); | |
| 4040 | DONE; | |
| 4041 | } | |
| 4042 | }") | |
| 4043 | ||
| 842eb20e MM |
4044 | ;; Insn generated by block moves |
| 4045 | ||
| 4046 | (define_insn "movstrsi_internal" | |
| aa4e54c4 JW |
4047 | [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination |
| 4048 | (match_operand:BLK 1 "memory_operand" "o")) ;; source | |
| 26b8e6e5 MM |
4049 | (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 |
| 4050 | (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 | |
| 4051 | (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 | |
| 4052 | (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 | |
| 4053 | (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move | |
| 4054 | (use (match_operand:SI 3 "small_int" "I")) ;; alignment | |
| 4055 | (use (const_int 0))] ;; normal block move | |
| 4056 | "" | |
| 4057 | "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);" | |
| 842eb20e MM |
4058 | [(set_attr "type" "multi") |
| 4059 | (set_attr "mode" "none") | |
| 4060 | (set_attr "length" "20")]) | |
| 4061 | ||
| 26b8e6e5 MM |
4062 | ;; Split a block move into 2 parts, the first part is everything |
| 4063 | ;; except for the last move, and the second part is just the last | |
| 4064 | ;; store, which is exactly 1 instruction (ie, not a usw), so it can | |
| 4065 | ;; fill a delay slot. This also prevents a bug in delayed branches | |
| 4066 | ;; from showing up, which reuses one of the registers in our clobbers. | |
| 4067 | ||
| 4068 | (define_split | |
| 4069 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "")) | |
| 4070 | (mem:BLK (match_operand:SI 1 "register_operand" ""))) | |
| 4071 | (clobber (match_operand:SI 4 "register_operand" "")) | |
| 4072 | (clobber (match_operand:SI 5 "register_operand" "")) | |
| 4073 | (clobber (match_operand:SI 6 "register_operand" "")) | |
| 4074 | (clobber (match_operand:SI 7 "register_operand" "")) | |
| 4075 | (use (match_operand:SI 2 "small_int" "")) | |
| 4076 | (use (match_operand:SI 3 "small_int" "")) | |
| 4077 | (use (const_int 0))] | |
| 4078 | ||
| 4079 | "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0" | |
| 4080 | ||
| 4081 | ;; All but the last move | |
| 4082 | [(parallel [(set (mem:BLK (match_dup 0)) | |
| 4083 | (mem:BLK (match_dup 1))) | |
| 4084 | (clobber (match_dup 4)) | |
| 4085 | (clobber (match_dup 5)) | |
| 4086 | (clobber (match_dup 6)) | |
| 4087 | (clobber (match_dup 7)) | |
| 4088 | (use (match_dup 2)) | |
| 4089 | (use (match_dup 3)) | |
| 4090 | (use (const_int 1))]) | |
| 4091 | ||
| 4092 | ;; The last store, so it can fill a delay slot | |
| 4093 | (parallel [(set (mem:BLK (match_dup 0)) | |
| 4094 | (mem:BLK (match_dup 1))) | |
| 4095 | (clobber (match_dup 4)) | |
| 4096 | (clobber (match_dup 5)) | |
| 4097 | (clobber (match_dup 6)) | |
| 4098 | (clobber (match_dup 7)) | |
| 4099 | (use (match_dup 2)) | |
| 4100 | (use (match_dup 3)) | |
| 4101 | (use (const_int 2))])] | |
| 4102 | ||
| 4103 | "") | |
| 4104 | ||
| 4105 | (define_insn "movstrsi_internal2" | |
| aa4e54c4 JW |
4106 | [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination |
| 4107 | (match_operand:BLK 1 "memory_operand" "o")) ;; source | |
| 26b8e6e5 MM |
4108 | (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 |
| 4109 | (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 | |
| 4110 | (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 | |
| 4111 | (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 | |
| 4112 | (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move | |
| 4113 | (use (match_operand:SI 3 "small_int" "I")) ;; alignment | |
| 4114 | (use (const_int 1))] ;; all but last store | |
| 4115 | "" | |
| 4116 | "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);" | |
| 4117 | [(set_attr "type" "multi") | |
| 4118 | (set_attr "mode" "none") | |
| 4119 | (set_attr "length" "20")]) | |
| 4120 | ||
| 4121 | (define_insn "movstrsi_internal3" | |
| 4122 | [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination | |
| 4123 | (match_operand:BLK 1 "memory_operand" "Ro")) ;; source | |
| 4124 | (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 | |
| 4125 | (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 | |
| 4126 | (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 | |
| 4127 | (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 | |
| 4128 | (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move | |
| 4129 | (use (match_operand:SI 3 "small_int" "I")) ;; alignment | |
| bb621ad7 | 4130 | (use (const_int 2))] ;; just last store of block move |
| 26b8e6e5 MM |
4131 | "" |
| 4132 | "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);" | |
| 4133 | [(set_attr "type" "store") | |
| 4134 | (set_attr "mode" "none") | |
| 4135 | (set_attr "length" "1")]) | |
| 4136 | ||
| 8ef30996 MM |
4137 | \f |
| 4138 | ;; | |
| 4139 | ;; .................... | |
| 4140 | ;; | |
| 4141 | ;; SHIFTS | |
| 4142 | ;; | |
| 4143 | ;; .................... | |
| 4144 | ||
| 4145 | (define_insn "ashlsi3" | |
| 4146 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4147 | (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
| 4148 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 4149 | "" | |
| 4150 | "* | |
| 4151 | { | |
| 4152 | if (GET_CODE (operands[2]) == CONST_INT) | |
| e19ff60f | 4153 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f); |
| 8ef30996 MM |
4154 | |
| 4155 | return \"sll\\t%0,%1,%2\"; | |
| 4156 | }" | |
| 4157 | [(set_attr "type" "arith") | |
| 4158 | (set_attr "mode" "SI") | |
| 4159 | (set_attr "length" "1")]) | |
| 4160 | ||
| 4161 | ||
| 4162 | (define_expand "ashldi3" | |
| 4163 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
| 4164 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
| 4165 | (match_operand:SI 2 "arith_operand" ""))) | |
| 4166 | (clobber (match_dup 3))])] | |
| bb621ad7 JW |
4167 | "TARGET_64BIT || !TARGET_DEBUG_G_MODE" |
| 4168 | " | |
| 4169 | { | |
| 4170 | if (TARGET_64BIT) | |
| 4171 | { | |
| 4172 | emit_insn (gen_ashldi3_internal4 (operands[0], operands[1], | |
| 4173 | operands[2])); | |
| 4174 | DONE; | |
| 4175 | } | |
| 4176 | ||
| 4177 | operands[3] = gen_reg_rtx (SImode); | |
| 4178 | }") | |
| 8ef30996 MM |
4179 | |
| 4180 | ||
| 4181 | (define_insn "ashldi3_internal" | |
| 0fb5ac6f | 4182 | [(set (match_operand:DI 0 "register_operand" "=&d") |
| 8ef30996 MM |
4183 | (ashift:DI (match_operand:DI 1 "register_operand" "d") |
| 4184 | (match_operand:SI 2 "register_operand" "d"))) | |
| 4185 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 4186 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE" |
| 8ef30996 MM |
4187 | "* |
| 4188 | { | |
| 4189 | operands[4] = const0_rtx; | |
| 4190 | dslots_jump_total += 3; | |
| 4191 | dslots_jump_filled += 2; | |
| 4192 | ||
| 4193 | return \"sll\\t%3,%2,26\\n\\ | |
| 4194 | \\tbgez\\t%3,1f\\n\\ | |
| 4195 | \\tsll\\t%M0,%L1,%2\\n\\ | |
| 4196 | \\t%(b\\t3f\\n\\ | |
| 4197 | \\tmove\\t%L0,%z4%)\\n\\ | |
| 4198 | \\n\\ | |
| 4199 | 1:\\n\\ | |
| 4200 | \\t%(beq\\t%3,%z4,2f\\n\\ | |
| 4201 | \\tsll\\t%M0,%M1,%2%)\\n\\ | |
| 4202 | \\n\\ | |
| 4203 | \\tsubu\\t%3,%z4,%2\\n\\ | |
| 4204 | \\tsrl\\t%3,%L1,%3\\n\\ | |
| 4205 | \\tor\\t%M0,%M0,%3\\n\\ | |
| 4206 | 2:\\n\\ | |
| 4207 | \\tsll\\t%L0,%L1,%2\\n\\ | |
| 4208 | 3:\"; | |
| 4209 | }" | |
| 4210 | [(set_attr "type" "darith") | |
| 4211 | (set_attr "mode" "SI") | |
| 4212 | (set_attr "length" "12")]) | |
| 4213 | ||
| 4214 | ||
| 4215 | (define_insn "ashldi3_internal2" | |
| 4216 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4217 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
| 4218 | (match_operand:SI 2 "small_int" "IJK"))) | |
| 4219 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 4220 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0" |
| 8ef30996 MM |
4221 | "* |
| 4222 | { | |
| e19ff60f | 4223 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f); |
| 8ef30996 MM |
4224 | operands[4] = const0_rtx; |
| 4225 | return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\"; | |
| 4226 | }" | |
| 4227 | [(set_attr "type" "darith") | |
| 4228 | (set_attr "mode" "DI") | |
| 4229 | (set_attr "length" "2")]) | |
| 4230 | ||
| 4231 | ||
| 4232 | (define_split | |
| 4233 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4234 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
| 4235 | (match_operand:SI 2 "small_int" ""))) | |
| 4236 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4237 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4238 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4239 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4240 | && (INTVAL (operands[2]) & 32) != 0" | |
| 4241 | ||
| 4242 | [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) | |
| 4243 | (set (subreg:SI (match_dup 0) 0) (const_int 0))] | |
| 4244 | ||
| e19ff60f | 4245 | "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);") |
| 8ef30996 MM |
4246 | |
| 4247 | ||
| 4248 | (define_split | |
| 4249 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4250 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
| 4251 | (match_operand:SI 2 "small_int" ""))) | |
| 4252 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4253 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4254 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4255 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4256 | && (INTVAL (operands[2]) & 32) != 0" | |
| 4257 | ||
| 4258 | [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2))) | |
| 4259 | (set (subreg:SI (match_dup 0) 1) (const_int 0))] | |
| 4260 | ||
| e19ff60f | 4261 | "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);") |
| 8ef30996 MM |
4262 | |
| 4263 | ||
| 4264 | (define_insn "ashldi3_internal3" | |
| 4265 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4266 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
| 4267 | (match_operand:SI 2 "small_int" "IJK"))) | |
| 4268 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 4269 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4270 | && (INTVAL (operands[2]) & 63) < 32 |
| 4271 | && (INTVAL (operands[2]) & 63) != 0" | |
| 4272 | "* | |
| 4273 | { | |
| 4274 | int amount = INTVAL (operands[2]); | |
| 4275 | ||
| 4276 | operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31)); | |
| 4277 | operands[4] = const0_rtx; | |
| 4278 | operands[5] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31)); | |
| 4279 | ||
| 4280 | return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\"; | |
| 4281 | }" | |
| 4282 | [(set_attr "type" "darith") | |
| 4283 | (set_attr "mode" "DI") | |
| 4284 | (set_attr "length" "4")]) | |
| 4285 | ||
| 4286 | ||
| 4287 | (define_split | |
| 4288 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4289 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
| 4290 | (match_operand:SI 2 "small_int" ""))) | |
| 4291 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4292 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4293 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4294 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4295 | && (INTVAL (operands[2]) & 63) < 32 | |
| 4296 | && (INTVAL (operands[2]) & 63) != 0" | |
| 4297 | ||
| 4298 | [(set (subreg:SI (match_dup 0) 1) | |
| 4299 | (ashift:SI (subreg:SI (match_dup 1) 1) | |
| 4300 | (match_dup 2))) | |
| 4301 | ||
| 4302 | (set (match_dup 3) | |
| 4303 | (lshiftrt:SI (subreg:SI (match_dup 1) 0) | |
| 4304 | (match_dup 4))) | |
| 4305 | ||
| 4306 | (set (subreg:SI (match_dup 0) 1) | |
| 4307 | (ior:SI (subreg:SI (match_dup 0) 1) | |
| 4308 | (match_dup 3))) | |
| 4309 | ||
| 4310 | (set (subreg:SI (match_dup 0) 0) | |
| 4311 | (ashift:SI (subreg:SI (match_dup 1) 0) | |
| 4312 | (match_dup 2)))] | |
| 4313 | " | |
| 4314 | { | |
| 4315 | int amount = INTVAL (operands[2]); | |
| 4316 | operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31)); | |
| 4317 | operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31)); | |
| 4318 | }") | |
| 4319 | ||
| 4320 | ||
| 4321 | (define_split | |
| 4322 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4323 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
| 4324 | (match_operand:SI 2 "small_int" ""))) | |
| 4325 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4326 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4327 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4328 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4329 | && (INTVAL (operands[2]) & 63) < 32 | |
| 4330 | && (INTVAL (operands[2]) & 63) != 0" | |
| 4331 | ||
| 4332 | [(set (subreg:SI (match_dup 0) 0) | |
| 4333 | (ashift:SI (subreg:SI (match_dup 1) 0) | |
| 4334 | (match_dup 2))) | |
| 4335 | ||
| 4336 | (set (match_dup 3) | |
| 4337 | (lshiftrt:SI (subreg:SI (match_dup 1) 1) | |
| 4338 | (match_dup 4))) | |
| 4339 | ||
| 4340 | (set (subreg:SI (match_dup 0) 0) | |
| 4341 | (ior:SI (subreg:SI (match_dup 0) 0) | |
| 4342 | (match_dup 3))) | |
| 4343 | ||
| 4344 | (set (subreg:SI (match_dup 0) 1) | |
| 4345 | (ashift:SI (subreg:SI (match_dup 1) 1) | |
| 4346 | (match_dup 2)))] | |
| 4347 | " | |
| 4348 | { | |
| 4349 | int amount = INTVAL (operands[2]); | |
| 4350 | operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31)); | |
| 4351 | operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31)); | |
| 4352 | }") | |
| 4353 | ||
| 4354 | ||
| bb621ad7 JW |
4355 | (define_insn "ashldi3_internal4" |
| 4356 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4357 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
| 4358 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 4359 | "TARGET_64BIT" | |
| 4360 | "* | |
| 4361 | { | |
| 4362 | if (GET_CODE (operands[2]) == CONST_INT) | |
| 4363 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); | |
| 4364 | ||
| 4365 | return \"dsll\\t%0,%1,%2\"; | |
| 4366 | }" | |
| 4367 | [(set_attr "type" "arith") | |
| 4368 | (set_attr "mode" "DI") | |
| 4369 | (set_attr "length" "1")]) | |
| 4370 | ||
| 4371 | ||
| 8ef30996 MM |
4372 | (define_insn "ashrsi3" |
| 4373 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4374 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 4375 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 4376 | "" | |
| 4377 | "* | |
| 4378 | { | |
| 4379 | if (GET_CODE (operands[2]) == CONST_INT) | |
| e19ff60f | 4380 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f); |
| 8ef30996 MM |
4381 | |
| 4382 | return \"sra\\t%0,%1,%2\"; | |
| 4383 | }" | |
| 4384 | [(set_attr "type" "arith") | |
| 4385 | (set_attr "mode" "SI") | |
| 4386 | (set_attr "length" "1")]) | |
| 4387 | ||
| 4388 | ||
| 4389 | (define_expand "ashrdi3" | |
| 4390 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
| 4391 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4392 | (match_operand:SI 2 "arith_operand" ""))) | |
| 4393 | (clobber (match_dup 3))])] | |
| bb621ad7 JW |
4394 | "TARGET_64BIT || !TARGET_DEBUG_G_MODE" |
| 4395 | " | |
| 4396 | { | |
| 4397 | if (TARGET_64BIT) | |
| 4398 | { | |
| 4399 | emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1], | |
| 4400 | operands[2])); | |
| 4401 | DONE; | |
| 4402 | } | |
| 4403 | ||
| 4404 | operands[3] = gen_reg_rtx (SImode); | |
| 4405 | }") | |
| 8ef30996 MM |
4406 | |
| 4407 | ||
| 4408 | (define_insn "ashrdi3_internal" | |
| 0fb5ac6f | 4409 | [(set (match_operand:DI 0 "register_operand" "=&d") |
| 8ef30996 MM |
4410 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
| 4411 | (match_operand:SI 2 "register_operand" "d"))) | |
| 4412 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 4413 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE" |
| 8ef30996 MM |
4414 | "* |
| 4415 | { | |
| 4416 | operands[4] = const0_rtx; | |
| 4417 | dslots_jump_total += 3; | |
| 4418 | dslots_jump_filled += 2; | |
| 4419 | ||
| 4420 | return \"sll\\t%3,%2,26\\n\\ | |
| 4421 | \\tbgez\\t%3,1f\\n\\ | |
| 4422 | \\tsra\\t%L0,%M1,%2\\n\\ | |
| 4423 | \\t%(b\\t3f\\n\\ | |
| 4424 | \\tsra\\t%M0,%M1,31%)\\n\\ | |
| 4425 | \\n\\ | |
| 4426 | 1:\\n\\ | |
| 4427 | \\t%(beq\\t%3,%z4,2f\\n\\ | |
| 4428 | \\tsrl\\t%L0,%L1,%2%)\\n\\ | |
| 4429 | \\n\\ | |
| 4430 | \\tsubu\\t%3,%z4,%2\\n\\ | |
| 4431 | \\tsll\\t%3,%M1,%3\\n\\ | |
| 4432 | \\tor\\t%L0,%L0,%3\\n\\ | |
| 4433 | 2:\\n\\ | |
| 4434 | \\tsra\\t%M0,%M1,%2\\n\\ | |
| 4435 | 3:\"; | |
| 4436 | }" | |
| 4437 | [(set_attr "type" "darith") | |
| 4438 | (set_attr "mode" "DI") | |
| 4439 | (set_attr "length" "12")]) | |
| 4440 | ||
| 4441 | ||
| 4442 | (define_insn "ashrdi3_internal2" | |
| 4443 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4444 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 4445 | (match_operand:SI 2 "small_int" "IJK"))) | |
| 4446 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 4447 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0" |
| 8ef30996 MM |
4448 | "* |
| 4449 | { | |
| e19ff60f | 4450 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f); |
| 8ef30996 MM |
4451 | return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\"; |
| 4452 | }" | |
| 4453 | [(set_attr "type" "darith") | |
| 4454 | (set_attr "mode" "DI") | |
| 4455 | (set_attr "length" "2")]) | |
| 4456 | ||
| 4457 | ||
| 4458 | (define_split | |
| 4459 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4460 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4461 | (match_operand:SI 2 "small_int" ""))) | |
| 4462 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4463 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4464 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4465 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4466 | && (INTVAL (operands[2]) & 32) != 0" | |
| 4467 | ||
| 4468 | [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2))) | |
| 4469 | (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))] | |
| 4470 | ||
| e19ff60f | 4471 | "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);") |
| 8ef30996 MM |
4472 | |
| 4473 | ||
| 4474 | (define_split | |
| 4475 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4476 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4477 | (match_operand:SI 2 "small_int" ""))) | |
| 4478 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4479 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4480 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4481 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4482 | && (INTVAL (operands[2]) & 32) != 0" | |
| 4483 | ||
| 4484 | [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) | |
| 4485 | (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))] | |
| 4486 | ||
| e19ff60f | 4487 | "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);") |
| 8ef30996 MM |
4488 | |
| 4489 | ||
| 4490 | (define_insn "ashrdi3_internal3" | |
| 4491 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4492 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 4493 | (match_operand:SI 2 "small_int" "IJK"))) | |
| 4494 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 4495 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4496 | && (INTVAL (operands[2]) & 63) < 32 |
| 4497 | && (INTVAL (operands[2]) & 63) != 0" | |
| 4498 | "* | |
| 4499 | { | |
| 4500 | int amount = INTVAL (operands[2]); | |
| 4501 | ||
| 4502 | operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31)); | |
| 4503 | operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31)); | |
| 4504 | ||
| 4505 | return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\"; | |
| 4506 | }" | |
| 4507 | [(set_attr "type" "darith") | |
| 4508 | (set_attr "mode" "DI") | |
| 4509 | (set_attr "length" "4")]) | |
| 4510 | ||
| 4511 | ||
| 4512 | (define_split | |
| 4513 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4514 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4515 | (match_operand:SI 2 "small_int" ""))) | |
| 4516 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4517 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4518 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4519 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4520 | && (INTVAL (operands[2]) & 63) < 32 | |
| 4521 | && (INTVAL (operands[2]) & 63) != 0" | |
| 4522 | ||
| 4523 | [(set (subreg:SI (match_dup 0) 0) | |
| 4524 | (lshiftrt:SI (subreg:SI (match_dup 1) 0) | |
| 4525 | (match_dup 2))) | |
| 4526 | ||
| 4527 | (set (match_dup 3) | |
| 4528 | (ashift:SI (subreg:SI (match_dup 1) 1) | |
| 4529 | (match_dup 4))) | |
| 4530 | ||
| 4531 | (set (subreg:SI (match_dup 0) 0) | |
| 4532 | (ior:SI (subreg:SI (match_dup 0) 0) | |
| 4533 | (match_dup 3))) | |
| 4534 | ||
| 4535 | (set (subreg:SI (match_dup 0) 1) | |
| 4536 | (ashiftrt:SI (subreg:SI (match_dup 1) 1) | |
| 4537 | (match_dup 2)))] | |
| 4538 | " | |
| 4539 | { | |
| 4540 | int amount = INTVAL (operands[2]); | |
| 4541 | operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31)); | |
| 4542 | operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31)); | |
| 4543 | }") | |
| 4544 | ||
| 4545 | ||
| 4546 | (define_split | |
| 4547 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4548 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4549 | (match_operand:SI 2 "small_int" ""))) | |
| 4550 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4551 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4552 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4553 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4554 | && (INTVAL (operands[2]) & 63) < 32 | |
| 4555 | && (INTVAL (operands[2]) & 63) != 0" | |
| 4556 | ||
| 4557 | [(set (subreg:SI (match_dup 0) 1) | |
| 4558 | (lshiftrt:SI (subreg:SI (match_dup 1) 1) | |
| 4559 | (match_dup 2))) | |
| 4560 | ||
| 4561 | (set (match_dup 3) | |
| 4562 | (ashift:SI (subreg:SI (match_dup 1) 0) | |
| 4563 | (match_dup 4))) | |
| 4564 | ||
| 4565 | (set (subreg:SI (match_dup 0) 1) | |
| 4566 | (ior:SI (subreg:SI (match_dup 0) 1) | |
| 4567 | (match_dup 3))) | |
| 4568 | ||
| 4569 | (set (subreg:SI (match_dup 0) 0) | |
| 4570 | (ashiftrt:SI (subreg:SI (match_dup 1) 0) | |
| 4571 | (match_dup 2)))] | |
| 4572 | " | |
| 4573 | { | |
| 4574 | int amount = INTVAL (operands[2]); | |
| 4575 | operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31)); | |
| 4576 | operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31)); | |
| 4577 | }") | |
| 4578 | ||
| 4579 | ||
| bb621ad7 JW |
4580 | (define_insn "ashrdi3_internal4" |
| 4581 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4582 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 4583 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 4584 | "TARGET_64BIT" | |
| 4585 | "* | |
| 4586 | { | |
| 4587 | if (GET_CODE (operands[2]) == CONST_INT) | |
| 4588 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); | |
| 4589 | ||
| 4590 | return \"dsra\\t%0,%1,%2\"; | |
| 4591 | }" | |
| 4592 | [(set_attr "type" "arith") | |
| 4593 | (set_attr "mode" "DI") | |
| 4594 | (set_attr "length" "1")]) | |
| 4595 | ||
| 4596 | ||
| 8ef30996 MM |
4597 | (define_insn "lshrsi3" |
| 4598 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4599 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 4600 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 4601 | "" | |
| 4602 | "* | |
| 4603 | { | |
| 4604 | if (GET_CODE (operands[2]) == CONST_INT) | |
| e19ff60f | 4605 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f); |
| 8ef30996 MM |
4606 | |
| 4607 | return \"srl\\t%0,%1,%2\"; | |
| 4608 | }" | |
| 4609 | [(set_attr "type" "arith") | |
| 4610 | (set_attr "mode" "SI") | |
| 4611 | (set_attr "length" "1")]) | |
| 4612 | ||
| 4613 | ||
| 4614 | (define_expand "lshrdi3" | |
| 4615 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
| 4616 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4617 | (match_operand:SI 2 "arith_operand" ""))) | |
| 4618 | (clobber (match_dup 3))])] | |
| bb621ad7 JW |
4619 | "TARGET_64BIT || !TARGET_DEBUG_G_MODE" |
| 4620 | " | |
| 4621 | { | |
| 4622 | if (TARGET_64BIT) | |
| 4623 | { | |
| 4624 | emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1], | |
| 4625 | operands[2])); | |
| 4626 | DONE; | |
| 4627 | } | |
| 4628 | ||
| 4629 | operands[3] = gen_reg_rtx (SImode); | |
| 4630 | }") | |
| 8ef30996 MM |
4631 | |
| 4632 | ||
| 4633 | (define_insn "lshrdi3_internal" | |
| 4634 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
| 4635 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 4636 | (match_operand:SI 2 "register_operand" "d"))) | |
| 4637 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 4638 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE" |
| 8ef30996 MM |
4639 | "* |
| 4640 | { | |
| 4641 | operands[4] = const0_rtx; | |
| 4642 | dslots_jump_total += 3; | |
| 4643 | dslots_jump_filled += 2; | |
| 4644 | ||
| 4645 | return \"sll\\t%3,%2,26\\n\\ | |
| 4646 | \\tbgez\\t%3,1f\\n\\ | |
| 4647 | \\tsrl\\t%L0,%M1,%2\\n\\ | |
| 4648 | \\t%(b\\t3f\\n\\ | |
| 4649 | \\tmove\\t%M0,%z4%)\\n\\ | |
| 4650 | \\n\\ | |
| 4651 | 1:\\n\\ | |
| 4652 | \\t%(beq\\t%3,%z4,2f\\n\\ | |
| 4653 | \\tsrl\\t%L0,%L1,%2%)\\n\\ | |
| 4654 | \\n\\ | |
| 4655 | \\tsubu\\t%3,%z4,%2\\n\\ | |
| 4656 | \\tsll\\t%3,%M1,%3\\n\\ | |
| 4657 | \\tor\\t%L0,%L0,%3\\n\\ | |
| 4658 | 2:\\n\\ | |
| 4659 | \\tsrl\\t%M0,%M1,%2\\n\\ | |
| 4660 | 3:\"; | |
| 4661 | }" | |
| 4662 | [(set_attr "type" "darith") | |
| 4663 | (set_attr "mode" "DI") | |
| 4664 | (set_attr "length" "12")]) | |
| 4665 | ||
| 4666 | ||
| 4667 | (define_insn "lshrdi3_internal2" | |
| 4668 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4669 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 4670 | (match_operand:SI 2 "small_int" "IJK"))) | |
| 4671 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 4672 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0" |
| 8ef30996 MM |
4673 | "* |
| 4674 | { | |
| e19ff60f | 4675 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f); |
| 8ef30996 MM |
4676 | operands[4] = const0_rtx; |
| 4677 | return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\"; | |
| 4678 | }" | |
| 4679 | [(set_attr "type" "darith") | |
| 4680 | (set_attr "mode" "DI") | |
| 4681 | (set_attr "length" "2")]) | |
| 4682 | ||
| 4683 | ||
| 4684 | (define_split | |
| 4685 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4686 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4687 | (match_operand:SI 2 "small_int" ""))) | |
| 4688 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4689 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4690 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4691 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4692 | && (INTVAL (operands[2]) & 32) != 0" | |
| 4693 | ||
| 4694 | [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2))) | |
| 4695 | (set (subreg:SI (match_dup 0) 1) (const_int 0))] | |
| 4696 | ||
| e19ff60f | 4697 | "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);") |
| 8ef30996 MM |
4698 | |
| 4699 | ||
| 4700 | (define_split | |
| 4701 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4702 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4703 | (match_operand:SI 2 "small_int" ""))) | |
| 4704 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4705 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4706 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4707 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4708 | && (INTVAL (operands[2]) & 32) != 0" | |
| 4709 | ||
| 4710 | [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) | |
| 4711 | (set (subreg:SI (match_dup 0) 0) (const_int 0))] | |
| 4712 | ||
| e19ff60f | 4713 | "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);") |
| 8ef30996 MM |
4714 | |
| 4715 | ||
| 4716 | (define_insn "lshrdi3_internal3" | |
| 4717 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4718 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 4719 | (match_operand:SI 2 "small_int" "IJK"))) | |
| 4720 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 | 4721 | "!TARGET_64BIT && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4722 | && (INTVAL (operands[2]) & 63) < 32 |
| 4723 | && (INTVAL (operands[2]) & 63) != 0" | |
| 4724 | "* | |
| 4725 | { | |
| 4726 | int amount = INTVAL (operands[2]); | |
| 4727 | ||
| 4728 | operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31)); | |
| 4729 | operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31)); | |
| 4730 | ||
| 4731 | return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\"; | |
| 4732 | }" | |
| 4733 | [(set_attr "type" "darith") | |
| 4734 | (set_attr "mode" "DI") | |
| 4735 | (set_attr "length" "4")]) | |
| 4736 | ||
| 4737 | ||
| 4738 | (define_split | |
| 4739 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4740 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4741 | (match_operand:SI 2 "small_int" ""))) | |
| 4742 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4743 | "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4744 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4745 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4746 | && (INTVAL (operands[2]) & 63) < 32 | |
| 4747 | && (INTVAL (operands[2]) & 63) != 0" | |
| 4748 | ||
| 4749 | [(set (subreg:SI (match_dup 0) 0) | |
| 4750 | (lshiftrt:SI (subreg:SI (match_dup 1) 0) | |
| 4751 | (match_dup 2))) | |
| 4752 | ||
| 4753 | (set (match_dup 3) | |
| 4754 | (ashift:SI (subreg:SI (match_dup 1) 1) | |
| 4755 | (match_dup 4))) | |
| 4756 | ||
| 4757 | (set (subreg:SI (match_dup 0) 0) | |
| 4758 | (ior:SI (subreg:SI (match_dup 0) 0) | |
| 4759 | (match_dup 3))) | |
| 4760 | ||
| 4761 | (set (subreg:SI (match_dup 0) 1) | |
| 4762 | (lshiftrt:SI (subreg:SI (match_dup 1) 1) | |
| 4763 | (match_dup 2)))] | |
| 4764 | " | |
| 4765 | { | |
| 4766 | int amount = INTVAL (operands[2]); | |
| 4767 | operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31)); | |
| 4768 | operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31)); | |
| 4769 | }") | |
| 4770 | ||
| 4771 | ||
| 4772 | (define_split | |
| 4773 | [(set (match_operand:DI 0 "register_operand" "") | |
| 4774 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 4775 | (match_operand:SI 2 "small_int" ""))) | |
| 4776 | (clobber (match_operand:SI 3 "register_operand" ""))] | |
| bb621ad7 | 4777 | "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE |
| 8ef30996 MM |
4778 | && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER |
| 4779 | && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
| 4780 | && (INTVAL (operands[2]) & 63) < 32 | |
| 4781 | && (INTVAL (operands[2]) & 63) != 0" | |
| 4782 | ||
| 4783 | [(set (subreg:SI (match_dup 0) 1) | |
| 4784 | (lshiftrt:SI (subreg:SI (match_dup 1) 1) | |
| 4785 | (match_dup 2))) | |
| 4786 | ||
| 4787 | (set (match_dup 3) | |
| 4788 | (ashift:SI (subreg:SI (match_dup 1) 0) | |
| 4789 | (match_dup 4))) | |
| 4790 | ||
| 4791 | (set (subreg:SI (match_dup 0) 1) | |
| 4792 | (ior:SI (subreg:SI (match_dup 0) 1) | |
| 4793 | (match_dup 3))) | |
| 4794 | ||
| 4795 | (set (subreg:SI (match_dup 0) 0) | |
| 4796 | (lshiftrt:SI (subreg:SI (match_dup 1) 0) | |
| 4797 | (match_dup 2)))] | |
| 4798 | " | |
| 4799 | { | |
| 4800 | int amount = INTVAL (operands[2]); | |
| 4801 | operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31)); | |
| 4802 | operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31)); | |
| 4803 | }") | |
| 4804 | ||
| bb621ad7 JW |
4805 | |
| 4806 | (define_insn "lshrdi3_internal4" | |
| 4807 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4808 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 4809 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 4810 | "TARGET_64BIT" | |
| 4811 | "* | |
| 4812 | { | |
| 4813 | if (GET_CODE (operands[2]) == CONST_INT) | |
| 4814 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); | |
| 4815 | ||
| 4816 | return \"dsrl\\t%0,%1,%2\"; | |
| 4817 | }" | |
| 4818 | [(set_attr "type" "arith") | |
| 4819 | (set_attr "mode" "DI") | |
| 4820 | (set_attr "length" "1")]) | |
| 4821 | ||
| 8ef30996 MM |
4822 | \f |
| 4823 | ;; | |
| 4824 | ;; .................... | |
| 4825 | ;; | |
| 4826 | ;; COMPARISONS | |
| 4827 | ;; | |
| 4828 | ;; .................... | |
| 4829 | ||
| 4830 | ;; Flow here is rather complex: | |
| 4831 | ;; | |
| bb621ad7 | 4832 | ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the |
| 8ef30996 MM |
4833 | ;; arguments into the branch_cmp array, and the type into |
| 4834 | ;; branch_type. No RTL is generated. | |
| 4835 | ;; | |
| 4836 | ;; 2) The appropriate branch define_expand is called, which then | |
| 4837 | ;; creates the appropriate RTL for the comparison and branch. | |
| 4838 | ;; Different CC modes are used, based on what type of branch is | |
| 4839 | ;; done, so that we can constrain things appropriately. There | |
| 4840 | ;; are assumptions in the rest of GCC that break if we fold the | |
| 4841 | ;; operands into the branchs for integer operations, and use cc0 | |
| 34b650b3 MM |
4842 | ;; for floating point, so we use the fp status register instead. |
| 4843 | ;; If needed, an appropriate temporary is created to hold the | |
| 4844 | ;; of the integer compare. | |
| 8ef30996 MM |
4845 | |
| 4846 | (define_expand "cmpsi" | |
| 4847 | [(set (cc0) | |
| 4848 | (compare:CC (match_operand:SI 0 "register_operand" "") | |
| 4849 | (match_operand:SI 1 "arith_operand" "")))] | |
| 4850 | "" | |
| 4851 | " | |
| 4852 | { | |
| 4853 | if (operands[0]) /* avoid unused code message */ | |
| 4854 | { | |
| 4855 | branch_cmp[0] = operands[0]; | |
| 4856 | branch_cmp[1] = operands[1]; | |
| 4857 | branch_type = CMP_SI; | |
| 4858 | DONE; | |
| 4859 | } | |
| 4860 | }") | |
| 4861 | ||
| 4862 | (define_expand "tstsi" | |
| 4863 | [(set (cc0) | |
| 4864 | (match_operand:SI 0 "register_operand" ""))] | |
| 4865 | "" | |
| 4866 | " | |
| 4867 | { | |
| 4868 | if (operands[0]) /* avoid unused code message */ | |
| 4869 | { | |
| 4870 | branch_cmp[0] = operands[0]; | |
| 4871 | branch_cmp[1] = const0_rtx; | |
| 4872 | branch_type = CMP_SI; | |
| 4873 | DONE; | |
| 4874 | } | |
| 4875 | }") | |
| 4876 | ||
| bb621ad7 JW |
4877 | (define_expand "cmpdi" |
| 4878 | [(set (cc0) | |
| 4879 | (compare:CC (match_operand:DI 0 "register_operand" "") | |
| 4880 | (match_operand:DI 1 "arith_operand" "")))] | |
| 4881 | "TARGET_64BIT" | |
| 4882 | " | |
| 4883 | { | |
| 4884 | if (operands[0]) /* avoid unused code message */ | |
| 4885 | { | |
| 4886 | branch_cmp[0] = operands[0]; | |
| 4887 | branch_cmp[1] = operands[1]; | |
| 4888 | branch_type = CMP_DI; | |
| 4889 | DONE; | |
| 4890 | } | |
| 4891 | }") | |
| 4892 | ||
| 4893 | (define_expand "tstdi" | |
| 4894 | [(set (cc0) | |
| 4895 | (match_operand:DI 0 "register_operand" ""))] | |
| 4896 | "TARGET_64BIT" | |
| 4897 | " | |
| 4898 | { | |
| 4899 | if (operands[0]) /* avoid unused code message */ | |
| 4900 | { | |
| 4901 | branch_cmp[0] = operands[0]; | |
| 4902 | branch_cmp[1] = const0_rtx; | |
| 4903 | branch_type = CMP_DI; | |
| 4904 | DONE; | |
| 4905 | } | |
| 4906 | }") | |
| 4907 | ||
| 8ef30996 MM |
4908 | (define_expand "cmpdf" |
| 4909 | [(set (cc0) | |
| b8eb88d0 ILT |
4910 | (compare:CC (match_operand:DF 0 "register_operand" "") |
| 4911 | (match_operand:DF 1 "register_operand" "")))] | |
| 46299de9 | 4912 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 8ef30996 MM |
4913 | " |
| 4914 | { | |
| 4915 | if (operands[0]) /* avoid unused code message */ | |
| 4916 | { | |
| 4917 | branch_cmp[0] = operands[0]; | |
| 4918 | branch_cmp[1] = operands[1]; | |
| 4919 | branch_type = CMP_DF; | |
| 4920 | DONE; | |
| 4921 | } | |
| 4922 | }") | |
| 4923 | ||
| 8ef30996 MM |
4924 | (define_expand "cmpsf" |
| 4925 | [(set (cc0) | |
| b8eb88d0 ILT |
4926 | (compare:CC (match_operand:SF 0 "register_operand" "") |
| 4927 | (match_operand:SF 1 "register_operand" "")))] | |
| 8ef30996 MM |
4928 | "TARGET_HARD_FLOAT" |
| 4929 | " | |
| 4930 | { | |
| 4931 | if (operands[0]) /* avoid unused code message */ | |
| 4932 | { | |
| 4933 | branch_cmp[0] = operands[0]; | |
| 4934 | branch_cmp[1] = operands[1]; | |
| 4935 | branch_type = CMP_SF; | |
| 4936 | DONE; | |
| 4937 | } | |
| 4938 | }") | |
| 4939 | ||
| 8ef30996 MM |
4940 | \f |
| 4941 | ;; | |
| 4942 | ;; .................... | |
| 4943 | ;; | |
| 4944 | ;; CONDITIONAL BRANCHES | |
| 4945 | ;; | |
| 4946 | ;; .................... | |
| 4947 | ||
| 34b650b3 | 4948 | (define_insn "branch_fp_ne" |
| 8ef30996 | 4949 | [(set (pc) |
| b8eb88d0 ILT |
4950 | (if_then_else (ne:CC (match_operand:CC 0 "register_operand" "z") |
| 4951 | (const_int 0)) | |
| 4952 | (match_operand 1 "pc_or_label_operand" "") | |
| 4953 | (match_operand 2 "pc_or_label_operand" "")))] | |
| bb621ad7 | 4954 | "TARGET_HARD_FLOAT" |
| 8ef30996 MM |
4955 | "* |
| 4956 | { | |
| 8ef30996 | 4957 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); |
| b8eb88d0 | 4958 | return (operands[1] != pc_rtx) ? \"%*bc1t%?\\t%Z0%1\" : \"%*bc1f%?\\t%Z0%2\"; |
| 8ef30996 MM |
4959 | }" |
| 4960 | [(set_attr "type" "branch") | |
| 4961 | (set_attr "mode" "none") | |
| 34b650b3 | 4962 | (set_attr "length" "1")]) |
| 8ef30996 | 4963 | |
| 34b650b3 | 4964 | (define_insn "branch_fp_eq" |
| 8ef30996 | 4965 | [(set (pc) |
| b8eb88d0 ILT |
4966 | (if_then_else (eq:CC (match_operand:CC 0 "register_operand" "z") |
| 4967 | (const_int 0)) | |
| 4968 | (match_operand 1 "pc_or_label_operand" "") | |
| 4969 | (match_operand 2 "pc_or_label_operand" "")))] | |
| bb621ad7 | 4970 | "TARGET_HARD_FLOAT" |
| 8ef30996 MM |
4971 | "* |
| 4972 | { | |
| 4973 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); | |
| b8eb88d0 | 4974 | return (operands[1] != pc_rtx) ? \"%*bc1f%?\\t%Z0%1\" : \"%*bc1t%?\\t%Z0%2\"; |
| 8ef30996 MM |
4975 | }" |
| 4976 | [(set_attr "type" "branch") | |
| 4977 | (set_attr "mode" "none") | |
| 4978 | (set_attr "length" "1")]) | |
| 4979 | ||
| 34b650b3 | 4980 | (define_insn "branch_zero" |
| 8ef30996 | 4981 | [(set (pc) |
| 34b650b3 | 4982 | (if_then_else (match_operator:SI 0 "cmp_op" |
| 81723db9 | 4983 | [(match_operand:SI 1 "register_operand" "d") |
| 34b650b3 MM |
4984 | (const_int 0)]) |
| 4985 | (match_operand 2 "pc_or_label_operand" "") | |
| 4986 | (match_operand 3 "pc_or_label_operand" "")))] | |
| 8ef30996 MM |
4987 | "" |
| 4988 | "* | |
| 4989 | { | |
| 4990 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); | |
| 34b650b3 MM |
4991 | if (operands[2] != pc_rtx) |
| 4992 | { /* normal jump */ | |
| 4993 | switch (GET_CODE (operands[0])) | |
| 4994 | { | |
| 4995 | case EQ: return \"%*beq%?\\t%z1,%.,%2\"; | |
| 4996 | case NE: return \"%*bne%?\\t%z1,%.,%2\"; | |
| 4997 | case GTU: return \"%*bne%?\\t%z1,%.,%2\"; | |
| 4998 | case LEU: return \"%*beq%?\\t%z1,%.,%2\"; | |
| 4999 | case GEU: return \"%*j\\t%2\"; | |
| 81723db9 | 5000 | case LTU: return \"%*bne%?\\t%.,%.,%2\"; |
| 34b650b3 | 5001 | } |
| 8ef30996 | 5002 | |
| 34b650b3 | 5003 | return \"%*b%C0z%?\\t%z1,%2\"; |
| 8ef30996 | 5004 | } |
| 34b650b3 MM |
5005 | else |
| 5006 | { /* inverted jump */ | |
| 5007 | switch (GET_CODE (operands[0])) | |
| 5008 | { | |
| 5009 | case EQ: return \"%*bne%?\\t%z1,%.,%3\"; | |
| 5010 | case NE: return \"%*beq%?\\t%z1,%.,%3\"; | |
| 5011 | case GTU: return \"%*beq%?\\t%z1,%.,%3\"; | |
| 5012 | case LEU: return \"%*bne%?\\t%z1,%.,%3\"; | |
| 81723db9 | 5013 | case GEU: return \"%*beq%?\\t%.,%.,%3\"; |
| 34b650b3 MM |
5014 | case LTU: return \"%*j\\t%3\"; |
| 5015 | } | |
| 8ef30996 | 5016 | |
| 34b650b3 MM |
5017 | return \"%*b%N0z%?\\t%z1,%3\"; |
| 5018 | } | |
| 8ef30996 MM |
5019 | }" |
| 5020 | [(set_attr "type" "branch") | |
| 5021 | (set_attr "mode" "none") | |
| 5022 | (set_attr "length" "1")]) | |
| 5023 | ||
| 8ef30996 | 5024 | |
| bb621ad7 JW |
5025 | (define_insn "branch_zero_di" |
| 5026 | [(set (pc) | |
| 5027 | (if_then_else (match_operator:DI 0 "cmp_op" | |
| 5028 | [(match_operand:DI 1 "register_operand" "d") | |
| 5029 | (const_int 0)]) | |
| 5030 | (match_operand 2 "pc_or_label_operand" "") | |
| 5031 | (match_operand 3 "pc_or_label_operand" "")))] | |
| 5032 | "" | |
| 5033 | "* | |
| 5034 | { | |
| 5035 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); | |
| 5036 | if (operands[2] != pc_rtx) | |
| 5037 | { /* normal jump */ | |
| 5038 | switch (GET_CODE (operands[0])) | |
| 5039 | { | |
| 5040 | case EQ: return \"%*beq%?\\t%z1,%.,%2\"; | |
| 5041 | case NE: return \"%*bne%?\\t%z1,%.,%2\"; | |
| 5042 | case GTU: return \"%*bne%?\\t%z1,%.,%2\"; | |
| 5043 | case LEU: return \"%*beq%?\\t%z1,%.,%2\"; | |
| 5044 | case GEU: return \"%*j\\t%2\"; | |
| 5045 | case LTU: return \"%*bne%?\\t%.,%.,%2\"; | |
| 5046 | } | |
| 5047 | ||
| 5048 | return \"%*b%C0z%?\\t%z1,%2\"; | |
| 5049 | } | |
| 5050 | else | |
| 5051 | { /* inverted jump */ | |
| 5052 | switch (GET_CODE (operands[0])) | |
| 5053 | { | |
| 5054 | case EQ: return \"%*bne%?\\t%z1,%.,%3\"; | |
| 5055 | case NE: return \"%*beq%?\\t%z1,%.,%3\"; | |
| 5056 | case GTU: return \"%*beq%?\\t%z1,%.,%3\"; | |
| 5057 | case LEU: return \"%*bne%?\\t%z1,%.,%3\"; | |
| 5058 | case GEU: return \"%*beq%?\\t%.,%.,%3\"; | |
| 5059 | case LTU: return \"%*j\\t%3\"; | |
| 5060 | } | |
| 5061 | ||
| 5062 | return \"%*b%N0z%?\\t%z1,%3\"; | |
| 5063 | } | |
| 5064 | }" | |
| 5065 | [(set_attr "type" "branch") | |
| 5066 | (set_attr "mode" "none") | |
| 5067 | (set_attr "length" "1")]) | |
| 5068 | ||
| 5069 | ||
| 34b650b3 | 5070 | (define_insn "branch_equality" |
| 8ef30996 | 5071 | [(set (pc) |
| 34b650b3 MM |
5072 | (if_then_else (match_operator:SI 0 "equality_op" |
| 5073 | [(match_operand:SI 1 "register_operand" "d") | |
| 5074 | (match_operand:SI 2 "register_operand" "d")]) | |
| 5075 | (match_operand 3 "pc_or_label_operand" "") | |
| 5076 | (match_operand 4 "pc_or_label_operand" "")))] | |
| 8ef30996 MM |
5077 | "" |
| 5078 | "* | |
| 5079 | { | |
| 5080 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); | |
| 34b650b3 MM |
5081 | return (operands[3] != pc_rtx) |
| 5082 | ? \"%*b%C0%?\\t%z1,%z2,%3\" | |
| 5083 | : \"%*b%N0%?\\t%z1,%z2,%4\"; | |
| 8ef30996 MM |
5084 | }" |
| 5085 | [(set_attr "type" "branch") | |
| 5086 | (set_attr "mode" "none") | |
| 34b650b3 MM |
5087 | (set_attr "length" "1")]) |
| 5088 | ||
| 8ef30996 | 5089 | |
| bb621ad7 JW |
5090 | (define_insn "branch_equality_di" |
| 5091 | [(set (pc) | |
| 5092 | (if_then_else (match_operator:DI 0 "equality_op" | |
| 5093 | [(match_operand:DI 1 "register_operand" "d") | |
| 5094 | (match_operand:DI 2 "register_operand" "d")]) | |
| 5095 | (match_operand 3 "pc_or_label_operand" "") | |
| 5096 | (match_operand 4 "pc_or_label_operand" "")))] | |
| 5097 | "" | |
| 5098 | "* | |
| 5099 | { | |
| 5100 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); | |
| 5101 | return (operands[3] != pc_rtx) | |
| 5102 | ? \"%*b%C0%?\\t%z1,%z2,%3\" | |
| 5103 | : \"%*b%N0%?\\t%z1,%z2,%4\"; | |
| 5104 | }" | |
| 5105 | [(set_attr "type" "branch") | |
| 5106 | (set_attr "mode" "none") | |
| 5107 | (set_attr "length" "1")]) | |
| 5108 | ||
| 5109 | ||
| 8ef30996 MM |
5110 | (define_expand "beq" |
| 5111 | [(set (pc) | |
| b8eb88d0 ILT |
5112 | (if_then_else (eq:CC (cc0) |
| 5113 | (const_int 0)) | |
| 8ef30996 MM |
5114 | (label_ref (match_operand 0 "" "")) |
| 5115 | (pc)))] | |
| 5116 | "" | |
| 5117 | " | |
| 5118 | { | |
| 5119 | if (operands[0]) /* avoid unused code warning */ | |
| 5120 | { | |
| 5121 | gen_conditional_branch (operands, EQ); | |
| 5122 | DONE; | |
| 5123 | } | |
| 5124 | }") | |
| 5125 | ||
| 5126 | (define_expand "bne" | |
| 5127 | [(set (pc) | |
| b8eb88d0 ILT |
5128 | (if_then_else (ne:CC (cc0) |
| 5129 | (const_int 0)) | |
| 8ef30996 MM |
5130 | (label_ref (match_operand 0 "" "")) |
| 5131 | (pc)))] | |
| 5132 | "" | |
| 5133 | " | |
| 5134 | { | |
| 5135 | if (operands[0]) /* avoid unused code warning */ | |
| 5136 | { | |
| 5137 | gen_conditional_branch (operands, NE); | |
| 5138 | DONE; | |
| 5139 | } | |
| 5140 | }") | |
| 5141 | ||
| 5142 | (define_expand "bgt" | |
| 5143 | [(set (pc) | |
| 5144 | (if_then_else (gt:CC (cc0) | |
| 5145 | (const_int 0)) | |
| 5146 | (label_ref (match_operand 0 "" "")) | |
| 5147 | (pc)))] | |
| 5148 | "" | |
| 5149 | " | |
| 5150 | { | |
| 5151 | if (operands[0]) /* avoid unused code warning */ | |
| 5152 | { | |
| 5153 | gen_conditional_branch (operands, GT); | |
| 5154 | DONE; | |
| 5155 | } | |
| 5156 | }") | |
| 5157 | ||
| 5158 | (define_expand "bge" | |
| 5159 | [(set (pc) | |
| 5160 | (if_then_else (ge:CC (cc0) | |
| 5161 | (const_int 0)) | |
| 5162 | (label_ref (match_operand 0 "" "")) | |
| 5163 | (pc)))] | |
| 5164 | "" | |
| 5165 | " | |
| 5166 | { | |
| 5167 | if (operands[0]) /* avoid unused code warning */ | |
| 5168 | { | |
| 5169 | gen_conditional_branch (operands, GE); | |
| 5170 | DONE; | |
| 5171 | } | |
| 5172 | }") | |
| 5173 | ||
| 5174 | (define_expand "blt" | |
| 5175 | [(set (pc) | |
| 5176 | (if_then_else (lt:CC (cc0) | |
| 5177 | (const_int 0)) | |
| 5178 | (label_ref (match_operand 0 "" "")) | |
| 5179 | (pc)))] | |
| 5180 | "" | |
| 5181 | " | |
| 5182 | { | |
| 5183 | if (operands[0]) /* avoid unused code warning */ | |
| 5184 | { | |
| 5185 | gen_conditional_branch (operands, LT); | |
| 5186 | DONE; | |
| 5187 | } | |
| 5188 | }") | |
| 5189 | ||
| 5190 | (define_expand "ble" | |
| 5191 | [(set (pc) | |
| 5192 | (if_then_else (le:CC (cc0) | |
| 5193 | (const_int 0)) | |
| 5194 | (label_ref (match_operand 0 "" "")) | |
| 5195 | (pc)))] | |
| 5196 | "" | |
| 5197 | " | |
| 5198 | { | |
| 5199 | if (operands[0]) /* avoid unused code warning */ | |
| 5200 | { | |
| 5201 | gen_conditional_branch (operands, LE); | |
| 5202 | DONE; | |
| 5203 | } | |
| 5204 | }") | |
| 5205 | ||
| 5206 | (define_expand "bgtu" | |
| 5207 | [(set (pc) | |
| 5208 | (if_then_else (gtu:CC (cc0) | |
| 5209 | (const_int 0)) | |
| 5210 | (label_ref (match_operand 0 "" "")) | |
| 5211 | (pc)))] | |
| 5212 | "" | |
| 5213 | " | |
| 5214 | { | |
| 5215 | if (operands[0]) /* avoid unused code warning */ | |
| 5216 | { | |
| 5217 | gen_conditional_branch (operands, GTU); | |
| 5218 | DONE; | |
| 5219 | } | |
| 5220 | }") | |
| 5221 | ||
| 5222 | (define_expand "bgeu" | |
| 5223 | [(set (pc) | |
| 5224 | (if_then_else (geu:CC (cc0) | |
| 5225 | (const_int 0)) | |
| 5226 | (label_ref (match_operand 0 "" "")) | |
| 5227 | (pc)))] | |
| 5228 | "" | |
| 5229 | " | |
| 5230 | { | |
| 5231 | if (operands[0]) /* avoid unused code warning */ | |
| 5232 | { | |
| 5233 | gen_conditional_branch (operands, GEU); | |
| 5234 | DONE; | |
| 5235 | } | |
| 5236 | }") | |
| 5237 | ||
| 5238 | ||
| 5239 | (define_expand "bltu" | |
| 5240 | [(set (pc) | |
| 5241 | (if_then_else (ltu:CC (cc0) | |
| 5242 | (const_int 0)) | |
| 5243 | (label_ref (match_operand 0 "" "")) | |
| 5244 | (pc)))] | |
| 5245 | "" | |
| 5246 | " | |
| 5247 | { | |
| 5248 | if (operands[0]) /* avoid unused code warning */ | |
| 5249 | { | |
| 5250 | gen_conditional_branch (operands, LTU); | |
| 5251 | DONE; | |
| 5252 | } | |
| 5253 | }") | |
| 5254 | ||
| 5255 | (define_expand "bleu" | |
| 5256 | [(set (pc) | |
| 5257 | (if_then_else (leu:CC (cc0) | |
| 5258 | (const_int 0)) | |
| 5259 | (label_ref (match_operand 0 "" "")) | |
| 5260 | (pc)))] | |
| 5261 | "" | |
| 5262 | " | |
| 5263 | { | |
| 5264 | if (operands[0]) /* avoid unused code warning */ | |
| 5265 | { | |
| 5266 | gen_conditional_branch (operands, LEU); | |
| 5267 | DONE; | |
| 5268 | } | |
| 5269 | }") | |
| 5270 | ||
| 5271 | \f | |
| 5272 | ;; | |
| 5273 | ;; .................... | |
| 5274 | ;; | |
| 5275 | ;; SETTING A REGISTER FROM A COMPARISON | |
| 5276 | ;; | |
| 5277 | ;; .................... | |
| 5278 | ||
| 5279 | (define_expand "seq" | |
| 5280 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 MM |
5281 | (eq:SI (match_dup 1) |
| 5282 | (match_dup 2)))] | |
| 8ef30996 MM |
5283 | "" |
| 5284 | " | |
| 5285 | { | |
| bb621ad7 | 5286 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5287 | FAIL; |
| 5288 | ||
| 5289 | /* set up operands from compare. */ | |
| 5290 | operands[1] = branch_cmp[0]; | |
| 5291 | operands[2] = branch_cmp[1]; | |
| 5292 | ||
| bb621ad7 | 5293 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5294 | { |
| 5295 | gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0); | |
| 5296 | DONE; | |
| 5297 | } | |
| 5298 | ||
| 8ef30996 MM |
5299 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) |
| 5300 | operands[2] = force_reg (SImode, operands[2]); | |
| 5301 | ||
| 5302 | /* fall through and generate default code */ | |
| 5303 | }") | |
| 5304 | ||
| 34b650b3 MM |
5305 | |
| 5306 | (define_insn "seq_si_zero" | |
| 5307 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5308 | (eq:SI (match_operand:SI 1 "register_operand" "d") | |
| 5309 | (const_int 0)))] | |
| 8ef30996 | 5310 | "" |
| 34b650b3 | 5311 | "sltu\\t%0,%1,1" |
| bb621ad7 | 5312 | [(set_attr "type" "arith") |
| 34b650b3 MM |
5313 | (set_attr "mode" "SI") |
| 5314 | (set_attr "length" "1")]) | |
| 5315 | ||
| bb621ad7 JW |
5316 | (define_insn "seq_di_zero" |
| 5317 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5318 | (eq:DI (match_operand:DI 1 "register_operand" "d") | |
| 5319 | (const_int 0)))] | |
| 5320 | "TARGET_64BIT" | |
| 5321 | "sltu\\t%0,%1,1" | |
| 5322 | [(set_attr "type" "arith") | |
| 5323 | (set_attr "mode" "DI") | |
| 5324 | (set_attr "length" "1")]) | |
| 5325 | ||
| 34b650b3 MM |
5326 | (define_insn "seq_si" |
| 5327 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 5328 | (eq:SI (match_operand:SI 1 "register_operand" "%d,d") | |
| 5329 | (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| bbdb5552 | 5330 | "TARGET_DEBUG_C_MODE" |
| 8ef30996 | 5331 | "@ |
| 8ef30996 | 5332 | xor\\t%0,%1,%2\;sltu\\t%0,%0,1 |
| 34b650b3 | 5333 | xori\\t%0,%1,%2\;sltu\\t%0,%0,1" |
| bb621ad7 JW |
5334 | [(set_attr "type" "arith") |
| 5335 | (set_attr "mode" "SI") | |
| 5336 | (set_attr "length" "2")]) | |
| 5337 | ||
| 5338 | (define_split | |
| 5339 | [(set (match_operand:SI 0 "register_operand" "") | |
| 5340 | (eq:SI (match_operand:SI 1 "register_operand" "") | |
| 5341 | (match_operand:SI 2 "uns_arith_operand" "")))] | |
| 5342 | "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE | |
| 5343 | && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" | |
| 5344 | [(set (match_dup 0) | |
| 5345 | (xor:SI (match_dup 1) | |
| 5346 | (match_dup 2))) | |
| 5347 | (set (match_dup 0) | |
| 5348 | (ltu:SI (match_dup 0) | |
| 5349 | (const_int 1)))] | |
| 5350 | "") | |
| 5351 | ||
| 5352 | (define_insn "seq_di" | |
| 5353 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5354 | (eq:DI (match_operand:DI 1 "register_operand" "%d,d") | |
| 5355 | (match_operand:DI 2 "uns_arith_operand" "d,K")))] | |
| 5356 | "TARGET_64BIT && TARGET_DEBUG_C_MODE" | |
| 5357 | "@ | |
| 5358 | xor\\t%0,%1,%2\;sltu\\t%0,%0,1 | |
| 5359 | xori\\t%0,%1,%2\;sltu\\t%0,%0,1" | |
| 5360 | [(set_attr "type" "arith") | |
| 5361 | (set_attr "mode" "DI") | |
| 92b4cee1 | 5362 | (set_attr "length" "2")]) |
| 8ef30996 MM |
5363 | |
| 5364 | (define_split | |
| bb621ad7 JW |
5365 | [(set (match_operand:DI 0 "register_operand" "") |
| 5366 | (eq:DI (match_operand:DI 1 "register_operand" "") | |
| 5367 | (match_operand:DI 2 "uns_arith_operand" "")))] | |
| 5368 | "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE | |
| 26b8e6e5 | 5369 | && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" |
| 8ef30996 | 5370 | [(set (match_dup 0) |
| bb621ad7 | 5371 | (xor:DI (match_dup 1) |
| 8ef30996 MM |
5372 | (match_dup 2))) |
| 5373 | (set (match_dup 0) | |
| bb621ad7 | 5374 | (ltu:DI (match_dup 0) |
| 8ef30996 MM |
5375 | (const_int 1)))] |
| 5376 | "") | |
| 5377 | ||
| 5378 | (define_expand "sne" | |
| 5379 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 MM |
5380 | (ne:SI (match_dup 1) |
| 5381 | (match_dup 2)))] | |
| 8ef30996 MM |
5382 | "" |
| 5383 | " | |
| 5384 | { | |
| bb621ad7 | 5385 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5386 | FAIL; |
| 5387 | ||
| 5388 | /* set up operands from compare. */ | |
| 5389 | operands[1] = branch_cmp[0]; | |
| 5390 | operands[2] = branch_cmp[1]; | |
| 5391 | ||
| bb621ad7 | 5392 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5393 | { |
| 5394 | gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0); | |
| 5395 | DONE; | |
| 5396 | } | |
| 5397 | ||
| 8ef30996 MM |
5398 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) |
| 5399 | operands[2] = force_reg (SImode, operands[2]); | |
| 5400 | ||
| 5401 | /* fall through and generate default code */ | |
| 5402 | }") | |
| 5403 | ||
| 34b650b3 MM |
5404 | (define_insn "sne_si_zero" |
| 5405 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5406 | (ne:SI (match_operand:SI 1 "register_operand" "d") | |
| 5407 | (const_int 0)))] | |
| 8ef30996 | 5408 | "" |
| 34b650b3 | 5409 | "sltu\\t%0,%.,%1" |
| bb621ad7 | 5410 | [(set_attr "type" "arith") |
| 34b650b3 MM |
5411 | (set_attr "mode" "SI") |
| 5412 | (set_attr "length" "1")]) | |
| 8ef30996 | 5413 | |
| bb621ad7 JW |
5414 | (define_insn "sne_di_zero" |
| 5415 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5416 | (ne:DI (match_operand:DI 1 "register_operand" "d") | |
| 5417 | (const_int 0)))] | |
| 5418 | "TARGET_64BIT" | |
| 5419 | "sltu\\t%0,%.,%1" | |
| 5420 | [(set_attr "type" "arith") | |
| 5421 | (set_attr "mode" "DI") | |
| 5422 | (set_attr "length" "1")]) | |
| 5423 | ||
| 34b650b3 MM |
5424 | (define_insn "sne_si" |
| 5425 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 5426 | (ne:SI (match_operand:SI 1 "register_operand" "%d,d") | |
| 5427 | (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| bbdb5552 | 5428 | "TARGET_DEBUG_C_MODE" |
| 34b650b3 MM |
5429 | "@ |
| 5430 | xor\\t%0,%1,%2\;sltu\\t%0,%.,%0 | |
| 5431 | xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0" | |
| bb621ad7 | 5432 | [(set_attr "type" "arith") |
| 92b4cee1 MM |
5433 | (set_attr "mode" "SI") |
| 5434 | (set_attr "length" "2")]) | |
| 8ef30996 MM |
5435 | |
| 5436 | (define_split | |
| 5437 | [(set (match_operand:SI 0 "register_operand" "") | |
| 34b650b3 MM |
5438 | (ne:SI (match_operand:SI 1 "register_operand" "") |
| 5439 | (match_operand:SI 2 "uns_arith_operand" "")))] | |
| bbdb5552 | 5440 | "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE |
| 26b8e6e5 | 5441 | && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" |
| 8ef30996 MM |
5442 | [(set (match_dup 0) |
| 5443 | (xor:SI (match_dup 1) | |
| 5444 | (match_dup 2))) | |
| 5445 | (set (match_dup 0) | |
| 34b650b3 | 5446 | (gtu:SI (match_dup 0) |
| 8ef30996 MM |
5447 | (const_int 0)))] |
| 5448 | "") | |
| 5449 | ||
| bb621ad7 JW |
5450 | (define_insn "sne_di" |
| 5451 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5452 | (ne:DI (match_operand:DI 1 "register_operand" "%d,d") | |
| 5453 | (match_operand:DI 2 "uns_arith_operand" "d,K")))] | |
| 5454 | "TARGET_64BIT && TARGET_DEBUG_C_MODE" | |
| 5455 | "@ | |
| 5456 | xor\\t%0,%1,%2\;sltu\\t%0,%.,%0 | |
| 5457 | xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0" | |
| 5458 | [(set_attr "type" "arith") | |
| 5459 | (set_attr "mode" "DI") | |
| 5460 | (set_attr "length" "2")]) | |
| 5461 | ||
| 5462 | (define_split | |
| 5463 | [(set (match_operand:DI 0 "register_operand" "") | |
| 5464 | (ne:DI (match_operand:DI 1 "register_operand" "") | |
| 5465 | (match_operand:DI 2 "uns_arith_operand" "")))] | |
| 5466 | "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE | |
| 5467 | && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" | |
| 5468 | [(set (match_dup 0) | |
| 5469 | (xor:DI (match_dup 1) | |
| 5470 | (match_dup 2))) | |
| 5471 | (set (match_dup 0) | |
| 5472 | (gtu:DI (match_dup 0) | |
| 5473 | (const_int 0)))] | |
| 5474 | "") | |
| 5475 | ||
| 8ef30996 MM |
5476 | (define_expand "sgt" |
| 5477 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5478 | (gt:SI (match_dup 1) |
| 8ef30996 MM |
5479 | (match_dup 2)))] |
| 5480 | "" | |
| 5481 | " | |
| 5482 | { | |
| bb621ad7 | 5483 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5484 | FAIL; |
| 5485 | ||
| 5486 | /* set up operands from compare. */ | |
| 5487 | operands[1] = branch_cmp[0]; | |
| 5488 | operands[2] = branch_cmp[1]; | |
| 5489 | ||
| bb621ad7 | 5490 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5491 | { |
| 5492 | gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0); | |
| 5493 | DONE; | |
| 5494 | } | |
| 5495 | ||
| 8ef30996 MM |
5496 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
| 5497 | operands[2] = force_reg (SImode, operands[2]); | |
| 5498 | ||
| 5499 | /* fall through and generate default code */ | |
| 5500 | }") | |
| 5501 | ||
| 5502 | (define_insn "sgt_si" | |
| 5503 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5504 | (gt:SI (match_operand:SI 1 "register_operand" "d") |
| 8ef30996 MM |
5505 | (match_operand:SI 2 "reg_or_0_operand" "dJ")))] |
| 5506 | "" | |
| 5507 | "slt\\t%0,%z2,%1" | |
| bb621ad7 | 5508 | [(set_attr "type" "arith") |
| 8ef30996 MM |
5509 | (set_attr "mode" "SI") |
| 5510 | (set_attr "length" "1")]) | |
| 5511 | ||
| bb621ad7 JW |
5512 | (define_insn "sgt_di" |
| 5513 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5514 | (gt:DI (match_operand:DI 1 "register_operand" "d") | |
| 5515 | (match_operand:DI 2 "reg_or_0_operand" "dJ")))] | |
| 5516 | "TARGET_64BIT" | |
| 5517 | "slt\\t%0,%z2,%1" | |
| 5518 | [(set_attr "type" "arith") | |
| 5519 | (set_attr "mode" "DI") | |
| 5520 | (set_attr "length" "1")]) | |
| 5521 | ||
| 8ef30996 MM |
5522 | (define_expand "sge" |
| 5523 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5524 | (ge:SI (match_dup 1) |
| 8ef30996 MM |
5525 | (match_dup 2)))] |
| 5526 | "" | |
| 5527 | " | |
| 5528 | { | |
| bb621ad7 | 5529 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5530 | FAIL; |
| 5531 | ||
| 5532 | /* set up operands from compare. */ | |
| 5533 | operands[1] = branch_cmp[0]; | |
| 5534 | operands[2] = branch_cmp[1]; | |
| 5535 | ||
| bb621ad7 | 5536 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5537 | { |
| 5538 | gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0); | |
| 5539 | DONE; | |
| 5540 | } | |
| 5541 | ||
| 8ef30996 MM |
5542 | /* fall through and generate default code */ |
| 5543 | }") | |
| 5544 | ||
| 5545 | (define_insn "sge_si" | |
| 5546 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5547 | (ge:SI (match_operand:SI 1 "register_operand" "d") |
| 8ef30996 | 5548 | (match_operand:SI 2 "arith_operand" "dI")))] |
| bbdb5552 | 5549 | "TARGET_DEBUG_C_MODE" |
| 8ef30996 | 5550 | "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001" |
| bb621ad7 | 5551 | [(set_attr "type" "arith") |
| 8ef30996 MM |
5552 | (set_attr "mode" "SI") |
| 5553 | (set_attr "length" "2")]) | |
| 5554 | ||
| 5555 | (define_split | |
| 5556 | [(set (match_operand:SI 0 "register_operand" "") | |
| 34b650b3 | 5557 | (ge:SI (match_operand:SI 1 "register_operand" "") |
| 8ef30996 | 5558 | (match_operand:SI 2 "arith_operand" "")))] |
| bbdb5552 | 5559 | "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE" |
| 8ef30996 | 5560 | [(set (match_dup 0) |
| 34b650b3 | 5561 | (lt:SI (match_dup 1) |
| 8ef30996 MM |
5562 | (match_dup 2))) |
| 5563 | (set (match_dup 0) | |
| 5564 | (xor:SI (match_dup 0) | |
| 5565 | (const_int 1)))] | |
| 5566 | "") | |
| 5567 | ||
| bb621ad7 JW |
5568 | (define_insn "sge_di" |
| 5569 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5570 | (ge:DI (match_operand:DI 1 "register_operand" "d") | |
| 5571 | (match_operand:DI 2 "arith_operand" "dI")))] | |
| 5572 | "TARGET_64BIT && TARGET_DEBUG_C_MODE" | |
| 5573 | "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001" | |
| 5574 | [(set_attr "type" "arith") | |
| 5575 | (set_attr "mode" "DI") | |
| 5576 | (set_attr "length" "2")]) | |
| 5577 | ||
| 5578 | (define_split | |
| 5579 | [(set (match_operand:DI 0 "register_operand" "") | |
| 5580 | (ge:DI (match_operand:DI 1 "register_operand" "") | |
| 5581 | (match_operand:DI 2 "arith_operand" "")))] | |
| 5582 | "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE" | |
| 5583 | [(set (match_dup 0) | |
| 5584 | (lt:DI (match_dup 1) | |
| 5585 | (match_dup 2))) | |
| 5586 | (set (match_dup 0) | |
| 5587 | (xor:DI (match_dup 0) | |
| 5588 | (const_int 1)))] | |
| 5589 | "") | |
| 5590 | ||
| 8ef30996 MM |
5591 | (define_expand "slt" |
| 5592 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5593 | (lt:SI (match_dup 1) |
| 8ef30996 MM |
5594 | (match_dup 2)))] |
| 5595 | "" | |
| 5596 | " | |
| 5597 | { | |
| bb621ad7 | 5598 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5599 | FAIL; |
| 5600 | ||
| 5601 | /* set up operands from compare. */ | |
| 5602 | operands[1] = branch_cmp[0]; | |
| 5603 | operands[2] = branch_cmp[1]; | |
| 5604 | ||
| bb621ad7 | 5605 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5606 | { |
| 5607 | gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0); | |
| 5608 | DONE; | |
| 5609 | } | |
| 5610 | ||
| 8ef30996 MM |
5611 | /* fall through and generate default code */ |
| 5612 | }") | |
| 5613 | ||
| 5614 | (define_insn "slt_si" | |
| 5615 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5616 | (lt:SI (match_operand:SI 1 "register_operand" "d") |
| 8ef30996 MM |
5617 | (match_operand:SI 2 "arith_operand" "dI")))] |
| 5618 | "" | |
| 5619 | "slt\\t%0,%1,%2" | |
| bb621ad7 | 5620 | [(set_attr "type" "arith") |
| 8ef30996 MM |
5621 | (set_attr "mode" "SI") |
| 5622 | (set_attr "length" "1")]) | |
| 5623 | ||
| bb621ad7 JW |
5624 | (define_insn "slt_di" |
| 5625 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5626 | (lt:DI (match_operand:DI 1 "register_operand" "d") | |
| 5627 | (match_operand:DI 2 "arith_operand" "dI")))] | |
| 5628 | "TARGET_64BIT" | |
| 5629 | "slt\\t%0,%1,%2" | |
| 5630 | [(set_attr "type" "arith") | |
| 5631 | (set_attr "mode" "DI") | |
| 5632 | (set_attr "length" "1")]) | |
| 5633 | ||
| 8ef30996 MM |
5634 | (define_expand "sle" |
| 5635 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5636 | (le:SI (match_dup 1) |
| 8ef30996 MM |
5637 | (match_dup 2)))] |
| 5638 | "" | |
| 5639 | " | |
| 5640 | { | |
| bb621ad7 | 5641 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5642 | FAIL; |
| 5643 | ||
| 5644 | /* set up operands from compare. */ | |
| 5645 | operands[1] = branch_cmp[0]; | |
| 5646 | operands[2] = branch_cmp[1]; | |
| 5647 | ||
| bb621ad7 | 5648 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5649 | { |
| 5650 | gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0); | |
| 5651 | DONE; | |
| 5652 | } | |
| 5653 | ||
| 8ef30996 MM |
5654 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767) |
| 5655 | operands[2] = force_reg (SImode, operands[2]); | |
| 5656 | ||
| 5657 | /* fall through and generate default code */ | |
| 5658 | }") | |
| 5659 | ||
| 34b650b3 MM |
5660 | (define_insn "sle_si_const" |
| 5661 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5662 | (le:SI (match_operand:SI 1 "register_operand" "d") | |
| 5663 | (match_operand:SI 2 "small_int" "I")))] | |
| 5664 | "INTVAL (operands[2]) < 32767" | |
| 5665 | "* | |
| 5666 | { | |
| 5667 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1); | |
| 5668 | return \"slt\\t%0,%1,%2\"; | |
| 5669 | }" | |
| bb621ad7 | 5670 | [(set_attr "type" "arith") |
| 34b650b3 MM |
5671 | (set_attr "mode" "SI") |
| 5672 | (set_attr "length" "1")]) | |
| 5673 | ||
| bb621ad7 JW |
5674 | (define_insn "sle_di_const" |
| 5675 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5676 | (le:DI (match_operand:DI 1 "register_operand" "d") | |
| 5677 | (match_operand:DI 2 "small_int" "I")))] | |
| 5678 | "TARGET_64BIT && INTVAL (operands[2]) < 32767" | |
| 5679 | "* | |
| 5680 | { | |
| 5681 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1); | |
| 5682 | return \"slt\\t%0,%1,%2\"; | |
| 5683 | }" | |
| 5684 | [(set_attr "type" "arith") | |
| 5685 | (set_attr "mode" "DI") | |
| 5686 | (set_attr "length" "1")]) | |
| 5687 | ||
| 34b650b3 MM |
5688 | (define_insn "sle_si_reg" |
| 5689 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5690 | (le:SI (match_operand:SI 1 "register_operand" "d") | |
| 5691 | (match_operand:SI 2 "register_operand" "d")))] | |
| bbdb5552 | 5692 | "TARGET_DEBUG_C_MODE" |
| 34b650b3 | 5693 | "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001" |
| bb621ad7 | 5694 | [(set_attr "type" "arith") |
| 34b650b3 MM |
5695 | (set_attr "mode" "SI") |
| 5696 | (set_attr "length" "2")]) | |
| 8ef30996 MM |
5697 | |
| 5698 | (define_split | |
| 5699 | [(set (match_operand:SI 0 "register_operand" "") | |
| 34b650b3 | 5700 | (le:SI (match_operand:SI 1 "register_operand" "") |
| 8ef30996 | 5701 | (match_operand:SI 2 "register_operand" "")))] |
| bbdb5552 | 5702 | "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE" |
| 8ef30996 | 5703 | [(set (match_dup 0) |
| 34b650b3 | 5704 | (lt:SI (match_dup 2) |
| 8ef30996 MM |
5705 | (match_dup 1))) |
| 5706 | (set (match_dup 0) | |
| 5707 | (xor:SI (match_dup 0) | |
| 5708 | (const_int 1)))] | |
| 5709 | "") | |
| 5710 | ||
| bb621ad7 JW |
5711 | (define_insn "sle_di_reg" |
| 5712 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5713 | (le:DI (match_operand:DI 1 "register_operand" "d") | |
| 5714 | (match_operand:DI 2 "register_operand" "d")))] | |
| 5715 | "TARGET_64BIT && TARGET_DEBUG_C_MODE" | |
| 5716 | "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001" | |
| 5717 | [(set_attr "type" "arith") | |
| 5718 | (set_attr "mode" "DI") | |
| 5719 | (set_attr "length" "2")]) | |
| 5720 | ||
| 5721 | (define_split | |
| 5722 | [(set (match_operand:DI 0 "register_operand" "") | |
| 5723 | (le:DI (match_operand:DI 1 "register_operand" "") | |
| 5724 | (match_operand:DI 2 "register_operand" "")))] | |
| 5725 | "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE" | |
| 5726 | [(set (match_dup 0) | |
| 5727 | (lt:DI (match_dup 2) | |
| 5728 | (match_dup 1))) | |
| 5729 | (set (match_dup 0) | |
| 5730 | (xor:DI (match_dup 0) | |
| 5731 | (const_int 1)))] | |
| 5732 | "") | |
| 5733 | ||
| 8ef30996 MM |
5734 | (define_expand "sgtu" |
| 5735 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5736 | (gtu:SI (match_dup 1) |
| 8ef30996 MM |
5737 | (match_dup 2)))] |
| 5738 | "" | |
| 5739 | " | |
| 5740 | { | |
| bb621ad7 | 5741 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5742 | FAIL; |
| 5743 | ||
| 5744 | /* set up operands from compare. */ | |
| 5745 | operands[1] = branch_cmp[0]; | |
| 5746 | operands[2] = branch_cmp[1]; | |
| 5747 | ||
| bb621ad7 | 5748 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5749 | { |
| 5750 | gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0); | |
| 5751 | DONE; | |
| 5752 | } | |
| 5753 | ||
| 8ef30996 MM |
5754 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
| 5755 | operands[2] = force_reg (SImode, operands[2]); | |
| 5756 | ||
| 5757 | /* fall through and generate default code */ | |
| 5758 | }") | |
| 5759 | ||
| 5760 | (define_insn "sgtu_si" | |
| 5761 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5762 | (gtu:SI (match_operand:SI 1 "register_operand" "d") |
| 8ef30996 MM |
5763 | (match_operand:SI 2 "reg_or_0_operand" "dJ")))] |
| 5764 | "" | |
| 5765 | "sltu\\t%0,%z2,%1" | |
| bb621ad7 | 5766 | [(set_attr "type" "arith") |
| 8ef30996 MM |
5767 | (set_attr "mode" "SI") |
| 5768 | (set_attr "length" "1")]) | |
| 5769 | ||
| bb621ad7 JW |
5770 | (define_insn "sgtu_di" |
| 5771 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5772 | (gtu:DI (match_operand:DI 1 "register_operand" "d") | |
| 5773 | (match_operand:DI 2 "reg_or_0_operand" "dJ")))] | |
| 5774 | "TARGET_64BIT" | |
| 5775 | "sltu\\t%0,%z2,%1" | |
| 5776 | [(set_attr "type" "arith") | |
| 5777 | (set_attr "mode" "DI") | |
| 5778 | (set_attr "length" "1")]) | |
| 5779 | ||
| 8ef30996 MM |
5780 | (define_expand "sgeu" |
| 5781 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5782 | (geu:SI (match_dup 1) |
| 8ef30996 MM |
5783 | (match_dup 2)))] |
| 5784 | "" | |
| 5785 | " | |
| 5786 | { | |
| bb621ad7 | 5787 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5788 | FAIL; |
| 5789 | ||
| 5790 | /* set up operands from compare. */ | |
| 5791 | operands[1] = branch_cmp[0]; | |
| 5792 | operands[2] = branch_cmp[1]; | |
| 5793 | ||
| bb621ad7 | 5794 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5795 | { |
| 5796 | gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0); | |
| 5797 | DONE; | |
| 5798 | } | |
| 5799 | ||
| 8ef30996 MM |
5800 | /* fall through and generate default code */ |
| 5801 | }") | |
| 5802 | ||
| 5803 | (define_insn "sgeu_si" | |
| 5804 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5805 | (geu:SI (match_operand:SI 1 "register_operand" "d") |
| 8ef30996 | 5806 | (match_operand:SI 2 "arith_operand" "dI")))] |
| bbdb5552 | 5807 | "TARGET_DEBUG_C_MODE" |
| 8ef30996 | 5808 | "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001" |
| bb621ad7 | 5809 | [(set_attr "type" "arith") |
| 8ef30996 MM |
5810 | (set_attr "mode" "SI") |
| 5811 | (set_attr "length" "2")]) | |
| 5812 | ||
| 5813 | (define_split | |
| 5814 | [(set (match_operand:SI 0 "register_operand" "") | |
| 34b650b3 | 5815 | (geu:SI (match_operand:SI 1 "register_operand" "") |
| 8ef30996 | 5816 | (match_operand:SI 2 "arith_operand" "")))] |
| bbdb5552 | 5817 | "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE" |
| 8ef30996 | 5818 | [(set (match_dup 0) |
| 34b650b3 | 5819 | (ltu:SI (match_dup 1) |
| 8ef30996 MM |
5820 | (match_dup 2))) |
| 5821 | (set (match_dup 0) | |
| 5822 | (xor:SI (match_dup 0) | |
| 5823 | (const_int 1)))] | |
| 5824 | "") | |
| 5825 | ||
| bb621ad7 JW |
5826 | (define_insn "sgeu_di" |
| 5827 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5828 | (geu:DI (match_operand:DI 1 "register_operand" "d") | |
| 5829 | (match_operand:DI 2 "arith_operand" "dI")))] | |
| 5830 | "TARGET_64BIT && TARGET_DEBUG_C_MODE" | |
| 5831 | "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001" | |
| 5832 | [(set_attr "type" "arith") | |
| 5833 | (set_attr "mode" "DI") | |
| 5834 | (set_attr "length" "2")]) | |
| 5835 | ||
| 5836 | (define_split | |
| 5837 | [(set (match_operand:DI 0 "register_operand" "") | |
| 5838 | (geu:DI (match_operand:DI 1 "register_operand" "") | |
| 5839 | (match_operand:DI 2 "arith_operand" "")))] | |
| 5840 | "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE" | |
| 5841 | [(set (match_dup 0) | |
| 5842 | (ltu:DI (match_dup 1) | |
| 5843 | (match_dup 2))) | |
| 5844 | (set (match_dup 0) | |
| 5845 | (xor:DI (match_dup 0) | |
| 5846 | (const_int 1)))] | |
| 5847 | "") | |
| 5848 | ||
| 8ef30996 MM |
5849 | (define_expand "sltu" |
| 5850 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5851 | (ltu:SI (match_dup 1) |
| 8ef30996 MM |
5852 | (match_dup 2)))] |
| 5853 | "" | |
| 5854 | " | |
| 5855 | { | |
| bb621ad7 | 5856 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5857 | FAIL; |
| 5858 | ||
| 5859 | /* set up operands from compare. */ | |
| 5860 | operands[1] = branch_cmp[0]; | |
| 5861 | operands[2] = branch_cmp[1]; | |
| 5862 | ||
| bb621ad7 | 5863 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5864 | { |
| 5865 | gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0); | |
| 5866 | DONE; | |
| 5867 | } | |
| 5868 | ||
| 8ef30996 MM |
5869 | /* fall through and generate default code */ |
| 5870 | }") | |
| 5871 | ||
| 5872 | (define_insn "sltu_si" | |
| 5873 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5874 | (ltu:SI (match_operand:SI 1 "register_operand" "d") |
| 8ef30996 MM |
5875 | (match_operand:SI 2 "arith_operand" "dI")))] |
| 5876 | "" | |
| 5877 | "sltu\\t%0,%1,%2" | |
| bb621ad7 | 5878 | [(set_attr "type" "arith") |
| 8ef30996 MM |
5879 | (set_attr "mode" "SI") |
| 5880 | (set_attr "length" "1")]) | |
| 5881 | ||
| bb621ad7 JW |
5882 | (define_insn "sltu_di" |
| 5883 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5884 | (ltu:DI (match_operand:DI 1 "register_operand" "d") | |
| 5885 | (match_operand:DI 2 "arith_operand" "dI")))] | |
| 5886 | "TARGET_64BIT" | |
| 5887 | "sltu\\t%0,%1,%2" | |
| 5888 | [(set_attr "type" "arith") | |
| 5889 | (set_attr "mode" "DI") | |
| 5890 | (set_attr "length" "1")]) | |
| 5891 | ||
| 8ef30996 MM |
5892 | (define_expand "sleu" |
| 5893 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 34b650b3 | 5894 | (leu:SI (match_dup 1) |
| 8ef30996 MM |
5895 | (match_dup 2)))] |
| 5896 | "" | |
| 5897 | " | |
| 5898 | { | |
| bb621ad7 | 5899 | if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) |
| 8ef30996 MM |
5900 | FAIL; |
| 5901 | ||
| 5902 | /* set up operands from compare. */ | |
| 5903 | operands[1] = branch_cmp[0]; | |
| 5904 | operands[2] = branch_cmp[1]; | |
| 5905 | ||
| bb621ad7 | 5906 | if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) |
| 34b650b3 MM |
5907 | { |
| 5908 | gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0); | |
| 5909 | DONE; | |
| 5910 | } | |
| 5911 | ||
| 8ef30996 MM |
5912 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767) |
| 5913 | operands[2] = force_reg (SImode, operands[2]); | |
| 5914 | ||
| 5915 | /* fall through and generate default code */ | |
| 5916 | }") | |
| 5917 | ||
| 34b650b3 MM |
5918 | (define_insn "sleu_si_const" |
| 5919 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5920 | (leu:SI (match_operand:SI 1 "register_operand" "d") | |
| 5921 | (match_operand:SI 2 "small_int" "I")))] | |
| 5922 | "INTVAL (operands[2]) < 32767" | |
| 5923 | "* | |
| 5924 | { | |
| 5925 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1); | |
| 5926 | return \"sltu\\t%0,%1,%2\"; | |
| 5927 | }" | |
| bb621ad7 | 5928 | [(set_attr "type" "arith") |
| 34b650b3 MM |
5929 | (set_attr "mode" "SI") |
| 5930 | (set_attr "length" "1")]) | |
| 5931 | ||
| bb621ad7 JW |
5932 | (define_insn "sleu_di_const" |
| 5933 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5934 | (leu:DI (match_operand:DI 1 "register_operand" "d") | |
| 5935 | (match_operand:DI 2 "small_int" "I")))] | |
| 5936 | "TARGET_64BIT && INTVAL (operands[2]) < 32767" | |
| 5937 | "* | |
| 5938 | { | |
| 5939 | operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1); | |
| 5940 | return \"sltu\\t%0,%1,%2\"; | |
| 5941 | }" | |
| 5942 | [(set_attr "type" "arith") | |
| 5943 | (set_attr "mode" "DI") | |
| 5944 | (set_attr "length" "1")]) | |
| 5945 | ||
| 34b650b3 MM |
5946 | (define_insn "sleu_si_reg" |
| 5947 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5948 | (leu:SI (match_operand:SI 1 "register_operand" "d") | |
| 5949 | (match_operand:SI 2 "register_operand" "d")))] | |
| bbdb5552 | 5950 | "TARGET_DEBUG_C_MODE" |
| 34b650b3 | 5951 | "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001" |
| bb621ad7 | 5952 | [(set_attr "type" "arith") |
| 34b650b3 MM |
5953 | (set_attr "mode" "SI") |
| 5954 | (set_attr "length" "2")]) | |
| 8ef30996 MM |
5955 | |
| 5956 | (define_split | |
| 5957 | [(set (match_operand:SI 0 "register_operand" "") | |
| 34b650b3 | 5958 | (leu:SI (match_operand:SI 1 "register_operand" "") |
| 8ef30996 | 5959 | (match_operand:SI 2 "register_operand" "")))] |
| bbdb5552 | 5960 | "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE" |
| 8ef30996 | 5961 | [(set (match_dup 0) |
| 34b650b3 | 5962 | (ltu:SI (match_dup 2) |
| 8ef30996 MM |
5963 | (match_dup 1))) |
| 5964 | (set (match_dup 0) | |
| 5965 | (xor:SI (match_dup 0) | |
| 5966 | (const_int 1)))] | |
| 5967 | "") | |
| 5968 | ||
| bb621ad7 JW |
5969 | (define_insn "sleu_di_reg" |
| 5970 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5971 | (leu:DI (match_operand:DI 1 "register_operand" "d") | |
| 5972 | (match_operand:DI 2 "register_operand" "d")))] | |
| 5973 | "TARGET_64BIT && TARGET_DEBUG_C_MODE" | |
| 5974 | "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001" | |
| 5975 | [(set_attr "type" "arith") | |
| 5976 | (set_attr "mode" "DI") | |
| 5977 | (set_attr "length" "2")]) | |
| 5978 | ||
| 5979 | (define_split | |
| 5980 | [(set (match_operand:DI 0 "register_operand" "") | |
| 5981 | (leu:DI (match_operand:DI 1 "register_operand" "") | |
| 5982 | (match_operand:DI 2 "register_operand" "")))] | |
| 5983 | "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE" | |
| 5984 | [(set (match_dup 0) | |
| 5985 | (ltu:DI (match_dup 2) | |
| 5986 | (match_dup 1))) | |
| 5987 | (set (match_dup 0) | |
| 5988 | (xor:DI (match_dup 0) | |
| 5989 | (const_int 1)))] | |
| 5990 | "") | |
| 5991 | ||
| 34b650b3 MM |
5992 | \f |
| 5993 | ;; | |
| 5994 | ;; .................... | |
| 5995 | ;; | |
| 5996 | ;; FLOATING POINT COMPARISONS | |
| 5997 | ;; | |
| 5998 | ;; .................... | |
| 5999 | ||
| 6000 | (define_insn "seq_df" | |
| b8eb88d0 ILT |
6001 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6002 | (eq:CC (match_operand:DF 1 "register_operand" "f") | |
| 6003 | (match_operand:DF 2 "register_operand" "f")))] | |
| 46299de9 | 6004 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 34b650b3 MM |
6005 | "* |
| 6006 | { | |
| b8eb88d0 | 6007 | return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6008 | }" |
| 6009 | [(set_attr "type" "fcmp") | |
| 6010 | (set_attr "mode" "FPSW") | |
| 6011 | (set_attr "length" "1")]) | |
| 6012 | ||
| 6013 | (define_insn "slt_df" | |
| b8eb88d0 ILT |
6014 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6015 | (lt:CC (match_operand:DF 1 "register_operand" "f") | |
| 6016 | (match_operand:DF 2 "register_operand" "f")))] | |
| 46299de9 | 6017 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 34b650b3 MM |
6018 | "* |
| 6019 | { | |
| b8eb88d0 | 6020 | return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6021 | }" |
| 6022 | [(set_attr "type" "fcmp") | |
| 6023 | (set_attr "mode" "FPSW") | |
| 6024 | (set_attr "length" "1")]) | |
| 6025 | ||
| 6026 | (define_insn "sle_df" | |
| b8eb88d0 ILT |
6027 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6028 | (le:CC (match_operand:DF 1 "register_operand" "f") | |
| 6029 | (match_operand:DF 2 "register_operand" "f")))] | |
| 46299de9 | 6030 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 34b650b3 MM |
6031 | "* |
| 6032 | { | |
| b8eb88d0 | 6033 | return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6034 | }" |
| 6035 | [(set_attr "type" "fcmp") | |
| 6036 | (set_attr "mode" "FPSW") | |
| 6037 | (set_attr "length" "1")]) | |
| 6038 | ||
| 6039 | (define_insn "sgt_df" | |
| b8eb88d0 ILT |
6040 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6041 | (gt:CC (match_operand:DF 1 "register_operand" "f") | |
| 6042 | (match_operand:DF 2 "register_operand" "f")))] | |
| 46299de9 | 6043 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 34b650b3 MM |
6044 | "* |
| 6045 | { | |
| b8eb88d0 | 6046 | return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6047 | }" |
| 6048 | [(set_attr "type" "fcmp") | |
| 6049 | (set_attr "mode" "FPSW") | |
| 6050 | (set_attr "length" "1")]) | |
| 6051 | ||
| 6052 | (define_insn "sge_df" | |
| b8eb88d0 ILT |
6053 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6054 | (ge:CC (match_operand:DF 1 "register_operand" "f") | |
| 6055 | (match_operand:DF 2 "register_operand" "f")))] | |
| 46299de9 | 6056 | "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| 34b650b3 MM |
6057 | "* |
| 6058 | { | |
| b8eb88d0 | 6059 | return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6060 | }" |
| 6061 | [(set_attr "type" "fcmp") | |
| 6062 | (set_attr "mode" "FPSW") | |
| 6063 | (set_attr "length" "1")]) | |
| 6064 | ||
| 6065 | (define_insn "seq_sf" | |
| b8eb88d0 ILT |
6066 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6067 | (eq:CC (match_operand:SF 1 "register_operand" "f") | |
| 6068 | (match_operand:SF 2 "register_operand" "f")))] | |
| bb621ad7 | 6069 | "TARGET_HARD_FLOAT" |
| 34b650b3 MM |
6070 | "* |
| 6071 | { | |
| b8eb88d0 | 6072 | return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6073 | }" |
| 6074 | [(set_attr "type" "fcmp") | |
| 6075 | (set_attr "mode" "FPSW") | |
| 6076 | (set_attr "length" "1")]) | |
| 6077 | ||
| 6078 | (define_insn "slt_sf" | |
| b8eb88d0 ILT |
6079 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6080 | (lt:CC (match_operand:SF 1 "register_operand" "f") | |
| 6081 | (match_operand:SF 2 "register_operand" "f")))] | |
| bb621ad7 | 6082 | "TARGET_HARD_FLOAT" |
| 34b650b3 MM |
6083 | "* |
| 6084 | { | |
| b8eb88d0 | 6085 | return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6086 | }" |
| 6087 | [(set_attr "type" "fcmp") | |
| 6088 | (set_attr "mode" "FPSW") | |
| 6089 | (set_attr "length" "1")]) | |
| 6090 | ||
| 6091 | (define_insn "sle_sf" | |
| b8eb88d0 ILT |
6092 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6093 | (le:CC (match_operand:SF 1 "register_operand" "f") | |
| 6094 | (match_operand:SF 2 "register_operand" "f")))] | |
| bb621ad7 | 6095 | "TARGET_HARD_FLOAT" |
| 34b650b3 MM |
6096 | "* |
| 6097 | { | |
| b8eb88d0 | 6098 | return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6099 | }" |
| 6100 | [(set_attr "type" "fcmp") | |
| 6101 | (set_attr "mode" "FPSW") | |
| 6102 | (set_attr "length" "1")]) | |
| 6103 | ||
| 6104 | (define_insn "sgt_sf" | |
| b8eb88d0 ILT |
6105 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6106 | (gt:CC (match_operand:SF 1 "register_operand" "f") | |
| 6107 | (match_operand:SF 2 "register_operand" "f")))] | |
| bb621ad7 | 6108 | "TARGET_HARD_FLOAT" |
| 34b650b3 MM |
6109 | "* |
| 6110 | { | |
| b8eb88d0 | 6111 | return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6112 | }" |
| 6113 | [(set_attr "type" "fcmp") | |
| 6114 | (set_attr "mode" "FPSW") | |
| 6115 | (set_attr "length" "1")]) | |
| 6116 | ||
| 6117 | (define_insn "sge_sf" | |
| b8eb88d0 ILT |
6118 | [(set (match_operand:CC 0 "register_operand" "=z") |
| 6119 | (ge:CC (match_operand:SF 1 "register_operand" "f") | |
| 6120 | (match_operand:SF 2 "register_operand" "f")))] | |
| bb621ad7 | 6121 | "TARGET_HARD_FLOAT" |
| 34b650b3 MM |
6122 | "* |
| 6123 | { | |
| b8eb88d0 | 6124 | return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); |
| 34b650b3 MM |
6125 | }" |
| 6126 | [(set_attr "type" "fcmp") | |
| 6127 | (set_attr "mode" "FPSW") | |
| 6128 | (set_attr "length" "1")]) | |
| 6129 | ||
| 8ef30996 MM |
6130 | \f |
| 6131 | ;; | |
| 6132 | ;; .................... | |
| 6133 | ;; | |
| 6134 | ;; UNCONDITIONAL BRANCHES | |
| 6135 | ;; | |
| 6136 | ;; .................... | |
| 6137 | ||
| 6138 | ;; Unconditional branches. | |
| 6139 | ||
| 6140 | (define_insn "jump" | |
| 6141 | [(set (pc) | |
| 6142 | (label_ref (match_operand 0 "" "")))] | |
| 6143 | "" | |
| 6144 | "* | |
| 6145 | { | |
| 6146 | if (GET_CODE (operands[0]) == REG) | |
| 6147 | return \"%*j\\t%0\"; | |
| e19ff60f JW |
6148 | /* ??? I don't know why this is necessary. This works around an |
| 6149 | assembler problem that appears when a label is defined, then referenced | |
| 6150 | in a switch table, then used in a `j' instruction. */ | |
| 694aa3f2 | 6151 | else if (mips_abi != ABI_32) |
| e19ff60f JW |
6152 | return \"%*b\\t%l0\"; |
| 6153 | else | |
| 8ef30996 MM |
6154 | return \"%*j\\t%l0\"; |
| 6155 | }" | |
| 6156 | [(set_attr "type" "jump") | |
| 6157 | (set_attr "mode" "none") | |
| 6158 | (set_attr "length" "1")]) | |
| 6159 | ||
| bb621ad7 JW |
6160 | (define_expand "indirect_jump" |
| 6161 | [(set (pc) (match_operand 0 "register_operand" "d"))] | |
| 8ef30996 | 6162 | "" |
| bb621ad7 JW |
6163 | " |
| 6164 | { | |
| 6165 | rtx dest; | |
| 6166 | ||
| 6167 | if (operands[0]) /* eliminate unused code warnings */ | |
| 6168 | { | |
| 6169 | dest = operands[0]; | |
| 6170 | if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode) | |
| 6171 | operands[0] = copy_to_mode_reg (Pmode, dest); | |
| 6172 | ||
| 6173 | if (!TARGET_LONG64) | |
| 6174 | emit_jump_insn (gen_indirect_jump_internal1 (operands[0])); | |
| 6175 | else | |
| 6176 | emit_jump_insn (gen_indirect_jump_internal2 (operands[0])); | |
| 6177 | ||
| 6178 | DONE; | |
| 6179 | } | |
| 6180 | }") | |
| 6181 | ||
| 6182 | (define_insn "indirect_jump_internal1" | |
| 6183 | [(set (pc) (match_operand:SI 0 "register_operand" "d"))] | |
| 6184 | "!TARGET_LONG64" | |
| 6185 | "%*j\\t%0" | |
| 6186 | [(set_attr "type" "jump") | |
| 6187 | (set_attr "mode" "none") | |
| 6188 | (set_attr "length" "1")]) | |
| 6189 | ||
| 6190 | (define_insn "indirect_jump_internal2" | |
| 6191 | [(set (pc) (match_operand:DI 0 "register_operand" "d"))] | |
| 6192 | "TARGET_LONG64" | |
| 8ef30996 MM |
6193 | "%*j\\t%0" |
| 6194 | [(set_attr "type" "jump") | |
| 6195 | (set_attr "mode" "none") | |
| 6196 | (set_attr "length" "1")]) | |
| 6197 | ||
| bb621ad7 | 6198 | (define_expand "tablejump" |
| 8ef30996 | 6199 | [(set (pc) |
| bb621ad7 | 6200 | (match_operand 0 "register_operand" "d")) |
| 8ef30996 MM |
6201 | (use (label_ref (match_operand 1 "" "")))] |
| 6202 | "" | |
| bb621ad7 JW |
6203 | " |
| 6204 | { | |
| 6205 | rtx dest; | |
| 6206 | ||
| 6207 | if (operands[0]) /* eliminate unused code warnings */ | |
| 6208 | { | |
| 6209 | if (GET_MODE (operands[0]) != Pmode) | |
| 6210 | abort (); | |
| 6211 | ||
| 9fa0af71 JW |
6212 | if (! flag_pic) |
| 6213 | { | |
| 6214 | if (!TARGET_LONG64) | |
| 6215 | emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); | |
| 6216 | else | |
| 6217 | emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); | |
| 6218 | } | |
| bb621ad7 | 6219 | else |
| 9fa0af71 JW |
6220 | { |
| 6221 | if (!TARGET_LONG64) | |
| 6222 | emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); | |
| 6223 | else | |
| 6224 | emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); | |
| 6225 | } | |
| bb621ad7 JW |
6226 | |
| 6227 | DONE; | |
| 6228 | } | |
| 6229 | }") | |
| 6230 | ||
| 6231 | (define_insn "tablejump_internal1" | |
| 6232 | [(set (pc) | |
| 6233 | (match_operand:SI 0 "register_operand" "d")) | |
| 6234 | (use (label_ref (match_operand 1 "" "")))] | |
| 6235 | "!TARGET_LONG64" | |
| 9fa0af71 | 6236 | "%*j\\t%0" |
| bb621ad7 JW |
6237 | [(set_attr "type" "jump") |
| 6238 | (set_attr "mode" "none") | |
| 9fa0af71 | 6239 | (set_attr "length" "1")]) |
| bb621ad7 JW |
6240 | |
| 6241 | (define_insn "tablejump_internal2" | |
| 6242 | [(set (pc) | |
| 6243 | (match_operand:DI 0 "register_operand" "d")) | |
| 6244 | (use (label_ref (match_operand 1 "" "")))] | |
| 6245 | "TARGET_LONG64" | |
| 9fa0af71 JW |
6246 | "%*j\\t%0" |
| 6247 | [(set_attr "type" "jump") | |
| 6248 | (set_attr "mode" "none") | |
| 6249 | (set_attr "length" "1")]) | |
| 6250 | ||
| 6251 | (define_expand "tablejump_internal3" | |
| 6252 | [(set (pc) | |
| 6253 | (plus:SI (match_operand:SI 0 "register_operand" "d") | |
| 6254 | (label_ref:SI (match_operand:SI 1 "" ""))))] | |
| 6255 | "" | |
| 6256 | "") | |
| 6257 | ||
| 6258 | ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise | |
| 6259 | ;;; it is not valid. | |
| 6260 | ||
| 6261 | ;;; ??? The length depends on the ABI. It is two for o32, and one for n32. | |
| 6262 | ;;; We just use the conservative number here. | |
| 6263 | ||
| 6264 | (define_insn "" | |
| 6265 | [(set (pc) | |
| 6266 | (plus:SI (match_operand:SI 0 "register_operand" "d") | |
| 6267 | (label_ref:SI (match_operand:SI 1 "" ""))))] | |
| 6268 | "!TARGET_LONG64 && next_active_insn (insn) != 0 | |
| 6269 | && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC | |
| 6270 | && PREV_INSN (next_active_insn (insn)) == operands[1]" | |
| 5a5b76a2 JW |
6271 | "* |
| 6272 | { | |
| 9fa0af71 JW |
6273 | /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic. */ |
| 6274 | if (mips_abi == ABI_32) | |
| e19ff60f | 6275 | output_asm_insn (\".cpadd\\t%0\", operands); |
| 5a5b76a2 JW |
6276 | return \"%*j\\t%0\"; |
| 6277 | }" | |
| 8ef30996 MM |
6278 | [(set_attr "type" "jump") |
| 6279 | (set_attr "mode" "none") | |
| 9fa0af71 JW |
6280 | (set_attr "length" "2")]) |
| 6281 | ||
| 6282 | (define_expand "tablejump_internal4" | |
| 6283 | [(set (pc) | |
| 6284 | (plus:DI (match_operand:DI 0 "register_operand" "d") | |
| 6285 | (label_ref:DI (match_operand:SI 1 "" ""))))] | |
| 6286 | "" | |
| 6287 | "") | |
| 6288 | ||
| 6289 | ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise | |
| 6290 | ;;; it is not valid. | |
| 6291 | ||
| 6292 | (define_insn "" | |
| 6293 | [(set (pc) | |
| 6294 | (plus:DI (match_operand:DI 0 "register_operand" "d") | |
| 6295 | (label_ref:DI (match_operand:SI 1 "" ""))))] | |
| b067d889 | 6296 | "TARGET_LONG64 && next_active_insn (insn) != 0 |
| 9fa0af71 JW |
6297 | && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC |
| 6298 | && PREV_INSN (next_active_insn (insn)) == operands[1]" | |
| 6299 | "%*j\\t%0" | |
| 6300 | [(set_attr "type" "jump") | |
| 6301 | (set_attr "mode" "none") | |
| 6302 | (set_attr "length" "1")]) | |
| 8ef30996 MM |
6303 | |
| 6304 | ;; Function return, only allow after optimization, so that we can | |
| 6305 | ;; eliminate jumps to jumps if no stack space is used. | |
| 6306 | ||
| 0fb5ac6f MM |
6307 | ;; (define_expand "return" |
| 6308 | ;; [(set (pc) (reg:SI 31))] | |
| 6309 | ;; "simple_epilogue_p ()" | |
| 6310 | ;; "") | |
| 6311 | ||
| 6312 | (define_expand "return" | |
| 6313 | [(parallel [(return) | |
| 6314 | (use (reg:SI 31))])] | |
| 6315 | "simple_epilogue_p ()" | |
| 6316 | "") | |
| 6317 | ||
| 6318 | (define_insn "return_internal" | |
| 6319 | [(parallel [(return) | |
| 6320 | (use (match_operand:SI 0 "register_operand" "d"))])] | |
| 6321 | "" | |
| 6322 | "%*j\\t%0" | |
| 8ef30996 MM |
6323 | [(set_attr "type" "jump") |
| 6324 | (set_attr "mode" "none") | |
| 6325 | (set_attr "length" "1")]) | |
| 6326 | ||
| e0bfcea5 ILT |
6327 | ;; Implement a switch statement when generating embedded PIC code. |
| 6328 | ;; Switches are implemented by `tablejump' when not using -membedded-pic. | |
| 6329 | ||
| 6330 | (define_expand "casesi" | |
| 6331 | [(set (match_dup 5) | |
| 6332 | (minus:SI (match_operand:SI 0 "register_operand" "d") | |
| 6333 | (match_operand:SI 1 "arith_operand" "dI"))) | |
| 6334 | (set (cc0) | |
| 6335 | (compare:CC (match_dup 5) | |
| 6336 | (match_operand:SI 2 "arith_operand" ""))) | |
| 6337 | (set (pc) | |
| 6338 | (if_then_else (gtu (cc0) | |
| 6339 | (const_int 0)) | |
| 6340 | (label_ref (match_operand 4 "" "")) | |
| 6341 | (pc))) | |
| 6342 | (parallel | |
| 6343 | [(set (pc) | |
| 6344 | (mem:SI (plus:SI (mult:SI (match_dup 5) | |
| 6345 | (const_int 4)) | |
| 6346 | (label_ref (match_operand 3 "" ""))))) | |
| 6347 | (clobber (match_scratch:SI 6 "")) | |
| 6348 | (clobber (reg:SI 31))])] | |
| 6349 | "TARGET_EMBEDDED_PIC" | |
| 6350 | " | |
| 6351 | { | |
| 6352 | /* We need slightly different code for eight byte table entries. */ | |
| 6353 | if (TARGET_LONG64) | |
| 6354 | abort (); | |
| 6355 | ||
| 6356 | if (operands[0]) | |
| 6357 | { | |
| 6358 | rtx reg = gen_reg_rtx (SImode); | |
| 6359 | ||
| e0bfcea5 ILT |
6360 | /* If the index is too large, go to the default label. */ |
| 6361 | emit_insn (gen_subsi3 (reg, operands[0], operands[1])); | |
| 6362 | emit_insn (gen_cmpsi (reg, operands[2])); | |
| 6363 | emit_insn (gen_bgtu (operands[4])); | |
| 6364 | ||
| 6365 | /* Do the PIC jump. */ | |
| 6366 | emit_insn (gen_casesi_internal (reg, operands[3], gen_reg_rtx (SImode))); | |
| 6367 | ||
| 6368 | DONE; | |
| 6369 | } | |
| 6370 | }") | |
| 6371 | ||
| 6372 | ;; An embedded PIC switch statement looks like this: | |
| 6373 | ;; bal $LS1 | |
| 6374 | ;; sll $reg,$index,2 | |
| 6375 | ;; $LS1: | |
| 6376 | ;; addu $reg,$reg,$31 | |
| 6377 | ;; lw $reg,$L1-$LS1($reg) | |
| 6378 | ;; addu $reg,$reg,$31 | |
| 6379 | ;; j $reg | |
| 6380 | ;; $L1: | |
| 6381 | ;; .word case1-$LS1 | |
| 6382 | ;; .word case2-$LS1 | |
| 6383 | ;; ... | |
| 6384 | ||
| 6385 | (define_insn "casesi_internal" | |
| 6386 | [(set (pc) | |
| 6387 | (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d") | |
| 6388 | (const_int 4)) | |
| 6389 | (label_ref (match_operand 1 "" ""))))) | |
| 6390 | (clobber (match_operand:SI 2 "register_operand" "d")) | |
| 6391 | (clobber (reg:SI 31))] | |
| 6392 | "TARGET_EMBEDDED_PIC" | |
| 6393 | "* | |
| 6394 | { | |
| 6395 | output_asm_insn (\"%(bal\\t%S1\;sll\\t%0,2\\n%S1:\", operands); | |
| 6396 | output_asm_insn (\"addu\\t%0,%0,$31%)\", operands); | |
| 6397 | output_asm_insn (\"lw\\t%0,%1-%S1(%0)\;addu\\t%0,%0,$31\", operands); | |
| 6398 | return \"j\\t%0\"; | |
| 6399 | }" | |
| 6400 | [(set_attr "type" "jump") | |
| 6401 | (set_attr "mode" "none") | |
| 6402 | (set_attr "length" "6")]) | |
| 6403 | ||
| 0fb5ac6f MM |
6404 | \f |
| 6405 | ;; | |
| 6406 | ;; .................... | |
| 6407 | ;; | |
| 6408 | ;; Function prologue/epilogue | |
| 6409 | ;; | |
| 6410 | ;; .................... | |
| 6411 | ;; | |
| 6412 | ||
| 6413 | (define_expand "prologue" | |
| 6414 | [(const_int 1)] | |
| 6415 | "" | |
| 6416 | " | |
| 6417 | { | |
| 6418 | if (mips_isa >= 0) /* avoid unused code warnings */ | |
| 6419 | { | |
| 6420 | mips_expand_prologue (); | |
| 6421 | DONE; | |
| 6422 | } | |
| 6423 | }") | |
| 6424 | ||
| d8d5b1e1 MM |
6425 | ;; Block any insns from being moved before this point, since the |
| 6426 | ;; profiling call to mcount can use various registers that aren't | |
| 6427 | ;; saved or used to pass arguments. | |
| 6428 | ||
| 6429 | (define_insn "blockage" | |
| 6430 | [(unspec_volatile [(const_int 0)] 0)] | |
| 6431 | "" | |
| 6432 | "" | |
| 6433 | [(set_attr "type" "unknown") | |
| 6434 | (set_attr "mode" "none") | |
| 6435 | (set_attr "length" "0")]) | |
| 6436 | ||
| 0fb5ac6f MM |
6437 | ;; At present, don't expand the epilogue, reorg.c will clobber the |
| 6438 | ;; return register in compiling gen_lowpart (emit-rtl.c). | |
| 6439 | ;; | |
| 6440 | ;; (define_expand "epilogue" | |
| 6441 | ;; [(const_int 2)] | |
| 6442 | ;; "" | |
| 6443 | ;; " | |
| 6444 | ;; { | |
| 6445 | ;; if (mips_isa >= 0) /* avoid unused code warnings */ | |
| 6446 | ;; { | |
| 6447 | ;; mips_expand_epilogue (); | |
| 6448 | ;; DONE; | |
| 6449 | ;; } | |
| 6450 | ;; }") | |
| 6451 | ||
| 92544bdf ILT |
6452 | ;; When generating embedded PIC code we need to get the address of the |
| 6453 | ;; current function. This specialized instruction does just that. | |
| 6454 | ||
| 6455 | (define_insn "get_fnaddr" | |
| 0d3b5987 | 6456 | [(set (match_operand 0 "register_operand" "=d") |
| 92544bdf ILT |
6457 | (unspec [(match_operand 1 "" "")] 1)) |
| 6458 | (clobber (reg:SI 31))] | |
| 6459 | "TARGET_EMBEDDED_PIC | |
| 6460 | && GET_CODE (operands[1]) == SYMBOL_REF" | |
| 6461 | "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31" | |
| 6462 | [(set_attr "type" "call") | |
| 6463 | (set_attr "mode" "none") | |
| 6464 | (set_attr "length" "4")]) | |
| 6465 | ||
| 8ef30996 MM |
6466 | \f |
| 6467 | ;; | |
| 6468 | ;; .................... | |
| 6469 | ;; | |
| 6470 | ;; FUNCTION CALLS | |
| 6471 | ;; | |
| 6472 | ;; .................... | |
| 6473 | ||
| 6474 | ;; calls.c now passes a third argument, make saber happy | |
| 6475 | ||
| 6476 | (define_expand "call" | |
| af4a697f | 6477 | [(parallel [(call (match_operand 0 "memory_operand" "m") |
| 8ef30996 | 6478 | (match_operand 1 "" "i")) |
| 3f1f8d8c MM |
6479 | (clobber (reg:SI 31)) |
| 6480 | (use (match_operand 2 "" "")) ;; next_arg_reg | |
| 6481 | (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx | |
| 8ef30996 MM |
6482 | "" |
| 6483 | " | |
| 6484 | { | |
| 6485 | rtx addr; | |
| 6486 | ||
| 3f1f8d8c MM |
6487 | if (operands[0]) /* eliminate unused code warnings */ |
| 6488 | { | |
| 6489 | addr = XEXP (operands[0], 0); | |
| 322dce45 | 6490 | if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS)) |
| aa4e54c4 | 6491 | || ! call_insn_operand (addr, VOIDmode)) |
| 322dce45 | 6492 | XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr); |
| 3f1f8d8c MM |
6493 | |
| 6494 | /* In order to pass small structures by value in registers | |
| 6495 | compatibly with the MIPS compiler, we need to shift the value | |
| 6496 | into the high part of the register. Function_arg has encoded | |
| 6497 | a PARALLEL rtx, holding a vector of adjustments to be made | |
| 6498 | as the next_arg_reg variable, so we split up the insns, | |
| 6499 | and emit them separately. */ | |
| 6500 | ||
| 6501 | if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL) | |
| 6502 | { | |
| 6503 | rtvec adjust = XVEC (operands[2], 0); | |
| 6504 | int num = GET_NUM_ELEM (adjust); | |
| 6505 | int i; | |
| 6506 | ||
| 6507 | for (i = 0; i < num; i++) | |
| 6508 | emit_insn (RTVEC_ELT (adjust, i)); | |
| 6509 | } | |
| 8ef30996 | 6510 | |
| aa4e54c4 | 6511 | emit_call_insn (gen_call_internal0 (operands[0], operands[1], |
| bb621ad7 | 6512 | gen_rtx (REG, SImode, GP_REG_FIRST + 31))); |
| 3f1f8d8c MM |
6513 | DONE; |
| 6514 | } | |
| 8ef30996 MM |
6515 | }") |
| 6516 | ||
| aa4e54c4 JW |
6517 | (define_expand "call_internal0" |
| 6518 | [(parallel [(call (match_operand 0 "" "") | |
| 6519 | (match_operand 1 "" "")) | |
| 6520 | (clobber (match_operand:SI 2 "" ""))])] | |
| 6521 | "" | |
| 6522 | "") | |
| 6523 | ||
| d1399bd0 | 6524 | (define_insn "call_internal1" |
| aa4e54c4 | 6525 | [(call (mem (match_operand 0 "call_insn_operand" "ri")) |
| 8ef30996 MM |
6526 | (match_operand 1 "" "i")) |
| 6527 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| 84a92af4 | 6528 | "!TARGET_ABICALLS && !TARGET_LONG_CALLS" |
| 8ef30996 MM |
6529 | "* |
| 6530 | { | |
| aa4e54c4 | 6531 | register rtx target = operands[0]; |
| 8ef30996 MM |
6532 | |
| 6533 | if (GET_CODE (target) == SYMBOL_REF) | |
| 6534 | return \"%*jal\\t%0\"; | |
| 2bba3a75 | 6535 | else if (GET_CODE (target) == CONST_INT) |
| 5aae9091 | 6536 | return \"%[li\\t%@,%0\\n\\t%*jal\\t%2,%@%]\"; |
| 8ef30996 | 6537 | else |
| 5aae9091 | 6538 | return \"%*jal\\t%2,%0\"; |
| 8ef30996 MM |
6539 | }" |
| 6540 | [(set_attr "type" "call") | |
| 6541 | (set_attr "mode" "none") | |
| 6542 | (set_attr "length" "1")]) | |
| 6543 | ||
| d1399bd0 | 6544 | (define_insn "call_internal2" |
| aa4e54c4 | 6545 | [(call (mem (match_operand 0 "call_insn_operand" "ri")) |
| 84a92af4 JW |
6546 | (match_operand 1 "" "i")) |
| 6547 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| 6548 | "TARGET_ABICALLS && !TARGET_LONG_CALLS" | |
| 6549 | "* | |
| 6550 | { | |
| aa4e54c4 | 6551 | register rtx target = operands[0]; |
| 84a92af4 JW |
6552 | |
| 6553 | if (GET_CODE (target) == SYMBOL_REF) | |
| 84a92af4 | 6554 | { |
| 5aae9091 JW |
6555 | if (GET_MODE (target) == SImode) |
| 6556 | return \"la\\t%^,%0\\n\\tjal\\t%2,%^\"; | |
| 84a92af4 | 6557 | else |
| 5aae9091 | 6558 | return \"dla\\t%^,%0\\n\\tjal\\t%2,%^\"; |
| 84a92af4 | 6559 | } |
| 5aae9091 JW |
6560 | else if (GET_CODE (target) == CONST_INT) |
| 6561 | return \"li\\t%^,%0\\n\\tjal\\t%2,%^\"; | |
| 6562 | else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM) | |
| 6563 | return \"move\\t%^,%0\\n\\tjal\\t%2,%^\"; | |
| 6564 | else | |
| 6565 | return \"jal\\t%2,%0\"; | |
| 84a92af4 JW |
6566 | }" |
| 6567 | [(set_attr "type" "call") | |
| 6568 | (set_attr "mode" "none") | |
| 6569 | (set_attr "length" "2")]) | |
| 6570 | ||
| bb621ad7 | 6571 | (define_insn "call_internal3a" |
| d1399bd0 MM |
6572 | [(call (mem:SI (match_operand:SI 0 "register_operand" "r")) |
| 6573 | (match_operand 1 "" "i")) | |
| 6574 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| bb621ad7 JW |
6575 | "!TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS" |
| 6576 | "%*jal\\t%2,%0" | |
| 6577 | [(set_attr "type" "call") | |
| 6578 | (set_attr "mode" "none") | |
| 6579 | (set_attr "length" "1")]) | |
| 6580 | ||
| 6581 | (define_insn "call_internal3b" | |
| 6582 | [(call (mem:DI (match_operand:DI 0 "register_operand" "r")) | |
| 6583 | (match_operand 1 "" "i")) | |
| 6584 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| 6585 | "TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS" | |
| d1399bd0 MM |
6586 | "%*jal\\t%2,%0" |
| 6587 | [(set_attr "type" "call") | |
| 6588 | (set_attr "mode" "none") | |
| 6589 | (set_attr "length" "1")]) | |
| 6590 | ||
| bb621ad7 | 6591 | (define_insn "call_internal4a" |
| 84a92af4 JW |
6592 | [(call (mem:SI (match_operand:SI 0 "register_operand" "r")) |
| 6593 | (match_operand 1 "" "i")) | |
| 6594 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| bb621ad7 | 6595 | "!TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS" |
| 84a92af4 JW |
6596 | "* |
| 6597 | { | |
| 6598 | if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM) | |
| 6599 | return \"move\\t%^,%0\\n\\tjal\\t%2,%^\"; | |
| 6600 | else | |
| 6601 | return \"jal\\t%2,%0\"; | |
| 6602 | }" | |
| 6603 | [(set_attr "type" "call") | |
| 6604 | (set_attr "mode" "none") | |
| 6605 | (set_attr "length" "2")]) | |
| 6606 | ||
| bb621ad7 JW |
6607 | (define_insn "call_internal4b" |
| 6608 | [(call (mem:DI (match_operand:DI 0 "register_operand" "r")) | |
| 6609 | (match_operand 1 "" "i")) | |
| 6610 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| 6611 | "TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS" | |
| 6612 | "* | |
| 6613 | { | |
| 6614 | if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM) | |
| 6615 | return \"move\\t%^,%0\\n\\tjal\\t%2,%^\"; | |
| 6616 | else | |
| 6617 | return \"jal\\t%2,%0\"; | |
| 6618 | }" | |
| 6619 | [(set_attr "type" "call") | |
| 6620 | (set_attr "mode" "none") | |
| 6621 | (set_attr "length" "2")]) | |
| d1399bd0 | 6622 | |
| 8ef30996 MM |
6623 | ;; calls.c now passes a fourth argument, make saber happy |
| 6624 | ||
| 6625 | (define_expand "call_value" | |
| 6626 | [(parallel [(set (match_operand 0 "register_operand" "=df") | |
| af4a697f | 6627 | (call (match_operand 1 "memory_operand" "m") |
| 8ef30996 | 6628 | (match_operand 2 "" "i"))) |
| 3f1f8d8c MM |
6629 | (clobber (reg:SI 31)) |
| 6630 | (use (match_operand 3 "" ""))])] ;; next_arg_reg | |
| 8ef30996 MM |
6631 | "" |
| 6632 | " | |
| 6633 | { | |
| 6634 | rtx addr; | |
| 6635 | ||
| 3f1f8d8c MM |
6636 | if (operands[0]) /* eliminate unused code warning */ |
| 6637 | { | |
| 6638 | addr = XEXP (operands[1], 0); | |
| 322dce45 | 6639 | if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS)) |
| aa4e54c4 | 6640 | || ! call_insn_operand (addr, VOIDmode)) |
| 322dce45 | 6641 | XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr); |
| 3f1f8d8c MM |
6642 | |
| 6643 | /* In order to pass small structures by value in registers | |
| 6644 | compatibly with the MIPS compiler, we need to shift the value | |
| 6645 | into the high part of the register. Function_arg has encoded | |
| 6646 | a PARALLEL rtx, holding a vector of adjustments to be made | |
| 6647 | as the next_arg_reg variable, so we split up the insns, | |
| 6648 | and emit them separately. */ | |
| 6649 | ||
| 6650 | if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL) | |
| 6651 | { | |
| 6652 | rtvec adjust = XVEC (operands[3], 0); | |
| 6653 | int num = GET_NUM_ELEM (adjust); | |
| 6654 | int i; | |
| 6655 | ||
| 6656 | for (i = 0; i < num; i++) | |
| 6657 | emit_insn (RTVEC_ELT (adjust, i)); | |
| 6658 | } | |
| 6659 | ||
| bd16a708 JW |
6660 | /* Handle Irix6 function calls that have multiple non-contiguous |
| 6661 | results. */ | |
| f7a61b83 | 6662 | if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1) |
| bd16a708 | 6663 | { |
| aa4e54c4 | 6664 | emit_call_insn (gen_call_value_multiple_internal0 |
| bd16a708 JW |
6665 | (XEXP (XVECEXP (operands[0], 0, 0), 0), |
| 6666 | operands[1], operands[2], | |
| 6667 | XEXP (XVECEXP (operands[0], 0, 1), 0), | |
| 6668 | gen_rtx (REG, SImode, GP_REG_FIRST + 31))); | |
| 6669 | DONE; | |
| 6670 | } | |
| 6671 | ||
| f7a61b83 JW |
6672 | /* We have a call returning a DImode structure in an FP reg. |
| 6673 | Strip off the now unnecessary PARALLEL. */ | |
| 6674 | if (GET_CODE (operands[0]) == PARALLEL) | |
| 6675 | operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0); | |
| 6676 | ||
| aa4e54c4 | 6677 | emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2], |
| 5aae9091 | 6678 | gen_rtx (REG, SImode, GP_REG_FIRST + 31))); |
| 3f1f8d8c MM |
6679 | |
| 6680 | DONE; | |
| 6681 | } | |
| 8ef30996 MM |
6682 | }") |
| 6683 | ||
| aa4e54c4 JW |
6684 | (define_expand "call_value_internal0" |
| 6685 | [(parallel [(set (match_operand 0 "" "") | |
| 6686 | (call (match_operand 1 "" "") | |
| 6687 | (match_operand 2 "" ""))) | |
| 6688 | (clobber (match_operand:SI 3 "" ""))])] | |
| 6689 | "" | |
| 6690 | "") | |
| 6691 | ||
| d1399bd0 | 6692 | (define_insn "call_value_internal1" |
| 8ef30996 | 6693 | [(set (match_operand 0 "register_operand" "=df") |
| aa4e54c4 | 6694 | (call (mem (match_operand 1 "call_insn_operand" "ri")) |
| 8ef30996 MM |
6695 | (match_operand 2 "" "i"))) |
| 6696 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| 84a92af4 | 6697 | "!TARGET_ABICALLS && !TARGET_LONG_CALLS" |
| 8ef30996 MM |
6698 | "* |
| 6699 | { | |
| aa4e54c4 | 6700 | register rtx target = operands[1]; |
| 8ef30996 MM |
6701 | |
| 6702 | if (GET_CODE (target) == SYMBOL_REF) | |
| 6703 | return \"%*jal\\t%1\"; | |
| 2bba3a75 | 6704 | else if (GET_CODE (target) == CONST_INT) |
| 5aae9091 | 6705 | return \"%[li\\t%@,%1\\n\\t%*jal\\t%3,%@%]\"; |
| 8ef30996 | 6706 | else |
| 5aae9091 | 6707 | return \"%*jal\\t%3,%1\"; |
| 8ef30996 MM |
6708 | }" |
| 6709 | [(set_attr "type" "call") | |
| 6710 | (set_attr "mode" "none") | |
| 6711 | (set_attr "length" "1")]) | |
| 6712 | ||
| d1399bd0 | 6713 | (define_insn "call_value_internal2" |
| 84a92af4 | 6714 | [(set (match_operand 0 "register_operand" "=df") |
| aa4e54c4 | 6715 | (call (mem (match_operand 1 "call_insn_operand" "ri")) |
| 84a92af4 JW |
6716 | (match_operand 2 "" "i"))) |
| 6717 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| 6718 | "TARGET_ABICALLS && !TARGET_LONG_CALLS" | |
| 6719 | "* | |
| 6720 | { | |
| aa4e54c4 | 6721 | register rtx target = operands[1]; |
| 84a92af4 JW |
6722 | |
| 6723 | if (GET_CODE (target) == SYMBOL_REF) | |
| 84a92af4 | 6724 | { |
| 5aae9091 JW |
6725 | if (GET_MODE (target) == SImode) |
| 6726 | return \"la\\t%^,%1\\n\\tjal\\t%3,%^\"; | |
| 84a92af4 | 6727 | else |
| 5aae9091 | 6728 | return \"dla\\t%^,%1\\n\\tjal\\t%3,%^\"; |
| 84a92af4 | 6729 | } |
| 5aae9091 JW |
6730 | else if (GET_CODE (target) == CONST_INT) |
| 6731 | return \"li\\t%^,%1\\n\\tjal\\t%3,%^\"; | |
| 6732 | else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM) | |
| 6733 | return \"move\\t%^,%1\\n\\tjal\\t%3,%^\"; | |
| 6734 | else | |
| 6735 | return \"jal\\t%3,%1\"; | |
| 84a92af4 JW |
6736 | }" |
| 6737 | [(set_attr "type" "call") | |
| 6738 | (set_attr "mode" "none") | |
| 6739 | (set_attr "length" "2")]) | |
| 6740 | ||
| bb621ad7 | 6741 | (define_insn "call_value_internal3a" |
| d1399bd0 MM |
6742 | [(set (match_operand 0 "register_operand" "=df") |
| 6743 | (call (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
| 6744 | (match_operand 2 "" "i"))) | |
| 6745 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 JW |
6746 | "!TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS" |
| 6747 | "%*jal\\t%3,%1" | |
| 6748 | [(set_attr "type" "call") | |
| 6749 | (set_attr "mode" "none") | |
| 6750 | (set_attr "length" "1")]) | |
| 6751 | ||
| 6752 | (define_insn "call_value_internal3b" | |
| 6753 | [(set (match_operand 0 "register_operand" "=df") | |
| 6754 | (call (mem:DI (match_operand:DI 1 "register_operand" "r")) | |
| 6755 | (match_operand 2 "" "i"))) | |
| 6756 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| 6757 | "TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS" | |
| d1399bd0 MM |
6758 | "%*jal\\t%3,%1" |
| 6759 | [(set_attr "type" "call") | |
| 6760 | (set_attr "mode" "none") | |
| 6761 | (set_attr "length" "1")]) | |
| 6762 | ||
| bb621ad7 | 6763 | (define_insn "call_value_internal4a" |
| 84a92af4 JW |
6764 | [(set (match_operand 0 "register_operand" "=df") |
| 6765 | (call (mem:SI (match_operand:SI 1 "register_operand" "r")) | |
| 6766 | (match_operand 2 "" "i"))) | |
| 6767 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| bb621ad7 JW |
6768 | "!TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS" |
| 6769 | "* | |
| 6770 | { | |
| 6771 | if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM) | |
| 6772 | return \"move\\t%^,%1\\n\\tjal\\t%3,%^\"; | |
| 6773 | else | |
| 6774 | return \"jal\\t%3,%1\"; | |
| 6775 | }" | |
| 6776 | [(set_attr "type" "call") | |
| 6777 | (set_attr "mode" "none") | |
| 6778 | (set_attr "length" "2")]) | |
| 6779 | ||
| 6780 | (define_insn "call_value_internal4b" | |
| 6781 | [(set (match_operand 0 "register_operand" "=df") | |
| 6782 | (call (mem:DI (match_operand:DI 1 "register_operand" "r")) | |
| 6783 | (match_operand 2 "" "i"))) | |
| 6784 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| 6785 | "TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS" | |
| 84a92af4 JW |
6786 | "* |
| 6787 | { | |
| 6788 | if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM) | |
| 6789 | return \"move\\t%^,%1\\n\\tjal\\t%3,%^\"; | |
| 6790 | else | |
| 6791 | return \"jal\\t%3,%1\"; | |
| 6792 | }" | |
| 6793 | [(set_attr "type" "call") | |
| 6794 | (set_attr "mode" "none") | |
| 6795 | (set_attr "length" "2")]) | |
| 6796 | ||
| a5262009 | 6797 | (define_expand "call_value_multiple_internal0" |
| aa4e54c4 JW |
6798 | [(parallel [(set (match_operand 0 "" "") |
| 6799 | (call (match_operand 1 "" "") | |
| 6800 | (match_operand 2 "" ""))) | |
| 6801 | (set (match_operand 3 "" "") | |
| 6802 | (call (match_dup 1) | |
| 6803 | (match_dup 2))) | |
| 6804 | (clobber (match_operand:SI 4 "" ""))])] | |
| 6805 | "" | |
| 6806 | "") | |
| 6807 | ||
| bd16a708 JW |
6808 | ;; ??? May eventually need all 6 versions of the call patterns with multiple |
| 6809 | ;; return values. | |
| 6810 | ||
| 6811 | (define_insn "call_value_multiple_internal2" | |
| 6812 | [(set (match_operand 0 "register_operand" "=df") | |
| aa4e54c4 | 6813 | (call (mem (match_operand 1 "call_insn_operand" "ri")) |
| bd16a708 JW |
6814 | (match_operand 2 "" "i"))) |
| 6815 | (set (match_operand 3 "register_operand" "=df") | |
| aa4e54c4 | 6816 | (call (mem (match_dup 1)) |
| bd16a708 JW |
6817 | (match_dup 2))) |
| 6818 | (clobber (match_operand:SI 4 "register_operand" "=d"))] | |
| 6819 | "TARGET_ABICALLS && !TARGET_LONG_CALLS" | |
| 6820 | "* | |
| 6821 | { | |
| aa4e54c4 | 6822 | register rtx target = operands[1]; |
| bd16a708 JW |
6823 | |
| 6824 | if (GET_CODE (target) == SYMBOL_REF) | |
| bd16a708 | 6825 | { |
| 5aae9091 JW |
6826 | if (GET_MODE (target) == SImode) |
| 6827 | return \"la\\t%^,%1\\n\\tjal\\t%4,%^\"; | |
| bd16a708 | 6828 | else |
| 5aae9091 | 6829 | return \"la\\t%^,%1\\n\\tjal\\t%4,%^\"; |
| bd16a708 | 6830 | } |
| 5aae9091 JW |
6831 | else if (GET_CODE (target) == CONST_INT) |
| 6832 | return \"li\\t%^,%1\\n\\tjal\\t%4,%^\"; | |
| 6833 | else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM) | |
| 6834 | return \"move\\t%^,%1\\n\\tjal\\t%4,%^\"; | |
| 6835 | else | |
| 6836 | return \"jal\\t%4,%1\"; | |
| bd16a708 JW |
6837 | }" |
| 6838 | [(set_attr "type" "call") | |
| 6839 | (set_attr "mode" "none") | |
| 6840 | (set_attr "length" "2")]) | |
| 6841 | ||
| 6842 | ||
| a93821e9 TW |
6843 | ;; Call subroutine returning any type. |
| 6844 | ||
| 6845 | (define_expand "untyped_call" | |
| 6846 | [(parallel [(call (match_operand 0 "" "") | |
| 6847 | (const_int 0)) | |
| 6848 | (match_operand 1 "" "") | |
| 6849 | (match_operand 2 "" "")])] | |
| 6850 | "" | |
| 6851 | " | |
| 6852 | { | |
| 740b4585 | 6853 | if (operands[0]) /* silence statement not reached warnings */ |
| a93821e9 | 6854 | { |
| 740b4585 MM |
6855 | int i; |
| 6856 | ||
| 6857 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
| a93821e9 | 6858 | |
| 740b4585 MM |
6859 | for (i = 0; i < XVECLEN (operands[2], 0); i++) |
| 6860 | { | |
| 6861 | rtx set = XVECEXP (operands[2], 0, i); | |
| 6862 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
| 6863 | } | |
| a93821e9 | 6864 | |
| 740b4585 MM |
6865 | emit_insn (gen_blockage ()); |
| 6866 | DONE; | |
| 6867 | } | |
| a93821e9 | 6868 | }") |
| 8ef30996 MM |
6869 | \f |
| 6870 | ;; | |
| 6871 | ;; .................... | |
| 6872 | ;; | |
| 6873 | ;; MISC. | |
| 6874 | ;; | |
| 6875 | ;; .................... | |
| 6876 | ;; | |
| 6877 | ||
| 6878 | (define_insn "nop" | |
| 6879 | [(const_int 0)] | |
| 6880 | "" | |
| 6881 | "%(nop%)" | |
| 6882 | [(set_attr "type" "nop") | |
| 6883 | (set_attr "mode" "none") | |
| 6884 | (set_attr "length" "1")]) | |
| 6885 | ||
| 6886 | (define_expand "probe" | |
| 6887 | [(set (match_dup 0) | |
| 6888 | (match_dup 1))] | |
| 6889 | "" | |
| 6890 | " | |
| 6891 | { | |
| 6892 | operands[0] = gen_reg_rtx (SImode); | |
| 6893 | operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx); | |
| 6894 | MEM_VOLATILE_P (operands[1]) = TRUE; | |
| 6895 | ||
| 6896 | /* fall through and generate default code */ | |
| 6897 | }") | |
| e19ff60f JW |
6898 | \f |
| 6899 | ;; | |
| 6900 | ;; MIPS4 Conditional move instructions. | |
| 6901 | ||
| 6902 | (define_insn "" | |
| 6903 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 6904 | (if_then_else:SI | |
| 6905 | (match_operator 4 "equality_op" | |
| 6906 | [(match_operand:SI 1 "register_operand" "d,d") | |
| 6907 | (const_int 0)]) | |
| 6908 | (match_operand:SI 2 "reg_or_0_operand" "dJ,0") | |
| 6909 | (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))] | |
| 6910 | "mips_isa >= 4" | |
| 6911 | "@ | |
| 6912 | mov%B4\\t%0,%z2,%1 | |
| 6913 | mov%b4\\t%0,%z3,%1" | |
| 6914 | [(set_attr "type" "move") | |
| 6915 | (set_attr "mode" "SI")]) | |
| 6916 | ||
| 197b2bf3 JW |
6917 | (define_insn "" |
| 6918 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 6919 | (if_then_else:SI | |
| 6920 | (match_operator 4 "equality_op" | |
| 6921 | [(match_operand:DI 1 "register_operand" "d,d") | |
| 6922 | (const_int 0)]) | |
| 6923 | (match_operand:SI 2 "reg_or_0_operand" "dJ,0") | |
| 6924 | (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))] | |
| 6925 | "mips_isa >= 4" | |
| 6926 | "@ | |
| 6927 | mov%B4\\t%0,%z2,%1 | |
| 6928 | mov%b4\\t%0,%z3,%1" | |
| 6929 | [(set_attr "type" "move") | |
| 6930 | (set_attr "mode" "SI")]) | |
| 6931 | ||
| e19ff60f JW |
6932 | (define_insn "" |
| 6933 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 6934 | (if_then_else:SI | |
| b8eb88d0 ILT |
6935 | (match_operator 3 "equality_op" [(match_operand:CC 4 |
| 6936 | "register_operand" | |
| 6937 | "z,z") | |
| 6938 | (const_int 0)]) | |
| e19ff60f JW |
6939 | (match_operand:SI 1 "reg_or_0_operand" "dJ,0") |
| 6940 | (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))] | |
| b8eb88d0 | 6941 | "mips_isa >= 4 && TARGET_HARD_FLOAT" |
| e19ff60f | 6942 | "@ |
| b8eb88d0 ILT |
6943 | mov%T3\\t%0,%z1,%4 |
| 6944 | mov%t3\\t%0,%z2,%4" | |
| e19ff60f JW |
6945 | [(set_attr "type" "move") |
| 6946 | (set_attr "mode" "SI")]) | |
| 6947 | ||
| 197b2bf3 JW |
6948 | (define_insn "" |
| 6949 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 6950 | (if_then_else:DI | |
| 6951 | (match_operator 4 "equality_op" | |
| 6952 | [(match_operand:SI 1 "register_operand" "d,d") | |
| 6953 | (const_int 0)]) | |
| 6954 | (match_operand:DI 2 "reg_or_0_operand" "dJ,0") | |
| 6955 | (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))] | |
| 6956 | "mips_isa >= 4" | |
| 6957 | "@ | |
| 6958 | mov%B4\\t%0,%z2,%1 | |
| 6959 | mov%b4\\t%0,%z3,%1" | |
| 6960 | [(set_attr "type" "move") | |
| 6961 | (set_attr "mode" "DI")]) | |
| 6962 | ||
| e19ff60f JW |
6963 | (define_insn "" |
| 6964 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 6965 | (if_then_else:DI | |
| 6966 | (match_operator 4 "equality_op" | |
| 6967 | [(match_operand:DI 1 "register_operand" "d,d") | |
| 6968 | (const_int 0)]) | |
| 6969 | (match_operand:DI 2 "reg_or_0_operand" "dJ,0") | |
| 6970 | (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))] | |
| 6971 | "mips_isa >= 4" | |
| 6972 | "@ | |
| 6973 | mov%B4\\t%0,%z2,%1 | |
| 6974 | mov%b4\\t%0,%z3,%1" | |
| 6975 | [(set_attr "type" "move") | |
| 6976 | (set_attr "mode" "DI")]) | |
| 6977 | ||
| 6978 | (define_insn "" | |
| 6979 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 6980 | (if_then_else:DI | |
| b8eb88d0 ILT |
6981 | (match_operator 3 "equality_op" [(match_operand:CC 4 |
| 6982 | "register_operand" | |
| 6983 | "z,z") | |
| 6984 | (const_int 0)]) | |
| e19ff60f JW |
6985 | (match_operand:DI 1 "reg_or_0_operand" "dJ,0") |
| 6986 | (match_operand:DI 2 "reg_or_0_operand" "0,dJ")))] | |
| b8eb88d0 | 6987 | "mips_isa >= 4 && TARGET_HARD_FLOAT" |
| e19ff60f | 6988 | "@ |
| b8eb88d0 ILT |
6989 | mov%T3\\t%0,%z1,%4 |
| 6990 | mov%t3\\t%0,%z2,%4" | |
| e19ff60f JW |
6991 | [(set_attr "type" "move") |
| 6992 | (set_attr "mode" "DI")]) | |
| 6993 | ||
| 6994 | (define_insn "" | |
| 6995 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 6996 | (if_then_else:SF | |
| 6997 | (match_operator 4 "equality_op" | |
| 6998 | [(match_operand:SI 1 "register_operand" "d,d") | |
| 6999 | (const_int 0)]) | |
| 7000 | (match_operand:SF 2 "register_operand" "f,0") | |
| 7001 | (match_operand:SF 3 "register_operand" "0,f")))] | |
| 7002 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 7003 | "@ | |
| 7004 | mov%B4.s\\t%0,%2,%1 | |
| 7005 | mov%b4.s\\t%0,%3,%1" | |
| 7006 | [(set_attr "type" "move") | |
| 7007 | (set_attr "mode" "SF")]) | |
| 7008 | ||
| 7009 | (define_insn "" | |
| 7010 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 7011 | (if_then_else:SF | |
| b8eb88d0 ILT |
7012 | (match_operator 3 "equality_op" [(match_operand:CC 4 |
| 7013 | "register_operand" | |
| 7014 | "z,z") | |
| 7015 | (const_int 0)]) | |
| e19ff60f JW |
7016 | (match_operand:SF 1 "register_operand" "f,0") |
| 7017 | (match_operand:SF 2 "register_operand" "0,f")))] | |
| 7018 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 7019 | "@ | |
| b8eb88d0 ILT |
7020 | mov%T3.s\\t%0,%1,%4 |
| 7021 | mov%t3.s\\t%0,%2,%4" | |
| e19ff60f JW |
7022 | [(set_attr "type" "move") |
| 7023 | (set_attr "mode" "SF")]) | |
| 7024 | ||
| 7025 | (define_insn "" | |
| 7026 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 7027 | (if_then_else:DF | |
| 7028 | (match_operator 4 "equality_op" | |
| 7029 | [(match_operand:SI 1 "register_operand" "d,d") | |
| 7030 | (const_int 0)]) | |
| 7031 | (match_operand:DF 2 "register_operand" "f,0") | |
| 7032 | (match_operand:DF 3 "register_operand" "0,f")))] | |
| b8eb88d0 | 7033 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| e19ff60f JW |
7034 | "@ |
| 7035 | mov%B4.d\\t%0,%2,%1 | |
| 7036 | mov%b4.d\\t%0,%3,%1" | |
| 7037 | [(set_attr "type" "move") | |
| 7038 | (set_attr "mode" "DF")]) | |
| 7039 | ||
| 7040 | (define_insn "" | |
| 7041 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 7042 | (if_then_else:DF | |
| b8eb88d0 ILT |
7043 | (match_operator 3 "equality_op" [(match_operand:CC 4 |
| 7044 | "register_operand" | |
| 7045 | "z,z") | |
| 7046 | (const_int 0)]) | |
| e19ff60f JW |
7047 | (match_operand:DF 1 "register_operand" "f,0") |
| 7048 | (match_operand:DF 2 "register_operand" "0,f")))] | |
| b8eb88d0 | 7049 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" |
| e19ff60f | 7050 | "@ |
| b8eb88d0 ILT |
7051 | mov%T3.d\\t%0,%1,%4 |
| 7052 | mov%t3.d\\t%0,%2,%4" | |
| e19ff60f JW |
7053 | [(set_attr "type" "move") |
| 7054 | (set_attr "mode" "DF")]) | |
| 7055 | ||
| 7056 | ;; These are the main define_expand's used to make conditional moves. | |
| 7057 | ||
| 7058 | (define_expand "movsicc" | |
| 7059 | [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) | |
| 7060 | (set (match_operand:SI 0 "register_operand" "") | |
| 7061 | (if_then_else:SI (match_dup 5) | |
| 7062 | (match_operand:SI 2 "reg_or_0_operand" "") | |
| 7063 | (match_operand:SI 3 "reg_or_0_operand" "")))] | |
| 7064 | "mips_isa >= 4" | |
| 7065 | " | |
| 7066 | { | |
| b8eb88d0 ILT |
7067 | gen_conditional_move (operands); |
| 7068 | DONE; | |
| 7069 | }") | |
| e19ff60f | 7070 | |
| b8eb88d0 ILT |
7071 | (define_expand "movdicc" |
| 7072 | [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) | |
| 7073 | (set (match_operand:DI 0 "register_operand" "") | |
| 7074 | (if_then_else:DI (match_dup 5) | |
| 7075 | (match_operand:DI 2 "reg_or_0_operand" "") | |
| 7076 | (match_operand:DI 3 "reg_or_0_operand" "")))] | |
| 7077 | "mips_isa >= 4" | |
| 7078 | " | |
| 7079 | { | |
| 7080 | gen_conditional_move (operands); | |
| 7081 | DONE; | |
| 7082 | }") | |
| e19ff60f | 7083 | |
| b8eb88d0 ILT |
7084 | (define_expand "movsfcc" |
| 7085 | [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) | |
| 7086 | (set (match_operand:SF 0 "register_operand" "") | |
| 7087 | (if_then_else:SF (match_dup 5) | |
| 7088 | (match_operand:SF 2 "reg_or_0_operand" "") | |
| 7089 | (match_operand:SF 3 "reg_or_0_operand" "")))] | |
| 7090 | "mips_isa >= 4 && TARGET_HARD_FLOAT" | |
| 7091 | " | |
| 7092 | { | |
| 7093 | gen_conditional_move (operands); | |
| 7094 | DONE; | |
| e19ff60f JW |
7095 | }") |
| 7096 | ||
| b8eb88d0 ILT |
7097 | (define_expand "movdfcc" |
| 7098 | [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) | |
| 7099 | (set (match_operand:DF 0 "register_operand" "") | |
| 7100 | (if_then_else:DF (match_dup 5) | |
| 7101 | (match_operand:DF 2 "reg_or_0_operand" "") | |
| 7102 | (match_operand:DF 3 "reg_or_0_operand" "")))] | |
| 7103 | "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" | |
| 7104 | " | |
| 7105 | { | |
| 7106 | gen_conditional_move (operands); | |
| 7107 | DONE; | |
| 7108 | }") |