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8ef30996
MM		 1;; Mips.md Machine Description for MIPS based processors
2;; Contributed by A. Lichnewsky, lich@inria.inria.fr
3;; Changes by Michael Meissner, meissner@osf.org
4;; Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc.
5
6;; This file is part of GNU CC.
7
8;; GNU CC is free software; you can redistribute it and/or modify
9;; it under the terms of the GNU General Public License as published by
10;; the Free Software Foundation; either version 2, or (at your option)
11;; any later version.
12
13;; GNU CC is distributed in the hope that it will be useful,
14;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16;; GNU General Public License for more details.
17
18;; You should have received a copy of the GNU General Public License
19;; along with GNU CC; see the file COPYING. If not, write to
20;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21
22\f
23
24;; ....................
25;;
26;; Attributes
27;;
28;; ....................
29
30;; Classification of each insn.
31;; branch conditional branch
32;; jump unconditional jump
33;; call unconditional call
34;; load load instruction(s)
35;; store store instruction(s)
36;; move data movement within same register set
37;; xfer transfer to/from coprocessor
38;; hilo transfer of hi/lo registers
39;; arith integer arithmetic instruction
40;; darith double precision integer arithmetic instructions
41;; imul integer multiply
42;; idiv integer divide
43;; icmp integer compare
44;; fadd floating point add/subtract
45;; fmul floating point multiply
46;; fdiv floating point divide
47;; fabs floating point absolute value
48;; fneg floating point negation
49;; fcmp floating point compare
50;; fcvt floating point convert
51;; fsqrt floating point square root
52;; multi multiword sequence (or user asm statements)
53;; nop no operation
54;; pic OSF/rose half pic load
55
56(define_attr "type"
57 "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop,pic"
58 (const_string "unknown"))
59
60;; Main data type used by the insn
34b650b3 61(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
8ef30996
MM		 62
63;; # instructions (4 bytes each)
64(define_attr "length" "" (const_int 1))
65
6d518002 66;; whether or not an instruction has a mandatory delay slot
8ef30996 67(define_attr "dslot" "no,yes"
f3b39eba 68 (if_then_else (eq_attr "type" "branch,jump,call,load,xfer,hilo,fcmp,pic")
8ef30996
MM		 69 (const_string "yes")
70 (const_string "no")))
71
ddd8ab48
MM		 72;; Attribute describing the processor. This attribute must match exactly
73;; with the processor_type enumeration in mips.h.
74
8ef30996 75;; Attribute describing the processor
ddd8ab48
MM		 76;; (define_attr "cpu" "default,r3000,r6000,r4000"
77;; (const
78;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
79;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
80;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
81;; (const_string "default"))))
82
83(define_attr "cpu" "default,r3000,r6000,r4000"
84 (const (symbol_ref "mips_cpu_attr")))
8ef30996
MM		 85
86;; Attribute defining whether or not we can use the branch-likely instructions
87;; (MIPS ISA level 2)
88
89(define_attr "branch_likely" "no,yes"
6d518002 90 (const
8ef30996
MM		 91 (if_then_else (ge (symbol_ref "mips_isa") (const_int 2))
92 (const_string "yes")
6d518002 93 (const_string "no"))))
8ef30996
MM		 94
95
96;; Describe a user's asm statement.
97(define_asm_attributes
98 [(set_attr "type" "multi")])
99
100\f
101
102;; .........................
103;;
104;; Delay slots, can't describe load/fcmp/xfer delay slots here
105;;
106;; .........................
107
108(define_delay (eq_attr "type" "branch")
109 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
110 (nil)
bbdb5552 111 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))])
8ef30996
MM		 112
113(define_delay (eq_attr "type" "call,jump")
114 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
115 (nil)
116 (nil)])
117
118\f
119
120;; .........................
121;;
122;; Functional units
123;;
124;; .........................
125
126; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
127; TEST READY-DELAY BUSY-DELAY [CONFLICT-LIST])
128
129;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
130
131(define_function_unit "memory" 1 0
132 (and (eq_attr "type" "load,pic") (eq_attr "cpu" "!r3000"))
133 3 0)
134
135(define_function_unit "memory" 1 0
136 (and (eq_attr "type" "load,pic") (eq_attr "cpu" "r3000"))
137 2 0)
138
ddd8ab48 139(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
8ef30996 140
c3f3d7e1 141(define_function_unit "addr" 1 0 (eq_attr "type" "fcmp") 2 0)
34b650b3 142
c3f3d7e1
MM		 143(define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
144(define_function_unit "memory" 1 0 (eq_attr "type" "hilo") 3 0)
8ef30996
MM		 145
146(define_function_unit "imuldiv" 1 1
147 (and (eq_attr "type" "imul") (eq_attr "cpu" "!r3000,r4000"))
148 17 34)
149
150(define_function_unit "imuldiv" 1 1
151 (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000"))
152 12 24)
153
154(define_function_unit "imuldiv" 1 1
155 (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000"))
156 10 20)
157
158(define_function_unit "imuldiv" 1 1
159 (and (eq_attr "type" "idiv") (eq_attr "cpu" "!r3000,r4000"))
160 38 76)
161
162(define_function_unit "imuldiv" 1 1
163 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000"))
164 35 70)
165
166(define_function_unit "imuldiv" 1 1
167 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
168 69 138)
169
170(define_function_unit "adder" 1 1
171 (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r6000"))
172 4 8)
173
174(define_function_unit "adder" 1 1
175 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000"))
176 2 4)
177
178(define_function_unit "adder" 1 1
179 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
180 3 6)
181
ddd8ab48 182(define_function_unit "adder" 1 1
8ef30996
MM		 183 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "!r3000"))
184 2 4)
185
ddd8ab48 186(define_function_unit "adder" 1 1
8ef30996
MM		 187 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000"))
188 1 2)
189
190(define_function_unit "mult" 1 1
191 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r3000,r6000")))
192 7 14)
193
194(define_function_unit "mult" 1 1
195 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
196 4 8)
197
198(define_function_unit "mult" 1 1
199 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
200 5 10)
201
202(define_function_unit "mult" 1 1
203 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r6000")))
204 8 16)
205
206(define_function_unit "mult" 1 1
207 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
208 5 10)
209
210(define_function_unit "mult" 1 1
211 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
212 6 12)
213
214(define_function_unit "divide" 1 1
215 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r3000,r6000")))
216 23 46)
217
218(define_function_unit "divide" 1 1
219 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
220 12 24)
221
222(define_function_unit "divide" 1 1
223 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
224 15 30)
225
226(define_function_unit "divide" 1 1
227 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r6000")))
228 36 72)
229
230(define_function_unit "divide" 1 1
231 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
232 19 34)
233
234(define_function_unit "divide" 1 1
235 (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
236 16 32)
237
c3f3d7e1
MM		 238(define_function_unit "divide" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 108)
239(define_function_unit "divide" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 224)
8ef30996 240
ddd8ab48
MM		 241\f
242;; The following functional units do not use the cpu type, and use
243;; much less memory in genattrtab.c.
244
245;; (define_function_unit "memory" 1 0 (eq_attr "type" "load,pic") 3 0)
246;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
247;;
248;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
249;;
250;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
251;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
252;;
253;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 34)
254;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 76)
255;;
256;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 8)
257;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 4)
258;;
259;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 14)
260;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 16)
261;;
262;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 46)
263;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 72)
264;;
265;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 108)
266;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 224)
267
8ef30996
MM		 268\f
269;;
270;; ....................
271;;
272;; ADDITION
273;;
274;; ....................
275;;
276
277(define_insn "adddf3"
278 [(set (match_operand:DF 0 "register_operand" "=f")
279 (plus:DF (match_operand:DF 1 "register_operand" "f")
280 (match_operand:DF 2 "register_operand" "f")))]
281 "TARGET_HARD_FLOAT"
282 "add.d\\t%0,%1,%2"
283 [(set_attr "type" "fadd")
284 (set_attr "mode" "DF")
285 (set_attr "length" "1")])
286
287(define_insn "addsf3"
288 [(set (match_operand:SF 0 "register_operand" "=f")
289 (plus:SF (match_operand:SF 1 "register_operand" "f")
290 (match_operand:SF 2 "register_operand" "f")))]
291 "TARGET_HARD_FLOAT"
292 "add.s\\t%0,%1,%2"
293 [(set_attr "type" "fadd")
294 (set_attr "mode" "SF")
295 (set_attr "length" "1")])
296
297(define_insn "addsi3"
298 [(set (match_operand:SI 0 "register_operand" "=d")
299 (plus:SI (match_operand:SI 1 "arith_operand" "%d")
300 (match_operand:SI 2 "arith_operand" "dI")))]
301 ""
302 "*
303{
304 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
305 ? \"subu\\t%0,%1,%n2\"
306 : \"addu\\t%0,%1,%2\";
307}"
308 [(set_attr "type" "arith")
309 (set_attr "mode" "SI")
310 (set_attr "length" "1")])
311
312(define_expand "adddi3"
313 [(parallel [(set (match_operand:DI 0 "register_operand" "")
314 (plus:DI (match_operand:DI 1 "register_operand" "")
315 (match_operand:DI 2 "arith_operand" "")))
316 (clobber (match_dup 3))])]
317 "!TARGET_DEBUG_G_MODE"
92b4cee1
MM		 318 "
319{
320 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
321 operands[2] = force_reg (SImode, operands[2]);
322
323 operands[3] = gen_reg_rtx (SImode);
324}")
8ef30996
MM		 325
326(define_insn "adddi3_internal_1"
327 [(set (match_operand:DI 0 "register_operand" "=d,&d")
328 (plus:DI (match_operand:DI 1 "register_operand" "0,d")
329 (match_operand:DI 2 "register_operand" "d,d")))
330 (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
331 "!TARGET_DEBUG_G_MODE"
332 "*
333{
334 return (REGNO (operands[0]) == REGNO (operands[1])
335 && REGNO (operands[0]) == REGNO (operands[2]))
336 ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
337 : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
338}"
92b4cee1
MM		 339 [(set_attr "type" "darith")
340 (set_attr "mode" "DI")
341 (set_attr "length" "4")])
8ef30996
MM		 342
343(define_split
344 [(set (match_operand:DI 0 "register_operand" "")
345 (plus:DI (match_operand:DI 1 "register_operand" "")
346 (match_operand:DI 2 "register_operand" "")))
347 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 348 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 349 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
350 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
351 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
352 && (REGNO (operands[0]) != REGNO (operands[1])
353 || REGNO (operands[0]) != REGNO (operands[2]))"
354
355 [(set (subreg:SI (match_dup 0) 0)
356 (plus:SI (subreg:SI (match_dup 1) 0)
357 (subreg:SI (match_dup 2) 0)))
358
359 (set (match_dup 3)
34b650b3 360 (ltu:SI (subreg:SI (match_dup 0) 0)
8ef30996
MM		 361 (subreg:SI (match_dup 2) 0)))
362
363 (set (subreg:SI (match_dup 0) 1)
364 (plus:SI (subreg:SI (match_dup 1) 1)
365 (subreg:SI (match_dup 2) 1)))
366
367 (set (subreg:SI (match_dup 0) 1)
368 (plus:SI (subreg:SI (match_dup 0) 1)
369 (match_dup 3)))]
370 "")
371
372(define_split
373 [(set (match_operand:DI 0 "register_operand" "")
374 (plus:DI (match_operand:DI 1 "register_operand" "")
375 (match_operand:DI 2 "register_operand" "")))
376 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 377 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 378 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
379 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
380 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
381 && (REGNO (operands[0]) != REGNO (operands[1])
382 || REGNO (operands[0]) != REGNO (operands[2]))"
383
384 [(set (subreg:SI (match_dup 0) 1)
385 (plus:SI (subreg:SI (match_dup 1) 1)
386 (subreg:SI (match_dup 2) 1)))
387
388 (set (match_dup 3)
34b650b3 389 (ltu:SI (subreg:SI (match_dup 0) 1)
8ef30996
MM		 390 (subreg:SI (match_dup 2) 1)))
391
392 (set (subreg:SI (match_dup 0) 0)
393 (plus:SI (subreg:SI (match_dup 1) 0)
394 (subreg:SI (match_dup 2) 0)))
395
396 (set (subreg:SI (match_dup 0) 0)
397 (plus:SI (subreg:SI (match_dup 0) 0)
398 (match_dup 3)))]
399 "")
400
401(define_insn "adddi3_internal_2"
402 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
403 (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
404 (match_operand:DI 2 "small_int" "P,J,N")))
405 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
406 "!TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
407 "@
408 addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
409 move\\t%L0,%L1\;move\\t%M0,%M1
410 subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
92b4cee1
MM		 411 [(set_attr "type" "darith")
412 (set_attr "mode" "DI")
8ef30996
MM		 413 (set_attr "length" "3,2,4")])
414
415(define_split
416 [(set (match_operand:DI 0 "register_operand" "")
417 (plus:DI (match_operand:DI 1 "register_operand" "")
418 (match_operand:DI 2 "small_int" "")))
419 (clobber (match_operand:SI 3 "register_operand" "=d"))]
26b8e6e5 420 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 421 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
422 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
423 && INTVAL (operands[2]) > 0"
424
425 [(set (subreg:SI (match_dup 0) 0)
426 (plus:SI (subreg:SI (match_dup 1) 0)
427 (match_dup 2)))
428
429 (set (match_dup 3)
34b650b3 430 (ltu:SI (subreg:SI (match_dup 0) 0)
8ef30996
MM		 431 (match_dup 2)))
432
433 (set (subreg:SI (match_dup 0) 1)
434 (plus:SI (subreg:SI (match_dup 1) 1)
435 (match_dup 3)))]
436 "")
437
438(define_split
439 [(set (match_operand:DI 0 "register_operand" "")
440 (plus:DI (match_operand:DI 1 "register_operand" "")
441 (match_operand:DI 2 "small_int" "")))
442 (clobber (match_operand:SI 3 "register_operand" "=d"))]
26b8e6e5 443 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 444 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
445 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
446 && INTVAL (operands[2]) > 0"
447
448 [(set (subreg:SI (match_dup 0) 1)
449 (plus:SI (subreg:SI (match_dup 1) 1)
450 (match_dup 2)))
451
452 (set (match_dup 3)
34b650b3 453 (ltu:SI (subreg:SI (match_dup 0) 1)
8ef30996
MM		 454 (match_dup 2)))
455
456 (set (subreg:SI (match_dup 0) 0)
457 (plus:SI (subreg:SI (match_dup 1) 0)
458 (match_dup 3)))]
459 "")
460\f
461;;
462;; ....................
463;;
464;; SUBTRACTION
465;;
466;; ....................
467;;
468
469(define_insn "subdf3"
470 [(set (match_operand:DF 0 "register_operand" "=f")
471 (minus:DF (match_operand:DF 1 "register_operand" "f")
472 (match_operand:DF 2 "register_operand" "f")))]
473 "TARGET_HARD_FLOAT"
474 "sub.d\\t%0,%1,%2"
475 [(set_attr "type" "fadd")
476 (set_attr "mode" "DF")
477 (set_attr "length" "1")])
478
479(define_insn "subsf3"
480 [(set (match_operand:SF 0 "register_operand" "=f")
481 (minus:SF (match_operand:SF 1 "register_operand" "f")
482 (match_operand:SF 2 "register_operand" "f")))]
483 "TARGET_HARD_FLOAT"
484 "sub.s\\t%0,%1,%2"
485 [(set_attr "type" "fadd")
486 (set_attr "mode" "SF")
487 (set_attr "length" "1")])
488
489(define_insn "subsi3"
490 [(set (match_operand:SI 0 "register_operand" "=d")
491 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
492 (match_operand:SI 2 "arith_operand" "dI")))]
493 ""
494 "*
495{
496 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
497 ? \"addu\\t%0,%z1,%n2\"
498 : \"subu\\t%0,%z1,%2\";
499}"
500 [(set_attr "type" "arith")
501 (set_attr "mode" "SI")
502 (set_attr "length" "1")])
503
504(define_expand "subdi3"
505 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
506 (minus:DI (match_operand:DI 1 "register_operand" "d")
507 (match_operand:DI 2 "register_operand" "d")))
508 (clobber (match_dup 3))])]
509 "!TARGET_DEBUG_G_MODE"
510 "operands[3] = gen_reg_rtx (SImode);")
511
512(define_insn "subdi3_internal"
513 [(set (match_operand:DI 0 "register_operand" "=d")
514 (minus:DI (match_operand:DI 1 "register_operand" "d")
515 (match_operand:DI 2 "register_operand" "d")))
516 (clobber (match_operand:SI 3 "register_operand" "=d"))]
517 "!TARGET_DEBUG_G_MODE"
518 "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
519 [(set_attr "type" "darith")
520 (set_attr "mode" "DI")
521 (set_attr "length" "4")])
522
523(define_split
524 [(set (match_operand:DI 0 "register_operand" "")
525 (minus:DI (match_operand:DI 1 "register_operand" "")
526 (match_operand:DI 2 "register_operand" "")))
527 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 528 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 529 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
530 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
531 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
532
533 [(set (match_dup 3)
34b650b3 534 (ltu:SI (subreg:SI (match_dup 1) 0)
6d518002 535 (subreg:SI (match_dup 2) 0)))
8ef30996
MM		 536
537 (set (subreg:SI (match_dup 0) 0)
538 (minus:SI (subreg:SI (match_dup 1) 0)
539 (subreg:SI (match_dup 2) 0)))
540
541 (set (subreg:SI (match_dup 0) 1)
542 (minus:SI (subreg:SI (match_dup 1) 1)
543 (subreg:SI (match_dup 2) 1)))
544
545 (set (subreg:SI (match_dup 0) 1)
546 (minus:SI (subreg:SI (match_dup 0) 1)
547 (match_dup 3)))]
548 "")
549
550(define_split
551 [(set (match_operand:DI 0 "register_operand" "")
552 (minus:DI (match_operand:DI 1 "register_operand" "")
553 (match_operand:DI 2 "register_operand" "")))
554 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 555 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 556 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
557 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
558 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
559
560 [(set (match_dup 3)
34b650b3 561 (ltu:SI (subreg:SI (match_dup 1) 1)
6d518002 562 (subreg:SI (match_dup 2) 1)))
8ef30996
MM		 563
564 (set (subreg:SI (match_dup 0) 1)
565 (minus:SI (subreg:SI (match_dup 1) 1)
566 (subreg:SI (match_dup 2) 1)))
567
568 (set (subreg:SI (match_dup 0) 0)
569 (minus:SI (subreg:SI (match_dup 1) 0)
570 (subreg:SI (match_dup 2) 0)))
571
572 (set (subreg:SI (match_dup 0) 0)
573 (minus:SI (subreg:SI (match_dup 0) 0)
574 (match_dup 3)))]
575 "")
576
577(define_insn "subdi3_internal_2"
578 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
579 (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
580 (match_operand:DI 2 "small_int" "P,J,N")))
581 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
582 "!TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
583 "@
584 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
585 move\\t%L0,%L1\;move\\t%M0,%M1
586 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
92b4cee1
MM		 587 [(set_attr "type" "darith")
588 (set_attr "mode" "DI")
8ef30996
MM		 589 (set_attr "length" "3,2,4")])
590
591(define_split
592 [(set (match_operand:DI 0 "register_operand" "")
593 (minus:DI (match_operand:DI 1 "register_operand" "")
594 (match_operand:DI 2 "small_int" "")))
595 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 596 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 597 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
598 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
599 && INTVAL (operands[2]) > 0"
600
601 [(set (match_dup 3)
34b650b3 602 (ltu:SI (subreg:SI (match_dup 1) 0)
8ef30996
MM		 603 (match_dup 2)))
604
605 (set (subreg:SI (match_dup 0) 0)
606 (minus:SI (subreg:SI (match_dup 1) 0)
607 (match_dup 2)))
608
609 (set (subreg:SI (match_dup 0) 1)
610 (minus:SI (subreg:SI (match_dup 1) 1)
611 (match_dup 3)))]
612 "")
613
614(define_split
615 [(set (match_operand:DI 0 "register_operand" "")
616 (minus:DI (match_operand:DI 1 "register_operand" "")
617 (match_operand:DI 2 "small_int" "")))
618 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 619 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 620 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
621 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
622 && INTVAL (operands[2]) > 0"
623
624 [(set (match_dup 3)
34b650b3 625 (ltu:SI (subreg:SI (match_dup 1) 1)
8ef30996
MM		 626 (match_dup 2)))
627
628 (set (subreg:SI (match_dup 0) 1)
629 (minus:SI (subreg:SI (match_dup 1) 1)
630 (match_dup 2)))
631
632 (set (subreg:SI (match_dup 0) 0)
633 (minus:SI (subreg:SI (match_dup 1) 0)
634 (match_dup 3)))]
635 "")
636
637\f
638;;
639;; ....................
640;;
641;; MULTIPLICATION
642;;
643;; ....................
644;;
645
646(define_insn "muldf3"
647 [(set (match_operand:DF 0 "register_operand" "=f")
648 (mult:DF (match_operand:DF 1 "register_operand" "f")
649 (match_operand:DF 2 "register_operand" "f")))]
650 "TARGET_HARD_FLOAT"
651 "mul.d\\t%0,%1,%2"
652 [(set_attr "type" "fmul")
653 (set_attr "mode" "DF")
654 (set_attr "length" "1")])
655
656(define_insn "mulsf3"
657 [(set (match_operand:SF 0 "register_operand" "=f")
658 (mult:SF (match_operand:SF 1 "register_operand" "f")
659 (match_operand:SF 2 "register_operand" "f")))]
660 "TARGET_HARD_FLOAT"
661 "mul.s\\t%0,%1,%2"
662 [(set_attr "type" "fmul")
663 (set_attr "mode" "SF")
664 (set_attr "length" "1")])
665
666(define_insn "mulsi3"
667 [(set (match_operand:SI 0 "register_operand" "=d")
668 (mult:SI (match_operand:SI 1 "register_operand" "d")
669 (match_operand:SI 2 "register_operand" "d")))
670 (clobber (reg:SI 64))
671 (clobber (reg:SI 65))]
672 ""
673 "*
674{
675 rtx xoperands[10];
676
677 xoperands[0] = operands[0];
678 xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM);
679
680 output_asm_insn (\"mult\\t%1,%2\", operands);
681 output_asm_insn (mips_move_1word (xoperands, insn), xoperands);
682 return \"\";
683}"
684 [(set_attr "type" "imul")
685 (set_attr "mode" "SI")
686 (set_attr "length" "3")]) ;; mult + mflo + delay
687
688(define_split
689 [(set (match_operand:SI 0 "register_operand" "")
690 (mult:SI (match_operand:SI 1 "register_operand" "")
691 (match_operand:SI 2 "register_operand" "")))
692 (clobber (reg:SI 64))
693 (clobber (reg:SI 65))]
26b8e6e5 694 "!TARGET_DEBUG_D_MODE"
8ef30996
MM		 695 [(parallel [(set (reg:SI 65) ;; low register
696 (mult:SI (match_dup 1)
697 (match_dup 2)))
698 (clobber (reg:SI 64))])
699 (set (match_dup 0)
700 (reg:SI 65))]
701 "")
702
703(define_insn "mulsi3_internal"
704 [(set (reg:SI 65) ;; low register
705 (mult:SI (match_operand:SI 0 "register_operand" "d")
706 (match_operand:SI 1 "register_operand" "d")))
707 (clobber (reg:SI 64))]
708 ""
709 "mult\\t%0,%1"
710 [(set_attr "type" "imul")
711 (set_attr "mode" "SI")
712 (set_attr "length" "1")])
713
714(define_insn "mulsidi3"
715 [(set (match_operand:DI 0 "register_operand" "=d")
716 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
717 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
718 (clobber (reg:DI 64))]
719 ""
720 "*
721{
722 rtx xoperands[10];
723
724 xoperands[0] = operands[0];
725 xoperands[1] = gen_rtx (REG, DImode, MD_REG_FIRST);
726
727 output_asm_insn (\"mult\\t%1,%2\", operands);
728 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
729 return \"\";
730}"
731 [(set_attr "type" "imul")
732 (set_attr "mode" "SI")
733 (set_attr "length" "4")]) ;; mult + mflo + mfhi + delay
734
735(define_insn "umulsidi3"
736 [(set (match_operand:DI 0 "register_operand" "=d")
737 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
738 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))
739 (clobber (reg:DI 64))]
740 ""
741 "*
742{
743 rtx xoperands[10];
744
745 xoperands[0] = operands[0];
746 xoperands[1] = gen_rtx (REG, DImode, MD_REG_FIRST);
747
748 output_asm_insn (\"multu\\t%1,%2\", operands);
749 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
750 return \"\";
751}"
752 [(set_attr "type" "imul")
753 (set_attr "mode" "SI")
754 (set_attr "length" "4")]) ;; mult + mflo + mfhi + delay
755
756\f
757;;
758;; ....................
759;;
760;; DIVISION and REMAINDER
761;;
762;; ....................
763;;
764
765(define_insn "divdf3"
766 [(set (match_operand:DF 0 "register_operand" "=f")
767 (div:DF (match_operand:DF 1 "register_operand" "f")
768 (match_operand:DF 2 "register_operand" "f")))]
769 "TARGET_HARD_FLOAT"
770 "div.d\\t%0,%1,%2"
771 [(set_attr "type" "fdiv")
772 (set_attr "mode" "DF")
773 (set_attr "length" "1")])
774
775(define_insn "divsf3"
776 [(set (match_operand:SF 0 "register_operand" "=f")
777 (div:SF (match_operand:SF 1 "register_operand" "f")
778 (match_operand:SF 2 "register_operand" "f")))]
779 "TARGET_HARD_FLOAT"
780 "div.s\\t%0,%1,%2"
781 [(set_attr "type" "fdiv")
782 (set_attr "mode" "SF")
783 (set_attr "length" "1")])
784
785;; If optimizing, prefer the divmod functions over separate div and
786;; mod functions, since this will allow using one instruction for both
787;; the quotient and remainder. At present, the divmod is not moved out
788;; of loops if it is constant within the loop, so allow -mdebugc to
789;; use the old method of doing things.
790
791;; 64 is the multiply/divide hi register
792;; 65 is the multiply/divide lo register
793
794(define_insn "divmodsi4"
70252580
MM		 795 [(set (match_operand:SI 0 "register_operand" "=d")
796 (div:SI (match_operand:SI 1 "register_operand" "d")
797 (match_operand:SI 2 "register_operand" "d")))
798 (set (match_operand:SI 3 "register_operand" "=d")
799 (mod:SI (match_dup 1)
800 (match_dup 2)))
801 (clobber (reg:SI 64))
802 (clobber (reg:SI 65))]
34b650b3 803 "optimize"
8ef30996
MM		 804 "*
805{
806 if (find_reg_note (insn, REG_UNUSED, operands[3]))
807 return \"div\\t%0,%1,%2\";
808
809 if (find_reg_note (insn, REG_UNUSED, operands[0]))
810 return \"rem\\t%3,%1,%2\";
811
812 return \"div\\t%0,%1,%2\;mfhi\\t%3\";
813}"
814 [(set_attr "type" "idiv")
815 (set_attr "mode" "SI")
816 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
817
818(define_insn "udivmodsi4"
70252580
MM		 819 [(set (match_operand:SI 0 "register_operand" "=d")
820 (udiv:SI (match_operand:SI 1 "register_operand" "d")
821 (match_operand:SI 2 "register_operand" "d")))
822 (set (match_operand:SI 3 "register_operand" "=d")
823 (umod:SI (match_dup 1)
824 (match_dup 2)))
825 (clobber (reg:SI 64))
826 (clobber (reg:SI 65))]
34b650b3 827 "optimize"
8ef30996
MM		 828 "*
829{
830 if (find_reg_note (insn, REG_UNUSED, operands[3]))
831 return \"divu\\t%0,%1,%2\";
832
833 if (find_reg_note (insn, REG_UNUSED, operands[0]))
834 return \"remu\\t%3,%1,%2\";
835
836 return \"divu\\t%0,%1,%2\;mfhi\\t%3\";
837}"
838 [(set_attr "type" "idiv")
839 (set_attr "mode" "SI")
840 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
841
842(define_insn "divsi3"
843 [(set (match_operand:SI 0 "register_operand" "=d")
844 (div:SI (match_operand:SI 1 "register_operand" "d")
845 (match_operand:SI 2 "register_operand" "d")))
846 (clobber (reg:SI 64))
847 (clobber (reg:SI 65))]
34b650b3 848 "!optimize"
8ef30996
MM		 849 "div\\t%0,%1,%2"
850 [(set_attr "type" "idiv")
851 (set_attr "mode" "SI")
852 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
853
854(define_insn "modsi3"
855 [(set (match_operand:SI 0 "register_operand" "=d")
856 (mod:SI (match_operand:SI 1 "register_operand" "d")
857 (match_operand:SI 2 "register_operand" "d")))
858 (clobber (reg:SI 64))
859 (clobber (reg:SI 65))]
34b650b3 860 "!optimize"
8ef30996
MM		 861 "rem\\t%0,%1,%2"
862 [(set_attr "type" "idiv")
863 (set_attr "mode" "SI")
864 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
865
866(define_insn "udivsi3"
867 [(set (match_operand:SI 0 "register_operand" "=d")
868 (udiv:SI (match_operand:SI 1 "register_operand" "d")
869 (match_operand:SI 2 "register_operand" "d")))
870 (clobber (reg:SI 64))
871 (clobber (reg:SI 65))]
34b650b3 872 "!optimize"
8ef30996
MM		 873 "divu\\t%0,%1,%2"
874 [(set_attr "type" "idiv")
875 (set_attr "mode" "SI")
876 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
877
878(define_insn "umodsi3"
879 [(set (match_operand:SI 0 "register_operand" "=d")
880 (umod:SI (match_operand:SI 1 "register_operand" "d")
881 (match_operand:SI 2 "register_operand" "d")))
882 (clobber (reg:SI 64))
883 (clobber (reg:SI 65))]
34b650b3 884 "!optimize"
8ef30996
MM		 885 "remu\\t%0,%1,%2"
886 [(set_attr "type" "idiv")
887 (set_attr "mode" "SI")
888 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
889
890\f
891;;
892;; ....................
893;;
894;; SQUARE ROOT
895;;
896;; ....................
897
898(define_insn "sqrtdf2"
899 [(set (match_operand:DF 0 "register_operand" "=f")
900 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
901 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
902 "sqrt.d\\t%0,%1"
903 [(set_attr "type" "fabs")
904 (set_attr "mode" "DF")
905 (set_attr "length" "1")])
906
907(define_insn "sqrtsf2"
908 [(set (match_operand:SF 0 "register_operand" "=f")
909 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
910 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
911 "sqrt.s\\t%0,%1"
912 [(set_attr "type" "fabs")
913 (set_attr "mode" "SF")
914 (set_attr "length" "1")])
915
916\f
917;;
918;; ....................
919;;
920;; ABSOLUTE VALUE
921;;
922;; ....................
923
924;; Do not use the integer abs macro instruction, since that signals an
925;; exception on -2147483648 (sigh).
926
927(define_insn "abssi2"
928 [(set (match_operand:SI 0 "register_operand" "=d")
929 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
930 ""
931 "*
932{
933 dslots_jump_total++;
934 dslots_jump_filled++;
935 operands[2] = const0_rtx;
936
937 return (REGNO (operands[0]) == REGNO (operands[1]))
938 ? \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n1:\"
939 : \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
940}"
941 [(set_attr "type" "multi")
942 (set_attr "mode" "SI")
943 (set_attr "length" "3")])
944
945(define_insn "absdf2"
946 [(set (match_operand:DF 0 "register_operand" "=f")
947 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
948 "TARGET_HARD_FLOAT"
949 "abs.d\\t%0,%1"
950 [(set_attr "type" "fabs")
951 (set_attr "mode" "DF")
952 (set_attr "length" "1")])
953
954(define_insn "abssf2"
955 [(set (match_operand:SF 0 "register_operand" "=f")
956 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
957 "TARGET_HARD_FLOAT"
958 "abs.s\\t%0,%1"
959 [(set_attr "type" "fabs")
960 (set_attr "mode" "SF")
961 (set_attr "length" "1")])
962
963\f
964;;
965;; ....................
966;;
967;; FIND FIRST BIT INSTRUCTION
968;;
969;; ....................
970;;
971
972(define_insn "ffssi2"
973 [(set (match_operand:SI 0 "register_operand" "=&d")
974 (ffs:SI (match_operand:SI 1 "register_operand" "d")))
975 (clobber (match_scratch:SI 2 "d"))
976 (clobber (match_scratch:SI 3 "d"))]
977 ""
978 "*
979{
980 dslots_jump_total += 2;
981 dslots_jump_filled += 2;
982 operands[4] = const0_rtx;
983
984 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
985 return \"%(\\
986move\\t%0,%z4\\n\\
987\\tbeq\\t%1,%z4,2f\\n\\
9881:\\tand\\t%2,%1,0x0001\\n\\
989\\taddu\\t%0,%0,1\\n\\
990\\tbeq\\t%2,%z4,1b\\n\\
991\\tsrl\\t%1,%1,1\\n\\
9922:%)\";
993
994 return \"%(\\
995move\\t%0,%z4\\n\\
996\\tmove\\t%3,%1\\n\\
997\\tbeq\\t%3,%z4,2f\\n\\
9981:\\tand\\t%2,%3,0x0001\\n\\
999\\taddu\\t%0,%0,1\\n\\
1000\\tbeq\\t%2,%z4,1b\\n\\
1001\\tsrl\\t%3,%3,1\\n\\
10022:%)\";
1003}"
1004 [(set_attr "type" "multi")
1005 (set_attr "mode" "SI")
1006 (set_attr "length" "6")])
1007
1008\f
1009;;
1010;; ....................
1011;;
1012;; NEGATION and ONE'S COMPLEMENT
1013;;
1014;; ....................
1015
1016(define_insn "negsi2"
1017 [(set (match_operand:SI 0 "register_operand" "=d")
1018 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1019 ""
1020 "*
1021{
1022 operands[2] = const0_rtx;
1023 return \"subu\\t%0,%z2,%1\";
1024}"
1025 [(set_attr "type" "arith")
1026 (set_attr "mode" "SI")
1027 (set_attr "length" "1")])
1028
1029(define_expand "negdi3"
1030 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
1031 (neg:DI (match_operand:DI 1 "register_operand" "d")))
1032 (clobber (match_dup 2))])]
1033 "!TARGET_DEBUG_G_MODE"
1034 "operands[2] = gen_reg_rtx (SImode);")
1035
1036(define_insn "negdi3_internal"
1037 [(set (match_operand:DI 0 "register_operand" "=d")
1038 (neg:DI (match_operand:DI 1 "register_operand" "d")))
1039 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1040 "!TARGET_DEBUG_G_MODE"
1041 "*
1042{
1043 operands[3] = const0_rtx;
1044 return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
1045}"
1046 [(set_attr "type" "darith")
1047 (set_attr "mode" "DI")
1048 (set_attr "length" "4")])
1049
1050(define_insn "negdf2"
1051 [(set (match_operand:DF 0 "register_operand" "=f")
1052 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
1053 "TARGET_HARD_FLOAT"
1054 "neg.d\\t%0,%1"
1055 [(set_attr "type" "fneg")
1056 (set_attr "mode" "DF")
1057 (set_attr "length" "1")])
1058
1059(define_insn "negsf2"
1060 [(set (match_operand:SF 0 "register_operand" "=f")
1061 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
1062 "TARGET_HARD_FLOAT"
1063 "neg.s\\t%0,%1"
1064 [(set_attr "type" "fneg")
1065 (set_attr "mode" "SF")
1066 (set_attr "length" "1")])
1067
1068(define_insn "one_cmplsi2"
1069 [(set (match_operand:SI 0 "register_operand" "=d")
1070 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1071 ""
1072 "*
1073{
1074 operands[2] = const0_rtx;
1075 return \"nor\\t%0,%z2,%1\";
1076}"
1077 [(set_attr "type" "arith")
1078 (set_attr "mode" "SI")
1079 (set_attr "length" "1")])
1080
1081(define_insn "one_cmpldi2"
1082 [(set (match_operand:DI 0 "register_operand" "=d")
1083 (not:SI (match_operand:DI 1 "register_operand" "d")))]
1084 ""
1085 "*
1086{
1087 operands[2] = const0_rtx;
1088 return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
1089}"
1090 [(set_attr "type" "darith")
1091 (set_attr "mode" "DI")
1092 (set_attr "length" "2")])
1093
1094(define_split
1095 [(set (match_operand:DI 0 "register_operand" "")
1096 (not:DI (match_operand:DI 1 "register_operand" "")))]
26b8e6e5 1097 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1098 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1099 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
1100
1101 [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
1102 (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))]
1103 "")
1104
1105;; Simple hack to recognize the "nor" instruction on the MIPS
1106;; This must appear before the normal or patterns, so that the
1107;; combiner will correctly fold things.
1108
1109(define_insn "norsi3"
1110 [(set (match_operand:SI 0 "register_operand" "=d")
1111 (not:SI (ior:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1112 (match_operand:SI 2 "reg_or_0_operand" "dJ"))))]
1113 ""
1114 "nor\\t%0,%z1,%z2"
1115 [(set_attr "type" "arith")
1116 (set_attr "mode" "SI")
1117 (set_attr "length" "1")])
1118
1119(define_insn "nordi3"
1120 [(set (match_operand:DI 0 "register_operand" "=d")
1121 (not:DI (ior:DI (match_operand:DI 1 "register_operand" "d")
1122 (match_operand:DI 2 "register_operand" "d"))))]
1123 ""
1124 "nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2"
1125 [(set_attr "type" "darith")
1126 (set_attr "mode" "DI")
1127 (set_attr "length" "2")])
1128
1129(define_split
1130 [(set (match_operand:DI 0 "register_operand" "")
1131 (not:DI (ior:DI (match_operand:DI 1 "register_operand" "")
1132 (match_operand:DI 2 "register_operand" ""))))]
26b8e6e5 1133 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1134 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1135 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1136 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1137
1138 [(set (subreg:SI (match_dup 0) 0) (not:SI (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))))
1139 (set (subreg:SI (match_dup 0) 1) (not:SI (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1))))]
1140 "")
1141
1142\f
1143;;
1144;; ....................
1145;;
1146;; LOGICAL
1147;;
1148;; ....................
1149;;
1150
1151;; Be more liberal in allowing logical operations than the machine actually
1152;; supports. This causes better code to be generated for bitfields, since
1153;; the optimizer can fold things together, at the expense of not moving the
1154;; constant out of loops.
1155
65437fe8
MM		 1156(define_expand "andsi3"
1157 [(set (match_operand:SI 0 "register_operand" "=d")
1158 (and:SI (match_operand:SI 1 "arith32_operand" "dKIM")
1159 (match_operand:SI 2 "arith32_operand" "dKIM")))]
1160 ""
1161 "
1162{
1163 extern rtx gen_andsi3_internal2 ();
1164
1165 /* Canonlicalize */
1166 if (GET_CODE (operands[1]) == CONST_INT)
1167 {
1168 rtx temp;
1169
1170 if (GET_CODE (operands[2]) == CONST_INT)
1171 {
1172 emit_move_insn (operands[0],
1173 gen_rtx (CONST_INT, VOIDmode,
1174 INTVAL (operands[1]) & INTVAL (operands[2])));
1175 DONE;
1176 }
1177
1178 temp = operands[1];
1179 operands[1] = operands[2];
1180 operands[2] = temp;
1181 }
1182
1183 if (GET_CODE (operands[2]) == CONST_INT && !SMALL_INT_UNSIGNED (operands[2]))
1184 {
1185 emit_insn (gen_andsi3_internal2 (operands[0],
1186 operands[1],
1187 operands[2],
1188 gen_reg_rtx (SImode)));
1189 DONE;
1190 }
1191}")
1192
1193(define_insn "andsi3_internal1"
1194 [(set (match_operand:SI 0 "register_operand" "=d,d")
1195 (and:SI (match_operand:SI 1 "register_operand" "d,d")
1196 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
1197 ""
1198 "@
1199 and\\t%0,%1,%2
1200 andi\\t%0,%1,%x2"
1201 [(set_attr "type" "arith")
1202 (set_attr "mode" "SI")
1203 (set_attr "length" "1")])
1204
1205(define_insn "andsi3_internal2"
1206 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
1207 (and:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
1208 (match_operand:SI 2 "arith32_operand" "d,K,I,M")))
1209 (clobber (match_operand:SI 3 "register_operand" "=d,d,d,d"))]
8ef30996
MM		 1210 ""
1211 "@
1212 and\\t%0,%1,%2
1213 andi\\t%0,%1,%x2
65437fe8
MM		 1214 li\\t%3,%X2\\t\\t# %2\;and\\t%0,%1,%3
1215 li\\t%3,%X2\\t\\t# %2\;and\\t%0,%1,%3"
8ef30996 1216 [(set_attr "type" "arith,arith,multi,multi")
92b4cee1 1217 (set_attr "mode" "SI")
3014fb49 1218 (set_attr "length" "1,1,2,3")])
8ef30996 1219
65437fe8
MM		 1220(define_split
1221 [(set (match_operand:SI 0 "register_operand" "")
1222 (and:SI (match_operand:SI 1 "register_operand" "")
1223 (match_operand:SI 2 "lui_int" "")))
1224 (clobber (match_operand:SI 3 "register_operand" ""))]
1225 "reload_completed && !TARGET_DEBUG_D_MODE"
1226
1227 [(set (match_dup 3) (match_dup 2))
1228 (set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))]
1229 "")
1230
1231(define_split
1232 [(set (match_operand:SI 0 "register_operand" "")
1233 (and:SI (match_operand:SI 1 "register_operand" "")
1234 (match_operand:SI 2 "large_int" "")))
1235 (clobber (match_operand:SI 3 "register_operand" ""))]
1236 "reload_completed && !TARGET_DEBUG_D_MODE"
1237
1238 [(set (match_dup 3) (match_dup 4))
1239 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 5)))
1240 (set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))]
1241 "
1242{
1243 int val = INTVAL (operands[2]);
1244 operands[4] = gen_rtx (CONST_INT, VOIDmode, val & 0xffff0000);
1245 operands[5] = gen_rtx (CONST_INT, VOIDmode, val & 0x0000ffff);
1246}")
1247
8ef30996
MM		 1248(define_insn "anddi3"
1249 [(set (match_operand:DI 0 "register_operand" "=d")
1250 (and:DI (match_operand:DI 1 "register_operand" "d")
1251 (match_operand:DI 2 "register_operand" "d")))]
1252 "!TARGET_DEBUG_G_MODE"
1253 "and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2"
1254 [(set_attr "type" "darith")
1255 (set_attr "mode" "DI")
1256 (set_attr "length" "2")])
1257
1258(define_split
1259 [(set (match_operand:DI 0 "register_operand" "")
1260 (and:DI (match_operand:DI 1 "register_operand" "")
1261 (match_operand:DI 2 "register_operand" "")))]
26b8e6e5 1262 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1263 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1264 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1265 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1266
1267 [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1268 (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1269 "")
1270
65437fe8
MM		 1271(define_expand "iorsi3"
1272 [(set (match_operand:SI 0 "register_operand" "=d")
1273 (ior:SI (match_operand:SI 1 "arith32_operand" "dKIM")
1274 (match_operand:SI 2 "arith32_operand" "dKIM")))]
1275 ""
1276 "
1277{
1278 extern rtx gen_iorsi3_internal2 ();
1279
1280 /* Canonlicalize */
1281 if (GET_CODE (operands[1]) == CONST_INT)
1282 {
1283 rtx temp;
1284
1285 if (GET_CODE (operands[2]) == CONST_INT)
1286 {
1287 emit_move_insn (operands[0],
1288 gen_rtx (CONST_INT, VOIDmode,
1289 INTVAL (operands[1]) | INTVAL (operands[2])));
1290 DONE;
1291 }
1292
1293 temp = operands[1];
1294 operands[1] = operands[2];
1295 operands[2] = temp;
1296 }
1297
1298 if (GET_CODE (operands[2]) == CONST_INT && !SMALL_INT_UNSIGNED (operands[2]))
1299 {
1300 emit_insn (gen_iorsi3_internal2 (operands[0],
1301 operands[1],
1302 operands[2],
1303 gen_reg_rtx (SImode)));
1304 DONE;
1305 }
1306}")
1307
1308(define_insn "iorsi3_internal1"
1309 [(set (match_operand:SI 0 "register_operand" "=d,d")
1310 (ior:SI (match_operand:SI 1 "register_operand" "d,d")
1311 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
1312 ""
1313 "@
1314 or\\t%0,%1,%2
1315 ori\\t%0,%1,%x2"
1316 [(set_attr "type" "arith")
1317 (set_attr "mode" "SI")
1318 (set_attr "length" "1")])
1319
1320(define_insn "iorsi3_internal2"
1321 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
1322 (ior:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
1323 (match_operand:SI 2 "arith32_operand" "d,K,I,M")))
1324 (clobber (match_operand:SI 3 "register_operand" "=d,d,d,d"))]
8ef30996
MM		 1325 ""
1326 "@
1327 or\\t%0,%1,%2
1328 ori\\t%0,%1,%x2
65437fe8
MM		 1329 li\\t%3,%X2\\t\\t# %2\;or\\t%0,%1,%3
1330 li\\t%3,%X2\\t\\t# %2\;or\\t%0,%1,%3"
8ef30996 1331 [(set_attr "type" "arith,arith,multi,multi")
92b4cee1 1332 (set_attr "mode" "SI")
3014fb49 1333 (set_attr "length" "1,1,2,3")])
8ef30996 1334
65437fe8
MM		 1335(define_split
1336 [(set (match_operand:SI 0 "register_operand" "")
1337 (ior:SI (match_operand:SI 1 "register_operand" "")
1338 (match_operand:SI 2 "lui_int" "")))
1339 (clobber (match_operand:SI 3 "register_operand" ""))]
1340 "reload_completed && !TARGET_DEBUG_D_MODE"
1341
1342 [(set (match_dup 3) (match_dup 2))
1343 (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))]
1344 "")
1345
1346(define_split
1347 [(set (match_operand:SI 0 "register_operand" "")
1348 (ior:SI (match_operand:SI 1 "register_operand" "")
1349 (match_operand:SI 2 "large_int" "")))
1350 (clobber (match_operand:SI 3 "register_operand" ""))]
1351 "reload_completed && !TARGET_DEBUG_D_MODE"
1352
1353 [(set (match_dup 3) (match_dup 4))
1354 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 5)))
1355 (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))]
1356 "
1357{
1358 int val = INTVAL (operands[2]);
1359 operands[4] = gen_rtx (CONST_INT, VOIDmode, val & 0xffff0000);
1360 operands[5] = gen_rtx (CONST_INT, VOIDmode, val & 0x0000ffff);
1361}")
1362
8ef30996
MM		 1363(define_insn "iordi3"
1364 [(set (match_operand:DI 0 "register_operand" "=d")
1365 (ior:DI (match_operand:DI 1 "register_operand" "d")
1366 (match_operand:DI 2 "register_operand" "d")))]
1367 "!TARGET_DEBUG_G_MODE"
1368 "or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2"
1369 [(set_attr "type" "darith")
1370 (set_attr "mode" "DI")
1371 (set_attr "length" "2")])
1372
1373(define_split
1374 [(set (match_operand:DI 0 "register_operand" "")
1375 (ior:DI (match_operand:DI 1 "register_operand" "")
1376 (match_operand:DI 2 "register_operand" "")))]
26b8e6e5 1377 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1378 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1379 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1380 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1381
1382 [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1383 (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1384 "")
1385
65437fe8
MM		 1386(define_expand "xorsi3"
1387 [(set (match_operand:SI 0 "register_operand" "=d")
1388 (xor:SI (match_operand:SI 1 "arith32_operand" "dKIM")
1389 (match_operand:SI 2 "arith32_operand" "dKIM")))]
1390 ""
1391 "
1392{
1393 extern rtx gen_xorsi3_internal2 ();
1394
1395 /* Canonlicalize */
1396 if (GET_CODE (operands[1]) == CONST_INT)
1397 {
1398 rtx temp;
1399
1400 if (GET_CODE (operands[2]) == CONST_INT)
1401 {
1402 emit_move_insn (operands[0],
1403 gen_rtx (CONST_INT, VOIDmode,
1404 INTVAL (operands[1]) ^ INTVAL (operands[2])));
1405 DONE;
1406 }
1407
1408 temp = operands[1];
1409 operands[1] = operands[2];
1410 operands[2] = temp;
1411 }
1412
1413 if (GET_CODE (operands[2]) == CONST_INT && !SMALL_INT_UNSIGNED (operands[2]))
1414 {
1415 emit_insn (gen_xorsi3_internal2 (operands[0],
1416 operands[1],
1417 operands[2],
1418 gen_reg_rtx (SImode)));
1419 DONE;
1420 }
1421}")
1422
1423(define_insn "xorsi3_internal1"
1424 [(set (match_operand:SI 0 "register_operand" "=d,d")
1425 (xor:SI (match_operand:SI 1 "register_operand" "d,d")
1426 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
1427 ""
1428 "@
1429 xor\\t%0,%1,%2
1430 xori\\t%0,%1,%x2"
1431 [(set_attr "type" "arith")
1432 (set_attr "mode" "SI")
1433 (set_attr "length" "1")])
1434
1435(define_insn "xorsi3_internal2"
1436 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
1437 (xor:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
1438 (match_operand:SI 2 "arith32_operand" "d,K,I,M")))
1439 (clobber (match_operand:SI 3 "register_operand" "=d,d,d,d"))]
8ef30996
MM		 1440 ""
1441 "@
1442 xor\\t%0,%1,%2
1443 xori\\t%0,%1,%x2
65437fe8
MM		 1444 li\\t%3,%X2\\t\\t# %2\;xor\\t%0,%1,%3
1445 li\\t%3,%X2\\t\\t# %2\;xor\\t%0,%1,%3"
8ef30996 1446 [(set_attr "type" "arith,arith,multi,multi")
92b4cee1 1447 (set_attr "mode" "SI")
3014fb49 1448 (set_attr "length" "1,1,2,3")])
8ef30996 1449
65437fe8
MM		 1450(define_split
1451 [(set (match_operand:SI 0 "register_operand" "")
1452 (xor:SI (match_operand:SI 1 "register_operand" "")
1453 (match_operand:SI 2 "lui_int" "")))
1454 (clobber (match_operand:SI 3 "register_operand" ""))]
1455 "reload_completed && !TARGET_DEBUG_D_MODE"
1456
1457 [(set (match_dup 3) (match_dup 2))
1458 (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))]
1459 "")
1460
1461(define_split
1462 [(set (match_operand:SI 0 "register_operand" "")
1463 (xor:SI (match_operand:SI 1 "register_operand" "")
1464 (match_operand:SI 2 "large_int" "")))
1465 (clobber (match_operand:SI 3 "register_operand" ""))]
1466 "reload_completed && !TARGET_DEBUG_D_MODE"
1467
1468 [(set (match_dup 3) (match_dup 4))
1469 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 5)))
1470 (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))]
1471 "
1472{
1473 int val = INTVAL (operands[2]);
1474 operands[4] = gen_rtx (CONST_INT, VOIDmode, val & 0xffff0000);
1475 operands[5] = gen_rtx (CONST_INT, VOIDmode, val & 0x0000ffff);
1476}")
1477
1478
8ef30996
MM		 1479(define_insn "xordi3"
1480 [(set (match_operand:DI 0 "register_operand" "=d")
1481 (xor:DI (match_operand:DI 1 "register_operand" "d")
1482 (match_operand:DI 2 "register_operand" "d")))]
1483 "!TARGET_DEBUG_G_MODE"
1484 "xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2"
1485 [(set_attr "type" "darith")
1486 (set_attr "mode" "DI")
1487 (set_attr "length" "2")])
1488
1489(define_split
1490 [(set (match_operand:DI 0 "register_operand" "")
1491 (xor:DI (match_operand:DI 1 "register_operand" "")
1492 (match_operand:DI 2 "register_operand" "")))]
26b8e6e5 1493 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 1494 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1495 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1496 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1497
1498 [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1499 (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1500 "")
1501
1502\f
1503;;
1504;; ....................
1505;;
1506;; TRUNCATION
1507;;
1508;; ....................
1509
1510(define_insn "truncdfsf2"
1511 [(set (match_operand:SF 0 "register_operand" "=f")
1512 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
1513 "TARGET_HARD_FLOAT"
1514 "cvt.s.d\\t%0,%1"
1515 [(set_attr "type" "fcvt")
1516 (set_attr "mode" "SF")
1517 (set_attr "length" "1")])
1518
1519\f
1520;;
1521;; ....................
1522;;
1523;; ZERO EXTENSION
1524;;
1525;; ....................
1526
1527;; Extension insns.
1528;; Those for integer source operand
1529;; are ordered widest source type first.
1530
1531(define_insn "zero_extendhisi2"
1532 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
1533 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
1534 ""
1535 "*
1536{
1537 if (which_alternative == 0)
1538 return \"andi\\t%0,%1,0xffff\";
1539 else
1540 return mips_move_1word (operands, insn, TRUE);
1541}"
1542 [(set_attr "type" "arith,load,load")
92b4cee1 1543 (set_attr "mode" "SI")
8ef30996
MM		 1544 (set_attr "length" "1,1,2")])
1545
1546(define_insn "zero_extendqihi2"
1547 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
1548 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
1549 ""
1550 "*
1551{
1552 if (which_alternative == 0)
1553 return \"andi\\t%0,%1,0x00ff\";
1554 else
1555 return mips_move_1word (operands, insn, TRUE);
1556}"
1557 [(set_attr "type" "arith,load,load")
92b4cee1 1558 (set_attr "mode" "HI")
8ef30996
MM		 1559 (set_attr "length" "1,1,2")])
1560
1561(define_insn "zero_extendqisi2"
1562 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
1563 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
1564 ""
1565 "*
1566{
1567 if (which_alternative == 0)
1568 return \"andi\\t%0,%1,0x00ff\";
1569 else
1570 return mips_move_1word (operands, insn, TRUE);
1571}"
1572 [(set_attr "type" "arith,load,load")
92b4cee1 1573 (set_attr "mode" "SI")
8ef30996
MM		 1574 (set_attr "length" "1,1,2")])
1575
1576\f
1577;;
1578;; ....................
1579;;
1580;; SIGN EXTENSION
1581;;
1582;; ....................
1583
1584;; Extension insns.
1585;; Those for integer source operand
1586;; are ordered widest source type first.
1587
1588;; These patterns originally accepted general_operands, however, slightly
1589;; better code is generated by only accepting register_operands, and then
1590;; letting combine generate the lh and lb insns.
1591
1592(define_expand "extendhisi2"
1593 [(set (match_operand:SI 0 "register_operand" "")
1594 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1595 ""
1596 "
1597{
1598 if (optimize && GET_CODE (operands[1]) == MEM)
1599 operands[1] = force_not_mem (operands[1]);
1600
1601 if (GET_CODE (operands[1]) != MEM)
1602 {
1603 rtx op1 = gen_lowpart (SImode, operands[1]);
1604 rtx temp = gen_reg_rtx (SImode);
1605 rtx shift = gen_rtx (CONST_INT, VOIDmode, 16);
1606
1607 emit_insn (gen_ashlsi3 (temp, op1, shift));
1608 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
1609 DONE;
1610 }
1611}")
1612
1613(define_insn "extendhisi2_internal"
1614 [(set (match_operand:SI 0 "register_operand" "=d,d")
1615 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
1616 ""
1617 "* return mips_move_1word (operands, insn, FALSE);"
92b4cee1
MM		 1618 [(set_attr "type" "load")
1619 (set_attr "mode" "SI")
8ef30996
MM		 1620 (set_attr "length" "1,2")])
1621
1622(define_expand "extendqihi2"
1623 [(set (match_operand:HI 0 "register_operand" "")
1624 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1625 ""
1626 "
1627{
1628 if (optimize && GET_CODE (operands[1]) == MEM)
1629 operands[1] = force_not_mem (operands[1]);
1630
1631 if (GET_CODE (operands[1]) != MEM)
1632 {
1633 rtx op0 = gen_lowpart (SImode, operands[0]);
1634 rtx op1 = gen_lowpart (SImode, operands[1]);
1635 rtx temp = gen_reg_rtx (SImode);
1636 rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
1637
1638 emit_insn (gen_ashlsi3 (temp, op1, shift));
1639 emit_insn (gen_ashrsi3 (op0, temp, shift));
1640 DONE;
1641 }
1642}")
1643
1644(define_insn "extendqihi2_internal"
1645 [(set (match_operand:HI 0 "register_operand" "=d,d")
1646 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
1647 ""
1648 "* return mips_move_1word (operands, insn, FALSE);"
92b4cee1
MM		 1649 [(set_attr "type" "load")
1650 (set_attr "mode" "SI")
8ef30996
MM		 1651 (set_attr "length" "1,2")])
1652
1653
1654(define_expand "extendqisi2"
1655 [(set (match_operand:SI 0 "register_operand" "")
1656 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1657 ""
1658 "
1659{
1660 if (optimize && GET_CODE (operands[1]) == MEM)
1661 operands[1] = force_not_mem (operands[1]);
1662
1663 if (GET_CODE (operands[1]) != MEM)
1664 {
1665 rtx op1 = gen_lowpart (SImode, operands[1]);
1666 rtx temp = gen_reg_rtx (SImode);
1667 rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
1668
1669 emit_insn (gen_ashlsi3 (temp, op1, shift));
1670 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
1671 DONE;
1672 }
1673}")
1674
1675(define_insn "extendqisi2_insn"
1676 [(set (match_operand:SI 0 "register_operand" "=d,d")
1677 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
1678 ""
1679 "* return mips_move_1word (operands, insn, FALSE);"
92b4cee1
MM		 1680 [(set_attr "type" "load")
1681 (set_attr "mode" "SI")
8ef30996
MM		 1682 (set_attr "length" "1,2")])
1683
1684
1685(define_insn "extendsfdf2"
1686 [(set (match_operand:DF 0 "register_operand" "=f")
1687 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
1688 "TARGET_HARD_FLOAT"
1689 "cvt.d.s\\t%0,%1"
1690 [(set_attr "type" "fcvt")
1691 (set_attr "mode" "DF")
1692 (set_attr "length" "1")])
1693
1694\f
1695
1696;;
1697;; ....................
1698;;
1699;; CONVERSIONS
1700;;
1701;; ....................
1702
1703(define_insn "fix_truncdfsi2_internal"
1704 [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
1705 (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
1706 (clobber (match_operand:SI 2 "register_operand" "d,*d,d,d"))
1707 (clobber (match_operand:DF 3 "register_operand" "f,*f,f,f"))]
1708 "TARGET_HARD_FLOAT"
1709 "*
1710{
1711 rtx xoperands[10];
1712
1713 if (which_alternative == 1)
1714 return \"trunc.w.d %0,%1,%2\";
1715
1716 output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
1717
1718 xoperands[0] = operands[0];
1719 xoperands[1] = operands[3];
1720 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1721 return \"\";
1722}"
92b4cee1
MM		 1723 [(set_attr "type" "fcvt")
1724 (set_attr "mode" "DF")
8ef30996
MM		 1725 (set_attr "length" "14,12,13,14")])
1726
1727
1728(define_expand "fix_truncdfsi2"
1729 [(parallel [(set (match_operand:SI 0 "register_operand" "=d")
1730 (fix:SI (match_operand:DF 1 "register_operand" "f")))
1731 (clobber (match_dup 2))
1732 (clobber (match_dup 3))])]
1733 "TARGET_HARD_FLOAT"
1734 "
1735{
1736 operands[2] = gen_reg_rtx (SImode); /* gp reg that saves FP status bits */
1737 operands[3] = gen_reg_rtx (DFmode); /* fp reg that gets the conversion */
1738
1739 /* Fall through and generate default code */
1740}")
1741
1742(define_insn "fix_truncsfsi2_internal"
1743 [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
1744 (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
1745 (clobber (match_operand:SI 2 "register_operand" "d,*d,d,d"))
1746 (clobber (match_operand:SF 3 "register_operand" "f,*f,f,f"))]
1747 "TARGET_HARD_FLOAT"
1748 "*
1749{
1750 rtx xoperands[10];
1751
1752 if (which_alternative == 1)
1753 return \"trunc.w.s %0,%1,%2\";
1754
1755 output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
1756
1757 xoperands[0] = operands[0];
1758 xoperands[1] = operands[3];
1759 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1760 return \"\";
1761}"
92b4cee1
MM		 1762 [(set_attr "type" "fcvt")
1763 (set_attr "mode" "SF")
8ef30996
MM		 1764 (set_attr "length" "14,12,13,14")])
1765
1766
1767(define_expand "fix_truncsfsi2"
1768 [(parallel [(set (match_operand:SI 0 "register_operand" "=f")
1769 (fix:SI (match_operand:SF 1 "register_operand" "f")))
1770 (clobber (match_dup 2))
1771 (clobber (match_dup 3))])]
1772 "TARGET_HARD_FLOAT"
1773 "
1774{
1775 operands[2] = gen_reg_rtx (SImode); /* gp reg that saves FP status bits */
1776 operands[3] = gen_reg_rtx (SFmode); /* fp reg that gets the conversion */
1777
1778 /* Fall through and generate default code */
1779}")
1780
1781
1782(define_insn "floatsidf2"
bbdb5552
MM		 1783 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
1784 (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
8ef30996 1785 "TARGET_HARD_FLOAT"
bbdb5552
MM		 1786 "*
1787{
1788 dslots_load_total++;
1789 if (GET_CODE (operands[1]) == MEM)
5cccf78f 1790 return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
bbdb5552
MM		 1791
1792 return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
1793}"
92b4cee1
MM		 1794 [(set_attr "type" "fcvt")
1795 (set_attr "mode" "DF")
bbdb5552 1796 (set_attr "length" "3,4,3")])
8ef30996
MM		 1797
1798(define_insn "floatsisf2"
bbdb5552
MM		 1799 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
1800 (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
8ef30996 1801 "TARGET_HARD_FLOAT"
bbdb5552
MM		 1802 "*
1803{
1804 dslots_load_total++;
1805 if (GET_CODE (operands[1]) == MEM)
5cccf78f 1806 return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
bbdb5552
MM		 1807
1808 return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
1809}"
92b4cee1
MM		 1810 [(set_attr "type" "fcvt")
1811 (set_attr "mode" "SF")
bbdb5552
MM		 1812 (set_attr "length" "3,4,3")])
1813
8ef30996
MM		 1814
1815(define_expand "fixuns_truncdfsi2"
1816 [(set (match_operand:SI 0 "register_operand" "")
1817 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
1818 "TARGET_HARD_FLOAT"
1819 "
1820{
1821 rtx reg1 = gen_reg_rtx (DFmode);
1822 rtx reg2 = gen_reg_rtx (DFmode);
1823 rtx reg3 = gen_reg_rtx (SImode);
1824 rtx label1 = gen_label_rtx ();
1825 rtx label2 = gen_label_rtx ();
1826 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
1827
1828 if (reg1) /* turn off complaints about unreached code */
1829 {
1830 extern rtx gen_cmpdf ();
1831 emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
1832 do_pending_stack_adjust ();
1833
1834 emit_insn (gen_cmpdf (operands[1], reg1));
1835 emit_jump_insn (gen_bge (label1));
1836
1837 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
1838 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
1839 gen_rtx (LABEL_REF, VOIDmode, label2)));
1840 emit_barrier ();
1841
1842 emit_label (label1);
1843 emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
1844 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
1845
1846 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
1847 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
1848
1849 emit_label (label2);
1850
1851 /* allow REG_NOTES to be set on last insn (labels don't have enough
1852 fields, and can't be used for REG_NOTES anyway). */
1853 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
1854 DONE;
1855 }
1856}")
1857
1858(define_expand "fixuns_truncsfsi2"
1859 [(set (match_operand:SI 0 "register_operand" "")
1860 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
1861 "TARGET_HARD_FLOAT"
1862 "
1863{
1864 rtx reg1 = gen_reg_rtx (SFmode);
1865 rtx reg2 = gen_reg_rtx (SFmode);
1866 rtx reg3 = gen_reg_rtx (SImode);
1867 rtx label1 = gen_label_rtx ();
1868 rtx label2 = gen_label_rtx ();
1869 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
1870
1871 if (reg1) /* turn off complaints about unreached code */
1872 {
1873 extern rtx gen_cmpsf ();
1874 emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
1875 do_pending_stack_adjust ();
1876
1877 emit_insn (gen_cmpsf (operands[1], reg1));
1878 emit_jump_insn (gen_bge (label1));
1879
1880 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
1881 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
1882 gen_rtx (LABEL_REF, VOIDmode, label2)));
1883 emit_barrier ();
1884
1885 emit_label (label1);
1886 emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
1887 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
1888
1889 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
1890 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
1891
1892 emit_label (label2);
1893
1894 /* allow REG_NOTES to be set on last insn (labels don't have enough
1895 fields, and can't be used for REG_NOTES anyway). */
1896 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
1897 DONE;
1898 }
1899}")
1900
1901\f
1902;;
1903;; ....................
1904;;
1905;; DATA MOVEMENT
1906;;
1907;; ....................
1908
1909;; unaligned word moves generated by the block moves.
8ef30996
MM		 1910
1911(define_expand "movsi_unaligned"
6d518002
MM		 1912 [(set (match_operand:SI 0 "general_operand" "")
1913 (unspec [(match_operand:SI 1 "general_operand" "")] 0))]
8ef30996
MM		 1914 ""
1915 "
1916{
8ef30996
MM		 1917 extern rtx gen_movsi_ulw ();
1918 extern rtx gen_movsi ();
1919
842eb20e
MM		 1920 /* Handle loads. */
1921 if (GET_CODE (operands[0]) == MEM)
8ef30996
MM		 1922 {
1923 rtx reg = gen_reg_rtx (SImode);
842eb20e
MM		 1924 rtx insn = emit_insn (gen_movsi_ulw (reg, operands[1]));
1925 rtx addr = XEXP (operands[0], 0);
1926 if (CONSTANT_P (addr))
1927 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUIV, addr, REG_NOTES (insn));
1928
1929 if (reg_or_0_operand (operands[1], SImode))
1930 DONE;
8ef30996 1931
8ef30996
MM		 1932 operands[1] = reg;
1933 }
1934
1935 /* Generate appropriate load, store. If not a load or store,
1936 do a normal movsi. */
1937 if (GET_CODE (operands[0]) != MEM && GET_CODE (operands[1]) != MEM)
1938 {
1939 emit_insn (gen_movsi (operands[0], operands[1]));
1940 DONE;
1941 }
1942
1943 /* Fall through and generate normal code. */
1944}")
1945
1946(define_insn "movsi_ulw"
1947 [(set (match_operand:SI 0 "register_operand" "=&d,&d,d,d")
6d518002 1948 (unspec [(match_operand:SI 1 "general_operand" "R,o,dIKL,M")] 0))]
8ef30996
MM		 1949 ""
1950 "*
1951{
1952 extern rtx eliminate_constant_term ();
1953 enum rtx_code code;
1954 char *ret;
6d518002 1955 rtx offset;
8ef30996
MM		 1956 rtx addr;
1957 rtx mem_addr;
1958
1959 if (which_alternative != 0)
1960 return mips_move_1word (operands, insn, FALSE);
1961
1962 if (TARGET_STATS)
1963 mips_count_memory_refs (operands[1], 2);
1964
1965 /* The stack/frame pointers are always aligned, so we can convert
1966 to the faster lw if we are referencing an aligned stack location. */
1967
6d518002 1968 offset = const0_rtx;
8ef30996
MM		 1969 addr = XEXP (operands[1], 0);
1970 mem_addr = eliminate_constant_term (addr, &offset);
1971
6d518002 1972 if ((INTVAL (offset) & (UNITS_PER_WORD-1)) == 0
8ef30996
MM		 1973 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
1974 ret = \"lw\\t%0,%1\";
1975
1976 else
1977 {
1978 ret = \"ulw\\t%0,%1\";
1979 if (TARGET_GAS)
1980 {
1981 enum rtx_code code = GET_CODE (addr);
1982
1983 if (code == CONST || code == SYMBOL_REF || code == LABEL_REF)
1984 {
1985 operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 1);
1986 ret = \"%[la\\t%2,%1\;ulw\\t%0,0(%2)%]\";
1987 }
1988 }
1989 }
1990
1991 return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
1992}"
1993 [(set_attr "type" "load,load,move,arith")
92b4cee1 1994 (set_attr "mode" "SI")
8ef30996
MM		 1995 (set_attr "length" "2,4,1,2")])
1996
1997(define_insn "movsi_usw"
1998 [(set (match_operand:SI 0 "memory_operand" "=R,o")
6d518002 1999 (unspec [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 0))]
8ef30996
MM		 2000 ""
2001 "*
2002{
2003 extern rtx eliminate_constant_term ();
6d518002 2004 rtx offset = const0_rtx;
8ef30996
MM		 2005 rtx addr = XEXP (operands[0], 0);
2006 rtx mem_addr = eliminate_constant_term (addr, &offset);
2007
2008 if (TARGET_STATS)
2009 mips_count_memory_refs (operands[0], 2);
2010
2011 /* The stack/frame pointers are always aligned, so we can convert
2012 to the faster sw if we are referencing an aligned stack location. */
2013
6d518002 2014 if ((INTVAL (offset) & (UNITS_PER_WORD-1)) == 0
8ef30996
MM		 2015 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
2016 return \"sw\\t%1,%0\";
2017
2018
2019 if (TARGET_GAS)
2020 {
2021 enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
2022
2023 if (code == CONST || code == SYMBOL_REF || code == LABEL_REF)
2024 {
2025 operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 1);
2026 return \"%[la\\t%2,%0\;usw\\t%z1,0(%2)%]\";
2027 }
2028 }
2029
2030 return \"usw\\t%z1,%0\";
2031}"
92b4cee1
MM		 2032 [(set_attr "type" "store")
2033 (set_attr "mode" "SI")
8ef30996
MM		 2034 (set_attr "length" "2,4")])
2035
2036;; 64-bit integer moves
2037
2038;; Unlike most other insns, the move insns can't be split with
2039;; different predicates, because register spilling and other parts of
2040;; the compiler, have memoized the insn number already.
2041
2042(define_insn "movdi"
6d518002
MM		 2043 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*d,*x")
2044 (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,*x,*d"))]
8ef30996
MM		 2045 ""
2046 "* return mips_move_2words (operands, insn); "
6d518002 2047 [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo")
92b4cee1 2048 (set_attr "mode" "DI")
6d518002 2049 (set_attr "length" "2,4,2,4,2,4,2,2")])
8ef30996
MM		 2050
2051(define_split
2052 [(set (match_operand:DI 0 "register_operand" "")
2053 (match_operand:DI 1 "register_operand" ""))]
26b8e6e5 2054 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2055 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2056 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
2057
2058 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
2059 (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
2060 "")
2061
2062
2063;; 32-bit Integer moves
2064
2065(define_split
2066 [(set (match_operand:SI 0 "register_operand" "")
2067 (match_operand:SI 1 "large_int" ""))]
26b8e6e5 2068 "!TARGET_DEBUG_D_MODE"
8ef30996
MM		 2069 [(set (match_dup 0)
2070 (match_dup 2))
2071 (set (match_dup 0)
2072 (ior:SI (match_dup 0)
2073 (match_dup 3)))]
2074 "
2075{
2076 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff0000);
2077 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0x0000ffff);
2078}")
2079
2080;; Unlike most other insns, the move insns can't be split with
2081;; different predicates, because register spilling and other parts of
2082;; the compiler, have memoized the insn number already.
2083
f3b39eba
MM		 2084(define_expand "movsi"
2085 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2086 (match_operand:SI 1 "general_operand" ""))]
2087 ""
2088 "
2089{
2090 /* If this is a half-pic address being moved to a register, convert the
2091 address into a load, so that scheduling and stuff works properly. */
2092
2093 if (HALF_PIC_P()
2094 && GET_CODE (operands[0]) == REG
2095 && GET_CODE (operands[1]) == SYMBOL_REF
2096 && HALF_PIC_ADDRESS_P (operands[1]))
2097 {
2098 rtx ptr = HALF_PIC_PTR (operands[1]);
2099 if (XSTR (ptr, 0) != XSTR (operands[1], 0))
2100 {
2101 emit_move_insn (operands[0], gen_rtx (MEM, Pmode, ptr));
2102 DONE;
2103 }
2104 }
2105}")
2106
2107(define_insn "movsi_internal"
ddd8ab48
MM		 2108 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*fz,*f,*f,*f,*R,*m,*x,*d")
2109 (match_operand:SI 1 "general_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*fz,*d,*f,*R,*m,*f,*f,*d,*x"))]
8ef30996
MM		 2110 ""
2111 "* return mips_move_1word (operands, insn, TRUE);"
2112 [(set_attr "type" "move,pic,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo")
92b4cee1 2113 (set_attr "mode" "SI")
8ef30996
MM		 2114 (set_attr "length" "1,4,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1")])
2115
2116;; 16-bit Integer moves
2117
2118;; Unlike most other insns, the move insns can't be split with
2119;; different predicates, because register spilling and other parts of
2120;; the compiler, have memoized the insn number already.
2121;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
2122
2123(define_insn "movhi"
2124 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f,*x,*d")
ddd8ab48 2125 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*fz,*d,*f,*d,*x"))]
8ef30996
MM		 2126 ""
2127 "* return mips_move_1word (operands, insn, TRUE);"
2128 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
92b4cee1 2129 (set_attr "mode" "HI")
8ef30996
MM		 2130 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
2131
2132;; 8-bit Integer moves
2133
2134;; Unlike most other insns, the move insns can't be split with
2135;; different predicates, because register spilling and other parts of
2136;; the compiler, have memoized the insn number already.
2137;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
2138
2139(define_insn "movqi"
2140 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f,*x,*d")
ddd8ab48 2141 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*fz,*d,*f,*d,*x"))]
8ef30996
MM		 2142 ""
2143 "* return mips_move_1word (operands, insn, TRUE);"
2144 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
92b4cee1 2145 (set_attr "mode" "QI")
8ef30996
MM		 2146 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
2147
2148
2149;; 32-bit floating point moves
2150
2151(define_insn "movsf"
2152 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
2153 (match_operand:SF 1 "general_operand" "f,G,R,Em,fG,fG,*d,*f,*Gd,*R,*Em,*d,*d"))]
2154 ""
2155 "* return mips_move_1word (operands, insn, FALSE);"
2156 [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
92b4cee1 2157 (set_attr "mode" "SF")
8ef30996
MM		 2158 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")])
2159
2160;; 64-bit floating point moves
2161
2162(define_insn "movdf"
2163 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,o,f,*f,*d,*d,*d,*d,*R,*o")
2164 (match_operand:DF 1 "general_operand" "f,R,o,fG,fG,E,*d,*f,*dG,*R,*oE,*d,*d"))]
2165 ""
2166 "* return mips_move_2words (operands, insn); "
2167 [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
92b4cee1 2168 (set_attr "mode" "DF")
8ef30996
MM		 2169 (set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")])
2170
2171(define_split
2172 [(set (match_operand:DF 0 "register_operand" "")
2173 (match_operand:DF 1 "register_operand" ""))]
26b8e6e5 2174 "reload_completed && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2175 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2176 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
2177
2178 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
2179 (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
2180 "")
2181
26b8e6e5 2182\f
8ef30996
MM		 2183;; Block moves, see mips.c for more details.
2184;; Argument 0 is the destination
2185;; Argument 1 is the source
2186;; Argument 2 is the length
2187;; Argument 3 is the alignment
2188
2189(define_expand "movstrsi"
2190 [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
2191 (mem:BLK (match_operand:BLK 1 "general_operand" "")))
2192 (use (match_operand:SI 2 "arith32_operand" ""))
2193 (use (match_operand:SI 3 "immediate_operand" ""))])]
2194 ""
2195 "
2196{
2197 if (operands[0]) /* avoid unused code messages */
2198 {
2199 expand_block_move (operands);
2200 DONE;
2201 }
2202}")
2203
842eb20e
MM		 2204;; Insn generated by block moves
2205
2206(define_insn "movstrsi_internal"
26b8e6e5
MM		 2207 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
2208 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
2209 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
2210 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
2211 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
2212 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
2213 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
2214 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
2215 (use (const_int 0))] ;; normal block move
2216 ""
2217 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
842eb20e
MM		 2218 [(set_attr "type" "multi")
2219 (set_attr "mode" "none")
2220 (set_attr "length" "20")])
2221
26b8e6e5
MM		 2222;; Split a block move into 2 parts, the first part is everything
2223;; except for the last move, and the second part is just the last
2224;; store, which is exactly 1 instruction (ie, not a usw), so it can
2225;; fill a delay slot. This also prevents a bug in delayed branches
2226;; from showing up, which reuses one of the registers in our clobbers.
2227
2228(define_split
2229 [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
2230 (mem:BLK (match_operand:SI 1 "register_operand" "")))
2231 (clobber (match_operand:SI 4 "register_operand" ""))
2232 (clobber (match_operand:SI 5 "register_operand" ""))
2233 (clobber (match_operand:SI 6 "register_operand" ""))
2234 (clobber (match_operand:SI 7 "register_operand" ""))
2235 (use (match_operand:SI 2 "small_int" ""))
2236 (use (match_operand:SI 3 "small_int" ""))
2237 (use (const_int 0))]
2238
2239 "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
2240
2241 ;; All but the last move
2242 [(parallel [(set (mem:BLK (match_dup 0))
2243 (mem:BLK (match_dup 1)))
2244 (clobber (match_dup 4))
2245 (clobber (match_dup 5))
2246 (clobber (match_dup 6))
2247 (clobber (match_dup 7))
2248 (use (match_dup 2))
2249 (use (match_dup 3))
2250 (use (const_int 1))])
2251
2252 ;; The last store, so it can fill a delay slot
2253 (parallel [(set (mem:BLK (match_dup 0))
2254 (mem:BLK (match_dup 1)))
2255 (clobber (match_dup 4))
2256 (clobber (match_dup 5))
2257 (clobber (match_dup 6))
2258 (clobber (match_dup 7))
2259 (use (match_dup 2))
2260 (use (match_dup 3))
2261 (use (const_int 2))])]
2262
2263 "")
2264
2265(define_insn "movstrsi_internal2"
2266 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
2267 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
2268 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
2269 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
2270 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
2271 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
2272 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
2273 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
2274 (use (const_int 1))] ;; all but last store
2275 ""
2276 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
2277 [(set_attr "type" "multi")
2278 (set_attr "mode" "none")
2279 (set_attr "length" "20")])
2280
2281(define_insn "movstrsi_internal3"
2282 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
2283 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
2284 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
2285 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
2286 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
2287 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
2288 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
2289 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
2290 (use (const_int 2))] ;; just last store of block mvoe
2291 ""
2292 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
2293 [(set_attr "type" "store")
2294 (set_attr "mode" "none")
2295 (set_attr "length" "1")])
2296
8ef30996
MM		 2297\f
2298;;
2299;; ....................
2300;;
2301;; SHIFTS
2302;;
2303;; ....................
2304
2305(define_insn "ashlsi3"
2306 [(set (match_operand:SI 0 "register_operand" "=d")
2307 (ashift:SI (match_operand:SI 1 "register_operand" "d")
2308 (match_operand:SI 2 "arith_operand" "dI")))]
2309 ""
2310 "*
2311{
2312 if (GET_CODE (operands[2]) == CONST_INT)
2313 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2314
2315 return \"sll\\t%0,%1,%2\";
2316}"
2317 [(set_attr "type" "arith")
2318 (set_attr "mode" "SI")
2319 (set_attr "length" "1")])
2320
2321
2322(define_expand "ashldi3"
2323 [(parallel [(set (match_operand:DI 0 "register_operand" "")
2324 (ashift:DI (match_operand:DI 1 "register_operand" "")
2325 (match_operand:SI 2 "arith_operand" "")))
2326 (clobber (match_dup 3))])]
2327 "!TARGET_DEBUG_G_MODE"
2328 "operands[3] = gen_reg_rtx (SImode);")
2329
2330
2331(define_insn "ashldi3_internal"
2332 [(set (match_operand:DI 0 "register_operand" "=d")
2333 (ashift:DI (match_operand:DI 1 "register_operand" "d")
2334 (match_operand:SI 2 "register_operand" "d")))
2335 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2336 "!TARGET_DEBUG_G_MODE"
2337 "*
2338{
2339 operands[4] = const0_rtx;
2340 dslots_jump_total += 3;
2341 dslots_jump_filled += 2;
2342
2343 return \"sll\\t%3,%2,26\\n\\
2344\\tbgez\\t%3,1f\\n\\
2345\\tsll\\t%M0,%L1,%2\\n\\
2346\\t%(b\\t3f\\n\\
2347\\tmove\\t%L0,%z4%)\\n\\
2348\\n\\
23491:\\n\\
2350\\t%(beq\\t%3,%z4,2f\\n\\
2351\\tsll\\t%M0,%M1,%2%)\\n\\
2352\\n\\
2353\\tsubu\\t%3,%z4,%2\\n\\
2354\\tsrl\\t%3,%L1,%3\\n\\
2355\\tor\\t%M0,%M0,%3\\n\\
23562:\\n\\
2357\\tsll\\t%L0,%L1,%2\\n\\
23583:\";
2359}"
2360 [(set_attr "type" "darith")
2361 (set_attr "mode" "SI")
2362 (set_attr "length" "12")])
2363
2364
2365(define_insn "ashldi3_internal2"
2366 [(set (match_operand:DI 0 "register_operand" "=d")
2367 (ashift:DI (match_operand:DI 1 "register_operand" "d")
2368 (match_operand:SI 2 "small_int" "IJK")))
2369 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2370 "!TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
2371 "*
2372{
2373 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2374 operands[4] = const0_rtx;
2375 return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
2376}"
2377 [(set_attr "type" "darith")
2378 (set_attr "mode" "DI")
2379 (set_attr "length" "2")])
2380
2381
2382(define_split
2383 [(set (match_operand:DI 0 "register_operand" "")
2384 (ashift:DI (match_operand:DI 1 "register_operand" "")
2385 (match_operand:SI 2 "small_int" "")))
2386 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2387 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2388 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2389 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2390 && (INTVAL (operands[2]) & 32) != 0"
2391
2392 [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
2393 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
2394
2395 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2396
2397
2398(define_split
2399 [(set (match_operand:DI 0 "register_operand" "")
2400 (ashift:DI (match_operand:DI 1 "register_operand" "")
2401 (match_operand:SI 2 "small_int" "")))
2402 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2403 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2404 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2405 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2406 && (INTVAL (operands[2]) & 32) != 0"
2407
2408 [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
2409 (set (subreg:SI (match_dup 0) 1) (const_int 0))]
2410
2411 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2412
2413
2414(define_insn "ashldi3_internal3"
2415 [(set (match_operand:DI 0 "register_operand" "=d")
2416 (ashift:DI (match_operand:DI 1 "register_operand" "d")
2417 (match_operand:SI 2 "small_int" "IJK")))
2418 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2419 "!TARGET_DEBUG_G_MODE
2420 && (INTVAL (operands[2]) & 63) < 32
2421 && (INTVAL (operands[2]) & 63) != 0"
2422 "*
2423{
2424 int amount = INTVAL (operands[2]);
2425
2426 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2427 operands[4] = const0_rtx;
2428 operands[5] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2429
2430 return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
2431}"
2432 [(set_attr "type" "darith")
2433 (set_attr "mode" "DI")
2434 (set_attr "length" "4")])
2435
2436
2437(define_split
2438 [(set (match_operand:DI 0 "register_operand" "")
2439 (ashift:DI (match_operand:DI 1 "register_operand" "")
2440 (match_operand:SI 2 "small_int" "")))
2441 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2442 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2443 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2444 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2445 && (INTVAL (operands[2]) & 63) < 32
2446 && (INTVAL (operands[2]) & 63) != 0"
2447
2448 [(set (subreg:SI (match_dup 0) 1)
2449 (ashift:SI (subreg:SI (match_dup 1) 1)
2450 (match_dup 2)))
2451
2452 (set (match_dup 3)
2453 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
2454 (match_dup 4)))
2455
2456 (set (subreg:SI (match_dup 0) 1)
2457 (ior:SI (subreg:SI (match_dup 0) 1)
2458 (match_dup 3)))
2459
2460 (set (subreg:SI (match_dup 0) 0)
2461 (ashift:SI (subreg:SI (match_dup 1) 0)
2462 (match_dup 2)))]
2463 "
2464{
2465 int amount = INTVAL (operands[2]);
2466 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2467 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2468}")
2469
2470
2471(define_split
2472 [(set (match_operand:DI 0 "register_operand" "")
2473 (ashift:DI (match_operand:DI 1 "register_operand" "")
2474 (match_operand:SI 2 "small_int" "")))
2475 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2476 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2477 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2478 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2479 && (INTVAL (operands[2]) & 63) < 32
2480 && (INTVAL (operands[2]) & 63) != 0"
2481
2482 [(set (subreg:SI (match_dup 0) 0)
2483 (ashift:SI (subreg:SI (match_dup 1) 0)
2484 (match_dup 2)))
2485
2486 (set (match_dup 3)
2487 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
2488 (match_dup 4)))
2489
2490 (set (subreg:SI (match_dup 0) 0)
2491 (ior:SI (subreg:SI (match_dup 0) 0)
2492 (match_dup 3)))
2493
2494 (set (subreg:SI (match_dup 0) 1)
2495 (ashift:SI (subreg:SI (match_dup 1) 1)
2496 (match_dup 2)))]
2497 "
2498{
2499 int amount = INTVAL (operands[2]);
2500 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2501 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2502}")
2503
2504
2505(define_insn "ashrsi3"
2506 [(set (match_operand:SI 0 "register_operand" "=d")
2507 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
2508 (match_operand:SI 2 "arith_operand" "dI")))]
2509 ""
2510 "*
2511{
2512 if (GET_CODE (operands[2]) == CONST_INT)
2513 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2514
2515 return \"sra\\t%0,%1,%2\";
2516}"
2517 [(set_attr "type" "arith")
2518 (set_attr "mode" "SI")
2519 (set_attr "length" "1")])
2520
2521
2522(define_expand "ashrdi3"
2523 [(parallel [(set (match_operand:DI 0 "register_operand" "")
2524 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2525 (match_operand:SI 2 "arith_operand" "")))
2526 (clobber (match_dup 3))])]
2527 "!TARGET_DEBUG_G_MODE"
2528 "operands[3] = gen_reg_rtx (SImode);")
2529
2530
2531(define_insn "ashrdi3_internal"
2532 [(set (match_operand:DI 0 "register_operand" "=d")
2533 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2534 (match_operand:SI 2 "register_operand" "d")))
2535 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2536 "!TARGET_DEBUG_G_MODE"
2537 "*
2538{
2539 operands[4] = const0_rtx;
2540 dslots_jump_total += 3;
2541 dslots_jump_filled += 2;
2542
2543 return \"sll\\t%3,%2,26\\n\\
2544\\tbgez\\t%3,1f\\n\\
2545\\tsra\\t%L0,%M1,%2\\n\\
2546\\t%(b\\t3f\\n\\
2547\\tsra\\t%M0,%M1,31%)\\n\\
2548\\n\\
25491:\\n\\
2550\\t%(beq\\t%3,%z4,2f\\n\\
2551\\tsrl\\t%L0,%L1,%2%)\\n\\
2552\\n\\
2553\\tsubu\\t%3,%z4,%2\\n\\
2554\\tsll\\t%3,%M1,%3\\n\\
2555\\tor\\t%L0,%L0,%3\\n\\
25562:\\n\\
2557\\tsra\\t%M0,%M1,%2\\n\\
25583:\";
2559}"
2560 [(set_attr "type" "darith")
2561 (set_attr "mode" "DI")
2562 (set_attr "length" "12")])
2563
2564
2565(define_insn "ashrdi3_internal2"
2566 [(set (match_operand:DI 0 "register_operand" "=d")
2567 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2568 (match_operand:SI 2 "small_int" "IJK")))
2569 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2570 "!TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
2571 "*
2572{
2573 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2574 return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
2575}"
2576 [(set_attr "type" "darith")
2577 (set_attr "mode" "DI")
2578 (set_attr "length" "2")])
2579
2580
2581(define_split
2582 [(set (match_operand:DI 0 "register_operand" "")
2583 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2584 (match_operand:SI 2 "small_int" "")))
2585 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2586 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2587 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2588 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2589 && (INTVAL (operands[2]) & 32) != 0"
2590
2591 [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
2592 (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))]
2593
2594 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2595
2596
2597(define_split
2598 [(set (match_operand:DI 0 "register_operand" "")
2599 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2600 (match_operand:SI 2 "small_int" "")))
2601 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2602 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2603 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2604 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2605 && (INTVAL (operands[2]) & 32) != 0"
2606
2607 [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
2608 (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
2609
2610 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2611
2612
2613(define_insn "ashrdi3_internal3"
2614 [(set (match_operand:DI 0 "register_operand" "=d")
2615 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2616 (match_operand:SI 2 "small_int" "IJK")))
2617 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2618 "!TARGET_DEBUG_G_MODE
2619 && (INTVAL (operands[2]) & 63) < 32
2620 && (INTVAL (operands[2]) & 63) != 0"
2621 "*
2622{
2623 int amount = INTVAL (operands[2]);
2624
2625 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2626 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2627
2628 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
2629}"
2630 [(set_attr "type" "darith")
2631 (set_attr "mode" "DI")
2632 (set_attr "length" "4")])
2633
2634
2635(define_split
2636 [(set (match_operand:DI 0 "register_operand" "")
2637 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2638 (match_operand:SI 2 "small_int" "")))
2639 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2640 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2641 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2642 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2643 && (INTVAL (operands[2]) & 63) < 32
2644 && (INTVAL (operands[2]) & 63) != 0"
2645
2646 [(set (subreg:SI (match_dup 0) 0)
2647 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
2648 (match_dup 2)))
2649
2650 (set (match_dup 3)
2651 (ashift:SI (subreg:SI (match_dup 1) 1)
2652 (match_dup 4)))
2653
2654 (set (subreg:SI (match_dup 0) 0)
2655 (ior:SI (subreg:SI (match_dup 0) 0)
2656 (match_dup 3)))
2657
2658 (set (subreg:SI (match_dup 0) 1)
2659 (ashiftrt:SI (subreg:SI (match_dup 1) 1)
2660 (match_dup 2)))]
2661 "
2662{
2663 int amount = INTVAL (operands[2]);
2664 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2665 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2666}")
2667
2668
2669(define_split
2670 [(set (match_operand:DI 0 "register_operand" "")
2671 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
2672 (match_operand:SI 2 "small_int" "")))
2673 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2674 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2675 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2676 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2677 && (INTVAL (operands[2]) & 63) < 32
2678 && (INTVAL (operands[2]) & 63) != 0"
2679
2680 [(set (subreg:SI (match_dup 0) 1)
2681 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
2682 (match_dup 2)))
2683
2684 (set (match_dup 3)
2685 (ashift:SI (subreg:SI (match_dup 1) 0)
2686 (match_dup 4)))
2687
2688 (set (subreg:SI (match_dup 0) 1)
2689 (ior:SI (subreg:SI (match_dup 0) 1)
2690 (match_dup 3)))
2691
2692 (set (subreg:SI (match_dup 0) 0)
2693 (ashiftrt:SI (subreg:SI (match_dup 1) 0)
2694 (match_dup 2)))]
2695 "
2696{
2697 int amount = INTVAL (operands[2]);
2698 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2699 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2700}")
2701
2702
2703(define_insn "lshrsi3"
2704 [(set (match_operand:SI 0 "register_operand" "=d")
2705 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
2706 (match_operand:SI 2 "arith_operand" "dI")))]
2707 ""
2708 "*
2709{
2710 if (GET_CODE (operands[2]) == CONST_INT)
2711 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2712
2713 return \"srl\\t%0,%1,%2\";
2714}"
2715 [(set_attr "type" "arith")
2716 (set_attr "mode" "SI")
2717 (set_attr "length" "1")])
2718
2719
2720(define_expand "lshrdi3"
2721 [(parallel [(set (match_operand:DI 0 "register_operand" "")
2722 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2723 (match_operand:SI 2 "arith_operand" "")))
2724 (clobber (match_dup 3))])]
2725 "!TARGET_DEBUG_G_MODE"
2726 "operands[3] = gen_reg_rtx (SImode);")
2727
2728
2729(define_insn "lshrdi3_internal"
2730 [(set (match_operand:DI 0 "register_operand" "=&d")
2731 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2732 (match_operand:SI 2 "register_operand" "d")))
2733 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2734 "!TARGET_DEBUG_G_MODE"
2735 "*
2736{
2737 operands[4] = const0_rtx;
2738 dslots_jump_total += 3;
2739 dslots_jump_filled += 2;
2740
2741 return \"sll\\t%3,%2,26\\n\\
2742\\tbgez\\t%3,1f\\n\\
2743\\tsrl\\t%L0,%M1,%2\\n\\
2744\\t%(b\\t3f\\n\\
2745\\tmove\\t%M0,%z4%)\\n\\
2746\\n\\
27471:\\n\\
2748\\t%(beq\\t%3,%z4,2f\\n\\
2749\\tsrl\\t%L0,%L1,%2%)\\n\\
2750\\n\\
2751\\tsubu\\t%3,%z4,%2\\n\\
2752\\tsll\\t%3,%M1,%3\\n\\
2753\\tor\\t%L0,%L0,%3\\n\\
27542:\\n\\
2755\\tsrl\\t%M0,%M1,%2\\n\\
27563:\";
2757}"
2758 [(set_attr "type" "darith")
2759 (set_attr "mode" "DI")
2760 (set_attr "length" "12")])
2761
2762
2763(define_insn "lshrdi3_internal2"
2764 [(set (match_operand:DI 0 "register_operand" "=d")
2765 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2766 (match_operand:SI 2 "small_int" "IJK")))
2767 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2768 "!TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
2769 "*
2770{
2771 operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
2772 operands[4] = const0_rtx;
2773 return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
2774}"
2775 [(set_attr "type" "darith")
2776 (set_attr "mode" "DI")
2777 (set_attr "length" "2")])
2778
2779
2780(define_split
2781 [(set (match_operand:DI 0 "register_operand" "")
2782 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2783 (match_operand:SI 2 "small_int" "")))
2784 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2785 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2786 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2787 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2788 && (INTVAL (operands[2]) & 32) != 0"
2789
2790 [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
2791 (set (subreg:SI (match_dup 0) 1) (const_int 0))]
2792
2793 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2794
2795
2796(define_split
2797 [(set (match_operand:DI 0 "register_operand" "")
2798 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2799 (match_operand:SI 2 "small_int" "")))
2800 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2801 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2802 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2803 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2804 && (INTVAL (operands[2]) & 32) != 0"
2805
2806 [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
2807 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
2808
2809 "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
2810
2811
2812(define_insn "lshrdi3_internal3"
2813 [(set (match_operand:DI 0 "register_operand" "=d")
2814 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2815 (match_operand:SI 2 "small_int" "IJK")))
2816 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2817 "!TARGET_DEBUG_G_MODE
2818 && (INTVAL (operands[2]) & 63) < 32
2819 && (INTVAL (operands[2]) & 63) != 0"
2820 "*
2821{
2822 int amount = INTVAL (operands[2]);
2823
2824 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2825 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2826
2827 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
2828}"
2829 [(set_attr "type" "darith")
2830 (set_attr "mode" "DI")
2831 (set_attr "length" "4")])
2832
2833
2834(define_split
2835 [(set (match_operand:DI 0 "register_operand" "")
2836 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2837 (match_operand:SI 2 "small_int" "")))
2838 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2839 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2840 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2841 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2842 && (INTVAL (operands[2]) & 63) < 32
2843 && (INTVAL (operands[2]) & 63) != 0"
2844
2845 [(set (subreg:SI (match_dup 0) 0)
2846 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
2847 (match_dup 2)))
2848
2849 (set (match_dup 3)
2850 (ashift:SI (subreg:SI (match_dup 1) 1)
2851 (match_dup 4)))
2852
2853 (set (subreg:SI (match_dup 0) 0)
2854 (ior:SI (subreg:SI (match_dup 0) 0)
2855 (match_dup 3)))
2856
2857 (set (subreg:SI (match_dup 0) 1)
2858 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
2859 (match_dup 2)))]
2860 "
2861{
2862 int amount = INTVAL (operands[2]);
2863 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2864 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2865}")
2866
2867
2868(define_split
2869 [(set (match_operand:DI 0 "register_operand" "")
2870 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
2871 (match_operand:SI 2 "small_int" "")))
2872 (clobber (match_operand:SI 3 "register_operand" ""))]
26b8e6e5 2873 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
8ef30996
MM		 2874 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
2875 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
2876 && (INTVAL (operands[2]) & 63) < 32
2877 && (INTVAL (operands[2]) & 63) != 0"
2878
2879 [(set (subreg:SI (match_dup 0) 1)
2880 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
2881 (match_dup 2)))
2882
2883 (set (match_dup 3)
2884 (ashift:SI (subreg:SI (match_dup 1) 0)
2885 (match_dup 4)))
2886
2887 (set (subreg:SI (match_dup 0) 1)
2888 (ior:SI (subreg:SI (match_dup 0) 1)
2889 (match_dup 3)))
2890
2891 (set (subreg:SI (match_dup 0) 0)
2892 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
2893 (match_dup 2)))]
2894 "
2895{
2896 int amount = INTVAL (operands[2]);
2897 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
2898 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
2899}")
2900
2901\f
2902;;
2903;; ....................
2904;;
2905;; COMPARISONS
2906;;
2907;; ....................
2908
2909;; Flow here is rather complex:
2910;;
2911;; 1) The cmp{si,sf,df} routine is called. It deposits the
2912;; arguments into the branch_cmp array, and the type into
2913;; branch_type. No RTL is generated.
2914;;
2915;; 2) The appropriate branch define_expand is called, which then
2916;; creates the appropriate RTL for the comparison and branch.
2917;; Different CC modes are used, based on what type of branch is
2918;; done, so that we can constrain things appropriately. There
2919;; are assumptions in the rest of GCC that break if we fold the
2920;; operands into the branchs for integer operations, and use cc0
34b650b3
MM		 2921;; for floating point, so we use the fp status register instead.
2922;; If needed, an appropriate temporary is created to hold the
2923;; of the integer compare.
8ef30996
MM		 2924
2925(define_expand "cmpsi"
2926 [(set (cc0)
2927 (compare:CC (match_operand:SI 0 "register_operand" "")
2928 (match_operand:SI 1 "arith_operand" "")))]
2929 ""
2930 "
2931{
2932 if (operands[0]) /* avoid unused code message */
2933 {
2934 branch_cmp[0] = operands[0];
2935 branch_cmp[1] = operands[1];
2936 branch_type = CMP_SI;
2937 DONE;
2938 }
2939}")
2940
2941(define_expand "tstsi"
2942 [(set (cc0)
2943 (match_operand:SI 0 "register_operand" ""))]
2944 ""
2945 "
2946{
2947 if (operands[0]) /* avoid unused code message */
2948 {
2949 branch_cmp[0] = operands[0];
2950 branch_cmp[1] = const0_rtx;
2951 branch_type = CMP_SI;
2952 DONE;
2953 }
2954}")
2955
8ef30996
MM		 2956(define_expand "cmpdf"
2957 [(set (cc0)
2958 (compare:CC_FP (match_operand:DF 0 "register_operand" "")
2959 (match_operand:DF 1 "register_operand" "")))]
2960 "TARGET_HARD_FLOAT"
2961 "
2962{
2963 if (operands[0]) /* avoid unused code message */
2964 {
2965 branch_cmp[0] = operands[0];
2966 branch_cmp[1] = operands[1];
2967 branch_type = CMP_DF;
2968 DONE;
2969 }
2970}")
2971
8ef30996
MM		 2972(define_expand "cmpsf"
2973 [(set (cc0)
2974 (compare:CC_FP (match_operand:SF 0 "register_operand" "")
2975 (match_operand:SF 1 "register_operand" "")))]
2976 "TARGET_HARD_FLOAT"
2977 "
2978{
2979 if (operands[0]) /* avoid unused code message */
2980 {
2981 branch_cmp[0] = operands[0];
2982 branch_cmp[1] = operands[1];
2983 branch_type = CMP_SF;
2984 DONE;
2985 }
2986}")
2987
8ef30996
MM		 2988\f
2989;;
2990;; ....................
2991;;
2992;; CONDITIONAL BRANCHES
2993;;
2994;; ....................
2995
34b650b3 2996(define_insn "branch_fp_ne"
8ef30996 2997 [(set (pc)
34b650b3
MM		 2998 (if_then_else (ne:CC_FP (reg:CC_FP 66)
2999 (const_int 0))
3000 (match_operand 0 "pc_or_label_operand" "")
3001 (match_operand 1 "pc_or_label_operand" "")))]
8ef30996
MM		 3002 ""
3003 "*
3004{
8ef30996 3005 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 3006 return (operands[0] != pc_rtx) ? \"%*bc1t%?\\t%0\" : \"%*bc1f%?\\t%1\";
8ef30996
MM		 3007}"
3008 [(set_attr "type" "branch")
3009 (set_attr "mode" "none")
34b650b3 3010 (set_attr "length" "1")])
8ef30996 3011
34b650b3 3012(define_insn "branch_fp_ne_rev"
8ef30996 3013 [(set (pc)
34b650b3
MM		 3014 (if_then_else (ne:CC_REV_FP (reg:CC_REV_FP 66)
3015 (const_int 0))
3016 (match_operand 0 "pc_or_label_operand" "")
3017 (match_operand 1 "pc_or_label_operand" "")))]
8ef30996
MM		 3018 ""
3019 "*
3020{
8ef30996 3021 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 3022 return (operands[0] != pc_rtx) ? \"%*bc1f%?\\t%0\" : \"%*bc1t%?\\t%1\";
8ef30996
MM		 3023}"
3024 [(set_attr "type" "branch")
3025 (set_attr "mode" "none")
34b650b3 3026 (set_attr "length" "1")])
8ef30996 3027
34b650b3 3028(define_insn "branch_fp_eq"
8ef30996 3029 [(set (pc)
34b650b3
MM		 3030 (if_then_else (eq:CC_FP (reg:CC_FP 66)
3031 (const_int 0))
3032 (match_operand 0 "pc_or_label_operand" "")
3033 (match_operand 1 "pc_or_label_operand" "")))]
8ef30996
MM		 3034 ""
3035 "*
3036{
3037 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 3038 return (operands[0] != pc_rtx) ? \"%*bc1f%?\\t%0\" : \"%*bc1t%?\\t%1\";
8ef30996
MM		 3039}"
3040 [(set_attr "type" "branch")
3041 (set_attr "mode" "none")
3042 (set_attr "length" "1")])
3043
34b650b3 3044(define_insn "branch_fp_eq_rev"
8ef30996 3045 [(set (pc)
34b650b3
MM		 3046 (if_then_else (eq:CC_REV_FP (reg:CC_REV_FP 66)
3047 (const_int 0))
3048 (match_operand 0 "pc_or_label_operand" "")
3049 (match_operand 1 "pc_or_label_operand" "")))]
8ef30996
MM		 3050 ""
3051 "*
3052{
3053 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3 3054 return (operands[0] != pc_rtx) ? \"%*bc1t%?\\t%0\" : \"%*bc1f%?\\t%1\";
8ef30996
MM		 3055}"
3056 [(set_attr "type" "branch")
3057 (set_attr "mode" "none")
3058 (set_attr "length" "1")])
3059
34b650b3
MM		 3060
3061(define_insn "branch_zero"
8ef30996 3062 [(set (pc)
34b650b3
MM		 3063 (if_then_else (match_operator:SI 0 "cmp_op"
3064 [(match_operand:SI 1 "arith32_operand" "rn")
3065 (const_int 0)])
3066 (match_operand 2 "pc_or_label_operand" "")
3067 (match_operand 3 "pc_or_label_operand" "")))]
8ef30996
MM		 3068 ""
3069 "*
3070{
3071 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8ef30996 3072
34b650b3
MM		 3073 /* Handle places where CSE has folded a constant into the register operand. */
3074 if (GET_CODE (operands[1]) == CONST_INT)
8ef30996 3075 {
34b650b3
MM		 3076 int value = INTVAL (operands[1]);
3077 int truth = 0;
3078
3079 switch (GET_CODE (operands[0]))
3080 {
3081 default: abort ();
3082 case EQ: truth = (value == 0); break;
3083 case NE: truth = (value != 0); break;
3084 case GT: truth = (value > 0); break;
3085 case GE: truth = (value >= 0); break;
3086 case LT: truth = (value < 0); break;
3087 case LE: truth = (value <= 0); break;
3088 case GTU: truth = (((unsigned)value) > 0); break;
3089 case GEU: truth = 1; break;
3090 case LTU: truth = 0; break;
3091 case LEU: truth = (((unsigned)value) <= 0); break;
3092 }
3093
3094 if (operands[2] != pc_rtx)
c3f3d7e1 3095 return (truth) ? \"%*beq%?\\t%.,%.,%2\" : \"%*bne%?\\t%.,%.,%2\";
34b650b3 3096 else
c3f3d7e1 3097 return (truth) ? \"%*bne%?\\t%.,%.,%2\" : \"%*beq%?\\t%.,%.,%2\";
8ef30996
MM		 3098 }
3099
34b650b3
MM		 3100 if (operands[2] != pc_rtx)
3101 { /* normal jump */
3102 switch (GET_CODE (operands[0]))
3103 {
3104 case EQ: return \"%*beq%?\\t%z1,%.,%2\";
3105 case NE: return \"%*bne%?\\t%z1,%.,%2\";
3106 case GTU: return \"%*bne%?\\t%z1,%.,%2\";
3107 case LEU: return \"%*beq%?\\t%z1,%.,%2\";
3108 case GEU: return \"%*j\\t%2\";
3109 case LTU: return \"#%*bltuz\\t%z1,%2\";
3110 }
8ef30996 3111
34b650b3 3112 return \"%*b%C0z%?\\t%z1,%2\";
8ef30996 3113 }
34b650b3
MM		 3114 else
3115 { /* inverted jump */
3116 switch (GET_CODE (operands[0]))
3117 {
3118 case EQ: return \"%*bne%?\\t%z1,%.,%3\";
3119 case NE: return \"%*beq%?\\t%z1,%.,%3\";
3120 case GTU: return \"%*beq%?\\t%z1,%.,%3\";
3121 case LEU: return \"%*bne%?\\t%z1,%.,%3\";
3122 case GEU: return \"#%*bgeuz\\t%z1,%3\";
3123 case LTU: return \"%*j\\t%3\";
3124 }
8ef30996 3125
34b650b3
MM		 3126 return \"%*b%N0z%?\\t%z1,%3\";
3127 }
8ef30996
MM		 3128}"
3129 [(set_attr "type" "branch")
3130 (set_attr "mode" "none")
3131 (set_attr "length" "1")])
3132
8ef30996 3133
34b650b3 3134(define_insn "branch_equality"
8ef30996 3135 [(set (pc)
34b650b3
MM		 3136 (if_then_else (match_operator:SI 0 "equality_op"
3137 [(match_operand:SI 1 "register_operand" "d")
3138 (match_operand:SI 2 "register_operand" "d")])
3139 (match_operand 3 "pc_or_label_operand" "")
3140 (match_operand 4 "pc_or_label_operand" "")))]
8ef30996
MM		 3141 ""
3142 "*
3143{
3144 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
34b650b3
MM		 3145 return (operands[3] != pc_rtx)
3146 ? \"%*b%C0%?\\t%z1,%z2,%3\"
3147 : \"%*b%N0%?\\t%z1,%z2,%4\";
8ef30996
MM		 3148}"
3149 [(set_attr "type" "branch")
3150 (set_attr "mode" "none")
34b650b3
MM		 3151 (set_attr "length" "1")])
3152
8ef30996
MM		 3153
3154(define_expand "beq"
3155 [(set (pc)
3156 (if_then_else (eq:CC_EQ (cc0)
3157 (const_int 0))
3158 (label_ref (match_operand 0 "" ""))
3159 (pc)))]
3160 ""
3161 "
3162{
3163 if (operands[0]) /* avoid unused code warning */
3164 {
3165 gen_conditional_branch (operands, EQ);
3166 DONE;
3167 }
3168}")
3169
3170(define_expand "bne"
3171 [(set (pc)
3172 (if_then_else (ne:CC_EQ (cc0)
3173 (const_int 0))
3174 (label_ref (match_operand 0 "" ""))
3175 (pc)))]
3176 ""
3177 "
3178{
3179 if (operands[0]) /* avoid unused code warning */
3180 {
3181 gen_conditional_branch (operands, NE);
3182 DONE;
3183 }
3184}")
3185
3186(define_expand "bgt"
3187 [(set (pc)
3188 (if_then_else (gt:CC (cc0)
3189 (const_int 0))
3190 (label_ref (match_operand 0 "" ""))
3191 (pc)))]
3192 ""
3193 "
3194{
3195 if (operands[0]) /* avoid unused code warning */
3196 {
3197 gen_conditional_branch (operands, GT);
3198 DONE;
3199 }
3200}")
3201
3202(define_expand "bge"
3203 [(set (pc)
3204 (if_then_else (ge:CC (cc0)
3205 (const_int 0))
3206 (label_ref (match_operand 0 "" ""))
3207 (pc)))]
3208 ""
3209 "
3210{
3211 if (operands[0]) /* avoid unused code warning */
3212 {
3213 gen_conditional_branch (operands, GE);
3214 DONE;
3215 }
3216}")
3217
3218(define_expand "blt"
3219 [(set (pc)
3220 (if_then_else (lt:CC (cc0)
3221 (const_int 0))
3222 (label_ref (match_operand 0 "" ""))
3223 (pc)))]
3224 ""
3225 "
3226{
3227 if (operands[0]) /* avoid unused code warning */
3228 {
3229 gen_conditional_branch (operands, LT);
3230 DONE;
3231 }
3232}")
3233
3234(define_expand "ble"
3235 [(set (pc)
3236 (if_then_else (le:CC (cc0)
3237 (const_int 0))
3238 (label_ref (match_operand 0 "" ""))
3239 (pc)))]
3240 ""
3241 "
3242{
3243 if (operands[0]) /* avoid unused code warning */
3244 {
3245 gen_conditional_branch (operands, LE);
3246 DONE;
3247 }
3248}")
3249
3250(define_expand "bgtu"
3251 [(set (pc)
3252 (if_then_else (gtu:CC (cc0)
3253 (const_int 0))
3254 (label_ref (match_operand 0 "" ""))
3255 (pc)))]
3256 ""
3257 "
3258{
3259 if (operands[0]) /* avoid unused code warning */
3260 {
3261 gen_conditional_branch (operands, GTU);
3262 DONE;
3263 }
3264}")
3265
3266(define_expand "bgeu"
3267 [(set (pc)
3268 (if_then_else (geu:CC (cc0)
3269 (const_int 0))
3270 (label_ref (match_operand 0 "" ""))
3271 (pc)))]
3272 ""
3273 "
3274{
3275 if (operands[0]) /* avoid unused code warning */
3276 {
3277 gen_conditional_branch (operands, GEU);
3278 DONE;
3279 }
3280}")
3281
3282
3283(define_expand "bltu"
3284 [(set (pc)
3285 (if_then_else (ltu:CC (cc0)
3286 (const_int 0))
3287 (label_ref (match_operand 0 "" ""))
3288 (pc)))]
3289 ""
3290 "
3291{
3292 if (operands[0]) /* avoid unused code warning */
3293 {
3294 gen_conditional_branch (operands, LTU);
3295 DONE;
3296 }
3297}")
3298
3299(define_expand "bleu"
3300 [(set (pc)
3301 (if_then_else (leu:CC (cc0)
3302 (const_int 0))
3303 (label_ref (match_operand 0 "" ""))
3304 (pc)))]
3305 ""
3306 "
3307{
3308 if (operands[0]) /* avoid unused code warning */
3309 {
3310 gen_conditional_branch (operands, LEU);
3311 DONE;
3312 }
3313}")
3314
3315\f
3316;;
3317;; ....................
3318;;
3319;; SETTING A REGISTER FROM A COMPARISON
3320;;
3321;; ....................
3322
3323(define_expand "seq"
3324 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3
MM		 3325 (eq:SI (match_dup 1)
3326 (match_dup 2)))]
8ef30996
MM		 3327 ""
3328 "
3329{
3330 extern rtx force_reg ();
3331
3332 if (branch_type != CMP_SI)
3333 FAIL;
3334
3335 /* set up operands from compare. */
3336 operands[1] = branch_cmp[0];
3337 operands[2] = branch_cmp[1];
3338
bbdb5552 3339 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3340 {
3341 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
3342 DONE;
3343 }
3344
8ef30996
MM		 3345 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3346 operands[2] = force_reg (SImode, operands[2]);
3347
3348 /* fall through and generate default code */
3349}")
3350
34b650b3
MM		 3351
3352(define_insn "seq_si_zero"
3353 [(set (match_operand:SI 0 "register_operand" "=d")
3354 (eq:SI (match_operand:SI 1 "register_operand" "d")
3355 (const_int 0)))]
8ef30996 3356 ""
34b650b3
MM		 3357 "sltu\\t%0,%1,1"
3358 [(set_attr "type" "arith")
3359 (set_attr "mode" "SI")
3360 (set_attr "length" "1")])
3361
3362(define_insn "seq_si"
3363 [(set (match_operand:SI 0 "register_operand" "=d,d")
3364 (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
3365 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
bbdb5552 3366 "TARGET_DEBUG_C_MODE"
8ef30996 3367 "@
8ef30996 3368 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
34b650b3 3369 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
92b4cee1
MM		 3370 [(set_attr "type" "arith")
3371 (set_attr "mode" "SI")
3372 (set_attr "length" "2")])
8ef30996
MM		 3373
3374(define_split
3375 [(set (match_operand:SI 0 "register_operand" "")
34b650b3
MM		 3376 (eq:SI (match_operand:SI 1 "register_operand" "")
3377 (match_operand:SI 2 "uns_arith_operand" "")))]
bbdb5552 3378 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
26b8e6e5 3379 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8ef30996
MM		 3380 [(set (match_dup 0)
3381 (xor:SI (match_dup 1)
3382 (match_dup 2)))
3383 (set (match_dup 0)
34b650b3 3384 (ltu:SI (match_dup 0)
8ef30996
MM		 3385 (const_int 1)))]
3386 "")
3387
3388(define_expand "sne"
3389 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3
MM		 3390 (ne:SI (match_dup 1)
3391 (match_dup 2)))]
8ef30996
MM		 3392 ""
3393 "
3394{
3395 extern rtx force_reg ();
3396
3397 if (branch_type != CMP_SI)
3398 FAIL;
3399
3400 /* set up operands from compare. */
3401 operands[1] = branch_cmp[0];
3402 operands[2] = branch_cmp[1];
3403
bbdb5552 3404 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3405 {
3406 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
3407 DONE;
3408 }
3409
8ef30996
MM		 3410 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3411 operands[2] = force_reg (SImode, operands[2]);
3412
3413 /* fall through and generate default code */
3414}")
3415
34b650b3
MM		 3416(define_insn "sne_si_zero"
3417 [(set (match_operand:SI 0 "register_operand" "=d")
3418 (ne:SI (match_operand:SI 1 "register_operand" "d")
3419 (const_int 0)))]
8ef30996 3420 ""
34b650b3
MM		 3421 "sltu\\t%0,%.,%1"
3422 [(set_attr "type" "arith")
3423 (set_attr "mode" "SI")
3424 (set_attr "length" "1")])
8ef30996 3425
34b650b3
MM		 3426(define_insn "sne_si"
3427 [(set (match_operand:SI 0 "register_operand" "=d,d")
3428 (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
3429 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
bbdb5552 3430 "TARGET_DEBUG_C_MODE"
34b650b3
MM		 3431 "@
3432 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
3433 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
92b4cee1
MM		 3434 [(set_attr "type" "arith")
3435 (set_attr "mode" "SI")
3436 (set_attr "length" "2")])
8ef30996
MM		 3437
3438(define_split
3439 [(set (match_operand:SI 0 "register_operand" "")
34b650b3
MM		 3440 (ne:SI (match_operand:SI 1 "register_operand" "")
3441 (match_operand:SI 2 "uns_arith_operand" "")))]
bbdb5552 3442 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
26b8e6e5 3443 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8ef30996
MM		 3444 [(set (match_dup 0)
3445 (xor:SI (match_dup 1)
3446 (match_dup 2)))
3447 (set (match_dup 0)
34b650b3 3448 (gtu:SI (match_dup 0)
8ef30996
MM		 3449 (const_int 0)))]
3450 "")
3451
3452(define_expand "sgt"
3453 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3454 (gt:SI (match_dup 1)
8ef30996
MM		 3455 (match_dup 2)))]
3456 ""
3457 "
3458{
3459 extern rtx force_reg ();
3460
3461 if (branch_type != CMP_SI)
3462 FAIL;
3463
3464 /* set up operands from compare. */
3465 operands[1] = branch_cmp[0];
3466 operands[2] = branch_cmp[1];
3467
bbdb5552 3468 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3469 {
3470 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
3471 DONE;
3472 }
3473
8ef30996
MM		 3474 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3475 operands[2] = force_reg (SImode, operands[2]);
3476
3477 /* fall through and generate default code */
3478}")
3479
3480(define_insn "sgt_si"
3481 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3482 (gt:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 3483 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
3484 ""
3485 "slt\\t%0,%z2,%1"
3486 [(set_attr "type" "arith")
3487 (set_attr "mode" "SI")
3488 (set_attr "length" "1")])
3489
3490(define_expand "sge"
3491 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3492 (ge:SI (match_dup 1)
8ef30996
MM		 3493 (match_dup 2)))]
3494 ""
3495 "
3496{
3497 if (branch_type != CMP_SI)
3498 FAIL;
3499
3500 /* set up operands from compare. */
3501 operands[1] = branch_cmp[0];
3502 operands[2] = branch_cmp[1];
3503
bbdb5552 3504 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3505 {
3506 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
3507 DONE;
3508 }
3509
8ef30996
MM		 3510 /* fall through and generate default code */
3511}")
3512
3513(define_insn "sge_si"
3514 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3515 (ge:SI (match_operand:SI 1 "register_operand" "d")
8ef30996 3516 (match_operand:SI 2 "arith_operand" "dI")))]
bbdb5552 3517 "TARGET_DEBUG_C_MODE"
8ef30996
MM		 3518 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
3519 [(set_attr "type" "arith")
3520 (set_attr "mode" "SI")
3521 (set_attr "length" "2")])
3522
3523(define_split
3524 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 3525 (ge:SI (match_operand:SI 1 "register_operand" "")
8ef30996 3526 (match_operand:SI 2 "arith_operand" "")))]
bbdb5552 3527 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 3528 [(set (match_dup 0)
34b650b3 3529 (lt:SI (match_dup 1)
8ef30996
MM		 3530 (match_dup 2)))
3531 (set (match_dup 0)
3532 (xor:SI (match_dup 0)
3533 (const_int 1)))]
3534 "")
3535
3536(define_expand "slt"
3537 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3538 (lt:SI (match_dup 1)
8ef30996
MM		 3539 (match_dup 2)))]
3540 ""
3541 "
3542{
3543 if (branch_type != CMP_SI)
3544 FAIL;
3545
3546 /* set up operands from compare. */
3547 operands[1] = branch_cmp[0];
3548 operands[2] = branch_cmp[1];
3549
bbdb5552 3550 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3551 {
3552 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
3553 DONE;
3554 }
3555
8ef30996
MM		 3556 /* fall through and generate default code */
3557}")
3558
3559(define_insn "slt_si"
3560 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3561 (lt:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 3562 (match_operand:SI 2 "arith_operand" "dI")))]
3563 ""
3564 "slt\\t%0,%1,%2"
3565 [(set_attr "type" "arith")
3566 (set_attr "mode" "SI")
3567 (set_attr "length" "1")])
3568
3569(define_expand "sle"
3570 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3571 (le:SI (match_dup 1)
8ef30996
MM		 3572 (match_dup 2)))]
3573 ""
3574 "
3575{
3576 extern rtx force_reg ();
3577
3578 if (branch_type != CMP_SI)
3579 FAIL;
3580
3581 /* set up operands from compare. */
3582 operands[1] = branch_cmp[0];
3583 operands[2] = branch_cmp[1];
3584
bbdb5552 3585 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3586 {
3587 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
3588 DONE;
3589 }
3590
8ef30996
MM		 3591 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
3592 operands[2] = force_reg (SImode, operands[2]);
3593
3594 /* fall through and generate default code */
3595}")
3596
34b650b3
MM		 3597(define_insn "sle_si_const"
3598 [(set (match_operand:SI 0 "register_operand" "=d")
3599 (le:SI (match_operand:SI 1 "register_operand" "d")
3600 (match_operand:SI 2 "small_int" "I")))]
3601 "INTVAL (operands[2]) < 32767"
3602 "*
3603{
3604 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
3605 return \"slt\\t%0,%1,%2\";
3606}"
3607 [(set_attr "type" "arith")
3608 (set_attr "mode" "SI")
3609 (set_attr "length" "1")])
3610
3611(define_insn "sle_si_reg"
3612 [(set (match_operand:SI 0 "register_operand" "=d")
3613 (le:SI (match_operand:SI 1 "register_operand" "d")
3614 (match_operand:SI 2 "register_operand" "d")))]
bbdb5552 3615 "TARGET_DEBUG_C_MODE"
34b650b3
MM		 3616 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
3617 [(set_attr "type" "arith")
3618 (set_attr "mode" "SI")
3619 (set_attr "length" "2")])
8ef30996
MM		 3620
3621(define_split
3622 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 3623 (le:SI (match_operand:SI 1 "register_operand" "")
8ef30996 3624 (match_operand:SI 2 "register_operand" "")))]
bbdb5552 3625 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 3626 [(set (match_dup 0)
34b650b3 3627 (lt:SI (match_dup 2)
8ef30996
MM		 3628 (match_dup 1)))
3629 (set (match_dup 0)
3630 (xor:SI (match_dup 0)
3631 (const_int 1)))]
3632 "")
3633
3634(define_expand "sgtu"
3635 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3636 (gtu:SI (match_dup 1)
8ef30996
MM		 3637 (match_dup 2)))]
3638 ""
3639 "
3640{
3641 extern rtx force_reg ();
3642
3643 if (branch_type != CMP_SI)
3644 FAIL;
3645
3646 /* set up operands from compare. */
3647 operands[1] = branch_cmp[0];
3648 operands[2] = branch_cmp[1];
3649
bbdb5552 3650 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3651 {
3652 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
3653 DONE;
3654 }
3655
8ef30996
MM		 3656 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3657 operands[2] = force_reg (SImode, operands[2]);
3658
3659 /* fall through and generate default code */
3660}")
3661
3662(define_insn "sgtu_si"
3663 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3664 (gtu:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 3665 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
3666 ""
3667 "sltu\\t%0,%z2,%1"
3668 [(set_attr "type" "arith")
3669 (set_attr "mode" "SI")
3670 (set_attr "length" "1")])
3671
3672(define_expand "sgeu"
3673 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3674 (geu:SI (match_dup 1)
8ef30996
MM		 3675 (match_dup 2)))]
3676 ""
3677 "
3678{
3679 if (branch_type != CMP_SI)
3680 FAIL;
3681
3682 /* set up operands from compare. */
3683 operands[1] = branch_cmp[0];
3684 operands[2] = branch_cmp[1];
3685
bbdb5552 3686 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3687 {
3688 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
3689 DONE;
3690 }
3691
8ef30996
MM		 3692 /* fall through and generate default code */
3693}")
3694
3695(define_insn "sgeu_si"
3696 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3697 (geu:SI (match_operand:SI 1 "register_operand" "d")
8ef30996 3698 (match_operand:SI 2 "arith_operand" "dI")))]
bbdb5552 3699 "TARGET_DEBUG_C_MODE"
8ef30996
MM		 3700 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
3701 [(set_attr "type" "arith")
3702 (set_attr "mode" "SI")
3703 (set_attr "length" "2")])
3704
3705(define_split
3706 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 3707 (geu:SI (match_operand:SI 1 "register_operand" "")
8ef30996 3708 (match_operand:SI 2 "arith_operand" "")))]
bbdb5552 3709 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 3710 [(set (match_dup 0)
34b650b3 3711 (ltu:SI (match_dup 1)
8ef30996
MM		 3712 (match_dup 2)))
3713 (set (match_dup 0)
3714 (xor:SI (match_dup 0)
3715 (const_int 1)))]
3716 "")
3717
3718(define_expand "sltu"
3719 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3720 (ltu:SI (match_dup 1)
8ef30996
MM		 3721 (match_dup 2)))]
3722 ""
3723 "
3724{
3725 if (branch_type != CMP_SI)
3726 FAIL;
3727
3728 /* set up operands from compare. */
3729 operands[1] = branch_cmp[0];
3730 operands[2] = branch_cmp[1];
3731
bbdb5552 3732 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3733 {
3734 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
3735 DONE;
3736 }
3737
8ef30996
MM		 3738 /* fall through and generate default code */
3739}")
3740
3741(define_insn "sltu_si"
3742 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3743 (ltu:SI (match_operand:SI 1 "register_operand" "d")
8ef30996
MM		 3744 (match_operand:SI 2 "arith_operand" "dI")))]
3745 ""
3746 "sltu\\t%0,%1,%2"
3747 [(set_attr "type" "arith")
3748 (set_attr "mode" "SI")
3749 (set_attr "length" "1")])
3750
3751(define_expand "sleu"
3752 [(set (match_operand:SI 0 "register_operand" "=d")
34b650b3 3753 (leu:SI (match_dup 1)
8ef30996
MM		 3754 (match_dup 2)))]
3755 ""
3756 "
3757{
3758 extern rtx force_reg ();
3759
3760 if (branch_type != CMP_SI)
3761 FAIL;
3762
3763 /* set up operands from compare. */
3764 operands[1] = branch_cmp[0];
3765 operands[2] = branch_cmp[1];
3766
bbdb5552 3767 if (!TARGET_DEBUG_C_MODE)
34b650b3
MM		 3768 {
3769 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
3770 DONE;
3771 }
3772
8ef30996
MM		 3773 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
3774 operands[2] = force_reg (SImode, operands[2]);
3775
3776 /* fall through and generate default code */
3777}")
3778
34b650b3
MM		 3779(define_insn "sleu_si_const"
3780 [(set (match_operand:SI 0 "register_operand" "=d")
3781 (leu:SI (match_operand:SI 1 "register_operand" "d")
3782 (match_operand:SI 2 "small_int" "I")))]
3783 "INTVAL (operands[2]) < 32767"
3784 "*
3785{
3786 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
3787 return \"sltu\\t%0,%1,%2\";
3788}"
3789 [(set_attr "type" "arith")
3790 (set_attr "mode" "SI")
3791 (set_attr "length" "1")])
3792
3793(define_insn "sleu_si_reg"
3794 [(set (match_operand:SI 0 "register_operand" "=d")
3795 (leu:SI (match_operand:SI 1 "register_operand" "d")
3796 (match_operand:SI 2 "register_operand" "d")))]
bbdb5552 3797 "TARGET_DEBUG_C_MODE"
34b650b3
MM		 3798 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
3799 [(set_attr "type" "arith")
3800 (set_attr "mode" "SI")
3801 (set_attr "length" "2")])
8ef30996
MM		 3802
3803(define_split
3804 [(set (match_operand:SI 0 "register_operand" "")
34b650b3 3805 (leu:SI (match_operand:SI 1 "register_operand" "")
8ef30996 3806 (match_operand:SI 2 "register_operand" "")))]
bbdb5552 3807 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
8ef30996 3808 [(set (match_dup 0)
34b650b3 3809 (ltu:SI (match_dup 2)
8ef30996
MM		 3810 (match_dup 1)))
3811 (set (match_dup 0)
3812 (xor:SI (match_dup 0)
3813 (const_int 1)))]
3814 "")
3815
34b650b3
MM		 3816\f
3817;;
3818;; ....................
3819;;
3820;; FLOATING POINT COMPARISONS
3821;;
3822;; ....................
3823
3824(define_insn "seq_df"
3825 [(set (reg:CC_FP 66)
3826 (eq:CC_FP (match_operand:DF 0 "register_operand" "f")
3827 (match_operand:DF 1 "register_operand" "f")))]
3828 ""
3829 "*
3830{
3831 rtx xoperands[10];
3832 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3833 xoperands[1] = operands[0];
3834 xoperands[2] = operands[1];
3835
3836 return mips_fill_delay_slot (\"c.eq.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3837}"
3838 [(set_attr "type" "fcmp")
3839 (set_attr "mode" "FPSW")
3840 (set_attr "length" "1")])
3841
3842(define_insn "sne_df"
3843 [(set (reg:CC_REV_FP 66)
3844 (ne:CC_REV_FP (match_operand:DF 0 "register_operand" "f")
3845 (match_operand:DF 1 "register_operand" "f")))]
3846 ""
3847 "*
3848{
3849 rtx xoperands[10];
3850 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3851 xoperands[1] = operands[0];
3852 xoperands[2] = operands[1];
3853
3854 return mips_fill_delay_slot (\"c.eq.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3855}"
3856 [(set_attr "type" "fcmp")
3857 (set_attr "mode" "FPSW")
3858 (set_attr "length" "1")])
3859
3860(define_insn "slt_df"
3861 [(set (reg:CC_FP 66)
3862 (lt:CC_FP (match_operand:DF 0 "register_operand" "f")
3863 (match_operand:DF 1 "register_operand" "f")))]
3864 ""
3865 "*
3866{
3867 rtx xoperands[10];
3868 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3869 xoperands[1] = operands[0];
3870 xoperands[2] = operands[1];
3871
3872 return mips_fill_delay_slot (\"c.lt.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3873}"
3874 [(set_attr "type" "fcmp")
3875 (set_attr "mode" "FPSW")
3876 (set_attr "length" "1")])
3877
3878(define_insn "sle_df"
3879 [(set (reg:CC_FP 66)
3880 (le:CC_FP (match_operand:DF 0 "register_operand" "f")
3881 (match_operand:DF 1 "register_operand" "f")))]
3882 ""
3883 "*
3884{
3885 rtx xoperands[10];
3886 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3887 xoperands[1] = operands[0];
3888 xoperands[2] = operands[1];
3889
3890 return mips_fill_delay_slot (\"c.le.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3891}"
3892 [(set_attr "type" "fcmp")
3893 (set_attr "mode" "FPSW")
3894 (set_attr "length" "1")])
3895
3896(define_insn "sgt_df"
3897 [(set (reg:CC_FP 66)
3898 (gt:CC_FP (match_operand:DF 0 "register_operand" "f")
3899 (match_operand:DF 1 "register_operand" "f")))]
3900 ""
3901 "*
3902{
3903 rtx xoperands[10];
3904 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3905 xoperands[1] = operands[0];
3906 xoperands[2] = operands[1];
3907
3908 return mips_fill_delay_slot (\"c.lt.d\\t%1,%0\", DELAY_FCMP, xoperands, insn);
3909}"
3910 [(set_attr "type" "fcmp")
3911 (set_attr "mode" "FPSW")
3912 (set_attr "length" "1")])
3913
3914(define_insn "sge_df"
3915 [(set (reg:CC_FP 66)
3916 (ge:CC_FP (match_operand:DF 0 "register_operand" "f")
3917 (match_operand:DF 1 "register_operand" "f")))]
3918 ""
3919 "*
3920{
3921 rtx xoperands[10];
3922 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3923 xoperands[1] = operands[0];
3924 xoperands[2] = operands[1];
3925
3926 return mips_fill_delay_slot (\"c.le.d\\t%1,%0\", DELAY_FCMP, xoperands, insn);
3927}"
3928 [(set_attr "type" "fcmp")
3929 (set_attr "mode" "FPSW")
3930 (set_attr "length" "1")])
3931
3932(define_insn "seq_sf"
3933 [(set (reg:CC_FP 66)
3934 (eq:CC_FP (match_operand:SF 0 "register_operand" "f")
3935 (match_operand:SF 1 "register_operand" "f")))]
3936 ""
3937 "*
3938{
3939 rtx xoperands[10];
3940 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3941 xoperands[1] = operands[0];
3942 xoperands[2] = operands[1];
3943
3944 return mips_fill_delay_slot (\"c.eq.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3945}"
3946 [(set_attr "type" "fcmp")
3947 (set_attr "mode" "FPSW")
3948 (set_attr "length" "1")])
3949
3950(define_insn "sne_sf"
3951 [(set (reg:CC_REV_FP 66)
3952 (ne:CC_REV_FP (match_operand:SF 0 "register_operand" "f")
3953 (match_operand:SF 1 "register_operand" "f")))]
3954 ""
3955 "*
3956{
3957 rtx xoperands[10];
3958 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3959 xoperands[1] = operands[0];
3960 xoperands[2] = operands[1];
3961
3962 return mips_fill_delay_slot (\"c.eq.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3963}"
3964 [(set_attr "type" "fcmp")
3965 (set_attr "mode" "FPSW")
3966 (set_attr "length" "1")])
3967
3968(define_insn "slt_sf"
3969 [(set (reg:CC_FP 66)
3970 (lt:CC_FP (match_operand:SF 0 "register_operand" "f")
3971 (match_operand:SF 1 "register_operand" "f")))]
3972 ""
3973 "*
3974{
3975 rtx xoperands[10];
3976 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3977 xoperands[1] = operands[0];
3978 xoperands[2] = operands[1];
3979
3980 return mips_fill_delay_slot (\"c.lt.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3981}"
3982 [(set_attr "type" "fcmp")
3983 (set_attr "mode" "FPSW")
3984 (set_attr "length" "1")])
3985
3986(define_insn "sle_sf"
3987 [(set (reg:CC_FP 66)
3988 (le:CC_FP (match_operand:SF 0 "register_operand" "f")
3989 (match_operand:SF 1 "register_operand" "f")))]
3990 ""
3991 "*
3992{
3993 rtx xoperands[10];
3994 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
3995 xoperands[1] = operands[0];
3996 xoperands[2] = operands[1];
3997
3998 return mips_fill_delay_slot (\"c.le.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
3999}"
4000 [(set_attr "type" "fcmp")
4001 (set_attr "mode" "FPSW")
4002 (set_attr "length" "1")])
4003
4004(define_insn "sgt_sf"
4005 [(set (reg:CC_FP 66)
4006 (gt:CC_FP (match_operand:SF 0 "register_operand" "f")
4007 (match_operand:SF 1 "register_operand" "f")))]
4008 ""
4009 "*
4010{
4011 rtx xoperands[10];
4012 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
4013 xoperands[1] = operands[0];
4014 xoperands[2] = operands[1];
4015
4016 return mips_fill_delay_slot (\"c.lt.s\\t%1,%0\", DELAY_FCMP, xoperands, insn);
4017}"
4018 [(set_attr "type" "fcmp")
4019 (set_attr "mode" "FPSW")
4020 (set_attr "length" "1")])
4021
4022(define_insn "sge_sf"
4023 [(set (reg:CC_FP 66)
4024 (ge:CC_FP (match_operand:SF 0 "register_operand" "f")
4025 (match_operand:SF 1 "register_operand" "f")))]
4026 ""
4027 "*
4028{
4029 rtx xoperands[10];
4030 xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
4031 xoperands[1] = operands[0];
4032 xoperands[2] = operands[1];
4033
4034 return mips_fill_delay_slot (\"c.le.s\\t%1,%0\", DELAY_FCMP, xoperands, insn);
4035}"
4036 [(set_attr "type" "fcmp")
4037 (set_attr "mode" "FPSW")
4038 (set_attr "length" "1")])
4039
8ef30996
MM		 4040\f
4041;;
4042;; ....................
4043;;
4044;; UNCONDITIONAL BRANCHES
4045;;
4046;; ....................
4047
4048;; Unconditional branches.
4049
4050(define_insn "jump"
4051 [(set (pc)
4052 (label_ref (match_operand 0 "" "")))]
4053 ""
4054 "*
4055{
4056 if (GET_CODE (operands[0]) == REG)
4057 return \"%*j\\t%0\";
4058 else
4059 return \"%*j\\t%l0\";
4060}"
4061 [(set_attr "type" "jump")
4062 (set_attr "mode" "none")
4063 (set_attr "length" "1")])
4064
4065(define_insn "indirect_jump"
4066 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
4067 ""
4068 "%*j\\t%0"
4069 [(set_attr "type" "jump")
4070 (set_attr "mode" "none")
4071 (set_attr "length" "1")])
4072
4073(define_insn "tablejump"
4074 [(set (pc)
4075 (match_operand:SI 0 "register_operand" "d"))
4076 (use (label_ref (match_operand 1 "" "")))]
4077 ""
4078 "%*j\\t%0"
4079 [(set_attr "type" "jump")
4080 (set_attr "mode" "none")
4081 (set_attr "length" "1")])
4082
4083;; Function return, only allow after optimization, so that we can
4084;; eliminate jumps to jumps if no stack space is used.
4085
4086(define_insn "return"
4087 [(return)]
4088 "null_epilogue ()"
4089 "*
4090{
4091 operands[0] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4092 return \"%*j\\t%0\";
4093}"
4094 [(set_attr "type" "jump")
4095 (set_attr "mode" "none")
4096 (set_attr "length" "1")])
4097
4098\f
4099;;
4100;; ....................
4101;;
4102;; FUNCTION CALLS
4103;;
4104;; ....................
4105
4106;; calls.c now passes a third argument, make saber happy
4107
4108(define_expand "call"
af4a697f 4109 [(parallel [(call (match_operand 0 "memory_operand" "m")
8ef30996
MM		 4110 (match_operand 1 "" "i"))
4111 (clobber (match_operand 2 "" ""))])] ;; overwrite op2 with $31
4112 ""
4113 "
4114{
4115 rtx addr;
4116
4117 operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4118
4119 addr = XEXP (operands[0], 0);
af4a697f 4120 if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
8ef30996
MM		 4121 XEXP (operands[0], 0) = force_reg (FUNCTION_MODE, addr);
4122}")
4123
4124(define_insn "call_internal"
af4a697f 4125 [(call (match_operand 0 "memory_operand" "m")
8ef30996
MM		 4126 (match_operand 1 "" "i"))
4127 (clobber (match_operand:SI 2 "register_operand" "=d"))]
4128 ""
4129 "*
4130{
4131 register rtx target = XEXP (operands[0], 0);
4132
4133 if (GET_CODE (target) == SYMBOL_REF)
4134 return \"%*jal\\t%0\";
4135
4136 else
4137 {
4138 operands[0] = target;
4139 operands[1] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4140 return \"%*jal\\t%1,%0\";
4141 }
4142}"
4143 [(set_attr "type" "call")
4144 (set_attr "mode" "none")
4145 (set_attr "length" "1")])
4146
4147;; calls.c now passes a fourth argument, make saber happy
4148
4149(define_expand "call_value"
4150 [(parallel [(set (match_operand 0 "register_operand" "=df")
af4a697f 4151 (call (match_operand 1 "memory_operand" "m")
8ef30996
MM		 4152 (match_operand 2 "" "i")))
4153 (clobber (match_operand 3 "" ""))])] ;; overwrite op3 with $31
4154 ""
4155 "
4156{
4157 rtx addr;
4158
4159 operands[3] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4160
4161 addr = XEXP (operands[1], 0);
af4a697f 4162 if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
8ef30996
MM		 4163 XEXP (operands[1], 0) = force_reg (FUNCTION_MODE, addr);
4164}")
4165
4166(define_insn "call_value_internal"
4167 [(set (match_operand 0 "register_operand" "=df")
af4a697f 4168 (call (match_operand 1 "memory_operand" "m")
8ef30996
MM		 4169 (match_operand 2 "" "i")))
4170 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4171 ""
4172 "*
4173{
4174 register rtx target = XEXP (operands[1], 0);
4175
4176 if (GET_CODE (target) == SYMBOL_REF)
4177 return \"%*jal\\t%1\";
4178
4179 else
4180 {
4181 operands[1] = target;
4182 operands[2] = gen_rtx (REG, SImode, GP_REG_FIRST + 31);
4183 return \"%*jal\\t%2,%1\";
4184 }
4185}"
4186 [(set_attr "type" "call")
4187 (set_attr "mode" "none")
4188 (set_attr "length" "1")])
4189
4190\f
4191;;
4192;; ....................
4193;;
4194;; MISC.
4195;;
4196;; ....................
4197;;
4198
4199(define_insn "nop"
4200 [(const_int 0)]
4201 ""
4202 "%(nop%)"
4203 [(set_attr "type" "nop")
4204 (set_attr "mode" "none")
4205 (set_attr "length" "1")])
4206
4207(define_expand "probe"
4208 [(set (match_dup 0)
4209 (match_dup 1))]
4210 ""
4211 "
4212{
4213 operands[0] = gen_reg_rtx (SImode);
4214 operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx);
4215 MEM_VOLATILE_P (operands[1]) = TRUE;
4216
4217 /* fall through and generate default code */
4218}")
4219
4220\f
4221;;
4222;; Local variables:
4223;; mode:emacs-lisp
4224;; comment-start: ";; "
4225;; eval: (set-syntax-table (copy-sequence (syntax-table)))
4226;; eval: (modify-syntax-entry ?[ "(]")
4227;; eval: (modify-syntax-entry ?] ")[")
4228;; eval: (modify-syntax-entry ?{ "(}")
4229;; eval: (modify-syntax-entry ?} "){")
4230;; End:
GNU Compiler Collection
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