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e75b25e7 1/* Definitions of target machine for GNU compiler. MIPS version.
214be03f 2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
2d2a50c3 3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
ae3e1bb4
RK		 4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
e75b25e7
MM		 8
9This file is part of GNU CC.
10
11GNU CC is free software; you can redistribute it and/or modify
12it under the terms of the GNU General Public License as published by
13the Free Software Foundation; either version 2, or (at your option)
14any later version.
15
16GNU CC is distributed in the hope that it will be useful,
17but WITHOUT ANY WARRANTY; without even the implied warranty of
18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19GNU General Public License for more details.
20
21You should have received a copy of the GNU General Public License
22along with GNU CC; see the file COPYING. If not, write to
75fe0c5e
RK		 23the Free Software Foundation, 59 Temple Place - Suite 330,
24Boston, MA 02111-1307, USA. */
e75b25e7
MM		 25
26
e75b25e7
MM		 27/* Standard GCC variables that we reference. */
28
0fb5ac6f 29extern char call_used_regs[];
0fb5ac6f 30extern int may_call_alloca;
0fb5ac6f
MM		 31extern char **save_argv;
32extern int target_flags;
e75b25e7
MM		 33
34/* MIPS external variables defined in mips.c. */
35
36/* comparison type */
37enum cmp_type {
876c09d3
JW		 38 CMP_SI, /* compare four byte integers */
39 CMP_DI, /* compare eight byte integers */
e75b25e7
MM		 40 CMP_SF, /* compare single precision floats */
41 CMP_DF, /* compare double precision floats */
42 CMP_MAX /* max comparison type */
43};
44
e75b25e7
MM		 45/* Which processor to schedule for. Since there is no difference between
46 a R2000 and R3000 in terms of the scheduler, we collapse them into
4a392643
RS		 47 just an R3000. The elements of the enumeration must match exactly
48 the cpu attribute in the mips.md machine description. */
e75b25e7
MM		 49
50enum processor_type {
51 PROCESSOR_DEFAULT,
fcc11c35
CD		 52 PROCESSOR_4KC,
53 PROCESSOR_5KC,
54 PROCESSOR_20KC,
55 PROCESSOR_M4K,
e75b25e7 56 PROCESSOR_R3000,
e9a25f70 57 PROCESSOR_R3900,
e75b25e7 58 PROCESSOR_R6000,
876c09d3 59 PROCESSOR_R4000,
00b3e052 60 PROCESSOR_R4100,
5ce6f47b 61 PROCESSOR_R4111,
3f7967e3 62 PROCESSOR_R4120,
00b3e052 63 PROCESSOR_R4300,
516a2dfd 64 PROCESSOR_R4600,
053665d7 65 PROCESSOR_R4650,
b8eb88d0 66 PROCESSOR_R5000,
5ce6f47b
EC		 67 PROCESSOR_R5400,
68 PROCESSOR_R5500,
0e5a4ad8 69 PROCESSOR_R8000,
fcc11c35
CD		 70 PROCESSOR_SB1,
71 PROCESSOR_SR71000
e75b25e7
MM		 72};
73
4a392643 74/* Recast the cpu class to be the cpu attribute. */
919b1aec 75#define mips_cpu_attr ((enum attr_cpu)mips_tune)
4a392643 76
ac8ab9fe
RS		 77/* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
78 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
79 to work on a 64 bit machine. */
b2d8cf33 80
04bd620d
JW		 81#define ABI_32 0
82#define ABI_N32 1
83#define ABI_64 2
84#define ABI_EABI 3
a53f72db 85#define ABI_O64 4
0e5a4ad8 86
45ceb85d
RS		 87/* Whether to emit abicalls code sequences or not. */
88
89enum mips_abicalls_type {
90 MIPS_ABICALLS_NO,
91 MIPS_ABICALLS_YES
92};
93
94/* Recast the abicalls class to be the abicalls attribute. */
95#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
96
05713b80 97/* Information about one recognized processor. Defined here for the
a27fb29b
RS		 98 benefit of TARGET_CPU_CPP_BUILTINS. */
99struct mips_cpu_info {
100 /* The 'canonical' name of the processor as far as GCC is concerned.
101 It's typically a manufacturer's prefix followed by a numerical
102 designation. It should be lower case. */
103 const char *name;
104
105 /* The internal processor number that most closely matches this
106 entry. Several processors can have the same value, if there's no
107 difference between them from GCC's point of view. */
108 enum processor_type cpu;
109
110 /* The ISA level that the processor implements. */
111 int isa;
112};
113
987ba558 114extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
f540a7d3 115extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
e2fe6aba 116extern const char *current_function_file; /* filename current function is in */
e75b25e7
MM		 117extern int num_source_filenames; /* current .file # */
118extern int inside_function; /* != 0 if inside of a function */
119extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
120extern int file_in_function_warning; /* warning given about .file in func */
121extern int sdb_label_count; /* block start/end next label # */
a642a781 122extern int sdb_begin_function_line; /* Starting Line of current function */
e75b25e7 123extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
e75b25e7
MM		 124extern int sym_lineno; /* sgi next label # for each stmt */
125extern int set_noreorder; /* # of nested .set noreorder's */
126extern int set_nomacro; /* # of nested .set nomacro's */
127extern int set_noat; /* # of nested .set noat's */
128extern int set_volatile; /* # of nested .set volatile's */
e75b25e7
MM		 129extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
130extern int mips_dbx_regno[]; /* Map register # to debug register # */
e2500fed 131extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
e75b25e7 132extern enum cmp_type branch_type; /* what type of branch to use */
7dac2f89
EC		 133extern enum processor_type mips_arch; /* which cpu to codegen for */
134extern enum processor_type mips_tune; /* which cpu to schedule for */
45ceb85d 135extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
e75b25e7 136extern int mips_isa; /* architectural level */
2bcb2ab3
GK		 137extern int mips16; /* whether generating mips16 code */
138extern int mips16_hard_float; /* mips16 without -msoft-float */
139extern int mips_entry; /* generate entry/exit for mips16 */
7dac2f89
EC		 140extern const char *mips_arch_string; /* for -march=<xxx> */
141extern const char *mips_tune_string; /* for -mtune=<xxx> */
e2fe6aba
KG		 142extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
143extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
144extern const char *mips_entry_string; /* for -mentry */
145extern const char *mips_no_mips16_string;/* for -mno-mips16 */
d490e8ad 146extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
2bcb2ab3 147extern int mips_string_length; /* length of strings for mips16 */
a27fb29b
RS		 148extern const struct mips_cpu_info mips_cpu_info_table[];
149extern const struct mips_cpu_info *mips_arch_info;
150extern const struct mips_cpu_info *mips_tune_info;
e75b25e7 151
0fb5ac6f 152/* Functions to change what output section we are using. */
bd9f1972 153extern void sdata_section PARAMS ((void));
cc8f5ec0 154extern void sbss_section PARAMS ((void));
e75b25e7 155
3a6ee9f4
MM		 156/* Macros to silence warnings about numbers being signed in traditional
157 C and unsigned in ISO C when compiled on 32-bit hosts. */
158
159#define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
160#define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
161#define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
162
149e4e00
MM		 163\f
164/* Run-time compilation parameters selecting different hardware subsets. */
165
166/* Macros used in the machine description to test the flags. */
167
168 /* Bits for real switches */
6d81ba45
CD		 169#define MASK_INT64 0x00000001 /* ints are 64 bits */
170#define MASK_LONG64 0x00000002 /* longs are 64 bits */
171#define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
172#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
173#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
174#define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
f29d1b66 175#define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
6d81ba45
CD		 176#define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
177#define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
178#define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
179#define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
33005162 180#define MASK_UNUSED1 0x00000800 /* Unused Mask. */
6d81ba45
CD		 181#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
182#define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
183#define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
365c6a0b 184#define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
6d81ba45
CD		 185#define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
186#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
187#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
188#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
7dac2f89 189#define MASK_MIPS16 0x00100000 /* Generate mips16 code */
6d81ba45 190#define MASK_NO_CHECK_ZERO_DIV \
7dac2f89 191 0x00200000 /* divide by zero checking */
32ad6a47
RS		 192#define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
193 instructions. */
6d81ba45 194#define MASK_UNINIT_CONST_IN_RODATA \
7dac2f89 195 0x00800000 /* Store uninitialized
6d81ba45 196 consts in rodata */
13fac94a
GK		 197#define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
198 multiply-add operations. */
149e4e00
MM		 199
200 /* Debug switches, not documented */
6d81ba45
CD		 201#define MASK_DEBUG 0 /* unused */
202#define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
203#define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
987ba558 204#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
08c2951c 205#define MASK_DEBUG_D 0 /* don't do define_split's */
e4f5c5d6 206#define MASK_DEBUG_E 0 /* function_arg debug */
6d81ba45 207#define MASK_DEBUG_F 0 /* ??? */
2bcb2ab3 208#define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
e4f5c5d6 209#define MASK_DEBUG_I 0 /* unused */
149e4e00 210
6d81ba45
CD		 211 /* Dummy switches used only in specs */
212#define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
213
149e4e00
MM		 214 /* r4000 64 bit sizes */
215#define TARGET_INT64 (target_flags & MASK_INT64)
216#define TARGET_LONG64 (target_flags & MASK_LONG64)
149e4e00 217#define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
876c09d3 218#define TARGET_64BIT (target_flags & MASK_64BIT)
149e4e00 219
5ef37cd3
JW		 220 /* Mips vs. GNU linker */
221#define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
222
149e4e00
MM		 223 /* Mips vs. GNU assembler */
224#define TARGET_GAS (target_flags & MASK_GAS)
6d81ba45 225#define TARGET_MIPS_AS (!TARGET_GAS)
149e4e00 226
6d81ba45 227 /* Debug Modes */
149e4e00
MM		 228#define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
229#define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
230#define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
231#define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
232#define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
233#define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
234#define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
235#define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
149e4e00 236#define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
149e4e00
MM		 237
238 /* Reg. Naming in .s ($21 vs. $a0) */
239#define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
240
241 /* Optimize for Sdata/Sbss */
242#define TARGET_GP_OPT (target_flags & MASK_GPOPT)
243
149e4e00
MM		 244 /* call memcpy instead of inline code */
245#define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
246
247 /* .abicalls, etc from Pyramid V.4 */
248#define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
249
149e4e00
MM		 250 /* software floating point */
251#define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
252#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
253
254 /* always call through a register */
255#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
256
e0bfcea5
ILT		 257 /* generate embedded PIC code;
258 requires gas. */
259#define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
260
365c6a0b
JW		 261 /* for embedded systems, optimize for
262 reduced RAM space instead of for
263 fastest code. */
264#define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
265
919509ce
DN		 266 /* always store uninitialized const
267 variables in rodata, requires
987ba558 268 TARGET_EMBEDDED_DATA. */
919509ce
DN		 269#define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
270
96abdcb1
ILT		 271 /* generate big endian code. */
272#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
273
46299de9
ILT		 274#define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
275#define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
276
277#define TARGET_MAD (target_flags & MASK_MAD)
278
13fac94a
GK		 279#define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
280
00b3e052
JW		 281#define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
282
32ad6a47 283#define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
08c2951c 284
af34e51e
CD		 285#define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
286
cafe096b
EC		 287
288/* True if we should use NewABI-style relocation operators for
289 symbolic addresses. This is never true for mips16 code,
290 which has its own conventions. */
291
292#define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
293
294
cafe096b
EC		 295/* True if the call patterns should be split into a jalr followed by
296 an instruction to restore $gp. This is only ever true for SVR4 PIC,
297 in which $gp is call-clobbered. It is only safe to split the load
298 from the call when every use of $gp is explicit. */
299
300#define TARGET_SPLIT_CALLS \
301 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
302
303/* True if we can optimize sibling calls. For simplicity, we only
304 handle cases in which call_insn_operand will reject invalid
305 sibcall addresses. There are two cases in which this isn't true:
306
307 - TARGET_MIPS16. call_insn_operand accepts constant addresses
308 but there is no direct jump instruction. It isn't worth
309 using sibling calls in this case anyway; they would usually
310 be longer than normal calls.
311
312 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
313 accepts global constants, but "jr $25" is the only allowed
314 sibcall. */
315
316#define TARGET_SIBCALLS \
317 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
318
319/* True if .gpword or .gpdword should be used for switch tables.
320 Not all SGI assemblers support this. */
321
322#define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
323
2bcb2ab3
GK		 324 /* Generate mips16 code */
325#define TARGET_MIPS16 (target_flags & MASK_MIPS16)
326
ce3649d2
EC		 327/* Generic ISA defines. */
328#define ISA_MIPS1 (mips_isa == 1)
329#define ISA_MIPS2 (mips_isa == 2)
330#define ISA_MIPS3 (mips_isa == 3)
331#define ISA_MIPS4 (mips_isa == 4)
332#define ISA_MIPS32 (mips_isa == 32)
2d2a50c3 333#define ISA_MIPS32R2 (mips_isa == 33)
ce3649d2
EC		 334#define ISA_MIPS64 (mips_isa == 64)
335
7dac2f89
EC		 336/* Architecture target defines. */
337#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
338#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
3ccbe819 339#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
3f7967e3 340#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
7dac2f89 341#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
2d2a50c3
CD		 342#define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
343#define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
5ce6f47b
EC		 344#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
345#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
5b552f76 346#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
5ce6f47b 347#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
7dac2f89
EC		 348
349/* Scheduling target defines. */
7a38df19
EC		 350#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
351#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
352#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
353#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
5ce6f47b
EC		 354#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
355#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
7a38df19 356#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
5b552f76 357#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
5ce6f47b 358#define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
7dac2f89 359
cafe096b
EC		 360#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
361
a27fb29b
RS		 362/* Define preprocessor macros for the -march and -mtune options.
363 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
364 processor. If INFO's canonical name is "foo", define PREFIX to
365 be "foo", and define an additional macro PREFIX_FOO. */
366#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
367 do \
368 { \
369 char *macro, *p; \
370 \
371 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
372 for (p = macro; *p != 0; p++) \
373 *p = TOUPPER (*p); \
374 \
375 builtin_define (macro); \
376 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
377 free (macro); \
378 } \
379 while (0)
380
ce3649d2
EC		 381/* Target CPU builtins. */
382#define TARGET_CPU_CPP_BUILTINS() \
383 do \
384 { \
385 builtin_assert ("cpu=mips"); \
386 builtin_define ("__mips__"); \
387 builtin_define ("_mips"); \
388 \
389 /* We do this here because __mips is defined below \
390 and so we can't use builtin_define_std. */ \
391 if (!flag_iso) \
392 builtin_define ("mips"); \
393 \
a27fb29b
RS		 394 /* Treat _R3000 and _R4000 like register-size defines, \
395 which is how they've historically been used. */ \
ce3649d2
EC		 396 if (TARGET_64BIT) \
397 { \
398 builtin_define ("__mips64"); \
ce3649d2
EC		 399 builtin_define_std ("R4000"); \
400 builtin_define ("_R4000"); \
401 } \
402 else \
403 { \
ce3649d2
EC		 404 builtin_define_std ("R3000"); \
405 builtin_define ("_R3000"); \
406 } \
407 if (TARGET_FLOAT64) \
408 builtin_define ("__mips_fpr=64"); \
409 else \
410 builtin_define ("__mips_fpr=32"); \
411 \
412 if (TARGET_MIPS16) \
413 builtin_define ("__mips16"); \
414 \
a27fb29b
RS		 415 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
416 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
417 \
ce3649d2
EC		 418 if (ISA_MIPS1) \
419 { \
420 builtin_define ("__mips=1"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
422 } \
423 else if (ISA_MIPS2) \
424 { \
425 builtin_define ("__mips=2"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
427 } \
428 else if (ISA_MIPS3) \
429 { \
430 builtin_define ("__mips=3"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
432 } \
433 else if (ISA_MIPS4) \
434 { \
435 builtin_define ("__mips=4"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
437 } \
438 else if (ISA_MIPS32) \
439 { \
440 builtin_define ("__mips=32"); \
2d2a50c3
CD		 441 builtin_define ("__mips_isa_rev=1"); \
442 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
443 } \
444 else if (ISA_MIPS32R2) \
445 { \
446 builtin_define ("__mips=32"); \
447 builtin_define ("__mips_isa_rev=2"); \
ce3649d2
EC		 448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
449 } \
450 else if (ISA_MIPS64) \
451 { \
452 builtin_define ("__mips=64"); \
2d2a50c3 453 builtin_define ("__mips_isa_rev=1"); \
ce3649d2
EC		 454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
455 } \
456 \
457 if (TARGET_HARD_FLOAT) \
458 builtin_define ("__mips_hard_float"); \
459 else if (TARGET_SOFT_FLOAT) \
460 builtin_define ("__mips_soft_float"); \
461 \
462 if (TARGET_SINGLE_FLOAT) \
463 builtin_define ("__mips_single_float"); \
464 \
ce3649d2
EC		 465 if (TARGET_BIG_ENDIAN) \
466 { \
467 builtin_define_std ("MIPSEB"); \
468 builtin_define ("_MIPSEB"); \
469 } \
470 else \
471 { \
472 builtin_define_std ("MIPSEL"); \
473 builtin_define ("_MIPSEL"); \
474 } \
475 \
476 /* Macros dependent on the C dialect. */ \
477 if (preprocessing_asm_p ()) \
478 { \
479 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
480 builtin_define ("_LANGUAGE_ASSEMBLY"); \
481 } \
482 else if (c_language == clk_c) \
483 { \
484 builtin_define_std ("LANGUAGE_C"); \
485 builtin_define ("_LANGUAGE_C"); \
486 } \
487 else if (c_language == clk_cplusplus) \
488 { \
489 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
490 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
491 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
492 } \
2516f236 493 if (flag_objc) \
ce3649d2
EC		 494 { \
495 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
496 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
497 /* Bizzare, but needed at least for Irix. */ \
498 builtin_define_std ("LANGUAGE_C"); \
499 builtin_define ("_LANGUAGE_C"); \
500 } \
501 \
502 if (mips_abi == ABI_EABI) \
503 builtin_define ("__mips_eabi"); \
504 \
505} while (0)
506
507
508
149e4e00
MM		 509/* Macro to define tables used to set the flags.
510 This is a list in braces of pairs in braces,
511 each pair being { "NAME", VALUE }
512 where VALUE is the bits to set or minus the bits to clear.
513 An empty string NAME is used to identify the default VALUE. */
514
515#define TARGET_SWITCHES \
516{ \
cafe096b 517 SUBTARGET_TARGET_SWITCHES \
a127db75 518 {"int64", MASK_INT64 | MASK_LONG64, \
047142d3 519 N_("Use 64-bit int type")}, \
a127db75 520 {"long64", MASK_LONG64, \
047142d3 521 N_("Use 64-bit long type")}, \
a127db75 522 {"long32", -(MASK_LONG64 | MASK_INT64), \
047142d3 523 N_("Use 32-bit long type")}, \
a127db75 524 {"split-addresses", MASK_SPLIT_ADDR, \
047142d3 525 N_("Optimize lui/addiu address loads")}, \
a127db75 526 {"no-split-addresses", -MASK_SPLIT_ADDR, \
047142d3 527 N_("Don't optimize lui/addiu address loads")}, \
a127db75 528 {"mips-as", -MASK_GAS, \
047142d3 529 N_("Use MIPS as")}, \
a127db75 530 {"gas", MASK_GAS, \
047142d3 531 N_("Use GNU as")}, \
a127db75 532 {"rnames", MASK_NAME_REGS, \
047142d3 533 N_("Use symbolic register names")}, \
a127db75 534 {"no-rnames", -MASK_NAME_REGS, \
047142d3 535 N_("Don't use symbolic register names")}, \
a127db75 536 {"gpOPT", MASK_GPOPT, \
047142d3 537 N_("Use GP relative sdata/sbss sections")}, \
a127db75 538 {"gpopt", MASK_GPOPT, \
047142d3 539 N_("Use GP relative sdata/sbss sections")}, \
a127db75 540 {"no-gpOPT", -MASK_GPOPT, \
047142d3 541 N_("Don't use GP relative sdata/sbss sections")}, \
a127db75 542 {"no-gpopt", -MASK_GPOPT, \
047142d3 543 N_("Don't use GP relative sdata/sbss sections")}, \
f29d1b66
RS		 544 {"stats", 0, \
545 N_("Output compiler statistics (now ignored)")}, \
546 {"no-stats", 0, \
047142d3 547 N_("Don't output compiler statistics")}, \
a127db75 548 {"memcpy", MASK_MEMCPY, \
047142d3 549 N_("Don't optimize block moves")}, \
a127db75 550 {"no-memcpy", -MASK_MEMCPY, \
047142d3 551 N_("Optimize block moves")}, \
a127db75 552 {"mips-tfile", MASK_MIPS_TFILE, \
047142d3 553 N_("Use mips-tfile asm postpass")}, \
a127db75 554 {"no-mips-tfile", -MASK_MIPS_TFILE, \
047142d3 555 N_("Don't use mips-tfile asm postpass")}, \
a127db75 556 {"soft-float", MASK_SOFT_FLOAT, \
047142d3 557 N_("Use software floating point")}, \
a127db75 558 {"hard-float", -MASK_SOFT_FLOAT, \
047142d3 559 N_("Use hardware floating point")}, \
a127db75 560 {"fp64", MASK_FLOAT64, \
047142d3 561 N_("Use 64-bit FP registers")}, \
a127db75 562 {"fp32", -MASK_FLOAT64, \
047142d3 563 N_("Use 32-bit FP registers")}, \
a127db75 564 {"gp64", MASK_64BIT, \
047142d3 565 N_("Use 64-bit general registers")}, \
a127db75 566 {"gp32", -MASK_64BIT, \
047142d3 567 N_("Use 32-bit general registers")}, \
a127db75 568 {"abicalls", MASK_ABICALLS, \
047142d3 569 N_("Use Irix PIC")}, \
a127db75 570 {"no-abicalls", -MASK_ABICALLS, \
047142d3 571 N_("Don't use Irix PIC")}, \
a127db75 572 {"long-calls", MASK_LONG_CALLS, \
047142d3 573 N_("Use indirect calls")}, \
a127db75 574 {"no-long-calls", -MASK_LONG_CALLS, \
047142d3 575 N_("Don't use indirect calls")}, \
a127db75 576 {"embedded-pic", MASK_EMBEDDED_PIC, \
047142d3 577 N_("Use embedded PIC")}, \
a127db75 578 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
047142d3 579 N_("Don't use embedded PIC")}, \
a127db75 580 {"embedded-data", MASK_EMBEDDED_DATA, \
047142d3 581 N_("Use ROM instead of RAM")}, \
a127db75 582 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
047142d3 583 N_("Don't use ROM instead of RAM")}, \
919509ce 584 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
047142d3 585 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
919509ce 586 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
047142d3 587 N_("Don't put uninitialized constants in ROM")}, \
a127db75 588 {"eb", MASK_BIG_ENDIAN, \
047142d3 589 N_("Use big-endian byte order")}, \
a127db75 590 {"el", -MASK_BIG_ENDIAN, \
047142d3 591 N_("Use little-endian byte order")}, \
a127db75 592 {"single-float", MASK_SINGLE_FLOAT, \
047142d3 593 N_("Use single (32-bit) FP only")}, \
a127db75 594 {"double-float", -MASK_SINGLE_FLOAT, \
047142d3 595 N_("Don't use single (32-bit) FP only")}, \
a127db75 596 {"mad", MASK_MAD, \
047142d3 597 N_("Use multiply accumulate")}, \
a127db75 598 {"no-mad", -MASK_MAD, \
047142d3 599 N_("Don't use multiply accumulate")}, \
13fac94a
GK		 600 {"no-fused-madd", MASK_NO_FUSED_MADD, \
601 N_("Don't generate fused multiply/add instructions")}, \
602 {"fused-madd", -MASK_NO_FUSED_MADD, \
603 N_("Generate fused multiply/add instructions")}, \
a127db75 604 {"fix4300", MASK_4300_MUL_FIX, \
047142d3 605 N_("Work around early 4300 hardware bug")}, \
a127db75 606 {"no-fix4300", -MASK_4300_MUL_FIX, \
047142d3 607 N_("Don't work around early 4300 hardware bug")}, \
a127db75 608 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
047142d3 609 N_("Trap on integer divide by zero")}, \
a127db75 610 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
047142d3 611 N_("Don't trap on integer divide by zero")}, \
af34e51e
CD		 612 { "branch-likely", MASK_BRANCHLIKELY, \
613 N_("Use Branch Likely instructions, overriding default for arch")}, \
614 { "no-branch-likely", -MASK_BRANCHLIKELY, \
615 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
cafe096b
EC		 616 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
617 N_("Use NewABI-style %reloc() assembly operators")}, \
618 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
619 N_("Use assembler macros instead of relocation operators")}, \
a127db75
JW		 620 {"debug", MASK_DEBUG, \
621 NULL}, \
622 {"debuga", MASK_DEBUG_A, \
623 NULL}, \
624 {"debugb", MASK_DEBUG_B, \
625 NULL}, \
626 {"debugc", MASK_DEBUG_C, \
627 NULL}, \
628 {"debugd", MASK_DEBUG_D, \
629 NULL}, \
630 {"debuge", MASK_DEBUG_E, \
631 NULL}, \
632 {"debugf", MASK_DEBUG_F, \
633 NULL}, \
634 {"debugg", MASK_DEBUG_G, \
635 NULL}, \
a127db75
JW		 636 {"debugi", MASK_DEBUG_I, \
637 NULL}, \
96abdcb1
ILT		 638 {"", (TARGET_DEFAULT \
639 | TARGET_CPU_DEFAULT \
a127db75
JW		 640 | TARGET_ENDIAN_DEFAULT), \
641 NULL}, \
7dac2f89 642}
149e4e00
MM		 643
644/* Default target_flags if no switches are specified */
645
646#ifndef TARGET_DEFAULT
647#define TARGET_DEFAULT 0
648#endif
649
404f986e
MM		 650#ifndef TARGET_CPU_DEFAULT
651#define TARGET_CPU_DEFAULT 0
652#endif
653
96abdcb1 654#ifndef TARGET_ENDIAN_DEFAULT
96abdcb1 655#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
96abdcb1
ILT		 656#endif
657
a27fb29b 658/* 'from-abi' makes a good default: you get whatever the ABI requires. */
ea09f032 659#ifndef MIPS_ISA_DEFAULT
a27fb29b
RS		 660#ifndef MIPS_CPU_STRING_DEFAULT
661#define MIPS_CPU_STRING_DEFAULT "from-abi"
662#endif
ea09f032
GRK		 663#endif
664
996ed075
JJ		 665#ifdef IN_LIBGCC2
666#undef TARGET_64BIT
667/* Make this compile time constant for libgcc2 */
668#ifdef __mips64
669#define TARGET_64BIT 1
670#else
671#define TARGET_64BIT 0
672#endif
440927ec 673#endif /* IN_LIBGCC2 */
996ed075 674
cbab8d02 675#ifndef MULTILIB_ENDIAN_DEFAULT
7f2e00db 676#if TARGET_ENDIAN_DEFAULT == 0
cbab8d02 677#define MULTILIB_ENDIAN_DEFAULT "EL"
7f2e00db 678#else
cbab8d02
GRK		 679#define MULTILIB_ENDIAN_DEFAULT "EB"
680#endif
7f2e00db 681#endif
cbab8d02 682
ea09f032 683#ifndef MULTILIB_ISA_DEFAULT
7ce2fcb9
KG		 684# if MIPS_ISA_DEFAULT == 1
685# define MULTILIB_ISA_DEFAULT "mips1"
686# else
687# if MIPS_ISA_DEFAULT == 2
688# define MULTILIB_ISA_DEFAULT "mips2"
689# else
690# if MIPS_ISA_DEFAULT == 3
691# define MULTILIB_ISA_DEFAULT "mips3"
692# else
693# if MIPS_ISA_DEFAULT == 4
694# define MULTILIB_ISA_DEFAULT "mips4"
695# else
0e5a4ad8
EC		 696# if MIPS_ISA_DEFAULT == 32
697# define MULTILIB_ISA_DEFAULT "mips32"
698# else
2d2a50c3
CD		 699# if MIPS_ISA_DEFAULT == 33
700# define MULTILIB_ISA_DEFAULT "mips32r2"
0e5a4ad8 701# else
2d2a50c3
CD		 702# if MIPS_ISA_DEFAULT == 64
703# define MULTILIB_ISA_DEFAULT "mips64"
704# else
705# define MULTILIB_ISA_DEFAULT "mips1"
706# endif
707# endif
708# endif
7ce2fcb9
KG		 709# endif
710# endif
711# endif
712# endif
ea09f032
GRK		 713#endif
714
cbab8d02 715#ifndef MULTILIB_DEFAULTS
a27fb29b
RS		 716#define MULTILIB_DEFAULTS \
717 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
7f2e00db
RK		 718#endif
719
34bcd7fd
JW		 720/* We must pass -EL to the linker by default for little endian embedded
721 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
722 linker will default to using big-endian output files. The OUTPUT_FORMAT
723 line must be in the linker script, otherwise -EB/-EL will not work. */
724
120dc6cd 725#ifndef ENDIAN_SPEC
34bcd7fd 726#if TARGET_ENDIAN_DEFAULT == 0
ac282977 727#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
34bcd7fd 728#else
ac282977 729#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
34bcd7fd
JW		 730#endif
731#endif
732
149e4e00
MM		 733#define TARGET_OPTIONS \
734{ \
b2d8cf33 735 SUBTARGET_TARGET_OPTIONS \
8f2e3902 736 { "tune=", &mips_tune_string, \
c409ea0d 737 N_("Specify CPU for scheduling purposes"), 0}, \
7dac2f89 738 { "arch=", &mips_arch_string, \
c409ea0d 739 N_("Specify CPU for code generation purposes"), 0}, \
a27fb29b 740 { "abi=", &mips_abi_string, \
c409ea0d 741 N_("Specify an ABI"), 0}, \
a127db75 742 { "ips", &mips_isa_string, \
c409ea0d 743 N_("Specify a Standard MIPS ISA"), 0}, \
a127db75 744 { "entry", &mips_entry_string, \
c409ea0d 745 N_("Use mips16 entry/exit psuedo ops"), 0}, \
a127db75 746 { "no-mips16", &mips_no_mips16_string, \
c409ea0d 747 N_("Don't use MIPS16 instructions"), 0}, \
d490e8ad 748 { "no-flush-func", &mips_cache_flush_func, \
c409ea0d 749 N_("Don't call any cache flush functions"), 0}, \
d490e8ad 750 { "flush-func=", &mips_cache_flush_func, \
c409ea0d 751 N_("Specify cache flush function"), 0}, \
149e4e00
MM		 752}
753
b2d8cf33
JW		 754/* This is meant to be redefined in the host dependent files. */
755#define SUBTARGET_TARGET_OPTIONS
756
7816bea0
DJ		 757/* Support for a compile-time default CPU, et cetera. The rules are:
758 --with-arch is ignored if -march is specified or a -mips is specified
759 (other than -mips16).
760 --with-tune is ignored if -mtune is specified.
761 --with-abi is ignored if -mabi is specified.
762 --with-float is ignored if -mhard-float or -msoft-float are
763 specified. */
764#define OPTION_DEFAULT_SPECS \
765 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
766 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
767 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
768 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
769
770
5ce6f47b
EC		 771#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
772 && !TARGET_SR71K \
773 && !TARGET_MIPS16)
e4f5c5d6 774
0e5a4ad8
EC		 775/* Generate three-operand multiply instructions for SImode. */
776#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
5ce6f47b
EC		 777 || TARGET_MIPS5400 \
778 || TARGET_MIPS5500 \
ce3649d2 779 || ISA_MIPS32 \
2d2a50c3 780 || ISA_MIPS32R2 \
ce3649d2 781 || ISA_MIPS64) \
0e5a4ad8
EC		 782 && !TARGET_MIPS16)
783
784/* Generate three-operand multiply instructions for DImode. */
785#define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
786 && !TARGET_MIPS16)
e9a25f70 787
149e4e00
MM		 788/* Macros to decide whether certain features are available or not,
789 depending on the instruction set architecture level. */
790
ce3649d2 791#define HAVE_SQRT_P() (!ISA_MIPS1)
1d5d552e 792
a27fb29b
RS		 793/* True if the ABI can only work with 64-bit integer registers. We
794 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
795 otherwise floating-point registers must also be 64-bit. */
796#define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
797 || mips_abi == ABI_O64 \
798 || mips_abi == ABI_N32)
799
800/* Likewise for 32-bit regs. */
801#define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
802
cafe096b
EC		 803/* True if symbols are 64 bits wide. At present, n64 is the only
804 ABI for which this is true. */
805#define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
806
987ba558 807/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
8f2e3902
EC		 808#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
809 || ISA_MIPS4 \
ce3649d2 810 || ISA_MIPS64)
1d5d552e 811
987ba558 812/* ISA has branch likely instructions (eg. mips2). */
7dac2f89
EC		 813/* Disable branchlikely for tx39 until compare rewrite. They haven't
814 been generated up to this point. */
5ce6f47b
EC		 815#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
816 && !TARGET_MIPS5500)
1d5d552e 817
987ba558 818/* ISA has the conditional move instructions introduced in mips4. */
ce3649d2
EC		 819#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
820 || ISA_MIPS32 \
2d2a50c3 821 || ISA_MIPS32R2 \
ce3649d2 822 || ISA_MIPS64) \
5ce6f47b 823 && !TARGET_MIPS5500 \
ce3649d2 824 && !TARGET_MIPS16)
76ee8042 825
0025b7fa
GRK		 826/* ISA has just the integer condition move instructions (movn,movz) */
827#define ISA_HAS_INT_CONDMOVE 0
828
76ee8042 829/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
987ba558 830 branch on CC, and move (both FP and non-FP) on CC. */
ce3649d2
EC		 831#define ISA_HAS_8CC (ISA_MIPS4 \
832 || ISA_MIPS32 \
2d2a50c3 833 || ISA_MIPS32R2 \
ce3649d2 834 || ISA_MIPS64)
76ee8042 835
76ee8042 836/* This is a catch all for the other new mips4 instructions: indexed load and
8fff5435
CD		 837 indexed prefetch instructions, the FP madd and msub instructions,
838 and the FP recip and recip sqrt instructions */
12bf26b6
EC		 839#define ISA_HAS_FP4 ((ISA_MIPS4 \
840 || ISA_MIPS64) \
ce3649d2 841 && !TARGET_MIPS16)
76ee8042 842
a0b6cdee 843/* ISA has conditional trap instructions. */
ce3649d2
EC		 844#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
845 && !TARGET_MIPS16)
1d5d552e 846
12bf26b6 847/* ISA has integer multiply-accumulate instructions, madd and msub. */
ce3649d2 848#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
2d2a50c3 849 || ISA_MIPS32R2 \
ce3649d2
EC		 850 || ISA_MIPS64 \
851 ) && !TARGET_MIPS16)
0e5a4ad8 852
12bf26b6
EC		 853/* ISA has floating-point nmadd and nmsub instructions. */
854#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
855 || ISA_MIPS64) \
5ce6f47b 856 && (!TARGET_MIPS5400 || TARGET_MAD) \
974a3101 857 && ! TARGET_MIPS16)
149e4e00 858
0e5a4ad8 859/* ISA has count leading zeroes/ones instruction (not implemented). */
ce3649d2 860#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
2d2a50c3 861 || ISA_MIPS32R2 \
ce3649d2
EC		 862 || ISA_MIPS64 \
863 ) && !TARGET_MIPS16)
0e5a4ad8
EC		 864
865/* ISA has double-word count leading zeroes/ones instruction (not
866 implemented). */
ce3649d2
EC		 867#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
868 && !TARGET_MIPS16)
0e5a4ad8 869
5ce6f47b
EC		 870/* ISA has three operand multiply instructions that put
871 the high part in an accumulator: mulhi or mulhiu. */
872#define ISA_HAS_MULHI (TARGET_MIPS5400 \
873 || TARGET_MIPS5500 \
874 || TARGET_SR71K \
875 )
876
877/* ISA has three operand multiply instructions that
878 negates the result and puts the result in an accumulator. */
879#define ISA_HAS_MULS (TARGET_MIPS5400 \
880 || TARGET_MIPS5500 \
881 || TARGET_SR71K \
882 )
883
884/* ISA has three operand multiply instructions that subtracts the
885 result from a 4th operand and puts the result in an accumulator. */
886#define ISA_HAS_MSAC (TARGET_MIPS5400 \
887 || TARGET_MIPS5500 \
888 || TARGET_SR71K \
889 )
890/* ISA has three operand multiply instructions that the result
891 from a 4th operand and puts the result in an accumulator. */
cafe096b
EC		 892#define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
893 || TARGET_MIPS5400 \
5ce6f47b
EC		 894 || TARGET_MIPS5500 \
895 || TARGET_SR71K \
896 )
897
898/* ISA has 32-bit rotate right instruction. */
2d2a50c3
CD		 899#define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
900 && (ISA_MIPS32R2 \
901 || TARGET_MIPS5400 \
902 || TARGET_MIPS5500 \
903 || TARGET_SR71K \
904 ))
5ce6f47b 905
2d2a50c3 906/* ISA has 64-bit rotate right instruction. */
5ce6f47b 907#define ISA_HAS_ROTR_DI (TARGET_64BIT \
2d2a50c3 908 && !TARGET_MIPS16 \
5ce6f47b
EC		 909 && (TARGET_MIPS5400 \
910 || TARGET_MIPS5500 \
911 || TARGET_SR71K \
912 ))
913
8f2e3902
EC		 914/* ISA has data prefetch instruction. */
915#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
916 || ISA_MIPS32 \
2d2a50c3 917 || ISA_MIPS32R2 \
8f2e3902
EC		 918 || ISA_MIPS64) \
919 && !TARGET_MIPS16)
920
8214bf98
RS		 921/* True if trunc.w.s and trunc.w.d are real (not synthetic)
922 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
923 also requires TARGET_DOUBLE_FLOAT. */
924#define ISA_HAS_TRUNC_W (!ISA_MIPS1)
925
2d2a50c3
CD		 926/* ISA includes the MIPS32r2 seb and seh instructions. */
927#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
928 && (ISA_MIPS32R2 \
929 ))
930
21c9500d
RS		 931/* True if the result of a load is not available to the next instruction.
932 A nop will then be needed between instructions like "lw $4,..."
933 and "addiu $4,$4,1". */
934#define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
935 && !TARGET_MIPS3900 \
936 && !TARGET_MIPS16)
937
938/* Likewise mtc1 and mfc1. */
939#define ISA_HAS_XFER_DELAY (mips_isa <= 3)
940
941/* Likewise floating-point comparisons. */
942#define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
943
944/* True if mflo and mfhi can be immediately followed by instructions
945 which write to the HI and LO registers. Most targets require a
946 two-instruction gap. */
947#define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
948
516a2dfd
JW		 949/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
950 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
2370b831
JW		 951 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
952 target_flags, and -mgp64 sets MASK_64BIT.
876c09d3 953
2370b831
JW		 954 Setting MASK_64BIT in target_flags will cause gcc to assume that
955 registers are 64 bits wide. int, long and void * will be 32 bit;
956 this may be changed with -mint64 or -mlong64.
876c09d3 957
2370b831
JW		 958 The gen* programs link code that refers to MASK_64BIT. They don't
959 actually use the information in target_flags; they just refer to
960 it. */
e75b25e7
MM		 961\f
962/* Switch Recognition by gcc.c. Add -G xx support */
963
0e5a4ad8 964#undef SWITCH_TAKES_ARG
e75b25e7 965#define SWITCH_TAKES_ARG(CHAR) \
7d4ea832 966 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
e75b25e7
MM		 967
968/* Sometimes certain combinations of command options do not make sense
969 on a particular target machine. You can define a macro
970 `OVERRIDE_OPTIONS' to take account of this. This macro, if
971 defined, is executed once just after all the command options have
972 been parsed.
973
974 On the MIPS, it is used to handle -G. We also use it to set up all
975 of the tables referenced in the other macros. */
976
977#define OVERRIDE_OPTIONS override_options ()
978
ac8ab9fe 979#define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
516a2dfd 980
7be1e523
RK		 981/* Show we can debug even without a frame pointer. */
982#define CAN_DEBUG_WITHOUT_FP
983\f
59c94430
MM		 984/* Tell collect what flags to pass to nm. */
985#ifndef NM_FLAGS
2ce3c6c6 986#define NM_FLAGS "-Bn"
59c94430
MM		 987#endif
988
e75b25e7 989\f
4e88bbcd
ILT		 990/* Assembler specs. */
991
992/* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
993 than gas. */
994
995#define MIPS_AS_ASM_SPEC "\
996%{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
c725bd79 997%{pipe: %e-pipe is not supported} \
4e88bbcd
ILT		 998%{K} %(subtarget_mips_as_asm_spec)"
999
1000/* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1001 rather than gas. It may be overridden by subtargets. */
1002
1003#ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1004#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1005#endif
1006
1007/* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1008 assembler. */
1009
a27fb29b 1010#define GAS_ASM_SPEC "%{mtune=*} %{v}"
009da785 1011
3bd6d4c4 1012#define SUBTARGET_TARGET_SWITCHES
009da785 1013
009da785 1014extern int mips_abi;
0e5a4ad8
EC		 1015
1016#ifndef MIPS_ABI_DEFAULT
009da785
EC		 1017#define MIPS_ABI_DEFAULT ABI_32
1018#endif
0e5a4ad8 1019
a27fb29b
RS		 1020/* Use the most portable ABI flag for the ASM specs. */
1021
1022#if MIPS_ABI_DEFAULT == ABI_32
1023#define MULTILIB_ABI_DEFAULT "mabi=32"
1024#define ASM_ABI_DEFAULT_SPEC "-32"
1025#endif
1026
1027#if MIPS_ABI_DEFAULT == ABI_O64
1028#define MULTILIB_ABI_DEFAULT "mabi=o64"
1029#define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1030#endif
1031
1032#if MIPS_ABI_DEFAULT == ABI_N32
1033#define MULTILIB_ABI_DEFAULT "mabi=n32"
1034#define ASM_ABI_DEFAULT_SPEC "-n32"
1035#endif
1036
1037#if MIPS_ABI_DEFAULT == ABI_64
1038#define MULTILIB_ABI_DEFAULT "mabi=64"
1039#define ASM_ABI_DEFAULT_SPEC "-64"
1040#endif
1041
1042#if MIPS_ABI_DEFAULT == ABI_EABI
1043#define MULTILIB_ABI_DEFAULT "mabi=eabi"
1044#define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1045#endif
1046
a27fb29b
RS		 1047/* Only ELF targets can switch the ABI. */
1048#ifndef OBJECT_FORMAT_ELF
1049#undef ASM_ABI_DEFAULT_SPEC
1050#define ASM_ABI_DEFAULT_SPEC ""
0e5a4ad8 1051#endif
4e88bbcd
ILT		 1052
1053/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1054 GAS_ASM_SPEC as the default, depending upon the value of
1055 TARGET_DEFAULT. */
e75b25e7 1056
bb98bc58
JW		 1057#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1058/* GAS */
bb98bc58 1059
4e88bbcd
ILT		 1060#define TARGET_ASM_SPEC "\
1061%{mmips-as: %(mips_as_asm_spec)} \
1062%{!mmips-as: %(gas_asm_spec)}"
1063
1064#else /* not GAS */
1065
1066#define TARGET_ASM_SPEC "\
1067%{!mgas: %(mips_as_asm_spec)} \
1068%{mgas: %(gas_asm_spec)}"
1069
1070#endif /* not GAS */
1071
1072/* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1073 to the assembler. It may be overridden by subtargets. */
1074#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1075#define SUBTARGET_ASM_OPTIMIZING_SPEC "\
bb98bc58 1076%{noasmopt:-O0} \
4e88bbcd
ILT		 1077%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1078#endif
1079
1080/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1081 the assembler. It may be overridden by subtargets. */
1082#ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1083#define SUBTARGET_ASM_DEBUGGING_SPEC "\
bb98bc58
JW		 1084%{g} %{g0} %{g1} %{g2} %{g3} \
1085%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1086%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1087%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
6d439235 1088%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
3bd4f460 1089%(mdebug_asm_spec)"
4e88bbcd 1090#endif
bb98bc58 1091
3bd4f460
RO		 1092/* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1093 and stabs debugging info. */
1094#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1095/* GAS */
1096#define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1097#else /* not GAS */
1098#define MDEBUG_ASM_SPEC ""
1099#endif /* not GAS */
1100
4e88bbcd
ILT		 1101/* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1102 overridden by subtargets. */
1103
1104#ifndef SUBTARGET_ASM_SPEC
1105#define SUBTARGET_ASM_SPEC ""
bb98bc58 1106#endif
4e88bbcd 1107
a27fb29b
RS		 1108/* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1109 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1110 whether we're using GAS. These options can only be used properly
1111 with GAS, and it is better to get an error from a non-GAS assembler
1112 than to silently generate bad code. */
4e88bbcd 1113
b2bcb32d 1114#undef ASM_SPEC
4e88bbcd 1115#define ASM_SPEC "\
2d2a50c3
CD		 1116%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1117%{mips32} %{mips32r2} %{mips64} \
2bcb2ab3 1118%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
4e88bbcd
ILT		 1119%(subtarget_asm_optimizing_spec) \
1120%(subtarget_asm_debugging_spec) \
1121%{membedded-pic} \
a27fb29b
RS		 1122%{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1123%{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1124%{mgp32} %{mgp64} %{march=*} \
4e88bbcd
ILT		 1125%(target_asm_spec) \
1126%(subtarget_asm_spec)"
e75b25e7
MM		 1127
1128/* Specify to run a post-processor, mips-tfile after the assembler
1129 has run to stuff the mips debug information into the object file.
1130 This is needed because the $#!%^ MIPS assembler provides no way
a813fadf
MM		 1131 of specifying such information in the assembly file. If we are
1132 cross compiling, disable mips-tfile unless the user specifies
1133 -mmips-tfile. */
e75b25e7
MM		 1134
1135#ifndef ASM_FINAL_SPEC
bb98bc58
JW		 1136#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1137/* GAS */
31c714e3 1138#define ASM_FINAL_SPEC "\
149e4e00 1139%{mmips-as: %{!mno-mips-tfile: \
31c714e3
MM		 1140 \n mips-tfile %{v*: -v} \
1141 %{K: -I %b.o~} \
1142 %{!K: %{save-temps: -I %b.o~}} \
ab78d4a8 1143 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
31c714e3 1144 %{.s:%i} %{!.s:%g.s}}}"
a813fadf 1145
bb98bc58
JW		 1146#else
1147/* not GAS */
a813fadf 1148#define ASM_FINAL_SPEC "\
149e4e00 1149%{!mgas: %{!mno-mips-tfile: \
a813fadf
MM		 1150 \n mips-tfile %{v*: -v} \
1151 %{K: -I %b.o~} \
1152 %{!K: %{save-temps: -I %b.o~}} \
1153 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1154 %{.s:%i} %{!.s:%g.s}}}"
1155
bb98bc58 1156#endif
a813fadf 1157#endif /* ASM_FINAL_SPEC */
e75b25e7
MM		 1158
1159/* Redefinition of libraries used. Mips doesn't support normal
1160 UNIX style profiling via calling _mcount. It does offer
987ba558 1161 profiling that samples the PC, so do what we can... */
e75b25e7
MM		 1162
1163#ifndef LIB_SPEC
1164#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1165#endif
1166
31c714e3 1167/* Extra switches sometimes passed to the linker. */
bb98bc58
JW		 1168/* ??? The bestGnum will never be passed to the linker, because the gcc driver
1169 will interpret it as a -b option. */
e75b25e7
MM		 1170
1171#ifndef LINK_SPEC
31c714e3 1172#define LINK_SPEC "\
120dc6cd 1173%(endian_spec) \
2d2a50c3 1174%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
120dc6cd 1175%{bestGnum} %{shared} %{non_shared}"
0e5a4ad8
EC		 1176#endif /* LINK_SPEC defined */
1177
e75b25e7
MM		 1178
1179/* Specs for the compiler proper */
1180
c9db96ce
JR		 1181/* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1182 overridden by subtargets. */
1183#ifndef SUBTARGET_CC1_SPEC
1184#define SUBTARGET_CC1_SPEC ""
1185#endif
1186
1187/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
75dcd8fe
MM		 1188/* Note, we will need to adjust the following if we ever find a MIPS variant
1189 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1190 that show up in this case. */
c9db96ce 1191
e75b25e7 1192#ifndef CC1_SPEC
31c714e3 1193#define CC1_SPEC "\
31c714e3 1194%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
96abdcb1 1195%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
c9db96ce 1196%{save-temps: } \
4e314d1f 1197%(subtarget_cc1_spec)"
e75b25e7
MM		 1198#endif
1199
4e88bbcd
ILT		 1200/* Preprocessor specs. */
1201
4e88bbcd
ILT		 1202/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1203 overridden by subtargets. */
1204#ifndef SUBTARGET_CPP_SPEC
1205#define SUBTARGET_CPP_SPEC ""
1206#endif
1207
ce3649d2 1208#define CPP_SPEC "%(subtarget_cpp_spec)"
4e88bbcd
ILT		 1209
1210/* This macro defines names of additional specifications to put in the specs
1211 that can be used in various specifications like CC1_SPEC. Its definition
1212 is an initializer with a subgrouping for each command option.
1213
1214 Each subgrouping contains a string constant, that defines the
1215 specification name, and a string constant that used by the GNU CC driver
1216 program.
1217
1218 Do not define this macro if it does not need to do anything. */
1219
1220#define EXTRA_SPECS \
829245be
KG		 1221 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1222 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
829245be
KG		 1223 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1224 { "gas_asm_spec", GAS_ASM_SPEC }, \
1225 { "target_asm_spec", TARGET_ASM_SPEC }, \
1226 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1227 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1228 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
3bd4f460 1229 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
829245be 1230 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
a27fb29b 1231 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
120dc6cd 1232 { "endian_spec", ENDIAN_SPEC }, \
4e88bbcd
ILT		 1233 SUBTARGET_EXTRA_SPECS
1234
1235#ifndef SUBTARGET_EXTRA_SPECS
1236#define SUBTARGET_EXTRA_SPECS
e75b25e7
MM		 1237#endif
1238
1239/* If defined, this macro is an additional prefix to try after
1240 `STANDARD_EXEC_PREFIX'. */
1241
1242#ifndef MD_EXEC_PREFIX
31c714e3 1243#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
e75b25e7
MM		 1244#endif
1245
59c94430
MM		 1246#ifndef MD_STARTFILE_PREFIX
1247#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1248#endif
1249
e75b25e7
MM		 1250\f
1251/* Print subsidiary information on the compiler version in use. */
1252
42dee4c7 1253#define MIPS_VERSION "[AL 1.1, MM 40]"
e75b25e7
MM		 1254
1255#ifndef MACHINE_TYPE
1256#define MACHINE_TYPE "BSD Mips"
1257#endif
1258
1259#ifndef TARGET_VERSION_INTERNAL
1260#define TARGET_VERSION_INTERNAL(STREAM) \
1261 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1262#endif
1263
1264#ifndef TARGET_VERSION
1265#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1266#endif
1267
1268\f
23532de9
JT		 1269#define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1270#define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1271#define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
e75b25e7
MM		 1272
1273#ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
fe0986b4 1274#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
e75b25e7
MM		 1275#endif
1276
59c94430
MM		 1277/* By default, turn on GDB extensions. */
1278#define DEFAULT_GDB_EXTENSIONS 1
1279
e75b25e7
MM		 1280/* If we are passing smuggling stabs through the MIPS ECOFF object
1281 format, put a comment in front of the .stab<x> operation so
1282 that the MIPS assembler does not choke. The mips-tfile program
1283 will correctly put the stab into the object file. */
1284
78d057d8
HPN		 1285#define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1286#define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1287#define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
e75b25e7 1288
6ae1498b
JW		 1289/* Local compiler-generated symbols must have a prefix that the assembler
1290 understands. By default, this is $, although some targets (e.g.,
987ba558 1291 NetBSD-ELF) need to override this. */
6ae1498b
JW		 1292
1293#ifndef LOCAL_LABEL_PREFIX
1294#define LOCAL_LABEL_PREFIX "$"
1295#endif
1296
1297/* By default on the mips, external symbols do not have an underscore
987ba558 1298 prepended, but some targets (e.g., NetBSD) require this. */
6ae1498b
JW		 1299
1300#ifndef USER_LABEL_PREFIX
1301#define USER_LABEL_PREFIX ""
1302#endif
1303
e75b25e7
MM		 1304/* Forward references to tags are allowed. */
1305#define SDB_ALLOW_FORWARD_REFERENCES
1306
1307/* Unknown tags are also allowed. */
1308#define SDB_ALLOW_UNKNOWN_REFERENCES
1309
1310/* On Sun 4, this limit is 2048. We use 1500 to be safe,
1311 since the length can run past this up to a continuation point. */
44404b8b 1312#undef DBX_CONTIN_LENGTH
e75b25e7
MM		 1313#define DBX_CONTIN_LENGTH 1500
1314
987ba558 1315/* How to renumber registers for dbx and gdb. */
e75b25e7
MM		 1316#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1317
c8cc5c4a 1318/* The mapping from gcc register number to DWARF 2 CFA column number.
0021b564
JM		 1319 This mapping does not allow for tracking register 0, since SGI's broken
1320 dwarf reader thinks column 0 is used for the frame address, but since
1321 register 0 is fixed this is not a problem. */
469ac993 1322#define DWARF_FRAME_REGNUM(REG) \
0021b564 1323 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
c8cc5c4a
JM		 1324
1325/* The DWARF 2 CFA column which tracks the return address. */
1326#define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
e75b25e7 1327
469ac993 1328/* Before the prologue, RA lives in r31. */
c5c76735 1329#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
469ac993 1330
9e800206 1331/* Describe how we implement __builtin_eh_return. */
282cb01b 1332#define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
9e800206
RH		 1333#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1334
7dac2f89 1335/* Offsets recorded in opcodes are a multiple of this alignment factor.
b3276c7a
GK		 1336 The default for this in 64-bit mode is 8, which causes problems with
1337 SFmode register saves. */
1338#define DWARF_CIE_DATA_ALIGNMENT 4
1339
e8b84d3d 1340#define FIND_BASE_TERM(X) mips_delegitimize_address (X)
cafe096b 1341
e75b25e7
MM		 1342#define PUT_SDB_DEF(a) \
1343do { \
20db0e3c 1344 fprintf (asm_out_file, "\t%s.def\t", \
b82b0773 1345 (TARGET_GAS) ? "" : "#"); \
20db0e3c
RS		 1346 ASM_OUTPUT_LABELREF (asm_out_file, a); \
1347 fputc (';', asm_out_file); \
e75b25e7
MM		 1348} while (0)
1349
1350#define PUT_SDB_PLAIN_DEF(a) \
1351do { \
20db0e3c 1352 fprintf (asm_out_file, "\t%s.def\t.%s;", \
b82b0773 1353 (TARGET_GAS) ? "" : "#", (a)); \
e75b25e7
MM		 1354} while (0)
1355
e75b25e7
MM		 1356/* For block start and end, we create labels, so that
1357 later we can figure out where the correct offset is.
1358 The normal .ent/.end serve well enough for functions,
1359 so those are just commented out. */
1360
1361#define PUT_SDB_BLOCK_START(LINE) \
1362do { \
20db0e3c 1363 fprintf (asm_out_file, \
6ae1498b
JW		 1364 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1365 LOCAL_LABEL_PREFIX, \
e75b25e7 1366 sdb_label_count, \
b82b0773 1367 (TARGET_GAS) ? "" : "#", \
6ae1498b 1368 LOCAL_LABEL_PREFIX, \
e75b25e7
MM		 1369 sdb_label_count, \
1370 (LINE)); \
1371 sdb_label_count++; \
1372} while (0)
1373
1374#define PUT_SDB_BLOCK_END(LINE) \
1375do { \
20db0e3c 1376 fprintf (asm_out_file, \
6ae1498b
JW		 1377 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1378 LOCAL_LABEL_PREFIX, \
e75b25e7 1379 sdb_label_count, \
b82b0773 1380 (TARGET_GAS) ? "" : "#", \
6ae1498b 1381 LOCAL_LABEL_PREFIX, \
e75b25e7
MM		 1382 sdb_label_count, \
1383 (LINE)); \
1384 sdb_label_count++; \
1385} while (0)
1386
1387#define PUT_SDB_FUNCTION_START(LINE)
1388
8f2e3902
EC		 1389#define PUT_SDB_FUNCTION_END(LINE) \
1390do { \
9e21232c 1391 ASM_OUTPUT_SOURCE_LINE (asm_out_file, LINE + sdb_begin_function_line, 0); \
a642a781 1392} while (0)
e75b25e7
MM		 1393
1394#define PUT_SDB_EPILOGUE_END(NAME)
1395
ab78d4a8
MM		 1396/* Correct the offset of automatic variables and arguments. Note that
1397 the MIPS debug format wants all automatic variables and arguments
1398 to be in terms of the virtual frame pointer (stack pointer before
1399 any adjustment in the function), while the MIPS 3.0 linker wants
1400 the frame pointer to be the stack pointer after the initial
1401 adjustment. */
e75b25e7 1402
8f2e3902 1403#define DEBUGGER_AUTO_OFFSET(X) \
f5963e61 1404 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
8f2e3902 1405#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
f5963e61 1406 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
31c714e3
MM		 1407
1408/* Tell collect that the object format is ECOFF */
31c714e3
MM		 1409#define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1410#define EXTENDED_COFF /* ECOFF, not normal coff */
e75b25e7
MM		 1411\f
1412/* Target machine storage layout */
1413
1414/* Define this if most significant bit is lowest numbered
1415 in instructions that operate on numbered bit-fields.
1416*/
4851a75c 1417#define BITS_BIG_ENDIAN 0
e75b25e7 1418
987ba558 1419/* Define this if most significant byte of a word is the lowest numbered. */
96abdcb1 1420#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
e75b25e7 1421
987ba558 1422/* Define this if most significant word of a multiword number is the lowest. */
96abdcb1 1423#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
e75b25e7 1424
96abdcb1
ILT		 1425/* Define this to set the endianness to use in libgcc2.c, which can
1426 not depend on target_flags. */
1427#if !defined(MIPSEL) && !defined(__MIPSEL__)
1428#define LIBGCC2_WORDS_BIG_ENDIAN 1
e75b25e7 1429#else
96abdcb1 1430#define LIBGCC2_WORDS_BIG_ENDIAN 0
e75b25e7
MM		 1431#endif
1432
876c09d3 1433#define MAX_BITS_PER_WORD 64
e75b25e7
MM		 1434
1435/* Width of a word, in units (bytes). */
456f6501 1436#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
ef0e53ce 1437#define MIN_UNITS_PER_WORD 4
876c09d3
JW		 1438
1439/* For MIPS, width of a floating point register. */
456f6501 1440#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
e75b25e7 1441
3f26edaa
RS		 1442/* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1443 the next available register. */
1444#define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1445
8a381273
AO		 1446/* The largest size of value that can be held in floating-point
1447 registers and moved with a single instruction. */
1448#define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1449
1450/* The largest size of value that can be held in floating-point
1451 registers. */
1452#define UNITS_PER_FPVALUE \
1453 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
4d72536e
RS		 1454
1455/* The number of bytes in a double. */
1456#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
3f26edaa 1457
e75b25e7
MM		 1458/* A C expression for the size in bits of the type `int' on the
1459 target machine. If you don't define this, the default is one
1460 word. */
456f6501 1461#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
876c09d3
JW		 1462
1463/* Tell the preprocessor the maximum size of wchar_t. */
1464#ifndef MAX_WCHAR_TYPE_SIZE
1465#ifndef WCHAR_TYPE_SIZE
16c484c7 1466#define MAX_WCHAR_TYPE_SIZE 64
876c09d3
JW		 1467#endif
1468#endif
e75b25e7
MM		 1469
1470/* A C expression for the size in bits of the type `short' on the
1471 target machine. If you don't define this, the default is half a
1472 word. (If this would be less than one storage unit, it is
1473 rounded up to one unit.) */
1474#define SHORT_TYPE_SIZE 16
1475
1476/* A C expression for the size in bits of the type `long' on the
1477 target machine. If you don't define this, the default is one
1478 word. */
456f6501 1479#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
876c09d3 1480#define MAX_LONG_TYPE_SIZE 64
e75b25e7
MM		 1481
1482/* A C expression for the size in bits of the type `long long' on the
1483 target machine. If you don't define this, the default is two
1484 words. */
923d630e 1485#define LONG_LONG_TYPE_SIZE 64
e75b25e7 1486
e75b25e7
MM		 1487/* A C expression for the size in bits of the type `float' on the
1488 target machine. If you don't define this, the default is one
1489 word. */
1490#define FLOAT_TYPE_SIZE 32
1491
1492/* A C expression for the size in bits of the type `double' on the
1493 target machine. If you don't define this, the default is two
1494 words. */
1495#define DOUBLE_TYPE_SIZE 64
1496
1497/* A C expression for the size in bits of the type `long double' on
1498 the target machine. If you don't define this, the default is two
1499 words. */
8a381273
AO		 1500#define LONG_DOUBLE_TYPE_SIZE \
1501 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1502
1503/* long double is not a fixed mode, but the idea is that, if we
1504 support long double, we also want a 128-bit integer type. */
1505#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1506
1507#ifdef IN_LIBGCC2
1508#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1509 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1510# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1511# else
1512# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1513# endif
1514#endif
e75b25e7 1515
cafe096b 1516/* Width in bits of a pointer. */
1eeed24e 1517#ifndef POINTER_SIZE
cafe096b 1518#define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1eeed24e 1519#endif
e75b25e7 1520
cafe096b 1521#define POINTERS_EXTEND_UNSIGNED 0
e75b25e7
MM		 1522
1523/* Allocation boundary (in *bits*) for storing arguments in argument list. */
0b51254d
AO		 1524#define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1525 || mips_abi == ABI_64 \
1526 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
e75b25e7 1527
cafe096b 1528
e75b25e7
MM		 1529/* Allocation boundary (in *bits*) for the code of a function. */
1530#define FUNCTION_BOUNDARY 32
1531
1532/* Alignment of field after `int : 0' in a structure. */
9e95597a 1533#define EMPTY_FIELD_BOUNDARY 32
e75b25e7
MM		 1534
1535/* Every structure's size must be a multiple of this. */
1536/* 8 is observed right on a DECstation and on riscos 4.02. */
1537#define STRUCTURE_SIZE_BOUNDARY 8
1538
1539/* There is no point aligning anything to a rounder boundary than this. */
8a381273 1540#define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
e75b25e7 1541
31c714e3 1542/* Set this nonzero if move instructions will actually fail to work
e75b25e7 1543 when given unaligned data. */
31c714e3 1544#define STRICT_ALIGNMENT 1
e75b25e7
MM		 1545
1546/* Define this if you wish to imitate the way many other C compilers
1547 handle alignment of bitfields and the structures that contain
1548 them.
1549
43a88a8c 1550 The behavior is that the type written for a bit-field (`int',
e75b25e7
MM		 1551 `short', or other integer type) imposes an alignment for the
1552 entire structure, as if the structure really did contain an
43a88a8c 1553 ordinary field of that type. In addition, the bit-field is placed
e75b25e7
MM		 1554 within the structure so that it would fit within such a field,
1555 not crossing a boundary for it.
1556
43a88a8c 1557 Thus, on most machines, a bit-field whose type is written as `int'
e75b25e7
MM		 1558 would not cross a four-byte boundary, and would force four-byte
1559 alignment for the whole structure. (The alignment used may not
1560 be four bytes; it is controlled by the other alignment
1561 parameters.)
1562
1563 If the macro is defined, its definition should be a C expression;
1564 a nonzero value for the expression enables this behavior. */
1565
1566#define PCC_BITFIELD_TYPE_MATTERS 1
1567
1568/* If defined, a C expression to compute the alignment given to a
1569 constant that is being placed in memory. CONSTANT is the constant
1570 and ALIGN is the alignment that the object would ordinarily have.
1571 The value of this macro is used instead of that alignment to align
1572 the object.
1573
1574 If this macro is not defined, then ALIGN is used.
1575
1576 The typical use of this macro is to increase alignment for string
1577 constants to be word aligned so that `strcpy' calls that copy
1578 constants can be done inline. */
1579
1580#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1581 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
75131237 1582 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
e75b25e7
MM		 1583
1584/* If defined, a C expression to compute the alignment for a static
1585 variable. TYPE is the data type, and ALIGN is the alignment that
1586 the object would ordinarily have. The value of this macro is used
1587 instead of that alignment to align the object.
1588
1589 If this macro is not defined, then ALIGN is used.
1590
1591 One use of this macro is to increase alignment of medium-size
1592 data to make it all fit in fewer cache lines. Another is to
1593 cause character arrays to be word-aligned so that `strcpy' calls
1594 that copy constants to character arrays can be done inline. */
1595
1596#undef DATA_ALIGNMENT
1597#define DATA_ALIGNMENT(TYPE, ALIGN) \
1598 ((((ALIGN) < BITS_PER_WORD) \
1599 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1600 || TREE_CODE (TYPE) == UNION_TYPE \
1601 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1602
f5c8ac96
CP		 1603
1604/* Force right-alignment for small varargs in 32 bit little_endian mode */
1605
cafe096b 1606#define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
f5c8ac96 1607
e75b25e7
MM		 1608/* Define this macro if an argument declared as `char' or `short' in a
1609 prototype should actually be passed as an `int'. In addition to
1610 avoiding errors in certain cases of mismatch, it also makes for
987ba558 1611 better code on certain machines. */
e75b25e7 1612
cb560352 1613#define PROMOTE_PROTOTYPES 1
e75b25e7 1614
9a63901f
RK		 1615/* Define if operations between registers always perform the operation
1616 on the full register even if a narrower mode is specified. */
1617#define WORD_REGISTER_OPERATIONS
1618
1619/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1620 will either zero-extend or sign-extend. The value of this macro should
1621 be the code that says which one of the two operations is implicitly
7dac2f89 1622 done, NIL if none.
a872728c
JL		 1623
1624 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1625 moves. All other referces are zero extended. */
1626#define LOAD_EXTEND_OP(MODE) \
1627 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1628 ? SIGN_EXTEND : ZERO_EXTEND)
2bcb2ab3
GK		 1629
1630/* Define this macro if it is advisable to hold scalars in registers
7dac2f89 1631 in a wider mode than that declared by the program. In such cases,
2bcb2ab3
GK		 1632 the value is constrained to be within the bounds of the declared
1633 type, but kept valid in the wider mode. The signedness of the
cafe096b 1634 extension may differ from that of the type. */
2bcb2ab3
GK		 1635
1636#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1637 if (GET_MODE_CLASS (MODE) == MODE_INT \
cafe096b
EC		 1638 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1639 { \
1640 if ((MODE) == SImode) \
1641 (UNSIGNEDP) = 0; \
1642 (MODE) = Pmode; \
1643 }
1644
1645/* Define if loading short immediate values into registers sign extends. */
1646#define SHORT_IMMEDIATES_SIGN_EXTEND
1647
2bcb2ab3
GK		 1648
1649/* Define this if function arguments should also be promoted using the above
1650 procedure. */
2bcb2ab3
GK		 1651#define PROMOTE_FUNCTION_ARGS
1652
1653/* Likewise, if the function return value is promoted. */
2bcb2ab3 1654#define PROMOTE_FUNCTION_RETURN
cafe096b 1655
e75b25e7
MM		 1656\f
1657/* Standard register usage. */
1658
1659/* Number of actual hardware registers.
1660 The hardware registers are assigned numbers for the compiler
1661 from 0 to just below FIRST_PSEUDO_REGISTER.
1662 All registers that the compiler knows about must be given numbers,
1663 even those that are not normally considered general registers.
1664
225b8835 1665 On the Mips, we have 32 integer registers, 32 floating point
b8eb88d0 1666 registers, 8 condition code registers, and the special registers
d334c3c1
RS		 1667 hi and lo. After that we have 32 COP0 registers, 32 COP2 registers,
1668 and 32 COP3 registers. (COP1 is the floating-point processor.)
1669 The 8 condition code registers are only used if mips_isa >= 4. */
e75b25e7 1670
d604bca3 1671#define FIRST_PSEUDO_REGISTER 176
e75b25e7
MM		 1672
1673/* 1 for registers that have pervasive standard uses
1674 and are not available for the register allocator.
1675
1676 On the MIPS, see conventions, page D-2 */
1677
d604bca3
MH		 1678/* Regarding coprocessor registers: without evidence to the contrary,
1679 it's best to assume that each coprocessor register has a unique
1680 use. This can be overridden, in, e.g., override_options() or
1681 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1682 for a particular target. */
1683
e75b25e7
MM		 1684#define FIXED_REGISTERS \
1685{ \
1686 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
cafe096b 1687 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
e75b25e7
MM		 1688 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1689 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
d334c3c1 1690 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
d604bca3
MH		 1691 /* COP0 registers */ \
1692 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1693 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1694 /* COP2 registers */ \
1695 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1696 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1697 /* COP3 registers */ \
1698 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1699 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
e75b25e7
MM		 1700}
1701
1702
cafe096b
EC		 1703/* Don't mark $31 as a call-clobbered register. The idea is that
1704 it's really the call instructions themselves which clobber $31.
1705 We don't care what the called function does with it afterwards.
1706
1707 This approach makes it easier to implement sibcalls. Unlike normal
1708 calls, sibcalls don't clobber $31, so the register reaches the
1709 called function in tact. EPILOGUE_USES says that $31 is useful
1710 to the called function. */
e75b25e7
MM		 1711
1712#define CALL_USED_REGISTERS \
1713{ \
1714 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
cafe096b 1715 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
e75b25e7
MM		 1716 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1717 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
cafe096b 1718 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
d604bca3
MH		 1719 /* COP0 registers */ \
1720 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1721 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1722 /* COP2 registers */ \
1723 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1724 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1725 /* COP3 registers */ \
1726 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1727 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
e75b25e7
MM		 1728}
1729
2ca2d9ee
EC		 1730/* Like `CALL_USED_REGISTERS' but used to overcome a historical
1731 problem which makes CALL_USED_REGISTERS *always* include
1732 all the FIXED_REGISTERS. Until this problem has been
1733 resolved this macro can be used to overcome this situation.
1734 In particular, block_propagate() requires this list
1735 be acurate, or we can remove registers which should be live.
1736 This macro is used in regs_invalidated_by_call. */
1737
1738
1739#define CALL_REALLY_USED_REGISTERS \
1740{ /* General registers. */ \
1741 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
cafe096b 1742 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
2ca2d9ee
EC		 1743 /* Floating-point registers. */ \
1744 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1745 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1746 /* Others. */ \
cafe096b 1747 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
d604bca3
MH		 1748 /* COP0 registers */ \
1749 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1750 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1751 /* COP2 registers */ \
1752 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1753 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1754 /* COP3 registers */ \
1755 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1756 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
2ca2d9ee 1757}
e75b25e7
MM		 1758
1759/* Internal macros to classify a register number as to whether it's a
1760 general purpose register, a floating point register, a
516a2dfd 1761 multiply/divide register, or a status register. */
e75b25e7
MM		 1762
1763#define GP_REG_FIRST 0
1764#define GP_REG_LAST 31
1765#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1766#define GP_DBX_FIRST 0
1767
1768#define FP_REG_FIRST 32
1769#define FP_REG_LAST 63
1770#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1771#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1772
1773#define MD_REG_FIRST 64
d334c3c1 1774#define MD_REG_LAST 65
e75b25e7 1775#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
77d4f3a4 1776#define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
e75b25e7 1777
225b8835 1778#define ST_REG_FIRST 67
b8eb88d0 1779#define ST_REG_LAST 74
e75b25e7
MM		 1780#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1781
39dffea3 1782
cafe096b 1783/* FIXME: renumber. */
d604bca3
MH		 1784#define COP0_REG_FIRST 80
1785#define COP0_REG_LAST 111
1786#define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1787
1788#define COP2_REG_FIRST 112
1789#define COP2_REG_LAST 143
1790#define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1791
1792#define COP3_REG_FIRST 144
1793#define COP3_REG_LAST 175
1794#define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1795/* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1796#define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1797
e75b25e7
MM		 1798#define AT_REGNUM (GP_REG_FIRST + 1)
1799#define HI_REGNUM (MD_REG_FIRST + 0)
1800#define LO_REGNUM (MD_REG_FIRST + 1)
b8eb88d0
ILT		 1801
1802/* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1803 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1804 should be used instead. */
e75b25e7
MM		 1805#define FPSW_REGNUM ST_REG_FIRST
1806
75131237
RK		 1807#define GP_REG_P(REGNO) \
1808 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
2bcb2ab3
GK		 1809#define M16_REG_P(REGNO) \
1810 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
75131237
RK		 1811#define FP_REG_P(REGNO) \
1812 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1813#define MD_REG_P(REGNO) \
1814 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1815#define ST_REG_P(REGNO) \
1816 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
d604bca3
MH		 1817#define COP0_REG_P(REGNO) \
1818 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1819#define COP2_REG_P(REGNO) \
1820 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1821#define COP3_REG_P(REGNO) \
1822 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1823#define ALL_COP_REG_P(REGNO) \
1824 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1825
5b0f0db6
RS		 1826#define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1827
d604bca3
MH		 1828/* Return coprocessor number from register number. */
1829
1830#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1831 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1832 : COP3_REG_P (REGNO) ? '3' : '?')
e75b25e7 1833
e75b25e7
MM		 1834/* Return number of consecutive hard regs needed starting at reg REGNO
1835 to hold something of mode MODE.
1836 This is ordinarily the length in words of a value of mode MODE
1837 but can be less for certain modes in special long registers.
1838
1839 On the MIPS, all general registers are one word long. Except on
1840 the R4000 with the FR bit set, the floating point uses register
956d6950 1841 pairs, with the second register not being allocable. */
e75b25e7 1842
0e5a4ad8 1843#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
e75b25e7
MM		 1844
1845/* Value is 1 if hard register REGNO can hold a value of machine-mode
876c09d3
JW		 1846 MODE. In 32 bit mode, require that DImode and DFmode be in even
1847 registers. For DImode, this makes some of the insns easier to
1848 write, since you don't have to worry about a DImode value in
1849 registers 3 & 4, producing a result in 4 & 5.
e75b25e7
MM		 1850
1851 To make the code simpler HARD_REGNO_MODE_OK now just references an
1852 array built in override_options. Because machmodes.h is not yet
1853 included before this file is processed, the MODE bound can't be
1854 expressed here. */
1855
1856extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1857
1858#define HARD_REGNO_MODE_OK(REGNO, MODE) \
1859 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1860
1861/* Value is 1 if it is a good idea to tie two pseudo registers
1862 when one has mode MODE1 and one has mode MODE2.
1863 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1864 for any hard reg, then this must be 0 for correct output. */
1865#define MODES_TIEABLE_P(MODE1, MODE2) \
1866 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1867 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1868 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1869 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1870
1871/* MIPS pc is not overloaded on a register. */
1872/* #define PC_REGNUM xx */
1873
1874/* Register to use for pushing function arguments. */
0fb5ac6f 1875#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
e75b25e7 1876
97116296
ILT		 1877/* Offset from the stack pointer to the first available location. Use
1878 the default value zero. */
1879/* #define STACK_POINTER_OFFSET 0 */
e75b25e7 1880
2bcb2ab3
GK		 1881/* Base register for access to local variables of the function. We
1882 pretend that the frame pointer is $1, and then eliminate it to
1883 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1884 a fixed register, and will not be used for anything else. */
1885#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1886
0ff83799
MM		 1887/* Temporary scratch register for use by the assembler. */
1888#define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1889
2bcb2ab3
GK		 1890/* $30 is not available on the mips16, so we use $17 as the frame
1891 pointer. */
1892#define HARD_FRAME_POINTER_REGNUM \
1893 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
e75b25e7
MM		 1894
1895/* Value should be nonzero if functions must have frame pointers.
1896 Zero means the frame pointer need not be set up (and parms
1897 may be accessed via the stack pointer) in functions that seem suitable.
1898 This is computed in `reload', in reload1.c. */
1899#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1900
1901/* Base register for access to arguments of the function. */
ab78d4a8 1902#define ARG_POINTER_REGNUM GP_REG_FIRST
e75b25e7
MM		 1903
1904/* Register in which static-chain is passed to a function. */
0fb5ac6f 1905#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
e75b25e7 1906
1154b096
MM		 1907/* If the structure value address is passed in a register, then
1908 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1909/* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1910
1911/* If the structure value address is not passed in a register, define
1912 `STRUCT_VALUE' as an expression returning an RTX for the place
1913 where the address is passed. If it returns 0, the address is
1914 passed as an "invisible" first argument. */
f58cfbfb 1915#define STRUCT_VALUE 0
e75b25e7
MM		 1916
1917/* Mips registers used in prologue/epilogue code when the stack frame
1918 is larger than 32K bytes. These registers must come from the
1919 scratch register set, and not used for passing and returning
1920 arguments and any other information used in the calling sequence
516a2dfd
JW		 1921 (such as pic). Must start at 12, since t0/t3 are parameter passing
1922 registers in the 64 bit ABI. */
7bea35e7 1923
516a2dfd
JW		 1924#define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1925#define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
e75b25e7
MM		 1926
1927/* Define this macro if it is as good or better to call a constant
1928 function address than to call an address kept in a register. */
1929#define NO_FUNCTION_CSE 1
1930
1931/* Define this macro if it is as good or better for a function to
1932 call itself with an explicit address than to call an address
1933 kept in a register. */
1934#define NO_RECURSIVE_FUNCTION_CSE 1
1935
f833ffd4
RS		 1936/* The ABI-defined global pointer. Sometimes we use a different
1937 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1938#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1939
1940/* We normally use $28 as the global pointer. However, when generating
1941 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1942 register instead. They can then avoid saving and restoring $28
1943 and perhaps avoid using a frame at all.
1944
1945 When a leaf function uses something other than $28, mips_expand_prologue
1946 will modify pic_offset_table_rtx in place. Take the register number
1947 from there after reload. */
1948#define PIC_OFFSET_TABLE_REGNUM \
1949 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
e75b25e7 1950
24e214e3 1951#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
e75b25e7
MM		 1952\f
1953/* Define the classes of registers for register constraints in the
1954 machine description. Also define ranges of constants.
1955
1956 One of the classes must always be named ALL_REGS and include all hard regs.
1957 If there is more than one class, another class must be named NO_REGS
1958 and contain no registers.
1959
1960 The name GENERAL_REGS must be the name of a class (or an alias for
1961 another name such as ALL_REGS). This is the class of registers
1962 that is allowed by "g" or "r" in a register constraint.
1963 Also, registers outside this class are allocated only when
1964 instructions express preferences for them.
1965
1966 The classes must be numbered in nondecreasing order; that is,
1967 a larger-numbered class must never be contained completely
1968 in a smaller-numbered class.
1969
1970 For any two classes, it is very desirable that there be another
1971 class that represents their union. */
1972
1973enum reg_class
1974{
1975 NO_REGS, /* no registers in set */
2bcb2ab3
GK		 1976 M16_NA_REGS, /* mips16 regs not used to pass args */
1977 M16_REGS, /* mips16 directly accessible registers */
1978 T_REG, /* mips16 T register ($24) */
1979 M16_T_REGS, /* mips16 registers plus T register */
cafe096b
EC		 1980 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1981 LEA_REGS, /* Every GPR except $25 */
e75b25e7
MM		 1982 GR_REGS, /* integer registers */
1983 FP_REGS, /* floating point registers */
1984 HI_REG, /* hi register */
1985 LO_REG, /* lo register */
1986 MD_REGS, /* multiply/divide registers (hi/lo) */
d604bca3
MH		 1987 COP0_REGS, /* generic coprocessor classes */
1988 COP2_REGS,
1989 COP3_REGS,
e4f5c5d6
KR		 1990 HI_AND_GR_REGS, /* union classes */
1991 LO_AND_GR_REGS,
ab093b81 1992 HI_AND_FP_REGS,
d604bca3
MH		 1993 COP0_AND_GR_REGS,
1994 COP2_AND_GR_REGS,
1995 COP3_AND_GR_REGS,
1996 ALL_COP_REGS,
1997 ALL_COP_AND_GR_REGS,
e75b25e7
MM		 1998 ST_REGS, /* status registers (fp status) */
1999 ALL_REGS, /* all registers */
2000 LIM_REG_CLASSES /* max value + 1 */
2001};
2002
2003#define N_REG_CLASSES (int) LIM_REG_CLASSES
2004
2005#define GENERAL_REGS GR_REGS
2006
2007/* An initializer containing the names of the register classes as C
2008 string constants. These names are used in writing some of the
2009 debugging dumps. */
2010
2011#define REG_CLASS_NAMES \
2012{ \
2013 "NO_REGS", \
2bcb2ab3
GK		 2014 "M16_NA_REGS", \
2015 "M16_REGS", \
2016 "T_REG", \
2017 "M16_T_REGS", \
cafe096b
EC		 2018 "PIC_FN_ADDR_REG", \
2019 "LEA_REGS", \
e75b25e7
MM		 2020 "GR_REGS", \
2021 "FP_REGS", \
2022 "HI_REG", \
2023 "LO_REG", \
2024 "MD_REGS", \
d604bca3
MH		 2025 /* coprocessor registers */ \
2026 "COP0_REGS", \
2027 "COP2_REGS", \
2028 "COP3_REGS", \
e4f5c5d6
KR		 2029 "HI_AND_GR_REGS", \
2030 "LO_AND_GR_REGS", \
ab093b81 2031 "HI_AND_FP_REGS", \
d604bca3
MH		 2032 "COP0_AND_GR_REGS", \
2033 "COP2_AND_GR_REGS", \
2034 "COP3_AND_GR_REGS", \
2035 "ALL_COP_REGS", \
2036 "ALL_COP_AND_GR_REGS", \
e75b25e7
MM		 2037 "ST_REGS", \
2038 "ALL_REGS" \
2039}
2040
2041/* An initializer containing the contents of the register classes,
2042 as integers which are bit masks. The Nth integer specifies the
2043 contents of class N. The way the integer MASK is interpreted is
2044 that register R is in the class if `MASK & (1 << R)' is 1.
2045
2046 When the machine has more than 32 registers, an integer does not
2047 suffice. Then the integers are replaced by sub-initializers,
2048 braced groupings containing several integers. Each
2049 sub-initializer must be suitable as an initializer for the type
2050 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2051
2052#define REG_CLASS_CONTENTS \
2053{ \
d604bca3
MH		 2054 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2055 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2056 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2057 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2058 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
cafe096b
EC		 2059 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
2060 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
d604bca3
MH		 2061 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2062 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2063 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2064 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
d604bca3
MH		 2065 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2066 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2067 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2068 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2069 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2070 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
d604bca3
MH		 2071 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2072 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2073 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2074 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2075 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2076 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2077 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2078 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
e75b25e7
MM		 2079}
2080
2081
2082/* A C expression whose value is a register class containing hard
2083 register REGNO. In general there is more that one such class;
2084 choose a class which is "minimal", meaning that no smaller class
2085 also contains the register. */
2086
8b60264b 2087extern const enum reg_class mips_regno_to_class[];
e75b25e7
MM		 2088
2089#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2090
2091/* A macro whose definition is the name of the class to which a
2092 valid base register must belong. A base register is one used in
2093 an address which is the register value plus a displacement. */
2094
2bcb2ab3 2095#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
e75b25e7
MM		 2096
2097/* A macro whose definition is the name of the class to which a
2098 valid index register must belong. An index register is one used
2099 in an address where its value is either multiplied by a scale
2100 factor or added to another register (as well as added to a
2101 displacement). */
2102
876c09d3 2103#define INDEX_REG_CLASS NO_REGS
e75b25e7 2104
2bcb2ab3
GK		 2105/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2106 registers explicitly used in the rtl to be used as spill registers
2107 but prevents the compiler from extending the lifetime of these
987ba558 2108 registers. */
2bcb2ab3
GK		 2109
2110#define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2111
2112/* This macro is used later on in the file. */
2113#define GR_REG_CLASS_P(CLASS) \
2114 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
cafe096b
EC		 2115 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
2116 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
2bcb2ab3 2117
d604bca3
MH		 2118/* This macro is also used later on in the file. */
2119#define COP_REG_CLASS_P(CLASS) \
2120 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2121
2bcb2ab3
GK		 2122/* REG_ALLOC_ORDER is to order in which to allocate registers. This
2123 is the default value (allocate the registers in numeric order). We
2124 define it just so that we can override it for the mips16 target in
2125 ORDER_REGS_FOR_LOCAL_ALLOC. */
2126
2127#define REG_ALLOC_ORDER \
2128{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2129 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2130 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2131 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
d604bca3
MH		 2132 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2133 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2134 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2135 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2136 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2137 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2138 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2bcb2ab3
GK		 2139}
2140
2141/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2142 to be rearranged based on a particular function. On the mips16, we
2143 want to allocate $24 (T_REG) before other registers for
2144 instructions for which it is possible. */
2145
2146#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
e75b25e7
MM		 2147
2148/* REGISTER AND CONSTANT CLASSES */
2149
2150/* Get reg_class from a letter such as appears in the machine
2151 description.
2152
2153 DEFINED REGISTER CLASSES:
2154
2155 'd' General (aka integer) registers
2bcb2ab3
GK		 2156 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2157 'y' General registers (in both mips16 and non mips16 mode)
2158 'e' mips16 non argument registers (M16_NA_REGS)
2159 't' mips16 temporary register ($24)
e75b25e7
MM		 2160 'f' Floating point registers
2161 'h' Hi register
2162 'l' Lo register
34b650b3 2163 'x' Multiply/divide registers
225b8835 2164 'z' FP Status register
d604bca3
MH		 2165 'B' Cop0 register
2166 'C' Cop2 register
2167 'D' Cop3 register
225b8835 2168 'b' All registers */
e75b25e7 2169
f540a7d3 2170extern enum reg_class mips_char_to_class[256];
e75b25e7 2171
8f54374e 2172#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
e75b25e7 2173
cafe096b
EC		 2174/* True if VALUE is a signed 16-bit number. */
2175
2176#define SMALL_OPERAND(VALUE) \
2177 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2178
2179/* True if VALUE is an unsigned 16-bit number. */
2180
2181#define SMALL_OPERAND_UNSIGNED(VALUE) \
2182 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2183
2184/* True if VALUE can be loaded into a register using LUI. */
2185
2186#define LUI_OPERAND(VALUE) \
2187 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2188 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2189
2190/* Return a value X with the low 16 bits clear, and such that
2191 VALUE - X is a signed 16-bit value. */
2192
2193#define CONST_HIGH_PART(VALUE) \
2194 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2195
2196#define CONST_LOW_PART(VALUE) \
2197 ((VALUE) - CONST_HIGH_PART (VALUE))
2198
2199#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2200#define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2201#define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2202
e75b25e7
MM		 2203/* The letters I, J, K, L, M, N, O, and P in a register constraint
2204 string can be used to stand for particular ranges of immediate
2205 operands. This macro defines what the ranges are. C is the
2206 letter, and VALUE is a constant value. Return 1 if VALUE is
2207 in the range specified by C. */
2208
2209/* For MIPS:
2210
2211 `I' is used for the range of constants an arithmetic insn can
2212 actually contain (16 bits signed integers).
2213
2214 `J' is used for the range which is just zero (ie, $r0).
2215
2216 `K' is used for the range of constants a logical insn can actually
2217 contain (16 bit zero-extended integers).
2218
2219 `L' is used for the range of constants that be loaded with lui
2220 (ie, the bottom 16 bits are zero).
2221
2222 `M' is used for the range of constants that take two words to load
2223 (ie, not matched by `I', `K', and `L').
2224
2bcb2ab3 2225 `N' is used for negative 16 bit constants other than -65536.
e75b25e7 2226
2bcb2ab3 2227 `O' is a 15 bit signed integer.
e75b25e7
MM		 2228
2229 `P' is used for positive 16 bit constants. */
2230
e75b25e7 2231#define CONST_OK_FOR_LETTER_P(VALUE, C) \
cafe096b 2232 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
e75b25e7 2233 : (C) == 'J' ? ((VALUE) == 0) \
cafe096b
EC		 2234 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2235 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2236 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2237 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2238 && !LUI_OPERAND (VALUE)) \
2bcb2ab3
GK		 2239 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2240 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
99cbc4b0 2241 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
e75b25e7
MM		 2242 : 0)
2243
2244/* Similar, but for floating constants, and defining letters G and H.
2245 Here VALUE is the CONST_DOUBLE rtx itself. */
2246
2247/* For Mips
2248
2249 'G' : Floating point 0 */
2250
2251#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2252 ((C) == 'G' \
876c09d3 2253 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
e75b25e7 2254
cafe096b
EC		 2255/* True if OP is a constant that should not be moved into $25.
2256 We need this because many versions of gas treat 'la $25,foo' as
2257 part of a call sequence and allow a global 'foo' to be lazily bound. */
2258
2259#define DANGEROUS_FOR_LA25_P(OP) \
2260 (TARGET_ABICALLS \
2261 && !TARGET_EXPLICIT_RELOCS \
2262 && mips_global_pic_constant_p (OP))
2263
e75b25e7 2264/* Letters in the range `Q' through `U' may be defined in a
7dac2f89 2265 machine-dependent fashion to stand for arbitrary operand types.
e75b25e7
MM		 2266 The machine description macro `EXTRA_CONSTRAINT' is passed the
2267 operand as its first argument and the constraint letter as its
2268 second operand.
2269
cafe096b
EC		 2270 `Q' is for signed 16-bit constants.
2271 `R' is for single-instruction memory references. Note that this
2272 constraint has often been used in linux and glibc code.
2273 `S' is for legitimate constant call addresses.
2274 `T' is for constant move_operands that cannot be safely loaded into $25.
2275 `U' is for constant move_operands that can be safely loaded into $25. */
e75b25e7
MM		 2276
2277#define EXTRA_CONSTRAINT(OP,CODE) \
cafe096b
EC		 2278 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2279 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2280 && mips_fetch_insns (OP) == 1) \
2281 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2282 && call_insn_operand (OP, VOIDmode)) \
2283 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2284 && move_operand (OP, VOIDmode) \
2285 && DANGEROUS_FOR_LA25_P (OP)) \
2286 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2287 && move_operand (OP, VOIDmode) \
2288 && !DANGEROUS_FOR_LA25_P (OP)) \
e75b25e7
MM		 2289 : FALSE)
2290
2291/* Given an rtx X being reloaded into a reg required to be
2292 in class CLASS, return the class of reg to actually use.
2293 In general this is just CLASS; but on some machines
2294 in some cases it is preferable to use a more restrictive class. */
2295
2296#define PREFERRED_RELOAD_CLASS(X,CLASS) \
876c09d3 2297 ((CLASS) != ALL_REGS \
2bcb2ab3
GK		 2298 ? (! TARGET_MIPS16 \
2299 ? (CLASS) \
2300 : ((CLASS) != GR_REGS \
2301 ? (CLASS) \
2302 : M16_REGS)) \
876c09d3
JW		 2303 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2304 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2bcb2ab3
GK		 2305 ? (TARGET_SOFT_FLOAT \
2306 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2307 : FP_REGS) \
876c09d3
JW		 2308 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2309 || GET_MODE (X) == VOIDmode) \
2bcb2ab3 2310 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
876c09d3 2311 : (CLASS))))
e75b25e7 2312
0fb5ac6f
MM		 2313/* Certain machines have the property that some registers cannot be
2314 copied to some other registers without using memory. Define this
a0ab749a 2315 macro on those machines to be a C expression that is nonzero if
0fb5ac6f
MM		 2316 objects of mode MODE in registers of CLASS1 can only be copied to
2317 registers of class CLASS2 by storing a register of CLASS1 into
2318 memory and loading that memory location into a register of CLASS2.
2319
2320 Do not define this macro if its value would always be zero. */
7b2e1077 2321#if 0
0fb5ac6f 2322#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2370b831
JW		 2323 ((!TARGET_DEBUG_H_MODE \
2324 && GET_MODE_CLASS (MODE) == MODE_INT \
2bcb2ab3
GK		 2325 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2326 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2370b831 2327 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2bcb2ab3
GK		 2328 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2329 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
7b2e1077 2330#endif
46299de9 2331/* The HI and LO registers can only be reloaded via the general
b8eb88d0
ILT		 2332 registers. Condition code registers can only be loaded to the
2333 general registers, and from the floating point registers. */
46299de9 2334
225b8835
ILT		 2335#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2336 mips_secondary_reload_class (CLASS, MODE, X, 1)
2337#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2338 mips_secondary_reload_class (CLASS, MODE, X, 0)
46299de9 2339
e75b25e7
MM		 2340/* Return the maximum number of consecutive registers
2341 needed to represent mode MODE in a register of class CLASS. */
2342
d604bca3 2343#define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
e75b25e7 2344
b0c42aed
JH		 2345#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2346 mips_cannot_change_mode_class (FROM, TO, CLASS)
e75b25e7
MM		 2347\f
2348/* Stack layout; function entry, exit and calling. */
2349
e75b25e7
MM		 2350#define STACK_GROWS_DOWNWARD
2351
f833ffd4
RS		 2352/* The offset of the first local variable from the beginning of the frame.
2353 See compute_frame_size for details about the frame layout. */
24e214e3
JW		 2354#define STARTING_FRAME_OFFSET \
2355 (current_function_outgoing_args_size \
f833ffd4
RS		 2356 + (TARGET_ABICALLS && !TARGET_NEWABI \
2357 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
ab78d4a8
MM		 2358
2359/* Offset from the stack pointer register to an item dynamically
2360 allocated on the stack, e.g., by `alloca'.
2361
2362 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2363 length of the outgoing arguments. The default is correct for most
2364 machines. See `function.c' for details.
2365
51bdc4d3
MM		 2366 The MIPS ABI states that functions which dynamically allocate the
2367 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2368 we are trying to create a second frame pointer to the function, so
2369 allocate some stack space to make it happy.
ab78d4a8 2370
51bdc4d3
MM		 2371 However, the linker currently complains about linking any code that
2372 dynamically allocates stack space, and there seems to be a bug in
2373 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2374
2375#if 0
ab78d4a8
MM		 2376#define STACK_DYNAMIC_OFFSET(FUNDECL) \
2377 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2378 ? 4*UNITS_PER_WORD \
2379 : current_function_outgoing_args_size)
51bdc4d3 2380#endif
e75b25e7 2381
ce3649d2 2382/* The return address for the current frame is in r31 if this is a leaf
39dffea3
JW		 2383 function. Otherwise, it is on the stack. It is at a variable offset
2384 from sp/fp/ap, so we define a fake hard register rap which is a
2385 poiner to the return address on the stack. This always gets eliminated
2386 during reload to be either the frame pointer or the stack pointer plus
2387 an offset. */
2388
cafe096b 2389#define RETURN_ADDR_RTX mips_return_addr
39dffea3 2390
7f48c9e1
AO		 2391/* Since the mips16 ISA mode is encoded in the least-significant bit
2392 of the address, mask it off return addresses for purposes of
2393 finding exception handling regions. */
2394
2395#define MASK_RETURN_ADDR GEN_INT (-2)
2396
cafe096b 2397
7f48c9e1
AO		 2398/* Similarly, don't use the least-significant bit to tell pointers to
2399 code from vtable index. */
2400
2401#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2402
ab78d4a8
MM		 2403/* If defined, this macro specifies a table of register pairs used to
2404 eliminate unneeded registers that point into the stack frame. If
2405 it is not defined, the only elimination attempted by the compiler
2406 is to replace references to the frame pointer with references to
2407 the stack pointer.
2408
2409 The definition of this macro is a list of structure
2410 initializations, each of which specifies an original and
2411 replacement register.
2412
2413 On some machines, the position of the argument pointer is not
2414 known until the compilation is completed. In such a case, a
7dac2f89 2415 separate hard register must be used for the argument pointer.
ab78d4a8
MM		 2416 This register can be eliminated by replacing it with either the
2417 frame pointer or the argument pointer, depending on whether or not
2418 the frame pointer has been eliminated.
2419
2420 In this case, you might specify:
2421 #define ELIMINABLE_REGS \
2422 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2423 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2424 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2425
2426 Note that the elimination of the argument pointer with the stack
2bcb2ab3
GK		 2427 pointer is specified first since that is the preferred elimination.
2428
2429 The eliminations to $17 are only used on the mips16. See the
2430 definition of HARD_FRAME_POINTER_REGNUM. */
ab78d4a8
MM		 2431
2432#define ELIMINABLE_REGS \
2433{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2bcb2ab3
GK		 2434 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2435 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2bcb2ab3
GK		 2436 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2437 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2438 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
ab78d4a8 2439
a0ab749a 2440/* A C expression that returns nonzero if the compiler is allowed to
ab78d4a8
MM		 2441 try to replace register number FROM-REG with register number
2442 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2443 defined, and will usually be the constant 1, since most of the
2444 cases preventing register elimination are things that the compiler
2bcb2ab3
GK		 2445 already knows about.
2446
365ca18b
GK		 2447 When not in mips16 and mips64, we can always eliminate to the
2448 frame pointer. We can eliminate to the stack pointer unless
2449 a frame pointer is needed. In mips16 mode, we need a frame
2450 pointer for a large frame; otherwise, reload may be unable
2451 to compute the address of a local variable, since there is
2452 no way to add a large constant to the stack pointer
2453 without using a temporary register.
2454
2455 In mips16, for some instructions (eg lwu), we can't eliminate the
2456 frame pointer for the stack pointer. These instructions are
2457 only generated in TARGET_64BIT mode.
2458 */
ab78d4a8
MM		 2459
2460#define CAN_ELIMINATE(FROM, TO) \
cafe096b 2461 (((TO) == HARD_FRAME_POINTER_REGNUM \
cfb773f9
AO		 2462 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2463 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2464 && (! TARGET_MIPS16 \
cafe096b 2465 || compute_frame_size (get_frame_size ()) < 32768))))
ab78d4a8 2466
b2471838
RS		 2467#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2468 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
ab78d4a8 2469
e75b25e7
MM		 2470/* If we generate an insn to push BYTES bytes,
2471 this says how many the stack pointer really advances by.
8aeea6e6 2472 On the VAX, sp@- in a byte insn really pushes a word. */
e75b25e7
MM		 2473
2474/* #define PUSH_ROUNDING(BYTES) 0 */
2475
2476/* If defined, the maximum amount of space required for outgoing
2477 arguments will be computed and placed into the variable
2478 `current_function_outgoing_args_size'. No space will be pushed
2479 onto the stack for each call; instead, the function prologue
2480 should increase the stack frame size by this amount.
2481
2482 It is not proper to define both `PUSH_ROUNDING' and
2483 `ACCUMULATE_OUTGOING_ARGS'. */
f73ad30e 2484#define ACCUMULATE_OUTGOING_ARGS 1
e75b25e7 2485
6cb6c3b3
MM		 2486/* Offset from the argument pointer register to the first argument's
2487 address. On some machines it may depend on the data type of the
2488 function.
e75b25e7 2489
6cb6c3b3 2490 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
39282292
MM		 2491 the first argument's address.
2492
2493 On the MIPS, we must skip the first argument position if we are
876c09d3 2494 returning a structure or a union, to account for its address being
305aa9e2
MM		 2495 passed in $4. However, at the current time, this produces a compiler
2496 that can't bootstrap, so comment it out for now. */
e75b25e7 2497
305aa9e2 2498#if 0
6cb6c3b3
MM		 2499#define FIRST_PARM_OFFSET(FNDECL) \
2500 (FNDECL != 0 \
2501 && TREE_TYPE (FNDECL) != 0 \
2502 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2503 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
39282292
MM		 2504 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2505 ? UNITS_PER_WORD \
2506 : 0)
305aa9e2
MM		 2507#else
2508#define FIRST_PARM_OFFSET(FNDECL) 0
2509#endif
e75b25e7
MM		 2510
2511/* When a parameter is passed in a register, stack space is still
2512 allocated for it. For the MIPS, stack space must be allocated, cf
2513 Asm Lang Prog Guide page 7-8.
2514
2515 BEWARE that some space is also allocated for non existing arguments
2516 in register. In case an argument list is of form GF used registers
2517 are a0 (a2,a3), but we should push over a1... */
2518
ac8ab9fe
RS		 2519#define REG_PARM_STACK_SPACE(FNDECL) \
2520 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2521 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2522 : 0)
e75b25e7
MM		 2523
2524/* Define this if it is the responsibility of the caller to
7dac2f89 2525 allocate the area reserved for arguments passed in registers.
e75b25e7 2526 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
7dac2f89 2527 of this macro is to determine whether the space is included in
e75b25e7
MM		 2528 `current_function_outgoing_args_size'. */
2529#define OUTGOING_REG_PARM_STACK_SPACE
2530
ac8ab9fe
RS		 2531#define STACK_BOUNDARY \
2532 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2533 ? 64 : 128)
e75b25e7 2534
876c09d3 2535/* Make sure 4 words are always allocated on the stack. */
e75b25e7
MM		 2536
2537#ifndef STACK_ARGS_ADJUST
2538#define STACK_ARGS_ADJUST(SIZE) \
2539{ \
876c09d3
JW		 2540 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2541 SIZE.constant = 4 * UNITS_PER_WORD; \
e75b25e7
MM		 2542}
2543#endif
2544
2545\f
2546/* A C expression that should indicate the number of bytes of its
38e01259 2547 own arguments that a function pops on returning, or 0
e75b25e7
MM		 2548 if the function pops no arguments and the caller must therefore
2549 pop them all after the function returns.
2550
8b109b37
RK		 2551 FUNDECL is the declaration node of the function (as a tree).
2552
e75b25e7
MM		 2553 FUNTYPE is a C variable whose value is a tree node that
2554 describes the function in question. Normally it is a node of
2555 type `FUNCTION_TYPE' that describes the data type of the function.
2556 From this it is possible to obtain the data types of the value
2557 and arguments (if known).
2558
2559 When a call to a library function is being considered, FUNTYPE
2560 will contain an identifier node for the library function. Thus,
2561 if you need to distinguish among various library functions, you
2562 can do so by their names. Note that "library function" in this
2563 context means a function used to perform arithmetic, whose name
2564 is known specially in the compiler and was not mentioned in the
2565 C code being compiled.
2566
2567 STACK-SIZE is the number of bytes of arguments passed on the
2568 stack. If a variable number of bytes is passed, it is zero, and
2569 argument popping will always be the responsibility of the
2570 calling function. */
2571
8b109b37 2572#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
e75b25e7
MM		 2573
2574
2575/* Symbolic macros for the registers used to return integer and floating
2576 point values. */
2577
2578#define GP_RETURN (GP_REG_FIRST + 2)
2579#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2580
ac8ab9fe
RS		 2581#define MAX_ARGS_IN_REGISTERS \
2582 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2583
2584/* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2585
2586#define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2587
e75b25e7
MM		 2588/* Symbolic macros for the first/last argument registers. */
2589
2590#define GP_ARG_FIRST (GP_REG_FIRST + 4)
ac8ab9fe 2591#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
e75b25e7 2592#define FP_ARG_FIRST (FP_REG_FIRST + 12)
ac8ab9fe 2593#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
e75b25e7
MM		 2594
2595/* Define how to find the value returned by a library function
2bcb2ab3
GK		 2596 assuming the value has mode MODE. Because we define
2597 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2598 PROMOTE_MODE does. */
e75b25e7 2599
c6e6f5c1
RH		 2600#define LIBCALL_VALUE(MODE) \
2601 mips_function_value (NULL_TREE, NULL, (MODE))
e75b25e7
MM		 2602
2603/* Define how to find the value returned by a function.
2604 VALTYPE is the data type of the value (as a tree).
2605 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2606 otherwise, FUNC is 0. */
2607
c6e6f5c1
RH		 2608#define FUNCTION_VALUE(VALTYPE, FUNC) \
2609 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
e75b25e7
MM		 2610
2611/* 1 if N is a possible register number for a function value.
2612 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2613 Currently, R2 and F0 are only implemented here (C has no complex type) */
2614
8a381273
AO		 2615#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2616 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2617 && (N) == FP_RETURN + 2))
e75b25e7 2618
46af8e31
JW		 2619/* 1 if N is a possible register number for function argument passing.
2620 We have no FP argument registers when soft-float. When FP registers
2621 are 32 bits, we can't directly reference the odd numbered ones. */
2622
2623#define FUNCTION_ARG_REGNO_P(N) \
8bf3ccbb
KG		 2624 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2625 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2626 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2627 && !fixed_regs[N])
e75b25e7
MM		 2628
2629/* A C expression which can inhibit the returning of certain function
2630 values in registers, based on the type of value. A nonzero value says
2631 to return the function value in memory, just as large structures are
2632 always returned. Here TYPE will be a C expression of type
2633 `tree', representing the data type of the value.
2634
e14fa9c4
DE		 2635 Note that values of mode `BLKmode' must be explicitly
2636 handled by this macro. Also, the option `-fpcc-struct-return'
e75b25e7
MM		 2637 takes effect regardless of this macro. On most systems, it is
2638 possible to leave the macro undefined; this causes a default
e14fa9c4
DE		 2639 definition to be used, whose value is the constant 1 for BLKmode
2640 values, and 0 otherwise.
e75b25e7
MM		 2641
2642 GCC normally converts 1 byte structures into chars, 2 byte
2643 structs into shorts, and 4 byte structs into ints, and returns
2644 them this way. Defining the following macro overrides this,
2645 to give us MIPS cc compatibility. */
2646
2647#define RETURN_IN_MEMORY(TYPE) \
54401342 2648 mips_return_in_memory (TYPE)
4d72536e
RS		 2649
2650#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2651 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2652 (TYPE), (NO_RTL))
e75b25e7 2653\f
ac8ab9fe
RS		 2654#define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2655
e75b25e7
MM		 2656/* Define a data type for recording info about an argument list
2657 during the scan of that argument list. This data type should
2658 hold all necessary information about the function itself
2659 and about the args processed so far, enough to enable macros
2660 such as FUNCTION_ARG to determine where the next arg should go.
2bcb2ab3 2661
4d72536e
RS		 2662 This structure has to cope with two different argument allocation
2663 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2664 first N words go in registers and the rest go on the stack. If I < N,
2665 the Ith word might go in Ith integer argument register or the
2666 Ith floating-point one. In some cases, it has to go in both (see
2667 function_arg). For these ABIs, we only need to remember the number
2668 of words passed so far.
2669
2670 The EABI instead allocates the integer and floating-point arguments
2671 separately. The first N words of FP arguments go in FP registers,
2672 the rest go on the stack. Likewise, the first N words of the other
2673 arguments go in integer registers, and the rest go on the stack. We
2674 need to maintain three counts: the number of integer registers used,
2675 the number of floating-point registers used, and the number of words
2676 passed on the stack.
2677
2678 We could keep separate information for the two ABIs (a word count for
2679 the standard ABIs, and three separate counts for the EABI). But it
2680 seems simpler to view the standard ABIs as forms of EABI that do not
2681 allocate floating-point registers.
2682
2683 So for the standard ABIs, the first N words are allocated to integer
2684 registers, and function_arg decides on an argument-by-argument basis
2685 whether that argument should really go in an integer register, or in
2686 a floating-point one. */
e75b25e7
MM		 2687
2688typedef struct mips_args {
4d72536e
RS		 2689 /* Always true for varargs functions. Otherwise true if at least
2690 one argument has been passed in an integer register. */
2691 int gp_reg_found;
2692
2693 /* The number of arguments seen so far. */
2694 unsigned int arg_number;
2695
2696 /* For EABI, the number of integer registers used so far. For other
2697 ABIs, the number of words passed in registers (whether integer
2698 or floating-point). */
bb63e5a0 2699 unsigned int num_gprs;
4d72536e
RS		 2700
2701 /* For EABI, the number of floating-point registers used so far. */
bb63e5a0 2702 unsigned int num_fprs;
4d72536e
RS		 2703
2704 /* The number of words passed on the stack. */
2705 unsigned int stack_words;
2706
2707 /* On the mips16, we need to keep track of which floating point
2708 arguments were passed in general registers, but would have been
2709 passed in the FP regs if this were a 32 bit function, so that we
2710 can move them to the FP regs if we wind up calling a 32 bit
2711 function. We record this information in fp_code, encoded in base
2712 four. A zero digit means no floating point argument, a one digit
2713 means an SFmode argument, and a two digit means a DFmode argument,
2714 and a three digit is not used. The low order digit is the first
2715 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2716 an SFmode argument. ??? A more sophisticated approach will be
2717 needed if MIPS_ABI != ABI_32. */
2718 int fp_code;
2719
2720 /* True if the function has a prototype. */
2721 int prototype;
2722
2723 /* When a structure does not take up a full register, the argument
2724 should sometimes be shifted left so that it occupies the high part
2725 of the register. These two fields describe an array of ashl
2726 patterns for doing this. See function_arg_advance, which creates
2727 the shift patterns, and function_arg, which returns them when given
2728 a VOIDmode argument. */
2729 unsigned int num_adjusts;
ac8ab9fe 2730 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
e75b25e7
MM		 2731} CUMULATIVE_ARGS;
2732
2733/* Initialize a variable CUM of type CUMULATIVE_ARGS
2734 for a call to a function whose data type is FNTYPE.
2735 For a library call, FNTYPE is 0.
2736
2737*/
2738
2c7ee1a6 2739#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
e75b25e7
MM		 2740 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2741
2742/* Update the data in CUM to advance over an argument
2743 of mode MODE and data type TYPE.
2744 (TYPE is null for libcalls where that information may not be available.) */
2745
2746#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2747 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2748
2749/* Determine where to put an argument to a function.
2750 Value is zero to push the argument on the stack,
2751 or a hard register in which to store the argument.
2752
2753 MODE is the argument's machine mode.
2754 TYPE is the data type of the argument (as a tree).
2755 This is null for libcalls where that information may
2756 not be available.
2757 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2758 the preceding args and about the function being called.
2759 NAMED is nonzero if this argument is a named parameter
2760 (otherwise it is an extra parameter matching an ellipsis). */
2761
2762#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2763 function_arg( &CUM, MODE, TYPE, NAMED)
2764
2765/* For an arg passed partly in registers and partly in memory,
2766 this is the number of registers used.
987ba558 2767 For args passed entirely in registers or entirely in memory, zero. */
e75b25e7
MM		 2768
2769#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2770 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2771
2772/* If defined, a C expression that gives the alignment boundary, in
2773 bits, of an argument with the specified mode and type. If it is
2774 not defined, `PARM_BOUNDARY' is used for all arguments. */
2775
2776#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2777 (((TYPE) != 0) \
75131237 2778 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
e75b25e7
MM		 2779 ? PARM_BOUNDARY \
2780 : TYPE_ALIGN(TYPE)) \
2781 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2782 ? PARM_BOUNDARY \
2783 : GET_MODE_ALIGNMENT(MODE)))
2784
ac8ab9fe
RS		 2785#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2786 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2787
2788#define FUNCTION_ARG_PADDING(MODE, TYPE) \
2789 (! BYTES_BIG_ENDIAN \
2790 ? upward \
2791 : (((MODE) == BLKmode \
2792 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2793 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2794 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2795 && (mips_abi == ABI_32 \
2796 || mips_abi == ABI_O64 \
2797 || mips_abi == ABI_EABI \
2798 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2799 ? downward : upward))
2800
2801#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2802 (mips_abi == ABI_EABI && (NAMED) \
2803 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2804
2805/* Modified version of the macro in expr.h. */
2806#define MUST_PASS_IN_STACK(MODE,TYPE) \
2807 ((TYPE) != 0 \
2808 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2809 || TREE_ADDRESSABLE (TYPE) \
2810 || ((MODE) == BLKmode \
2811 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2812 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2813 && 0 == (int_size_in_bytes (TYPE) \
2814 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2815 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2816 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2817
4d72536e
RS		 2818/* True if using EABI and varargs can be passed in floating-point
2819 registers. Under these conditions, we need a more complex form
2820 of va_list, which tracks GPR, FPR and stack arguments separately. */
2821#define EABI_FLOAT_VARARGS_P \
2822 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2823
e75b25e7 2824\f
cafe096b
EC		 2825/* Say that the epilogue uses the return address register. Note that
2826 in the case of sibcalls, the values "used by the epilogue" are
2827 considered live at the start of the called function. */
2828#define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2829
ac8ab9fe
RS		 2830/* Treat LOC as a byte offset from the stack pointer and round it up
2831 to the next fully-aligned offset. */
2832#define MIPS_STACK_ALIGN(LOC) \
2833 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2834 ? ((LOC) + 7) & ~7 \
2835 : ((LOC) + 15) & ~15)
e75b25e7 2836
5d3f2bd5
RH		 2837\f
2838/* Define the `__builtin_va_list' type for the ABI. */
2839#define BUILD_VA_LIST_TYPE(VALIST) \
2840 (VALIST) = mips_build_va_list ()
2841
2842/* Implement `va_start' for varargs and stdarg. */
e5faf155
ZW		 2843#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2844 mips_va_start (valist, nextarg)
5d3f2bd5
RH		 2845
2846/* Implement `va_arg'. */
2847#define EXPAND_BUILTIN_VA_ARG(valist, type) \
2848 mips_va_arg (valist, type)
e75b25e7
MM		 2849\f
2850/* Output assembler code to FILE to increment profiler label # LABELNO
2851 for profiling a function entry. */
2852
2853#define FUNCTION_PROFILER(FILE, LABELNO) \
2854{ \
2bcb2ab3
GK		 2855 if (TARGET_MIPS16) \
2856 sorry ("mips16 function profiling"); \
e75b25e7
MM		 2857 fprintf (FILE, "\t.set\tnoat\n"); \
2858 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2859 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
a0a89ed0
CD		 2860 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2861 { \
2862 fprintf (FILE, \
2863 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2864 TARGET_64BIT ? "dsubu" : "subu", \
2865 reg_names[STACK_POINTER_REGNUM], \
2866 reg_names[STACK_POINTER_REGNUM], \
2867 Pmode == DImode ? 16 : 8); \
2868 } \
0617ed52 2869 fprintf (FILE, "\tjal\t_mcount\n"); \
e75b25e7
MM		 2870 fprintf (FILE, "\t.set\tat\n"); \
2871}
2872
d8d5b1e1
MM		 2873/* Define this macro if the code for function profiling should come
2874 before the function prologue. Normally, the profiling code comes
2875 after. */
2876
2877/* #define PROFILE_BEFORE_PROLOGUE */
2878
e75b25e7
MM		 2879/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2880 the stack pointer does not matter. The value is tested only in
2881 functions that have frame pointers.
2882 No definition is equivalent to always zero. */
2883
2884#define EXIT_IGNORE_STACK 1
2885
2886\f
2887/* A C statement to output, on the stream FILE, assembler code for a
7dac2f89 2888 block of data that contains the constant parts of a trampoline.
e75b25e7
MM		 2889 This code should not include a label--the label is taken care of
2890 automatically. */
2891
2892#define TRAMPOLINE_TEMPLATE(STREAM) \
2893{ \
2894 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2895 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2896 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
cafe096b 2897 if (ptr_mode == DImode) \
876c09d3
JW		 2898 { \
2899 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2900 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2901 } \
2902 else \
2903 { \
0acefe54
JW		 2904 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2905 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
876c09d3 2906 } \
0acefe54 2907 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
e75b25e7
MM		 2908 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2909 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
cafe096b 2910 if (ptr_mode == DImode) \
876c09d3 2911 { \
876c09d3
JW		 2912 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2913 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2914 } \
2915 else \
2916 { \
2917 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2918 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2919 } \
e75b25e7
MM		 2920}
2921
2922/* A C expression for the size in bytes of the trampoline, as an
2923 integer. */
2924
cafe096b 2925#define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
e75b25e7 2926
876c09d3 2927/* Alignment required for trampolines, in bits. */
e75b25e7 2928
cafe096b 2929#define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
e75b25e7 2930
c85f7c16
JL		 2931/* INITIALIZE_TRAMPOLINE calls this library function to flush
2932 program and data caches. */
2933
2934#ifndef CACHE_FLUSH_FUNC
2935#define CACHE_FLUSH_FUNC "_flush_cache"
2936#endif
2937
7dac2f89 2938/* A C statement to initialize the variable parts of a trampoline.
e75b25e7
MM		 2939 ADDR is an RTX for the address of the trampoline; FNADDR is an
2940 RTX for the address of the nested function; STATIC_CHAIN is an
2941 RTX for the static chain value that should be passed to the
2942 function when it is called. */
2943
2944#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2945{ \
cafe096b
EC		 2946 rtx func_addr, chain_addr; \
2947 \
2948 func_addr = plus_constant (ADDR, 32); \
2949 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2950 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
2951 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
2952 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
2953 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
e75b25e7 2954 \
22b54c57
RK		 2955 /* Flush both caches. We need to flush the data cache in case \
2956 the system has a write-back cache. */ \
876c09d3 2957 /* ??? Should check the return value for errors. */ \
d490e8ad
DD		 2958 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2959 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
cafe096b 2960 0, VOIDmode, 3, ADDR, Pmode, \
d490e8ad
DD		 2961 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2962 GEN_INT (3), TYPE_MODE (integer_type_node)); \
e75b25e7 2963}
e75b25e7
MM		 2964\f
2965/* Addressing modes, and classification of registers for them. */
2966
e75b25e7
MM		 2967/* These assume that REGNO is a hard or pseudo reg number.
2968 They give nonzero only if REGNO is a hard reg of the suitable class
2969 or a pseudo reg currently allocated to a suitable hard reg.
2970 These definitions are NOT overridden anywhere. */
2971
2bcb2ab3
GK		 2972#define BASE_REG_P(regno, mode) \
2973 (TARGET_MIPS16 \
2974 ? (M16_REG_P (regno) \
2975 || (regno) == FRAME_POINTER_REGNUM \
2976 || (regno) == ARG_POINTER_REGNUM \
2977 || ((regno) == STACK_POINTER_REGNUM \
2978 && (GET_MODE_SIZE (mode) == 4 \
2979 || GET_MODE_SIZE (mode) == 8))) \
2980 : GP_REG_P (regno))
e75b25e7 2981
2bcb2ab3 2982#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
c3d03e3a 2983 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2bcb2ab3
GK		 2984 (mode))
2985
2986#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2987 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
e75b25e7 2988
876c09d3 2989#define REGNO_OK_FOR_INDEX_P(regno) 0
2bcb2ab3
GK		 2990#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2991 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
e75b25e7
MM		 2992
2993/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2994 and check its validity for a certain class.
2995 We have two alternate definitions for each of them.
2996 The usual definition accepts all pseudo regs; the other rejects them all.
2997 The symbol REG_OK_STRICT causes the latter definition to be used.
2998
2999 Most source files want to accept pseudo regs in the hope that
3000 they will get allocated to the class that the insn wants them to be in.
3001 Some source files that are used after register allocation
3002 need to be strict. */
3003
3004#ifndef REG_OK_STRICT
2bcb2ab3 3005#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
c94c9817 3006 mips_reg_mode_ok_for_base_p (X, MODE, 0)
e75b25e7 3007#else
2bcb2ab3 3008#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
c94c9817 3009 mips_reg_mode_ok_for_base_p (X, MODE, 1)
e75b25e7
MM		 3010#endif
3011
c94c9817
MM		 3012#define REG_OK_FOR_INDEX_P(X) 0
3013
e75b25e7
MM		 3014\f
3015/* Maximum number of registers that can appear in a valid memory address. */
3016
3017#define MAX_REGS_PER_ADDRESS 1
3018
3019/* A C compound statement with a conditional `goto LABEL;' executed
3020 if X (an RTX) is a legitimate memory address on the target
fb49053f 3021 machine for a memory operand of mode MODE. */
e75b25e7
MM		 3022
3023#if 1
bd9f1972
KG		 3024#define GO_PRINTF(x) fprintf(stderr, (x))
3025#define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
e75b25e7
MM		 3026#define GO_DEBUG_RTX(x) debug_rtx(x)
3027
3028#else
3029#define GO_PRINTF(x)
3030#define GO_PRINTF2(x,y)
3031#define GO_DEBUG_RTX(x)
3032#endif
3033
c94c9817
MM		 3034#ifdef REG_OK_STRICT
3035#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3036{ \
3037 if (mips_legitimate_address_p (MODE, X, 1)) \
3038 goto ADDR; \
e75b25e7 3039}
c94c9817
MM		 3040#else
3041#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3042{ \
3043 if (mips_legitimate_address_p (MODE, X, 0)) \
3044 goto ADDR; \
3045}
3046#endif
e75b25e7 3047
cafe096b
EC		 3048/* Check for constness inline but use mips_legitimate_address_p
3049 to check whether a constant really is an address. */
3050
3051#define CONSTANT_ADDRESS_P(X) \
3052 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
3053
e75b25e7
MM		 3054
3055/* Nonzero if the constant value X is a legitimate general operand.
3056 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3057
3058 At present, GAS doesn't understand li.[sd], so don't allow it
3059 to be generated at present. Also, the MIPS assembler does not
3060 grok li.d Infinity. */
3061
7dac2f89 3062/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
8e466531
GRK		 3063 Note that the Irix 6 assembler problem may already be fixed.
3064 Note also that the GET_CODE (X) == CONST test catches the mips16
3065 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3066 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3067 ABI_64 to work together, we'll need to fix this. */
cafe096b 3068#define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2649b2ee 3069
cafe096b
EC		 3070#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3071 do { \
3072 if (mips_legitimize_address (&(X), MODE)) \
3073 goto WIN; \
3074 } while (0)
e75b25e7
MM		 3075
3076
3077/* A C statement or compound statement with a conditional `goto
3078 LABEL;' executed if memory address X (an RTX) can have different
3079 meanings depending on the machine mode of the memory reference it
3080 is used for.
3081
3082 Autoincrement and autodecrement addresses typically have
3083 mode-dependent effects because the amount of the increment or
3084 decrement is the size of the operand being addressed. Some
3085 machines have other mode-dependent addresses. Many RISC machines
3086 have no mode-dependent addresses.
3087
3088 You may assume that ADDR is a valid address for the machine. */
3089
3090#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3091
9c9e7632
GK		 3092/* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3093 'the start of the function that this code is output in'. */
3094
3095#define ASM_OUTPUT_LABELREF(FILE,NAME) \
3096 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3097 asm_fprintf ((FILE), "%U%s", \
3098 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3099 else \
3100 asm_fprintf ((FILE), "%U%s", (NAME))
3101
2bcb2ab3
GK		 3102/* The mips16 wants the constant pool to be after the function,
3103 because the PC relative load instructions use unsigned offsets. */
3104
3105#define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3106
3107#define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3108 mips_string_length = 0;
e75b25e7
MM		 3109\f
3110/* Specify the machine mode that this machine uses
2bcb2ab3
GK		 3111 for the index in the tablejump instruction.
3112 ??? Using HImode in mips16 mode can cause overflow. However, the
3113 overflow is no more likely than the overflow in a branch
3114 instruction. Large functions can currently break in both ways. */
3115#define CASE_VECTOR_MODE \
cafe096b 3116 (TARGET_MIPS16 ? HImode : ptr_mode)
2bcb2ab3
GK		 3117
3118/* Define as C expression which evaluates to nonzero if the tablejump
3119 instruction expects the table to contain offsets from the address of the
3120 table.
987ba558 3121 Do not define this if the table should contain absolute addresses. */
2bcb2ab3 3122#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
e75b25e7 3123
e75b25e7 3124/* Define this as 1 if `char' should by default be signed; else as 0. */
6639753e 3125#ifndef DEFAULT_SIGNED_CHAR
e75b25e7 3126#define DEFAULT_SIGNED_CHAR 1
6639753e 3127#endif
e75b25e7
MM		 3128
3129/* Max number of bytes we can move from memory to memory
3130 in one reasonably fast instruction. */
876c09d3
JW		 3131#define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3132#define MAX_MOVE_MAX 8
e75b25e7
MM		 3133
3134/* Define this macro as a C expression which is nonzero if
3135 accessing less than a word of memory (i.e. a `char' or a
3136 `short') is no faster than accessing a word of memory, i.e., if
3137 such access require more than one instruction or if there is no
3138 difference in cost between byte and (aligned) word loads.
3139
3140 On RISC machines, it tends to generate better code to define
3141 this as 1, since it avoids making a QI or HI mode register. */
3142#define SLOW_BYTE_ACCESS 1
3143
d969caf8 3144/* Define this to be nonzero if shift instructions ignore all but the low-order
987ba558 3145 few bits. */
d969caf8 3146#define SHIFT_COUNT_TRUNCATED 1
e75b25e7
MM		 3147
3148/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3149 is done just by pretending it is already truncated. */
876c09d3
JW		 3150#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3151 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
e75b25e7 3152
cafe096b 3153
e75b25e7
MM		 3154/* Specify the machine mode that pointers have.
3155 After generation of rtl, the compiler makes no further distinction
cafe096b 3156 between pointers and any other objects of this machine mode. */
876c09d3 3157
1eeed24e 3158#ifndef Pmode
cafe096b 3159#define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
1eeed24e 3160#endif
e75b25e7 3161
cafe096b
EC		 3162/* Give call MEMs SImode since it is the "most permissive" mode
3163 for both 32-bit and 64-bit targets. */
e75b25e7 3164
cafe096b 3165#define FUNCTION_MODE SImode
e75b25e7 3166
e75b25e7 3167\f
cafe096b 3168/* The cost of loading values from the constant pool. It should be
f1ba665b 3169 larger than the cost of any constant we want to synthesize in-line. */
cafe096b
EC		 3170
3171#define CONSTANT_POOL_COST COSTS_N_INSNS (8)
3172
e75b25e7
MM		 3173/* A C expression for the cost of moving data from a register in
3174 class FROM to one in class TO. The classes are expressed using
3175 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3176 the default; other values are interpreted relative to that.
3177
3178 It is not required that the cost always equal 2 when FROM is the
3179 same as TO; on some machines it is expensive to move between
3180 registers if they are not general registers.
3181
3182 If reload sees an insn consisting of a single `set' between two
3183 hard registers, and if `REGISTER_MOVE_COST' applied to their
3184 classes returns a value of 2, reload does not check to ensure
3185 that the constraints of the insn are met. Setting a cost of
3186 other than 2 will allow reload to verify that the constraints are
3187 met. You should do this if the `movM' pattern's constraints do
d604bca3
MH		 3188 not allow such copying. */
3189
3190#define REGISTER_MOVE_COST(MODE, FROM, TO) \
3191 mips_register_move_cost (MODE, FROM, TO)
e75b25e7 3192
516a2dfd 3193/* ??? Fix this to be right for the R8000. */
cbd5b9a2 3194#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
7dac2f89 3195 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
cbd5b9a2 3196 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
876c09d3 3197
7506f491
DE		 3198/* Define if copies to/from condition code registers should be avoided.
3199
3200 This is needed for the MIPS because reload_outcc is not complete;
3201 it needs to handle cases where the source is a general or another
3202 condition code register. */
3203#define AVOID_CCMODE_COPIES
3204
e75b25e7
MM		 3205/* A C expression for the cost of a branch instruction. A value of
3206 1 is the default; other values are interpreted relative to that. */
3207
516a2dfd 3208/* ??? Fix this to be right for the R8000. */
2bcb2ab3
GK		 3209#define BRANCH_COST \
3210 ((! TARGET_MIPS16 \
7dac2f89 3211 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2bcb2ab3 3212 ? 2 : 1)
e75b25e7 3213
0ff83799
MM		 3214/* If defined, modifies the length assigned to instruction INSN as a
3215 function of the context in which it is used. LENGTH is an lvalue
3216 that contains the initially computed length of the insn and should
3217 be updated with the correct length of the insn. */
3218#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3219 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3220
e75b25e7
MM		 3221\f
3222/* Optionally define this if you have added predicates to
3223 `MACHINE.c'. This macro is called within an initializer of an
3224 array of structures. The first field in the structure is the
31c714e3 3225 name of a predicate and the second field is an array of rtl
e75b25e7
MM		 3226 codes. For each predicate, list all rtl codes that can be in
3227 expressions matched by the predicate. The list should have a
3228 trailing comma. Here is an example of two entries in the list
3229 for a typical RISC machine:
3230
3231 #define PREDICATE_CODES \
3232 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3233 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3234
3235 Defining this macro does not affect the generated code (however,
3236 incorrect definitions that omit an rtl code that may be matched
7dac2f89 3237 by the predicate can cause the compiler to malfunction).
e75b25e7
MM		 3238 Instead, it allows the table built by `genrecog' to be more
3239 compact and efficient, thus speeding up the compiler. The most
3240 important predicates to include in the list specified by this
3241 macro are thoses used in the most insn patterns. */
3242
3243#define PREDICATE_CODES \
98c29f71 3244 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
cafe096b
EC		 3245 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
3246 {"const_arith_operand", { CONST, CONST_INT }}, \
3247 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
3248 {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3249 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3250 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
e75b25e7
MM		 3251 {"small_int", { CONST_INT }}, \
3252 {"large_int", { CONST_INT }}, \
e75b25e7 3253 {"mips_const_double_ok", { CONST_DOUBLE }}, \
b8eb88d0 3254 {"const_float_1_operand", { CONST_DOUBLE }}, \
e75b25e7 3255 {"simple_memory_operand", { MEM, SUBREG }}, \
e75b25e7
MM		 3256 {"equality_op", { EQ, NE }}, \
3257 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3258 LTU, LEU }}, \
a0b6cdee 3259 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
f8634644 3260 {"pc_or_label_operand", { PC, LABEL_REF }}, \
cafe096b 3261 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
ce57d6f4
JW		 3262 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3263 SYMBOL_REF, LABEL_REF, SUBREG, \
cafe096b 3264 REG, MEM}}, \
2bcb2ab3 3265 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
cb923660 3266 CONST_DOUBLE, CONST }}, \
21c9500d 3267 {"fcc_register_operand", { REG, SUBREG }}, \
d334c3c1
RS		 3268 {"hilo_operand", { REG }}, \
3269 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
cb923660 3270
0e7e9155
RH		 3271/* A list of predicates that do special things with modes, and so
3272 should not elicit warnings for VOIDmode match_operand. */
3273
3274#define SPECIAL_MODE_PREDICATES \
3275 "pc_or_label_operand",
e75b25e7
MM		 3276\f
3277/* Control the assembler format that we output. */
3278
e75b25e7
MM		 3279/* Output to assembler file text saying following lines
3280 may contain character constants, extra white space, comments, etc. */
3281
b2bcb32d 3282#ifndef ASM_APP_ON
e75b25e7 3283#define ASM_APP_ON " #APP\n"
b2bcb32d 3284#endif
e75b25e7
MM		 3285
3286/* Output to assembler file text saying following lines
3287 no longer contain unusual constructs. */
3288
b2bcb32d 3289#ifndef ASM_APP_OFF
e75b25e7 3290#define ASM_APP_OFF " #NO_APP\n"
b2bcb32d 3291#endif
e75b25e7
MM		 3292
3293/* How to refer to registers in assembler output.
3294 This sequence is indexed by compiler's hard-register-number (see above).
3295
3296 In order to support the two different conventions for register names,
3297 we use the name of a table set up in mips.c, which is overwritten
3298 if -mrnames is used. */
3299
3300#define REGISTER_NAMES \
3301{ \
3302 &mips_reg_names[ 0][0], \
3303 &mips_reg_names[ 1][0], \
3304 &mips_reg_names[ 2][0], \
3305 &mips_reg_names[ 3][0], \
3306 &mips_reg_names[ 4][0], \
3307 &mips_reg_names[ 5][0], \
3308 &mips_reg_names[ 6][0], \
3309 &mips_reg_names[ 7][0], \
3310 &mips_reg_names[ 8][0], \
3311 &mips_reg_names[ 9][0], \
3312 &mips_reg_names[10][0], \
3313 &mips_reg_names[11][0], \
3314 &mips_reg_names[12][0], \
3315 &mips_reg_names[13][0], \
3316 &mips_reg_names[14][0], \
3317 &mips_reg_names[15][0], \
3318 &mips_reg_names[16][0], \
3319 &mips_reg_names[17][0], \
3320 &mips_reg_names[18][0], \
3321 &mips_reg_names[19][0], \
3322 &mips_reg_names[20][0], \
3323 &mips_reg_names[21][0], \
3324 &mips_reg_names[22][0], \
3325 &mips_reg_names[23][0], \
3326 &mips_reg_names[24][0], \
3327 &mips_reg_names[25][0], \
3328 &mips_reg_names[26][0], \
3329 &mips_reg_names[27][0], \
3330 &mips_reg_names[28][0], \
3331 &mips_reg_names[29][0], \
3332 &mips_reg_names[30][0], \
3333 &mips_reg_names[31][0], \
3334 &mips_reg_names[32][0], \
3335 &mips_reg_names[33][0], \
3336 &mips_reg_names[34][0], \
3337 &mips_reg_names[35][0], \
3338 &mips_reg_names[36][0], \
3339 &mips_reg_names[37][0], \
3340 &mips_reg_names[38][0], \
3341 &mips_reg_names[39][0], \
3342 &mips_reg_names[40][0], \
3343 &mips_reg_names[41][0], \
3344 &mips_reg_names[42][0], \
3345 &mips_reg_names[43][0], \
3346 &mips_reg_names[44][0], \
3347 &mips_reg_names[45][0], \
3348 &mips_reg_names[46][0], \
3349 &mips_reg_names[47][0], \
3350 &mips_reg_names[48][0], \
3351 &mips_reg_names[49][0], \
3352 &mips_reg_names[50][0], \
3353 &mips_reg_names[51][0], \
3354 &mips_reg_names[52][0], \
3355 &mips_reg_names[53][0], \
3356 &mips_reg_names[54][0], \
3357 &mips_reg_names[55][0], \
3358 &mips_reg_names[56][0], \
3359 &mips_reg_names[57][0], \
3360 &mips_reg_names[58][0], \
3361 &mips_reg_names[59][0], \
3362 &mips_reg_names[60][0], \
3363 &mips_reg_names[61][0], \
3364 &mips_reg_names[62][0], \
3365 &mips_reg_names[63][0], \
3366 &mips_reg_names[64][0], \
3367 &mips_reg_names[65][0], \
3368 &mips_reg_names[66][0], \
225b8835 3369 &mips_reg_names[67][0], \
39dffea3 3370 &mips_reg_names[68][0], \
b8eb88d0
ILT		 3371 &mips_reg_names[69][0], \
3372 &mips_reg_names[70][0], \
3373 &mips_reg_names[71][0], \
3374 &mips_reg_names[72][0], \
3375 &mips_reg_names[73][0], \
3376 &mips_reg_names[74][0], \
3377 &mips_reg_names[75][0], \
d604bca3
MH		 3378 &mips_reg_names[76][0], \
3379 &mips_reg_names[77][0], \
3380 &mips_reg_names[78][0], \
3381 &mips_reg_names[79][0], \
3382 &mips_reg_names[80][0], \
3383 &mips_reg_names[81][0], \
3384 &mips_reg_names[82][0], \
3385 &mips_reg_names[83][0], \
3386 &mips_reg_names[84][0], \
3387 &mips_reg_names[85][0], \
3388 &mips_reg_names[86][0], \
3389 &mips_reg_names[87][0], \
3390 &mips_reg_names[88][0], \
3391 &mips_reg_names[89][0], \
3392 &mips_reg_names[90][0], \
3393 &mips_reg_names[91][0], \
3394 &mips_reg_names[92][0], \
3395 &mips_reg_names[93][0], \
3396 &mips_reg_names[94][0], \
3397 &mips_reg_names[95][0], \
3398 &mips_reg_names[96][0], \
3399 &mips_reg_names[97][0], \
3400 &mips_reg_names[98][0], \
3401 &mips_reg_names[99][0], \
3402 &mips_reg_names[100][0], \
3403 &mips_reg_names[101][0], \
3404 &mips_reg_names[102][0], \
3405 &mips_reg_names[103][0], \
3406 &mips_reg_names[104][0], \
3407 &mips_reg_names[105][0], \
3408 &mips_reg_names[106][0], \
3409 &mips_reg_names[107][0], \
3410 &mips_reg_names[108][0], \
3411 &mips_reg_names[109][0], \
3412 &mips_reg_names[110][0], \
3413 &mips_reg_names[111][0], \
3414 &mips_reg_names[112][0], \
3415 &mips_reg_names[113][0], \
3416 &mips_reg_names[114][0], \
3417 &mips_reg_names[115][0], \
3418 &mips_reg_names[116][0], \
3419 &mips_reg_names[117][0], \
3420 &mips_reg_names[118][0], \
3421 &mips_reg_names[119][0], \
3422 &mips_reg_names[120][0], \
3423 &mips_reg_names[121][0], \
3424 &mips_reg_names[122][0], \
3425 &mips_reg_names[123][0], \
3426 &mips_reg_names[124][0], \
3427 &mips_reg_names[125][0], \
3428 &mips_reg_names[126][0], \
3429 &mips_reg_names[127][0], \
3430 &mips_reg_names[128][0], \
3431 &mips_reg_names[129][0], \
3432 &mips_reg_names[130][0], \
3433 &mips_reg_names[131][0], \
3434 &mips_reg_names[132][0], \
3435 &mips_reg_names[133][0], \
3436 &mips_reg_names[134][0], \
3437 &mips_reg_names[135][0], \
3438 &mips_reg_names[136][0], \
3439 &mips_reg_names[137][0], \
3440 &mips_reg_names[138][0], \
3441 &mips_reg_names[139][0], \
3442 &mips_reg_names[140][0], \
3443 &mips_reg_names[141][0], \
3444 &mips_reg_names[142][0], \
3445 &mips_reg_names[143][0], \
3446 &mips_reg_names[144][0], \
3447 &mips_reg_names[145][0], \
3448 &mips_reg_names[146][0], \
3449 &mips_reg_names[147][0], \
3450 &mips_reg_names[148][0], \
3451 &mips_reg_names[149][0], \
3452 &mips_reg_names[150][0], \
3453 &mips_reg_names[151][0], \
3454 &mips_reg_names[152][0], \
3455 &mips_reg_names[153][0], \
3456 &mips_reg_names[154][0], \
3457 &mips_reg_names[155][0], \
3458 &mips_reg_names[156][0], \
3459 &mips_reg_names[157][0], \
3460 &mips_reg_names[158][0], \
3461 &mips_reg_names[159][0], \
3462 &mips_reg_names[160][0], \
3463 &mips_reg_names[161][0], \
3464 &mips_reg_names[162][0], \
3465 &mips_reg_names[163][0], \
3466 &mips_reg_names[164][0], \
3467 &mips_reg_names[165][0], \
3468 &mips_reg_names[166][0], \
3469 &mips_reg_names[167][0], \
3470 &mips_reg_names[168][0], \
3471 &mips_reg_names[169][0], \
3472 &mips_reg_names[170][0], \
3473 &mips_reg_names[171][0], \
3474 &mips_reg_names[172][0], \
3475 &mips_reg_names[173][0], \
3476 &mips_reg_names[174][0], \
3477 &mips_reg_names[175][0] \
e75b25e7
MM		 3478}
3479
46cca58c
RS		 3480/* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3481 So define this for it. */
3482#define DEBUG_REGISTER_NAMES \
3483{ \
3484 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3485 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3486 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
07e2e444 3487 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
46cca58c
RS		 3488 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3489 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3490 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3491 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
d334c3c1 3492 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
d604bca3
MH		 3493 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3494 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3495 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3496 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3497 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3498 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3499 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3500 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3501 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3502 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3503 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3504 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3505 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
46cca58c
RS		 3506}
3507
e75b25e7
MM		 3508/* If defined, a C initializer for an array of structures
3509 containing a name and a register number. This macro defines
3510 additional names for hard registers, thus allowing the `asm'
3511 option in declarations to refer to registers using alternate
3512 names.
3513
3514 We define both names for the integer registers here. */
3515
3516#define ADDITIONAL_REGISTER_NAMES \
3517{ \
3518 { "$0", 0 + GP_REG_FIRST }, \
3519 { "$1", 1 + GP_REG_FIRST }, \
3520 { "$2", 2 + GP_REG_FIRST }, \
3521 { "$3", 3 + GP_REG_FIRST }, \
3522 { "$4", 4 + GP_REG_FIRST }, \
3523 { "$5", 5 + GP_REG_FIRST }, \
3524 { "$6", 6 + GP_REG_FIRST }, \
3525 { "$7", 7 + GP_REG_FIRST }, \
3526 { "$8", 8 + GP_REG_FIRST }, \
3527 { "$9", 9 + GP_REG_FIRST }, \
3528 { "$10", 10 + GP_REG_FIRST }, \
3529 { "$11", 11 + GP_REG_FIRST }, \
3530 { "$12", 12 + GP_REG_FIRST }, \
3531 { "$13", 13 + GP_REG_FIRST }, \
3532 { "$14", 14 + GP_REG_FIRST }, \
3533 { "$15", 15 + GP_REG_FIRST }, \
3534 { "$16", 16 + GP_REG_FIRST }, \
3535 { "$17", 17 + GP_REG_FIRST }, \
3536 { "$18", 18 + GP_REG_FIRST }, \
3537 { "$19", 19 + GP_REG_FIRST }, \
3538 { "$20", 20 + GP_REG_FIRST }, \
3539 { "$21", 21 + GP_REG_FIRST }, \
3540 { "$22", 22 + GP_REG_FIRST }, \
3541 { "$23", 23 + GP_REG_FIRST }, \
3542 { "$24", 24 + GP_REG_FIRST }, \
3543 { "$25", 25 + GP_REG_FIRST }, \
3544 { "$26", 26 + GP_REG_FIRST }, \
3545 { "$27", 27 + GP_REG_FIRST }, \
3546 { "$28", 28 + GP_REG_FIRST }, \
3547 { "$29", 29 + GP_REG_FIRST }, \
3548 { "$30", 30 + GP_REG_FIRST }, \
3549 { "$31", 31 + GP_REG_FIRST }, \
3550 { "$sp", 29 + GP_REG_FIRST }, \
3551 { "$fp", 30 + GP_REG_FIRST }, \
3552 { "at", 1 + GP_REG_FIRST }, \
3553 { "v0", 2 + GP_REG_FIRST }, \
3554 { "v1", 3 + GP_REG_FIRST }, \
3555 { "a0", 4 + GP_REG_FIRST }, \
3556 { "a1", 5 + GP_REG_FIRST }, \
3557 { "a2", 6 + GP_REG_FIRST }, \
3558 { "a3", 7 + GP_REG_FIRST }, \
3559 { "t0", 8 + GP_REG_FIRST }, \
3560 { "t1", 9 + GP_REG_FIRST }, \
3561 { "t2", 10 + GP_REG_FIRST }, \
3562 { "t3", 11 + GP_REG_FIRST }, \
3563 { "t4", 12 + GP_REG_FIRST }, \
3564 { "t5", 13 + GP_REG_FIRST }, \
3565 { "t6", 14 + GP_REG_FIRST }, \
3566 { "t7", 15 + GP_REG_FIRST }, \
3567 { "s0", 16 + GP_REG_FIRST }, \
3568 { "s1", 17 + GP_REG_FIRST }, \
3569 { "s2", 18 + GP_REG_FIRST }, \
3570 { "s3", 19 + GP_REG_FIRST }, \
3571 { "s4", 20 + GP_REG_FIRST }, \
3572 { "s5", 21 + GP_REG_FIRST }, \
3573 { "s6", 22 + GP_REG_FIRST }, \
3574 { "s7", 23 + GP_REG_FIRST }, \
3575 { "t8", 24 + GP_REG_FIRST }, \
3576 { "t9", 25 + GP_REG_FIRST }, \
3577 { "k0", 26 + GP_REG_FIRST }, \
3578 { "k1", 27 + GP_REG_FIRST }, \
3579 { "gp", 28 + GP_REG_FIRST }, \
3580 { "sp", 29 + GP_REG_FIRST }, \
3581 { "fp", 30 + GP_REG_FIRST }, \
3582 { "ra", 31 + GP_REG_FIRST }, \
924706a0 3583 { "$sp", 29 + GP_REG_FIRST }, \
b8eb88d0 3584 { "$fp", 30 + GP_REG_FIRST } \
d604bca3 3585 ALL_COP_ADDITIONAL_REGISTER_NAMES \
e75b25e7
MM		 3586}
3587
33005162 3588/* This is meant to be redefined in the host dependent files. It is a
d604bca3
MH		 3589 set of alternative names and regnums for mips coprocessors. */
3590
3591#define ALL_COP_ADDITIONAL_REGISTER_NAMES
3592
e75b25e7
MM		 3593/* A C compound statement to output to stdio stream STREAM the
3594 assembler syntax for an instruction operand X. X is an RTL
3595 expression.
3596
3597 CODE is a value that can be used to specify one of several ways
3598 of printing the operand. It is used when identical operands
3599 must be printed differently depending on the context. CODE
3600 comes from the `%' specification that was used to request
3601 printing of the operand. If the specification was just `%DIGIT'
3602 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3603 is the ASCII code for LTR.
3604
3605 If X is a register, this macro should print the register's name.
3606 The names can be found in an array `reg_names' whose type is
3607 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3608
3609 When the machine description has a specification `%PUNCT' (a `%'
3610 followed by a punctuation character), this macro is called with
3611 a null pointer for X and the punctuation character for CODE.
3612
3613 See mips.c for the MIPS specific codes. */
3614
3615#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3616
3617/* A C expression which evaluates to true if CODE is a valid
3618 punctuation character for use in the `PRINT_OPERAND' macro. If
3619 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3620 punctuation characters (except for the standard one, `%') are
3621 used in this way. */
3622
3623#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3624
3625/* A C compound statement to output to stdio stream STREAM the
3626 assembler syntax for an instruction operand that is a memory
fb49053f 3627 reference whose address is ADDR. ADDR is an RTL expression. */
e75b25e7
MM		 3628
3629#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3630
3631
3632/* A C statement, to be executed after all slot-filler instructions
3633 have been output. If necessary, call `dbr_sequence_length' to
3634 determine the number of slots filled in a sequence (zero if not
3635 currently outputting a sequence), to decide how many no-ops to
3636 output, or whatever.
3637
3638 Don't define this macro if it has nothing to do, but it is
3639 helpful in reading assembly output if the extent of the delay
3640 sequence is made explicit (e.g. with white space).
3641
3642 Note that output routines for instructions with delay slots must
3643 be prepared to deal with not being output as part of a sequence
3644 (i.e. when the scheduling pass is not run, or when no slot
3645 fillers could be found.) The variable `final_sequence' is null
3646 when not processing a sequence, otherwise it contains the
3647 `sequence' rtx being output. */
3648
3649#define DBR_OUTPUT_SEQEND(STREAM) \
3650do \
3651 { \
3652 if (set_nomacro > 0 && --set_nomacro == 0) \
3653 fputs ("\t.set\tmacro\n", STREAM); \
3654 \
3655 if (set_noreorder > 0 && --set_noreorder == 0) \
3656 fputs ("\t.set\treorder\n", STREAM); \
3657 \
e75b25e7
MM		 3658 fputs ("\n", STREAM); \
3659 } \
3660while (0)
3661
3662
3663/* How to tell the debugger about changes of source files. Note, the
3664 mips ECOFF format cannot deal with changes of files inside of
3665 functions, which means the output of parser generators like bison
3666 is generally not debuggable without using the -l switch. Lose,
3667 lose, lose. Silicon graphics seems to want all .file's hardwired
3668 to 1. */
3669
3670#ifndef SET_FILE_NUMBER
3671#define SET_FILE_NUMBER() ++num_source_filenames
3672#endif
3673
3674#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3675 mips_output_filename (STREAM, NAME)
3676
ddd5a7c1 3677/* This is defined so that it can be overridden in iris6.h. */
516a2dfd
JW		 3678#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3679do \
3680 { \
3681 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3682 output_quoted_string (STREAM, NAME); \
3683 fputs ("\n", STREAM); \
3684 } \
3685while (0)
3686
e75b25e7
MM		 3687/* This is how to output a note the debugger telling it the line number
3688 to which the following sequence of instructions corresponds.
3689 Silicon graphics puts a label after each .loc. */
3690
3691#ifndef LABEL_AFTER_LOC
3692#define LABEL_AFTER_LOC(STREAM)
3693#endif
3694
b2bcb32d 3695#ifndef ASM_OUTPUT_SOURCE_LINE
a8d0467e 3696#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
e75b25e7 3697 mips_output_lineno (STREAM, LINE)
b2bcb32d 3698#endif
e75b25e7 3699
9ec36da5 3700/* The MIPS implementation uses some labels for its own purpose. The
e75b25e7
MM		 3701 following lists what labels are created, and are all formed by the
3702 pattern $L[a-z].*. The machine independent portion of GCC creates
3703 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3704
c5b7917e 3705 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
e75b25e7
MM		 3706 $Lb[0-9]+ Begin blocks for MIPS debug support
3707 $Lc[0-9]+ Label for use in s<xx> operation.
33005162 3708 $Le[0-9]+ End blocks for MIPS debug support */
e75b25e7 3709
31c714e3
MM		 3710/* A C statement (sans semicolon) to output to the stdio stream
3711 STREAM any text necessary for declaring the name NAME of an
3712 initialized variable which is being defined. This macro must
7dac2f89 3713 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
31c714e3
MM		 3714 The argument DECL is the `VAR_DECL' tree node representing the
3715 variable.
3716
3717 If this macro is not defined, then the variable name is defined
3718 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3719
44404b8b 3720#undef ASM_DECLARE_OBJECT_NAME
31c714e3 3721#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
f3b39eba
MM		 3722do \
3723 { \
3724 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
f3b39eba
MM		 3725 } \
3726while (0)
31c714e3 3727
506a61b1
KG		 3728/* Globalizing directive for a label. */
3729#define GLOBAL_ASM_OP "\t.globl\t"
e75b25e7 3730
31c714e3 3731/* This says how to define a global common symbol. */
e75b25e7 3732
919509ce
DN		 3733#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3734 do { \
3735 /* If the target wants uninitialized const declarations in \
3736 .rdata then don't put them in .comm */ \
3737 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3738 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3739 && (DECL_INITIAL (DECL) == 0 \
3740 || DECL_INITIAL (DECL) == error_mark_node)) \
3741 { \
3742 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
5eb99654 3743 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
919509ce 3744 \
d48bc59a 3745 readonly_data_section (); \
919509ce
DN		 3746 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3747 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3748 (SIZE)); \
3749 } \
3750 else \
d239cdc0 3751 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
919509ce
DN		 3752 (SIZE)); \
3753 } while (0)
3754
e75b25e7 3755
c5b7917e 3756/* This says how to define a local common symbol (ie, not visible to
31c714e3 3757 linker). */
e75b25e7
MM		 3758
3759#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
58e15542 3760 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
e75b25e7
MM		 3761
3762
3763/* This says how to output an external. It would be possible not to
3764 output anything and let undefined symbol become external. However
3765 the assembler uses length information on externals to allocate in
3766 data/sdata bss/sbss, thereby saving exec time. */
3767
3768#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3769 mips_output_external(STREAM,DECL,NAME)
3770
f99ffb60 3771
e75b25e7
MM		 3772/* This is how to declare a function name. The actual work of
3773 emitting the label is moved to function_prologue, so that we can
3774 get the line number correctly emitted before the .ent directive,
789b7de5 3775 and after any .file directives. Define as empty so that the function
4e314d1f
EC		 3776 is not declared before the .ent directive elsewhere. */
3777
44404b8b 3778#undef ASM_DECLARE_FUNCTION_NAME
33005162 3779#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4e314d1f 3780
e75b25e7
MM		 3781/* This is how to store into the string LABEL
3782 the symbol_ref name of an internal numbered label where
3783 PREFIX is the class of label and NUM is the number within the class.
3784 This is suitable for output with `assemble_name'. */
3785
44404b8b 3786#undef ASM_GENERATE_INTERNAL_LABEL
e75b25e7 3787#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4f70758f 3788 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
e75b25e7 3789
e75b25e7
MM		 3790/* This is how to output an element of a case-vector that is absolute. */
3791
3792#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
6ae1498b 3793 fprintf (STREAM, "\t%s\t%sL%d\n", \
cafe096b 3794 ptr_mode == DImode ? ".dword" : ".word", \
6ae1498b 3795 LOCAL_LABEL_PREFIX, \
876c09d3 3796 VALUE)
e75b25e7
MM		 3797
3798/* This is how to output an element of a case-vector that is relative.
e0bfcea5
ILT		 3799 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3800 TARGET_EMBEDDED_PIC). */
e75b25e7 3801
33f7f353 3802#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
e0bfcea5 3803do { \
2bcb2ab3
GK		 3804 if (TARGET_MIPS16) \
3805 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3806 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3807 else if (TARGET_EMBEDDED_PIC) \
6ae1498b 3808 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
cafe096b 3809 ptr_mode == DImode ? ".dword" : ".word", \
6ae1498b 3810 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
cafe096b 3811 else if (TARGET_GPWORD) \
6ae1498b 3812 fprintf (STREAM, "\t%s\t%sL%d\n", \
cafe096b 3813 ptr_mode == DImode ? ".gpdword" : ".gpword", \
6ae1498b 3814 LOCAL_LABEL_PREFIX, VALUE); \
516a2dfd 3815 else \
b2d8cf33 3816 fprintf (STREAM, "\t%s\t%sL%d\n", \
cafe096b 3817 ptr_mode == DImode ? ".dword" : ".word", \
b2d8cf33 3818 LOCAL_LABEL_PREFIX, VALUE); \
e0bfcea5
ILT		 3819} while (0)
3820
2bcb2ab3
GK		 3821/* When generating embedded PIC or mips16 code we want to put the jump
3822 table in the .text section. In all other cases, we want to put the
3823 jump table in the .rdata section. Unfortunately, we can't use
e0bfcea5
ILT		 3824 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3825 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3826 section if appropriate. */
44404b8b 3827#undef ASM_OUTPUT_CASE_LABEL
e0bfcea5
ILT		 3828#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3829do { \
2bcb2ab3
GK		 3830 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3831 function_section (current_function_decl); \
4977bab6 3832 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
e0bfcea5 3833} while (0)
e75b25e7
MM		 3834
3835/* This is how to output an assembler line
3836 that says to advance the location counter
3837 to a multiple of 2**LOG bytes. */
3838
3839#define ASM_OUTPUT_ALIGN(STREAM,LOG) \
a688e0b7 3840 fprintf (STREAM, "\t.align\t%d\n", (LOG))
e75b25e7 3841
38e01259 3842/* This is how to output an assembler line to advance the location
e75b25e7
MM		 3843 counter by SIZE bytes. */
3844
44404b8b 3845#undef ASM_OUTPUT_SKIP
e75b25e7 3846#define ASM_OUTPUT_SKIP(STREAM,SIZE) \
c394cdb7 3847 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
e75b25e7 3848
e75b25e7 3849/* This is how to output a string. */
44404b8b 3850#undef ASM_OUTPUT_ASCII
e75b25e7 3851#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
b3276c7a 3852 mips_output_ascii (STREAM, STRING, LEN)
e75b25e7 3853
e75b25e7 3854/* Output #ident as a in the read-only data section. */
0e5a4ad8 3855#undef ASM_OUTPUT_IDENT
e75b25e7
MM		 3856#define ASM_OUTPUT_IDENT(FILE, STRING) \
3857{ \
3cce094d 3858 const char *p = STRING; \
e75b25e7 3859 int size = strlen (p) + 1; \
d48bc59a 3860 readonly_data_section (); \
e75b25e7
MM		 3861 assemble_string (p, size); \
3862}
3863\f
b82b0773
MM		 3864/* Default to -G 8 */
3865#ifndef MIPS_DEFAULT_GVALUE
3866#define MIPS_DEFAULT_GVALUE 8
3867#endif
e75b25e7 3868
f3b39eba
MM		 3869/* Define the strings to put out for each section in the object file. */
3870#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3871#define DATA_SECTION_ASM_OP "\t.data" /* large data */
3872#define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
2017ed61
EC		 3873
3874#undef READONLY_DATA_SECTION_ASM_OP
d48bc59a 3875#define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2017ed61 3876
3cf6400d 3877#define SMALL_DATA_SECTION sdata_section
e75b25e7
MM		 3878
3879/* What other sections we support other than the normal .data/.text. */
3880
44404b8b 3881#undef EXTRA_SECTIONS
d48bc59a 3882#define EXTRA_SECTIONS in_sdata
e75b25e7
MM		 3883
3884/* Define the additional functions to select our additional sections. */
3885
3886/* on the MIPS it is not a good idea to put constants in the text
3887 section, since this defeats the sdata/data mechanism. This is
3888 especially true when -O is used. In this case an effort is made to
3889 address with faster (gp) register relative addressing, which can
3890 only get at sdata and sbss items (there is no stext !!) However,
3891 if the constant is too large for sdata, and it's readonly, it
987ba558 3892 will go into the .rdata section. */
e75b25e7 3893
44404b8b 3894#undef EXTRA_SECTION_FUNCTIONS
e75b25e7
MM		 3895#define EXTRA_SECTION_FUNCTIONS \
3896void \
3897sdata_section () \
3898{ \
3899 if (in_section != in_sdata) \
3900 { \
3901 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3902 in_section = in_sdata; \
3903 } \
e75b25e7
MM		 3904}
3905
3906/* Given a decl node or constant node, choose the section to output it in
3907 and select that section. */
3908
ae46c4e0
RH		 3909#undef TARGET_ASM_SELECT_SECTION
3910#define TARGET_ASM_SELECT_SECTION mips_select_section
e75b25e7 3911\f
e75b25e7
MM		 3912#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3913do \
3914 { \
876c09d3
JW		 3915 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3916 TARGET_64BIT ? "dsubu" : "subu", \
e75b25e7
MM		 3917 reg_names[STACK_POINTER_REGNUM], \
3918 reg_names[STACK_POINTER_REGNUM], \
876c09d3 3919 TARGET_64BIT ? "sd" : "sw", \
e75b25e7
MM		 3920 reg_names[REGNO], \
3921 reg_names[STACK_POINTER_REGNUM]); \
3922 } \
3923while (0)
3924
3925#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3926do \
3927 { \
3928 if (! set_noreorder) \
3929 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3930 \
876c09d3
JW		 3931 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3932 TARGET_64BIT ? "ld" : "lw", \
e75b25e7
MM		 3933 reg_names[REGNO], \
3934 reg_names[STACK_POINTER_REGNUM], \
876c09d3 3935 TARGET_64BIT ? "daddu" : "addu", \
e75b25e7
MM		 3936 reg_names[STACK_POINTER_REGNUM], \
3937 reg_names[STACK_POINTER_REGNUM]); \
3938 \
3939 if (! set_noreorder) \
3940 fprintf (STREAM, "\t.set\treorder\n"); \
3941 } \
3942while (0)
3943
4baed42f
DE		 3944/* How to start an assembler comment.
3945 The leading space is important (the mips native assembler requires it). */
e75b25e7 3946#ifndef ASM_COMMENT_START
4baed42f 3947#define ASM_COMMENT_START " #"
e75b25e7 3948#endif
e75b25e7
MM		 3949\f
3950
3951/* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3952 and mips-tdump.c to print them out.
3953
3954 These must match the corresponding definitions in gdb/mipsread.c.
987ba558 3955 Unfortunately, gcc and gdb do not currently share any directories. */
e75b25e7
MM		 3956
3957#define CODE_MASK 0x8F300
3958#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3959#define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3960#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3f1f8d8c
MM		 3961
3962\f
48b80d93
AO		 3963/* Default definitions for size_t and ptrdiff_t. We must override the
3964 definitions from ../svr4.h on mips-*-linux-gnu. */
3f1f8d8c 3965
cafe096b
EC		 3966#ifndef SIZE_TYPE
3967#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3968#endif
3f1f8d8c 3969
cafe096b
EC		 3970#ifndef PTRDIFF_TYPE
3971#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3972#endif
28174a14
MS		 3973
3974/* See mips_expand_prologue's use of loadgp for when this should be
3975 true. */
3976
a53f72db
GRK		 3977#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3978 && mips_abi != ABI_32 \
3979 && mips_abi != ABI_O64)
2bcb2ab3 3980\f
2bcb2ab3
GK		 3981/* We need to use a special set of functions to handle hard floating
3982 point code in mips16 mode. */
337e2b69
ILT		 3983
3984#ifndef INIT_SUBTARGET_OPTABS
3985#define INIT_SUBTARGET_OPTABS
3986#endif
3987
3988#define INIT_TARGET_OPTABS \
3989do \
3990 { \
2bcb2ab3
GK		 3991 if (! TARGET_MIPS16 || ! mips16_hard_float) \
3992 INIT_SUBTARGET_OPTABS; \
3993 else \
3994 { \
3995 add_optab->handlers[(int) SFmode].libfunc = \
e85cde9a 3996 init_one_libfunc ("__mips16_addsf3"); \
2bcb2ab3 3997 sub_optab->handlers[(int) SFmode].libfunc = \
e85cde9a 3998 init_one_libfunc ("__mips16_subsf3"); \
2bcb2ab3 3999 smul_optab->handlers[(int) SFmode].libfunc = \
e85cde9a 4000 init_one_libfunc ("__mips16_mulsf3"); \
ef89d648 4001 sdiv_optab->handlers[(int) SFmode].libfunc = \
e85cde9a 4002 init_one_libfunc ("__mips16_divsf3"); \
2bcb2ab3 4003 \
e85cde9a
JL		 4004 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4005 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4006 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4007 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4008 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4009 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
2bcb2ab3
GK		 4010 \
4011 floatsisf_libfunc = \
e85cde9a 4012 init_one_libfunc ("__mips16_floatsisf"); \
2bcb2ab3 4013 fixsfsi_libfunc = \
e85cde9a 4014 init_one_libfunc ("__mips16_fixsfsi"); \
2bcb2ab3
GK		 4015 \
4016 if (TARGET_DOUBLE_FLOAT) \
4017 { \
4018 add_optab->handlers[(int) DFmode].libfunc = \
e85cde9a 4019 init_one_libfunc ("__mips16_adddf3"); \
2bcb2ab3 4020 sub_optab->handlers[(int) DFmode].libfunc = \
e85cde9a 4021 init_one_libfunc ("__mips16_subdf3"); \
2bcb2ab3 4022 smul_optab->handlers[(int) DFmode].libfunc = \
e85cde9a 4023 init_one_libfunc ("__mips16_muldf3"); \
ef89d648 4024 sdiv_optab->handlers[(int) DFmode].libfunc = \
e85cde9a 4025 init_one_libfunc ("__mips16_divdf3"); \
2bcb2ab3
GK		 4026 \
4027 extendsfdf2_libfunc = \
e85cde9a 4028 init_one_libfunc ("__mips16_extendsfdf2"); \
2bcb2ab3 4029 truncdfsf2_libfunc = \
e85cde9a 4030 init_one_libfunc ("__mips16_truncdfsf2"); \
2bcb2ab3
GK		 4031 \
4032 eqdf2_libfunc = \
e85cde9a 4033 init_one_libfunc ("__mips16_eqdf2"); \
2bcb2ab3 4034 nedf2_libfunc = \
e85cde9a 4035 init_one_libfunc ("__mips16_nedf2"); \
2bcb2ab3 4036 gtdf2_libfunc = \
e85cde9a 4037 init_one_libfunc ("__mips16_gtdf2"); \
2bcb2ab3 4038 gedf2_libfunc = \
e85cde9a 4039 init_one_libfunc ("__mips16_gedf2"); \
2bcb2ab3 4040 ltdf2_libfunc = \
e85cde9a 4041 init_one_libfunc ("__mips16_ltdf2"); \
2bcb2ab3 4042 ledf2_libfunc = \
e85cde9a 4043 init_one_libfunc ("__mips16_ledf2"); \
2bcb2ab3
GK		 4044 \
4045 floatsidf_libfunc = \
e85cde9a 4046 init_one_libfunc ("__mips16_floatsidf"); \
2bcb2ab3 4047 fixdfsi_libfunc = \
e85cde9a 4048 init_one_libfunc ("__mips16_fixdfsi"); \
2bcb2ab3
GK		 4049 } \
4050 } \
337e2b69
ILT		 4051 } \
4052while (0)
e0c13c70
L		 4053
4054#define DFMODE_NAN \
4055 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4056 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4057#define SFMODE_NAN \
4058 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4059 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
6d439235
EC		 4060
4061/* Generate calls to memcpy, etc., not bcopy, etc. */
2017ed61 4062#define TARGET_MEM_FUNCTIONS
3c0121e4 4063
28727f1f 4064#ifndef __mips16
3c0121e4
AO		 4065/* Since the bits of the _init and _fini function is spread across
4066 many object files, each potentially with its own GP, we must assume
4067 we need to load our GP. We don't preserve $gp or $ra, since each
4068 init/fini chunk is supposed to initialize $gp, and crti/crtn
4069 already take care of preserving $ra and, when appropriate, $gp. */
4070#if _MIPS_SIM == _MIPS_SIM_ABI32
4071#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4072 asm (SECTION_OP "\n\
4073 .set noreorder\n\
4074 bal 1f\n\
4075 nop\n\
40761: .cpload $31\n\
4077 .set reorder\n\
4078 jal " USER_LABEL_PREFIX #FUNC "\n\
4079 " TEXT_SECTION_ASM_OP);
e1551d47
AO		 4080#endif /* Switch to #elif when we're no longer limited by K&R C. */
4081#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3c0121e4
AO		 4082 || (defined _ABI64 && _MIPS_SIM == _ABI64)
4083#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4084 asm (SECTION_OP "\n\
4085 .set noreorder\n\
4086 bal 1f\n\
4087 nop\n\
40881: .set reorder\n\
4089 .cpsetup $31, $2, 1b\n\
4090 jal " USER_LABEL_PREFIX #FUNC "\n\
4091 " TEXT_SECTION_ASM_OP);
4092#endif
28727f1f 4093#endif
GNU Compiler Collection
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