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e75b25e7 | 1 | /* Definitions of target machine for GNU compiler. MIPS version. |
214be03f | 2 | Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 |
16c484c7 | 3 | 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
ae3e1bb4 RK |
4 | Contributed by A. Lichnewsky (lich@inria.inria.fr). |
5 | Changed by Michael Meissner (meissner@osf.org). | |
6 | 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and | |
7 | Brendan Eich (brendan@microunity.com). | |
e75b25e7 MM |
8 | |
9 | This file is part of GNU CC. | |
10 | ||
11 | GNU CC is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GNU CC is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GNU CC; see the file COPYING. If not, write to | |
75fe0c5e RK |
23 | the Free Software Foundation, 59 Temple Place - Suite 330, |
24 | Boston, MA 02111-1307, USA. */ | |
e75b25e7 MM |
25 | |
26 | ||
e75b25e7 MM |
27 | /* Standard GCC variables that we reference. */ |
28 | ||
0fb5ac6f MM |
29 | extern char *asm_file_name; |
30 | extern char call_used_regs[]; | |
0fb5ac6f | 31 | extern int may_call_alloca; |
0fb5ac6f MM |
32 | extern char **save_argv; |
33 | extern int target_flags; | |
e75b25e7 MM |
34 | |
35 | /* MIPS external variables defined in mips.c. */ | |
36 | ||
37 | /* comparison type */ | |
38 | enum cmp_type { | |
876c09d3 JW |
39 | CMP_SI, /* compare four byte integers */ |
40 | CMP_DI, /* compare eight byte integers */ | |
e75b25e7 MM |
41 | CMP_SF, /* compare single precision floats */ |
42 | CMP_DF, /* compare double precision floats */ | |
43 | CMP_MAX /* max comparison type */ | |
44 | }; | |
45 | ||
46 | /* types of delay slot */ | |
47 | enum delay_type { | |
48 | DELAY_NONE, /* no delay slot */ | |
49 | DELAY_LOAD, /* load from memory delay */ | |
34b650b3 MM |
50 | DELAY_HILO, /* move from/to hi/lo registers */ |
51 | DELAY_FCMP /* delay after doing c.<xx>.{d,s} */ | |
e75b25e7 MM |
52 | }; |
53 | ||
54 | /* Which processor to schedule for. Since there is no difference between | |
55 | a R2000 and R3000 in terms of the scheduler, we collapse them into | |
4a392643 RS |
56 | just an R3000. The elements of the enumeration must match exactly |
57 | the cpu attribute in the mips.md machine description. */ | |
e75b25e7 MM |
58 | |
59 | enum processor_type { | |
60 | PROCESSOR_DEFAULT, | |
61 | PROCESSOR_R3000, | |
e9a25f70 | 62 | PROCESSOR_R3900, |
e75b25e7 | 63 | PROCESSOR_R6000, |
876c09d3 | 64 | PROCESSOR_R4000, |
00b3e052 JW |
65 | PROCESSOR_R4100, |
66 | PROCESSOR_R4300, | |
516a2dfd | 67 | PROCESSOR_R4600, |
053665d7 | 68 | PROCESSOR_R4650, |
b8eb88d0 | 69 | PROCESSOR_R5000, |
0e5a4ad8 EC |
70 | PROCESSOR_R8000, |
71 | PROCESSOR_R4KC, | |
72 | PROCESSOR_R5KC, | |
73 | PROCESSOR_R20KC | |
e75b25e7 MM |
74 | }; |
75 | ||
4a392643 | 76 | /* Recast the cpu class to be the cpu attribute. */ |
919b1aec | 77 | #define mips_cpu_attr ((enum attr_cpu)mips_tune) |
4a392643 | 78 | |
04bd620d | 79 | /* Which ABI to use. These are constants because abi64.h must check their |
a53f72db GRK |
80 | value at preprocessing time. |
81 | ||
82 | ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all | |
987ba558 | 83 | defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */ |
b2d8cf33 | 84 | |
04bd620d JW |
85 | #define ABI_32 0 |
86 | #define ABI_N32 1 | |
87 | #define ABI_64 2 | |
88 | #define ABI_EABI 3 | |
a53f72db | 89 | #define ABI_O64 4 |
0e5a4ad8 EC |
90 | /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS) |
91 | which is not the same as the above EABI (defined by Cygnus, | |
92 | Greenhills, and Toshiba?). MEABI is not yet complete or published, | |
93 | but at this point it looks like N32 as far as calling conventions go, | |
94 | but allows for either 32 or 64 bit registers. | |
95 | ||
96 | Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus' | |
97 | EABI the legacy EABI. In the end we may end up calling both ABI's | |
98 | EABI but give them different version numbers, but for now I'm going | |
987ba558 | 99 | with different names. */ |
0e5a4ad8 EC |
100 | #define ABI_MEABI 5 |
101 | ||
45ceb85d RS |
102 | /* Whether to emit abicalls code sequences or not. */ |
103 | ||
104 | enum mips_abicalls_type { | |
105 | MIPS_ABICALLS_NO, | |
106 | MIPS_ABICALLS_YES | |
107 | }; | |
108 | ||
109 | /* Recast the abicalls class to be the abicalls attribute. */ | |
110 | #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls) | |
111 | ||
b7d3fabe RS |
112 | /* Which type of block move to do (whether or not the last store is |
113 | split out so it can fill a branch delay slot). */ | |
114 | ||
115 | enum block_move_type { | |
116 | BLOCK_MOVE_NORMAL, /* generate complete block move */ | |
117 | BLOCK_MOVE_NOT_LAST, /* generate all but last store */ | |
118 | BLOCK_MOVE_LAST /* generate just the last store */ | |
119 | }; | |
120 | ||
987ba558 | 121 | extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */ |
f540a7d3 | 122 | extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */ |
e2fe6aba | 123 | extern const char *current_function_file; /* filename current function is in */ |
e75b25e7 MM |
124 | extern int num_source_filenames; /* current .file # */ |
125 | extern int inside_function; /* != 0 if inside of a function */ | |
126 | extern int ignore_line_number; /* != 0 if we are to ignore next .loc */ | |
127 | extern int file_in_function_warning; /* warning given about .file in func */ | |
128 | extern int sdb_label_count; /* block start/end next label # */ | |
a642a781 | 129 | extern int sdb_begin_function_line; /* Starting Line of current function */ |
e75b25e7 MM |
130 | extern int mips_section_threshold; /* # bytes of data/sdata cutoff */ |
131 | extern int g_switch_value; /* value of the -G xx switch */ | |
132 | extern int g_switch_set; /* whether -G xx was passed. */ | |
133 | extern int sym_lineno; /* sgi next label # for each stmt */ | |
134 | extern int set_noreorder; /* # of nested .set noreorder's */ | |
135 | extern int set_nomacro; /* # of nested .set nomacro's */ | |
136 | extern int set_noat; /* # of nested .set noat's */ | |
137 | extern int set_volatile; /* # of nested .set volatile's */ | |
e75b25e7 MM |
138 | extern int mips_branch_likely; /* emit 'l' after br (branch likely) */ |
139 | extern int mips_dbx_regno[]; /* Map register # to debug register # */ | |
e75b25e7 MM |
140 | extern struct rtx_def *branch_cmp[2]; /* operands for compare */ |
141 | extern enum cmp_type branch_type; /* what type of branch to use */ | |
7dac2f89 EC |
142 | extern enum processor_type mips_arch; /* which cpu to codegen for */ |
143 | extern enum processor_type mips_tune; /* which cpu to schedule for */ | |
45ceb85d | 144 | extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */ |
e75b25e7 | 145 | extern int mips_isa; /* architectural level */ |
2bcb2ab3 GK |
146 | extern int mips16; /* whether generating mips16 code */ |
147 | extern int mips16_hard_float; /* mips16 without -msoft-float */ | |
148 | extern int mips_entry; /* generate entry/exit for mips16 */ | |
e2fe6aba | 149 | extern const char *mips_cpu_string; /* for -mcpu=<xxx> */ |
7dac2f89 EC |
150 | extern const char *mips_arch_string; /* for -march=<xxx> */ |
151 | extern const char *mips_tune_string; /* for -mtune=<xxx> */ | |
e2fe6aba KG |
152 | extern const char *mips_isa_string; /* for -mips{1,2,3,4} */ |
153 | extern const char *mips_abi_string; /* for -mabi={32,n32,64} */ | |
154 | extern const char *mips_entry_string; /* for -mentry */ | |
155 | extern const char *mips_no_mips16_string;/* for -mno-mips16 */ | |
3ce1ba83 | 156 | extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */ |
d490e8ad | 157 | extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */ |
ce57d6f4 | 158 | extern int mips_split_addresses; /* perform high/lo_sum support */ |
e75b25e7 MM |
159 | extern int dslots_load_total; /* total # load related delay slots */ |
160 | extern int dslots_load_filled; /* # filled load delay slots */ | |
161 | extern int dslots_jump_total; /* total # jump related delay slots */ | |
162 | extern int dslots_jump_filled; /* # filled jump delay slots */ | |
163 | extern int dslots_number_nops; /* # of nops needed by previous insn */ | |
164 | extern int num_refs[3]; /* # 1/2/3 word references */ | |
165 | extern struct rtx_def *mips_load_reg; /* register to check for load delay */ | |
166 | extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */ | |
167 | extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */ | |
168 | extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */ | |
2bcb2ab3 | 169 | extern int mips_string_length; /* length of strings for mips16 */ |
e75b25e7 | 170 | |
0fb5ac6f | 171 | /* Functions to change what output section we are using. */ |
bd9f1972 | 172 | extern void sdata_section PARAMS ((void)); |
cc8f5ec0 | 173 | extern void sbss_section PARAMS ((void)); |
e75b25e7 | 174 | |
31c714e3 MM |
175 | /* Stubs for half-pic support if not OSF/1 reference platform. */ |
176 | ||
177 | #ifndef HALF_PIC_P | |
178 | #define HALF_PIC_P() 0 | |
4a392643 RS |
179 | #define HALF_PIC_NUMBER_PTRS 0 |
180 | #define HALF_PIC_NUMBER_REFS 0 | |
31c714e3 | 181 | #define HALF_PIC_ENCODE(DECL) |
f3b39eba | 182 | #define HALF_PIC_DECLARE(NAME) |
c725bd79 | 183 | #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it") |
31c714e3 | 184 | #define HALF_PIC_ADDRESS_P(X) 0 |
d26e29e1 MM |
185 | #define HALF_PIC_PTR(X) X |
186 | #define HALF_PIC_FINISH(STREAM) | |
31c714e3 MM |
187 | #endif |
188 | ||
3a6ee9f4 MM |
189 | /* Macros to silence warnings about numbers being signed in traditional |
190 | C and unsigned in ISO C when compiled on 32-bit hosts. */ | |
191 | ||
192 | #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ | |
193 | #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ | |
194 | #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ | |
195 | ||
149e4e00 MM |
196 | \f |
197 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
198 | ||
199 | /* Macros used in the machine description to test the flags. */ | |
200 | ||
201 | /* Bits for real switches */ | |
6d81ba45 CD |
202 | #define MASK_INT64 0x00000001 /* ints are 64 bits */ |
203 | #define MASK_LONG64 0x00000002 /* longs are 64 bits */ | |
204 | #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */ | |
205 | #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */ | |
206 | #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */ | |
207 | #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */ | |
208 | #define MASK_STATS 0x00000040 /* print statistics to stderr */ | |
209 | #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/ | |
210 | #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */ | |
211 | #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */ | |
212 | #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */ | |
213 | #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/ | |
214 | #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */ | |
215 | #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */ | |
216 | #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */ | |
365c6a0b | 217 | #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */ |
6d81ba45 CD |
218 | #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */ |
219 | #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */ | |
220 | #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */ | |
221 | #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */ | |
7dac2f89 | 222 | #define MASK_MIPS16 0x00100000 /* Generate mips16 code */ |
6d81ba45 | 223 | #define MASK_NO_CHECK_ZERO_DIV \ |
7dac2f89 | 224 | 0x00200000 /* divide by zero checking */ |
6d81ba45 | 225 | #define MASK_CHECK_RANGE_DIV \ |
7dac2f89 | 226 | 0x00400000 /* divide result range checking */ |
6d81ba45 | 227 | #define MASK_UNINIT_CONST_IN_RODATA \ |
7dac2f89 | 228 | 0x00800000 /* Store uninitialized |
6d81ba45 | 229 | consts in rodata */ |
13fac94a GK |
230 | #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point |
231 | multiply-add operations. */ | |
149e4e00 MM |
232 | |
233 | /* Debug switches, not documented */ | |
6d81ba45 CD |
234 | #define MASK_DEBUG 0 /* unused */ |
235 | #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */ | |
236 | #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */ | |
987ba558 | 237 | #define MASK_DEBUG_C 0 /* don't expand seq, etc. */ |
08c2951c | 238 | #define MASK_DEBUG_D 0 /* don't do define_split's */ |
e4f5c5d6 | 239 | #define MASK_DEBUG_E 0 /* function_arg debug */ |
6d81ba45 | 240 | #define MASK_DEBUG_F 0 /* ??? */ |
2bcb2ab3 | 241 | #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */ |
6d1350cd | 242 | #define MASK_DEBUG_H 0 /* allow ints in FP registers */ |
e4f5c5d6 | 243 | #define MASK_DEBUG_I 0 /* unused */ |
149e4e00 | 244 | |
6d81ba45 CD |
245 | /* Dummy switches used only in specs */ |
246 | #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */ | |
247 | ||
149e4e00 MM |
248 | /* r4000 64 bit sizes */ |
249 | #define TARGET_INT64 (target_flags & MASK_INT64) | |
250 | #define TARGET_LONG64 (target_flags & MASK_LONG64) | |
149e4e00 | 251 | #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64) |
876c09d3 | 252 | #define TARGET_64BIT (target_flags & MASK_64BIT) |
149e4e00 | 253 | |
5ef37cd3 JW |
254 | /* Mips vs. GNU linker */ |
255 | #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR) | |
256 | ||
149e4e00 MM |
257 | /* Mips vs. GNU assembler */ |
258 | #define TARGET_GAS (target_flags & MASK_GAS) | |
6d81ba45 | 259 | #define TARGET_MIPS_AS (!TARGET_GAS) |
149e4e00 | 260 | |
6d81ba45 | 261 | /* Debug Modes */ |
149e4e00 MM |
262 | #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG) |
263 | #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A) | |
264 | #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B) | |
265 | #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C) | |
266 | #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D) | |
267 | #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E) | |
268 | #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F) | |
269 | #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G) | |
270 | #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H) | |
271 | #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I) | |
149e4e00 MM |
272 | |
273 | /* Reg. Naming in .s ($21 vs. $a0) */ | |
274 | #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS) | |
275 | ||
276 | /* Optimize for Sdata/Sbss */ | |
277 | #define TARGET_GP_OPT (target_flags & MASK_GPOPT) | |
278 | ||
279 | /* print program statistics */ | |
280 | #define TARGET_STATS (target_flags & MASK_STATS) | |
281 | ||
282 | /* call memcpy instead of inline code */ | |
283 | #define TARGET_MEMCPY (target_flags & MASK_MEMCPY) | |
284 | ||
285 | /* .abicalls, etc from Pyramid V.4 */ | |
286 | #define TARGET_ABICALLS (target_flags & MASK_ABICALLS) | |
287 | ||
288 | /* OSF pic references to externs */ | |
289 | #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC) | |
290 | ||
291 | /* software floating point */ | |
292 | #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT) | |
293 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) | |
294 | ||
295 | /* always call through a register */ | |
296 | #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS) | |
297 | ||
e0bfcea5 ILT |
298 | /* generate embedded PIC code; |
299 | requires gas. */ | |
300 | #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC) | |
301 | ||
365c6a0b JW |
302 | /* for embedded systems, optimize for |
303 | reduced RAM space instead of for | |
304 | fastest code. */ | |
305 | #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA) | |
306 | ||
919509ce DN |
307 | /* always store uninitialized const |
308 | variables in rodata, requires | |
987ba558 | 309 | TARGET_EMBEDDED_DATA. */ |
919509ce DN |
310 | #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA) |
311 | ||
96abdcb1 ILT |
312 | /* generate big endian code. */ |
313 | #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN) | |
314 | ||
46299de9 ILT |
315 | #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT) |
316 | #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT) | |
317 | ||
318 | #define TARGET_MAD (target_flags & MASK_MAD) | |
319 | ||
13fac94a GK |
320 | #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD)) |
321 | ||
00b3e052 JW |
322 | #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX) |
323 | ||
08c2951c SC |
324 | #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV) |
325 | #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV) | |
326 | ||
33b5e50b JW |
327 | /* This is true if we must enable the assembly language file switching |
328 | code. */ | |
329 | ||
f99ffb60 RH |
330 | #define TARGET_FILE_SWITCHING \ |
331 | (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16) | |
33b5e50b JW |
332 | |
333 | /* We must disable the function end stabs when doing the file switching trick, | |
334 | because the Lscope stabs end up in the wrong place, making it impossible | |
335 | to debug the resulting code. */ | |
336 | #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING | |
337 | ||
2bcb2ab3 GK |
338 | /* Generate mips16 code */ |
339 | #define TARGET_MIPS16 (target_flags & MASK_MIPS16) | |
340 | ||
7dac2f89 EC |
341 | /* Architecture target defines. */ |
342 | #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) | |
343 | #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) | |
344 | #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100) | |
345 | #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300) | |
0e5a4ad8 EC |
346 | #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC) |
347 | #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC) | |
7dac2f89 EC |
348 | |
349 | /* Scheduling target defines. */ | |
7a38df19 EC |
350 | #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) |
351 | #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) | |
352 | #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) | |
353 | #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) | |
354 | #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) | |
7dac2f89 | 355 | |
149e4e00 MM |
356 | /* Macro to define tables used to set the flags. |
357 | This is a list in braces of pairs in braces, | |
358 | each pair being { "NAME", VALUE } | |
359 | where VALUE is the bits to set or minus the bits to clear. | |
360 | An empty string NAME is used to identify the default VALUE. */ | |
361 | ||
362 | #define TARGET_SWITCHES \ | |
363 | { \ | |
c45fd7f9 | 364 | {"no-crt0", 0, \ |
047142d3 | 365 | N_("No default crt0.o") }, \ |
a127db75 | 366 | {"int64", MASK_INT64 | MASK_LONG64, \ |
047142d3 | 367 | N_("Use 64-bit int type")}, \ |
a127db75 | 368 | {"long64", MASK_LONG64, \ |
047142d3 | 369 | N_("Use 64-bit long type")}, \ |
a127db75 | 370 | {"long32", -(MASK_LONG64 | MASK_INT64), \ |
047142d3 | 371 | N_("Use 32-bit long type")}, \ |
a127db75 | 372 | {"split-addresses", MASK_SPLIT_ADDR, \ |
047142d3 | 373 | N_("Optimize lui/addiu address loads")}, \ |
a127db75 | 374 | {"no-split-addresses", -MASK_SPLIT_ADDR, \ |
047142d3 | 375 | N_("Don't optimize lui/addiu address loads")}, \ |
a127db75 | 376 | {"mips-as", -MASK_GAS, \ |
047142d3 | 377 | N_("Use MIPS as")}, \ |
a127db75 | 378 | {"gas", MASK_GAS, \ |
047142d3 | 379 | N_("Use GNU as")}, \ |
a127db75 | 380 | {"rnames", MASK_NAME_REGS, \ |
047142d3 | 381 | N_("Use symbolic register names")}, \ |
a127db75 | 382 | {"no-rnames", -MASK_NAME_REGS, \ |
047142d3 | 383 | N_("Don't use symbolic register names")}, \ |
a127db75 | 384 | {"gpOPT", MASK_GPOPT, \ |
047142d3 | 385 | N_("Use GP relative sdata/sbss sections")}, \ |
a127db75 | 386 | {"gpopt", MASK_GPOPT, \ |
047142d3 | 387 | N_("Use GP relative sdata/sbss sections")}, \ |
a127db75 | 388 | {"no-gpOPT", -MASK_GPOPT, \ |
047142d3 | 389 | N_("Don't use GP relative sdata/sbss sections")}, \ |
a127db75 | 390 | {"no-gpopt", -MASK_GPOPT, \ |
047142d3 | 391 | N_("Don't use GP relative sdata/sbss sections")}, \ |
a127db75 | 392 | {"stats", MASK_STATS, \ |
047142d3 | 393 | N_("Output compiler statistics")}, \ |
a127db75 | 394 | {"no-stats", -MASK_STATS, \ |
047142d3 | 395 | N_("Don't output compiler statistics")}, \ |
a127db75 | 396 | {"memcpy", MASK_MEMCPY, \ |
047142d3 | 397 | N_("Don't optimize block moves")}, \ |
a127db75 | 398 | {"no-memcpy", -MASK_MEMCPY, \ |
047142d3 | 399 | N_("Optimize block moves")}, \ |
a127db75 | 400 | {"mips-tfile", MASK_MIPS_TFILE, \ |
047142d3 | 401 | N_("Use mips-tfile asm postpass")}, \ |
a127db75 | 402 | {"no-mips-tfile", -MASK_MIPS_TFILE, \ |
047142d3 | 403 | N_("Don't use mips-tfile asm postpass")}, \ |
a127db75 | 404 | {"soft-float", MASK_SOFT_FLOAT, \ |
047142d3 | 405 | N_("Use software floating point")}, \ |
a127db75 | 406 | {"hard-float", -MASK_SOFT_FLOAT, \ |
047142d3 | 407 | N_("Use hardware floating point")}, \ |
a127db75 | 408 | {"fp64", MASK_FLOAT64, \ |
047142d3 | 409 | N_("Use 64-bit FP registers")}, \ |
a127db75 | 410 | {"fp32", -MASK_FLOAT64, \ |
047142d3 | 411 | N_("Use 32-bit FP registers")}, \ |
a127db75 | 412 | {"gp64", MASK_64BIT, \ |
047142d3 | 413 | N_("Use 64-bit general registers")}, \ |
a127db75 | 414 | {"gp32", -MASK_64BIT, \ |
047142d3 | 415 | N_("Use 32-bit general registers")}, \ |
a127db75 | 416 | {"abicalls", MASK_ABICALLS, \ |
047142d3 | 417 | N_("Use Irix PIC")}, \ |
a127db75 | 418 | {"no-abicalls", -MASK_ABICALLS, \ |
047142d3 | 419 | N_("Don't use Irix PIC")}, \ |
a127db75 | 420 | {"half-pic", MASK_HALF_PIC, \ |
047142d3 | 421 | N_("Use OSF PIC")}, \ |
a127db75 | 422 | {"no-half-pic", -MASK_HALF_PIC, \ |
047142d3 | 423 | N_("Don't use OSF PIC")}, \ |
a127db75 | 424 | {"long-calls", MASK_LONG_CALLS, \ |
047142d3 | 425 | N_("Use indirect calls")}, \ |
a127db75 | 426 | {"no-long-calls", -MASK_LONG_CALLS, \ |
047142d3 | 427 | N_("Don't use indirect calls")}, \ |
a127db75 | 428 | {"embedded-pic", MASK_EMBEDDED_PIC, \ |
047142d3 | 429 | N_("Use embedded PIC")}, \ |
a127db75 | 430 | {"no-embedded-pic", -MASK_EMBEDDED_PIC, \ |
047142d3 | 431 | N_("Don't use embedded PIC")}, \ |
a127db75 | 432 | {"embedded-data", MASK_EMBEDDED_DATA, \ |
047142d3 | 433 | N_("Use ROM instead of RAM")}, \ |
a127db75 | 434 | {"no-embedded-data", -MASK_EMBEDDED_DATA, \ |
047142d3 | 435 | N_("Don't use ROM instead of RAM")}, \ |
919509ce | 436 | {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \ |
047142d3 | 437 | N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \ |
919509ce | 438 | {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \ |
047142d3 | 439 | N_("Don't put uninitialized constants in ROM")}, \ |
a127db75 | 440 | {"eb", MASK_BIG_ENDIAN, \ |
047142d3 | 441 | N_("Use big-endian byte order")}, \ |
a127db75 | 442 | {"el", -MASK_BIG_ENDIAN, \ |
047142d3 | 443 | N_("Use little-endian byte order")}, \ |
a127db75 | 444 | {"single-float", MASK_SINGLE_FLOAT, \ |
047142d3 | 445 | N_("Use single (32-bit) FP only")}, \ |
a127db75 | 446 | {"double-float", -MASK_SINGLE_FLOAT, \ |
047142d3 | 447 | N_("Don't use single (32-bit) FP only")}, \ |
a127db75 | 448 | {"mad", MASK_MAD, \ |
047142d3 | 449 | N_("Use multiply accumulate")}, \ |
a127db75 | 450 | {"no-mad", -MASK_MAD, \ |
047142d3 | 451 | N_("Don't use multiply accumulate")}, \ |
13fac94a GK |
452 | {"no-fused-madd", MASK_NO_FUSED_MADD, \ |
453 | N_("Don't generate fused multiply/add instructions")}, \ | |
454 | {"fused-madd", -MASK_NO_FUSED_MADD, \ | |
455 | N_("Generate fused multiply/add instructions")}, \ | |
a127db75 | 456 | {"fix4300", MASK_4300_MUL_FIX, \ |
047142d3 | 457 | N_("Work around early 4300 hardware bug")}, \ |
a127db75 | 458 | {"no-fix4300", -MASK_4300_MUL_FIX, \ |
047142d3 | 459 | N_("Don't work around early 4300 hardware bug")}, \ |
7dac2f89 | 460 | {"3900", 0, \ |
047142d3 | 461 | N_("Optimize for 3900")}, \ |
7dac2f89 EC |
462 | {"4650", 0, \ |
463 | N_("Optimize for 4650")}, \ | |
a127db75 | 464 | {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \ |
047142d3 | 465 | N_("Trap on integer divide by zero")}, \ |
a127db75 | 466 | {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \ |
047142d3 | 467 | N_("Don't trap on integer divide by zero")}, \ |
a127db75 | 468 | {"check-range-division",MASK_CHECK_RANGE_DIV, \ |
047142d3 | 469 | N_("Trap on integer divide overflow")}, \ |
a127db75 | 470 | {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \ |
047142d3 | 471 | N_("Don't trap on integer divide overflow")}, \ |
a127db75 JW |
472 | {"debug", MASK_DEBUG, \ |
473 | NULL}, \ | |
474 | {"debuga", MASK_DEBUG_A, \ | |
475 | NULL}, \ | |
476 | {"debugb", MASK_DEBUG_B, \ | |
477 | NULL}, \ | |
478 | {"debugc", MASK_DEBUG_C, \ | |
479 | NULL}, \ | |
480 | {"debugd", MASK_DEBUG_D, \ | |
481 | NULL}, \ | |
482 | {"debuge", MASK_DEBUG_E, \ | |
483 | NULL}, \ | |
484 | {"debugf", MASK_DEBUG_F, \ | |
485 | NULL}, \ | |
486 | {"debugg", MASK_DEBUG_G, \ | |
487 | NULL}, \ | |
488 | {"debugh", MASK_DEBUG_H, \ | |
489 | NULL}, \ | |
490 | {"debugi", MASK_DEBUG_I, \ | |
491 | NULL}, \ | |
96abdcb1 ILT |
492 | {"", (TARGET_DEFAULT \ |
493 | | TARGET_CPU_DEFAULT \ | |
a127db75 JW |
494 | | TARGET_ENDIAN_DEFAULT), \ |
495 | NULL}, \ | |
7dac2f89 | 496 | } |
149e4e00 MM |
497 | |
498 | /* Default target_flags if no switches are specified */ | |
499 | ||
500 | #ifndef TARGET_DEFAULT | |
501 | #define TARGET_DEFAULT 0 | |
502 | #endif | |
503 | ||
404f986e MM |
504 | #ifndef TARGET_CPU_DEFAULT |
505 | #define TARGET_CPU_DEFAULT 0 | |
506 | #endif | |
507 | ||
96abdcb1 ILT |
508 | #ifndef TARGET_ENDIAN_DEFAULT |
509 | #ifndef DECSTATION | |
510 | #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN | |
511 | #else | |
512 | #define TARGET_ENDIAN_DEFAULT 0 | |
513 | #endif | |
514 | #endif | |
515 | ||
ea09f032 GRK |
516 | #ifndef MIPS_ISA_DEFAULT |
517 | #define MIPS_ISA_DEFAULT 1 | |
518 | #endif | |
519 | ||
996ed075 JJ |
520 | #ifdef IN_LIBGCC2 |
521 | #undef TARGET_64BIT | |
522 | /* Make this compile time constant for libgcc2 */ | |
523 | #ifdef __mips64 | |
524 | #define TARGET_64BIT 1 | |
525 | #else | |
526 | #define TARGET_64BIT 0 | |
527 | #endif | |
440927ec | 528 | #endif /* IN_LIBGCC2 */ |
996ed075 | 529 | |
cbab8d02 | 530 | #ifndef MULTILIB_ENDIAN_DEFAULT |
7f2e00db | 531 | #if TARGET_ENDIAN_DEFAULT == 0 |
cbab8d02 | 532 | #define MULTILIB_ENDIAN_DEFAULT "EL" |
7f2e00db | 533 | #else |
cbab8d02 GRK |
534 | #define MULTILIB_ENDIAN_DEFAULT "EB" |
535 | #endif | |
7f2e00db | 536 | #endif |
cbab8d02 | 537 | |
ea09f032 | 538 | #ifndef MULTILIB_ISA_DEFAULT |
7ce2fcb9 KG |
539 | # if MIPS_ISA_DEFAULT == 1 |
540 | # define MULTILIB_ISA_DEFAULT "mips1" | |
541 | # else | |
542 | # if MIPS_ISA_DEFAULT == 2 | |
543 | # define MULTILIB_ISA_DEFAULT "mips2" | |
544 | # else | |
545 | # if MIPS_ISA_DEFAULT == 3 | |
546 | # define MULTILIB_ISA_DEFAULT "mips3" | |
547 | # else | |
548 | # if MIPS_ISA_DEFAULT == 4 | |
549 | # define MULTILIB_ISA_DEFAULT "mips4" | |
550 | # else | |
0e5a4ad8 EC |
551 | # if MIPS_ISA_DEFAULT == 32 |
552 | # define MULTILIB_ISA_DEFAULT "mips32" | |
553 | # else | |
554 | # if MIPS_ISA_DEFAULT == 64 | |
555 | # define MULTILIB_ISA_DEFAULT "mips64" | |
556 | # else | |
7ce2fcb9 | 557 | # define MULTILIB_ISA_DEFAULT "mips1" |
0e5a4ad8 | 558 | # endif |
7ce2fcb9 | 559 | # endif |
0e5a4ad8 | 560 | # endif |
7ce2fcb9 KG |
561 | # endif |
562 | # endif | |
563 | # endif | |
ea09f032 GRK |
564 | #endif |
565 | ||
cbab8d02 | 566 | #ifndef MULTILIB_DEFAULTS |
ea09f032 | 567 | #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT } |
7f2e00db RK |
568 | #endif |
569 | ||
34bcd7fd JW |
570 | /* We must pass -EL to the linker by default for little endian embedded |
571 | targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the | |
572 | linker will default to using big-endian output files. The OUTPUT_FORMAT | |
573 | line must be in the linker script, otherwise -EB/-EL will not work. */ | |
574 | ||
120dc6cd | 575 | #ifndef ENDIAN_SPEC |
34bcd7fd | 576 | #if TARGET_ENDIAN_DEFAULT == 0 |
ac282977 | 577 | #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" |
34bcd7fd | 578 | #else |
ac282977 | 579 | #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" |
34bcd7fd JW |
580 | #endif |
581 | #endif | |
582 | ||
149e4e00 MM |
583 | #define TARGET_OPTIONS \ |
584 | { \ | |
b2d8cf33 | 585 | SUBTARGET_TARGET_OPTIONS \ |
a127db75 | 586 | { "cpu=", &mips_cpu_string, \ |
047142d3 | 587 | N_("Specify CPU for scheduling purposes")}, \ |
7dac2f89 EC |
588 | { "tune=", &mips_tune_string, \ |
589 | N_("Specify CPU for scheduling purposes")}, \ | |
590 | { "arch=", &mips_arch_string, \ | |
591 | N_("Specify CPU for code generation purposes")}, \ | |
a127db75 | 592 | { "ips", &mips_isa_string, \ |
7dac2f89 | 593 | N_("Specify a Standard MIPS ISA")}, \ |
a127db75 | 594 | { "entry", &mips_entry_string, \ |
047142d3 | 595 | N_("Use mips16 entry/exit psuedo ops")}, \ |
a127db75 | 596 | { "no-mips16", &mips_no_mips16_string, \ |
047142d3 | 597 | N_("Don't use MIPS16 instructions")}, \ |
a127db75 JW |
598 | { "explicit-type-size", &mips_explicit_type_size_string, \ |
599 | NULL}, \ | |
d490e8ad DD |
600 | { "no-flush-func", &mips_cache_flush_func, \ |
601 | N_("Don't call any cache flush functions")}, \ | |
602 | { "flush-func=", &mips_cache_flush_func, \ | |
603 | N_("Specify cache flush function")}, \ | |
149e4e00 MM |
604 | } |
605 | ||
b2d8cf33 JW |
606 | /* This is meant to be redefined in the host dependent files. */ |
607 | #define SUBTARGET_TARGET_OPTIONS | |
608 | ||
7dac2f89 | 609 | #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY) |
e4f5c5d6 | 610 | |
0e5a4ad8 EC |
611 | /* Generate three-operand multiply instructions for SImode. */ |
612 | #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \ | |
613 | || mips_isa == 32 \ | |
614 | || mips_isa == 64) \ | |
615 | && !TARGET_MIPS16) | |
616 | ||
617 | /* Generate three-operand multiply instructions for DImode. */ | |
618 | #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \ | |
619 | && !TARGET_MIPS16) | |
e9a25f70 | 620 | |
149e4e00 MM |
621 | /* Macros to decide whether certain features are available or not, |
622 | depending on the instruction set architecture level. */ | |
623 | ||
e9a25f70 | 624 | #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY |
1d5d552e GRK |
625 | #define HAVE_SQRT_P() (mips_isa != 1) |
626 | ||
987ba558 | 627 | /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */ |
0e5a4ad8 EC |
628 | #define ISA_HAS_64BIT_REGS (mips_isa == 3 \ |
629 | || mips_isa == 4 \ | |
630 | || mips_isa == 64) | |
1d5d552e | 631 | |
987ba558 | 632 | /* ISA has branch likely instructions (eg. mips2). */ |
7dac2f89 EC |
633 | /* Disable branchlikely for tx39 until compare rewrite. They haven't |
634 | been generated up to this point. */ | |
635 | #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \ | |
974a3101 | 636 | && ! TARGET_MIPS16) |
1d5d552e | 637 | |
987ba558 | 638 | /* ISA has the conditional move instructions introduced in mips4. */ |
974a3101 AO |
639 | #define ISA_HAS_CONDMOVE ((mips_isa == 4 \ |
640 | || mips_isa == 32 \ | |
641 | || mips_isa == 64) \ | |
642 | && ! TARGET_MIPS16) | |
76ee8042 | 643 | |
0025b7fa GRK |
644 | /* ISA has just the integer condition move instructions (movn,movz) */ |
645 | #define ISA_HAS_INT_CONDMOVE 0 | |
646 | ||
76ee8042 | 647 | /* ISA has the mips4 FP condition code instructions: FP-compare to CC, |
987ba558 | 648 | branch on CC, and move (both FP and non-FP) on CC. */ |
76ee8042 | 649 | #define ISA_HAS_8CC (mips_isa == 4 \ |
0e5a4ad8 EC |
650 | || mips_isa == 32 \ |
651 | || mips_isa == 64) | |
76ee8042 | 652 | |
76ee8042 | 653 | /* This is a catch all for the other new mips4 instructions: indexed load and |
7dac2f89 | 654 | indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions, |
76ee8042 GRK |
655 | and the FP recip and recip sqrt instructions */ |
656 | #define ISA_HAS_FP4 (mips_isa == 4 \ | |
974a3101 | 657 | && ! TARGET_MIPS16) |
76ee8042 | 658 | |
a0b6cdee | 659 | /* ISA has conditional trap instructions. */ |
974a3101 AO |
660 | #define ISA_HAS_COND_TRAP (mips_isa >= 2 \ |
661 | && ! TARGET_MIPS16) | |
1d5d552e | 662 | |
0e5a4ad8 | 663 | /* ISA has multiply-accumulate instructions, madd and msub. */ |
974a3101 AO |
664 | #define ISA_HAS_MADD_MSUB ((mips_isa == 32 \ |
665 | || mips_isa == 64 \ | |
666 | ) && ! TARGET_MIPS16) | |
0e5a4ad8 | 667 | |
1f28c666 AH |
668 | /* ISA has nmadd and nmsub instructions. */ |
669 | #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \ | |
974a3101 | 670 | && ! TARGET_MIPS16) |
149e4e00 | 671 | |
0e5a4ad8 | 672 | /* ISA has count leading zeroes/ones instruction (not implemented). */ |
974a3101 AO |
673 | #define ISA_HAS_CLZ_CLO ((mips_isa == 32 \ |
674 | || mips_isa == 64 \ | |
675 | ) && ! TARGET_MIPS16) | |
0e5a4ad8 EC |
676 | |
677 | /* ISA has double-word count leading zeroes/ones instruction (not | |
678 | implemented). */ | |
974a3101 AO |
679 | #define ISA_HAS_DCLZ_DCLO (mips_isa == 64 \ |
680 | && ! TARGET_MIPS16) | |
0e5a4ad8 | 681 | |
516a2dfd JW |
682 | /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or |
683 | -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit | |
2370b831 JW |
684 | -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in |
685 | target_flags, and -mgp64 sets MASK_64BIT. | |
876c09d3 | 686 | |
2370b831 JW |
687 | Setting MASK_64BIT in target_flags will cause gcc to assume that |
688 | registers are 64 bits wide. int, long and void * will be 32 bit; | |
689 | this may be changed with -mint64 or -mlong64. | |
876c09d3 | 690 | |
2370b831 JW |
691 | The gen* programs link code that refers to MASK_64BIT. They don't |
692 | actually use the information in target_flags; they just refer to | |
693 | it. */ | |
e75b25e7 MM |
694 | \f |
695 | /* Switch Recognition by gcc.c. Add -G xx support */ | |
696 | ||
0e5a4ad8 | 697 | #undef SWITCH_TAKES_ARG |
e75b25e7 | 698 | #define SWITCH_TAKES_ARG(CHAR) \ |
7d4ea832 | 699 | (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') |
e75b25e7 MM |
700 | |
701 | /* Sometimes certain combinations of command options do not make sense | |
702 | on a particular target machine. You can define a macro | |
703 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
704 | defined, is executed once just after all the command options have | |
705 | been parsed. | |
706 | ||
707 | On the MIPS, it is used to handle -G. We also use it to set up all | |
708 | of the tables referenced in the other macros. */ | |
709 | ||
710 | #define OVERRIDE_OPTIONS override_options () | |
711 | ||
712 | /* Zero or more C statements that may conditionally modify two | |
713 | variables `fixed_regs' and `call_used_regs' (both of type `char | |
714 | []') after they have been initialized from the two preceding | |
715 | macros. | |
716 | ||
717 | This is necessary in case the fixed or call-clobbered registers | |
718 | depend on target flags. | |
719 | ||
720 | You need not define this macro if it has no work to do. | |
721 | ||
722 | If the usage of an entire class of registers depends on the target | |
723 | flags, you may indicate this to GCC by using this macro to modify | |
724 | `fixed_regs' and `call_used_regs' to 1 for each of the registers in | |
725 | the classes which should not be used by GCC. Also define the macro | |
726 | `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a | |
727 | letter for a class that shouldn't be used. | |
728 | ||
729 | (However, if this class is not included in `GENERAL_REGS' and all | |
730 | of the insn patterns whose constraints permit this class are | |
731 | controlled by target switches, then GCC will automatically avoid | |
732 | using these registers when the target switches are opposed to | |
733 | them.) */ | |
734 | ||
735 | #define CONDITIONAL_REGISTER_USAGE \ | |
736 | do \ | |
737 | { \ | |
738 | if (!TARGET_HARD_FLOAT) \ | |
739 | { \ | |
740 | int regno; \ | |
741 | \ | |
742 | for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \ | |
743 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
b8eb88d0 ILT |
744 | for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \ |
745 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
746 | } \ | |
76ee8042 | 747 | else if (! ISA_HAS_8CC) \ |
b8eb88d0 ILT |
748 | { \ |
749 | int regno; \ | |
750 | \ | |
751 | /* We only have a single condition code register. We \ | |
752 | implement this by hiding all the condition code registers, \ | |
753 | and generating RTL that refers directly to ST_REG_FIRST. */ \ | |
754 | for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \ | |
755 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
e75b25e7 | 756 | } \ |
2bcb2ab3 GK |
757 | /* In mips16 mode, we permit the $t temporary registers to be used \ |
758 | for reload. We prohibit the unused $s registers, since they \ | |
759 | are caller saved, and saving them via a mips16 register would \ | |
760 | probably waste more time than just reloading the value. */ \ | |
761 | if (TARGET_MIPS16) \ | |
762 | { \ | |
763 | fixed_regs[18] = call_used_regs[18] = 1; \ | |
764 | fixed_regs[19] = call_used_regs[19] = 1; \ | |
765 | fixed_regs[20] = call_used_regs[20] = 1; \ | |
766 | fixed_regs[21] = call_used_regs[21] = 1; \ | |
767 | fixed_regs[22] = call_used_regs[22] = 1; \ | |
768 | fixed_regs[23] = call_used_regs[23] = 1; \ | |
769 | fixed_regs[26] = call_used_regs[26] = 1; \ | |
770 | fixed_regs[27] = call_used_regs[27] = 1; \ | |
771 | fixed_regs[30] = call_used_regs[30] = 1; \ | |
772 | } \ | |
516a2dfd | 773 | SUBTARGET_CONDITIONAL_REGISTER_USAGE \ |
e75b25e7 MM |
774 | } \ |
775 | while (0) | |
776 | ||
b2d8cf33 | 777 | /* This is meant to be redefined in the host dependent files. */ |
516a2dfd JW |
778 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE |
779 | ||
7be1e523 RK |
780 | /* Show we can debug even without a frame pointer. */ |
781 | #define CAN_DEBUG_WITHOUT_FP | |
782 | \f | |
e75b25e7 MM |
783 | /* Complain about missing specs and predefines that should be defined in each |
784 | of the target tm files to override the defaults. This is mostly a place- | |
785 | holder until I can get each of the files updated [mm]. */ | |
786 | ||
787 | #if defined(OSF_OS) \ | |
788 | || defined(DECSTATION) \ | |
789 | || defined(SGI_TARGET) \ | |
790 | || defined(MIPS_NEWS) \ | |
791 | || defined(MIPS_SYSV) \ | |
59c94430 | 792 | || defined(MIPS_SVR4) \ |
e75b25e7 MM |
793 | || defined(MIPS_BSD43) |
794 | ||
795 | #ifndef CPP_PREDEFINES | |
796 | #error "Define CPP_PREDEFINES in the appropriate tm.h file" | |
797 | #endif | |
798 | ||
e75b25e7 MM |
799 | #ifndef LIB_SPEC |
800 | #error "Define LIB_SPEC in the appropriate tm.h file" | |
801 | #endif | |
802 | ||
803 | #ifndef STARTFILE_SPEC | |
804 | #error "Define STARTFILE_SPEC in the appropriate tm.h file" | |
805 | #endif | |
806 | ||
807 | #ifndef MACHINE_TYPE | |
808 | #error "Define MACHINE_TYPE in the appropriate tm.h file" | |
809 | #endif | |
810 | #endif | |
811 | ||
59c94430 MM |
812 | /* Tell collect what flags to pass to nm. */ |
813 | #ifndef NM_FLAGS | |
2ce3c6c6 | 814 | #define NM_FLAGS "-Bn" |
59c94430 MM |
815 | #endif |
816 | ||
e75b25e7 MM |
817 | \f |
818 | /* Names to predefine in the preprocessor for this target machine. */ | |
819 | ||
820 | #ifndef CPP_PREDEFINES | |
d4099651 | 821 | #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \ |
65c42379 | 822 | -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \ |
2b57e919 | 823 | -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips" |
e75b25e7 MM |
824 | #endif |
825 | ||
4e88bbcd ILT |
826 | /* Assembler specs. */ |
827 | ||
828 | /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather | |
829 | than gas. */ | |
830 | ||
831 | #define MIPS_AS_ASM_SPEC "\ | |
832 | %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \ | |
c725bd79 | 833 | %{pipe: %e-pipe is not supported} \ |
4e88bbcd ILT |
834 | %{K} %(subtarget_mips_as_asm_spec)" |
835 | ||
836 | /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler | |
837 | rather than gas. It may be overridden by subtargets. */ | |
838 | ||
839 | #ifndef SUBTARGET_MIPS_AS_ASM_SPEC | |
840 | #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}" | |
841 | #endif | |
842 | ||
843 | /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS | |
844 | assembler. */ | |
845 | ||
009da785 EC |
846 | #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}" |
847 | ||
848 | ||
009da785 | 849 | extern int mips_abi; |
0e5a4ad8 EC |
850 | |
851 | #ifndef MIPS_ABI_DEFAULT | |
009da785 EC |
852 | #define MIPS_ABI_DEFAULT ABI_32 |
853 | #endif | |
0e5a4ad8 | 854 | |
009da785 | 855 | #ifndef ABI_GAS_ASM_SPEC |
f9f45c65 | 856 | #define ABI_GAS_ASM_SPEC "" |
0e5a4ad8 | 857 | #endif |
4e88bbcd ILT |
858 | |
859 | /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or | |
860 | GAS_ASM_SPEC as the default, depending upon the value of | |
861 | TARGET_DEFAULT. */ | |
e75b25e7 | 862 | |
bb98bc58 JW |
863 | #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0 |
864 | /* GAS */ | |
bb98bc58 | 865 | |
4e88bbcd ILT |
866 | #define TARGET_ASM_SPEC "\ |
867 | %{mmips-as: %(mips_as_asm_spec)} \ | |
868 | %{!mmips-as: %(gas_asm_spec)}" | |
869 | ||
870 | #else /* not GAS */ | |
871 | ||
872 | #define TARGET_ASM_SPEC "\ | |
873 | %{!mgas: %(mips_as_asm_spec)} \ | |
874 | %{mgas: %(gas_asm_spec)}" | |
875 | ||
876 | #endif /* not GAS */ | |
877 | ||
878 | /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options | |
879 | to the assembler. It may be overridden by subtargets. */ | |
880 | #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC | |
881 | #define SUBTARGET_ASM_OPTIMIZING_SPEC "\ | |
bb98bc58 | 882 | %{noasmopt:-O0} \ |
4e88bbcd ILT |
883 | %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}" |
884 | #endif | |
885 | ||
886 | /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to | |
887 | the assembler. It may be overridden by subtargets. */ | |
888 | #ifndef SUBTARGET_ASM_DEBUGGING_SPEC | |
889 | #define SUBTARGET_ASM_DEBUGGING_SPEC "\ | |
bb98bc58 JW |
890 | %{g} %{g0} %{g1} %{g2} %{g3} \ |
891 | %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ | |
892 | %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ | |
893 | %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ | |
4e88bbcd ILT |
894 | %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}" |
895 | #endif | |
bb98bc58 | 896 | |
4e88bbcd ILT |
897 | /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be |
898 | overridden by subtargets. */ | |
899 | ||
900 | #ifndef SUBTARGET_ASM_SPEC | |
901 | #define SUBTARGET_ASM_SPEC "" | |
bb98bc58 | 902 | #endif |
4e88bbcd ILT |
903 | |
904 | /* ASM_SPEC is the set of arguments to pass to the assembler. */ | |
905 | ||
b2bcb32d | 906 | #undef ASM_SPEC |
4e88bbcd | 907 | #define ASM_SPEC "\ |
0e5a4ad8 | 908 | %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\ |
2bcb2ab3 | 909 | %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ |
4e88bbcd ILT |
910 | %(subtarget_asm_optimizing_spec) \ |
911 | %(subtarget_asm_debugging_spec) \ | |
912 | %{membedded-pic} \ | |
913 | %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \ | |
914 | %(target_asm_spec) \ | |
915 | %(subtarget_asm_spec)" | |
e75b25e7 MM |
916 | |
917 | /* Specify to run a post-processor, mips-tfile after the assembler | |
918 | has run to stuff the mips debug information into the object file. | |
919 | This is needed because the $#!%^ MIPS assembler provides no way | |
a813fadf MM |
920 | of specifying such information in the assembly file. If we are |
921 | cross compiling, disable mips-tfile unless the user specifies | |
922 | -mmips-tfile. */ | |
e75b25e7 MM |
923 | |
924 | #ifndef ASM_FINAL_SPEC | |
bb98bc58 JW |
925 | #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0 |
926 | /* GAS */ | |
31c714e3 | 927 | #define ASM_FINAL_SPEC "\ |
149e4e00 | 928 | %{mmips-as: %{!mno-mips-tfile: \ |
31c714e3 MM |
929 | \n mips-tfile %{v*: -v} \ |
930 | %{K: -I %b.o~} \ | |
931 | %{!K: %{save-temps: -I %b.o~}} \ | |
ab78d4a8 | 932 | %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \ |
31c714e3 | 933 | %{.s:%i} %{!.s:%g.s}}}" |
a813fadf | 934 | |
bb98bc58 JW |
935 | #else |
936 | /* not GAS */ | |
a813fadf | 937 | #define ASM_FINAL_SPEC "\ |
149e4e00 | 938 | %{!mgas: %{!mno-mips-tfile: \ |
a813fadf MM |
939 | \n mips-tfile %{v*: -v} \ |
940 | %{K: -I %b.o~} \ | |
941 | %{!K: %{save-temps: -I %b.o~}} \ | |
942 | %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \ | |
943 | %{.s:%i} %{!.s:%g.s}}}" | |
944 | ||
bb98bc58 | 945 | #endif |
a813fadf | 946 | #endif /* ASM_FINAL_SPEC */ |
e75b25e7 MM |
947 | |
948 | /* Redefinition of libraries used. Mips doesn't support normal | |
949 | UNIX style profiling via calling _mcount. It does offer | |
987ba558 | 950 | profiling that samples the PC, so do what we can... */ |
e75b25e7 MM |
951 | |
952 | #ifndef LIB_SPEC | |
953 | #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc" | |
954 | #endif | |
955 | ||
31c714e3 | 956 | /* Extra switches sometimes passed to the linker. */ |
bb98bc58 JW |
957 | /* ??? The bestGnum will never be passed to the linker, because the gcc driver |
958 | will interpret it as a -b option. */ | |
e75b25e7 MM |
959 | |
960 | #ifndef LINK_SPEC | |
31c714e3 | 961 | #define LINK_SPEC "\ |
120dc6cd | 962 | %(endian_spec) \ |
0e5a4ad8 | 963 | %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \ |
120dc6cd | 964 | %{bestGnum} %{shared} %{non_shared}" |
0e5a4ad8 EC |
965 | #endif /* LINK_SPEC defined */ |
966 | ||
e75b25e7 MM |
967 | |
968 | /* Specs for the compiler proper */ | |
969 | ||
c9db96ce JR |
970 | /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be |
971 | overridden by subtargets. */ | |
972 | #ifndef SUBTARGET_CC1_SPEC | |
973 | #define SUBTARGET_CC1_SPEC "" | |
974 | #endif | |
975 | ||
7dac2f89 EC |
976 | /* Deal with historic options. */ |
977 | #ifndef CC1_CPU_SPEC | |
978 | #define CC1_CPU_SPEC "\ | |
979 | %{!mcpu*: \ | |
980 | %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \ | |
981 | %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \ | |
982 | %{m4650:-march=r4650 -mmad -msingle-float \ | |
983 | %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}" | |
984 | #endif | |
985 | ||
c9db96ce | 986 | /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ |
75dcd8fe MM |
987 | /* Note, we will need to adjust the following if we ever find a MIPS variant |
988 | that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs | |
989 | that show up in this case. */ | |
c9db96ce | 990 | |
e75b25e7 | 991 | #ifndef CC1_SPEC |
31c714e3 | 992 | #define CC1_SPEC "\ |
31c714e3 | 993 | %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ |
7e99e494 | 994 | %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\ |
46299de9 | 995 | %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \ |
516a2dfd | 996 | %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \ |
0e5a4ad8 EC |
997 | %{mips32:-mfp32 -mgp32} \ |
998 | %{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \ | |
46299de9 ILT |
999 | %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \ |
1000 | %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \ | |
3ce1ba83 | 1001 | %{mint64|mlong64|mlong32:-mexplicit-type-size }\ |
75dcd8fe | 1002 | %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \ |
96abdcb1 | 1003 | %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ |
31c714e3 MM |
1004 | %{pic-none: -mno-half-pic} \ |
1005 | %{pic-lib: -mhalf-pic} \ | |
1006 | %{pic-extern: -mhalf-pic} \ | |
1007 | %{pic-calls: -mhalf-pic} \ | |
c9db96ce | 1008 | %{save-temps: } \ |
7dac2f89 EC |
1009 | %(subtarget_cc1_spec) \ |
1010 | %(cc1_cpu_spec)" | |
e75b25e7 MM |
1011 | #endif |
1012 | ||
4e88bbcd ILT |
1013 | /* Preprocessor specs. */ |
1014 | ||
8a13c092 AO |
1015 | /* Rules for SIZE_TYPE and PTRDIFF_TYPE are: |
1016 | ||
1017 | both gp64 and long64 (not the options, but the corresponding flags, | |
1018 | so defaults came into play) are required in order to have `long' in | |
1019 | SIZE_TYPE and PTRDIFF_TYPE. | |
1020 | ||
1021 | on eabi, -mips1, -mips2 and -mips32 disable gp64, whereas mips3, | |
1022 | -mips4, -mips5 and -mips64 enable it. | |
1023 | ||
1024 | on other ABIs, -mips* options do not affect gp32/64, but the | |
1025 | default ISA affects the default gp size. | |
1026 | ||
1027 | -mgp32 disables gp64, whereas -mgp64 enables it. | |
1028 | ||
1029 | on eabi, gp64 implies long64. | |
1030 | ||
1031 | -mlong64, and -mabi=64 are the only other ways to enable long64. | |
1032 | ||
1033 | */ | |
1034 | ||
f9f45c65 EC |
1035 | #if MIPS_ISA_DEFAULT != 3 && MIPS_ISA_DEFAULT != 4 && MIPS_ISA_DEFAULT != 5 && MIPS_ISA_DEFAULT != 64 |
1036 | ||
1037 | /* 32-bit cases first. */ | |
1038 | ||
1039 | #if MIPS_ABI_DEFAULT == ABI_EABI | |
5faae4f7 AO |
1040 | #define LONG_MAX_SPEC "\ |
1041 | %{mlong64:-D__LONG_MAX__=9223372036854775807L}\ | |
1042 | %{!mlong64:\ | |
1043 | %{mabi=eabi|!mabi=*:\ | |
1044 | %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \ | |
1045 | %{mips3|mips4|mips5|mips64|mgp64: \ | |
1046 | -D__LONG_MAX__=9223372036854775807L}}}}}}}} \ | |
1047 | " | |
1048 | #else /* ABI_DEFAULT != ABI_EABI */ | |
1049 | #define LONG_MAX_SPEC "\ | |
1050 | %{mlong64:-D__LONG_MAX__=9223372036854775807L}\ | |
1051 | %{!mlong64:\ | |
1052 | %{mabi=eabi:\ | |
1053 | %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \ | |
1054 | %{mips3|mips4|mips5|mips64|mgp64: \ | |
1055 | -D__LONG_MAX__=9223372036854775807L}}}}}}}} \ | |
1056 | " | |
f9f45c65 EC |
1057 | #endif |
1058 | ||
f9f45c65 EC |
1059 | #else |
1060 | ||
1061 | /* 64-bit default ISA. */ | |
f9f45c65 | 1062 | #if MIPS_ABI_DEFAULT == ABI_EABI |
5faae4f7 AO |
1063 | #define LONG_MAX_SPEC "\ |
1064 | %{mlong64:-D__LONG_MAX__=9223372036854775807L}\ | |
1065 | %{!mlong64:\ | |
1066 | %{mabi=eabi|!mabi=*:\ | |
1067 | %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \ | |
1068 | -D__LONG_MAX__=9223372036854775807L}}}}}}}\ | |
1069 | " | |
1070 | #else /* ABI_DEFAULT != ABI_EABI */ | |
1071 | #define LONG_MAX_SPEC "\ | |
1072 | %{mlong64:-D__LONG_MAX__=9223372036854775807L}\ | |
1073 | %{!mlong64:\ | |
1074 | %{mabi=eabi:\ | |
1075 | %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \ | |
1076 | -D__LONG_MAX__=9223372036854775807L}}}}}}}\ | |
1077 | " | |
f9f45c65 EC |
1078 | #endif |
1079 | ||
4e88bbcd ILT |
1080 | #endif |
1081 | ||
1082 | /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be | |
1083 | overridden by subtargets. */ | |
1084 | #ifndef SUBTARGET_CPP_SPEC | |
1085 | #define SUBTARGET_CPP_SPEC "" | |
1086 | #endif | |
1087 | ||
75dcd8fe MM |
1088 | /* Define appropriate macros for fpr register size. */ |
1089 | #ifndef CPP_FPR_SPEC | |
1090 | #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64) | |
1091 | #define CPP_FPR_SPEC "-D__mips_fpr=64" | |
1092 | #else | |
1093 | #define CPP_FPR_SPEC "-D__mips_fpr=32" | |
1094 | #endif | |
1095 | #endif | |
1096 | ||
64b172fe RO |
1097 | /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent |
1098 | of the source file extension. */ | |
b2bcb32d | 1099 | #undef CPLUSPLUS_CPP_SPEC |
64b172fe RO |
1100 | #define CPLUSPLUS_CPP_SPEC "\ |
1101 | -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \ | |
1102 | %(cpp) \ | |
1103 | " | |
4e88bbcd | 1104 | /* CPP_SPEC is the set of arguments to pass to the preprocessor. */ |
e75b25e7 MM |
1105 | |
1106 | #ifndef CPP_SPEC | |
31c714e3 | 1107 | #define CPP_SPEC "\ |
0002d808 | 1108 | %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \ |
64b172fe RO |
1109 | %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ |
1110 | %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \ | |
4e88bbcd | 1111 | %(subtarget_cpp_size_spec) \ |
192616a4 RK |
1112 | %{mips3:-U__mips -D__mips=3 -D__mips64} \ |
1113 | %{mips4:-U__mips -D__mips=4 -D__mips64} \ | |
0e5a4ad8 EC |
1114 | %{mips32:-U__mips -D__mips=32} \ |
1115 | %{mips64:-U__mips -D__mips=64 -D__mips64} \ | |
192616a4 | 1116 | %{mgp32:-U__mips64} %{mgp64:-D__mips64} \ |
75dcd8fe | 1117 | %{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \ |
54efdaa4 JW |
1118 | %{msingle-float:%{!msoft-float:-D__mips_single_float}} \ |
1119 | %{m4650:%{!msoft-float:-D__mips_single_float}} \ | |
293a36eb ILT |
1120 | %{msoft-float:-D__mips_soft_float} \ |
1121 | %{mabi=eabi:-D__mips_eabi} \ | |
2bcb2ab3 | 1122 | %{mips16:%{!mno-mips16:-D__mips16}} \ |
96abdcb1 | 1123 | %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \ |
4e88bbcd | 1124 | %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \ |
4eb66248 | 1125 | %(long_max_spec) \ |
4e88bbcd ILT |
1126 | %(subtarget_cpp_spec) " |
1127 | #endif | |
1128 | ||
1129 | /* This macro defines names of additional specifications to put in the specs | |
1130 | that can be used in various specifications like CC1_SPEC. Its definition | |
1131 | is an initializer with a subgrouping for each command option. | |
1132 | ||
1133 | Each subgrouping contains a string constant, that defines the | |
1134 | specification name, and a string constant that used by the GNU CC driver | |
1135 | program. | |
1136 | ||
1137 | Do not define this macro if it does not need to do anything. */ | |
1138 | ||
1139 | #define EXTRA_SPECS \ | |
829245be | 1140 | { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ |
7a38df19 | 1141 | { "cc1_cpu_spec", CC1_CPU_SPEC}, \ |
829245be | 1142 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
829245be | 1143 | { "long_max_spec", LONG_MAX_SPEC }, \ |
75dcd8fe | 1144 | { "cpp_fpr_spec", CPP_FPR_SPEC }, \ |
829245be KG |
1145 | { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \ |
1146 | { "gas_asm_spec", GAS_ASM_SPEC }, \ | |
0e5a4ad8 | 1147 | { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, \ |
829245be KG |
1148 | { "target_asm_spec", TARGET_ASM_SPEC }, \ |
1149 | { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \ | |
1150 | { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \ | |
1151 | { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ | |
1152 | { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ | |
120dc6cd | 1153 | { "endian_spec", ENDIAN_SPEC }, \ |
4e88bbcd ILT |
1154 | SUBTARGET_EXTRA_SPECS |
1155 | ||
1156 | #ifndef SUBTARGET_EXTRA_SPECS | |
1157 | #define SUBTARGET_EXTRA_SPECS | |
e75b25e7 MM |
1158 | #endif |
1159 | ||
1160 | /* If defined, this macro is an additional prefix to try after | |
1161 | `STANDARD_EXEC_PREFIX'. */ | |
1162 | ||
1163 | #ifndef MD_EXEC_PREFIX | |
31c714e3 | 1164 | #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/" |
e75b25e7 MM |
1165 | #endif |
1166 | ||
59c94430 MM |
1167 | #ifndef MD_STARTFILE_PREFIX |
1168 | #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/" | |
1169 | #endif | |
1170 | ||
e75b25e7 MM |
1171 | \f |
1172 | /* Print subsidiary information on the compiler version in use. */ | |
1173 | ||
42dee4c7 | 1174 | #define MIPS_VERSION "[AL 1.1, MM 40]" |
e75b25e7 MM |
1175 | |
1176 | #ifndef MACHINE_TYPE | |
1177 | #define MACHINE_TYPE "BSD Mips" | |
1178 | #endif | |
1179 | ||
1180 | #ifndef TARGET_VERSION_INTERNAL | |
1181 | #define TARGET_VERSION_INTERNAL(STREAM) \ | |
1182 | fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE) | |
1183 | #endif | |
1184 | ||
1185 | #ifndef TARGET_VERSION | |
1186 | #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr) | |
1187 | #endif | |
1188 | ||
1189 | \f | |
1190 | #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */ | |
1191 | #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */ | |
1192 | #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */ | |
1193 | ||
1194 | #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ | |
fe0986b4 | 1195 | #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG |
e75b25e7 MM |
1196 | #endif |
1197 | ||
59c94430 MM |
1198 | /* By default, turn on GDB extensions. */ |
1199 | #define DEFAULT_GDB_EXTENSIONS 1 | |
1200 | ||
e75b25e7 MM |
1201 | /* If we are passing smuggling stabs through the MIPS ECOFF object |
1202 | format, put a comment in front of the .stab<x> operation so | |
1203 | that the MIPS assembler does not choke. The mips-tfile program | |
1204 | will correctly put the stab into the object file. */ | |
1205 | ||
78d057d8 HPN |
1206 | #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t") |
1207 | #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t") | |
1208 | #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t") | |
e75b25e7 | 1209 | |
6ae1498b JW |
1210 | /* Local compiler-generated symbols must have a prefix that the assembler |
1211 | understands. By default, this is $, although some targets (e.g., | |
987ba558 | 1212 | NetBSD-ELF) need to override this. */ |
6ae1498b JW |
1213 | |
1214 | #ifndef LOCAL_LABEL_PREFIX | |
1215 | #define LOCAL_LABEL_PREFIX "$" | |
1216 | #endif | |
1217 | ||
1218 | /* By default on the mips, external symbols do not have an underscore | |
987ba558 | 1219 | prepended, but some targets (e.g., NetBSD) require this. */ |
6ae1498b JW |
1220 | |
1221 | #ifndef USER_LABEL_PREFIX | |
1222 | #define USER_LABEL_PREFIX "" | |
1223 | #endif | |
1224 | ||
e75b25e7 MM |
1225 | /* Forward references to tags are allowed. */ |
1226 | #define SDB_ALLOW_FORWARD_REFERENCES | |
1227 | ||
1228 | /* Unknown tags are also allowed. */ | |
1229 | #define SDB_ALLOW_UNKNOWN_REFERENCES | |
1230 | ||
1231 | /* On Sun 4, this limit is 2048. We use 1500 to be safe, | |
1232 | since the length can run past this up to a continuation point. */ | |
44404b8b | 1233 | #undef DBX_CONTIN_LENGTH |
e75b25e7 MM |
1234 | #define DBX_CONTIN_LENGTH 1500 |
1235 | ||
987ba558 | 1236 | /* How to renumber registers for dbx and gdb. */ |
e75b25e7 MM |
1237 | #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ] |
1238 | ||
c8cc5c4a | 1239 | /* The mapping from gcc register number to DWARF 2 CFA column number. |
0021b564 JM |
1240 | This mapping does not allow for tracking register 0, since SGI's broken |
1241 | dwarf reader thinks column 0 is used for the frame address, but since | |
1242 | register 0 is fixed this is not a problem. */ | |
469ac993 | 1243 | #define DWARF_FRAME_REGNUM(REG) \ |
0021b564 | 1244 | (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG) |
c8cc5c4a JM |
1245 | |
1246 | /* The DWARF 2 CFA column which tracks the return address. */ | |
1247 | #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1) | |
e75b25e7 | 1248 | |
469ac993 | 1249 | /* Before the prologue, RA lives in r31. */ |
c5c76735 | 1250 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31) |
469ac993 | 1251 | |
9e800206 | 1252 | /* Describe how we implement __builtin_eh_return. */ |
282cb01b | 1253 | #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) |
9e800206 RH |
1254 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) |
1255 | ||
7dac2f89 | 1256 | /* Offsets recorded in opcodes are a multiple of this alignment factor. |
b3276c7a GK |
1257 | The default for this in 64-bit mode is 8, which causes problems with |
1258 | SFmode register saves. */ | |
1259 | #define DWARF_CIE_DATA_ALIGNMENT 4 | |
1260 | ||
e75b25e7 MM |
1261 | /* Overrides for the COFF debug format. */ |
1262 | #define PUT_SDB_SCL(a) \ | |
1263 | do { \ | |
1264 | extern FILE *asm_out_text_file; \ | |
1265 | fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \ | |
1266 | } while (0) | |
1267 | ||
1268 | #define PUT_SDB_INT_VAL(a) \ | |
1269 | do { \ | |
1270 | extern FILE *asm_out_text_file; \ | |
e59f7d3d KG |
1271 | fprintf (asm_out_text_file, "\t.val\t"); \ |
1272 | fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \ | |
1273 | fprintf (asm_out_text_file, ";"); \ | |
e75b25e7 MM |
1274 | } while (0) |
1275 | ||
1276 | #define PUT_SDB_VAL(a) \ | |
1277 | do { \ | |
1278 | extern FILE *asm_out_text_file; \ | |
1279 | fputs ("\t.val\t", asm_out_text_file); \ | |
1280 | output_addr_const (asm_out_text_file, (a)); \ | |
1281 | fputc (';', asm_out_text_file); \ | |
1282 | } while (0) | |
1283 | ||
1284 | #define PUT_SDB_DEF(a) \ | |
1285 | do { \ | |
1286 | extern FILE *asm_out_text_file; \ | |
b82b0773 MM |
1287 | fprintf (asm_out_text_file, "\t%s.def\t", \ |
1288 | (TARGET_GAS) ? "" : "#"); \ | |
e75b25e7 MM |
1289 | ASM_OUTPUT_LABELREF (asm_out_text_file, a); \ |
1290 | fputc (';', asm_out_text_file); \ | |
1291 | } while (0) | |
1292 | ||
1293 | #define PUT_SDB_PLAIN_DEF(a) \ | |
1294 | do { \ | |
1295 | extern FILE *asm_out_text_file; \ | |
b82b0773 MM |
1296 | fprintf (asm_out_text_file, "\t%s.def\t.%s;", \ |
1297 | (TARGET_GAS) ? "" : "#", (a)); \ | |
e75b25e7 MM |
1298 | } while (0) |
1299 | ||
1300 | #define PUT_SDB_ENDEF \ | |
1301 | do { \ | |
1302 | extern FILE *asm_out_text_file; \ | |
1303 | fprintf (asm_out_text_file, "\t.endef\n"); \ | |
1304 | } while (0) | |
1305 | ||
1306 | #define PUT_SDB_TYPE(a) \ | |
1307 | do { \ | |
1308 | extern FILE *asm_out_text_file; \ | |
1309 | fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \ | |
1310 | } while (0) | |
1311 | ||
1312 | #define PUT_SDB_SIZE(a) \ | |
1313 | do { \ | |
1314 | extern FILE *asm_out_text_file; \ | |
e59f7d3d KG |
1315 | fprintf (asm_out_text_file, "\t.size\t"); \ |
1316 | fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \ | |
1317 | fprintf (asm_out_text_file, ";"); \ | |
e75b25e7 MM |
1318 | } while (0) |
1319 | ||
1320 | #define PUT_SDB_DIM(a) \ | |
1321 | do { \ | |
1322 | extern FILE *asm_out_text_file; \ | |
1323 | fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \ | |
1324 | } while (0) | |
1325 | ||
1326 | #ifndef PUT_SDB_START_DIM | |
1327 | #define PUT_SDB_START_DIM \ | |
1328 | do { \ | |
1329 | extern FILE *asm_out_text_file; \ | |
1330 | fprintf (asm_out_text_file, "\t.dim\t"); \ | |
1331 | } while (0) | |
1332 | #endif | |
1333 | ||
1334 | #ifndef PUT_SDB_NEXT_DIM | |
1335 | #define PUT_SDB_NEXT_DIM(a) \ | |
1336 | do { \ | |
1337 | extern FILE *asm_out_text_file; \ | |
1338 | fprintf (asm_out_text_file, "%d,", a); \ | |
1339 | } while (0) | |
1340 | #endif | |
1341 | ||
1342 | #ifndef PUT_SDB_LAST_DIM | |
1343 | #define PUT_SDB_LAST_DIM(a) \ | |
1344 | do { \ | |
1345 | extern FILE *asm_out_text_file; \ | |
1346 | fprintf (asm_out_text_file, "%d;", a); \ | |
1347 | } while (0) | |
1348 | #endif | |
1349 | ||
1350 | #define PUT_SDB_TAG(a) \ | |
1351 | do { \ | |
1352 | extern FILE *asm_out_text_file; \ | |
1353 | fprintf (asm_out_text_file, "\t.tag\t"); \ | |
1354 | ASM_OUTPUT_LABELREF (asm_out_text_file, a); \ | |
1355 | fputc (';', asm_out_text_file); \ | |
1356 | } while (0) | |
1357 | ||
1358 | /* For block start and end, we create labels, so that | |
1359 | later we can figure out where the correct offset is. | |
1360 | The normal .ent/.end serve well enough for functions, | |
1361 | so those are just commented out. */ | |
1362 | ||
1363 | #define PUT_SDB_BLOCK_START(LINE) \ | |
1364 | do { \ | |
1365 | extern FILE *asm_out_text_file; \ | |
1366 | fprintf (asm_out_text_file, \ | |
6ae1498b JW |
1367 | "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \ |
1368 | LOCAL_LABEL_PREFIX, \ | |
e75b25e7 | 1369 | sdb_label_count, \ |
b82b0773 | 1370 | (TARGET_GAS) ? "" : "#", \ |
6ae1498b | 1371 | LOCAL_LABEL_PREFIX, \ |
e75b25e7 MM |
1372 | sdb_label_count, \ |
1373 | (LINE)); \ | |
1374 | sdb_label_count++; \ | |
1375 | } while (0) | |
1376 | ||
1377 | #define PUT_SDB_BLOCK_END(LINE) \ | |
1378 | do { \ | |
1379 | extern FILE *asm_out_text_file; \ | |
1380 | fprintf (asm_out_text_file, \ | |
6ae1498b JW |
1381 | "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \ |
1382 | LOCAL_LABEL_PREFIX, \ | |
e75b25e7 | 1383 | sdb_label_count, \ |
b82b0773 | 1384 | (TARGET_GAS) ? "" : "#", \ |
6ae1498b | 1385 | LOCAL_LABEL_PREFIX, \ |
e75b25e7 MM |
1386 | sdb_label_count, \ |
1387 | (LINE)); \ | |
1388 | sdb_label_count++; \ | |
1389 | } while (0) | |
1390 | ||
1391 | #define PUT_SDB_FUNCTION_START(LINE) | |
1392 | ||
a642a781 RK |
1393 | #define PUT_SDB_FUNCTION_END(LINE) \ |
1394 | do { \ | |
1395 | extern FILE *asm_out_text_file; \ | |
1396 | ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \ | |
1397 | } while (0) | |
e75b25e7 MM |
1398 | |
1399 | #define PUT_SDB_EPILOGUE_END(NAME) | |
1400 | ||
cc694a81 DE |
1401 | #define PUT_SDB_SRC_FILE(FILENAME) \ |
1402 | do { \ | |
1403 | extern FILE *asm_out_text_file; \ | |
1404 | output_file_directive (asm_out_text_file, (FILENAME)); \ | |
1405 | } while (0) | |
1406 | ||
e75b25e7 MM |
1407 | #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ |
1408 | sprintf ((BUFFER), ".%dfake", (NUMBER)); | |
1409 | ||
ab78d4a8 MM |
1410 | /* Correct the offset of automatic variables and arguments. Note that |
1411 | the MIPS debug format wants all automatic variables and arguments | |
1412 | to be in terms of the virtual frame pointer (stack pointer before | |
1413 | any adjustment in the function), while the MIPS 3.0 linker wants | |
1414 | the frame pointer to be the stack pointer after the initial | |
1415 | adjustment. */ | |
e75b25e7 | 1416 | |
f5963e61 JL |
1417 | #define DEBUGGER_AUTO_OFFSET(X) \ |
1418 | mips_debugger_offset (X, (HOST_WIDE_INT) 0) | |
1419 | #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ | |
1420 | mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) | |
31c714e3 MM |
1421 | |
1422 | /* Tell collect that the object format is ECOFF */ | |
1423 | #ifndef OBJECT_FORMAT_ROSE | |
1424 | #define OBJECT_FORMAT_COFF /* Object file looks like COFF */ | |
1425 | #define EXTENDED_COFF /* ECOFF, not normal coff */ | |
1426 | #endif | |
e75b25e7 MM |
1427 | \f |
1428 | /* Target machine storage layout */ | |
1429 | ||
1430 | /* Define this if most significant bit is lowest numbered | |
1431 | in instructions that operate on numbered bit-fields. | |
1432 | */ | |
4851a75c | 1433 | #define BITS_BIG_ENDIAN 0 |
e75b25e7 | 1434 | |
987ba558 | 1435 | /* Define this if most significant byte of a word is the lowest numbered. */ |
96abdcb1 | 1436 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
e75b25e7 | 1437 | |
987ba558 | 1438 | /* Define this if most significant word of a multiword number is the lowest. */ |
96abdcb1 | 1439 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
e75b25e7 | 1440 | |
96abdcb1 ILT |
1441 | /* Define this to set the endianness to use in libgcc2.c, which can |
1442 | not depend on target_flags. */ | |
1443 | #if !defined(MIPSEL) && !defined(__MIPSEL__) | |
1444 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
e75b25e7 | 1445 | #else |
96abdcb1 | 1446 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 |
e75b25e7 MM |
1447 | #endif |
1448 | ||
876c09d3 | 1449 | #define MAX_BITS_PER_WORD 64 |
e75b25e7 MM |
1450 | |
1451 | /* Width of a word, in units (bytes). */ | |
456f6501 | 1452 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
ef0e53ce | 1453 | #define MIN_UNITS_PER_WORD 4 |
876c09d3 JW |
1454 | |
1455 | /* For MIPS, width of a floating point register. */ | |
456f6501 | 1456 | #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) |
e75b25e7 | 1457 | |
3f26edaa RS |
1458 | /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is |
1459 | the next available register. */ | |
1460 | #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) | |
1461 | ||
1462 | /* The largest size of value that can be held in floating-point registers. */ | |
4d72536e RS |
1463 | #define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG) |
1464 | ||
1465 | /* The number of bytes in a double. */ | |
1466 | #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) | |
3f26edaa | 1467 | |
e75b25e7 MM |
1468 | /* A C expression for the size in bits of the type `int' on the |
1469 | target machine. If you don't define this, the default is one | |
1470 | word. */ | |
456f6501 | 1471 | #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32) |
876c09d3 JW |
1472 | |
1473 | /* Tell the preprocessor the maximum size of wchar_t. */ | |
1474 | #ifndef MAX_WCHAR_TYPE_SIZE | |
1475 | #ifndef WCHAR_TYPE_SIZE | |
16c484c7 | 1476 | #define MAX_WCHAR_TYPE_SIZE 64 |
876c09d3 JW |
1477 | #endif |
1478 | #endif | |
e75b25e7 MM |
1479 | |
1480 | /* A C expression for the size in bits of the type `short' on the | |
1481 | target machine. If you don't define this, the default is half a | |
1482 | word. (If this would be less than one storage unit, it is | |
1483 | rounded up to one unit.) */ | |
1484 | #define SHORT_TYPE_SIZE 16 | |
1485 | ||
1486 | /* A C expression for the size in bits of the type `long' on the | |
1487 | target machine. If you don't define this, the default is one | |
1488 | word. */ | |
456f6501 | 1489 | #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) |
876c09d3 | 1490 | #define MAX_LONG_TYPE_SIZE 64 |
e75b25e7 MM |
1491 | |
1492 | /* A C expression for the size in bits of the type `long long' on the | |
1493 | target machine. If you don't define this, the default is two | |
1494 | words. */ | |
923d630e | 1495 | #define LONG_LONG_TYPE_SIZE 64 |
e75b25e7 | 1496 | |
e75b25e7 MM |
1497 | /* A C expression for the size in bits of the type `float' on the |
1498 | target machine. If you don't define this, the default is one | |
1499 | word. */ | |
1500 | #define FLOAT_TYPE_SIZE 32 | |
1501 | ||
1502 | /* A C expression for the size in bits of the type `double' on the | |
1503 | target machine. If you don't define this, the default is two | |
1504 | words. */ | |
1505 | #define DOUBLE_TYPE_SIZE 64 | |
1506 | ||
1507 | /* A C expression for the size in bits of the type `long double' on | |
1508 | the target machine. If you don't define this, the default is two | |
1509 | words. */ | |
1510 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
1511 | ||
1512 | /* Width in bits of a pointer. | |
1513 | See also the macro `Pmode' defined below. */ | |
1eeed24e | 1514 | #ifndef POINTER_SIZE |
456f6501 | 1515 | #define POINTER_SIZE (Pmode == DImode ? 64 : 32) |
1eeed24e | 1516 | #endif |
e75b25e7 MM |
1517 | |
1518 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ | |
456f6501 | 1519 | #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32) |
e75b25e7 MM |
1520 | |
1521 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
0b51254d AO |
1522 | #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \ |
1523 | || mips_abi == ABI_64 \ | |
1524 | || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32) | |
e75b25e7 MM |
1525 | |
1526 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
1527 | #define FUNCTION_BOUNDARY 32 | |
1528 | ||
1529 | /* Alignment of field after `int : 0' in a structure. */ | |
9e95597a | 1530 | #define EMPTY_FIELD_BOUNDARY 32 |
e75b25e7 MM |
1531 | |
1532 | /* Every structure's size must be a multiple of this. */ | |
1533 | /* 8 is observed right on a DECstation and on riscos 4.02. */ | |
1534 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
1535 | ||
1536 | /* There is no point aligning anything to a rounder boundary than this. */ | |
1537 | #define BIGGEST_ALIGNMENT 64 | |
1538 | ||
31c714e3 | 1539 | /* Set this nonzero if move instructions will actually fail to work |
e75b25e7 | 1540 | when given unaligned data. */ |
31c714e3 | 1541 | #define STRICT_ALIGNMENT 1 |
e75b25e7 MM |
1542 | |
1543 | /* Define this if you wish to imitate the way many other C compilers | |
1544 | handle alignment of bitfields and the structures that contain | |
1545 | them. | |
1546 | ||
1547 | The behavior is that the type written for a bitfield (`int', | |
1548 | `short', or other integer type) imposes an alignment for the | |
1549 | entire structure, as if the structure really did contain an | |
1550 | ordinary field of that type. In addition, the bitfield is placed | |
1551 | within the structure so that it would fit within such a field, | |
1552 | not crossing a boundary for it. | |
1553 | ||
1554 | Thus, on most machines, a bitfield whose type is written as `int' | |
1555 | would not cross a four-byte boundary, and would force four-byte | |
1556 | alignment for the whole structure. (The alignment used may not | |
1557 | be four bytes; it is controlled by the other alignment | |
1558 | parameters.) | |
1559 | ||
1560 | If the macro is defined, its definition should be a C expression; | |
1561 | a nonzero value for the expression enables this behavior. */ | |
1562 | ||
1563 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
1564 | ||
1565 | /* If defined, a C expression to compute the alignment given to a | |
1566 | constant that is being placed in memory. CONSTANT is the constant | |
1567 | and ALIGN is the alignment that the object would ordinarily have. | |
1568 | The value of this macro is used instead of that alignment to align | |
1569 | the object. | |
1570 | ||
1571 | If this macro is not defined, then ALIGN is used. | |
1572 | ||
1573 | The typical use of this macro is to increase alignment for string | |
1574 | constants to be word aligned so that `strcpy' calls that copy | |
1575 | constants can be done inline. */ | |
1576 | ||
1577 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
1578 | ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ | |
75131237 | 1579 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) |
e75b25e7 MM |
1580 | |
1581 | /* If defined, a C expression to compute the alignment for a static | |
1582 | variable. TYPE is the data type, and ALIGN is the alignment that | |
1583 | the object would ordinarily have. The value of this macro is used | |
1584 | instead of that alignment to align the object. | |
1585 | ||
1586 | If this macro is not defined, then ALIGN is used. | |
1587 | ||
1588 | One use of this macro is to increase alignment of medium-size | |
1589 | data to make it all fit in fewer cache lines. Another is to | |
1590 | cause character arrays to be word-aligned so that `strcpy' calls | |
1591 | that copy constants to character arrays can be done inline. */ | |
1592 | ||
1593 | #undef DATA_ALIGNMENT | |
1594 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
1595 | ((((ALIGN) < BITS_PER_WORD) \ | |
1596 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
1597 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
1598 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
1599 | ||
f5c8ac96 CP |
1600 | |
1601 | /* Force right-alignment for small varargs in 32 bit little_endian mode */ | |
1602 | ||
0e5a4ad8 EC |
1603 | #define PAD_VARARGS_DOWN (TARGET_64BIT \ |
1604 | || mips_abi == ABI_MEABI \ | |
1605 | ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN) | |
f5c8ac96 | 1606 | |
e75b25e7 MM |
1607 | /* Define this macro if an argument declared as `char' or `short' in a |
1608 | prototype should actually be passed as an `int'. In addition to | |
1609 | avoiding errors in certain cases of mismatch, it also makes for | |
987ba558 | 1610 | better code on certain machines. */ |
e75b25e7 | 1611 | |
cb560352 | 1612 | #define PROMOTE_PROTOTYPES 1 |
e75b25e7 | 1613 | |
9a63901f RK |
1614 | /* Define if operations between registers always perform the operation |
1615 | on the full register even if a narrower mode is specified. */ | |
1616 | #define WORD_REGISTER_OPERATIONS | |
1617 | ||
1618 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1619 | will either zero-extend or sign-extend. The value of this macro should | |
1620 | be the code that says which one of the two operations is implicitly | |
7dac2f89 | 1621 | done, NIL if none. |
a872728c JL |
1622 | |
1623 | When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode | |
1624 | moves. All other referces are zero extended. */ | |
1625 | #define LOAD_EXTEND_OP(MODE) \ | |
1626 | (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ | |
1627 | ? SIGN_EXTEND : ZERO_EXTEND) | |
2bcb2ab3 GK |
1628 | |
1629 | /* Define this macro if it is advisable to hold scalars in registers | |
7dac2f89 | 1630 | in a wider mode than that declared by the program. In such cases, |
2bcb2ab3 GK |
1631 | the value is constrained to be within the bounds of the declared |
1632 | type, but kept valid in the wider mode. The signedness of the | |
1633 | extension may differ from that of the type. | |
1634 | ||
1635 | We promote any value smaller than SImode up to SImode. We don't | |
1636 | want to promote to DImode when in 64 bit mode, because that would | |
1637 | prevent us from using the faster SImode multiply and divide | |
1638 | instructions. */ | |
1639 | ||
1640 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1641 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
1642 | && GET_MODE_SIZE (MODE) < 4) \ | |
1643 | (MODE) = SImode; | |
1644 | ||
1645 | /* Define this if function arguments should also be promoted using the above | |
1646 | procedure. */ | |
1647 | ||
1648 | #define PROMOTE_FUNCTION_ARGS | |
1649 | ||
1650 | /* Likewise, if the function return value is promoted. */ | |
1651 | ||
1652 | #define PROMOTE_FUNCTION_RETURN | |
e75b25e7 MM |
1653 | \f |
1654 | /* Standard register usage. */ | |
1655 | ||
1656 | /* Number of actual hardware registers. | |
1657 | The hardware registers are assigned numbers for the compiler | |
1658 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
1659 | All registers that the compiler knows about must be given numbers, | |
1660 | even those that are not normally considered general registers. | |
1661 | ||
225b8835 | 1662 | On the Mips, we have 32 integer registers, 32 floating point |
b8eb88d0 | 1663 | registers, 8 condition code registers, and the special registers |
d604bca3 MH |
1664 | hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32 |
1665 | COP2 registers, and 32 COp3 registers. (COP1 is the floating-point | |
1666 | processor.) The 8 condition code registers are only used if | |
1667 | mips_isa >= 4. The hilo register is only used in 64 bit mode. It | |
1668 | represents a 64 bit value stored as two 32 bit values in the hi and | |
1669 | lo registers; this is the result of the mult instruction. rap is a | |
1670 | pointer to the stack where the return address reg ($31) was stored. | |
1671 | This is needed for C++ exception handling. */ | |
e75b25e7 | 1672 | |
d604bca3 | 1673 | #define FIRST_PSEUDO_REGISTER 176 |
e75b25e7 MM |
1674 | |
1675 | /* 1 for registers that have pervasive standard uses | |
1676 | and are not available for the register allocator. | |
1677 | ||
1678 | On the MIPS, see conventions, page D-2 */ | |
1679 | ||
d604bca3 MH |
1680 | /* Regarding coprocessor registers: without evidence to the contrary, |
1681 | it's best to assume that each coprocessor register has a unique | |
1682 | use. This can be overridden, in, e.g., override_options() or | |
1683 | CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate | |
1684 | for a particular target. */ | |
1685 | ||
e75b25e7 MM |
1686 | #define FIXED_REGISTERS \ |
1687 | { \ | |
1688 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1689 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \ | |
1690 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1691 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
d604bca3 MH |
1692 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ |
1693 | /* COP0 registers */ \ | |
1694 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1695 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1696 | /* COP2 registers */ \ | |
1697 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1698 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1699 | /* COP3 registers */ \ | |
1700 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1701 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ | |
e75b25e7 MM |
1702 | } |
1703 | ||
1704 | ||
1705 | /* 1 for registers not available across function calls. | |
1706 | These must include the FIXED_REGISTERS and also any | |
1707 | registers that can be used without being saved. | |
1708 | The latter must include the registers where values are returned | |
1709 | and the register where structure-value addresses are passed. | |
1710 | Aside from that, you can include as many other registers as you like. */ | |
1711 | ||
1712 | #define CALL_USED_REGISTERS \ | |
1713 | { \ | |
1714 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1715 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ | |
1716 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1717 | 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
d604bca3 MH |
1718 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \ |
1719 | /* COP0 registers */ \ | |
1720 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1721 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1722 | /* COP2 registers */ \ | |
1723 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1724 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1725 | /* COP3 registers */ \ | |
1726 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1727 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ | |
e75b25e7 MM |
1728 | } |
1729 | ||
2ca2d9ee EC |
1730 | /* Like `CALL_USED_REGISTERS' but used to overcome a historical |
1731 | problem which makes CALL_USED_REGISTERS *always* include | |
1732 | all the FIXED_REGISTERS. Until this problem has been | |
1733 | resolved this macro can be used to overcome this situation. | |
1734 | In particular, block_propagate() requires this list | |
1735 | be acurate, or we can remove registers which should be live. | |
1736 | This macro is used in regs_invalidated_by_call. */ | |
1737 | ||
1738 | ||
1739 | #define CALL_REALLY_USED_REGISTERS \ | |
1740 | { /* General registers. */ \ | |
1741 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1742 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \ | |
1743 | /* Floating-point registers. */ \ | |
1744 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1745 | 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1746 | /* Others. */ \ | |
d604bca3 MH |
1747 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \ |
1748 | /* COP0 registers */ \ | |
1749 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1750 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1751 | /* COP2 registers */ \ | |
1752 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1753 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1754 | /* COP3 registers */ \ | |
1755 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1756 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ | |
2ca2d9ee | 1757 | } |
e75b25e7 MM |
1758 | |
1759 | /* Internal macros to classify a register number as to whether it's a | |
1760 | general purpose register, a floating point register, a | |
516a2dfd | 1761 | multiply/divide register, or a status register. */ |
e75b25e7 MM |
1762 | |
1763 | #define GP_REG_FIRST 0 | |
1764 | #define GP_REG_LAST 31 | |
1765 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
1766 | #define GP_DBX_FIRST 0 | |
1767 | ||
1768 | #define FP_REG_FIRST 32 | |
1769 | #define FP_REG_LAST 63 | |
1770 | #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
1771 | #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) | |
1772 | ||
1773 | #define MD_REG_FIRST 64 | |
225b8835 | 1774 | #define MD_REG_LAST 66 |
e75b25e7 MM |
1775 | #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) |
1776 | ||
225b8835 | 1777 | #define ST_REG_FIRST 67 |
b8eb88d0 | 1778 | #define ST_REG_LAST 74 |
e75b25e7 MM |
1779 | #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) |
1780 | ||
b8eb88d0 | 1781 | #define RAP_REG_NUM 75 |
39dffea3 | 1782 | |
d604bca3 MH |
1783 | #define COP0_REG_FIRST 80 |
1784 | #define COP0_REG_LAST 111 | |
1785 | #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) | |
1786 | ||
1787 | #define COP2_REG_FIRST 112 | |
1788 | #define COP2_REG_LAST 143 | |
1789 | #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) | |
1790 | ||
1791 | #define COP3_REG_FIRST 144 | |
1792 | #define COP3_REG_LAST 175 | |
1793 | #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) | |
1794 | /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */ | |
1795 | #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1) | |
1796 | ||
e75b25e7 MM |
1797 | #define AT_REGNUM (GP_REG_FIRST + 1) |
1798 | #define HI_REGNUM (MD_REG_FIRST + 0) | |
1799 | #define LO_REGNUM (MD_REG_FIRST + 1) | |
225b8835 | 1800 | #define HILO_REGNUM (MD_REG_FIRST + 2) |
b8eb88d0 ILT |
1801 | |
1802 | /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If | |
1803 | mips_isa >= 4, it should not be used, and an arbitrary ST_REG | |
1804 | should be used instead. */ | |
e75b25e7 MM |
1805 | #define FPSW_REGNUM ST_REG_FIRST |
1806 | ||
75131237 RK |
1807 | #define GP_REG_P(REGNO) \ |
1808 | ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
2bcb2ab3 GK |
1809 | #define M16_REG_P(REGNO) \ |
1810 | (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) | |
75131237 RK |
1811 | #define FP_REG_P(REGNO) \ |
1812 | ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
1813 | #define MD_REG_P(REGNO) \ | |
1814 | ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) | |
1815 | #define ST_REG_P(REGNO) \ | |
1816 | ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) | |
d604bca3 MH |
1817 | #define COP0_REG_P(REGNO) \ |
1818 | ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) | |
1819 | #define COP2_REG_P(REGNO) \ | |
1820 | ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) | |
1821 | #define COP3_REG_P(REGNO) \ | |
1822 | ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) | |
1823 | #define ALL_COP_REG_P(REGNO) \ | |
1824 | ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) | |
1825 | ||
1826 | /* Return coprocessor number from register number. */ | |
1827 | ||
1828 | #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ | |
1829 | (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ | |
1830 | : COP3_REG_P (REGNO) ? '3' : '?') | |
e75b25e7 | 1831 | |
e75b25e7 MM |
1832 | /* Return number of consecutive hard regs needed starting at reg REGNO |
1833 | to hold something of mode MODE. | |
1834 | This is ordinarily the length in words of a value of mode MODE | |
1835 | but can be less for certain modes in special long registers. | |
1836 | ||
1837 | On the MIPS, all general registers are one word long. Except on | |
1838 | the R4000 with the FR bit set, the floating point uses register | |
956d6950 | 1839 | pairs, with the second register not being allocable. */ |
e75b25e7 | 1840 | |
0e5a4ad8 | 1841 | #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE) |
e75b25e7 MM |
1842 | |
1843 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
876c09d3 JW |
1844 | MODE. In 32 bit mode, require that DImode and DFmode be in even |
1845 | registers. For DImode, this makes some of the insns easier to | |
1846 | write, since you don't have to worry about a DImode value in | |
1847 | registers 3 & 4, producing a result in 4 & 5. | |
e75b25e7 MM |
1848 | |
1849 | To make the code simpler HARD_REGNO_MODE_OK now just references an | |
1850 | array built in override_options. Because machmodes.h is not yet | |
1851 | included before this file is processed, the MODE bound can't be | |
1852 | expressed here. */ | |
1853 | ||
1854 | extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; | |
1855 | ||
1856 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
1857 | mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ] | |
1858 | ||
1859 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1860 | when one has mode MODE1 and one has mode MODE2. | |
1861 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1862 | for any hard reg, then this must be 0 for correct output. */ | |
1863 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
1864 | ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ | |
1865 | GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ | |
1866 | == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ | |
1867 | GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) | |
1868 | ||
1869 | /* MIPS pc is not overloaded on a register. */ | |
1870 | /* #define PC_REGNUM xx */ | |
1871 | ||
1872 | /* Register to use for pushing function arguments. */ | |
0fb5ac6f | 1873 | #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) |
e75b25e7 | 1874 | |
97116296 ILT |
1875 | /* Offset from the stack pointer to the first available location. Use |
1876 | the default value zero. */ | |
1877 | /* #define STACK_POINTER_OFFSET 0 */ | |
e75b25e7 | 1878 | |
2bcb2ab3 GK |
1879 | /* Base register for access to local variables of the function. We |
1880 | pretend that the frame pointer is $1, and then eliminate it to | |
1881 | HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is | |
1882 | a fixed register, and will not be used for anything else. */ | |
1883 | #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1) | |
1884 | ||
0ff83799 MM |
1885 | /* Temporary scratch register for use by the assembler. */ |
1886 | #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1) | |
1887 | ||
2bcb2ab3 GK |
1888 | /* $30 is not available on the mips16, so we use $17 as the frame |
1889 | pointer. */ | |
1890 | #define HARD_FRAME_POINTER_REGNUM \ | |
1891 | (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) | |
e75b25e7 MM |
1892 | |
1893 | /* Value should be nonzero if functions must have frame pointers. | |
1894 | Zero means the frame pointer need not be set up (and parms | |
1895 | may be accessed via the stack pointer) in functions that seem suitable. | |
1896 | This is computed in `reload', in reload1.c. */ | |
1897 | #define FRAME_POINTER_REQUIRED (current_function_calls_alloca) | |
1898 | ||
1899 | /* Base register for access to arguments of the function. */ | |
ab78d4a8 | 1900 | #define ARG_POINTER_REGNUM GP_REG_FIRST |
e75b25e7 | 1901 | |
39dffea3 JW |
1902 | /* Fake register that holds the address on the stack of the |
1903 | current function's return address. */ | |
1904 | #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM | |
1905 | ||
e75b25e7 | 1906 | /* Register in which static-chain is passed to a function. */ |
0fb5ac6f | 1907 | #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2) |
e75b25e7 | 1908 | |
1154b096 MM |
1909 | /* If the structure value address is passed in a register, then |
1910 | `STRUCT_VALUE_REGNUM' should be the number of that register. */ | |
1911 | /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */ | |
1912 | ||
1913 | /* If the structure value address is not passed in a register, define | |
1914 | `STRUCT_VALUE' as an expression returning an RTX for the place | |
1915 | where the address is passed. If it returns 0, the address is | |
1916 | passed as an "invisible" first argument. */ | |
f58cfbfb | 1917 | #define STRUCT_VALUE 0 |
e75b25e7 MM |
1918 | |
1919 | /* Mips registers used in prologue/epilogue code when the stack frame | |
1920 | is larger than 32K bytes. These registers must come from the | |
1921 | scratch register set, and not used for passing and returning | |
1922 | arguments and any other information used in the calling sequence | |
516a2dfd JW |
1923 | (such as pic). Must start at 12, since t0/t3 are parameter passing |
1924 | registers in the 64 bit ABI. */ | |
7bea35e7 | 1925 | |
516a2dfd JW |
1926 | #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12) |
1927 | #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13) | |
e75b25e7 MM |
1928 | |
1929 | /* Define this macro if it is as good or better to call a constant | |
1930 | function address than to call an address kept in a register. */ | |
1931 | #define NO_FUNCTION_CSE 1 | |
1932 | ||
1933 | /* Define this macro if it is as good or better for a function to | |
1934 | call itself with an explicit address than to call an address | |
1935 | kept in a register. */ | |
1936 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
1937 | ||
1938 | /* The register number of the register used to address a table of | |
1939 | static data addresses in memory. In some cases this register is | |
7dac2f89 | 1940 | defined by a processor's "application binary interface" (ABI). |
e75b25e7 MM |
1941 | When this macro is defined, RTL is generated for this register |
1942 | once, as with the stack pointer and frame pointer registers. If | |
1943 | this macro is not defined, it is up to the machine-dependent | |
1944 | files to allocate such a register (if necessary). */ | |
0fb5ac6f | 1945 | #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28) |
e75b25e7 | 1946 | |
24e214e3 | 1947 | #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25) |
e75b25e7 MM |
1948 | \f |
1949 | /* Define the classes of registers for register constraints in the | |
1950 | machine description. Also define ranges of constants. | |
1951 | ||
1952 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1953 | If there is more than one class, another class must be named NO_REGS | |
1954 | and contain no registers. | |
1955 | ||
1956 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1957 | another name such as ALL_REGS). This is the class of registers | |
1958 | that is allowed by "g" or "r" in a register constraint. | |
1959 | Also, registers outside this class are allocated only when | |
1960 | instructions express preferences for them. | |
1961 | ||
1962 | The classes must be numbered in nondecreasing order; that is, | |
1963 | a larger-numbered class must never be contained completely | |
1964 | in a smaller-numbered class. | |
1965 | ||
1966 | For any two classes, it is very desirable that there be another | |
1967 | class that represents their union. */ | |
1968 | ||
1969 | enum reg_class | |
1970 | { | |
1971 | NO_REGS, /* no registers in set */ | |
2bcb2ab3 GK |
1972 | M16_NA_REGS, /* mips16 regs not used to pass args */ |
1973 | M16_REGS, /* mips16 directly accessible registers */ | |
1974 | T_REG, /* mips16 T register ($24) */ | |
1975 | M16_T_REGS, /* mips16 registers plus T register */ | |
e75b25e7 MM |
1976 | GR_REGS, /* integer registers */ |
1977 | FP_REGS, /* floating point registers */ | |
1978 | HI_REG, /* hi register */ | |
1979 | LO_REG, /* lo register */ | |
225b8835 | 1980 | HILO_REG, /* hilo register pair for 64 bit mode mult */ |
e75b25e7 | 1981 | MD_REGS, /* multiply/divide registers (hi/lo) */ |
d604bca3 MH |
1982 | COP0_REGS, /* generic coprocessor classes */ |
1983 | COP2_REGS, | |
1984 | COP3_REGS, | |
e4f5c5d6 KR |
1985 | HI_AND_GR_REGS, /* union classes */ |
1986 | LO_AND_GR_REGS, | |
1987 | HILO_AND_GR_REGS, | |
ab093b81 | 1988 | HI_AND_FP_REGS, |
d604bca3 MH |
1989 | COP0_AND_GR_REGS, |
1990 | COP2_AND_GR_REGS, | |
1991 | COP3_AND_GR_REGS, | |
1992 | ALL_COP_REGS, | |
1993 | ALL_COP_AND_GR_REGS, | |
e75b25e7 MM |
1994 | ST_REGS, /* status registers (fp status) */ |
1995 | ALL_REGS, /* all registers */ | |
1996 | LIM_REG_CLASSES /* max value + 1 */ | |
1997 | }; | |
1998 | ||
1999 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
2000 | ||
2001 | #define GENERAL_REGS GR_REGS | |
2002 | ||
2003 | /* An initializer containing the names of the register classes as C | |
2004 | string constants. These names are used in writing some of the | |
2005 | debugging dumps. */ | |
2006 | ||
2007 | #define REG_CLASS_NAMES \ | |
2008 | { \ | |
2009 | "NO_REGS", \ | |
2bcb2ab3 GK |
2010 | "M16_NA_REGS", \ |
2011 | "M16_REGS", \ | |
2012 | "T_REG", \ | |
2013 | "M16_T_REGS", \ | |
e75b25e7 MM |
2014 | "GR_REGS", \ |
2015 | "FP_REGS", \ | |
2016 | "HI_REG", \ | |
2017 | "LO_REG", \ | |
225b8835 | 2018 | "HILO_REG", \ |
e75b25e7 | 2019 | "MD_REGS", \ |
d604bca3 MH |
2020 | /* coprocessor registers */ \ |
2021 | "COP0_REGS", \ | |
2022 | "COP2_REGS", \ | |
2023 | "COP3_REGS", \ | |
e4f5c5d6 KR |
2024 | "HI_AND_GR_REGS", \ |
2025 | "LO_AND_GR_REGS", \ | |
2026 | "HILO_AND_GR_REGS", \ | |
ab093b81 | 2027 | "HI_AND_FP_REGS", \ |
d604bca3 MH |
2028 | "COP0_AND_GR_REGS", \ |
2029 | "COP2_AND_GR_REGS", \ | |
2030 | "COP3_AND_GR_REGS", \ | |
2031 | "ALL_COP_REGS", \ | |
2032 | "ALL_COP_AND_GR_REGS", \ | |
e75b25e7 MM |
2033 | "ST_REGS", \ |
2034 | "ALL_REGS" \ | |
2035 | } | |
2036 | ||
2037 | /* An initializer containing the contents of the register classes, | |
2038 | as integers which are bit masks. The Nth integer specifies the | |
2039 | contents of class N. The way the integer MASK is interpreted is | |
2040 | that register R is in the class if `MASK & (1 << R)' is 1. | |
2041 | ||
2042 | When the machine has more than 32 registers, an integer does not | |
2043 | suffice. Then the integers are replaced by sub-initializers, | |
2044 | braced groupings containing several integers. Each | |
2045 | sub-initializer must be suitable as an initializer for the type | |
2046 | `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ | |
2047 | ||
2048 | #define REG_CLASS_CONTENTS \ | |
2049 | { \ | |
d604bca3 MH |
2050 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \ |
2051 | { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\ | |
2052 | { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \ | |
2053 | { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \ | |
2054 | { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \ | |
2055 | { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \ | |
2056 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \ | |
2057 | { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \ | |
2058 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \ | |
2059 | { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \ | |
2060 | { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \ | |
2061 | { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \ | |
2062 | { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \ | |
2063 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \ | |
2064 | { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \ | |
2065 | { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \ | |
2066 | { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \ | |
2067 | { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \ | |
2068 | { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \ | |
2069 | { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \ | |
2070 | { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \ | |
2071 | { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ | |
2072 | { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \ | |
2073 | { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \ | |
2074 | { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \ | |
e75b25e7 MM |
2075 | } |
2076 | ||
2077 | ||
2078 | /* A C expression whose value is a register class containing hard | |
2079 | register REGNO. In general there is more that one such class; | |
2080 | choose a class which is "minimal", meaning that no smaller class | |
2081 | also contains the register. */ | |
2082 | ||
8b60264b | 2083 | extern const enum reg_class mips_regno_to_class[]; |
e75b25e7 MM |
2084 | |
2085 | #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] | |
2086 | ||
2087 | /* A macro whose definition is the name of the class to which a | |
2088 | valid base register must belong. A base register is one used in | |
2089 | an address which is the register value plus a displacement. */ | |
2090 | ||
2bcb2ab3 | 2091 | #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS) |
e75b25e7 MM |
2092 | |
2093 | /* A macro whose definition is the name of the class to which a | |
2094 | valid index register must belong. An index register is one used | |
2095 | in an address where its value is either multiplied by a scale | |
2096 | factor or added to another register (as well as added to a | |
2097 | displacement). */ | |
2098 | ||
876c09d3 | 2099 | #define INDEX_REG_CLASS NO_REGS |
e75b25e7 | 2100 | |
2bcb2ab3 GK |
2101 | /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows |
2102 | registers explicitly used in the rtl to be used as spill registers | |
2103 | but prevents the compiler from extending the lifetime of these | |
987ba558 | 2104 | registers. */ |
2bcb2ab3 GK |
2105 | |
2106 | #define SMALL_REGISTER_CLASSES (TARGET_MIPS16) | |
2107 | ||
2108 | /* This macro is used later on in the file. */ | |
2109 | #define GR_REG_CLASS_P(CLASS) \ | |
2110 | ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \ | |
2111 | || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS) | |
2112 | ||
d604bca3 MH |
2113 | /* This macro is also used later on in the file. */ |
2114 | #define COP_REG_CLASS_P(CLASS) \ | |
2115 | ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS) | |
2116 | ||
2bcb2ab3 GK |
2117 | /* REG_ALLOC_ORDER is to order in which to allocate registers. This |
2118 | is the default value (allocate the registers in numeric order). We | |
2119 | define it just so that we can override it for the mips16 target in | |
2120 | ORDER_REGS_FOR_LOCAL_ALLOC. */ | |
2121 | ||
2122 | #define REG_ALLOC_ORDER \ | |
2123 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ | |
2124 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ | |
2125 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
2126 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ | |
d604bca3 MH |
2127 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ |
2128 | 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ | |
2129 | 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ | |
2130 | 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ | |
2131 | 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ | |
2132 | 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ | |
2133 | 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \ | |
2bcb2ab3 GK |
2134 | } |
2135 | ||
2136 | /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order | |
2137 | to be rearranged based on a particular function. On the mips16, we | |
2138 | want to allocate $24 (T_REG) before other registers for | |
2139 | instructions for which it is possible. */ | |
2140 | ||
2141 | #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () | |
e75b25e7 MM |
2142 | |
2143 | /* REGISTER AND CONSTANT CLASSES */ | |
2144 | ||
2145 | /* Get reg_class from a letter such as appears in the machine | |
2146 | description. | |
2147 | ||
2148 | DEFINED REGISTER CLASSES: | |
2149 | ||
2150 | 'd' General (aka integer) registers | |
2bcb2ab3 GK |
2151 | Normally this is GR_REGS, but in mips16 mode this is M16_REGS |
2152 | 'y' General registers (in both mips16 and non mips16 mode) | |
2153 | 'e' mips16 non argument registers (M16_NA_REGS) | |
2154 | 't' mips16 temporary register ($24) | |
e75b25e7 MM |
2155 | 'f' Floating point registers |
2156 | 'h' Hi register | |
2157 | 'l' Lo register | |
34b650b3 | 2158 | 'x' Multiply/divide registers |
225b8835 ILT |
2159 | 'a' HILO_REG |
2160 | 'z' FP Status register | |
d604bca3 MH |
2161 | 'B' Cop0 register |
2162 | 'C' Cop2 register | |
2163 | 'D' Cop3 register | |
225b8835 | 2164 | 'b' All registers */ |
e75b25e7 | 2165 | |
f540a7d3 | 2166 | extern enum reg_class mips_char_to_class[256]; |
e75b25e7 | 2167 | |
8f54374e | 2168 | #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)] |
e75b25e7 MM |
2169 | |
2170 | /* The letters I, J, K, L, M, N, O, and P in a register constraint | |
2171 | string can be used to stand for particular ranges of immediate | |
2172 | operands. This macro defines what the ranges are. C is the | |
2173 | letter, and VALUE is a constant value. Return 1 if VALUE is | |
2174 | in the range specified by C. */ | |
2175 | ||
2176 | /* For MIPS: | |
2177 | ||
2178 | `I' is used for the range of constants an arithmetic insn can | |
2179 | actually contain (16 bits signed integers). | |
2180 | ||
2181 | `J' is used for the range which is just zero (ie, $r0). | |
2182 | ||
2183 | `K' is used for the range of constants a logical insn can actually | |
2184 | contain (16 bit zero-extended integers). | |
2185 | ||
2186 | `L' is used for the range of constants that be loaded with lui | |
2187 | (ie, the bottom 16 bits are zero). | |
2188 | ||
2189 | `M' is used for the range of constants that take two words to load | |
2190 | (ie, not matched by `I', `K', and `L'). | |
2191 | ||
2bcb2ab3 | 2192 | `N' is used for negative 16 bit constants other than -65536. |
e75b25e7 | 2193 | |
2bcb2ab3 | 2194 | `O' is a 15 bit signed integer. |
e75b25e7 MM |
2195 | |
2196 | `P' is used for positive 16 bit constants. */ | |
2197 | ||
516a2dfd JW |
2198 | #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) |
2199 | #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000) | |
e75b25e7 MM |
2200 | |
2201 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
516a2dfd | 2202 | ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \ |
e75b25e7 | 2203 | : (C) == 'J' ? ((VALUE) == 0) \ |
516a2dfd | 2204 | : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \ |
876c09d3 JW |
2205 | : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \ |
2206 | && (((VALUE) & ~2147483647) == 0 \ | |
2207 | || ((VALUE) & ~2147483647) == ~2147483647)) \ | |
99cbc4b0 MM |
2208 | : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \ |
2209 | && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \ | |
876c09d3 JW |
2210 | && (((VALUE) & 0x0000ffff) != 0 \ |
2211 | || (((VALUE) & ~2147483647) != 0 \ | |
2212 | && ((VALUE) & ~2147483647) != ~2147483647))) \ | |
2bcb2ab3 GK |
2213 | : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \ |
2214 | : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \ | |
99cbc4b0 | 2215 | : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \ |
e75b25e7 MM |
2216 | : 0) |
2217 | ||
2218 | /* Similar, but for floating constants, and defining letters G and H. | |
2219 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
2220 | ||
2221 | /* For Mips | |
2222 | ||
2223 | 'G' : Floating point 0 */ | |
2224 | ||
2225 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
2226 | ((C) == 'G' \ | |
876c09d3 | 2227 | && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) |
e75b25e7 MM |
2228 | |
2229 | /* Letters in the range `Q' through `U' may be defined in a | |
7dac2f89 | 2230 | machine-dependent fashion to stand for arbitrary operand types. |
e75b25e7 MM |
2231 | The machine description macro `EXTRA_CONSTRAINT' is passed the |
2232 | operand as its first argument and the constraint letter as its | |
2233 | second operand. | |
2234 | ||
2bcb2ab3 | 2235 | `Q' is for mips16 GP relative constants |
31c714e3 | 2236 | `R' is for memory references which take 1 word for the instruction. |
2bcb2ab3 GK |
2237 | `S' is for references to extern items which are PIC for OSF/rose. |
2238 | `T' is for memory addresses that can be used to load two words. */ | |
e75b25e7 MM |
2239 | |
2240 | #define EXTRA_CONSTRAINT(OP,CODE) \ | |
2bcb2ab3 GK |
2241 | (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \ |
2242 | : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \ | |
2243 | && mips16_gp_offset_p (OP)) \ | |
2244 | : (GET_CODE (OP) != MEM) ? FALSE \ | |
e75b25e7 | 2245 | : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \ |
31c714e3 MM |
2246 | : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \ |
2247 | && HALF_PIC_ADDRESS_P (OP)) \ | |
e75b25e7 MM |
2248 | : FALSE) |
2249 | ||
2250 | /* Given an rtx X being reloaded into a reg required to be | |
2251 | in class CLASS, return the class of reg to actually use. | |
2252 | In general this is just CLASS; but on some machines | |
2253 | in some cases it is preferable to use a more restrictive class. */ | |
2254 | ||
2255 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
876c09d3 | 2256 | ((CLASS) != ALL_REGS \ |
2bcb2ab3 GK |
2257 | ? (! TARGET_MIPS16 \ |
2258 | ? (CLASS) \ | |
2259 | : ((CLASS) != GR_REGS \ | |
2260 | ? (CLASS) \ | |
2261 | : M16_REGS)) \ | |
876c09d3 JW |
2262 | : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
2263 | || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \ | |
2bcb2ab3 GK |
2264 | ? (TARGET_SOFT_FLOAT \ |
2265 | ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \ | |
2266 | : FP_REGS) \ | |
876c09d3 JW |
2267 | : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ |
2268 | || GET_MODE (X) == VOIDmode) \ | |
2bcb2ab3 | 2269 | ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \ |
876c09d3 | 2270 | : (CLASS)))) |
e75b25e7 | 2271 | |
0fb5ac6f MM |
2272 | /* Certain machines have the property that some registers cannot be |
2273 | copied to some other registers without using memory. Define this | |
2274 | macro on those machines to be a C expression that is non-zero if | |
2275 | objects of mode MODE in registers of CLASS1 can only be copied to | |
2276 | registers of class CLASS2 by storing a register of CLASS1 into | |
2277 | memory and loading that memory location into a register of CLASS2. | |
2278 | ||
2279 | Do not define this macro if its value would always be zero. */ | |
7b2e1077 | 2280 | #if 0 |
0fb5ac6f | 2281 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
2370b831 JW |
2282 | ((!TARGET_DEBUG_H_MODE \ |
2283 | && GET_MODE_CLASS (MODE) == MODE_INT \ | |
2bcb2ab3 GK |
2284 | && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \ |
2285 | || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \ | |
2370b831 | 2286 | || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \ |
2bcb2ab3 GK |
2287 | && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \ |
2288 | || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS)))) | |
7b2e1077 | 2289 | #endif |
46299de9 | 2290 | /* The HI and LO registers can only be reloaded via the general |
b8eb88d0 ILT |
2291 | registers. Condition code registers can only be loaded to the |
2292 | general registers, and from the floating point registers. */ | |
46299de9 | 2293 | |
225b8835 ILT |
2294 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
2295 | mips_secondary_reload_class (CLASS, MODE, X, 1) | |
2296 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
2297 | mips_secondary_reload_class (CLASS, MODE, X, 0) | |
46299de9 | 2298 | |
e75b25e7 MM |
2299 | /* Return the maximum number of consecutive registers |
2300 | needed to represent mode MODE in a register of class CLASS. */ | |
2301 | ||
d604bca3 | 2302 | #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) |
e75b25e7 | 2303 | |
87d9d860 | 2304 | /* If defined, gives a class of registers that cannot be used as the |
ab093b81 | 2305 | operand of a SUBREG that changes the mode of the object illegally. |
ab093b81 RH |
2306 | When FP regs are larger than integer regs... Er, anyone remember what |
2307 | goes wrong? | |
2308 | ||
2309 | In little-endian mode, the hi-lo registers are numbered backwards, | |
2310 | so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low | |
2311 | word as intended. */ | |
2312 | ||
2313 | #define CLASS_CANNOT_CHANGE_MODE \ | |
2314 | (TARGET_BIG_ENDIAN \ | |
2315 | ? (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS) \ | |
2316 | : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI_REG)) | |
02188693 RH |
2317 | |
2318 | /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ | |
2319 | ||
2320 | #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ | |
2321 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) | |
e75b25e7 MM |
2322 | \f |
2323 | /* Stack layout; function entry, exit and calling. */ | |
2324 | ||
2325 | /* Define this if pushing a word on the stack | |
2326 | makes the stack pointer a smaller address. */ | |
2327 | #define STACK_GROWS_DOWNWARD | |
2328 | ||
2329 | /* Define this if the nominal address of the stack frame | |
2330 | is at the high-address end of the local variables; | |
2331 | that is, each additional local variable allocated | |
2332 | goes at a more negative offset in the frame. */ | |
ab78d4a8 | 2333 | /* #define FRAME_GROWS_DOWNWARD */ |
e75b25e7 MM |
2334 | |
2335 | /* Offset within stack frame to start allocating local variables at. | |
2336 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
2337 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
2338 | of the first local allocated. */ | |
24e214e3 JW |
2339 | #define STARTING_FRAME_OFFSET \ |
2340 | (current_function_outgoing_args_size \ | |
2341 | + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)) | |
ab78d4a8 MM |
2342 | |
2343 | /* Offset from the stack pointer register to an item dynamically | |
2344 | allocated on the stack, e.g., by `alloca'. | |
2345 | ||
2346 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
2347 | length of the outgoing arguments. The default is correct for most | |
2348 | machines. See `function.c' for details. | |
2349 | ||
51bdc4d3 MM |
2350 | The MIPS ABI states that functions which dynamically allocate the |
2351 | stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like | |
2352 | we are trying to create a second frame pointer to the function, so | |
2353 | allocate some stack space to make it happy. | |
ab78d4a8 | 2354 | |
51bdc4d3 MM |
2355 | However, the linker currently complains about linking any code that |
2356 | dynamically allocates stack space, and there seems to be a bug in | |
2357 | STACK_DYNAMIC_OFFSET, so don't define this right now. */ | |
2358 | ||
2359 | #if 0 | |
ab78d4a8 MM |
2360 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
2361 | ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \ | |
2362 | ? 4*UNITS_PER_WORD \ | |
2363 | : current_function_outgoing_args_size) | |
51bdc4d3 | 2364 | #endif |
e75b25e7 | 2365 | |
39dffea3 JW |
2366 | /* The return address for the current frame is in r31 is this is a leaf |
2367 | function. Otherwise, it is on the stack. It is at a variable offset | |
2368 | from sp/fp/ap, so we define a fake hard register rap which is a | |
2369 | poiner to the return address on the stack. This always gets eliminated | |
2370 | during reload to be either the frame pointer or the stack pointer plus | |
2371 | an offset. */ | |
2372 | ||
2373 | /* ??? This definition fails for leaf functions. There is currently no | |
2374 | general solution for this problem. */ | |
2375 | ||
2376 | /* ??? There appears to be no way to get the return address of any previous | |
2377 | frame except by disassembling instructions in the prologue/epilogue. | |
2378 | So currently we support only the current frame. */ | |
2379 | ||
07e2e444 AO |
2380 | #define RETURN_ADDR_RTX(count, frame) \ |
2381 | (((count) == 0) \ | |
2382 | ? (leaf_function_p () \ | |
2383 | ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \ | |
2384 | : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \ | |
2385 | RETURN_ADDRESS_POINTER_REGNUM))) \ | |
24ba333f | 2386 | : (rtx) 0) |
39dffea3 | 2387 | |
7f48c9e1 AO |
2388 | /* Since the mips16 ISA mode is encoded in the least-significant bit |
2389 | of the address, mask it off return addresses for purposes of | |
2390 | finding exception handling regions. */ | |
2391 | ||
2392 | #define MASK_RETURN_ADDR GEN_INT (-2) | |
2393 | ||
2394 | /* Similarly, don't use the least-significant bit to tell pointers to | |
2395 | code from vtable index. */ | |
2396 | ||
2397 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
2398 | ||
e75b25e7 MM |
2399 | /* Structure to be filled in by compute_frame_size with register |
2400 | save masks, and offsets for the current function. */ | |
2401 | ||
2402 | struct mips_frame_info | |
2403 | { | |
7bea35e7 MM |
2404 | long total_size; /* # bytes that the entire frame takes up */ |
2405 | long var_size; /* # bytes that variables take up */ | |
2406 | long args_size; /* # bytes that outgoing arguments take up */ | |
2407 | long extra_size; /* # bytes of extra gunk */ | |
2408 | int gp_reg_size; /* # bytes needed to store gp regs */ | |
2409 | int fp_reg_size; /* # bytes needed to store fp regs */ | |
2410 | long mask; /* mask of saved gp registers */ | |
2411 | long fmask; /* mask of saved fp registers */ | |
2412 | long gp_save_offset; /* offset from vfp to store gp registers */ | |
2413 | long fp_save_offset; /* offset from vfp to store fp registers */ | |
2414 | long gp_sp_offset; /* offset from new sp to store gp registers */ | |
2415 | long fp_sp_offset; /* offset from new sp to store fp registers */ | |
2416 | int initialized; /* != 0 if frame size already calculated */ | |
2417 | int num_gp; /* number of gp registers saved */ | |
2418 | int num_fp; /* number of fp registers saved */ | |
2bcb2ab3 | 2419 | long insns_len; /* length of insns; mips16 only */ |
e75b25e7 MM |
2420 | }; |
2421 | ||
2422 | extern struct mips_frame_info current_frame_info; | |
2423 | ||
ab78d4a8 MM |
2424 | /* If defined, this macro specifies a table of register pairs used to |
2425 | eliminate unneeded registers that point into the stack frame. If | |
2426 | it is not defined, the only elimination attempted by the compiler | |
2427 | is to replace references to the frame pointer with references to | |
2428 | the stack pointer. | |
2429 | ||
2430 | The definition of this macro is a list of structure | |
2431 | initializations, each of which specifies an original and | |
2432 | replacement register. | |
2433 | ||
2434 | On some machines, the position of the argument pointer is not | |
2435 | known until the compilation is completed. In such a case, a | |
7dac2f89 | 2436 | separate hard register must be used for the argument pointer. |
ab78d4a8 MM |
2437 | This register can be eliminated by replacing it with either the |
2438 | frame pointer or the argument pointer, depending on whether or not | |
2439 | the frame pointer has been eliminated. | |
2440 | ||
2441 | In this case, you might specify: | |
2442 | #define ELIMINABLE_REGS \ | |
2443 | {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
2444 | {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
2445 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} | |
2446 | ||
2447 | Note that the elimination of the argument pointer with the stack | |
2bcb2ab3 GK |
2448 | pointer is specified first since that is the preferred elimination. |
2449 | ||
2450 | The eliminations to $17 are only used on the mips16. See the | |
2451 | definition of HARD_FRAME_POINTER_REGNUM. */ | |
ab78d4a8 MM |
2452 | |
2453 | #define ELIMINABLE_REGS \ | |
2454 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
2bcb2ab3 GK |
2455 | { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ |
2456 | { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ | |
39dffea3 | 2457 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
2bcb2ab3 GK |
2458 | { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \ |
2459 | { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \ | |
2460 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
2461 | { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ | |
2462 | { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} | |
ab78d4a8 | 2463 | |
ab78d4a8 MM |
2464 | /* A C expression that returns non-zero if the compiler is allowed to |
2465 | try to replace register number FROM-REG with register number | |
2466 | TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is | |
2467 | defined, and will usually be the constant 1, since most of the | |
2468 | cases preventing register elimination are things that the compiler | |
2bcb2ab3 GK |
2469 | already knows about. |
2470 | ||
365ca18b GK |
2471 | When not in mips16 and mips64, we can always eliminate to the |
2472 | frame pointer. We can eliminate to the stack pointer unless | |
2473 | a frame pointer is needed. In mips16 mode, we need a frame | |
2474 | pointer for a large frame; otherwise, reload may be unable | |
2475 | to compute the address of a local variable, since there is | |
2476 | no way to add a large constant to the stack pointer | |
2477 | without using a temporary register. | |
2478 | ||
2479 | In mips16, for some instructions (eg lwu), we can't eliminate the | |
2480 | frame pointer for the stack pointer. These instructions are | |
2481 | only generated in TARGET_64BIT mode. | |
2482 | */ | |
ab78d4a8 MM |
2483 | |
2484 | #define CAN_ELIMINATE(FROM, TO) \ | |
cfb773f9 | 2485 | (((FROM) == RETURN_ADDRESS_POINTER_REGNUM \ |
07e2e444 AO |
2486 | && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \ |
2487 | || (TO) == HARD_FRAME_POINTER_REGNUM)) \ | |
cfb773f9 AO |
2488 | || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \ |
2489 | && ((TO) == HARD_FRAME_POINTER_REGNUM \ | |
2490 | || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \ | |
2491 | && ! (TARGET_MIPS16 && TARGET_64BIT) \ | |
2492 | && (! TARGET_MIPS16 \ | |
2493 | || compute_frame_size (get_frame_size ()) < 32768))))) | |
ab78d4a8 MM |
2494 | |
2495 | /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It | |
2496 | specifies the initial difference between the specified pair of | |
2497 | registers. This macro must be defined if `ELIMINABLE_REGS' is | |
2498 | defined. */ | |
2499 | ||
2500 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
2501 | { compute_frame_size (get_frame_size ()); \ | |
2bcb2ab3 GK |
2502 | if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \ |
2503 | && (TO) == HARD_FRAME_POINTER_REGNUM) \ | |
2504 | (OFFSET) = - current_function_outgoing_args_size; \ | |
2505 | else if ((FROM) == FRAME_POINTER_REGNUM) \ | |
ab78d4a8 | 2506 | (OFFSET) = 0; \ |
2bcb2ab3 GK |
2507 | else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \ |
2508 | && (TO) == HARD_FRAME_POINTER_REGNUM) \ | |
2509 | (OFFSET) = (current_frame_info.total_size \ | |
2510 | - current_function_outgoing_args_size \ | |
a53f72db GRK |
2511 | - ((mips_abi != ABI_32 \ |
2512 | && mips_abi != ABI_O64 \ | |
2513 | && mips_abi != ABI_EABI) \ | |
2bcb2ab3 GK |
2514 | ? current_function_pretend_args_size \ |
2515 | : 0)); \ | |
2516 | else if ((FROM) == ARG_POINTER_REGNUM) \ | |
a2ef6e41 | 2517 | (OFFSET) = (current_frame_info.total_size \ |
a53f72db GRK |
2518 | - ((mips_abi != ABI_32 \ |
2519 | && mips_abi != ABI_O64 \ | |
2520 | && mips_abi != ABI_EABI) \ | |
a2ef6e41 RK |
2521 | ? current_function_pretend_args_size \ |
2522 | : 0)); \ | |
c9b4de06 JW |
2523 | /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \ |
2524 | so we must add 4 bytes to the offset to get the right value. */ \ | |
2bcb2ab3 | 2525 | else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \ |
973838fd | 2526 | { \ |
07e2e444 AO |
2527 | (OFFSET) = current_frame_info.gp_sp_offset \ |
2528 | + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \ | |
2529 | * (BYTES_BIG_ENDIAN != 0)); \ | |
2530 | if (TARGET_MIPS16 && (TO) != STACK_POINTER_REGNUM) \ | |
2531 | (OFFSET) -= current_function_outgoing_args_size; \ | |
973838fd | 2532 | } \ |
a6ffcb2a KG |
2533 | else \ |
2534 | abort(); \ | |
ab78d4a8 MM |
2535 | } |
2536 | ||
e75b25e7 MM |
2537 | /* If we generate an insn to push BYTES bytes, |
2538 | this says how many the stack pointer really advances by. | |
8aeea6e6 | 2539 | On the VAX, sp@- in a byte insn really pushes a word. */ |
e75b25e7 MM |
2540 | |
2541 | /* #define PUSH_ROUNDING(BYTES) 0 */ | |
2542 | ||
2543 | /* If defined, the maximum amount of space required for outgoing | |
2544 | arguments will be computed and placed into the variable | |
2545 | `current_function_outgoing_args_size'. No space will be pushed | |
2546 | onto the stack for each call; instead, the function prologue | |
2547 | should increase the stack frame size by this amount. | |
2548 | ||
2549 | It is not proper to define both `PUSH_ROUNDING' and | |
2550 | `ACCUMULATE_OUTGOING_ARGS'. */ | |
f73ad30e | 2551 | #define ACCUMULATE_OUTGOING_ARGS 1 |
e75b25e7 | 2552 | |
6cb6c3b3 MM |
2553 | /* Offset from the argument pointer register to the first argument's |
2554 | address. On some machines it may depend on the data type of the | |
2555 | function. | |
e75b25e7 | 2556 | |
6cb6c3b3 | 2557 | If `ARGS_GROW_DOWNWARD', this is the offset to the location above |
39282292 MM |
2558 | the first argument's address. |
2559 | ||
2560 | On the MIPS, we must skip the first argument position if we are | |
876c09d3 | 2561 | returning a structure or a union, to account for its address being |
305aa9e2 MM |
2562 | passed in $4. However, at the current time, this produces a compiler |
2563 | that can't bootstrap, so comment it out for now. */ | |
e75b25e7 | 2564 | |
305aa9e2 | 2565 | #if 0 |
6cb6c3b3 MM |
2566 | #define FIRST_PARM_OFFSET(FNDECL) \ |
2567 | (FNDECL != 0 \ | |
2568 | && TREE_TYPE (FNDECL) != 0 \ | |
2569 | && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \ | |
2570 | && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \ | |
39282292 MM |
2571 | || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \ |
2572 | ? UNITS_PER_WORD \ | |
2573 | : 0) | |
305aa9e2 MM |
2574 | #else |
2575 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
2576 | #endif | |
e75b25e7 MM |
2577 | |
2578 | /* When a parameter is passed in a register, stack space is still | |
2579 | allocated for it. For the MIPS, stack space must be allocated, cf | |
2580 | Asm Lang Prog Guide page 7-8. | |
2581 | ||
2582 | BEWARE that some space is also allocated for non existing arguments | |
2583 | in register. In case an argument list is of form GF used registers | |
2584 | are a0 (a2,a3), but we should push over a1... */ | |
2585 | ||
516a2dfd JW |
2586 | #define REG_PARM_STACK_SPACE(FNDECL) \ |
2587 | ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL)) | |
e75b25e7 MM |
2588 | |
2589 | /* Define this if it is the responsibility of the caller to | |
7dac2f89 | 2590 | allocate the area reserved for arguments passed in registers. |
e75b25e7 | 2591 | If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect |
7dac2f89 | 2592 | of this macro is to determine whether the space is included in |
e75b25e7 MM |
2593 | `current_function_outgoing_args_size'. */ |
2594 | #define OUTGOING_REG_PARM_STACK_SPACE | |
2595 | ||
2596 | /* Align stack frames on 64 bits (Double Word ). */ | |
d1c17572 | 2597 | #ifndef STACK_BOUNDARY |
e75b25e7 | 2598 | #define STACK_BOUNDARY 64 |
d1c17572 | 2599 | #endif |
e75b25e7 | 2600 | |
876c09d3 | 2601 | /* Make sure 4 words are always allocated on the stack. */ |
e75b25e7 MM |
2602 | |
2603 | #ifndef STACK_ARGS_ADJUST | |
2604 | #define STACK_ARGS_ADJUST(SIZE) \ | |
2605 | { \ | |
876c09d3 JW |
2606 | if (SIZE.constant < 4 * UNITS_PER_WORD) \ |
2607 | SIZE.constant = 4 * UNITS_PER_WORD; \ | |
e75b25e7 MM |
2608 | } |
2609 | #endif | |
2610 | ||
2611 | \f | |
2612 | /* A C expression that should indicate the number of bytes of its | |
38e01259 | 2613 | own arguments that a function pops on returning, or 0 |
e75b25e7 MM |
2614 | if the function pops no arguments and the caller must therefore |
2615 | pop them all after the function returns. | |
2616 | ||
8b109b37 RK |
2617 | FUNDECL is the declaration node of the function (as a tree). |
2618 | ||
e75b25e7 MM |
2619 | FUNTYPE is a C variable whose value is a tree node that |
2620 | describes the function in question. Normally it is a node of | |
2621 | type `FUNCTION_TYPE' that describes the data type of the function. | |
2622 | From this it is possible to obtain the data types of the value | |
2623 | and arguments (if known). | |
2624 | ||
2625 | When a call to a library function is being considered, FUNTYPE | |
2626 | will contain an identifier node for the library function. Thus, | |
2627 | if you need to distinguish among various library functions, you | |
2628 | can do so by their names. Note that "library function" in this | |
2629 | context means a function used to perform arithmetic, whose name | |
2630 | is known specially in the compiler and was not mentioned in the | |
2631 | C code being compiled. | |
2632 | ||
2633 | STACK-SIZE is the number of bytes of arguments passed on the | |
2634 | stack. If a variable number of bytes is passed, it is zero, and | |
2635 | argument popping will always be the responsibility of the | |
2636 | calling function. */ | |
2637 | ||
8b109b37 | 2638 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
e75b25e7 MM |
2639 | |
2640 | ||
2641 | /* Symbolic macros for the registers used to return integer and floating | |
2642 | point values. */ | |
2643 | ||
2644 | #define GP_RETURN (GP_REG_FIRST + 2) | |
2645 | #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) | |
2646 | ||
2647 | /* Symbolic macros for the first/last argument registers. */ | |
2648 | ||
2649 | #define GP_ARG_FIRST (GP_REG_FIRST + 4) | |
2650 | #define GP_ARG_LAST (GP_REG_FIRST + 7) | |
2651 | #define FP_ARG_FIRST (FP_REG_FIRST + 12) | |
2652 | #define FP_ARG_LAST (FP_REG_FIRST + 15) | |
2653 | ||
2654 | #define MAX_ARGS_IN_REGISTERS 4 | |
2655 | ||
2656 | /* Define how to find the value returned by a library function | |
2bcb2ab3 GK |
2657 | assuming the value has mode MODE. Because we define |
2658 | PROMOTE_FUNCTION_RETURN, we must promote the mode just as | |
2659 | PROMOTE_MODE does. */ | |
e75b25e7 | 2660 | |
c6e6f5c1 RH |
2661 | #define LIBCALL_VALUE(MODE) \ |
2662 | mips_function_value (NULL_TREE, NULL, (MODE)) | |
e75b25e7 MM |
2663 | |
2664 | /* Define how to find the value returned by a function. | |
2665 | VALTYPE is the data type of the value (as a tree). | |
2666 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
2667 | otherwise, FUNC is 0. */ | |
2668 | ||
c6e6f5c1 RH |
2669 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
2670 | mips_function_value ((VALTYPE), (FUNC), VOIDmode) | |
e75b25e7 MM |
2671 | |
2672 | /* 1 if N is a possible register number for a function value. | |
2673 | On the MIPS, R2 R3 and F0 F2 are the only register thus used. | |
2674 | Currently, R2 and F0 are only implemented here (C has no complex type) */ | |
2675 | ||
2676 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) | |
2677 | ||
46af8e31 JW |
2678 | /* 1 if N is a possible register number for function argument passing. |
2679 | We have no FP argument registers when soft-float. When FP registers | |
2680 | are 32 bits, we can't directly reference the odd numbered ones. */ | |
d239cdc0 | 2681 | /* For o64 we should be checking the mode for SFmode as well. */ |
46af8e31 JW |
2682 | |
2683 | #define FUNCTION_ARG_REGNO_P(N) \ | |
e6f884cd | 2684 | ((((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \ |
d239cdc0 EC |
2685 | || ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST \ |
2686 | && (((N) % FP_INC) == 0 \ | |
2687 | && (! mips_abi == ABI_O64))) \ | |
2688 | && !fixed_regs[N])) | |
e75b25e7 MM |
2689 | |
2690 | /* A C expression which can inhibit the returning of certain function | |
2691 | values in registers, based on the type of value. A nonzero value says | |
2692 | to return the function value in memory, just as large structures are | |
2693 | always returned. Here TYPE will be a C expression of type | |
2694 | `tree', representing the data type of the value. | |
2695 | ||
e14fa9c4 DE |
2696 | Note that values of mode `BLKmode' must be explicitly |
2697 | handled by this macro. Also, the option `-fpcc-struct-return' | |
e75b25e7 MM |
2698 | takes effect regardless of this macro. On most systems, it is |
2699 | possible to leave the macro undefined; this causes a default | |
e14fa9c4 DE |
2700 | definition to be used, whose value is the constant 1 for BLKmode |
2701 | values, and 0 otherwise. | |
e75b25e7 MM |
2702 | |
2703 | GCC normally converts 1 byte structures into chars, 2 byte | |
2704 | structs into shorts, and 4 byte structs into ints, and returns | |
2705 | them this way. Defining the following macro overrides this, | |
2706 | to give us MIPS cc compatibility. */ | |
2707 | ||
2708 | #define RETURN_IN_MEMORY(TYPE) \ | |
54401342 | 2709 | mips_return_in_memory (TYPE) |
4d72536e RS |
2710 | |
2711 | #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ | |
2712 | (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \ | |
2713 | (TYPE), (NO_RTL)) | |
e75b25e7 | 2714 | \f |
e75b25e7 MM |
2715 | |
2716 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT | |
2717 | ||
2718 | \f | |
2719 | /* Define a data type for recording info about an argument list | |
2720 | during the scan of that argument list. This data type should | |
2721 | hold all necessary information about the function itself | |
2722 | and about the args processed so far, enough to enable macros | |
2723 | such as FUNCTION_ARG to determine where the next arg should go. | |
2bcb2ab3 | 2724 | |
4d72536e RS |
2725 | This structure has to cope with two different argument allocation |
2726 | schemes. Most MIPS ABIs view the arguments as a struct, of which the | |
2727 | first N words go in registers and the rest go on the stack. If I < N, | |
2728 | the Ith word might go in Ith integer argument register or the | |
2729 | Ith floating-point one. In some cases, it has to go in both (see | |
2730 | function_arg). For these ABIs, we only need to remember the number | |
2731 | of words passed so far. | |
2732 | ||
2733 | The EABI instead allocates the integer and floating-point arguments | |
2734 | separately. The first N words of FP arguments go in FP registers, | |
2735 | the rest go on the stack. Likewise, the first N words of the other | |
2736 | arguments go in integer registers, and the rest go on the stack. We | |
2737 | need to maintain three counts: the number of integer registers used, | |
2738 | the number of floating-point registers used, and the number of words | |
2739 | passed on the stack. | |
2740 | ||
2741 | We could keep separate information for the two ABIs (a word count for | |
2742 | the standard ABIs, and three separate counts for the EABI). But it | |
2743 | seems simpler to view the standard ABIs as forms of EABI that do not | |
2744 | allocate floating-point registers. | |
2745 | ||
2746 | So for the standard ABIs, the first N words are allocated to integer | |
2747 | registers, and function_arg decides on an argument-by-argument basis | |
2748 | whether that argument should really go in an integer register, or in | |
2749 | a floating-point one. */ | |
e75b25e7 MM |
2750 | |
2751 | typedef struct mips_args { | |
4d72536e RS |
2752 | /* Always true for varargs functions. Otherwise true if at least |
2753 | one argument has been passed in an integer register. */ | |
2754 | int gp_reg_found; | |
2755 | ||
2756 | /* The number of arguments seen so far. */ | |
2757 | unsigned int arg_number; | |
2758 | ||
2759 | /* For EABI, the number of integer registers used so far. For other | |
2760 | ABIs, the number of words passed in registers (whether integer | |
2761 | or floating-point). */ | |
bb63e5a0 | 2762 | unsigned int num_gprs; |
4d72536e RS |
2763 | |
2764 | /* For EABI, the number of floating-point registers used so far. */ | |
bb63e5a0 | 2765 | unsigned int num_fprs; |
4d72536e RS |
2766 | |
2767 | /* The number of words passed on the stack. */ | |
2768 | unsigned int stack_words; | |
2769 | ||
2770 | /* On the mips16, we need to keep track of which floating point | |
2771 | arguments were passed in general registers, but would have been | |
2772 | passed in the FP regs if this were a 32 bit function, so that we | |
2773 | can move them to the FP regs if we wind up calling a 32 bit | |
2774 | function. We record this information in fp_code, encoded in base | |
2775 | four. A zero digit means no floating point argument, a one digit | |
2776 | means an SFmode argument, and a two digit means a DFmode argument, | |
2777 | and a three digit is not used. The low order digit is the first | |
2778 | argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by | |
2779 | an SFmode argument. ??? A more sophisticated approach will be | |
2780 | needed if MIPS_ABI != ABI_32. */ | |
2781 | int fp_code; | |
2782 | ||
2783 | /* True if the function has a prototype. */ | |
2784 | int prototype; | |
2785 | ||
2786 | /* When a structure does not take up a full register, the argument | |
2787 | should sometimes be shifted left so that it occupies the high part | |
2788 | of the register. These two fields describe an array of ashl | |
2789 | patterns for doing this. See function_arg_advance, which creates | |
2790 | the shift patterns, and function_arg, which returns them when given | |
2791 | a VOIDmode argument. */ | |
2792 | unsigned int num_adjusts; | |
2793 | struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS]; | |
e75b25e7 MM |
2794 | } CUMULATIVE_ARGS; |
2795 | ||
2796 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2797 | for a call to a function whose data type is FNTYPE. | |
2798 | For a library call, FNTYPE is 0. | |
2799 | ||
2800 | */ | |
2801 | ||
2c7ee1a6 | 2802 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
e75b25e7 MM |
2803 | init_cumulative_args (&CUM, FNTYPE, LIBNAME) \ |
2804 | ||
2805 | /* Update the data in CUM to advance over an argument | |
2806 | of mode MODE and data type TYPE. | |
2807 | (TYPE is null for libcalls where that information may not be available.) */ | |
2808 | ||
2809 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
2810 | function_arg_advance (&CUM, MODE, TYPE, NAMED) | |
2811 | ||
2812 | /* Determine where to put an argument to a function. | |
2813 | Value is zero to push the argument on the stack, | |
2814 | or a hard register in which to store the argument. | |
2815 | ||
2816 | MODE is the argument's machine mode. | |
2817 | TYPE is the data type of the argument (as a tree). | |
2818 | This is null for libcalls where that information may | |
2819 | not be available. | |
2820 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2821 | the preceding args and about the function being called. | |
2822 | NAMED is nonzero if this argument is a named parameter | |
2823 | (otherwise it is an extra parameter matching an ellipsis). */ | |
2824 | ||
2825 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
2826 | function_arg( &CUM, MODE, TYPE, NAMED) | |
2827 | ||
2828 | /* For an arg passed partly in registers and partly in memory, | |
2829 | this is the number of registers used. | |
987ba558 | 2830 | For args passed entirely in registers or entirely in memory, zero. */ |
e75b25e7 MM |
2831 | |
2832 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
2833 | function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) | |
2834 | ||
2835 | /* If defined, a C expression that gives the alignment boundary, in | |
2836 | bits, of an argument with the specified mode and type. If it is | |
2837 | not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
2838 | ||
2839 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
2840 | (((TYPE) != 0) \ | |
75131237 | 2841 | ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \ |
e75b25e7 MM |
2842 | ? PARM_BOUNDARY \ |
2843 | : TYPE_ALIGN(TYPE)) \ | |
2844 | : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \ | |
2845 | ? PARM_BOUNDARY \ | |
2846 | : GET_MODE_ALIGNMENT(MODE))) | |
2847 | ||
4d72536e RS |
2848 | /* True if using EABI and varargs can be passed in floating-point |
2849 | registers. Under these conditions, we need a more complex form | |
2850 | of va_list, which tracks GPR, FPR and stack arguments separately. */ | |
2851 | #define EABI_FLOAT_VARARGS_P \ | |
2852 | (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) | |
2853 | ||
e75b25e7 | 2854 | \f |
e75b25e7 MM |
2855 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ |
2856 | ||
2857 | #define MUST_SAVE_REGISTER(regno) \ | |
2bcb2ab3 GK |
2858 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ |
2859 | || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
ab78d4a8 | 2860 | || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31])) |
e75b25e7 MM |
2861 | |
2862 | /* ALIGN FRAMES on double word boundaries */ | |
d1c17572 JL |
2863 | #ifndef MIPS_STACK_ALIGN |
2864 | #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7) | |
2865 | #endif | |
e75b25e7 | 2866 | |
5d3f2bd5 RH |
2867 | \f |
2868 | /* Define the `__builtin_va_list' type for the ABI. */ | |
2869 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
2870 | (VALIST) = mips_build_va_list () | |
2871 | ||
2872 | /* Implement `va_start' for varargs and stdarg. */ | |
2873 | #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \ | |
2874 | mips_va_start (stdarg, valist, nextarg) | |
2875 | ||
2876 | /* Implement `va_arg'. */ | |
2877 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
2878 | mips_va_arg (valist, type) | |
e75b25e7 MM |
2879 | \f |
2880 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
2881 | for profiling a function entry. */ | |
2882 | ||
2883 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
2884 | { \ | |
2bcb2ab3 GK |
2885 | if (TARGET_MIPS16) \ |
2886 | sorry ("mips16 function profiling"); \ | |
e75b25e7 MM |
2887 | fprintf (FILE, "\t.set\tnoat\n"); \ |
2888 | fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \ | |
2889 | reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \ | |
876c09d3 JW |
2890 | fprintf (FILE, \ |
2891 | "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \ | |
2892 | TARGET_64BIT ? "dsubu" : "subu", \ | |
e75b25e7 | 2893 | reg_names[STACK_POINTER_REGNUM], \ |
876c09d3 | 2894 | reg_names[STACK_POINTER_REGNUM], \ |
1eeed24e | 2895 | Pmode == DImode ? 16 : 8); \ |
0617ed52 | 2896 | fprintf (FILE, "\tjal\t_mcount\n"); \ |
e75b25e7 MM |
2897 | fprintf (FILE, "\t.set\tat\n"); \ |
2898 | } | |
2899 | ||
d8d5b1e1 MM |
2900 | /* Define this macro if the code for function profiling should come |
2901 | before the function prologue. Normally, the profiling code comes | |
2902 | after. */ | |
2903 | ||
2904 | /* #define PROFILE_BEFORE_PROLOGUE */ | |
2905 | ||
e75b25e7 MM |
2906 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
2907 | the stack pointer does not matter. The value is tested only in | |
2908 | functions that have frame pointers. | |
2909 | No definition is equivalent to always zero. */ | |
2910 | ||
2911 | #define EXIT_IGNORE_STACK 1 | |
2912 | ||
2913 | \f | |
2914 | /* A C statement to output, on the stream FILE, assembler code for a | |
7dac2f89 | 2915 | block of data that contains the constant parts of a trampoline. |
e75b25e7 MM |
2916 | This code should not include a label--the label is taken care of |
2917 | automatically. */ | |
2918 | ||
2919 | #define TRAMPOLINE_TEMPLATE(STREAM) \ | |
2920 | { \ | |
2921 | fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \ | |
2922 | fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \ | |
2923 | fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \ | |
1eeed24e | 2924 | if (Pmode == DImode) \ |
876c09d3 JW |
2925 | { \ |
2926 | fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \ | |
2927 | fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \ | |
2928 | } \ | |
2929 | else \ | |
2930 | { \ | |
0acefe54 JW |
2931 | fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \ |
2932 | fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \ | |
876c09d3 | 2933 | } \ |
0acefe54 | 2934 | fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \ |
e75b25e7 MM |
2935 | fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \ |
2936 | fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \ | |
1eeed24e | 2937 | if (Pmode == DImode) \ |
876c09d3 | 2938 | { \ |
876c09d3 JW |
2939 | fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \ |
2940 | fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \ | |
2941 | } \ | |
2942 | else \ | |
2943 | { \ | |
2944 | fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \ | |
2945 | fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \ | |
2946 | } \ | |
e75b25e7 MM |
2947 | } |
2948 | ||
2949 | /* A C expression for the size in bytes of the trampoline, as an | |
2950 | integer. */ | |
2951 | ||
1eeed24e | 2952 | #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8)) |
e75b25e7 | 2953 | |
876c09d3 | 2954 | /* Alignment required for trampolines, in bits. */ |
e75b25e7 | 2955 | |
1eeed24e | 2956 | #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32) |
e75b25e7 | 2957 | |
c85f7c16 JL |
2958 | /* INITIALIZE_TRAMPOLINE calls this library function to flush |
2959 | program and data caches. */ | |
2960 | ||
2961 | #ifndef CACHE_FLUSH_FUNC | |
2962 | #define CACHE_FLUSH_FUNC "_flush_cache" | |
2963 | #endif | |
2964 | ||
7dac2f89 | 2965 | /* A C statement to initialize the variable parts of a trampoline. |
e75b25e7 MM |
2966 | ADDR is an RTX for the address of the trampoline; FNADDR is an |
2967 | RTX for the address of the nested function; STATIC_CHAIN is an | |
2968 | RTX for the static chain value that should be passed to the | |
2969 | function when it is called. */ | |
2970 | ||
2971 | #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \ | |
2972 | { \ | |
2973 | rtx addr = ADDR; \ | |
1eeed24e | 2974 | if (Pmode == DImode) \ |
876c09d3 | 2975 | { \ |
c5c76735 JL |
2976 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \ |
2977 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\ | |
876c09d3 JW |
2978 | } \ |
2979 | else \ | |
2980 | { \ | |
c5c76735 JL |
2981 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \ |
2982 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\ | |
876c09d3 | 2983 | } \ |
e75b25e7 | 2984 | \ |
22b54c57 RK |
2985 | /* Flush both caches. We need to flush the data cache in case \ |
2986 | the system has a write-back cache. */ \ | |
876c09d3 | 2987 | /* ??? Should check the return value for errors. */ \ |
d490e8ad DD |
2988 | if (mips_cache_flush_func && mips_cache_flush_func[0]) \ |
2989 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ | |
2990 | 0, VOIDmode, 3, addr, Pmode, \ | |
2991 | GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\ | |
2992 | GEN_INT (3), TYPE_MODE (integer_type_node)); \ | |
e75b25e7 | 2993 | } |
e75b25e7 MM |
2994 | \f |
2995 | /* Addressing modes, and classification of registers for them. */ | |
2996 | ||
940da324 JL |
2997 | /* #define HAVE_POST_INCREMENT 0 */ |
2998 | /* #define HAVE_POST_DECREMENT 0 */ | |
e75b25e7 | 2999 | |
940da324 JL |
3000 | /* #define HAVE_PRE_DECREMENT 0 */ |
3001 | /* #define HAVE_PRE_INCREMENT 0 */ | |
e75b25e7 MM |
3002 | |
3003 | /* These assume that REGNO is a hard or pseudo reg number. | |
3004 | They give nonzero only if REGNO is a hard reg of the suitable class | |
3005 | or a pseudo reg currently allocated to a suitable hard reg. | |
3006 | These definitions are NOT overridden anywhere. */ | |
3007 | ||
2bcb2ab3 GK |
3008 | #define BASE_REG_P(regno, mode) \ |
3009 | (TARGET_MIPS16 \ | |
3010 | ? (M16_REG_P (regno) \ | |
3011 | || (regno) == FRAME_POINTER_REGNUM \ | |
3012 | || (regno) == ARG_POINTER_REGNUM \ | |
3013 | || ((regno) == STACK_POINTER_REGNUM \ | |
3014 | && (GET_MODE_SIZE (mode) == 4 \ | |
3015 | || GET_MODE_SIZE (mode) == 8))) \ | |
3016 | : GP_REG_P (regno)) | |
e75b25e7 | 3017 | |
2bcb2ab3 | 3018 | #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \ |
c3d03e3a | 3019 | BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \ |
2bcb2ab3 GK |
3020 | (mode)) |
3021 | ||
3022 | #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \ | |
3023 | (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode)))) | |
e75b25e7 | 3024 | |
876c09d3 | 3025 | #define REGNO_OK_FOR_INDEX_P(regno) 0 |
2bcb2ab3 GK |
3026 | #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \ |
3027 | GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode)) | |
e75b25e7 MM |
3028 | |
3029 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
3030 | and check its validity for a certain class. | |
3031 | We have two alternate definitions for each of them. | |
3032 | The usual definition accepts all pseudo regs; the other rejects them all. | |
3033 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
3034 | ||
3035 | Most source files want to accept pseudo regs in the hope that | |
3036 | they will get allocated to the class that the insn wants them to be in. | |
3037 | Some source files that are used after register allocation | |
3038 | need to be strict. */ | |
3039 | ||
3040 | #ifndef REG_OK_STRICT | |
2bcb2ab3 | 3041 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
c94c9817 | 3042 | mips_reg_mode_ok_for_base_p (X, MODE, 0) |
e75b25e7 | 3043 | #else |
2bcb2ab3 | 3044 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
c94c9817 | 3045 | mips_reg_mode_ok_for_base_p (X, MODE, 1) |
e75b25e7 MM |
3046 | #endif |
3047 | ||
c94c9817 MM |
3048 | #define REG_OK_FOR_INDEX_P(X) 0 |
3049 | ||
e75b25e7 MM |
3050 | \f |
3051 | /* Maximum number of registers that can appear in a valid memory address. */ | |
3052 | ||
3053 | #define MAX_REGS_PER_ADDRESS 1 | |
3054 | ||
3055 | /* A C compound statement with a conditional `goto LABEL;' executed | |
3056 | if X (an RTX) is a legitimate memory address on the target | |
fb49053f | 3057 | machine for a memory operand of mode MODE. */ |
e75b25e7 MM |
3058 | |
3059 | #if 1 | |
bd9f1972 KG |
3060 | #define GO_PRINTF(x) fprintf(stderr, (x)) |
3061 | #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y)) | |
e75b25e7 MM |
3062 | #define GO_DEBUG_RTX(x) debug_rtx(x) |
3063 | ||
3064 | #else | |
3065 | #define GO_PRINTF(x) | |
3066 | #define GO_PRINTF2(x,y) | |
3067 | #define GO_DEBUG_RTX(x) | |
3068 | #endif | |
3069 | ||
c94c9817 MM |
3070 | #ifdef REG_OK_STRICT |
3071 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
3072 | { \ | |
3073 | if (mips_legitimate_address_p (MODE, X, 1)) \ | |
3074 | goto ADDR; \ | |
e75b25e7 | 3075 | } |
c94c9817 MM |
3076 | #else |
3077 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
3078 | { \ | |
3079 | if (mips_legitimate_address_p (MODE, X, 0)) \ | |
3080 | goto ADDR; \ | |
3081 | } | |
3082 | #endif | |
e75b25e7 MM |
3083 | |
3084 | /* A C expression that is 1 if the RTX X is a constant which is a | |
6eff269e BK |
3085 | valid address. This is defined to be the same as `CONSTANT_P (X)', |
3086 | but rejecting CONST_DOUBLE. */ | |
5de1e2ce JW |
3087 | /* When pic, we must reject addresses of the form symbol+large int. |
3088 | This is because an instruction `sw $4,s+70000' needs to be converted | |
3089 | by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the | |
3090 | assembler would use $at as a temp to load in the large offset. In this | |
3091 | case $at is already in use. We convert such problem addresses to | |
3092 | `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */ | |
516a2dfd | 3093 | /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */ |
31c714e3 | 3094 | #define CONSTANT_ADDRESS_P(X) \ |
6eff269e | 3095 | ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ |
5de1e2ce JW |
3096 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ |
3097 | || (GET_CODE (X) == CONST \ | |
516a2dfd | 3098 | && ! (flag_pic && pic_address_needs_scratch (X)) \ |
a53f72db GRK |
3099 | && (mips_abi == ABI_32 \ |
3100 | || mips_abi == ABI_O64 \ | |
3101 | || mips_abi == ABI_EABI))) \ | |
5de1e2ce | 3102 | && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X))) |
e75b25e7 | 3103 | |
5de1e2ce JW |
3104 | /* Define this, so that when PIC, reload won't try to reload invalid |
3105 | addresses which require two reload registers. */ | |
3106 | ||
3107 | #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) | |
e75b25e7 MM |
3108 | |
3109 | /* Nonzero if the constant value X is a legitimate general operand. | |
3110 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
3111 | ||
3112 | At present, GAS doesn't understand li.[sd], so don't allow it | |
3113 | to be generated at present. Also, the MIPS assembler does not | |
3114 | grok li.d Infinity. */ | |
3115 | ||
7dac2f89 | 3116 | /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. |
8e466531 GRK |
3117 | Note that the Irix 6 assembler problem may already be fixed. |
3118 | Note also that the GET_CODE (X) == CONST test catches the mips16 | |
3119 | gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not | |
3120 | a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or | |
3121 | ABI_64 to work together, we'll need to fix this. */ | |
e75b25e7 | 3122 | #define LEGITIMATE_CONSTANT_P(X) \ |
516a2dfd JW |
3123 | ((GET_CODE (X) != CONST_DOUBLE \ |
3124 | || mips_const_double_ok (X, GET_MODE (X))) \ | |
8e466531 GRK |
3125 | && ! (GET_CODE (X) == CONST \ |
3126 | && ! TARGET_GAS \ | |
3127 | && (mips_abi == ABI_N32 \ | |
3128 | || mips_abi == ABI_64)) \ | |
2bcb2ab3 | 3129 | && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0))) |
e75b25e7 MM |
3130 | |
3131 | /* A C compound statement that attempts to replace X with a valid | |
3132 | memory address for an operand of mode MODE. WIN will be a C | |
3133 | statement label elsewhere in the code; the macro definition may | |
3134 | use | |
3135 | ||
3136 | GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); | |
3137 | ||
3138 | to avoid further processing if the address has become legitimate. | |
3139 | ||
3140 | X will always be the result of a call to `break_out_memory_refs', | |
3141 | and OLDX will be the operand that was given to that function to | |
3142 | produce X. | |
3143 | ||
3144 | The code generated by this macro should not alter the | |
3145 | substructure of X. If it transforms X into a more legitimate | |
3146 | form, it should assign X (which will always be a C variable) a | |
3147 | new value. | |
3148 | ||
3149 | It is not necessary for this macro to come up with a legitimate | |
3150 | address. The compiler has standard ways of doing so in all | |
3151 | cases. In fact, it is safe for this macro to do nothing. But | |
2649b2ee | 3152 | often a machine-dependent strategy can generate better code. |
e75b25e7 | 3153 | |
2649b2ee MM |
3154 | For the MIPS, transform: |
3155 | ||
3156 | memory(X + <large int>) | |
3157 | ||
3158 | into: | |
3159 | ||
3160 | Y = <large int> & ~0x7fff; | |
3161 | Z = X + Y | |
3162 | memory (Z + (<large int> & 0x7fff)); | |
3163 | ||
5de1e2ce JW |
3164 | This is for CSE to find several similar references, and only use one Z. |
3165 | ||
3166 | When PIC, convert addresses of the form memory (symbol+large int) to | |
3167 | memory (reg+large int). */ | |
7dac2f89 | 3168 | |
2649b2ee MM |
3169 | |
3170 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
3171 | { \ | |
3172 | register rtx xinsn = (X); \ | |
3173 | \ | |
3174 | if (TARGET_DEBUG_B_MODE) \ | |
3175 | { \ | |
3176 | GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \ | |
3177 | GO_DEBUG_RTX (xinsn); \ | |
3178 | } \ | |
3179 | \ | |
ce57d6f4 JW |
3180 | if (mips_split_addresses && mips_check_split (X, MODE)) \ |
3181 | { \ | |
3182 | /* ??? Is this ever executed? */ \ | |
c5c76735 JL |
3183 | X = gen_rtx_LO_SUM (Pmode, \ |
3184 | copy_to_mode_reg (Pmode, \ | |
3185 | gen_rtx (HIGH, Pmode, X)), \ | |
3186 | X); \ | |
ce57d6f4 JW |
3187 | goto WIN; \ |
3188 | } \ | |
3189 | \ | |
516a2dfd JW |
3190 | if (GET_CODE (xinsn) == CONST \ |
3191 | && ((flag_pic && pic_address_needs_scratch (xinsn)) \ | |
3192 | /* ??? SGI's Irix 6 assembler can't handle CONST. */ \ | |
a53f72db GRK |
3193 | || (mips_abi != ABI_32 \ |
3194 | && mips_abi != ABI_O64 \ | |
3195 | && mips_abi != ABI_EABI))) \ | |
516a2dfd JW |
3196 | { \ |
3197 | rtx ptr_reg = gen_reg_rtx (Pmode); \ | |
3198 | rtx constant = XEXP (XEXP (xinsn, 0), 1); \ | |
3199 | \ | |
3200 | emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \ | |
3201 | \ | |
c5c76735 | 3202 | X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \ |
516a2dfd JW |
3203 | if (SMALL_INT (constant)) \ |
3204 | goto WIN; \ | |
3205 | /* Otherwise we fall through so the code below will fix the \ | |
3206 | constant. */ \ | |
3207 | xinsn = X; \ | |
3208 | } \ | |
3209 | \ | |
b3de0f1f | 3210 | if (GET_CODE (xinsn) == PLUS) \ |
2649b2ee MM |
3211 | { \ |
3212 | register rtx xplus0 = XEXP (xinsn, 0); \ | |
3213 | register rtx xplus1 = XEXP (xinsn, 1); \ | |
3214 | register enum rtx_code code0 = GET_CODE (xplus0); \ | |
3215 | register enum rtx_code code1 = GET_CODE (xplus1); \ | |
3216 | \ | |
3217 | if (code0 != REG && code1 == REG) \ | |
3218 | { \ | |
3219 | xplus0 = XEXP (xinsn, 1); \ | |
3220 | xplus1 = XEXP (xinsn, 0); \ | |
3221 | code0 = GET_CODE (xplus0); \ | |
3222 | code1 = GET_CODE (xplus1); \ | |
3223 | } \ | |
3224 | \ | |
2bcb2ab3 | 3225 | if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \ |
2649b2ee MM |
3226 | && code1 == CONST_INT && !SMALL_INT (xplus1)) \ |
3227 | { \ | |
3228 | rtx int_reg = gen_reg_rtx (Pmode); \ | |
3229 | rtx ptr_reg = gen_reg_rtx (Pmode); \ | |
3230 | \ | |
3231 | emit_move_insn (int_reg, \ | |
3232 | GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \ | |
3233 | \ | |
c5c76735 JL |
3234 | emit_insn (gen_rtx_SET (VOIDmode, \ |
3235 | ptr_reg, \ | |
3236 | gen_rtx_PLUS (Pmode, xplus0, int_reg))); \ | |
2649b2ee | 3237 | \ |
8da665d5 | 3238 | X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \ |
2649b2ee MM |
3239 | goto WIN; \ |
3240 | } \ | |
3241 | } \ | |
3242 | \ | |
3243 | if (TARGET_DEBUG_B_MODE) \ | |
3244 | GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \ | |
3245 | } | |
e75b25e7 MM |
3246 | |
3247 | ||
3248 | /* A C statement or compound statement with a conditional `goto | |
3249 | LABEL;' executed if memory address X (an RTX) can have different | |
3250 | meanings depending on the machine mode of the memory reference it | |
3251 | is used for. | |
3252 | ||
3253 | Autoincrement and autodecrement addresses typically have | |
3254 | mode-dependent effects because the amount of the increment or | |
3255 | decrement is the size of the operand being addressed. Some | |
3256 | machines have other mode-dependent addresses. Many RISC machines | |
3257 | have no mode-dependent addresses. | |
3258 | ||
3259 | You may assume that ADDR is a valid address for the machine. */ | |
3260 | ||
3261 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} | |
3262 | ||
9c9e7632 GK |
3263 | /* This handles the magic '..CURRENT_FUNCTION' symbol, which means |
3264 | 'the start of the function that this code is output in'. */ | |
3265 | ||
3266 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
3267 | if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ | |
3268 | asm_fprintf ((FILE), "%U%s", \ | |
3269 | XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ | |
3270 | else \ | |
3271 | asm_fprintf ((FILE), "%U%s", (NAME)) | |
3272 | ||
2bcb2ab3 GK |
3273 | /* The mips16 wants the constant pool to be after the function, |
3274 | because the PC relative load instructions use unsigned offsets. */ | |
3275 | ||
3276 | #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16) | |
3277 | ||
3278 | #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \ | |
3279 | mips_string_length = 0; | |
3280 | ||
3281 | #if 0 | |
3282 | /* In mips16 mode, put most string constants after the function. */ | |
3283 | #define CONSTANT_AFTER_FUNCTION_P(tree) \ | |
3284 | (TARGET_MIPS16 && mips16_constant_after_function_p (tree)) | |
3285 | #endif | |
e75b25e7 MM |
3286 | \f |
3287 | /* Specify the machine mode that this machine uses | |
2bcb2ab3 GK |
3288 | for the index in the tablejump instruction. |
3289 | ??? Using HImode in mips16 mode can cause overflow. However, the | |
3290 | overflow is no more likely than the overflow in a branch | |
3291 | instruction. Large functions can currently break in both ways. */ | |
3292 | #define CASE_VECTOR_MODE \ | |
1eeed24e | 3293 | (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode) |
2bcb2ab3 GK |
3294 | |
3295 | /* Define as C expression which evaluates to nonzero if the tablejump | |
3296 | instruction expects the table to contain offsets from the address of the | |
3297 | table. | |
987ba558 | 3298 | Do not define this if the table should contain absolute addresses. */ |
2bcb2ab3 | 3299 | #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16) |
e75b25e7 | 3300 | |
e75b25e7 | 3301 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
6639753e | 3302 | #ifndef DEFAULT_SIGNED_CHAR |
e75b25e7 | 3303 | #define DEFAULT_SIGNED_CHAR 1 |
6639753e | 3304 | #endif |
e75b25e7 MM |
3305 | |
3306 | /* Max number of bytes we can move from memory to memory | |
3307 | in one reasonably fast instruction. */ | |
876c09d3 JW |
3308 | #define MOVE_MAX (TARGET_64BIT ? 8 : 4) |
3309 | #define MAX_MOVE_MAX 8 | |
e75b25e7 MM |
3310 | |
3311 | /* Define this macro as a C expression which is nonzero if | |
3312 | accessing less than a word of memory (i.e. a `char' or a | |
3313 | `short') is no faster than accessing a word of memory, i.e., if | |
3314 | such access require more than one instruction or if there is no | |
3315 | difference in cost between byte and (aligned) word loads. | |
3316 | ||
3317 | On RISC machines, it tends to generate better code to define | |
3318 | this as 1, since it avoids making a QI or HI mode register. */ | |
3319 | #define SLOW_BYTE_ACCESS 1 | |
3320 | ||
3321 | /* We assume that the store-condition-codes instructions store 0 for false | |
3322 | and some other value for true. This is the value stored for true. */ | |
3323 | ||
3324 | #define STORE_FLAG_VALUE 1 | |
3325 | ||
d969caf8 | 3326 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
987ba558 | 3327 | few bits. */ |
d969caf8 | 3328 | #define SHIFT_COUNT_TRUNCATED 1 |
e75b25e7 MM |
3329 | |
3330 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
3331 | is done just by pretending it is already truncated. */ | |
876c09d3 JW |
3332 | /* In 64 bit mode, 32 bit instructions require that register values be properly |
3333 | sign-extended to 64 bits. As a result, a truncate is not a no-op if it | |
3334 | converts a value >32 bits to a value <32 bits. */ | |
3335 | /* ??? This results in inefficient code for 64 bit to 32 conversions. | |
3336 | Something needs to be done about this. Perhaps not use any 32 bit | |
3337 | instructions? Perhaps use PROMOTE_MODE? */ | |
3338 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ | |
3339 | (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1) | |
e75b25e7 | 3340 | |
e75b25e7 MM |
3341 | /* Specify the machine mode that pointers have. |
3342 | After generation of rtl, the compiler makes no further distinction | |
fb1bf66d GRK |
3343 | between pointers and any other objects of this machine mode. |
3344 | ||
987ba558 | 3345 | For MIPS we make pointers are the smaller of longs and gp-registers. */ |
876c09d3 | 3346 | |
1eeed24e | 3347 | #ifndef Pmode |
8ca47902 | 3348 | #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode) |
1eeed24e | 3349 | #endif |
e75b25e7 MM |
3350 | |
3351 | /* A function address in a call instruction | |
3352 | is a word address (for indexing purposes) | |
3353 | so give the MEM rtx a words's mode. */ | |
3354 | ||
1eeed24e | 3355 | #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode) |
e75b25e7 MM |
3356 | |
3357 | /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and | |
3358 | memset, instead of the BSD functions bcopy and bzero. */ | |
3359 | ||
3360 | #if defined(MIPS_SYSV) || defined(OSF_OS) | |
3361 | #define TARGET_MEM_FUNCTIONS | |
3362 | #endif | |
3363 | ||
3364 | \f | |
3365 | /* A part of a C `switch' statement that describes the relative | |
3366 | costs of constant RTL expressions. It must contain `case' | |
3367 | labels for expression codes `const_int', `const', `symbol_ref', | |
3368 | `label_ref' and `const_double'. Each case must ultimately reach | |
3369 | a `return' statement to return the relative cost of the use of | |
3370 | that kind of constant value in an expression. The cost may | |
3371 | depend on the precise value of the constant, which is available | |
3372 | for examination in X. | |
3373 | ||
3374 | CODE is the expression code--redundant, since it can be obtained | |
3375 | with `GET_CODE (X)'. */ | |
3376 | ||
def9623c | 3377 | #define CONST_COSTS(X,CODE,OUTER_CODE) \ |
e75b25e7 | 3378 | case CONST_INT: \ |
2bcb2ab3 GK |
3379 | if (! TARGET_MIPS16) \ |
3380 | { \ | |
3381 | /* Always return 0, since we don't have different sized \ | |
3382 | instructions, hence different costs according to Richard \ | |
3383 | Kenner */ \ | |
3384 | return 0; \ | |
3385 | } \ | |
3386 | if ((OUTER_CODE) == SET) \ | |
3387 | { \ | |
3388 | if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \ | |
3389 | return 0; \ | |
3390 | else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \ | |
3391 | || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \ | |
3392 | return COSTS_N_INSNS (1); \ | |
3393 | else \ | |
3394 | return COSTS_N_INSNS (2); \ | |
3395 | } \ | |
3396 | /* A PLUS could be an address. We don't want to force an address \ | |
3397 | to use a register, so accept any signed 16 bit value without \ | |
3398 | complaint. */ \ | |
3399 | if ((OUTER_CODE) == PLUS \ | |
3400 | && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \ | |
3401 | return 0; \ | |
3402 | /* A number between 1 and 8 inclusive is efficient for a shift. \ | |
3403 | Otherwise, we will need an extended instruction. */ \ | |
3404 | if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \ | |
3405 | || (OUTER_CODE) == LSHIFTRT) \ | |
3406 | { \ | |
3407 | if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \ | |
3408 | return 0; \ | |
3409 | return COSTS_N_INSNS (1); \ | |
3410 | } \ | |
3411 | /* We can use cmpi for an xor with an unsigned 16 bit value. */ \ | |
3412 | if ((OUTER_CODE) == XOR \ | |
3413 | && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \ | |
3414 | return 0; \ | |
3415 | /* We may be able to use slt or sltu for a comparison with a \ | |
3416 | signed 16 bit value. (The boundary conditions aren't quite \ | |
3417 | right, but this is just a heuristic anyhow.) */ \ | |
3418 | if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \ | |
3419 | || (OUTER_CODE) == GE || (OUTER_CODE) == GT \ | |
3420 | || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \ | |
3421 | || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \ | |
3422 | && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \ | |
3423 | return 0; \ | |
3424 | /* Equality comparisons with 0 are cheap. */ \ | |
3425 | if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \ | |
3426 | && INTVAL (X) == 0) \ | |
3427 | return 0; \ | |
3428 | \ | |
3429 | /* Otherwise, work out the cost to load the value into a \ | |
3430 | register. */ \ | |
3431 | if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \ | |
3432 | return COSTS_N_INSNS (1); \ | |
3433 | else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \ | |
3434 | || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \ | |
3435 | return COSTS_N_INSNS (2); \ | |
3436 | else \ | |
3437 | return COSTS_N_INSNS (3); \ | |
e75b25e7 MM |
3438 | \ |
3439 | case LABEL_REF: \ | |
3440 | return COSTS_N_INSNS (2); \ | |
3441 | \ | |
3442 | case CONST: \ | |
3443 | { \ | |
31c714e3 | 3444 | rtx offset = const0_rtx; \ |
876c09d3 | 3445 | rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \ |
e75b25e7 | 3446 | \ |
2bcb2ab3 GK |
3447 | if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \ |
3448 | { \ | |
3449 | /* Treat this like a signed 16 bit CONST_INT. */ \ | |
3450 | if ((OUTER_CODE) == PLUS) \ | |
3451 | return 0; \ | |
3452 | else if ((OUTER_CODE) == SET) \ | |
3453 | return COSTS_N_INSNS (1); \ | |
3454 | else \ | |
3455 | return COSTS_N_INSNS (2); \ | |
3456 | } \ | |
3457 | \ | |
e75b25e7 MM |
3458 | if (GET_CODE (symref) == LABEL_REF) \ |
3459 | return COSTS_N_INSNS (2); \ | |
3460 | \ | |
3461 | if (GET_CODE (symref) != SYMBOL_REF) \ | |
3462 | return COSTS_N_INSNS (4); \ | |
3463 | \ | |
987ba558 | 3464 | /* let's be paranoid.... */ \ |
31c714e3 | 3465 | if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \ |
e75b25e7 MM |
3466 | return COSTS_N_INSNS (2); \ |
3467 | \ | |
3468 | return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \ | |
3469 | } \ | |
3470 | \ | |
3471 | case SYMBOL_REF: \ | |
3472 | return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \ | |
3473 | \ | |
3474 | case CONST_DOUBLE: \ | |
96abdcb1 ILT |
3475 | { \ |
3476 | rtx high, low; \ | |
2bcb2ab3 GK |
3477 | if (TARGET_MIPS16) \ |
3478 | return COSTS_N_INSNS (4); \ | |
96abdcb1 ILT |
3479 | split_double (X, &high, &low); \ |
3480 | return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \ | |
3481 | || low == CONST0_RTX (GET_MODE (low))) \ | |
3482 | ? 2 : 4); \ | |
3483 | } | |
e75b25e7 MM |
3484 | |
3485 | /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. | |
3486 | This can be used, for example, to indicate how costly a multiply | |
3487 | instruction is. In writing this macro, you can use the construct | |
3488 | `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions. | |
3489 | ||
3490 | This macro is optional; do not define it if the default cost | |
3491 | assumptions are adequate for the target machine. | |
3492 | ||
3493 | If -mdebugd is used, change the multiply cost to 2, so multiply by | |
3494 | a constant isn't converted to a series of shifts. This helps | |
3495 | strength reduction, and also makes it easier to identify what the | |
3496 | compiler is doing. */ | |
3497 | ||
516a2dfd | 3498 | /* ??? Fix this to be right for the R8000. */ |
def9623c | 3499 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
e75b25e7 MM |
3500 | case MEM: \ |
3501 | { \ | |
3502 | int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \ | |
3503 | if (simple_memory_operand (X, GET_MODE (X))) \ | |
3504 | return COSTS_N_INSNS (num_words); \ | |
3505 | \ | |
3506 | return COSTS_N_INSNS (2*num_words); \ | |
3507 | } \ | |
3508 | \ | |
3509 | case FFS: \ | |
3510 | return COSTS_N_INSNS (6); \ | |
3511 | \ | |
3512 | case NOT: \ | |
876c09d3 | 3513 | return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \ |
e75b25e7 MM |
3514 | \ |
3515 | case AND: \ | |
3516 | case IOR: \ | |
3517 | case XOR: \ | |
876c09d3 | 3518 | if (GET_MODE (X) == DImode && !TARGET_64BIT) \ |
e75b25e7 MM |
3519 | return COSTS_N_INSNS (2); \ |
3520 | \ | |
2bcb2ab3 | 3521 | break; \ |
e75b25e7 MM |
3522 | \ |
3523 | case ASHIFT: \ | |
3524 | case ASHIFTRT: \ | |
e75b25e7 | 3525 | case LSHIFTRT: \ |
876c09d3 JW |
3526 | if (GET_MODE (X) == DImode && !TARGET_64BIT) \ |
3527 | return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \ | |
e75b25e7 | 3528 | \ |
2bcb2ab3 | 3529 | break; \ |
e75b25e7 MM |
3530 | \ |
3531 | case ABS: \ | |
3532 | { \ | |
3533 | enum machine_mode xmode = GET_MODE (X); \ | |
3534 | if (xmode == SFmode || xmode == DFmode) \ | |
3535 | return COSTS_N_INSNS (1); \ | |
3536 | \ | |
3537 | return COSTS_N_INSNS (4); \ | |
3538 | } \ | |
3539 | \ | |
3540 | case PLUS: \ | |
3541 | case MINUS: \ | |
3542 | { \ | |
3543 | enum machine_mode xmode = GET_MODE (X); \ | |
3544 | if (xmode == SFmode || xmode == DFmode) \ | |
9a863c83 | 3545 | { \ |
7dac2f89 EC |
3546 | if (TUNE_MIPS3000 \ |
3547 | || TUNE_MIPS3900) \ | |
9a863c83 | 3548 | return COSTS_N_INSNS (2); \ |
7dac2f89 | 3549 | else if (TUNE_MIPS6000) \ |
9a863c83 JW |
3550 | return COSTS_N_INSNS (3); \ |
3551 | else \ | |
3552 | return COSTS_N_INSNS (6); \ | |
3553 | } \ | |
e75b25e7 | 3554 | \ |
876c09d3 | 3555 | if (xmode == DImode && !TARGET_64BIT) \ |
e75b25e7 MM |
3556 | return COSTS_N_INSNS (4); \ |
3557 | \ | |
2bcb2ab3 | 3558 | break; \ |
e75b25e7 MM |
3559 | } \ |
3560 | \ | |
3561 | case NEG: \ | |
2bcb2ab3 GK |
3562 | if (GET_MODE (X) == DImode && !TARGET_64BIT) \ |
3563 | return 4; \ | |
3564 | \ | |
3565 | break; \ | |
e75b25e7 MM |
3566 | \ |
3567 | case MULT: \ | |
3568 | { \ | |
3569 | enum machine_mode xmode = GET_MODE (X); \ | |
3570 | if (xmode == SFmode) \ | |
9a863c83 | 3571 | { \ |
7dac2f89 EC |
3572 | if (TUNE_MIPS3000 \ |
3573 | || TUNE_MIPS3900 \ | |
3574 | || TUNE_MIPS5000) \ | |
9a863c83 | 3575 | return COSTS_N_INSNS (4); \ |
7dac2f89 | 3576 | else if (TUNE_MIPS6000) \ |
9a863c83 JW |
3577 | return COSTS_N_INSNS (5); \ |
3578 | else \ | |
3579 | return COSTS_N_INSNS (7); \ | |
3580 | } \ | |
e75b25e7 MM |
3581 | \ |
3582 | if (xmode == DFmode) \ | |
9a863c83 | 3583 | { \ |
7dac2f89 EC |
3584 | if (TUNE_MIPS3000 \ |
3585 | || TUNE_MIPS3900 \ | |
3586 | || TUNE_MIPS5000) \ | |
9a863c83 | 3587 | return COSTS_N_INSNS (5); \ |
7dac2f89 | 3588 | else if (TUNE_MIPS6000) \ |
9a863c83 JW |
3589 | return COSTS_N_INSNS (6); \ |
3590 | else \ | |
3591 | return COSTS_N_INSNS (8); \ | |
3592 | } \ | |
e75b25e7 | 3593 | \ |
7dac2f89 | 3594 | if (TUNE_MIPS3000) \ |
9a863c83 | 3595 | return COSTS_N_INSNS (12); \ |
7dac2f89 | 3596 | else if (TUNE_MIPS3900) \ |
e9a25f70 | 3597 | return COSTS_N_INSNS (2); \ |
7dac2f89 | 3598 | else if (TUNE_MIPS6000) \ |
9a863c83 | 3599 | return COSTS_N_INSNS (17); \ |
7dac2f89 | 3600 | else if (TUNE_MIPS5000) \ |
b8eb88d0 | 3601 | return COSTS_N_INSNS (5); \ |
9a863c83 JW |
3602 | else \ |
3603 | return COSTS_N_INSNS (10); \ | |
e75b25e7 MM |
3604 | } \ |
3605 | \ | |
3606 | case DIV: \ | |
3607 | case MOD: \ | |
3608 | { \ | |
3609 | enum machine_mode xmode = GET_MODE (X); \ | |
3610 | if (xmode == SFmode) \ | |
9a863c83 | 3611 | { \ |
7dac2f89 EC |
3612 | if (TUNE_MIPS3000 \ |
3613 | || TUNE_MIPS3900) \ | |
9a863c83 | 3614 | return COSTS_N_INSNS (12); \ |
7dac2f89 | 3615 | else if (TUNE_MIPS6000) \ |
9a863c83 JW |
3616 | return COSTS_N_INSNS (15); \ |
3617 | else \ | |
3618 | return COSTS_N_INSNS (23); \ | |
3619 | } \ | |
e75b25e7 MM |
3620 | \ |
3621 | if (xmode == DFmode) \ | |
9a863c83 | 3622 | { \ |
7dac2f89 EC |
3623 | if (TUNE_MIPS3000 \ |
3624 | || TUNE_MIPS3900) \ | |
9a863c83 | 3625 | return COSTS_N_INSNS (19); \ |
7dac2f89 | 3626 | else if (TUNE_MIPS6000) \ |
9a863c83 JW |
3627 | return COSTS_N_INSNS (16); \ |
3628 | else \ | |
3629 | return COSTS_N_INSNS (36); \ | |
3630 | } \ | |
e75b25e7 MM |
3631 | } \ |
3632 | /* fall through */ \ | |
3633 | \ | |
3634 | case UDIV: \ | |
3635 | case UMOD: \ | |
7dac2f89 EC |
3636 | if (TUNE_MIPS3000 \ |
3637 | || TUNE_MIPS3900) \ | |
9a863c83 | 3638 | return COSTS_N_INSNS (35); \ |
7dac2f89 | 3639 | else if (TUNE_MIPS6000) \ |
9a863c83 | 3640 | return COSTS_N_INSNS (38); \ |
7dac2f89 | 3641 | else if (TUNE_MIPS5000) \ |
b8eb88d0 | 3642 | return COSTS_N_INSNS (36); \ |
9a863c83 | 3643 | else \ |
1a4fa807 ILT |
3644 | return COSTS_N_INSNS (69); \ |
3645 | \ | |
3646 | case SIGN_EXTEND: \ | |
3647 | /* A sign extend from SImode to DImode in 64 bit mode is often \ | |
3648 | zero instructions, because the result can often be used \ | |
3649 | directly by another instruction; we'll call it one. */ \ | |
3650 | if (TARGET_64BIT && GET_MODE (X) == DImode \ | |
3651 | && GET_MODE (XEXP (X, 0)) == SImode) \ | |
3652 | return COSTS_N_INSNS (1); \ | |
3653 | else \ | |
3654 | return COSTS_N_INSNS (2); \ | |
3655 | \ | |
3656 | case ZERO_EXTEND: \ | |
3657 | if (TARGET_64BIT && GET_MODE (X) == DImode \ | |
3658 | && GET_MODE (XEXP (X, 0)) == SImode) \ | |
3659 | return COSTS_N_INSNS (2); \ | |
3660 | else \ | |
3661 | return COSTS_N_INSNS (1); | |
e75b25e7 MM |
3662 | |
3663 | /* An expression giving the cost of an addressing mode that | |
3664 | contains ADDRESS. If not defined, the cost is computed from the | |
3665 | form of the ADDRESS expression and the `CONST_COSTS' values. | |
3666 | ||
3667 | For most CISC machines, the default cost is a good approximation | |
3668 | of the true cost of the addressing mode. However, on RISC | |
3669 | machines, all instructions normally have the same length and | |
3670 | execution time. Hence all addresses will have equal costs. | |
3671 | ||
3672 | In cases where more than one form of an address is known, the | |
3673 | form with the lowest cost will be used. If multiple forms have | |
3674 | the same, lowest, cost, the one that is the most complex will be | |
3675 | used. | |
3676 | ||
3677 | For example, suppose an address that is equal to the sum of a | |
7dac2f89 | 3678 | register and a constant is used twice in the same basic block. |
e75b25e7 MM |
3679 | When this macro is not defined, the address will be computed in |
3680 | a register and memory references will be indirect through that | |
3681 | register. On machines where the cost of the addressing mode | |
3682 | containing the sum is no higher than that of a simple indirect | |
3683 | reference, this will produce an additional instruction and | |
3684 | possibly require an additional register. Proper specification | |
3685 | of this macro eliminates this overhead for such machines. | |
3686 | ||
3687 | Similar use of this macro is made in strength reduction of loops. | |
3688 | ||
3689 | ADDRESS need not be valid as an address. In such a case, the | |
3690 | cost is not relevant and can be any value; invalid addresses | |
3691 | need not be assigned a different cost. | |
3692 | ||
3693 | On machines where an address involving more than one register is | |
3694 | as cheap as an address computation involving only one register, | |
3695 | defining `ADDRESS_COST' to reflect this can cause two registers | |
3696 | to be live over a region of code where only one would have been | |
3697 | if `ADDRESS_COST' were not defined in that manner. This effect | |
7dac2f89 | 3698 | should be considered in the definition of this macro. |
e75b25e7 MM |
3699 | Equivalent costs should probably only be given to addresses with |
3700 | different numbers of registers on machines with lots of registers. | |
3701 | ||
3702 | This macro will normally either not be defined or be defined as | |
987ba558 | 3703 | a constant. */ |
e75b25e7 MM |
3704 | |
3705 | #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR)) | |
3706 | ||
3707 | /* A C expression for the cost of moving data from a register in | |
3708 | class FROM to one in class TO. The classes are expressed using | |
3709 | the enumeration values such as `GENERAL_REGS'. A value of 2 is | |
3710 | the default; other values are interpreted relative to that. | |
3711 | ||
3712 | It is not required that the cost always equal 2 when FROM is the | |
3713 | same as TO; on some machines it is expensive to move between | |
3714 | registers if they are not general registers. | |
3715 | ||
3716 | If reload sees an insn consisting of a single `set' between two | |
3717 | hard registers, and if `REGISTER_MOVE_COST' applied to their | |
3718 | classes returns a value of 2, reload does not check to ensure | |
3719 | that the constraints of the insn are met. Setting a cost of | |
3720 | other than 2 will allow reload to verify that the constraints are | |
3721 | met. You should do this if the `movM' pattern's constraints do | |
d604bca3 MH |
3722 | not allow such copying. */ |
3723 | ||
3724 | #define REGISTER_MOVE_COST(MODE, FROM, TO) \ | |
3725 | mips_register_move_cost (MODE, FROM, TO) | |
e75b25e7 | 3726 | |
516a2dfd | 3727 | /* ??? Fix this to be right for the R8000. */ |
cbd5b9a2 | 3728 | #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ |
7dac2f89 | 3729 | (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \ |
cbd5b9a2 | 3730 | + memory_move_secondary_cost ((MODE), (CLASS), (TO_P))) |
876c09d3 | 3731 | |
7506f491 DE |
3732 | /* Define if copies to/from condition code registers should be avoided. |
3733 | ||
3734 | This is needed for the MIPS because reload_outcc is not complete; | |
3735 | it needs to handle cases where the source is a general or another | |
3736 | condition code register. */ | |
3737 | #define AVOID_CCMODE_COPIES | |
3738 | ||
e75b25e7 MM |
3739 | /* A C expression for the cost of a branch instruction. A value of |
3740 | 1 is the default; other values are interpreted relative to that. */ | |
3741 | ||
516a2dfd | 3742 | /* ??? Fix this to be right for the R8000. */ |
2bcb2ab3 GK |
3743 | #define BRANCH_COST \ |
3744 | ((! TARGET_MIPS16 \ | |
7dac2f89 | 3745 | && (TUNE_MIPS4000 || TUNE_MIPS6000)) \ |
2bcb2ab3 | 3746 | ? 2 : 1) |
e75b25e7 | 3747 | |
0ff83799 MM |
3748 | /* If defined, modifies the length assigned to instruction INSN as a |
3749 | function of the context in which it is used. LENGTH is an lvalue | |
3750 | that contains the initially computed length of the insn and should | |
3751 | be updated with the correct length of the insn. */ | |
3752 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
3753 | ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) | |
3754 | ||
e75b25e7 MM |
3755 | \f |
3756 | /* Optionally define this if you have added predicates to | |
3757 | `MACHINE.c'. This macro is called within an initializer of an | |
3758 | array of structures. The first field in the structure is the | |
31c714e3 | 3759 | name of a predicate and the second field is an array of rtl |
e75b25e7 MM |
3760 | codes. For each predicate, list all rtl codes that can be in |
3761 | expressions matched by the predicate. The list should have a | |
3762 | trailing comma. Here is an example of two entries in the list | |
3763 | for a typical RISC machine: | |
3764 | ||
3765 | #define PREDICATE_CODES \ | |
3766 | {"gen_reg_rtx_operand", {SUBREG, REG}}, \ | |
3767 | {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}}, | |
3768 | ||
3769 | Defining this macro does not affect the generated code (however, | |
3770 | incorrect definitions that omit an rtl code that may be matched | |
7dac2f89 | 3771 | by the predicate can cause the compiler to malfunction). |
e75b25e7 MM |
3772 | Instead, it allows the table built by `genrecog' to be more |
3773 | compact and efficient, thus speeding up the compiler. The most | |
3774 | important predicates to include in the list specified by this | |
3775 | macro are thoses used in the most insn patterns. */ | |
3776 | ||
3777 | #define PREDICATE_CODES \ | |
3778 | {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \ | |
3779 | {"arith_operand", { REG, CONST_INT, SUBREG }}, \ | |
3780 | {"arith32_operand", { REG, CONST_INT, SUBREG }}, \ | |
def72bd2 GRK |
3781 | {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \ |
3782 | {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \ | |
e75b25e7 MM |
3783 | {"small_int", { CONST_INT }}, \ |
3784 | {"large_int", { CONST_INT }}, \ | |
e75b25e7 | 3785 | {"mips_const_double_ok", { CONST_DOUBLE }}, \ |
b8eb88d0 | 3786 | {"const_float_1_operand", { CONST_DOUBLE }}, \ |
e75b25e7 | 3787 | {"simple_memory_operand", { MEM, SUBREG }}, \ |
e75b25e7 MM |
3788 | {"equality_op", { EQ, NE }}, \ |
3789 | {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \ | |
3790 | LTU, LEU }}, \ | |
a0b6cdee | 3791 | {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \ |
f8634644 | 3792 | {"pc_or_label_operand", { PC, LABEL_REF }}, \ |
ce57d6f4 JW |
3793 | {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \ |
3794 | {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \ | |
3795 | SYMBOL_REF, LABEL_REF, SUBREG, \ | |
3796 | REG, MEM}}, \ | |
1908a152 ILT |
3797 | {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \ |
3798 | SYMBOL_REF, LABEL_REF, SUBREG, REG, \ | |
3799 | MEM, SIGN_EXTEND }}, \ | |
3800 | {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \ | |
def72bd2 | 3801 | {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \ |
1908a152 ILT |
3802 | SIGN_EXTEND }}, \ |
3803 | {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \ | |
3804 | SIGN_EXTEND }}, \ | |
3805 | {"se_arith_operand", { REG, CONST_INT, SUBREG, \ | |
3806 | SIGN_EXTEND }}, \ | |
3807 | {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \ | |
3808 | SYMBOL_REF, LABEL_REF, SUBREG, \ | |
3809 | REG, SIGN_EXTEND }}, \ | |
2bcb2ab3 GK |
3810 | {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \ |
3811 | {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \ | |
cb923660 KR |
3812 | CONST_DOUBLE, CONST }}, \ |
3813 | {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \ | |
3814 | {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }}, | |
3815 | ||
0e7e9155 RH |
3816 | /* A list of predicates that do special things with modes, and so |
3817 | should not elicit warnings for VOIDmode match_operand. */ | |
3818 | ||
3819 | #define SPECIAL_MODE_PREDICATES \ | |
3820 | "pc_or_label_operand", | |
e75b25e7 MM |
3821 | |
3822 | \f | |
3823 | /* If defined, a C statement to be executed just prior to the | |
3824 | output of assembler code for INSN, to modify the extracted | |
3825 | operands so they will be output differently. | |
3826 | ||
3827 | Here the argument OPVEC is the vector containing the operands | |
3828 | extracted from INSN, and NOPERANDS is the number of elements of | |
3829 | the vector which contain meaningful data for this insn. The | |
3830 | contents of this vector are what will be used to convert the | |
3831 | insn template into assembler code, so you can change the | |
3832 | assembler output by changing the contents of the vector. | |
3833 | ||
3834 | We use it to check if the current insn needs a nop in front of it | |
3835 | because of load delays, and also to update the delay slot | |
3836 | statistics. */ | |
3837 | ||
3838 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
65437fe8 | 3839 | final_prescan_insn (INSN, OPVEC, NOPERANDS) |
e75b25e7 | 3840 | |
e75b25e7 MM |
3841 | \f |
3842 | /* Control the assembler format that we output. */ | |
3843 | ||
3844 | /* Output at beginning of assembler file. | |
3845 | If we are optimizing to use the global pointer, create a temporary | |
3846 | file to hold all of the text stuff, and write it out to the end. | |
3847 | This is needed because the MIPS assembler is evidently one pass, | |
3848 | and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata | |
3849 | declaration when the code is processed, it generates a two | |
3850 | instruction sequence. */ | |
3851 | ||
44404b8b | 3852 | #undef ASM_FILE_START |
e75b25e7 MM |
3853 | #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM) |
3854 | ||
3855 | /* Output to assembler file text saying following lines | |
3856 | may contain character constants, extra white space, comments, etc. */ | |
3857 | ||
b2bcb32d | 3858 | #ifndef ASM_APP_ON |
e75b25e7 | 3859 | #define ASM_APP_ON " #APP\n" |
b2bcb32d | 3860 | #endif |
e75b25e7 MM |
3861 | |
3862 | /* Output to assembler file text saying following lines | |
3863 | no longer contain unusual constructs. */ | |
3864 | ||
b2bcb32d | 3865 | #ifndef ASM_APP_OFF |
e75b25e7 | 3866 | #define ASM_APP_OFF " #NO_APP\n" |
b2bcb32d | 3867 | #endif |
e75b25e7 MM |
3868 | |
3869 | /* How to refer to registers in assembler output. | |
3870 | This sequence is indexed by compiler's hard-register-number (see above). | |
3871 | ||
3872 | In order to support the two different conventions for register names, | |
3873 | we use the name of a table set up in mips.c, which is overwritten | |
3874 | if -mrnames is used. */ | |
3875 | ||
3876 | #define REGISTER_NAMES \ | |
3877 | { \ | |
3878 | &mips_reg_names[ 0][0], \ | |
3879 | &mips_reg_names[ 1][0], \ | |
3880 | &mips_reg_names[ 2][0], \ | |
3881 | &mips_reg_names[ 3][0], \ | |
3882 | &mips_reg_names[ 4][0], \ | |
3883 | &mips_reg_names[ 5][0], \ | |
3884 | &mips_reg_names[ 6][0], \ | |
3885 | &mips_reg_names[ 7][0], \ | |
3886 | &mips_reg_names[ 8][0], \ | |
3887 | &mips_reg_names[ 9][0], \ | |
3888 | &mips_reg_names[10][0], \ | |
3889 | &mips_reg_names[11][0], \ | |
3890 | &mips_reg_names[12][0], \ | |
3891 | &mips_reg_names[13][0], \ | |
3892 | &mips_reg_names[14][0], \ | |
3893 | &mips_reg_names[15][0], \ | |
3894 | &mips_reg_names[16][0], \ | |
3895 | &mips_reg_names[17][0], \ | |
3896 | &mips_reg_names[18][0], \ | |
3897 | &mips_reg_names[19][0], \ | |
3898 | &mips_reg_names[20][0], \ | |
3899 | &mips_reg_names[21][0], \ | |
3900 | &mips_reg_names[22][0], \ | |
3901 | &mips_reg_names[23][0], \ | |
3902 | &mips_reg_names[24][0], \ | |
3903 | &mips_reg_names[25][0], \ | |
3904 | &mips_reg_names[26][0], \ | |
3905 | &mips_reg_names[27][0], \ | |
3906 | &mips_reg_names[28][0], \ | |
3907 | &mips_reg_names[29][0], \ | |
3908 | &mips_reg_names[30][0], \ | |
3909 | &mips_reg_names[31][0], \ | |
3910 | &mips_reg_names[32][0], \ | |
3911 | &mips_reg_names[33][0], \ | |
3912 | &mips_reg_names[34][0], \ | |
3913 | &mips_reg_names[35][0], \ | |
3914 | &mips_reg_names[36][0], \ | |
3915 | &mips_reg_names[37][0], \ | |
3916 | &mips_reg_names[38][0], \ | |
3917 | &mips_reg_names[39][0], \ | |
3918 | &mips_reg_names[40][0], \ | |
3919 | &mips_reg_names[41][0], \ | |
3920 | &mips_reg_names[42][0], \ | |
3921 | &mips_reg_names[43][0], \ | |
3922 | &mips_reg_names[44][0], \ | |
3923 | &mips_reg_names[45][0], \ | |
3924 | &mips_reg_names[46][0], \ | |
3925 | &mips_reg_names[47][0], \ | |
3926 | &mips_reg_names[48][0], \ | |
3927 | &mips_reg_names[49][0], \ | |
3928 | &mips_reg_names[50][0], \ | |
3929 | &mips_reg_names[51][0], \ | |
3930 | &mips_reg_names[52][0], \ | |
3931 | &mips_reg_names[53][0], \ | |
3932 | &mips_reg_names[54][0], \ | |
3933 | &mips_reg_names[55][0], \ | |
3934 | &mips_reg_names[56][0], \ | |
3935 | &mips_reg_names[57][0], \ | |
3936 | &mips_reg_names[58][0], \ | |
3937 | &mips_reg_names[59][0], \ | |
3938 | &mips_reg_names[60][0], \ | |
3939 | &mips_reg_names[61][0], \ | |
3940 | &mips_reg_names[62][0], \ | |
3941 | &mips_reg_names[63][0], \ | |
3942 | &mips_reg_names[64][0], \ | |
3943 | &mips_reg_names[65][0], \ | |
3944 | &mips_reg_names[66][0], \ | |
225b8835 | 3945 | &mips_reg_names[67][0], \ |
39dffea3 | 3946 | &mips_reg_names[68][0], \ |
b8eb88d0 ILT |
3947 | &mips_reg_names[69][0], \ |
3948 | &mips_reg_names[70][0], \ | |
3949 | &mips_reg_names[71][0], \ | |
3950 | &mips_reg_names[72][0], \ | |
3951 | &mips_reg_names[73][0], \ | |
3952 | &mips_reg_names[74][0], \ | |
3953 | &mips_reg_names[75][0], \ | |
d604bca3 MH |
3954 | &mips_reg_names[76][0], \ |
3955 | &mips_reg_names[77][0], \ | |
3956 | &mips_reg_names[78][0], \ | |
3957 | &mips_reg_names[79][0], \ | |
3958 | &mips_reg_names[80][0], \ | |
3959 | &mips_reg_names[81][0], \ | |
3960 | &mips_reg_names[82][0], \ | |
3961 | &mips_reg_names[83][0], \ | |
3962 | &mips_reg_names[84][0], \ | |
3963 | &mips_reg_names[85][0], \ | |
3964 | &mips_reg_names[86][0], \ | |
3965 | &mips_reg_names[87][0], \ | |
3966 | &mips_reg_names[88][0], \ | |
3967 | &mips_reg_names[89][0], \ | |
3968 | &mips_reg_names[90][0], \ | |
3969 | &mips_reg_names[91][0], \ | |
3970 | &mips_reg_names[92][0], \ | |
3971 | &mips_reg_names[93][0], \ | |
3972 | &mips_reg_names[94][0], \ | |
3973 | &mips_reg_names[95][0], \ | |
3974 | &mips_reg_names[96][0], \ | |
3975 | &mips_reg_names[97][0], \ | |
3976 | &mips_reg_names[98][0], \ | |
3977 | &mips_reg_names[99][0], \ | |
3978 | &mips_reg_names[100][0], \ | |
3979 | &mips_reg_names[101][0], \ | |
3980 | &mips_reg_names[102][0], \ | |
3981 | &mips_reg_names[103][0], \ | |
3982 | &mips_reg_names[104][0], \ | |
3983 | &mips_reg_names[105][0], \ | |
3984 | &mips_reg_names[106][0], \ | |
3985 | &mips_reg_names[107][0], \ | |
3986 | &mips_reg_names[108][0], \ | |
3987 | &mips_reg_names[109][0], \ | |
3988 | &mips_reg_names[110][0], \ | |
3989 | &mips_reg_names[111][0], \ | |
3990 | &mips_reg_names[112][0], \ | |
3991 | &mips_reg_names[113][0], \ | |
3992 | &mips_reg_names[114][0], \ | |
3993 | &mips_reg_names[115][0], \ | |
3994 | &mips_reg_names[116][0], \ | |
3995 | &mips_reg_names[117][0], \ | |
3996 | &mips_reg_names[118][0], \ | |
3997 | &mips_reg_names[119][0], \ | |
3998 | &mips_reg_names[120][0], \ | |
3999 | &mips_reg_names[121][0], \ | |
4000 | &mips_reg_names[122][0], \ | |
4001 | &mips_reg_names[123][0], \ | |
4002 | &mips_reg_names[124][0], \ | |
4003 | &mips_reg_names[125][0], \ | |
4004 | &mips_reg_names[126][0], \ | |
4005 | &mips_reg_names[127][0], \ | |
4006 | &mips_reg_names[128][0], \ | |
4007 | &mips_reg_names[129][0], \ | |
4008 | &mips_reg_names[130][0], \ | |
4009 | &mips_reg_names[131][0], \ | |
4010 | &mips_reg_names[132][0], \ | |
4011 | &mips_reg_names[133][0], \ | |
4012 | &mips_reg_names[134][0], \ | |
4013 | &mips_reg_names[135][0], \ | |
4014 | &mips_reg_names[136][0], \ | |
4015 | &mips_reg_names[137][0], \ | |
4016 | &mips_reg_names[138][0], \ | |
4017 | &mips_reg_names[139][0], \ | |
4018 | &mips_reg_names[140][0], \ | |
4019 | &mips_reg_names[141][0], \ | |
4020 | &mips_reg_names[142][0], \ | |
4021 | &mips_reg_names[143][0], \ | |
4022 | &mips_reg_names[144][0], \ | |
4023 | &mips_reg_names[145][0], \ | |
4024 | &mips_reg_names[146][0], \ | |
4025 | &mips_reg_names[147][0], \ | |
4026 | &mips_reg_names[148][0], \ | |
4027 | &mips_reg_names[149][0], \ | |
4028 | &mips_reg_names[150][0], \ | |
4029 | &mips_reg_names[151][0], \ | |
4030 | &mips_reg_names[152][0], \ | |
4031 | &mips_reg_names[153][0], \ | |
4032 | &mips_reg_names[154][0], \ | |
4033 | &mips_reg_names[155][0], \ | |
4034 | &mips_reg_names[156][0], \ | |
4035 | &mips_reg_names[157][0], \ | |
4036 | &mips_reg_names[158][0], \ | |
4037 | &mips_reg_names[159][0], \ | |
4038 | &mips_reg_names[160][0], \ | |
4039 | &mips_reg_names[161][0], \ | |
4040 | &mips_reg_names[162][0], \ | |
4041 | &mips_reg_names[163][0], \ | |
4042 | &mips_reg_names[164][0], \ | |
4043 | &mips_reg_names[165][0], \ | |
4044 | &mips_reg_names[166][0], \ | |
4045 | &mips_reg_names[167][0], \ | |
4046 | &mips_reg_names[168][0], \ | |
4047 | &mips_reg_names[169][0], \ | |
4048 | &mips_reg_names[170][0], \ | |
4049 | &mips_reg_names[171][0], \ | |
4050 | &mips_reg_names[172][0], \ | |
4051 | &mips_reg_names[173][0], \ | |
4052 | &mips_reg_names[174][0], \ | |
4053 | &mips_reg_names[175][0] \ | |
e75b25e7 MM |
4054 | } |
4055 | ||
46cca58c RS |
4056 | /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c. |
4057 | So define this for it. */ | |
4058 | #define DEBUG_REGISTER_NAMES \ | |
4059 | { \ | |
4060 | "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ | |
4061 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ | |
4062 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ | |
07e2e444 | 4063 | "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \ |
46cca58c RS |
4064 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ |
4065 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
4066 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ | |
4067 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ | |
b8eb88d0 | 4068 | "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ |
d604bca3 MH |
4069 | "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \ |
4070 | "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\ | |
4071 | "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\ | |
4072 | "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\ | |
4073 | "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\ | |
4074 | "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\ | |
4075 | "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\ | |
4076 | "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\ | |
4077 | "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\ | |
4078 | "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\ | |
4079 | "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\ | |
4080 | "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\ | |
4081 | "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\ | |
46cca58c RS |
4082 | } |
4083 | ||
e75b25e7 MM |
4084 | /* If defined, a C initializer for an array of structures |
4085 | containing a name and a register number. This macro defines | |
4086 | additional names for hard registers, thus allowing the `asm' | |
4087 | option in declarations to refer to registers using alternate | |
4088 | names. | |
4089 | ||
4090 | We define both names for the integer registers here. */ | |
4091 | ||
4092 | #define ADDITIONAL_REGISTER_NAMES \ | |
4093 | { \ | |
4094 | { "$0", 0 + GP_REG_FIRST }, \ | |
4095 | { "$1", 1 + GP_REG_FIRST }, \ | |
4096 | { "$2", 2 + GP_REG_FIRST }, \ | |
4097 | { "$3", 3 + GP_REG_FIRST }, \ | |
4098 | { "$4", 4 + GP_REG_FIRST }, \ | |
4099 | { "$5", 5 + GP_REG_FIRST }, \ | |
4100 | { "$6", 6 + GP_REG_FIRST }, \ | |
4101 | { "$7", 7 + GP_REG_FIRST }, \ | |
4102 | { "$8", 8 + GP_REG_FIRST }, \ | |
4103 | { "$9", 9 + GP_REG_FIRST }, \ | |
4104 | { "$10", 10 + GP_REG_FIRST }, \ | |
4105 | { "$11", 11 + GP_REG_FIRST }, \ | |
4106 | { "$12", 12 + GP_REG_FIRST }, \ | |
4107 | { "$13", 13 + GP_REG_FIRST }, \ | |
4108 | { "$14", 14 + GP_REG_FIRST }, \ | |
4109 | { "$15", 15 + GP_REG_FIRST }, \ | |
4110 | { "$16", 16 + GP_REG_FIRST }, \ | |
4111 | { "$17", 17 + GP_REG_FIRST }, \ | |
4112 | { "$18", 18 + GP_REG_FIRST }, \ | |
4113 | { "$19", 19 + GP_REG_FIRST }, \ | |
4114 | { "$20", 20 + GP_REG_FIRST }, \ | |
4115 | { "$21", 21 + GP_REG_FIRST }, \ | |
4116 | { "$22", 22 + GP_REG_FIRST }, \ | |
4117 | { "$23", 23 + GP_REG_FIRST }, \ | |
4118 | { "$24", 24 + GP_REG_FIRST }, \ | |
4119 | { "$25", 25 + GP_REG_FIRST }, \ | |
4120 | { "$26", 26 + GP_REG_FIRST }, \ | |
4121 | { "$27", 27 + GP_REG_FIRST }, \ | |
4122 | { "$28", 28 + GP_REG_FIRST }, \ | |
4123 | { "$29", 29 + GP_REG_FIRST }, \ | |
4124 | { "$30", 30 + GP_REG_FIRST }, \ | |
4125 | { "$31", 31 + GP_REG_FIRST }, \ | |
4126 | { "$sp", 29 + GP_REG_FIRST }, \ | |
4127 | { "$fp", 30 + GP_REG_FIRST }, \ | |
4128 | { "at", 1 + GP_REG_FIRST }, \ | |
4129 | { "v0", 2 + GP_REG_FIRST }, \ | |
4130 | { "v1", 3 + GP_REG_FIRST }, \ | |
4131 | { "a0", 4 + GP_REG_FIRST }, \ | |
4132 | { "a1", 5 + GP_REG_FIRST }, \ | |
4133 | { "a2", 6 + GP_REG_FIRST }, \ | |
4134 | { "a3", 7 + GP_REG_FIRST }, \ | |
4135 | { "t0", 8 + GP_REG_FIRST }, \ | |
4136 | { "t1", 9 + GP_REG_FIRST }, \ | |
4137 | { "t2", 10 + GP_REG_FIRST }, \ | |
4138 | { "t3", 11 + GP_REG_FIRST }, \ | |
4139 | { "t4", 12 + GP_REG_FIRST }, \ | |
4140 | { "t5", 13 + GP_REG_FIRST }, \ | |
4141 | { "t6", 14 + GP_REG_FIRST }, \ | |
4142 | { "t7", 15 + GP_REG_FIRST }, \ | |
4143 | { "s0", 16 + GP_REG_FIRST }, \ | |
4144 | { "s1", 17 + GP_REG_FIRST }, \ | |
4145 | { "s2", 18 + GP_REG_FIRST }, \ | |
4146 | { "s3", 19 + GP_REG_FIRST }, \ | |
4147 | { "s4", 20 + GP_REG_FIRST }, \ | |
4148 | { "s5", 21 + GP_REG_FIRST }, \ | |
4149 | { "s6", 22 + GP_REG_FIRST }, \ | |
4150 | { "s7", 23 + GP_REG_FIRST }, \ | |
4151 | { "t8", 24 + GP_REG_FIRST }, \ | |
4152 | { "t9", 25 + GP_REG_FIRST }, \ | |
4153 | { "k0", 26 + GP_REG_FIRST }, \ | |
4154 | { "k1", 27 + GP_REG_FIRST }, \ | |
4155 | { "gp", 28 + GP_REG_FIRST }, \ | |
4156 | { "sp", 29 + GP_REG_FIRST }, \ | |
4157 | { "fp", 30 + GP_REG_FIRST }, \ | |
4158 | { "ra", 31 + GP_REG_FIRST }, \ | |
924706a0 | 4159 | { "$sp", 29 + GP_REG_FIRST }, \ |
b8eb88d0 | 4160 | { "$fp", 30 + GP_REG_FIRST } \ |
d604bca3 | 4161 | ALL_COP_ADDITIONAL_REGISTER_NAMES \ |
e75b25e7 MM |
4162 | } |
4163 | ||
d604bca3 MH |
4164 | /* This is meant to be redefined in the host dependent files. It is a |
4165 | set of alternative names and regnums for mips coprocessors. */ | |
4166 | ||
4167 | #define ALL_COP_ADDITIONAL_REGISTER_NAMES | |
4168 | ||
e75b25e7 MM |
4169 | /* A C compound statement to output to stdio stream STREAM the |
4170 | assembler syntax for an instruction operand X. X is an RTL | |
4171 | expression. | |
4172 | ||
4173 | CODE is a value that can be used to specify one of several ways | |
4174 | of printing the operand. It is used when identical operands | |
4175 | must be printed differently depending on the context. CODE | |
4176 | comes from the `%' specification that was used to request | |
4177 | printing of the operand. If the specification was just `%DIGIT' | |
4178 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
4179 | is the ASCII code for LTR. | |
4180 | ||
4181 | If X is a register, this macro should print the register's name. | |
4182 | The names can be found in an array `reg_names' whose type is | |
4183 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
4184 | ||
4185 | When the machine description has a specification `%PUNCT' (a `%' | |
4186 | followed by a punctuation character), this macro is called with | |
4187 | a null pointer for X and the punctuation character for CODE. | |
4188 | ||
4189 | See mips.c for the MIPS specific codes. */ | |
4190 | ||
4191 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
4192 | ||
4193 | /* A C expression which evaluates to true if CODE is a valid | |
4194 | punctuation character for use in the `PRINT_OPERAND' macro. If | |
4195 | `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no | |
4196 | punctuation characters (except for the standard one, `%') are | |
4197 | used in this way. */ | |
4198 | ||
4199 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE] | |
4200 | ||
4201 | /* A C compound statement to output to stdio stream STREAM the | |
4202 | assembler syntax for an instruction operand that is a memory | |
fb49053f | 4203 | reference whose address is ADDR. ADDR is an RTL expression. */ |
e75b25e7 MM |
4204 | |
4205 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
4206 | ||
4207 | ||
4208 | /* A C statement, to be executed after all slot-filler instructions | |
4209 | have been output. If necessary, call `dbr_sequence_length' to | |
4210 | determine the number of slots filled in a sequence (zero if not | |
4211 | currently outputting a sequence), to decide how many no-ops to | |
4212 | output, or whatever. | |
4213 | ||
4214 | Don't define this macro if it has nothing to do, but it is | |
4215 | helpful in reading assembly output if the extent of the delay | |
4216 | sequence is made explicit (e.g. with white space). | |
4217 | ||
4218 | Note that output routines for instructions with delay slots must | |
4219 | be prepared to deal with not being output as part of a sequence | |
4220 | (i.e. when the scheduling pass is not run, or when no slot | |
4221 | fillers could be found.) The variable `final_sequence' is null | |
4222 | when not processing a sequence, otherwise it contains the | |
4223 | `sequence' rtx being output. */ | |
4224 | ||
4225 | #define DBR_OUTPUT_SEQEND(STREAM) \ | |
4226 | do \ | |
4227 | { \ | |
4228 | if (set_nomacro > 0 && --set_nomacro == 0) \ | |
4229 | fputs ("\t.set\tmacro\n", STREAM); \ | |
4230 | \ | |
4231 | if (set_noreorder > 0 && --set_noreorder == 0) \ | |
4232 | fputs ("\t.set\treorder\n", STREAM); \ | |
4233 | \ | |
4234 | dslots_jump_filled++; \ | |
4235 | fputs ("\n", STREAM); \ | |
4236 | } \ | |
4237 | while (0) | |
4238 | ||
4239 | ||
4240 | /* How to tell the debugger about changes of source files. Note, the | |
4241 | mips ECOFF format cannot deal with changes of files inside of | |
4242 | functions, which means the output of parser generators like bison | |
4243 | is generally not debuggable without using the -l switch. Lose, | |
4244 | lose, lose. Silicon graphics seems to want all .file's hardwired | |
4245 | to 1. */ | |
4246 | ||
4247 | #ifndef SET_FILE_NUMBER | |
4248 | #define SET_FILE_NUMBER() ++num_source_filenames | |
4249 | #endif | |
4250 | ||
4251 | #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ | |
4252 | mips_output_filename (STREAM, NAME) | |
4253 | ||
ddd5a7c1 | 4254 | /* This is defined so that it can be overridden in iris6.h. */ |
516a2dfd JW |
4255 | #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \ |
4256 | do \ | |
4257 | { \ | |
4258 | fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \ | |
4259 | output_quoted_string (STREAM, NAME); \ | |
4260 | fputs ("\n", STREAM); \ | |
4261 | } \ | |
4262 | while (0) | |
4263 | ||
e75b25e7 MM |
4264 | /* This is how to output a note the debugger telling it the line number |
4265 | to which the following sequence of instructions corresponds. | |
4266 | Silicon graphics puts a label after each .loc. */ | |
4267 | ||
4268 | #ifndef LABEL_AFTER_LOC | |
4269 | #define LABEL_AFTER_LOC(STREAM) | |
4270 | #endif | |
4271 | ||
b2bcb32d | 4272 | #ifndef ASM_OUTPUT_SOURCE_LINE |
e75b25e7 MM |
4273 | #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \ |
4274 | mips_output_lineno (STREAM, LINE) | |
b2bcb32d | 4275 | #endif |
e75b25e7 | 4276 | |
9ec36da5 | 4277 | /* The MIPS implementation uses some labels for its own purpose. The |
e75b25e7 MM |
4278 | following lists what labels are created, and are all formed by the |
4279 | pattern $L[a-z].*. The machine independent portion of GCC creates | |
4280 | labels matching: $L[A-Z][0-9]+ and $L[0-9]+. | |
4281 | ||
c5b7917e | 4282 | LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. |
e75b25e7 MM |
4283 | $Lb[0-9]+ Begin blocks for MIPS debug support |
4284 | $Lc[0-9]+ Label for use in s<xx> operation. | |
4285 | $Le[0-9]+ End blocks for MIPS debug support | |
987ba558 | 4286 | $Lp\..+ Half-pic labels. */ |
e75b25e7 MM |
4287 | |
4288 | /* This is how to output the definition of a user-level label named NAME, | |
4289 | such as the label on a static function or variable NAME. | |
4290 | ||
4291 | If we are optimizing the gp, remember that this label has been put | |
4292 | out, so we know not to emit an .extern for it in mips_asm_file_end. | |
4293 | We use one of the common bits in the IDENTIFIER tree node for this, | |
4294 | since those bits seem to be unused, and we don't have any method | |
4295 | of getting the decl nodes from the name. */ | |
4296 | ||
e75b25e7 MM |
4297 | #define ASM_OUTPUT_LABEL(STREAM,NAME) \ |
4298 | do { \ | |
4299 | assemble_name (STREAM, NAME); \ | |
4300 | fputs (":\n", STREAM); \ | |
e75b25e7 MM |
4301 | } while (0) |
4302 | ||
31c714e3 MM |
4303 | |
4304 | /* A C statement (sans semicolon) to output to the stdio stream | |
4305 | STREAM any text necessary for declaring the name NAME of an | |
4306 | initialized variable which is being defined. This macro must | |
7dac2f89 | 4307 | output the label definition (perhaps using `ASM_OUTPUT_LABEL'). |
31c714e3 MM |
4308 | The argument DECL is the `VAR_DECL' tree node representing the |
4309 | variable. | |
4310 | ||
4311 | If this macro is not defined, then the variable name is defined | |
4312 | in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */ | |
4313 | ||
44404b8b | 4314 | #undef ASM_DECLARE_OBJECT_NAME |
31c714e3 | 4315 | #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ |
f3b39eba MM |
4316 | do \ |
4317 | { \ | |
4318 | mips_declare_object (STREAM, NAME, "", ":\n", 0); \ | |
4319 | HALF_PIC_DECLARE (NAME); \ | |
4320 | } \ | |
4321 | while (0) | |
31c714e3 | 4322 | |
e75b25e7 MM |
4323 | |
4324 | /* This is how to output a command to make the user-level label named NAME | |
4325 | defined for reference from other files. */ | |
4326 | ||
e75b25e7 MM |
4327 | #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ |
4328 | do { \ | |
4329 | fputs ("\t.globl\t", STREAM); \ | |
4330 | assemble_name (STREAM, NAME); \ | |
4331 | fputs ("\n", STREAM); \ | |
4332 | } while (0) | |
4333 | ||
31c714e3 | 4334 | /* This says how to define a global common symbol. */ |
e75b25e7 | 4335 | |
919509ce DN |
4336 | #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \ |
4337 | do { \ | |
4338 | /* If the target wants uninitialized const declarations in \ | |
4339 | .rdata then don't put them in .comm */ \ | |
4340 | if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \ | |
4341 | && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \ | |
4342 | && (DECL_INITIAL (DECL) == 0 \ | |
4343 | || DECL_INITIAL (DECL) == error_mark_node)) \ | |
4344 | { \ | |
4345 | if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \ | |
4346 | ASM_GLOBALIZE_LABEL (STREAM, NAME); \ | |
4347 | \ | |
d48bc59a | 4348 | readonly_data_section (); \ |
919509ce DN |
4349 | ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \ |
4350 | mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \ | |
4351 | (SIZE)); \ | |
4352 | } \ | |
4353 | else \ | |
d239cdc0 | 4354 | mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \ |
919509ce DN |
4355 | (SIZE)); \ |
4356 | } while (0) | |
4357 | ||
e75b25e7 | 4358 | |
c5b7917e | 4359 | /* This says how to define a local common symbol (ie, not visible to |
31c714e3 | 4360 | linker). */ |
e75b25e7 MM |
4361 | |
4362 | #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \ | |
69520b54 | 4363 | mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE)) |
e75b25e7 MM |
4364 | |
4365 | ||
4366 | /* This says how to output an external. It would be possible not to | |
4367 | output anything and let undefined symbol become external. However | |
4368 | the assembler uses length information on externals to allocate in | |
4369 | data/sdata bss/sbss, thereby saving exec time. */ | |
4370 | ||
4371 | #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ | |
4372 | mips_output_external(STREAM,DECL,NAME) | |
4373 | ||
4374 | /* This says what to print at the end of the assembly file */ | |
44404b8b | 4375 | #undef ASM_FILE_END |
e75b25e7 MM |
4376 | #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM) |
4377 | ||
4378 | ||
f99ffb60 RH |
4379 | /* Play switch file games if we're optimizing the global pointer. */ |
4380 | ||
4381 | #undef TEXT_SECTION | |
4382 | #define TEXT_SECTION() \ | |
4383 | do { \ | |
4384 | extern FILE *asm_out_text_file; \ | |
4385 | if (TARGET_FILE_SWITCHING) \ | |
4386 | asm_out_file = asm_out_text_file; \ | |
4387 | fputs (TEXT_SECTION_ASM_OP, asm_out_file); \ | |
4388 | fputc ('\n', asm_out_file); \ | |
4389 | } while (0) | |
4390 | ||
4391 | ||
e75b25e7 MM |
4392 | /* This is how to declare a function name. The actual work of |
4393 | emitting the label is moved to function_prologue, so that we can | |
4394 | get the line number correctly emitted before the .ent directive, | |
f99ffb60 | 4395 | and after any .file directives. */ |
e75b25e7 | 4396 | |
44404b8b | 4397 | #undef ASM_DECLARE_FUNCTION_NAME |
f99ffb60 RH |
4398 | #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ |
4399 | HALF_PIC_DECLARE (NAME) | |
e75b25e7 | 4400 | |
e75b25e7 MM |
4401 | /* This is how to output an internal numbered label where |
4402 | PREFIX is the class of label and NUM is the number within the class. */ | |
4403 | ||
44404b8b | 4404 | #undef ASM_OUTPUT_INTERNAL_LABEL |
e75b25e7 | 4405 | #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \ |
6ae1498b | 4406 | fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) |
e75b25e7 MM |
4407 | |
4408 | /* This is how to store into the string LABEL | |
4409 | the symbol_ref name of an internal numbered label where | |
4410 | PREFIX is the class of label and NUM is the number within the class. | |
4411 | This is suitable for output with `assemble_name'. */ | |
4412 | ||
44404b8b | 4413 | #undef ASM_GENERATE_INTERNAL_LABEL |
e75b25e7 | 4414 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ |
4f70758f | 4415 | sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) |
e75b25e7 | 4416 | |
e75b25e7 MM |
4417 | /* This is how to output an element of a case-vector that is absolute. */ |
4418 | ||
4419 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
6ae1498b | 4420 | fprintf (STREAM, "\t%s\t%sL%d\n", \ |
1eeed24e | 4421 | Pmode == DImode ? ".dword" : ".word", \ |
6ae1498b | 4422 | LOCAL_LABEL_PREFIX, \ |
876c09d3 | 4423 | VALUE) |
e75b25e7 MM |
4424 | |
4425 | /* This is how to output an element of a case-vector that is relative. | |
e0bfcea5 ILT |
4426 | This is used for pc-relative code (e.g. when TARGET_ABICALLS or |
4427 | TARGET_EMBEDDED_PIC). */ | |
e75b25e7 | 4428 | |
33f7f353 | 4429 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ |
e0bfcea5 | 4430 | do { \ |
2bcb2ab3 GK |
4431 | if (TARGET_MIPS16) \ |
4432 | fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ | |
4433 | LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ | |
4434 | else if (TARGET_EMBEDDED_PIC) \ | |
6ae1498b | 4435 | fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \ |
1eeed24e | 4436 | Pmode == DImode ? ".dword" : ".word", \ |
6ae1498b | 4437 | LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ |
a53f72db | 4438 | else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \ |
6ae1498b | 4439 | fprintf (STREAM, "\t%s\t%sL%d\n", \ |
1eeed24e | 4440 | Pmode == DImode ? ".gpdword" : ".gpword", \ |
6ae1498b | 4441 | LOCAL_LABEL_PREFIX, VALUE); \ |
516a2dfd | 4442 | else \ |
b2d8cf33 | 4443 | fprintf (STREAM, "\t%s\t%sL%d\n", \ |
1eeed24e | 4444 | Pmode == DImode ? ".dword" : ".word", \ |
b2d8cf33 | 4445 | LOCAL_LABEL_PREFIX, VALUE); \ |
e0bfcea5 ILT |
4446 | } while (0) |
4447 | ||
2bcb2ab3 GK |
4448 | /* When generating embedded PIC or mips16 code we want to put the jump |
4449 | table in the .text section. In all other cases, we want to put the | |
4450 | jump table in the .rdata section. Unfortunately, we can't use | |
e0bfcea5 ILT |
4451 | JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional. |
4452 | Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text | |
4453 | section if appropriate. */ | |
44404b8b | 4454 | #undef ASM_OUTPUT_CASE_LABEL |
e0bfcea5 ILT |
4455 | #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \ |
4456 | do { \ | |
2bcb2ab3 GK |
4457 | if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \ |
4458 | function_section (current_function_decl); \ | |
e0bfcea5 ILT |
4459 | ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ |
4460 | } while (0) | |
e75b25e7 MM |
4461 | |
4462 | /* This is how to output an assembler line | |
4463 | that says to advance the location counter | |
4464 | to a multiple of 2**LOG bytes. */ | |
4465 | ||
4466 | #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ | |
a688e0b7 | 4467 | fprintf (STREAM, "\t.align\t%d\n", (LOG)) |
e75b25e7 | 4468 | |
38e01259 | 4469 | /* This is how to output an assembler line to advance the location |
e75b25e7 MM |
4470 | counter by SIZE bytes. */ |
4471 | ||
44404b8b | 4472 | #undef ASM_OUTPUT_SKIP |
e75b25e7 MM |
4473 | #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ |
4474 | fprintf (STREAM, "\t.space\t%u\n", (SIZE)) | |
4475 | ||
e75b25e7 | 4476 | /* This is how to output a string. */ |
44404b8b | 4477 | #undef ASM_OUTPUT_ASCII |
e75b25e7 | 4478 | #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \ |
b3276c7a | 4479 | mips_output_ascii (STREAM, STRING, LEN) |
e75b25e7 MM |
4480 | |
4481 | /* Handle certain cpp directives used in header files on sysV. */ | |
4482 | #define SCCS_DIRECTIVE | |
4483 | ||
4484 | /* Output #ident as a in the read-only data section. */ | |
0e5a4ad8 | 4485 | #undef ASM_OUTPUT_IDENT |
e75b25e7 MM |
4486 | #define ASM_OUTPUT_IDENT(FILE, STRING) \ |
4487 | { \ | |
3cce094d | 4488 | const char *p = STRING; \ |
e75b25e7 | 4489 | int size = strlen (p) + 1; \ |
d48bc59a | 4490 | readonly_data_section (); \ |
e75b25e7 MM |
4491 | assemble_string (p, size); \ |
4492 | } | |
4493 | \f | |
b82b0773 MM |
4494 | /* Default to -G 8 */ |
4495 | #ifndef MIPS_DEFAULT_GVALUE | |
4496 | #define MIPS_DEFAULT_GVALUE 8 | |
4497 | #endif | |
e75b25e7 | 4498 | |
f3b39eba MM |
4499 | /* Define the strings to put out for each section in the object file. */ |
4500 | #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ | |
4501 | #define DATA_SECTION_ASM_OP "\t.data" /* large data */ | |
4502 | #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */ | |
50efa737 | 4503 | #ifndef READONLY_DATA_SECTION_ASM_OP |
d48bc59a | 4504 | #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ |
50efa737 | 4505 | #endif |
3cf6400d | 4506 | #define SMALL_DATA_SECTION sdata_section |
e75b25e7 MM |
4507 | |
4508 | /* What other sections we support other than the normal .data/.text. */ | |
4509 | ||
44404b8b | 4510 | #undef EXTRA_SECTIONS |
d48bc59a | 4511 | #define EXTRA_SECTIONS in_sdata |
e75b25e7 MM |
4512 | |
4513 | /* Define the additional functions to select our additional sections. */ | |
4514 | ||
4515 | /* on the MIPS it is not a good idea to put constants in the text | |
4516 | section, since this defeats the sdata/data mechanism. This is | |
4517 | especially true when -O is used. In this case an effort is made to | |
4518 | address with faster (gp) register relative addressing, which can | |
4519 | only get at sdata and sbss items (there is no stext !!) However, | |
4520 | if the constant is too large for sdata, and it's readonly, it | |
987ba558 | 4521 | will go into the .rdata section. */ |
e75b25e7 | 4522 | |
44404b8b | 4523 | #undef EXTRA_SECTION_FUNCTIONS |
e75b25e7 MM |
4524 | #define EXTRA_SECTION_FUNCTIONS \ |
4525 | void \ | |
4526 | sdata_section () \ | |
4527 | { \ | |
4528 | if (in_section != in_sdata) \ | |
4529 | { \ | |
4530 | fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \ | |
4531 | in_section = in_sdata; \ | |
4532 | } \ | |
e75b25e7 MM |
4533 | } |
4534 | ||
4535 | /* Given a decl node or constant node, choose the section to output it in | |
4536 | and select that section. */ | |
4537 | ||
ae46c4e0 RH |
4538 | #undef TARGET_ASM_SELECT_SECTION |
4539 | #define TARGET_ASM_SELECT_SECTION mips_select_section | |
e75b25e7 MM |
4540 | \f |
4541 | /* Store in OUTPUT a string (made with alloca) containing | |
4542 | an assembler-name for a local static variable named NAME. | |
4543 | LABELNO is an integer which is different for each call. */ | |
4544 | ||
4545 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
4546 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
4547 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
4548 | ||
4549 | #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ | |
4550 | do \ | |
4551 | { \ | |
876c09d3 JW |
4552 | fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \ |
4553 | TARGET_64BIT ? "dsubu" : "subu", \ | |
e75b25e7 MM |
4554 | reg_names[STACK_POINTER_REGNUM], \ |
4555 | reg_names[STACK_POINTER_REGNUM], \ | |
876c09d3 | 4556 | TARGET_64BIT ? "sd" : "sw", \ |
e75b25e7 MM |
4557 | reg_names[REGNO], \ |
4558 | reg_names[STACK_POINTER_REGNUM]); \ | |
4559 | } \ | |
4560 | while (0) | |
4561 | ||
4562 | #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ | |
4563 | do \ | |
4564 | { \ | |
4565 | if (! set_noreorder) \ | |
4566 | fprintf (STREAM, "\t.set\tnoreorder\n"); \ | |
4567 | \ | |
4568 | dslots_load_total++; \ | |
4569 | dslots_load_filled++; \ | |
876c09d3 JW |
4570 | fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ |
4571 | TARGET_64BIT ? "ld" : "lw", \ | |
e75b25e7 MM |
4572 | reg_names[REGNO], \ |
4573 | reg_names[STACK_POINTER_REGNUM], \ | |
876c09d3 | 4574 | TARGET_64BIT ? "daddu" : "addu", \ |
e75b25e7 MM |
4575 | reg_names[STACK_POINTER_REGNUM], \ |
4576 | reg_names[STACK_POINTER_REGNUM]); \ | |
4577 | \ | |
4578 | if (! set_noreorder) \ | |
4579 | fprintf (STREAM, "\t.set\treorder\n"); \ | |
4580 | } \ | |
4581 | while (0) | |
4582 | ||
4baed42f DE |
4583 | /* How to start an assembler comment. |
4584 | The leading space is important (the mips native assembler requires it). */ | |
e75b25e7 | 4585 | #ifndef ASM_COMMENT_START |
4baed42f | 4586 | #define ASM_COMMENT_START " #" |
e75b25e7 | 4587 | #endif |
e75b25e7 MM |
4588 | \f |
4589 | ||
4590 | /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for | |
4591 | and mips-tdump.c to print them out. | |
4592 | ||
4593 | These must match the corresponding definitions in gdb/mipsread.c. | |
987ba558 | 4594 | Unfortunately, gcc and gdb do not currently share any directories. */ |
e75b25e7 MM |
4595 | |
4596 | #define CODE_MASK 0x8F300 | |
4597 | #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) | |
4598 | #define MIPS_MARK_STAB(code) ((code)+CODE_MASK) | |
4599 | #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK) | |
3f1f8d8c MM |
4600 | |
4601 | \f | |
4602 | /* Default definitions for size_t and ptrdiff_t. */ | |
4603 | ||
4604 | #ifndef SIZE_TYPE | |
79e69af0 | 4605 | #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int") |
3f1f8d8c MM |
4606 | #endif |
4607 | ||
4608 | #ifndef PTRDIFF_TYPE | |
79e69af0 | 4609 | #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int") |
3f1f8d8c | 4610 | #endif |
28174a14 MS |
4611 | |
4612 | /* See mips_expand_prologue's use of loadgp for when this should be | |
4613 | true. */ | |
4614 | ||
a53f72db GRK |
4615 | #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \ |
4616 | && mips_abi != ABI_32 \ | |
4617 | && mips_abi != ABI_O64) | |
2bcb2ab3 GK |
4618 | \f |
4619 | /* In mips16 mode, we need to look through the function to check for | |
4620 | PC relative loads that are out of range. */ | |
4621 | #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X) | |
4622 | ||
4623 | /* We need to use a special set of functions to handle hard floating | |
4624 | point code in mips16 mode. */ | |
337e2b69 ILT |
4625 | |
4626 | #ifndef INIT_SUBTARGET_OPTABS | |
4627 | #define INIT_SUBTARGET_OPTABS | |
4628 | #endif | |
4629 | ||
4630 | #define INIT_TARGET_OPTABS \ | |
4631 | do \ | |
4632 | { \ | |
2bcb2ab3 GK |
4633 | if (! TARGET_MIPS16 || ! mips16_hard_float) \ |
4634 | INIT_SUBTARGET_OPTABS; \ | |
4635 | else \ | |
4636 | { \ | |
4637 | add_optab->handlers[(int) SFmode].libfunc = \ | |
e85cde9a | 4638 | init_one_libfunc ("__mips16_addsf3"); \ |
2bcb2ab3 | 4639 | sub_optab->handlers[(int) SFmode].libfunc = \ |
e85cde9a | 4640 | init_one_libfunc ("__mips16_subsf3"); \ |
2bcb2ab3 | 4641 | smul_optab->handlers[(int) SFmode].libfunc = \ |
e85cde9a | 4642 | init_one_libfunc ("__mips16_mulsf3"); \ |
ef89d648 | 4643 | sdiv_optab->handlers[(int) SFmode].libfunc = \ |
e85cde9a | 4644 | init_one_libfunc ("__mips16_divsf3"); \ |
2bcb2ab3 | 4645 | \ |
e85cde9a JL |
4646 | eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \ |
4647 | nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \ | |
4648 | gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \ | |
4649 | gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \ | |
4650 | ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \ | |
4651 | lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \ | |
2bcb2ab3 GK |
4652 | \ |
4653 | floatsisf_libfunc = \ | |
e85cde9a | 4654 | init_one_libfunc ("__mips16_floatsisf"); \ |
2bcb2ab3 | 4655 | fixsfsi_libfunc = \ |
e85cde9a | 4656 | init_one_libfunc ("__mips16_fixsfsi"); \ |
2bcb2ab3 GK |
4657 | \ |
4658 | if (TARGET_DOUBLE_FLOAT) \ | |
4659 | { \ | |
4660 | add_optab->handlers[(int) DFmode].libfunc = \ | |
e85cde9a | 4661 | init_one_libfunc ("__mips16_adddf3"); \ |
2bcb2ab3 | 4662 | sub_optab->handlers[(int) DFmode].libfunc = \ |
e85cde9a | 4663 | init_one_libfunc ("__mips16_subdf3"); \ |
2bcb2ab3 | 4664 | smul_optab->handlers[(int) DFmode].libfunc = \ |
e85cde9a | 4665 | init_one_libfunc ("__mips16_muldf3"); \ |
ef89d648 | 4666 | sdiv_optab->handlers[(int) DFmode].libfunc = \ |
e85cde9a | 4667 | init_one_libfunc ("__mips16_divdf3"); \ |
2bcb2ab3 GK |
4668 | \ |
4669 | extendsfdf2_libfunc = \ | |
e85cde9a | 4670 | init_one_libfunc ("__mips16_extendsfdf2"); \ |
2bcb2ab3 | 4671 | truncdfsf2_libfunc = \ |
e85cde9a | 4672 | init_one_libfunc ("__mips16_truncdfsf2"); \ |
2bcb2ab3 GK |
4673 | \ |
4674 | eqdf2_libfunc = \ | |
e85cde9a | 4675 | init_one_libfunc ("__mips16_eqdf2"); \ |
2bcb2ab3 | 4676 | nedf2_libfunc = \ |
e85cde9a | 4677 | init_one_libfunc ("__mips16_nedf2"); \ |
2bcb2ab3 | 4678 | gtdf2_libfunc = \ |
e85cde9a | 4679 | init_one_libfunc ("__mips16_gtdf2"); \ |
2bcb2ab3 | 4680 | gedf2_libfunc = \ |
e85cde9a | 4681 | init_one_libfunc ("__mips16_gedf2"); \ |
2bcb2ab3 | 4682 | ltdf2_libfunc = \ |
e85cde9a | 4683 | init_one_libfunc ("__mips16_ltdf2"); \ |
2bcb2ab3 | 4684 | ledf2_libfunc = \ |
e85cde9a | 4685 | init_one_libfunc ("__mips16_ledf2"); \ |
2bcb2ab3 GK |
4686 | \ |
4687 | floatsidf_libfunc = \ | |
e85cde9a | 4688 | init_one_libfunc ("__mips16_floatsidf"); \ |
2bcb2ab3 | 4689 | fixdfsi_libfunc = \ |
e85cde9a | 4690 | init_one_libfunc ("__mips16_fixdfsi"); \ |
2bcb2ab3 GK |
4691 | } \ |
4692 | } \ | |
337e2b69 ILT |
4693 | } \ |
4694 | while (0) | |
e0c13c70 L |
4695 | |
4696 | #define DFMODE_NAN \ | |
4697 | unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \ | |
4698 | unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7} | |
4699 | #define SFMODE_NAN \ | |
4700 | unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \ | |
4701 | unsigned short SFlittlenan[2] = {0xffff, 0xffbf} |