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mips.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Add additional information to .comm directive.
[gcc.git] / gcc / config / mips / mips.h
CommitLineData
e75b25e7 1/* Definitions of target machine for GNU compiler. MIPS version.
214be03f 2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
16c484c7 3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
ae3e1bb4
RK		 4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
e75b25e7
MM		 8
9This file is part of GNU CC.
10
11GNU CC is free software; you can redistribute it and/or modify
12it under the terms of the GNU General Public License as published by
13the Free Software Foundation; either version 2, or (at your option)
14any later version.
15
16GNU CC is distributed in the hope that it will be useful,
17but WITHOUT ANY WARRANTY; without even the implied warranty of
18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19GNU General Public License for more details.
20
21You should have received a copy of the GNU General Public License
22along with GNU CC; see the file COPYING. If not, write to
75fe0c5e
RK		 23the Free Software Foundation, 59 Temple Place - Suite 330,
24Boston, MA 02111-1307, USA. */
e75b25e7
MM		 25
26
e75b25e7
MM		 27/* Standard GCC variables that we reference. */
28
0fb5ac6f
MM		 29extern char *asm_file_name;
30extern char call_used_regs[];
0fb5ac6f 31extern int may_call_alloca;
0fb5ac6f
MM		 32extern char **save_argv;
33extern int target_flags;
e75b25e7
MM		 34
35/* MIPS external variables defined in mips.c. */
36
37/* comparison type */
38enum cmp_type {
876c09d3
JW		 39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
e75b25e7
MM		 41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
44};
45
46/* types of delay slot */
47enum delay_type {
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
34b650b3
MM		 50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
e75b25e7
MM		 52};
53
54/* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
4a392643
RS		 56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
e75b25e7
MM		 58
59enum processor_type {
60 PROCESSOR_DEFAULT,
61 PROCESSOR_R3000,
e9a25f70 62 PROCESSOR_R3900,
e75b25e7 63 PROCESSOR_R6000,
876c09d3 64 PROCESSOR_R4000,
00b3e052
JW		 65 PROCESSOR_R4100,
66 PROCESSOR_R4300,
516a2dfd 67 PROCESSOR_R4600,
053665d7 68 PROCESSOR_R4650,
b8eb88d0 69 PROCESSOR_R5000,
0e5a4ad8
EC		 70 PROCESSOR_R8000,
71 PROCESSOR_R4KC,
72 PROCESSOR_R5KC,
73 PROCESSOR_R20KC
e75b25e7
MM		 74};
75
4a392643 76/* Recast the cpu class to be the cpu attribute. */
919b1aec 77#define mips_cpu_attr ((enum attr_cpu)mips_tune)
4a392643 78
04bd620d 79/* Which ABI to use. These are constants because abi64.h must check their
a53f72db
GRK		 80 value at preprocessing time.
81
82 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
987ba558 83 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
b2d8cf33 84
04bd620d
JW		 85#define ABI_32 0
86#define ABI_N32 1
87#define ABI_64 2
88#define ABI_EABI 3
a53f72db 89#define ABI_O64 4
0e5a4ad8
EC		 90/* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
91 which is not the same as the above EABI (defined by Cygnus,
92 Greenhills, and Toshiba?). MEABI is not yet complete or published,
93 but at this point it looks like N32 as far as calling conventions go,
94 but allows for either 32 or 64 bit registers.
95
96 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
97 EABI the legacy EABI. In the end we may end up calling both ABI's
98 EABI but give them different version numbers, but for now I'm going
987ba558 99 with different names. */
0e5a4ad8
EC		 100#define ABI_MEABI 5
101
45ceb85d
RS		 102/* Whether to emit abicalls code sequences or not. */
103
104enum mips_abicalls_type {
105 MIPS_ABICALLS_NO,
106 MIPS_ABICALLS_YES
107};
108
109/* Recast the abicalls class to be the abicalls attribute. */
110#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
111
b7d3fabe
RS		 112/* Which type of block move to do (whether or not the last store is
113 split out so it can fill a branch delay slot). */
114
115enum block_move_type {
116 BLOCK_MOVE_NORMAL, /* generate complete block move */
117 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
118 BLOCK_MOVE_LAST /* generate just the last store */
119};
120
987ba558 121extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
f540a7d3 122extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
e2fe6aba 123extern const char *current_function_file; /* filename current function is in */
e75b25e7
MM		 124extern int num_source_filenames; /* current .file # */
125extern int inside_function; /* != 0 if inside of a function */
126extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
127extern int file_in_function_warning; /* warning given about .file in func */
128extern int sdb_label_count; /* block start/end next label # */
a642a781 129extern int sdb_begin_function_line; /* Starting Line of current function */
e75b25e7
MM		 130extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
131extern int g_switch_value; /* value of the -G xx switch */
132extern int g_switch_set; /* whether -G xx was passed. */
133extern int sym_lineno; /* sgi next label # for each stmt */
134extern int set_noreorder; /* # of nested .set noreorder's */
135extern int set_nomacro; /* # of nested .set nomacro's */
136extern int set_noat; /* # of nested .set noat's */
137extern int set_volatile; /* # of nested .set volatile's */
e75b25e7
MM		 138extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
139extern int mips_dbx_regno[]; /* Map register # to debug register # */
e75b25e7
MM		 140extern struct rtx_def *branch_cmp[2]; /* operands for compare */
141extern enum cmp_type branch_type; /* what type of branch to use */
7dac2f89
EC		 142extern enum processor_type mips_arch; /* which cpu to codegen for */
143extern enum processor_type mips_tune; /* which cpu to schedule for */
45ceb85d 144extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
e75b25e7 145extern int mips_isa; /* architectural level */
2bcb2ab3
GK		 146extern int mips16; /* whether generating mips16 code */
147extern int mips16_hard_float; /* mips16 without -msoft-float */
148extern int mips_entry; /* generate entry/exit for mips16 */
e2fe6aba 149extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
7dac2f89
EC		 150extern const char *mips_arch_string; /* for -march=<xxx> */
151extern const char *mips_tune_string; /* for -mtune=<xxx> */
e2fe6aba
KG		 152extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
153extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
154extern const char *mips_entry_string; /* for -mentry */
155extern const char *mips_no_mips16_string;/* for -mno-mips16 */
3ce1ba83 156extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
d490e8ad 157extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
ce57d6f4 158extern int mips_split_addresses; /* perform high/lo_sum support */
e75b25e7
MM		 159extern int dslots_load_total; /* total # load related delay slots */
160extern int dslots_load_filled; /* # filled load delay slots */
161extern int dslots_jump_total; /* total # jump related delay slots */
162extern int dslots_jump_filled; /* # filled jump delay slots */
163extern int dslots_number_nops; /* # of nops needed by previous insn */
164extern int num_refs[3]; /* # 1/2/3 word references */
165extern struct rtx_def *mips_load_reg; /* register to check for load delay */
166extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
167extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
168extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
2bcb2ab3 169extern int mips_string_length; /* length of strings for mips16 */
e75b25e7 170
0fb5ac6f 171/* Functions to change what output section we are using. */
bd9f1972
KG		 172extern void rdata_section PARAMS ((void));
173extern void sdata_section PARAMS ((void));
cc8f5ec0 174extern void sbss_section PARAMS ((void));
e75b25e7 175
31c714e3
MM		 176/* Stubs for half-pic support if not OSF/1 reference platform. */
177
178#ifndef HALF_PIC_P
179#define HALF_PIC_P() 0
4a392643
RS		 180#define HALF_PIC_NUMBER_PTRS 0
181#define HALF_PIC_NUMBER_REFS 0
31c714e3 182#define HALF_PIC_ENCODE(DECL)
f3b39eba 183#define HALF_PIC_DECLARE(NAME)
c725bd79 184#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
31c714e3 185#define HALF_PIC_ADDRESS_P(X) 0
d26e29e1
MM		 186#define HALF_PIC_PTR(X) X
187#define HALF_PIC_FINISH(STREAM)
31c714e3
MM		 188#endif
189
3a6ee9f4
MM		 190/* Macros to silence warnings about numbers being signed in traditional
191 C and unsigned in ISO C when compiled on 32-bit hosts. */
192
193#define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
194#define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
195#define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
196
149e4e00
MM		 197\f
198/* Run-time compilation parameters selecting different hardware subsets. */
199
200/* Macros used in the machine description to test the flags. */
201
202 /* Bits for real switches */
6d81ba45
CD		 203#define MASK_INT64 0x00000001 /* ints are 64 bits */
204#define MASK_LONG64 0x00000002 /* longs are 64 bits */
205#define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
206#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
207#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
208#define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
209#define MASK_STATS 0x00000040 /* print statistics to stderr */
210#define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
211#define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
212#define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
213#define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
214#define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
215#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
216#define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
217#define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
365c6a0b 218#define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
6d81ba45
CD		 219#define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
220#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
221#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
222#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
7dac2f89 223#define MASK_MIPS16 0x00100000 /* Generate mips16 code */
6d81ba45 224#define MASK_NO_CHECK_ZERO_DIV \
7dac2f89 225 0x00200000 /* divide by zero checking */
6d81ba45 226#define MASK_CHECK_RANGE_DIV \
7dac2f89 227 0x00400000 /* divide result range checking */
6d81ba45 228#define MASK_UNINIT_CONST_IN_RODATA \
7dac2f89 229 0x00800000 /* Store uninitialized
6d81ba45 230 consts in rodata */
13fac94a
GK		 231#define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
232 multiply-add operations. */
149e4e00
MM		 233
234 /* Debug switches, not documented */
6d81ba45
CD		 235#define MASK_DEBUG 0 /* unused */
236#define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
237#define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
987ba558 238#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
08c2951c 239#define MASK_DEBUG_D 0 /* don't do define_split's */
e4f5c5d6 240#define MASK_DEBUG_E 0 /* function_arg debug */
6d81ba45 241#define MASK_DEBUG_F 0 /* ??? */
2bcb2ab3 242#define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
6d1350cd 243#define MASK_DEBUG_H 0 /* allow ints in FP registers */
e4f5c5d6 244#define MASK_DEBUG_I 0 /* unused */
149e4e00 245
6d81ba45
CD		 246 /* Dummy switches used only in specs */
247#define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
248
149e4e00
MM		 249 /* r4000 64 bit sizes */
250#define TARGET_INT64 (target_flags & MASK_INT64)
251#define TARGET_LONG64 (target_flags & MASK_LONG64)
149e4e00 252#define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
876c09d3 253#define TARGET_64BIT (target_flags & MASK_64BIT)
149e4e00 254
5ef37cd3
JW		 255 /* Mips vs. GNU linker */
256#define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
257
149e4e00
MM		 258 /* Mips vs. GNU assembler */
259#define TARGET_GAS (target_flags & MASK_GAS)
6d81ba45 260#define TARGET_MIPS_AS (!TARGET_GAS)
149e4e00 261
6d81ba45 262 /* Debug Modes */
149e4e00
MM		 263#define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
264#define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
265#define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
266#define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
267#define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
268#define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
269#define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
270#define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
271#define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
272#define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
149e4e00
MM		 273
274 /* Reg. Naming in .s ($21 vs. $a0) */
275#define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
276
277 /* Optimize for Sdata/Sbss */
278#define TARGET_GP_OPT (target_flags & MASK_GPOPT)
279
280 /* print program statistics */
281#define TARGET_STATS (target_flags & MASK_STATS)
282
283 /* call memcpy instead of inline code */
284#define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
285
286 /* .abicalls, etc from Pyramid V.4 */
287#define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
288
289 /* OSF pic references to externs */
290#define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
291
292 /* software floating point */
293#define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
294#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
295
296 /* always call through a register */
297#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
298
e0bfcea5
ILT		 299 /* generate embedded PIC code;
300 requires gas. */
301#define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
302
365c6a0b
JW		 303 /* for embedded systems, optimize for
304 reduced RAM space instead of for
305 fastest code. */
306#define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
307
919509ce
DN		 308 /* always store uninitialized const
309 variables in rodata, requires
987ba558 310 TARGET_EMBEDDED_DATA. */
919509ce
DN		 311#define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
312
96abdcb1
ILT		 313 /* generate big endian code. */
314#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
315
46299de9
ILT		 316#define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
317#define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
318
319#define TARGET_MAD (target_flags & MASK_MAD)
320
13fac94a
GK		 321#define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
322
00b3e052
JW		 323#define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
324
08c2951c
SC		 325#define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
326#define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
327
33b5e50b
JW		 328/* This is true if we must enable the assembly language file switching
329 code. */
330
f99ffb60
RH		 331#define TARGET_FILE_SWITCHING \
332 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
33b5e50b
JW		 333
334/* We must disable the function end stabs when doing the file switching trick,
335 because the Lscope stabs end up in the wrong place, making it impossible
336 to debug the resulting code. */
337#define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
338
2bcb2ab3
GK		 339 /* Generate mips16 code */
340#define TARGET_MIPS16 (target_flags & MASK_MIPS16)
341
7dac2f89
EC		 342/* Architecture target defines. */
343#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
344#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
345#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
346#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
0e5a4ad8
EC		 347#define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
348#define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
7dac2f89
EC		 349
350/* Scheduling target defines. */
7a38df19
EC		 351#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
352#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
353#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
354#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
355#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
7dac2f89 356
149e4e00
MM		 357/* Macro to define tables used to set the flags.
358 This is a list in braces of pairs in braces,
359 each pair being { "NAME", VALUE }
360 where VALUE is the bits to set or minus the bits to clear.
361 An empty string NAME is used to identify the default VALUE. */
362
363#define TARGET_SWITCHES \
364{ \
c45fd7f9 365 {"no-crt0", 0, \
047142d3 366 N_("No default crt0.o") }, \
a127db75 367 {"int64", MASK_INT64 | MASK_LONG64, \
047142d3 368 N_("Use 64-bit int type")}, \
a127db75 369 {"long64", MASK_LONG64, \
047142d3 370 N_("Use 64-bit long type")}, \
a127db75 371 {"long32", -(MASK_LONG64 | MASK_INT64), \
047142d3 372 N_("Use 32-bit long type")}, \
a127db75 373 {"split-addresses", MASK_SPLIT_ADDR, \
047142d3 374 N_("Optimize lui/addiu address loads")}, \
a127db75 375 {"no-split-addresses", -MASK_SPLIT_ADDR, \
047142d3 376 N_("Don't optimize lui/addiu address loads")}, \
a127db75 377 {"mips-as", -MASK_GAS, \
047142d3 378 N_("Use MIPS as")}, \
a127db75 379 {"gas", MASK_GAS, \
047142d3 380 N_("Use GNU as")}, \
a127db75 381 {"rnames", MASK_NAME_REGS, \
047142d3 382 N_("Use symbolic register names")}, \
a127db75 383 {"no-rnames", -MASK_NAME_REGS, \
047142d3 384 N_("Don't use symbolic register names")}, \
a127db75 385 {"gpOPT", MASK_GPOPT, \
047142d3 386 N_("Use GP relative sdata/sbss sections")}, \
a127db75 387 {"gpopt", MASK_GPOPT, \
047142d3 388 N_("Use GP relative sdata/sbss sections")}, \
a127db75 389 {"no-gpOPT", -MASK_GPOPT, \
047142d3 390 N_("Don't use GP relative sdata/sbss sections")}, \
a127db75 391 {"no-gpopt", -MASK_GPOPT, \
047142d3 392 N_("Don't use GP relative sdata/sbss sections")}, \
a127db75 393 {"stats", MASK_STATS, \
047142d3 394 N_("Output compiler statistics")}, \
a127db75 395 {"no-stats", -MASK_STATS, \
047142d3 396 N_("Don't output compiler statistics")}, \
a127db75 397 {"memcpy", MASK_MEMCPY, \
047142d3 398 N_("Don't optimize block moves")}, \
a127db75 399 {"no-memcpy", -MASK_MEMCPY, \
047142d3 400 N_("Optimize block moves")}, \
a127db75 401 {"mips-tfile", MASK_MIPS_TFILE, \
047142d3 402 N_("Use mips-tfile asm postpass")}, \
a127db75 403 {"no-mips-tfile", -MASK_MIPS_TFILE, \
047142d3 404 N_("Don't use mips-tfile asm postpass")}, \
a127db75 405 {"soft-float", MASK_SOFT_FLOAT, \
047142d3 406 N_("Use software floating point")}, \
a127db75 407 {"hard-float", -MASK_SOFT_FLOAT, \
047142d3 408 N_("Use hardware floating point")}, \
a127db75 409 {"fp64", MASK_FLOAT64, \
047142d3 410 N_("Use 64-bit FP registers")}, \
a127db75 411 {"fp32", -MASK_FLOAT64, \
047142d3 412 N_("Use 32-bit FP registers")}, \
a127db75 413 {"gp64", MASK_64BIT, \
047142d3 414 N_("Use 64-bit general registers")}, \
a127db75 415 {"gp32", -MASK_64BIT, \
047142d3 416 N_("Use 32-bit general registers")}, \
a127db75 417 {"abicalls", MASK_ABICALLS, \
047142d3 418 N_("Use Irix PIC")}, \
a127db75 419 {"no-abicalls", -MASK_ABICALLS, \
047142d3 420 N_("Don't use Irix PIC")}, \
a127db75 421 {"half-pic", MASK_HALF_PIC, \
047142d3 422 N_("Use OSF PIC")}, \
a127db75 423 {"no-half-pic", -MASK_HALF_PIC, \
047142d3 424 N_("Don't use OSF PIC")}, \
a127db75 425 {"long-calls", MASK_LONG_CALLS, \
047142d3 426 N_("Use indirect calls")}, \
a127db75 427 {"no-long-calls", -MASK_LONG_CALLS, \
047142d3 428 N_("Don't use indirect calls")}, \
a127db75 429 {"embedded-pic", MASK_EMBEDDED_PIC, \
047142d3 430 N_("Use embedded PIC")}, \
a127db75 431 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
047142d3 432 N_("Don't use embedded PIC")}, \
a127db75 433 {"embedded-data", MASK_EMBEDDED_DATA, \
047142d3 434 N_("Use ROM instead of RAM")}, \
a127db75 435 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
047142d3 436 N_("Don't use ROM instead of RAM")}, \
919509ce 437 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
047142d3 438 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
919509ce 439 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
047142d3 440 N_("Don't put uninitialized constants in ROM")}, \
a127db75 441 {"eb", MASK_BIG_ENDIAN, \
047142d3 442 N_("Use big-endian byte order")}, \
a127db75 443 {"el", -MASK_BIG_ENDIAN, \
047142d3 444 N_("Use little-endian byte order")}, \
a127db75 445 {"single-float", MASK_SINGLE_FLOAT, \
047142d3 446 N_("Use single (32-bit) FP only")}, \
a127db75 447 {"double-float", -MASK_SINGLE_FLOAT, \
047142d3 448 N_("Don't use single (32-bit) FP only")}, \
a127db75 449 {"mad", MASK_MAD, \
047142d3 450 N_("Use multiply accumulate")}, \
a127db75 451 {"no-mad", -MASK_MAD, \
047142d3 452 N_("Don't use multiply accumulate")}, \
13fac94a
GK		 453 {"no-fused-madd", MASK_NO_FUSED_MADD, \
454 N_("Don't generate fused multiply/add instructions")}, \
455 {"fused-madd", -MASK_NO_FUSED_MADD, \
456 N_("Generate fused multiply/add instructions")}, \
a127db75 457 {"fix4300", MASK_4300_MUL_FIX, \
047142d3 458 N_("Work around early 4300 hardware bug")}, \
a127db75 459 {"no-fix4300", -MASK_4300_MUL_FIX, \
047142d3 460 N_("Don't work around early 4300 hardware bug")}, \
7dac2f89 461 {"3900", 0, \
047142d3 462 N_("Optimize for 3900")}, \
7dac2f89
EC		 463 {"4650", 0, \
464 N_("Optimize for 4650")}, \
a127db75 465 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
047142d3 466 N_("Trap on integer divide by zero")}, \
a127db75 467 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
047142d3 468 N_("Don't trap on integer divide by zero")}, \
a127db75 469 {"check-range-division",MASK_CHECK_RANGE_DIV, \
047142d3 470 N_("Trap on integer divide overflow")}, \
a127db75 471 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
047142d3 472 N_("Don't trap on integer divide overflow")}, \
a127db75
JW		 473 {"debug", MASK_DEBUG, \
474 NULL}, \
475 {"debuga", MASK_DEBUG_A, \
476 NULL}, \
477 {"debugb", MASK_DEBUG_B, \
478 NULL}, \
479 {"debugc", MASK_DEBUG_C, \
480 NULL}, \
481 {"debugd", MASK_DEBUG_D, \
482 NULL}, \
483 {"debuge", MASK_DEBUG_E, \
484 NULL}, \
485 {"debugf", MASK_DEBUG_F, \
486 NULL}, \
487 {"debugg", MASK_DEBUG_G, \
488 NULL}, \
489 {"debugh", MASK_DEBUG_H, \
490 NULL}, \
491 {"debugi", MASK_DEBUG_I, \
492 NULL}, \
96abdcb1
ILT		 493 {"", (TARGET_DEFAULT \
494 | TARGET_CPU_DEFAULT \
a127db75
JW		 495 | TARGET_ENDIAN_DEFAULT), \
496 NULL}, \
7dac2f89 497}
149e4e00
MM		 498
499/* Default target_flags if no switches are specified */
500
501#ifndef TARGET_DEFAULT
502#define TARGET_DEFAULT 0
503#endif
504
404f986e
MM		 505#ifndef TARGET_CPU_DEFAULT
506#define TARGET_CPU_DEFAULT 0
507#endif
508
96abdcb1
ILT		 509#ifndef TARGET_ENDIAN_DEFAULT
510#ifndef DECSTATION
511#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
512#else
513#define TARGET_ENDIAN_DEFAULT 0
514#endif
515#endif
516
ea09f032
GRK		 517#ifndef MIPS_ISA_DEFAULT
518#define MIPS_ISA_DEFAULT 1
519#endif
520
996ed075
JJ		 521#ifdef IN_LIBGCC2
522#undef TARGET_64BIT
523/* Make this compile time constant for libgcc2 */
524#ifdef __mips64
525#define TARGET_64BIT 1
526#else
527#define TARGET_64BIT 0
528#endif
440927ec 529#endif /* IN_LIBGCC2 */
996ed075 530
cbab8d02 531#ifndef MULTILIB_ENDIAN_DEFAULT
7f2e00db 532#if TARGET_ENDIAN_DEFAULT == 0
cbab8d02 533#define MULTILIB_ENDIAN_DEFAULT "EL"
7f2e00db 534#else
cbab8d02
GRK		 535#define MULTILIB_ENDIAN_DEFAULT "EB"
536#endif
7f2e00db 537#endif
cbab8d02 538
ea09f032 539#ifndef MULTILIB_ISA_DEFAULT
7ce2fcb9
KG		 540# if MIPS_ISA_DEFAULT == 1
541# define MULTILIB_ISA_DEFAULT "mips1"
542# else
543# if MIPS_ISA_DEFAULT == 2
544# define MULTILIB_ISA_DEFAULT "mips2"
545# else
546# if MIPS_ISA_DEFAULT == 3
547# define MULTILIB_ISA_DEFAULT "mips3"
548# else
549# if MIPS_ISA_DEFAULT == 4
550# define MULTILIB_ISA_DEFAULT "mips4"
551# else
0e5a4ad8
EC		 552# if MIPS_ISA_DEFAULT == 32
553# define MULTILIB_ISA_DEFAULT "mips32"
554# else
555# if MIPS_ISA_DEFAULT == 64
556# define MULTILIB_ISA_DEFAULT "mips64"
557# else
7ce2fcb9 558# define MULTILIB_ISA_DEFAULT "mips1"
0e5a4ad8 559# endif
7ce2fcb9 560# endif
0e5a4ad8 561# endif
7ce2fcb9
KG		 562# endif
563# endif
564# endif
ea09f032
GRK		 565#endif
566
cbab8d02 567#ifndef MULTILIB_DEFAULTS
ea09f032 568#define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
7f2e00db
RK		 569#endif
570
34bcd7fd
JW		 571/* We must pass -EL to the linker by default for little endian embedded
572 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
573 linker will default to using big-endian output files. The OUTPUT_FORMAT
574 line must be in the linker script, otherwise -EB/-EL will not work. */
575
120dc6cd 576#ifndef ENDIAN_SPEC
34bcd7fd 577#if TARGET_ENDIAN_DEFAULT == 0
ac282977 578#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
34bcd7fd 579#else
ac282977 580#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
34bcd7fd
JW		 581#endif
582#endif
583
149e4e00
MM		 584#define TARGET_OPTIONS \
585{ \
b2d8cf33 586 SUBTARGET_TARGET_OPTIONS \
a127db75 587 { "cpu=", &mips_cpu_string, \
047142d3 588 N_("Specify CPU for scheduling purposes")}, \
7dac2f89
EC		 589 { "tune=", &mips_tune_string, \
590 N_("Specify CPU for scheduling purposes")}, \
591 { "arch=", &mips_arch_string, \
592 N_("Specify CPU for code generation purposes")}, \
a127db75 593 { "ips", &mips_isa_string, \
7dac2f89 594 N_("Specify a Standard MIPS ISA")}, \
a127db75 595 { "entry", &mips_entry_string, \
047142d3 596 N_("Use mips16 entry/exit psuedo ops")}, \
a127db75 597 { "no-mips16", &mips_no_mips16_string, \
047142d3 598 N_("Don't use MIPS16 instructions")}, \
a127db75
JW		 599 { "explicit-type-size", &mips_explicit_type_size_string, \
600 NULL}, \
d490e8ad
DD		 601 { "no-flush-func", &mips_cache_flush_func, \
602 N_("Don't call any cache flush functions")}, \
603 { "flush-func=", &mips_cache_flush_func, \
604 N_("Specify cache flush function")}, \
149e4e00
MM		 605}
606
b2d8cf33
JW		 607/* This is meant to be redefined in the host dependent files. */
608#define SUBTARGET_TARGET_OPTIONS
609
7dac2f89 610#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
e4f5c5d6 611
0e5a4ad8
EC		 612/* Generate three-operand multiply instructions for SImode. */
613#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
614 || mips_isa == 32 \
615 || mips_isa == 64) \
616 && !TARGET_MIPS16)
617
618/* Generate three-operand multiply instructions for DImode. */
619#define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
620 && !TARGET_MIPS16)
e9a25f70 621
149e4e00
MM		 622/* Macros to decide whether certain features are available or not,
623 depending on the instruction set architecture level. */
624
e9a25f70 625#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
1d5d552e
GRK		 626#define HAVE_SQRT_P() (mips_isa != 1)
627
987ba558 628/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
0e5a4ad8
EC		 629#define ISA_HAS_64BIT_REGS (mips_isa == 3 \
630 || mips_isa == 4 \
631 || mips_isa == 64)
1d5d552e 632
987ba558 633/* ISA has branch likely instructions (eg. mips2). */
7dac2f89
EC		 634/* Disable branchlikely for tx39 until compare rewrite. They haven't
635 been generated up to this point. */
636#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
974a3101 637 && ! TARGET_MIPS16)
1d5d552e 638
987ba558 639/* ISA has the conditional move instructions introduced in mips4. */
974a3101
AO		 640#define ISA_HAS_CONDMOVE ((mips_isa == 4 \
641 || mips_isa == 32 \
642 || mips_isa == 64) \
643 && ! TARGET_MIPS16)
76ee8042 644
0025b7fa
GRK		 645/* ISA has just the integer condition move instructions (movn,movz) */
646#define ISA_HAS_INT_CONDMOVE 0
647
76ee8042 648/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
987ba558 649 branch on CC, and move (both FP and non-FP) on CC. */
76ee8042 650#define ISA_HAS_8CC (mips_isa == 4 \
0e5a4ad8
EC		 651 || mips_isa == 32 \
652 || mips_isa == 64)
76ee8042 653
76ee8042 654/* This is a catch all for the other new mips4 instructions: indexed load and
7dac2f89 655 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
76ee8042
GRK		 656 and the FP recip and recip sqrt instructions */
657#define ISA_HAS_FP4 (mips_isa == 4 \
974a3101 658 && ! TARGET_MIPS16)
76ee8042 659
a0b6cdee 660/* ISA has conditional trap instructions. */
974a3101
AO		 661#define ISA_HAS_COND_TRAP (mips_isa >= 2 \
662 && ! TARGET_MIPS16)
1d5d552e 663
0e5a4ad8 664/* ISA has multiply-accumulate instructions, madd and msub. */
974a3101
AO		 665#define ISA_HAS_MADD_MSUB ((mips_isa == 32 \
666 || mips_isa == 64 \
667 ) && ! TARGET_MIPS16)
0e5a4ad8 668
1f28c666
AH		 669/* ISA has nmadd and nmsub instructions. */
670#define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
974a3101 671 && ! TARGET_MIPS16)
149e4e00 672
0e5a4ad8 673/* ISA has count leading zeroes/ones instruction (not implemented). */
974a3101
AO		 674#define ISA_HAS_CLZ_CLO ((mips_isa == 32 \
675 || mips_isa == 64 \
676 ) && ! TARGET_MIPS16)
0e5a4ad8
EC		 677
678/* ISA has double-word count leading zeroes/ones instruction (not
679 implemented). */
974a3101
AO		 680#define ISA_HAS_DCLZ_DCLO (mips_isa == 64 \
681 && ! TARGET_MIPS16)
0e5a4ad8 682
516a2dfd
JW		 683/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
684 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
2370b831
JW		 685 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
686 target_flags, and -mgp64 sets MASK_64BIT.
876c09d3 687
2370b831
JW		 688 Setting MASK_64BIT in target_flags will cause gcc to assume that
689 registers are 64 bits wide. int, long and void * will be 32 bit;
690 this may be changed with -mint64 or -mlong64.
876c09d3 691
2370b831
JW		 692 The gen* programs link code that refers to MASK_64BIT. They don't
693 actually use the information in target_flags; they just refer to
694 it. */
e75b25e7
MM		 695\f
696/* Switch Recognition by gcc.c. Add -G xx support */
697
0e5a4ad8 698#undef SWITCH_TAKES_ARG
e75b25e7 699#define SWITCH_TAKES_ARG(CHAR) \
7d4ea832 700 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
e75b25e7
MM		 701
702/* Sometimes certain combinations of command options do not make sense
703 on a particular target machine. You can define a macro
704 `OVERRIDE_OPTIONS' to take account of this. This macro, if
705 defined, is executed once just after all the command options have
706 been parsed.
707
708 On the MIPS, it is used to handle -G. We also use it to set up all
709 of the tables referenced in the other macros. */
710
711#define OVERRIDE_OPTIONS override_options ()
712
713/* Zero or more C statements that may conditionally modify two
714 variables `fixed_regs' and `call_used_regs' (both of type `char
715 []') after they have been initialized from the two preceding
716 macros.
717
718 This is necessary in case the fixed or call-clobbered registers
719 depend on target flags.
720
721 You need not define this macro if it has no work to do.
722
723 If the usage of an entire class of registers depends on the target
724 flags, you may indicate this to GCC by using this macro to modify
725 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
726 the classes which should not be used by GCC. Also define the macro
727 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
728 letter for a class that shouldn't be used.
729
730 (However, if this class is not included in `GENERAL_REGS' and all
731 of the insn patterns whose constraints permit this class are
732 controlled by target switches, then GCC will automatically avoid
733 using these registers when the target switches are opposed to
734 them.) */
735
736#define CONDITIONAL_REGISTER_USAGE \
737do \
738 { \
739 if (!TARGET_HARD_FLOAT) \
740 { \
741 int regno; \
742 \
743 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
744 fixed_regs[regno] = call_used_regs[regno] = 1; \
b8eb88d0
ILT		 745 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
746 fixed_regs[regno] = call_used_regs[regno] = 1; \
747 } \
76ee8042 748 else if (! ISA_HAS_8CC) \
b8eb88d0
ILT		 749 { \
750 int regno; \
751 \
752 /* We only have a single condition code register. We \
753 implement this by hiding all the condition code registers, \
754 and generating RTL that refers directly to ST_REG_FIRST. */ \
755 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
756 fixed_regs[regno] = call_used_regs[regno] = 1; \
e75b25e7 757 } \
2bcb2ab3
GK		 758 /* In mips16 mode, we permit the $t temporary registers to be used \
759 for reload. We prohibit the unused $s registers, since they \
760 are caller saved, and saving them via a mips16 register would \
761 probably waste more time than just reloading the value. */ \
762 if (TARGET_MIPS16) \
763 { \
764 fixed_regs[18] = call_used_regs[18] = 1; \
765 fixed_regs[19] = call_used_regs[19] = 1; \
766 fixed_regs[20] = call_used_regs[20] = 1; \
767 fixed_regs[21] = call_used_regs[21] = 1; \
768 fixed_regs[22] = call_used_regs[22] = 1; \
769 fixed_regs[23] = call_used_regs[23] = 1; \
770 fixed_regs[26] = call_used_regs[26] = 1; \
771 fixed_regs[27] = call_used_regs[27] = 1; \
772 fixed_regs[30] = call_used_regs[30] = 1; \
773 } \
516a2dfd 774 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
e75b25e7
MM		 775 } \
776while (0)
777
b2d8cf33 778/* This is meant to be redefined in the host dependent files. */
516a2dfd
JW		 779#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
780
7be1e523
RK		 781/* Show we can debug even without a frame pointer. */
782#define CAN_DEBUG_WITHOUT_FP
783\f
e75b25e7
MM		 784/* Complain about missing specs and predefines that should be defined in each
785 of the target tm files to override the defaults. This is mostly a place-
786 holder until I can get each of the files updated [mm]. */
787
788#if defined(OSF_OS) \
789 || defined(DECSTATION) \
790 || defined(SGI_TARGET) \
791 || defined(MIPS_NEWS) \
792 || defined(MIPS_SYSV) \
59c94430 793 || defined(MIPS_SVR4) \
e75b25e7
MM		 794 || defined(MIPS_BSD43)
795
796#ifndef CPP_PREDEFINES
797 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
798#endif
799
e75b25e7
MM		 800#ifndef LIB_SPEC
801 #error "Define LIB_SPEC in the appropriate tm.h file"
802#endif
803
804#ifndef STARTFILE_SPEC
805 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
806#endif
807
808#ifndef MACHINE_TYPE
809 #error "Define MACHINE_TYPE in the appropriate tm.h file"
810#endif
811#endif
812
59c94430
MM		 813/* Tell collect what flags to pass to nm. */
814#ifndef NM_FLAGS
2ce3c6c6 815#define NM_FLAGS "-Bn"
59c94430
MM		 816#endif
817
e75b25e7
MM		 818\f
819/* Names to predefine in the preprocessor for this target machine. */
820
821#ifndef CPP_PREDEFINES
d4099651 822#define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
65c42379 823-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
2b57e919 824-Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
e75b25e7
MM		 825#endif
826
4e88bbcd
ILT		 827/* Assembler specs. */
828
829/* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
830 than gas. */
831
832#define MIPS_AS_ASM_SPEC "\
833%{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
c725bd79 834%{pipe: %e-pipe is not supported} \
4e88bbcd
ILT		 835%{K} %(subtarget_mips_as_asm_spec)"
836
837/* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
838 rather than gas. It may be overridden by subtargets. */
839
840#ifndef SUBTARGET_MIPS_AS_ASM_SPEC
841#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
842#endif
843
844/* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
845 assembler. */
846
009da785
EC		 847#define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}"
848
849
009da785 850extern int mips_abi;
0e5a4ad8
EC		 851
852#ifndef MIPS_ABI_DEFAULT
009da785
EC		 853#define MIPS_ABI_DEFAULT ABI_32
854#endif
0e5a4ad8 855
009da785 856#ifndef ABI_GAS_ASM_SPEC
f9f45c65 857#define ABI_GAS_ASM_SPEC ""
0e5a4ad8 858#endif
4e88bbcd
ILT		 859
860/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
861 GAS_ASM_SPEC as the default, depending upon the value of
862 TARGET_DEFAULT. */
e75b25e7 863
bb98bc58
JW		 864#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
865/* GAS */
bb98bc58 866
4e88bbcd
ILT		 867#define TARGET_ASM_SPEC "\
868%{mmips-as: %(mips_as_asm_spec)} \
869%{!mmips-as: %(gas_asm_spec)}"
870
871#else /* not GAS */
872
873#define TARGET_ASM_SPEC "\
874%{!mgas: %(mips_as_asm_spec)} \
875%{mgas: %(gas_asm_spec)}"
876
877#endif /* not GAS */
878
879/* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
880 to the assembler. It may be overridden by subtargets. */
881#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
882#define SUBTARGET_ASM_OPTIMIZING_SPEC "\
bb98bc58 883%{noasmopt:-O0} \
4e88bbcd
ILT		 884%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
885#endif
886
887/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
888 the assembler. It may be overridden by subtargets. */
889#ifndef SUBTARGET_ASM_DEBUGGING_SPEC
890#define SUBTARGET_ASM_DEBUGGING_SPEC "\
bb98bc58
JW		 891%{g} %{g0} %{g1} %{g2} %{g3} \
892%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
893%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
894%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
4e88bbcd
ILT		 895%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
896#endif
bb98bc58 897
4e88bbcd
ILT		 898/* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
899 overridden by subtargets. */
900
901#ifndef SUBTARGET_ASM_SPEC
902#define SUBTARGET_ASM_SPEC ""
bb98bc58 903#endif
4e88bbcd
ILT		 904
905/* ASM_SPEC is the set of arguments to pass to the assembler. */
906
b2bcb32d 907#undef ASM_SPEC
4e88bbcd 908#define ASM_SPEC "\
0e5a4ad8 909%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
2bcb2ab3 910%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
4e88bbcd
ILT		 911%(subtarget_asm_optimizing_spec) \
912%(subtarget_asm_debugging_spec) \
913%{membedded-pic} \
914%{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
915%(target_asm_spec) \
916%(subtarget_asm_spec)"
e75b25e7
MM		 917
918/* Specify to run a post-processor, mips-tfile after the assembler
919 has run to stuff the mips debug information into the object file.
920 This is needed because the $#!%^ MIPS assembler provides no way
a813fadf
MM		 921 of specifying such information in the assembly file. If we are
922 cross compiling, disable mips-tfile unless the user specifies
923 -mmips-tfile. */
e75b25e7
MM		 924
925#ifndef ASM_FINAL_SPEC
bb98bc58
JW		 926#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
927/* GAS */
31c714e3 928#define ASM_FINAL_SPEC "\
149e4e00 929%{mmips-as: %{!mno-mips-tfile: \
31c714e3
MM		 930 \n mips-tfile %{v*: -v} \
931 %{K: -I %b.o~} \
932 %{!K: %{save-temps: -I %b.o~}} \
ab78d4a8 933 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
31c714e3 934 %{.s:%i} %{!.s:%g.s}}}"
a813fadf 935
bb98bc58
JW		 936#else
937/* not GAS */
a813fadf 938#define ASM_FINAL_SPEC "\
149e4e00 939%{!mgas: %{!mno-mips-tfile: \
a813fadf
MM		 940 \n mips-tfile %{v*: -v} \
941 %{K: -I %b.o~} \
942 %{!K: %{save-temps: -I %b.o~}} \
943 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
944 %{.s:%i} %{!.s:%g.s}}}"
945
bb98bc58 946#endif
a813fadf 947#endif /* ASM_FINAL_SPEC */
e75b25e7
MM		 948
949/* Redefinition of libraries used. Mips doesn't support normal
950 UNIX style profiling via calling _mcount. It does offer
987ba558 951 profiling that samples the PC, so do what we can... */
e75b25e7
MM		 952
953#ifndef LIB_SPEC
954#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
955#endif
956
31c714e3 957/* Extra switches sometimes passed to the linker. */
bb98bc58
JW		 958/* ??? The bestGnum will never be passed to the linker, because the gcc driver
959 will interpret it as a -b option. */
e75b25e7
MM		 960
961#ifndef LINK_SPEC
31c714e3 962#define LINK_SPEC "\
120dc6cd 963%(endian_spec) \
0e5a4ad8 964%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
120dc6cd 965%{bestGnum} %{shared} %{non_shared}"
0e5a4ad8
EC		 966#endif /* LINK_SPEC defined */
967
e75b25e7
MM		 968
969/* Specs for the compiler proper */
970
c9db96ce
JR		 971/* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
972 overridden by subtargets. */
973#ifndef SUBTARGET_CC1_SPEC
974#define SUBTARGET_CC1_SPEC ""
975#endif
976
7dac2f89
EC		 977/* Deal with historic options. */
978#ifndef CC1_CPU_SPEC
979#define CC1_CPU_SPEC "\
980%{!mcpu*: \
981%{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
982%n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
983%{m4650:-march=r4650 -mmad -msingle-float \
984%n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
985#endif
986
c9db96ce 987/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
75dcd8fe
MM		 988/* Note, we will need to adjust the following if we ever find a MIPS variant
989 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
990 that show up in this case. */
c9db96ce 991
e75b25e7 992#ifndef CC1_SPEC
31c714e3 993#define CC1_SPEC "\
31c714e3 994%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
7e99e494 995%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
46299de9 996%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
516a2dfd 997%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
0e5a4ad8
EC		 998%{mips32:-mfp32 -mgp32} \
999%{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
46299de9
ILT		 1000%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
1001%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
3ce1ba83 1002%{mint64|mlong64|mlong32:-mexplicit-type-size }\
75dcd8fe 1003%{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
96abdcb1 1004%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
31c714e3
MM		 1005%{pic-none: -mno-half-pic} \
1006%{pic-lib: -mhalf-pic} \
1007%{pic-extern: -mhalf-pic} \
1008%{pic-calls: -mhalf-pic} \
c9db96ce 1009%{save-temps: } \
7dac2f89
EC		 1010%(subtarget_cc1_spec) \
1011%(cc1_cpu_spec)"
e75b25e7
MM		 1012#endif
1013
4e88bbcd
ILT		 1014/* Preprocessor specs. */
1015
1016/* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
1017 be overridden by subtargets. */
1018
1019#ifndef SUBTARGET_CPP_SIZE_SPEC
f9f45c65 1020
8a13c092
AO		 1021/* Rules for SIZE_TYPE and PTRDIFF_TYPE are:
1022
1023 both gp64 and long64 (not the options, but the corresponding flags,
1024 so defaults came into play) are required in order to have `long' in
1025 SIZE_TYPE and PTRDIFF_TYPE.
1026
1027 on eabi, -mips1, -mips2 and -mips32 disable gp64, whereas mips3,
1028 -mips4, -mips5 and -mips64 enable it.
1029
1030 on other ABIs, -mips* options do not affect gp32/64, but the
1031 default ISA affects the default gp size.
1032
1033 -mgp32 disables gp64, whereas -mgp64 enables it.
1034
1035 on eabi, gp64 implies long64.
1036
1037 -mlong64, and -mabi=64 are the only other ways to enable long64.
1038
1039*/
1040
f9f45c65
EC		 1041#if MIPS_ISA_DEFAULT != 3 && MIPS_ISA_DEFAULT != 4 && MIPS_ISA_DEFAULT != 5 && MIPS_ISA_DEFAULT != 64
1042
1043/* 32-bit cases first. */
1044
1045#if MIPS_ABI_DEFAULT == ABI_EABI
1046#define SUBTARGET_CPP_SIZE_SPEC "\
1047%{mabi=eabi|!mabi=*:\
8a13c092
AO		 1048 %{mips1|mips2|mips32|mgp32|mlong32: \
1049 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1050 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1051 %{mips3|mips4|mips5|mips64|mgp64: \
1052 -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1053 %{!mips3:%{!mips4:%{!mips5:%{!mips64:%{!mgp64: \
1054 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}} \
f9f45c65 1055%{mabi=o64:\
8a13c092
AO		 1056 %{!mgp64|!-mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1057 %{mgp64:%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
f9f45c65
EC		 1058%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1059"
5faae4f7
AO		 1060#define LONG_MAX_SPEC "\
1061%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
1062%{!mlong64:\
1063 %{mabi=eabi|!mabi=*:\
1064 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1065 %{mips3|mips4|mips5|mips64|mgp64: \
1066 -D__LONG_MAX__=9223372036854775807L}}}}}}}} \
1067"
1068#else /* ABI_DEFAULT != ABI_EABI */
1069#define LONG_MAX_SPEC "\
1070%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
1071%{!mlong64:\
1072 %{mabi=eabi:\
1073 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1074 %{mips3|mips4|mips5|mips64|mgp64: \
1075 -D__LONG_MAX__=9223372036854775807L}}}}}}}} \
1076"
f9f45c65
EC		 1077#endif
1078
1079#if MIPS_ABI_DEFAULT == ABI_O64
1080#define SUBTARGET_CPP_SIZE_SPEC "\
1081%{mabi=eabi:\
8a13c092
AO		 1082 %{mips1|mips2|mips32|mgp32|mlong32: \
1083 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1084 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1085 %{mips3|mips4|mips5|mips64|mgp64: \
1086 -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1087 %{!mips3:%{!mips4:%{!mips5:%{!mips64:%{!mgp64: \
1088 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}} \
f9f45c65 1089%{mabi=o64|!mabi=*:\
8a13c092
AO		 1090 %{!mgp64|!-mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1091 %{mgp64:%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
1092%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1ac458d4 1093%{mabi=meabi:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
f9f45c65
EC		 1094"
1095#endif
1096
1097#if MIPS_ABI_DEFAULT == ABI_32
4e88bbcd 1098#define SUBTARGET_CPP_SIZE_SPEC "\
f9f45c65 1099%{mabi=eabi:\
8a13c092
AO		 1100 %{mips1|mips2|mips32|mgp32|mlong32: \
1101 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1102 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1103 %{mips3|mips4|mips5|mips64|mgp64: \
1104 -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1105 %{!mips3:%{!mips4:%{!mips5:%{!mips64:%{!mgp64: \
1106 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}} \
f9f45c65 1107%{mabi=o64:\
8a13c092
AO		 1108 %{!mgp64|!-mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1109 %{mgp64:%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
1110%{mabi=32|!mabi=*:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1ac458d4 1111%{mabi=meabi:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
f9f45c65
EC		 1112"
1113#endif
1114
1115#if MIPS_ABI_DEFAULT == ABI_MEABI
1116#define SUBTARGET_CPP_SIZE_SPEC "\
1117%{mabi=eabi:\
8a13c092
AO		 1118 %{mips1|mips2|mips32|mgp32|mlong32: \
1119 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1120 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1121 %{mips3|mips4|mips5|mips64|mgp64: \
1122 -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1123 %{!mips3:%{!mips4:%{!mips5:%{!mips64:%{!mgp64: \
1124 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}} \
f9f45c65 1125%{mabi=o64:\
8a13c092
AO		 1126 %{!mgp64|!-mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1127 %{mgp64:%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
e25d11b0 1128%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1ac458d4 1129%{mabi=meabi|!mabi=*:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
f9f45c65
EC		 1130"
1131#endif
1132
1133#else
1134
1135/* 64-bit default ISA. */
f9f45c65
EC		 1136#if MIPS_ABI_DEFAULT == ABI_EABI
1137#define SUBTARGET_CPP_SIZE_SPEC "\
1138%{mabi=eabi|!mabi=*: \
8a13c092
AO		 1139 %{mips1|mips2|mips32|mgp32|mlong32: \
1140 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1141 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1142 -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}} \
f9f45c65 1143%{mabi=o64:\
8a13c092
AO		 1144 %{mgp32|!-mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1145 %{!mgp32:%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
f9f45c65 1146%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1ac458d4 1147%{mabi=meabi:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
f9f45c65 1148"
5faae4f7
AO		 1149#define LONG_MAX_SPEC "\
1150%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
1151%{!mlong64:\
1152 %{mabi=eabi|!mabi=*:\
1153 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1154 -D__LONG_MAX__=9223372036854775807L}}}}}}}\
1155"
1156#else /* ABI_DEFAULT != ABI_EABI */
1157#define LONG_MAX_SPEC "\
1158%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
1159%{!mlong64:\
1160 %{mabi=eabi:\
1161 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1162 -D__LONG_MAX__=9223372036854775807L}}}}}}}\
1163"
f9f45c65
EC		 1164#endif
1165
1166#if MIPS_ABI_DEFAULT == ABI_O64
1167#define SUBTARGET_CPP_SIZE_SPEC "\
1168%{mabi=eabi: \
8a13c092
AO		 1169 %{mips1|mips2|mips32|mgp32|mlong32: \
1170 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1171 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1172 -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}} \
f9f45c65 1173%{mabi=o64|!mabi=*:\
8a13c092
AO		 1174 %{mgp32|!-mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1175 %{!mgp32:%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
1176%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1ac458d4 1177%{mabi=meabi:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
f9f45c65
EC		 1178"
1179#endif
1180
1181#if MIPS_ABI_DEFAULT == ABI_32
1182#define SUBTARGET_CPP_SIZE_SPEC "\
1183%{mabi=eabi:\
8a13c092
AO		 1184 %{mips1|mips2|mips32|mgp32|mlong32: \
1185 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1186 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1187 -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}} \
f9f45c65 1188%{mabi=o64:\
8a13c092
AO		 1189 %{mgp32|!-mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1190 %{!mgp32:%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
1191%{mabi=32|!mabi=*:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1ac458d4 1192%{mabi=meabi:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
f9f45c65
EC		 1193"
1194#endif
1195
1196#if MIPS_ABI_DEFAULT == ABI_MEABI
1197#define SUBTARGET_CPP_SIZE_SPEC "\
1198%{mabi=eabi:\
8a13c092
AO		 1199 %{mips1|mips2|mips32|mgp32|mlong32: \
1200 -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1201 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1202 -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}} \
f9f45c65 1203%{mabi=o64:\
8a13c092
AO		 1204 %{mgp32|!-mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1205 %{!mgp32:%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
e25d11b0 1206%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1ac458d4 1207%{mabi=meabi|!mabi=*:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
f9f45c65
EC		 1208"
1209#endif
1210
1211#endif
1212
4e88bbcd
ILT		 1213#endif
1214
1215/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1216 overridden by subtargets. */
1217#ifndef SUBTARGET_CPP_SPEC
1218#define SUBTARGET_CPP_SPEC ""
1219#endif
1220
75dcd8fe
MM		 1221/* Define appropriate macros for fpr register size. */
1222#ifndef CPP_FPR_SPEC
1223#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64)
1224#define CPP_FPR_SPEC "-D__mips_fpr=64"
1225#else
1226#define CPP_FPR_SPEC "-D__mips_fpr=32"
1227#endif
1228#endif
1229
64b172fe
RO		 1230/* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
1231 of the source file extension. */
b2bcb32d 1232#undef CPLUSPLUS_CPP_SPEC
64b172fe
RO		 1233#define CPLUSPLUS_CPP_SPEC "\
1234-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
1235%(cpp) \
1236"
4e88bbcd 1237/* CPP_SPEC is the set of arguments to pass to the preprocessor. */
e75b25e7
MM		 1238
1239#ifndef CPP_SPEC
31c714e3 1240#define CPP_SPEC "\
0002d808 1241%{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
64b172fe
RO		 1242%{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1243%{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
4e88bbcd 1244%(subtarget_cpp_size_spec) \
192616a4
RK		 1245%{mips3:-U__mips -D__mips=3 -D__mips64} \
1246%{mips4:-U__mips -D__mips=4 -D__mips64} \
0e5a4ad8
EC		 1247%{mips32:-U__mips -D__mips=32} \
1248%{mips64:-U__mips -D__mips=64 -D__mips64} \
192616a4 1249%{mgp32:-U__mips64} %{mgp64:-D__mips64} \
75dcd8fe 1250%{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
54efdaa4
JW		 1251%{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1252%{m4650:%{!msoft-float:-D__mips_single_float}} \
293a36eb
ILT		 1253%{msoft-float:-D__mips_soft_float} \
1254%{mabi=eabi:-D__mips_eabi} \
2bcb2ab3 1255%{mips16:%{!mno-mips16:-D__mips16}} \
96abdcb1 1256%{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
4e88bbcd 1257%{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
4eb66248 1258%(long_max_spec) \
4e88bbcd
ILT		 1259%(subtarget_cpp_spec) "
1260#endif
1261
1262/* This macro defines names of additional specifications to put in the specs
1263 that can be used in various specifications like CC1_SPEC. Its definition
1264 is an initializer with a subgrouping for each command option.
1265
1266 Each subgrouping contains a string constant, that defines the
1267 specification name, and a string constant that used by the GNU CC driver
1268 program.
1269
1270 Do not define this macro if it does not need to do anything. */
1271
1272#define EXTRA_SPECS \
829245be 1273 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
7a38df19 1274 { "cc1_cpu_spec", CC1_CPU_SPEC}, \
829245be
KG		 1275 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1276 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1277 { "long_max_spec", LONG_MAX_SPEC }, \
75dcd8fe 1278 { "cpp_fpr_spec", CPP_FPR_SPEC }, \
829245be
KG		 1279 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1280 { "gas_asm_spec", GAS_ASM_SPEC }, \
0e5a4ad8 1281 { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, \
829245be
KG		 1282 { "target_asm_spec", TARGET_ASM_SPEC }, \
1283 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1284 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1285 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1286 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
120dc6cd 1287 { "endian_spec", ENDIAN_SPEC }, \
4e88bbcd
ILT		 1288 SUBTARGET_EXTRA_SPECS
1289
1290#ifndef SUBTARGET_EXTRA_SPECS
1291#define SUBTARGET_EXTRA_SPECS
e75b25e7
MM		 1292#endif
1293
1294/* If defined, this macro is an additional prefix to try after
1295 `STANDARD_EXEC_PREFIX'. */
1296
1297#ifndef MD_EXEC_PREFIX
31c714e3 1298#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
e75b25e7
MM		 1299#endif
1300
59c94430
MM		 1301#ifndef MD_STARTFILE_PREFIX
1302#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1303#endif
1304
e75b25e7
MM		 1305\f
1306/* Print subsidiary information on the compiler version in use. */
1307
42dee4c7 1308#define MIPS_VERSION "[AL 1.1, MM 40]"
e75b25e7
MM		 1309
1310#ifndef MACHINE_TYPE
1311#define MACHINE_TYPE "BSD Mips"
1312#endif
1313
1314#ifndef TARGET_VERSION_INTERNAL
1315#define TARGET_VERSION_INTERNAL(STREAM) \
1316 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1317#endif
1318
1319#ifndef TARGET_VERSION
1320#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1321#endif
1322
1323\f
1324#define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1325#define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1326#define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1327
1328#ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
fe0986b4 1329#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
e75b25e7
MM		 1330#endif
1331
59c94430
MM		 1332/* By default, turn on GDB extensions. */
1333#define DEFAULT_GDB_EXTENSIONS 1
1334
e75b25e7
MM		 1335/* If we are passing smuggling stabs through the MIPS ECOFF object
1336 format, put a comment in front of the .stab<x> operation so
1337 that the MIPS assembler does not choke. The mips-tfile program
1338 will correctly put the stab into the object file. */
1339
78d057d8
HPN		 1340#define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1341#define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1342#define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
e75b25e7 1343
6ae1498b
JW		 1344/* Local compiler-generated symbols must have a prefix that the assembler
1345 understands. By default, this is $, although some targets (e.g.,
987ba558 1346 NetBSD-ELF) need to override this. */
6ae1498b
JW		 1347
1348#ifndef LOCAL_LABEL_PREFIX
1349#define LOCAL_LABEL_PREFIX "$"
1350#endif
1351
1352/* By default on the mips, external symbols do not have an underscore
987ba558 1353 prepended, but some targets (e.g., NetBSD) require this. */
6ae1498b
JW		 1354
1355#ifndef USER_LABEL_PREFIX
1356#define USER_LABEL_PREFIX ""
1357#endif
1358
e75b25e7
MM		 1359/* Forward references to tags are allowed. */
1360#define SDB_ALLOW_FORWARD_REFERENCES
1361
1362/* Unknown tags are also allowed. */
1363#define SDB_ALLOW_UNKNOWN_REFERENCES
1364
1365/* On Sun 4, this limit is 2048. We use 1500 to be safe,
1366 since the length can run past this up to a continuation point. */
44404b8b 1367#undef DBX_CONTIN_LENGTH
e75b25e7
MM		 1368#define DBX_CONTIN_LENGTH 1500
1369
987ba558 1370/* How to renumber registers for dbx and gdb. */
e75b25e7
MM		 1371#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1372
c8cc5c4a 1373/* The mapping from gcc register number to DWARF 2 CFA column number.
0021b564
JM		 1374 This mapping does not allow for tracking register 0, since SGI's broken
1375 dwarf reader thinks column 0 is used for the frame address, but since
1376 register 0 is fixed this is not a problem. */
469ac993 1377#define DWARF_FRAME_REGNUM(REG) \
0021b564 1378 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
c8cc5c4a
JM		 1379
1380/* The DWARF 2 CFA column which tracks the return address. */
1381#define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
e75b25e7 1382
469ac993 1383/* Before the prologue, RA lives in r31. */
c5c76735 1384#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
469ac993 1385
9e800206 1386/* Describe how we implement __builtin_eh_return. */
282cb01b 1387#define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
9e800206
RH		 1388#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1389
7dac2f89 1390/* Offsets recorded in opcodes are a multiple of this alignment factor.
b3276c7a
GK		 1391 The default for this in 64-bit mode is 8, which causes problems with
1392 SFmode register saves. */
1393#define DWARF_CIE_DATA_ALIGNMENT 4
1394
e75b25e7
MM		 1395/* Overrides for the COFF debug format. */
1396#define PUT_SDB_SCL(a) \
1397do { \
1398 extern FILE *asm_out_text_file; \
1399 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1400} while (0)
1401
1402#define PUT_SDB_INT_VAL(a) \
1403do { \
1404 extern FILE *asm_out_text_file; \
e59f7d3d
KG		 1405 fprintf (asm_out_text_file, "\t.val\t"); \
1406 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1407 fprintf (asm_out_text_file, ";"); \
e75b25e7
MM		 1408} while (0)
1409
1410#define PUT_SDB_VAL(a) \
1411do { \
1412 extern FILE *asm_out_text_file; \
1413 fputs ("\t.val\t", asm_out_text_file); \
1414 output_addr_const (asm_out_text_file, (a)); \
1415 fputc (';', asm_out_text_file); \
1416} while (0)
1417
1418#define PUT_SDB_DEF(a) \
1419do { \
1420 extern FILE *asm_out_text_file; \
b82b0773
MM		 1421 fprintf (asm_out_text_file, "\t%s.def\t", \
1422 (TARGET_GAS) ? "" : "#"); \
e75b25e7
MM		 1423 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1424 fputc (';', asm_out_text_file); \
1425} while (0)
1426
1427#define PUT_SDB_PLAIN_DEF(a) \
1428do { \
1429 extern FILE *asm_out_text_file; \
b82b0773
MM		 1430 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1431 (TARGET_GAS) ? "" : "#", (a)); \
e75b25e7
MM		 1432} while (0)
1433
1434#define PUT_SDB_ENDEF \
1435do { \
1436 extern FILE *asm_out_text_file; \
1437 fprintf (asm_out_text_file, "\t.endef\n"); \
1438} while (0)
1439
1440#define PUT_SDB_TYPE(a) \
1441do { \
1442 extern FILE *asm_out_text_file; \
1443 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1444} while (0)
1445
1446#define PUT_SDB_SIZE(a) \
1447do { \
1448 extern FILE *asm_out_text_file; \
e59f7d3d
KG		 1449 fprintf (asm_out_text_file, "\t.size\t"); \
1450 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1451 fprintf (asm_out_text_file, ";"); \
e75b25e7
MM		 1452} while (0)
1453
1454#define PUT_SDB_DIM(a) \
1455do { \
1456 extern FILE *asm_out_text_file; \
1457 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1458} while (0)
1459
1460#ifndef PUT_SDB_START_DIM
1461#define PUT_SDB_START_DIM \
1462do { \
1463 extern FILE *asm_out_text_file; \
1464 fprintf (asm_out_text_file, "\t.dim\t"); \
1465} while (0)
1466#endif
1467
1468#ifndef PUT_SDB_NEXT_DIM
1469#define PUT_SDB_NEXT_DIM(a) \
1470do { \
1471 extern FILE *asm_out_text_file; \
1472 fprintf (asm_out_text_file, "%d,", a); \
1473} while (0)
1474#endif
1475
1476#ifndef PUT_SDB_LAST_DIM
1477#define PUT_SDB_LAST_DIM(a) \
1478do { \
1479 extern FILE *asm_out_text_file; \
1480 fprintf (asm_out_text_file, "%d;", a); \
1481} while (0)
1482#endif
1483
1484#define PUT_SDB_TAG(a) \
1485do { \
1486 extern FILE *asm_out_text_file; \
1487 fprintf (asm_out_text_file, "\t.tag\t"); \
1488 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1489 fputc (';', asm_out_text_file); \
1490} while (0)
1491
1492/* For block start and end, we create labels, so that
1493 later we can figure out where the correct offset is.
1494 The normal .ent/.end serve well enough for functions,
1495 so those are just commented out. */
1496
1497#define PUT_SDB_BLOCK_START(LINE) \
1498do { \
1499 extern FILE *asm_out_text_file; \
1500 fprintf (asm_out_text_file, \
6ae1498b
JW		 1501 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1502 LOCAL_LABEL_PREFIX, \
e75b25e7 1503 sdb_label_count, \
b82b0773 1504 (TARGET_GAS) ? "" : "#", \
6ae1498b 1505 LOCAL_LABEL_PREFIX, \
e75b25e7
MM		 1506 sdb_label_count, \
1507 (LINE)); \
1508 sdb_label_count++; \
1509} while (0)
1510
1511#define PUT_SDB_BLOCK_END(LINE) \
1512do { \
1513 extern FILE *asm_out_text_file; \
1514 fprintf (asm_out_text_file, \
6ae1498b
JW		 1515 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1516 LOCAL_LABEL_PREFIX, \
e75b25e7 1517 sdb_label_count, \
b82b0773 1518 (TARGET_GAS) ? "" : "#", \
6ae1498b 1519 LOCAL_LABEL_PREFIX, \
e75b25e7
MM		 1520 sdb_label_count, \
1521 (LINE)); \
1522 sdb_label_count++; \
1523} while (0)
1524
1525#define PUT_SDB_FUNCTION_START(LINE)
1526
a642a781
RK		 1527#define PUT_SDB_FUNCTION_END(LINE) \
1528do { \
1529 extern FILE *asm_out_text_file; \
1530 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1531} while (0)
e75b25e7
MM		 1532
1533#define PUT_SDB_EPILOGUE_END(NAME)
1534
cc694a81
DE		 1535#define PUT_SDB_SRC_FILE(FILENAME) \
1536do { \
1537 extern FILE *asm_out_text_file; \
1538 output_file_directive (asm_out_text_file, (FILENAME)); \
1539} while (0)
1540
e75b25e7
MM		 1541#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1542 sprintf ((BUFFER), ".%dfake", (NUMBER));
1543
ab78d4a8
MM		 1544/* Correct the offset of automatic variables and arguments. Note that
1545 the MIPS debug format wants all automatic variables and arguments
1546 to be in terms of the virtual frame pointer (stack pointer before
1547 any adjustment in the function), while the MIPS 3.0 linker wants
1548 the frame pointer to be the stack pointer after the initial
1549 adjustment. */
e75b25e7 1550
f5963e61
JL		 1551#define DEBUGGER_AUTO_OFFSET(X) \
1552 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1553#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1554 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
31c714e3
MM		 1555
1556/* Tell collect that the object format is ECOFF */
1557#ifndef OBJECT_FORMAT_ROSE
1558#define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1559#define EXTENDED_COFF /* ECOFF, not normal coff */
1560#endif
e75b25e7
MM		 1561\f
1562/* Target machine storage layout */
1563
1564/* Define this if most significant bit is lowest numbered
1565 in instructions that operate on numbered bit-fields.
1566*/
4851a75c 1567#define BITS_BIG_ENDIAN 0
e75b25e7 1568
987ba558 1569/* Define this if most significant byte of a word is the lowest numbered. */
96abdcb1 1570#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
e75b25e7 1571
987ba558 1572/* Define this if most significant word of a multiword number is the lowest. */
96abdcb1 1573#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
e75b25e7 1574
96abdcb1
ILT		 1575/* Define this to set the endianness to use in libgcc2.c, which can
1576 not depend on target_flags. */
1577#if !defined(MIPSEL) && !defined(__MIPSEL__)
1578#define LIBGCC2_WORDS_BIG_ENDIAN 1
e75b25e7 1579#else
96abdcb1 1580#define LIBGCC2_WORDS_BIG_ENDIAN 0
e75b25e7
MM		 1581#endif
1582
876c09d3 1583#define MAX_BITS_PER_WORD 64
e75b25e7
MM		 1584
1585/* Width of a word, in units (bytes). */
456f6501 1586#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
ef0e53ce 1587#define MIN_UNITS_PER_WORD 4
876c09d3
JW		 1588
1589/* For MIPS, width of a floating point register. */
456f6501 1590#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
e75b25e7 1591
3f26edaa
RS		 1592/* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1593 the next available register. */
1594#define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1595
1596/* The largest size of value that can be held in floating-point registers. */
4d72536e
RS		 1597#define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1598
1599/* The number of bytes in a double. */
1600#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
3f26edaa 1601
e75b25e7
MM		 1602/* A C expression for the size in bits of the type `int' on the
1603 target machine. If you don't define this, the default is one
1604 word. */
456f6501 1605#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
876c09d3
JW		 1606
1607/* Tell the preprocessor the maximum size of wchar_t. */
1608#ifndef MAX_WCHAR_TYPE_SIZE
1609#ifndef WCHAR_TYPE_SIZE
16c484c7 1610#define MAX_WCHAR_TYPE_SIZE 64
876c09d3
JW		 1611#endif
1612#endif
e75b25e7
MM		 1613
1614/* A C expression for the size in bits of the type `short' on the
1615 target machine. If you don't define this, the default is half a
1616 word. (If this would be less than one storage unit, it is
1617 rounded up to one unit.) */
1618#define SHORT_TYPE_SIZE 16
1619
1620/* A C expression for the size in bits of the type `long' on the
1621 target machine. If you don't define this, the default is one
1622 word. */
456f6501 1623#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
876c09d3 1624#define MAX_LONG_TYPE_SIZE 64
e75b25e7
MM		 1625
1626/* A C expression for the size in bits of the type `long long' on the
1627 target machine. If you don't define this, the default is two
1628 words. */
923d630e 1629#define LONG_LONG_TYPE_SIZE 64
e75b25e7 1630
e75b25e7
MM		 1631/* A C expression for the size in bits of the type `float' on the
1632 target machine. If you don't define this, the default is one
1633 word. */
1634#define FLOAT_TYPE_SIZE 32
1635
1636/* A C expression for the size in bits of the type `double' on the
1637 target machine. If you don't define this, the default is two
1638 words. */
1639#define DOUBLE_TYPE_SIZE 64
1640
1641/* A C expression for the size in bits of the type `long double' on
1642 the target machine. If you don't define this, the default is two
1643 words. */
1644#define LONG_DOUBLE_TYPE_SIZE 64
1645
1646/* Width in bits of a pointer.
1647 See also the macro `Pmode' defined below. */
1eeed24e 1648#ifndef POINTER_SIZE
456f6501 1649#define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1eeed24e 1650#endif
e75b25e7
MM		 1651
1652/* Allocation boundary (in *bits*) for storing pointers in memory. */
456f6501 1653#define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
e75b25e7
MM		 1654
1655/* Allocation boundary (in *bits*) for storing arguments in argument list. */
0b51254d
AO		 1656#define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1657 || mips_abi == ABI_64 \
1658 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
e75b25e7
MM		 1659
1660/* Allocation boundary (in *bits*) for the code of a function. */
1661#define FUNCTION_BOUNDARY 32
1662
1663/* Alignment of field after `int : 0' in a structure. */
9e95597a 1664#define EMPTY_FIELD_BOUNDARY 32
e75b25e7
MM		 1665
1666/* Every structure's size must be a multiple of this. */
1667/* 8 is observed right on a DECstation and on riscos 4.02. */
1668#define STRUCTURE_SIZE_BOUNDARY 8
1669
1670/* There is no point aligning anything to a rounder boundary than this. */
1671#define BIGGEST_ALIGNMENT 64
1672
31c714e3 1673/* Set this nonzero if move instructions will actually fail to work
e75b25e7 1674 when given unaligned data. */
31c714e3 1675#define STRICT_ALIGNMENT 1
e75b25e7
MM		 1676
1677/* Define this if you wish to imitate the way many other C compilers
1678 handle alignment of bitfields and the structures that contain
1679 them.
1680
1681 The behavior is that the type written for a bitfield (`int',
1682 `short', or other integer type) imposes an alignment for the
1683 entire structure, as if the structure really did contain an
1684 ordinary field of that type. In addition, the bitfield is placed
1685 within the structure so that it would fit within such a field,
1686 not crossing a boundary for it.
1687
1688 Thus, on most machines, a bitfield whose type is written as `int'
1689 would not cross a four-byte boundary, and would force four-byte
1690 alignment for the whole structure. (The alignment used may not
1691 be four bytes; it is controlled by the other alignment
1692 parameters.)
1693
1694 If the macro is defined, its definition should be a C expression;
1695 a nonzero value for the expression enables this behavior. */
1696
1697#define PCC_BITFIELD_TYPE_MATTERS 1
1698
1699/* If defined, a C expression to compute the alignment given to a
1700 constant that is being placed in memory. CONSTANT is the constant
1701 and ALIGN is the alignment that the object would ordinarily have.
1702 The value of this macro is used instead of that alignment to align
1703 the object.
1704
1705 If this macro is not defined, then ALIGN is used.
1706
1707 The typical use of this macro is to increase alignment for string
1708 constants to be word aligned so that `strcpy' calls that copy
1709 constants can be done inline. */
1710
1711#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1712 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
75131237 1713 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
e75b25e7
MM		 1714
1715/* If defined, a C expression to compute the alignment for a static
1716 variable. TYPE is the data type, and ALIGN is the alignment that
1717 the object would ordinarily have. The value of this macro is used
1718 instead of that alignment to align the object.
1719
1720 If this macro is not defined, then ALIGN is used.
1721
1722 One use of this macro is to increase alignment of medium-size
1723 data to make it all fit in fewer cache lines. Another is to
1724 cause character arrays to be word-aligned so that `strcpy' calls
1725 that copy constants to character arrays can be done inline. */
1726
1727#undef DATA_ALIGNMENT
1728#define DATA_ALIGNMENT(TYPE, ALIGN) \
1729 ((((ALIGN) < BITS_PER_WORD) \
1730 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1731 || TREE_CODE (TYPE) == UNION_TYPE \
1732 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1733
f5c8ac96
CP		 1734
1735/* Force right-alignment for small varargs in 32 bit little_endian mode */
1736
0e5a4ad8
EC		 1737#define PAD_VARARGS_DOWN (TARGET_64BIT \
1738 || mips_abi == ABI_MEABI \
1739 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
f5c8ac96 1740
e75b25e7
MM		 1741/* Define this macro if an argument declared as `char' or `short' in a
1742 prototype should actually be passed as an `int'. In addition to
1743 avoiding errors in certain cases of mismatch, it also makes for
987ba558 1744 better code on certain machines. */
e75b25e7 1745
cb560352 1746#define PROMOTE_PROTOTYPES 1
e75b25e7 1747
9a63901f
RK		 1748/* Define if operations between registers always perform the operation
1749 on the full register even if a narrower mode is specified. */
1750#define WORD_REGISTER_OPERATIONS
1751
1752/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1753 will either zero-extend or sign-extend. The value of this macro should
1754 be the code that says which one of the two operations is implicitly
7dac2f89 1755 done, NIL if none.
a872728c
JL		 1756
1757 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1758 moves. All other referces are zero extended. */
1759#define LOAD_EXTEND_OP(MODE) \
1760 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1761 ? SIGN_EXTEND : ZERO_EXTEND)
2bcb2ab3
GK		 1762
1763/* Define this macro if it is advisable to hold scalars in registers
7dac2f89 1764 in a wider mode than that declared by the program. In such cases,
2bcb2ab3
GK		 1765 the value is constrained to be within the bounds of the declared
1766 type, but kept valid in the wider mode. The signedness of the
1767 extension may differ from that of the type.
1768
1769 We promote any value smaller than SImode up to SImode. We don't
1770 want to promote to DImode when in 64 bit mode, because that would
1771 prevent us from using the faster SImode multiply and divide
1772 instructions. */
1773
1774#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1775 if (GET_MODE_CLASS (MODE) == MODE_INT \
1776 && GET_MODE_SIZE (MODE) < 4) \
1777 (MODE) = SImode;
1778
1779/* Define this if function arguments should also be promoted using the above
1780 procedure. */
1781
1782#define PROMOTE_FUNCTION_ARGS
1783
1784/* Likewise, if the function return value is promoted. */
1785
1786#define PROMOTE_FUNCTION_RETURN
e75b25e7
MM		 1787\f
1788/* Standard register usage. */
1789
1790/* Number of actual hardware registers.
1791 The hardware registers are assigned numbers for the compiler
1792 from 0 to just below FIRST_PSEUDO_REGISTER.
1793 All registers that the compiler knows about must be given numbers,
1794 even those that are not normally considered general registers.
1795
225b8835 1796 On the Mips, we have 32 integer registers, 32 floating point
b8eb88d0
ILT		 1797 registers, 8 condition code registers, and the special registers
1798 hi, lo, hilo, and rap. The 8 condition code registers are only
1799 used if mips_isa >= 4. The hilo register is only used in 64 bit
1800 mode. It represents a 64 bit value stored as two 32 bit values in
1801 the hi and lo registers; this is the result of the mult
1802 instruction. rap is a pointer to the stack where the return
1803 address reg ($31) was stored. This is needed for C++ exception
1804 handling. */
e75b25e7 1805
b8eb88d0 1806#define FIRST_PSEUDO_REGISTER 76
e75b25e7
MM		 1807
1808/* 1 for registers that have pervasive standard uses
1809 and are not available for the register allocator.
1810
1811 On the MIPS, see conventions, page D-2 */
1812
1813#define FIXED_REGISTERS \
1814{ \
1815 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1816 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1817 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1818 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
b8eb88d0 1819 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
e75b25e7
MM		 1820}
1821
1822
1823/* 1 for registers not available across function calls.
1824 These must include the FIXED_REGISTERS and also any
1825 registers that can be used without being saved.
1826 The latter must include the registers where values are returned
1827 and the register where structure-value addresses are passed.
1828 Aside from that, you can include as many other registers as you like. */
1829
1830#define CALL_USED_REGISTERS \
1831{ \
1832 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1833 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1834 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1835 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
b8eb88d0 1836 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
e75b25e7
MM		 1837}
1838
2ca2d9ee
EC		 1839/* Like `CALL_USED_REGISTERS' but used to overcome a historical
1840 problem which makes CALL_USED_REGISTERS *always* include
1841 all the FIXED_REGISTERS. Until this problem has been
1842 resolved this macro can be used to overcome this situation.
1843 In particular, block_propagate() requires this list
1844 be acurate, or we can remove registers which should be live.
1845 This macro is used in regs_invalidated_by_call. */
1846
1847
1848#define CALL_REALLY_USED_REGISTERS \
1849{ /* General registers. */ \
1850 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1851 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1852 /* Floating-point registers. */ \
1853 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1854 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1855 /* Others. */ \
1856 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1857}
e75b25e7
MM		 1858
1859/* Internal macros to classify a register number as to whether it's a
1860 general purpose register, a floating point register, a
516a2dfd 1861 multiply/divide register, or a status register. */
e75b25e7
MM		 1862
1863#define GP_REG_FIRST 0
1864#define GP_REG_LAST 31
1865#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1866#define GP_DBX_FIRST 0
1867
1868#define FP_REG_FIRST 32
1869#define FP_REG_LAST 63
1870#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1871#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1872
1873#define MD_REG_FIRST 64
225b8835 1874#define MD_REG_LAST 66
e75b25e7
MM		 1875#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1876
225b8835 1877#define ST_REG_FIRST 67
b8eb88d0 1878#define ST_REG_LAST 74
e75b25e7
MM		 1879#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1880
b8eb88d0 1881#define RAP_REG_NUM 75
39dffea3 1882
e75b25e7
MM		 1883#define AT_REGNUM (GP_REG_FIRST + 1)
1884#define HI_REGNUM (MD_REG_FIRST + 0)
1885#define LO_REGNUM (MD_REG_FIRST + 1)
225b8835 1886#define HILO_REGNUM (MD_REG_FIRST + 2)
b8eb88d0
ILT		 1887
1888/* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1889 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1890 should be used instead. */
e75b25e7
MM		 1891#define FPSW_REGNUM ST_REG_FIRST
1892
75131237
RK		 1893#define GP_REG_P(REGNO) \
1894 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
2bcb2ab3
GK		 1895#define M16_REG_P(REGNO) \
1896 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
75131237
RK		 1897#define FP_REG_P(REGNO) \
1898 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1899#define MD_REG_P(REGNO) \
1900 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1901#define ST_REG_P(REGNO) \
1902 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
e75b25e7 1903
e75b25e7
MM		 1904/* Return number of consecutive hard regs needed starting at reg REGNO
1905 to hold something of mode MODE.
1906 This is ordinarily the length in words of a value of mode MODE
1907 but can be less for certain modes in special long registers.
1908
1909 On the MIPS, all general registers are one word long. Except on
1910 the R4000 with the FR bit set, the floating point uses register
956d6950 1911 pairs, with the second register not being allocable. */
e75b25e7 1912
0e5a4ad8 1913#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
e75b25e7
MM		 1914
1915/* Value is 1 if hard register REGNO can hold a value of machine-mode
876c09d3
JW		 1916 MODE. In 32 bit mode, require that DImode and DFmode be in even
1917 registers. For DImode, this makes some of the insns easier to
1918 write, since you don't have to worry about a DImode value in
1919 registers 3 & 4, producing a result in 4 & 5.
e75b25e7
MM		 1920
1921 To make the code simpler HARD_REGNO_MODE_OK now just references an
1922 array built in override_options. Because machmodes.h is not yet
1923 included before this file is processed, the MODE bound can't be
1924 expressed here. */
1925
1926extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1927
1928#define HARD_REGNO_MODE_OK(REGNO, MODE) \
1929 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1930
1931/* Value is 1 if it is a good idea to tie two pseudo registers
1932 when one has mode MODE1 and one has mode MODE2.
1933 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1934 for any hard reg, then this must be 0 for correct output. */
1935#define MODES_TIEABLE_P(MODE1, MODE2) \
1936 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1937 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1938 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1939 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1940
1941/* MIPS pc is not overloaded on a register. */
1942/* #define PC_REGNUM xx */
1943
1944/* Register to use for pushing function arguments. */
0fb5ac6f 1945#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
e75b25e7 1946
97116296
ILT		 1947/* Offset from the stack pointer to the first available location. Use
1948 the default value zero. */
1949/* #define STACK_POINTER_OFFSET 0 */
e75b25e7 1950
2bcb2ab3
GK		 1951/* Base register for access to local variables of the function. We
1952 pretend that the frame pointer is $1, and then eliminate it to
1953 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1954 a fixed register, and will not be used for anything else. */
1955#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1956
0ff83799
MM		 1957/* Temporary scratch register for use by the assembler. */
1958#define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1959
2bcb2ab3
GK		 1960/* $30 is not available on the mips16, so we use $17 as the frame
1961 pointer. */
1962#define HARD_FRAME_POINTER_REGNUM \
1963 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
e75b25e7
MM		 1964
1965/* Value should be nonzero if functions must have frame pointers.
1966 Zero means the frame pointer need not be set up (and parms
1967 may be accessed via the stack pointer) in functions that seem suitable.
1968 This is computed in `reload', in reload1.c. */
1969#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1970
1971/* Base register for access to arguments of the function. */
ab78d4a8 1972#define ARG_POINTER_REGNUM GP_REG_FIRST
e75b25e7 1973
39dffea3
JW		 1974/* Fake register that holds the address on the stack of the
1975 current function's return address. */
1976#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1977
e75b25e7 1978/* Register in which static-chain is passed to a function. */
0fb5ac6f 1979#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
e75b25e7 1980
1154b096
MM		 1981/* If the structure value address is passed in a register, then
1982 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1983/* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1984
1985/* If the structure value address is not passed in a register, define
1986 `STRUCT_VALUE' as an expression returning an RTX for the place
1987 where the address is passed. If it returns 0, the address is
1988 passed as an "invisible" first argument. */
f58cfbfb 1989#define STRUCT_VALUE 0
e75b25e7
MM		 1990
1991/* Mips registers used in prologue/epilogue code when the stack frame
1992 is larger than 32K bytes. These registers must come from the
1993 scratch register set, and not used for passing and returning
1994 arguments and any other information used in the calling sequence
516a2dfd
JW		 1995 (such as pic). Must start at 12, since t0/t3 are parameter passing
1996 registers in the 64 bit ABI. */
7bea35e7 1997
516a2dfd
JW		 1998#define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1999#define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
e75b25e7
MM		 2000
2001/* Define this macro if it is as good or better to call a constant
2002 function address than to call an address kept in a register. */
2003#define NO_FUNCTION_CSE 1
2004
2005/* Define this macro if it is as good or better for a function to
2006 call itself with an explicit address than to call an address
2007 kept in a register. */
2008#define NO_RECURSIVE_FUNCTION_CSE 1
2009
2010/* The register number of the register used to address a table of
2011 static data addresses in memory. In some cases this register is
7dac2f89 2012 defined by a processor's "application binary interface" (ABI).
e75b25e7
MM		 2013 When this macro is defined, RTL is generated for this register
2014 once, as with the stack pointer and frame pointer registers. If
2015 this macro is not defined, it is up to the machine-dependent
2016 files to allocate such a register (if necessary). */
0fb5ac6f 2017#define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
e75b25e7 2018
24e214e3 2019#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
e75b25e7
MM		 2020\f
2021/* Define the classes of registers for register constraints in the
2022 machine description. Also define ranges of constants.
2023
2024 One of the classes must always be named ALL_REGS and include all hard regs.
2025 If there is more than one class, another class must be named NO_REGS
2026 and contain no registers.
2027
2028 The name GENERAL_REGS must be the name of a class (or an alias for
2029 another name such as ALL_REGS). This is the class of registers
2030 that is allowed by "g" or "r" in a register constraint.
2031 Also, registers outside this class are allocated only when
2032 instructions express preferences for them.
2033
2034 The classes must be numbered in nondecreasing order; that is,
2035 a larger-numbered class must never be contained completely
2036 in a smaller-numbered class.
2037
2038 For any two classes, it is very desirable that there be another
2039 class that represents their union. */
2040
2041enum reg_class
2042{
2043 NO_REGS, /* no registers in set */
2bcb2ab3
GK		 2044 M16_NA_REGS, /* mips16 regs not used to pass args */
2045 M16_REGS, /* mips16 directly accessible registers */
2046 T_REG, /* mips16 T register ($24) */
2047 M16_T_REGS, /* mips16 registers plus T register */
e75b25e7
MM		 2048 GR_REGS, /* integer registers */
2049 FP_REGS, /* floating point registers */
2050 HI_REG, /* hi register */
2051 LO_REG, /* lo register */
225b8835 2052 HILO_REG, /* hilo register pair for 64 bit mode mult */
e75b25e7 2053 MD_REGS, /* multiply/divide registers (hi/lo) */
e4f5c5d6
KR		 2054 HI_AND_GR_REGS, /* union classes */
2055 LO_AND_GR_REGS,
2056 HILO_AND_GR_REGS,
ab093b81 2057 HI_AND_FP_REGS,
e75b25e7
MM		 2058 ST_REGS, /* status registers (fp status) */
2059 ALL_REGS, /* all registers */
2060 LIM_REG_CLASSES /* max value + 1 */
2061};
2062
2063#define N_REG_CLASSES (int) LIM_REG_CLASSES
2064
2065#define GENERAL_REGS GR_REGS
2066
2067/* An initializer containing the names of the register classes as C
2068 string constants. These names are used in writing some of the
2069 debugging dumps. */
2070
2071#define REG_CLASS_NAMES \
2072{ \
2073 "NO_REGS", \
2bcb2ab3
GK		 2074 "M16_NA_REGS", \
2075 "M16_REGS", \
2076 "T_REG", \
2077 "M16_T_REGS", \
e75b25e7
MM		 2078 "GR_REGS", \
2079 "FP_REGS", \
2080 "HI_REG", \
2081 "LO_REG", \
225b8835 2082 "HILO_REG", \
e75b25e7 2083 "MD_REGS", \
e4f5c5d6
KR		 2084 "HI_AND_GR_REGS", \
2085 "LO_AND_GR_REGS", \
2086 "HILO_AND_GR_REGS", \
ab093b81 2087 "HI_AND_FP_REGS", \
e75b25e7
MM		 2088 "ST_REGS", \
2089 "ALL_REGS" \
2090}
2091
2092/* An initializer containing the contents of the register classes,
2093 as integers which are bit masks. The Nth integer specifies the
2094 contents of class N. The way the integer MASK is interpreted is
2095 that register R is in the class if `MASK & (1 << R)' is 1.
2096
2097 When the machine has more than 32 registers, an integer does not
2098 suffice. Then the integers are replaced by sub-initializers,
2099 braced groupings containing several integers. Each
2100 sub-initializer must be suitable as an initializer for the type
2101 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2102
2103#define REG_CLASS_CONTENTS \
2104{ \
2105 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2bcb2ab3
GK		 2106 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2107 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2108 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2109 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
e75b25e7
MM		 2110 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
2111 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
2e7bfcec
MM		 2112 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
2113 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
225b8835 2114 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
e75b25e7 2115 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
e4f5c5d6
KR		 2116 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
2117 { 0xffffffff, 0x00000000, 0x00000002 }, \
2118 { 0xffffffff, 0x00000000, 0x00000004 }, \
ab093b81 2119 { 0x00000000, 0xffffffff, 0x00000001 }, \
b8eb88d0
ILT		 2120 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
2121 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
e75b25e7
MM		 2122}
2123
2124
2125/* A C expression whose value is a register class containing hard
2126 register REGNO. In general there is more that one such class;
2127 choose a class which is "minimal", meaning that no smaller class
2128 also contains the register. */
2129
8b60264b 2130extern const enum reg_class mips_regno_to_class[];
e75b25e7
MM		 2131
2132#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2133
2134/* A macro whose definition is the name of the class to which a
2135 valid base register must belong. A base register is one used in
2136 an address which is the register value plus a displacement. */
2137
2bcb2ab3 2138#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
e75b25e7
MM		 2139
2140/* A macro whose definition is the name of the class to which a
2141 valid index register must belong. An index register is one used
2142 in an address where its value is either multiplied by a scale
2143 factor or added to another register (as well as added to a
2144 displacement). */
2145
876c09d3 2146#define INDEX_REG_CLASS NO_REGS
e75b25e7 2147
2bcb2ab3
GK		 2148/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2149 registers explicitly used in the rtl to be used as spill registers
2150 but prevents the compiler from extending the lifetime of these
987ba558 2151 registers. */
2bcb2ab3
GK		 2152
2153#define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2154
2155/* This macro is used later on in the file. */
2156#define GR_REG_CLASS_P(CLASS) \
2157 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2158 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2159
2160/* REG_ALLOC_ORDER is to order in which to allocate registers. This
2161 is the default value (allocate the registers in numeric order). We
2162 define it just so that we can override it for the mips16 target in
2163 ORDER_REGS_FOR_LOCAL_ALLOC. */
2164
2165#define REG_ALLOC_ORDER \
2166{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2167 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2168 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2169 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2170 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
2171}
2172
2173/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2174 to be rearranged based on a particular function. On the mips16, we
2175 want to allocate $24 (T_REG) before other registers for
2176 instructions for which it is possible. */
2177
2178#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
e75b25e7
MM		 2179
2180/* REGISTER AND CONSTANT CLASSES */
2181
2182/* Get reg_class from a letter such as appears in the machine
2183 description.
2184
2185 DEFINED REGISTER CLASSES:
2186
2187 'd' General (aka integer) registers
2bcb2ab3
GK		 2188 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2189 'y' General registers (in both mips16 and non mips16 mode)
2190 'e' mips16 non argument registers (M16_NA_REGS)
2191 't' mips16 temporary register ($24)
e75b25e7
MM		 2192 'f' Floating point registers
2193 'h' Hi register
2194 'l' Lo register
34b650b3 2195 'x' Multiply/divide registers
225b8835
ILT		 2196 'a' HILO_REG
2197 'z' FP Status register
2198 'b' All registers */
e75b25e7 2199
f540a7d3 2200extern enum reg_class mips_char_to_class[256];
e75b25e7 2201
8f54374e 2202#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
e75b25e7
MM		 2203
2204/* The letters I, J, K, L, M, N, O, and P in a register constraint
2205 string can be used to stand for particular ranges of immediate
2206 operands. This macro defines what the ranges are. C is the
2207 letter, and VALUE is a constant value. Return 1 if VALUE is
2208 in the range specified by C. */
2209
2210/* For MIPS:
2211
2212 `I' is used for the range of constants an arithmetic insn can
2213 actually contain (16 bits signed integers).
2214
2215 `J' is used for the range which is just zero (ie, $r0).
2216
2217 `K' is used for the range of constants a logical insn can actually
2218 contain (16 bit zero-extended integers).
2219
2220 `L' is used for the range of constants that be loaded with lui
2221 (ie, the bottom 16 bits are zero).
2222
2223 `M' is used for the range of constants that take two words to load
2224 (ie, not matched by `I', `K', and `L').
2225
2bcb2ab3 2226 `N' is used for negative 16 bit constants other than -65536.
e75b25e7 2227
2bcb2ab3 2228 `O' is a 15 bit signed integer.
e75b25e7
MM		 2229
2230 `P' is used for positive 16 bit constants. */
2231
516a2dfd
JW		 2232#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2233#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
e75b25e7
MM		 2234
2235#define CONST_OK_FOR_LETTER_P(VALUE, C) \
516a2dfd 2236 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
e75b25e7 2237 : (C) == 'J' ? ((VALUE) == 0) \
516a2dfd 2238 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
876c09d3
JW		 2239 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2240 && (((VALUE) & ~2147483647) == 0 \
2241 || ((VALUE) & ~2147483647) == ~2147483647)) \
99cbc4b0
MM		 2242 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2243 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
876c09d3
JW		 2244 && (((VALUE) & 0x0000ffff) != 0 \
2245 || (((VALUE) & ~2147483647) != 0 \
2246 && ((VALUE) & ~2147483647) != ~2147483647))) \
2bcb2ab3
GK		 2247 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2248 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
99cbc4b0 2249 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
e75b25e7
MM		 2250 : 0)
2251
2252/* Similar, but for floating constants, and defining letters G and H.
2253 Here VALUE is the CONST_DOUBLE rtx itself. */
2254
2255/* For Mips
2256
2257 'G' : Floating point 0 */
2258
2259#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2260 ((C) == 'G' \
876c09d3 2261 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
e75b25e7
MM		 2262
2263/* Letters in the range `Q' through `U' may be defined in a
7dac2f89 2264 machine-dependent fashion to stand for arbitrary operand types.
e75b25e7
MM		 2265 The machine description macro `EXTRA_CONSTRAINT' is passed the
2266 operand as its first argument and the constraint letter as its
2267 second operand.
2268
2bcb2ab3 2269 `Q' is for mips16 GP relative constants
31c714e3 2270 `R' is for memory references which take 1 word for the instruction.
2bcb2ab3
GK		 2271 `S' is for references to extern items which are PIC for OSF/rose.
2272 `T' is for memory addresses that can be used to load two words. */
e75b25e7
MM		 2273
2274#define EXTRA_CONSTRAINT(OP,CODE) \
2bcb2ab3
GK		 2275 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2276 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2277 && mips16_gp_offset_p (OP)) \
2278 : (GET_CODE (OP) != MEM) ? FALSE \
e75b25e7 2279 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
31c714e3
MM		 2280 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2281 && HALF_PIC_ADDRESS_P (OP)) \
e75b25e7
MM		 2282 : FALSE)
2283
2284/* Given an rtx X being reloaded into a reg required to be
2285 in class CLASS, return the class of reg to actually use.
2286 In general this is just CLASS; but on some machines
2287 in some cases it is preferable to use a more restrictive class. */
2288
2289#define PREFERRED_RELOAD_CLASS(X,CLASS) \
876c09d3 2290 ((CLASS) != ALL_REGS \
2bcb2ab3
GK		 2291 ? (! TARGET_MIPS16 \
2292 ? (CLASS) \
2293 : ((CLASS) != GR_REGS \
2294 ? (CLASS) \
2295 : M16_REGS)) \
876c09d3
JW		 2296 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2297 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2bcb2ab3
GK		 2298 ? (TARGET_SOFT_FLOAT \
2299 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2300 : FP_REGS) \
876c09d3
JW		 2301 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2302 || GET_MODE (X) == VOIDmode) \
2bcb2ab3 2303 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
876c09d3 2304 : (CLASS))))
e75b25e7 2305
0fb5ac6f
MM		 2306/* Certain machines have the property that some registers cannot be
2307 copied to some other registers without using memory. Define this
2308 macro on those machines to be a C expression that is non-zero if
2309 objects of mode MODE in registers of CLASS1 can only be copied to
2310 registers of class CLASS2 by storing a register of CLASS1 into
2311 memory and loading that memory location into a register of CLASS2.
2312
2313 Do not define this macro if its value would always be zero. */
7b2e1077 2314#if 0
0fb5ac6f 2315#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2370b831
JW		 2316 ((!TARGET_DEBUG_H_MODE \
2317 && GET_MODE_CLASS (MODE) == MODE_INT \
2bcb2ab3
GK		 2318 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2319 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2370b831 2320 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2bcb2ab3
GK		 2321 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2322 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
7b2e1077 2323#endif
46299de9 2324/* The HI and LO registers can only be reloaded via the general
b8eb88d0
ILT		 2325 registers. Condition code registers can only be loaded to the
2326 general registers, and from the floating point registers. */
46299de9 2327
225b8835
ILT		 2328#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2329 mips_secondary_reload_class (CLASS, MODE, X, 1)
2330#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2331 mips_secondary_reload_class (CLASS, MODE, X, 0)
46299de9 2332
e75b25e7
MM		 2333/* Return the maximum number of consecutive registers
2334 needed to represent mode MODE in a register of class CLASS. */
2335
2336#define CLASS_MAX_NREGS(CLASS, MODE) \
b206a757 2337 ((CLASS) == FP_REGS \
e6f884cd
RS		 2338 ? FP_INC \
2339 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
e75b25e7 2340
87d9d860 2341/* If defined, gives a class of registers that cannot be used as the
ab093b81 2342 operand of a SUBREG that changes the mode of the object illegally.
ab093b81
RH		 2343 When FP regs are larger than integer regs... Er, anyone remember what
2344 goes wrong?
2345
2346 In little-endian mode, the hi-lo registers are numbered backwards,
2347 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
2348 word as intended. */
2349
2350#define CLASS_CANNOT_CHANGE_MODE \
2351 (TARGET_BIG_ENDIAN \
2352 ? (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS) \
2353 : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI_REG))
02188693
RH		 2354
2355/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2356
2357#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2358 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
e75b25e7
MM		 2359\f
2360/* Stack layout; function entry, exit and calling. */
2361
2362/* Define this if pushing a word on the stack
2363 makes the stack pointer a smaller address. */
2364#define STACK_GROWS_DOWNWARD
2365
2366/* Define this if the nominal address of the stack frame
2367 is at the high-address end of the local variables;
2368 that is, each additional local variable allocated
2369 goes at a more negative offset in the frame. */
ab78d4a8 2370/* #define FRAME_GROWS_DOWNWARD */
e75b25e7
MM		 2371
2372/* Offset within stack frame to start allocating local variables at.
2373 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2374 first local allocated. Otherwise, it is the offset to the BEGINNING
2375 of the first local allocated. */
24e214e3
JW		 2376#define STARTING_FRAME_OFFSET \
2377 (current_function_outgoing_args_size \
2378 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
ab78d4a8
MM		 2379
2380/* Offset from the stack pointer register to an item dynamically
2381 allocated on the stack, e.g., by `alloca'.
2382
2383 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2384 length of the outgoing arguments. The default is correct for most
2385 machines. See `function.c' for details.
2386
51bdc4d3
MM		 2387 The MIPS ABI states that functions which dynamically allocate the
2388 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2389 we are trying to create a second frame pointer to the function, so
2390 allocate some stack space to make it happy.
ab78d4a8 2391
51bdc4d3
MM		 2392 However, the linker currently complains about linking any code that
2393 dynamically allocates stack space, and there seems to be a bug in
2394 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2395
2396#if 0
ab78d4a8
MM		 2397#define STACK_DYNAMIC_OFFSET(FUNDECL) \
2398 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2399 ? 4*UNITS_PER_WORD \
2400 : current_function_outgoing_args_size)
51bdc4d3 2401#endif
e75b25e7 2402
39dffea3
JW		 2403/* The return address for the current frame is in r31 is this is a leaf
2404 function. Otherwise, it is on the stack. It is at a variable offset
2405 from sp/fp/ap, so we define a fake hard register rap which is a
2406 poiner to the return address on the stack. This always gets eliminated
2407 during reload to be either the frame pointer or the stack pointer plus
2408 an offset. */
2409
2410/* ??? This definition fails for leaf functions. There is currently no
2411 general solution for this problem. */
2412
2413/* ??? There appears to be no way to get the return address of any previous
2414 frame except by disassembling instructions in the prologue/epilogue.
2415 So currently we support only the current frame. */
2416
07e2e444
AO		 2417#define RETURN_ADDR_RTX(count, frame) \
2418 (((count) == 0) \
2419 ? (leaf_function_p () \
2420 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
2421 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
2422 RETURN_ADDRESS_POINTER_REGNUM))) \
24ba333f 2423 : (rtx) 0)
39dffea3 2424
7f48c9e1
AO		 2425/* Since the mips16 ISA mode is encoded in the least-significant bit
2426 of the address, mask it off return addresses for purposes of
2427 finding exception handling regions. */
2428
2429#define MASK_RETURN_ADDR GEN_INT (-2)
2430
2431/* Similarly, don't use the least-significant bit to tell pointers to
2432 code from vtable index. */
2433
2434#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2435
e75b25e7
MM		 2436/* Structure to be filled in by compute_frame_size with register
2437 save masks, and offsets for the current function. */
2438
2439struct mips_frame_info
2440{
7bea35e7
MM		 2441 long total_size; /* # bytes that the entire frame takes up */
2442 long var_size; /* # bytes that variables take up */
2443 long args_size; /* # bytes that outgoing arguments take up */
2444 long extra_size; /* # bytes of extra gunk */
2445 int gp_reg_size; /* # bytes needed to store gp regs */
2446 int fp_reg_size; /* # bytes needed to store fp regs */
2447 long mask; /* mask of saved gp registers */
2448 long fmask; /* mask of saved fp registers */
2449 long gp_save_offset; /* offset from vfp to store gp registers */
2450 long fp_save_offset; /* offset from vfp to store fp registers */
2451 long gp_sp_offset; /* offset from new sp to store gp registers */
2452 long fp_sp_offset; /* offset from new sp to store fp registers */
2453 int initialized; /* != 0 if frame size already calculated */
2454 int num_gp; /* number of gp registers saved */
2455 int num_fp; /* number of fp registers saved */
2bcb2ab3 2456 long insns_len; /* length of insns; mips16 only */
e75b25e7
MM		 2457};
2458
2459extern struct mips_frame_info current_frame_info;
2460
ab78d4a8
MM		 2461/* If defined, this macro specifies a table of register pairs used to
2462 eliminate unneeded registers that point into the stack frame. If
2463 it is not defined, the only elimination attempted by the compiler
2464 is to replace references to the frame pointer with references to
2465 the stack pointer.
2466
2467 The definition of this macro is a list of structure
2468 initializations, each of which specifies an original and
2469 replacement register.
2470
2471 On some machines, the position of the argument pointer is not
2472 known until the compilation is completed. In such a case, a
7dac2f89 2473 separate hard register must be used for the argument pointer.
ab78d4a8
MM		 2474 This register can be eliminated by replacing it with either the
2475 frame pointer or the argument pointer, depending on whether or not
2476 the frame pointer has been eliminated.
2477
2478 In this case, you might specify:
2479 #define ELIMINABLE_REGS \
2480 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2481 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2482 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2483
2484 Note that the elimination of the argument pointer with the stack
2bcb2ab3
GK		 2485 pointer is specified first since that is the preferred elimination.
2486
2487 The eliminations to $17 are only used on the mips16. See the
2488 definition of HARD_FRAME_POINTER_REGNUM. */
ab78d4a8
MM		 2489
2490#define ELIMINABLE_REGS \
2491{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2bcb2ab3
GK		 2492 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2493 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
39dffea3 2494 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2bcb2ab3
GK		 2495 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2496 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2497 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2498 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2499 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
ab78d4a8 2500
ab78d4a8
MM		 2501/* A C expression that returns non-zero if the compiler is allowed to
2502 try to replace register number FROM-REG with register number
2503 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2504 defined, and will usually be the constant 1, since most of the
2505 cases preventing register elimination are things that the compiler
2bcb2ab3
GK		 2506 already knows about.
2507
365ca18b
GK		 2508 When not in mips16 and mips64, we can always eliminate to the
2509 frame pointer. We can eliminate to the stack pointer unless
2510 a frame pointer is needed. In mips16 mode, we need a frame
2511 pointer for a large frame; otherwise, reload may be unable
2512 to compute the address of a local variable, since there is
2513 no way to add a large constant to the stack pointer
2514 without using a temporary register.
2515
2516 In mips16, for some instructions (eg lwu), we can't eliminate the
2517 frame pointer for the stack pointer. These instructions are
2518 only generated in TARGET_64BIT mode.
2519 */
ab78d4a8
MM		 2520
2521#define CAN_ELIMINATE(FROM, TO) \
cfb773f9 2522 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
07e2e444
AO		 2523 && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
2524 || (TO) == HARD_FRAME_POINTER_REGNUM)) \
cfb773f9
AO		 2525 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2526 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2527 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2528 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2529 && (! TARGET_MIPS16 \
2530 || compute_frame_size (get_frame_size ()) < 32768)))))
ab78d4a8
MM		 2531
2532/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2533 specifies the initial difference between the specified pair of
2534 registers. This macro must be defined if `ELIMINABLE_REGS' is
2535 defined. */
2536
2537#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2538{ compute_frame_size (get_frame_size ()); \
2bcb2ab3
GK		 2539 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2540 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2541 (OFFSET) = - current_function_outgoing_args_size; \
2542 else if ((FROM) == FRAME_POINTER_REGNUM) \
ab78d4a8 2543 (OFFSET) = 0; \
2bcb2ab3
GK		 2544 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2545 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2546 (OFFSET) = (current_frame_info.total_size \
2547 - current_function_outgoing_args_size \
a53f72db
GRK		 2548 - ((mips_abi != ABI_32 \
2549 && mips_abi != ABI_O64 \
2550 && mips_abi != ABI_EABI) \
2bcb2ab3
GK		 2551 ? current_function_pretend_args_size \
2552 : 0)); \
2553 else if ((FROM) == ARG_POINTER_REGNUM) \
a2ef6e41 2554 (OFFSET) = (current_frame_info.total_size \
a53f72db
GRK		 2555 - ((mips_abi != ABI_32 \
2556 && mips_abi != ABI_O64 \
2557 && mips_abi != ABI_EABI) \
a2ef6e41
RK		 2558 ? current_function_pretend_args_size \
2559 : 0)); \
c9b4de06
JW		 2560 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2561 so we must add 4 bytes to the offset to get the right value. */ \
2bcb2ab3 2562 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
973838fd 2563 { \
07e2e444
AO		 2564 (OFFSET) = current_frame_info.gp_sp_offset \
2565 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2566 * (BYTES_BIG_ENDIAN != 0)); \
2567 if (TARGET_MIPS16 && (TO) != STACK_POINTER_REGNUM) \
2568 (OFFSET) -= current_function_outgoing_args_size; \
973838fd 2569 } \
a6ffcb2a
KG		 2570 else \
2571 abort(); \
ab78d4a8
MM		 2572}
2573
e75b25e7
MM		 2574/* If we generate an insn to push BYTES bytes,
2575 this says how many the stack pointer really advances by.
8aeea6e6 2576 On the VAX, sp@- in a byte insn really pushes a word. */
e75b25e7
MM		 2577
2578/* #define PUSH_ROUNDING(BYTES) 0 */
2579
2580/* If defined, the maximum amount of space required for outgoing
2581 arguments will be computed and placed into the variable
2582 `current_function_outgoing_args_size'. No space will be pushed
2583 onto the stack for each call; instead, the function prologue
2584 should increase the stack frame size by this amount.
2585
2586 It is not proper to define both `PUSH_ROUNDING' and
2587 `ACCUMULATE_OUTGOING_ARGS'. */
f73ad30e 2588#define ACCUMULATE_OUTGOING_ARGS 1
e75b25e7 2589
6cb6c3b3
MM		 2590/* Offset from the argument pointer register to the first argument's
2591 address. On some machines it may depend on the data type of the
2592 function.
e75b25e7 2593
6cb6c3b3 2594 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
39282292
MM		 2595 the first argument's address.
2596
2597 On the MIPS, we must skip the first argument position if we are
876c09d3 2598 returning a structure or a union, to account for its address being
305aa9e2
MM		 2599 passed in $4. However, at the current time, this produces a compiler
2600 that can't bootstrap, so comment it out for now. */
e75b25e7 2601
305aa9e2 2602#if 0
6cb6c3b3
MM		 2603#define FIRST_PARM_OFFSET(FNDECL) \
2604 (FNDECL != 0 \
2605 && TREE_TYPE (FNDECL) != 0 \
2606 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2607 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
39282292
MM		 2608 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2609 ? UNITS_PER_WORD \
2610 : 0)
305aa9e2
MM		 2611#else
2612#define FIRST_PARM_OFFSET(FNDECL) 0
2613#endif
e75b25e7
MM		 2614
2615/* When a parameter is passed in a register, stack space is still
2616 allocated for it. For the MIPS, stack space must be allocated, cf
2617 Asm Lang Prog Guide page 7-8.
2618
2619 BEWARE that some space is also allocated for non existing arguments
2620 in register. In case an argument list is of form GF used registers
2621 are a0 (a2,a3), but we should push over a1... */
2622
516a2dfd
JW		 2623#define REG_PARM_STACK_SPACE(FNDECL) \
2624 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
e75b25e7
MM		 2625
2626/* Define this if it is the responsibility of the caller to
7dac2f89 2627 allocate the area reserved for arguments passed in registers.
e75b25e7 2628 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
7dac2f89 2629 of this macro is to determine whether the space is included in
e75b25e7
MM		 2630 `current_function_outgoing_args_size'. */
2631#define OUTGOING_REG_PARM_STACK_SPACE
2632
2633/* Align stack frames on 64 bits (Double Word ). */
d1c17572 2634#ifndef STACK_BOUNDARY
e75b25e7 2635#define STACK_BOUNDARY 64
d1c17572 2636#endif
e75b25e7 2637
876c09d3 2638/* Make sure 4 words are always allocated on the stack. */
e75b25e7
MM		 2639
2640#ifndef STACK_ARGS_ADJUST
2641#define STACK_ARGS_ADJUST(SIZE) \
2642{ \
876c09d3
JW		 2643 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2644 SIZE.constant = 4 * UNITS_PER_WORD; \
e75b25e7
MM		 2645}
2646#endif
2647
2648\f
2649/* A C expression that should indicate the number of bytes of its
38e01259 2650 own arguments that a function pops on returning, or 0
e75b25e7
MM		 2651 if the function pops no arguments and the caller must therefore
2652 pop them all after the function returns.
2653
8b109b37
RK		 2654 FUNDECL is the declaration node of the function (as a tree).
2655
e75b25e7
MM		 2656 FUNTYPE is a C variable whose value is a tree node that
2657 describes the function in question. Normally it is a node of
2658 type `FUNCTION_TYPE' that describes the data type of the function.
2659 From this it is possible to obtain the data types of the value
2660 and arguments (if known).
2661
2662 When a call to a library function is being considered, FUNTYPE
2663 will contain an identifier node for the library function. Thus,
2664 if you need to distinguish among various library functions, you
2665 can do so by their names. Note that "library function" in this
2666 context means a function used to perform arithmetic, whose name
2667 is known specially in the compiler and was not mentioned in the
2668 C code being compiled.
2669
2670 STACK-SIZE is the number of bytes of arguments passed on the
2671 stack. If a variable number of bytes is passed, it is zero, and
2672 argument popping will always be the responsibility of the
2673 calling function. */
2674
8b109b37 2675#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
e75b25e7
MM		 2676
2677
2678/* Symbolic macros for the registers used to return integer and floating
2679 point values. */
2680
2681#define GP_RETURN (GP_REG_FIRST + 2)
2682#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2683
2684/* Symbolic macros for the first/last argument registers. */
2685
2686#define GP_ARG_FIRST (GP_REG_FIRST + 4)
2687#define GP_ARG_LAST (GP_REG_FIRST + 7)
2688#define FP_ARG_FIRST (FP_REG_FIRST + 12)
2689#define FP_ARG_LAST (FP_REG_FIRST + 15)
2690
2691#define MAX_ARGS_IN_REGISTERS 4
2692
2693/* Define how to find the value returned by a library function
2bcb2ab3
GK		 2694 assuming the value has mode MODE. Because we define
2695 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2696 PROMOTE_MODE does. */
e75b25e7 2697
c6e6f5c1
RH		 2698#define LIBCALL_VALUE(MODE) \
2699 mips_function_value (NULL_TREE, NULL, (MODE))
e75b25e7
MM		 2700
2701/* Define how to find the value returned by a function.
2702 VALTYPE is the data type of the value (as a tree).
2703 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2704 otherwise, FUNC is 0. */
2705
c6e6f5c1
RH		 2706#define FUNCTION_VALUE(VALTYPE, FUNC) \
2707 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
e75b25e7
MM		 2708
2709/* 1 if N is a possible register number for a function value.
2710 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2711 Currently, R2 and F0 are only implemented here (C has no complex type) */
2712
2713#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2714
46af8e31
JW		 2715/* 1 if N is a possible register number for function argument passing.
2716 We have no FP argument registers when soft-float. When FP registers
2717 are 32 bits, we can't directly reference the odd numbered ones. */
2718
2719#define FUNCTION_ARG_REGNO_P(N) \
e6f884cd
RS		 2720 ((((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2721 || ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST)) \
2722 && !fixed_regs[N])
e75b25e7
MM		 2723
2724/* A C expression which can inhibit the returning of certain function
2725 values in registers, based on the type of value. A nonzero value says
2726 to return the function value in memory, just as large structures are
2727 always returned. Here TYPE will be a C expression of type
2728 `tree', representing the data type of the value.
2729
e14fa9c4
DE		 2730 Note that values of mode `BLKmode' must be explicitly
2731 handled by this macro. Also, the option `-fpcc-struct-return'
e75b25e7
MM		 2732 takes effect regardless of this macro. On most systems, it is
2733 possible to leave the macro undefined; this causes a default
e14fa9c4
DE		 2734 definition to be used, whose value is the constant 1 for BLKmode
2735 values, and 0 otherwise.
e75b25e7
MM		 2736
2737 GCC normally converts 1 byte structures into chars, 2 byte
2738 structs into shorts, and 4 byte structs into ints, and returns
2739 them this way. Defining the following macro overrides this,
2740 to give us MIPS cc compatibility. */
2741
2742#define RETURN_IN_MEMORY(TYPE) \
54401342 2743 mips_return_in_memory (TYPE)
4d72536e
RS		 2744
2745#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2746 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2747 (TYPE), (NO_RTL))
e75b25e7 2748\f
e75b25e7
MM		 2749
2750#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2751
2752\f
2753/* Define a data type for recording info about an argument list
2754 during the scan of that argument list. This data type should
2755 hold all necessary information about the function itself
2756 and about the args processed so far, enough to enable macros
2757 such as FUNCTION_ARG to determine where the next arg should go.
2bcb2ab3 2758
4d72536e
RS		 2759 This structure has to cope with two different argument allocation
2760 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2761 first N words go in registers and the rest go on the stack. If I < N,
2762 the Ith word might go in Ith integer argument register or the
2763 Ith floating-point one. In some cases, it has to go in both (see
2764 function_arg). For these ABIs, we only need to remember the number
2765 of words passed so far.
2766
2767 The EABI instead allocates the integer and floating-point arguments
2768 separately. The first N words of FP arguments go in FP registers,
2769 the rest go on the stack. Likewise, the first N words of the other
2770 arguments go in integer registers, and the rest go on the stack. We
2771 need to maintain three counts: the number of integer registers used,
2772 the number of floating-point registers used, and the number of words
2773 passed on the stack.
2774
2775 We could keep separate information for the two ABIs (a word count for
2776 the standard ABIs, and three separate counts for the EABI). But it
2777 seems simpler to view the standard ABIs as forms of EABI that do not
2778 allocate floating-point registers.
2779
2780 So for the standard ABIs, the first N words are allocated to integer
2781 registers, and function_arg decides on an argument-by-argument basis
2782 whether that argument should really go in an integer register, or in
2783 a floating-point one. */
e75b25e7
MM		 2784
2785typedef struct mips_args {
4d72536e
RS		 2786 /* Always true for varargs functions. Otherwise true if at least
2787 one argument has been passed in an integer register. */
2788 int gp_reg_found;
2789
2790 /* The number of arguments seen so far. */
2791 unsigned int arg_number;
2792
2793 /* For EABI, the number of integer registers used so far. For other
2794 ABIs, the number of words passed in registers (whether integer
2795 or floating-point). */
bb63e5a0 2796 unsigned int num_gprs;
4d72536e
RS		 2797
2798 /* For EABI, the number of floating-point registers used so far. */
bb63e5a0 2799 unsigned int num_fprs;
4d72536e
RS		 2800
2801 /* The number of words passed on the stack. */
2802 unsigned int stack_words;
2803
2804 /* On the mips16, we need to keep track of which floating point
2805 arguments were passed in general registers, but would have been
2806 passed in the FP regs if this were a 32 bit function, so that we
2807 can move them to the FP regs if we wind up calling a 32 bit
2808 function. We record this information in fp_code, encoded in base
2809 four. A zero digit means no floating point argument, a one digit
2810 means an SFmode argument, and a two digit means a DFmode argument,
2811 and a three digit is not used. The low order digit is the first
2812 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2813 an SFmode argument. ??? A more sophisticated approach will be
2814 needed if MIPS_ABI != ABI_32. */
2815 int fp_code;
2816
2817 /* True if the function has a prototype. */
2818 int prototype;
2819
2820 /* When a structure does not take up a full register, the argument
2821 should sometimes be shifted left so that it occupies the high part
2822 of the register. These two fields describe an array of ashl
2823 patterns for doing this. See function_arg_advance, which creates
2824 the shift patterns, and function_arg, which returns them when given
2825 a VOIDmode argument. */
2826 unsigned int num_adjusts;
2827 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS];
e75b25e7
MM		 2828} CUMULATIVE_ARGS;
2829
2830/* Initialize a variable CUM of type CUMULATIVE_ARGS
2831 for a call to a function whose data type is FNTYPE.
2832 For a library call, FNTYPE is 0.
2833
2834*/
2835
2c7ee1a6 2836#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
e75b25e7
MM		 2837 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2838
2839/* Update the data in CUM to advance over an argument
2840 of mode MODE and data type TYPE.
2841 (TYPE is null for libcalls where that information may not be available.) */
2842
2843#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2844 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2845
2846/* Determine where to put an argument to a function.
2847 Value is zero to push the argument on the stack,
2848 or a hard register in which to store the argument.
2849
2850 MODE is the argument's machine mode.
2851 TYPE is the data type of the argument (as a tree).
2852 This is null for libcalls where that information may
2853 not be available.
2854 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2855 the preceding args and about the function being called.
2856 NAMED is nonzero if this argument is a named parameter
2857 (otherwise it is an extra parameter matching an ellipsis). */
2858
2859#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2860 function_arg( &CUM, MODE, TYPE, NAMED)
2861
2862/* For an arg passed partly in registers and partly in memory,
2863 this is the number of registers used.
987ba558 2864 For args passed entirely in registers or entirely in memory, zero. */
e75b25e7
MM		 2865
2866#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2867 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2868
2869/* If defined, a C expression that gives the alignment boundary, in
2870 bits, of an argument with the specified mode and type. If it is
2871 not defined, `PARM_BOUNDARY' is used for all arguments. */
2872
2873#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2874 (((TYPE) != 0) \
75131237 2875 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
e75b25e7
MM		 2876 ? PARM_BOUNDARY \
2877 : TYPE_ALIGN(TYPE)) \
2878 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2879 ? PARM_BOUNDARY \
2880 : GET_MODE_ALIGNMENT(MODE)))
2881
4d72536e
RS		 2882/* True if using EABI and varargs can be passed in floating-point
2883 registers. Under these conditions, we need a more complex form
2884 of va_list, which tracks GPR, FPR and stack arguments separately. */
2885#define EABI_FLOAT_VARARGS_P \
2886 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2887
e75b25e7 2888\f
e75b25e7
MM		 2889/* Tell prologue and epilogue if register REGNO should be saved / restored. */
2890
2891#define MUST_SAVE_REGISTER(regno) \
2bcb2ab3
GK		 2892 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2893 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
ab78d4a8 2894 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
e75b25e7
MM		 2895
2896/* ALIGN FRAMES on double word boundaries */
d1c17572
JL		 2897#ifndef MIPS_STACK_ALIGN
2898#define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2899#endif
e75b25e7 2900
5d3f2bd5
RH		 2901\f
2902/* Define the `__builtin_va_list' type for the ABI. */
2903#define BUILD_VA_LIST_TYPE(VALIST) \
2904 (VALIST) = mips_build_va_list ()
2905
2906/* Implement `va_start' for varargs and stdarg. */
2907#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2908 mips_va_start (stdarg, valist, nextarg)
2909
2910/* Implement `va_arg'. */
2911#define EXPAND_BUILTIN_VA_ARG(valist, type) \
2912 mips_va_arg (valist, type)
e75b25e7
MM		 2913\f
2914/* Output assembler code to FILE to increment profiler label # LABELNO
2915 for profiling a function entry. */
2916
2917#define FUNCTION_PROFILER(FILE, LABELNO) \
2918{ \
2bcb2ab3
GK		 2919 if (TARGET_MIPS16) \
2920 sorry ("mips16 function profiling"); \
e75b25e7
MM		 2921 fprintf (FILE, "\t.set\tnoat\n"); \
2922 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2923 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
876c09d3
JW		 2924 fprintf (FILE, \
2925 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2926 TARGET_64BIT ? "dsubu" : "subu", \
e75b25e7 2927 reg_names[STACK_POINTER_REGNUM], \
876c09d3 2928 reg_names[STACK_POINTER_REGNUM], \
1eeed24e 2929 Pmode == DImode ? 16 : 8); \
0617ed52 2930 fprintf (FILE, "\tjal\t_mcount\n"); \
e75b25e7
MM		 2931 fprintf (FILE, "\t.set\tat\n"); \
2932}
2933
d8d5b1e1
MM		 2934/* Define this macro if the code for function profiling should come
2935 before the function prologue. Normally, the profiling code comes
2936 after. */
2937
2938/* #define PROFILE_BEFORE_PROLOGUE */
2939
e75b25e7
MM		 2940/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2941 the stack pointer does not matter. The value is tested only in
2942 functions that have frame pointers.
2943 No definition is equivalent to always zero. */
2944
2945#define EXIT_IGNORE_STACK 1
2946
2947\f
2948/* A C statement to output, on the stream FILE, assembler code for a
7dac2f89 2949 block of data that contains the constant parts of a trampoline.
e75b25e7
MM		 2950 This code should not include a label--the label is taken care of
2951 automatically. */
2952
2953#define TRAMPOLINE_TEMPLATE(STREAM) \
2954{ \
2955 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2956 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2957 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
1eeed24e 2958 if (Pmode == DImode) \
876c09d3
JW		 2959 { \
2960 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2961 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2962 } \
2963 else \
2964 { \
0acefe54
JW		 2965 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2966 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
876c09d3 2967 } \
0acefe54 2968 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
e75b25e7
MM		 2969 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2970 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
1eeed24e 2971 if (Pmode == DImode) \
876c09d3 2972 { \
876c09d3
JW		 2973 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2974 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2975 } \
2976 else \
2977 { \
2978 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2979 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2980 } \
e75b25e7
MM		 2981}
2982
2983/* A C expression for the size in bytes of the trampoline, as an
2984 integer. */
2985
1eeed24e 2986#define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
e75b25e7 2987
876c09d3 2988/* Alignment required for trampolines, in bits. */
e75b25e7 2989
1eeed24e 2990#define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
e75b25e7 2991
c85f7c16
JL		 2992/* INITIALIZE_TRAMPOLINE calls this library function to flush
2993 program and data caches. */
2994
2995#ifndef CACHE_FLUSH_FUNC
2996#define CACHE_FLUSH_FUNC "_flush_cache"
2997#endif
2998
7dac2f89 2999/* A C statement to initialize the variable parts of a trampoline.
e75b25e7
MM		 3000 ADDR is an RTX for the address of the trampoline; FNADDR is an
3001 RTX for the address of the nested function; STATIC_CHAIN is an
3002 RTX for the static chain value that should be passed to the
3003 function when it is called. */
3004
3005#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
3006{ \
3007 rtx addr = ADDR; \
1eeed24e 3008 if (Pmode == DImode) \
876c09d3 3009 { \
c5c76735
JL		 3010 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
3011 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
876c09d3
JW		 3012 } \
3013 else \
3014 { \
c5c76735
JL		 3015 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
3016 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
876c09d3 3017 } \
e75b25e7 3018 \
22b54c57
RK		 3019 /* Flush both caches. We need to flush the data cache in case \
3020 the system has a write-back cache. */ \
876c09d3 3021 /* ??? Should check the return value for errors. */ \
d490e8ad
DD		 3022 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
3023 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
3024 0, VOIDmode, 3, addr, Pmode, \
3025 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
3026 GEN_INT (3), TYPE_MODE (integer_type_node)); \
e75b25e7 3027}
e75b25e7
MM		 3028\f
3029/* Addressing modes, and classification of registers for them. */
3030
940da324
JL		 3031/* #define HAVE_POST_INCREMENT 0 */
3032/* #define HAVE_POST_DECREMENT 0 */
e75b25e7 3033
940da324
JL		 3034/* #define HAVE_PRE_DECREMENT 0 */
3035/* #define HAVE_PRE_INCREMENT 0 */
e75b25e7
MM		 3036
3037/* These assume that REGNO is a hard or pseudo reg number.
3038 They give nonzero only if REGNO is a hard reg of the suitable class
3039 or a pseudo reg currently allocated to a suitable hard reg.
3040 These definitions are NOT overridden anywhere. */
3041
2bcb2ab3
GK		 3042#define BASE_REG_P(regno, mode) \
3043 (TARGET_MIPS16 \
3044 ? (M16_REG_P (regno) \
3045 || (regno) == FRAME_POINTER_REGNUM \
3046 || (regno) == ARG_POINTER_REGNUM \
3047 || ((regno) == STACK_POINTER_REGNUM \
3048 && (GET_MODE_SIZE (mode) == 4 \
3049 || GET_MODE_SIZE (mode) == 8))) \
3050 : GP_REG_P (regno))
e75b25e7 3051
2bcb2ab3 3052#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
c3d03e3a 3053 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2bcb2ab3
GK		 3054 (mode))
3055
3056#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3057 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
e75b25e7 3058
876c09d3 3059#define REGNO_OK_FOR_INDEX_P(regno) 0
2bcb2ab3
GK		 3060#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3061 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
e75b25e7
MM		 3062
3063/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3064 and check its validity for a certain class.
3065 We have two alternate definitions for each of them.
3066 The usual definition accepts all pseudo regs; the other rejects them all.
3067 The symbol REG_OK_STRICT causes the latter definition to be used.
3068
3069 Most source files want to accept pseudo regs in the hope that
3070 they will get allocated to the class that the insn wants them to be in.
3071 Some source files that are used after register allocation
3072 need to be strict. */
3073
3074#ifndef REG_OK_STRICT
2bcb2ab3 3075#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
c94c9817 3076 mips_reg_mode_ok_for_base_p (X, MODE, 0)
e75b25e7 3077#else
2bcb2ab3 3078#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
c94c9817 3079 mips_reg_mode_ok_for_base_p (X, MODE, 1)
e75b25e7
MM		 3080#endif
3081
c94c9817
MM		 3082#define REG_OK_FOR_INDEX_P(X) 0
3083
e75b25e7
MM		 3084\f
3085/* Maximum number of registers that can appear in a valid memory address. */
3086
3087#define MAX_REGS_PER_ADDRESS 1
3088
3089/* A C compound statement with a conditional `goto LABEL;' executed
3090 if X (an RTX) is a legitimate memory address on the target
3091 machine for a memory operand of mode MODE.
3092
3093 It usually pays to define several simpler macros to serve as
3094 subroutines for this one. Otherwise it may be too complicated
3095 to understand.
3096
3097 This macro must exist in two variants: a strict variant and a
7dac2f89 3098 non-strict one. The strict variant is used in the reload pass.
e75b25e7
MM		 3099 It must be defined so that any pseudo-register that has not been
3100 allocated a hard register is considered a memory reference. In
3101 contexts where some kind of register is required, a
3102 pseudo-register with no hard register must be rejected.
3103
3104 The non-strict variant is used in other passes. It must be
3105 defined to accept all pseudo-registers in every context where
3106 some kind of register is required.
3107
3108 Compiler source files that want to use the strict variant of
3109 this macro define the macro `REG_OK_STRICT'. You should use an
3110 `#ifdef REG_OK_STRICT' conditional to define the strict variant
3111 in that case and the non-strict variant otherwise.
3112
3113 Typically among the subroutines used to define
3114 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
3115 acceptable registers for various purposes (one for base
3116 registers, one for index registers, and so on). Then only these
3117 subroutine macros need have two variants; the higher levels of
3118 macros may be the same whether strict or not.
3119
3120 Normally, constant addresses which are the sum of a `symbol_ref'
3121 and an integer are stored inside a `const' RTX to mark them as
3122 constant. Therefore, there is no need to recognize such sums
3123 specifically as legitimate addresses. Normally you would simply
3124 recognize any `const' as legitimate.
3125
3126 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
3127 constant sums that are not marked with `const'. It assumes
3128 that a naked `plus' indicates indexing. If so, then you *must*
3129 reject such naked constant sums as illegitimate addresses, so
3130 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
3131
3132 On some machines, whether a symbolic address is legitimate
3133 depends on the section that the address refers to. On these
3134 machines, define the macro `ENCODE_SECTION_INFO' to store the
7dac2f89 3135 information into the `symbol_ref', and then check for it here.
e75b25e7
MM		 3136 When you see a `const', you will have to look inside it to find
3137 the `symbol_ref' in order to determine the section. */
3138
3139#if 1
bd9f1972
KG		 3140#define GO_PRINTF(x) fprintf(stderr, (x))
3141#define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
e75b25e7
MM		 3142#define GO_DEBUG_RTX(x) debug_rtx(x)
3143
3144#else
3145#define GO_PRINTF(x)
3146#define GO_PRINTF2(x,y)
3147#define GO_DEBUG_RTX(x)
3148#endif
3149
c94c9817
MM		 3150#ifdef REG_OK_STRICT
3151#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3152{ \
3153 if (mips_legitimate_address_p (MODE, X, 1)) \
3154 goto ADDR; \
e75b25e7 3155}
c94c9817
MM		 3156#else
3157#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3158{ \
3159 if (mips_legitimate_address_p (MODE, X, 0)) \
3160 goto ADDR; \
3161}
3162#endif
e75b25e7
MM		 3163
3164/* A C expression that is 1 if the RTX X is a constant which is a
6eff269e
BK		 3165 valid address. This is defined to be the same as `CONSTANT_P (X)',
3166 but rejecting CONST_DOUBLE. */
5de1e2ce
JW		 3167/* When pic, we must reject addresses of the form symbol+large int.
3168 This is because an instruction `sw $4,s+70000' needs to be converted
3169 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3170 assembler would use $at as a temp to load in the large offset. In this
3171 case $at is already in use. We convert such problem addresses to
3172 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
516a2dfd 3173/* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
31c714e3 3174#define CONSTANT_ADDRESS_P(X) \
6eff269e 3175 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
5de1e2ce
JW		 3176 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3177 || (GET_CODE (X) == CONST \
516a2dfd 3178 && ! (flag_pic && pic_address_needs_scratch (X)) \
a53f72db
GRK		 3179 && (mips_abi == ABI_32 \
3180 || mips_abi == ABI_O64 \
3181 || mips_abi == ABI_EABI))) \
5de1e2ce 3182 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
e75b25e7 3183
5de1e2ce
JW		 3184/* Define this, so that when PIC, reload won't try to reload invalid
3185 addresses which require two reload registers. */
3186
3187#define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
e75b25e7
MM		 3188
3189/* Nonzero if the constant value X is a legitimate general operand.
3190 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3191
3192 At present, GAS doesn't understand li.[sd], so don't allow it
3193 to be generated at present. Also, the MIPS assembler does not
3194 grok li.d Infinity. */
3195
7dac2f89 3196/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
8e466531
GRK		 3197 Note that the Irix 6 assembler problem may already be fixed.
3198 Note also that the GET_CODE (X) == CONST test catches the mips16
3199 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3200 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3201 ABI_64 to work together, we'll need to fix this. */
e75b25e7 3202#define LEGITIMATE_CONSTANT_P(X) \
516a2dfd
JW		 3203 ((GET_CODE (X) != CONST_DOUBLE \
3204 || mips_const_double_ok (X, GET_MODE (X))) \
8e466531
GRK		 3205 && ! (GET_CODE (X) == CONST \
3206 && ! TARGET_GAS \
3207 && (mips_abi == ABI_N32 \
3208 || mips_abi == ABI_64)) \
2bcb2ab3 3209 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
e75b25e7
MM		 3210
3211/* A C compound statement that attempts to replace X with a valid
3212 memory address for an operand of mode MODE. WIN will be a C
3213 statement label elsewhere in the code; the macro definition may
3214 use
3215
3216 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3217
3218 to avoid further processing if the address has become legitimate.
3219
3220 X will always be the result of a call to `break_out_memory_refs',
3221 and OLDX will be the operand that was given to that function to
3222 produce X.
3223
3224 The code generated by this macro should not alter the
3225 substructure of X. If it transforms X into a more legitimate
3226 form, it should assign X (which will always be a C variable) a
3227 new value.
3228
3229 It is not necessary for this macro to come up with a legitimate
3230 address. The compiler has standard ways of doing so in all
3231 cases. In fact, it is safe for this macro to do nothing. But
2649b2ee 3232 often a machine-dependent strategy can generate better code.
e75b25e7 3233
2649b2ee
MM		 3234 For the MIPS, transform:
3235
3236 memory(X + <large int>)
3237
3238 into:
3239
3240 Y = <large int> & ~0x7fff;
3241 Z = X + Y
3242 memory (Z + (<large int> & 0x7fff));
3243
5de1e2ce
JW		 3244 This is for CSE to find several similar references, and only use one Z.
3245
3246 When PIC, convert addresses of the form memory (symbol+large int) to
3247 memory (reg+large int). */
7dac2f89 3248
2649b2ee
MM		 3249
3250#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3251{ \
3252 register rtx xinsn = (X); \
3253 \
3254 if (TARGET_DEBUG_B_MODE) \
3255 { \
3256 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3257 GO_DEBUG_RTX (xinsn); \
3258 } \
3259 \
ce57d6f4
JW		 3260 if (mips_split_addresses && mips_check_split (X, MODE)) \
3261 { \
3262 /* ??? Is this ever executed? */ \
c5c76735
JL		 3263 X = gen_rtx_LO_SUM (Pmode, \
3264 copy_to_mode_reg (Pmode, \
3265 gen_rtx (HIGH, Pmode, X)), \
3266 X); \
ce57d6f4
JW		 3267 goto WIN; \
3268 } \
3269 \
516a2dfd
JW		 3270 if (GET_CODE (xinsn) == CONST \
3271 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3272 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
a53f72db
GRK		 3273 || (mips_abi != ABI_32 \
3274 && mips_abi != ABI_O64 \
3275 && mips_abi != ABI_EABI))) \
516a2dfd
JW		 3276 { \
3277 rtx ptr_reg = gen_reg_rtx (Pmode); \
3278 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3279 \
3280 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3281 \
c5c76735 3282 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
516a2dfd
JW		 3283 if (SMALL_INT (constant)) \
3284 goto WIN; \
3285 /* Otherwise we fall through so the code below will fix the \
3286 constant. */ \
3287 xinsn = X; \
3288 } \
3289 \
b3de0f1f 3290 if (GET_CODE (xinsn) == PLUS) \
2649b2ee
MM		 3291 { \
3292 register rtx xplus0 = XEXP (xinsn, 0); \
3293 register rtx xplus1 = XEXP (xinsn, 1); \
3294 register enum rtx_code code0 = GET_CODE (xplus0); \
3295 register enum rtx_code code1 = GET_CODE (xplus1); \
3296 \
3297 if (code0 != REG && code1 == REG) \
3298 { \
3299 xplus0 = XEXP (xinsn, 1); \
3300 xplus1 = XEXP (xinsn, 0); \
3301 code0 = GET_CODE (xplus0); \
3302 code1 = GET_CODE (xplus1); \
3303 } \
3304 \
2bcb2ab3 3305 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2649b2ee
MM		 3306 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3307 { \
3308 rtx int_reg = gen_reg_rtx (Pmode); \
3309 rtx ptr_reg = gen_reg_rtx (Pmode); \
3310 \
3311 emit_move_insn (int_reg, \
3312 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3313 \
c5c76735
JL		 3314 emit_insn (gen_rtx_SET (VOIDmode, \
3315 ptr_reg, \
3316 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
2649b2ee 3317 \
8da665d5 3318 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
2649b2ee
MM		 3319 goto WIN; \
3320 } \
3321 } \
3322 \
3323 if (TARGET_DEBUG_B_MODE) \
3324 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3325}
e75b25e7
MM		 3326
3327
3328/* A C statement or compound statement with a conditional `goto
3329 LABEL;' executed if memory address X (an RTX) can have different
3330 meanings depending on the machine mode of the memory reference it
3331 is used for.
3332
3333 Autoincrement and autodecrement addresses typically have
3334 mode-dependent effects because the amount of the increment or
3335 decrement is the size of the operand being addressed. Some
3336 machines have other mode-dependent addresses. Many RISC machines
3337 have no mode-dependent addresses.
3338
3339 You may assume that ADDR is a valid address for the machine. */
3340
3341#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3342
3343
3344/* Define this macro if references to a symbol must be treated
3345 differently depending on something about the variable or
3346 function named by the symbol (such as what section it is in).
3347
3348 The macro definition, if any, is executed immediately after the
7dac2f89 3349 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
e75b25e7
MM		 3350 The value of the rtl will be a `mem' whose address is a
3351 `symbol_ref'.
3352
3353 The usual thing for this macro to do is to a flag in the
3354 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3355 name string in the `symbol_ref' (if one bit is not enough
3356 information).
3357
3358 The best way to modify the name string is by adding text to the
7dac2f89 3359 beginning, with suitable punctuation to prevent any ambiguity.
e75b25e7
MM		 3360 Allocate the new name in `saveable_obstack'. You will have to
3361 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3362 and output the name accordingly.
3363
3364 You can also check the information stored in the `symbol_ref' in
3365 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2bcb2ab3
GK		 3366 `PRINT_OPERAND_ADDRESS'.
3367
3368 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3369 small objects.
3370
3371 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3372 symbols which are not in the .text section.
3373
3374 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3375 constants which are put in the .text section. We also record the
3376 total length of all such strings; this total is used to decide
3377 whether we need to split the constant table, and need not be
7dac2f89 3378 precisely correct.
a9e3e611
GRK		 3379
3380 When not mips16 code nor embedded PIC, if a symbol is in a
3381 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3382 splitting the reference so that gas can generate a gp relative
3383 reference.
5f680ab6
DD		 3384
3385 When TARGET_EMBEDDED_DATA is set, we assume that all const
3386 variables will be stored in ROM, which is too far from %gp to use
3387 %gprel addressing. Note that (1) we include "extern const"
3388 variables in this, which mips_select_section doesn't, and (2) we
3389 can't always tell if they're really const (they might be const C++
3390 objects with non-const constructors), so we err on the side of
3391 caution and won't use %gprel anyway (otherwise we'd have to defer
3392 this decision to the linker/loader). The handling of extern consts
3393 is why the DECL_INITIAL macros differ from mips_select_section.
3394
3395 If you are changing this macro, you should look at
3396 mips_select_section and see if it needs a similar change. */
e75b25e7 3397
b2003250 3398#define ENCODE_SECTION_INFO(DECL, FIRST) \
e75b25e7
MM		 3399do \
3400 { \
2bcb2ab3
GK		 3401 if (TARGET_MIPS16) \
3402 { \
b2003250 3403 if ((FIRST) && TREE_CODE (DECL) == STRING_CST \
52ecdfda
JW		 3404 && ! flag_writable_strings \
3405 /* If this string is from a function, and the function will \
3406 go in a gnu linkonce section, then we can't directly \
3407 access the string. This gets an assembler error \
3408 "unsupported PC relative reference to different section".\
3409 If we modify SELECT_SECTION to put it in function_section\
3410 instead of text_section, it still fails because \
3411 DECL_SECTION_NAME isn't set until assemble_start_function.\
3412 If we fix that, it still fails because strings are shared\
3413 among multiple functions, and we have cross section \
3414 references again. We force it to work by putting string \
3415 addresses in the constant pool and indirecting. */ \
3416 && (! current_function_decl \
7c262518 3417 || ! DECL_ONE_ONLY (current_function_decl))) \
2bcb2ab3
GK		 3418 { \
3419 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3420 mips_string_length += TREE_STRING_LENGTH (DECL); \
3421 } \
3422 } \
5f680ab6
DD		 3423 \
3424 if (TARGET_EMBEDDED_DATA \
3425 && (TREE_CODE (DECL) == VAR_DECL \
3426 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3427 && (!DECL_INITIAL (DECL) \
3428 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3429 { \
3430 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3431 } \
3432 \
3433 else if (TARGET_EMBEDDED_PIC) \
92544bdf
ILT		 3434 { \
3435 if (TREE_CODE (DECL) == VAR_DECL) \
3436 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3437 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3438 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3439 else if (TREE_CODE (DECL) == STRING_CST \
3440 && ! flag_writable_strings) \
3441 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3442 else \
3443 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3444 } \
3445 \
a9e3e611
GRK		 3446 else if (TREE_CODE (DECL) == VAR_DECL \
3447 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3448 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3449 ".sdata") \
3450 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3451 ".sbss"))) \
3452 { \
3453 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3454 } \
3455 \
13b6b42c
JL		 3456 /* We can not perform GP optimizations on variables which are in \
3457 specific sections, except for .sdata and .sbss which are \
3458 handled above. */ \
3459 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
c066429e
AO		 3460 && DECL_SECTION_NAME (DECL) == NULL_TREE \
3461 && ! (TARGET_MIPS16 && TREE_PUBLIC (DECL) \
3462 && (DECL_COMMON (DECL) \
3463 || DECL_ONE_ONLY (DECL) \
3464 || DECL_WEAK (DECL)))) \
e75b25e7
MM		 3465 { \
3466 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3467 \
3468 if (size > 0 && size <= mips_section_threshold) \
3469 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3470 } \
3471 \
31c714e3 3472 else if (HALF_PIC_P ()) \
6e92f4b6 3473 { \
b2003250
RH		 3474 if (FIRST) \
3475 HALF_PIC_ENCODE (DECL); \
6e92f4b6 3476 } \
e75b25e7
MM		 3477 } \
3478while (0)
3479
9c9e7632
GK		 3480/* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3481 'the start of the function that this code is output in'. */
3482
3483#define ASM_OUTPUT_LABELREF(FILE,NAME) \
3484 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3485 asm_fprintf ((FILE), "%U%s", \
3486 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3487 else \
3488 asm_fprintf ((FILE), "%U%s", (NAME))
3489
2bcb2ab3
GK		 3490/* The mips16 wants the constant pool to be after the function,
3491 because the PC relative load instructions use unsigned offsets. */
3492
3493#define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3494
3495#define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3496 mips_string_length = 0;
3497
3498#if 0
3499/* In mips16 mode, put most string constants after the function. */
3500#define CONSTANT_AFTER_FUNCTION_P(tree) \
3501 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3502#endif
e75b25e7
MM		 3503\f
3504/* Specify the machine mode that this machine uses
2bcb2ab3
GK		 3505 for the index in the tablejump instruction.
3506 ??? Using HImode in mips16 mode can cause overflow. However, the
3507 overflow is no more likely than the overflow in a branch
3508 instruction. Large functions can currently break in both ways. */
3509#define CASE_VECTOR_MODE \
1eeed24e 3510 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
2bcb2ab3
GK		 3511
3512/* Define as C expression which evaluates to nonzero if the tablejump
3513 instruction expects the table to contain offsets from the address of the
3514 table.
987ba558 3515 Do not define this if the table should contain absolute addresses. */
2bcb2ab3 3516#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
e75b25e7 3517
e75b25e7 3518/* Define this as 1 if `char' should by default be signed; else as 0. */
6639753e 3519#ifndef DEFAULT_SIGNED_CHAR
e75b25e7 3520#define DEFAULT_SIGNED_CHAR 1
6639753e 3521#endif
e75b25e7
MM		 3522
3523/* Max number of bytes we can move from memory to memory
3524 in one reasonably fast instruction. */
876c09d3
JW		 3525#define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3526#define MAX_MOVE_MAX 8
e75b25e7
MM		 3527
3528/* Define this macro as a C expression which is nonzero if
3529 accessing less than a word of memory (i.e. a `char' or a
3530 `short') is no faster than accessing a word of memory, i.e., if
3531 such access require more than one instruction or if there is no
3532 difference in cost between byte and (aligned) word loads.
3533
3534 On RISC machines, it tends to generate better code to define
3535 this as 1, since it avoids making a QI or HI mode register. */
3536#define SLOW_BYTE_ACCESS 1
3537
3538/* We assume that the store-condition-codes instructions store 0 for false
3539 and some other value for true. This is the value stored for true. */
3540
3541#define STORE_FLAG_VALUE 1
3542
d969caf8 3543/* Define this to be nonzero if shift instructions ignore all but the low-order
987ba558 3544 few bits. */
d969caf8 3545#define SHIFT_COUNT_TRUNCATED 1
e75b25e7
MM		 3546
3547/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3548 is done just by pretending it is already truncated. */
876c09d3
JW		 3549/* In 64 bit mode, 32 bit instructions require that register values be properly
3550 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3551 converts a value >32 bits to a value <32 bits. */
3552/* ??? This results in inefficient code for 64 bit to 32 conversions.
3553 Something needs to be done about this. Perhaps not use any 32 bit
3554 instructions? Perhaps use PROMOTE_MODE? */
3555#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3556 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
e75b25e7 3557
e75b25e7
MM		 3558/* Specify the machine mode that pointers have.
3559 After generation of rtl, the compiler makes no further distinction
fb1bf66d
GRK		 3560 between pointers and any other objects of this machine mode.
3561
987ba558 3562 For MIPS we make pointers are the smaller of longs and gp-registers. */
876c09d3 3563
1eeed24e 3564#ifndef Pmode
8ca47902 3565#define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
1eeed24e 3566#endif
e75b25e7
MM		 3567
3568/* A function address in a call instruction
3569 is a word address (for indexing purposes)
3570 so give the MEM rtx a words's mode. */
3571
1eeed24e 3572#define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
e75b25e7
MM		 3573
3574/* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3575 memset, instead of the BSD functions bcopy and bzero. */
3576
3577#if defined(MIPS_SYSV) || defined(OSF_OS)
3578#define TARGET_MEM_FUNCTIONS
3579#endif
3580
3581\f
3582/* A part of a C `switch' statement that describes the relative
3583 costs of constant RTL expressions. It must contain `case'
3584 labels for expression codes `const_int', `const', `symbol_ref',
3585 `label_ref' and `const_double'. Each case must ultimately reach
3586 a `return' statement to return the relative cost of the use of
3587 that kind of constant value in an expression. The cost may
3588 depend on the precise value of the constant, which is available
3589 for examination in X.
3590
3591 CODE is the expression code--redundant, since it can be obtained
3592 with `GET_CODE (X)'. */
3593
def9623c 3594#define CONST_COSTS(X,CODE,OUTER_CODE) \
e75b25e7 3595 case CONST_INT: \
2bcb2ab3
GK		 3596 if (! TARGET_MIPS16) \
3597 { \
3598 /* Always return 0, since we don't have different sized \
3599 instructions, hence different costs according to Richard \
3600 Kenner */ \
3601 return 0; \
3602 } \
3603 if ((OUTER_CODE) == SET) \
3604 { \
3605 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3606 return 0; \
3607 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3608 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3609 return COSTS_N_INSNS (1); \
3610 else \
3611 return COSTS_N_INSNS (2); \
3612 } \
3613 /* A PLUS could be an address. We don't want to force an address \
3614 to use a register, so accept any signed 16 bit value without \
3615 complaint. */ \
3616 if ((OUTER_CODE) == PLUS \
3617 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3618 return 0; \
3619 /* A number between 1 and 8 inclusive is efficient for a shift. \
3620 Otherwise, we will need an extended instruction. */ \
3621 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3622 || (OUTER_CODE) == LSHIFTRT) \
3623 { \
3624 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3625 return 0; \
3626 return COSTS_N_INSNS (1); \
3627 } \
3628 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3629 if ((OUTER_CODE) == XOR \
3630 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3631 return 0; \
3632 /* We may be able to use slt or sltu for a comparison with a \
3633 signed 16 bit value. (The boundary conditions aren't quite \
3634 right, but this is just a heuristic anyhow.) */ \
3635 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3636 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3637 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3638 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3639 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3640 return 0; \
3641 /* Equality comparisons with 0 are cheap. */ \
3642 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3643 && INTVAL (X) == 0) \
3644 return 0; \
3645 \
3646 /* Otherwise, work out the cost to load the value into a \
3647 register. */ \
3648 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3649 return COSTS_N_INSNS (1); \
3650 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3651 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3652 return COSTS_N_INSNS (2); \
3653 else \
3654 return COSTS_N_INSNS (3); \
e75b25e7
MM		 3655 \
3656 case LABEL_REF: \
3657 return COSTS_N_INSNS (2); \
3658 \
3659 case CONST: \
3660 { \
31c714e3 3661 rtx offset = const0_rtx; \
876c09d3 3662 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
e75b25e7 3663 \
2bcb2ab3
GK		 3664 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3665 { \
3666 /* Treat this like a signed 16 bit CONST_INT. */ \
3667 if ((OUTER_CODE) == PLUS) \
3668 return 0; \
3669 else if ((OUTER_CODE) == SET) \
3670 return COSTS_N_INSNS (1); \
3671 else \
3672 return COSTS_N_INSNS (2); \
3673 } \
3674 \
e75b25e7
MM		 3675 if (GET_CODE (symref) == LABEL_REF) \
3676 return COSTS_N_INSNS (2); \
3677 \
3678 if (GET_CODE (symref) != SYMBOL_REF) \
3679 return COSTS_N_INSNS (4); \
3680 \
987ba558 3681 /* let's be paranoid.... */ \
31c714e3 3682 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
e75b25e7
MM		 3683 return COSTS_N_INSNS (2); \
3684 \
3685 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3686 } \
3687 \
3688 case SYMBOL_REF: \
3689 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3690 \
3691 case CONST_DOUBLE: \
96abdcb1
ILT		 3692 { \
3693 rtx high, low; \
2bcb2ab3
GK		 3694 if (TARGET_MIPS16) \
3695 return COSTS_N_INSNS (4); \
96abdcb1
ILT		 3696 split_double (X, &high, &low); \
3697 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3698 || low == CONST0_RTX (GET_MODE (low))) \
3699 ? 2 : 4); \
3700 }
e75b25e7
MM		 3701
3702/* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3703 This can be used, for example, to indicate how costly a multiply
3704 instruction is. In writing this macro, you can use the construct
3705 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3706
3707 This macro is optional; do not define it if the default cost
3708 assumptions are adequate for the target machine.
3709
3710 If -mdebugd is used, change the multiply cost to 2, so multiply by
3711 a constant isn't converted to a series of shifts. This helps
3712 strength reduction, and also makes it easier to identify what the
3713 compiler is doing. */
3714
516a2dfd 3715/* ??? Fix this to be right for the R8000. */
def9623c 3716#define RTX_COSTS(X,CODE,OUTER_CODE) \
e75b25e7
MM		 3717 case MEM: \
3718 { \
3719 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3720 if (simple_memory_operand (X, GET_MODE (X))) \
3721 return COSTS_N_INSNS (num_words); \
3722 \
3723 return COSTS_N_INSNS (2*num_words); \
3724 } \
3725 \
3726 case FFS: \
3727 return COSTS_N_INSNS (6); \
3728 \
3729 case NOT: \
876c09d3 3730 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
e75b25e7
MM		 3731 \
3732 case AND: \
3733 case IOR: \
3734 case XOR: \
876c09d3 3735 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
e75b25e7
MM		 3736 return COSTS_N_INSNS (2); \
3737 \
2bcb2ab3 3738 break; \
e75b25e7
MM		 3739 \
3740 case ASHIFT: \
3741 case ASHIFTRT: \
e75b25e7 3742 case LSHIFTRT: \
876c09d3
JW		 3743 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3744 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
e75b25e7 3745 \
2bcb2ab3 3746 break; \
e75b25e7
MM		 3747 \
3748 case ABS: \
3749 { \
3750 enum machine_mode xmode = GET_MODE (X); \
3751 if (xmode == SFmode || xmode == DFmode) \
3752 return COSTS_N_INSNS (1); \
3753 \
3754 return COSTS_N_INSNS (4); \
3755 } \
3756 \
3757 case PLUS: \
3758 case MINUS: \
3759 { \
3760 enum machine_mode xmode = GET_MODE (X); \
3761 if (xmode == SFmode || xmode == DFmode) \
9a863c83 3762 { \
7dac2f89
EC		 3763 if (TUNE_MIPS3000 \
3764 || TUNE_MIPS3900) \
9a863c83 3765 return COSTS_N_INSNS (2); \
7dac2f89 3766 else if (TUNE_MIPS6000) \
9a863c83
JW		 3767 return COSTS_N_INSNS (3); \
3768 else \
3769 return COSTS_N_INSNS (6); \
3770 } \
e75b25e7 3771 \
876c09d3 3772 if (xmode == DImode && !TARGET_64BIT) \
e75b25e7
MM		 3773 return COSTS_N_INSNS (4); \
3774 \
2bcb2ab3 3775 break; \
e75b25e7
MM		 3776 } \
3777 \
3778 case NEG: \
2bcb2ab3
GK		 3779 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3780 return 4; \
3781 \
3782 break; \
e75b25e7
MM		 3783 \
3784 case MULT: \
3785 { \
3786 enum machine_mode xmode = GET_MODE (X); \
3787 if (xmode == SFmode) \
9a863c83 3788 { \
7dac2f89
EC		 3789 if (TUNE_MIPS3000 \
3790 || TUNE_MIPS3900 \
3791 || TUNE_MIPS5000) \
9a863c83 3792 return COSTS_N_INSNS (4); \
7dac2f89 3793 else if (TUNE_MIPS6000) \
9a863c83
JW		 3794 return COSTS_N_INSNS (5); \
3795 else \
3796 return COSTS_N_INSNS (7); \
3797 } \
e75b25e7
MM		 3798 \
3799 if (xmode == DFmode) \
9a863c83 3800 { \
7dac2f89
EC		 3801 if (TUNE_MIPS3000 \
3802 || TUNE_MIPS3900 \
3803 || TUNE_MIPS5000) \
9a863c83 3804 return COSTS_N_INSNS (5); \
7dac2f89 3805 else if (TUNE_MIPS6000) \
9a863c83
JW		 3806 return COSTS_N_INSNS (6); \
3807 else \
3808 return COSTS_N_INSNS (8); \
3809 } \
e75b25e7 3810 \
7dac2f89 3811 if (TUNE_MIPS3000) \
9a863c83 3812 return COSTS_N_INSNS (12); \
7dac2f89 3813 else if (TUNE_MIPS3900) \
e9a25f70 3814 return COSTS_N_INSNS (2); \
7dac2f89 3815 else if (TUNE_MIPS6000) \
9a863c83 3816 return COSTS_N_INSNS (17); \
7dac2f89 3817 else if (TUNE_MIPS5000) \
b8eb88d0 3818 return COSTS_N_INSNS (5); \
9a863c83
JW		 3819 else \
3820 return COSTS_N_INSNS (10); \
e75b25e7
MM		 3821 } \
3822 \
3823 case DIV: \
3824 case MOD: \
3825 { \
3826 enum machine_mode xmode = GET_MODE (X); \
3827 if (xmode == SFmode) \
9a863c83 3828 { \
7dac2f89
EC		 3829 if (TUNE_MIPS3000 \
3830 || TUNE_MIPS3900) \
9a863c83 3831 return COSTS_N_INSNS (12); \
7dac2f89 3832 else if (TUNE_MIPS6000) \
9a863c83
JW		 3833 return COSTS_N_INSNS (15); \
3834 else \
3835 return COSTS_N_INSNS (23); \
3836 } \
e75b25e7
MM		 3837 \
3838 if (xmode == DFmode) \
9a863c83 3839 { \
7dac2f89
EC		 3840 if (TUNE_MIPS3000 \
3841 || TUNE_MIPS3900) \
9a863c83 3842 return COSTS_N_INSNS (19); \
7dac2f89 3843 else if (TUNE_MIPS6000) \
9a863c83
JW		 3844 return COSTS_N_INSNS (16); \
3845 else \
3846 return COSTS_N_INSNS (36); \
3847 } \
e75b25e7
MM		 3848 } \
3849 /* fall through */ \
3850 \
3851 case UDIV: \
3852 case UMOD: \
7dac2f89
EC		 3853 if (TUNE_MIPS3000 \
3854 || TUNE_MIPS3900) \
9a863c83 3855 return COSTS_N_INSNS (35); \
7dac2f89 3856 else if (TUNE_MIPS6000) \
9a863c83 3857 return COSTS_N_INSNS (38); \
7dac2f89 3858 else if (TUNE_MIPS5000) \
b8eb88d0 3859 return COSTS_N_INSNS (36); \
9a863c83 3860 else \
1a4fa807
ILT		 3861 return COSTS_N_INSNS (69); \
3862 \
3863 case SIGN_EXTEND: \
3864 /* A sign extend from SImode to DImode in 64 bit mode is often \
3865 zero instructions, because the result can often be used \
3866 directly by another instruction; we'll call it one. */ \
3867 if (TARGET_64BIT && GET_MODE (X) == DImode \
3868 && GET_MODE (XEXP (X, 0)) == SImode) \
3869 return COSTS_N_INSNS (1); \
3870 else \
3871 return COSTS_N_INSNS (2); \
3872 \
3873 case ZERO_EXTEND: \
3874 if (TARGET_64BIT && GET_MODE (X) == DImode \
3875 && GET_MODE (XEXP (X, 0)) == SImode) \
3876 return COSTS_N_INSNS (2); \
3877 else \
3878 return COSTS_N_INSNS (1);
e75b25e7
MM		 3879
3880/* An expression giving the cost of an addressing mode that
3881 contains ADDRESS. If not defined, the cost is computed from the
3882 form of the ADDRESS expression and the `CONST_COSTS' values.
3883
3884 For most CISC machines, the default cost is a good approximation
3885 of the true cost of the addressing mode. However, on RISC
3886 machines, all instructions normally have the same length and
3887 execution time. Hence all addresses will have equal costs.
3888
3889 In cases where more than one form of an address is known, the
3890 form with the lowest cost will be used. If multiple forms have
3891 the same, lowest, cost, the one that is the most complex will be
3892 used.
3893
3894 For example, suppose an address that is equal to the sum of a
7dac2f89 3895 register and a constant is used twice in the same basic block.
e75b25e7
MM		 3896 When this macro is not defined, the address will be computed in
3897 a register and memory references will be indirect through that
3898 register. On machines where the cost of the addressing mode
3899 containing the sum is no higher than that of a simple indirect
3900 reference, this will produce an additional instruction and
3901 possibly require an additional register. Proper specification
3902 of this macro eliminates this overhead for such machines.
3903
3904 Similar use of this macro is made in strength reduction of loops.
3905
3906 ADDRESS need not be valid as an address. In such a case, the
3907 cost is not relevant and can be any value; invalid addresses
3908 need not be assigned a different cost.
3909
3910 On machines where an address involving more than one register is
3911 as cheap as an address computation involving only one register,
3912 defining `ADDRESS_COST' to reflect this can cause two registers
3913 to be live over a region of code where only one would have been
3914 if `ADDRESS_COST' were not defined in that manner. This effect
7dac2f89 3915 should be considered in the definition of this macro.
e75b25e7
MM		 3916 Equivalent costs should probably only be given to addresses with
3917 different numbers of registers on machines with lots of registers.
3918
3919 This macro will normally either not be defined or be defined as
987ba558 3920 a constant. */
e75b25e7
MM		 3921
3922#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3923
3924/* A C expression for the cost of moving data from a register in
3925 class FROM to one in class TO. The classes are expressed using
3926 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3927 the default; other values are interpreted relative to that.
3928
3929 It is not required that the cost always equal 2 when FROM is the
3930 same as TO; on some machines it is expensive to move between
3931 registers if they are not general registers.
3932
3933 If reload sees an insn consisting of a single `set' between two
3934 hard registers, and if `REGISTER_MOVE_COST' applied to their
3935 classes returns a value of 2, reload does not check to ensure
3936 that the constraints of the insn are met. Setting a cost of
3937 other than 2 will allow reload to verify that the constraints are
3938 met. You should do this if the `movM' pattern's constraints do
56dc4d15
JW		 3939 not allow such copying.
3940
3941 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3942 registers the same as for one of moving general registers to
3943 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3944 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3945 isn't clear if it is wise. And it might not work in all cases. We
3946 could solve the DImode LO reg problem by using a multiply, just like
3947 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3948 by using divide instructions. divu puts the remainder in the HI
3949 reg, so doing a divide by -1 will move the value in the HI reg for
3950 all values except -1. We could handle that case by using a signed
3951 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3952 compare/branch to test the input value to see which instruction we
987ba558 3953 need to use. This gets pretty messy, but it is feasible. */
e75b25e7 3954
cf011243 3955#define REGISTER_MOVE_COST(MODE, FROM, TO) \
2bcb2ab3
GK		 3956 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3957 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3958 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3959 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3960 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
9a863c83 3961 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
2bcb2ab3
GK		 3962 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3963 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
225b8835
ILT		 3964 : (((FROM) == HI_REG || (FROM) == LO_REG \
3965 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
56dc4d15 3966 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
225b8835 3967 : (((TO) == HI_REG || (TO) == LO_REG \
2bcb2ab3
GK		 3968 || (TO) == MD_REGS || (TO) == HILO_REG) \
3969 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3970 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
b8eb88d0 3971 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
46299de9 3972 : 12)
e75b25e7 3973
516a2dfd 3974/* ??? Fix this to be right for the R8000. */
cbd5b9a2 3975#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
7dac2f89 3976 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
cbd5b9a2 3977 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
876c09d3 3978
7506f491
DE		 3979/* Define if copies to/from condition code registers should be avoided.
3980
3981 This is needed for the MIPS because reload_outcc is not complete;
3982 it needs to handle cases where the source is a general or another
3983 condition code register. */
3984#define AVOID_CCMODE_COPIES
3985
e75b25e7
MM		 3986/* A C expression for the cost of a branch instruction. A value of
3987 1 is the default; other values are interpreted relative to that. */
3988
516a2dfd 3989/* ??? Fix this to be right for the R8000. */
2bcb2ab3
GK		 3990#define BRANCH_COST \
3991 ((! TARGET_MIPS16 \
7dac2f89 3992 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2bcb2ab3 3993 ? 2 : 1)
e75b25e7 3994
0ff83799
MM		 3995/* If defined, modifies the length assigned to instruction INSN as a
3996 function of the context in which it is used. LENGTH is an lvalue
3997 that contains the initially computed length of the insn and should
3998 be updated with the correct length of the insn. */
3999#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
4000 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
4001
e75b25e7
MM		 4002\f
4003/* Optionally define this if you have added predicates to
4004 `MACHINE.c'. This macro is called within an initializer of an
4005 array of structures. The first field in the structure is the
31c714e3 4006 name of a predicate and the second field is an array of rtl
e75b25e7
MM		 4007 codes. For each predicate, list all rtl codes that can be in
4008 expressions matched by the predicate. The list should have a
4009 trailing comma. Here is an example of two entries in the list
4010 for a typical RISC machine:
4011
4012 #define PREDICATE_CODES \
4013 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
4014 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
4015
4016 Defining this macro does not affect the generated code (however,
4017 incorrect definitions that omit an rtl code that may be matched
7dac2f89 4018 by the predicate can cause the compiler to malfunction).
e75b25e7
MM		 4019 Instead, it allows the table built by `genrecog' to be more
4020 compact and efficient, thus speeding up the compiler. The most
4021 important predicates to include in the list specified by this
4022 macro are thoses used in the most insn patterns. */
4023
4024#define PREDICATE_CODES \
4025 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
4026 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
4027 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
def72bd2
GRK		 4028 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
4029 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
e75b25e7
MM		 4030 {"small_int", { CONST_INT }}, \
4031 {"large_int", { CONST_INT }}, \
e75b25e7 4032 {"mips_const_double_ok", { CONST_DOUBLE }}, \
b8eb88d0 4033 {"const_float_1_operand", { CONST_DOUBLE }}, \
e75b25e7 4034 {"simple_memory_operand", { MEM, SUBREG }}, \
e75b25e7
MM		 4035 {"equality_op", { EQ, NE }}, \
4036 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
4037 LTU, LEU }}, \
a0b6cdee 4038 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
f8634644 4039 {"pc_or_label_operand", { PC, LABEL_REF }}, \
ce57d6f4
JW		 4040 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
4041 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
4042 SYMBOL_REF, LABEL_REF, SUBREG, \
4043 REG, MEM}}, \
1908a152
ILT		 4044 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
4045 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
4046 MEM, SIGN_EXTEND }}, \
4047 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
def72bd2 4048 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
1908a152
ILT		 4049 SIGN_EXTEND }}, \
4050 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
4051 SIGN_EXTEND }}, \
4052 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
4053 SIGN_EXTEND }}, \
4054 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
4055 SYMBOL_REF, LABEL_REF, SUBREG, \
4056 REG, SIGN_EXTEND }}, \
2bcb2ab3
GK		 4057 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
4058 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
cb923660
KR		 4059 CONST_DOUBLE, CONST }}, \
4060 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
4061 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
4062
0e7e9155
RH		 4063/* A list of predicates that do special things with modes, and so
4064 should not elicit warnings for VOIDmode match_operand. */
4065
4066#define SPECIAL_MODE_PREDICATES \
4067 "pc_or_label_operand",
e75b25e7
MM		 4068
4069\f
4070/* If defined, a C statement to be executed just prior to the
4071 output of assembler code for INSN, to modify the extracted
4072 operands so they will be output differently.
4073
4074 Here the argument OPVEC is the vector containing the operands
4075 extracted from INSN, and NOPERANDS is the number of elements of
4076 the vector which contain meaningful data for this insn. The
4077 contents of this vector are what will be used to convert the
4078 insn template into assembler code, so you can change the
4079 assembler output by changing the contents of the vector.
4080
4081 We use it to check if the current insn needs a nop in front of it
4082 because of load delays, and also to update the delay slot
4083 statistics. */
4084
4085#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
65437fe8 4086 final_prescan_insn (INSN, OPVEC, NOPERANDS)
e75b25e7 4087
e75b25e7
MM		 4088\f
4089/* Control the assembler format that we output. */
4090
4091/* Output at beginning of assembler file.
4092 If we are optimizing to use the global pointer, create a temporary
4093 file to hold all of the text stuff, and write it out to the end.
4094 This is needed because the MIPS assembler is evidently one pass,
4095 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4096 declaration when the code is processed, it generates a two
4097 instruction sequence. */
4098
44404b8b 4099#undef ASM_FILE_START
e75b25e7
MM		 4100#define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
4101
4102/* Output to assembler file text saying following lines
4103 may contain character constants, extra white space, comments, etc. */
4104
b2bcb32d 4105#ifndef ASM_APP_ON
e75b25e7 4106#define ASM_APP_ON " #APP\n"
b2bcb32d 4107#endif
e75b25e7
MM		 4108
4109/* Output to assembler file text saying following lines
4110 no longer contain unusual constructs. */
4111
b2bcb32d 4112#ifndef ASM_APP_OFF
e75b25e7 4113#define ASM_APP_OFF " #NO_APP\n"
b2bcb32d 4114#endif
e75b25e7
MM		 4115
4116/* How to refer to registers in assembler output.
4117 This sequence is indexed by compiler's hard-register-number (see above).
4118
4119 In order to support the two different conventions for register names,
4120 we use the name of a table set up in mips.c, which is overwritten
4121 if -mrnames is used. */
4122
4123#define REGISTER_NAMES \
4124{ \
4125 &mips_reg_names[ 0][0], \
4126 &mips_reg_names[ 1][0], \
4127 &mips_reg_names[ 2][0], \
4128 &mips_reg_names[ 3][0], \
4129 &mips_reg_names[ 4][0], \
4130 &mips_reg_names[ 5][0], \
4131 &mips_reg_names[ 6][0], \
4132 &mips_reg_names[ 7][0], \
4133 &mips_reg_names[ 8][0], \
4134 &mips_reg_names[ 9][0], \
4135 &mips_reg_names[10][0], \
4136 &mips_reg_names[11][0], \
4137 &mips_reg_names[12][0], \
4138 &mips_reg_names[13][0], \
4139 &mips_reg_names[14][0], \
4140 &mips_reg_names[15][0], \
4141 &mips_reg_names[16][0], \
4142 &mips_reg_names[17][0], \
4143 &mips_reg_names[18][0], \
4144 &mips_reg_names[19][0], \
4145 &mips_reg_names[20][0], \
4146 &mips_reg_names[21][0], \
4147 &mips_reg_names[22][0], \
4148 &mips_reg_names[23][0], \
4149 &mips_reg_names[24][0], \
4150 &mips_reg_names[25][0], \
4151 &mips_reg_names[26][0], \
4152 &mips_reg_names[27][0], \
4153 &mips_reg_names[28][0], \
4154 &mips_reg_names[29][0], \
4155 &mips_reg_names[30][0], \
4156 &mips_reg_names[31][0], \
4157 &mips_reg_names[32][0], \
4158 &mips_reg_names[33][0], \
4159 &mips_reg_names[34][0], \
4160 &mips_reg_names[35][0], \
4161 &mips_reg_names[36][0], \
4162 &mips_reg_names[37][0], \
4163 &mips_reg_names[38][0], \
4164 &mips_reg_names[39][0], \
4165 &mips_reg_names[40][0], \
4166 &mips_reg_names[41][0], \
4167 &mips_reg_names[42][0], \
4168 &mips_reg_names[43][0], \
4169 &mips_reg_names[44][0], \
4170 &mips_reg_names[45][0], \
4171 &mips_reg_names[46][0], \
4172 &mips_reg_names[47][0], \
4173 &mips_reg_names[48][0], \
4174 &mips_reg_names[49][0], \
4175 &mips_reg_names[50][0], \
4176 &mips_reg_names[51][0], \
4177 &mips_reg_names[52][0], \
4178 &mips_reg_names[53][0], \
4179 &mips_reg_names[54][0], \
4180 &mips_reg_names[55][0], \
4181 &mips_reg_names[56][0], \
4182 &mips_reg_names[57][0], \
4183 &mips_reg_names[58][0], \
4184 &mips_reg_names[59][0], \
4185 &mips_reg_names[60][0], \
4186 &mips_reg_names[61][0], \
4187 &mips_reg_names[62][0], \
4188 &mips_reg_names[63][0], \
4189 &mips_reg_names[64][0], \
4190 &mips_reg_names[65][0], \
4191 &mips_reg_names[66][0], \
225b8835 4192 &mips_reg_names[67][0], \
39dffea3 4193 &mips_reg_names[68][0], \
b8eb88d0
ILT		 4194 &mips_reg_names[69][0], \
4195 &mips_reg_names[70][0], \
4196 &mips_reg_names[71][0], \
4197 &mips_reg_names[72][0], \
4198 &mips_reg_names[73][0], \
4199 &mips_reg_names[74][0], \
4200 &mips_reg_names[75][0], \
e75b25e7
MM		 4201}
4202
46cca58c
RS		 4203/* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4204 So define this for it. */
4205#define DEBUG_REGISTER_NAMES \
4206{ \
4207 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4208 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4209 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
07e2e444 4210 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
46cca58c
RS		 4211 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4212 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4213 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4214 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
b8eb88d0
ILT		 4215 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4216 "$fcc5","$fcc6","$fcc7","$rap" \
46cca58c
RS		 4217}
4218
e75b25e7
MM		 4219/* If defined, a C initializer for an array of structures
4220 containing a name and a register number. This macro defines
4221 additional names for hard registers, thus allowing the `asm'
4222 option in declarations to refer to registers using alternate
4223 names.
4224
4225 We define both names for the integer registers here. */
4226
4227#define ADDITIONAL_REGISTER_NAMES \
4228{ \
4229 { "$0", 0 + GP_REG_FIRST }, \
4230 { "$1", 1 + GP_REG_FIRST }, \
4231 { "$2", 2 + GP_REG_FIRST }, \
4232 { "$3", 3 + GP_REG_FIRST }, \
4233 { "$4", 4 + GP_REG_FIRST }, \
4234 { "$5", 5 + GP_REG_FIRST }, \
4235 { "$6", 6 + GP_REG_FIRST }, \
4236 { "$7", 7 + GP_REG_FIRST }, \
4237 { "$8", 8 + GP_REG_FIRST }, \
4238 { "$9", 9 + GP_REG_FIRST }, \
4239 { "$10", 10 + GP_REG_FIRST }, \
4240 { "$11", 11 + GP_REG_FIRST }, \
4241 { "$12", 12 + GP_REG_FIRST }, \
4242 { "$13", 13 + GP_REG_FIRST }, \
4243 { "$14", 14 + GP_REG_FIRST }, \
4244 { "$15", 15 + GP_REG_FIRST }, \
4245 { "$16", 16 + GP_REG_FIRST }, \
4246 { "$17", 17 + GP_REG_FIRST }, \
4247 { "$18", 18 + GP_REG_FIRST }, \
4248 { "$19", 19 + GP_REG_FIRST }, \
4249 { "$20", 20 + GP_REG_FIRST }, \
4250 { "$21", 21 + GP_REG_FIRST }, \
4251 { "$22", 22 + GP_REG_FIRST }, \
4252 { "$23", 23 + GP_REG_FIRST }, \
4253 { "$24", 24 + GP_REG_FIRST }, \
4254 { "$25", 25 + GP_REG_FIRST }, \
4255 { "$26", 26 + GP_REG_FIRST }, \
4256 { "$27", 27 + GP_REG_FIRST }, \
4257 { "$28", 28 + GP_REG_FIRST }, \
4258 { "$29", 29 + GP_REG_FIRST }, \
4259 { "$30", 30 + GP_REG_FIRST }, \
4260 { "$31", 31 + GP_REG_FIRST }, \
4261 { "$sp", 29 + GP_REG_FIRST }, \
4262 { "$fp", 30 + GP_REG_FIRST }, \
4263 { "at", 1 + GP_REG_FIRST }, \
4264 { "v0", 2 + GP_REG_FIRST }, \
4265 { "v1", 3 + GP_REG_FIRST }, \
4266 { "a0", 4 + GP_REG_FIRST }, \
4267 { "a1", 5 + GP_REG_FIRST }, \
4268 { "a2", 6 + GP_REG_FIRST }, \
4269 { "a3", 7 + GP_REG_FIRST }, \
4270 { "t0", 8 + GP_REG_FIRST }, \
4271 { "t1", 9 + GP_REG_FIRST }, \
4272 { "t2", 10 + GP_REG_FIRST }, \
4273 { "t3", 11 + GP_REG_FIRST }, \
4274 { "t4", 12 + GP_REG_FIRST }, \
4275 { "t5", 13 + GP_REG_FIRST }, \
4276 { "t6", 14 + GP_REG_FIRST }, \
4277 { "t7", 15 + GP_REG_FIRST }, \
4278 { "s0", 16 + GP_REG_FIRST }, \
4279 { "s1", 17 + GP_REG_FIRST }, \
4280 { "s2", 18 + GP_REG_FIRST }, \
4281 { "s3", 19 + GP_REG_FIRST }, \
4282 { "s4", 20 + GP_REG_FIRST }, \
4283 { "s5", 21 + GP_REG_FIRST }, \
4284 { "s6", 22 + GP_REG_FIRST }, \
4285 { "s7", 23 + GP_REG_FIRST }, \
4286 { "t8", 24 + GP_REG_FIRST }, \
4287 { "t9", 25 + GP_REG_FIRST }, \
4288 { "k0", 26 + GP_REG_FIRST }, \
4289 { "k1", 27 + GP_REG_FIRST }, \
4290 { "gp", 28 + GP_REG_FIRST }, \
4291 { "sp", 29 + GP_REG_FIRST }, \
4292 { "fp", 30 + GP_REG_FIRST }, \
4293 { "ra", 31 + GP_REG_FIRST }, \
924706a0 4294 { "$sp", 29 + GP_REG_FIRST }, \
b8eb88d0 4295 { "$fp", 30 + GP_REG_FIRST } \
e75b25e7
MM		 4296}
4297
e75b25e7
MM		 4298/* A C compound statement to output to stdio stream STREAM the
4299 assembler syntax for an instruction operand X. X is an RTL
4300 expression.
4301
4302 CODE is a value that can be used to specify one of several ways
4303 of printing the operand. It is used when identical operands
4304 must be printed differently depending on the context. CODE
4305 comes from the `%' specification that was used to request
4306 printing of the operand. If the specification was just `%DIGIT'
4307 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4308 is the ASCII code for LTR.
4309
4310 If X is a register, this macro should print the register's name.
4311 The names can be found in an array `reg_names' whose type is
4312 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4313
4314 When the machine description has a specification `%PUNCT' (a `%'
4315 followed by a punctuation character), this macro is called with
4316 a null pointer for X and the punctuation character for CODE.
4317
4318 See mips.c for the MIPS specific codes. */
4319
4320#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4321
4322/* A C expression which evaluates to true if CODE is a valid
4323 punctuation character for use in the `PRINT_OPERAND' macro. If
4324 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4325 punctuation characters (except for the standard one, `%') are
4326 used in this way. */
4327
4328#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4329
4330/* A C compound statement to output to stdio stream STREAM the
4331 assembler syntax for an instruction operand that is a memory
4332 reference whose address is ADDR. ADDR is an RTL expression.
4333
4334 On some machines, the syntax for a symbolic address depends on
4335 the section that the address refers to. On these machines,
4336 define the macro `ENCODE_SECTION_INFO' to store the information
4337 into the `symbol_ref', and then check for it here. */
4338
4339#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4340
4341
4342/* A C statement, to be executed after all slot-filler instructions
4343 have been output. If necessary, call `dbr_sequence_length' to
4344 determine the number of slots filled in a sequence (zero if not
4345 currently outputting a sequence), to decide how many no-ops to
4346 output, or whatever.
4347
4348 Don't define this macro if it has nothing to do, but it is
4349 helpful in reading assembly output if the extent of the delay
4350 sequence is made explicit (e.g. with white space).
4351
4352 Note that output routines for instructions with delay slots must
4353 be prepared to deal with not being output as part of a sequence
4354 (i.e. when the scheduling pass is not run, or when no slot
4355 fillers could be found.) The variable `final_sequence' is null
4356 when not processing a sequence, otherwise it contains the
4357 `sequence' rtx being output. */
4358
4359#define DBR_OUTPUT_SEQEND(STREAM) \
4360do \
4361 { \
4362 if (set_nomacro > 0 && --set_nomacro == 0) \
4363 fputs ("\t.set\tmacro\n", STREAM); \
4364 \
4365 if (set_noreorder > 0 && --set_noreorder == 0) \
4366 fputs ("\t.set\treorder\n", STREAM); \
4367 \
4368 dslots_jump_filled++; \
4369 fputs ("\n", STREAM); \
4370 } \
4371while (0)
4372
4373
4374/* How to tell the debugger about changes of source files. Note, the
4375 mips ECOFF format cannot deal with changes of files inside of
4376 functions, which means the output of parser generators like bison
4377 is generally not debuggable without using the -l switch. Lose,
4378 lose, lose. Silicon graphics seems to want all .file's hardwired
4379 to 1. */
4380
4381#ifndef SET_FILE_NUMBER
4382#define SET_FILE_NUMBER() ++num_source_filenames
4383#endif
4384
4385#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4386 mips_output_filename (STREAM, NAME)
4387
ddd5a7c1 4388/* This is defined so that it can be overridden in iris6.h. */
516a2dfd
JW		 4389#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4390do \
4391 { \
4392 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4393 output_quoted_string (STREAM, NAME); \
4394 fputs ("\n", STREAM); \
4395 } \
4396while (0)
4397
e75b25e7
MM		 4398/* This is how to output a note the debugger telling it the line number
4399 to which the following sequence of instructions corresponds.
4400 Silicon graphics puts a label after each .loc. */
4401
4402#ifndef LABEL_AFTER_LOC
4403#define LABEL_AFTER_LOC(STREAM)
4404#endif
4405
b2bcb32d 4406#ifndef ASM_OUTPUT_SOURCE_LINE
e75b25e7
MM		 4407#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4408 mips_output_lineno (STREAM, LINE)
b2bcb32d 4409#endif
e75b25e7 4410
9ec36da5 4411/* The MIPS implementation uses some labels for its own purpose. The
e75b25e7
MM		 4412 following lists what labels are created, and are all formed by the
4413 pattern $L[a-z].*. The machine independent portion of GCC creates
4414 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4415
c5b7917e 4416 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
e75b25e7
MM		 4417 $Lb[0-9]+ Begin blocks for MIPS debug support
4418 $Lc[0-9]+ Label for use in s<xx> operation.
4419 $Le[0-9]+ End blocks for MIPS debug support
987ba558 4420 $Lp\..+ Half-pic labels. */
e75b25e7
MM		 4421
4422/* This is how to output the definition of a user-level label named NAME,
4423 such as the label on a static function or variable NAME.
4424
4425 If we are optimizing the gp, remember that this label has been put
4426 out, so we know not to emit an .extern for it in mips_asm_file_end.
4427 We use one of the common bits in the IDENTIFIER tree node for this,
4428 since those bits seem to be unused, and we don't have any method
4429 of getting the decl nodes from the name. */
4430
e75b25e7
MM		 4431#define ASM_OUTPUT_LABEL(STREAM,NAME) \
4432do { \
4433 assemble_name (STREAM, NAME); \
4434 fputs (":\n", STREAM); \
e75b25e7
MM		 4435} while (0)
4436
31c714e3
MM		 4437
4438/* A C statement (sans semicolon) to output to the stdio stream
4439 STREAM any text necessary for declaring the name NAME of an
4440 initialized variable which is being defined. This macro must
7dac2f89 4441 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
31c714e3
MM		 4442 The argument DECL is the `VAR_DECL' tree node representing the
4443 variable.
4444
4445 If this macro is not defined, then the variable name is defined
4446 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4447
44404b8b 4448#undef ASM_DECLARE_OBJECT_NAME
31c714e3 4449#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
f3b39eba
MM		 4450do \
4451 { \
4452 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4453 HALF_PIC_DECLARE (NAME); \
4454 } \
4455while (0)
31c714e3 4456
e75b25e7
MM		 4457
4458/* This is how to output a command to make the user-level label named NAME
4459 defined for reference from other files. */
4460
e75b25e7
MM		 4461#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4462 do { \
4463 fputs ("\t.globl\t", STREAM); \
4464 assemble_name (STREAM, NAME); \
4465 fputs ("\n", STREAM); \
4466 } while (0)
4467
31c714e3 4468/* This says how to define a global common symbol. */
e75b25e7 4469
919509ce
DN		 4470#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4471 do { \
4472 /* If the target wants uninitialized const declarations in \
4473 .rdata then don't put them in .comm */ \
4474 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4475 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4476 && (DECL_INITIAL (DECL) == 0 \
4477 || DECL_INITIAL (DECL) == error_mark_node)) \
4478 { \
4479 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4480 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4481 \
4482 READONLY_DATA_SECTION (); \
4483 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4484 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4485 (SIZE)); \
4486 } \
4487 else \
7b2e1077
EC		 4488 { \
4489 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u", \
919509ce 4490 (SIZE)); \
7b2e1077
EC		 4491 fprintf ((STREAM), "%u\n", ((unsigned)(ALIGN) / BITS_PER_UNIT));\
4492 } \
919509ce
DN		 4493 } while (0)
4494
e75b25e7 4495
c5b7917e 4496/* This says how to define a local common symbol (ie, not visible to
31c714e3 4497 linker). */
e75b25e7
MM		 4498
4499#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
69520b54 4500 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
e75b25e7
MM		 4501
4502
4503/* This says how to output an external. It would be possible not to
4504 output anything and let undefined symbol become external. However
4505 the assembler uses length information on externals to allocate in
4506 data/sdata bss/sbss, thereby saving exec time. */
4507
4508#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4509 mips_output_external(STREAM,DECL,NAME)
4510
4511/* This says what to print at the end of the assembly file */
44404b8b 4512#undef ASM_FILE_END
e75b25e7
MM		 4513#define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4514
4515
f99ffb60
RH		 4516/* Play switch file games if we're optimizing the global pointer. */
4517
4518#undef TEXT_SECTION
4519#define TEXT_SECTION() \
4520do { \
4521 extern FILE *asm_out_text_file; \
4522 if (TARGET_FILE_SWITCHING) \
4523 asm_out_file = asm_out_text_file; \
4524 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4525 fputc ('\n', asm_out_file); \
4526} while (0)
4527
4528
e75b25e7
MM		 4529/* This is how to declare a function name. The actual work of
4530 emitting the label is moved to function_prologue, so that we can
4531 get the line number correctly emitted before the .ent directive,
f99ffb60 4532 and after any .file directives. */
e75b25e7 4533
44404b8b 4534#undef ASM_DECLARE_FUNCTION_NAME
f99ffb60
RH		 4535#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4536 HALF_PIC_DECLARE (NAME)
e75b25e7 4537
e75b25e7
MM		 4538/* This is how to output an internal numbered label where
4539 PREFIX is the class of label and NUM is the number within the class. */
4540
44404b8b 4541#undef ASM_OUTPUT_INTERNAL_LABEL
e75b25e7 4542#define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
6ae1498b 4543 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
e75b25e7
MM		 4544
4545/* This is how to store into the string LABEL
4546 the symbol_ref name of an internal numbered label where
4547 PREFIX is the class of label and NUM is the number within the class.
4548 This is suitable for output with `assemble_name'. */
4549
44404b8b 4550#undef ASM_GENERATE_INTERNAL_LABEL
e75b25e7 4551#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4f70758f 4552 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
e75b25e7 4553
e75b25e7
MM		 4554/* This is how to output an element of a case-vector that is absolute. */
4555
4556#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
6ae1498b 4557 fprintf (STREAM, "\t%s\t%sL%d\n", \
1eeed24e 4558 Pmode == DImode ? ".dword" : ".word", \
6ae1498b 4559 LOCAL_LABEL_PREFIX, \
876c09d3 4560 VALUE)
e75b25e7
MM		 4561
4562/* This is how to output an element of a case-vector that is relative.
e0bfcea5
ILT		 4563 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4564 TARGET_EMBEDDED_PIC). */
e75b25e7 4565
33f7f353 4566#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
e0bfcea5 4567do { \
2bcb2ab3
GK		 4568 if (TARGET_MIPS16) \
4569 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4570 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4571 else if (TARGET_EMBEDDED_PIC) \
6ae1498b 4572 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
1eeed24e 4573 Pmode == DImode ? ".dword" : ".word", \
6ae1498b 4574 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
a53f72db 4575 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
6ae1498b 4576 fprintf (STREAM, "\t%s\t%sL%d\n", \
1eeed24e 4577 Pmode == DImode ? ".gpdword" : ".gpword", \
6ae1498b 4578 LOCAL_LABEL_PREFIX, VALUE); \
516a2dfd 4579 else \
b2d8cf33 4580 fprintf (STREAM, "\t%s\t%sL%d\n", \
1eeed24e 4581 Pmode == DImode ? ".dword" : ".word", \
b2d8cf33 4582 LOCAL_LABEL_PREFIX, VALUE); \
e0bfcea5
ILT		 4583} while (0)
4584
2bcb2ab3
GK		 4585/* When generating embedded PIC or mips16 code we want to put the jump
4586 table in the .text section. In all other cases, we want to put the
4587 jump table in the .rdata section. Unfortunately, we can't use
e0bfcea5
ILT		 4588 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4589 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4590 section if appropriate. */
44404b8b 4591#undef ASM_OUTPUT_CASE_LABEL
e0bfcea5
ILT		 4592#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4593do { \
2bcb2ab3
GK		 4594 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4595 function_section (current_function_decl); \
e0bfcea5
ILT		 4596 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4597} while (0)
e75b25e7
MM		 4598
4599/* This is how to output an assembler line
4600 that says to advance the location counter
4601 to a multiple of 2**LOG bytes. */
4602
4603#define ASM_OUTPUT_ALIGN(STREAM,LOG) \
a688e0b7 4604 fprintf (STREAM, "\t.align\t%d\n", (LOG))
e75b25e7 4605
38e01259 4606/* This is how to output an assembler line to advance the location
e75b25e7
MM		 4607 counter by SIZE bytes. */
4608
44404b8b 4609#undef ASM_OUTPUT_SKIP
e75b25e7
MM		 4610#define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4611 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4612
e75b25e7 4613/* This is how to output a string. */
44404b8b 4614#undef ASM_OUTPUT_ASCII
e75b25e7 4615#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
b3276c7a 4616 mips_output_ascii (STREAM, STRING, LEN)
e75b25e7
MM		 4617
4618/* Handle certain cpp directives used in header files on sysV. */
4619#define SCCS_DIRECTIVE
4620
4621/* Output #ident as a in the read-only data section. */
0e5a4ad8 4622#undef ASM_OUTPUT_IDENT
e75b25e7
MM		 4623#define ASM_OUTPUT_IDENT(FILE, STRING) \
4624{ \
3cce094d 4625 const char *p = STRING; \
e75b25e7
MM		 4626 int size = strlen (p) + 1; \
4627 rdata_section (); \
4628 assemble_string (p, size); \
4629}
4630\f
b82b0773
MM		 4631/* Default to -G 8 */
4632#ifndef MIPS_DEFAULT_GVALUE
4633#define MIPS_DEFAULT_GVALUE 8
4634#endif
e75b25e7 4635
f3b39eba
MM		 4636/* Define the strings to put out for each section in the object file. */
4637#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4638#define DATA_SECTION_ASM_OP "\t.data" /* large data */
4639#define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4640#define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
44404b8b 4641#undef READONLY_DATA_SECTION
f3b39eba 4642#define READONLY_DATA_SECTION rdata_section
3cf6400d 4643#define SMALL_DATA_SECTION sdata_section
e75b25e7
MM		 4644
4645/* What other sections we support other than the normal .data/.text. */
4646
44404b8b 4647#undef EXTRA_SECTIONS
876c09d3 4648#define EXTRA_SECTIONS in_sdata, in_rdata
e75b25e7
MM		 4649
4650/* Define the additional functions to select our additional sections. */
4651
4652/* on the MIPS it is not a good idea to put constants in the text
4653 section, since this defeats the sdata/data mechanism. This is
4654 especially true when -O is used. In this case an effort is made to
4655 address with faster (gp) register relative addressing, which can
4656 only get at sdata and sbss items (there is no stext !!) However,
4657 if the constant is too large for sdata, and it's readonly, it
987ba558 4658 will go into the .rdata section. */
e75b25e7 4659
44404b8b 4660#undef EXTRA_SECTION_FUNCTIONS
e75b25e7
MM		 4661#define EXTRA_SECTION_FUNCTIONS \
4662void \
4663sdata_section () \
4664{ \
4665 if (in_section != in_sdata) \
4666 { \
4667 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4668 in_section = in_sdata; \
4669 } \
4670} \
4671 \
4672void \
4673rdata_section () \
4674{ \
4675 if (in_section != in_rdata) \
4676 { \
4677 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4678 in_section = in_rdata; \
4679 } \
4680}
4681
4682/* Given a decl node or constant node, choose the section to output it in
4683 and select that section. */
4684
44404b8b 4685#undef SELECT_RTX_SECTION
201556f0
JJ		 4686#define SELECT_RTX_SECTION(MODE, RTX, ALIGN) \
4687 mips_select_rtx_section (MODE, RTX)
e75b25e7 4688
44404b8b 4689#undef SELECT_SECTION
201556f0
JJ		 4690#define SELECT_SECTION(DECL, RELOC, ALIGN) \
4691 mips_select_section (DECL, RELOC)
e75b25e7
MM		 4692
4693\f
4694/* Store in OUTPUT a string (made with alloca) containing
4695 an assembler-name for a local static variable named NAME.
4696 LABELNO is an integer which is different for each call. */
4697
4698#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4699( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4700 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4701
4702#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4703do \
4704 { \
876c09d3
JW		 4705 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4706 TARGET_64BIT ? "dsubu" : "subu", \
e75b25e7
MM		 4707 reg_names[STACK_POINTER_REGNUM], \
4708 reg_names[STACK_POINTER_REGNUM], \
876c09d3 4709 TARGET_64BIT ? "sd" : "sw", \
e75b25e7
MM		 4710 reg_names[REGNO], \
4711 reg_names[STACK_POINTER_REGNUM]); \
4712 } \
4713while (0)
4714
4715#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4716do \
4717 { \
4718 if (! set_noreorder) \
4719 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4720 \
4721 dslots_load_total++; \
4722 dslots_load_filled++; \
876c09d3
JW		 4723 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4724 TARGET_64BIT ? "ld" : "lw", \
e75b25e7
MM		 4725 reg_names[REGNO], \
4726 reg_names[STACK_POINTER_REGNUM], \
876c09d3 4727 TARGET_64BIT ? "daddu" : "addu", \
e75b25e7
MM		 4728 reg_names[STACK_POINTER_REGNUM], \
4729 reg_names[STACK_POINTER_REGNUM]); \
4730 \
4731 if (! set_noreorder) \
4732 fprintf (STREAM, "\t.set\treorder\n"); \
4733 } \
4734while (0)
4735
4baed42f
DE		 4736/* How to start an assembler comment.
4737 The leading space is important (the mips native assembler requires it). */
e75b25e7 4738#ifndef ASM_COMMENT_START
4baed42f 4739#define ASM_COMMENT_START " #"
e75b25e7 4740#endif
e75b25e7
MM		 4741\f
4742
4743/* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4744 and mips-tdump.c to print them out.
4745
4746 These must match the corresponding definitions in gdb/mipsread.c.
987ba558 4747 Unfortunately, gcc and gdb do not currently share any directories. */
e75b25e7
MM		 4748
4749#define CODE_MASK 0x8F300
4750#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4751#define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4752#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3f1f8d8c
MM		 4753
4754\f
4755/* Default definitions for size_t and ptrdiff_t. */
4756
4757#ifndef SIZE_TYPE
876c09d3 4758#define NO_BUILTIN_SIZE_TYPE
79e69af0 4759#define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
3f1f8d8c
MM		 4760#endif
4761
4762#ifndef PTRDIFF_TYPE
876c09d3 4763#define NO_BUILTIN_PTRDIFF_TYPE
79e69af0 4764#define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
3f1f8d8c 4765#endif
28174a14
MS		 4766
4767/* See mips_expand_prologue's use of loadgp for when this should be
4768 true. */
4769
a53f72db
GRK		 4770#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4771 && mips_abi != ABI_32 \
4772 && mips_abi != ABI_O64)
2bcb2ab3
GK		 4773\f
4774/* In mips16 mode, we need to look through the function to check for
4775 PC relative loads that are out of range. */
4776#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4777
4778/* We need to use a special set of functions to handle hard floating
4779 point code in mips16 mode. */
337e2b69
ILT		 4780
4781#ifndef INIT_SUBTARGET_OPTABS
4782#define INIT_SUBTARGET_OPTABS
4783#endif
4784
4785#define INIT_TARGET_OPTABS \
4786do \
4787 { \
2bcb2ab3
GK		 4788 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4789 INIT_SUBTARGET_OPTABS; \
4790 else \
4791 { \
4792 add_optab->handlers[(int) SFmode].libfunc = \
e85cde9a 4793 init_one_libfunc ("__mips16_addsf3"); \
2bcb2ab3 4794 sub_optab->handlers[(int) SFmode].libfunc = \
e85cde9a 4795 init_one_libfunc ("__mips16_subsf3"); \
2bcb2ab3 4796 smul_optab->handlers[(int) SFmode].libfunc = \
e85cde9a 4797 init_one_libfunc ("__mips16_mulsf3"); \
ef89d648 4798 sdiv_optab->handlers[(int) SFmode].libfunc = \
e85cde9a 4799 init_one_libfunc ("__mips16_divsf3"); \
2bcb2ab3 4800 \
e85cde9a
JL		 4801 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4802 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4803 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4804 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4805 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4806 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
2bcb2ab3
GK		 4807 \
4808 floatsisf_libfunc = \
e85cde9a 4809 init_one_libfunc ("__mips16_floatsisf"); \
2bcb2ab3 4810 fixsfsi_libfunc = \
e85cde9a 4811 init_one_libfunc ("__mips16_fixsfsi"); \
2bcb2ab3
GK		 4812 \
4813 if (TARGET_DOUBLE_FLOAT) \
4814 { \
4815 add_optab->handlers[(int) DFmode].libfunc = \
e85cde9a 4816 init_one_libfunc ("__mips16_adddf3"); \
2bcb2ab3 4817 sub_optab->handlers[(int) DFmode].libfunc = \
e85cde9a 4818 init_one_libfunc ("__mips16_subdf3"); \
2bcb2ab3 4819 smul_optab->handlers[(int) DFmode].libfunc = \
e85cde9a 4820 init_one_libfunc ("__mips16_muldf3"); \
ef89d648 4821 sdiv_optab->handlers[(int) DFmode].libfunc = \
e85cde9a 4822 init_one_libfunc ("__mips16_divdf3"); \
2bcb2ab3
GK		 4823 \
4824 extendsfdf2_libfunc = \
e85cde9a 4825 init_one_libfunc ("__mips16_extendsfdf2"); \
2bcb2ab3 4826 truncdfsf2_libfunc = \
e85cde9a 4827 init_one_libfunc ("__mips16_truncdfsf2"); \
2bcb2ab3
GK		 4828 \
4829 eqdf2_libfunc = \
e85cde9a 4830 init_one_libfunc ("__mips16_eqdf2"); \
2bcb2ab3 4831 nedf2_libfunc = \
e85cde9a 4832 init_one_libfunc ("__mips16_nedf2"); \
2bcb2ab3 4833 gtdf2_libfunc = \
e85cde9a 4834 init_one_libfunc ("__mips16_gtdf2"); \
2bcb2ab3 4835 gedf2_libfunc = \
e85cde9a 4836 init_one_libfunc ("__mips16_gedf2"); \
2bcb2ab3 4837 ltdf2_libfunc = \
e85cde9a 4838 init_one_libfunc ("__mips16_ltdf2"); \
2bcb2ab3 4839 ledf2_libfunc = \
e85cde9a 4840 init_one_libfunc ("__mips16_ledf2"); \
2bcb2ab3
GK		 4841 \
4842 floatsidf_libfunc = \
e85cde9a 4843 init_one_libfunc ("__mips16_floatsidf"); \
2bcb2ab3 4844 fixdfsi_libfunc = \
e85cde9a 4845 init_one_libfunc ("__mips16_fixdfsi"); \
2bcb2ab3
GK		 4846 } \
4847 } \
337e2b69
ILT		 4848 } \
4849while (0)
GNU Compiler Collection
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