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Use byte offsets in SUBREGs instead of words.
[gcc.git] / gcc / config / mips / mips.c
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cee98a59 1/* Subroutines for insn-output.c for MIPS
214be03f 2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
d07bec95 3 1999, 2000, 2001 Free Software Foundation, Inc.
cee98a59 4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
b2a68403 5 Changes by Michael Meissner, meissner@osf.org.
147255d8
JW		 6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
cee98a59
MM		 8
9This file is part of GNU CC.
10
11GNU CC is free software; you can redistribute it and/or modify
12it under the terms of the GNU General Public License as published by
13the Free Software Foundation; either version 2, or (at your option)
14any later version.
15
16GNU CC is distributed in the hope that it will be useful,
17but WITHOUT ANY WARRANTY; without even the implied warranty of
18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19GNU General Public License for more details.
20
21You should have received a copy of the GNU General Public License
22along with GNU CC; see the file COPYING. If not, write to
0e29e3c9
RK		 23the Free Software Foundation, 59 Temple Place - Suite 330,
24Boston, MA 02111-1307, USA. */
cee98a59 25
147255d8
JW		 26/* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
29
cee98a59 30#include "config.h"
50b2596f
KG		 31#include "system.h"
32#include <signal.h>
cee98a59
MM		 33#include "rtl.h"
34#include "regs.h"
35#include "hard-reg-set.h"
36#include "real.h"
37#include "insn-config.h"
38#include "conditions.h"
cee98a59 39#include "insn-attr.h"
cee98a59 40#include "recog.h"
50b2596f 41#include "toplev.h"
c5c76735
JL		 42#include "output.h"
43
cee98a59 44#include "tree.h"
49ad7cfa 45#include "function.h"
cee98a59
MM		 46#include "expr.h"
47#include "flags.h"
2bcb2ab3 48#include "reload.h"
50b2596f 49#include "output.h"
bd9f1972 50#include "tm_p.h"
d07d525a 51#include "ggc.h"
cee98a59 52
c7391272 53#if defined(USG) || !defined(HAVE_STAB_H)
cee98a59
MM		 54#include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
55#else
56#include <stab.h> /* On BSD, use the system's stab.h. */
57#endif /* not USG */
58
59#ifdef __GNU_STAB__
60#define STAB_CODE_TYPE enum __stab_debug_code
61#else
62#define STAB_CODE_TYPE int
63#endif
64
bd9f1972 65extern tree lookup_name PARAMS ((tree));
cee98a59 66
34b650b3
MM		 67/* Enumeration for all of the relational tests, so that we can build
68 arrays indexed by the test type, and not worry about the order
69 of EQ, NE, etc. */
70
71enum internal_test {
72 ITEST_EQ,
73 ITEST_NE,
74 ITEST_GT,
75 ITEST_GE,
76 ITEST_LT,
77 ITEST_LE,
78 ITEST_GTU,
79 ITEST_GEU,
80 ITEST_LTU,
81 ITEST_LEU,
82 ITEST_MAX
83 };
84
881060d0
JL		 85
86struct constant;
f6da8bc3
KG		 87static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
88static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
881060d0 89 enum machine_mode));
f6da8bc3 90static int m16_check_op PARAMS ((rtx, int, int, int));
c94c9817
MM		 91static void block_move_loop PARAMS ((rtx, rtx,
92 unsigned int,
93 int,
94 rtx, rtx));
f6da8bc3
KG		 95static void block_move_call PARAMS ((rtx, rtx, rtx));
96static FILE *mips_make_temp_file PARAMS ((void));
97static void save_restore_insns PARAMS ((int, rtx,
881060d0 98 long, FILE *));
f6da8bc3
KG		 99static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
100static void mips16_fp_args PARAMS ((FILE *, int, int));
101static void build_mips16_function_stub PARAMS ((FILE *));
102static void mips16_optimize_gp PARAMS ((rtx));
103static rtx add_constant PARAMS ((struct constant **,
881060d0
JL		 104 rtx,
105 enum machine_mode));
f6da8bc3 106static void dump_constants PARAMS ((struct constant *,
881060d0 107 rtx));
f6da8bc3
KG		 108static rtx mips_find_symbol PARAMS ((rtx));
109static void abort_with_insn PARAMS ((rtx, const char *))
e2fe6aba 110 ATTRIBUTE_NORETURN;
f6da8bc3
KG		 111static int symbolic_expression_p PARAMS ((rtx));
112static void mips_add_gc_roots PARAMS ((void));
881060d0 113
cee98a59
MM		 114/* Global variables for machine-dependent things. */
115
116/* Threshold for data being put into the small data/bss area, instead
117 of the normal data area (references to the small data/bss area take
118 1 instruction, and use the global pointer, references to the normal
119 data area takes 2 instructions). */
120int mips_section_threshold = -1;
121
122/* Count the number of .file directives, so that .loc is up to date. */
123int num_source_filenames = 0;
124
cee98a59
MM		 125/* Count the number of sdb related labels are generated (to find block
126 start and end boundaries). */
127int sdb_label_count = 0;
128
ddd5a7c1 129/* Next label # for each statement for Silicon Graphics IRIS systems. */
cee98a59
MM		 130int sym_lineno = 0;
131
132/* Non-zero if inside of a function, because the stupid MIPS asm can't
133 handle .files inside of functions. */
134int inside_function = 0;
135
cee98a59
MM		 136/* Files to separate the text and the data output, so that all of the data
137 can be emitted before the text, which will mean that the assembler will
138 generate smaller code, based on the global pointer. */
139FILE *asm_out_data_file;
140FILE *asm_out_text_file;
141
142/* Linked list of all externals that are to be emitted when optimizing
143 for the global pointer if they haven't been declared by the end of
144 the program with an appropriate .comm or initialization. */
145
f5963e61
JL		 146struct extern_list
147{
cee98a59 148 struct extern_list *next; /* next external */
bd9f1972 149 const char *name; /* name of the external */
cee98a59
MM		 150 int size; /* size in bytes */
151} *extern_head = 0;
152
cee98a59 153/* Name of the file containing the current function. */
e2fe6aba 154const char *current_function_file = "";
cee98a59
MM		 155
156/* Warning given that Mips ECOFF can't support changing files
157 within a function. */
158int file_in_function_warning = FALSE;
159
c831afd5 160/* Whether to suppress issuing .loc's because the user attempted
cee98a59
MM		 161 to change the filename within a function. */
162int ignore_line_number = FALSE;
163
164/* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
165int set_noreorder;
166int set_noat;
167int set_nomacro;
168int set_volatile;
169
170/* The next branch instruction is a branch likely, not branch normal. */
171int mips_branch_likely;
172
173/* Count of delay slots and how many are filled. */
174int dslots_load_total;
175int dslots_load_filled;
176int dslots_jump_total;
177int dslots_jump_filled;
178
179/* # of nops needed by previous insn */
180int dslots_number_nops;
181
182/* Number of 1/2/3 word references to data items (ie, not jal's). */
183int num_refs[3];
184
185/* registers to check for load delay */
186rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
187
a0b6cdee
GM		 188/* Cached operands, and operator to compare for use in set/branch/trap
189 on condition codes. */
cee98a59
MM		 190rtx branch_cmp[2];
191
192/* what type of branch to use */
193enum cmp_type branch_type;
194
6f3c667f
MM		 195/* Number of previously seen half-pic pointers and references. */
196static int prev_half_pic_ptrs = 0;
197static int prev_half_pic_refs = 0;
198
cee98a59
MM		 199/* which cpu are we scheduling for */
200enum processor_type mips_cpu;
201
202/* which instruction set architecture to use. */
203int mips_isa;
204
ade6c319 205#ifdef MIPS_ABI_DEFAULT
04bd620d 206/* Which ABI to use. This is defined to a constant in mips.h if the target
ade6c319 207 doesn't support multiple ABIs. */
04bd620d 208int mips_abi;
ade6c319
JW		 209#endif
210
cee98a59 211/* Strings to hold which cpu and instruction set architecture to use. */
e2fe6aba
KG		 212const char *mips_cpu_string; /* for -mcpu=<xxx> */
213const char *mips_isa_string; /* for -mips{1,2,3,4} */
214const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
cee98a59 215
2bcb2ab3
GK		 216/* Whether we are generating mips16 code. This is a synonym for
217 TARGET_MIPS16, and exists for use as an attribute. */
218int mips16;
219
220/* This variable is set by -mno-mips16. We only care whether
221 -mno-mips16 appears or not, and using a string in this fashion is
222 just a way to avoid using up another bit in target_flags. */
e2fe6aba 223const char *mips_no_mips16_string;
2bcb2ab3 224
3ce1ba83
GRK		 225/* This is only used to determine if an type size setting option was
226 explicitly specified (-mlong64, -mint64, -mlong32). The specs
227 set this option if such an option is used. */
d8c8a706 228const char *mips_explicit_type_size_string;
3ce1ba83 229
2bcb2ab3
GK		 230/* Whether we are generating mips16 hard float code. In mips16 mode
231 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
232 -msoft-float was not specified by the user, which means that we
233 should arrange to call mips32 hard floating point code. */
234int mips16_hard_float;
235
236/* This variable is set by -mentry. We only care whether -mentry
237 appears or not, and using a string in this fashion is just a way to
238 avoid using up another bit in target_flags. */
e2fe6aba 239const char *mips_entry_string;
2bcb2ab3
GK		 240
241/* Whether we should entry and exit pseudo-ops in mips16 mode. */
242int mips_entry;
243
910628b8
JW		 244/* If TRUE, we split addresses into their high and low parts in the RTL. */
245int mips_split_addresses;
246
ffa9d0b1 247/* Generating calls to position independent functions? */
1d6ce736 248enum mips_abicalls_type mips_abicalls;
ffa9d0b1 249
147255d8
JW		 250/* High and low marks for floating point values which we will accept
251 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
252 initialized in override_options. */
253REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
254
bfed8dac 255/* Mode used for saving/restoring general purpose registers. */
b3fb0b5e 256static enum machine_mode gpr_mode;
bfed8dac 257
cee98a59
MM		 258/* Array giving truth value on whether or not a given hard register
259 can support a given mode. */
260char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
261
262/* Current frame information calculated by compute_frame_size. */
263struct mips_frame_info current_frame_info;
264
265/* Zero structure to initialize current_frame_info. */
266struct mips_frame_info zero_frame_info;
267
c831afd5
MM		 268/* Temporary filename used to buffer .text until end of program
269 for -mgpopt. */
270static char *temp_filename;
271
92544bdf
ILT		 272/* Pseudo-reg holding the address of the current function when
273 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
274 by mips_finalize_pic if it was created. */
275rtx embedded_pic_fnaddr_rtx;
276
2bcb2ab3
GK		 277/* The length of all strings seen when compiling for the mips16. This
278 is used to tell how many strings are in the constant pool, so that
279 we can see if we may have an overflow. This is reset each time the
280 constant pool is output. */
281int mips_string_length;
282
283/* Pseudo-reg holding the value of $28 in a mips16 function which
284 refers to GP relative global variables. */
285rtx mips16_gp_pseudo_rtx;
286
287/* In mips16 mode, we build a list of all the string constants we see
288 in a particular function. */
289
290struct string_constant
291{
292 struct string_constant *next;
bd9f1972 293 const char *label;
2bcb2ab3
GK		 294};
295
296static struct string_constant *string_constants;
297
cee98a59
MM		 298/* List of all MIPS punctuation characters used by print_operand. */
299char mips_print_operand_punct[256];
300
301/* Map GCC register number to debugger register number. */
302int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
303
304/* Buffer to use to enclose a load/store operation with %{ %} to
305 turn on .set volatile. */
306static char volatile_buffer[60];
307
308/* Hardware names for the registers. If -mrnames is used, this
309 will be overwritten with mips_sw_reg_names. */
310
311char mips_reg_names[][8] =
312{
313 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
314 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
315 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
316 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
317 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
318 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
319 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
320 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
b8eb88d0
ILT		 321 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
322 "$fcc5","$fcc6","$fcc7","$rap"
cee98a59
MM		 323};
324
325/* Mips software names for the registers, used to overwrite the
326 mips_reg_names array. */
327
328char mips_sw_reg_names[][8] =
329{
147255d8
JW		 330 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
331 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
332 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
333 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
cee98a59
MM		 334 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
335 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
336 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
337 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
b8eb88d0
ILT		 338 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
339 "$fcc5","$fcc6","$fcc7","$rap"
cee98a59
MM		 340};
341
342/* Map hard register number to register class */
343enum reg_class mips_regno_to_class[] =
344{
2bcb2ab3
GK		 345 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
346 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
cee98a59
MM		 347 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
348 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
2bcb2ab3 349 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
cee98a59 350 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
2bcb2ab3 351 T_REG, GR_REGS, GR_REGS, GR_REGS,
cee98a59
MM		 352 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
353 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
354 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
355 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
356 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
357 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
358 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
359 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
360 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
b987661c 361 HI_REG, LO_REG, HILO_REG, ST_REGS,
b8eb88d0
ILT		 362 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
363 ST_REGS, ST_REGS, ST_REGS, GR_REGS
cee98a59
MM		 364};
365
366/* Map register constraint character to register class. */
367enum reg_class mips_char_to_class[256] =
368{
369 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
370 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
371 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
372 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
373 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
374 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
375 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
376 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
377 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
378 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
379 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
380 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
381 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
382 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
383 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
384 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
385 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
386 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
430 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
431 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
432 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
433};
434
435\f
436/* Return truth value of whether OP can be used as an operands
437 where a register or 16 bit unsigned integer is needed. */
438
439int
440uns_arith_operand (op, mode)
441 rtx op;
442 enum machine_mode mode;
443{
444 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
f5963e61 445 return 1;
cee98a59
MM		 446
447 return register_operand (op, mode);
448}
449
450/* Return truth value of whether OP can be used as an operands
451 where a 16 bit integer is needed */
452
453int
454arith_operand (op, mode)
455 rtx op;
456 enum machine_mode mode;
457{
458 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
f5963e61 459 return 1;
cee98a59 460
2bcb2ab3
GK		 461 /* On the mips16, a GP relative value is a signed 16 bit offset. */
462 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
463 return 1;
464
cee98a59
MM		 465 return register_operand (op, mode);
466}
467
468/* Return truth value of whether OP can be used as an operand in a two
469 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
470
471int
472arith32_operand (op, mode)
473 rtx op;
474 enum machine_mode mode;
475{
476 if (GET_CODE (op) == CONST_INT)
f5963e61 477 return 1;
cee98a59
MM		 478
479 return register_operand (op, mode);
480}
481
482/* Return truth value of whether OP is a integer which fits in 16 bits */
483
484int
485small_int (op, mode)
486 rtx op;
38831dfe 487 enum machine_mode mode ATTRIBUTE_UNUSED;
cee98a59
MM		 488{
489 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
490}
491
33563487 492/* Return truth value of whether OP is a 32 bit integer which is too big to
cee98a59
MM		 493 be loaded with one instruction. */
494
495int
496large_int (op, mode)
497 rtx op;
38831dfe 498 enum machine_mode mode ATTRIBUTE_UNUSED;
cee98a59 499{
85f5e2b6 500 HOST_WIDE_INT value;
cee98a59
MM		 501
502 if (GET_CODE (op) != CONST_INT)
f5963e61 503 return 0;
cee98a59
MM		 504
505 value = INTVAL (op);
cee98a59 506
f5963e61
JL		 507 /* ior reg,$r0,value */
508 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
509 return 0;
cee98a59 510
f5963e61
JL		 511 /* subu reg,$r0,value */
512 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
513 return 0;
cee98a59 514
f5963e61
JL		 515 /* lui reg,value>>16 */
516 if ((value & 0x0000ffff) == 0)
517 return 0;
518
519 return 1;
cee98a59
MM		 520}
521
2bcb2ab3
GK		 522/* Return truth value of whether OP is a register or the constant 0.
523 In mips16 mode, we only accept a register, since the mips16 does
524 not have $0. */
cee98a59
MM		 525
526int
527reg_or_0_operand (op, mode)
528 rtx op;
529 enum machine_mode mode;
530{
531 switch (GET_CODE (op))
532 {
533 case CONST_INT:
2bcb2ab3 534 if (TARGET_MIPS16)
f5963e61
JL		 535 return 0;
536 return INTVAL (op) == 0;
cee98a59
MM		 537
538 case CONST_DOUBLE:
f5963e61
JL		 539 if (TARGET_MIPS16)
540 return 0;
541 return op == CONST0_RTX (mode);
cee98a59
MM		 542
543 case REG:
544 case SUBREG:
545 return register_operand (op, mode);
f5963e61
JL		 546
547 default:
548 break;
cee98a59
MM		 549 }
550
f5963e61 551 return 0;
cee98a59
MM		 552}
553
def72bd2
GRK		 554/* Return truth value of whether OP is a register or the constant 0,
555 even in mips16 mode. */
556
557int
558true_reg_or_0_operand (op, mode)
559 rtx op;
560 enum machine_mode mode;
561{
562 switch (GET_CODE (op))
563 {
564 case CONST_INT:
565 return INTVAL (op) == 0;
566
567 case CONST_DOUBLE:
568 return op == CONST0_RTX (mode);
569
570 case REG:
571 case SUBREG:
572 return register_operand (op, mode);
573
574 default:
575 break;
576 }
577
578 return 0;
579}
580
cee98a59
MM		 581/* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
582
583int
584mips_const_double_ok (op, mode)
585 rtx op;
586 enum machine_mode mode;
587{
85098019
JW		 588 REAL_VALUE_TYPE d;
589
cee98a59 590 if (GET_CODE (op) != CONST_DOUBLE)
f5963e61 591 return 0;
cee98a59 592
79438502 593 if (mode == VOIDmode)
f5963e61 594 return 1;
cee98a59
MM		 595
596 if (mode != SFmode && mode != DFmode)
f5963e61 597 return 0;
cee98a59 598
147255d8 599 if (op == CONST0_RTX (mode))
f5963e61 600 return 1;
cee98a59 601
33563487 602 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
a53f72db 603 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
f5963e61 604 return 0;
33563487 605
85098019 606 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
cee98a59 607
85098019
JW		 608 if (REAL_VALUE_ISNAN (d))
609 return FALSE;
cee98a59 610
85098019
JW		 611 if (REAL_VALUE_NEGATIVE (d))
612 d = REAL_VALUE_NEGATE (d);
cee98a59 613
85098019
JW		 614 if (mode == DFmode)
615 {
616 if (REAL_VALUES_LESS (d, dfhigh)
617 && REAL_VALUES_LESS (dflow, d))
f5963e61 618 return 1;
85098019
JW		 619 }
620 else
621 {
622 if (REAL_VALUES_LESS (d, sfhigh)
623 && REAL_VALUES_LESS (sflow, d))
f5963e61 624 return 1;
cee98a59 625 }
cee98a59 626
f5963e61 627 return 0;
cee98a59
MM		 628}
629
b8eb88d0
ILT		 630/* Accept the floating point constant 1 in the appropriate mode. */
631
632int
633const_float_1_operand (op, mode)
634 rtx op;
635 enum machine_mode mode;
636{
637 REAL_VALUE_TYPE d;
638 static REAL_VALUE_TYPE onedf;
639 static REAL_VALUE_TYPE onesf;
640 static int one_initialized;
641
642 if (GET_CODE (op) != CONST_DOUBLE
643 || mode != GET_MODE (op)
644 || (mode != DFmode && mode != SFmode))
f5963e61 645 return 0;
b8eb88d0
ILT		 646
647 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
648
649 /* We only initialize these values if we need them, since we will
650 never get called unless mips_isa >= 4. */
651 if (! one_initialized)
652 {
653 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
654 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
f5963e61 655 one_initialized = 1;
b8eb88d0
ILT		 656 }
657
658 if (mode == DFmode)
659 return REAL_VALUES_EQUAL (d, onedf);
660 else
661 return REAL_VALUES_EQUAL (d, onesf);
662}
663
2bcb2ab3
GK		 664/* Return true if a memory load or store of REG plus OFFSET in MODE
665 can be represented in a single word on the mips16. */
666
667static int
668mips16_simple_memory_operand (reg, offset, mode)
669 rtx reg;
670 rtx offset;
671 enum machine_mode mode;
672{
c94c9817
MM		 673 unsigned int size;
674 int off;
2bcb2ab3
GK		 675
676 if (mode == BLKmode)
677 {
678 /* We can't tell, because we don't know how the value will
f5963e61 679 eventually be accessed. Returning 0 here does no great
2bcb2ab3 680 harm; it just prevents some possible instruction scheduling. */
f5963e61 681 return 0;
2bcb2ab3
GK		 682 }
683
684 size = GET_MODE_SIZE (mode);
685
686 if (INTVAL (offset) % size != 0)
f5963e61 687 return 0;
2bcb2ab3
GK		 688 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
689 off = 0x100;
690 else
691 off = 0x20;
0da9afa6 692 if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
f5963e61
JL		 693 return 1;
694 return 0;
2bcb2ab3
GK		 695}
696
cee98a59
MM		 697/* Return truth value if a memory operand fits in a single instruction
698 (ie, register + small offset). */
699
700int
701simple_memory_operand (op, mode)
702 rtx op;
703 enum machine_mode mode;
704{
705 rtx addr, plus0, plus1;
cee98a59
MM		 706
707 /* Eliminate non-memory operations */
708 if (GET_CODE (op) != MEM)
f5963e61 709 return 0;
cee98a59
MM		 710
711 /* dword operations really put out 2 instructions, so eliminate them. */
910628b8
JW		 712 /* ??? This isn't strictly correct. It is OK to accept multiword modes
713 here, since the length attributes are being set correctly, but only
714 if the address is offsettable. LO_SUM is not offsettable. */
0da9afa6 715 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
f5963e61 716 return 0;
cee98a59
MM		 717
718 /* Decode the address now. */
719 addr = XEXP (op, 0);
720 switch (GET_CODE (addr))
721 {
722 case REG:
910628b8 723 case LO_SUM:
f5963e61 724 return 1;
cee98a59
MM		 725
726 case CONST_INT:
2bcb2ab3 727 if (TARGET_MIPS16)
f5963e61 728 return 0;
821a8792 729 return SMALL_INT (addr);
cee98a59
MM		 730
731 case PLUS:
732 plus0 = XEXP (addr, 0);
733 plus1 = XEXP (addr, 1);
734 if (GET_CODE (plus0) == REG
f5963e61 735 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
2bcb2ab3
GK		 736 && (! TARGET_MIPS16
737 || mips16_simple_memory_operand (plus0, plus1, mode)))
f5963e61 738 return 1;
cee98a59
MM		 739
740 else if (GET_CODE (plus1) == REG
f5963e61 741 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
2bcb2ab3
GK		 742 && (! TARGET_MIPS16
743 || mips16_simple_memory_operand (plus1, plus0, mode)))
f5963e61 744 return 1;
cee98a59
MM		 745
746 else
f5963e61 747 return 0;
cee98a59
MM		 748
749#if 0
750 /* We used to allow small symbol refs here (ie, stuff in .sdata
751 or .sbss), but this causes some bugs in G++. Also, it won't
752 interfere if the MIPS linker rewrites the store instruction
753 because the function is PIC. */
754
755 case LABEL_REF: /* never gp relative */
756 break;
757
758 case CONST:
759 /* If -G 0, we can never have a GP relative memory operation.
760 Also, save some time if not optimizing. */
147255d8 761 if (!TARGET_GP_OPT)
f5963e61 762 return 0;
cee98a59 763
c831afd5
MM		 764 {
765 rtx offset = const0_rtx;
147255d8 766 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
c831afd5 767 if (GET_CODE (op) != SYMBOL_REF)
f5963e61 768 return 0;
cee98a59 769
c831afd5 770 /* let's be paranoid.... */
147255d8 771 if (! SMALL_INT (offset))
f5963e61 772 return 0;
c831afd5 773 }
f5963e61 774
cee98a59
MM		 775 /* fall through */
776
777 case SYMBOL_REF:
cee98a59
MM		 778 return SYMBOL_REF_FLAG (addr);
779#endif
2bcb2ab3
GK		 780
781 /* This SYMBOL_REF case is for the mips16. If the above case is
782 reenabled, this one should be merged in. */
783 case SYMBOL_REF:
784 /* References to the constant pool on the mips16 use a small
785 offset if the function is small. The only time we care about
786 getting this right is during delayed branch scheduling, so
787 don't need to check until then. The machine_dependent_reorg
788 function will set the total length of the instructions used
789 in the function in current_frame_info. If that is small
790 enough, we know for sure that this is a small offset. It
791 would be better if we could take into account the location of
792 the instruction within the function, but we can't, because we
793 don't know where we are. */
794 if (TARGET_MIPS16
795 && CONSTANT_POOL_ADDRESS_P (addr)
796 && current_frame_info.insns_len > 0)
797 {
798 long size;
799
800 size = current_frame_info.insns_len + get_pool_size ();
801 if (GET_MODE_SIZE (mode) == 4)
802 return size < 4 * 0x100;
803 else if (GET_MODE_SIZE (mode) == 8)
804 return size < 8 * 0x20;
805 else
f5963e61 806 return 0;
2bcb2ab3
GK		 807 }
808
f5963e61
JL		 809 return 0;
810
811 default:
812 break;
cee98a59
MM		 813 }
814
f5963e61 815 return 0;
cee98a59
MM		 816}
817
f5963e61 818/* Return nonzero for a memory address that can be used to load or store
2bcb2ab3
GK		 819 a doubleword. */
820
821int
822double_memory_operand (op, mode)
823 rtx op;
824 enum machine_mode mode;
825{
826 rtx addr;
827
828 if (GET_CODE (op) != MEM
829 || ! memory_operand (op, mode))
830 {
831 /* During reload, we accept a pseudo register if it has an
832 appropriate memory address. If we don't do this, we will
833 wind up reloading into a register, and then reloading that
834 register from memory, when we could just reload directly from
835 memory. */
836 if (reload_in_progress
837 && GET_CODE (op) == REG
838 && REGNO (op) >= FIRST_PSEUDO_REGISTER
839 && reg_renumber[REGNO (op)] < 0
840 && reg_equiv_mem[REGNO (op)] != 0
841 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
f5963e61 842 return 1;
2bcb2ab3 843
f85c8be7
JW		 844 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
845 the same test performed for 'm' in find_reloads. */
846
847 if (reload_in_progress
848 && TARGET_64BIT
849 && (GET_CODE (op) == MEM
850 || (GET_CODE (op) == REG
851 && REGNO (op) >= FIRST_PSEUDO_REGISTER
852 && reg_renumber[REGNO (op)] < 0)))
853 return 1;
854
2bcb2ab3
GK		 855 if (reload_in_progress
856 && TARGET_MIPS16
857 && GET_CODE (op) == MEM)
858 {
859 rtx addr;
860
861 addr = XEXP (op, 0);
862
863 /* During reload on the mips16, we accept a large offset
864 from the frame pointer or the stack pointer. This large
865 address will get reloaded anyhow. */
866 if (GET_CODE (addr) == PLUS
867 && GET_CODE (XEXP (addr, 0)) == REG
0da9afa6 868 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
2bcb2ab3
GK		 869 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
870 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
871 && ! SMALL_INT (XEXP (addr, 1)))
872 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
873 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
f5963e61 874 return 1;
2bcb2ab3
GK		 875
876 /* Similarly, we accept a case where the memory address is
877 itself on the stack, and will be reloaded. */
878 if (GET_CODE (addr) == MEM)
879 {
880 rtx maddr;
881
882 maddr = XEXP (addr, 0);
883 if (GET_CODE (maddr) == PLUS
884 && GET_CODE (XEXP (maddr, 0)) == REG
0da9afa6 885 && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
2bcb2ab3
GK		 886 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
887 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
888 && ! SMALL_INT (XEXP (maddr, 1)))
889 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
890 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
f5963e61 891 return 1;
2bcb2ab3
GK		 892 }
893
894 /* We also accept the same case when we have a 16 bit signed
895 offset mixed in as well. The large address will get
896 reloaded, and the 16 bit offset will be OK. */
897 if (GET_CODE (addr) == PLUS
898 && GET_CODE (XEXP (addr, 0)) == MEM
899 && GET_CODE (XEXP (addr, 1)) == CONST_INT
900 && SMALL_INT (XEXP (addr, 1)))
901 {
902 addr = XEXP (XEXP (addr, 0), 0);
903 if (GET_CODE (addr) == PLUS
904 && GET_CODE (XEXP (addr, 0)) == REG
0da9afa6 905 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
2bcb2ab3
GK		 906 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
907 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
908 && ! SMALL_INT (XEXP (addr, 1)))
909 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
910 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
f5963e61 911 return 1;
2bcb2ab3
GK		 912 }
913 }
914
f5963e61 915 return 0;
2bcb2ab3
GK		 916 }
917
918 if (TARGET_64BIT)
919 {
920 /* In this case we can use an instruction like sd. */
f5963e61 921 return 1;
2bcb2ab3
GK		 922 }
923
924 /* Make sure that 4 added to the address is a valid memory address.
925 This essentially just checks for overflow in an added constant. */
926
927 addr = XEXP (op, 0);
928
929 if (CONSTANT_ADDRESS_P (addr))
f5963e61 930 return 1;
2bcb2ab3
GK		 931
932 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
933 ? SImode
934 : SFmode),
935 plus_constant_for_output (addr, 4));
936}
937
f5963e61 938/* Return nonzero if the code of this rtx pattern is EQ or NE. */
cee98a59
MM		 939
940int
941equality_op (op, mode)
942 rtx op;
943 enum machine_mode mode;
944{
945 if (mode != GET_MODE (op))
f5963e61 946 return 0;
cee98a59 947
f5963e61 948 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
cee98a59
MM		 949}
950
f5963e61 951/* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
cee98a59
MM		 952
953int
954cmp_op (op, mode)
955 rtx op;
956 enum machine_mode mode;
957{
958 if (mode != GET_MODE (op))
f5963e61 959 return 0;
cee98a59 960
f5963e61 961 return GET_RTX_CLASS (GET_CODE (op)) == '<';
cee98a59
MM		 962}
963
a0b6cdee
GM		 964/* Return nonzero if the code is a relational operation suitable for a
965 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
966 We need this in the insn that expands `trap_if' in order to prevent
967 combine from erroneously altering the condition. */
968
969int
970trap_cmp_op (op, mode)
971 rtx op;
972 enum machine_mode mode;
973{
974 if (mode != GET_MODE (op))
975 return 0;
976
977 switch (GET_CODE (op))
978 {
979 case EQ:
980 case NE:
981 case LT:
982 case LTU:
983 case GE:
984 case GEU:
985 return 1;
986
987 default:
988 return 0;
989 }
990}
991
f5963e61 992/* Return nonzero if the operand is either the PC or a label_ref. */
34b650b3
MM		 993
994int
995pc_or_label_operand (op, mode)
996 rtx op;
38831dfe 997 enum machine_mode mode ATTRIBUTE_UNUSED;
34b650b3
MM		 998{
999 if (op == pc_rtx)
f5963e61 1000 return 1;
34b650b3
MM		 1001
1002 if (GET_CODE (op) == LABEL_REF)
f5963e61 1003 return 1;
34b650b3 1004
f5963e61 1005 return 0;
34b650b3
MM		 1006}
1007
50c0000c
RS		 1008/* Test for a valid operand for a call instruction.
1009 Don't allow the arg pointer register or virtual regs
1010 since they may change into reg + const, which the patterns
1011 can't handle yet. */
1012
1013int
1014call_insn_operand (op, mode)
1015 rtx op;
38831dfe 1016 enum machine_mode mode ATTRIBUTE_UNUSED;
50c0000c 1017{
f5963e61
JL		 1018 return (CONSTANT_ADDRESS_P (op)
1019 || (GET_CODE (op) == REG && op != arg_pointer_rtx
1020 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1021 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
910628b8
JW		 1022}
1023
f5963e61 1024/* Return nonzero if OPERAND is valid as a source operand for a move
910628b8
JW		 1025 instruction. */
1026
1027int
1028move_operand (op, mode)
1029 rtx op;
1030 enum machine_mode mode;
1031{
15f3d16a
JL		 1032 /* Accept any general operand after reload has started; doing so
1033 avoids losing if reload does an in-place replacement of a register
1034 with a SYMBOL_REF or CONST. */
910628b8 1035 return (general_operand (op, mode)
15f3d16a 1036 && (! (mips_split_addresses && mips_check_split (op, mode))
f5963e61 1037 || reload_in_progress || reload_completed)
2bcb2ab3
GK		 1038 && ! (TARGET_MIPS16
1039 && GET_CODE (op) == SYMBOL_REF
1040 && ! mips16_constant (op, mode, 1, 0)));
910628b8
JW		 1041}
1042
f5963e61 1043/* Return nonzero if OPERAND is valid as a source operand for movdi.
2a0b0bf5
ILT		 1044 This accepts not only general_operand, but also sign extended
1045 constants and registers. We need to accept sign extended constants
1046 in case a sign extended register which is used in an expression,
1047 and is equivalent to a constant, is spilled. */
1048
1049int
1050movdi_operand (op, mode)
1051 rtx op;
1052 enum machine_mode mode;
1053{
1054 if (TARGET_64BIT
1055 && mode == DImode
1056 && GET_CODE (op) == SIGN_EXTEND
1057 && GET_MODE (op) == DImode
1058 && (GET_MODE (XEXP (op, 0)) == SImode
1059 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1060 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1061 && (register_operand (XEXP (op, 0), SImode)
1062 || immediate_operand (XEXP (op, 0), SImode)))
1063 return 1;
1064
3871c609
GK		 1065 return (general_operand (op, mode)
1066 && ! (TARGET_MIPS16
1067 && GET_CODE (op) == SYMBOL_REF
1068 && ! mips16_constant (op, mode, 1, 0)));
2a0b0bf5
ILT		 1069}
1070
1071/* Like register_operand, but when in 64 bit mode also accept a sign
1072 extend of a 32 bit register, since the value is known to be already
1073 sign extended. */
1074
1075int
1076se_register_operand (op, mode)
1077 rtx op;
1078 enum machine_mode mode;
1079{
1080 if (TARGET_64BIT
1081 && mode == DImode
1082 && GET_CODE (op) == SIGN_EXTEND
1083 && GET_MODE (op) == DImode
1084 && GET_MODE (XEXP (op, 0)) == SImode
1085 && register_operand (XEXP (op, 0), SImode))
1086 return 1;
1087
1088 return register_operand (op, mode);
1089}
1090
1091/* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1092 extend of a 32 bit register, since the value is known to be already
1093 sign extended. */
1094
1095int
1096se_reg_or_0_operand (op, mode)
1097 rtx op;
1098 enum machine_mode mode;
1099{
1100 if (TARGET_64BIT
1101 && mode == DImode
1102 && GET_CODE (op) == SIGN_EXTEND
1103 && GET_MODE (op) == DImode
1104 && GET_MODE (XEXP (op, 0)) == SImode
1105 && register_operand (XEXP (op, 0), SImode))
1106 return 1;
1107
1108 return reg_or_0_operand (op, mode);
1109}
1110
1111/* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1112 extend of a 32 bit register, since the value is known to be already
1113 sign extended. */
1114
1115int
1116se_uns_arith_operand (op, mode)
1117 rtx op;
1118 enum machine_mode mode;
1119{
1120 if (TARGET_64BIT
1121 && mode == DImode
1122 && GET_CODE (op) == SIGN_EXTEND
1123 && GET_MODE (op) == DImode
1124 && GET_MODE (XEXP (op, 0)) == SImode
1125 && register_operand (XEXP (op, 0), SImode))
1126 return 1;
1127
1128 return uns_arith_operand (op, mode);
1129}
1130
1131/* Like arith_operand, but when in 64 bit mode also accept a sign
1132 extend of a 32 bit register, since the value is known to be already
1133 sign extended. */
1134
1135int
1136se_arith_operand (op, mode)
1137 rtx op;
1138 enum machine_mode mode;
1139{
1140 if (TARGET_64BIT
1141 && mode == DImode
1142 && GET_CODE (op) == SIGN_EXTEND
1143 && GET_MODE (op) == DImode
1144 && GET_MODE (XEXP (op, 0)) == SImode
1145 && register_operand (XEXP (op, 0), SImode))
1146 return 1;
1147
1148 return arith_operand (op, mode);
1149}
1150
1151/* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1152 extend of a 32 bit register, since the value is known to be already
1153 sign extended. */
1154
1155int
1156se_nonmemory_operand (op, mode)
1157 rtx op;
1158 enum machine_mode mode;
1159{
1160 if (TARGET_64BIT
1161 && mode == DImode
1162 && GET_CODE (op) == SIGN_EXTEND
1163 && GET_MODE (op) == DImode
1164 && GET_MODE (XEXP (op, 0)) == SImode
1165 && register_operand (XEXP (op, 0), SImode))
1166 return 1;
1167
1168 return nonmemory_operand (op, mode);
1169}
1170
1171/* Like nonimmediate_operand, but when in 64 bit mode also accept a
1172 sign extend of a 32 bit register, since the value is known to be
1173 already sign extended. */
1174
1175int
1176se_nonimmediate_operand (op, mode)
1177 rtx op;
1178 enum machine_mode mode;
1179{
1180 if (TARGET_64BIT
1181 && mode == DImode
1182 && GET_CODE (op) == SIGN_EXTEND
1183 && GET_MODE (op) == DImode
1184 && GET_MODE (XEXP (op, 0)) == SImode
1185 && register_operand (XEXP (op, 0), SImode))
1186 return 1;
1187
1188 return nonimmediate_operand (op, mode);
1189}
1190
2bcb2ab3
GK		 1191/* Accept any operand that can appear in a mips16 constant table
1192 instruction. We can't use any of the standard operand functions
1193 because for these instructions we accept values that are not
1194 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1195
1196int
1197consttable_operand (op, mode)
1198 rtx op;
38831dfe 1199 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1200{
1201 return CONSTANT_P (op);
1202}
1203
f5963e61 1204/* Return nonzero if we split the address into high and low parts. */
910628b8
JW		 1205
1206/* ??? We should also handle reg+array somewhere. We get four
1207 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1208 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1209 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1210 out of the address, then we have 4 instructions to combine. Perhaps
1211 add a 3->2 define_split for combine. */
1212
1213/* ??? We could also split a CONST_INT here if it is a large_int().
1214 However, it doesn't seem to be very useful to have %hi(constant).
1215 We would be better off by doing the masking ourselves and then putting
1216 the explicit high part of the constant in the RTL. This will give better
1217 optimization. Also, %hi(constant) needs assembler changes to work.
1218 There is already a define_split that does this. */
1219
1220int
1221mips_check_split (address, mode)
1222 rtx address;
1223 enum machine_mode mode;
1224{
1225 /* ??? This is the same check used in simple_memory_operand.
1226 We use it here because LO_SUM is not offsettable. */
0da9afa6 1227 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
910628b8
JW		 1228 return 0;
1229
1230 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1231 || (GET_CODE (address) == CONST
1232 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1233 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1234 || GET_CODE (address) == LABEL_REF)
50c0000c 1235 return 1;
910628b8 1236
50c0000c
RS		 1237 return 0;
1238}
c94c9817
MM		 1239
1240/* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1241
1242int
1243mips_reg_mode_ok_for_base_p (reg, mode, strict)
1244 rtx reg;
1245 enum machine_mode mode;
1246 int strict;
1247{
1248 return (strict
1249 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1250 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1251}
1252
1253/* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1254 returns a nonzero value if XINSN is a legitimate address for a
1255 memory operand of the indicated MODE. STRICT is non-zero if this
1256 function is called during reload. */
1257
1258int
1259mips_legitimate_address_p (mode, xinsn, strict)
1260 enum machine_mode mode;
1261 rtx xinsn;
1262 int strict;
1263{
1264 if (TARGET_DEBUG_B_MODE)
1265 {
1266 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1267 strict ? "" : "not ");
1268 GO_DEBUG_RTX (xinsn);
1269 }
1270
1271 /* Check for constant before stripping off SUBREG, so that we don't
1272 accept (subreg (const_int)) which will fail to reload. */
1273 if (CONSTANT_ADDRESS_P (xinsn)
0da9afa6 1274 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
c94c9817
MM		 1275 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1276 return 1;
1277
1278 while (GET_CODE (xinsn) == SUBREG)
1279 xinsn = SUBREG_REG (xinsn);
1280
1281 /* The mips16 can only use the stack pointer as a base register when
1282 loading SImode or DImode values. */
1283 if (GET_CODE (xinsn) == REG
1284 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1285 return 1;
1286
1287 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1288 {
1289 register rtx xlow0 = XEXP (xinsn, 0);
1290 register rtx xlow1 = XEXP (xinsn, 1);
1291
1292 while (GET_CODE (xlow0) == SUBREG)
1293 xlow0 = SUBREG_REG (xlow0);
1294 if (GET_CODE (xlow0) == REG
1295 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1296 && mips_check_split (xlow1, mode))
1297 return 1;
1298 }
1299
1300 if (GET_CODE (xinsn) == PLUS)
1301 {
1302 register rtx xplus0 = XEXP (xinsn, 0);
1303 register rtx xplus1 = XEXP (xinsn, 1);
1304 register enum rtx_code code0;
1305 register enum rtx_code code1;
1306
1307 while (GET_CODE (xplus0) == SUBREG)
1308 xplus0 = SUBREG_REG (xplus0);
1309 code0 = GET_CODE (xplus0);
1310
1311 while (GET_CODE (xplus1) == SUBREG)
1312 xplus1 = SUBREG_REG (xplus1);
1313 code1 = GET_CODE (xplus1);
1314
1315 /* The mips16 can only use the stack pointer as a base register
1316 when loading SImode or DImode values. */
1317 if (code0 == REG
1318 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1319 {
1320 if (code1 == CONST_INT && SMALL_INT (xplus1))
1321 return 1;
1322
1323 /* On the mips16, we represent GP relative offsets in RTL.
1324 These are 16 bit signed values, and can serve as register
1325 offsets. */
1326 if (TARGET_MIPS16
1327 && mips16_gp_offset_p (xplus1))
1328 return 1;
1329
1330 /* For some code sequences, you actually get better code by
1331 pretending that the MIPS supports an address mode of a
1332 constant address + a register, even though the real
1333 machine doesn't support it. This is because the
1334 assembler can use $r1 to load just the high 16 bits, add
1335 in the register, and fold the low 16 bits into the memory
1336 reference, whereas the compiler generates a 4 instruction
1337 sequence. On the other hand, CSE is not as effective.
1338 It would be a win to generate the lui directly, but the
1339 MIPS assembler does not have syntax to generate the
1340 appropriate relocation. */
1341
1342 /* Also accept CONST_INT addresses here, so no else. */
1343 /* Reject combining an embedded PIC text segment reference
1344 with a register. That requires an additional
1345 instruction. */
1346 /* ??? Reject combining an address with a register for the MIPS
1347 64 bit ABI, because the SGI assembler can not handle this. */
1348 if (!TARGET_DEBUG_A_MODE
1349 && (mips_abi == ABI_32
1350 || mips_abi == ABI_O64
1351 || mips_abi == ABI_EABI)
1352 && CONSTANT_ADDRESS_P (xplus1)
1353 && ! mips_split_addresses
1354 && (!TARGET_EMBEDDED_PIC
1355 || code1 != CONST
1356 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
5896d794
CP		 1357 /* When assembling for machines with 64 bit registers,
1358 the assembler will not sign-extend the constant "foo"
1359 in "la x, foo(x)" */
1360 && (!TARGET_64BIT || (INTVAL (xplus1) > 0))
c94c9817
MM		 1361 && !TARGET_MIPS16)
1362 return 1;
1363 }
1364 }
1365
1366 if (TARGET_DEBUG_B_MODE)
1367 GO_PRINTF ("Not a legitimate address\n");
1368
1369 /* The address was not legitimate. */
1370 return 0;
1371}
1372
cee98a59 1373\f
2bcb2ab3
GK		 1374/* We need a lot of little routines to check constant values on the
1375 mips16. These are used to figure out how long the instruction will
1376 be. It would be much better to do this using constraints, but
1377 there aren't nearly enough letters available. */
1378
1379static int
1380m16_check_op (op, low, high, mask)
1381 rtx op;
1382 int low;
1383 int high;
1384 int mask;
1385{
1386 return (GET_CODE (op) == CONST_INT
1387 && INTVAL (op) >= low
1388 && INTVAL (op) <= high
1389 && (INTVAL (op) & mask) == 0);
1390}
1391
1392int
1393m16_uimm3_b (op, mode)
1394 rtx op;
38831dfe 1395 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1396{
1397 return m16_check_op (op, 0x1, 0x8, 0);
1398}
1399
1400int
1401m16_simm4_1 (op, mode)
1402 rtx op;
38831dfe 1403 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1404{
1405 return m16_check_op (op, - 0x8, 0x7, 0);
1406}
1407
1408int
1409m16_nsimm4_1 (op, mode)
1410 rtx op;
38831dfe 1411 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1412{
1413 return m16_check_op (op, - 0x7, 0x8, 0);
1414}
1415
1416int
1417m16_simm5_1 (op, mode)
1418 rtx op;
38831dfe 1419 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1420{
1421 return m16_check_op (op, - 0x10, 0xf, 0);
1422}
1423
1424int
1425m16_nsimm5_1 (op, mode)
1426 rtx op;
38831dfe 1427 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1428{
1429 return m16_check_op (op, - 0xf, 0x10, 0);
1430}
1431
1432int
1433m16_uimm5_4 (op, mode)
1434 rtx op;
38831dfe 1435 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1436{
1437 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1438}
1439
1440int
1441m16_nuimm5_4 (op, mode)
1442 rtx op;
38831dfe 1443 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1444{
1445 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1446}
1447
1448int
1449m16_simm8_1 (op, mode)
1450 rtx op;
38831dfe 1451 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1452{
1453 return m16_check_op (op, - 0x80, 0x7f, 0);
1454}
1455
1456int
1457m16_nsimm8_1 (op, mode)
1458 rtx op;
38831dfe 1459 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1460{
1461 return m16_check_op (op, - 0x7f, 0x80, 0);
1462}
1463
1464int
1465m16_uimm8_1 (op, mode)
1466 rtx op;
38831dfe 1467 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1468{
1469 return m16_check_op (op, 0x0, 0xff, 0);
1470}
1471
1472int
1473m16_nuimm8_1 (op, mode)
1474 rtx op;
38831dfe 1475 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1476{
1477 return m16_check_op (op, - 0xff, 0x0, 0);
1478}
1479
1480int
1481m16_uimm8_m1_1 (op, mode)
1482 rtx op;
38831dfe 1483 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1484{
1485 return m16_check_op (op, - 0x1, 0xfe, 0);
1486}
1487
1488int
1489m16_uimm8_4 (op, mode)
1490 rtx op;
38831dfe 1491 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1492{
1493 return m16_check_op (op, 0x0, 0xff << 2, 3);
1494}
1495
1496int
1497m16_nuimm8_4 (op, mode)
1498 rtx op;
38831dfe 1499 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1500{
1501 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1502}
1503
1504int
1505m16_simm8_8 (op, mode)
1506 rtx op;
38831dfe 1507 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1508{
1509 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1510}
1511
1512int
1513m16_nsimm8_8 (op, mode)
1514 rtx op;
38831dfe 1515 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1516{
1517 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1518}
1519
1520/* References to the string table on the mips16 only use a small
1521 offset if the function is small. See the comment in the SYMBOL_REF
1522 case in simple_memory_operand. We can't check for LABEL_REF here,
1523 because the offset is always large if the label is before the
1524 referencing instruction. */
1525
1526int
1527m16_usym8_4 (op, mode)
1528 rtx op;
38831dfe 1529 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1530{
1531 if (GET_CODE (op) == SYMBOL_REF
1532 && SYMBOL_REF_FLAG (op)
1533 && current_frame_info.insns_len > 0
1534 && XSTR (op, 0)[0] == '*'
1535 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1536 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1537 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1538 < 4 * 0x100))
1539 {
1540 struct string_constant *l;
1541
1542 /* Make sure this symbol is on thelist of string constants to be
1543 output for this function. It is possible that it has already
1544 been output, in which case this requires a large offset. */
1545 for (l = string_constants; l != NULL; l = l->next)
1546 if (strcmp (l->label, XSTR (op, 0)) == 0)
1547 return 1;
1548 }
1549
1550 return 0;
1551}
1552
1553int
1554m16_usym5_4 (op, mode)
1555 rtx op;
38831dfe 1556 enum machine_mode mode ATTRIBUTE_UNUSED;
2bcb2ab3
GK		 1557{
1558 if (GET_CODE (op) == SYMBOL_REF
1559 && SYMBOL_REF_FLAG (op)
1560 && current_frame_info.insns_len > 0
1561 && XSTR (op, 0)[0] == '*'
1562 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1563 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1564 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1565 < 4 * 0x20))
1566 {
1567 struct string_constant *l;
1568
1569 /* Make sure this symbol is on thelist of string constants to be
1570 output for this function. It is possible that it has already
1571 been output, in which case this requires a large offset. */
1572 for (l = string_constants; l != NULL; l = l->next)
1573 if (strcmp (l->label, XSTR (op, 0)) == 0)
1574 return 1;
1575 }
1576
1577 return 0;
1578}
1579\f
85098019
JW		 1580/* Returns an operand string for the given instruction's delay slot,
1581 after updating filled delay slot statistics.
cee98a59
MM		 1582
1583 We assume that operands[0] is the target register that is set.
1584
1585 In order to check the next insn, most of this functionality is moved
1586 to FINAL_PRESCAN_INSN, and we just set the global variables that
1587 it needs. */
1588
85098019
JW		 1589/* ??? This function no longer does anything useful, because final_prescan_insn
1590 now will never emit a nop. */
1591
bd9f1972 1592const char *
cee98a59 1593mips_fill_delay_slot (ret, type, operands, cur_insn)
bd9f1972 1594 const char *ret; /* normal string to return */
cee98a59
MM		 1595 enum delay_type type; /* type of delay */
1596 rtx operands[]; /* operands to use */
1597 rtx cur_insn; /* current insn */
1598{
1599 register rtx set_reg;
1600 register enum machine_mode mode;
f5963e61 1601 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
cee98a59
MM		 1602 register int num_nops;
1603
34b650b3 1604 if (type == DELAY_LOAD || type == DELAY_FCMP)
cee98a59
MM		 1605 num_nops = 1;
1606
1607 else if (type == DELAY_HILO)
1608 num_nops = 2;
1609
1610 else
1611 num_nops = 0;
1612
1613 /* Make sure that we don't put nop's after labels. */
1614 next_insn = NEXT_INSN (cur_insn);
f5963e61 1615 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
cee98a59
MM		 1616 next_insn = NEXT_INSN (next_insn);
1617
1618 dslots_load_total += num_nops;
1619 if (TARGET_DEBUG_F_MODE
1620 || !optimize
1621 || type == DELAY_NONE
f5963e61
JL		 1622 || operands == 0
1623 || cur_insn == 0
1624 || next_insn == 0
cee98a59 1625 || GET_CODE (next_insn) == CODE_LABEL
f5963e61 1626 || (set_reg = operands[0]) == 0)
cee98a59
MM		 1627 {
1628 dslots_number_nops = 0;
f5963e61
JL		 1629 mips_load_reg = 0;
1630 mips_load_reg2 = 0;
1631 mips_load_reg3 = 0;
1632 mips_load_reg4 = 0;
cee98a59
MM		 1633 return ret;
1634 }
1635
1636 set_reg = operands[0];
f5963e61 1637 if (set_reg == 0)
cee98a59
MM		 1638 return ret;
1639
1640 while (GET_CODE (set_reg) == SUBREG)
1641 set_reg = SUBREG_REG (set_reg);
1642
1643 mode = GET_MODE (set_reg);
1644 dslots_number_nops = num_nops;
147255d8
JW		 1645 mips_load_reg = set_reg;
1646 if (GET_MODE_SIZE (mode)
0da9afa6 1647 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
c5c76735 1648 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
147255d8
JW		 1649 else
1650 mips_load_reg2 = 0;
cee98a59
MM		 1651
1652 if (type == DELAY_HILO)
1653 {
c5c76735
JL		 1654 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1655 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
cee98a59
MM		 1656 }
1657 else
1658 {
1659 mips_load_reg3 = 0;
1660 mips_load_reg4 = 0;
1661 }
1662
cee98a59
MM		 1663 return ret;
1664}
1665
1666\f
f5963e61
JL		 1667/* Determine whether a memory reference takes one (based off of the GP
1668 pointer), two (normal), or three (label + reg) instructions, and bump the
1669 appropriate counter for -mstats. */
cee98a59
MM		 1670
1671void
1672mips_count_memory_refs (op, num)
1673 rtx op;
1674 int num;
1675{
1676 int additional = 0;
1677 int n_words = 0;
1678 rtx addr, plus0, plus1;
1679 enum rtx_code code0, code1;
1680 int looping;
1681
1682 if (TARGET_DEBUG_B_MODE)
1683 {
1684 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1685 debug_rtx (op);
1686 }
1687
1688 /* Skip MEM if passed, otherwise handle movsi of address. */
1689 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1690
f5963e61 1691 /* Loop, going through the address RTL. */
cee98a59
MM		 1692 do
1693 {
1694 looping = FALSE;
1695 switch (GET_CODE (addr))
1696 {
1697 case REG:
1698 case CONST_INT:
910628b8 1699 case LO_SUM:
cee98a59
MM		 1700 break;
1701
1702 case PLUS:
1703 plus0 = XEXP (addr, 0);
1704 plus1 = XEXP (addr, 1);
1705 code0 = GET_CODE (plus0);
1706 code1 = GET_CODE (plus1);
1707
1708 if (code0 == REG)
1709 {
1710 additional++;
1711 addr = plus1;
f5963e61 1712 looping = 1;
cee98a59
MM		 1713 continue;
1714 }
1715
1716 if (code0 == CONST_INT)
1717 {
1718 addr = plus1;
f5963e61 1719 looping = 1;
cee98a59
MM		 1720 continue;
1721 }
1722
1723 if (code1 == REG)
1724 {
1725 additional++;
1726 addr = plus0;
f5963e61 1727 looping = 1;
cee98a59
MM		 1728 continue;
1729 }
1730
1731 if (code1 == CONST_INT)
1732 {
1733 addr = plus0;
f5963e61 1734 looping = 1;
cee98a59
MM		 1735 continue;
1736 }
1737
1738 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1739 {
1740 addr = plus0;
f5963e61 1741 looping = 1;
cee98a59
MM		 1742 continue;
1743 }
1744
1745 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1746 {
1747 addr = plus1;
f5963e61 1748 looping = 1;
cee98a59
MM		 1749 continue;
1750 }
1751
1752 break;
1753
1754 case LABEL_REF:
1755 n_words = 2; /* always 2 words */
1756 break;
1757
1758 case CONST:
1759 addr = XEXP (addr, 0);
f5963e61 1760 looping = 1;
cee98a59
MM		 1761 continue;
1762
1763 case SYMBOL_REF:
1764 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1765 break;
f5963e61
JL		 1766
1767 default:
1768 break;
cee98a59
MM		 1769 }
1770 }
1771 while (looping);
1772
1773 if (n_words == 0)
1774 return;
1775
1776 n_words += additional;
1777 if (n_words > 3)
1778 n_words = 3;
1779
1780 num_refs[n_words-1] += num;
1781}
1782
1783\f
f5963e61
JL		 1784/* Return RTL for the offset from the current function to the argument.
1785
1786 ??? Which argument is this? */
92544bdf
ILT		 1787
1788rtx
1789embedded_pic_offset (x)
1790 rtx x;
1791{
1792 if (embedded_pic_fnaddr_rtx == NULL)
40f8d046
JW		 1793 {
1794 rtx seq;
1795
1796 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1797
abc95ed3 1798 /* Output code at function start to initialize the pseudo-reg. */
40f8d046
JW		 1799 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1800 inline functions, because it is called after RTL for the function
1801 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1802 does not get copied, and ends up not matching the rest of the RTL.
1803 This solution works, but means that we get unnecessary code to
abc95ed3 1804 initialize this value every time a function is inlined into another
40f8d046
JW		 1805 function. */
1806 start_sequence ();
1807 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1808 XEXP (DECL_RTL (current_function_decl), 0)));
1809 seq = gen_sequence ();
1810 end_sequence ();
1811 push_topmost_sequence ();
1812 emit_insn_after (seq, get_insns ());
1813 pop_topmost_sequence ();
1814 }
1815
c5c76735
JL		 1816 return
1817 gen_rtx_CONST (Pmode,
1818 gen_rtx_MINUS (Pmode, x,
1819 XEXP (DECL_RTL (current_function_decl), 0)));
92544bdf
ILT		 1820}
1821
cee98a59
MM		 1822/* Return the appropriate instructions to move one operand to another. */
1823
e2fe6aba 1824const char *
cee98a59
MM		 1825mips_move_1word (operands, insn, unsignedp)
1826 rtx operands[];
1827 rtx insn;
1828 int unsignedp;
1829{
e2fe6aba 1830 const char *ret = 0;
cee98a59
MM		 1831 rtx op0 = operands[0];
1832 rtx op1 = operands[1];
1833 enum rtx_code code0 = GET_CODE (op0);
1834 enum rtx_code code1 = GET_CODE (op1);
1835 enum machine_mode mode = GET_MODE (op0);
ddef6bc7
JJ		 1836 int subreg_offset0 = 0;
1837 int subreg_offset1 = 0;
cee98a59
MM		 1838 enum delay_type delay = DELAY_NONE;
1839
1840 while (code0 == SUBREG)
1841 {
ddef6bc7
JJ		 1842 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
1843 GET_MODE (SUBREG_REG (op0)),
1844 SUBREG_BYTE (op0),
1845 GET_MODE (op0));
cee98a59
MM		 1846 op0 = SUBREG_REG (op0);
1847 code0 = GET_CODE (op0);
1848 }
1849
1850 while (code1 == SUBREG)
1851 {
ddef6bc7
JJ		 1852 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
1853 GET_MODE (SUBREG_REG (op1)),
1854 SUBREG_BYTE (op1),
1855 GET_MODE (op1));
cee98a59
MM		 1856 op1 = SUBREG_REG (op1);
1857 code1 = GET_CODE (op1);
1858 }
1859
b8eb88d0
ILT		 1860 /* For our purposes, a condition code mode is the same as SImode. */
1861 if (mode == CCmode)
1862 mode = SImode;
1863
cee98a59
MM		 1864 if (code0 == REG)
1865 {
ddef6bc7 1866 int regno0 = REGNO (op0) + subreg_offset0;
cee98a59
MM		 1867
1868 if (code1 == REG)
1869 {
ddef6bc7 1870 int regno1 = REGNO (op1) + subreg_offset1;
cee98a59
MM		 1871
1872 /* Just in case, don't do anything for assigning a register
1873 to itself, unless we are filling a delay slot. */
1874 if (regno0 == regno1 && set_nomacro == 0)
1875 ret = "";
1876
1877 else if (GP_REG_P (regno0))
1878 {
1879 if (GP_REG_P (regno1))
1880 ret = "move\t%0,%1";
1881
1882 else if (MD_REG_P (regno1))
1883 {
1884 delay = DELAY_HILO;
225b8835
ILT		 1885 if (regno1 != HILO_REGNUM)
1886 ret = "mf%1\t%0";
1887 else
1888 ret = "mflo\t%0";
cee98a59
MM		 1889 }
1890
76ee8042 1891 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
b8eb88d0
ILT		 1892 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1893
cee98a59
MM		 1894 else
1895 {
1896 delay = DELAY_LOAD;
1897 if (FP_REG_P (regno1))
1898 ret = "mfc1\t%0,%1";
1899
76ee8042 1900 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
cee98a59
MM		 1901 ret = "cfc1\t%0,$31";
1902 }
1903 }
1904
1905 else if (FP_REG_P (regno0))
1906 {
1907 if (GP_REG_P (regno1))
1908 {
1909 delay = DELAY_LOAD;
1910 ret = "mtc1\t%1,%0";
1911 }
1912
1913 if (FP_REG_P (regno1))
1914 ret = "mov.s\t%0,%1";
1915 }
1916
1917 else if (MD_REG_P (regno0))
1918 {
1919 if (GP_REG_P (regno1))
1920 {
1921 delay = DELAY_HILO;
2bcb2ab3 1922 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
225b8835 1923 ret = "mt%0\t%1";
cee98a59
MM		 1924 }
1925 }
1926
76ee8042 1927 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
cee98a59
MM		 1928 {
1929 if (GP_REG_P (regno1))
1930 {
1931 delay = DELAY_LOAD;
1932 ret = "ctc1\t%0,$31";
1933 }
1934 }
1935 }
1936
1937 else if (code1 == MEM)
1938 {
1939 delay = DELAY_LOAD;
1940
1941 if (TARGET_STATS)
1942 mips_count_memory_refs (op1, 1);
1943
1944 if (GP_REG_P (regno0))
1945 {
1946 /* For loads, use the mode of the memory item, instead of the
1947 target, so zero/sign extend can use this code as well. */
1948 switch (GET_MODE (op1))
1949 {
147255d8
JW		 1950 default:
1951 break;
1952 case SFmode:
1953 ret = "lw\t%0,%1";
1954 break;
1955 case SImode:
b8eb88d0 1956 case CCmode:
147255d8
JW		 1957 ret = ((unsignedp && TARGET_64BIT)
1958 ? "lwu\t%0,%1"
1959 : "lw\t%0,%1");
1960 break;
1961 case HImode:
1962 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1963 break;
1964 case QImode:
1965 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1966 break;
cee98a59
MM		 1967 }
1968 }
1969
1970 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1971 ret = "l.s\t%0,%1";
1972
1973 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1974 {
38831dfe 1975 size_t i = strlen (ret);
cee98a59
MM		 1976 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1977 abort ();
1978
1979 sprintf (volatile_buffer, "%%{%s%%}", ret);
1980 ret = volatile_buffer;
1981 }
1982 }
1983
79438502
JW		 1984 else if (code1 == CONST_INT
1985 || (code1 == CONST_DOUBLE
1986 && GET_MODE (op1) == VOIDmode))
cee98a59 1987 {
79438502
JW		 1988 if (code1 == CONST_DOUBLE)
1989 {
1990 /* This can happen when storing constants into long long
1991 bitfields. Just store the least significant word of
1992 the value. */
1993 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1994 }
1995
2bcb2ab3 1996 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
cee98a59
MM		 1997 {
1998 if (GP_REG_P (regno0))
1999 ret = "move\t%0,%z1";
2000
2001 else if (FP_REG_P (regno0))
2002 {
2003 delay = DELAY_LOAD;
842eb20e 2004 ret = "mtc1\t%z1,%0";
cee98a59 2005 }
225b8835
ILT		 2006
2007 else if (MD_REG_P (regno0))
2008 {
2009 delay = DELAY_HILO;
2010 ret = "mt%0\t%.";
2011 }
cee98a59
MM		 2012 }
2013
2014 else if (GP_REG_P (regno0))
2bcb2ab3
GK		 2015 {
2016 /* Don't use X format, because that will give out of
2017 range numbers for 64 bit host and 32 bit target. */
2018 if (! TARGET_MIPS16)
2019 ret = "li\t%0,%1\t\t\t# %X1";
2020 else
2021 {
2022 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2023 ret = "li\t%0,%1";
2024 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2025 ret = "li\t%0,%n1\n\tneg\t%0";
2026 }
2027 }
cee98a59
MM		 2028 }
2029
2030 else if (code1 == CONST_DOUBLE && mode == SFmode)
2031 {
147255d8 2032 if (op1 == CONST0_RTX (SFmode))
cee98a59
MM		 2033 {
2034 if (GP_REG_P (regno0))
2035 ret = "move\t%0,%.";
2036
2037 else if (FP_REG_P (regno0))
2038 {
2039 delay = DELAY_LOAD;
2040 ret = "mtc1\t%.,%0";
2041 }
2042 }
2043
2044 else
2045 {
2046 delay = DELAY_LOAD;
2047 ret = "li.s\t%0,%1";
2048 }
2049 }
2050
2051 else if (code1 == LABEL_REF)
cee98a59
MM		 2052 {
2053 if (TARGET_STATS)
2054 mips_count_memory_refs (op1, 1);
2055
c7343333
MM		 2056 ret = "la\t%0,%a1";
2057 }
2058
2059 else if (code1 == SYMBOL_REF || code1 == CONST)
2060 {
c831afd5 2061 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
cee98a59 2062 {
c7343333
MM		 2063 rtx offset = const0_rtx;
2064
2065 if (GET_CODE (op1) == CONST)
2066 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
2067
2068 if (GET_CODE (op1) == SYMBOL_REF)
2069 {
2070 operands[2] = HALF_PIC_PTR (op1);
2071
2072 if (TARGET_STATS)
2073 mips_count_memory_refs (operands[2], 1);
2074
2075 if (INTVAL (offset) == 0)
2076 {
2077 delay = DELAY_LOAD;
147255d8
JW		 2078 ret = (unsignedp && TARGET_64BIT
2079 ? "lwu\t%0,%2"
2080 : "lw\t%0,%2");
c7343333
MM		 2081 }
2082 else
2083 {
2084 dslots_load_total++;
2085 operands[3] = offset;
147255d8 2086 if (unsignedp && TARGET_64BIT)
f5963e61
JL		 2087 ret = (SMALL_INT (offset)
2088 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2089 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
147255d8 2090 else
f5963e61
JL		 2091 ret = (SMALL_INT (offset)
2092 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2093 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
c7343333
MM		 2094 }
2095 }
cee98a59 2096 }
2bcb2ab3
GK		 2097 else if (TARGET_MIPS16
2098 && code1 == CONST
2099 && GET_CODE (XEXP (op1, 0)) == REG
2100 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2101 {
2102 /* This case arises on the mips16; see
2103 mips16_gp_pseudo_reg. */
2104 ret = "move\t%0,%+";
2105 }
2106 else if (TARGET_MIPS16
2107 && code1 == SYMBOL_REF
2108 && SYMBOL_REF_FLAG (op1)
2109 && (XSTR (op1, 0)[0] != '*'
2110 || strncmp (XSTR (op1, 0) + 1,
2111 LOCAL_LABEL_PREFIX,
2112 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2113 {
2114 /* This can occur when reloading the address of a GP
2115 relative symbol on the mips16. */
2116 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2117 }
cee98a59 2118 else
c7343333
MM		 2119 {
2120 if (TARGET_STATS)
2121 mips_count_memory_refs (op1, 1);
2122
2123 ret = "la\t%0,%a1";
2124 }
cee98a59
MM		 2125 }
2126
2127 else if (code1 == PLUS)
2128 {
2129 rtx add_op0 = XEXP (op1, 0);
2130 rtx add_op1 = XEXP (op1, 1);
2131
f5963e61
JL		 2132 if (GET_CODE (XEXP (op1, 1)) == REG
2133 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2134 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
cee98a59
MM		 2135
2136 operands[2] = add_op0;
2137 operands[3] = add_op1;
2138 ret = "add%:\t%0,%2,%3";
2139 }
910628b8
JW		 2140
2141 else if (code1 == HIGH)
2142 {
2143 operands[1] = XEXP (op1, 0);
2144 ret = "lui\t%0,%%hi(%1)";
2145 }
cee98a59
MM		 2146 }
2147
2148 else if (code0 == MEM)
2149 {
2150 if (TARGET_STATS)
2151 mips_count_memory_refs (op0, 1);
2152
2153 if (code1 == REG)
2154 {
ddef6bc7 2155 int regno1 = REGNO (op1) + subreg_offset1;
cee98a59
MM		 2156
2157 if (GP_REG_P (regno1))
2158 {
2159 switch (mode)
2160 {
2161 case SFmode: ret = "sw\t%1,%0"; break;
2162 case SImode: ret = "sw\t%1,%0"; break;
2163 case HImode: ret = "sh\t%1,%0"; break;
2164 case QImode: ret = "sb\t%1,%0"; break;
f5963e61 2165 default: break;
cee98a59
MM		 2166 }
2167 }
2168
2169 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2170 ret = "s.s\t%1,%0";
2171 }
2172
2173 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2174 {
2175 switch (mode)
2176 {
2177 case SFmode: ret = "sw\t%z1,%0"; break;
2178 case SImode: ret = "sw\t%z1,%0"; break;
2179 case HImode: ret = "sh\t%z1,%0"; break;
2180 case QImode: ret = "sb\t%z1,%0"; break;
f5963e61 2181 default: break;
cee98a59
MM		 2182 }
2183 }
2184
147255d8 2185 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
cee98a59
MM		 2186 {
2187 switch (mode)
2188 {
2189 case SFmode: ret = "sw\t%.,%0"; break;
2190 case SImode: ret = "sw\t%.,%0"; break;
2191 case HImode: ret = "sh\t%.,%0"; break;
2192 case QImode: ret = "sb\t%.,%0"; break;
f5963e61 2193 default: break;
cee98a59
MM		 2194 }
2195 }
2196
f5963e61 2197 if (ret != 0 && MEM_VOLATILE_P (op0))
cee98a59 2198 {
38831dfe 2199 size_t i = strlen (ret);
f5963e61 2200
cee98a59
MM		 2201 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2202 abort ();
2203
2204 sprintf (volatile_buffer, "%%{%s%%}", ret);
2205 ret = volatile_buffer;
2206 }
2207 }
2208
f5963e61 2209 if (ret == 0)
cee98a59
MM		 2210 {
2211 abort_with_insn (insn, "Bad move");
2212 return 0;
2213 }
2214
2215 if (delay != DELAY_NONE)
2216 return mips_fill_delay_slot (ret, delay, operands, insn);
2217
2218 return ret;
2219}
2220
2221\f
2222/* Return the appropriate instructions to move 2 words */
2223
e2fe6aba 2224const char *
cee98a59
MM		 2225mips_move_2words (operands, insn)
2226 rtx operands[];
2227 rtx insn;
2228{
e2fe6aba 2229 const char *ret = 0;
cee98a59
MM		 2230 rtx op0 = operands[0];
2231 rtx op1 = operands[1];
2232 enum rtx_code code0 = GET_CODE (operands[0]);
2233 enum rtx_code code1 = GET_CODE (operands[1]);
ddef6bc7
JJ		 2234 int subreg_offset0 = 0;
2235 int subreg_offset1 = 0;
cee98a59
MM		 2236 enum delay_type delay = DELAY_NONE;
2237
2238 while (code0 == SUBREG)
2239 {
ddef6bc7
JJ		 2240 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2241 GET_MODE (SUBREG_REG (op0)),
2242 SUBREG_BYTE (op0),
2243 GET_MODE (op0));
cee98a59
MM		 2244 op0 = SUBREG_REG (op0);
2245 code0 = GET_CODE (op0);
2246 }
2247
2a0b0bf5
ILT		 2248 if (code1 == SIGN_EXTEND)
2249 {
2250 op1 = XEXP (op1, 0);
2251 code1 = GET_CODE (op1);
2252 }
2253
cee98a59
MM		 2254 while (code1 == SUBREG)
2255 {
ddef6bc7
JJ		 2256 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2257 GET_MODE (SUBREG_REG (op1)),
2258 SUBREG_BYTE (op1),
2259 GET_MODE (op1));
cee98a59
MM		 2260 op1 = SUBREG_REG (op1);
2261 code1 = GET_CODE (op1);
2262 }
2263
2a0b0bf5
ILT		 2264 /* Sanity check. */
2265 if (GET_CODE (operands[1]) == SIGN_EXTEND
2266 && code1 != REG
27c38b75
JW		 2267 && code1 != CONST_INT
2268 /* The following three can happen as the result of a questionable
2269 cast. */
2270 && code1 != LABEL_REF
2271 && code1 != SYMBOL_REF
2272 && code1 != CONST)
2a0b0bf5
ILT		 2273 abort ();
2274
cee98a59
MM		 2275 if (code0 == REG)
2276 {
ddef6bc7 2277 int regno0 = REGNO (op0) + subreg_offset0;
cee98a59
MM		 2278
2279 if (code1 == REG)
2280 {
ddef6bc7 2281 int regno1 = REGNO (op1) + subreg_offset1;
cee98a59
MM		 2282
2283 /* Just in case, don't do anything for assigning a register
2284 to itself, unless we are filling a delay slot. */
2285 if (regno0 == regno1 && set_nomacro == 0)
2286 ret = "";
2287
2288 else if (FP_REG_P (regno0))
2289 {
2290 if (FP_REG_P (regno1))
2291 ret = "mov.d\t%0,%1";
2292
2293 else
2294 {
2295 delay = DELAY_LOAD;
f8151871 2296 if (TARGET_FLOAT64)
147255d8 2297 {
f8151871
JW		 2298 if (!TARGET_64BIT)
2299 abort_with_insn (insn, "Bad move");
f5963e61 2300
147255d8
JW		 2301#ifdef TARGET_FP_CALL_32
2302 if (FP_CALL_GP_REG_P (regno1))
2303 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2304 else
2305#endif
2306 ret = "dmtc1\t%1,%0";
2307 }
2308 else
2309 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
cee98a59
MM		 2310 }
2311 }
2312
2313 else if (FP_REG_P (regno1))
2314 {
2315 delay = DELAY_LOAD;
f8151871 2316 if (TARGET_FLOAT64)
147255d8 2317 {
f8151871
JW		 2318 if (!TARGET_64BIT)
2319 abort_with_insn (insn, "Bad move");
f5963e61 2320
147255d8
JW		 2321#ifdef TARGET_FP_CALL_32
2322 if (FP_CALL_GP_REG_P (regno0))
2323 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2324 else
2325#endif
2326 ret = "dmfc1\t%0,%1";
2327 }
2328 else
2329 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
cee98a59
MM		 2330 }
2331
2bcb2ab3 2332 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
cee98a59
MM		 2333 {
2334 delay = DELAY_HILO;
147255d8 2335 if (TARGET_64BIT)
225b8835
ILT		 2336 {
2337 if (regno0 != HILO_REGNUM)
2338 ret = "mt%0\t%1";
2339 else if (regno1 == 0)
2340 ret = "mtlo\t%.\n\tmthi\t%.";
2341 }
147255d8
JW		 2342 else
2343 ret = "mthi\t%M1\n\tmtlo\t%L1";
cee98a59
MM		 2344 }
2345
2346 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2347 {
2348 delay = DELAY_HILO;
147255d8 2349 if (TARGET_64BIT)
225b8835
ILT		 2350 {
2351 if (regno1 != HILO_REGNUM)
2352 ret = "mf%1\t%0";
2353 }
147255d8
JW		 2354 else
2355 ret = "mfhi\t%M0\n\tmflo\t%L0";
cee98a59
MM		 2356 }
2357
147255d8
JW		 2358 else if (TARGET_64BIT)
2359 ret = "move\t%0,%1";
2360
cee98a59
MM		 2361 else if (regno0 != (regno1+1))
2362 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2363
2364 else
2365 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2366 }
2367
2368 else if (code1 == CONST_DOUBLE)
2369 {
f8151871
JW		 2370 /* Move zero from $0 unless !TARGET_64BIT and recipient
2371 is 64-bit fp reg, in which case generate a constant. */
2372 if (op1 != CONST0_RTX (GET_MODE (op1))
2373 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
cee98a59
MM		 2374 {
2375 if (GET_MODE (op1) == DFmode)
2376 {
2377 delay = DELAY_LOAD;
f5963e61 2378
147255d8
JW		 2379#ifdef TARGET_FP_CALL_32
2380 if (FP_CALL_GP_REG_P (regno0))
f8151871
JW		 2381 {
2382 if (TARGET_FLOAT64 && !TARGET_64BIT)
2383 {
96abdcb1
ILT		 2384 split_double (op1, operands + 2, operands + 3);
2385 ret = "li\t%0,%2\n\tli\t%D0,%3";
f8151871
JW		 2386 }
2387 else
2388 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2389 }
147255d8
JW		 2390 else
2391#endif
b81fdb5a
DN		 2392 /* GNU as emits 64-bit code for li.d if the ISA is 3
2393 or higher. For !TARGET_64BIT && gp registers we
2394 need to avoid this by using two li instructions
2395 instead. */
1d5d552e
GRK		 2396 if (ISA_HAS_64BIT_REGS
2397 && ! TARGET_64BIT
2398 && ! FP_REG_P (regno0))
b81fdb5a
DN		 2399 {
2400 split_double (op1, operands + 2, operands + 3);
2401 ret = "li\t%0,%2\n\tli\t%D0,%3";
2402 }
2403 else
2404 ret = "li.d\t%0,%1";
cee98a59
MM		 2405 }
2406
33563487 2407 else if (TARGET_64BIT)
2bcb2ab3
GK		 2408 {
2409 if (! TARGET_MIPS16)
2410 ret = "dli\t%0,%1";
2411 }
147255d8 2412
cee98a59
MM		 2413 else
2414 {
96abdcb1
ILT		 2415 split_double (op1, operands + 2, operands + 3);
2416 ret = "li\t%0,%2\n\tli\t%D0,%3";
cee98a59
MM		 2417 }
2418 }
2419
2420 else
2421 {
2422 if (GP_REG_P (regno0))
147255d8
JW		 2423 ret = (TARGET_64BIT
2424#ifdef TARGET_FP_CALL_32
2425 && ! FP_CALL_GP_REG_P (regno0)
2426#endif
f5963e61
JL		 2427 ? "move\t%0,%."
2428 : "move\t%0,%.\n\tmove\t%D0,%.");
cee98a59
MM		 2429
2430 else if (FP_REG_P (regno0))
2431 {
2432 delay = DELAY_LOAD;
f5963e61
JL		 2433 ret = (TARGET_64BIT
2434 ? "dmtc1\t%.,%0"
2435 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
cee98a59
MM		 2436 }
2437 }
2438 }
2439
2bcb2ab3 2440 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
cee98a59
MM		 2441 {
2442 if (GP_REG_P (regno0))
f5963e61
JL		 2443 ret = (TARGET_64BIT
2444 ? "move\t%0,%."
2445 : "move\t%0,%.\n\tmove\t%D0,%.");
2446
cee98a59
MM		 2447 else if (FP_REG_P (regno0))
2448 {
2449 delay = DELAY_LOAD;
f5963e61
JL		 2450 ret = (TARGET_64BIT
2451 ? "dmtc1\t%.,%0"
2452 : (TARGET_FLOAT64
2453 ? "li.d\t%0,%1"
2454 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
cee98a59 2455 }
225b8835
ILT		 2456 else if (MD_REG_P (regno0))
2457 {
2458 delay = DELAY_HILO;
f5963e61
JL		 2459 ret = (regno0 == HILO_REGNUM
2460 ? "mtlo\t%.\n\tmthi\t%."
2461 : "mt%0\t%.\n");
225b8835 2462 }
cee98a59
MM		 2463 }
2464
f5963e61
JL		 2465 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2466 && GP_REG_P (regno0))
cee98a59 2467 {
147255d8 2468 if (TARGET_64BIT)
33563487 2469 {
2bcb2ab3
GK		 2470 if (TARGET_MIPS16)
2471 {
2472 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2473 ret = "li\t%0,%1";
2474 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2475 ret = "li\t%0,%n1\n\tneg\t%0";
2476 }
2477 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2a0b0bf5
ILT		 2478 ret = "li\t%0,%1\t\t# %X1";
2479 else if (HOST_BITS_PER_WIDE_INT < 64)
33563487
JW		 2480 /* We can't use 'X' for negative numbers, because then we won't
2481 get the right value for the upper 32 bits. */
f5963e61
JL		 2482 ret = (INTVAL (op1) < 0
2483 ? "dli\t%0,%1\t\t\t# %X1"
33563487
JW		 2484 : "dli\t%0,%X1\t\t# %1");
2485 else
2486 /* We must use 'X', because otherwise LONG_MIN will print as
2487 a number that the assembler won't accept. */
2488 ret = "dli\t%0,%X1\t\t# %1";
2489 }
ade6c319 2490 else if (HOST_BITS_PER_WIDE_INT < 64)
147255d8
JW		 2491 {
2492 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2bcb2ab3
GK		 2493 if (TARGET_MIPS16)
2494 {
2495 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2496 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2497 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2498 {
2499 operands[2] = GEN_INT (1);
2500 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2501 }
2502 }
2503 else
2504 ret = "li\t%M0,%2\n\tli\t%L0,%1";
147255d8 2505 }
ade6c319
JW		 2506 else
2507 {
5107b750
JW		 2508 /* We use multiple shifts here, to avoid warnings about out
2509 of range shifts on 32 bit hosts. */
2510 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
f5963e61
JL		 2511 operands[1]
2512 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
ade6c319
JW		 2513 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2514 }
cee98a59
MM		 2515 }
2516
2517 else if (code1 == MEM)
2518 {
2519 delay = DELAY_LOAD;
2520
2521 if (TARGET_STATS)
2522 mips_count_memory_refs (op1, 2);
2523
2524 if (FP_REG_P (regno0))
2525 ret = "l.d\t%0,%1";
2526
147255d8
JW		 2527 else if (TARGET_64BIT)
2528 {
f5963e61 2529
147255d8
JW		 2530#ifdef TARGET_FP_CALL_32
2531 if (FP_CALL_GP_REG_P (regno0))
f5963e61
JL		 2532 ret = (double_memory_operand (op1, GET_MODE (op1))
2533 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2534 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
147255d8
JW		 2535 else
2536#endif
2537 ret = "ld\t%0,%1";
2538 }
2539
2bcb2ab3 2540 else if (double_memory_operand (op1, GET_MODE (op1)))
cee98a59
MM		 2541 {
2542 operands[2] = adj_offsettable_operand (op1, 4);
f5963e61
JL		 2543 ret = (reg_mentioned_p (op0, op1)
2544 ? "lw\t%D0,%2\n\tlw\t%0,%1"
2545 : "lw\t%0,%1\n\tlw\t%D0,%2");
cee98a59
MM		 2546 }
2547
f5963e61 2548 if (ret != 0 && MEM_VOLATILE_P (op1))
cee98a59 2549 {
38831dfe 2550 size_t i = strlen (ret);
f5963e61 2551
cee98a59
MM		 2552 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2553 abort ();
2554
2555 sprintf (volatile_buffer, "%%{%s%%}", ret);
2556 ret = volatile_buffer;
2557 }
2558 }
147255d8 2559
3871c609 2560 else if (code1 == LABEL_REF)
147255d8 2561 {
33563487
JW		 2562 if (TARGET_STATS)
2563 mips_count_memory_refs (op1, 2);
2564
27c38b75
JW		 2565 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2566 /* We deliberately remove the 'a' from '%1', so that we don't
2567 have to add SIGN_EXTEND support to print_operand_address.
2568 print_operand will just call print_operand_address in this
2569 case, so there is no problem. */
2570 ret = "la\t%0,%1";
2571 else
2572 ret = "dla\t%0,%a1";
147255d8 2573 }
f5963e61 2574 else if (code1 == SYMBOL_REF || code1 == CONST)
3871c609
GK		 2575 {
2576 if (TARGET_MIPS16
2577 && code1 == CONST
2578 && GET_CODE (XEXP (op1, 0)) == REG
2579 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2580 {
2581 /* This case arises on the mips16; see
2582 mips16_gp_pseudo_reg. */
2583 ret = "move\t%0,%+";
2584 }
2585 else if (TARGET_MIPS16
2586 && code1 == SYMBOL_REF
2587 && SYMBOL_REF_FLAG (op1)
2588 && (XSTR (op1, 0)[0] != '*'
2589 || strncmp (XSTR (op1, 0) + 1,
2590 LOCAL_LABEL_PREFIX,
2591 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2592 {
2593 /* This can occur when reloading the address of a GP
2594 relative symbol on the mips16. */
2595 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2596 }
2597 else
2598 {
2599 if (TARGET_STATS)
2600 mips_count_memory_refs (op1, 2);
2601
2602 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2603 /* We deliberately remove the 'a' from '%1', so that we don't
2604 have to add SIGN_EXTEND support to print_operand_address.
2605 print_operand will just call print_operand_address in this
2606 case, so there is no problem. */
2607 ret = "la\t%0,%1";
2608 else
2609 ret = "dla\t%0,%a1";
2610 }
2611 }
cee98a59
MM		 2612 }
2613
2614 else if (code0 == MEM)
2615 {
2616 if (code1 == REG)
2617 {
ddef6bc7 2618 int regno1 = REGNO (op1) + subreg_offset1;
cee98a59
MM		 2619
2620 if (FP_REG_P (regno1))
2621 ret = "s.d\t%1,%0";
2622
147255d8
JW		 2623 else if (TARGET_64BIT)
2624 {
f5963e61 2625
147255d8
JW		 2626#ifdef TARGET_FP_CALL_32
2627 if (FP_CALL_GP_REG_P (regno1))
2628 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2629 else
2630#endif
2631 ret = "sd\t%1,%0";
2632 }
2633
2bcb2ab3 2634 else if (double_memory_operand (op0, GET_MODE (op0)))
cee98a59
MM		 2635 {
2636 operands[2] = adj_offsettable_operand (op0, 4);
2637 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2638 }
2639 }
2640
147255d8
JW		 2641 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2642 || (code1 == CONST_DOUBLE
2643 && op1 == CONST0_RTX (GET_MODE (op1))))
2644 && (TARGET_64BIT
2bcb2ab3 2645 || double_memory_operand (op0, GET_MODE (op0))))
cee98a59 2646 {
147255d8 2647 if (TARGET_64BIT)
cee98a59
MM		 2648 ret = "sd\t%.,%0";
2649 else
2650 {
2651 operands[2] = adj_offsettable_operand (op0, 4);
2652 ret = "sw\t%.,%0\n\tsw\t%.,%2";
2653 }
2654 }
2655
2656 if (TARGET_STATS)
2657 mips_count_memory_refs (op0, 2);
2658
f5963e61 2659 if (ret != 0 && MEM_VOLATILE_P (op0))
cee98a59 2660 {
38831dfe 2661 size_t i = strlen (ret);
f5963e61 2662
cee98a59
MM		 2663 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2664 abort ();
2665
2666 sprintf (volatile_buffer, "%%{%s%%}", ret);
2667 ret = volatile_buffer;
2668 }
2669 }
2670
f5963e61 2671 if (ret == 0)
cee98a59
MM		 2672 {
2673 abort_with_insn (insn, "Bad move");
2674 return 0;
2675 }
2676
2677 if (delay != DELAY_NONE)
2678 return mips_fill_delay_slot (ret, delay, operands, insn);
2679
2680 return ret;
2681}
cee98a59
MM		 2682\f
2683/* Provide the costs of an addressing mode that contains ADDR.
c831afd5 2684 If ADDR is not a valid address, its cost is irrelevant. */
cee98a59
MM		 2685
2686int
2687mips_address_cost (addr)
2688 rtx addr;
2689{
cee98a59
MM		 2690 switch (GET_CODE (addr))
2691 {
2692 case LO_SUM:
cee98a59
MM		 2693 return 1;
2694
2695 case LABEL_REF:
2696 return 2;
2697
2698 case CONST:
c831afd5
MM		 2699 {
2700 rtx offset = const0_rtx;
147255d8 2701 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
c831afd5
MM		 2702 if (GET_CODE (addr) == LABEL_REF)
2703 return 2;
cee98a59 2704
c831afd5
MM		 2705 if (GET_CODE (addr) != SYMBOL_REF)
2706 return 4;
cee98a59 2707
147255d8 2708 if (! SMALL_INT (offset))
c831afd5
MM		 2709 return 2;
2710 }
f5963e61
JL		 2711
2712 /* ... fall through ... */
cee98a59
MM		 2713
2714 case SYMBOL_REF:
2715 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2716
2717 case PLUS:
2718 {
2719 register rtx plus0 = XEXP (addr, 0);
2720 register rtx plus1 = XEXP (addr, 1);
2721
2722 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
f5963e61 2723 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
cee98a59
MM		 2724
2725 if (GET_CODE (plus0) != REG)
2726 break;
2727
2728 switch (GET_CODE (plus1))
2729 {
2730 case CONST_INT:
f5963e61 2731 return SMALL_INT (plus1) ? 1 : 2;
cee98a59
MM		 2732
2733 case CONST:
2734 case SYMBOL_REF:
2735 case LABEL_REF:
2736 case HIGH:
2737 case LO_SUM:
2738 return mips_address_cost (plus1) + 1;
f5963e61
JL		 2739
2740 default:
2741 break;
cee98a59
MM		 2742 }
2743 }
f5963e61
JL		 2744
2745 default:
2746 break;
cee98a59
MM		 2747 }
2748
2749 return 4;
2750}
2751
f5963e61 2752/* Return nonzero if X is an address which needs a temporary register when
508a48d1
JW		 2753 reloaded while generating PIC code. */
2754
2755int
2756pic_address_needs_scratch (x)
2757 rtx x;
2758{
2759 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2760 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2761 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2762 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2763 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2764 return 1;
2765
2766 return 0;
2767}
34b650b3
MM		 2768\f
2769/* Make normal rtx_code into something we can index from an array */
2770
2771static enum internal_test
2772map_test_to_internal_test (test_code)
2773 enum rtx_code test_code;
2774{
2775 enum internal_test test = ITEST_MAX;
2776
2777 switch (test_code)
2778 {
2779 case EQ: test = ITEST_EQ; break;
2780 case NE: test = ITEST_NE; break;
2781 case GT: test = ITEST_GT; break;
2782 case GE: test = ITEST_GE; break;
2783 case LT: test = ITEST_LT; break;
2784 case LE: test = ITEST_LE; break;
2785 case GTU: test = ITEST_GTU; break;
2786 case GEU: test = ITEST_GEU; break;
2787 case LTU: test = ITEST_LTU; break;
2788 case LEU: test = ITEST_LEU; break;
f5963e61 2789 default: break;
34b650b3
MM		 2790 }
2791
2792 return test;
2793}
2794
2795\f
2796/* Generate the code to compare two integer values. The return value is:
2797 (reg:SI xx) The pseudo register the comparison is in
f5963e61 2798 0 No register, generate a simple branch.
147255d8
JW		 2799
2800 ??? This is called with result nonzero by the Scond patterns in
2801 mips.md. These patterns are called with a target in the mode of
2802 the Scond instruction pattern. Since this must be a constant, we
2803 must use SImode. This means that if RESULT is non-zero, it will
2804 always be an SImode register, even if TARGET_64BIT is true. We
2805 cope with this by calling convert_move rather than emit_move_insn.
2806 This will sometimes lead to an unnecessary extension of the result;
2807 for example:
2808
2809 long long
2810 foo (long long i)
2811 {
2812 return i < 5;
2813 }
2814
2815 */
34b650b3
MM		 2816
2817rtx
2818gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2819 enum rtx_code test_code; /* relational test (EQ, etc) */
2820 rtx result; /* result to store comp. or 0 if branch */
2821 rtx cmp0; /* first operand to compare */
2822 rtx cmp1; /* second operand to compare */
2823 int *p_invert; /* NULL or ptr to hold whether branch needs */
2296cba3 2824 /* to reverse its test */
34b650b3 2825{
f5963e61
JL		 2826 struct cmp_info
2827 {
34b650b3
MM		 2828 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2829 int const_low; /* low bound of constant we can accept */
2830 int const_high; /* high bound of constant we can accept */
2831 int const_add; /* constant to add (convert LE -> LT) */
2832 int reverse_regs; /* reverse registers in test */
2833 int invert_const; /* != 0 if invert value if cmp1 is constant */
2834 int invert_reg; /* != 0 if invert value if cmp1 is register */
55f8a64c 2835 int unsignedp; /* != 0 for unsigned comparisons. */
34b650b3
MM		 2836 };
2837
2838 static struct cmp_info info[ (int)ITEST_MAX ] = {
2839
55f8a64c
RS		 2840 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2841 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2842 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2843 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2844 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2845 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2846 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2847 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2848 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2849 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
34b650b3
MM		 2850 };
2851
2852 enum internal_test test;
147255d8 2853 enum machine_mode mode;
34b650b3
MM		 2854 struct cmp_info *p_info;
2855 int branch_p;
2856 int eqne_p;
2857 int invert;
2858 rtx reg;
2859 rtx reg2;
2860
2861 test = map_test_to_internal_test (test_code);
2862 if (test == ITEST_MAX)
2863 abort ();
2864
f5963e61 2865 p_info = &info[(int) test];
34b650b3
MM		 2866 eqne_p = (p_info->test_code == XOR);
2867
147255d8
JW		 2868 mode = GET_MODE (cmp0);
2869 if (mode == VOIDmode)
2870 mode = GET_MODE (cmp1);
2871
34b650b3 2872 /* Eliminate simple branches */
f5963e61 2873 branch_p = (result == 0);
34b650b3
MM		 2874 if (branch_p)
2875 {
2876 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2877 {
2878 /* Comparisons against zero are simple branches */
2bcb2ab3
GK		 2879 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2880 && (! TARGET_MIPS16 || eqne_p))
f5963e61 2881 return 0;
34b650b3
MM		 2882
2883 /* Test for beq/bne. */
2bcb2ab3 2884 if (eqne_p && ! TARGET_MIPS16)
f5963e61 2885 return 0;
34b650b3
MM		 2886 }
2887
2296cba3 2888 /* allocate a pseudo to calculate the value in. */
147255d8 2889 result = gen_reg_rtx (mode);
34b650b3
MM		 2890 }
2891
2892 /* Make sure we can handle any constants given to us. */
2893 if (GET_CODE (cmp0) == CONST_INT)
147255d8 2894 cmp0 = force_reg (mode, cmp0);
34b650b3
MM		 2895
2896 if (GET_CODE (cmp1) == CONST_INT)
2897 {
85f5e2b6 2898 HOST_WIDE_INT value = INTVAL (cmp1);
f5963e61 2899
147255d8
JW		 2900 if (value < p_info->const_low
2901 || value > p_info->const_high
2902 /* ??? Why? And why wasn't the similar code below modified too? */
2903 || (TARGET_64BIT
2904 && HOST_BITS_PER_WIDE_INT < 64
2905 && p_info->const_add != 0
2906 && ((p_info->unsignedp
2907 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
e51712db 2908 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
147255d8
JW		 2909 : (value + p_info->const_add) > INTVAL (cmp1))
2910 != (p_info->const_add > 0))))
2911 cmp1 = force_reg (mode, cmp1);
34b650b3
MM		 2912 }
2913
2914 /* See if we need to invert the result. */
f5963e61
JL		 2915 invert = (GET_CODE (cmp1) == CONST_INT
2916 ? p_info->invert_const : p_info->invert_reg);
34b650b3
MM		 2917
2918 if (p_invert != (int *)0)
2919 {
2920 *p_invert = invert;
f5963e61 2921 invert = 0;
34b650b3
MM		 2922 }
2923
2924 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2925 Comparison between two registers, may involve switching operands. */
2926 if (GET_CODE (cmp1) == CONST_INT)
2927 {
2928 if (p_info->const_add != 0)
55f8a64c
RS		 2929 {
2930 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
f5963e61 2931
55f8a64c
RS		 2932 /* If modification of cmp1 caused overflow,
2933 we would get the wrong answer if we follow the usual path;
4db7b4ce 2934 thus, x > 0xffffffffU would turn into x > 0U. */
55f8a64c 2935 if ((p_info->unsignedp
e51712db
KG		 2936 ? (unsigned HOST_WIDE_INT) new >
2937 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
55f8a64c
RS		 2938 : new > INTVAL (cmp1))
2939 != (p_info->const_add > 0))
d40bb52a
RS		 2940 {
2941 /* This test is always true, but if INVERT is true then
2942 the result of the test needs to be inverted so 0 should
2943 be returned instead. */
2944 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2945 return result;
2946 }
55f8a64c
RS		 2947 else
2948 cmp1 = GEN_INT (new);
2949 }
34b650b3 2950 }
f5963e61 2951
34b650b3
MM		 2952 else if (p_info->reverse_regs)
2953 {
2954 rtx temp = cmp0;
2955 cmp0 = cmp1;
2956 cmp1 = temp;
2957 }
2958
34b650b3 2959 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
bbdb5552
MM		 2960 reg = cmp0;
2961 else
2962 {
147255d8
JW		 2963 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2964 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
bbdb5552
MM		 2965 }
2966
2967 if (test == ITEST_NE)
34b650b3 2968 {
2bcb2ab3
GK		 2969 if (! TARGET_MIPS16)
2970 {
2971 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
f5963e61 2972 invert = 0;
2bcb2ab3
GK		 2973 }
2974 else
2975 {
2976 reg2 = invert ? gen_reg_rtx (mode) : result;
2977 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2978 reg = reg2;
2979 }
34b650b3
MM		 2980 }
2981
bbdb5552 2982 else if (test == ITEST_EQ)
34b650b3 2983 {
f5963e61 2984 reg2 = invert ? gen_reg_rtx (mode) : result;
c5c76735 2985 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
34b650b3
MM		 2986 reg = reg2;
2987 }
2988
2989 if (invert)
2bcb2ab3
GK		 2990 {
2991 rtx one;
2992
2993 if (! TARGET_MIPS16)
2994 one = const1_rtx;
2995 else
2996 {
2997 /* The value is in $24. Copy it to another register, so
2998 that reload doesn't think it needs to store the $24 and
2999 the input to the XOR in the same location. */
3000 reg2 = gen_reg_rtx (mode);
3001 emit_move_insn (reg2, reg);
3002 reg = reg2;
3003 one = force_reg (mode, const1_rtx);
3004 }
3005 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3006 }
34b650b3
MM		 3007
3008 return result;
3009}
cee98a59
MM		 3010\f
3011/* Emit the common code for doing conditional branches.
3012 operand[0] is the label to jump to.
147255d8 3013 The comparison operands are saved away by cmp{si,di,sf,df}. */
cee98a59
MM		 3014
3015void
3016gen_conditional_branch (operands, test_code)
3017 rtx operands[];
3018 enum rtx_code test_code;
3019{
b8eb88d0
ILT		 3020 enum cmp_type type = branch_type;
3021 rtx cmp0 = branch_cmp[0];
3022 rtx cmp1 = branch_cmp[1];
cee98a59 3023 enum machine_mode mode;
b8eb88d0
ILT		 3024 rtx reg;
3025 int invert;
3026 rtx label1, label2;
cee98a59 3027
147255d8 3028 switch (type)
cee98a59 3029 {
cee98a59 3030 case CMP_SI:
147255d8 3031 case CMP_DI:
b8eb88d0 3032 mode = type == CMP_SI ? SImode : DImode;
f5963e61 3033 invert = 0;
b8eb88d0 3034 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
f5963e61 3035
b8eb88d0 3036 if (reg)
cee98a59 3037 {
34b650b3
MM		 3038 cmp0 = reg;
3039 cmp1 = const0_rtx;
3040 test_code = NE;
cee98a59 3041 }
34b650b3 3042 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
f5963e61
JL		 3043 /* We don't want to build a comparison against a non-zero
3044 constant. */
3045 cmp1 = force_reg (mode, cmp1);
3046
cee98a59
MM		 3047 break;
3048
cee98a59 3049 case CMP_SF:
b8eb88d0 3050 case CMP_DF:
76ee8042 3051 if (! ISA_HAS_8CC)
c5c76735 3052 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
b8eb88d0
ILT		 3053 else
3054 reg = gen_reg_rtx (CCmode);
3055
3056 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3057 0 in the instruction built below. The MIPS FPU handles
3058 inequality testing by testing for equality and looking for a
3059 false result. */
c5c76735
JL		 3060 emit_insn (gen_rtx_SET (VOIDmode, reg,
3061 gen_rtx (test_code == NE ? EQ : test_code,
3062 CCmode, cmp0, cmp1)));
3063
b8eb88d0
ILT		 3064 test_code = test_code == NE ? EQ : NE;
3065 mode = CCmode;
3066 cmp0 = reg;
3067 cmp1 = const0_rtx;
f5963e61 3068 invert = 0;
cee98a59 3069 break;
f5963e61
JL		 3070
3071 default:
3072 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
cee98a59 3073 }
85f5e2b6 3074
b8eb88d0
ILT		 3075 /* Generate the branch. */
3076
c5c76735 3077 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
b8eb88d0
ILT		 3078 label2 = pc_rtx;
3079
34b650b3
MM		 3080 if (invert)
3081 {
3082 label2 = label1;
3083 label1 = pc_rtx;
3084 }
3085
c5c76735
JL		 3086 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3087 gen_rtx_IF_THEN_ELSE (VOIDmode,
3088 gen_rtx (test_code, mode,
3089 cmp0, cmp1),
3090 label1, label2)));
b8eb88d0 3091}
34b650b3 3092
b8eb88d0
ILT		 3093/* Emit the common code for conditional moves. OPERANDS is the array
3094 of operands passed to the conditional move defined_expand. */
cee98a59 3095
b8eb88d0
ILT		 3096void
3097gen_conditional_move (operands)
3098 rtx *operands;
3099{
3100 rtx op0 = branch_cmp[0];
3101 rtx op1 = branch_cmp[1];
3102 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3103 enum rtx_code cmp_code = GET_CODE (operands[1]);
3104 enum rtx_code move_code = NE;
3105 enum machine_mode op_mode = GET_MODE (operands[0]);
3106 enum machine_mode cmp_mode;
3107 rtx cmp_reg;
3108
3109 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3110 {
3111 switch (cmp_code)
3112 {
3113 case EQ:
3114 cmp_code = XOR;
3115 move_code = EQ;
3116 break;
3117 case NE:
3118 cmp_code = XOR;
3119 break;
3120 case LT:
3121 break;
3122 case GE:
3123 cmp_code = LT;
3124 move_code = EQ;
3125 break;
3126 case GT:
3127 cmp_code = LT;
3128 op0 = force_reg (mode, branch_cmp[1]);
3129 op1 = branch_cmp[0];
3130 break;
3131 case LE:
3132 cmp_code = LT;
3133 op0 = force_reg (mode, branch_cmp[1]);
3134 op1 = branch_cmp[0];
3135 move_code = EQ;
3136 break;
3137 case LTU:
3138 break;
3139 case GEU:
3140 cmp_code = LTU;
3141 move_code = EQ;
3142 break;
3143 case GTU:
3144 cmp_code = LTU;
3145 op0 = force_reg (mode, branch_cmp[1]);
3146 op1 = branch_cmp[0];
3147 break;
3148 case LEU:
3149 cmp_code = LTU;
3150 op0 = force_reg (mode, branch_cmp[1]);
3151 op1 = branch_cmp[0];
3152 move_code = EQ;
3153 break;
3154 default:
3155 abort ();
3156 }
3157 }
f5963e61
JL		 3158 else if (cmp_code == NE)
3159 cmp_code = EQ, move_code = EQ;
b8eb88d0
ILT		 3160
3161 if (mode == SImode || mode == DImode)
3162 cmp_mode = mode;
3163 else if (mode == SFmode || mode == DFmode)
3164 cmp_mode = CCmode;
3165 else
3166 abort ();
cee98a59 3167
b8eb88d0 3168 cmp_reg = gen_reg_rtx (cmp_mode);
c5c76735
JL		 3169 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3170 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3171
3172 emit_insn (gen_rtx_SET (op_mode, operands[0],
3173 gen_rtx_IF_THEN_ELSE (op_mode,
3174 gen_rtx (move_code, VOIDmode,
3175 cmp_reg,
3176 CONST0_RTX (SImode)),
3177 operands[2], operands[3])));
b8eb88d0 3178}
a0b6cdee
GM		 3179
3180/* Emit the common code for conditional moves. OPERANDS is the array
3181 of operands passed to the conditional move defined_expand. */
3182
3183void
3184mips_gen_conditional_trap (operands)
3185 rtx operands[];
3186{
3187 rtx op0, op1;
3188 enum rtx_code cmp_code = GET_CODE (operands[0]);
3189 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3190
3191 /* MIPS conditional trap machine instructions don't have GT or LE
3192 flavors, so we must invert the comparison and convert to LT and
3193 GE, respectively. */
3194 switch (cmp_code)
3195 {
3196 case GT: cmp_code = LT; break;
3197 case LE: cmp_code = GE; break;
3198 case GTU: cmp_code = LTU; break;
3199 case LEU: cmp_code = GEU; break;
3200 default: break;
3201 }
3202 if (cmp_code == GET_CODE (operands[0]))
3203 {
3204 op0 = force_reg (mode, branch_cmp[0]);
3205 op1 = branch_cmp[1];
3206 }
3207 else
3208 {
3209 op0 = force_reg (mode, branch_cmp[1]);
3210 op1 = branch_cmp[0];
3211 }
3212 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3213 op1 = force_reg (mode, op1);
3214
3215 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3216 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3217 operands[1]));
3218}
cee98a59 3219\f
f5963e61
JL		 3220/* Write a loop to move a constant number of bytes.
3221 Generate load/stores as follows:
cee98a59
MM		 3222
3223 do {
3224 temp1 = src[0];
3225 temp2 = src[1];
3226 ...
3227 temp<last> = src[MAX_MOVE_REGS-1];
cee98a59
MM		 3228 dest[0] = temp1;
3229 dest[1] = temp2;
3230 ...
3231 dest[MAX_MOVE_REGS-1] = temp<last>;
842eb20e 3232 src += MAX_MOVE_REGS;
cee98a59
MM		 3233 dest += MAX_MOVE_REGS;
3234 } while (src != final);
3235
3236 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3237 registers are needed.
3238
3239 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3240 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3241 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3242
3243#define MAX_MOVE_REGS 4
3244#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3245
3246static void
7cabe29a 3247block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
cee98a59
MM		 3248 rtx dest_reg; /* register holding destination address */
3249 rtx src_reg; /* register holding source address */
c94c9817 3250 unsigned int bytes; /* # bytes to move */
cee98a59 3251 int align; /* alignment */
7cabe29a 3252 rtx orig_dest; /* original dest for change_address */
842eb20e 3253 rtx orig_src; /* original source for making a reg note */
cee98a59 3254{
f5963e61
JL		 3255 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
3256 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
3257 rtx align_rtx = GEN_INT (align);
cee98a59
MM		 3258 rtx label;
3259 rtx final_src;
3260 rtx bytes_rtx;
cee98a59 3261 int leftover;
cee98a59 3262
95adab8e 3263 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
cee98a59
MM		 3264 abort ();
3265
3266 leftover = bytes % MAX_MOVE_BYTES;
3267 bytes -= leftover;
3268
3269 label = gen_label_rtx ();
3270 final_src = gen_reg_rtx (Pmode);
0fb5ac6f 3271 bytes_rtx = GEN_INT (bytes);
cee98a59
MM		 3272
3273 if (bytes > 0x7fff)
3274 {
1eeed24e 3275 if (Pmode == DImode)
147255d8
JW		 3276 {
3277 emit_insn (gen_movdi (final_src, bytes_rtx));
3278 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3279 }
3280 else
3281 {
3282 emit_insn (gen_movsi (final_src, bytes_rtx));
3283 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3284 }
cee98a59
MM		 3285 }
3286 else
147255d8 3287 {
1eeed24e 3288 if (Pmode == DImode)
147255d8
JW		 3289 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3290 else
3291 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3292 }
cee98a59
MM		 3293
3294 emit_label (label);
3295
0fb5ac6f 3296 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
842eb20e 3297 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
f5963e61 3298
1eeed24e 3299 if (Pmode == DImode)
147255d8
JW		 3300 {
3301 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3302 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3303 emit_insn (gen_cmpdi (src_reg, final_src));
3304 }
3305 else
3306 {
3307 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3308 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3309 emit_insn (gen_cmpsi (src_reg, final_src));
3310 }
f5963e61 3311
cee98a59
MM		 3312 emit_jump_insn (gen_bne (label));
3313
3314 if (leftover)
f5963e61 3315 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
842eb20e 3316 align_rtx));
cee98a59 3317}
cee98a59
MM		 3318\f
3319/* Use a library function to move some bytes. */
3320
3321static void
3322block_move_call (dest_reg, src_reg, bytes_rtx)
3323 rtx dest_reg;
3324 rtx src_reg;
3325 rtx bytes_rtx;
3326{
147255d8
JW		 3327 /* We want to pass the size as Pmode, which will normally be SImode
3328 but will be DImode if we are using 64 bit longs and pointers. */
3329 if (GET_MODE (bytes_rtx) != VOIDmode
0da9afa6 3330 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
f5963e61 3331 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
147255d8 3332
cee98a59 3333#ifdef TARGET_MEM_FUNCTIONS
c5c76735 3334 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
f5963e61 3335 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
e24b8776
JW		 3336 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3337 TREE_UNSIGNED (sizetype)),
3338 TYPE_MODE (sizetype));
cee98a59 3339#else
c5c76735 3340 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
f5963e61
JL		 3341 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3342 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3343 TREE_UNSIGNED (integer_type_node)),
e24b8776 3344 TYPE_MODE (integer_type_node));
cee98a59
MM		 3345#endif
3346}
cee98a59
MM		 3347\f
3348/* Expand string/block move operations.
3349
3350 operands[0] is the pointer to the destination.
3351 operands[1] is the pointer to the source.
3352 operands[2] is the number of bytes to move.
3353 operands[3] is the alignment. */
3354
3355void
3356expand_block_move (operands)
3357 rtx operands[];
3358{
3359 rtx bytes_rtx = operands[2];
842eb20e 3360 rtx align_rtx = operands[3];
f5963e61 3361 int constp = GET_CODE (bytes_rtx) == CONST_INT;
c94c9817
MM		 3362 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3363 unsigned int align = INTVAL (align_rtx);
842eb20e 3364 rtx orig_src = operands[1];
7cabe29a 3365 rtx orig_dest = operands[0];
cee98a59
MM		 3366 rtx src_reg;
3367 rtx dest_reg;
3368
c94c9817 3369 if (constp && bytes == 0)
cee98a59
MM		 3370 return;
3371
0da9afa6 3372 if (align > (unsigned) UNITS_PER_WORD)
842eb20e
MM		 3373 align = UNITS_PER_WORD;
3374
cee98a59 3375 /* Move the address into scratch registers. */
7cabe29a 3376 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
842eb20e 3377 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
cee98a59
MM		 3378
3379 if (TARGET_MEMCPY)
3380 block_move_call (dest_reg, src_reg, bytes_rtx);
3381
95adab8e 3382 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
0da9afa6 3383 && align == (unsigned) UNITS_PER_WORD)
460f6b71 3384 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
2e245dac 3385
95adab8e 3386 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
7cabe29a
JW		 3387 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3388 dest_reg),
ff18b63b
RK		 3389 change_address (orig_src, BLKmode,
3390 src_reg),
842eb20e 3391 bytes_rtx, align_rtx));
cee98a59 3392
0da9afa6 3393 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
7cabe29a 3394 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
cee98a59
MM		 3395
3396 else if (constp && optimize)
3397 {
3398 /* If the alignment is not word aligned, generate a test at
3399 runtime, to see whether things wound up aligned, and we
3400 can use the faster lw/sw instead ulw/usw. */
3401
f5963e61 3402 rtx temp = gen_reg_rtx (Pmode);
cee98a59 3403 rtx aligned_label = gen_label_rtx ();
f5963e61
JL		 3404 rtx join_label = gen_label_rtx ();
3405 int leftover = bytes % MAX_MOVE_BYTES;
cee98a59
MM		 3406
3407 bytes -= leftover;
3408
1eeed24e 3409 if (Pmode == DImode)
147255d8
JW		 3410 {
3411 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
f5963e61 3412 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
147255d8
JW		 3413 emit_insn (gen_cmpdi (temp, const0_rtx));
3414 }
3415 else
3416 {
3417 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
f5963e61 3418 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
147255d8
JW		 3419 emit_insn (gen_cmpsi (temp, const0_rtx));
3420 }
f5963e61 3421
cee98a59
MM		 3422 emit_jump_insn (gen_beq (aligned_label));
3423
3424 /* Unaligned loop. */
7cabe29a 3425 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
cee98a59
MM		 3426 emit_jump_insn (gen_jump (join_label));
3427 emit_barrier ();
3428
3429 /* Aligned loop. */
3430 emit_label (aligned_label);
7cabe29a
JW		 3431 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3432 orig_src);
cee98a59
MM		 3433 emit_label (join_label);
3434
3435 /* Bytes at the end of the loop. */
3436 if (leftover)
7cabe29a
JW		 3437 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3438 dest_reg),
3439 change_address (orig_src, BLKmode,
3440 src_reg),
3441 GEN_INT (leftover),
3442 GEN_INT (align)));
cee98a59
MM		 3443 }
3444
3445 else
3446 block_move_call (dest_reg, src_reg, bytes_rtx);
3447}
842eb20e
MM		 3448\f
3449/* Emit load/stores for a small constant block_move.
3450
3451 operands[0] is the memory address of the destination.
3452 operands[1] is the memory address of the source.
3453 operands[2] is the number of bytes to move.
3454 operands[3] is the alignment.
3455 operands[4] is a temp register.
3456 operands[5] is a temp register.
c4b9be8e
MM		 3457 ...
3458 operands[3+num_regs] is the last temp register.
3459
3460 The block move type can be one of the following:
3461 BLOCK_MOVE_NORMAL Do all of the block move.
3462 BLOCK_MOVE_NOT_LAST Do all but the last store.
3463 BLOCK_MOVE_LAST Do just the last store. */
842eb20e 3464
e2fe6aba 3465const char *
c4b9be8e 3466output_block_move (insn, operands, num_regs, move_type)
842eb20e
MM		 3467 rtx insn;
3468 rtx operands[];
3469 int num_regs;
c4b9be8e 3470 enum block_move_type move_type;
842eb20e 3471{
f5963e61
JL		 3472 rtx dest_reg = XEXP (operands[0], 0);
3473 rtx src_reg = XEXP (operands[1], 0);
3474 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3475 int align = INTVAL (operands[3]);
3476 int num = 0;
3477 int offset = 0;
3478 int use_lwl_lwr = 0;
3479 int last_operand = num_regs + 4;
3480 int safe_regs = 4;
842eb20e
MM		 3481 int i;
3482 rtx xoperands[10];
3483
3484 struct {
e2fe6aba
KG		 3485 const char *load; /* load insn without nop */
3486 const char *load_nop; /* load insn with trailing nop */
3487 const char *store; /* store insn */
3488 const char *final; /* if last_store used: NULL or swr */
3489 const char *last_store; /* last store instruction */
842eb20e
MM		 3490 int offset; /* current offset */
3491 enum machine_mode mode; /* mode to use on (MEM) */
3492 } load_store[4];
3493
f5963e61 3494 /* ??? Detect a bug in GCC, where it can give us a register
4bb89a8e
MM		 3495 the same as one of the addressing registers and reduce
3496 the number of registers available. */
b6a1cbae 3497 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
f5963e61
JL		 3498 if (! reg_mentioned_p (operands[i], operands[0])
3499 && ! reg_mentioned_p (operands[i], operands[1]))
3500 xoperands[safe_regs++] = operands[i];
4bb89a8e
MM		 3501
3502 if (safe_regs < last_operand)
3503 {
3504 xoperands[0] = operands[0];
3505 xoperands[1] = operands[1];
3506 xoperands[2] = operands[2];
3507 xoperands[3] = operands[3];
f5963e61 3508 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
c6f3187f
RS		 3509 }
3510
842eb20e
MM		 3511 /* If we are given global or static addresses, and we would be
3512 emitting a few instructions, try to save time by using a
3513 temporary register for the pointer. */
a8136932
JW		 3514 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3515 an ldl/ldr instruction pair. We play it safe, and always move
3516 constant addresses into registers when generating N32/N64 code, just
3517 in case we might emit an unaligned load instruction. */
f5963e61 3518 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
a8136932 3519 || mips_abi == ABI_N32 || mips_abi == ABI_64))
842eb20e
MM		 3520 {
3521 if (CONSTANT_P (src_reg))
3522 {
4e09f580
MM		 3523 if (TARGET_STATS)
3524 mips_count_memory_refs (operands[1], 1);
3525
f5963e61 3526 src_reg = operands[3 + num_regs--];
c4b9be8e
MM		 3527 if (move_type != BLOCK_MOVE_LAST)
3528 {
3529 xoperands[1] = operands[1];
3530 xoperands[0] = src_reg;
33563487
JW		 3531 if (Pmode == DImode)
3532 output_asm_insn ("dla\t%0,%1", xoperands);
3533 else
3534 output_asm_insn ("la\t%0,%1", xoperands);
c4b9be8e 3535 }
842eb20e
MM		 3536 }
3537
3538 if (CONSTANT_P (dest_reg))
3539 {
4e09f580
MM		 3540 if (TARGET_STATS)
3541 mips_count_memory_refs (operands[0], 1);
3542
f5963e61 3543 dest_reg = operands[3 + num_regs--];
c4b9be8e
MM		 3544 if (move_type != BLOCK_MOVE_LAST)
3545 {
3546 xoperands[1] = operands[0];
3547 xoperands[0] = dest_reg;
33563487
JW		 3548 if (Pmode == DImode)
3549 output_asm_insn ("dla\t%0,%1", xoperands);
3550 else
3551 output_asm_insn ("la\t%0,%1", xoperands);
c4b9be8e 3552 }
842eb20e
MM		 3553 }
3554 }
3555
910628b8
JW		 3556 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3557 are not offsettable, however, offsettable_address_p says they are
3558 offsettable. I think this is a bug in offsettable_address_p.
3559 For expediency, we fix this by just loading the address into a register
3560 if we happen to get one. */
3561
3562 if (GET_CODE (src_reg) == LO_SUM)
3563 {
f5963e61 3564 src_reg = operands[3 + num_regs--];
910628b8
JW		 3565 if (move_type != BLOCK_MOVE_LAST)
3566 {
3567 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3568 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3569 xoperands[0] = src_reg;
3570 if (Pmode == DImode)
3571 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3572 else
3573 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3574 }
3575 }
3576
3577 if (GET_CODE (dest_reg) == LO_SUM)
3578 {
f5963e61 3579 dest_reg = operands[3 + num_regs--];
910628b8
JW		 3580 if (move_type != BLOCK_MOVE_LAST)
3581 {
3582 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3583 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3584 xoperands[0] = dest_reg;
3585 if (Pmode == DImode)
3586 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3587 else
3588 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3589 }
3590 }
3591
b6a1cbae
GM		 3592 if (num_regs > (int) ARRAY_SIZE (load_store))
3593 num_regs = ARRAY_SIZE (load_store);
842eb20e
MM		 3594
3595 else if (num_regs < 1)
f5963e61
JL		 3596 abort_with_insn (insn,
3597 "Cannot do block move, not enough scratch registers");
842eb20e 3598
842eb20e
MM		 3599 while (bytes > 0)
3600 {
3601 load_store[num].offset = offset;
3602
147255d8
JW		 3603 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3604 {
f5963e61
JL		 3605 load_store[num].load = "ld\t%0,%1";
3606 load_store[num].load_nop = "ld\t%0,%1%#";
3607 load_store[num].store = "sd\t%0,%1";
147255d8 3608 load_store[num].last_store = "sd\t%0,%1";
f5963e61
JL		 3609 load_store[num].final = 0;
3610 load_store[num].mode = DImode;
147255d8
JW		 3611 offset += 8;
3612 bytes -= 8;
3613 }
3614
2bcb2ab3
GK		 3615 /* ??? Fails because of a MIPS assembler bug? */
3616 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
147255d8 3617 {
96abdcb1
ILT		 3618 if (BYTES_BIG_ENDIAN)
3619 {
f5963e61
JL		 3620 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3621 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3622 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
96abdcb1 3623 load_store[num].last_store = "sdr\t%0,%2";
f5963e61 3624 load_store[num].final = "sdl\t%0,%1";
96abdcb1
ILT		 3625 }
3626 else
3627 {
f5963e61
JL		 3628 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3629 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3630 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
96abdcb1 3631 load_store[num].last_store = "sdr\t%0,%1";
f5963e61 3632 load_store[num].final = "sdl\t%0,%2";
96abdcb1 3633 }
f5963e61 3634
147255d8
JW		 3635 load_store[num].mode = DImode;
3636 offset += 8;
3637 bytes -= 8;
f5963e61 3638 use_lwl_lwr = 1;
147255d8
JW		 3639 }
3640
3641 else if (bytes >= 4 && align >= 4)
842eb20e 3642 {
f5963e61
JL		 3643 load_store[num].load = "lw\t%0,%1";
3644 load_store[num].load_nop = "lw\t%0,%1%#";
3645 load_store[num].store = "sw\t%0,%1";
c4b9be8e 3646 load_store[num].last_store = "sw\t%0,%1";
f5963e61
JL		 3647 load_store[num].final = 0;
3648 load_store[num].mode = SImode;
147255d8
JW		 3649 offset += 4;
3650 bytes -= 4;
842eb20e
MM		 3651 }
3652
2bcb2ab3 3653 else if (bytes >= 4 && ! TARGET_MIPS16)
0cebb05d 3654 {
96abdcb1
ILT		 3655 if (BYTES_BIG_ENDIAN)
3656 {
f5963e61
JL		 3657 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3658 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3659 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
96abdcb1 3660 load_store[num].last_store = "swr\t%0,%2";
f5963e61 3661 load_store[num].final = "swl\t%0,%1";
96abdcb1
ILT		 3662 }
3663 else
3664 {
f5963e61
JL		 3665 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3666 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3667 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
96abdcb1 3668 load_store[num].last_store = "swr\t%0,%1";
f5963e61 3669 load_store[num].final = "swl\t%0,%2";
96abdcb1 3670 }
f5963e61 3671
0cebb05d 3672 load_store[num].mode = SImode;
147255d8
JW		 3673 offset += 4;
3674 bytes -= 4;
f5963e61 3675 use_lwl_lwr = 1;
0cebb05d
MM		 3676 }
3677
147255d8 3678 else if (bytes >= 2 && align >= 2)
842eb20e 3679 {
f5963e61
JL		 3680 load_store[num].load = "lh\t%0,%1";
3681 load_store[num].load_nop = "lh\t%0,%1%#";
3682 load_store[num].store = "sh\t%0,%1";
c4b9be8e 3683 load_store[num].last_store = "sh\t%0,%1";
f5963e61
JL		 3684 load_store[num].final = 0;
3685 load_store[num].mode = HImode;
147255d8
JW		 3686 offset += 2;
3687 bytes -= 2;
842eb20e 3688 }
842eb20e
MM		 3689 else
3690 {
f5963e61
JL		 3691 load_store[num].load = "lb\t%0,%1";
3692 load_store[num].load_nop = "lb\t%0,%1%#";
3693 load_store[num].store = "sb\t%0,%1";
c4b9be8e 3694 load_store[num].last_store = "sb\t%0,%1";
f5963e61
JL		 3695 load_store[num].final = 0;
3696 load_store[num].mode = QImode;
842eb20e
MM		 3697 offset++;
3698 bytes--;
3699 }
3700
c4b9be8e 3701 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
4e09f580 3702 {
c4b9be8e
MM		 3703 dslots_load_total++;
3704 dslots_load_filled++;
3705
4e09f580
MM		 3706 if (CONSTANT_P (src_reg))
3707 mips_count_memory_refs (src_reg, 1);
3708
3709 if (CONSTANT_P (dest_reg))
3710 mips_count_memory_refs (dest_reg, 1);
3711 }
3712
842eb20e
MM		 3713 /* Emit load/stores now if we have run out of registers or are
3714 at the end of the move. */
3715
4e09f580 3716 if (++num == num_regs || bytes == 0)
842eb20e
MM		 3717 {
3718 /* If only load/store, we need a NOP after the load. */
3719 if (num == 1)
4e09f580
MM		 3720 {
3721 load_store[0].load = load_store[0].load_nop;
c4b9be8e
MM		 3722 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3723 dslots_load_filled--;
4e09f580 3724 }
842eb20e 3725
c4b9be8e 3726 if (move_type != BLOCK_MOVE_LAST)
842eb20e 3727 {
c4b9be8e
MM		 3728 for (i = 0; i < num; i++)
3729 {
3730 int offset;
0cebb05d 3731
f5963e61 3732 if (!operands[i + 4])
c4b9be8e 3733 abort ();
842eb20e 3734
f5963e61 3735 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
c5c76735
JL		 3736 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3737 REGNO (operands[i + 4]));
842eb20e 3738
c4b9be8e 3739 offset = load_store[i].offset;
f5963e61 3740 xoperands[0] = operands[i + 4];
c5c76735
JL		 3741 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3742 plus_constant (src_reg, offset));
0cebb05d 3743
c4b9be8e 3744 if (use_lwl_lwr)
147255d8 3745 {
f5963e61
JL		 3746 int extra_offset
3747 = GET_MODE_SIZE (load_store[i].mode) - 1;
3748
c5c76735
JL		 3749 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3750 plus_constant (src_reg,
3751 extra_offset
3752 + offset));
147255d8 3753 }
0cebb05d 3754
c4b9be8e
MM		 3755 output_asm_insn (load_store[i].load, xoperands);
3756 }
842eb20e
MM		 3757 }
3758
3759 for (i = 0; i < num; i++)
3760 {
c4b9be8e 3761 int last_p = (i == num-1 && bytes == 0);
0cebb05d 3762 int offset = load_store[i].offset;
c4b9be8e 3763
f5963e61 3764 xoperands[0] = operands[i + 4];
c5c76735
JL		 3765 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3766 plus_constant (dest_reg, offset));
0cebb05d
MM		 3767
3768
3769 if (use_lwl_lwr)
147255d8 3770 {
f5963e61 3771 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
c5c76735
JL		 3772 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3773 plus_constant (dest_reg,
3774 extra_offset
3775 + offset));
147255d8 3776 }
0cebb05d 3777
c4b9be8e
MM		 3778 if (move_type == BLOCK_MOVE_NORMAL)
3779 output_asm_insn (load_store[i].store, xoperands);
3780
3781 else if (move_type == BLOCK_MOVE_NOT_LAST)
3782 {
3783 if (!last_p)
3784 output_asm_insn (load_store[i].store, xoperands);
3785
f5963e61 3786 else if (load_store[i].final != 0)
c4b9be8e
MM		 3787 output_asm_insn (load_store[i].final, xoperands);
3788 }
3789
3790 else if (last_p)
3791 output_asm_insn (load_store[i].last_store, xoperands);
842eb20e
MM		 3792 }
3793
3794 num = 0; /* reset load_store */
f5963e61 3795 use_lwl_lwr = 0;
842eb20e
MM		 3796 }
3797 }
3798
842eb20e
MM		 3799 return "";
3800}
cee98a59
MM		 3801\f
3802/* Argument support functions. */
3803
3804/* Initialize CUMULATIVE_ARGS for a function. */
3805
3806void
3807init_cumulative_args (cum, fntype, libname)
38831dfe
KG		 3808 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3809 tree fntype; /* tree ptr for function decl */
3810 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
cee98a59 3811{
3f1f8d8c 3812 static CUMULATIVE_ARGS zero_cum;
cee98a59
MM		 3813 tree param, next_param;
3814
3815 if (TARGET_DEBUG_E_MODE)
6cb6c3b3 3816 {
f5963e61
JL		 3817 fprintf (stderr,
3818 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3819
6cb6c3b3
MM		 3820 if (!fntype)
3821 fputc ('\n', stderr);
3822
3823 else
3824 {
3825 tree ret_type = TREE_TYPE (fntype);
3826 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
f5963e61
JL		 3827 tree_code_name[(int)TREE_CODE (fntype)],
3828 tree_code_name[(int)TREE_CODE (ret_type)]);
6cb6c3b3
MM		 3829 }
3830 }
cee98a59 3831
3f1f8d8c 3832 *cum = zero_cum;
cee98a59
MM		 3833
3834 /* Determine if this function has variable arguments. This is
3835 indicated by the last argument being 'void_type_mode' if there
3836 are no variable arguments. The standard MIPS calling sequence
f5963e61 3837 passes all arguments in the general purpose registers in this case. */
cee98a59 3838
f5963e61
JL		 3839 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3840 param != 0; param = next_param)
cee98a59
MM		 3841 {
3842 next_param = TREE_CHAIN (param);
f5963e61 3843 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
cee98a59
MM		 3844 cum->gp_reg_found = 1;
3845 }
cee98a59
MM		 3846}
3847
3848/* Advance the argument to the next argument position. */
3849
3850void
3851function_arg_advance (cum, mode, type, named)
3852 CUMULATIVE_ARGS *cum; /* current arg information */
3853 enum machine_mode mode; /* current arg mode */
3854 tree type; /* type of the argument or 0 if lib support */
0fb5ac6f 3855 int named; /* whether or not the argument was named */
cee98a59
MM		 3856{
3857 if (TARGET_DEBUG_E_MODE)
38831dfe
KG		 3858 {
3859 fprintf (stderr,
3860 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3861 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3862 GET_MODE_NAME (mode));
95adab8e 3863 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
38831dfe
KG		 3864 fprintf (stderr, ", %d )\n\n", named);
3865 }
cee98a59
MM		 3866
3867 cum->arg_number++;
3868 switch (mode)
3869 {
b4b93495 3870 case VOIDmode:
cee98a59
MM		 3871 break;
3872
b4b93495
RS		 3873 default:
3874 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3875 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3876 abort ();
f5963e61 3877
b4b93495 3878 cum->gp_reg_found = 1;
147255d8
JW		 3879 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3880 / UNITS_PER_WORD);
cee98a59
MM		 3881 break;
3882
3883 case BLKmode:
3884 cum->gp_reg_found = 1;
147255d8
JW		 3885 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3886 / UNITS_PER_WORD);
cee98a59
MM		 3887 break;
3888
3889 case SFmode:
293a36eb
ILT		 3890 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3891 cum->fp_arg_words++;
3892 else
3893 cum->arg_words++;
2bcb2ab3
GK		 3894 if (! cum->gp_reg_found && cum->arg_number <= 2)
3895 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
cee98a59
MM		 3896 break;
3897
3898 case DFmode:
293a36eb
ILT		 3899 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3900 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3901 else
3902 cum->arg_words += (TARGET_64BIT ? 1 : 2);
2bcb2ab3
GK		 3903 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3904 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
cee98a59
MM		 3905 break;
3906
3907 case DImode:
3908 cum->gp_reg_found = 1;
147255d8 3909 cum->arg_words += (TARGET_64BIT ? 1 : 2);
cee98a59
MM		 3910 break;
3911
3912 case QImode:
3913 case HImode:
3914 case SImode:
3915 cum->gp_reg_found = 1;
3916 cum->arg_words++;
3917 break;
3918 }
3919}
3920
147255d8
JW		 3921/* Return an RTL expression containing the register for the given mode,
3922 or 0 if the argument is to be passed on the stack. */
cee98a59
MM		 3923
3924struct rtx_def *
3925function_arg (cum, mode, type, named)
3926 CUMULATIVE_ARGS *cum; /* current arg information */
3927 enum machine_mode mode; /* current arg mode */
3928 tree type; /* type of the argument or 0 if lib support */
3929 int named; /* != 0 for normal args, == 0 for ... args */
3930{
3f1f8d8c 3931 rtx ret;
cee98a59
MM		 3932 int regbase = -1;
3933 int bias = 0;
0da9afa6 3934 unsigned int *arg_words = &cum->arg_words;
f5963e61 3935 int struct_p = (type != 0
3f1f8d8c 3936 && (TREE_CODE (type) == RECORD_TYPE
f5963e61
JL		 3937 || TREE_CODE (type) == UNION_TYPE
3938 || TREE_CODE (type) == QUAL_UNION_TYPE));
cee98a59
MM		 3939
3940 if (TARGET_DEBUG_E_MODE)
38831dfe
KG		 3941 {
3942 fprintf (stderr,
3943 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3944 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3945 GET_MODE_NAME (mode));
95adab8e 3946 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
38831dfe
KG		 3947 fprintf (stderr, ", %d ) = ", named);
3948 }
3949
cee98a59 3950
293a36eb 3951 cum->last_arg_fp = 0;
cee98a59
MM		 3952 switch (mode)
3953 {
cee98a59 3954 case SFmode:
a53f72db 3955 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
dc55be0e 3956 {
33563487
JW		 3957 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3958 regbase = GP_ARG_FIRST;
3959 else
3960 {
3961 regbase = FP_ARG_FIRST;
f5963e61 3962
33563487
JW		 3963 /* If the first arg was a float in a floating point register,
3964 then set bias to align this float arg properly. */
3965 if (cum->arg_words == 1)
3966 bias = 1;
3967 }
dc55be0e 3968 }
293a36eb
ILT		 3969 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3970 {
3971 if (! TARGET_64BIT)
3972 cum->fp_arg_words += cum->fp_arg_words & 1;
3973 cum->last_arg_fp = 1;
3974 arg_words = &cum->fp_arg_words;
3975 regbase = FP_ARG_FIRST;
3976 }
33563487
JW		 3977 else
3978 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
cee98a59
MM		 3979 break;
3980
3981 case DFmode:
147255d8 3982 if (! TARGET_64BIT)
293a36eb
ILT		 3983 {
3984 if (mips_abi == ABI_EABI
f5963e61 3985 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
293a36eb
ILT		 3986 cum->fp_arg_words += cum->fp_arg_words & 1;
3987 else
3988 cum->arg_words += cum->arg_words & 1;
3989 }
f5963e61 3990
a53f72db 3991 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
33563487 3992 regbase = ((cum->gp_reg_found
f5963e61 3993 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
33563487 3994 || cum->arg_number >= 2)
f5963e61 3995 ? GP_ARG_FIRST : FP_ARG_FIRST);
293a36eb 3996 else if (mips_abi == ABI_EABI
f5963e61 3997 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
293a36eb
ILT		 3998 {
3999 cum->last_arg_fp = 1;
4000 arg_words = &cum->fp_arg_words;
4001 regbase = FP_ARG_FIRST;
4002 }
33563487
JW		 4003 else
4004 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
4005 ? GP_ARG_FIRST : FP_ARG_FIRST);
cee98a59
MM		 4006 break;
4007
b4b93495
RS		 4008 default:
4009 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4010 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4011 abort ();
4012
4013 /* Drops through. */
cee98a59 4014 case BLKmode:
0da9afa6 4015 if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
293a36eb 4016 && ! TARGET_64BIT && mips_abi != ABI_EABI)
df7fef57 4017 cum->arg_words += (cum->arg_words & 1);
df7fef57
MM		 4018 regbase = GP_ARG_FIRST;
4019 break;
4020
4021 case VOIDmode:
cee98a59
MM		 4022 case QImode:
4023 case HImode:
4024 case SImode:
4025 regbase = GP_ARG_FIRST;
4026 break;
4027
4028 case DImode:
147255d8
JW		 4029 if (! TARGET_64BIT)
4030 cum->arg_words += (cum->arg_words & 1);
cee98a59
MM		 4031 regbase = GP_ARG_FIRST;
4032 }
4033
0da9afa6 4034 if (*arg_words >= (unsigned) MAX_ARGS_IN_REGISTERS)
cee98a59
MM		 4035 {
4036 if (TARGET_DEBUG_E_MODE)
3f1f8d8c 4037 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
cee98a59 4038
f5963e61 4039 ret = 0;
cee98a59 4040 }
3f1f8d8c
MM		 4041 else
4042 {
4043 if (regbase == -1)
4044 abort ();
cee98a59 4045
a20b7b05 4046 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
75131237 4047 || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named
d07bec95 4048 || ! TYPE_SIZE_UNIT (type)
75131237 4049 || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
c5c76735 4050 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
a20b7b05
JW		 4051 else
4052 {
4053 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4054 structure contains a double in its entirety, then that 64 bit
4055 chunk is passed in a floating point register. */
4056 tree field;
4057
4058 /* First check to see if there is any such field. */
4059 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
320aba9c
JW		 4060 if (TREE_CODE (field) == FIELD_DECL
4061 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
a20b7b05 4062 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
75131237
RK		 4063 && host_integerp (bit_position (field), 0)
4064 && int_bit_position (field) % BITS_PER_WORD == 0)
a20b7b05
JW		 4065 break;
4066
e9a25f70
JL		 4067 /* If the whole struct fits a DFmode register,
4068 we don't need the PARALLEL. */
15039abe 4069 if (! field || mode == DFmode)
c5c76735 4070 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
a20b7b05
JW		 4071 else
4072 {
4073 /* Now handle the special case by returning a PARALLEL
4074 indicating where each 64 bit chunk goes. */
75131237
RK		 4075 unsigned int chunks;
4076 HOST_WIDE_INT bitpos;
4077 unsigned int regno;
c94c9817 4078 unsigned int i;
a20b7b05
JW		 4079
4080 /* ??? If this is a packed structure, then the last hunk won't
4081 be 64 bits. */
4082
75131237
RK		 4083 chunks
4084 = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD;
0da9afa6 4085 if (chunks + *arg_words + bias > (unsigned) MAX_ARGS_IN_REGISTERS)
293a36eb 4086 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
a20b7b05
JW		 4087
4088 /* assign_parms checks the mode of ENTRY_PARM, so we must
4089 use the actual mode here. */
c5c76735 4090 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
a20b7b05
JW		 4091
4092 bitpos = 0;
293a36eb 4093 regno = regbase + *arg_words + bias;
a20b7b05
JW		 4094 field = TYPE_FIELDS (type);
4095 for (i = 0; i < chunks; i++)
4096 {
4097 rtx reg;
4098
4099 for (; field; field = TREE_CHAIN (field))
320aba9c 4100 if (TREE_CODE (field) == FIELD_DECL
75131237 4101 && int_bit_position (field) >= bitpos)
a20b7b05
JW		 4102 break;
4103
4104 if (field
75131237 4105 && int_bit_position (field) == bitpos
a20b7b05
JW		 4106 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4107 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
c5c76735
JL		 4108 reg = gen_rtx_REG (DFmode,
4109 regno + FP_ARG_FIRST - GP_ARG_FIRST);
a20b7b05 4110 else
c5c76735
JL		 4111 reg = gen_rtx_REG (word_mode, regno);
4112
f5963e61 4113 XVECEXP (ret, 0, i)
c5c76735
JL		 4114 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4115 GEN_INT (bitpos / BITS_PER_UNIT));
a20b7b05
JW		 4116
4117 bitpos += 64;
4118 regno++;
4119 }
4120 }
4121 }
cee98a59 4122
3f1f8d8c 4123 if (TARGET_DEBUG_E_MODE)
293a36eb 4124 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
3f1f8d8c
MM		 4125 struct_p ? ", [struct]" : "");
4126
4127 /* The following is a hack in order to pass 1 byte structures
4128 the same way that the MIPS compiler does (namely by passing
4129 the structure in the high byte or half word of the register).
4130 This also makes varargs work. If we have such a structure,
4131 we save the adjustment RTL, and the call define expands will
4132 emit them. For the VOIDmode argument (argument after the
147255d8 4133 last real argument), pass back a parallel vector holding each
3f1f8d8c
MM		 4134 of the adjustments. */
4135
894715dd
RS		 4136 /* ??? function_arg can be called more than once for each argument.
4137 As a result, we compute more adjustments than we need here.
4138 See the CUMULATIVE_ARGS definition in mips.h. */
4139
147255d8
JW		 4140 /* ??? This scheme requires everything smaller than the word size to
4141 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4142 that would mean every int needs to be shifted left, which is very
4143 inefficient. Let's not carry this compatibility to the 64 bit
4144 calling convention for now. */
4145
4146 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
293a36eb 4147 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3f1f8d8c 4148 {
f4ef129a
JW		 4149 rtx amount = GEN_INT (BITS_PER_WORD
4150 - int_size_in_bytes (type) * BITS_PER_UNIT);
c5c76735 4151 rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
f5963e61 4152
147255d8 4153 if (TARGET_64BIT)
f5963e61 4154 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
147255d8 4155 else
f5963e61 4156 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
3f1f8d8c
MM		 4157 }
4158 }
4159
2bcb2ab3
GK		 4160 /* We will be called with a mode of VOIDmode after the last argument
4161 has been seen. Whatever we return will be passed to the call
4162 insn. If we need any shifts for small structures, return them in
4163 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4164 mode. Otherwise, if we have need a mips16 fp_code, return a REG
4165 with the code stored as the mode. */
4166 if (mode == VOIDmode)
4167 {
4168 if (cum->num_adjusts > 0)
4169 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
4170 gen_rtvec_v (cum->num_adjusts, cum->adjust));
4171 else if (TARGET_MIPS16 && cum->fp_code != 0)
4172 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
4173 }
cee98a59 4174
3f1f8d8c 4175 return ret;
cee98a59
MM		 4176}
4177
cee98a59
MM		 4178int
4179function_arg_partial_nregs (cum, mode, type, named)
4180 CUMULATIVE_ARGS *cum; /* current arg information */
4181 enum machine_mode mode; /* current arg mode */
4182 tree type; /* type of the argument or 0 if lib support */
38831dfe 4183 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
cee98a59 4184{
b4b93495
RS		 4185 if ((mode == BLKmode
4186 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4187 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
0da9afa6 4188 && cum->arg_words < (unsigned) MAX_ARGS_IN_REGISTERS
293a36eb 4189 && mips_abi != ABI_EABI)
cee98a59 4190 {
b4b93495
RS		 4191 int words;
4192 if (mode == BLKmode)
147255d8
JW		 4193 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
4194 / UNITS_PER_WORD);
b4b93495 4195 else
147255d8 4196 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
cee98a59 4197
0da9afa6 4198 if (words + cum->arg_words <= (unsigned) MAX_ARGS_IN_REGISTERS)
cee98a59
MM		 4199 return 0; /* structure fits in registers */
4200
4201 if (TARGET_DEBUG_E_MODE)
4202 fprintf (stderr, "function_arg_partial_nregs = %d\n",
4203 MAX_ARGS_IN_REGISTERS - cum->arg_words);
4204
4205 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
4206 }
4207
95adab8e
KG		 4208 else if (mode == DImode
4209 && cum->arg_words == MAX_ARGS_IN_REGISTERS - (unsigned)1
f5963e61 4210 && ! TARGET_64BIT && mips_abi != ABI_EABI)
cee98a59
MM		 4211 {
4212 if (TARGET_DEBUG_E_MODE)
4213 fprintf (stderr, "function_arg_partial_nregs = 1\n");
4214
4215 return 1;
4216 }
4217
4218 return 0;
4219}
cee98a59 4220\f
4fe12442
DL		 4221/* Create the va_list data type.
4222 We keep 3 pointers, and two offsets.
4223 Two pointers are to the overflow area, which starts at the CFA.
4224 One of these is constant, for addressing into the GPR save area below it.
4225 The other is advanced up the stack through the overflow region.
4226 The third pointer is to the GPR save area. Since the FPR save area
4227 is just below it, we can address FPR slots off this pointer.
4228 We also keep two one-byte offsets, which are to be subtracted from the
4229 constant pointers to yield addresses in the GPR and FPR save areas.
4230 These are downcounted as float or non-float arguments are used,
4231 and when they get to zero, the argument must be obtained from the
4232 overflow region.
4233 If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
4234 and a single pointer is enough. It's started at the GPR save area,
4235 and is advanced, period.
4236 Note that the GPR save area is not constant size, due to optimization
4237 in the prologue. Hence, we can't use a design with two pointers
4238 and two offsets, although we could have designed this with two pointers
4239 and three offsets. */
4240
5d3f2bd5
RH		 4241
4242tree
4243mips_build_va_list ()
4244{
4245 if (mips_abi == ABI_EABI && !TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4246 {
4fe12442 4247 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
5d3f2bd5
RH		 4248
4249 record = make_node (RECORD_TYPE);
4250
4fe12442
DL		 4251 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4252 ptr_type_node);
4253 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
5d3f2bd5 4254 ptr_type_node);
4fe12442 4255 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
5d3f2bd5 4256 ptr_type_node);
4fe12442
DL		 4257 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4258 unsigned_char_type_node);
4259 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4260 unsigned_char_type_node);
5d3f2bd5 4261
5d3f2bd5 4262
4fe12442
DL		 4263 DECL_FIELD_CONTEXT (f_ovfl) = record;
4264 DECL_FIELD_CONTEXT (f_gtop) = record;
4265 DECL_FIELD_CONTEXT (f_ftop) = record;
4266 DECL_FIELD_CONTEXT (f_goff) = record;
4267 DECL_FIELD_CONTEXT (f_foff) = record;
5d3f2bd5 4268
4fe12442
DL		 4269 TYPE_FIELDS (record) = f_ovfl;
4270 TREE_CHAIN (f_ovfl) = f_gtop;
4271 TREE_CHAIN (f_gtop) = f_ftop;
4272 TREE_CHAIN (f_ftop) = f_goff;
4273 TREE_CHAIN (f_goff) = f_foff;
5d3f2bd5 4274
4fe12442 4275 layout_type (record);
5d3f2bd5
RH		 4276 return record;
4277 }
4278 else
4279 return ptr_type_node;
4280}
4281
4fe12442
DL		 4282/* Implement va_start. stdarg_p is 0 if implementing
4283 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4284 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4285 (It doesn't have "...", so it inherits the pointers of its caller.) */
5d3f2bd5
RH		 4286
4287void
4288mips_va_start (stdarg_p, valist, nextarg)
4289 int stdarg_p;
4290 tree valist;
4291 rtx nextarg;
4292{
4fe12442 4293 int int_arg_words;
bd9f1972 4294 tree t;
5d3f2bd5 4295
4fe12442
DL		 4296 /* Find out how many non-float named formals */
4297 int_arg_words = current_function_args_info.arg_words;
5d3f2bd5
RH		 4298
4299 if (mips_abi == ABI_EABI)
4300 {
4fe12442
DL		 4301 int gpr_save_area_size;
4302 /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
4303 if (int_arg_words < 8 )
4304 /* Adjust for the prologue's economy measure */
4305 gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
4306 else
4307 gpr_save_area_size = 0;
4308
5d3f2bd5
RH		 4309 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4310 {
4fe12442
DL		 4311 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4312 tree ovfl, gtop, ftop, goff, foff;
4313 tree gprv;
4314 int float_formals, fpr_offset, size_excess, floats_passed_in_regs;
4315 int fpr_save_offset;
4316
4317 float_formals = current_function_args_info.fp_arg_words;
4318 /* If mips2, the number of formals is half the reported # of words */
4319 if (!TARGET_64BIT)
4320 float_formals /= 2;
4321 floats_passed_in_regs = (TARGET_64BIT ? 8 : 4);
4322
4323 f_ovfl = TYPE_FIELDS (va_list_type_node);
4324 f_gtop = TREE_CHAIN (f_ovfl);
4325 f_ftop = TREE_CHAIN (f_gtop);
4326 f_goff = TREE_CHAIN (f_ftop);
4327 f_foff = TREE_CHAIN (f_goff);
4328
4329 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4330 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4331 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4332 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4333 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4334
4335 /* Emit code setting a pointer into the overflow (shared-stack) area.
4336 If there were more than 8 non-float formals, or more than 8
4337 float formals, then this pointer isn't to the base of the area.
4338 In that case, it must point to where the first vararg is. */
4339 size_excess = 0;
4340 if (float_formals > floats_passed_in_regs)
4341 size_excess += (float_formals-floats_passed_in_regs) * 8;
4342 if (int_arg_words > 8)
4343 size_excess += (int_arg_words-8) * UNITS_PER_WORD;
4344
4345 /* FIXME: for mips2, the above size_excess can be wrong. Because the
4346 overflow stack holds mixed size items, there can be alignments,
4347 so that an 8 byte double following a 4 byte int will be on an
4348 8 byte boundary. This means that the above calculation should
4349 take into account the exact sequence of floats and non-floats
4350 which make up the excess. That calculation should be rolled
4351 into the code which sets the current_function_args_info struct.
4352 The above then reduces to a fetch from that struct. */
4353
4354
4355 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4356 if (size_excess)
4357 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4358 build_int_2 (size_excess, 0));
4359 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4360 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4361
4362 /* Emit code setting a ptr to the base of the overflow area. */
4363 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4364 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4365 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4366
4367 /* Emit code setting a pointer to the GPR save area.
4368 More precisely, a pointer to off-the-end of the FPR save area.
4369 If mips4, this is gpr_save_area_size below the overflow area.
4370 If mips2, also round down to an 8-byte boundary, since the FPR
4371 save area is 8-byte aligned, and GPR is 4-byte-aligned.
4372 Therefore there can be a 4-byte gap between the save areas. */
4373 gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4374 fpr_save_offset = gpr_save_area_size;
5e4f6244 4375 if (!TARGET_64BIT)
5d3f2bd5 4376 {
4fe12442
DL		 4377 if (fpr_save_offset & 7)
4378 fpr_save_offset += 4;
5d3f2bd5 4379 }
4fe12442
DL		 4380 if (fpr_save_offset)
4381 gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
4382 build_int_2 (-fpr_save_offset,-1));
4383 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, gprv);
5d3f2bd5
RH		 4384 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4385
4fe12442
DL		 4386 /* Emit code initting an offset to the size of the GPR save area */
4387 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4388 build_int_2 (gpr_save_area_size,0));
5d3f2bd5
RH		 4389 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4390
4fe12442
DL		 4391 /* Emit code initting an offset from ftop to the first float
4392 vararg. This varies in size, since any float
4393 varargs are put in the FPR save area after the formals.
4394 Note it's 8 bytes/formal regardless of TARGET_64BIT.
4395 However, mips2 stores 4 GPRs, mips4 stores 8 GPRs.
4396 If there are 8 or more float formals, init to zero.
4397 (In fact, the formals aren't stored in the bottom of the
4398 FPR save area: they are elsewhere, and the size of the FPR
4399 save area is economized by the prologue. But this code doesn't
4400 care. This design is unaffected by that fact.) */
4401 if (float_formals >= floats_passed_in_regs)
4402 fpr_offset = 0;
5d3f2bd5 4403 else
4fe12442
DL		 4404 fpr_offset = (floats_passed_in_regs - float_formals) * 8;
4405 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4406 build_int_2 (fpr_offset,0));
5d3f2bd5
RH		 4407 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4408 }
4409 else
4410 {
4fe12442 4411 /* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
5d3f2bd5 4412
4fe12442
DL		 4413 /* Everything is in the GPR save area, or in the overflow
4414 area which is contiguous with it. */
5d3f2bd5 4415
4fe12442
DL		 4416 int offset = -gpr_save_area_size;
4417 if (gpr_save_area_size == 0)
4418 offset = (stdarg_p ? 0 : -UNITS_PER_WORD);
4419 nextarg = plus_constant (nextarg, offset);
5d3f2bd5
RH		 4420 std_expand_builtin_va_start (1, valist, nextarg);
4421 }
4422 }
4423 else
4424 {
4fe12442 4425 /* not EABI */
5d3f2bd5
RH		 4426 int ofs;
4427
4428 if (stdarg_p)
4429 ofs = 0;
4430 else
4431 {
4432 /* ??? This had been conditional on
4433 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4434 and both iris5.h and iris6.h define _MIPS_SIM. */
4435 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
4fe12442 4436 ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
5d3f2bd5
RH		 4437 else
4438 ofs = -UNITS_PER_WORD;
4439 }
4440
4441 nextarg = plus_constant (nextarg, ofs);
4442 std_expand_builtin_va_start (1, valist, nextarg);
4443 }
4444}
4445
4446/* Implement va_arg. */
4447
4448rtx
4449mips_va_arg (valist, type)
4450 tree valist, type;
4451{
4452 HOST_WIDE_INT size, rsize;
4453 rtx addr_rtx;
4454 tree t;
4455
4456 size = int_size_in_bytes (type);
4457 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4458
4459 if (mips_abi == ABI_EABI)
4460 {
5d3f2bd5 4461 int indirect;
4fe12442
DL		 4462 rtx r, lab_over = NULL_RTX, lab_false;
4463 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4464 tree ovfl, gtop, ftop, goff, foff;
5d3f2bd5
RH		 4465
4466 indirect
4467 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4468 if (indirect)
dd193c79
BS		 4469 {
4470 size = POINTER_SIZE / BITS_PER_UNIT;
4471 rsize = UNITS_PER_WORD;
4472 }
5d3f2bd5
RH		 4473
4474 addr_rtx = gen_reg_rtx (Pmode);
4475
4fe12442 4476 if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
5d3f2bd5 4477 {
4fe12442
DL		 4478 /* Case of all args in a merged stack. No need to check bounds,
4479 just advance valist along the stack. */
5d3f2bd5 4480
4fe12442
DL		 4481 tree gpr = valist;
4482 if (! indirect
4483 && ! TARGET_64BIT
4484 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
5d3f2bd5 4485 {
4fe12442
DL		 4486 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4487 build_int_2 (2*UNITS_PER_WORD - 1, 0));
4488 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4489 build_int_2 (-2*UNITS_PER_WORD, -1));
4490 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
5d3f2bd5 4491 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4fe12442 4492 }
5d3f2bd5 4493
4fe12442
DL		 4494 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4495 size_int (rsize));
4496 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4497 if (r != addr_rtx)
4498 emit_move_insn (addr_rtx, r);
5d3f2bd5 4499
4fe12442
DL		 4500 /* flush the POSTINCREMENT */
4501 emit_queue();
5e4f6244 4502
4fe12442
DL		 4503 if (indirect)
4504 {
4505 r = gen_rtx_MEM (Pmode, addr_rtx);
4506 MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4507 emit_move_insn (addr_rtx, r);
5d3f2bd5 4508 }
4fe12442
DL		 4509 else
4510 {
4511 if (BYTES_BIG_ENDIAN && rsize != size)
4512 addr_rtx = plus_constant (addr_rtx, rsize - size);
4513 }
4514 return addr_rtx;
5d3f2bd5
RH		 4515 }
4516
4fe12442
DL		 4517 /* Not a simple merged stack. Need ptrs and indexes left by va_start. */
4518
4519 f_ovfl = TYPE_FIELDS (va_list_type_node);
4520 f_gtop = TREE_CHAIN (f_ovfl);
4521 f_ftop = TREE_CHAIN (f_gtop);
4522 f_goff = TREE_CHAIN (f_ftop);
4523 f_foff = TREE_CHAIN (f_goff);
4524
4525 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4526 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4527 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4528 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4529 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4530
4531 lab_false = gen_label_rtx ();
4532 lab_over = gen_label_rtx ();
4533
4534 if (TREE_CODE (type) == REAL_TYPE)
4535 {
4536
4537 /* Emit code to branch if foff == 0. */
4538 r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)),
4539 EXPAND_NORMAL);
4540 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4541 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4542
4543 /* Emit code for addr_rtx = ftop - foff */
4544 t = build (MINUS_EXPR, TREE_TYPE (ftop), ftop, foff );
4545 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4546 if (r != addr_rtx)
4547 emit_move_insn (addr_rtx, r);
4548
4549 /* Emit code for foff-=8.
4550 Advances the offset up FPR save area by one double */
4551 t = build (MINUS_EXPR, TREE_TYPE (foff), foff, build_int_2 (8, 0));
4552 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff, t);
4553 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4554
4555 emit_queue();
4556 emit_jump (lab_over);
4557 emit_barrier ();
4558 emit_label (lab_false);
4559
4560 if (!TARGET_64BIT)
4561 {
4562 /* For mips2, the overflow area contains mixed size items.
4563 If a 4-byte int is followed by an 8-byte float, then
4564 natural alignment causes a 4 byte gap.
4565 So, dynamically adjust ovfl up to a multiple of 8. */
4566 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl,
4567 build_int_2 (7, 0));
4568 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t);
4569 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4570 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4571 }
5d3f2bd5 4572
4fe12442
DL		 4573 /* Emit code for addr_rtx = the ovfl pointer into overflow area.
4574 Regardless of mips2, postincrement the ovfl pointer by 8. */
4575 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4576 size_int (8));
4577 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4578 if (r != addr_rtx)
4579 emit_move_insn (addr_rtx, r);
4580
4581 emit_queue();
4582 emit_label (lab_over);
4583 return addr_rtx;
4584 }
4585 else
4586 {
4587 /* not REAL_TYPE */
4588 int step_size;
1e7a71c1 4589
4fe12442
DL		 4590 if (! TARGET_64BIT
4591 && TREE_CODE (type) == INTEGER_TYPE
4592 && TYPE_PRECISION (type) == 64)
4593 {
4594 /* In mips2, int takes 32 bits of the GPR save area, but
4595 longlong takes an aligned 64 bits. So, emit code
4596 to zero the low order bits of goff, thus aligning
4597 the later calculation of (gtop-goff) upwards. */
4598 t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff,
4599 build_int_2 (-8, -1));
4600 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4601 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4602 }
5d3f2bd5 4603
4fe12442
DL		 4604 /* Emit code to branch if goff == 0. */
4605 r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)),
4606 EXPAND_NORMAL);
4607 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4608 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4609
4610 /* Emit code for addr_rtx = gtop - goff. */
4611 t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff);
4612 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4613 if (r != addr_rtx)
4614 emit_move_insn (addr_rtx, r);
4615
4616 /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
4617 if (! TARGET_64BIT && TYPE_PRECISION (type) == 64)
4618 step_size = 8;
4619 else
4620 step_size = UNITS_PER_WORD;
4621
4622 /* Emit code for goff = goff - step_size.
4623 Advances the offset up GPR save area over the item. */
4624 t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
4625 build_int_2 (step_size, 0));
4626 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4627 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4628
4629 emit_queue();
4630 emit_jump (lab_over);
4631 emit_barrier ();
4632 emit_label (lab_false);
4633
4634 /* Emit code for addr_rtx -> overflow area, postinc by step_size */
4635 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4636 size_int (step_size));
4637 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4638 if (r != addr_rtx)
4639 emit_move_insn (addr_rtx, r);
4640
4641 emit_queue();
4642 emit_label (lab_over);
4643
4644 if (indirect)
4645 {
4646 r = gen_rtx_MEM (Pmode, addr_rtx);
4647 MEM_ALIAS_SET (r) = get_varargs_alias_set ();
4648 emit_move_insn (addr_rtx, r);
4649 }
4650 else
4651 {
4652 if (BYTES_BIG_ENDIAN && rsize != size)
4653 addr_rtx = plus_constant (addr_rtx, rsize - size);
4654 }
4655 return addr_rtx;
5d3f2bd5
RH		 4656 }
4657 }
4658 else
4659 {
4fe12442 4660 /* Not EABI. */
5d3f2bd5
RH		 4661 int align;
4662
4663 /* ??? The original va-mips.h did always align, despite the fact
4664 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4665 increment mechanism. */
4666
4667 if (TARGET_64BIT)
4668 align = 8;
4669 else if (TYPE_ALIGN (type) > 32)
4670 align = 8;
4671 else
4672 align = 4;
4673
4674 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4675 build_int_2 (align - 1, 0));
4676 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4677 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5d3f2bd5
RH		 4678 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4679
4680 /* Everything past the alignment is standard. */
4681 return std_expand_builtin_va_arg (valist, type);
4682 }
4683}
4684\f
cee98a59
MM		 4685/* Abort after printing out a specific insn. */
4686
e2fe6aba 4687static void
cee98a59
MM		 4688abort_with_insn (insn, reason)
4689 rtx insn;
e2fe6aba 4690 const char *reason;
cee98a59
MM		 4691{
4692 error (reason);
4693 debug_rtx (insn);
4694 abort ();
4695}
cee98a59
MM		 4696\f
4697/* Set up the threshold for data to go into the small data area, instead
4698 of the normal data area, and detect any conflicts in the switches. */
4699
4700void
4701override_options ()
4702{
4703 register int i, start;
4704 register int regno;
4705 register enum machine_mode mode;
4706
f5963e61 4707 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
cee98a59 4708
147255d8
JW		 4709 if (mips_section_threshold <= 0)
4710 target_flags &= ~MASK_GPOPT;
4711 else if (optimize)
4712 target_flags |= MASK_GPOPT;
4713
2bcb2ab3
GK		 4714 /* If both single-float and soft-float are set, then clear the one that
4715 was set by TARGET_DEFAULT, leaving the one that was set by the
4716 user. We assume here that the specs prevent both being set by the
4717 user. */
4718#ifdef TARGET_DEFAULT
4719 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
0da9afa6 4720 target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
2bcb2ab3
GK		 4721#endif
4722
147255d8 4723 /* Get the architectural level. */
f5963e61 4724 if (mips_isa_string == 0)
2bcb2ab3 4725 mips_isa = MIPS_ISA_DEFAULT;
147255d8 4726
38831dfe 4727 else if (ISDIGIT (*mips_isa_string))
147255d8
JW		 4728 {
4729 mips_isa = atoi (mips_isa_string);
2bcb2ab3
GK		 4730 if (mips_isa == 16)
4731 {
4732 /* -mno-mips16 overrides -mips16. */
4733 if (mips_no_mips16_string == NULL)
4734 {
4735 target_flags |= MASK_MIPS16;
4736 if (TARGET_64BIT)
4737 mips_isa = 3;
4738 else
4739 mips_isa = MIPS_ISA_DEFAULT;
4740 }
4741 else
4742 {
4743 mips_isa = MIPS_ISA_DEFAULT;
4744 }
4745 }
4746 else if (mips_isa < 1 || mips_isa > 4)
147255d8
JW		 4747 {
4748 error ("-mips%d not supported", mips_isa);
4749 mips_isa = 1;
4750 }
4751 }
4752
4753 else
4754 {
4755 error ("bad value (%s) for -mips switch", mips_isa_string);
4756 mips_isa = 1;
4757 }
4758
ade6c319 4759#ifdef MIPS_ABI_DEFAULT
a53f72db 4760 /* Get the ABI to use. */
ade6c319
JW		 4761 if (mips_abi_string == (char *) 0)
4762 mips_abi = MIPS_ABI_DEFAULT;
748b909e 4763 else if (! strcmp (mips_abi_string, "32"))
ade6c319 4764 mips_abi = ABI_32;
a53f72db
GRK		 4765 else if (! strcmp (mips_abi_string, "o64"))
4766 mips_abi = ABI_O64;
ade6c319
JW		 4767 else if (! strcmp (mips_abi_string, "n32"))
4768 mips_abi = ABI_N32;
748b909e 4769 else if (! strcmp (mips_abi_string, "64"))
ade6c319 4770 mips_abi = ABI_64;
293a36eb
ILT		 4771 else if (! strcmp (mips_abi_string, "eabi"))
4772 mips_abi = ABI_EABI;
ade6c319
JW		 4773 else
4774 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4775
4776 /* A specified ISA defaults the ABI if it was not specified. */
a53f72db
GRK		 4777 if (mips_abi_string == 0 && mips_isa_string
4778 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
ade6c319 4779 {
1d5d552e 4780 if (! ISA_HAS_64BIT_REGS)
ade6c319
JW		 4781 mips_abi = ABI_32;
4782 else
4783 mips_abi = ABI_64;
4784 }
f5963e61 4785
ade6c319 4786 /* A specified ABI defaults the ISA if it was not specified. */
a53f72db
GRK		 4787 else if (mips_isa_string == 0 && mips_abi_string
4788 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
ade6c319
JW		 4789 {
4790 if (mips_abi == ABI_32)
4791 mips_isa = 1;
4792 else if (mips_abi == ABI_N32)
4793 mips_isa = 3;
4794 else
4795 mips_isa = 4;
4796 }
f5963e61 4797
ade6c319
JW		 4798 /* If both ABI and ISA were specified, check for conflicts. */
4799 else if (mips_isa_string && mips_abi_string)
4800 {
1d5d552e 4801 if ((! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
a53f72db 4802 || mips_abi == ABI_O64))
1d5d552e 4803 || (ISA_HAS_64BIT_REGS && mips_abi == ABI_32))
ade6c319
JW		 4804 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4805 }
4806
4807 /* Override TARGET_DEFAULT if necessary. */
4808 if (mips_abi == ABI_32)
4809 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4810
3ce1ba83
GRK		 4811 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4812 then set the type sizes. In the EABI in 64 bit mode, longs and
4813 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4814 if (mips_explicit_type_size_string == NULL
4815 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4816 || mips_abi == ABI_64))
29a5d7cc
ILT		 4817 target_flags |= MASK_LONG64;
4818
ade6c319
JW		 4819 /* ??? This doesn't work yet, so don't let people try to use it. */
4820 if (mips_abi == ABI_32)
4821 error ("The -mabi=32 support does not work yet.");
f5963e61 4822
ade6c319
JW		 4823#else
4824 if (mips_abi_string)
4825 error ("This target does not support the -mabi switch.");
4826#endif
4827
1bd9166e
JW		 4828#ifdef MIPS_CPU_STRING_DEFAULT
4829 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4830 greater than that supported by the default processor, then the user gets
4831 an error. Normally, the compiler will just default to the base level cpu
4832 for the indicated isa. */
f5963e61 4833 if (mips_cpu_string == 0)
1bd9166e
JW		 4834 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
4835#endif
4836
0da9afa6 4837 /* Identify the processor type. */
f5963e61 4838 if (mips_cpu_string == 0
0da9afa6
NC		 4839 || ! strcmp (mips_cpu_string, "default")
4840 || ! strcmp (mips_cpu_string, "DEFAULT"))
cee98a59 4841 {
147255d8
JW		 4842 switch (mips_isa)
4843 {
4844 default:
4845 mips_cpu_string = "3000";
4846 mips_cpu = PROCESSOR_R3000;
4847 break;
4848 case 2:
4849 mips_cpu_string = "6000";
4850 mips_cpu = PROCESSOR_R6000;
4851 break;
4852 case 3:
4853 mips_cpu_string = "4000";
4854 mips_cpu = PROCESSOR_R4000;
4855 break;
33563487
JW		 4856 case 4:
4857 mips_cpu_string = "8000";
4858 mips_cpu = PROCESSOR_R8000;
4859 break;
147255d8 4860 }
cee98a59 4861 }
cee98a59
MM		 4862 else
4863 {
e2fe6aba 4864 const char *p = mips_cpu_string;
f5963e61 4865 int seen_v = 0;
cee98a59 4866
5034b7bd
JW		 4867 /* We need to cope with the various "vr" prefixes for the NEC 4300
4868 and 4100 processors. */
4869 if (*p == 'v' || *p == 'V')
f5963e61
JL		 4870 seen_v = 1, p++;
4871
cee98a59
MM		 4872 if (*p == 'r' || *p == 'R')
4873 p++;
4874
4875 /* Since there is no difference between a R2000 and R3000 in
0da9afa6 4876 terms of the scheduler, we collapse them into just an R3000. */
cee98a59
MM		 4877
4878 mips_cpu = PROCESSOR_DEFAULT;
4879 switch (*p)
4880 {
2bcb2ab3 4881 case '2':
cee98a59
MM		 4882 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
4883 mips_cpu = PROCESSOR_R3000;
4884 break;
4885
4886 case '3':
4887 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
4888 mips_cpu = PROCESSOR_R3000;
e9a25f70
JL		 4889 else if (!strcmp (p, "3900"))
4890 mips_cpu = PROCESSOR_R3900;
cee98a59
MM		 4891 break;
4892
4893 case '4':
4894 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
4895 mips_cpu = PROCESSOR_R4000;
5034b7bd
JW		 4896 /* The vr4100 is a non-FP ISA III processor with some extra
4897 instructions. */
f5963e61
JL		 4898 else if (!strcmp (p, "4100"))
4899 {
4900 mips_cpu = PROCESSOR_R4100;
4901 target_flags |= MASK_SOFT_FLOAT ;
4902 }
5034b7bd
JW		 4903 /* The vr4300 is a standard ISA III processor, but with a different
4904 pipeline. */
4905 else if (!strcmp (p, "4300"))
4906 mips_cpu = PROCESSOR_R4300;
147255d8
JW		 4907 /* The r4400 is exactly the same as the r4000 from the compiler's
4908 viewpoint. */
4909 else if (!strcmp (p, "4400"))
4910 mips_cpu = PROCESSOR_R4000;
4911 else if (!strcmp (p, "4600"))
4912 mips_cpu = PROCESSOR_R4600;
46299de9 4913 else if (!strcmp (p, "4650"))
053665d7 4914 mips_cpu = PROCESSOR_R4650;
cee98a59
MM		 4915 break;
4916
b8eb88d0
ILT		 4917 case '5':
4918 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
4919 mips_cpu = PROCESSOR_R5000;
4920 break;
4921
cee98a59
MM		 4922 case '6':
4923 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
4924 mips_cpu = PROCESSOR_R6000;
4925 break;
147255d8 4926
33563487
JW		 4927 case '8':
4928 if (!strcmp (p, "8000"))
4929 mips_cpu = PROCESSOR_R8000;
4930 break;
4931
147255d8
JW		 4932 case 'o':
4933 if (!strcmp (p, "orion"))
4934 mips_cpu = PROCESSOR_R4600;
4935 break;
cee98a59
MM		 4936 }
4937
b8eb88d0
ILT		 4938 if (seen_v
4939 && mips_cpu != PROCESSOR_R4300
4940 && mips_cpu != PROCESSOR_R4100
4941 && mips_cpu != PROCESSOR_R5000)
5034b7bd
JW		 4942 mips_cpu = PROCESSOR_DEFAULT;
4943
cee98a59
MM		 4944 if (mips_cpu == PROCESSOR_DEFAULT)
4945 {
4946 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4947 mips_cpu_string = "default";
4948 }
4949 }
4950
1d5d552e
GRK		 4951 if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
4952 || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
053665d7 4953 || ((mips_cpu == PROCESSOR_R4000
5034b7bd
JW		 4954 || mips_cpu == PROCESSOR_R4100
4955 || mips_cpu == PROCESSOR_R4300
053665d7
ILT		 4956 || mips_cpu == PROCESSOR_R4600
4957 || mips_cpu == PROCESSOR_R4650)
1d5d552e 4958 && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
cee98a59
MM		 4959 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
4960
4961 /* make sure sizes of ints/longs/etc. are ok */
1d5d552e 4962 if (! ISA_HAS_64BIT_REGS)
cee98a59 4963 {
fb1bf66d 4964 if (TARGET_FLOAT64)
400500c4
RK		 4965 {
4966 error ("-mips%d does not support 64 bit fp registers", mips_isa);
789c026d 4967 target_flags &= ~ MASK_FLOAT64;
400500c4 4968 }
f8151871
JW		 4969
4970 else if (TARGET_64BIT)
400500c4
RK		 4971 {
4972 error ("-mips%d does not support 64 bit gp registers", mips_isa);
4973 target_flags &= ~MASK_64BIT;
4974 }
147255d8 4975 }
cee98a59 4976
a53f72db 4977 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
33563487
JW		 4978 flag_pcc_struct_return = 0;
4979
cee98a59
MM		 4980 /* Tell halfpic.c that we have half-pic code if we do. */
4981 if (TARGET_HALF_PIC)
c831afd5 4982 HALF_PIC_INIT ();
cee98a59 4983
508a48d1
JW		 4984 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4985 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4986 /* ??? -non_shared turns off pic code generation, but this is not
4987 implemented. */
ffa9d0b1 4988 if (TARGET_ABICALLS)
508a48d1
JW		 4989 {
4990 mips_abicalls = MIPS_ABICALLS_YES;
4991 flag_pic = 1;
508a48d1
JW		 4992 if (mips_section_threshold > 0)
4993 warning ("-G is incompatible with PIC code which is the default");
4994 }
ffa9d0b1 4995 else
1d6ce736 4996 mips_abicalls = MIPS_ABICALLS_NO;
ffa9d0b1 4997
e0bfcea5
ILT		 4998 /* -membedded-pic is a form of PIC code suitable for embedded
4999 systems. All calls are made using PC relative addressing, and
5000 all data is addressed using the $gp register. This requires gas,
5001 which does most of the work, and GNU ld, which automatically
5002 expands PC relative calls which are out of range into a longer
5003 instruction sequence. All gcc really does differently is
5004 generate a different sequence for a switch. */
5005 if (TARGET_EMBEDDED_PIC)
5006 {
5007 flag_pic = 1;
5008 if (TARGET_ABICALLS)
5009 warning ("-membedded-pic and -mabicalls are incompatible");
f5963e61 5010
e0bfcea5
ILT		 5011 if (g_switch_set)
5012 warning ("-G and -membedded-pic are incompatible");
f5963e61 5013
e0bfcea5
ILT		 5014 /* Setting mips_section_threshold is not required, because gas
5015 will force everything to be GP addressable anyhow, but
5016 setting it will cause gcc to make better estimates of the
5017 number of instructions required to access a particular data
5018 item. */
5019 mips_section_threshold = 0x7fffffff;
5020 }
5021
8acd7d30 5022 /* This optimization requires a linker that can support a R_MIPS_LO16
f5963e61 5023 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
8acd7d30
JW		 5024 GNU ld has this support, but not all other MIPS linkers do, so we enable
5025 this optimization only if the user requests it, or if GNU ld is the
5026 standard linker for this configuration. */
910628b8
JW		 5027 /* ??? This does not work when target addresses are DImode.
5028 This is because we are missing DImode high/lo_sum patterns. */
2bcb2ab3 5029 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
8acd7d30 5030 && Pmode == SImode)
910628b8
JW		 5031 mips_split_addresses = 1;
5032 else
5033 mips_split_addresses = 0;
5034
cee98a59 5035 /* -mrnames says to use the MIPS software convention for register
147255d8 5036 names instead of the hardware names (ie, $a0 instead of $4).
cee98a59
MM		 5037 We do this by switching the names in mips_reg_names, which the
5038 reg_names points into via the REGISTER_NAMES macro. */
5039
5040 if (TARGET_NAME_REGS)
4e135bdd 5041 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
cee98a59 5042
2bcb2ab3
GK		 5043 /* When compiling for the mips16, we can not use floating point. We
5044 record the original hard float value in mips16_hard_float. */
5045 if (TARGET_MIPS16)
5046 {
5047 if (TARGET_SOFT_FLOAT)
5048 mips16_hard_float = 0;
5049 else
5050 mips16_hard_float = 1;
5051 target_flags |= MASK_SOFT_FLOAT;
5052
5053 /* Don't run the scheduler before reload, since it tends to
5054 increase register pressure. */
5055 flag_schedule_insns = 0;
5056 }
5057
5058 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5059 to avoid using up another bit in target_flags. */
5060 if (mips_entry_string != NULL)
5061 {
5062 if (*mips_entry_string != '\0')
5063 error ("Invalid option `entry%s'", mips_entry_string);
5064
5065 if (! TARGET_MIPS16)
5066 warning ("-mentry is only meaningful with -mips-16");
5067 else
5068 mips_entry = 1;
5069 }
5070
5071 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5072 attributes can access it. */
5073 if (TARGET_MIPS16)
5074 mips16 = 1;
5075 else
5076 mips16 = 0;
5077
147255d8
JW		 5078 /* Initialize the high and low values for legitimate floating point
5079 constants. Rather than trying to get the accuracy down to the
5080 last bit, just use approximate ranges. */
5081 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
5082 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
5083 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
5084 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
5085
f5963e61
JL		 5086 mips_print_operand_punct['?'] = 1;
5087 mips_print_operand_punct['#'] = 1;
5088 mips_print_operand_punct['&'] = 1;
5089 mips_print_operand_punct['!'] = 1;
5090 mips_print_operand_punct['*'] = 1;
5091 mips_print_operand_punct['@'] = 1;
5092 mips_print_operand_punct['.'] = 1;
5093 mips_print_operand_punct['('] = 1;
5094 mips_print_operand_punct[')'] = 1;
5095 mips_print_operand_punct['['] = 1;
5096 mips_print_operand_punct[']'] = 1;
5097 mips_print_operand_punct['<'] = 1;
5098 mips_print_operand_punct['>'] = 1;
5099 mips_print_operand_punct['{'] = 1;
5100 mips_print_operand_punct['}'] = 1;
5101 mips_print_operand_punct['^'] = 1;
5102 mips_print_operand_punct['$'] = 1;
5103 mips_print_operand_punct['+'] = 1;
efa3896a 5104 mips_print_operand_punct['~'] = 1;
cee98a59 5105
2bcb2ab3
GK		 5106 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5107 mips_char_to_class['e'] = M16_NA_REGS;
5108 mips_char_to_class['t'] = T_REG;
f5963e61 5109 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
cee98a59
MM		 5110 mips_char_to_class['h'] = HI_REG;
5111 mips_char_to_class['l'] = LO_REG;
225b8835 5112 mips_char_to_class['a'] = HILO_REG;
cee98a59 5113 mips_char_to_class['x'] = MD_REGS;
225b8835 5114 mips_char_to_class['b'] = ALL_REGS;
cee98a59 5115 mips_char_to_class['y'] = GR_REGS;
34b650b3 5116 mips_char_to_class['z'] = ST_REGS;
cee98a59
MM		 5117
5118 /* Set up array to map GCC register number to debug register number.
5119 Ignore the special purpose register numbers. */
5120
5121 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5122 mips_dbx_regno[i] = -1;
5123
5124 start = GP_DBX_FIRST - GP_REG_FIRST;
5125 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5126 mips_dbx_regno[i] = i + start;
5127
5128 start = FP_DBX_FIRST - FP_REG_FIRST;
5129 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5130 mips_dbx_regno[i] = i + start;
5131
5132 /* Set up array giving whether a given register can hold a given mode.
5133 At present, restrict ints from being in FP registers, because reload
5134 is a little enthusiastic about storing extra values in FP registers,
5135 and this is not good for things like OS kernels. Also, due to the
c831afd5 5136 mandatory delay, it is as fast to load from cached memory as to move
cee98a59
MM		 5137 from the FP register. */
5138
5139 for (mode = VOIDmode;
5140 mode != MAX_MACHINE_MODE;
f5963e61 5141 mode = (enum machine_mode) ((int)mode + 1))
cee98a59
MM		 5142 {
5143 register int size = GET_MODE_SIZE (mode);
5144 register enum mode_class class = GET_MODE_CLASS (mode);
5145
5146 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5147 {
34b650b3
MM		 5148 register int temp;
5149
b8eb88d0
ILT		 5150 if (mode == CCmode)
5151 {
76ee8042 5152 if (! ISA_HAS_8CC)
b8eb88d0
ILT		 5153 temp = (regno == FPSW_REGNUM);
5154 else
f5963e61 5155 temp = (ST_REG_P (regno) || GP_REG_P (regno)
b8eb88d0
ILT		 5156 || FP_REG_P (regno));
5157 }
cee98a59 5158
34b650b3 5159 else if (GP_REG_P (regno))
f5963e61 5160 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
cee98a59
MM		 5161
5162 else if (FP_REG_P (regno))
5163 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
34b650b3
MM		 5164 && (class == MODE_FLOAT
5165 || class == MODE_COMPLEX_FLOAT
46299de9
ILT		 5166 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
5167 && (! TARGET_SINGLE_FLOAT || size <= 4));
cee98a59
MM		 5168
5169 else if (MD_REG_P (regno))
1cfb3048
RK		 5170 temp = (class == MODE_INT
5171 && (size <= UNITS_PER_WORD
f5963e61
JL		 5172 || (regno == MD_REG_FIRST
5173 && size == 2 * UNITS_PER_WORD)));
cee98a59 5174
34b650b3 5175 else
f5963e61 5176 temp = 0;
cee98a59
MM		 5177
5178 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5179 }
5180 }
bfed8dac 5181
45cc4c09
JW		 5182 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5183 initialized yet, so we can't use that here. */
5184 gpr_mode = TARGET_64BIT ? DImode : SImode;
efa3896a
GK		 5185
5186 /* Provide default values for align_* for 64-bit targets. */
ea64cab4 5187 if (TARGET_64BIT && !TARGET_MIPS16)
efa3896a
GK		 5188 {
5189 if (align_loops == 0)
5190 align_loops = 8;
5191 if (align_jumps == 0)
5192 align_jumps = 8;
5193 if (align_functions == 0)
5194 align_functions = 8;
5195 }
d07d525a
MM		 5196
5197 /* Register global variables with the garbage collector. */
5198 mips_add_gc_roots ();
cee98a59
MM		 5199}
5200
2bcb2ab3
GK		 5201/* On the mips16, we want to allocate $24 (T_REG) before other
5202 registers for instructions for which it is possible. This helps
5203 avoid shuffling registers around in order to set up for an xor,
5204 encouraging the compiler to use a cmp instead. */
5205
5206void
5207mips_order_regs_for_local_alloc ()
5208{
5209 register int i;
5210
5211 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5212 reg_alloc_order[i] = i;
5213
5214 if (TARGET_MIPS16)
5215 {
5216 /* It really doesn't matter where we put register 0, since it is
5217 a fixed register anyhow. */
5218 reg_alloc_order[0] = 24;
5219 reg_alloc_order[24] = 0;
5220 }
5221}
5222
cee98a59 5223\f
f5963e61
JL		 5224/* The MIPS debug format wants all automatic variables and arguments
5225 to be in terms of the virtual frame pointer (stack pointer before
5226 any adjustment in the function), while the MIPS 3.0 linker wants
5227 the frame pointer to be the stack pointer after the initial
5228 adjustment. So, we do the adjustment here. The arg pointer (which
5229 is eliminated) points to the virtual frame pointer, while the frame
5230 pointer (which may be eliminated) points to the stack pointer after
5231 the initial adjustments. */
5232
5233HOST_WIDE_INT
cee98a59
MM		 5234mips_debugger_offset (addr, offset)
5235 rtx addr;
f5963e61 5236 HOST_WIDE_INT offset;
cee98a59 5237{
c831afd5 5238 rtx offset2 = const0_rtx;
cee98a59
MM		 5239 rtx reg = eliminate_constant_term (addr, &offset2);
5240
f5963e61 5241 if (offset == 0)
c831afd5 5242 offset = INTVAL (offset2);
cee98a59 5243
2bcb2ab3
GK		 5244 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5245 || reg == hard_frame_pointer_rtx)
c831afd5 5246 {
f5963e61
JL		 5247 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
5248 ? compute_frame_size (get_frame_size ())
5249 : current_frame_info.total_size;
c831afd5 5250
a50f2a09
AC		 5251 /* MIPS16 frame is smaller */
5252 if (frame_pointer_needed && TARGET_MIPS16)
5253 frame_size -= current_function_outgoing_args_size;
5254
c831afd5
MM		 5255 offset = offset - frame_size;
5256 }
f5963e61 5257
acc15f57
RS		 5258 /* sdbout_parms does not want this to crash for unrecognized cases. */
5259#if 0
ab78d4a8
MM		 5260 else if (reg != arg_pointer_rtx)
5261 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
acc15f57 5262#endif
cee98a59
MM		 5263
5264 return offset;
5265}
5266\f
5267/* A C compound statement to output to stdio stream STREAM the
5268 assembler syntax for an instruction operand X. X is an RTL
5269 expression.
5270
5271 CODE is a value that can be used to specify one of several ways
5272 of printing the operand. It is used when identical operands
5273 must be printed differently depending on the context. CODE
5274 comes from the `%' specification that was used to request
5275 printing of the operand. If the specification was just `%DIGIT'
5276 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5277 is the ASCII code for LTR.
5278
5279 If X is a register, this macro should print the register's name.
5280 The names can be found in an array `reg_names' whose type is
5281 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5282
5283 When the machine description has a specification `%PUNCT' (a `%'
5284 followed by a punctuation character), this macro is called with
5285 a null pointer for X and the punctuation character for CODE.
5286
5287 The MIPS specific codes are:
5288
5289 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5290 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5291 'd' output integer constant in decimal,
5292 'z' if the operand is 0, use $0 instead of normal operand.
5293 'D' print second register of double-word register operand.
5294 'L' print low-order register of double-word register operand.
5295 'M' print high-order register of double-word register operand.
5296 'C' print part of opcode for a branch condition.
0ff83799 5297 'F' print part of opcode for a floating-point branch condition.
cee98a59 5298 'N' print part of opcode for a branch condition, inverted.
0ff83799 5299 'W' print part of opcode for a floating-point branch condition, inverted.
e0bfcea5 5300 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
33563487
JW		 5301 'B' print 'z' for EQ, 'n' for NE
5302 'b' print 'n' for EQ, 'z' for NE
5303 'T' print 'f' for EQ, 't' for NE
5304 't' print 't' for EQ, 'f' for NE
b8eb88d0 5305 'Z' print register and a comma, but print nothing for $fcc0
cee98a59
MM		 5306 '(' Turn on .set noreorder
5307 ')' Turn on .set reorder
5308 '[' Turn on .set noat
5309 ']' Turn on .set at
5310 '<' Turn on .set nomacro
5311 '>' Turn on .set macro
5312 '{' Turn on .set volatile (not GAS)
5313 '}' Turn on .set novolatile (not GAS)
5314 '&' Turn on .set noreorder if filling delay slots
5315 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5316 '!' Turn on .set nomacro if filling delay slots
5317 '#' Print nop if in a .set noreorder section.
5318 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5319 '@' Print the name of the assembler temporary register (at or $1).
ffa9d0b1 5320 '.' Print the name of the register with a hard-wired zero (zero or $0).
2bcb2ab3
GK		 5321 '^' Print the name of the pic call-through register (t9 or $25).
5322 '$' Print the name of the stack pointer register (sp or $29).
efa3896a
GK		 5323 '+' Print the name of the gp register (gp or $28).
5324 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
cee98a59
MM		 5325
5326void
5327print_operand (file, op, letter)
5328 FILE *file; /* file to write to */
5329 rtx op; /* operand to print */
5330 int letter; /* %<letter> or 0 */
5331{
5332 register enum rtx_code code;
5333
5334 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5335 {
5336 switch (letter)
5337 {
cee98a59
MM		 5338 case '?':
5339 if (mips_branch_likely)
5340 putc ('l', file);
5341 break;
5342
5343 case '@':
5344 fputs (reg_names [GP_REG_FIRST + 1], file);
5345 break;
5346
ffa9d0b1
JW		 5347 case '^':
5348 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5349 break;
5350
cee98a59
MM		 5351 case '.':
5352 fputs (reg_names [GP_REG_FIRST + 0], file);
5353 break;
5354
2bcb2ab3
GK		 5355 case '$':
5356 fputs (reg_names[STACK_POINTER_REGNUM], file);
5357 break;
5358
5359 case '+':
5360 fputs (reg_names[GP_REG_FIRST + 28], file);
5361 break;
5362
cee98a59
MM		 5363 case '&':
5364 if (final_sequence != 0 && set_noreorder++ == 0)
5365 fputs (".set\tnoreorder\n\t", file);
5366 break;
5367
5368 case '*':
5369 if (final_sequence != 0)
5370 {
5371 if (set_noreorder++ == 0)
5372 fputs (".set\tnoreorder\n\t", file);
5373
5374 if (set_nomacro++ == 0)
5375 fputs (".set\tnomacro\n\t", file);
5376 }
5377 break;
5378
5379 case '!':
5380 if (final_sequence != 0 && set_nomacro++ == 0)
5381 fputs ("\n\t.set\tnomacro", file);
5382 break;
5383
5384 case '#':
5385 if (set_noreorder != 0)
5386 fputs ("\n\tnop", file);
85098019 5387 else if (TARGET_STATS)
cee98a59
MM		 5388 fputs ("\n\t#nop", file);
5389
5390 break;
5391
5392 case '(':
5393 if (set_noreorder++ == 0)
5394 fputs (".set\tnoreorder\n\t", file);
5395 break;
5396
5397 case ')':
5398 if (set_noreorder == 0)
5399 error ("internal error: %%) found without a %%( in assembler pattern");
5400
5401 else if (--set_noreorder == 0)
5402 fputs ("\n\t.set\treorder", file);
5403
5404 break;
5405
5406 case '[':
5407 if (set_noat++ == 0)
5408 fputs (".set\tnoat\n\t", file);
5409 break;
5410
5411 case ']':
5412 if (set_noat == 0)
5413 error ("internal error: %%] found without a %%[ in assembler pattern");
cee98a59
MM		 5414 else if (--set_noat == 0)
5415 fputs ("\n\t.set\tat", file);
5416
5417 break;
5418
5419 case '<':
5420 if (set_nomacro++ == 0)
5421 fputs (".set\tnomacro\n\t", file);
5422 break;
5423
5424 case '>':
5425 if (set_nomacro == 0)
5426 error ("internal error: %%> found without a %%< in assembler pattern");
cee98a59
MM		 5427 else if (--set_nomacro == 0)
5428 fputs ("\n\t.set\tmacro", file);
5429
5430 break;
5431
5432 case '{':
5433 if (set_volatile++ == 0)
f5963e61 5434 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
cee98a59
MM		 5435 break;
5436
5437 case '}':
5438 if (set_volatile == 0)
5439 error ("internal error: %%} found without a %%{ in assembler pattern");
cee98a59
MM		 5440 else if (--set_volatile == 0)
5441 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5442
5443 break;
f5963e61 5444
efa3896a
GK		 5445 case '~':
5446 {
5447 if (align_labels_log > 0)
5448 ASM_OUTPUT_ALIGN (file, align_labels_log);
5449 }
5450 break;
5451
f5963e61
JL		 5452 default:
5453 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
5454 break;
cee98a59 5455 }
f5963e61 5456
cee98a59
MM		 5457 return;
5458 }
5459
5460 if (! op)
5461 {
5462 error ("PRINT_OPERAND null pointer");
5463 return;
5464 }
5465
5466 code = GET_CODE (op);
2a0b0bf5
ILT		 5467
5468 if (code == SIGN_EXTEND)
f5963e61 5469 op = XEXP (op, 0), code = GET_CODE (op);
2a0b0bf5 5470
cee98a59
MM		 5471 if (letter == 'C')
5472 switch (code)
5473 {
5474 case EQ: fputs ("eq", file); break;
5475 case NE: fputs ("ne", file); break;
5476 case GT: fputs ("gt", file); break;
5477 case GE: fputs ("ge", file); break;
5478 case LT: fputs ("lt", file); break;
5479 case LE: fputs ("le", file); break;
5480 case GTU: fputs ("gtu", file); break;
5481 case GEU: fputs ("geu", file); break;
5482 case LTU: fputs ("ltu", file); break;
5483 case LEU: fputs ("leu", file); break;
cee98a59 5484 default:
e7f6e33b 5485 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
cee98a59
MM		 5486 }
5487
5488 else if (letter == 'N')
5489 switch (code)
5490 {
5491 case EQ: fputs ("ne", file); break;
5492 case NE: fputs ("eq", file); break;
5493 case GT: fputs ("le", file); break;
5494 case GE: fputs ("lt", file); break;
5495 case LT: fputs ("ge", file); break;
5496 case LE: fputs ("gt", file); break;
5497 case GTU: fputs ("leu", file); break;
5498 case GEU: fputs ("ltu", file); break;
5499 case LTU: fputs ("geu", file); break;
5500 case LEU: fputs ("gtu", file); break;
cee98a59 5501 default:
e7f6e33b 5502 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
cee98a59
MM		 5503 }
5504
0ff83799
MM		 5505 else if (letter == 'F')
5506 switch (code)
5507 {
5508 case EQ: fputs ("c1f", file); break;
5509 case NE: fputs ("c1t", file); break;
5510 default:
5511 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5512 }
5513
5514 else if (letter == 'W')
5515 switch (code)
5516 {
5517 case EQ: fputs ("c1t", file); break;
5518 case NE: fputs ("c1f", file); break;
5519 default:
5520 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5521 }
5522
e0bfcea5
ILT		 5523 else if (letter == 'S')
5524 {
5525 char buffer[100];
5526
5527 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5528 assemble_name (file, buffer);
5529 }
5530
b8eb88d0
ILT		 5531 else if (letter == 'Z')
5532 {
5533 register int regnum;
5534
5535 if (code != REG)
5536 abort ();
f5963e61 5537
b8eb88d0
ILT		 5538 regnum = REGNO (op);
5539 if (! ST_REG_P (regnum))
5540 abort ();
f5963e61 5541
b8eb88d0
ILT		 5542 if (regnum != ST_REG_FIRST)
5543 fprintf (file, "%s,", reg_names[regnum]);
5544 }
5545
2a0b0bf5 5546 else if (code == REG || code == SUBREG)
cee98a59 5547 {
2a0b0bf5
ILT		 5548 register int regnum;
5549
5550 if (code == REG)
5551 regnum = REGNO (op);
5552 else
5553 regnum = true_regnum (op);
cee98a59 5554
96abdcb1
ILT		 5555 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5556 || (letter == 'L' && WORDS_BIG_ENDIAN)
5557 || letter == 'D')
cee98a59
MM		 5558 regnum++;
5559
5560 fprintf (file, "%s", reg_names[regnum]);
5561 }
5562
5563 else if (code == MEM)
5564 output_address (XEXP (op, 0));
5565
28ae04f1
ILT		 5566 else if (code == CONST_DOUBLE
5567 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
cee98a59 5568 {
147255d8
JW		 5569 REAL_VALUE_TYPE d;
5570 char s[30];
5571
5572 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5573 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5574 fprintf (file, s);
cee98a59
MM		 5575 }
5576
f5963e61 5577 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
8f9661dd 5578 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
f5963e61
JL		 5579
5580 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5581 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5582
5583 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5584 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
cee98a59 5585
f5963e61 5586 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
cee98a59
MM		 5587 fputs (reg_names[GP_REG_FIRST], file);
5588
5589 else if (letter == 'd' || letter == 'x' || letter == 'X')
400500c4 5590 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
cee98a59 5591
33563487
JW		 5592 else if (letter == 'B')
5593 fputs (code == EQ ? "z" : "n", file);
5594 else if (letter == 'b')
5595 fputs (code == EQ ? "n" : "z", file);
5596 else if (letter == 'T')
5597 fputs (code == EQ ? "f" : "t", file);
5598 else if (letter == 't')
5599 fputs (code == EQ ? "t" : "f", file);
5600
2bcb2ab3
GK		 5601 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5602 {
5603 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5604 print_operand (file, XEXP (op, 0), letter);
5605 }
5606
5607 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5608 {
5609 fputs ("%gprel(", file);
5610 mips16_output_gp_offset (file, op);
5611 fputs (")", file);
5612 }
5613
cee98a59
MM		 5614 else
5615 output_addr_const (file, op);
5616}
cee98a59
MM		 5617\f
5618/* A C compound statement to output to stdio stream STREAM the
5619 assembler syntax for an instruction operand that is a memory
5620 reference whose address is ADDR. ADDR is an RTL expression.
5621
5622 On some machines, the syntax for a symbolic address depends on
5623 the section that the address refers to. On these machines,
5624 define the macro `ENCODE_SECTION_INFO' to store the information
5625 into the `symbol_ref', and then check for it here. */
5626
5627void
5628print_operand_address (file, addr)
5629 FILE *file;
5630 rtx addr;
5631{
5632 if (!addr)
5633 error ("PRINT_OPERAND_ADDRESS, null pointer");
5634
5635 else
5636 switch (GET_CODE (addr))
5637 {
cee98a59 5638 case REG:
2bcb2ab3 5639 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
ab78d4a8
MM		 5640 abort_with_insn (addr, "Arg pointer not eliminated.");
5641
cee98a59
MM		 5642 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5643 break;
5644
910628b8
JW		 5645 case LO_SUM:
5646 {
f5963e61
JL		 5647 register rtx arg0 = XEXP (addr, 0);
5648 register rtx arg1 = XEXP (addr, 1);
910628b8
JW		 5649
5650 if (! mips_split_addresses)
5651 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
5652
5653 if (GET_CODE (arg0) != REG)
f5963e61
JL		 5654 abort_with_insn (addr,
5655 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
910628b8
JW		 5656
5657 fprintf (file, "%%lo(");
5658 print_operand_address (file, arg1);
5659 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5660 }
5661 break;
5662
cee98a59
MM		 5663 case PLUS:
5664 {
f5963e61
JL		 5665 register rtx reg = 0;
5666 register rtx offset = 0;
5667 register rtx arg0 = XEXP (addr, 0);
5668 register rtx arg1 = XEXP (addr, 1);
cee98a59
MM		 5669
5670 if (GET_CODE (arg0) == REG)
5671 {
5672 reg = arg0;
5673 offset = arg1;
5674 if (GET_CODE (offset) == REG)
5675 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5676 }
f5963e61 5677
cee98a59 5678 else if (GET_CODE (arg1) == REG)
f5963e61 5679 reg = arg1, offset = arg0;
cee98a59
MM		 5680 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5681 {
5682 output_addr_const (file, addr);
5683 break;
5684 }
5685 else
5686 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5687
f5963e61 5688 if (! CONSTANT_P (offset))
e7f6e33b 5689 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
cee98a59 5690
910628b8
JW		 5691 if (REGNO (reg) == ARG_POINTER_REGNUM)
5692 abort_with_insn (addr, "Arg pointer not eliminated.");
ab78d4a8 5693
2bcb2ab3
GK		 5694 if (TARGET_MIPS16
5695 && GET_CODE (offset) == CONST
5696 && mips16_gp_offset_p (offset))
5697 {
5698 fputs ("%gprel(", file);
5699 mips16_output_gp_offset (file, offset);
5700 fputs (")", file);
5701 }
5702 else
5703 output_addr_const (file, offset);
cee98a59
MM		 5704 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5705 }
5706 break;
5707
5708 case LABEL_REF:
5709 case SYMBOL_REF:
5710 case CONST_INT:
5711 case CONST:
5712 output_addr_const (file, addr);
5713 break;
f5963e61
JL		 5714
5715 default:
5716 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5717 break;
cee98a59
MM		 5718 }
5719}
5720
5721\f
f5963e61
JL		 5722/* If optimizing for the global pointer, keep track of all of the externs, so
5723 that at the end of the file, we can emit the appropriate .extern
5724 declaration for them, before writing out the text section. We assume all
5725 names passed to us are in the permanent obstack, so they will be valid at
5726 the end of the compilation.
5727
5728 If we have -G 0, or the extern size is unknown, or the object is in a user
5729 specified section that is not .sbss/.sdata, don't bother emitting the
5730 .externs. In the case of user specified sections this behaviour is
5731 required as otherwise GAS will think the object lives in .sbss/.sdata. */
cee98a59
MM		 5732
5733int
5734mips_output_external (file, decl, name)
38831dfe 5735 FILE *file ATTRIBUTE_UNUSED;
cee98a59 5736 tree decl;
bd9f1972 5737 const char *name;
cee98a59
MM		 5738{
5739 register struct extern_list *p;
5740 int len;
4144ff62 5741 tree section_name;
cee98a59
MM		 5742
5743 if (TARGET_GP_OPT
f5963e61
JL		 5744 && TREE_CODE (decl) != FUNCTION_DECL
5745 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5746 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
4144ff62
DE		 5747 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5748 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
cee98a59 5749 {
f5963e61 5750 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
cee98a59
MM		 5751 p->next = extern_head;
5752 p->name = name;
5753 p->size = len;
5754 extern_head = p;
5755 }
5619cc87
JW		 5756
5757#ifdef ASM_OUTPUT_UNDEF_FUNCTION
dd947ed9
RK		 5758 if (TREE_CODE (decl) == FUNCTION_DECL
5759 /* ??? Don't include alloca, since gcc will always expand it
e5e809f4 5760 inline. If we don't do this, the C++ library fails to build. */
9f770b61
JW		 5761 && strcmp (name, "alloca")
5762 /* ??? Don't include __builtin_next_arg, because then gcc will not
5763 bootstrap under Irix 5.1. */
5764 && strcmp (name, "__builtin_next_arg"))
5619cc87 5765 {
f5963e61 5766 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5619cc87
JW		 5767 p->next = extern_head;
5768 p->name = name;
5769 p->size = -1;
5770 extern_head = p;
5771 }
5772#endif
5773
5774 return 0;
5775}
5776
5777#ifdef ASM_OUTPUT_UNDEF_FUNCTION
5778int
5779mips_output_external_libcall (file, name)
5780 FILE *file;
bd9f1972 5781 const char *name;
5619cc87
JW		 5782{
5783 register struct extern_list *p;
5784
f5963e61 5785 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5619cc87
JW		 5786 p->next = extern_head;
5787 p->name = name;
5788 p->size = -1;
5789 extern_head = p;
5790
cee98a59
MM		 5791 return 0;
5792}
5619cc87 5793#endif
cee98a59
MM		 5794\f
5795/* Compute a string to use as a temporary file name. */
5796
5797static FILE *
5a657fc3 5798mips_make_temp_file ()
cee98a59 5799{
cee98a59 5800 FILE *stream;
cee98a59 5801
e1b71de9 5802 temp_filename = make_temp_file (0);
8bb3dc77 5803 stream = fopen (temp_filename, "w+");
cee98a59 5804 if (!stream)
e1b71de9 5805 fatal_io_error ("can't open %s", temp_filename);
cee98a59
MM		 5806 return stream;
5807}
cee98a59
MM		 5808\f
5809/* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5810 for .file's that start within a function. If we are smuggling stabs, try to
5811 put out a MIPS ECOFF file and a stab. */
5812
5813void
5814mips_output_filename (stream, name)
5815 FILE *stream;
bd9f1972 5816 const char *name;
cee98a59 5817{
f5963e61 5818 static int first_time = 1;
cee98a59
MM		 5819 char ltext_label_name[100];
5820
5821 if (first_time)
5822 {
f5963e61 5823 first_time = 0;
cee98a59
MM		 5824 SET_FILE_NUMBER ();
5825 current_function_file = name;
33563487 5826 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
2bacb292 5827 /* This tells mips-tfile that stabs will follow. */
9987501f
MM		 5828 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5829 fprintf (stream, "\t#@stabs\n");
cee98a59
MM		 5830 }
5831
2bacb292 5832 else if (write_symbols == DBX_DEBUG)
cee98a59
MM		 5833 {
5834 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
016c8440 5835 fprintf (stream, "%s", ASM_STABS_OP);
99107e86
PE		 5836 output_quoted_string (stream, name);
5837 fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
cee98a59
MM		 5838 }
5839
5840 else if (name != current_function_file
5841 && strcmp (name, current_function_file) != 0)
5842 {
5843 if (inside_function && !TARGET_GAS)
5844 {
5845 if (!file_in_function_warning)
5846 {
f5963e61
JL		 5847 file_in_function_warning = 1;
5848 ignore_line_number = 1;
cee98a59
MM		 5849 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5850 }
cee98a59 5851 }
cee98a59
MM		 5852 else
5853 {
5854 SET_FILE_NUMBER ();
5855 current_function_file = name;
33563487 5856 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
cee98a59
MM		 5857 }
5858 }
5859}
cee98a59
MM		 5860\f
5861/* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5862 as well as a .loc, since it is possible that MIPS ECOFF might not be
5863 able to represent the location for inlines that come from a different
5864 file. */
5865
5866void
5867mips_output_lineno (stream, line)
5868 FILE *stream;
5869 int line;
5870{
2bacb292 5871 if (write_symbols == DBX_DEBUG)
cee98a59
MM		 5872 {
5873 ++sym_lineno;
016c8440 5874 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
dccc9e85
JW		 5875 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5876 LOCAL_LABEL_PREFIX, sym_lineno);
cee98a59
MM		 5877 }
5878
5879 else
5880 {
5881 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5882 (ignore_line_number) ? "#" : "",
5883 num_source_filenames, line);
5884
5885 LABEL_AFTER_LOC (stream);
5886 }
5887}
65437fe8 5888\f
f5963e61
JL		 5889/* If defined, a C statement to be executed just prior to the output of
5890 assembler code for INSN, to modify the extracted operands so they will be
5891 output differently.
65437fe8 5892
f5963e61
JL		 5893 Here the argument OPVEC is the vector containing the operands extracted
5894 from INSN, and NOPERANDS is the number of elements of the vector which
5895 contain meaningful data for this insn. The contents of this vector are
5896 what will be used to convert the insn template into assembler code, so you
5897 can change the assembler output by changing the contents of the vector.
65437fe8 5898
f5963e61
JL		 5899 We use it to check if the current insn needs a nop in front of it because
5900 of load delays, and also to update the delay slot statistics. */
65437fe8 5901
85098019
JW		 5902/* ??? There is no real need for this function, because it never actually
5903 emits a NOP anymore. */
5904
65437fe8
MM		 5905void
5906final_prescan_insn (insn, opvec, noperands)
5907 rtx insn;
38831dfe
KG		 5908 rtx opvec[] ATTRIBUTE_UNUSED;
5909 int noperands ATTRIBUTE_UNUSED;
65437fe8
MM		 5910{
5911 if (dslots_number_nops > 0)
5912 {
65437fe8
MM		 5913 rtx pattern = PATTERN (insn);
5914 int length = get_attr_length (insn);
5915
5916 /* Do we need to emit a NOP? */
5917 if (length == 0
f5963e61
JL		 5918 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
5919 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5920 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5921 || (mips_load_reg4 != 0
5922 && reg_mentioned_p (mips_load_reg4, pattern)))
85098019 5923 fputs ("\t#nop\n", asm_out_file);
65437fe8
MM		 5924
5925 else
5926 dslots_load_filled++;
5927
5928 while (--dslots_number_nops > 0)
85098019 5929 fputs ("\t#nop\n", asm_out_file);
65437fe8 5930
f5963e61
JL		 5931 mips_load_reg = 0;
5932 mips_load_reg2 = 0;
5933 mips_load_reg3 = 0;
5934 mips_load_reg4 = 0;
65437fe8
MM		 5935 }
5936
f5963e61
JL		 5937 if (TARGET_STATS
5938 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
5939 dslots_jump_total++;
65437fe8 5940}
cee98a59
MM		 5941\f
5942/* Output at beginning of assembler file.
f5963e61
JL		 5943
5944 If we are optimizing to use the global pointer, create a temporary file to
5945 hold all of the text stuff, and write it out to the end. This is needed
5946 because the MIPS assembler is evidently one pass, and if it hasn't seen the
5947 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
5948 processed, it generates a two instruction sequence. */
cee98a59
MM		 5949
5950void
5951mips_asm_file_start (stream)
5952 FILE *stream;
5953{
5954 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
5955
f5963e61
JL		 5956 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5957 inside of a .set noreorder section jumps to a label outside of the .set
5958 noreorder section. Revision 2.20 just set nobopt silently rather than
5959 fixing the bug. */
cee98a59
MM		 5960
5961 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5962 fprintf (stream, "\t.set\tnobopt\n");
5963
ffa9d0b1 5964 /* Generate the pseudo ops that System V.4 wants. */
c388a0c4 5965#ifndef ABICALLS_ASM_OP
78d057d8 5966#define ABICALLS_ASM_OP "\t.abicalls"
c388a0c4 5967#endif
cee98a59 5968 if (TARGET_ABICALLS)
ffa9d0b1 5969 /* ??? but do not want this (or want pic0) if -non-shared? */
016c8440 5970 fprintf (stream, "%s\n", ABICALLS_ASM_OP);
cee98a59 5971
2bcb2ab3
GK		 5972 if (TARGET_MIPS16)
5973 fprintf (stream, "\t.set\tmips16\n");
5974
33563487
JW		 5975 /* Start a section, so that the first .popsection directive is guaranteed
5976 to have a previously defined section to pop back to. */
a53f72db 5977 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
33563487
JW		 5978 fprintf (stream, "\t.section\t.text\n");
5979
d7a58f30 5980 /* This code exists so that we can put all externs before all symbol
d46c6fce 5981 references. This is necessary for the MIPS assembler's global pointer
d7a58f30 5982 optimizations to work. */
2bcb2ab3 5983 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
cee98a59
MM		 5984 {
5985 asm_out_data_file = stream;
5a657fc3 5986 asm_out_text_file = mips_make_temp_file ();
cee98a59 5987 }
f5963e61 5988
cee98a59
MM		 5989 else
5990 asm_out_data_file = asm_out_text_file = stream;
5991
2096c147
DE		 5992 if (flag_verbose_asm)
5993 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
5994 ASM_COMMENT_START,
5995 mips_section_threshold, mips_cpu_string, mips_isa);
cee98a59 5996}
cee98a59 5997\f
f5963e61
JL		 5998/* If we are optimizing the global pointer, emit the text section now and any
5999 small externs which did not have .comm, etc that are needed. Also, give a
6000 warning if the data area is more than 32K and -pic because 3 instructions
6001 are needed to reference the data pointers. */
cee98a59
MM		 6002
6003void
6004mips_asm_file_end (file)
6005 FILE *file;
6006{
6007 char buffer[8192];
6008 tree name_tree;
6009 struct extern_list *p;
6010 int len;
842eb20e
MM		 6011
6012 if (HALF_PIC_P ())
6e92f4b6
KG		 6013 {
6014 HALF_PIC_FINISH (file);
6015 }
cee98a59 6016
5619cc87 6017 if (extern_head)
cee98a59 6018 {
5619cc87 6019 fputs ("\n", file);
cee98a59
MM		 6020
6021 for (p = extern_head; p != 0; p = p->next)
6022 {
6023 name_tree = get_identifier (p->name);
c831afd5
MM		 6024
6025 /* Positively ensure only one .extern for any given symbol. */
6026 if (! TREE_ASM_WRITTEN (name_tree))
cee98a59 6027 {
c831afd5 6028 TREE_ASM_WRITTEN (name_tree) = 1;
5619cc87
JW		 6029#ifdef ASM_OUTPUT_UNDEF_FUNCTION
6030 if (p->size == -1)
6031 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6032 else
6033#endif
6034 {
6035 fputs ("\t.extern\t", file);
6036 assemble_name (file, p->name);
6037 fprintf (file, ", %d\n", p->size);
6038 }
cee98a59
MM		 6039 }
6040 }
5619cc87
JW		 6041 }
6042
2bcb2ab3 6043 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5619cc87 6044 {
cee98a59
MM		 6045 fprintf (file, "\n\t.text\n");
6046 rewind (asm_out_text_file);
6047 if (ferror (asm_out_text_file))
e2bbb660 6048 fatal_io_error ("can't rewind %s", temp_filename);
cee98a59
MM		 6049
6050 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
973838fd 6051 if ((int) fwrite (buffer, 1, len, file) != len)
e2bbb660 6052 fatal_io_error ("can't write to %s", asm_file_name);
cee98a59
MM		 6053
6054 if (len < 0)
e2bbb660 6055 fatal_io_error ("can't read from %s", temp_filename);
cee98a59
MM		 6056
6057 if (fclose (asm_out_text_file) != 0)
e2bbb660 6058 fatal_io_error ("can't close %s", temp_filename);
147255d8 6059
147255d8 6060 unlink (temp_filename);
e1b71de9 6061 free (temp_filename);
cee98a59
MM		 6062 }
6063}
6064
f5963e61
JL		 6065/* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6066 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
9987501f
MM		 6067
6068void
6069mips_declare_object (stream, name, init_string, final_string, size)
6070 FILE *stream;
bd9f1972
KG		 6071 const char *name;
6072 const char *init_string;
6073 const char *final_string;
9987501f
MM		 6074 int size;
6075{
6076 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
6077 assemble_name (stream, name);
6078 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6079
147255d8 6080 if (TARGET_GP_OPT)
9987501f
MM		 6081 {
6082 tree name_tree = get_identifier (name);
6083 TREE_ASM_WRITTEN (name_tree) = 1;
6084 }
6085}
dbe9742d
MM		 6086\f
6087/* Output a double precision value to the assembler. If both the
6088 host and target are IEEE, emit the values in hex. */
6089
6090void
6091mips_output_double (stream, value)
6092 FILE *stream;
6093 REAL_VALUE_TYPE value;
6094{
6095#ifdef REAL_VALUE_TO_TARGET_DOUBLE
6096 long value_long[2];
6097 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
6098
6099 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
6100 value_long[0], value, value_long[1]);
6101#else
6102 fprintf (stream, "\t.double\t%.20g\n", value);
6103#endif
6104}
6105
dbe9742d
MM		 6106/* Output a single precision value to the assembler. If both the
6107 host and target are IEEE, emit the values in hex. */
6108
6109void
6110mips_output_float (stream, value)
6111 FILE *stream;
6112 REAL_VALUE_TYPE value;
6113{
6114#ifdef REAL_VALUE_TO_TARGET_SINGLE
6115 long value_long;
6116 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
6117
6118 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
6119#else
6120 fprintf (stream, "\t.float\t%.12g\n", value);
6121#endif
6122}
cee98a59
MM		 6123\f
6124/* Return the bytes needed to compute the frame pointer from the current
6125 stack pointer.
6126
6127 Mips stack frames look like:
6128
6129 Before call After call
6130 +-----------------------+ +-----------------------+
6131 high | | | |
6132 mem. | | | |
6133 | caller's temps. | | caller's temps. |
6134 | | | |
6135 +-----------------------+ +-----------------------+
6136 | | | |
6137 | arguments on stack. | | arguments on stack. |
6138 | | | |
6139 +-----------------------+ +-----------------------+
6140 | 4 words to save | | 4 words to save |
6141 | arguments passed | | arguments passed |
6142 | in registers, even | | in registers, even |
ffa9d0b1 6143 SP->| if not passed. | VFP->| if not passed. |
cee98a59 6144 +-----------------------+ +-----------------------+
cee98a59
MM		 6145 | |
6146 | fp register save |
6147 | |
6148 +-----------------------+
6149 | |
6150 | gp register save |
6151 | |
6152 +-----------------------+
6153 | |
ab78d4a8
MM		 6154 | local variables |
6155 | |
6156 +-----------------------+
6157 | |
cee98a59
MM		 6158 | alloca allocations |
6159 | |
6160 +-----------------------+
6161 | |
ffa9d0b1
JW		 6162 | GP save for V.4 abi |
6163 | |
6164 +-----------------------+
6165 | |
cee98a59
MM		 6166 | arguments on stack |
6167 | |
6168 +-----------------------+
6169 | 4 words to save |
6170 | arguments passed |
6171 | in registers, even |
6172 low SP->| if not passed. |
6173 memory +-----------------------+
6174
6175*/
6176
f5963e61 6177HOST_WIDE_INT
cee98a59 6178compute_frame_size (size)
db4c1c35 6179 HOST_WIDE_INT size; /* # of var. bytes allocated */
cee98a59
MM		 6180{
6181 int regno;
f5963e61
JL		 6182 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6183 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6184 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6185 HOST_WIDE_INT extra_size; /* # extra bytes */
6186 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6187 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6188 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
7bea35e7
MM		 6189 long mask; /* mask of saved gp registers */
6190 long fmask; /* mask of saved fp registers */
6191 int fp_inc; /* 1 or 2 depending on the size of fp regs */
6192 long fp_bits; /* bitmask to use for each fp register */
cee98a59 6193
f5963e61
JL		 6194 gp_reg_size = 0;
6195 fp_reg_size = 0;
6196 mask = 0;
6197 fmask = 0;
6198 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6199 var_size = MIPS_STACK_ALIGN (size);
6200 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
ab78d4a8
MM		 6201
6202 /* The MIPS 3.0 linker does not like functions that dynamically
6203 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6204 looks like we are trying to create a second frame pointer to the
6205 function, so allocate some stack space to make it happy. */
6206
6207 if (args_size == 0 && current_function_calls_alloca)
f5963e61 6208 args_size = 4 * UNITS_PER_WORD;
ab78d4a8
MM		 6209
6210 total_size = var_size + args_size + extra_size;
cee98a59
MM		 6211
6212 /* Calculate space needed for gp registers. */
6213 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6214 {
2bcb2ab3
GK		 6215 /* $18 is a special case on the mips16. It may be used to call
6216 a function which returns a floating point value, but it is
6217 marked in call_used_regs. $31 is also a special case. When
6218 not using -mentry, it will be used to copy a return value
6219 into the floating point registers if the return value is
6220 floating point. */
6221 if (MUST_SAVE_REGISTER (regno)
6222 || (TARGET_MIPS16
6223 && regno == GP_REG_FIRST + 18
6224 && regs_ever_live[regno])
6225 || (TARGET_MIPS16
6226 && regno == GP_REG_FIRST + 31
6227 && mips16_hard_float
6228 && ! mips_entry
6229 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6230 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6231 == MODE_FLOAT)
6232 && (! TARGET_SINGLE_FLOAT
6233 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6234 <= 4))))
cee98a59 6235 {
bfed8dac 6236 gp_reg_size += GET_MODE_SIZE (gpr_mode);
7bea35e7 6237 mask |= 1L << (regno - GP_REG_FIRST);
2bcb2ab3
GK		 6238
6239 /* The entry and exit pseudo instructions can not save $17
6240 without also saving $16. */
6241 if (mips_entry
6242 && regno == GP_REG_FIRST + 17
6243 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6244 {
6245 gp_reg_size += UNITS_PER_WORD;
6246 mask |= 1L << 16;
6247 }
cee98a59
MM		 6248 }
6249 }
6250
6251 /* Calculate space needed for fp registers. */
46299de9 6252 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
cee98a59
MM		 6253 {
6254 fp_inc = 1;
6255 fp_bits = 1;
6256 }
6257 else
6258 {
6259 fp_inc = 2;
6260 fp_bits = 3;
6261 }
6262
d1d3a2df
JL		 6263 /* This loop must iterate over the same space as its companion in
6264 save_restore_regs. */
6265 for (regno = (FP_REG_LAST - fp_inc + 1);
6266 regno >= FP_REG_FIRST;
6267 regno -= fp_inc)
cee98a59
MM		 6268 {
6269 if (regs_ever_live[regno] && !call_used_regs[regno])
6270 {
147255d8 6271 fp_reg_size += fp_inc * UNITS_PER_FPREG;
cee98a59
MM		 6272 fmask |= fp_bits << (regno - FP_REG_FIRST);
6273 }
6274 }
6275
6276 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
46299de9 6277 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
cee98a59 6278
33563487
JW		 6279 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6280 for leaf routines (total_size == extra_size) to save the gp reg.
6281 The gp reg is callee saved in the 64 bit ABI, so all routines must
a944a4eb
JW		 6282 save the gp reg. This is not a leaf routine if -p, because of the
6283 call to mcount. */
a53f72db
GRK		 6284 if (total_size == extra_size
6285 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
a944a4eb 6286 && ! profile_flag)
cee98a59 6287 total_size = extra_size = 0;
ffa9d0b1
JW		 6288 else if (TARGET_ABICALLS)
6289 {
6290 /* Add the context-pointer to the saved registers. */
6291 gp_reg_size += UNITS_PER_WORD;
6292 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6293 total_size -= gp_reg_rounded;
6294 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6295 total_size += gp_reg_rounded;
6296 }
cee98a59 6297
33563487
JW		 6298 /* Add in space reserved on the stack by the callee for storing arguments
6299 passed in registers. */
a53f72db 6300 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
33563487
JW		 6301 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6302
2bcb2ab3
GK		 6303 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6304 if (mips_entry && total_size > 0 && total_size < 32)
6305 total_size = 32;
6306
cee98a59 6307 /* Save other computed information. */
f5963e61
JL		 6308 current_frame_info.total_size = total_size;
6309 current_frame_info.var_size = var_size;
6310 current_frame_info.args_size = args_size;
6311 current_frame_info.extra_size = extra_size;
cee98a59
MM		 6312 current_frame_info.gp_reg_size = gp_reg_size;
6313 current_frame_info.fp_reg_size = fp_reg_size;
f5963e61
JL		 6314 current_frame_info.mask = mask;
6315 current_frame_info.fmask = fmask;
cee98a59 6316 current_frame_info.initialized = reload_completed;
f5963e61
JL		 6317 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
6318 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
cee98a59
MM		 6319
6320 if (mask)
6321 {
2bcb2ab3
GK		 6322 unsigned long offset;
6323
6324 /* When using mips_entry, the registers are always saved at the
6325 top of the stack. */
6326 if (! mips_entry)
6327 offset = (args_size + extra_size + var_size
bfed8dac 6328 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
2bcb2ab3 6329 else
bfed8dac
JL		 6330 offset = total_size - GET_MODE_SIZE (gpr_mode);
6331
cee98a59
MM		 6332 current_frame_info.gp_sp_offset = offset;
6333 current_frame_info.gp_save_offset = offset - total_size;
6334 }
258d81a8
MM		 6335 else
6336 {
6337 current_frame_info.gp_sp_offset = 0;
6338 current_frame_info.gp_save_offset = 0;
6339 }
6340
cee98a59
MM		 6341 if (fmask)
6342 {
147255d8
JW		 6343 unsigned long offset = (args_size + extra_size + var_size
6344 + gp_reg_rounded + fp_reg_size
6345 - fp_inc * UNITS_PER_FPREG);
cee98a59 6346 current_frame_info.fp_sp_offset = offset;
a94dbf2c 6347 current_frame_info.fp_save_offset = offset - total_size;
cee98a59 6348 }
258d81a8
MM		 6349 else
6350 {
6351 current_frame_info.fp_sp_offset = 0;
6352 current_frame_info.fp_save_offset = 0;
6353 }
cee98a59
MM		 6354
6355 /* Ok, we're done. */
6356 return total_size;
6357}
cee98a59 6358\f
7bea35e7
MM		 6359/* Common code to emit the insns (or to write the instructions to a file)
6360 to save/restore registers.
cee98a59 6361
7bea35e7
MM		 6362 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6363 is not modified within save_restore_insns. */
6364
f5963e61 6365#define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
7bea35e7
MM		 6366
6367static void
6368save_restore_insns (store_p, large_reg, large_offset, file)
f5963e61
JL		 6369 int store_p; /* true if this is prologue */
6370 rtx large_reg; /* register holding large offset constant or NULL */
6371 long large_offset; /* large constant offset value */
6372 FILE *file; /* file to write instructions instead of making RTL */
cee98a59 6373{
f5963e61
JL		 6374 long mask = current_frame_info.mask;
6375 long fmask = current_frame_info.fmask;
cee98a59 6376 int regno;
7bea35e7 6377 rtx base_reg_rtx;
f5963e61
JL		 6378 HOST_WIDE_INT base_offset;
6379 HOST_WIDE_INT gp_offset;
6380 HOST_WIDE_INT fp_offset;
6381 HOST_WIDE_INT end_offset;
141719a8 6382 rtx insn;
7bea35e7 6383
f5963e61 6384 if (frame_pointer_needed
1b15c5de 6385 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
7bea35e7 6386 abort ();
cee98a59
MM		 6387
6388 if (mask == 0 && fmask == 0)
6389 return;
6390
f5963e61
JL		 6391 /* Save registers starting from high to low. The debuggers prefer at least
6392 the return register be stored at func+4, and also it allows us not to
6393 need a nop in the epilog if at least one register is reloaded in
6394 addition to return address. */
cee98a59 6395
7bea35e7
MM		 6396 /* Save GP registers if needed. */
6397 if (mask)
cee98a59 6398 {
f5963e61
JL		 6399 /* Pick which pointer to use as a base register. For small frames, just
6400 use the stack pointer. Otherwise, use a temporary register. Save 2
6401 cycles if the save area is near the end of a large frame, by reusing
6402 the constant created in the prologue/epilogue to adjust the stack
6403 frame. */
cee98a59 6404
f5963e61
JL		 6405 gp_offset = current_frame_info.gp_sp_offset;
6406 end_offset
bfed8dac
JL		 6407 = gp_offset - (current_frame_info.gp_reg_size
6408 - GET_MODE_SIZE (gpr_mode));
7bea35e7
MM		 6409
6410 if (gp_offset < 0 || end_offset < 0)
400500c4
RK		 6411 internal_error
6412 ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
6413 (long) gp_offset, (long) end_offset);
7bea35e7 6414
2bcb2ab3
GK		 6415 /* If we see a large frame in mips16 mode, we save the registers
6416 before adjusting the stack pointer, and load them afterward. */
6417 else if (TARGET_MIPS16 && large_offset > 32767)
f5963e61 6418 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
2bcb2ab3 6419
7bea35e7 6420 else if (gp_offset < 32768)
f5963e61 6421 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
cee98a59 6422
f5963e61
JL		 6423 else if (large_reg != 0
6424 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6425 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
7bea35e7 6426 {
c5c76735 6427 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61
JL		 6428 base_offset = large_offset;
6429 if (file == 0)
147255d8 6430 {
1eeed24e 6431 if (Pmode == DImode)
f5963e61
JL		 6432 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6433 stack_pointer_rtx));
147255d8 6434 else
f5963e61
JL		 6435 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6436 stack_pointer_rtx));
4b7e467b
JW		 6437 if (store_p)
6438 RTX_FRAME_RELATED_P (insn) = 1;
147255d8 6439 }
7bea35e7 6440 else
147255d8 6441 fprintf (file, "\t%s\t%s,%s,%s\n",
1eeed24e 6442 Pmode == DImode ? "daddu" : "addu",
7bea35e7
MM		 6443 reg_names[MIPS_TEMP2_REGNUM],
6444 reg_names[REGNO (large_reg)],
6445 reg_names[STACK_POINTER_REGNUM]);
6446 }
cee98a59 6447
7bea35e7 6448 else
cee98a59 6449 {
c5c76735 6450 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61
JL		 6451 base_offset = gp_offset;
6452 if (file == 0)
cee98a59 6453 {
218c2cdb
JW		 6454 rtx gp_offset_rtx = GEN_INT (gp_offset);
6455
6456 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6457 bit, so make sure that we don't emit anything that can be
6458 split. */
6459 /* ??? There is no DImode ori immediate pattern, so we can only
6460 do this for 32 bit code. */
bd9f1972 6461 if (large_int (gp_offset_rtx, GET_MODE (gp_offset_rtx))
218c2cdb
JW		 6462 && GET_MODE (base_reg_rtx) == SImode)
6463 {
6464 insn = emit_move_insn (base_reg_rtx,
3a6ee9f4 6465 GEN_INT (gp_offset & BITMASK_UPPER16));
218c2cdb
JW		 6466 if (store_p)
6467 RTX_FRAME_RELATED_P (insn) = 1;
f5963e61
JL		 6468 insn
6469 = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
3a6ee9f4
MM		 6470 GEN_INT (gp_offset
6471 & BITMASK_LOWER16)));
218c2cdb
JW		 6472 if (store_p)
6473 RTX_FRAME_RELATED_P (insn) = 1;
6474 }
6475 else
6476 {
6477 insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
6478 if (store_p)
6479 RTX_FRAME_RELATED_P (insn) = 1;
6480 }
6481
1eeed24e 6482 if (Pmode == DImode)
f5963e61
JL		 6483 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6484 stack_pointer_rtx));
147255d8 6485 else
f5963e61
JL		 6486 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6487 stack_pointer_rtx));
4b7e467b
JW		 6488 if (store_p)
6489 RTX_FRAME_RELATED_P (insn) = 1;
cee98a59 6490 }
7bea35e7 6491 else
38831dfe
KG		 6492 {
6493 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
e51712db 6494 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
38831dfe
KG		 6495 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6496 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6497 Pmode == DImode ? "daddu" : "addu",
6498 reg_names[MIPS_TEMP2_REGNUM],
6499 reg_names[MIPS_TEMP2_REGNUM],
6500 reg_names[STACK_POINTER_REGNUM]);
6501 }
cee98a59 6502 }
0fb5ac6f 6503
2bcb2ab3
GK		 6504 /* When we restore the registers in MIPS16 mode, then if we are
6505 using a frame pointer, and this is not a large frame, the
6506 current stack pointer will be offset by
6507 current_function_outgoing_args_size. Doing it this way lets
6508 us avoid offsetting the frame pointer before copying it into
6509 the stack pointer; there is no instruction to set the stack
6510 pointer to the sum of a register and a constant. */
6511 if (TARGET_MIPS16
6512 && ! store_p
6513 && frame_pointer_needed
6514 && large_offset <= 32767)
6515 base_offset += current_function_outgoing_args_size;
6516
6517 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
f5963e61
JL		 6518 if (BITSET_P (mask, regno - GP_REG_FIRST))
6519 {
6520 if (file == 0)
6521 {
6522 rtx reg_rtx;
6523 rtx mem_rtx
bfed8dac 6524 = gen_rtx (MEM, gpr_mode,
f5963e61
JL		 6525 gen_rtx (PLUS, Pmode, base_reg_rtx,
6526 GEN_INT (gp_offset - base_offset)));
6527
6528 RTX_UNCHANGING_P (mem_rtx) = 1;
6529
6530 /* The mips16 does not have an instruction to load
6531 $31, so we load $7 instead, and work things out
6532 in the caller. */
6533 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
bfed8dac 6534 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
f5963e61
JL		 6535 /* The mips16 sometimes needs to save $18. */
6536 else if (TARGET_MIPS16
6537 && regno != GP_REG_FIRST + 31
6538 && ! M16_REG_P (regno))
6539 {
6540 if (! store_p)
bfed8dac 6541 reg_rtx = gen_rtx (REG, gpr_mode, 6);
f5963e61
JL		 6542 else
6543 {
bfed8dac 6544 reg_rtx = gen_rtx (REG, gpr_mode, 3);
f5963e61 6545 emit_move_insn (reg_rtx,
bfed8dac 6546 gen_rtx (REG, gpr_mode, regno));
f5963e61
JL		 6547 }
6548 }
6549 else
bfed8dac 6550 reg_rtx = gen_rtx (REG, gpr_mode, regno);
f5963e61
JL		 6551
6552 if (store_p)
6553 {
6554 insn = emit_move_insn (mem_rtx, reg_rtx);
6555 RTX_FRAME_RELATED_P (insn) = 1;
6556 }
a53f72db
GRK		 6557 else if (!TARGET_ABICALLS
6558 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
f5963e61
JL		 6559 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6560 {
6561 emit_move_insn (reg_rtx, mem_rtx);
6562 if (TARGET_MIPS16
6563 && regno != GP_REG_FIRST + 31
6564 && ! M16_REG_P (regno))
bfed8dac 6565 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
f5963e61
JL		 6566 reg_rtx);
6567 }
6568 }
6569 else
6570 {
a53f72db
GRK		 6571 if (store_p || !TARGET_ABICALLS
6572 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
f5963e61
JL		 6573 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6574 {
6575 int r = regno;
6576
6577 /* The mips16 does not have an instruction to
6578 load $31, so we load $7 instead, and work
6579 things out in the caller. */
6580 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
6581 r = GP_REG_FIRST + 7;
2bcb2ab3 6582 /* The mips16 sometimes needs to save $18. */
f5963e61
JL		 6583 if (TARGET_MIPS16
6584 && regno != GP_REG_FIRST + 31
6585 && ! M16_REG_P (regno))
6586 {
6587 if (! store_p)
6588 r = GP_REG_FIRST + 6;
6589 else
6590 {
6591 r = GP_REG_FIRST + 3;
6592 fprintf (file, "\tmove\t%s,%s\n",
6593 reg_names[r], reg_names[regno]);
6594 }
6595 }
38831dfe 6596 fprintf (file, "\t%s\t%s,",
f5963e61
JL		 6597 (TARGET_64BIT
6598 ? (store_p) ? "sd" : "ld"
6599 : (store_p) ? "sw" : "lw"),
38831dfe
KG		 6600 reg_names[r]);
6601 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6602 gp_offset - base_offset);
6603 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
f5963e61
JL		 6604 if (! store_p
6605 && TARGET_MIPS16
6606 && regno != GP_REG_FIRST + 31
6607 && ! M16_REG_P (regno))
6608 fprintf (file, "\tmove\t%s,%s\n",
6609 reg_names[regno], reg_names[r]);
6610 }
6611
6612 }
bfed8dac 6613 gp_offset -= GET_MODE_SIZE (gpr_mode);
f5963e61 6614 }
0fb5ac6f 6615 }
7bea35e7 6616 else
f5963e61 6617 base_reg_rtx = 0, base_offset = 0;
0fb5ac6f 6618
7bea35e7 6619 /* Save floating point registers if needed. */
0fb5ac6f
MM		 6620 if (fmask)
6621 {
46299de9 6622 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
147255d8 6623 int fp_size = fp_inc * UNITS_PER_FPREG;
0fb5ac6f 6624
7bea35e7 6625 /* Pick which pointer to use as a base register. */
f5963e61 6626 fp_offset = current_frame_info.fp_sp_offset;
147255d8 6627 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
7bea35e7
MM		 6628
6629 if (fp_offset < 0 || end_offset < 0)
400500c4
RK		 6630 internal_error
6631 ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
6632 (long) fp_offset, (long) end_offset);
7bea35e7
MM		 6633
6634 else if (fp_offset < 32768)
f5963e61 6635 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
7bea35e7 6636
f5963e61
JL		 6637 else if (base_reg_rtx != 0
6638 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6639 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6640 ; /* already set up for gp registers above */
7bea35e7 6641
f5963e61
JL		 6642 else if (large_reg != 0
6643 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6644 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
7bea35e7 6645 {
c5c76735 6646 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61
JL		 6647 base_offset = large_offset;
6648 if (file == 0)
147255d8 6649 {
1eeed24e 6650 if (Pmode == DImode)
f5963e61
JL		 6651 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6652 stack_pointer_rtx));
147255d8 6653 else
f5963e61
JL		 6654 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6655 stack_pointer_rtx));
4b7e467b
JW		 6656 if (store_p)
6657 RTX_FRAME_RELATED_P (insn) = 1;
147255d8 6658 }
f5963e61 6659
7bea35e7 6660 else
147255d8 6661 fprintf (file, "\t%s\t%s,%s,%s\n",
1eeed24e 6662 Pmode == DImode ? "daddu" : "addu",
7bea35e7
MM		 6663 reg_names[MIPS_TEMP2_REGNUM],
6664 reg_names[REGNO (large_reg)],
6665 reg_names[STACK_POINTER_REGNUM]);
6666 }
6667
6668 else
6669 {
c5c76735 6670 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
f5963e61
JL		 6671 base_offset = fp_offset;
6672 if (file == 0)
7bea35e7 6673 {
218c2cdb
JW		 6674 rtx fp_offset_rtx = GEN_INT (fp_offset);
6675
6676 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6677 bit, so make sure that we don't emit anything that can be
6678 split. */
6679 /* ??? There is no DImode ori immediate pattern, so we can only
6680 do this for 32 bit code. */
bd9f1972 6681 if (large_int (fp_offset_rtx, GET_MODE (fp_offset_rtx))
218c2cdb
JW		 6682 && GET_MODE (base_reg_rtx) == SImode)
6683 {
6684 insn = emit_move_insn (base_reg_rtx,
3a6ee9f4 6685 GEN_INT (fp_offset & BITMASK_UPPER16));
218c2cdb
JW		 6686 if (store_p)
6687 RTX_FRAME_RELATED_P (insn) = 1;
6688 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
3a6ee9f4
MM		 6689 GEN_INT (fp_offset
6690 & BITMASK_LOWER16)));
218c2cdb
JW		 6691 if (store_p)
6692 RTX_FRAME_RELATED_P (insn) = 1;
6693 }
6694 else
6695 {
6696 insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
6697 if (store_p)
6698 RTX_FRAME_RELATED_P (insn) = 1;
6699 }
6700
4b7e467b
JW		 6701 if (store_p)
6702 RTX_FRAME_RELATED_P (insn) = 1;
1eeed24e 6703 if (Pmode == DImode)
f5963e61
JL		 6704 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
6705 stack_pointer_rtx));
147255d8 6706 else
f5963e61
JL		 6707 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
6708 stack_pointer_rtx));
4b7e467b
JW		 6709 if (store_p)
6710 RTX_FRAME_RELATED_P (insn) = 1;
7bea35e7
MM		 6711 }
6712 else
38831dfe
KG		 6713 {
6714 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
e51712db 6715 reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
38831dfe
KG		 6716 fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
6717 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6718 Pmode == DImode ? "daddu" : "addu",
6719 reg_names[MIPS_TEMP2_REGNUM],
6720 reg_names[MIPS_TEMP2_REGNUM],
6721 reg_names[STACK_POINTER_REGNUM]);
6722 }
7bea35e7
MM		 6723 }
6724
d1d3a2df
JL		 6725 /* This loop must iterate over the same space as its companion in
6726 compute_frame_size. */
6727 for (regno = (FP_REG_LAST - fp_inc + 1);
6728 regno >= FP_REG_FIRST;
6729 regno -= fp_inc)
f5963e61
JL		 6730 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6731 {
6732 if (file == 0)
6733 {
6734 enum machine_mode sz
6735 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6736 rtx reg_rtx = gen_rtx (REG, sz, regno);
6737 rtx mem_rtx = gen_rtx (MEM, sz,
6738 gen_rtx (PLUS, Pmode, base_reg_rtx,
6739 GEN_INT (fp_offset
6740 - base_offset)));
6741 RTX_UNCHANGING_P (mem_rtx) = 1;
6742
6743 if (store_p)
6744 {
6745 insn = emit_move_insn (mem_rtx, reg_rtx);
6746 RTX_FRAME_RELATED_P (insn) = 1;
6747 }
6748 else
6749 emit_move_insn (reg_rtx, mem_rtx);
6750 }
6751 else
38831dfe
KG		 6752 {
6753 fprintf (file, "\t%s\t%s,",
6754 (TARGET_SINGLE_FLOAT
6755 ? (store_p ? "s.s" : "l.s")
6756 : (store_p ? "s.d" : "l.d")),
6757 reg_names[regno]);
6758 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6759 fp_offset - base_offset);
6760 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6761 }
f5963e61
JL		 6762
6763 fp_offset -= fp_size;
6764 }
0fb5ac6f
MM		 6765 }
6766}
cee98a59
MM		 6767\f
6768/* Set up the stack and frame (if desired) for the function. */
6769
6770void
6771function_prologue (file, size)
6772 FILE *file;
810c1b83 6773 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
cee98a59 6774{
6e92f4b6 6775#ifndef FUNCTION_NAME_ALREADY_DECLARED
bd9f1972 6776 const char *fnname;
6e92f4b6 6777#endif
7bea35e7 6778 long tsize = current_frame_info.total_size;
cee98a59
MM		 6779
6780 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
8a2d2f90 6781
8bd8e198 6782#ifdef SDB_DEBUGGING_INFO
af173031 6783 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8a2d2f90 6784 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8bd8e198 6785#endif
cee98a59 6786
2bcb2ab3
GK		 6787 /* In mips16 mode, we may need to generate a 32 bit to handle
6788 floating point arguments. The linker will arrange for any 32 bit
6789 functions to call this stub, which will then jump to the 16 bit
6790 function proper. */
6791 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6792 && current_function_args_info.fp_code != 0)
6793 build_mips16_function_stub (file);
6794
993cd990
JW		 6795 inside_function = 1;
6796
6797#ifndef FUNCTION_NAME_ALREADY_DECLARED
10389f52
RK		 6798 /* Get the function name the same way that toplev.c does before calling
6799 assemble_start_function. This is needed so that the name used here
6800 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6801 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6802
e9a25f70
JL		 6803 if (!flag_inhibit_size_directive)
6804 {
6805 fputs ("\t.ent\t", file);
6806 assemble_name (file, fnname);
6807 fputs ("\n", file);
6808 }
7bea35e7 6809
10389f52 6810 assemble_name (file, fnname);
cee98a59 6811 fputs (":\n", file);
993cd990 6812#endif
cee98a59 6813
e9a25f70
JL		 6814 if (!flag_inhibit_size_directive)
6815 {
a50f2a09 6816 /* .frame FRAMEREG, FRAMESIZE, RETREG */
f5963e61
JL		 6817 fprintf (file,
6818 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6819 (reg_names[(frame_pointer_needed)
6820 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
a50f2a09
AC		 6821 ((frame_pointer_needed && TARGET_MIPS16)
6822 ? (tsize - current_function_outgoing_args_size)
6823 : tsize),
6824 reg_names[31 + GP_REG_FIRST],
f5963e61
JL		 6825 current_frame_info.var_size,
6826 current_frame_info.num_gp,
6827 current_frame_info.num_fp,
6828 current_function_outgoing_args_size,
6829 current_frame_info.extra_size);
e9a25f70 6830
a50f2a09 6831 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
3afaa6e8 6832 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
e9a25f70 6833 current_frame_info.mask,
a50f2a09 6834 current_frame_info.gp_save_offset,
e9a25f70
JL		 6835 current_frame_info.fmask,
6836 current_frame_info.fp_save_offset);
a50f2a09
AC		 6837
6838 /* Require:
6839 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6840 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
e9a25f70 6841 }
ffa9d0b1 6842
2bcb2ab3
GK		 6843 if (mips_entry && ! mips_can_use_return_insn ())
6844 {
6845 int save16 = BITSET_P (current_frame_info.mask, 16);
6846 int save17 = BITSET_P (current_frame_info.mask, 17);
6847 int save31 = BITSET_P (current_frame_info.mask, 31);
6848 int savearg = 0;
6849 rtx insn;
6850
6851 /* Look through the initial insns to see if any of them store
6852 the function parameters into the incoming parameter storage
6853 area. If they do, we delete the insn, and save the register
6854 using the entry pseudo-instruction instead. We don't try to
6855 look past a label, jump, or call. */
6856 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6857 {
6858 rtx note, set, src, dest, base, offset;
6859 int hireg;
6860
6861 if (GET_CODE (insn) == CODE_LABEL
6862 || GET_CODE (insn) == JUMP_INSN
6863 || GET_CODE (insn) == CALL_INSN)
6864 break;
6865 if (GET_CODE (insn) != INSN)
6866 continue;
6867 set = PATTERN (insn);
6868 if (GET_CODE (set) != SET)
6869 continue;
6870
6871 /* An insn storing a function parameter will still have a
6872 REG_EQUIV note on it mentioning the argument pointer. */
6873 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6874 if (note == NULL_RTX)
6875 continue;
6876 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6877 continue;
6878
6879 src = SET_SRC (set);
6880 if (GET_CODE (src) != REG
6881 || REGNO (src) < GP_REG_FIRST + 4
6882 || REGNO (src) > GP_REG_FIRST + 7)
6883 continue;
6884
6885 dest = SET_DEST (set);
6886 if (GET_CODE (dest) != MEM)
6887 continue;
0da9afa6 6888 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
2bcb2ab3 6889 ;
95adab8e 6890 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
2bcb2ab3
GK		 6891 && REGNO (src) < GP_REG_FIRST + 7)
6892 ;
6893 else
6894 continue;
6895 offset = const0_rtx;
6896 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6897 if (GET_CODE (base) != REG
6898 || GET_CODE (offset) != CONST_INT)
6899 continue;
0da9afa6
NC		 6900 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
6901 && (unsigned HOST_WIDE_INT) INTVAL (offset)
6902 == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
2bcb2ab3 6903 ;
0da9afa6
NC		 6904 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
6905 && ((unsigned HOST_WIDE_INT) INTVAL (offset)
2bcb2ab3
GK		 6906 == (tsize
6907 + (REGNO (src) - 4) * UNITS_PER_WORD
6908 - current_function_outgoing_args_size)))
6909 ;
6910 else
6911 continue;
6912
6913 /* This insn stores a parameter onto the stack, in the same
6914 location where the entry pseudo-instruction will put it.
6915 Delete the insn, and arrange to tell the entry
6916 instruction to save the register. */
6917 PUT_CODE (insn, NOTE);
6918 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
6919 NOTE_SOURCE_FILE (insn) = 0;
6920
6921 hireg = (REGNO (src)
6922 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
6923 - 1);
6924 if (hireg > savearg)
6925 savearg = hireg;
6926 }
6927
6928 /* If this is a varargs function, we need to save all the
6929 registers onto the stack anyhow. */
6930 if (current_function_stdarg || current_function_varargs)
6931 savearg = GP_REG_FIRST + 7;
6932
6933 fprintf (file, "\tentry\t");
6934 if (savearg > 0)
6935 {
6936 if (savearg == GP_REG_FIRST + 4)
6937 fprintf (file, "%s", reg_names[savearg]);
6938 else
6939 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
6940 reg_names[savearg]);
6941 }
6942 if (save16 || save17)
6943 {
6944 if (savearg > 0)
6945 fprintf (file, ",");
6946 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
6947 if (save17)
6948 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
6949 }
6950 if (save31)
6951 {
6952 if (savearg > 0 || save16 || save17)
6953 fprintf (file, ",");
6954 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
6955 }
6956 fprintf (file, "\n");
6957 }
6958
a53f72db 6959 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
ffa9d0b1 6960 {
bd9f1972 6961 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
ffa9d0b1
JW		 6962
6963 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
6964 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
6965 if (tsize > 0)
6966 {
3afaa6e8 6967 fprintf (file, "\t%s\t%s,%s,%ld\n",
1eeed24e 6968 (Pmode == DImode ? "dsubu" : "subu"),
147255d8 6969 sp_str, sp_str, tsize);
3afaa6e8 6970 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
ffa9d0b1 6971 }
0021b564
JM		 6972
6973 if (dwarf2out_do_frame ())
6974 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
ffa9d0b1 6975 }
0fb5ac6f 6976}
0fb5ac6f
MM		 6977\f
6978/* Expand the prologue into a bunch of separate insns. */
6979
6980void
6981mips_expand_prologue ()
6982{
6983 int regno;
f5963e61
JL		 6984 HOST_WIDE_INT tsize;
6985 rtx tmp_rtx = 0;
4730fa4f 6986 int last_arg_is_vararg_marker = 0;
f5963e61
JL		 6987 tree fndecl = current_function_decl;
6988 tree fntype = TREE_TYPE (fndecl);
6989 tree fnargs = DECL_ARGUMENTS (fndecl);
3f1f8d8c
MM		 6990 rtx next_arg_reg;
6991 int i;
0fb5ac6f
MM		 6992 tree next_arg;
6993 tree cur_arg;
0fb5ac6f 6994 CUMULATIVE_ARGS args_so_far;
2bcb2ab3 6995 rtx reg_18_save = NULL_RTX;
9e5ac782
CP		 6996 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
6997 && (! mips_entry || mips_can_use_return_insn ());
0fb5ac6f 6998
518e5ce8
JW		 6999 /* If struct value address is treated as the first argument, make it so. */
7000 if (aggregate_value_p (DECL_RESULT (fndecl))
7001 && ! current_function_returns_pcc_struct
7002 && struct_value_incoming_rtx == 0)
7003 {
7004 tree type = build_pointer_type (fntype);
7005 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
f5963e61 7006
518e5ce8
JW		 7007 DECL_ARG_TYPE (function_result_decl) = type;
7008 TREE_CHAIN (function_result_decl) = fnargs;
7009 fnargs = function_result_decl;
7010 }
7011
4730fa4f
GRK		 7012 /* For arguments passed in registers, find the register number
7013 of the first argument in the variable part of the argument list,
7014 otherwise GP_ARG_LAST+1. Note also if the last argument is
7015 the varargs special argument, and treat it as part of the
0da9afa6 7016 variable arguments.
9e5ac782
CP		 7017
7018 This is only needed if store_args_on_stack is true. */
3f1f8d8c 7019
f5963e61 7020 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
3f1f8d8c
MM		 7021 regno = GP_ARG_FIRST;
7022
f5963e61 7023 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
cee98a59 7024 {
6f673359
JW		 7025 tree passed_type = DECL_ARG_TYPE (cur_arg);
7026 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7027 rtx entry_parm;
7028
e0c228da 7029 if (TREE_ADDRESSABLE (passed_type))
6f673359
JW		 7030 {
7031 passed_type = build_pointer_type (passed_type);
7032 passed_mode = Pmode;
7033 }
7034
7035 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
3f1f8d8c 7036
4730fa4f
GRK		 7037 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7038 next_arg = TREE_CHAIN (cur_arg);
7039
9e5ac782 7040 if (entry_parm && store_args_on_stack)
3f1f8d8c 7041 {
4730fa4f
GRK		 7042 if (next_arg == 0
7043 && DECL_NAME (cur_arg)
7044 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7045 "__builtin_va_alist"))
7046 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7047 "va_alist"))))
7048 {
7049 last_arg_is_vararg_marker = 1;
7050 break;
7051 }
3f1f8d8c 7052 else
4730fa4f
GRK		 7053 {
7054 int words;
9e5ac782
CP		 7055
7056 if (GET_CODE (entry_parm) != REG)
7057 abort ();
7058
4730fa4f
GRK		 7059 /* passed in a register, so will get homed automatically */
7060 if (GET_MODE (entry_parm) == BLKmode)
7061 words = (int_size_in_bytes (passed_type) + 3) / 4;
7062 else
7063 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
3f1f8d8c 7064
4730fa4f
GRK		 7065 regno = REGNO (entry_parm) + words - 1;
7066 }
3f1f8d8c
MM		 7067 }
7068 else
7069 {
7070 regno = GP_ARG_LAST+1;
7071 break;
7072 }
cee98a59
MM		 7073 }
7074
f5963e61
JL		 7075 /* In order to pass small structures by value in registers compatibly with
7076 the MIPS compiler, we need to shift the value into the high part of the
7077 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7078 adjustments to be made as the next_arg_reg variable, so we split up the
7079 insns, and emit them separately. */
cee98a59 7080
3f1f8d8c 7081 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
f5963e61 7082 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
3f1f8d8c
MM		 7083 {
7084 rtvec adjust = XVEC (next_arg_reg, 0);
7085 int num = GET_NUM_ELEM (adjust);
cee98a59 7086
3f1f8d8c 7087 for (i = 0; i < num; i++)
cee98a59 7088 {
71641c15
RH		 7089 rtx insn, pattern;
7090
7091 pattern = RTVEC_ELT (adjust, i);
3f1f8d8c
MM		 7092 if (GET_CODE (pattern) != SET
7093 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7094 abort_with_insn (pattern, "Insn is not a shift");
3f1f8d8c 7095 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
71641c15
RH		 7096
7097 insn = emit_insn (pattern);
7098
7099 /* Global life information isn't valid at this point, so we
7100 can't check whether these shifts are actually used. Mark
7101 them MAYBE_DEAD so that flow2 will remove them, and not
7102 complain about dead code in the prologue. */
7103 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7104 REG_NOTES (insn));
cee98a59 7105 }
3f1f8d8c 7106 }
cee98a59 7107
ffa9d0b1
JW		 7108 tsize = compute_frame_size (get_frame_size ());
7109
3f1f8d8c
MM		 7110 /* If this function is a varargs function, store any registers that
7111 would normally hold arguments ($4 - $7) on the stack. */
9e5ac782 7112 if (store_args_on_stack
33563487 7113 && ((TYPE_ARG_TYPES (fntype) != 0
f5963e61
JL		 7114 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7115 != void_type_node))
4730fa4f 7116 || last_arg_is_vararg_marker))
3f1f8d8c 7117 {
ffa9d0b1
JW		 7118 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7119 rtx ptr = stack_pointer_rtx;
7120
7121 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
ade6c319 7122 if (TARGET_ABICALLS)
ffa9d0b1
JW		 7123 offset += tsize;
7124
0fb5ac6f 7125 for (; regno <= GP_ARG_LAST; regno++)
cee98a59 7126 {
ffa9d0b1
JW		 7127 if (offset != 0)
7128 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
bfed8dac
JL		 7129 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7130 gen_rtx (REG, gpr_mode, regno));
7131
7132 offset += GET_MODE_SIZE (gpr_mode);
cee98a59
MM		 7133 }
7134 }
7135
2bcb2ab3
GK		 7136 /* If we are using the entry pseudo instruction, it will
7137 automatically subtract 32 from the stack pointer, so we don't
7138 need to. The entry pseudo instruction is emitted by
7139 function_prologue. */
7140 if (mips_entry && ! mips_can_use_return_insn ())
7141 {
7142 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7143 {
7144 rtx insn;
7145
7146 /* If we are using a frame pointer with a small stack frame,
7147 we need to initialize it here since it won't be done
7148 below. */
7149 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7150 {
7151 rtx incr = GEN_INT (current_function_outgoing_args_size);
1eeed24e 7152 if (Pmode == DImode)
2bcb2ab3
GK		 7153 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7154 stack_pointer_rtx,
7155 incr));
7156 else
7157 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7158 stack_pointer_rtx,
7159 incr));
7160 }
1eeed24e 7161 else if (Pmode == DImode)
f5963e61
JL		 7162 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7163 stack_pointer_rtx));
2bcb2ab3 7164 else
f5963e61
JL		 7165 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7166 stack_pointer_rtx));
2bcb2ab3
GK		 7167
7168 RTX_FRAME_RELATED_P (insn) = 1;
7169 }
7170
7171 /* We may need to save $18, if it is used to call a function
7172 which may return a floating point value. Set up a sequence
7173 of instructions to do so. Later on we emit them at the right
7174 moment. */
7175 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
7176 {
bfed8dac 7177 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
2bcb2ab3
GK		 7178 long gp_offset, base_offset;
7179
7180 gp_offset = current_frame_info.gp_sp_offset;
7181 if (BITSET_P (current_frame_info.mask, 16))
7182 gp_offset -= UNITS_PER_WORD;
7183 if (BITSET_P (current_frame_info.mask, 17))
7184 gp_offset -= UNITS_PER_WORD;
7185 if (BITSET_P (current_frame_info.mask, 31))
7186 gp_offset -= UNITS_PER_WORD;
7187 if (tsize > 32767)
7188 base_offset = tsize;
7189 else
7190 base_offset = 0;
7191 start_sequence ();
7192 emit_move_insn (reg_rtx,
bfed8dac
JL		 7193 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7194 emit_move_insn (gen_rtx (MEM, gpr_mode,
2bcb2ab3
GK		 7195 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7196 GEN_INT (gp_offset
7197 - base_offset))),
7198 reg_rtx);
7199 reg_18_save = gen_sequence ();
7200 end_sequence ();
7201 }
7202
7203 if (tsize > 32)
7204 tsize -= 32;
7205 else
7206 {
7207 tsize = 0;
7208 if (reg_18_save != NULL_RTX)
7209 emit_insn (reg_18_save);
7210 }
7211 }
7212
cee98a59
MM		 7213 if (tsize > 0)
7214 {
0fb5ac6f 7215 rtx tsize_rtx = GEN_INT (tsize);
cee98a59 7216
2bcb2ab3
GK		 7217 /* If we are doing svr4-abi, sp move is done by
7218 function_prologue. In mips16 mode with a large frame, we
7219 save the registers before adjusting the stack. */
a53f72db 7220 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
2bcb2ab3 7221 && (!TARGET_MIPS16 || tsize <= 32767))
0fb5ac6f 7222 {
a94dbf2c
JM		 7223 rtx insn;
7224
ffa9d0b1
JW		 7225 if (tsize > 32767)
7226 {
147255d8 7227 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
119f2738
JW		 7228
7229 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
7230 bit, so make sure that we don't emit anything that can be
7231 split. */
9d1cf1d9
JW		 7232 /* ??? There is no DImode ori immediate pattern, so we can only
7233 do this for 32 bit code. */
bd9f1972
KG		 7234 if (large_int (tsize_rtx, GET_MODE (tsize_rtx))
7235 && GET_MODE (tmp_rtx) == SImode)
119f2738
JW		 7236 {
7237 insn = emit_move_insn (tmp_rtx,
3a6ee9f4 7238 GEN_INT (tsize & BITMASK_UPPER16));
119f2738
JW		 7239 RTX_FRAME_RELATED_P (insn) = 1;
7240 insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
3a6ee9f4
MM		 7241 GEN_INT (tsize
7242 & BITMASK_LOWER16)));
119f2738
JW		 7243 RTX_FRAME_RELATED_P (insn) = 1;
7244 }
7245 else
7246 {
7247 insn = emit_move_insn (tmp_rtx, tsize_rtx);
7248 RTX_FRAME_RELATED_P (insn) = 1;
7249 }
7250
ffa9d0b1
JW		 7251 tsize_rtx = tmp_rtx;
7252 }
cee98a59 7253
1eeed24e 7254 if (Pmode == DImode)
a94dbf2c
JM		 7255 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7256 tsize_rtx));
147255d8 7257 else
a94dbf2c
JM		 7258 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7259 tsize_rtx));
7260
469ac993 7261 RTX_FRAME_RELATED_P (insn) = 1;
ffa9d0b1 7262 }
cee98a59 7263
2bcb2ab3 7264 if (! mips_entry)
f5963e61 7265 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
2bcb2ab3
GK		 7266 else if (reg_18_save != NULL_RTX)
7267 emit_insn (reg_18_save);
cee98a59 7268
a53f72db 7269 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
2bcb2ab3
GK		 7270 && TARGET_MIPS16
7271 && tsize > 32767)
147255d8 7272 {
2bcb2ab3 7273 rtx reg_rtx;
a94dbf2c 7274
2bcb2ab3
GK		 7275 if (!frame_pointer_needed)
7276 abort ();
7277
c3499f00 7278 reg_rtx = gen_rtx (REG, Pmode, 3);
2bcb2ab3
GK		 7279 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7280 emit_move_insn (reg_rtx, tsize_rtx);
1eeed24e 7281 if (Pmode == DImode)
2bcb2ab3
GK		 7282 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7283 hard_frame_pointer_rtx,
7284 reg_rtx));
7285 else
7286 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7287 hard_frame_pointer_rtx,
7288 reg_rtx));
7289 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7290 }
7291
7292 if (frame_pointer_needed)
7293 {
7294 rtx insn = 0;
7295
7296 /* On the mips16, we encourage the use of unextended
7297 instructions when using the frame pointer by pointing the
7298 frame pointer ahead of the argument space allocated on
7299 the stack. */
a53f72db 7300 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
2bcb2ab3
GK		 7301 && TARGET_MIPS16
7302 && tsize > 32767)
7303 {
7304 /* In this case, we have already copied the stack
7305 pointer into the frame pointer, above. We need only
7306 adjust for the outgoing argument size. */
7307 if (current_function_outgoing_args_size != 0)
7308 {
7309 rtx incr = GEN_INT (current_function_outgoing_args_size);
1eeed24e 7310 if (Pmode == DImode)
2bcb2ab3
GK		 7311 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7312 hard_frame_pointer_rtx,
7313 incr));
7314 else
7315 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7316 hard_frame_pointer_rtx,
7317 incr));
7318 }
7319 }
7320 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7321 {
7322 rtx incr = GEN_INT (current_function_outgoing_args_size);
1eeed24e 7323 if (Pmode == DImode)
2bcb2ab3
GK		 7324 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7325 stack_pointer_rtx,
7326 incr));
7327 else
7328 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7329 stack_pointer_rtx,
7330 incr));
7331 }
1eeed24e 7332 else if (Pmode == DImode)
f5963e61
JL		 7333 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7334 stack_pointer_rtx));
147255d8 7335 else
f5963e61
JL		 7336 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7337 stack_pointer_rtx));
a94dbf2c 7338
8fa4e1b4
JL		 7339 if (insn)
7340 RTX_FRAME_RELATED_P (insn) = 1;
147255d8 7341 }
33563487 7342
a53f72db 7343 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
e5e809f4 7344 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
c5c76735 7345 gen_rtx_REG (DImode, 25)));
cee98a59 7346 }
d8d5b1e1
MM		 7347
7348 /* If we are profiling, make sure no instructions are scheduled before
7349 the call to mcount. */
7350
7351 if (profile_flag || profile_block_flag)
7352 emit_insn (gen_blockage ());
cee98a59 7353}
cee98a59 7354\f
f5963e61
JL		 7355/* Do any necessary cleanup after a function to restore stack, frame,
7356 and regs. */
cee98a59 7357
3a6ee9f4 7358#define RA_MASK BITMASK_HIGH /* 1 << 31 */
4d889da9 7359#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
b5e9dd03 7360
cee98a59
MM		 7361void
7362function_epilogue (file, size)
38831dfe
KG		 7363 FILE *file ATTRIBUTE_UNUSED;
7364 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
cee98a59 7365{
bd9f1972 7366 const char *fnname;
cee98a59 7367
993cd990 7368#ifndef FUNCTION_NAME_ALREADY_DECLARED
10389f52
RK		 7369 /* Get the function name the same way that toplev.c does before calling
7370 assemble_start_function. This is needed so that the name used here
7371 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7372 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7373
e9a25f70
JL		 7374 if (!flag_inhibit_size_directive)
7375 {
7376 fputs ("\t.end\t", file);
7377 assemble_name (file, fnname);
7378 fputs ("\n", file);
7379 }
993cd990 7380#endif
cee98a59
MM		 7381
7382 if (TARGET_STATS)
7383 {
7384 int num_gp_regs = current_frame_info.gp_reg_size / 4;
7385 int num_fp_regs = current_frame_info.fp_reg_size / 8;
f5963e61 7386 int num_regs = num_gp_regs + num_fp_regs;
bd9f1972 7387 const char *name = fnname;
ab78d4a8
MM		 7388
7389 if (name[0] == '*')
7390 name++;
cee98a59
MM		 7391
7392 dslots_load_total += num_regs;
7393
cee98a59 7394 fprintf (stderr,
38831dfe 7395 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
f5963e61
JL		 7396 name, frame_pointer_needed ? 'y' : 'n',
7397 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
7398 current_function_calls_alloca ? 'y' : 'n',
7399 current_function_calls_setjmp ? 'y' : 'n',
7400 current_frame_info.total_size,
7401 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
cee98a59
MM		 7402 dslots_load_total, dslots_load_filled,
7403 dslots_jump_total, dslots_jump_filled,
7404 num_refs[0], num_refs[1], num_refs[2]);
ddd8ab48 7405
6f3c667f
MM		 7406 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7407 {
f5963e61
JL		 7408 fprintf (stderr,
7409 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
6f3c667f
MM		 7410 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7411 }
ddd8ab48 7412
6f3c667f
MM		 7413 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7414 {
f5963e61
JL		 7415 fprintf (stderr,
7416 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
6f3c667f
MM		 7417 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7418 }
ddd8ab48
MM		 7419
7420 fputc ('\n', stderr);
cee98a59
MM		 7421 }
7422
7423 /* Reset state info for each function. */
f5963e61
JL		 7424 inside_function = 0;
7425 ignore_line_number = 0;
7426 dslots_load_total = 0;
7427 dslots_jump_total = 0;
cee98a59
MM		 7428 dslots_load_filled = 0;
7429 dslots_jump_filled = 0;
f5963e61
JL		 7430 num_refs[0] = 0;
7431 num_refs[1] = 0;
7432 num_refs[2] = 0;
7433 mips_load_reg = 0;
7434 mips_load_reg2 = 0;
cee98a59
MM		 7435 current_frame_info = zero_frame_info;
7436
2bcb2ab3
GK		 7437 while (string_constants != NULL)
7438 {
7439 struct string_constant *next;
7440
7441 next = string_constants->next;
7442 free (string_constants);
7443 string_constants = next;
7444 }
7445
cee98a59
MM		 7446 /* Restore the output file if optimizing the GP (optimizing the GP causes
7447 the text to be diverted to a tempfile, so that data decls come before
7448 references to the data). */
7449
2bcb2ab3 7450 if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
cee98a59
MM		 7451 asm_out_file = asm_out_data_file;
7452}
0fb5ac6f
MM		 7453\f
7454/* Expand the epilogue into a bunch of separate insns. */
7455
7456void
7457mips_expand_epilogue ()
7458{
f5963e61 7459 HOST_WIDE_INT tsize = current_frame_info.total_size;
0fb5ac6f 7460 rtx tsize_rtx = GEN_INT (tsize);
7bea35e7 7461 rtx tmp_rtx = (rtx)0;
0fb5ac6f 7462
1f2d8f51
JL		 7463 if (mips_can_use_return_insn ())
7464 {
7465 emit_insn (gen_return ());
7466 return;
7467 }
7468
2bcb2ab3
GK		 7469 if (mips_entry && ! mips_can_use_return_insn ())
7470 tsize -= 32;
7471
7472 if (tsize > 32767 && ! TARGET_MIPS16)
0fb5ac6f 7473 {
c5c76735 7474 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
0fb5ac6f
MM		 7475 emit_move_insn (tmp_rtx, tsize_rtx);
7476 tsize_rtx = tmp_rtx;
7477 }
7478
7479 if (tsize > 0)
7480 {
2bcb2ab3
GK		 7481 long orig_tsize = tsize;
7482
0fb5ac6f 7483 if (frame_pointer_needed)
147255d8 7484 {
1f2d8f51 7485 emit_insn (gen_blockage ());
2bcb2ab3
GK		 7486
7487 /* On the mips16, the frame pointer is offset from the stack
7488 pointer by current_function_outgoing_args_size. We
7489 account for that by changing tsize. Note that this can
7490 actually make tsize negative. */
7491 if (TARGET_MIPS16)
7492 {
7493 tsize -= current_function_outgoing_args_size;
7494
7495 /* If we have a large frame, it's easier to add to $17
7496 than to $sp, since the mips16 has no instruction to
7497 add a register to $sp. */
7498 if (orig_tsize > 32767)
7499 {
c3499f00 7500 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
2bcb2ab3
GK		 7501
7502 emit_move_insn (g6_rtx, GEN_INT (tsize));
1eeed24e 7503 if (Pmode == DImode)
2bcb2ab3
GK		 7504 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7505 hard_frame_pointer_rtx,
7506 g6_rtx));
7507 else
7508 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7509 hard_frame_pointer_rtx,
7510 g6_rtx));
7511 tsize = 0;
7512 }
a4dee8a5
GK		 7513
7514 if (tsize && tsize != orig_tsize)
7515 tsize_rtx = GEN_INT (tsize);
2bcb2ab3
GK		 7516 }
7517
1eeed24e 7518 if (Pmode == DImode)
2bcb2ab3 7519 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
147255d8 7520 else
2bcb2ab3 7521 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
147255d8 7522 }
f5963e61 7523
ab00eb0a
JW		 7524 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7525 are going to restore it, then we must emit a blockage insn to
7526 prevent the scheduler from moving the restore out of the epilogue. */
a53f72db 7527 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
ab00eb0a
JW		 7528 && (current_frame_info.mask
7529 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7530 emit_insn (gen_blockage ());
0fb5ac6f 7531
f5963e61 7532 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
0fb5ac6f 7533
2bcb2ab3
GK		 7534 /* In mips16 mode with a large frame, we adjust the stack
7535 pointer before restoring the registers. In this case, we
7536 should always be using a frame pointer, so everything should
7537 have been handled above. */
7538 if (tsize > 32767 && TARGET_MIPS16)
7539 abort ();
7540
1f2d8f51 7541 emit_insn (gen_blockage ());
1eeed24e 7542 if (Pmode == DImode && tsize != 0)
147255d8
JW		 7543 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7544 tsize_rtx));
8fa4e1b4 7545 else if (tsize != 0)
147255d8
JW		 7546 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7547 tsize_rtx));
0fb5ac6f
MM		 7548 }
7549
2bcb2ab3
GK		 7550 /* The mips16 loads the return address into $7, not $31. */
7551 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7552 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7553 GP_REG_FIRST + 7)));
7554 else
7555 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7556 GP_REG_FIRST + 31)));
cee98a59 7557}
cee98a59 7558\f
f5963e61 7559/* Return nonzero if this function is known to have a null epilogue.
cee98a59
MM		 7560 This allows the optimizer to omit jumps to jumps if no stack
7561 was created. */
7562
7563int
1f2d8f51 7564mips_can_use_return_insn ()
cee98a59 7565{
f5963e61 7566 if (! reload_completed)
cee98a59
MM		 7567 return 0;
7568
1f2d8f51
JL		 7569 if (regs_ever_live[31] || profile_flag)
7570 return 0;
7571
2bcb2ab3
GK		 7572 /* In mips16 mode, a function which returns a floating point value
7573 needs to arrange to copy the return value into the floating point
7574 registers. */
7575 if (TARGET_MIPS16
7576 && mips16_hard_float
7577 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
7578 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
7579 == MODE_FLOAT)
7580 && (! TARGET_SINGLE_FLOAT
7581 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
7582 <= 4)))
7583 return 0;
7584
cee98a59
MM		 7585 if (current_frame_info.initialized)
7586 return current_frame_info.total_size == 0;
7587
f5963e61 7588 return compute_frame_size (get_frame_size ()) == 0;
cee98a59 7589}
9753d4e4 7590\f
d660677d
MM		 7591/* Returns non-zero if X contains a SYMBOL_REF. */
7592
7593static int
7594symbolic_expression_p (x)
7595 rtx x;
7596{
7597 if (GET_CODE (x) == SYMBOL_REF)
7598 return 1;
7599
7600 if (GET_CODE (x) == CONST)
7601 return symbolic_expression_p (XEXP (x, 0));
7602
7603 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7604 return symbolic_expression_p (XEXP (x, 0));
7605
7606 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7607 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7608 return (symbolic_expression_p (XEXP (x, 0))
7609 || symbolic_expression_p (XEXP (x, 1)));
7610
7611 return 0;
7612}
7613
9753d4e4
JW		 7614/* Choose the section to use for the constant rtx expression X that has
7615 mode MODE. */
7616
6e92f4b6 7617void
9753d4e4
JW		 7618mips_select_rtx_section (mode, x)
7619 enum machine_mode mode;
38831dfe 7620 rtx x ATTRIBUTE_UNUSED;
9753d4e4 7621{
2bcb2ab3
GK		 7622 if (TARGET_MIPS16)
7623 {
52ecdfda
JW		 7624 /* In mips16 mode, the constant table always goes in the same section
7625 as the function, so that constants can be loaded using PC relative
2bcb2ab3 7626 addressing. */
52ecdfda 7627 function_section (current_function_decl);
2bcb2ab3
GK		 7628 }
7629 else if (TARGET_EMBEDDED_DATA)
9753d4e4
JW		 7630 {
7631 /* For embedded applications, always put constants in read-only data,
7632 in order to reduce RAM usage. */
8bd8e198 7633 READONLY_DATA_SECTION ();
9753d4e4
JW		 7634 }
7635 else
7636 {
7637 /* For hosted applications, always put constants in small data if
7638 possible, as this gives the best performance. */
7639
0da9afa6 7640 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
9753d4e4 7641 && mips_section_threshold > 0)
8bd8e198 7642 SMALL_DATA_SECTION ();
d660677d
MM		 7643 else if (flag_pic && symbolic_expression_p (x))
7644 /* Any expression involving a SYMBOL_REF might need a run-time
7645 relocation. (The symbol might be defined in a shared
7646 library loaded at an unexpected base address.) So, we must
7647 put such expressions in the data segment (which is
7648 writable), rather than the text segment (which is
7649 read-only). */
7650 data_section ();
9753d4e4 7651 else
8bd8e198 7652 READONLY_DATA_SECTION ();
9753d4e4
JW		 7653 }
7654}
7655
7656/* Choose the section to use for DECL. RELOC is true if its value contains
5f680ab6
DD		 7657 any relocatable expression.
7658
7659 Some of the logic used here needs to be replicated in
7660 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7661 are done correctly. Specifically, at least all symbols assigned
7662 here to rom (.text and/or .rodata) must not be referenced via
7663 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7664
7665 If you need to make a change here, you probably should check
7666 ENCODE_SECTION_INFO to see if it needs a similar change. */
9753d4e4 7667
6e92f4b6 7668void
9753d4e4
JW		 7669mips_select_section (decl, reloc)
7670 tree decl;
7671 int reloc;
7672{
7673 int size = int_size_in_bytes (TREE_TYPE (decl));
7674
2bcb2ab3 7675 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
92544bdf
ILT		 7676 && TREE_CODE (decl) == STRING_CST
7677 && !flag_writable_strings)
f5963e61
JL		 7678 /* For embedded position independent code, put constant strings in the
7679 text section, because the data section is limited to 64K in size.
7680 For mips16 code, put strings in the text section so that a PC
7681 relative load instruction can be used to get their address. */
7682 text_section ();
92544bdf 7683 else if (TARGET_EMBEDDED_DATA)
9753d4e4
JW		 7684 {
7685 /* For embedded applications, always put an object in read-only data
7686 if possible, in order to reduce RAM usage. */
7687
1d306530
JW		 7688 if (((TREE_CODE (decl) == VAR_DECL
7689 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
9753d4e4
JW		 7690 && DECL_INITIAL (decl)
7691 && (DECL_INITIAL (decl) == error_mark_node
7692 || TREE_CONSTANT (DECL_INITIAL (decl))))
7693 /* Deal with calls from output_constant_def_contents. */
7694 || (TREE_CODE (decl) != VAR_DECL
7695 && (TREE_CODE (decl) != STRING_CST
7696 || !flag_writable_strings)))
7697 && ! (flag_pic && reloc))
8bd8e198 7698 READONLY_DATA_SECTION ();
9753d4e4 7699 else if (size > 0 && size <= mips_section_threshold)
8bd8e198 7700 SMALL_DATA_SECTION ();
9753d4e4
JW		 7701 else
7702 data_section ();
7703 }
7704 else
7705 {
7706 /* For hosted applications, always put an object in small data if
7707 possible, as this gives the best performance. */
7708
7709 if (size > 0 && size <= mips_section_threshold)
8bd8e198 7710 SMALL_DATA_SECTION ();
1d306530
JW		 7711 else if (((TREE_CODE (decl) == VAR_DECL
7712 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
9753d4e4
JW		 7713 && DECL_INITIAL (decl)
7714 && (DECL_INITIAL (decl) == error_mark_node
7715 || TREE_CONSTANT (DECL_INITIAL (decl))))
7716 /* Deal with calls from output_constant_def_contents. */
7717 || (TREE_CODE (decl) != VAR_DECL
7718 && (TREE_CODE (decl) != STRING_CST
7719 || !flag_writable_strings)))
7720 && ! (flag_pic && reloc))
8bd8e198 7721 READONLY_DATA_SECTION ();
9753d4e4
JW		 7722 else
7723 data_section ();
7724 }
7725}
33563487 7726\f
ade6c319 7727#ifdef MIPS_ABI_DEFAULT
f5963e61 7728
33563487
JW		 7729/* Support functions for the 64 bit ABI. */
7730
33563487
JW		 7731/* Return register to use for a function return value with VALTYPE for function
7732 FUNC. */
7733
7734rtx
7735mips_function_value (valtype, func)
7736 tree valtype;
38831dfe 7737 tree func ATTRIBUTE_UNUSED;
33563487
JW		 7738{
7739 int reg = GP_RETURN;
7740 enum machine_mode mode = TYPE_MODE (valtype);
7741 enum mode_class mclass = GET_MODE_CLASS (mode);
2bcb2ab3
GK		 7742 int unsignedp = TREE_UNSIGNED (valtype);
7743
7744 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7745 just as PROMOTE_MODE does. */
7746 mode = promote_mode (valtype, mode, &unsignedp, 1);
33563487 7747
a20b7b05 7748 /* ??? How should we return complex float? */
33563487 7749 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
efcedf42
ILT		 7750 {
7751 if (TARGET_SINGLE_FLOAT
7752 && (mclass == MODE_FLOAT
f5963e61 7753 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
efcedf42
ILT		 7754 reg = GP_RETURN;
7755 else
7756 reg = FP_RETURN;
7757 }
f5963e61 7758
293a36eb 7759 else if (TREE_CODE (valtype) == RECORD_TYPE
a53f72db
GRK		 7760 && mips_abi != ABI_32
7761 && mips_abi != ABI_O64
7762 && mips_abi != ABI_EABI)
33563487
JW		 7763 {
7764 /* A struct with only one or two floating point fields is returned in
7765 the floating point registers. */
320aba9c 7766 tree field, fields[2];
33563487
JW		 7767 int i;
7768
7769 for (i = 0, field = TYPE_FIELDS (valtype); field;
320aba9c 7770 field = TREE_CHAIN (field))
33563487 7771 {
320aba9c
JW		 7772 if (TREE_CODE (field) != FIELD_DECL)
7773 continue;
f5963e61 7774
33563487
JW		 7775 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7776 break;
320aba9c
JW		 7777
7778 fields[i++] = field;
33563487
JW		 7779 }
7780
1417e9bd 7781 /* Must check i, so that we reject structures with no elements. */
a20b7b05
JW		 7782 if (! field)
7783 {
7784 if (i == 1)
7785 {
320aba9c
JW		 7786 /* The structure has DImode, but we don't allow DImode values
7787 in FP registers, so we use a PARALLEL even though it isn't
7788 strictly necessary. */
7789 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7790
c5c76735
JL		 7791 return gen_rtx_PARALLEL
7792 (mode,
7793 gen_rtvec (1,
7794 gen_rtx_EXPR_LIST (VOIDmode,
7795 gen_rtx_REG (field_mode,
7796 FP_RETURN),
7797 const0_rtx)));
a20b7b05 7798 }
f5963e61 7799
a20b7b05
JW		 7800 else if (i == 2)
7801 {
7802 enum machine_mode first_mode
320aba9c 7803 = TYPE_MODE (TREE_TYPE (fields[0]));
a20b7b05 7804 enum machine_mode second_mode
320aba9c 7805 = TYPE_MODE (TREE_TYPE (fields[1]));
75131237
RK		 7806 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
7807 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
a20b7b05 7808
c5c76735
JL		 7809 return gen_rtx_PARALLEL
7810 (mode,
7811 gen_rtvec (2,
7812 gen_rtx_EXPR_LIST (VOIDmode,
7813 gen_rtx_REG (first_mode,
7814 FP_RETURN),
75131237 7815 GEN_INT (first_offset)),
c5c76735
JL		 7816 gen_rtx_EXPR_LIST (VOIDmode,
7817 gen_rtx_REG (second_mode,
7818 FP_RETURN + 2),
75131237 7819 GEN_INT (second_offset))));
a20b7b05
JW		 7820 }
7821 }
33563487
JW		 7822 }
7823
c5c76735 7824 return gen_rtx_REG (mode, reg);
33563487 7825}
48f45f57 7826#endif
293a36eb
ILT		 7827
7828/* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7829 nonzero when an argument must be passed by reference. */
7830
7831int
7832function_arg_pass_by_reference (cum, mode, type, named)
38831dfe 7833 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
293a36eb
ILT		 7834 enum machine_mode mode;
7835 tree type;
38831dfe 7836 int named ATTRIBUTE_UNUSED;
293a36eb
ILT		 7837{
7838 int size;
7839
c5c76735
JL		 7840 /* We must pass by reference if we would be both passing in registers
7841 and the stack. This is because any subsequent partial arg would be
7842 handled incorrectly in this case.
7843
7844 ??? This is really a kludge. We should either fix GCC so that such
7845 a situation causes an abort and then do something in the MIPS port
7846 to prevent it, or add code to function.c to properly handle the case. */
c9fc373c
JW		 7847 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
7848 here hopefully is not relevant to mips_va_arg. */
1e7a71c1
CP		 7849 if (cum && MUST_PASS_IN_STACK (mode, type))
7850 {
0da9afa6
NC		 7851 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
7852 get double copies of any offsets generated for small structs
7853 passed in registers. */
7854 CUMULATIVE_ARGS temp;
7855 temp = *cum;
7856 if (FUNCTION_ARG (temp, mode, type, named) != 0)
7857 return 1;
1e7a71c1
CP		 7858 }
7859
c5c76735 7860 /* Otherwise, we only do this if EABI is selected. */
293a36eb
ILT		 7861 if (mips_abi != ABI_EABI)
7862 return 0;
7863
7864 /* ??? How should SCmode be handled? */
7865 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7866 return 0;
7867
7868 size = int_size_in_bytes (type);
7869 return size == -1 || size > UNITS_PER_WORD;
7870}
46299de9 7871
225b8835
ILT		 7872/* This function returns the register class required for a secondary
7873 register when copying between one of the registers in CLASS, and X,
7874 using MODE. If IN_P is nonzero, the copy is going from X to the
7875 register, otherwise the register is the source. A return value of
7876 NO_REGS means that no secondary register is required. */
46299de9
ILT		 7877
7878enum reg_class
225b8835 7879mips_secondary_reload_class (class, mode, x, in_p)
46299de9
ILT		 7880 enum reg_class class;
7881 enum machine_mode mode;
7882 rtx x;
225b8835 7883 int in_p;
46299de9 7884{
2bcb2ab3 7885 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
225b8835 7886 int regno = -1;
2bcb2ab3 7887 int gp_reg_p;
46299de9 7888
2a0b0bf5
ILT		 7889 if (GET_CODE (x) == SIGN_EXTEND)
7890 {
7891 int off = 0;
7892
7893 x = XEXP (x, 0);
7894
7895 /* We may be called with reg_renumber NULL from regclass.
7896 ??? This is probably a bug. */
7897 if (reg_renumber)
7898 regno = true_regnum (x);
7899 else
7900 {
7901 while (GET_CODE (x) == SUBREG)
7902 {
ddef6bc7
JJ		 7903 off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
7904 GET_MODE (SUBREG_REG (x)),
7905 SUBREG_BYTE (x),
7906 GET_MODE (x));
2a0b0bf5
ILT		 7907 x = SUBREG_REG (x);
7908 }
f5963e61 7909
2a0b0bf5
ILT		 7910 if (GET_CODE (x) == REG)
7911 regno = REGNO (x) + off;
7912 }
7913 }
f5963e61 7914
2a0b0bf5 7915 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
225b8835
ILT		 7916 regno = true_regnum (x);
7917
2bcb2ab3
GK		 7918 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7919
225b8835
ILT		 7920 /* We always require a general register when copying anything to
7921 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7922 to a general register, or when copying from register 0. */
7923 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
f5963e61 7924 return ((! in_p
33d7a521 7925 && gp_reg_p
f5963e61 7926 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
33d7a521 7927 ? NO_REGS : gr_regs);
f5963e61
JL		 7928 else if (regno == HILO_REGNUM)
7929 return ((in_p
33d7a521 7930 && class == gr_regs
f5963e61 7931 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
33d7a521 7932 ? NO_REGS : gr_regs);
46299de9 7933
225b8835
ILT		 7934 /* Copying from HI or LO to anywhere other than a general register
7935 requires a general register. */
7936 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7937 {
2bcb2ab3
GK		 7938 if (TARGET_MIPS16 && in_p)
7939 {
7940 /* We can't really copy to HI or LO at all in mips16 mode. */
7941 return M16_REGS;
7942 }
33d7a521 7943 return gp_reg_p ? NO_REGS : gr_regs;
225b8835
ILT		 7944 }
7945 if (MD_REG_P (regno))
7946 {
2bcb2ab3
GK		 7947 if (TARGET_MIPS16 && ! in_p)
7948 {
7949 /* We can't really copy to HI or LO at all in mips16 mode. */
7950 return M16_REGS;
7951 }
33d7a521 7952 return class == gr_regs ? NO_REGS : gr_regs;
46299de9
ILT		 7953 }
7954
b8eb88d0
ILT		 7955 /* We can only copy a value to a condition code register from a
7956 floating point register, and even then we require a scratch
7957 floating point register. We can only copy a value out of a
7958 condition code register into a general register. */
7959 if (class == ST_REGS)
7960 {
7961 if (in_p)
7962 return FP_REGS;
f5963e61 7963 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
b8eb88d0
ILT		 7964 }
7965 if (ST_REG_P (regno))
7966 {
7967 if (! in_p)
7968 return FP_REGS;
f5963e61 7969 return class == GR_REGS ? NO_REGS : GR_REGS;
b8eb88d0
ILT		 7970 }
7971
2bcb2ab3
GK		 7972 /* In mips16 mode, going between memory and anything but M16_REGS
7973 requires an M16_REG. */
7974 if (TARGET_MIPS16)
7975 {
7976 if (class != M16_REGS && class != M16_NA_REGS)
7977 {
7978 if (gp_reg_p)
7979 return NO_REGS;
7980 return M16_REGS;
7981 }
7982 if (! gp_reg_p)
7983 {
bf4f78ee
JW		 7984 /* The stack pointer isn't a valid operand to an add instruction,
7985 so we need to load it into M16_REGS first. This can happen as
7986 a result of register elimination and form_sum converting
7987 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
7988 need an extra register if the dest is the same as the other
7989 register. In that case, we can't fix the problem by loading SP
7990 into the dest first. */
7991 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
7992 && GET_CODE (XEXP (x, 1)) == REG
7993 && (XEXP (x, 0) == stack_pointer_rtx
7994 || XEXP (x, 1) == stack_pointer_rtx))
7995 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
7996
2bcb2ab3
GK		 7997 if (class == M16_REGS || class == M16_NA_REGS)
7998 return NO_REGS;
7999 return M16_REGS;
8000 }
8001 }
8002
225b8835 8003 return NO_REGS;
46299de9 8004}
2bcb2ab3
GK		 8005\f
8006/* For each mips16 function which refers to GP relative symbols, we
8007 use a pseudo register, initialized at the start of the function, to
8008 hold the $gp value. */
8009
8010rtx
8011mips16_gp_pseudo_reg ()
8012{
8013 if (mips16_gp_pseudo_rtx == NULL_RTX)
8014 {
8015 rtx const_gp;
8016 rtx insn, scan;
8017
8018 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8019 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
8020
8021 /* We want to initialize this to a value which gcc will believe
8022 is constant. */
8023 const_gp = gen_rtx (CONST, Pmode,
8024 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8025
8026 start_sequence ();
8027 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
8028 insn = gen_sequence ();
8029 end_sequence ();
8030
8031 push_topmost_sequence ();
8032 /* We need to emit the initialization after the FUNCTION_BEG
8033 note, so that it will be integrated. */
8034 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8035 if (GET_CODE (scan) == NOTE
8036 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8037 break;
8038 if (scan == NULL_RTX)
8039 scan = get_insns ();
8040 insn = emit_insn_after (insn, scan);
8041 pop_topmost_sequence ();
8042 }
8043
8044 return mips16_gp_pseudo_rtx;
8045}
8046
8047/* Return an RTX which represents the signed 16 bit offset from the
8048 $gp register for the given symbol. This is only used on the
8049 mips16. */
8050
8051rtx
8052mips16_gp_offset (sym)
8053 rtx sym;
8054{
8055 tree gp;
8056
8057 if (GET_CODE (sym) != SYMBOL_REF
8058 || ! SYMBOL_REF_FLAG (sym))
8059 abort ();
8060
8061 /* We use a special identifier to represent the value of the gp
8062 register. */
8063 gp = get_identifier ("__mips16_gp_value");
8064
8065 return gen_rtx (CONST, Pmode,
8066 gen_rtx (MINUS, Pmode, sym,
8067 gen_rtx (SYMBOL_REF, Pmode,
8068 IDENTIFIER_POINTER (gp))));
8069}
8070
8071/* Return nonzero if the given RTX represents a signed 16 bit offset
8072 from the $gp register. */
8073
8074int
8075mips16_gp_offset_p (x)
8076 rtx x;
8077{
8078 if (GET_CODE (x) == CONST)
8079 x = XEXP (x, 0);
8080
8081 /* It's OK to add a small integer value to a gp offset. */
8082 if (GET_CODE (x) == PLUS)
8083 {
8084 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8085 && SMALL_INT (XEXP (x, 1)))
8086 return mips16_gp_offset_p (XEXP (x, 0));
8087 if (GET_CODE (XEXP (x, 0)) == CONST_INT
8088 && SMALL_INT (XEXP (x, 0)))
8089 return mips16_gp_offset_p (XEXP (x, 1));
8090 return 0;
8091 }
8092
8093 /* Make sure it is in the form SYM - __mips16_gp_value. */
8094 return (GET_CODE (x) == MINUS
8095 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8096 && SYMBOL_REF_FLAG (XEXP (x, 0))
8097 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8098 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8099}
8100
8101/* Output a GP offset. We don't want to print the subtraction of
8102 __mips16_gp_value; it is implicitly represented by the %gprel which
8103 should have been printed by the caller. */
8104
8105static void
8106mips16_output_gp_offset (file, x)
8107 FILE *file;
8108 rtx x;
8109{
8110 if (GET_CODE (x) == CONST)
8111 x = XEXP (x, 0);
8112
8113 if (GET_CODE (x) == PLUS)
8114 {
8115 mips16_output_gp_offset (file, XEXP (x, 0));
8116 fputs ("+", file);
8117 mips16_output_gp_offset (file, XEXP (x, 1));
8118 return;
8119 }
8120
8121 if (GET_CODE (x) == MINUS
8122 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8123 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8124 {
8125 mips16_output_gp_offset (file, XEXP (x, 0));
8126 return;
8127 }
8128
8129 output_addr_const (file, x);
8130}
8131
8132/* Return nonzero if a constant should not be output until after the
8133 function. This is true of most string constants, so that we can
8134 use a more efficient PC relative reference. However, a static
8135 inline function may never call assemble_function_end to write out
8136 the constant pool, so don't try to postpone the constant in that
8137 case.
8138
8139 ??? It's really a bug that a static inline function can put stuff
8140 in the constant pool even if the function itself is not output.
8141
8142 We record which string constants we've seen, so that we know which
8143 ones might use the more efficient reference. */
8144
8145int
8146mips16_constant_after_function_p (x)
8147 tree x;
8148{
8149 if (TREE_CODE (x) == STRING_CST
8150 && ! flag_writable_strings
8151 && current_function_decl != 0
8152 && ! DECL_DEFER_OUTPUT (current_function_decl)
8153 && ! (DECL_INLINE (current_function_decl)
8154 && ((! TREE_PUBLIC (current_function_decl)
8155 && ! TREE_ADDRESSABLE (current_function_decl)
8156 && ! flag_keep_inline_functions)
8157 || DECL_EXTERNAL (current_function_decl))))
8158 {
8159 struct string_constant *n;
8160
8161 n = (struct string_constant *) xmalloc (sizeof *n);
8162 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8163 n->next = string_constants;
8164 string_constants = n;
8165
8166 return 1;
8167 }
8168
8169 return 0;
8170}
8171
8172/* Validate a constant for the mips16. This rejects general symbolic
8173 addresses, which must be loaded from memory. If ADDR is nonzero,
8174 this should reject anything which is not a legal address. If
8175 ADDEND is nonzero, this is being added to something else. */
8176
8177int
8178mips16_constant (x, mode, addr, addend)
8179 rtx x;
8180 enum machine_mode mode;
8181 int addr;
8182 int addend;
8183{
8184 while (GET_CODE (x) == CONST)
8185 x = XEXP (x, 0);
8186
8187 switch (GET_CODE (x))
8188 {
8189 default:
8190 return 0;
8191
8192 case PLUS:
8193 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8194 && mips16_constant (XEXP (x, 1), mode, addr, 1));
8195
8196 case SYMBOL_REF:
8197 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8198 return 0;
8199 if (CONSTANT_POOL_ADDRESS_P (x))
8200 return 1;
8201
8202 /* If we aren't looking for a memory address, we can accept a GP
8203 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8204 knows how to handle this. We can always accept a string
8205 constant, which is the other case in which SYMBOL_REF_FLAG
8206 will be set. */
0da9afa6
NC		 8207 if (! addr
8208 && ! addend
8209 && SYMBOL_REF_FLAG (x)
8210 && mode == (enum machine_mode) Pmode)
2bcb2ab3
GK		 8211 return 1;
8212
8213 /* We can accept a string constant, which will have
8214 SYMBOL_REF_FLAG set but must be recognized by name to
8215 distinguish from a GP accessible symbol. The name of a
8216 string constant will have been generated by
8217 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8218 if (SYMBOL_REF_FLAG (x))
8219 {
bd9f1972 8220 const char *name = XSTR (x, 0);
2bcb2ab3
GK		 8221
8222 return (name[0] == '*'
8223 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8224 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8225 }
8226
8227 return 0;
8228
8229 case LABEL_REF:
8230 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8231 return 0;
8232 return 1;
8233
8234 case CONST_INT:
8235 if (addr && ! addend)
8236 return 0;
8237 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8238
8239 case REG:
8240 /* We need to treat $gp as a legitimate constant, because
8241 mips16_gp_pseudo_reg assumes that. */
8242 return REGNO (x) == GP_REG_FIRST + 28;
8243 }
8244}
8245
8246/* Write out code to move floating point arguments in or out of
8247 general registers. Output the instructions to FILE. FP_CODE is
8248 the code describing which arguments are present (see the comment at
8249 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8250 we are copying from the floating point registers. */
8251
8252static void
8253mips16_fp_args (file, fp_code, from_fp_p)
8254 FILE *file;
8255 int fp_code;
8256 int from_fp_p;
8257{
e2fe6aba 8258 const char *s;
2bcb2ab3
GK		 8259 int gparg, fparg;
8260 unsigned int f;
8261
a53f72db
GRK		 8262 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8263 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
2bcb2ab3
GK		 8264 abort ();
8265
8266 if (from_fp_p)
8267 s = "mfc1";
8268 else
8269 s = "mtc1";
8270 gparg = GP_ARG_FIRST;
8271 fparg = FP_ARG_FIRST;
8272 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8273 {
8274 if ((f & 3) == 1)
8275 {
8276 if ((fparg & 1) != 0)
8277 ++fparg;
8278 fprintf (file, "\t%s\t%s,%s\n", s,
8279 reg_names[gparg], reg_names[fparg]);
8280 }
8281 else if ((f & 3) == 2)
8282 {
8283 if (TARGET_64BIT)
8284 fprintf (file, "\td%s\t%s,%s\n", s,
8285 reg_names[gparg], reg_names[fparg]);
8286 else
8287 {
8288 if ((fparg & 1) != 0)
8289 ++fparg;
a3bc83cc
AC		 8290 if (TARGET_BIG_ENDIAN)
8291 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8292 reg_names[gparg], reg_names[fparg + 1], s,
8293 reg_names[gparg + 1], reg_names[fparg]);
8294 else
8295 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8296 reg_names[gparg], reg_names[fparg], s,
8297 reg_names[gparg + 1], reg_names[fparg + 1]);
2bcb2ab3
GK		 8298 ++gparg;
8299 ++fparg;
8300 }
8301 }
8302 else
8303 abort ();
8304
8305 ++gparg;
8306 ++fparg;
8307 }
8308}
8309
8310/* Build a mips16 function stub. This is used for functions which
8311 take aruments in the floating point registers. It is 32 bit code
8312 that moves the floating point args into the general registers, and
8313 then jumps to the 16 bit code. */
8314
8315static void
8316build_mips16_function_stub (file)
8317 FILE *file;
8318{
bd9f1972 8319 const char *fnname;
2bcb2ab3
GK		 8320 char *secname, *stubname;
8321 tree stubid, stubdecl;
8322 int need_comma;
8323 unsigned int f;
8324
8325 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8326 secname = (char *) alloca (strlen (fnname) + 20);
8327 sprintf (secname, ".mips16.fn.%s", fnname);
8328 stubname = (char *) alloca (strlen (fnname) + 20);
8329 sprintf (stubname, "__fn_stub_%s", fnname);
8330 stubid = get_identifier (stubname);
8331 stubdecl = build_decl (FUNCTION_DECL, stubid,
8332 build_function_type (void_type_node, NULL_TREE));
8333 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8334
8335 fprintf (file, "\t# Stub function for %s (", current_function_name);
8336 need_comma = 0;
8337 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8338 {
8339 fprintf (file, "%s%s",
8340 need_comma ? ", " : "",
8341 (f & 3) == 1 ? "float" : "double");
8342 need_comma = 1;
8343 }
8344 fprintf (file, ")\n");
8345
8346 fprintf (file, "\t.set\tnomips16\n");
8347 function_section (stubdecl);
8348 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8349
8350 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8351 within a .ent, and we can not emit another .ent. */
8352#ifndef FUNCTION_NAME_ALREADY_DECLARED
8353 fputs ("\t.ent\t", file);
8354 assemble_name (file, stubname);
8355 fputs ("\n", file);
8356#endif
8357
8358 assemble_name (file, stubname);
8359 fputs (":\n", file);
8360
8361 /* We don't want the assembler to insert any nops here. */
8362 fprintf (file, "\t.set\tnoreorder\n");
8363
8364 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8365
8366 fprintf (asm_out_file, "\t.set\tnoat\n");
8367 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8368 assemble_name (file, fnname);
8369 fprintf (file, "\n");
8370 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8371 fprintf (asm_out_file, "\t.set\tat\n");
8372
8373 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8374 with one of the mfc1 instructions, because the result is not
8375 available for one instruction, so if the very first instruction
8376 in the function refers to the register, it will see the wrong
8377 value. */
8378 fprintf (file, "\tnop\n");
8379
8380 fprintf (file, "\t.set\treorder\n");
8381
8382#ifndef FUNCTION_NAME_ALREADY_DECLARED
8383 fputs ("\t.end\t", file);
8384 assemble_name (file, stubname);
8385 fputs ("\n", file);
8386#endif
8387
8388 fprintf (file, "\t.set\tmips16\n");
8389
8390 function_section (current_function_decl);
8391}
8392
8393/* We keep a list of functions for which we have already built stubs
8394 in build_mips16_call_stub. */
8395
8396struct mips16_stub
8397{
8398 struct mips16_stub *next;
8399 char *name;
8400 int fpret;
8401};
8402
8403static struct mips16_stub *mips16_stubs;
8404
8405/* Build a call stub for a mips16 call. A stub is needed if we are
8406 passing any floating point values which should go into the floating
8407 point registers. If we are, and the call turns out to be to a 32
8408 bit function, the stub will be used to move the values into the
8409 floating point registers before calling the 32 bit function. The
8410 linker will magically adjust the function call to either the 16 bit
8411 function or the 32 bit stub, depending upon where the function call
8412 is actually defined.
8413
8414 Similarly, we need a stub if the return value might come back in a
8415 floating point register.
8416
8417 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8418 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8419 is the code built by function_arg. This function returns a nonzero
8420 value if it builds the call instruction itself. */
8421
8422int
8423build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8424 rtx retval;
8425 rtx fnmem;
8426 rtx arg_size;
8427 int fp_code;
8428{
8429 int fpret;
8430 rtx fn;
bd9f1972
KG		 8431 const char *fnname;
8432 char *secname, *stubname;
2bcb2ab3
GK		 8433 struct mips16_stub *l;
8434 tree stubid, stubdecl;
8435 int need_comma;
8436 unsigned int f;
8437
8438 /* We don't need to do anything if we aren't in mips16 mode, or if
8439 we were invoked with the -msoft-float option. */
8440 if (! TARGET_MIPS16 || ! mips16_hard_float)
8441 return 0;
8442
8443 /* Figure out whether the value might come back in a floating point
8444 register. */
8445 fpret = (retval != 0
8446 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8447 && (! TARGET_SINGLE_FLOAT
8448 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
8449
8450 /* We don't need to do anything if there were no floating point
8451 arguments and the value will not be returned in a floating point
8452 register. */
8453 if (fp_code == 0 && ! fpret)
8454 return 0;
8455
8456 if (GET_CODE (fnmem) != MEM)
8457 abort ();
8458 fn = XEXP (fnmem, 0);
8459
8460 /* We don't need to do anything if this is a call to a special
8461 mips16 support function. */
8462 if (GET_CODE (fn) == SYMBOL_REF
8463 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8464 return 0;
8465
a53f72db 8466 /* This code will only work for o32 and o64 abis. The other ABI's
2bcb2ab3 8467 require more sophisticated support. */
a53f72db 8468 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
2bcb2ab3
GK		 8469 abort ();
8470
8471 /* We can only handle SFmode and DFmode floating point return
8472 values. */
8473 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8474 abort ();
8475
8476 /* If we're calling via a function pointer, then we must always call
8477 via a stub. There are magic stubs provided in libgcc.a for each
8478 of the required cases. Each of them expects the function address
8479 to arrive in register $2. */
8480
8481 if (GET_CODE (fn) != SYMBOL_REF)
8482 {
8483 char buf[30];
8484 tree id;
8485 rtx stub_fn, stub_mem, insn;
8486
8487 /* ??? If this code is modified to support other ABI's, we need
8488 to handle PARALLEL return values here. */
8489
8490 sprintf (buf, "__mips16_call_stub_%s%d",
8491 (fpret
8492 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8493 : ""),
8494 fp_code);
8495 id = get_identifier (buf);
8496 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8497 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8498
8499 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8500
8501 if (retval == NULL_RTX)
8502 insn = gen_call_internal0 (stub_mem, arg_size,
8503 gen_rtx (REG, SImode,
8504 GP_REG_FIRST + 31));
8505 else
8506 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8507 gen_rtx (REG, SImode,
8508 GP_REG_FIRST + 31));
8509 insn = emit_call_insn (insn);
8510
8511 /* Put the register usage information on the CALL. */
8512 if (GET_CODE (insn) != CALL_INSN)
8513 abort ();
8514 CALL_INSN_FUNCTION_USAGE (insn) =
8515 gen_rtx (EXPR_LIST, VOIDmode,
8516 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8517 CALL_INSN_FUNCTION_USAGE (insn));
8518
8519 /* If we are handling a floating point return value, we need to
8520 save $18 in the function prologue. Putting a note on the
8521 call will mean that regs_ever_live[$18] will be true if the
8522 call is not eliminated, and we can check that in the prologue
8523 code. */
8524 if (fpret)
8525 CALL_INSN_FUNCTION_USAGE (insn) =
8526 gen_rtx (EXPR_LIST, VOIDmode,
8527 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8528 CALL_INSN_FUNCTION_USAGE (insn));
8529
8530 /* Return 1 to tell the caller that we've generated the call
8531 insn. */
8532 return 1;
8533 }
8534
8535 /* We know the function we are going to call. If we have already
8536 built a stub, we don't need to do anything further. */
8537
8538 fnname = XSTR (fn, 0);
8539 for (l = mips16_stubs; l != NULL; l = l->next)
8540 if (strcmp (l->name, fnname) == 0)
8541 break;
8542
8543 if (l == NULL)
8544 {
8545 /* Build a special purpose stub. When the linker sees a
8546 function call in mips16 code, it will check where the target
8547 is defined. If the target is a 32 bit call, the linker will
8548 search for the section defined here. It can tell which
8549 symbol this section is associated with by looking at the
8550 relocation information (the name is unreliable, since this
8551 might be a static function). If such a section is found, the
8552 linker will redirect the call to the start of the magic
8553 section.
8554
8555 If the function does not return a floating point value, the
8556 special stub section is named
8557 .mips16.call.FNNAME
8558
8559 If the function does return a floating point value, the stub
8560 section is named
8561 .mips16.call.fp.FNNAME
8562 */
8563
8564 secname = (char *) alloca (strlen (fnname) + 40);
8565 sprintf (secname, ".mips16.call.%s%s",
8566 fpret ? "fp." : "",
8567 fnname);
8568 stubname = (char *) alloca (strlen (fnname) + 20);
8569 sprintf (stubname, "__call_stub_%s%s",
8570 fpret ? "fp_" : "",
8571 fnname);
8572 stubid = get_identifier (stubname);
8573 stubdecl = build_decl (FUNCTION_DECL, stubid,
8574 build_function_type (void_type_node, NULL_TREE));
8575 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8576
8577 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8578 (fpret
8579 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8580 : ""),
8581 fnname);
8582 need_comma = 0;
8583 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8584 {
8585 fprintf (asm_out_file, "%s%s",
8586 need_comma ? ", " : "",
8587 (f & 3) == 1 ? "float" : "double");
8588 need_comma = 1;
8589 }
8590 fprintf (asm_out_file, ")\n");
8591
8592 fprintf (asm_out_file, "\t.set\tnomips16\n");
8593 assemble_start_function (stubdecl, stubname);
8594
8595#ifndef FUNCTION_NAME_ALREADY_DECLARED
8596 fputs ("\t.ent\t", asm_out_file);
8597 assemble_name (asm_out_file, stubname);
8598 fputs ("\n", asm_out_file);
8599
8600 assemble_name (asm_out_file, stubname);
8601 fputs (":\n", asm_out_file);
8602#endif
8603
8604 /* We build the stub code by hand. That's the only way we can
8605 do it, since we can't generate 32 bit code during a 16 bit
8606 compilation. */
8607
8608 /* We don't want the assembler to insert any nops here. */
8609 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8610
8611 mips16_fp_args (asm_out_file, fp_code, 0);
8612
8613 if (! fpret)
8614 {
8615 fprintf (asm_out_file, "\t.set\tnoat\n");
8616 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8617 fnname);
8618 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8619 fprintf (asm_out_file, "\t.set\tat\n");
8620 /* Unfortunately, we can't fill the jump delay slot. We
8621 can't fill with one of the mtc1 instructions, because the
8622 result is not available for one instruction, so if the
8623 very first instruction in the function refers to the
8624 register, it will see the wrong value. */
8625 fprintf (asm_out_file, "\tnop\n");
8626 }
8627 else
8628 {
8629 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8630 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8631 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8632 /* As above, we can't fill the delay slot. */
8633 fprintf (asm_out_file, "\tnop\n");
8634 if (GET_MODE (retval) == SFmode)
8635 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8636 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8637 else
8638 {
a3bc83cc
AC		 8639 if (TARGET_BIG_ENDIAN)
8640 {
8641 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8642 reg_names[GP_REG_FIRST + 2],
8643 reg_names[FP_REG_FIRST + 1]);
8644 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8645 reg_names[GP_REG_FIRST + 3],
8646 reg_names[FP_REG_FIRST + 0]);
8647 }
8648 else
8649 {
8650 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8651 reg_names[GP_REG_FIRST + 2],
8652 reg_names[FP_REG_FIRST + 0]);
8653 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8654 reg_names[GP_REG_FIRST + 3],
8655 reg_names[FP_REG_FIRST + 1]);
8656 }
2bcb2ab3
GK		 8657 }
8658 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8659 /* As above, we can't fill the delay slot. */
8660 fprintf (asm_out_file, "\tnop\n");
8661 }
8662
8663 fprintf (asm_out_file, "\t.set\treorder\n");
8664
8665#ifdef ASM_DECLARE_FUNCTION_SIZE
8666 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8667#endif
8668
8669#ifndef FUNCTION_NAME_ALREADY_DECLARED
8670 fputs ("\t.end\t", asm_out_file);
8671 assemble_name (asm_out_file, stubname);
8672 fputs ("\n", asm_out_file);
8673#endif
8674
8675 fprintf (asm_out_file, "\t.set\tmips16\n");
8676
8677 /* Record this stub. */
8678 l = (struct mips16_stub *) xmalloc (sizeof *l);
ad85216e 8679 l->name = xstrdup (fnname);
2bcb2ab3
GK		 8680 l->fpret = fpret;
8681 l->next = mips16_stubs;
8682 mips16_stubs = l;
8683 }
8684
8685 /* If we expect a floating point return value, but we've built a
8686 stub which does not expect one, then we're in trouble. We can't
8687 use the existing stub, because it won't handle the floating point
8688 value. We can't build a new stub, because the linker won't know
8689 which stub to use for the various calls in this object file.
8690 Fortunately, this case is illegal, since it means that a function
8691 was declared in two different ways in a single compilation. */
8692 if (fpret && ! l->fpret)
8693 error ("can not handle inconsistent calls to `%s'", fnname);
8694
8695 /* If we are calling a stub which handles a floating point return
8696 value, we need to arrange to save $18 in the prologue. We do
8697 this by marking the function call as using the register. The
8698 prologue will later see that it is used, and emit code to save
8699 it. */
8700
8701 if (l->fpret)
8702 {
8703 rtx insn;
8704
8705 if (retval == NULL_RTX)
8706 insn = gen_call_internal0 (fnmem, arg_size,
8707 gen_rtx (REG, SImode,
8708 GP_REG_FIRST + 31));
8709 else
8710 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8711 gen_rtx (REG, SImode,
8712 GP_REG_FIRST + 31));
8713 insn = emit_call_insn (insn);
8714
8715 if (GET_CODE (insn) != CALL_INSN)
8716 abort ();
8717
8718 CALL_INSN_FUNCTION_USAGE (insn) =
8719 gen_rtx (EXPR_LIST, VOIDmode,
8720 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8721 CALL_INSN_FUNCTION_USAGE (insn));
8722
8723 /* Return 1 to tell the caller that we've generated the call
8724 insn. */
8725 return 1;
8726 }
8727
8728 /* Return 0 to let the caller generate the call insn. */
8729 return 0;
8730}
8731
8732/* This function looks through the code for a function, and tries to
8733 optimize the usage of the $gp register. We arrange to copy $gp
8734 into a pseudo-register, and then let gcc's normal reload handling
8735 deal with the pseudo-register. Unfortunately, if reload choose to
8736 put the pseudo-register into a call-clobbered register, it will
8737 emit saves and restores for that register around any function
8738 calls. We don't need the saves, and it's faster to copy $gp than
8739 to do an actual restore. ??? This still means that we waste a
8740 stack slot.
8741
8742 This is an optimization, and the code which gcc has actually
8743 generated is correct, so we do not need to catch all cases. */
8744
8745static void
8746mips16_optimize_gp (first)
8747 rtx first;
8748{
8749 rtx gpcopy, slot, insn;
8750
8751 /* Look through the instructions. Set GPCOPY to the register which
8752 holds a copy of $gp. Set SLOT to the stack slot where it is
8753 saved. If we find an instruction which sets GPCOPY to anything
8754 other than $gp or SLOT, then we can't use it. If we find an
8755 instruction which sets SLOT to anything other than GPCOPY, we
8756 can't use it. */
8757
8758 gpcopy = NULL_RTX;
8759 slot = NULL_RTX;
8760 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8761 {
8762 rtx set;
8763
2c3c49de 8764 if (! INSN_P (insn))
2bcb2ab3
GK		 8765 continue;
8766
8767 set = PATTERN (insn);
8768
8769 /* We know that all references to memory will be inside a SET,
8770 because there is no other way to access memory on the mips16.
8771 We don't have to worry about a PARALLEL here, because the
8772 mips.md file will never generate them for memory references. */
8773 if (GET_CODE (set) != SET)
8774 continue;
8775
8776 if (gpcopy == NULL_RTX
8777 && GET_CODE (SET_SRC (set)) == CONST
8778 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8779 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8780 && GET_CODE (SET_DEST (set)) == REG
0da9afa6 8781 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
2bcb2ab3
GK		 8782 gpcopy = SET_DEST (set);
8783 else if (slot == NULL_RTX
8784 && gpcopy != NULL_RTX
8785 && GET_CODE (SET_DEST (set)) == MEM
8786 && GET_CODE (SET_SRC (set)) == REG
8787 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
0da9afa6 8788 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
2bcb2ab3
GK		 8789 {
8790 rtx base, offset;
8791
8792 offset = const0_rtx;
8793 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8794 if (GET_CODE (base) == REG
8795 && (REGNO (base) == STACK_POINTER_REGNUM
8796 || REGNO (base) == FRAME_POINTER_REGNUM))
8797 slot = SET_DEST (set);
8798 }
8799 else if (gpcopy != NULL_RTX
8800 && (GET_CODE (SET_DEST (set)) == REG
8801 || GET_CODE (SET_DEST (set)) == SUBREG)
8802 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8803 && (GET_CODE (SET_DEST (set)) != REG
8804 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
0da9afa6 8805 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
2bcb2ab3
GK		 8806 || ((GET_CODE (SET_SRC (set)) != CONST
8807 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
8808 || (REGNO (XEXP (SET_SRC (set), 0))
8809 != GP_REG_FIRST + 28))
8810 && ! rtx_equal_p (SET_SRC (set), slot))))
8811 break;
8812 else if (slot != NULL_RTX
8813 && GET_CODE (SET_DEST (set)) == MEM
8814 && rtx_equal_p (SET_DEST (set), slot)
8815 && (GET_CODE (SET_SRC (set)) != REG
8816 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8817 break;
8818 }
8819
8820 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8821 different optimization. Any time we find a copy of $28 into a
8822 register, followed by an add of a symbol_ref to that register, we
8823 convert it to load the value from the constant table instead.
8824 The copy and add will take six bytes, just as the load and
8825 constant table entry will take six bytes. However, it is
8826 possible that the constant table entry will be shared.
8827
8828 This could be a peephole optimization, but I don't know if the
8829 peephole code can call force_const_mem.
8830
8831 Using the same register for the copy of $28 and the add of the
8832 symbol_ref is actually pretty likely, since the add instruction
8833 requires the destination and the first addend to be the same
8834 register. */
8835
8836 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8837 {
8838 rtx next;
8839
8840 /* This optimization is only reasonable if the constant table
8841 entries are only 4 bytes. */
8842 if (Pmode != SImode)
8843 return;
8844
8845 for (insn = first; insn != NULL_RTX; insn = next)
8846 {
8847 rtx set1, set2;
8848
8849 next = insn;
8850 do
8851 {
8852 next = NEXT_INSN (next);
8853 }
8854 while (next != NULL_RTX
8855 && (GET_CODE (next) == NOTE
8856 || (GET_CODE (next) == INSN
8857 && (GET_CODE (PATTERN (next)) == USE
8858 || GET_CODE (PATTERN (next)) == CLOBBER))));
8859
8860 if (next == NULL_RTX)
8861 break;
8862
2c3c49de 8863 if (! INSN_P (insn))
2bcb2ab3
GK		 8864 continue;
8865
2c3c49de 8866 if (! INSN_P (next))
2bcb2ab3
GK		 8867 continue;
8868
8869 set1 = PATTERN (insn);
8870 if (GET_CODE (set1) != SET)
8871 continue;
8872 set2 = PATTERN (next);
8873 if (GET_CODE (set2) != SET)
8874 continue;
8875
8876 if (GET_CODE (SET_DEST (set1)) == REG
8877 && GET_CODE (SET_SRC (set1)) == CONST
8878 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8879 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8880 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8881 && GET_CODE (SET_SRC (set2)) == PLUS
8882 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8883 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8884 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8885 {
8886 rtx sym;
8887
8888 /* We've found a case we can change to load from the
8889 constant table. */
8890
8891 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8892 if (GET_CODE (sym) != SYMBOL_REF)
8893 abort ();
8894 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8895 force_const_mem (Pmode, sym)),
8896 next);
8897
8898 PUT_CODE (insn, NOTE);
8899 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8900 NOTE_SOURCE_FILE (insn) = 0;
8901
8902 PUT_CODE (next, NOTE);
8903 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8904 NOTE_SOURCE_FILE (next) = 0;
8905 }
8906 }
8907
8908 return;
8909 }
8910
8911 /* We can safely remove all assignments to SLOT from GPCOPY, and
8912 replace all assignments from SLOT to GPCOPY with assignments from
8913 $28. */
8914
8915 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8916 {
8917 rtx set;
8918
2c3c49de 8919 if (! INSN_P (insn))
2bcb2ab3
GK		 8920 continue;
8921
8922 set = PATTERN (insn);
8923 if (GET_CODE (set) != SET
0da9afa6 8924 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
2bcb2ab3
GK		 8925 continue;
8926
8927 if (GET_CODE (SET_DEST (set)) == MEM
8928 && rtx_equal_p (SET_DEST (set), slot)
8929 && GET_CODE (SET_SRC (set)) == REG
8930 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8931 {
8932 PUT_CODE (insn, NOTE);
8933 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8934 NOTE_SOURCE_FILE (insn) = 0;
8935 }
8936 else if (GET_CODE (SET_DEST (set)) == REG
8937 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
8938 && GET_CODE (SET_SRC (set)) == MEM
8939 && rtx_equal_p (SET_SRC (set), slot))
8940 {
8941 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
8942 gen_rtx (CONST, Pmode,
8943 gen_rtx (REG, Pmode,
8944 GP_REG_FIRST + 28))),
8945 insn);
8946 PUT_CODE (insn, NOTE);
8947 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8948 NOTE_SOURCE_FILE (insn) = 0;
8949 }
8950 }
8951}
8952
8953/* We keep a list of constants we which we have to add to internal
8954 constant tables in the middle of large functions. */
8955
8956struct constant
8957{
8958 struct constant *next;
8959 rtx value;
8960 rtx label;
8961 enum machine_mode mode;
8962};
8963
8964/* Add a constant to the list in *PCONSTANTS. */
8965
8966static rtx
8967add_constant (pconstants, val, mode)
8968 struct constant **pconstants;
8969 rtx val;
8970 enum machine_mode mode;
8971{
8972 struct constant *c;
8973
8974 for (c = *pconstants; c != NULL; c = c->next)
8975 if (mode == c->mode && rtx_equal_p (val, c->value))
8976 return c->label;
8977
8978 c = (struct constant *) xmalloc (sizeof *c);
8979 c->value = val;
8980 c->mode = mode;
8981 c->label = gen_label_rtx ();
8982 c->next = *pconstants;
8983 *pconstants = c;
8984 return c->label;
8985}
8986
8987/* Dump out the constants in CONSTANTS after INSN. */
8988
8989static void
8990dump_constants (constants, insn)
8991 struct constant *constants;
8992 rtx insn;
8993{
8994 struct constant *c;
8995 int align;
8996
8997 c = constants;
8998 align = 0;
8999 while (c != NULL)
9000 {
9001 rtx r;
9002 struct constant *next;
9003
9004 switch (GET_MODE_SIZE (c->mode))
9005 {
9006 case 1:
9007 align = 0;
9008 break;
9009 case 2:
9010 if (align < 1)
9011 insn = emit_insn_after (gen_align_2 (), insn);
9012 align = 1;
9013 break;
9014 case 4:
9015 if (align < 2)
9016 insn = emit_insn_after (gen_align_4 (), insn);
9017 align = 2;
9018 break;
9019 default:
9020 if (align < 3)
9021 insn = emit_insn_after (gen_align_8 (), insn);
9022 align = 3;
9023 break;
9024 }
9025
9026 insn = emit_label_after (c->label, insn);
9027
9028 switch (c->mode)
9029 {
9030 case QImode:
9031 r = gen_consttable_qi (c->value);
9032 break;
9033 case HImode:
9034 r = gen_consttable_hi (c->value);
9035 break;
9036 case SImode:
9037 r = gen_consttable_si (c->value);
9038 break;
9039 case SFmode:
9040 r = gen_consttable_sf (c->value);
9041 break;
9042 case DImode:
9043 r = gen_consttable_di (c->value);
9044 break;
9045 case DFmode:
9046 r = gen_consttable_df (c->value);
9047 break;
9048 default:
9049 abort ();
9050 }
9051
9052 insn = emit_insn_after (r, insn);
9053
9054 next = c->next;
9055 free (c);
9056 c = next;
9057 }
9058
9059 emit_barrier_after (insn);
9060}
9061
9062/* Find the symbol in an address expression. */
9063
9064static rtx
9065mips_find_symbol (addr)
9066 rtx addr;
9067{
9068 if (GET_CODE (addr) == MEM)
9069 addr = XEXP (addr, 0);
9070 while (GET_CODE (addr) == CONST)
9071 addr = XEXP (addr, 0);
9072 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9073 return addr;
9074 if (GET_CODE (addr) == PLUS)
9075 {
9076 rtx l1, l2;
9077
9078 l1 = mips_find_symbol (XEXP (addr, 0));
9079 l2 = mips_find_symbol (XEXP (addr, 1));
9080 if (l1 != NULL_RTX && l2 == NULL_RTX)
9081 return l1;
9082 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9083 return l2;
9084 }
9085 return NULL_RTX;
9086}
9087
9088/* Exported to toplev.c.
9089
9090 Do a final pass over the function, just before delayed branch
9091 scheduling. */
9092
9093void
9094machine_dependent_reorg (first)
9095 rtx first;
9096{
82305258 9097 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
2bcb2ab3
GK		 9098 rtx insn;
9099 struct constant *constants;
9100
9101 if (! TARGET_MIPS16)
9102 return;
9103
9104 /* If $gp is used, try to remove stores, and replace loads with
9105 copies from $gp. */
9106 if (optimize)
9107 mips16_optimize_gp (first);
9108
9109 /* Scan the function looking for PC relative loads which may be out
9110 of range. All such loads will either be from the constant table,
9111 or be getting the address of a constant string. If the size of
9112 the function plus the size of the constant table is less than
9113 0x8000, then all loads are in range. */
9114
9115 insns_len = 0;
9116 for (insn = first; insn; insn = NEXT_INSN (insn))
9117 {
0ff83799 9118 insns_len += get_attr_length (insn);
2bcb2ab3
GK		 9119
9120 /* ??? We put switch tables in .text, but we don't define
9121 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9122 compute their lengths correctly. */
9123 if (GET_CODE (insn) == JUMP_INSN)
9124 {
9125 rtx body;
9126
9127 body = PATTERN (insn);
9128 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9129 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9130 * GET_MODE_SIZE (GET_MODE (body)));
9131 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9132 }
9133 }
9134
9135 /* Store the original value of insns_len in current_frame_info, so
9136 that simple_memory_operand can look at it. */
9137 current_frame_info.insns_len = insns_len;
9138
9139 pool_size = get_pool_size ();
9140 if (insns_len + pool_size + mips_string_length < 0x8000)
9141 return;
9142
9143 /* Loop over the insns and figure out what the maximum internal pool
9144 size could be. */
9145 max_internal_pool_size = 0;
9146 for (insn = first; insn; insn = NEXT_INSN (insn))
9147 {
9148 if (GET_CODE (insn) == INSN
9149 && GET_CODE (PATTERN (insn)) == SET)
9150 {
9151 rtx src;
9152
9153 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9154 if (src == NULL_RTX)
9155 continue;
9156 if (CONSTANT_POOL_ADDRESS_P (src))
9157 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9158 else if (SYMBOL_REF_FLAG (src))
9159 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9160 }
9161 }
9162
9163 constants = NULL;
9164 addr = 0;
82305258 9165 first_constant_ref = -1;
2bcb2ab3
GK		 9166
9167 for (insn = first; insn; insn = NEXT_INSN (insn))
9168 {
9169 if (GET_CODE (insn) == INSN
9170 && GET_CODE (PATTERN (insn)) == SET)
9171 {
9172 rtx val, src;
404e4854 9173 enum machine_mode mode = VOIDmode;
2bcb2ab3
GK		 9174
9175 val = NULL_RTX;
9176 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9177 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9178 {
9179 /* ??? This is very conservative, which means that we
9180 will generate too many copies of the constant table.
9181 The only solution would seem to be some form of
9182 relaxing. */
9183 if (((insns_len - addr)
9184 + max_internal_pool_size
9185 + get_pool_offset (src))
9186 >= 0x8000)
9187 {
9188 val = get_pool_constant (src);
9189 mode = get_pool_mode (src);
9190 }
9191 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9192 }
9193 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9194 {
9195 /* Including all of mips_string_length is conservative,
9196 and so is including all of max_internal_pool_size. */
9197 if (((insns_len - addr)
9198 + max_internal_pool_size
9199 + pool_size
9200 + mips_string_length)
9201 >= 0x8000)
ddc22296
R		 9202 {
9203 val = src;
9204 mode = Pmode;
9205 }
2bcb2ab3
GK		 9206 max_internal_pool_size -= Pmode;
9207 }
9208
9209 if (val != NULL_RTX)
9210 {
9211 rtx lab, newsrc;
9212
9213 /* This PC relative load is out of range. ??? In the
9214 case of a string constant, we are only guessing that
9215 it is range, since we don't know the offset of a
9216 particular string constant. */
9217
9218 lab = add_constant (&constants, val, mode);
9219 newsrc = gen_rtx (MEM, mode,
9220 gen_rtx (LABEL_REF, VOIDmode, lab));
9221 RTX_UNCHANGING_P (newsrc) = 1;
9222 PATTERN (insn) = gen_rtx (SET, VOIDmode,
9223 SET_DEST (PATTERN (insn)),
9224 newsrc);
9225 INSN_CODE (insn) = -1;
82305258
AH		 9226
9227 if (first_constant_ref < 0)
9228 first_constant_ref = addr;
2bcb2ab3
GK		 9229 }
9230 }
9231
0ff83799 9232 addr += get_attr_length (insn);
2bcb2ab3
GK		 9233
9234 /* ??? We put switch tables in .text, but we don't define
9235 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9236 compute their lengths correctly. */
9237 if (GET_CODE (insn) == JUMP_INSN)
9238 {
9239 rtx body;
9240
9241 body = PATTERN (insn);
9242 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9243 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9244 * GET_MODE_SIZE (GET_MODE (body)));
9245 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9246 }
9247
9248 if (GET_CODE (insn) == BARRIER)
9249 {
9250 /* Output any constants we have accumulated. Note that we
9251 don't need to change ADDR, since its only use is
9252 subtraction from INSNS_LEN, and both would be changed by
9253 the same amount.
9254 ??? If the instructions up to the next barrier reuse a
9255 constant, it would often be better to continue
9256 accumulating. */
9257 if (constants != NULL)
9258 dump_constants (constants, insn);
9259 constants = NULL;
82305258 9260 first_constant_ref = -1;
2bcb2ab3 9261 }
82305258
AH		 9262
9263 if (constants != NULL
9264 && (NEXT_INSN (insn) == NULL
9265 || (first_constant_ref >= 0
9266 && (((addr - first_constant_ref)
9267 + 2 /* for alignment */
9268 + 2 /* for a short jump insn */
9269 + pool_size)
9270 >= 0x8000))))
9271 {
9272 /* If we haven't had a barrier within 0x8000 bytes of a
9273 constant reference or we are at the end of the function,
9274 emit a barrier now. */
2bcb2ab3 9275
82305258
AH		 9276 rtx label, jump, barrier;
9277
9278 label = gen_label_rtx ();
9279 jump = emit_jump_insn_after (gen_jump (label), insn);
9280 JUMP_LABEL (jump) = label;
9281 LABEL_NUSES (label) = 1;
9282 barrier = emit_barrier_after (jump);
9283 emit_label_after (label, barrier);
9284 first_constant_ref = -1;
9285 }
9286 }
2bcb2ab3
GK		 9287
9288 /* ??? If we output all references to a constant in internal
9289 constants table, we don't need to output the constant in the real
9290 constant table, but we have no way to prevent that. */
9291}
cb923660
KR		 9292
9293/* Return nonzero if X is a SIGN or ZERO extend operator. */
9294int
9295extend_operator (x, mode)
9296 rtx x;
38831dfe 9297 enum machine_mode mode ATTRIBUTE_UNUSED;
cb923660
KR		 9298{
9299 enum rtx_code code = GET_CODE (x);
9300 return code == SIGN_EXTEND || code == ZERO_EXTEND;
9301}
9302
9303/* Accept any operator that can be used to shift the high half of the
9304 input value to the lower half, suitable for truncation. The
9305 remainder (the lower half of the input, and the upper half of the
9306 output) will be discarded. */
9307int
9308highpart_shift_operator (x, mode)
9309 rtx x;
38831dfe 9310 enum machine_mode mode ATTRIBUTE_UNUSED;
cb923660
KR		 9311{
9312 enum rtx_code code = GET_CODE (x);
9313 return (code == LSHIFTRT
9314 || code == ASHIFTRT
9315 || code == ROTATERT
9316 || code == ROTATE);
9317}
0ff83799
MM		 9318
9319/* Return the length of INSN. LENGTH is the initial length computed by
9320 attributes in the machine-description file. */
9321
9322int
9323mips_adjust_insn_length (insn, length)
9324 rtx insn;
9325 int length;
9326{
9327 /* A unconditional jump has an unfilled delay slot if it is not part
9328 of a sequence. A conditional jump normally has a delay slot, but
9329 does not on MIPS16. */
9330 if (simplejump_p (insn)
9331 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
9332 || GET_CODE (insn) == CALL_INSN)))
9333 length += 4;
9334
9335 /* All MIPS16 instructions are a measly two bytes. */
9336 if (TARGET_MIPS16)
9337 length /= 2;
9338
9339 return length;
9340}
9341
9342/* Output assembly instructions to peform a conditional branch.
9343
9344 INSN is the branch instruction. OPERANDS[0] is the condition.
9345 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9346 of the first operand to the condition. If TWO_OPERANDS_P is
9347 non-zero the comparison takes two operands; OPERANDS[3] will be the
9348 second operand.
9349
9350 If INVERTED_P is non-zero we are to branch if the condition does
9351 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9352
9353 LENGTH is the length (in bytes) of the sequence we are to generate.
9354 That tells us whether to generate a simple conditional branch, or a
9355 reversed conditional branch around a `jr' instruction. */
9356char *
9357mips_output_conditional_branch (insn,
9358 operands,
9359 two_operands_p,
9360 float_p,
9361 inverted_p,
9362 length)
9363 rtx insn;
9364 rtx *operands;
9365 int two_operands_p;
9366 int float_p;
9367 int inverted_p;
9368 int length;
9369{
9370 static char buffer[200];
9371 /* The kind of comparison we are doing. */
9372 enum rtx_code code = GET_CODE (operands[0]);
9373 /* Non-zero if the opcode for the comparison needs a `z' indicating
9374 that it is a comparision against zero. */
9375 int need_z_p;
9376 /* A string to use in the assembly output to represent the first
9377 operand. */
bd9f1972 9378 const char *op1 = "%z2";
0ff83799
MM		 9379 /* A string to use in the assembly output to represent the second
9380 operand. Use the hard-wired zero register if there's no second
9381 operand. */
bd9f1972 9382 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
0ff83799 9383 /* The operand-printing string for the comparison. */
bd9f1972 9384 const char *comp = (float_p ? "%F0" : "%C0");
0ff83799 9385 /* The operand-printing string for the inverted comparison. */
bd9f1972 9386 const char *inverted_comp = (float_p ? "%W0" : "%N0");
0ff83799
MM		 9387
9388 /* The MIPS processors (for levels of the ISA at least two), have
9389 "likely" variants of each branch instruction. These instructions
9390 annul the instruction in the delay slot if the branch is not
9391 taken. */
9392 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9393
9394 if (!two_operands_p)
9395 {
9396 /* To compute whether than A > B, for example, we normally
9397 subtract B from A and then look at the sign bit. But, if we
9398 are doing an unsigned comparison, and B is zero, we don't
9399 have to do the subtraction. Instead, we can just check to
9400 see if A is non-zero. Thus, we change the CODE here to
9401 reflect the simpler comparison operation. */
9402 switch (code)
9403 {
9404 case GTU:
9405 code = NE;
9406 break;
9407
9408 case LEU:
9409 code = EQ;
9410 break;
9411
9412 case GEU:
9413 /* A condition which will always be true. */
9414 code = EQ;
9415 op1 = "%.";
9416 break;
9417
9418 case LTU:
9419 /* A condition which will always be false. */
9420 code = NE;
9421 op1 = "%.";
9422 break;
9423
9424 default:
9425 /* Not a special case. */
c4e992ae 9426 break;
0ff83799
MM		 9427 }
9428 }
9429
9430 /* Relative comparisons are always done against zero. But
9431 equality comparisons are done between two operands, and therefore
9432 do not require a `z' in the assembly language output. */
9433 need_z_p = (!float_p && code != EQ && code != NE);
9434 /* For comparisons against zero, the zero is not provided
9435 explicitly. */
9436 if (need_z_p)
9437 op2 = "";
9438
9439 /* Begin by terminating the buffer. That way we can always use
9440 strcat to add to it. */
9441 buffer[0] = '\0';
9442
9443 switch (length)
9444 {
9445 case 4:
9446 case 8:
9447 /* Just a simple conditional branch. */
9448 if (float_p)
9449 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9450 inverted_p ? inverted_comp : comp);
9451 else
9452 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9453 inverted_p ? inverted_comp : comp,
9454 need_z_p ? "z" : "",
9455 op1,
9456 op2);
9457 return buffer;
9458
9459 case 12:
9460 case 16:
9461 {
9462 /* Generate a reversed conditional branch around ` j'
9463 instruction:
9464
9465 .set noreorder
9466 .set nomacro
9467 bc l
9468 nop
9469 j target
9470 .set macro
9471 .set reorder
9472 l:
9473
9474 Because we have to jump four bytes *past* the following
9475 instruction if this branch was annulled, we can't just use
9476 a label, as in the picture above; there's no way to put the
9477 label after the next instruction, as the assembler does not
9478 accept `.L+4' as the target of a branch. (We can't just
9479 wait until the next instruction is output; it might be a
9480 macro and take up more than four bytes. Once again, we see
9481 why we want to eliminate macros.)
9482
9483 If the branch is annulled, we jump four more bytes that we
9484 would otherwise; that way we skip the annulled instruction
9485 in the delay slot. */
9486
bd9f1972 9487 const char *target
0ff83799
MM		 9488 = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
9489 char *c;
9490
9491 strcpy (buffer, "%(%<");
9492 c = strchr (buffer, '\0');
9493 /* Generate the reversed comparision. This takes four
9494 bytes. */
9495 if (float_p)
9496 sprintf (c, "%%*b%s\t%%Z2%s",
9497 inverted_p ? comp : inverted_comp,
9498 target);
9499 else
9500 sprintf (c, "%%*b%s%s\t%s%s,%s",
9501 inverted_p ? comp : inverted_comp,
9502 need_z_p ? "z" : "",
9503 op1,
9504 op2,
9505 target);
9506 strcat (c, "\n\tnop\n\tj\t%1");
9507 if (length == 16)
9508 /* The delay slot was unfilled. Since we're inside
9509 .noreorder, the assembler will not fill in the NOP for
9510 us, so we must do it ourselves. */
9511 strcat (buffer, "\n\tnop");
9512 strcat (buffer, "%>%)");
9513 return buffer;
9514 }
9515
9516 /* We do not currently use this code. It handles jumps to
9517 arbitrary locations, using `jr', even across a 256MB boundary.
9518 We could add a -mhuge switch, and then use this code instead of
9519 the `j' alternative above when -mhuge was used. */
9520#if 0
9521 case 16:
9522 case 20:
9523 {
9524 /* Generate a reversed conditional branch around a `jr'
9525 instruction:
9526
9527 .set noreorder
9528 .set nomacro
9529 .set noat
9530 bc l
9531 la $at, target
9532 jr $at
9533 .set at
9534 .set macro
9535 .set reorder
9536 l:
9537
9538 Not pretty, but allows a conditional branch anywhere in the
9539 32-bit address space. If the original branch is annulled,
9540 then the instruction in the delay slot should be executed
9541 only if the branch is taken. The la instruction is really
9542 a macro which will usually take eight bytes, but sometimes
9543 takes only four, if the instruction to which we're jumping
9544 gets its own entry in the global pointer table, which will
9545 happen if its a case label. The assembler will then
9546 generate only a four-byte sequence, rather than eight, and
9547 there seems to be no way to tell it not to. Thus, we can't
9548 just use a `.+x' addressing form; we don't know what value
9549 to give for `x'.
9550
9551 So, we resort to using the explicit relocation syntax
9552 available in the assembler and do:
9553
9554 lw $at,%got_page(target)($gp)
9555 daddiu $at,$at,%got_ofst(target)
9556
9557 That way, this always takes up eight bytes, and we can use
9558 the `.+x' form. Of course, these explicit machinations
9559 with relocation will not work with old assemblers. Then
9560 again, neither do out-of-range branches, so we haven't lost
9561 anything. */
9562
9563 /* The target of the reversed branch. */
bd9f1972 9564 const char *target
0ff83799 9565 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
bd9f1972
KG		 9566 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9567 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
0ff83799
MM		 9568 char *c;
9569
9570 strcpy (buffer, "%(%<%[");
9571 c = strchr (buffer, '\0');
9572 /* Generate the reversed comparision. This takes four
9573 bytes. */
9574 if (float_p)
9575 sprintf (c, "%%*b%s\t%%Z2%s",
9576 inverted_p ? comp : inverted_comp,
9577 target);
9578 else
9579 sprintf (c, "%%*b%s%s\t%s%s,%s",
9580 inverted_p ? comp : inverted_comp,
9581 need_z_p ? "z" : "",
9582 op1,
9583 op2,
9584 target);
9585 c = strchr (buffer, '\0');
9586 /* Generate the load-address, and jump. This takes twelve
9587 bytes, for a total of 16. */
9588 sprintf (c,
9589 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9590 at_register,
9591 gp_register,
9592 at_register,
9593 at_register,
9594 at_register);
9595 if (length == 20)
9596 /* The delay slot was unfilled. Since we're inside
9597 .noreorder, the assembler will not fill in the NOP for
9598 us, so we must do it ourselves. */
9599 strcat (buffer, "\n\tnop");
9600 strcat (buffer, "%]%>%)");
9601 return buffer;
9602 }
9603#endif
9604
9605 default:
9606 abort ();
9607 }
9608
9609 /* NOTREACHED */
9610 return 0;
9611}
d07d525a
MM		 9612
9613/* Called to register all of our global variables with the garbage
9614 collector. */
9615
9616static void
9617mips_add_gc_roots ()
9618{
9619 ggc_add_rtx_root (&mips_load_reg, 1);
9620 ggc_add_rtx_root (&mips_load_reg2, 1);
9621 ggc_add_rtx_root (&mips_load_reg3, 1);
9622 ggc_add_rtx_root (&mips_load_reg4, 1);
9623 ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
9624 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
9625 ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);
9626}
GNU Compiler Collection
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