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cee98a59 | 1 | /* Subroutines for insn-output.c for MIPS |
2096c147 | 2 | Copyright (C) 1989, 90, 91, 93-95, 1996 Free Software Foundation, Inc. |
cee98a59 | 3 | Contributed by A. Lichnewsky, lich@inria.inria.fr. |
b2a68403 | 4 | Changes by Michael Meissner, meissner@osf.org. |
147255d8 JW |
5 | 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and |
6 | Brendan Eich, brendan@microunity.com. | |
cee98a59 MM |
7 | |
8 | This file is part of GNU CC. | |
9 | ||
10 | GNU CC is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GNU CC is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GNU CC; see the file COPYING. If not, write to | |
0e29e3c9 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
cee98a59 | 24 | |
147255d8 JW |
25 | /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit |
26 | calling convention in 64 bit mode. It doesn't work though, and should | |
27 | be replaced with something better designed. */ | |
28 | ||
cee98a59 MM |
29 | #include "config.h" |
30 | #include "rtl.h" | |
31 | #include "regs.h" | |
32 | #include "hard-reg-set.h" | |
33 | #include "real.h" | |
34 | #include "insn-config.h" | |
35 | #include "conditions.h" | |
36 | #include "insn-flags.h" | |
37 | #include "insn-attr.h" | |
38 | #include "insn-codes.h" | |
39 | #include "recog.h" | |
40 | #include "output.h" | |
41 | ||
42 | #undef MAX /* sys/param.h may also define these */ | |
43 | #undef MIN | |
44 | ||
45 | #include <stdio.h> | |
46 | #include <signal.h> | |
47 | #include <sys/types.h> | |
48 | #include <sys/file.h> | |
49 | #include <ctype.h> | |
50 | #include "tree.h" | |
51 | #include "expr.h" | |
52 | #include "flags.h" | |
53 | ||
54 | #ifndef R_OK | |
55 | #define R_OK 4 | |
56 | #define W_OK 2 | |
57 | #define X_OK 1 | |
58 | #endif | |
59 | ||
9987501f | 60 | #if defined(USG) || defined(NO_STAB_H) |
cee98a59 MM |
61 | #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */ |
62 | #else | |
63 | #include <stab.h> /* On BSD, use the system's stab.h. */ | |
64 | #endif /* not USG */ | |
65 | ||
66 | #ifdef __GNU_STAB__ | |
67 | #define STAB_CODE_TYPE enum __stab_debug_code | |
68 | #else | |
69 | #define STAB_CODE_TYPE int | |
70 | #endif | |
71 | ||
0fb5ac6f MM |
72 | extern void abort (); |
73 | extern int atoi (); | |
74 | extern char *getenv (); | |
75 | extern char *mktemp (); | |
76 | ||
77 | extern rtx adj_offsettable_operand (); | |
78 | extern rtx copy_to_reg (); | |
79 | extern void error (); | |
80 | extern void fatal (); | |
81 | extern tree lookup_name (); | |
82 | extern void pfatal_with_name (); | |
83 | extern void warning (); | |
84 | ||
0fb5ac6f | 85 | extern FILE *asm_out_file; |
cee98a59 | 86 | |
34b650b3 MM |
87 | /* Enumeration for all of the relational tests, so that we can build |
88 | arrays indexed by the test type, and not worry about the order | |
89 | of EQ, NE, etc. */ | |
90 | ||
91 | enum internal_test { | |
92 | ITEST_EQ, | |
93 | ITEST_NE, | |
94 | ITEST_GT, | |
95 | ITEST_GE, | |
96 | ITEST_LT, | |
97 | ITEST_LE, | |
98 | ITEST_GTU, | |
99 | ITEST_GEU, | |
100 | ITEST_LTU, | |
101 | ITEST_LEU, | |
102 | ITEST_MAX | |
103 | }; | |
104 | ||
cee98a59 MM |
105 | /* Global variables for machine-dependent things. */ |
106 | ||
107 | /* Threshold for data being put into the small data/bss area, instead | |
108 | of the normal data area (references to the small data/bss area take | |
109 | 1 instruction, and use the global pointer, references to the normal | |
110 | data area takes 2 instructions). */ | |
111 | int mips_section_threshold = -1; | |
112 | ||
113 | /* Count the number of .file directives, so that .loc is up to date. */ | |
114 | int num_source_filenames = 0; | |
115 | ||
cee98a59 MM |
116 | /* Count the number of sdb related labels are generated (to find block |
117 | start and end boundaries). */ | |
118 | int sdb_label_count = 0; | |
119 | ||
ddd5a7c1 | 120 | /* Next label # for each statement for Silicon Graphics IRIS systems. */ |
cee98a59 MM |
121 | int sym_lineno = 0; |
122 | ||
123 | /* Non-zero if inside of a function, because the stupid MIPS asm can't | |
124 | handle .files inside of functions. */ | |
125 | int inside_function = 0; | |
126 | ||
cee98a59 MM |
127 | /* Files to separate the text and the data output, so that all of the data |
128 | can be emitted before the text, which will mean that the assembler will | |
129 | generate smaller code, based on the global pointer. */ | |
130 | FILE *asm_out_data_file; | |
131 | FILE *asm_out_text_file; | |
132 | ||
133 | /* Linked list of all externals that are to be emitted when optimizing | |
134 | for the global pointer if they haven't been declared by the end of | |
135 | the program with an appropriate .comm or initialization. */ | |
136 | ||
137 | struct extern_list { | |
138 | struct extern_list *next; /* next external */ | |
139 | char *name; /* name of the external */ | |
140 | int size; /* size in bytes */ | |
141 | } *extern_head = 0; | |
142 | ||
cee98a59 MM |
143 | /* Name of the file containing the current function. */ |
144 | char *current_function_file = ""; | |
145 | ||
146 | /* Warning given that Mips ECOFF can't support changing files | |
147 | within a function. */ | |
148 | int file_in_function_warning = FALSE; | |
149 | ||
c831afd5 | 150 | /* Whether to suppress issuing .loc's because the user attempted |
cee98a59 MM |
151 | to change the filename within a function. */ |
152 | int ignore_line_number = FALSE; | |
153 | ||
154 | /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */ | |
155 | int set_noreorder; | |
156 | int set_noat; | |
157 | int set_nomacro; | |
158 | int set_volatile; | |
159 | ||
160 | /* The next branch instruction is a branch likely, not branch normal. */ | |
161 | int mips_branch_likely; | |
162 | ||
163 | /* Count of delay slots and how many are filled. */ | |
164 | int dslots_load_total; | |
165 | int dslots_load_filled; | |
166 | int dslots_jump_total; | |
167 | int dslots_jump_filled; | |
168 | ||
169 | /* # of nops needed by previous insn */ | |
170 | int dslots_number_nops; | |
171 | ||
172 | /* Number of 1/2/3 word references to data items (ie, not jal's). */ | |
173 | int num_refs[3]; | |
174 | ||
175 | /* registers to check for load delay */ | |
176 | rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4; | |
177 | ||
178 | /* Cached operands, and operator to compare for use in set/branch on | |
179 | condition codes. */ | |
180 | rtx branch_cmp[2]; | |
181 | ||
182 | /* what type of branch to use */ | |
183 | enum cmp_type branch_type; | |
184 | ||
6f3c667f MM |
185 | /* Number of previously seen half-pic pointers and references. */ |
186 | static int prev_half_pic_ptrs = 0; | |
187 | static int prev_half_pic_refs = 0; | |
188 | ||
cee98a59 MM |
189 | /* which cpu are we scheduling for */ |
190 | enum processor_type mips_cpu; | |
191 | ||
192 | /* which instruction set architecture to use. */ | |
193 | int mips_isa; | |
194 | ||
ade6c319 JW |
195 | #ifdef MIPS_ABI_DEFAULT |
196 | /* which ABI to use. This is defined to a constant in mips.h if the target | |
197 | doesn't support multiple ABIs. */ | |
198 | enum mips_abi_type mips_abi; | |
199 | #endif | |
200 | ||
cee98a59 MM |
201 | /* Strings to hold which cpu and instruction set architecture to use. */ |
202 | char *mips_cpu_string; /* for -mcpu=<xxx> */ | |
33563487 | 203 | char *mips_isa_string; /* for -mips{1,2,3,4} */ |
293a36eb | 204 | char *mips_abi_string; /* for -mabi={o32,32,n32,n64,64,eabi} */ |
cee98a59 | 205 | |
910628b8 JW |
206 | /* If TRUE, we split addresses into their high and low parts in the RTL. */ |
207 | int mips_split_addresses; | |
208 | ||
ffa9d0b1 | 209 | /* Generating calls to position independent functions? */ |
1d6ce736 | 210 | enum mips_abicalls_type mips_abicalls; |
ffa9d0b1 | 211 | |
147255d8 JW |
212 | /* High and low marks for floating point values which we will accept |
213 | as legitimate constants for LEGITIMATE_CONSTANT_P. These are | |
214 | initialized in override_options. */ | |
215 | REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow; | |
216 | ||
cee98a59 MM |
217 | /* Array giving truth value on whether or not a given hard register |
218 | can support a given mode. */ | |
219 | char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; | |
220 | ||
221 | /* Current frame information calculated by compute_frame_size. */ | |
222 | struct mips_frame_info current_frame_info; | |
223 | ||
224 | /* Zero structure to initialize current_frame_info. */ | |
225 | struct mips_frame_info zero_frame_info; | |
226 | ||
c831afd5 MM |
227 | /* Temporary filename used to buffer .text until end of program |
228 | for -mgpopt. */ | |
229 | static char *temp_filename; | |
230 | ||
92544bdf ILT |
231 | /* Pseudo-reg holding the address of the current function when |
232 | generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used | |
233 | by mips_finalize_pic if it was created. */ | |
234 | rtx embedded_pic_fnaddr_rtx; | |
235 | ||
cee98a59 MM |
236 | /* List of all MIPS punctuation characters used by print_operand. */ |
237 | char mips_print_operand_punct[256]; | |
238 | ||
239 | /* Map GCC register number to debugger register number. */ | |
240 | int mips_dbx_regno[FIRST_PSEUDO_REGISTER]; | |
241 | ||
242 | /* Buffer to use to enclose a load/store operation with %{ %} to | |
243 | turn on .set volatile. */ | |
244 | static char volatile_buffer[60]; | |
245 | ||
246 | /* Hardware names for the registers. If -mrnames is used, this | |
247 | will be overwritten with mips_sw_reg_names. */ | |
248 | ||
249 | char mips_reg_names[][8] = | |
250 | { | |
251 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", | |
252 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
253 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
254 | "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", | |
255 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", | |
256 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", | |
257 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", | |
258 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", | |
b8eb88d0 ILT |
259 | "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", |
260 | "$fcc5","$fcc6","$fcc7","$rap" | |
cee98a59 MM |
261 | }; |
262 | ||
263 | /* Mips software names for the registers, used to overwrite the | |
264 | mips_reg_names array. */ | |
265 | ||
266 | char mips_sw_reg_names[][8] = | |
267 | { | |
147255d8 JW |
268 | "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3", |
269 | "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", | |
270 | "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", | |
271 | "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra", | |
cee98a59 MM |
272 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", |
273 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", | |
274 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", | |
275 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", | |
b8eb88d0 ILT |
276 | "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", |
277 | "$fcc5","$fcc6","$fcc7","$rap" | |
cee98a59 MM |
278 | }; |
279 | ||
280 | /* Map hard register number to register class */ | |
281 | enum reg_class mips_regno_to_class[] = | |
282 | { | |
283 | GR_REGS, GR_REGS, GR_REGS, GR_REGS, | |
284 | GR_REGS, GR_REGS, GR_REGS, GR_REGS, | |
285 | GR_REGS, GR_REGS, GR_REGS, GR_REGS, | |
286 | GR_REGS, GR_REGS, GR_REGS, GR_REGS, | |
287 | GR_REGS, GR_REGS, GR_REGS, GR_REGS, | |
288 | GR_REGS, GR_REGS, GR_REGS, GR_REGS, | |
289 | GR_REGS, GR_REGS, GR_REGS, GR_REGS, | |
290 | GR_REGS, GR_REGS, GR_REGS, GR_REGS, | |
291 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
292 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
293 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
294 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
295 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
296 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
297 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
298 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
b987661c | 299 | HI_REG, LO_REG, HILO_REG, ST_REGS, |
b8eb88d0 ILT |
300 | ST_REGS, ST_REGS, ST_REGS, ST_REGS, |
301 | ST_REGS, ST_REGS, ST_REGS, GR_REGS | |
cee98a59 MM |
302 | }; |
303 | ||
304 | /* Map register constraint character to register class. */ | |
305 | enum reg_class mips_char_to_class[256] = | |
306 | { | |
307 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
308 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
309 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
310 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
311 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
312 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
313 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
314 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
315 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
316 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
317 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
318 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
319 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
320 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
321 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
322 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
323 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
324 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
325 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
326 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
327 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
328 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
329 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
330 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
331 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
332 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
333 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
334 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
335 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
336 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
337 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
338 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
339 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
340 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
341 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
342 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
343 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
344 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
345 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
346 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
347 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
348 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
349 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
350 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
351 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
352 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
353 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
354 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
355 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
356 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
357 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
358 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
359 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
360 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
361 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
362 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
363 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
364 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
365 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
366 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
367 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
368 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
369 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
370 | NO_REGS, NO_REGS, NO_REGS, NO_REGS, | |
371 | }; | |
372 | ||
373 | \f | |
374 | /* Return truth value of whether OP can be used as an operands | |
375 | where a register or 16 bit unsigned integer is needed. */ | |
376 | ||
377 | int | |
378 | uns_arith_operand (op, mode) | |
379 | rtx op; | |
380 | enum machine_mode mode; | |
381 | { | |
382 | if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op)) | |
383 | return TRUE; | |
384 | ||
385 | return register_operand (op, mode); | |
386 | } | |
387 | ||
388 | /* Return truth value of whether OP can be used as an operands | |
389 | where a 16 bit integer is needed */ | |
390 | ||
391 | int | |
392 | arith_operand (op, mode) | |
393 | rtx op; | |
394 | enum machine_mode mode; | |
395 | { | |
396 | if (GET_CODE (op) == CONST_INT && SMALL_INT (op)) | |
397 | return TRUE; | |
398 | ||
399 | return register_operand (op, mode); | |
400 | } | |
401 | ||
402 | /* Return truth value of whether OP can be used as an operand in a two | |
403 | address arithmetic insn (such as set 123456,%o4) of mode MODE. */ | |
404 | ||
405 | int | |
406 | arith32_operand (op, mode) | |
407 | rtx op; | |
408 | enum machine_mode mode; | |
409 | { | |
410 | if (GET_CODE (op) == CONST_INT) | |
411 | return TRUE; | |
412 | ||
413 | return register_operand (op, mode); | |
414 | } | |
415 | ||
416 | /* Return truth value of whether OP is a integer which fits in 16 bits */ | |
417 | ||
418 | int | |
419 | small_int (op, mode) | |
420 | rtx op; | |
421 | enum machine_mode mode; | |
422 | { | |
423 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); | |
424 | } | |
425 | ||
33563487 | 426 | /* Return truth value of whether OP is a 32 bit integer which is too big to |
cee98a59 MM |
427 | be loaded with one instruction. */ |
428 | ||
429 | int | |
430 | large_int (op, mode) | |
431 | rtx op; | |
432 | enum machine_mode mode; | |
433 | { | |
85f5e2b6 | 434 | HOST_WIDE_INT value; |
cee98a59 MM |
435 | |
436 | if (GET_CODE (op) != CONST_INT) | |
437 | return FALSE; | |
438 | ||
439 | value = INTVAL (op); | |
4763b498 | 440 | if ((value & ~0x0000ffff) == 0) /* ior reg,$r0,value */ |
cee98a59 MM |
441 | return FALSE; |
442 | ||
4763b498 | 443 | if (((unsigned long)(value + 32768)) <= 32767) /* subu reg,$r0,value */ |
cee98a59 MM |
444 | return FALSE; |
445 | ||
33563487 | 446 | if ((value & 0x0000ffff) == 0) /* lui reg,value>>16 */ |
cee98a59 MM |
447 | return FALSE; |
448 | ||
449 | return TRUE; | |
450 | } | |
451 | ||
452 | /* Return truth value of whether OP is a register or the constant 0. */ | |
453 | ||
454 | int | |
455 | reg_or_0_operand (op, mode) | |
456 | rtx op; | |
457 | enum machine_mode mode; | |
458 | { | |
459 | switch (GET_CODE (op)) | |
460 | { | |
0fb5ac6f MM |
461 | default: |
462 | break; | |
463 | ||
cee98a59 MM |
464 | case CONST_INT: |
465 | return (INTVAL (op) == 0); | |
466 | ||
467 | case CONST_DOUBLE: | |
147255d8 | 468 | if (op != CONST0_RTX (mode)) |
cee98a59 MM |
469 | return FALSE; |
470 | ||
471 | return TRUE; | |
472 | ||
473 | case REG: | |
474 | case SUBREG: | |
475 | return register_operand (op, mode); | |
476 | } | |
477 | ||
478 | return FALSE; | |
479 | } | |
480 | ||
cee98a59 MM |
481 | /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ |
482 | ||
483 | int | |
484 | mips_const_double_ok (op, mode) | |
485 | rtx op; | |
486 | enum machine_mode mode; | |
487 | { | |
85098019 JW |
488 | REAL_VALUE_TYPE d; |
489 | ||
cee98a59 MM |
490 | if (GET_CODE (op) != CONST_DOUBLE) |
491 | return FALSE; | |
492 | ||
79438502 | 493 | if (mode == VOIDmode) |
cee98a59 MM |
494 | return TRUE; |
495 | ||
496 | if (mode != SFmode && mode != DFmode) | |
497 | return FALSE; | |
498 | ||
147255d8 | 499 | if (op == CONST0_RTX (mode)) |
cee98a59 MM |
500 | return TRUE; |
501 | ||
33563487 | 502 | /* ??? li.s does not work right with SGI's Irix 6 assembler. */ |
293a36eb | 503 | if (mips_abi != ABI_32 && mips_abi != ABI_EABI) |
33563487 JW |
504 | return FALSE; |
505 | ||
85098019 | 506 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); |
cee98a59 | 507 | |
85098019 JW |
508 | if (REAL_VALUE_ISNAN (d)) |
509 | return FALSE; | |
cee98a59 | 510 | |
85098019 JW |
511 | if (REAL_VALUE_NEGATIVE (d)) |
512 | d = REAL_VALUE_NEGATE (d); | |
cee98a59 | 513 | |
85098019 JW |
514 | if (mode == DFmode) |
515 | { | |
516 | if (REAL_VALUES_LESS (d, dfhigh) | |
517 | && REAL_VALUES_LESS (dflow, d)) | |
518 | return TRUE; | |
519 | } | |
520 | else | |
521 | { | |
522 | if (REAL_VALUES_LESS (d, sfhigh) | |
523 | && REAL_VALUES_LESS (sflow, d)) | |
524 | return TRUE; | |
cee98a59 | 525 | } |
cee98a59 MM |
526 | |
527 | return FALSE; | |
528 | } | |
529 | ||
b8eb88d0 ILT |
530 | /* Accept the floating point constant 1 in the appropriate mode. */ |
531 | ||
532 | int | |
533 | const_float_1_operand (op, mode) | |
534 | rtx op; | |
535 | enum machine_mode mode; | |
536 | { | |
537 | REAL_VALUE_TYPE d; | |
538 | static REAL_VALUE_TYPE onedf; | |
539 | static REAL_VALUE_TYPE onesf; | |
540 | static int one_initialized; | |
541 | ||
542 | if (GET_CODE (op) != CONST_DOUBLE | |
543 | || mode != GET_MODE (op) | |
544 | || (mode != DFmode && mode != SFmode)) | |
545 | return FALSE; | |
546 | ||
547 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
548 | ||
549 | /* We only initialize these values if we need them, since we will | |
550 | never get called unless mips_isa >= 4. */ | |
551 | if (! one_initialized) | |
552 | { | |
553 | onedf = REAL_VALUE_ATOF ("1.0", DFmode); | |
554 | onesf = REAL_VALUE_ATOF ("1.0", SFmode); | |
555 | one_initialized = TRUE; | |
556 | } | |
557 | ||
558 | if (mode == DFmode) | |
559 | return REAL_VALUES_EQUAL (d, onedf); | |
560 | else | |
561 | return REAL_VALUES_EQUAL (d, onesf); | |
562 | } | |
563 | ||
cee98a59 MM |
564 | /* Return truth value if a memory operand fits in a single instruction |
565 | (ie, register + small offset). */ | |
566 | ||
567 | int | |
568 | simple_memory_operand (op, mode) | |
569 | rtx op; | |
570 | enum machine_mode mode; | |
571 | { | |
572 | rtx addr, plus0, plus1; | |
cee98a59 MM |
573 | |
574 | /* Eliminate non-memory operations */ | |
575 | if (GET_CODE (op) != MEM) | |
576 | return FALSE; | |
577 | ||
578 | /* dword operations really put out 2 instructions, so eliminate them. */ | |
910628b8 JW |
579 | /* ??? This isn't strictly correct. It is OK to accept multiword modes |
580 | here, since the length attributes are being set correctly, but only | |
581 | if the address is offsettable. LO_SUM is not offsettable. */ | |
147255d8 | 582 | if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD) |
cee98a59 MM |
583 | return FALSE; |
584 | ||
585 | /* Decode the address now. */ | |
586 | addr = XEXP (op, 0); | |
587 | switch (GET_CODE (addr)) | |
588 | { | |
0fb5ac6f MM |
589 | default: |
590 | break; | |
591 | ||
cee98a59 | 592 | case REG: |
910628b8 | 593 | case LO_SUM: |
cee98a59 MM |
594 | return TRUE; |
595 | ||
596 | case CONST_INT: | |
597 | return SMALL_INT (op); | |
598 | ||
599 | case PLUS: | |
600 | plus0 = XEXP (addr, 0); | |
601 | plus1 = XEXP (addr, 1); | |
602 | if (GET_CODE (plus0) == REG | |
603 | && GET_CODE (plus1) == CONST_INT | |
604 | && SMALL_INT (plus1)) | |
605 | return TRUE; | |
606 | ||
607 | else if (GET_CODE (plus1) == REG | |
608 | && GET_CODE (plus0) == CONST_INT | |
609 | && SMALL_INT (plus0)) | |
610 | return TRUE; | |
611 | ||
612 | else | |
613 | return FALSE; | |
614 | ||
615 | #if 0 | |
616 | /* We used to allow small symbol refs here (ie, stuff in .sdata | |
617 | or .sbss), but this causes some bugs in G++. Also, it won't | |
618 | interfere if the MIPS linker rewrites the store instruction | |
619 | because the function is PIC. */ | |
620 | ||
621 | case LABEL_REF: /* never gp relative */ | |
622 | break; | |
623 | ||
624 | case CONST: | |
625 | /* If -G 0, we can never have a GP relative memory operation. | |
626 | Also, save some time if not optimizing. */ | |
147255d8 | 627 | if (!TARGET_GP_OPT) |
cee98a59 MM |
628 | return FALSE; |
629 | ||
c831afd5 MM |
630 | { |
631 | rtx offset = const0_rtx; | |
147255d8 | 632 | addr = eliminate_constant_term (XEXP (addr, 0), &offset); |
c831afd5 MM |
633 | if (GET_CODE (op) != SYMBOL_REF) |
634 | return FALSE; | |
cee98a59 | 635 | |
c831afd5 | 636 | /* let's be paranoid.... */ |
147255d8 | 637 | if (! SMALL_INT (offset)) |
c831afd5 MM |
638 | return FALSE; |
639 | } | |
cee98a59 MM |
640 | /* fall through */ |
641 | ||
642 | case SYMBOL_REF: | |
cee98a59 MM |
643 | return SYMBOL_REF_FLAG (addr); |
644 | #endif | |
645 | } | |
646 | ||
647 | return FALSE; | |
648 | } | |
649 | ||
cee98a59 MM |
650 | /* Return true if the code of this rtx pattern is EQ or NE. */ |
651 | ||
652 | int | |
653 | equality_op (op, mode) | |
654 | rtx op; | |
655 | enum machine_mode mode; | |
656 | { | |
657 | if (mode != GET_MODE (op)) | |
658 | return FALSE; | |
659 | ||
85098019 | 660 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); |
cee98a59 MM |
661 | } |
662 | ||
663 | /* Return true if the code is a relational operations (EQ, LE, etc.) */ | |
664 | ||
665 | int | |
666 | cmp_op (op, mode) | |
667 | rtx op; | |
668 | enum machine_mode mode; | |
669 | { | |
670 | if (mode != GET_MODE (op)) | |
671 | return FALSE; | |
672 | ||
85098019 | 673 | return (GET_RTX_CLASS (GET_CODE (op)) == '<'); |
cee98a59 MM |
674 | } |
675 | ||
34b650b3 MM |
676 | /* Return true if the operand is either the PC or a label_ref. */ |
677 | ||
678 | int | |
679 | pc_or_label_operand (op, mode) | |
680 | rtx op; | |
681 | enum machine_mode mode; | |
682 | { | |
683 | if (op == pc_rtx) | |
684 | return TRUE; | |
685 | ||
686 | if (GET_CODE (op) == LABEL_REF) | |
687 | return TRUE; | |
688 | ||
689 | return FALSE; | |
690 | } | |
691 | ||
50c0000c RS |
692 | /* Test for a valid operand for a call instruction. |
693 | Don't allow the arg pointer register or virtual regs | |
694 | since they may change into reg + const, which the patterns | |
695 | can't handle yet. */ | |
696 | ||
697 | int | |
698 | call_insn_operand (op, mode) | |
699 | rtx op; | |
700 | enum machine_mode mode; | |
701 | { | |
910628b8 JW |
702 | if (CONSTANT_ADDRESS_P (op) |
703 | || (GET_CODE (op) == REG && op != arg_pointer_rtx | |
704 | && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
705 | && REGNO (op) <= LAST_VIRTUAL_REGISTER))) | |
706 | return 1; | |
707 | return 0; | |
708 | } | |
709 | ||
710 | /* Return true if OPERAND is valid as a source operand for a move | |
711 | instruction. */ | |
712 | ||
713 | int | |
714 | move_operand (op, mode) | |
715 | rtx op; | |
716 | enum machine_mode mode; | |
717 | { | |
15f3d16a JL |
718 | /* Accept any general operand after reload has started; doing so |
719 | avoids losing if reload does an in-place replacement of a register | |
720 | with a SYMBOL_REF or CONST. */ | |
910628b8 | 721 | return (general_operand (op, mode) |
15f3d16a JL |
722 | && (! (mips_split_addresses && mips_check_split (op, mode)) |
723 | || reload_in_progress | |
724 | || reload_completed)); | |
725 | ||
726 | ||
910628b8 JW |
727 | } |
728 | ||
2a0b0bf5 ILT |
729 | /* Return true if OPERAND is valid as a source operand for movdi. |
730 | This accepts not only general_operand, but also sign extended | |
731 | constants and registers. We need to accept sign extended constants | |
732 | in case a sign extended register which is used in an expression, | |
733 | and is equivalent to a constant, is spilled. */ | |
734 | ||
735 | int | |
736 | movdi_operand (op, mode) | |
737 | rtx op; | |
738 | enum machine_mode mode; | |
739 | { | |
740 | if (TARGET_64BIT | |
741 | && mode == DImode | |
742 | && GET_CODE (op) == SIGN_EXTEND | |
743 | && GET_MODE (op) == DImode | |
744 | && (GET_MODE (XEXP (op, 0)) == SImode | |
745 | || (GET_CODE (XEXP (op, 0)) == CONST_INT | |
746 | && GET_MODE (XEXP (op, 0)) == VOIDmode)) | |
747 | && (register_operand (XEXP (op, 0), SImode) | |
748 | || immediate_operand (XEXP (op, 0), SImode))) | |
749 | return 1; | |
750 | ||
751 | return general_operand (op, mode); | |
752 | } | |
753 | ||
754 | /* Like register_operand, but when in 64 bit mode also accept a sign | |
755 | extend of a 32 bit register, since the value is known to be already | |
756 | sign extended. */ | |
757 | ||
758 | int | |
759 | se_register_operand (op, mode) | |
760 | rtx op; | |
761 | enum machine_mode mode; | |
762 | { | |
763 | if (TARGET_64BIT | |
764 | && mode == DImode | |
765 | && GET_CODE (op) == SIGN_EXTEND | |
766 | && GET_MODE (op) == DImode | |
767 | && GET_MODE (XEXP (op, 0)) == SImode | |
768 | && register_operand (XEXP (op, 0), SImode)) | |
769 | return 1; | |
770 | ||
771 | return register_operand (op, mode); | |
772 | } | |
773 | ||
774 | /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign | |
775 | extend of a 32 bit register, since the value is known to be already | |
776 | sign extended. */ | |
777 | ||
778 | int | |
779 | se_reg_or_0_operand (op, mode) | |
780 | rtx op; | |
781 | enum machine_mode mode; | |
782 | { | |
783 | if (TARGET_64BIT | |
784 | && mode == DImode | |
785 | && GET_CODE (op) == SIGN_EXTEND | |
786 | && GET_MODE (op) == DImode | |
787 | && GET_MODE (XEXP (op, 0)) == SImode | |
788 | && register_operand (XEXP (op, 0), SImode)) | |
789 | return 1; | |
790 | ||
791 | return reg_or_0_operand (op, mode); | |
792 | } | |
793 | ||
794 | /* Like uns_arith_operand, but when in 64 bit mode also accept a sign | |
795 | extend of a 32 bit register, since the value is known to be already | |
796 | sign extended. */ | |
797 | ||
798 | int | |
799 | se_uns_arith_operand (op, mode) | |
800 | rtx op; | |
801 | enum machine_mode mode; | |
802 | { | |
803 | if (TARGET_64BIT | |
804 | && mode == DImode | |
805 | && GET_CODE (op) == SIGN_EXTEND | |
806 | && GET_MODE (op) == DImode | |
807 | && GET_MODE (XEXP (op, 0)) == SImode | |
808 | && register_operand (XEXP (op, 0), SImode)) | |
809 | return 1; | |
810 | ||
811 | return uns_arith_operand (op, mode); | |
812 | } | |
813 | ||
814 | /* Like arith_operand, but when in 64 bit mode also accept a sign | |
815 | extend of a 32 bit register, since the value is known to be already | |
816 | sign extended. */ | |
817 | ||
818 | int | |
819 | se_arith_operand (op, mode) | |
820 | rtx op; | |
821 | enum machine_mode mode; | |
822 | { | |
823 | if (TARGET_64BIT | |
824 | && mode == DImode | |
825 | && GET_CODE (op) == SIGN_EXTEND | |
826 | && GET_MODE (op) == DImode | |
827 | && GET_MODE (XEXP (op, 0)) == SImode | |
828 | && register_operand (XEXP (op, 0), SImode)) | |
829 | return 1; | |
830 | ||
831 | return arith_operand (op, mode); | |
832 | } | |
833 | ||
834 | /* Like nonmemory_operand, but when in 64 bit mode also accept a sign | |
835 | extend of a 32 bit register, since the value is known to be already | |
836 | sign extended. */ | |
837 | ||
838 | int | |
839 | se_nonmemory_operand (op, mode) | |
840 | rtx op; | |
841 | enum machine_mode mode; | |
842 | { | |
843 | if (TARGET_64BIT | |
844 | && mode == DImode | |
845 | && GET_CODE (op) == SIGN_EXTEND | |
846 | && GET_MODE (op) == DImode | |
847 | && GET_MODE (XEXP (op, 0)) == SImode | |
848 | && register_operand (XEXP (op, 0), SImode)) | |
849 | return 1; | |
850 | ||
851 | return nonmemory_operand (op, mode); | |
852 | } | |
853 | ||
854 | /* Like nonimmediate_operand, but when in 64 bit mode also accept a | |
855 | sign extend of a 32 bit register, since the value is known to be | |
856 | already sign extended. */ | |
857 | ||
858 | int | |
859 | se_nonimmediate_operand (op, mode) | |
860 | rtx op; | |
861 | enum machine_mode mode; | |
862 | { | |
863 | if (TARGET_64BIT | |
864 | && mode == DImode | |
865 | && GET_CODE (op) == SIGN_EXTEND | |
866 | && GET_MODE (op) == DImode | |
867 | && GET_MODE (XEXP (op, 0)) == SImode | |
868 | && register_operand (XEXP (op, 0), SImode)) | |
869 | return 1; | |
870 | ||
871 | return nonimmediate_operand (op, mode); | |
872 | } | |
873 | ||
910628b8 JW |
874 | /* Return true if we split the address into high and low parts. */ |
875 | ||
876 | /* ??? We should also handle reg+array somewhere. We get four | |
877 | instructions currently, lui %hi/addui %lo/addui reg/lw. Better is | |
878 | lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept | |
879 | (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken | |
880 | out of the address, then we have 4 instructions to combine. Perhaps | |
881 | add a 3->2 define_split for combine. */ | |
882 | ||
883 | /* ??? We could also split a CONST_INT here if it is a large_int(). | |
884 | However, it doesn't seem to be very useful to have %hi(constant). | |
885 | We would be better off by doing the masking ourselves and then putting | |
886 | the explicit high part of the constant in the RTL. This will give better | |
887 | optimization. Also, %hi(constant) needs assembler changes to work. | |
888 | There is already a define_split that does this. */ | |
889 | ||
890 | int | |
891 | mips_check_split (address, mode) | |
892 | rtx address; | |
893 | enum machine_mode mode; | |
894 | { | |
895 | /* ??? This is the same check used in simple_memory_operand. | |
896 | We use it here because LO_SUM is not offsettable. */ | |
897 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
898 | return 0; | |
899 | ||
900 | if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address)) | |
901 | || (GET_CODE (address) == CONST | |
902 | && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF | |
903 | && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0))) | |
904 | || GET_CODE (address) == LABEL_REF) | |
50c0000c | 905 | return 1; |
910628b8 | 906 | |
50c0000c RS |
907 | return 0; |
908 | } | |
cee98a59 | 909 | \f |
85098019 JW |
910 | /* Returns an operand string for the given instruction's delay slot, |
911 | after updating filled delay slot statistics. | |
cee98a59 MM |
912 | |
913 | We assume that operands[0] is the target register that is set. | |
914 | ||
915 | In order to check the next insn, most of this functionality is moved | |
916 | to FINAL_PRESCAN_INSN, and we just set the global variables that | |
917 | it needs. */ | |
918 | ||
85098019 JW |
919 | /* ??? This function no longer does anything useful, because final_prescan_insn |
920 | now will never emit a nop. */ | |
921 | ||
cee98a59 MM |
922 | char * |
923 | mips_fill_delay_slot (ret, type, operands, cur_insn) | |
924 | char *ret; /* normal string to return */ | |
925 | enum delay_type type; /* type of delay */ | |
926 | rtx operands[]; /* operands to use */ | |
927 | rtx cur_insn; /* current insn */ | |
928 | { | |
929 | register rtx set_reg; | |
930 | register enum machine_mode mode; | |
931 | register rtx next_insn = (cur_insn) ? NEXT_INSN (cur_insn) : (rtx)0; | |
932 | register int num_nops; | |
933 | ||
34b650b3 | 934 | if (type == DELAY_LOAD || type == DELAY_FCMP) |
cee98a59 MM |
935 | num_nops = 1; |
936 | ||
937 | else if (type == DELAY_HILO) | |
938 | num_nops = 2; | |
939 | ||
940 | else | |
941 | num_nops = 0; | |
942 | ||
943 | /* Make sure that we don't put nop's after labels. */ | |
944 | next_insn = NEXT_INSN (cur_insn); | |
945 | while (next_insn != (rtx)0 && GET_CODE (next_insn) == NOTE) | |
946 | next_insn = NEXT_INSN (next_insn); | |
947 | ||
948 | dslots_load_total += num_nops; | |
949 | if (TARGET_DEBUG_F_MODE | |
950 | || !optimize | |
951 | || type == DELAY_NONE | |
952 | || operands == (rtx *)0 | |
953 | || cur_insn == (rtx)0 | |
954 | || next_insn == (rtx)0 | |
955 | || GET_CODE (next_insn) == CODE_LABEL | |
956 | || (set_reg = operands[0]) == (rtx)0) | |
957 | { | |
958 | dslots_number_nops = 0; | |
959 | mips_load_reg = (rtx)0; | |
960 | mips_load_reg2 = (rtx)0; | |
961 | mips_load_reg3 = (rtx)0; | |
962 | mips_load_reg4 = (rtx)0; | |
963 | return ret; | |
964 | } | |
965 | ||
966 | set_reg = operands[0]; | |
967 | if (set_reg == (rtx)0) | |
968 | return ret; | |
969 | ||
970 | while (GET_CODE (set_reg) == SUBREG) | |
971 | set_reg = SUBREG_REG (set_reg); | |
972 | ||
973 | mode = GET_MODE (set_reg); | |
974 | dslots_number_nops = num_nops; | |
147255d8 JW |
975 | mips_load_reg = set_reg; |
976 | if (GET_MODE_SIZE (mode) | |
b2a68403 | 977 | > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD)) |
147255d8 JW |
978 | mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1); |
979 | else | |
980 | mips_load_reg2 = 0; | |
cee98a59 MM |
981 | |
982 | if (type == DELAY_HILO) | |
983 | { | |
984 | mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST); | |
985 | mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1); | |
986 | } | |
987 | else | |
988 | { | |
989 | mips_load_reg3 = 0; | |
990 | mips_load_reg4 = 0; | |
991 | } | |
992 | ||
cee98a59 MM |
993 | return ret; |
994 | } | |
995 | ||
996 | \f | |
997 | /* Determine whether a memory reference takes one (based off of the GP pointer), | |
c831afd5 | 998 | two (normal), or three (label + reg) instructions, and bump the appropriate |
cee98a59 MM |
999 | counter for -mstats. */ |
1000 | ||
1001 | void | |
1002 | mips_count_memory_refs (op, num) | |
1003 | rtx op; | |
1004 | int num; | |
1005 | { | |
1006 | int additional = 0; | |
1007 | int n_words = 0; | |
1008 | rtx addr, plus0, plus1; | |
1009 | enum rtx_code code0, code1; | |
1010 | int looping; | |
1011 | ||
1012 | if (TARGET_DEBUG_B_MODE) | |
1013 | { | |
1014 | fprintf (stderr, "\n========== mips_count_memory_refs:\n"); | |
1015 | debug_rtx (op); | |
1016 | } | |
1017 | ||
1018 | /* Skip MEM if passed, otherwise handle movsi of address. */ | |
1019 | addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0); | |
1020 | ||
1021 | /* Loop, going through the address RTL */ | |
1022 | do | |
1023 | { | |
1024 | looping = FALSE; | |
1025 | switch (GET_CODE (addr)) | |
1026 | { | |
0fb5ac6f MM |
1027 | default: |
1028 | break; | |
1029 | ||
cee98a59 MM |
1030 | case REG: |
1031 | case CONST_INT: | |
910628b8 | 1032 | case LO_SUM: |
cee98a59 MM |
1033 | break; |
1034 | ||
1035 | case PLUS: | |
1036 | plus0 = XEXP (addr, 0); | |
1037 | plus1 = XEXP (addr, 1); | |
1038 | code0 = GET_CODE (plus0); | |
1039 | code1 = GET_CODE (plus1); | |
1040 | ||
1041 | if (code0 == REG) | |
1042 | { | |
1043 | additional++; | |
1044 | addr = plus1; | |
1045 | looping = TRUE; | |
1046 | continue; | |
1047 | } | |
1048 | ||
1049 | if (code0 == CONST_INT) | |
1050 | { | |
1051 | addr = plus1; | |
1052 | looping = TRUE; | |
1053 | continue; | |
1054 | } | |
1055 | ||
1056 | if (code1 == REG) | |
1057 | { | |
1058 | additional++; | |
1059 | addr = plus0; | |
1060 | looping = TRUE; | |
1061 | continue; | |
1062 | } | |
1063 | ||
1064 | if (code1 == CONST_INT) | |
1065 | { | |
1066 | addr = plus0; | |
1067 | looping = TRUE; | |
1068 | continue; | |
1069 | } | |
1070 | ||
1071 | if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST) | |
1072 | { | |
1073 | addr = plus0; | |
1074 | looping = TRUE; | |
1075 | continue; | |
1076 | } | |
1077 | ||
1078 | if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST) | |
1079 | { | |
1080 | addr = plus1; | |
1081 | looping = TRUE; | |
1082 | continue; | |
1083 | } | |
1084 | ||
1085 | break; | |
1086 | ||
1087 | case LABEL_REF: | |
1088 | n_words = 2; /* always 2 words */ | |
1089 | break; | |
1090 | ||
1091 | case CONST: | |
1092 | addr = XEXP (addr, 0); | |
1093 | looping = TRUE; | |
1094 | continue; | |
1095 | ||
1096 | case SYMBOL_REF: | |
1097 | n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2; | |
1098 | break; | |
1099 | } | |
1100 | } | |
1101 | while (looping); | |
1102 | ||
1103 | if (n_words == 0) | |
1104 | return; | |
1105 | ||
1106 | n_words += additional; | |
1107 | if (n_words > 3) | |
1108 | n_words = 3; | |
1109 | ||
1110 | num_refs[n_words-1] += num; | |
1111 | } | |
1112 | ||
1113 | \f | |
92544bdf ILT |
1114 | /* Return RTL for the offset from the current function to the |
1115 | argument. */ | |
1116 | ||
1117 | rtx | |
1118 | embedded_pic_offset (x) | |
1119 | rtx x; | |
1120 | { | |
1121 | if (embedded_pic_fnaddr_rtx == NULL) | |
40f8d046 JW |
1122 | { |
1123 | rtx seq; | |
1124 | ||
1125 | embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode); | |
1126 | ||
abc95ed3 | 1127 | /* Output code at function start to initialize the pseudo-reg. */ |
40f8d046 JW |
1128 | /* ??? We used to do this in FINALIZE_PIC, but that does not work for |
1129 | inline functions, because it is called after RTL for the function | |
1130 | has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however | |
1131 | does not get copied, and ends up not matching the rest of the RTL. | |
1132 | This solution works, but means that we get unnecessary code to | |
abc95ed3 | 1133 | initialize this value every time a function is inlined into another |
40f8d046 JW |
1134 | function. */ |
1135 | start_sequence (); | |
1136 | emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx, | |
1137 | XEXP (DECL_RTL (current_function_decl), 0))); | |
1138 | seq = gen_sequence (); | |
1139 | end_sequence (); | |
1140 | push_topmost_sequence (); | |
1141 | emit_insn_after (seq, get_insns ()); | |
1142 | pop_topmost_sequence (); | |
1143 | } | |
1144 | ||
92544bdf ILT |
1145 | return gen_rtx (CONST, Pmode, |
1146 | gen_rtx (MINUS, Pmode, x, | |
1147 | XEXP (DECL_RTL (current_function_decl), 0))); | |
1148 | } | |
1149 | ||
cee98a59 MM |
1150 | /* Return the appropriate instructions to move one operand to another. */ |
1151 | ||
1152 | char * | |
1153 | mips_move_1word (operands, insn, unsignedp) | |
1154 | rtx operands[]; | |
1155 | rtx insn; | |
1156 | int unsignedp; | |
1157 | { | |
1158 | char *ret = 0; | |
1159 | rtx op0 = operands[0]; | |
1160 | rtx op1 = operands[1]; | |
1161 | enum rtx_code code0 = GET_CODE (op0); | |
1162 | enum rtx_code code1 = GET_CODE (op1); | |
1163 | enum machine_mode mode = GET_MODE (op0); | |
1164 | int subreg_word0 = 0; | |
1165 | int subreg_word1 = 0; | |
1166 | enum delay_type delay = DELAY_NONE; | |
1167 | ||
1168 | while (code0 == SUBREG) | |
1169 | { | |
1170 | subreg_word0 += SUBREG_WORD (op0); | |
1171 | op0 = SUBREG_REG (op0); | |
1172 | code0 = GET_CODE (op0); | |
1173 | } | |
1174 | ||
1175 | while (code1 == SUBREG) | |
1176 | { | |
1177 | subreg_word1 += SUBREG_WORD (op1); | |
1178 | op1 = SUBREG_REG (op1); | |
1179 | code1 = GET_CODE (op1); | |
1180 | } | |
1181 | ||
b8eb88d0 ILT |
1182 | /* For our purposes, a condition code mode is the same as SImode. */ |
1183 | if (mode == CCmode) | |
1184 | mode = SImode; | |
1185 | ||
cee98a59 MM |
1186 | if (code0 == REG) |
1187 | { | |
1188 | int regno0 = REGNO (op0) + subreg_word0; | |
1189 | ||
1190 | if (code1 == REG) | |
1191 | { | |
1192 | int regno1 = REGNO (op1) + subreg_word1; | |
1193 | ||
1194 | /* Just in case, don't do anything for assigning a register | |
1195 | to itself, unless we are filling a delay slot. */ | |
1196 | if (regno0 == regno1 && set_nomacro == 0) | |
1197 | ret = ""; | |
1198 | ||
1199 | else if (GP_REG_P (regno0)) | |
1200 | { | |
1201 | if (GP_REG_P (regno1)) | |
1202 | ret = "move\t%0,%1"; | |
1203 | ||
1204 | else if (MD_REG_P (regno1)) | |
1205 | { | |
1206 | delay = DELAY_HILO; | |
225b8835 ILT |
1207 | if (regno1 != HILO_REGNUM) |
1208 | ret = "mf%1\t%0"; | |
1209 | else | |
1210 | ret = "mflo\t%0"; | |
cee98a59 MM |
1211 | } |
1212 | ||
b8eb88d0 ILT |
1213 | else if (ST_REG_P (regno1) && mips_isa >= 4) |
1214 | ret = "li\t%0,1\n\tmovf\t%0,%.,%1"; | |
1215 | ||
cee98a59 MM |
1216 | else |
1217 | { | |
1218 | delay = DELAY_LOAD; | |
1219 | if (FP_REG_P (regno1)) | |
1220 | ret = "mfc1\t%0,%1"; | |
1221 | ||
b8eb88d0 | 1222 | else if (regno1 == FPSW_REGNUM && mips_isa < 4) |
cee98a59 MM |
1223 | ret = "cfc1\t%0,$31"; |
1224 | } | |
1225 | } | |
1226 | ||
1227 | else if (FP_REG_P (regno0)) | |
1228 | { | |
1229 | if (GP_REG_P (regno1)) | |
1230 | { | |
1231 | delay = DELAY_LOAD; | |
1232 | ret = "mtc1\t%1,%0"; | |
1233 | } | |
1234 | ||
1235 | if (FP_REG_P (regno1)) | |
1236 | ret = "mov.s\t%0,%1"; | |
1237 | } | |
1238 | ||
1239 | else if (MD_REG_P (regno0)) | |
1240 | { | |
1241 | if (GP_REG_P (regno1)) | |
1242 | { | |
1243 | delay = DELAY_HILO; | |
225b8835 ILT |
1244 | if (regno0 != HILO_REGNUM) |
1245 | ret = "mt%0\t%1"; | |
cee98a59 MM |
1246 | } |
1247 | } | |
1248 | ||
b8eb88d0 | 1249 | else if (regno0 == FPSW_REGNUM && mips_isa < 4) |
cee98a59 MM |
1250 | { |
1251 | if (GP_REG_P (regno1)) | |
1252 | { | |
1253 | delay = DELAY_LOAD; | |
1254 | ret = "ctc1\t%0,$31"; | |
1255 | } | |
1256 | } | |
1257 | } | |
1258 | ||
1259 | else if (code1 == MEM) | |
1260 | { | |
1261 | delay = DELAY_LOAD; | |
1262 | ||
1263 | if (TARGET_STATS) | |
1264 | mips_count_memory_refs (op1, 1); | |
1265 | ||
1266 | if (GP_REG_P (regno0)) | |
1267 | { | |
1268 | /* For loads, use the mode of the memory item, instead of the | |
1269 | target, so zero/sign extend can use this code as well. */ | |
1270 | switch (GET_MODE (op1)) | |
1271 | { | |
147255d8 JW |
1272 | default: |
1273 | break; | |
1274 | case SFmode: | |
1275 | ret = "lw\t%0,%1"; | |
1276 | break; | |
1277 | case SImode: | |
b8eb88d0 | 1278 | case CCmode: |
147255d8 JW |
1279 | ret = ((unsignedp && TARGET_64BIT) |
1280 | ? "lwu\t%0,%1" | |
1281 | : "lw\t%0,%1"); | |
1282 | break; | |
1283 | case HImode: | |
1284 | ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1"; | |
1285 | break; | |
1286 | case QImode: | |
1287 | ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1"; | |
1288 | break; | |
cee98a59 MM |
1289 | } |
1290 | } | |
1291 | ||
1292 | else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode)) | |
1293 | ret = "l.s\t%0,%1"; | |
1294 | ||
1295 | if (ret != (char *)0 && MEM_VOLATILE_P (op1)) | |
1296 | { | |
1297 | int i = strlen (ret); | |
1298 | if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) | |
1299 | abort (); | |
1300 | ||
1301 | sprintf (volatile_buffer, "%%{%s%%}", ret); | |
1302 | ret = volatile_buffer; | |
1303 | } | |
1304 | } | |
1305 | ||
79438502 JW |
1306 | else if (code1 == CONST_INT |
1307 | || (code1 == CONST_DOUBLE | |
1308 | && GET_MODE (op1) == VOIDmode)) | |
cee98a59 | 1309 | { |
79438502 JW |
1310 | if (code1 == CONST_DOUBLE) |
1311 | { | |
1312 | /* This can happen when storing constants into long long | |
1313 | bitfields. Just store the least significant word of | |
1314 | the value. */ | |
1315 | operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1)); | |
1316 | } | |
1317 | ||
cee98a59 MM |
1318 | if (INTVAL (op1) == 0) |
1319 | { | |
1320 | if (GP_REG_P (regno0)) | |
1321 | ret = "move\t%0,%z1"; | |
1322 | ||
1323 | else if (FP_REG_P (regno0)) | |
1324 | { | |
1325 | delay = DELAY_LOAD; | |
842eb20e | 1326 | ret = "mtc1\t%z1,%0"; |
cee98a59 | 1327 | } |
225b8835 ILT |
1328 | |
1329 | else if (MD_REG_P (regno0)) | |
1330 | { | |
1331 | delay = DELAY_HILO; | |
1332 | ret = "mt%0\t%."; | |
1333 | } | |
cee98a59 MM |
1334 | } |
1335 | ||
1336 | else if (GP_REG_P (regno0)) | |
ade6c319 JW |
1337 | /* Don't use X format, because that will give out of range |
1338 | numbers for 64 bit host and 32 bit target. */ | |
1339 | ret = "li\t%0,%1\t\t\t# %X1"; | |
cee98a59 MM |
1340 | } |
1341 | ||
1342 | else if (code1 == CONST_DOUBLE && mode == SFmode) | |
1343 | { | |
147255d8 | 1344 | if (op1 == CONST0_RTX (SFmode)) |
cee98a59 MM |
1345 | { |
1346 | if (GP_REG_P (regno0)) | |
1347 | ret = "move\t%0,%."; | |
1348 | ||
1349 | else if (FP_REG_P (regno0)) | |
1350 | { | |
1351 | delay = DELAY_LOAD; | |
1352 | ret = "mtc1\t%.,%0"; | |
1353 | } | |
1354 | } | |
1355 | ||
1356 | else | |
1357 | { | |
1358 | delay = DELAY_LOAD; | |
1359 | ret = "li.s\t%0,%1"; | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | else if (code1 == LABEL_REF) | |
cee98a59 MM |
1364 | { |
1365 | if (TARGET_STATS) | |
1366 | mips_count_memory_refs (op1, 1); | |
1367 | ||
c7343333 MM |
1368 | ret = "la\t%0,%a1"; |
1369 | } | |
1370 | ||
1371 | else if (code1 == SYMBOL_REF || code1 == CONST) | |
1372 | { | |
c831afd5 | 1373 | if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1)) |
cee98a59 | 1374 | { |
c7343333 MM |
1375 | rtx offset = const0_rtx; |
1376 | ||
1377 | if (GET_CODE (op1) == CONST) | |
1378 | op1 = eliminate_constant_term (XEXP (op1, 0), &offset); | |
1379 | ||
1380 | if (GET_CODE (op1) == SYMBOL_REF) | |
1381 | { | |
1382 | operands[2] = HALF_PIC_PTR (op1); | |
1383 | ||
1384 | if (TARGET_STATS) | |
1385 | mips_count_memory_refs (operands[2], 1); | |
1386 | ||
1387 | if (INTVAL (offset) == 0) | |
1388 | { | |
1389 | delay = DELAY_LOAD; | |
147255d8 JW |
1390 | ret = (unsignedp && TARGET_64BIT |
1391 | ? "lwu\t%0,%2" | |
1392 | : "lw\t%0,%2"); | |
c7343333 MM |
1393 | } |
1394 | else | |
1395 | { | |
1396 | dslots_load_total++; | |
1397 | operands[3] = offset; | |
147255d8 JW |
1398 | if (unsignedp && TARGET_64BIT) |
1399 | ret = (SMALL_INT (offset)) | |
1400 | ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3" | |
1401 | : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]"; | |
1402 | else | |
1403 | ret = (SMALL_INT (offset)) | |
1404 | ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3" | |
1405 | : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]"; | |
c7343333 MM |
1406 | } |
1407 | } | |
cee98a59 MM |
1408 | } |
1409 | else | |
c7343333 MM |
1410 | { |
1411 | if (TARGET_STATS) | |
1412 | mips_count_memory_refs (op1, 1); | |
1413 | ||
1414 | ret = "la\t%0,%a1"; | |
1415 | } | |
cee98a59 MM |
1416 | } |
1417 | ||
1418 | else if (code1 == PLUS) | |
1419 | { | |
1420 | rtx add_op0 = XEXP (op1, 0); | |
1421 | rtx add_op1 = XEXP (op1, 1); | |
1422 | ||
1423 | if (GET_CODE (XEXP (op1, 1)) == REG && GET_CODE (XEXP (op1, 0)) == CONST_INT) | |
1424 | { | |
1425 | add_op0 = XEXP (op1, 1); /* reverse operands */ | |
1426 | add_op1 = XEXP (op1, 0); | |
1427 | } | |
1428 | ||
1429 | operands[2] = add_op0; | |
1430 | operands[3] = add_op1; | |
1431 | ret = "add%:\t%0,%2,%3"; | |
1432 | } | |
910628b8 JW |
1433 | |
1434 | else if (code1 == HIGH) | |
1435 | { | |
1436 | operands[1] = XEXP (op1, 0); | |
1437 | ret = "lui\t%0,%%hi(%1)"; | |
1438 | } | |
cee98a59 MM |
1439 | } |
1440 | ||
1441 | else if (code0 == MEM) | |
1442 | { | |
1443 | if (TARGET_STATS) | |
1444 | mips_count_memory_refs (op0, 1); | |
1445 | ||
1446 | if (code1 == REG) | |
1447 | { | |
1448 | int regno1 = REGNO (op1) + subreg_word1; | |
1449 | ||
1450 | if (GP_REG_P (regno1)) | |
1451 | { | |
1452 | switch (mode) | |
1453 | { | |
0fb5ac6f | 1454 | default: break; |
cee98a59 MM |
1455 | case SFmode: ret = "sw\t%1,%0"; break; |
1456 | case SImode: ret = "sw\t%1,%0"; break; | |
1457 | case HImode: ret = "sh\t%1,%0"; break; | |
1458 | case QImode: ret = "sb\t%1,%0"; break; | |
1459 | } | |
1460 | } | |
1461 | ||
1462 | else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode)) | |
1463 | ret = "s.s\t%1,%0"; | |
1464 | } | |
1465 | ||
1466 | else if (code1 == CONST_INT && INTVAL (op1) == 0) | |
1467 | { | |
1468 | switch (mode) | |
1469 | { | |
0fb5ac6f | 1470 | default: break; |
cee98a59 MM |
1471 | case SFmode: ret = "sw\t%z1,%0"; break; |
1472 | case SImode: ret = "sw\t%z1,%0"; break; | |
1473 | case HImode: ret = "sh\t%z1,%0"; break; | |
1474 | case QImode: ret = "sb\t%z1,%0"; break; | |
1475 | } | |
1476 | } | |
1477 | ||
147255d8 | 1478 | else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode)) |
cee98a59 MM |
1479 | { |
1480 | switch (mode) | |
1481 | { | |
0fb5ac6f | 1482 | default: break; |
cee98a59 MM |
1483 | case SFmode: ret = "sw\t%.,%0"; break; |
1484 | case SImode: ret = "sw\t%.,%0"; break; | |
1485 | case HImode: ret = "sh\t%.,%0"; break; | |
1486 | case QImode: ret = "sb\t%.,%0"; break; | |
1487 | } | |
1488 | } | |
1489 | ||
1490 | if (ret != (char *)0 && MEM_VOLATILE_P (op0)) | |
1491 | { | |
1492 | int i = strlen (ret); | |
1493 | if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) | |
1494 | abort (); | |
1495 | ||
1496 | sprintf (volatile_buffer, "%%{%s%%}", ret); | |
1497 | ret = volatile_buffer; | |
1498 | } | |
1499 | } | |
1500 | ||
1501 | if (ret == (char *)0) | |
1502 | { | |
1503 | abort_with_insn (insn, "Bad move"); | |
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | if (delay != DELAY_NONE) | |
1508 | return mips_fill_delay_slot (ret, delay, operands, insn); | |
1509 | ||
1510 | return ret; | |
1511 | } | |
1512 | ||
1513 | \f | |
1514 | /* Return the appropriate instructions to move 2 words */ | |
1515 | ||
1516 | char * | |
1517 | mips_move_2words (operands, insn) | |
1518 | rtx operands[]; | |
1519 | rtx insn; | |
1520 | { | |
1521 | char *ret = 0; | |
1522 | rtx op0 = operands[0]; | |
1523 | rtx op1 = operands[1]; | |
1524 | enum rtx_code code0 = GET_CODE (operands[0]); | |
1525 | enum rtx_code code1 = GET_CODE (operands[1]); | |
1526 | int subreg_word0 = 0; | |
1527 | int subreg_word1 = 0; | |
1528 | enum delay_type delay = DELAY_NONE; | |
1529 | ||
1530 | while (code0 == SUBREG) | |
1531 | { | |
1532 | subreg_word0 += SUBREG_WORD (op0); | |
1533 | op0 = SUBREG_REG (op0); | |
1534 | code0 = GET_CODE (op0); | |
1535 | } | |
1536 | ||
2a0b0bf5 ILT |
1537 | if (code1 == SIGN_EXTEND) |
1538 | { | |
1539 | op1 = XEXP (op1, 0); | |
1540 | code1 = GET_CODE (op1); | |
1541 | } | |
1542 | ||
cee98a59 MM |
1543 | while (code1 == SUBREG) |
1544 | { | |
1545 | subreg_word1 += SUBREG_WORD (op1); | |
1546 | op1 = SUBREG_REG (op1); | |
1547 | code1 = GET_CODE (op1); | |
1548 | } | |
1549 | ||
2a0b0bf5 ILT |
1550 | /* Sanity check. */ |
1551 | if (GET_CODE (operands[1]) == SIGN_EXTEND | |
1552 | && code1 != REG | |
27c38b75 JW |
1553 | && code1 != CONST_INT |
1554 | /* The following three can happen as the result of a questionable | |
1555 | cast. */ | |
1556 | && code1 != LABEL_REF | |
1557 | && code1 != SYMBOL_REF | |
1558 | && code1 != CONST) | |
2a0b0bf5 ILT |
1559 | abort (); |
1560 | ||
cee98a59 MM |
1561 | if (code0 == REG) |
1562 | { | |
1563 | int regno0 = REGNO (op0) + subreg_word0; | |
1564 | ||
1565 | if (code1 == REG) | |
1566 | { | |
1567 | int regno1 = REGNO (op1) + subreg_word1; | |
1568 | ||
1569 | /* Just in case, don't do anything for assigning a register | |
1570 | to itself, unless we are filling a delay slot. */ | |
1571 | if (regno0 == regno1 && set_nomacro == 0) | |
1572 | ret = ""; | |
1573 | ||
1574 | else if (FP_REG_P (regno0)) | |
1575 | { | |
1576 | if (FP_REG_P (regno1)) | |
1577 | ret = "mov.d\t%0,%1"; | |
1578 | ||
1579 | else | |
1580 | { | |
1581 | delay = DELAY_LOAD; | |
f8151871 | 1582 | if (TARGET_FLOAT64) |
147255d8 | 1583 | { |
f8151871 JW |
1584 | if (!TARGET_64BIT) |
1585 | abort_with_insn (insn, "Bad move"); | |
147255d8 JW |
1586 | #ifdef TARGET_FP_CALL_32 |
1587 | if (FP_CALL_GP_REG_P (regno1)) | |
1588 | ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0"; | |
1589 | else | |
1590 | #endif | |
1591 | ret = "dmtc1\t%1,%0"; | |
1592 | } | |
1593 | else | |
1594 | ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0"; | |
cee98a59 MM |
1595 | } |
1596 | } | |
1597 | ||
1598 | else if (FP_REG_P (regno1)) | |
1599 | { | |
1600 | delay = DELAY_LOAD; | |
f8151871 | 1601 | if (TARGET_FLOAT64) |
147255d8 | 1602 | { |
f8151871 JW |
1603 | if (!TARGET_64BIT) |
1604 | abort_with_insn (insn, "Bad move"); | |
147255d8 JW |
1605 | #ifdef TARGET_FP_CALL_32 |
1606 | if (FP_CALL_GP_REG_P (regno0)) | |
1607 | ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32"; | |
1608 | else | |
1609 | #endif | |
1610 | ret = "dmfc1\t%0,%1"; | |
1611 | } | |
1612 | else | |
1613 | ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1"; | |
cee98a59 MM |
1614 | } |
1615 | ||
1616 | else if (MD_REG_P (regno0) && GP_REG_P (regno1)) | |
1617 | { | |
1618 | delay = DELAY_HILO; | |
147255d8 | 1619 | if (TARGET_64BIT) |
225b8835 ILT |
1620 | { |
1621 | if (regno0 != HILO_REGNUM) | |
1622 | ret = "mt%0\t%1"; | |
1623 | else if (regno1 == 0) | |
1624 | ret = "mtlo\t%.\n\tmthi\t%."; | |
1625 | } | |
147255d8 JW |
1626 | else |
1627 | ret = "mthi\t%M1\n\tmtlo\t%L1"; | |
cee98a59 MM |
1628 | } |
1629 | ||
1630 | else if (GP_REG_P (regno0) && MD_REG_P (regno1)) | |
1631 | { | |
1632 | delay = DELAY_HILO; | |
147255d8 | 1633 | if (TARGET_64BIT) |
225b8835 ILT |
1634 | { |
1635 | if (regno1 != HILO_REGNUM) | |
1636 | ret = "mf%1\t%0"; | |
1637 | } | |
147255d8 JW |
1638 | else |
1639 | ret = "mfhi\t%M0\n\tmflo\t%L0"; | |
cee98a59 MM |
1640 | } |
1641 | ||
147255d8 JW |
1642 | else if (TARGET_64BIT) |
1643 | ret = "move\t%0,%1"; | |
1644 | ||
cee98a59 MM |
1645 | else if (regno0 != (regno1+1)) |
1646 | ret = "move\t%0,%1\n\tmove\t%D0,%D1"; | |
1647 | ||
1648 | else | |
1649 | ret = "move\t%D0,%D1\n\tmove\t%0,%1"; | |
1650 | } | |
1651 | ||
1652 | else if (code1 == CONST_DOUBLE) | |
1653 | { | |
f8151871 JW |
1654 | /* Move zero from $0 unless !TARGET_64BIT and recipient |
1655 | is 64-bit fp reg, in which case generate a constant. */ | |
1656 | if (op1 != CONST0_RTX (GET_MODE (op1)) | |
1657 | || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0))) | |
cee98a59 MM |
1658 | { |
1659 | if (GET_MODE (op1) == DFmode) | |
1660 | { | |
1661 | delay = DELAY_LOAD; | |
147255d8 JW |
1662 | #ifdef TARGET_FP_CALL_32 |
1663 | if (FP_CALL_GP_REG_P (regno0)) | |
f8151871 JW |
1664 | { |
1665 | if (TARGET_FLOAT64 && !TARGET_64BIT) | |
1666 | { | |
96abdcb1 ILT |
1667 | split_double (op1, operands + 2, operands + 3); |
1668 | ret = "li\t%0,%2\n\tli\t%D0,%3"; | |
f8151871 JW |
1669 | } |
1670 | else | |
1671 | ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32"; | |
1672 | } | |
147255d8 JW |
1673 | else |
1674 | #endif | |
1675 | ret = "li.d\t%0,%1"; | |
cee98a59 MM |
1676 | } |
1677 | ||
33563487 JW |
1678 | else if (TARGET_64BIT) |
1679 | ret = "dli\t%0,%1"; | |
147255d8 | 1680 | |
cee98a59 MM |
1681 | else |
1682 | { | |
96abdcb1 ILT |
1683 | split_double (op1, operands + 2, operands + 3); |
1684 | ret = "li\t%0,%2\n\tli\t%D0,%3"; | |
cee98a59 MM |
1685 | } |
1686 | } | |
1687 | ||
1688 | else | |
1689 | { | |
1690 | if (GP_REG_P (regno0)) | |
147255d8 JW |
1691 | ret = (TARGET_64BIT |
1692 | #ifdef TARGET_FP_CALL_32 | |
1693 | && ! FP_CALL_GP_REG_P (regno0) | |
1694 | #endif | |
1695 | ) | |
1696 | ? "move\t%0,%." | |
1697 | : "move\t%0,%.\n\tmove\t%D0,%."; | |
cee98a59 MM |
1698 | |
1699 | else if (FP_REG_P (regno0)) | |
1700 | { | |
1701 | delay = DELAY_LOAD; | |
147255d8 | 1702 | ret = (TARGET_64BIT) |
cee98a59 MM |
1703 | ? "dmtc1\t%.,%0" |
1704 | : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"; | |
1705 | } | |
1706 | } | |
1707 | } | |
1708 | ||
1709 | else if (code1 == CONST_INT && INTVAL (op1) == 0) | |
1710 | { | |
1711 | if (GP_REG_P (regno0)) | |
147255d8 JW |
1712 | ret = (TARGET_64BIT) |
1713 | ? "move\t%0,%." | |
1714 | : "move\t%0,%.\n\tmove\t%D0,%."; | |
cee98a59 MM |
1715 | |
1716 | else if (FP_REG_P (regno0)) | |
1717 | { | |
1718 | delay = DELAY_LOAD; | |
147255d8 | 1719 | ret = (TARGET_64BIT) |
cee98a59 | 1720 | ? "dmtc1\t%.,%0" |
f8151871 JW |
1721 | : (TARGET_FLOAT64 |
1722 | ? "li.d\t%0,%1" | |
1723 | : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"); | |
cee98a59 | 1724 | } |
225b8835 ILT |
1725 | else if (MD_REG_P (regno0)) |
1726 | { | |
1727 | delay = DELAY_HILO; | |
1728 | if (regno0 != HILO_REGNUM) | |
1729 | ret = "mt%0\t%.\n"; | |
1730 | else | |
1731 | ret = "mtlo\t%.\n\tmthi\t%."; | |
1732 | } | |
cee98a59 MM |
1733 | } |
1734 | ||
1735 | else if (code1 == CONST_INT && GET_MODE (op0) == DImode && GP_REG_P (regno0)) | |
1736 | { | |
147255d8 | 1737 | if (TARGET_64BIT) |
33563487 | 1738 | { |
2a0b0bf5 ILT |
1739 | if (GET_CODE (operands[1]) == SIGN_EXTEND) |
1740 | ret = "li\t%0,%1\t\t# %X1"; | |
1741 | else if (HOST_BITS_PER_WIDE_INT < 64) | |
33563487 JW |
1742 | /* We can't use 'X' for negative numbers, because then we won't |
1743 | get the right value for the upper 32 bits. */ | |
1744 | ret = ((INTVAL (op1) < 0) ? "dli\t%0,%1\t\t\t# %X1" | |
1745 | : "dli\t%0,%X1\t\t# %1"); | |
1746 | else | |
1747 | /* We must use 'X', because otherwise LONG_MIN will print as | |
1748 | a number that the assembler won't accept. */ | |
1749 | ret = "dli\t%0,%X1\t\t# %1"; | |
1750 | } | |
ade6c319 | 1751 | else if (HOST_BITS_PER_WIDE_INT < 64) |
147255d8 JW |
1752 | { |
1753 | operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1); | |
1754 | ret = "li\t%M0,%2\n\tli\t%L0,%1"; | |
1755 | } | |
ade6c319 JW |
1756 | else |
1757 | { | |
5107b750 JW |
1758 | /* We use multiple shifts here, to avoid warnings about out |
1759 | of range shifts on 32 bit hosts. */ | |
1760 | operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16); | |
1761 | operands[1] = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16); | |
ade6c319 JW |
1762 | ret = "li\t%M0,%2\n\tli\t%L0,%1"; |
1763 | } | |
cee98a59 MM |
1764 | } |
1765 | ||
1766 | else if (code1 == MEM) | |
1767 | { | |
1768 | delay = DELAY_LOAD; | |
1769 | ||
1770 | if (TARGET_STATS) | |
1771 | mips_count_memory_refs (op1, 2); | |
1772 | ||
1773 | if (FP_REG_P (regno0)) | |
1774 | ret = "l.d\t%0,%1"; | |
1775 | ||
147255d8 JW |
1776 | else if (TARGET_64BIT) |
1777 | { | |
1778 | #ifdef TARGET_FP_CALL_32 | |
1779 | if (FP_CALL_GP_REG_P (regno0)) | |
1780 | { | |
1781 | if (offsettable_address_p (FALSE, SImode, op1)) | |
1782 | ret = "lwu\t%0,%1\n\tlwu\t%D0,4+%1"; | |
1783 | else | |
1784 | ret = "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32"; | |
1785 | } | |
1786 | else | |
1787 | #endif | |
1788 | ret = "ld\t%0,%1"; | |
1789 | } | |
1790 | ||
cee98a59 MM |
1791 | else if (offsettable_address_p (1, DFmode, XEXP (op1, 0))) |
1792 | { | |
1793 | operands[2] = adj_offsettable_operand (op1, 4); | |
1794 | if (reg_mentioned_p (op0, op1)) | |
1795 | ret = "lw\t%D0,%2\n\tlw\t%0,%1"; | |
1796 | else | |
1797 | ret = "lw\t%0,%1\n\tlw\t%D0,%2"; | |
1798 | } | |
1799 | ||
1800 | if (ret != (char *)0 && MEM_VOLATILE_P (op1)) | |
1801 | { | |
1802 | int i = strlen (ret); | |
1803 | if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) | |
1804 | abort (); | |
1805 | ||
1806 | sprintf (volatile_buffer, "%%{%s%%}", ret); | |
1807 | ret = volatile_buffer; | |
1808 | } | |
1809 | } | |
147255d8 JW |
1810 | |
1811 | else if (code1 == LABEL_REF | |
1812 | || code1 == SYMBOL_REF | |
1813 | || code1 == CONST) | |
1814 | { | |
33563487 JW |
1815 | if (TARGET_STATS) |
1816 | mips_count_memory_refs (op1, 2); | |
1817 | ||
27c38b75 JW |
1818 | if (GET_CODE (operands[1]) == SIGN_EXTEND) |
1819 | /* We deliberately remove the 'a' from '%1', so that we don't | |
1820 | have to add SIGN_EXTEND support to print_operand_address. | |
1821 | print_operand will just call print_operand_address in this | |
1822 | case, so there is no problem. */ | |
1823 | ret = "la\t%0,%1"; | |
1824 | else | |
1825 | ret = "dla\t%0,%a1"; | |
147255d8 | 1826 | } |
cee98a59 MM |
1827 | } |
1828 | ||
1829 | else if (code0 == MEM) | |
1830 | { | |
1831 | if (code1 == REG) | |
1832 | { | |
1833 | int regno1 = REGNO (op1) + subreg_word1; | |
1834 | ||
1835 | if (FP_REG_P (regno1)) | |
1836 | ret = "s.d\t%1,%0"; | |
1837 | ||
147255d8 JW |
1838 | else if (TARGET_64BIT) |
1839 | { | |
1840 | #ifdef TARGET_FP_CALL_32 | |
1841 | if (FP_CALL_GP_REG_P (regno1)) | |
1842 | ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0"; | |
1843 | else | |
1844 | #endif | |
1845 | ret = "sd\t%1,%0"; | |
1846 | } | |
1847 | ||
cee98a59 MM |
1848 | else if (offsettable_address_p (1, DFmode, XEXP (op0, 0))) |
1849 | { | |
1850 | operands[2] = adj_offsettable_operand (op0, 4); | |
1851 | ret = "sw\t%1,%0\n\tsw\t%D1,%2"; | |
1852 | } | |
1853 | } | |
1854 | ||
147255d8 JW |
1855 | else if (((code1 == CONST_INT && INTVAL (op1) == 0) |
1856 | || (code1 == CONST_DOUBLE | |
1857 | && op1 == CONST0_RTX (GET_MODE (op1)))) | |
1858 | && (TARGET_64BIT | |
1859 | || offsettable_address_p (1, DFmode, XEXP (op0, 0)))) | |
cee98a59 | 1860 | { |
147255d8 | 1861 | if (TARGET_64BIT) |
cee98a59 MM |
1862 | ret = "sd\t%.,%0"; |
1863 | else | |
1864 | { | |
1865 | operands[2] = adj_offsettable_operand (op0, 4); | |
1866 | ret = "sw\t%.,%0\n\tsw\t%.,%2"; | |
1867 | } | |
1868 | } | |
1869 | ||
1870 | if (TARGET_STATS) | |
1871 | mips_count_memory_refs (op0, 2); | |
1872 | ||
1873 | if (ret != (char *)0 && MEM_VOLATILE_P (op0)) | |
1874 | { | |
1875 | int i = strlen (ret); | |
1876 | if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) | |
1877 | abort (); | |
1878 | ||
1879 | sprintf (volatile_buffer, "%%{%s%%}", ret); | |
1880 | ret = volatile_buffer; | |
1881 | } | |
1882 | } | |
1883 | ||
1884 | if (ret == (char *)0) | |
1885 | { | |
1886 | abort_with_insn (insn, "Bad move"); | |
1887 | return 0; | |
1888 | } | |
1889 | ||
1890 | if (delay != DELAY_NONE) | |
1891 | return mips_fill_delay_slot (ret, delay, operands, insn); | |
1892 | ||
1893 | return ret; | |
1894 | } | |
1895 | ||
1896 | \f | |
1897 | /* Provide the costs of an addressing mode that contains ADDR. | |
c831afd5 | 1898 | If ADDR is not a valid address, its cost is irrelevant. */ |
cee98a59 MM |
1899 | |
1900 | int | |
1901 | mips_address_cost (addr) | |
1902 | rtx addr; | |
1903 | { | |
cee98a59 MM |
1904 | switch (GET_CODE (addr)) |
1905 | { | |
0fb5ac6f MM |
1906 | default: |
1907 | break; | |
1908 | ||
cee98a59 | 1909 | case LO_SUM: |
cee98a59 MM |
1910 | return 1; |
1911 | ||
1912 | case LABEL_REF: | |
1913 | return 2; | |
1914 | ||
1915 | case CONST: | |
c831afd5 MM |
1916 | { |
1917 | rtx offset = const0_rtx; | |
147255d8 | 1918 | addr = eliminate_constant_term (XEXP (addr, 0), &offset); |
c831afd5 MM |
1919 | if (GET_CODE (addr) == LABEL_REF) |
1920 | return 2; | |
cee98a59 | 1921 | |
c831afd5 MM |
1922 | if (GET_CODE (addr) != SYMBOL_REF) |
1923 | return 4; | |
cee98a59 | 1924 | |
147255d8 | 1925 | if (! SMALL_INT (offset)) |
c831afd5 MM |
1926 | return 2; |
1927 | } | |
cee98a59 MM |
1928 | /* fall through */ |
1929 | ||
1930 | case SYMBOL_REF: | |
1931 | return SYMBOL_REF_FLAG (addr) ? 1 : 2; | |
1932 | ||
1933 | case PLUS: | |
1934 | { | |
1935 | register rtx plus0 = XEXP (addr, 0); | |
1936 | register rtx plus1 = XEXP (addr, 1); | |
1937 | ||
1938 | if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) | |
1939 | { | |
1940 | plus0 = XEXP (addr, 1); | |
1941 | plus1 = XEXP (addr, 0); | |
1942 | } | |
1943 | ||
1944 | if (GET_CODE (plus0) != REG) | |
1945 | break; | |
1946 | ||
1947 | switch (GET_CODE (plus1)) | |
1948 | { | |
0fb5ac6f MM |
1949 | default: |
1950 | break; | |
1951 | ||
cee98a59 | 1952 | case CONST_INT: |
147255d8 | 1953 | return (SMALL_INT (plus1) ? 1 : 2); |
cee98a59 MM |
1954 | |
1955 | case CONST: | |
1956 | case SYMBOL_REF: | |
1957 | case LABEL_REF: | |
1958 | case HIGH: | |
1959 | case LO_SUM: | |
1960 | return mips_address_cost (plus1) + 1; | |
1961 | } | |
1962 | } | |
1963 | } | |
1964 | ||
1965 | return 4; | |
1966 | } | |
1967 | ||
508a48d1 JW |
1968 | /* Return true if X is an address which needs a temporary register when |
1969 | reloaded while generating PIC code. */ | |
1970 | ||
1971 | int | |
1972 | pic_address_needs_scratch (x) | |
1973 | rtx x; | |
1974 | { | |
1975 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ | |
1976 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
1977 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1978 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1979 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
1980 | return 1; | |
1981 | ||
1982 | return 0; | |
1983 | } | |
34b650b3 MM |
1984 | \f |
1985 | /* Make normal rtx_code into something we can index from an array */ | |
1986 | ||
1987 | static enum internal_test | |
1988 | map_test_to_internal_test (test_code) | |
1989 | enum rtx_code test_code; | |
1990 | { | |
1991 | enum internal_test test = ITEST_MAX; | |
1992 | ||
1993 | switch (test_code) | |
1994 | { | |
0fb5ac6f | 1995 | default: break; |
34b650b3 MM |
1996 | case EQ: test = ITEST_EQ; break; |
1997 | case NE: test = ITEST_NE; break; | |
1998 | case GT: test = ITEST_GT; break; | |
1999 | case GE: test = ITEST_GE; break; | |
2000 | case LT: test = ITEST_LT; break; | |
2001 | case LE: test = ITEST_LE; break; | |
2002 | case GTU: test = ITEST_GTU; break; | |
2003 | case GEU: test = ITEST_GEU; break; | |
2004 | case LTU: test = ITEST_LTU; break; | |
2005 | case LEU: test = ITEST_LEU; break; | |
2006 | } | |
2007 | ||
2008 | return test; | |
2009 | } | |
2010 | ||
2011 | \f | |
2012 | /* Generate the code to compare two integer values. The return value is: | |
2013 | (reg:SI xx) The pseudo register the comparison is in | |
147255d8 JW |
2014 | (rtx)0 No register, generate a simple branch. |
2015 | ||
2016 | ??? This is called with result nonzero by the Scond patterns in | |
2017 | mips.md. These patterns are called with a target in the mode of | |
2018 | the Scond instruction pattern. Since this must be a constant, we | |
2019 | must use SImode. This means that if RESULT is non-zero, it will | |
2020 | always be an SImode register, even if TARGET_64BIT is true. We | |
2021 | cope with this by calling convert_move rather than emit_move_insn. | |
2022 | This will sometimes lead to an unnecessary extension of the result; | |
2023 | for example: | |
2024 | ||
2025 | long long | |
2026 | foo (long long i) | |
2027 | { | |
2028 | return i < 5; | |
2029 | } | |
2030 | ||
2031 | */ | |
34b650b3 MM |
2032 | |
2033 | rtx | |
2034 | gen_int_relational (test_code, result, cmp0, cmp1, p_invert) | |
2035 | enum rtx_code test_code; /* relational test (EQ, etc) */ | |
2036 | rtx result; /* result to store comp. or 0 if branch */ | |
2037 | rtx cmp0; /* first operand to compare */ | |
2038 | rtx cmp1; /* second operand to compare */ | |
2039 | int *p_invert; /* NULL or ptr to hold whether branch needs */ | |
2296cba3 | 2040 | /* to reverse its test */ |
34b650b3 MM |
2041 | { |
2042 | struct cmp_info { | |
2043 | enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */ | |
2044 | int const_low; /* low bound of constant we can accept */ | |
2045 | int const_high; /* high bound of constant we can accept */ | |
2046 | int const_add; /* constant to add (convert LE -> LT) */ | |
2047 | int reverse_regs; /* reverse registers in test */ | |
2048 | int invert_const; /* != 0 if invert value if cmp1 is constant */ | |
2049 | int invert_reg; /* != 0 if invert value if cmp1 is register */ | |
55f8a64c | 2050 | int unsignedp; /* != 0 for unsigned comparisons. */ |
34b650b3 MM |
2051 | }; |
2052 | ||
2053 | static struct cmp_info info[ (int)ITEST_MAX ] = { | |
2054 | ||
55f8a64c RS |
2055 | { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */ |
2056 | { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */ | |
2057 | { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */ | |
2058 | { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */ | |
2059 | { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */ | |
2060 | { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */ | |
2061 | { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */ | |
2062 | { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */ | |
2063 | { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */ | |
2064 | { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */ | |
34b650b3 MM |
2065 | }; |
2066 | ||
2067 | enum internal_test test; | |
147255d8 | 2068 | enum machine_mode mode; |
34b650b3 MM |
2069 | struct cmp_info *p_info; |
2070 | int branch_p; | |
2071 | int eqne_p; | |
2072 | int invert; | |
2073 | rtx reg; | |
2074 | rtx reg2; | |
2075 | ||
2076 | test = map_test_to_internal_test (test_code); | |
2077 | if (test == ITEST_MAX) | |
2078 | abort (); | |
2079 | ||
2080 | p_info = &info[ (int)test ]; | |
2081 | eqne_p = (p_info->test_code == XOR); | |
2082 | ||
147255d8 JW |
2083 | mode = GET_MODE (cmp0); |
2084 | if (mode == VOIDmode) | |
2085 | mode = GET_MODE (cmp1); | |
2086 | ||
34b650b3 MM |
2087 | /* Eliminate simple branches */ |
2088 | branch_p = (result == (rtx)0); | |
2089 | if (branch_p) | |
2090 | { | |
2091 | if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG) | |
2092 | { | |
2093 | /* Comparisons against zero are simple branches */ | |
2094 | if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0) | |
2095 | return (rtx)0; | |
2096 | ||
2097 | /* Test for beq/bne. */ | |
2098 | if (eqne_p) | |
2099 | return (rtx)0; | |
2100 | } | |
2101 | ||
2296cba3 | 2102 | /* allocate a pseudo to calculate the value in. */ |
147255d8 | 2103 | result = gen_reg_rtx (mode); |
34b650b3 MM |
2104 | } |
2105 | ||
2106 | /* Make sure we can handle any constants given to us. */ | |
2107 | if (GET_CODE (cmp0) == CONST_INT) | |
147255d8 | 2108 | cmp0 = force_reg (mode, cmp0); |
34b650b3 MM |
2109 | |
2110 | if (GET_CODE (cmp1) == CONST_INT) | |
2111 | { | |
85f5e2b6 | 2112 | HOST_WIDE_INT value = INTVAL (cmp1); |
147255d8 JW |
2113 | if (value < p_info->const_low |
2114 | || value > p_info->const_high | |
2115 | /* ??? Why? And why wasn't the similar code below modified too? */ | |
2116 | || (TARGET_64BIT | |
2117 | && HOST_BITS_PER_WIDE_INT < 64 | |
2118 | && p_info->const_add != 0 | |
2119 | && ((p_info->unsignedp | |
2120 | ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add) | |
2121 | > INTVAL (cmp1)) | |
2122 | : (value + p_info->const_add) > INTVAL (cmp1)) | |
2123 | != (p_info->const_add > 0)))) | |
2124 | cmp1 = force_reg (mode, cmp1); | |
34b650b3 MM |
2125 | } |
2126 | ||
2127 | /* See if we need to invert the result. */ | |
2128 | invert = (GET_CODE (cmp1) == CONST_INT) | |
2129 | ? p_info->invert_const | |
2130 | : p_info->invert_reg; | |
2131 | ||
2132 | if (p_invert != (int *)0) | |
2133 | { | |
2134 | *p_invert = invert; | |
2135 | invert = FALSE; | |
2136 | } | |
2137 | ||
2138 | /* Comparison to constants, may involve adding 1 to change a LT into LE. | |
2139 | Comparison between two registers, may involve switching operands. */ | |
2140 | if (GET_CODE (cmp1) == CONST_INT) | |
2141 | { | |
2142 | if (p_info->const_add != 0) | |
55f8a64c RS |
2143 | { |
2144 | HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add; | |
2145 | /* If modification of cmp1 caused overflow, | |
2146 | we would get the wrong answer if we follow the usual path; | |
4db7b4ce | 2147 | thus, x > 0xffffffffU would turn into x > 0U. */ |
55f8a64c RS |
2148 | if ((p_info->unsignedp |
2149 | ? (unsigned HOST_WIDE_INT) new > INTVAL (cmp1) | |
2150 | : new > INTVAL (cmp1)) | |
2151 | != (p_info->const_add > 0)) | |
d40bb52a RS |
2152 | { |
2153 | /* This test is always true, but if INVERT is true then | |
2154 | the result of the test needs to be inverted so 0 should | |
2155 | be returned instead. */ | |
2156 | emit_move_insn (result, invert ? const0_rtx : const_true_rtx); | |
2157 | return result; | |
2158 | } | |
55f8a64c RS |
2159 | else |
2160 | cmp1 = GEN_INT (new); | |
2161 | } | |
34b650b3 MM |
2162 | } |
2163 | else if (p_info->reverse_regs) | |
2164 | { | |
2165 | rtx temp = cmp0; | |
2166 | cmp0 = cmp1; | |
2167 | cmp1 = temp; | |
2168 | } | |
2169 | ||
34b650b3 | 2170 | if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0) |
bbdb5552 MM |
2171 | reg = cmp0; |
2172 | else | |
2173 | { | |
147255d8 JW |
2174 | reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result; |
2175 | convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0); | |
bbdb5552 MM |
2176 | } |
2177 | ||
2178 | if (test == ITEST_NE) | |
34b650b3 | 2179 | { |
147255d8 | 2180 | convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0); |
34b650b3 MM |
2181 | invert = FALSE; |
2182 | } | |
2183 | ||
bbdb5552 | 2184 | else if (test == ITEST_EQ) |
34b650b3 | 2185 | { |
147255d8 JW |
2186 | reg2 = (invert) ? gen_reg_rtx (mode) : result; |
2187 | convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0); | |
34b650b3 MM |
2188 | reg = reg2; |
2189 | } | |
2190 | ||
2191 | if (invert) | |
147255d8 | 2192 | convert_move (result, gen_rtx (XOR, mode, reg, const1_rtx), 0); |
34b650b3 MM |
2193 | |
2194 | return result; | |
2195 | } | |
2196 | ||
cee98a59 MM |
2197 | \f |
2198 | /* Emit the common code for doing conditional branches. | |
2199 | operand[0] is the label to jump to. | |
147255d8 | 2200 | The comparison operands are saved away by cmp{si,di,sf,df}. */ |
cee98a59 MM |
2201 | |
2202 | void | |
2203 | gen_conditional_branch (operands, test_code) | |
2204 | rtx operands[]; | |
2205 | enum rtx_code test_code; | |
2206 | { | |
b8eb88d0 ILT |
2207 | enum cmp_type type = branch_type; |
2208 | rtx cmp0 = branch_cmp[0]; | |
2209 | rtx cmp1 = branch_cmp[1]; | |
cee98a59 | 2210 | enum machine_mode mode; |
b8eb88d0 ILT |
2211 | rtx reg; |
2212 | int invert; | |
2213 | rtx label1, label2; | |
cee98a59 | 2214 | |
147255d8 | 2215 | switch (type) |
cee98a59 MM |
2216 | { |
2217 | default: | |
b8eb88d0 | 2218 | abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test"); |
cee98a59 MM |
2219 | |
2220 | case CMP_SI: | |
147255d8 | 2221 | case CMP_DI: |
b8eb88d0 ILT |
2222 | mode = type == CMP_SI ? SImode : DImode; |
2223 | invert = FALSE; | |
2224 | reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert); | |
2225 | if (reg) | |
cee98a59 | 2226 | { |
34b650b3 MM |
2227 | cmp0 = reg; |
2228 | cmp1 = const0_rtx; | |
2229 | test_code = NE; | |
cee98a59 | 2230 | } |
34b650b3 | 2231 | else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0) |
b8eb88d0 ILT |
2232 | { |
2233 | /* We don't want to build a comparison against a non-zero | |
2234 | constant. */ | |
2235 | cmp1 = force_reg (mode, cmp1); | |
2236 | } | |
cee98a59 MM |
2237 | break; |
2238 | ||
cee98a59 | 2239 | case CMP_SF: |
b8eb88d0 ILT |
2240 | case CMP_DF: |
2241 | if (mips_isa < 4) | |
2242 | reg = gen_rtx (REG, CCmode, FPSW_REGNUM); | |
2243 | else | |
2244 | reg = gen_reg_rtx (CCmode); | |
2245 | ||
2246 | /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result == | |
2247 | 0 in the instruction built below. The MIPS FPU handles | |
2248 | inequality testing by testing for equality and looking for a | |
2249 | false result. */ | |
2250 | emit_insn (gen_rtx (SET, VOIDmode, | |
2251 | reg, | |
2252 | gen_rtx (test_code == NE ? EQ : test_code, | |
2253 | CCmode, cmp0, cmp1))); | |
2254 | ||
2255 | test_code = test_code == NE ? EQ : NE; | |
2256 | mode = CCmode; | |
2257 | cmp0 = reg; | |
2258 | cmp1 = const0_rtx; | |
2259 | invert = FALSE; | |
cee98a59 MM |
2260 | break; |
2261 | } | |
85f5e2b6 | 2262 | |
b8eb88d0 ILT |
2263 | /* Generate the branch. */ |
2264 | ||
2265 | label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]); | |
2266 | label2 = pc_rtx; | |
2267 | ||
34b650b3 MM |
2268 | if (invert) |
2269 | { | |
2270 | label2 = label1; | |
2271 | label1 = pc_rtx; | |
2272 | } | |
2273 | ||
cee98a59 MM |
2274 | emit_jump_insn (gen_rtx (SET, VOIDmode, |
2275 | pc_rtx, | |
2276 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
34b650b3 MM |
2277 | gen_rtx (test_code, mode, cmp0, cmp1), |
2278 | label1, | |
2279 | label2))); | |
b8eb88d0 | 2280 | } |
34b650b3 | 2281 | |
b8eb88d0 ILT |
2282 | /* Emit the common code for conditional moves. OPERANDS is the array |
2283 | of operands passed to the conditional move defined_expand. */ | |
cee98a59 | 2284 | |
b8eb88d0 ILT |
2285 | void |
2286 | gen_conditional_move (operands) | |
2287 | rtx *operands; | |
2288 | { | |
2289 | rtx op0 = branch_cmp[0]; | |
2290 | rtx op1 = branch_cmp[1]; | |
2291 | enum machine_mode mode = GET_MODE (branch_cmp[0]); | |
2292 | enum rtx_code cmp_code = GET_CODE (operands[1]); | |
2293 | enum rtx_code move_code = NE; | |
2294 | enum machine_mode op_mode = GET_MODE (operands[0]); | |
2295 | enum machine_mode cmp_mode; | |
2296 | rtx cmp_reg; | |
2297 | ||
2298 | if (GET_MODE_CLASS (mode) != MODE_FLOAT) | |
2299 | { | |
2300 | switch (cmp_code) | |
2301 | { | |
2302 | case EQ: | |
2303 | cmp_code = XOR; | |
2304 | move_code = EQ; | |
2305 | break; | |
2306 | case NE: | |
2307 | cmp_code = XOR; | |
2308 | break; | |
2309 | case LT: | |
2310 | break; | |
2311 | case GE: | |
2312 | cmp_code = LT; | |
2313 | move_code = EQ; | |
2314 | break; | |
2315 | case GT: | |
2316 | cmp_code = LT; | |
2317 | op0 = force_reg (mode, branch_cmp[1]); | |
2318 | op1 = branch_cmp[0]; | |
2319 | break; | |
2320 | case LE: | |
2321 | cmp_code = LT; | |
2322 | op0 = force_reg (mode, branch_cmp[1]); | |
2323 | op1 = branch_cmp[0]; | |
2324 | move_code = EQ; | |
2325 | break; | |
2326 | case LTU: | |
2327 | break; | |
2328 | case GEU: | |
2329 | cmp_code = LTU; | |
2330 | move_code = EQ; | |
2331 | break; | |
2332 | case GTU: | |
2333 | cmp_code = LTU; | |
2334 | op0 = force_reg (mode, branch_cmp[1]); | |
2335 | op1 = branch_cmp[0]; | |
2336 | break; | |
2337 | case LEU: | |
2338 | cmp_code = LTU; | |
2339 | op0 = force_reg (mode, branch_cmp[1]); | |
2340 | op1 = branch_cmp[0]; | |
2341 | move_code = EQ; | |
2342 | break; | |
2343 | default: | |
2344 | abort (); | |
2345 | } | |
2346 | } | |
2347 | else | |
2348 | { | |
2349 | if (cmp_code == NE) | |
2350 | { | |
2351 | cmp_code = EQ; | |
2352 | move_code = EQ; | |
2353 | } | |
2354 | } | |
2355 | ||
2356 | if (mode == SImode || mode == DImode) | |
2357 | cmp_mode = mode; | |
2358 | else if (mode == SFmode || mode == DFmode) | |
2359 | cmp_mode = CCmode; | |
2360 | else | |
2361 | abort (); | |
cee98a59 | 2362 | |
b8eb88d0 ILT |
2363 | cmp_reg = gen_reg_rtx (cmp_mode); |
2364 | emit_insn (gen_rtx (SET, cmp_mode, | |
2365 | cmp_reg, | |
2366 | gen_rtx (cmp_code, cmp_mode, op0, op1))); | |
2367 | emit_insn (gen_rtx (SET, op_mode, | |
2368 | operands[0], | |
2369 | gen_rtx (IF_THEN_ELSE, op_mode, | |
2370 | gen_rtx (move_code, VOIDmode, | |
2371 | cmp_reg, | |
2372 | CONST0_RTX (SImode)), | |
2373 | operands[2], | |
2374 | operands[3]))); | |
2375 | } | |
cee98a59 MM |
2376 | \f |
2377 | /* Write a loop to move a constant number of bytes. Generate load/stores as follows: | |
2378 | ||
2379 | do { | |
2380 | temp1 = src[0]; | |
2381 | temp2 = src[1]; | |
2382 | ... | |
2383 | temp<last> = src[MAX_MOVE_REGS-1]; | |
cee98a59 MM |
2384 | dest[0] = temp1; |
2385 | dest[1] = temp2; | |
2386 | ... | |
2387 | dest[MAX_MOVE_REGS-1] = temp<last>; | |
842eb20e | 2388 | src += MAX_MOVE_REGS; |
cee98a59 MM |
2389 | dest += MAX_MOVE_REGS; |
2390 | } while (src != final); | |
2391 | ||
2392 | This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp | |
2393 | registers are needed. | |
2394 | ||
2395 | Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3 | |
2396 | cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every | |
2397 | (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */ | |
2398 | ||
2399 | #define MAX_MOVE_REGS 4 | |
2400 | #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD) | |
2401 | ||
2402 | static void | |
7cabe29a | 2403 | block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src) |
cee98a59 MM |
2404 | rtx dest_reg; /* register holding destination address */ |
2405 | rtx src_reg; /* register holding source address */ | |
2406 | int bytes; /* # bytes to move */ | |
2407 | int align; /* alignment */ | |
7cabe29a | 2408 | rtx orig_dest; /* original dest for change_address */ |
842eb20e | 2409 | rtx orig_src; /* original source for making a reg note */ |
cee98a59 | 2410 | { |
7cabe29a JW |
2411 | rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg); |
2412 | rtx src_mem = change_address (orig_src, BLKmode, src_reg); | |
0fb5ac6f | 2413 | rtx align_rtx = GEN_INT (align); |
cee98a59 MM |
2414 | rtx label; |
2415 | rtx final_src; | |
2416 | rtx bytes_rtx; | |
cee98a59 | 2417 | int leftover; |
cee98a59 MM |
2418 | |
2419 | if (bytes < 2*MAX_MOVE_BYTES) | |
2420 | abort (); | |
2421 | ||
2422 | leftover = bytes % MAX_MOVE_BYTES; | |
2423 | bytes -= leftover; | |
2424 | ||
2425 | label = gen_label_rtx (); | |
2426 | final_src = gen_reg_rtx (Pmode); | |
0fb5ac6f | 2427 | bytes_rtx = GEN_INT (bytes); |
cee98a59 MM |
2428 | |
2429 | if (bytes > 0x7fff) | |
2430 | { | |
147255d8 JW |
2431 | if (TARGET_LONG64) |
2432 | { | |
2433 | emit_insn (gen_movdi (final_src, bytes_rtx)); | |
2434 | emit_insn (gen_adddi3 (final_src, final_src, src_reg)); | |
2435 | } | |
2436 | else | |
2437 | { | |
2438 | emit_insn (gen_movsi (final_src, bytes_rtx)); | |
2439 | emit_insn (gen_addsi3 (final_src, final_src, src_reg)); | |
2440 | } | |
cee98a59 MM |
2441 | } |
2442 | else | |
147255d8 JW |
2443 | { |
2444 | if (TARGET_LONG64) | |
2445 | emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx)); | |
2446 | else | |
2447 | emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx)); | |
2448 | } | |
cee98a59 MM |
2449 | |
2450 | emit_label (label); | |
2451 | ||
0fb5ac6f | 2452 | bytes_rtx = GEN_INT (MAX_MOVE_BYTES); |
842eb20e | 2453 | emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx)); |
147255d8 JW |
2454 | if (TARGET_LONG64) |
2455 | { | |
2456 | emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx)); | |
2457 | emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx)); | |
2458 | emit_insn (gen_cmpdi (src_reg, final_src)); | |
2459 | } | |
2460 | else | |
2461 | { | |
2462 | emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx)); | |
2463 | emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx)); | |
2464 | emit_insn (gen_cmpsi (src_reg, final_src)); | |
2465 | } | |
cee98a59 MM |
2466 | emit_jump_insn (gen_bne (label)); |
2467 | ||
2468 | if (leftover) | |
842eb20e | 2469 | emit_insn (gen_movstrsi_internal (dest_mem, src_mem, |
0fb5ac6f | 2470 | GEN_INT (leftover), |
842eb20e | 2471 | align_rtx)); |
cee98a59 | 2472 | } |
cee98a59 MM |
2473 | \f |
2474 | /* Use a library function to move some bytes. */ | |
2475 | ||
2476 | static void | |
2477 | block_move_call (dest_reg, src_reg, bytes_rtx) | |
2478 | rtx dest_reg; | |
2479 | rtx src_reg; | |
2480 | rtx bytes_rtx; | |
2481 | { | |
147255d8 JW |
2482 | /* We want to pass the size as Pmode, which will normally be SImode |
2483 | but will be DImode if we are using 64 bit longs and pointers. */ | |
2484 | if (GET_MODE (bytes_rtx) != VOIDmode | |
2485 | && GET_MODE (bytes_rtx) != Pmode) | |
2486 | bytes_rtx = convert_to_mode (Pmode, bytes_rtx, TRUE); | |
2487 | ||
cee98a59 MM |
2488 | #ifdef TARGET_MEM_FUNCTIONS |
2489 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0, | |
2490 | VOIDmode, 3, | |
2491 | dest_reg, Pmode, | |
2492 | src_reg, Pmode, | |
e24b8776 JW |
2493 | convert_to_mode (TYPE_MODE (sizetype), bytes_rtx, |
2494 | TREE_UNSIGNED (sizetype)), | |
2495 | TYPE_MODE (sizetype)); | |
cee98a59 MM |
2496 | #else |
2497 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0, | |
2498 | VOIDmode, 3, | |
2499 | src_reg, Pmode, | |
2500 | dest_reg, Pmode, | |
d02f4ef7 | 2501 | convert_to_mode (TYPE_MODE (integer_type_node), |
e24b8776 JW |
2502 | bytes_rtx, |
2503 | TREE_UNSIGNED (integer_type_node)), | |
2504 | TYPE_MODE (integer_type_node)); | |
cee98a59 MM |
2505 | #endif |
2506 | } | |
2507 | ||
2508 | \f | |
2509 | /* Expand string/block move operations. | |
2510 | ||
2511 | operands[0] is the pointer to the destination. | |
2512 | operands[1] is the pointer to the source. | |
2513 | operands[2] is the number of bytes to move. | |
2514 | operands[3] is the alignment. */ | |
2515 | ||
2516 | void | |
2517 | expand_block_move (operands) | |
2518 | rtx operands[]; | |
2519 | { | |
2520 | rtx bytes_rtx = operands[2]; | |
842eb20e | 2521 | rtx align_rtx = operands[3]; |
cee98a59 MM |
2522 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
2523 | int bytes = (constp ? INTVAL (bytes_rtx) : 0); | |
842eb20e MM |
2524 | int align = INTVAL (align_rtx); |
2525 | rtx orig_src = operands[1]; | |
7cabe29a | 2526 | rtx orig_dest = operands[0]; |
cee98a59 MM |
2527 | rtx src_reg; |
2528 | rtx dest_reg; | |
2529 | ||
2530 | if (constp && bytes <= 0) | |
2531 | return; | |
2532 | ||
842eb20e MM |
2533 | if (align > UNITS_PER_WORD) |
2534 | align = UNITS_PER_WORD; | |
2535 | ||
cee98a59 | 2536 | /* Move the address into scratch registers. */ |
7cabe29a | 2537 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
842eb20e | 2538 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); |
cee98a59 MM |
2539 | |
2540 | if (TARGET_MEMCPY) | |
2541 | block_move_call (dest_reg, src_reg, bytes_rtx); | |
2542 | ||
2543 | else if (constp && bytes <= 2*MAX_MOVE_BYTES) | |
7cabe29a JW |
2544 | emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode, |
2545 | dest_reg), | |
ff18b63b RK |
2546 | change_address (orig_src, BLKmode, |
2547 | src_reg), | |
842eb20e | 2548 | bytes_rtx, align_rtx)); |
cee98a59 MM |
2549 | |
2550 | else if (constp && align >= UNITS_PER_WORD && optimize) | |
7cabe29a | 2551 | block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src); |
cee98a59 MM |
2552 | |
2553 | else if (constp && optimize) | |
2554 | { | |
2555 | /* If the alignment is not word aligned, generate a test at | |
2556 | runtime, to see whether things wound up aligned, and we | |
2557 | can use the faster lw/sw instead ulw/usw. */ | |
2558 | ||
2559 | rtx temp = gen_reg_rtx (Pmode); | |
2560 | rtx aligned_label = gen_label_rtx (); | |
2561 | rtx join_label = gen_label_rtx (); | |
2562 | int leftover = bytes % MAX_MOVE_BYTES; | |
2563 | ||
2564 | bytes -= leftover; | |
2565 | ||
147255d8 JW |
2566 | if (TARGET_LONG64) |
2567 | { | |
2568 | emit_insn (gen_iordi3 (temp, src_reg, dest_reg)); | |
2569 | emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1))); | |
2570 | emit_insn (gen_cmpdi (temp, const0_rtx)); | |
2571 | } | |
2572 | else | |
2573 | { | |
2574 | emit_insn (gen_iorsi3 (temp, src_reg, dest_reg)); | |
2575 | emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1))); | |
2576 | emit_insn (gen_cmpsi (temp, const0_rtx)); | |
2577 | } | |
cee98a59 MM |
2578 | emit_jump_insn (gen_beq (aligned_label)); |
2579 | ||
2580 | /* Unaligned loop. */ | |
7cabe29a | 2581 | block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src); |
cee98a59 MM |
2582 | emit_jump_insn (gen_jump (join_label)); |
2583 | emit_barrier (); | |
2584 | ||
2585 | /* Aligned loop. */ | |
2586 | emit_label (aligned_label); | |
7cabe29a JW |
2587 | block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest, |
2588 | orig_src); | |
cee98a59 MM |
2589 | emit_label (join_label); |
2590 | ||
2591 | /* Bytes at the end of the loop. */ | |
2592 | if (leftover) | |
7cabe29a JW |
2593 | emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode, |
2594 | dest_reg), | |
2595 | change_address (orig_src, BLKmode, | |
2596 | src_reg), | |
2597 | GEN_INT (leftover), | |
2598 | GEN_INT (align))); | |
cee98a59 MM |
2599 | } |
2600 | ||
2601 | else | |
2602 | block_move_call (dest_reg, src_reg, bytes_rtx); | |
2603 | } | |
2604 | ||
842eb20e MM |
2605 | \f |
2606 | /* Emit load/stores for a small constant block_move. | |
2607 | ||
2608 | operands[0] is the memory address of the destination. | |
2609 | operands[1] is the memory address of the source. | |
2610 | operands[2] is the number of bytes to move. | |
2611 | operands[3] is the alignment. | |
2612 | operands[4] is a temp register. | |
2613 | operands[5] is a temp register. | |
c4b9be8e MM |
2614 | ... |
2615 | operands[3+num_regs] is the last temp register. | |
2616 | ||
2617 | The block move type can be one of the following: | |
2618 | BLOCK_MOVE_NORMAL Do all of the block move. | |
2619 | BLOCK_MOVE_NOT_LAST Do all but the last store. | |
2620 | BLOCK_MOVE_LAST Do just the last store. */ | |
842eb20e MM |
2621 | |
2622 | char * | |
c4b9be8e | 2623 | output_block_move (insn, operands, num_regs, move_type) |
842eb20e MM |
2624 | rtx insn; |
2625 | rtx operands[]; | |
2626 | int num_regs; | |
c4b9be8e | 2627 | enum block_move_type move_type; |
842eb20e MM |
2628 | { |
2629 | rtx dest_reg = XEXP (operands[0], 0); | |
2630 | rtx src_reg = XEXP (operands[1], 0); | |
2631 | int bytes = INTVAL (operands[2]); | |
2632 | int align = INTVAL (operands[3]); | |
2633 | int num = 0; | |
2634 | int offset = 0; | |
0cebb05d | 2635 | int use_lwl_lwr = FALSE; |
c6f3187f | 2636 | int last_operand = num_regs+4; |
4bb89a8e | 2637 | int safe_regs = 4; |
842eb20e MM |
2638 | int i; |
2639 | rtx xoperands[10]; | |
2640 | ||
2641 | struct { | |
2642 | char *load; /* load insn without nop */ | |
2643 | char *load_nop; /* load insn with trailing nop */ | |
2644 | char *store; /* store insn */ | |
c4b9be8e MM |
2645 | char *final; /* if last_store used: NULL or swr */ |
2646 | char *last_store; /* last store instruction */ | |
842eb20e MM |
2647 | int offset; /* current offset */ |
2648 | enum machine_mode mode; /* mode to use on (MEM) */ | |
2649 | } load_store[4]; | |
2650 | ||
c4b9be8e | 2651 | /* Detect a bug in GCC, where it can give us a register |
4bb89a8e MM |
2652 | the same as one of the addressing registers and reduce |
2653 | the number of registers available. */ | |
2654 | for (i = 4; | |
2655 | i < last_operand && safe_regs < (sizeof(xoperands) / sizeof(xoperands[0])); | |
2656 | i++) | |
c6f3187f | 2657 | { |
4bb89a8e MM |
2658 | if (!reg_mentioned_p (operands[i], operands[0]) |
2659 | && !reg_mentioned_p (operands[i], operands[1])) | |
2660 | ||
2661 | xoperands[safe_regs++] = operands[i]; | |
2662 | } | |
2663 | ||
2664 | if (safe_regs < last_operand) | |
2665 | { | |
2666 | xoperands[0] = operands[0]; | |
2667 | xoperands[1] = operands[1]; | |
2668 | xoperands[2] = operands[2]; | |
2669 | xoperands[3] = operands[3]; | |
2670 | return output_block_move (insn, xoperands, safe_regs-4, move_type); | |
c6f3187f RS |
2671 | } |
2672 | ||
842eb20e MM |
2673 | /* If we are given global or static addresses, and we would be |
2674 | emitting a few instructions, try to save time by using a | |
2675 | temporary register for the pointer. */ | |
a8136932 JW |
2676 | /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in |
2677 | an ldl/ldr instruction pair. We play it safe, and always move | |
2678 | constant addresses into registers when generating N32/N64 code, just | |
2679 | in case we might emit an unaligned load instruction. */ | |
2680 | if (num_regs > 2 && (bytes > 2*align || move_type != BLOCK_MOVE_NORMAL | |
2681 | || mips_abi == ABI_N32 || mips_abi == ABI_64)) | |
842eb20e MM |
2682 | { |
2683 | if (CONSTANT_P (src_reg)) | |
2684 | { | |
4e09f580 MM |
2685 | if (TARGET_STATS) |
2686 | mips_count_memory_refs (operands[1], 1); | |
2687 | ||
c4b9be8e MM |
2688 | src_reg = operands[ 3 + num_regs-- ]; |
2689 | if (move_type != BLOCK_MOVE_LAST) | |
2690 | { | |
2691 | xoperands[1] = operands[1]; | |
2692 | xoperands[0] = src_reg; | |
33563487 JW |
2693 | if (Pmode == DImode) |
2694 | output_asm_insn ("dla\t%0,%1", xoperands); | |
2695 | else | |
2696 | output_asm_insn ("la\t%0,%1", xoperands); | |
c4b9be8e | 2697 | } |
842eb20e MM |
2698 | } |
2699 | ||
2700 | if (CONSTANT_P (dest_reg)) | |
2701 | { | |
4e09f580 MM |
2702 | if (TARGET_STATS) |
2703 | mips_count_memory_refs (operands[0], 1); | |
2704 | ||
c4b9be8e MM |
2705 | dest_reg = operands[ 3 + num_regs-- ]; |
2706 | if (move_type != BLOCK_MOVE_LAST) | |
2707 | { | |
2708 | xoperands[1] = operands[0]; | |
2709 | xoperands[0] = dest_reg; | |
33563487 JW |
2710 | if (Pmode == DImode) |
2711 | output_asm_insn ("dla\t%0,%1", xoperands); | |
2712 | else | |
2713 | output_asm_insn ("la\t%0,%1", xoperands); | |
c4b9be8e | 2714 | } |
842eb20e MM |
2715 | } |
2716 | } | |
2717 | ||
910628b8 JW |
2718 | /* ??? We really shouldn't get any LO_SUM addresses here, because they |
2719 | are not offsettable, however, offsettable_address_p says they are | |
2720 | offsettable. I think this is a bug in offsettable_address_p. | |
2721 | For expediency, we fix this by just loading the address into a register | |
2722 | if we happen to get one. */ | |
2723 | ||
2724 | if (GET_CODE (src_reg) == LO_SUM) | |
2725 | { | |
2726 | src_reg = operands[ 3 + num_regs-- ]; | |
2727 | if (move_type != BLOCK_MOVE_LAST) | |
2728 | { | |
2729 | xoperands[2] = XEXP (XEXP (operands[1], 0), 1); | |
2730 | xoperands[1] = XEXP (XEXP (operands[1], 0), 0); | |
2731 | xoperands[0] = src_reg; | |
2732 | if (Pmode == DImode) | |
2733 | output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands); | |
2734 | else | |
2735 | output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands); | |
2736 | } | |
2737 | } | |
2738 | ||
2739 | if (GET_CODE (dest_reg) == LO_SUM) | |
2740 | { | |
2741 | dest_reg = operands[ 3 + num_regs-- ]; | |
2742 | if (move_type != BLOCK_MOVE_LAST) | |
2743 | { | |
2744 | xoperands[2] = XEXP (XEXP (operands[0], 0), 1); | |
2745 | xoperands[1] = XEXP (XEXP (operands[0], 0), 0); | |
2746 | xoperands[0] = dest_reg; | |
2747 | if (Pmode == DImode) | |
2748 | output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands); | |
2749 | else | |
2750 | output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands); | |
2751 | } | |
2752 | } | |
2753 | ||
842eb20e MM |
2754 | if (num_regs > (sizeof (load_store) / sizeof (load_store[0]))) |
2755 | num_regs = (sizeof (load_store) / sizeof (load_store[0])); | |
2756 | ||
2757 | else if (num_regs < 1) | |
4bb89a8e | 2758 | abort_with_insn (insn, "Cannot do block move, not enough scratch registers"); |
842eb20e | 2759 | |
842eb20e MM |
2760 | while (bytes > 0) |
2761 | { | |
2762 | load_store[num].offset = offset; | |
2763 | ||
147255d8 JW |
2764 | if (TARGET_64BIT && bytes >= 8 && align >= 8) |
2765 | { | |
2766 | load_store[num].load = "ld\t%0,%1"; | |
2767 | load_store[num].load_nop = "ld\t%0,%1%#"; | |
2768 | load_store[num].store = "sd\t%0,%1"; | |
2769 | load_store[num].last_store = "sd\t%0,%1"; | |
2770 | load_store[num].final = (char *)0; | |
2771 | load_store[num].mode = DImode; | |
2772 | offset += 8; | |
2773 | bytes -= 8; | |
2774 | } | |
2775 | ||
147255d8 JW |
2776 | else if (TARGET_64BIT && bytes >= 8) |
2777 | { | |
96abdcb1 ILT |
2778 | if (BYTES_BIG_ENDIAN) |
2779 | { | |
2780 | load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2"; | |
2781 | load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#"; | |
2782 | load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2"; | |
2783 | load_store[num].last_store = "sdr\t%0,%2"; | |
2784 | load_store[num].final = "sdl\t%0,%1"; | |
2785 | } | |
2786 | else | |
2787 | { | |
2788 | load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1"; | |
2789 | load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#"; | |
2790 | load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1"; | |
2791 | load_store[num].last_store = "sdr\t%0,%1"; | |
2792 | load_store[num].final = "sdl\t%0,%2"; | |
2793 | } | |
147255d8 JW |
2794 | load_store[num].mode = DImode; |
2795 | offset += 8; | |
2796 | bytes -= 8; | |
2797 | use_lwl_lwr = TRUE; | |
2798 | } | |
2799 | ||
2800 | else if (bytes >= 4 && align >= 4) | |
842eb20e | 2801 | { |
c4b9be8e MM |
2802 | load_store[num].load = "lw\t%0,%1"; |
2803 | load_store[num].load_nop = "lw\t%0,%1%#"; | |
2804 | load_store[num].store = "sw\t%0,%1"; | |
2805 | load_store[num].last_store = "sw\t%0,%1"; | |
2806 | load_store[num].final = (char *)0; | |
2807 | load_store[num].mode = SImode; | |
147255d8 JW |
2808 | offset += 4; |
2809 | bytes -= 4; | |
842eb20e MM |
2810 | } |
2811 | ||
147255d8 | 2812 | else if (bytes >= 4) |
0cebb05d | 2813 | { |
96abdcb1 ILT |
2814 | if (BYTES_BIG_ENDIAN) |
2815 | { | |
2816 | load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2"; | |
2817 | load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#"; | |
2818 | load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2"; | |
2819 | load_store[num].last_store = "swr\t%0,%2"; | |
2820 | load_store[num].final = "swl\t%0,%1"; | |
2821 | } | |
2822 | else | |
2823 | { | |
2824 | load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1"; | |
2825 | load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#"; | |
2826 | load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1"; | |
2827 | load_store[num].last_store = "swr\t%0,%1"; | |
2828 | load_store[num].final = "swl\t%0,%2"; | |
2829 | } | |
0cebb05d | 2830 | load_store[num].mode = SImode; |
147255d8 JW |
2831 | offset += 4; |
2832 | bytes -= 4; | |
0cebb05d MM |
2833 | use_lwl_lwr = TRUE; |
2834 | } | |
2835 | ||
147255d8 | 2836 | else if (bytes >= 2 && align >= 2) |
842eb20e | 2837 | { |
c4b9be8e MM |
2838 | load_store[num].load = "lh\t%0,%1"; |
2839 | load_store[num].load_nop = "lh\t%0,%1%#"; | |
2840 | load_store[num].store = "sh\t%0,%1"; | |
2841 | load_store[num].last_store = "sh\t%0,%1"; | |
2842 | load_store[num].final = (char *)0; | |
c4b9be8e | 2843 | load_store[num].mode = HImode; |
147255d8 JW |
2844 | offset += 2; |
2845 | bytes -= 2; | |
842eb20e MM |
2846 | } |
2847 | ||
2848 | else | |
2849 | { | |
c4b9be8e MM |
2850 | load_store[num].load = "lb\t%0,%1"; |
2851 | load_store[num].load_nop = "lb\t%0,%1%#"; | |
2852 | load_store[num].store = "sb\t%0,%1"; | |
2853 | load_store[num].last_store = "sb\t%0,%1"; | |
2854 | load_store[num].final = (char *)0; | |
2855 | load_store[num].mode = QImode; | |
842eb20e MM |
2856 | offset++; |
2857 | bytes--; | |
2858 | } | |
2859 | ||
c4b9be8e | 2860 | if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) |
4e09f580 | 2861 | { |
c4b9be8e MM |
2862 | dslots_load_total++; |
2863 | dslots_load_filled++; | |
2864 | ||
4e09f580 MM |
2865 | if (CONSTANT_P (src_reg)) |
2866 | mips_count_memory_refs (src_reg, 1); | |
2867 | ||
2868 | if (CONSTANT_P (dest_reg)) | |
2869 | mips_count_memory_refs (dest_reg, 1); | |
2870 | } | |
2871 | ||
842eb20e MM |
2872 | /* Emit load/stores now if we have run out of registers or are |
2873 | at the end of the move. */ | |
2874 | ||
4e09f580 | 2875 | if (++num == num_regs || bytes == 0) |
842eb20e MM |
2876 | { |
2877 | /* If only load/store, we need a NOP after the load. */ | |
2878 | if (num == 1) | |
4e09f580 MM |
2879 | { |
2880 | load_store[0].load = load_store[0].load_nop; | |
c4b9be8e MM |
2881 | if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) |
2882 | dslots_load_filled--; | |
4e09f580 | 2883 | } |
842eb20e | 2884 | |
c4b9be8e | 2885 | if (move_type != BLOCK_MOVE_LAST) |
842eb20e | 2886 | { |
c4b9be8e MM |
2887 | for (i = 0; i < num; i++) |
2888 | { | |
2889 | int offset; | |
0cebb05d | 2890 | |
c4b9be8e MM |
2891 | if (!operands[i+4]) |
2892 | abort (); | |
842eb20e | 2893 | |
c4b9be8e MM |
2894 | if (GET_MODE (operands[i+4]) != load_store[i].mode) |
2895 | operands[i+4] = gen_rtx (REG, load_store[i].mode, REGNO (operands[i+4])); | |
842eb20e | 2896 | |
c4b9be8e MM |
2897 | offset = load_store[i].offset; |
2898 | xoperands[0] = operands[i+4]; | |
2899 | xoperands[1] = gen_rtx (MEM, load_store[i].mode, | |
2900 | plus_constant (src_reg, offset)); | |
0cebb05d | 2901 | |
c4b9be8e | 2902 | if (use_lwl_lwr) |
147255d8 JW |
2903 | { |
2904 | int extra_offset; | |
2905 | extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1; | |
2906 | xoperands[2] = gen_rtx (MEM, load_store[i].mode, | |
2907 | plus_constant (src_reg, | |
2908 | extra_offset | |
2909 | + offset)); | |
2910 | } | |
0cebb05d | 2911 | |
c4b9be8e MM |
2912 | output_asm_insn (load_store[i].load, xoperands); |
2913 | } | |
842eb20e MM |
2914 | } |
2915 | ||
2916 | for (i = 0; i < num; i++) | |
2917 | { | |
c4b9be8e | 2918 | int last_p = (i == num-1 && bytes == 0); |
0cebb05d | 2919 | int offset = load_store[i].offset; |
c4b9be8e | 2920 | |
842eb20e MM |
2921 | xoperands[0] = operands[i+4]; |
2922 | xoperands[1] = gen_rtx (MEM, load_store[i].mode, | |
0cebb05d MM |
2923 | plus_constant (dest_reg, offset)); |
2924 | ||
2925 | ||
2926 | if (use_lwl_lwr) | |
147255d8 JW |
2927 | { |
2928 | int extra_offset; | |
2929 | extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1; | |
2930 | xoperands[2] = gen_rtx (MEM, load_store[i].mode, | |
2931 | plus_constant (dest_reg, | |
2932 | extra_offset | |
2933 | + offset)); | |
2934 | } | |
0cebb05d | 2935 | |
c4b9be8e MM |
2936 | if (move_type == BLOCK_MOVE_NORMAL) |
2937 | output_asm_insn (load_store[i].store, xoperands); | |
2938 | ||
2939 | else if (move_type == BLOCK_MOVE_NOT_LAST) | |
2940 | { | |
2941 | if (!last_p) | |
2942 | output_asm_insn (load_store[i].store, xoperands); | |
2943 | ||
2944 | else if (load_store[i].final != (char *)0) | |
2945 | output_asm_insn (load_store[i].final, xoperands); | |
2946 | } | |
2947 | ||
2948 | else if (last_p) | |
2949 | output_asm_insn (load_store[i].last_store, xoperands); | |
842eb20e MM |
2950 | } |
2951 | ||
2952 | num = 0; /* reset load_store */ | |
147255d8 | 2953 | use_lwl_lwr = FALSE; |
842eb20e MM |
2954 | } |
2955 | } | |
2956 | ||
842eb20e MM |
2957 | return ""; |
2958 | } | |
2959 | ||
cee98a59 MM |
2960 | \f |
2961 | /* Argument support functions. */ | |
2962 | ||
2963 | /* Initialize CUMULATIVE_ARGS for a function. */ | |
2964 | ||
2965 | void | |
2966 | init_cumulative_args (cum, fntype, libname) | |
2967 | CUMULATIVE_ARGS *cum; /* argument info to initialize */ | |
2968 | tree fntype; /* tree ptr for function decl */ | |
2969 | rtx libname; /* SYMBOL_REF of library name or 0 */ | |
2970 | { | |
3f1f8d8c | 2971 | static CUMULATIVE_ARGS zero_cum; |
cee98a59 MM |
2972 | tree param, next_param; |
2973 | ||
2974 | if (TARGET_DEBUG_E_MODE) | |
6cb6c3b3 MM |
2975 | { |
2976 | fprintf (stderr, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype); | |
2977 | if (!fntype) | |
2978 | fputc ('\n', stderr); | |
2979 | ||
2980 | else | |
2981 | { | |
2982 | tree ret_type = TREE_TYPE (fntype); | |
2983 | fprintf (stderr, ", fntype code = %s, ret code = %s\n", | |
2984 | tree_code_name[ (int)TREE_CODE (fntype) ], | |
2985 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
2986 | } | |
2987 | } | |
cee98a59 | 2988 | |
3f1f8d8c | 2989 | *cum = zero_cum; |
cee98a59 MM |
2990 | |
2991 | /* Determine if this function has variable arguments. This is | |
2992 | indicated by the last argument being 'void_type_mode' if there | |
2993 | are no variable arguments. The standard MIPS calling sequence | |
2994 | passes all arguments in the general purpose registers in this | |
2995 | case. */ | |
2996 | ||
2997 | for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0; | |
2998 | param != (tree)0; | |
2999 | param = next_param) | |
3000 | { | |
3001 | next_param = TREE_CHAIN (param); | |
3002 | if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node) | |
3003 | cum->gp_reg_found = 1; | |
3004 | } | |
cee98a59 MM |
3005 | } |
3006 | ||
3007 | /* Advance the argument to the next argument position. */ | |
3008 | ||
3009 | void | |
3010 | function_arg_advance (cum, mode, type, named) | |
3011 | CUMULATIVE_ARGS *cum; /* current arg information */ | |
3012 | enum machine_mode mode; /* current arg mode */ | |
3013 | tree type; /* type of the argument or 0 if lib support */ | |
0fb5ac6f | 3014 | int named; /* whether or not the argument was named */ |
cee98a59 MM |
3015 | { |
3016 | if (TARGET_DEBUG_E_MODE) | |
3017 | fprintf (stderr, | |
3f1f8d8c | 3018 | "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n", |
cee98a59 MM |
3019 | cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode), |
3020 | type, named); | |
3021 | ||
3022 | cum->arg_number++; | |
3023 | switch (mode) | |
3024 | { | |
b4b93495 | 3025 | case VOIDmode: |
cee98a59 MM |
3026 | break; |
3027 | ||
b4b93495 RS |
3028 | default: |
3029 | if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT | |
3030 | && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) | |
3031 | abort (); | |
3032 | cum->gp_reg_found = 1; | |
147255d8 JW |
3033 | cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) |
3034 | / UNITS_PER_WORD); | |
cee98a59 MM |
3035 | break; |
3036 | ||
3037 | case BLKmode: | |
3038 | cum->gp_reg_found = 1; | |
147255d8 JW |
3039 | cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) |
3040 | / UNITS_PER_WORD); | |
cee98a59 MM |
3041 | break; |
3042 | ||
3043 | case SFmode: | |
293a36eb ILT |
3044 | if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT) |
3045 | cum->fp_arg_words++; | |
3046 | else | |
3047 | cum->arg_words++; | |
cee98a59 MM |
3048 | break; |
3049 | ||
3050 | case DFmode: | |
293a36eb ILT |
3051 | if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT) |
3052 | cum->fp_arg_words += (TARGET_64BIT ? 1 : 2); | |
3053 | else | |
3054 | cum->arg_words += (TARGET_64BIT ? 1 : 2); | |
cee98a59 MM |
3055 | break; |
3056 | ||
3057 | case DImode: | |
3058 | cum->gp_reg_found = 1; | |
147255d8 | 3059 | cum->arg_words += (TARGET_64BIT ? 1 : 2); |
cee98a59 MM |
3060 | break; |
3061 | ||
3062 | case QImode: | |
3063 | case HImode: | |
3064 | case SImode: | |
3065 | cum->gp_reg_found = 1; | |
3066 | cum->arg_words++; | |
3067 | break; | |
3068 | } | |
3069 | } | |
3070 | ||
147255d8 JW |
3071 | /* Return an RTL expression containing the register for the given mode, |
3072 | or 0 if the argument is to be passed on the stack. */ | |
cee98a59 MM |
3073 | |
3074 | struct rtx_def * | |
3075 | function_arg (cum, mode, type, named) | |
3076 | CUMULATIVE_ARGS *cum; /* current arg information */ | |
3077 | enum machine_mode mode; /* current arg mode */ | |
3078 | tree type; /* type of the argument or 0 if lib support */ | |
3079 | int named; /* != 0 for normal args, == 0 for ... args */ | |
3080 | { | |
3f1f8d8c | 3081 | rtx ret; |
cee98a59 MM |
3082 | int regbase = -1; |
3083 | int bias = 0; | |
293a36eb | 3084 | int *arg_words = &cum->arg_words; |
3f1f8d8c MM |
3085 | int struct_p = ((type != (tree)0) |
3086 | && (TREE_CODE (type) == RECORD_TYPE | |
3087 | || TREE_CODE (type) == UNION_TYPE)); | |
cee98a59 MM |
3088 | |
3089 | if (TARGET_DEBUG_E_MODE) | |
3090 | fprintf (stderr, | |
3091 | "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ", | |
3092 | cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode), | |
3093 | type, named); | |
3094 | ||
293a36eb | 3095 | cum->last_arg_fp = 0; |
cee98a59 MM |
3096 | switch (mode) |
3097 | { | |
cee98a59 | 3098 | case SFmode: |
ade6c319 | 3099 | if (mips_abi == ABI_32) |
dc55be0e | 3100 | { |
33563487 JW |
3101 | if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT) |
3102 | regbase = GP_ARG_FIRST; | |
3103 | else | |
3104 | { | |
3105 | regbase = FP_ARG_FIRST; | |
3106 | /* If the first arg was a float in a floating point register, | |
3107 | then set bias to align this float arg properly. */ | |
3108 | if (cum->arg_words == 1) | |
3109 | bias = 1; | |
3110 | } | |
dc55be0e | 3111 | } |
293a36eb ILT |
3112 | else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT) |
3113 | { | |
3114 | if (! TARGET_64BIT) | |
3115 | cum->fp_arg_words += cum->fp_arg_words & 1; | |
3116 | cum->last_arg_fp = 1; | |
3117 | arg_words = &cum->fp_arg_words; | |
3118 | regbase = FP_ARG_FIRST; | |
3119 | } | |
33563487 JW |
3120 | else |
3121 | regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST); | |
cee98a59 MM |
3122 | break; |
3123 | ||
3124 | case DFmode: | |
147255d8 | 3125 | if (! TARGET_64BIT) |
293a36eb ILT |
3126 | { |
3127 | if (mips_abi == ABI_EABI | |
3128 | && ! TARGET_SOFT_FLOAT | |
3129 | && ! TARGET_SINGLE_FLOAT) | |
3130 | cum->fp_arg_words += cum->fp_arg_words & 1; | |
3131 | else | |
3132 | cum->arg_words += cum->arg_words & 1; | |
3133 | } | |
ade6c319 | 3134 | if (mips_abi == ABI_32) |
33563487 JW |
3135 | regbase = ((cum->gp_reg_found |
3136 | || TARGET_SOFT_FLOAT | |
3137 | || TARGET_SINGLE_FLOAT | |
3138 | || cum->arg_number >= 2) | |
3139 | ? GP_ARG_FIRST | |
3140 | : FP_ARG_FIRST); | |
293a36eb ILT |
3141 | else if (mips_abi == ABI_EABI |
3142 | && ! TARGET_SOFT_FLOAT | |
3143 | && ! TARGET_SINGLE_FLOAT) | |
3144 | { | |
3145 | cum->last_arg_fp = 1; | |
3146 | arg_words = &cum->fp_arg_words; | |
3147 | regbase = FP_ARG_FIRST; | |
3148 | } | |
33563487 JW |
3149 | else |
3150 | regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named | |
3151 | ? GP_ARG_FIRST : FP_ARG_FIRST); | |
cee98a59 MM |
3152 | break; |
3153 | ||
b4b93495 RS |
3154 | default: |
3155 | if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT | |
3156 | && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) | |
3157 | abort (); | |
3158 | ||
3159 | /* Drops through. */ | |
cee98a59 | 3160 | case BLKmode: |
147255d8 | 3161 | if (type != (tree)0 && TYPE_ALIGN (type) > BITS_PER_WORD |
293a36eb | 3162 | && ! TARGET_64BIT && mips_abi != ABI_EABI) |
df7fef57 | 3163 | cum->arg_words += (cum->arg_words & 1); |
df7fef57 MM |
3164 | regbase = GP_ARG_FIRST; |
3165 | break; | |
3166 | ||
3167 | case VOIDmode: | |
cee98a59 MM |
3168 | case QImode: |
3169 | case HImode: | |
3170 | case SImode: | |
3171 | regbase = GP_ARG_FIRST; | |
3172 | break; | |
3173 | ||
3174 | case DImode: | |
147255d8 JW |
3175 | if (! TARGET_64BIT) |
3176 | cum->arg_words += (cum->arg_words & 1); | |
cee98a59 MM |
3177 | regbase = GP_ARG_FIRST; |
3178 | } | |
3179 | ||
293a36eb | 3180 | if (*arg_words >= MAX_ARGS_IN_REGISTERS) |
cee98a59 MM |
3181 | { |
3182 | if (TARGET_DEBUG_E_MODE) | |
3f1f8d8c | 3183 | fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : ""); |
cee98a59 | 3184 | |
3f1f8d8c | 3185 | ret = (rtx)0; |
cee98a59 | 3186 | } |
3f1f8d8c MM |
3187 | else |
3188 | { | |
3189 | if (regbase == -1) | |
3190 | abort (); | |
cee98a59 | 3191 | |
a20b7b05 | 3192 | if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32 |
293a36eb ILT |
3193 | || mips_abi == ABI_EABI || ! named) |
3194 | ret = gen_rtx (REG, mode, regbase + *arg_words + bias); | |
a20b7b05 JW |
3195 | else |
3196 | { | |
3197 | /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the | |
3198 | structure contains a double in its entirety, then that 64 bit | |
3199 | chunk is passed in a floating point register. */ | |
3200 | tree field; | |
3201 | ||
3202 | /* First check to see if there is any such field. */ | |
3203 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
320aba9c JW |
3204 | if (TREE_CODE (field) == FIELD_DECL |
3205 | && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
a20b7b05 JW |
3206 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD |
3207 | && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) | |
3208 | % BITS_PER_WORD == 0)) | |
3209 | break; | |
3210 | ||
15039abe | 3211 | if (! field || mode == DFmode) |
293a36eb | 3212 | ret = gen_rtx (REG, mode, regbase + *arg_words + bias); |
a20b7b05 JW |
3213 | else |
3214 | { | |
3215 | /* Now handle the special case by returning a PARALLEL | |
3216 | indicating where each 64 bit chunk goes. */ | |
3217 | int chunks; | |
3218 | int bitpos; | |
3219 | int regno; | |
3220 | int i; | |
3221 | ||
3222 | /* ??? If this is a packed structure, then the last hunk won't | |
3223 | be 64 bits. */ | |
3224 | ||
3225 | /* ??? If this is a structure with a single double field, | |
3226 | it would be more convenient to return (REG:DI %fX) than | |
3227 | a parallel. However, we would have to modify the mips | |
3228 | backend to allow DImode values in fp registers. */ | |
3229 | ||
3230 | chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD; | |
293a36eb ILT |
3231 | if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS) |
3232 | chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias; | |
a20b7b05 JW |
3233 | |
3234 | /* assign_parms checks the mode of ENTRY_PARM, so we must | |
3235 | use the actual mode here. */ | |
3236 | ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks)); | |
3237 | ||
3238 | bitpos = 0; | |
293a36eb | 3239 | regno = regbase + *arg_words + bias; |
a20b7b05 JW |
3240 | field = TYPE_FIELDS (type); |
3241 | for (i = 0; i < chunks; i++) | |
3242 | { | |
3243 | rtx reg; | |
3244 | ||
3245 | for (; field; field = TREE_CHAIN (field)) | |
320aba9c JW |
3246 | if (TREE_CODE (field) == FIELD_DECL |
3247 | && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) | |
3248 | >= bitpos)) | |
a20b7b05 JW |
3249 | break; |
3250 | ||
3251 | if (field | |
3252 | && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos | |
3253 | && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
3254 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) | |
3255 | reg = gen_rtx (REG, DFmode, | |
3256 | regno + FP_ARG_FIRST - GP_ARG_FIRST); | |
3257 | else | |
3258 | reg = gen_rtx (REG, word_mode, regno); | |
3259 | ||
3260 | XVECEXP (ret, 0, i) = gen_rtx (EXPR_LIST, VOIDmode, reg, | |
3261 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
3262 | ||
3263 | bitpos += 64; | |
3264 | regno++; | |
3265 | } | |
3266 | } | |
3267 | } | |
cee98a59 | 3268 | |
3f1f8d8c | 3269 | if (TARGET_DEBUG_E_MODE) |
293a36eb | 3270 | fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias], |
3f1f8d8c MM |
3271 | struct_p ? ", [struct]" : ""); |
3272 | ||
3273 | /* The following is a hack in order to pass 1 byte structures | |
3274 | the same way that the MIPS compiler does (namely by passing | |
3275 | the structure in the high byte or half word of the register). | |
3276 | This also makes varargs work. If we have such a structure, | |
3277 | we save the adjustment RTL, and the call define expands will | |
3278 | emit them. For the VOIDmode argument (argument after the | |
147255d8 | 3279 | last real argument), pass back a parallel vector holding each |
3f1f8d8c MM |
3280 | of the adjustments. */ |
3281 | ||
894715dd RS |
3282 | /* ??? function_arg can be called more than once for each argument. |
3283 | As a result, we compute more adjustments than we need here. | |
3284 | See the CUMULATIVE_ARGS definition in mips.h. */ | |
3285 | ||
147255d8 JW |
3286 | /* ??? This scheme requires everything smaller than the word size to |
3287 | shifted to the left, but when TARGET_64BIT and ! TARGET_INT64, | |
3288 | that would mean every int needs to be shifted left, which is very | |
3289 | inefficient. Let's not carry this compatibility to the 64 bit | |
3290 | calling convention for now. */ | |
3291 | ||
3292 | if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD | |
293a36eb | 3293 | && ! TARGET_64BIT && mips_abi != ABI_EABI) |
3f1f8d8c | 3294 | { |
f4ef129a JW |
3295 | rtx amount = GEN_INT (BITS_PER_WORD |
3296 | - int_size_in_bytes (type) * BITS_PER_UNIT); | |
293a36eb | 3297 | rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias); |
147255d8 JW |
3298 | if (TARGET_64BIT) |
3299 | cum->adjust[ cum->num_adjusts++ ] = gen_ashldi3 (reg, reg, amount); | |
3300 | else | |
3301 | cum->adjust[ cum->num_adjusts++ ] = gen_ashlsi3 (reg, reg, amount); | |
3f1f8d8c MM |
3302 | } |
3303 | } | |
3304 | ||
3305 | if (mode == VOIDmode && cum->num_adjusts > 0) | |
3306 | ret = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (cum->num_adjusts, cum->adjust)); | |
cee98a59 | 3307 | |
3f1f8d8c | 3308 | return ret; |
cee98a59 MM |
3309 | } |
3310 | ||
3311 | ||
3312 | int | |
3313 | function_arg_partial_nregs (cum, mode, type, named) | |
3314 | CUMULATIVE_ARGS *cum; /* current arg information */ | |
3315 | enum machine_mode mode; /* current arg mode */ | |
3316 | tree type; /* type of the argument or 0 if lib support */ | |
3317 | int named; /* != 0 for normal args, == 0 for ... args */ | |
3318 | { | |
b4b93495 RS |
3319 | if ((mode == BLKmode |
3320 | || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT | |
3321 | || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) | |
293a36eb ILT |
3322 | && cum->arg_words < MAX_ARGS_IN_REGISTERS |
3323 | && mips_abi != ABI_EABI) | |
cee98a59 | 3324 | { |
b4b93495 RS |
3325 | int words; |
3326 | if (mode == BLKmode) | |
147255d8 JW |
3327 | words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) |
3328 | / UNITS_PER_WORD); | |
b4b93495 | 3329 | else |
147255d8 | 3330 | words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; |
cee98a59 | 3331 | |
47f113fe | 3332 | if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS) |
cee98a59 MM |
3333 | return 0; /* structure fits in registers */ |
3334 | ||
3335 | if (TARGET_DEBUG_E_MODE) | |
3336 | fprintf (stderr, "function_arg_partial_nregs = %d\n", | |
3337 | MAX_ARGS_IN_REGISTERS - cum->arg_words); | |
3338 | ||
3339 | return MAX_ARGS_IN_REGISTERS - cum->arg_words; | |
3340 | } | |
3341 | ||
147255d8 | 3342 | else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1 |
293a36eb ILT |
3343 | && ! TARGET_64BIT |
3344 | && mips_abi != ABI_EABI) | |
cee98a59 MM |
3345 | { |
3346 | if (TARGET_DEBUG_E_MODE) | |
3347 | fprintf (stderr, "function_arg_partial_nregs = 1\n"); | |
3348 | ||
3349 | return 1; | |
3350 | } | |
3351 | ||
3352 | return 0; | |
3353 | } | |
cee98a59 MM |
3354 | \f |
3355 | /* Abort after printing out a specific insn. */ | |
3356 | ||
3357 | void | |
3358 | abort_with_insn (insn, reason) | |
3359 | rtx insn; | |
3360 | char *reason; | |
3361 | { | |
3362 | error (reason); | |
3363 | debug_rtx (insn); | |
3364 | abort (); | |
3365 | } | |
3366 | ||
3367 | /* Write a message to stderr (for use in macros expanded in files that do not | |
3368 | include stdio.h). */ | |
3369 | ||
3370 | void | |
3371 | trace (s, s1, s2) | |
3372 | char *s, *s1, *s2; | |
3373 | { | |
3374 | fprintf (stderr, s, s1, s2); | |
3375 | } | |
3376 | ||
3377 | \f | |
3378 | #ifdef SIGINFO | |
3379 | ||
cee98a59 MM |
3380 | static void |
3381 | siginfo (signo) | |
3382 | int signo; | |
3383 | { | |
cee98a59 MM |
3384 | fprintf (stderr, "compiling '%s' in '%s'\n", |
3385 | (current_function_name != (char *)0) ? current_function_name : "<toplevel>", | |
3386 | (current_function_file != (char *)0) ? current_function_file : "<no file>"); | |
a6b65dff | 3387 | fflush (stderr); |
cee98a59 | 3388 | } |
cee98a59 MM |
3389 | #endif /* SIGINFO */ |
3390 | ||
3391 | \f | |
3392 | /* Set up the threshold for data to go into the small data area, instead | |
3393 | of the normal data area, and detect any conflicts in the switches. */ | |
3394 | ||
3395 | void | |
3396 | override_options () | |
3397 | { | |
3398 | register int i, start; | |
3399 | register int regno; | |
3400 | register enum machine_mode mode; | |
3401 | ||
b82b0773 | 3402 | mips_section_threshold = (g_switch_set) ? g_switch_value : MIPS_DEFAULT_GVALUE; |
cee98a59 | 3403 | |
147255d8 JW |
3404 | if (mips_section_threshold <= 0) |
3405 | target_flags &= ~MASK_GPOPT; | |
3406 | else if (optimize) | |
3407 | target_flags |= MASK_GPOPT; | |
3408 | ||
3409 | /* Get the architectural level. */ | |
3410 | if (mips_isa_string == (char *)0) | |
3411 | { | |
3412 | #ifdef MIPS_ISA_DEFAULT | |
3413 | mips_isa = MIPS_ISA_DEFAULT; | |
3414 | #else | |
3415 | mips_isa = 1; | |
3416 | #endif | |
3417 | } | |
3418 | ||
3419 | else if (isdigit (*mips_isa_string)) | |
3420 | { | |
3421 | mips_isa = atoi (mips_isa_string); | |
33563487 | 3422 | if (mips_isa < 1 || mips_isa > 4) |
147255d8 JW |
3423 | { |
3424 | error ("-mips%d not supported", mips_isa); | |
3425 | mips_isa = 1; | |
3426 | } | |
3427 | } | |
3428 | ||
3429 | else | |
3430 | { | |
3431 | error ("bad value (%s) for -mips switch", mips_isa_string); | |
3432 | mips_isa = 1; | |
3433 | } | |
3434 | ||
ade6c319 JW |
3435 | #ifdef MIPS_ABI_DEFAULT |
3436 | /* Get the ABI to use. Currently this code is only used for Irix 6. */ | |
3437 | if (mips_abi_string == (char *) 0) | |
3438 | mips_abi = MIPS_ABI_DEFAULT; | |
d6c46142 RK |
3439 | else if (! strcmp (mips_abi_string, "32") |
3440 | || ! strcmp (mips_abi_string, "o32")) | |
ade6c319 JW |
3441 | mips_abi = ABI_32; |
3442 | else if (! strcmp (mips_abi_string, "n32")) | |
3443 | mips_abi = ABI_N32; | |
d6c46142 RK |
3444 | else if (! strcmp (mips_abi_string, "64") |
3445 | || ! strcmp (mips_abi_string, "n64")) | |
ade6c319 | 3446 | mips_abi = ABI_64; |
293a36eb ILT |
3447 | else if (! strcmp (mips_abi_string, "eabi")) |
3448 | mips_abi = ABI_EABI; | |
ade6c319 JW |
3449 | else |
3450 | error ("bad value (%s) for -mabi= switch", mips_abi_string); | |
3451 | ||
3452 | /* A specified ISA defaults the ABI if it was not specified. */ | |
293a36eb | 3453 | if (mips_abi_string == 0 && mips_isa_string && mips_abi != ABI_EABI) |
ade6c319 JW |
3454 | { |
3455 | if (mips_isa <= 2) | |
3456 | mips_abi = ABI_32; | |
3457 | else | |
3458 | mips_abi = ABI_64; | |
3459 | } | |
3460 | /* A specified ABI defaults the ISA if it was not specified. */ | |
293a36eb | 3461 | else if (mips_isa_string == 0 && mips_abi_string && mips_abi != ABI_EABI) |
ade6c319 JW |
3462 | { |
3463 | if (mips_abi == ABI_32) | |
3464 | mips_isa = 1; | |
3465 | else if (mips_abi == ABI_N32) | |
3466 | mips_isa = 3; | |
3467 | else | |
3468 | mips_isa = 4; | |
3469 | } | |
3470 | /* If both ABI and ISA were specified, check for conflicts. */ | |
3471 | else if (mips_isa_string && mips_abi_string) | |
3472 | { | |
3473 | if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64)) | |
3474 | || (mips_isa >= 3 && mips_abi == ABI_32)) | |
3475 | error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa); | |
3476 | } | |
3477 | ||
3478 | /* Override TARGET_DEFAULT if necessary. */ | |
3479 | if (mips_abi == ABI_32) | |
3480 | target_flags &= ~ (MASK_FLOAT64|MASK_64BIT); | |
3481 | ||
29a5d7cc | 3482 | /* In the EABI in 64 bit mode, longs and pointers are 64 bits. */ |
17964a96 | 3483 | if (mips_abi == ABI_EABI && TARGET_64BIT) |
29a5d7cc ILT |
3484 | target_flags |= MASK_LONG64; |
3485 | ||
ade6c319 JW |
3486 | /* ??? This doesn't work yet, so don't let people try to use it. */ |
3487 | if (mips_abi == ABI_32) | |
3488 | error ("The -mabi=32 support does not work yet."); | |
3489 | #else | |
3490 | if (mips_abi_string) | |
3491 | error ("This target does not support the -mabi switch."); | |
3492 | #endif | |
3493 | ||
1bd9166e JW |
3494 | #ifdef MIPS_CPU_STRING_DEFAULT |
3495 | /* ??? There is a minor inconsistency here. If the user specifies an ISA | |
3496 | greater than that supported by the default processor, then the user gets | |
3497 | an error. Normally, the compiler will just default to the base level cpu | |
3498 | for the indicated isa. */ | |
3499 | if (mips_cpu_string == (char *)0) | |
3500 | mips_cpu_string = MIPS_CPU_STRING_DEFAULT; | |
3501 | #endif | |
3502 | ||
cee98a59 MM |
3503 | /* Identify the processor type */ |
3504 | if (mips_cpu_string == (char *)0 | |
3505 | || !strcmp (mips_cpu_string, "default") | |
3506 | || !strcmp (mips_cpu_string, "DEFAULT")) | |
3507 | { | |
147255d8 JW |
3508 | switch (mips_isa) |
3509 | { | |
3510 | default: | |
3511 | mips_cpu_string = "3000"; | |
3512 | mips_cpu = PROCESSOR_R3000; | |
3513 | break; | |
3514 | case 2: | |
3515 | mips_cpu_string = "6000"; | |
3516 | mips_cpu = PROCESSOR_R6000; | |
3517 | break; | |
3518 | case 3: | |
3519 | mips_cpu_string = "4000"; | |
3520 | mips_cpu = PROCESSOR_R4000; | |
3521 | break; | |
33563487 JW |
3522 | case 4: |
3523 | mips_cpu_string = "8000"; | |
3524 | mips_cpu = PROCESSOR_R8000; | |
3525 | break; | |
147255d8 | 3526 | } |
cee98a59 MM |
3527 | } |
3528 | ||
3529 | else | |
3530 | { | |
3531 | char *p = mips_cpu_string; | |
5034b7bd | 3532 | int seen_v = FALSE; |
cee98a59 | 3533 | |
5034b7bd JW |
3534 | /* We need to cope with the various "vr" prefixes for the NEC 4300 |
3535 | and 4100 processors. */ | |
3536 | if (*p == 'v' || *p == 'V') | |
3537 | { | |
3538 | seen_v = TRUE; | |
3539 | p++; | |
3540 | } | |
cee98a59 MM |
3541 | if (*p == 'r' || *p == 'R') |
3542 | p++; | |
3543 | ||
3544 | /* Since there is no difference between a R2000 and R3000 in | |
3545 | terms of the scheduler, we collapse them into just an R3000. */ | |
3546 | ||
3547 | mips_cpu = PROCESSOR_DEFAULT; | |
3548 | switch (*p) | |
3549 | { | |
3550 | case '2': | |
3551 | if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K")) | |
3552 | mips_cpu = PROCESSOR_R3000; | |
3553 | break; | |
3554 | ||
3555 | case '3': | |
3556 | if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K")) | |
3557 | mips_cpu = PROCESSOR_R3000; | |
3558 | break; | |
3559 | ||
3560 | case '4': | |
3561 | if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K")) | |
3562 | mips_cpu = PROCESSOR_R4000; | |
5034b7bd JW |
3563 | /* The vr4100 is a non-FP ISA III processor with some extra |
3564 | instructions. */ | |
3565 | else if (!strcmp (p, "4100")) { | |
3566 | mips_cpu = PROCESSOR_R4100; | |
3567 | target_flags |= MASK_SOFT_FLOAT ; | |
3568 | } | |
3569 | /* The vr4300 is a standard ISA III processor, but with a different | |
3570 | pipeline. */ | |
3571 | else if (!strcmp (p, "4300")) | |
3572 | mips_cpu = PROCESSOR_R4300; | |
147255d8 JW |
3573 | /* The r4400 is exactly the same as the r4000 from the compiler's |
3574 | viewpoint. */ | |
3575 | else if (!strcmp (p, "4400")) | |
3576 | mips_cpu = PROCESSOR_R4000; | |
3577 | else if (!strcmp (p, "4600")) | |
3578 | mips_cpu = PROCESSOR_R4600; | |
46299de9 | 3579 | else if (!strcmp (p, "4650")) |
053665d7 | 3580 | mips_cpu = PROCESSOR_R4650; |
cee98a59 MM |
3581 | break; |
3582 | ||
b8eb88d0 ILT |
3583 | case '5': |
3584 | if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K")) | |
3585 | mips_cpu = PROCESSOR_R5000; | |
3586 | break; | |
3587 | ||
cee98a59 MM |
3588 | case '6': |
3589 | if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K")) | |
3590 | mips_cpu = PROCESSOR_R6000; | |
3591 | break; | |
147255d8 | 3592 | |
33563487 JW |
3593 | case '8': |
3594 | if (!strcmp (p, "8000")) | |
3595 | mips_cpu = PROCESSOR_R8000; | |
3596 | break; | |
3597 | ||
147255d8 JW |
3598 | case 'o': |
3599 | if (!strcmp (p, "orion")) | |
3600 | mips_cpu = PROCESSOR_R4600; | |
3601 | break; | |
cee98a59 MM |
3602 | } |
3603 | ||
b8eb88d0 ILT |
3604 | if (seen_v |
3605 | && mips_cpu != PROCESSOR_R4300 | |
3606 | && mips_cpu != PROCESSOR_R4100 | |
3607 | && mips_cpu != PROCESSOR_R5000) | |
5034b7bd JW |
3608 | mips_cpu = PROCESSOR_DEFAULT; |
3609 | ||
cee98a59 MM |
3610 | if (mips_cpu == PROCESSOR_DEFAULT) |
3611 | { | |
3612 | error ("bad value (%s) for -mcpu= switch", mips_cpu_string); | |
3613 | mips_cpu_string = "default"; | |
3614 | } | |
3615 | } | |
3616 | ||
147255d8 | 3617 | if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1) |
33563487 | 3618 | || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2) |
053665d7 | 3619 | || ((mips_cpu == PROCESSOR_R4000 |
5034b7bd JW |
3620 | || mips_cpu == PROCESSOR_R4100 |
3621 | || mips_cpu == PROCESSOR_R4300 | |
053665d7 ILT |
3622 | || mips_cpu == PROCESSOR_R4600 |
3623 | || mips_cpu == PROCESSOR_R4650) | |
33563487 | 3624 | && mips_isa > 3)) |
cee98a59 MM |
3625 | error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa); |
3626 | ||
3627 | /* make sure sizes of ints/longs/etc. are ok */ | |
3628 | if (mips_isa < 3) | |
3629 | { | |
3630 | if (TARGET_INT64) | |
33563487 | 3631 | fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints"); |
cee98a59 MM |
3632 | |
3633 | else if (TARGET_LONG64) | |
33563487 | 3634 | fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs"); |
cee98a59 | 3635 | |
cee98a59 | 3636 | else if (TARGET_FLOAT64) |
33563487 | 3637 | fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers"); |
f8151871 JW |
3638 | |
3639 | else if (TARGET_64BIT) | |
33563487 | 3640 | fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers"); |
147255d8 | 3641 | } |
cee98a59 | 3642 | |
ade6c319 | 3643 | if (mips_abi != ABI_32) |
33563487 JW |
3644 | flag_pcc_struct_return = 0; |
3645 | ||
cee98a59 MM |
3646 | /* Tell halfpic.c that we have half-pic code if we do. */ |
3647 | if (TARGET_HALF_PIC) | |
c831afd5 | 3648 | HALF_PIC_INIT (); |
cee98a59 | 3649 | |
508a48d1 JW |
3650 | /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need |
3651 | to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */ | |
3652 | /* ??? -non_shared turns off pic code generation, but this is not | |
3653 | implemented. */ | |
ffa9d0b1 | 3654 | if (TARGET_ABICALLS) |
508a48d1 JW |
3655 | { |
3656 | mips_abicalls = MIPS_ABICALLS_YES; | |
3657 | flag_pic = 1; | |
508a48d1 JW |
3658 | if (mips_section_threshold > 0) |
3659 | warning ("-G is incompatible with PIC code which is the default"); | |
3660 | } | |
ffa9d0b1 | 3661 | else |
1d6ce736 | 3662 | mips_abicalls = MIPS_ABICALLS_NO; |
ffa9d0b1 | 3663 | |
e0bfcea5 ILT |
3664 | /* -membedded-pic is a form of PIC code suitable for embedded |
3665 | systems. All calls are made using PC relative addressing, and | |
3666 | all data is addressed using the $gp register. This requires gas, | |
3667 | which does most of the work, and GNU ld, which automatically | |
3668 | expands PC relative calls which are out of range into a longer | |
3669 | instruction sequence. All gcc really does differently is | |
3670 | generate a different sequence for a switch. */ | |
3671 | if (TARGET_EMBEDDED_PIC) | |
3672 | { | |
3673 | flag_pic = 1; | |
3674 | if (TARGET_ABICALLS) | |
3675 | warning ("-membedded-pic and -mabicalls are incompatible"); | |
3676 | if (g_switch_set) | |
3677 | warning ("-G and -membedded-pic are incompatible"); | |
3678 | /* Setting mips_section_threshold is not required, because gas | |
3679 | will force everything to be GP addressable anyhow, but | |
3680 | setting it will cause gcc to make better estimates of the | |
3681 | number of instructions required to access a particular data | |
3682 | item. */ | |
3683 | mips_section_threshold = 0x7fffffff; | |
3684 | } | |
3685 | ||
8acd7d30 JW |
3686 | /* This optimization requires a linker that can support a R_MIPS_LO16 |
3687 | relocation which is not immediately preceeded by a R_MIPS_HI16 relocation. | |
3688 | GNU ld has this support, but not all other MIPS linkers do, so we enable | |
3689 | this optimization only if the user requests it, or if GNU ld is the | |
3690 | standard linker for this configuration. */ | |
910628b8 JW |
3691 | /* ??? This does not work when target addresses are DImode. |
3692 | This is because we are missing DImode high/lo_sum patterns. */ | |
8acd7d30 JW |
3693 | if (TARGET_GAS && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic |
3694 | && Pmode == SImode) | |
910628b8 JW |
3695 | mips_split_addresses = 1; |
3696 | else | |
3697 | mips_split_addresses = 0; | |
3698 | ||
cee98a59 | 3699 | /* -mrnames says to use the MIPS software convention for register |
147255d8 | 3700 | names instead of the hardware names (ie, $a0 instead of $4). |
cee98a59 MM |
3701 | We do this by switching the names in mips_reg_names, which the |
3702 | reg_names points into via the REGISTER_NAMES macro. */ | |
3703 | ||
3704 | if (TARGET_NAME_REGS) | |
147255d8 | 3705 | bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names, sizeof (mips_reg_names)); |
cee98a59 MM |
3706 | |
3707 | /* If this is OSF/1, set up a SIGINFO handler so we can see what function | |
3708 | is currently being compiled. */ | |
3709 | #ifdef SIGINFO | |
3710 | if (getenv ("GCC_SIGINFO") != (char *)0) | |
3711 | { | |
3712 | struct sigaction action; | |
3713 | action.sa_handler = siginfo; | |
3714 | action.sa_mask = 0; | |
3715 | action.sa_flags = SA_RESTART; | |
3716 | sigaction (SIGINFO, &action, (struct sigaction *)0); | |
3717 | } | |
3718 | #endif | |
3719 | ||
d4099651 MM |
3720 | #if defined(_IOLBF) |
3721 | #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf) | |
842eb20e MM |
3722 | /* If -mstats and -quiet, make stderr line buffered. */ |
3723 | if (quiet_flag && TARGET_STATS) | |
d4099651 | 3724 | setvbuf (stderr, (char *)0, _IOLBF, BUFSIZ); |
842eb20e | 3725 | #endif |
4dee632b | 3726 | #endif |
842eb20e | 3727 | |
147255d8 JW |
3728 | /* Initialize the high and low values for legitimate floating point |
3729 | constants. Rather than trying to get the accuracy down to the | |
3730 | last bit, just use approximate ranges. */ | |
3731 | dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode); | |
3732 | dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode); | |
3733 | sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode); | |
3734 | sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode); | |
3735 | ||
cee98a59 MM |
3736 | mips_print_operand_punct['?'] = TRUE; |
3737 | mips_print_operand_punct['#'] = TRUE; | |
3738 | mips_print_operand_punct['&'] = TRUE; | |
3739 | mips_print_operand_punct['!'] = TRUE; | |
3740 | mips_print_operand_punct['*'] = TRUE; | |
3741 | mips_print_operand_punct['@'] = TRUE; | |
3742 | mips_print_operand_punct['.'] = TRUE; | |
3743 | mips_print_operand_punct['('] = TRUE; | |
3744 | mips_print_operand_punct[')'] = TRUE; | |
3745 | mips_print_operand_punct['['] = TRUE; | |
3746 | mips_print_operand_punct[']'] = TRUE; | |
3747 | mips_print_operand_punct['<'] = TRUE; | |
3748 | mips_print_operand_punct['>'] = TRUE; | |
3749 | mips_print_operand_punct['{'] = TRUE; | |
3750 | mips_print_operand_punct['}'] = TRUE; | |
ffa9d0b1 | 3751 | mips_print_operand_punct['^'] = TRUE; |
cee98a59 MM |
3752 | |
3753 | mips_char_to_class['d'] = GR_REGS; | |
3754 | mips_char_to_class['f'] = ((TARGET_HARD_FLOAT) ? FP_REGS : NO_REGS); | |
3755 | mips_char_to_class['h'] = HI_REG; | |
3756 | mips_char_to_class['l'] = LO_REG; | |
225b8835 | 3757 | mips_char_to_class['a'] = HILO_REG; |
cee98a59 | 3758 | mips_char_to_class['x'] = MD_REGS; |
225b8835 | 3759 | mips_char_to_class['b'] = ALL_REGS; |
cee98a59 | 3760 | mips_char_to_class['y'] = GR_REGS; |
34b650b3 | 3761 | mips_char_to_class['z'] = ST_REGS; |
cee98a59 MM |
3762 | |
3763 | /* Set up array to map GCC register number to debug register number. | |
3764 | Ignore the special purpose register numbers. */ | |
3765 | ||
3766 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3767 | mips_dbx_regno[i] = -1; | |
3768 | ||
3769 | start = GP_DBX_FIRST - GP_REG_FIRST; | |
3770 | for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) | |
3771 | mips_dbx_regno[i] = i + start; | |
3772 | ||
3773 | start = FP_DBX_FIRST - FP_REG_FIRST; | |
3774 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
3775 | mips_dbx_regno[i] = i + start; | |
3776 | ||
3777 | /* Set up array giving whether a given register can hold a given mode. | |
3778 | At present, restrict ints from being in FP registers, because reload | |
3779 | is a little enthusiastic about storing extra values in FP registers, | |
3780 | and this is not good for things like OS kernels. Also, due to the | |
c831afd5 | 3781 | mandatory delay, it is as fast to load from cached memory as to move |
cee98a59 MM |
3782 | from the FP register. */ |
3783 | ||
3784 | for (mode = VOIDmode; | |
3785 | mode != MAX_MACHINE_MODE; | |
3786 | mode = (enum machine_mode)((int)mode + 1)) | |
3787 | { | |
3788 | register int size = GET_MODE_SIZE (mode); | |
3789 | register enum mode_class class = GET_MODE_CLASS (mode); | |
3790 | ||
3791 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
3792 | { | |
34b650b3 MM |
3793 | register int temp; |
3794 | ||
b8eb88d0 ILT |
3795 | if (mode == CCmode) |
3796 | { | |
3797 | if (mips_isa < 4) | |
3798 | temp = (regno == FPSW_REGNUM); | |
3799 | else | |
3800 | temp = (ST_REG_P (regno) | |
3801 | || GP_REG_P (regno) | |
3802 | || FP_REG_P (regno)); | |
3803 | } | |
cee98a59 | 3804 | |
34b650b3 | 3805 | else if (GP_REG_P (regno)) |
cee98a59 MM |
3806 | temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD)); |
3807 | ||
3808 | else if (FP_REG_P (regno)) | |
3809 | temp = ((TARGET_FLOAT64 || ((regno & 1) == 0)) | |
34b650b3 MM |
3810 | && (class == MODE_FLOAT |
3811 | || class == MODE_COMPLEX_FLOAT | |
46299de9 ILT |
3812 | || (TARGET_DEBUG_H_MODE && class == MODE_INT)) |
3813 | && (! TARGET_SINGLE_FLOAT || size <= 4)); | |
cee98a59 MM |
3814 | |
3815 | else if (MD_REG_P (regno)) | |
1cfb3048 RK |
3816 | temp = (class == MODE_INT |
3817 | && (size <= UNITS_PER_WORD | |
3818 | || (regno == MD_REG_FIRST && size == 2 * UNITS_PER_WORD))); | |
cee98a59 | 3819 | |
34b650b3 MM |
3820 | else |
3821 | temp = FALSE; | |
cee98a59 MM |
3822 | |
3823 | mips_hard_regno_mode_ok[(int)mode][regno] = temp; | |
3824 | } | |
3825 | } | |
3826 | } | |
3827 | ||
3828 | \f | |
3829 | /* | |
ab78d4a8 MM |
3830 | * The MIPS debug format wants all automatic variables and arguments |
3831 | * to be in terms of the virtual frame pointer (stack pointer before | |
3832 | * any adjustment in the function), while the MIPS 3.0 linker wants | |
3833 | * the frame pointer to be the stack pointer after the initial | |
3834 | * adjustment. So, we do the adjustment here. The arg pointer (which | |
3835 | * is eliminated) points to the virtual frame pointer, while the frame | |
3836 | * pointer (which may be eliminated) points to the stack pointer after | |
3837 | * the initial adjustments. | |
cee98a59 MM |
3838 | */ |
3839 | ||
3840 | int | |
3841 | mips_debugger_offset (addr, offset) | |
3842 | rtx addr; | |
3843 | int offset; | |
3844 | { | |
c831afd5 | 3845 | rtx offset2 = const0_rtx; |
cee98a59 MM |
3846 | rtx reg = eliminate_constant_term (addr, &offset2); |
3847 | ||
3848 | if (!offset) | |
c831afd5 | 3849 | offset = INTVAL (offset2); |
cee98a59 | 3850 | |
ab78d4a8 | 3851 | if (reg == stack_pointer_rtx || reg == frame_pointer_rtx) |
c831afd5 MM |
3852 | { |
3853 | int frame_size = (!current_frame_info.initialized) | |
3854 | ? compute_frame_size (get_frame_size ()) | |
3855 | : current_frame_info.total_size; | |
3856 | ||
3857 | offset = offset - frame_size; | |
3858 | } | |
acc15f57 RS |
3859 | /* sdbout_parms does not want this to crash for unrecognized cases. */ |
3860 | #if 0 | |
ab78d4a8 MM |
3861 | else if (reg != arg_pointer_rtx) |
3862 | abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer."); | |
acc15f57 | 3863 | #endif |
cee98a59 MM |
3864 | |
3865 | return offset; | |
3866 | } | |
dbe9742d | 3867 | |
cee98a59 MM |
3868 | \f |
3869 | /* A C compound statement to output to stdio stream STREAM the | |
3870 | assembler syntax for an instruction operand X. X is an RTL | |
3871 | expression. | |
3872 | ||
3873 | CODE is a value that can be used to specify one of several ways | |
3874 | of printing the operand. It is used when identical operands | |
3875 | must be printed differently depending on the context. CODE | |
3876 | comes from the `%' specification that was used to request | |
3877 | printing of the operand. If the specification was just `%DIGIT' | |
3878 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
3879 | is the ASCII code for LTR. | |
3880 | ||
3881 | If X is a register, this macro should print the register's name. | |
3882 | The names can be found in an array `reg_names' whose type is | |
3883 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
3884 | ||
3885 | When the machine description has a specification `%PUNCT' (a `%' | |
3886 | followed by a punctuation character), this macro is called with | |
3887 | a null pointer for X and the punctuation character for CODE. | |
3888 | ||
3889 | The MIPS specific codes are: | |
3890 | ||
3891 | 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x", | |
3892 | 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x", | |
3893 | 'd' output integer constant in decimal, | |
3894 | 'z' if the operand is 0, use $0 instead of normal operand. | |
3895 | 'D' print second register of double-word register operand. | |
3896 | 'L' print low-order register of double-word register operand. | |
3897 | 'M' print high-order register of double-word register operand. | |
3898 | 'C' print part of opcode for a branch condition. | |
3899 | 'N' print part of opcode for a branch condition, inverted. | |
e0bfcea5 | 3900 | 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch). |
33563487 JW |
3901 | 'B' print 'z' for EQ, 'n' for NE |
3902 | 'b' print 'n' for EQ, 'z' for NE | |
3903 | 'T' print 'f' for EQ, 't' for NE | |
3904 | 't' print 't' for EQ, 'f' for NE | |
b8eb88d0 | 3905 | 'Z' print register and a comma, but print nothing for $fcc0 |
cee98a59 MM |
3906 | '(' Turn on .set noreorder |
3907 | ')' Turn on .set reorder | |
3908 | '[' Turn on .set noat | |
3909 | ']' Turn on .set at | |
3910 | '<' Turn on .set nomacro | |
3911 | '>' Turn on .set macro | |
3912 | '{' Turn on .set volatile (not GAS) | |
3913 | '}' Turn on .set novolatile (not GAS) | |
3914 | '&' Turn on .set noreorder if filling delay slots | |
3915 | '*' Turn on both .set noreorder and .set nomacro if filling delay slots | |
3916 | '!' Turn on .set nomacro if filling delay slots | |
3917 | '#' Print nop if in a .set noreorder section. | |
3918 | '?' Print 'l' if we are to use a branch likely instead of normal branch. | |
3919 | '@' Print the name of the assembler temporary register (at or $1). | |
ffa9d0b1 JW |
3920 | '.' Print the name of the register with a hard-wired zero (zero or $0). |
3921 | '^' Print the name of the pic call-through register (t9 or $25). */ | |
cee98a59 MM |
3922 | |
3923 | void | |
3924 | print_operand (file, op, letter) | |
3925 | FILE *file; /* file to write to */ | |
3926 | rtx op; /* operand to print */ | |
3927 | int letter; /* %<letter> or 0 */ | |
3928 | { | |
3929 | register enum rtx_code code; | |
3930 | ||
3931 | if (PRINT_OPERAND_PUNCT_VALID_P (letter)) | |
3932 | { | |
3933 | switch (letter) | |
3934 | { | |
3935 | default: | |
3936 | error ("PRINT_OPERAND: Unknown punctuation '%c'", letter); | |
3937 | break; | |
3938 | ||
3939 | case '?': | |
3940 | if (mips_branch_likely) | |
3941 | putc ('l', file); | |
3942 | break; | |
3943 | ||
3944 | case '@': | |
3945 | fputs (reg_names [GP_REG_FIRST + 1], file); | |
3946 | break; | |
3947 | ||
ffa9d0b1 JW |
3948 | case '^': |
3949 | fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file); | |
3950 | break; | |
3951 | ||
cee98a59 MM |
3952 | case '.': |
3953 | fputs (reg_names [GP_REG_FIRST + 0], file); | |
3954 | break; | |
3955 | ||
3956 | case '&': | |
3957 | if (final_sequence != 0 && set_noreorder++ == 0) | |
3958 | fputs (".set\tnoreorder\n\t", file); | |
3959 | break; | |
3960 | ||
3961 | case '*': | |
3962 | if (final_sequence != 0) | |
3963 | { | |
3964 | if (set_noreorder++ == 0) | |
3965 | fputs (".set\tnoreorder\n\t", file); | |
3966 | ||
3967 | if (set_nomacro++ == 0) | |
3968 | fputs (".set\tnomacro\n\t", file); | |
3969 | } | |
3970 | break; | |
3971 | ||
3972 | case '!': | |
3973 | if (final_sequence != 0 && set_nomacro++ == 0) | |
3974 | fputs ("\n\t.set\tnomacro", file); | |
3975 | break; | |
3976 | ||
3977 | case '#': | |
3978 | if (set_noreorder != 0) | |
3979 | fputs ("\n\tnop", file); | |
3980 | ||
85098019 | 3981 | else if (TARGET_STATS) |
cee98a59 MM |
3982 | fputs ("\n\t#nop", file); |
3983 | ||
3984 | break; | |
3985 | ||
3986 | case '(': | |
3987 | if (set_noreorder++ == 0) | |
3988 | fputs (".set\tnoreorder\n\t", file); | |
3989 | break; | |
3990 | ||
3991 | case ')': | |
3992 | if (set_noreorder == 0) | |
3993 | error ("internal error: %%) found without a %%( in assembler pattern"); | |
3994 | ||
3995 | else if (--set_noreorder == 0) | |
3996 | fputs ("\n\t.set\treorder", file); | |
3997 | ||
3998 | break; | |
3999 | ||
4000 | case '[': | |
4001 | if (set_noat++ == 0) | |
4002 | fputs (".set\tnoat\n\t", file); | |
4003 | break; | |
4004 | ||
4005 | case ']': | |
4006 | if (set_noat == 0) | |
4007 | error ("internal error: %%] found without a %%[ in assembler pattern"); | |
4008 | ||
4009 | else if (--set_noat == 0) | |
4010 | fputs ("\n\t.set\tat", file); | |
4011 | ||
4012 | break; | |
4013 | ||
4014 | case '<': | |
4015 | if (set_nomacro++ == 0) | |
4016 | fputs (".set\tnomacro\n\t", file); | |
4017 | break; | |
4018 | ||
4019 | case '>': | |
4020 | if (set_nomacro == 0) | |
4021 | error ("internal error: %%> found without a %%< in assembler pattern"); | |
4022 | ||
4023 | else if (--set_nomacro == 0) | |
4024 | fputs ("\n\t.set\tmacro", file); | |
4025 | ||
4026 | break; | |
4027 | ||
4028 | case '{': | |
4029 | if (set_volatile++ == 0) | |
4030 | fprintf (file, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS) ? "" : "#"); | |
4031 | break; | |
4032 | ||
4033 | case '}': | |
4034 | if (set_volatile == 0) | |
4035 | error ("internal error: %%} found without a %%{ in assembler pattern"); | |
4036 | ||
4037 | else if (--set_volatile == 0) | |
4038 | fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#"); | |
4039 | ||
4040 | break; | |
4041 | } | |
4042 | return; | |
4043 | } | |
4044 | ||
4045 | if (! op) | |
4046 | { | |
4047 | error ("PRINT_OPERAND null pointer"); | |
4048 | return; | |
4049 | } | |
4050 | ||
4051 | code = GET_CODE (op); | |
2a0b0bf5 ILT |
4052 | |
4053 | if (code == SIGN_EXTEND) | |
4054 | { | |
4055 | op = XEXP (op, 0); | |
4056 | code = GET_CODE (op); | |
4057 | } | |
4058 | ||
cee98a59 MM |
4059 | if (letter == 'C') |
4060 | switch (code) | |
4061 | { | |
4062 | case EQ: fputs ("eq", file); break; | |
4063 | case NE: fputs ("ne", file); break; | |
4064 | case GT: fputs ("gt", file); break; | |
4065 | case GE: fputs ("ge", file); break; | |
4066 | case LT: fputs ("lt", file); break; | |
4067 | case LE: fputs ("le", file); break; | |
4068 | case GTU: fputs ("gtu", file); break; | |
4069 | case GEU: fputs ("geu", file); break; | |
4070 | case LTU: fputs ("ltu", file); break; | |
4071 | case LEU: fputs ("leu", file); break; | |
4072 | ||
4073 | default: | |
e7f6e33b | 4074 | abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C"); |
cee98a59 MM |
4075 | } |
4076 | ||
4077 | else if (letter == 'N') | |
4078 | switch (code) | |
4079 | { | |
4080 | case EQ: fputs ("ne", file); break; | |
4081 | case NE: fputs ("eq", file); break; | |
4082 | case GT: fputs ("le", file); break; | |
4083 | case GE: fputs ("lt", file); break; | |
4084 | case LT: fputs ("ge", file); break; | |
4085 | case LE: fputs ("gt", file); break; | |
4086 | case GTU: fputs ("leu", file); break; | |
4087 | case GEU: fputs ("ltu", file); break; | |
4088 | case LTU: fputs ("geu", file); break; | |
4089 | case LEU: fputs ("gtu", file); break; | |
4090 | ||
4091 | default: | |
e7f6e33b | 4092 | abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N"); |
cee98a59 MM |
4093 | } |
4094 | ||
e0bfcea5 ILT |
4095 | else if (letter == 'S') |
4096 | { | |
4097 | char buffer[100]; | |
4098 | ||
4099 | ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op)); | |
4100 | assemble_name (file, buffer); | |
4101 | } | |
4102 | ||
b8eb88d0 ILT |
4103 | else if (letter == 'Z') |
4104 | { | |
4105 | register int regnum; | |
4106 | ||
4107 | if (code != REG) | |
4108 | abort (); | |
4109 | regnum = REGNO (op); | |
4110 | if (! ST_REG_P (regnum)) | |
4111 | abort (); | |
4112 | if (regnum != ST_REG_FIRST) | |
4113 | fprintf (file, "%s,", reg_names[regnum]); | |
4114 | } | |
4115 | ||
2a0b0bf5 | 4116 | else if (code == REG || code == SUBREG) |
cee98a59 | 4117 | { |
2a0b0bf5 ILT |
4118 | register int regnum; |
4119 | ||
4120 | if (code == REG) | |
4121 | regnum = REGNO (op); | |
4122 | else | |
4123 | regnum = true_regnum (op); | |
cee98a59 | 4124 | |
96abdcb1 ILT |
4125 | if ((letter == 'M' && ! WORDS_BIG_ENDIAN) |
4126 | || (letter == 'L' && WORDS_BIG_ENDIAN) | |
4127 | || letter == 'D') | |
cee98a59 MM |
4128 | regnum++; |
4129 | ||
4130 | fprintf (file, "%s", reg_names[regnum]); | |
4131 | } | |
4132 | ||
4133 | else if (code == MEM) | |
4134 | output_address (XEXP (op, 0)); | |
4135 | ||
28ae04f1 ILT |
4136 | else if (code == CONST_DOUBLE |
4137 | && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT) | |
cee98a59 | 4138 | { |
147255d8 JW |
4139 | REAL_VALUE_TYPE d; |
4140 | char s[30]; | |
4141 | ||
4142 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
4143 | REAL_VALUE_TO_DECIMAL (d, "%.20e", s); | |
4144 | fprintf (file, s); | |
cee98a59 MM |
4145 | } |
4146 | ||
4147 | else if ((letter == 'x') && (GET_CODE(op) == CONST_INT)) | |
4148 | fprintf (file, "0x%04x", 0xffff & (INTVAL(op))); | |
4149 | ||
33563487 JW |
4150 | else if ((letter == 'X') && (GET_CODE(op) == CONST_INT) |
4151 | && HOST_BITS_PER_WIDE_INT == 32) | |
cee98a59 MM |
4152 | fprintf (file, "0x%08x", INTVAL(op)); |
4153 | ||
33563487 JW |
4154 | else if ((letter == 'X') && (GET_CODE(op) == CONST_INT) |
4155 | && HOST_BITS_PER_WIDE_INT == 64) | |
4156 | fprintf (file, "0x%016lx", INTVAL(op)); | |
4157 | ||
cee98a59 MM |
4158 | else if ((letter == 'd') && (GET_CODE(op) == CONST_INT)) |
4159 | fprintf (file, "%d", (INTVAL(op))); | |
4160 | ||
4161 | else if (letter == 'z' | |
4162 | && (GET_CODE (op) == CONST_INT) | |
4163 | && INTVAL (op) == 0) | |
4164 | fputs (reg_names[GP_REG_FIRST], file); | |
4165 | ||
4166 | else if (letter == 'd' || letter == 'x' || letter == 'X') | |
4167 | fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter); | |
4168 | ||
33563487 JW |
4169 | else if (letter == 'B') |
4170 | fputs (code == EQ ? "z" : "n", file); | |
4171 | else if (letter == 'b') | |
4172 | fputs (code == EQ ? "n" : "z", file); | |
4173 | else if (letter == 'T') | |
4174 | fputs (code == EQ ? "f" : "t", file); | |
4175 | else if (letter == 't') | |
4176 | fputs (code == EQ ? "t" : "f", file); | |
4177 | ||
cee98a59 MM |
4178 | else |
4179 | output_addr_const (file, op); | |
4180 | } | |
4181 | ||
4182 | \f | |
4183 | /* A C compound statement to output to stdio stream STREAM the | |
4184 | assembler syntax for an instruction operand that is a memory | |
4185 | reference whose address is ADDR. ADDR is an RTL expression. | |
4186 | ||
4187 | On some machines, the syntax for a symbolic address depends on | |
4188 | the section that the address refers to. On these machines, | |
4189 | define the macro `ENCODE_SECTION_INFO' to store the information | |
4190 | into the `symbol_ref', and then check for it here. */ | |
4191 | ||
4192 | void | |
4193 | print_operand_address (file, addr) | |
4194 | FILE *file; | |
4195 | rtx addr; | |
4196 | { | |
4197 | if (!addr) | |
4198 | error ("PRINT_OPERAND_ADDRESS, null pointer"); | |
4199 | ||
4200 | else | |
4201 | switch (GET_CODE (addr)) | |
4202 | { | |
4203 | default: | |
e7f6e33b | 4204 | abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1"); |
cee98a59 MM |
4205 | break; |
4206 | ||
4207 | case REG: | |
ab78d4a8 MM |
4208 | if (REGNO (addr) == ARG_POINTER_REGNUM) |
4209 | abort_with_insn (addr, "Arg pointer not eliminated."); | |
4210 | ||
cee98a59 MM |
4211 | fprintf (file, "0(%s)", reg_names [REGNO (addr)]); |
4212 | break; | |
4213 | ||
910628b8 JW |
4214 | case LO_SUM: |
4215 | { | |
4216 | register rtx arg0 = XEXP (addr, 0); | |
4217 | register rtx arg1 = XEXP (addr, 1); | |
4218 | ||
4219 | if (! mips_split_addresses) | |
4220 | abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM."); | |
4221 | ||
4222 | if (GET_CODE (arg0) != REG) | |
4223 | abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG."); | |
4224 | ||
4225 | fprintf (file, "%%lo("); | |
4226 | print_operand_address (file, arg1); | |
4227 | fprintf (file, ")(%s)", reg_names [REGNO (arg0)]); | |
4228 | } | |
4229 | break; | |
4230 | ||
cee98a59 MM |
4231 | case PLUS: |
4232 | { | |
4233 | register rtx reg = (rtx)0; | |
4234 | register rtx offset = (rtx)0; | |
4235 | register rtx arg0 = XEXP (addr, 0); | |
4236 | register rtx arg1 = XEXP (addr, 1); | |
4237 | ||
4238 | if (GET_CODE (arg0) == REG) | |
4239 | { | |
4240 | reg = arg0; | |
4241 | offset = arg1; | |
4242 | if (GET_CODE (offset) == REG) | |
4243 | abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs"); | |
4244 | } | |
4245 | else if (GET_CODE (arg1) == REG) | |
4246 | { | |
4247 | reg = arg1; | |
4248 | offset = arg0; | |
4249 | } | |
4250 | else if (CONSTANT_P (arg0) && CONSTANT_P (arg1)) | |
4251 | { | |
4252 | output_addr_const (file, addr); | |
4253 | break; | |
4254 | } | |
4255 | else | |
4256 | abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs"); | |
4257 | ||
4258 | if (!CONSTANT_P (offset)) | |
e7f6e33b | 4259 | abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2"); |
cee98a59 | 4260 | |
910628b8 JW |
4261 | if (REGNO (reg) == ARG_POINTER_REGNUM) |
4262 | abort_with_insn (addr, "Arg pointer not eliminated."); | |
ab78d4a8 | 4263 | |
cee98a59 MM |
4264 | output_addr_const (file, offset); |
4265 | fprintf (file, "(%s)", reg_names [REGNO (reg)]); | |
4266 | } | |
4267 | break; | |
4268 | ||
4269 | case LABEL_REF: | |
4270 | case SYMBOL_REF: | |
4271 | case CONST_INT: | |
4272 | case CONST: | |
4273 | output_addr_const (file, addr); | |
4274 | break; | |
4275 | } | |
4276 | } | |
4277 | ||
4278 | \f | |
4279 | /* If optimizing for the global pointer, keep track of all of | |
4280 | the externs, so that at the end of the file, we can emit | |
4281 | the appropriate .extern declaration for them, before writing | |
4282 | out the text section. We assume that all names passed to | |
4283 | us are in the permanent obstack, so that they will be valid | |
4284 | at the end of the compilation. | |
4285 | ||
4144ff62 DE |
4286 | If we have -G 0, or the extern size is unknown, or the object is in |
4287 | a user specified section that is not .sbss/.sdata, don't bother | |
4288 | emitting the .externs. In the case of user specified sections this | |
4289 | behaviour is required as otherwise GAS will think the object lives in | |
4290 | .sbss/.sdata. */ | |
cee98a59 MM |
4291 | |
4292 | int | |
4293 | mips_output_external (file, decl, name) | |
4294 | FILE *file; | |
4295 | tree decl; | |
4296 | char *name; | |
4297 | { | |
4298 | register struct extern_list *p; | |
4299 | int len; | |
4144ff62 | 4300 | tree section_name; |
cee98a59 MM |
4301 | |
4302 | if (TARGET_GP_OPT | |
cee98a59 | 4303 | && ((TREE_CODE (decl)) != FUNCTION_DECL) |
4144ff62 DE |
4304 | && ((len = int_size_in_bytes (TREE_TYPE (decl))) > 0) |
4305 | && (((section_name = DECL_SECTION_NAME (decl)) == NULL) | |
4306 | || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0 | |
4307 | || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0)) | |
cee98a59 MM |
4308 | { |
4309 | p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list)); | |
4310 | p->next = extern_head; | |
4311 | p->name = name; | |
4312 | p->size = len; | |
4313 | extern_head = p; | |
4314 | } | |
5619cc87 JW |
4315 | |
4316 | #ifdef ASM_OUTPUT_UNDEF_FUNCTION | |
dd947ed9 RK |
4317 | if (TREE_CODE (decl) == FUNCTION_DECL |
4318 | /* ??? Don't include alloca, since gcc will always expand it | |
4319 | inline. If we don't do this, libg++ fails to build. */ | |
9f770b61 JW |
4320 | && strcmp (name, "alloca") |
4321 | /* ??? Don't include __builtin_next_arg, because then gcc will not | |
4322 | bootstrap under Irix 5.1. */ | |
4323 | && strcmp (name, "__builtin_next_arg")) | |
5619cc87 JW |
4324 | { |
4325 | p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list)); | |
4326 | p->next = extern_head; | |
4327 | p->name = name; | |
4328 | p->size = -1; | |
4329 | extern_head = p; | |
4330 | } | |
4331 | #endif | |
4332 | ||
4333 | return 0; | |
4334 | } | |
4335 | ||
4336 | #ifdef ASM_OUTPUT_UNDEF_FUNCTION | |
4337 | int | |
4338 | mips_output_external_libcall (file, name) | |
4339 | FILE *file; | |
4340 | char *name; | |
4341 | { | |
4342 | register struct extern_list *p; | |
4343 | ||
4344 | p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list)); | |
4345 | p->next = extern_head; | |
4346 | p->name = name; | |
4347 | p->size = -1; | |
4348 | extern_head = p; | |
4349 | ||
cee98a59 MM |
4350 | return 0; |
4351 | } | |
5619cc87 | 4352 | #endif |
cee98a59 MM |
4353 | |
4354 | \f | |
4355 | /* Compute a string to use as a temporary file name. */ | |
4356 | ||
147255d8 JW |
4357 | /* On MSDOS, write temp files in current dir |
4358 | because there's no place else we can expect to use. */ | |
4359 | #if __MSDOS__ | |
4360 | #ifndef P_tmpdir | |
4361 | #define P_tmpdir "./" | |
4362 | #endif | |
4363 | #endif | |
4364 | ||
cee98a59 MM |
4365 | static FILE * |
4366 | make_temp_file () | |
4367 | { | |
cee98a59 MM |
4368 | FILE *stream; |
4369 | char *base = getenv ("TMPDIR"); | |
4370 | int len; | |
4371 | ||
4372 | if (base == (char *)0) | |
4373 | { | |
4374 | #ifdef P_tmpdir | |
4375 | if (access (P_tmpdir, R_OK | W_OK) == 0) | |
4376 | base = P_tmpdir; | |
4377 | else | |
4378 | #endif | |
4379 | if (access ("/usr/tmp", R_OK | W_OK) == 0) | |
4380 | base = "/usr/tmp/"; | |
4381 | else | |
4382 | base = "/tmp/"; | |
4383 | } | |
4384 | ||
4385 | len = strlen (base); | |
147255d8 JW |
4386 | /* temp_filename is global, so we must use malloc, not alloca. */ |
4387 | temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX")); | |
cee98a59 MM |
4388 | strcpy (temp_filename, base); |
4389 | if (len > 0 && temp_filename[len-1] != '/') | |
4390 | temp_filename[len++] = '/'; | |
4391 | ||
147255d8 | 4392 | strcpy (temp_filename + len, "ctXXXXXX"); |
cee98a59 MM |
4393 | mktemp (temp_filename); |
4394 | ||
4395 | stream = fopen (temp_filename, "w+"); | |
4396 | if (!stream) | |
4397 | pfatal_with_name (temp_filename); | |
4398 | ||
147255d8 JW |
4399 | #ifndef __MSDOS__ |
4400 | /* In MSDOS, we cannot unlink the temporary file until we are finished using | |
4401 | it. Otherwise, we delete it now, so that it will be gone even if the | |
4402 | compiler happens to crash. */ | |
cee98a59 | 4403 | unlink (temp_filename); |
147255d8 | 4404 | #endif |
cee98a59 MM |
4405 | return stream; |
4406 | } | |
4407 | ||
4408 | \f | |
4409 | /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out | |
4410 | for .file's that start within a function. If we are smuggling stabs, try to | |
4411 | put out a MIPS ECOFF file and a stab. */ | |
4412 | ||
4413 | void | |
4414 | mips_output_filename (stream, name) | |
4415 | FILE *stream; | |
4416 | char *name; | |
4417 | { | |
4418 | static int first_time = TRUE; | |
4419 | char ltext_label_name[100]; | |
4420 | ||
4421 | if (first_time) | |
4422 | { | |
4423 | first_time = FALSE; | |
4424 | SET_FILE_NUMBER (); | |
4425 | current_function_file = name; | |
33563487 | 4426 | ASM_OUTPUT_FILENAME (stream, num_source_filenames, name); |
2bacb292 | 4427 | /* This tells mips-tfile that stabs will follow. */ |
9987501f MM |
4428 | if (!TARGET_GAS && write_symbols == DBX_DEBUG) |
4429 | fprintf (stream, "\t#@stabs\n"); | |
cee98a59 MM |
4430 | } |
4431 | ||
2bacb292 | 4432 | else if (write_symbols == DBX_DEBUG) |
cee98a59 MM |
4433 | { |
4434 | ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0); | |
99107e86 PE |
4435 | fprintf (stream, "%s ", ASM_STABS_OP); |
4436 | output_quoted_string (stream, name); | |
4437 | fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]); | |
cee98a59 MM |
4438 | } |
4439 | ||
4440 | else if (name != current_function_file | |
4441 | && strcmp (name, current_function_file) != 0) | |
4442 | { | |
4443 | if (inside_function && !TARGET_GAS) | |
4444 | { | |
4445 | if (!file_in_function_warning) | |
4446 | { | |
4447 | file_in_function_warning = TRUE; | |
4448 | ignore_line_number = TRUE; | |
4449 | warning ("MIPS ECOFF format does not allow changing filenames within functions with #line"); | |
4450 | } | |
cee98a59 | 4451 | } |
cee98a59 MM |
4452 | else |
4453 | { | |
4454 | SET_FILE_NUMBER (); | |
4455 | current_function_file = name; | |
33563487 | 4456 | ASM_OUTPUT_FILENAME (stream, num_source_filenames, name); |
cee98a59 MM |
4457 | } |
4458 | } | |
4459 | } | |
4460 | ||
4461 | \f | |
4462 | /* Emit a linenumber. For encapsulated stabs, we need to put out a stab | |
4463 | as well as a .loc, since it is possible that MIPS ECOFF might not be | |
4464 | able to represent the location for inlines that come from a different | |
4465 | file. */ | |
4466 | ||
4467 | void | |
4468 | mips_output_lineno (stream, line) | |
4469 | FILE *stream; | |
4470 | int line; | |
4471 | { | |
2bacb292 | 4472 | if (write_symbols == DBX_DEBUG) |
cee98a59 MM |
4473 | { |
4474 | ++sym_lineno; | |
dccc9e85 JW |
4475 | fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n", |
4476 | LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line, | |
4477 | LOCAL_LABEL_PREFIX, sym_lineno); | |
cee98a59 MM |
4478 | } |
4479 | ||
4480 | else | |
4481 | { | |
4482 | fprintf (stream, "\n\t%s.loc\t%d %d\n", | |
4483 | (ignore_line_number) ? "#" : "", | |
4484 | num_source_filenames, line); | |
4485 | ||
4486 | LABEL_AFTER_LOC (stream); | |
4487 | } | |
4488 | } | |
4489 | ||
65437fe8 MM |
4490 | \f |
4491 | /* If defined, a C statement to be executed just prior to the | |
4492 | output of assembler code for INSN, to modify the extracted | |
4493 | operands so they will be output differently. | |
4494 | ||
4495 | Here the argument OPVEC is the vector containing the operands | |
4496 | extracted from INSN, and NOPERANDS is the number of elements of | |
4497 | the vector which contain meaningful data for this insn. The | |
4498 | contents of this vector are what will be used to convert the | |
4499 | insn template into assembler code, so you can change the | |
4500 | assembler output by changing the contents of the vector. | |
4501 | ||
4502 | We use it to check if the current insn needs a nop in front of it | |
4503 | because of load delays, and also to update the delay slot | |
4504 | statistics. */ | |
4505 | ||
85098019 JW |
4506 | /* ??? There is no real need for this function, because it never actually |
4507 | emits a NOP anymore. */ | |
4508 | ||
65437fe8 MM |
4509 | void |
4510 | final_prescan_insn (insn, opvec, noperands) | |
4511 | rtx insn; | |
4512 | rtx opvec[]; | |
4513 | int noperands; | |
4514 | { | |
4515 | if (dslots_number_nops > 0) | |
4516 | { | |
65437fe8 MM |
4517 | rtx pattern = PATTERN (insn); |
4518 | int length = get_attr_length (insn); | |
4519 | ||
4520 | /* Do we need to emit a NOP? */ | |
4521 | if (length == 0 | |
4522 | || (mips_load_reg != (rtx)0 && reg_mentioned_p (mips_load_reg, pattern)) | |
4523 | || (mips_load_reg2 != (rtx)0 && reg_mentioned_p (mips_load_reg2, pattern)) | |
4524 | || (mips_load_reg3 != (rtx)0 && reg_mentioned_p (mips_load_reg3, pattern)) | |
4525 | || (mips_load_reg4 != (rtx)0 && reg_mentioned_p (mips_load_reg4, pattern))) | |
85098019 | 4526 | fputs ("\t#nop\n", asm_out_file); |
65437fe8 MM |
4527 | |
4528 | else | |
4529 | dslots_load_filled++; | |
4530 | ||
4531 | while (--dslots_number_nops > 0) | |
85098019 | 4532 | fputs ("\t#nop\n", asm_out_file); |
65437fe8 MM |
4533 | |
4534 | mips_load_reg = (rtx)0; | |
4535 | mips_load_reg2 = (rtx)0; | |
4536 | mips_load_reg3 = (rtx)0; | |
4537 | mips_load_reg4 = (rtx)0; | |
65437fe8 MM |
4538 | } |
4539 | ||
4540 | if (TARGET_STATS) | |
4541 | { | |
4542 | enum rtx_code code = GET_CODE (insn); | |
4543 | if (code == JUMP_INSN || code == CALL_INSN) | |
4544 | dslots_jump_total++; | |
4545 | } | |
4546 | } | |
4547 | ||
cee98a59 MM |
4548 | \f |
4549 | /* Output at beginning of assembler file. | |
4550 | If we are optimizing to use the global pointer, create a temporary | |
4551 | file to hold all of the text stuff, and write it out to the end. | |
4552 | This is needed because the MIPS assembler is evidently one pass, | |
4553 | and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata | |
4554 | declaration when the code is processed, it generates a two | |
4555 | instruction sequence. */ | |
4556 | ||
4557 | void | |
4558 | mips_asm_file_start (stream) | |
4559 | FILE *stream; | |
4560 | { | |
4561 | ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename); | |
4562 | ||
4563 | /* Versions of the MIPS assembler before 2.20 generate errors | |
4564 | if a branch inside of a .set noreorder section jumps to a | |
4565 | label outside of the .set noreorder section. Revision 2.20 | |
4566 | just set nobopt silently rather than fixing the bug. */ | |
4567 | ||
4568 | if (TARGET_MIPS_AS && optimize && flag_delayed_branch) | |
4569 | fprintf (stream, "\t.set\tnobopt\n"); | |
4570 | ||
ffa9d0b1 | 4571 | /* Generate the pseudo ops that System V.4 wants. */ |
c388a0c4 RS |
4572 | #ifndef ABICALLS_ASM_OP |
4573 | #define ABICALLS_ASM_OP ".abicalls" | |
4574 | #endif | |
cee98a59 | 4575 | if (TARGET_ABICALLS) |
ffa9d0b1 | 4576 | /* ??? but do not want this (or want pic0) if -non-shared? */ |
c388a0c4 | 4577 | fprintf (stream, "\t%s\n", ABICALLS_ASM_OP); |
cee98a59 | 4578 | |
33563487 JW |
4579 | /* Start a section, so that the first .popsection directive is guaranteed |
4580 | to have a previously defined section to pop back to. */ | |
293a36eb | 4581 | if (mips_abi != ABI_32 && mips_abi != ABI_EABI) |
33563487 JW |
4582 | fprintf (stream, "\t.section\t.text\n"); |
4583 | ||
d7a58f30 | 4584 | /* This code exists so that we can put all externs before all symbol |
d46c6fce | 4585 | references. This is necessary for the MIPS assembler's global pointer |
d7a58f30 | 4586 | optimizations to work. */ |
d46c6fce | 4587 | if (TARGET_FILE_SWITCHING) |
cee98a59 MM |
4588 | { |
4589 | asm_out_data_file = stream; | |
4590 | asm_out_text_file = make_temp_file (); | |
4591 | } | |
4592 | else | |
4593 | asm_out_data_file = asm_out_text_file = stream; | |
4594 | ||
2096c147 DE |
4595 | if (flag_verbose_asm) |
4596 | fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n", | |
4597 | ASM_COMMENT_START, | |
4598 | mips_section_threshold, mips_cpu_string, mips_isa); | |
cee98a59 MM |
4599 | } |
4600 | ||
4601 | \f | |
4602 | /* If we are optimizing the global pointer, emit the text section now | |
4603 | and any small externs which did not have .comm, etc that are | |
4604 | needed. Also, give a warning if the data area is more than 32K and | |
4605 | -pic because 3 instructions are needed to reference the data | |
4606 | pointers. */ | |
4607 | ||
4608 | void | |
4609 | mips_asm_file_end (file) | |
4610 | FILE *file; | |
4611 | { | |
4612 | char buffer[8192]; | |
4613 | tree name_tree; | |
4614 | struct extern_list *p; | |
4615 | int len; | |
842eb20e MM |
4616 | |
4617 | if (HALF_PIC_P ()) | |
4618 | HALF_PIC_FINISH (file); | |
cee98a59 | 4619 | |
5619cc87 | 4620 | if (extern_head) |
cee98a59 | 4621 | { |
5619cc87 | 4622 | fputs ("\n", file); |
cee98a59 MM |
4623 | |
4624 | for (p = extern_head; p != 0; p = p->next) | |
4625 | { | |
4626 | name_tree = get_identifier (p->name); | |
c831afd5 MM |
4627 | |
4628 | /* Positively ensure only one .extern for any given symbol. */ | |
4629 | if (! TREE_ASM_WRITTEN (name_tree)) | |
cee98a59 | 4630 | { |
c831afd5 | 4631 | TREE_ASM_WRITTEN (name_tree) = 1; |
5619cc87 JW |
4632 | #ifdef ASM_OUTPUT_UNDEF_FUNCTION |
4633 | if (p->size == -1) | |
4634 | ASM_OUTPUT_UNDEF_FUNCTION (file, p->name); | |
4635 | else | |
4636 | #endif | |
4637 | { | |
4638 | fputs ("\t.extern\t", file); | |
4639 | assemble_name (file, p->name); | |
4640 | fprintf (file, ", %d\n", p->size); | |
4641 | } | |
cee98a59 MM |
4642 | } |
4643 | } | |
5619cc87 JW |
4644 | } |
4645 | ||
d46c6fce | 4646 | if (TARGET_FILE_SWITCHING) |
5619cc87 | 4647 | { |
cee98a59 MM |
4648 | fprintf (file, "\n\t.text\n"); |
4649 | rewind (asm_out_text_file); | |
4650 | if (ferror (asm_out_text_file)) | |
c831afd5 | 4651 | fatal_io_error (temp_filename); |
cee98a59 MM |
4652 | |
4653 | while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0) | |
4654 | if (fwrite (buffer, 1, len, file) != len) | |
c831afd5 | 4655 | pfatal_with_name (asm_file_name); |
cee98a59 MM |
4656 | |
4657 | if (len < 0) | |
c831afd5 | 4658 | pfatal_with_name (temp_filename); |
cee98a59 MM |
4659 | |
4660 | if (fclose (asm_out_text_file) != 0) | |
c831afd5 | 4661 | pfatal_with_name (temp_filename); |
147255d8 JW |
4662 | |
4663 | #ifdef __MSDOS__ | |
4664 | unlink (temp_filename); | |
4665 | #endif | |
cee98a59 MM |
4666 | } |
4667 | } | |
4668 | ||
9987501f MM |
4669 | \f |
4670 | /* Emit either a label, .comm, or .lcomm directive, and mark | |
4671 | that the symbol is used, so that we don't emit an .extern | |
4672 | for it in mips_asm_file_end. */ | |
4673 | ||
4674 | void | |
4675 | mips_declare_object (stream, name, init_string, final_string, size) | |
4676 | FILE *stream; | |
4677 | char *name; | |
4678 | char *init_string; | |
4679 | char *final_string; | |
4680 | int size; | |
4681 | { | |
4682 | fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */ | |
4683 | assemble_name (stream, name); | |
4684 | fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */ | |
4685 | ||
147255d8 | 4686 | if (TARGET_GP_OPT) |
9987501f MM |
4687 | { |
4688 | tree name_tree = get_identifier (name); | |
4689 | TREE_ASM_WRITTEN (name_tree) = 1; | |
4690 | } | |
4691 | } | |
4692 | ||
dbe9742d MM |
4693 | \f |
4694 | /* Output a double precision value to the assembler. If both the | |
4695 | host and target are IEEE, emit the values in hex. */ | |
4696 | ||
4697 | void | |
4698 | mips_output_double (stream, value) | |
4699 | FILE *stream; | |
4700 | REAL_VALUE_TYPE value; | |
4701 | { | |
4702 | #ifdef REAL_VALUE_TO_TARGET_DOUBLE | |
4703 | long value_long[2]; | |
4704 | REAL_VALUE_TO_TARGET_DOUBLE (value, value_long); | |
4705 | ||
4706 | fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n", | |
4707 | value_long[0], value, value_long[1]); | |
4708 | #else | |
4709 | fprintf (stream, "\t.double\t%.20g\n", value); | |
4710 | #endif | |
4711 | } | |
4712 | ||
4713 | ||
4714 | /* Output a single precision value to the assembler. If both the | |
4715 | host and target are IEEE, emit the values in hex. */ | |
4716 | ||
4717 | void | |
4718 | mips_output_float (stream, value) | |
4719 | FILE *stream; | |
4720 | REAL_VALUE_TYPE value; | |
4721 | { | |
4722 | #ifdef REAL_VALUE_TO_TARGET_SINGLE | |
4723 | long value_long; | |
4724 | REAL_VALUE_TO_TARGET_SINGLE (value, value_long); | |
4725 | ||
4726 | fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value); | |
4727 | #else | |
4728 | fprintf (stream, "\t.float\t%.12g\n", value); | |
4729 | #endif | |
4730 | } | |
4731 | ||
cee98a59 MM |
4732 | \f |
4733 | /* Return the bytes needed to compute the frame pointer from the current | |
4734 | stack pointer. | |
4735 | ||
4736 | Mips stack frames look like: | |
4737 | ||
4738 | Before call After call | |
4739 | +-----------------------+ +-----------------------+ | |
4740 | high | | | | | |
4741 | mem. | | | | | |
4742 | | caller's temps. | | caller's temps. | | |
4743 | | | | | | |
4744 | +-----------------------+ +-----------------------+ | |
4745 | | | | | | |
4746 | | arguments on stack. | | arguments on stack. | | |
4747 | | | | | | |
4748 | +-----------------------+ +-----------------------+ | |
4749 | | 4 words to save | | 4 words to save | | |
4750 | | arguments passed | | arguments passed | | |
4751 | | in registers, even | | in registers, even | | |
ffa9d0b1 | 4752 | SP->| if not passed. | VFP->| if not passed. | |
cee98a59 | 4753 | +-----------------------+ +-----------------------+ |
cee98a59 MM |
4754 | | | |
4755 | | fp register save | | |
4756 | | | | |
4757 | +-----------------------+ | |
4758 | | | | |
4759 | | gp register save | | |
4760 | | | | |
4761 | +-----------------------+ | |
4762 | | | | |
ab78d4a8 MM |
4763 | | local variables | |
4764 | | | | |
4765 | +-----------------------+ | |
4766 | | | | |
cee98a59 MM |
4767 | | alloca allocations | |
4768 | | | | |
4769 | +-----------------------+ | |
4770 | | | | |
ffa9d0b1 JW |
4771 | | GP save for V.4 abi | |
4772 | | | | |
4773 | +-----------------------+ | |
4774 | | | | |
cee98a59 MM |
4775 | | arguments on stack | |
4776 | | | | |
4777 | +-----------------------+ | |
4778 | | 4 words to save | | |
4779 | | arguments passed | | |
4780 | | in registers, even | | |
4781 | low SP->| if not passed. | | |
4782 | memory +-----------------------+ | |
4783 | ||
4784 | */ | |
4785 | ||
7bea35e7 | 4786 | long |
cee98a59 MM |
4787 | compute_frame_size (size) |
4788 | int size; /* # of var. bytes allocated */ | |
4789 | { | |
4790 | int regno; | |
7bea35e7 MM |
4791 | long total_size; /* # bytes that the entire frame takes up */ |
4792 | long var_size; /* # bytes that variables take up */ | |
4793 | long args_size; /* # bytes that outgoing arguments take up */ | |
4794 | long extra_size; /* # extra bytes */ | |
4795 | long gp_reg_rounded; /* # bytes needed to store gp after rounding */ | |
4796 | long gp_reg_size; /* # bytes needed to store gp regs */ | |
4797 | long fp_reg_size; /* # bytes needed to store fp regs */ | |
4798 | long mask; /* mask of saved gp registers */ | |
4799 | long fmask; /* mask of saved fp registers */ | |
4800 | int fp_inc; /* 1 or 2 depending on the size of fp regs */ | |
4801 | long fp_bits; /* bitmask to use for each fp register */ | |
cee98a59 | 4802 | |
cee98a59 MM |
4803 | gp_reg_size = 0; |
4804 | fp_reg_size = 0; | |
4805 | mask = 0; | |
4806 | fmask = 0; | |
ab78d4a8 MM |
4807 | extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0)); |
4808 | var_size = MIPS_STACK_ALIGN (size); | |
4809 | args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size); | |
4810 | ||
4811 | /* The MIPS 3.0 linker does not like functions that dynamically | |
4812 | allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it | |
4813 | looks like we are trying to create a second frame pointer to the | |
4814 | function, so allocate some stack space to make it happy. */ | |
4815 | ||
4816 | if (args_size == 0 && current_function_calls_alloca) | |
258d81a8 | 4817 | args_size = 4*UNITS_PER_WORD; |
ab78d4a8 MM |
4818 | |
4819 | total_size = var_size + args_size + extra_size; | |
cee98a59 MM |
4820 | |
4821 | /* Calculate space needed for gp registers. */ | |
4822 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) | |
4823 | { | |
4824 | if (MUST_SAVE_REGISTER (regno)) | |
4825 | { | |
4826 | gp_reg_size += UNITS_PER_WORD; | |
7bea35e7 | 4827 | mask |= 1L << (regno - GP_REG_FIRST); |
cee98a59 MM |
4828 | } |
4829 | } | |
4830 | ||
4831 | /* Calculate space needed for fp registers. */ | |
46299de9 | 4832 | if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) |
cee98a59 MM |
4833 | { |
4834 | fp_inc = 1; | |
4835 | fp_bits = 1; | |
4836 | } | |
4837 | else | |
4838 | { | |
4839 | fp_inc = 2; | |
4840 | fp_bits = 3; | |
4841 | } | |
4842 | ||
4843 | for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += fp_inc) | |
4844 | { | |
4845 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
4846 | { | |
147255d8 | 4847 | fp_reg_size += fp_inc * UNITS_PER_FPREG; |
cee98a59 MM |
4848 | fmask |= fp_bits << (regno - FP_REG_FIRST); |
4849 | } | |
4850 | } | |
4851 | ||
4852 | gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size); | |
46299de9 | 4853 | total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size); |
cee98a59 | 4854 | |
33563487 JW |
4855 | /* The gp reg is caller saved in the 32 bit ABI, so there is no need |
4856 | for leaf routines (total_size == extra_size) to save the gp reg. | |
4857 | The gp reg is callee saved in the 64 bit ABI, so all routines must | |
4858 | save the gp reg. */ | |
293a36eb | 4859 | if (total_size == extra_size && (mips_abi == ABI_32 || mips_abi == ABI_EABI)) |
cee98a59 | 4860 | total_size = extra_size = 0; |
ffa9d0b1 JW |
4861 | else if (TARGET_ABICALLS) |
4862 | { | |
4863 | /* Add the context-pointer to the saved registers. */ | |
4864 | gp_reg_size += UNITS_PER_WORD; | |
4865 | mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST); | |
4866 | total_size -= gp_reg_rounded; | |
4867 | gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size); | |
4868 | total_size += gp_reg_rounded; | |
4869 | } | |
cee98a59 | 4870 | |
33563487 JW |
4871 | /* Add in space reserved on the stack by the callee for storing arguments |
4872 | passed in registers. */ | |
ade6c319 | 4873 | if (mips_abi != ABI_32) |
33563487 JW |
4874 | total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size); |
4875 | ||
cee98a59 MM |
4876 | /* Save other computed information. */ |
4877 | current_frame_info.total_size = total_size; | |
4878 | current_frame_info.var_size = var_size; | |
4879 | current_frame_info.args_size = args_size; | |
4880 | current_frame_info.extra_size = extra_size; | |
4881 | current_frame_info.gp_reg_size = gp_reg_size; | |
4882 | current_frame_info.fp_reg_size = fp_reg_size; | |
4883 | current_frame_info.mask = mask; | |
4884 | current_frame_info.fmask = fmask; | |
4885 | current_frame_info.initialized = reload_completed; | |
0fb5ac6f | 4886 | current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD; |
147255d8 | 4887 | current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG); |
cee98a59 MM |
4888 | |
4889 | if (mask) | |
4890 | { | |
33563487 JW |
4891 | unsigned long offset = (args_size + extra_size + var_size |
4892 | + gp_reg_size - UNITS_PER_WORD); | |
cee98a59 MM |
4893 | current_frame_info.gp_sp_offset = offset; |
4894 | current_frame_info.gp_save_offset = offset - total_size; | |
4895 | } | |
258d81a8 MM |
4896 | else |
4897 | { | |
4898 | current_frame_info.gp_sp_offset = 0; | |
4899 | current_frame_info.gp_save_offset = 0; | |
4900 | } | |
4901 | ||
cee98a59 MM |
4902 | |
4903 | if (fmask) | |
4904 | { | |
147255d8 JW |
4905 | unsigned long offset = (args_size + extra_size + var_size |
4906 | + gp_reg_rounded + fp_reg_size | |
4907 | - fp_inc * UNITS_PER_FPREG); | |
cee98a59 | 4908 | current_frame_info.fp_sp_offset = offset; |
a94dbf2c | 4909 | current_frame_info.fp_save_offset = offset - total_size; |
cee98a59 | 4910 | } |
258d81a8 MM |
4911 | else |
4912 | { | |
4913 | current_frame_info.fp_sp_offset = 0; | |
4914 | current_frame_info.fp_save_offset = 0; | |
4915 | } | |
cee98a59 MM |
4916 | |
4917 | /* Ok, we're done. */ | |
4918 | return total_size; | |
4919 | } | |
4920 | ||
4921 | \f | |
7bea35e7 MM |
4922 | /* Common code to emit the insns (or to write the instructions to a file) |
4923 | to save/restore registers. | |
cee98a59 | 4924 | |
7bea35e7 MM |
4925 | Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg) |
4926 | is not modified within save_restore_insns. */ | |
4927 | ||
4928 | #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0) | |
4929 | ||
4930 | static void | |
4931 | save_restore_insns (store_p, large_reg, large_offset, file) | |
4932 | int store_p; /* true if this is prologue */ | |
4933 | rtx large_reg; /* register holding large offset constant or NULL */ | |
4934 | long large_offset; /* large constant offset value */ | |
4935 | FILE *file; /* file to write instructions to instead of making RTL */ | |
cee98a59 | 4936 | { |
7bea35e7 MM |
4937 | long mask = current_frame_info.mask; |
4938 | long fmask = current_frame_info.fmask; | |
cee98a59 | 4939 | int regno; |
7bea35e7 MM |
4940 | rtx base_reg_rtx; |
4941 | long base_offset; | |
4942 | long gp_offset; | |
4943 | long fp_offset; | |
4944 | long end_offset; | |
141719a8 | 4945 | rtx insn; |
7bea35e7 MM |
4946 | |
4947 | if (frame_pointer_needed && !BITSET_P (mask, FRAME_POINTER_REGNUM - GP_REG_FIRST)) | |
4948 | abort (); | |
cee98a59 MM |
4949 | |
4950 | if (mask == 0 && fmask == 0) | |
4951 | return; | |
4952 | ||
cee98a59 MM |
4953 | /* Save registers starting from high to low. The debuggers prefer |
4954 | at least the return register be stored at func+4, and also it | |
4955 | allows us not to need a nop in the epilog if at least one | |
4956 | register is reloaded in addition to return address. */ | |
4957 | ||
7bea35e7 MM |
4958 | /* Save GP registers if needed. */ |
4959 | if (mask) | |
cee98a59 | 4960 | { |
7bea35e7 MM |
4961 | /* Pick which pointer to use as a base register. For small |
4962 | frames, just use the stack pointer. Otherwise, use a | |
4963 | temporary register. Save 2 cycles if the save area is near | |
4964 | the end of a large frame, by reusing the constant created in | |
4965 | the prologue/epilogue to adjust the stack frame. */ | |
cee98a59 | 4966 | |
7bea35e7 MM |
4967 | gp_offset = current_frame_info.gp_sp_offset; |
4968 | end_offset = gp_offset - (current_frame_info.gp_reg_size - UNITS_PER_WORD); | |
4969 | ||
4970 | if (gp_offset < 0 || end_offset < 0) | |
4971 | fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.", | |
4972 | gp_offset, end_offset); | |
4973 | ||
4974 | else if (gp_offset < 32768) | |
4975 | { | |
4976 | base_reg_rtx = stack_pointer_rtx; | |
4977 | base_offset = 0; | |
cee98a59 | 4978 | } |
cee98a59 | 4979 | |
7bea35e7 MM |
4980 | else if (large_reg != (rtx)0 |
4981 | && (((unsigned long)(large_offset - gp_offset)) < 32768) | |
4982 | && (((unsigned long)(large_offset - end_offset)) < 32768)) | |
4983 | { | |
4984 | base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); | |
4985 | base_offset = large_offset; | |
4986 | if (file == (FILE *)0) | |
147255d8 JW |
4987 | { |
4988 | if (TARGET_LONG64) | |
141719a8 | 4989 | insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx)); |
147255d8 | 4990 | else |
141719a8 | 4991 | insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx)); |
4b7e467b JW |
4992 | if (store_p) |
4993 | RTX_FRAME_RELATED_P (insn) = 1; | |
147255d8 | 4994 | } |
7bea35e7 | 4995 | else |
147255d8 JW |
4996 | fprintf (file, "\t%s\t%s,%s,%s\n", |
4997 | TARGET_LONG64 ? "daddu" : "addu", | |
7bea35e7 MM |
4998 | reg_names[MIPS_TEMP2_REGNUM], |
4999 | reg_names[REGNO (large_reg)], | |
5000 | reg_names[STACK_POINTER_REGNUM]); | |
5001 | } | |
cee98a59 | 5002 | |
7bea35e7 | 5003 | else |
cee98a59 | 5004 | { |
7bea35e7 MM |
5005 | base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); |
5006 | base_offset = gp_offset; | |
5007 | if (file == (FILE *)0) | |
cee98a59 | 5008 | { |
141719a8 | 5009 | insn = emit_move_insn (base_reg_rtx, GEN_INT (gp_offset)); |
4b7e467b JW |
5010 | if (store_p) |
5011 | RTX_FRAME_RELATED_P (insn) = 1; | |
147255d8 | 5012 | if (TARGET_LONG64) |
141719a8 | 5013 | insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx)); |
147255d8 | 5014 | else |
141719a8 | 5015 | insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx)); |
4b7e467b JW |
5016 | if (store_p) |
5017 | RTX_FRAME_RELATED_P (insn) = 1; | |
cee98a59 | 5018 | } |
7bea35e7 | 5019 | else |
147255d8 | 5020 | fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n", |
7bea35e7 MM |
5021 | reg_names[MIPS_TEMP2_REGNUM], |
5022 | (long)base_offset, | |
5023 | (long)base_offset, | |
147255d8 | 5024 | TARGET_LONG64 ? "daddu" : "addu", |
7bea35e7 MM |
5025 | reg_names[MIPS_TEMP2_REGNUM], |
5026 | reg_names[MIPS_TEMP2_REGNUM], | |
5027 | reg_names[STACK_POINTER_REGNUM]); | |
cee98a59 | 5028 | } |
0fb5ac6f | 5029 | |
0fb5ac6f MM |
5030 | for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) |
5031 | { | |
7bea35e7 | 5032 | if (BITSET_P (mask, regno - GP_REG_FIRST)) |
0fb5ac6f | 5033 | { |
7bea35e7 MM |
5034 | if (file == (FILE *)0) |
5035 | { | |
147255d8 JW |
5036 | rtx reg_rtx = gen_rtx (REG, word_mode, regno); |
5037 | rtx mem_rtx = gen_rtx (MEM, word_mode, | |
7bea35e7 MM |
5038 | gen_rtx (PLUS, Pmode, base_reg_rtx, |
5039 | GEN_INT (gp_offset - base_offset))); | |
0fb5ac6f | 5040 | |
7bea35e7 | 5041 | if (store_p) |
a94dbf2c | 5042 | { |
141719a8 | 5043 | insn = emit_move_insn (mem_rtx, reg_rtx); |
469ac993 | 5044 | RTX_FRAME_RELATED_P (insn) = 1; |
a94dbf2c | 5045 | } |
ade6c319 | 5046 | else if (!TARGET_ABICALLS || mips_abi != ABI_32 |
ffa9d0b1 | 5047 | || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) |
7bea35e7 MM |
5048 | emit_move_insn (reg_rtx, mem_rtx); |
5049 | } | |
0fb5ac6f | 5050 | else |
ffa9d0b1 | 5051 | { |
ade6c319 | 5052 | if (store_p || !TARGET_ABICALLS || mips_abi != ABI_32 |
ffa9d0b1 JW |
5053 | || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) |
5054 | fprintf (file, "\t%s\t%s,%ld(%s)\n", | |
147255d8 JW |
5055 | (TARGET_64BIT |
5056 | ? (store_p) ? "sd" : "ld" | |
5057 | : (store_p) ? "sw" : "lw"), | |
ffa9d0b1 JW |
5058 | reg_names[regno], |
5059 | gp_offset - base_offset, | |
5060 | reg_names[REGNO(base_reg_rtx)]); | |
0fb5ac6f | 5061 | |
ffa9d0b1 | 5062 | } |
0fb5ac6f MM |
5063 | gp_offset -= UNITS_PER_WORD; |
5064 | } | |
5065 | } | |
5066 | } | |
7bea35e7 MM |
5067 | else |
5068 | { | |
ddd5a7c1 | 5069 | base_reg_rtx = (rtx)0; /* Make sure these are initialized */ |
7bea35e7 MM |
5070 | base_offset = 0; |
5071 | } | |
0fb5ac6f | 5072 | |
7bea35e7 | 5073 | /* Save floating point registers if needed. */ |
0fb5ac6f MM |
5074 | if (fmask) |
5075 | { | |
46299de9 | 5076 | int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2; |
147255d8 | 5077 | int fp_size = fp_inc * UNITS_PER_FPREG; |
0fb5ac6f | 5078 | |
7bea35e7 MM |
5079 | /* Pick which pointer to use as a base register. */ |
5080 | fp_offset = current_frame_info.fp_sp_offset; | |
147255d8 | 5081 | end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size); |
7bea35e7 MM |
5082 | |
5083 | if (fp_offset < 0 || end_offset < 0) | |
5084 | fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.", | |
5085 | fp_offset, end_offset); | |
5086 | ||
5087 | else if (fp_offset < 32768) | |
5088 | { | |
5089 | base_reg_rtx = stack_pointer_rtx; | |
5090 | base_offset = 0; | |
5091 | } | |
5092 | ||
5093 | else if (base_reg_rtx != (rtx)0 | |
5094 | && (((unsigned long)(base_offset - fp_offset)) < 32768) | |
5095 | && (((unsigned long)(base_offset - end_offset)) < 32768)) | |
5096 | { | |
5097 | ; /* already set up for gp registers above */ | |
5098 | } | |
5099 | ||
5100 | else if (large_reg != (rtx)0 | |
5101 | && (((unsigned long)(large_offset - fp_offset)) < 32768) | |
5102 | && (((unsigned long)(large_offset - end_offset)) < 32768)) | |
5103 | { | |
5104 | base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); | |
5105 | base_offset = large_offset; | |
5106 | if (file == (FILE *)0) | |
147255d8 JW |
5107 | { |
5108 | if (TARGET_LONG64) | |
141719a8 | 5109 | insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx)); |
147255d8 | 5110 | else |
141719a8 | 5111 | insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx)); |
4b7e467b JW |
5112 | if (store_p) |
5113 | RTX_FRAME_RELATED_P (insn) = 1; | |
147255d8 | 5114 | } |
7bea35e7 | 5115 | else |
147255d8 JW |
5116 | fprintf (file, "\t%s\t%s,%s,%s\n", |
5117 | TARGET_LONG64 ? "daddu" : "addu", | |
7bea35e7 MM |
5118 | reg_names[MIPS_TEMP2_REGNUM], |
5119 | reg_names[REGNO (large_reg)], | |
5120 | reg_names[STACK_POINTER_REGNUM]); | |
5121 | } | |
5122 | ||
5123 | else | |
5124 | { | |
5125 | base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); | |
5126 | base_offset = fp_offset; | |
5127 | if (file == (FILE *)0) | |
5128 | { | |
141719a8 | 5129 | insn = emit_move_insn (base_reg_rtx, GEN_INT (fp_offset)); |
4b7e467b JW |
5130 | if (store_p) |
5131 | RTX_FRAME_RELATED_P (insn) = 1; | |
147255d8 | 5132 | if (TARGET_LONG64) |
141719a8 | 5133 | insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx)); |
147255d8 | 5134 | else |
141719a8 | 5135 | insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx)); |
4b7e467b JW |
5136 | if (store_p) |
5137 | RTX_FRAME_RELATED_P (insn) = 1; | |
7bea35e7 MM |
5138 | } |
5139 | else | |
147255d8 | 5140 | fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n", |
7bea35e7 MM |
5141 | reg_names[MIPS_TEMP2_REGNUM], |
5142 | (long)base_offset, | |
5143 | (long)base_offset, | |
147255d8 | 5144 | TARGET_LONG64 ? "daddu" : "addu", |
7bea35e7 MM |
5145 | reg_names[MIPS_TEMP2_REGNUM], |
5146 | reg_names[MIPS_TEMP2_REGNUM], | |
5147 | reg_names[STACK_POINTER_REGNUM]); | |
5148 | } | |
5149 | ||
0fb5ac6f MM |
5150 | for (regno = FP_REG_LAST-1; regno >= FP_REG_FIRST; regno -= fp_inc) |
5151 | { | |
7bea35e7 | 5152 | if (BITSET_P (fmask, regno - FP_REG_FIRST)) |
0fb5ac6f | 5153 | { |
7bea35e7 MM |
5154 | if (file == (FILE *)0) |
5155 | { | |
46299de9 ILT |
5156 | enum machine_mode sz = |
5157 | TARGET_SINGLE_FLOAT ? SFmode : DFmode; | |
5158 | rtx reg_rtx = gen_rtx (REG, sz, regno); | |
5159 | rtx mem_rtx = gen_rtx (MEM, sz, | |
7bea35e7 MM |
5160 | gen_rtx (PLUS, Pmode, base_reg_rtx, |
5161 | GEN_INT (fp_offset - base_offset))); | |
0fb5ac6f | 5162 | |
7bea35e7 | 5163 | if (store_p) |
a94dbf2c | 5164 | { |
141719a8 | 5165 | insn = emit_move_insn (mem_rtx, reg_rtx); |
469ac993 | 5166 | RTX_FRAME_RELATED_P (insn) = 1; |
a94dbf2c | 5167 | } |
7bea35e7 MM |
5168 | else |
5169 | emit_move_insn (reg_rtx, mem_rtx); | |
5170 | } | |
0fb5ac6f | 5171 | else |
7bea35e7 | 5172 | fprintf (file, "\t%s\t%s,%ld(%s)\n", |
46299de9 ILT |
5173 | (TARGET_SINGLE_FLOAT |
5174 | ? ((store_p) ? "s.s" : "l.s") | |
5175 | : ((store_p) ? "s.d" : "l.d")), | |
7bea35e7 MM |
5176 | reg_names[regno], |
5177 | fp_offset - base_offset, | |
5178 | reg_names[REGNO(base_reg_rtx)]); | |
5179 | ||
0fb5ac6f | 5180 | |
147255d8 | 5181 | fp_offset -= fp_size; |
0fb5ac6f MM |
5182 | } |
5183 | } | |
5184 | } | |
5185 | } | |
5186 | ||
cee98a59 MM |
5187 | \f |
5188 | /* Set up the stack and frame (if desired) for the function. */ | |
5189 | ||
5190 | void | |
5191 | function_prologue (file, size) | |
5192 | FILE *file; | |
5193 | int size; | |
5194 | { | |
10389f52 | 5195 | char *fnname; |
7bea35e7 | 5196 | long tsize = current_frame_info.total_size; |
cee98a59 MM |
5197 | |
5198 | ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl)); | |
8a2d2f90 | 5199 | |
8bd8e198 | 5200 | #ifdef SDB_DEBUGGING_INFO |
af173031 | 5201 | if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG) |
8a2d2f90 | 5202 | ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl)); |
8bd8e198 | 5203 | #endif |
cee98a59 | 5204 | |
993cd990 JW |
5205 | inside_function = 1; |
5206 | ||
5207 | #ifndef FUNCTION_NAME_ALREADY_DECLARED | |
10389f52 RK |
5208 | /* Get the function name the same way that toplev.c does before calling |
5209 | assemble_start_function. This is needed so that the name used here | |
5210 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
5211 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
5212 | ||
cee98a59 | 5213 | fputs ("\t.ent\t", file); |
10389f52 | 5214 | assemble_name (file, fnname); |
cee98a59 | 5215 | fputs ("\n", file); |
7bea35e7 | 5216 | |
10389f52 | 5217 | assemble_name (file, fnname); |
cee98a59 | 5218 | fputs (":\n", file); |
993cd990 | 5219 | #endif |
cee98a59 | 5220 | |
ffa9d0b1 | 5221 | fprintf (file, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n", |
ab78d4a8 MM |
5222 | reg_names[ (frame_pointer_needed) ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ], |
5223 | tsize, | |
0fb5ac6f MM |
5224 | reg_names[31 + GP_REG_FIRST], |
5225 | current_frame_info.var_size, | |
5226 | current_frame_info.num_gp, | |
5227 | current_frame_info.num_fp, | |
5228 | current_function_outgoing_args_size, | |
5229 | current_frame_info.extra_size); | |
5230 | ||
5231 | fprintf (file, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n", | |
5232 | current_frame_info.mask, | |
5233 | current_frame_info.gp_save_offset, | |
5234 | current_frame_info.fmask, | |
5235 | current_frame_info.fp_save_offset); | |
ffa9d0b1 | 5236 | |
ade6c319 | 5237 | if (TARGET_ABICALLS && mips_abi == ABI_32) |
ffa9d0b1 JW |
5238 | { |
5239 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; | |
5240 | ||
5241 | fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n", | |
5242 | reg_names[PIC_FUNCTION_ADDR_REGNUM]); | |
5243 | if (tsize > 0) | |
5244 | { | |
147255d8 JW |
5245 | fprintf (file, "\t%s\t%s,%s,%d\n", |
5246 | (TARGET_LONG64 ? "dsubu" : "subu"), | |
5247 | sp_str, sp_str, tsize); | |
ffa9d0b1 JW |
5248 | fprintf (file, "\t.cprestore %d\n", current_frame_info.args_size); |
5249 | } | |
0021b564 JM |
5250 | |
5251 | if (dwarf2out_do_frame ()) | |
5252 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize); | |
ffa9d0b1 | 5253 | } |
0fb5ac6f MM |
5254 | } |
5255 | ||
5256 | \f | |
5257 | /* Expand the prologue into a bunch of separate insns. */ | |
5258 | ||
5259 | void | |
5260 | mips_expand_prologue () | |
5261 | { | |
5262 | int regno; | |
7bea35e7 | 5263 | long tsize; |
3f1f8d8c MM |
5264 | rtx tmp_rtx = (rtx)0; |
5265 | char *arg_name = (char *)0; | |
5266 | tree fndecl = current_function_decl; | |
5267 | tree fntype = TREE_TYPE (fndecl); | |
1b2202b8 | 5268 | tree fnargs = DECL_ARGUMENTS (fndecl); |
3f1f8d8c MM |
5269 | rtx next_arg_reg; |
5270 | int i; | |
0fb5ac6f MM |
5271 | tree next_arg; |
5272 | tree cur_arg; | |
0fb5ac6f MM |
5273 | CUMULATIVE_ARGS args_so_far; |
5274 | ||
518e5ce8 JW |
5275 | /* If struct value address is treated as the first argument, make it so. */ |
5276 | if (aggregate_value_p (DECL_RESULT (fndecl)) | |
5277 | && ! current_function_returns_pcc_struct | |
5278 | && struct_value_incoming_rtx == 0) | |
5279 | { | |
5280 | tree type = build_pointer_type (fntype); | |
5281 | tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type); | |
5282 | DECL_ARG_TYPE (function_result_decl) = type; | |
5283 | TREE_CHAIN (function_result_decl) = fnargs; | |
5284 | fnargs = function_result_decl; | |
5285 | } | |
5286 | ||
cee98a59 | 5287 | /* Determine the last argument, and get its name. */ |
3f1f8d8c | 5288 | |
030d2f01 | 5289 | INIT_CUMULATIVE_ARGS (args_so_far, fntype, (rtx)0, 0); |
3f1f8d8c MM |
5290 | regno = GP_ARG_FIRST; |
5291 | ||
cee98a59 MM |
5292 | for (cur_arg = fnargs; cur_arg != (tree)0; cur_arg = next_arg) |
5293 | { | |
6f673359 JW |
5294 | tree passed_type = DECL_ARG_TYPE (cur_arg); |
5295 | enum machine_mode passed_mode = TYPE_MODE (passed_type); | |
5296 | rtx entry_parm; | |
5297 | ||
e0c228da | 5298 | if (TREE_ADDRESSABLE (passed_type)) |
6f673359 JW |
5299 | { |
5300 | passed_type = build_pointer_type (passed_type); | |
5301 | passed_mode = Pmode; | |
5302 | } | |
5303 | ||
5304 | entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1); | |
3f1f8d8c MM |
5305 | |
5306 | if (entry_parm) | |
5307 | { | |
5308 | int words; | |
5309 | ||
5310 | /* passed in a register, so will get homed automatically */ | |
5311 | if (GET_MODE (entry_parm) == BLKmode) | |
6f673359 | 5312 | words = (int_size_in_bytes (passed_type) + 3) / 4; |
3f1f8d8c MM |
5313 | else |
5314 | words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4; | |
5315 | ||
5316 | regno = REGNO (entry_parm) + words - 1; | |
5317 | } | |
5318 | else | |
5319 | { | |
5320 | regno = GP_ARG_LAST+1; | |
5321 | break; | |
5322 | } | |
5323 | ||
6f673359 | 5324 | FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1); |
3f1f8d8c | 5325 | |
cee98a59 MM |
5326 | next_arg = TREE_CHAIN (cur_arg); |
5327 | if (next_arg == (tree)0) | |
5328 | { | |
5329 | if (DECL_NAME (cur_arg)) | |
5330 | arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg)); | |
5331 | ||
5332 | break; | |
5333 | } | |
5334 | } | |
5335 | ||
3f1f8d8c MM |
5336 | /* In order to pass small structures by value in registers |
5337 | compatibly with the MIPS compiler, we need to shift the value | |
5338 | into the high part of the register. Function_arg has encoded a | |
5339 | PARALLEL rtx, holding a vector of adjustments to be made as the | |
5340 | next_arg_reg variable, so we split up the insns, and emit them | |
5341 | separately. */ | |
cee98a59 | 5342 | |
3f1f8d8c MM |
5343 | next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1); |
5344 | if (next_arg_reg != (rtx)0 && GET_CODE (next_arg_reg) == PARALLEL) | |
5345 | { | |
5346 | rtvec adjust = XVEC (next_arg_reg, 0); | |
5347 | int num = GET_NUM_ELEM (adjust); | |
cee98a59 | 5348 | |
3f1f8d8c | 5349 | for (i = 0; i < num; i++) |
cee98a59 | 5350 | { |
3f1f8d8c MM |
5351 | rtx pattern = RTVEC_ELT (adjust, i); |
5352 | if (GET_CODE (pattern) != SET | |
5353 | || GET_CODE (SET_SRC (pattern)) != ASHIFT) | |
5354 | abort_with_insn (pattern, "Insn is not a shift"); | |
cee98a59 | 5355 | |
3f1f8d8c MM |
5356 | PUT_CODE (SET_SRC (pattern), ASHIFTRT); |
5357 | emit_insn (pattern); | |
cee98a59 | 5358 | } |
3f1f8d8c | 5359 | } |
cee98a59 | 5360 | |
ffa9d0b1 JW |
5361 | tsize = compute_frame_size (get_frame_size ()); |
5362 | ||
3f1f8d8c MM |
5363 | /* If this function is a varargs function, store any registers that |
5364 | would normally hold arguments ($4 - $7) on the stack. */ | |
ade6c319 | 5365 | if (mips_abi == ABI_32 |
33563487 JW |
5366 | && ((TYPE_ARG_TYPES (fntype) != 0 |
5367 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node)) | |
5368 | || (arg_name != (char *)0 | |
5369 | && ((arg_name[0] == '_' && strcmp (arg_name, "__builtin_va_alist") == 0) | |
5370 | || (arg_name[0] == 'v' && strcmp (arg_name, "va_alist") == 0))))) | |
3f1f8d8c | 5371 | { |
ffa9d0b1 JW |
5372 | int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD; |
5373 | rtx ptr = stack_pointer_rtx; | |
5374 | ||
5375 | /* If we are doing svr4-abi, sp has already been decremented by tsize. */ | |
ade6c319 | 5376 | if (TARGET_ABICALLS) |
ffa9d0b1 JW |
5377 | offset += tsize; |
5378 | ||
0fb5ac6f | 5379 | for (; regno <= GP_ARG_LAST; regno++) |
cee98a59 | 5380 | { |
ffa9d0b1 JW |
5381 | if (offset != 0) |
5382 | ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset)); | |
147255d8 JW |
5383 | emit_move_insn (gen_rtx (MEM, word_mode, ptr), |
5384 | gen_rtx (REG, word_mode, regno)); | |
ffa9d0b1 | 5385 | offset += UNITS_PER_WORD; |
cee98a59 MM |
5386 | } |
5387 | } | |
5388 | ||
cee98a59 MM |
5389 | if (tsize > 0) |
5390 | { | |
0fb5ac6f | 5391 | rtx tsize_rtx = GEN_INT (tsize); |
cee98a59 | 5392 | |
ffa9d0b1 | 5393 | /* If we are doing svr4-abi, sp move is done by function_prologue. */ |
ade6c319 | 5394 | if (!TARGET_ABICALLS || mips_abi != ABI_32) |
0fb5ac6f | 5395 | { |
a94dbf2c JM |
5396 | rtx insn; |
5397 | ||
ffa9d0b1 JW |
5398 | if (tsize > 32767) |
5399 | { | |
147255d8 | 5400 | tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM); |
119f2738 JW |
5401 | |
5402 | /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P | |
5403 | bit, so make sure that we don't emit anything that can be | |
5404 | split. */ | |
9d1cf1d9 JW |
5405 | /* ??? There is no DImode ori immediate pattern, so we can only |
5406 | do this for 32 bit code. */ | |
5407 | if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode) | |
119f2738 JW |
5408 | { |
5409 | insn = emit_move_insn (tmp_rtx, | |
5410 | GEN_INT (tsize & 0xffff0000)); | |
5411 | RTX_FRAME_RELATED_P (insn) = 1; | |
5412 | insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx, | |
5413 | GEN_INT (tsize & 0x0000ffff))); | |
5414 | RTX_FRAME_RELATED_P (insn) = 1; | |
5415 | } | |
5416 | else | |
5417 | { | |
5418 | insn = emit_move_insn (tmp_rtx, tsize_rtx); | |
5419 | RTX_FRAME_RELATED_P (insn) = 1; | |
5420 | } | |
5421 | ||
ffa9d0b1 JW |
5422 | tsize_rtx = tmp_rtx; |
5423 | } | |
cee98a59 | 5424 | |
147255d8 | 5425 | if (TARGET_LONG64) |
a94dbf2c JM |
5426 | insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, |
5427 | tsize_rtx)); | |
147255d8 | 5428 | else |
a94dbf2c JM |
5429 | insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, |
5430 | tsize_rtx)); | |
5431 | ||
469ac993 | 5432 | RTX_FRAME_RELATED_P (insn) = 1; |
ffa9d0b1 | 5433 | } |
cee98a59 | 5434 | |
7bea35e7 | 5435 | save_restore_insns (TRUE, tmp_rtx, tsize, (FILE *)0); |
cee98a59 | 5436 | |
0fb5ac6f | 5437 | if (frame_pointer_needed) |
147255d8 | 5438 | { |
a94dbf2c JM |
5439 | rtx insn; |
5440 | ||
147255d8 | 5441 | if (TARGET_64BIT) |
a94dbf2c | 5442 | insn= emit_insn (gen_movdi (frame_pointer_rtx, stack_pointer_rtx)); |
147255d8 | 5443 | else |
a94dbf2c JM |
5444 | insn= emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx)); |
5445 | ||
469ac993 | 5446 | RTX_FRAME_RELATED_P (insn) = 1; |
147255d8 | 5447 | } |
33563487 | 5448 | |
ade6c319 | 5449 | if (TARGET_ABICALLS && mips_abi != ABI_32) |
33563487 | 5450 | emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0))); |
cee98a59 | 5451 | } |
d8d5b1e1 MM |
5452 | |
5453 | /* If we are profiling, make sure no instructions are scheduled before | |
5454 | the call to mcount. */ | |
5455 | ||
5456 | if (profile_flag || profile_block_flag) | |
5457 | emit_insn (gen_blockage ()); | |
cee98a59 MM |
5458 | } |
5459 | ||
5460 | \f | |
5461 | /* Do any necessary cleanup after a function to restore stack, frame, and regs. */ | |
5462 | ||
b5e9dd03 | 5463 | #define RA_MASK ((long) 0x80000000) /* 1 << 31 */ |
4d889da9 | 5464 | #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) |
b5e9dd03 | 5465 | |
cee98a59 MM |
5466 | void |
5467 | function_epilogue (file, size) | |
5468 | FILE *file; | |
5469 | int size; | |
5470 | { | |
10389f52 | 5471 | char *fnname; |
cee98a59 | 5472 | |
993cd990 | 5473 | #ifndef FUNCTION_NAME_ALREADY_DECLARED |
10389f52 RK |
5474 | /* Get the function name the same way that toplev.c does before calling |
5475 | assemble_start_function. This is needed so that the name used here | |
5476 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
5477 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
5478 | ||
cee98a59 | 5479 | fputs ("\t.end\t", file); |
10389f52 | 5480 | assemble_name (file, fnname); |
cee98a59 | 5481 | fputs ("\n", file); |
993cd990 | 5482 | #endif |
cee98a59 MM |
5483 | |
5484 | if (TARGET_STATS) | |
5485 | { | |
5486 | int num_gp_regs = current_frame_info.gp_reg_size / 4; | |
5487 | int num_fp_regs = current_frame_info.fp_reg_size / 8; | |
5488 | int num_regs = num_gp_regs + num_fp_regs; | |
10389f52 | 5489 | char *name = fnname; |
ab78d4a8 MM |
5490 | |
5491 | if (name[0] == '*') | |
5492 | name++; | |
cee98a59 MM |
5493 | |
5494 | dslots_load_total += num_regs; | |
5495 | ||
cee98a59 | 5496 | fprintf (stderr, |
ddd8ab48 | 5497 | "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d", |
ab78d4a8 | 5498 | name, |
cee98a59 | 5499 | (frame_pointer_needed) ? 'y' : 'n', |
b5e9dd03 | 5500 | ((current_frame_info.mask & RA_MASK) != 0) ? 'n' : 'y', |
cee98a59 MM |
5501 | (current_function_calls_alloca) ? 'y' : 'n', |
5502 | (current_function_calls_setjmp) ? 'y' : 'n', | |
5503 | (long)current_frame_info.total_size, | |
5504 | (long)current_function_outgoing_args_size, | |
5505 | num_gp_regs, num_fp_regs, | |
5506 | dslots_load_total, dslots_load_filled, | |
5507 | dslots_jump_total, dslots_jump_filled, | |
5508 | num_refs[0], num_refs[1], num_refs[2]); | |
ddd8ab48 | 5509 | |
6f3c667f MM |
5510 | if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs) |
5511 | { | |
5512 | fprintf (stderr, " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs); | |
5513 | prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS; | |
5514 | } | |
ddd8ab48 | 5515 | |
6f3c667f MM |
5516 | if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs) |
5517 | { | |
5518 | fprintf (stderr, " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs); | |
5519 | prev_half_pic_refs = HALF_PIC_NUMBER_REFS; | |
5520 | } | |
ddd8ab48 MM |
5521 | |
5522 | fputc ('\n', stderr); | |
cee98a59 MM |
5523 | } |
5524 | ||
5525 | /* Reset state info for each function. */ | |
5526 | inside_function = FALSE; | |
5527 | ignore_line_number = FALSE; | |
5528 | dslots_load_total = 0; | |
5529 | dslots_jump_total = 0; | |
5530 | dslots_load_filled = 0; | |
5531 | dslots_jump_filled = 0; | |
5532 | num_refs[0] = 0; | |
5533 | num_refs[1] = 0; | |
5534 | num_refs[2] = 0; | |
5535 | mips_load_reg = (rtx)0; | |
5536 | mips_load_reg2 = (rtx)0; | |
cee98a59 MM |
5537 | current_frame_info = zero_frame_info; |
5538 | ||
5539 | /* Restore the output file if optimizing the GP (optimizing the GP causes | |
5540 | the text to be diverted to a tempfile, so that data decls come before | |
5541 | references to the data). */ | |
5542 | ||
5543 | if (TARGET_GP_OPT) | |
5544 | asm_out_file = asm_out_data_file; | |
5545 | } | |
5546 | ||
0fb5ac6f MM |
5547 | \f |
5548 | /* Expand the epilogue into a bunch of separate insns. */ | |
5549 | ||
5550 | void | |
5551 | mips_expand_epilogue () | |
5552 | { | |
7bea35e7 | 5553 | long tsize = current_frame_info.total_size; |
0fb5ac6f | 5554 | rtx tsize_rtx = GEN_INT (tsize); |
7bea35e7 | 5555 | rtx tmp_rtx = (rtx)0; |
0fb5ac6f | 5556 | |
1f2d8f51 JL |
5557 | if (mips_can_use_return_insn ()) |
5558 | { | |
5559 | emit_insn (gen_return ()); | |
5560 | return; | |
5561 | } | |
5562 | ||
0fb5ac6f MM |
5563 | if (tsize > 32767) |
5564 | { | |
147255d8 | 5565 | tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM); |
0fb5ac6f MM |
5566 | emit_move_insn (tmp_rtx, tsize_rtx); |
5567 | tsize_rtx = tmp_rtx; | |
5568 | } | |
5569 | ||
5570 | if (tsize > 0) | |
5571 | { | |
5572 | if (frame_pointer_needed) | |
147255d8 | 5573 | { |
1f2d8f51 | 5574 | emit_insn (gen_blockage ()); |
147255d8 JW |
5575 | if (TARGET_LONG64) |
5576 | emit_insn (gen_movdi (stack_pointer_rtx, frame_pointer_rtx)); | |
5577 | else | |
5578 | emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); | |
5579 | } | |
0fb5ac6f | 5580 | |
7bea35e7 | 5581 | save_restore_insns (FALSE, tmp_rtx, tsize, (FILE *)0); |
0fb5ac6f | 5582 | |
1f2d8f51 | 5583 | emit_insn (gen_blockage ()); |
147255d8 JW |
5584 | if (TARGET_LONG64) |
5585 | emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, | |
5586 | tsize_rtx)); | |
5587 | else | |
5588 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
5589 | tsize_rtx)); | |
0fb5ac6f MM |
5590 | } |
5591 | ||
1f2d8f51 | 5592 | emit_jump_insn (gen_return_internal ()); |
cee98a59 MM |
5593 | } |
5594 | ||
5595 | \f | |
5596 | /* Return true if this function is known to have a null epilogue. | |
5597 | This allows the optimizer to omit jumps to jumps if no stack | |
5598 | was created. */ | |
5599 | ||
5600 | int | |
1f2d8f51 | 5601 | mips_can_use_return_insn () |
cee98a59 MM |
5602 | { |
5603 | if (!reload_completed) | |
5604 | return 0; | |
5605 | ||
1f2d8f51 JL |
5606 | if (regs_ever_live[31] || profile_flag) |
5607 | return 0; | |
5608 | ||
cee98a59 MM |
5609 | if (current_frame_info.initialized) |
5610 | return current_frame_info.total_size == 0; | |
5611 | ||
5612 | return (compute_frame_size (get_frame_size ())) == 0; | |
5613 | } | |
9753d4e4 JW |
5614 | \f |
5615 | /* Choose the section to use for the constant rtx expression X that has | |
5616 | mode MODE. */ | |
5617 | ||
5618 | mips_select_rtx_section (mode, x) | |
5619 | enum machine_mode mode; | |
5620 | rtx x; | |
5621 | { | |
5622 | if (TARGET_EMBEDDED_DATA) | |
5623 | { | |
5624 | /* For embedded applications, always put constants in read-only data, | |
5625 | in order to reduce RAM usage. */ | |
8bd8e198 | 5626 | READONLY_DATA_SECTION (); |
9753d4e4 JW |
5627 | } |
5628 | else | |
5629 | { | |
5630 | /* For hosted applications, always put constants in small data if | |
5631 | possible, as this gives the best performance. */ | |
5632 | ||
5633 | if (GET_MODE_SIZE (mode) <= mips_section_threshold | |
5634 | && mips_section_threshold > 0) | |
8bd8e198 | 5635 | SMALL_DATA_SECTION (); |
9753d4e4 | 5636 | else |
8bd8e198 | 5637 | READONLY_DATA_SECTION (); |
9753d4e4 JW |
5638 | } |
5639 | } | |
5640 | ||
5641 | /* Choose the section to use for DECL. RELOC is true if its value contains | |
5642 | any relocatable expression. */ | |
5643 | ||
5644 | mips_select_section (decl, reloc) | |
5645 | tree decl; | |
5646 | int reloc; | |
5647 | { | |
5648 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
5649 | ||
92544bdf ILT |
5650 | if (TARGET_EMBEDDED_PIC |
5651 | && TREE_CODE (decl) == STRING_CST | |
5652 | && !flag_writable_strings) | |
5653 | { | |
5654 | /* For embedded position independent code, put constant strings | |
5655 | in the text section, because the data section is limited to | |
5656 | 64K in size. */ | |
5657 | ||
5658 | text_section (); | |
5659 | } | |
5660 | else if (TARGET_EMBEDDED_DATA) | |
9753d4e4 JW |
5661 | { |
5662 | /* For embedded applications, always put an object in read-only data | |
5663 | if possible, in order to reduce RAM usage. */ | |
5664 | ||
1d306530 JW |
5665 | if (((TREE_CODE (decl) == VAR_DECL |
5666 | && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl) | |
9753d4e4 JW |
5667 | && DECL_INITIAL (decl) |
5668 | && (DECL_INITIAL (decl) == error_mark_node | |
5669 | || TREE_CONSTANT (DECL_INITIAL (decl)))) | |
5670 | /* Deal with calls from output_constant_def_contents. */ | |
5671 | || (TREE_CODE (decl) != VAR_DECL | |
5672 | && (TREE_CODE (decl) != STRING_CST | |
5673 | || !flag_writable_strings))) | |
5674 | && ! (flag_pic && reloc)) | |
8bd8e198 | 5675 | READONLY_DATA_SECTION (); |
9753d4e4 | 5676 | else if (size > 0 && size <= mips_section_threshold) |
8bd8e198 | 5677 | SMALL_DATA_SECTION (); |
9753d4e4 JW |
5678 | else |
5679 | data_section (); | |
5680 | } | |
5681 | else | |
5682 | { | |
5683 | /* For hosted applications, always put an object in small data if | |
5684 | possible, as this gives the best performance. */ | |
5685 | ||
5686 | if (size > 0 && size <= mips_section_threshold) | |
8bd8e198 | 5687 | SMALL_DATA_SECTION (); |
1d306530 JW |
5688 | else if (((TREE_CODE (decl) == VAR_DECL |
5689 | && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl) | |
9753d4e4 JW |
5690 | && DECL_INITIAL (decl) |
5691 | && (DECL_INITIAL (decl) == error_mark_node | |
5692 | || TREE_CONSTANT (DECL_INITIAL (decl)))) | |
5693 | /* Deal with calls from output_constant_def_contents. */ | |
5694 | || (TREE_CODE (decl) != VAR_DECL | |
5695 | && (TREE_CODE (decl) != STRING_CST | |
5696 | || !flag_writable_strings))) | |
5697 | && ! (flag_pic && reloc)) | |
8bd8e198 | 5698 | READONLY_DATA_SECTION (); |
9753d4e4 JW |
5699 | else |
5700 | data_section (); | |
5701 | } | |
5702 | } | |
33563487 | 5703 | \f |
ade6c319 | 5704 | #ifdef MIPS_ABI_DEFAULT |
33563487 JW |
5705 | /* Support functions for the 64 bit ABI. */ |
5706 | ||
33563487 JW |
5707 | /* Return register to use for a function return value with VALTYPE for function |
5708 | FUNC. */ | |
5709 | ||
5710 | rtx | |
5711 | mips_function_value (valtype, func) | |
5712 | tree valtype; | |
5713 | tree func; | |
5714 | { | |
5715 | int reg = GP_RETURN; | |
5716 | enum machine_mode mode = TYPE_MODE (valtype); | |
5717 | enum mode_class mclass = GET_MODE_CLASS (mode); | |
5718 | ||
a20b7b05 | 5719 | /* ??? How should we return complex float? */ |
33563487 | 5720 | if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) |
efcedf42 ILT |
5721 | { |
5722 | if (TARGET_SINGLE_FLOAT | |
5723 | && (mclass == MODE_FLOAT | |
5724 | ? GET_MODE_SIZE (mode) > 4 | |
5725 | : GET_MODE_SIZE (mode) / 2 > 4)) | |
5726 | reg = GP_RETURN; | |
5727 | else | |
5728 | reg = FP_RETURN; | |
5729 | } | |
293a36eb ILT |
5730 | else if (TREE_CODE (valtype) == RECORD_TYPE |
5731 | && mips_abi != ABI_32 && mips_abi != ABI_EABI) | |
33563487 JW |
5732 | { |
5733 | /* A struct with only one or two floating point fields is returned in | |
5734 | the floating point registers. */ | |
320aba9c | 5735 | tree field, fields[2]; |
33563487 JW |
5736 | int i; |
5737 | ||
5738 | for (i = 0, field = TYPE_FIELDS (valtype); field; | |
320aba9c | 5739 | field = TREE_CHAIN (field)) |
33563487 | 5740 | { |
320aba9c JW |
5741 | if (TREE_CODE (field) != FIELD_DECL) |
5742 | continue; | |
33563487 JW |
5743 | if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2) |
5744 | break; | |
320aba9c JW |
5745 | |
5746 | fields[i++] = field; | |
33563487 JW |
5747 | } |
5748 | ||
1417e9bd | 5749 | /* Must check i, so that we reject structures with no elements. */ |
a20b7b05 JW |
5750 | if (! field) |
5751 | { | |
5752 | if (i == 1) | |
5753 | { | |
320aba9c JW |
5754 | /* The structure has DImode, but we don't allow DImode values |
5755 | in FP registers, so we use a PARALLEL even though it isn't | |
5756 | strictly necessary. */ | |
5757 | enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0])); | |
5758 | ||
5759 | return gen_rtx (PARALLEL, mode, | |
5760 | gen_rtvec (1, | |
5761 | gen_rtx (EXPR_LIST, VOIDmode, | |
5762 | gen_rtx (REG, field_mode, FP_RETURN), | |
5763 | const0_rtx))); | |
a20b7b05 JW |
5764 | } |
5765 | else if (i == 2) | |
5766 | { | |
5767 | enum machine_mode first_mode | |
320aba9c | 5768 | = TYPE_MODE (TREE_TYPE (fields[0])); |
a20b7b05 | 5769 | enum machine_mode second_mode |
320aba9c | 5770 | = TYPE_MODE (TREE_TYPE (fields[1])); |
a20b7b05 | 5771 | int first_offset |
320aba9c | 5772 | = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0])); |
a20b7b05 | 5773 | int second_offset |
320aba9c | 5774 | = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1])); |
a20b7b05 JW |
5775 | |
5776 | return gen_rtx (PARALLEL, mode, | |
5777 | gen_rtvec (2, | |
5778 | gen_rtx (EXPR_LIST, VOIDmode, | |
5779 | gen_rtx (REG, first_mode, FP_RETURN), | |
5780 | GEN_INT (first_offset / BITS_PER_UNIT)), | |
5781 | gen_rtx (EXPR_LIST, VOIDmode, | |
5782 | gen_rtx (REG, second_mode, FP_RETURN + 2), | |
5783 | GEN_INT (second_offset / BITS_PER_UNIT)))); | |
5784 | } | |
5785 | } | |
33563487 JW |
5786 | } |
5787 | ||
5788 | return gen_rtx (REG, mode, reg); | |
5789 | } | |
293a36eb ILT |
5790 | |
5791 | /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return | |
5792 | nonzero when an argument must be passed by reference. */ | |
5793 | ||
5794 | int | |
5795 | function_arg_pass_by_reference (cum, mode, type, named) | |
5796 | CUMULATIVE_ARGS *cum; | |
5797 | enum machine_mode mode; | |
5798 | tree type; | |
5799 | int named; | |
5800 | { | |
5801 | int size; | |
5802 | ||
5803 | if (mips_abi != ABI_EABI) | |
5804 | return 0; | |
5805 | ||
5806 | /* ??? How should SCmode be handled? */ | |
5807 | if (type == NULL_TREE || mode == DImode || mode == DFmode) | |
5808 | return 0; | |
5809 | ||
5810 | size = int_size_in_bytes (type); | |
5811 | return size == -1 || size > UNITS_PER_WORD; | |
5812 | } | |
5813 | ||
33563487 | 5814 | #endif |
46299de9 | 5815 | |
225b8835 ILT |
5816 | /* This function returns the register class required for a secondary |
5817 | register when copying between one of the registers in CLASS, and X, | |
5818 | using MODE. If IN_P is nonzero, the copy is going from X to the | |
5819 | register, otherwise the register is the source. A return value of | |
5820 | NO_REGS means that no secondary register is required. */ | |
46299de9 ILT |
5821 | |
5822 | enum reg_class | |
225b8835 | 5823 | mips_secondary_reload_class (class, mode, x, in_p) |
46299de9 ILT |
5824 | enum reg_class class; |
5825 | enum machine_mode mode; | |
5826 | rtx x; | |
225b8835 | 5827 | int in_p; |
46299de9 | 5828 | { |
225b8835 | 5829 | int regno = -1; |
46299de9 | 5830 | |
2a0b0bf5 ILT |
5831 | if (GET_CODE (x) == SIGN_EXTEND) |
5832 | { | |
5833 | int off = 0; | |
5834 | ||
5835 | x = XEXP (x, 0); | |
5836 | ||
5837 | /* We may be called with reg_renumber NULL from regclass. | |
5838 | ??? This is probably a bug. */ | |
5839 | if (reg_renumber) | |
5840 | regno = true_regnum (x); | |
5841 | else | |
5842 | { | |
5843 | while (GET_CODE (x) == SUBREG) | |
5844 | { | |
5845 | off += SUBREG_WORD (x); | |
5846 | x = SUBREG_REG (x); | |
5847 | } | |
5848 | if (GET_CODE (x) == REG) | |
5849 | regno = REGNO (x) + off; | |
5850 | } | |
5851 | } | |
5852 | else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
225b8835 ILT |
5853 | regno = true_regnum (x); |
5854 | ||
5855 | /* We always require a general register when copying anything to | |
5856 | HILO_REGNUM, except when copying an SImode value from HILO_REGNUM | |
5857 | to a general register, or when copying from register 0. */ | |
5858 | if (class == HILO_REG && regno != GP_REG_FIRST + 0) | |
5859 | { | |
5860 | if (! in_p | |
5861 | && GP_REG_P (regno) | |
5862 | && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode)) | |
5863 | return NO_REGS; | |
5864 | return GR_REGS; | |
5865 | } | |
5866 | if (regno == HILO_REGNUM) | |
46299de9 | 5867 | { |
225b8835 ILT |
5868 | if (in_p |
5869 | && class == GR_REGS | |
5870 | && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode)) | |
5871 | return NO_REGS; | |
5872 | return GR_REGS; | |
5873 | } | |
46299de9 | 5874 | |
225b8835 ILT |
5875 | /* Copying from HI or LO to anywhere other than a general register |
5876 | requires a general register. */ | |
5877 | if (class == HI_REG || class == LO_REG || class == MD_REGS) | |
5878 | { | |
5879 | if (GP_REG_P (regno)) | |
5880 | return NO_REGS; | |
5881 | return GR_REGS; | |
5882 | } | |
5883 | if (MD_REG_P (regno)) | |
5884 | { | |
5885 | if (class == GR_REGS) | |
46299de9 | 5886 | return NO_REGS; |
225b8835 | 5887 | return GR_REGS; |
46299de9 ILT |
5888 | } |
5889 | ||
b8eb88d0 ILT |
5890 | /* We can only copy a value to a condition code register from a |
5891 | floating point register, and even then we require a scratch | |
5892 | floating point register. We can only copy a value out of a | |
5893 | condition code register into a general register. */ | |
5894 | if (class == ST_REGS) | |
5895 | { | |
5896 | if (in_p) | |
5897 | return FP_REGS; | |
5898 | if (GP_REG_P (regno)) | |
5899 | return NO_REGS; | |
5900 | return GR_REGS; | |
5901 | } | |
5902 | if (ST_REG_P (regno)) | |
5903 | { | |
5904 | if (! in_p) | |
5905 | return FP_REGS; | |
5906 | if (class == GR_REGS) | |
5907 | return NO_REGS; | |
5908 | return GR_REGS; | |
5909 | } | |
5910 | ||
225b8835 | 5911 | return NO_REGS; |
46299de9 | 5912 | } |