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7acf4da6 | 1 | ; Toshiba MeP Media Engine architecture description. -*- Scheme -*- |
5624e564 | 2 | ; Copyright (C) 2001-2015 Free Software Foundation, Inc. |
b6402fc3 DD |
3 | ; Contributed by Red Hat, Inc. |
4 | ; | |
5 | ; This file is part of GCC. | |
6 | ; | |
7 | ; GCC is free software; you can redistribute it and/or modify it under | |
8 | ; the terms of the GNU General Public License as published by the Free | |
9 | ; Software Foundation; either version 3, or (at your option) any later | |
10 | ; version. | |
11 | ; | |
12 | ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | ; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | ; for more details. | |
16 | ; | |
17 | ; You should have received a copy of the GNU General Public License | |
18 | ; along with GCC; see the file COPYING3. If not see | |
19 | ; <http://www.gnu.org/licenses/>. | |
7acf4da6 DD |
20 | |
21 | (include "simplify.inc") | |
22 | ||
23 | (define-pmacro isa-enum () | |
24 | (isas mep | |
25 | ; begin-isa-enum | |
26 | ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64 | |
27 | ; end-isa-enum | |
28 | ) | |
29 | ) | |
30 | ||
31 | (define-arch | |
32 | (name mep) | |
33 | (comment "Toshiba MeP Media Engine") | |
34 | (insn-lsb0? #f) ;; work around cgen limitation | |
35 | (machs mep h1 c5) | |
36 | isa-enum | |
37 | ) | |
38 | ||
39 | (define-isa | |
40 | (name mep) | |
41 | (comment "MeP core instruction set") | |
42 | (default-insn-word-bitsize 32) | |
43 | (default-insn-bitsize 32) | |
44 | (base-insn-bitsize 32) | |
45 | ) | |
46 | ||
47 | ; begin-isas | |
48 | (define-isa | |
49 | (name ext_core1) | |
50 | (comment "MeP core extension instruction set") | |
51 | (default-insn-word-bitsize 32) | |
52 | (default-insn-bitsize 32) | |
53 | (base-insn-bitsize 32) | |
54 | ) | |
55 | ||
56 | (define-isa | |
57 | (name ext_cop1_16) | |
58 | (comment "MeP coprocessor instruction set") | |
59 | (default-insn-word-bitsize 32) | |
60 | (default-insn-bitsize 32) | |
61 | (base-insn-bitsize 32) | |
62 | ) | |
63 | ||
64 | (define-isa | |
65 | (name ext_cop1_32) | |
66 | (comment "MeP coprocessor instruction set") | |
67 | (default-insn-word-bitsize 32) | |
68 | (default-insn-bitsize 32) | |
69 | (base-insn-bitsize 32) | |
70 | ) | |
71 | ||
72 | (define-isa | |
73 | (name ext_cop1_48) | |
74 | (comment "MeP coprocessor instruction set") | |
75 | (default-insn-word-bitsize 32) | |
76 | (default-insn-bitsize 32) | |
77 | (base-insn-bitsize 32) | |
78 | ) | |
79 | ||
80 | (define-isa | |
81 | (name ext_cop1_64) | |
82 | (comment "MeP coprocessor instruction set") | |
83 | (default-insn-word-bitsize 32) | |
84 | (default-insn-bitsize 32) | |
85 | (base-insn-bitsize 32) | |
86 | ) | |
87 | ||
88 | (define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) | |
89 | ||
90 | (define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_cop1_32)) | |
91 | ||
92 | (define-pmacro all-core-isa-list () mep,ext_core1) | |
93 | ; end-isas | |
94 | ||
95 | (define-cpu | |
96 | (name mepf) | |
97 | (comment "MeP family") | |
98 | (endian either) | |
99 | (insn-chunk-bitsize 16) | |
100 | (word-bitsize 32) | |
101 | ) | |
102 | ||
103 | (define-mach | |
104 | (name mep) | |
105 | (comment "MeP media engine") | |
106 | (cpu mepf) | |
107 | isa-enum | |
108 | ) | |
109 | ||
110 | (define-mach | |
111 | (name h1) | |
112 | (comment "H1 media engine") | |
113 | (cpu mepf) | |
114 | isa-enum | |
115 | ) | |
116 | ||
117 | (define-mach | |
118 | (name c5) | |
119 | (comment "C5 media engine") | |
120 | (cpu mepf) | |
121 | isa-enum | |
122 | ) | |
123 | ||
124 | (define-model | |
125 | (name mep) | |
126 | (comment "MeP media engine processor") | |
127 | (mach c5) ; mach gets changed by MeP-Integrator | |
128 | ||
129 | (unit u-exec "execution unit" () | |
130 | 1 1 ; issue done | |
131 | () () () ()) | |
132 | ||
133 | ; Branch unit | |
134 | (unit u-branch "Branch Unit" () | |
135 | 0 0 ; issue done | |
136 | () ; state | |
137 | () ; inputs | |
138 | ((pc)) ; outputs | |
139 | () ; profile action (default) | |
140 | ) | |
141 | ||
142 | ; Multiply unit | |
143 | (unit u-multiply "Multiply Unit" () | |
144 | 0 0 ; issue done | |
145 | () ; state | |
146 | () ; inputs | |
147 | () ; outputs | |
148 | () ; profile action (default) | |
149 | ) | |
150 | ||
151 | ; Divide unit | |
152 | (unit u-divide "Divide Unit" () | |
153 | 0 0 ; issue done | |
154 | () ; state | |
155 | () ; inputs | |
156 | () ; outputs | |
157 | () ; profile action (default) | |
158 | ) | |
159 | ||
160 | ; Stcb unit | |
161 | (unit u-stcb "stcb Unit" () | |
162 | 0 0 ; issue done | |
163 | () ; state | |
164 | () ; inputs | |
165 | () ; outputs | |
166 | () ; profile action (default) | |
167 | ) | |
168 | ||
169 | ; Ldcb unit | |
170 | (unit u-ldcb "ldcb Unit" () | |
171 | 0 0 ; issue done | |
172 | () ; state | |
173 | () ; inputs | |
174 | () ; outputs | |
175 | () ; profile action (default) | |
176 | ) | |
177 | ||
178 | ; Load gpr unit | |
179 | (unit u-load-gpr "Load into GPR Unit" () | |
180 | 0 0 ; issue done | |
181 | () ; state | |
182 | () ; inputs | |
183 | ((loadreg INT -1)) ; outputs | |
184 | () ; profile action (default) | |
185 | ) | |
186 | ||
187 | (unit u-ldcb-gpr "Ldcb into GPR Unit" () | |
188 | 0 0 ; issue done | |
189 | () ; state | |
190 | () ; inputs | |
191 | ((loadreg INT -1)) ; outputs | |
192 | () ; profile action (default) | |
193 | ) | |
194 | ||
195 | ; Multiply into GPR unit | |
196 | (unit u-mul-gpr "Multiply into GPR Unit" () | |
197 | 0 0 ; issue done | |
198 | () ; state | |
199 | () ; inputs | |
200 | ((resultreg INT -1)) ; outputs | |
201 | () ; profile action (default) | |
202 | ) | |
203 | ||
204 | ; Use gpr unit -- stalls if GPR not ready | |
205 | (unit u-use-gpr "Use GPR Unit" () | |
206 | 0 0 ; issue done | |
207 | () ; state | |
208 | ((usereg INT -1)) ; inputs | |
209 | () ; outputs | |
210 | () ; profile action (default) | |
211 | ) | |
212 | ||
213 | ; Use ctrl-reg unit -- stalls if CTRL-REG not ready | |
214 | (unit u-use-ctrl-reg "Use CTRL-REG Unit" () | |
215 | 0 0 ; issue done | |
216 | () ; state | |
217 | ((usereg INT -1)) ; inputs | |
218 | () ; outputs | |
219 | () ; profile action (default) | |
220 | ) | |
221 | ||
222 | ; Store ctrl-reg unit -- stalls if CTRL-REG not ready | |
223 | (unit u-store-ctrl-reg "Store CTRL-REG Unit" () | |
224 | 0 0 ; issue done | |
225 | () ; state | |
226 | () ; inputs | |
227 | ((storereg INT -1)) ; outputs | |
228 | () ; profile action (default) | |
229 | ) | |
230 | ) | |
231 | \f | |
232 | ; Hardware elements. | |
233 | ||
234 | (dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ()) | |
235 | ||
236 | (define-hardware | |
237 | (name h-gpr) | |
238 | (comment "General purpose registers") | |
239 | (attrs all-mep-isas CACHE-ADDR PROFILE) | |
240 | (type register SI (16)) | |
241 | (indices keyword "$" | |
242 | (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) | |
243 | ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11) | |
244 | ; "$8" is the preferred name for register 8, but "$tp", "$gp" | |
245 | ; and "$sp" are preferred for their respective registers. | |
246 | (fp 8) (tp 13) (gp 14) (sp 15) | |
247 | ("12" 12) ("13" 13) ("14" 14) ("15" 15))) | |
248 | ) | |
249 | ||
250 | (define-hardware | |
251 | (name h-csr) | |
252 | (comment "Control/special registers") | |
253 | (attrs all-mep-isas PROFILE) | |
254 | (type register SI (32)) | |
255 | (indices keyword "$" | |
256 | ((pc 0) (lp 1) (sar 2) (rpb 4) (rpe 5) (rpc 6) | |
257 | (hi 7) (lo 8) (mb0 12) (me0 13) (mb1 14) (me1 15) | |
258 | (psw 16) (id 17) (tmp 18) (epc 19) (exc 20) (cfg 21) | |
259 | (npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28) | |
260 | ; begin-extra-csr-registers | |
261 | (vid 22) | |
262 | ; end-extra-csr-registers | |
263 | )) | |
264 | (get (index) (c-call SI "cgen_get_csr_value" index)) | |
265 | (set (index newval) (c-call VOID "cgen_set_csr_value" index newval)) | |
266 | ) | |
267 | ||
268 | (define-pmacro (-reg-pair n) ((.sym n) n)) | |
269 | (define-hardware | |
270 | (name h-cr64) | |
271 | (comment "64-bit coprocessor registers") | |
272 | (attrs all-mep-isas) | |
273 | ; This assumes that the data path of the co-pro is 64 bits. | |
274 | (type register DI (32)) | |
275 | (indices keyword "$c" (.map -reg-pair (.iota 32))) | |
276 | (set (index newval) (c-call VOID "h_cr64_queue_set" index newval)) | |
277 | ) | |
278 | (define-hardware | |
279 | (name h-cr64-w) | |
280 | (comment "64-bit coprocessor registers, pending writes") | |
281 | (attrs all-mep-isas) | |
282 | ; This assumes that the data path of the co-pro is 64 bits. | |
283 | (type register DI (32)) | |
284 | ) | |
285 | ||
286 | (define-hardware | |
287 | (name h-cr) | |
288 | (comment "32-bit coprocessor registers") | |
289 | (attrs all-mep-isas VIRTUAL) | |
290 | (type register SI (32)) | |
291 | (indices keyword "$c" (.map -reg-pair (.iota 32))) | |
292 | (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) | |
293 | (get (index) (trunc SI (c-call DI "h_cr64_get" index))) | |
294 | ) | |
295 | ||
296 | ;; Given a coprocessor control register number N, expand to a | |
297 | ;; name/index pair: ($ccrN N) | |
298 | (define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n)) | |
299 | ||
300 | (define-hardware | |
301 | (name h-ccr) | |
302 | (comment "Coprocessor control registers") | |
303 | (attrs all-mep-isas) | |
304 | (type register SI (64)) | |
305 | (indices keyword "" (.map -ccr-reg-pair (.iota 64))) | |
306 | (set (index newval) (c-call VOID "h_ccr_queue_set" index newval)) | |
307 | ) | |
308 | (define-hardware | |
309 | (name h-ccr-w) | |
310 | (comment "Coprocessor control registers, pending writes") | |
311 | (attrs all-mep-isas) | |
312 | (type register SI (64)) | |
313 | ) | |
314 | ||
315 | \f | |
316 | ; Instruction fields. Bit numbering reversed. | |
317 | ||
318 | ; Conventions: | |
319 | ; | |
320 | ; N = number of bits in value | |
321 | ; A = alignment (2 or 4, omit for 1) | |
322 | ; B = leftmost (i.e. closest to zero) bit position | |
323 | ; | |
324 | ; -- Generic Fields (f-*) -- | |
325 | ; N number of bits in *value* (1-24) | |
326 | ; [us] signed vs unsigned | |
327 | ; B position of left-most bit (4-16) | |
328 | ; aA opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc) | |
329 | ; n opt. for noncontiguous fields | |
330 | ; f-foo-{hi,lo} msb/lsb parts of field f-foo | |
331 | ; | |
332 | ; -- Operands -- | |
333 | ; pcrelNaA PC-relative branch target (signed) | |
334 | ; pcabsNaA Absolute branch target (unsigned) | |
335 | ; | |
336 | ; [us]dispNaA [un]signed displacement | |
337 | ; [us]immN [un]signed immediate value | |
338 | ; addrNaA absolute address (unsigned) | |
339 | ; | |
340 | ; Additional prefixes may be used for special cases. | |
341 | ||
342 | (dnf f-major "major opcode" (all-mep-core-isas) 0 4) | |
343 | ||
344 | (dnf f-rn "register n" (all-mep-core-isas) 4 4) | |
345 | (dnf f-rn3 "register 0-7" (all-mep-core-isas) 5 3) | |
346 | (dnf f-rm "register m" (all-mep-core-isas) 8 4) | |
347 | (dnf f-rl "register l" (all-mep-core-isas) 12 4) | |
348 | (dnf f-sub2 "sub opcode (2 bits)" (all-mep-core-isas) 14 2) | |
349 | (dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3) | |
350 | (dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4) | |
351 | (dnf f-ext "extended field" (all-mep-core-isas) 16 8) | |
352 | (dnf f-ext4 "extended field 16:4" (all-mep-core-isas) 16 4) | |
353 | (dnf f-ext62 "extended field 20:2" (all-mep-core-isas) 20 2) | |
354 | (dnf f-crn "copro register n" (all-mep-core-isas) 4 4) | |
355 | ||
356 | (df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f) | |
357 | (df f-csrn-lo "cr lo 4u8" (all-mep-core-isas) 8 4 UINT #f #f) | |
358 | (define-multi-ifield | |
359 | (name f-csrn) | |
360 | (comment "control reg") | |
361 | (attrs all-mep-core-isas) | |
362 | (mode UINT) | |
363 | (subfields f-csrn-hi f-csrn-lo) | |
364 | (insert (sequence () | |
365 | (set (ifield f-csrn-lo) (and (ifield f-csrn) #xf)) | |
366 | (set (ifield f-csrn-hi) (srl (ifield f-csrn) 4)))) | |
367 | (extract (set (ifield f-csrn) | |
368 | (or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo)))) | |
369 | ) | |
370 | ||
371 | (df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f) | |
372 | (df f-crnx-lo "crx lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f) | |
373 | (define-multi-ifield | |
374 | (name f-crnx) | |
375 | (comment "copro register n (0-31)") | |
376 | (attrs all-mep-core-isas) | |
377 | (mode UINT) | |
378 | (subfields f-crnx-hi f-crnx-lo) | |
379 | (insert (sequence () | |
380 | (set (ifield f-crnx-lo) (and (ifield f-crnx) #xf)) | |
381 | (set (ifield f-crnx-hi) (srl (ifield f-crnx) 4)))) | |
382 | (extract (set (ifield f-crnx) | |
383 | (or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo)))) | |
384 | ) | |
385 | ||
386 | ; Miscellaneous fields. | |
387 | ||
388 | (define-pmacro (dnfb n) | |
389 | (dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1)) | |
390 | ||
391 | ; Define small fields used throughout the instruction set description. | |
392 | ; Each field (eg. `f-N') is at single bit field at position N. | |
393 | ||
394 | (dnfb 0) | |
395 | (dnfb 1) | |
396 | (dnfb 2) | |
397 | (dnfb 3) | |
398 | (dnfb 4) | |
399 | (dnfb 5) | |
400 | (dnfb 6) | |
401 | (dnfb 7) | |
402 | (dnfb 8) | |
403 | (dnfb 9) | |
404 | (dnfb 10) | |
405 | (dnfb 11) | |
406 | (dnfb 12) | |
407 | (dnfb 13) | |
408 | (dnfb 14) | |
409 | (dnfb 15) | |
410 | (dnfb 16) | |
411 | (dnfb 17) | |
412 | (dnfb 18) | |
413 | (dnfb 19) | |
414 | (dnfb 20) | |
415 | (dnfb 21) | |
416 | (dnfb 22) | |
417 | (dnfb 23) | |
418 | (dnfb 24) | |
419 | (dnfb 25) | |
420 | (dnfb 26) | |
421 | (dnfb 27) | |
422 | (dnfb 28) | |
423 | (dnfb 29) | |
424 | (dnfb 30) | |
425 | (dnfb 31) | |
426 | ||
427 | ; Branch/Jump target addresses | |
428 | ||
429 | (df f-8s8a2 "pc-rel addr (8 bits)" (all-mep-core-isas PCREL-ADDR) 8 7 INT | |
430 | ((value pc) (sra SI (sub SI value pc) 1)) | |
431 | ((value pc) (add SI (sll SI value 1) pc))) | |
432 | ||
433 | (df f-12s4a2 "pc-rel addr (12 bits)" (all-mep-core-isas PCREL-ADDR) 4 11 INT | |
434 | ((value pc) (sra SI (sub SI value pc) 1)) | |
435 | ((value pc) (add SI (sll SI value 1) pc))) | |
436 | ||
437 | (df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT | |
438 | ((value pc) (sra SI (sub SI value pc) 1)) | |
439 | ((value pc) (add SI (sll SI value 1) pc))) | |
440 | ||
441 | (df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16 INT #f #f) | |
442 | (df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR) 5 7 UINT #f #f) | |
443 | (define-multi-ifield | |
444 | (name f-24s5a2n) | |
445 | (comment "pc-rel addr (24 bits align 2)") | |
446 | (attrs all-mep-core-isas PCREL-ADDR) | |
447 | (mode INT) | |
448 | (subfields f-24s5a2n-hi f-24s5a2n-lo) | |
449 | (insert (sequence () | |
450 | (set (ifield f-24s5a2n) | |
451 | (sub (ifield f-24s5a2n) pc)) | |
452 | (set (ifield f-24s5a2n-lo) | |
453 | (srl (and (ifield f-24s5a2n) #xfe) 1)) | |
454 | (set (ifield f-24s5a2n-hi) | |
455 | (sra INT (ifield f-24s5a2n) 8)))) | |
456 | (extract (set (ifield f-24s5a2n) | |
457 | (add SI (or (sll (ifield f-24s5a2n-hi) 8) | |
458 | (sll (ifield f-24s5a2n-lo) 1)) | |
459 | pc))) | |
460 | ) | |
461 | ||
462 | (df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) | |
463 | (df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas) 5 7 UINT #f #f) | |
464 | (define-multi-ifield | |
465 | (name f-24u5a2n) | |
466 | (comment "abs jump target (24 bits, alignment 2)") | |
467 | (attrs all-mep-core-isas ABS-ADDR) | |
468 | (mode UINT) | |
469 | (subfields f-24u5a2n-hi f-24u5a2n-lo) | |
470 | (insert (sequence () | |
471 | (set (ifield f-24u5a2n-lo) | |
472 | (srl (and (ifield f-24u5a2n) #xff) 1)) | |
473 | (set (ifield f-24u5a2n-hi) | |
474 | (srl (ifield f-24u5a2n) 8)) | |
475 | )) | |
476 | (extract (set (ifield f-24u5a2n) | |
477 | (or (sll (ifield f-24u5a2n-hi) 8) | |
478 | (sll (ifield f-24u5a2n-lo) 1)))) | |
479 | ) | |
480 | ||
481 | ; Displacement fields. | |
482 | ||
483 | (df f-2u6 "SAR offset (2 bits)" (all-mep-core-isas) 6 2 UINT #f #f) | |
484 | (df f-7u9 "tp-rel b (7 bits)" (all-mep-core-isas) 9 7 UINT #f #f) | |
485 | (df f-7u9a2 "tp-rel h (7 bits)" (all-mep-core-isas) 9 6 UINT | |
486 | ((value pc) (srl SI value 1)) | |
487 | ((value pc) (sll SI value 1))) | |
488 | (df f-7u9a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas) 9 5 UINT | |
489 | ((value pc) (srl SI value 2)) | |
490 | ((value pc) (sll SI value 2))) | |
491 | (df f-16s16 "general 16-bit s-val" (all-mep-core-isas) 16 16 INT #f #f) | |
492 | ||
493 | ; Immediate fields. | |
494 | ||
495 | (df f-2u10 "swi level (2 bits)" (all-mep-core-isas) 10 2 UINT #f #f) | |
496 | (df f-3u5 "bit offset (3 bits)" (all-mep-core-isas) 5 3 UINT #f #f) | |
497 | (df f-4u8 "bCC const (4 bits)" (all-mep-core-isas) 8 4 UINT #f #f) | |
498 | (df f-5u8 "slt & shifts (5 bits)" (all-mep-core-isas) 8 5 UINT #f #f) | |
499 | (df f-5u24 "clip immediate (5 bits)" (all-mep-core-isas) 24 5 UINT #f #f) | |
500 | (df f-6s8 "add immediate (6 bits)" (all-mep-core-isas) 8 6 INT #f #f) | |
501 | (df f-8s8 "add imm (8 bits)" (all-mep-core-isas) 8 8 INT #f #f) | |
502 | (df f-16u16 "general 16-bit u-val" (all-mep-core-isas) 16 16 UINT #f #f) | |
503 | (df f-12u16 "cmov fixed 1" (all-mep-core-isas) 16 12 UINT #f #f) | |
504 | (df f-3u29 "cmov fixed 2" (all-mep-core-isas) 29 3 UINT #f #f) | |
505 | ||
506 | ||
507 | ; These are all for the coprocessor opcodes | |
508 | ||
509 | ; The field is like IJKiiiiiii where I and J are toggled if K is set, | |
510 | ; for compatibility with older cores. | |
511 | (define-pmacro (compute-cdisp10 val) | |
512 | (cond SI | |
513 | ((and SI (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x200) | |
514 | (sub (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x400)) | |
515 | (else | |
516 | (cond SI ((and SI val #x80) (xor SI val #x300)) (else val))) | |
517 | ) | |
518 | ) | |
519 | (define-pmacro (extend-cdisp10 val) | |
520 | (cond SI | |
521 | ((and SI (compute-cdisp10 val) #x200) | |
522 | (sub (and SI (compute-cdisp10 val) #x3ff) #x400)) | |
523 | (else | |
524 | (and SI (compute-cdisp10 val) #x3ff)) | |
525 | ) | |
526 | ) | |
527 | ||
528 | (df f-cdisp10 "cop imm10" (all-mep-core-isas) 22 10 INT | |
529 | ((value pc) (extend-cdisp10 value)) | |
530 | ((value pc) (extend-cdisp10 value)) | |
531 | ) | |
532 | ||
533 | ; Non-contiguous fields. | |
534 | ||
535 | (df f-24u8a4n-hi "24u8a4n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) | |
536 | (df f-24u8a4n-lo "24u8a4n lo 8u8a4" (all-mep-core-isas) 8 6 UINT #f #f) | |
537 | (define-multi-ifield | |
538 | (name f-24u8a4n) | |
539 | (comment "absolute 24-bit address") | |
540 | (attrs all-mep-core-isas) | |
541 | (mode UINT) | |
542 | (subfields f-24u8a4n-hi f-24u8a4n-lo) | |
543 | (insert (sequence () | |
544 | (set (ifield f-24u8a4n-hi) (srl (ifield f-24u8a4n) 8)) | |
545 | (set (ifield f-24u8a4n-lo) (srl (and (ifield f-24u8a4n) #xfc) 2)))) | |
546 | (extract (set (ifield f-24u8a4n) | |
547 | (or (sll (ifield f-24u8a4n-hi) 8) | |
548 | (sll (ifield f-24u8a4n-lo) 2)))) | |
549 | ) | |
550 | ||
551 | (df f-24u8n-hi "24u8n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) | |
552 | (df f-24u8n-lo "24u8n lo 8u8" (all-mep-core-isas) 8 8 UINT #f #f) | |
553 | (define-multi-ifield | |
554 | (name f-24u8n) | |
555 | (comment "24-bit constant") | |
556 | (attrs all-mep-core-isas) | |
557 | (mode UINT) | |
558 | (subfields f-24u8n-hi f-24u8n-lo) | |
559 | (insert (sequence () | |
560 | (set (ifield f-24u8n-hi) (srl (ifield f-24u8n) 8)) | |
561 | (set (ifield f-24u8n-lo) (and (ifield f-24u8n) #xff)))) | |
562 | (extract (set (ifield f-24u8n) | |
563 | (or (sll (ifield f-24u8n-hi) 8) | |
564 | (ifield f-24u8n-lo)))) | |
565 | ) | |
566 | ||
567 | (df f-24u4n-hi "24u4n hi 8u4" (all-mep-core-isas) 4 8 UINT #f #f) | |
568 | (df f-24u4n-lo "24u4n lo 16u16" (all-mep-core-isas) 16 16 UINT #f #f) | |
569 | (define-multi-ifield | |
570 | (name f-24u4n) | |
571 | (comment "coprocessor code") | |
572 | (attrs all-mep-core-isas) | |
573 | (mode UINT) | |
574 | (subfields f-24u4n-hi f-24u4n-lo) | |
575 | (insert (sequence () | |
576 | (set (ifield f-24u4n-hi) (srl (ifield f-24u4n) 16)) | |
577 | (set (ifield f-24u4n-lo) (and (ifield f-24u4n) #xffff)))) | |
578 | (extract (set (ifield f-24u4n) | |
579 | (or (sll (ifield f-24u4n-hi) 16) | |
580 | (ifield f-24u4n-lo)))) | |
581 | ) | |
582 | ||
583 | (define-multi-ifield | |
584 | (name f-callnum) | |
585 | (comment "system call number field") | |
586 | (attrs all-mep-core-isas) | |
587 | (mode UINT) | |
588 | (subfields f-5 f-6 f-7 f-11) | |
589 | (insert (sequence () | |
590 | (set (ifield f-5) (and (srl (ifield f-callnum) 3) 1)) | |
591 | (set (ifield f-6) (and (srl (ifield f-callnum) 2) 1)) | |
592 | (set (ifield f-7) (and (srl (ifield f-callnum) 1) 1)) | |
593 | (set (ifield f-11) (and (ifield f-callnum) 1)))) | |
594 | (extract (set (ifield f-callnum) | |
595 | (or (sll (ifield f-5) 3) | |
596 | (or (sll (ifield f-6) 2) | |
597 | (or (sll (ifield f-7) 1) | |
598 | (ifield f-11)))))) | |
599 | ) | |
600 | ||
601 | (df f-ccrn-hi "ccrn hi 2u28" (all-mep-core-isas) 28 2 UINT #f #f) | |
602 | (df f-ccrn-lo "ccrn lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f) | |
603 | (define-multi-ifield | |
604 | (name f-ccrn) | |
605 | (comment "Coprocessor register number field") | |
606 | (attrs all-mep-core-isas) | |
607 | (mode UINT) | |
608 | (subfields f-ccrn-hi f-ccrn-lo) | |
609 | (insert (sequence () | |
610 | (set (ifield f-ccrn-hi) (and (srl (ifield f-ccrn) 4) #x3)) | |
611 | (set (ifield f-ccrn-lo) (and (ifield f-ccrn) #xf)))) | |
612 | (extract (set (ifield f-ccrn) | |
613 | (or (sll (ifield f-ccrn-hi) 4) | |
614 | (ifield f-ccrn-lo)))) | |
615 | ) | |
616 | \f | |
617 | ; Operands. | |
618 | ||
619 | ;; Only LABEL, REGNUM, FMAX_FLOAT and FMAX_INT are now relevant for correct | |
620 | ;; operation. The others are mostly kept for backwards compatibility, | |
621 | ;; although they do affect the dummy prototypes in | |
622 | ;; gcc/config/mep/intrinsics.h. | |
623 | (define-attr | |
624 | (type enum) | |
625 | (for operand) | |
626 | (name CDATA) | |
627 | (comment "datatype to use for C intrinsics mapping") | |
628 | (values LABEL REGNUM FMAX_FLOAT FMAX_INT | |
629 | POINTER LONG ULONG SHORT USHORT CHAR UCHAR CP_DATA_BUS_INT) | |
630 | (default LONG)) | |
631 | ||
632 | (define-attr | |
633 | (type enum) | |
634 | (for insn) | |
635 | (name CPTYPE) | |
636 | (comment "datatype to use for coprocessor values") | |
637 | (values CP_DATA_BUS_INT VECT V2SI V4HI V8QI V2USI V4UHI V8UQI) | |
638 | (default CP_DATA_BUS_INT)) | |
639 | ||
640 | (define-attr | |
641 | (type enum) | |
642 | (for insn) | |
643 | (name CRET) | |
644 | ;; VOID - all arguments are passed as parameters; if any are written, pointers to them are passed. | |
645 | ;; FIRST - the first argument is the return value. | |
646 | ;; FIRSTCOPY - the first argument is the return value, but a copy is also the first parameter. | |
647 | (values VOID FIRST FIRSTCOPY) | |
648 | (default VOID) | |
649 | (comment "Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it.")) | |
650 | ||
651 | (define-attr | |
652 | (type integer) | |
653 | (for operand) | |
654 | (name ALIGN) | |
655 | (comment "alignment of immediate operands") | |
656 | (default 1)) | |
657 | ||
658 | (define-attr | |
659 | (for operand) | |
660 | (type boolean) | |
661 | (name RELOC_IMPLIES_OVERFLOW) | |
662 | (comment "Operand should not be considered as a candidate for relocs")) | |
663 | ||
664 | (define-attr | |
665 | (for hardware) | |
666 | (type boolean) | |
667 | (name IS_FLOAT) | |
668 | (comment "Register contains a floating point value")) | |
669 | ||
670 | (define-pmacro (dpop name commment attrib hwr field func) | |
671 | (define-full-operand name comment attrib | |
672 | hwr DFLT field ((parse func)) () ())) | |
673 | (define-pmacro (dprp name commment attrib hwr field pafunc prfunc) | |
674 | (define-full-operand name comment attrib | |
675 | hwr DFLT field ((parse pafunc) (print prfunc)) () ())) | |
676 | ||
677 | (dnop r0 "register 0" (all-mep-core-isas) h-gpr 0) | |
678 | (dnop rn "register Rn" (all-mep-core-isas) h-gpr f-rn) | |
679 | (dnop rm "register Rm" (all-mep-core-isas) h-gpr f-rm) | |
680 | (dnop rl "register Rl" (all-mep-core-isas) h-gpr f-rl) | |
681 | (dnop rn3 "register 0-7" (all-mep-core-isas) h-gpr f-rn3) | |
682 | ||
683 | ;; Variants of RM/RN with different CDATA attributes. See comment above | |
684 | ;; CDATA for more details. | |
685 | ||
686 | (dnop rma "register Rm holding pointer" (all-mep-core-isas (CDATA POINTER)) h-gpr f-rm) | |
687 | ||
688 | (dnop rnc "register Rn holding char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) | |
689 | (dnop rnuc "register Rn holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) | |
690 | (dnop rns "register Rn holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) | |
691 | (dnop rnus "register Rn holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) | |
692 | (dnop rnl "register Rn holding long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) | |
693 | (dnop rnul "register Rn holding unsigned long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn) | |
694 | ||
695 | (dnop rn3c "register 0-7 holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) | |
696 | (dnop rn3uc "register 0-7 holding byte" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) | |
697 | (dnop rn3s "register 0-7 holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) | |
698 | (dnop rn3us "register 0-7 holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) | |
699 | (dnop rn3l "register 0-7 holding unsigned long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) | |
700 | (dnop rn3ul "register 0-7 holding long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn3) | |
701 | ||
702 | ||
703 | (dnop lp "link pointer" (all-mep-core-isas) h-csr 1) | |
704 | (dnop sar "shift amount register" (all-mep-core-isas) h-csr 2) | |
705 | (dnop hi "high result" (all-mep-core-isas) h-csr 7) | |
706 | (dnop lo "low result" (all-mep-core-isas) h-csr 8) | |
707 | (dnop mb0 "modulo begin register 0" (all-mep-core-isas) h-csr 12) | |
708 | (dnop me0 "modulo end register 0" (all-mep-core-isas) h-csr 13) | |
709 | (dnop mb1 "modulo begin register 1" (all-mep-core-isas) h-csr 14) | |
710 | (dnop me1 "modulo end register 1" (all-mep-core-isas) h-csr 15) | |
711 | (dnop psw "program status word" (all-mep-core-isas) h-csr 16) | |
712 | (dnop epc "exception prog counter" (all-mep-core-isas) h-csr 19) | |
713 | (dnop exc "exception cause" (all-mep-core-isas) h-csr 20) | |
714 | (dnop npc "nmi program counter" (all-mep-core-isas) h-csr 23) | |
715 | (dnop dbg "debug register" (all-mep-core-isas) h-csr 24) | |
716 | (dnop depc "debug exception pc" (all-mep-core-isas) h-csr 25) | |
717 | (dnop opt "option register" (all-mep-core-isas) h-csr 26) | |
718 | (dnop r1 "register 1" (all-mep-core-isas) h-gpr 1) | |
719 | (dnop tp "tiny data area pointer" (all-mep-core-isas) h-gpr 13) | |
720 | (dnop sp "stack pointer" (all-mep-core-isas) h-gpr 15) | |
721 | (dprp tpr "TP register" (all-mep-core-isas) h-gpr 13 "tpreg" "tpreg") | |
722 | (dprp spr "SP register" (all-mep-core-isas) h-gpr 15 "spreg" "spreg") | |
723 | ||
724 | (define-full-operand | |
725 | csrn "control/special register" (all-mep-core-isas (CDATA REGNUM)) h-csr | |
726 | DFLT f-csrn ((parse "csrn")) () () | |
727 | ) | |
728 | ||
729 | (dnop csrn-idx "control/special reg idx" (all-mep-core-isas) h-uint f-csrn) | |
730 | (dnop crn64 "copro Rn (64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crn) | |
731 | (dnop crn "copro Rn (32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crn) | |
732 | (dnop crnx64 "copro Rn (0-31, 64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crnx) | |
733 | (dnop crnx "copro Rn (0-31, 32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crnx) | |
734 | (dnop ccrn "copro control reg CCRn" (all-mep-core-isas (CDATA REGNUM)) h-ccr f-ccrn) | |
735 | (dnop cccc "copro flags" (all-mep-core-isas) h-uint f-rm) | |
736 | ||
737 | (dprp pcrel8a2 "pc-rel addr (8 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-8s8a2 "mep_align" "address") | |
738 | (dprp pcrel12a2 "pc-rel addr (12 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-12s4a2 "mep_align" "address") | |
739 | (dprp pcrel17a2 "pc-rel addr (17 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-17s16a2 "mep_align" "address") | |
740 | (dprp pcrel24a2 "pc-rel addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-sint f-24s5a2n "mep_align" "address") | |
741 | (dprp pcabs24a2 "pc-abs addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-uint f-24u5a2n "mep_alignu" "address") | |
742 | ||
743 | (dpop sdisp16 "displacement (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16") | |
744 | (dpop simm16 "signed imm (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16") | |
745 | (dpop uimm16 "unsigned imm (16 bits)" (all-mep-core-isas) h-uint f-16u16 "unsigned16") | |
746 | (dnop code16 "uci/dsp code (16 bits)" (all-mep-core-isas) h-uint f-16u16) | |
747 | ||
748 | (dnop udisp2 "SSARB addend (2 bits)" (all-mep-core-isas) h-sint f-2u6) | |
749 | (dnop uimm2 "interrupt (2 bits)" (all-mep-core-isas) h-uint f-2u10) | |
750 | ||
751 | (dnop simm6 "add const (6 bits)" (all-mep-core-isas) h-sint f-6s8) | |
752 | (dnop simm8 "mov const (8 bits)" (all-mep-core-isas RELOC_IMPLIES_OVERFLOW) | |
753 | h-sint f-8s8) | |
754 | ||
755 | (dpop addr24a4 "sw/lw addr (24 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-24u8a4n "mep_alignu") | |
756 | (dnop code24 "coprocessor code" (all-mep-core-isas) h-uint f-24u4n) | |
757 | ||
758 | (dnop callnum "system call number" (all-mep-core-isas) h-uint f-callnum) | |
759 | (dnop uimm3 "bit immediate (3 bits)" (all-mep-core-isas) h-uint f-3u5) | |
760 | (dnop uimm4 "bCC const (4 bits)" (all-mep-core-isas) h-uint f-4u8) | |
761 | (dnop uimm5 "bit/shift val (5 bits)" (all-mep-core-isas) h-uint f-5u8) | |
762 | ||
763 | (dpop udisp7 "tp-rel b (7 bits)" (all-mep-core-isas) h-uint f-7u9 "unsigned7") | |
764 | (dpop udisp7a2 "tp-rel h (7 bits)" (all-mep-core-isas (ALIGN 2)) h-uint f-7u9a2 "unsigned7") | |
765 | (dpop udisp7a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "unsigned7") | |
766 | (dpop uimm7a4 "sp w-addend (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "mep_alignu") | |
767 | ||
768 | (dnop uimm24 "immediate (24 bits)" (all-mep-core-isas) h-uint f-24u8n) | |
769 | ||
770 | (dnop cimm4 "cache immed'te (4 bits)" (all-mep-core-isas) h-uint f-rn) | |
771 | (dnop cimm5 "clip immediate (5 bits)" (all-mep-core-isas) h-uint f-5u24) | |
772 | ||
773 | (dpop cdisp10 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") | |
774 | (dpop cdisp10a2 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") | |
775 | (dpop cdisp10a4 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") | |
776 | (dpop cdisp10a8 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") | |
777 | ||
778 | ; Special operand representing the various ways that the literal zero can be | |
779 | ; specified. | |
780 | (define-full-operand | |
781 | zero "Zero operand" (all-mep-core-isas) h-sint DFLT f-nil | |
782 | ((parse "zero")) () () | |
783 | ) | |
784 | \f | |
785 | ; Attributes. | |
786 | ||
787 | (define-attr | |
788 | (for insn) | |
789 | (type boolean) | |
790 | (name OPTIONAL_BIT_INSN) | |
791 | (comment "optional bit manipulation instruction")) | |
792 | ||
793 | (define-attr | |
794 | (for insn) | |
795 | (type boolean) | |
796 | (name OPTIONAL_MUL_INSN) | |
797 | (comment "optional 32-bit multiply instruction")) | |
798 | ||
799 | (define-attr | |
800 | (for insn) | |
801 | (type boolean) | |
802 | (name OPTIONAL_DIV_INSN) | |
803 | (comment "optional 32-bit divide instruction")) | |
804 | ||
805 | (define-attr | |
806 | (for insn) | |
807 | (type boolean) | |
808 | (name OPTIONAL_DEBUG_INSN) | |
809 | (comment "optional debug instruction")) | |
810 | ||
811 | (define-attr | |
812 | (for insn) | |
813 | (type boolean) | |
814 | (name OPTIONAL_LDZ_INSN) | |
815 | (comment "optional leading zeroes instruction")) | |
816 | ||
817 | (define-attr | |
818 | (for insn) | |
819 | (type boolean) | |
820 | (name OPTIONAL_ABS_INSN) | |
821 | (comment "optional absolute difference instruction")) | |
822 | ||
823 | (define-attr | |
824 | (for insn) | |
825 | (type boolean) | |
826 | (name OPTIONAL_AVE_INSN) | |
827 | (comment "optional average instruction")) | |
828 | ||
829 | (define-attr | |
830 | (for insn) | |
831 | (type boolean) | |
832 | (name OPTIONAL_MINMAX_INSN) | |
833 | (comment "optional min/max instruction")) | |
834 | ||
835 | (define-attr | |
836 | (for insn) | |
837 | (type boolean) | |
838 | (name OPTIONAL_CLIP_INSN) | |
839 | (comment "optional clipping instruction")) | |
840 | ||
841 | (define-attr | |
842 | (for insn) | |
843 | (type boolean) | |
844 | (name OPTIONAL_SAT_INSN) | |
845 | (comment "optional saturation instruction")) | |
846 | ||
847 | (define-attr | |
848 | (for insn) | |
849 | (type boolean) | |
850 | (name OPTIONAL_UCI_INSN) | |
851 | (comment "optional UCI instruction")) | |
852 | ||
853 | (define-attr | |
854 | (for insn) | |
855 | (type boolean) | |
856 | (name OPTIONAL_DSP_INSN) | |
857 | (comment "optional DSP instruction")) | |
858 | ||
859 | (define-attr | |
860 | (for insn) | |
861 | (type boolean) | |
862 | (name OPTIONAL_CP_INSN) | |
863 | (comment "optional coprocessor-related instruction")) | |
864 | ||
865 | (define-attr | |
866 | (for insn) | |
867 | (type boolean) | |
868 | (name OPTIONAL_CP64_INSN) | |
869 | (comment "optional coprocessor-related 64 data bit instruction")) | |
870 | ||
871 | (define-attr | |
872 | (for insn) | |
873 | (type boolean) | |
874 | (name OPTIONAL_VLIW64) | |
875 | (comment "optional vliw64 mode (vliw32 is default)")) | |
876 | ||
877 | (define-attr | |
878 | (for insn) | |
879 | (type enum) | |
880 | (name STALL) | |
881 | (attrs META) | |
882 | (values NONE SHIFTI INT2 LOAD STORE LDC STC LDCB STCB SSARB FSFT RET | |
883 | ADVCK MUL MULR DIV) | |
884 | (default NONE) | |
885 | (comment "gcc stall attribute")) | |
886 | ||
887 | (define-attr | |
888 | (for insn) | |
889 | (type string) | |
890 | (name INTRINSIC) | |
891 | (attrs META) | |
892 | (comment "gcc intrinsic name")) | |
893 | ||
894 | (define-attr | |
895 | (for insn) | |
896 | (type enum) | |
897 | (name SLOT) | |
898 | (attrs META) | |
899 | (values NONE C3 V1 V3 P0S P0 P1) | |
900 | (default NONE) | |
901 | (comment "coprocessor slot type")) | |
902 | ||
903 | (define-attr | |
904 | (for insn) | |
905 | (type boolean) | |
906 | (name MAY_TRAP) | |
907 | (comment "instruction may generate an exception")) | |
908 | ||
909 | ; Attributes for scheduling restrictions in vliw mode | |
910 | ||
911 | (define-attr | |
912 | (for insn) | |
913 | (type boolean) | |
914 | (name VLIW_ALONE) | |
915 | (comment "instruction can be scheduled alone in vliw mode")) | |
916 | ||
917 | (define-attr | |
918 | (for insn) | |
919 | (type boolean) | |
920 | (name VLIW_NO_CORE_NOP) | |
921 | (comment "there is no corresponding nop core instruction")) | |
922 | ||
923 | (define-attr | |
924 | (for insn) | |
925 | (type boolean) | |
926 | (name VLIW_NO_COP_NOP) | |
927 | (comment "there is no corresponding nop coprocessor instruction")) | |
928 | ||
929 | (define-attr | |
930 | (for insn) | |
931 | (type boolean) | |
932 | (name VLIW64_NO_MATCHING_NOP) | |
933 | (comment "there is no corresponding nop coprocessor instruction")) | |
934 | (define-attr | |
935 | (for insn) | |
936 | (type boolean) | |
937 | (name VLIW32_NO_MATCHING_NOP) | |
938 | (comment "there is no corresponding nop coprocessor instruction")) | |
939 | ||
940 | (define-attr | |
941 | (for insn) | |
942 | (type boolean) | |
943 | (name VOLATILE) | |
944 | (comment "Insn is volatile.")) | |
945 | ||
946 | (define-attr | |
947 | (for insn) | |
948 | (type integer) | |
949 | (name LATENCY) | |
950 | (comment "The latency of this insn, used for scheduling as an intrinsic in gcc") | |
951 | (default 0)) | |
952 | ||
953 | ; The MeP config tool will edit this. | |
954 | (define-attr | |
955 | (type enum) | |
956 | (for insn) | |
957 | (name CONFIG) | |
958 | (values NONE ; config-attr-start | |
959 | default | |
960 | ) ; config-attr-end | |
961 | ) | |
962 | ||
963 | \f | |
964 | ; Enumerations. | |
965 | ||
966 | (define-normal-insn-enum major "major opcodes" (all-mep-core-isas) MAJ_ | |
967 | f-major | |
968 | (.map .str (.iota 16)) | |
969 | ) | |
970 | ||
971 | ||
972 | (define-pmacro (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming isa) | |
973 | (define-insn | |
974 | (name xname) | |
975 | (comment xcomment) | |
976 | (.splice attrs (.unsplice xattrs) (ISA isa)) | |
977 | (syntax xsyntax) | |
978 | (format xformat) | |
979 | (semantics xsemantics) | |
980 | (.splice timing (.unsplice xtiming)) | |
981 | ) | |
982 | ) | |
983 | ||
984 | (define-pmacro (dnmi-isa xname xcomment xattrs xsyntax xemit isa) | |
985 | (dnmi xname xcomment (.splice (.unsplice xattrs) (ISA isa)) xsyntax xemit) | |
986 | ) | |
987 | ||
988 | ; For making profiling calls and dynamic configuration | |
989 | (define-pmacro (cg-profile caller callee) | |
990 | (c-call "cg_profile" caller callee) | |
991 | ) | |
992 | ; For dynamic configuration only | |
993 | (define-pmacro (cg-profile-jump caller callee) | |
994 | (c-call "cg_profile_jump" caller callee) | |
995 | ) | |
996 | ||
997 | ; For defining Core Instructions | |
998 | (define-pmacro (dnci xname xcomment xattrs xsyntax xformat xsemantics xtiming) | |
999 | (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming all-core-isa-list) | |
1000 | ) | |
1001 | (define-pmacro (dncmi xname xcomment xattrs xsyntax xemit) | |
1002 | (dnmi-isa xname xcomment xattrs xsyntax xemit all-core-isa-list) | |
1003 | ) | |
1004 | ||
1005 | ; For defining Coprocessor Instructions | |
1006 | ;(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming cop) | |
1007 | ;) | |
1008 | ||
1009 | ;; flag setting macro | |
1010 | (define-pmacro (set-bit xop xbitnum xval) | |
1011 | (set xop (or | |
1012 | (and xop (inv (sll 1 xbitnum))) | |
1013 | (and (sll 1 xbitnum) (sll xval xbitnum))))) | |
1014 | ||
1015 | ;; some flags we commonly use in vliw reasoning / mode-switching etc. | |
1016 | (define-pmacro (get-opt.vliw64) (and (srl opt 6) 1)) | |
1017 | (define-pmacro (get-opt.vliw32) (and (srl opt 5) 1)) | |
1018 | (define-pmacro (get-rm.lsb) (and rm 1)) | |
1019 | (define-pmacro (get-psw.om) (and (srl psw 12) 1)) | |
1020 | (define-pmacro (get-psw.nmi) (and (srl psw 9) 1)) | |
1021 | (define-pmacro (get-psw.iep) (and (srl psw 1) 1)) | |
1022 | (define-pmacro (get-psw.ump) (and (srl psw 3) 1)) | |
1023 | (define-pmacro (get-epc.etom) (and epc 1)) | |
1024 | (define-pmacro (get-npc.ntom) (and npc 1)) | |
1025 | (define-pmacro (get-lp.ltom) (and lp 1)) | |
1026 | ||
1027 | (define-pmacro (set-psw.om zval) (set-bit (raw-reg h-csr 16) 12 zval)) | |
1028 | (define-pmacro (set-psw.nmi zval) (set-bit (raw-reg h-csr 16) 9 zval)) | |
1029 | (define-pmacro (set-psw.umc zval) (set-bit (raw-reg h-csr 16) 2 zval)) | |
1030 | (define-pmacro (set-psw.iec zval) (set-bit (raw-reg h-csr 16) 0 zval)) | |
1031 | (define-pmacro (set-rpe.elr zval) (set-bit (raw-reg h-csr 5) 0 zval)) | |
1032 | ||
1033 | ||
1034 | ;; the "3 way switch" depending on our current operating mode and vliw status flags | |
1035 | (define-pmacro (core-vliw-switch core-rtl vliw32-rtl vliw64-rtl) | |
1036 | (cond | |
1037 | ((andif (get-psw.om) (get-opt.vliw64)) vliw64-rtl) | |
1038 | ((andif (get-psw.om) (get-opt.vliw32)) vliw32-rtl) | |
1039 | (else core-rtl))) | |
1040 | ||
1041 | ;; the varying-pcrel idiom | |
1042 | (define-pmacro (set-vliw-modified-pcrel-offset xtarg xa xb xc) | |
1043 | (core-vliw-switch (set xtarg (add pc xa)) | |
1044 | (set xtarg (add pc xb)) | |
1045 | (set xtarg (add pc xc)))) | |
1046 | ||
1047 | ;; the increasing-alignment idiom in branch displacements | |
1048 | (define-pmacro (set-vliw-alignment-modified xtarg zaddr) | |
1049 | (core-vliw-switch (set xtarg (and zaddr (inv 1))) | |
1050 | (set xtarg (and zaddr (inv 3))) | |
1051 | (set xtarg (and zaddr (inv 7))))) | |
1052 | ||
1053 | ;; the increasing-alignment idiom in option-only form | |
1054 | (define-pmacro (set-vliw-aliignment-modified-by-option xtarg zaddr) | |
1055 | (if (get-opt.vliw32) | |
1056 | (set xtarg (and zaddr (inv 3))) | |
1057 | (set xtarg (and zaddr (inv 7))))) | |
1058 | ||
1059 | ||
1060 | \f | |
1061 | ; pmacros needed for coprocessor modulo addressing. | |
1062 | ||
1063 | ; Taken from supplement ``The operation of the modulo addressing'' in | |
1064 | ; Toshiba documentation rev 2.2, p. 34. | |
1065 | ||
1066 | (define-pmacro (compute-mask0) | |
1067 | (sequence SI ((SI temp)) | |
1068 | (set temp (or mb0 me0)) | |
1069 | (srl (const SI -1) (c-call SI "do_ldz" temp)))) | |
1070 | ||
1071 | (define-pmacro (mod0 immed) | |
1072 | (sequence SI ((SI modulo-mask)) | |
1073 | (set modulo-mask (compute-mask0)) | |
1074 | (if SI (eq (and rma modulo-mask) me0) | |
1075 | (or (and rma (inv modulo-mask)) mb0) | |
1076 | (add rma (ext SI immed))))) | |
1077 | ||
1078 | (define-pmacro (compute-mask1) | |
1079 | (sequence SI ((SI temp)) | |
1080 | (set temp (or mb1 me1)) | |
1081 | (srl (const SI -1) (c-call SI "do_ldz" temp)))) | |
1082 | ||
1083 | (define-pmacro (mod1 immed) | |
1084 | (sequence SI ((SI modulo-mask)) | |
1085 | (set modulo-mask (compute-mask1)) | |
1086 | (if SI (eq (and rma modulo-mask) me1) | |
1087 | (or (and rma (inv modulo-mask)) mb1) | |
1088 | (add rma (ext SI immed))))) | |
1089 | ||
1090 | \f | |
1091 | ; Instructions. | |
1092 | ||
1093 | ; A pmacro for use in semantic bodies of unimplemented insns. | |
1094 | (define-pmacro (unimp mnemonic) (nop)) | |
1095 | ||
1096 | ; Core specific instructions | |
1097 | ; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator | |
1098 | (include "mep-c5.cpu") ; -- exposed by MeP-Integrator | |
1099 | ||
1100 | ; Load/store instructions. | |
1101 | ||
1102 | (dnci sb "store byte (register indirect)" ((STALL STORE)) | |
1103 | "sb $rnc,($rma)" | |
1104 | (+ MAJ_0 rnc rma (f-sub4 8)) | |
1105 | (sequence () | |
1106 | (c-call VOID "check_write_to_text" rma) | |
1107 | (set (mem UQI rma) (and rnc #xff))) | |
1108 | ((mep (unit u-use-gpr (in usereg rnc)) | |
1109 | (unit u-use-gpr (in usereg rma)) | |
1110 | (unit u-exec)))) | |
1111 | ||
1112 | (dnci sh "store half-word (register indirect)" ((STALL STORE)) | |
1113 | "sh $rns,($rma)" | |
1114 | (+ MAJ_0 rns rma (f-sub4 9)) | |
1115 | (sequence () | |
1116 | (c-call VOID "check_write_to_text" (and rma (inv 1))) | |
1117 | (set (mem UHI (and rma (inv 1))) (and rns #xffff))) | |
1118 | ((mep (unit u-use-gpr (in usereg rns)) | |
1119 | (unit u-use-gpr (in usereg rma)) | |
1120 | (unit u-exec)))) | |
1121 | ||
1122 | (dnci sw "store word (register indirect)" ((STALL STORE)) | |
1123 | "sw $rnl,($rma)" | |
1124 | (+ MAJ_0 rnl rma (f-sub4 10)) | |
1125 | (sequence () | |
1126 | (c-call VOID "check_write_to_text" (and rma (inv 3))) | |
1127 | (set (mem USI (and rma (inv 3))) rnl)) | |
1128 | ((mep (unit u-use-gpr (in usereg rnl)) | |
1129 | (unit u-use-gpr (in usereg rma)) | |
1130 | (unit u-exec)))) | |
1131 | ||
1132 | (dnci lb "load byte (register indirect)" ((STALL LOAD) (LATENCY 2)) | |
1133 | "lb $rnc,($rma)" | |
1134 | (+ MAJ_0 rnc rma (f-sub4 12)) | |
1135 | (set rnc (ext SI (mem QI rma))) | |
1136 | ((mep (unit u-use-gpr (in usereg rma)) | |
1137 | (unit u-exec) | |
1138 | (unit u-load-gpr (out loadreg rnc))))) | |
1139 | ||
1140 | (dnci lh "load half-word (register indirect)" ((STALL LOAD) (LATENCY 2)) | |
1141 | "lh $rns,($rma)" | |
1142 | (+ MAJ_0 rns rma (f-sub4 13)) | |
1143 | (set rns (ext SI (mem HI (and rma (inv 1))))) | |
1144 | ((mep (unit u-use-gpr (in usereg rma)) | |
1145 | (unit u-exec) | |
1146 | (unit u-load-gpr (out loadreg rns))))) | |
1147 | ||
1148 | (dnci lw "load word (register indirect)" ((STALL LOAD) (LATENCY 2)) | |
1149 | "lw $rnl,($rma)" | |
1150 | (+ MAJ_0 rnl rma (f-sub4 14)) | |
1151 | (set rnl (mem SI (and rma (inv 3)))) | |
1152 | ((mep (unit u-use-gpr (in usereg rma)) | |
1153 | (unit u-exec) | |
1154 | (unit u-load-gpr (out loadreg rnl))))) | |
1155 | ||
1156 | (dnci lbu "load unsigned byte (register indirect)" ((STALL LOAD) (LATENCY 2)) | |
1157 | "lbu $rnuc,($rma)" | |
1158 | (+ MAJ_0 rnuc rma (f-sub4 11)) | |
1159 | (set rnuc (zext SI (mem UQI rma))) | |
1160 | ((mep (unit u-use-gpr (in usereg rma)) | |
1161 | (unit u-exec) | |
1162 | (unit u-load-gpr (out loadreg rnuc))))) | |
1163 | ||
1164 | (dnci lhu "load unsigned half-word (register indirect)" ((STALL LOAD) (LATENCY 2)) | |
1165 | "lhu $rnus,($rma)" | |
1166 | (+ MAJ_0 rnus rma (f-sub4 15)) | |
1167 | (set rnus (zext SI (mem UHI (and rma (inv 1))))) | |
1168 | ((mep (unit u-use-gpr (in usereg rma)) | |
1169 | (unit u-exec) | |
1170 | (unit u-load-gpr (out loadreg rnus))))) | |
1171 | ||
1172 | (dnci sw-sp "store word (sp relative)" ((STALL STORE)) | |
1173 | "sw $rnl,$udisp7a4($spr)" | |
1174 | (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 2)) | |
1175 | (sequence () | |
1176 | (c-call VOID "check_write_to_text" (and (add udisp7a4 sp) (inv 3))) | |
1177 | (set (mem SI (and (add udisp7a4 sp) (inv 3))) rnl)) | |
1178 | ((mep (unit u-use-gpr (in usereg rnl)) | |
1179 | (unit u-use-gpr (in usereg sp)) | |
1180 | (unit u-exec)))) | |
1181 | ||
1182 | ||
1183 | (dnci lw-sp "load word (sp relative)" ((STALL LOAD) (LATENCY 2)) | |
1184 | "lw $rnl,$udisp7a4($spr)" | |
1185 | (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 3)) | |
1186 | (set rnl (mem SI (and (add udisp7a4 sp) (inv 3)))) | |
1187 | ((mep (unit u-use-gpr (in usereg sp)) | |
1188 | (unit u-exec) | |
1189 | (unit u-load-gpr (out loadreg rnl))))) | |
1190 | ||
1191 | (dnci sb-tp "store byte (tp relative)" ((STALL STORE)) | |
1192 | "sb $rn3c,$udisp7($tpr)" | |
1193 | (+ MAJ_8 (f-4 0) rn3c (f-8 0) udisp7) | |
1194 | (sequence () | |
1195 | (c-call VOID "check_write_to_text" (add (zext SI udisp7) tp)) | |
1196 | (set (mem QI (add (zext SI udisp7) tp)) (and rn3c #xff))) | |
1197 | ((mep (unit u-use-gpr (in usereg rn3c)) | |
1198 | (unit u-use-gpr (in usereg tp)) | |
1199 | (unit u-exec)))) | |
1200 | ||
1201 | (dnci sh-tp "store half-word (tp relative)" ((STALL STORE)) | |
1202 | "sh $rn3s,$udisp7a2($tpr)" | |
1203 | (+ MAJ_8 (f-4 0) rn3s (f-8 1) udisp7a2 (f-15 0)) | |
1204 | (sequence () | |
1205 | (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a2) tp) (inv 1))) | |
1206 | (set (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))) (and rn3s #xffff))) | |
1207 | ((mep (unit u-use-gpr (in usereg rn3s)) | |
1208 | (unit u-use-gpr (in usereg tp)) | |
1209 | (unit u-exec)))) | |
1210 | ||
1211 | (dnci sw-tp "store word (tp relative)" ((STALL STORE)) | |
1212 | "sw $rn3l,$udisp7a4($tpr)" | |
1213 | (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 2)) | |
1214 | (sequence () | |
1215 | (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a4) tp) (inv 3))) | |
1216 | (set (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))) rn3l)) | |
1217 | ((mep (unit u-use-gpr (in usereg rn3l)) | |
1218 | (unit u-use-gpr (in usereg tp)) | |
1219 | (unit u-exec)))) | |
1220 | ||
1221 | (dnci lb-tp "load byte (tp relative)" ((STALL LOAD) (LATENCY 2)) | |
1222 | "lb $rn3c,$udisp7($tpr)" | |
1223 | (+ MAJ_8 (f-4 1) rn3c (f-8 0) udisp7) | |
1224 | (set rn3c (ext SI (mem QI (add (zext SI udisp7) tp)))) | |
1225 | ((mep (unit u-use-gpr (in usereg tp)) | |
1226 | (unit u-exec) | |
1227 | (unit u-load-gpr (out loadreg rn3c))))) | |
1228 | ||
1229 | (dnci lh-tp "load half-word (tp relative)" ((STALL LOAD) (LATENCY 2)) | |
1230 | "lh $rn3s,$udisp7a2($tpr)" | |
1231 | (+ MAJ_8 (f-4 1) rn3s (f-8 1) udisp7a2 (f-15 0)) | |
1232 | (set rn3s (ext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))))) | |
1233 | ((mep (unit u-use-gpr (in usereg tp)) | |
1234 | (unit u-exec) | |
1235 | (unit u-load-gpr (out loadreg rn3s))))) | |
1236 | ||
1237 | (dnci lw-tp "load word (tp relative)" ((STALL LOAD) (LATENCY 2)) | |
1238 | "lw $rn3l,$udisp7a4($tpr)" | |
1239 | (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 3)) | |
1240 | (set rn3l (mem SI (and (add (zext SI udisp7a4) tp) (inv 3)))) | |
1241 | ((mep (unit u-use-gpr (in usereg tp)) | |
1242 | (unit u-exec) | |
1243 | (unit u-load-gpr (out loadreg rn3l))))) | |
1244 | ||
1245 | (dnci lbu-tp "load unsigned byte (tp relative)" ((STALL LOAD) (LATENCY 2)) | |
1246 | "lbu $rn3uc,$udisp7($tpr)" | |
1247 | (+ MAJ_4 (f-4 1) rn3uc (f-8 1) udisp7) | |
1248 | (set rn3uc (zext SI (mem QI (add (zext SI udisp7) tp)))) | |
1249 | ((mep (unit u-use-gpr (in usereg tp)) | |
1250 | (unit u-exec) | |
1251 | (unit u-load-gpr (out loadreg rn3uc))))) | |
1252 | ||
1253 | (dnci lhu-tp "load unsigned half-word (tp relative)" ((STALL LOAD) (LATENCY 2)) | |
1254 | "lhu $rn3us,$udisp7a2($tpr)" | |
1255 | (+ MAJ_8 (f-4 1) rn3us (f-8 1) udisp7a2 (f-15 1)) | |
1256 | (set rn3us (zext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))))) | |
1257 | ((mep (unit u-use-gpr (in usereg tp)) | |
1258 | (unit u-exec) | |
1259 | (unit u-load-gpr (out loadreg rn3us))))) | |
1260 | ||
1261 | (dnci sb16 "store byte (16 bit displacement)" ((STALL STORE)) | |
1262 | "sb $rnc,$sdisp16($rma)" | |
1263 | (+ MAJ_12 rnc rma (f-sub4 8) sdisp16) | |
1264 | (sequence () | |
1265 | (c-call VOID "check_write_to_text" (add rma (ext SI sdisp16))) | |
1266 | (set (mem QI (add rma (ext SI sdisp16))) (and rnc #xff))) | |
1267 | ((mep (unit u-use-gpr (in usereg rnc)) | |
1268 | (unit u-use-gpr (in usereg rma)) | |
1269 | (unit u-exec)))) | |
1270 | ||
1271 | (dnci sh16 "store half-word (16 bit displacement)" ((STALL STORE)) | |
1272 | "sh $rns,$sdisp16($rma)" | |
1273 | (+ MAJ_12 rns rma (f-sub4 9) sdisp16) | |
1274 | (sequence () | |
1275 | (c-call VOID "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 1))) | |
1276 | (set (mem HI (and (add rma (ext SI sdisp16)) (inv 1))) (and rns #xffff))) | |
1277 | ((mep (unit u-use-gpr (in usereg rns)) | |
1278 | (unit u-use-gpr (in usereg rma)) | |
1279 | (unit u-exec)))) | |
1280 | ||
1281 | (dnci sw16 "store word (16 bit displacement)" ((STALL STORE)) | |
1282 | "sw $rnl,$sdisp16($rma)" | |
1283 | (+ MAJ_12 rnl rma (f-sub4 10) sdisp16) | |
1284 | (sequence () | |
1285 | (c-call "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 3))) | |
1286 | (set (mem SI (and (add rma (ext SI sdisp16)) (inv 3))) rnl)) | |
1287 | ((mep (unit u-use-gpr (in usereg rnl)) | |
1288 | (unit u-use-gpr (in usereg rma)) | |
1289 | (unit u-exec)))) | |
1290 | ||
1291 | (dnci lb16 "load byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) | |
1292 | "lb $rnc,$sdisp16($rma)" | |
1293 | (+ MAJ_12 rnc rma (f-sub4 12) sdisp16) | |
1294 | (set rnc (ext SI (mem QI (add rma (ext SI sdisp16))))) | |
1295 | ((mep (unit u-use-gpr (in usereg rma)) | |
1296 | (unit u-exec) | |
1297 | (unit u-load-gpr (out loadreg rnc))))) | |
1298 | ||
1299 | (dnci lh16 "load half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) | |
1300 | "lh $rns,$sdisp16($rma)" | |
1301 | (+ MAJ_12 rns rma (f-sub4 13) sdisp16) | |
1302 | (set rns (ext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1))))) | |
1303 | ((mep (unit u-use-gpr (in usereg rma)) | |
1304 | (unit u-exec) | |
1305 | (unit u-load-gpr (out loadreg rns))))) | |
1306 | ||
1307 | (dnci lw16 "load word (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) | |
1308 | "lw $rnl,$sdisp16($rma)" | |
1309 | (+ MAJ_12 rnl rma (f-sub4 14) sdisp16) | |
1310 | (set rnl (mem SI (and (add rma (ext SI sdisp16)) (inv 3)))) | |
1311 | ((mep (unit u-use-gpr (in usereg rma)) | |
1312 | (unit u-exec) | |
1313 | (unit u-load-gpr (out loadreg rnl))))) | |
1314 | ||
1315 | (dnci lbu16 "load unsigned byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) | |
1316 | "lbu $rnuc,$sdisp16($rma)" | |
1317 | (+ MAJ_12 rnuc rma (f-sub4 11) sdisp16) | |
1318 | (set rnuc (zext SI (mem QI (add rma (ext SI sdisp16))))) | |
1319 | ((mep (unit u-use-gpr (in usereg rma)) | |
1320 | (unit u-exec) | |
1321 | (unit u-load-gpr (out loadreg rnuc))))) | |
1322 | ||
1323 | (dnci lhu16 "load unsigned half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) | |
1324 | "lhu $rnus,$sdisp16($rma)" | |
1325 | (+ MAJ_12 rnus rma (f-sub4 15) sdisp16) | |
1326 | (set rnus (zext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1))))) | |
1327 | ((mep (unit u-use-gpr (in usereg rma)) | |
1328 | (unit u-exec) | |
1329 | (unit u-load-gpr (out loadreg rnus))))) | |
1330 | ||
1331 | (dnci sw24 "store word (24 bit absolute addressing)" ((STALL STORE)) | |
1332 | "sw $rnl,($addr24a4)" | |
1333 | (+ MAJ_14 rnl addr24a4 (f-sub2 2)) | |
1334 | (sequence () | |
1335 | (c-call VOID "check_write_to_text" (zext SI addr24a4)) | |
1336 | (set (mem SI (zext SI addr24a4)) rnl)) | |
1337 | ((mep (unit u-use-gpr (in usereg rnl)) | |
1338 | (unit u-exec)))) | |
1339 | ||
1340 | (dnci lw24 "load word (24 bit absolute addressing)" ((STALL LOAD) (LATENCY 2)) | |
1341 | "lw $rnl,($addr24a4)" | |
1342 | (+ MAJ_14 rnl addr24a4 (f-sub2 3)) | |
1343 | (set rnl (mem SI (zext SI addr24a4))) | |
1344 | ((mep (unit u-exec) | |
1345 | (unit u-load-gpr (out loadreg rnl))))) | |
1346 | ||
1347 | \f | |
1348 | ; Extension instructions. | |
1349 | ||
1350 | (dnci extb "sign extend byte" () | |
1351 | "extb $rn" | |
1352 | (+ MAJ_1 rn (f-rm 0) (f-sub4 13)) | |
1353 | (set rn (ext SI (and QI rn #xff))) | |
1354 | ((mep (unit u-use-gpr (in usereg rn)) | |
1355 | (unit u-exec)))) | |
1356 | ||
1357 | (dnci exth "sign extend half-word" () | |
1358 | "exth $rn" | |
1359 | (+ MAJ_1 rn (f-rm 2) (f-sub4 13)) | |
1360 | (set rn (ext SI (and HI rn #xffff))) | |
1361 | ((mep (unit u-use-gpr (in usereg rn)) | |
1362 | (unit u-exec)))) | |
1363 | ||
1364 | (dnci extub "zero extend byte" () | |
1365 | "extub $rn" | |
1366 | (+ MAJ_1 rn (f-rm 8) (f-sub4 13)) | |
1367 | (set rn (zext SI (and rn #xff))) | |
1368 | ((mep (unit u-use-gpr (in usereg rn)) | |
1369 | (unit u-exec)))) | |
1370 | ||
1371 | (dnci extuh "zero extend half-word" () | |
1372 | "extuh $rn" | |
1373 | (+ MAJ_1 rn (f-rm 10) (f-sub4 13)) | |
1374 | (set rn (zext SI (and rn #xffff))) | |
1375 | ((mep (unit u-use-gpr (in usereg rn)) | |
1376 | (unit u-exec)))) | |
1377 | ||
1378 | \f | |
1379 | ; Shift amount manipulation instructions. | |
1380 | ||
b932c20b | 1381 | (dnci ssarb "set sar to bytes" ((STALL SSARB) VOLATILE) |
7acf4da6 DD |
1382 | "ssarb $udisp2($rm)" |
1383 | (+ MAJ_1 (f-4 0) (f-5 0) udisp2 rm (f-sub4 12)) | |
1384 | (if (c-call BI "big_endian_p") | |
1385 | (set sar (zext SI (mul (and (add udisp2 rm) 3) 8))) | |
1386 | (set sar (sub 32 (zext SI (mul (and (add udisp2 rm) 3) 8))))) | |
1387 | ((mep (unit u-use-gpr (in usereg rm)) | |
1388 | (unit u-exec)))) | |
1389 | ||
1390 | \f | |
1391 | ; Move instructions. | |
1392 | ||
1393 | (dnci mov "move" () | |
1394 | "mov $rn,$rm" | |
1395 | (+ MAJ_0 rn rm (f-sub4 0)) | |
1396 | (set rn rm) | |
1397 | ((mep (unit u-use-gpr (in usereg rm)) | |
1398 | (unit u-exec)))) | |
1399 | ||
1400 | (dnci movi8 "move 8-bit immediate" () | |
1401 | "mov $rn,$simm8" | |
1402 | (+ MAJ_5 rn simm8) | |
1403 | (set rn (ext SI simm8)) | |
1404 | ()) | |
1405 | ||
1406 | (dnci movi16 "move 16-bit immediate" () | |
1407 | "mov $rn,$simm16" | |
1408 | (+ MAJ_12 rn (f-rm 0) (f-sub4 1) simm16) | |
1409 | (set rn (ext SI simm16)) | |
1410 | ()) | |
1411 | ||
1412 | (dnci movu24 "move 24-bit unsigned immediate" () | |
1413 | "movu $rn3,$uimm24" | |
1414 | (+ MAJ_13 (f-4 0) rn3 uimm24) | |
1415 | (set rn3 (zext SI uimm24)) | |
1416 | ()) | |
1417 | ||
1418 | (dnci movu16 "move 16-bit unsigned immediate" () | |
1419 | "movu $rn,$uimm16" | |
1420 | (+ MAJ_12 rn (f-rm 1) (f-sub4 1) uimm16) | |
1421 | (set rn (zext SI uimm16)) | |
1422 | ()) | |
1423 | ||
1424 | (dnci movh "move high 16-bit immediate" () | |
1425 | "movh $rn,$uimm16" | |
1426 | (+ MAJ_12 rn (f-rm 2) (f-sub4 1) uimm16) | |
1427 | (set rn (sll uimm16 16)) | |
1428 | ()) | |
1429 | ||
1430 | \f | |
1431 | ; Arithmetic instructions. | |
1432 | ||
1433 | (dnci add3 "add three registers" () | |
1434 | "add3 $rl,$rn,$rm" | |
1435 | (+ MAJ_9 rn rm rl) | |
1436 | (set rl (add rn rm)) | |
1437 | ((mep (unit u-use-gpr (in usereg rn)) | |
1438 | (unit u-use-gpr (in usereg rm)) | |
1439 | (unit u-exec)))) | |
1440 | ||
1441 | (dnci add "add" () | |
1442 | "add $rn,$simm6" | |
1443 | (+ MAJ_6 rn simm6 (f-sub2 0)) | |
1444 | (set rn (add rn (ext SI simm6))) | |
1445 | ((mep (unit u-use-gpr (in usereg rn)) | |
1446 | (unit u-exec)))) | |
1447 | ||
1448 | (dnci add3i "add two registers and immediate" () | |
1449 | "add3 $rn,$spr,$uimm7a4" | |
1450 | (+ MAJ_4 rn (f-8 0) uimm7a4 (f-sub2 0)) | |
1451 | (set rn (add sp (zext SI uimm7a4))) | |
1452 | ((mep (unit u-use-gpr (in usereg sp)) | |
1453 | (unit u-exec)))) | |
1454 | ||
1455 | (dnci advck3 "add overflow check" ((STALL ADVCK)) | |
1456 | "advck3 \\$0,$rn,$rm" | |
1457 | (+ MAJ_0 rn rm (f-sub4 7)) | |
1458 | (if (add-oflag rn rm 0) | |
1459 | (set r0 1) | |
1460 | (set r0 0)) | |
1461 | ((mep (unit u-use-gpr (in usereg rn)) | |
1462 | (unit u-use-gpr (in usereg rm)) | |
1463 | (unit u-exec)))) | |
1464 | ||
1465 | (dnci sub "subtract" () | |
1466 | "sub $rn,$rm" | |
1467 | (+ MAJ_0 rn rm (f-sub4 4)) | |
1468 | (set rn (sub rn rm)) | |
1469 | ((mep (unit u-use-gpr (in usereg rn)) | |
1470 | (unit u-use-gpr (in usereg rm))))) | |
1471 | ||
1472 | (dnci sbvck3 "subtraction overflow check" ((STALL ADVCK)) | |
1473 | "sbvck3 \\$0,$rn,$rm" | |
1474 | (+ MAJ_0 rn rm (f-sub4 5)) | |
1475 | (if (sub-oflag rn rm 0) | |
1476 | (set r0 1) | |
1477 | (set r0 0)) | |
1478 | ((mep (unit u-use-gpr (in usereg rn)) | |
1479 | (unit u-use-gpr (in usereg rm)) | |
1480 | (unit u-exec)))) | |
1481 | ||
1482 | (dnci neg "negate" () | |
1483 | "neg $rn,$rm" | |
1484 | (+ MAJ_0 rn rm (f-sub4 1)) | |
1485 | (set rn (neg rm)) | |
1486 | ((mep (unit u-use-gpr (in usereg rm)) | |
1487 | (unit u-exec)))) | |
1488 | ||
1489 | (dnci slt3 "set if less than" () | |
1490 | "slt3 \\$0,$rn,$rm" | |
1491 | (+ MAJ_0 rn rm (f-sub4 2)) | |
1492 | (if (lt rn rm) | |
1493 | (set r0 1) | |
1494 | (set r0 0)) | |
1495 | ((mep (unit u-use-gpr (in usereg rn)) | |
1496 | (unit u-use-gpr (in usereg rm)) | |
1497 | (unit u-exec)))) | |
1498 | ||
1499 | (dnci sltu3 "set less than unsigned" () | |
1500 | "sltu3 \\$0,$rn,$rm" | |
1501 | (+ MAJ_0 rn rm (f-sub4 3)) | |
1502 | (if (ltu rn rm) | |
1503 | (set r0 1) | |
1504 | (set r0 0)) | |
1505 | ((mep (unit u-use-gpr (in usereg rn)) | |
1506 | (unit u-use-gpr (in usereg rm)) | |
1507 | (unit u-exec)))) | |
1508 | ||
1509 | (dnci slt3i "set if less than immediate" () | |
1510 | "slt3 \\$0,$rn,$uimm5" | |
1511 | (+ MAJ_6 rn uimm5 (f-sub3 1)) | |
1512 | (if (lt rn (zext SI uimm5)) | |
1513 | (set r0 1) | |
1514 | (set r0 0)) | |
1515 | ((mep (unit u-use-gpr (in usereg rn)) | |
1516 | (unit u-exec)))) | |
1517 | ||
1518 | (dnci sltu3i "set if less than unsigned immediate" () | |
1519 | "sltu3 \\$0,$rn,$uimm5" | |
1520 | (+ MAJ_6 rn uimm5 (f-sub3 5)) | |
1521 | (if (ltu rn (zext SI uimm5)) | |
1522 | (set r0 1) | |
1523 | (set r0 0)) | |
1524 | ()) | |
1525 | ||
1526 | (dnci sl1ad3 "shift left one and add" ((STALL INT2)) | |
1527 | "sl1ad3 \\$0,$rn,$rm" | |
1528 | (+ MAJ_2 rn rm (f-sub4 6)) | |
1529 | (set r0 (add (sll rn 1) rm)) | |
1530 | ((mep (unit u-use-gpr (in usereg rn)) | |
1531 | (unit u-use-gpr (in usereg rm)) | |
1532 | (unit u-exec)))) | |
1533 | ||
1534 | (dnci sl2ad3 "shift left two and add" ((STALL INT2)) | |
1535 | "sl2ad3 \\$0,$rn,$rm" | |
1536 | (+ MAJ_2 rn rm (f-sub4 7)) | |
1537 | (set r0 (add (sll rn 2) rm)) | |
1538 | ((mep (unit u-use-gpr (in usereg rn)) | |
1539 | (unit u-use-gpr (in usereg rm)) | |
1540 | (unit u-exec)))) | |
1541 | ||
1542 | (dnci add3x "three operand add (extended)" () | |
1543 | "add3 $rn,$rm,$simm16" | |
1544 | (+ MAJ_12 rn rm (f-sub4 0) simm16) | |
1545 | (set rn (add rm (ext SI simm16))) | |
1546 | ((mep (unit u-use-gpr (in usereg rm)) | |
1547 | (unit u-exec)))) | |
1548 | ||
1549 | (dnci slt3x "set if less than (extended)" () | |
1550 | "slt3 $rn,$rm,$simm16" | |
1551 | (+ MAJ_12 rn rm (f-sub4 2) simm16) | |
1552 | (if (lt rm (ext SI simm16)) | |
1553 | (set rn 1) | |
1554 | (set rn 0)) | |
1555 | ((mep (unit u-use-gpr (in usereg rm)) | |
1556 | (unit u-exec)))) | |
1557 | ||
1558 | (dnci sltu3x "set if less than unsigned (extended)" () | |
1559 | "sltu3 $rn,$rm,$uimm16" | |
1560 | (+ MAJ_12 rn rm (f-sub4 3) uimm16) | |
1561 | (if (ltu rm (zext SI uimm16)) | |
1562 | (set rn 1) | |
1563 | (set rn 0)) | |
1564 | ((mep (unit u-use-gpr (in usereg rm)) | |
1565 | (unit u-exec)))) | |
1566 | ||
1567 | \f | |
1568 | ; Logical instructions. | |
1569 | ||
1570 | (dnci or "bitwise or" () | |
1571 | "or $rn,$rm" | |
1572 | (+ MAJ_1 rn rm (f-sub4 0)) | |
1573 | (set rn (or rn rm)) | |
1574 | ((mep (unit u-use-gpr (in usereg rn)) | |
1575 | (unit u-use-gpr (in usereg rm)) | |
1576 | (unit u-exec)))) | |
1577 | ||
1578 | (dnci and "bitwise and" () | |
1579 | "and $rn,$rm" | |
1580 | (+ MAJ_1 rn rm (f-sub4 1)) | |
1581 | (set rn (and rn rm)) | |
1582 | ((mep (unit u-use-gpr (in usereg rn)) | |
1583 | (unit u-use-gpr (in usereg rm)) | |
1584 | (unit u-exec)))) | |
1585 | ||
1586 | (dnci xor "bitwise exclusive or" () | |
1587 | "xor $rn,$rm" | |
1588 | (+ MAJ_1 rn rm (f-sub4 2)) | |
1589 | (set rn (xor rn rm)) | |
1590 | ((mep (unit u-use-gpr (in usereg rn)) | |
1591 | (unit u-use-gpr (in usereg rm)) | |
1592 | (unit u-exec)))) | |
1593 | ||
1594 | (dnci nor "bitwise negated or" () | |
1595 | "nor $rn,$rm" | |
1596 | (+ MAJ_1 rn rm (f-sub4 3)) | |
1597 | (set rn (inv (or rn rm))) | |
1598 | ((mep (unit u-use-gpr (in usereg rn)) | |
1599 | (unit u-use-gpr (in usereg rm)) | |
1600 | (unit u-exec)))) | |
1601 | ||
1602 | (dnci or3 "or three operand" () | |
1603 | "or3 $rn,$rm,$uimm16" | |
1604 | (+ MAJ_12 rn rm (f-sub4 4) uimm16) | |
1605 | (set rn (or rm (zext SI uimm16))) | |
1606 | ((mep (unit u-use-gpr (in usereg rm)) | |
1607 | (unit u-exec)))) | |
1608 | ||
1609 | (dnci and3 "and three operand" () | |
1610 | "and3 $rn,$rm,$uimm16" | |
1611 | (+ MAJ_12 rn rm (f-sub4 5) uimm16) | |
1612 | (set rn (and rm (zext SI uimm16))) | |
1613 | ((mep (unit u-use-gpr (in usereg rm)) | |
1614 | (unit u-exec)))) | |
1615 | ||
1616 | (dnci xor3 "exclusive or three operand" () | |
1617 | "xor3 $rn,$rm,$uimm16" | |
1618 | (+ MAJ_12 rn rm (f-sub4 6) uimm16) | |
1619 | (set rn (xor rm (zext SI uimm16))) | |
1620 | ((mep (unit u-use-gpr (in usereg rm)) | |
1621 | (unit u-exec)))) | |
1622 | ||
1623 | \f | |
1624 | ; Shift instructions. | |
1625 | ||
1626 | (dnci sra "shift right arithmetic" ((STALL INT2)) | |
1627 | "sra $rn,$rm" | |
1628 | (+ MAJ_2 rn rm (f-sub4 13)) | |
1629 | (set rn (sra rn (and rm #x1f))) | |
1630 | ((mep (unit u-use-gpr (in usereg rn)) | |
1631 | (unit u-use-gpr (in usereg rm)) | |
1632 | (unit u-exec)))) | |
1633 | ||
1634 | (dnci srl "shift right logical" ((STALL INT2)) | |
1635 | "srl $rn,$rm" | |
1636 | (+ MAJ_2 rn rm (f-sub4 12)) | |
1637 | (set rn (srl rn (and rm #x1f))) | |
1638 | ((mep (unit u-use-gpr (in usereg rn)) | |
1639 | (unit u-use-gpr (in usereg rm)) | |
1640 | (unit u-exec)))) | |
1641 | ||
1642 | (dnci sll "shift left logical" ((STALL INT2)) | |
1643 | "sll $rn,$rm" | |
1644 | (+ MAJ_2 rn rm (f-sub4 14)) | |
1645 | (set rn (sll rn (and rm #x1f))) | |
1646 | ((mep (unit u-use-gpr (in usereg rn)) | |
1647 | (unit u-use-gpr (in usereg rm)) | |
1648 | (unit u-exec)))) | |
1649 | ||
1650 | (dnci srai "shift right arithmetic (immediate)" ((STALL SHIFTI)) | |
1651 | "sra $rn,$uimm5" | |
1652 | (+ MAJ_6 rn uimm5 (f-sub3 3)) | |
1653 | (set rn (sra rn uimm5)) | |
1654 | ((mep (unit u-use-gpr (in usereg rn)) | |
1655 | (unit u-exec)))) | |
1656 | ||
1657 | (dnci srli "shift right logical (immediate)" ((STALL SHIFTI)) | |
1658 | "srl $rn,$uimm5" | |
1659 | (+ MAJ_6 rn uimm5 (f-sub3 2)) | |
1660 | (set rn (srl rn uimm5)) | |
1661 | ((mep (unit u-use-gpr (in usereg rn)) | |
1662 | (unit u-exec)))) | |
1663 | ||
1664 | (dnci slli "shift left logical (immediate)" ((STALL SHIFTI)) | |
1665 | "sll $rn,$uimm5" | |
1666 | (+ MAJ_6 rn uimm5 (f-sub3 6)) | |
1667 | (set rn (sll rn uimm5)) | |
1668 | ((mep (unit u-use-gpr (in usereg rn)) | |
1669 | (unit u-exec)))) | |
1670 | ||
1671 | (dnci sll3 "three-register shift left logical" ((STALL INT2)) | |
1672 | "sll3 \\$0,$rn,$uimm5" | |
1673 | (+ MAJ_6 rn uimm5 (f-sub3 7)) | |
1674 | (set r0 (sll rn uimm5)) | |
1675 | ((mep (unit u-use-gpr (in usereg rn)) | |
1676 | (unit u-exec)))) | |
1677 | ||
b932c20b | 1678 | (dnci fsft "field shift" ((STALL FSFT) VOLATILE) |
7acf4da6 DD |
1679 | "fsft $rn,$rm" |
1680 | (+ MAJ_2 rn rm (f-sub4 15)) | |
1681 | (sequence ((DI temp) (QI shamt)) | |
1682 | (set shamt (and sar #x3f)) | |
1683 | (set temp (sll (or (sll (zext DI rn) 32) (zext DI rm)) shamt)) | |
1684 | (set rn (subword SI (srl temp 32) 1))) | |
1685 | ((mep (unit u-use-gpr (in usereg rn)) | |
1686 | (unit u-use-gpr (in usereg rm)) | |
1687 | (unit u-exec)))) | |
1688 | ||
1689 | \f | |
1690 | ; Branch/jump instructions. | |
1691 | ||
1692 | (dnci bra "branch" (RELAXABLE) | |
1693 | "bra $pcrel12a2" | |
1694 | (+ MAJ_11 pcrel12a2 (f-15 0)) | |
1695 | (set-vliw-alignment-modified pc pcrel12a2) | |
1696 | ((mep (unit u-branch) | |
1697 | (unit u-exec)))) | |
1698 | ||
1699 | (dnci beqz "branch if equal zero" (RELAXABLE) | |
1700 | "beqz $rn,$pcrel8a2" | |
1701 | (+ MAJ_10 rn pcrel8a2 (f-15 0)) | |
1702 | (if (eq rn 0) | |
1703 | (set-vliw-alignment-modified pc pcrel8a2)) | |
1704 | ((mep (unit u-use-gpr (in usereg rn)) | |
1705 | (unit u-exec) | |
1706 | (unit u-branch)))) | |
1707 | ||
1708 | (dnci bnez "branch if not equal zero" (RELAXABLE) | |
1709 | "bnez $rn,$pcrel8a2" | |
1710 | (+ MAJ_10 rn pcrel8a2 (f-15 1)) | |
1711 | (if (ne rn 0) | |
1712 | (set-vliw-alignment-modified pc pcrel8a2)) | |
1713 | ((mep (unit u-use-gpr (in usereg rn)) | |
1714 | (unit u-exec) | |
1715 | (unit u-branch)))) | |
1716 | ||
1717 | (dnci beqi "branch equal immediate" (RELAXABLE) | |
1718 | "beqi $rn,$uimm4,$pcrel17a2" | |
1719 | (+ MAJ_14 rn uimm4 (f-sub4 0) pcrel17a2) | |
1720 | (if (eq rn (zext SI uimm4)) | |
1721 | (set-vliw-alignment-modified pc pcrel17a2)) | |
1722 | ((mep (unit u-use-gpr (in usereg rn)) | |
1723 | (unit u-exec) | |
1724 | (unit u-branch)))) | |
1725 | ||
1726 | (dnci bnei "branch not equal immediate" (RELAXABLE) | |
1727 | "bnei $rn,$uimm4,$pcrel17a2" | |
1728 | (+ MAJ_14 rn uimm4 (f-sub4 4) pcrel17a2) | |
1729 | (if (ne rn (zext SI uimm4)) | |
1730 | (set-vliw-alignment-modified pc pcrel17a2)) | |
1731 | ((mep (unit u-use-gpr (in usereg rn)) | |
1732 | (unit u-exec) | |
1733 | (unit u-branch)))) | |
1734 | ||
1735 | (dnci blti "branch less than immediate" (RELAXABLE) | |
1736 | "blti $rn,$uimm4,$pcrel17a2" | |
1737 | (+ MAJ_14 rn uimm4 (f-sub4 12) pcrel17a2) | |
1738 | (if (lt rn (zext SI uimm4)) | |
1739 | (set-vliw-alignment-modified pc pcrel17a2)) | |
1740 | ((mep (unit u-use-gpr (in usereg rn)) | |
1741 | (unit u-exec) | |
1742 | (unit u-branch)))) | |
1743 | ||
1744 | (dnci bgei "branch greater than immediate" (RELAXABLE) | |
1745 | "bgei $rn,$uimm4,$pcrel17a2" | |
1746 | (+ MAJ_14 rn uimm4 (f-sub4 8) pcrel17a2) | |
1747 | (if (ge rn (zext SI uimm4)) | |
1748 | (set-vliw-alignment-modified pc pcrel17a2)) | |
1749 | ((mep (unit u-use-gpr (in usereg rn)) | |
1750 | (unit u-exec) | |
1751 | (unit u-branch)))) | |
1752 | ||
1753 | (dnci beq "branch equal" () | |
1754 | "beq $rn,$rm,$pcrel17a2" | |
1755 | (+ MAJ_14 rn rm (f-sub4 1) pcrel17a2) | |
1756 | (if (eq rn rm) | |
1757 | (set-vliw-alignment-modified pc pcrel17a2)) | |
1758 | ((mep (unit u-use-gpr (in usereg rn)) | |
1759 | (unit u-use-gpr (in usereg rm)) | |
1760 | (unit u-exec) | |
1761 | (unit u-branch)))) | |
1762 | ||
1763 | (dnci bne "branch not equal" () | |
1764 | "bne $rn,$rm,$pcrel17a2" | |
1765 | (+ MAJ_14 rn rm (f-sub4 5) pcrel17a2) | |
1766 | (if (ne rn rm) | |
1767 | (set-vliw-alignment-modified pc pcrel17a2)) | |
1768 | ((mep (unit u-use-gpr (in usereg rn)) | |
1769 | (unit u-use-gpr (in usereg rm)) | |
1770 | (unit u-exec) | |
1771 | (unit u-branch)))) | |
1772 | ||
1773 | (dnci bsr12 "branch to subroutine (12 bit displacement)" (RELAXABLE) | |
1774 | "bsr $pcrel12a2" | |
1775 | (+ MAJ_11 pcrel12a2 (f-15 1)) | |
1776 | (sequence () | |
1777 | (cg-profile pc pcrel12a2) | |
1778 | (set-vliw-modified-pcrel-offset lp 2 4 8) | |
1779 | (set-vliw-alignment-modified pc pcrel12a2)) | |
1780 | ((mep (unit u-exec) | |
1781 | (unit u-branch)))) | |
1782 | ||
1783 | (dnci bsr24 "branch to subroutine (24 bit displacement)" () | |
1784 | "bsr $pcrel24a2" | |
1785 | (+ MAJ_13 (f-4 1) (f-sub4 9) pcrel24a2) | |
1786 | (sequence () | |
1787 | (cg-profile pc pcrel24a2) | |
1788 | (set-vliw-modified-pcrel-offset lp 4 4 8) | |
1789 | (set-vliw-alignment-modified pc pcrel24a2)) | |
1790 | ((mep (unit u-exec) | |
1791 | (unit u-branch)))) | |
1792 | ||
1793 | (dnci jmp "jump" () | |
1794 | "jmp $rm" | |
1795 | (+ MAJ_1 (f-rn 0) rm (f-sub4 14)) | |
1796 | (sequence () | |
1797 | (if (eq (get-psw.om) 0) | |
1798 | ;; core mode | |
1799 | (if (get-rm.lsb) | |
1800 | (sequence () | |
1801 | (set-psw.om 1) ;; enter VLIW mode | |
1802 | (set-vliw-aliignment-modified-by-option pc rm)) | |
1803 | (set pc (and rm (inv 1)))) | |
1804 | ;; VLIW mode | |
1805 | (if (get-rm.lsb) | |
1806 | (sequence () | |
1807 | (set-psw.om 0) ;; enter core mode | |
1808 | (set pc (and rm (inv 1)))) | |
1809 | (set-vliw-aliignment-modified-by-option pc rm))) | |
1810 | (cg-profile-jump pc rm)) | |
1811 | ((mep (unit u-use-gpr (in usereg rm)) | |
1812 | (unit u-exec) | |
1813 | (unit u-branch)))) | |
1814 | ||
1815 | (dnci jmp24 "jump (24 bit target)" () | |
1816 | "jmp $pcabs24a2" | |
1817 | (+ MAJ_13 (f-4 1) (f-sub4 8) pcabs24a2) | |
1818 | (sequence () | |
1819 | (set-vliw-alignment-modified pc (or (and pc #xf0000000) pcabs24a2)) | |
1820 | (cg-profile-jump pc pcabs24a2)) | |
1821 | ((mep (unit u-exec) | |
1822 | (unit u-branch)))) | |
1823 | ||
1824 | (dnci jsr "jump to subroutine" () | |
1825 | "jsr $rm" | |
1826 | (+ MAJ_1 (f-rn 0) rm (f-sub4 15)) | |
1827 | (sequence () | |
1828 | (cg-profile pc rm) | |
1829 | (set-vliw-modified-pcrel-offset lp 2 4 8) | |
1830 | (set-vliw-alignment-modified pc rm)) | |
1831 | ((mep (unit u-use-gpr (in usereg rm)) | |
1832 | (unit u-exec) | |
1833 | (unit u-branch)))) | |
1834 | ||
1835 | (dnci ret "return from subroutine" ((STALL RET)) | |
1836 | "ret" | |
1837 | (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 2)) | |
1838 | (sequence () | |
1839 | (if (eq (get-psw.om) 0) | |
1840 | ;; core mode | |
1841 | (if (get-lp.ltom) ;; link-pointer "toggle mode" bit | |
1842 | (sequence () | |
1843 | (set-psw.om 1) ;; enter VLIW mode | |
1844 | (set-vliw-aliignment-modified-by-option pc lp)) | |
1845 | (set pc (and lp (inv 1)))) | |
1846 | ;; VLIW mode | |
1847 | (if (get-lp.ltom) ;; link-pointer "toggle mode" bit | |
1848 | (sequence () | |
1849 | (set-psw.om 0) ;; enter VLIW mode | |
1850 | (set pc (and lp (inv 1)))) | |
1851 | (set-vliw-aliignment-modified-by-option pc lp))) | |
1852 | (c-call VOID "notify_ret" pc)) | |
1853 | ((mep (unit u-exec) | |
1854 | (unit u-branch)))) | |
1855 | ||
1856 | \f | |
1857 | ; Repeat instructions. | |
1858 | ||
1859 | (dnci repeat "repeat specified repeat block" () | |
1860 | "repeat $rn,$pcrel17a2" | |
1861 | (+ MAJ_14 rn (f-rm 0) (f-sub4 9) pcrel17a2) | |
1862 | (sequence () | |
1863 | (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8) | |
1864 | (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2) | |
1865 | (set (reg h-csr 6) rn)) | |
1866 | ((mep (unit u-use-gpr (in usereg rn)) | |
1867 | (unit u-exec)))) | |
1868 | ||
1869 | (dnci erepeat "endless repeat" () | |
1870 | "erepeat $pcrel17a2" | |
1871 | (+ MAJ_14 (f-rn 0) (f-rm 1) (f-sub4 9) pcrel17a2) | |
1872 | (sequence () | |
1873 | (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8) | |
1874 | (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2) | |
1875 | (set-rpe.elr 1) | |
1876 | ; rpc may be undefined for erepeat | |
1877 | ; use 1 to trigger repeat logic in the sim's main loop | |
1878 | (set (reg h-csr 6) 1)) | |
1879 | ()) | |
1880 | ||
1881 | \f | |
1882 | ; Control instructions. | |
1883 | ||
1884 | ;; special store variants | |
1885 | ||
1886 | (dnci stc_lp "store to control register lp" ((STALL STC)) | |
1887 | "stc $rn,\\$lp" | |
1888 | (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0)) | |
1889 | (set lp rn) | |
1890 | ((mep (unit u-use-gpr (in usereg rn)) | |
1891 | (unit u-store-ctrl-reg (out storereg lp)) | |
1892 | (unit u-exec)))) | |
1893 | ||
1894 | (dnci stc_hi "store to control register hi" ((STALL STC)) | |
1895 | "stc $rn,\\$hi" | |
1896 | (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0)) | |
1897 | (set hi rn) | |
1898 | ((mep (unit u-use-gpr (in usereg rn)) | |
1899 | (unit u-store-ctrl-reg (out storereg hi)) | |
1900 | (unit u-exec)))) | |
1901 | ||
1902 | (dnci stc_lo "store to control register lo" ((STALL STC)) | |
1903 | "stc $rn,\\$lo" | |
1904 | (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0)) | |
1905 | (set lo rn) | |
1906 | ((mep (unit u-use-gpr (in usereg rn)) | |
1907 | (unit u-store-ctrl-reg (out storereg lo)) | |
1908 | (unit u-exec)))) | |
1909 | ||
1910 | ;; general store | |
1911 | ||
1912 | (dnci stc "store to control register" (VOLATILE (STALL STC)) | |
1913 | "stc $rn,$csrn" | |
1914 | (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 0)) | |
1915 | (set csrn rn) | |
1916 | ((mep (unit u-use-gpr (in usereg rn)) | |
1917 | (unit u-store-ctrl-reg (out storereg csrn)) | |
1918 | (unit u-exec)))) | |
1919 | ||
1920 | ;; special load variants | |
1921 | ||
1922 | (dnci ldc_lp "load from control register lp" ((STALL LDC)) | |
1923 | "ldc $rn,\\$lp" | |
1924 | (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1)) | |
1925 | (set rn lp) | |
1926 | ((mep (unit u-use-ctrl-reg (in usereg lp)) | |
1927 | (unit u-exec) | |
1928 | (unit u-load-gpr (out loadreg rn))))) | |
1929 | ||
1930 | ||
1931 | (dnci ldc_hi "load from control register hi" ((STALL LDC)) | |
1932 | "ldc $rn,\\$hi" | |
1933 | (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1)) | |
1934 | (set rn hi) | |
1935 | ((mep (unit u-use-ctrl-reg (in usereg hi)) | |
1936 | (unit u-exec) | |
1937 | (unit u-load-gpr (out loadreg rn))))) | |
1938 | ||
1939 | (dnci ldc_lo "load from control register lo" ((STALL LDC)) | |
1940 | "ldc $rn,\\$lo" | |
1941 | (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1)) | |
1942 | (set rn lo) | |
1943 | ((mep (unit u-use-ctrl-reg (in usereg lo)) | |
1944 | (unit u-exec) | |
1945 | (unit u-load-gpr (out loadreg rn))))) | |
1946 | ||
1947 | ;; general load | |
1948 | ||
1949 | (dnci ldc "load from control register" (VOLATILE (STALL LDC) (LATENCY 2)) | |
1950 | "ldc $rn,$csrn" | |
1951 | (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 1)) | |
1952 | (if (eq (ifield f-csrn) 0) | |
1953 | ;; loading from the pc | |
1954 | (set-vliw-modified-pcrel-offset rn 2 4 8) | |
1955 | ;; loading from something else | |
1956 | (set rn csrn)) | |
1957 | ((mep (unit u-use-ctrl-reg (in usereg csrn)) | |
1958 | (unit u-exec) | |
1959 | (unit u-load-gpr (out loadreg rn))))) | |
1960 | ||
1961 | (dnci di "disable interrupt" (VOLATILE) | |
1962 | "di" | |
1963 | (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 0)) | |
1964 | ; clear psw.iec | |
1965 | (set psw (sll (srl psw 1) 1)) | |
1966 | ()) | |
1967 | ||
1968 | (dnci ei "enable interrupt" (VOLATILE) | |
1969 | "ei" | |
1970 | (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 0)) | |
1971 | ; set psw.iec | |
1972 | (set psw (or psw 1)) | |
1973 | ()) | |
1974 | ||
1975 | (dnci reti "return from interrupt" ((STALL RET)) | |
1976 | "reti" | |
1977 | (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 2)) | |
1978 | (if (eq (get-psw.om) 0) | |
1979 | ;; core operation mode | |
1980 | (if (get-psw.nmi) | |
1981 | ;; return from NMI | |
1982 | (if (get-npc.ntom) | |
1983 | ;; return in VLIW operation mode | |
1984 | (sequence () | |
1985 | (set-psw.om 1) | |
1986 | (set-vliw-aliignment-modified-by-option pc npc) | |
1987 | (set-psw.nmi 0)) | |
1988 | ;; return in core mode | |
1989 | (sequence () | |
1990 | (set pc (and npc (inv 1))) | |
1991 | (set-psw.nmi 0))) | |
1992 | ;; return from non-NMI | |
1993 | (if (get-epc.etom) | |
1994 | ;; return in VLIW mode | |
1995 | (sequence () | |
1996 | (set-psw.om 1) | |
1997 | (set-vliw-aliignment-modified-by-option pc epc) | |
1998 | (set-psw.umc (get-psw.ump)) | |
1999 | (set-psw.iec (get-psw.iep))) | |
2000 | ;; return in core mode | |
2001 | (sequence () | |
2002 | (set pc (and epc (inv 1))) | |
2003 | (set-psw.umc (get-psw.ump)) | |
2004 | (set-psw.iec (get-psw.iep))))) | |
2005 | ;; VLIW operation mode | |
2006 | ;; xxx undefined | |
2007 | (nop)) | |
2008 | ((mep (unit u-exec) | |
2009 | (unit u-branch)))) | |
2010 | ||
2011 | (dnci halt "halt pipeline" (VOLATILE) | |
2012 | "halt" | |
2013 | (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 2)) | |
2014 | ; set psw.halt | |
2015 | (set (raw-reg h-csr 16) (or psw (sll 1 11))) | |
2016 | ()) | |
2017 | ||
2018 | (dnci sleep "sleep pipeline" (VOLATILE) | |
2019 | "sleep" | |
2020 | (+ MAJ_7 (f-rn 0) (f-rm 6) (f-sub4 2)) | |
2021 | (c-call VOID "do_sleep") | |
2022 | ()) | |
2023 | ||
2024 | (dnci swi "software interrupt" (MAY_TRAP VOLATILE) | |
2025 | "swi $uimm2" | |
2026 | (+ MAJ_7 (f-rn 0) (f-8 0) (f-9 0) uimm2 (f-sub4 6)) | |
2027 | (cond | |
2028 | ((eq uimm2 0) (set exc (or exc (sll 1 4)))) | |
2029 | ((eq uimm2 1) (set exc (or exc (sll 1 5)))) | |
2030 | ((eq uimm2 2) (set exc (or exc (sll 1 6)))) | |
2031 | ((eq uimm2 3) (set exc (or exc (sll 1 7))))) | |
2032 | ()) | |
2033 | ||
2034 | (dnci break "break exception" (MAY_TRAP VOLATILE) | |
2035 | "break" | |
2036 | (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 2)) | |
2037 | (set pc (c-call USI "break_exception" pc)) | |
2038 | ((mep (unit u-exec) | |
2039 | (unit u-branch)))) | |
2040 | ||
2041 | (dnci syncm "synchronise with memory" (VOLATILE) | |
2042 | "syncm" | |
2043 | (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 1)) | |
2044 | (unimp "syncm") | |
2045 | ()) | |
2046 | ||
2047 | (dnci stcb "store in control bus space" (VOLATILE (STALL STCB)) | |
2048 | "stcb $rn,$uimm16" | |
2049 | (+ MAJ_15 rn (f-rm 0) (f-sub4 4) uimm16) | |
2050 | (c-call VOID "do_stcb" rn uimm16) | |
2051 | ((mep (unit u-use-gpr (in usereg rn)) | |
2052 | (unit u-exec) | |
2053 | (unit u-stcb)))) | |
2054 | ||
2055 | (dnci ldcb "load from control bus space" (VOLATILE (STALL LDCB) (LATENCY 3)) | |
2056 | "ldcb $rn,$uimm16" | |
2057 | (+ MAJ_15 rn (f-rm 1) (f-sub4 4) uimm16) | |
2058 | (set rn (c-call SI "do_ldcb" uimm16)) | |
2059 | ((mep (unit u-ldcb) | |
2060 | (unit u-exec) | |
2061 | (unit u-ldcb-gpr (out loadreg rn))))) | |
2062 | ||
2063 | \f | |
2064 | ; Bit manipulation instructions. | |
2065 | ; The following instructions become the reserved instruction when the | |
2066 | ; bit manipulation option is off. | |
2067 | ||
2068 | (dnci bsetm "set bit in memory" (OPTIONAL_BIT_INSN) | |
2069 | "bsetm ($rma),$uimm3" | |
2070 | (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 0)) | |
2071 | (sequence () | |
2072 | (c-call "check_option_bit" pc) | |
2073 | (set (mem UQI rma) (or (mem UQI rma) (sll 1 uimm3)))) | |
2074 | ((mep (unit u-use-gpr (in usereg rma)) | |
2075 | (unit u-exec)))) | |
2076 | ||
2077 | (dnci bclrm "clear bit in memory" (OPTIONAL_BIT_INSN) | |
2078 | "bclrm ($rma),$uimm3" | |
2079 | (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 1)) | |
2080 | (sequence () | |
2081 | (c-call "check_option_bit" pc) | |
2082 | (set (mem UQI rma) (and (mem UQI rma) (inv (sll 1 uimm3))))) | |
2083 | ((mep (unit u-use-gpr (in usereg rma)) | |
2084 | (unit u-exec)))) | |
2085 | ||
2086 | (dnci bnotm "toggle bit in memory" (OPTIONAL_BIT_INSN) | |
2087 | "bnotm ($rma),$uimm3" | |
2088 | (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 2)) | |
2089 | (sequence () | |
2090 | (c-call "check_option_bit" pc) | |
2091 | (set (mem UQI rma) (xor (mem UQI rma) (sll 1 uimm3)))) | |
2092 | ((mep (unit u-use-gpr (in usereg rma)) | |
2093 | (unit u-exec)))) | |
2094 | ||
2095 | (dnci btstm "test bit in memory" (OPTIONAL_BIT_INSN) | |
2096 | "btstm \\$0,($rma),$uimm3" | |
2097 | (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 3)) | |
2098 | (sequence () | |
2099 | (c-call "check_option_bit" pc) | |
2100 | (set r0 (zext SI (and UQI (mem UQI rma) (sll 1 uimm3))))) | |
2101 | ((mep (unit u-use-gpr (in usereg rma)) | |
2102 | (unit u-exec)))) | |
2103 | ||
2104 | (dnci tas "test and set" (OPTIONAL_BIT_INSN) | |
2105 | "tas $rn,($rma)" | |
2106 | (+ MAJ_2 rn rma (f-sub4 4)) | |
2107 | (sequence ((SI result)) | |
2108 | (c-call "check_option_bit" pc) | |
2109 | (set result (zext SI (mem UQI rma))) | |
2110 | (set (mem UQI rma) 1) | |
2111 | (set rn result)) | |
2112 | ((mep (unit u-use-gpr (in usereg rma)) | |
2113 | (unit u-exec)))) | |
2114 | ||
2115 | \f | |
2116 | ; Data cache instruction. | |
2117 | ||
2118 | (dnci cache "cache operations" (VOLATILE) | |
2119 | "cache $cimm4,($rma)" | |
2120 | (+ MAJ_7 cimm4 rma (f-sub4 4)) | |
2121 | (c-call VOID "do_cache" cimm4 rma pc) | |
2122 | ((mep (unit u-use-gpr (in usereg rma)) | |
2123 | (unit u-exec)))) | |
2124 | ||
2125 | \f | |
2126 | ; Multiply instructions. | |
2127 | ; These instructions become the RI when the 32-bit multiply | |
2128 | ; instruction option is off. | |
2129 | ||
2130 | (dnci mul "multiply" (OPTIONAL_MUL_INSN (STALL MUL)) | |
2131 | "mul $rn,$rm" | |
2132 | (+ MAJ_1 rn rm (f-sub4 4)) | |
2133 | (sequence ((DI result)) | |
2134 | (c-call "check_option_mul" pc) | |
2135 | (set result (mul (ext DI rn) (ext DI rm))) | |
2136 | (set hi (subword SI result 0)) | |
2137 | (set lo (subword SI result 1))) | |
2138 | ((mep (unit u-use-gpr (in usereg rn)) | |
2139 | (unit u-use-gpr (in usereg rm)) | |
2140 | (unit u-exec) | |
2141 | (unit u-multiply)))) | |
2142 | ||
2143 | (dnci mulu "multiply unsigned" (OPTIONAL_MUL_INSN (STALL MUL)) | |
2144 | "mulu $rn,$rm" | |
2145 | (+ MAJ_1 rn rm (f-sub4 5)) | |
2146 | (sequence ((DI result)) | |
2147 | (c-call "check_option_mul" pc) | |
2148 | (set result (mul (zext UDI rn) (zext UDI rm))) | |
2149 | (set hi (subword SI result 0)) | |
2150 | (set lo (subword SI result 1))) | |
2151 | ((mep (unit u-use-gpr (in usereg rn)) | |
2152 | (unit u-use-gpr (in usereg rm)) | |
2153 | (unit u-exec) | |
2154 | (unit u-multiply)))) | |
2155 | ||
2156 | (dnci mulr "multiply, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) | |
2157 | "mulr $rn,$rm" | |
2158 | (+ MAJ_1 rn rm (f-sub4 6)) | |
2159 | (sequence ((DI result)) | |
2160 | (c-call "check_option_mul" pc) | |
2161 | (set result (mul (ext DI rn) (ext DI rm))) | |
2162 | (set hi (subword SI result 0)) | |
2163 | (set lo (subword SI result 1)) | |
2164 | (set rn (subword SI result 1))) | |
2165 | ((mep (unit u-use-gpr (in usereg rn)) | |
2166 | (unit u-use-gpr (in usereg rm)) | |
2167 | (unit u-exec) | |
2168 | (unit u-multiply) | |
2169 | (unit u-mul-gpr (out resultreg rn))))) | |
2170 | ||
2171 | (dnci mulru "multiply unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) | |
2172 | "mulru $rn,$rm" | |
2173 | (+ MAJ_1 rn rm (f-sub4 7)) | |
2174 | (sequence ((DI result)) | |
2175 | (c-call "check_option_mul" pc) | |
2176 | (set result (mul (zext UDI rn) (zext UDI rm))) | |
2177 | (set hi (subword SI result 0)) | |
2178 | (set lo (subword SI result 1)) | |
2179 | (set rn (subword SI result 1))) | |
2180 | ((mep (unit u-use-gpr (in usereg rn)) | |
2181 | (unit u-use-gpr (in usereg rm)) | |
2182 | (unit u-exec) | |
2183 | (unit u-multiply) | |
2184 | (unit u-mul-gpr (out resultreg rn))))) | |
2185 | ||
2186 | (dnci madd "multiply accumulate" (OPTIONAL_MUL_INSN (STALL MUL)) | |
2187 | "madd $rn,$rm" | |
2188 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3004)) | |
2189 | (sequence ((DI result)) | |
2190 | (c-call "check_option_mul" pc) | |
2191 | (set result (or (sll (zext DI hi) 32) (zext DI lo))) | |
2192 | (set result (add result (mul (ext DI rn) (ext DI rm)))) | |
2193 | (set hi (subword SI result 0)) | |
2194 | (set lo (subword SI result 1))) | |
2195 | ((mep (unit u-use-gpr (in usereg rn)) | |
2196 | (unit u-use-gpr (in usereg rm)) | |
2197 | (unit u-exec) | |
2198 | (unit u-multiply)))) | |
2199 | ||
2200 | (dnci maddu "multiply accumulate unsigned" (OPTIONAL_MUL_INSN (STALL MUL)) | |
2201 | "maddu $rn,$rm" | |
2202 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3005)) | |
2203 | (sequence ((DI result)) | |
2204 | (c-call "check_option_mul" pc) | |
2205 | (set result (or (sll (zext DI hi) 32) (zext DI lo))) | |
2206 | (set result (add result (mul (zext UDI rn) (zext UDI rm)))) | |
2207 | (set hi (subword SI result 0)) | |
2208 | (set lo (subword SI result 1))) | |
2209 | ((mep (unit u-use-gpr (in usereg rn)) | |
2210 | (unit u-use-gpr (in usereg rm)) | |
2211 | (unit u-exec) | |
2212 | (unit u-multiply)))) | |
2213 | ||
2214 | ||
2215 | (dnci maddr "multiply accumulate, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) | |
2216 | "maddr $rn,$rm" | |
2217 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3006)) | |
2218 | (sequence ((DI result)) | |
2219 | (c-call "check_option_mul" pc) | |
2220 | (set result (or (sll (zext DI hi) 32) (zext DI lo))) | |
2221 | (set result (add result (mul (ext DI rn) (ext DI rm)))) | |
2222 | (set hi (subword SI result 0)) | |
2223 | (set lo (subword SI result 1)) | |
2224 | (set rn (subword SI result 1))) | |
2225 | ((mep (unit u-use-gpr (in usereg rn)) | |
2226 | (unit u-use-gpr (in usereg rm)) | |
2227 | (unit u-exec) | |
2228 | (unit u-multiply) | |
2229 | (unit u-mul-gpr (out resultreg rn))))) | |
2230 | ||
2231 | (dnci maddru "multiple accumulate unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) | |
2232 | "maddru $rn,$rm" | |
2233 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3007)) | |
2234 | (sequence ((DI result)) | |
2235 | (c-call "check_option_mul" pc) | |
2236 | (set result (or (sll (zext DI hi) 32) (zext DI lo))) | |
2237 | (set result (add result (mul (zext UDI rn) (zext UDI rm)))) | |
2238 | (set hi (subword SI result 0)) | |
2239 | (set lo (subword SI result 1)) | |
2240 | (set rn (subword SI result 1))) | |
2241 | ((mep (unit u-use-gpr (in usereg rn)) | |
2242 | (unit u-use-gpr (in usereg rm)) | |
2243 | (unit u-exec) | |
2244 | (unit u-multiply) | |
2245 | (unit u-mul-gpr (out resultreg rn))))) | |
2246 | ||
2247 | \f | |
2248 | ; Divide instructions. | |
2249 | ; These instructions become the RI when the 32-bit divide instruction | |
2250 | ; option is off. | |
2251 | ||
2252 | (dnci div "divide" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP) | |
2253 | "div $rn,$rm" | |
2254 | (+ MAJ_1 rn rm (f-sub4 8)) | |
2255 | (sequence () | |
2256 | (c-call "check_option_div" pc) | |
2257 | (if (eq rm 0) | |
2258 | (set pc (c-call USI "zdiv_exception" pc)) | |
2259 | ; Special case described on p. 76. | |
2260 | (if (and (eq rn #x80000000) | |
2261 | (eq rm #xffffffff)) | |
2262 | (sequence () | |
2263 | (set lo #x80000000) | |
2264 | (set hi 0)) | |
2265 | (sequence () | |
2266 | (set lo (div rn rm)) | |
2267 | (set hi (mod rn rm)))))) | |
2268 | ((mep (unit u-use-gpr (in usereg rn)) | |
2269 | (unit u-use-gpr (in usereg rm)) | |
2270 | (unit u-exec) | |
2271 | (unit u-divide) | |
2272 | (unit u-branch)))) | |
2273 | ||
2274 | (dnci divu "divide unsigned" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP) | |
2275 | "divu $rn,$rm" | |
2276 | (+ MAJ_1 rn rm (f-sub4 9)) | |
2277 | (sequence () | |
2278 | (c-call "check_option_div" pc) | |
2279 | (if (eq rm 0) | |
2280 | (set pc (c-call USI "zdiv_exception" pc)) | |
2281 | (sequence () | |
2282 | (set lo (udiv rn rm)) | |
2283 | (set hi (umod rn rm))))) | |
2284 | ((mep (unit u-use-gpr (in usereg rn)) | |
2285 | (unit u-use-gpr (in usereg rm)) | |
2286 | (unit u-exec) | |
2287 | (unit u-divide) | |
2288 | (unit u-branch)))) | |
2289 | ||
2290 | \f | |
2291 | ; Debug functions. | |
2292 | ; These instructions become the RI when the debug function option is | |
2293 | ; off. | |
2294 | ||
2295 | (dnci dret "return from debug exception" (OPTIONAL_DEBUG_INSN) | |
2296 | "dret" | |
2297 | (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 3)) | |
2298 | (sequence () | |
2299 | (c-call "check_option_debug" pc) | |
2300 | ; set DBG.DM. | |
2301 | (set dbg (and dbg (inv (sll SI 1 15)))) | |
2302 | (set pc depc)) | |
2303 | ((mep (unit u-exec) | |
2304 | (unit u-branch)))) | |
2305 | ||
2306 | (dnci dbreak "generate debug exception" (OPTIONAL_DEBUG_INSN MAY_TRAP VOLATILE) | |
2307 | "dbreak" | |
2308 | (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 3)) | |
2309 | (sequence () | |
2310 | (c-call "check_option_debug" pc) | |
2311 | ; set DBG.DPB. | |
2312 | (set dbg (or dbg 1))) | |
2313 | ()) | |
2314 | ||
2315 | \f | |
2316 | ; Leading zero instruction. | |
2317 | ||
2318 | (dnci ldz "leading zeroes" (OPTIONAL_LDZ_INSN (STALL INT2)) | |
2319 | "ldz $rn,$rm" | |
2320 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 0)) | |
2321 | (sequence () | |
2322 | (c-call "check_option_ldz" pc) | |
2323 | (set rn (c-call SI "do_ldz" rm))) | |
2324 | ((mep (unit u-use-gpr (in usereg rm)) | |
2325 | (unit u-exec)))) | |
2326 | ||
2327 | \f | |
2328 | ; Absolute difference instruction. | |
2329 | ||
2330 | (dnci abs "absolute difference" (OPTIONAL_ABS_INSN (STALL INT2)) | |
2331 | "abs $rn,$rm" | |
2332 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 3)) | |
2333 | (sequence () | |
2334 | (c-call "check_option_abs" pc) | |
2335 | (set rn (abs (sub rn rm)))) | |
2336 | ((mep (unit u-use-gpr (in usereg rm)) | |
2337 | (unit u-use-gpr (in usereg rn)) | |
2338 | (unit u-exec)))) | |
2339 | ||
2340 | \f | |
2341 | ; Average instruction. | |
2342 | ||
2343 | (dnci ave "average" (OPTIONAL_AVE_INSN (STALL INT2)) | |
2344 | "ave $rn,$rm" | |
2345 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 2)) | |
2346 | (sequence () | |
2347 | (c-call "check_option_ave" pc) | |
2348 | (set rn (sra (add (add rn rm) 1) 1))) | |
2349 | ((mep (unit u-use-gpr (in usereg rm)) | |
2350 | (unit u-use-gpr (in usereg rn)) | |
2351 | (unit u-exec)))) | |
2352 | ||
2353 | \f | |
2354 | ; MIN/MAX instructions. | |
2355 | ||
2356 | (dnci min "minimum" (OPTIONAL_MINMAX_INSN (STALL INT2)) | |
2357 | "min $rn,$rm" | |
2358 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 4)) | |
2359 | (sequence () | |
2360 | (c-call "check_option_minmax" pc) | |
2361 | (if (gt rn rm) | |
2362 | (set rn rm))) | |
2363 | ((mep (unit u-use-gpr (in usereg rm)) | |
2364 | (unit u-use-gpr (in usereg rn)) | |
2365 | (unit u-exec)))) | |
2366 | ||
2367 | (dnci max "maximum" (OPTIONAL_MINMAX_INSN (STALL INT2)) | |
2368 | "max $rn,$rm" | |
2369 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 5)) | |
2370 | (sequence () | |
2371 | (c-call "check_option_minmax" pc) | |
2372 | (if (lt rn rm) | |
2373 | (set rn rm))) | |
2374 | ((mep (unit u-use-gpr (in usereg rm)) | |
2375 | (unit u-use-gpr (in usereg rn)) | |
2376 | (unit u-exec)))) | |
2377 | ||
2378 | (dnci minu "minimum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2)) | |
2379 | "minu $rn,$rm" | |
2380 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 6)) | |
2381 | (sequence () | |
2382 | (c-call "check_option_minmax" pc) | |
2383 | (if (gtu rn rm) | |
2384 | (set rn rm))) | |
2385 | ((mep (unit u-use-gpr (in usereg rm)) | |
2386 | (unit u-use-gpr (in usereg rn)) | |
2387 | (unit u-exec)))) | |
2388 | ||
2389 | (dnci maxu "maximum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2)) | |
2390 | "maxu $rn,$rm" | |
2391 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 7)) | |
2392 | (sequence () | |
2393 | (c-call "check_option_minmax" pc) | |
2394 | (if (ltu rn rm) | |
2395 | (set rn rm))) | |
2396 | ((mep (unit u-use-gpr (in usereg rm)) | |
2397 | (unit u-use-gpr (in usereg rn)) | |
2398 | (unit u-exec)))) | |
2399 | ||
2400 | \f | |
2401 | ; Clipping instruction. | |
2402 | ||
2403 | (dnci clip "clip" (OPTIONAL_CLIP_INSN (STALL INT2)) | |
2404 | "clip $rn,$cimm5" | |
2405 | (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 0)) | |
2406 | (sequence ((SI min) (SI max)) | |
2407 | (c-call "check_option_clip" pc) | |
2408 | (set max (sub (sll 1 (sub cimm5 1)) 1)) | |
2409 | (set min (neg (sll 1 (sub cimm5 1)))) | |
2410 | (cond | |
2411 | ((eq cimm5 0) (set rn 0)) | |
2412 | ((gt rn max) (set rn max)) | |
2413 | ((lt rn min) (set rn min)))) | |
2414 | ((mep (unit u-use-gpr (in usereg rn)) | |
2415 | (unit u-exec)))) | |
2416 | ||
2417 | (dnci clipu "clip unsigned" (OPTIONAL_CLIP_INSN (STALL INT2)) | |
2418 | "clipu $rn,$cimm5" | |
2419 | (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 1)) | |
2420 | (sequence ((SI max)) | |
2421 | (c-call "check_option_clip" pc) | |
2422 | (set max (sub (sll 1 cimm5) 1)) | |
2423 | (cond | |
2424 | ((eq cimm5 0) (set rn 0)) | |
2425 | ((gt rn max) (set rn max)) | |
2426 | ((lt rn 0) (set rn 0)))) | |
2427 | ((mep (unit u-use-gpr (in usereg rn)) | |
2428 | (unit u-exec)))) | |
2429 | ||
2430 | \f | |
2431 | ; Saturation instructions. | |
2432 | ||
2433 | (dnci sadd "saturating addition" (OPTIONAL_SAT_INSN (STALL INT2)) | |
2434 | "sadd $rn,$rm" | |
2435 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 8)) | |
2436 | (sequence () | |
2437 | (c-call "check_option_sat" pc) | |
2438 | (if (add-oflag rn rm 0) | |
2439 | (if (nflag rn) | |
2440 | ; underflow | |
2441 | (set rn (neg (sll 1 31))) | |
2442 | ; overflow | |
2443 | (set rn (sub (sll 1 31) 1))) | |
2444 | (set rn (add rn rm)))) | |
2445 | ((mep (unit u-use-gpr (in usereg rm)) | |
2446 | (unit u-use-gpr (in usereg rn)) | |
2447 | (unit u-exec)))) | |
2448 | ||
2449 | (dnci ssub "saturating subtraction" (OPTIONAL_SAT_INSN (STALL INT2)) | |
2450 | "ssub $rn,$rm" | |
2451 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 10)) | |
2452 | (sequence () | |
2453 | (c-call "check_option_sat" pc) | |
2454 | (if (sub-oflag rn rm 0) | |
2455 | (if (nflag rn) | |
2456 | ; underflow | |
2457 | (set rn (neg (sll 1 31))) | |
2458 | ; overflow | |
2459 | (set rn (sub (sll 1 31) 1))) | |
2460 | (set rn (sub rn rm)))) | |
2461 | ((mep (unit u-use-gpr (in usereg rm)) | |
2462 | (unit u-use-gpr (in usereg rn)) | |
2463 | (unit u-exec)))) | |
2464 | ||
2465 | (dnci saddu "saturating unsigned addition" (OPTIONAL_SAT_INSN (STALL INT2)) | |
2466 | "saddu $rn,$rm" | |
2467 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 9)) | |
2468 | (sequence () | |
2469 | (c-call "check_option_sat" pc) | |
2470 | (if (add-cflag rn rm 0) | |
2471 | (set rn (inv 0)) | |
2472 | (set rn (add rn rm)))) | |
2473 | ((mep (unit u-use-gpr (in usereg rm)) | |
2474 | (unit u-use-gpr (in usereg rn)) | |
2475 | (unit u-exec)))) | |
2476 | ||
2477 | (dnci ssubu "saturating unsigned subtraction" (OPTIONAL_SAT_INSN (STALL INT2)) | |
2478 | "ssubu $rn,$rm" | |
2479 | (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 11)) | |
2480 | (sequence () | |
2481 | (c-call "check_option_sat" pc) | |
2482 | (if (sub-cflag rn rm 0) | |
2483 | (set rn 0) | |
2484 | (set rn (sub rn rm)))) | |
2485 | ((mep (unit u-use-gpr (in usereg rm)) | |
2486 | (unit u-use-gpr (in usereg rn)) | |
2487 | (unit u-exec)))) | |
2488 | ||
2489 | \f | |
2490 | ; UCI and DSP options are defined in an external file. | |
2491 | ; See `mep-sample-ucidsp.cpu' for a sample. | |
2492 | ||
2493 | \f | |
2494 | ; Coprocessor instructions. | |
2495 | ||
2496 | (dnci swcp "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) | |
2497 | "swcp $crn,($rma)" | |
2498 | (+ MAJ_3 crn rma (f-sub4 8)) | |
2499 | (sequence () | |
2500 | (c-call "check_option_cp" pc) | |
2501 | (c-call VOID "check_write_to_text" (and rma (inv SI 3))) | |
2502 | (set (mem SI (and rma (inv SI 3))) crn)) | |
2503 | ((mep (unit u-use-gpr (in usereg rma)) | |
2504 | (unit u-exec)))) | |
2505 | ||
2506 | (dnci lwcp "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) | |
2507 | "lwcp $crn,($rma)" | |
2508 | (+ MAJ_3 crn rma (f-sub4 9)) | |
2509 | (sequence () | |
2510 | (c-call "check_option_cp" pc) | |
2511 | (set crn (mem SI (and rma (inv SI 3))))) | |
2512 | ((mep (unit u-use-gpr (in usereg rma)) | |
2513 | (unit u-exec)))) | |
2514 | ||
2515 | (dnci smcp "smcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) | |
2516 | "smcp $crn64,($rma)" | |
2517 | (+ MAJ_3 crn64 rma (f-sub4 10)) | |
2518 | (sequence () | |
2519 | (c-call "check_option_cp" pc) | |
2520 | (c-call "check_option_cp64" pc) | |
2521 | (c-call VOID "check_write_to_text" rma) | |
2522 | (c-call "do_smcp" rma crn64 pc)) | |
2523 | ((mep (unit u-use-gpr (in usereg rma)) | |
2524 | (unit u-exec)))) | |
2525 | ||
2526 | (dnci lmcp "lmcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) | |
2527 | "lmcp $crn64,($rma)" | |
2528 | (+ MAJ_3 crn64 rma (f-sub4 11)) | |
2529 | (sequence () | |
2530 | (c-call "check_option_cp" pc) | |
2531 | (c-call "check_option_cp64" pc) | |
2532 | (set crn64 (c-call DI "do_lmcp" rma pc))) | |
2533 | ((mep (unit u-use-gpr (in usereg rma)) | |
2534 | (unit u-exec)))) | |
2535 | ||
2536 | (dnci swcpi "swcp (post-increment)" (OPTIONAL_CP_INSN (STALL STORE)) | |
2537 | "swcpi $crn,($rma+)" | |
2538 | (+ MAJ_3 crn rma (f-sub4 0)) | |
2539 | (sequence () | |
2540 | (c-call "check_option_cp" pc) | |
2541 | (c-call VOID "check_write_to_text" (and rma (inv SI 3))) | |
2542 | (set (mem SI (and rma (inv SI 3))) crn) | |
2543 | (set rma (add rma 4))) | |
2544 | ((mep (unit u-use-gpr (in usereg rma)) | |
2545 | (unit u-exec)))) | |
2546 | ||
2547 | (dnci lwcpi "lwcp (post-increment)" (OPTIONAL_CP_INSN (STALL LOAD)) | |
2548 | "lwcpi $crn,($rma+)" | |
2549 | (+ MAJ_3 crn rma (f-sub4 1)) | |
2550 | (sequence () | |
2551 | (c-call "check_option_cp" pc) | |
2552 | (set crn (mem SI (and rma (inv SI 3)))) | |
2553 | (set rma (add rma 4))) | |
2554 | ((mep (unit u-use-gpr (in usereg rma)) | |
2555 | (unit u-exec)))) | |
2556 | ||
2557 | (dnci smcpi "smcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) | |
2558 | "smcpi $crn64,($rma+)" | |
2559 | (+ MAJ_3 crn64 rma (f-sub4 2)) | |
2560 | (sequence () | |
2561 | (c-call "check_option_cp" pc) | |
2562 | (c-call "check_option_cp64" pc) | |
2563 | (c-call VOID "check_write_to_text" rma) | |
2564 | (c-call "do_smcpi" (index-of rma) crn64 pc) | |
2565 | (set rma rma)) ; reference as output for intrinsic generation | |
2566 | ((mep (unit u-use-gpr (in usereg rma)) | |
2567 | (unit u-exec)))) | |
2568 | ||
2569 | (dnci lmcpi "lmcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) | |
2570 | "lmcpi $crn64,($rma+)" | |
2571 | (+ MAJ_3 crn64 rma (f-sub4 3)) | |
2572 | (sequence () | |
2573 | (c-call "check_option_cp" pc) | |
2574 | (c-call "check_option_cp64" pc) | |
2575 | (set crn64 (c-call DI "do_lmcpi" (index-of rma) pc)) | |
2576 | (set rma rma)) ; reference as output for intrinsic generation | |
2577 | ((mep (unit u-use-gpr (in usereg rma)) | |
2578 | (unit u-exec)))) | |
2579 | ||
2580 | (dnci swcp16 "swcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL STORE)) | |
2581 | "swcp $crn,$sdisp16($rma)" | |
2582 | (+ MAJ_15 crn rma (f-sub4 12) sdisp16) | |
2583 | (sequence () | |
2584 | (c-call "check_option_cp" pc) | |
2585 | (set (mem SI (and (add rma sdisp16) (inv SI 3))) crn)) | |
2586 | ((mep (unit u-use-gpr (in usereg rma)) | |
2587 | (unit u-exec)))) | |
2588 | ||
2589 | (dnci lwcp16 "lwcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL LOAD)) | |
2590 | "lwcp $crn,$sdisp16($rma)" | |
2591 | (+ MAJ_15 crn rma (f-sub4 13) sdisp16) | |
2592 | (sequence () | |
2593 | (c-call "check_option_cp" pc) | |
2594 | (set crn (mem SI (and (add rma sdisp16) (inv SI 3))))) | |
2595 | ((mep (unit u-use-gpr (in usereg rma)) | |
2596 | (unit u-exec)))) | |
2597 | ||
2598 | (dnci smcp16 "smcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) | |
2599 | "smcp $crn64,$sdisp16($rma)" | |
2600 | (+ MAJ_15 crn64 rma (f-sub4 14) sdisp16) | |
2601 | (sequence () | |
2602 | (c-call "check_option_cp" pc) | |
2603 | (c-call "check_option_cp64" pc) | |
2604 | (c-call "do_smcp16" rma sdisp16 crn64 pc)) | |
2605 | ((mep (unit u-use-gpr (in usereg rma)) | |
2606 | (unit u-exec)))) | |
2607 | ||
2608 | (dnci lmcp16 "lmcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) | |
2609 | "lmcp $crn64,$sdisp16($rma)" | |
2610 | (+ MAJ_15 crn64 rma (f-sub4 15) sdisp16) | |
2611 | (sequence () | |
2612 | (c-call "check_option_cp" pc) | |
2613 | (c-call "check_option_cp64" pc) | |
2614 | (set crn64 (c-call DI "do_lmcp16" rma sdisp16 pc))) | |
2615 | ((mep (unit u-use-gpr (in usereg rma)) | |
2616 | (unit u-exec)))) | |
2617 | ||
2618 | (dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) | |
2619 | "sbcpa $crn,($rma+),$cdisp10" | |
2620 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 0) (f-ext62 0) cdisp10) | |
2621 | (sequence () | |
2622 | (c-call "check_option_cp" pc) | |
2623 | (c-call VOID "check_write_to_text" rma) | |
2624 | (set (mem QI rma) (and crn #xff)) | |
2625 | (set rma (add rma (ext SI cdisp10)))) | |
2626 | ((mep (unit u-use-gpr (in usereg rma)) | |
2627 | (unit u-exec)))) | |
2628 | ||
2629 | (dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) | |
2630 | "lbcpa $crn,($rma+),$cdisp10" | |
2631 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x0) cdisp10) | |
2632 | (sequence () | |
2633 | (c-call "check_option_cp" pc) | |
2634 | (set crn (ext SI (mem QI rma))) | |
2635 | (set rma (add rma (ext SI cdisp10)))) | |
2636 | ((mep (unit u-use-gpr (in usereg rma)) | |
2637 | (unit u-exec)))) | |
2638 | ||
2639 | (dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) | |
2640 | "shcpa $crn,($rma+),$cdisp10a2" | |
2641 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x0) cdisp10a2) | |
2642 | (sequence () | |
2643 | (c-call "check_option_cp" pc) | |
2644 | (c-call VOID "check_write_to_text" (and rma (inv SI 1))) | |
2645 | (set (mem HI (and rma (inv SI 1))) (and crn #xffff)) | |
2646 | (set rma (add rma (ext SI cdisp10a2)))) | |
2647 | ((mep (unit u-use-gpr (in usereg rma)) | |
2648 | (unit u-exec)))) | |
2649 | ||
2650 | (dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) | |
2651 | "lhcpa $crn,($rma+),$cdisp10a2" | |
2652 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x0) cdisp10a2) | |
2653 | (sequence () | |
2654 | (c-call "check_option_cp" pc) | |
2655 | (set crn (ext SI (mem HI (and rma (inv SI 1))))) | |
2656 | (set rma (add rma (ext SI cdisp10a2)))) | |
2657 | ((mep (unit u-use-gpr (in usereg rma)) | |
2658 | (unit u-exec)))) | |
2659 | ||
2660 | (dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) | |
2661 | "swcpa $crn,($rma+),$cdisp10a4" | |
2662 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x0) cdisp10a4) | |
2663 | (sequence () | |
2664 | (c-call "check_option_cp" pc) | |
2665 | (c-call VOID "check_write_to_text" (and rma (inv SI 3))) | |
2666 | (set (mem SI (and rma (inv SI 3))) crn) | |
2667 | (set rma (add rma (ext SI cdisp10a4)))) | |
2668 | ((mep (unit u-use-gpr (in usereg rma)) | |
2669 | (unit u-exec)))) | |
2670 | ||
2671 | (dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) | |
2672 | "lwcpa $crn,($rma+),$cdisp10a4" | |
2673 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x0) cdisp10a4) | |
2674 | (sequence () | |
2675 | (c-call "check_option_cp" pc) | |
2676 | (set crn (mem SI (and rma (inv SI 3)))) | |
2677 | (set rma (add rma (ext SI cdisp10a4)))) | |
2678 | ((mep (unit u-use-gpr (in usereg rma)) | |
2679 | (unit u-exec)))) | |
2680 | ||
2681 | (dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) | |
2682 | "smcpa $crn64,($rma+),$cdisp10a8" | |
2683 | (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x0) cdisp10a8) | |
2684 | (sequence () | |
2685 | (c-call "check_option_cp" pc) | |
2686 | (c-call "check_option_cp64" pc) | |
2687 | (c-call VOID "check_write_to_text" rma) | |
2688 | (c-call "do_smcpa" (index-of rma) cdisp10a8 crn64 pc) | |
2689 | (set rma rma)) ; reference as output for intrinsic generation | |
2690 | ((mep (unit u-use-gpr (in usereg rma)) | |
2691 | (unit u-exec)))) | |
2692 | ||
2693 | (dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) | |
2694 | "lmcpa $crn64,($rma+),$cdisp10a8" | |
2695 | (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x0) cdisp10a8) | |
2696 | (sequence () | |
2697 | (c-call "check_option_cp" pc) | |
2698 | (c-call "check_option_cp64" pc) | |
2699 | (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp10a8 pc)) | |
2700 | (set rma rma)) ; reference as output for intrinsic generation | |
2701 | ((mep (unit u-use-gpr (in usereg rma)) | |
2702 | (unit u-exec)))) | |
2703 | ||
2704 | \f | |
2705 | (dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN) | |
2706 | "sbcpm0 $crn,($rma+),$cdisp10" | |
2707 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10) | |
2708 | (sequence () | |
2709 | (c-call "check_option_cp" pc) | |
2710 | (c-call VOID "check_write_to_text" rma) | |
2711 | (set (mem QI rma) (and crn #xff)) | |
2712 | (set rma (mod0 cdisp10))) | |
2713 | ((mep (unit u-use-gpr (in usereg rma)) | |
2714 | (unit u-exec)))) | |
2715 | ||
2716 | (dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN) | |
2717 | "lbcpm0 $crn,($rma+),$cdisp10" | |
2718 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x2) cdisp10) | |
2719 | (sequence () | |
2720 | (c-call "check_option_cp" pc) | |
2721 | (set crn (ext SI (mem QI rma))) | |
2722 | (set rma (mod0 cdisp10))) | |
2723 | ((mep (unit u-use-gpr (in usereg rma)) | |
2724 | (unit u-exec)))) | |
2725 | ||
2726 | (dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN) | |
2727 | "shcpm0 $crn,($rma+),$cdisp10a2" | |
2728 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x2) cdisp10a2) | |
2729 | (sequence () | |
2730 | (c-call "check_option_cp" pc) | |
2731 | (c-call VOID "check_write_to_text" (and rma (inv SI 1))) | |
2732 | (set (mem HI (and rma (inv SI 1))) (and crn #xffff)) | |
2733 | (set rma (mod0 cdisp10a2))) | |
2734 | ((mep (unit u-use-gpr (in usereg rma)) | |
2735 | (unit u-exec)))) | |
2736 | ||
2737 | (dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN) | |
2738 | "lhcpm0 $crn,($rma+),$cdisp10a2" | |
2739 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x2) cdisp10a2) | |
2740 | (sequence () | |
2741 | (c-call "check_option_cp" pc) | |
2742 | (set crn (ext SI (mem HI (and rma (inv SI 1))))) | |
2743 | (set rma (mod0 cdisp10a2))) | |
2744 | ((mep (unit u-use-gpr (in usereg rma)) | |
2745 | (unit u-exec)))) | |
2746 | ||
2747 | (dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN) | |
2748 | "swcpm0 $crn,($rma+),$cdisp10a4" | |
2749 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x2) cdisp10a4) | |
2750 | (sequence () | |
2751 | (c-call "check_option_cp" pc) | |
2752 | (c-call VOID "check_write_to_text" (and rma (inv SI 3))) | |
2753 | (set (mem SI (and rma (inv SI 3))) crn) | |
2754 | (set rma (mod0 cdisp10a4))) | |
2755 | ((mep (unit u-use-gpr (in usereg rma)) | |
2756 | (unit u-exec)))) | |
2757 | ||
2758 | (dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN) | |
2759 | "lwcpm0 $crn,($rma+),$cdisp10a4" | |
2760 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x2) cdisp10a4) | |
2761 | (sequence () | |
2762 | (c-call "check_option_cp" pc) | |
2763 | (set crn (mem SI (and rma (inv SI 3)))) | |
2764 | (set rma (mod0 cdisp10a4))) | |
2765 | ((mep (unit u-use-gpr (in usereg rma)) | |
2766 | (unit u-exec)))) | |
2767 | ||
2768 | (dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) | |
2769 | "smcpm0 $crn64,($rma+),$cdisp10a8" | |
2770 | (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x2) cdisp10a8) | |
2771 | (sequence () | |
2772 | (c-call "check_option_cp" pc) | |
2773 | (c-call "check_option_cp64" pc) | |
2774 | (c-call VOID "check_write_to_text" rma) | |
2775 | (c-call "do_smcp" rma crn64 pc) | |
2776 | (set rma (mod0 cdisp10a8))) | |
2777 | ((mep (unit u-use-gpr (in usereg rma)) | |
2778 | (unit u-exec)))) | |
2779 | ||
2780 | (dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) | |
2781 | "lmcpm0 $crn64,($rma+),$cdisp10a8" | |
2782 | (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x2) cdisp10a8) | |
2783 | (sequence () | |
2784 | (c-call "check_option_cp" pc) | |
2785 | (c-call "check_option_cp64" pc) | |
2786 | (set crn64 (c-call DI "do_lmcp" rma pc)) | |
2787 | (set rma (mod0 cdisp10a8))) | |
2788 | ((mep (unit u-use-gpr (in usereg rma)) | |
2789 | (unit u-exec)))) | |
2790 | ||
2791 | (dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN) | |
2792 | "sbcpm1 $crn,($rma+),$cdisp10" | |
2793 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x3) cdisp10) | |
2794 | (sequence () | |
2795 | (c-call "check_option_cp" pc) | |
2796 | (c-call VOID "check_write_to_text" rma) | |
2797 | (set (mem QI rma) (and crn #xff)) | |
2798 | (set rma (mod1 cdisp10))) | |
2799 | ((mep (unit u-use-gpr (in usereg rma)) | |
2800 | (unit u-exec)))) | |
2801 | ||
2802 | (dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN) | |
2803 | "lbcpm1 $crn,($rma+),$cdisp10" | |
2804 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x3) cdisp10) | |
2805 | (sequence () | |
2806 | (c-call "check_option_cp" pc) | |
2807 | (set crn (ext SI (mem QI rma))) | |
2808 | (set rma (mod1 cdisp10))) | |
2809 | ((mep (unit u-use-gpr (in usereg rma)) | |
2810 | (unit u-exec)))) | |
2811 | ||
2812 | (dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN) | |
2813 | "shcpm1 $crn,($rma+),$cdisp10a2" | |
2814 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x3) cdisp10a2) | |
2815 | (sequence () | |
2816 | (c-call "check_option_cp" pc) | |
2817 | (c-call VOID "check_write_to_text" (and rma (inv SI 1))) | |
2818 | (set (mem HI (and rma (inv SI 1))) (and crn #xffff)) | |
2819 | (set rma (mod1 cdisp10a2))) | |
2820 | ((mep (unit u-use-gpr (in usereg rma)) | |
2821 | (unit u-exec)))) | |
2822 | ||
2823 | (dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN) | |
2824 | "lhcpm1 $crn,($rma+),$cdisp10a2" | |
2825 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x3) cdisp10a2) | |
2826 | (sequence () | |
2827 | (c-call "check_option_cp" pc) | |
2828 | (set crn (ext SI (mem HI (and rma (inv SI 1))))) | |
2829 | (set rma (mod1 cdisp10a2))) | |
2830 | ((mep (unit u-use-gpr (in usereg rma)) | |
2831 | (unit u-exec)))) | |
2832 | ||
2833 | (dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN) | |
2834 | "swcpm1 $crn,($rma+),$cdisp10a4" | |
2835 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x3) cdisp10a4) | |
2836 | (sequence () | |
2837 | (c-call "check_option_cp" pc) | |
2838 | (c-call VOID "check_write_to_text" (and rma (inv SI 3))) | |
2839 | (set (mem SI (and rma (inv SI 3))) crn) | |
2840 | (set rma (mod1 cdisp10a4))) | |
2841 | ((mep (unit u-use-gpr (in usereg rma)) | |
2842 | (unit u-exec)))) | |
2843 | ||
2844 | (dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN) | |
2845 | "lwcpm1 $crn,($rma+),$cdisp10a4" | |
2846 | (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x3) cdisp10a4) | |
2847 | (sequence () | |
2848 | (c-call "check_option_cp" pc) | |
2849 | (set crn (ext SI (mem SI (and rma (inv SI 3))))) | |
2850 | (set rma (mod1 cdisp10a4))) | |
2851 | ((mep (unit u-use-gpr (in usereg rma)) | |
2852 | (unit u-exec)))) | |
2853 | ||
2854 | (dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) | |
2855 | "smcpm1 $crn64,($rma+),$cdisp10a8" | |
2856 | (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x3) cdisp10a8) | |
2857 | (sequence () | |
2858 | (c-call "check_option_cp" pc) | |
2859 | (c-call "check_option_cp64" pc) | |
2860 | (c-call "do_smcp" rma crn64 pc) | |
2861 | (c-call VOID "check_write_to_text" rma) | |
2862 | (set rma (mod1 cdisp10a8))) | |
2863 | ((mep (unit u-use-gpr (in usereg rma)) | |
2864 | (unit u-exec)))) | |
2865 | ||
2866 | (dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) | |
2867 | "lmcpm1 $crn64,($rma+),$cdisp10a8" | |
2868 | (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x3) cdisp10a8) | |
2869 | (sequence () | |
2870 | (c-call "check_option_cp" pc) | |
2871 | (c-call "check_option_cp64" pc) | |
2872 | (set crn64 (c-call DI "do_lmcp" rma pc)) | |
2873 | (set rma (mod1 cdisp10a8))) | |
2874 | ((mep (unit u-use-gpr (in usereg rma)) | |
2875 | (unit u-exec)))) | |
2876 | ||
2877 | (dnop cp_flag "branch condition register" (all-mep-isas) h-ccr 1) | |
2878 | ||
2879 | (dnci bcpeq "branch coprocessor equal" (OPTIONAL_CP_INSN RELAXABLE) | |
2880 | "bcpeq $cccc,$pcrel17a2" | |
2881 | (+ MAJ_13 (f-rn 8) cccc (f-sub4 4) pcrel17a2) | |
2882 | (sequence () | |
2883 | (c-call "check_option_cp" pc) | |
2884 | (if (eq (xor cccc cp_flag) 0) | |
2885 | (set-vliw-alignment-modified pc pcrel17a2))) | |
2886 | ()) | |
2887 | ||
2888 | (dnci bcpne "branch coprocessor not equal" (OPTIONAL_CP_INSN RELAXABLE) | |
2889 | "bcpne $cccc,$pcrel17a2" | |
2890 | (+ MAJ_13 (f-rn 8) cccc (f-sub4 5) pcrel17a2) | |
2891 | (sequence () | |
2892 | (c-call "check_option_cp" pc) | |
2893 | (if (ne (xor cccc cp_flag) 0) | |
2894 | (set-vliw-alignment-modified pc pcrel17a2))) | |
2895 | ()) | |
2896 | ||
2897 | (dnci bcpat "branch coprocessor and true" (OPTIONAL_CP_INSN RELAXABLE) | |
2898 | "bcpat $cccc,$pcrel17a2" | |
2899 | (+ MAJ_13 (f-rn 8) cccc (f-sub4 6) pcrel17a2) | |
2900 | (sequence () | |
2901 | (c-call "check_option_cp" pc) | |
2902 | (if (ne (and cccc cp_flag) 0) | |
2903 | (set-vliw-alignment-modified pc pcrel17a2))) | |
2904 | ()) | |
2905 | ||
2906 | (dnci bcpaf "branch coprocessor and false" (OPTIONAL_CP_INSN RELAXABLE) | |
2907 | "bcpaf $cccc,$pcrel17a2" | |
2908 | (+ MAJ_13 (f-rn 8) cccc (f-sub4 7) pcrel17a2) | |
2909 | (sequence () | |
2910 | (c-call "check_option_cp" pc) | |
2911 | (if (eq (and cccc cp_flag) 0) | |
2912 | (set-vliw-alignment-modified pc pcrel17a2))) | |
2913 | ()) | |
2914 | ||
2915 | (dnci synccp "synchronise with coprocessor" (OPTIONAL_CP_INSN) | |
2916 | "synccp" | |
2917 | (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 1)) | |
2918 | (sequence () | |
2919 | (c-call "check_option_cp" pc) | |
2920 | (unimp "synccp")) | |
2921 | ()) | |
2922 | ||
2923 | (dnci jsrv "jump to vliw subroutine " (OPTIONAL_CP_INSN) | |
2924 | "jsrv $rm" | |
2925 | (+ MAJ_1 (f-rn 8) rm (f-sub4 15)) | |
2926 | (sequence () | |
2927 | (cg-profile pc rm) | |
2928 | (c-call "check_option_cp" pc) | |
2929 | (core-vliw-switch | |
2930 | ||
2931 | ;; in core operating mode | |
2932 | (sequence () | |
2933 | (set lp (or (add pc 2) 1)) | |
2934 | (set-vliw-aliignment-modified-by-option pc rm) | |
2935 | (set-psw.om 1)) ;; to VLIW operation mode | |
2936 | ||
2937 | ;; in VLIW32 operating mode | |
2938 | (sequence () | |
2939 | (set lp (or (add pc 4) 1)) | |
2940 | (set pc (and rm (inv 1))) | |
2941 | (set-psw.om 0)) ;; to core operation mode | |
2942 | ||
2943 | ;; in VLIW64 operating mode | |
2944 | (sequence () | |
2945 | (set lp (or (add pc 8) 1)) | |
2946 | (set pc (and rm (inv 1))) | |
2947 | (set-psw.om 0)))) ;; to core operation mode | |
2948 | ((mep (unit u-use-gpr (in usereg rm)) | |
2949 | (unit u-exec) | |
2950 | (unit u-branch)))) | |
2951 | ||
2952 | (dnci bsrv "branch to vliw subroutine" (OPTIONAL_CP_INSN) | |
2953 | "bsrv $pcrel24a2" | |
2954 | (+ MAJ_13 (f-4 1) (f-sub4 11) pcrel24a2) | |
2955 | (sequence () | |
2956 | (cg-profile pc pcrel24a2) | |
2957 | (c-call "check_option_cp" pc) | |
2958 | (core-vliw-switch | |
2959 | ||
2960 | ;; in core operating mode | |
2961 | (sequence () | |
2962 | (set lp (or (add pc 4) 1)) | |
2963 | (set-vliw-aliignment-modified-by-option pc pcrel24a2) | |
2964 | (set-psw.om 1)) ;; to VLIW operation mode | |
2965 | ||
2966 | ;; in VLIW32 operating mode | |
2967 | (sequence () | |
2968 | (set lp (or (add pc 4) 1)) | |
2969 | (set pc (and pcrel24a2 (inv 1))) | |
2970 | (set-psw.om 0)) ;; to core operation mode | |
2971 | ||
2972 | ;; in VLIW64 operating mode | |
2973 | (sequence () | |
2974 | (set lp (or (add pc 8) 1)) | |
2975 | (set pc (and pcrel24a2 (inv 1))) | |
2976 | (set-psw.om 0)))) ;; to core operation mode | |
2977 | ((mep (unit u-exec) | |
2978 | (unit u-branch)))) | |
2979 | ||
2980 | \f | |
2981 | ; An instruction for test instrumentation. | |
2982 | ; Using a reserved opcode. | |
2983 | ||
2984 | (dnci sim-syscall "simulator system call" () | |
2985 | "--syscall--" | |
2986 | (+ MAJ_7 (f-4 1) callnum (f-8 0) (f-9 0) (f-10 0) (f-sub4 0)) | |
2987 | (c-call "do_syscall" pc callnum) | |
2988 | ()) | |
2989 | ||
2990 | (define-pmacro (dnri n major minor) | |
2991 | (dnci (.sym ri- n) "reserved instruction" () | |
2992 | "--reserved--" | |
2993 | (+ major rn rm (f-sub4 minor)) | |
2994 | (set pc (c-call USI "ri_exception" pc)) | |
2995 | ((mep (unit u-exec) | |
2996 | (unit u-branch))))) | |
2997 | ||
2998 | (dnri 0 MAJ_0 6) | |
2999 | (dnri 1 MAJ_1 10) | |
3000 | (dnri 2 MAJ_1 11) | |
3001 | (dnri 3 MAJ_2 5) | |
3002 | (dnri 4 MAJ_2 8) | |
3003 | (dnri 5 MAJ_2 9) | |
3004 | (dnri 6 MAJ_2 10) | |
3005 | (dnri 7 MAJ_2 11) | |
3006 | (dnri 8 MAJ_3 4) | |
3007 | (dnri 9 MAJ_3 5) | |
3008 | (dnri 10 MAJ_3 6) | |
3009 | (dnri 11 MAJ_3 7) | |
3010 | (dnri 12 MAJ_3 12) | |
3011 | (dnri 13 MAJ_3 13) | |
3012 | (dnri 14 MAJ_3 14) | |
3013 | (dnri 15 MAJ_3 15) | |
3014 | (dnri 17 MAJ_7 7) | |
3015 | (dnri 20 MAJ_7 14) | |
3016 | (dnri 21 MAJ_7 15) | |
3017 | (dnri 22 MAJ_12 7) | |
3018 | (dnri 23 MAJ_14 13) | |
3019 | ;(dnri 24 MAJ_15 3) | |
3020 | (dnri 26 MAJ_15 8) | |
3021 | ; begin core-specific reserved insns | |
3022 | ; end core-specific reserved insns | |
3023 | ||
3024 | \f | |
3025 | ; Macro instructions. | |
3026 | ||
3027 | (dnmi nop "nop" | |
3028 | () | |
3029 | "nop" | |
3030 | (emit mov (rn 0) (rm 0))) | |
3031 | ||
3032 | ; Emit the 16 bit form of these 32 bit insns when the displacement is zero. | |
3033 | ; | |
3034 | (dncmi sb16-0 "store byte (explicit 16 bit displacement of zero)" (NO-DIS) | |
3035 | "sb $rnc,$zero($rma)" | |
3036 | (emit sb rnc rma)) | |
3037 | ||
3038 | (dncmi sh16-0 "store half (explicit 16 bit displacement of zero)" (NO-DIS) | |
3039 | "sh $rns,$zero($rma)" | |
3040 | (emit sh rns rma)) | |
3041 | ||
3042 | (dncmi sw16-0 "store word (explicit 16 bit displacement of zero)" (NO-DIS) | |
3043 | "sw $rnl,$zero($rma)" | |
3044 | (emit sw rnl rma)) | |
3045 | ||
3046 | (dncmi lb16-0 "load byte (explicit 16 bit displacement of zero)" (NO-DIS) | |
3047 | "lb $rnc,$zero($rma)" | |
3048 | (emit lb rnc rma)) | |
3049 | ||
3050 | (dncmi lh16-0 "load half (explicit 16 bit displacement of zero)" (NO-DIS) | |
3051 | "lh $rns,$zero($rma)" | |
3052 | (emit lh rns rma)) | |
3053 | ||
3054 | (dncmi lw16-0 "load word (explicit 16 bit displacement of zero)" (NO-DIS) | |
3055 | "lw $rnl,$zero($rma)" | |
3056 | (emit lw rnl rma)) | |
3057 | ||
3058 | (dncmi lbu16-0 "load unsigned byte (explicit 16 bit displacement of zero)" (NO-DIS) | |
3059 | "lbu $rnuc,$zero($rma)" | |
3060 | (emit lbu rnuc rma)) | |
3061 | ||
3062 | (dncmi lhu16-0 "load unsigned half (explicit 16 bit displacement of zero)" (NO-DIS) | |
3063 | "lhu $rnus,$zero($rma)" | |
3064 | (emit lhu rnus rma)) | |
3065 | ||
3066 | (dncmi swcp16-0 "swcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS) | |
3067 | "swcp $crn,$zero($rma)" | |
3068 | (emit swcp crn rma)) | |
3069 | ||
3070 | (dncmi lwcp16-0 "lwcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS) | |
3071 | "lwcp $crn,$zero($rma)" | |
3072 | (emit lwcp crn rma)) | |
3073 | ||
3074 | (dncmi smcp16-0 "smcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS) | |
3075 | "smcp $crn64,$zero($rma)" | |
3076 | (emit smcp crn64 rma)) | |
3077 | ||
3078 | (dncmi lmcp16-0 "lmcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS) | |
3079 | "lmcp $crn64,$zero($rma)" | |
3080 | (emit lmcp crn64 rma)) |