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3d339ad2 | 1 | /* Definitions of target machine for GNU compiler. Sun 68000/68020 version. |
d8fa884b | 2 | Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc. |
25a1b918 | 3 | |
3d339ad2 RS |
4 | This file is part of GNU CC. |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
0e29e3c9 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
3d339ad2 RS |
20 | |
21 | ||
22 | /* Note that some other tm.h files include this one and then override | |
23 | many of the definitions that relate to assembler syntax. */ | |
24 | ||
25 | ||
26 | /* Names to predefine in the preprocessor for this target machine. */ | |
27 | ||
28 | /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */ | |
29 | ||
30 | /* Print subsidiary information on the compiler version in use. */ | |
31 | #ifdef MOTOROLA | |
32 | #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)"); | |
33 | #else | |
34 | #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)"); | |
35 | #endif | |
36 | ||
37 | /* Define SUPPORT_SUN_FPA to include support for generating code for | |
38 | the Sun Floating Point Accelerator, an optional product for Sun 3 | |
39 | machines. By default, it is not defined. Avoid defining it unless | |
40 | you need to output code for the Sun3+FPA architecture, as it has the | |
41 | effect of slowing down the register set operations in hard-reg-set.h | |
42 | (total number of registers will exceed number of bits in a long, | |
43 | if defined, causing the set operations to expand to loops). | |
44 | SUPPORT_SUN_FPA is typically defined in sun3.h. */ | |
45 | ||
46 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
47 | ||
48 | extern int target_flags; | |
49 | ||
50 | /* Macros used in the machine description to test the flags. */ | |
51 | ||
52 | /* Compile for a 68020 (not a 68000 or 68010). */ | |
7a1b98a9 RK |
53 | #define MASK_68020 1 |
54 | #define TARGET_68020 (target_flags & MASK_68020) | |
3d339ad2 RS |
55 | |
56 | /* Compile 68881 insns for floating point (not library calls). */ | |
7a1b98a9 RK |
57 | #define MASK_68881 2 |
58 | #define TARGET_68881 (target_flags & MASK_68881) | |
3d339ad2 RS |
59 | |
60 | /* Compile using 68020 bitfield insns. */ | |
7a1b98a9 RK |
61 | #define MASK_BITFIELD 4 |
62 | #define TARGET_BITFIELD (target_flags & MASK_BITFIELD) | |
3d339ad2 RS |
63 | |
64 | /* Compile using rtd insn calling sequence. | |
65 | This will not work unless you use prototypes at least | |
66 | for all functions that can take varying numbers of args. */ | |
7a1b98a9 RK |
67 | #define MASK_RTD 8 |
68 | #define TARGET_RTD (target_flags & MASK_RTD) | |
3d339ad2 RS |
69 | |
70 | /* Compile passing first two args in regs 0 and 1. | |
71 | This exists only to test compiler features that will | |
72 | be needed for RISC chips. It is not usable | |
73 | and is not intended to be usable on this cpu. */ | |
7a1b98a9 RK |
74 | #define MASK_REGPARM 16 |
75 | #define TARGET_REGPARM (target_flags & MASK_REGPARM) | |
3d339ad2 RS |
76 | |
77 | /* Compile with 16-bit `int'. */ | |
7a1b98a9 RK |
78 | #define MASK_SHORT 32 |
79 | #define TARGET_SHORT (target_flags & MASK_SHORT) | |
3d339ad2 RS |
80 | |
81 | /* Compile with special insns for Sun FPA. */ | |
7a1b98a9 RK |
82 | #define MASK_FPA 64 |
83 | #define TARGET_FPA (target_flags & MASK_FPA) | |
3d339ad2 RS |
84 | |
85 | /* Compile (actually, link) for Sun SKY board. */ | |
7a1b98a9 RK |
86 | #define MASK_SKY 128 |
87 | #define TARGET_SKY (target_flags & MASK_SKY) | |
3d339ad2 | 88 | |
b4281273 RS |
89 | /* Optimize for 68040, but still allow execution on 68020 |
90 | (-m68020-40 or -m68040). | |
b4ac57ab | 91 | The 68040 will execute all 68030 and 68881/2 instructions, but some |
3d339ad2 RS |
92 | of them must be emulated in software by the OS. When TARGET_68040 is |
93 | turned on, these instructions won't be used. This code will still | |
94 | run on a 68030 and 68881/2. */ | |
35bcca7b | 95 | #define MASK_68040 256 |
7a1b98a9 | 96 | #define TARGET_68040 (target_flags & MASK_68040) |
3d339ad2 | 97 | |
30e6bc63 | 98 | /* Use the 68040-only fp instructions (-m68040 or -m68060). */ |
7a1b98a9 RK |
99 | #define MASK_68040_ONLY 512 |
100 | #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY) | |
3d339ad2 | 101 | |
30e6bc63 | 102 | /* Optimize for 68060, but still allow execution on 68020 |
35bcca7b | 103 | (-m68020-60 or -m68060). |
30e6bc63 RK |
104 | The 68060 will execute all 68030 and 68881/2 instructions, but some |
105 | of them must be emulated in software by the OS. When TARGET_68060 is | |
106 | turned on, these instructions won't be used. This code will still | |
107 | run on a 68030 and 68881/2. */ | |
7a1b98a9 RK |
108 | #define MASK_68060 1024 |
109 | #define TARGET_68060 (target_flags & MASK_68060) | |
30e6bc63 | 110 | |
106bee4b RK |
111 | /* Compile for mcf5200 */ |
112 | #define MASK_5200 2048 | |
113 | #define TARGET_5200 (target_flags & MASK_5200) | |
114 | ||
dcd13066 RK |
115 | /* Align ints to a word boundary. This breaks compatibility with the |
116 | published ABI's for structures containing ints, but produces faster | |
117 | code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire). | |
118 | It's required for coldfire cpus without a misalignment module. */ | |
119 | #define MASK_ALIGN_INT 4096 | |
120 | #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT) | |
121 | ||
b686ee30 RK |
122 | /* Compile for a CPU32 */ |
123 | /* A 68020 without bitfields is a good heuristic for a CPU32 */ | |
124 | #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD) | |
125 | ||
3d339ad2 RS |
126 | /* Macro to define tables used to set the flags. |
127 | This is a list in braces of pairs in braces, | |
128 | each pair being { "NAME", VALUE } | |
129 | where VALUE is the bits to set or minus the bits to clear. | |
130 | An empty string NAME is used to identify the default VALUE. */ | |
131 | ||
132 | #define TARGET_SWITCHES \ | |
35bcca7b RK |
133 | { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \ |
134 | { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \ | |
7a1b98a9 RK |
135 | { "68020", (MASK_68020|MASK_BITFIELD)}, \ |
136 | { "c68020", (MASK_68020|MASK_BITFIELD)}, \ | |
35bcca7b RK |
137 | { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
138 | |MASK_68020|MASK_BITFIELD)}, \ | |
139 | { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ | |
140 | |MASK_68020|MASK_BITFIELD)}, \ | |
d6539615 | 141 | { "bitfield", MASK_BITFIELD}, \ |
7a1b98a9 RK |
142 | { "nobitfield", - MASK_BITFIELD}, \ |
143 | { "rtd", MASK_RTD}, \ | |
144 | { "nortd", - MASK_RTD}, \ | |
145 | { "short", MASK_SHORT}, \ | |
146 | { "noshort", - MASK_SHORT}, \ | |
d6539615 | 147 | { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \ |
7a1b98a9 RK |
148 | { "fpa", MASK_FPA}, \ |
149 | { "nofpa", - MASK_FPA}, \ | |
d6539615 | 150 | { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881)}, \ |
7a1b98a9 RK |
151 | { "sky", MASK_SKY}, \ |
152 | { "nosky", - MASK_SKY}, \ | |
d6539615 RK |
153 | { "68881" - (MASK_FPA|MASK_SKY)}, \ |
154 | { "68881", MASK_68881}, \ | |
155 | { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \ | |
35bcca7b RK |
156 | { "68020-40", -(MASK_5200|MASK_68060)}, \ |
157 | { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040)}, \ | |
158 | { "68020-60", -(MASK_5200|MASK_68040)}, \ | |
159 | { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68060)}, \ | |
160 | { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \ | |
7a1b98a9 | 161 | { "68030", (MASK_68020|MASK_BITFIELD)}, \ |
35bcca7b RK |
162 | { "68040", - (MASK_5200|MASK_68060)}, \ |
163 | { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \ | |
164 | |MASK_68040_ONLY|MASK_68040)}, \ | |
165 | { "68060", - (MASK_5200|MASK_68040)}, \ | |
7a1b98a9 RK |
166 | { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \ |
167 | |MASK_68040_ONLY|MASK_68060)}, \ | |
106bee4b RK |
168 | { "5200", - (MASK_68060|MASK_68040|MASK_68020|MASK_BITFIELD|MASK_68881)}, \ |
169 | { "5200", (MASK_5200)}, \ | |
7a1b98a9 RK |
170 | { "68851", 0}, \ |
171 | { "no-68851", 0}, \ | |
35bcca7b RK |
172 | { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68020|MASK_BITFIELD)}, \ |
173 | { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_BITFIELD)}, \ | |
bae37e71 | 174 | { "68332", MASK_68020}, \ |
dcd13066 RK |
175 | { "align-int", MASK_ALIGN_INT }, \ |
176 | { "no-align-int", -MASK_ALIGN_INT }, \ | |
7a1b98a9 | 177 | SUBTARGET_SWITCHES \ |
3d339ad2 RS |
178 | { "", TARGET_DEFAULT}} |
179 | /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */ | |
882ed710 | 180 | |
9e62c7f2 RK |
181 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
182 | command options that have values. Its definition is an | |
183 | initializer with a subgrouping for each command option. | |
184 | ||
185 | Each subgrouping contains a string constant, that defines the | |
186 | fixed part of the option name, and the address of a variable. The | |
187 | variable, type `char *', is set to the variable part of the given | |
188 | option if the fixed part matches. The actual option name is made | |
189 | by appending `-m' to the specified name. */ | |
190 | #define TARGET_OPTIONS \ | |
191 | { { "align-loops=", &m68k_align_loops_string }, \ | |
192 | { "align-jumps=", &m68k_align_jumps_string }, \ | |
193 | { "align-functions=", &m68k_align_funcs_string }, \ | |
194 | SUBTARGET_OPTIONS \ | |
195 | } | |
196 | ||
197 | /* Sometimes certain combinations of command options do not make | |
198 | sense on a particular target machine. You can define a macro | |
199 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
200 | defined, is executed once just after all the command options have | |
201 | been parsed. | |
202 | ||
203 | Don't use this macro to turn on various extra optimizations for | |
204 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
84ab3bfb | 205 | |
3d339ad2 RS |
206 | #define OVERRIDE_OPTIONS \ |
207 | { \ | |
9e62c7f2 | 208 | override_options(); \ |
3d339ad2 RS |
209 | if (! TARGET_68020 && flag_pic == 2) \ |
210 | error("-fPIC is not currently supported on the 68000 or 68010\n"); \ | |
cf9be6f0 | 211 | SUBTARGET_OVERRIDE_OPTIONS; \ |
3d339ad2 | 212 | } |
84ab3bfb | 213 | |
9e62c7f2 RK |
214 | /* These are meant to be redefined in the host dependent files */ |
215 | #define SUBTARGET_SWITCHES | |
216 | #define SUBTARGET_OPTIONS | |
84ab3bfb | 217 | #define SUBTARGET_OVERRIDE_OPTIONS |
3d339ad2 RS |
218 | \f |
219 | /* target machine storage layout */ | |
220 | ||
f6ba6a91 RS |
221 | /* Define for XFmode extended real floating point support. |
222 | This will automatically cause REAL_ARITHMETIC to be defined. */ | |
223 | #define LONG_DOUBLE_TYPE_SIZE 96 | |
224 | ||
225 | /* Define if you don't want extended real, but do want to use the | |
226 | software floating point emulator for REAL_ARITHMETIC and | |
227 | decimal <-> binary conversion. */ | |
228 | /* #define REAL_ARITHMETIC */ | |
229 | ||
3d339ad2 RS |
230 | /* Define this if most significant bit is lowest numbered |
231 | in instructions that operate on numbered bit-fields. | |
232 | This is true for 68020 insns such as bfins and bfexts. | |
233 | We make it true always by avoiding using the single-bit insns | |
234 | except in special cases with constant bit numbers. */ | |
235 | #define BITS_BIG_ENDIAN 1 | |
236 | ||
237 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
238 | /* That is true on the 68000. */ | |
239 | #define BYTES_BIG_ENDIAN 1 | |
240 | ||
241 | /* Define this if most significant word of a multiword number is the lowest | |
242 | numbered. */ | |
243 | /* For 68000 we can decide arbitrarily | |
244 | since there are no machine instructions for them. | |
245 | So let's be consistent. */ | |
246 | #define WORDS_BIG_ENDIAN 1 | |
247 | ||
b4ac57ab | 248 | /* number of bits in an addressable storage unit */ |
3d339ad2 RS |
249 | #define BITS_PER_UNIT 8 |
250 | ||
251 | /* Width in bits of a "word", which is the contents of a machine register. | |
252 | Note that this is not necessarily the width of data type `int'; | |
253 | if using 16-bit ints on a 68000, this would still be 32. | |
254 | But on a machine with 16-bit registers, this would be 16. */ | |
255 | #define BITS_PER_WORD 32 | |
256 | ||
257 | /* Width of a word, in units (bytes). */ | |
258 | #define UNITS_PER_WORD 4 | |
259 | ||
260 | /* Width in bits of a pointer. | |
261 | See also the macro `Pmode' defined below. */ | |
262 | #define POINTER_SIZE 32 | |
263 | ||
264 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
265 | #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) | |
266 | ||
267 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
268 | #define STACK_BOUNDARY 16 | |
269 | ||
270 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
9e62c7f2 | 271 | #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3)) |
3d339ad2 RS |
272 | |
273 | /* Alignment of field after `int : 0' in a structure. */ | |
274 | #define EMPTY_FIELD_BOUNDARY 16 | |
275 | ||
dcd13066 RK |
276 | /* No data type wants to be aligned rounder than this. |
277 | Most published ABIs say that ints should be aligned on 16 bit | |
278 | boundries, but cpus with 32 bit busses get better performance | |
279 | aligned on 32 bit boundries. Coldfires without a misalignment | |
280 | module require 32 bit alignment. */ | |
281 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) | |
3d339ad2 | 282 | |
b4ac57ab | 283 | /* Set this nonzero if move instructions will actually fail to work |
3d339ad2 | 284 | when given unaligned data. */ |
b4ac57ab | 285 | #define STRICT_ALIGNMENT 1 |
3d339ad2 | 286 | |
9e62c7f2 RK |
287 | /* Maximum power of 2 that code can be aligned to. */ |
288 | #define MAX_CODE_ALIGN 2 /* 4 byte alignment */ | |
289 | ||
290 | /* Align loop starts for optimal branching. */ | |
291 | #define ASM_OUTPUT_LOOP_ALIGN(FILE) ASM_OUTPUT_ALIGN ((FILE), m68k_align_loops) | |
292 | ||
293 | /* This is how to align an instruction for optimal branching. */ | |
294 | #define ASM_OUTPUT_ALIGN_CODE(FILE) ASM_OUTPUT_ALIGN ((FILE), m68k_align_jumps) | |
295 | ||
3d339ad2 RS |
296 | #define SELECT_RTX_SECTION(MODE, X) \ |
297 | { \ | |
298 | if (!flag_pic) \ | |
299 | readonly_data_section(); \ | |
300 | else if (LEGITIMATE_PIC_OPERAND_P (X)) \ | |
301 | readonly_data_section(); \ | |
302 | else \ | |
303 | data_section(); \ | |
304 | } | |
305 | ||
306 | /* Define number of bits in most basic integer type. | |
307 | (If undefined, default is BITS_PER_WORD). */ | |
308 | ||
309 | #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) | |
310 | ||
311 | /* Define these to avoid dependence on meaning of `int'. | |
312 | Note that WCHAR_TYPE_SIZE is used in cexp.y, | |
313 | where TARGET_SHORT is not available. */ | |
314 | ||
315 | #define WCHAR_TYPE "long int" | |
316 | #define WCHAR_TYPE_SIZE 32 | |
317 | \f | |
318 | /* Standard register usage. */ | |
319 | ||
320 | /* Number of actual hardware registers. | |
321 | The hardware registers are assigned numbers for the compiler | |
322 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
323 | All registers that the compiler knows about must be given numbers, | |
324 | even those that are not normally considered general registers. | |
325 | For the 68000, we give the data registers numbers 0-7, | |
326 | the address registers numbers 010-017, | |
327 | and the 68881 floating point registers numbers 020-027. */ | |
328 | #ifndef SUPPORT_SUN_FPA | |
329 | #define FIRST_PSEUDO_REGISTER 24 | |
330 | #else | |
331 | #define FIRST_PSEUDO_REGISTER 56 | |
332 | #endif | |
333 | ||
334 | /* This defines the register which is used to hold the offset table for PIC. */ | |
335 | #define PIC_OFFSET_TABLE_REGNUM 13 | |
336 | ||
337 | /* Used to output a (use pic_offset_table_rtx) so that we | |
338 | always save/restore a5 in functions that use PIC relocation | |
339 | at *any* time during the compilation process. */ | |
340 | #define FINALIZE_PIC finalize_pic() | |
341 | ||
342 | #ifndef SUPPORT_SUN_FPA | |
343 | ||
344 | /* 1 for registers that have pervasive standard uses | |
345 | and are not available for the register allocator. | |
346 | On the 68000, only the stack pointer is such. */ | |
347 | ||
348 | #define FIXED_REGISTERS \ | |
349 | {/* Data registers. */ \ | |
350 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
351 | \ | |
352 | /* Address registers. */ \ | |
353 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
354 | \ | |
355 | /* Floating point registers \ | |
356 | (if available). */ \ | |
357 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
358 | ||
359 | /* 1 for registers not available across function calls. | |
360 | These must include the FIXED_REGISTERS and also any | |
361 | registers that can be used without being saved. | |
362 | The latter must include the registers where values are returned | |
363 | and the register where structure-value addresses are passed. | |
364 | Aside from that, you can include as many other registers as you like. */ | |
365 | #define CALL_USED_REGISTERS \ | |
366 | {1, 1, 0, 0, 0, 0, 0, 0, \ | |
367 | 1, 1, 0, 0, 0, 0, 0, 1, \ | |
368 | 1, 1, 0, 0, 0, 0, 0, 0 } | |
369 | ||
370 | #else /* SUPPORT_SUN_FPA */ | |
371 | ||
372 | /* 1 for registers that have pervasive standard uses | |
373 | and are not available for the register allocator. | |
374 | On the 68000, only the stack pointer is such. */ | |
375 | ||
376 | /* fpa0 is also reserved so that it can be used to move shit back and | |
377 | forth between high fpa regs and everything else. */ | |
378 | ||
379 | #define FIXED_REGISTERS \ | |
380 | {/* Data registers. */ \ | |
381 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
382 | \ | |
383 | /* Address registers. */ \ | |
384 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
385 | \ | |
386 | /* Floating point registers \ | |
387 | (if available). */ \ | |
388 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
389 | \ | |
390 | /* Sun3 FPA registers. */ \ | |
391 | 1, 0, 0, 0, 0, 0, 0, 0, \ | |
392 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
393 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
394 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
395 | ||
396 | /* 1 for registers not available across function calls. | |
397 | These must include the FIXED_REGISTERS and also any | |
398 | registers that can be used without being saved. | |
399 | The latter must include the registers where values are returned | |
400 | and the register where structure-value addresses are passed. | |
401 | Aside from that, you can include as many other registers as you like. */ | |
402 | #define CALL_USED_REGISTERS \ | |
403 | {1, 1, 0, 0, 0, 0, 0, 0, \ | |
404 | 1, 1, 0, 0, 0, 0, 0, 1, \ | |
405 | 1, 1, 0, 0, 0, 0, 0, 0, \ | |
406 | /* FPA registers. */ \ | |
407 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
408 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
409 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
410 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
411 | ||
412 | #endif /* defined SUPPORT_SUN_FPA */ | |
413 | ||
414 | ||
415 | /* Make sure everything's fine if we *don't* have a given processor. | |
416 | This assumes that putting a register in fixed_regs will keep the | |
417 | compiler's mitts completely off it. We don't bother to zero it out | |
418 | of register classes. If neither TARGET_FPA or TARGET_68881 is set, | |
419 | the compiler won't touch since no instructions that use these | |
eb939872 | 420 | registers will be valid. */ |
3d339ad2 | 421 | |
eb939872 | 422 | #ifdef SUPPORT_SUN_FPA |
3d339ad2 RS |
423 | |
424 | #define CONDITIONAL_REGISTER_USAGE \ | |
425 | { \ | |
426 | int i; \ | |
427 | HARD_REG_SET x; \ | |
428 | if (!TARGET_FPA) \ | |
429 | { \ | |
430 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \ | |
431 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
432 | if (TEST_HARD_REG_BIT (x, i)) \ | |
433 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
434 | } \ | |
435 | if (TARGET_FPA) \ | |
436 | { \ | |
437 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ | |
438 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
439 | if (TEST_HARD_REG_BIT (x, i)) \ | |
440 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
441 | } \ | |
3d339ad2 RS |
442 | } |
443 | ||
444 | #endif /* defined SUPPORT_SUN_FPA */ | |
445 | ||
446 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
447 | to hold something of mode MODE. | |
448 | This is ordinarily the length in words of a value of mode MODE | |
449 | but can be less for certain modes in special long registers. | |
450 | ||
451 | On the 68000, ordinary registers hold 32 bits worth; | |
452 | for the 68881 registers, a single register is always enough for | |
453 | anything that can be stored in them at all. */ | |
454 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
455 | ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ | |
456 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
457 | ||
458 | #ifndef SUPPORT_SUN_FPA | |
459 | ||
460 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
461 | On the 68000, the cpu registers can hold any mode but the 68881 registers | |
462 | can hold only SFmode or DFmode. The 68881 registers can't hold anything | |
463 | if 68881 use is disabled. */ | |
464 | ||
465 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
71380ac6 RK |
466 | (((REGNO) < 16 \ |
467 | && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8)) \ | |
3d339ad2 RS |
468 | || ((REGNO) < 24 \ |
469 | && TARGET_68881 \ | |
470 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
471 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT))) | |
472 | ||
473 | #else /* defined SUPPORT_SUN_FPA */ | |
474 | ||
475 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
476 | On the 68000, the cpu registers can hold any mode but the 68881 registers | |
477 | can hold only SFmode or DFmode. And the 68881 registers can't hold anything | |
478 | if 68881 use is disabled. However, the Sun FPA register can | |
479 | (apparently) hold whatever you feel like putting in them. | |
480 | If using the fpa, don't put a double in d7/a0. */ | |
481 | ||
482 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
483 | (((REGNO) < 16 \ | |
484 | && !(TARGET_FPA \ | |
485 | && GET_MODE_CLASS ((MODE)) != MODE_INT \ | |
486 | && GET_MODE_UNIT_SIZE ((MODE)) > 4 \ | |
487 | && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \ | |
488 | && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \ | |
489 | || ((REGNO) < 24 \ | |
490 | ? TARGET_68881 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
491 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
492 | : ((REGNO) < 56 ? TARGET_FPA : 0))) | |
493 | ||
494 | #endif /* defined SUPPORT_SUN_FPA */ | |
495 | ||
496 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
497 | when one has mode MODE1 and one has mode MODE2. | |
498 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
499 | for any hard reg, then this must be 0 for correct output. */ | |
500 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
501 | (! TARGET_68881 \ | |
502 | || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
503 | || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ | |
504 | == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
505 | || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) | |
506 | ||
507 | /* Specify the registers used for certain standard purposes. | |
508 | The values of these macros are register numbers. */ | |
509 | ||
510 | /* m68000 pc isn't overloaded on a register. */ | |
511 | /* #define PC_REGNUM */ | |
512 | ||
513 | /* Register to use for pushing function arguments. */ | |
514 | #define STACK_POINTER_REGNUM 15 | |
515 | ||
516 | /* Base register for access to local variables of the function. */ | |
517 | #define FRAME_POINTER_REGNUM 14 | |
518 | ||
519 | /* Value should be nonzero if functions must have frame pointers. | |
520 | Zero means the frame pointer need not be set up (and parms | |
521 | may be accessed via the stack pointer) in functions that seem suitable. | |
522 | This is computed in `reload', in reload1.c. */ | |
523 | #define FRAME_POINTER_REQUIRED 0 | |
524 | ||
525 | /* Base register for access to arguments of the function. */ | |
526 | #define ARG_POINTER_REGNUM 14 | |
527 | ||
528 | /* Register in which static-chain is passed to a function. */ | |
529 | #define STATIC_CHAIN_REGNUM 8 | |
530 | ||
531 | /* Register in which address to store a structure value | |
532 | is passed to a function. */ | |
533 | #define STRUCT_VALUE_REGNUM 9 | |
534 | \f | |
535 | /* Define the classes of registers for register constraints in the | |
536 | machine description. Also define ranges of constants. | |
537 | ||
538 | One of the classes must always be named ALL_REGS and include all hard regs. | |
539 | If there is more than one class, another class must be named NO_REGS | |
540 | and contain no registers. | |
541 | ||
542 | The name GENERAL_REGS must be the name of a class (or an alias for | |
543 | another name such as ALL_REGS). This is the class of registers | |
544 | that is allowed by "g" or "r" in a register constraint. | |
545 | Also, registers outside this class are allocated only when | |
546 | instructions express preferences for them. | |
547 | ||
548 | The classes must be numbered in nondecreasing order; that is, | |
549 | a larger-numbered class must never be contained completely | |
550 | in a smaller-numbered class. | |
551 | ||
552 | For any two classes, it is very desirable that there be another | |
553 | class that represents their union. */ | |
554 | ||
555 | /* The 68000 has three kinds of registers, so eight classes would be | |
556 | a complete set. One of them is not needed. */ | |
557 | ||
558 | #ifndef SUPPORT_SUN_FPA | |
559 | ||
560 | enum reg_class { | |
561 | NO_REGS, DATA_REGS, | |
562 | ADDR_REGS, FP_REGS, | |
563 | GENERAL_REGS, DATA_OR_FP_REGS, | |
564 | ADDR_OR_FP_REGS, ALL_REGS, | |
565 | LIM_REG_CLASSES }; | |
566 | ||
567 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
568 | ||
569 | /* Give names of register classes as strings for dump file. */ | |
570 | ||
571 | #define REG_CLASS_NAMES \ | |
572 | { "NO_REGS", "DATA_REGS", \ | |
573 | "ADDR_REGS", "FP_REGS", \ | |
574 | "GENERAL_REGS", "DATA_OR_FP_REGS", \ | |
575 | "ADDR_OR_FP_REGS", "ALL_REGS" } | |
576 | ||
577 | /* Define which registers fit in which classes. | |
578 | This is an initializer for a vector of HARD_REG_SET | |
579 | of length N_REG_CLASSES. */ | |
580 | ||
581 | #define REG_CLASS_CONTENTS \ | |
582 | { \ | |
583 | 0x00000000, /* NO_REGS */ \ | |
584 | 0x000000ff, /* DATA_REGS */ \ | |
585 | 0x0000ff00, /* ADDR_REGS */ \ | |
586 | 0x00ff0000, /* FP_REGS */ \ | |
587 | 0x0000ffff, /* GENERAL_REGS */ \ | |
588 | 0x00ff00ff, /* DATA_OR_FP_REGS */ \ | |
589 | 0x00ffff00, /* ADDR_OR_FP_REGS */ \ | |
590 | 0x00ffffff, /* ALL_REGS */ \ | |
591 | } | |
592 | ||
593 | /* The same information, inverted: | |
594 | Return the class number of the smallest class containing | |
595 | reg number REGNO. This could be a conditional expression | |
596 | or could index an array. */ | |
597 | ||
598 | #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1) | |
599 | ||
600 | #else /* defined SUPPORT_SUN_FPA */ | |
601 | ||
602 | /* | |
603 | * Notes on final choices: | |
604 | * | |
605 | * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything | |
606 | * else. | |
607 | * 2) Removed all unions that involve address registers with | |
608 | * floating point registers (left in unions of address and data with | |
609 | * floating point). | |
610 | * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS. | |
611 | * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS. | |
612 | * 4) Left in everything else. | |
613 | */ | |
614 | enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS, | |
615 | FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS, | |
616 | DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS, | |
617 | GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS, | |
618 | LIM_REG_CLASSES }; | |
619 | ||
620 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
621 | ||
622 | /* Give names of register classes as strings for dump file. */ | |
623 | ||
624 | #define REG_CLASS_NAMES \ | |
625 | { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \ | |
626 | "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \ | |
627 | "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \ | |
628 | "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" } | |
629 | ||
630 | /* Define which registers fit in which classes. | |
631 | This is an initializer for a vector of HARD_REG_SET | |
632 | of length N_REG_CLASSES. */ | |
633 | ||
634 | #define REG_CLASS_CONTENTS \ | |
635 | { \ | |
636 | {0, 0}, /* NO_REGS */ \ | |
637 | {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \ | |
638 | {0xff000000, 0x00ffffff}, /* FPA_REGS */ \ | |
639 | {0x00ff0000, 0x00000000}, /* FP_REGS */ \ | |
640 | {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \ | |
641 | {0x000000ff, 0x00000000}, /* DATA_REGS */ \ | |
642 | {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \ | |
643 | {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \ | |
644 | {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\ | |
645 | {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \ | |
646 | {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \ | |
647 | {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\ | |
648 | {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\ | |
649 | {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \ | |
650 | } | |
651 | ||
652 | /* The same information, inverted: | |
653 | Return the class number of the smallest class containing | |
654 | reg number REGNO. This could be a conditional expression | |
655 | or could index an array. */ | |
656 | ||
657 | extern enum reg_class regno_reg_class[]; | |
658 | #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) | |
659 | ||
660 | #endif /* SUPPORT_SUN_FPA */ | |
661 | ||
662 | /* The class value for index registers, and the one for base regs. */ | |
663 | ||
664 | #define INDEX_REG_CLASS GENERAL_REGS | |
665 | #define BASE_REG_CLASS ADDR_REGS | |
666 | ||
667 | /* Get reg_class from a letter such as appears in the machine description. | |
668 | We do a trick here to modify the effective constraints on the | |
669 | machine description; we zorch the constraint letters that aren't | |
670 | appropriate for a specific target. This allows us to guarantee | |
671 | that a specific kind of register will not be used for a given target | |
672 | without fiddling with the register classes above. */ | |
673 | ||
674 | #ifndef SUPPORT_SUN_FPA | |
675 | ||
676 | #define REG_CLASS_FROM_LETTER(C) \ | |
677 | ((C) == 'a' ? ADDR_REGS : \ | |
678 | ((C) == 'd' ? DATA_REGS : \ | |
679 | ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ | |
680 | NO_REGS) : \ | |
681 | NO_REGS))) | |
682 | ||
683 | #else /* defined SUPPORT_SUN_FPA */ | |
684 | ||
685 | #define REG_CLASS_FROM_LETTER(C) \ | |
686 | ((C) == 'a' ? ADDR_REGS : \ | |
687 | ((C) == 'd' ? DATA_REGS : \ | |
688 | ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ | |
689 | NO_REGS) : \ | |
690 | ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \ | |
691 | NO_REGS) : \ | |
692 | ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \ | |
693 | NO_REGS) : \ | |
694 | NO_REGS))))) | |
695 | ||
696 | #endif /* defined SUPPORT_SUN_FPA */ | |
697 | ||
698 | /* The letters I, J, K, L and M in a register constraint string | |
699 | can be used to stand for particular ranges of immediate operands. | |
700 | This macro defines what the ranges are. | |
701 | C is the letter, and VALUE is a constant value. | |
702 | Return 1 if VALUE is in the range specified by C. | |
703 | ||
704 | For the 68000, `I' is used for the range 1 to 8 | |
705 | allowed as immediate shift counts and in addq. | |
706 | `J' is used for the range of signed numbers that fit in 16 bits. | |
707 | `K' is for numbers that moveq can't handle. | |
a9f6f5aa | 708 | `L' is for range -8 to -1, range of values that can be added with subq. |
d8fa884b RK |
709 | `M' is for numbers that moveq+notb can't handle. |
710 | 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate. | |
711 | 'O' is for 16 (for rotate using swap). | |
712 | 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */ | |
a9f6f5aa RK |
713 | |
714 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
715 | ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ | |
716 | (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ | |
717 | (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ | |
718 | (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \ | |
d8fa884b RK |
719 | (C) == 'M' ? (VALUE) < -0x100 && (VALUE) >= 0x100 : \ |
720 | (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \ | |
721 | (C) == 'O' ? (VALUE) == 16 : \ | |
722 | (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0) | |
3d339ad2 RS |
723 | |
724 | /* | |
725 | * A small bit of explanation: | |
726 | * "G" defines all of the floating constants that are *NOT* 68881 | |
727 | * constants. this is so 68881 constants get reloaded and the | |
728 | * fpmovecr is used. "H" defines *only* the class of constants that | |
729 | * the fpa can use, because these can be gotten at in any fpa | |
730 | * instruction and there is no need to force reloads. | |
731 | */ | |
732 | #ifndef SUPPORT_SUN_FPA | |
733 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
734 | ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) | |
735 | #else /* defined SUPPORT_SUN_FPA */ | |
736 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
737 | ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \ | |
738 | (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0) | |
739 | #endif /* defined SUPPORT_SUN_FPA */ | |
740 | ||
741 | /* Given an rtx X being reloaded into a reg required to be | |
742 | in class CLASS, return the class of reg to actually use. | |
743 | In general this is just CLASS; but on some machines | |
744 | in some cases it is preferable to use a more restrictive class. | |
745 | On the 68000 series, use a data reg if possible when the | |
746 | value is a constant in the range where moveq could be used | |
747 | and we ensure that QImodes are reloaded into data regs. | |
9c05a5ad RK |
748 | Also, if a floating constant needs reloading, put it in memory. |
749 | Don't do this for !G constants, since all patterns in the md file | |
750 | expect them to be loaded into a register via fpmovecr. See above. */ | |
3d339ad2 RS |
751 | |
752 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
753 | ((GET_CODE (X) == CONST_INT \ | |
754 | && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ | |
755 | && (CLASS) != ADDR_REGS) \ | |
756 | ? DATA_REGS \ | |
757 | : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ | |
758 | ? DATA_REGS \ | |
759 | : (GET_CODE (X) == CONST_DOUBLE \ | |
760 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ | |
9c05a5ad | 761 | ? (! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G') \ |
089a0f39 | 762 | && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ |
9c05a5ad | 763 | ? FP_REGS : NO_REGS) \ |
3d339ad2 RS |
764 | : (CLASS)) |
765 | ||
766 | /* Return the maximum number of consecutive registers | |
767 | needed to represent mode MODE in a register of class CLASS. */ | |
768 | /* On the 68000, this is the size of MODE in words, | |
769 | except in the FP regs, where a single reg is always enough. */ | |
770 | #ifndef SUPPORT_SUN_FPA | |
771 | ||
772 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
773 | ((CLASS) == FP_REGS ? 1 \ | |
774 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
775 | ||
776 | /* Moves between fp regs and other regs are two insns. */ | |
777 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ | |
778 | (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ | |
779 | || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ | |
780 | ? 4 : 2) | |
781 | ||
782 | #else /* defined SUPPORT_SUN_FPA */ | |
783 | ||
784 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
785 | ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \ | |
786 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
787 | ||
788 | /* Moves between fp regs and other regs are two insns. */ | |
789 | /* Likewise for high fpa regs and other regs. */ | |
790 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ | |
791 | ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ | |
792 | || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ | |
793 | || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \ | |
794 | || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \ | |
795 | ? 4 : 2) | |
796 | ||
797 | #endif /* define SUPPORT_SUN_FPA */ | |
798 | \f | |
799 | /* Stack layout; function entry, exit and calling. */ | |
800 | ||
801 | /* Define this if pushing a word on the stack | |
802 | makes the stack pointer a smaller address. */ | |
803 | #define STACK_GROWS_DOWNWARD | |
804 | ||
805 | /* Nonzero if we need to generate stack-probe insns. | |
806 | On most systems they are not needed. | |
807 | When they are needed, define this as the stack offset to probe at. */ | |
808 | #define NEED_PROBE 0 | |
809 | ||
810 | /* Define this if the nominal address of the stack frame | |
811 | is at the high-address end of the local variables; | |
812 | that is, each additional local variable allocated | |
813 | goes at a more negative offset in the frame. */ | |
814 | #define FRAME_GROWS_DOWNWARD | |
815 | ||
816 | /* Offset within stack frame to start allocating local variables at. | |
817 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
818 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
819 | of the first local allocated. */ | |
820 | #define STARTING_FRAME_OFFSET 0 | |
821 | ||
822 | /* If we generate an insn to push BYTES bytes, | |
823 | this says how many the stack pointer really advances by. | |
824 | On the 68000, sp@- in a byte insn really pushes a word. */ | |
825 | #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) | |
826 | ||
827 | /* Offset of first parameter from the argument pointer register value. */ | |
828 | #define FIRST_PARM_OFFSET(FNDECL) 8 | |
829 | ||
830 | /* Value is the number of byte of arguments automatically | |
831 | popped when returning from a subroutine call. | |
8b109b37 | 832 | FUNDECL is the declaration node of the function (as a tree), |
3d339ad2 RS |
833 | FUNTYPE is the data type of the function (as a tree), |
834 | or for a library call it is an identifier node for the subroutine name. | |
835 | SIZE is the number of bytes of arguments passed on the stack. | |
836 | ||
837 | On the 68000, the RTS insn cannot pop anything. | |
838 | On the 68010, the RTD insn may be used to pop them if the number | |
839 | of args is fixed, but if the number is variable then the caller | |
840 | must pop them all. RTD can't be used for library calls now | |
841 | because the library is compiled with the Unix compiler. | |
842 | Use of RTD is a selectable option, since it is incompatible with | |
843 | standard Unix calling sequences. If the option is not selected, | |
844 | the caller must always pop the args. */ | |
845 | ||
8b109b37 | 846 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ |
2033a41a | 847 | ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \ |
3d339ad2 RS |
848 | && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ |
849 | || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ | |
850 | == void_type_node))) \ | |
851 | ? (SIZE) : 0) | |
852 | ||
853 | /* Define how to find the value returned by a function. | |
854 | VALTYPE is the data type of the value (as a tree). | |
855 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
856 | otherwise, FUNC is 0. */ | |
857 | ||
858 | /* On the 68000 the return value is in D0 regardless. */ | |
859 | ||
860 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
861 | gen_rtx (REG, TYPE_MODE (VALTYPE), 0) | |
862 | ||
863 | /* Define how to find the value returned by a library function | |
864 | assuming the value has mode MODE. */ | |
865 | ||
866 | /* On the 68000 the return value is in D0 regardless. */ | |
867 | ||
868 | #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0) | |
869 | ||
870 | /* 1 if N is a possible register number for a function value. | |
871 | On the 68000, d0 is the only register thus used. */ | |
872 | ||
873 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) | |
874 | ||
7972af82 TW |
875 | /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for |
876 | more than one register. */ | |
877 | ||
878 | #define NEEDS_UNTYPED_CALL 0 | |
879 | ||
3d339ad2 RS |
880 | /* Define this if PCC uses the nonreentrant convention for returning |
881 | structure and union values. */ | |
882 | ||
883 | #define PCC_STATIC_STRUCT_RETURN | |
884 | ||
885 | /* 1 if N is a possible register number for function argument passing. | |
886 | On the 68000, no registers are used in this way. */ | |
887 | ||
888 | #define FUNCTION_ARG_REGNO_P(N) 0 | |
889 | \f | |
890 | /* Define a data type for recording info about an argument list | |
891 | during the scan of that argument list. This data type should | |
892 | hold all necessary information about the function itself | |
893 | and about the args processed so far, enough to enable macros | |
894 | such as FUNCTION_ARG to determine where the next arg should go. | |
895 | ||
896 | On the m68k, this is a single integer, which is a number of bytes | |
897 | of arguments scanned so far. */ | |
898 | ||
899 | #define CUMULATIVE_ARGS int | |
900 | ||
901 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
902 | for a call to a function whose data type is FNTYPE. | |
903 | For a library call, FNTYPE is 0. | |
904 | ||
905 | On the m68k, the offset starts at 0. */ | |
906 | ||
2c7ee1a6 | 907 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
3d339ad2 RS |
908 | ((CUM) = 0) |
909 | ||
910 | /* Update the data in CUM to advance over an argument | |
911 | of mode MODE and data type TYPE. | |
912 | (TYPE is null for libcalls where that information may not be available.) */ | |
913 | ||
914 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
915 | ((CUM) += ((MODE) != BLKmode \ | |
916 | ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ | |
917 | : (int_size_in_bytes (TYPE) + 3) & ~3)) | |
918 | ||
919 | /* Define where to put the arguments to a function. | |
920 | Value is zero to push the argument on the stack, | |
921 | or a hard register in which to store the argument. | |
922 | ||
923 | MODE is the argument's machine mode. | |
924 | TYPE is the data type of the argument (as a tree). | |
925 | This is null for libcalls where that information may | |
926 | not be available. | |
927 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
928 | the preceding args and about the function being called. | |
929 | NAMED is nonzero if this argument is a named parameter | |
930 | (otherwise it is an extra parameter matching an ellipsis). */ | |
931 | ||
932 | /* On the 68000 all args are pushed, except if -mregparm is specified | |
933 | then the first two words of arguments are passed in d0, d1. | |
934 | *NOTE* -mregparm does not work. | |
935 | It exists only to test register calling conventions. */ | |
936 | ||
937 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
938 | ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0) | |
939 | ||
940 | /* For an arg passed partly in registers and partly in memory, | |
941 | this is the number of registers used. | |
942 | For args passed entirely in registers or entirely in memory, zero. */ | |
943 | ||
944 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
945 | ((TARGET_REGPARM && (CUM) < 8 \ | |
946 | && 8 < ((CUM) + ((MODE) == BLKmode \ | |
947 | ? int_size_in_bytes (TYPE) \ | |
948 | : GET_MODE_SIZE (MODE)))) \ | |
949 | ? 2 - (CUM) / 4 : 0) | |
950 | ||
951 | /* Generate the assembly code for function entry. */ | |
952 | #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE) | |
953 | ||
954 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
955 | for profiling a function entry. */ | |
956 | ||
957 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
958 | asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) | |
959 | ||
960 | /* Output assembler code to FILE to initialize this source file's | |
961 | basic block profiling info, if that has not already been done. */ | |
962 | ||
6e753900 RK |
963 | #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \ |
964 | do \ | |
965 | { \ | |
966 | switch (profile_block_flag) \ | |
967 | { \ | |
968 | case 2: \ | |
969 | asm_fprintf (FILE, "\tpea %d\n\tpea %LLPBX0\n\tjsr %U__bb_init_trace_func\n\taddql %I8,%Rsp\n", \ | |
970 | (BLOCK_OR_LABEL)); \ | |
971 | break; \ | |
972 | \ | |
973 | default: \ | |
974 | asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \ | |
975 | (BLOCK_OR_LABEL), (BLOCK_OR_LABEL)); \ | |
976 | break; \ | |
977 | } \ | |
978 | } \ | |
979 | while(0) | |
980 | ||
981 | /* Output assembler code to FILE to increment the counter for | |
3d339ad2 RS |
982 | the BLOCKNO'th basic block in this source file. */ |
983 | ||
984 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
6e753900 RK |
985 | do \ |
986 | { \ | |
987 | switch (profile_block_flag) \ | |
988 | { \ | |
989 | case 2: \ | |
990 | asm_fprintf (FILE, "\tmovel %Ra1,%Rsp@-\n\tlea ___bb,%Ra1\n\tmovel %I%d,%Ra1@(0)\n\tmovel %I%LLPBX0,%Ra1@(4)\n\tmovel %Rsp@+,%Ra1\n\tjsr %U__bb_trace_func\n", \ | |
991 | BLOCKNO); \ | |
992 | break; \ | |
993 | \ | |
994 | default: \ | |
995 | asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO); \ | |
996 | break; \ | |
997 | } \ | |
998 | } \ | |
999 | while(0) | |
1000 | ||
1001 | /* Output assembler code to FILE to indicate return from | |
1002 | a function during basic block profiling. */ | |
1003 | ||
1004 | #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \ | |
1005 | asm_fprintf (FILE, "\tjsr %U__bb_trace_ret\n"); | |
1006 | ||
1007 | /* Save all registers which may be clobbered by a function call. */ | |
1008 | ||
ad92f794 RK |
1009 | #ifdef MOTOROLA |
1010 | #define MACHINE_STATE_SAVE(id) \ | |
0be1f0e1 JW |
1011 | if (TARGET_5200) \ |
1012 | { \ | |
1013 | asm ("sub.l 20,%sp"); \ | |
1014 | asm ("movm.l &0x0303,4(%sp)"); \ | |
1015 | asm ("move.w %ccr,%d0"); \ | |
1016 | asm ("movm.l &0x0001,(%sp)"); \ | |
1017 | } \ | |
1018 | else \ | |
1019 | { \ | |
1020 | asm ("move.w %ccr,-(%sp)"); \ | |
1021 | asm ("movm.l &0xc0c0,-(%sp)"); \ | |
1022 | } | |
ad92f794 RK |
1023 | #else |
1024 | #define MACHINE_STATE_SAVE(id) \ | |
0be1f0e1 JW |
1025 | if (TARGET_5200) \ |
1026 | { \ | |
1027 | asm ("subl 20,sp"); \ | |
1028 | asm ("movml d0/d1/a0/a1,sp@(4)"); \ | |
1029 | asm ("movew cc,d0"); \ | |
1030 | asm ("movml d0,sp@"); \ | |
1031 | } \ | |
1032 | else \ | |
1033 | { \ | |
1034 | asm ("movew cc,sp@-"); \ | |
1035 | asm ("moveml d0/d1/a0/a1,sp@-"); \ | |
1036 | } | |
ad92f794 | 1037 | #endif |
6e753900 RK |
1038 | |
1039 | /* Restore all registers saved by MACHINE_STATE_SAVE. */ | |
1040 | ||
ad92f794 RK |
1041 | #ifdef MOTOROLA |
1042 | #define MACHINE_STATE_RESTORE(id) \ | |
0be1f0e1 JW |
1043 | if (TARGET_5200) \ |
1044 | { \ | |
1045 | asm ("movm.l (%sp),&0x0001"); \ | |
1046 | asm ("move.w %d0,%ccr"); \ | |
1047 | asm ("movm.l 4(%sp),&0x0303"); \ | |
1048 | asm ("add.l 20,%sp"); \ | |
1049 | } \ | |
1050 | else \ | |
1051 | { \ | |
1052 | asm ("movm.l (%sp)+,&0x0303"); \ | |
1053 | asm ("move.w (%sp)+,%ccr"); \ | |
1054 | } | |
ad92f794 RK |
1055 | #else |
1056 | #define MACHINE_STATE_RESTORE(id) \ | |
0be1f0e1 JW |
1057 | if (TARGET_5200) \ |
1058 | { \ | |
1059 | asm ("movml sp@,d0"); \ | |
1060 | asm ("movew d0,cc"); \ | |
1061 | asm ("movml sp@(4),d0/d1/a0/a1"); \ | |
1062 | asm ("addl 20,sp"); \ | |
1063 | } \ | |
1064 | else \ | |
1065 | { \ | |
1066 | asm ("moveml sp@+,d0/d1/a0/a1"); \ | |
1067 | asm ("movew sp@+,cc"); \ | |
1068 | } | |
ad92f794 | 1069 | #endif |
3d339ad2 RS |
1070 | |
1071 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1072 | the stack pointer does not matter. The value is tested only in | |
1073 | functions that have frame pointers. | |
1074 | No definition is equivalent to always zero. */ | |
1075 | ||
1076 | #define EXIT_IGNORE_STACK 1 | |
1077 | ||
1078 | /* Generate the assembly code for function exit. */ | |
1079 | #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE) | |
1080 | ||
1081 | /* This is a hook for other tm files to change. */ | |
1082 | /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */ | |
1083 | ||
1084 | /* Determine if the epilogue should be output as RTL. | |
1085 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
1086 | #define USE_RETURN_INSN use_return_insn () | |
1087 | ||
1088 | /* Store in the variable DEPTH the initial difference between the | |
1089 | frame pointer reg contents and the stack pointer reg contents, | |
1090 | as of the start of the function body. This depends on the layout | |
1091 | of the fixed parts of the stack frame and on how registers are saved. | |
1092 | ||
1093 | On the 68k, if we have a frame, we must add one word to its length | |
1094 | to allow for the place that a6 is stored when we do have a frame pointer. | |
1095 | Otherwise, we would need to compute the offset from the frame pointer | |
1096 | of a local variable as a function of frame_pointer_needed, which | |
1097 | is hard. */ | |
1098 | ||
1099 | #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ | |
1100 | { int regno; \ | |
1101 | int offset = -4; \ | |
1102 | for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ | |
1103 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1104 | offset += 12; \ | |
1105 | for (regno = 0; regno < 16; regno++) \ | |
1106 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1107 | offset += 4; \ | |
1108 | (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \ | |
1109 | + (get_frame_size () == 0 ? 0 : 4)); \ | |
1110 | } | |
1111 | ||
1112 | /* Output assembler code for a block containing the constant parts | |
1113 | of a trampoline, leaving space for the variable parts. */ | |
1114 | ||
1115 | /* On the 68k, the trampoline looks like this: | |
27a55d6b RK |
1116 | movl #STATIC,a0 |
1117 | jmp FUNCTION | |
1118 | ||
1119 | WARNING: Targets that may run on 68040+ cpus must arrange for | |
1120 | the instruction cache to be flushed. Previous incarnations of | |
1121 | the m68k trampoline code attempted to get around this by either | |
1122 | using an out-of-line transfer function or pc-relative data, but | |
1123 | the fact remains that the code to jump to the transfer function | |
1124 | or the code to load the pc-relative data needs to be flushed | |
1125 | just as much as the "variable" portion of the trampoline. | |
1126 | Recognizing that a cache flush is going to be required anyway, | |
1127 | dispense with such notions and build a smaller trampoline. */ | |
1128 | ||
1129 | /* Since more instructions are required to move a template into | |
1130 | place than to create it on the spot, don't use a template. */ | |
3d339ad2 RS |
1131 | |
1132 | /* Length in units of the trampoline for entering a nested function. */ | |
1133 | ||
27a55d6b RK |
1134 | #define TRAMPOLINE_SIZE 12 |
1135 | ||
1136 | /* Alignment required for a trampoline in bits. */ | |
3d339ad2 | 1137 | |
27a55d6b | 1138 | #define TRAMPOLINE_ALIGNMENT 16 |
3d339ad2 | 1139 | |
27a55d6b RK |
1140 | /* Targets redefine this to invoke code to either flush the cache, |
1141 | or enable stack execution (or both). */ | |
1142 | ||
1143 | #ifndef FINALIZE_TRAMPOLINE | |
1144 | #define FINALIZE_TRAMPOLINE(TRAMP) | |
1145 | #endif | |
3d339ad2 RS |
1146 | |
1147 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1148 | FNADDR is an RTX for the address of the function's pure code. | |
1149 | CXT is an RTX for the static chain value for the function. */ | |
1150 | ||
1151 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1152 | { \ | |
27a55d6b RK |
1153 | emit_move_insn (gen_rtx (MEM, HImode, TRAMP), GEN_INT(0x207C)); \ |
1154 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), CXT); \ | |
1155 | emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 6)), \ | |
1156 | GEN_INT(0x4EF9)); \ | |
1157 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), FNADDR); \ | |
1158 | FINALIZE_TRAMPOLINE(TRAMP); \ | |
3d339ad2 RS |
1159 | } |
1160 | ||
1161 | /* This is the library routine that is used | |
1162 | to transfer control from the trampoline | |
e73cbb04 RK |
1163 | to the actual nested function. |
1164 | It is defined for backward compatibility, | |
1165 | for linking with object code that used the old | |
1166 | trampoline definition. */ | |
3d339ad2 RS |
1167 | |
1168 | /* A colon is used with no explicit operands | |
1169 | to cause the template string to be scanned for %-constructs. */ | |
1170 | /* The function name __transfer_from_trampoline is not actually used. | |
1171 | The function definition just permits use of "asm with operands" | |
1172 | (though the operand list is empty). */ | |
1173 | #define TRANSFER_FROM_TRAMPOLINE \ | |
1174 | void \ | |
1175 | __transfer_from_trampoline () \ | |
1176 | { \ | |
1177 | register char *a0 asm ("%a0"); \ | |
2e3c09cd | 1178 | asm (GLOBAL_ASM_OP " ___trampoline"); \ |
3d339ad2 | 1179 | asm ("___trampoline:"); \ |
338818c7 RK |
1180 | asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ |
1181 | asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ | |
3d339ad2 RS |
1182 | asm ("rts":); \ |
1183 | } | |
1184 | \f | |
1185 | /* Addressing modes, and classification of registers for them. */ | |
1186 | ||
1187 | #define HAVE_POST_INCREMENT | |
1188 | /* #define HAVE_POST_DECREMENT */ | |
1189 | ||
1190 | #define HAVE_PRE_DECREMENT | |
1191 | /* #define HAVE_PRE_INCREMENT */ | |
1192 | ||
1193 | /* Macros to check register numbers against specific register classes. */ | |
1194 | ||
1195 | /* These assume that REGNO is a hard or pseudo reg number. | |
1196 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1197 | or a pseudo reg currently allocated to a suitable hard reg. | |
1198 | Since they use reg_renumber, they are safe only once reg_renumber | |
1199 | has been allocated, which happens in local-alloc.c. */ | |
1200 | ||
1201 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1202 | ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) | |
1203 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1204 | (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) | |
1205 | #define REGNO_OK_FOR_DATA_P(REGNO) \ | |
1206 | ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) | |
1207 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
1208 | (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) | |
1209 | #ifdef SUPPORT_SUN_FPA | |
1210 | #define REGNO_OK_FOR_FPA_P(REGNO) \ | |
1211 | (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56)) | |
1212 | #endif | |
1213 | ||
1214 | /* Now macros that check whether X is a register and also, | |
1215 | strictly, whether it is in a specified class. | |
1216 | ||
1217 | These macros are specific to the 68000, and may be used only | |
1218 | in code for printing assembler insns and in conditions for | |
1219 | define_optimization. */ | |
1220 | ||
1221 | /* 1 if X is a data register. */ | |
1222 | ||
1223 | #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) | |
1224 | ||
1225 | /* 1 if X is an fp register. */ | |
1226 | ||
1227 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
1228 | ||
1229 | /* 1 if X is an address register */ | |
1230 | ||
1231 | #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) | |
1232 | ||
1233 | #ifdef SUPPORT_SUN_FPA | |
1234 | /* 1 if X is a register in the Sun FPA. */ | |
1235 | #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X))) | |
1236 | #else | |
1237 | /* Answer must be no if we don't have an FPA. */ | |
1238 | #define FPA_REG_P(X) 0 | |
1239 | #endif | |
1240 | \f | |
1241 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1242 | ||
1243 | #define MAX_REGS_PER_ADDRESS 2 | |
1244 | ||
1245 | /* Recognize any constant value that is a valid address. */ | |
1246 | ||
6eff269e BK |
1247 | #define CONSTANT_ADDRESS_P(X) \ |
1248 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1249 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1250 | || GET_CODE (X) == HIGH) | |
3d339ad2 RS |
1251 | |
1252 | /* Nonzero if the constant value X is a legitimate general operand. | |
1253 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1254 | ||
1255 | #define LEGITIMATE_CONSTANT_P(X) 1 | |
1256 | ||
1257 | /* Nonzero if the constant value X is a legitimate general operand | |
1258 | when generating PIC code. It is given that flag_pic is on and | |
1259 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1260 | ||
1261 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
c57eee67 RK |
1262 | ((! symbolic_operand (X, VOIDmode) \ |
1263 | && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X) \ | |
1264 | && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM \ | |
1265 | && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), \ | |
1266 | VOIDmode))) \ | |
1267 | || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X))) | |
3d339ad2 RS |
1268 | |
1269 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1270 | and check its validity for a certain class. | |
1271 | We have two alternate definitions for each of them. | |
1272 | The usual definition accepts all pseudo regs; the other rejects | |
1273 | them unless they have been allocated suitable hard regs. | |
1274 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1275 | ||
1276 | Most source files want to accept pseudo regs in the hope that | |
1277 | they will get allocated to the class that the insn wants them to be in. | |
1278 | Source files for reload pass need to be strict. | |
1279 | After reload, it makes no difference, since pseudo regs have | |
1280 | been eliminated by then. */ | |
1281 | ||
1282 | #ifndef REG_OK_STRICT | |
1283 | ||
1284 | /* Nonzero if X is a hard reg that can be used as an index | |
1285 | or if it is a pseudo reg. */ | |
1286 | #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) | |
1287 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1288 | or if it is a pseudo reg. */ | |
1289 | #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) | |
1290 | ||
1291 | #else | |
1292 | ||
1293 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1294 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1295 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1296 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1297 | ||
1298 | #endif | |
1299 | \f | |
1300 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1301 | that is a valid memory address for an instruction. | |
1302 | The MODE argument is the machine mode for the MEM expression | |
1303 | that wants to use this address. | |
1304 | ||
1305 | When generating PIC, an address involving a SYMBOL_REF is legitimate | |
1306 | if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. | |
1307 | We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, | |
1308 | and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. | |
1309 | ||
1310 | Likewise for a LABEL_REF when generating PIC. | |
1311 | ||
1312 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
1313 | ||
22291e2f JW |
1314 | /* Allow SUBREG everywhere we allow REG. This results in better code. It |
1315 | also makes function inlining work when inline functions are called with | |
1316 | arguments that are SUBREGs. */ | |
1317 | ||
1318 | #define LEGITIMATE_BASE_REG_P(X) \ | |
1319 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1320 | || (GET_CODE (X) == SUBREG \ | |
1321 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1322 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
1323 | ||
3d339ad2 RS |
1324 | #define INDIRECTABLE_1_ADDRESS_P(X) \ |
1325 | ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ | |
22291e2f | 1326 | || LEGITIMATE_BASE_REG_P (X) \ |
3d339ad2 | 1327 | || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ |
22291e2f | 1328 | && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ |
3d339ad2 | 1329 | || (GET_CODE (X) == PLUS \ |
22291e2f | 1330 | && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ |
3d339ad2 RS |
1331 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ |
1332 | && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000) \ | |
1333 | || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ | |
1334 | && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ | |
1335 | || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ | |
1336 | && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) \ | |
1337 | ||
1338 | #if 0 | |
1339 | /* This should replace the last two (non-pic) lines | |
1340 | except that Sun's assembler does not seem to handle such operands. */ | |
1341 | && (TARGET_68020 ? CONSTANT_ADDRESS_P (XEXP (X, 1)) \ | |
1342 | : (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1343 | && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) | |
1344 | #endif | |
1345 | ||
1346 | ||
1347 | #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ | |
1348 | { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } | |
1349 | ||
875c5a31 RS |
1350 | /* Only labels on dispatch tables are valid for indexing from. */ |
1351 | #define GO_IF_INDEXABLE_BASE(X, ADDR) \ | |
1352 | { rtx temp; \ | |
1353 | if (GET_CODE (X) == LABEL_REF \ | |
1354 | && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ | |
1355 | && GET_CODE (temp) == JUMP_INSN \ | |
1356 | && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ | |
1357 | || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ | |
1358 | goto ADDR; \ | |
22291e2f | 1359 | if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } |
3d339ad2 RS |
1360 | |
1361 | #define GO_IF_INDEXING(X, ADDR) \ | |
1362 | { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ | |
1363 | { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ | |
1364 | if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ | |
1365 | { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } | |
1366 | ||
1367 | #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ | |
1368 | { GO_IF_INDEXING (X, ADDR); \ | |
1369 | if (GET_CODE (X) == PLUS) \ | |
1370 | { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1371 | && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \ | |
1372 | { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ | |
1373 | if (GET_CODE (XEXP (X, 0)) == CONST_INT \ | |
1374 | && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \ | |
1375 | { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } | |
1376 | ||
1377 | #define LEGITIMATE_INDEX_REG_P(X) \ | |
1378 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
1379 | || (GET_CODE (X) == SIGN_EXTEND \ | |
1380 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1381 | && GET_MODE (XEXP (X, 0)) == HImode \ | |
22291e2f JW |
1382 | && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ |
1383 | || (GET_CODE (X) == SUBREG \ | |
1384 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1385 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
3d339ad2 RS |
1386 | |
1387 | #define LEGITIMATE_INDEX_P(X) \ | |
1388 | (LEGITIMATE_INDEX_REG_P (X) \ | |
106bee4b | 1389 | || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \ |
3d339ad2 RS |
1390 | && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ |
1391 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1392 | && (INTVAL (XEXP (X, 1)) == 2 \ | |
1393 | || INTVAL (XEXP (X, 1)) == 4 \ | |
1c4e4dc4 | 1394 | || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200)))) |
3d339ad2 | 1395 | |
04e61bd4 RS |
1396 | /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ |
1397 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1398 | { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ | |
1399 | GO_IF_INDEXED_ADDRESS (X, ADDR); \ | |
1400 | if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ | |
1401 | && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ | |
1402 | && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ | |
1403 | goto ADDR; } | |
1404 | ||
1405 | /* Don't call memory_address_noforce for the address to fetch | |
1406 | the switch offset. This address is ok as it stands (see above), | |
1407 | but memory_address_noforce would alter it. */ | |
1408 | #define PIC_CASE_VECTOR_ADDRESS(index) index | |
3d339ad2 RS |
1409 | \f |
1410 | /* Try machine-dependent ways of modifying an illegitimate address | |
1411 | to be legitimate. If we find one, return the new, valid address. | |
1412 | This macro is used in only one place: `memory_address' in explow.c. | |
1413 | ||
1414 | OLDX is the address as it was before break_out_memory_refs was called. | |
1415 | In some cases it is useful to look at this to decide what needs to be done. | |
1416 | ||
1417 | MODE and WIN are passed so that this macro can use | |
1418 | GO_IF_LEGITIMATE_ADDRESS. | |
1419 | ||
1420 | It is always safe for this macro to do nothing. It exists to recognize | |
1421 | opportunities to optimize the output. | |
1422 | ||
1423 | For the 68000, we handle X+REG by loading X into a register R and | |
1424 | using R+REG. R will go in an address reg and indexing will be used. | |
1425 | However, if REG is a broken-out memory address or multiplication, | |
1426 | nothing needs to be done because REG can certainly go in an address reg. */ | |
1427 | ||
1428 | #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } | |
1429 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1430 | { register int ch = (X) != (OLDX); \ | |
1431 | if (GET_CODE (X) == PLUS) \ | |
1432 | { int copied = 0; \ | |
1433 | if (GET_CODE (XEXP (X, 0)) == MULT) \ | |
1434 | { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ | |
1435 | if (GET_CODE (XEXP (X, 1)) == MULT) \ | |
1436 | { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ | |
1437 | if (ch && GET_CODE (XEXP (X, 1)) == REG \ | |
1438 | && GET_CODE (XEXP (X, 0)) == REG) \ | |
1439 | goto WIN; \ | |
1440 | if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ | |
1441 | if (GET_CODE (XEXP (X, 0)) == REG \ | |
1442 | || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ | |
1443 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1444 | && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ | |
1445 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
1446 | register rtx val = force_operand (XEXP (X, 1), 0); \ | |
1447 | emit_move_insn (temp, val); \ | |
1448 | COPY_ONCE (X); \ | |
1449 | XEXP (X, 1) = temp; \ | |
1450 | goto WIN; } \ | |
1451 | else if (GET_CODE (XEXP (X, 1)) == REG \ | |
1452 | || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ | |
1453 | && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ | |
1454 | && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ | |
1455 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
1456 | register rtx val = force_operand (XEXP (X, 0), 0); \ | |
1457 | emit_move_insn (temp, val); \ | |
1458 | COPY_ONCE (X); \ | |
1459 | XEXP (X, 0) = temp; \ | |
1460 | goto WIN; }}} | |
1461 | ||
1462 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1463 | has an effect that depends on the machine mode it is used for. | |
1464 | On the 68000, only predecrement and postincrement address depend thus | |
1465 | (the amount of decrement or increment being the length of the operand). */ | |
1466 | ||
1467 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1468 | if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL | |
1469 | \f | |
1470 | /* Specify the machine mode that this machine uses | |
1471 | for the index in the tablejump instruction. */ | |
1472 | #define CASE_VECTOR_MODE HImode | |
1473 | ||
1474 | /* Define this if the tablejump instruction expects the table | |
1475 | to contain offsets from the address of the table. | |
1476 | Do not define this if the table should contain absolute addresses. */ | |
1477 | #define CASE_VECTOR_PC_RELATIVE | |
1478 | ||
1479 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1480 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1481 | ||
1482 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1483 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1484 | ||
1485 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1486 | #define DEFAULT_SIGNED_CHAR 1 | |
1487 | ||
1488 | /* Don't cse the address of the function being compiled. */ | |
1489 | #define NO_RECURSIVE_FUNCTION_CSE | |
1490 | ||
1491 | /* Max number of bytes we can move from memory to memory | |
1492 | in one reasonably fast instruction. */ | |
1493 | #define MOVE_MAX 4 | |
1494 | ||
1495 | /* Define this if zero-extension is slow (more than one real instruction). */ | |
1496 | #define SLOW_ZERO_EXTEND | |
1497 | ||
1498 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
1499 | #define SLOW_BYTE_ACCESS 0 | |
1500 | ||
3d339ad2 RS |
1501 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1502 | is done just by pretending it is already truncated. */ | |
1503 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1504 | ||
1505 | /* We assume that the store-condition-codes instructions store 0 for false | |
1506 | and some other value for true. This is the value stored for true. */ | |
1507 | ||
1508 | #define STORE_FLAG_VALUE -1 | |
1509 | ||
1510 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
1511 | #define PROMOTE_PROTOTYPES | |
1512 | ||
1513 | /* Specify the machine mode that pointers have. | |
1514 | After generation of rtl, the compiler makes no further distinction | |
1515 | between pointers and any other objects of this machine mode. */ | |
1516 | #define Pmode SImode | |
1517 | ||
1518 | /* A function address in a call instruction | |
1519 | is a byte address (for indexing purposes) | |
1520 | so give the MEM rtx a byte's mode. */ | |
1521 | #define FUNCTION_MODE QImode | |
1522 | ||
1523 | /* Compute the cost of computing a constant rtl expression RTX | |
1524 | whose rtx-code is CODE. The body of this macro is a portion | |
1525 | of a switch statement. If the code is computed here, | |
1526 | return it with a return statement. Otherwise, break from the switch. */ | |
1527 | ||
3bb22aee | 1528 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
3d339ad2 RS |
1529 | case CONST_INT: \ |
1530 | /* Constant zero is super cheap due to clr instruction. */ \ | |
1531 | if (RTX == const0_rtx) return 0; \ | |
8dbda09a RK |
1532 | /* if ((OUTER_CODE) == SET) */ \ |
1533 | return const_int_cost(RTX); \ | |
3d339ad2 RS |
1534 | case CONST: \ |
1535 | case LABEL_REF: \ | |
1536 | case SYMBOL_REF: \ | |
1537 | return 3; \ | |
1538 | case CONST_DOUBLE: \ | |
1539 | return 5; | |
1540 | ||
1541 | /* Compute the cost of various arithmetic operations. | |
1542 | These are vaguely right for a 68020. */ | |
1543 | /* The costs for long multiply have been adjusted to | |
1544 | work properly in synth_mult on the 68020, | |
1545 | relative to an average of the time for add and the time for shift, | |
1546 | taking away a little more because sometimes move insns are needed. */ | |
3296aff4 | 1547 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */ |
7a13fe96 RK |
1548 | #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13) |
1549 | #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5) | |
3296aff4 | 1550 | #define DIVW_COST (TARGET_68020 ? 27 : 12) |
3d339ad2 | 1551 | |
3bb22aee | 1552 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
3d339ad2 RS |
1553 | case PLUS: \ |
1554 | /* An lea costs about three times as much as a simple add. */ \ | |
1555 | if (GET_MODE (X) == SImode \ | |
8df73827 TG |
1556 | && GET_CODE (XEXP (X, 1)) == REG \ |
1557 | && GET_CODE (XEXP (X, 0)) == MULT \ | |
1558 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1559 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1560 | && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \ | |
1561 | || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \ | |
1562 | || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \ | |
3d339ad2 RS |
1563 | return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \ |
1564 | break; \ | |
1565 | case ASHIFT: \ | |
1566 | case ASHIFTRT: \ | |
7a13fe96 RK |
1567 | case LSHIFTRT: \ |
1568 | if (TARGET_68060) \ | |
1569 | return COSTS_N_INSNS(1); \ | |
3296aff4 TG |
1570 | if (! TARGET_68020) \ |
1571 | { \ | |
1572 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1573 | { \ | |
1574 | if (INTVAL (XEXP (X, 1)) < 16) \ | |
1575 | return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \ | |
1576 | else \ | |
1577 | /* We're using clrw + swap for these cases. */ \ | |
bd2e6d53 | 1578 | return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \ |
3296aff4 TG |
1579 | } \ |
1580 | return COSTS_N_INSNS (10); /* worst case */ \ | |
1581 | } \ | |
3d339ad2 | 1582 | /* A shift by a big integer takes an extra instruction. */ \ |
b4ac57ab RS |
1583 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ |
1584 | && (INTVAL (XEXP (X, 1)) == 16)) \ | |
1585 | return COSTS_N_INSNS (2); /* clrw;swap */ \ | |
3d339ad2 RS |
1586 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ |
1587 | && !(INTVAL (XEXP (X, 1)) > 0 \ | |
1588 | && INTVAL (XEXP (X, 1)) <= 8)) \ | |
1589 | return COSTS_N_INSNS (3); /* lsr #i,dn */ \ | |
1590 | break; \ | |
1591 | case MULT: \ | |
3296aff4 TG |
1592 | if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \ |
1593 | || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \ | |
1594 | && GET_MODE (X) == SImode) \ | |
1595 | return COSTS_N_INSNS (MULW_COST); \ | |
5d195441 | 1596 | if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ |
9fd3fbd0 | 1597 | return COSTS_N_INSNS (MULW_COST); \ |
3d339ad2 | 1598 | else \ |
9fd3fbd0 | 1599 | return COSTS_N_INSNS (MULL_COST); \ |
3d339ad2 RS |
1600 | case DIV: \ |
1601 | case UDIV: \ | |
1602 | case MOD: \ | |
1603 | case UMOD: \ | |
1604 | if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ | |
3296aff4 | 1605 | return COSTS_N_INSNS (DIVW_COST); /* div.w */ \ |
3d339ad2 RS |
1606 | return COSTS_N_INSNS (43); /* div.l */ |
1607 | \f | |
1608 | /* Tell final.c how to eliminate redundant test instructions. */ | |
1609 | ||
1610 | /* Here we define machine-dependent flags and fields in cc_status | |
1611 | (see `conditions.h'). */ | |
1612 | ||
1613 | /* Set if the cc value is actually in the 68881, so a floating point | |
1614 | conditional branch must be output. */ | |
1615 | #define CC_IN_68881 04000 | |
1616 | ||
1617 | /* Store in cc_status the expressions that the condition codes will | |
1618 | describe after execution of an instruction whose pattern is EXP. | |
1619 | Do not alter them if the instruction would not alter the cc's. */ | |
1620 | ||
1621 | /* On the 68000, all the insns to store in an address register fail to | |
1622 | set the cc's. However, in some cases these instructions can make it | |
1623 | possibly invalid to use the saved cc's. In those cases we clear out | |
1624 | some or all of the saved cc's so they won't be used. */ | |
1625 | ||
1626 | #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) | |
1627 | ||
1628 | #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ | |
1629 | { if (cc_prev_status.flags & CC_IN_68881) \ | |
1630 | return FLOAT; \ | |
1631 | if (cc_prev_status.flags & CC_NO_OVERFLOW) \ | |
1632 | return NO_OV; \ | |
1633 | return NORMAL; } | |
1634 | \f | |
1635 | /* Control the assembler format that we output. */ | |
1636 | ||
1637 | /* Output at beginning of assembler file. */ | |
1638 | ||
1639 | #define ASM_FILE_START(FILE) \ | |
1640 | fprintf (FILE, "#NO_APP\n"); | |
1641 | ||
1642 | /* Output to assembler file text saying following lines | |
1643 | may contain character constants, extra white space, comments, etc. */ | |
1644 | ||
1645 | #define ASM_APP_ON "#APP\n" | |
1646 | ||
1647 | /* Output to assembler file text saying following lines | |
1648 | no longer contain unusual constructs. */ | |
1649 | ||
1650 | #define ASM_APP_OFF "#NO_APP\n" | |
1651 | ||
1652 | /* Output before read-only data. */ | |
1653 | ||
1654 | #define TEXT_SECTION_ASM_OP ".text" | |
1655 | ||
1656 | /* Output before writable data. */ | |
1657 | ||
1658 | #define DATA_SECTION_ASM_OP ".data" | |
1659 | ||
1660 | /* Here are four prefixes that are used by asm_fprintf to | |
1661 | facilitate customization for alternate assembler syntaxes. | |
1662 | Machines with no likelihood of an alternate syntax need not | |
1663 | define these and need not use asm_fprintf. */ | |
1664 | ||
1665 | /* The prefix for register names. Note that REGISTER_NAMES | |
1666 | is supposed to include this prefix. */ | |
1667 | ||
1668 | #define REGISTER_PREFIX "" | |
1669 | ||
1670 | /* The prefix for local labels. You should be able to define this as | |
1671 | an empty string, or any arbitrary string (such as ".", ".L%", etc) | |
1672 | without having to make any other changes to account for the specific | |
1673 | definition. Note it is a string literal, not interpreted by printf | |
1674 | and friends. */ | |
1675 | ||
1676 | #define LOCAL_LABEL_PREFIX "" | |
1677 | ||
1678 | /* The prefix to add to user-visible assembler symbols. */ | |
1679 | ||
1680 | #define USER_LABEL_PREFIX "_" | |
1681 | ||
1682 | /* The prefix for immediate operands. */ | |
1683 | ||
1684 | #define IMMEDIATE_PREFIX "#" | |
1685 | ||
1686 | /* How to refer to registers in assembler output. | |
1687 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1688 | ||
1689 | #ifndef SUPPORT_SUN_FPA | |
1690 | ||
1691 | #define REGISTER_NAMES \ | |
1692 | {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ | |
1693 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ | |
1694 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } | |
1695 | ||
1696 | #else /* SUPPORTED_SUN_FPA */ | |
1697 | ||
1698 | #define REGISTER_NAMES \ | |
1699 | {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ | |
1700 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ | |
1701 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \ | |
1702 | "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \ | |
1703 | "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \ | |
1704 | "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \ | |
1705 | "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" } | |
1706 | ||
1707 | #endif /* defined SUPPORT_SUN_FPA */ | |
1708 | ||
1709 | /* How to renumber registers for dbx and gdb. | |
1710 | On the Sun-3, the floating point registers have numbers | |
1711 | 18 to 25, not 16 to 23 as they do in the compiler. */ | |
1712 | ||
1713 | #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) | |
1714 | ||
1715 | /* This is how to output the definition of a user-level label named NAME, | |
1716 | such as the label on a static function or variable NAME. */ | |
1717 | ||
1718 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1719 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1720 | ||
1721 | /* This is how to output a command to make the user-level label named NAME | |
1722 | defined for reference from other files. */ | |
1723 | ||
9fd3fbd0 | 1724 | #define GLOBAL_ASM_OP ".globl" |
3d339ad2 | 1725 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ |
9fd3fbd0 RS |
1726 | do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \ |
1727 | assemble_name (FILE, NAME); \ | |
1728 | fputs ("\n", FILE);} while (0) | |
3d339ad2 RS |
1729 | |
1730 | /* This is how to output a reference to a user-level label named NAME. | |
1731 | `assemble_name' uses this. */ | |
1732 | ||
1733 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
338818c7 | 1734 | asm_fprintf (FILE, "%0U%s", NAME) |
3d339ad2 RS |
1735 | |
1736 | /* This is how to output an internal numbered label where | |
1737 | PREFIX is the class of label and NUM is the number within the class. */ | |
1738 | ||
1739 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
338818c7 | 1740 | asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM) |
3d339ad2 RS |
1741 | |
1742 | /* This is how to store into the string LABEL | |
1743 | the symbol_ref name of an internal numbered label where | |
1744 | PREFIX is the class of label and NUM is the number within the class. | |
1745 | This is suitable for output with `assemble_name'. */ | |
1746 | ||
1747 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
1748 | sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM) | |
1749 | ||
f6ba6a91 RS |
1750 | /* This is how to output a `long double' extended real constant. */ |
1751 | ||
1752 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ | |
1753 | do { long l[3]; \ | |
1754 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ | |
1755 | if (sizeof (int) == sizeof (long)) \ | |
1756 | fprintf (FILE, "\t.long 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \ | |
1757 | else \ | |
1758 | fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \ | |
1759 | } while (0) | |
1760 | ||
3d339ad2 RS |
1761 | /* This is how to output an assembler line defining a `double' constant. */ |
1762 | ||
f6ba6a91 RS |
1763 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
1764 | do { char dstr[30]; \ | |
1765 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ | |
1766 | fprintf (FILE, "\t.double 0r%s\n", dstr); \ | |
1767 | } while (0) | |
3d339ad2 RS |
1768 | |
1769 | /* This is how to output an assembler line defining a `float' constant. */ | |
1770 | ||
f6ba6a91 RS |
1771 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
1772 | do { long l; \ | |
1773 | REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ | |
1774 | if (sizeof (int) == sizeof (long)) \ | |
1775 | fprintf (FILE, "\t.long 0x%x\n", l); \ | |
1776 | else \ | |
1777 | fprintf (FILE, "\t.long 0x%lx\n", l); \ | |
3d339ad2 RS |
1778 | } while (0) |
1779 | ||
3d339ad2 RS |
1780 | /* This is how to output an assembler line defining an `int' constant. */ |
1781 | ||
1782 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
1783 | ( fprintf (FILE, "\t.long "), \ | |
1784 | output_addr_const (FILE, (VALUE)), \ | |
1785 | fprintf (FILE, "\n")) | |
1786 | ||
1787 | /* Likewise for `char' and `short' constants. */ | |
1788 | ||
1789 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
1790 | ( fprintf (FILE, "\t.word "), \ | |
1791 | output_addr_const (FILE, (VALUE)), \ | |
1792 | fprintf (FILE, "\n")) | |
1793 | ||
1794 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
1795 | ( fprintf (FILE, "\t.byte "), \ | |
1796 | output_addr_const (FILE, (VALUE)), \ | |
1797 | fprintf (FILE, "\n")) | |
1798 | ||
1799 | /* This is how to output an assembler line for a numeric constant byte. */ | |
1800 | ||
1801 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
1802 | fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) | |
1803 | ||
1804 | /* This is how to output an insn to push a register on the stack. | |
1805 | It need not be very fast code. */ | |
1806 | ||
1807 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
1808 | asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) | |
1809 | ||
1810 | /* This is how to output an insn to pop a register from the stack. | |
1811 | It need not be very fast code. */ | |
1812 | ||
1813 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
1814 | asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) | |
1815 | ||
1816 | /* This is how to output an element of a case-vector that is absolute. | |
1817 | (The 68000 does not use such vectors, | |
1818 | but we must define this macro anyway.) */ | |
1819 | ||
1820 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1821 | asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) | |
1822 | ||
1823 | /* This is how to output an element of a case-vector that is relative. */ | |
1824 | ||
1825 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ | |
1826 | asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) | |
1827 | ||
1828 | /* This is how to output an assembler line | |
1829 | that says to advance the location counter | |
1830 | to a multiple of 2**LOG bytes. */ | |
1831 | ||
b4ac57ab RS |
1832 | /* We don't have a way to align to more than a two-byte boundary, so do the |
1833 | best we can and don't complain. */ | |
3d339ad2 | 1834 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ |
b4ac57ab RS |
1835 | if ((LOG) >= 1) \ |
1836 | fprintf (FILE, "\t.even\n"); | |
3d339ad2 RS |
1837 | |
1838 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1839 | fprintf (FILE, "\t.skip %u\n", (SIZE)) | |
1840 | ||
1841 | /* This says how to output an assembler line | |
1842 | to define a global common symbol. */ | |
1843 | ||
1844 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1845 | ( fputs (".comm ", (FILE)), \ | |
1846 | assemble_name ((FILE), (NAME)), \ | |
1847 | fprintf ((FILE), ",%u\n", (ROUNDED))) | |
1848 | ||
1849 | /* This says how to output an assembler line | |
1850 | to define a local common symbol. */ | |
1851 | ||
1852 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1853 | ( fputs (".lcomm ", (FILE)), \ | |
1854 | assemble_name ((FILE), (NAME)), \ | |
1855 | fprintf ((FILE), ",%u\n", (ROUNDED))) | |
1856 | ||
1857 | /* Store in OUTPUT a string (made with alloca) containing | |
1858 | an assembler-name for a local static variable named NAME. | |
1859 | LABELNO is an integer which is different for each call. */ | |
1860 | ||
1861 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1862 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
1863 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
1864 | ||
1865 | /* Define the parentheses used to group arithmetic operations | |
1866 | in assembler code. */ | |
1867 | ||
1868 | #define ASM_OPEN_PAREN "(" | |
1869 | #define ASM_CLOSE_PAREN ")" | |
1870 | ||
1871 | /* Define results of standard character escape sequences. */ | |
1872 | #define TARGET_BELL 007 | |
1873 | #define TARGET_BS 010 | |
1874 | #define TARGET_TAB 011 | |
1875 | #define TARGET_NEWLINE 012 | |
1876 | #define TARGET_VT 013 | |
1877 | #define TARGET_FF 014 | |
1878 | #define TARGET_CR 015 | |
1879 | ||
1880 | /* Output a float value (represented as a C double) as an immediate operand. | |
1881 | This macro is a 68k-specific macro. */ | |
f6ba6a91 RS |
1882 | |
1883 | #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ | |
1884 | do { \ | |
1885 | if (CODE == 'f') \ | |
1886 | { \ | |
1887 | char dstr[30]; \ | |
1888 | REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ | |
1889 | asm_fprintf ((FILE), "%I0r%s", dstr); \ | |
1890 | } \ | |
1891 | else \ | |
1892 | { \ | |
1893 | long l; \ | |
1894 | REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ | |
1895 | if (sizeof (int) == sizeof (long)) \ | |
1896 | asm_fprintf ((FILE), "%I0x%x", l); \ | |
1897 | else \ | |
1898 | asm_fprintf ((FILE), "%I0x%lx", l); \ | |
1899 | } \ | |
1900 | } while (0) | |
3d339ad2 RS |
1901 | |
1902 | /* Output a double value (represented as a C double) as an immediate operand. | |
1903 | This macro is a 68k-specific macro. */ | |
1904 | #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ | |
f6ba6a91 RS |
1905 | do { char dstr[30]; \ |
1906 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ | |
1907 | asm_fprintf (FILE, "%I0r%s", dstr); \ | |
1908 | } while (0) | |
1909 | ||
1910 | /* Note, long double immediate operands are not actually | |
1911 | generated by m68k.md. */ | |
1912 | #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ | |
1913 | do { char dstr[30]; \ | |
1914 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ | |
1915 | asm_fprintf (FILE, "%I0r%s", dstr); \ | |
1916 | } while (0) | |
3d339ad2 RS |
1917 | |
1918 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1919 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1920 | For `%' followed by punctuation, CODE is the punctuation and X is null. | |
1921 | ||
1922 | On the 68000, we use several CODE characters: | |
1923 | '.' for dot needed in Motorola-style opcode names. | |
1924 | '-' for an operand pushing on the stack: | |
1925 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
1926 | '+' for an operand pushing on the stack: | |
1927 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
1928 | '@' for a reference to the top word on the stack: | |
1929 | sp@, (sp) or (%sp) depending on the style of syntax. | |
1930 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
1931 | but & in SGS syntax). | |
7c129456 | 1932 | '!' for the fpcr register (used in some float-to-fixed conversions). |
3d339ad2 RS |
1933 | '$' for the letter `s' in an op code, but only on the 68040. |
1934 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 1935 | '/' for register prefix needed by longlong.h. |
3d339ad2 RS |
1936 | |
1937 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
1938 | 'd' to force memory addressing to be absolute, not relative. | |
1939 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
1940 | 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather | |
1941 | than directly). Second part of 'y' below. | |
1942 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), | |
1943 | or print pair of registers as rx:ry. | |
1944 | 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs | |
1945 | CONST_DOUBLE's as SunFPA constant RAM registers if | |
1946 | possible, so it should not be used except for the SunFPA. */ | |
1947 | ||
1948 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
1949 | ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ | |
1950 | || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ | |
2ac5f14a | 1951 | || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') |
3d339ad2 | 1952 | |
3d339ad2 RS |
1953 | /* A C compound statement to output to stdio stream STREAM the |
1954 | assembler syntax for an instruction operand X. X is an RTL | |
1955 | expression. | |
1956 | ||
1957 | CODE is a value that can be used to specify one of several ways | |
1958 | of printing the operand. It is used when identical operands | |
1959 | must be printed differently depending on the context. CODE | |
1960 | comes from the `%' specification that was used to request | |
1961 | printing of the operand. If the specification was just `%DIGIT' | |
1962 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
1963 | is the ASCII code for LTR. | |
1964 | ||
1965 | If X is a register, this macro should print the register's name. | |
1966 | The names can be found in an array `reg_names' whose type is | |
1967 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
1968 | ||
1969 | When the machine description has a specification `%PUNCT' (a `%' | |
1970 | followed by a punctuation character), this macro is called with | |
1971 | a null pointer for X and the punctuation character for CODE. | |
1972 | ||
1973 | See m68k.c for the m68k specific codes. */ | |
1974 | ||
1975 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
1976 | ||
1977 | /* A C compound statement to output to stdio stream STREAM the | |
1978 | assembler syntax for an instruction operand that is a memory | |
1979 | reference whose address is ADDR. ADDR is an RTL expression. | |
1980 | ||
1981 | On some machines, the syntax for a symbolic address depends on | |
1982 | the section that the address refers to. On these machines, | |
1983 | define the macro `ENCODE_SECTION_INFO' to store the information | |
1984 | into the `symbol_ref', and then check for it here. */ | |
1985 | ||
1986 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
1987 | ||
1988 | ||
e72498e1 JB |
1989 | /* Definitions for generating bytecode */ |
1990 | ||
1991 | /* Just so it's known this target is supported by the bytecode generator. | |
1992 | If this define isn't found anywhere in the target config files, then | |
1993 | dummy stubs are supplied by bytecode.h, and any attempt to use | |
1994 | -fbytecode will result in an error message. */ | |
1995 | ||
1996 | #define TARGET_SUPPORTS_BYTECODE | |
1997 | ||
1998 | /* Minimal segment alignment within sections is 8 units. */ | |
1999 | #define MACHINE_SEG_ALIGN 3 | |
2000 | ||
2001 | /* Integer alignment is two units. */ | |
2002 | #define INT_ALIGN 2 | |
2003 | ||
2004 | /* Pointer alignment is eight units. */ | |
2005 | #define PTR_ALIGN 3 | |
2006 | ||
2007 | /* Global symbols begin with `_' */ | |
2008 | #define NAMES_HAVE_UNDERSCORES | |
2009 | ||
2010 | /* BC_xxx below are similar to their ASM_xxx counterparts above. */ | |
2011 | #define BC_GLOBALIZE_LABEL(FP, NAME) bc_globalize_label(NAME) | |
2012 | ||
2013 | #define BC_OUTPUT_COMMON(FP, NAME, SIZE, ROUNDED) \ | |
2014 | do { bc_emit_common(NAME, ROUNDED); bc_globalize_label(NAME); } while (0) | |
2015 | ||
f3d91607 DE |
2016 | #define BC_OUTPUT_BSS(FP, NAME, SIZE, ROUNDED) \ |
2017 | do { bc_data (); bc_emit_labeldef(NAME); bc_emit_skip (SIZE); } while (0) | |
2018 | ||
e72498e1 JB |
2019 | #define BC_OUTPUT_LOCAL(FP, NAME, SIZE, ROUNDED) \ |
2020 | bc_emit_common(NAME, ROUNDED) | |
2021 | ||
2022 | #define BC_OUTPUT_ALIGN(FP, ALIGN) bc_align(ALIGN) | |
2023 | ||
2024 | #define BC_OUTPUT_LABEL(FP, NAME) bc_emit_labeldef(NAME) | |
2025 | ||
2026 | #define BC_OUTPUT_SKIP(FP, SIZE) bc_emit_skip(SIZE) | |
2027 | ||
2028 | #define BC_OUTPUT_LABELREF(FP, NAME) \ | |
2029 | do { \ | |
2030 | char *foo = (char *) xmalloc(strlen(NAME) + 2); \ | |
2031 | strcpy(foo, "_"); \ | |
2032 | strcat(foo, NAME); \ | |
2033 | bc_emit_labelref (foo); \ | |
2034 | free (foo); \ | |
2035 | } while (0) | |
2036 | ||
2037 | #define BC_OUTPUT_FLOAT(FP, VAL) \ | |
2038 | do { \ | |
2039 | float F = VAL; \ | |
2040 | bc_emit ((char *) &F, sizeof F); \ | |
2041 | } while (0) | |
2042 | ||
2043 | #define BC_OUTPUT_DOUBLE(FP, VAL) \ | |
2044 | do { \ | |
2045 | double D = VAL; \ | |
2046 | bc_emit ((char *) &D, sizeof D); \ | |
2047 | } while (0) | |
2048 | ||
2049 | #define BC_OUTPUT_BYTE(FP, VAL) \ | |
2050 | do { \ | |
2051 | char C = VAL; \ | |
2052 | bc_emit (&C, 1); \ | |
2053 | } while (0) | |
2054 | ||
2055 | ||
2056 | #define BC_OUTPUT_FILE ASM_OUTPUT_FILE | |
2057 | #define BC_OUTPUT_ASCII ASM_OUTPUT_ASCII | |
2058 | #define BC_OUTPUT_IDENT ASM_OUTPUT_IDENT | |
2059 | ||
2060 | /* Same as XSTR, but for bytecode */ | |
2061 | #define BCXSTR(RTX) ((RTX)->bc_label) | |
2062 | ||
2063 | ||
2064 | /* Flush bytecode buffer onto file */ | |
2065 | #define BC_WRITE_FILE(FP) \ | |
2066 | { \ | |
2067 | fprintf (FP, ".text\n"); \ | |
2068 | bc_seg_write (bc_text_seg, FP); \ | |
2069 | fprintf(FP, "\n.data\n"); \ | |
2070 | bc_seg_write (bc_data_seg, FP); \ | |
2071 | bc_sym_write (FP); /* do .globl, .bss, etc. */ \ | |
2072 | } | |
2073 | ||
2074 | /* Write one symbol */ | |
2075 | #define BC_WRITE_SEGSYM(SEGSYM, FP) \ | |
2076 | { \ | |
2077 | prsym (FP, (SEGSYM)->sym->name); \ | |
2078 | fprintf (FP, ":\n"); \ | |
2079 | } | |
2080 | ||
2081 | ||
2082 | /* Write one reloc entry */ | |
2083 | #define BC_WRITE_RELOC_ENTRY(SEGRELOC, FP, OFFSET) \ | |
2084 | { \ | |
2085 | fprintf (FP, "\t.long "); \ | |
2086 | prsym (FP, (SEGRELOC)->sym->name); \ | |
2087 | fprintf (FP, " + %d\n", OFFSET); \ | |
2088 | } | |
2089 | ||
2090 | /* Start new line of bytecodes */ | |
2091 | #define BC_START_BYTECODE_LINE(FP) \ | |
2092 | { \ | |
2093 | fprintf (FP, "\t.byte"); \ | |
2094 | } | |
2095 | ||
2096 | /* Write one bytecode */ | |
2097 | #define BC_WRITE_BYTECODE(SEP, VAL, FP) \ | |
2098 | { \ | |
2099 | fprintf (FP, "%c0x%02X", (SEP), (VAL) & 0xff); \ | |
2100 | } | |
2101 | ||
2102 | /* Write one bytecode RTL entry */ | |
2103 | #define BC_WRITE_RTL(R, FP) \ | |
2104 | { \ | |
2105 | fprintf (FP, "%s+%d/0x%08X\n", (R)->label, (R)->offset, (R)->bc_label); \ | |
2106 | } | |
2107 | ||
2108 | ||
2109 | /* Emit function entry trampoline */ | |
2110 | #define BC_EMIT_TRAMPOLINE(TRAMPSEG, CALLINFO) \ | |
2111 | { \ | |
2112 | short insn; \ | |
2113 | \ | |
2114 | /* Push a reference to the callinfo structure. */ \ | |
2115 | insn = 0x4879; /* pea xxx.L */ \ | |
2116 | seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ | |
2117 | seg_refsym (TRAMPSEG, CALLINFO, 0); \ | |
2118 | \ | |
2119 | /* Call __interp, pop arguments, and return. */ \ | |
2120 | insn = 0x4eb9; /* jsr xxx.L */ \ | |
2121 | seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ | |
2122 | seg_refsym (TRAMPSEG, "__callint", 0); \ | |
2123 | insn = 0x588f; /* addql #4, sp */ \ | |
2124 | seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ | |
2125 | insn = 0x4e75; /* rts */ \ | |
2126 | seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ | |
2127 | } | |
2128 | ||
2129 | ||
2130 | ||
2131 | #if 0 | |
2132 | #define VALIDATE_STACK() if (stack_depth < 0) abort (); | |
2133 | #else | |
2134 | #if 0 | |
2135 | #define VALIDATE_STACK() \ | |
2136 | fprintf (stderr, " %%%d%%", stack_depth); | |
2137 | #endif | |
2138 | #endif | |
2139 | ||
3d339ad2 RS |
2140 | /* Define functions defined in aux-output.c and used in templates. */ |
2141 | ||
8dbda09a | 2142 | extern char *output_move_const_into_data_reg (); |
cab70741 | 2143 | extern char *output_move_simode_const (); |
6901b620 RK |
2144 | extern char *output_move_simode (); |
2145 | extern char *output_move_himode (); | |
2146 | extern char *output_move_qimode (); | |
d96b2631 RK |
2147 | extern char *output_move_stricthi (); |
2148 | extern char *output_move_strictqi (); | |
3d339ad2 RS |
2149 | extern char *output_move_double (); |
2150 | extern char *output_move_const_single (); | |
2151 | extern char *output_move_const_double (); | |
2152 | extern char *output_btst (); | |
71380ac6 | 2153 | extern char *output_scc_di (); |
dfcce277 | 2154 | extern char *output_addsi3 (); |
9e62c7f2 RK |
2155 | |
2156 | /* Variables in m68k.c */ | |
2157 | extern char *m68k_align_loops_string; | |
2158 | extern char *m68k_align_jumps_string; | |
2159 | extern char *m68k_align_funcs_string; | |
2160 | extern int m68k_align_loops; | |
2161 | extern int m68k_align_jumps; | |
2162 | extern int m68k_align_funcs; | |
2b3600ac | 2163 | extern int m68k_last_compare_had_fp_operands; |
9e62c7f2 | 2164 | |
3d339ad2 RS |
2165 | \f |
2166 | /* | |
2167 | Local variables: | |
2168 | version-control: t | |
2169 | End: | |
2170 | */ |