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cf011243 AO |
1 | /* Definitions of target machine for GNU compiler. |
2 | Sun 68000/68020 version. | |
3 | Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, | |
4 | 2000, 2001 Free Software Foundation, Inc. | |
25a1b918 | 5 | |
3d339ad2 RS |
6 | This file is part of GNU CC. |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
0e29e3c9 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
3d339ad2 RS |
22 | |
23 | ||
24 | /* Note that some other tm.h files include this one and then override | |
25 | many of the definitions that relate to assembler syntax. */ | |
26 | ||
27 | ||
28 | /* Names to predefine in the preprocessor for this target machine. */ | |
29 | ||
30 | /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */ | |
31 | ||
32 | /* Print subsidiary information on the compiler version in use. */ | |
33 | #ifdef MOTOROLA | |
34 | #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)"); | |
35 | #else | |
36 | #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)"); | |
37 | #endif | |
38 | ||
39 | /* Define SUPPORT_SUN_FPA to include support for generating code for | |
40 | the Sun Floating Point Accelerator, an optional product for Sun 3 | |
41 | machines. By default, it is not defined. Avoid defining it unless | |
42 | you need to output code for the Sun3+FPA architecture, as it has the | |
43 | effect of slowing down the register set operations in hard-reg-set.h | |
44 | (total number of registers will exceed number of bits in a long, | |
45 | if defined, causing the set operations to expand to loops). | |
46 | SUPPORT_SUN_FPA is typically defined in sun3.h. */ | |
47 | ||
48 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
49 | ||
50 | extern int target_flags; | |
51 | ||
52 | /* Macros used in the machine description to test the flags. */ | |
53 | ||
54 | /* Compile for a 68020 (not a 68000 or 68010). */ | |
7a1b98a9 RK |
55 | #define MASK_68020 1 |
56 | #define TARGET_68020 (target_flags & MASK_68020) | |
3d339ad2 RS |
57 | |
58 | /* Compile 68881 insns for floating point (not library calls). */ | |
7a1b98a9 RK |
59 | #define MASK_68881 2 |
60 | #define TARGET_68881 (target_flags & MASK_68881) | |
3d339ad2 RS |
61 | |
62 | /* Compile using 68020 bitfield insns. */ | |
7a1b98a9 RK |
63 | #define MASK_BITFIELD 4 |
64 | #define TARGET_BITFIELD (target_flags & MASK_BITFIELD) | |
3d339ad2 RS |
65 | |
66 | /* Compile using rtd insn calling sequence. | |
67 | This will not work unless you use prototypes at least | |
68 | for all functions that can take varying numbers of args. */ | |
7a1b98a9 RK |
69 | #define MASK_RTD 8 |
70 | #define TARGET_RTD (target_flags & MASK_RTD) | |
3d339ad2 RS |
71 | |
72 | /* Compile passing first two args in regs 0 and 1. | |
73 | This exists only to test compiler features that will | |
74 | be needed for RISC chips. It is not usable | |
75 | and is not intended to be usable on this cpu. */ | |
7a1b98a9 RK |
76 | #define MASK_REGPARM 16 |
77 | #define TARGET_REGPARM (target_flags & MASK_REGPARM) | |
3d339ad2 RS |
78 | |
79 | /* Compile with 16-bit `int'. */ | |
7a1b98a9 RK |
80 | #define MASK_SHORT 32 |
81 | #define TARGET_SHORT (target_flags & MASK_SHORT) | |
3d339ad2 RS |
82 | |
83 | /* Compile with special insns for Sun FPA. */ | |
7a1b98a9 RK |
84 | #define MASK_FPA 64 |
85 | #define TARGET_FPA (target_flags & MASK_FPA) | |
3d339ad2 RS |
86 | |
87 | /* Compile (actually, link) for Sun SKY board. */ | |
7a1b98a9 RK |
88 | #define MASK_SKY 128 |
89 | #define TARGET_SKY (target_flags & MASK_SKY) | |
3d339ad2 | 90 | |
b4281273 RS |
91 | /* Optimize for 68040, but still allow execution on 68020 |
92 | (-m68020-40 or -m68040). | |
b4ac57ab | 93 | The 68040 will execute all 68030 and 68881/2 instructions, but some |
3d339ad2 RS |
94 | of them must be emulated in software by the OS. When TARGET_68040 is |
95 | turned on, these instructions won't be used. This code will still | |
96 | run on a 68030 and 68881/2. */ | |
35bcca7b | 97 | #define MASK_68040 256 |
7a1b98a9 | 98 | #define TARGET_68040 (target_flags & MASK_68040) |
3d339ad2 | 99 | |
30e6bc63 | 100 | /* Use the 68040-only fp instructions (-m68040 or -m68060). */ |
7a1b98a9 RK |
101 | #define MASK_68040_ONLY 512 |
102 | #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY) | |
3d339ad2 | 103 | |
30e6bc63 | 104 | /* Optimize for 68060, but still allow execution on 68020 |
35bcca7b | 105 | (-m68020-60 or -m68060). |
30e6bc63 RK |
106 | The 68060 will execute all 68030 and 68881/2 instructions, but some |
107 | of them must be emulated in software by the OS. When TARGET_68060 is | |
108 | turned on, these instructions won't be used. This code will still | |
109 | run on a 68030 and 68881/2. */ | |
7a1b98a9 RK |
110 | #define MASK_68060 1024 |
111 | #define TARGET_68060 (target_flags & MASK_68060) | |
30e6bc63 | 112 | |
106bee4b RK |
113 | /* Compile for mcf5200 */ |
114 | #define MASK_5200 2048 | |
115 | #define TARGET_5200 (target_flags & MASK_5200) | |
116 | ||
dcd13066 RK |
117 | /* Align ints to a word boundary. This breaks compatibility with the |
118 | published ABI's for structures containing ints, but produces faster | |
119 | code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire). | |
120 | It's required for coldfire cpus without a misalignment module. */ | |
121 | #define MASK_ALIGN_INT 4096 | |
122 | #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT) | |
123 | ||
b686ee30 RK |
124 | /* Compile for a CPU32 */ |
125 | /* A 68020 without bitfields is a good heuristic for a CPU32 */ | |
126 | #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD) | |
127 | ||
2c8ec431 DL |
128 | /* Use PC-relative addressing modes (without using a global offset table). |
129 | The m68000 supports 16-bit PC-relative addressing. | |
130 | The m68020 supports 32-bit PC-relative addressing | |
131 | (using outer displacements). | |
132 | ||
133 | Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are | |
134 | treated as all containing an implicit PC-relative component, and hence | |
135 | cannot be used directly as addresses for memory writes. See the comments | |
136 | in m68k.c for more information. */ | |
b71733d5 | 137 | #define MASK_PCREL 8192 |
2c8ec431 DL |
138 | #define TARGET_PCREL (target_flags & MASK_PCREL) |
139 | ||
b71733d5 GM |
140 | /* Relax strict alignment. */ |
141 | #define MASK_NO_STRICT_ALIGNMENT 16384 | |
142 | #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT) | |
143 | ||
3d339ad2 RS |
144 | /* Macro to define tables used to set the flags. |
145 | This is a list in braces of pairs in braces, | |
146 | each pair being { "NAME", VALUE } | |
147 | where VALUE is the bits to set or minus the bits to clear. | |
148 | An empty string NAME is used to identify the default VALUE. */ | |
149 | ||
150 | #define TARGET_SWITCHES \ | |
35bcca7b RK |
151 | { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \ |
152 | { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \ | |
7a1b98a9 RK |
153 | { "68020", (MASK_68020|MASK_BITFIELD)}, \ |
154 | { "c68020", (MASK_68020|MASK_BITFIELD)}, \ | |
35bcca7b | 155 | { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
239e68f6 | 156 | |MASK_68020|MASK_BITFIELD|MASK_68881)}, \ |
35bcca7b | 157 | { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
239e68f6 | 158 | |MASK_68020|MASK_BITFIELD|MASK_68881)}, \ |
d6539615 | 159 | { "bitfield", MASK_BITFIELD}, \ |
7a1b98a9 RK |
160 | { "nobitfield", - MASK_BITFIELD}, \ |
161 | { "rtd", MASK_RTD}, \ | |
162 | { "nortd", - MASK_RTD}, \ | |
163 | { "short", MASK_SHORT}, \ | |
164 | { "noshort", - MASK_SHORT}, \ | |
d6539615 | 165 | { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \ |
7a1b98a9 RK |
166 | { "fpa", MASK_FPA}, \ |
167 | { "nofpa", - MASK_FPA}, \ | |
d6539615 | 168 | { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881)}, \ |
7a1b98a9 RK |
169 | { "sky", MASK_SKY}, \ |
170 | { "nosky", - MASK_SKY}, \ | |
f5963e61 | 171 | { "68881", - (MASK_FPA|MASK_SKY)}, \ |
d6539615 RK |
172 | { "68881", MASK_68881}, \ |
173 | { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \ | |
e8d16166 | 174 | { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY)}, \ |
35bcca7b | 175 | { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040)}, \ |
8309458a AS |
176 | { "68020-60", -(MASK_5200|MASK_68040_ONLY)}, \ |
177 | { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \ | |
178 | |MASK_68060)}, \ | |
35bcca7b | 179 | { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \ |
7a1b98a9 | 180 | { "68030", (MASK_68020|MASK_BITFIELD)}, \ |
35bcca7b RK |
181 | { "68040", - (MASK_5200|MASK_68060)}, \ |
182 | { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \ | |
183 | |MASK_68040_ONLY|MASK_68040)}, \ | |
184 | { "68060", - (MASK_5200|MASK_68040)}, \ | |
7a1b98a9 RK |
185 | { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \ |
186 | |MASK_68040_ONLY|MASK_68060)}, \ | |
e8d16166 KI |
187 | { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ |
188 | |MASK_BITFIELD|MASK_68881)}, \ | |
106bee4b | 189 | { "5200", (MASK_5200)}, \ |
7a1b98a9 RK |
190 | { "68851", 0}, \ |
191 | { "no-68851", 0}, \ | |
239e68f6 | 192 | { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
624cc15e | 193 | |MASK_68020|MASK_BITFIELD|MASK_68881)}, \ |
239e68f6 | 194 | { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
74cf1c6d | 195 | |MASK_BITFIELD|MASK_68881)}, \ |
bae37e71 | 196 | { "68332", MASK_68020}, \ |
239e68f6 | 197 | { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ |
74cf1c6d | 198 | |MASK_BITFIELD|MASK_68881)}, \ |
212198f4 | 199 | { "cpu32", MASK_68020}, \ |
dcd13066 RK |
200 | { "align-int", MASK_ALIGN_INT }, \ |
201 | { "no-align-int", -MASK_ALIGN_INT }, \ | |
2c8ec431 | 202 | { "pcrel", MASK_PCREL}, \ |
b71733d5 GM |
203 | { "strict-align", -MASK_NO_STRICT_ALIGNMENT}, \ |
204 | { "no-strict-align", MASK_NO_STRICT_ALIGNMENT}, \ | |
7a1b98a9 | 205 | SUBTARGET_SWITCHES \ |
3d339ad2 RS |
206 | { "", TARGET_DEFAULT}} |
207 | /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */ | |
882ed710 | 208 | |
9e62c7f2 RK |
209 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
210 | command options that have values. Its definition is an | |
211 | initializer with a subgrouping for each command option. | |
212 | ||
213 | Each subgrouping contains a string constant, that defines the | |
214 | fixed part of the option name, and the address of a variable. The | |
215 | variable, type `char *', is set to the variable part of the given | |
216 | option if the fixed part matches. The actual option name is made | |
217 | by appending `-m' to the specified name. */ | |
218 | #define TARGET_OPTIONS \ | |
219 | { { "align-loops=", &m68k_align_loops_string }, \ | |
220 | { "align-jumps=", &m68k_align_jumps_string }, \ | |
221 | { "align-functions=", &m68k_align_funcs_string }, \ | |
222 | SUBTARGET_OPTIONS \ | |
223 | } | |
224 | ||
225 | /* Sometimes certain combinations of command options do not make | |
226 | sense on a particular target machine. You can define a macro | |
227 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
228 | defined, is executed once just after all the command options have | |
229 | been parsed. | |
230 | ||
231 | Don't use this macro to turn on various extra optimizations for | |
232 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
84ab3bfb | 233 | |
3d339ad2 RS |
234 | #define OVERRIDE_OPTIONS \ |
235 | { \ | |
9e62c7f2 | 236 | override_options(); \ |
3d339ad2 RS |
237 | if (! TARGET_68020 && flag_pic == 2) \ |
238 | error("-fPIC is not currently supported on the 68000 or 68010\n"); \ | |
2c8ec431 DL |
239 | if (TARGET_PCREL && flag_pic == 0) \ |
240 | flag_pic = 1; \ | |
cf9be6f0 | 241 | SUBTARGET_OVERRIDE_OPTIONS; \ |
3d339ad2 | 242 | } |
84ab3bfb | 243 | |
9e62c7f2 RK |
244 | /* These are meant to be redefined in the host dependent files */ |
245 | #define SUBTARGET_SWITCHES | |
246 | #define SUBTARGET_OPTIONS | |
84ab3bfb | 247 | #define SUBTARGET_OVERRIDE_OPTIONS |
3d339ad2 RS |
248 | \f |
249 | /* target machine storage layout */ | |
250 | ||
f6ba6a91 RS |
251 | /* Define for XFmode extended real floating point support. |
252 | This will automatically cause REAL_ARITHMETIC to be defined. */ | |
253 | #define LONG_DOUBLE_TYPE_SIZE 96 | |
254 | ||
255 | /* Define if you don't want extended real, but do want to use the | |
256 | software floating point emulator for REAL_ARITHMETIC and | |
257 | decimal <-> binary conversion. */ | |
258 | /* #define REAL_ARITHMETIC */ | |
259 | ||
3d339ad2 RS |
260 | /* Define this if most significant bit is lowest numbered |
261 | in instructions that operate on numbered bit-fields. | |
262 | This is true for 68020 insns such as bfins and bfexts. | |
263 | We make it true always by avoiding using the single-bit insns | |
264 | except in special cases with constant bit numbers. */ | |
265 | #define BITS_BIG_ENDIAN 1 | |
266 | ||
267 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
268 | /* That is true on the 68000. */ | |
269 | #define BYTES_BIG_ENDIAN 1 | |
270 | ||
271 | /* Define this if most significant word of a multiword number is the lowest | |
272 | numbered. */ | |
273 | /* For 68000 we can decide arbitrarily | |
274 | since there are no machine instructions for them. | |
275 | So let's be consistent. */ | |
276 | #define WORDS_BIG_ENDIAN 1 | |
277 | ||
b4ac57ab | 278 | /* number of bits in an addressable storage unit */ |
3d339ad2 RS |
279 | #define BITS_PER_UNIT 8 |
280 | ||
281 | /* Width in bits of a "word", which is the contents of a machine register. | |
282 | Note that this is not necessarily the width of data type `int'; | |
283 | if using 16-bit ints on a 68000, this would still be 32. | |
284 | But on a machine with 16-bit registers, this would be 16. */ | |
285 | #define BITS_PER_WORD 32 | |
286 | ||
287 | /* Width of a word, in units (bytes). */ | |
288 | #define UNITS_PER_WORD 4 | |
289 | ||
290 | /* Width in bits of a pointer. | |
291 | See also the macro `Pmode' defined below. */ | |
292 | #define POINTER_SIZE 32 | |
293 | ||
294 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
295 | #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) | |
296 | ||
297 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
298 | #define STACK_BOUNDARY 16 | |
299 | ||
300 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
9e62c7f2 | 301 | #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3)) |
3d339ad2 RS |
302 | |
303 | /* Alignment of field after `int : 0' in a structure. */ | |
304 | #define EMPTY_FIELD_BOUNDARY 16 | |
305 | ||
dcd13066 RK |
306 | /* No data type wants to be aligned rounder than this. |
307 | Most published ABIs say that ints should be aligned on 16 bit | |
956d6950 JL |
308 | boundaries, but cpus with 32 bit busses get better performance |
309 | aligned on 32 bit boundaries. Coldfires without a misalignment | |
dcd13066 RK |
310 | module require 32 bit alignment. */ |
311 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) | |
3d339ad2 | 312 | |
b4ac57ab | 313 | /* Set this nonzero if move instructions will actually fail to work |
3d339ad2 | 314 | when given unaligned data. */ |
b71733d5 | 315 | #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) |
3d339ad2 | 316 | |
9e62c7f2 RK |
317 | /* Maximum power of 2 that code can be aligned to. */ |
318 | #define MAX_CODE_ALIGN 2 /* 4 byte alignment */ | |
319 | ||
320 | /* Align loop starts for optimal branching. */ | |
fc470718 | 321 | #define LOOP_ALIGN(LABEL) (m68k_align_loops) |
9e62c7f2 RK |
322 | |
323 | /* This is how to align an instruction for optimal branching. */ | |
fc470718 | 324 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps) |
9e62c7f2 | 325 | |
3d339ad2 RS |
326 | #define SELECT_RTX_SECTION(MODE, X) \ |
327 | { \ | |
328 | if (!flag_pic) \ | |
329 | readonly_data_section(); \ | |
330 | else if (LEGITIMATE_PIC_OPERAND_P (X)) \ | |
331 | readonly_data_section(); \ | |
332 | else \ | |
333 | data_section(); \ | |
334 | } | |
335 | ||
336 | /* Define number of bits in most basic integer type. | |
337 | (If undefined, default is BITS_PER_WORD). */ | |
338 | ||
339 | #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) | |
340 | ||
86702e31 ZW |
341 | /* Define these to avoid dependence on meaning of `int'. */ |
342 | ||
3d339ad2 RS |
343 | #define WCHAR_TYPE "long int" |
344 | #define WCHAR_TYPE_SIZE 32 | |
345 | \f | |
346 | /* Standard register usage. */ | |
347 | ||
348 | /* Number of actual hardware registers. | |
349 | The hardware registers are assigned numbers for the compiler | |
350 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
351 | All registers that the compiler knows about must be given numbers, | |
352 | even those that are not normally considered general registers. | |
353 | For the 68000, we give the data registers numbers 0-7, | |
354 | the address registers numbers 010-017, | |
355 | and the 68881 floating point registers numbers 020-027. */ | |
356 | #ifndef SUPPORT_SUN_FPA | |
357 | #define FIRST_PSEUDO_REGISTER 24 | |
358 | #else | |
359 | #define FIRST_PSEUDO_REGISTER 56 | |
360 | #endif | |
361 | ||
362 | /* This defines the register which is used to hold the offset table for PIC. */ | |
363 | #define PIC_OFFSET_TABLE_REGNUM 13 | |
364 | ||
3d339ad2 RS |
365 | #ifndef SUPPORT_SUN_FPA |
366 | ||
367 | /* 1 for registers that have pervasive standard uses | |
368 | and are not available for the register allocator. | |
369 | On the 68000, only the stack pointer is such. */ | |
370 | ||
371 | #define FIXED_REGISTERS \ | |
372 | {/* Data registers. */ \ | |
373 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
374 | \ | |
375 | /* Address registers. */ \ | |
376 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
377 | \ | |
378 | /* Floating point registers \ | |
379 | (if available). */ \ | |
380 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
381 | ||
382 | /* 1 for registers not available across function calls. | |
383 | These must include the FIXED_REGISTERS and also any | |
384 | registers that can be used without being saved. | |
385 | The latter must include the registers where values are returned | |
386 | and the register where structure-value addresses are passed. | |
387 | Aside from that, you can include as many other registers as you like. */ | |
388 | #define CALL_USED_REGISTERS \ | |
389 | {1, 1, 0, 0, 0, 0, 0, 0, \ | |
390 | 1, 1, 0, 0, 0, 0, 0, 1, \ | |
391 | 1, 1, 0, 0, 0, 0, 0, 0 } | |
392 | ||
393 | #else /* SUPPORT_SUN_FPA */ | |
394 | ||
395 | /* 1 for registers that have pervasive standard uses | |
396 | and are not available for the register allocator. | |
397 | On the 68000, only the stack pointer is such. */ | |
398 | ||
956d6950 | 399 | /* fpa0 is also reserved so that it can be used to move data back and |
3d339ad2 RS |
400 | forth between high fpa regs and everything else. */ |
401 | ||
402 | #define FIXED_REGISTERS \ | |
403 | {/* Data registers. */ \ | |
404 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
405 | \ | |
406 | /* Address registers. */ \ | |
407 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
408 | \ | |
409 | /* Floating point registers \ | |
410 | (if available). */ \ | |
411 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
412 | \ | |
413 | /* Sun3 FPA registers. */ \ | |
414 | 1, 0, 0, 0, 0, 0, 0, 0, \ | |
415 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
416 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
417 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
418 | ||
419 | /* 1 for registers not available across function calls. | |
420 | These must include the FIXED_REGISTERS and also any | |
421 | registers that can be used without being saved. | |
422 | The latter must include the registers where values are returned | |
423 | and the register where structure-value addresses are passed. | |
424 | Aside from that, you can include as many other registers as you like. */ | |
425 | #define CALL_USED_REGISTERS \ | |
426 | {1, 1, 0, 0, 0, 0, 0, 0, \ | |
427 | 1, 1, 0, 0, 0, 0, 0, 1, \ | |
428 | 1, 1, 0, 0, 0, 0, 0, 0, \ | |
429 | /* FPA registers. */ \ | |
430 | 1, 1, 1, 1, 0, 0, 0, 0, \ | |
431 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
432 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
433 | 0, 0, 0, 0, 0, 0, 0, 0 } | |
434 | ||
435 | #endif /* defined SUPPORT_SUN_FPA */ | |
436 | ||
437 | ||
438 | /* Make sure everything's fine if we *don't* have a given processor. | |
439 | This assumes that putting a register in fixed_regs will keep the | |
440 | compiler's mitts completely off it. We don't bother to zero it out | |
15a17b72 | 441 | of register classes. */ |
3d339ad2 | 442 | |
eb939872 | 443 | #ifdef SUPPORT_SUN_FPA |
3d339ad2 RS |
444 | |
445 | #define CONDITIONAL_REGISTER_USAGE \ | |
446 | { \ | |
447 | int i; \ | |
448 | HARD_REG_SET x; \ | |
15a17b72 | 449 | if (! TARGET_FPA) \ |
3d339ad2 RS |
450 | { \ |
451 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \ | |
452 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
453 | if (TEST_HARD_REG_BIT (x, i)) \ | |
454 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
455 | } \ | |
15a17b72 | 456 | if (! TARGET_68881) \ |
3d339ad2 RS |
457 | { \ |
458 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ | |
459 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
460 | if (TEST_HARD_REG_BIT (x, i)) \ | |
461 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
462 | } \ | |
9839cd62 | 463 | if (flag_pic) \ |
44e3d967 JL |
464 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ |
465 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\ | |
466 | } | |
467 | #else | |
468 | #define CONDITIONAL_REGISTER_USAGE \ | |
469 | { \ | |
15a17b72 GK |
470 | int i; \ |
471 | HARD_REG_SET x; \ | |
472 | if (! TARGET_68881) \ | |
473 | { \ | |
474 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ | |
475 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
476 | if (TEST_HARD_REG_BIT (x, i)) \ | |
477 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
478 | } \ | |
44e3d967 JL |
479 | if (flag_pic) \ |
480 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ | |
481 | = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;\ | |
3d339ad2 RS |
482 | } |
483 | ||
484 | #endif /* defined SUPPORT_SUN_FPA */ | |
485 | ||
486 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
487 | to hold something of mode MODE. | |
488 | This is ordinarily the length in words of a value of mode MODE | |
489 | but can be less for certain modes in special long registers. | |
490 | ||
491 | On the 68000, ordinary registers hold 32 bits worth; | |
492 | for the 68881 registers, a single register is always enough for | |
493 | anything that can be stored in them at all. */ | |
494 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
495 | ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ | |
496 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
497 | ||
498 | #ifndef SUPPORT_SUN_FPA | |
499 | ||
500 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
501 | On the 68000, the cpu registers can hold any mode but the 68881 registers | |
15a17b72 | 502 | can hold only SFmode or DFmode. */ |
3d339ad2 RS |
503 | |
504 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
71380ac6 | 505 | (((REGNO) < 16 \ |
619aeb96 JW |
506 | && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \ |
507 | || ((REGNO) >= 16 && (REGNO) < 24 \ | |
3d339ad2 | 508 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
b621b712 AS |
509 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ |
510 | && GET_MODE_UNIT_SIZE (MODE) <= 12)) | |
3d339ad2 RS |
511 | |
512 | #else /* defined SUPPORT_SUN_FPA */ | |
513 | ||
514 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
515 | On the 68000, the cpu registers can hold any mode but the 68881 registers | |
15a17b72 | 516 | can hold only SFmode or DFmode. However, the Sun FPA register can |
3d339ad2 RS |
517 | (apparently) hold whatever you feel like putting in them. |
518 | If using the fpa, don't put a double in d7/a0. */ | |
519 | ||
619aeb96 JW |
520 | /* ??? This is confused. The check to prohibit d7/a0 overlaps should always |
521 | be enabled regardless of whether TARGET_FPA is specified. It isn't clear | |
522 | what the other d/a register checks are for. Every check using REGNO | |
523 | actually needs to use a range, e.g. 24>=X<56 not <56. There is probably | |
15a17b72 GK |
524 | no one using this code anymore. |
525 | This code used to be used to suppress register usage for the 68881 by | |
526 | saying that the 68881 registers couldn't hold values of any mode if there | |
527 | was no 68881. This was wrong, because reload (etc.) will still try | |
528 | to save and restore call-saved registers during, for instance, non-local | |
529 | goto. */ | |
3d339ad2 RS |
530 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
531 | (((REGNO) < 16 \ | |
532 | && !(TARGET_FPA \ | |
533 | && GET_MODE_CLASS ((MODE)) != MODE_INT \ | |
534 | && GET_MODE_UNIT_SIZE ((MODE)) > 4 \ | |
535 | && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \ | |
536 | && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \ | |
15a17b72 GK |
537 | || ((REGNO) >= 16 && (REGNO) < 24 \ |
538 | ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
539 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
b621b712 AS |
540 | && GET_MODE_UNIT_SIZE (MODE) <= 12) \ |
541 | : ((REGNO) < 56 ? TARGET_FPA && GET_MODE_UNIT_SIZE (MODE) <= 8 : 0))) | |
3d339ad2 RS |
542 | |
543 | #endif /* defined SUPPORT_SUN_FPA */ | |
544 | ||
545 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
546 | when one has mode MODE1 and one has mode MODE2. | |
547 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
548 | for any hard reg, then this must be 0 for correct output. */ | |
549 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
550 | (! TARGET_68881 \ | |
551 | || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
552 | || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ | |
553 | == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
554 | || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) | |
555 | ||
556 | /* Specify the registers used for certain standard purposes. | |
557 | The values of these macros are register numbers. */ | |
558 | ||
559 | /* m68000 pc isn't overloaded on a register. */ | |
560 | /* #define PC_REGNUM */ | |
561 | ||
562 | /* Register to use for pushing function arguments. */ | |
563 | #define STACK_POINTER_REGNUM 15 | |
564 | ||
565 | /* Base register for access to local variables of the function. */ | |
566 | #define FRAME_POINTER_REGNUM 14 | |
567 | ||
568 | /* Value should be nonzero if functions must have frame pointers. | |
569 | Zero means the frame pointer need not be set up (and parms | |
570 | may be accessed via the stack pointer) in functions that seem suitable. | |
571 | This is computed in `reload', in reload1.c. */ | |
572 | #define FRAME_POINTER_REQUIRED 0 | |
573 | ||
574 | /* Base register for access to arguments of the function. */ | |
575 | #define ARG_POINTER_REGNUM 14 | |
576 | ||
577 | /* Register in which static-chain is passed to a function. */ | |
578 | #define STATIC_CHAIN_REGNUM 8 | |
579 | ||
580 | /* Register in which address to store a structure value | |
581 | is passed to a function. */ | |
582 | #define STRUCT_VALUE_REGNUM 9 | |
583 | \f | |
584 | /* Define the classes of registers for register constraints in the | |
585 | machine description. Also define ranges of constants. | |
586 | ||
587 | One of the classes must always be named ALL_REGS and include all hard regs. | |
588 | If there is more than one class, another class must be named NO_REGS | |
589 | and contain no registers. | |
590 | ||
591 | The name GENERAL_REGS must be the name of a class (or an alias for | |
592 | another name such as ALL_REGS). This is the class of registers | |
593 | that is allowed by "g" or "r" in a register constraint. | |
594 | Also, registers outside this class are allocated only when | |
595 | instructions express preferences for them. | |
596 | ||
597 | The classes must be numbered in nondecreasing order; that is, | |
598 | a larger-numbered class must never be contained completely | |
599 | in a smaller-numbered class. | |
600 | ||
601 | For any two classes, it is very desirable that there be another | |
602 | class that represents their union. */ | |
603 | ||
604 | /* The 68000 has three kinds of registers, so eight classes would be | |
605 | a complete set. One of them is not needed. */ | |
606 | ||
607 | #ifndef SUPPORT_SUN_FPA | |
608 | ||
609 | enum reg_class { | |
610 | NO_REGS, DATA_REGS, | |
611 | ADDR_REGS, FP_REGS, | |
612 | GENERAL_REGS, DATA_OR_FP_REGS, | |
613 | ADDR_OR_FP_REGS, ALL_REGS, | |
614 | LIM_REG_CLASSES }; | |
615 | ||
616 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
617 | ||
618 | /* Give names of register classes as strings for dump file. */ | |
619 | ||
620 | #define REG_CLASS_NAMES \ | |
621 | { "NO_REGS", "DATA_REGS", \ | |
622 | "ADDR_REGS", "FP_REGS", \ | |
623 | "GENERAL_REGS", "DATA_OR_FP_REGS", \ | |
624 | "ADDR_OR_FP_REGS", "ALL_REGS" } | |
625 | ||
626 | /* Define which registers fit in which classes. | |
627 | This is an initializer for a vector of HARD_REG_SET | |
628 | of length N_REG_CLASSES. */ | |
629 | ||
630 | #define REG_CLASS_CONTENTS \ | |
631 | { \ | |
7a87758d AS |
632 | {0x00000000}, /* NO_REGS */ \ |
633 | {0x000000ff}, /* DATA_REGS */ \ | |
634 | {0x0000ff00}, /* ADDR_REGS */ \ | |
635 | {0x00ff0000}, /* FP_REGS */ \ | |
636 | {0x0000ffff}, /* GENERAL_REGS */ \ | |
637 | {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ | |
638 | {0x00ffff00}, /* ADDR_OR_FP_REGS */ \ | |
639 | {0x00ffffff}, /* ALL_REGS */ \ | |
3d339ad2 RS |
640 | } |
641 | ||
642 | /* The same information, inverted: | |
643 | Return the class number of the smallest class containing | |
644 | reg number REGNO. This could be a conditional expression | |
645 | or could index an array. */ | |
646 | ||
647 | #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1) | |
648 | ||
649 | #else /* defined SUPPORT_SUN_FPA */ | |
650 | ||
651 | /* | |
652 | * Notes on final choices: | |
653 | * | |
654 | * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything | |
655 | * else. | |
656 | * 2) Removed all unions that involve address registers with | |
657 | * floating point registers (left in unions of address and data with | |
658 | * floating point). | |
659 | * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS. | |
660 | * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS. | |
661 | * 4) Left in everything else. | |
662 | */ | |
663 | enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS, | |
664 | FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS, | |
665 | DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS, | |
666 | GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS, | |
667 | LIM_REG_CLASSES }; | |
668 | ||
669 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
670 | ||
671 | /* Give names of register classes as strings for dump file. */ | |
672 | ||
673 | #define REG_CLASS_NAMES \ | |
674 | { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \ | |
675 | "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \ | |
676 | "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \ | |
677 | "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" } | |
678 | ||
679 | /* Define which registers fit in which classes. | |
680 | This is an initializer for a vector of HARD_REG_SET | |
681 | of length N_REG_CLASSES. */ | |
682 | ||
683 | #define REG_CLASS_CONTENTS \ | |
684 | { \ | |
685 | {0, 0}, /* NO_REGS */ \ | |
686 | {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \ | |
687 | {0xff000000, 0x00ffffff}, /* FPA_REGS */ \ | |
688 | {0x00ff0000, 0x00000000}, /* FP_REGS */ \ | |
689 | {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \ | |
690 | {0x000000ff, 0x00000000}, /* DATA_REGS */ \ | |
691 | {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \ | |
692 | {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \ | |
693 | {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\ | |
694 | {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \ | |
695 | {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \ | |
696 | {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\ | |
697 | {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\ | |
698 | {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \ | |
699 | } | |
700 | ||
701 | /* The same information, inverted: | |
702 | Return the class number of the smallest class containing | |
703 | reg number REGNO. This could be a conditional expression | |
704 | or could index an array. */ | |
705 | ||
706 | extern enum reg_class regno_reg_class[]; | |
707 | #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) | |
708 | ||
709 | #endif /* SUPPORT_SUN_FPA */ | |
710 | ||
711 | /* The class value for index registers, and the one for base regs. */ | |
712 | ||
713 | #define INDEX_REG_CLASS GENERAL_REGS | |
714 | #define BASE_REG_CLASS ADDR_REGS | |
715 | ||
716 | /* Get reg_class from a letter such as appears in the machine description. | |
717 | We do a trick here to modify the effective constraints on the | |
718 | machine description; we zorch the constraint letters that aren't | |
719 | appropriate for a specific target. This allows us to guarantee | |
720 | that a specific kind of register will not be used for a given target | |
721 | without fiddling with the register classes above. */ | |
722 | ||
723 | #ifndef SUPPORT_SUN_FPA | |
724 | ||
725 | #define REG_CLASS_FROM_LETTER(C) \ | |
726 | ((C) == 'a' ? ADDR_REGS : \ | |
727 | ((C) == 'd' ? DATA_REGS : \ | |
728 | ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ | |
729 | NO_REGS) : \ | |
730 | NO_REGS))) | |
731 | ||
732 | #else /* defined SUPPORT_SUN_FPA */ | |
733 | ||
734 | #define REG_CLASS_FROM_LETTER(C) \ | |
735 | ((C) == 'a' ? ADDR_REGS : \ | |
736 | ((C) == 'd' ? DATA_REGS : \ | |
737 | ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ | |
738 | NO_REGS) : \ | |
739 | ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \ | |
740 | NO_REGS) : \ | |
741 | ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \ | |
742 | NO_REGS) : \ | |
743 | NO_REGS))))) | |
744 | ||
745 | #endif /* defined SUPPORT_SUN_FPA */ | |
746 | ||
747 | /* The letters I, J, K, L and M in a register constraint string | |
748 | can be used to stand for particular ranges of immediate operands. | |
749 | This macro defines what the ranges are. | |
750 | C is the letter, and VALUE is a constant value. | |
751 | Return 1 if VALUE is in the range specified by C. | |
752 | ||
753 | For the 68000, `I' is used for the range 1 to 8 | |
754 | allowed as immediate shift counts and in addq. | |
755 | `J' is used for the range of signed numbers that fit in 16 bits. | |
756 | `K' is for numbers that moveq can't handle. | |
a9f6f5aa | 757 | `L' is for range -8 to -1, range of values that can be added with subq. |
d8fa884b RK |
758 | `M' is for numbers that moveq+notb can't handle. |
759 | 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate. | |
760 | 'O' is for 16 (for rotate using swap). | |
761 | 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */ | |
a9f6f5aa RK |
762 | |
763 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
764 | ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ | |
765 | (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ | |
766 | (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ | |
767 | (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \ | |
68137318 | 768 | (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \ |
d8fa884b RK |
769 | (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \ |
770 | (C) == 'O' ? (VALUE) == 16 : \ | |
771 | (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0) | |
3d339ad2 RS |
772 | |
773 | /* | |
774 | * A small bit of explanation: | |
775 | * "G" defines all of the floating constants that are *NOT* 68881 | |
776 | * constants. this is so 68881 constants get reloaded and the | |
777 | * fpmovecr is used. "H" defines *only* the class of constants that | |
778 | * the fpa can use, because these can be gotten at in any fpa | |
779 | * instruction and there is no need to force reloads. | |
780 | */ | |
781 | #ifndef SUPPORT_SUN_FPA | |
782 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
783 | ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) | |
784 | #else /* defined SUPPORT_SUN_FPA */ | |
785 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
786 | ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \ | |
787 | (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0) | |
788 | #endif /* defined SUPPORT_SUN_FPA */ | |
789 | ||
02385fc5 RK |
790 | /* A C expression that defines the optional machine-dependent constraint |
791 | letters that can be used to segregate specific types of operands, | |
792 | usually memory references, for the target machine. It should return 1 if | |
793 | VALUE corresponds to the operand type represented by the constraint letter | |
794 | C. If C is not defined as an extra constraint, the value returned should | |
795 | be 0 regardless of VALUE. */ | |
796 | ||
2c8ec431 DL |
797 | /* Letters in the range `Q' through `U' may be defined in a |
798 | machine-dependent fashion to stand for arbitrary operand types. | |
799 | The machine description macro `EXTRA_CONSTRAINT' is passed the | |
800 | operand as its first argument and the constraint letter as its | |
801 | second operand. | |
802 | ||
803 | `Q' means address register indirect addressing mode. | |
804 | `S' is for operands that satisfy 'm' when -mpcrel is in effect. | |
805 | `T' is for operands that satisfy 's' when -mpcrel is not in effect. */ | |
806 | ||
807 | #define EXTRA_CONSTRAINT(OP,CODE) \ | |
808 | (((CODE) == 'S') \ | |
809 | ? (TARGET_PCREL \ | |
810 | && GET_CODE (OP) == MEM \ | |
811 | && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
812 | || GET_CODE (XEXP (OP, 0)) == LABEL_REF \ | |
813 | || GET_CODE (XEXP (OP, 0)) == CONST)) \ | |
814 | : \ | |
815 | (((CODE) == 'T') \ | |
816 | ? ( !TARGET_PCREL \ | |
817 | && (GET_CODE (OP) == SYMBOL_REF \ | |
818 | || GET_CODE (OP) == LABEL_REF \ | |
819 | || GET_CODE (OP) == CONST)) \ | |
820 | : \ | |
821 | (((CODE) == 'Q') \ | |
822 | ? (GET_CODE (OP) == MEM \ | |
823 | && GET_CODE (XEXP (OP, 0)) == REG) \ | |
824 | : \ | |
825 | 0))) | |
02385fc5 | 826 | |
3d339ad2 RS |
827 | /* Given an rtx X being reloaded into a reg required to be |
828 | in class CLASS, return the class of reg to actually use. | |
829 | In general this is just CLASS; but on some machines | |
830 | in some cases it is preferable to use a more restrictive class. | |
831 | On the 68000 series, use a data reg if possible when the | |
832 | value is a constant in the range where moveq could be used | |
9839cd62 | 833 | and we ensure that QImodes are reloaded into data regs. */ |
3d339ad2 RS |
834 | |
835 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
836 | ((GET_CODE (X) == CONST_INT \ | |
837 | && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ | |
838 | && (CLASS) != ADDR_REGS) \ | |
839 | ? DATA_REGS \ | |
840 | : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ | |
841 | ? DATA_REGS \ | |
9839cd62 RH |
842 | : (GET_CODE (X) == CONST_DOUBLE \ |
843 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ | |
844 | ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ | |
845 | ? FP_REGS : NO_REGS) \ | |
2c8ec431 DL |
846 | : (TARGET_PCREL \ |
847 | && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ | |
848 | || GET_CODE (X) == LABEL_REF)) \ | |
849 | ? ADDR_REGS \ | |
3d339ad2 RS |
850 | : (CLASS)) |
851 | ||
6c13d910 JW |
852 | /* Force QImode output reloads from subregs to be allocated to data regs, |
853 | since QImode stores from address regs are not supported. We make the | |
854 | assumption that if the class is not ADDR_REGS, then it must be a superset | |
855 | of DATA_REGS. */ | |
856 | ||
857 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ | |
858 | (((MODE) == QImode && (CLASS) != ADDR_REGS) \ | |
859 | ? DATA_REGS \ | |
860 | : (CLASS)) | |
861 | ||
3d339ad2 RS |
862 | /* Return the maximum number of consecutive registers |
863 | needed to represent mode MODE in a register of class CLASS. */ | |
864 | /* On the 68000, this is the size of MODE in words, | |
865 | except in the FP regs, where a single reg is always enough. */ | |
866 | #ifndef SUPPORT_SUN_FPA | |
867 | ||
868 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
869 | ((CLASS) == FP_REGS ? 1 \ | |
870 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
871 | ||
872 | /* Moves between fp regs and other regs are two insns. */ | |
cf011243 | 873 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
3d339ad2 RS |
874 | (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ |
875 | || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ | |
876 | ? 4 : 2) | |
877 | ||
878 | #else /* defined SUPPORT_SUN_FPA */ | |
879 | ||
880 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
881 | ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \ | |
882 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
883 | ||
884 | /* Moves between fp regs and other regs are two insns. */ | |
885 | /* Likewise for high fpa regs and other regs. */ | |
cf011243 | 886 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
3d339ad2 RS |
887 | ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ |
888 | || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ | |
889 | || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \ | |
890 | || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \ | |
891 | ? 4 : 2) | |
892 | ||
893 | #endif /* define SUPPORT_SUN_FPA */ | |
894 | \f | |
895 | /* Stack layout; function entry, exit and calling. */ | |
896 | ||
897 | /* Define this if pushing a word on the stack | |
898 | makes the stack pointer a smaller address. */ | |
899 | #define STACK_GROWS_DOWNWARD | |
900 | ||
901 | /* Nonzero if we need to generate stack-probe insns. | |
902 | On most systems they are not needed. | |
903 | When they are needed, define this as the stack offset to probe at. */ | |
904 | #define NEED_PROBE 0 | |
905 | ||
906 | /* Define this if the nominal address of the stack frame | |
907 | is at the high-address end of the local variables; | |
908 | that is, each additional local variable allocated | |
909 | goes at a more negative offset in the frame. */ | |
910 | #define FRAME_GROWS_DOWNWARD | |
911 | ||
912 | /* Offset within stack frame to start allocating local variables at. | |
913 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
914 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
915 | of the first local allocated. */ | |
916 | #define STARTING_FRAME_OFFSET 0 | |
917 | ||
918 | /* If we generate an insn to push BYTES bytes, | |
919 | this says how many the stack pointer really advances by. | |
6d808a73 JW |
920 | On the 68000, sp@- in a byte insn really pushes a word. |
921 | On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */ | |
922 | #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1) | |
3d339ad2 | 923 | |
d676911f DD |
924 | /* We want to avoid trying to push bytes. */ |
925 | #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ | |
926 | (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \ | |
927 | && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200))) | |
928 | ||
3d339ad2 RS |
929 | /* Offset of first parameter from the argument pointer register value. */ |
930 | #define FIRST_PARM_OFFSET(FNDECL) 8 | |
931 | ||
932 | /* Value is the number of byte of arguments automatically | |
933 | popped when returning from a subroutine call. | |
8b109b37 | 934 | FUNDECL is the declaration node of the function (as a tree), |
3d339ad2 RS |
935 | FUNTYPE is the data type of the function (as a tree), |
936 | or for a library call it is an identifier node for the subroutine name. | |
937 | SIZE is the number of bytes of arguments passed on the stack. | |
938 | ||
939 | On the 68000, the RTS insn cannot pop anything. | |
940 | On the 68010, the RTD insn may be used to pop them if the number | |
941 | of args is fixed, but if the number is variable then the caller | |
942 | must pop them all. RTD can't be used for library calls now | |
943 | because the library is compiled with the Unix compiler. | |
944 | Use of RTD is a selectable option, since it is incompatible with | |
945 | standard Unix calling sequences. If the option is not selected, | |
946 | the caller must always pop the args. */ | |
947 | ||
8b109b37 | 948 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ |
2033a41a | 949 | ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \ |
3d339ad2 RS |
950 | && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ |
951 | || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ | |
952 | == void_type_node))) \ | |
953 | ? (SIZE) : 0) | |
954 | ||
955 | /* Define how to find the value returned by a function. | |
956 | VALTYPE is the data type of the value (as a tree). | |
957 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
958 | otherwise, FUNC is 0. */ | |
959 | ||
960 | /* On the 68000 the return value is in D0 regardless. */ | |
961 | ||
962 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1d8eaa6b | 963 | gen_rtx_REG (TYPE_MODE (VALTYPE), 0) |
3d339ad2 RS |
964 | |
965 | /* Define how to find the value returned by a library function | |
966 | assuming the value has mode MODE. */ | |
967 | ||
968 | /* On the 68000 the return value is in D0 regardless. */ | |
969 | ||
1d8eaa6b | 970 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) |
3d339ad2 RS |
971 | |
972 | /* 1 if N is a possible register number for a function value. | |
973 | On the 68000, d0 is the only register thus used. */ | |
974 | ||
975 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) | |
976 | ||
7972af82 TW |
977 | /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for |
978 | more than one register. */ | |
979 | ||
980 | #define NEEDS_UNTYPED_CALL 0 | |
981 | ||
3d339ad2 RS |
982 | /* Define this if PCC uses the nonreentrant convention for returning |
983 | structure and union values. */ | |
984 | ||
985 | #define PCC_STATIC_STRUCT_RETURN | |
986 | ||
987 | /* 1 if N is a possible register number for function argument passing. | |
988 | On the 68000, no registers are used in this way. */ | |
989 | ||
990 | #define FUNCTION_ARG_REGNO_P(N) 0 | |
991 | \f | |
992 | /* Define a data type for recording info about an argument list | |
993 | during the scan of that argument list. This data type should | |
994 | hold all necessary information about the function itself | |
995 | and about the args processed so far, enough to enable macros | |
996 | such as FUNCTION_ARG to determine where the next arg should go. | |
997 | ||
998 | On the m68k, this is a single integer, which is a number of bytes | |
999 | of arguments scanned so far. */ | |
1000 | ||
1001 | #define CUMULATIVE_ARGS int | |
1002 | ||
1003 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1004 | for a call to a function whose data type is FNTYPE. | |
1005 | For a library call, FNTYPE is 0. | |
1006 | ||
1007 | On the m68k, the offset starts at 0. */ | |
1008 | ||
2c7ee1a6 | 1009 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
3d339ad2 RS |
1010 | ((CUM) = 0) |
1011 | ||
1012 | /* Update the data in CUM to advance over an argument | |
1013 | of mode MODE and data type TYPE. | |
1014 | (TYPE is null for libcalls where that information may not be available.) */ | |
1015 | ||
1016 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1017 | ((CUM) += ((MODE) != BLKmode \ | |
1018 | ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ | |
1019 | : (int_size_in_bytes (TYPE) + 3) & ~3)) | |
1020 | ||
1021 | /* Define where to put the arguments to a function. | |
1022 | Value is zero to push the argument on the stack, | |
1023 | or a hard register in which to store the argument. | |
1024 | ||
1025 | MODE is the argument's machine mode. | |
1026 | TYPE is the data type of the argument (as a tree). | |
1027 | This is null for libcalls where that information may | |
1028 | not be available. | |
1029 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1030 | the preceding args and about the function being called. | |
1031 | NAMED is nonzero if this argument is a named parameter | |
1032 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1033 | ||
1034 | /* On the 68000 all args are pushed, except if -mregparm is specified | |
1035 | then the first two words of arguments are passed in d0, d1. | |
1036 | *NOTE* -mregparm does not work. | |
1037 | It exists only to test register calling conventions. */ | |
1038 | ||
1039 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
1d8eaa6b | 1040 | ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0) |
3d339ad2 RS |
1041 | |
1042 | /* For an arg passed partly in registers and partly in memory, | |
1043 | this is the number of registers used. | |
1044 | For args passed entirely in registers or entirely in memory, zero. */ | |
1045 | ||
1046 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
1047 | ((TARGET_REGPARM && (CUM) < 8 \ | |
1048 | && 8 < ((CUM) + ((MODE) == BLKmode \ | |
1049 | ? int_size_in_bytes (TYPE) \ | |
1050 | : GET_MODE_SIZE (MODE)))) \ | |
1051 | ? 2 - (CUM) / 4 : 0) | |
1052 | ||
3d339ad2 RS |
1053 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1054 | for profiling a function entry. */ | |
1055 | ||
1056 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
1057 | asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) | |
1058 | ||
1059 | /* Output assembler code to FILE to initialize this source file's | |
1060 | basic block profiling info, if that has not already been done. */ | |
1061 | ||
6e753900 RK |
1062 | #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \ |
1063 | do \ | |
1064 | { \ | |
1065 | switch (profile_block_flag) \ | |
1066 | { \ | |
1067 | case 2: \ | |
1068 | asm_fprintf (FILE, "\tpea %d\n\tpea %LLPBX0\n\tjsr %U__bb_init_trace_func\n\taddql %I8,%Rsp\n", \ | |
1069 | (BLOCK_OR_LABEL)); \ | |
1070 | break; \ | |
1071 | \ | |
1072 | default: \ | |
1073 | asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \ | |
1074 | (BLOCK_OR_LABEL), (BLOCK_OR_LABEL)); \ | |
1075 | break; \ | |
1076 | } \ | |
1077 | } \ | |
1078 | while(0) | |
1079 | ||
1080 | /* Output assembler code to FILE to increment the counter for | |
3d339ad2 RS |
1081 | the BLOCKNO'th basic block in this source file. */ |
1082 | ||
1083 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
6e753900 RK |
1084 | do \ |
1085 | { \ | |
1086 | switch (profile_block_flag) \ | |
1087 | { \ | |
1088 | case 2: \ | |
1089 | asm_fprintf (FILE, "\tmovel %Ra1,%Rsp@-\n\tlea ___bb,%Ra1\n\tmovel %I%d,%Ra1@(0)\n\tmovel %I%LLPBX0,%Ra1@(4)\n\tmovel %Rsp@+,%Ra1\n\tjsr %U__bb_trace_func\n", \ | |
1090 | BLOCKNO); \ | |
1091 | break; \ | |
1092 | \ | |
1093 | default: \ | |
1094 | asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO); \ | |
1095 | break; \ | |
1096 | } \ | |
1097 | } \ | |
1098 | while(0) | |
1099 | ||
1100 | /* Output assembler code to FILE to indicate return from | |
1101 | a function during basic block profiling. */ | |
1102 | ||
1103 | #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \ | |
1104 | asm_fprintf (FILE, "\tjsr %U__bb_trace_ret\n"); | |
1105 | ||
d947dca0 RK |
1106 | /* Save all registers which may be clobbered by a function call. |
1107 | MACHINE_STATE_SAVE and MACHINE_STATE_RESTORE are target-code macros, | |
1108 | used in libgcc2.c. They may not refer to TARGET_* macros !!! */ | |
1109 | #if defined (__mc68010__) || defined(mc68010) \ | |
1110 | || defined(__mc68020__) || defined(mc68020) \ | |
1111 | || defined(__mc68030__) || defined(mc68030) \ | |
1112 | || defined(__mc68040__) || defined(mc68040) \ | |
74cf1c6d | 1113 | || defined(__mcpu32__) || defined(mcpu32) |
d947dca0 RK |
1114 | #define MACHINE_STATE_m68010_up |
1115 | #endif | |
6e753900 | 1116 | |
ad92f794 | 1117 | #ifdef MOTOROLA |
d947dca0 | 1118 | #if defined(__mcf5200__) |
ad92f794 | 1119 | #define MACHINE_STATE_SAVE(id) \ |
0be1f0e1 JW |
1120 | { \ |
1121 | asm ("sub.l 20,%sp"); \ | |
1122 | asm ("movm.l &0x0303,4(%sp)"); \ | |
1123 | asm ("move.w %ccr,%d0"); \ | |
1124 | asm ("movm.l &0x0001,(%sp)"); \ | |
d947dca0 RK |
1125 | } |
1126 | #else /* !__mcf5200__ */ | |
1127 | #if defined(MACHINE_STATE_m68010_up) | |
89cc6098 JW |
1128 | #ifdef __HPUX_ASM__ |
1129 | /* HPUX assembler does not accept %ccr. */ | |
1130 | #define MACHINE_STATE_SAVE(id) \ | |
1131 | { \ | |
1132 | asm ("move.w %cc,-(%sp)"); \ | |
1133 | asm ("movm.l &0xc0c0,-(%sp)"); \ | |
1134 | } | |
1135 | #else /* ! __HPUX_ASM__ */ | |
d947dca0 | 1136 | #define MACHINE_STATE_SAVE(id) \ |
0be1f0e1 JW |
1137 | { \ |
1138 | asm ("move.w %ccr,-(%sp)"); \ | |
1139 | asm ("movm.l &0xc0c0,-(%sp)"); \ | |
1140 | } | |
89cc6098 | 1141 | #endif /* __HPUX_ASM__ */ |
d947dca0 RK |
1142 | #else /* !MACHINE_STATE_m68010_up */ |
1143 | #define MACHINE_STATE_SAVE(id) \ | |
1144 | { \ | |
1145 | asm ("move.w %sr,-(%sp)"); \ | |
1146 | asm ("movm.l &0xc0c0,-(%sp)"); \ | |
1147 | } | |
1148 | #endif /* MACHINE_STATE_m68010_up */ | |
1149 | #endif /* __mcf5200__ */ | |
1150 | #else /* !MOTOROLA */ | |
1151 | #if defined(__mcf5200__) | |
ad92f794 | 1152 | #define MACHINE_STATE_SAVE(id) \ |
0be1f0e1 | 1153 | { \ |
c0b04148 JW |
1154 | asm ("subl %#20,%/sp" : ); \ |
1155 | asm ("movml %/d0/%/d1/%/a0/%/a1,%/sp@(4)" : ); \ | |
1156 | asm ("movew %/cc,%/d0" : ); \ | |
1157 | asm ("movml %/d0,%/sp@" : ); \ | |
d947dca0 RK |
1158 | } |
1159 | #else /* !__mcf5200__ */ | |
1160 | #if defined(MACHINE_STATE_m68010_up) | |
1161 | #define MACHINE_STATE_SAVE(id) \ | |
0be1f0e1 | 1162 | { \ |
c0b04148 JW |
1163 | asm ("movew %/cc,%/sp@-" : ); \ |
1164 | asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \ | |
0be1f0e1 | 1165 | } |
d947dca0 RK |
1166 | #else /* !MACHINE_STATE_m68010_up */ |
1167 | #define MACHINE_STATE_SAVE(id) \ | |
1168 | { \ | |
c0b04148 JW |
1169 | asm ("movew %/sr,%/sp@-" : ); \ |
1170 | asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \ | |
d947dca0 RK |
1171 | } |
1172 | #endif /* MACHINE_STATE_m68010_up */ | |
1173 | #endif /* __mcf5200__ */ | |
1174 | #endif /* MOTOROLA */ | |
6e753900 RK |
1175 | |
1176 | /* Restore all registers saved by MACHINE_STATE_SAVE. */ | |
1177 | ||
ad92f794 | 1178 | #ifdef MOTOROLA |
d947dca0 | 1179 | #if defined(__mcf5200__) |
ad92f794 | 1180 | #define MACHINE_STATE_RESTORE(id) \ |
0be1f0e1 JW |
1181 | { \ |
1182 | asm ("movm.l (%sp),&0x0001"); \ | |
1183 | asm ("move.w %d0,%ccr"); \ | |
1184 | asm ("movm.l 4(%sp),&0x0303"); \ | |
1185 | asm ("add.l 20,%sp"); \ | |
d947dca0 RK |
1186 | } |
1187 | #else /* !__mcf5200__ */ | |
89cc6098 JW |
1188 | #ifdef __HPUX_ASM__ |
1189 | /* HPUX assembler does not accept %ccr. */ | |
1190 | #define MACHINE_STATE_RESTORE(id) \ | |
1191 | { \ | |
1192 | asm ("movm.l (%sp)+,&0x0303"); \ | |
1193 | asm ("move.w (%sp)+,%cc"); \ | |
1194 | } | |
1195 | #else /* ! __HPUX_ASM__ */ | |
d947dca0 | 1196 | #define MACHINE_STATE_RESTORE(id) \ |
0be1f0e1 JW |
1197 | { \ |
1198 | asm ("movm.l (%sp)+,&0x0303"); \ | |
1199 | asm ("move.w (%sp)+,%ccr"); \ | |
1200 | } | |
89cc6098 | 1201 | #endif /* __HPUX_ASM__ */ |
d947dca0 RK |
1202 | #endif /* __mcf5200__ */ |
1203 | #else /* !MOTOROLA */ | |
1204 | #if defined(__mcf5200__) | |
ad92f794 | 1205 | #define MACHINE_STATE_RESTORE(id) \ |
0be1f0e1 | 1206 | { \ |
c0b04148 JW |
1207 | asm ("movml %/sp@,%/d0" : ); \ |
1208 | asm ("movew %/d0,%/cc" : ); \ | |
1209 | asm ("movml %/sp@(4),%/d0/%/d1/%/a0/%/a1" : ); \ | |
1210 | asm ("addl %#20,%/sp" : ); \ | |
d947dca0 RK |
1211 | } |
1212 | #else /* !__mcf5200__ */ | |
1213 | #define MACHINE_STATE_RESTORE(id) \ | |
0be1f0e1 | 1214 | { \ |
c0b04148 JW |
1215 | asm ("moveml %/sp@+,%/d0/%/d1/%/a0/%/a1" : ); \ |
1216 | asm ("movew %/sp@+,%/cc" : ); \ | |
0be1f0e1 | 1217 | } |
d947dca0 RK |
1218 | #endif /* __mcf5200__ */ |
1219 | #endif /* MOTOROLA */ | |
3d339ad2 RS |
1220 | |
1221 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1222 | the stack pointer does not matter. The value is tested only in | |
1223 | functions that have frame pointers. | |
1224 | No definition is equivalent to always zero. */ | |
1225 | ||
1226 | #define EXIT_IGNORE_STACK 1 | |
1227 | ||
3d339ad2 RS |
1228 | /* This is a hook for other tm files to change. */ |
1229 | /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */ | |
1230 | ||
1231 | /* Determine if the epilogue should be output as RTL. | |
1232 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
1233 | #define USE_RETURN_INSN use_return_insn () | |
1234 | ||
1235 | /* Store in the variable DEPTH the initial difference between the | |
1236 | frame pointer reg contents and the stack pointer reg contents, | |
1237 | as of the start of the function body. This depends on the layout | |
1238 | of the fixed parts of the stack frame and on how registers are saved. | |
1239 | ||
1240 | On the 68k, if we have a frame, we must add one word to its length | |
1241 | to allow for the place that a6 is stored when we do have a frame pointer. | |
1242 | Otherwise, we would need to compute the offset from the frame pointer | |
1243 | of a local variable as a function of frame_pointer_needed, which | |
1244 | is hard. */ | |
1245 | ||
1246 | #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ | |
1247 | { int regno; \ | |
1248 | int offset = -4; \ | |
1249 | for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ | |
1250 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1251 | offset += 12; \ | |
1252 | for (regno = 0; regno < 16; regno++) \ | |
1253 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1254 | offset += 4; \ | |
d3f4f2d6 AS |
1255 | if (flag_pic && current_function_uses_pic_offset_table) \ |
1256 | offset += 4; \ | |
3d339ad2 RS |
1257 | (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \ |
1258 | + (get_frame_size () == 0 ? 0 : 4)); \ | |
1259 | } | |
1260 | ||
1261 | /* Output assembler code for a block containing the constant parts | |
1262 | of a trampoline, leaving space for the variable parts. */ | |
1263 | ||
1264 | /* On the 68k, the trampoline looks like this: | |
27a55d6b RK |
1265 | movl #STATIC,a0 |
1266 | jmp FUNCTION | |
1267 | ||
1268 | WARNING: Targets that may run on 68040+ cpus must arrange for | |
1269 | the instruction cache to be flushed. Previous incarnations of | |
1270 | the m68k trampoline code attempted to get around this by either | |
1271 | using an out-of-line transfer function or pc-relative data, but | |
1272 | the fact remains that the code to jump to the transfer function | |
1273 | or the code to load the pc-relative data needs to be flushed | |
1274 | just as much as the "variable" portion of the trampoline. | |
1275 | Recognizing that a cache flush is going to be required anyway, | |
1276 | dispense with such notions and build a smaller trampoline. */ | |
1277 | ||
1278 | /* Since more instructions are required to move a template into | |
1279 | place than to create it on the spot, don't use a template. */ | |
3d339ad2 RS |
1280 | |
1281 | /* Length in units of the trampoline for entering a nested function. */ | |
1282 | ||
27a55d6b RK |
1283 | #define TRAMPOLINE_SIZE 12 |
1284 | ||
1285 | /* Alignment required for a trampoline in bits. */ | |
3d339ad2 | 1286 | |
27a55d6b | 1287 | #define TRAMPOLINE_ALIGNMENT 16 |
3d339ad2 | 1288 | |
27a55d6b RK |
1289 | /* Targets redefine this to invoke code to either flush the cache, |
1290 | or enable stack execution (or both). */ | |
1291 | ||
1292 | #ifndef FINALIZE_TRAMPOLINE | |
1293 | #define FINALIZE_TRAMPOLINE(TRAMP) | |
1294 | #endif | |
3d339ad2 RS |
1295 | |
1296 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1297 | FNADDR is an RTX for the address of the function's pure code. | |
c85f7c16 JL |
1298 | CXT is an RTX for the static chain value for the function. |
1299 | ||
1300 | We generate a two-instructions program at address TRAMP : | |
1301 | movea.l &CXT,%a0 | |
1302 | jmp FNADDR */ | |
3d339ad2 RS |
1303 | |
1304 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1305 | { \ | |
1d8eaa6b AS |
1306 | emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \ |
1307 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \ | |
1308 | emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \ | |
27a55d6b | 1309 | GEN_INT(0x4EF9)); \ |
1d8eaa6b | 1310 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \ |
27a55d6b | 1311 | FINALIZE_TRAMPOLINE(TRAMP); \ |
3d339ad2 RS |
1312 | } |
1313 | ||
1314 | /* This is the library routine that is used | |
1315 | to transfer control from the trampoline | |
e73cbb04 RK |
1316 | to the actual nested function. |
1317 | It is defined for backward compatibility, | |
1318 | for linking with object code that used the old | |
1319 | trampoline definition. */ | |
3d339ad2 RS |
1320 | |
1321 | /* A colon is used with no explicit operands | |
1322 | to cause the template string to be scanned for %-constructs. */ | |
1323 | /* The function name __transfer_from_trampoline is not actually used. | |
1324 | The function definition just permits use of "asm with operands" | |
1325 | (though the operand list is empty). */ | |
1326 | #define TRANSFER_FROM_TRAMPOLINE \ | |
1327 | void \ | |
1328 | __transfer_from_trampoline () \ | |
1329 | { \ | |
1330 | register char *a0 asm ("%a0"); \ | |
016c8440 | 1331 | asm (GLOBAL_ASM_OP "___trampoline"); \ |
3d339ad2 | 1332 | asm ("___trampoline:"); \ |
338818c7 RK |
1333 | asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ |
1334 | asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ | |
3d339ad2 RS |
1335 | asm ("rts":); \ |
1336 | } | |
1337 | \f | |
1338 | /* Addressing modes, and classification of registers for them. */ | |
1339 | ||
940da324 JL |
1340 | #define HAVE_POST_INCREMENT 1 |
1341 | /* #define HAVE_POST_DECREMENT 0 */ | |
3d339ad2 | 1342 | |
940da324 JL |
1343 | #define HAVE_PRE_DECREMENT 1 |
1344 | /* #define HAVE_PRE_INCREMENT 0 */ | |
3d339ad2 RS |
1345 | |
1346 | /* Macros to check register numbers against specific register classes. */ | |
1347 | ||
1348 | /* These assume that REGNO is a hard or pseudo reg number. | |
1349 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1350 | or a pseudo reg currently allocated to a suitable hard reg. | |
1351 | Since they use reg_renumber, they are safe only once reg_renumber | |
1352 | has been allocated, which happens in local-alloc.c. */ | |
1353 | ||
1354 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1355 | ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) | |
1356 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1357 | (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) | |
1358 | #define REGNO_OK_FOR_DATA_P(REGNO) \ | |
1359 | ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) | |
1360 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
1361 | (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) | |
1362 | #ifdef SUPPORT_SUN_FPA | |
1363 | #define REGNO_OK_FOR_FPA_P(REGNO) \ | |
1364 | (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56)) | |
1365 | #endif | |
1366 | ||
1367 | /* Now macros that check whether X is a register and also, | |
1368 | strictly, whether it is in a specified class. | |
1369 | ||
1370 | These macros are specific to the 68000, and may be used only | |
1371 | in code for printing assembler insns and in conditions for | |
1372 | define_optimization. */ | |
1373 | ||
1374 | /* 1 if X is a data register. */ | |
1375 | ||
1376 | #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) | |
1377 | ||
1378 | /* 1 if X is an fp register. */ | |
1379 | ||
1380 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
1381 | ||
1382 | /* 1 if X is an address register */ | |
1383 | ||
1384 | #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) | |
1385 | ||
1386 | #ifdef SUPPORT_SUN_FPA | |
1387 | /* 1 if X is a register in the Sun FPA. */ | |
1388 | #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X))) | |
1389 | #else | |
1390 | /* Answer must be no if we don't have an FPA. */ | |
1391 | #define FPA_REG_P(X) 0 | |
1392 | #endif | |
1393 | \f | |
1394 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1395 | ||
1396 | #define MAX_REGS_PER_ADDRESS 2 | |
1397 | ||
1398 | /* Recognize any constant value that is a valid address. */ | |
1399 | ||
6eff269e BK |
1400 | #define CONSTANT_ADDRESS_P(X) \ |
1401 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1402 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1403 | || GET_CODE (X) == HIGH) | |
3d339ad2 RS |
1404 | |
1405 | /* Nonzero if the constant value X is a legitimate general operand. | |
1406 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1407 | ||
1408 | #define LEGITIMATE_CONSTANT_P(X) 1 | |
1409 | ||
1410 | /* Nonzero if the constant value X is a legitimate general operand | |
1411 | when generating PIC code. It is given that flag_pic is on and | |
2c8ec431 DL |
1412 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. |
1413 | ||
1414 | PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are | |
1415 | accepted by insn predicates, but which would otherwise fail the | |
1416 | `general_operand' test. */ | |
1417 | ||
1418 | #ifndef REG_OK_STRICT | |
1419 | #define PCREL_GENERAL_OPERAND_OK 0 | |
1420 | #else | |
1421 | #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL) | |
1422 | #endif | |
3d339ad2 RS |
1423 | |
1424 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
c57eee67 RK |
1425 | ((! symbolic_operand (X, VOIDmode) \ |
1426 | && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X) \ | |
1427 | && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM \ | |
1428 | && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), \ | |
1429 | VOIDmode))) \ | |
2c8ec431 DL |
1430 | || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \ |
1431 | || PCREL_GENERAL_OPERAND_OK) | |
3d339ad2 RS |
1432 | |
1433 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1434 | and check its validity for a certain class. | |
1435 | We have two alternate definitions for each of them. | |
1436 | The usual definition accepts all pseudo regs; the other rejects | |
1437 | them unless they have been allocated suitable hard regs. | |
1438 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1439 | ||
1440 | Most source files want to accept pseudo regs in the hope that | |
1441 | they will get allocated to the class that the insn wants them to be in. | |
1442 | Source files for reload pass need to be strict. | |
1443 | After reload, it makes no difference, since pseudo regs have | |
1444 | been eliminated by then. */ | |
1445 | ||
1446 | #ifndef REG_OK_STRICT | |
1447 | ||
1448 | /* Nonzero if X is a hard reg that can be used as an index | |
1449 | or if it is a pseudo reg. */ | |
1450 | #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) | |
1451 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1452 | or if it is a pseudo reg. */ | |
1453 | #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) | |
1454 | ||
1455 | #else | |
1456 | ||
1457 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1458 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1459 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1460 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1461 | ||
1462 | #endif | |
1463 | \f | |
1464 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1465 | that is a valid memory address for an instruction. | |
1466 | The MODE argument is the machine mode for the MEM expression | |
1467 | that wants to use this address. | |
1468 | ||
1469 | When generating PIC, an address involving a SYMBOL_REF is legitimate | |
1470 | if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. | |
1471 | We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, | |
1472 | and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. | |
1473 | ||
1474 | Likewise for a LABEL_REF when generating PIC. | |
1475 | ||
1476 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
1477 | ||
22291e2f JW |
1478 | /* Allow SUBREG everywhere we allow REG. This results in better code. It |
1479 | also makes function inlining work when inline functions are called with | |
1480 | arguments that are SUBREGs. */ | |
1481 | ||
1482 | #define LEGITIMATE_BASE_REG_P(X) \ | |
1483 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1484 | || (GET_CODE (X) == SUBREG \ | |
1485 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1486 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
1487 | ||
3d339ad2 RS |
1488 | #define INDIRECTABLE_1_ADDRESS_P(X) \ |
1489 | ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ | |
22291e2f | 1490 | || LEGITIMATE_BASE_REG_P (X) \ |
3d339ad2 | 1491 | || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ |
22291e2f | 1492 | && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ |
3d339ad2 | 1493 | || (GET_CODE (X) == PLUS \ |
22291e2f | 1494 | && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ |
3d339ad2 | 1495 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ |
8b83b2a7 PJ |
1496 | && (TARGET_68020 \ |
1497 | || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \ | |
3d339ad2 RS |
1498 | || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ |
1499 | && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ | |
1500 | || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ | |
2c8ec431 | 1501 | && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) |
3d339ad2 | 1502 | |
3d339ad2 RS |
1503 | #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ |
1504 | { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } | |
1505 | ||
875c5a31 RS |
1506 | /* Only labels on dispatch tables are valid for indexing from. */ |
1507 | #define GO_IF_INDEXABLE_BASE(X, ADDR) \ | |
1508 | { rtx temp; \ | |
1509 | if (GET_CODE (X) == LABEL_REF \ | |
1510 | && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ | |
1511 | && GET_CODE (temp) == JUMP_INSN \ | |
1512 | && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ | |
1513 | || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ | |
1514 | goto ADDR; \ | |
22291e2f | 1515 | if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } |
3d339ad2 RS |
1516 | |
1517 | #define GO_IF_INDEXING(X, ADDR) \ | |
1518 | { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ | |
1519 | { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ | |
1520 | if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ | |
1521 | { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } | |
1522 | ||
1523 | #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ | |
1524 | { GO_IF_INDEXING (X, ADDR); \ | |
1525 | if (GET_CODE (X) == PLUS) \ | |
1526 | { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
9cf3ae46 | 1527 | && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \ |
3d339ad2 RS |
1528 | { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ |
1529 | if (GET_CODE (XEXP (X, 0)) == CONST_INT \ | |
9cf3ae46 | 1530 | && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \ |
3d339ad2 RS |
1531 | { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } |
1532 | ||
03db53b1 | 1533 | /* coldfire/5200 does not allow HImode index registers. */ |
3d339ad2 RS |
1534 | #define LEGITIMATE_INDEX_REG_P(X) \ |
1535 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
03db53b1 JW |
1536 | || (! TARGET_5200 \ |
1537 | && GET_CODE (X) == SIGN_EXTEND \ | |
3d339ad2 RS |
1538 | && GET_CODE (XEXP (X, 0)) == REG \ |
1539 | && GET_MODE (XEXP (X, 0)) == HImode \ | |
22291e2f JW |
1540 | && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ |
1541 | || (GET_CODE (X) == SUBREG \ | |
1542 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1543 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
3d339ad2 RS |
1544 | |
1545 | #define LEGITIMATE_INDEX_P(X) \ | |
1546 | (LEGITIMATE_INDEX_REG_P (X) \ | |
106bee4b | 1547 | || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \ |
3d339ad2 RS |
1548 | && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ |
1549 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1550 | && (INTVAL (XEXP (X, 1)) == 2 \ | |
1551 | || INTVAL (XEXP (X, 1)) == 4 \ | |
1c4e4dc4 | 1552 | || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200)))) |
3d339ad2 | 1553 | |
04e61bd4 RS |
1554 | /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ |
1555 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1556 | { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ | |
1557 | GO_IF_INDEXED_ADDRESS (X, ADDR); \ | |
1558 | if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ | |
1559 | && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ | |
1560 | && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ | |
1561 | goto ADDR; } | |
1562 | ||
1563 | /* Don't call memory_address_noforce for the address to fetch | |
1564 | the switch offset. This address is ok as it stands (see above), | |
1565 | but memory_address_noforce would alter it. */ | |
1566 | #define PIC_CASE_VECTOR_ADDRESS(index) index | |
3d339ad2 RS |
1567 | \f |
1568 | /* Try machine-dependent ways of modifying an illegitimate address | |
1569 | to be legitimate. If we find one, return the new, valid address. | |
1570 | This macro is used in only one place: `memory_address' in explow.c. | |
1571 | ||
1572 | OLDX is the address as it was before break_out_memory_refs was called. | |
1573 | In some cases it is useful to look at this to decide what needs to be done. | |
1574 | ||
1575 | MODE and WIN are passed so that this macro can use | |
1576 | GO_IF_LEGITIMATE_ADDRESS. | |
1577 | ||
1578 | It is always safe for this macro to do nothing. It exists to recognize | |
1579 | opportunities to optimize the output. | |
1580 | ||
1581 | For the 68000, we handle X+REG by loading X into a register R and | |
1582 | using R+REG. R will go in an address reg and indexing will be used. | |
1583 | However, if REG is a broken-out memory address or multiplication, | |
1584 | nothing needs to be done because REG can certainly go in an address reg. */ | |
1585 | ||
1586 | #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } | |
1587 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1588 | { register int ch = (X) != (OLDX); \ | |
1589 | if (GET_CODE (X) == PLUS) \ | |
1590 | { int copied = 0; \ | |
1591 | if (GET_CODE (XEXP (X, 0)) == MULT) \ | |
1592 | { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ | |
1593 | if (GET_CODE (XEXP (X, 1)) == MULT) \ | |
1594 | { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ | |
1595 | if (ch && GET_CODE (XEXP (X, 1)) == REG \ | |
1596 | && GET_CODE (XEXP (X, 0)) == REG) \ | |
1597 | goto WIN; \ | |
1598 | if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ | |
1599 | if (GET_CODE (XEXP (X, 0)) == REG \ | |
1600 | || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ | |
1601 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1602 | && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ | |
1603 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
1604 | register rtx val = force_operand (XEXP (X, 1), 0); \ | |
1605 | emit_move_insn (temp, val); \ | |
1606 | COPY_ONCE (X); \ | |
1607 | XEXP (X, 1) = temp; \ | |
1608 | goto WIN; } \ | |
1609 | else if (GET_CODE (XEXP (X, 1)) == REG \ | |
1610 | || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ | |
1611 | && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ | |
1612 | && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ | |
1613 | { register rtx temp = gen_reg_rtx (Pmode); \ | |
1614 | register rtx val = force_operand (XEXP (X, 0), 0); \ | |
1615 | emit_move_insn (temp, val); \ | |
1616 | COPY_ONCE (X); \ | |
1617 | XEXP (X, 0) = temp; \ | |
1618 | goto WIN; }}} | |
1619 | ||
1620 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1621 | has an effect that depends on the machine mode it is used for. | |
1622 | On the 68000, only predecrement and postincrement address depend thus | |
1623 | (the amount of decrement or increment being the length of the operand). */ | |
1624 | ||
1625 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1626 | if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL | |
1627 | \f | |
1628 | /* Specify the machine mode that this machine uses | |
1629 | for the index in the tablejump instruction. */ | |
1630 | #define CASE_VECTOR_MODE HImode | |
1631 | ||
18543a22 ILT |
1632 | /* Define as C expression which evaluates to nonzero if the tablejump |
1633 | instruction expects the table to contain offsets from the address of the | |
1634 | table. | |
1635 | Do not define this if the table should contain absolute addresses. */ | |
1636 | #define CASE_VECTOR_PC_RELATIVE 1 | |
3d339ad2 RS |
1637 | |
1638 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1639 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1640 | ||
1641 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1642 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1643 | ||
1644 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1645 | #define DEFAULT_SIGNED_CHAR 1 | |
1646 | ||
1647 | /* Don't cse the address of the function being compiled. */ | |
1648 | #define NO_RECURSIVE_FUNCTION_CSE | |
1649 | ||
1650 | /* Max number of bytes we can move from memory to memory | |
1651 | in one reasonably fast instruction. */ | |
1652 | #define MOVE_MAX 4 | |
1653 | ||
1654 | /* Define this if zero-extension is slow (more than one real instruction). */ | |
1655 | #define SLOW_ZERO_EXTEND | |
1656 | ||
1657 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
1658 | #define SLOW_BYTE_ACCESS 0 | |
1659 | ||
3d339ad2 RS |
1660 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1661 | is done just by pretending it is already truncated. */ | |
1662 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1663 | ||
1664 | /* We assume that the store-condition-codes instructions store 0 for false | |
1665 | and some other value for true. This is the value stored for true. */ | |
1666 | ||
37941398 | 1667 | #define STORE_FLAG_VALUE (-1) |
3d339ad2 RS |
1668 | |
1669 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
cb560352 | 1670 | #define PROMOTE_PROTOTYPES 1 |
3d339ad2 RS |
1671 | |
1672 | /* Specify the machine mode that pointers have. | |
1673 | After generation of rtl, the compiler makes no further distinction | |
1674 | between pointers and any other objects of this machine mode. */ | |
1675 | #define Pmode SImode | |
1676 | ||
1677 | /* A function address in a call instruction | |
1678 | is a byte address (for indexing purposes) | |
1679 | so give the MEM rtx a byte's mode. */ | |
1680 | #define FUNCTION_MODE QImode | |
1681 | ||
1682 | /* Compute the cost of computing a constant rtl expression RTX | |
1683 | whose rtx-code is CODE. The body of this macro is a portion | |
1684 | of a switch statement. If the code is computed here, | |
1685 | return it with a return statement. Otherwise, break from the switch. */ | |
1686 | ||
3bb22aee | 1687 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
3d339ad2 RS |
1688 | case CONST_INT: \ |
1689 | /* Constant zero is super cheap due to clr instruction. */ \ | |
1690 | if (RTX == const0_rtx) return 0; \ | |
8dbda09a RK |
1691 | /* if ((OUTER_CODE) == SET) */ \ |
1692 | return const_int_cost(RTX); \ | |
3d339ad2 RS |
1693 | case CONST: \ |
1694 | case LABEL_REF: \ | |
1695 | case SYMBOL_REF: \ | |
1696 | return 3; \ | |
1697 | case CONST_DOUBLE: \ | |
1698 | return 5; | |
1699 | ||
1700 | /* Compute the cost of various arithmetic operations. | |
1701 | These are vaguely right for a 68020. */ | |
1702 | /* The costs for long multiply have been adjusted to | |
1703 | work properly in synth_mult on the 68020, | |
1704 | relative to an average of the time for add and the time for shift, | |
1705 | taking away a little more because sometimes move insns are needed. */ | |
3296aff4 | 1706 | /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */ |
7a13fe96 RK |
1707 | #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13) |
1708 | #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5) | |
3296aff4 | 1709 | #define DIVW_COST (TARGET_68020 ? 27 : 12) |
3d339ad2 | 1710 | |
3bb22aee | 1711 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
3d339ad2 RS |
1712 | case PLUS: \ |
1713 | /* An lea costs about three times as much as a simple add. */ \ | |
1714 | if (GET_MODE (X) == SImode \ | |
8df73827 TG |
1715 | && GET_CODE (XEXP (X, 1)) == REG \ |
1716 | && GET_CODE (XEXP (X, 0)) == MULT \ | |
1717 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1718 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1719 | && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \ | |
1720 | || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \ | |
1721 | || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \ | |
3d339ad2 RS |
1722 | return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \ |
1723 | break; \ | |
1724 | case ASHIFT: \ | |
1725 | case ASHIFTRT: \ | |
7a13fe96 RK |
1726 | case LSHIFTRT: \ |
1727 | if (TARGET_68060) \ | |
1728 | return COSTS_N_INSNS(1); \ | |
3296aff4 TG |
1729 | if (! TARGET_68020) \ |
1730 | { \ | |
1731 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1732 | { \ | |
1733 | if (INTVAL (XEXP (X, 1)) < 16) \ | |
1734 | return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \ | |
1735 | else \ | |
1736 | /* We're using clrw + swap for these cases. */ \ | |
bd2e6d53 | 1737 | return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \ |
3296aff4 TG |
1738 | } \ |
1739 | return COSTS_N_INSNS (10); /* worst case */ \ | |
1740 | } \ | |
3d339ad2 | 1741 | /* A shift by a big integer takes an extra instruction. */ \ |
b4ac57ab RS |
1742 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ |
1743 | && (INTVAL (XEXP (X, 1)) == 16)) \ | |
1744 | return COSTS_N_INSNS (2); /* clrw;swap */ \ | |
3d339ad2 RS |
1745 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ |
1746 | && !(INTVAL (XEXP (X, 1)) > 0 \ | |
1747 | && INTVAL (XEXP (X, 1)) <= 8)) \ | |
1748 | return COSTS_N_INSNS (3); /* lsr #i,dn */ \ | |
1749 | break; \ | |
1750 | case MULT: \ | |
3296aff4 TG |
1751 | if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \ |
1752 | || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \ | |
1753 | && GET_MODE (X) == SImode) \ | |
1754 | return COSTS_N_INSNS (MULW_COST); \ | |
5d195441 | 1755 | if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ |
9fd3fbd0 | 1756 | return COSTS_N_INSNS (MULW_COST); \ |
3d339ad2 | 1757 | else \ |
9fd3fbd0 | 1758 | return COSTS_N_INSNS (MULL_COST); \ |
3d339ad2 RS |
1759 | case DIV: \ |
1760 | case UDIV: \ | |
1761 | case MOD: \ | |
1762 | case UMOD: \ | |
1763 | if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ | |
3296aff4 | 1764 | return COSTS_N_INSNS (DIVW_COST); /* div.w */ \ |
3d339ad2 RS |
1765 | return COSTS_N_INSNS (43); /* div.l */ |
1766 | \f | |
1767 | /* Tell final.c how to eliminate redundant test instructions. */ | |
1768 | ||
1769 | /* Here we define machine-dependent flags and fields in cc_status | |
1770 | (see `conditions.h'). */ | |
1771 | ||
1772 | /* Set if the cc value is actually in the 68881, so a floating point | |
1773 | conditional branch must be output. */ | |
1774 | #define CC_IN_68881 04000 | |
1775 | ||
1776 | /* Store in cc_status the expressions that the condition codes will | |
1777 | describe after execution of an instruction whose pattern is EXP. | |
1778 | Do not alter them if the instruction would not alter the cc's. */ | |
1779 | ||
1780 | /* On the 68000, all the insns to store in an address register fail to | |
1781 | set the cc's. However, in some cases these instructions can make it | |
1782 | possibly invalid to use the saved cc's. In those cases we clear out | |
1783 | some or all of the saved cc's so they won't be used. */ | |
1784 | ||
1785 | #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) | |
1786 | ||
1787 | #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ | |
1788 | { if (cc_prev_status.flags & CC_IN_68881) \ | |
1789 | return FLOAT; \ | |
1790 | if (cc_prev_status.flags & CC_NO_OVERFLOW) \ | |
1791 | return NO_OV; \ | |
1792 | return NORMAL; } | |
1793 | \f | |
1794 | /* Control the assembler format that we output. */ | |
1795 | ||
1796 | /* Output at beginning of assembler file. */ | |
1797 | ||
1798 | #define ASM_FILE_START(FILE) \ | |
1799 | fprintf (FILE, "#NO_APP\n"); | |
1800 | ||
1801 | /* Output to assembler file text saying following lines | |
1802 | may contain character constants, extra white space, comments, etc. */ | |
1803 | ||
1804 | #define ASM_APP_ON "#APP\n" | |
1805 | ||
1806 | /* Output to assembler file text saying following lines | |
1807 | no longer contain unusual constructs. */ | |
1808 | ||
1809 | #define ASM_APP_OFF "#NO_APP\n" | |
1810 | ||
1811 | /* Output before read-only data. */ | |
1812 | ||
6e7b07a7 | 1813 | #define TEXT_SECTION_ASM_OP "\t.text" |
3d339ad2 RS |
1814 | |
1815 | /* Output before writable data. */ | |
1816 | ||
6e7b07a7 | 1817 | #define DATA_SECTION_ASM_OP "\t.data" |
3d339ad2 RS |
1818 | |
1819 | /* Here are four prefixes that are used by asm_fprintf to | |
1820 | facilitate customization for alternate assembler syntaxes. | |
1821 | Machines with no likelihood of an alternate syntax need not | |
1822 | define these and need not use asm_fprintf. */ | |
1823 | ||
1824 | /* The prefix for register names. Note that REGISTER_NAMES | |
1825 | is supposed to include this prefix. */ | |
1826 | ||
1827 | #define REGISTER_PREFIX "" | |
1828 | ||
1829 | /* The prefix for local labels. You should be able to define this as | |
1830 | an empty string, or any arbitrary string (such as ".", ".L%", etc) | |
1831 | without having to make any other changes to account for the specific | |
1832 | definition. Note it is a string literal, not interpreted by printf | |
1833 | and friends. */ | |
1834 | ||
1835 | #define LOCAL_LABEL_PREFIX "" | |
1836 | ||
1837 | /* The prefix to add to user-visible assembler symbols. */ | |
1838 | ||
1839 | #define USER_LABEL_PREFIX "_" | |
1840 | ||
1841 | /* The prefix for immediate operands. */ | |
1842 | ||
1843 | #define IMMEDIATE_PREFIX "#" | |
1844 | ||
1845 | /* How to refer to registers in assembler output. | |
1846 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1847 | ||
1848 | #ifndef SUPPORT_SUN_FPA | |
1849 | ||
1850 | #define REGISTER_NAMES \ | |
1851 | {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ | |
1852 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ | |
1853 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } | |
1854 | ||
1855 | #else /* SUPPORTED_SUN_FPA */ | |
1856 | ||
1857 | #define REGISTER_NAMES \ | |
1858 | {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ | |
1859 | "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ | |
1860 | "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \ | |
1861 | "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \ | |
1862 | "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \ | |
1863 | "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \ | |
1864 | "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" } | |
1865 | ||
1866 | #endif /* defined SUPPORT_SUN_FPA */ | |
1867 | ||
1868 | /* How to renumber registers for dbx and gdb. | |
1869 | On the Sun-3, the floating point registers have numbers | |
1870 | 18 to 25, not 16 to 23 as they do in the compiler. */ | |
1871 | ||
1872 | #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) | |
1873 | ||
078e983e AS |
1874 | /* Before the prologue, RA is at 0(%sp). */ |
1875 | #define INCOMING_RETURN_ADDR_RTX \ | |
1d8eaa6b | 1876 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
078e983e AS |
1877 | |
1878 | /* We must not use the DBX register numbers for the DWARF 2 CFA column | |
1879 | numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. | |
1880 | Instead use the identity mapping. */ | |
1881 | #define DWARF_FRAME_REGNUM(REG) REG | |
1882 | ||
1883 | /* Before the prologue, the top of the frame is at 4(%sp). */ | |
1884 | #define INCOMING_FRAME_SP_OFFSET 4 | |
1885 | ||
3d339ad2 RS |
1886 | /* This is how to output the definition of a user-level label named NAME, |
1887 | such as the label on a static function or variable NAME. */ | |
1888 | ||
1889 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1890 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1891 | ||
1892 | /* This is how to output a command to make the user-level label named NAME | |
1893 | defined for reference from other files. */ | |
1894 | ||
6e7b07a7 | 1895 | #define GLOBAL_ASM_OP "\t.globl\t" |
3d339ad2 | 1896 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ |
016c8440 | 1897 | do { fprintf (FILE, "%s", GLOBAL_ASM_OP); \ |
9fd3fbd0 RS |
1898 | assemble_name (FILE, NAME); \ |
1899 | fputs ("\n", FILE);} while (0) | |
3d339ad2 RS |
1900 | |
1901 | /* This is how to output a reference to a user-level label named NAME. | |
1902 | `assemble_name' uses this. */ | |
1903 | ||
1904 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
338818c7 | 1905 | asm_fprintf (FILE, "%0U%s", NAME) |
3d339ad2 RS |
1906 | |
1907 | /* This is how to output an internal numbered label where | |
1908 | PREFIX is the class of label and NUM is the number within the class. */ | |
1909 | ||
1910 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
338818c7 | 1911 | asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM) |
3d339ad2 RS |
1912 | |
1913 | /* This is how to store into the string LABEL | |
1914 | the symbol_ref name of an internal numbered label where | |
1915 | PREFIX is the class of label and NUM is the number within the class. | |
1916 | This is suitable for output with `assemble_name'. */ | |
1917 | ||
1918 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
1919 | sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM) | |
1920 | ||
f6ba6a91 RS |
1921 | /* This is how to output a `long double' extended real constant. */ |
1922 | ||
1923 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ | |
1924 | do { long l[3]; \ | |
1925 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ | |
97b57a81 | 1926 | fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \ |
f6ba6a91 RS |
1927 | } while (0) |
1928 | ||
3d339ad2 RS |
1929 | /* This is how to output an assembler line defining a `double' constant. */ |
1930 | ||
f6ba6a91 RS |
1931 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
1932 | do { char dstr[30]; \ | |
1933 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ | |
1934 | fprintf (FILE, "\t.double 0r%s\n", dstr); \ | |
1935 | } while (0) | |
3d339ad2 RS |
1936 | |
1937 | /* This is how to output an assembler line defining a `float' constant. */ | |
1938 | ||
f6ba6a91 RS |
1939 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
1940 | do { long l; \ | |
1941 | REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ | |
97b57a81 | 1942 | fprintf (FILE, "\t.long 0x%lx\n", l); \ |
3d339ad2 RS |
1943 | } while (0) |
1944 | ||
3d339ad2 RS |
1945 | /* This is how to output an assembler line defining an `int' constant. */ |
1946 | ||
1947 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
1948 | ( fprintf (FILE, "\t.long "), \ | |
1949 | output_addr_const (FILE, (VALUE)), \ | |
1950 | fprintf (FILE, "\n")) | |
1951 | ||
1952 | /* Likewise for `char' and `short' constants. */ | |
1953 | ||
1954 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
1955 | ( fprintf (FILE, "\t.word "), \ | |
1956 | output_addr_const (FILE, (VALUE)), \ | |
1957 | fprintf (FILE, "\n")) | |
1958 | ||
1959 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
1960 | ( fprintf (FILE, "\t.byte "), \ | |
1961 | output_addr_const (FILE, (VALUE)), \ | |
1962 | fprintf (FILE, "\n")) | |
1963 | ||
1964 | /* This is how to output an assembler line for a numeric constant byte. */ | |
1965 | ||
1966 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
1967 | fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) | |
1968 | ||
1969 | /* This is how to output an insn to push a register on the stack. | |
1970 | It need not be very fast code. */ | |
1971 | ||
1972 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
1973 | asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) | |
1974 | ||
1975 | /* This is how to output an insn to pop a register from the stack. | |
1976 | It need not be very fast code. */ | |
1977 | ||
1978 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
1979 | asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) | |
1980 | ||
1981 | /* This is how to output an element of a case-vector that is absolute. | |
1982 | (The 68000 does not use such vectors, | |
1983 | but we must define this macro anyway.) */ | |
1984 | ||
1985 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1986 | asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) | |
1987 | ||
1988 | /* This is how to output an element of a case-vector that is relative. */ | |
1989 | ||
33f7f353 | 1990 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3d339ad2 RS |
1991 | asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) |
1992 | ||
1993 | /* This is how to output an assembler line | |
1994 | that says to advance the location counter | |
1995 | to a multiple of 2**LOG bytes. */ | |
1996 | ||
b4ac57ab RS |
1997 | /* We don't have a way to align to more than a two-byte boundary, so do the |
1998 | best we can and don't complain. */ | |
3d339ad2 | 1999 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ |
b4ac57ab RS |
2000 | if ((LOG) >= 1) \ |
2001 | fprintf (FILE, "\t.even\n"); | |
3d339ad2 RS |
2002 | |
2003 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
2004 | fprintf (FILE, "\t.skip %u\n", (SIZE)) | |
2005 | ||
2006 | /* This says how to output an assembler line | |
2007 | to define a global common symbol. */ | |
2008 | ||
2009 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
2010 | ( fputs (".comm ", (FILE)), \ | |
2011 | assemble_name ((FILE), (NAME)), \ | |
2012 | fprintf ((FILE), ",%u\n", (ROUNDED))) | |
2013 | ||
2014 | /* This says how to output an assembler line | |
2015 | to define a local common symbol. */ | |
2016 | ||
2017 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
2018 | ( fputs (".lcomm ", (FILE)), \ | |
2019 | assemble_name ((FILE), (NAME)), \ | |
2020 | fprintf ((FILE), ",%u\n", (ROUNDED))) | |
2021 | ||
2022 | /* Store in OUTPUT a string (made with alloca) containing | |
2023 | an assembler-name for a local static variable named NAME. | |
2024 | LABELNO is an integer which is different for each call. */ | |
2025 | ||
2026 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2027 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2028 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2029 | ||
3d339ad2 RS |
2030 | /* Output a float value (represented as a C double) as an immediate operand. |
2031 | This macro is a 68k-specific macro. */ | |
f6ba6a91 RS |
2032 | |
2033 | #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ | |
2034 | do { \ | |
2035 | if (CODE == 'f') \ | |
2036 | { \ | |
2037 | char dstr[30]; \ | |
2038 | REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ | |
2039 | asm_fprintf ((FILE), "%I0r%s", dstr); \ | |
2040 | } \ | |
2041 | else \ | |
2042 | { \ | |
2043 | long l; \ | |
2044 | REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ | |
97b57a81 | 2045 | asm_fprintf ((FILE), "%I0x%lx", l); \ |
f6ba6a91 RS |
2046 | } \ |
2047 | } while (0) | |
3d339ad2 RS |
2048 | |
2049 | /* Output a double value (represented as a C double) as an immediate operand. | |
2050 | This macro is a 68k-specific macro. */ | |
2051 | #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ | |
f6ba6a91 RS |
2052 | do { char dstr[30]; \ |
2053 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ | |
2054 | asm_fprintf (FILE, "%I0r%s", dstr); \ | |
2055 | } while (0) | |
2056 | ||
2057 | /* Note, long double immediate operands are not actually | |
2058 | generated by m68k.md. */ | |
2059 | #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ | |
2060 | do { char dstr[30]; \ | |
2061 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ | |
2062 | asm_fprintf (FILE, "%I0r%s", dstr); \ | |
2063 | } while (0) | |
3d339ad2 RS |
2064 | |
2065 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2066 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2067 | For `%' followed by punctuation, CODE is the punctuation and X is null. | |
2068 | ||
2069 | On the 68000, we use several CODE characters: | |
2070 | '.' for dot needed in Motorola-style opcode names. | |
2071 | '-' for an operand pushing on the stack: | |
2072 | sp@-, -(sp) or -(%sp) depending on the style of syntax. | |
2073 | '+' for an operand pushing on the stack: | |
2074 | sp@+, (sp)+ or (%sp)+ depending on the style of syntax. | |
2075 | '@' for a reference to the top word on the stack: | |
2076 | sp@, (sp) or (%sp) depending on the style of syntax. | |
2077 | '#' for an immediate operand prefix (# in MIT and Motorola syntax | |
2078 | but & in SGS syntax). | |
7c129456 | 2079 | '!' for the fpcr register (used in some float-to-fixed conversions). |
3d339ad2 RS |
2080 | '$' for the letter `s' in an op code, but only on the 68040. |
2081 | '&' for the letter `d' in an op code, but only on the 68040. | |
2ac5f14a | 2082 | '/' for register prefix needed by longlong.h. |
3d339ad2 RS |
2083 | |
2084 | 'b' for byte insn (no effect, on the Sun; this is for the ISI). | |
2085 | 'd' to force memory addressing to be absolute, not relative. | |
2086 | 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) | |
2c8ec431 DL |
2087 | 'o' for operands to go directly to output_operand_address (bypassing |
2088 | print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) | |
3d339ad2 RS |
2089 | 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather |
2090 | than directly). Second part of 'y' below. | |
2091 | 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), | |
2092 | or print pair of registers as rx:ry. | |
2093 | 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs | |
2094 | CONST_DOUBLE's as SunFPA constant RAM registers if | |
2095 | possible, so it should not be used except for the SunFPA. */ | |
2096 | ||
2097 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
2098 | ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ | |
2099 | || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ | |
2ac5f14a | 2100 | || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') |
3d339ad2 | 2101 | |
3d339ad2 RS |
2102 | /* A C compound statement to output to stdio stream STREAM the |
2103 | assembler syntax for an instruction operand X. X is an RTL | |
2104 | expression. | |
2105 | ||
2106 | CODE is a value that can be used to specify one of several ways | |
2107 | of printing the operand. It is used when identical operands | |
2108 | must be printed differently depending on the context. CODE | |
2109 | comes from the `%' specification that was used to request | |
2110 | printing of the operand. If the specification was just `%DIGIT' | |
2111 | then CODE is 0; if the specification was `%LTR DIGIT' then CODE | |
2112 | is the ASCII code for LTR. | |
2113 | ||
2114 | If X is a register, this macro should print the register's name. | |
2115 | The names can be found in an array `reg_names' whose type is | |
2116 | `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. | |
2117 | ||
2118 | When the machine description has a specification `%PUNCT' (a `%' | |
2119 | followed by a punctuation character), this macro is called with | |
2120 | a null pointer for X and the punctuation character for CODE. | |
2121 | ||
2122 | See m68k.c for the m68k specific codes. */ | |
2123 | ||
2124 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2125 | ||
2126 | /* A C compound statement to output to stdio stream STREAM the | |
2127 | assembler syntax for an instruction operand that is a memory | |
2128 | reference whose address is ADDR. ADDR is an RTL expression. | |
2129 | ||
2130 | On some machines, the syntax for a symbolic address depends on | |
2131 | the section that the address refers to. On these machines, | |
2132 | define the macro `ENCODE_SECTION_INFO' to store the information | |
2133 | into the `symbol_ref', and then check for it here. */ | |
2134 | ||
2135 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2136 | ||
9e62c7f2 | 2137 | /* Variables in m68k.c */ |
577c6ece AS |
2138 | extern const char *m68k_align_loops_string; |
2139 | extern const char *m68k_align_jumps_string; | |
2140 | extern const char *m68k_align_funcs_string; | |
9e62c7f2 RK |
2141 | extern int m68k_align_loops; |
2142 | extern int m68k_align_jumps; | |
2143 | extern int m68k_align_funcs; | |
2b3600ac | 2144 | extern int m68k_last_compare_had_fp_operands; |
9e62c7f2 | 2145 | |
3d339ad2 RS |
2146 | \f |
2147 | /* | |
2148 | Local variables: | |
2149 | version-control: t | |
2150 | End: | |
2151 | */ |