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Commit | Line | Data |
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c65ebc55 | 1 | ;; IA-64 Machine description template |
bbbbb16a ILT |
2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, |
3 | ;; 2009 Free Software Foundation, Inc. | |
c65ebc55 JW |
4 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
5 | ;; David Mosberger <davidm@hpl.hp.com>. | |
6 | ||
3bed2930 | 7 | ;; This file is part of GCC. |
c65ebc55 | 8 | |
3bed2930 | 9 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 10 | ;; it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | ;; the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
12 | ;; any later version. |
13 | ||
3bed2930 | 14 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
18 | ||
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
c65ebc55 JW |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
086c0f96 | 51 | (define_constants |
7b6e506e RH |
52 | [; Relocations |
53 | (UNSPEC_LTOFF_DTPMOD 0) | |
54 | (UNSPEC_LTOFF_DTPREL 1) | |
55 | (UNSPEC_DTPREL 2) | |
56 | (UNSPEC_LTOFF_TPREL 3) | |
57 | (UNSPEC_TPREL 4) | |
5e6c8b64 | 58 | (UNSPEC_DTPMOD 5) |
7b6e506e RH |
59 | |
60 | (UNSPEC_LD_BASE 9) | |
61 | (UNSPEC_GR_SPILL 10) | |
62 | (UNSPEC_GR_RESTORE 11) | |
63 | (UNSPEC_FR_SPILL 12) | |
64 | (UNSPEC_FR_RESTORE 13) | |
65 | (UNSPEC_FR_RECIP_APPROX 14) | |
66 | (UNSPEC_PRED_REL_MUTEX 15) | |
c407570a | 67 | (UNSPEC_GETF_EXP 16) |
7b6e506e RH |
68 | (UNSPEC_PIC_CALL 17) |
69 | (UNSPEC_MF 18) | |
70 | (UNSPEC_CMPXCHG_ACQ 19) | |
71 | (UNSPEC_FETCHADD_ACQ 20) | |
72 | (UNSPEC_BSP_VALUE 21) | |
73 | (UNSPEC_FLUSHRS 22) | |
74 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
75 | (UNSPEC_ADDP4 24) |
76 | (UNSPEC_PROLOGUE_USE 25) | |
af1e5518 | 77 | (UNSPEC_RET_ADDR 26) |
b38ba463 ZW |
78 | (UNSPEC_SETF_EXP 27) |
79 | (UNSPEC_FR_SQRT_RECIP_APPROX 28) | |
f526a3c8 | 80 | (UNSPEC_SHRP 29) |
046625fa | 81 | (UNSPEC_COPYSIGN 30) |
b4e3537b | 82 | (UNSPEC_VECT_EXTR 31) |
048d0d36 MK |
83 | (UNSPEC_LDA 40) |
84 | (UNSPEC_LDS 41) | |
388092d5 AB |
85 | (UNSPEC_LDS_A 42) |
86 | (UNSPEC_LDSA 43) | |
87 | (UNSPEC_LDCCLR 44) | |
88 | (UNSPEC_LDCNC 45) | |
89 | (UNSPEC_CHKACLR 46) | |
90 | (UNSPEC_CHKANC 47) | |
91 | (UNSPEC_CHKS 48) | |
92 | (UNSPEC_FR_RECIP_APPROX_RES 49) | |
93 | (UNSPEC_FR_SQRT_RECIP_APPROX_RES 50) | |
086c0f96 RH |
94 | ]) |
95 | ||
96 | (define_constants | |
97 | [(UNSPECV_ALLOC 0) | |
98 | (UNSPECV_BLOCKAGE 1) | |
99 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
100 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
101 | (UNSPECV_SET_BSP 4) |
102 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
103 | (UNSPECV_PSAC_NORMAL 6) | |
b39eb2f9 | 104 | (UNSPECV_SETJMP_RECEIVER 7) |
39a5cfa4 | 105 | (UNSPECV_GOTO_RECEIVER 8) |
086c0f96 | 106 | ]) |
e543e219 | 107 | |
7905f799 | 108 | (include "predicates.md") |
13f70342 | 109 | (include "constraints.md") |
c65ebc55 JW |
110 | \f |
111 | ;; :::::::::::::::::::: | |
112 | ;; :: | |
113 | ;; :: Attributes | |
114 | ;; :: | |
115 | ;; :::::::::::::::::::: | |
116 | ||
30028c85 VM |
117 | ;; Processor type. This attribute must exactly match the processor_type |
118 | ;; enumeration in ia64.h. | |
bbbbb16a ILT |
119 | (define_attr "cpu" "itanium,itanium2" |
120 | (const (symbol_ref "((enum attr_cpu) ia64_tune)"))) | |
30028c85 | 121 | |
c65ebc55 JW |
122 | ;; Instruction type. This primarily determines how instructions can be |
123 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
124 | ||
125 | ;; A alu, can go in I or M syllable of a bundle | |
126 | ;; I integer | |
127 | ;; M memory | |
128 | ;; F floating-point | |
129 | ;; B branch | |
130 | ;; L long immediate, takes two syllables | |
131 | ;; S stop bit | |
132 | ||
133 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
134 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
135 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
136 | ;; which emit instruction that can go in any slot (e.g. nop). | |
137 | ||
1d5d7a21 | 138 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
a71aef0b | 139 | fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, |
048d0d36 | 140 | ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, |
f61134e8 RH |
141 | st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, |
142 | nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 143 | (const_string "unknown")) |
52e12ad0 | 144 | |
048d0d36 | 145 | ;; chk_s_i has an I and an M form; use type A for convenience. |
2130b7fb | 146 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" |
a71aef0b | 147 | (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") |
52e12ad0 BS |
148 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
149 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 150 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
048d0d36 MK |
151 | (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M") |
152 | (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua") | |
f61134e8 | 153 | (const_string "A") |
2130b7fb BS |
154 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") |
155 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
156 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
157 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
158 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
159 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 160 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 161 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
162 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
163 | (const_string "unknown"))) | |
c65ebc55 | 164 | |
2130b7fb BS |
165 | (define_attr "itanium_requires_unit0" "no,yes" |
166 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
167 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
168 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
169 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
170 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
171 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
172 | (const_string "no"))) | |
173 | ||
e5bde68a RH |
174 | ;; Predication. True iff this instruction can be predicated. |
175 | ||
176 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
177 | ||
fa978426 AS |
178 | ;; Empty. True iff this insn does not generate any code. |
179 | ||
180 | (define_attr "empty" "no,yes" (const_string "no")) | |
181 | ||
68e11b42 JW |
182 | ;; True iff this insn must be the first insn of an instruction group. |
183 | ;; This is true for the alloc instruction, and will also be true of others | |
184 | ;; when we have full intrinsics support. | |
185 | ||
186 | (define_attr "first_insn" "no,yes" (const_string "no")) | |
048d0d36 MK |
187 | |
188 | (define_attr "data_speculative" "no,yes" (const_string "no")) | |
189 | ||
190 | (define_attr "control_speculative" "no,yes" (const_string "no")) | |
191 | ||
192 | (define_attr "check_load" "no,yes" (const_string "no")) | |
388092d5 AB |
193 | |
194 | (define_attr "speculable1" "no,yes" (const_string "no")) | |
195 | ||
196 | (define_attr "speculable2" "no,yes" (const_string "no")) | |
c65ebc55 | 197 | \f |
30028c85 VM |
198 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
199 | ;; bundling. | |
200 | ||
201 | (automata_option "ndfa") | |
202 | ||
203 | ;; Uncomment the following line to output automata for debugging. | |
204 | ;; (automata_option "v") | |
205 | ||
206 | (automata_option "w") | |
207 | ||
30028c85 VM |
208 | (include "itanium1.md") |
209 | (include "itanium2.md") | |
210 | ||
c65ebc55 JW |
211 | \f |
212 | ;; :::::::::::::::::::: | |
213 | ;; :: | |
214 | ;; :: Moves | |
215 | ;; :: | |
216 | ;; :::::::::::::::::::: | |
217 | ||
f2f90c63 RH |
218 | ;; Set of a single predicate register. This is only used to implement |
219 | ;; pr-to-pr move and complement. | |
220 | ||
221 | (define_insn "*movcci" | |
222 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
223 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
224 | "" | |
225 | "@ | |
226 | cmp.ne %0, p0 = r0, r0 | |
227 | cmp.eq %0, p0 = r0, r0 | |
228 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 229 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
230 | (set_attr "predicable" "no")]) |
231 | ||
232 | (define_insn "movbi" | |
b6fb7d46 JW |
233 | [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
234 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
235 | "" |
236 | "@ | |
237 | cmp.ne %0, %I0 = r0, r0 | |
238 | cmp.eq %0, %I0 = r0, r0 | |
239 | # | |
240 | # | |
241 | tbit.nz %0, %I0 = %1, 0 | |
242 | adds %0 = %1, r0 | |
243 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
244 | st1%Q0 %0 = %1%P0 |
245 | mov %0 = %1" | |
388092d5 AB |
246 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu") |
247 | (set_attr "speculable1" "yes") | |
248 | (set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")]) | |
f2f90c63 RH |
249 | |
250 | (define_split | |
251 | [(set (match_operand:BI 0 "register_operand" "") | |
252 | (match_operand:BI 1 "register_operand" ""))] | |
253 | "reload_completed | |
254 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
255 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
256 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
257 | (set (match_dup 0) (const_int 1))) | |
258 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
259 | (set (match_dup 0) (const_int 0)))] | |
260 | "") | |
261 | ||
262 | (define_split | |
263 | [(set (match_operand:BI 0 "register_operand" "") | |
264 | (match_operand:BI 1 "register_operand" ""))] | |
265 | "reload_completed | |
266 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
267 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
268 | [(set (match_dup 2) (match_dup 4)) | |
269 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 270 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
271 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
272 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
273 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
274 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
275 | ||
c65ebc55 JW |
276 | (define_expand "movqi" |
277 | [(set (match_operand:QI 0 "general_operand" "") | |
278 | (match_operand:QI 1 "general_operand" ""))] | |
279 | "" | |
c65ebc55 | 280 | { |
7b6e506e RH |
281 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
282 | if (!op1) | |
283 | DONE; | |
284 | operands[1] = op1; | |
1d5d7a21 | 285 | }) |
c65ebc55 | 286 | |
388092d5 | 287 | (define_insn "movqi_internal" |
4b983fdc RH |
288 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
289 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 290 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 291 | "@ |
13da91fd | 292 | mov %0 = %r1 |
c65ebc55 JW |
293 | addl %0 = %1, r0 |
294 | ld1%O1 %0 = %1%P1 | |
13da91fd | 295 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 296 | getf.sig %0 = %1 |
13da91fd RH |
297 | setf.sig %0 = %r1 |
298 | mov %0 = %1" | |
388092d5 AB |
299 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
300 | (set_attr "speculable1" "yes") | |
301 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
302 | |
303 | (define_expand "movhi" | |
304 | [(set (match_operand:HI 0 "general_operand" "") | |
305 | (match_operand:HI 1 "general_operand" ""))] | |
306 | "" | |
c65ebc55 | 307 | { |
7b6e506e RH |
308 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
309 | if (!op1) | |
310 | DONE; | |
311 | operands[1] = op1; | |
1d5d7a21 | 312 | }) |
c65ebc55 | 313 | |
388092d5 | 314 | (define_insn "movhi_internal" |
4b983fdc RH |
315 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
316 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 317 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 318 | "@ |
13da91fd | 319 | mov %0 = %r1 |
c65ebc55 JW |
320 | addl %0 = %1, r0 |
321 | ld2%O1 %0 = %1%P1 | |
13da91fd | 322 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 323 | getf.sig %0 = %1 |
13da91fd RH |
324 | setf.sig %0 = %r1 |
325 | mov %0 = %1" | |
388092d5 AB |
326 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
327 | (set_attr "speculable1" "yes") | |
328 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
329 | |
330 | (define_expand "movsi" | |
331 | [(set (match_operand:SI 0 "general_operand" "") | |
332 | (match_operand:SI 1 "general_operand" ""))] | |
333 | "" | |
c65ebc55 | 334 | { |
7b6e506e RH |
335 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
336 | if (!op1) | |
337 | DONE; | |
338 | operands[1] = op1; | |
1d5d7a21 | 339 | }) |
c65ebc55 | 340 | |
388092d5 | 341 | (define_insn "movsi_internal" |
4e483a22 JB |
342 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d") |
343 | (match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))] | |
aebf2462 | 344 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 345 | "@ |
13da91fd | 346 | mov %0 = %r1 |
c65ebc55 | 347 | addl %0 = %1, r0 |
4e483a22 | 348 | addp4 %0 = %1 - 0x100000000, r0 |
c65ebc55 JW |
349 | movl %0 = %1 |
350 | ld4%O1 %0 = %1%P1 | |
13da91fd | 351 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 352 | getf.sig %0 = %1 |
13da91fd | 353 | setf.sig %0 = %r1 |
97e242b0 RH |
354 | mov %0 = %1 |
355 | mov %0 = %1 | |
356 | mov %0 = %r1" | |
1d5d7a21 | 357 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
388092d5 AB |
358 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m") |
359 | (set_attr "speculable1" "yes") | |
360 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")]) | |
c65ebc55 JW |
361 | |
362 | (define_expand "movdi" | |
363 | [(set (match_operand:DI 0 "general_operand" "") | |
364 | (match_operand:DI 1 "general_operand" ""))] | |
365 | "" | |
c65ebc55 | 366 | { |
7b6e506e RH |
367 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
368 | if (!op1) | |
369 | DONE; | |
370 | operands[1] = op1; | |
1d5d7a21 | 371 | }) |
c65ebc55 | 372 | |
388092d5 | 373 | (define_insn "movdi_internal" |
4b983fdc | 374 | [(set (match_operand:DI 0 "destination_operand" |
4e483a22 | 375 | "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 376 | (match_operand:DI 1 "move_operand" |
4e483a22 | 377 | "rO,JT,j,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 378 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
379 | { |
380 | static const char * const alt[] = { | |
1d5d7a21 RH |
381 | "%,mov %0 = %r1", |
382 | "%,addl %0 = %1, r0", | |
4e483a22 | 383 | "%,addp4 %0 = %1 - 0x100000000, r0", |
1d5d7a21 RH |
384 | "%,movl %0 = %1", |
385 | "%,ld8%O1 %0 = %1%P1", | |
386 | "%,st8%Q0 %0 = %r1%P0", | |
387 | "%,getf.sig %0 = %1", | |
388 | "%,setf.sig %0 = %r1", | |
389 | "%,mov %0 = %1", | |
390 | "%,ldf8 %0 = %1%P1", | |
391 | "%,stf8 %0 = %1%P0", | |
392 | "%,mov %0 = %1", | |
393 | "%,mov %0 = %r1", | |
394 | "%,mov %0 = %1", | |
395 | "%,mov %0 = %1", | |
396 | "%,mov %0 = %1", | |
397 | "%,mov %0 = %1", | |
398 | "mov %0 = pr", | |
399 | "mov pr = %1, -1" | |
9b7bf67d RH |
400 | }; |
401 | ||
e820471b NS |
402 | gcc_assert (which_alternative != 2 || TARGET_NO_PIC |
403 | || !symbolic_operand (operands[1], VOIDmode)); | |
9b7bf67d RH |
404 | |
405 | return alt[which_alternative]; | |
1d5d7a21 | 406 | } |
388092d5 AB |
407 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr") |
408 | (set_attr "speculable1" "yes") | |
409 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")]) | |
c65ebc55 | 410 | |
3abcb3a7 | 411 | (define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI]) |
f90b7a5a | 412 | (define_mode_iterator MODE_FOR_CMP [BI SI DI SF DF XF (TF "TARGET_HPUX")]) |
3abcb3a7 | 413 | (define_mode_iterator MODE_FOR_EXTEND [QI HI SI]) |
048d0d36 MK |
414 | |
415 | (define_mode_attr output_a [ | |
416 | (BI "ld1.a %0 = %1%P1") | |
417 | (QI "ld1.a %0 = %1%P1") | |
418 | (HI "ld2.a %0 = %1%P1") | |
419 | (SI "ld4.a %0 = %1%P1") | |
420 | (DI | |
421 | "@ | |
422 | ld8.a %0 = %1%P1 | |
423 | ldf8.a %0 = %1%P1") | |
424 | (SF | |
425 | "@ | |
426 | ldfs.a %0 = %1%P1 | |
427 | ld4.a %0 = %1%P1") | |
428 | (DF | |
429 | "@ | |
430 | ldfd.a %0 = %1%P1 | |
431 | ld8.a %0 = %1%P1") | |
432 | (XF "ldfe.a %0 = %1%P1") | |
433 | (TI "ldfp8.a %X0 = %1%P1")]) | |
434 | ||
435 | (define_mode_attr output_s [ | |
436 | (BI "ld1.s %0 = %1%P1") | |
437 | (QI "ld1.s %0 = %1%P1") | |
438 | (HI "ld2.s %0 = %1%P1") | |
439 | (SI "ld4.s %0 = %1%P1") | |
440 | (DI | |
441 | "@ | |
442 | ld8.s %0 = %1%P1 | |
443 | ldf8.s %0 = %1%P1") | |
444 | (SF | |
445 | "@ | |
446 | ldfs.s %0 = %1%P1 | |
447 | ld4.s %0 = %1%P1") | |
448 | (DF | |
449 | "@ | |
450 | ldfd.s %0 = %1%P1 | |
451 | ld8.s %0 = %1%P1") | |
452 | (XF "ldfe.s %0 = %1%P1") | |
453 | (TI "ldfp8.s %X0 = %1%P1")]) | |
454 | ||
455 | (define_mode_attr output_sa [ | |
456 | (BI "ld1.sa %0 = %1%P1") | |
457 | (QI "ld1.sa %0 = %1%P1") | |
458 | (HI "ld2.sa %0 = %1%P1") | |
459 | (SI "ld4.sa %0 = %1%P1") | |
460 | (DI | |
461 | "@ | |
462 | ld8.sa %0 = %1%P1 | |
463 | ldf8.sa %0 = %1%P1") | |
464 | (SF | |
465 | "@ | |
466 | ldfs.sa %0 = %1%P1 | |
467 | ld4.sa %0 = %1%P1") | |
468 | (DF | |
469 | "@ | |
470 | ldfd.sa %0 = %1%P1 | |
471 | ld8.sa %0 = %1%P1") | |
472 | (XF "ldfe.sa %0 = %1%P1") | |
473 | (TI "ldfp8.sa %X0 = %1%P1")]) | |
474 | ||
475 | (define_mode_attr output_c_clr [ | |
476 | (BI "ld1.c.clr%O1 %0 = %1%P1") | |
477 | (QI "ld1.c.clr%O1 %0 = %1%P1") | |
478 | (HI "ld2.c.clr%O1 %0 = %1%P1") | |
479 | (SI "ld4.c.clr%O1 %0 = %1%P1") | |
480 | (DI | |
481 | "@ | |
482 | ld8.c.clr%O1 %0 = %1%P1 | |
483 | ldf8.c.clr %0 = %1%P1") | |
484 | (SF | |
485 | "@ | |
486 | ldfs.c.clr %0 = %1%P1 | |
487 | ld4.c.clr%O1 %0 = %1%P1") | |
488 | (DF | |
489 | "@ | |
490 | ldfd.c.clr %0 = %1%P1 | |
491 | ld8.c.clr%O1 %0 = %1%P1") | |
492 | (XF "ldfe.c.clr %0 = %1%P1") | |
493 | (TI "ldfp8.c.clr %X0 = %1%P1")]) | |
494 | ||
388092d5 AB |
495 | (define_mode_attr output_c_nc [ |
496 | (BI "ld1.c.nc%O1 %0 = %1%P1") | |
497 | (QI "ld1.c.nc%O1 %0 = %1%P1") | |
498 | (HI "ld2.c.nc%O1 %0 = %1%P1") | |
499 | (SI "ld4.c.nc%O1 %0 = %1%P1") | |
500 | (DI | |
501 | "@ | |
502 | ld8.c.nc%O1 %0 = %1%P1 | |
503 | ldf8.c.nc %0 = %1%P1") | |
504 | (SF | |
505 | "@ | |
506 | ldfs.c.nc %0 = %1%P1 | |
507 | ld4.c.nc%O1 %0 = %1%P1") | |
508 | (DF | |
509 | "@ | |
510 | ldfd.c.nc %0 = %1%P1 | |
511 | ld8.c.nc%O1 %0 = %1%P1") | |
512 | (XF "ldfe.c.nc %0 = %1%P1") | |
513 | (TI "ldfp8.c.nc %X0 = %1%P1")]) | |
514 | ||
048d0d36 MK |
515 | (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")]) |
516 | (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")]) | |
517 | (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")]) | |
518 | ||
519 | (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) | |
520 | ||
f6ec1d11 MK |
521 | ;; Define register predicate prefix. |
522 | ;; We can generate speculative loads only for general and fp registers - this | |
ea2c620c | 523 | ;; is constrained in ia64.c: ia64_speculate_insn (). |
048d0d36 MK |
524 | (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) |
525 | ||
526 | (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) | |
527 | (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")]) | |
528 | (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")]) | |
529 | ||
530 | (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")]) | |
531 | ||
532 | (define_insn "mov<mode>_advanced" | |
533 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
534 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))] | |
535 | "ia64_move_ok (operands[0], operands[1])" | |
536 | "<output_a>" | |
537 | [(set_attr "itanium_class" "<ld_class>") | |
538 | (set_attr "data_speculative" "<attr_yes>")]) | |
539 | ||
540 | (define_insn "zero_extend<mode>di2_advanced" | |
541 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
542 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))] | |
543 | "" | |
544 | "<output_a>" | |
545 | [(set_attr "itanium_class" "<ld_class>") | |
546 | (set_attr "data_speculative" "<attr_yes>")]) | |
547 | ||
548 | (define_insn "mov<mode>_speculative" | |
549 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
550 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))] | |
551 | "ia64_move_ok (operands[0], operands[1])" | |
552 | "<output_s>" | |
553 | [(set_attr "itanium_class" "<ld_class>") | |
554 | (set_attr "control_speculative" "<attr_yes>")]) | |
555 | ||
556 | (define_insn "zero_extend<mode>di2_speculative" | |
557 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
558 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))] | |
559 | "" | |
560 | "<output_s>" | |
561 | [(set_attr "itanium_class" "<ld_class>") | |
562 | (set_attr "control_speculative" "<attr_yes>")]) | |
563 | ||
564 | (define_insn "mov<mode>_speculative_advanced" | |
565 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
566 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))] | |
567 | "ia64_move_ok (operands[0], operands[1])" | |
568 | "<output_sa>" | |
569 | [(set_attr "itanium_class" "<ld_class>") | |
570 | (set_attr "data_speculative" "<attr_yes>") | |
571 | (set_attr "control_speculative" "<attr_yes>")]) | |
572 | ||
388092d5 AB |
573 | (define_insn "mov<mode>_speculative_a" |
574 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
575 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))] | |
576 | "ia64_move_ok (operands[0], operands[1])" | |
577 | "<output_sa>" | |
578 | [(set_attr "itanium_class" "<ld_class>") | |
579 | (set_attr "data_speculative" "<attr_yes>") | |
580 | (set_attr "control_speculative" "<attr_yes>")]) | |
581 | ||
048d0d36 MK |
582 | (define_insn "zero_extend<mode>di2_speculative_advanced" |
583 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
584 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))] | |
585 | "" | |
586 | "<output_sa>" | |
587 | [(set_attr "itanium_class" "<ld_class>") | |
588 | (set_attr "data_speculative" "<attr_yes>") | |
589 | (set_attr "control_speculative" "<attr_yes>")]) | |
590 | ||
388092d5 AB |
591 | (define_insn "zero_extend<mode>di2_speculative_a" |
592 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
593 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))] | |
594 | "" | |
595 | "<output_sa>" | |
596 | [(set_attr "itanium_class" "<ld_class>") | |
597 | (set_attr "data_speculative" "<attr_yes>") | |
598 | (set_attr "control_speculative" "<attr_yes>")]) | |
599 | ||
048d0d36 MK |
600 | (define_insn "mov<mode>_clr" |
601 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
602 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
603 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
604 | (match_dup 0)))] | |
605 | "ia64_move_ok (operands[0], operands[1])" | |
606 | "<output_c_clr>" | |
607 | [(set_attr "itanium_class" "<ld_class>") | |
608 | (set_attr "check_load" "<attr_yes>")]) | |
609 | ||
388092d5 AB |
610 | (define_insn "mov<mode>_nc" |
611 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
612 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
613 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
614 | (match_dup 0)))] | |
615 | "ia64_move_ok (operands[0], operands[1])" | |
616 | "<output_c_nc>" | |
617 | [(set_attr "itanium_class" "<ld_class>") | |
618 | (set_attr "check_load" "<attr_yes>")]) | |
619 | ||
048d0d36 MK |
620 | (define_insn "zero_extend<mode>di2_clr" |
621 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
622 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
623 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
624 | (match_dup 0)))] | |
625 | "" | |
626 | "<output_c_clr>" | |
627 | [(set_attr "itanium_class" "<ld_class>") | |
628 | (set_attr "check_load" "<attr_yes>")]) | |
629 | ||
388092d5 AB |
630 | (define_insn "zero_extend<mode>di2_nc" |
631 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
632 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
633 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
634 | (match_dup 0)))] | |
635 | "" | |
636 | "<output_c_nc>" | |
637 | [(set_attr "itanium_class" "<ld_class>") | |
638 | (set_attr "check_load" "<attr_yes>")]) | |
639 | ||
048d0d36 MK |
640 | (define_insn "advanced_load_check_clr_<mode>" |
641 | [(set (pc) | |
642 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0)) | |
643 | (pc) | |
644 | (label_ref (match_operand 1 "" ""))))] | |
645 | "" | |
646 | "chk.a.clr %0, %l1" | |
647 | [(set_attr "itanium_class" "<chka_class>")]) | |
648 | ||
388092d5 AB |
649 | (define_insn "advanced_load_check_nc_<mode>" |
650 | [(set (pc) | |
651 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0)) | |
652 | (pc) | |
653 | (label_ref (match_operand 1 "" ""))))] | |
654 | "" | |
655 | "chk.a.clr %0, %l1" | |
656 | [(set_attr "itanium_class" "<chka_class>")]) | |
657 | ||
048d0d36 MK |
658 | (define_insn "speculation_check_<mode>" |
659 | [(set (pc) | |
660 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0)) | |
661 | (pc) | |
662 | (label_ref (match_operand 1 "" ""))))] | |
663 | "" | |
664 | "chk.s %0, %l1" | |
665 | [(set_attr "itanium_class" "<chks_class>")]) | |
666 | ||
9b7bf67d | 667 | (define_split |
21515593 RH |
668 | [(set (match_operand 0 "register_operand" "") |
669 | (match_operand 1 "symbolic_operand" ""))] | |
5e6c8b64 | 670 | "reload_completed" |
9b7bf67d | 671 | [(const_int 0)] |
9b7bf67d | 672 | { |
5e6c8b64 RH |
673 | if (ia64_expand_load_address (operands[0], operands[1])) |
674 | DONE; | |
675 | else | |
676 | FAIL; | |
1d5d7a21 | 677 | }) |
9b7bf67d | 678 | |
c65ebc55 | 679 | (define_expand "load_fptr" |
5e6c8b64 RH |
680 | [(set (match_operand:DI 0 "register_operand" "") |
681 | (plus:DI (match_dup 2) (match_operand 1 "function_operand" ""))) | |
682 | (set (match_dup 0) (match_dup 3))] | |
683 | "reload_completed" | |
c65ebc55 | 684 | { |
5e6c8b64 RH |
685 | operands[2] = pic_offset_table_rtx; |
686 | operands[3] = gen_const_mem (DImode, operands[0]); | |
1d5d7a21 | 687 | }) |
c65ebc55 JW |
688 | |
689 | (define_insn "*load_fptr_internal1" | |
690 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 691 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
5e6c8b64 | 692 | "reload_completed" |
c65ebc55 | 693 | "addl %0 = @ltoff(@fptr(%1)), gp" |
52e12ad0 | 694 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
695 | |
696 | (define_insn "load_gprel" | |
697 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 698 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
5e6c8b64 | 699 | "reload_completed" |
c65ebc55 | 700 | "addl %0 = @gprel(%1), gp" |
52e12ad0 | 701 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 702 | |
5e6c8b64 | 703 | (define_insn "*gprel64_offset" |
59da9a7d JW |
704 | [(set (match_operand:DI 0 "register_operand" "=r") |
705 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
5e6c8b64 | 706 | "reload_completed" |
59da9a7d | 707 | "movl %0 = @gprel(%1)" |
52e12ad0 | 708 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
709 | |
710 | (define_expand "load_gprel64" | |
5e6c8b64 RH |
711 | [(set (match_operand:DI 0 "register_operand" "") |
712 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2))) | |
713 | (set (match_dup 0) | |
714 | (plus:DI (match_dup 2) (match_dup 0)))] | |
715 | "reload_completed" | |
ec039e3c | 716 | { |
5e6c8b64 | 717 | operands[2] = pic_offset_table_rtx; |
1d5d7a21 | 718 | }) |
59da9a7d | 719 | |
af1e5518 RH |
720 | ;; This is used as a placeholder for the return address during early |
721 | ;; compilation. We won't know where we've placed this until during | |
722 | ;; reload, at which point it can wind up in b0, a general register, | |
723 | ;; or memory. The only safe destination under these conditions is a | |
724 | ;; general register. | |
725 | ||
726 | (define_insn_and_split "*movdi_ret_addr" | |
727 | [(set (match_operand:DI 0 "register_operand" "=r") | |
728 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
729 | "" | |
730 | "#" | |
731 | "reload_completed" | |
732 | [(const_int 0)] | |
733 | { | |
734 | ia64_split_return_addr_rtx (operands[0]); | |
735 | DONE; | |
736 | } | |
737 | [(set_attr "itanium_class" "ialu")]) | |
738 | ||
ef1ecf87 | 739 | (define_insn "*load_symptr_high" |
c65ebc55 | 740 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
741 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
742 | (match_operand:DI 2 "register_operand" "a")))] | |
5e6c8b64 | 743 | "reload_completed" |
ef1ecf87 RH |
744 | { |
745 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
746 | return "%,addl %0 = @ltoffx(%1), %2"; | |
747 | else | |
748 | return "%,addl %0 = @ltoff(%1), %2"; | |
749 | } | |
52e12ad0 | 750 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 751 | |
ef1ecf87 RH |
752 | (define_insn "*load_symptr_low" |
753 | [(set (match_operand:DI 0 "register_operand" "=r") | |
754 | (lo_sum:DI (match_operand:DI 1 "register_operand" "r") | |
755 | (match_operand 2 "got_symbolic_operand" "s")))] | |
5e6c8b64 | 756 | "reload_completed" |
ef1ecf87 RH |
757 | { |
758 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
759 | return "%,ld8.mov %0 = [%1], %2"; | |
760 | else | |
761 | return "%,ld8 %0 = [%1]"; | |
762 | } | |
763 | [(set_attr "itanium_class" "ld")]) | |
764 | ||
5e6c8b64 | 765 | (define_insn_and_split "load_dtpmod" |
7b6e506e | 766 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 767 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 | 768 | UNSPEC_DTPMOD))] |
7b6e506e | 769 | "" |
5e6c8b64 RH |
770 | "#" |
771 | "reload_completed" | |
772 | [(set (match_dup 0) | |
773 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD) | |
774 | (match_dup 2))) | |
775 | (set (match_dup 0) (match_dup 3))] | |
776 | { | |
777 | operands[2] = pic_offset_table_rtx; | |
778 | operands[3] = gen_const_mem (DImode, operands[0]); | |
779 | }) | |
7b6e506e | 780 | |
5e6c8b64 | 781 | (define_insn "*load_ltoff_dtpmod" |
7b6e506e | 782 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 783 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
784 | UNSPEC_LTOFF_DTPMOD) |
785 | (match_operand:DI 2 "register_operand" "a")))] | |
786 | "reload_completed" | |
787 | "addl %0 = @ltoff(@dtpmod(%1)), %2" | |
7b6e506e RH |
788 | [(set_attr "itanium_class" "ialu")]) |
789 | ||
790 | (define_expand "load_dtprel" | |
791 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 792 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
793 | UNSPEC_DTPREL))] |
794 | "" | |
795 | "") | |
796 | ||
797 | (define_insn "*load_dtprel64" | |
798 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 799 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
800 | UNSPEC_DTPREL))] |
801 | "TARGET_TLS64" | |
802 | "movl %0 = @dtprel(%1)" | |
803 | [(set_attr "itanium_class" "long_i")]) | |
804 | ||
805 | (define_insn "*load_dtprel22" | |
806 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 807 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
808 | UNSPEC_DTPREL))] |
809 | "" | |
810 | "addl %0 = @dtprel(%1), r0" | |
811 | [(set_attr "itanium_class" "ialu")]) | |
812 | ||
5e6c8b64 RH |
813 | (define_insn_and_split "*load_dtprel_gd" |
814 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 815 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
816 | UNSPEC_DTPREL))] |
817 | "" | |
818 | "#" | |
819 | "reload_completed" | |
820 | [(set (match_dup 0) | |
821 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL) | |
822 | (match_dup 2))) | |
823 | (set (match_dup 0) (match_dup 3))] | |
824 | { | |
825 | operands[2] = pic_offset_table_rtx; | |
826 | operands[3] = gen_const_mem (DImode, operands[0]); | |
827 | }) | |
828 | ||
829 | (define_insn "*load_ltoff_dtprel" | |
830 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 831 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
832 | UNSPEC_LTOFF_DTPREL) |
833 | (match_operand:DI 2 "register_operand" "a")))] | |
834 | "" | |
835 | "addl %0 = @ltoff(@dtprel(%1)), %2" | |
836 | [(set_attr "itanium_class" "ialu")]) | |
837 | ||
7b6e506e RH |
838 | (define_expand "add_dtprel" |
839 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 840 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
841 | UNSPEC_DTPREL) |
842 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
843 | "!TARGET_TLS64" |
844 | "") | |
845 | ||
846 | (define_insn "*add_dtprel14" | |
847 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 848 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
849 | UNSPEC_DTPREL) |
850 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 851 | "TARGET_TLS14" |
5e6c8b64 | 852 | "adds %0 = @dtprel(%1), %2" |
7b6e506e RH |
853 | [(set_attr "itanium_class" "ialu")]) |
854 | ||
855 | (define_insn "*add_dtprel22" | |
856 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 857 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
858 | UNSPEC_DTPREL) |
859 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 860 | "TARGET_TLS22" |
5e6c8b64 | 861 | "addl %0 = @dtprel(%1), %2" |
7b6e506e RH |
862 | [(set_attr "itanium_class" "ialu")]) |
863 | ||
864 | (define_expand "load_tprel" | |
865 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 866 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
867 | UNSPEC_TPREL))] |
868 | "" | |
869 | "") | |
870 | ||
871 | (define_insn "*load_tprel64" | |
872 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 873 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
874 | UNSPEC_TPREL))] |
875 | "TARGET_TLS64" | |
876 | "movl %0 = @tprel(%1)" | |
877 | [(set_attr "itanium_class" "long_i")]) | |
878 | ||
879 | (define_insn "*load_tprel22" | |
880 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 881 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
882 | UNSPEC_TPREL))] |
883 | "" | |
884 | "addl %0 = @tprel(%1), r0" | |
885 | [(set_attr "itanium_class" "ialu")]) | |
886 | ||
5e6c8b64 RH |
887 | (define_insn_and_split "*load_tprel_ie" |
888 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 889 | (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
890 | UNSPEC_TPREL))] |
891 | "" | |
892 | "#" | |
893 | "reload_completed" | |
894 | [(set (match_dup 0) | |
895 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL) | |
896 | (match_dup 2))) | |
897 | (set (match_dup 0) (match_dup 3))] | |
898 | { | |
899 | operands[2] = pic_offset_table_rtx; | |
900 | operands[3] = gen_const_mem (DImode, operands[0]); | |
901 | }) | |
902 | ||
903 | (define_insn "*load_ltoff_tprel" | |
904 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 905 | (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
906 | UNSPEC_LTOFF_TPREL) |
907 | (match_operand:DI 2 "register_operand" "a")))] | |
908 | "" | |
909 | "addl %0 = @ltoff(@tprel(%1)), %2" | |
910 | [(set_attr "itanium_class" "ialu")]) | |
911 | ||
7b6e506e RH |
912 | (define_expand "add_tprel" |
913 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 914 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
915 | UNSPEC_TPREL) |
916 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
917 | "!TARGET_TLS64" |
918 | "") | |
919 | ||
920 | (define_insn "*add_tprel14" | |
921 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 922 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
923 | UNSPEC_TPREL) |
924 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 925 | "TARGET_TLS14" |
5e6c8b64 | 926 | "adds %0 = @tprel(%1), %2" |
7b6e506e RH |
927 | [(set_attr "itanium_class" "ialu")]) |
928 | ||
929 | (define_insn "*add_tprel22" | |
930 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 931 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
932 | UNSPEC_TPREL) |
933 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 934 | "TARGET_TLS22" |
5e6c8b64 | 935 | "addl %0 = @tprel(%1), %2" |
7b6e506e RH |
936 | [(set_attr "itanium_class" "ialu")]) |
937 | ||
3f622353 | 938 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
939 | ;; around to play with the second word. However, in order to avoid a |
940 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
941 | ;; in ia64_split_tmode_move. | |
3f622353 | 942 | (define_expand "movti" |
2ffe0e02 ZW |
943 | [(set (match_operand:TI 0 "general_operand" "") |
944 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 945 | "" |
3f622353 | 946 | { |
7b6e506e RH |
947 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
948 | if (!op1) | |
949 | DONE; | |
950 | operands[1] = op1; | |
1d5d7a21 | 951 | }) |
3f622353 | 952 | |
388092d5 | 953 | (define_insn_and_split "movti_internal" |
b6fb7d46 JW |
954 | [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q") |
955 | (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))] | |
3f622353 | 956 | "ia64_move_ok (operands[0], operands[1])" |
a71aef0b JB |
957 | "@ |
958 | # | |
959 | # | |
960 | ldfp8 %X0 = %1%P1 | |
961 | # | |
962 | #" | |
963 | "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])" | |
3f622353 | 964 | [(const_int 0)] |
3f622353 | 965 | { |
f57fc998 | 966 | ia64_split_tmode_move (operands); |
3f622353 | 967 | DONE; |
1d5d7a21 | 968 | } |
388092d5 AB |
969 | [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown") |
970 | (set_attr "speculable1" "yes") | |
971 | (set_attr "speculable2" "no, no, yes, no, no")]) | |
e314e331 | 972 | |
c65ebc55 JW |
973 | ;; Floating Point Moves |
974 | ;; | |
975 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 976 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
977 | |
978 | (define_expand "movsf" | |
979 | [(set (match_operand:SF 0 "general_operand" "") | |
980 | (match_operand:SF 1 "general_operand" ""))] | |
981 | "" | |
c65ebc55 | 982 | { |
7b6e506e RH |
983 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
984 | if (!op1) | |
985 | DONE; | |
986 | operands[1] = op1; | |
1d5d7a21 | 987 | }) |
c65ebc55 | 988 | |
388092d5 | 989 | (define_insn "movsf_internal" |
735b94a7 SE |
990 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r") |
991 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))] | |
aebf2462 | 992 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 993 | "@ |
1d5d7a21 RH |
994 | mov %0 = %F1 |
995 | ldfs %0 = %1%P1 | |
996 | stfs %0 = %F1%P0 | |
997 | getf.s %0 = %F1 | |
998 | setf.s %0 = %1 | |
999 | mov %0 = %1 | |
1000 | ld4%O1 %0 = %1%P1 | |
735b94a7 SE |
1001 | st4%Q0 %0 = %1%P0 |
1002 | movl %0 = %G1" | |
1003 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i") | |
388092d5 | 1004 | (set_attr "speculable1" "yes") |
735b94a7 | 1005 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")]) |
c65ebc55 JW |
1006 | |
1007 | (define_expand "movdf" | |
1008 | [(set (match_operand:DF 0 "general_operand" "") | |
1009 | (match_operand:DF 1 "general_operand" ""))] | |
1010 | "" | |
c65ebc55 | 1011 | { |
7b6e506e RH |
1012 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
1013 | if (!op1) | |
1014 | DONE; | |
1015 | operands[1] = op1; | |
1d5d7a21 | 1016 | }) |
c65ebc55 | 1017 | |
388092d5 | 1018 | (define_insn "movdf_internal" |
735b94a7 SE |
1019 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r") |
1020 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))] | |
aebf2462 | 1021 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 1022 | "@ |
1d5d7a21 RH |
1023 | mov %0 = %F1 |
1024 | ldfd %0 = %1%P1 | |
1025 | stfd %0 = %F1%P0 | |
1026 | getf.d %0 = %F1 | |
1027 | setf.d %0 = %1 | |
1028 | mov %0 = %1 | |
1029 | ld8%O1 %0 = %1%P1 | |
735b94a7 SE |
1030 | st8%Q0 %0 = %1%P0 |
1031 | movl %0 = %G1" | |
1032 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i") | |
388092d5 | 1033 | (set_attr "speculable1" "yes") |
735b94a7 | 1034 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")]) |
c65ebc55 | 1035 | |
3f622353 RH |
1036 | ;; With no offsettable memory references, we've got to have a scratch |
1037 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
1038 | (define_expand "movxf" |
1039 | [(set (match_operand:XF 0 "general_operand" "") | |
1040 | (match_operand:XF 1 "general_operand" ""))] | |
1041 | "" | |
e5bde68a | 1042 | { |
4de67c26 JM |
1043 | if (ia64_expand_movxf_movrf (XFmode, operands)) |
1044 | DONE; | |
1d5d7a21 | 1045 | }) |
e5bde68a | 1046 | |
3b572406 | 1047 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 1048 | |
388092d5 | 1049 | (define_insn "movxf_internal" |
78d8e0f9 ZW |
1050 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
1051 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 1052 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 1053 | "@ |
1d5d7a21 RH |
1054 | mov %0 = %F1 |
1055 | ldfe %0 = %1%P1 | |
1056 | stfe %0 = %F1%P0" | |
388092d5 AB |
1057 | [(set_attr "itanium_class" "fmisc,fld,stf") |
1058 | (set_attr "speculable1" "yes") | |
1059 | (set_attr "speculable2" "no, yes,no")]) | |
f57fc998 | 1060 | |
4de67c26 JM |
1061 | ;; Same as for movxf, but for RFmode. |
1062 | (define_expand "movrf" | |
1063 | [(set (match_operand:RF 0 "general_operand" "") | |
1064 | (match_operand:RF 1 "general_operand" ""))] | |
1065 | "" | |
1066 | { | |
1067 | if (ia64_expand_movxf_movrf (RFmode, operands)) | |
1068 | DONE; | |
1069 | }) | |
1070 | ||
1071 | (define_insn "*movrf_internal" | |
1072 | [(set (match_operand:RF 0 "destination_operand" "=f,f, m") | |
1073 | (match_operand:RF 1 "general_operand" "fG,m,fG"))] | |
1074 | "ia64_move_ok (operands[0], operands[1])" | |
1075 | "@ | |
1076 | mov %0 = %F1 | |
1077 | ldf.fill %0 = %1%P1 | |
1078 | stf.spill %0 = %F1%P0" | |
1079 | [(set_attr "itanium_class" "fmisc,fld,stf")]) | |
1080 | ||
f57fc998 | 1081 | ;; Better code generation via insns that deal with TFmode register pairs |
2ffe0e02 | 1082 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 1083 | (define_expand "movtf" |
2ffe0e02 ZW |
1084 | [(set (match_operand:TF 0 "general_operand" "") |
1085 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
1086 | "" |
1087 | { | |
1088 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
1089 | if (!op1) | |
1090 | DONE; | |
1091 | operands[1] = op1; | |
1092 | }) | |
1093 | ||
1094 | (define_insn_and_split "*movtf_internal" | |
e77ee95d | 1095 | [(set (match_operand:TF 0 "destination_operand" "=r,r,m") |
2ffe0e02 | 1096 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
1097 | "ia64_move_ok (operands[0], operands[1])" |
1098 | "#" | |
1099 | "reload_completed" | |
1100 | [(const_int 0)] | |
1101 | { | |
1102 | ia64_split_tmode_move (operands); | |
1103 | DONE; | |
1104 | } | |
1105 | [(set_attr "itanium_class" "unknown") | |
1106 | (set_attr "predicable" "no")]) | |
1107 | ||
c65ebc55 JW |
1108 | \f |
1109 | ;; :::::::::::::::::::: | |
1110 | ;; :: | |
1111 | ;; :: Conversions | |
1112 | ;; :: | |
1113 | ;; :::::::::::::::::::: | |
1114 | ||
1115 | ;; Signed conversions from a smaller integer to a larger integer | |
1116 | ||
1117 | (define_insn "extendqidi2" | |
0551c32d RH |
1118 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1119 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1120 | "" |
1121 | "sxt1 %0 = %1" | |
52e12ad0 | 1122 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1123 | |
1124 | (define_insn "extendhidi2" | |
0551c32d RH |
1125 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1126 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1127 | "" |
1128 | "sxt2 %0 = %1" | |
52e12ad0 | 1129 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1130 | |
1131 | (define_insn "extendsidi2" | |
655f2eb9 RH |
1132 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
1133 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
1134 | "" |
1135 | "@ | |
1136 | sxt4 %0 = %1 | |
aebf2462 | 1137 | fsxt.r %0 = %1, %1" |
52e12ad0 | 1138 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
1139 | |
1140 | ;; Unsigned conversions from a smaller integer to a larger integer | |
1141 | ||
1142 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
1143 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1144 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1145 | "" |
1146 | "@ | |
1147 | zxt1 %0 = %1 | |
1148 | ld1%O1 %0 = %1%P1" | |
388092d5 AB |
1149 | [(set_attr "itanium_class" "xtd,ld") |
1150 | (set_attr "speculable1" "yes") | |
1151 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1152 | |
1153 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
1154 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1155 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1156 | "" |
1157 | "@ | |
1158 | zxt2 %0 = %1 | |
1159 | ld2%O1 %0 = %1%P1" | |
388092d5 AB |
1160 | [(set_attr "itanium_class" "xtd,ld") |
1161 | (set_attr "speculable1" "yes") | |
1162 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1163 | |
1164 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 1165 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 1166 | (zero_extend:DI |
655f2eb9 | 1167 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
1168 | "" |
1169 | "@ | |
d3f6e07b | 1170 | addp4 %0 = %1, r0 |
c65ebc55 | 1171 | ld4%O1 %0 = %1%P1 |
aebf2462 | 1172 | fmix.r %0 = f0, %1" |
388092d5 AB |
1173 | [(set_attr "itanium_class" "ialu,ld,fmisc") |
1174 | (set_attr "speculable1" "yes") | |
1175 | (set_attr "speculable2" "no, yes,no")]) | |
c65ebc55 JW |
1176 | |
1177 | ;; Convert between floating point types of different sizes. | |
1178 | ||
640cea5f JW |
1179 | ;; At first glance, it would appear that emitting fnorm for an extending |
1180 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
1181 | ;; correctly only if the input is properly rounded for its type. In | |
1182 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
1183 | ;; denorm single. Since we don't know what the next instruction will be, we | |
1184 | ;; have to emit an fnorm. | |
1185 | ||
e8e20f18 RH |
1186 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
1187 | ;; when we can. Should probably use a scheme like has been proposed | |
1188 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
1189 | ;; would let combine merge the thing into adjacent insns. See also how the |
1190 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
1191 | ;; se_register_operand. | |
c65ebc55 | 1192 | |
640cea5f JW |
1193 | (define_insn "extendsfdf2" |
1194 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
6adb807e | 1195 | (float_extend:DF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1196 | "" |
6adb807e | 1197 | "fnorm.d %0 = %F1" |
640cea5f | 1198 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1199 | |
02befdf4 ZW |
1200 | (define_insn "extendsfxf2" |
1201 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1202 | (float_extend:XF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1203 | "" |
6adb807e | 1204 | "fnorm %0 = %F1" |
640cea5f | 1205 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 1206 | |
02befdf4 ZW |
1207 | (define_insn "extenddfxf2" |
1208 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1209 | (float_extend:XF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1210 | "" |
6adb807e | 1211 | "fnorm %0 = %F1" |
640cea5f | 1212 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 1213 | |
c65ebc55 | 1214 | (define_insn "truncdfsf2" |
0551c32d | 1215 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1216 | (float_truncate:SF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1217 | "" |
6adb807e | 1218 | "fnorm.s %0 = %F1" |
52e12ad0 | 1219 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1220 | |
02befdf4 | 1221 | (define_insn "truncxfsf2" |
0551c32d | 1222 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1223 | (float_truncate:SF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1224 | "" |
6adb807e | 1225 | "fnorm.s %0 = %F1" |
52e12ad0 | 1226 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1227 | |
02befdf4 | 1228 | (define_insn "truncxfdf2" |
0551c32d | 1229 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 1230 | (float_truncate:DF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1231 | "" |
6adb807e | 1232 | "fnorm.d %0 = %F1" |
52e12ad0 | 1233 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
1234 | |
1235 | ;; Convert between signed integer types and floating point. | |
1236 | ||
49df2fb8 SE |
1237 | (define_insn "floatdirf2" |
1238 | [(set (match_operand:RF 0 "fr_register_operand" "=f") | |
1239 | (float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] | |
1240 | "" | |
1241 | "fcvt.xf %0 = %F1" | |
1242 | [(set_attr "itanium_class" "fcvtfx")]) | |
1243 | ||
02befdf4 ZW |
1244 | (define_insn "floatdixf2" |
1245 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1246 | (float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1247 | "" |
6adb807e | 1248 | "fcvt.xf %0 = %F1" |
52e12ad0 | 1249 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1250 | |
1251 | (define_insn "fix_truncsfdi2" | |
0551c32d | 1252 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1253 | (fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1254 | "" |
6adb807e | 1255 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1256 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1257 | |
1258 | (define_insn "fix_truncdfdi2" | |
0551c32d | 1259 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1260 | (fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1261 | "" |
6adb807e | 1262 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1263 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1264 | |
02befdf4 | 1265 | (define_insn "fix_truncxfdi2" |
0551c32d | 1266 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1267 | (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1268 | "" |
6adb807e | 1269 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1270 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1271 | |
49df2fb8 | 1272 | (define_insn "fix_truncrfdi2" |
655f2eb9 | 1273 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
49df2fb8 | 1274 | (fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1275 | "" |
49df2fb8 | 1276 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1277 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1278 | |
c65ebc55 JW |
1279 | ;; Convert between unsigned integer types and floating point. |
1280 | ||
1281 | (define_insn "floatunsdisf2" | |
0551c32d | 1282 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1283 | (unsigned_float:SF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1284 | "" |
6adb807e | 1285 | "fcvt.xuf.s %0 = %F1" |
52e12ad0 | 1286 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1287 | |
1288 | (define_insn "floatunsdidf2" | |
0551c32d | 1289 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 1290 | (unsigned_float:DF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1291 | "" |
6adb807e | 1292 | "fcvt.xuf.d %0 = %F1" |
52e12ad0 | 1293 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1294 | |
02befdf4 ZW |
1295 | (define_insn "floatunsdixf2" |
1296 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1297 | (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1298 | "" |
6adb807e | 1299 | "fcvt.xuf %0 = %F1" |
52e12ad0 | 1300 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1301 | |
49df2fb8 SE |
1302 | (define_insn "floatunsdirf2" |
1303 | [(set (match_operand:RF 0 "fr_register_operand" "=f") | |
1304 | (unsigned_float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] | |
1305 | "" | |
1306 | "fcvt.xuf %0 = %F1" | |
1307 | [(set_attr "itanium_class" "fcvtfx")]) | |
1308 | ||
c65ebc55 | 1309 | (define_insn "fixuns_truncsfdi2" |
0551c32d | 1310 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1311 | (unsigned_fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1312 | "" |
6adb807e | 1313 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1314 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1315 | |
1316 | (define_insn "fixuns_truncdfdi2" | |
0551c32d | 1317 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1318 | (unsigned_fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1319 | "" |
6adb807e | 1320 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1321 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1322 | |
02befdf4 | 1323 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 1324 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1325 | (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1326 | "" |
6adb807e | 1327 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1328 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1329 | |
49df2fb8 | 1330 | (define_insn "fixuns_truncrfdi2" |
655f2eb9 | 1331 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
49df2fb8 | 1332 | (unsigned_fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1333 | "" |
49df2fb8 | 1334 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1335 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1336 | \f |
1337 | ;; :::::::::::::::::::: | |
1338 | ;; :: | |
1339 | ;; :: Bit field extraction | |
1340 | ;; :: | |
1341 | ;; :::::::::::::::::::: | |
1342 | ||
c65ebc55 | 1343 | (define_insn "extv" |
0551c32d RH |
1344 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1345 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1346 | (match_operand:DI 2 "extr_len_operand" "n") |
1347 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1348 | "" |
1349 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1350 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1351 | |
1352 | (define_insn "extzv" | |
0551c32d RH |
1353 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1354 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1355 | (match_operand:DI 2 "extr_len_operand" "n") |
1356 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1357 | "" |
1358 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1359 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1360 | |
1361 | ;; Insert a bit field. | |
1362 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1363 | ;; Source1 can be 0 or -1. | |
1364 | ;; Source2 can be 0. | |
1365 | ||
1366 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1367 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1368 | ;; where source2 != dest. | |
1369 | ||
1370 | (define_expand "insv" | |
0551c32d | 1371 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1372 | (match_operand:DI 1 "const_int_operand" "") |
1373 | (match_operand:DI 2 "const_int_operand" "")) | |
1374 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1375 | "" | |
c65ebc55 JW |
1376 | { |
1377 | int width = INTVAL (operands[1]); | |
1378 | int shift = INTVAL (operands[2]); | |
1379 | ||
1380 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1381 | pseudo. */ | |
1382 | if (! register_operand (operands[3], DImode) | |
1383 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1384 | operands[3] = force_reg (DImode, operands[3]); | |
1385 | ||
1386 | /* If this is a single dep instruction, we have nothing to do. */ | |
1387 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1388 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1389 | { | |
1390 | /* Check for cases that can be implemented with a mix instruction. */ | |
1391 | if (width == 32 && shift == 0) | |
1392 | { | |
1393 | /* Directly generating the mix4left instruction confuses | |
1394 | optimize_bit_field in function.c. Since this is performing | |
1395 | a useful optimization, we defer generation of the complicated | |
1396 | mix4left RTL to the first splitting phase. */ | |
1397 | rtx tmp = gen_reg_rtx (DImode); | |
1398 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1399 | DONE; | |
1400 | } | |
1401 | else if (width == 32 && shift == 32) | |
1402 | { | |
1403 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1404 | DONE; | |
1405 | } | |
1406 | ||
d2ba6dcf JW |
1407 | /* We could handle remaining cases by emitting multiple dep |
1408 | instructions. | |
1409 | ||
1410 | If we need more than two dep instructions then we lose. A 6 | |
1411 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1412 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1413 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1414 | only one function unit that can execute dep and shr immed. | |
1415 | ||
1416 | If we only need two dep instruction, then we still lose. | |
1417 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1418 | the unnecessary mov, this is still undesirable because it will be | |
1419 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1420 | function unit. */ | |
1421 | ||
c65ebc55 JW |
1422 | FAIL; |
1423 | ||
1424 | #if 0 | |
1425 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1426 | for now. */ | |
1427 | while (width > 16) | |
1428 | { | |
1429 | rtx tmp; | |
1430 | ||
1431 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1432 | operands[3])); | |
1433 | shift += 16; | |
1434 | width -= 16; | |
1435 | tmp = gen_reg_rtx (DImode); | |
1436 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1437 | operands[3] = tmp; | |
1438 | } | |
1439 | operands[1] = GEN_INT (width); | |
1440 | operands[2] = GEN_INT (shift); | |
1441 | #endif | |
1442 | } | |
1d5d7a21 | 1443 | }) |
c65ebc55 JW |
1444 | |
1445 | (define_insn "*insv_internal" | |
0551c32d | 1446 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1447 | (match_operand:DI 1 "const_int_operand" "n") |
1448 | (match_operand:DI 2 "const_int_operand" "n")) | |
1449 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1450 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1451 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1452 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1453 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1454 | |
43a88a8c | 1455 | ;; Combine doesn't like to create bit-field insertions into zero. |
d3f6e07b JB |
1456 | (define_insn "*shladdp4_internal" |
1457 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
1458 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1459 | (match_operand:DI 2 "shladd_log2_operand" "n")) | |
1460 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1461 | "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" | |
1462 | "shladdp4 %0 = %1, %2, r0" | |
1463 | [(set_attr "itanium_class" "ialu")]) | |
1464 | ||
041f25e6 | 1465 | (define_insn "*depz_internal" |
0551c32d RH |
1466 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1467 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
13f70342 | 1468 | (match_operand:DI 2 "const_int_operand" "M")) |
041f25e6 | 1469 | (match_operand:DI 3 "const_int_operand" "n")))] |
13f70342 | 1470 | "satisfies_constraint_M (operands[2]) |
041f25e6 | 1471 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" |
041f25e6 RH |
1472 | { |
1473 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1474 | return "%,dep.z %0 = %1, %2, %3"; |
1475 | } | |
52e12ad0 | 1476 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1477 | |
c65ebc55 | 1478 | (define_insn "shift_mix4left" |
0551c32d | 1479 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1480 | (const_int 32) (const_int 0)) |
0551c32d RH |
1481 | (match_operand:DI 1 "gr_register_operand" "r")) |
1482 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1483 | "" |
1484 | "#" | |
52e12ad0 | 1485 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1486 | |
c65ebc55 JW |
1487 | (define_split |
1488 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1489 | (const_int 32) (const_int 0)) | |
1490 | (match_operand:DI 1 "register_operand" "")) | |
1491 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1492 | "" |
c65ebc55 JW |
1493 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1494 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1495 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1496 | "operands[3] = operands[2];") | |
1497 | ||
1498 | (define_insn "*mix4left" | |
0551c32d | 1499 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1500 | (const_int 32) (const_int 0)) |
0551c32d | 1501 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1502 | (const_int 32)))] |
1503 | "" | |
1504 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1505 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1506 | |
1507 | (define_insn "mix4right" | |
0551c32d | 1508 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1509 | (const_int 32) (const_int 32)) |
0551c32d | 1510 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1511 | "" |
1512 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1513 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1514 | |
1515 | ;; This is used by the rotrsi3 pattern. | |
1516 | ||
1517 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1518 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1519 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1520 | (ashift:DI (zero_extend:DI | |
1521 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1522 | (const_int 32))))] |
1523 | "" | |
fa9a44e8 | 1524 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1525 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1526 | |
1527 | \f | |
1528 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1529 | ;; :: |
27a9b99d | 1530 | ;; :: 1-bit Integer arithmetic |
f2f90c63 RH |
1531 | ;; :: |
1532 | ;; :::::::::::::::::::: | |
1533 | ||
1534 | (define_insn_and_split "andbi3" | |
1535 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1536 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1537 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1538 | "" | |
1539 | "@ | |
1540 | # | |
1541 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1542 | and %0 = %2, %1" | |
1543 | "reload_completed | |
1544 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1545 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1546 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1547 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1548 | (match_dup 0))))] | |
1549 | "" | |
52e12ad0 | 1550 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1551 | |
1552 | (define_insn_and_split "*andcmbi3" | |
1553 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1554 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1555 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1556 | "" | |
1557 | "@ | |
1558 | # | |
967603ef | 1559 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1560 | andcm %0 = %2, %1" |
1561 | "reload_completed | |
1562 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1563 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1564 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1565 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1566 | (match_dup 0))))] | |
1567 | "" | |
52e12ad0 | 1568 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1569 | |
1570 | (define_insn_and_split "iorbi3" | |
1571 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1572 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1573 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1574 | "" | |
1575 | "@ | |
1576 | # | |
1577 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1578 | or %0 = %2, %1" | |
1579 | "reload_completed | |
1580 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1581 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1582 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1583 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1584 | (match_dup 0))))] | |
1585 | "" | |
52e12ad0 | 1586 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1587 | |
1588 | (define_insn_and_split "*iorcmbi3" | |
1589 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1590 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1591 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1592 | "" | |
1593 | "@ | |
1594 | # | |
967603ef | 1595 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1596 | "reload_completed |
1597 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1598 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1599 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1600 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1601 | (match_dup 0))))] | |
1602 | "" | |
52e12ad0 | 1603 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1604 | |
1605 | (define_insn "one_cmplbi2" | |
1606 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1607 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1608 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1609 | "" | |
1610 | "@ | |
1611 | tbit.z %0, %I0 = %1, 0 | |
1612 | xor %0 = 1, %1 | |
1613 | # | |
1614 | #" | |
52e12ad0 | 1615 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1616 | |
1617 | (define_split | |
1618 | [(set (match_operand:BI 0 "register_operand" "") | |
1619 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1620 | (clobber (match_scratch:BI 2 ""))] | |
1621 | "reload_completed | |
1622 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1623 | && rtx_equal_p (operands[0], operands[1])" |
1624 | [(set (match_dup 4) (match_dup 3)) | |
1625 | (set (match_dup 0) (const_int 1)) | |
1626 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1627 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1628 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1629 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1630 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1631 | ||
1632 | (define_split | |
1633 | [(set (match_operand:BI 0 "register_operand" "") | |
1634 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1635 | (clobber (match_scratch:BI 2 ""))] | |
1636 | "reload_completed | |
1637 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1638 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1639 | && ! rtx_equal_p (operands[0], operands[1])" | |
1640 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1641 | (set (match_dup 0) (const_int 0))) | |
1642 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1643 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1644 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1645 | "") |
1646 | ||
1647 | (define_insn "*cmpsi_and_0" | |
1648 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1649 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1650 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1651 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1652 | (match_operand:BI 1 "register_operand" "0")))] | |
1653 | "" | |
1654 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1655 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1656 | |
1657 | (define_insn "*cmpsi_and_1" | |
1658 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1659 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1660 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1661 | (const_int 0)]) | |
1662 | (match_operand:BI 1 "register_operand" "0")))] | |
1663 | "" | |
1664 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1665 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1666 | |
1667 | (define_insn "*cmpsi_andnot_0" | |
1668 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1669 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1670 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1671 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1672 | (match_operand:BI 1 "register_operand" "0")))] | |
1673 | "" | |
1674 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1675 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1676 | |
1677 | (define_insn "*cmpsi_andnot_1" | |
1678 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1679 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1680 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1681 | (const_int 0)])) | |
1682 | (match_operand:BI 1 "register_operand" "0")))] | |
1683 | "" | |
1684 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1685 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1686 | |
1687 | (define_insn "*cmpdi_and_0" | |
1688 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1689 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1690 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1691 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1692 | (match_operand:BI 1 "register_operand" "0")))] | |
1693 | "" | |
1694 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1695 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1696 | |
1697 | (define_insn "*cmpdi_and_1" | |
1698 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1699 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1700 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1701 | (const_int 0)]) | |
1702 | (match_operand:BI 1 "register_operand" "0")))] | |
1703 | "" | |
1704 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1705 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1706 | |
1707 | (define_insn "*cmpdi_andnot_0" | |
1708 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1709 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1710 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1711 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1712 | (match_operand:BI 1 "register_operand" "0")))] | |
1713 | "" | |
1714 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1715 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1716 | |
1717 | (define_insn "*cmpdi_andnot_1" | |
1718 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1719 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1720 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1721 | (const_int 0)])) | |
1722 | (match_operand:BI 1 "register_operand" "0")))] | |
1723 | "" | |
1724 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1725 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1726 | |
1727 | (define_insn "*tbit_and_0" | |
1728 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1729 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1730 | (const_int 1)) | |
1731 | (const_int 0)) | |
c77e04ae | 1732 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1733 | "" |
1734 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1735 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1736 | |
1737 | (define_insn "*tbit_and_1" | |
1738 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1739 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1740 | (const_int 1)) | |
1741 | (const_int 0)) | |
c77e04ae | 1742 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1743 | "" |
1744 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1745 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1746 | |
1747 | (define_insn "*tbit_and_2" | |
1748 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1749 | (and:BI (ne:BI (zero_extract:DI | |
1750 | (match_operand:DI 1 "gr_register_operand" "r") | |
1751 | (const_int 1) | |
5d48891e | 1752 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1753 | (const_int 0)) |
1754 | (match_operand:BI 3 "register_operand" "0")))] | |
1755 | "" | |
1756 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1757 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1758 | |
1759 | (define_insn "*tbit_and_3" | |
1760 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1761 | (and:BI (eq:BI (zero_extract:DI | |
1762 | (match_operand:DI 1 "gr_register_operand" "r") | |
1763 | (const_int 1) | |
5d48891e | 1764 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1765 | (const_int 0)) |
1766 | (match_operand:BI 3 "register_operand" "0")))] | |
1767 | "" | |
1768 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1769 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1770 | |
1771 | (define_insn "*cmpsi_or_0" | |
1772 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1773 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1774 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1775 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1776 | (match_operand:BI 1 "register_operand" "0")))] | |
1777 | "" | |
1778 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1779 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1780 | |
1781 | (define_insn "*cmpsi_or_1" | |
1782 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1783 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1784 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1785 | (const_int 0)]) | |
1786 | (match_operand:BI 1 "register_operand" "0")))] | |
1787 | "" | |
1788 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1789 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1790 | |
1791 | (define_insn "*cmpsi_orcm_0" | |
1792 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1793 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1794 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1795 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1796 | (match_operand:BI 1 "register_operand" "0")))] | |
1797 | "" | |
1798 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1799 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1800 | |
1801 | (define_insn "*cmpsi_orcm_1" | |
1802 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1803 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1804 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1805 | (const_int 0)])) | |
1806 | (match_operand:BI 1 "register_operand" "0")))] | |
1807 | "" | |
1808 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1809 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1810 | |
1811 | (define_insn "*cmpdi_or_0" | |
1812 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1813 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1814 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1815 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1816 | (match_operand:BI 1 "register_operand" "0")))] | |
1817 | "" | |
1818 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1819 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1820 | |
1821 | (define_insn "*cmpdi_or_1" | |
1822 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1823 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1824 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1825 | (const_int 0)]) | |
1826 | (match_operand:BI 1 "register_operand" "0")))] | |
1827 | "" | |
1828 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1829 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1830 | |
1831 | (define_insn "*cmpdi_orcm_0" | |
1832 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1833 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1834 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1835 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1836 | (match_operand:BI 1 "register_operand" "0")))] | |
1837 | "" | |
1838 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1839 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1840 | |
1841 | (define_insn "*cmpdi_orcm_1" | |
1842 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1843 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1844 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1845 | (const_int 0)])) | |
1846 | (match_operand:BI 1 "register_operand" "0")))] | |
1847 | "" | |
1848 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1849 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1850 | |
1851 | (define_insn "*tbit_or_0" | |
1852 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1853 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1854 | (const_int 1)) | |
1855 | (const_int 0)) | |
c77e04ae | 1856 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1857 | "" |
1858 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1859 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1860 | |
1861 | (define_insn "*tbit_or_1" | |
1862 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1863 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1864 | (const_int 1)) | |
1865 | (const_int 0)) | |
c77e04ae | 1866 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1867 | "" |
1868 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1869 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1870 | |
1871 | (define_insn "*tbit_or_2" | |
1872 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1873 | (ior:BI (ne:BI (zero_extract:DI | |
1874 | (match_operand:DI 1 "gr_register_operand" "r") | |
1875 | (const_int 1) | |
5d48891e | 1876 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1877 | (const_int 0)) |
1878 | (match_operand:BI 3 "register_operand" "0")))] | |
1879 | "" | |
1880 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1881 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1882 | |
1883 | (define_insn "*tbit_or_3" | |
1884 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1885 | (ior:BI (eq:BI (zero_extract:DI | |
1886 | (match_operand:DI 1 "gr_register_operand" "r") | |
1887 | (const_int 1) | |
5d48891e | 1888 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1889 | (const_int 0)) |
1890 | (match_operand:BI 3 "register_operand" "0")))] | |
1891 | "" | |
1892 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1893 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1894 | |
1895 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1896 | ||
1897 | (define_split | |
1898 | [(set (match_operand:BI 0 "register_operand" "") | |
1899 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1900 | (const_int 0)) | |
1901 | (match_operand:DI 3 "register_operand" "")) | |
1902 | (const_int 0)))] | |
1903 | "" | |
1904 | [(set (match_dup 0) | |
1905 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1906 | (match_dup 2)))] | |
1907 | "") | |
1908 | ||
1909 | (define_split | |
1910 | [(set (match_operand:BI 0 "register_operand" "") | |
1911 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1912 | (const_int 0)) | |
1913 | (match_operand:DI 3 "register_operand" "")) | |
1914 | (const_int 0)))] | |
1915 | "" | |
1916 | [(set (match_dup 0) | |
1917 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1918 | (match_dup 2))) | |
1919 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1920 | (clobber (scratch))])] | |
1921 | "") | |
1922 | ||
1923 | (define_split | |
1924 | [(set (match_operand:BI 0 "register_operand" "") | |
1925 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1926 | (const_int 0)) | |
1927 | (match_operand:DI 3 "register_operand" "")) | |
1928 | (const_int 0)))] | |
1929 | "" | |
1930 | [(set (match_dup 0) | |
1931 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1932 | (match_dup 2)))] | |
1933 | "") | |
1934 | ||
1935 | (define_split | |
1936 | [(set (match_operand:BI 0 "register_operand" "") | |
1937 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1938 | (const_int 0)) | |
1939 | (match_operand:DI 3 "register_operand" "")) | |
1940 | (const_int 0)))] | |
1941 | "" | |
1942 | [(set (match_dup 0) | |
1943 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1944 | (match_dup 2))) | |
1945 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1946 | (clobber (scratch))])] | |
1947 | "") | |
1948 | ||
1949 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1950 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1951 | ;; nothing bad happens to the comparisons in the meantime. | |
1952 | ;; | |
1953 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1954 | ;; that we're doing height reduction. | |
1955 | ; | |
1956 | ;(define_insn_and_split "" | |
1957 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1958 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1959 | ; [(match_operand 2 "" "") | |
1960 | ; (match_operand 3 "" "")]) | |
1961 | ; (match_operator:BI 4 "comparison_operator" | |
1962 | ; [(match_operand 5 "" "") | |
1963 | ; (match_operand 6 "" "")])) | |
1964 | ; (match_dup 0)))] | |
1965 | ; "flag_schedule_insns" | |
1966 | ; "#" | |
1967 | ; "" | |
1968 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1969 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1970 | ; "") | |
1971 | ; | |
1972 | ;(define_insn_and_split "" | |
1973 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1974 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1975 | ; [(match_operand 2 "" "") | |
1976 | ; (match_operand 3 "" "")]) | |
1977 | ; (match_operator:BI 4 "comparison_operator" | |
1978 | ; [(match_operand 5 "" "") | |
1979 | ; (match_operand 6 "" "")])) | |
1980 | ; (match_dup 0)))] | |
1981 | ; "flag_schedule_insns" | |
1982 | ; "#" | |
1983 | ; "" | |
1984 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1985 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1986 | ; "") | |
1987 | ; | |
1988 | ;(define_split | |
1989 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1990 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1991 | ; [(match_operand 2 "" "") | |
1992 | ; (match_operand 3 "" "")]) | |
1993 | ; (match_operand:BI 7 "register_operand" "")) | |
1994 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1995 | ; [(match_operand 5 "" "") | |
1996 | ; (match_operand 6 "" "")]) | |
1997 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1998 | ; "" | |
1999 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
2000 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
2001 | ; (match_dup 0)))] | |
2002 | ; "") | |
2003 | ; | |
2004 | ;(define_split | |
2005 | ; [(set (match_operand:BI 0 "register_operand" "") | |
2006 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
2007 | ; [(match_operand 2 "" "") | |
2008 | ; (match_operand 3 "" "")]) | |
2009 | ; (match_operand:BI 7 "register_operand" "")) | |
2010 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
2011 | ; [(match_operand 5 "" "") | |
2012 | ; (match_operand 6 "" "")]) | |
2013 | ; (match_operand:BI 8 "register_operand" ""))))] | |
2014 | ; "" | |
2015 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
2016 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
2017 | ; (match_dup 0)))] | |
2018 | ; "") | |
2019 | ||
2020 | ;; Try harder to avoid predicate copies by duplicating compares. | |
2021 | ;; Note that we'll have already split the predicate copy, which | |
2022 | ;; is kind of a pain, but oh well. | |
2023 | ||
2024 | (define_peephole2 | |
2025 | [(set (match_operand:BI 0 "register_operand" "") | |
2026 | (match_operand:BI 1 "comparison_operator" "")) | |
2027 | (set (match_operand:CCI 2 "register_operand" "") | |
2028 | (match_operand:CCI 3 "register_operand" "")) | |
2029 | (set (match_operand:CCI 4 "register_operand" "") | |
2030 | (match_operand:CCI 5 "register_operand" "")) | |
2031 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 2032 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
2033 | "REGNO (operands[3]) == REGNO (operands[0]) |
2034 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
2035 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
2036 | && REGNO (operands[6]) == REGNO (operands[2])" | |
2037 | [(set (match_dup 0) (match_dup 1)) | |
2038 | (set (match_dup 6) (match_dup 7))] | |
2039 | "operands[7] = copy_rtx (operands[1]);") | |
2040 | \f | |
2041 | ;; :::::::::::::::::::: | |
2042 | ;; :: | |
27a9b99d | 2043 | ;; :: 16-bit Integer arithmetic |
cf1f6ae3 RH |
2044 | ;; :: |
2045 | ;; :::::::::::::::::::: | |
2046 | ||
2047 | (define_insn "mulhi3" | |
2048 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
2049 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
2050 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
2051 | "" | |
2a7ffc85 | 2052 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 2053 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
2054 | |
2055 | \f | |
2056 | ;; :::::::::::::::::::: | |
c65ebc55 | 2057 | ;; :: |
27a9b99d | 2058 | ;; :: 32-bit Integer arithmetic |
c65ebc55 JW |
2059 | ;; :: |
2060 | ;; :::::::::::::::::::: | |
2061 | ||
058557c4 | 2062 | (define_insn "addsi3" |
0551c32d RH |
2063 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
2064 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
2065 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2066 | "" |
2067 | "@ | |
1d5d7a21 RH |
2068 | add %0 = %1, %2 |
2069 | adds %0 = %2, %1 | |
2070 | addl %0 = %2, %1" | |
52e12ad0 | 2071 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2072 | |
2073 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
2074 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2075 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
2076 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2077 | (const_int 1)))] |
2078 | "" | |
2079 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2080 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2081 | |
5527bf14 | 2082 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
2083 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2084 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2085 | (const_int 2)) |
2086 | (const_int 1)))] | |
2087 | "" | |
2088 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2089 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2090 | |
058557c4 | 2091 | (define_insn "*addsi3_shladd" |
0551c32d RH |
2092 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2093 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 2094 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 2095 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 2096 | "" |
058557c4 | 2097 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 2098 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2099 | |
058557c4 | 2100 | (define_insn "subsi3" |
0551c32d RH |
2101 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2102 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
2103 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2104 | "" |
2105 | "sub %0 = %1, %2" | |
52e12ad0 | 2106 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2107 | |
2108 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
2109 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2110 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
2111 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2112 | "" |
2113 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
2114 | [(set_attr "itanium_class" "ialu")]) |
2115 | ||
2116 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 2117 | |
058557c4 | 2118 | (define_insn "mulsi3" |
0551c32d | 2119 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
2120 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
2121 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2122 | "" |
aebf2462 | 2123 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2124 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 2125 | |
655f2eb9 | 2126 | (define_insn "maddsi4" |
11a13704 RH |
2127 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
2128 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
2129 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
2130 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
2131 | "" | |
aebf2462 | 2132 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2133 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 2134 | |
058557c4 | 2135 | (define_insn "negsi2" |
0551c32d RH |
2136 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2137 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2138 | "" |
2139 | "sub %0 = r0, %1" | |
52e12ad0 | 2140 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2141 | |
2142 | (define_expand "abssi2" | |
2143 | [(set (match_dup 2) | |
f2f90c63 | 2144 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2145 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 2146 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2147 | (neg:SI (match_dup 1)) |
2148 | (match_dup 1)))] | |
c65ebc55 | 2149 | "" |
1d5d7a21 | 2150 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2151 | |
2152 | (define_expand "sminsi3" | |
2153 | [(set (match_dup 3) | |
f2f90c63 | 2154 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2155 | (match_operand:SI 2 "gr_register_operand" ""))) |
2156 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2157 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2158 | (match_dup 2) (match_dup 1)))] |
2159 | "" | |
1d5d7a21 | 2160 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2161 | |
2162 | (define_expand "smaxsi3" | |
2163 | [(set (match_dup 3) | |
f2f90c63 | 2164 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2165 | (match_operand:SI 2 "gr_register_operand" ""))) |
2166 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2167 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2168 | (match_dup 1) (match_dup 2)))] |
2169 | "" | |
1d5d7a21 | 2170 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2171 | |
2172 | (define_expand "uminsi3" | |
2173 | [(set (match_dup 3) | |
f2f90c63 | 2174 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2175 | (match_operand:SI 2 "gr_register_operand" ""))) |
2176 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2177 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2178 | (match_dup 2) (match_dup 1)))] |
2179 | "" | |
1d5d7a21 | 2180 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2181 | |
2182 | (define_expand "umaxsi3" | |
2183 | [(set (match_dup 3) | |
f2f90c63 | 2184 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2185 | (match_operand:SI 2 "gr_register_operand" ""))) |
2186 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2187 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2188 | (match_dup 1) (match_dup 2)))] |
2189 | "" | |
1d5d7a21 | 2190 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2191 | \f |
2192 | ;; :::::::::::::::::::: | |
2193 | ;; :: | |
27a9b99d | 2194 | ;; :: 64-bit Integer arithmetic |
c65ebc55 JW |
2195 | ;; :: |
2196 | ;; :::::::::::::::::::: | |
2197 | ||
2198 | (define_insn "adddi3" | |
0551c32d RH |
2199 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2200 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2201 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2202 | "" |
2203 | "@ | |
1d5d7a21 RH |
2204 | add %0 = %1, %2 |
2205 | adds %0 = %2, %1 | |
2206 | addl %0 = %2, %1" | |
52e12ad0 | 2207 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2208 | |
2209 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2210 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2211 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2212 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2213 | (const_int 1)))] |
2214 | "" | |
2215 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2216 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2217 | |
5527bf14 RH |
2218 | ;; This has some of the same problems as shladd. We let the shladd |
2219 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2220 | ;; a register, but not more ugliness here. | |
2221 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2222 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2223 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2224 | (const_int 2)) |
2225 | (const_int 1)))] | |
2226 | "" | |
2227 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2228 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2229 | |
c65ebc55 | 2230 | (define_insn "subdi3" |
0551c32d RH |
2231 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2232 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2233 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2234 | "" |
2235 | "sub %0 = %1, %2" | |
52e12ad0 | 2236 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2237 | |
2238 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2239 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2240 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2241 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2242 | "" |
2243 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2244 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2245 | |
cee58bc0 RH |
2246 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2247 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2248 | (define_insn "muldi3" |
0551c32d | 2249 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2250 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2251 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2252 | "" |
aebf2462 | 2253 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2254 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2255 | |
2256 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2257 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2258 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2259 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2260 | ;; here so that it will be present just in case register elimination gives us | |
2261 | ;; the funny result. | |
2262 | ||
2263 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2264 | ||
2265 | ;; ??? Maybe we should change how adds are canonicalized. | |
2266 | ||
655f2eb9 | 2267 | (define_insn "madddi4" |
0551c32d | 2268 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2269 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2270 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2271 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2272 | (clobber (match_scratch:DI 4 "=X"))] |
2273 | "" | |
aebf2462 | 2274 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2275 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2276 | |
2277 | ;; This can be created by register elimination if operand3 of shladd is an | |
2278 | ;; eliminable register or has reg_equiv_constant set. | |
2279 | ||
2280 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2281 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2282 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2283 | ;; incorrectly. |
2284 | ||
655f2eb9 | 2285 | (define_insn "*madddi4_elim" |
c65ebc55 | 2286 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2287 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2288 | (match_operand:DI 2 "register_operand" "f")) | |
2289 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2290 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2291 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2292 | "reload_in_progress" |
2293 | "#" | |
52e12ad0 | 2294 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2295 | |
c65ebc55 JW |
2296 | (define_split |
2297 | [(set (match_operand:DI 0 "register_operand" "") | |
2298 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2299 | (match_operand:DI 2 "register_operand" "")) | |
2300 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2301 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2302 | (clobber (match_scratch:DI 5 ""))] |
2303 | "reload_completed" | |
2304 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2305 | (match_dup 3))) | |
2306 | (clobber (match_dup 0))]) | |
c65ebc55 | 2307 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2308 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2309 | "") | |
2310 | ||
c65ebc55 | 2311 | (define_insn "smuldi3_highpart" |
0551c32d | 2312 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2313 | (truncate:DI |
2314 | (lshiftrt:TI | |
0551c32d | 2315 | (mult:TI (sign_extend:TI |
6adb807e | 2316 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
0551c32d | 2317 | (sign_extend:TI |
6adb807e | 2318 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))) |
c65ebc55 JW |
2319 | (const_int 64))))] |
2320 | "" | |
6adb807e | 2321 | "xmpy.h %0 = %F1, %F2" |
52e12ad0 | 2322 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2323 | |
2324 | (define_insn "umuldi3_highpart" | |
0551c32d | 2325 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2326 | (truncate:DI |
2327 | (lshiftrt:TI | |
0551c32d | 2328 | (mult:TI (zero_extend:TI |
6adb807e | 2329 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
0551c32d | 2330 | (zero_extend:TI |
6adb807e | 2331 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))) |
c65ebc55 JW |
2332 | (const_int 64))))] |
2333 | "" | |
6adb807e | 2334 | "xmpy.hu %0 = %F1, %F2" |
52e12ad0 | 2335 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2336 | |
2337 | (define_insn "negdi2" | |
0551c32d RH |
2338 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2339 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2340 | "" |
2341 | "sub %0 = r0, %1" | |
52e12ad0 | 2342 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2343 | |
2344 | (define_expand "absdi2" | |
2345 | [(set (match_dup 2) | |
f2f90c63 | 2346 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2347 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2348 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2349 | (neg:DI (match_dup 1)) |
2350 | (match_dup 1)))] | |
c65ebc55 | 2351 | "" |
1d5d7a21 | 2352 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2353 | |
2354 | (define_expand "smindi3" | |
2355 | [(set (match_dup 3) | |
f2f90c63 | 2356 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2357 | (match_operand:DI 2 "gr_register_operand" ""))) |
2358 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2359 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2360 | (match_dup 2) (match_dup 1)))] |
2361 | "" | |
1d5d7a21 | 2362 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2363 | |
2364 | (define_expand "smaxdi3" | |
2365 | [(set (match_dup 3) | |
f2f90c63 | 2366 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2367 | (match_operand:DI 2 "gr_register_operand" ""))) |
2368 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2369 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2370 | (match_dup 1) (match_dup 2)))] |
2371 | "" | |
1d5d7a21 | 2372 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2373 | |
2374 | (define_expand "umindi3" | |
2375 | [(set (match_dup 3) | |
f2f90c63 | 2376 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2377 | (match_operand:DI 2 "gr_register_operand" ""))) |
2378 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2379 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2380 | (match_dup 2) (match_dup 1)))] |
2381 | "" | |
1d5d7a21 | 2382 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2383 | |
2384 | (define_expand "umaxdi3" | |
2385 | [(set (match_dup 3) | |
f2f90c63 | 2386 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2387 | (match_operand:DI 2 "gr_register_operand" ""))) |
2388 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2389 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2390 | (match_dup 1) (match_dup 2)))] |
2391 | "" | |
1d5d7a21 | 2392 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2393 | |
2394 | (define_expand "ffsdi2" | |
2395 | [(set (match_dup 6) | |
f2f90c63 | 2396 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2397 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2398 | (set (match_dup 5) (const_int 0)) | |
2399 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2400 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2401 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2402 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2403 | (match_dup 5) (match_dup 4)))] |
2404 | "" | |
c65ebc55 JW |
2405 | { |
2406 | operands[2] = gen_reg_rtx (DImode); | |
2407 | operands[3] = gen_reg_rtx (DImode); | |
2408 | operands[4] = gen_reg_rtx (DImode); | |
2409 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2410 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2411 | }) |
c65ebc55 | 2412 | |
c407570a RH |
2413 | (define_expand "ctzdi2" |
2414 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2415 | (const_int -1))) | |
2416 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2417 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2418 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2419 | (popcount:DI (match_dup 4)))] | |
2420 | "" | |
2421 | { | |
2422 | operands[2] = gen_reg_rtx (DImode); | |
2423 | operands[3] = gen_reg_rtx (DImode); | |
2424 | operands[4] = gen_reg_rtx (DImode); | |
2425 | }) | |
2426 | ||
c407570a RH |
2427 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2428 | (define_expand "clzdi2" | |
2429 | [(set (match_dup 2) | |
6adb807e | 2430 | (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))) |
c407570a RH |
2431 | (set (match_dup 3) |
2432 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2433 | (set (match_dup 4) (const_int 65598)) | |
2434 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2435 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2436 | "" |
c407570a | 2437 | { |
02befdf4 | 2438 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2439 | operands[3] = gen_reg_rtx (DImode); |
2440 | operands[4] = gen_reg_rtx (DImode); | |
2441 | }) | |
2442 | ||
2443 | (define_insn "popcountdi2" | |
0551c32d | 2444 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2445 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2446 | "" |
2447 | "popcnt %0 = %1" | |
52e12ad0 | 2448 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2449 | |
ff848f0e RS |
2450 | (define_insn "bswapdi2" |
2451 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
2452 | (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
2453 | "" | |
2454 | "mux1 %0 = %1, @rev" | |
2455 | [(set_attr "itanium_class" "mmshf")]) | |
2456 | ||
02befdf4 | 2457 | (define_insn "*getf_exp_xf" |
c407570a | 2458 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6adb807e | 2459 | (unspec:DI [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")] |
c407570a | 2460 | UNSPEC_GETF_EXP))] |
02befdf4 | 2461 | "" |
6adb807e | 2462 | "getf.exp %0 = %F1" |
c407570a | 2463 | [(set_attr "itanium_class" "frfr")]) |
c65ebc55 JW |
2464 | \f |
2465 | ;; :::::::::::::::::::: | |
2466 | ;; :: | |
27a9b99d | 2467 | ;; :: 128-bit Integer arithmetic |
a71aef0b JB |
2468 | ;; :: |
2469 | ;; :::::::::::::::::::: | |
2470 | ||
2471 | (define_insn "addti3" | |
2472 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2473 | (plus:TI (match_operand:TI 1 "gr_register_operand" "%r") | |
2474 | (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI"))) | |
2475 | (clobber (match_scratch:BI 3 "=&c"))] | |
2476 | "" | |
2477 | "#" | |
2478 | [(set_attr "itanium_class" "unknown")]) | |
2479 | ||
2480 | (define_split | |
2481 | [(set (match_operand:TI 0 "register_operand" "") | |
2482 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2483 | (match_operand:TI 2 "register_operand" ""))) | |
2484 | (clobber (match_scratch:BI 3 ""))] | |
2485 | "reload_completed" | |
2486 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2487 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2488 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2489 | (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6)))) | |
2490 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2491 | (set (match_dup 4) | |
2492 | (plus:DI (plus:DI (match_dup 5) (match_dup 6)) | |
2493 | (const_int 1))))] | |
2494 | { | |
2495 | operands[4] = gen_highpart (DImode, operands[0]); | |
2496 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2497 | operands[5] = gen_highpart (DImode, operands[1]); | |
2498 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2499 | operands[6] = gen_highpart (DImode, operands[2]); | |
2500 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2501 | }) | |
2502 | ||
2503 | (define_split | |
2504 | [(set (match_operand:TI 0 "register_operand" "") | |
2505 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2506 | (match_operand:TI 2 "immediate_operand" ""))) | |
2507 | (clobber (match_scratch:BI 3 ""))] | |
2508 | "reload_completed" | |
2509 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2510 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2511 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2512 | (set (match_dup 4) | |
2513 | (plus:DI (match_dup 5) (match_dup 6)))) | |
2514 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2515 | (set (match_dup 4) | |
2516 | (plus:DI (match_dup 5) (match_dup 7))))] | |
2517 | { | |
2518 | operands[4] = gen_highpart (DImode, operands[0]); | |
2519 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2520 | operands[5] = gen_highpart (DImode, operands[1]); | |
2521 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2522 | operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx; | |
2523 | operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx; | |
2524 | }) | |
2525 | ||
2526 | (define_insn "subti3" | |
2527 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2528 | (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK") | |
2529 | (match_operand:TI 2 "gr_register_operand" "r"))) | |
2530 | (clobber (match_scratch:BI 3 "=&c"))] | |
2531 | "" | |
2532 | "#" | |
2533 | [(set_attr "itanium_class" "unknown")]) | |
2534 | ||
2535 | (define_split | |
2536 | [(set (match_operand:TI 0 "register_operand" "") | |
2537 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
2538 | (match_operand:TI 2 "register_operand" ""))) | |
2539 | (clobber (match_scratch:BI 3 "=&c"))] | |
2540 | "reload_completed" | |
2541 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) | |
2542 | (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0))) | |
2543 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2544 | (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6)))) | |
2545 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2546 | (set (match_dup 4) | |
2547 | (plus:DI (not:DI (match_dup 6)) (match_dup 5))))] | |
2548 | { | |
2549 | operands[4] = gen_highpart (DImode, operands[0]); | |
2550 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2551 | operands[5] = gen_highpart (DImode, operands[1]); | |
2552 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2553 | operands[6] = gen_highpart (DImode, operands[2]); | |
2554 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2555 | }) | |
2556 | ||
2557 | (define_split | |
2558 | [(set (match_operand:TI 0 "register_operand" "") | |
2559 | (minus:TI (match_operand:TI 1 "immediate_operand" "") | |
2560 | (match_operand:TI 2 "register_operand" ""))) | |
2561 | (clobber (match_scratch:BI 3 "=&c"))] | |
13f70342 | 2562 | "reload_completed && satisfies_constraint_K (operands[1])" |
a71aef0b JB |
2563 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) |
2564 | (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1))) | |
2565 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2566 | (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5)))) | |
2567 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2568 | (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))] | |
2569 | { | |
2570 | operands[4] = gen_highpart (DImode, operands[0]); | |
2571 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2572 | operands[5] = gen_highpart (DImode, operands[2]); | |
2573 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2574 | operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx; | |
2575 | operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; | |
2576 | }) | |
2577 | ||
2578 | (define_expand "mulditi3" | |
2579 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2580 | (mult:TI (sign_extend:TI | |
6adb807e | 2581 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "")) |
a71aef0b | 2582 | (sign_extend:TI |
6adb807e | 2583 | (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))] |
a71aef0b JB |
2584 | "" |
2585 | "") | |
2586 | ||
2587 | (define_insn_and_split "*mulditi3_internal" | |
2588 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2589 | (mult:TI (sign_extend:TI | |
6adb807e | 2590 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
a71aef0b | 2591 | (sign_extend:TI |
6adb807e | 2592 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))] |
a71aef0b JB |
2593 | "" |
2594 | "#" | |
2595 | "reload_completed" | |
2596 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2597 | (set (match_dup 3) (truncate:DI | |
2598 | (lshiftrt:TI | |
2599 | (mult:TI (sign_extend:TI (match_dup 1)) | |
2600 | (sign_extend:TI (match_dup 2))) | |
2601 | (const_int 64))))] | |
2602 | { | |
2603 | operands[3] = gen_highpart (DImode, operands[0]); | |
2604 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2605 | } | |
2606 | [(set_attr "itanium_class" "unknown")]) | |
2607 | ||
2608 | (define_expand "umulditi3" | |
2609 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2610 | (mult:TI (zero_extend:TI | |
6adb807e | 2611 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "")) |
a71aef0b | 2612 | (zero_extend:TI |
6adb807e | 2613 | (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))] |
a71aef0b JB |
2614 | "" |
2615 | "") | |
2616 | ||
2617 | (define_insn_and_split "*umulditi3_internal" | |
2618 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2619 | (mult:TI (zero_extend:TI | |
6adb807e | 2620 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
a71aef0b | 2621 | (zero_extend:TI |
6adb807e | 2622 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))] |
a71aef0b JB |
2623 | "" |
2624 | "#" | |
2625 | "reload_completed" | |
2626 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2627 | (set (match_dup 3) (truncate:DI | |
2628 | (lshiftrt:TI | |
2629 | (mult:TI (zero_extend:TI (match_dup 1)) | |
2630 | (zero_extend:TI (match_dup 2))) | |
2631 | (const_int 64))))] | |
2632 | { | |
2633 | operands[3] = gen_highpart (DImode, operands[0]); | |
2634 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2635 | } | |
2636 | [(set_attr "itanium_class" "unknown")]) | |
2637 | ||
2638 | (define_insn_and_split "negti2" | |
2639 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2640 | (neg:TI (match_operand:TI 1 "gr_register_operand" "r"))) | |
2641 | (clobber (match_scratch:BI 2 "=&c"))] | |
2642 | "" | |
2643 | "#" | |
2644 | "reload_completed" | |
2645 | [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0))) | |
2646 | (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1))) | |
2647 | (cond_exec (eq (match_dup 2) (const_int 0)) | |
2648 | (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4)))) | |
2649 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
2650 | (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))] | |
2651 | { | |
2652 | operands[3] = gen_highpart (DImode, operands[0]); | |
2653 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2654 | operands[4] = gen_highpart (DImode, operands[1]); | |
2655 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2656 | } | |
2657 | [(set_attr "itanium_class" "unknown")]) | |
2658 | \f | |
2659 | ;; :::::::::::::::::::: | |
2660 | ;; :: | |
27a9b99d | 2661 | ;; :: 32-bit floating point arithmetic |
c65ebc55 JW |
2662 | ;; :: |
2663 | ;; :::::::::::::::::::: | |
2664 | ||
2665 | (define_insn "addsf3" | |
0551c32d | 2666 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2667 | (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2668 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2669 | "" |
6adb807e | 2670 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 2671 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2672 | |
2673 | (define_insn "subsf3" | |
0551c32d RH |
2674 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2675 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2676 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2677 | "" |
aebf2462 | 2678 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2679 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2680 | |
2681 | (define_insn "mulsf3" | |
0551c32d | 2682 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
2683 | (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
2684 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2685 | "" |
6adb807e | 2686 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 2687 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2688 | |
2689 | (define_insn "abssf2" | |
0551c32d | 2690 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2691 | (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2692 | "" |
6adb807e | 2693 | "fabs %0 = %F1" |
52e12ad0 | 2694 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2695 | |
2696 | (define_insn "negsf2" | |
0551c32d | 2697 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2698 | (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2699 | "" |
6adb807e | 2700 | "fneg %0 = %F1" |
52e12ad0 | 2701 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2702 | |
2703 | (define_insn "*nabssf2" | |
0551c32d | 2704 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2705 | (neg:SF (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))))] |
c65ebc55 | 2706 | "" |
6adb807e | 2707 | "fnegabs %0 = %F1" |
52e12ad0 | 2708 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2709 | |
046625fa RH |
2710 | (define_insn "copysignsf3" |
2711 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2712 | (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2713 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2714 | UNSPEC_COPYSIGN))] | |
2715 | "" | |
2716 | "fmerge.s %0 = %F2, %F1" | |
2717 | [(set_attr "itanium_class" "fmisc")]) | |
2718 | ||
2719 | (define_insn "*ncopysignsf3" | |
2720 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2721 | (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2722 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2723 | UNSPEC_COPYSIGN)))] | |
2724 | "" | |
2725 | "fmerge.ns %0 = %F2, %F1" | |
2726 | [(set_attr "itanium_class" "fmisc")]) | |
2727 | ||
7ae4d8d4 | 2728 | (define_insn "sminsf3" |
0551c32d | 2729 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2730 | (smin:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2731 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2732 | "" |
6adb807e | 2733 | "fmin %0 = %F1, %F2" |
52e12ad0 | 2734 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2735 | |
7ae4d8d4 | 2736 | (define_insn "smaxsf3" |
0551c32d | 2737 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2738 | (smax:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2739 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2740 | "" |
6adb807e | 2741 | "fmax %0 = %F1, %F2" |
52e12ad0 | 2742 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2743 | |
655f2eb9 | 2744 | (define_insn "*maddsf4" |
0551c32d | 2745 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
2746 | (plus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
2747 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 2748 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
583ca921 | 2749 | "TARGET_FUSED_MADD" |
6adb807e | 2750 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 2751 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2752 | |
655f2eb9 | 2753 | (define_insn "*msubsf4" |
0551c32d | 2754 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
2755 | (minus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
2756 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 2757 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
583ca921 | 2758 | "TARGET_FUSED_MADD" |
6adb807e | 2759 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 2760 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2761 | |
2762 | (define_insn "*nmulsf3" | |
0551c32d | 2763 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
2764 | (neg:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
2765 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 2766 | "" |
6adb807e | 2767 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 2768 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2769 | |
655f2eb9 | 2770 | (define_insn "*nmaddsf4" |
0551c32d | 2771 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
52ad4d7b | 2772 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
2773 | (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
2774 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
583ca921 | 2775 | "TARGET_FUSED_MADD" |
6adb807e | 2776 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 2777 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2778 | \f |
2779 | ;; :::::::::::::::::::: | |
2780 | ;; :: | |
27a9b99d | 2781 | ;; :: 64-bit floating point arithmetic |
c65ebc55 JW |
2782 | ;; :: |
2783 | ;; :::::::::::::::::::: | |
2784 | ||
2785 | (define_insn "adddf3" | |
0551c32d | 2786 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2787 | (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2788 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2789 | "" |
6adb807e | 2790 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 2791 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2792 | |
26102535 RH |
2793 | (define_insn "*adddf3_trunc" |
2794 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2795 | (float_truncate:SF | |
6adb807e | 2796 | (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
26102535 RH |
2797 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] |
2798 | "" | |
6adb807e | 2799 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 2800 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2801 | |
c65ebc55 | 2802 | (define_insn "subdf3" |
0551c32d RH |
2803 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2804 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2805 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2806 | "" |
aebf2462 | 2807 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 2808 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2809 | |
26102535 RH |
2810 | (define_insn "*subdf3_trunc" |
2811 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2812 | (float_truncate:SF | |
2813 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2814 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2815 | "" | |
aebf2462 | 2816 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2817 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2818 | |
c65ebc55 | 2819 | (define_insn "muldf3" |
0551c32d | 2820 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
2821 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2822 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2823 | "" |
6adb807e | 2824 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 2825 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2826 | |
26102535 RH |
2827 | (define_insn "*muldf3_trunc" |
2828 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2829 | (float_truncate:SF | |
6adb807e SE |
2830 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2831 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
26102535 | 2832 | "" |
6adb807e | 2833 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 2834 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2835 | |
c65ebc55 | 2836 | (define_insn "absdf2" |
0551c32d | 2837 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2838 | (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2839 | "" |
6adb807e | 2840 | "fabs %0 = %F1" |
52e12ad0 | 2841 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2842 | |
2843 | (define_insn "negdf2" | |
0551c32d | 2844 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2845 | (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2846 | "" |
6adb807e | 2847 | "fneg %0 = %F1" |
52e12ad0 | 2848 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2849 | |
2850 | (define_insn "*nabsdf2" | |
0551c32d | 2851 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2852 | (neg:DF (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))))] |
c65ebc55 | 2853 | "" |
6adb807e | 2854 | "fnegabs %0 = %F1" |
52e12ad0 | 2855 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2856 | |
046625fa RH |
2857 | (define_insn "copysigndf3" |
2858 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2859 | (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2860 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
2861 | UNSPEC_COPYSIGN))] | |
2862 | "" | |
2863 | "fmerge.s %0 = %F2, %F1" | |
2864 | [(set_attr "itanium_class" "fmisc")]) | |
2865 | ||
2866 | (define_insn "*ncopysigndf3" | |
2867 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2868 | (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2869 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
2870 | UNSPEC_COPYSIGN)))] | |
2871 | "" | |
2872 | "fmerge.ns %0 = %F2, %F1" | |
2873 | [(set_attr "itanium_class" "fmisc")]) | |
2874 | ||
7ae4d8d4 | 2875 | (define_insn "smindf3" |
0551c32d | 2876 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2877 | (smin:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2878 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2879 | "" |
6adb807e | 2880 | "fmin %0 = %F1, %F2" |
52e12ad0 | 2881 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2882 | |
7ae4d8d4 | 2883 | (define_insn "smaxdf3" |
0551c32d | 2884 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2885 | (smax:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2886 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2887 | "" |
6adb807e | 2888 | "fmax %0 = %F1, %F2" |
52e12ad0 | 2889 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2890 | |
655f2eb9 | 2891 | (define_insn "*madddf4" |
0551c32d | 2892 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
2893 | (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2894 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 2895 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
583ca921 | 2896 | "TARGET_FUSED_MADD" |
6adb807e | 2897 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 2898 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2899 | |
26102535 RH |
2900 | (define_insn "*madddf4_trunc" |
2901 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2902 | (float_truncate:SF | |
6adb807e SE |
2903 | (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2904 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
26102535 | 2905 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] |
583ca921 | 2906 | "TARGET_FUSED_MADD" |
6adb807e | 2907 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 2908 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2909 | |
655f2eb9 | 2910 | (define_insn "*msubdf4" |
0551c32d | 2911 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
2912 | (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2913 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 2914 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
583ca921 | 2915 | "TARGET_FUSED_MADD" |
6adb807e | 2916 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 2917 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2918 | |
26102535 RH |
2919 | (define_insn "*msubdf4_trunc" |
2920 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2921 | (float_truncate:SF | |
6adb807e SE |
2922 | (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2923 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
26102535 | 2924 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] |
583ca921 | 2925 | "TARGET_FUSED_MADD" |
6adb807e | 2926 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 2927 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2928 | |
c65ebc55 | 2929 | (define_insn "*nmuldf3" |
0551c32d | 2930 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
2931 | (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2932 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 2933 | "" |
6adb807e | 2934 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 2935 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2936 | |
26102535 RH |
2937 | (define_insn "*nmuldf3_trunc" |
2938 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2939 | (float_truncate:SF | |
6adb807e SE |
2940 | (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2941 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))] | |
26102535 | 2942 | "" |
6adb807e | 2943 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 2944 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2945 | |
655f2eb9 | 2946 | (define_insn "*nmadddf4" |
0551c32d | 2947 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
52ad4d7b | 2948 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
2949 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2950 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
583ca921 | 2951 | "TARGET_FUSED_MADD" |
6adb807e | 2952 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 2953 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2954 | |
52ad4d7b | 2955 | (define_insn "*nmadddf4_truncsf" |
26102535 RH |
2956 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2957 | (float_truncate:SF | |
52ad4d7b | 2958 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
2959 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2960 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))] | |
583ca921 | 2961 | "TARGET_FUSED_MADD" |
6adb807e | 2962 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 2963 | [(set_attr "itanium_class" "fmac")]) |
3f622353 RH |
2964 | \f |
2965 | ;; :::::::::::::::::::: | |
2966 | ;; :: | |
27a9b99d | 2967 | ;; :: 80-bit floating point arithmetic |
3f622353 RH |
2968 | ;; :: |
2969 | ;; :::::::::::::::::::: | |
2970 | ||
02befdf4 ZW |
2971 | (define_insn "addxf3" |
2972 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
2973 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
2974 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
2975 | "" | |
aebf2462 | 2976 | "fadd %0 = %F1, %F2" |
52e12ad0 | 2977 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 2978 | |
02befdf4 | 2979 | (define_insn "*addxf3_truncsf" |
26102535 RH |
2980 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2981 | (float_truncate:SF | |
02befdf4 ZW |
2982 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
2983 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
2984 | "" | |
aebf2462 | 2985 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 2986 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2987 | |
02befdf4 | 2988 | (define_insn "*addxf3_truncdf" |
26102535 RH |
2989 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2990 | (float_truncate:DF | |
02befdf4 ZW |
2991 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
2992 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
2993 | "" | |
aebf2462 | 2994 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 2995 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2996 | |
02befdf4 ZW |
2997 | (define_insn "subxf3" |
2998 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
2999 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3000 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3001 | "" | |
aebf2462 | 3002 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3003 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3004 | |
02befdf4 | 3005 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3006 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3007 | (float_truncate:SF | |
02befdf4 ZW |
3008 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3009 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3010 | "" | |
aebf2462 | 3011 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3012 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3013 | |
02befdf4 | 3014 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3015 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3016 | (float_truncate:DF | |
02befdf4 ZW |
3017 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3018 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3019 | "" | |
aebf2462 | 3020 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3021 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3022 | |
02befdf4 ZW |
3023 | (define_insn "mulxf3" |
3024 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3025 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3026 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3027 | "" | |
aebf2462 | 3028 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3029 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3030 | |
02befdf4 | 3031 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3032 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3033 | (float_truncate:SF | |
02befdf4 ZW |
3034 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3035 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3036 | "" | |
aebf2462 | 3037 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3038 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3039 | |
02befdf4 | 3040 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3041 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3042 | (float_truncate:DF | |
02befdf4 ZW |
3043 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3044 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3045 | "" | |
aebf2462 | 3046 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3047 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3048 | |
02befdf4 ZW |
3049 | (define_insn "absxf2" |
3050 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3051 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3052 | "" | |
aebf2462 | 3053 | "fabs %0 = %F1" |
52e12ad0 | 3054 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3055 | |
02befdf4 ZW |
3056 | (define_insn "negxf2" |
3057 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3058 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3059 | "" | |
aebf2462 | 3060 | "fneg %0 = %F1" |
52e12ad0 | 3061 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3062 | |
02befdf4 ZW |
3063 | (define_insn "*nabsxf2" |
3064 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3065 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3066 | "" | |
aebf2462 | 3067 | "fnegabs %0 = %F1" |
52e12ad0 | 3068 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3069 | |
046625fa RH |
3070 | (define_insn "copysignxf3" |
3071 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3072 | (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3073 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3074 | UNSPEC_COPYSIGN))] | |
3075 | "" | |
3076 | "fmerge.s %0 = %F2, %F1" | |
3077 | [(set_attr "itanium_class" "fmisc")]) | |
3078 | ||
3079 | (define_insn "*ncopysignxf3" | |
3080 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3081 | (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3082 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3083 | UNSPEC_COPYSIGN)))] | |
3084 | "" | |
3085 | "fmerge.ns %0 = %F2, %F1" | |
3086 | [(set_attr "itanium_class" "fmisc")]) | |
3087 | ||
7ae4d8d4 | 3088 | (define_insn "sminxf3" |
02befdf4 ZW |
3089 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3090 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3091 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3092 | "" | |
aebf2462 | 3093 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3094 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3095 | |
7ae4d8d4 | 3096 | (define_insn "smaxxf3" |
02befdf4 ZW |
3097 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3098 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3099 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3100 | "" | |
aebf2462 | 3101 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3102 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3103 | |
02befdf4 ZW |
3104 | (define_insn "*maddxf4" |
3105 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3106 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3107 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3108 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
583ca921 | 3109 | "TARGET_FUSED_MADD" |
aebf2462 | 3110 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3111 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3112 | |
02befdf4 | 3113 | (define_insn "*maddxf4_truncsf" |
26102535 RH |
3114 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3115 | (float_truncate:SF | |
02befdf4 ZW |
3116 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3117 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3118 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
583ca921 | 3119 | "TARGET_FUSED_MADD" |
aebf2462 | 3120 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3121 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3122 | |
02befdf4 | 3123 | (define_insn "*maddxf4_truncdf" |
26102535 RH |
3124 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3125 | (float_truncate:DF | |
02befdf4 ZW |
3126 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3127 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3128 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
583ca921 | 3129 | "TARGET_FUSED_MADD" |
aebf2462 | 3130 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3131 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3132 | |
02befdf4 ZW |
3133 | (define_insn "*msubxf4" |
3134 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3135 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3136 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3137 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
583ca921 | 3138 | "TARGET_FUSED_MADD" |
aebf2462 | 3139 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3140 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3141 | |
02befdf4 | 3142 | (define_insn "*msubxf4_truncsf" |
26102535 RH |
3143 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3144 | (float_truncate:SF | |
02befdf4 ZW |
3145 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3146 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3147 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
583ca921 | 3148 | "TARGET_FUSED_MADD" |
aebf2462 | 3149 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3150 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3151 | |
02befdf4 | 3152 | (define_insn "*msubxf4_truncdf" |
26102535 RH |
3153 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3154 | (float_truncate:DF | |
02befdf4 ZW |
3155 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3156 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3157 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
583ca921 | 3158 | "TARGET_FUSED_MADD" |
aebf2462 | 3159 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3160 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3161 | |
02befdf4 ZW |
3162 | (define_insn "*nmulxf3" |
3163 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3164 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3165 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3166 | "" | |
aebf2462 | 3167 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3168 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3169 | |
02befdf4 | 3170 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
3171 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3172 | (float_truncate:SF | |
02befdf4 ZW |
3173 | (neg:XF (mult:XF |
3174 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3175 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3176 | "" | |
aebf2462 | 3177 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3178 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3179 | |
02befdf4 | 3180 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
3181 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3182 | (float_truncate:DF | |
02befdf4 ZW |
3183 | (neg:XF (mult:XF |
3184 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3185 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3186 | "" | |
aebf2462 | 3187 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3188 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3189 | |
02befdf4 ZW |
3190 | (define_insn "*nmaddxf4" |
3191 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3192 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3193 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3194 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3195 | )))] | |
583ca921 | 3196 | "TARGET_FUSED_MADD" |
aebf2462 | 3197 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3198 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3199 | |
02befdf4 | 3200 | (define_insn "*nmaddxf4_truncsf" |
26102535 RH |
3201 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3202 | (float_truncate:SF | |
52ad4d7b ZW |
3203 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3204 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3205 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3206 | ))))] | |
583ca921 | 3207 | "TARGET_FUSED_MADD" |
aebf2462 | 3208 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3209 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3210 | |
02befdf4 | 3211 | (define_insn "*nmaddxf4_truncdf" |
26102535 RH |
3212 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3213 | (float_truncate:DF | |
52ad4d7b ZW |
3214 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3215 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3216 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3217 | ))))] | |
583ca921 | 3218 | "TARGET_FUSED_MADD" |
aebf2462 | 3219 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3220 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3221 | \f |
3222 | ;; :::::::::::::::::::: | |
3223 | ;; :: | |
27a9b99d | 3224 | ;; :: 32-bit Integer Shifts and Rotates |
c65ebc55 JW |
3225 | ;; :: |
3226 | ;; :::::::::::::::::::: | |
3227 | ||
9c668921 | 3228 | (define_expand "ashlsi3" |
0551c32d RH |
3229 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3230 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
3231 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 3232 | "" |
9c668921 RH |
3233 | { |
3234 | if (GET_CODE (operands[2]) != CONST_INT) | |
3235 | { | |
3236 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
3237 | we've got to get rid of stray bits outside the SImode register. */ | |
3238 | rtx subshift = gen_reg_rtx (DImode); | |
3239 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
3240 | operands[2] = subshift; | |
3241 | } | |
1d5d7a21 | 3242 | }) |
9c668921 RH |
3243 | |
3244 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
3245 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
3246 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
3247 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 3248 | "" |
041f25e6 RH |
3249 | "@ |
3250 | shladd %0 = %1, %2, r0 | |
3251 | dep.z %0 = %1, %2, %E2 | |
3252 | shl %0 = %1, %2" | |
52e12ad0 | 3253 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
3254 | |
3255 | (define_expand "ashrsi3" | |
0551c32d RH |
3256 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3257 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3258 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3259 | "" |
c65ebc55 | 3260 | { |
041f25e6 RH |
3261 | rtx subtarget = gen_reg_rtx (DImode); |
3262 | if (GET_CODE (operands[2]) == CONST_INT) | |
3263 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
3264 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3265 | else | |
3266 | { | |
9c668921 | 3267 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3268 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3269 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3270 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3271 | } |
3272 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3273 | DONE; | |
1d5d7a21 | 3274 | }) |
c65ebc55 | 3275 | |
c65ebc55 | 3276 | (define_expand "lshrsi3" |
0551c32d RH |
3277 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3278 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3279 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3280 | "" |
c65ebc55 | 3281 | { |
041f25e6 RH |
3282 | rtx subtarget = gen_reg_rtx (DImode); |
3283 | if (GET_CODE (operands[2]) == CONST_INT) | |
3284 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
3285 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3286 | else | |
3287 | { | |
9c668921 | 3288 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3289 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3290 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3291 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3292 | } |
3293 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3294 | DONE; | |
1d5d7a21 | 3295 | }) |
c65ebc55 | 3296 | |
c65ebc55 | 3297 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
3298 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
3299 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
3300 | |
3301 | (define_expand "rotrsi3" | |
66db6b45 RH |
3302 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3303 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
3304 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
3305 | "" | |
66db6b45 RH |
3306 | { |
3307 | if (GET_MODE (operands[2]) != VOIDmode) | |
3308 | { | |
3309 | rtx tmp = gen_reg_rtx (DImode); | |
3310 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
3311 | operands[2] = tmp; | |
3312 | } | |
1d5d7a21 | 3313 | }) |
66db6b45 RH |
3314 | |
3315 | (define_insn_and_split "*rotrsi3_internal" | |
3316 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
3317 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3318 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
3319 | "" | |
3320 | "#" | |
3321 | "reload_completed" | |
c65ebc55 | 3322 | [(set (match_dup 3) |
66db6b45 | 3323 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
3324 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
3325 | (set (match_dup 3) | |
66db6b45 RH |
3326 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
3327 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
3328 | ||
3329 | (define_expand "rotlsi3" | |
3330 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
3331 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
3332 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3333 | "" |
c65ebc55 JW |
3334 | { |
3335 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
3336 | { |
3337 | rtx tmp = gen_reg_rtx (SImode); | |
3338 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
3339 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
3340 | DONE; | |
3341 | } | |
1d5d7a21 | 3342 | }) |
66db6b45 RH |
3343 | |
3344 | (define_insn_and_split "*rotlsi3_internal" | |
3345 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
3346 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3347 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
3348 | "" | |
51094457 JB |
3349 | "mux2 %0 = %1, 0xe1" |
3350 | "reload_completed && INTVAL (operands[2]) != 16" | |
66db6b45 RH |
3351 | [(set (match_dup 3) |
3352 | (ior:DI (zero_extend:DI (match_dup 1)) | |
3353 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
3354 | (set (match_dup 3) | |
3355 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
3356 | { |
3357 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
3358 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
51094457 JB |
3359 | } |
3360 | [(set_attr "itanium_class" "mmshf")]) | |
c65ebc55 JW |
3361 | \f |
3362 | ;; :::::::::::::::::::: | |
3363 | ;; :: | |
27a9b99d | 3364 | ;; :: 64-bit Integer Shifts and Rotates |
c65ebc55 JW |
3365 | ;; :: |
3366 | ;; :::::::::::::::::::: | |
3367 | ||
3368 | (define_insn "ashldi3" | |
52e12ad0 BS |
3369 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
3370 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
3371 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 3372 | "" |
041f25e6 RH |
3373 | "@ |
3374 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 3375 | shl %0 = %1, %2 |
041f25e6 | 3376 | shl %0 = %1, %2" |
52e12ad0 | 3377 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
3378 | |
3379 | ;; ??? Maybe combine this with the multiply and add instruction? | |
3380 | ||
3381 | (define_insn "*shladd" | |
0551c32d RH |
3382 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3383 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3384 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 3385 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
3386 | "" |
3387 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 3388 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
3389 | |
3390 | ;; This can be created by register elimination if operand3 of shladd is an | |
3391 | ;; eliminable register or has reg_equiv_constant set. | |
3392 | ||
3393 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
3394 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
3395 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
3396 | ;; incorrectly. | |
3397 | ||
5527bf14 | 3398 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
3399 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
3400 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3401 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 3402 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
3403 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
3404 | "reload_in_progress" | |
e820471b | 3405 | "* gcc_unreachable ();" |
c65ebc55 JW |
3406 | "reload_completed" |
3407 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
3408 | (match_dup 3))) | |
c65ebc55 | 3409 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 3410 | "" |
52e12ad0 | 3411 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
3412 | |
3413 | (define_insn "ashrdi3" | |
52e12ad0 BS |
3414 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3415 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3416 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3417 | "" |
52e12ad0 BS |
3418 | "@ |
3419 | shr %0 = %1, %2 | |
3420 | shr %0 = %1, %2" | |
3421 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3422 | |
3423 | (define_insn "lshrdi3" | |
52e12ad0 BS |
3424 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3425 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3426 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3427 | "" |
52e12ad0 BS |
3428 | "@ |
3429 | shr.u %0 = %1, %2 | |
3430 | shr.u %0 = %1, %2" | |
3431 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3432 | |
3433 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
3434 | ;; will load the operand into a register and call the pattern if the predicate | |
3435 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
3436 | ;; verify that we have an appropriate constant in the expander. | |
3437 | ||
3438 | (define_expand "rotrdi3" | |
0551c32d RH |
3439 | [(set (match_operand:DI 0 "gr_register_operand" "") |
3440 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
3441 | (match_operand:DI 2 "nonmemory_operand" "")))] |
3442 | "" | |
c65ebc55 JW |
3443 | { |
3444 | if (! shift_count_operand (operands[2], DImode)) | |
3445 | FAIL; | |
1d5d7a21 | 3446 | }) |
c65ebc55 JW |
3447 | |
3448 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
3449 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3450 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
3451 | (match_operand:DI 2 "shift_count_operand" "M")))] |
3452 | "" | |
3453 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 3454 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 3455 | |
66db6b45 RH |
3456 | (define_expand "rotldi3" |
3457 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3458 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
3459 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3460 | "" | |
66db6b45 RH |
3461 | { |
3462 | if (! shift_count_operand (operands[2], DImode)) | |
3463 | FAIL; | |
1d5d7a21 | 3464 | }) |
66db6b45 RH |
3465 | |
3466 | (define_insn "*rotldi3_internal" | |
3467 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
3468 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
3469 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
3470 | "" | |
3471 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 3472 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
3473 | \f |
3474 | ;; :::::::::::::::::::: | |
3475 | ;; :: | |
27a9b99d | 3476 | ;; :: 128-bit Integer Shifts and Rotates |
f526a3c8 RH |
3477 | ;; :: |
3478 | ;; :::::::::::::::::::: | |
3479 | ||
16d8386b JB |
3480 | (define_expand "ashlti3" |
3481 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
3482 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "") | |
3483 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3484 | "" | |
3485 | { | |
3486 | if (!dshift_count_operand (operands[2], DImode)) | |
3487 | FAIL; | |
3488 | }) | |
3489 | ||
3490 | (define_insn_and_split "*ashlti3_internal" | |
3491 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
3492 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "r") | |
3493 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
3494 | "" | |
3495 | "#" | |
3496 | "reload_completed" | |
3497 | [(const_int 0)] | |
3498 | { | |
3499 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
3500 | rtx rl = gen_lowpart (DImode, operands[0]); | |
3501 | rtx rh = gen_highpart (DImode, operands[0]); | |
3502 | rtx lo = gen_lowpart (DImode, operands[1]); | |
3503 | rtx shiftlo = GEN_INT (shift & 63); | |
3504 | ||
3505 | if (shift & 64) | |
3506 | { | |
3507 | emit_move_insn (rl, const0_rtx); | |
3508 | if (shift & 63) | |
3509 | emit_insn (gen_ashldi3 (rh, lo, shiftlo)); | |
3510 | else | |
3511 | emit_move_insn (rh, lo); | |
3512 | } | |
3513 | else | |
3514 | { | |
3515 | rtx hi = gen_highpart (DImode, operands[1]); | |
3516 | ||
3517 | emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63))); | |
3518 | emit_insn (gen_ashldi3 (rl, lo, shiftlo)); | |
3519 | } | |
3520 | DONE; | |
3521 | }) | |
3522 | ||
f526a3c8 RH |
3523 | (define_expand "ashrti3" |
3524 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
3525 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
3526 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3527 | "" | |
3528 | { | |
3529 | if (!dshift_count_operand (operands[2], DImode)) | |
3530 | FAIL; | |
3531 | }) | |
3532 | ||
3533 | (define_insn_and_split "*ashrti3_internal" | |
16d8386b | 3534 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
3535 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
3536 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
3537 | "" | |
3538 | "#" | |
3539 | "reload_completed" | |
3540 | [(const_int 0)] | |
3541 | { | |
3542 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
3543 | rtx rl = gen_lowpart (DImode, operands[0]); |
3544 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
3545 | rtx hi = gen_highpart (DImode, operands[1]); |
3546 | rtx shiftlo = GEN_INT (shift & 63); | |
3547 | ||
3548 | if (shift & 64) | |
3549 | { | |
16d8386b JB |
3550 | if (shift & 63) |
3551 | emit_insn (gen_ashrdi3 (rl, hi, shiftlo)); | |
3552 | else | |
3553 | emit_move_insn (rl, hi); | |
3554 | emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63))); | |
f526a3c8 RH |
3555 | } |
3556 | else | |
3557 | { | |
16d8386b JB |
3558 | rtx lo = gen_lowpart (DImode, operands[1]); |
3559 | ||
3560 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
3561 | emit_insn (gen_ashrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
3562 | } |
3563 | DONE; | |
3564 | }) | |
3565 | ||
3566 | (define_expand "lshrti3" | |
3567 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
3568 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
3569 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3570 | "" | |
3571 | { | |
3572 | if (!dshift_count_operand (operands[2], DImode)) | |
3573 | FAIL; | |
3574 | }) | |
3575 | ||
3576 | (define_insn_and_split "*lshrti3_internal" | |
16d8386b | 3577 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
3578 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
3579 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
3580 | "" | |
3581 | "#" | |
3582 | "reload_completed" | |
3583 | [(const_int 0)] | |
3584 | { | |
3585 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
3586 | rtx rl = gen_lowpart (DImode, operands[0]); |
3587 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
3588 | rtx hi = gen_highpart (DImode, operands[1]); |
3589 | rtx shiftlo = GEN_INT (shift & 63); | |
3590 | ||
3591 | if (shift & 64) | |
3592 | { | |
16d8386b JB |
3593 | if (shift & 63) |
3594 | emit_insn (gen_lshrdi3 (rl, hi, shiftlo)); | |
3595 | else | |
3596 | emit_move_insn (rl, hi); | |
3597 | emit_move_insn (rh, const0_rtx); | |
f526a3c8 RH |
3598 | } |
3599 | else | |
3600 | { | |
16d8386b JB |
3601 | rtx lo = gen_lowpart (DImode, operands[1]); |
3602 | ||
3603 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
3604 | emit_insn (gen_lshrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
3605 | } |
3606 | DONE; | |
3607 | }) | |
3608 | ||
a71aef0b JB |
3609 | (define_expand "rotlti3" |
3610 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
3611 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "") | |
3612 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3613 | "" | |
3614 | { | |
3615 | if (! dshift_count_operand (operands[2], DImode)) | |
3616 | FAIL; | |
3617 | }) | |
3618 | ||
3619 | (define_insn_and_split "*rotlti3_internal" | |
3620 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
3621 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "r") | |
3622 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
3623 | "" | |
3624 | "#" | |
3625 | "reload_completed" | |
3626 | [(const_int 0)] | |
3627 | { | |
3628 | HOST_WIDE_INT count = INTVAL (operands[2]); | |
3629 | rtx rl = gen_lowpart (DImode, operands[0]); | |
3630 | rtx rh = gen_highpart (DImode, operands[0]); | |
3631 | rtx lo = gen_lowpart (DImode, operands[1]); | |
3632 | rtx hi = gen_highpart (DImode, operands[1]); | |
3633 | rtx countlo = GEN_INT (-count & 63); | |
3634 | ||
3635 | if (count & 64) | |
3636 | { | |
3637 | if (count & 63) | |
3638 | { | |
3639 | emit_insn (gen_shrp (rl, hi, lo, countlo)); | |
3640 | emit_insn (gen_shrp (rh, lo, hi, countlo)); | |
3641 | } | |
3642 | else | |
3643 | { | |
3644 | emit_move_insn (rl, hi); | |
3645 | emit_move_insn (rh, lo); | |
3646 | } | |
3647 | } | |
3648 | else | |
3649 | { | |
3650 | emit_insn (gen_shrp (rl, lo, hi, countlo)); | |
3651 | emit_insn (gen_shrp (rh, hi, lo, countlo)); | |
3652 | } | |
3653 | DONE; | |
3654 | } | |
3655 | [(set_attr "itanium_class" "unknown")]) | |
3656 | ||
f526a3c8 RH |
3657 | (define_insn "shrp" |
3658 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
3659 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
3660 | (match_operand:DI 2 "gr_register_operand" "r") | |
3661 | (match_operand:DI 3 "shift_count_operand" "M")] | |
3662 | UNSPEC_SHRP))] | |
3663 | "" | |
3664 | "shrp %0 = %1, %2, %3" | |
3665 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
3666 | \f |
3667 | ;; :::::::::::::::::::: | |
3668 | ;; :: | |
27a9b99d | 3669 | ;; :: 32-bit Integer Logical operations |
c65ebc55 JW |
3670 | ;; :: |
3671 | ;; :::::::::::::::::::: | |
3672 | ||
3673 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
3674 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
3675 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
3676 | ;; This doesn't work for unary logical operations, because we don't call | |
3677 | ;; apply_distributive_law for them. | |
3678 | ||
3679 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
3680 | ;; apply_distributive_law. We get inefficient code for | |
3681 | ;; int sub4 (int i, int j) { return i & ~j; } | |
3682 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
3683 | ;; (zero_extend (and (not A) B)) in combine. | |
3684 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
3685 | ;; one_cmplsi2 pattern. | |
3686 | ||
058557c4 | 3687 | (define_insn "one_cmplsi2" |
0551c32d RH |
3688 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
3689 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3690 | "" |
3691 | "andcm %0 = -1, %1" | |
52e12ad0 | 3692 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3693 | \f |
3694 | ;; :::::::::::::::::::: | |
3695 | ;; :: | |
27a9b99d | 3696 | ;; :: 64-bit Integer Logical operations |
c65ebc55 JW |
3697 | ;; :: |
3698 | ;; :::::::::::::::::::: | |
3699 | ||
3700 | (define_insn "anddi3" | |
0551c32d RH |
3701 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3702 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3703 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3704 | "" |
3705 | "@ | |
3706 | and %0 = %2, %1 | |
aebf2462 | 3707 | fand %0 = %2, %1" |
52e12ad0 | 3708 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3709 | |
3710 | (define_insn "*andnot" | |
0551c32d RH |
3711 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3712 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
3713 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3714 | "" |
3715 | "@ | |
3716 | andcm %0 = %2, %1 | |
aebf2462 | 3717 | fandcm %0 = %2, %1" |
52e12ad0 | 3718 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3719 | |
3720 | (define_insn "iordi3" | |
0551c32d RH |
3721 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3722 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3723 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3724 | "" |
3725 | "@ | |
3726 | or %0 = %2, %1 | |
aebf2462 | 3727 | for %0 = %2, %1" |
52e12ad0 | 3728 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3729 | |
3730 | (define_insn "xordi3" | |
0551c32d RH |
3731 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3732 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3733 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3734 | "" |
3735 | "@ | |
3736 | xor %0 = %2, %1 | |
aebf2462 | 3737 | fxor %0 = %2, %1" |
52e12ad0 | 3738 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3739 | |
3740 | (define_insn "one_cmpldi2" | |
0551c32d RH |
3741 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3742 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3743 | "" |
3744 | "andcm %0 = -1, %1" | |
52e12ad0 | 3745 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3746 | \f |
3747 | ;; :::::::::::::::::::: | |
3748 | ;; :: | |
3749 | ;; :: Comparisons | |
3750 | ;; :: | |
3751 | ;; :::::::::::::::::::: | |
3752 | ||
f90b7a5a PB |
3753 | (define_expand "cbranchbi4" |
3754 | [(set (pc) | |
3755 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3756 | [(match_operand:BI 1 "register_operand" "") | |
3757 | (match_operand:BI 2 "const_int_operand" "")]) | |
3758 | (label_ref (match_operand 3 "" "")) | |
3759 | (pc)))] | |
f2f90c63 | 3760 | "" |
f90b7a5a | 3761 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
f2f90c63 | 3762 | |
f90b7a5a PB |
3763 | (define_expand "cbranchsi4" |
3764 | [(set (pc) | |
3765 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3766 | [(match_operand:SI 1 "gr_register_operand" "") | |
3767 | (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
3768 | (label_ref (match_operand 3 "" "")) | |
3769 | (pc)))] | |
c65ebc55 | 3770 | "" |
f90b7a5a | 3771 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3772 | |
f90b7a5a PB |
3773 | (define_expand "cbranchdi4" |
3774 | [(set (pc) | |
3775 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3776 | [(match_operand:DI 1 "gr_register_operand" "") | |
3777 | (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
3778 | (label_ref (match_operand 3 "" "")) | |
3779 | (pc)))] | |
c65ebc55 | 3780 | "" |
f90b7a5a | 3781 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3782 | |
f90b7a5a PB |
3783 | (define_expand "cbranchsf4" |
3784 | [(set (pc) | |
3785 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3786 | [(match_operand:SF 1 "fr_reg_or_fp01_operand" "") | |
3787 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "")]) | |
3788 | (label_ref (match_operand 3 "" "")) | |
3789 | (pc)))] | |
c65ebc55 | 3790 | "" |
f90b7a5a | 3791 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3792 | |
f90b7a5a PB |
3793 | (define_expand "cbranchdf4" |
3794 | [(set (pc) | |
3795 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3796 | [(match_operand:DF 1 "fr_reg_or_fp01_operand" "") | |
3797 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "")]) | |
3798 | (label_ref (match_operand 3 "" "")) | |
3799 | (pc)))] | |
c65ebc55 | 3800 | "" |
f90b7a5a | 3801 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3802 | |
f90b7a5a PB |
3803 | (define_expand "cbranchxf4" |
3804 | [(set (pc) | |
3805 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3806 | [(match_operand:XF 1 "xfreg_or_fp01_operand" "") | |
3807 | (match_operand:XF 2 "xfreg_or_fp01_operand" "")]) | |
3808 | (label_ref (match_operand 3 "" "")) | |
3809 | (pc)))] | |
02befdf4 | 3810 | "" |
f90b7a5a | 3811 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3812 | |
f90b7a5a PB |
3813 | (define_expand "cbranchtf4" |
3814 | [(set (pc) | |
3815 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3816 | [(match_operand:TF 1 "gr_register_operand" "") | |
3817 | (match_operand:TF 2 "gr_register_operand" "")]) | |
3818 | (label_ref (match_operand 3 "" "")) | |
3819 | (pc)))] | |
24ea7948 | 3820 | "TARGET_HPUX" |
f90b7a5a PB |
3821 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
3822 | ||
24ea7948 | 3823 | |
c65ebc55 | 3824 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
3825 | [(set (match_operand:BI 0 "register_operand" "=c") |
3826 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
3827 | [(match_operand:SI 2 "gr_register_operand" "r") |
3828 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
3829 | "" |
3830 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 3831 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3832 | |
18a3c539 JW |
3833 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
3834 | ;; unsigned comparisons don't accept immediate operands of zero. | |
3835 | ||
c65ebc55 | 3836 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
3837 | [(set (match_operand:BI 0 "register_operand" "=c") |
3838 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
3839 | [(match_operand:SI 2 "gr_register_operand" "r") |
3840 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 3841 | "" |
18a3c539 | 3842 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 3843 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
3844 | |
3845 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
3846 | [(set (match_operand:BI 0 "register_operand" "=c") |
3847 | (match_operator:BI 1 "normal_comparison_operator" | |
3848 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 3849 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 3850 | "" |
f2f90c63 | 3851 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 3852 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3853 | |
18a3c539 JW |
3854 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
3855 | ;; unsigned comparisons don't accept immediate operands of zero. | |
3856 | ||
c65ebc55 | 3857 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
3858 | [(set (match_operand:BI 0 "register_operand" "=c") |
3859 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
3860 | [(match_operand:DI 2 "gr_register_operand" "r") |
3861 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 3862 | "" |
18a3c539 | 3863 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 3864 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
3865 | |
3866 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
3867 | [(set (match_operand:BI 0 "register_operand" "=c") |
3868 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
3869 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
3870 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
3871 | "" |
3872 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 3873 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
3874 | |
3875 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
3876 | [(set (match_operand:BI 0 "register_operand" "=c") |
3877 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
3878 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
3879 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
3880 | "" |
3881 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 3882 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 3883 | |
02befdf4 | 3884 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
3885 | [(set (match_operand:BI 0 "register_operand" "=c") |
3886 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
3887 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
3888 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
3889 | "" | |
3f622353 | 3890 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 3891 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 3892 | |
c65ebc55 JW |
3893 | ;; ??? Can this pattern be generated? |
3894 | ||
3895 | (define_insn "*bit_zero" | |
f2f90c63 RH |
3896 | [(set (match_operand:BI 0 "register_operand" "=c") |
3897 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3898 | (const_int 1) |
5d48891e | 3899 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
3900 | (const_int 0)))] |
3901 | "" | |
3902 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 3903 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
3904 | |
3905 | (define_insn "*bit_one" | |
f2f90c63 RH |
3906 | [(set (match_operand:BI 0 "register_operand" "=c") |
3907 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3908 | (const_int 1) |
5d48891e | 3909 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
3910 | (const_int 0)))] |
3911 | "" | |
3912 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 3913 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
3914 | \f |
3915 | ;; :::::::::::::::::::: | |
3916 | ;; :: | |
3917 | ;; :: Branches | |
3918 | ;; :: | |
3919 | ;; :::::::::::::::::::: | |
3920 | ||
6b6c1201 | 3921 | (define_insn "*br_true" |
c65ebc55 | 3922 | [(set (pc) |
6b6c1201 | 3923 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 3924 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
3925 | (const_int 0)]) |
3926 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
3927 | (pc)))] |
3928 | "" | |
85548039 | 3929 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 3930 | [(set_attr "itanium_class" "br") |
e5bde68a | 3931 | (set_attr "predicable" "no")]) |
c65ebc55 | 3932 | |
6b6c1201 | 3933 | (define_insn "*br_false" |
c65ebc55 | 3934 | [(set (pc) |
6b6c1201 | 3935 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 3936 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 3937 | (const_int 0)]) |
c65ebc55 | 3938 | (pc) |
6b6c1201 | 3939 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 3940 | "" |
85548039 | 3941 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 3942 | [(set_attr "itanium_class" "br") |
e5bde68a | 3943 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
3944 | \f |
3945 | ;; :::::::::::::::::::: | |
3946 | ;; :: | |
5527bf14 RH |
3947 | ;; :: Counted loop operations |
3948 | ;; :: | |
3949 | ;; :::::::::::::::::::: | |
3950 | ||
3951 | (define_expand "doloop_end" | |
3952 | [(use (match_operand 0 "" "")) ; loop pseudo | |
3953 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
3954 | (use (match_operand 2 "" "")) ; max iterations | |
3955 | (use (match_operand 3 "" "")) ; loop level | |
3956 | (use (match_operand 4 "" ""))] ; label | |
3957 | "" | |
5527bf14 RH |
3958 | { |
3959 | /* Only use cloop on innermost loops. */ | |
3960 | if (INTVAL (operands[3]) > 1) | |
3961 | FAIL; | |
3962 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
3963 | operands[4])); | |
3964 | DONE; | |
1d5d7a21 | 3965 | }) |
5527bf14 RH |
3966 | |
3967 | (define_insn "doloop_end_internal" | |
3968 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
3969 | (const_int 0)) | |
3970 | (label_ref (match_operand 1 "" "")) | |
3971 | (pc))) | |
3972 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
3973 | (plus:DI (match_dup 0) (const_int -1)) |
3974 | (match_dup 0)))] | |
5527bf14 RH |
3975 | "" |
3976 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 3977 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
3978 | (set_attr "predicable" "no")]) |
3979 | \f | |
3980 | ;; :::::::::::::::::::: | |
3981 | ;; :: | |
c65ebc55 JW |
3982 | ;; :: Set flag operations |
3983 | ;; :: | |
3984 | ;; :::::::::::::::::::: | |
3985 | ||
f90b7a5a PB |
3986 | (define_expand "cstorebi4" |
3987 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3988 | (match_operator:DI 1 "ia64_cbranch_operator" | |
3989 | [(match_operand:BI 2 "register_operand" "") | |
3990 | (match_operand:BI 3 "const_int_operand" "")]))] | |
c65ebc55 | 3991 | "" |
f90b7a5a | 3992 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3993 | |
f90b7a5a PB |
3994 | (define_expand "cstoresi4" |
3995 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3996 | (match_operator:DI 1 "ia64_cbranch_operator" | |
3997 | [(match_operand:SI 2 "gr_register_operand" "") | |
3998 | (match_operand:SI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))] | |
c65ebc55 | 3999 | "" |
f90b7a5a | 4000 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4001 | |
f90b7a5a PB |
4002 | (define_expand "cstoredi4" |
4003 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4004 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4005 | [(match_operand:DI 2 "gr_register_operand" "") | |
4006 | (match_operand:DI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))] | |
c65ebc55 | 4007 | "" |
f90b7a5a | 4008 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4009 | |
f90b7a5a PB |
4010 | (define_expand "cstoresf4" |
4011 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4012 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4013 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "") | |
4014 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "")]))] | |
c65ebc55 | 4015 | "" |
f90b7a5a | 4016 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4017 | |
f90b7a5a PB |
4018 | (define_expand "cstoredf4" |
4019 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4020 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4021 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "") | |
4022 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "")]))] | |
c65ebc55 | 4023 | "" |
f90b7a5a | 4024 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4025 | |
f90b7a5a PB |
4026 | (define_expand "cstorexf4" |
4027 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4028 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4029 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "") | |
4030 | (match_operand:XF 3 "xfreg_or_fp01_operand" "")]))] | |
c65ebc55 | 4031 | "" |
f90b7a5a | 4032 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4033 | |
f90b7a5a PB |
4034 | (define_expand "cstoretf4" |
4035 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4036 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4037 | [(match_operand:TF 2 "gr_register_operand" "") | |
4038 | (match_operand:TF 3 "gr_register_operand" "")]))] | |
4039 | "TARGET_HPUX" | |
4040 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") | |
e57b9d65 | 4041 | |
c65ebc55 JW |
4042 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
4043 | ;; efficient than mov/mov/cst/cst. | |
4044 | ||
0551c32d RH |
4045 | (define_insn_and_split "*sne_internal" |
4046 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4047 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4048 | (const_int 0)))] |
4049 | "" | |
4050 | "#" | |
c65ebc55 | 4051 | "reload_completed" |
f2f90c63 RH |
4052 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4053 | (set (match_dup 0) (const_int 1))) | |
4054 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4055 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 4056 | "" |
52e12ad0 | 4057 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4058 | |
0551c32d RH |
4059 | (define_insn_and_split "*seq_internal" |
4060 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4061 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4062 | (const_int 0)))] |
4063 | "" | |
4064 | "#" | |
c65ebc55 | 4065 | "reload_completed" |
f2f90c63 RH |
4066 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4067 | (set (match_dup 0) (const_int 0))) | |
4068 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4069 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 4070 | "" |
52e12ad0 | 4071 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4072 | \f |
4073 | ;; :::::::::::::::::::: | |
4074 | ;; :: | |
4075 | ;; :: Conditional move instructions. | |
4076 | ;; :: | |
4077 | ;; :::::::::::::::::::: | |
4078 | ||
4079 | ;; ??? Add movXXcc patterns? | |
4080 | ||
c65ebc55 JW |
4081 | ;; |
4082 | ;; DImode if_then_else patterns. | |
4083 | ;; | |
4084 | ||
75cdbeb8 | 4085 | (define_insn "*cmovdi_internal" |
f2f90c63 | 4086 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 4087 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 4088 | (if_then_else:DI |
f2f90c63 RH |
4089 | (match_operator 4 "predicate_operator" |
4090 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 4091 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 4092 | (const_int 0)]) |
f2f90c63 | 4093 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 4094 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 4095 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 4096 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 4097 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4098 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 4099 | { gcc_unreachable (); } |
75cdbeb8 RH |
4100 | [(set_attr "predicable" "no")]) |
4101 | ||
4102 | (define_split | |
f2f90c63 | 4103 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 4104 | (if_then_else |
f2f90c63 RH |
4105 | (match_operator 4 "predicate_operator" |
4106 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 4107 | (const_int 0)]) |
f2f90c63 RH |
4108 | (match_operand 2 "move_operand" "") |
4109 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
4110 | "reload_completed" |
4111 | [(const_int 0)] | |
e5bde68a | 4112 | { |
21515593 RH |
4113 | bool emitted_something = false; |
4114 | rtx dest = operands[0]; | |
4115 | rtx srct = operands[2]; | |
4116 | rtx srcf = operands[3]; | |
4117 | rtx cond = operands[4]; | |
2f937369 | 4118 | |
21515593 | 4119 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 4120 | { |
21515593 RH |
4121 | ia64_emit_cond_move (dest, srct, cond); |
4122 | emitted_something = true; | |
e5bde68a | 4123 | } |
21515593 | 4124 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 4125 | { |
21515593 RH |
4126 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
4127 | VOIDmode, operands[1], const0_rtx); | |
4128 | ia64_emit_cond_move (dest, srcf, cond); | |
4129 | emitted_something = true; | |
3b572406 | 4130 | } |
2f937369 | 4131 | if (! emitted_something) |
f9974026 | 4132 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 4133 | DONE; |
1d5d7a21 | 4134 | }) |
c65ebc55 JW |
4135 | |
4136 | ;; Absolute value pattern. | |
4137 | ||
4138 | (define_insn "*absdi2_internal" | |
0551c32d | 4139 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4140 | (if_then_else:DI |
f2f90c63 RH |
4141 | (match_operator 4 "predicate_operator" |
4142 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4143 | (const_int 0)]) |
0551c32d RH |
4144 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
4145 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4146 | "" |
e5bde68a | 4147 | "#" |
52e12ad0 | 4148 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4149 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4150 | |
4151 | (define_split | |
4152 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 4153 | (if_then_else:DI |
f2f90c63 RH |
4154 | (match_operator 4 "predicate_operator" |
4155 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4156 | (const_int 0)]) |
0551c32d RH |
4157 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4158 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4159 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4160 | [(cond_exec | |
4161 | (match_dup 4) | |
4162 | (set (match_dup 0) | |
4163 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
4164 | "") |
4165 | ||
e5bde68a RH |
4166 | (define_split |
4167 | [(set (match_operand:DI 0 "register_operand" "") | |
4168 | (if_then_else:DI | |
f2f90c63 RH |
4169 | (match_operator 4 "predicate_operator" |
4170 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4171 | (const_int 0)]) |
0551c32d RH |
4172 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4173 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4174 | "reload_completed" |
4175 | [(cond_exec | |
4176 | (match_dup 4) | |
4177 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
4178 | (cond_exec | |
4179 | (match_dup 5) | |
4180 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4181 | { |
4182 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4183 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4184 | }) |
c65ebc55 JW |
4185 | |
4186 | ;; | |
4187 | ;; SImode if_then_else patterns. | |
4188 | ;; | |
4189 | ||
75cdbeb8 | 4190 | (define_insn "*cmovsi_internal" |
f2f90c63 | 4191 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 4192 | (if_then_else:SI |
f2f90c63 RH |
4193 | (match_operator 4 "predicate_operator" |
4194 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 4195 | (const_int 0)]) |
f2f90c63 | 4196 | (match_operand:SI 2 "move_operand" |
3b572406 | 4197 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 4198 | (match_operand:SI 3 "move_operand" |
3b572406 | 4199 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 4200 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4201 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 4202 | { gcc_unreachable (); } |
3b572406 | 4203 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
4204 | |
4205 | (define_insn "*abssi2_internal" | |
0551c32d | 4206 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4207 | (if_then_else:SI |
f2f90c63 RH |
4208 | (match_operator 4 "predicate_operator" |
4209 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4210 | (const_int 0)]) |
0551c32d RH |
4211 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
4212 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4213 | "" |
e5bde68a | 4214 | "#" |
52e12ad0 | 4215 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4216 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4217 | |
4218 | (define_split | |
4219 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 4220 | (if_then_else:SI |
f2f90c63 RH |
4221 | (match_operator 4 "predicate_operator" |
4222 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4223 | (const_int 0)]) |
0551c32d RH |
4224 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4225 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4226 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4227 | [(cond_exec | |
4228 | (match_dup 4) | |
4229 | (set (match_dup 0) | |
4230 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
4231 | "") |
4232 | ||
e5bde68a RH |
4233 | (define_split |
4234 | [(set (match_operand:SI 0 "register_operand" "") | |
4235 | (if_then_else:SI | |
f2f90c63 RH |
4236 | (match_operator 4 "predicate_operator" |
4237 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4238 | (const_int 0)]) |
0551c32d RH |
4239 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4240 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4241 | "reload_completed" |
4242 | [(cond_exec | |
4243 | (match_dup 4) | |
4244 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
4245 | (cond_exec | |
4246 | (match_dup 5) | |
4247 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4248 | { |
4249 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4250 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4251 | }) |
e5bde68a | 4252 | |
7dcc803e | 4253 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
4254 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4255 | (match_operator:SI 5 "condop_operator" | |
4256 | [(if_then_else:SI | |
4257 | (match_operator 6 "predicate_operator" | |
4258 | [(match_operand:BI 1 "register_operand" "c") | |
4259 | (const_int 0)]) | |
4260 | (match_operand:SI 2 "gr_register_operand" "r") | |
4261 | (match_operand:SI 3 "gr_register_operand" "r")) | |
4262 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
4263 | "" | |
4264 | "#" | |
acb0638d BS |
4265 | "reload_completed" |
4266 | [(cond_exec | |
4267 | (match_dup 6) | |
4268 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
4269 | (cond_exec | |
4270 | (match_dup 7) | |
4271 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
4272 | { |
4273 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4274 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4275 | } |
7dcc803e BS |
4276 | [(set_attr "itanium_class" "ialu") |
4277 | (set_attr "predicable" "no")]) | |
4278 | ||
acb0638d | 4279 | |
7dcc803e | 4280 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
4281 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4282 | (match_operator:SI 5 "condop_operator" | |
4283 | [(match_operand:SI 4 "gr_register_operand" "r") | |
4284 | (if_then_else:SI | |
4285 | (match_operator 6 "predicate_operator" | |
4286 | [(match_operand:BI 1 "register_operand" "c") | |
4287 | (const_int 0)]) | |
4288 | (match_operand:SI 2 "gr_register_operand" "r") | |
4289 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
4290 | "" | |
4291 | "#" | |
acb0638d BS |
4292 | "reload_completed" |
4293 | [(cond_exec | |
4294 | (match_dup 6) | |
4295 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
4296 | (cond_exec | |
4297 | (match_dup 7) | |
4298 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
4299 | { |
4300 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4301 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4302 | } |
7dcc803e BS |
4303 | [(set_attr "itanium_class" "ialu") |
4304 | (set_attr "predicable" "no")]) | |
acb0638d | 4305 | |
c65ebc55 JW |
4306 | \f |
4307 | ;; :::::::::::::::::::: | |
4308 | ;; :: | |
4309 | ;; :: Call and branch instructions | |
4310 | ;; :: | |
4311 | ;; :::::::::::::::::::: | |
4312 | ||
4313 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
4314 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
4315 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
4316 | ;; registers used as operands. | |
4317 | ||
4318 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
4319 | ;; is supplied for the sake of some RISC machines which need to put this | |
4320 | ;; information into the assembler code; they can put it in the RTL instead of | |
4321 | ;; operand 1. | |
4322 | ||
4323 | (define_expand "call" | |
4324 | [(use (match_operand:DI 0 "" "")) | |
4325 | (use (match_operand 1 "" "")) | |
4326 | (use (match_operand 2 "" "")) | |
4327 | (use (match_operand 3 "" ""))] | |
4328 | "" | |
c65ebc55 | 4329 | { |
599aedd9 | 4330 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 4331 | DONE; |
1d5d7a21 | 4332 | }) |
c65ebc55 | 4333 | |
2ed4af6f RH |
4334 | (define_expand "sibcall" |
4335 | [(use (match_operand:DI 0 "" "")) | |
4336 | (use (match_operand 1 "" "")) | |
4337 | (use (match_operand 2 "" "")) | |
4338 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 4339 | "" |
c65ebc55 | 4340 | { |
599aedd9 | 4341 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 4342 | DONE; |
1d5d7a21 | 4343 | }) |
c65ebc55 | 4344 | |
c65ebc55 | 4345 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
4346 | ;; register in which the value is returned. There are three more operands, |
4347 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 4348 | ;; increased by one). |
2ed4af6f | 4349 | ;; |
c65ebc55 JW |
4350 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
4351 | ||
4352 | (define_expand "call_value" | |
4353 | [(use (match_operand 0 "" "")) | |
4354 | (use (match_operand:DI 1 "" "")) | |
4355 | (use (match_operand 2 "" "")) | |
4356 | (use (match_operand 3 "" "")) | |
4357 | (use (match_operand 4 "" ""))] | |
4358 | "" | |
c65ebc55 | 4359 | { |
599aedd9 | 4360 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 4361 | DONE; |
1d5d7a21 | 4362 | }) |
c65ebc55 | 4363 | |
2ed4af6f RH |
4364 | (define_expand "sibcall_value" |
4365 | [(use (match_operand 0 "" "")) | |
4366 | (use (match_operand:DI 1 "" "")) | |
4367 | (use (match_operand 2 "" "")) | |
4368 | (use (match_operand 3 "" "")) | |
4369 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 4370 | "" |
c65ebc55 | 4371 | { |
599aedd9 | 4372 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 4373 | DONE; |
1d5d7a21 | 4374 | }) |
c65ebc55 | 4375 | |
c65ebc55 JW |
4376 | ;; Call subroutine returning any type. |
4377 | ||
4378 | (define_expand "untyped_call" | |
4379 | [(parallel [(call (match_operand 0 "" "") | |
4380 | (const_int 0)) | |
4381 | (match_operand 1 "" "") | |
4382 | (match_operand 2 "" "")])] | |
4383 | "" | |
c65ebc55 JW |
4384 | { |
4385 | int i; | |
4386 | ||
4387 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
4388 | ||
4389 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
4390 | { | |
4391 | rtx set = XVECEXP (operands[2], 0, i); | |
4392 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
4393 | } | |
4394 | ||
4395 | /* The optimizer does not know that the call sets the function value | |
4396 | registers we stored in the result block. We avoid problems by | |
4397 | claiming that all hard registers are used and clobbered at this | |
4398 | point. */ | |
4399 | emit_insn (gen_blockage ()); | |
4400 | ||
4401 | DONE; | |
1d5d7a21 | 4402 | }) |
c65ebc55 | 4403 | |
599aedd9 RH |
4404 | (define_insn "call_nogp" |
4405 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
4406 | (const_int 0)) | |
4407 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 4408 | "" |
599aedd9 | 4409 | "br.call%+.many %1 = %0" |
52e12ad0 | 4410 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4411 | |
599aedd9 | 4412 | (define_insn "call_value_nogp" |
75293ad6 | 4413 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
4414 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i")) |
4415 | (const_int 0))) | |
4416 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 4417 | "" |
599aedd9 | 4418 | "br.call%+.many %2 = %1" |
52e12ad0 | 4419 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4420 | |
599aedd9 RH |
4421 | (define_insn "sibcall_nogp" |
4422 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
4423 | (const_int 0))] | |
2ed4af6f RH |
4424 | "" |
4425 | "br%+.many %0" | |
52e12ad0 | 4426 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4427 | |
599aedd9 | 4428 | (define_insn "call_gp" |
c8083186 | 4429 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) |
599aedd9 RH |
4430 | (const_int 1)) |
4431 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
4432 | (clobber (match_scratch:DI 2 "=&r,X")) | |
4433 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 4434 | "" |
599aedd9 | 4435 | "#" |
52e12ad0 | 4436 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4437 | |
599aedd9 RH |
4438 | ;; Irritatingly, we don't have access to INSN within the split body. |
4439 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
4440 | (define_split | |
4441 | [(call (mem (match_operand 0 "call_operand" "")) | |
4442 | (const_int 1)) | |
4443 | (clobber (match_operand:DI 1 "register_operand" "")) | |
4444 | (clobber (match_scratch:DI 2 "")) | |
4445 | (clobber (match_scratch:DI 3 ""))] | |
4446 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
4447 | [(const_int 0)] | |
4448 | { | |
4449 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
4450 | operands[3], true, false); | |
4451 | DONE; | |
4452 | }) | |
4453 | ||
4454 | (define_split | |
4455 | [(call (mem (match_operand 0 "call_operand" "")) | |
4456 | (const_int 1)) | |
4457 | (clobber (match_operand:DI 1 "register_operand" "")) | |
4458 | (clobber (match_scratch:DI 2 "")) | |
4459 | (clobber (match_scratch:DI 3 ""))] | |
4460 | "reload_completed" | |
4461 | [(const_int 0)] | |
4462 | { | |
4463 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
4464 | operands[3], false, false); | |
4465 | DONE; | |
4466 | }) | |
4467 | ||
4468 | (define_insn "call_value_gp" | |
75293ad6 | 4469 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
4470 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i")) |
4471 | (const_int 1))) | |
4472 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
4473 | (clobber (match_scratch:DI 3 "=&r,X")) | |
4474 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 4475 | "" |
599aedd9 | 4476 | "#" |
52e12ad0 | 4477 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4478 | |
599aedd9 RH |
4479 | (define_split |
4480 | [(set (match_operand 0 "" "") | |
4481 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
4482 | (const_int 1))) | |
4483 | (clobber (match_operand:DI 2 "register_operand" "")) | |
4484 | (clobber (match_scratch:DI 3 "")) | |
4485 | (clobber (match_scratch:DI 4 ""))] | |
4486 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
4487 | [(const_int 0)] | |
4488 | { | |
4489 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
4490 | operands[4], true, false); | |
4491 | DONE; | |
4492 | }) | |
4493 | ||
4494 | (define_split | |
4495 | [(set (match_operand 0 "" "") | |
4496 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
4497 | (const_int 1))) | |
4498 | (clobber (match_operand:DI 2 "register_operand" "")) | |
4499 | (clobber (match_scratch:DI 3 "")) | |
4500 | (clobber (match_scratch:DI 4 ""))] | |
4501 | "reload_completed" | |
4502 | [(const_int 0)] | |
4503 | { | |
4504 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
4505 | operands[4], false, false); | |
4506 | DONE; | |
4507 | }) | |
4508 | ||
4509 | (define_insn_and_split "sibcall_gp" | |
4510 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) | |
4511 | (const_int 1)) | |
4512 | (clobber (match_scratch:DI 1 "=&r,X")) | |
4513 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 4514 | "" |
599aedd9 RH |
4515 | "#" |
4516 | "reload_completed" | |
4517 | [(const_int 0)] | |
4518 | { | |
4519 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
4520 | operands[2], true, true); | |
4521 | DONE; | |
4522 | } | |
52e12ad0 | 4523 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 4524 | |
c65ebc55 JW |
4525 | (define_insn "return_internal" |
4526 | [(return) | |
4527 | (use (match_operand:DI 0 "register_operand" "b"))] | |
4528 | "" | |
4529 | "br.ret.sptk.many %0" | |
52e12ad0 | 4530 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4531 | |
4532 | (define_insn "return" | |
4533 | [(return)] | |
4534 | "ia64_direct_return ()" | |
4535 | "br.ret.sptk.many rp" | |
52e12ad0 | 4536 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 4537 | |
6b6c1201 | 4538 | (define_insn "*return_true" |
c65ebc55 | 4539 | [(set (pc) |
6b6c1201 | 4540 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4541 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4542 | (const_int 0)]) |
c65ebc55 JW |
4543 | (return) |
4544 | (pc)))] | |
4545 | "ia64_direct_return ()" | |
13da91fd | 4546 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 4547 | [(set_attr "itanium_class" "br") |
e5bde68a | 4548 | (set_attr "predicable" "no")]) |
c65ebc55 | 4549 | |
6b6c1201 | 4550 | (define_insn "*return_false" |
c65ebc55 | 4551 | [(set (pc) |
6b6c1201 | 4552 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4553 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4554 | (const_int 0)]) |
c65ebc55 JW |
4555 | (pc) |
4556 | (return)))] | |
4557 | "ia64_direct_return ()" | |
13da91fd | 4558 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 4559 | [(set_attr "itanium_class" "br") |
e5bde68a | 4560 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4561 | |
4562 | (define_insn "jump" | |
4563 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
4564 | "" | |
4565 | "br %l0" | |
52e12ad0 | 4566 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4567 | |
4568 | (define_insn "indirect_jump" | |
4569 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
4570 | "" | |
4571 | "br %0" | |
52e12ad0 | 4572 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4573 | |
4574 | (define_expand "tablejump" | |
340f7e7c RH |
4575 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
4576 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 4577 | "" |
c65ebc55 | 4578 | { |
340f7e7c RH |
4579 | rtx op0 = operands[0]; |
4580 | rtx addr; | |
4581 | ||
4582 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
4583 | element into a register without bothering to see whether that | |
4584 | is necessary given the operand predicate. Check for MEM just | |
4585 | in case someone fixes this. */ | |
4586 | if (GET_CODE (op0) == MEM) | |
4587 | addr = XEXP (op0, 0); | |
4588 | else | |
4589 | { | |
4590 | /* Otherwise, cheat and guess that the previous insn in the | |
4591 | stream was the memory load. Grab the address from that. | |
4592 | Note we have to momentarily pop out of the sequence started | |
4593 | by the insn-emit wrapper in order to grab the last insn. */ | |
4594 | rtx last, set; | |
4595 | ||
4596 | end_sequence (); | |
4597 | last = get_last_insn (); | |
4598 | start_sequence (); | |
4599 | set = single_set (last); | |
4600 | ||
e820471b NS |
4601 | gcc_assert (rtx_equal_p (SET_DEST (set), op0) |
4602 | && GET_CODE (SET_SRC (set)) == MEM); | |
340f7e7c | 4603 | addr = XEXP (SET_SRC (set), 0); |
e820471b | 4604 | gcc_assert (!rtx_equal_p (addr, op0)); |
340f7e7c | 4605 | } |
c65ebc55 | 4606 | |
340f7e7c RH |
4607 | /* Jump table elements are stored pc-relative. That is, a displacement |
4608 | from the entry to the label. Thus to convert to an absolute address | |
4609 | we add the address of the memory from which the value is loaded. */ | |
4610 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
4611 | NULL_RTX, 1, OPTAB_DIRECT); | |
4612 | }) | |
c65ebc55 | 4613 | |
340f7e7c | 4614 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
4615 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
4616 | (use (label_ref (match_operand 1 "" "")))] | |
4617 | "" | |
4618 | "br %0" | |
52e12ad0 | 4619 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4620 | |
4621 | \f | |
4622 | ;; :::::::::::::::::::: | |
4623 | ;; :: | |
4624 | ;; :: Prologue and Epilogue instructions | |
4625 | ;; :: | |
4626 | ;; :::::::::::::::::::: | |
4627 | ||
4628 | (define_expand "prologue" | |
4629 | [(const_int 1)] | |
4630 | "" | |
c65ebc55 JW |
4631 | { |
4632 | ia64_expand_prologue (); | |
4633 | DONE; | |
1d5d7a21 | 4634 | }) |
c65ebc55 JW |
4635 | |
4636 | (define_expand "epilogue" | |
2ed4af6f RH |
4637 | [(return)] |
4638 | "" | |
2ed4af6f RH |
4639 | { |
4640 | ia64_expand_epilogue (0); | |
4641 | DONE; | |
1d5d7a21 | 4642 | }) |
2ed4af6f RH |
4643 | |
4644 | (define_expand "sibcall_epilogue" | |
4645 | [(return)] | |
c65ebc55 | 4646 | "" |
c65ebc55 | 4647 | { |
2ed4af6f | 4648 | ia64_expand_epilogue (1); |
c65ebc55 | 4649 | DONE; |
1d5d7a21 | 4650 | }) |
c65ebc55 JW |
4651 | |
4652 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
4653 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
4654 | ||
4655 | (define_insn "prologue_allocate_stack" | |
4656 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
4657 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 4658 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 4659 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
4660 | (match_dup 3))] |
4661 | "" | |
4662 | "@ | |
1d5d7a21 RH |
4663 | add %0 = %1, %2 |
4664 | adds %0 = %2, %1 | |
4665 | addl %0 = %2, %1" | |
52e12ad0 | 4666 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4667 | |
4668 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
4669 | ;; stack accesses. This is similar to movdi plus the extra set. | |
4670 | ||
4671 | (define_insn "epilogue_deallocate_stack" | |
4672 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4673 | (match_operand:DI 1 "register_operand" "+r")) | |
4674 | (set (match_dup 1) (match_dup 1))] | |
4675 | "" | |
4676 | "mov %0 = %1" | |
52e12ad0 | 4677 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 4678 | |
1d5d7a21 RH |
4679 | ;; As USE insns aren't meaningful after reload, this is used instead |
4680 | ;; to prevent deleting instructions setting registers for EH handling | |
4681 | (define_insn "prologue_use" | |
4682 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
4683 | UNSPEC_PROLOGUE_USE)] | |
4684 | "" | |
4685 | "" | |
4686 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
4687 | (set_attr "predicable" "no") |
4688 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 4689 | |
c65ebc55 JW |
4690 | ;; Allocate a new register frame. |
4691 | ||
4692 | (define_insn "alloc" | |
4693 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 4694 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
4695 | (use (match_operand:DI 1 "const_int_operand" "i")) |
4696 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
4697 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
4698 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
4699 | "" | |
4700 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 4701 | [(set_attr "itanium_class" "syst_m0") |
68e11b42 JW |
4702 | (set_attr "predicable" "no") |
4703 | (set_attr "first_insn" "yes")]) | |
c65ebc55 | 4704 | |
97e242b0 RH |
4705 | ;; Modifies ar.unat |
4706 | (define_expand "gr_spill" | |
870f9ec0 RH |
4707 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
4708 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
4709 | (match_operand:DI 2 "const_int_operand" "")] |
4710 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 4711 | (clobber (match_dup 3))])] |
97e242b0 | 4712 | "" |
870f9ec0 | 4713 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4714 | |
870f9ec0 | 4715 | (define_insn "gr_spill_internal" |
b6fb7d46 | 4716 | [(set (match_operand:DI 0 "destination_operand" "=m") |
870f9ec0 | 4717 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
4718 | (match_operand:DI 2 "const_int_operand" "")] |
4719 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 4720 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 4721 | "" |
2130b7fb | 4722 | { |
1d5d7a21 RH |
4723 | /* Note that we use a C output pattern here to avoid the predicate |
4724 | being automatically added before the .mem.offset directive. */ | |
4725 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
4726 | } | |
52e12ad0 | 4727 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 4728 | |
97e242b0 RH |
4729 | ;; Reads ar.unat |
4730 | (define_expand "gr_restore" | |
870f9ec0 RH |
4731 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
4732 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
4733 | (match_operand:DI 2 "const_int_operand" "")] |
4734 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 4735 | (use (match_dup 3))])] |
97e242b0 | 4736 | "" |
870f9ec0 | 4737 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4738 | |
870f9ec0 | 4739 | (define_insn "gr_restore_internal" |
c65ebc55 | 4740 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 4741 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
4742 | (match_operand:DI 2 "const_int_operand" "")] |
4743 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 4744 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 4745 | "" |
1d5d7a21 | 4746 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 4747 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
4748 | |
4749 | (define_insn "fr_spill" | |
b6fb7d46 | 4750 | [(set (match_operand:XF 0 "destination_operand" "=m") |
02befdf4 | 4751 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] |
086c0f96 | 4752 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
4753 | "" |
4754 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 4755 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
4756 | |
4757 | (define_insn "fr_restore" | |
02befdf4 ZW |
4758 | [(set (match_operand:XF 0 "register_operand" "=f") |
4759 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 4760 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
4761 | "" |
4762 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 4763 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 4764 | |
0024a804 JW |
4765 | ;; ??? The explicit stop is not ideal. It would be better if |
4766 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4767 | ;; fixed later. This avoids an RSE DV. | |
4768 | ||
0c96007e AM |
4769 | (define_insn "bsp_value" |
4770 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 4771 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 4772 | "" |
582d11e6 JW |
4773 | "* |
4774 | { | |
4775 | return \";;\;%,mov %0 = ar.bsp\"; | |
4776 | }" | |
52e12ad0 | 4777 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
4778 | |
4779 | (define_insn "set_bsp" | |
086c0f96 RH |
4780 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
4781 | UNSPECV_SET_BSP)] | |
0c96007e | 4782 | "" |
1d5d7a21 RH |
4783 | "flushrs |
4784 | mov r19=ar.rsc | |
4785 | ;; | |
4786 | and r19=0x1c,r19 | |
4787 | ;; | |
4788 | mov ar.rsc=r19 | |
4789 | ;; | |
4790 | mov ar.bspstore=%0 | |
4791 | ;; | |
4792 | or r19=0x3,r19 | |
4793 | ;; | |
4794 | loadrs | |
4795 | invala | |
4796 | ;; | |
4797 | mov ar.rsc=r19" | |
52e12ad0 | 4798 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 4799 | (set_attr "predicable" "no")]) |
ce152ef8 | 4800 | |
0024a804 JW |
4801 | ;; ??? The explicit stops are not ideal. It would be better if |
4802 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4803 | ;; fixed later. This avoids an RSE DV. | |
4804 | ||
ce152ef8 | 4805 | (define_insn "flushrs" |
086c0f96 | 4806 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 4807 | "" |
0024a804 | 4808 | ";;\;flushrs\;;;" |
582d11e6 JW |
4809 | [(set_attr "itanium_class" "rse_m") |
4810 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
4811 | \f |
4812 | ;; :::::::::::::::::::: | |
4813 | ;; :: | |
4814 | ;; :: Miscellaneous instructions | |
4815 | ;; :: | |
4816 | ;; :::::::::::::::::::: | |
4817 | ||
839a4992 | 4818 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
4819 | ;; be emitting ";;" to force a break in the instruction packing. |
4820 | ||
4821 | ;; No operation, needed in case the user uses -g but not -O. | |
4822 | (define_insn "nop" | |
4823 | [(const_int 0)] | |
4824 | "" | |
4825 | "nop 0" | |
30028c85 | 4826 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 4827 | |
2130b7fb BS |
4828 | (define_insn "nop_m" |
4829 | [(const_int 1)] | |
4830 | "" | |
4831 | "nop.m 0" | |
4832 | [(set_attr "itanium_class" "nop_m")]) | |
4833 | ||
4834 | (define_insn "nop_i" | |
4835 | [(const_int 2)] | |
4836 | "" | |
4837 | "nop.i 0" | |
4838 | [(set_attr "itanium_class" "nop_i")]) | |
4839 | ||
4840 | (define_insn "nop_f" | |
4841 | [(const_int 3)] | |
4842 | "" | |
4843 | "nop.f 0" | |
4844 | [(set_attr "itanium_class" "nop_f")]) | |
4845 | ||
4846 | (define_insn "nop_b" | |
4847 | [(const_int 4)] | |
4848 | "" | |
4849 | "nop.b 0" | |
4850 | [(set_attr "itanium_class" "nop_b")]) | |
4851 | ||
4852 | (define_insn "nop_x" | |
4853 | [(const_int 5)] | |
4854 | "" | |
4855 | "" | |
fa978426 AS |
4856 | [(set_attr "itanium_class" "nop_x") |
4857 | (set_attr "empty" "yes")]) | |
2130b7fb | 4858 | |
30028c85 VM |
4859 | ;; The following insn will be never generated. It is used only by |
4860 | ;; insn scheduler to change state before advancing cycle. | |
4861 | (define_insn "pre_cycle" | |
4862 | [(const_int 6)] | |
4863 | "" | |
4864 | "" | |
4865 | [(set_attr "itanium_class" "pre_cycle")]) | |
4866 | ||
2130b7fb | 4867 | (define_insn "bundle_selector" |
086c0f96 | 4868 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 4869 | "" |
1d5d7a21 | 4870 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
4871 | [(set_attr "itanium_class" "ignore") |
4872 | (set_attr "predicable" "no")]) | |
4873 | ||
c65ebc55 JW |
4874 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
4875 | ;; point. | |
4876 | (define_insn "blockage" | |
086c0f96 | 4877 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
4878 | "" |
4879 | "" | |
52e12ad0 | 4880 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 4881 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4882 | |
4883 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
4884 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
4885 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
4886 | "" |
4887 | ";;" | |
52e12ad0 | 4888 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
4889 | (set_attr "predicable" "no") |
4890 | (set_attr "empty" "yes")]) | |
c65ebc55 | 4891 | |
26406018 RH |
4892 | (define_expand "trap" |
4893 | [(trap_if (const_int 1) (const_int 0))] | |
4894 | "" | |
4895 | "") | |
4896 | ||
4897 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
4898 | ;; produces worse code that setting the slot type to A. | |
4899 | ||
4900 | (define_insn "*trap" | |
4901 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
4902 | "" | |
4903 | "break %0" | |
048d0d36 | 4904 | [(set_attr "itanium_class" "chk_s_i")]) |
26406018 | 4905 | |
f90b7a5a PB |
4906 | (define_expand "ctrapbi4" |
4907 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4908 | [(match_operand:BI 1 "register_operand" "") | |
4909 | (match_operand:BI 2 "const_int_operand" "")]) | |
4910 | (match_operand 3 "" ""))] | |
26406018 | 4911 | "" |
f90b7a5a PB |
4912 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
4913 | ||
4914 | (define_expand "ctrapsi4" | |
4915 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4916 | [(match_operand:SI 1 "gr_register_operand" "") | |
4917 | (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
4918 | (match_operand 3 "" ""))] | |
4919 | "" | |
4920 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4921 | ||
4922 | (define_expand "ctrapdi4" | |
4923 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4924 | [(match_operand:DI 1 "gr_register_operand" "") | |
4925 | (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
4926 | (match_operand 3 "" ""))] | |
4927 | "" | |
4928 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4929 | ||
4930 | (define_expand "ctrapsf4" | |
4931 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4932 | [(match_operand:SF 1 "fr_reg_or_fp01_operand" "") | |
4933 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "")]) | |
4934 | (match_operand 3 "" ""))] | |
4935 | "" | |
4936 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4937 | ||
4938 | (define_expand "ctrapdf4" | |
4939 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4940 | [(match_operand:DF 1 "fr_reg_or_fp01_operand" "") | |
4941 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "")]) | |
4942 | (match_operand 3 "" ""))] | |
4943 | "" | |
4944 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4945 | ||
4946 | (define_expand "ctrapxf4" | |
4947 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4948 | [(match_operand:XF 1 "xfreg_or_fp01_operand" "") | |
4949 | (match_operand:XF 2 "xfreg_or_fp01_operand" "")]) | |
4950 | (match_operand 3 "" ""))] | |
4951 | "" | |
4952 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4953 | ||
4954 | (define_expand "ctraptf4" | |
4955 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4956 | [(match_operand:TF 1 "gr_register_operand" "") | |
4957 | (match_operand:TF 2 "gr_register_operand" "")]) | |
4958 | (match_operand 3 "" ""))] | |
4959 | "TARGET_HPUX" | |
4960 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4961 | ||
26406018 RH |
4962 | |
4963 | (define_insn "*conditional_trap" | |
4964 | [(trap_if (match_operator 0 "predicate_operator" | |
4965 | [(match_operand:BI 1 "register_operand" "c") | |
4966 | (const_int 0)]) | |
4967 | (match_operand 2 "const_int_operand" ""))] | |
4968 | "" | |
5cf63e3f | 4969 | "(%J0) break %2" |
048d0d36 | 4970 | [(set_attr "itanium_class" "chk_s_i") |
26406018 RH |
4971 | (set_attr "predicable" "no")]) |
4972 | ||
f12f25a7 | 4973 | (define_insn "break_f" |
086c0f96 | 4974 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
4975 | "" |
4976 | "break.f 0" | |
4977 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
4978 | |
4979 | (define_insn "prefetch" | |
4980 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
4981 | (match_operand:DI 1 "const_int_operand" "n") | |
4982 | (match_operand:DI 2 "const_int_operand" "n"))] | |
4983 | "" | |
4984 | { | |
4985 | static const char * const alt[2][4] = { | |
b3656137 | 4986 | { |
92cbea22 L |
4987 | "%,lfetch.nta [%0]", |
4988 | "%,lfetch.nt1 [%0]", | |
4989 | "%,lfetch.nt2 [%0]", | |
4990 | "%,lfetch [%0]" | |
b3656137 KG |
4991 | }, |
4992 | { | |
92cbea22 L |
4993 | "%,lfetch.excl.nta [%0]", |
4994 | "%,lfetch.excl.nt1 [%0]", | |
4995 | "%,lfetch.excl.nt2 [%0]", | |
4996 | "%,lfetch.excl [%0]" | |
b3656137 | 4997 | } |
44eca121 JJ |
4998 | }; |
4999 | int i = (INTVAL (operands[1])); | |
5000 | int j = (INTVAL (operands[2])); | |
5001 | ||
e820471b NS |
5002 | gcc_assert (i == 0 || i == 1); |
5003 | gcc_assert (j >= 0 && j <= 3); | |
44eca121 JJ |
5004 | return alt[i][j]; |
5005 | } | |
5006 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
5007 | \f |
5008 | ;; Non-local goto support. | |
5009 | ||
5010 | (define_expand "save_stack_nonlocal" | |
5011 | [(use (match_operand:OI 0 "memory_operand" "")) | |
5012 | (use (match_operand:DI 1 "register_operand" ""))] | |
5013 | "" | |
c65ebc55 JW |
5014 | { |
5015 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5016 | \"__ia64_save_stack_nonlocal\"), | |
bbbbb16a | 5017 | LCT_NORMAL, VOIDmode, 2, XEXP (operands[0], 0), Pmode, |
c65ebc55 JW |
5018 | operands[1], Pmode); |
5019 | DONE; | |
1d5d7a21 | 5020 | }) |
c65ebc55 JW |
5021 | |
5022 | (define_expand "nonlocal_goto" | |
5023 | [(use (match_operand 0 "general_operand" "")) | |
5024 | (use (match_operand 1 "general_operand" "")) | |
5025 | (use (match_operand 2 "general_operand" "")) | |
5026 | (use (match_operand 3 "general_operand" ""))] | |
5027 | "" | |
c65ebc55 | 5028 | { |
c65ebc55 | 5029 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 5030 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 5031 | operands[1], Pmode, |
c65ebc55 | 5032 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 5033 | operands[3], Pmode); |
c65ebc55 JW |
5034 | emit_barrier (); |
5035 | DONE; | |
1d5d7a21 | 5036 | }) |
c65ebc55 | 5037 | |
39a5cfa4 SE |
5038 | (define_insn_and_split "nonlocal_goto_receiver" |
5039 | [(unspec_volatile [(const_int 0)] UNSPECV_GOTO_RECEIVER)] | |
5040 | "" | |
5041 | "#" | |
5042 | "reload_completed" | |
5043 | [(const_int 0)] | |
5044 | { | |
5045 | ia64_reload_gp (); | |
5046 | DONE; | |
5047 | }) | |
5048 | ||
b39eb2f9 RH |
5049 | (define_insn_and_split "builtin_setjmp_receiver" |
5050 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 5051 | "" |
b39eb2f9 RH |
5052 | "#" |
5053 | "reload_completed" | |
5054 | [(const_int 0)] | |
97e242b0 | 5055 | { |
599aedd9 | 5056 | ia64_reload_gp (); |
c65ebc55 | 5057 | DONE; |
1d5d7a21 | 5058 | }) |
c65ebc55 | 5059 | |
0c96007e AM |
5060 | (define_expand "eh_epilogue" |
5061 | [(use (match_operand:DI 0 "register_operand" "r")) | |
5062 | (use (match_operand:DI 1 "register_operand" "r")) | |
5063 | (use (match_operand:DI 2 "register_operand" "r"))] | |
5064 | "" | |
0c96007e AM |
5065 | { |
5066 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
5067 | rtx sp = gen_rtx_REG (Pmode, 9); | |
5068 | ||
5069 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
5070 | { | |
5071 | emit_move_insn (bsp, operands[0]); | |
5072 | operands[0] = bsp; | |
5073 | } | |
5074 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
5075 | { | |
5076 | emit_move_insn (sp, operands[2]); | |
5077 | operands[2] = sp; | |
5078 | } | |
c41c1387 RS |
5079 | emit_use (sp); |
5080 | emit_use (bsp); | |
0c96007e AM |
5081 | |
5082 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
5083 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 5084 | }) |
9525c690 JW |
5085 | \f |
5086 | ;; Builtin apply support. | |
5087 | ||
5088 | (define_expand "restore_stack_nonlocal" | |
5089 | [(use (match_operand:DI 0 "register_operand" "")) | |
5090 | (use (match_operand:OI 1 "memory_operand" ""))] | |
5091 | "" | |
9525c690 JW |
5092 | { |
5093 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 5094 | "__ia64_restore_stack_nonlocal"), |
bbbbb16a | 5095 | LCT_NORMAL, VOIDmode, 1, |
9525c690 JW |
5096 | copy_to_reg (XEXP (operands[1], 0)), Pmode); |
5097 | DONE; | |
1d5d7a21 | 5098 | }) |
9525c690 | 5099 | |
e5bde68a RH |
5100 | \f |
5101 | ;; Predication. | |
5102 | ||
5103 | (define_cond_exec | |
5104 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 5105 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
5106 | (const_int 0)])] |
5107 | "" | |
5108 | "(%J0)") | |
3b572406 RH |
5109 | |
5110 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 5111 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 5112 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 5113 | "" |
054451ea | 5114 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 5115 | [(set_attr "itanium_class" "ignore") |
3b572406 | 5116 | (set_attr "predicable" "no")]) |
ca3920ad JW |
5117 | |
5118 | (define_insn "safe_across_calls_all" | |
086c0f96 | 5119 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
5120 | "" |
5121 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 5122 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5123 | (set_attr "predicable" "no")]) |
5124 | ||
5125 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 5126 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 5127 | "" |
ca3920ad | 5128 | { |
1bc7c5b6 | 5129 | emit_safe_across_calls (); |
1d5d7a21 RH |
5130 | return ""; |
5131 | } | |
52e12ad0 | 5132 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5133 | (set_attr "predicable" "no")]) |
5134 | ||
27a9b99d | 5135 | ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit |
6dd12198 SE |
5136 | ;; pointer. This is used by the HP-UX 32 bit mode. |
5137 | ||
5138 | (define_insn "ptr_extend" | |
5139 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
5140 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
5141 | UNSPEC_ADDP4))] | |
6dd12198 SE |
5142 | "" |
5143 | "addp4 %0 = 0,%1" | |
5144 | [(set_attr "itanium_class" "ialu")]) | |
5145 | ||
e206a74f SE |
5146 | ;; |
5147 | ;; Optimizations for ptr_extend | |
5148 | ||
36c216e5 | 5149 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
5150 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5151 | (unspec:DI | |
5152 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
5153 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 5154 | UNSPEC_ADDP4))] |
08744705 | 5155 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
5156 | "addp4 %0 = %2, %1" |
5157 | [(set_attr "itanium_class" "ialu")]) | |
5158 | ||
5159 | (define_insn "*ptr_extend_plus_2" | |
5160 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5161 | (unspec:DI | |
5162 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5163 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 5164 | UNSPEC_ADDP4))] |
08744705 | 5165 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
5166 | "addp4 %0 = %1, %2" |
5167 | [(set_attr "itanium_class" "ialu")]) | |
f61134e8 | 5168 | |
d26afa4f SE |
5169 | ;; |
5170 | ;; Get instruction pointer | |
5171 | ||
5172 | (define_insn "ip_value" | |
5173 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5174 | (pc))] | |
5175 | "" | |
5176 | "mov %0 = ip" | |
6107a6ae | 5177 | [(set_attr "itanium_class" "frbr")]) |
d26afa4f | 5178 | |
f61134e8 RH |
5179 | ;; Vector operations |
5180 | (include "vect.md") | |
af795c3c RH |
5181 | ;; Atomic operations |
5182 | (include "sync.md") | |
4883241c SE |
5183 | ;; New division operations |
5184 | (include "div.md") |