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Commit | Line | Data |
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c65ebc55 | 1 | ;; IA-64 Machine description template |
07acc7b3 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
c65ebc55 JW |
4 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
5 | ;; David Mosberger <davidm@hpl.hp.com>. | |
6 | ||
3bed2930 | 7 | ;; This file is part of GCC. |
c65ebc55 | 8 | |
3bed2930 | 9 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 10 | ;; it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | ;; the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
12 | ;; any later version. |
13 | ||
3bed2930 | 14 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
18 | ||
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
c65ebc55 JW |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
086c0f96 | 51 | (define_constants |
7b6e506e RH |
52 | [; Relocations |
53 | (UNSPEC_LTOFF_DTPMOD 0) | |
54 | (UNSPEC_LTOFF_DTPREL 1) | |
55 | (UNSPEC_DTPREL 2) | |
56 | (UNSPEC_LTOFF_TPREL 3) | |
57 | (UNSPEC_TPREL 4) | |
5e6c8b64 | 58 | (UNSPEC_DTPMOD 5) |
7b6e506e RH |
59 | |
60 | (UNSPEC_LD_BASE 9) | |
61 | (UNSPEC_GR_SPILL 10) | |
62 | (UNSPEC_GR_RESTORE 11) | |
63 | (UNSPEC_FR_SPILL 12) | |
64 | (UNSPEC_FR_RESTORE 13) | |
65 | (UNSPEC_FR_RECIP_APPROX 14) | |
66 | (UNSPEC_PRED_REL_MUTEX 15) | |
c407570a | 67 | (UNSPEC_GETF_EXP 16) |
7b6e506e RH |
68 | (UNSPEC_PIC_CALL 17) |
69 | (UNSPEC_MF 18) | |
70 | (UNSPEC_CMPXCHG_ACQ 19) | |
71 | (UNSPEC_FETCHADD_ACQ 20) | |
72 | (UNSPEC_BSP_VALUE 21) | |
73 | (UNSPEC_FLUSHRS 22) | |
74 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
75 | (UNSPEC_ADDP4 24) |
76 | (UNSPEC_PROLOGUE_USE 25) | |
af1e5518 | 77 | (UNSPEC_RET_ADDR 26) |
b38ba463 ZW |
78 | (UNSPEC_SETF_EXP 27) |
79 | (UNSPEC_FR_SQRT_RECIP_APPROX 28) | |
f526a3c8 | 80 | (UNSPEC_SHRP 29) |
046625fa | 81 | (UNSPEC_COPYSIGN 30) |
b4e3537b | 82 | (UNSPEC_VECT_EXTR 31) |
048d0d36 MK |
83 | (UNSPEC_LDA 40) |
84 | (UNSPEC_LDS 41) | |
388092d5 AB |
85 | (UNSPEC_LDS_A 42) |
86 | (UNSPEC_LDSA 43) | |
87 | (UNSPEC_LDCCLR 44) | |
88 | (UNSPEC_LDCNC 45) | |
89 | (UNSPEC_CHKACLR 46) | |
90 | (UNSPEC_CHKANC 47) | |
91 | (UNSPEC_CHKS 48) | |
92 | (UNSPEC_FR_RECIP_APPROX_RES 49) | |
93 | (UNSPEC_FR_SQRT_RECIP_APPROX_RES 50) | |
086c0f96 RH |
94 | ]) |
95 | ||
96 | (define_constants | |
97 | [(UNSPECV_ALLOC 0) | |
98 | (UNSPECV_BLOCKAGE 1) | |
99 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
100 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
101 | (UNSPECV_SET_BSP 4) |
102 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
103 | (UNSPECV_PSAC_NORMAL 6) | |
b39eb2f9 | 104 | (UNSPECV_SETJMP_RECEIVER 7) |
39a5cfa4 | 105 | (UNSPECV_GOTO_RECEIVER 8) |
086c0f96 | 106 | ]) |
e543e219 | 107 | |
7905f799 | 108 | (include "predicates.md") |
13f70342 | 109 | (include "constraints.md") |
c65ebc55 JW |
110 | \f |
111 | ;; :::::::::::::::::::: | |
112 | ;; :: | |
113 | ;; :: Attributes | |
114 | ;; :: | |
115 | ;; :::::::::::::::::::: | |
116 | ||
30028c85 VM |
117 | ;; Processor type. This attribute must exactly match the processor_type |
118 | ;; enumeration in ia64.h. | |
119 | (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune"))) | |
120 | ||
c65ebc55 JW |
121 | ;; Instruction type. This primarily determines how instructions can be |
122 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
123 | ||
124 | ;; A alu, can go in I or M syllable of a bundle | |
125 | ;; I integer | |
126 | ;; M memory | |
127 | ;; F floating-point | |
128 | ;; B branch | |
129 | ;; L long immediate, takes two syllables | |
130 | ;; S stop bit | |
131 | ||
132 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
133 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
134 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
135 | ;; which emit instruction that can go in any slot (e.g. nop). | |
136 | ||
1d5d7a21 | 137 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
a71aef0b | 138 | fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, |
048d0d36 | 139 | ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, |
f61134e8 RH |
140 | st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, |
141 | nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 142 | (const_string "unknown")) |
52e12ad0 | 143 | |
048d0d36 | 144 | ;; chk_s_i has an I and an M form; use type A for convenience. |
2130b7fb | 145 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" |
a71aef0b | 146 | (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") |
52e12ad0 BS |
147 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
148 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 149 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
048d0d36 MK |
150 | (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M") |
151 | (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua") | |
f61134e8 | 152 | (const_string "A") |
2130b7fb BS |
153 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") |
154 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
155 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
156 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
157 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
158 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 159 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 160 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
161 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
162 | (const_string "unknown"))) | |
c65ebc55 | 163 | |
2130b7fb BS |
164 | (define_attr "itanium_requires_unit0" "no,yes" |
165 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
166 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
167 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
168 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
169 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
170 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
171 | (const_string "no"))) | |
172 | ||
e5bde68a RH |
173 | ;; Predication. True iff this instruction can be predicated. |
174 | ||
175 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
176 | ||
fa978426 AS |
177 | ;; Empty. True iff this insn does not generate any code. |
178 | ||
179 | (define_attr "empty" "no,yes" (const_string "no")) | |
180 | ||
68e11b42 JW |
181 | ;; True iff this insn must be the first insn of an instruction group. |
182 | ;; This is true for the alloc instruction, and will also be true of others | |
183 | ;; when we have full intrinsics support. | |
184 | ||
185 | (define_attr "first_insn" "no,yes" (const_string "no")) | |
048d0d36 MK |
186 | |
187 | (define_attr "data_speculative" "no,yes" (const_string "no")) | |
188 | ||
189 | (define_attr "control_speculative" "no,yes" (const_string "no")) | |
190 | ||
191 | (define_attr "check_load" "no,yes" (const_string "no")) | |
388092d5 AB |
192 | |
193 | (define_attr "speculable1" "no,yes" (const_string "no")) | |
194 | ||
195 | (define_attr "speculable2" "no,yes" (const_string "no")) | |
c65ebc55 | 196 | \f |
30028c85 VM |
197 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
198 | ;; bundling. | |
199 | ||
200 | (automata_option "ndfa") | |
201 | ||
202 | ;; Uncomment the following line to output automata for debugging. | |
203 | ;; (automata_option "v") | |
204 | ||
205 | (automata_option "w") | |
206 | ||
30028c85 VM |
207 | (include "itanium1.md") |
208 | (include "itanium2.md") | |
209 | ||
c65ebc55 JW |
210 | \f |
211 | ;; :::::::::::::::::::: | |
212 | ;; :: | |
213 | ;; :: Moves | |
214 | ;; :: | |
215 | ;; :::::::::::::::::::: | |
216 | ||
f2f90c63 RH |
217 | ;; Set of a single predicate register. This is only used to implement |
218 | ;; pr-to-pr move and complement. | |
219 | ||
220 | (define_insn "*movcci" | |
221 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
222 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
223 | "" | |
224 | "@ | |
225 | cmp.ne %0, p0 = r0, r0 | |
226 | cmp.eq %0, p0 = r0, r0 | |
227 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 228 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
229 | (set_attr "predicable" "no")]) |
230 | ||
231 | (define_insn "movbi" | |
b6fb7d46 JW |
232 | [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
233 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
234 | "" |
235 | "@ | |
236 | cmp.ne %0, %I0 = r0, r0 | |
237 | cmp.eq %0, %I0 = r0, r0 | |
238 | # | |
239 | # | |
240 | tbit.nz %0, %I0 = %1, 0 | |
241 | adds %0 = %1, r0 | |
242 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
243 | st1%Q0 %0 = %1%P0 |
244 | mov %0 = %1" | |
388092d5 AB |
245 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu") |
246 | (set_attr "speculable1" "yes") | |
247 | (set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")]) | |
f2f90c63 RH |
248 | |
249 | (define_split | |
250 | [(set (match_operand:BI 0 "register_operand" "") | |
251 | (match_operand:BI 1 "register_operand" ""))] | |
252 | "reload_completed | |
253 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
254 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
255 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
256 | (set (match_dup 0) (const_int 1))) | |
257 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
258 | (set (match_dup 0) (const_int 0)))] | |
259 | "") | |
260 | ||
261 | (define_split | |
262 | [(set (match_operand:BI 0 "register_operand" "") | |
263 | (match_operand:BI 1 "register_operand" ""))] | |
264 | "reload_completed | |
265 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
266 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
267 | [(set (match_dup 2) (match_dup 4)) | |
268 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 269 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
270 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
271 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
272 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
273 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
274 | ||
c65ebc55 JW |
275 | (define_expand "movqi" |
276 | [(set (match_operand:QI 0 "general_operand" "") | |
277 | (match_operand:QI 1 "general_operand" ""))] | |
278 | "" | |
c65ebc55 | 279 | { |
7b6e506e RH |
280 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
281 | if (!op1) | |
282 | DONE; | |
283 | operands[1] = op1; | |
1d5d7a21 | 284 | }) |
c65ebc55 | 285 | |
388092d5 | 286 | (define_insn "movqi_internal" |
4b983fdc RH |
287 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
288 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 289 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 290 | "@ |
13da91fd | 291 | mov %0 = %r1 |
c65ebc55 JW |
292 | addl %0 = %1, r0 |
293 | ld1%O1 %0 = %1%P1 | |
13da91fd | 294 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 295 | getf.sig %0 = %1 |
13da91fd RH |
296 | setf.sig %0 = %r1 |
297 | mov %0 = %1" | |
388092d5 AB |
298 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
299 | (set_attr "speculable1" "yes") | |
300 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
301 | |
302 | (define_expand "movhi" | |
303 | [(set (match_operand:HI 0 "general_operand" "") | |
304 | (match_operand:HI 1 "general_operand" ""))] | |
305 | "" | |
c65ebc55 | 306 | { |
7b6e506e RH |
307 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
308 | if (!op1) | |
309 | DONE; | |
310 | operands[1] = op1; | |
1d5d7a21 | 311 | }) |
c65ebc55 | 312 | |
388092d5 | 313 | (define_insn "movhi_internal" |
4b983fdc RH |
314 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
315 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 316 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 317 | "@ |
13da91fd | 318 | mov %0 = %r1 |
c65ebc55 JW |
319 | addl %0 = %1, r0 |
320 | ld2%O1 %0 = %1%P1 | |
13da91fd | 321 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 322 | getf.sig %0 = %1 |
13da91fd RH |
323 | setf.sig %0 = %r1 |
324 | mov %0 = %1" | |
388092d5 AB |
325 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
326 | (set_attr "speculable1" "yes") | |
327 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
328 | |
329 | (define_expand "movsi" | |
330 | [(set (match_operand:SI 0 "general_operand" "") | |
331 | (match_operand:SI 1 "general_operand" ""))] | |
332 | "" | |
c65ebc55 | 333 | { |
7b6e506e RH |
334 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
335 | if (!op1) | |
336 | DONE; | |
337 | operands[1] = op1; | |
1d5d7a21 | 338 | }) |
c65ebc55 | 339 | |
388092d5 | 340 | (define_insn "movsi_internal" |
4e483a22 JB |
341 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d") |
342 | (match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))] | |
aebf2462 | 343 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 344 | "@ |
13da91fd | 345 | mov %0 = %r1 |
c65ebc55 | 346 | addl %0 = %1, r0 |
4e483a22 | 347 | addp4 %0 = %1 - 0x100000000, r0 |
c65ebc55 JW |
348 | movl %0 = %1 |
349 | ld4%O1 %0 = %1%P1 | |
13da91fd | 350 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 351 | getf.sig %0 = %1 |
13da91fd | 352 | setf.sig %0 = %r1 |
97e242b0 RH |
353 | mov %0 = %1 |
354 | mov %0 = %1 | |
355 | mov %0 = %r1" | |
1d5d7a21 | 356 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
388092d5 AB |
357 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m") |
358 | (set_attr "speculable1" "yes") | |
359 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")]) | |
c65ebc55 JW |
360 | |
361 | (define_expand "movdi" | |
362 | [(set (match_operand:DI 0 "general_operand" "") | |
363 | (match_operand:DI 1 "general_operand" ""))] | |
364 | "" | |
c65ebc55 | 365 | { |
7b6e506e RH |
366 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
367 | if (!op1) | |
368 | DONE; | |
369 | operands[1] = op1; | |
1d5d7a21 | 370 | }) |
c65ebc55 | 371 | |
388092d5 | 372 | (define_insn "movdi_internal" |
4b983fdc | 373 | [(set (match_operand:DI 0 "destination_operand" |
4e483a22 | 374 | "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 375 | (match_operand:DI 1 "move_operand" |
4e483a22 | 376 | "rO,JT,j,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 377 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
378 | { |
379 | static const char * const alt[] = { | |
1d5d7a21 RH |
380 | "%,mov %0 = %r1", |
381 | "%,addl %0 = %1, r0", | |
4e483a22 | 382 | "%,addp4 %0 = %1 - 0x100000000, r0", |
1d5d7a21 RH |
383 | "%,movl %0 = %1", |
384 | "%,ld8%O1 %0 = %1%P1", | |
385 | "%,st8%Q0 %0 = %r1%P0", | |
386 | "%,getf.sig %0 = %1", | |
387 | "%,setf.sig %0 = %r1", | |
388 | "%,mov %0 = %1", | |
389 | "%,ldf8 %0 = %1%P1", | |
390 | "%,stf8 %0 = %1%P0", | |
391 | "%,mov %0 = %1", | |
392 | "%,mov %0 = %r1", | |
393 | "%,mov %0 = %1", | |
394 | "%,mov %0 = %1", | |
395 | "%,mov %0 = %1", | |
396 | "%,mov %0 = %1", | |
397 | "mov %0 = pr", | |
398 | "mov pr = %1, -1" | |
9b7bf67d RH |
399 | }; |
400 | ||
e820471b NS |
401 | gcc_assert (which_alternative != 2 || TARGET_NO_PIC |
402 | || !symbolic_operand (operands[1], VOIDmode)); | |
9b7bf67d RH |
403 | |
404 | return alt[which_alternative]; | |
1d5d7a21 | 405 | } |
388092d5 AB |
406 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr") |
407 | (set_attr "speculable1" "yes") | |
408 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")]) | |
c65ebc55 | 409 | |
3abcb3a7 HPN |
410 | (define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI]) |
411 | (define_mode_iterator MODE_FOR_EXTEND [QI HI SI]) | |
048d0d36 MK |
412 | |
413 | (define_mode_attr output_a [ | |
414 | (BI "ld1.a %0 = %1%P1") | |
415 | (QI "ld1.a %0 = %1%P1") | |
416 | (HI "ld2.a %0 = %1%P1") | |
417 | (SI "ld4.a %0 = %1%P1") | |
418 | (DI | |
419 | "@ | |
420 | ld8.a %0 = %1%P1 | |
421 | ldf8.a %0 = %1%P1") | |
422 | (SF | |
423 | "@ | |
424 | ldfs.a %0 = %1%P1 | |
425 | ld4.a %0 = %1%P1") | |
426 | (DF | |
427 | "@ | |
428 | ldfd.a %0 = %1%P1 | |
429 | ld8.a %0 = %1%P1") | |
430 | (XF "ldfe.a %0 = %1%P1") | |
431 | (TI "ldfp8.a %X0 = %1%P1")]) | |
432 | ||
433 | (define_mode_attr output_s [ | |
434 | (BI "ld1.s %0 = %1%P1") | |
435 | (QI "ld1.s %0 = %1%P1") | |
436 | (HI "ld2.s %0 = %1%P1") | |
437 | (SI "ld4.s %0 = %1%P1") | |
438 | (DI | |
439 | "@ | |
440 | ld8.s %0 = %1%P1 | |
441 | ldf8.s %0 = %1%P1") | |
442 | (SF | |
443 | "@ | |
444 | ldfs.s %0 = %1%P1 | |
445 | ld4.s %0 = %1%P1") | |
446 | (DF | |
447 | "@ | |
448 | ldfd.s %0 = %1%P1 | |
449 | ld8.s %0 = %1%P1") | |
450 | (XF "ldfe.s %0 = %1%P1") | |
451 | (TI "ldfp8.s %X0 = %1%P1")]) | |
452 | ||
453 | (define_mode_attr output_sa [ | |
454 | (BI "ld1.sa %0 = %1%P1") | |
455 | (QI "ld1.sa %0 = %1%P1") | |
456 | (HI "ld2.sa %0 = %1%P1") | |
457 | (SI "ld4.sa %0 = %1%P1") | |
458 | (DI | |
459 | "@ | |
460 | ld8.sa %0 = %1%P1 | |
461 | ldf8.sa %0 = %1%P1") | |
462 | (SF | |
463 | "@ | |
464 | ldfs.sa %0 = %1%P1 | |
465 | ld4.sa %0 = %1%P1") | |
466 | (DF | |
467 | "@ | |
468 | ldfd.sa %0 = %1%P1 | |
469 | ld8.sa %0 = %1%P1") | |
470 | (XF "ldfe.sa %0 = %1%P1") | |
471 | (TI "ldfp8.sa %X0 = %1%P1")]) | |
472 | ||
473 | (define_mode_attr output_c_clr [ | |
474 | (BI "ld1.c.clr%O1 %0 = %1%P1") | |
475 | (QI "ld1.c.clr%O1 %0 = %1%P1") | |
476 | (HI "ld2.c.clr%O1 %0 = %1%P1") | |
477 | (SI "ld4.c.clr%O1 %0 = %1%P1") | |
478 | (DI | |
479 | "@ | |
480 | ld8.c.clr%O1 %0 = %1%P1 | |
481 | ldf8.c.clr %0 = %1%P1") | |
482 | (SF | |
483 | "@ | |
484 | ldfs.c.clr %0 = %1%P1 | |
485 | ld4.c.clr%O1 %0 = %1%P1") | |
486 | (DF | |
487 | "@ | |
488 | ldfd.c.clr %0 = %1%P1 | |
489 | ld8.c.clr%O1 %0 = %1%P1") | |
490 | (XF "ldfe.c.clr %0 = %1%P1") | |
491 | (TI "ldfp8.c.clr %X0 = %1%P1")]) | |
492 | ||
388092d5 AB |
493 | (define_mode_attr output_c_nc [ |
494 | (BI "ld1.c.nc%O1 %0 = %1%P1") | |
495 | (QI "ld1.c.nc%O1 %0 = %1%P1") | |
496 | (HI "ld2.c.nc%O1 %0 = %1%P1") | |
497 | (SI "ld4.c.nc%O1 %0 = %1%P1") | |
498 | (DI | |
499 | "@ | |
500 | ld8.c.nc%O1 %0 = %1%P1 | |
501 | ldf8.c.nc %0 = %1%P1") | |
502 | (SF | |
503 | "@ | |
504 | ldfs.c.nc %0 = %1%P1 | |
505 | ld4.c.nc%O1 %0 = %1%P1") | |
506 | (DF | |
507 | "@ | |
508 | ldfd.c.nc %0 = %1%P1 | |
509 | ld8.c.nc%O1 %0 = %1%P1") | |
510 | (XF "ldfe.c.nc %0 = %1%P1") | |
511 | (TI "ldfp8.c.nc %X0 = %1%P1")]) | |
512 | ||
048d0d36 MK |
513 | (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")]) |
514 | (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")]) | |
515 | (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")]) | |
516 | ||
517 | (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) | |
518 | ||
f6ec1d11 MK |
519 | ;; Define register predicate prefix. |
520 | ;; We can generate speculative loads only for general and fp registers - this | |
ea2c620c | 521 | ;; is constrained in ia64.c: ia64_speculate_insn (). |
048d0d36 MK |
522 | (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) |
523 | ||
524 | (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) | |
525 | (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")]) | |
526 | (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")]) | |
527 | ||
528 | (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")]) | |
529 | ||
530 | (define_insn "mov<mode>_advanced" | |
531 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
532 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))] | |
533 | "ia64_move_ok (operands[0], operands[1])" | |
534 | "<output_a>" | |
535 | [(set_attr "itanium_class" "<ld_class>") | |
536 | (set_attr "data_speculative" "<attr_yes>")]) | |
537 | ||
538 | (define_insn "zero_extend<mode>di2_advanced" | |
539 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
540 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))] | |
541 | "" | |
542 | "<output_a>" | |
543 | [(set_attr "itanium_class" "<ld_class>") | |
544 | (set_attr "data_speculative" "<attr_yes>")]) | |
545 | ||
546 | (define_insn "mov<mode>_speculative" | |
547 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
548 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))] | |
549 | "ia64_move_ok (operands[0], operands[1])" | |
550 | "<output_s>" | |
551 | [(set_attr "itanium_class" "<ld_class>") | |
552 | (set_attr "control_speculative" "<attr_yes>")]) | |
553 | ||
554 | (define_insn "zero_extend<mode>di2_speculative" | |
555 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
556 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))] | |
557 | "" | |
558 | "<output_s>" | |
559 | [(set_attr "itanium_class" "<ld_class>") | |
560 | (set_attr "control_speculative" "<attr_yes>")]) | |
561 | ||
562 | (define_insn "mov<mode>_speculative_advanced" | |
563 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
564 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))] | |
565 | "ia64_move_ok (operands[0], operands[1])" | |
566 | "<output_sa>" | |
567 | [(set_attr "itanium_class" "<ld_class>") | |
568 | (set_attr "data_speculative" "<attr_yes>") | |
569 | (set_attr "control_speculative" "<attr_yes>")]) | |
570 | ||
388092d5 AB |
571 | (define_insn "mov<mode>_speculative_a" |
572 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
573 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))] | |
574 | "ia64_move_ok (operands[0], operands[1])" | |
575 | "<output_sa>" | |
576 | [(set_attr "itanium_class" "<ld_class>") | |
577 | (set_attr "data_speculative" "<attr_yes>") | |
578 | (set_attr "control_speculative" "<attr_yes>")]) | |
579 | ||
048d0d36 MK |
580 | (define_insn "zero_extend<mode>di2_speculative_advanced" |
581 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
582 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))] | |
583 | "" | |
584 | "<output_sa>" | |
585 | [(set_attr "itanium_class" "<ld_class>") | |
586 | (set_attr "data_speculative" "<attr_yes>") | |
587 | (set_attr "control_speculative" "<attr_yes>")]) | |
588 | ||
388092d5 AB |
589 | (define_insn "zero_extend<mode>di2_speculative_a" |
590 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
591 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))] | |
592 | "" | |
593 | "<output_sa>" | |
594 | [(set_attr "itanium_class" "<ld_class>") | |
595 | (set_attr "data_speculative" "<attr_yes>") | |
596 | (set_attr "control_speculative" "<attr_yes>")]) | |
597 | ||
048d0d36 MK |
598 | (define_insn "mov<mode>_clr" |
599 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
600 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
601 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
602 | (match_dup 0)))] | |
603 | "ia64_move_ok (operands[0], operands[1])" | |
604 | "<output_c_clr>" | |
605 | [(set_attr "itanium_class" "<ld_class>") | |
606 | (set_attr "check_load" "<attr_yes>")]) | |
607 | ||
388092d5 AB |
608 | (define_insn "mov<mode>_nc" |
609 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
610 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
611 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
612 | (match_dup 0)))] | |
613 | "ia64_move_ok (operands[0], operands[1])" | |
614 | "<output_c_nc>" | |
615 | [(set_attr "itanium_class" "<ld_class>") | |
616 | (set_attr "check_load" "<attr_yes>")]) | |
617 | ||
048d0d36 MK |
618 | (define_insn "zero_extend<mode>di2_clr" |
619 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
620 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
621 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
622 | (match_dup 0)))] | |
623 | "" | |
624 | "<output_c_clr>" | |
625 | [(set_attr "itanium_class" "<ld_class>") | |
626 | (set_attr "check_load" "<attr_yes>")]) | |
627 | ||
388092d5 AB |
628 | (define_insn "zero_extend<mode>di2_nc" |
629 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
630 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
631 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
632 | (match_dup 0)))] | |
633 | "" | |
634 | "<output_c_nc>" | |
635 | [(set_attr "itanium_class" "<ld_class>") | |
636 | (set_attr "check_load" "<attr_yes>")]) | |
637 | ||
048d0d36 MK |
638 | (define_insn "advanced_load_check_clr_<mode>" |
639 | [(set (pc) | |
640 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0)) | |
641 | (pc) | |
642 | (label_ref (match_operand 1 "" ""))))] | |
643 | "" | |
644 | "chk.a.clr %0, %l1" | |
645 | [(set_attr "itanium_class" "<chka_class>")]) | |
646 | ||
388092d5 AB |
647 | (define_insn "advanced_load_check_nc_<mode>" |
648 | [(set (pc) | |
649 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0)) | |
650 | (pc) | |
651 | (label_ref (match_operand 1 "" ""))))] | |
652 | "" | |
653 | "chk.a.clr %0, %l1" | |
654 | [(set_attr "itanium_class" "<chka_class>")]) | |
655 | ||
048d0d36 MK |
656 | (define_insn "speculation_check_<mode>" |
657 | [(set (pc) | |
658 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0)) | |
659 | (pc) | |
660 | (label_ref (match_operand 1 "" ""))))] | |
661 | "" | |
662 | "chk.s %0, %l1" | |
663 | [(set_attr "itanium_class" "<chks_class>")]) | |
664 | ||
9b7bf67d | 665 | (define_split |
21515593 RH |
666 | [(set (match_operand 0 "register_operand" "") |
667 | (match_operand 1 "symbolic_operand" ""))] | |
5e6c8b64 | 668 | "reload_completed" |
9b7bf67d | 669 | [(const_int 0)] |
9b7bf67d | 670 | { |
5e6c8b64 RH |
671 | if (ia64_expand_load_address (operands[0], operands[1])) |
672 | DONE; | |
673 | else | |
674 | FAIL; | |
1d5d7a21 | 675 | }) |
9b7bf67d | 676 | |
c65ebc55 | 677 | (define_expand "load_fptr" |
5e6c8b64 RH |
678 | [(set (match_operand:DI 0 "register_operand" "") |
679 | (plus:DI (match_dup 2) (match_operand 1 "function_operand" ""))) | |
680 | (set (match_dup 0) (match_dup 3))] | |
681 | "reload_completed" | |
c65ebc55 | 682 | { |
5e6c8b64 RH |
683 | operands[2] = pic_offset_table_rtx; |
684 | operands[3] = gen_const_mem (DImode, operands[0]); | |
1d5d7a21 | 685 | }) |
c65ebc55 JW |
686 | |
687 | (define_insn "*load_fptr_internal1" | |
688 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 689 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
5e6c8b64 | 690 | "reload_completed" |
c65ebc55 | 691 | "addl %0 = @ltoff(@fptr(%1)), gp" |
52e12ad0 | 692 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
693 | |
694 | (define_insn "load_gprel" | |
695 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 696 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
5e6c8b64 | 697 | "reload_completed" |
c65ebc55 | 698 | "addl %0 = @gprel(%1), gp" |
52e12ad0 | 699 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 700 | |
5e6c8b64 | 701 | (define_insn "*gprel64_offset" |
59da9a7d JW |
702 | [(set (match_operand:DI 0 "register_operand" "=r") |
703 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
5e6c8b64 | 704 | "reload_completed" |
59da9a7d | 705 | "movl %0 = @gprel(%1)" |
52e12ad0 | 706 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
707 | |
708 | (define_expand "load_gprel64" | |
5e6c8b64 RH |
709 | [(set (match_operand:DI 0 "register_operand" "") |
710 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2))) | |
711 | (set (match_dup 0) | |
712 | (plus:DI (match_dup 2) (match_dup 0)))] | |
713 | "reload_completed" | |
ec039e3c | 714 | { |
5e6c8b64 | 715 | operands[2] = pic_offset_table_rtx; |
1d5d7a21 | 716 | }) |
59da9a7d | 717 | |
af1e5518 RH |
718 | ;; This is used as a placeholder for the return address during early |
719 | ;; compilation. We won't know where we've placed this until during | |
720 | ;; reload, at which point it can wind up in b0, a general register, | |
721 | ;; or memory. The only safe destination under these conditions is a | |
722 | ;; general register. | |
723 | ||
724 | (define_insn_and_split "*movdi_ret_addr" | |
725 | [(set (match_operand:DI 0 "register_operand" "=r") | |
726 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
727 | "" | |
728 | "#" | |
729 | "reload_completed" | |
730 | [(const_int 0)] | |
731 | { | |
732 | ia64_split_return_addr_rtx (operands[0]); | |
733 | DONE; | |
734 | } | |
735 | [(set_attr "itanium_class" "ialu")]) | |
736 | ||
ef1ecf87 | 737 | (define_insn "*load_symptr_high" |
c65ebc55 | 738 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
739 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
740 | (match_operand:DI 2 "register_operand" "a")))] | |
5e6c8b64 | 741 | "reload_completed" |
ef1ecf87 RH |
742 | { |
743 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
744 | return "%,addl %0 = @ltoffx(%1), %2"; | |
745 | else | |
746 | return "%,addl %0 = @ltoff(%1), %2"; | |
747 | } | |
52e12ad0 | 748 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 749 | |
ef1ecf87 RH |
750 | (define_insn "*load_symptr_low" |
751 | [(set (match_operand:DI 0 "register_operand" "=r") | |
752 | (lo_sum:DI (match_operand:DI 1 "register_operand" "r") | |
753 | (match_operand 2 "got_symbolic_operand" "s")))] | |
5e6c8b64 | 754 | "reload_completed" |
ef1ecf87 RH |
755 | { |
756 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
757 | return "%,ld8.mov %0 = [%1], %2"; | |
758 | else | |
759 | return "%,ld8 %0 = [%1]"; | |
760 | } | |
761 | [(set_attr "itanium_class" "ld")]) | |
762 | ||
5e6c8b64 | 763 | (define_insn_and_split "load_dtpmod" |
7b6e506e | 764 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 765 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 | 766 | UNSPEC_DTPMOD))] |
7b6e506e | 767 | "" |
5e6c8b64 RH |
768 | "#" |
769 | "reload_completed" | |
770 | [(set (match_dup 0) | |
771 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD) | |
772 | (match_dup 2))) | |
773 | (set (match_dup 0) (match_dup 3))] | |
774 | { | |
775 | operands[2] = pic_offset_table_rtx; | |
776 | operands[3] = gen_const_mem (DImode, operands[0]); | |
777 | }) | |
7b6e506e | 778 | |
5e6c8b64 | 779 | (define_insn "*load_ltoff_dtpmod" |
7b6e506e | 780 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 781 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
782 | UNSPEC_LTOFF_DTPMOD) |
783 | (match_operand:DI 2 "register_operand" "a")))] | |
784 | "reload_completed" | |
785 | "addl %0 = @ltoff(@dtpmod(%1)), %2" | |
7b6e506e RH |
786 | [(set_attr "itanium_class" "ialu")]) |
787 | ||
788 | (define_expand "load_dtprel" | |
789 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 790 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
791 | UNSPEC_DTPREL))] |
792 | "" | |
793 | "") | |
794 | ||
795 | (define_insn "*load_dtprel64" | |
796 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 797 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
798 | UNSPEC_DTPREL))] |
799 | "TARGET_TLS64" | |
800 | "movl %0 = @dtprel(%1)" | |
801 | [(set_attr "itanium_class" "long_i")]) | |
802 | ||
803 | (define_insn "*load_dtprel22" | |
804 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 805 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
806 | UNSPEC_DTPREL))] |
807 | "" | |
808 | "addl %0 = @dtprel(%1), r0" | |
809 | [(set_attr "itanium_class" "ialu")]) | |
810 | ||
5e6c8b64 RH |
811 | (define_insn_and_split "*load_dtprel_gd" |
812 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 813 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
814 | UNSPEC_DTPREL))] |
815 | "" | |
816 | "#" | |
817 | "reload_completed" | |
818 | [(set (match_dup 0) | |
819 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL) | |
820 | (match_dup 2))) | |
821 | (set (match_dup 0) (match_dup 3))] | |
822 | { | |
823 | operands[2] = pic_offset_table_rtx; | |
824 | operands[3] = gen_const_mem (DImode, operands[0]); | |
825 | }) | |
826 | ||
827 | (define_insn "*load_ltoff_dtprel" | |
828 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 829 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
830 | UNSPEC_LTOFF_DTPREL) |
831 | (match_operand:DI 2 "register_operand" "a")))] | |
832 | "" | |
833 | "addl %0 = @ltoff(@dtprel(%1)), %2" | |
834 | [(set_attr "itanium_class" "ialu")]) | |
835 | ||
7b6e506e RH |
836 | (define_expand "add_dtprel" |
837 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 838 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
839 | UNSPEC_DTPREL) |
840 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
841 | "!TARGET_TLS64" |
842 | "") | |
843 | ||
844 | (define_insn "*add_dtprel14" | |
845 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 846 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
847 | UNSPEC_DTPREL) |
848 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 849 | "TARGET_TLS14" |
5e6c8b64 | 850 | "adds %0 = @dtprel(%1), %2" |
7b6e506e RH |
851 | [(set_attr "itanium_class" "ialu")]) |
852 | ||
853 | (define_insn "*add_dtprel22" | |
854 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 855 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
856 | UNSPEC_DTPREL) |
857 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 858 | "TARGET_TLS22" |
5e6c8b64 | 859 | "addl %0 = @dtprel(%1), %2" |
7b6e506e RH |
860 | [(set_attr "itanium_class" "ialu")]) |
861 | ||
862 | (define_expand "load_tprel" | |
863 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 864 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
865 | UNSPEC_TPREL))] |
866 | "" | |
867 | "") | |
868 | ||
869 | (define_insn "*load_tprel64" | |
870 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 871 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
872 | UNSPEC_TPREL))] |
873 | "TARGET_TLS64" | |
874 | "movl %0 = @tprel(%1)" | |
875 | [(set_attr "itanium_class" "long_i")]) | |
876 | ||
877 | (define_insn "*load_tprel22" | |
878 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 879 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
880 | UNSPEC_TPREL))] |
881 | "" | |
882 | "addl %0 = @tprel(%1), r0" | |
883 | [(set_attr "itanium_class" "ialu")]) | |
884 | ||
5e6c8b64 RH |
885 | (define_insn_and_split "*load_tprel_ie" |
886 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 887 | (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
888 | UNSPEC_TPREL))] |
889 | "" | |
890 | "#" | |
891 | "reload_completed" | |
892 | [(set (match_dup 0) | |
893 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL) | |
894 | (match_dup 2))) | |
895 | (set (match_dup 0) (match_dup 3))] | |
896 | { | |
897 | operands[2] = pic_offset_table_rtx; | |
898 | operands[3] = gen_const_mem (DImode, operands[0]); | |
899 | }) | |
900 | ||
901 | (define_insn "*load_ltoff_tprel" | |
902 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 903 | (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
904 | UNSPEC_LTOFF_TPREL) |
905 | (match_operand:DI 2 "register_operand" "a")))] | |
906 | "" | |
907 | "addl %0 = @ltoff(@tprel(%1)), %2" | |
908 | [(set_attr "itanium_class" "ialu")]) | |
909 | ||
7b6e506e RH |
910 | (define_expand "add_tprel" |
911 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 912 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
913 | UNSPEC_TPREL) |
914 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
915 | "!TARGET_TLS64" |
916 | "") | |
917 | ||
918 | (define_insn "*add_tprel14" | |
919 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 920 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
921 | UNSPEC_TPREL) |
922 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 923 | "TARGET_TLS14" |
5e6c8b64 | 924 | "adds %0 = @tprel(%1), %2" |
7b6e506e RH |
925 | [(set_attr "itanium_class" "ialu")]) |
926 | ||
927 | (define_insn "*add_tprel22" | |
928 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 929 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
930 | UNSPEC_TPREL) |
931 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 932 | "TARGET_TLS22" |
5e6c8b64 | 933 | "addl %0 = @tprel(%1), %2" |
7b6e506e RH |
934 | [(set_attr "itanium_class" "ialu")]) |
935 | ||
3f622353 | 936 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
937 | ;; around to play with the second word. However, in order to avoid a |
938 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
939 | ;; in ia64_split_tmode_move. | |
3f622353 | 940 | (define_expand "movti" |
2ffe0e02 ZW |
941 | [(set (match_operand:TI 0 "general_operand" "") |
942 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 943 | "" |
3f622353 | 944 | { |
7b6e506e RH |
945 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
946 | if (!op1) | |
947 | DONE; | |
948 | operands[1] = op1; | |
1d5d7a21 | 949 | }) |
3f622353 | 950 | |
388092d5 | 951 | (define_insn_and_split "movti_internal" |
b6fb7d46 JW |
952 | [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q") |
953 | (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))] | |
3f622353 | 954 | "ia64_move_ok (operands[0], operands[1])" |
a71aef0b JB |
955 | "@ |
956 | # | |
957 | # | |
958 | ldfp8 %X0 = %1%P1 | |
959 | # | |
960 | #" | |
961 | "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])" | |
3f622353 | 962 | [(const_int 0)] |
3f622353 | 963 | { |
f57fc998 | 964 | ia64_split_tmode_move (operands); |
3f622353 | 965 | DONE; |
1d5d7a21 | 966 | } |
388092d5 AB |
967 | [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown") |
968 | (set_attr "speculable1" "yes") | |
969 | (set_attr "speculable2" "no, no, yes, no, no")]) | |
e314e331 | 970 | |
c65ebc55 JW |
971 | ;; Floating Point Moves |
972 | ;; | |
973 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 974 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
975 | |
976 | (define_expand "movsf" | |
977 | [(set (match_operand:SF 0 "general_operand" "") | |
978 | (match_operand:SF 1 "general_operand" ""))] | |
979 | "" | |
c65ebc55 | 980 | { |
7b6e506e RH |
981 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
982 | if (!op1) | |
983 | DONE; | |
984 | operands[1] = op1; | |
1d5d7a21 | 985 | }) |
c65ebc55 | 986 | |
388092d5 | 987 | (define_insn "movsf_internal" |
4b983fdc RH |
988 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
989 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 990 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 991 | "@ |
1d5d7a21 RH |
992 | mov %0 = %F1 |
993 | ldfs %0 = %1%P1 | |
994 | stfs %0 = %F1%P0 | |
995 | getf.s %0 = %F1 | |
996 | setf.s %0 = %1 | |
997 | mov %0 = %1 | |
998 | ld4%O1 %0 = %1%P1 | |
999 | st4%Q0 %0 = %1%P0" | |
388092d5 AB |
1000 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st") |
1001 | (set_attr "speculable1" "yes") | |
1002 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no")]) | |
c65ebc55 JW |
1003 | |
1004 | (define_expand "movdf" | |
1005 | [(set (match_operand:DF 0 "general_operand" "") | |
1006 | (match_operand:DF 1 "general_operand" ""))] | |
1007 | "" | |
c65ebc55 | 1008 | { |
7b6e506e RH |
1009 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
1010 | if (!op1) | |
1011 | DONE; | |
1012 | operands[1] = op1; | |
1d5d7a21 | 1013 | }) |
c65ebc55 | 1014 | |
388092d5 | 1015 | (define_insn "movdf_internal" |
4b983fdc RH |
1016 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
1017 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 1018 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 1019 | "@ |
1d5d7a21 RH |
1020 | mov %0 = %F1 |
1021 | ldfd %0 = %1%P1 | |
1022 | stfd %0 = %F1%P0 | |
1023 | getf.d %0 = %F1 | |
1024 | setf.d %0 = %1 | |
1025 | mov %0 = %1 | |
1026 | ld8%O1 %0 = %1%P1 | |
1027 | st8%Q0 %0 = %1%P0" | |
388092d5 AB |
1028 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st") |
1029 | (set_attr "speculable1" "yes") | |
1030 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no")]) | |
c65ebc55 | 1031 | |
3f622353 RH |
1032 | ;; With no offsettable memory references, we've got to have a scratch |
1033 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
1034 | (define_expand "movxf" |
1035 | [(set (match_operand:XF 0 "general_operand" "") | |
1036 | (match_operand:XF 1 "general_operand" ""))] | |
1037 | "" | |
e5bde68a | 1038 | { |
4de67c26 JM |
1039 | if (ia64_expand_movxf_movrf (XFmode, operands)) |
1040 | DONE; | |
1d5d7a21 | 1041 | }) |
e5bde68a | 1042 | |
3b572406 | 1043 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 1044 | |
388092d5 | 1045 | (define_insn "movxf_internal" |
78d8e0f9 ZW |
1046 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
1047 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 1048 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 1049 | "@ |
1d5d7a21 RH |
1050 | mov %0 = %F1 |
1051 | ldfe %0 = %1%P1 | |
1052 | stfe %0 = %F1%P0" | |
388092d5 AB |
1053 | [(set_attr "itanium_class" "fmisc,fld,stf") |
1054 | (set_attr "speculable1" "yes") | |
1055 | (set_attr "speculable2" "no, yes,no")]) | |
f57fc998 | 1056 | |
4de67c26 JM |
1057 | ;; Same as for movxf, but for RFmode. |
1058 | (define_expand "movrf" | |
1059 | [(set (match_operand:RF 0 "general_operand" "") | |
1060 | (match_operand:RF 1 "general_operand" ""))] | |
1061 | "" | |
1062 | { | |
1063 | if (ia64_expand_movxf_movrf (RFmode, operands)) | |
1064 | DONE; | |
1065 | }) | |
1066 | ||
1067 | (define_insn "*movrf_internal" | |
1068 | [(set (match_operand:RF 0 "destination_operand" "=f,f, m") | |
1069 | (match_operand:RF 1 "general_operand" "fG,m,fG"))] | |
1070 | "ia64_move_ok (operands[0], operands[1])" | |
1071 | "@ | |
1072 | mov %0 = %F1 | |
1073 | ldf.fill %0 = %1%P1 | |
1074 | stf.spill %0 = %F1%P0" | |
1075 | [(set_attr "itanium_class" "fmisc,fld,stf")]) | |
1076 | ||
f57fc998 | 1077 | ;; Better code generation via insns that deal with TFmode register pairs |
2ffe0e02 | 1078 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 1079 | (define_expand "movtf" |
2ffe0e02 ZW |
1080 | [(set (match_operand:TF 0 "general_operand" "") |
1081 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
1082 | "" |
1083 | { | |
1084 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
1085 | if (!op1) | |
1086 | DONE; | |
1087 | operands[1] = op1; | |
1088 | }) | |
1089 | ||
1090 | (define_insn_and_split "*movtf_internal" | |
e77ee95d | 1091 | [(set (match_operand:TF 0 "destination_operand" "=r,r,m") |
2ffe0e02 | 1092 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
1093 | "ia64_move_ok (operands[0], operands[1])" |
1094 | "#" | |
1095 | "reload_completed" | |
1096 | [(const_int 0)] | |
1097 | { | |
1098 | ia64_split_tmode_move (operands); | |
1099 | DONE; | |
1100 | } | |
1101 | [(set_attr "itanium_class" "unknown") | |
1102 | (set_attr "predicable" "no")]) | |
1103 | ||
c65ebc55 JW |
1104 | \f |
1105 | ;; :::::::::::::::::::: | |
1106 | ;; :: | |
1107 | ;; :: Conversions | |
1108 | ;; :: | |
1109 | ;; :::::::::::::::::::: | |
1110 | ||
1111 | ;; Signed conversions from a smaller integer to a larger integer | |
1112 | ||
1113 | (define_insn "extendqidi2" | |
0551c32d RH |
1114 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1115 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1116 | "" |
1117 | "sxt1 %0 = %1" | |
52e12ad0 | 1118 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1119 | |
1120 | (define_insn "extendhidi2" | |
0551c32d RH |
1121 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1122 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1123 | "" |
1124 | "sxt2 %0 = %1" | |
52e12ad0 | 1125 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1126 | |
1127 | (define_insn "extendsidi2" | |
655f2eb9 RH |
1128 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
1129 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
1130 | "" |
1131 | "@ | |
1132 | sxt4 %0 = %1 | |
aebf2462 | 1133 | fsxt.r %0 = %1, %1" |
52e12ad0 | 1134 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
1135 | |
1136 | ;; Unsigned conversions from a smaller integer to a larger integer | |
1137 | ||
1138 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
1139 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1140 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1141 | "" |
1142 | "@ | |
1143 | zxt1 %0 = %1 | |
1144 | ld1%O1 %0 = %1%P1" | |
388092d5 AB |
1145 | [(set_attr "itanium_class" "xtd,ld") |
1146 | (set_attr "speculable1" "yes") | |
1147 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1148 | |
1149 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
1150 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1151 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1152 | "" |
1153 | "@ | |
1154 | zxt2 %0 = %1 | |
1155 | ld2%O1 %0 = %1%P1" | |
388092d5 AB |
1156 | [(set_attr "itanium_class" "xtd,ld") |
1157 | (set_attr "speculable1" "yes") | |
1158 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1159 | |
1160 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 1161 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 1162 | (zero_extend:DI |
655f2eb9 | 1163 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
1164 | "" |
1165 | "@ | |
d3f6e07b | 1166 | addp4 %0 = %1, r0 |
c65ebc55 | 1167 | ld4%O1 %0 = %1%P1 |
aebf2462 | 1168 | fmix.r %0 = f0, %1" |
388092d5 AB |
1169 | [(set_attr "itanium_class" "ialu,ld,fmisc") |
1170 | (set_attr "speculable1" "yes") | |
1171 | (set_attr "speculable2" "no, yes,no")]) | |
c65ebc55 JW |
1172 | |
1173 | ;; Convert between floating point types of different sizes. | |
1174 | ||
640cea5f JW |
1175 | ;; At first glance, it would appear that emitting fnorm for an extending |
1176 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
1177 | ;; correctly only if the input is properly rounded for its type. In | |
1178 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
1179 | ;; denorm single. Since we don't know what the next instruction will be, we | |
1180 | ;; have to emit an fnorm. | |
1181 | ||
e8e20f18 RH |
1182 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
1183 | ;; when we can. Should probably use a scheme like has been proposed | |
1184 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
1185 | ;; would let combine merge the thing into adjacent insns. See also how the |
1186 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
1187 | ;; se_register_operand. | |
c65ebc55 | 1188 | |
640cea5f JW |
1189 | (define_insn "extendsfdf2" |
1190 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
1191 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1192 | "" |
640cea5f JW |
1193 | "fnorm.d %0 = %1" |
1194 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 1195 | |
02befdf4 ZW |
1196 | (define_insn "extendsfxf2" |
1197 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1198 | (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))] | |
1199 | "" | |
640cea5f JW |
1200 | "fnorm %0 = %1" |
1201 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 1202 | |
02befdf4 ZW |
1203 | (define_insn "extenddfxf2" |
1204 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1205 | (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))] | |
1206 | "" | |
640cea5f JW |
1207 | "fnorm %0 = %1" |
1208 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 1209 | |
c65ebc55 | 1210 | (define_insn "truncdfsf2" |
0551c32d RH |
1211 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1212 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1213 | "" |
aebf2462 | 1214 | "fnorm.s %0 = %1" |
52e12ad0 | 1215 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1216 | |
02befdf4 | 1217 | (define_insn "truncxfsf2" |
0551c32d | 1218 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1219 | (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))] |
1220 | "" | |
aebf2462 | 1221 | "fnorm.s %0 = %1" |
52e12ad0 | 1222 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1223 | |
02befdf4 | 1224 | (define_insn "truncxfdf2" |
0551c32d | 1225 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1226 | (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))] |
1227 | "" | |
aebf2462 | 1228 | "fnorm.d %0 = %1" |
52e12ad0 | 1229 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
1230 | |
1231 | ;; Convert between signed integer types and floating point. | |
1232 | ||
02befdf4 ZW |
1233 | (define_insn "floatdixf2" |
1234 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1235 | (float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
1236 | "" | |
e5bde68a | 1237 | "fcvt.xf %0 = %1" |
52e12ad0 | 1238 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1239 | |
1240 | (define_insn "fix_truncsfdi2" | |
0551c32d RH |
1241 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1242 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1243 | "" |
aebf2462 | 1244 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1245 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1246 | |
1247 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
1248 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1249 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1250 | "" |
aebf2462 | 1251 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1252 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1253 | |
02befdf4 | 1254 | (define_insn "fix_truncxfdi2" |
0551c32d | 1255 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1256 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1257 | "" | |
aebf2462 | 1258 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1259 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1260 | |
02befdf4 | 1261 | (define_insn "fix_truncxfdi2_alts" |
655f2eb9 | 1262 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1263 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1264 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1265 | "" |
aebf2462 | 1266 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 1267 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1268 | |
c65ebc55 JW |
1269 | ;; Convert between unsigned integer types and floating point. |
1270 | ||
1271 | (define_insn "floatunsdisf2" | |
0551c32d RH |
1272 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1273 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1274 | "" |
aebf2462 | 1275 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 1276 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1277 | |
1278 | (define_insn "floatunsdidf2" | |
0551c32d RH |
1279 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
1280 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1281 | "" |
aebf2462 | 1282 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 1283 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1284 | |
02befdf4 ZW |
1285 | (define_insn "floatunsdixf2" |
1286 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1287 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
1288 | "" | |
aebf2462 | 1289 | "fcvt.xuf %0 = %1" |
52e12ad0 | 1290 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1291 | |
c65ebc55 | 1292 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
1293 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1294 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1295 | "" |
aebf2462 | 1296 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1297 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1298 | |
1299 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
1300 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1301 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1302 | "" |
aebf2462 | 1303 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1304 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1305 | |
02befdf4 | 1306 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 1307 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1308 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1309 | "" | |
aebf2462 | 1310 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1311 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1312 | |
02befdf4 | 1313 | (define_insn "fixuns_truncxfdi2_alts" |
655f2eb9 | 1314 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1315 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1316 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1317 | "" |
aebf2462 | 1318 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 1319 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1320 | \f |
1321 | ;; :::::::::::::::::::: | |
1322 | ;; :: | |
1323 | ;; :: Bit field extraction | |
1324 | ;; :: | |
1325 | ;; :::::::::::::::::::: | |
1326 | ||
c65ebc55 | 1327 | (define_insn "extv" |
0551c32d RH |
1328 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1329 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1330 | (match_operand:DI 2 "extr_len_operand" "n") |
1331 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1332 | "" |
1333 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1334 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1335 | |
1336 | (define_insn "extzv" | |
0551c32d RH |
1337 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1338 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1339 | (match_operand:DI 2 "extr_len_operand" "n") |
1340 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1341 | "" |
1342 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1343 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1344 | |
1345 | ;; Insert a bit field. | |
1346 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1347 | ;; Source1 can be 0 or -1. | |
1348 | ;; Source2 can be 0. | |
1349 | ||
1350 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1351 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1352 | ;; where source2 != dest. | |
1353 | ||
1354 | (define_expand "insv" | |
0551c32d | 1355 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1356 | (match_operand:DI 1 "const_int_operand" "") |
1357 | (match_operand:DI 2 "const_int_operand" "")) | |
1358 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1359 | "" | |
c65ebc55 JW |
1360 | { |
1361 | int width = INTVAL (operands[1]); | |
1362 | int shift = INTVAL (operands[2]); | |
1363 | ||
1364 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1365 | pseudo. */ | |
1366 | if (! register_operand (operands[3], DImode) | |
1367 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1368 | operands[3] = force_reg (DImode, operands[3]); | |
1369 | ||
1370 | /* If this is a single dep instruction, we have nothing to do. */ | |
1371 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1372 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1373 | { | |
1374 | /* Check for cases that can be implemented with a mix instruction. */ | |
1375 | if (width == 32 && shift == 0) | |
1376 | { | |
1377 | /* Directly generating the mix4left instruction confuses | |
1378 | optimize_bit_field in function.c. Since this is performing | |
1379 | a useful optimization, we defer generation of the complicated | |
1380 | mix4left RTL to the first splitting phase. */ | |
1381 | rtx tmp = gen_reg_rtx (DImode); | |
1382 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1383 | DONE; | |
1384 | } | |
1385 | else if (width == 32 && shift == 32) | |
1386 | { | |
1387 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1388 | DONE; | |
1389 | } | |
1390 | ||
d2ba6dcf JW |
1391 | /* We could handle remaining cases by emitting multiple dep |
1392 | instructions. | |
1393 | ||
1394 | If we need more than two dep instructions then we lose. A 6 | |
1395 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1396 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1397 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1398 | only one function unit that can execute dep and shr immed. | |
1399 | ||
1400 | If we only need two dep instruction, then we still lose. | |
1401 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1402 | the unnecessary mov, this is still undesirable because it will be | |
1403 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1404 | function unit. */ | |
1405 | ||
c65ebc55 JW |
1406 | FAIL; |
1407 | ||
1408 | #if 0 | |
1409 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1410 | for now. */ | |
1411 | while (width > 16) | |
1412 | { | |
1413 | rtx tmp; | |
1414 | ||
1415 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1416 | operands[3])); | |
1417 | shift += 16; | |
1418 | width -= 16; | |
1419 | tmp = gen_reg_rtx (DImode); | |
1420 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1421 | operands[3] = tmp; | |
1422 | } | |
1423 | operands[1] = GEN_INT (width); | |
1424 | operands[2] = GEN_INT (shift); | |
1425 | #endif | |
1426 | } | |
1d5d7a21 | 1427 | }) |
c65ebc55 JW |
1428 | |
1429 | (define_insn "*insv_internal" | |
0551c32d | 1430 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1431 | (match_operand:DI 1 "const_int_operand" "n") |
1432 | (match_operand:DI 2 "const_int_operand" "n")) | |
1433 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1434 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1435 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1436 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1437 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1438 | |
43a88a8c | 1439 | ;; Combine doesn't like to create bit-field insertions into zero. |
d3f6e07b JB |
1440 | (define_insn "*shladdp4_internal" |
1441 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
1442 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1443 | (match_operand:DI 2 "shladd_log2_operand" "n")) | |
1444 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1445 | "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" | |
1446 | "shladdp4 %0 = %1, %2, r0" | |
1447 | [(set_attr "itanium_class" "ialu")]) | |
1448 | ||
041f25e6 | 1449 | (define_insn "*depz_internal" |
0551c32d RH |
1450 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1451 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
13f70342 | 1452 | (match_operand:DI 2 "const_int_operand" "M")) |
041f25e6 | 1453 | (match_operand:DI 3 "const_int_operand" "n")))] |
13f70342 | 1454 | "satisfies_constraint_M (operands[2]) |
041f25e6 | 1455 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" |
041f25e6 RH |
1456 | { |
1457 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1458 | return "%,dep.z %0 = %1, %2, %3"; |
1459 | } | |
52e12ad0 | 1460 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1461 | |
c65ebc55 | 1462 | (define_insn "shift_mix4left" |
0551c32d | 1463 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1464 | (const_int 32) (const_int 0)) |
0551c32d RH |
1465 | (match_operand:DI 1 "gr_register_operand" "r")) |
1466 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1467 | "" |
1468 | "#" | |
52e12ad0 | 1469 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1470 | |
c65ebc55 JW |
1471 | (define_split |
1472 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1473 | (const_int 32) (const_int 0)) | |
1474 | (match_operand:DI 1 "register_operand" "")) | |
1475 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1476 | "" |
c65ebc55 JW |
1477 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1478 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1479 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1480 | "operands[3] = operands[2];") | |
1481 | ||
1482 | (define_insn "*mix4left" | |
0551c32d | 1483 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1484 | (const_int 32) (const_int 0)) |
0551c32d | 1485 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1486 | (const_int 32)))] |
1487 | "" | |
1488 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1489 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1490 | |
1491 | (define_insn "mix4right" | |
0551c32d | 1492 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1493 | (const_int 32) (const_int 32)) |
0551c32d | 1494 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1495 | "" |
1496 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1497 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1498 | |
1499 | ;; This is used by the rotrsi3 pattern. | |
1500 | ||
1501 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1502 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1503 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1504 | (ashift:DI (zero_extend:DI | |
1505 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1506 | (const_int 32))))] |
1507 | "" | |
fa9a44e8 | 1508 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1509 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1510 | |
1511 | \f | |
1512 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1513 | ;; :: |
27a9b99d | 1514 | ;; :: 1-bit Integer arithmetic |
f2f90c63 RH |
1515 | ;; :: |
1516 | ;; :::::::::::::::::::: | |
1517 | ||
1518 | (define_insn_and_split "andbi3" | |
1519 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1520 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1521 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1522 | "" | |
1523 | "@ | |
1524 | # | |
1525 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1526 | and %0 = %2, %1" | |
1527 | "reload_completed | |
1528 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1529 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1530 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1531 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1532 | (match_dup 0))))] | |
1533 | "" | |
52e12ad0 | 1534 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1535 | |
1536 | (define_insn_and_split "*andcmbi3" | |
1537 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1538 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1539 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1540 | "" | |
1541 | "@ | |
1542 | # | |
967603ef | 1543 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1544 | andcm %0 = %2, %1" |
1545 | "reload_completed | |
1546 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1547 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1548 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1549 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1550 | (match_dup 0))))] | |
1551 | "" | |
52e12ad0 | 1552 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1553 | |
1554 | (define_insn_and_split "iorbi3" | |
1555 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1556 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1557 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1558 | "" | |
1559 | "@ | |
1560 | # | |
1561 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1562 | or %0 = %2, %1" | |
1563 | "reload_completed | |
1564 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1565 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1566 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1567 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1568 | (match_dup 0))))] | |
1569 | "" | |
52e12ad0 | 1570 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1571 | |
1572 | (define_insn_and_split "*iorcmbi3" | |
1573 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1574 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1575 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1576 | "" | |
1577 | "@ | |
1578 | # | |
967603ef | 1579 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1580 | "reload_completed |
1581 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1582 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1583 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1584 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1585 | (match_dup 0))))] | |
1586 | "" | |
52e12ad0 | 1587 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1588 | |
1589 | (define_insn "one_cmplbi2" | |
1590 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1591 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1592 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1593 | "" | |
1594 | "@ | |
1595 | tbit.z %0, %I0 = %1, 0 | |
1596 | xor %0 = 1, %1 | |
1597 | # | |
1598 | #" | |
52e12ad0 | 1599 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1600 | |
1601 | (define_split | |
1602 | [(set (match_operand:BI 0 "register_operand" "") | |
1603 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1604 | (clobber (match_scratch:BI 2 ""))] | |
1605 | "reload_completed | |
1606 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1607 | && rtx_equal_p (operands[0], operands[1])" |
1608 | [(set (match_dup 4) (match_dup 3)) | |
1609 | (set (match_dup 0) (const_int 1)) | |
1610 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1611 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1612 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1613 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1614 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1615 | ||
1616 | (define_split | |
1617 | [(set (match_operand:BI 0 "register_operand" "") | |
1618 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1619 | (clobber (match_scratch:BI 2 ""))] | |
1620 | "reload_completed | |
1621 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1622 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1623 | && ! rtx_equal_p (operands[0], operands[1])" | |
1624 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1625 | (set (match_dup 0) (const_int 0))) | |
1626 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1627 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1628 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1629 | "") |
1630 | ||
1631 | (define_insn "*cmpsi_and_0" | |
1632 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1633 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1634 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1635 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1636 | (match_operand:BI 1 "register_operand" "0")))] | |
1637 | "" | |
1638 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1639 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1640 | |
1641 | (define_insn "*cmpsi_and_1" | |
1642 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1643 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1644 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1645 | (const_int 0)]) | |
1646 | (match_operand:BI 1 "register_operand" "0")))] | |
1647 | "" | |
1648 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1649 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1650 | |
1651 | (define_insn "*cmpsi_andnot_0" | |
1652 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1653 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1654 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1655 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1656 | (match_operand:BI 1 "register_operand" "0")))] | |
1657 | "" | |
1658 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1659 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1660 | |
1661 | (define_insn "*cmpsi_andnot_1" | |
1662 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1663 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1664 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1665 | (const_int 0)])) | |
1666 | (match_operand:BI 1 "register_operand" "0")))] | |
1667 | "" | |
1668 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1669 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1670 | |
1671 | (define_insn "*cmpdi_and_0" | |
1672 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1673 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1674 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1675 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1676 | (match_operand:BI 1 "register_operand" "0")))] | |
1677 | "" | |
1678 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1679 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1680 | |
1681 | (define_insn "*cmpdi_and_1" | |
1682 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1683 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1684 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1685 | (const_int 0)]) | |
1686 | (match_operand:BI 1 "register_operand" "0")))] | |
1687 | "" | |
1688 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1689 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1690 | |
1691 | (define_insn "*cmpdi_andnot_0" | |
1692 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1693 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1694 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1695 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1696 | (match_operand:BI 1 "register_operand" "0")))] | |
1697 | "" | |
1698 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1699 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1700 | |
1701 | (define_insn "*cmpdi_andnot_1" | |
1702 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1703 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1704 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1705 | (const_int 0)])) | |
1706 | (match_operand:BI 1 "register_operand" "0")))] | |
1707 | "" | |
1708 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1709 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1710 | |
1711 | (define_insn "*tbit_and_0" | |
1712 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1713 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1714 | (const_int 1)) | |
1715 | (const_int 0)) | |
c77e04ae | 1716 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1717 | "" |
1718 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1719 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1720 | |
1721 | (define_insn "*tbit_and_1" | |
1722 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1723 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1724 | (const_int 1)) | |
1725 | (const_int 0)) | |
c77e04ae | 1726 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1727 | "" |
1728 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1729 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1730 | |
1731 | (define_insn "*tbit_and_2" | |
1732 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1733 | (and:BI (ne:BI (zero_extract:DI | |
1734 | (match_operand:DI 1 "gr_register_operand" "r") | |
1735 | (const_int 1) | |
5d48891e | 1736 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1737 | (const_int 0)) |
1738 | (match_operand:BI 3 "register_operand" "0")))] | |
1739 | "" | |
1740 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1741 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1742 | |
1743 | (define_insn "*tbit_and_3" | |
1744 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1745 | (and:BI (eq:BI (zero_extract:DI | |
1746 | (match_operand:DI 1 "gr_register_operand" "r") | |
1747 | (const_int 1) | |
5d48891e | 1748 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1749 | (const_int 0)) |
1750 | (match_operand:BI 3 "register_operand" "0")))] | |
1751 | "" | |
1752 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1753 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1754 | |
1755 | (define_insn "*cmpsi_or_0" | |
1756 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1757 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1758 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1759 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1760 | (match_operand:BI 1 "register_operand" "0")))] | |
1761 | "" | |
1762 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1763 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1764 | |
1765 | (define_insn "*cmpsi_or_1" | |
1766 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1767 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1768 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1769 | (const_int 0)]) | |
1770 | (match_operand:BI 1 "register_operand" "0")))] | |
1771 | "" | |
1772 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1773 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1774 | |
1775 | (define_insn "*cmpsi_orcm_0" | |
1776 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1777 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1778 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1779 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1780 | (match_operand:BI 1 "register_operand" "0")))] | |
1781 | "" | |
1782 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1783 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1784 | |
1785 | (define_insn "*cmpsi_orcm_1" | |
1786 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1787 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1788 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1789 | (const_int 0)])) | |
1790 | (match_operand:BI 1 "register_operand" "0")))] | |
1791 | "" | |
1792 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1793 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1794 | |
1795 | (define_insn "*cmpdi_or_0" | |
1796 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1797 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1798 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1799 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1800 | (match_operand:BI 1 "register_operand" "0")))] | |
1801 | "" | |
1802 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1803 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1804 | |
1805 | (define_insn "*cmpdi_or_1" | |
1806 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1807 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1808 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1809 | (const_int 0)]) | |
1810 | (match_operand:BI 1 "register_operand" "0")))] | |
1811 | "" | |
1812 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1813 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1814 | |
1815 | (define_insn "*cmpdi_orcm_0" | |
1816 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1817 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1818 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1819 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1820 | (match_operand:BI 1 "register_operand" "0")))] | |
1821 | "" | |
1822 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1823 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1824 | |
1825 | (define_insn "*cmpdi_orcm_1" | |
1826 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1827 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1828 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1829 | (const_int 0)])) | |
1830 | (match_operand:BI 1 "register_operand" "0")))] | |
1831 | "" | |
1832 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1833 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1834 | |
1835 | (define_insn "*tbit_or_0" | |
1836 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1837 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1838 | (const_int 1)) | |
1839 | (const_int 0)) | |
c77e04ae | 1840 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1841 | "" |
1842 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1843 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1844 | |
1845 | (define_insn "*tbit_or_1" | |
1846 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1847 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1848 | (const_int 1)) | |
1849 | (const_int 0)) | |
c77e04ae | 1850 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1851 | "" |
1852 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1853 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1854 | |
1855 | (define_insn "*tbit_or_2" | |
1856 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1857 | (ior:BI (ne:BI (zero_extract:DI | |
1858 | (match_operand:DI 1 "gr_register_operand" "r") | |
1859 | (const_int 1) | |
5d48891e | 1860 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1861 | (const_int 0)) |
1862 | (match_operand:BI 3 "register_operand" "0")))] | |
1863 | "" | |
1864 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1865 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1866 | |
1867 | (define_insn "*tbit_or_3" | |
1868 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1869 | (ior:BI (eq:BI (zero_extract:DI | |
1870 | (match_operand:DI 1 "gr_register_operand" "r") | |
1871 | (const_int 1) | |
5d48891e | 1872 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1873 | (const_int 0)) |
1874 | (match_operand:BI 3 "register_operand" "0")))] | |
1875 | "" | |
1876 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1877 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1878 | |
1879 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1880 | ||
1881 | (define_split | |
1882 | [(set (match_operand:BI 0 "register_operand" "") | |
1883 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1884 | (const_int 0)) | |
1885 | (match_operand:DI 3 "register_operand" "")) | |
1886 | (const_int 0)))] | |
1887 | "" | |
1888 | [(set (match_dup 0) | |
1889 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1890 | (match_dup 2)))] | |
1891 | "") | |
1892 | ||
1893 | (define_split | |
1894 | [(set (match_operand:BI 0 "register_operand" "") | |
1895 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1896 | (const_int 0)) | |
1897 | (match_operand:DI 3 "register_operand" "")) | |
1898 | (const_int 0)))] | |
1899 | "" | |
1900 | [(set (match_dup 0) | |
1901 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1902 | (match_dup 2))) | |
1903 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1904 | (clobber (scratch))])] | |
1905 | "") | |
1906 | ||
1907 | (define_split | |
1908 | [(set (match_operand:BI 0 "register_operand" "") | |
1909 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1910 | (const_int 0)) | |
1911 | (match_operand:DI 3 "register_operand" "")) | |
1912 | (const_int 0)))] | |
1913 | "" | |
1914 | [(set (match_dup 0) | |
1915 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1916 | (match_dup 2)))] | |
1917 | "") | |
1918 | ||
1919 | (define_split | |
1920 | [(set (match_operand:BI 0 "register_operand" "") | |
1921 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1922 | (const_int 0)) | |
1923 | (match_operand:DI 3 "register_operand" "")) | |
1924 | (const_int 0)))] | |
1925 | "" | |
1926 | [(set (match_dup 0) | |
1927 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1928 | (match_dup 2))) | |
1929 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1930 | (clobber (scratch))])] | |
1931 | "") | |
1932 | ||
1933 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1934 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1935 | ;; nothing bad happens to the comparisons in the meantime. | |
1936 | ;; | |
1937 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1938 | ;; that we're doing height reduction. | |
1939 | ; | |
1940 | ;(define_insn_and_split "" | |
1941 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1942 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1943 | ; [(match_operand 2 "" "") | |
1944 | ; (match_operand 3 "" "")]) | |
1945 | ; (match_operator:BI 4 "comparison_operator" | |
1946 | ; [(match_operand 5 "" "") | |
1947 | ; (match_operand 6 "" "")])) | |
1948 | ; (match_dup 0)))] | |
1949 | ; "flag_schedule_insns" | |
1950 | ; "#" | |
1951 | ; "" | |
1952 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1953 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1954 | ; "") | |
1955 | ; | |
1956 | ;(define_insn_and_split "" | |
1957 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1958 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1959 | ; [(match_operand 2 "" "") | |
1960 | ; (match_operand 3 "" "")]) | |
1961 | ; (match_operator:BI 4 "comparison_operator" | |
1962 | ; [(match_operand 5 "" "") | |
1963 | ; (match_operand 6 "" "")])) | |
1964 | ; (match_dup 0)))] | |
1965 | ; "flag_schedule_insns" | |
1966 | ; "#" | |
1967 | ; "" | |
1968 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1969 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1970 | ; "") | |
1971 | ; | |
1972 | ;(define_split | |
1973 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1974 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1975 | ; [(match_operand 2 "" "") | |
1976 | ; (match_operand 3 "" "")]) | |
1977 | ; (match_operand:BI 7 "register_operand" "")) | |
1978 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1979 | ; [(match_operand 5 "" "") | |
1980 | ; (match_operand 6 "" "")]) | |
1981 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1982 | ; "" | |
1983 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1984 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1985 | ; (match_dup 0)))] | |
1986 | ; "") | |
1987 | ; | |
1988 | ;(define_split | |
1989 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1990 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1991 | ; [(match_operand 2 "" "") | |
1992 | ; (match_operand 3 "" "")]) | |
1993 | ; (match_operand:BI 7 "register_operand" "")) | |
1994 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1995 | ; [(match_operand 5 "" "") | |
1996 | ; (match_operand 6 "" "")]) | |
1997 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1998 | ; "" | |
1999 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
2000 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
2001 | ; (match_dup 0)))] | |
2002 | ; "") | |
2003 | ||
2004 | ;; Try harder to avoid predicate copies by duplicating compares. | |
2005 | ;; Note that we'll have already split the predicate copy, which | |
2006 | ;; is kind of a pain, but oh well. | |
2007 | ||
2008 | (define_peephole2 | |
2009 | [(set (match_operand:BI 0 "register_operand" "") | |
2010 | (match_operand:BI 1 "comparison_operator" "")) | |
2011 | (set (match_operand:CCI 2 "register_operand" "") | |
2012 | (match_operand:CCI 3 "register_operand" "")) | |
2013 | (set (match_operand:CCI 4 "register_operand" "") | |
2014 | (match_operand:CCI 5 "register_operand" "")) | |
2015 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 2016 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
2017 | "REGNO (operands[3]) == REGNO (operands[0]) |
2018 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
2019 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
2020 | && REGNO (operands[6]) == REGNO (operands[2])" | |
2021 | [(set (match_dup 0) (match_dup 1)) | |
2022 | (set (match_dup 6) (match_dup 7))] | |
2023 | "operands[7] = copy_rtx (operands[1]);") | |
2024 | \f | |
2025 | ;; :::::::::::::::::::: | |
2026 | ;; :: | |
27a9b99d | 2027 | ;; :: 16-bit Integer arithmetic |
cf1f6ae3 RH |
2028 | ;; :: |
2029 | ;; :::::::::::::::::::: | |
2030 | ||
2031 | (define_insn "mulhi3" | |
2032 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
2033 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
2034 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
2035 | "" | |
2a7ffc85 | 2036 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 2037 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
2038 | |
2039 | \f | |
2040 | ;; :::::::::::::::::::: | |
c65ebc55 | 2041 | ;; :: |
27a9b99d | 2042 | ;; :: 32-bit Integer arithmetic |
c65ebc55 JW |
2043 | ;; :: |
2044 | ;; :::::::::::::::::::: | |
2045 | ||
058557c4 | 2046 | (define_insn "addsi3" |
0551c32d RH |
2047 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
2048 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
2049 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2050 | "" |
2051 | "@ | |
1d5d7a21 RH |
2052 | add %0 = %1, %2 |
2053 | adds %0 = %2, %1 | |
2054 | addl %0 = %2, %1" | |
52e12ad0 | 2055 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2056 | |
2057 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
2058 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2059 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
2060 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2061 | (const_int 1)))] |
2062 | "" | |
2063 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2064 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2065 | |
5527bf14 | 2066 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
2067 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2068 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2069 | (const_int 2)) |
2070 | (const_int 1)))] | |
2071 | "" | |
2072 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2073 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2074 | |
058557c4 | 2075 | (define_insn "*addsi3_shladd" |
0551c32d RH |
2076 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2077 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 2078 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 2079 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 2080 | "" |
058557c4 | 2081 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 2082 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2083 | |
058557c4 | 2084 | (define_insn "subsi3" |
0551c32d RH |
2085 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2086 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
2087 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2088 | "" |
2089 | "sub %0 = %1, %2" | |
52e12ad0 | 2090 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2091 | |
2092 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
2093 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2094 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
2095 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2096 | "" |
2097 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
2098 | [(set_attr "itanium_class" "ialu")]) |
2099 | ||
2100 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 2101 | |
058557c4 | 2102 | (define_insn "mulsi3" |
0551c32d | 2103 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
2104 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
2105 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2106 | "" |
aebf2462 | 2107 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2108 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 2109 | |
655f2eb9 | 2110 | (define_insn "maddsi4" |
11a13704 RH |
2111 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
2112 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
2113 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
2114 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
2115 | "" | |
aebf2462 | 2116 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2117 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 2118 | |
058557c4 | 2119 | (define_insn "negsi2" |
0551c32d RH |
2120 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2121 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2122 | "" |
2123 | "sub %0 = r0, %1" | |
52e12ad0 | 2124 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2125 | |
2126 | (define_expand "abssi2" | |
2127 | [(set (match_dup 2) | |
f2f90c63 | 2128 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2129 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 2130 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2131 | (neg:SI (match_dup 1)) |
2132 | (match_dup 1)))] | |
c65ebc55 | 2133 | "" |
1d5d7a21 | 2134 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2135 | |
2136 | (define_expand "sminsi3" | |
2137 | [(set (match_dup 3) | |
f2f90c63 | 2138 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2139 | (match_operand:SI 2 "gr_register_operand" ""))) |
2140 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2141 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2142 | (match_dup 2) (match_dup 1)))] |
2143 | "" | |
1d5d7a21 | 2144 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2145 | |
2146 | (define_expand "smaxsi3" | |
2147 | [(set (match_dup 3) | |
f2f90c63 | 2148 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2149 | (match_operand:SI 2 "gr_register_operand" ""))) |
2150 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2151 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2152 | (match_dup 1) (match_dup 2)))] |
2153 | "" | |
1d5d7a21 | 2154 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2155 | |
2156 | (define_expand "uminsi3" | |
2157 | [(set (match_dup 3) | |
f2f90c63 | 2158 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2159 | (match_operand:SI 2 "gr_register_operand" ""))) |
2160 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2161 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2162 | (match_dup 2) (match_dup 1)))] |
2163 | "" | |
1d5d7a21 | 2164 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2165 | |
2166 | (define_expand "umaxsi3" | |
2167 | [(set (match_dup 3) | |
f2f90c63 | 2168 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2169 | (match_operand:SI 2 "gr_register_operand" ""))) |
2170 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2171 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2172 | (match_dup 1) (match_dup 2)))] |
2173 | "" | |
1d5d7a21 | 2174 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 2175 | |
655f2eb9 RH |
2176 | (define_expand "divsi3" |
2177 | [(set (match_operand:SI 0 "register_operand" "") | |
2178 | (div:SI (match_operand:SI 1 "general_operand" "") | |
2179 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2180 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2181 | { |
9aec7fb4 | 2182 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2183 | |
02befdf4 | 2184 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2185 | op0_di = gen_reg_rtx (DImode); |
2186 | ||
2187 | if (CONSTANT_P (operands[1])) | |
2188 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2189 | op1_xf = gen_reg_rtx (XFmode); |
2190 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2191 | |
2192 | if (CONSTANT_P (operands[2])) | |
2193 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2194 | op2_xf = gen_reg_rtx (XFmode); |
2195 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 RH |
2196 | |
2197 | /* 2^-34 */ | |
9aec7fb4 SE |
2198 | twon34_exp = gen_reg_rtx (DImode); |
2199 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2200 | twon34 = gen_reg_rtx (XFmode); | |
2201 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2202 | |
85199961 L |
2203 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2204 | CONST1_RTX (SImode))); | |
2205 | ||
02befdf4 | 2206 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2207 | |
02befdf4 | 2208 | emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2209 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2210 | DONE; | |
1d5d7a21 | 2211 | }) |
655f2eb9 RH |
2212 | |
2213 | (define_expand "modsi3" | |
2214 | [(set (match_operand:SI 0 "register_operand" "") | |
2215 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
2216 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2217 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2218 | { |
2219 | rtx op2_neg, op1_di, div; | |
2220 | ||
2221 | div = gen_reg_rtx (SImode); | |
2222 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
2223 | ||
2224 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2225 | ||
2226 | /* This is a trick to get us to reuse the value that we're sure to | |
2227 | have already copied to the FP regs. */ | |
2228 | op1_di = gen_reg_rtx (DImode); | |
2229 | convert_move (op1_di, operands[1], 0); | |
2230 | ||
2231 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2232 | gen_lowpart (SImode, op1_di))); | |
2233 | DONE; | |
1d5d7a21 | 2234 | }) |
655f2eb9 RH |
2235 | |
2236 | (define_expand "udivsi3" | |
2237 | [(set (match_operand:SI 0 "register_operand" "") | |
2238 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
2239 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2240 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2241 | { |
9aec7fb4 | 2242 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2243 | |
02befdf4 | 2244 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2245 | op0_di = gen_reg_rtx (DImode); |
2246 | ||
2247 | if (CONSTANT_P (operands[1])) | |
2248 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2249 | op1_xf = gen_reg_rtx (XFmode); |
2250 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2251 | |
2252 | if (CONSTANT_P (operands[2])) | |
2253 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2254 | op2_xf = gen_reg_rtx (XFmode); |
2255 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 RH |
2256 | |
2257 | /* 2^-34 */ | |
9aec7fb4 SE |
2258 | twon34_exp = gen_reg_rtx (DImode); |
2259 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2260 | twon34 = gen_reg_rtx (XFmode); | |
2261 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2262 | |
85199961 L |
2263 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2264 | CONST1_RTX (SImode))); | |
2265 | ||
02befdf4 | 2266 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2267 | |
02befdf4 | 2268 | emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2269 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2270 | DONE; | |
1d5d7a21 | 2271 | }) |
655f2eb9 RH |
2272 | |
2273 | (define_expand "umodsi3" | |
2274 | [(set (match_operand:SI 0 "register_operand" "") | |
2275 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
2276 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2277 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2278 | { |
2279 | rtx op2_neg, op1_di, div; | |
2280 | ||
2281 | div = gen_reg_rtx (SImode); | |
2282 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
2283 | ||
2284 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2285 | ||
2286 | /* This is a trick to get us to reuse the value that we're sure to | |
2287 | have already copied to the FP regs. */ | |
2288 | op1_di = gen_reg_rtx (DImode); | |
2289 | convert_move (op1_di, operands[1], 1); | |
2290 | ||
2291 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2292 | gen_lowpart (SImode, op1_di))); | |
2293 | DONE; | |
1d5d7a21 | 2294 | }) |
655f2eb9 RH |
2295 | |
2296 | (define_insn_and_split "divsi3_internal" | |
02befdf4 ZW |
2297 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2298 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2299 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2300 | (clobber (match_scratch:XF 4 "=&f")) | |
2301 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2302 | (clobber (match_scratch:BI 6 "=c")) |
02befdf4 ZW |
2303 | (use (match_operand:XF 3 "fr_register_operand" "f"))] |
2304 | "TARGET_INLINE_INT_DIV" | |
655f2eb9 RH |
2305 | "#" |
2306 | "&& reload_completed" | |
07acc7b3 JW |
2307 | [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] |
2308 | UNSPEC_FR_RECIP_APPROX_RES)) | |
086c0f96 RH |
2309 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2310 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2311 | (use (const_int 1))]) |
2312 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2313 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2314 | (use (const_int 1))])) |
2315 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2316 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
2317 | (minus:XF (match_dup 7) |
2318 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2319 | (use (const_int 1))])) |
2320 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2321 | (parallel [(set (match_dup 4) | |
02befdf4 | 2322 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2323 | (match_dup 4))) |
2324 | (use (const_int 1))])) | |
2325 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2326 | (parallel [(set (match_dup 5) | |
02befdf4 | 2327 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
655f2eb9 RH |
2328 | (match_dup 3))) |
2329 | (use (const_int 1))])) | |
2330 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2331 | (parallel [(set (match_dup 0) | |
02befdf4 | 2332 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2333 | (match_dup 4))) |
2334 | (use (const_int 1))])) | |
2335 | ] | |
02befdf4 | 2336 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 | 2337 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2338 | \f |
2339 | ;; :::::::::::::::::::: | |
2340 | ;; :: | |
27a9b99d | 2341 | ;; :: 64-bit Integer arithmetic |
c65ebc55 JW |
2342 | ;; :: |
2343 | ;; :::::::::::::::::::: | |
2344 | ||
2345 | (define_insn "adddi3" | |
0551c32d RH |
2346 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2347 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2348 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2349 | "" |
2350 | "@ | |
1d5d7a21 RH |
2351 | add %0 = %1, %2 |
2352 | adds %0 = %2, %1 | |
2353 | addl %0 = %2, %1" | |
52e12ad0 | 2354 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2355 | |
2356 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2357 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2358 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2359 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2360 | (const_int 1)))] |
2361 | "" | |
2362 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2363 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2364 | |
5527bf14 RH |
2365 | ;; This has some of the same problems as shladd. We let the shladd |
2366 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2367 | ;; a register, but not more ugliness here. | |
2368 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2369 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2370 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2371 | (const_int 2)) |
2372 | (const_int 1)))] | |
2373 | "" | |
2374 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2375 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2376 | |
c65ebc55 | 2377 | (define_insn "subdi3" |
0551c32d RH |
2378 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2379 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2380 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2381 | "" |
2382 | "sub %0 = %1, %2" | |
52e12ad0 | 2383 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2384 | |
2385 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2386 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2387 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2388 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2389 | "" |
2390 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2391 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2392 | |
cee58bc0 RH |
2393 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2394 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2395 | (define_insn "muldi3" |
0551c32d | 2396 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2397 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2398 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2399 | "" |
aebf2462 | 2400 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2401 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2402 | |
2403 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2404 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2405 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2406 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2407 | ;; here so that it will be present just in case register elimination gives us | |
2408 | ;; the funny result. | |
2409 | ||
2410 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2411 | ||
2412 | ;; ??? Maybe we should change how adds are canonicalized. | |
2413 | ||
655f2eb9 | 2414 | (define_insn "madddi4" |
0551c32d | 2415 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2416 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2417 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2418 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2419 | (clobber (match_scratch:DI 4 "=X"))] |
2420 | "" | |
aebf2462 | 2421 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2422 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2423 | |
2424 | ;; This can be created by register elimination if operand3 of shladd is an | |
2425 | ;; eliminable register or has reg_equiv_constant set. | |
2426 | ||
2427 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2428 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2429 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2430 | ;; incorrectly. |
2431 | ||
655f2eb9 | 2432 | (define_insn "*madddi4_elim" |
c65ebc55 | 2433 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2434 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2435 | (match_operand:DI 2 "register_operand" "f")) | |
2436 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2437 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2438 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2439 | "reload_in_progress" |
2440 | "#" | |
52e12ad0 | 2441 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2442 | |
c65ebc55 JW |
2443 | (define_split |
2444 | [(set (match_operand:DI 0 "register_operand" "") | |
2445 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2446 | (match_operand:DI 2 "register_operand" "")) | |
2447 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2448 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2449 | (clobber (match_scratch:DI 5 ""))] |
2450 | "reload_completed" | |
2451 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2452 | (match_dup 3))) | |
2453 | (clobber (match_dup 0))]) | |
c65ebc55 | 2454 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2455 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2456 | "") | |
2457 | ||
c65ebc55 | 2458 | (define_insn "smuldi3_highpart" |
0551c32d | 2459 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2460 | (truncate:DI |
2461 | (lshiftrt:TI | |
0551c32d RH |
2462 | (mult:TI (sign_extend:TI |
2463 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2464 | (sign_extend:TI | |
2465 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2466 | (const_int 64))))] |
2467 | "" | |
aebf2462 | 2468 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2469 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2470 | |
2471 | (define_insn "umuldi3_highpart" | |
0551c32d | 2472 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2473 | (truncate:DI |
2474 | (lshiftrt:TI | |
0551c32d RH |
2475 | (mult:TI (zero_extend:TI |
2476 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2477 | (zero_extend:TI | |
2478 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2479 | (const_int 64))))] |
2480 | "" | |
aebf2462 | 2481 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2482 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2483 | |
2484 | (define_insn "negdi2" | |
0551c32d RH |
2485 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2486 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2487 | "" |
2488 | "sub %0 = r0, %1" | |
52e12ad0 | 2489 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2490 | |
2491 | (define_expand "absdi2" | |
2492 | [(set (match_dup 2) | |
f2f90c63 | 2493 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2494 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2495 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2496 | (neg:DI (match_dup 1)) |
2497 | (match_dup 1)))] | |
c65ebc55 | 2498 | "" |
1d5d7a21 | 2499 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2500 | |
2501 | (define_expand "smindi3" | |
2502 | [(set (match_dup 3) | |
f2f90c63 | 2503 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2504 | (match_operand:DI 2 "gr_register_operand" ""))) |
2505 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2506 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2507 | (match_dup 2) (match_dup 1)))] |
2508 | "" | |
1d5d7a21 | 2509 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2510 | |
2511 | (define_expand "smaxdi3" | |
2512 | [(set (match_dup 3) | |
f2f90c63 | 2513 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2514 | (match_operand:DI 2 "gr_register_operand" ""))) |
2515 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2516 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2517 | (match_dup 1) (match_dup 2)))] |
2518 | "" | |
1d5d7a21 | 2519 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2520 | |
2521 | (define_expand "umindi3" | |
2522 | [(set (match_dup 3) | |
f2f90c63 | 2523 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2524 | (match_operand:DI 2 "gr_register_operand" ""))) |
2525 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2526 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2527 | (match_dup 2) (match_dup 1)))] |
2528 | "" | |
1d5d7a21 | 2529 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2530 | |
2531 | (define_expand "umaxdi3" | |
2532 | [(set (match_dup 3) | |
f2f90c63 | 2533 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2534 | (match_operand:DI 2 "gr_register_operand" ""))) |
2535 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2536 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2537 | (match_dup 1) (match_dup 2)))] |
2538 | "" | |
1d5d7a21 | 2539 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2540 | |
2541 | (define_expand "ffsdi2" | |
2542 | [(set (match_dup 6) | |
f2f90c63 | 2543 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2544 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2545 | (set (match_dup 5) (const_int 0)) | |
2546 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2547 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2548 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2549 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2550 | (match_dup 5) (match_dup 4)))] |
2551 | "" | |
c65ebc55 JW |
2552 | { |
2553 | operands[2] = gen_reg_rtx (DImode); | |
2554 | operands[3] = gen_reg_rtx (DImode); | |
2555 | operands[4] = gen_reg_rtx (DImode); | |
2556 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2557 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2558 | }) |
c65ebc55 | 2559 | |
c407570a RH |
2560 | (define_expand "ctzdi2" |
2561 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2562 | (const_int -1))) | |
2563 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2564 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2565 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2566 | (popcount:DI (match_dup 4)))] | |
2567 | "" | |
2568 | { | |
2569 | operands[2] = gen_reg_rtx (DImode); | |
2570 | operands[3] = gen_reg_rtx (DImode); | |
2571 | operands[4] = gen_reg_rtx (DImode); | |
2572 | }) | |
2573 | ||
c407570a RH |
2574 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2575 | (define_expand "clzdi2" | |
2576 | [(set (match_dup 2) | |
02befdf4 | 2577 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" ""))) |
c407570a RH |
2578 | (set (match_dup 3) |
2579 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2580 | (set (match_dup 4) (const_int 65598)) | |
2581 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2582 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2583 | "" |
c407570a | 2584 | { |
02befdf4 | 2585 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2586 | operands[3] = gen_reg_rtx (DImode); |
2587 | operands[4] = gen_reg_rtx (DImode); | |
2588 | }) | |
2589 | ||
2590 | (define_insn "popcountdi2" | |
0551c32d | 2591 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2592 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2593 | "" |
2594 | "popcnt %0 = %1" | |
52e12ad0 | 2595 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2596 | |
ff848f0e RS |
2597 | (define_insn "bswapdi2" |
2598 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
2599 | (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
2600 | "" | |
2601 | "mux1 %0 = %1, @rev" | |
2602 | [(set_attr "itanium_class" "mmshf")]) | |
2603 | ||
02befdf4 | 2604 | (define_insn "*getf_exp_xf" |
c407570a | 2605 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
02befdf4 | 2606 | (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")] |
c407570a | 2607 | UNSPEC_GETF_EXP))] |
02befdf4 | 2608 | "" |
c407570a RH |
2609 | "getf.exp %0 = %1" |
2610 | [(set_attr "itanium_class" "frfr")]) | |
2611 | ||
655f2eb9 RH |
2612 | (define_expand "divdi3" |
2613 | [(set (match_operand:DI 0 "register_operand" "") | |
2614 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2615 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2616 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2617 | { |
02befdf4 | 2618 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2619 | |
02befdf4 | 2620 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2621 | |
2622 | if (CONSTANT_P (operands[1])) | |
2623 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2624 | op1_xf = gen_reg_rtx (XFmode); |
2625 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2626 | |
2627 | if (CONSTANT_P (operands[2])) | |
2628 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2629 | op2_xf = gen_reg_rtx (XFmode); |
2630 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 | 2631 | |
85199961 L |
2632 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2633 | CONST1_RTX (DImode))); | |
2634 | ||
dbdd120f | 2635 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2636 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2637 | else |
02befdf4 | 2638 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2639 | |
02befdf4 | 2640 | emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2641 | DONE; |
1d5d7a21 | 2642 | }) |
655f2eb9 RH |
2643 | |
2644 | (define_expand "moddi3" | |
2645 | [(set (match_operand:DI 0 "register_operand" "") | |
2646 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2647 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2648 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2649 | { |
2650 | rtx op2_neg, div; | |
2651 | ||
2652 | div = gen_reg_rtx (DImode); | |
2653 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2654 | ||
2655 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2656 | ||
2657 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2658 | DONE; | |
1d5d7a21 | 2659 | }) |
655f2eb9 RH |
2660 | |
2661 | (define_expand "udivdi3" | |
2662 | [(set (match_operand:DI 0 "register_operand" "") | |
2663 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2664 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2665 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2666 | { |
02befdf4 | 2667 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2668 | |
02befdf4 | 2669 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2670 | |
2671 | if (CONSTANT_P (operands[1])) | |
2672 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2673 | op1_xf = gen_reg_rtx (XFmode); |
2674 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2675 | |
2676 | if (CONSTANT_P (operands[2])) | |
2677 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2678 | op2_xf = gen_reg_rtx (XFmode); |
2679 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 | 2680 | |
85199961 L |
2681 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2682 | CONST1_RTX (DImode))); | |
2683 | ||
dbdd120f | 2684 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2685 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2686 | else |
02befdf4 | 2687 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2688 | |
02befdf4 | 2689 | emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2690 | DONE; |
1d5d7a21 | 2691 | }) |
655f2eb9 RH |
2692 | |
2693 | (define_expand "umoddi3" | |
2694 | [(set (match_operand:DI 0 "register_operand" "") | |
2695 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2696 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2697 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2698 | { |
2699 | rtx op2_neg, div; | |
2700 | ||
2701 | div = gen_reg_rtx (DImode); | |
2702 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2703 | ||
2704 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2705 | ||
2706 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2707 | DONE; | |
1d5d7a21 | 2708 | }) |
655f2eb9 RH |
2709 | |
2710 | (define_insn_and_split "divdi3_internal_lat" | |
02befdf4 ZW |
2711 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2712 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2713 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2714 | (clobber (match_scratch:XF 3 "=&f")) | |
2715 | (clobber (match_scratch:XF 4 "=&f")) | |
2716 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2717 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 2718 | "TARGET_INLINE_INT_DIV == INL_MIN_LAT" |
655f2eb9 RH |
2719 | "#" |
2720 | "&& reload_completed" | |
07acc7b3 JW |
2721 | [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] |
2722 | UNSPEC_FR_RECIP_APPROX_RES)) | |
086c0f96 RH |
2723 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2724 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2725 | (use (const_int 1))]) |
2726 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2727 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2728 | (minus:XF (match_dup 7) |
2729 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2730 | (use (const_int 1))])) |
2731 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2732 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2733 | (use (const_int 1))])) |
2734 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2735 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2736 | (use (const_int 1))])) |
2737 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2738 | (parallel [(set (match_dup 4) | |
02befdf4 | 2739 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
655f2eb9 RH |
2740 | (match_dup 4))) |
2741 | (use (const_int 1))])) | |
2742 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2743 | (parallel [(set (match_dup 0) | |
02befdf4 | 2744 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2745 | (match_dup 0))) |
2746 | (use (const_int 1))])) | |
2747 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2748 | (parallel [(set (match_dup 3) | |
02befdf4 | 2749 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2750 | (match_dup 4))) |
2751 | (use (const_int 1))])) | |
2752 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2753 | (parallel [(set (match_dup 0) | |
02befdf4 | 2754 | (plus:XF (mult:XF (match_dup 5) (match_dup 0)) |
655f2eb9 RH |
2755 | (match_dup 0))) |
2756 | (use (const_int 1))])) | |
2757 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2758 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2759 | (minus:XF (match_dup 1) |
2760 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2761 | (use (const_int 1))])) |
2762 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2763 | (parallel [(set (match_dup 0) | |
02befdf4 | 2764 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2765 | (match_dup 3))) |
2766 | (use (const_int 1))])) | |
2767 | ] | |
02befdf4 | 2768 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 RH |
2769 | [(set_attr "predicable" "no")]) |
2770 | ||
2771 | (define_insn_and_split "divdi3_internal_thr" | |
02befdf4 ZW |
2772 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2773 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2774 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2775 | (clobber (match_scratch:XF 3 "=&f")) | |
2776 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2777 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2778 | "TARGET_INLINE_INT_DIV == INL_MAX_THR" |
655f2eb9 RH |
2779 | "#" |
2780 | "&& reload_completed" | |
07acc7b3 JW |
2781 | [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] |
2782 | UNSPEC_FR_RECIP_APPROX_RES)) | |
086c0f96 RH |
2783 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2784 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2785 | (use (const_int 1))]) |
2786 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2787 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2788 | (minus:XF (match_dup 6) |
2789 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2790 | (use (const_int 1))])) |
2791 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2792 | (parallel [(set (match_dup 0) | |
02befdf4 | 2793 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2794 | (match_dup 0))) |
2795 | (use (const_int 1))])) | |
2796 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2797 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2798 | (use (const_int 1))])) |
2799 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2800 | (parallel [(set (match_dup 0) | |
02befdf4 | 2801 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2802 | (match_dup 0))) |
2803 | (use (const_int 1))])) | |
2804 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2805 | (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1))) |
655f2eb9 RH |
2806 | (use (const_int 1))])) |
2807 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2808 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2809 | (minus:XF (match_dup 1) |
2810 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2811 | (use (const_int 1))])) |
2812 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2813 | (parallel [(set (match_dup 0) | |
02befdf4 | 2814 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2815 | (match_dup 3))) |
2816 | (use (const_int 1))])) | |
2817 | ] | |
02befdf4 | 2818 | "operands[6] = CONST1_RTX (XFmode);" |
655f2eb9 | 2819 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2820 | \f |
2821 | ;; :::::::::::::::::::: | |
2822 | ;; :: | |
27a9b99d | 2823 | ;; :: 128-bit Integer arithmetic |
a71aef0b JB |
2824 | ;; :: |
2825 | ;; :::::::::::::::::::: | |
2826 | ||
2827 | (define_insn "addti3" | |
2828 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2829 | (plus:TI (match_operand:TI 1 "gr_register_operand" "%r") | |
2830 | (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI"))) | |
2831 | (clobber (match_scratch:BI 3 "=&c"))] | |
2832 | "" | |
2833 | "#" | |
2834 | [(set_attr "itanium_class" "unknown")]) | |
2835 | ||
2836 | (define_split | |
2837 | [(set (match_operand:TI 0 "register_operand" "") | |
2838 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2839 | (match_operand:TI 2 "register_operand" ""))) | |
2840 | (clobber (match_scratch:BI 3 ""))] | |
2841 | "reload_completed" | |
2842 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2843 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2844 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2845 | (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6)))) | |
2846 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2847 | (set (match_dup 4) | |
2848 | (plus:DI (plus:DI (match_dup 5) (match_dup 6)) | |
2849 | (const_int 1))))] | |
2850 | { | |
2851 | operands[4] = gen_highpart (DImode, operands[0]); | |
2852 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2853 | operands[5] = gen_highpart (DImode, operands[1]); | |
2854 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2855 | operands[6] = gen_highpart (DImode, operands[2]); | |
2856 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2857 | }) | |
2858 | ||
2859 | (define_split | |
2860 | [(set (match_operand:TI 0 "register_operand" "") | |
2861 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2862 | (match_operand:TI 2 "immediate_operand" ""))) | |
2863 | (clobber (match_scratch:BI 3 ""))] | |
2864 | "reload_completed" | |
2865 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2866 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2867 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2868 | (set (match_dup 4) | |
2869 | (plus:DI (match_dup 5) (match_dup 6)))) | |
2870 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2871 | (set (match_dup 4) | |
2872 | (plus:DI (match_dup 5) (match_dup 7))))] | |
2873 | { | |
2874 | operands[4] = gen_highpart (DImode, operands[0]); | |
2875 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2876 | operands[5] = gen_highpart (DImode, operands[1]); | |
2877 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2878 | operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx; | |
2879 | operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx; | |
2880 | }) | |
2881 | ||
2882 | (define_insn "subti3" | |
2883 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2884 | (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK") | |
2885 | (match_operand:TI 2 "gr_register_operand" "r"))) | |
2886 | (clobber (match_scratch:BI 3 "=&c"))] | |
2887 | "" | |
2888 | "#" | |
2889 | [(set_attr "itanium_class" "unknown")]) | |
2890 | ||
2891 | (define_split | |
2892 | [(set (match_operand:TI 0 "register_operand" "") | |
2893 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
2894 | (match_operand:TI 2 "register_operand" ""))) | |
2895 | (clobber (match_scratch:BI 3 "=&c"))] | |
2896 | "reload_completed" | |
2897 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) | |
2898 | (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0))) | |
2899 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2900 | (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6)))) | |
2901 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2902 | (set (match_dup 4) | |
2903 | (plus:DI (not:DI (match_dup 6)) (match_dup 5))))] | |
2904 | { | |
2905 | operands[4] = gen_highpart (DImode, operands[0]); | |
2906 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2907 | operands[5] = gen_highpart (DImode, operands[1]); | |
2908 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2909 | operands[6] = gen_highpart (DImode, operands[2]); | |
2910 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2911 | }) | |
2912 | ||
2913 | (define_split | |
2914 | [(set (match_operand:TI 0 "register_operand" "") | |
2915 | (minus:TI (match_operand:TI 1 "immediate_operand" "") | |
2916 | (match_operand:TI 2 "register_operand" ""))) | |
2917 | (clobber (match_scratch:BI 3 "=&c"))] | |
13f70342 | 2918 | "reload_completed && satisfies_constraint_K (operands[1])" |
a71aef0b JB |
2919 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) |
2920 | (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1))) | |
2921 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2922 | (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5)))) | |
2923 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2924 | (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))] | |
2925 | { | |
2926 | operands[4] = gen_highpart (DImode, operands[0]); | |
2927 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2928 | operands[5] = gen_highpart (DImode, operands[2]); | |
2929 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2930 | operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx; | |
2931 | operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; | |
2932 | }) | |
2933 | ||
2934 | (define_expand "mulditi3" | |
2935 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2936 | (mult:TI (sign_extend:TI | |
2937 | (match_operand:DI 1 "fr_register_operand" "")) | |
2938 | (sign_extend:TI | |
2939 | (match_operand:DI 2 "fr_register_operand" ""))))] | |
2940 | "" | |
2941 | "") | |
2942 | ||
2943 | (define_insn_and_split "*mulditi3_internal" | |
2944 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2945 | (mult:TI (sign_extend:TI | |
2946 | (match_operand:DI 1 "fr_register_operand" "%f")) | |
2947 | (sign_extend:TI | |
2948 | (match_operand:DI 2 "fr_register_operand" "f"))))] | |
2949 | "" | |
2950 | "#" | |
2951 | "reload_completed" | |
2952 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2953 | (set (match_dup 3) (truncate:DI | |
2954 | (lshiftrt:TI | |
2955 | (mult:TI (sign_extend:TI (match_dup 1)) | |
2956 | (sign_extend:TI (match_dup 2))) | |
2957 | (const_int 64))))] | |
2958 | { | |
2959 | operands[3] = gen_highpart (DImode, operands[0]); | |
2960 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2961 | } | |
2962 | [(set_attr "itanium_class" "unknown")]) | |
2963 | ||
2964 | (define_expand "umulditi3" | |
2965 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2966 | (mult:TI (zero_extend:TI | |
2967 | (match_operand:DI 1 "fr_register_operand" "")) | |
2968 | (zero_extend:TI | |
2969 | (match_operand:DI 2 "fr_register_operand" ""))))] | |
2970 | "" | |
2971 | "") | |
2972 | ||
2973 | (define_insn_and_split "*umulditi3_internal" | |
2974 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2975 | (mult:TI (zero_extend:TI | |
2976 | (match_operand:DI 1 "fr_register_operand" "%f")) | |
2977 | (zero_extend:TI | |
2978 | (match_operand:DI 2 "fr_register_operand" "f"))))] | |
2979 | "" | |
2980 | "#" | |
2981 | "reload_completed" | |
2982 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2983 | (set (match_dup 3) (truncate:DI | |
2984 | (lshiftrt:TI | |
2985 | (mult:TI (zero_extend:TI (match_dup 1)) | |
2986 | (zero_extend:TI (match_dup 2))) | |
2987 | (const_int 64))))] | |
2988 | { | |
2989 | operands[3] = gen_highpart (DImode, operands[0]); | |
2990 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2991 | } | |
2992 | [(set_attr "itanium_class" "unknown")]) | |
2993 | ||
2994 | (define_insn_and_split "negti2" | |
2995 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2996 | (neg:TI (match_operand:TI 1 "gr_register_operand" "r"))) | |
2997 | (clobber (match_scratch:BI 2 "=&c"))] | |
2998 | "" | |
2999 | "#" | |
3000 | "reload_completed" | |
3001 | [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0))) | |
3002 | (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1))) | |
3003 | (cond_exec (eq (match_dup 2) (const_int 0)) | |
3004 | (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4)))) | |
3005 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
3006 | (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))] | |
3007 | { | |
3008 | operands[3] = gen_highpart (DImode, operands[0]); | |
3009 | operands[0] = gen_lowpart (DImode, operands[0]); | |
3010 | operands[4] = gen_highpart (DImode, operands[1]); | |
3011 | operands[1] = gen_lowpart (DImode, operands[1]); | |
3012 | } | |
3013 | [(set_attr "itanium_class" "unknown")]) | |
3014 | \f | |
3015 | ;; :::::::::::::::::::: | |
3016 | ;; :: | |
27a9b99d | 3017 | ;; :: 32-bit floating point arithmetic |
c65ebc55 JW |
3018 | ;; :: |
3019 | ;; :::::::::::::::::::: | |
3020 | ||
3021 | (define_insn "addsf3" | |
0551c32d RH |
3022 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3023 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
3024 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3025 | "" |
aebf2462 | 3026 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 3027 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3028 | |
3029 | (define_insn "subsf3" | |
0551c32d RH |
3030 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3031 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
3032 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3033 | "" |
aebf2462 | 3034 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3035 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3036 | |
3037 | (define_insn "mulsf3" | |
0551c32d RH |
3038 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3039 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
3040 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 3041 | "" |
aebf2462 | 3042 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 3043 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3044 | |
3045 | (define_insn "abssf2" | |
0551c32d RH |
3046 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3047 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3048 | "" |
aebf2462 | 3049 | "fabs %0 = %1" |
52e12ad0 | 3050 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3051 | |
3052 | (define_insn "negsf2" | |
0551c32d RH |
3053 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3054 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3055 | "" |
aebf2462 | 3056 | "fneg %0 = %1" |
52e12ad0 | 3057 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3058 | |
3059 | (define_insn "*nabssf2" | |
0551c32d RH |
3060 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3061 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 3062 | "" |
aebf2462 | 3063 | "fnegabs %0 = %1" |
52e12ad0 | 3064 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3065 | |
046625fa RH |
3066 | (define_insn "copysignsf3" |
3067 | [(set (match_operand:SF 0 "register_operand" "=f") | |
3068 | (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
3069 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
3070 | UNSPEC_COPYSIGN))] | |
3071 | "" | |
3072 | "fmerge.s %0 = %F2, %F1" | |
3073 | [(set_attr "itanium_class" "fmisc")]) | |
3074 | ||
3075 | (define_insn "*ncopysignsf3" | |
3076 | [(set (match_operand:SF 0 "register_operand" "=f") | |
3077 | (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
3078 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
3079 | UNSPEC_COPYSIGN)))] | |
3080 | "" | |
3081 | "fmerge.ns %0 = %F2, %F1" | |
3082 | [(set_attr "itanium_class" "fmisc")]) | |
3083 | ||
7ae4d8d4 | 3084 | (define_insn "sminsf3" |
0551c32d RH |
3085 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3086 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3087 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3088 | "" |
aebf2462 | 3089 | "fmin %0 = %1, %F2" |
52e12ad0 | 3090 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3091 | |
7ae4d8d4 | 3092 | (define_insn "smaxsf3" |
0551c32d RH |
3093 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3094 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3095 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3096 | "" |
aebf2462 | 3097 | "fmax %0 = %1, %F2" |
52e12ad0 | 3098 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3099 | |
655f2eb9 | 3100 | (define_insn "*maddsf4" |
0551c32d RH |
3101 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3102 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3103 | (match_operand:SF 2 "fr_register_operand" "f")) | |
3104 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3105 | "" |
aebf2462 | 3106 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 3107 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3108 | |
655f2eb9 | 3109 | (define_insn "*msubsf4" |
0551c32d RH |
3110 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3111 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3112 | (match_operand:SF 2 "fr_register_operand" "f")) | |
3113 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3114 | "" |
aebf2462 | 3115 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 3116 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3117 | |
3118 | (define_insn "*nmulsf3" | |
0551c32d RH |
3119 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3120 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3121 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3122 | "" |
aebf2462 | 3123 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 3124 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3125 | |
655f2eb9 | 3126 | (define_insn "*nmaddsf4" |
0551c32d | 3127 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
3128 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") |
3129 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3130 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3131 | "" |
aebf2462 | 3132 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 3133 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3134 | |
52ad4d7b ZW |
3135 | (define_insn "*nmaddsf4_alts" |
3136 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3137 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") | |
3138 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3139 | (match_operand:SF 2 "fr_register_operand" "f")))) | |
3140 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3141 | "" | |
3142 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
3143 | [(set_attr "itanium_class" "fmac")]) | |
3144 | ||
26102535 RH |
3145 | (define_expand "divsf3" |
3146 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
3147 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
3148 | (match_operand:SF 2 "fr_register_operand" "")))] | |
02befdf4 | 3149 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3150 | { |
3151 | rtx insn; | |
dbdd120f | 3152 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3153 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); |
3154 | else | |
3155 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
3156 | emit_insn (insn); | |
3157 | DONE; | |
1d5d7a21 | 3158 | }) |
26102535 | 3159 | |
b38ba463 ZW |
3160 | ;; Inline square root. |
3161 | ||
3162 | (define_insn "*sqrt_approx" | |
3163 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3164 | (div:XF (const_int 1) | |
07acc7b3 JW |
3165 | (unspec:XF [(match_operand:XF 2 "fr_register_operand" "f")] |
3166 | UNSPEC_FR_SQRT_RECIP_APPROX_RES))) | |
b38ba463 ZW |
3167 | (set (match_operand:BI 1 "register_operand" "=c") |
3168 | (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3169 | (use (match_operand:SI 3 "const_int_operand" "")) ] | |
3170 | "" | |
3171 | "frsqrta.s%3 %0, %1 = %2" | |
3172 | [(set_attr "itanium_class" "fmisc") | |
3173 | (set_attr "predicable" "no")]) | |
3174 | ||
9aec7fb4 | 3175 | (define_insn "setf_exp_xf" |
b38ba463 ZW |
3176 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3177 | (unspec:XF [(match_operand:DI 1 "register_operand" "r")] | |
3178 | UNSPEC_SETF_EXP))] | |
3179 | "" | |
3180 | "setf.exp %0 = %1" | |
3181 | [(set_attr "itanium_class" "frfr")]) | |
3182 | ||
3183 | (define_expand "sqrtsf2" | |
3184 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3185 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
3186 | "TARGET_INLINE_SQRT" | |
3187 | { | |
3188 | rtx insn; | |
b38ba463 | 3189 | #if 0 |
e820471b | 3190 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3191 | insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]); |
e820471b | 3192 | else |
b38ba463 | 3193 | #else |
e820471b | 3194 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3195 | #endif |
e820471b | 3196 | insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3197 | emit_insn (insn); |
3198 | DONE; | |
3199 | }) | |
3200 | ||
3201 | ;; Latency-optimized square root. | |
3202 | ;; FIXME: Implement. | |
3203 | ||
3204 | ;; Throughput-optimized square root. | |
3205 | ||
3206 | (define_insn_and_split "sqrtsf2_internal_thr" | |
3207 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3208 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f"))) | |
3209 | ;; Register r2 in optimization guide. | |
3210 | (clobber (match_scratch:DI 2 "=r")) | |
3211 | ;; Register f8 in optimization guide | |
3212 | (clobber (match_scratch:XF 3 "=&f")) | |
3213 | ;; Register f9 in optimization guide | |
3214 | (clobber (match_scratch:XF 4 "=&f")) | |
3215 | ;; Register f10 in optimization guide | |
3216 | (clobber (match_scratch:XF 5 "=&f")) | |
3217 | ;; Register p6 in optimization guide. | |
3218 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3219 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3220 | "#" |
3221 | "&& reload_completed" | |
3222 | [ ;; exponent of +1/2 in r2 | |
3223 | (set (match_dup 2) (const_int 65534)) | |
3224 | ;; +1/2 in f8 | |
3225 | (set (match_dup 3) | |
3226 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3227 | ;; Step 1 | |
3228 | ;; y0 = 1/sqrt(a) in f7 | |
3229 | (parallel [(set (match_dup 7) | |
3230 | (div:XF (const_int 1) | |
07acc7b3 JW |
3231 | (unspec:XF [(match_dup 8)] |
3232 | UNSPEC_FR_SQRT_RECIP_APPROX_RES))) | |
b38ba463 ZW |
3233 | (set (match_dup 6) |
3234 | (unspec:BI [(match_dup 8)] | |
07acc7b3 | 3235 | UNSPEC_FR_SQRT_RECIP_APPROX)) |
b38ba463 ZW |
3236 | (use (const_int 0))]) |
3237 | ;; Step 2 | |
3238 | ;; H0 = 1/2 * y0 in f9 | |
3239 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3240 | (parallel [(set (match_dup 4) | |
3241 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3242 | (match_dup 9))) | |
3243 | (use (const_int 1))])) | |
3244 | ;; Step 3 | |
3245 | ;; S0 = a * y0 in f7 | |
3246 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3247 | (parallel [(set (match_dup 7) | |
3248 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3249 | (match_dup 9))) | |
3250 | (use (const_int 1))])) | |
3251 | ;; Step 4 | |
3252 | ;; d = 1/2 - S0 * H0 in f10 | |
3253 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3254 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
3255 | (minus:XF (match_dup 3) |
3256 | (mult:XF (match_dup 7) (match_dup 4)))) | |
b38ba463 ZW |
3257 | (use (const_int 1))])) |
3258 | ;; Step 5 | |
3259 | ;; d' = d + 1/2 * d in f8 | |
3260 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3261 | (parallel [(set (match_dup 3) | |
3262 | (plus:XF (mult:XF (match_dup 3) (match_dup 5)) | |
3263 | (match_dup 5))) | |
3264 | (use (const_int 1))])) | |
3265 | ;; Step 6 | |
3266 | ;; e = d + d * d' in f8 | |
3267 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3268 | (parallel [(set (match_dup 3) | |
3269 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) | |
3270 | (match_dup 5))) | |
3271 | (use (const_int 1))])) | |
3272 | ;; Step 7 | |
3273 | ;; S1 = S0 + e * S0 in f7 | |
3274 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3275 | (parallel [(set (match_dup 0) | |
3276 | (float_truncate:SF | |
3277 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3278 | (match_dup 7)))) | |
3279 | (use (const_int 1))])) | |
3280 | ;; Step 8 | |
3281 | ;; H1 = H0 + e * H0 in f8 | |
3282 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3283 | (parallel [(set (match_dup 3) | |
3284 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
3285 | (match_dup 4))) | |
3286 | (use (const_int 1))])) | |
3287 | ;; Step 9 | |
3288 | ;; d1 = a - S1 * S1 in f9 | |
3289 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3290 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3291 | (minus:XF (match_dup 8) |
3292 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3293 | (use (const_int 1))])) |
3294 | ;; Step 10 | |
3295 | ;; S = S1 + d1 * H1 in f7 | |
3296 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3297 | (parallel [(set (match_dup 0) | |
3298 | (float_truncate:SF | |
3299 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3300 | (match_dup 7)))) | |
3301 | (use (const_int 0))]))] | |
3302 | { | |
3303 | /* Generate 82-bit versions of the input and output operands. */ | |
3304 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3305 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3306 | /* Generate required floating-point constants. */ | |
3307 | operands[9] = CONST0_RTX (XFmode); | |
3308 | } | |
3309 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
3310 | \f |
3311 | ;; :::::::::::::::::::: | |
3312 | ;; :: | |
27a9b99d | 3313 | ;; :: 64-bit floating point arithmetic |
c65ebc55 JW |
3314 | ;; :: |
3315 | ;; :::::::::::::::::::: | |
3316 | ||
3317 | (define_insn "adddf3" | |
0551c32d RH |
3318 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3319 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3320 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3321 | "" |
aebf2462 | 3322 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 3323 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3324 | |
26102535 RH |
3325 | (define_insn "*adddf3_trunc" |
3326 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3327 | (float_truncate:SF | |
3328 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3329 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3330 | "" | |
aebf2462 | 3331 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 3332 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3333 | |
c65ebc55 | 3334 | (define_insn "subdf3" |
0551c32d RH |
3335 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3336 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3337 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3338 | "" |
aebf2462 | 3339 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3340 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3341 | |
26102535 RH |
3342 | (define_insn "*subdf3_trunc" |
3343 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3344 | (float_truncate:SF | |
3345 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3346 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3347 | "" | |
aebf2462 | 3348 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3349 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3350 | |
c65ebc55 | 3351 | (define_insn "muldf3" |
0551c32d RH |
3352 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3353 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3354 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 3355 | "" |
aebf2462 | 3356 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 3357 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3358 | |
26102535 RH |
3359 | (define_insn "*muldf3_trunc" |
3360 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3361 | (float_truncate:SF | |
3362 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3363 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
3364 | "" | |
aebf2462 | 3365 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 3366 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3367 | |
c65ebc55 | 3368 | (define_insn "absdf2" |
0551c32d RH |
3369 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3370 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3371 | "" |
aebf2462 | 3372 | "fabs %0 = %1" |
52e12ad0 | 3373 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3374 | |
3375 | (define_insn "negdf2" | |
0551c32d RH |
3376 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3377 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3378 | "" |
aebf2462 | 3379 | "fneg %0 = %1" |
52e12ad0 | 3380 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3381 | |
3382 | (define_insn "*nabsdf2" | |
0551c32d RH |
3383 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3384 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 3385 | "" |
aebf2462 | 3386 | "fnegabs %0 = %1" |
52e12ad0 | 3387 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3388 | |
046625fa RH |
3389 | (define_insn "copysigndf3" |
3390 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3391 | (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3392 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3393 | UNSPEC_COPYSIGN))] | |
3394 | "" | |
3395 | "fmerge.s %0 = %F2, %F1" | |
3396 | [(set_attr "itanium_class" "fmisc")]) | |
3397 | ||
3398 | (define_insn "*ncopysigndf3" | |
3399 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3400 | (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3401 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3402 | UNSPEC_COPYSIGN)))] | |
3403 | "" | |
3404 | "fmerge.ns %0 = %F2, %F1" | |
3405 | [(set_attr "itanium_class" "fmisc")]) | |
3406 | ||
7ae4d8d4 | 3407 | (define_insn "smindf3" |
0551c32d RH |
3408 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3409 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3410 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3411 | "" |
aebf2462 | 3412 | "fmin %0 = %1, %F2" |
52e12ad0 | 3413 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3414 | |
7ae4d8d4 | 3415 | (define_insn "smaxdf3" |
0551c32d RH |
3416 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3417 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3418 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3419 | "" |
aebf2462 | 3420 | "fmax %0 = %1, %F2" |
52e12ad0 | 3421 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3422 | |
655f2eb9 | 3423 | (define_insn "*madddf4" |
0551c32d RH |
3424 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3425 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3426 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3427 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3428 | "" |
aebf2462 | 3429 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 3430 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3431 | |
26102535 RH |
3432 | (define_insn "*madddf4_trunc" |
3433 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3434 | (float_truncate:SF | |
3435 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3436 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3437 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3438 | "" | |
aebf2462 | 3439 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 3440 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3441 | |
655f2eb9 | 3442 | (define_insn "*msubdf4" |
0551c32d RH |
3443 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3444 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3445 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3446 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3447 | "" |
aebf2462 | 3448 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 3449 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3450 | |
26102535 RH |
3451 | (define_insn "*msubdf4_trunc" |
3452 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3453 | (float_truncate:SF | |
3454 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3455 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3456 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3457 | "" | |
aebf2462 | 3458 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 3459 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3460 | |
c65ebc55 | 3461 | (define_insn "*nmuldf3" |
0551c32d RH |
3462 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3463 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3464 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3465 | "" |
aebf2462 | 3466 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 3467 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3468 | |
26102535 RH |
3469 | (define_insn "*nmuldf3_trunc" |
3470 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3471 | (float_truncate:SF | |
3472 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3473 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
3474 | "" | |
aebf2462 | 3475 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 3476 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3477 | |
655f2eb9 | 3478 | (define_insn "*nmadddf4" |
0551c32d | 3479 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
3480 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3481 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3482 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3483 | "" |
aebf2462 | 3484 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 3485 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3486 | |
3487 | (define_insn "*nmadddf4_alts" | |
3488 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3489 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3490 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3491 | (match_operand:DF 2 "fr_register_operand" "f")))) | |
26102535 RH |
3492 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3493 | "" | |
aebf2462 | 3494 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 3495 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3496 | |
52ad4d7b | 3497 | (define_insn "*nmadddf4_truncsf" |
26102535 RH |
3498 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3499 | (float_truncate:SF | |
52ad4d7b ZW |
3500 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3501 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3502 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
26102535 | 3503 | "" |
aebf2462 | 3504 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 3505 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3506 | |
52ad4d7b ZW |
3507 | (define_insn "*nmadddf4_truncsf_alts" |
3508 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3509 | (float_truncate:SF | |
3510 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") | |
3511 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3512 | (match_operand:DF 2 "fr_register_operand" "f"))))) | |
3513 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3514 | "" | |
3515 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
3516 | [(set_attr "itanium_class" "fmac")]) | |
3517 | ||
26102535 RH |
3518 | (define_expand "divdf3" |
3519 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
3520 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
3521 | (match_operand:DF 2 "fr_register_operand" "")))] | |
02befdf4 | 3522 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3523 | { |
3524 | rtx insn; | |
dbdd120f | 3525 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3526 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); |
3527 | else | |
3528 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
3529 | emit_insn (insn); | |
3530 | DONE; | |
1d5d7a21 | 3531 | }) |
26102535 | 3532 | |
b38ba463 ZW |
3533 | ;; Inline square root. |
3534 | ||
3535 | (define_expand "sqrtdf2" | |
3536 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3537 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
3538 | "TARGET_INLINE_SQRT" | |
3539 | { | |
3540 | rtx insn; | |
b38ba463 | 3541 | #if 0 |
e820471b | 3542 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3543 | insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]); |
e820471b | 3544 | else |
b38ba463 | 3545 | #else |
e820471b | 3546 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3547 | #endif |
e820471b | 3548 | insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3549 | emit_insn (insn); |
3550 | DONE; | |
3551 | }) | |
3552 | ||
3553 | ;; Latency-optimized square root. | |
3554 | ;; FIXME: Implement. | |
3555 | ||
3556 | ;; Throughput-optimized square root. | |
3557 | ||
3558 | (define_insn_and_split "sqrtdf2_internal_thr" | |
3559 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3560 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f"))) | |
3561 | ;; Register r2 in optimization guide. | |
3562 | (clobber (match_scratch:DI 2 "=r")) | |
3563 | ;; Register f8 in optimization guide | |
3564 | (clobber (match_scratch:XF 3 "=&f")) | |
3565 | ;; Register f9 in optimization guide | |
3566 | (clobber (match_scratch:XF 4 "=&f")) | |
3567 | ;; Register f10 in optimization guide | |
3568 | (clobber (match_scratch:XF 5 "=&f")) | |
3569 | ;; Register p6 in optimization guide. | |
3570 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3571 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3572 | "#" |
3573 | "&& reload_completed" | |
3574 | [ ;; exponent of +1/2 in r2 | |
3575 | (set (match_dup 2) (const_int 65534)) | |
3576 | ;; +1/2 in f10 | |
3577 | (set (match_dup 5) | |
3578 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3579 | ;; Step 1 | |
3580 | ;; y0 = 1/sqrt(a) in f7 | |
3581 | (parallel [(set (match_dup 7) | |
3582 | (div:XF (const_int 1) | |
07acc7b3 JW |
3583 | (unspec:XF [(match_dup 8)] |
3584 | UNSPEC_FR_SQRT_RECIP_APPROX_RES))) | |
b38ba463 ZW |
3585 | (set (match_dup 6) |
3586 | (unspec:BI [(match_dup 8)] | |
07acc7b3 | 3587 | UNSPEC_FR_SQRT_RECIP_APPROX)) |
b38ba463 ZW |
3588 | (use (const_int 0))]) |
3589 | ;; Step 2 | |
3590 | ;; H0 = 1/2 * y0 in f8 | |
3591 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3592 | (parallel [(set (match_dup 3) | |
3593 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) | |
3594 | (match_dup 9))) | |
3595 | (use (const_int 1))])) | |
3596 | ;; Step 3 | |
3597 | ;; G0 = a * y0 in f7 | |
3598 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3599 | (parallel [(set (match_dup 7) | |
3600 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3601 | (match_dup 9))) | |
3602 | (use (const_int 1))])) | |
3603 | ;; Step 4 | |
3604 | ;; r0 = 1/2 - G0 * H0 in f9 | |
3605 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3606 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3607 | (minus:XF (match_dup 5) |
3608 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3609 | (use (const_int 1))])) |
3610 | ;; Step 5 | |
3611 | ;; H1 = H0 + r0 * H0 in f8 | |
3612 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3613 | (parallel [(set (match_dup 3) | |
3614 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3615 | (match_dup 3))) | |
3616 | (use (const_int 1))])) | |
3617 | ;; Step 6 | |
3618 | ;; G1 = G0 + r0 * G0 in f7 | |
3619 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3620 | (parallel [(set (match_dup 7) | |
3621 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3622 | (match_dup 7))) | |
3623 | (use (const_int 1))])) | |
3624 | ;; Step 7 | |
3625 | ;; r1 = 1/2 - G1 * H1 in f9 | |
3626 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3627 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3628 | (minus:XF (match_dup 5) |
3629 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3630 | (use (const_int 1))])) |
3631 | ;; Step 8 | |
3632 | ;; H2 = H1 + r1 * H1 in f8 | |
3633 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3634 | (parallel [(set (match_dup 3) | |
3635 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3636 | (match_dup 3))) | |
3637 | (use (const_int 1))])) | |
3638 | ;; Step 9 | |
3639 | ;; G2 = G1 + r1 * G1 in f7 | |
3640 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3641 | (parallel [(set (match_dup 7) | |
3642 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3643 | (match_dup 7))) | |
3644 | (use (const_int 1))])) | |
3645 | ;; Step 10 | |
3646 | ;; d2 = a - G2 * G2 in f9 | |
3647 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3648 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3649 | (minus:XF (match_dup 8) |
3650 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3651 | (use (const_int 1))])) |
3652 | ;; Step 11 | |
3653 | ;; G3 = G2 + d2 * H2 in f7 | |
3654 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3655 | (parallel [(set (match_dup 7) | |
3656 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3657 | (match_dup 7))) | |
3658 | (use (const_int 1))])) | |
3659 | ;; Step 12 | |
3660 | ;; d3 = a - G3 * G3 in f9 | |
3661 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3662 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3663 | (minus:XF (match_dup 8) |
3664 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3665 | (use (const_int 1))])) |
3666 | ;; Step 13 | |
3667 | ;; S = G3 + d3 * H2 in f7 | |
3668 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3669 | (parallel [(set (match_dup 0) | |
3670 | (float_truncate:DF | |
3671 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3672 | (match_dup 7)))) | |
3673 | (use (const_int 0))]))] | |
3674 | { | |
3675 | /* Generate 82-bit versions of the input and output operands. */ | |
3676 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3677 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3678 | /* Generate required floating-point constants. */ | |
3679 | operands[9] = CONST0_RTX (XFmode); | |
3680 | } | |
3681 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3682 | \f |
3683 | ;; :::::::::::::::::::: | |
3684 | ;; :: | |
27a9b99d | 3685 | ;; :: 80-bit floating point arithmetic |
3f622353 RH |
3686 | ;; :: |
3687 | ;; :::::::::::::::::::: | |
3688 | ||
02befdf4 ZW |
3689 | (define_insn "addxf3" |
3690 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3691 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3692 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3693 | "" | |
aebf2462 | 3694 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3695 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3696 | |
02befdf4 | 3697 | (define_insn "*addxf3_truncsf" |
26102535 RH |
3698 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3699 | (float_truncate:SF | |
02befdf4 ZW |
3700 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3701 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3702 | "" | |
aebf2462 | 3703 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3704 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3705 | |
02befdf4 | 3706 | (define_insn "*addxf3_truncdf" |
26102535 RH |
3707 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3708 | (float_truncate:DF | |
02befdf4 ZW |
3709 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3710 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3711 | "" | |
aebf2462 | 3712 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3713 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3714 | |
02befdf4 ZW |
3715 | (define_insn "subxf3" |
3716 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3717 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3718 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3719 | "" | |
aebf2462 | 3720 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3721 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3722 | |
02befdf4 | 3723 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3724 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3725 | (float_truncate:SF | |
02befdf4 ZW |
3726 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3727 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3728 | "" | |
aebf2462 | 3729 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3730 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3731 | |
02befdf4 | 3732 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3733 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3734 | (float_truncate:DF | |
02befdf4 ZW |
3735 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3736 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3737 | "" | |
aebf2462 | 3738 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3739 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3740 | |
02befdf4 ZW |
3741 | (define_insn "mulxf3" |
3742 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3743 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3744 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3745 | "" | |
aebf2462 | 3746 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3747 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3748 | |
02befdf4 | 3749 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3750 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3751 | (float_truncate:SF | |
02befdf4 ZW |
3752 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3753 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3754 | "" | |
aebf2462 | 3755 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3756 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3757 | |
02befdf4 | 3758 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3759 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3760 | (float_truncate:DF | |
02befdf4 ZW |
3761 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3762 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3763 | "" | |
aebf2462 | 3764 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3765 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3766 | |
02befdf4 ZW |
3767 | (define_insn "*mulxf3_alts" |
3768 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3769 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3770 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3771 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3772 | "" |
aebf2462 | 3773 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3774 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3775 | |
02befdf4 | 3776 | (define_insn "*mulxf3_truncsf_alts" |
26102535 RH |
3777 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3778 | (float_truncate:SF | |
02befdf4 ZW |
3779 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3780 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3781 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3782 | "" |
aebf2462 | 3783 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3784 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3785 | |
02befdf4 | 3786 | (define_insn "*mulxf3_truncdf_alts" |
26102535 RH |
3787 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3788 | (float_truncate:DF | |
02befdf4 ZW |
3789 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3790 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3791 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3792 | "" |
aebf2462 | 3793 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3794 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3795 | |
02befdf4 ZW |
3796 | (define_insn "absxf2" |
3797 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3798 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3799 | "" | |
aebf2462 | 3800 | "fabs %0 = %F1" |
52e12ad0 | 3801 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3802 | |
02befdf4 ZW |
3803 | (define_insn "negxf2" |
3804 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3805 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3806 | "" | |
aebf2462 | 3807 | "fneg %0 = %F1" |
52e12ad0 | 3808 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3809 | |
02befdf4 ZW |
3810 | (define_insn "*nabsxf2" |
3811 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3812 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3813 | "" | |
aebf2462 | 3814 | "fnegabs %0 = %F1" |
52e12ad0 | 3815 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3816 | |
046625fa RH |
3817 | (define_insn "copysignxf3" |
3818 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3819 | (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3820 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3821 | UNSPEC_COPYSIGN))] | |
3822 | "" | |
3823 | "fmerge.s %0 = %F2, %F1" | |
3824 | [(set_attr "itanium_class" "fmisc")]) | |
3825 | ||
3826 | (define_insn "*ncopysignxf3" | |
3827 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3828 | (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3829 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3830 | UNSPEC_COPYSIGN)))] | |
3831 | "" | |
3832 | "fmerge.ns %0 = %F2, %F1" | |
3833 | [(set_attr "itanium_class" "fmisc")]) | |
3834 | ||
7ae4d8d4 | 3835 | (define_insn "sminxf3" |
02befdf4 ZW |
3836 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3837 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3838 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3839 | "" | |
aebf2462 | 3840 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3841 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3842 | |
7ae4d8d4 | 3843 | (define_insn "smaxxf3" |
02befdf4 ZW |
3844 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3845 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3846 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3847 | "" | |
aebf2462 | 3848 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3849 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3850 | |
02befdf4 ZW |
3851 | (define_insn "*maddxf4" |
3852 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3853 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3854 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3855 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3856 | "" | |
aebf2462 | 3857 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3858 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3859 | |
02befdf4 | 3860 | (define_insn "*maddxf4_truncsf" |
26102535 RH |
3861 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3862 | (float_truncate:SF | |
02befdf4 ZW |
3863 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3864 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3865 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3866 | "" | |
aebf2462 | 3867 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3868 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3869 | |
02befdf4 | 3870 | (define_insn "*maddxf4_truncdf" |
26102535 RH |
3871 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3872 | (float_truncate:DF | |
02befdf4 ZW |
3873 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3874 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3875 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3876 | "" | |
aebf2462 | 3877 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3878 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3879 | |
02befdf4 ZW |
3880 | (define_insn "*maddxf4_alts" |
3881 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3882 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3883 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3884 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3885 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3886 | "" |
aebf2462 | 3887 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3888 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3889 | |
b38ba463 ZW |
3890 | (define_insn "*maddxf4_alts_truncsf" |
3891 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3892 | (float_truncate:SF | |
3893 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3894 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3895 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
3896 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3897 | "" | |
3898 | "fma.s.s%4 %0 = %F1, %F2, %F3" | |
3899 | [(set_attr "itanium_class" "fmac")]) | |
3900 | ||
02befdf4 | 3901 | (define_insn "*maddxf4_alts_truncdf" |
26102535 RH |
3902 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3903 | (float_truncate:DF | |
02befdf4 ZW |
3904 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3905 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3906 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3907 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3908 | "" |
aebf2462 | 3909 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3910 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3911 | |
02befdf4 ZW |
3912 | (define_insn "*msubxf4" |
3913 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3914 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3915 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3916 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3917 | "" | |
aebf2462 | 3918 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3919 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3920 | |
02befdf4 | 3921 | (define_insn "*msubxf4_truncsf" |
26102535 RH |
3922 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3923 | (float_truncate:SF | |
02befdf4 ZW |
3924 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3925 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3926 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3927 | "" | |
aebf2462 | 3928 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3929 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3930 | |
02befdf4 | 3931 | (define_insn "*msubxf4_truncdf" |
26102535 RH |
3932 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3933 | (float_truncate:DF | |
02befdf4 ZW |
3934 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3935 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3936 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3937 | "" | |
aebf2462 | 3938 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3939 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3940 | |
02befdf4 ZW |
3941 | (define_insn "*nmulxf3" |
3942 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3943 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3944 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3945 | "" | |
aebf2462 | 3946 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3947 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3948 | |
02befdf4 | 3949 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
3950 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3951 | (float_truncate:SF | |
02befdf4 ZW |
3952 | (neg:XF (mult:XF |
3953 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3954 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3955 | "" | |
aebf2462 | 3956 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3957 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3958 | |
02befdf4 | 3959 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
3960 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3961 | (float_truncate:DF | |
02befdf4 ZW |
3962 | (neg:XF (mult:XF |
3963 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3964 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3965 | "" | |
aebf2462 | 3966 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3967 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3968 | |
02befdf4 ZW |
3969 | (define_insn "*nmaddxf4" |
3970 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3971 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3972 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3973 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3974 | )))] | |
02befdf4 | 3975 | "" |
aebf2462 | 3976 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3977 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3978 | |
02befdf4 | 3979 | (define_insn "*nmaddxf4_truncsf" |
26102535 RH |
3980 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3981 | (float_truncate:SF | |
52ad4d7b ZW |
3982 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3983 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3984 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3985 | ))))] | |
02befdf4 | 3986 | "" |
aebf2462 | 3987 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3988 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3989 | |
02befdf4 | 3990 | (define_insn "*nmaddxf4_truncdf" |
26102535 RH |
3991 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3992 | (float_truncate:DF | |
52ad4d7b ZW |
3993 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3994 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3995 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3996 | ))))] | |
02befdf4 | 3997 | "" |
aebf2462 | 3998 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3999 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4000 | |
02befdf4 ZW |
4001 | (define_insn "*nmaddxf4_alts" |
4002 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
4003 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4004 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4005 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4006 | ))) | |
655f2eb9 | 4007 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4008 | "" |
aebf2462 | 4009 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4010 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 4011 | |
52ad4d7b ZW |
4012 | (define_insn "*nmaddxf4_truncsf_alts" |
4013 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
4014 | (float_truncate:SF | |
4015 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") | |
4016 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4017 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4018 | )))) | |
4019 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
4020 | "" | |
4021 | "fnma.s.s%4 %0 = %F1, %F2, %F3" | |
4022 | [(set_attr "itanium_class" "fmac")]) | |
4023 | ||
02befdf4 | 4024 | (define_insn "*nmaddxf4_truncdf_alts" |
26102535 RH |
4025 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4026 | (float_truncate:DF | |
52ad4d7b ZW |
4027 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4028 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4029 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4030 | )))) | |
26102535 | 4031 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4032 | "" |
aebf2462 | 4033 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4034 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4035 | |
02befdf4 ZW |
4036 | (define_expand "divxf3" |
4037 | [(set (match_operand:XF 0 "fr_register_operand" "") | |
4038 | (div:XF (match_operand:XF 1 "fr_register_operand" "") | |
4039 | (match_operand:XF 2 "fr_register_operand" "")))] | |
4040 | "TARGET_INLINE_FLOAT_DIV" | |
26102535 | 4041 | { |
13d1a6e7 SE |
4042 | /* There is only one divxf3 sequence, not two like for divsf and divdf. */ |
4043 | emit_insn (gen_divxf3_internal (operands[0], operands[1], operands[2])); | |
26102535 | 4044 | DONE; |
1d5d7a21 | 4045 | }) |
26102535 | 4046 | |
b38ba463 ZW |
4047 | ;; Inline square root. |
4048 | ||
4049 | (define_expand "sqrtxf2" | |
4050 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4051 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))] | |
4052 | "TARGET_INLINE_SQRT" | |
4053 | { | |
4054 | rtx insn; | |
b38ba463 | 4055 | #if 0 |
e820471b | 4056 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 4057 | insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]); |
e820471b | 4058 | else |
b38ba463 | 4059 | #else |
e820471b | 4060 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 4061 | #endif |
e820471b | 4062 | insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
4063 | emit_insn (insn); |
4064 | DONE; | |
4065 | }) | |
4066 | ||
4067 | ;; Latency-optimized square root. | |
4068 | ;; FIXME: Implement. | |
4069 | ||
4070 | ;; Throughput-optimized square root. | |
4071 | ||
4072 | (define_insn_and_split "sqrtxf2_internal_thr" | |
4073 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4074 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f"))) | |
4075 | ;; Register r2 in optimization guide. | |
4076 | (clobber (match_scratch:DI 2 "=r")) | |
4077 | ;; Register f8 in optimization guide | |
4078 | (clobber (match_scratch:XF 3 "=&f")) | |
4079 | ;; Register f9 in optimization guide | |
4080 | (clobber (match_scratch:XF 4 "=&f")) | |
4081 | ;; Register f10 in optimization guide | |
4082 | (clobber (match_scratch:XF 5 "=&f")) | |
4083 | ;; Register f11 in optimization guide | |
4084 | (clobber (match_scratch:XF 6 "=&f")) | |
4085 | ;; Register p6 in optimization guide. | |
4086 | (clobber (match_scratch:BI 7 "=c"))] | |
dbdd120f | 4087 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
4088 | "#" |
4089 | "&& reload_completed" | |
4090 | [ ;; exponent of +1/2 in r2 | |
4091 | (set (match_dup 2) (const_int 65534)) | |
4092 | ;; +1/2 in f8. The Intel manual mistakenly specifies f10. | |
4093 | (set (match_dup 3) | |
4094 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
4095 | ;; Step 1 | |
4096 | ;; y0 = 1/sqrt(a) in f7 | |
4097 | (parallel [(set (match_dup 8) | |
4098 | (div:XF (const_int 1) | |
07acc7b3 JW |
4099 | (unspec:XF [(match_dup 9)] |
4100 | UNSPEC_FR_SQRT_RECIP_APPROX_RES))) | |
b38ba463 ZW |
4101 | (set (match_dup 7) |
4102 | (unspec:BI [(match_dup 9)] | |
07acc7b3 | 4103 | UNSPEC_FR_SQRT_RECIP_APPROX)) |
b38ba463 ZW |
4104 | (use (const_int 0))]) |
4105 | ;; Step 2 | |
4106 | ;; H0 = 1/2 * y0 in f9 | |
4107 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4108 | (parallel [(set (match_dup 4) | |
4109 | (plus:XF (mult:XF (match_dup 3) (match_dup 8)) | |
4110 | (match_dup 10))) | |
4111 | (use (const_int 1))])) | |
4112 | ;; Step 3 | |
4113 | ;; S0 = a * y0 in f7 | |
4114 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4115 | (parallel [(set (match_dup 8) | |
4116 | (plus:XF (mult:XF (match_dup 9) (match_dup 8)) | |
4117 | (match_dup 10))) | |
4118 | (use (const_int 1))])) | |
4119 | ;; Step 4 | |
4120 | ;; d0 = 1/2 - S0 * H0 in f10 | |
4121 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4122 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4123 | (minus:XF (match_dup 3) |
4124 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4125 | (use (const_int 1))])) |
4126 | ;; Step 5 | |
4127 | ;; H1 = H0 + d0 * H0 in f9 | |
4128 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4129 | (parallel [(set (match_dup 4) | |
4130 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4131 | (match_dup 4))) | |
4132 | (use (const_int 1))])) | |
4133 | ;; Step 6 | |
4134 | ;; S1 = S0 + d0 * S0 in f7 | |
4135 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4136 | (parallel [(set (match_dup 8) | |
4137 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4138 | (match_dup 8))) | |
4139 | (use (const_int 1))])) | |
4140 | ;; Step 7 | |
4141 | ;; d1 = 1/2 - S1 * H1 in f10 | |
4142 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4143 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4144 | (minus:XF (match_dup 3) |
4145 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4146 | (use (const_int 1))])) |
4147 | ;; Step 8 | |
4148 | ;; H2 = H1 + d1 * H1 in f9 | |
4149 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4150 | (parallel [(set (match_dup 4) | |
4151 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4152 | (match_dup 4))) | |
4153 | (use (const_int 1))])) | |
4154 | ;; Step 9 | |
4155 | ;; S2 = S1 + d1 * S1 in f7 | |
4156 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4157 | (parallel [(set (match_dup 8) | |
4158 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4159 | (match_dup 8))) | |
4160 | (use (const_int 1))])) | |
4161 | ;; Step 10 | |
4162 | ;; d2 = 1/2 - S2 * H2 in f10 | |
4163 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4164 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4165 | (minus:XF (match_dup 3) |
4166 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4167 | (use (const_int 1))])) |
4168 | ;; Step 11 | |
4169 | ;; e2 = a - S2 * S2 in f8 | |
4170 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4171 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4172 | (minus:XF (match_dup 9) |
4173 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4174 | (use (const_int 1))])) |
4175 | ;; Step 12 | |
4176 | ;; S3 = S2 + e2 * H2 in f7 | |
4177 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4178 | (parallel [(set (match_dup 8) | |
4179 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4180 | (match_dup 8))) | |
4181 | (use (const_int 1))])) | |
4182 | ;; Step 13 | |
4183 | ;; H3 = H2 + d2 * H2 in f9 | |
4184 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4185 | (parallel [(set (match_dup 4) | |
4186 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4187 | (match_dup 4))) | |
4188 | (use (const_int 1))])) | |
4189 | ;; Step 14 | |
4190 | ;; e3 = a - S3 * S3 in f8 | |
4191 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4192 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4193 | (minus:XF (match_dup 9) |
4194 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4195 | (use (const_int 1))])) |
4196 | ;; Step 15 | |
4197 | ;; S = S3 + e3 * H3 in f7 | |
4198 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4199 | (parallel [(set (match_dup 0) | |
4200 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4201 | (match_dup 8))) | |
4202 | (use (const_int 0))]))] | |
4203 | { | |
4204 | /* Generate 82-bit versions of the input and output operands. */ | |
4205 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
4206 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
4207 | /* Generate required floating-point constants. */ | |
4208 | operands[10] = CONST0_RTX (XFmode); | |
4209 | } | |
4210 | [(set_attr "predicable" "no")]) | |
4211 | ||
26102535 RH |
4212 | ;; ??? frcpa works like cmp.foo.unc. |
4213 | ||
655f2eb9 | 4214 | (define_insn "*recip_approx" |
02befdf4 | 4215 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
07acc7b3 JW |
4216 | (unspec:XF [(const_int 1) |
4217 | (match_operand:XF 3 "fr_register_operand" "f")] | |
4218 | UNSPEC_FR_RECIP_APPROX_RES)) | |
f2f90c63 | 4219 | (set (match_operand:BI 1 "register_operand" "=c") |
02befdf4 | 4220 | (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f") |
086c0f96 | 4221 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 4222 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4223 | "" |
655f2eb9 | 4224 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 4225 | [(set_attr "itanium_class" "fmisc") |
26102535 | 4226 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4227 | \f |
4228 | ;; :::::::::::::::::::: | |
4229 | ;; :: | |
27a9b99d | 4230 | ;; :: 32-bit Integer Shifts and Rotates |
c65ebc55 JW |
4231 | ;; :: |
4232 | ;; :::::::::::::::::::: | |
4233 | ||
9c668921 | 4234 | (define_expand "ashlsi3" |
0551c32d RH |
4235 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4236 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
4237 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 4238 | "" |
9c668921 RH |
4239 | { |
4240 | if (GET_CODE (operands[2]) != CONST_INT) | |
4241 | { | |
4242 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
4243 | we've got to get rid of stray bits outside the SImode register. */ | |
4244 | rtx subshift = gen_reg_rtx (DImode); | |
4245 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
4246 | operands[2] = subshift; | |
4247 | } | |
1d5d7a21 | 4248 | }) |
9c668921 RH |
4249 | |
4250 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
4251 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
4252 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
4253 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 4254 | "" |
041f25e6 RH |
4255 | "@ |
4256 | shladd %0 = %1, %2, r0 | |
4257 | dep.z %0 = %1, %2, %E2 | |
4258 | shl %0 = %1, %2" | |
52e12ad0 | 4259 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
4260 | |
4261 | (define_expand "ashrsi3" | |
0551c32d RH |
4262 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4263 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4264 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4265 | "" |
c65ebc55 | 4266 | { |
041f25e6 RH |
4267 | rtx subtarget = gen_reg_rtx (DImode); |
4268 | if (GET_CODE (operands[2]) == CONST_INT) | |
4269 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
4270 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4271 | else | |
4272 | { | |
9c668921 | 4273 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4274 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4275 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4276 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4277 | } |
4278 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4279 | DONE; | |
1d5d7a21 | 4280 | }) |
c65ebc55 | 4281 | |
c65ebc55 | 4282 | (define_expand "lshrsi3" |
0551c32d RH |
4283 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4284 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4285 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4286 | "" |
c65ebc55 | 4287 | { |
041f25e6 RH |
4288 | rtx subtarget = gen_reg_rtx (DImode); |
4289 | if (GET_CODE (operands[2]) == CONST_INT) | |
4290 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
4291 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4292 | else | |
4293 | { | |
9c668921 | 4294 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4295 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4296 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4297 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4298 | } |
4299 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4300 | DONE; | |
1d5d7a21 | 4301 | }) |
c65ebc55 | 4302 | |
c65ebc55 | 4303 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
4304 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
4305 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
4306 | |
4307 | (define_expand "rotrsi3" | |
66db6b45 RH |
4308 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4309 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
4310 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
4311 | "" | |
66db6b45 RH |
4312 | { |
4313 | if (GET_MODE (operands[2]) != VOIDmode) | |
4314 | { | |
4315 | rtx tmp = gen_reg_rtx (DImode); | |
4316 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
4317 | operands[2] = tmp; | |
4318 | } | |
1d5d7a21 | 4319 | }) |
66db6b45 RH |
4320 | |
4321 | (define_insn_and_split "*rotrsi3_internal" | |
4322 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
4323 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4324 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
4325 | "" | |
4326 | "#" | |
4327 | "reload_completed" | |
c65ebc55 | 4328 | [(set (match_dup 3) |
66db6b45 | 4329 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
4330 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
4331 | (set (match_dup 3) | |
66db6b45 RH |
4332 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
4333 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
4334 | ||
4335 | (define_expand "rotlsi3" | |
4336 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
4337 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
4338 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4339 | "" |
c65ebc55 JW |
4340 | { |
4341 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
4342 | { |
4343 | rtx tmp = gen_reg_rtx (SImode); | |
4344 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
4345 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
4346 | DONE; | |
4347 | } | |
1d5d7a21 | 4348 | }) |
66db6b45 RH |
4349 | |
4350 | (define_insn_and_split "*rotlsi3_internal" | |
4351 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
4352 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4353 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
4354 | "" | |
51094457 JB |
4355 | "mux2 %0 = %1, 0xe1" |
4356 | "reload_completed && INTVAL (operands[2]) != 16" | |
66db6b45 RH |
4357 | [(set (match_dup 3) |
4358 | (ior:DI (zero_extend:DI (match_dup 1)) | |
4359 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
4360 | (set (match_dup 3) | |
4361 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
4362 | { |
4363 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
4364 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
51094457 JB |
4365 | } |
4366 | [(set_attr "itanium_class" "mmshf")]) | |
c65ebc55 JW |
4367 | \f |
4368 | ;; :::::::::::::::::::: | |
4369 | ;; :: | |
27a9b99d | 4370 | ;; :: 64-bit Integer Shifts and Rotates |
c65ebc55 JW |
4371 | ;; :: |
4372 | ;; :::::::::::::::::::: | |
4373 | ||
4374 | (define_insn "ashldi3" | |
52e12ad0 BS |
4375 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
4376 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
4377 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 4378 | "" |
041f25e6 RH |
4379 | "@ |
4380 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 4381 | shl %0 = %1, %2 |
041f25e6 | 4382 | shl %0 = %1, %2" |
52e12ad0 | 4383 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
4384 | |
4385 | ;; ??? Maybe combine this with the multiply and add instruction? | |
4386 | ||
4387 | (define_insn "*shladd" | |
0551c32d RH |
4388 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4389 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4390 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 4391 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
4392 | "" |
4393 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 4394 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4395 | |
4396 | ;; This can be created by register elimination if operand3 of shladd is an | |
4397 | ;; eliminable register or has reg_equiv_constant set. | |
4398 | ||
4399 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
4400 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
4401 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
4402 | ;; incorrectly. | |
4403 | ||
5527bf14 | 4404 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
4405 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
4406 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4407 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 4408 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
4409 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
4410 | "reload_in_progress" | |
e820471b | 4411 | "* gcc_unreachable ();" |
c65ebc55 JW |
4412 | "reload_completed" |
4413 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
4414 | (match_dup 3))) | |
c65ebc55 | 4415 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 4416 | "" |
52e12ad0 | 4417 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4418 | |
4419 | (define_insn "ashrdi3" | |
52e12ad0 BS |
4420 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4421 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4422 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4423 | "" |
52e12ad0 BS |
4424 | "@ |
4425 | shr %0 = %1, %2 | |
4426 | shr %0 = %1, %2" | |
4427 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4428 | |
4429 | (define_insn "lshrdi3" | |
52e12ad0 BS |
4430 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4431 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4432 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4433 | "" |
52e12ad0 BS |
4434 | "@ |
4435 | shr.u %0 = %1, %2 | |
4436 | shr.u %0 = %1, %2" | |
4437 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4438 | |
4439 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
4440 | ;; will load the operand into a register and call the pattern if the predicate | |
4441 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
4442 | ;; verify that we have an appropriate constant in the expander. | |
4443 | ||
4444 | (define_expand "rotrdi3" | |
0551c32d RH |
4445 | [(set (match_operand:DI 0 "gr_register_operand" "") |
4446 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
4447 | (match_operand:DI 2 "nonmemory_operand" "")))] |
4448 | "" | |
c65ebc55 JW |
4449 | { |
4450 | if (! shift_count_operand (operands[2], DImode)) | |
4451 | FAIL; | |
1d5d7a21 | 4452 | }) |
c65ebc55 JW |
4453 | |
4454 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
4455 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4456 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4457 | (match_operand:DI 2 "shift_count_operand" "M")))] |
4458 | "" | |
4459 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 4460 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 4461 | |
66db6b45 RH |
4462 | (define_expand "rotldi3" |
4463 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4464 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
4465 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4466 | "" | |
66db6b45 RH |
4467 | { |
4468 | if (! shift_count_operand (operands[2], DImode)) | |
4469 | FAIL; | |
1d5d7a21 | 4470 | }) |
66db6b45 RH |
4471 | |
4472 | (define_insn "*rotldi3_internal" | |
4473 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4474 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
4475 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
4476 | "" | |
4477 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 4478 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
4479 | \f |
4480 | ;; :::::::::::::::::::: | |
4481 | ;; :: | |
27a9b99d | 4482 | ;; :: 128-bit Integer Shifts and Rotates |
f526a3c8 RH |
4483 | ;; :: |
4484 | ;; :::::::::::::::::::: | |
4485 | ||
16d8386b JB |
4486 | (define_expand "ashlti3" |
4487 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4488 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "") | |
4489 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4490 | "" | |
4491 | { | |
4492 | if (!dshift_count_operand (operands[2], DImode)) | |
4493 | FAIL; | |
4494 | }) | |
4495 | ||
4496 | (define_insn_and_split "*ashlti3_internal" | |
4497 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4498 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4499 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4500 | "" | |
4501 | "#" | |
4502 | "reload_completed" | |
4503 | [(const_int 0)] | |
4504 | { | |
4505 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
4506 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4507 | rtx rh = gen_highpart (DImode, operands[0]); | |
4508 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4509 | rtx shiftlo = GEN_INT (shift & 63); | |
4510 | ||
4511 | if (shift & 64) | |
4512 | { | |
4513 | emit_move_insn (rl, const0_rtx); | |
4514 | if (shift & 63) | |
4515 | emit_insn (gen_ashldi3 (rh, lo, shiftlo)); | |
4516 | else | |
4517 | emit_move_insn (rh, lo); | |
4518 | } | |
4519 | else | |
4520 | { | |
4521 | rtx hi = gen_highpart (DImode, operands[1]); | |
4522 | ||
4523 | emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63))); | |
4524 | emit_insn (gen_ashldi3 (rl, lo, shiftlo)); | |
4525 | } | |
4526 | DONE; | |
4527 | }) | |
4528 | ||
f526a3c8 RH |
4529 | (define_expand "ashrti3" |
4530 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4531 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4532 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4533 | "" | |
4534 | { | |
4535 | if (!dshift_count_operand (operands[2], DImode)) | |
4536 | FAIL; | |
4537 | }) | |
4538 | ||
4539 | (define_insn_and_split "*ashrti3_internal" | |
16d8386b | 4540 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4541 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4542 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4543 | "" | |
4544 | "#" | |
4545 | "reload_completed" | |
4546 | [(const_int 0)] | |
4547 | { | |
4548 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4549 | rtx rl = gen_lowpart (DImode, operands[0]); |
4550 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4551 | rtx hi = gen_highpart (DImode, operands[1]); |
4552 | rtx shiftlo = GEN_INT (shift & 63); | |
4553 | ||
4554 | if (shift & 64) | |
4555 | { | |
16d8386b JB |
4556 | if (shift & 63) |
4557 | emit_insn (gen_ashrdi3 (rl, hi, shiftlo)); | |
4558 | else | |
4559 | emit_move_insn (rl, hi); | |
4560 | emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63))); | |
f526a3c8 RH |
4561 | } |
4562 | else | |
4563 | { | |
16d8386b JB |
4564 | rtx lo = gen_lowpart (DImode, operands[1]); |
4565 | ||
4566 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4567 | emit_insn (gen_ashrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4568 | } |
4569 | DONE; | |
4570 | }) | |
4571 | ||
4572 | (define_expand "lshrti3" | |
4573 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4574 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4575 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4576 | "" | |
4577 | { | |
4578 | if (!dshift_count_operand (operands[2], DImode)) | |
4579 | FAIL; | |
4580 | }) | |
4581 | ||
4582 | (define_insn_and_split "*lshrti3_internal" | |
16d8386b | 4583 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4584 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4585 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4586 | "" | |
4587 | "#" | |
4588 | "reload_completed" | |
4589 | [(const_int 0)] | |
4590 | { | |
4591 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4592 | rtx rl = gen_lowpart (DImode, operands[0]); |
4593 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4594 | rtx hi = gen_highpart (DImode, operands[1]); |
4595 | rtx shiftlo = GEN_INT (shift & 63); | |
4596 | ||
4597 | if (shift & 64) | |
4598 | { | |
16d8386b JB |
4599 | if (shift & 63) |
4600 | emit_insn (gen_lshrdi3 (rl, hi, shiftlo)); | |
4601 | else | |
4602 | emit_move_insn (rl, hi); | |
4603 | emit_move_insn (rh, const0_rtx); | |
f526a3c8 RH |
4604 | } |
4605 | else | |
4606 | { | |
16d8386b JB |
4607 | rtx lo = gen_lowpart (DImode, operands[1]); |
4608 | ||
4609 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4610 | emit_insn (gen_lshrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4611 | } |
4612 | DONE; | |
4613 | }) | |
4614 | ||
a71aef0b JB |
4615 | (define_expand "rotlti3" |
4616 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4617 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "") | |
4618 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4619 | "" | |
4620 | { | |
4621 | if (! dshift_count_operand (operands[2], DImode)) | |
4622 | FAIL; | |
4623 | }) | |
4624 | ||
4625 | (define_insn_and_split "*rotlti3_internal" | |
4626 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4627 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4628 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4629 | "" | |
4630 | "#" | |
4631 | "reload_completed" | |
4632 | [(const_int 0)] | |
4633 | { | |
4634 | HOST_WIDE_INT count = INTVAL (operands[2]); | |
4635 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4636 | rtx rh = gen_highpart (DImode, operands[0]); | |
4637 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4638 | rtx hi = gen_highpart (DImode, operands[1]); | |
4639 | rtx countlo = GEN_INT (-count & 63); | |
4640 | ||
4641 | if (count & 64) | |
4642 | { | |
4643 | if (count & 63) | |
4644 | { | |
4645 | emit_insn (gen_shrp (rl, hi, lo, countlo)); | |
4646 | emit_insn (gen_shrp (rh, lo, hi, countlo)); | |
4647 | } | |
4648 | else | |
4649 | { | |
4650 | emit_move_insn (rl, hi); | |
4651 | emit_move_insn (rh, lo); | |
4652 | } | |
4653 | } | |
4654 | else | |
4655 | { | |
4656 | emit_insn (gen_shrp (rl, lo, hi, countlo)); | |
4657 | emit_insn (gen_shrp (rh, hi, lo, countlo)); | |
4658 | } | |
4659 | DONE; | |
4660 | } | |
4661 | [(set_attr "itanium_class" "unknown")]) | |
4662 | ||
f526a3c8 RH |
4663 | (define_insn "shrp" |
4664 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4665 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
4666 | (match_operand:DI 2 "gr_register_operand" "r") | |
4667 | (match_operand:DI 3 "shift_count_operand" "M")] | |
4668 | UNSPEC_SHRP))] | |
4669 | "" | |
4670 | "shrp %0 = %1, %2, %3" | |
4671 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
4672 | \f |
4673 | ;; :::::::::::::::::::: | |
4674 | ;; :: | |
27a9b99d | 4675 | ;; :: 32-bit Integer Logical operations |
c65ebc55 JW |
4676 | ;; :: |
4677 | ;; :::::::::::::::::::: | |
4678 | ||
4679 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
4680 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
4681 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
4682 | ;; This doesn't work for unary logical operations, because we don't call | |
4683 | ;; apply_distributive_law for them. | |
4684 | ||
4685 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
4686 | ;; apply_distributive_law. We get inefficient code for | |
4687 | ;; int sub4 (int i, int j) { return i & ~j; } | |
4688 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
4689 | ;; (zero_extend (and (not A) B)) in combine. | |
4690 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
4691 | ;; one_cmplsi2 pattern. | |
4692 | ||
058557c4 | 4693 | (define_insn "one_cmplsi2" |
0551c32d RH |
4694 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4695 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4696 | "" |
4697 | "andcm %0 = -1, %1" | |
52e12ad0 | 4698 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4699 | \f |
4700 | ;; :::::::::::::::::::: | |
4701 | ;; :: | |
27a9b99d | 4702 | ;; :: 64-bit Integer Logical operations |
c65ebc55 JW |
4703 | ;; :: |
4704 | ;; :::::::::::::::::::: | |
4705 | ||
4706 | (define_insn "anddi3" | |
0551c32d RH |
4707 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4708 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4709 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4710 | "" |
4711 | "@ | |
4712 | and %0 = %2, %1 | |
aebf2462 | 4713 | fand %0 = %2, %1" |
52e12ad0 | 4714 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4715 | |
4716 | (define_insn "*andnot" | |
0551c32d RH |
4717 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4718 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
4719 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4720 | "" |
4721 | "@ | |
4722 | andcm %0 = %2, %1 | |
aebf2462 | 4723 | fandcm %0 = %2, %1" |
52e12ad0 | 4724 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4725 | |
4726 | (define_insn "iordi3" | |
0551c32d RH |
4727 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4728 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4729 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4730 | "" |
4731 | "@ | |
4732 | or %0 = %2, %1 | |
aebf2462 | 4733 | for %0 = %2, %1" |
52e12ad0 | 4734 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4735 | |
4736 | (define_insn "xordi3" | |
0551c32d RH |
4737 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4738 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4739 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4740 | "" |
4741 | "@ | |
4742 | xor %0 = %2, %1 | |
aebf2462 | 4743 | fxor %0 = %2, %1" |
52e12ad0 | 4744 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4745 | |
4746 | (define_insn "one_cmpldi2" | |
0551c32d RH |
4747 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4748 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4749 | "" |
4750 | "andcm %0 = -1, %1" | |
52e12ad0 | 4751 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4752 | \f |
4753 | ;; :::::::::::::::::::: | |
4754 | ;; :: | |
4755 | ;; :: Comparisons | |
4756 | ;; :: | |
4757 | ;; :::::::::::::::::::: | |
4758 | ||
f2f90c63 RH |
4759 | (define_expand "cmpbi" |
4760 | [(set (cc0) | |
4761 | (compare (match_operand:BI 0 "register_operand" "") | |
4762 | (match_operand:BI 1 "const_int_operand" "")))] | |
4763 | "" | |
f2f90c63 RH |
4764 | { |
4765 | ia64_compare_op0 = operands[0]; | |
4766 | ia64_compare_op1 = operands[1]; | |
4767 | DONE; | |
1d5d7a21 | 4768 | }) |
f2f90c63 | 4769 | |
c65ebc55 JW |
4770 | (define_expand "cmpsi" |
4771 | [(set (cc0) | |
0551c32d RH |
4772 | (compare (match_operand:SI 0 "gr_register_operand" "") |
4773 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4774 | "" |
c65ebc55 JW |
4775 | { |
4776 | ia64_compare_op0 = operands[0]; | |
4777 | ia64_compare_op1 = operands[1]; | |
4778 | DONE; | |
1d5d7a21 | 4779 | }) |
c65ebc55 JW |
4780 | |
4781 | (define_expand "cmpdi" | |
4782 | [(set (cc0) | |
0551c32d RH |
4783 | (compare (match_operand:DI 0 "gr_register_operand" "") |
4784 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4785 | "" |
c65ebc55 JW |
4786 | { |
4787 | ia64_compare_op0 = operands[0]; | |
4788 | ia64_compare_op1 = operands[1]; | |
4789 | DONE; | |
1d5d7a21 | 4790 | }) |
c65ebc55 JW |
4791 | |
4792 | (define_expand "cmpsf" | |
4793 | [(set (cc0) | |
0551c32d RH |
4794 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
4795 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4796 | "" |
c65ebc55 JW |
4797 | { |
4798 | ia64_compare_op0 = operands[0]; | |
4799 | ia64_compare_op1 = operands[1]; | |
4800 | DONE; | |
1d5d7a21 | 4801 | }) |
c65ebc55 JW |
4802 | |
4803 | (define_expand "cmpdf" | |
4804 | [(set (cc0) | |
0551c32d RH |
4805 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
4806 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4807 | "" |
c65ebc55 JW |
4808 | { |
4809 | ia64_compare_op0 = operands[0]; | |
4810 | ia64_compare_op1 = operands[1]; | |
4811 | DONE; | |
1d5d7a21 | 4812 | }) |
c65ebc55 | 4813 | |
02befdf4 | 4814 | (define_expand "cmpxf" |
c65ebc55 | 4815 | [(set (cc0) |
02befdf4 ZW |
4816 | (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "") |
4817 | (match_operand:XF 1 "xfreg_or_fp01_operand" "")))] | |
4818 | "" | |
c65ebc55 JW |
4819 | { |
4820 | ia64_compare_op0 = operands[0]; | |
4821 | ia64_compare_op1 = operands[1]; | |
4822 | DONE; | |
1d5d7a21 | 4823 | }) |
c65ebc55 | 4824 | |
24ea7948 ZW |
4825 | (define_expand "cmptf" |
4826 | [(set (cc0) | |
4827 | (compare (match_operand:TF 0 "gr_register_operand" "") | |
4828 | (match_operand:TF 1 "gr_register_operand" "")))] | |
4829 | "TARGET_HPUX" | |
4830 | { | |
4831 | ia64_compare_op0 = operands[0]; | |
4832 | ia64_compare_op1 = operands[1]; | |
4833 | DONE; | |
4834 | }) | |
4835 | ||
c65ebc55 | 4836 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
4837 | [(set (match_operand:BI 0 "register_operand" "=c") |
4838 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
4839 | [(match_operand:SI 2 "gr_register_operand" "r") |
4840 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
4841 | "" |
4842 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 4843 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4844 | |
18a3c539 JW |
4845 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4846 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4847 | ||
c65ebc55 | 4848 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
4849 | [(set (match_operand:BI 0 "register_operand" "=c") |
4850 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4851 | [(match_operand:SI 2 "gr_register_operand" "r") |
4852 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4853 | "" |
18a3c539 | 4854 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4855 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4856 | |
4857 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
4858 | [(set (match_operand:BI 0 "register_operand" "=c") |
4859 | (match_operator:BI 1 "normal_comparison_operator" | |
4860 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 4861 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 4862 | "" |
f2f90c63 | 4863 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 4864 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4865 | |
18a3c539 JW |
4866 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4867 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4868 | ||
c65ebc55 | 4869 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
4870 | [(set (match_operand:BI 0 "register_operand" "=c") |
4871 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4872 | [(match_operand:DI 2 "gr_register_operand" "r") |
4873 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4874 | "" |
18a3c539 | 4875 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4876 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4877 | |
4878 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4879 | [(set (match_operand:BI 0 "register_operand" "=c") |
4880 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4881 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4882 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4883 | "" |
4884 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4885 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4886 | |
4887 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4888 | [(set (match_operand:BI 0 "register_operand" "=c") |
4889 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4890 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4891 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4892 | "" |
4893 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4894 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4895 | |
02befdf4 | 4896 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
4897 | [(set (match_operand:BI 0 "register_operand" "=c") |
4898 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
4899 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
4900 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
4901 | "" | |
3f622353 | 4902 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4903 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4904 | |
c65ebc55 JW |
4905 | ;; ??? Can this pattern be generated? |
4906 | ||
4907 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4908 | [(set (match_operand:BI 0 "register_operand" "=c") |
4909 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4910 | (const_int 1) |
5d48891e | 4911 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
4912 | (const_int 0)))] |
4913 | "" | |
4914 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4915 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4916 | |
4917 | (define_insn "*bit_one" | |
f2f90c63 RH |
4918 | [(set (match_operand:BI 0 "register_operand" "=c") |
4919 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4920 | (const_int 1) |
5d48891e | 4921 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
4922 | (const_int 0)))] |
4923 | "" | |
4924 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 4925 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4926 | \f |
4927 | ;; :::::::::::::::::::: | |
4928 | ;; :: | |
4929 | ;; :: Branches | |
4930 | ;; :: | |
4931 | ;; :::::::::::::::::::: | |
4932 | ||
4933 | (define_expand "beq" | |
f2f90c63 RH |
4934 | [(set (pc) |
4935 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4936 | (label_ref (match_operand 0 "" "")) |
4937 | (pc)))] | |
4938 | "" | |
f2f90c63 | 4939 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
4940 | |
4941 | (define_expand "bne" | |
f2f90c63 RH |
4942 | [(set (pc) |
4943 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4944 | (label_ref (match_operand 0 "" "")) |
4945 | (pc)))] | |
4946 | "" | |
f2f90c63 | 4947 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
4948 | |
4949 | (define_expand "blt" | |
f2f90c63 RH |
4950 | [(set (pc) |
4951 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4952 | (label_ref (match_operand 0 "" "")) |
4953 | (pc)))] | |
4954 | "" | |
f2f90c63 | 4955 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
4956 | |
4957 | (define_expand "ble" | |
f2f90c63 RH |
4958 | [(set (pc) |
4959 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4960 | (label_ref (match_operand 0 "" "")) |
4961 | (pc)))] | |
4962 | "" | |
f2f90c63 | 4963 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
4964 | |
4965 | (define_expand "bgt" | |
f2f90c63 RH |
4966 | [(set (pc) |
4967 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4968 | (label_ref (match_operand 0 "" "")) |
4969 | (pc)))] | |
4970 | "" | |
f2f90c63 | 4971 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
4972 | |
4973 | (define_expand "bge" | |
f2f90c63 RH |
4974 | [(set (pc) |
4975 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4976 | (label_ref (match_operand 0 "" "")) |
4977 | (pc)))] | |
4978 | "" | |
f2f90c63 | 4979 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
4980 | |
4981 | (define_expand "bltu" | |
f2f90c63 RH |
4982 | [(set (pc) |
4983 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4984 | (label_ref (match_operand 0 "" "")) |
4985 | (pc)))] | |
4986 | "" | |
f2f90c63 | 4987 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
4988 | |
4989 | (define_expand "bleu" | |
f2f90c63 RH |
4990 | [(set (pc) |
4991 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4992 | (label_ref (match_operand 0 "" "")) |
4993 | (pc)))] | |
4994 | "" | |
f2f90c63 | 4995 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
4996 | |
4997 | (define_expand "bgtu" | |
f2f90c63 RH |
4998 | [(set (pc) |
4999 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5000 | (label_ref (match_operand 0 "" "")) |
5001 | (pc)))] | |
5002 | "" | |
f2f90c63 | 5003 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
5004 | |
5005 | (define_expand "bgeu" | |
f2f90c63 RH |
5006 | [(set (pc) |
5007 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5008 | (label_ref (match_operand 0 "" "")) |
5009 | (pc)))] | |
5010 | "" | |
f2f90c63 | 5011 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 5012 | |
e57b9d65 | 5013 | (define_expand "bunordered" |
f2f90c63 RH |
5014 | [(set (pc) |
5015 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5016 | (label_ref (match_operand 0 "" "")) |
5017 | (pc)))] | |
5018 | "" | |
f2f90c63 | 5019 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
5020 | |
5021 | (define_expand "bordered" | |
f2f90c63 RH |
5022 | [(set (pc) |
5023 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5024 | (label_ref (match_operand 0 "" "")) |
5025 | (pc)))] | |
5026 | "" | |
f2f90c63 | 5027 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 5028 | |
6b6c1201 | 5029 | (define_insn "*br_true" |
c65ebc55 | 5030 | [(set (pc) |
6b6c1201 | 5031 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5032 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
5033 | (const_int 0)]) |
5034 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
5035 | (pc)))] |
5036 | "" | |
85548039 | 5037 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 5038 | [(set_attr "itanium_class" "br") |
e5bde68a | 5039 | (set_attr "predicable" "no")]) |
c65ebc55 | 5040 | |
6b6c1201 | 5041 | (define_insn "*br_false" |
c65ebc55 | 5042 | [(set (pc) |
6b6c1201 | 5043 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5044 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5045 | (const_int 0)]) |
c65ebc55 | 5046 | (pc) |
6b6c1201 | 5047 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 5048 | "" |
85548039 | 5049 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 5050 | [(set_attr "itanium_class" "br") |
e5bde68a | 5051 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5052 | \f |
5053 | ;; :::::::::::::::::::: | |
5054 | ;; :: | |
5527bf14 RH |
5055 | ;; :: Counted loop operations |
5056 | ;; :: | |
5057 | ;; :::::::::::::::::::: | |
5058 | ||
5059 | (define_expand "doloop_end" | |
5060 | [(use (match_operand 0 "" "")) ; loop pseudo | |
5061 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
5062 | (use (match_operand 2 "" "")) ; max iterations | |
5063 | (use (match_operand 3 "" "")) ; loop level | |
5064 | (use (match_operand 4 "" ""))] ; label | |
5065 | "" | |
5527bf14 RH |
5066 | { |
5067 | /* Only use cloop on innermost loops. */ | |
5068 | if (INTVAL (operands[3]) > 1) | |
5069 | FAIL; | |
5070 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
5071 | operands[4])); | |
5072 | DONE; | |
1d5d7a21 | 5073 | }) |
5527bf14 RH |
5074 | |
5075 | (define_insn "doloop_end_internal" | |
5076 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
5077 | (const_int 0)) | |
5078 | (label_ref (match_operand 1 "" "")) | |
5079 | (pc))) | |
5080 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
5081 | (plus:DI (match_dup 0) (const_int -1)) |
5082 | (match_dup 0)))] | |
5527bf14 RH |
5083 | "" |
5084 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 5085 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
5086 | (set_attr "predicable" "no")]) |
5087 | \f | |
5088 | ;; :::::::::::::::::::: | |
5089 | ;; :: | |
c65ebc55 JW |
5090 | ;; :: Set flag operations |
5091 | ;; :: | |
5092 | ;; :::::::::::::::::::: | |
5093 | ||
5094 | (define_expand "seq" | |
f2f90c63 | 5095 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5096 | "" |
f2f90c63 | 5097 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
5098 | |
5099 | (define_expand "sne" | |
f2f90c63 | 5100 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5101 | "" |
f2f90c63 | 5102 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
5103 | |
5104 | (define_expand "slt" | |
f2f90c63 | 5105 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5106 | "" |
f2f90c63 | 5107 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
5108 | |
5109 | (define_expand "sle" | |
f2f90c63 | 5110 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5111 | "" |
f2f90c63 | 5112 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
5113 | |
5114 | (define_expand "sgt" | |
f2f90c63 | 5115 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5116 | "" |
f2f90c63 | 5117 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
5118 | |
5119 | (define_expand "sge" | |
f2f90c63 | 5120 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5121 | "" |
f2f90c63 | 5122 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
5123 | |
5124 | (define_expand "sltu" | |
f2f90c63 | 5125 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5126 | "" |
f2f90c63 | 5127 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
5128 | |
5129 | (define_expand "sleu" | |
f2f90c63 | 5130 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5131 | "" |
f2f90c63 | 5132 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
5133 | |
5134 | (define_expand "sgtu" | |
f2f90c63 | 5135 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5136 | "" |
f2f90c63 | 5137 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
5138 | |
5139 | (define_expand "sgeu" | |
f2f90c63 | 5140 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5141 | "" |
f2f90c63 | 5142 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 5143 | |
e57b9d65 | 5144 | (define_expand "sunordered" |
f2f90c63 | 5145 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5146 | "" |
f2f90c63 | 5147 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
5148 | |
5149 | (define_expand "sordered" | |
f2f90c63 | 5150 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5151 | "" |
f2f90c63 | 5152 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 5153 | |
c65ebc55 JW |
5154 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
5155 | ;; efficient than mov/mov/cst/cst. | |
5156 | ||
0551c32d RH |
5157 | (define_insn_and_split "*sne_internal" |
5158 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5159 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5160 | (const_int 0)))] |
5161 | "" | |
5162 | "#" | |
c65ebc55 | 5163 | "reload_completed" |
f2f90c63 RH |
5164 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5165 | (set (match_dup 0) (const_int 1))) | |
5166 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5167 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 5168 | "" |
52e12ad0 | 5169 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 5170 | |
0551c32d RH |
5171 | (define_insn_and_split "*seq_internal" |
5172 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5173 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5174 | (const_int 0)))] |
5175 | "" | |
5176 | "#" | |
c65ebc55 | 5177 | "reload_completed" |
f2f90c63 RH |
5178 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5179 | (set (match_dup 0) (const_int 0))) | |
5180 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5181 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 5182 | "" |
52e12ad0 | 5183 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
5184 | \f |
5185 | ;; :::::::::::::::::::: | |
5186 | ;; :: | |
5187 | ;; :: Conditional move instructions. | |
5188 | ;; :: | |
5189 | ;; :::::::::::::::::::: | |
5190 | ||
5191 | ;; ??? Add movXXcc patterns? | |
5192 | ||
c65ebc55 JW |
5193 | ;; |
5194 | ;; DImode if_then_else patterns. | |
5195 | ;; | |
5196 | ||
75cdbeb8 | 5197 | (define_insn "*cmovdi_internal" |
f2f90c63 | 5198 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 5199 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 5200 | (if_then_else:DI |
f2f90c63 RH |
5201 | (match_operator 4 "predicate_operator" |
5202 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 5203 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 5204 | (const_int 0)]) |
f2f90c63 | 5205 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 5206 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 5207 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 5208 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 5209 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5210 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5211 | { gcc_unreachable (); } |
75cdbeb8 RH |
5212 | [(set_attr "predicable" "no")]) |
5213 | ||
5214 | (define_split | |
f2f90c63 | 5215 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 5216 | (if_then_else |
f2f90c63 RH |
5217 | (match_operator 4 "predicate_operator" |
5218 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 5219 | (const_int 0)]) |
f2f90c63 RH |
5220 | (match_operand 2 "move_operand" "") |
5221 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
5222 | "reload_completed" |
5223 | [(const_int 0)] | |
e5bde68a | 5224 | { |
21515593 RH |
5225 | bool emitted_something = false; |
5226 | rtx dest = operands[0]; | |
5227 | rtx srct = operands[2]; | |
5228 | rtx srcf = operands[3]; | |
5229 | rtx cond = operands[4]; | |
2f937369 | 5230 | |
21515593 | 5231 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 5232 | { |
21515593 RH |
5233 | ia64_emit_cond_move (dest, srct, cond); |
5234 | emitted_something = true; | |
e5bde68a | 5235 | } |
21515593 | 5236 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 5237 | { |
21515593 RH |
5238 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
5239 | VOIDmode, operands[1], const0_rtx); | |
5240 | ia64_emit_cond_move (dest, srcf, cond); | |
5241 | emitted_something = true; | |
3b572406 | 5242 | } |
2f937369 | 5243 | if (! emitted_something) |
f9974026 | 5244 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 5245 | DONE; |
1d5d7a21 | 5246 | }) |
c65ebc55 JW |
5247 | |
5248 | ;; Absolute value pattern. | |
5249 | ||
5250 | (define_insn "*absdi2_internal" | |
0551c32d | 5251 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5252 | (if_then_else:DI |
f2f90c63 RH |
5253 | (match_operator 4 "predicate_operator" |
5254 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5255 | (const_int 0)]) |
0551c32d RH |
5256 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
5257 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5258 | "" |
e5bde68a | 5259 | "#" |
52e12ad0 | 5260 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5261 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5262 | |
5263 | (define_split | |
5264 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 5265 | (if_then_else:DI |
f2f90c63 RH |
5266 | (match_operator 4 "predicate_operator" |
5267 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5268 | (const_int 0)]) |
0551c32d RH |
5269 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5270 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5271 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5272 | [(cond_exec | |
5273 | (match_dup 4) | |
5274 | (set (match_dup 0) | |
5275 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
5276 | "") |
5277 | ||
e5bde68a RH |
5278 | (define_split |
5279 | [(set (match_operand:DI 0 "register_operand" "") | |
5280 | (if_then_else:DI | |
f2f90c63 RH |
5281 | (match_operator 4 "predicate_operator" |
5282 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5283 | (const_int 0)]) |
0551c32d RH |
5284 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5285 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5286 | "reload_completed" |
5287 | [(cond_exec | |
5288 | (match_dup 4) | |
5289 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
5290 | (cond_exec | |
5291 | (match_dup 5) | |
5292 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5293 | { |
5294 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5295 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5296 | }) |
c65ebc55 JW |
5297 | |
5298 | ;; | |
5299 | ;; SImode if_then_else patterns. | |
5300 | ;; | |
5301 | ||
75cdbeb8 | 5302 | (define_insn "*cmovsi_internal" |
f2f90c63 | 5303 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 5304 | (if_then_else:SI |
f2f90c63 RH |
5305 | (match_operator 4 "predicate_operator" |
5306 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 5307 | (const_int 0)]) |
f2f90c63 | 5308 | (match_operand:SI 2 "move_operand" |
3b572406 | 5309 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 5310 | (match_operand:SI 3 "move_operand" |
3b572406 | 5311 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 5312 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5313 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5314 | { gcc_unreachable (); } |
3b572406 | 5315 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
5316 | |
5317 | (define_insn "*abssi2_internal" | |
0551c32d | 5318 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5319 | (if_then_else:SI |
f2f90c63 RH |
5320 | (match_operator 4 "predicate_operator" |
5321 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5322 | (const_int 0)]) |
0551c32d RH |
5323 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
5324 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5325 | "" |
e5bde68a | 5326 | "#" |
52e12ad0 | 5327 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5328 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5329 | |
5330 | (define_split | |
5331 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 5332 | (if_then_else:SI |
f2f90c63 RH |
5333 | (match_operator 4 "predicate_operator" |
5334 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5335 | (const_int 0)]) |
0551c32d RH |
5336 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5337 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5338 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5339 | [(cond_exec | |
5340 | (match_dup 4) | |
5341 | (set (match_dup 0) | |
5342 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
5343 | "") |
5344 | ||
e5bde68a RH |
5345 | (define_split |
5346 | [(set (match_operand:SI 0 "register_operand" "") | |
5347 | (if_then_else:SI | |
f2f90c63 RH |
5348 | (match_operator 4 "predicate_operator" |
5349 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5350 | (const_int 0)]) |
0551c32d RH |
5351 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5352 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5353 | "reload_completed" |
5354 | [(cond_exec | |
5355 | (match_dup 4) | |
5356 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
5357 | (cond_exec | |
5358 | (match_dup 5) | |
5359 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5360 | { |
5361 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5362 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5363 | }) |
e5bde68a | 5364 | |
7dcc803e | 5365 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
5366 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5367 | (match_operator:SI 5 "condop_operator" | |
5368 | [(if_then_else:SI | |
5369 | (match_operator 6 "predicate_operator" | |
5370 | [(match_operand:BI 1 "register_operand" "c") | |
5371 | (const_int 0)]) | |
5372 | (match_operand:SI 2 "gr_register_operand" "r") | |
5373 | (match_operand:SI 3 "gr_register_operand" "r")) | |
5374 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
5375 | "" | |
5376 | "#" | |
acb0638d BS |
5377 | "reload_completed" |
5378 | [(cond_exec | |
5379 | (match_dup 6) | |
5380 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
5381 | (cond_exec | |
5382 | (match_dup 7) | |
5383 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
5384 | { |
5385 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5386 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5387 | } |
7dcc803e BS |
5388 | [(set_attr "itanium_class" "ialu") |
5389 | (set_attr "predicable" "no")]) | |
5390 | ||
acb0638d | 5391 | |
7dcc803e | 5392 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
5393 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5394 | (match_operator:SI 5 "condop_operator" | |
5395 | [(match_operand:SI 4 "gr_register_operand" "r") | |
5396 | (if_then_else:SI | |
5397 | (match_operator 6 "predicate_operator" | |
5398 | [(match_operand:BI 1 "register_operand" "c") | |
5399 | (const_int 0)]) | |
5400 | (match_operand:SI 2 "gr_register_operand" "r") | |
5401 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
5402 | "" | |
5403 | "#" | |
acb0638d BS |
5404 | "reload_completed" |
5405 | [(cond_exec | |
5406 | (match_dup 6) | |
5407 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
5408 | (cond_exec | |
5409 | (match_dup 7) | |
5410 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
5411 | { |
5412 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5413 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5414 | } |
7dcc803e BS |
5415 | [(set_attr "itanium_class" "ialu") |
5416 | (set_attr "predicable" "no")]) | |
acb0638d | 5417 | |
c65ebc55 JW |
5418 | \f |
5419 | ;; :::::::::::::::::::: | |
5420 | ;; :: | |
5421 | ;; :: Call and branch instructions | |
5422 | ;; :: | |
5423 | ;; :::::::::::::::::::: | |
5424 | ||
5425 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
5426 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
5427 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
5428 | ;; registers used as operands. | |
5429 | ||
5430 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
5431 | ;; is supplied for the sake of some RISC machines which need to put this | |
5432 | ;; information into the assembler code; they can put it in the RTL instead of | |
5433 | ;; operand 1. | |
5434 | ||
5435 | (define_expand "call" | |
5436 | [(use (match_operand:DI 0 "" "")) | |
5437 | (use (match_operand 1 "" "")) | |
5438 | (use (match_operand 2 "" "")) | |
5439 | (use (match_operand 3 "" ""))] | |
5440 | "" | |
c65ebc55 | 5441 | { |
599aedd9 | 5442 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 5443 | DONE; |
1d5d7a21 | 5444 | }) |
c65ebc55 | 5445 | |
2ed4af6f RH |
5446 | (define_expand "sibcall" |
5447 | [(use (match_operand:DI 0 "" "")) | |
5448 | (use (match_operand 1 "" "")) | |
5449 | (use (match_operand 2 "" "")) | |
5450 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 5451 | "" |
c65ebc55 | 5452 | { |
599aedd9 | 5453 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 5454 | DONE; |
1d5d7a21 | 5455 | }) |
c65ebc55 | 5456 | |
c65ebc55 | 5457 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
5458 | ;; register in which the value is returned. There are three more operands, |
5459 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 5460 | ;; increased by one). |
2ed4af6f | 5461 | ;; |
c65ebc55 JW |
5462 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
5463 | ||
5464 | (define_expand "call_value" | |
5465 | [(use (match_operand 0 "" "")) | |
5466 | (use (match_operand:DI 1 "" "")) | |
5467 | (use (match_operand 2 "" "")) | |
5468 | (use (match_operand 3 "" "")) | |
5469 | (use (match_operand 4 "" ""))] | |
5470 | "" | |
c65ebc55 | 5471 | { |
599aedd9 | 5472 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 5473 | DONE; |
1d5d7a21 | 5474 | }) |
c65ebc55 | 5475 | |
2ed4af6f RH |
5476 | (define_expand "sibcall_value" |
5477 | [(use (match_operand 0 "" "")) | |
5478 | (use (match_operand:DI 1 "" "")) | |
5479 | (use (match_operand 2 "" "")) | |
5480 | (use (match_operand 3 "" "")) | |
5481 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 5482 | "" |
c65ebc55 | 5483 | { |
599aedd9 | 5484 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 5485 | DONE; |
1d5d7a21 | 5486 | }) |
c65ebc55 | 5487 | |
c65ebc55 JW |
5488 | ;; Call subroutine returning any type. |
5489 | ||
5490 | (define_expand "untyped_call" | |
5491 | [(parallel [(call (match_operand 0 "" "") | |
5492 | (const_int 0)) | |
5493 | (match_operand 1 "" "") | |
5494 | (match_operand 2 "" "")])] | |
5495 | "" | |
c65ebc55 JW |
5496 | { |
5497 | int i; | |
5498 | ||
5499 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
5500 | ||
5501 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
5502 | { | |
5503 | rtx set = XVECEXP (operands[2], 0, i); | |
5504 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
5505 | } | |
5506 | ||
5507 | /* The optimizer does not know that the call sets the function value | |
5508 | registers we stored in the result block. We avoid problems by | |
5509 | claiming that all hard registers are used and clobbered at this | |
5510 | point. */ | |
5511 | emit_insn (gen_blockage ()); | |
5512 | ||
5513 | DONE; | |
1d5d7a21 | 5514 | }) |
c65ebc55 | 5515 | |
599aedd9 RH |
5516 | (define_insn "call_nogp" |
5517 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5518 | (const_int 0)) | |
5519 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 5520 | "" |
599aedd9 | 5521 | "br.call%+.many %1 = %0" |
52e12ad0 | 5522 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5523 | |
599aedd9 | 5524 | (define_insn "call_value_nogp" |
75293ad6 | 5525 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5526 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i")) |
5527 | (const_int 0))) | |
5528 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 5529 | "" |
599aedd9 | 5530 | "br.call%+.many %2 = %1" |
52e12ad0 | 5531 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5532 | |
599aedd9 RH |
5533 | (define_insn "sibcall_nogp" |
5534 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5535 | (const_int 0))] | |
2ed4af6f RH |
5536 | "" |
5537 | "br%+.many %0" | |
52e12ad0 | 5538 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5539 | |
599aedd9 | 5540 | (define_insn "call_gp" |
c8083186 | 5541 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) |
599aedd9 RH |
5542 | (const_int 1)) |
5543 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
5544 | (clobber (match_scratch:DI 2 "=&r,X")) | |
5545 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 5546 | "" |
599aedd9 | 5547 | "#" |
52e12ad0 | 5548 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5549 | |
599aedd9 RH |
5550 | ;; Irritatingly, we don't have access to INSN within the split body. |
5551 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
5552 | (define_split | |
5553 | [(call (mem (match_operand 0 "call_operand" "")) | |
5554 | (const_int 1)) | |
5555 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5556 | (clobber (match_scratch:DI 2 "")) | |
5557 | (clobber (match_scratch:DI 3 ""))] | |
5558 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5559 | [(const_int 0)] | |
5560 | { | |
5561 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5562 | operands[3], true, false); | |
5563 | DONE; | |
5564 | }) | |
5565 | ||
5566 | (define_split | |
5567 | [(call (mem (match_operand 0 "call_operand" "")) | |
5568 | (const_int 1)) | |
5569 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5570 | (clobber (match_scratch:DI 2 "")) | |
5571 | (clobber (match_scratch:DI 3 ""))] | |
5572 | "reload_completed" | |
5573 | [(const_int 0)] | |
5574 | { | |
5575 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5576 | operands[3], false, false); | |
5577 | DONE; | |
5578 | }) | |
5579 | ||
5580 | (define_insn "call_value_gp" | |
75293ad6 | 5581 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5582 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i")) |
5583 | (const_int 1))) | |
5584 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
5585 | (clobber (match_scratch:DI 3 "=&r,X")) | |
5586 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 5587 | "" |
599aedd9 | 5588 | "#" |
52e12ad0 | 5589 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5590 | |
599aedd9 RH |
5591 | (define_split |
5592 | [(set (match_operand 0 "" "") | |
5593 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5594 | (const_int 1))) | |
5595 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5596 | (clobber (match_scratch:DI 3 "")) | |
5597 | (clobber (match_scratch:DI 4 ""))] | |
5598 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5599 | [(const_int 0)] | |
5600 | { | |
5601 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5602 | operands[4], true, false); | |
5603 | DONE; | |
5604 | }) | |
5605 | ||
5606 | (define_split | |
5607 | [(set (match_operand 0 "" "") | |
5608 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5609 | (const_int 1))) | |
5610 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5611 | (clobber (match_scratch:DI 3 "")) | |
5612 | (clobber (match_scratch:DI 4 ""))] | |
5613 | "reload_completed" | |
5614 | [(const_int 0)] | |
5615 | { | |
5616 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5617 | operands[4], false, false); | |
5618 | DONE; | |
5619 | }) | |
5620 | ||
5621 | (define_insn_and_split "sibcall_gp" | |
5622 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) | |
5623 | (const_int 1)) | |
5624 | (clobber (match_scratch:DI 1 "=&r,X")) | |
5625 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 5626 | "" |
599aedd9 RH |
5627 | "#" |
5628 | "reload_completed" | |
5629 | [(const_int 0)] | |
5630 | { | |
5631 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
5632 | operands[2], true, true); | |
5633 | DONE; | |
5634 | } | |
52e12ad0 | 5635 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 5636 | |
c65ebc55 JW |
5637 | (define_insn "return_internal" |
5638 | [(return) | |
5639 | (use (match_operand:DI 0 "register_operand" "b"))] | |
5640 | "" | |
5641 | "br.ret.sptk.many %0" | |
52e12ad0 | 5642 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5643 | |
5644 | (define_insn "return" | |
5645 | [(return)] | |
5646 | "ia64_direct_return ()" | |
5647 | "br.ret.sptk.many rp" | |
52e12ad0 | 5648 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 5649 | |
6b6c1201 | 5650 | (define_insn "*return_true" |
c65ebc55 | 5651 | [(set (pc) |
6b6c1201 | 5652 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5653 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5654 | (const_int 0)]) |
c65ebc55 JW |
5655 | (return) |
5656 | (pc)))] | |
5657 | "ia64_direct_return ()" | |
13da91fd | 5658 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 5659 | [(set_attr "itanium_class" "br") |
e5bde68a | 5660 | (set_attr "predicable" "no")]) |
c65ebc55 | 5661 | |
6b6c1201 | 5662 | (define_insn "*return_false" |
c65ebc55 | 5663 | [(set (pc) |
6b6c1201 | 5664 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5665 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5666 | (const_int 0)]) |
c65ebc55 JW |
5667 | (pc) |
5668 | (return)))] | |
5669 | "ia64_direct_return ()" | |
13da91fd | 5670 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 5671 | [(set_attr "itanium_class" "br") |
e5bde68a | 5672 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5673 | |
5674 | (define_insn "jump" | |
5675 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
5676 | "" | |
5677 | "br %l0" | |
52e12ad0 | 5678 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5679 | |
5680 | (define_insn "indirect_jump" | |
5681 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
5682 | "" | |
5683 | "br %0" | |
52e12ad0 | 5684 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5685 | |
5686 | (define_expand "tablejump" | |
340f7e7c RH |
5687 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
5688 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 5689 | "" |
c65ebc55 | 5690 | { |
340f7e7c RH |
5691 | rtx op0 = operands[0]; |
5692 | rtx addr; | |
5693 | ||
5694 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
5695 | element into a register without bothering to see whether that | |
5696 | is necessary given the operand predicate. Check for MEM just | |
5697 | in case someone fixes this. */ | |
5698 | if (GET_CODE (op0) == MEM) | |
5699 | addr = XEXP (op0, 0); | |
5700 | else | |
5701 | { | |
5702 | /* Otherwise, cheat and guess that the previous insn in the | |
5703 | stream was the memory load. Grab the address from that. | |
5704 | Note we have to momentarily pop out of the sequence started | |
5705 | by the insn-emit wrapper in order to grab the last insn. */ | |
5706 | rtx last, set; | |
5707 | ||
5708 | end_sequence (); | |
5709 | last = get_last_insn (); | |
5710 | start_sequence (); | |
5711 | set = single_set (last); | |
5712 | ||
e820471b NS |
5713 | gcc_assert (rtx_equal_p (SET_DEST (set), op0) |
5714 | && GET_CODE (SET_SRC (set)) == MEM); | |
340f7e7c | 5715 | addr = XEXP (SET_SRC (set), 0); |
e820471b | 5716 | gcc_assert (!rtx_equal_p (addr, op0)); |
340f7e7c | 5717 | } |
c65ebc55 | 5718 | |
340f7e7c RH |
5719 | /* Jump table elements are stored pc-relative. That is, a displacement |
5720 | from the entry to the label. Thus to convert to an absolute address | |
5721 | we add the address of the memory from which the value is loaded. */ | |
5722 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
5723 | NULL_RTX, 1, OPTAB_DIRECT); | |
5724 | }) | |
c65ebc55 | 5725 | |
340f7e7c | 5726 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
5727 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
5728 | (use (label_ref (match_operand 1 "" "")))] | |
5729 | "" | |
5730 | "br %0" | |
52e12ad0 | 5731 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5732 | |
5733 | \f | |
5734 | ;; :::::::::::::::::::: | |
5735 | ;; :: | |
5736 | ;; :: Prologue and Epilogue instructions | |
5737 | ;; :: | |
5738 | ;; :::::::::::::::::::: | |
5739 | ||
5740 | (define_expand "prologue" | |
5741 | [(const_int 1)] | |
5742 | "" | |
c65ebc55 JW |
5743 | { |
5744 | ia64_expand_prologue (); | |
5745 | DONE; | |
1d5d7a21 | 5746 | }) |
c65ebc55 JW |
5747 | |
5748 | (define_expand "epilogue" | |
2ed4af6f RH |
5749 | [(return)] |
5750 | "" | |
2ed4af6f RH |
5751 | { |
5752 | ia64_expand_epilogue (0); | |
5753 | DONE; | |
1d5d7a21 | 5754 | }) |
2ed4af6f RH |
5755 | |
5756 | (define_expand "sibcall_epilogue" | |
5757 | [(return)] | |
c65ebc55 | 5758 | "" |
c65ebc55 | 5759 | { |
2ed4af6f | 5760 | ia64_expand_epilogue (1); |
c65ebc55 | 5761 | DONE; |
1d5d7a21 | 5762 | }) |
c65ebc55 JW |
5763 | |
5764 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
5765 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
5766 | ||
5767 | (define_insn "prologue_allocate_stack" | |
5768 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
5769 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 5770 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 5771 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
5772 | (match_dup 3))] |
5773 | "" | |
5774 | "@ | |
1d5d7a21 RH |
5775 | add %0 = %1, %2 |
5776 | adds %0 = %2, %1 | |
5777 | addl %0 = %2, %1" | |
52e12ad0 | 5778 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
5779 | |
5780 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
5781 | ;; stack accesses. This is similar to movdi plus the extra set. | |
5782 | ||
5783 | (define_insn "epilogue_deallocate_stack" | |
5784 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5785 | (match_operand:DI 1 "register_operand" "+r")) | |
5786 | (set (match_dup 1) (match_dup 1))] | |
5787 | "" | |
5788 | "mov %0 = %1" | |
52e12ad0 | 5789 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 5790 | |
1d5d7a21 RH |
5791 | ;; As USE insns aren't meaningful after reload, this is used instead |
5792 | ;; to prevent deleting instructions setting registers for EH handling | |
5793 | (define_insn "prologue_use" | |
5794 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
5795 | UNSPEC_PROLOGUE_USE)] | |
5796 | "" | |
5797 | "" | |
5798 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
5799 | (set_attr "predicable" "no") |
5800 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 5801 | |
c65ebc55 JW |
5802 | ;; Allocate a new register frame. |
5803 | ||
5804 | (define_insn "alloc" | |
5805 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5806 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
5807 | (use (match_operand:DI 1 "const_int_operand" "i")) |
5808 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
5809 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
5810 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
5811 | "" | |
5812 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 5813 | [(set_attr "itanium_class" "syst_m0") |
68e11b42 JW |
5814 | (set_attr "predicable" "no") |
5815 | (set_attr "first_insn" "yes")]) | |
c65ebc55 | 5816 | |
97e242b0 RH |
5817 | ;; Modifies ar.unat |
5818 | (define_expand "gr_spill" | |
870f9ec0 RH |
5819 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
5820 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
5821 | (match_operand:DI 2 "const_int_operand" "")] |
5822 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5823 | (clobber (match_dup 3))])] |
97e242b0 | 5824 | "" |
870f9ec0 | 5825 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5826 | |
870f9ec0 | 5827 | (define_insn "gr_spill_internal" |
b6fb7d46 | 5828 | [(set (match_operand:DI 0 "destination_operand" "=m") |
870f9ec0 | 5829 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
5830 | (match_operand:DI 2 "const_int_operand" "")] |
5831 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5832 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5833 | "" |
2130b7fb | 5834 | { |
1d5d7a21 RH |
5835 | /* Note that we use a C output pattern here to avoid the predicate |
5836 | being automatically added before the .mem.offset directive. */ | |
5837 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
5838 | } | |
52e12ad0 | 5839 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 5840 | |
97e242b0 RH |
5841 | ;; Reads ar.unat |
5842 | (define_expand "gr_restore" | |
870f9ec0 RH |
5843 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
5844 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
5845 | (match_operand:DI 2 "const_int_operand" "")] |
5846 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5847 | (use (match_dup 3))])] |
97e242b0 | 5848 | "" |
870f9ec0 | 5849 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5850 | |
870f9ec0 | 5851 | (define_insn "gr_restore_internal" |
c65ebc55 | 5852 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 5853 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
5854 | (match_operand:DI 2 "const_int_operand" "")] |
5855 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5856 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5857 | "" |
1d5d7a21 | 5858 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 5859 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
5860 | |
5861 | (define_insn "fr_spill" | |
b6fb7d46 | 5862 | [(set (match_operand:XF 0 "destination_operand" "=m") |
02befdf4 | 5863 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] |
086c0f96 | 5864 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
5865 | "" |
5866 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 5867 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
5868 | |
5869 | (define_insn "fr_restore" | |
02befdf4 ZW |
5870 | [(set (match_operand:XF 0 "register_operand" "=f") |
5871 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 5872 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
5873 | "" |
5874 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 5875 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 5876 | |
0024a804 JW |
5877 | ;; ??? The explicit stop is not ideal. It would be better if |
5878 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5879 | ;; fixed later. This avoids an RSE DV. | |
5880 | ||
0c96007e AM |
5881 | (define_insn "bsp_value" |
5882 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5883 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 5884 | "" |
582d11e6 JW |
5885 | "* |
5886 | { | |
5887 | return \";;\;%,mov %0 = ar.bsp\"; | |
5888 | }" | |
52e12ad0 | 5889 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
5890 | |
5891 | (define_insn "set_bsp" | |
086c0f96 RH |
5892 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
5893 | UNSPECV_SET_BSP)] | |
0c96007e | 5894 | "" |
1d5d7a21 RH |
5895 | "flushrs |
5896 | mov r19=ar.rsc | |
5897 | ;; | |
5898 | and r19=0x1c,r19 | |
5899 | ;; | |
5900 | mov ar.rsc=r19 | |
5901 | ;; | |
5902 | mov ar.bspstore=%0 | |
5903 | ;; | |
5904 | or r19=0x3,r19 | |
5905 | ;; | |
5906 | loadrs | |
5907 | invala | |
5908 | ;; | |
5909 | mov ar.rsc=r19" | |
52e12ad0 | 5910 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 5911 | (set_attr "predicable" "no")]) |
ce152ef8 | 5912 | |
0024a804 JW |
5913 | ;; ??? The explicit stops are not ideal. It would be better if |
5914 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5915 | ;; fixed later. This avoids an RSE DV. | |
5916 | ||
ce152ef8 | 5917 | (define_insn "flushrs" |
086c0f96 | 5918 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 5919 | "" |
0024a804 | 5920 | ";;\;flushrs\;;;" |
582d11e6 JW |
5921 | [(set_attr "itanium_class" "rse_m") |
5922 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
5923 | \f |
5924 | ;; :::::::::::::::::::: | |
5925 | ;; :: | |
5926 | ;; :: Miscellaneous instructions | |
5927 | ;; :: | |
5928 | ;; :::::::::::::::::::: | |
5929 | ||
839a4992 | 5930 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
5931 | ;; be emitting ";;" to force a break in the instruction packing. |
5932 | ||
5933 | ;; No operation, needed in case the user uses -g but not -O. | |
5934 | (define_insn "nop" | |
5935 | [(const_int 0)] | |
5936 | "" | |
5937 | "nop 0" | |
30028c85 | 5938 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 5939 | |
2130b7fb BS |
5940 | (define_insn "nop_m" |
5941 | [(const_int 1)] | |
5942 | "" | |
5943 | "nop.m 0" | |
5944 | [(set_attr "itanium_class" "nop_m")]) | |
5945 | ||
5946 | (define_insn "nop_i" | |
5947 | [(const_int 2)] | |
5948 | "" | |
5949 | "nop.i 0" | |
5950 | [(set_attr "itanium_class" "nop_i")]) | |
5951 | ||
5952 | (define_insn "nop_f" | |
5953 | [(const_int 3)] | |
5954 | "" | |
5955 | "nop.f 0" | |
5956 | [(set_attr "itanium_class" "nop_f")]) | |
5957 | ||
5958 | (define_insn "nop_b" | |
5959 | [(const_int 4)] | |
5960 | "" | |
5961 | "nop.b 0" | |
5962 | [(set_attr "itanium_class" "nop_b")]) | |
5963 | ||
5964 | (define_insn "nop_x" | |
5965 | [(const_int 5)] | |
5966 | "" | |
5967 | "" | |
fa978426 AS |
5968 | [(set_attr "itanium_class" "nop_x") |
5969 | (set_attr "empty" "yes")]) | |
2130b7fb | 5970 | |
30028c85 VM |
5971 | ;; The following insn will be never generated. It is used only by |
5972 | ;; insn scheduler to change state before advancing cycle. | |
5973 | (define_insn "pre_cycle" | |
5974 | [(const_int 6)] | |
5975 | "" | |
5976 | "" | |
5977 | [(set_attr "itanium_class" "pre_cycle")]) | |
5978 | ||
2130b7fb | 5979 | (define_insn "bundle_selector" |
086c0f96 | 5980 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 5981 | "" |
1d5d7a21 | 5982 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
5983 | [(set_attr "itanium_class" "ignore") |
5984 | (set_attr "predicable" "no")]) | |
5985 | ||
c65ebc55 JW |
5986 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
5987 | ;; point. | |
5988 | (define_insn "blockage" | |
086c0f96 | 5989 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
5990 | "" |
5991 | "" | |
52e12ad0 | 5992 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 5993 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5994 | |
5995 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
5996 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
5997 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
5998 | "" |
5999 | ";;" | |
52e12ad0 | 6000 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
6001 | (set_attr "predicable" "no") |
6002 | (set_attr "empty" "yes")]) | |
c65ebc55 | 6003 | |
26406018 RH |
6004 | (define_expand "trap" |
6005 | [(trap_if (const_int 1) (const_int 0))] | |
6006 | "" | |
6007 | "") | |
6008 | ||
6009 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
6010 | ;; produces worse code that setting the slot type to A. | |
6011 | ||
6012 | (define_insn "*trap" | |
6013 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
6014 | "" | |
6015 | "break %0" | |
048d0d36 | 6016 | [(set_attr "itanium_class" "chk_s_i")]) |
26406018 RH |
6017 | |
6018 | (define_expand "conditional_trap" | |
6019 | [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] | |
6020 | "" | |
6021 | { | |
6022 | operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode); | |
6023 | }) | |
6024 | ||
6025 | (define_insn "*conditional_trap" | |
6026 | [(trap_if (match_operator 0 "predicate_operator" | |
6027 | [(match_operand:BI 1 "register_operand" "c") | |
6028 | (const_int 0)]) | |
6029 | (match_operand 2 "const_int_operand" ""))] | |
6030 | "" | |
5cf63e3f | 6031 | "(%J0) break %2" |
048d0d36 | 6032 | [(set_attr "itanium_class" "chk_s_i") |
26406018 RH |
6033 | (set_attr "predicable" "no")]) |
6034 | ||
f12f25a7 | 6035 | (define_insn "break_f" |
086c0f96 | 6036 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
6037 | "" |
6038 | "break.f 0" | |
6039 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
6040 | |
6041 | (define_insn "prefetch" | |
6042 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
6043 | (match_operand:DI 1 "const_int_operand" "n") | |
6044 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6045 | "" | |
6046 | { | |
6047 | static const char * const alt[2][4] = { | |
b3656137 | 6048 | { |
92cbea22 L |
6049 | "%,lfetch.nta [%0]", |
6050 | "%,lfetch.nt1 [%0]", | |
6051 | "%,lfetch.nt2 [%0]", | |
6052 | "%,lfetch [%0]" | |
b3656137 KG |
6053 | }, |
6054 | { | |
92cbea22 L |
6055 | "%,lfetch.excl.nta [%0]", |
6056 | "%,lfetch.excl.nt1 [%0]", | |
6057 | "%,lfetch.excl.nt2 [%0]", | |
6058 | "%,lfetch.excl [%0]" | |
b3656137 | 6059 | } |
44eca121 JJ |
6060 | }; |
6061 | int i = (INTVAL (operands[1])); | |
6062 | int j = (INTVAL (operands[2])); | |
6063 | ||
e820471b NS |
6064 | gcc_assert (i == 0 || i == 1); |
6065 | gcc_assert (j >= 0 && j <= 3); | |
44eca121 JJ |
6066 | return alt[i][j]; |
6067 | } | |
6068 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
6069 | \f |
6070 | ;; Non-local goto support. | |
6071 | ||
6072 | (define_expand "save_stack_nonlocal" | |
6073 | [(use (match_operand:OI 0 "memory_operand" "")) | |
6074 | (use (match_operand:DI 1 "register_operand" ""))] | |
6075 | "" | |
c65ebc55 JW |
6076 | { |
6077 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
6078 | \"__ia64_save_stack_nonlocal\"), | |
6079 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
6080 | operands[1], Pmode); | |
6081 | DONE; | |
1d5d7a21 | 6082 | }) |
c65ebc55 JW |
6083 | |
6084 | (define_expand "nonlocal_goto" | |
6085 | [(use (match_operand 0 "general_operand" "")) | |
6086 | (use (match_operand 1 "general_operand" "")) | |
6087 | (use (match_operand 2 "general_operand" "")) | |
6088 | (use (match_operand 3 "general_operand" ""))] | |
6089 | "" | |
c65ebc55 | 6090 | { |
c65ebc55 | 6091 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 6092 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 6093 | operands[1], Pmode, |
c65ebc55 | 6094 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 6095 | operands[3], Pmode); |
c65ebc55 JW |
6096 | emit_barrier (); |
6097 | DONE; | |
1d5d7a21 | 6098 | }) |
c65ebc55 | 6099 | |
39a5cfa4 SE |
6100 | (define_insn_and_split "nonlocal_goto_receiver" |
6101 | [(unspec_volatile [(const_int 0)] UNSPECV_GOTO_RECEIVER)] | |
6102 | "" | |
6103 | "#" | |
6104 | "reload_completed" | |
6105 | [(const_int 0)] | |
6106 | { | |
6107 | ia64_reload_gp (); | |
6108 | DONE; | |
6109 | }) | |
6110 | ||
b39eb2f9 RH |
6111 | (define_insn_and_split "builtin_setjmp_receiver" |
6112 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 6113 | "" |
b39eb2f9 RH |
6114 | "#" |
6115 | "reload_completed" | |
6116 | [(const_int 0)] | |
97e242b0 | 6117 | { |
599aedd9 | 6118 | ia64_reload_gp (); |
c65ebc55 | 6119 | DONE; |
1d5d7a21 | 6120 | }) |
c65ebc55 | 6121 | |
0c96007e AM |
6122 | (define_expand "eh_epilogue" |
6123 | [(use (match_operand:DI 0 "register_operand" "r")) | |
6124 | (use (match_operand:DI 1 "register_operand" "r")) | |
6125 | (use (match_operand:DI 2 "register_operand" "r"))] | |
6126 | "" | |
0c96007e AM |
6127 | { |
6128 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
6129 | rtx sp = gen_rtx_REG (Pmode, 9); | |
6130 | ||
6131 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
6132 | { | |
6133 | emit_move_insn (bsp, operands[0]); | |
6134 | operands[0] = bsp; | |
6135 | } | |
6136 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
6137 | { | |
6138 | emit_move_insn (sp, operands[2]); | |
6139 | operands[2] = sp; | |
6140 | } | |
c41c1387 RS |
6141 | emit_use (sp); |
6142 | emit_use (bsp); | |
0c96007e AM |
6143 | |
6144 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
6145 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 6146 | }) |
9525c690 JW |
6147 | \f |
6148 | ;; Builtin apply support. | |
6149 | ||
6150 | (define_expand "restore_stack_nonlocal" | |
6151 | [(use (match_operand:DI 0 "register_operand" "")) | |
6152 | (use (match_operand:OI 1 "memory_operand" ""))] | |
6153 | "" | |
9525c690 JW |
6154 | { |
6155 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 6156 | "__ia64_restore_stack_nonlocal"), |
9525c690 JW |
6157 | 0, VOIDmode, 1, |
6158 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
6159 | DONE; | |
1d5d7a21 | 6160 | }) |
9525c690 | 6161 | |
e5bde68a RH |
6162 | \f |
6163 | ;; Predication. | |
6164 | ||
6165 | (define_cond_exec | |
6166 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 6167 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
6168 | (const_int 0)])] |
6169 | "" | |
6170 | "(%J0)") | |
3b572406 RH |
6171 | |
6172 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 6173 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 6174 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 6175 | "" |
054451ea | 6176 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 6177 | [(set_attr "itanium_class" "ignore") |
3b572406 | 6178 | (set_attr "predicable" "no")]) |
ca3920ad JW |
6179 | |
6180 | (define_insn "safe_across_calls_all" | |
086c0f96 | 6181 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
6182 | "" |
6183 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 6184 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6185 | (set_attr "predicable" "no")]) |
6186 | ||
6187 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 6188 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 6189 | "" |
ca3920ad | 6190 | { |
1bc7c5b6 | 6191 | emit_safe_across_calls (); |
1d5d7a21 RH |
6192 | return ""; |
6193 | } | |
52e12ad0 | 6194 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6195 | (set_attr "predicable" "no")]) |
6196 | ||
27a9b99d | 6197 | ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit |
6dd12198 SE |
6198 | ;; pointer. This is used by the HP-UX 32 bit mode. |
6199 | ||
6200 | (define_insn "ptr_extend" | |
6201 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
6202 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
6203 | UNSPEC_ADDP4))] | |
6dd12198 SE |
6204 | "" |
6205 | "addp4 %0 = 0,%1" | |
6206 | [(set_attr "itanium_class" "ialu")]) | |
6207 | ||
e206a74f SE |
6208 | ;; |
6209 | ;; Optimizations for ptr_extend | |
6210 | ||
36c216e5 | 6211 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
6212 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6213 | (unspec:DI | |
6214 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
6215 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 6216 | UNSPEC_ADDP4))] |
08744705 | 6217 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6218 | "addp4 %0 = %2, %1" |
6219 | [(set_attr "itanium_class" "ialu")]) | |
6220 | ||
6221 | (define_insn "*ptr_extend_plus_2" | |
6222 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
6223 | (unspec:DI | |
6224 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
6225 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 6226 | UNSPEC_ADDP4))] |
08744705 | 6227 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6228 | "addp4 %0 = %1, %2" |
6229 | [(set_attr "itanium_class" "ialu")]) | |
f61134e8 | 6230 | |
d26afa4f SE |
6231 | ;; |
6232 | ;; Get instruction pointer | |
6233 | ||
6234 | (define_insn "ip_value" | |
6235 | [(set (match_operand:DI 0 "register_operand" "=r") | |
6236 | (pc))] | |
6237 | "" | |
6238 | "mov %0 = ip" | |
6107a6ae | 6239 | [(set_attr "itanium_class" "frbr")]) |
d26afa4f | 6240 | |
f61134e8 RH |
6241 | ;; Vector operations |
6242 | (include "vect.md") | |
af795c3c RH |
6243 | ;; Atomic operations |
6244 | (include "sync.md") | |
4883241c SE |
6245 | ;; New division operations |
6246 | (include "div.md") |