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c65ebc55 1;; IA-64 Machine description template
e65271be 2;; Copyright (C) 1999, 2000 Free Software Foundation, Inc.
c65ebc55
JW		 3;; Contributed by James E. Wilson <wilson@cygnus.com> and
4;; David Mosberger <davidm@hpl.hp.com>.
5
6;; This file is part of GNU CC.
7
8;; GNU CC is free software; you can redistribute it and/or modify
9;; it under the terms of the GNU General Public License as published by
10;; the Free Software Foundation; either version 2, or (at your option)
11;; any later version.
12
13;; GNU CC is distributed in the hope that it will be useful,
14;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16;; GNU General Public License for more details.
17
18;; You should have received a copy of the GNU General Public License
19;; along with GNU CC; see the file COPYING. If not, write to
20;; the Free Software Foundation, 59 Temple Place - Suite 330,
21;; Boston, MA 02111-1307, USA.
22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
c65ebc55
JW		 25;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
26;; reload. This will be fixed once scheduling support is turned on.
27
28;; ??? Optimize for post-increment addressing modes.
29
30;; ??? fselect is not supported, because there is no integer register
31;; equivalent.
32
33;; ??? fp abs/min/max instructions may also work for integer values.
34
35;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
36;; it assumes the operand is a register and takes REGNO of it without checking.
37
38;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
39;; it assumes the operand is a register and takes REGNO of it without checking.
40
41;; ??? Go through list of documented named patterns and look for more to
42;; implement.
43
44;; ??? Go through instruction manual and look for more instructions that
45;; can be emitted.
46
47;; ??? Add function unit scheduling info for Itanium (TM) processor.
48
26102535
RH		 49;; ??? Need a better way to describe alternate fp status registers.
50
e5bde68a
RH		 51;; Unspec usage:
52;;
53;; unspec:
54;; 1 gr_spill
55;; 2 gr_restore
56;; 3 fr_spill
57;; 4 fr_restore
655f2eb9 58;; 5 recip_approx
f2f90c63 59;; 7 pred_rel_mutex
e5bde68a 60;; 8 popcnt
2ed4af6f 61;; 9 pic call
97e242b0 62;; 12 mf
e5bde68a 63;; 13 cmpxchg_acq
e5bde68a
RH		 64;; 19 fetchadd_acq
65;; 20 bsp_value
ce152ef8 66;; 21 flushrs
2130b7fb
BS		 67;; 22 bundle selector
68;; 23 cycle display
e5bde68a
RH		 69;;
70;; unspec_volatile:
71;; 0 alloc
72;; 1 blockage
73;; 2 insn_group_barrier
f12f25a7 74;; 3 break
e5bde68a 75;; 5 set_bsp
ca3920ad
JW		 76;; 8 pred.safe_across_calls all
77;; 9 pred.safe_across_calls normal
c65ebc55
JW		 78\f
79;; ::::::::::::::::::::
80;; ::
81;; :: Attributes
82;; ::
83;; ::::::::::::::::::::
84
85;; Instruction type. This primarily determines how instructions can be
86;; packed in bundles, and secondarily affects scheduling to function units.
87
88;; A alu, can go in I or M syllable of a bundle
89;; I integer
90;; M memory
91;; F floating-point
92;; B branch
93;; L long immediate, takes two syllables
94;; S stop bit
95
96;; ??? Should not have any pattern with type unknown. Perhaps add code to
97;; check this in md_reorg? Currently use unknown for patterns which emit
98;; multiple instructions, patterns which emit 0 instructions, and patterns
99;; which emit instruction that can go in any slot (e.g. nop).
100
2130b7fb 101(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,nop_i,nop_m,nop_x"
52e12ad0
BS		 102 (const_string "unknown"))
103
2130b7fb
BS		 104;; chk_s has an I and an M form; use type A for convenience.
105(define_attr "type" "unknown,A,I,M,F,B,L,X,S"
106 (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M")
52e12ad0
BS		 107 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
108 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
2130b7fb
BS		 109 (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A")
110 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
111 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
52e12ad0
BS		 112 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
113 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
2130b7fb
BS		 114 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
115 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
52e12ad0 116 (eq_attr "itanium_class" "stop_bit") (const_string "S")
2130b7fb 117 (eq_attr "itanium_class" "nop_x") (const_string "X")
52e12ad0
BS		 118 (eq_attr "itanium_class" "long_i") (const_string "L")]
119 (const_string "unknown")))
c65ebc55 120
2130b7fb
BS		 121(define_attr "itanium_requires_unit0" "no,yes"
122 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
123 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
124 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
125 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
126 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
127 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
128 (const_string "no")))
129
e5bde68a
RH		 130;; Predication. True iff this instruction can be predicated.
131
132(define_attr "predicable" "no,yes" (const_string "yes"))
133
c65ebc55
JW		 134\f
135;; ::::::::::::::::::::
136;; ::
137;; :: Function Units
138;; ::
139;; ::::::::::::::::::::
140
2130b7fb
BS		 141;; We define 6 "dummy" functional units. All the real work to decide which
142;; insn uses which unit is done by our MD_SCHED_REORDER hooks. We only
143;; have to ensure here that there are enough copies of the dummy unit so
144;; that the scheduler doesn't get confused by MD_SCHED_REORDER.
145;; Other than the 6 dummies for normal insns, we also add a single dummy unit
146;; for stop bits.
147
148(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "br") 0 0)
149(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "scall") 0 0)
150(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcmp") 2 0)
151(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcvtfx") 7 0)
152(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fld") 9 0)
153(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmac") 5 0)
154(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmisc") 5 0)
155
156;; There is only one insn `mov = ar.bsp' for frar_i:
157(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_i") 13 0)
158;; There is only ony insn `mov = ar.unat' for frar_m:
159(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_m") 6 0)
160(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frbr") 2 0)
161(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frfr") 2 0)
162(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frpr") 2 0)
163
164(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ialu") 1 0)
165(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "icmp") 1 0)
166(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ilog") 1 0)
167(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ishf") 1 0)
168(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ld") 2 0)
169(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "long_i") 1 0)
170(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmmul") 2 0)
171(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshf") 2 0)
172(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshfi") 2 0)
173
174;; Now we have only one insn (flushrs) of such class. We assume that flushrs
175;; is the 1st syllable of the bundle after stop bit.
176(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "rse_m") 0 0)
177(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "sem") 11 0)
178(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "stf") 1 0)
179(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "st") 1 0)
180(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m0") 1 0)
181;; Now we use only one insn `mf'. Therfore latency time is set up to 0.
182(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m") 0 0)
183(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tbit") 1 0)
184
185;; There is only one insn `mov ar.pfs =' for toar_i therefore we use
186;; latency time equal to 0:
187(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_i") 0 0)
188;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m:
189(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_m") 5 0)
190(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tobr") 1 0)
191(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tofr") 9 0)
192(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "topr") 1 0)
193(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xmpy") 7 0)
194(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xtd") 1 0)
195
196(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_m") 0 0)
197(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_i") 0 0)
198(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_f") 0 0)
199(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_b") 0 0)
200(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_x") 0 0)
201
202(define_function_unit "stop_bit" 1 1 (eq_attr "itanium_class" "stop_bit") 0 0)
203(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ignore") 0 0)
204(define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "unknown") 0 0)
c65ebc55
JW		 205\f
206;; ::::::::::::::::::::
207;; ::
208;; :: Moves
209;; ::
210;; ::::::::::::::::::::
211
f2f90c63
RH		 212;; Set of a single predicate register. This is only used to implement
213;; pr-to-pr move and complement.
214
215(define_insn "*movcci"
216 [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
217 (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
218 ""
219 "@
220 cmp.ne %0, p0 = r0, r0
221 cmp.eq %0, p0 = r0, r0
222 (%1) cmp.eq.unc %0, p0 = r0, r0"
52e12ad0 223 [(set_attr "itanium_class" "icmp")
f2f90c63
RH		 224 (set_attr "predicable" "no")])
225
226(define_insn "movbi"
cd5c4048
RH		 227 [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
228 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
f2f90c63
RH		 229 ""
230 "@
231 cmp.ne %0, %I0 = r0, r0
232 cmp.eq %0, %I0 = r0, r0
233 #
234 #
235 tbit.nz %0, %I0 = %1, 0
236 adds %0 = %1, r0
237 ld1%O1 %0 = %1%P1
cd5c4048
RH		 238 st1%Q0 %0 = %1%P0
239 mov %0 = %1"
52e12ad0 240 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
f2f90c63
RH		 241
242(define_split
243 [(set (match_operand:BI 0 "register_operand" "")
244 (match_operand:BI 1 "register_operand" ""))]
245 "reload_completed
246 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
247 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
248 [(cond_exec (ne (match_dup 1) (const_int 0))
249 (set (match_dup 0) (const_int 1)))
250 (cond_exec (eq (match_dup 1) (const_int 0))
251 (set (match_dup 0) (const_int 0)))]
252 "")
253
254(define_split
255 [(set (match_operand:BI 0 "register_operand" "")
256 (match_operand:BI 1 "register_operand" ""))]
257 "reload_completed
258 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
259 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
260 [(set (match_dup 2) (match_dup 4))
261 (set (match_dup 3) (match_dup 5))
262 (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
263 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
264 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
265 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
266 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
267
c65ebc55
JW		 268(define_expand "movqi"
269 [(set (match_operand:QI 0 "general_operand" "")
270 (match_operand:QI 1 "general_operand" ""))]
271 ""
272 "
273{
274 if (! reload_in_progress && ! reload_completed
557b9df5
RH		 275 && ! ia64_move_ok (operands[0], operands[1]))
276 operands[1] = force_reg (QImode, operands[1]);
c65ebc55
JW		 277}")
278
279(define_insn "*movqi_internal"
4b983fdc
RH		 280 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
281 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
aebf2462 282 "ia64_move_ok (operands[0], operands[1])"
c65ebc55 283 "@
13da91fd 284 mov %0 = %r1
c65ebc55
JW		 285 addl %0 = %1, r0
286 ld1%O1 %0 = %1%P1
13da91fd 287 st1%Q0 %0 = %r1%P0
c65ebc55 288 getf.sig %0 = %1
13da91fd
RH		 289 setf.sig %0 = %r1
290 mov %0 = %1"
52e12ad0 291 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
c65ebc55
JW		 292
293(define_expand "movhi"
294 [(set (match_operand:HI 0 "general_operand" "")
295 (match_operand:HI 1 "general_operand" ""))]
296 ""
297 "
298{
299 if (! reload_in_progress && ! reload_completed
557b9df5
RH		 300 && ! ia64_move_ok (operands[0], operands[1]))
301 operands[1] = force_reg (HImode, operands[1]);
c65ebc55
JW		 302}")
303
304(define_insn "*movhi_internal"
4b983fdc
RH		 305 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
306 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
aebf2462 307 "ia64_move_ok (operands[0], operands[1])"
c65ebc55 308 "@
13da91fd 309 mov %0 = %r1
c65ebc55
JW		 310 addl %0 = %1, r0
311 ld2%O1 %0 = %1%P1
13da91fd 312 st2%Q0 %0 = %r1%P0
c65ebc55 313 getf.sig %0 = %1
13da91fd
RH		 314 setf.sig %0 = %r1
315 mov %0 = %1"
52e12ad0 316 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
c65ebc55
JW		 317
318(define_expand "movsi"
319 [(set (match_operand:SI 0 "general_operand" "")
320 (match_operand:SI 1 "general_operand" ""))]
321 ""
322 "
323{
324 if (! reload_in_progress && ! reload_completed
557b9df5
RH		 325 && ! ia64_move_ok (operands[0], operands[1]))
326 operands[1] = force_reg (SImode, operands[1]);
c65ebc55
JW		 327}")
328
329(define_insn "*movsi_internal"
97e242b0 330 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
514f96e6 331 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
aebf2462 332 "ia64_move_ok (operands[0], operands[1])"
c65ebc55 333 "@
13da91fd 334 mov %0 = %r1
c65ebc55
JW		 335 addl %0 = %1, r0
336 movl %0 = %1
337 ld4%O1 %0 = %1%P1
13da91fd 338 st4%Q0 %0 = %r1%P0
c65ebc55 339 getf.sig %0 = %1
13da91fd 340 setf.sig %0 = %r1
97e242b0
RH		 341 mov %0 = %1
342 mov %0 = %1
343 mov %0 = %r1"
52e12ad0
BS		 344;; frar_m, toar_m ??? why not frar_i and toar_i
345 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
c65ebc55
JW		 346
347(define_expand "movdi"
348 [(set (match_operand:DI 0 "general_operand" "")
349 (match_operand:DI 1 "general_operand" ""))]
350 ""
351 "
352{
9a89adb8
RH		 353 if (! reload_in_progress && ! reload_completed
354 && ! ia64_move_ok (operands[0], operands[1]))
355 operands[1] = force_reg (DImode, operands[1]);
ec039e3c 356 if (! TARGET_NO_PIC && symbolic_operand (operands[1], DImode))
c65ebc55 357 {
9a89adb8
RH		 358 /* Before optimization starts, delay committing to any particular
359 type of PIC address load. If this function gets deferred, we
360 may acquire information that changes the value of the
361 sdata_symbolic_operand predicate. */
7c866fb5
JW		 362 /* But don't delay for function pointers. Loading a function address
363 actually loads the address of the descriptor not the function.
364 If we represent these as SYMBOL_REFs, then they get cse'd with
365 calls, and we end up with calls to the descriptor address instead of
366 calls to the function address. Functions are not candidates for
367 sdata anyways. */
368 if (rtx_equal_function_value_matters
369 && ! (GET_CODE (operands[1]) == SYMBOL_REF
370 && SYMBOL_REF_FLAG (operands[1])))
b5d37c6f 371 emit_insn (gen_movdi_symbolic (operands[0], operands[1], gen_reg_rtx (DImode)));
9a89adb8 372 else
b5d37c6f 373 ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
9b7bf67d 374 DONE;
c65ebc55 375 }
c65ebc55
JW		 376}")
377
9a89adb8
RH		 378;; This is used during early compilation to delay the decision on
379;; how to refer to a variable as long as possible. This is especially
380;; important between initial rtl generation and optimization for
381;; deferred functions, since we may acquire additional information
382;; on the variables used in the meantime.
383
ef375129
JW		 384;; ??? This causes us to lose REG_LABEL notes, because the insn splitter
385;; does not attempt to preserve any REG_NOTES on the input instruction.
386
9a89adb8
RH		 387(define_insn_and_split "movdi_symbolic"
388 [(set (match_operand:DI 0 "register_operand" "=r")
389 (match_operand:DI 1 "symbolic_operand" "s"))
b5d37c6f 390 (clobber (match_operand:DI 2 "register_operand" "+r"))
9a89adb8
RH		 391 (use (reg:DI 1))]
392 ""
393 "* abort ();"
394 ""
395 [(const_int 0)]
b5d37c6f 396 "ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE;")
9a89adb8 397
c65ebc55 398(define_insn "*movdi_internal"
4b983fdc 399 [(set (match_operand:DI 0 "destination_operand"
52e12ad0 400 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
4b983fdc 401 (match_operand:DI 1 "move_operand"
52e12ad0 402 "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
aebf2462 403 "ia64_move_ok (operands[0], operands[1])"
9b7bf67d
RH		 404 "*
405{
406 static const char * const alt[] = {
6f8aa100
RH		 407 \"%,mov %0 = %r1\",
408 \"%,addl %0 = %1, r0\",
409 \"%,movl %0 = %1\",
410 \"%,ld8%O1 %0 = %1%P1\",
411 \"%,st8%Q0 %0 = %r1%P0\",
412 \"%,getf.sig %0 = %1\",
413 \"%,setf.sig %0 = %r1\",
414 \"%,mov %0 = %1\",
415 \"%,ldf8 %0 = %1%P1\",
416 \"%,stf8 %0 = %1%P0\",
417 \"%,mov %0 = %1\",
5527bf14
RH		 418 \"%,mov %0 = %r1\",
419 \"%,mov %0 = %1\",
514f96e6
RH		 420 \"%,mov %0 = %1\",
421 \"%,mov %0 = %1\",
52e12ad0 422 \"%,mov %0 = %1\",
97e242b0
RH		 423 \"mov %0 = pr\",
424 \"mov pr = %1, -1\"
9b7bf67d
RH		 425 };
426
9b7bf67d
RH		 427 if (which_alternative == 2 && ! TARGET_NO_PIC
428 && symbolic_operand (operands[1], VOIDmode))
429 abort ();
430
431 return alt[which_alternative];
432}"
52e12ad0 433 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
c65ebc55 434
9b7bf67d
RH		 435(define_split
436 [(set (match_operand:DI 0 "register_operand" "")
437 (match_operand:DI 1 "symbolic_operand" ""))]
438 "reload_completed && ! TARGET_NO_PIC"
439 [(const_int 0)]
440 "
441{
b5d37c6f 442 ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
9b7bf67d
RH		 443 DONE;
444}")
445
c65ebc55
JW		 446(define_expand "load_fptr"
447 [(set (match_dup 2)
448 (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "")))
ec039e3c 449 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
c65ebc55
JW		 450 ""
451 "
452{
ec039e3c
RH		 453 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
454 operands[3] = gen_rtx_MEM (DImode, operands[2]);
455 RTX_UNCHANGING_P (operands[3]) = 1;
c65ebc55
JW		 456}")
457
458(define_insn "*load_fptr_internal1"
459 [(set (match_operand:DI 0 "register_operand" "=r")
460 (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))]
461 ""
462 "addl %0 = @ltoff(@fptr(%1)), gp"
52e12ad0 463 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 464
465(define_insn "load_gprel"
466 [(set (match_operand:DI 0 "register_operand" "=r")
467 (plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))]
468 ""
469 "addl %0 = @gprel(%1), gp"
52e12ad0 470 [(set_attr "itanium_class" "ialu")])
c65ebc55 471
59da9a7d
JW		 472(define_insn "gprel64_offset"
473 [(set (match_operand:DI 0 "register_operand" "=r")
474 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
475 ""
476 "movl %0 = @gprel(%1)"
52e12ad0 477 [(set_attr "itanium_class" "long_i")])
59da9a7d
JW		 478
479(define_expand "load_gprel64"
480 [(set (match_dup 2)
b5d37c6f 481 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3)))
59da9a7d 482 (set (match_operand:DI 0 "register_operand" "")
b5d37c6f 483 (plus:DI (match_dup 3) (match_dup 2)))]
59da9a7d 484 ""
ec039e3c
RH		 485 "
486{
487 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
b5d37c6f 488 operands[3] = pic_offset_table_rtx;
59da9a7d
JW		 489}")
490
c65ebc55 491(define_expand "load_symptr"
b5d37c6f
BS		 492 [(set (match_operand:DI 2 "register_operand" "")
493 (plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" "")))
dee4095a 494 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
c65ebc55
JW		 495 ""
496 "
497{
dee4095a 498 operands[3] = gen_rtx_MEM (DImode, operands[2]);
b5d37c6f 499 operands[4] = pic_offset_table_rtx;
dee4095a 500 RTX_UNCHANGING_P (operands[3]) = 1;
c65ebc55
JW		 501}")
502
503(define_insn "*load_symptr_internal1"
504 [(set (match_operand:DI 0 "register_operand" "=r")
ec039e3c 505 (plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "s")))]
c65ebc55
JW		 506 ""
507 "addl %0 = @ltoff(%1), gp"
52e12ad0 508 [(set_attr "itanium_class" "ialu")])
c65ebc55 509
3f622353
RH		 510;; With no offsettable memory references, we've got to have a scratch
511;; around to play with the second word.
512(define_expand "movti"
513 [(parallel [(set (match_operand:TI 0 "general_operand" "")
514 (match_operand:TI 1 "general_operand" ""))
515 (clobber (match_scratch:DI 2 ""))])]
516 ""
517 "
518{
519 if (! reload_in_progress && ! reload_completed
520 && ! ia64_move_ok (operands[0], operands[1]))
521 operands[1] = force_reg (TImode, operands[1]);
522}")
523
524(define_insn_and_split "*movti_internal"
525 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
526 (match_operand:TI 1 "general_operand" "ri,m,r"))
527 (clobber (match_scratch:DI 2 "=X,&r,&r"))]
528 "ia64_move_ok (operands[0], operands[1])"
529 "#"
530 "reload_completed"
531 [(const_int 0)]
532 "
533{
534 rtx adj1, adj2, in[2], out[2];
535 int first;
536
537 adj1 = ia64_split_timode (in, operands[1], operands[2]);
538 adj2 = ia64_split_timode (out, operands[0], operands[2]);
539
540 first = 0;
541 if (reg_overlap_mentioned_p (out[0], in[1]))
542 {
543 if (reg_overlap_mentioned_p (out[1], in[0]))
544 abort ();
545 first = 1;
546 }
547
548 if (adj1 && adj2)
549 abort ();
550 if (adj1)
551 emit_insn (adj1);
552 if (adj2)
553 emit_insn (adj2);
554 emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
555 emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
556 DONE;
557}"
52e12ad0 558 [(set_attr "itanium_class" "unknown")
3f622353 559 (set_attr "predicable" "no")])
e314e331 560
3f622353
RH		 561;; ??? SSA creates these. Can't allow memories since we don't have
562;; the scratch register. Fortunately combine will know how to add
563;; the clobber and scratch.
564(define_insn_and_split "*movti_internal_reg"
565 [(set (match_operand:TI 0 "register_operand" "=r")
566 (match_operand:TI 1 "nonmemory_operand" "ri"))]
567 ""
e314e331 568 "#"
3f622353
RH		 569 "reload_completed"
570 [(const_int 0)]
571 "
572{
573 rtx in[2], out[2];
574 int first;
575
576 ia64_split_timode (in, operands[1], NULL_RTX);
577 ia64_split_timode (out, operands[0], NULL_RTX);
578
579 first = 0;
580 if (reg_overlap_mentioned_p (out[0], in[1]))
581 {
582 if (reg_overlap_mentioned_p (out[1], in[0]))
583 abort ();
584 first = 1;
585 }
586
587 emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
588 emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
589 DONE;
590}"
52e12ad0 591 [(set_attr "itanium_class" "unknown")
e314e331
JW		 592 (set_attr "predicable" "no")])
593
3f622353
RH		 594(define_expand "reload_inti"
595 [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
596 (match_operand:TI 1 "" "m"))
60a3c181 597 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
3f622353
RH		 598 ""
599 "
600{
60a3c181
RH		 601 unsigned int s_regno = REGNO (operands[2]);
602 if (s_regno == REGNO (operands[0]))
603 s_regno += 1;
604 operands[2] = gen_rtx_REG (DImode, s_regno);
3f622353
RH		 605}")
606
607(define_expand "reload_outti"
608 [(parallel [(set (match_operand:TI 0 "" "=m")
609 (match_operand:TI 1 "register_operand" "r"))
60a3c181 610 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
3f622353
RH		 611 ""
612 "
613{
60a3c181
RH		 614 unsigned int s_regno = REGNO (operands[2]);
615 if (s_regno == REGNO (operands[1]))
616 s_regno += 1;
617 operands[2] = gen_rtx_REG (DImode, s_regno);
3f622353 618}")
e314e331 619
c65ebc55
JW		 620;; Floating Point Moves
621;;
622;; Note - Patterns for SF mode moves are compulsory, but
623;; patterns for DF are optional, as GCC can synthesise them.
624
625(define_expand "movsf"
626 [(set (match_operand:SF 0 "general_operand" "")
627 (match_operand:SF 1 "general_operand" ""))]
628 ""
629 "
630{
631 if (! reload_in_progress && ! reload_completed
557b9df5
RH		 632 && ! ia64_move_ok (operands[0], operands[1]))
633 operands[1] = force_reg (SFmode, operands[1]);
c65ebc55
JW		 634}")
635
c65ebc55 636(define_insn "*movsf_internal"
4b983fdc
RH		 637 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
638 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
aebf2462 639 "ia64_move_ok (operands[0], operands[1])"
c65ebc55
JW		 640 "@
641 mov %0 = %F1
642 ldfs %0 = %1%P1
643 stfs %0 = %F1%P0
644 getf.s %0 = %F1
645 setf.s %0 = %1
646 mov %0 = %1
13da91fd
RH		 647 ld4%O1 %0 = %1%P1
648 st4%Q0 %0 = %1%P0"
52e12ad0 649 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
c65ebc55
JW		 650
651(define_expand "movdf"
652 [(set (match_operand:DF 0 "general_operand" "")
653 (match_operand:DF 1 "general_operand" ""))]
654 ""
655 "
656{
657 if (! reload_in_progress && ! reload_completed
557b9df5
RH		 658 && ! ia64_move_ok (operands[0], operands[1]))
659 operands[1] = force_reg (DFmode, operands[1]);
c65ebc55
JW		 660}")
661
c65ebc55 662(define_insn "*movdf_internal"
4b983fdc
RH		 663 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
664 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
aebf2462 665 "ia64_move_ok (operands[0], operands[1])"
c65ebc55
JW		 666 "@
667 mov %0 = %F1
668 ldfd %0 = %1%P1
669 stfd %0 = %F1%P0
670 getf.d %0 = %F1
671 setf.d %0 = %1
13da91fd
RH		 672 mov %0 = %1
673 ld8%O1 %0 = %1%P1
674 st8%Q0 %0 = %1%P0"
52e12ad0 675 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
c65ebc55 676
3f622353
RH		 677;; With no offsettable memory references, we've got to have a scratch
678;; around to play with the second word if the variable winds up in GRs.
679(define_expand "movtf"
680 [(set (match_operand:TF 0 "general_operand" "")
681 (match_operand:TF 1 "general_operand" ""))]
23c108af 682 "INTEL_EXTENDED_IEEE_FORMAT"
e5bde68a
RH		 683 "
684{
3f622353
RH		 685 /* We must support TFmode loads into general registers for stdarg/vararg
686 and unprototyped calls. We split them into DImode loads for convenience.
687 We don't need TFmode stores from general regs, because a stdarg/vararg
688 routine does a block store to memory of unnamed arguments. */
689 if (GET_CODE (operands[0]) == REG
690 && GR_REGNO_P (REGNO (operands[0])))
691 {
692 /* We're hoping to transform everything that deals with TFmode
693 quantities and GR registers early in the compiler. */
694 if (no_new_pseudos)
695 abort ();
696
697 /* Struct to register can just use TImode instead. */
698 if ((GET_CODE (operands[1]) == SUBREG
699 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
700 || (GET_CODE (operands[1]) == REG
701 && GR_REGNO_P (REGNO (operands[1]))))
702 {
703 emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])),
704 SUBREG_REG (operands[1]));
705 DONE;
706 }
707
708 if (GET_CODE (operands[1]) == CONST_DOUBLE)
709 {
710 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])),
2bf47a10 711 operand_subword (operands[1], 0, 0, TFmode));
3f622353 712 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1),
2bf47a10 713 operand_subword (operands[1], 1, 0, TFmode));
3f622353
RH		 714 DONE;
715 }
716
717 /* If the quantity is in a register not known to be GR, spill it. */
718 if (register_operand (operands[1], TFmode))
719 operands[1] = spill_tfmode_operand (operands[1], 1);
720
721 if (GET_CODE (operands[1]) == MEM)
722 {
723 rtx out[2];
724
725 out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0]));
726 out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1);
727
728 emit_move_insn (out[0], change_address (operands[1], DImode, NULL));
729 emit_move_insn (out[1],
730 change_address (operands[1], DImode,
731 plus_constant (XEXP (operands[1], 0),
732 8)));
733 DONE;
734 }
735
736 abort ();
737 }
738
739 if (! reload_in_progress && ! reload_completed)
740 {
741 operands[0] = spill_tfmode_operand (operands[0], 0);
742 operands[1] = spill_tfmode_operand (operands[1], 0);
743
744 if (! ia64_move_ok (operands[0], operands[1]))
745 operands[1] = force_reg (TFmode, operands[1]);
746 }
e5bde68a
RH		 747}")
748
3b572406 749;; ??? There's no easy way to mind volatile acquire/release semantics.
75cdbeb8 750
3f622353
RH		 751(define_insn "*movtf_internal"
752 [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
753 (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
23c108af 754 "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])"
e5bde68a
RH		 755 "@
756 mov %0 = %F1
46b1ac3f
JW		 757 ldfe %0 = %1%P1
758 stfe %0 = %F1%P0"
52e12ad0 759 [(set_attr "itanium_class" "fmisc,fld,stf")])
c65ebc55
JW		 760\f
761;; ::::::::::::::::::::
762;; ::
763;; :: Conversions
764;; ::
765;; ::::::::::::::::::::
766
767;; Signed conversions from a smaller integer to a larger integer
768
769(define_insn "extendqidi2"
0551c32d
RH		 770 [(set (match_operand:DI 0 "gr_register_operand" "=r")
771 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
c65ebc55
JW		 772 ""
773 "sxt1 %0 = %1"
52e12ad0 774 [(set_attr "itanium_class" "xtd")])
c65ebc55
JW		 775
776(define_insn "extendhidi2"
0551c32d
RH		 777 [(set (match_operand:DI 0 "gr_register_operand" "=r")
778 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
c65ebc55
JW		 779 ""
780 "sxt2 %0 = %1"
52e12ad0 781 [(set_attr "itanium_class" "xtd")])
c65ebc55
JW		 782
783(define_insn "extendsidi2"
655f2eb9
RH		 784 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
785 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
c65ebc55
JW		 786 ""
787 "@
788 sxt4 %0 = %1
aebf2462 789 fsxt.r %0 = %1, %1"
52e12ad0 790 [(set_attr "itanium_class" "xtd,fmisc")])
c65ebc55
JW		 791
792;; Unsigned conversions from a smaller integer to a larger integer
793
794(define_insn "zero_extendqidi2"
0551c32d
RH		 795 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
796 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
c65ebc55
JW		 797 ""
798 "@
799 zxt1 %0 = %1
800 ld1%O1 %0 = %1%P1"
52e12ad0 801 [(set_attr "itanium_class" "xtd,ld")])
c65ebc55
JW		 802
803(define_insn "zero_extendhidi2"
0551c32d
RH		 804 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
805 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
c65ebc55
JW		 806 ""
807 "@
808 zxt2 %0 = %1
809 ld2%O1 %0 = %1%P1"
52e12ad0 810 [(set_attr "itanium_class" "xtd,ld")])
c65ebc55
JW		 811
812(define_insn "zero_extendsidi2"
655f2eb9 813 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
0551c32d 814 (zero_extend:DI
655f2eb9 815 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
c65ebc55
JW		 816 ""
817 "@
818 zxt4 %0 = %1
819 ld4%O1 %0 = %1%P1
aebf2462 820 fmix.r %0 = f0, %1"
52e12ad0 821 [(set_attr "itanium_class" "xtd,ld,fmisc")])
c65ebc55
JW		 822
823;; Convert between floating point types of different sizes.
824
640cea5f
JW		 825;; At first glance, it would appear that emitting fnorm for an extending
826;; conversion is unnecessary. However, the stf and getf instructions work
827;; correctly only if the input is properly rounded for its type. In
828;; particular, we get the wrong result for getf.d/stfd if the input is a
829;; denorm single. Since we don't know what the next instruction will be, we
830;; have to emit an fnorm.
831
e8e20f18
RH		 832;; ??? Optimization opportunity here. Get rid of the insn altogether
833;; when we can. Should probably use a scheme like has been proposed
834;; for ia32 in dealing with operands that match unary operators. This
640cea5f
JW		 835;; would let combine merge the thing into adjacent insns. See also how the
836;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
837;; se_register_operand.
c65ebc55 838
640cea5f
JW		 839(define_insn "extendsfdf2"
840 [(set (match_operand:DF 0 "fr_register_operand" "=f")
841 (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))]
c65ebc55 842 ""
640cea5f
JW		 843 "fnorm.d %0 = %1"
844 [(set_attr "itanium_class" "fmac")])
c65ebc55 845
640cea5f
JW		 846(define_insn "extendsftf2"
847 [(set (match_operand:TF 0 "fr_register_operand" "=f")
848 (float_extend:TF (match_operand:SF 1 "fr_register_operand" "f")))]
23c108af 849 "INTEL_EXTENDED_IEEE_FORMAT"
640cea5f
JW		 850 "fnorm %0 = %1"
851 [(set_attr "itanium_class" "fmac")])
3f622353 852
640cea5f
JW		 853(define_insn "extenddftf2"
854 [(set (match_operand:TF 0 "fr_register_operand" "=f")
855 (float_extend:TF (match_operand:DF 1 "fr_register_operand" "f")))]
23c108af 856 "INTEL_EXTENDED_IEEE_FORMAT"
640cea5f
JW		 857 "fnorm %0 = %1"
858 [(set_attr "itanium_class" "fmac")])
3f622353 859
c65ebc55 860(define_insn "truncdfsf2"
0551c32d
RH		 861 [(set (match_operand:SF 0 "fr_register_operand" "=f")
862 (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
c65ebc55 863 ""
aebf2462 864 "fnorm.s %0 = %1"
52e12ad0 865 [(set_attr "itanium_class" "fmac")])
c65ebc55 866
3f622353 867(define_insn "trunctfsf2"
0551c32d
RH		 868 [(set (match_operand:SF 0 "fr_register_operand" "=f")
869 (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
23c108af 870 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 871 "fnorm.s %0 = %1"
52e12ad0 872 [(set_attr "itanium_class" "fmac")])
c65ebc55 873
3f622353 874(define_insn "trunctfdf2"
0551c32d
RH		 875 [(set (match_operand:DF 0 "fr_register_operand" "=f")
876 (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
23c108af 877 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 878 "fnorm.d %0 = %1"
52e12ad0 879 [(set_attr "itanium_class" "fmac")])
e5bde68a
RH		 880
881;; Convert between signed integer types and floating point.
882
3f622353 883(define_insn "floatditf2"
0551c32d
RH		 884 [(set (match_operand:TF 0 "fr_register_operand" "=f")
885 (float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
23c108af 886 "INTEL_EXTENDED_IEEE_FORMAT"
e5bde68a 887 "fcvt.xf %0 = %1"
52e12ad0 888 [(set_attr "itanium_class" "fcvtfx")])
c65ebc55 889
23c108af
SE		 890;; ??? Suboptimal. This should be split somehow.
891(define_insn "floatdidf2"
892 [(set (match_operand:DF 0 "register_operand" "=f")
893 (float:DF (match_operand:DI 1 "register_operand" "f")))]
894 "!INTEL_EXTENDED_IEEE_FORMAT"
895 "fcvt.xf %0 = %1\;;;\;fnorm.d %0 = %0"
896 [(set_attr "itanium_class" "fcvtfx")])
897
898;; ??? Suboptimal. This should be split somehow.
899(define_insn "floatdisf2"
900 [(set (match_operand:SF 0 "register_operand" "=f")
901 (float:SF (match_operand:DI 1 "register_operand" "f")))]
902 "!INTEL_EXTENDED_IEEE_FORMAT"
903 "fcvt.xf %0 = %1\;;;\;fnorm.s %0 = %0"
904 [(set_attr "itanium_class" "fcvtfx")])
905
c65ebc55 906(define_insn "fix_truncsfdi2"
0551c32d
RH		 907 [(set (match_operand:DI 0 "fr_register_operand" "=f")
908 (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
c65ebc55 909 ""
aebf2462 910 "fcvt.fx.trunc %0 = %1"
52e12ad0 911 [(set_attr "itanium_class" "fcvtfx")])
c65ebc55
JW		 912
913(define_insn "fix_truncdfdi2"
0551c32d
RH		 914 [(set (match_operand:DI 0 "fr_register_operand" "=f")
915 (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
c65ebc55 916 ""
aebf2462 917 "fcvt.fx.trunc %0 = %1"
52e12ad0 918 [(set_attr "itanium_class" "fcvtfx")])
c65ebc55 919
3f622353 920(define_insn "fix_trunctfdi2"
0551c32d
RH		 921 [(set (match_operand:DI 0 "fr_register_operand" "=f")
922 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
23c108af 923 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 924 "fcvt.fx.trunc %0 = %1"
52e12ad0 925 [(set_attr "itanium_class" "fcvtfx")])
3f622353 926
655f2eb9
RH		 927(define_insn "fix_trunctfdi2_alts"
928 [(set (match_operand:DI 0 "fr_register_operand" "=f")
929 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
930 (use (match_operand:SI 2 "const_int_operand" ""))]
23c108af 931 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 932 "fcvt.fx.trunc.s%2 %0 = %1"
52e12ad0 933 [(set_attr "itanium_class" "fcvtfx")])
655f2eb9 934
c65ebc55
JW		 935;; Convert between unsigned integer types and floating point.
936
937(define_insn "floatunsdisf2"
0551c32d
RH		 938 [(set (match_operand:SF 0 "fr_register_operand" "=f")
939 (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
c65ebc55 940 ""
aebf2462 941 "fcvt.xuf.s %0 = %1"
52e12ad0 942 [(set_attr "itanium_class" "fcvtfx")])
c65ebc55
JW		 943
944(define_insn "floatunsdidf2"
0551c32d
RH		 945 [(set (match_operand:DF 0 "fr_register_operand" "=f")
946 (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
c65ebc55 947 ""
aebf2462 948 "fcvt.xuf.d %0 = %1"
52e12ad0 949 [(set_attr "itanium_class" "fcvtfx")])
c65ebc55 950
3f622353 951(define_insn "floatunsditf2"
0551c32d
RH		 952 [(set (match_operand:TF 0 "fr_register_operand" "=f")
953 (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
23c108af 954 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 955 "fcvt.xuf %0 = %1"
52e12ad0 956 [(set_attr "itanium_class" "fcvtfx")])
3f622353 957
c65ebc55 958(define_insn "fixuns_truncsfdi2"
0551c32d
RH		 959 [(set (match_operand:DI 0 "fr_register_operand" "=f")
960 (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
c65ebc55 961 ""
aebf2462 962 "fcvt.fxu.trunc %0 = %1"
52e12ad0 963 [(set_attr "itanium_class" "fcvtfx")])
c65ebc55
JW		 964
965(define_insn "fixuns_truncdfdi2"
0551c32d
RH		 966 [(set (match_operand:DI 0 "fr_register_operand" "=f")
967 (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
c65ebc55 968 ""
aebf2462 969 "fcvt.fxu.trunc %0 = %1"
52e12ad0 970 [(set_attr "itanium_class" "fcvtfx")])
c65ebc55 971
3f622353 972(define_insn "fixuns_trunctfdi2"
0551c32d
RH		 973 [(set (match_operand:DI 0 "fr_register_operand" "=f")
974 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
23c108af 975 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 976 "fcvt.fxu.trunc %0 = %1"
52e12ad0 977 [(set_attr "itanium_class" "fcvtfx")])
655f2eb9
RH		 978
979(define_insn "fixuns_trunctfdi2_alts"
980 [(set (match_operand:DI 0 "fr_register_operand" "=f")
981 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
982 (use (match_operand:SI 2 "const_int_operand" ""))]
23c108af 983 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 984 "fcvt.fxu.trunc.s%2 %0 = %1"
52e12ad0 985 [(set_attr "itanium_class" "fcvtfx")])
c65ebc55
JW		 986\f
987;; ::::::::::::::::::::
988;; ::
989;; :: Bit field extraction
990;; ::
991;; ::::::::::::::::::::
992
c65ebc55 993(define_insn "extv"
0551c32d
RH		 994 [(set (match_operand:DI 0 "gr_register_operand" "=r")
995 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
c65ebc55
JW		 996 (match_operand:DI 2 "const_int_operand" "n")
997 (match_operand:DI 3 "const_int_operand" "n")))]
998 ""
999 "extr %0 = %1, %3, %2"
52e12ad0 1000 [(set_attr "itanium_class" "ishf")])
c65ebc55
JW		 1001
1002(define_insn "extzv"
0551c32d
RH		 1003 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1004 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
c65ebc55
JW		 1005 (match_operand:DI 2 "const_int_operand" "n")
1006 (match_operand:DI 3 "const_int_operand" "n")))]
1007 ""
1008 "extr.u %0 = %1, %3, %2"
52e12ad0 1009 [(set_attr "itanium_class" "ishf")])
c65ebc55
JW		 1010
1011;; Insert a bit field.
1012;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1013;; Source1 can be 0 or -1.
1014;; Source2 can be 0.
1015
1016;; ??? Actual dep instruction is more powerful than what these insv
1017;; patterns support. Unfortunately, combine is unable to create patterns
1018;; where source2 != dest.
1019
1020(define_expand "insv"
0551c32d 1021 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
c65ebc55
JW		 1022 (match_operand:DI 1 "const_int_operand" "")
1023 (match_operand:DI 2 "const_int_operand" ""))
1024 (match_operand:DI 3 "nonmemory_operand" ""))]
1025 ""
1026 "
1027{
1028 int width = INTVAL (operands[1]);
1029 int shift = INTVAL (operands[2]);
1030
1031 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1032 pseudo. */
1033 if (! register_operand (operands[3], DImode)
1034 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1035 operands[3] = force_reg (DImode, operands[3]);
1036
1037 /* If this is a single dep instruction, we have nothing to do. */
1038 if (! ((register_operand (operands[3], DImode) && width <= 16)
1039 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1040 {
1041 /* Check for cases that can be implemented with a mix instruction. */
1042 if (width == 32 && shift == 0)
1043 {
1044 /* Directly generating the mix4left instruction confuses
1045 optimize_bit_field in function.c. Since this is performing
1046 a useful optimization, we defer generation of the complicated
1047 mix4left RTL to the first splitting phase. */
1048 rtx tmp = gen_reg_rtx (DImode);
1049 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1050 DONE;
1051 }
1052 else if (width == 32 && shift == 32)
1053 {
1054 emit_insn (gen_mix4right (operands[0], operands[3]));
1055 DONE;
1056 }
1057
d2ba6dcf
JW		 1058 /* We could handle remaining cases by emitting multiple dep
1059 instructions.
1060
1061 If we need more than two dep instructions then we lose. A 6
1062 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1063 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1064 the latter is 6 cycles on an Itanium (TM) processor, because there is
1065 only one function unit that can execute dep and shr immed.
1066
1067 If we only need two dep instruction, then we still lose.
1068 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1069 the unnecessary mov, this is still undesirable because it will be
1070 hard to optimize, and it creates unnecessary pressure on the I0
1071 function unit. */
1072
c65ebc55
JW		 1073 FAIL;
1074
1075#if 0
1076 /* This code may be useful for other IA-64 processors, so we leave it in
1077 for now. */
1078 while (width > 16)
1079 {
1080 rtx tmp;
1081
1082 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1083 operands[3]));
1084 shift += 16;
1085 width -= 16;
1086 tmp = gen_reg_rtx (DImode);
1087 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1088 operands[3] = tmp;
1089 }
1090 operands[1] = GEN_INT (width);
1091 operands[2] = GEN_INT (shift);
1092#endif
1093 }
1094}")
1095
1096(define_insn "*insv_internal"
0551c32d 1097 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
c65ebc55
JW		 1098 (match_operand:DI 1 "const_int_operand" "n")
1099 (match_operand:DI 2 "const_int_operand" "n"))
1100 (match_operand:DI 3 "nonmemory_operand" "rP"))]
0551c32d 1101 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
c65ebc55
JW		 1102 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1103 "dep %0 = %3, %0, %2, %1"
52e12ad0 1104 [(set_attr "itanium_class" "ishf")])
c65ebc55 1105
041f25e6
RH		 1106;; Combine doesn't like to create bitfield insertions into zero.
1107(define_insn "*depz_internal"
0551c32d
RH		 1108 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1109 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
041f25e6
RH		 1110 (match_operand:DI 2 "const_int_operand" "n"))
1111 (match_operand:DI 3 "const_int_operand" "n")))]
1112 "CONST_OK_FOR_M (INTVAL (operands[2]))
1113 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1114 "*
1115{
1116 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1117 return \"%,dep.z %0 = %1, %2, %3\";
1118}"
52e12ad0 1119 [(set_attr "itanium_class" "ishf")])
041f25e6 1120
c65ebc55 1121(define_insn "shift_mix4left"
0551c32d 1122 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
c65ebc55 1123 (const_int 32) (const_int 0))
0551c32d
RH		 1124 (match_operand:DI 1 "gr_register_operand" "r"))
1125 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
c65ebc55
JW		 1126 ""
1127 "#"
52e12ad0 1128 [(set_attr "itanium_class" "unknown")])
c65ebc55 1129
c65ebc55
JW		 1130(define_split
1131 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1132 (const_int 32) (const_int 0))
1133 (match_operand:DI 1 "register_operand" ""))
1134 (clobber (match_operand:DI 2 "register_operand" ""))]
1135 "reload_completed"
1136 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
c65ebc55
JW		 1137 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1138 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1139 "operands[3] = operands[2];")
1140
1141(define_split
1142 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1143 (const_int 32) (const_int 0))
1144 (match_operand:DI 1 "register_operand" ""))
1145 (clobber (match_operand:DI 2 "register_operand" ""))]
1146 "! reload_completed"
1147 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1148 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1149 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1150 "operands[3] = operands[2];")
1151
1152(define_insn "*mix4left"
0551c32d 1153 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
c65ebc55 1154 (const_int 32) (const_int 0))
0551c32d 1155 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
c65ebc55
JW		 1156 (const_int 32)))]
1157 ""
1158 "mix4.l %0 = %0, %r1"
52e12ad0 1159 [(set_attr "itanium_class" "mmshf")])
c65ebc55
JW		 1160
1161(define_insn "mix4right"
0551c32d 1162 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
c65ebc55 1163 (const_int 32) (const_int 32))
0551c32d 1164 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
c65ebc55
JW		 1165 ""
1166 "mix4.r %0 = %r1, %0"
52e12ad0 1167 [(set_attr "itanium_class" "mmshf")])
c65ebc55
JW		 1168
1169;; This is used by the rotrsi3 pattern.
1170
1171(define_insn "*mix4right_3op"
0551c32d
RH		 1172 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1173 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1174 (ashift:DI (zero_extend:DI
1175 (match_operand:SI 2 "gr_register_operand" "r"))
c65ebc55
JW		 1176 (const_int 32))))]
1177 ""
fa9a44e8 1178 "mix4.r %0 = %2, %1"
52e12ad0 1179 [(set_attr "itanium_class" "mmshf")])
c65ebc55
JW		 1180
1181\f
1182;; ::::::::::::::::::::
cf1f6ae3 1183;; ::
f2f90c63
RH		 1184;; :: 1 bit Integer arithmetic
1185;; ::
1186;; ::::::::::::::::::::
1187
1188(define_insn_and_split "andbi3"
1189 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1190 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1191 (match_operand:BI 2 "register_operand" "c,r,r")))]
1192 ""
1193 "@
1194 #
1195 tbit.nz.and.orcm %0, %I0 = %2, 0
1196 and %0 = %2, %1"
1197 "reload_completed
1198 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1199 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1200 [(cond_exec (eq (match_dup 2) (const_int 0))
1201 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1202 (match_dup 0))))]
1203 ""
52e12ad0 1204 [(set_attr "itanium_class" "unknown,tbit,ilog")])
f2f90c63
RH		 1205
1206(define_insn_and_split "*andcmbi3"
1207 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1208 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1209 (match_operand:BI 2 "register_operand" "0,0,r")))]
1210 ""
1211 "@
1212 #
1213 tbit.z.and.orcm %0, %I0 = %2, 0
1214 andcm %0 = %2, %1"
1215 "reload_completed
1216 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1217 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1218 [(cond_exec (ne (match_dup 1) (const_int 0))
1219 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1220 (match_dup 0))))]
1221 ""
52e12ad0 1222 [(set_attr "itanium_class" "unknown,tbit,ilog")])
f2f90c63
RH		 1223
1224(define_insn_and_split "iorbi3"
1225 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1226 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1227 (match_operand:BI 2 "register_operand" "c,r,r")))]
1228 ""
1229 "@
1230 #
1231 tbit.nz.or.andcm %0, %I0 = %2, 0
1232 or %0 = %2, %1"
1233 "reload_completed
1234 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1235 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1236 [(cond_exec (ne (match_dup 2) (const_int 0))
1237 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1238 (match_dup 0))))]
1239 ""
52e12ad0 1240 [(set_attr "itanium_class" "unknown,tbit,ilog")])
f2f90c63
RH		 1241
1242(define_insn_and_split "*iorcmbi3"
1243 [(set (match_operand:BI 0 "register_operand" "=c,c")
1244 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1245 (match_operand:BI 2 "register_operand" "0,0")))]
1246 ""
1247 "@
1248 #
1249 tbit.z.or.andcm %0, %I0 = %2, 0"
1250 "reload_completed
1251 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1252 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1253 [(cond_exec (eq (match_dup 1) (const_int 0))
1254 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1255 (match_dup 0))))]
1256 ""
52e12ad0 1257 [(set_attr "itanium_class" "unknown,tbit")])
f2f90c63
RH		 1258
1259(define_insn "one_cmplbi2"
1260 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1261 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1262 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1263 ""
1264 "@
1265 tbit.z %0, %I0 = %1, 0
1266 xor %0 = 1, %1
1267 #
1268 #"
52e12ad0 1269 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
f2f90c63
RH		 1270
1271(define_split
1272 [(set (match_operand:BI 0 "register_operand" "")
1273 (not:BI (match_operand:BI 1 "register_operand" "")))
1274 (clobber (match_scratch:BI 2 ""))]
1275 "reload_completed
1276 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1277 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1278 && rtx_equal_p (operands[0], operands[1])"
1279 [(set (match_dup 4) (match_dup 3))
1280 (set (match_dup 0) (const_int 1))
1281 (cond_exec (ne (match_dup 2) (const_int 0))
1282 (set (match_dup 0) (const_int 0)))
1283 (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
1284 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1285 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1286
1287(define_split
1288 [(set (match_operand:BI 0 "register_operand" "")
1289 (not:BI (match_operand:BI 1 "register_operand" "")))
1290 (clobber (match_scratch:BI 2 ""))]
1291 "reload_completed
1292 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1293 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1294 && ! rtx_equal_p (operands[0], operands[1])"
1295 [(cond_exec (ne (match_dup 1) (const_int 0))
1296 (set (match_dup 0) (const_int 0)))
1297 (cond_exec (eq (match_dup 1) (const_int 0))
1298 (set (match_dup 0) (const_int 1)))
1299 (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
1300 "")
1301
1302(define_insn "*cmpsi_and_0"
1303 [(set (match_operand:BI 0 "register_operand" "=c")
1304 (and:BI (match_operator:BI 4 "predicate_operator"
1305 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1306 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1307 (match_operand:BI 1 "register_operand" "0")))]
1308 ""
1309 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
52e12ad0 1310 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1311
1312(define_insn "*cmpsi_and_1"
1313 [(set (match_operand:BI 0 "register_operand" "=c")
1314 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1315 [(match_operand:SI 2 "gr_register_operand" "r")
1316 (const_int 0)])
1317 (match_operand:BI 1 "register_operand" "0")))]
1318 ""
1319 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
52e12ad0 1320 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1321
1322(define_insn "*cmpsi_andnot_0"
1323 [(set (match_operand:BI 0 "register_operand" "=c")
1324 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1325 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1326 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1327 (match_operand:BI 1 "register_operand" "0")))]
1328 ""
1329 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
52e12ad0 1330 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1331
1332(define_insn "*cmpsi_andnot_1"
1333 [(set (match_operand:BI 0 "register_operand" "=c")
1334 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1335 [(match_operand:SI 2 "gr_register_operand" "r")
1336 (const_int 0)]))
1337 (match_operand:BI 1 "register_operand" "0")))]
1338 ""
1339 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
52e12ad0 1340 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1341
1342(define_insn "*cmpdi_and_0"
1343 [(set (match_operand:BI 0 "register_operand" "=c")
1344 (and:BI (match_operator:BI 4 "predicate_operator"
1345 [(match_operand:DI 2 "gr_register_operand" "r")
1346 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1347 (match_operand:BI 1 "register_operand" "0")))]
1348 ""
1349 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
52e12ad0 1350 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1351
1352(define_insn "*cmpdi_and_1"
1353 [(set (match_operand:BI 0 "register_operand" "=c")
1354 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1355 [(match_operand:DI 2 "gr_register_operand" "r")
1356 (const_int 0)])
1357 (match_operand:BI 1 "register_operand" "0")))]
1358 ""
1359 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
52e12ad0 1360 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1361
1362(define_insn "*cmpdi_andnot_0"
1363 [(set (match_operand:BI 0 "register_operand" "=c")
1364 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1365 [(match_operand:DI 2 "gr_register_operand" "r")
1366 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1367 (match_operand:BI 1 "register_operand" "0")))]
1368 ""
1369 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
52e12ad0 1370 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1371
1372(define_insn "*cmpdi_andnot_1"
1373 [(set (match_operand:BI 0 "register_operand" "=c")
1374 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1375 [(match_operand:DI 2 "gr_register_operand" "r")
1376 (const_int 0)]))
1377 (match_operand:BI 1 "register_operand" "0")))]
1378 ""
1379 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
52e12ad0 1380 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1381
1382(define_insn "*tbit_and_0"
1383 [(set (match_operand:BI 0 "register_operand" "=c")
1384 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1385 (const_int 1))
1386 (const_int 0))
c77e04ae 1387 (match_operand:BI 2 "register_operand" "0")))]
f2f90c63
RH		 1388 ""
1389 "tbit.nz.and.orcm %0, %I0 = %1, 0"
52e12ad0 1390 [(set_attr "itanium_class" "tbit")])
f2f90c63
RH		 1391
1392(define_insn "*tbit_and_1"
1393 [(set (match_operand:BI 0 "register_operand" "=c")
1394 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1395 (const_int 1))
1396 (const_int 0))
c77e04ae 1397 (match_operand:BI 2 "register_operand" "0")))]
f2f90c63
RH		 1398 ""
1399 "tbit.z.and.orcm %0, %I0 = %1, 0"
52e12ad0 1400 [(set_attr "itanium_class" "tbit")])
f2f90c63
RH		 1401
1402(define_insn "*tbit_and_2"
1403 [(set (match_operand:BI 0 "register_operand" "=c")
1404 (and:BI (ne:BI (zero_extract:DI
1405 (match_operand:DI 1 "gr_register_operand" "r")
1406 (const_int 1)
1407 (match_operand:DI 2 "const_int_operand" "n"))
1408 (const_int 0))
1409 (match_operand:BI 3 "register_operand" "0")))]
1410 ""
1411 "tbit.nz.and.orcm %0, %I0 = %1, %2"
52e12ad0 1412 [(set_attr "itanium_class" "tbit")])
f2f90c63
RH		 1413
1414(define_insn "*tbit_and_3"
1415 [(set (match_operand:BI 0 "register_operand" "=c")
1416 (and:BI (eq:BI (zero_extract:DI
1417 (match_operand:DI 1 "gr_register_operand" "r")
1418 (const_int 1)
1419 (match_operand:DI 2 "const_int_operand" "n"))
1420 (const_int 0))
1421 (match_operand:BI 3 "register_operand" "0")))]
1422 ""
1423 "tbit.z.and.orcm %0, %I0 = %1, %2"
52e12ad0 1424 [(set_attr "itanium_class" "tbit")])
f2f90c63
RH		 1425
1426(define_insn "*cmpsi_or_0"
1427 [(set (match_operand:BI 0 "register_operand" "=c")
1428 (ior:BI (match_operator:BI 4 "predicate_operator"
1429 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1430 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1431 (match_operand:BI 1 "register_operand" "0")))]
1432 ""
1433 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
52e12ad0 1434 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1435
1436(define_insn "*cmpsi_or_1"
1437 [(set (match_operand:BI 0 "register_operand" "=c")
1438 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1439 [(match_operand:SI 2 "gr_register_operand" "r")
1440 (const_int 0)])
1441 (match_operand:BI 1 "register_operand" "0")))]
1442 ""
1443 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
52e12ad0 1444 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1445
1446(define_insn "*cmpsi_orcm_0"
1447 [(set (match_operand:BI 0 "register_operand" "=c")
1448 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1449 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1450 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1451 (match_operand:BI 1 "register_operand" "0")))]
1452 ""
1453 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
52e12ad0 1454 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1455
1456(define_insn "*cmpsi_orcm_1"
1457 [(set (match_operand:BI 0 "register_operand" "=c")
1458 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1459 [(match_operand:SI 2 "gr_register_operand" "r")
1460 (const_int 0)]))
1461 (match_operand:BI 1 "register_operand" "0")))]
1462 ""
1463 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
52e12ad0 1464 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1465
1466(define_insn "*cmpdi_or_0"
1467 [(set (match_operand:BI 0 "register_operand" "=c")
1468 (ior:BI (match_operator:BI 4 "predicate_operator"
1469 [(match_operand:DI 2 "gr_register_operand" "r")
1470 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1471 (match_operand:BI 1 "register_operand" "0")))]
1472 ""
1473 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
52e12ad0 1474 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1475
1476(define_insn "*cmpdi_or_1"
1477 [(set (match_operand:BI 0 "register_operand" "=c")
1478 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1479 [(match_operand:DI 2 "gr_register_operand" "r")
1480 (const_int 0)])
1481 (match_operand:BI 1 "register_operand" "0")))]
1482 ""
1483 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
52e12ad0 1484 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1485
1486(define_insn "*cmpdi_orcm_0"
1487 [(set (match_operand:BI 0 "register_operand" "=c")
1488 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1489 [(match_operand:DI 2 "gr_register_operand" "r")
1490 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1491 (match_operand:BI 1 "register_operand" "0")))]
1492 ""
1493 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
52e12ad0 1494 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1495
1496(define_insn "*cmpdi_orcm_1"
1497 [(set (match_operand:BI 0 "register_operand" "=c")
1498 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1499 [(match_operand:DI 2 "gr_register_operand" "r")
1500 (const_int 0)]))
1501 (match_operand:BI 1 "register_operand" "0")))]
1502 ""
1503 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
52e12ad0 1504 [(set_attr "itanium_class" "icmp")])
f2f90c63
RH		 1505
1506(define_insn "*tbit_or_0"
1507 [(set (match_operand:BI 0 "register_operand" "=c")
1508 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1509 (const_int 1))
1510 (const_int 0))
c77e04ae 1511 (match_operand:BI 2 "register_operand" "0")))]
f2f90c63
RH		 1512 ""
1513 "tbit.nz.or.andcm %0, %I0 = %1, 0"
52e12ad0 1514 [(set_attr "itanium_class" "tbit")])
f2f90c63
RH		 1515
1516(define_insn "*tbit_or_1"
1517 [(set (match_operand:BI 0 "register_operand" "=c")
1518 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1519 (const_int 1))
1520 (const_int 0))
c77e04ae 1521 (match_operand:BI 2 "register_operand" "0")))]
f2f90c63
RH		 1522 ""
1523 "tbit.z.or.andcm %0, %I0 = %1, 0"
52e12ad0 1524 [(set_attr "itanium_class" "tbit")])
f2f90c63
RH		 1525
1526(define_insn "*tbit_or_2"
1527 [(set (match_operand:BI 0 "register_operand" "=c")
1528 (ior:BI (ne:BI (zero_extract:DI
1529 (match_operand:DI 1 "gr_register_operand" "r")
1530 (const_int 1)
1531 (match_operand:DI 2 "const_int_operand" "n"))
1532 (const_int 0))
1533 (match_operand:BI 3 "register_operand" "0")))]
1534 ""
1535 "tbit.nz.or.andcm %0, %I0 = %1, %2"
52e12ad0 1536 [(set_attr "itanium_class" "tbit")])
f2f90c63
RH		 1537
1538(define_insn "*tbit_or_3"
1539 [(set (match_operand:BI 0 "register_operand" "=c")
1540 (ior:BI (eq:BI (zero_extract:DI
1541 (match_operand:DI 1 "gr_register_operand" "r")
1542 (const_int 1)
1543 (match_operand:DI 2 "const_int_operand" "n"))
1544 (const_int 0))
1545 (match_operand:BI 3 "register_operand" "0")))]
1546 ""
1547 "tbit.z.or.andcm %0, %I0 = %1, %2"
52e12ad0 1548 [(set_attr "itanium_class" "tbit")])
f2f90c63
RH		 1549
1550;; Transform test of and/or of setcc into parallel comparisons.
1551
1552(define_split
1553 [(set (match_operand:BI 0 "register_operand" "")
1554 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1555 (const_int 0))
1556 (match_operand:DI 3 "register_operand" ""))
1557 (const_int 0)))]
1558 ""
1559 [(set (match_dup 0)
1560 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1561 (match_dup 2)))]
1562 "")
1563
1564(define_split
1565 [(set (match_operand:BI 0 "register_operand" "")
1566 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1567 (const_int 0))
1568 (match_operand:DI 3 "register_operand" ""))
1569 (const_int 0)))]
1570 ""
1571 [(set (match_dup 0)
1572 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1573 (match_dup 2)))
1574 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1575 (clobber (scratch))])]
1576 "")
1577
1578(define_split
1579 [(set (match_operand:BI 0 "register_operand" "")
1580 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1581 (const_int 0))
1582 (match_operand:DI 3 "register_operand" ""))
1583 (const_int 0)))]
1584 ""
1585 [(set (match_dup 0)
1586 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1587 (match_dup 2)))]
1588 "")
1589
1590(define_split
1591 [(set (match_operand:BI 0 "register_operand" "")
1592 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1593 (const_int 0))
1594 (match_operand:DI 3 "register_operand" ""))
1595 (const_int 0)))]
1596 ""
1597 [(set (match_dup 0)
1598 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1599 (match_dup 2)))
1600 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1601 (clobber (scratch))])]
1602 "")
1603
1604;; ??? Incredibly hackish. Either need four proper patterns with all
1605;; the alternatives, or rely on sched1 to split the insn and hope that
1606;; nothing bad happens to the comparisons in the meantime.
1607;;
1608;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1609;; that we're doing height reduction.
1610;
1611;(define_insn_and_split ""
1612; [(set (match_operand:BI 0 "register_operand" "=c")
1613; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1614; [(match_operand 2 "" "")
1615; (match_operand 3 "" "")])
1616; (match_operator:BI 4 "comparison_operator"
1617; [(match_operand 5 "" "")
1618; (match_operand 6 "" "")]))
1619; (match_dup 0)))]
1620; "flag_schedule_insns"
1621; "#"
1622; ""
1623; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1624; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
1625; "")
1626;
1627;(define_insn_and_split ""
1628; [(set (match_operand:BI 0 "register_operand" "=c")
1629; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1630; [(match_operand 2 "" "")
1631; (match_operand 3 "" "")])
1632; (match_operator:BI 4 "comparison_operator"
1633; [(match_operand 5 "" "")
1634; (match_operand 6 "" "")]))
1635; (match_dup 0)))]
1636; "flag_schedule_insns"
1637; "#"
1638; ""
1639; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
1640; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
1641; "")
1642;
1643;(define_split
1644; [(set (match_operand:BI 0 "register_operand" "")
1645; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1646; [(match_operand 2 "" "")
1647; (match_operand 3 "" "")])
1648; (match_operand:BI 7 "register_operand" ""))
1649; (and:BI (match_operator:BI 4 "comparison_operator"
1650; [(match_operand 5 "" "")
1651; (match_operand 6 "" "")])
1652; (match_operand:BI 8 "register_operand" ""))))]
1653; ""
1654; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
1655; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
1656; (match_dup 0)))]
1657; "")
1658;
1659;(define_split
1660; [(set (match_operand:BI 0 "register_operand" "")
1661; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1662; [(match_operand 2 "" "")
1663; (match_operand 3 "" "")])
1664; (match_operand:BI 7 "register_operand" ""))
1665; (ior:BI (match_operator:BI 4 "comparison_operator"
1666; [(match_operand 5 "" "")
1667; (match_operand 6 "" "")])
1668; (match_operand:BI 8 "register_operand" ""))))]
1669; ""
1670; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
1671; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
1672; (match_dup 0)))]
1673; "")
1674
1675;; Try harder to avoid predicate copies by duplicating compares.
1676;; Note that we'll have already split the predicate copy, which
1677;; is kind of a pain, but oh well.
1678
1679(define_peephole2
1680 [(set (match_operand:BI 0 "register_operand" "")
1681 (match_operand:BI 1 "comparison_operator" ""))
1682 (set (match_operand:CCI 2 "register_operand" "")
1683 (match_operand:CCI 3 "register_operand" ""))
1684 (set (match_operand:CCI 4 "register_operand" "")
1685 (match_operand:CCI 5 "register_operand" ""))
1686 (set (match_operand:BI 6 "register_operand" "")
1687 (unspec:BI [(match_dup 6)] 7))]
1688 "REGNO (operands[3]) == REGNO (operands[0])
1689 && REGNO (operands[4]) == REGNO (operands[0]) + 1
1690 && REGNO (operands[4]) == REGNO (operands[2]) + 1
1691 && REGNO (operands[6]) == REGNO (operands[2])"
1692 [(set (match_dup 0) (match_dup 1))
1693 (set (match_dup 6) (match_dup 7))]
1694 "operands[7] = copy_rtx (operands[1]);")
1695\f
1696;; ::::::::::::::::::::
1697;; ::
cf1f6ae3
RH		 1698;; :: 16 bit Integer arithmetic
1699;; ::
1700;; ::::::::::::::::::::
1701
1702(define_insn "mulhi3"
1703 [(set (match_operand:HI 0 "gr_register_operand" "=r")
1704 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
1705 (match_operand:HI 2 "gr_register_operand" "r")))]
1706 ""
2a7ffc85 1707 "pmpy2.r %0 = %1, %2"
52e12ad0 1708 [(set_attr "itanium_class" "mmmul")])
cf1f6ae3
RH		 1709
1710\f
1711;; ::::::::::::::::::::
c65ebc55
JW		 1712;; ::
1713;; :: 32 bit Integer arithmetic
1714;; ::
1715;; ::::::::::::::::::::
1716
058557c4 1717(define_insn "addsi3"
0551c32d
RH		 1718 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
1719 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
1720 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
c65ebc55
JW		 1721 ""
1722 "@
1723 add %0 = %1, %2
1724 adds %0 = %2, %1
1725 addl %0 = %2, %1"
52e12ad0 1726 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 1727
1728(define_insn "*addsi3_plus1"
0551c32d
RH		 1729 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1730 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
1731 (match_operand:SI 2 "gr_register_operand" "r"))
c65ebc55
JW		 1732 (const_int 1)))]
1733 ""
1734 "add %0 = %1, %2, 1"
52e12ad0 1735 [(set_attr "itanium_class" "ialu")])
c65ebc55 1736
5527bf14 1737(define_insn "*addsi3_plus1_alt"
0551c32d
RH		 1738 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1739 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
5527bf14
RH		 1740 (const_int 2))
1741 (const_int 1)))]
1742 ""
1743 "add %0 = %1, %1, 1"
52e12ad0 1744 [(set_attr "itanium_class" "ialu")])
5527bf14 1745
058557c4 1746(define_insn "*addsi3_shladd"
0551c32d
RH		 1747 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1748 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
058557c4 1749 (match_operand:SI 2 "shladd_operand" "n"))
0551c32d 1750 (match_operand:SI 3 "gr_register_operand" "r")))]
c65ebc55 1751 ""
058557c4 1752 "shladd %0 = %1, %S2, %3"
52e12ad0 1753 [(set_attr "itanium_class" "ialu")])
c65ebc55 1754
058557c4 1755(define_insn "subsi3"
0551c32d
RH		 1756 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1757 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
1758 (match_operand:SI 2 "gr_register_operand" "r")))]
c65ebc55
JW		 1759 ""
1760 "sub %0 = %1, %2"
52e12ad0 1761 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 1762
1763(define_insn "*subsi3_minus1"
0551c32d
RH		 1764 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1765 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
1766 (match_operand:SI 2 "gr_register_operand" "r")))]
c65ebc55
JW		 1767 ""
1768 "sub %0 = %2, %1, 1"
52e12ad0
BS		 1769 [(set_attr "itanium_class" "ialu")])
1770
1771;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
c65ebc55 1772
058557c4 1773(define_insn "mulsi3"
0551c32d 1774 [(set (match_operand:SI 0 "fr_register_operand" "=f")
11a13704
RH		 1775 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
1776 (match_operand:SI 2 "grfr_register_operand" "f")))]
c65ebc55 1777 ""
aebf2462 1778 "xmpy.l %0 = %1, %2"
52e12ad0 1779 [(set_attr "itanium_class" "xmpy")])
c65ebc55 1780
655f2eb9 1781(define_insn "maddsi4"
11a13704
RH		 1782 [(set (match_operand:SI 0 "fr_register_operand" "=f")
1783 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
1784 (match_operand:SI 2 "grfr_register_operand" "f"))
1785 (match_operand:SI 3 "grfr_register_operand" "f")))]
1786 ""
aebf2462 1787 "xma.l %0 = %1, %2, %3"
52e12ad0 1788 [(set_attr "itanium_class" "xmpy")])
11a13704 1789
058557c4 1790(define_insn "negsi2"
0551c32d
RH		 1791 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1792 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
c65ebc55
JW		 1793 ""
1794 "sub %0 = r0, %1"
52e12ad0 1795 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 1796
1797(define_expand "abssi2"
1798 [(set (match_dup 2)
f2f90c63 1799 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
0551c32d 1800 (set (match_operand:SI 0 "gr_register_operand" "")
f2f90c63 1801 (if_then_else:SI (eq (match_dup 2) (const_int 0))
e5bde68a
RH		 1802 (neg:SI (match_dup 1))
1803 (match_dup 1)))]
c65ebc55
JW		 1804 ""
1805 "
1806{
f2f90c63 1807 operands[2] = gen_reg_rtx (BImode);
c65ebc55
JW		 1808}")
1809
1810(define_expand "sminsi3"
1811 [(set (match_dup 3)
f2f90c63 1812 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
0551c32d
RH		 1813 (match_operand:SI 2 "gr_register_operand" "")))
1814 (set (match_operand:SI 0 "gr_register_operand" "")
f2f90c63 1815 (if_then_else:SI (ne (match_dup 3) (const_int 0))
c65ebc55
JW		 1816 (match_dup 2) (match_dup 1)))]
1817 ""
1818 "
1819{
f2f90c63 1820 operands[3] = gen_reg_rtx (BImode);
c65ebc55
JW		 1821}")
1822
1823(define_expand "smaxsi3"
1824 [(set (match_dup 3)
f2f90c63 1825 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
0551c32d
RH		 1826 (match_operand:SI 2 "gr_register_operand" "")))
1827 (set (match_operand:SI 0 "gr_register_operand" "")
f2f90c63 1828 (if_then_else:SI (ne (match_dup 3) (const_int 0))
c65ebc55
JW		 1829 (match_dup 1) (match_dup 2)))]
1830 ""
1831 "
1832{
f2f90c63 1833 operands[3] = gen_reg_rtx (BImode);
c65ebc55
JW		 1834}")
1835
1836(define_expand "uminsi3"
1837 [(set (match_dup 3)
f2f90c63 1838 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
0551c32d
RH		 1839 (match_operand:SI 2 "gr_register_operand" "")))
1840 (set (match_operand:SI 0 "gr_register_operand" "")
f2f90c63 1841 (if_then_else:SI (ne (match_dup 3) (const_int 0))
c65ebc55
JW		 1842 (match_dup 2) (match_dup 1)))]
1843 ""
1844 "
1845{
f2f90c63 1846 operands[3] = gen_reg_rtx (BImode);
c65ebc55
JW		 1847}")
1848
1849(define_expand "umaxsi3"
1850 [(set (match_dup 3)
f2f90c63 1851 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
0551c32d
RH		 1852 (match_operand:SI 2 "gr_register_operand" "")))
1853 (set (match_operand:SI 0 "gr_register_operand" "")
f2f90c63 1854 (if_then_else:SI (ne (match_dup 3) (const_int 0))
c65ebc55
JW		 1855 (match_dup 1) (match_dup 2)))]
1856 ""
1857 "
1858{
f2f90c63 1859 operands[3] = gen_reg_rtx (BImode);
c65ebc55
JW		 1860}")
1861
655f2eb9
RH		 1862(define_expand "divsi3"
1863 [(set (match_operand:SI 0 "register_operand" "")
1864 (div:SI (match_operand:SI 1 "general_operand" "")
1865 (match_operand:SI 2 "general_operand" "")))]
23c108af 1866 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
655f2eb9
RH		 1867 "
1868{
1869 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
1870
1871 op0_tf = gen_reg_rtx (TFmode);
1872 op0_di = gen_reg_rtx (DImode);
1873
1874 if (CONSTANT_P (operands[1]))
1875 operands[1] = force_reg (SImode, operands[1]);
1876 op1_tf = gen_reg_rtx (TFmode);
1877 expand_float (op1_tf, operands[1], 0);
1878
1879 if (CONSTANT_P (operands[2]))
1880 operands[2] = force_reg (SImode, operands[2]);
1881 op2_tf = gen_reg_rtx (TFmode);
1882 expand_float (op2_tf, operands[2], 0);
1883
1884 /* 2^-34 */
1885#if 0
1886 twon34 = (CONST_DOUBLE_FROM_REAL_VALUE
1887 (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode));
1888 twon34 = force_reg (TFmode, twon34);
1889#else
1890 twon34 = gen_reg_rtx (TFmode);
1891 convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0);
1892#endif
1893
1894 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
1895
1896 emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
1897 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
1898 DONE;
1899}")
1900
1901(define_expand "modsi3"
1902 [(set (match_operand:SI 0 "register_operand" "")
1903 (mod:SI (match_operand:SI 1 "general_operand" "")
1904 (match_operand:SI 2 "general_operand" "")))]
23c108af 1905 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
655f2eb9
RH		 1906 "
1907{
1908 rtx op2_neg, op1_di, div;
1909
1910 div = gen_reg_rtx (SImode);
1911 emit_insn (gen_divsi3 (div, operands[1], operands[2]));
1912
1913 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
1914
1915 /* This is a trick to get us to reuse the value that we're sure to
1916 have already copied to the FP regs. */
1917 op1_di = gen_reg_rtx (DImode);
1918 convert_move (op1_di, operands[1], 0);
1919
1920 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
1921 gen_lowpart (SImode, op1_di)));
1922 DONE;
1923}")
1924
1925(define_expand "udivsi3"
1926 [(set (match_operand:SI 0 "register_operand" "")
1927 (udiv:SI (match_operand:SI 1 "general_operand" "")
1928 (match_operand:SI 2 "general_operand" "")))]
23c108af 1929 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
655f2eb9
RH		 1930 "
1931{
1932 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
1933
1934 op0_tf = gen_reg_rtx (TFmode);
1935 op0_di = gen_reg_rtx (DImode);
1936
1937 if (CONSTANT_P (operands[1]))
1938 operands[1] = force_reg (SImode, operands[1]);
1939 op1_tf = gen_reg_rtx (TFmode);
1940 expand_float (op1_tf, operands[1], 1);
1941
1942 if (CONSTANT_P (operands[2]))
1943 operands[2] = force_reg (SImode, operands[2]);
1944 op2_tf = gen_reg_rtx (TFmode);
1945 expand_float (op2_tf, operands[2], 1);
1946
1947 /* 2^-34 */
1948#if 0
1949 twon34 = (CONST_DOUBLE_FROM_REAL_VALUE
1950 (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode));
1951 twon34 = force_reg (TFmode, twon34);
1952#else
1953 twon34 = gen_reg_rtx (TFmode);
1954 convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0);
1955#endif
1956
1957 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
1958
1959 emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
1960 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
1961 DONE;
1962}")
1963
1964(define_expand "umodsi3"
1965 [(set (match_operand:SI 0 "register_operand" "")
1966 (umod:SI (match_operand:SI 1 "general_operand" "")
1967 (match_operand:SI 2 "general_operand" "")))]
23c108af 1968 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
655f2eb9
RH		 1969 "
1970{
1971 rtx op2_neg, op1_di, div;
1972
1973 div = gen_reg_rtx (SImode);
1974 emit_insn (gen_udivsi3 (div, operands[1], operands[2]));
1975
1976 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
1977
1978 /* This is a trick to get us to reuse the value that we're sure to
1979 have already copied to the FP regs. */
1980 op1_di = gen_reg_rtx (DImode);
1981 convert_move (op1_di, operands[1], 1);
1982
1983 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
1984 gen_lowpart (SImode, op1_di)));
1985 DONE;
1986}")
1987
1988(define_insn_and_split "divsi3_internal"
1989 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
1990 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
1991 (match_operand:TF 2 "fr_register_operand" "f"))))
1992 (clobber (match_scratch:TF 4 "=&f"))
1993 (clobber (match_scratch:TF 5 "=&f"))
f2f90c63 1994 (clobber (match_scratch:BI 6 "=c"))
655f2eb9 1995 (use (match_operand:TF 3 "fr_register_operand" "f"))]
23c108af 1996 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
655f2eb9
RH		 1997 "#"
1998 "&& reload_completed"
1999 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
f2f90c63 2000 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
655f2eb9
RH		 2001 (use (const_int 1))])
2002 (cond_exec (ne (match_dup 6) (const_int 0))
2003 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2004 (use (const_int 1))]))
2005 (cond_exec (ne (match_dup 6) (const_int 0))
2006 (parallel [(set (match_dup 5)
2007 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2008 (match_dup 7)))
2009 (use (const_int 1))]))
2010 (cond_exec (ne (match_dup 6) (const_int 0))
2011 (parallel [(set (match_dup 4)
2012 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2013 (match_dup 4)))
2014 (use (const_int 1))]))
2015 (cond_exec (ne (match_dup 6) (const_int 0))
2016 (parallel [(set (match_dup 5)
2017 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
2018 (match_dup 3)))
2019 (use (const_int 1))]))
2020 (cond_exec (ne (match_dup 6) (const_int 0))
2021 (parallel [(set (match_dup 0)
2022 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2023 (match_dup 4)))
2024 (use (const_int 1))]))
2025 ]
2026 "operands[7] = CONST1_RTX (TFmode);"
2027 [(set_attr "predicable" "no")])
c65ebc55
JW		 2028\f
2029;; ::::::::::::::::::::
2030;; ::
2031;; :: 64 bit Integer arithmetic
2032;; ::
2033;; ::::::::::::::::::::
2034
2035(define_insn "adddi3"
0551c32d
RH		 2036 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2037 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2038 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
c65ebc55
JW		 2039 ""
2040 "@
2041 add %0 = %1, %2
2042 adds %0 = %2, %1
2043 addl %0 = %2, %1"
52e12ad0 2044 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 2045
2046(define_insn "*adddi3_plus1"
0551c32d
RH		 2047 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2048 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2049 (match_operand:DI 2 "gr_register_operand" "r"))
c65ebc55
JW		 2050 (const_int 1)))]
2051 ""
2052 "add %0 = %1, %2, 1"
52e12ad0 2053 [(set_attr "itanium_class" "ialu")])
c65ebc55 2054
5527bf14
RH		 2055;; This has some of the same problems as shladd. We let the shladd
2056;; eliminator hack handle it, which results in the 1 being forced into
2057;; a register, but not more ugliness here.
2058(define_insn "*adddi3_plus1_alt"
0551c32d
RH		 2059 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2060 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
5527bf14
RH		 2061 (const_int 2))
2062 (const_int 1)))]
2063 ""
2064 "add %0 = %1, %1, 1"
52e12ad0 2065 [(set_attr "itanium_class" "ialu")])
5527bf14 2066
c65ebc55 2067(define_insn "subdi3"
0551c32d
RH		 2068 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2069 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2070 (match_operand:DI 2 "gr_register_operand" "r")))]
c65ebc55
JW		 2071 ""
2072 "sub %0 = %1, %2"
52e12ad0 2073 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 2074
2075(define_insn "*subdi3_minus1"
0551c32d
RH		 2076 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2077 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2078 (match_operand:DI 2 "gr_register_operand" "r")))]
c65ebc55
JW		 2079 ""
2080 "sub %0 = %2, %1, 1"
52e12ad0 2081 [(set_attr "itanium_class" "ialu")])
c65ebc55 2082
cee58bc0
RH		 2083;; ??? Use grfr instead of fr because of virtual register elimination
2084;; and silly test cases multiplying by the frame pointer.
c65ebc55 2085(define_insn "muldi3"
0551c32d 2086 [(set (match_operand:DI 0 "fr_register_operand" "=f")
cee58bc0
RH		 2087 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2088 (match_operand:DI 2 "grfr_register_operand" "f")))]
c65ebc55 2089 ""
aebf2462 2090 "xmpy.l %0 = %1, %2"
52e12ad0 2091 [(set_attr "itanium_class" "xmpy")])
c65ebc55
JW		 2092
2093;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2094;; same problem that we have with shladd below. Unfortunately, this case is
2095;; much harder to fix because the multiply puts the result in an FP register,
2096;; but the add needs inputs from a general register. We add a spurious clobber
2097;; here so that it will be present just in case register elimination gives us
2098;; the funny result.
2099
2100;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2101
2102;; ??? Maybe we should change how adds are canonicalized.
2103
655f2eb9 2104(define_insn "madddi4"
0551c32d 2105 [(set (match_operand:DI 0 "fr_register_operand" "=f")
11a13704
RH		 2106 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2107 (match_operand:DI 2 "grfr_register_operand" "f"))
2108 (match_operand:DI 3 "grfr_register_operand" "f")))
c65ebc55
JW		 2109 (clobber (match_scratch:DI 4 "=X"))]
2110 ""
aebf2462 2111 "xma.l %0 = %1, %2, %3"
52e12ad0 2112 [(set_attr "itanium_class" "xmpy")])
c65ebc55
JW		 2113
2114;; This can be created by register elimination if operand3 of shladd is an
2115;; eliminable register or has reg_equiv_constant set.
2116
2117;; We have to use nonmemory_operand for operand 4, to ensure that the
2118;; validate_changes call inside eliminate_regs will always succeed. If it
655f2eb9 2119;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
c65ebc55
JW		 2120;; incorrectly.
2121
655f2eb9 2122(define_insn "*madddi4_elim"
c65ebc55 2123 [(set (match_operand:DI 0 "register_operand" "=&r")
13da91fd
RH		 2124 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2125 (match_operand:DI 2 "register_operand" "f"))
2126 (match_operand:DI 3 "register_operand" "f"))
c65ebc55 2127 (match_operand:DI 4 "nonmemory_operand" "rI")))
13da91fd 2128 (clobber (match_scratch:DI 5 "=f"))]
c65ebc55
JW		 2129 "reload_in_progress"
2130 "#"
52e12ad0 2131 [(set_attr "itanium_class" "unknown")])
c65ebc55 2132
c65ebc55
JW		 2133(define_split
2134 [(set (match_operand:DI 0 "register_operand" "")
2135 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2136 (match_operand:DI 2 "register_operand" ""))
2137 (match_operand:DI 3 "register_operand" ""))
0551c32d 2138 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
c65ebc55
JW		 2139 (clobber (match_scratch:DI 5 ""))]
2140 "reload_completed"
2141 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2142 (match_dup 3)))
2143 (clobber (match_dup 0))])
c65ebc55 2144 (set (match_dup 0) (match_dup 5))
c65ebc55
JW		 2145 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2146 "")
2147
2148;; ??? There are highpart multiply and add instructions, but we have no way
2149;; to generate them.
2150
2151(define_insn "smuldi3_highpart"
0551c32d 2152 [(set (match_operand:DI 0 "fr_register_operand" "=f")
c65ebc55
JW		 2153 (truncate:DI
2154 (lshiftrt:TI
0551c32d
RH		 2155 (mult:TI (sign_extend:TI
2156 (match_operand:DI 1 "fr_register_operand" "f"))
2157 (sign_extend:TI
2158 (match_operand:DI 2 "fr_register_operand" "f")))
c65ebc55
JW		 2159 (const_int 64))))]
2160 ""
aebf2462 2161 "xmpy.h %0 = %1, %2"
52e12ad0 2162 [(set_attr "itanium_class" "xmpy")])
c65ebc55
JW		 2163
2164(define_insn "umuldi3_highpart"
0551c32d 2165 [(set (match_operand:DI 0 "fr_register_operand" "=f")
c65ebc55
JW		 2166 (truncate:DI
2167 (lshiftrt:TI
0551c32d
RH		 2168 (mult:TI (zero_extend:TI
2169 (match_operand:DI 1 "fr_register_operand" "f"))
2170 (zero_extend:TI
2171 (match_operand:DI 2 "fr_register_operand" "f")))
c65ebc55
JW		 2172 (const_int 64))))]
2173 ""
aebf2462 2174 "xmpy.hu %0 = %1, %2"
52e12ad0 2175 [(set_attr "itanium_class" "xmpy")])
c65ebc55
JW		 2176
2177(define_insn "negdi2"
0551c32d
RH		 2178 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2179 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
c65ebc55
JW		 2180 ""
2181 "sub %0 = r0, %1"
52e12ad0 2182 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 2183
2184(define_expand "absdi2"
2185 [(set (match_dup 2)
f2f90c63 2186 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
0551c32d 2187 (set (match_operand:DI 0 "gr_register_operand" "")
f2f90c63 2188 (if_then_else:DI (eq (match_dup 2) (const_int 0))
e5bde68a
RH		 2189 (neg:DI (match_dup 1))
2190 (match_dup 1)))]
c65ebc55
JW		 2191 ""
2192 "
2193{
f2f90c63 2194 operands[2] = gen_reg_rtx (BImode);
c65ebc55
JW		 2195}")
2196
2197(define_expand "smindi3"
2198 [(set (match_dup 3)
f2f90c63 2199 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
0551c32d
RH		 2200 (match_operand:DI 2 "gr_register_operand" "")))
2201 (set (match_operand:DI 0 "gr_register_operand" "")
f2f90c63 2202 (if_then_else:DI (ne (match_dup 3) (const_int 0))
c65ebc55
JW		 2203 (match_dup 2) (match_dup 1)))]
2204 ""
2205 "
2206{
f2f90c63 2207 operands[3] = gen_reg_rtx (BImode);
c65ebc55
JW		 2208}")
2209
2210(define_expand "smaxdi3"
2211 [(set (match_dup 3)
f2f90c63 2212 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
0551c32d
RH		 2213 (match_operand:DI 2 "gr_register_operand" "")))
2214 (set (match_operand:DI 0 "gr_register_operand" "")
f2f90c63 2215 (if_then_else:DI (ne (match_dup 3) (const_int 0))
c65ebc55
JW		 2216 (match_dup 1) (match_dup 2)))]
2217 ""
2218 "
2219{
f2f90c63 2220 operands[3] = gen_reg_rtx (BImode);
c65ebc55
JW		 2221}")
2222
2223(define_expand "umindi3"
2224 [(set (match_dup 3)
f2f90c63 2225 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
0551c32d
RH		 2226 (match_operand:DI 2 "gr_register_operand" "")))
2227 (set (match_operand:DI 0 "gr_register_operand" "")
f2f90c63 2228 (if_then_else:DI (ne (match_dup 3) (const_int 0))
c65ebc55
JW		 2229 (match_dup 2) (match_dup 1)))]
2230 ""
2231 "
2232{
f2f90c63 2233 operands[3] = gen_reg_rtx (BImode);
c65ebc55
JW		 2234}")
2235
2236(define_expand "umaxdi3"
2237 [(set (match_dup 3)
f2f90c63 2238 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
0551c32d
RH		 2239 (match_operand:DI 2 "gr_register_operand" "")))
2240 (set (match_operand:DI 0 "gr_register_operand" "")
f2f90c63 2241 (if_then_else:DI (ne (match_dup 3) (const_int 0))
c65ebc55
JW		 2242 (match_dup 1) (match_dup 2)))]
2243 ""
2244 "
2245{
f2f90c63 2246 operands[3] = gen_reg_rtx (BImode);
c65ebc55
JW		 2247}")
2248
2249(define_expand "ffsdi2"
2250 [(set (match_dup 6)
f2f90c63 2251 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
c65ebc55
JW		 2252 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2253 (set (match_dup 5) (const_int 0))
2254 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2255 (set (match_dup 4) (unspec:DI [(match_dup 3)] 8))
0551c32d 2256 (set (match_operand:DI 0 "gr_register_operand" "")
f2f90c63 2257 (if_then_else:DI (ne (match_dup 6) (const_int 0))
c65ebc55
JW		 2258 (match_dup 5) (match_dup 4)))]
2259 ""
2260 "
2261{
2262 operands[2] = gen_reg_rtx (DImode);
2263 operands[3] = gen_reg_rtx (DImode);
2264 operands[4] = gen_reg_rtx (DImode);
2265 operands[5] = gen_reg_rtx (DImode);
f2f90c63 2266 operands[6] = gen_reg_rtx (BImode);
c65ebc55
JW		 2267}")
2268
2269(define_insn "*popcnt"
0551c32d
RH		 2270 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2271 (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))]
c65ebc55
JW		 2272 ""
2273 "popcnt %0 = %1"
52e12ad0 2274 [(set_attr "itanium_class" "mmmul")])
c65ebc55 2275
655f2eb9
RH		 2276(define_expand "divdi3"
2277 [(set (match_operand:DI 0 "register_operand" "")
2278 (div:DI (match_operand:DI 1 "general_operand" "")
2279 (match_operand:DI 2 "general_operand" "")))]
23c108af 2280 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
655f2eb9
RH		 2281 "
2282{
2283 rtx op1_tf, op2_tf, op0_tf;
2284
2285 op0_tf = gen_reg_rtx (TFmode);
2286
2287 if (CONSTANT_P (operands[1]))
2288 operands[1] = force_reg (DImode, operands[1]);
2289 op1_tf = gen_reg_rtx (TFmode);
2290 expand_float (op1_tf, operands[1], 0);
2291
2292 if (CONSTANT_P (operands[2]))
2293 operands[2] = force_reg (DImode, operands[2]);
2294 op2_tf = gen_reg_rtx (TFmode);
2295 expand_float (op2_tf, operands[2], 0);
2296
2297 if (TARGET_INLINE_DIV_LAT)
2298 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2299 else
2300 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2301
2302 emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2303 DONE;
2304}")
2305
2306(define_expand "moddi3"
2307 [(set (match_operand:DI 0 "register_operand" "")
2308 (mod:SI (match_operand:DI 1 "general_operand" "")
2309 (match_operand:DI 2 "general_operand" "")))]
23c108af 2310 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
655f2eb9
RH		 2311 "
2312{
2313 rtx op2_neg, div;
2314
2315 div = gen_reg_rtx (DImode);
2316 emit_insn (gen_divdi3 (div, operands[1], operands[2]));
2317
2318 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2319
2320 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2321 DONE;
2322}")
2323
2324(define_expand "udivdi3"
2325 [(set (match_operand:DI 0 "register_operand" "")
2326 (udiv:DI (match_operand:DI 1 "general_operand" "")
2327 (match_operand:DI 2 "general_operand" "")))]
23c108af 2328 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
655f2eb9
RH		 2329 "
2330{
2331 rtx op1_tf, op2_tf, op0_tf;
2332
2333 op0_tf = gen_reg_rtx (TFmode);
2334
2335 if (CONSTANT_P (operands[1]))
2336 operands[1] = force_reg (DImode, operands[1]);
2337 op1_tf = gen_reg_rtx (TFmode);
2338 expand_float (op1_tf, operands[1], 1);
2339
2340 if (CONSTANT_P (operands[2]))
2341 operands[2] = force_reg (DImode, operands[2]);
2342 op2_tf = gen_reg_rtx (TFmode);
2343 expand_float (op2_tf, operands[2], 1);
2344
2345 if (TARGET_INLINE_DIV_LAT)
2346 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2347 else
2348 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2349
2350 emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2351 DONE;
2352}")
2353
2354(define_expand "umoddi3"
2355 [(set (match_operand:DI 0 "register_operand" "")
2356 (umod:DI (match_operand:DI 1 "general_operand" "")
2357 (match_operand:DI 2 "general_operand" "")))]
23c108af 2358 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
655f2eb9
RH		 2359 "
2360{
2361 rtx op2_neg, div;
2362
2363 div = gen_reg_rtx (DImode);
2364 emit_insn (gen_udivdi3 (div, operands[1], operands[2]));
2365
2366 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2367
2368 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2369 DONE;
2370}")
2371
2372(define_insn_and_split "divdi3_internal_lat"
2373 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2374 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2375 (match_operand:TF 2 "fr_register_operand" "f"))))
2376 (clobber (match_scratch:TF 3 "=&f"))
2377 (clobber (match_scratch:TF 4 "=&f"))
2378 (clobber (match_scratch:TF 5 "=&f"))
f2f90c63 2379 (clobber (match_scratch:BI 6 "=c"))]
23c108af 2380 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
655f2eb9
RH		 2381 "#"
2382 "&& reload_completed"
2383 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
f2f90c63 2384 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
655f2eb9
RH		 2385 (use (const_int 1))])
2386 (cond_exec (ne (match_dup 6) (const_int 0))
2387 (parallel [(set (match_dup 3)
2388 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2389 (match_dup 7)))
2390 (use (const_int 1))]))
2391 (cond_exec (ne (match_dup 6) (const_int 0))
2392 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2393 (use (const_int 1))]))
2394 (cond_exec (ne (match_dup 6) (const_int 0))
2395 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
2396 (use (const_int 1))]))
2397 (cond_exec (ne (match_dup 6) (const_int 0))
2398 (parallel [(set (match_dup 4)
2399 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
2400 (match_dup 4)))
2401 (use (const_int 1))]))
2402 (cond_exec (ne (match_dup 6) (const_int 0))
2403 (parallel [(set (match_dup 0)
2404 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2405 (match_dup 0)))
2406 (use (const_int 1))]))
2407 (cond_exec (ne (match_dup 6) (const_int 0))
2408 (parallel [(set (match_dup 3)
2409 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2410 (match_dup 4)))
2411 (use (const_int 1))]))
2412 (cond_exec (ne (match_dup 6) (const_int 0))
2413 (parallel [(set (match_dup 0)
2414 (plus:TF (mult:TF (match_dup 5) (match_dup 0))
2415 (match_dup 0)))
2416 (use (const_int 1))]))
2417 (cond_exec (ne (match_dup 6) (const_int 0))
2418 (parallel [(set (match_dup 4)
2419 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2420 (match_dup 1)))
2421 (use (const_int 1))]))
2422 (cond_exec (ne (match_dup 6) (const_int 0))
2423 (parallel [(set (match_dup 0)
2424 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2425 (match_dup 3)))
2426 (use (const_int 1))]))
2427 ]
2428 "operands[7] = CONST1_RTX (TFmode);"
2429 [(set_attr "predicable" "no")])
2430
2431(define_insn_and_split "divdi3_internal_thr"
2432 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2433 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2434 (match_operand:TF 2 "fr_register_operand" "f"))))
2435 (clobber (match_scratch:TF 3 "=&f"))
2436 (clobber (match_scratch:TF 4 "=f"))
f2f90c63 2437 (clobber (match_scratch:BI 5 "=c"))]
23c108af 2438 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
655f2eb9
RH		 2439 "#"
2440 "&& reload_completed"
2441 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
f2f90c63 2442 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
655f2eb9
RH		 2443 (use (const_int 1))])
2444 (cond_exec (ne (match_dup 5) (const_int 0))
2445 (parallel [(set (match_dup 3)
2446 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2447 (match_dup 6)))
2448 (use (const_int 1))]))
2449 (cond_exec (ne (match_dup 5) (const_int 0))
2450 (parallel [(set (match_dup 0)
2451 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2452 (match_dup 0)))
2453 (use (const_int 1))]))
2454 (cond_exec (ne (match_dup 5) (const_int 0))
2455 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
2456 (use (const_int 1))]))
2457 (cond_exec (ne (match_dup 5) (const_int 0))
2458 (parallel [(set (match_dup 0)
2459 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2460 (match_dup 0)))
2461 (use (const_int 1))]))
2462 (cond_exec (ne (match_dup 5) (const_int 0))
2463 (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1)))
2464 (use (const_int 1))]))
2465 (cond_exec (ne (match_dup 5) (const_int 0))
2466 (parallel [(set (match_dup 4)
2467 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2468 (match_dup 1)))
2469 (use (const_int 1))]))
2470 (cond_exec (ne (match_dup 5) (const_int 0))
2471 (parallel [(set (match_dup 0)
2472 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2473 (match_dup 3)))
2474 (use (const_int 1))]))
2475 ]
2476 "operands[6] = CONST1_RTX (TFmode);"
2477 [(set_attr "predicable" "no")])
c65ebc55
JW		 2478\f
2479;; ::::::::::::::::::::
2480;; ::
2481;; :: 32 bit floating point arithmetic
2482;; ::
2483;; ::::::::::::::::::::
2484
2485(define_insn "addsf3"
0551c32d
RH		 2486 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2487 (plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
2488 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2489 ""
aebf2462 2490 "fadd.s %0 = %1, %F2"
52e12ad0 2491 [(set_attr "itanium_class" "fmac")])
c65ebc55
JW		 2492
2493(define_insn "subsf3"
0551c32d
RH		 2494 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2495 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2496 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2497 ""
aebf2462 2498 "fsub.s %0 = %F1, %F2"
52e12ad0 2499 [(set_attr "itanium_class" "fmac")])
c65ebc55
JW		 2500
2501(define_insn "mulsf3"
0551c32d
RH		 2502 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2503 (mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
2504 (match_operand:SF 2 "fr_register_operand" "f")))]
c65ebc55 2505 ""
aebf2462 2506 "fmpy.s %0 = %1, %2"
52e12ad0 2507 [(set_attr "itanium_class" "fmac")])
c65ebc55
JW		 2508
2509(define_insn "abssf2"
0551c32d
RH		 2510 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2511 (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
c65ebc55 2512 ""
aebf2462 2513 "fabs %0 = %1"
52e12ad0 2514 [(set_attr "itanium_class" "fmisc")])
c65ebc55
JW		 2515
2516(define_insn "negsf2"
0551c32d
RH		 2517 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2518 (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
c65ebc55 2519 ""
aebf2462 2520 "fneg %0 = %1"
52e12ad0 2521 [(set_attr "itanium_class" "fmisc")])
c65ebc55
JW		 2522
2523(define_insn "*nabssf2"
0551c32d
RH		 2524 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2525 (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
c65ebc55 2526 ""
aebf2462 2527 "fnegabs %0 = %1"
52e12ad0 2528 [(set_attr "itanium_class" "fmisc")])
c65ebc55
JW		 2529
2530(define_insn "minsf3"
0551c32d
RH		 2531 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2532 (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
2533 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2534 ""
aebf2462 2535 "fmin %0 = %1, %F2"
52e12ad0 2536 [(set_attr "itanium_class" "fmisc")])
c65ebc55
JW		 2537
2538(define_insn "maxsf3"
0551c32d
RH		 2539 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2540 (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
2541 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2542 ""
aebf2462 2543 "fmax %0 = %1, %F2"
52e12ad0 2544 [(set_attr "itanium_class" "fmisc")])
c65ebc55 2545
655f2eb9 2546(define_insn "*maddsf4"
0551c32d
RH		 2547 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2548 (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2549 (match_operand:SF 2 "fr_register_operand" "f"))
2550 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2551 ""
aebf2462 2552 "fma.s %0 = %1, %2, %F3"
52e12ad0 2553 [(set_attr "itanium_class" "fmac")])
c65ebc55 2554
655f2eb9 2555(define_insn "*msubsf4"
0551c32d
RH		 2556 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2557 (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2558 (match_operand:SF 2 "fr_register_operand" "f"))
2559 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2560 ""
aebf2462 2561 "fms.s %0 = %1, %2, %F3"
52e12ad0 2562 [(set_attr "itanium_class" "fmac")])
c65ebc55
JW		 2563
2564(define_insn "*nmulsf3"
0551c32d
RH		 2565 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2566 (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2567 (match_operand:SF 2 "fr_register_operand" "f"))))]
c65ebc55 2568 ""
aebf2462 2569 "fnmpy.s %0 = %1, %2"
52e12ad0 2570 [(set_attr "itanium_class" "fmac")])
c65ebc55
JW		 2571
2572;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
2573
655f2eb9 2574(define_insn "*nmaddsf4"
0551c32d 2575 [(set (match_operand:SF 0 "fr_register_operand" "=f")
26102535
RH		 2576 (plus:SF (neg:SF (mult:SF
2577 (match_operand:SF 1 "fr_register_operand" "f")
2578 (match_operand:SF 2 "fr_register_operand" "f")))
0551c32d 2579 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2580 ""
aebf2462 2581 "fnma.s %0 = %1, %2, %F3"
52e12ad0 2582 [(set_attr "itanium_class" "fmac")])
c65ebc55 2583
26102535
RH		 2584(define_expand "divsf3"
2585 [(set (match_operand:SF 0 "fr_register_operand" "")
2586 (div:SF (match_operand:SF 1 "fr_register_operand" "")
2587 (match_operand:SF 2 "fr_register_operand" "")))]
23c108af 2588 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
26102535
RH		 2589 "
2590{
2591 rtx insn;
2592 if (TARGET_INLINE_DIV_LAT)
2593 insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
2594 else
2595 insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
2596 emit_insn (insn);
2597 DONE;
2598}")
2599
2600(define_insn_and_split "divsf3_internal_lat"
2601 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2602 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2603 (match_operand:SF 2 "fr_register_operand" "f")))
2604 (clobber (match_scratch:TF 3 "=&f"))
2605 (clobber (match_scratch:TF 4 "=f"))
f2f90c63 2606 (clobber (match_scratch:BI 5 "=c"))]
23c108af 2607 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
26102535
RH		 2608 "#"
2609 "&& reload_completed"
2610 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
f2f90c63 2611 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
26102535
RH		 2612 (use (const_int 1))])
2613 (cond_exec (ne (match_dup 5) (const_int 0))
2614 (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
2615 (use (const_int 1))]))
2616 (cond_exec (ne (match_dup 5) (const_int 0))
2617 (parallel [(set (match_dup 4)
2618 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2619 (match_dup 10)))
2620 (use (const_int 1))]))
2621 (cond_exec (ne (match_dup 5) (const_int 0))
2622 (parallel [(set (match_dup 3)
2623 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2624 (match_dup 3)))
2625 (use (const_int 1))]))
2626 (cond_exec (ne (match_dup 5) (const_int 0))
2627 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2628 (use (const_int 1))]))
2629 (cond_exec (ne (match_dup 5) (const_int 0))
2630 (parallel [(set (match_dup 3)
2631 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2632 (match_dup 3)))
2633 (use (const_int 1))]))
2634 (cond_exec (ne (match_dup 5) (const_int 0))
2635 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2636 (use (const_int 1))]))
2637 (cond_exec (ne (match_dup 5) (const_int 0))
2638 (parallel [(set (match_dup 9)
2639 (float_truncate:DF
2640 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2641 (match_dup 3))))
2642 (use (const_int 1))]))
2643 (cond_exec (ne (match_dup 5) (const_int 0))
2644 (set (match_dup 0)
2645 (float_truncate:SF (match_dup 6))))
2646 ]
2647 "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2648 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2649 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2650 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
2651 operands[10] = CONST1_RTX (TFmode);"
2652 [(set_attr "predicable" "no")])
2653
2654(define_insn_and_split "divsf3_internal_thr"
2655 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2656 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2657 (match_operand:SF 2 "fr_register_operand" "f")))
2658 (clobber (match_scratch:TF 3 "=&f"))
2659 (clobber (match_scratch:TF 4 "=f"))
f2f90c63 2660 (clobber (match_scratch:BI 5 "=c"))]
23c108af 2661 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
26102535
RH		 2662 "#"
2663 "&& reload_completed"
2664 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
f2f90c63 2665 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
26102535
RH		 2666 (use (const_int 1))])
2667 (cond_exec (ne (match_dup 5) (const_int 0))
2668 (parallel [(set (match_dup 3)
2669 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2670 (match_dup 10)))
2671 (use (const_int 1))]))
2672 (cond_exec (ne (match_dup 5) (const_int 0))
2673 (parallel [(set (match_dup 3)
2674 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
2675 (match_dup 3)))
2676 (use (const_int 1))]))
2677 (cond_exec (ne (match_dup 5) (const_int 0))
2678 (parallel [(set (match_dup 6)
2679 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
2680 (match_dup 6)))
2681 (use (const_int 1))]))
2682 (cond_exec (ne (match_dup 5) (const_int 0))
2683 (parallel [(set (match_dup 9)
2684 (float_truncate:SF
2685 (mult:TF (match_dup 7) (match_dup 6))))
2686 (use (const_int 1))]))
2687 (cond_exec (ne (match_dup 5) (const_int 0))
2688 (parallel [(set (match_dup 4)
2689 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3)))
2690 (match_dup 7)))
2691 (use (const_int 1))]))
2692 (cond_exec (ne (match_dup 5) (const_int 0))
2693 (set (match_dup 0)
2694 (float_truncate:SF
2695 (plus:TF (mult:TF (match_dup 4) (match_dup 6))
2696 (match_dup 3)))))
2697 ]
2698 "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2699 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2700 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2701 operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
2702 operands[10] = CONST1_RTX (TFmode);"
2703 [(set_attr "predicable" "no")])
c65ebc55
JW		 2704\f
2705;; ::::::::::::::::::::
2706;; ::
2707;; :: 64 bit floating point arithmetic
2708;; ::
2709;; ::::::::::::::::::::
2710
2711(define_insn "adddf3"
0551c32d
RH		 2712 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2713 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
2714 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2715 ""
aebf2462 2716 "fadd.d %0 = %1, %F2"
52e12ad0 2717 [(set_attr "itanium_class" "fmac")])
c65ebc55 2718
26102535
RH		 2719(define_insn "*adddf3_trunc"
2720 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2721 (float_truncate:SF
2722 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
2723 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2724 ""
aebf2462 2725 "fadd.s %0 = %1, %F2"
52e12ad0 2726 [(set_attr "itanium_class" "fmac")])
26102535 2727
c65ebc55 2728(define_insn "subdf3"
0551c32d
RH		 2729 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2730 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2731 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2732 ""
aebf2462 2733 "fsub.d %0 = %F1, %F2"
52e12ad0 2734 [(set_attr "itanium_class" "fmac")])
c65ebc55 2735
26102535
RH		 2736(define_insn "*subdf3_trunc"
2737 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2738 (float_truncate:SF
2739 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2740 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2741 ""
aebf2462 2742 "fsub.s %0 = %F1, %F2"
52e12ad0 2743 [(set_attr "itanium_class" "fmac")])
26102535 2744
c65ebc55 2745(define_insn "muldf3"
0551c32d
RH		 2746 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2747 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2748 (match_operand:DF 2 "fr_register_operand" "f")))]
c65ebc55 2749 ""
aebf2462 2750 "fmpy.d %0 = %1, %2"
52e12ad0 2751 [(set_attr "itanium_class" "fmac")])
c65ebc55 2752
26102535
RH		 2753(define_insn "*muldf3_trunc"
2754 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2755 (float_truncate:SF
2756 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2757 (match_operand:DF 2 "fr_register_operand" "f"))))]
2758 ""
aebf2462 2759 "fmpy.s %0 = %1, %2"
52e12ad0 2760 [(set_attr "itanium_class" "fmac")])
26102535 2761
c65ebc55 2762(define_insn "absdf2"
0551c32d
RH		 2763 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2764 (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
c65ebc55 2765 ""
aebf2462 2766 "fabs %0 = %1"
52e12ad0 2767 [(set_attr "itanium_class" "fmisc")])
c65ebc55
JW		 2768
2769(define_insn "negdf2"
0551c32d
RH		 2770 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2771 (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
c65ebc55 2772 ""
aebf2462 2773 "fneg %0 = %1"
52e12ad0 2774 [(set_attr "itanium_class" "fmisc")])
c65ebc55
JW		 2775
2776(define_insn "*nabsdf2"
0551c32d
RH		 2777 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2778 (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
c65ebc55 2779 ""
aebf2462 2780 "fnegabs %0 = %1"
52e12ad0 2781 [(set_attr "itanium_class" "fmisc")])
c65ebc55
JW		 2782
2783(define_insn "mindf3"
0551c32d
RH		 2784 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2785 (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
2786 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2787 ""
aebf2462 2788 "fmin %0 = %1, %F2"
52e12ad0 2789 [(set_attr "itanium_class" "fmisc")])
c65ebc55
JW		 2790
2791(define_insn "maxdf3"
0551c32d
RH		 2792 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2793 (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
2794 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2795 ""
aebf2462 2796 "fmax %0 = %1, %F2"
52e12ad0 2797 [(set_attr "itanium_class" "fmisc")])
c65ebc55 2798
655f2eb9 2799(define_insn "*madddf4"
0551c32d
RH		 2800 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2801 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2802 (match_operand:DF 2 "fr_register_operand" "f"))
2803 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2804 ""
aebf2462 2805 "fma.d %0 = %1, %2, %F3"
52e12ad0 2806 [(set_attr "itanium_class" "fmac")])
c65ebc55 2807
26102535
RH		 2808(define_insn "*madddf4_trunc"
2809 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2810 (float_truncate:SF
2811 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2812 (match_operand:DF 2 "fr_register_operand" "f"))
2813 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2814 ""
aebf2462 2815 "fma.s %0 = %1, %2, %F3"
52e12ad0 2816 [(set_attr "itanium_class" "fmac")])
26102535 2817
655f2eb9 2818(define_insn "*msubdf4"
0551c32d
RH		 2819 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2820 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2821 (match_operand:DF 2 "fr_register_operand" "f"))
2822 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2823 ""
aebf2462 2824 "fms.d %0 = %1, %2, %F3"
52e12ad0 2825 [(set_attr "itanium_class" "fmac")])
c65ebc55 2826
26102535
RH		 2827(define_insn "*msubdf4_trunc"
2828 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2829 (float_truncate:SF
2830 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2831 (match_operand:DF 2 "fr_register_operand" "f"))
2832 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2833 ""
aebf2462 2834 "fms.s %0 = %1, %2, %F3"
52e12ad0 2835 [(set_attr "itanium_class" "fmac")])
26102535 2836
c65ebc55 2837(define_insn "*nmuldf3"
0551c32d
RH		 2838 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2839 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2840 (match_operand:DF 2 "fr_register_operand" "f"))))]
c65ebc55 2841 ""
aebf2462 2842 "fnmpy.d %0 = %1, %2"
52e12ad0 2843 [(set_attr "itanium_class" "fmac")])
c65ebc55 2844
26102535
RH		 2845(define_insn "*nmuldf3_trunc"
2846 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2847 (float_truncate:SF
2848 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2849 (match_operand:DF 2 "fr_register_operand" "f")))))]
2850 ""
aebf2462 2851 "fnmpy.s %0 = %1, %2"
52e12ad0 2852 [(set_attr "itanium_class" "fmac")])
26102535 2853
c65ebc55
JW		 2854;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
2855
655f2eb9 2856(define_insn "*nmadddf4"
0551c32d 2857 [(set (match_operand:DF 0 "fr_register_operand" "=f")
26102535
RH		 2858 (plus:DF (neg:DF (mult:DF
2859 (match_operand:DF 1 "fr_register_operand" "f")
2860 (match_operand:DF 2 "fr_register_operand" "f")))
0551c32d 2861 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
c65ebc55 2862 ""
aebf2462 2863 "fnma.d %0 = %1, %2, %F3"
52e12ad0 2864 [(set_attr "itanium_class" "fmac")])
26102535
RH		 2865
2866(define_insn "*nmadddf4_alts"
2867 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2868 (plus:DF (neg:DF (mult:DF
2869 (match_operand:DF 1 "fr_register_operand" "f")
2870 (match_operand:DF 2 "fr_register_operand" "f")))
2871 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))
2872 (use (match_operand:SI 4 "const_int_operand" ""))]
2873 ""
aebf2462 2874 "fnma.d.s%4 %0 = %1, %2, %F3"
52e12ad0 2875 [(set_attr "itanium_class" "fmac")])
26102535
RH		 2876
2877(define_insn "*nmadddf4_trunc"
2878 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2879 (float_truncate:SF
2880 (plus:DF (neg:DF (mult:DF
2881 (match_operand:DF 1 "fr_register_operand" "f")
2882 (match_operand:DF 2 "fr_register_operand" "f")))
2883 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2884 ""
aebf2462 2885 "fnma.s %0 = %1, %2, %F3"
52e12ad0 2886 [(set_attr "itanium_class" "fmac")])
26102535
RH		 2887
2888(define_expand "divdf3"
2889 [(set (match_operand:DF 0 "fr_register_operand" "")
2890 (div:DF (match_operand:DF 1 "fr_register_operand" "")
2891 (match_operand:DF 2 "fr_register_operand" "")))]
23c108af 2892 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
26102535
RH		 2893 "
2894{
2895 rtx insn;
2896 if (TARGET_INLINE_DIV_LAT)
2897 insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
2898 else
2899 insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
2900 emit_insn (insn);
2901 DONE;
2902}")
2903
2904(define_insn_and_split "divdf3_internal_lat"
2905 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
2906 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
2907 (match_operand:DF 2 "fr_register_operand" "f")))
2908 (clobber (match_scratch:TF 3 "=&f"))
2909 (clobber (match_scratch:TF 4 "=&f"))
2910 (clobber (match_scratch:TF 5 "=&f"))
f2f90c63 2911 (clobber (match_scratch:BI 6 "=c"))]
23c108af 2912 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
26102535
RH		 2913 "#"
2914 "&& reload_completed"
2915 [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
f2f90c63 2916 (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5))
26102535
RH		 2917 (use (const_int 1))])
2918 (cond_exec (ne (match_dup 6) (const_int 0))
2919 (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
2920 (use (const_int 1))]))
2921 (cond_exec (ne (match_dup 6) (const_int 0))
2922 (parallel [(set (match_dup 4)
2923 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7)))
2924 (match_dup 12)))
2925 (use (const_int 1))]))
2926 (cond_exec (ne (match_dup 6) (const_int 0))
2927 (parallel [(set (match_dup 3)
2928 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2929 (match_dup 3)))
2930 (use (const_int 1))]))
2931 (cond_exec (ne (match_dup 6) (const_int 0))
2932 (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4)))
2933 (use (const_int 1))]))
2934 (cond_exec (ne (match_dup 6) (const_int 0))
2935 (parallel [(set (match_dup 7)
2936 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
2937 (match_dup 7)))
2938 (use (const_int 1))]))
2939 (cond_exec (ne (match_dup 6) (const_int 0))
2940 (parallel [(set (match_dup 3)
2941 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
2942 (match_dup 3)))
2943 (use (const_int 1))]))
2944 (cond_exec (ne (match_dup 6) (const_int 0))
2945 (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5)))
2946 (use (const_int 1))]))
2947 (cond_exec (ne (match_dup 6) (const_int 0))
2948 (parallel [(set (match_dup 7)
2949 (plus:TF (mult:TF (match_dup 5) (match_dup 7))
2950 (match_dup 7)))
2951 (use (const_int 1))]))
2952 (cond_exec (ne (match_dup 6) (const_int 0))
2953 (parallel [(set (match_dup 10)
2954 (float_truncate:DF
2955 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2956 (match_dup 3))))
2957 (use (const_int 1))]))
2958 (cond_exec (ne (match_dup 6) (const_int 0))
2959 (parallel [(set (match_dup 7)
2960 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
2961 (match_dup 7)))
2962 (use (const_int 1))]))
2963 (cond_exec (ne (match_dup 6) (const_int 0))
2964 (parallel [(set (match_dup 11)
2965 (float_truncate:DF
2966 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3)))
2967 (match_dup 8))))
2968 (use (const_int 1))]))
2969 (cond_exec (ne (match_dup 6) (const_int 0))
2970 (set (match_dup 0)
2971 (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7))
2972 (match_dup 3)))))
2973 ]
2974 "operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2975 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2976 operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2977 operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
2978 operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
2979 operands[12] = CONST1_RTX (TFmode);"
2980 [(set_attr "predicable" "no")])
2981
2982(define_insn_and_split "divdf3_internal_thr"
2983 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
2984 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
2985 (match_operand:DF 2 "fr_register_operand" "f")))
2986 (clobber (match_scratch:TF 3 "=&f"))
2987 (clobber (match_scratch:DF 4 "=f"))
f2f90c63 2988 (clobber (match_scratch:BI 5 "=c"))]
23c108af 2989 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
26102535
RH		 2990 "#"
2991 "&& reload_completed"
2992 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
f2f90c63 2993 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
26102535
RH		 2994 (use (const_int 1))])
2995 (cond_exec (ne (match_dup 5) (const_int 0))
2996 (parallel [(set (match_dup 3)
2997 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2998 (match_dup 10)))
2999 (use (const_int 1))]))
3000 (cond_exec (ne (match_dup 5) (const_int 0))
3001 (parallel [(set (match_dup 6)
3002 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3003 (match_dup 6)))
3004 (use (const_int 1))]))
3005 (cond_exec (ne (match_dup 5) (const_int 0))
3006 (parallel [(set (match_dup 3)
3007 (mult:TF (match_dup 3) (match_dup 3)))
3008 (use (const_int 1))]))
3009 (cond_exec (ne (match_dup 5) (const_int 0))
3010 (parallel [(set (match_dup 6)
3011 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3012 (match_dup 6)))
3013 (use (const_int 1))]))
3014 (cond_exec (ne (match_dup 5) (const_int 0))
3015 (parallel [(set (match_dup 3)
3016 (mult:TF (match_dup 3) (match_dup 3)))
3017 (use (const_int 1))]))
3018 (cond_exec (ne (match_dup 5) (const_int 0))
3019 (parallel [(set (match_dup 6)
3020 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3021 (match_dup 6)))
3022 (use (const_int 1))]))
3023 (cond_exec (ne (match_dup 5) (const_int 0))
3024 (parallel [(set (match_dup 9)
3025 (float_truncate:DF
3026 (mult:TF (match_dup 7) (match_dup 3))))
3027 (use (const_int 1))]))
3028 (cond_exec (ne (match_dup 5) (const_int 0))
3029 (parallel [(set (match_dup 4)
3030 (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9)))
3031 (match_dup 1)))
3032 (use (const_int 1))]))
3033 (cond_exec (ne (match_dup 5) (const_int 0))
3034 (set (match_dup 0)
3035 (plus:DF (mult:DF (match_dup 4) (match_dup 0))
3036 (match_dup 9))))
3037 ]
3038 "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3039 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3040 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3041 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3042 operands[10] = CONST1_RTX (TFmode);"
3043 [(set_attr "predicable" "no")])
3f622353
RH		 3044\f
3045;; ::::::::::::::::::::
3046;; ::
3047;; :: 80 bit floating point arithmetic
3048;; ::
3049;; ::::::::::::::::::::
3050
3051(define_insn "addtf3"
0551c32d 3052 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353
RH		 3053 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3054 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
23c108af 3055 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3056 "fadd %0 = %F1, %F2"
52e12ad0 3057 [(set_attr "itanium_class" "fmac")])
3f622353 3058
26102535
RH		 3059(define_insn "*addtf3_truncsf"
3060 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3061 (float_truncate:SF
3062 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3063 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3064 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3065 "fadd.s %0 = %F1, %F2"
52e12ad0 3066 [(set_attr "itanium_class" "fmac")])
26102535
RH		 3067
3068(define_insn "*addtf3_truncdf"
3069 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3070 (float_truncate:DF
3071 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3072 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3073 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3074 "fadd.d %0 = %F1, %F2"
52e12ad0 3075 [(set_attr "itanium_class" "fmac")])
26102535 3076
3f622353 3077(define_insn "subtf3"
0551c32d 3078 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353
RH		 3079 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3080 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
23c108af 3081 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3082 "fsub %0 = %F1, %F2"
52e12ad0 3083 [(set_attr "itanium_class" "fmac")])
3f622353 3084
26102535
RH		 3085(define_insn "*subtf3_truncsf"
3086 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3087 (float_truncate:SF
3088 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3089 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3090 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3091 "fsub.s %0 = %F1, %F2"
52e12ad0 3092 [(set_attr "itanium_class" "fmac")])
26102535
RH		 3093
3094(define_insn "*subtf3_truncdf"
3095 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3096 (float_truncate:DF
3097 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3098 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3099 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3100 "fsub.d %0 = %F1, %F2"
52e12ad0 3101 [(set_attr "itanium_class" "fmac")])
26102535 3102
3f622353 3103(define_insn "multf3"
0551c32d 3104 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353
RH		 3105 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3106 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
23c108af 3107 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3108 "fmpy %0 = %F1, %F2"
52e12ad0 3109 [(set_attr "itanium_class" "fmac")])
3f622353 3110
26102535
RH		 3111(define_insn "*multf3_truncsf"
3112 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3113 (float_truncate:SF
3114 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3115 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3116 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3117 "fmpy.s %0 = %F1, %F2"
52e12ad0 3118 [(set_attr "itanium_class" "fmac")])
26102535
RH		 3119
3120(define_insn "*multf3_truncdf"
3121 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3122 (float_truncate:DF
3123 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3124 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3125 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3126 "fmpy.d %0 = %F1, %F2"
52e12ad0 3127 [(set_attr "itanium_class" "fmac")])
26102535 3128
655f2eb9
RH		 3129(define_insn "*multf3_alts"
3130 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3131 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3132 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3133 (use (match_operand:SI 3 "const_int_operand" ""))]
23c108af 3134 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3135 "fmpy.s%3 %0 = %F1, %F2"
52e12ad0 3136 [(set_attr "itanium_class" "fmac")])
655f2eb9 3137
26102535
RH		 3138(define_insn "*multf3_truncsf_alts"
3139 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3140 (float_truncate:SF
3141 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3142 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3143 (use (match_operand:SI 3 "const_int_operand" ""))]
23c108af 3144 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3145 "fmpy.s.s%3 %0 = %F1, %F2"
52e12ad0 3146 [(set_attr "itanium_class" "fmac")])
26102535
RH		 3147
3148(define_insn "*multf3_truncdf_alts"
3149 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3150 (float_truncate:DF
3151 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3152 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3153 (use (match_operand:SI 3 "const_int_operand" ""))]
23c108af 3154 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3155 "fmpy.d.s%3 %0 = %F1, %F2"
52e12ad0 3156 [(set_attr "itanium_class" "fmac")])
26102535 3157
3f622353 3158(define_insn "abstf2"
0551c32d 3159 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353 3160 (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
23c108af 3161 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3162 "fabs %0 = %F1"
52e12ad0 3163 [(set_attr "itanium_class" "fmisc")])
3f622353
RH		 3164
3165(define_insn "negtf2"
0551c32d 3166 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353 3167 (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
23c108af 3168 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3169 "fneg %0 = %F1"
52e12ad0 3170 [(set_attr "itanium_class" "fmisc")])
3f622353
RH		 3171
3172(define_insn "*nabstf2"
0551c32d 3173 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353 3174 (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3175 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3176 "fnegabs %0 = %F1"
52e12ad0 3177 [(set_attr "itanium_class" "fmisc")])
3f622353
RH		 3178
3179(define_insn "mintf3"
0551c32d 3180 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353
RH		 3181 (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3182 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
23c108af 3183 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3184 "fmin %0 = %F1, %F2"
52e12ad0 3185 [(set_attr "itanium_class" "fmisc")])
3f622353
RH		 3186
3187(define_insn "maxtf3"
0551c32d 3188 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353
RH		 3189 (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3190 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
23c108af 3191 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3192 "fmax %0 = %F1, %F2"
52e12ad0 3193 [(set_attr "itanium_class" "fmisc")])
3f622353 3194
655f2eb9 3195(define_insn "*maddtf4"
0551c32d 3196 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353
RH		 3197 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3198 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3199 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
23c108af 3200 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3201 "fma %0 = %F1, %F2, %F3"
52e12ad0 3202 [(set_attr "itanium_class" "fmac")])
3f622353 3203
26102535
RH		 3204(define_insn "*maddtf4_truncsf"
3205 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3206 (float_truncate:SF
3207 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3208 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3209 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3210 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3211 "fma.s %0 = %F1, %F2, %F3"
52e12ad0 3212 [(set_attr "itanium_class" "fmac")])
26102535
RH		 3213
3214(define_insn "*maddtf4_truncdf"
3215 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3216 (float_truncate:DF
3217 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3218 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3219 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3220 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3221 "fma.d %0 = %F1, %F2, %F3"
52e12ad0 3222 [(set_attr "itanium_class" "fmac")])
26102535 3223
655f2eb9
RH		 3224(define_insn "*maddtf4_alts"
3225 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3226 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3227 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3228 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3229 (use (match_operand:SI 4 "const_int_operand" ""))]
23c108af 3230 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3231 "fma.s%4 %0 = %F1, %F2, %F3"
52e12ad0 3232 [(set_attr "itanium_class" "fmac")])
655f2eb9 3233
26102535
RH		 3234(define_insn "*maddtf4_alts_truncdf"
3235 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3236 (float_truncate:DF
3237 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3238 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3239 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3240 (use (match_operand:SI 4 "const_int_operand" ""))]
23c108af 3241 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3242 "fma.d.s%4 %0 = %F1, %F2, %F3"
52e12ad0 3243 [(set_attr "itanium_class" "fmac")])
26102535 3244
655f2eb9 3245(define_insn "*msubtf4"
0551c32d 3246 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353
RH		 3247 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3248 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3249 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
23c108af 3250 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3251 "fms %0 = %F1, %F2, %F3"
52e12ad0 3252 [(set_attr "itanium_class" "fmac")])
3f622353 3253
26102535
RH		 3254(define_insn "*msubtf4_truncsf"
3255 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3256 (float_truncate:SF
3257 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3258 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3259 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3260 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3261 "fms.s %0 = %F1, %F2, %F3"
52e12ad0 3262 [(set_attr "itanium_class" "fmac")])
26102535
RH		 3263
3264(define_insn "*msubtf4_truncdf"
3265 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3266 (float_truncate:DF
3267 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3268 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3269 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3270 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3271 "fms.d %0 = %F1, %F2, %F3"
52e12ad0 3272 [(set_attr "itanium_class" "fmac")])
26102535 3273
3f622353 3274(define_insn "*nmultf3"
0551c32d 3275 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353
RH		 3276 (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3277 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3278 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3279 "fnmpy %0 = %F1, %F2"
52e12ad0 3280 [(set_attr "itanium_class" "fmac")])
c65ebc55 3281
26102535
RH		 3282(define_insn "*nmultf3_truncsf"
3283 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3284 (float_truncate:SF
3285 (neg:TF (mult:TF
3286 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3287 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
23c108af 3288 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3289 "fnmpy.s %0 = %F1, %F2"
52e12ad0 3290 [(set_attr "itanium_class" "fmac")])
26102535
RH		 3291
3292(define_insn "*nmultf3_truncdf"
3293 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3294 (float_truncate:DF
3295 (neg:TF (mult:TF
3296 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3297 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
23c108af 3298 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3299 "fnmpy.d %0 = %F1, %F2"
52e12ad0 3300 [(set_attr "itanium_class" "fmac")])
26102535 3301
3f622353
RH		 3302;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
3303
655f2eb9 3304(define_insn "*nmaddtf4"
0551c32d 3305 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3f622353
RH		 3306 (plus:TF (neg:TF (mult:TF
3307 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3308 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3309 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
23c108af 3310 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3311 "fnma %0 = %F1, %F2, %F3"
52e12ad0 3312 [(set_attr "itanium_class" "fmac")])
655f2eb9 3313
26102535
RH		 3314(define_insn "*nmaddtf4_truncsf"
3315 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3316 (float_truncate:SF
3317 (plus:TF (neg:TF (mult:TF
3318 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3319 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3320 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3321 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3322 "fnma.s %0 = %F1, %F2, %F3"
52e12ad0 3323 [(set_attr "itanium_class" "fmac")])
26102535
RH		 3324
3325(define_insn "*nmaddtf4_truncdf"
3326 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3327 (float_truncate:DF
3328 (plus:TF (neg:TF (mult:TF
3329 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3330 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3331 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
23c108af 3332 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3333 "fnma.d %0 = %F1, %F2, %F3"
52e12ad0 3334 [(set_attr "itanium_class" "fmac")])
26102535 3335
655f2eb9
RH		 3336(define_insn "*nmaddtf4_alts"
3337 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3338 (plus:TF (neg:TF (mult:TF
3339 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3340 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3341 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3342 (use (match_operand:SI 4 "const_int_operand" ""))]
23c108af 3343 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3344 "fnma.s%4 %0 = %F1, %F2, %F3"
52e12ad0 3345 [(set_attr "itanium_class" "fmac")])
655f2eb9 3346
26102535
RH		 3347(define_insn "*nmaddtf4_truncdf_alts"
3348 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3349 (float_truncate:DF
3350 (plus:TF (neg:TF
3351 (mult:TF
3352 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3353 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3354 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3355 (use (match_operand:SI 4 "const_int_operand" ""))]
23c108af 3356 "INTEL_EXTENDED_IEEE_FORMAT"
aebf2462 3357 "fnma.d.s%4 %0 = %F1, %F2, %F3"
52e12ad0 3358 [(set_attr "itanium_class" "fmac")])
26102535
RH		 3359
3360(define_expand "divtf3"
3361 [(set (match_operand:TF 0 "fr_register_operand" "")
3362 (div:TF (match_operand:TF 1 "fr_register_operand" "")
3363 (match_operand:TF 2 "fr_register_operand" "")))]
23c108af 3364 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
26102535
RH		 3365 "
3366{
3367 rtx insn;
3368 if (TARGET_INLINE_DIV_LAT)
3369 insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
3370 else
3371 insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
3372 emit_insn (insn);
3373 DONE;
3374}")
3375
3376(define_insn_and_split "divtf3_internal_lat"
3377 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3378 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3379 (match_operand:TF 2 "fr_register_operand" "f")))
3380 (clobber (match_scratch:TF 3 "=&f"))
3381 (clobber (match_scratch:TF 4 "=&f"))
3382 (clobber (match_scratch:TF 5 "=&f"))
3383 (clobber (match_scratch:TF 6 "=&f"))
f2f90c63 3384 (clobber (match_scratch:BI 7 "=c"))]
23c108af 3385 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
26102535
RH		 3386 "#"
3387 "&& reload_completed"
3388 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
f2f90c63 3389 (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
26102535
RH		 3390 (use (const_int 1))])
3391 (cond_exec (ne (match_dup 7) (const_int 0))
3392 (parallel [(set (match_dup 3)
3393 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3394 (match_dup 8)))
3395 (use (const_int 1))]))
3396 (cond_exec (ne (match_dup 7) (const_int 0))
3397 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3398 (use (const_int 1))]))
3399 (cond_exec (ne (match_dup 7) (const_int 0))
3400 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
3401 (use (const_int 1))]))
3402 (cond_exec (ne (match_dup 7) (const_int 0))
3403 (parallel [(set (match_dup 6)
3404 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
3405 (match_dup 3)))
3406 (use (const_int 1))]))
3407 (cond_exec (ne (match_dup 7) (const_int 0))
3408 (parallel [(set (match_dup 3)
3409 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
3410 (match_dup 3)))
3411 (use (const_int 1))]))
3412 (cond_exec (ne (match_dup 7) (const_int 0))
3413 (parallel [(set (match_dup 5)
3414 (plus:TF (mult:TF (match_dup 6) (match_dup 0))
3415 (match_dup 0)))
3416 (use (const_int 1))]))
3417 (cond_exec (ne (match_dup 7) (const_int 0))
3418 (parallel [(set (match_dup 0)
3419 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
3420 (match_dup 0)))
3421 (use (const_int 1))]))
3422 (cond_exec (ne (match_dup 7) (const_int 0))
3423 (parallel [(set (match_dup 4)
3424 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3425 (match_dup 1)))
3426 (use (const_int 1))]))
3427 (cond_exec (ne (match_dup 7) (const_int 0))
3428 (parallel [(set (match_dup 3)
3429 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3430 (match_dup 4)))
3431 (use (const_int 1))]))
3432 (cond_exec (ne (match_dup 7) (const_int 0))
3433 (parallel [(set (match_dup 5)
3434 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3435 (match_dup 8)))
3436 (use (const_int 1))]))
3437 (cond_exec (ne (match_dup 7) (const_int 0))
3438 (parallel [(set (match_dup 0)
3439 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3440 (match_dup 0)))
3441 (use (const_int 1))]))
3442 (cond_exec (ne (match_dup 7) (const_int 0))
3443 (parallel [(set (match_dup 4)
3444 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3445 (match_dup 1)))
3446 (use (const_int 1))]))
3447 (cond_exec (ne (match_dup 7) (const_int 0))
3448 (set (match_dup 0)
3449 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3450 (match_dup 3))))
3451 ]
3452 "operands[8] = CONST1_RTX (TFmode);"
3453 [(set_attr "predicable" "no")])
3454
3455(define_insn_and_split "divtf3_internal_thr"
3456 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3457 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3458 (match_operand:TF 2 "fr_register_operand" "f")))
3459 (clobber (match_scratch:TF 3 "=&f"))
3460 (clobber (match_scratch:TF 4 "=&f"))
f2f90c63 3461 (clobber (match_scratch:BI 5 "=c"))]
23c108af 3462 "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
26102535
RH		 3463 "#"
3464 "&& reload_completed"
3465 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
f2f90c63 3466 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
26102535
RH		 3467 (use (const_int 1))])
3468 (cond_exec (ne (match_dup 5) (const_int 0))
3469 (parallel [(set (match_dup 3)
3470 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3471 (match_dup 6)))
3472 (use (const_int 1))]))
3473 (cond_exec (ne (match_dup 5) (const_int 0))
3474 (parallel [(set (match_dup 4)
3475 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3476 (match_dup 0)))
3477 (use (const_int 1))]))
3478 (cond_exec (ne (match_dup 5) (const_int 0))
3479 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
3480 (use (const_int 1))]))
3481 (cond_exec (ne (match_dup 5) (const_int 0))
3482 (parallel [(set (match_dup 3)
3483 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
3484 (match_dup 4)))
3485 (use (const_int 1))]))
3486 (cond_exec (ne (match_dup 5) (const_int 0))
3487 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3488 (use (const_int 1))]))
3489 (cond_exec (ne (match_dup 5) (const_int 0))
3490 (parallel [(set (match_dup 0)
3491 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3492 (match_dup 6)))
3493 (use (const_int 1))]))
3494 (cond_exec (ne (match_dup 5) (const_int 0))
3495 (parallel [(set (match_dup 0)
3496 (plus:TF (mult:TF (match_dup 0) (match_dup 3))
3497 (match_dup 3)))
3498 (use (const_int 1))]))
3499 (cond_exec (ne (match_dup 5) (const_int 0))
3500 (parallel [(set (match_dup 3)
3501 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3502 (match_dup 1)))
3503 (use (const_int 1))]))
3504 (cond_exec (ne (match_dup 5) (const_int 0))
3505 (parallel [(set (match_dup 3)
3506 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3507 (match_dup 4)))
3508 (use (const_int 1))]))
3509 (cond_exec (ne (match_dup 5) (const_int 0))
3510 (parallel [(set (match_dup 4)
3511 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3512 (match_dup 6)))
3513 (use (const_int 1))]))
3514 (cond_exec (ne (match_dup 5) (const_int 0))
3515 (parallel [(set (match_dup 0)
3516 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3517 (match_dup 0)))
3518 (use (const_int 1))]))
3519 (cond_exec (ne (match_dup 5) (const_int 0))
3520 (parallel [(set (match_dup 4)
3521 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3522 (match_dup 1)))
3523 (use (const_int 1))]))
3524 (cond_exec (ne (match_dup 5) (const_int 0))
3525 (set (match_dup 0)
3526 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3527 (match_dup 3))))
3528 ]
3529 "operands[6] = CONST1_RTX (TFmode);"
3530 [(set_attr "predicable" "no")])
3531
3532;; ??? frcpa works like cmp.foo.unc.
3533
655f2eb9
RH		 3534(define_insn "*recip_approx"
3535 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3536 (div:TF (const_int 1)
3537 (match_operand:TF 3 "fr_register_operand" "f")))
f2f90c63
RH		 3538 (set (match_operand:BI 1 "register_operand" "=c")
3539 (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
655f2eb9
RH		 3540 (match_dup 3)] 5))
3541 (use (match_operand:SI 4 "const_int_operand" ""))]
23c108af 3542 "INTEL_EXTENDED_IEEE_FORMAT"
655f2eb9 3543 "frcpa.s%4 %0, %1 = %2, %3"
52e12ad0 3544 [(set_attr "itanium_class" "fmisc")
26102535 3545 (set_attr "predicable" "no")])
c65ebc55
JW		 3546\f
3547;; ::::::::::::::::::::
3548;; ::
3549;; :: 32 bit Integer Shifts and Rotates
3550;; ::
3551;; ::::::::::::::::::::
3552
9c668921 3553(define_expand "ashlsi3"
0551c32d
RH		 3554 [(set (match_operand:SI 0 "gr_register_operand" "")
3555 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
3556 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
9c668921
RH		 3557 ""
3558 "
3559{
3560 if (GET_CODE (operands[2]) != CONST_INT)
3561 {
3562 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
3563 we've got to get rid of stray bits outside the SImode register. */
3564 rtx subshift = gen_reg_rtx (DImode);
3565 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3566 operands[2] = subshift;
3567 }
3568}")
3569
3570(define_insn "*ashlsi3_internal"
0551c32d
RH		 3571 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
3572 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
3573 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
c65ebc55 3574 ""
041f25e6
RH		 3575 "@
3576 shladd %0 = %1, %2, r0
3577 dep.z %0 = %1, %2, %E2
3578 shl %0 = %1, %2"
52e12ad0 3579 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
c65ebc55
JW		 3580
3581(define_expand "ashrsi3"
0551c32d
RH		 3582 [(set (match_operand:SI 0 "gr_register_operand" "")
3583 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3584 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
c65ebc55
JW		 3585 ""
3586 "
3587{
041f25e6
RH		 3588 rtx subtarget = gen_reg_rtx (DImode);
3589 if (GET_CODE (operands[2]) == CONST_INT)
3590 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
3591 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3592 else
3593 {
9c668921 3594 rtx subshift = gen_reg_rtx (DImode);
041f25e6 3595 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
9c668921
RH		 3596 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3597 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
041f25e6
RH		 3598 }
3599 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3600 DONE;
c65ebc55
JW		 3601}")
3602
c65ebc55 3603(define_expand "lshrsi3"
0551c32d
RH		 3604 [(set (match_operand:SI 0 "gr_register_operand" "")
3605 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3606 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
c65ebc55
JW		 3607 ""
3608 "
3609{
041f25e6
RH		 3610 rtx subtarget = gen_reg_rtx (DImode);
3611 if (GET_CODE (operands[2]) == CONST_INT)
3612 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
3613 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3614 else
3615 {
9c668921 3616 rtx subshift = gen_reg_rtx (DImode);
041f25e6 3617 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
9c668921
RH		 3618 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3619 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
041f25e6
RH		 3620 }
3621 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3622 DONE;
c65ebc55
JW		 3623}")
3624
c65ebc55 3625;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
66db6b45
RH		 3626;; here, instead of 64 like the patterns above. Keep the pattern together
3627;; until after combine; otherwise it won't get matched often.
c65ebc55
JW		 3628
3629(define_expand "rotrsi3"
66db6b45
RH		 3630 [(set (match_operand:SI 0 "gr_register_operand" "")
3631 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
3632 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3633 ""
3634 "
3635{
3636 if (GET_MODE (operands[2]) != VOIDmode)
3637 {
3638 rtx tmp = gen_reg_rtx (DImode);
3639 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
3640 operands[2] = tmp;
3641 }
3642}")
3643
3644(define_insn_and_split "*rotrsi3_internal"
3645 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
3646 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
3647 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
3648 ""
3649 "#"
3650 "reload_completed"
c65ebc55 3651 [(set (match_dup 3)
66db6b45 3652 (ior:DI (zero_extend:DI (match_dup 1))
c65ebc55
JW		 3653 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3654 (set (match_dup 3)
66db6b45
RH		 3655 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3656 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
3657
3658(define_expand "rotlsi3"
3659 [(set (match_operand:SI 0 "gr_register_operand" "")
3660 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
3661 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
c65ebc55
JW		 3662 ""
3663 "
3664{
3665 if (! shift_32bit_count_operand (operands[2], SImode))
66db6b45
RH		 3666 {
3667 rtx tmp = gen_reg_rtx (SImode);
3668 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
3669 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
3670 DONE;
3671 }
c65ebc55 3672}")
66db6b45
RH		 3673
3674(define_insn_and_split "*rotlsi3_internal"
3675 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3676 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
3677 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
3678 ""
3679 "#"
3680 "reload_completed"
3681 [(set (match_dup 3)
3682 (ior:DI (zero_extend:DI (match_dup 1))
3683 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3684 (set (match_dup 3)
3685 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3686 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
3687 operands[2] = GEN_INT (32 - INTVAL (operands[2]));")
c65ebc55
JW		 3688\f
3689;; ::::::::::::::::::::
3690;; ::
3691;; :: 64 bit Integer Shifts and Rotates
3692;; ::
3693;; ::::::::::::::::::::
3694
3695(define_insn "ashldi3"
52e12ad0
BS		 3696 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
3697 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
3698 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
c65ebc55 3699 ""
041f25e6
RH		 3700 "@
3701 shladd %0 = %1, %2, r0
52e12ad0 3702 shl %0 = %1, %2
041f25e6 3703 shl %0 = %1, %2"
52e12ad0 3704 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
c65ebc55
JW		 3705
3706;; ??? Maybe combine this with the multiply and add instruction?
3707
3708(define_insn "*shladd"
0551c32d
RH		 3709 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3710 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
c65ebc55 3711 (match_operand:DI 2 "shladd_operand" "n"))
0551c32d 3712 (match_operand:DI 3 "gr_register_operand" "r")))]
c65ebc55
JW		 3713 ""
3714 "shladd %0 = %1, %S2, %3"
52e12ad0 3715 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 3716
3717;; This can be created by register elimination if operand3 of shladd is an
3718;; eliminable register or has reg_equiv_constant set.
3719
3720;; We have to use nonmemory_operand for operand 4, to ensure that the
3721;; validate_changes call inside eliminate_regs will always succeed. If it
3722;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
3723;; incorrectly.
3724
5527bf14 3725(define_insn_and_split "*shladd_elim"
0551c32d
RH		 3726 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
3727 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
c65ebc55 3728 (match_operand:DI 2 "shladd_operand" "n"))
5527bf14 3729 (match_operand:DI 3 "nonmemory_operand" "r"))
c65ebc55
JW		 3730 (match_operand:DI 4 "nonmemory_operand" "rI")))]
3731 "reload_in_progress"
5527bf14 3732 "* abort ();"
c65ebc55
JW		 3733 "reload_completed"
3734 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
3735 (match_dup 3)))
c65ebc55 3736 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5527bf14 3737 ""
52e12ad0 3738 [(set_attr "itanium_class" "unknown")])
c65ebc55
JW		 3739
3740(define_insn "ashrdi3"
52e12ad0
BS		 3741 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3742 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3743 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
c65ebc55 3744 ""
52e12ad0
BS		 3745 "@
3746 shr %0 = %1, %2
3747 shr %0 = %1, %2"
3748 [(set_attr "itanium_class" "mmshf,mmshfi")])
c65ebc55
JW		 3749
3750(define_insn "lshrdi3"
52e12ad0
BS		 3751 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3752 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3753 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
c65ebc55 3754 ""
52e12ad0
BS		 3755 "@
3756 shr.u %0 = %1, %2
3757 shr.u %0 = %1, %2"
3758 [(set_attr "itanium_class" "mmshf,mmshfi")])
c65ebc55
JW		 3759
3760;; Using a predicate that accepts only constants doesn't work, because optabs
3761;; will load the operand into a register and call the pattern if the predicate
3762;; did not accept it on the first try. So we use nonmemory_operand and then
3763;; verify that we have an appropriate constant in the expander.
3764
3765(define_expand "rotrdi3"
0551c32d
RH		 3766 [(set (match_operand:DI 0 "gr_register_operand" "")
3767 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
c65ebc55
JW		 3768 (match_operand:DI 2 "nonmemory_operand" "")))]
3769 ""
3770 "
3771{
3772 if (! shift_count_operand (operands[2], DImode))
3773 FAIL;
3774}")
3775
3776(define_insn "*rotrdi3_internal"
0551c32d
RH		 3777 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3778 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
c65ebc55
JW		 3779 (match_operand:DI 2 "shift_count_operand" "M")))]
3780 ""
3781 "shrp %0 = %1, %1, %2"
52e12ad0 3782 [(set_attr "itanium_class" "ishf")])
c65ebc55 3783
66db6b45
RH		 3784(define_expand "rotldi3"
3785 [(set (match_operand:DI 0 "gr_register_operand" "")
3786 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
3787 (match_operand:DI 2 "nonmemory_operand" "")))]
3788 ""
3789 "
3790{
3791 if (! shift_count_operand (operands[2], DImode))
3792 FAIL;
3793}")
3794
3795(define_insn "*rotldi3_internal"
3796 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3797 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
3798 (match_operand:DI 2 "shift_count_operand" "M")))]
3799 ""
3800 "shrp %0 = %1, %1, %e2"
52e12ad0 3801 [(set_attr "itanium_class" "ishf")])
c65ebc55
JW		 3802\f
3803;; ::::::::::::::::::::
3804;; ::
058557c4 3805;; :: 32 bit Integer Logical operations
c65ebc55
JW		 3806;; ::
3807;; ::::::::::::::::::::
3808
3809;; We don't seem to need any other 32-bit logical operations, because gcc
3810;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
3811;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
3812;; This doesn't work for unary logical operations, because we don't call
3813;; apply_distributive_law for them.
3814
3815;; ??? Likewise, this doesn't work for andnot, which isn't handled by
3816;; apply_distributive_law. We get inefficient code for
3817;; int sub4 (int i, int j) { return i & ~j; }
3818;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
3819;; (zero_extend (and (not A) B)) in combine.
3820;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
3821;; one_cmplsi2 pattern.
3822
058557c4 3823(define_insn "one_cmplsi2"
0551c32d
RH		 3824 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3825 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
c65ebc55
JW		 3826 ""
3827 "andcm %0 = -1, %1"
52e12ad0 3828 [(set_attr "itanium_class" "ilog")])
c65ebc55
JW		 3829\f
3830;; ::::::::::::::::::::
3831;; ::
058557c4 3832;; :: 64 bit Integer Logical operations
c65ebc55
JW		 3833;; ::
3834;; ::::::::::::::::::::
3835
3836(define_insn "anddi3"
0551c32d
RH		 3837 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3838 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3839 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
c65ebc55
JW		 3840 ""
3841 "@
3842 and %0 = %2, %1
aebf2462 3843 fand %0 = %2, %1"
52e12ad0 3844 [(set_attr "itanium_class" "ilog,fmisc")])
c65ebc55
JW		 3845
3846(define_insn "*andnot"
0551c32d
RH		 3847 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3848 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
3849 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
c65ebc55
JW		 3850 ""
3851 "@
3852 andcm %0 = %2, %1
aebf2462 3853 fandcm %0 = %2, %1"
52e12ad0 3854 [(set_attr "itanium_class" "ilog,fmisc")])
c65ebc55
JW		 3855
3856(define_insn "iordi3"
0551c32d
RH		 3857 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3858 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3859 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
c65ebc55
JW		 3860 ""
3861 "@
3862 or %0 = %2, %1
aebf2462 3863 for %0 = %2, %1"
52e12ad0 3864 [(set_attr "itanium_class" "ilog,fmisc")])
c65ebc55
JW		 3865
3866(define_insn "xordi3"
0551c32d
RH		 3867 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3868 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3869 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
c65ebc55
JW		 3870 ""
3871 "@
3872 xor %0 = %2, %1
aebf2462 3873 fxor %0 = %2, %1"
52e12ad0 3874 [(set_attr "itanium_class" "ilog,fmisc")])
c65ebc55
JW		 3875
3876(define_insn "one_cmpldi2"
0551c32d
RH		 3877 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3878 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
c65ebc55
JW		 3879 ""
3880 "andcm %0 = -1, %1"
52e12ad0 3881 [(set_attr "itanium_class" "ilog")])
c65ebc55
JW		 3882\f
3883;; ::::::::::::::::::::
3884;; ::
3885;; :: Comparisons
3886;; ::
3887;; ::::::::::::::::::::
3888
f2f90c63
RH		 3889(define_expand "cmpbi"
3890 [(set (cc0)
3891 (compare (match_operand:BI 0 "register_operand" "")
3892 (match_operand:BI 1 "const_int_operand" "")))]
3893 ""
3894 "
3895{
3896 ia64_compare_op0 = operands[0];
3897 ia64_compare_op1 = operands[1];
3898 DONE;
3899}")
3900
c65ebc55
JW		 3901(define_expand "cmpsi"
3902 [(set (cc0)
0551c32d
RH		 3903 (compare (match_operand:SI 0 "gr_register_operand" "")
3904 (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
c65ebc55
JW		 3905 ""
3906 "
3907{
3908 ia64_compare_op0 = operands[0];
3909 ia64_compare_op1 = operands[1];
3910 DONE;
3911}")
3912
3913(define_expand "cmpdi"
3914 [(set (cc0)
0551c32d
RH		 3915 (compare (match_operand:DI 0 "gr_register_operand" "")
3916 (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
c65ebc55
JW		 3917 ""
3918 "
3919{
3920 ia64_compare_op0 = operands[0];
3921 ia64_compare_op1 = operands[1];
3922 DONE;
3923}")
3924
3925(define_expand "cmpsf"
3926 [(set (cc0)
0551c32d
RH		 3927 (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
3928 (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
c65ebc55
JW		 3929 ""
3930 "
3931{
3932 ia64_compare_op0 = operands[0];
3933 ia64_compare_op1 = operands[1];
3934 DONE;
3935}")
3936
3937(define_expand "cmpdf"
3938 [(set (cc0)
0551c32d
RH		 3939 (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
3940 (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
c65ebc55
JW		 3941 ""
3942 "
3943{
3944 ia64_compare_op0 = operands[0];
3945 ia64_compare_op1 = operands[1];
3946 DONE;
3947}")
3948
3f622353 3949(define_expand "cmptf"
c65ebc55 3950 [(set (cc0)
3f622353
RH		 3951 (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
3952 (match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
23c108af 3953 "INTEL_EXTENDED_IEEE_FORMAT"
c65ebc55
JW		 3954 "
3955{
3956 ia64_compare_op0 = operands[0];
3957 ia64_compare_op1 = operands[1];
3958 DONE;
3959}")
3960
3961(define_insn "*cmpsi_normal"
f2f90c63
RH		 3962 [(set (match_operand:BI 0 "register_operand" "=c")
3963 (match_operator:BI 1 "normal_comparison_operator"
0551c32d
RH		 3964 [(match_operand:SI 2 "gr_register_operand" "r")
3965 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
c65ebc55
JW		 3966 ""
3967 "cmp4.%C1 %0, %I0 = %3, %2"
52e12ad0 3968 [(set_attr "itanium_class" "icmp")])
c65ebc55 3969
18a3c539
JW		 3970;; We use %r3 because it is possible for us to match a 0, and two of the
3971;; unsigned comparisons don't accept immediate operands of zero.
3972
c65ebc55 3973(define_insn "*cmpsi_adjusted"
f2f90c63
RH		 3974 [(set (match_operand:BI 0 "register_operand" "=c")
3975 (match_operator:BI 1 "adjusted_comparison_operator"
0551c32d
RH		 3976 [(match_operand:SI 2 "gr_register_operand" "r")
3977 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
c65ebc55 3978 ""
18a3c539 3979 "cmp4.%C1 %0, %I0 = %r3, %2"
52e12ad0 3980 [(set_attr "itanium_class" "icmp")])
c65ebc55
JW		 3981
3982(define_insn "*cmpdi_normal"
f2f90c63
RH		 3983 [(set (match_operand:BI 0 "register_operand" "=c")
3984 (match_operator:BI 1 "normal_comparison_operator"
3985 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
0551c32d 3986 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
c65ebc55 3987 ""
f2f90c63 3988 "cmp.%C1 %0, %I0 = %3, %r2"
52e12ad0 3989 [(set_attr "itanium_class" "icmp")])
c65ebc55 3990
18a3c539
JW		 3991;; We use %r3 because it is possible for us to match a 0, and two of the
3992;; unsigned comparisons don't accept immediate operands of zero.
3993
c65ebc55 3994(define_insn "*cmpdi_adjusted"
f2f90c63
RH		 3995 [(set (match_operand:BI 0 "register_operand" "=c")
3996 (match_operator:BI 1 "adjusted_comparison_operator"
0551c32d
RH		 3997 [(match_operand:DI 2 "gr_register_operand" "r")
3998 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
c65ebc55 3999 ""
18a3c539 4000 "cmp.%C1 %0, %I0 = %r3, %2"
52e12ad0 4001 [(set_attr "itanium_class" "icmp")])
c65ebc55
JW		 4002
4003(define_insn "*cmpsf_internal"
f2f90c63
RH		 4004 [(set (match_operand:BI 0 "register_operand" "=c")
4005 (match_operator:BI 1 "comparison_operator"
0551c32d
RH		 4006 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
4007 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
c65ebc55
JW		 4008 ""
4009 "fcmp.%D1 %0, %I0 = %F2, %F3"
52e12ad0 4010 [(set_attr "itanium_class" "fcmp")])
c65ebc55
JW		 4011
4012(define_insn "*cmpdf_internal"
f2f90c63
RH		 4013 [(set (match_operand:BI 0 "register_operand" "=c")
4014 (match_operator:BI 1 "comparison_operator"
0551c32d
RH		 4015 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
4016 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
c65ebc55
JW		 4017 ""
4018 "fcmp.%D1 %0, %I0 = %F2, %F3"
52e12ad0 4019 [(set_attr "itanium_class" "fcmp")])
c65ebc55 4020
3f622353 4021(define_insn "*cmptf_internal"
f2f90c63
RH		 4022 [(set (match_operand:BI 0 "register_operand" "=c")
4023 (match_operator:BI 1 "comparison_operator"
3f622353
RH		 4024 [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
4025 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
23c108af 4026 "INTEL_EXTENDED_IEEE_FORMAT"
3f622353 4027 "fcmp.%D1 %0, %I0 = %F2, %F3"
52e12ad0 4028 [(set_attr "itanium_class" "fcmp")])
3f622353 4029
c65ebc55
JW		 4030;; ??? Can this pattern be generated?
4031
4032(define_insn "*bit_zero"
f2f90c63
RH		 4033 [(set (match_operand:BI 0 "register_operand" "=c")
4034 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
c65ebc55
JW		 4035 (const_int 1)
4036 (match_operand:DI 2 "immediate_operand" "n"))
4037 (const_int 0)))]
4038 ""
4039 "tbit.z %0, %I0 = %1, %2"
52e12ad0 4040 [(set_attr "itanium_class" "tbit")])
c65ebc55
JW		 4041
4042(define_insn "*bit_one"
f2f90c63
RH		 4043 [(set (match_operand:BI 0 "register_operand" "=c")
4044 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
c65ebc55
JW		 4045 (const_int 1)
4046 (match_operand:DI 2 "immediate_operand" "n"))
4047 (const_int 0)))]
4048 ""
4049 "tbit.nz %0, %I0 = %1, %2"
52e12ad0 4050 [(set_attr "itanium_class" "tbit")])
c65ebc55
JW		 4051\f
4052;; ::::::::::::::::::::
4053;; ::
4054;; :: Branches
4055;; ::
4056;; ::::::::::::::::::::
4057
4058(define_expand "beq"
f2f90c63
RH		 4059 [(set (pc)
4060 (if_then_else (match_dup 1)
c65ebc55
JW		 4061 (label_ref (match_operand 0 "" ""))
4062 (pc)))]
4063 ""
f2f90c63 4064 "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
c65ebc55
JW		 4065
4066(define_expand "bne"
f2f90c63
RH		 4067 [(set (pc)
4068 (if_then_else (match_dup 1)
c65ebc55
JW		 4069 (label_ref (match_operand 0 "" ""))
4070 (pc)))]
4071 ""
f2f90c63 4072 "operands[1] = ia64_expand_compare (NE, VOIDmode);")
c65ebc55
JW		 4073
4074(define_expand "blt"
f2f90c63
RH		 4075 [(set (pc)
4076 (if_then_else (match_dup 1)
c65ebc55
JW		 4077 (label_ref (match_operand 0 "" ""))
4078 (pc)))]
4079 ""
f2f90c63 4080 "operands[1] = ia64_expand_compare (LT, VOIDmode);")
c65ebc55
JW		 4081
4082(define_expand "ble"
f2f90c63
RH		 4083 [(set (pc)
4084 (if_then_else (match_dup 1)
c65ebc55
JW		 4085 (label_ref (match_operand 0 "" ""))
4086 (pc)))]
4087 ""
f2f90c63 4088 "operands[1] = ia64_expand_compare (LE, VOIDmode);")
c65ebc55
JW		 4089
4090(define_expand "bgt"
f2f90c63
RH		 4091 [(set (pc)
4092 (if_then_else (match_dup 1)
c65ebc55
JW		 4093 (label_ref (match_operand 0 "" ""))
4094 (pc)))]
4095 ""
f2f90c63 4096 "operands[1] = ia64_expand_compare (GT, VOIDmode);")
c65ebc55
JW		 4097
4098(define_expand "bge"
f2f90c63
RH		 4099 [(set (pc)
4100 (if_then_else (match_dup 1)
c65ebc55
JW		 4101 (label_ref (match_operand 0 "" ""))
4102 (pc)))]
4103 ""
f2f90c63 4104 "operands[1] = ia64_expand_compare (GE, VOIDmode);")
c65ebc55
JW		 4105
4106(define_expand "bltu"
f2f90c63
RH		 4107 [(set (pc)
4108 (if_then_else (match_dup 1)
c65ebc55
JW		 4109 (label_ref (match_operand 0 "" ""))
4110 (pc)))]
4111 ""
f2f90c63 4112 "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
c65ebc55
JW		 4113
4114(define_expand "bleu"
f2f90c63
RH		 4115 [(set (pc)
4116 (if_then_else (match_dup 1)
c65ebc55
JW		 4117 (label_ref (match_operand 0 "" ""))
4118 (pc)))]
4119 ""
f2f90c63 4120 "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
c65ebc55
JW		 4121
4122(define_expand "bgtu"
f2f90c63
RH		 4123 [(set (pc)
4124 (if_then_else (match_dup 1)
c65ebc55
JW		 4125 (label_ref (match_operand 0 "" ""))
4126 (pc)))]
4127 ""
f2f90c63 4128 "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
c65ebc55
JW		 4129
4130(define_expand "bgeu"
f2f90c63
RH		 4131 [(set (pc)
4132 (if_then_else (match_dup 1)
c65ebc55
JW		 4133 (label_ref (match_operand 0 "" ""))
4134 (pc)))]
4135 ""
f2f90c63 4136 "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
c65ebc55 4137
e57b9d65 4138(define_expand "bunordered"
f2f90c63
RH		 4139 [(set (pc)
4140 (if_then_else (match_dup 1)
e57b9d65
RH		 4141 (label_ref (match_operand 0 "" ""))
4142 (pc)))]
4143 ""
f2f90c63 4144 "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
e57b9d65
RH		 4145
4146(define_expand "bordered"
f2f90c63
RH		 4147 [(set (pc)
4148 (if_then_else (match_dup 1)
e57b9d65
RH		 4149 (label_ref (match_operand 0 "" ""))
4150 (pc)))]
4151 ""
f2f90c63 4152 "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
e57b9d65 4153
6b6c1201 4154(define_insn "*br_true"
c65ebc55 4155 [(set (pc)
6b6c1201 4156 (if_then_else (match_operator 0 "predicate_operator"
f2f90c63 4157 [(match_operand:BI 1 "register_operand" "c")
6b6c1201
RH		 4158 (const_int 0)])
4159 (label_ref (match_operand 2 "" ""))
c65ebc55
JW		 4160 (pc)))]
4161 ""
85548039 4162 "(%J0) br.cond%+ %l2"
52e12ad0 4163 [(set_attr "itanium_class" "br")
e5bde68a 4164 (set_attr "predicable" "no")])
c65ebc55 4165
6b6c1201 4166(define_insn "*br_false"
c65ebc55 4167 [(set (pc)
6b6c1201 4168 (if_then_else (match_operator 0 "predicate_operator"
f2f90c63 4169 [(match_operand:BI 1 "register_operand" "c")
6b6c1201 4170 (const_int 0)])
c65ebc55 4171 (pc)
6b6c1201 4172 (label_ref (match_operand 2 "" ""))))]
c65ebc55 4173 ""
85548039 4174 "(%j0) br.cond%+ %l2"
52e12ad0 4175 [(set_attr "itanium_class" "br")
e5bde68a 4176 (set_attr "predicable" "no")])
c65ebc55
JW		 4177\f
4178;; ::::::::::::::::::::
4179;; ::
5527bf14
RH		 4180;; :: Counted loop operations
4181;; ::
4182;; ::::::::::::::::::::
4183
4184(define_expand "doloop_end"
4185 [(use (match_operand 0 "" "")) ; loop pseudo
4186 (use (match_operand 1 "" "")) ; iterations; zero if unknown
4187 (use (match_operand 2 "" "")) ; max iterations
4188 (use (match_operand 3 "" "")) ; loop level
4189 (use (match_operand 4 "" ""))] ; label
4190 ""
4191 "
4192{
4193 /* Only use cloop on innermost loops. */
4194 if (INTVAL (operands[3]) > 1)
4195 FAIL;
4196 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
4197 operands[4]));
4198 DONE;
4199}")
4200
4201(define_insn "doloop_end_internal"
4202 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
4203 (const_int 0))
4204 (label_ref (match_operand 1 "" ""))
4205 (pc)))
4206 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
4207 (match_dup 0)
4208 (plus:DI (match_dup 0) (const_int -1))))]
4209 ""
4210 "br.cloop.sptk.few %l1"
52e12ad0 4211 [(set_attr "itanium_class" "br")
5527bf14
RH		 4212 (set_attr "predicable" "no")])
4213\f
4214;; ::::::::::::::::::::
4215;; ::
c65ebc55
JW		 4216;; :: Set flag operations
4217;; ::
4218;; ::::::::::::::::::::
4219
4220(define_expand "seq"
f2f90c63 4221 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4222 ""
f2f90c63 4223 "operands[1] = ia64_expand_compare (EQ, DImode);")
c65ebc55
JW		 4224
4225(define_expand "sne"
f2f90c63 4226 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4227 ""
f2f90c63 4228 "operands[1] = ia64_expand_compare (NE, DImode);")
c65ebc55
JW		 4229
4230(define_expand "slt"
f2f90c63 4231 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4232 ""
f2f90c63 4233 "operands[1] = ia64_expand_compare (LT, DImode);")
c65ebc55
JW		 4234
4235(define_expand "sle"
f2f90c63 4236 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4237 ""
f2f90c63 4238 "operands[1] = ia64_expand_compare (LE, DImode);")
c65ebc55
JW		 4239
4240(define_expand "sgt"
f2f90c63 4241 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4242 ""
f2f90c63 4243 "operands[1] = ia64_expand_compare (GT, DImode);")
c65ebc55
JW		 4244
4245(define_expand "sge"
f2f90c63 4246 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4247 ""
f2f90c63 4248 "operands[1] = ia64_expand_compare (GE, DImode);")
c65ebc55
JW		 4249
4250(define_expand "sltu"
f2f90c63 4251 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4252 ""
f2f90c63 4253 "operands[1] = ia64_expand_compare (LTU, DImode);")
c65ebc55
JW		 4254
4255(define_expand "sleu"
f2f90c63 4256 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4257 ""
f2f90c63 4258 "operands[1] = ia64_expand_compare (LEU, DImode);")
c65ebc55
JW		 4259
4260(define_expand "sgtu"
f2f90c63 4261 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4262 ""
f2f90c63 4263 "operands[1] = ia64_expand_compare (GTU, DImode);")
c65ebc55
JW		 4264
4265(define_expand "sgeu"
f2f90c63 4266 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
c65ebc55 4267 ""
f2f90c63 4268 "operands[1] = ia64_expand_compare (GEU, DImode);")
c65ebc55 4269
e57b9d65 4270(define_expand "sunordered"
f2f90c63 4271 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
e57b9d65 4272 ""
f2f90c63 4273 "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
e57b9d65
RH		 4274
4275(define_expand "sordered"
f2f90c63 4276 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
e57b9d65 4277 ""
f2f90c63 4278 "operands[1] = ia64_expand_compare (ORDERED, DImode);")
e57b9d65 4279
c65ebc55
JW		 4280;; Don't allow memory as destination here, because cmov/cmov/st is more
4281;; efficient than mov/mov/cst/cst.
4282
0551c32d
RH		 4283(define_insn_and_split "*sne_internal"
4284 [(set (match_operand:DI 0 "gr_register_operand" "=r")
f2f90c63 4285 (ne:DI (match_operand:BI 1 "register_operand" "c")
c65ebc55
JW		 4286 (const_int 0)))]
4287 ""
4288 "#"
c65ebc55 4289 "reload_completed"
f2f90c63
RH		 4290 [(cond_exec (ne (match_dup 1) (const_int 0))
4291 (set (match_dup 0) (const_int 1)))
4292 (cond_exec (eq (match_dup 1) (const_int 0))
4293 (set (match_dup 0) (const_int 0)))]
0551c32d 4294 ""
52e12ad0 4295 [(set_attr "itanium_class" "unknown")])
c65ebc55 4296
0551c32d
RH		 4297(define_insn_and_split "*seq_internal"
4298 [(set (match_operand:DI 0 "gr_register_operand" "=r")
f2f90c63 4299 (eq:DI (match_operand:BI 1 "register_operand" "c")
c65ebc55
JW		 4300 (const_int 0)))]
4301 ""
4302 "#"
c65ebc55 4303 "reload_completed"
f2f90c63
RH		 4304 [(cond_exec (ne (match_dup 1) (const_int 0))
4305 (set (match_dup 0) (const_int 0)))
4306 (cond_exec (eq (match_dup 1) (const_int 0))
4307 (set (match_dup 0) (const_int 1)))]
0551c32d 4308 ""
52e12ad0 4309 [(set_attr "itanium_class" "unknown")])
c65ebc55
JW		 4310\f
4311;; ::::::::::::::::::::
4312;; ::
4313;; :: Conditional move instructions.
4314;; ::
4315;; ::::::::::::::::::::
4316
4317;; ??? Add movXXcc patterns?
4318
c65ebc55
JW		 4319;;
4320;; DImode if_then_else patterns.
4321;;
4322
75cdbeb8 4323(define_insn "*cmovdi_internal"
f2f90c63 4324 [(set (match_operand:DI 0 "destination_operand"
cd5c4048 4325 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
e5bde68a 4326 (if_then_else:DI
f2f90c63
RH		 4327 (match_operator 4 "predicate_operator"
4328 [(match_operand:BI 1 "register_operand"
cd5c4048 4329 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
e5bde68a 4330 (const_int 0)])
f2f90c63 4331 (match_operand:DI 2 "move_operand"
cd5c4048 4332 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
f2f90c63 4333 (match_operand:DI 3 "move_operand"
cd5c4048 4334 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
aebf2462 4335 "ia64_move_ok (operands[0], operands[2])
f2f90c63 4336 && ia64_move_ok (operands[0], operands[3])"
75cdbeb8
RH		 4337 "* abort ();"
4338 [(set_attr "predicable" "no")])
4339
4340(define_split
f2f90c63 4341 [(set (match_operand 0 "destination_operand" "")
75cdbeb8 4342 (if_then_else
f2f90c63
RH		 4343 (match_operator 4 "predicate_operator"
4344 [(match_operand:BI 1 "register_operand" "")
75cdbeb8 4345 (const_int 0)])
f2f90c63
RH		 4346 (match_operand 2 "move_operand" "")
4347 (match_operand 3 "move_operand" "")))]
3b572406
RH		 4348 "reload_completed"
4349 [(const_int 0)]
e5bde68a
RH		 4350 "
4351{
3b572406
RH		 4352 rtx tmp;
4353 if (! rtx_equal_p (operands[0], operands[2]))
e5bde68a 4354 {
3b572406
RH		 4355 tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]);
4356 tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp);
4357 emit_insn (tmp);
e5bde68a 4358 }
3b572406
RH		 4359 if (! rtx_equal_p (operands[0], operands[3]))
4360 {
4361 tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
f2f90c63 4362 VOIDmode, operands[1], const0_rtx);
3b572406
RH		 4363 tmp = gen_rtx_COND_EXEC (VOIDmode, tmp,
4364 gen_rtx_SET (VOIDmode, operands[0],
4365 operands[3]));
4366 emit_insn (tmp);
4367 }
4368 DONE;
75cdbeb8 4369}")
c65ebc55
JW		 4370
4371;; Absolute value pattern.
4372
4373(define_insn "*absdi2_internal"
0551c32d 4374 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
e5bde68a 4375 (if_then_else:DI
f2f90c63
RH		 4376 (match_operator 4 "predicate_operator"
4377 [(match_operand:BI 1 "register_operand" "c,c")
e5bde68a 4378 (const_int 0)])
0551c32d
RH		 4379 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
4380 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
c65ebc55 4381 ""
e5bde68a 4382 "#"
52e12ad0 4383 [(set_attr "itanium_class" "ialu,unknown")
3b572406 4384 (set_attr "predicable" "no")])
c65ebc55
JW		 4385
4386(define_split
4387 [(set (match_operand:DI 0 "register_operand" "")
e5bde68a 4388 (if_then_else:DI
f2f90c63
RH		 4389 (match_operator 4 "predicate_operator"
4390 [(match_operand:BI 1 "register_operand" "c,c")
e5bde68a 4391 (const_int 0)])
0551c32d
RH		 4392 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4393 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
e5bde68a
RH		 4394 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4395 [(cond_exec
4396 (match_dup 4)
4397 (set (match_dup 0)
4398 (neg:DI (match_dup 2))))]
c65ebc55
JW		 4399 "")
4400
e5bde68a
RH		 4401(define_split
4402 [(set (match_operand:DI 0 "register_operand" "")
4403 (if_then_else:DI
f2f90c63
RH		 4404 (match_operator 4 "predicate_operator"
4405 [(match_operand:BI 1 "register_operand" "c,c")
e5bde68a 4406 (const_int 0)])
0551c32d
RH		 4407 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4408 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
e5bde68a
RH		 4409 "reload_completed"
4410 [(cond_exec
4411 (match_dup 4)
4412 (set (match_dup 0) (neg:DI (match_dup 2))))
4413 (cond_exec
4414 (match_dup 5)
4415 (set (match_dup 0) (match_dup 3)))]
4416 "
4417{
4418 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
f2f90c63 4419 VOIDmode, operands[1], const0_rtx);
e5bde68a 4420}")
c65ebc55
JW		 4421
4422;;
4423;; SImode if_then_else patterns.
4424;;
4425
75cdbeb8 4426(define_insn "*cmovsi_internal"
f2f90c63 4427 [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
e5bde68a 4428 (if_then_else:SI
f2f90c63
RH		 4429 (match_operator 4 "predicate_operator"
4430 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
e5bde68a 4431 (const_int 0)])
f2f90c63 4432 (match_operand:SI 2 "move_operand"
3b572406 4433 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
f2f90c63 4434 (match_operand:SI 3 "move_operand"
3b572406 4435 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
aebf2462 4436 "ia64_move_ok (operands[0], operands[2])
f2f90c63 4437 && ia64_move_ok (operands[0], operands[3])"
75cdbeb8 4438 "* abort ();"
3b572406 4439 [(set_attr "predicable" "no")])
c65ebc55
JW		 4440
4441(define_insn "*abssi2_internal"
0551c32d 4442 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
e5bde68a 4443 (if_then_else:SI
f2f90c63
RH		 4444 (match_operator 4 "predicate_operator"
4445 [(match_operand:BI 1 "register_operand" "c,c")
e5bde68a 4446 (const_int 0)])
0551c32d
RH		 4447 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
4448 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
c65ebc55 4449 ""
e5bde68a 4450 "#"
52e12ad0 4451 [(set_attr "itanium_class" "ialu,unknown")
3b572406 4452 (set_attr "predicable" "no")])
c65ebc55
JW		 4453
4454(define_split
4455 [(set (match_operand:SI 0 "register_operand" "")
e5bde68a 4456 (if_then_else:SI
f2f90c63
RH		 4457 (match_operator 4 "predicate_operator"
4458 [(match_operand:BI 1 "register_operand" "c,c")
e5bde68a 4459 (const_int 0)])
0551c32d
RH		 4460 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4461 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
e5bde68a
RH		 4462 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4463 [(cond_exec
4464 (match_dup 4)
4465 (set (match_dup 0)
4466 (neg:SI (match_dup 2))))]
c65ebc55
JW		 4467 "")
4468
e5bde68a
RH		 4469(define_split
4470 [(set (match_operand:SI 0 "register_operand" "")
4471 (if_then_else:SI
f2f90c63
RH		 4472 (match_operator 4 "predicate_operator"
4473 [(match_operand:BI 1 "register_operand" "c,c")
e5bde68a 4474 (const_int 0)])
0551c32d
RH		 4475 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4476 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
e5bde68a
RH		 4477 "reload_completed"
4478 [(cond_exec
4479 (match_dup 4)
4480 (set (match_dup 0) (neg:SI (match_dup 2))))
4481 (cond_exec
4482 (match_dup 5)
4483 (set (match_dup 0) (match_dup 3)))]
4484 "
4485{
4486 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
f2f90c63 4487 VOIDmode, operands[1], const0_rtx);
e5bde68a
RH		 4488}")
4489
c65ebc55
JW		 4490\f
4491;; ::::::::::::::::::::
4492;; ::
4493;; :: Call and branch instructions
4494;; ::
4495;; ::::::::::::::::::::
4496
4497;; Subroutine call instruction returning no value. Operand 0 is the function
4498;; to call; operand 1 is the number of bytes of arguments pushed (in mode
4499;; `SImode', except it is normally a `const_int'); operand 2 is the number of
4500;; registers used as operands.
4501
4502;; On most machines, operand 2 is not actually stored into the RTL pattern. It
4503;; is supplied for the sake of some RISC machines which need to put this
4504;; information into the assembler code; they can put it in the RTL instead of
4505;; operand 1.
4506
4507(define_expand "call"
4508 [(use (match_operand:DI 0 "" ""))
4509 (use (match_operand 1 "" ""))
4510 (use (match_operand 2 "" ""))
4511 (use (match_operand 3 "" ""))]
4512 ""
4513 "
4514{
2ed4af6f 4515 ia64_expand_call (NULL_RTX, operands[0], operands[2], 0);
c65ebc55
JW		 4516 DONE;
4517}")
4518
2ed4af6f
RH		 4519(define_expand "sibcall"
4520 [(use (match_operand:DI 0 "" ""))
4521 (use (match_operand 1 "" ""))
4522 (use (match_operand 2 "" ""))
4523 (use (match_operand 3 "" ""))]
c65ebc55
JW		 4524 ""
4525 "
4526{
2ed4af6f
RH		 4527 ia64_expand_call (NULL_RTX, operands[0], operands[2], 1);
4528 DONE;
c65ebc55
JW		 4529}")
4530
c65ebc55 4531;; Subroutine call instruction returning a value. Operand 0 is the hard
2ed4af6f
RH		 4532;; register in which the value is returned. There are three more operands,
4533;; the same as the three operands of the `call' instruction (but with numbers
c65ebc55 4534;; increased by one).
2ed4af6f 4535;;
c65ebc55
JW		 4536;; Subroutines that return `BLKmode' objects use the `call' insn.
4537
4538(define_expand "call_value"
4539 [(use (match_operand 0 "" ""))
4540 (use (match_operand:DI 1 "" ""))
4541 (use (match_operand 2 "" ""))
4542 (use (match_operand 3 "" ""))
4543 (use (match_operand 4 "" ""))]
4544 ""
4545 "
4546{
2ed4af6f 4547 ia64_expand_call (operands[0], operands[1], operands[3], 0);
c65ebc55
JW		 4548 DONE;
4549}")
4550
2ed4af6f
RH		 4551(define_expand "sibcall_value"
4552 [(use (match_operand 0 "" ""))
4553 (use (match_operand:DI 1 "" ""))
4554 (use (match_operand 2 "" ""))
4555 (use (match_operand 3 "" ""))
4556 (use (match_operand 4 "" ""))]
c65ebc55
JW		 4557 ""
4558 "
4559{
2ed4af6f
RH		 4560 ia64_expand_call (operands[0], operands[1], operands[3], 1);
4561 DONE;
c65ebc55
JW		 4562}")
4563
c65ebc55
JW		 4564;; Call subroutine returning any type.
4565
4566(define_expand "untyped_call"
4567 [(parallel [(call (match_operand 0 "" "")
4568 (const_int 0))
4569 (match_operand 1 "" "")
4570 (match_operand 2 "" "")])]
4571 ""
4572 "
4573{
4574 int i;
4575
4576 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
4577
4578 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4579 {
4580 rtx set = XVECEXP (operands[2], 0, i);
4581 emit_move_insn (SET_DEST (set), SET_SRC (set));
4582 }
4583
4584 /* The optimizer does not know that the call sets the function value
4585 registers we stored in the result block. We avoid problems by
4586 claiming that all hard registers are used and clobbered at this
4587 point. */
4588 emit_insn (gen_blockage ());
4589
4590 DONE;
4591}")
4592
2ed4af6f 4593(define_insn "call_nopic"
52e12ad0 4594 [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
2ed4af6f 4595 (match_operand 1 "" ""))
52e12ad0 4596 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
2ed4af6f
RH		 4597 ""
4598 "br.call%+.many %2 = %0"
52e12ad0 4599 [(set_attr "itanium_class" "br,scall")])
2ed4af6f
RH		 4600
4601(define_insn "call_value_nopic"
4602 [(set (match_operand 0 "" "")
52e12ad0 4603 (call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
2ed4af6f 4604 (match_operand 2 "" "")))
52e12ad0 4605 (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
2ed4af6f
RH		 4606 ""
4607 "br.call%+.many %3 = %1"
52e12ad0 4608 [(set_attr "itanium_class" "br,scall")])
2ed4af6f
RH		 4609
4610(define_insn "sibcall_nopic"
52e12ad0 4611 [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
2ed4af6f 4612 (match_operand 1 "" ""))
52e12ad0 4613 (use (match_operand:DI 2 "register_operand" "=b,b"))]
2ed4af6f
RH		 4614 ""
4615 "br%+.many %0"
52e12ad0 4616 [(set_attr "itanium_class" "br,scall")])
2ed4af6f
RH		 4617
4618(define_insn "call_pic"
52e12ad0 4619 [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
2ed4af6f
RH		 4620 (match_operand 1 "" ""))
4621 (use (unspec [(reg:DI 1)] 9))
52e12ad0 4622 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
2ed4af6f
RH		 4623 ""
4624 "br.call%+.many %2 = %0"
52e12ad0 4625 [(set_attr "itanium_class" "br,scall")])
2ed4af6f
RH		 4626
4627(define_insn "call_value_pic"
4628 [(set (match_operand 0 "" "")
52e12ad0 4629 (call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
2ed4af6f
RH		 4630 (match_operand 2 "" "")))
4631 (use (unspec [(reg:DI 1)] 9))
52e12ad0 4632 (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
2ed4af6f
RH		 4633 ""
4634 "br.call%+.many %3 = %1"
52e12ad0 4635 [(set_attr "itanium_class" "br,scall")])
2ed4af6f
RH		 4636
4637(define_insn "sibcall_pic"
4638 [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
4639 (match_operand 1 "" ""))
4640 (use (unspec [(reg:DI 1)] 9))
4641 (use (match_operand:DI 2 "register_operand" "=b"))]
4642 ""
4643 "br%+.many %0"
52e12ad0 4644 [(set_attr "itanium_class" "br")])
2ed4af6f 4645
c65ebc55
JW		 4646(define_insn "return_internal"
4647 [(return)
4648 (use (match_operand:DI 0 "register_operand" "b"))]
4649 ""
4650 "br.ret.sptk.many %0"
52e12ad0 4651 [(set_attr "itanium_class" "br")])
c65ebc55
JW		 4652
4653(define_insn "return"
4654 [(return)]
4655 "ia64_direct_return ()"
4656 "br.ret.sptk.many rp"
52e12ad0 4657 [(set_attr "itanium_class" "br")])
c65ebc55 4658
6b6c1201 4659(define_insn "*return_true"
c65ebc55 4660 [(set (pc)
6b6c1201 4661 (if_then_else (match_operator 0 "predicate_operator"
f2f90c63 4662 [(match_operand:BI 1 "register_operand" "c")
6b6c1201 4663 (const_int 0)])
c65ebc55
JW		 4664 (return)
4665 (pc)))]
4666 "ia64_direct_return ()"
13da91fd 4667 "(%J0) br.ret%+.many rp"
52e12ad0 4668 [(set_attr "itanium_class" "br")
e5bde68a 4669 (set_attr "predicable" "no")])
c65ebc55 4670
6b6c1201 4671(define_insn "*return_false"
c65ebc55 4672 [(set (pc)
6b6c1201 4673 (if_then_else (match_operator 0 "predicate_operator"
f2f90c63 4674 [(match_operand:BI 1 "register_operand" "c")
6b6c1201 4675 (const_int 0)])
c65ebc55
JW		 4676 (pc)
4677 (return)))]
4678 "ia64_direct_return ()"
13da91fd 4679 "(%j0) br.ret%+.many rp"
52e12ad0 4680 [(set_attr "itanium_class" "br")
e5bde68a 4681 (set_attr "predicable" "no")])
c65ebc55
JW		 4682
4683(define_insn "jump"
4684 [(set (pc) (label_ref (match_operand 0 "" "")))]
4685 ""
4686 "br %l0"
52e12ad0 4687 [(set_attr "itanium_class" "br")])
c65ebc55
JW		 4688
4689(define_insn "indirect_jump"
4690 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
4691 ""
4692 "br %0"
52e12ad0 4693 [(set_attr "itanium_class" "br")])
c65ebc55
JW		 4694
4695(define_expand "tablejump"
4696 [(match_operand:DI 0 "register_operand" "")
4697 (match_operand 1 "" "")]
4698 ""
4699 "
4700{
4701 rtx tmp1 = gen_reg_rtx (DImode);
4702 rtx tmp2 = gen_reg_rtx (DImode);
4703
4704 emit_move_insn (tmp1, gen_rtx_LABEL_REF (Pmode, operands[1]));
4705 emit_insn (gen_adddi3 (tmp2, operands[0], tmp1));
4706 emit_jump_insn (gen_tablejump_internal (tmp2, operands[1]));
4707 DONE;
4708}")
4709
4710(define_insn "tablejump_internal"
4711 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
4712 (use (label_ref (match_operand 1 "" "")))]
4713 ""
4714 "br %0"
52e12ad0 4715 [(set_attr "itanium_class" "br")])
c65ebc55
JW		 4716
4717\f
4718;; ::::::::::::::::::::
4719;; ::
4720;; :: Prologue and Epilogue instructions
4721;; ::
4722;; ::::::::::::::::::::
4723
4724(define_expand "prologue"
4725 [(const_int 1)]
4726 ""
4727 "
4728{
4729 ia64_expand_prologue ();
4730 DONE;
4731}")
4732
4733(define_expand "epilogue"
2ed4af6f
RH		 4734 [(return)]
4735 ""
4736 "
4737{
4738 ia64_expand_epilogue (0);
4739 DONE;
4740}")
4741
4742(define_expand "sibcall_epilogue"
4743 [(return)]
c65ebc55
JW		 4744 ""
4745 "
4746{
2ed4af6f 4747 ia64_expand_epilogue (1);
c65ebc55
JW		 4748 DONE;
4749}")
4750
4751;; This prevents the scheduler from moving the SP decrement past FP-relative
4752;; stack accesses. This is the same as adddi3 plus the extra set.
4753
4754(define_insn "prologue_allocate_stack"
4755 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
4756 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
0551c32d 4757 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
c65ebc55
JW		 4758 (set (match_operand:DI 3 "register_operand" "=r,r,r")
4759 (match_dup 3))]
4760 ""
4761 "@
4762 add %0 = %1, %2
4763 adds %0 = %2, %1
4764 addl %0 = %2, %1"
52e12ad0 4765 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 4766
4767;; This prevents the scheduler from moving the SP restore past FP-relative
4768;; stack accesses. This is similar to movdi plus the extra set.
4769
4770(define_insn "epilogue_deallocate_stack"
4771 [(set (match_operand:DI 0 "register_operand" "=r")
4772 (match_operand:DI 1 "register_operand" "+r"))
4773 (set (match_dup 1) (match_dup 1))]
4774 ""
4775 "mov %0 = %1"
52e12ad0 4776 [(set_attr "itanium_class" "ialu")])
c65ebc55
JW		 4777
4778;; Allocate a new register frame.
4779
4780(define_insn "alloc"
4781 [(set (match_operand:DI 0 "register_operand" "=r")
4782 (unspec_volatile:DI [(const_int 0)] 0))
4783 (use (match_operand:DI 1 "const_int_operand" "i"))
4784 (use (match_operand:DI 2 "const_int_operand" "i"))
4785 (use (match_operand:DI 3 "const_int_operand" "i"))
4786 (use (match_operand:DI 4 "const_int_operand" "i"))]
4787 ""
4788 "alloc %0 = ar.pfs, %1, %2, %3, %4"
52e12ad0 4789 [(set_attr "itanium_class" "syst_m0")
e5bde68a 4790 (set_attr "predicable" "no")])
c65ebc55 4791
97e242b0
RH		 4792;; Modifies ar.unat
4793(define_expand "gr_spill"
870f9ec0
RH		 4794 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
4795 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
4796 (match_operand:DI 2 "const_int_operand" "")] 1))
4797 (clobber (match_dup 3))])]
97e242b0 4798 ""
870f9ec0 4799 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
97e242b0 4800
870f9ec0 4801(define_insn "gr_spill_internal"
c65ebc55 4802 [(set (match_operand:DI 0 "memory_operand" "=m")
870f9ec0
RH		 4803 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
4804 (match_operand:DI 2 "const_int_operand" "")] 1))
4805 (clobber (match_operand:DI 3 "register_operand" ""))]
c65ebc55 4806 ""
2130b7fb
BS		 4807 "*
4808{
4809 return \".mem.offset %2, 0\;%,st8.spill %0 = %1%P0\";
4810}"
52e12ad0 4811 [(set_attr "itanium_class" "st")])
c65ebc55 4812
97e242b0
RH		 4813;; Reads ar.unat
4814(define_expand "gr_restore"
870f9ec0
RH		 4815 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
4816 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
4817 (match_operand:DI 2 "const_int_operand" "")] 2))
4818 (use (match_dup 3))])]
97e242b0 4819 ""
870f9ec0 4820 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
97e242b0 4821
870f9ec0 4822(define_insn "gr_restore_internal"
c65ebc55 4823 [(set (match_operand:DI 0 "register_operand" "=r")
870f9ec0
RH		 4824 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
4825 (match_operand:DI 2 "const_int_operand" "")] 2))
4826 (use (match_operand:DI 3 "register_operand" ""))]
c65ebc55 4827 ""
2130b7fb
BS		 4828 "*
4829{
4830 return \".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1\";
4831}"
52e12ad0 4832 [(set_attr "itanium_class" "ld")])
c65ebc55
JW		 4833
4834(define_insn "fr_spill"
3f622353
RH		 4835 [(set (match_operand:TF 0 "memory_operand" "=m")
4836 (unspec:TF [(match_operand:TF 1 "register_operand" "f")] 3))]
c65ebc55
JW		 4837 ""
4838 "stf.spill %0 = %1%P0"
52e12ad0 4839 [(set_attr "itanium_class" "stf")])
c65ebc55
JW		 4840
4841(define_insn "fr_restore"
3f622353
RH		 4842 [(set (match_operand:TF 0 "register_operand" "=f")
4843 (unspec:TF [(match_operand:TF 1 "memory_operand" "m")] 4))]
c65ebc55
JW		 4844 ""
4845 "ldf.fill %0 = %1%P1"
52e12ad0 4846 [(set_attr "itanium_class" "fld")])
c65ebc55 4847
0024a804
JW		 4848;; ??? The explicit stop is not ideal. It would be better if
4849;; rtx_needs_barrier took care of this, but this is something that can be
4850;; fixed later. This avoids an RSE DV.
4851
0c96007e
AM		 4852(define_insn "bsp_value"
4853 [(set (match_operand:DI 0 "register_operand" "=r")
4854 (unspec:DI [(const_int 0)] 20))]
4855 ""
0024a804 4856 ";;\;mov %0 = ar.bsp"
52e12ad0 4857 [(set_attr "itanium_class" "frar_i")])
0c96007e
AM		 4858
4859(define_insn "set_bsp"
2ed4af6f 4860 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 5)]
0c96007e 4861 ""
13da91fd 4862 "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
52e12ad0 4863 [(set_attr "itanium_class" "unknown")
e5bde68a 4864 (set_attr "predicable" "no")])
ce152ef8 4865
0024a804
JW		 4866;; ??? The explicit stops are not ideal. It would be better if
4867;; rtx_needs_barrier took care of this, but this is something that can be
4868;; fixed later. This avoids an RSE DV.
4869
ce152ef8
AM		 4870(define_insn "flushrs"
4871 [(unspec [(const_int 0)] 21)]
4872 ""
0024a804 4873 ";;\;flushrs\;;;"
52e12ad0 4874 [(set_attr "itanium_class" "rse_m")])
c65ebc55
JW		 4875\f
4876;; ::::::::::::::::::::
4877;; ::
4878;; :: Miscellaneous instructions
4879;; ::
4880;; ::::::::::::::::::::
4881
4882;; ??? Emiting a NOP instruction isn't very useful. This should probably
4883;; be emitting ";;" to force a break in the instruction packing.
4884
4885;; No operation, needed in case the user uses -g but not -O.
4886(define_insn "nop"
4887 [(const_int 0)]
4888 ""
4889 "nop 0"
52e12ad0 4890 [(set_attr "itanium_class" "unknown")])
c65ebc55 4891
2130b7fb
BS		 4892(define_insn "nop_m"
4893 [(const_int 1)]
4894 ""
4895 "nop.m 0"
4896 [(set_attr "itanium_class" "nop_m")])
4897
4898(define_insn "nop_i"
4899 [(const_int 2)]
4900 ""
4901 "nop.i 0"
4902 [(set_attr "itanium_class" "nop_i")])
4903
4904(define_insn "nop_f"
4905 [(const_int 3)]
4906 ""
4907 "nop.f 0"
4908 [(set_attr "itanium_class" "nop_f")])
4909
4910(define_insn "nop_b"
4911 [(const_int 4)]
4912 ""
4913 "nop.b 0"
4914 [(set_attr "itanium_class" "nop_b")])
4915
4916(define_insn "nop_x"
4917 [(const_int 5)]
4918 ""
4919 ""
4920 [(set_attr "itanium_class" "nop_x")])
4921
4922(define_expand "cycle_display"
4923 [(unspec [(match_operand 0 "const_int_operand" "")] 23)]
4924 "ia64_final_schedule"
4925 "")
4926
4927(define_insn "*cycle_display_1"
4928 [(unspec [(match_operand 0 "const_int_operand" "")] 23)]
4929 ""
4930 "// cycle %0"
4931 [(set_attr "itanium_class" "ignore")
4932 (set_attr "predicable" "no")])
4933
4934(define_insn "bundle_selector"
4935 [(unspec [(match_operand 0 "const_int_operand" "")] 22)]
4936 ""
4937 "*
4938{
4939 return get_bundle_name (INTVAL (operands[0]));
4940}"
4941 [(set_attr "itanium_class" "ignore")
4942 (set_attr "predicable" "no")])
4943
c65ebc55
JW		 4944;; Pseudo instruction that prevents the scheduler from moving code above this
4945;; point.
4946(define_insn "blockage"
4947 [(unspec_volatile [(const_int 0)] 1)]
4948 ""
4949 ""
52e12ad0 4950 [(set_attr "itanium_class" "ignore")
e5bde68a 4951 (set_attr "predicable" "no")])
c65ebc55
JW		 4952
4953(define_insn "insn_group_barrier"
2130b7fb 4954 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 2)]
c65ebc55
JW		 4955 ""
4956 ";;"
52e12ad0 4957 [(set_attr "itanium_class" "stop_bit")
e5bde68a 4958 (set_attr "predicable" "no")])
c65ebc55 4959
f12f25a7
RH		 4960(define_insn "break_f"
4961 [(unspec_volatile [(const_int 0)] 3)]
4962 ""
4963 "break.f 0"
4964 [(set_attr "itanium_class" "nop_f")])
c65ebc55
JW		 4965\f
4966;; Non-local goto support.
4967
4968(define_expand "save_stack_nonlocal"
4969 [(use (match_operand:OI 0 "memory_operand" ""))
4970 (use (match_operand:DI 1 "register_operand" ""))]
4971 ""
4972 "
4973{
4974 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
4975 \"__ia64_save_stack_nonlocal\"),
4976 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
4977 operands[1], Pmode);
4978 DONE;
4979}")
4980
4981(define_expand "nonlocal_goto"
4982 [(use (match_operand 0 "general_operand" ""))
4983 (use (match_operand 1 "general_operand" ""))
4984 (use (match_operand 2 "general_operand" ""))
4985 (use (match_operand 3 "general_operand" ""))]
4986 ""
4987 "
4988{
c65ebc55 4989 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
8206fc89
AM		 4990 LCT_NORETURN, VOIDmode, 3,
4991 operands[3], Pmode,
c65ebc55 4992 copy_to_reg (XEXP (operands[2], 0)), Pmode,
8206fc89 4993 operands[1], Pmode);
c65ebc55
JW		 4994 emit_barrier ();
4995 DONE;
4996}")
4997
97e242b0
RH		 4998;; The rest of the setjmp processing happens with the nonlocal_goto expander.
4999;; ??? This is not tested.
5000(define_expand "builtin_setjmp_setup"
5001 [(use (match_operand:DI 0 "" ""))]
c65ebc55
JW		 5002 ""
5003 "
5004{
97e242b0
RH		 5005 emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1)));
5006 DONE;
5007}")
5008
5009(define_expand "builtin_setjmp_receiver"
5010 [(use (match_operand:DI 0 "" ""))]
5011 ""
5012 "
5013{
5014 emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0));
c65ebc55
JW		 5015 DONE;
5016}")
5017
0c96007e
AM		 5018(define_expand "eh_epilogue"
5019 [(use (match_operand:DI 0 "register_operand" "r"))
5020 (use (match_operand:DI 1 "register_operand" "r"))
5021 (use (match_operand:DI 2 "register_operand" "r"))]
5022 ""
5023 "
5024{
5025 rtx bsp = gen_rtx_REG (Pmode, 10);
5026 rtx sp = gen_rtx_REG (Pmode, 9);
5027
5028 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
5029 {
5030 emit_move_insn (bsp, operands[0]);
5031 operands[0] = bsp;
5032 }
5033 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
5034 {
5035 emit_move_insn (sp, operands[2]);
5036 operands[2] = sp;
5037 }
5038 emit_insn (gen_rtx_USE (VOIDmode, sp));
5039 emit_insn (gen_rtx_USE (VOIDmode, bsp));
5040
5041 cfun->machine->ia64_eh_epilogue_sp = sp;
5042 cfun->machine->ia64_eh_epilogue_bsp = bsp;
0c96007e 5043}")
9525c690
JW		 5044\f
5045;; Builtin apply support.
5046
5047(define_expand "restore_stack_nonlocal"
5048 [(use (match_operand:DI 0 "register_operand" ""))
5049 (use (match_operand:OI 1 "memory_operand" ""))]
5050 ""
5051 "
5052{
5053 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5054 \"__ia64_restore_stack_nonlocal\"),
5055 0, VOIDmode, 1,
5056 copy_to_reg (XEXP (operands[1], 0)), Pmode);
5057 DONE;
5058}")
5059
5060\f
5061;;; Intrinsics support.
c65ebc55 5062
0551c32d
RH		 5063(define_expand "mf"
5064 [(set (mem:BLK (match_dup 0))
5065 (unspec:BLK [(mem:BLK (match_dup 0))] 12))]
5066 ""
5067 "
5068{
5069 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
5070 MEM_VOLATILE_P (operands[0]) = 1;
5071}")
5072
5073(define_insn "*mf_internal"
5074 [(set (match_operand:BLK 0 "" "")
5075 (unspec:BLK [(match_operand:BLK 1 "" "")] 12))]
c65ebc55
JW		 5076 ""
5077 "mf"
52e12ad0 5078 [(set_attr "itanium_class" "syst_m")])
c65ebc55
JW		 5079
5080(define_insn "fetchadd_acq_si"
0551c32d
RH		 5081 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5082 (match_dup 1))
5083 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5084 (unspec:SI [(match_dup 1)
5085 (match_operand:SI 2 "fetchadd_operand" "n")] 19))]
c65ebc55
JW		 5086 ""
5087 "fetchadd4.acq %0 = %1, %2"
52e12ad0 5088 [(set_attr "itanium_class" "sem")])
c65ebc55
JW		 5089
5090(define_insn "fetchadd_acq_di"
0551c32d
RH		 5091 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5092 (match_dup 1))
5093 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5094 (unspec:DI [(match_dup 1)
5095 (match_operand:DI 2 "fetchadd_operand" "n")] 19))]
c65ebc55
JW		 5096 ""
5097 "fetchadd8.acq %0 = %1, %2"
52e12ad0 5098 [(set_attr "itanium_class" "sem")])
c65ebc55
JW		 5099
5100(define_insn "cmpxchg_acq_si"
0551c32d
RH		 5101 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5102 (match_dup 1))
5103 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5104 (unspec:SI [(match_dup 1)
5105 (match_operand:SI 2 "gr_register_operand" "r")
97e242b0 5106 (match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))]
c65ebc55 5107 ""
97e242b0 5108 "cmpxchg4.acq %0 = %1, %2, %3"
52e12ad0 5109 [(set_attr "itanium_class" "sem")])
c65ebc55
JW		 5110
5111(define_insn "cmpxchg_acq_di"
0551c32d
RH		 5112 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5113 (match_dup 1))
5114 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5115 (unspec:DI [(match_dup 1)
5116 (match_operand:DI 2 "gr_register_operand" "r")
5117 (match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))]
c65ebc55 5118 ""
97e242b0 5119 "cmpxchg8.acq %0 = %1, %2, %3"
52e12ad0 5120 [(set_attr "itanium_class" "sem")])
c65ebc55 5121
c65ebc55 5122(define_insn "xchgsi"
0551c32d
RH		 5123 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5124 (match_operand:SI 1 "not_postinc_memory_operand" "+S"))
c65ebc55 5125 (set (match_dup 1)
0551c32d 5126 (match_operand:SI 2 "gr_register_operand" "r"))]
c65ebc55
JW		 5127 ""
5128 "xchg4 %0 = %1, %2"
52e12ad0 5129 [(set_attr "itanium_class" "sem")])
c65ebc55
JW		 5130
5131(define_insn "xchgdi"
0551c32d
RH		 5132 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5133 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
c65ebc55 5134 (set (match_dup 1)
0551c32d 5135 (match_operand:DI 2 "gr_register_operand" "r"))]
c65ebc55
JW		 5136 ""
5137 "xchg8 %0 = %1, %2"
52e12ad0 5138 [(set_attr "itanium_class" "sem")])
e5bde68a
RH		 5139\f
5140;; Predication.
5141
5142(define_cond_exec
5143 [(match_operator 0 "predicate_operator"
f2f90c63 5144 [(match_operand:BI 1 "register_operand" "c")
e5bde68a
RH		 5145 (const_int 0)])]
5146 ""
5147 "(%J0)")
3b572406
RH		 5148
5149(define_insn "pred_rel_mutex"
f2f90c63
RH		 5150 [(set (match_operand:BI 0 "register_operand" "+c")
5151 (unspec:BI [(match_dup 0)] 7))]
3b572406 5152 ""
054451ea 5153 ".pred.rel.mutex %0, %I0"
52e12ad0 5154 [(set_attr "itanium_class" "ignore")
3b572406 5155 (set_attr "predicable" "no")])
ca3920ad
JW		 5156
5157(define_insn "safe_across_calls_all"
5158 [(unspec_volatile [(const_int 0)] 8)]
5159 ""
5160 ".pred.safe_across_calls p1-p63"
52e12ad0 5161 [(set_attr "itanium_class" "ignore")
ca3920ad
JW		 5162 (set_attr "predicable" "no")])
5163
5164(define_insn "safe_across_calls_normal"
5165 [(unspec_volatile [(const_int 0)] 9)]
5166 ""
5167 "*
5168{
5169 emit_safe_across_calls (asm_out_file);
5170 return \"\";
5171}"
52e12ad0 5172 [(set_attr "itanium_class" "ignore")
ca3920ad
JW		 5173 (set_attr "predicable" "no")])
5174
GNU Compiler Collection
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