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c65ebc55 | 1 | ;; IA-64 Machine description template |
ff848f0e | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
c65ebc55 JW |
4 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
5 | ;; David Mosberger <davidm@hpl.hp.com>. | |
6 | ||
3bed2930 | 7 | ;; This file is part of GCC. |
c65ebc55 | 8 | |
3bed2930 | 9 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 JW |
10 | ;; it under the terms of the GNU General Public License as published by |
11 | ;; the Free Software Foundation; either version 2, or (at your option) | |
12 | ;; any later version. | |
13 | ||
3bed2930 | 14 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
18 | ||
19 | ;; You should have received a copy of the GNU General Public License | |
3bed2930 | 20 | ;; along with GCC; see the file COPYING. If not, write to |
39d14dda KC |
21 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
22 | ;; Boston, MA 02110-1301, USA. | |
c65ebc55 JW |
23 | |
24 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
25 | ||
c65ebc55 JW |
26 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
27 | ;; reload. This will be fixed once scheduling support is turned on. | |
28 | ||
29 | ;; ??? Optimize for post-increment addressing modes. | |
30 | ||
31 | ;; ??? fselect is not supported, because there is no integer register | |
32 | ;; equivalent. | |
33 | ||
34 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
35 | ||
36 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
37 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
38 | ||
39 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
40 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
41 | ||
42 | ;; ??? Go through list of documented named patterns and look for more to | |
43 | ;; implement. | |
44 | ||
45 | ;; ??? Go through instruction manual and look for more instructions that | |
46 | ;; can be emitted. | |
47 | ||
48 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
49 | ||
26102535 RH |
50 | ;; ??? Need a better way to describe alternate fp status registers. |
51 | ||
086c0f96 | 52 | (define_constants |
7b6e506e RH |
53 | [; Relocations |
54 | (UNSPEC_LTOFF_DTPMOD 0) | |
55 | (UNSPEC_LTOFF_DTPREL 1) | |
56 | (UNSPEC_DTPREL 2) | |
57 | (UNSPEC_LTOFF_TPREL 3) | |
58 | (UNSPEC_TPREL 4) | |
5e6c8b64 | 59 | (UNSPEC_DTPMOD 5) |
7b6e506e RH |
60 | |
61 | (UNSPEC_LD_BASE 9) | |
62 | (UNSPEC_GR_SPILL 10) | |
63 | (UNSPEC_GR_RESTORE 11) | |
64 | (UNSPEC_FR_SPILL 12) | |
65 | (UNSPEC_FR_RESTORE 13) | |
66 | (UNSPEC_FR_RECIP_APPROX 14) | |
67 | (UNSPEC_PRED_REL_MUTEX 15) | |
c407570a | 68 | (UNSPEC_GETF_EXP 16) |
7b6e506e RH |
69 | (UNSPEC_PIC_CALL 17) |
70 | (UNSPEC_MF 18) | |
71 | (UNSPEC_CMPXCHG_ACQ 19) | |
72 | (UNSPEC_FETCHADD_ACQ 20) | |
73 | (UNSPEC_BSP_VALUE 21) | |
74 | (UNSPEC_FLUSHRS 22) | |
75 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
76 | (UNSPEC_ADDP4 24) |
77 | (UNSPEC_PROLOGUE_USE 25) | |
af1e5518 | 78 | (UNSPEC_RET_ADDR 26) |
b38ba463 ZW |
79 | (UNSPEC_SETF_EXP 27) |
80 | (UNSPEC_FR_SQRT_RECIP_APPROX 28) | |
f526a3c8 | 81 | (UNSPEC_SHRP 29) |
046625fa | 82 | (UNSPEC_COPYSIGN 30) |
b4e3537b | 83 | (UNSPEC_VECT_EXTR 31) |
048d0d36 MK |
84 | (UNSPEC_LDA 40) |
85 | (UNSPEC_LDS 41) | |
86 | (UNSPEC_LDSA 42) | |
87 | (UNSPEC_LDCCLR 43) | |
88 | (UNSPEC_CHKACLR 45) | |
89 | (UNSPEC_CHKS 47) | |
086c0f96 RH |
90 | ]) |
91 | ||
92 | (define_constants | |
93 | [(UNSPECV_ALLOC 0) | |
94 | (UNSPECV_BLOCKAGE 1) | |
95 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
96 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
97 | (UNSPECV_SET_BSP 4) |
98 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
99 | (UNSPECV_PSAC_NORMAL 6) | |
b39eb2f9 | 100 | (UNSPECV_SETJMP_RECEIVER 7) |
086c0f96 | 101 | ]) |
e543e219 | 102 | |
7905f799 | 103 | (include "predicates.md") |
13f70342 | 104 | (include "constraints.md") |
c65ebc55 JW |
105 | \f |
106 | ;; :::::::::::::::::::: | |
107 | ;; :: | |
108 | ;; :: Attributes | |
109 | ;; :: | |
110 | ;; :::::::::::::::::::: | |
111 | ||
30028c85 VM |
112 | ;; Processor type. This attribute must exactly match the processor_type |
113 | ;; enumeration in ia64.h. | |
114 | (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune"))) | |
115 | ||
c65ebc55 JW |
116 | ;; Instruction type. This primarily determines how instructions can be |
117 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
118 | ||
119 | ;; A alu, can go in I or M syllable of a bundle | |
120 | ;; I integer | |
121 | ;; M memory | |
122 | ;; F floating-point | |
123 | ;; B branch | |
124 | ;; L long immediate, takes two syllables | |
125 | ;; S stop bit | |
126 | ||
127 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
128 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
129 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
130 | ;; which emit instruction that can go in any slot (e.g. nop). | |
131 | ||
1d5d7a21 | 132 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
a71aef0b | 133 | fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, |
048d0d36 | 134 | ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, |
f61134e8 RH |
135 | st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, |
136 | nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 137 | (const_string "unknown")) |
52e12ad0 | 138 | |
048d0d36 | 139 | ;; chk_s_i has an I and an M form; use type A for convenience. |
2130b7fb | 140 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" |
a71aef0b | 141 | (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") |
52e12ad0 BS |
142 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
143 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 144 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
048d0d36 MK |
145 | (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M") |
146 | (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua") | |
f61134e8 | 147 | (const_string "A") |
2130b7fb BS |
148 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") |
149 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
150 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
151 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
152 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
153 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 154 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 155 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
156 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
157 | (const_string "unknown"))) | |
c65ebc55 | 158 | |
2130b7fb BS |
159 | (define_attr "itanium_requires_unit0" "no,yes" |
160 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
161 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
162 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
163 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
164 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
165 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
166 | (const_string "no"))) | |
167 | ||
e5bde68a RH |
168 | ;; Predication. True iff this instruction can be predicated. |
169 | ||
170 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
171 | ||
fa978426 AS |
172 | ;; Empty. True iff this insn does not generate any code. |
173 | ||
174 | (define_attr "empty" "no,yes" (const_string "no")) | |
175 | ||
68e11b42 JW |
176 | ;; True iff this insn must be the first insn of an instruction group. |
177 | ;; This is true for the alloc instruction, and will also be true of others | |
178 | ;; when we have full intrinsics support. | |
179 | ||
180 | (define_attr "first_insn" "no,yes" (const_string "no")) | |
048d0d36 MK |
181 | |
182 | (define_attr "data_speculative" "no,yes" (const_string "no")) | |
183 | ||
184 | (define_attr "control_speculative" "no,yes" (const_string "no")) | |
185 | ||
186 | (define_attr "check_load" "no,yes" (const_string "no")) | |
c65ebc55 | 187 | \f |
30028c85 VM |
188 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
189 | ;; bundling. | |
190 | ||
191 | (automata_option "ndfa") | |
192 | ||
193 | ;; Uncomment the following line to output automata for debugging. | |
194 | ;; (automata_option "v") | |
195 | ||
196 | (automata_option "w") | |
197 | ||
30028c85 VM |
198 | (include "itanium1.md") |
199 | (include "itanium2.md") | |
200 | ||
c65ebc55 JW |
201 | \f |
202 | ;; :::::::::::::::::::: | |
203 | ;; :: | |
204 | ;; :: Moves | |
205 | ;; :: | |
206 | ;; :::::::::::::::::::: | |
207 | ||
f2f90c63 RH |
208 | ;; Set of a single predicate register. This is only used to implement |
209 | ;; pr-to-pr move and complement. | |
210 | ||
211 | (define_insn "*movcci" | |
212 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
213 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
214 | "" | |
215 | "@ | |
216 | cmp.ne %0, p0 = r0, r0 | |
217 | cmp.eq %0, p0 = r0, r0 | |
218 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 219 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
220 | (set_attr "predicable" "no")]) |
221 | ||
222 | (define_insn "movbi" | |
b6fb7d46 JW |
223 | [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
224 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
225 | "" |
226 | "@ | |
227 | cmp.ne %0, %I0 = r0, r0 | |
228 | cmp.eq %0, %I0 = r0, r0 | |
229 | # | |
230 | # | |
231 | tbit.nz %0, %I0 = %1, 0 | |
232 | adds %0 = %1, r0 | |
233 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
234 | st1%Q0 %0 = %1%P0 |
235 | mov %0 = %1" | |
52e12ad0 | 236 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
237 | |
238 | (define_split | |
239 | [(set (match_operand:BI 0 "register_operand" "") | |
240 | (match_operand:BI 1 "register_operand" ""))] | |
241 | "reload_completed | |
242 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
243 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
244 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
245 | (set (match_dup 0) (const_int 1))) | |
246 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
247 | (set (match_dup 0) (const_int 0)))] | |
248 | "") | |
249 | ||
250 | (define_split | |
251 | [(set (match_operand:BI 0 "register_operand" "") | |
252 | (match_operand:BI 1 "register_operand" ""))] | |
253 | "reload_completed | |
254 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
255 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
256 | [(set (match_dup 2) (match_dup 4)) | |
257 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 258 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
259 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
260 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
261 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
262 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
263 | ||
c65ebc55 JW |
264 | (define_expand "movqi" |
265 | [(set (match_operand:QI 0 "general_operand" "") | |
266 | (match_operand:QI 1 "general_operand" ""))] | |
267 | "" | |
c65ebc55 | 268 | { |
7b6e506e RH |
269 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
270 | if (!op1) | |
271 | DONE; | |
272 | operands[1] = op1; | |
1d5d7a21 | 273 | }) |
c65ebc55 JW |
274 | |
275 | (define_insn "*movqi_internal" | |
4b983fdc RH |
276 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
277 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 278 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 279 | "@ |
13da91fd | 280 | mov %0 = %r1 |
c65ebc55 JW |
281 | addl %0 = %1, r0 |
282 | ld1%O1 %0 = %1%P1 | |
13da91fd | 283 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 284 | getf.sig %0 = %1 |
13da91fd RH |
285 | setf.sig %0 = %r1 |
286 | mov %0 = %1" | |
52e12ad0 | 287 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
288 | |
289 | (define_expand "movhi" | |
290 | [(set (match_operand:HI 0 "general_operand" "") | |
291 | (match_operand:HI 1 "general_operand" ""))] | |
292 | "" | |
c65ebc55 | 293 | { |
7b6e506e RH |
294 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
295 | if (!op1) | |
296 | DONE; | |
297 | operands[1] = op1; | |
1d5d7a21 | 298 | }) |
c65ebc55 JW |
299 | |
300 | (define_insn "*movhi_internal" | |
4b983fdc RH |
301 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
302 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 303 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 304 | "@ |
13da91fd | 305 | mov %0 = %r1 |
c65ebc55 JW |
306 | addl %0 = %1, r0 |
307 | ld2%O1 %0 = %1%P1 | |
13da91fd | 308 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 309 | getf.sig %0 = %1 |
13da91fd RH |
310 | setf.sig %0 = %r1 |
311 | mov %0 = %1" | |
52e12ad0 | 312 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
313 | |
314 | (define_expand "movsi" | |
315 | [(set (match_operand:SI 0 "general_operand" "") | |
316 | (match_operand:SI 1 "general_operand" ""))] | |
317 | "" | |
c65ebc55 | 318 | { |
7b6e506e RH |
319 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
320 | if (!op1) | |
321 | DONE; | |
322 | operands[1] = op1; | |
1d5d7a21 | 323 | }) |
c65ebc55 JW |
324 | |
325 | (define_insn "*movsi_internal" | |
97e242b0 | 326 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 327 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 328 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 329 | "@ |
13da91fd | 330 | mov %0 = %r1 |
c65ebc55 JW |
331 | addl %0 = %1, r0 |
332 | movl %0 = %1 | |
333 | ld4%O1 %0 = %1%P1 | |
13da91fd | 334 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 335 | getf.sig %0 = %1 |
13da91fd | 336 | setf.sig %0 = %r1 |
97e242b0 RH |
337 | mov %0 = %1 |
338 | mov %0 = %1 | |
339 | mov %0 = %r1" | |
1d5d7a21 | 340 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
52e12ad0 | 341 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) |
c65ebc55 JW |
342 | |
343 | (define_expand "movdi" | |
344 | [(set (match_operand:DI 0 "general_operand" "") | |
345 | (match_operand:DI 1 "general_operand" ""))] | |
346 | "" | |
c65ebc55 | 347 | { |
7b6e506e RH |
348 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
349 | if (!op1) | |
350 | DONE; | |
351 | operands[1] = op1; | |
1d5d7a21 | 352 | }) |
c65ebc55 | 353 | |
c65ebc55 | 354 | (define_insn "*movdi_internal" |
4b983fdc | 355 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 356 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 357 | (match_operand:DI 1 "move_operand" |
a32767e4 | 358 | "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 359 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
360 | { |
361 | static const char * const alt[] = { | |
1d5d7a21 RH |
362 | "%,mov %0 = %r1", |
363 | "%,addl %0 = %1, r0", | |
364 | "%,movl %0 = %1", | |
365 | "%,ld8%O1 %0 = %1%P1", | |
366 | "%,st8%Q0 %0 = %r1%P0", | |
367 | "%,getf.sig %0 = %1", | |
368 | "%,setf.sig %0 = %r1", | |
369 | "%,mov %0 = %1", | |
370 | "%,ldf8 %0 = %1%P1", | |
371 | "%,stf8 %0 = %1%P0", | |
372 | "%,mov %0 = %1", | |
373 | "%,mov %0 = %r1", | |
374 | "%,mov %0 = %1", | |
375 | "%,mov %0 = %1", | |
376 | "%,mov %0 = %1", | |
377 | "%,mov %0 = %1", | |
378 | "mov %0 = pr", | |
379 | "mov pr = %1, -1" | |
9b7bf67d RH |
380 | }; |
381 | ||
e820471b NS |
382 | gcc_assert (which_alternative != 2 || TARGET_NO_PIC |
383 | || !symbolic_operand (operands[1], VOIDmode)); | |
9b7bf67d RH |
384 | |
385 | return alt[which_alternative]; | |
1d5d7a21 | 386 | } |
52e12ad0 | 387 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 388 | |
048d0d36 MK |
389 | (define_mode_macro MODE [BI QI HI SI DI SF DF XF TI]) |
390 | (define_mode_macro MODE_FOR_EXTEND [QI HI SI]) | |
391 | ||
392 | (define_mode_attr output_a [ | |
393 | (BI "ld1.a %0 = %1%P1") | |
394 | (QI "ld1.a %0 = %1%P1") | |
395 | (HI "ld2.a %0 = %1%P1") | |
396 | (SI "ld4.a %0 = %1%P1") | |
397 | (DI | |
398 | "@ | |
399 | ld8.a %0 = %1%P1 | |
400 | ldf8.a %0 = %1%P1") | |
401 | (SF | |
402 | "@ | |
403 | ldfs.a %0 = %1%P1 | |
404 | ld4.a %0 = %1%P1") | |
405 | (DF | |
406 | "@ | |
407 | ldfd.a %0 = %1%P1 | |
408 | ld8.a %0 = %1%P1") | |
409 | (XF "ldfe.a %0 = %1%P1") | |
410 | (TI "ldfp8.a %X0 = %1%P1")]) | |
411 | ||
412 | (define_mode_attr output_s [ | |
413 | (BI "ld1.s %0 = %1%P1") | |
414 | (QI "ld1.s %0 = %1%P1") | |
415 | (HI "ld2.s %0 = %1%P1") | |
416 | (SI "ld4.s %0 = %1%P1") | |
417 | (DI | |
418 | "@ | |
419 | ld8.s %0 = %1%P1 | |
420 | ldf8.s %0 = %1%P1") | |
421 | (SF | |
422 | "@ | |
423 | ldfs.s %0 = %1%P1 | |
424 | ld4.s %0 = %1%P1") | |
425 | (DF | |
426 | "@ | |
427 | ldfd.s %0 = %1%P1 | |
428 | ld8.s %0 = %1%P1") | |
429 | (XF "ldfe.s %0 = %1%P1") | |
430 | (TI "ldfp8.s %X0 = %1%P1")]) | |
431 | ||
432 | (define_mode_attr output_sa [ | |
433 | (BI "ld1.sa %0 = %1%P1") | |
434 | (QI "ld1.sa %0 = %1%P1") | |
435 | (HI "ld2.sa %0 = %1%P1") | |
436 | (SI "ld4.sa %0 = %1%P1") | |
437 | (DI | |
438 | "@ | |
439 | ld8.sa %0 = %1%P1 | |
440 | ldf8.sa %0 = %1%P1") | |
441 | (SF | |
442 | "@ | |
443 | ldfs.sa %0 = %1%P1 | |
444 | ld4.sa %0 = %1%P1") | |
445 | (DF | |
446 | "@ | |
447 | ldfd.sa %0 = %1%P1 | |
448 | ld8.sa %0 = %1%P1") | |
449 | (XF "ldfe.sa %0 = %1%P1") | |
450 | (TI "ldfp8.sa %X0 = %1%P1")]) | |
451 | ||
452 | (define_mode_attr output_c_clr [ | |
453 | (BI "ld1.c.clr%O1 %0 = %1%P1") | |
454 | (QI "ld1.c.clr%O1 %0 = %1%P1") | |
455 | (HI "ld2.c.clr%O1 %0 = %1%P1") | |
456 | (SI "ld4.c.clr%O1 %0 = %1%P1") | |
457 | (DI | |
458 | "@ | |
459 | ld8.c.clr%O1 %0 = %1%P1 | |
460 | ldf8.c.clr %0 = %1%P1") | |
461 | (SF | |
462 | "@ | |
463 | ldfs.c.clr %0 = %1%P1 | |
464 | ld4.c.clr%O1 %0 = %1%P1") | |
465 | (DF | |
466 | "@ | |
467 | ldfd.c.clr %0 = %1%P1 | |
468 | ld8.c.clr%O1 %0 = %1%P1") | |
469 | (XF "ldfe.c.clr %0 = %1%P1") | |
470 | (TI "ldfp8.c.clr %X0 = %1%P1")]) | |
471 | ||
472 | (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")]) | |
473 | (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")]) | |
474 | (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")]) | |
475 | ||
476 | (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) | |
477 | ||
f6ec1d11 MK |
478 | ;; Define register predicate prefix. |
479 | ;; We can generate speculative loads only for general and fp registers - this | |
ea2c620c | 480 | ;; is constrained in ia64.c: ia64_speculate_insn (). |
048d0d36 MK |
481 | (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) |
482 | ||
483 | (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) | |
484 | (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")]) | |
485 | (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")]) | |
486 | ||
487 | (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")]) | |
488 | ||
489 | (define_insn "mov<mode>_advanced" | |
490 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
491 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))] | |
492 | "ia64_move_ok (operands[0], operands[1])" | |
493 | "<output_a>" | |
494 | [(set_attr "itanium_class" "<ld_class>") | |
495 | (set_attr "data_speculative" "<attr_yes>")]) | |
496 | ||
497 | (define_insn "zero_extend<mode>di2_advanced" | |
498 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
499 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))] | |
500 | "" | |
501 | "<output_a>" | |
502 | [(set_attr "itanium_class" "<ld_class>") | |
503 | (set_attr "data_speculative" "<attr_yes>")]) | |
504 | ||
505 | (define_insn "mov<mode>_speculative" | |
506 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
507 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))] | |
508 | "ia64_move_ok (operands[0], operands[1])" | |
509 | "<output_s>" | |
510 | [(set_attr "itanium_class" "<ld_class>") | |
511 | (set_attr "control_speculative" "<attr_yes>")]) | |
512 | ||
513 | (define_insn "zero_extend<mode>di2_speculative" | |
514 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
515 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))] | |
516 | "" | |
517 | "<output_s>" | |
518 | [(set_attr "itanium_class" "<ld_class>") | |
519 | (set_attr "control_speculative" "<attr_yes>")]) | |
520 | ||
521 | (define_insn "mov<mode>_speculative_advanced" | |
522 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
523 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))] | |
524 | "ia64_move_ok (operands[0], operands[1])" | |
525 | "<output_sa>" | |
526 | [(set_attr "itanium_class" "<ld_class>") | |
527 | (set_attr "data_speculative" "<attr_yes>") | |
528 | (set_attr "control_speculative" "<attr_yes>")]) | |
529 | ||
530 | (define_insn "zero_extend<mode>di2_speculative_advanced" | |
531 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
532 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))] | |
533 | "" | |
534 | "<output_sa>" | |
535 | [(set_attr "itanium_class" "<ld_class>") | |
536 | (set_attr "data_speculative" "<attr_yes>") | |
537 | (set_attr "control_speculative" "<attr_yes>")]) | |
538 | ||
539 | (define_insn "mov<mode>_clr" | |
540 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
541 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
542 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
543 | (match_dup 0)))] | |
544 | "ia64_move_ok (operands[0], operands[1])" | |
545 | "<output_c_clr>" | |
546 | [(set_attr "itanium_class" "<ld_class>") | |
547 | (set_attr "check_load" "<attr_yes>")]) | |
548 | ||
549 | (define_insn "zero_extend<mode>di2_clr" | |
550 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
551 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
552 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
553 | (match_dup 0)))] | |
554 | "" | |
555 | "<output_c_clr>" | |
556 | [(set_attr "itanium_class" "<ld_class>") | |
557 | (set_attr "check_load" "<attr_yes>")]) | |
558 | ||
559 | (define_insn "advanced_load_check_clr_<mode>" | |
560 | [(set (pc) | |
561 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0)) | |
562 | (pc) | |
563 | (label_ref (match_operand 1 "" ""))))] | |
564 | "" | |
565 | "chk.a.clr %0, %l1" | |
566 | [(set_attr "itanium_class" "<chka_class>")]) | |
567 | ||
568 | (define_insn "speculation_check_<mode>" | |
569 | [(set (pc) | |
570 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0)) | |
571 | (pc) | |
572 | (label_ref (match_operand 1 "" ""))))] | |
573 | "" | |
574 | "chk.s %0, %l1" | |
575 | [(set_attr "itanium_class" "<chks_class>")]) | |
576 | ||
9b7bf67d | 577 | (define_split |
21515593 RH |
578 | [(set (match_operand 0 "register_operand" "") |
579 | (match_operand 1 "symbolic_operand" ""))] | |
5e6c8b64 | 580 | "reload_completed" |
9b7bf67d | 581 | [(const_int 0)] |
9b7bf67d | 582 | { |
5e6c8b64 RH |
583 | if (ia64_expand_load_address (operands[0], operands[1])) |
584 | DONE; | |
585 | else | |
586 | FAIL; | |
1d5d7a21 | 587 | }) |
9b7bf67d | 588 | |
c65ebc55 | 589 | (define_expand "load_fptr" |
5e6c8b64 RH |
590 | [(set (match_operand:DI 0 "register_operand" "") |
591 | (plus:DI (match_dup 2) (match_operand 1 "function_operand" ""))) | |
592 | (set (match_dup 0) (match_dup 3))] | |
593 | "reload_completed" | |
c65ebc55 | 594 | { |
5e6c8b64 RH |
595 | operands[2] = pic_offset_table_rtx; |
596 | operands[3] = gen_const_mem (DImode, operands[0]); | |
1d5d7a21 | 597 | }) |
c65ebc55 JW |
598 | |
599 | (define_insn "*load_fptr_internal1" | |
600 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 601 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
5e6c8b64 | 602 | "reload_completed" |
c65ebc55 | 603 | "addl %0 = @ltoff(@fptr(%1)), gp" |
52e12ad0 | 604 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
605 | |
606 | (define_insn "load_gprel" | |
607 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 608 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
5e6c8b64 | 609 | "reload_completed" |
c65ebc55 | 610 | "addl %0 = @gprel(%1), gp" |
52e12ad0 | 611 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 612 | |
5e6c8b64 | 613 | (define_insn "*gprel64_offset" |
59da9a7d JW |
614 | [(set (match_operand:DI 0 "register_operand" "=r") |
615 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
5e6c8b64 | 616 | "reload_completed" |
59da9a7d | 617 | "movl %0 = @gprel(%1)" |
52e12ad0 | 618 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
619 | |
620 | (define_expand "load_gprel64" | |
5e6c8b64 RH |
621 | [(set (match_operand:DI 0 "register_operand" "") |
622 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2))) | |
623 | (set (match_dup 0) | |
624 | (plus:DI (match_dup 2) (match_dup 0)))] | |
625 | "reload_completed" | |
ec039e3c | 626 | { |
5e6c8b64 | 627 | operands[2] = pic_offset_table_rtx; |
1d5d7a21 | 628 | }) |
59da9a7d | 629 | |
af1e5518 RH |
630 | ;; This is used as a placeholder for the return address during early |
631 | ;; compilation. We won't know where we've placed this until during | |
632 | ;; reload, at which point it can wind up in b0, a general register, | |
633 | ;; or memory. The only safe destination under these conditions is a | |
634 | ;; general register. | |
635 | ||
636 | (define_insn_and_split "*movdi_ret_addr" | |
637 | [(set (match_operand:DI 0 "register_operand" "=r") | |
638 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
639 | "" | |
640 | "#" | |
641 | "reload_completed" | |
642 | [(const_int 0)] | |
643 | { | |
644 | ia64_split_return_addr_rtx (operands[0]); | |
645 | DONE; | |
646 | } | |
647 | [(set_attr "itanium_class" "ialu")]) | |
648 | ||
ef1ecf87 | 649 | (define_insn "*load_symptr_high" |
c65ebc55 | 650 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
651 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
652 | (match_operand:DI 2 "register_operand" "a")))] | |
5e6c8b64 | 653 | "reload_completed" |
ef1ecf87 RH |
654 | { |
655 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
656 | return "%,addl %0 = @ltoffx(%1), %2"; | |
657 | else | |
658 | return "%,addl %0 = @ltoff(%1), %2"; | |
659 | } | |
52e12ad0 | 660 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 661 | |
ef1ecf87 RH |
662 | (define_insn "*load_symptr_low" |
663 | [(set (match_operand:DI 0 "register_operand" "=r") | |
664 | (lo_sum:DI (match_operand:DI 1 "register_operand" "r") | |
665 | (match_operand 2 "got_symbolic_operand" "s")))] | |
5e6c8b64 | 666 | "reload_completed" |
ef1ecf87 RH |
667 | { |
668 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
669 | return "%,ld8.mov %0 = [%1], %2"; | |
670 | else | |
671 | return "%,ld8 %0 = [%1]"; | |
672 | } | |
673 | [(set_attr "itanium_class" "ld")]) | |
674 | ||
5e6c8b64 | 675 | (define_insn_and_split "load_dtpmod" |
7b6e506e | 676 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 677 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 | 678 | UNSPEC_DTPMOD))] |
7b6e506e | 679 | "" |
5e6c8b64 RH |
680 | "#" |
681 | "reload_completed" | |
682 | [(set (match_dup 0) | |
683 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD) | |
684 | (match_dup 2))) | |
685 | (set (match_dup 0) (match_dup 3))] | |
686 | { | |
687 | operands[2] = pic_offset_table_rtx; | |
688 | operands[3] = gen_const_mem (DImode, operands[0]); | |
689 | }) | |
7b6e506e | 690 | |
5e6c8b64 | 691 | (define_insn "*load_ltoff_dtpmod" |
7b6e506e | 692 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 693 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
694 | UNSPEC_LTOFF_DTPMOD) |
695 | (match_operand:DI 2 "register_operand" "a")))] | |
696 | "reload_completed" | |
697 | "addl %0 = @ltoff(@dtpmod(%1)), %2" | |
7b6e506e RH |
698 | [(set_attr "itanium_class" "ialu")]) |
699 | ||
700 | (define_expand "load_dtprel" | |
701 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 702 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
703 | UNSPEC_DTPREL))] |
704 | "" | |
705 | "") | |
706 | ||
707 | (define_insn "*load_dtprel64" | |
708 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 709 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
710 | UNSPEC_DTPREL))] |
711 | "TARGET_TLS64" | |
712 | "movl %0 = @dtprel(%1)" | |
713 | [(set_attr "itanium_class" "long_i")]) | |
714 | ||
715 | (define_insn "*load_dtprel22" | |
716 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 717 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
718 | UNSPEC_DTPREL))] |
719 | "" | |
720 | "addl %0 = @dtprel(%1), r0" | |
721 | [(set_attr "itanium_class" "ialu")]) | |
722 | ||
5e6c8b64 RH |
723 | (define_insn_and_split "*load_dtprel_gd" |
724 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 725 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
726 | UNSPEC_DTPREL))] |
727 | "" | |
728 | "#" | |
729 | "reload_completed" | |
730 | [(set (match_dup 0) | |
731 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL) | |
732 | (match_dup 2))) | |
733 | (set (match_dup 0) (match_dup 3))] | |
734 | { | |
735 | operands[2] = pic_offset_table_rtx; | |
736 | operands[3] = gen_const_mem (DImode, operands[0]); | |
737 | }) | |
738 | ||
739 | (define_insn "*load_ltoff_dtprel" | |
740 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 741 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
742 | UNSPEC_LTOFF_DTPREL) |
743 | (match_operand:DI 2 "register_operand" "a")))] | |
744 | "" | |
745 | "addl %0 = @ltoff(@dtprel(%1)), %2" | |
746 | [(set_attr "itanium_class" "ialu")]) | |
747 | ||
7b6e506e RH |
748 | (define_expand "add_dtprel" |
749 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 750 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
751 | UNSPEC_DTPREL) |
752 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
753 | "!TARGET_TLS64" |
754 | "") | |
755 | ||
756 | (define_insn "*add_dtprel14" | |
757 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 758 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
759 | UNSPEC_DTPREL) |
760 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 761 | "TARGET_TLS14" |
5e6c8b64 | 762 | "adds %0 = @dtprel(%1), %2" |
7b6e506e RH |
763 | [(set_attr "itanium_class" "ialu")]) |
764 | ||
765 | (define_insn "*add_dtprel22" | |
766 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 767 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
768 | UNSPEC_DTPREL) |
769 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 770 | "TARGET_TLS22" |
5e6c8b64 | 771 | "addl %0 = @dtprel(%1), %2" |
7b6e506e RH |
772 | [(set_attr "itanium_class" "ialu")]) |
773 | ||
774 | (define_expand "load_tprel" | |
775 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 776 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
777 | UNSPEC_TPREL))] |
778 | "" | |
779 | "") | |
780 | ||
781 | (define_insn "*load_tprel64" | |
782 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 783 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
784 | UNSPEC_TPREL))] |
785 | "TARGET_TLS64" | |
786 | "movl %0 = @tprel(%1)" | |
787 | [(set_attr "itanium_class" "long_i")]) | |
788 | ||
789 | (define_insn "*load_tprel22" | |
790 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 791 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
792 | UNSPEC_TPREL))] |
793 | "" | |
794 | "addl %0 = @tprel(%1), r0" | |
795 | [(set_attr "itanium_class" "ialu")]) | |
796 | ||
5e6c8b64 RH |
797 | (define_insn_and_split "*load_tprel_ie" |
798 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 799 | (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
800 | UNSPEC_TPREL))] |
801 | "" | |
802 | "#" | |
803 | "reload_completed" | |
804 | [(set (match_dup 0) | |
805 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL) | |
806 | (match_dup 2))) | |
807 | (set (match_dup 0) (match_dup 3))] | |
808 | { | |
809 | operands[2] = pic_offset_table_rtx; | |
810 | operands[3] = gen_const_mem (DImode, operands[0]); | |
811 | }) | |
812 | ||
813 | (define_insn "*load_ltoff_tprel" | |
814 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 815 | (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
816 | UNSPEC_LTOFF_TPREL) |
817 | (match_operand:DI 2 "register_operand" "a")))] | |
818 | "" | |
819 | "addl %0 = @ltoff(@tprel(%1)), %2" | |
820 | [(set_attr "itanium_class" "ialu")]) | |
821 | ||
7b6e506e RH |
822 | (define_expand "add_tprel" |
823 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 824 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
825 | UNSPEC_TPREL) |
826 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
827 | "!TARGET_TLS64" |
828 | "") | |
829 | ||
830 | (define_insn "*add_tprel14" | |
831 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 832 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
833 | UNSPEC_TPREL) |
834 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 835 | "TARGET_TLS14" |
5e6c8b64 | 836 | "adds %0 = @tprel(%1), %2" |
7b6e506e RH |
837 | [(set_attr "itanium_class" "ialu")]) |
838 | ||
839 | (define_insn "*add_tprel22" | |
840 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 841 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
842 | UNSPEC_TPREL) |
843 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 844 | "TARGET_TLS22" |
5e6c8b64 | 845 | "addl %0 = @tprel(%1), %2" |
7b6e506e RH |
846 | [(set_attr "itanium_class" "ialu")]) |
847 | ||
3f622353 | 848 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
849 | ;; around to play with the second word. However, in order to avoid a |
850 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
851 | ;; in ia64_split_tmode_move. | |
3f622353 | 852 | (define_expand "movti" |
2ffe0e02 ZW |
853 | [(set (match_operand:TI 0 "general_operand" "") |
854 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 855 | "" |
3f622353 | 856 | { |
7b6e506e RH |
857 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
858 | if (!op1) | |
859 | DONE; | |
860 | operands[1] = op1; | |
1d5d7a21 | 861 | }) |
3f622353 RH |
862 | |
863 | (define_insn_and_split "*movti_internal" | |
b6fb7d46 JW |
864 | [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q") |
865 | (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))] | |
3f622353 | 866 | "ia64_move_ok (operands[0], operands[1])" |
a71aef0b JB |
867 | "@ |
868 | # | |
869 | # | |
870 | ldfp8 %X0 = %1%P1 | |
871 | # | |
872 | #" | |
873 | "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])" | |
3f622353 | 874 | [(const_int 0)] |
3f622353 | 875 | { |
f57fc998 | 876 | ia64_split_tmode_move (operands); |
3f622353 | 877 | DONE; |
1d5d7a21 | 878 | } |
a71aef0b | 879 | [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")]) |
e314e331 | 880 | |
c65ebc55 JW |
881 | ;; Floating Point Moves |
882 | ;; | |
883 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 884 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
885 | |
886 | (define_expand "movsf" | |
887 | [(set (match_operand:SF 0 "general_operand" "") | |
888 | (match_operand:SF 1 "general_operand" ""))] | |
889 | "" | |
c65ebc55 | 890 | { |
7b6e506e RH |
891 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
892 | if (!op1) | |
893 | DONE; | |
894 | operands[1] = op1; | |
1d5d7a21 | 895 | }) |
c65ebc55 | 896 | |
c65ebc55 | 897 | (define_insn "*movsf_internal" |
4b983fdc RH |
898 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
899 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 900 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 901 | "@ |
1d5d7a21 RH |
902 | mov %0 = %F1 |
903 | ldfs %0 = %1%P1 | |
904 | stfs %0 = %F1%P0 | |
905 | getf.s %0 = %F1 | |
906 | setf.s %0 = %1 | |
907 | mov %0 = %1 | |
908 | ld4%O1 %0 = %1%P1 | |
909 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 910 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
911 | |
912 | (define_expand "movdf" | |
913 | [(set (match_operand:DF 0 "general_operand" "") | |
914 | (match_operand:DF 1 "general_operand" ""))] | |
915 | "" | |
c65ebc55 | 916 | { |
7b6e506e RH |
917 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
918 | if (!op1) | |
919 | DONE; | |
920 | operands[1] = op1; | |
1d5d7a21 | 921 | }) |
c65ebc55 | 922 | |
c65ebc55 | 923 | (define_insn "*movdf_internal" |
4b983fdc RH |
924 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
925 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 926 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 927 | "@ |
1d5d7a21 RH |
928 | mov %0 = %F1 |
929 | ldfd %0 = %1%P1 | |
930 | stfd %0 = %F1%P0 | |
931 | getf.d %0 = %F1 | |
932 | setf.d %0 = %1 | |
933 | mov %0 = %1 | |
934 | ld8%O1 %0 = %1%P1 | |
935 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 936 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 937 | |
3f622353 RH |
938 | ;; With no offsettable memory references, we've got to have a scratch |
939 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
940 | (define_expand "movxf" |
941 | [(set (match_operand:XF 0 "general_operand" "") | |
942 | (match_operand:XF 1 "general_operand" ""))] | |
943 | "" | |
e5bde68a | 944 | { |
4de67c26 JM |
945 | if (ia64_expand_movxf_movrf (XFmode, operands)) |
946 | DONE; | |
1d5d7a21 | 947 | }) |
e5bde68a | 948 | |
3b572406 | 949 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 950 | |
02befdf4 | 951 | (define_insn "*movxf_internal" |
78d8e0f9 ZW |
952 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
953 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 954 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 955 | "@ |
1d5d7a21 RH |
956 | mov %0 = %F1 |
957 | ldfe %0 = %1%P1 | |
958 | stfe %0 = %F1%P0" | |
52e12ad0 | 959 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
f57fc998 | 960 | |
4de67c26 JM |
961 | ;; Same as for movxf, but for RFmode. |
962 | (define_expand "movrf" | |
963 | [(set (match_operand:RF 0 "general_operand" "") | |
964 | (match_operand:RF 1 "general_operand" ""))] | |
965 | "" | |
966 | { | |
967 | if (ia64_expand_movxf_movrf (RFmode, operands)) | |
968 | DONE; | |
969 | }) | |
970 | ||
971 | (define_insn "*movrf_internal" | |
972 | [(set (match_operand:RF 0 "destination_operand" "=f,f, m") | |
973 | (match_operand:RF 1 "general_operand" "fG,m,fG"))] | |
974 | "ia64_move_ok (operands[0], operands[1])" | |
975 | "@ | |
976 | mov %0 = %F1 | |
977 | ldf.fill %0 = %1%P1 | |
978 | stf.spill %0 = %F1%P0" | |
979 | [(set_attr "itanium_class" "fmisc,fld,stf")]) | |
980 | ||
f57fc998 | 981 | ;; Better code generation via insns that deal with TFmode register pairs |
2ffe0e02 | 982 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 983 | (define_expand "movtf" |
2ffe0e02 ZW |
984 | [(set (match_operand:TF 0 "general_operand" "") |
985 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
986 | "" |
987 | { | |
988 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
989 | if (!op1) | |
990 | DONE; | |
991 | operands[1] = op1; | |
992 | }) | |
993 | ||
994 | (define_insn_and_split "*movtf_internal" | |
e77ee95d | 995 | [(set (match_operand:TF 0 "destination_operand" "=r,r,m") |
2ffe0e02 | 996 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
997 | "ia64_move_ok (operands[0], operands[1])" |
998 | "#" | |
999 | "reload_completed" | |
1000 | [(const_int 0)] | |
1001 | { | |
1002 | ia64_split_tmode_move (operands); | |
1003 | DONE; | |
1004 | } | |
1005 | [(set_attr "itanium_class" "unknown") | |
1006 | (set_attr "predicable" "no")]) | |
1007 | ||
c65ebc55 JW |
1008 | \f |
1009 | ;; :::::::::::::::::::: | |
1010 | ;; :: | |
1011 | ;; :: Conversions | |
1012 | ;; :: | |
1013 | ;; :::::::::::::::::::: | |
1014 | ||
1015 | ;; Signed conversions from a smaller integer to a larger integer | |
1016 | ||
1017 | (define_insn "extendqidi2" | |
0551c32d RH |
1018 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1019 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1020 | "" |
1021 | "sxt1 %0 = %1" | |
52e12ad0 | 1022 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1023 | |
1024 | (define_insn "extendhidi2" | |
0551c32d RH |
1025 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1026 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1027 | "" |
1028 | "sxt2 %0 = %1" | |
52e12ad0 | 1029 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1030 | |
1031 | (define_insn "extendsidi2" | |
655f2eb9 RH |
1032 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
1033 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
1034 | "" |
1035 | "@ | |
1036 | sxt4 %0 = %1 | |
aebf2462 | 1037 | fsxt.r %0 = %1, %1" |
52e12ad0 | 1038 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
1039 | |
1040 | ;; Unsigned conversions from a smaller integer to a larger integer | |
1041 | ||
1042 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
1043 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1044 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1045 | "" |
1046 | "@ | |
1047 | zxt1 %0 = %1 | |
1048 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 1049 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
1050 | |
1051 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
1052 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1053 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1054 | "" |
1055 | "@ | |
1056 | zxt2 %0 = %1 | |
1057 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 1058 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
1059 | |
1060 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 1061 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 1062 | (zero_extend:DI |
655f2eb9 | 1063 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
1064 | "" |
1065 | "@ | |
d3f6e07b | 1066 | addp4 %0 = %1, r0 |
c65ebc55 | 1067 | ld4%O1 %0 = %1%P1 |
aebf2462 | 1068 | fmix.r %0 = f0, %1" |
d3f6e07b | 1069 | [(set_attr "itanium_class" "ialu,ld,fmisc")]) |
c65ebc55 JW |
1070 | |
1071 | ;; Convert between floating point types of different sizes. | |
1072 | ||
640cea5f JW |
1073 | ;; At first glance, it would appear that emitting fnorm for an extending |
1074 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
1075 | ;; correctly only if the input is properly rounded for its type. In | |
1076 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
1077 | ;; denorm single. Since we don't know what the next instruction will be, we | |
1078 | ;; have to emit an fnorm. | |
1079 | ||
e8e20f18 RH |
1080 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
1081 | ;; when we can. Should probably use a scheme like has been proposed | |
1082 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
1083 | ;; would let combine merge the thing into adjacent insns. See also how the |
1084 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
1085 | ;; se_register_operand. | |
c65ebc55 | 1086 | |
640cea5f JW |
1087 | (define_insn "extendsfdf2" |
1088 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
1089 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1090 | "" |
640cea5f JW |
1091 | "fnorm.d %0 = %1" |
1092 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 1093 | |
02befdf4 ZW |
1094 | (define_insn "extendsfxf2" |
1095 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1096 | (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))] | |
1097 | "" | |
640cea5f JW |
1098 | "fnorm %0 = %1" |
1099 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 1100 | |
02befdf4 ZW |
1101 | (define_insn "extenddfxf2" |
1102 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1103 | (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))] | |
1104 | "" | |
640cea5f JW |
1105 | "fnorm %0 = %1" |
1106 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 1107 | |
c65ebc55 | 1108 | (define_insn "truncdfsf2" |
0551c32d RH |
1109 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1110 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1111 | "" |
aebf2462 | 1112 | "fnorm.s %0 = %1" |
52e12ad0 | 1113 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1114 | |
02befdf4 | 1115 | (define_insn "truncxfsf2" |
0551c32d | 1116 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1117 | (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))] |
1118 | "" | |
aebf2462 | 1119 | "fnorm.s %0 = %1" |
52e12ad0 | 1120 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1121 | |
02befdf4 | 1122 | (define_insn "truncxfdf2" |
0551c32d | 1123 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1124 | (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))] |
1125 | "" | |
aebf2462 | 1126 | "fnorm.d %0 = %1" |
52e12ad0 | 1127 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
1128 | |
1129 | ;; Convert between signed integer types and floating point. | |
1130 | ||
02befdf4 ZW |
1131 | (define_insn "floatdixf2" |
1132 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1133 | (float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
1134 | "" | |
e5bde68a | 1135 | "fcvt.xf %0 = %1" |
52e12ad0 | 1136 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1137 | |
1138 | (define_insn "fix_truncsfdi2" | |
0551c32d RH |
1139 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1140 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1141 | "" |
aebf2462 | 1142 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1143 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1144 | |
1145 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
1146 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1147 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1148 | "" |
aebf2462 | 1149 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1150 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1151 | |
02befdf4 | 1152 | (define_insn "fix_truncxfdi2" |
0551c32d | 1153 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1154 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1155 | "" | |
aebf2462 | 1156 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1157 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1158 | |
02befdf4 | 1159 | (define_insn "fix_truncxfdi2_alts" |
655f2eb9 | 1160 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1161 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1162 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1163 | "" |
aebf2462 | 1164 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 1165 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1166 | |
c65ebc55 JW |
1167 | ;; Convert between unsigned integer types and floating point. |
1168 | ||
1169 | (define_insn "floatunsdisf2" | |
0551c32d RH |
1170 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1171 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1172 | "" |
aebf2462 | 1173 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 1174 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1175 | |
1176 | (define_insn "floatunsdidf2" | |
0551c32d RH |
1177 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
1178 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1179 | "" |
aebf2462 | 1180 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 1181 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1182 | |
02befdf4 ZW |
1183 | (define_insn "floatunsdixf2" |
1184 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1185 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
1186 | "" | |
aebf2462 | 1187 | "fcvt.xuf %0 = %1" |
52e12ad0 | 1188 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1189 | |
c65ebc55 | 1190 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
1191 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1192 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1193 | "" |
aebf2462 | 1194 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1195 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1196 | |
1197 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
1198 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1199 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1200 | "" |
aebf2462 | 1201 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1202 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1203 | |
02befdf4 | 1204 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 1205 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1206 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1207 | "" | |
aebf2462 | 1208 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1209 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1210 | |
02befdf4 | 1211 | (define_insn "fixuns_truncxfdi2_alts" |
655f2eb9 | 1212 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1213 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1214 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1215 | "" |
aebf2462 | 1216 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 1217 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1218 | \f |
1219 | ;; :::::::::::::::::::: | |
1220 | ;; :: | |
1221 | ;; :: Bit field extraction | |
1222 | ;; :: | |
1223 | ;; :::::::::::::::::::: | |
1224 | ||
c65ebc55 | 1225 | (define_insn "extv" |
0551c32d RH |
1226 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1227 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1228 | (match_operand:DI 2 "extr_len_operand" "n") |
1229 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1230 | "" |
1231 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1232 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1233 | |
1234 | (define_insn "extzv" | |
0551c32d RH |
1235 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1236 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1237 | (match_operand:DI 2 "extr_len_operand" "n") |
1238 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1239 | "" |
1240 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1241 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1242 | |
1243 | ;; Insert a bit field. | |
1244 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1245 | ;; Source1 can be 0 or -1. | |
1246 | ;; Source2 can be 0. | |
1247 | ||
1248 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1249 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1250 | ;; where source2 != dest. | |
1251 | ||
1252 | (define_expand "insv" | |
0551c32d | 1253 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1254 | (match_operand:DI 1 "const_int_operand" "") |
1255 | (match_operand:DI 2 "const_int_operand" "")) | |
1256 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1257 | "" | |
c65ebc55 JW |
1258 | { |
1259 | int width = INTVAL (operands[1]); | |
1260 | int shift = INTVAL (operands[2]); | |
1261 | ||
1262 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1263 | pseudo. */ | |
1264 | if (! register_operand (operands[3], DImode) | |
1265 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1266 | operands[3] = force_reg (DImode, operands[3]); | |
1267 | ||
1268 | /* If this is a single dep instruction, we have nothing to do. */ | |
1269 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1270 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1271 | { | |
1272 | /* Check for cases that can be implemented with a mix instruction. */ | |
1273 | if (width == 32 && shift == 0) | |
1274 | { | |
1275 | /* Directly generating the mix4left instruction confuses | |
1276 | optimize_bit_field in function.c. Since this is performing | |
1277 | a useful optimization, we defer generation of the complicated | |
1278 | mix4left RTL to the first splitting phase. */ | |
1279 | rtx tmp = gen_reg_rtx (DImode); | |
1280 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1281 | DONE; | |
1282 | } | |
1283 | else if (width == 32 && shift == 32) | |
1284 | { | |
1285 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1286 | DONE; | |
1287 | } | |
1288 | ||
d2ba6dcf JW |
1289 | /* We could handle remaining cases by emitting multiple dep |
1290 | instructions. | |
1291 | ||
1292 | If we need more than two dep instructions then we lose. A 6 | |
1293 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1294 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1295 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1296 | only one function unit that can execute dep and shr immed. | |
1297 | ||
1298 | If we only need two dep instruction, then we still lose. | |
1299 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1300 | the unnecessary mov, this is still undesirable because it will be | |
1301 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1302 | function unit. */ | |
1303 | ||
c65ebc55 JW |
1304 | FAIL; |
1305 | ||
1306 | #if 0 | |
1307 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1308 | for now. */ | |
1309 | while (width > 16) | |
1310 | { | |
1311 | rtx tmp; | |
1312 | ||
1313 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1314 | operands[3])); | |
1315 | shift += 16; | |
1316 | width -= 16; | |
1317 | tmp = gen_reg_rtx (DImode); | |
1318 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1319 | operands[3] = tmp; | |
1320 | } | |
1321 | operands[1] = GEN_INT (width); | |
1322 | operands[2] = GEN_INT (shift); | |
1323 | #endif | |
1324 | } | |
1d5d7a21 | 1325 | }) |
c65ebc55 JW |
1326 | |
1327 | (define_insn "*insv_internal" | |
0551c32d | 1328 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1329 | (match_operand:DI 1 "const_int_operand" "n") |
1330 | (match_operand:DI 2 "const_int_operand" "n")) | |
1331 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1332 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1333 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1334 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1335 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1336 | |
43a88a8c | 1337 | ;; Combine doesn't like to create bit-field insertions into zero. |
d3f6e07b JB |
1338 | (define_insn "*shladdp4_internal" |
1339 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
1340 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1341 | (match_operand:DI 2 "shladd_log2_operand" "n")) | |
1342 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1343 | "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" | |
1344 | "shladdp4 %0 = %1, %2, r0" | |
1345 | [(set_attr "itanium_class" "ialu")]) | |
1346 | ||
041f25e6 | 1347 | (define_insn "*depz_internal" |
0551c32d RH |
1348 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1349 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
13f70342 | 1350 | (match_operand:DI 2 "const_int_operand" "M")) |
041f25e6 | 1351 | (match_operand:DI 3 "const_int_operand" "n")))] |
13f70342 | 1352 | "satisfies_constraint_M (operands[2]) |
041f25e6 | 1353 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" |
041f25e6 RH |
1354 | { |
1355 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1356 | return "%,dep.z %0 = %1, %2, %3"; |
1357 | } | |
52e12ad0 | 1358 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1359 | |
c65ebc55 | 1360 | (define_insn "shift_mix4left" |
0551c32d | 1361 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1362 | (const_int 32) (const_int 0)) |
0551c32d RH |
1363 | (match_operand:DI 1 "gr_register_operand" "r")) |
1364 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1365 | "" |
1366 | "#" | |
52e12ad0 | 1367 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1368 | |
c65ebc55 JW |
1369 | (define_split |
1370 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1371 | (const_int 32) (const_int 0)) | |
1372 | (match_operand:DI 1 "register_operand" "")) | |
1373 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1374 | "" |
c65ebc55 JW |
1375 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1376 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1377 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1378 | "operands[3] = operands[2];") | |
1379 | ||
1380 | (define_insn "*mix4left" | |
0551c32d | 1381 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1382 | (const_int 32) (const_int 0)) |
0551c32d | 1383 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1384 | (const_int 32)))] |
1385 | "" | |
1386 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1387 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1388 | |
1389 | (define_insn "mix4right" | |
0551c32d | 1390 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1391 | (const_int 32) (const_int 32)) |
0551c32d | 1392 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1393 | "" |
1394 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1395 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1396 | |
1397 | ;; This is used by the rotrsi3 pattern. | |
1398 | ||
1399 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1400 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1401 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1402 | (ashift:DI (zero_extend:DI | |
1403 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1404 | (const_int 32))))] |
1405 | "" | |
fa9a44e8 | 1406 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1407 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1408 | |
1409 | \f | |
1410 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1411 | ;; :: |
27a9b99d | 1412 | ;; :: 1-bit Integer arithmetic |
f2f90c63 RH |
1413 | ;; :: |
1414 | ;; :::::::::::::::::::: | |
1415 | ||
1416 | (define_insn_and_split "andbi3" | |
1417 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1418 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1419 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1420 | "" | |
1421 | "@ | |
1422 | # | |
1423 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1424 | and %0 = %2, %1" | |
1425 | "reload_completed | |
1426 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1427 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1428 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1429 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1430 | (match_dup 0))))] | |
1431 | "" | |
52e12ad0 | 1432 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1433 | |
1434 | (define_insn_and_split "*andcmbi3" | |
1435 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1436 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1437 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1438 | "" | |
1439 | "@ | |
1440 | # | |
967603ef | 1441 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1442 | andcm %0 = %2, %1" |
1443 | "reload_completed | |
1444 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1445 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1446 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1447 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1448 | (match_dup 0))))] | |
1449 | "" | |
52e12ad0 | 1450 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1451 | |
1452 | (define_insn_and_split "iorbi3" | |
1453 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1454 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1455 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1456 | "" | |
1457 | "@ | |
1458 | # | |
1459 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1460 | or %0 = %2, %1" | |
1461 | "reload_completed | |
1462 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1463 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1464 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1465 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1466 | (match_dup 0))))] | |
1467 | "" | |
52e12ad0 | 1468 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1469 | |
1470 | (define_insn_and_split "*iorcmbi3" | |
1471 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1472 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1473 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1474 | "" | |
1475 | "@ | |
1476 | # | |
967603ef | 1477 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1478 | "reload_completed |
1479 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1480 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1481 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1482 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1483 | (match_dup 0))))] | |
1484 | "" | |
52e12ad0 | 1485 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1486 | |
1487 | (define_insn "one_cmplbi2" | |
1488 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1489 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1490 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1491 | "" | |
1492 | "@ | |
1493 | tbit.z %0, %I0 = %1, 0 | |
1494 | xor %0 = 1, %1 | |
1495 | # | |
1496 | #" | |
52e12ad0 | 1497 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1498 | |
1499 | (define_split | |
1500 | [(set (match_operand:BI 0 "register_operand" "") | |
1501 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1502 | (clobber (match_scratch:BI 2 ""))] | |
1503 | "reload_completed | |
1504 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1505 | && rtx_equal_p (operands[0], operands[1])" |
1506 | [(set (match_dup 4) (match_dup 3)) | |
1507 | (set (match_dup 0) (const_int 1)) | |
1508 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1509 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1510 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1511 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1512 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1513 | ||
1514 | (define_split | |
1515 | [(set (match_operand:BI 0 "register_operand" "") | |
1516 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1517 | (clobber (match_scratch:BI 2 ""))] | |
1518 | "reload_completed | |
1519 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1520 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1521 | && ! rtx_equal_p (operands[0], operands[1])" | |
1522 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1523 | (set (match_dup 0) (const_int 0))) | |
1524 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1525 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1526 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1527 | "") |
1528 | ||
1529 | (define_insn "*cmpsi_and_0" | |
1530 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1531 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1532 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1533 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1534 | (match_operand:BI 1 "register_operand" "0")))] | |
1535 | "" | |
1536 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1537 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1538 | |
1539 | (define_insn "*cmpsi_and_1" | |
1540 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1541 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1542 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1543 | (const_int 0)]) | |
1544 | (match_operand:BI 1 "register_operand" "0")))] | |
1545 | "" | |
1546 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1547 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1548 | |
1549 | (define_insn "*cmpsi_andnot_0" | |
1550 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1551 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1552 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1553 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1554 | (match_operand:BI 1 "register_operand" "0")))] | |
1555 | "" | |
1556 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1557 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1558 | |
1559 | (define_insn "*cmpsi_andnot_1" | |
1560 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1561 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1562 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1563 | (const_int 0)])) | |
1564 | (match_operand:BI 1 "register_operand" "0")))] | |
1565 | "" | |
1566 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1567 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1568 | |
1569 | (define_insn "*cmpdi_and_0" | |
1570 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1571 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1572 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1573 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1574 | (match_operand:BI 1 "register_operand" "0")))] | |
1575 | "" | |
1576 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1577 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1578 | |
1579 | (define_insn "*cmpdi_and_1" | |
1580 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1581 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1582 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1583 | (const_int 0)]) | |
1584 | (match_operand:BI 1 "register_operand" "0")))] | |
1585 | "" | |
1586 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1587 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1588 | |
1589 | (define_insn "*cmpdi_andnot_0" | |
1590 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1591 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1592 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1593 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1594 | (match_operand:BI 1 "register_operand" "0")))] | |
1595 | "" | |
1596 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1597 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1598 | |
1599 | (define_insn "*cmpdi_andnot_1" | |
1600 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1601 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1602 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1603 | (const_int 0)])) | |
1604 | (match_operand:BI 1 "register_operand" "0")))] | |
1605 | "" | |
1606 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1607 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1608 | |
1609 | (define_insn "*tbit_and_0" | |
1610 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1611 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1612 | (const_int 1)) | |
1613 | (const_int 0)) | |
c77e04ae | 1614 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1615 | "" |
1616 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1617 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1618 | |
1619 | (define_insn "*tbit_and_1" | |
1620 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1621 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1622 | (const_int 1)) | |
1623 | (const_int 0)) | |
c77e04ae | 1624 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1625 | "" |
1626 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1627 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1628 | |
1629 | (define_insn "*tbit_and_2" | |
1630 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1631 | (and:BI (ne:BI (zero_extract:DI | |
1632 | (match_operand:DI 1 "gr_register_operand" "r") | |
1633 | (const_int 1) | |
5d48891e | 1634 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1635 | (const_int 0)) |
1636 | (match_operand:BI 3 "register_operand" "0")))] | |
1637 | "" | |
1638 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1639 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1640 | |
1641 | (define_insn "*tbit_and_3" | |
1642 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1643 | (and:BI (eq:BI (zero_extract:DI | |
1644 | (match_operand:DI 1 "gr_register_operand" "r") | |
1645 | (const_int 1) | |
5d48891e | 1646 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1647 | (const_int 0)) |
1648 | (match_operand:BI 3 "register_operand" "0")))] | |
1649 | "" | |
1650 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1651 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1652 | |
1653 | (define_insn "*cmpsi_or_0" | |
1654 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1655 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1656 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1657 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1658 | (match_operand:BI 1 "register_operand" "0")))] | |
1659 | "" | |
1660 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1661 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1662 | |
1663 | (define_insn "*cmpsi_or_1" | |
1664 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1665 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1666 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1667 | (const_int 0)]) | |
1668 | (match_operand:BI 1 "register_operand" "0")))] | |
1669 | "" | |
1670 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1671 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1672 | |
1673 | (define_insn "*cmpsi_orcm_0" | |
1674 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1675 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1676 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1677 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1678 | (match_operand:BI 1 "register_operand" "0")))] | |
1679 | "" | |
1680 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1681 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1682 | |
1683 | (define_insn "*cmpsi_orcm_1" | |
1684 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1685 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1686 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1687 | (const_int 0)])) | |
1688 | (match_operand:BI 1 "register_operand" "0")))] | |
1689 | "" | |
1690 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1691 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1692 | |
1693 | (define_insn "*cmpdi_or_0" | |
1694 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1695 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1696 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1697 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1698 | (match_operand:BI 1 "register_operand" "0")))] | |
1699 | "" | |
1700 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1701 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1702 | |
1703 | (define_insn "*cmpdi_or_1" | |
1704 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1705 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1706 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1707 | (const_int 0)]) | |
1708 | (match_operand:BI 1 "register_operand" "0")))] | |
1709 | "" | |
1710 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1711 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1712 | |
1713 | (define_insn "*cmpdi_orcm_0" | |
1714 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1715 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1716 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1717 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1718 | (match_operand:BI 1 "register_operand" "0")))] | |
1719 | "" | |
1720 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1721 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1722 | |
1723 | (define_insn "*cmpdi_orcm_1" | |
1724 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1725 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1726 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1727 | (const_int 0)])) | |
1728 | (match_operand:BI 1 "register_operand" "0")))] | |
1729 | "" | |
1730 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1731 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1732 | |
1733 | (define_insn "*tbit_or_0" | |
1734 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1735 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1736 | (const_int 1)) | |
1737 | (const_int 0)) | |
c77e04ae | 1738 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1739 | "" |
1740 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1741 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1742 | |
1743 | (define_insn "*tbit_or_1" | |
1744 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1745 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1746 | (const_int 1)) | |
1747 | (const_int 0)) | |
c77e04ae | 1748 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1749 | "" |
1750 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1751 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1752 | |
1753 | (define_insn "*tbit_or_2" | |
1754 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1755 | (ior:BI (ne:BI (zero_extract:DI | |
1756 | (match_operand:DI 1 "gr_register_operand" "r") | |
1757 | (const_int 1) | |
5d48891e | 1758 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1759 | (const_int 0)) |
1760 | (match_operand:BI 3 "register_operand" "0")))] | |
1761 | "" | |
1762 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1763 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1764 | |
1765 | (define_insn "*tbit_or_3" | |
1766 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1767 | (ior:BI (eq:BI (zero_extract:DI | |
1768 | (match_operand:DI 1 "gr_register_operand" "r") | |
1769 | (const_int 1) | |
5d48891e | 1770 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1771 | (const_int 0)) |
1772 | (match_operand:BI 3 "register_operand" "0")))] | |
1773 | "" | |
1774 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1775 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1776 | |
1777 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1778 | ||
1779 | (define_split | |
1780 | [(set (match_operand:BI 0 "register_operand" "") | |
1781 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1782 | (const_int 0)) | |
1783 | (match_operand:DI 3 "register_operand" "")) | |
1784 | (const_int 0)))] | |
1785 | "" | |
1786 | [(set (match_dup 0) | |
1787 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1788 | (match_dup 2)))] | |
1789 | "") | |
1790 | ||
1791 | (define_split | |
1792 | [(set (match_operand:BI 0 "register_operand" "") | |
1793 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1794 | (const_int 0)) | |
1795 | (match_operand:DI 3 "register_operand" "")) | |
1796 | (const_int 0)))] | |
1797 | "" | |
1798 | [(set (match_dup 0) | |
1799 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1800 | (match_dup 2))) | |
1801 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1802 | (clobber (scratch))])] | |
1803 | "") | |
1804 | ||
1805 | (define_split | |
1806 | [(set (match_operand:BI 0 "register_operand" "") | |
1807 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1808 | (const_int 0)) | |
1809 | (match_operand:DI 3 "register_operand" "")) | |
1810 | (const_int 0)))] | |
1811 | "" | |
1812 | [(set (match_dup 0) | |
1813 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1814 | (match_dup 2)))] | |
1815 | "") | |
1816 | ||
1817 | (define_split | |
1818 | [(set (match_operand:BI 0 "register_operand" "") | |
1819 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1820 | (const_int 0)) | |
1821 | (match_operand:DI 3 "register_operand" "")) | |
1822 | (const_int 0)))] | |
1823 | "" | |
1824 | [(set (match_dup 0) | |
1825 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1826 | (match_dup 2))) | |
1827 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1828 | (clobber (scratch))])] | |
1829 | "") | |
1830 | ||
1831 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1832 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1833 | ;; nothing bad happens to the comparisons in the meantime. | |
1834 | ;; | |
1835 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1836 | ;; that we're doing height reduction. | |
1837 | ; | |
1838 | ;(define_insn_and_split "" | |
1839 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1840 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1841 | ; [(match_operand 2 "" "") | |
1842 | ; (match_operand 3 "" "")]) | |
1843 | ; (match_operator:BI 4 "comparison_operator" | |
1844 | ; [(match_operand 5 "" "") | |
1845 | ; (match_operand 6 "" "")])) | |
1846 | ; (match_dup 0)))] | |
1847 | ; "flag_schedule_insns" | |
1848 | ; "#" | |
1849 | ; "" | |
1850 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1851 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1852 | ; "") | |
1853 | ; | |
1854 | ;(define_insn_and_split "" | |
1855 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1856 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1857 | ; [(match_operand 2 "" "") | |
1858 | ; (match_operand 3 "" "")]) | |
1859 | ; (match_operator:BI 4 "comparison_operator" | |
1860 | ; [(match_operand 5 "" "") | |
1861 | ; (match_operand 6 "" "")])) | |
1862 | ; (match_dup 0)))] | |
1863 | ; "flag_schedule_insns" | |
1864 | ; "#" | |
1865 | ; "" | |
1866 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1867 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1868 | ; "") | |
1869 | ; | |
1870 | ;(define_split | |
1871 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1872 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1873 | ; [(match_operand 2 "" "") | |
1874 | ; (match_operand 3 "" "")]) | |
1875 | ; (match_operand:BI 7 "register_operand" "")) | |
1876 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1877 | ; [(match_operand 5 "" "") | |
1878 | ; (match_operand 6 "" "")]) | |
1879 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1880 | ; "" | |
1881 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1882 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1883 | ; (match_dup 0)))] | |
1884 | ; "") | |
1885 | ; | |
1886 | ;(define_split | |
1887 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1888 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1889 | ; [(match_operand 2 "" "") | |
1890 | ; (match_operand 3 "" "")]) | |
1891 | ; (match_operand:BI 7 "register_operand" "")) | |
1892 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1893 | ; [(match_operand 5 "" "") | |
1894 | ; (match_operand 6 "" "")]) | |
1895 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1896 | ; "" | |
1897 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
1898 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
1899 | ; (match_dup 0)))] | |
1900 | ; "") | |
1901 | ||
1902 | ;; Try harder to avoid predicate copies by duplicating compares. | |
1903 | ;; Note that we'll have already split the predicate copy, which | |
1904 | ;; is kind of a pain, but oh well. | |
1905 | ||
1906 | (define_peephole2 | |
1907 | [(set (match_operand:BI 0 "register_operand" "") | |
1908 | (match_operand:BI 1 "comparison_operator" "")) | |
1909 | (set (match_operand:CCI 2 "register_operand" "") | |
1910 | (match_operand:CCI 3 "register_operand" "")) | |
1911 | (set (match_operand:CCI 4 "register_operand" "") | |
1912 | (match_operand:CCI 5 "register_operand" "")) | |
1913 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 1914 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1915 | "REGNO (operands[3]) == REGNO (operands[0]) |
1916 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
1917 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
1918 | && REGNO (operands[6]) == REGNO (operands[2])" | |
1919 | [(set (match_dup 0) (match_dup 1)) | |
1920 | (set (match_dup 6) (match_dup 7))] | |
1921 | "operands[7] = copy_rtx (operands[1]);") | |
1922 | \f | |
1923 | ;; :::::::::::::::::::: | |
1924 | ;; :: | |
27a9b99d | 1925 | ;; :: 16-bit Integer arithmetic |
cf1f6ae3 RH |
1926 | ;; :: |
1927 | ;; :::::::::::::::::::: | |
1928 | ||
1929 | (define_insn "mulhi3" | |
1930 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
1931 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
1932 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
1933 | "" | |
2a7ffc85 | 1934 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 1935 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
1936 | |
1937 | \f | |
1938 | ;; :::::::::::::::::::: | |
c65ebc55 | 1939 | ;; :: |
27a9b99d | 1940 | ;; :: 32-bit Integer arithmetic |
c65ebc55 JW |
1941 | ;; :: |
1942 | ;; :::::::::::::::::::: | |
1943 | ||
058557c4 | 1944 | (define_insn "addsi3" |
0551c32d RH |
1945 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
1946 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
1947 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
1948 | "" |
1949 | "@ | |
1d5d7a21 RH |
1950 | add %0 = %1, %2 |
1951 | adds %0 = %2, %1 | |
1952 | addl %0 = %2, %1" | |
52e12ad0 | 1953 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1954 | |
1955 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
1956 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1957 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
1958 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1959 | (const_int 1)))] |
1960 | "" | |
1961 | "add %0 = %1, %2, 1" | |
52e12ad0 | 1962 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1963 | |
5527bf14 | 1964 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
1965 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1966 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
1967 | (const_int 2)) |
1968 | (const_int 1)))] | |
1969 | "" | |
1970 | "add %0 = %1, %1, 1" | |
52e12ad0 | 1971 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 1972 | |
058557c4 | 1973 | (define_insn "*addsi3_shladd" |
0551c32d RH |
1974 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1975 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 1976 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 1977 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 1978 | "" |
058557c4 | 1979 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 1980 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1981 | |
058557c4 | 1982 | (define_insn "subsi3" |
0551c32d RH |
1983 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1984 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
1985 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1986 | "" |
1987 | "sub %0 = %1, %2" | |
52e12ad0 | 1988 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1989 | |
1990 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
1991 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1992 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
1993 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1994 | "" |
1995 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
1996 | [(set_attr "itanium_class" "ialu")]) |
1997 | ||
1998 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 1999 | |
058557c4 | 2000 | (define_insn "mulsi3" |
0551c32d | 2001 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
2002 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
2003 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2004 | "" |
aebf2462 | 2005 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2006 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 2007 | |
655f2eb9 | 2008 | (define_insn "maddsi4" |
11a13704 RH |
2009 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
2010 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
2011 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
2012 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
2013 | "" | |
aebf2462 | 2014 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2015 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 2016 | |
058557c4 | 2017 | (define_insn "negsi2" |
0551c32d RH |
2018 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2019 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2020 | "" |
2021 | "sub %0 = r0, %1" | |
52e12ad0 | 2022 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2023 | |
2024 | (define_expand "abssi2" | |
2025 | [(set (match_dup 2) | |
f2f90c63 | 2026 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2027 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 2028 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2029 | (neg:SI (match_dup 1)) |
2030 | (match_dup 1)))] | |
c65ebc55 | 2031 | "" |
1d5d7a21 | 2032 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2033 | |
2034 | (define_expand "sminsi3" | |
2035 | [(set (match_dup 3) | |
f2f90c63 | 2036 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2037 | (match_operand:SI 2 "gr_register_operand" ""))) |
2038 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2039 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2040 | (match_dup 2) (match_dup 1)))] |
2041 | "" | |
1d5d7a21 | 2042 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2043 | |
2044 | (define_expand "smaxsi3" | |
2045 | [(set (match_dup 3) | |
f2f90c63 | 2046 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2047 | (match_operand:SI 2 "gr_register_operand" ""))) |
2048 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2049 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2050 | (match_dup 1) (match_dup 2)))] |
2051 | "" | |
1d5d7a21 | 2052 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2053 | |
2054 | (define_expand "uminsi3" | |
2055 | [(set (match_dup 3) | |
f2f90c63 | 2056 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2057 | (match_operand:SI 2 "gr_register_operand" ""))) |
2058 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2059 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2060 | (match_dup 2) (match_dup 1)))] |
2061 | "" | |
1d5d7a21 | 2062 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2063 | |
2064 | (define_expand "umaxsi3" | |
2065 | [(set (match_dup 3) | |
f2f90c63 | 2066 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2067 | (match_operand:SI 2 "gr_register_operand" ""))) |
2068 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2069 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2070 | (match_dup 1) (match_dup 2)))] |
2071 | "" | |
1d5d7a21 | 2072 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 2073 | |
655f2eb9 RH |
2074 | (define_expand "divsi3" |
2075 | [(set (match_operand:SI 0 "register_operand" "") | |
2076 | (div:SI (match_operand:SI 1 "general_operand" "") | |
2077 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2078 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2079 | { |
9aec7fb4 | 2080 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2081 | |
02befdf4 | 2082 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2083 | op0_di = gen_reg_rtx (DImode); |
2084 | ||
2085 | if (CONSTANT_P (operands[1])) | |
2086 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2087 | op1_xf = gen_reg_rtx (XFmode); |
2088 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2089 | |
2090 | if (CONSTANT_P (operands[2])) | |
2091 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2092 | op2_xf = gen_reg_rtx (XFmode); |
2093 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 RH |
2094 | |
2095 | /* 2^-34 */ | |
9aec7fb4 SE |
2096 | twon34_exp = gen_reg_rtx (DImode); |
2097 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2098 | twon34 = gen_reg_rtx (XFmode); | |
2099 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2100 | |
85199961 L |
2101 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2102 | CONST1_RTX (SImode))); | |
2103 | ||
02befdf4 | 2104 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2105 | |
02befdf4 | 2106 | emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2107 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2108 | DONE; | |
1d5d7a21 | 2109 | }) |
655f2eb9 RH |
2110 | |
2111 | (define_expand "modsi3" | |
2112 | [(set (match_operand:SI 0 "register_operand" "") | |
2113 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
2114 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2115 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2116 | { |
2117 | rtx op2_neg, op1_di, div; | |
2118 | ||
2119 | div = gen_reg_rtx (SImode); | |
2120 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
2121 | ||
2122 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2123 | ||
2124 | /* This is a trick to get us to reuse the value that we're sure to | |
2125 | have already copied to the FP regs. */ | |
2126 | op1_di = gen_reg_rtx (DImode); | |
2127 | convert_move (op1_di, operands[1], 0); | |
2128 | ||
2129 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2130 | gen_lowpart (SImode, op1_di))); | |
2131 | DONE; | |
1d5d7a21 | 2132 | }) |
655f2eb9 RH |
2133 | |
2134 | (define_expand "udivsi3" | |
2135 | [(set (match_operand:SI 0 "register_operand" "") | |
2136 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
2137 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2138 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2139 | { |
9aec7fb4 | 2140 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2141 | |
02befdf4 | 2142 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2143 | op0_di = gen_reg_rtx (DImode); |
2144 | ||
2145 | if (CONSTANT_P (operands[1])) | |
2146 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2147 | op1_xf = gen_reg_rtx (XFmode); |
2148 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2149 | |
2150 | if (CONSTANT_P (operands[2])) | |
2151 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2152 | op2_xf = gen_reg_rtx (XFmode); |
2153 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 RH |
2154 | |
2155 | /* 2^-34 */ | |
9aec7fb4 SE |
2156 | twon34_exp = gen_reg_rtx (DImode); |
2157 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2158 | twon34 = gen_reg_rtx (XFmode); | |
2159 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2160 | |
85199961 L |
2161 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2162 | CONST1_RTX (SImode))); | |
2163 | ||
02befdf4 | 2164 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2165 | |
02befdf4 | 2166 | emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2167 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2168 | DONE; | |
1d5d7a21 | 2169 | }) |
655f2eb9 RH |
2170 | |
2171 | (define_expand "umodsi3" | |
2172 | [(set (match_operand:SI 0 "register_operand" "") | |
2173 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
2174 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2175 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2176 | { |
2177 | rtx op2_neg, op1_di, div; | |
2178 | ||
2179 | div = gen_reg_rtx (SImode); | |
2180 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
2181 | ||
2182 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2183 | ||
2184 | /* This is a trick to get us to reuse the value that we're sure to | |
2185 | have already copied to the FP regs. */ | |
2186 | op1_di = gen_reg_rtx (DImode); | |
2187 | convert_move (op1_di, operands[1], 1); | |
2188 | ||
2189 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2190 | gen_lowpart (SImode, op1_di))); | |
2191 | DONE; | |
1d5d7a21 | 2192 | }) |
655f2eb9 RH |
2193 | |
2194 | (define_insn_and_split "divsi3_internal" | |
02befdf4 ZW |
2195 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2196 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2197 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2198 | (clobber (match_scratch:XF 4 "=&f")) | |
2199 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2200 | (clobber (match_scratch:BI 6 "=c")) |
02befdf4 ZW |
2201 | (use (match_operand:XF 3 "fr_register_operand" "f"))] |
2202 | "TARGET_INLINE_INT_DIV" | |
655f2eb9 RH |
2203 | "#" |
2204 | "&& reload_completed" | |
02befdf4 | 2205 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2206 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2207 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2208 | (use (const_int 1))]) |
2209 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2210 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2211 | (use (const_int 1))])) |
2212 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2213 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
2214 | (minus:XF (match_dup 7) |
2215 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2216 | (use (const_int 1))])) |
2217 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2218 | (parallel [(set (match_dup 4) | |
02befdf4 | 2219 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2220 | (match_dup 4))) |
2221 | (use (const_int 1))])) | |
2222 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2223 | (parallel [(set (match_dup 5) | |
02befdf4 | 2224 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
655f2eb9 RH |
2225 | (match_dup 3))) |
2226 | (use (const_int 1))])) | |
2227 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2228 | (parallel [(set (match_dup 0) | |
02befdf4 | 2229 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2230 | (match_dup 4))) |
2231 | (use (const_int 1))])) | |
2232 | ] | |
02befdf4 | 2233 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 | 2234 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2235 | \f |
2236 | ;; :::::::::::::::::::: | |
2237 | ;; :: | |
27a9b99d | 2238 | ;; :: 64-bit Integer arithmetic |
c65ebc55 JW |
2239 | ;; :: |
2240 | ;; :::::::::::::::::::: | |
2241 | ||
2242 | (define_insn "adddi3" | |
0551c32d RH |
2243 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2244 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2245 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2246 | "" |
2247 | "@ | |
1d5d7a21 RH |
2248 | add %0 = %1, %2 |
2249 | adds %0 = %2, %1 | |
2250 | addl %0 = %2, %1" | |
52e12ad0 | 2251 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2252 | |
2253 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2254 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2255 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2256 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2257 | (const_int 1)))] |
2258 | "" | |
2259 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2260 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2261 | |
5527bf14 RH |
2262 | ;; This has some of the same problems as shladd. We let the shladd |
2263 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2264 | ;; a register, but not more ugliness here. | |
2265 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2266 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2267 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2268 | (const_int 2)) |
2269 | (const_int 1)))] | |
2270 | "" | |
2271 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2272 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2273 | |
c65ebc55 | 2274 | (define_insn "subdi3" |
0551c32d RH |
2275 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2276 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2277 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2278 | "" |
2279 | "sub %0 = %1, %2" | |
52e12ad0 | 2280 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2281 | |
2282 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2283 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2284 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2285 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2286 | "" |
2287 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2288 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2289 | |
cee58bc0 RH |
2290 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2291 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2292 | (define_insn "muldi3" |
0551c32d | 2293 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2294 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2295 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2296 | "" |
aebf2462 | 2297 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2298 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2299 | |
2300 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2301 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2302 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2303 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2304 | ;; here so that it will be present just in case register elimination gives us | |
2305 | ;; the funny result. | |
2306 | ||
2307 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2308 | ||
2309 | ;; ??? Maybe we should change how adds are canonicalized. | |
2310 | ||
655f2eb9 | 2311 | (define_insn "madddi4" |
0551c32d | 2312 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2313 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2314 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2315 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2316 | (clobber (match_scratch:DI 4 "=X"))] |
2317 | "" | |
aebf2462 | 2318 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2319 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2320 | |
2321 | ;; This can be created by register elimination if operand3 of shladd is an | |
2322 | ;; eliminable register or has reg_equiv_constant set. | |
2323 | ||
2324 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2325 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2326 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2327 | ;; incorrectly. |
2328 | ||
655f2eb9 | 2329 | (define_insn "*madddi4_elim" |
c65ebc55 | 2330 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2331 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2332 | (match_operand:DI 2 "register_operand" "f")) | |
2333 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2334 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2335 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2336 | "reload_in_progress" |
2337 | "#" | |
52e12ad0 | 2338 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2339 | |
c65ebc55 JW |
2340 | (define_split |
2341 | [(set (match_operand:DI 0 "register_operand" "") | |
2342 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2343 | (match_operand:DI 2 "register_operand" "")) | |
2344 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2345 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2346 | (clobber (match_scratch:DI 5 ""))] |
2347 | "reload_completed" | |
2348 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2349 | (match_dup 3))) | |
2350 | (clobber (match_dup 0))]) | |
c65ebc55 | 2351 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2352 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2353 | "") | |
2354 | ||
c65ebc55 | 2355 | (define_insn "smuldi3_highpart" |
0551c32d | 2356 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2357 | (truncate:DI |
2358 | (lshiftrt:TI | |
0551c32d RH |
2359 | (mult:TI (sign_extend:TI |
2360 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2361 | (sign_extend:TI | |
2362 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2363 | (const_int 64))))] |
2364 | "" | |
aebf2462 | 2365 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2366 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2367 | |
2368 | (define_insn "umuldi3_highpart" | |
0551c32d | 2369 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2370 | (truncate:DI |
2371 | (lshiftrt:TI | |
0551c32d RH |
2372 | (mult:TI (zero_extend:TI |
2373 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2374 | (zero_extend:TI | |
2375 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2376 | (const_int 64))))] |
2377 | "" | |
aebf2462 | 2378 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2379 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2380 | |
2381 | (define_insn "negdi2" | |
0551c32d RH |
2382 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2383 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2384 | "" |
2385 | "sub %0 = r0, %1" | |
52e12ad0 | 2386 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2387 | |
2388 | (define_expand "absdi2" | |
2389 | [(set (match_dup 2) | |
f2f90c63 | 2390 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2391 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2392 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2393 | (neg:DI (match_dup 1)) |
2394 | (match_dup 1)))] | |
c65ebc55 | 2395 | "" |
1d5d7a21 | 2396 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2397 | |
2398 | (define_expand "smindi3" | |
2399 | [(set (match_dup 3) | |
f2f90c63 | 2400 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2401 | (match_operand:DI 2 "gr_register_operand" ""))) |
2402 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2403 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2404 | (match_dup 2) (match_dup 1)))] |
2405 | "" | |
1d5d7a21 | 2406 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2407 | |
2408 | (define_expand "smaxdi3" | |
2409 | [(set (match_dup 3) | |
f2f90c63 | 2410 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2411 | (match_operand:DI 2 "gr_register_operand" ""))) |
2412 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2413 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2414 | (match_dup 1) (match_dup 2)))] |
2415 | "" | |
1d5d7a21 | 2416 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2417 | |
2418 | (define_expand "umindi3" | |
2419 | [(set (match_dup 3) | |
f2f90c63 | 2420 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2421 | (match_operand:DI 2 "gr_register_operand" ""))) |
2422 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2423 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2424 | (match_dup 2) (match_dup 1)))] |
2425 | "" | |
1d5d7a21 | 2426 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2427 | |
2428 | (define_expand "umaxdi3" | |
2429 | [(set (match_dup 3) | |
f2f90c63 | 2430 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2431 | (match_operand:DI 2 "gr_register_operand" ""))) |
2432 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2433 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2434 | (match_dup 1) (match_dup 2)))] |
2435 | "" | |
1d5d7a21 | 2436 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2437 | |
2438 | (define_expand "ffsdi2" | |
2439 | [(set (match_dup 6) | |
f2f90c63 | 2440 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2441 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2442 | (set (match_dup 5) (const_int 0)) | |
2443 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2444 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2445 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2446 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2447 | (match_dup 5) (match_dup 4)))] |
2448 | "" | |
c65ebc55 JW |
2449 | { |
2450 | operands[2] = gen_reg_rtx (DImode); | |
2451 | operands[3] = gen_reg_rtx (DImode); | |
2452 | operands[4] = gen_reg_rtx (DImode); | |
2453 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2454 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2455 | }) |
c65ebc55 | 2456 | |
c407570a RH |
2457 | (define_expand "ctzdi2" |
2458 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2459 | (const_int -1))) | |
2460 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2461 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2462 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2463 | (popcount:DI (match_dup 4)))] | |
2464 | "" | |
2465 | { | |
2466 | operands[2] = gen_reg_rtx (DImode); | |
2467 | operands[3] = gen_reg_rtx (DImode); | |
2468 | operands[4] = gen_reg_rtx (DImode); | |
2469 | }) | |
2470 | ||
c407570a RH |
2471 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2472 | (define_expand "clzdi2" | |
2473 | [(set (match_dup 2) | |
02befdf4 | 2474 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" ""))) |
c407570a RH |
2475 | (set (match_dup 3) |
2476 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2477 | (set (match_dup 4) (const_int 65598)) | |
2478 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2479 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2480 | "" |
c407570a | 2481 | { |
02befdf4 | 2482 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2483 | operands[3] = gen_reg_rtx (DImode); |
2484 | operands[4] = gen_reg_rtx (DImode); | |
2485 | }) | |
2486 | ||
2487 | (define_insn "popcountdi2" | |
0551c32d | 2488 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2489 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2490 | "" |
2491 | "popcnt %0 = %1" | |
52e12ad0 | 2492 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2493 | |
ff848f0e RS |
2494 | (define_insn "bswapdi2" |
2495 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
2496 | (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
2497 | "" | |
2498 | "mux1 %0 = %1, @rev" | |
2499 | [(set_attr "itanium_class" "mmshf")]) | |
2500 | ||
02befdf4 | 2501 | (define_insn "*getf_exp_xf" |
c407570a | 2502 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
02befdf4 | 2503 | (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")] |
c407570a | 2504 | UNSPEC_GETF_EXP))] |
02befdf4 | 2505 | "" |
c407570a RH |
2506 | "getf.exp %0 = %1" |
2507 | [(set_attr "itanium_class" "frfr")]) | |
2508 | ||
655f2eb9 RH |
2509 | (define_expand "divdi3" |
2510 | [(set (match_operand:DI 0 "register_operand" "") | |
2511 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2512 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2513 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2514 | { |
02befdf4 | 2515 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2516 | |
02befdf4 | 2517 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2518 | |
2519 | if (CONSTANT_P (operands[1])) | |
2520 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2521 | op1_xf = gen_reg_rtx (XFmode); |
2522 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2523 | |
2524 | if (CONSTANT_P (operands[2])) | |
2525 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2526 | op2_xf = gen_reg_rtx (XFmode); |
2527 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 | 2528 | |
85199961 L |
2529 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2530 | CONST1_RTX (DImode))); | |
2531 | ||
dbdd120f | 2532 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2533 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2534 | else |
02befdf4 | 2535 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2536 | |
02befdf4 | 2537 | emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2538 | DONE; |
1d5d7a21 | 2539 | }) |
655f2eb9 RH |
2540 | |
2541 | (define_expand "moddi3" | |
2542 | [(set (match_operand:DI 0 "register_operand" "") | |
2543 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2544 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2545 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2546 | { |
2547 | rtx op2_neg, div; | |
2548 | ||
2549 | div = gen_reg_rtx (DImode); | |
2550 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2551 | ||
2552 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2553 | ||
2554 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2555 | DONE; | |
1d5d7a21 | 2556 | }) |
655f2eb9 RH |
2557 | |
2558 | (define_expand "udivdi3" | |
2559 | [(set (match_operand:DI 0 "register_operand" "") | |
2560 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2561 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2562 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2563 | { |
02befdf4 | 2564 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2565 | |
02befdf4 | 2566 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2567 | |
2568 | if (CONSTANT_P (operands[1])) | |
2569 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2570 | op1_xf = gen_reg_rtx (XFmode); |
2571 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2572 | |
2573 | if (CONSTANT_P (operands[2])) | |
2574 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2575 | op2_xf = gen_reg_rtx (XFmode); |
2576 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 | 2577 | |
85199961 L |
2578 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2579 | CONST1_RTX (DImode))); | |
2580 | ||
dbdd120f | 2581 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2582 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2583 | else |
02befdf4 | 2584 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2585 | |
02befdf4 | 2586 | emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2587 | DONE; |
1d5d7a21 | 2588 | }) |
655f2eb9 RH |
2589 | |
2590 | (define_expand "umoddi3" | |
2591 | [(set (match_operand:DI 0 "register_operand" "") | |
2592 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2593 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2594 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2595 | { |
2596 | rtx op2_neg, div; | |
2597 | ||
2598 | div = gen_reg_rtx (DImode); | |
2599 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2600 | ||
2601 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2602 | ||
2603 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2604 | DONE; | |
1d5d7a21 | 2605 | }) |
655f2eb9 RH |
2606 | |
2607 | (define_insn_and_split "divdi3_internal_lat" | |
02befdf4 ZW |
2608 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2609 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2610 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2611 | (clobber (match_scratch:XF 3 "=&f")) | |
2612 | (clobber (match_scratch:XF 4 "=&f")) | |
2613 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2614 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 2615 | "TARGET_INLINE_INT_DIV == INL_MIN_LAT" |
655f2eb9 RH |
2616 | "#" |
2617 | "&& reload_completed" | |
02befdf4 | 2618 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2619 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2620 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2621 | (use (const_int 1))]) |
2622 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2623 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2624 | (minus:XF (match_dup 7) |
2625 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2626 | (use (const_int 1))])) |
2627 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2628 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2629 | (use (const_int 1))])) |
2630 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2631 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2632 | (use (const_int 1))])) |
2633 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2634 | (parallel [(set (match_dup 4) | |
02befdf4 | 2635 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
655f2eb9 RH |
2636 | (match_dup 4))) |
2637 | (use (const_int 1))])) | |
2638 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2639 | (parallel [(set (match_dup 0) | |
02befdf4 | 2640 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2641 | (match_dup 0))) |
2642 | (use (const_int 1))])) | |
2643 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2644 | (parallel [(set (match_dup 3) | |
02befdf4 | 2645 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2646 | (match_dup 4))) |
2647 | (use (const_int 1))])) | |
2648 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2649 | (parallel [(set (match_dup 0) | |
02befdf4 | 2650 | (plus:XF (mult:XF (match_dup 5) (match_dup 0)) |
655f2eb9 RH |
2651 | (match_dup 0))) |
2652 | (use (const_int 1))])) | |
2653 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2654 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2655 | (minus:XF (match_dup 1) |
2656 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2657 | (use (const_int 1))])) |
2658 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2659 | (parallel [(set (match_dup 0) | |
02befdf4 | 2660 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2661 | (match_dup 3))) |
2662 | (use (const_int 1))])) | |
2663 | ] | |
02befdf4 | 2664 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 RH |
2665 | [(set_attr "predicable" "no")]) |
2666 | ||
2667 | (define_insn_and_split "divdi3_internal_thr" | |
02befdf4 ZW |
2668 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2669 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2670 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2671 | (clobber (match_scratch:XF 3 "=&f")) | |
2672 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2673 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2674 | "TARGET_INLINE_INT_DIV == INL_MAX_THR" |
655f2eb9 RH |
2675 | "#" |
2676 | "&& reload_completed" | |
02befdf4 | 2677 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2678 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2679 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2680 | (use (const_int 1))]) |
2681 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2682 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2683 | (minus:XF (match_dup 6) |
2684 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2685 | (use (const_int 1))])) |
2686 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2687 | (parallel [(set (match_dup 0) | |
02befdf4 | 2688 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2689 | (match_dup 0))) |
2690 | (use (const_int 1))])) | |
2691 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2692 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2693 | (use (const_int 1))])) |
2694 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2695 | (parallel [(set (match_dup 0) | |
02befdf4 | 2696 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2697 | (match_dup 0))) |
2698 | (use (const_int 1))])) | |
2699 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2700 | (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1))) |
655f2eb9 RH |
2701 | (use (const_int 1))])) |
2702 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2703 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2704 | (minus:XF (match_dup 1) |
2705 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2706 | (use (const_int 1))])) |
2707 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2708 | (parallel [(set (match_dup 0) | |
02befdf4 | 2709 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2710 | (match_dup 3))) |
2711 | (use (const_int 1))])) | |
2712 | ] | |
02befdf4 | 2713 | "operands[6] = CONST1_RTX (XFmode);" |
655f2eb9 | 2714 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2715 | \f |
2716 | ;; :::::::::::::::::::: | |
2717 | ;; :: | |
27a9b99d | 2718 | ;; :: 128-bit Integer arithmetic |
a71aef0b JB |
2719 | ;; :: |
2720 | ;; :::::::::::::::::::: | |
2721 | ||
2722 | (define_insn "addti3" | |
2723 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2724 | (plus:TI (match_operand:TI 1 "gr_register_operand" "%r") | |
2725 | (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI"))) | |
2726 | (clobber (match_scratch:BI 3 "=&c"))] | |
2727 | "" | |
2728 | "#" | |
2729 | [(set_attr "itanium_class" "unknown")]) | |
2730 | ||
2731 | (define_split | |
2732 | [(set (match_operand:TI 0 "register_operand" "") | |
2733 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2734 | (match_operand:TI 2 "register_operand" ""))) | |
2735 | (clobber (match_scratch:BI 3 ""))] | |
2736 | "reload_completed" | |
2737 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2738 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2739 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2740 | (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6)))) | |
2741 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2742 | (set (match_dup 4) | |
2743 | (plus:DI (plus:DI (match_dup 5) (match_dup 6)) | |
2744 | (const_int 1))))] | |
2745 | { | |
2746 | operands[4] = gen_highpart (DImode, operands[0]); | |
2747 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2748 | operands[5] = gen_highpart (DImode, operands[1]); | |
2749 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2750 | operands[6] = gen_highpart (DImode, operands[2]); | |
2751 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2752 | }) | |
2753 | ||
2754 | (define_split | |
2755 | [(set (match_operand:TI 0 "register_operand" "") | |
2756 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2757 | (match_operand:TI 2 "immediate_operand" ""))) | |
2758 | (clobber (match_scratch:BI 3 ""))] | |
2759 | "reload_completed" | |
2760 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2761 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2762 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2763 | (set (match_dup 4) | |
2764 | (plus:DI (match_dup 5) (match_dup 6)))) | |
2765 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2766 | (set (match_dup 4) | |
2767 | (plus:DI (match_dup 5) (match_dup 7))))] | |
2768 | { | |
2769 | operands[4] = gen_highpart (DImode, operands[0]); | |
2770 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2771 | operands[5] = gen_highpart (DImode, operands[1]); | |
2772 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2773 | operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx; | |
2774 | operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx; | |
2775 | }) | |
2776 | ||
2777 | (define_insn "subti3" | |
2778 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2779 | (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK") | |
2780 | (match_operand:TI 2 "gr_register_operand" "r"))) | |
2781 | (clobber (match_scratch:BI 3 "=&c"))] | |
2782 | "" | |
2783 | "#" | |
2784 | [(set_attr "itanium_class" "unknown")]) | |
2785 | ||
2786 | (define_split | |
2787 | [(set (match_operand:TI 0 "register_operand" "") | |
2788 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
2789 | (match_operand:TI 2 "register_operand" ""))) | |
2790 | (clobber (match_scratch:BI 3 "=&c"))] | |
2791 | "reload_completed" | |
2792 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) | |
2793 | (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0))) | |
2794 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2795 | (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6)))) | |
2796 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2797 | (set (match_dup 4) | |
2798 | (plus:DI (not:DI (match_dup 6)) (match_dup 5))))] | |
2799 | { | |
2800 | operands[4] = gen_highpart (DImode, operands[0]); | |
2801 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2802 | operands[5] = gen_highpart (DImode, operands[1]); | |
2803 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2804 | operands[6] = gen_highpart (DImode, operands[2]); | |
2805 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2806 | }) | |
2807 | ||
2808 | (define_split | |
2809 | [(set (match_operand:TI 0 "register_operand" "") | |
2810 | (minus:TI (match_operand:TI 1 "immediate_operand" "") | |
2811 | (match_operand:TI 2 "register_operand" ""))) | |
2812 | (clobber (match_scratch:BI 3 "=&c"))] | |
13f70342 | 2813 | "reload_completed && satisfies_constraint_K (operands[1])" |
a71aef0b JB |
2814 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) |
2815 | (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1))) | |
2816 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2817 | (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5)))) | |
2818 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2819 | (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))] | |
2820 | { | |
2821 | operands[4] = gen_highpart (DImode, operands[0]); | |
2822 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2823 | operands[5] = gen_highpart (DImode, operands[2]); | |
2824 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2825 | operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx; | |
2826 | operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; | |
2827 | }) | |
2828 | ||
2829 | (define_expand "mulditi3" | |
2830 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2831 | (mult:TI (sign_extend:TI | |
2832 | (match_operand:DI 1 "fr_register_operand" "")) | |
2833 | (sign_extend:TI | |
2834 | (match_operand:DI 2 "fr_register_operand" ""))))] | |
2835 | "" | |
2836 | "") | |
2837 | ||
2838 | (define_insn_and_split "*mulditi3_internal" | |
2839 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2840 | (mult:TI (sign_extend:TI | |
2841 | (match_operand:DI 1 "fr_register_operand" "%f")) | |
2842 | (sign_extend:TI | |
2843 | (match_operand:DI 2 "fr_register_operand" "f"))))] | |
2844 | "" | |
2845 | "#" | |
2846 | "reload_completed" | |
2847 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2848 | (set (match_dup 3) (truncate:DI | |
2849 | (lshiftrt:TI | |
2850 | (mult:TI (sign_extend:TI (match_dup 1)) | |
2851 | (sign_extend:TI (match_dup 2))) | |
2852 | (const_int 64))))] | |
2853 | { | |
2854 | operands[3] = gen_highpart (DImode, operands[0]); | |
2855 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2856 | } | |
2857 | [(set_attr "itanium_class" "unknown")]) | |
2858 | ||
2859 | (define_expand "umulditi3" | |
2860 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2861 | (mult:TI (zero_extend:TI | |
2862 | (match_operand:DI 1 "fr_register_operand" "")) | |
2863 | (zero_extend:TI | |
2864 | (match_operand:DI 2 "fr_register_operand" ""))))] | |
2865 | "" | |
2866 | "") | |
2867 | ||
2868 | (define_insn_and_split "*umulditi3_internal" | |
2869 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2870 | (mult:TI (zero_extend:TI | |
2871 | (match_operand:DI 1 "fr_register_operand" "%f")) | |
2872 | (zero_extend:TI | |
2873 | (match_operand:DI 2 "fr_register_operand" "f"))))] | |
2874 | "" | |
2875 | "#" | |
2876 | "reload_completed" | |
2877 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2878 | (set (match_dup 3) (truncate:DI | |
2879 | (lshiftrt:TI | |
2880 | (mult:TI (zero_extend:TI (match_dup 1)) | |
2881 | (zero_extend:TI (match_dup 2))) | |
2882 | (const_int 64))))] | |
2883 | { | |
2884 | operands[3] = gen_highpart (DImode, operands[0]); | |
2885 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2886 | } | |
2887 | [(set_attr "itanium_class" "unknown")]) | |
2888 | ||
2889 | (define_insn_and_split "negti2" | |
2890 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2891 | (neg:TI (match_operand:TI 1 "gr_register_operand" "r"))) | |
2892 | (clobber (match_scratch:BI 2 "=&c"))] | |
2893 | "" | |
2894 | "#" | |
2895 | "reload_completed" | |
2896 | [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0))) | |
2897 | (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1))) | |
2898 | (cond_exec (eq (match_dup 2) (const_int 0)) | |
2899 | (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4)))) | |
2900 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
2901 | (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))] | |
2902 | { | |
2903 | operands[3] = gen_highpart (DImode, operands[0]); | |
2904 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2905 | operands[4] = gen_highpart (DImode, operands[1]); | |
2906 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2907 | } | |
2908 | [(set_attr "itanium_class" "unknown")]) | |
2909 | \f | |
2910 | ;; :::::::::::::::::::: | |
2911 | ;; :: | |
27a9b99d | 2912 | ;; :: 32-bit floating point arithmetic |
c65ebc55 JW |
2913 | ;; :: |
2914 | ;; :::::::::::::::::::: | |
2915 | ||
2916 | (define_insn "addsf3" | |
0551c32d RH |
2917 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2918 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2919 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2920 | "" |
aebf2462 | 2921 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2922 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2923 | |
2924 | (define_insn "subsf3" | |
0551c32d RH |
2925 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2926 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2927 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2928 | "" |
aebf2462 | 2929 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2930 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2931 | |
2932 | (define_insn "mulsf3" | |
0551c32d RH |
2933 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2934 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2935 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2936 | "" |
aebf2462 | 2937 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2938 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2939 | |
2940 | (define_insn "abssf2" | |
0551c32d RH |
2941 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2942 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2943 | "" |
aebf2462 | 2944 | "fabs %0 = %1" |
52e12ad0 | 2945 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2946 | |
2947 | (define_insn "negsf2" | |
0551c32d RH |
2948 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2949 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2950 | "" |
aebf2462 | 2951 | "fneg %0 = %1" |
52e12ad0 | 2952 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2953 | |
2954 | (define_insn "*nabssf2" | |
0551c32d RH |
2955 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2956 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2957 | "" |
aebf2462 | 2958 | "fnegabs %0 = %1" |
52e12ad0 | 2959 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2960 | |
046625fa RH |
2961 | (define_insn "copysignsf3" |
2962 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2963 | (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2964 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2965 | UNSPEC_COPYSIGN))] | |
2966 | "" | |
2967 | "fmerge.s %0 = %F2, %F1" | |
2968 | [(set_attr "itanium_class" "fmisc")]) | |
2969 | ||
2970 | (define_insn "*ncopysignsf3" | |
2971 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2972 | (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2973 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2974 | UNSPEC_COPYSIGN)))] | |
2975 | "" | |
2976 | "fmerge.ns %0 = %F2, %F1" | |
2977 | [(set_attr "itanium_class" "fmisc")]) | |
2978 | ||
7ae4d8d4 | 2979 | (define_insn "sminsf3" |
0551c32d RH |
2980 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2981 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2982 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2983 | "" |
aebf2462 | 2984 | "fmin %0 = %1, %F2" |
52e12ad0 | 2985 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2986 | |
7ae4d8d4 | 2987 | (define_insn "smaxsf3" |
0551c32d RH |
2988 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2989 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2990 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2991 | "" |
aebf2462 | 2992 | "fmax %0 = %1, %F2" |
52e12ad0 | 2993 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2994 | |
655f2eb9 | 2995 | (define_insn "*maddsf4" |
0551c32d RH |
2996 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2997 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2998 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2999 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3000 | "" |
aebf2462 | 3001 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 3002 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3003 | |
655f2eb9 | 3004 | (define_insn "*msubsf4" |
0551c32d RH |
3005 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3006 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3007 | (match_operand:SF 2 "fr_register_operand" "f")) | |
3008 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3009 | "" |
aebf2462 | 3010 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 3011 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3012 | |
3013 | (define_insn "*nmulsf3" | |
0551c32d RH |
3014 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3015 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3016 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3017 | "" |
aebf2462 | 3018 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 3019 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3020 | |
655f2eb9 | 3021 | (define_insn "*nmaddsf4" |
0551c32d | 3022 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
3023 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") |
3024 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3025 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3026 | "" |
aebf2462 | 3027 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 3028 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3029 | |
52ad4d7b ZW |
3030 | (define_insn "*nmaddsf4_alts" |
3031 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3032 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") | |
3033 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3034 | (match_operand:SF 2 "fr_register_operand" "f")))) | |
3035 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3036 | "" | |
3037 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
3038 | [(set_attr "itanium_class" "fmac")]) | |
3039 | ||
26102535 RH |
3040 | (define_expand "divsf3" |
3041 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
3042 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
3043 | (match_operand:SF 2 "fr_register_operand" "")))] | |
02befdf4 | 3044 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3045 | { |
3046 | rtx insn; | |
dbdd120f | 3047 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3048 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); |
3049 | else | |
3050 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
3051 | emit_insn (insn); | |
3052 | DONE; | |
1d5d7a21 | 3053 | }) |
26102535 RH |
3054 | |
3055 | (define_insn_and_split "divsf3_internal_lat" | |
3056 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3057 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3058 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
3059 | (clobber (match_scratch:XF 3 "=&f")) |
3060 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 3061 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 3062 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
3063 | "#" |
3064 | "&& reload_completed" | |
02befdf4 | 3065 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
3066 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3067 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3068 | (use (const_int 0))]) |
26102535 | 3069 | (cond_exec (ne (match_dup 5) (const_int 0)) |
02befdf4 | 3070 | (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6))) |
26102535 RH |
3071 | (use (const_int 1))])) |
3072 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3073 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3074 | (minus:XF (match_dup 10) |
3075 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
3076 | (use (const_int 1))])) |
3077 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3078 | (parallel [(set (match_dup 3) | |
02befdf4 | 3079 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3080 | (match_dup 3))) |
3081 | (use (const_int 1))])) | |
3082 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 3083 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3084 | (use (const_int 1))])) |
3085 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3086 | (parallel [(set (match_dup 3) | |
02befdf4 | 3087 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3088 | (match_dup 3))) |
3089 | (use (const_int 1))])) | |
3090 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 3091 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3092 | (use (const_int 1))])) |
3093 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3094 | (parallel [(set (match_dup 9) | |
3095 | (float_truncate:DF | |
02befdf4 | 3096 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3097 | (match_dup 3)))) |
3098 | (use (const_int 1))])) | |
3099 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3100 | (set (match_dup 0) | |
3101 | (float_truncate:SF (match_dup 6)))) | |
3102 | ] | |
1d5d7a21 | 3103 | { |
02befdf4 ZW |
3104 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3105 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3106 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 3107 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); |
02befdf4 | 3108 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 3109 | } |
26102535 RH |
3110 | [(set_attr "predicable" "no")]) |
3111 | ||
3112 | (define_insn_and_split "divsf3_internal_thr" | |
3113 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3114 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3115 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
3116 | (clobber (match_scratch:XF 3 "=&f")) |
3117 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 3118 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 3119 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
3120 | "#" |
3121 | "&& reload_completed" | |
02befdf4 | 3122 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
3123 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3124 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3125 | (use (const_int 0))]) |
26102535 RH |
3126 | (cond_exec (ne (match_dup 5) (const_int 0)) |
3127 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
3128 | (minus:XF (match_dup 10) |
3129 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
3130 | (use (const_int 1))])) |
3131 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3132 | (parallel [(set (match_dup 3) | |
02befdf4 | 3133 | (plus:XF (mult:XF (match_dup 3) (match_dup 3)) |
26102535 RH |
3134 | (match_dup 3))) |
3135 | (use (const_int 1))])) | |
3136 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3137 | (parallel [(set (match_dup 6) | |
02befdf4 | 3138 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3139 | (match_dup 6))) |
3140 | (use (const_int 1))])) | |
3141 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3142 | (parallel [(set (match_dup 9) | |
3143 | (float_truncate:SF | |
02befdf4 | 3144 | (mult:XF (match_dup 7) (match_dup 6)))) |
26102535 RH |
3145 | (use (const_int 1))])) |
3146 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3147 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3148 | (minus:XF (match_dup 7) |
3149 | (mult:XF (match_dup 8) (match_dup 3)))) | |
26102535 RH |
3150 | (use (const_int 1))])) |
3151 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3152 | (set (match_dup 0) | |
3153 | (float_truncate:SF | |
02befdf4 | 3154 | (plus:XF (mult:XF (match_dup 4) (match_dup 6)) |
26102535 RH |
3155 | (match_dup 3))))) |
3156 | ] | |
1d5d7a21 | 3157 | { |
02befdf4 ZW |
3158 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3159 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3160 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 3161 | operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); |
02befdf4 | 3162 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 3163 | } |
26102535 | 3164 | [(set_attr "predicable" "no")]) |
b38ba463 ZW |
3165 | |
3166 | ;; Inline square root. | |
3167 | ||
3168 | (define_insn "*sqrt_approx" | |
3169 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3170 | (div:XF (const_int 1) | |
3171 | (sqrt:XF (match_operand:XF 2 "fr_register_operand" "f")))) | |
3172 | (set (match_operand:BI 1 "register_operand" "=c") | |
3173 | (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3174 | (use (match_operand:SI 3 "const_int_operand" "")) ] | |
3175 | "" | |
3176 | "frsqrta.s%3 %0, %1 = %2" | |
3177 | [(set_attr "itanium_class" "fmisc") | |
3178 | (set_attr "predicable" "no")]) | |
3179 | ||
9aec7fb4 | 3180 | (define_insn "setf_exp_xf" |
b38ba463 ZW |
3181 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3182 | (unspec:XF [(match_operand:DI 1 "register_operand" "r")] | |
3183 | UNSPEC_SETF_EXP))] | |
3184 | "" | |
3185 | "setf.exp %0 = %1" | |
3186 | [(set_attr "itanium_class" "frfr")]) | |
3187 | ||
3188 | (define_expand "sqrtsf2" | |
3189 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3190 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
3191 | "TARGET_INLINE_SQRT" | |
3192 | { | |
3193 | rtx insn; | |
b38ba463 | 3194 | #if 0 |
e820471b | 3195 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3196 | insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]); |
e820471b | 3197 | else |
b38ba463 | 3198 | #else |
e820471b | 3199 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3200 | #endif |
e820471b | 3201 | insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3202 | emit_insn (insn); |
3203 | DONE; | |
3204 | }) | |
3205 | ||
3206 | ;; Latency-optimized square root. | |
3207 | ;; FIXME: Implement. | |
3208 | ||
3209 | ;; Throughput-optimized square root. | |
3210 | ||
3211 | (define_insn_and_split "sqrtsf2_internal_thr" | |
3212 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3213 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f"))) | |
3214 | ;; Register r2 in optimization guide. | |
3215 | (clobber (match_scratch:DI 2 "=r")) | |
3216 | ;; Register f8 in optimization guide | |
3217 | (clobber (match_scratch:XF 3 "=&f")) | |
3218 | ;; Register f9 in optimization guide | |
3219 | (clobber (match_scratch:XF 4 "=&f")) | |
3220 | ;; Register f10 in optimization guide | |
3221 | (clobber (match_scratch:XF 5 "=&f")) | |
3222 | ;; Register p6 in optimization guide. | |
3223 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3224 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3225 | "#" |
3226 | "&& reload_completed" | |
3227 | [ ;; exponent of +1/2 in r2 | |
3228 | (set (match_dup 2) (const_int 65534)) | |
3229 | ;; +1/2 in f8 | |
3230 | (set (match_dup 3) | |
3231 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3232 | ;; Step 1 | |
3233 | ;; y0 = 1/sqrt(a) in f7 | |
3234 | (parallel [(set (match_dup 7) | |
3235 | (div:XF (const_int 1) | |
3236 | (sqrt:XF (match_dup 8)))) | |
3237 | (set (match_dup 6) | |
3238 | (unspec:BI [(match_dup 8)] | |
3239 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3240 | (use (const_int 0))]) | |
3241 | ;; Step 2 | |
3242 | ;; H0 = 1/2 * y0 in f9 | |
3243 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3244 | (parallel [(set (match_dup 4) | |
3245 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3246 | (match_dup 9))) | |
3247 | (use (const_int 1))])) | |
3248 | ;; Step 3 | |
3249 | ;; S0 = a * y0 in f7 | |
3250 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3251 | (parallel [(set (match_dup 7) | |
3252 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3253 | (match_dup 9))) | |
3254 | (use (const_int 1))])) | |
3255 | ;; Step 4 | |
3256 | ;; d = 1/2 - S0 * H0 in f10 | |
3257 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3258 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
3259 | (minus:XF (match_dup 3) |
3260 | (mult:XF (match_dup 7) (match_dup 4)))) | |
b38ba463 ZW |
3261 | (use (const_int 1))])) |
3262 | ;; Step 5 | |
3263 | ;; d' = d + 1/2 * d in f8 | |
3264 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3265 | (parallel [(set (match_dup 3) | |
3266 | (plus:XF (mult:XF (match_dup 3) (match_dup 5)) | |
3267 | (match_dup 5))) | |
3268 | (use (const_int 1))])) | |
3269 | ;; Step 6 | |
3270 | ;; e = d + d * d' in f8 | |
3271 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3272 | (parallel [(set (match_dup 3) | |
3273 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) | |
3274 | (match_dup 5))) | |
3275 | (use (const_int 1))])) | |
3276 | ;; Step 7 | |
3277 | ;; S1 = S0 + e * S0 in f7 | |
3278 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3279 | (parallel [(set (match_dup 0) | |
3280 | (float_truncate:SF | |
3281 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3282 | (match_dup 7)))) | |
3283 | (use (const_int 1))])) | |
3284 | ;; Step 8 | |
3285 | ;; H1 = H0 + e * H0 in f8 | |
3286 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3287 | (parallel [(set (match_dup 3) | |
3288 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
3289 | (match_dup 4))) | |
3290 | (use (const_int 1))])) | |
3291 | ;; Step 9 | |
3292 | ;; d1 = a - S1 * S1 in f9 | |
3293 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3294 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3295 | (minus:XF (match_dup 8) |
3296 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3297 | (use (const_int 1))])) |
3298 | ;; Step 10 | |
3299 | ;; S = S1 + d1 * H1 in f7 | |
3300 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3301 | (parallel [(set (match_dup 0) | |
3302 | (float_truncate:SF | |
3303 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3304 | (match_dup 7)))) | |
3305 | (use (const_int 0))]))] | |
3306 | { | |
3307 | /* Generate 82-bit versions of the input and output operands. */ | |
3308 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3309 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3310 | /* Generate required floating-point constants. */ | |
3311 | operands[9] = CONST0_RTX (XFmode); | |
3312 | } | |
3313 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
3314 | \f |
3315 | ;; :::::::::::::::::::: | |
3316 | ;; :: | |
27a9b99d | 3317 | ;; :: 64-bit floating point arithmetic |
c65ebc55 JW |
3318 | ;; :: |
3319 | ;; :::::::::::::::::::: | |
3320 | ||
3321 | (define_insn "adddf3" | |
0551c32d RH |
3322 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3323 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3324 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3325 | "" |
aebf2462 | 3326 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 3327 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3328 | |
26102535 RH |
3329 | (define_insn "*adddf3_trunc" |
3330 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3331 | (float_truncate:SF | |
3332 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3333 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3334 | "" | |
aebf2462 | 3335 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 3336 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3337 | |
c65ebc55 | 3338 | (define_insn "subdf3" |
0551c32d RH |
3339 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3340 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3341 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3342 | "" |
aebf2462 | 3343 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3344 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3345 | |
26102535 RH |
3346 | (define_insn "*subdf3_trunc" |
3347 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3348 | (float_truncate:SF | |
3349 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3350 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3351 | "" | |
aebf2462 | 3352 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3353 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3354 | |
c65ebc55 | 3355 | (define_insn "muldf3" |
0551c32d RH |
3356 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3357 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3358 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 3359 | "" |
aebf2462 | 3360 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 3361 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3362 | |
26102535 RH |
3363 | (define_insn "*muldf3_trunc" |
3364 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3365 | (float_truncate:SF | |
3366 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3367 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
3368 | "" | |
aebf2462 | 3369 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 3370 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3371 | |
c65ebc55 | 3372 | (define_insn "absdf2" |
0551c32d RH |
3373 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3374 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3375 | "" |
aebf2462 | 3376 | "fabs %0 = %1" |
52e12ad0 | 3377 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3378 | |
3379 | (define_insn "negdf2" | |
0551c32d RH |
3380 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3381 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3382 | "" |
aebf2462 | 3383 | "fneg %0 = %1" |
52e12ad0 | 3384 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3385 | |
3386 | (define_insn "*nabsdf2" | |
0551c32d RH |
3387 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3388 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 3389 | "" |
aebf2462 | 3390 | "fnegabs %0 = %1" |
52e12ad0 | 3391 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3392 | |
046625fa RH |
3393 | (define_insn "copysigndf3" |
3394 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3395 | (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3396 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3397 | UNSPEC_COPYSIGN))] | |
3398 | "" | |
3399 | "fmerge.s %0 = %F2, %F1" | |
3400 | [(set_attr "itanium_class" "fmisc")]) | |
3401 | ||
3402 | (define_insn "*ncopysigndf3" | |
3403 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3404 | (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3405 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3406 | UNSPEC_COPYSIGN)))] | |
3407 | "" | |
3408 | "fmerge.ns %0 = %F2, %F1" | |
3409 | [(set_attr "itanium_class" "fmisc")]) | |
3410 | ||
7ae4d8d4 | 3411 | (define_insn "smindf3" |
0551c32d RH |
3412 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3413 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3414 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3415 | "" |
aebf2462 | 3416 | "fmin %0 = %1, %F2" |
52e12ad0 | 3417 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3418 | |
7ae4d8d4 | 3419 | (define_insn "smaxdf3" |
0551c32d RH |
3420 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3421 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3422 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3423 | "" |
aebf2462 | 3424 | "fmax %0 = %1, %F2" |
52e12ad0 | 3425 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3426 | |
655f2eb9 | 3427 | (define_insn "*madddf4" |
0551c32d RH |
3428 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3429 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3430 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3431 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3432 | "" |
aebf2462 | 3433 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 3434 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3435 | |
26102535 RH |
3436 | (define_insn "*madddf4_trunc" |
3437 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3438 | (float_truncate:SF | |
3439 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3440 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3441 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3442 | "" | |
aebf2462 | 3443 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 3444 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3445 | |
655f2eb9 | 3446 | (define_insn "*msubdf4" |
0551c32d RH |
3447 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3448 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3449 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3450 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3451 | "" |
aebf2462 | 3452 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 3453 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3454 | |
26102535 RH |
3455 | (define_insn "*msubdf4_trunc" |
3456 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3457 | (float_truncate:SF | |
3458 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3459 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3460 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3461 | "" | |
aebf2462 | 3462 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 3463 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3464 | |
c65ebc55 | 3465 | (define_insn "*nmuldf3" |
0551c32d RH |
3466 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3467 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3468 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3469 | "" |
aebf2462 | 3470 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 3471 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3472 | |
26102535 RH |
3473 | (define_insn "*nmuldf3_trunc" |
3474 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3475 | (float_truncate:SF | |
3476 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3477 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
3478 | "" | |
aebf2462 | 3479 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 3480 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3481 | |
655f2eb9 | 3482 | (define_insn "*nmadddf4" |
0551c32d | 3483 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
3484 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3485 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3486 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3487 | "" |
aebf2462 | 3488 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 3489 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3490 | |
3491 | (define_insn "*nmadddf4_alts" | |
3492 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3493 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3494 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3495 | (match_operand:DF 2 "fr_register_operand" "f")))) | |
26102535 RH |
3496 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3497 | "" | |
aebf2462 | 3498 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 3499 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3500 | |
52ad4d7b | 3501 | (define_insn "*nmadddf4_truncsf" |
26102535 RH |
3502 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3503 | (float_truncate:SF | |
52ad4d7b ZW |
3504 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3505 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3506 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
26102535 | 3507 | "" |
aebf2462 | 3508 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 3509 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3510 | |
52ad4d7b ZW |
3511 | (define_insn "*nmadddf4_truncsf_alts" |
3512 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3513 | (float_truncate:SF | |
3514 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") | |
3515 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3516 | (match_operand:DF 2 "fr_register_operand" "f"))))) | |
3517 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3518 | "" | |
3519 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
3520 | [(set_attr "itanium_class" "fmac")]) | |
3521 | ||
26102535 RH |
3522 | (define_expand "divdf3" |
3523 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
3524 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
3525 | (match_operand:DF 2 "fr_register_operand" "")))] | |
02befdf4 | 3526 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3527 | { |
3528 | rtx insn; | |
dbdd120f | 3529 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3530 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); |
3531 | else | |
3532 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
3533 | emit_insn (insn); | |
3534 | DONE; | |
1d5d7a21 | 3535 | }) |
26102535 RH |
3536 | |
3537 | (define_insn_and_split "divdf3_internal_lat" | |
3538 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3539 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3540 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
3541 | (clobber (match_scratch:XF 3 "=&f")) |
3542 | (clobber (match_scratch:XF 4 "=&f")) | |
3543 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 3544 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 3545 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
3546 | "#" |
3547 | "&& reload_completed" | |
02befdf4 | 3548 | [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9))) |
086c0f96 RH |
3549 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] |
3550 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3551 | (use (const_int 0))]) |
26102535 | 3552 | (cond_exec (ne (match_dup 6) (const_int 0)) |
02befdf4 | 3553 | (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7))) |
26102535 RH |
3554 | (use (const_int 1))])) |
3555 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3556 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3557 | (minus:XF (match_dup 12) |
3558 | (mult:XF (match_dup 9) (match_dup 7)))) | |
26102535 RH |
3559 | (use (const_int 1))])) |
3560 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3561 | (parallel [(set (match_dup 3) | |
02befdf4 | 3562 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3563 | (match_dup 3))) |
3564 | (use (const_int 1))])) | |
3565 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3566 | (parallel [(set (match_dup 5) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3567 | (use (const_int 1))])) |
3568 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3569 | (parallel [(set (match_dup 7) | |
02befdf4 | 3570 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3571 | (match_dup 7))) |
3572 | (use (const_int 1))])) | |
3573 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3574 | (parallel [(set (match_dup 3) | |
02befdf4 | 3575 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
3576 | (match_dup 3))) |
3577 | (use (const_int 1))])) | |
3578 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3579 | (parallel [(set (match_dup 4) (mult:XF (match_dup 5) (match_dup 5))) |
26102535 RH |
3580 | (use (const_int 1))])) |
3581 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3582 | (parallel [(set (match_dup 7) | |
02befdf4 | 3583 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3584 | (match_dup 7))) |
3585 | (use (const_int 1))])) | |
3586 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3587 | (parallel [(set (match_dup 10) | |
3588 | (float_truncate:DF | |
02befdf4 | 3589 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3590 | (match_dup 3)))) |
3591 | (use (const_int 1))])) | |
3592 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3593 | (parallel [(set (match_dup 7) | |
02befdf4 | 3594 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3595 | (match_dup 7))) |
3596 | (use (const_int 1))])) | |
3597 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3598 | (parallel [(set (match_dup 11) | |
3599 | (float_truncate:DF | |
52ad4d7b ZW |
3600 | (minus:XF (match_dup 8) |
3601 | (mult:XF (match_dup 9) (match_dup 3))))) | |
26102535 RH |
3602 | (use (const_int 1))])) |
3603 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3604 | (set (match_dup 0) | |
02befdf4 | 3605 | (float_truncate:DF (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3606 | (match_dup 3))))) |
3607 | ] | |
1d5d7a21 | 3608 | { |
02befdf4 ZW |
3609 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3610 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3611 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 RH |
3612 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); |
3613 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
02befdf4 | 3614 | operands[12] = CONST1_RTX (XFmode); |
1d5d7a21 | 3615 | } |
26102535 RH |
3616 | [(set_attr "predicable" "no")]) |
3617 | ||
3618 | (define_insn_and_split "divdf3_internal_thr" | |
3619 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3620 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3621 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
02befdf4 | 3622 | (clobber (match_scratch:XF 3 "=&f")) |
26102535 | 3623 | (clobber (match_scratch:DF 4 "=f")) |
f2f90c63 | 3624 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 3625 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
3626 | "#" |
3627 | "&& reload_completed" | |
02befdf4 | 3628 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
3629 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3630 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3631 | (use (const_int 0))]) |
26102535 RH |
3632 | (cond_exec (ne (match_dup 5) (const_int 0)) |
3633 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
3634 | (minus:XF (match_dup 10) |
3635 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
3636 | (use (const_int 1))])) |
3637 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3638 | (parallel [(set (match_dup 6) | |
02befdf4 | 3639 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3640 | (match_dup 6))) |
3641 | (use (const_int 1))])) | |
3642 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3643 | (parallel [(set (match_dup 3) | |
02befdf4 | 3644 | (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3645 | (use (const_int 1))])) |
3646 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3647 | (parallel [(set (match_dup 6) | |
02befdf4 | 3648 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3649 | (match_dup 6))) |
3650 | (use (const_int 1))])) | |
3651 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3652 | (parallel [(set (match_dup 3) | |
02befdf4 | 3653 | (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3654 | (use (const_int 1))])) |
3655 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3656 | (parallel [(set (match_dup 6) | |
02befdf4 | 3657 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3658 | (match_dup 6))) |
3659 | (use (const_int 1))])) | |
3660 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3661 | (parallel [(set (match_dup 9) | |
3662 | (float_truncate:DF | |
aa42f99d | 3663 | (mult:XF (match_dup 7) (match_dup 6)))) |
26102535 RH |
3664 | (use (const_int 1))])) |
3665 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3666 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3667 | (minus:DF (match_dup 1) |
3668 | (mult:DF (match_dup 2) (match_dup 9)))) | |
26102535 RH |
3669 | (use (const_int 1))])) |
3670 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3671 | (set (match_dup 0) | |
3672 | (plus:DF (mult:DF (match_dup 4) (match_dup 0)) | |
3673 | (match_dup 9)))) | |
3674 | ] | |
1d5d7a21 | 3675 | { |
02befdf4 ZW |
3676 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3677 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3678 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 3679 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); |
02befdf4 | 3680 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 3681 | } |
26102535 | 3682 | [(set_attr "predicable" "no")]) |
b38ba463 ZW |
3683 | |
3684 | ;; Inline square root. | |
3685 | ||
3686 | (define_expand "sqrtdf2" | |
3687 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3688 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
3689 | "TARGET_INLINE_SQRT" | |
3690 | { | |
3691 | rtx insn; | |
b38ba463 | 3692 | #if 0 |
e820471b | 3693 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3694 | insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]); |
e820471b | 3695 | else |
b38ba463 | 3696 | #else |
e820471b | 3697 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3698 | #endif |
e820471b | 3699 | insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3700 | emit_insn (insn); |
3701 | DONE; | |
3702 | }) | |
3703 | ||
3704 | ;; Latency-optimized square root. | |
3705 | ;; FIXME: Implement. | |
3706 | ||
3707 | ;; Throughput-optimized square root. | |
3708 | ||
3709 | (define_insn_and_split "sqrtdf2_internal_thr" | |
3710 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3711 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f"))) | |
3712 | ;; Register r2 in optimization guide. | |
3713 | (clobber (match_scratch:DI 2 "=r")) | |
3714 | ;; Register f8 in optimization guide | |
3715 | (clobber (match_scratch:XF 3 "=&f")) | |
3716 | ;; Register f9 in optimization guide | |
3717 | (clobber (match_scratch:XF 4 "=&f")) | |
3718 | ;; Register f10 in optimization guide | |
3719 | (clobber (match_scratch:XF 5 "=&f")) | |
3720 | ;; Register p6 in optimization guide. | |
3721 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3722 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3723 | "#" |
3724 | "&& reload_completed" | |
3725 | [ ;; exponent of +1/2 in r2 | |
3726 | (set (match_dup 2) (const_int 65534)) | |
3727 | ;; +1/2 in f10 | |
3728 | (set (match_dup 5) | |
3729 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3730 | ;; Step 1 | |
3731 | ;; y0 = 1/sqrt(a) in f7 | |
3732 | (parallel [(set (match_dup 7) | |
3733 | (div:XF (const_int 1) | |
3734 | (sqrt:XF (match_dup 8)))) | |
3735 | (set (match_dup 6) | |
3736 | (unspec:BI [(match_dup 8)] | |
3737 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3738 | (use (const_int 0))]) | |
3739 | ;; Step 2 | |
3740 | ;; H0 = 1/2 * y0 in f8 | |
3741 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3742 | (parallel [(set (match_dup 3) | |
3743 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) | |
3744 | (match_dup 9))) | |
3745 | (use (const_int 1))])) | |
3746 | ;; Step 3 | |
3747 | ;; G0 = a * y0 in f7 | |
3748 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3749 | (parallel [(set (match_dup 7) | |
3750 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3751 | (match_dup 9))) | |
3752 | (use (const_int 1))])) | |
3753 | ;; Step 4 | |
3754 | ;; r0 = 1/2 - G0 * H0 in f9 | |
3755 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3756 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3757 | (minus:XF (match_dup 5) |
3758 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3759 | (use (const_int 1))])) |
3760 | ;; Step 5 | |
3761 | ;; H1 = H0 + r0 * H0 in f8 | |
3762 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3763 | (parallel [(set (match_dup 3) | |
3764 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3765 | (match_dup 3))) | |
3766 | (use (const_int 1))])) | |
3767 | ;; Step 6 | |
3768 | ;; G1 = G0 + r0 * G0 in f7 | |
3769 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3770 | (parallel [(set (match_dup 7) | |
3771 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3772 | (match_dup 7))) | |
3773 | (use (const_int 1))])) | |
3774 | ;; Step 7 | |
3775 | ;; r1 = 1/2 - G1 * H1 in f9 | |
3776 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3777 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3778 | (minus:XF (match_dup 5) |
3779 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3780 | (use (const_int 1))])) |
3781 | ;; Step 8 | |
3782 | ;; H2 = H1 + r1 * H1 in f8 | |
3783 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3784 | (parallel [(set (match_dup 3) | |
3785 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3786 | (match_dup 3))) | |
3787 | (use (const_int 1))])) | |
3788 | ;; Step 9 | |
3789 | ;; G2 = G1 + r1 * G1 in f7 | |
3790 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3791 | (parallel [(set (match_dup 7) | |
3792 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3793 | (match_dup 7))) | |
3794 | (use (const_int 1))])) | |
3795 | ;; Step 10 | |
3796 | ;; d2 = a - G2 * G2 in f9 | |
3797 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3798 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3799 | (minus:XF (match_dup 8) |
3800 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3801 | (use (const_int 1))])) |
3802 | ;; Step 11 | |
3803 | ;; G3 = G2 + d2 * H2 in f7 | |
3804 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3805 | (parallel [(set (match_dup 7) | |
3806 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3807 | (match_dup 7))) | |
3808 | (use (const_int 1))])) | |
3809 | ;; Step 12 | |
3810 | ;; d3 = a - G3 * G3 in f9 | |
3811 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3812 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3813 | (minus:XF (match_dup 8) |
3814 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3815 | (use (const_int 1))])) |
3816 | ;; Step 13 | |
3817 | ;; S = G3 + d3 * H2 in f7 | |
3818 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3819 | (parallel [(set (match_dup 0) | |
3820 | (float_truncate:DF | |
3821 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3822 | (match_dup 7)))) | |
3823 | (use (const_int 0))]))] | |
3824 | { | |
3825 | /* Generate 82-bit versions of the input and output operands. */ | |
3826 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3827 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3828 | /* Generate required floating-point constants. */ | |
3829 | operands[9] = CONST0_RTX (XFmode); | |
3830 | } | |
3831 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3832 | \f |
3833 | ;; :::::::::::::::::::: | |
3834 | ;; :: | |
27a9b99d | 3835 | ;; :: 80-bit floating point arithmetic |
3f622353 RH |
3836 | ;; :: |
3837 | ;; :::::::::::::::::::: | |
3838 | ||
02befdf4 ZW |
3839 | (define_insn "addxf3" |
3840 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3841 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3842 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3843 | "" | |
aebf2462 | 3844 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3845 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3846 | |
02befdf4 | 3847 | (define_insn "*addxf3_truncsf" |
26102535 RH |
3848 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3849 | (float_truncate:SF | |
02befdf4 ZW |
3850 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3851 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3852 | "" | |
aebf2462 | 3853 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3854 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3855 | |
02befdf4 | 3856 | (define_insn "*addxf3_truncdf" |
26102535 RH |
3857 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3858 | (float_truncate:DF | |
02befdf4 ZW |
3859 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3860 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3861 | "" | |
aebf2462 | 3862 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3863 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3864 | |
02befdf4 ZW |
3865 | (define_insn "subxf3" |
3866 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3867 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3868 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3869 | "" | |
aebf2462 | 3870 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3871 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3872 | |
02befdf4 | 3873 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3874 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3875 | (float_truncate:SF | |
02befdf4 ZW |
3876 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3877 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3878 | "" | |
aebf2462 | 3879 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3880 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3881 | |
02befdf4 | 3882 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3883 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3884 | (float_truncate:DF | |
02befdf4 ZW |
3885 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3886 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3887 | "" | |
aebf2462 | 3888 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3889 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3890 | |
02befdf4 ZW |
3891 | (define_insn "mulxf3" |
3892 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3893 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3894 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3895 | "" | |
aebf2462 | 3896 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3897 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3898 | |
02befdf4 | 3899 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3900 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3901 | (float_truncate:SF | |
02befdf4 ZW |
3902 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3903 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3904 | "" | |
aebf2462 | 3905 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3906 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3907 | |
02befdf4 | 3908 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3909 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3910 | (float_truncate:DF | |
02befdf4 ZW |
3911 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3912 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3913 | "" | |
aebf2462 | 3914 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3915 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3916 | |
02befdf4 ZW |
3917 | (define_insn "*mulxf3_alts" |
3918 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3919 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3920 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3921 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3922 | "" |
aebf2462 | 3923 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3924 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3925 | |
02befdf4 | 3926 | (define_insn "*mulxf3_truncsf_alts" |
26102535 RH |
3927 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3928 | (float_truncate:SF | |
02befdf4 ZW |
3929 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3930 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3931 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3932 | "" |
aebf2462 | 3933 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3934 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3935 | |
02befdf4 | 3936 | (define_insn "*mulxf3_truncdf_alts" |
26102535 RH |
3937 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3938 | (float_truncate:DF | |
02befdf4 ZW |
3939 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3940 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3941 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3942 | "" |
aebf2462 | 3943 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3944 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3945 | |
02befdf4 ZW |
3946 | (define_insn "absxf2" |
3947 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3948 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3949 | "" | |
aebf2462 | 3950 | "fabs %0 = %F1" |
52e12ad0 | 3951 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3952 | |
02befdf4 ZW |
3953 | (define_insn "negxf2" |
3954 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3955 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3956 | "" | |
aebf2462 | 3957 | "fneg %0 = %F1" |
52e12ad0 | 3958 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3959 | |
02befdf4 ZW |
3960 | (define_insn "*nabsxf2" |
3961 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3962 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3963 | "" | |
aebf2462 | 3964 | "fnegabs %0 = %F1" |
52e12ad0 | 3965 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3966 | |
046625fa RH |
3967 | (define_insn "copysignxf3" |
3968 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3969 | (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3970 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3971 | UNSPEC_COPYSIGN))] | |
3972 | "" | |
3973 | "fmerge.s %0 = %F2, %F1" | |
3974 | [(set_attr "itanium_class" "fmisc")]) | |
3975 | ||
3976 | (define_insn "*ncopysignxf3" | |
3977 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3978 | (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3979 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3980 | UNSPEC_COPYSIGN)))] | |
3981 | "" | |
3982 | "fmerge.ns %0 = %F2, %F1" | |
3983 | [(set_attr "itanium_class" "fmisc")]) | |
3984 | ||
7ae4d8d4 | 3985 | (define_insn "sminxf3" |
02befdf4 ZW |
3986 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3987 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3988 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3989 | "" | |
aebf2462 | 3990 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3991 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3992 | |
7ae4d8d4 | 3993 | (define_insn "smaxxf3" |
02befdf4 ZW |
3994 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3995 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3996 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3997 | "" | |
aebf2462 | 3998 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3999 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 4000 | |
02befdf4 ZW |
4001 | (define_insn "*maddxf4" |
4002 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
4003 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4004 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
4005 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
4006 | "" | |
aebf2462 | 4007 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 4008 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 4009 | |
02befdf4 | 4010 | (define_insn "*maddxf4_truncsf" |
26102535 RH |
4011 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
4012 | (float_truncate:SF | |
02befdf4 ZW |
4013 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
4014 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
4015 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
4016 | "" | |
aebf2462 | 4017 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 4018 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4019 | |
02befdf4 | 4020 | (define_insn "*maddxf4_truncdf" |
26102535 RH |
4021 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4022 | (float_truncate:DF | |
02befdf4 ZW |
4023 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
4024 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
4025 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
4026 | "" | |
aebf2462 | 4027 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 4028 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4029 | |
02befdf4 ZW |
4030 | (define_insn "*maddxf4_alts" |
4031 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
4032 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4033 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
4034 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 4035 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4036 | "" |
aebf2462 | 4037 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4038 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 4039 | |
b38ba463 ZW |
4040 | (define_insn "*maddxf4_alts_truncsf" |
4041 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
4042 | (float_truncate:SF | |
4043 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4044 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
4045 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
4046 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
4047 | "" | |
4048 | "fma.s.s%4 %0 = %F1, %F2, %F3" | |
4049 | [(set_attr "itanium_class" "fmac")]) | |
4050 | ||
02befdf4 | 4051 | (define_insn "*maddxf4_alts_truncdf" |
26102535 RH |
4052 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4053 | (float_truncate:DF | |
02befdf4 ZW |
4054 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
4055 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
4056 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 4057 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4058 | "" |
aebf2462 | 4059 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4060 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4061 | |
02befdf4 ZW |
4062 | (define_insn "*msubxf4" |
4063 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
4064 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4065 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
4066 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
4067 | "" | |
aebf2462 | 4068 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 4069 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 4070 | |
02befdf4 | 4071 | (define_insn "*msubxf4_truncsf" |
26102535 RH |
4072 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
4073 | (float_truncate:SF | |
02befdf4 ZW |
4074 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
4075 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
4076 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
4077 | "" | |
aebf2462 | 4078 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 4079 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4080 | |
02befdf4 | 4081 | (define_insn "*msubxf4_truncdf" |
26102535 RH |
4082 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4083 | (float_truncate:DF | |
02befdf4 ZW |
4084 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
4085 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
4086 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
4087 | "" | |
aebf2462 | 4088 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 4089 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4090 | |
02befdf4 ZW |
4091 | (define_insn "*nmulxf3" |
4092 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
4093 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4094 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
4095 | "" | |
aebf2462 | 4096 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 4097 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 4098 | |
02befdf4 | 4099 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
4100 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
4101 | (float_truncate:SF | |
02befdf4 ZW |
4102 | (neg:XF (mult:XF |
4103 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4104 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
4105 | "" | |
aebf2462 | 4106 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 4107 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4108 | |
02befdf4 | 4109 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
4110 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4111 | (float_truncate:DF | |
02befdf4 ZW |
4112 | (neg:XF (mult:XF |
4113 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4114 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
4115 | "" | |
aebf2462 | 4116 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 4117 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4118 | |
02befdf4 ZW |
4119 | (define_insn "*nmaddxf4" |
4120 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
4121 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4122 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4123 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4124 | )))] | |
02befdf4 | 4125 | "" |
aebf2462 | 4126 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 4127 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 4128 | |
02befdf4 | 4129 | (define_insn "*nmaddxf4_truncsf" |
26102535 RH |
4130 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
4131 | (float_truncate:SF | |
52ad4d7b ZW |
4132 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4133 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4134 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4135 | ))))] | |
02befdf4 | 4136 | "" |
aebf2462 | 4137 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 4138 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4139 | |
02befdf4 | 4140 | (define_insn "*nmaddxf4_truncdf" |
26102535 RH |
4141 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4142 | (float_truncate:DF | |
52ad4d7b ZW |
4143 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4144 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4145 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4146 | ))))] | |
02befdf4 | 4147 | "" |
aebf2462 | 4148 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 4149 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4150 | |
02befdf4 ZW |
4151 | (define_insn "*nmaddxf4_alts" |
4152 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
4153 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4154 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4155 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4156 | ))) | |
655f2eb9 | 4157 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4158 | "" |
aebf2462 | 4159 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4160 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 4161 | |
52ad4d7b ZW |
4162 | (define_insn "*nmaddxf4_truncsf_alts" |
4163 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
4164 | (float_truncate:SF | |
4165 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") | |
4166 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4167 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4168 | )))) | |
4169 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
4170 | "" | |
4171 | "fnma.s.s%4 %0 = %F1, %F2, %F3" | |
4172 | [(set_attr "itanium_class" "fmac")]) | |
4173 | ||
02befdf4 | 4174 | (define_insn "*nmaddxf4_truncdf_alts" |
26102535 RH |
4175 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4176 | (float_truncate:DF | |
52ad4d7b ZW |
4177 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4178 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4179 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4180 | )))) | |
26102535 | 4181 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4182 | "" |
aebf2462 | 4183 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4184 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4185 | |
02befdf4 ZW |
4186 | (define_expand "divxf3" |
4187 | [(set (match_operand:XF 0 "fr_register_operand" "") | |
4188 | (div:XF (match_operand:XF 1 "fr_register_operand" "") | |
4189 | (match_operand:XF 2 "fr_register_operand" "")))] | |
4190 | "TARGET_INLINE_FLOAT_DIV" | |
26102535 RH |
4191 | { |
4192 | rtx insn; | |
dbdd120f | 4193 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
02befdf4 | 4194 | insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]); |
26102535 | 4195 | else |
02befdf4 | 4196 | insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]); |
26102535 RH |
4197 | emit_insn (insn); |
4198 | DONE; | |
1d5d7a21 | 4199 | }) |
26102535 | 4200 | |
02befdf4 ZW |
4201 | (define_insn_and_split "divxf3_internal_lat" |
4202 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4203 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
4204 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
4205 | (clobber (match_scratch:XF 3 "=&f")) | |
4206 | (clobber (match_scratch:XF 4 "=&f")) | |
4207 | (clobber (match_scratch:XF 5 "=&f")) | |
4208 | (clobber (match_scratch:XF 6 "=&f")) | |
f2f90c63 | 4209 | (clobber (match_scratch:BI 7 "=c"))] |
dbdd120f | 4210 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
4211 | "#" |
4212 | "&& reload_completed" | |
02befdf4 | 4213 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
4214 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] |
4215 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 4216 | (use (const_int 0))]) |
26102535 RH |
4217 | (cond_exec (ne (match_dup 7) (const_int 0)) |
4218 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4219 | (minus:XF (match_dup 8) |
4220 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4221 | (use (const_int 1))])) |
4222 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 4223 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
4224 | (use (const_int 1))])) |
4225 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 4226 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
4227 | (use (const_int 1))])) |
4228 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4229 | (parallel [(set (match_dup 6) | |
02befdf4 | 4230 | (plus:XF (mult:XF (match_dup 3) (match_dup 3)) |
26102535 RH |
4231 | (match_dup 3))) |
4232 | (use (const_int 1))])) | |
4233 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4234 | (parallel [(set (match_dup 3) | |
02befdf4 | 4235 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
26102535 RH |
4236 | (match_dup 3))) |
4237 | (use (const_int 1))])) | |
4238 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4239 | (parallel [(set (match_dup 5) | |
02befdf4 | 4240 | (plus:XF (mult:XF (match_dup 6) (match_dup 0)) |
26102535 RH |
4241 | (match_dup 0))) |
4242 | (use (const_int 1))])) | |
4243 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4244 | (parallel [(set (match_dup 0) | |
02befdf4 | 4245 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
4246 | (match_dup 0))) |
4247 | (use (const_int 1))])) | |
4248 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4249 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4250 | (minus:XF (match_dup 1) |
4251 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
4252 | (use (const_int 1))])) |
4253 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4254 | (parallel [(set (match_dup 3) | |
02befdf4 | 4255 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4256 | (match_dup 4))) |
4257 | (use (const_int 1))])) | |
4258 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4259 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4260 | (minus:XF (match_dup 8) |
4261 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4262 | (use (const_int 1))])) |
4263 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4264 | (parallel [(set (match_dup 0) | |
02befdf4 | 4265 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4266 | (match_dup 0))) |
4267 | (use (const_int 1))])) | |
4268 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4269 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4270 | (minus:XF (match_dup 1) |
4271 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4272 | (use (const_int 1))])) |
4273 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4274 | (set (match_dup 0) | |
02befdf4 | 4275 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4276 | (match_dup 3)))) |
4277 | ] | |
02befdf4 | 4278 | "operands[8] = CONST1_RTX (XFmode);" |
26102535 RH |
4279 | [(set_attr "predicable" "no")]) |
4280 | ||
02befdf4 ZW |
4281 | (define_insn_and_split "divxf3_internal_thr" |
4282 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4283 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
4284 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
4285 | (clobber (match_scratch:XF 3 "=&f")) | |
4286 | (clobber (match_scratch:XF 4 "=&f")) | |
f2f90c63 | 4287 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 4288 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
4289 | "#" |
4290 | "&& reload_completed" | |
02befdf4 | 4291 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
4292 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
4293 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 4294 | (use (const_int 0))]) |
26102535 RH |
4295 | (cond_exec (ne (match_dup 5) (const_int 0)) |
4296 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4297 | (minus:XF (match_dup 6) |
4298 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4299 | (use (const_int 1))])) |
4300 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4301 | (parallel [(set (match_dup 4) | |
02befdf4 | 4302 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4303 | (match_dup 0))) |
4304 | (use (const_int 1))])) | |
4305 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 4306 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
4307 | (use (const_int 1))])) |
4308 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4309 | (parallel [(set (match_dup 3) | |
02befdf4 | 4310 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
26102535 RH |
4311 | (match_dup 4))) |
4312 | (use (const_int 1))])) | |
4313 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 4314 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
4315 | (use (const_int 1))])) |
4316 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4317 | (parallel [(set (match_dup 0) | |
52ad4d7b ZW |
4318 | (minus:XF (match_dup 6) |
4319 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4320 | (use (const_int 1))])) |
4321 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4322 | (parallel [(set (match_dup 0) | |
02befdf4 | 4323 | (plus:XF (mult:XF (match_dup 0) (match_dup 3)) |
26102535 RH |
4324 | (match_dup 3))) |
4325 | (use (const_int 1))])) | |
4326 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4327 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4328 | (minus:XF (match_dup 1) |
4329 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
4330 | (use (const_int 1))])) |
4331 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4332 | (parallel [(set (match_dup 3) | |
02befdf4 | 4333 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4334 | (match_dup 4))) |
4335 | (use (const_int 1))])) | |
4336 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4337 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4338 | (minus:XF (match_dup 6) |
4339 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4340 | (use (const_int 1))])) |
4341 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4342 | (parallel [(set (match_dup 0) | |
02befdf4 | 4343 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4344 | (match_dup 0))) |
4345 | (use (const_int 1))])) | |
4346 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4347 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4348 | (minus:XF (match_dup 1) |
4349 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4350 | (use (const_int 1))])) |
4351 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4352 | (set (match_dup 0) | |
02befdf4 | 4353 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4354 | (match_dup 3)))) |
4355 | ] | |
02befdf4 | 4356 | "operands[6] = CONST1_RTX (XFmode);" |
26102535 RH |
4357 | [(set_attr "predicable" "no")]) |
4358 | ||
b38ba463 ZW |
4359 | ;; Inline square root. |
4360 | ||
4361 | (define_expand "sqrtxf2" | |
4362 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4363 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))] | |
4364 | "TARGET_INLINE_SQRT" | |
4365 | { | |
4366 | rtx insn; | |
b38ba463 | 4367 | #if 0 |
e820471b | 4368 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 4369 | insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]); |
e820471b | 4370 | else |
b38ba463 | 4371 | #else |
e820471b | 4372 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 4373 | #endif |
e820471b | 4374 | insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
4375 | emit_insn (insn); |
4376 | DONE; | |
4377 | }) | |
4378 | ||
4379 | ;; Latency-optimized square root. | |
4380 | ;; FIXME: Implement. | |
4381 | ||
4382 | ;; Throughput-optimized square root. | |
4383 | ||
4384 | (define_insn_and_split "sqrtxf2_internal_thr" | |
4385 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4386 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f"))) | |
4387 | ;; Register r2 in optimization guide. | |
4388 | (clobber (match_scratch:DI 2 "=r")) | |
4389 | ;; Register f8 in optimization guide | |
4390 | (clobber (match_scratch:XF 3 "=&f")) | |
4391 | ;; Register f9 in optimization guide | |
4392 | (clobber (match_scratch:XF 4 "=&f")) | |
4393 | ;; Register f10 in optimization guide | |
4394 | (clobber (match_scratch:XF 5 "=&f")) | |
4395 | ;; Register f11 in optimization guide | |
4396 | (clobber (match_scratch:XF 6 "=&f")) | |
4397 | ;; Register p6 in optimization guide. | |
4398 | (clobber (match_scratch:BI 7 "=c"))] | |
dbdd120f | 4399 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
4400 | "#" |
4401 | "&& reload_completed" | |
4402 | [ ;; exponent of +1/2 in r2 | |
4403 | (set (match_dup 2) (const_int 65534)) | |
4404 | ;; +1/2 in f8. The Intel manual mistakenly specifies f10. | |
4405 | (set (match_dup 3) | |
4406 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
4407 | ;; Step 1 | |
4408 | ;; y0 = 1/sqrt(a) in f7 | |
4409 | (parallel [(set (match_dup 8) | |
4410 | (div:XF (const_int 1) | |
4411 | (sqrt:XF (match_dup 9)))) | |
4412 | (set (match_dup 7) | |
4413 | (unspec:BI [(match_dup 9)] | |
4414 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
4415 | (use (const_int 0))]) | |
4416 | ;; Step 2 | |
4417 | ;; H0 = 1/2 * y0 in f9 | |
4418 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4419 | (parallel [(set (match_dup 4) | |
4420 | (plus:XF (mult:XF (match_dup 3) (match_dup 8)) | |
4421 | (match_dup 10))) | |
4422 | (use (const_int 1))])) | |
4423 | ;; Step 3 | |
4424 | ;; S0 = a * y0 in f7 | |
4425 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4426 | (parallel [(set (match_dup 8) | |
4427 | (plus:XF (mult:XF (match_dup 9) (match_dup 8)) | |
4428 | (match_dup 10))) | |
4429 | (use (const_int 1))])) | |
4430 | ;; Step 4 | |
4431 | ;; d0 = 1/2 - S0 * H0 in f10 | |
4432 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4433 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4434 | (minus:XF (match_dup 3) |
4435 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4436 | (use (const_int 1))])) |
4437 | ;; Step 5 | |
4438 | ;; H1 = H0 + d0 * H0 in f9 | |
4439 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4440 | (parallel [(set (match_dup 4) | |
4441 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4442 | (match_dup 4))) | |
4443 | (use (const_int 1))])) | |
4444 | ;; Step 6 | |
4445 | ;; S1 = S0 + d0 * S0 in f7 | |
4446 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4447 | (parallel [(set (match_dup 8) | |
4448 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4449 | (match_dup 8))) | |
4450 | (use (const_int 1))])) | |
4451 | ;; Step 7 | |
4452 | ;; d1 = 1/2 - S1 * H1 in f10 | |
4453 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4454 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4455 | (minus:XF (match_dup 3) |
4456 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4457 | (use (const_int 1))])) |
4458 | ;; Step 8 | |
4459 | ;; H2 = H1 + d1 * H1 in f9 | |
4460 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4461 | (parallel [(set (match_dup 4) | |
4462 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4463 | (match_dup 4))) | |
4464 | (use (const_int 1))])) | |
4465 | ;; Step 9 | |
4466 | ;; S2 = S1 + d1 * S1 in f7 | |
4467 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4468 | (parallel [(set (match_dup 8) | |
4469 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4470 | (match_dup 8))) | |
4471 | (use (const_int 1))])) | |
4472 | ;; Step 10 | |
4473 | ;; d2 = 1/2 - S2 * H2 in f10 | |
4474 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4475 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4476 | (minus:XF (match_dup 3) |
4477 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4478 | (use (const_int 1))])) |
4479 | ;; Step 11 | |
4480 | ;; e2 = a - S2 * S2 in f8 | |
4481 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4482 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4483 | (minus:XF (match_dup 9) |
4484 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4485 | (use (const_int 1))])) |
4486 | ;; Step 12 | |
4487 | ;; S3 = S2 + e2 * H2 in f7 | |
4488 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4489 | (parallel [(set (match_dup 8) | |
4490 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4491 | (match_dup 8))) | |
4492 | (use (const_int 1))])) | |
4493 | ;; Step 13 | |
4494 | ;; H3 = H2 + d2 * H2 in f9 | |
4495 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4496 | (parallel [(set (match_dup 4) | |
4497 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4498 | (match_dup 4))) | |
4499 | (use (const_int 1))])) | |
4500 | ;; Step 14 | |
4501 | ;; e3 = a - S3 * S3 in f8 | |
4502 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4503 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4504 | (minus:XF (match_dup 9) |
4505 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4506 | (use (const_int 1))])) |
4507 | ;; Step 15 | |
4508 | ;; S = S3 + e3 * H3 in f7 | |
4509 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4510 | (parallel [(set (match_dup 0) | |
4511 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4512 | (match_dup 8))) | |
4513 | (use (const_int 0))]))] | |
4514 | { | |
4515 | /* Generate 82-bit versions of the input and output operands. */ | |
4516 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
4517 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
4518 | /* Generate required floating-point constants. */ | |
4519 | operands[10] = CONST0_RTX (XFmode); | |
4520 | } | |
4521 | [(set_attr "predicable" "no")]) | |
4522 | ||
26102535 RH |
4523 | ;; ??? frcpa works like cmp.foo.unc. |
4524 | ||
655f2eb9 | 4525 | (define_insn "*recip_approx" |
02befdf4 ZW |
4526 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
4527 | (div:XF (const_int 1) | |
4528 | (match_operand:XF 3 "fr_register_operand" "f"))) | |
f2f90c63 | 4529 | (set (match_operand:BI 1 "register_operand" "=c") |
02befdf4 | 4530 | (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f") |
086c0f96 | 4531 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 4532 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4533 | "" |
655f2eb9 | 4534 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 4535 | [(set_attr "itanium_class" "fmisc") |
26102535 | 4536 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4537 | \f |
4538 | ;; :::::::::::::::::::: | |
4539 | ;; :: | |
27a9b99d | 4540 | ;; :: 32-bit Integer Shifts and Rotates |
c65ebc55 JW |
4541 | ;; :: |
4542 | ;; :::::::::::::::::::: | |
4543 | ||
9c668921 | 4544 | (define_expand "ashlsi3" |
0551c32d RH |
4545 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4546 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
4547 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 4548 | "" |
9c668921 RH |
4549 | { |
4550 | if (GET_CODE (operands[2]) != CONST_INT) | |
4551 | { | |
4552 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
4553 | we've got to get rid of stray bits outside the SImode register. */ | |
4554 | rtx subshift = gen_reg_rtx (DImode); | |
4555 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
4556 | operands[2] = subshift; | |
4557 | } | |
1d5d7a21 | 4558 | }) |
9c668921 RH |
4559 | |
4560 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
4561 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
4562 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
4563 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 4564 | "" |
041f25e6 RH |
4565 | "@ |
4566 | shladd %0 = %1, %2, r0 | |
4567 | dep.z %0 = %1, %2, %E2 | |
4568 | shl %0 = %1, %2" | |
52e12ad0 | 4569 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
4570 | |
4571 | (define_expand "ashrsi3" | |
0551c32d RH |
4572 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4573 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4574 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4575 | "" |
c65ebc55 | 4576 | { |
041f25e6 RH |
4577 | rtx subtarget = gen_reg_rtx (DImode); |
4578 | if (GET_CODE (operands[2]) == CONST_INT) | |
4579 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
4580 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4581 | else | |
4582 | { | |
9c668921 | 4583 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4584 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4585 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4586 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4587 | } |
4588 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4589 | DONE; | |
1d5d7a21 | 4590 | }) |
c65ebc55 | 4591 | |
c65ebc55 | 4592 | (define_expand "lshrsi3" |
0551c32d RH |
4593 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4594 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4595 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4596 | "" |
c65ebc55 | 4597 | { |
041f25e6 RH |
4598 | rtx subtarget = gen_reg_rtx (DImode); |
4599 | if (GET_CODE (operands[2]) == CONST_INT) | |
4600 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
4601 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4602 | else | |
4603 | { | |
9c668921 | 4604 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4605 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4606 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4607 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4608 | } |
4609 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4610 | DONE; | |
1d5d7a21 | 4611 | }) |
c65ebc55 | 4612 | |
c65ebc55 | 4613 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
4614 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
4615 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
4616 | |
4617 | (define_expand "rotrsi3" | |
66db6b45 RH |
4618 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4619 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
4620 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
4621 | "" | |
66db6b45 RH |
4622 | { |
4623 | if (GET_MODE (operands[2]) != VOIDmode) | |
4624 | { | |
4625 | rtx tmp = gen_reg_rtx (DImode); | |
4626 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
4627 | operands[2] = tmp; | |
4628 | } | |
1d5d7a21 | 4629 | }) |
66db6b45 RH |
4630 | |
4631 | (define_insn_and_split "*rotrsi3_internal" | |
4632 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
4633 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4634 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
4635 | "" | |
4636 | "#" | |
4637 | "reload_completed" | |
c65ebc55 | 4638 | [(set (match_dup 3) |
66db6b45 | 4639 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
4640 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
4641 | (set (match_dup 3) | |
66db6b45 RH |
4642 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
4643 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
4644 | ||
4645 | (define_expand "rotlsi3" | |
4646 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
4647 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
4648 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4649 | "" |
c65ebc55 JW |
4650 | { |
4651 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
4652 | { |
4653 | rtx tmp = gen_reg_rtx (SImode); | |
4654 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
4655 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
4656 | DONE; | |
4657 | } | |
1d5d7a21 | 4658 | }) |
66db6b45 RH |
4659 | |
4660 | (define_insn_and_split "*rotlsi3_internal" | |
4661 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
4662 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4663 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
4664 | "" | |
51094457 JB |
4665 | "mux2 %0 = %1, 0xe1" |
4666 | "reload_completed && INTVAL (operands[2]) != 16" | |
66db6b45 RH |
4667 | [(set (match_dup 3) |
4668 | (ior:DI (zero_extend:DI (match_dup 1)) | |
4669 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
4670 | (set (match_dup 3) | |
4671 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
4672 | { |
4673 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
4674 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
51094457 JB |
4675 | } |
4676 | [(set_attr "itanium_class" "mmshf")]) | |
c65ebc55 JW |
4677 | \f |
4678 | ;; :::::::::::::::::::: | |
4679 | ;; :: | |
27a9b99d | 4680 | ;; :: 64-bit Integer Shifts and Rotates |
c65ebc55 JW |
4681 | ;; :: |
4682 | ;; :::::::::::::::::::: | |
4683 | ||
4684 | (define_insn "ashldi3" | |
52e12ad0 BS |
4685 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
4686 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
4687 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 4688 | "" |
041f25e6 RH |
4689 | "@ |
4690 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 4691 | shl %0 = %1, %2 |
041f25e6 | 4692 | shl %0 = %1, %2" |
52e12ad0 | 4693 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
4694 | |
4695 | ;; ??? Maybe combine this with the multiply and add instruction? | |
4696 | ||
4697 | (define_insn "*shladd" | |
0551c32d RH |
4698 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4699 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4700 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 4701 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
4702 | "" |
4703 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 4704 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4705 | |
4706 | ;; This can be created by register elimination if operand3 of shladd is an | |
4707 | ;; eliminable register or has reg_equiv_constant set. | |
4708 | ||
4709 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
4710 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
4711 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
4712 | ;; incorrectly. | |
4713 | ||
5527bf14 | 4714 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
4715 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
4716 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4717 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 4718 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
4719 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
4720 | "reload_in_progress" | |
e820471b | 4721 | "* gcc_unreachable ();" |
c65ebc55 JW |
4722 | "reload_completed" |
4723 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
4724 | (match_dup 3))) | |
c65ebc55 | 4725 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 4726 | "" |
52e12ad0 | 4727 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4728 | |
4729 | (define_insn "ashrdi3" | |
52e12ad0 BS |
4730 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4731 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4732 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4733 | "" |
52e12ad0 BS |
4734 | "@ |
4735 | shr %0 = %1, %2 | |
4736 | shr %0 = %1, %2" | |
4737 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4738 | |
4739 | (define_insn "lshrdi3" | |
52e12ad0 BS |
4740 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4741 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4742 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4743 | "" |
52e12ad0 BS |
4744 | "@ |
4745 | shr.u %0 = %1, %2 | |
4746 | shr.u %0 = %1, %2" | |
4747 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4748 | |
4749 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
4750 | ;; will load the operand into a register and call the pattern if the predicate | |
4751 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
4752 | ;; verify that we have an appropriate constant in the expander. | |
4753 | ||
4754 | (define_expand "rotrdi3" | |
0551c32d RH |
4755 | [(set (match_operand:DI 0 "gr_register_operand" "") |
4756 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
4757 | (match_operand:DI 2 "nonmemory_operand" "")))] |
4758 | "" | |
c65ebc55 JW |
4759 | { |
4760 | if (! shift_count_operand (operands[2], DImode)) | |
4761 | FAIL; | |
1d5d7a21 | 4762 | }) |
c65ebc55 JW |
4763 | |
4764 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
4765 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4766 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4767 | (match_operand:DI 2 "shift_count_operand" "M")))] |
4768 | "" | |
4769 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 4770 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 4771 | |
66db6b45 RH |
4772 | (define_expand "rotldi3" |
4773 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4774 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
4775 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4776 | "" | |
66db6b45 RH |
4777 | { |
4778 | if (! shift_count_operand (operands[2], DImode)) | |
4779 | FAIL; | |
1d5d7a21 | 4780 | }) |
66db6b45 RH |
4781 | |
4782 | (define_insn "*rotldi3_internal" | |
4783 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4784 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
4785 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
4786 | "" | |
4787 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 4788 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
4789 | \f |
4790 | ;; :::::::::::::::::::: | |
4791 | ;; :: | |
27a9b99d | 4792 | ;; :: 128-bit Integer Shifts and Rotates |
f526a3c8 RH |
4793 | ;; :: |
4794 | ;; :::::::::::::::::::: | |
4795 | ||
16d8386b JB |
4796 | (define_expand "ashlti3" |
4797 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4798 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "") | |
4799 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4800 | "" | |
4801 | { | |
4802 | if (!dshift_count_operand (operands[2], DImode)) | |
4803 | FAIL; | |
4804 | }) | |
4805 | ||
4806 | (define_insn_and_split "*ashlti3_internal" | |
4807 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4808 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4809 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4810 | "" | |
4811 | "#" | |
4812 | "reload_completed" | |
4813 | [(const_int 0)] | |
4814 | { | |
4815 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
4816 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4817 | rtx rh = gen_highpart (DImode, operands[0]); | |
4818 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4819 | rtx shiftlo = GEN_INT (shift & 63); | |
4820 | ||
4821 | if (shift & 64) | |
4822 | { | |
4823 | emit_move_insn (rl, const0_rtx); | |
4824 | if (shift & 63) | |
4825 | emit_insn (gen_ashldi3 (rh, lo, shiftlo)); | |
4826 | else | |
4827 | emit_move_insn (rh, lo); | |
4828 | } | |
4829 | else | |
4830 | { | |
4831 | rtx hi = gen_highpart (DImode, operands[1]); | |
4832 | ||
4833 | emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63))); | |
4834 | emit_insn (gen_ashldi3 (rl, lo, shiftlo)); | |
4835 | } | |
4836 | DONE; | |
4837 | }) | |
4838 | ||
f526a3c8 RH |
4839 | (define_expand "ashrti3" |
4840 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4841 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4842 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4843 | "" | |
4844 | { | |
4845 | if (!dshift_count_operand (operands[2], DImode)) | |
4846 | FAIL; | |
4847 | }) | |
4848 | ||
4849 | (define_insn_and_split "*ashrti3_internal" | |
16d8386b | 4850 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4851 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4852 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4853 | "" | |
4854 | "#" | |
4855 | "reload_completed" | |
4856 | [(const_int 0)] | |
4857 | { | |
4858 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4859 | rtx rl = gen_lowpart (DImode, operands[0]); |
4860 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4861 | rtx hi = gen_highpart (DImode, operands[1]); |
4862 | rtx shiftlo = GEN_INT (shift & 63); | |
4863 | ||
4864 | if (shift & 64) | |
4865 | { | |
16d8386b JB |
4866 | if (shift & 63) |
4867 | emit_insn (gen_ashrdi3 (rl, hi, shiftlo)); | |
4868 | else | |
4869 | emit_move_insn (rl, hi); | |
4870 | emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63))); | |
f526a3c8 RH |
4871 | } |
4872 | else | |
4873 | { | |
16d8386b JB |
4874 | rtx lo = gen_lowpart (DImode, operands[1]); |
4875 | ||
4876 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4877 | emit_insn (gen_ashrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4878 | } |
4879 | DONE; | |
4880 | }) | |
4881 | ||
4882 | (define_expand "lshrti3" | |
4883 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4884 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4885 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4886 | "" | |
4887 | { | |
4888 | if (!dshift_count_operand (operands[2], DImode)) | |
4889 | FAIL; | |
4890 | }) | |
4891 | ||
4892 | (define_insn_and_split "*lshrti3_internal" | |
16d8386b | 4893 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4894 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4895 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4896 | "" | |
4897 | "#" | |
4898 | "reload_completed" | |
4899 | [(const_int 0)] | |
4900 | { | |
4901 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4902 | rtx rl = gen_lowpart (DImode, operands[0]); |
4903 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4904 | rtx hi = gen_highpart (DImode, operands[1]); |
4905 | rtx shiftlo = GEN_INT (shift & 63); | |
4906 | ||
4907 | if (shift & 64) | |
4908 | { | |
16d8386b JB |
4909 | if (shift & 63) |
4910 | emit_insn (gen_lshrdi3 (rl, hi, shiftlo)); | |
4911 | else | |
4912 | emit_move_insn (rl, hi); | |
4913 | emit_move_insn (rh, const0_rtx); | |
f526a3c8 RH |
4914 | } |
4915 | else | |
4916 | { | |
16d8386b JB |
4917 | rtx lo = gen_lowpart (DImode, operands[1]); |
4918 | ||
4919 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4920 | emit_insn (gen_lshrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4921 | } |
4922 | DONE; | |
4923 | }) | |
4924 | ||
a71aef0b JB |
4925 | (define_expand "rotlti3" |
4926 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4927 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "") | |
4928 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4929 | "" | |
4930 | { | |
4931 | if (! dshift_count_operand (operands[2], DImode)) | |
4932 | FAIL; | |
4933 | }) | |
4934 | ||
4935 | (define_insn_and_split "*rotlti3_internal" | |
4936 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4937 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4938 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4939 | "" | |
4940 | "#" | |
4941 | "reload_completed" | |
4942 | [(const_int 0)] | |
4943 | { | |
4944 | HOST_WIDE_INT count = INTVAL (operands[2]); | |
4945 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4946 | rtx rh = gen_highpart (DImode, operands[0]); | |
4947 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4948 | rtx hi = gen_highpart (DImode, operands[1]); | |
4949 | rtx countlo = GEN_INT (-count & 63); | |
4950 | ||
4951 | if (count & 64) | |
4952 | { | |
4953 | if (count & 63) | |
4954 | { | |
4955 | emit_insn (gen_shrp (rl, hi, lo, countlo)); | |
4956 | emit_insn (gen_shrp (rh, lo, hi, countlo)); | |
4957 | } | |
4958 | else | |
4959 | { | |
4960 | emit_move_insn (rl, hi); | |
4961 | emit_move_insn (rh, lo); | |
4962 | } | |
4963 | } | |
4964 | else | |
4965 | { | |
4966 | emit_insn (gen_shrp (rl, lo, hi, countlo)); | |
4967 | emit_insn (gen_shrp (rh, hi, lo, countlo)); | |
4968 | } | |
4969 | DONE; | |
4970 | } | |
4971 | [(set_attr "itanium_class" "unknown")]) | |
4972 | ||
f526a3c8 RH |
4973 | (define_insn "shrp" |
4974 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4975 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
4976 | (match_operand:DI 2 "gr_register_operand" "r") | |
4977 | (match_operand:DI 3 "shift_count_operand" "M")] | |
4978 | UNSPEC_SHRP))] | |
4979 | "" | |
4980 | "shrp %0 = %1, %2, %3" | |
4981 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
4982 | \f |
4983 | ;; :::::::::::::::::::: | |
4984 | ;; :: | |
27a9b99d | 4985 | ;; :: 32-bit Integer Logical operations |
c65ebc55 JW |
4986 | ;; :: |
4987 | ;; :::::::::::::::::::: | |
4988 | ||
4989 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
4990 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
4991 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
4992 | ;; This doesn't work for unary logical operations, because we don't call | |
4993 | ;; apply_distributive_law for them. | |
4994 | ||
4995 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
4996 | ;; apply_distributive_law. We get inefficient code for | |
4997 | ;; int sub4 (int i, int j) { return i & ~j; } | |
4998 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
4999 | ;; (zero_extend (and (not A) B)) in combine. | |
5000 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
5001 | ;; one_cmplsi2 pattern. | |
5002 | ||
058557c4 | 5003 | (define_insn "one_cmplsi2" |
0551c32d RH |
5004 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5005 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
5006 | "" |
5007 | "andcm %0 = -1, %1" | |
52e12ad0 | 5008 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
5009 | \f |
5010 | ;; :::::::::::::::::::: | |
5011 | ;; :: | |
27a9b99d | 5012 | ;; :: 64-bit Integer Logical operations |
c65ebc55 JW |
5013 | ;; :: |
5014 | ;; :::::::::::::::::::: | |
5015 | ||
5016 | (define_insn "anddi3" | |
0551c32d RH |
5017 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
5018 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
5019 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
5020 | "" |
5021 | "@ | |
5022 | and %0 = %2, %1 | |
aebf2462 | 5023 | fand %0 = %2, %1" |
52e12ad0 | 5024 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
5025 | |
5026 | (define_insn "*andnot" | |
0551c32d RH |
5027 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
5028 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
5029 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
5030 | "" |
5031 | "@ | |
5032 | andcm %0 = %2, %1 | |
aebf2462 | 5033 | fandcm %0 = %2, %1" |
52e12ad0 | 5034 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
5035 | |
5036 | (define_insn "iordi3" | |
0551c32d RH |
5037 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
5038 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
5039 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
5040 | "" |
5041 | "@ | |
5042 | or %0 = %2, %1 | |
aebf2462 | 5043 | for %0 = %2, %1" |
52e12ad0 | 5044 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
5045 | |
5046 | (define_insn "xordi3" | |
0551c32d RH |
5047 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
5048 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
5049 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
5050 | "" |
5051 | "@ | |
5052 | xor %0 = %2, %1 | |
aebf2462 | 5053 | fxor %0 = %2, %1" |
52e12ad0 | 5054 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
5055 | |
5056 | (define_insn "one_cmpldi2" | |
0551c32d RH |
5057 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5058 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
5059 | "" |
5060 | "andcm %0 = -1, %1" | |
52e12ad0 | 5061 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
5062 | \f |
5063 | ;; :::::::::::::::::::: | |
5064 | ;; :: | |
5065 | ;; :: Comparisons | |
5066 | ;; :: | |
5067 | ;; :::::::::::::::::::: | |
5068 | ||
f2f90c63 RH |
5069 | (define_expand "cmpbi" |
5070 | [(set (cc0) | |
5071 | (compare (match_operand:BI 0 "register_operand" "") | |
5072 | (match_operand:BI 1 "const_int_operand" "")))] | |
5073 | "" | |
f2f90c63 RH |
5074 | { |
5075 | ia64_compare_op0 = operands[0]; | |
5076 | ia64_compare_op1 = operands[1]; | |
5077 | DONE; | |
1d5d7a21 | 5078 | }) |
f2f90c63 | 5079 | |
c65ebc55 JW |
5080 | (define_expand "cmpsi" |
5081 | [(set (cc0) | |
0551c32d RH |
5082 | (compare (match_operand:SI 0 "gr_register_operand" "") |
5083 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 5084 | "" |
c65ebc55 JW |
5085 | { |
5086 | ia64_compare_op0 = operands[0]; | |
5087 | ia64_compare_op1 = operands[1]; | |
5088 | DONE; | |
1d5d7a21 | 5089 | }) |
c65ebc55 JW |
5090 | |
5091 | (define_expand "cmpdi" | |
5092 | [(set (cc0) | |
0551c32d RH |
5093 | (compare (match_operand:DI 0 "gr_register_operand" "") |
5094 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 5095 | "" |
c65ebc55 JW |
5096 | { |
5097 | ia64_compare_op0 = operands[0]; | |
5098 | ia64_compare_op1 = operands[1]; | |
5099 | DONE; | |
1d5d7a21 | 5100 | }) |
c65ebc55 JW |
5101 | |
5102 | (define_expand "cmpsf" | |
5103 | [(set (cc0) | |
0551c32d RH |
5104 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
5105 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 5106 | "" |
c65ebc55 JW |
5107 | { |
5108 | ia64_compare_op0 = operands[0]; | |
5109 | ia64_compare_op1 = operands[1]; | |
5110 | DONE; | |
1d5d7a21 | 5111 | }) |
c65ebc55 JW |
5112 | |
5113 | (define_expand "cmpdf" | |
5114 | [(set (cc0) | |
0551c32d RH |
5115 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
5116 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 5117 | "" |
c65ebc55 JW |
5118 | { |
5119 | ia64_compare_op0 = operands[0]; | |
5120 | ia64_compare_op1 = operands[1]; | |
5121 | DONE; | |
1d5d7a21 | 5122 | }) |
c65ebc55 | 5123 | |
02befdf4 | 5124 | (define_expand "cmpxf" |
c65ebc55 | 5125 | [(set (cc0) |
02befdf4 ZW |
5126 | (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "") |
5127 | (match_operand:XF 1 "xfreg_or_fp01_operand" "")))] | |
5128 | "" | |
c65ebc55 JW |
5129 | { |
5130 | ia64_compare_op0 = operands[0]; | |
5131 | ia64_compare_op1 = operands[1]; | |
5132 | DONE; | |
1d5d7a21 | 5133 | }) |
c65ebc55 | 5134 | |
24ea7948 ZW |
5135 | (define_expand "cmptf" |
5136 | [(set (cc0) | |
5137 | (compare (match_operand:TF 0 "gr_register_operand" "") | |
5138 | (match_operand:TF 1 "gr_register_operand" "")))] | |
5139 | "TARGET_HPUX" | |
5140 | { | |
5141 | ia64_compare_op0 = operands[0]; | |
5142 | ia64_compare_op1 = operands[1]; | |
5143 | DONE; | |
5144 | }) | |
5145 | ||
c65ebc55 | 5146 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
5147 | [(set (match_operand:BI 0 "register_operand" "=c") |
5148 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
5149 | [(match_operand:SI 2 "gr_register_operand" "r") |
5150 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
5151 | "" |
5152 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 5153 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 5154 | |
18a3c539 JW |
5155 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
5156 | ;; unsigned comparisons don't accept immediate operands of zero. | |
5157 | ||
c65ebc55 | 5158 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
5159 | [(set (match_operand:BI 0 "register_operand" "=c") |
5160 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
5161 | [(match_operand:SI 2 "gr_register_operand" "r") |
5162 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 5163 | "" |
18a3c539 | 5164 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 5165 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
5166 | |
5167 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
5168 | [(set (match_operand:BI 0 "register_operand" "=c") |
5169 | (match_operator:BI 1 "normal_comparison_operator" | |
5170 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 5171 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 5172 | "" |
f2f90c63 | 5173 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 5174 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 5175 | |
18a3c539 JW |
5176 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
5177 | ;; unsigned comparisons don't accept immediate operands of zero. | |
5178 | ||
c65ebc55 | 5179 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
5180 | [(set (match_operand:BI 0 "register_operand" "=c") |
5181 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
5182 | [(match_operand:DI 2 "gr_register_operand" "r") |
5183 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 5184 | "" |
18a3c539 | 5185 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 5186 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
5187 | |
5188 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
5189 | [(set (match_operand:BI 0 "register_operand" "=c") |
5190 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
5191 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
5192 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
5193 | "" |
5194 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 5195 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
5196 | |
5197 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
5198 | [(set (match_operand:BI 0 "register_operand" "=c") |
5199 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
5200 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
5201 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
5202 | "" |
5203 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 5204 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 5205 | |
02befdf4 | 5206 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
5207 | [(set (match_operand:BI 0 "register_operand" "=c") |
5208 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
5209 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
5210 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
5211 | "" | |
3f622353 | 5212 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 5213 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 5214 | |
c65ebc55 JW |
5215 | ;; ??? Can this pattern be generated? |
5216 | ||
5217 | (define_insn "*bit_zero" | |
f2f90c63 RH |
5218 | [(set (match_operand:BI 0 "register_operand" "=c") |
5219 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 5220 | (const_int 1) |
5d48891e | 5221 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
5222 | (const_int 0)))] |
5223 | "" | |
5224 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 5225 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
5226 | |
5227 | (define_insn "*bit_one" | |
f2f90c63 RH |
5228 | [(set (match_operand:BI 0 "register_operand" "=c") |
5229 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 5230 | (const_int 1) |
5d48891e | 5231 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
5232 | (const_int 0)))] |
5233 | "" | |
5234 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 5235 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
5236 | \f |
5237 | ;; :::::::::::::::::::: | |
5238 | ;; :: | |
5239 | ;; :: Branches | |
5240 | ;; :: | |
5241 | ;; :::::::::::::::::::: | |
5242 | ||
5243 | (define_expand "beq" | |
f2f90c63 RH |
5244 | [(set (pc) |
5245 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5246 | (label_ref (match_operand 0 "" "")) |
5247 | (pc)))] | |
5248 | "" | |
f2f90c63 | 5249 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
5250 | |
5251 | (define_expand "bne" | |
f2f90c63 RH |
5252 | [(set (pc) |
5253 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5254 | (label_ref (match_operand 0 "" "")) |
5255 | (pc)))] | |
5256 | "" | |
f2f90c63 | 5257 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
5258 | |
5259 | (define_expand "blt" | |
f2f90c63 RH |
5260 | [(set (pc) |
5261 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5262 | (label_ref (match_operand 0 "" "")) |
5263 | (pc)))] | |
5264 | "" | |
f2f90c63 | 5265 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
5266 | |
5267 | (define_expand "ble" | |
f2f90c63 RH |
5268 | [(set (pc) |
5269 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5270 | (label_ref (match_operand 0 "" "")) |
5271 | (pc)))] | |
5272 | "" | |
f2f90c63 | 5273 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
5274 | |
5275 | (define_expand "bgt" | |
f2f90c63 RH |
5276 | [(set (pc) |
5277 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5278 | (label_ref (match_operand 0 "" "")) |
5279 | (pc)))] | |
5280 | "" | |
f2f90c63 | 5281 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
5282 | |
5283 | (define_expand "bge" | |
f2f90c63 RH |
5284 | [(set (pc) |
5285 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5286 | (label_ref (match_operand 0 "" "")) |
5287 | (pc)))] | |
5288 | "" | |
f2f90c63 | 5289 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
5290 | |
5291 | (define_expand "bltu" | |
f2f90c63 RH |
5292 | [(set (pc) |
5293 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5294 | (label_ref (match_operand 0 "" "")) |
5295 | (pc)))] | |
5296 | "" | |
f2f90c63 | 5297 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
5298 | |
5299 | (define_expand "bleu" | |
f2f90c63 RH |
5300 | [(set (pc) |
5301 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5302 | (label_ref (match_operand 0 "" "")) |
5303 | (pc)))] | |
5304 | "" | |
f2f90c63 | 5305 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
5306 | |
5307 | (define_expand "bgtu" | |
f2f90c63 RH |
5308 | [(set (pc) |
5309 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5310 | (label_ref (match_operand 0 "" "")) |
5311 | (pc)))] | |
5312 | "" | |
f2f90c63 | 5313 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
5314 | |
5315 | (define_expand "bgeu" | |
f2f90c63 RH |
5316 | [(set (pc) |
5317 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5318 | (label_ref (match_operand 0 "" "")) |
5319 | (pc)))] | |
5320 | "" | |
f2f90c63 | 5321 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 5322 | |
e57b9d65 | 5323 | (define_expand "bunordered" |
f2f90c63 RH |
5324 | [(set (pc) |
5325 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5326 | (label_ref (match_operand 0 "" "")) |
5327 | (pc)))] | |
5328 | "" | |
f2f90c63 | 5329 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
5330 | |
5331 | (define_expand "bordered" | |
f2f90c63 RH |
5332 | [(set (pc) |
5333 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5334 | (label_ref (match_operand 0 "" "")) |
5335 | (pc)))] | |
5336 | "" | |
f2f90c63 | 5337 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 5338 | |
6b6c1201 | 5339 | (define_insn "*br_true" |
c65ebc55 | 5340 | [(set (pc) |
6b6c1201 | 5341 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5342 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
5343 | (const_int 0)]) |
5344 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
5345 | (pc)))] |
5346 | "" | |
85548039 | 5347 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 5348 | [(set_attr "itanium_class" "br") |
e5bde68a | 5349 | (set_attr "predicable" "no")]) |
c65ebc55 | 5350 | |
6b6c1201 | 5351 | (define_insn "*br_false" |
c65ebc55 | 5352 | [(set (pc) |
6b6c1201 | 5353 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5354 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5355 | (const_int 0)]) |
c65ebc55 | 5356 | (pc) |
6b6c1201 | 5357 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 5358 | "" |
85548039 | 5359 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 5360 | [(set_attr "itanium_class" "br") |
e5bde68a | 5361 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5362 | \f |
5363 | ;; :::::::::::::::::::: | |
5364 | ;; :: | |
5527bf14 RH |
5365 | ;; :: Counted loop operations |
5366 | ;; :: | |
5367 | ;; :::::::::::::::::::: | |
5368 | ||
5369 | (define_expand "doloop_end" | |
5370 | [(use (match_operand 0 "" "")) ; loop pseudo | |
5371 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
5372 | (use (match_operand 2 "" "")) ; max iterations | |
5373 | (use (match_operand 3 "" "")) ; loop level | |
5374 | (use (match_operand 4 "" ""))] ; label | |
5375 | "" | |
5527bf14 RH |
5376 | { |
5377 | /* Only use cloop on innermost loops. */ | |
5378 | if (INTVAL (operands[3]) > 1) | |
5379 | FAIL; | |
5380 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
5381 | operands[4])); | |
5382 | DONE; | |
1d5d7a21 | 5383 | }) |
5527bf14 RH |
5384 | |
5385 | (define_insn "doloop_end_internal" | |
5386 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
5387 | (const_int 0)) | |
5388 | (label_ref (match_operand 1 "" "")) | |
5389 | (pc))) | |
5390 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
5391 | (plus:DI (match_dup 0) (const_int -1)) |
5392 | (match_dup 0)))] | |
5527bf14 RH |
5393 | "" |
5394 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 5395 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
5396 | (set_attr "predicable" "no")]) |
5397 | \f | |
5398 | ;; :::::::::::::::::::: | |
5399 | ;; :: | |
c65ebc55 JW |
5400 | ;; :: Set flag operations |
5401 | ;; :: | |
5402 | ;; :::::::::::::::::::: | |
5403 | ||
5404 | (define_expand "seq" | |
f2f90c63 | 5405 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5406 | "" |
f2f90c63 | 5407 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
5408 | |
5409 | (define_expand "sne" | |
f2f90c63 | 5410 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5411 | "" |
f2f90c63 | 5412 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
5413 | |
5414 | (define_expand "slt" | |
f2f90c63 | 5415 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5416 | "" |
f2f90c63 | 5417 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
5418 | |
5419 | (define_expand "sle" | |
f2f90c63 | 5420 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5421 | "" |
f2f90c63 | 5422 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
5423 | |
5424 | (define_expand "sgt" | |
f2f90c63 | 5425 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5426 | "" |
f2f90c63 | 5427 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
5428 | |
5429 | (define_expand "sge" | |
f2f90c63 | 5430 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5431 | "" |
f2f90c63 | 5432 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
5433 | |
5434 | (define_expand "sltu" | |
f2f90c63 | 5435 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5436 | "" |
f2f90c63 | 5437 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
5438 | |
5439 | (define_expand "sleu" | |
f2f90c63 | 5440 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5441 | "" |
f2f90c63 | 5442 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
5443 | |
5444 | (define_expand "sgtu" | |
f2f90c63 | 5445 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5446 | "" |
f2f90c63 | 5447 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
5448 | |
5449 | (define_expand "sgeu" | |
f2f90c63 | 5450 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5451 | "" |
f2f90c63 | 5452 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 5453 | |
e57b9d65 | 5454 | (define_expand "sunordered" |
f2f90c63 | 5455 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5456 | "" |
f2f90c63 | 5457 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
5458 | |
5459 | (define_expand "sordered" | |
f2f90c63 | 5460 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5461 | "" |
f2f90c63 | 5462 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 5463 | |
c65ebc55 JW |
5464 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
5465 | ;; efficient than mov/mov/cst/cst. | |
5466 | ||
0551c32d RH |
5467 | (define_insn_and_split "*sne_internal" |
5468 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5469 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5470 | (const_int 0)))] |
5471 | "" | |
5472 | "#" | |
c65ebc55 | 5473 | "reload_completed" |
f2f90c63 RH |
5474 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5475 | (set (match_dup 0) (const_int 1))) | |
5476 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5477 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 5478 | "" |
52e12ad0 | 5479 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 5480 | |
0551c32d RH |
5481 | (define_insn_and_split "*seq_internal" |
5482 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5483 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5484 | (const_int 0)))] |
5485 | "" | |
5486 | "#" | |
c65ebc55 | 5487 | "reload_completed" |
f2f90c63 RH |
5488 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5489 | (set (match_dup 0) (const_int 0))) | |
5490 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5491 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 5492 | "" |
52e12ad0 | 5493 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
5494 | \f |
5495 | ;; :::::::::::::::::::: | |
5496 | ;; :: | |
5497 | ;; :: Conditional move instructions. | |
5498 | ;; :: | |
5499 | ;; :::::::::::::::::::: | |
5500 | ||
5501 | ;; ??? Add movXXcc patterns? | |
5502 | ||
c65ebc55 JW |
5503 | ;; |
5504 | ;; DImode if_then_else patterns. | |
5505 | ;; | |
5506 | ||
75cdbeb8 | 5507 | (define_insn "*cmovdi_internal" |
f2f90c63 | 5508 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 5509 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 5510 | (if_then_else:DI |
f2f90c63 RH |
5511 | (match_operator 4 "predicate_operator" |
5512 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 5513 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 5514 | (const_int 0)]) |
f2f90c63 | 5515 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 5516 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 5517 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 5518 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 5519 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5520 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5521 | { gcc_unreachable (); } |
75cdbeb8 RH |
5522 | [(set_attr "predicable" "no")]) |
5523 | ||
5524 | (define_split | |
f2f90c63 | 5525 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 5526 | (if_then_else |
f2f90c63 RH |
5527 | (match_operator 4 "predicate_operator" |
5528 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 5529 | (const_int 0)]) |
f2f90c63 RH |
5530 | (match_operand 2 "move_operand" "") |
5531 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
5532 | "reload_completed" |
5533 | [(const_int 0)] | |
e5bde68a | 5534 | { |
21515593 RH |
5535 | bool emitted_something = false; |
5536 | rtx dest = operands[0]; | |
5537 | rtx srct = operands[2]; | |
5538 | rtx srcf = operands[3]; | |
5539 | rtx cond = operands[4]; | |
2f937369 | 5540 | |
21515593 | 5541 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 5542 | { |
21515593 RH |
5543 | ia64_emit_cond_move (dest, srct, cond); |
5544 | emitted_something = true; | |
e5bde68a | 5545 | } |
21515593 | 5546 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 5547 | { |
21515593 RH |
5548 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
5549 | VOIDmode, operands[1], const0_rtx); | |
5550 | ia64_emit_cond_move (dest, srcf, cond); | |
5551 | emitted_something = true; | |
3b572406 | 5552 | } |
2f937369 | 5553 | if (! emitted_something) |
f9974026 | 5554 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 5555 | DONE; |
1d5d7a21 | 5556 | }) |
c65ebc55 JW |
5557 | |
5558 | ;; Absolute value pattern. | |
5559 | ||
5560 | (define_insn "*absdi2_internal" | |
0551c32d | 5561 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5562 | (if_then_else:DI |
f2f90c63 RH |
5563 | (match_operator 4 "predicate_operator" |
5564 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5565 | (const_int 0)]) |
0551c32d RH |
5566 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
5567 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5568 | "" |
e5bde68a | 5569 | "#" |
52e12ad0 | 5570 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5571 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5572 | |
5573 | (define_split | |
5574 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 5575 | (if_then_else:DI |
f2f90c63 RH |
5576 | (match_operator 4 "predicate_operator" |
5577 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5578 | (const_int 0)]) |
0551c32d RH |
5579 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5580 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5581 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5582 | [(cond_exec | |
5583 | (match_dup 4) | |
5584 | (set (match_dup 0) | |
5585 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
5586 | "") |
5587 | ||
e5bde68a RH |
5588 | (define_split |
5589 | [(set (match_operand:DI 0 "register_operand" "") | |
5590 | (if_then_else:DI | |
f2f90c63 RH |
5591 | (match_operator 4 "predicate_operator" |
5592 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5593 | (const_int 0)]) |
0551c32d RH |
5594 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5595 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5596 | "reload_completed" |
5597 | [(cond_exec | |
5598 | (match_dup 4) | |
5599 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
5600 | (cond_exec | |
5601 | (match_dup 5) | |
5602 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5603 | { |
5604 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5605 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5606 | }) |
c65ebc55 JW |
5607 | |
5608 | ;; | |
5609 | ;; SImode if_then_else patterns. | |
5610 | ;; | |
5611 | ||
75cdbeb8 | 5612 | (define_insn "*cmovsi_internal" |
f2f90c63 | 5613 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 5614 | (if_then_else:SI |
f2f90c63 RH |
5615 | (match_operator 4 "predicate_operator" |
5616 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 5617 | (const_int 0)]) |
f2f90c63 | 5618 | (match_operand:SI 2 "move_operand" |
3b572406 | 5619 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 5620 | (match_operand:SI 3 "move_operand" |
3b572406 | 5621 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 5622 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5623 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5624 | { gcc_unreachable (); } |
3b572406 | 5625 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
5626 | |
5627 | (define_insn "*abssi2_internal" | |
0551c32d | 5628 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5629 | (if_then_else:SI |
f2f90c63 RH |
5630 | (match_operator 4 "predicate_operator" |
5631 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5632 | (const_int 0)]) |
0551c32d RH |
5633 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
5634 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5635 | "" |
e5bde68a | 5636 | "#" |
52e12ad0 | 5637 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5638 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5639 | |
5640 | (define_split | |
5641 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 5642 | (if_then_else:SI |
f2f90c63 RH |
5643 | (match_operator 4 "predicate_operator" |
5644 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5645 | (const_int 0)]) |
0551c32d RH |
5646 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5647 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5648 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5649 | [(cond_exec | |
5650 | (match_dup 4) | |
5651 | (set (match_dup 0) | |
5652 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
5653 | "") |
5654 | ||
e5bde68a RH |
5655 | (define_split |
5656 | [(set (match_operand:SI 0 "register_operand" "") | |
5657 | (if_then_else:SI | |
f2f90c63 RH |
5658 | (match_operator 4 "predicate_operator" |
5659 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5660 | (const_int 0)]) |
0551c32d RH |
5661 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5662 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5663 | "reload_completed" |
5664 | [(cond_exec | |
5665 | (match_dup 4) | |
5666 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
5667 | (cond_exec | |
5668 | (match_dup 5) | |
5669 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5670 | { |
5671 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5672 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5673 | }) |
e5bde68a | 5674 | |
7dcc803e | 5675 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
5676 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5677 | (match_operator:SI 5 "condop_operator" | |
5678 | [(if_then_else:SI | |
5679 | (match_operator 6 "predicate_operator" | |
5680 | [(match_operand:BI 1 "register_operand" "c") | |
5681 | (const_int 0)]) | |
5682 | (match_operand:SI 2 "gr_register_operand" "r") | |
5683 | (match_operand:SI 3 "gr_register_operand" "r")) | |
5684 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
5685 | "" | |
5686 | "#" | |
acb0638d BS |
5687 | "reload_completed" |
5688 | [(cond_exec | |
5689 | (match_dup 6) | |
5690 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
5691 | (cond_exec | |
5692 | (match_dup 7) | |
5693 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
5694 | { |
5695 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5696 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5697 | } |
7dcc803e BS |
5698 | [(set_attr "itanium_class" "ialu") |
5699 | (set_attr "predicable" "no")]) | |
5700 | ||
acb0638d | 5701 | |
7dcc803e | 5702 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
5703 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5704 | (match_operator:SI 5 "condop_operator" | |
5705 | [(match_operand:SI 4 "gr_register_operand" "r") | |
5706 | (if_then_else:SI | |
5707 | (match_operator 6 "predicate_operator" | |
5708 | [(match_operand:BI 1 "register_operand" "c") | |
5709 | (const_int 0)]) | |
5710 | (match_operand:SI 2 "gr_register_operand" "r") | |
5711 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
5712 | "" | |
5713 | "#" | |
acb0638d BS |
5714 | "reload_completed" |
5715 | [(cond_exec | |
5716 | (match_dup 6) | |
5717 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
5718 | (cond_exec | |
5719 | (match_dup 7) | |
5720 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
5721 | { |
5722 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5723 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5724 | } |
7dcc803e BS |
5725 | [(set_attr "itanium_class" "ialu") |
5726 | (set_attr "predicable" "no")]) | |
acb0638d | 5727 | |
c65ebc55 JW |
5728 | \f |
5729 | ;; :::::::::::::::::::: | |
5730 | ;; :: | |
5731 | ;; :: Call and branch instructions | |
5732 | ;; :: | |
5733 | ;; :::::::::::::::::::: | |
5734 | ||
5735 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
5736 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
5737 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
5738 | ;; registers used as operands. | |
5739 | ||
5740 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
5741 | ;; is supplied for the sake of some RISC machines which need to put this | |
5742 | ;; information into the assembler code; they can put it in the RTL instead of | |
5743 | ;; operand 1. | |
5744 | ||
5745 | (define_expand "call" | |
5746 | [(use (match_operand:DI 0 "" "")) | |
5747 | (use (match_operand 1 "" "")) | |
5748 | (use (match_operand 2 "" "")) | |
5749 | (use (match_operand 3 "" ""))] | |
5750 | "" | |
c65ebc55 | 5751 | { |
599aedd9 | 5752 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 5753 | DONE; |
1d5d7a21 | 5754 | }) |
c65ebc55 | 5755 | |
2ed4af6f RH |
5756 | (define_expand "sibcall" |
5757 | [(use (match_operand:DI 0 "" "")) | |
5758 | (use (match_operand 1 "" "")) | |
5759 | (use (match_operand 2 "" "")) | |
5760 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 5761 | "" |
c65ebc55 | 5762 | { |
599aedd9 | 5763 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 5764 | DONE; |
1d5d7a21 | 5765 | }) |
c65ebc55 | 5766 | |
c65ebc55 | 5767 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
5768 | ;; register in which the value is returned. There are three more operands, |
5769 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 5770 | ;; increased by one). |
2ed4af6f | 5771 | ;; |
c65ebc55 JW |
5772 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
5773 | ||
5774 | (define_expand "call_value" | |
5775 | [(use (match_operand 0 "" "")) | |
5776 | (use (match_operand:DI 1 "" "")) | |
5777 | (use (match_operand 2 "" "")) | |
5778 | (use (match_operand 3 "" "")) | |
5779 | (use (match_operand 4 "" ""))] | |
5780 | "" | |
c65ebc55 | 5781 | { |
599aedd9 | 5782 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 5783 | DONE; |
1d5d7a21 | 5784 | }) |
c65ebc55 | 5785 | |
2ed4af6f RH |
5786 | (define_expand "sibcall_value" |
5787 | [(use (match_operand 0 "" "")) | |
5788 | (use (match_operand:DI 1 "" "")) | |
5789 | (use (match_operand 2 "" "")) | |
5790 | (use (match_operand 3 "" "")) | |
5791 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 5792 | "" |
c65ebc55 | 5793 | { |
599aedd9 | 5794 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 5795 | DONE; |
1d5d7a21 | 5796 | }) |
c65ebc55 | 5797 | |
c65ebc55 JW |
5798 | ;; Call subroutine returning any type. |
5799 | ||
5800 | (define_expand "untyped_call" | |
5801 | [(parallel [(call (match_operand 0 "" "") | |
5802 | (const_int 0)) | |
5803 | (match_operand 1 "" "") | |
5804 | (match_operand 2 "" "")])] | |
5805 | "" | |
c65ebc55 JW |
5806 | { |
5807 | int i; | |
5808 | ||
5809 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
5810 | ||
5811 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
5812 | { | |
5813 | rtx set = XVECEXP (operands[2], 0, i); | |
5814 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
5815 | } | |
5816 | ||
5817 | /* The optimizer does not know that the call sets the function value | |
5818 | registers we stored in the result block. We avoid problems by | |
5819 | claiming that all hard registers are used and clobbered at this | |
5820 | point. */ | |
5821 | emit_insn (gen_blockage ()); | |
5822 | ||
5823 | DONE; | |
1d5d7a21 | 5824 | }) |
c65ebc55 | 5825 | |
599aedd9 RH |
5826 | (define_insn "call_nogp" |
5827 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5828 | (const_int 0)) | |
5829 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 5830 | "" |
599aedd9 | 5831 | "br.call%+.many %1 = %0" |
52e12ad0 | 5832 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5833 | |
599aedd9 | 5834 | (define_insn "call_value_nogp" |
75293ad6 | 5835 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5836 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i")) |
5837 | (const_int 0))) | |
5838 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 5839 | "" |
599aedd9 | 5840 | "br.call%+.many %2 = %1" |
52e12ad0 | 5841 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5842 | |
599aedd9 RH |
5843 | (define_insn "sibcall_nogp" |
5844 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5845 | (const_int 0))] | |
2ed4af6f RH |
5846 | "" |
5847 | "br%+.many %0" | |
52e12ad0 | 5848 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5849 | |
599aedd9 | 5850 | (define_insn "call_gp" |
c8083186 | 5851 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) |
599aedd9 RH |
5852 | (const_int 1)) |
5853 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
5854 | (clobber (match_scratch:DI 2 "=&r,X")) | |
5855 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 5856 | "" |
599aedd9 | 5857 | "#" |
52e12ad0 | 5858 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5859 | |
599aedd9 RH |
5860 | ;; Irritatingly, we don't have access to INSN within the split body. |
5861 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
5862 | (define_split | |
5863 | [(call (mem (match_operand 0 "call_operand" "")) | |
5864 | (const_int 1)) | |
5865 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5866 | (clobber (match_scratch:DI 2 "")) | |
5867 | (clobber (match_scratch:DI 3 ""))] | |
5868 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5869 | [(const_int 0)] | |
5870 | { | |
5871 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5872 | operands[3], true, false); | |
5873 | DONE; | |
5874 | }) | |
5875 | ||
5876 | (define_split | |
5877 | [(call (mem (match_operand 0 "call_operand" "")) | |
5878 | (const_int 1)) | |
5879 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5880 | (clobber (match_scratch:DI 2 "")) | |
5881 | (clobber (match_scratch:DI 3 ""))] | |
5882 | "reload_completed" | |
5883 | [(const_int 0)] | |
5884 | { | |
5885 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5886 | operands[3], false, false); | |
5887 | DONE; | |
5888 | }) | |
5889 | ||
5890 | (define_insn "call_value_gp" | |
75293ad6 | 5891 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5892 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i")) |
5893 | (const_int 1))) | |
5894 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
5895 | (clobber (match_scratch:DI 3 "=&r,X")) | |
5896 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 5897 | "" |
599aedd9 | 5898 | "#" |
52e12ad0 | 5899 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5900 | |
599aedd9 RH |
5901 | (define_split |
5902 | [(set (match_operand 0 "" "") | |
5903 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5904 | (const_int 1))) | |
5905 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5906 | (clobber (match_scratch:DI 3 "")) | |
5907 | (clobber (match_scratch:DI 4 ""))] | |
5908 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5909 | [(const_int 0)] | |
5910 | { | |
5911 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5912 | operands[4], true, false); | |
5913 | DONE; | |
5914 | }) | |
5915 | ||
5916 | (define_split | |
5917 | [(set (match_operand 0 "" "") | |
5918 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5919 | (const_int 1))) | |
5920 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5921 | (clobber (match_scratch:DI 3 "")) | |
5922 | (clobber (match_scratch:DI 4 ""))] | |
5923 | "reload_completed" | |
5924 | [(const_int 0)] | |
5925 | { | |
5926 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5927 | operands[4], false, false); | |
5928 | DONE; | |
5929 | }) | |
5930 | ||
5931 | (define_insn_and_split "sibcall_gp" | |
5932 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) | |
5933 | (const_int 1)) | |
5934 | (clobber (match_scratch:DI 1 "=&r,X")) | |
5935 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 5936 | "" |
599aedd9 RH |
5937 | "#" |
5938 | "reload_completed" | |
5939 | [(const_int 0)] | |
5940 | { | |
5941 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
5942 | operands[2], true, true); | |
5943 | DONE; | |
5944 | } | |
52e12ad0 | 5945 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 5946 | |
c65ebc55 JW |
5947 | (define_insn "return_internal" |
5948 | [(return) | |
5949 | (use (match_operand:DI 0 "register_operand" "b"))] | |
5950 | "" | |
5951 | "br.ret.sptk.many %0" | |
52e12ad0 | 5952 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5953 | |
5954 | (define_insn "return" | |
5955 | [(return)] | |
5956 | "ia64_direct_return ()" | |
5957 | "br.ret.sptk.many rp" | |
52e12ad0 | 5958 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 5959 | |
6b6c1201 | 5960 | (define_insn "*return_true" |
c65ebc55 | 5961 | [(set (pc) |
6b6c1201 | 5962 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5963 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5964 | (const_int 0)]) |
c65ebc55 JW |
5965 | (return) |
5966 | (pc)))] | |
5967 | "ia64_direct_return ()" | |
13da91fd | 5968 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 5969 | [(set_attr "itanium_class" "br") |
e5bde68a | 5970 | (set_attr "predicable" "no")]) |
c65ebc55 | 5971 | |
6b6c1201 | 5972 | (define_insn "*return_false" |
c65ebc55 | 5973 | [(set (pc) |
6b6c1201 | 5974 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5975 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5976 | (const_int 0)]) |
c65ebc55 JW |
5977 | (pc) |
5978 | (return)))] | |
5979 | "ia64_direct_return ()" | |
13da91fd | 5980 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 5981 | [(set_attr "itanium_class" "br") |
e5bde68a | 5982 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5983 | |
5984 | (define_insn "jump" | |
5985 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
5986 | "" | |
5987 | "br %l0" | |
52e12ad0 | 5988 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5989 | |
5990 | (define_insn "indirect_jump" | |
5991 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
5992 | "" | |
5993 | "br %0" | |
52e12ad0 | 5994 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5995 | |
5996 | (define_expand "tablejump" | |
340f7e7c RH |
5997 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
5998 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 5999 | "" |
c65ebc55 | 6000 | { |
340f7e7c RH |
6001 | rtx op0 = operands[0]; |
6002 | rtx addr; | |
6003 | ||
6004 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
6005 | element into a register without bothering to see whether that | |
6006 | is necessary given the operand predicate. Check for MEM just | |
6007 | in case someone fixes this. */ | |
6008 | if (GET_CODE (op0) == MEM) | |
6009 | addr = XEXP (op0, 0); | |
6010 | else | |
6011 | { | |
6012 | /* Otherwise, cheat and guess that the previous insn in the | |
6013 | stream was the memory load. Grab the address from that. | |
6014 | Note we have to momentarily pop out of the sequence started | |
6015 | by the insn-emit wrapper in order to grab the last insn. */ | |
6016 | rtx last, set; | |
6017 | ||
6018 | end_sequence (); | |
6019 | last = get_last_insn (); | |
6020 | start_sequence (); | |
6021 | set = single_set (last); | |
6022 | ||
e820471b NS |
6023 | gcc_assert (rtx_equal_p (SET_DEST (set), op0) |
6024 | && GET_CODE (SET_SRC (set)) == MEM); | |
340f7e7c | 6025 | addr = XEXP (SET_SRC (set), 0); |
e820471b | 6026 | gcc_assert (!rtx_equal_p (addr, op0)); |
340f7e7c | 6027 | } |
c65ebc55 | 6028 | |
340f7e7c RH |
6029 | /* Jump table elements are stored pc-relative. That is, a displacement |
6030 | from the entry to the label. Thus to convert to an absolute address | |
6031 | we add the address of the memory from which the value is loaded. */ | |
6032 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
6033 | NULL_RTX, 1, OPTAB_DIRECT); | |
6034 | }) | |
c65ebc55 | 6035 | |
340f7e7c | 6036 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
6037 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
6038 | (use (label_ref (match_operand 1 "" "")))] | |
6039 | "" | |
6040 | "br %0" | |
52e12ad0 | 6041 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
6042 | |
6043 | \f | |
6044 | ;; :::::::::::::::::::: | |
6045 | ;; :: | |
6046 | ;; :: Prologue and Epilogue instructions | |
6047 | ;; :: | |
6048 | ;; :::::::::::::::::::: | |
6049 | ||
6050 | (define_expand "prologue" | |
6051 | [(const_int 1)] | |
6052 | "" | |
c65ebc55 JW |
6053 | { |
6054 | ia64_expand_prologue (); | |
6055 | DONE; | |
1d5d7a21 | 6056 | }) |
c65ebc55 JW |
6057 | |
6058 | (define_expand "epilogue" | |
2ed4af6f RH |
6059 | [(return)] |
6060 | "" | |
2ed4af6f RH |
6061 | { |
6062 | ia64_expand_epilogue (0); | |
6063 | DONE; | |
1d5d7a21 | 6064 | }) |
2ed4af6f RH |
6065 | |
6066 | (define_expand "sibcall_epilogue" | |
6067 | [(return)] | |
c65ebc55 | 6068 | "" |
c65ebc55 | 6069 | { |
2ed4af6f | 6070 | ia64_expand_epilogue (1); |
c65ebc55 | 6071 | DONE; |
1d5d7a21 | 6072 | }) |
c65ebc55 JW |
6073 | |
6074 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
6075 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
6076 | ||
6077 | (define_insn "prologue_allocate_stack" | |
6078 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
6079 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 6080 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 6081 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
6082 | (match_dup 3))] |
6083 | "" | |
6084 | "@ | |
1d5d7a21 RH |
6085 | add %0 = %1, %2 |
6086 | adds %0 = %2, %1 | |
6087 | addl %0 = %2, %1" | |
52e12ad0 | 6088 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
6089 | |
6090 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
6091 | ;; stack accesses. This is similar to movdi plus the extra set. | |
6092 | ||
6093 | (define_insn "epilogue_deallocate_stack" | |
6094 | [(set (match_operand:DI 0 "register_operand" "=r") | |
6095 | (match_operand:DI 1 "register_operand" "+r")) | |
6096 | (set (match_dup 1) (match_dup 1))] | |
6097 | "" | |
6098 | "mov %0 = %1" | |
52e12ad0 | 6099 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 6100 | |
1d5d7a21 RH |
6101 | ;; As USE insns aren't meaningful after reload, this is used instead |
6102 | ;; to prevent deleting instructions setting registers for EH handling | |
6103 | (define_insn "prologue_use" | |
6104 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
6105 | UNSPEC_PROLOGUE_USE)] | |
6106 | "" | |
6107 | "" | |
6108 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
6109 | (set_attr "predicable" "no") |
6110 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 6111 | |
c65ebc55 JW |
6112 | ;; Allocate a new register frame. |
6113 | ||
6114 | (define_insn "alloc" | |
6115 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 6116 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
6117 | (use (match_operand:DI 1 "const_int_operand" "i")) |
6118 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
6119 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
6120 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
6121 | "" | |
6122 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 6123 | [(set_attr "itanium_class" "syst_m0") |
68e11b42 JW |
6124 | (set_attr "predicable" "no") |
6125 | (set_attr "first_insn" "yes")]) | |
c65ebc55 | 6126 | |
97e242b0 RH |
6127 | ;; Modifies ar.unat |
6128 | (define_expand "gr_spill" | |
870f9ec0 RH |
6129 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
6130 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
6131 | (match_operand:DI 2 "const_int_operand" "")] |
6132 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 6133 | (clobber (match_dup 3))])] |
97e242b0 | 6134 | "" |
870f9ec0 | 6135 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 6136 | |
870f9ec0 | 6137 | (define_insn "gr_spill_internal" |
b6fb7d46 | 6138 | [(set (match_operand:DI 0 "destination_operand" "=m") |
870f9ec0 | 6139 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
6140 | (match_operand:DI 2 "const_int_operand" "")] |
6141 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 6142 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 6143 | "" |
2130b7fb | 6144 | { |
1d5d7a21 RH |
6145 | /* Note that we use a C output pattern here to avoid the predicate |
6146 | being automatically added before the .mem.offset directive. */ | |
6147 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
6148 | } | |
52e12ad0 | 6149 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 6150 | |
97e242b0 RH |
6151 | ;; Reads ar.unat |
6152 | (define_expand "gr_restore" | |
870f9ec0 RH |
6153 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
6154 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
6155 | (match_operand:DI 2 "const_int_operand" "")] |
6156 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 6157 | (use (match_dup 3))])] |
97e242b0 | 6158 | "" |
870f9ec0 | 6159 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 6160 | |
870f9ec0 | 6161 | (define_insn "gr_restore_internal" |
c65ebc55 | 6162 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 6163 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
6164 | (match_operand:DI 2 "const_int_operand" "")] |
6165 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 6166 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 6167 | "" |
1d5d7a21 | 6168 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 6169 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
6170 | |
6171 | (define_insn "fr_spill" | |
b6fb7d46 | 6172 | [(set (match_operand:XF 0 "destination_operand" "=m") |
02befdf4 | 6173 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] |
086c0f96 | 6174 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
6175 | "" |
6176 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 6177 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
6178 | |
6179 | (define_insn "fr_restore" | |
02befdf4 ZW |
6180 | [(set (match_operand:XF 0 "register_operand" "=f") |
6181 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 6182 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
6183 | "" |
6184 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 6185 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 6186 | |
0024a804 JW |
6187 | ;; ??? The explicit stop is not ideal. It would be better if |
6188 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
6189 | ;; fixed later. This avoids an RSE DV. | |
6190 | ||
0c96007e AM |
6191 | (define_insn "bsp_value" |
6192 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 6193 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 6194 | "" |
582d11e6 JW |
6195 | "* |
6196 | { | |
6197 | return \";;\;%,mov %0 = ar.bsp\"; | |
6198 | }" | |
52e12ad0 | 6199 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
6200 | |
6201 | (define_insn "set_bsp" | |
086c0f96 RH |
6202 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
6203 | UNSPECV_SET_BSP)] | |
0c96007e | 6204 | "" |
1d5d7a21 RH |
6205 | "flushrs |
6206 | mov r19=ar.rsc | |
6207 | ;; | |
6208 | and r19=0x1c,r19 | |
6209 | ;; | |
6210 | mov ar.rsc=r19 | |
6211 | ;; | |
6212 | mov ar.bspstore=%0 | |
6213 | ;; | |
6214 | or r19=0x3,r19 | |
6215 | ;; | |
6216 | loadrs | |
6217 | invala | |
6218 | ;; | |
6219 | mov ar.rsc=r19" | |
52e12ad0 | 6220 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 6221 | (set_attr "predicable" "no")]) |
ce152ef8 | 6222 | |
0024a804 JW |
6223 | ;; ??? The explicit stops are not ideal. It would be better if |
6224 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
6225 | ;; fixed later. This avoids an RSE DV. | |
6226 | ||
ce152ef8 | 6227 | (define_insn "flushrs" |
086c0f96 | 6228 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 6229 | "" |
0024a804 | 6230 | ";;\;flushrs\;;;" |
582d11e6 JW |
6231 | [(set_attr "itanium_class" "rse_m") |
6232 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
6233 | \f |
6234 | ;; :::::::::::::::::::: | |
6235 | ;; :: | |
6236 | ;; :: Miscellaneous instructions | |
6237 | ;; :: | |
6238 | ;; :::::::::::::::::::: | |
6239 | ||
839a4992 | 6240 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
6241 | ;; be emitting ";;" to force a break in the instruction packing. |
6242 | ||
6243 | ;; No operation, needed in case the user uses -g but not -O. | |
6244 | (define_insn "nop" | |
6245 | [(const_int 0)] | |
6246 | "" | |
6247 | "nop 0" | |
30028c85 | 6248 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 6249 | |
2130b7fb BS |
6250 | (define_insn "nop_m" |
6251 | [(const_int 1)] | |
6252 | "" | |
6253 | "nop.m 0" | |
6254 | [(set_attr "itanium_class" "nop_m")]) | |
6255 | ||
6256 | (define_insn "nop_i" | |
6257 | [(const_int 2)] | |
6258 | "" | |
6259 | "nop.i 0" | |
6260 | [(set_attr "itanium_class" "nop_i")]) | |
6261 | ||
6262 | (define_insn "nop_f" | |
6263 | [(const_int 3)] | |
6264 | "" | |
6265 | "nop.f 0" | |
6266 | [(set_attr "itanium_class" "nop_f")]) | |
6267 | ||
6268 | (define_insn "nop_b" | |
6269 | [(const_int 4)] | |
6270 | "" | |
6271 | "nop.b 0" | |
6272 | [(set_attr "itanium_class" "nop_b")]) | |
6273 | ||
6274 | (define_insn "nop_x" | |
6275 | [(const_int 5)] | |
6276 | "" | |
6277 | "" | |
fa978426 AS |
6278 | [(set_attr "itanium_class" "nop_x") |
6279 | (set_attr "empty" "yes")]) | |
2130b7fb | 6280 | |
30028c85 VM |
6281 | ;; The following insn will be never generated. It is used only by |
6282 | ;; insn scheduler to change state before advancing cycle. | |
6283 | (define_insn "pre_cycle" | |
6284 | [(const_int 6)] | |
6285 | "" | |
6286 | "" | |
6287 | [(set_attr "itanium_class" "pre_cycle")]) | |
6288 | ||
2130b7fb | 6289 | (define_insn "bundle_selector" |
086c0f96 | 6290 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 6291 | "" |
1d5d7a21 | 6292 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
6293 | [(set_attr "itanium_class" "ignore") |
6294 | (set_attr "predicable" "no")]) | |
6295 | ||
c65ebc55 JW |
6296 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
6297 | ;; point. | |
6298 | (define_insn "blockage" | |
086c0f96 | 6299 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
6300 | "" |
6301 | "" | |
52e12ad0 | 6302 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 6303 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
6304 | |
6305 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
6306 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
6307 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
6308 | "" |
6309 | ";;" | |
52e12ad0 | 6310 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
6311 | (set_attr "predicable" "no") |
6312 | (set_attr "empty" "yes")]) | |
c65ebc55 | 6313 | |
26406018 RH |
6314 | (define_expand "trap" |
6315 | [(trap_if (const_int 1) (const_int 0))] | |
6316 | "" | |
6317 | "") | |
6318 | ||
6319 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
6320 | ;; produces worse code that setting the slot type to A. | |
6321 | ||
6322 | (define_insn "*trap" | |
6323 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
6324 | "" | |
6325 | "break %0" | |
048d0d36 | 6326 | [(set_attr "itanium_class" "chk_s_i")]) |
26406018 RH |
6327 | |
6328 | (define_expand "conditional_trap" | |
6329 | [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] | |
6330 | "" | |
6331 | { | |
6332 | operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode); | |
6333 | }) | |
6334 | ||
6335 | (define_insn "*conditional_trap" | |
6336 | [(trap_if (match_operator 0 "predicate_operator" | |
6337 | [(match_operand:BI 1 "register_operand" "c") | |
6338 | (const_int 0)]) | |
6339 | (match_operand 2 "const_int_operand" ""))] | |
6340 | "" | |
5cf63e3f | 6341 | "(%J0) break %2" |
048d0d36 | 6342 | [(set_attr "itanium_class" "chk_s_i") |
26406018 RH |
6343 | (set_attr "predicable" "no")]) |
6344 | ||
f12f25a7 | 6345 | (define_insn "break_f" |
086c0f96 | 6346 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
6347 | "" |
6348 | "break.f 0" | |
6349 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
6350 | |
6351 | (define_insn "prefetch" | |
6352 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
6353 | (match_operand:DI 1 "const_int_operand" "n") | |
6354 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6355 | "" | |
6356 | { | |
6357 | static const char * const alt[2][4] = { | |
b3656137 | 6358 | { |
92cbea22 L |
6359 | "%,lfetch.nta [%0]", |
6360 | "%,lfetch.nt1 [%0]", | |
6361 | "%,lfetch.nt2 [%0]", | |
6362 | "%,lfetch [%0]" | |
b3656137 KG |
6363 | }, |
6364 | { | |
92cbea22 L |
6365 | "%,lfetch.excl.nta [%0]", |
6366 | "%,lfetch.excl.nt1 [%0]", | |
6367 | "%,lfetch.excl.nt2 [%0]", | |
6368 | "%,lfetch.excl [%0]" | |
b3656137 | 6369 | } |
44eca121 JJ |
6370 | }; |
6371 | int i = (INTVAL (operands[1])); | |
6372 | int j = (INTVAL (operands[2])); | |
6373 | ||
e820471b NS |
6374 | gcc_assert (i == 0 || i == 1); |
6375 | gcc_assert (j >= 0 && j <= 3); | |
44eca121 JJ |
6376 | return alt[i][j]; |
6377 | } | |
6378 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
6379 | \f |
6380 | ;; Non-local goto support. | |
6381 | ||
6382 | (define_expand "save_stack_nonlocal" | |
6383 | [(use (match_operand:OI 0 "memory_operand" "")) | |
6384 | (use (match_operand:DI 1 "register_operand" ""))] | |
6385 | "" | |
c65ebc55 JW |
6386 | { |
6387 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
6388 | \"__ia64_save_stack_nonlocal\"), | |
6389 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
6390 | operands[1], Pmode); | |
6391 | DONE; | |
1d5d7a21 | 6392 | }) |
c65ebc55 JW |
6393 | |
6394 | (define_expand "nonlocal_goto" | |
6395 | [(use (match_operand 0 "general_operand" "")) | |
6396 | (use (match_operand 1 "general_operand" "")) | |
6397 | (use (match_operand 2 "general_operand" "")) | |
6398 | (use (match_operand 3 "general_operand" ""))] | |
6399 | "" | |
c65ebc55 | 6400 | { |
c65ebc55 | 6401 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 6402 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 6403 | operands[1], Pmode, |
c65ebc55 | 6404 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 6405 | operands[3], Pmode); |
c65ebc55 JW |
6406 | emit_barrier (); |
6407 | DONE; | |
1d5d7a21 | 6408 | }) |
c65ebc55 | 6409 | |
b39eb2f9 RH |
6410 | (define_insn_and_split "builtin_setjmp_receiver" |
6411 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 6412 | "" |
b39eb2f9 RH |
6413 | "#" |
6414 | "reload_completed" | |
6415 | [(const_int 0)] | |
97e242b0 | 6416 | { |
599aedd9 | 6417 | ia64_reload_gp (); |
c65ebc55 | 6418 | DONE; |
1d5d7a21 | 6419 | }) |
c65ebc55 | 6420 | |
0c96007e AM |
6421 | (define_expand "eh_epilogue" |
6422 | [(use (match_operand:DI 0 "register_operand" "r")) | |
6423 | (use (match_operand:DI 1 "register_operand" "r")) | |
6424 | (use (match_operand:DI 2 "register_operand" "r"))] | |
6425 | "" | |
0c96007e AM |
6426 | { |
6427 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
6428 | rtx sp = gen_rtx_REG (Pmode, 9); | |
6429 | ||
6430 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
6431 | { | |
6432 | emit_move_insn (bsp, operands[0]); | |
6433 | operands[0] = bsp; | |
6434 | } | |
6435 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
6436 | { | |
6437 | emit_move_insn (sp, operands[2]); | |
6438 | operands[2] = sp; | |
6439 | } | |
6440 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
6441 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
6442 | ||
6443 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
6444 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 6445 | }) |
9525c690 JW |
6446 | \f |
6447 | ;; Builtin apply support. | |
6448 | ||
6449 | (define_expand "restore_stack_nonlocal" | |
6450 | [(use (match_operand:DI 0 "register_operand" "")) | |
6451 | (use (match_operand:OI 1 "memory_operand" ""))] | |
6452 | "" | |
9525c690 JW |
6453 | { |
6454 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 6455 | "__ia64_restore_stack_nonlocal"), |
9525c690 JW |
6456 | 0, VOIDmode, 1, |
6457 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
6458 | DONE; | |
1d5d7a21 | 6459 | }) |
9525c690 | 6460 | |
e5bde68a RH |
6461 | \f |
6462 | ;; Predication. | |
6463 | ||
6464 | (define_cond_exec | |
6465 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 6466 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
6467 | (const_int 0)])] |
6468 | "" | |
6469 | "(%J0)") | |
3b572406 RH |
6470 | |
6471 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 6472 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 6473 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 6474 | "" |
054451ea | 6475 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 6476 | [(set_attr "itanium_class" "ignore") |
3b572406 | 6477 | (set_attr "predicable" "no")]) |
ca3920ad JW |
6478 | |
6479 | (define_insn "safe_across_calls_all" | |
086c0f96 | 6480 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
6481 | "" |
6482 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 6483 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6484 | (set_attr "predicable" "no")]) |
6485 | ||
6486 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 6487 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 6488 | "" |
ca3920ad | 6489 | { |
1bc7c5b6 | 6490 | emit_safe_across_calls (); |
1d5d7a21 RH |
6491 | return ""; |
6492 | } | |
52e12ad0 | 6493 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6494 | (set_attr "predicable" "no")]) |
6495 | ||
27a9b99d | 6496 | ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit |
6dd12198 SE |
6497 | ;; pointer. This is used by the HP-UX 32 bit mode. |
6498 | ||
6499 | (define_insn "ptr_extend" | |
6500 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
6501 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
6502 | UNSPEC_ADDP4))] | |
6dd12198 SE |
6503 | "" |
6504 | "addp4 %0 = 0,%1" | |
6505 | [(set_attr "itanium_class" "ialu")]) | |
6506 | ||
e206a74f SE |
6507 | ;; |
6508 | ;; Optimizations for ptr_extend | |
6509 | ||
36c216e5 | 6510 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
6511 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6512 | (unspec:DI | |
6513 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
6514 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 6515 | UNSPEC_ADDP4))] |
08744705 | 6516 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6517 | "addp4 %0 = %2, %1" |
6518 | [(set_attr "itanium_class" "ialu")]) | |
6519 | ||
6520 | (define_insn "*ptr_extend_plus_2" | |
6521 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
6522 | (unspec:DI | |
6523 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
6524 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 6525 | UNSPEC_ADDP4))] |
08744705 | 6526 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6527 | "addp4 %0 = %1, %2" |
6528 | [(set_attr "itanium_class" "ialu")]) | |
f61134e8 | 6529 | |
d26afa4f SE |
6530 | ;; |
6531 | ;; Get instruction pointer | |
6532 | ||
6533 | (define_insn "ip_value" | |
6534 | [(set (match_operand:DI 0 "register_operand" "=r") | |
6535 | (pc))] | |
6536 | "" | |
6537 | "mov %0 = ip" | |
6538 | [(set_attr "itanium_class" "ialu")]) | |
6539 | ||
f61134e8 RH |
6540 | ;; Vector operations |
6541 | (include "vect.md") | |
af795c3c RH |
6542 | ;; Atomic operations |
6543 | (include "sync.md") |