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c65ebc55 | 1 | ;; IA-64 Machine description template |
ff848f0e | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
c65ebc55 JW |
4 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
5 | ;; David Mosberger <davidm@hpl.hp.com>. | |
6 | ||
3bed2930 | 7 | ;; This file is part of GCC. |
c65ebc55 | 8 | |
3bed2930 | 9 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 10 | ;; it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | ;; the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
12 | ;; any later version. |
13 | ||
3bed2930 | 14 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
18 | ||
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
c65ebc55 JW |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
086c0f96 | 51 | (define_constants |
7b6e506e RH |
52 | [; Relocations |
53 | (UNSPEC_LTOFF_DTPMOD 0) | |
54 | (UNSPEC_LTOFF_DTPREL 1) | |
55 | (UNSPEC_DTPREL 2) | |
56 | (UNSPEC_LTOFF_TPREL 3) | |
57 | (UNSPEC_TPREL 4) | |
5e6c8b64 | 58 | (UNSPEC_DTPMOD 5) |
7b6e506e RH |
59 | |
60 | (UNSPEC_LD_BASE 9) | |
61 | (UNSPEC_GR_SPILL 10) | |
62 | (UNSPEC_GR_RESTORE 11) | |
63 | (UNSPEC_FR_SPILL 12) | |
64 | (UNSPEC_FR_RESTORE 13) | |
65 | (UNSPEC_FR_RECIP_APPROX 14) | |
66 | (UNSPEC_PRED_REL_MUTEX 15) | |
c407570a | 67 | (UNSPEC_GETF_EXP 16) |
7b6e506e RH |
68 | (UNSPEC_PIC_CALL 17) |
69 | (UNSPEC_MF 18) | |
70 | (UNSPEC_CMPXCHG_ACQ 19) | |
71 | (UNSPEC_FETCHADD_ACQ 20) | |
72 | (UNSPEC_BSP_VALUE 21) | |
73 | (UNSPEC_FLUSHRS 22) | |
74 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
75 | (UNSPEC_ADDP4 24) |
76 | (UNSPEC_PROLOGUE_USE 25) | |
af1e5518 | 77 | (UNSPEC_RET_ADDR 26) |
b38ba463 ZW |
78 | (UNSPEC_SETF_EXP 27) |
79 | (UNSPEC_FR_SQRT_RECIP_APPROX 28) | |
f526a3c8 | 80 | (UNSPEC_SHRP 29) |
046625fa | 81 | (UNSPEC_COPYSIGN 30) |
b4e3537b | 82 | (UNSPEC_VECT_EXTR 31) |
048d0d36 MK |
83 | (UNSPEC_LDA 40) |
84 | (UNSPEC_LDS 41) | |
85 | (UNSPEC_LDSA 42) | |
86 | (UNSPEC_LDCCLR 43) | |
87 | (UNSPEC_CHKACLR 45) | |
88 | (UNSPEC_CHKS 47) | |
086c0f96 RH |
89 | ]) |
90 | ||
91 | (define_constants | |
92 | [(UNSPECV_ALLOC 0) | |
93 | (UNSPECV_BLOCKAGE 1) | |
94 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
95 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
96 | (UNSPECV_SET_BSP 4) |
97 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
98 | (UNSPECV_PSAC_NORMAL 6) | |
b39eb2f9 | 99 | (UNSPECV_SETJMP_RECEIVER 7) |
086c0f96 | 100 | ]) |
e543e219 | 101 | |
7905f799 | 102 | (include "predicates.md") |
13f70342 | 103 | (include "constraints.md") |
c65ebc55 JW |
104 | \f |
105 | ;; :::::::::::::::::::: | |
106 | ;; :: | |
107 | ;; :: Attributes | |
108 | ;; :: | |
109 | ;; :::::::::::::::::::: | |
110 | ||
30028c85 VM |
111 | ;; Processor type. This attribute must exactly match the processor_type |
112 | ;; enumeration in ia64.h. | |
113 | (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune"))) | |
114 | ||
c65ebc55 JW |
115 | ;; Instruction type. This primarily determines how instructions can be |
116 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
117 | ||
118 | ;; A alu, can go in I or M syllable of a bundle | |
119 | ;; I integer | |
120 | ;; M memory | |
121 | ;; F floating-point | |
122 | ;; B branch | |
123 | ;; L long immediate, takes two syllables | |
124 | ;; S stop bit | |
125 | ||
126 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
127 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
128 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
129 | ;; which emit instruction that can go in any slot (e.g. nop). | |
130 | ||
1d5d7a21 | 131 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
a71aef0b | 132 | fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, |
048d0d36 | 133 | ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, |
f61134e8 RH |
134 | st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, |
135 | nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 136 | (const_string "unknown")) |
52e12ad0 | 137 | |
048d0d36 | 138 | ;; chk_s_i has an I and an M form; use type A for convenience. |
2130b7fb | 139 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" |
a71aef0b | 140 | (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") |
52e12ad0 BS |
141 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
142 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 143 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
048d0d36 MK |
144 | (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M") |
145 | (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua") | |
f61134e8 | 146 | (const_string "A") |
2130b7fb BS |
147 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") |
148 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
149 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
150 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
151 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
152 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 153 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 154 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
155 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
156 | (const_string "unknown"))) | |
c65ebc55 | 157 | |
2130b7fb BS |
158 | (define_attr "itanium_requires_unit0" "no,yes" |
159 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
160 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
161 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
162 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
163 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
164 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
165 | (const_string "no"))) | |
166 | ||
e5bde68a RH |
167 | ;; Predication. True iff this instruction can be predicated. |
168 | ||
169 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
170 | ||
fa978426 AS |
171 | ;; Empty. True iff this insn does not generate any code. |
172 | ||
173 | (define_attr "empty" "no,yes" (const_string "no")) | |
174 | ||
68e11b42 JW |
175 | ;; True iff this insn must be the first insn of an instruction group. |
176 | ;; This is true for the alloc instruction, and will also be true of others | |
177 | ;; when we have full intrinsics support. | |
178 | ||
179 | (define_attr "first_insn" "no,yes" (const_string "no")) | |
048d0d36 MK |
180 | |
181 | (define_attr "data_speculative" "no,yes" (const_string "no")) | |
182 | ||
183 | (define_attr "control_speculative" "no,yes" (const_string "no")) | |
184 | ||
185 | (define_attr "check_load" "no,yes" (const_string "no")) | |
c65ebc55 | 186 | \f |
30028c85 VM |
187 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
188 | ;; bundling. | |
189 | ||
190 | (automata_option "ndfa") | |
191 | ||
192 | ;; Uncomment the following line to output automata for debugging. | |
193 | ;; (automata_option "v") | |
194 | ||
195 | (automata_option "w") | |
196 | ||
30028c85 VM |
197 | (include "itanium1.md") |
198 | (include "itanium2.md") | |
199 | ||
c65ebc55 JW |
200 | \f |
201 | ;; :::::::::::::::::::: | |
202 | ;; :: | |
203 | ;; :: Moves | |
204 | ;; :: | |
205 | ;; :::::::::::::::::::: | |
206 | ||
f2f90c63 RH |
207 | ;; Set of a single predicate register. This is only used to implement |
208 | ;; pr-to-pr move and complement. | |
209 | ||
210 | (define_insn "*movcci" | |
211 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
212 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
213 | "" | |
214 | "@ | |
215 | cmp.ne %0, p0 = r0, r0 | |
216 | cmp.eq %0, p0 = r0, r0 | |
217 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 218 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
219 | (set_attr "predicable" "no")]) |
220 | ||
221 | (define_insn "movbi" | |
b6fb7d46 JW |
222 | [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
223 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
224 | "" |
225 | "@ | |
226 | cmp.ne %0, %I0 = r0, r0 | |
227 | cmp.eq %0, %I0 = r0, r0 | |
228 | # | |
229 | # | |
230 | tbit.nz %0, %I0 = %1, 0 | |
231 | adds %0 = %1, r0 | |
232 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
233 | st1%Q0 %0 = %1%P0 |
234 | mov %0 = %1" | |
52e12ad0 | 235 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
236 | |
237 | (define_split | |
238 | [(set (match_operand:BI 0 "register_operand" "") | |
239 | (match_operand:BI 1 "register_operand" ""))] | |
240 | "reload_completed | |
241 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
242 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
243 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
244 | (set (match_dup 0) (const_int 1))) | |
245 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
246 | (set (match_dup 0) (const_int 0)))] | |
247 | "") | |
248 | ||
249 | (define_split | |
250 | [(set (match_operand:BI 0 "register_operand" "") | |
251 | (match_operand:BI 1 "register_operand" ""))] | |
252 | "reload_completed | |
253 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
254 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
255 | [(set (match_dup 2) (match_dup 4)) | |
256 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 257 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
258 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
259 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
260 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
261 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
262 | ||
c65ebc55 JW |
263 | (define_expand "movqi" |
264 | [(set (match_operand:QI 0 "general_operand" "") | |
265 | (match_operand:QI 1 "general_operand" ""))] | |
266 | "" | |
c65ebc55 | 267 | { |
7b6e506e RH |
268 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
269 | if (!op1) | |
270 | DONE; | |
271 | operands[1] = op1; | |
1d5d7a21 | 272 | }) |
c65ebc55 JW |
273 | |
274 | (define_insn "*movqi_internal" | |
4b983fdc RH |
275 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
276 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 277 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 278 | "@ |
13da91fd | 279 | mov %0 = %r1 |
c65ebc55 JW |
280 | addl %0 = %1, r0 |
281 | ld1%O1 %0 = %1%P1 | |
13da91fd | 282 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 283 | getf.sig %0 = %1 |
13da91fd RH |
284 | setf.sig %0 = %r1 |
285 | mov %0 = %1" | |
52e12ad0 | 286 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
287 | |
288 | (define_expand "movhi" | |
289 | [(set (match_operand:HI 0 "general_operand" "") | |
290 | (match_operand:HI 1 "general_operand" ""))] | |
291 | "" | |
c65ebc55 | 292 | { |
7b6e506e RH |
293 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
294 | if (!op1) | |
295 | DONE; | |
296 | operands[1] = op1; | |
1d5d7a21 | 297 | }) |
c65ebc55 JW |
298 | |
299 | (define_insn "*movhi_internal" | |
4b983fdc RH |
300 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
301 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 302 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 303 | "@ |
13da91fd | 304 | mov %0 = %r1 |
c65ebc55 JW |
305 | addl %0 = %1, r0 |
306 | ld2%O1 %0 = %1%P1 | |
13da91fd | 307 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 308 | getf.sig %0 = %1 |
13da91fd RH |
309 | setf.sig %0 = %r1 |
310 | mov %0 = %1" | |
52e12ad0 | 311 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
312 | |
313 | (define_expand "movsi" | |
314 | [(set (match_operand:SI 0 "general_operand" "") | |
315 | (match_operand:SI 1 "general_operand" ""))] | |
316 | "" | |
c65ebc55 | 317 | { |
7b6e506e RH |
318 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
319 | if (!op1) | |
320 | DONE; | |
321 | operands[1] = op1; | |
1d5d7a21 | 322 | }) |
c65ebc55 JW |
323 | |
324 | (define_insn "*movsi_internal" | |
97e242b0 | 325 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 326 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 327 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 328 | "@ |
13da91fd | 329 | mov %0 = %r1 |
c65ebc55 JW |
330 | addl %0 = %1, r0 |
331 | movl %0 = %1 | |
332 | ld4%O1 %0 = %1%P1 | |
13da91fd | 333 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 334 | getf.sig %0 = %1 |
13da91fd | 335 | setf.sig %0 = %r1 |
97e242b0 RH |
336 | mov %0 = %1 |
337 | mov %0 = %1 | |
338 | mov %0 = %r1" | |
1d5d7a21 | 339 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
52e12ad0 | 340 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) |
c65ebc55 JW |
341 | |
342 | (define_expand "movdi" | |
343 | [(set (match_operand:DI 0 "general_operand" "") | |
344 | (match_operand:DI 1 "general_operand" ""))] | |
345 | "" | |
c65ebc55 | 346 | { |
7b6e506e RH |
347 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
348 | if (!op1) | |
349 | DONE; | |
350 | operands[1] = op1; | |
1d5d7a21 | 351 | }) |
c65ebc55 | 352 | |
c65ebc55 | 353 | (define_insn "*movdi_internal" |
4b983fdc | 354 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 355 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 356 | (match_operand:DI 1 "move_operand" |
a32767e4 | 357 | "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 358 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
359 | { |
360 | static const char * const alt[] = { | |
1d5d7a21 RH |
361 | "%,mov %0 = %r1", |
362 | "%,addl %0 = %1, r0", | |
363 | "%,movl %0 = %1", | |
364 | "%,ld8%O1 %0 = %1%P1", | |
365 | "%,st8%Q0 %0 = %r1%P0", | |
366 | "%,getf.sig %0 = %1", | |
367 | "%,setf.sig %0 = %r1", | |
368 | "%,mov %0 = %1", | |
369 | "%,ldf8 %0 = %1%P1", | |
370 | "%,stf8 %0 = %1%P0", | |
371 | "%,mov %0 = %1", | |
372 | "%,mov %0 = %r1", | |
373 | "%,mov %0 = %1", | |
374 | "%,mov %0 = %1", | |
375 | "%,mov %0 = %1", | |
376 | "%,mov %0 = %1", | |
377 | "mov %0 = pr", | |
378 | "mov pr = %1, -1" | |
9b7bf67d RH |
379 | }; |
380 | ||
e820471b NS |
381 | gcc_assert (which_alternative != 2 || TARGET_NO_PIC |
382 | || !symbolic_operand (operands[1], VOIDmode)); | |
9b7bf67d RH |
383 | |
384 | return alt[which_alternative]; | |
1d5d7a21 | 385 | } |
52e12ad0 | 386 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 387 | |
048d0d36 MK |
388 | (define_mode_macro MODE [BI QI HI SI DI SF DF XF TI]) |
389 | (define_mode_macro MODE_FOR_EXTEND [QI HI SI]) | |
390 | ||
391 | (define_mode_attr output_a [ | |
392 | (BI "ld1.a %0 = %1%P1") | |
393 | (QI "ld1.a %0 = %1%P1") | |
394 | (HI "ld2.a %0 = %1%P1") | |
395 | (SI "ld4.a %0 = %1%P1") | |
396 | (DI | |
397 | "@ | |
398 | ld8.a %0 = %1%P1 | |
399 | ldf8.a %0 = %1%P1") | |
400 | (SF | |
401 | "@ | |
402 | ldfs.a %0 = %1%P1 | |
403 | ld4.a %0 = %1%P1") | |
404 | (DF | |
405 | "@ | |
406 | ldfd.a %0 = %1%P1 | |
407 | ld8.a %0 = %1%P1") | |
408 | (XF "ldfe.a %0 = %1%P1") | |
409 | (TI "ldfp8.a %X0 = %1%P1")]) | |
410 | ||
411 | (define_mode_attr output_s [ | |
412 | (BI "ld1.s %0 = %1%P1") | |
413 | (QI "ld1.s %0 = %1%P1") | |
414 | (HI "ld2.s %0 = %1%P1") | |
415 | (SI "ld4.s %0 = %1%P1") | |
416 | (DI | |
417 | "@ | |
418 | ld8.s %0 = %1%P1 | |
419 | ldf8.s %0 = %1%P1") | |
420 | (SF | |
421 | "@ | |
422 | ldfs.s %0 = %1%P1 | |
423 | ld4.s %0 = %1%P1") | |
424 | (DF | |
425 | "@ | |
426 | ldfd.s %0 = %1%P1 | |
427 | ld8.s %0 = %1%P1") | |
428 | (XF "ldfe.s %0 = %1%P1") | |
429 | (TI "ldfp8.s %X0 = %1%P1")]) | |
430 | ||
431 | (define_mode_attr output_sa [ | |
432 | (BI "ld1.sa %0 = %1%P1") | |
433 | (QI "ld1.sa %0 = %1%P1") | |
434 | (HI "ld2.sa %0 = %1%P1") | |
435 | (SI "ld4.sa %0 = %1%P1") | |
436 | (DI | |
437 | "@ | |
438 | ld8.sa %0 = %1%P1 | |
439 | ldf8.sa %0 = %1%P1") | |
440 | (SF | |
441 | "@ | |
442 | ldfs.sa %0 = %1%P1 | |
443 | ld4.sa %0 = %1%P1") | |
444 | (DF | |
445 | "@ | |
446 | ldfd.sa %0 = %1%P1 | |
447 | ld8.sa %0 = %1%P1") | |
448 | (XF "ldfe.sa %0 = %1%P1") | |
449 | (TI "ldfp8.sa %X0 = %1%P1")]) | |
450 | ||
451 | (define_mode_attr output_c_clr [ | |
452 | (BI "ld1.c.clr%O1 %0 = %1%P1") | |
453 | (QI "ld1.c.clr%O1 %0 = %1%P1") | |
454 | (HI "ld2.c.clr%O1 %0 = %1%P1") | |
455 | (SI "ld4.c.clr%O1 %0 = %1%P1") | |
456 | (DI | |
457 | "@ | |
458 | ld8.c.clr%O1 %0 = %1%P1 | |
459 | ldf8.c.clr %0 = %1%P1") | |
460 | (SF | |
461 | "@ | |
462 | ldfs.c.clr %0 = %1%P1 | |
463 | ld4.c.clr%O1 %0 = %1%P1") | |
464 | (DF | |
465 | "@ | |
466 | ldfd.c.clr %0 = %1%P1 | |
467 | ld8.c.clr%O1 %0 = %1%P1") | |
468 | (XF "ldfe.c.clr %0 = %1%P1") | |
469 | (TI "ldfp8.c.clr %X0 = %1%P1")]) | |
470 | ||
471 | (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")]) | |
472 | (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")]) | |
473 | (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")]) | |
474 | ||
475 | (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) | |
476 | ||
f6ec1d11 MK |
477 | ;; Define register predicate prefix. |
478 | ;; We can generate speculative loads only for general and fp registers - this | |
ea2c620c | 479 | ;; is constrained in ia64.c: ia64_speculate_insn (). |
048d0d36 MK |
480 | (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) |
481 | ||
482 | (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) | |
483 | (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")]) | |
484 | (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")]) | |
485 | ||
486 | (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")]) | |
487 | ||
488 | (define_insn "mov<mode>_advanced" | |
489 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
490 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))] | |
491 | "ia64_move_ok (operands[0], operands[1])" | |
492 | "<output_a>" | |
493 | [(set_attr "itanium_class" "<ld_class>") | |
494 | (set_attr "data_speculative" "<attr_yes>")]) | |
495 | ||
496 | (define_insn "zero_extend<mode>di2_advanced" | |
497 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
498 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))] | |
499 | "" | |
500 | "<output_a>" | |
501 | [(set_attr "itanium_class" "<ld_class>") | |
502 | (set_attr "data_speculative" "<attr_yes>")]) | |
503 | ||
504 | (define_insn "mov<mode>_speculative" | |
505 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
506 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))] | |
507 | "ia64_move_ok (operands[0], operands[1])" | |
508 | "<output_s>" | |
509 | [(set_attr "itanium_class" "<ld_class>") | |
510 | (set_attr "control_speculative" "<attr_yes>")]) | |
511 | ||
512 | (define_insn "zero_extend<mode>di2_speculative" | |
513 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
514 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))] | |
515 | "" | |
516 | "<output_s>" | |
517 | [(set_attr "itanium_class" "<ld_class>") | |
518 | (set_attr "control_speculative" "<attr_yes>")]) | |
519 | ||
520 | (define_insn "mov<mode>_speculative_advanced" | |
521 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
522 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))] | |
523 | "ia64_move_ok (operands[0], operands[1])" | |
524 | "<output_sa>" | |
525 | [(set_attr "itanium_class" "<ld_class>") | |
526 | (set_attr "data_speculative" "<attr_yes>") | |
527 | (set_attr "control_speculative" "<attr_yes>")]) | |
528 | ||
529 | (define_insn "zero_extend<mode>di2_speculative_advanced" | |
530 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
531 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))] | |
532 | "" | |
533 | "<output_sa>" | |
534 | [(set_attr "itanium_class" "<ld_class>") | |
535 | (set_attr "data_speculative" "<attr_yes>") | |
536 | (set_attr "control_speculative" "<attr_yes>")]) | |
537 | ||
538 | (define_insn "mov<mode>_clr" | |
539 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
540 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
541 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
542 | (match_dup 0)))] | |
543 | "ia64_move_ok (operands[0], operands[1])" | |
544 | "<output_c_clr>" | |
545 | [(set_attr "itanium_class" "<ld_class>") | |
546 | (set_attr "check_load" "<attr_yes>")]) | |
547 | ||
548 | (define_insn "zero_extend<mode>di2_clr" | |
549 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
550 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
551 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
552 | (match_dup 0)))] | |
553 | "" | |
554 | "<output_c_clr>" | |
555 | [(set_attr "itanium_class" "<ld_class>") | |
556 | (set_attr "check_load" "<attr_yes>")]) | |
557 | ||
558 | (define_insn "advanced_load_check_clr_<mode>" | |
559 | [(set (pc) | |
560 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0)) | |
561 | (pc) | |
562 | (label_ref (match_operand 1 "" ""))))] | |
563 | "" | |
564 | "chk.a.clr %0, %l1" | |
565 | [(set_attr "itanium_class" "<chka_class>")]) | |
566 | ||
567 | (define_insn "speculation_check_<mode>" | |
568 | [(set (pc) | |
569 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0)) | |
570 | (pc) | |
571 | (label_ref (match_operand 1 "" ""))))] | |
572 | "" | |
573 | "chk.s %0, %l1" | |
574 | [(set_attr "itanium_class" "<chks_class>")]) | |
575 | ||
9b7bf67d | 576 | (define_split |
21515593 RH |
577 | [(set (match_operand 0 "register_operand" "") |
578 | (match_operand 1 "symbolic_operand" ""))] | |
5e6c8b64 | 579 | "reload_completed" |
9b7bf67d | 580 | [(const_int 0)] |
9b7bf67d | 581 | { |
5e6c8b64 RH |
582 | if (ia64_expand_load_address (operands[0], operands[1])) |
583 | DONE; | |
584 | else | |
585 | FAIL; | |
1d5d7a21 | 586 | }) |
9b7bf67d | 587 | |
c65ebc55 | 588 | (define_expand "load_fptr" |
5e6c8b64 RH |
589 | [(set (match_operand:DI 0 "register_operand" "") |
590 | (plus:DI (match_dup 2) (match_operand 1 "function_operand" ""))) | |
591 | (set (match_dup 0) (match_dup 3))] | |
592 | "reload_completed" | |
c65ebc55 | 593 | { |
5e6c8b64 RH |
594 | operands[2] = pic_offset_table_rtx; |
595 | operands[3] = gen_const_mem (DImode, operands[0]); | |
1d5d7a21 | 596 | }) |
c65ebc55 JW |
597 | |
598 | (define_insn "*load_fptr_internal1" | |
599 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 600 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
5e6c8b64 | 601 | "reload_completed" |
c65ebc55 | 602 | "addl %0 = @ltoff(@fptr(%1)), gp" |
52e12ad0 | 603 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
604 | |
605 | (define_insn "load_gprel" | |
606 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 607 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
5e6c8b64 | 608 | "reload_completed" |
c65ebc55 | 609 | "addl %0 = @gprel(%1), gp" |
52e12ad0 | 610 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 611 | |
5e6c8b64 | 612 | (define_insn "*gprel64_offset" |
59da9a7d JW |
613 | [(set (match_operand:DI 0 "register_operand" "=r") |
614 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
5e6c8b64 | 615 | "reload_completed" |
59da9a7d | 616 | "movl %0 = @gprel(%1)" |
52e12ad0 | 617 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
618 | |
619 | (define_expand "load_gprel64" | |
5e6c8b64 RH |
620 | [(set (match_operand:DI 0 "register_operand" "") |
621 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2))) | |
622 | (set (match_dup 0) | |
623 | (plus:DI (match_dup 2) (match_dup 0)))] | |
624 | "reload_completed" | |
ec039e3c | 625 | { |
5e6c8b64 | 626 | operands[2] = pic_offset_table_rtx; |
1d5d7a21 | 627 | }) |
59da9a7d | 628 | |
af1e5518 RH |
629 | ;; This is used as a placeholder for the return address during early |
630 | ;; compilation. We won't know where we've placed this until during | |
631 | ;; reload, at which point it can wind up in b0, a general register, | |
632 | ;; or memory. The only safe destination under these conditions is a | |
633 | ;; general register. | |
634 | ||
635 | (define_insn_and_split "*movdi_ret_addr" | |
636 | [(set (match_operand:DI 0 "register_operand" "=r") | |
637 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
638 | "" | |
639 | "#" | |
640 | "reload_completed" | |
641 | [(const_int 0)] | |
642 | { | |
643 | ia64_split_return_addr_rtx (operands[0]); | |
644 | DONE; | |
645 | } | |
646 | [(set_attr "itanium_class" "ialu")]) | |
647 | ||
ef1ecf87 | 648 | (define_insn "*load_symptr_high" |
c65ebc55 | 649 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
650 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
651 | (match_operand:DI 2 "register_operand" "a")))] | |
5e6c8b64 | 652 | "reload_completed" |
ef1ecf87 RH |
653 | { |
654 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
655 | return "%,addl %0 = @ltoffx(%1), %2"; | |
656 | else | |
657 | return "%,addl %0 = @ltoff(%1), %2"; | |
658 | } | |
52e12ad0 | 659 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 660 | |
ef1ecf87 RH |
661 | (define_insn "*load_symptr_low" |
662 | [(set (match_operand:DI 0 "register_operand" "=r") | |
663 | (lo_sum:DI (match_operand:DI 1 "register_operand" "r") | |
664 | (match_operand 2 "got_symbolic_operand" "s")))] | |
5e6c8b64 | 665 | "reload_completed" |
ef1ecf87 RH |
666 | { |
667 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
668 | return "%,ld8.mov %0 = [%1], %2"; | |
669 | else | |
670 | return "%,ld8 %0 = [%1]"; | |
671 | } | |
672 | [(set_attr "itanium_class" "ld")]) | |
673 | ||
5e6c8b64 | 674 | (define_insn_and_split "load_dtpmod" |
7b6e506e | 675 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 676 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 | 677 | UNSPEC_DTPMOD))] |
7b6e506e | 678 | "" |
5e6c8b64 RH |
679 | "#" |
680 | "reload_completed" | |
681 | [(set (match_dup 0) | |
682 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD) | |
683 | (match_dup 2))) | |
684 | (set (match_dup 0) (match_dup 3))] | |
685 | { | |
686 | operands[2] = pic_offset_table_rtx; | |
687 | operands[3] = gen_const_mem (DImode, operands[0]); | |
688 | }) | |
7b6e506e | 689 | |
5e6c8b64 | 690 | (define_insn "*load_ltoff_dtpmod" |
7b6e506e | 691 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 692 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
693 | UNSPEC_LTOFF_DTPMOD) |
694 | (match_operand:DI 2 "register_operand" "a")))] | |
695 | "reload_completed" | |
696 | "addl %0 = @ltoff(@dtpmod(%1)), %2" | |
7b6e506e RH |
697 | [(set_attr "itanium_class" "ialu")]) |
698 | ||
699 | (define_expand "load_dtprel" | |
700 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 701 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
702 | UNSPEC_DTPREL))] |
703 | "" | |
704 | "") | |
705 | ||
706 | (define_insn "*load_dtprel64" | |
707 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 708 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
709 | UNSPEC_DTPREL))] |
710 | "TARGET_TLS64" | |
711 | "movl %0 = @dtprel(%1)" | |
712 | [(set_attr "itanium_class" "long_i")]) | |
713 | ||
714 | (define_insn "*load_dtprel22" | |
715 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 716 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
717 | UNSPEC_DTPREL))] |
718 | "" | |
719 | "addl %0 = @dtprel(%1), r0" | |
720 | [(set_attr "itanium_class" "ialu")]) | |
721 | ||
5e6c8b64 RH |
722 | (define_insn_and_split "*load_dtprel_gd" |
723 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 724 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
725 | UNSPEC_DTPREL))] |
726 | "" | |
727 | "#" | |
728 | "reload_completed" | |
729 | [(set (match_dup 0) | |
730 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL) | |
731 | (match_dup 2))) | |
732 | (set (match_dup 0) (match_dup 3))] | |
733 | { | |
734 | operands[2] = pic_offset_table_rtx; | |
735 | operands[3] = gen_const_mem (DImode, operands[0]); | |
736 | }) | |
737 | ||
738 | (define_insn "*load_ltoff_dtprel" | |
739 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 740 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
741 | UNSPEC_LTOFF_DTPREL) |
742 | (match_operand:DI 2 "register_operand" "a")))] | |
743 | "" | |
744 | "addl %0 = @ltoff(@dtprel(%1)), %2" | |
745 | [(set_attr "itanium_class" "ialu")]) | |
746 | ||
7b6e506e RH |
747 | (define_expand "add_dtprel" |
748 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 749 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
750 | UNSPEC_DTPREL) |
751 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
752 | "!TARGET_TLS64" |
753 | "") | |
754 | ||
755 | (define_insn "*add_dtprel14" | |
756 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 757 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
758 | UNSPEC_DTPREL) |
759 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 760 | "TARGET_TLS14" |
5e6c8b64 | 761 | "adds %0 = @dtprel(%1), %2" |
7b6e506e RH |
762 | [(set_attr "itanium_class" "ialu")]) |
763 | ||
764 | (define_insn "*add_dtprel22" | |
765 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 766 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
767 | UNSPEC_DTPREL) |
768 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 769 | "TARGET_TLS22" |
5e6c8b64 | 770 | "addl %0 = @dtprel(%1), %2" |
7b6e506e RH |
771 | [(set_attr "itanium_class" "ialu")]) |
772 | ||
773 | (define_expand "load_tprel" | |
774 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 775 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
776 | UNSPEC_TPREL))] |
777 | "" | |
778 | "") | |
779 | ||
780 | (define_insn "*load_tprel64" | |
781 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 782 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
783 | UNSPEC_TPREL))] |
784 | "TARGET_TLS64" | |
785 | "movl %0 = @tprel(%1)" | |
786 | [(set_attr "itanium_class" "long_i")]) | |
787 | ||
788 | (define_insn "*load_tprel22" | |
789 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 790 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
791 | UNSPEC_TPREL))] |
792 | "" | |
793 | "addl %0 = @tprel(%1), r0" | |
794 | [(set_attr "itanium_class" "ialu")]) | |
795 | ||
5e6c8b64 RH |
796 | (define_insn_and_split "*load_tprel_ie" |
797 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 798 | (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
799 | UNSPEC_TPREL))] |
800 | "" | |
801 | "#" | |
802 | "reload_completed" | |
803 | [(set (match_dup 0) | |
804 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL) | |
805 | (match_dup 2))) | |
806 | (set (match_dup 0) (match_dup 3))] | |
807 | { | |
808 | operands[2] = pic_offset_table_rtx; | |
809 | operands[3] = gen_const_mem (DImode, operands[0]); | |
810 | }) | |
811 | ||
812 | (define_insn "*load_ltoff_tprel" | |
813 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 814 | (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
815 | UNSPEC_LTOFF_TPREL) |
816 | (match_operand:DI 2 "register_operand" "a")))] | |
817 | "" | |
818 | "addl %0 = @ltoff(@tprel(%1)), %2" | |
819 | [(set_attr "itanium_class" "ialu")]) | |
820 | ||
7b6e506e RH |
821 | (define_expand "add_tprel" |
822 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 823 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
824 | UNSPEC_TPREL) |
825 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
826 | "!TARGET_TLS64" |
827 | "") | |
828 | ||
829 | (define_insn "*add_tprel14" | |
830 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 831 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
832 | UNSPEC_TPREL) |
833 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 834 | "TARGET_TLS14" |
5e6c8b64 | 835 | "adds %0 = @tprel(%1), %2" |
7b6e506e RH |
836 | [(set_attr "itanium_class" "ialu")]) |
837 | ||
838 | (define_insn "*add_tprel22" | |
839 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 840 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
841 | UNSPEC_TPREL) |
842 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 843 | "TARGET_TLS22" |
5e6c8b64 | 844 | "addl %0 = @tprel(%1), %2" |
7b6e506e RH |
845 | [(set_attr "itanium_class" "ialu")]) |
846 | ||
3f622353 | 847 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
848 | ;; around to play with the second word. However, in order to avoid a |
849 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
850 | ;; in ia64_split_tmode_move. | |
3f622353 | 851 | (define_expand "movti" |
2ffe0e02 ZW |
852 | [(set (match_operand:TI 0 "general_operand" "") |
853 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 854 | "" |
3f622353 | 855 | { |
7b6e506e RH |
856 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
857 | if (!op1) | |
858 | DONE; | |
859 | operands[1] = op1; | |
1d5d7a21 | 860 | }) |
3f622353 RH |
861 | |
862 | (define_insn_and_split "*movti_internal" | |
b6fb7d46 JW |
863 | [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q") |
864 | (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))] | |
3f622353 | 865 | "ia64_move_ok (operands[0], operands[1])" |
a71aef0b JB |
866 | "@ |
867 | # | |
868 | # | |
869 | ldfp8 %X0 = %1%P1 | |
870 | # | |
871 | #" | |
872 | "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])" | |
3f622353 | 873 | [(const_int 0)] |
3f622353 | 874 | { |
f57fc998 | 875 | ia64_split_tmode_move (operands); |
3f622353 | 876 | DONE; |
1d5d7a21 | 877 | } |
a71aef0b | 878 | [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")]) |
e314e331 | 879 | |
c65ebc55 JW |
880 | ;; Floating Point Moves |
881 | ;; | |
882 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 883 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
884 | |
885 | (define_expand "movsf" | |
886 | [(set (match_operand:SF 0 "general_operand" "") | |
887 | (match_operand:SF 1 "general_operand" ""))] | |
888 | "" | |
c65ebc55 | 889 | { |
7b6e506e RH |
890 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
891 | if (!op1) | |
892 | DONE; | |
893 | operands[1] = op1; | |
1d5d7a21 | 894 | }) |
c65ebc55 | 895 | |
c65ebc55 | 896 | (define_insn "*movsf_internal" |
4b983fdc RH |
897 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
898 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 899 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 900 | "@ |
1d5d7a21 RH |
901 | mov %0 = %F1 |
902 | ldfs %0 = %1%P1 | |
903 | stfs %0 = %F1%P0 | |
904 | getf.s %0 = %F1 | |
905 | setf.s %0 = %1 | |
906 | mov %0 = %1 | |
907 | ld4%O1 %0 = %1%P1 | |
908 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 909 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
910 | |
911 | (define_expand "movdf" | |
912 | [(set (match_operand:DF 0 "general_operand" "") | |
913 | (match_operand:DF 1 "general_operand" ""))] | |
914 | "" | |
c65ebc55 | 915 | { |
7b6e506e RH |
916 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
917 | if (!op1) | |
918 | DONE; | |
919 | operands[1] = op1; | |
1d5d7a21 | 920 | }) |
c65ebc55 | 921 | |
c65ebc55 | 922 | (define_insn "*movdf_internal" |
4b983fdc RH |
923 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
924 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 925 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 926 | "@ |
1d5d7a21 RH |
927 | mov %0 = %F1 |
928 | ldfd %0 = %1%P1 | |
929 | stfd %0 = %F1%P0 | |
930 | getf.d %0 = %F1 | |
931 | setf.d %0 = %1 | |
932 | mov %0 = %1 | |
933 | ld8%O1 %0 = %1%P1 | |
934 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 935 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 936 | |
3f622353 RH |
937 | ;; With no offsettable memory references, we've got to have a scratch |
938 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
939 | (define_expand "movxf" |
940 | [(set (match_operand:XF 0 "general_operand" "") | |
941 | (match_operand:XF 1 "general_operand" ""))] | |
942 | "" | |
e5bde68a | 943 | { |
4de67c26 JM |
944 | if (ia64_expand_movxf_movrf (XFmode, operands)) |
945 | DONE; | |
1d5d7a21 | 946 | }) |
e5bde68a | 947 | |
3b572406 | 948 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 949 | |
02befdf4 | 950 | (define_insn "*movxf_internal" |
78d8e0f9 ZW |
951 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
952 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 953 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 954 | "@ |
1d5d7a21 RH |
955 | mov %0 = %F1 |
956 | ldfe %0 = %1%P1 | |
957 | stfe %0 = %F1%P0" | |
52e12ad0 | 958 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
f57fc998 | 959 | |
4de67c26 JM |
960 | ;; Same as for movxf, but for RFmode. |
961 | (define_expand "movrf" | |
962 | [(set (match_operand:RF 0 "general_operand" "") | |
963 | (match_operand:RF 1 "general_operand" ""))] | |
964 | "" | |
965 | { | |
966 | if (ia64_expand_movxf_movrf (RFmode, operands)) | |
967 | DONE; | |
968 | }) | |
969 | ||
970 | (define_insn "*movrf_internal" | |
971 | [(set (match_operand:RF 0 "destination_operand" "=f,f, m") | |
972 | (match_operand:RF 1 "general_operand" "fG,m,fG"))] | |
973 | "ia64_move_ok (operands[0], operands[1])" | |
974 | "@ | |
975 | mov %0 = %F1 | |
976 | ldf.fill %0 = %1%P1 | |
977 | stf.spill %0 = %F1%P0" | |
978 | [(set_attr "itanium_class" "fmisc,fld,stf")]) | |
979 | ||
f57fc998 | 980 | ;; Better code generation via insns that deal with TFmode register pairs |
2ffe0e02 | 981 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 982 | (define_expand "movtf" |
2ffe0e02 ZW |
983 | [(set (match_operand:TF 0 "general_operand" "") |
984 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
985 | "" |
986 | { | |
987 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
988 | if (!op1) | |
989 | DONE; | |
990 | operands[1] = op1; | |
991 | }) | |
992 | ||
993 | (define_insn_and_split "*movtf_internal" | |
e77ee95d | 994 | [(set (match_operand:TF 0 "destination_operand" "=r,r,m") |
2ffe0e02 | 995 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
996 | "ia64_move_ok (operands[0], operands[1])" |
997 | "#" | |
998 | "reload_completed" | |
999 | [(const_int 0)] | |
1000 | { | |
1001 | ia64_split_tmode_move (operands); | |
1002 | DONE; | |
1003 | } | |
1004 | [(set_attr "itanium_class" "unknown") | |
1005 | (set_attr "predicable" "no")]) | |
1006 | ||
c65ebc55 JW |
1007 | \f |
1008 | ;; :::::::::::::::::::: | |
1009 | ;; :: | |
1010 | ;; :: Conversions | |
1011 | ;; :: | |
1012 | ;; :::::::::::::::::::: | |
1013 | ||
1014 | ;; Signed conversions from a smaller integer to a larger integer | |
1015 | ||
1016 | (define_insn "extendqidi2" | |
0551c32d RH |
1017 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1018 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1019 | "" |
1020 | "sxt1 %0 = %1" | |
52e12ad0 | 1021 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1022 | |
1023 | (define_insn "extendhidi2" | |
0551c32d RH |
1024 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1025 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1026 | "" |
1027 | "sxt2 %0 = %1" | |
52e12ad0 | 1028 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1029 | |
1030 | (define_insn "extendsidi2" | |
655f2eb9 RH |
1031 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
1032 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
1033 | "" |
1034 | "@ | |
1035 | sxt4 %0 = %1 | |
aebf2462 | 1036 | fsxt.r %0 = %1, %1" |
52e12ad0 | 1037 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
1038 | |
1039 | ;; Unsigned conversions from a smaller integer to a larger integer | |
1040 | ||
1041 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
1042 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1043 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1044 | "" |
1045 | "@ | |
1046 | zxt1 %0 = %1 | |
1047 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 1048 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
1049 | |
1050 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
1051 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1052 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1053 | "" |
1054 | "@ | |
1055 | zxt2 %0 = %1 | |
1056 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 1057 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
1058 | |
1059 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 1060 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 1061 | (zero_extend:DI |
655f2eb9 | 1062 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
1063 | "" |
1064 | "@ | |
d3f6e07b | 1065 | addp4 %0 = %1, r0 |
c65ebc55 | 1066 | ld4%O1 %0 = %1%P1 |
aebf2462 | 1067 | fmix.r %0 = f0, %1" |
d3f6e07b | 1068 | [(set_attr "itanium_class" "ialu,ld,fmisc")]) |
c65ebc55 JW |
1069 | |
1070 | ;; Convert between floating point types of different sizes. | |
1071 | ||
640cea5f JW |
1072 | ;; At first glance, it would appear that emitting fnorm for an extending |
1073 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
1074 | ;; correctly only if the input is properly rounded for its type. In | |
1075 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
1076 | ;; denorm single. Since we don't know what the next instruction will be, we | |
1077 | ;; have to emit an fnorm. | |
1078 | ||
e8e20f18 RH |
1079 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
1080 | ;; when we can. Should probably use a scheme like has been proposed | |
1081 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
1082 | ;; would let combine merge the thing into adjacent insns. See also how the |
1083 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
1084 | ;; se_register_operand. | |
c65ebc55 | 1085 | |
640cea5f JW |
1086 | (define_insn "extendsfdf2" |
1087 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
1088 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1089 | "" |
640cea5f JW |
1090 | "fnorm.d %0 = %1" |
1091 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 1092 | |
02befdf4 ZW |
1093 | (define_insn "extendsfxf2" |
1094 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1095 | (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))] | |
1096 | "" | |
640cea5f JW |
1097 | "fnorm %0 = %1" |
1098 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 1099 | |
02befdf4 ZW |
1100 | (define_insn "extenddfxf2" |
1101 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1102 | (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))] | |
1103 | "" | |
640cea5f JW |
1104 | "fnorm %0 = %1" |
1105 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 1106 | |
c65ebc55 | 1107 | (define_insn "truncdfsf2" |
0551c32d RH |
1108 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1109 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1110 | "" |
aebf2462 | 1111 | "fnorm.s %0 = %1" |
52e12ad0 | 1112 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1113 | |
02befdf4 | 1114 | (define_insn "truncxfsf2" |
0551c32d | 1115 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1116 | (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))] |
1117 | "" | |
aebf2462 | 1118 | "fnorm.s %0 = %1" |
52e12ad0 | 1119 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1120 | |
02befdf4 | 1121 | (define_insn "truncxfdf2" |
0551c32d | 1122 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1123 | (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))] |
1124 | "" | |
aebf2462 | 1125 | "fnorm.d %0 = %1" |
52e12ad0 | 1126 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
1127 | |
1128 | ;; Convert between signed integer types and floating point. | |
1129 | ||
02befdf4 ZW |
1130 | (define_insn "floatdixf2" |
1131 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1132 | (float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
1133 | "" | |
e5bde68a | 1134 | "fcvt.xf %0 = %1" |
52e12ad0 | 1135 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1136 | |
1137 | (define_insn "fix_truncsfdi2" | |
0551c32d RH |
1138 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1139 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1140 | "" |
aebf2462 | 1141 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1142 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1143 | |
1144 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
1145 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1146 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1147 | "" |
aebf2462 | 1148 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1149 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1150 | |
02befdf4 | 1151 | (define_insn "fix_truncxfdi2" |
0551c32d | 1152 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1153 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1154 | "" | |
aebf2462 | 1155 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1156 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1157 | |
02befdf4 | 1158 | (define_insn "fix_truncxfdi2_alts" |
655f2eb9 | 1159 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1160 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1161 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1162 | "" |
aebf2462 | 1163 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 1164 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1165 | |
c65ebc55 JW |
1166 | ;; Convert between unsigned integer types and floating point. |
1167 | ||
1168 | (define_insn "floatunsdisf2" | |
0551c32d RH |
1169 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1170 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1171 | "" |
aebf2462 | 1172 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 1173 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1174 | |
1175 | (define_insn "floatunsdidf2" | |
0551c32d RH |
1176 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
1177 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1178 | "" |
aebf2462 | 1179 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 1180 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1181 | |
02befdf4 ZW |
1182 | (define_insn "floatunsdixf2" |
1183 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1184 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
1185 | "" | |
aebf2462 | 1186 | "fcvt.xuf %0 = %1" |
52e12ad0 | 1187 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1188 | |
c65ebc55 | 1189 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
1190 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1191 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1192 | "" |
aebf2462 | 1193 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1194 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1195 | |
1196 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
1197 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1198 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1199 | "" |
aebf2462 | 1200 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1201 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1202 | |
02befdf4 | 1203 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 1204 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1205 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1206 | "" | |
aebf2462 | 1207 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1208 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1209 | |
02befdf4 | 1210 | (define_insn "fixuns_truncxfdi2_alts" |
655f2eb9 | 1211 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1212 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1213 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1214 | "" |
aebf2462 | 1215 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 1216 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1217 | \f |
1218 | ;; :::::::::::::::::::: | |
1219 | ;; :: | |
1220 | ;; :: Bit field extraction | |
1221 | ;; :: | |
1222 | ;; :::::::::::::::::::: | |
1223 | ||
c65ebc55 | 1224 | (define_insn "extv" |
0551c32d RH |
1225 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1226 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1227 | (match_operand:DI 2 "extr_len_operand" "n") |
1228 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1229 | "" |
1230 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1231 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1232 | |
1233 | (define_insn "extzv" | |
0551c32d RH |
1234 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1235 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1236 | (match_operand:DI 2 "extr_len_operand" "n") |
1237 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1238 | "" |
1239 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1240 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1241 | |
1242 | ;; Insert a bit field. | |
1243 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1244 | ;; Source1 can be 0 or -1. | |
1245 | ;; Source2 can be 0. | |
1246 | ||
1247 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1248 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1249 | ;; where source2 != dest. | |
1250 | ||
1251 | (define_expand "insv" | |
0551c32d | 1252 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1253 | (match_operand:DI 1 "const_int_operand" "") |
1254 | (match_operand:DI 2 "const_int_operand" "")) | |
1255 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1256 | "" | |
c65ebc55 JW |
1257 | { |
1258 | int width = INTVAL (operands[1]); | |
1259 | int shift = INTVAL (operands[2]); | |
1260 | ||
1261 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1262 | pseudo. */ | |
1263 | if (! register_operand (operands[3], DImode) | |
1264 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1265 | operands[3] = force_reg (DImode, operands[3]); | |
1266 | ||
1267 | /* If this is a single dep instruction, we have nothing to do. */ | |
1268 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1269 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1270 | { | |
1271 | /* Check for cases that can be implemented with a mix instruction. */ | |
1272 | if (width == 32 && shift == 0) | |
1273 | { | |
1274 | /* Directly generating the mix4left instruction confuses | |
1275 | optimize_bit_field in function.c. Since this is performing | |
1276 | a useful optimization, we defer generation of the complicated | |
1277 | mix4left RTL to the first splitting phase. */ | |
1278 | rtx tmp = gen_reg_rtx (DImode); | |
1279 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1280 | DONE; | |
1281 | } | |
1282 | else if (width == 32 && shift == 32) | |
1283 | { | |
1284 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1285 | DONE; | |
1286 | } | |
1287 | ||
d2ba6dcf JW |
1288 | /* We could handle remaining cases by emitting multiple dep |
1289 | instructions. | |
1290 | ||
1291 | If we need more than two dep instructions then we lose. A 6 | |
1292 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1293 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1294 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1295 | only one function unit that can execute dep and shr immed. | |
1296 | ||
1297 | If we only need two dep instruction, then we still lose. | |
1298 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1299 | the unnecessary mov, this is still undesirable because it will be | |
1300 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1301 | function unit. */ | |
1302 | ||
c65ebc55 JW |
1303 | FAIL; |
1304 | ||
1305 | #if 0 | |
1306 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1307 | for now. */ | |
1308 | while (width > 16) | |
1309 | { | |
1310 | rtx tmp; | |
1311 | ||
1312 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1313 | operands[3])); | |
1314 | shift += 16; | |
1315 | width -= 16; | |
1316 | tmp = gen_reg_rtx (DImode); | |
1317 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1318 | operands[3] = tmp; | |
1319 | } | |
1320 | operands[1] = GEN_INT (width); | |
1321 | operands[2] = GEN_INT (shift); | |
1322 | #endif | |
1323 | } | |
1d5d7a21 | 1324 | }) |
c65ebc55 JW |
1325 | |
1326 | (define_insn "*insv_internal" | |
0551c32d | 1327 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1328 | (match_operand:DI 1 "const_int_operand" "n") |
1329 | (match_operand:DI 2 "const_int_operand" "n")) | |
1330 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1331 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1332 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1333 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1334 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1335 | |
43a88a8c | 1336 | ;; Combine doesn't like to create bit-field insertions into zero. |
d3f6e07b JB |
1337 | (define_insn "*shladdp4_internal" |
1338 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
1339 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1340 | (match_operand:DI 2 "shladd_log2_operand" "n")) | |
1341 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1342 | "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" | |
1343 | "shladdp4 %0 = %1, %2, r0" | |
1344 | [(set_attr "itanium_class" "ialu")]) | |
1345 | ||
041f25e6 | 1346 | (define_insn "*depz_internal" |
0551c32d RH |
1347 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1348 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
13f70342 | 1349 | (match_operand:DI 2 "const_int_operand" "M")) |
041f25e6 | 1350 | (match_operand:DI 3 "const_int_operand" "n")))] |
13f70342 | 1351 | "satisfies_constraint_M (operands[2]) |
041f25e6 | 1352 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" |
041f25e6 RH |
1353 | { |
1354 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1355 | return "%,dep.z %0 = %1, %2, %3"; |
1356 | } | |
52e12ad0 | 1357 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1358 | |
c65ebc55 | 1359 | (define_insn "shift_mix4left" |
0551c32d | 1360 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1361 | (const_int 32) (const_int 0)) |
0551c32d RH |
1362 | (match_operand:DI 1 "gr_register_operand" "r")) |
1363 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1364 | "" |
1365 | "#" | |
52e12ad0 | 1366 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1367 | |
c65ebc55 JW |
1368 | (define_split |
1369 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1370 | (const_int 32) (const_int 0)) | |
1371 | (match_operand:DI 1 "register_operand" "")) | |
1372 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1373 | "" |
c65ebc55 JW |
1374 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1375 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1376 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1377 | "operands[3] = operands[2];") | |
1378 | ||
1379 | (define_insn "*mix4left" | |
0551c32d | 1380 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1381 | (const_int 32) (const_int 0)) |
0551c32d | 1382 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1383 | (const_int 32)))] |
1384 | "" | |
1385 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1386 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1387 | |
1388 | (define_insn "mix4right" | |
0551c32d | 1389 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1390 | (const_int 32) (const_int 32)) |
0551c32d | 1391 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1392 | "" |
1393 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1394 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1395 | |
1396 | ;; This is used by the rotrsi3 pattern. | |
1397 | ||
1398 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1399 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1400 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1401 | (ashift:DI (zero_extend:DI | |
1402 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1403 | (const_int 32))))] |
1404 | "" | |
fa9a44e8 | 1405 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1406 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1407 | |
1408 | \f | |
1409 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1410 | ;; :: |
27a9b99d | 1411 | ;; :: 1-bit Integer arithmetic |
f2f90c63 RH |
1412 | ;; :: |
1413 | ;; :::::::::::::::::::: | |
1414 | ||
1415 | (define_insn_and_split "andbi3" | |
1416 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1417 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1418 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1419 | "" | |
1420 | "@ | |
1421 | # | |
1422 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1423 | and %0 = %2, %1" | |
1424 | "reload_completed | |
1425 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1426 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1427 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1428 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1429 | (match_dup 0))))] | |
1430 | "" | |
52e12ad0 | 1431 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1432 | |
1433 | (define_insn_and_split "*andcmbi3" | |
1434 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1435 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1436 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1437 | "" | |
1438 | "@ | |
1439 | # | |
967603ef | 1440 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1441 | andcm %0 = %2, %1" |
1442 | "reload_completed | |
1443 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1444 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1445 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1446 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1447 | (match_dup 0))))] | |
1448 | "" | |
52e12ad0 | 1449 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1450 | |
1451 | (define_insn_and_split "iorbi3" | |
1452 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1453 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1454 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1455 | "" | |
1456 | "@ | |
1457 | # | |
1458 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1459 | or %0 = %2, %1" | |
1460 | "reload_completed | |
1461 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1462 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1463 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1464 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1465 | (match_dup 0))))] | |
1466 | "" | |
52e12ad0 | 1467 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1468 | |
1469 | (define_insn_and_split "*iorcmbi3" | |
1470 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1471 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1472 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1473 | "" | |
1474 | "@ | |
1475 | # | |
967603ef | 1476 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1477 | "reload_completed |
1478 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1479 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1480 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1481 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1482 | (match_dup 0))))] | |
1483 | "" | |
52e12ad0 | 1484 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1485 | |
1486 | (define_insn "one_cmplbi2" | |
1487 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1488 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1489 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1490 | "" | |
1491 | "@ | |
1492 | tbit.z %0, %I0 = %1, 0 | |
1493 | xor %0 = 1, %1 | |
1494 | # | |
1495 | #" | |
52e12ad0 | 1496 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1497 | |
1498 | (define_split | |
1499 | [(set (match_operand:BI 0 "register_operand" "") | |
1500 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1501 | (clobber (match_scratch:BI 2 ""))] | |
1502 | "reload_completed | |
1503 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1504 | && rtx_equal_p (operands[0], operands[1])" |
1505 | [(set (match_dup 4) (match_dup 3)) | |
1506 | (set (match_dup 0) (const_int 1)) | |
1507 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1508 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1509 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1510 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1511 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1512 | ||
1513 | (define_split | |
1514 | [(set (match_operand:BI 0 "register_operand" "") | |
1515 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1516 | (clobber (match_scratch:BI 2 ""))] | |
1517 | "reload_completed | |
1518 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1519 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1520 | && ! rtx_equal_p (operands[0], operands[1])" | |
1521 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1522 | (set (match_dup 0) (const_int 0))) | |
1523 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1524 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1525 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1526 | "") |
1527 | ||
1528 | (define_insn "*cmpsi_and_0" | |
1529 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1530 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1531 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1532 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1533 | (match_operand:BI 1 "register_operand" "0")))] | |
1534 | "" | |
1535 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1536 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1537 | |
1538 | (define_insn "*cmpsi_and_1" | |
1539 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1540 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1541 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1542 | (const_int 0)]) | |
1543 | (match_operand:BI 1 "register_operand" "0")))] | |
1544 | "" | |
1545 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1546 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1547 | |
1548 | (define_insn "*cmpsi_andnot_0" | |
1549 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1550 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1551 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1552 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1553 | (match_operand:BI 1 "register_operand" "0")))] | |
1554 | "" | |
1555 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1556 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1557 | |
1558 | (define_insn "*cmpsi_andnot_1" | |
1559 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1560 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1561 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1562 | (const_int 0)])) | |
1563 | (match_operand:BI 1 "register_operand" "0")))] | |
1564 | "" | |
1565 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1566 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1567 | |
1568 | (define_insn "*cmpdi_and_0" | |
1569 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1570 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1571 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1572 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1573 | (match_operand:BI 1 "register_operand" "0")))] | |
1574 | "" | |
1575 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1576 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1577 | |
1578 | (define_insn "*cmpdi_and_1" | |
1579 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1580 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1581 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1582 | (const_int 0)]) | |
1583 | (match_operand:BI 1 "register_operand" "0")))] | |
1584 | "" | |
1585 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1586 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1587 | |
1588 | (define_insn "*cmpdi_andnot_0" | |
1589 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1590 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1591 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1592 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1593 | (match_operand:BI 1 "register_operand" "0")))] | |
1594 | "" | |
1595 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1596 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1597 | |
1598 | (define_insn "*cmpdi_andnot_1" | |
1599 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1600 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1601 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1602 | (const_int 0)])) | |
1603 | (match_operand:BI 1 "register_operand" "0")))] | |
1604 | "" | |
1605 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1606 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1607 | |
1608 | (define_insn "*tbit_and_0" | |
1609 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1610 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1611 | (const_int 1)) | |
1612 | (const_int 0)) | |
c77e04ae | 1613 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1614 | "" |
1615 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1616 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1617 | |
1618 | (define_insn "*tbit_and_1" | |
1619 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1620 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1621 | (const_int 1)) | |
1622 | (const_int 0)) | |
c77e04ae | 1623 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1624 | "" |
1625 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1626 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1627 | |
1628 | (define_insn "*tbit_and_2" | |
1629 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1630 | (and:BI (ne:BI (zero_extract:DI | |
1631 | (match_operand:DI 1 "gr_register_operand" "r") | |
1632 | (const_int 1) | |
5d48891e | 1633 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1634 | (const_int 0)) |
1635 | (match_operand:BI 3 "register_operand" "0")))] | |
1636 | "" | |
1637 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1638 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1639 | |
1640 | (define_insn "*tbit_and_3" | |
1641 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1642 | (and:BI (eq:BI (zero_extract:DI | |
1643 | (match_operand:DI 1 "gr_register_operand" "r") | |
1644 | (const_int 1) | |
5d48891e | 1645 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1646 | (const_int 0)) |
1647 | (match_operand:BI 3 "register_operand" "0")))] | |
1648 | "" | |
1649 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1650 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1651 | |
1652 | (define_insn "*cmpsi_or_0" | |
1653 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1654 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1655 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1656 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1657 | (match_operand:BI 1 "register_operand" "0")))] | |
1658 | "" | |
1659 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1660 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1661 | |
1662 | (define_insn "*cmpsi_or_1" | |
1663 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1664 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1665 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1666 | (const_int 0)]) | |
1667 | (match_operand:BI 1 "register_operand" "0")))] | |
1668 | "" | |
1669 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1670 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1671 | |
1672 | (define_insn "*cmpsi_orcm_0" | |
1673 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1674 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1675 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1676 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1677 | (match_operand:BI 1 "register_operand" "0")))] | |
1678 | "" | |
1679 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1680 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1681 | |
1682 | (define_insn "*cmpsi_orcm_1" | |
1683 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1684 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1685 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1686 | (const_int 0)])) | |
1687 | (match_operand:BI 1 "register_operand" "0")))] | |
1688 | "" | |
1689 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1690 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1691 | |
1692 | (define_insn "*cmpdi_or_0" | |
1693 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1694 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1695 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1696 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1697 | (match_operand:BI 1 "register_operand" "0")))] | |
1698 | "" | |
1699 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1700 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1701 | |
1702 | (define_insn "*cmpdi_or_1" | |
1703 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1704 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1705 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1706 | (const_int 0)]) | |
1707 | (match_operand:BI 1 "register_operand" "0")))] | |
1708 | "" | |
1709 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1710 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1711 | |
1712 | (define_insn "*cmpdi_orcm_0" | |
1713 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1714 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1715 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1716 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1717 | (match_operand:BI 1 "register_operand" "0")))] | |
1718 | "" | |
1719 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1720 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1721 | |
1722 | (define_insn "*cmpdi_orcm_1" | |
1723 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1724 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1725 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1726 | (const_int 0)])) | |
1727 | (match_operand:BI 1 "register_operand" "0")))] | |
1728 | "" | |
1729 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1730 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1731 | |
1732 | (define_insn "*tbit_or_0" | |
1733 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1734 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1735 | (const_int 1)) | |
1736 | (const_int 0)) | |
c77e04ae | 1737 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1738 | "" |
1739 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1740 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1741 | |
1742 | (define_insn "*tbit_or_1" | |
1743 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1744 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1745 | (const_int 1)) | |
1746 | (const_int 0)) | |
c77e04ae | 1747 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1748 | "" |
1749 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1750 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1751 | |
1752 | (define_insn "*tbit_or_2" | |
1753 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1754 | (ior:BI (ne:BI (zero_extract:DI | |
1755 | (match_operand:DI 1 "gr_register_operand" "r") | |
1756 | (const_int 1) | |
5d48891e | 1757 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1758 | (const_int 0)) |
1759 | (match_operand:BI 3 "register_operand" "0")))] | |
1760 | "" | |
1761 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1762 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1763 | |
1764 | (define_insn "*tbit_or_3" | |
1765 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1766 | (ior:BI (eq:BI (zero_extract:DI | |
1767 | (match_operand:DI 1 "gr_register_operand" "r") | |
1768 | (const_int 1) | |
5d48891e | 1769 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1770 | (const_int 0)) |
1771 | (match_operand:BI 3 "register_operand" "0")))] | |
1772 | "" | |
1773 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1774 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1775 | |
1776 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1777 | ||
1778 | (define_split | |
1779 | [(set (match_operand:BI 0 "register_operand" "") | |
1780 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1781 | (const_int 0)) | |
1782 | (match_operand:DI 3 "register_operand" "")) | |
1783 | (const_int 0)))] | |
1784 | "" | |
1785 | [(set (match_dup 0) | |
1786 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1787 | (match_dup 2)))] | |
1788 | "") | |
1789 | ||
1790 | (define_split | |
1791 | [(set (match_operand:BI 0 "register_operand" "") | |
1792 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1793 | (const_int 0)) | |
1794 | (match_operand:DI 3 "register_operand" "")) | |
1795 | (const_int 0)))] | |
1796 | "" | |
1797 | [(set (match_dup 0) | |
1798 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1799 | (match_dup 2))) | |
1800 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1801 | (clobber (scratch))])] | |
1802 | "") | |
1803 | ||
1804 | (define_split | |
1805 | [(set (match_operand:BI 0 "register_operand" "") | |
1806 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1807 | (const_int 0)) | |
1808 | (match_operand:DI 3 "register_operand" "")) | |
1809 | (const_int 0)))] | |
1810 | "" | |
1811 | [(set (match_dup 0) | |
1812 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1813 | (match_dup 2)))] | |
1814 | "") | |
1815 | ||
1816 | (define_split | |
1817 | [(set (match_operand:BI 0 "register_operand" "") | |
1818 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1819 | (const_int 0)) | |
1820 | (match_operand:DI 3 "register_operand" "")) | |
1821 | (const_int 0)))] | |
1822 | "" | |
1823 | [(set (match_dup 0) | |
1824 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1825 | (match_dup 2))) | |
1826 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1827 | (clobber (scratch))])] | |
1828 | "") | |
1829 | ||
1830 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1831 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1832 | ;; nothing bad happens to the comparisons in the meantime. | |
1833 | ;; | |
1834 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1835 | ;; that we're doing height reduction. | |
1836 | ; | |
1837 | ;(define_insn_and_split "" | |
1838 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1839 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1840 | ; [(match_operand 2 "" "") | |
1841 | ; (match_operand 3 "" "")]) | |
1842 | ; (match_operator:BI 4 "comparison_operator" | |
1843 | ; [(match_operand 5 "" "") | |
1844 | ; (match_operand 6 "" "")])) | |
1845 | ; (match_dup 0)))] | |
1846 | ; "flag_schedule_insns" | |
1847 | ; "#" | |
1848 | ; "" | |
1849 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1850 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1851 | ; "") | |
1852 | ; | |
1853 | ;(define_insn_and_split "" | |
1854 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1855 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1856 | ; [(match_operand 2 "" "") | |
1857 | ; (match_operand 3 "" "")]) | |
1858 | ; (match_operator:BI 4 "comparison_operator" | |
1859 | ; [(match_operand 5 "" "") | |
1860 | ; (match_operand 6 "" "")])) | |
1861 | ; (match_dup 0)))] | |
1862 | ; "flag_schedule_insns" | |
1863 | ; "#" | |
1864 | ; "" | |
1865 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1866 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1867 | ; "") | |
1868 | ; | |
1869 | ;(define_split | |
1870 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1871 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1872 | ; [(match_operand 2 "" "") | |
1873 | ; (match_operand 3 "" "")]) | |
1874 | ; (match_operand:BI 7 "register_operand" "")) | |
1875 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1876 | ; [(match_operand 5 "" "") | |
1877 | ; (match_operand 6 "" "")]) | |
1878 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1879 | ; "" | |
1880 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1881 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1882 | ; (match_dup 0)))] | |
1883 | ; "") | |
1884 | ; | |
1885 | ;(define_split | |
1886 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1887 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1888 | ; [(match_operand 2 "" "") | |
1889 | ; (match_operand 3 "" "")]) | |
1890 | ; (match_operand:BI 7 "register_operand" "")) | |
1891 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1892 | ; [(match_operand 5 "" "") | |
1893 | ; (match_operand 6 "" "")]) | |
1894 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1895 | ; "" | |
1896 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
1897 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
1898 | ; (match_dup 0)))] | |
1899 | ; "") | |
1900 | ||
1901 | ;; Try harder to avoid predicate copies by duplicating compares. | |
1902 | ;; Note that we'll have already split the predicate copy, which | |
1903 | ;; is kind of a pain, but oh well. | |
1904 | ||
1905 | (define_peephole2 | |
1906 | [(set (match_operand:BI 0 "register_operand" "") | |
1907 | (match_operand:BI 1 "comparison_operator" "")) | |
1908 | (set (match_operand:CCI 2 "register_operand" "") | |
1909 | (match_operand:CCI 3 "register_operand" "")) | |
1910 | (set (match_operand:CCI 4 "register_operand" "") | |
1911 | (match_operand:CCI 5 "register_operand" "")) | |
1912 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 1913 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1914 | "REGNO (operands[3]) == REGNO (operands[0]) |
1915 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
1916 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
1917 | && REGNO (operands[6]) == REGNO (operands[2])" | |
1918 | [(set (match_dup 0) (match_dup 1)) | |
1919 | (set (match_dup 6) (match_dup 7))] | |
1920 | "operands[7] = copy_rtx (operands[1]);") | |
1921 | \f | |
1922 | ;; :::::::::::::::::::: | |
1923 | ;; :: | |
27a9b99d | 1924 | ;; :: 16-bit Integer arithmetic |
cf1f6ae3 RH |
1925 | ;; :: |
1926 | ;; :::::::::::::::::::: | |
1927 | ||
1928 | (define_insn "mulhi3" | |
1929 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
1930 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
1931 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
1932 | "" | |
2a7ffc85 | 1933 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 1934 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
1935 | |
1936 | \f | |
1937 | ;; :::::::::::::::::::: | |
c65ebc55 | 1938 | ;; :: |
27a9b99d | 1939 | ;; :: 32-bit Integer arithmetic |
c65ebc55 JW |
1940 | ;; :: |
1941 | ;; :::::::::::::::::::: | |
1942 | ||
058557c4 | 1943 | (define_insn "addsi3" |
0551c32d RH |
1944 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
1945 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
1946 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
1947 | "" |
1948 | "@ | |
1d5d7a21 RH |
1949 | add %0 = %1, %2 |
1950 | adds %0 = %2, %1 | |
1951 | addl %0 = %2, %1" | |
52e12ad0 | 1952 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1953 | |
1954 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
1955 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1956 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
1957 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1958 | (const_int 1)))] |
1959 | "" | |
1960 | "add %0 = %1, %2, 1" | |
52e12ad0 | 1961 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1962 | |
5527bf14 | 1963 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
1964 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1965 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
1966 | (const_int 2)) |
1967 | (const_int 1)))] | |
1968 | "" | |
1969 | "add %0 = %1, %1, 1" | |
52e12ad0 | 1970 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 1971 | |
058557c4 | 1972 | (define_insn "*addsi3_shladd" |
0551c32d RH |
1973 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1974 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 1975 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 1976 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 1977 | "" |
058557c4 | 1978 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 1979 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1980 | |
058557c4 | 1981 | (define_insn "subsi3" |
0551c32d RH |
1982 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1983 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
1984 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1985 | "" |
1986 | "sub %0 = %1, %2" | |
52e12ad0 | 1987 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1988 | |
1989 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
1990 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1991 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
1992 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1993 | "" |
1994 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
1995 | [(set_attr "itanium_class" "ialu")]) |
1996 | ||
1997 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 1998 | |
058557c4 | 1999 | (define_insn "mulsi3" |
0551c32d | 2000 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
2001 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
2002 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2003 | "" |
aebf2462 | 2004 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2005 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 2006 | |
655f2eb9 | 2007 | (define_insn "maddsi4" |
11a13704 RH |
2008 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
2009 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
2010 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
2011 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
2012 | "" | |
aebf2462 | 2013 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2014 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 2015 | |
058557c4 | 2016 | (define_insn "negsi2" |
0551c32d RH |
2017 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2018 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2019 | "" |
2020 | "sub %0 = r0, %1" | |
52e12ad0 | 2021 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2022 | |
2023 | (define_expand "abssi2" | |
2024 | [(set (match_dup 2) | |
f2f90c63 | 2025 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2026 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 2027 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2028 | (neg:SI (match_dup 1)) |
2029 | (match_dup 1)))] | |
c65ebc55 | 2030 | "" |
1d5d7a21 | 2031 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2032 | |
2033 | (define_expand "sminsi3" | |
2034 | [(set (match_dup 3) | |
f2f90c63 | 2035 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2036 | (match_operand:SI 2 "gr_register_operand" ""))) |
2037 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2038 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2039 | (match_dup 2) (match_dup 1)))] |
2040 | "" | |
1d5d7a21 | 2041 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2042 | |
2043 | (define_expand "smaxsi3" | |
2044 | [(set (match_dup 3) | |
f2f90c63 | 2045 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2046 | (match_operand:SI 2 "gr_register_operand" ""))) |
2047 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2048 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2049 | (match_dup 1) (match_dup 2)))] |
2050 | "" | |
1d5d7a21 | 2051 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2052 | |
2053 | (define_expand "uminsi3" | |
2054 | [(set (match_dup 3) | |
f2f90c63 | 2055 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2056 | (match_operand:SI 2 "gr_register_operand" ""))) |
2057 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2058 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2059 | (match_dup 2) (match_dup 1)))] |
2060 | "" | |
1d5d7a21 | 2061 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2062 | |
2063 | (define_expand "umaxsi3" | |
2064 | [(set (match_dup 3) | |
f2f90c63 | 2065 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2066 | (match_operand:SI 2 "gr_register_operand" ""))) |
2067 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2068 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2069 | (match_dup 1) (match_dup 2)))] |
2070 | "" | |
1d5d7a21 | 2071 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 2072 | |
655f2eb9 RH |
2073 | (define_expand "divsi3" |
2074 | [(set (match_operand:SI 0 "register_operand" "") | |
2075 | (div:SI (match_operand:SI 1 "general_operand" "") | |
2076 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2077 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2078 | { |
9aec7fb4 | 2079 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2080 | |
02befdf4 | 2081 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2082 | op0_di = gen_reg_rtx (DImode); |
2083 | ||
2084 | if (CONSTANT_P (operands[1])) | |
2085 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2086 | op1_xf = gen_reg_rtx (XFmode); |
2087 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2088 | |
2089 | if (CONSTANT_P (operands[2])) | |
2090 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2091 | op2_xf = gen_reg_rtx (XFmode); |
2092 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 RH |
2093 | |
2094 | /* 2^-34 */ | |
9aec7fb4 SE |
2095 | twon34_exp = gen_reg_rtx (DImode); |
2096 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2097 | twon34 = gen_reg_rtx (XFmode); | |
2098 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2099 | |
85199961 L |
2100 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2101 | CONST1_RTX (SImode))); | |
2102 | ||
02befdf4 | 2103 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2104 | |
02befdf4 | 2105 | emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2106 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2107 | DONE; | |
1d5d7a21 | 2108 | }) |
655f2eb9 RH |
2109 | |
2110 | (define_expand "modsi3" | |
2111 | [(set (match_operand:SI 0 "register_operand" "") | |
2112 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
2113 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2114 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2115 | { |
2116 | rtx op2_neg, op1_di, div; | |
2117 | ||
2118 | div = gen_reg_rtx (SImode); | |
2119 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
2120 | ||
2121 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2122 | ||
2123 | /* This is a trick to get us to reuse the value that we're sure to | |
2124 | have already copied to the FP regs. */ | |
2125 | op1_di = gen_reg_rtx (DImode); | |
2126 | convert_move (op1_di, operands[1], 0); | |
2127 | ||
2128 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2129 | gen_lowpart (SImode, op1_di))); | |
2130 | DONE; | |
1d5d7a21 | 2131 | }) |
655f2eb9 RH |
2132 | |
2133 | (define_expand "udivsi3" | |
2134 | [(set (match_operand:SI 0 "register_operand" "") | |
2135 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
2136 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2137 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2138 | { |
9aec7fb4 | 2139 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2140 | |
02befdf4 | 2141 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2142 | op0_di = gen_reg_rtx (DImode); |
2143 | ||
2144 | if (CONSTANT_P (operands[1])) | |
2145 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2146 | op1_xf = gen_reg_rtx (XFmode); |
2147 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2148 | |
2149 | if (CONSTANT_P (operands[2])) | |
2150 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2151 | op2_xf = gen_reg_rtx (XFmode); |
2152 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 RH |
2153 | |
2154 | /* 2^-34 */ | |
9aec7fb4 SE |
2155 | twon34_exp = gen_reg_rtx (DImode); |
2156 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2157 | twon34 = gen_reg_rtx (XFmode); | |
2158 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2159 | |
85199961 L |
2160 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2161 | CONST1_RTX (SImode))); | |
2162 | ||
02befdf4 | 2163 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2164 | |
02befdf4 | 2165 | emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2166 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2167 | DONE; | |
1d5d7a21 | 2168 | }) |
655f2eb9 RH |
2169 | |
2170 | (define_expand "umodsi3" | |
2171 | [(set (match_operand:SI 0 "register_operand" "") | |
2172 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
2173 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2174 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2175 | { |
2176 | rtx op2_neg, op1_di, div; | |
2177 | ||
2178 | div = gen_reg_rtx (SImode); | |
2179 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
2180 | ||
2181 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2182 | ||
2183 | /* This is a trick to get us to reuse the value that we're sure to | |
2184 | have already copied to the FP regs. */ | |
2185 | op1_di = gen_reg_rtx (DImode); | |
2186 | convert_move (op1_di, operands[1], 1); | |
2187 | ||
2188 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2189 | gen_lowpart (SImode, op1_di))); | |
2190 | DONE; | |
1d5d7a21 | 2191 | }) |
655f2eb9 RH |
2192 | |
2193 | (define_insn_and_split "divsi3_internal" | |
02befdf4 ZW |
2194 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2195 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2196 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2197 | (clobber (match_scratch:XF 4 "=&f")) | |
2198 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2199 | (clobber (match_scratch:BI 6 "=c")) |
02befdf4 ZW |
2200 | (use (match_operand:XF 3 "fr_register_operand" "f"))] |
2201 | "TARGET_INLINE_INT_DIV" | |
655f2eb9 RH |
2202 | "#" |
2203 | "&& reload_completed" | |
02befdf4 | 2204 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2205 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2206 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2207 | (use (const_int 1))]) |
2208 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2209 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2210 | (use (const_int 1))])) |
2211 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2212 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
2213 | (minus:XF (match_dup 7) |
2214 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2215 | (use (const_int 1))])) |
2216 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2217 | (parallel [(set (match_dup 4) | |
02befdf4 | 2218 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2219 | (match_dup 4))) |
2220 | (use (const_int 1))])) | |
2221 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2222 | (parallel [(set (match_dup 5) | |
02befdf4 | 2223 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
655f2eb9 RH |
2224 | (match_dup 3))) |
2225 | (use (const_int 1))])) | |
2226 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2227 | (parallel [(set (match_dup 0) | |
02befdf4 | 2228 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2229 | (match_dup 4))) |
2230 | (use (const_int 1))])) | |
2231 | ] | |
02befdf4 | 2232 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 | 2233 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2234 | \f |
2235 | ;; :::::::::::::::::::: | |
2236 | ;; :: | |
27a9b99d | 2237 | ;; :: 64-bit Integer arithmetic |
c65ebc55 JW |
2238 | ;; :: |
2239 | ;; :::::::::::::::::::: | |
2240 | ||
2241 | (define_insn "adddi3" | |
0551c32d RH |
2242 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2243 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2244 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2245 | "" |
2246 | "@ | |
1d5d7a21 RH |
2247 | add %0 = %1, %2 |
2248 | adds %0 = %2, %1 | |
2249 | addl %0 = %2, %1" | |
52e12ad0 | 2250 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2251 | |
2252 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2253 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2254 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2255 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2256 | (const_int 1)))] |
2257 | "" | |
2258 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2259 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2260 | |
5527bf14 RH |
2261 | ;; This has some of the same problems as shladd. We let the shladd |
2262 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2263 | ;; a register, but not more ugliness here. | |
2264 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2265 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2266 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2267 | (const_int 2)) |
2268 | (const_int 1)))] | |
2269 | "" | |
2270 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2271 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2272 | |
c65ebc55 | 2273 | (define_insn "subdi3" |
0551c32d RH |
2274 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2275 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2276 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2277 | "" |
2278 | "sub %0 = %1, %2" | |
52e12ad0 | 2279 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2280 | |
2281 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2282 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2283 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2284 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2285 | "" |
2286 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2287 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2288 | |
cee58bc0 RH |
2289 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2290 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2291 | (define_insn "muldi3" |
0551c32d | 2292 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2293 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2294 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2295 | "" |
aebf2462 | 2296 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2297 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2298 | |
2299 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2300 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2301 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2302 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2303 | ;; here so that it will be present just in case register elimination gives us | |
2304 | ;; the funny result. | |
2305 | ||
2306 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2307 | ||
2308 | ;; ??? Maybe we should change how adds are canonicalized. | |
2309 | ||
655f2eb9 | 2310 | (define_insn "madddi4" |
0551c32d | 2311 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2312 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2313 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2314 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2315 | (clobber (match_scratch:DI 4 "=X"))] |
2316 | "" | |
aebf2462 | 2317 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2318 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2319 | |
2320 | ;; This can be created by register elimination if operand3 of shladd is an | |
2321 | ;; eliminable register or has reg_equiv_constant set. | |
2322 | ||
2323 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2324 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2325 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2326 | ;; incorrectly. |
2327 | ||
655f2eb9 | 2328 | (define_insn "*madddi4_elim" |
c65ebc55 | 2329 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2330 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2331 | (match_operand:DI 2 "register_operand" "f")) | |
2332 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2333 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2334 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2335 | "reload_in_progress" |
2336 | "#" | |
52e12ad0 | 2337 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2338 | |
c65ebc55 JW |
2339 | (define_split |
2340 | [(set (match_operand:DI 0 "register_operand" "") | |
2341 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2342 | (match_operand:DI 2 "register_operand" "")) | |
2343 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2344 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2345 | (clobber (match_scratch:DI 5 ""))] |
2346 | "reload_completed" | |
2347 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2348 | (match_dup 3))) | |
2349 | (clobber (match_dup 0))]) | |
c65ebc55 | 2350 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2351 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2352 | "") | |
2353 | ||
c65ebc55 | 2354 | (define_insn "smuldi3_highpart" |
0551c32d | 2355 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2356 | (truncate:DI |
2357 | (lshiftrt:TI | |
0551c32d RH |
2358 | (mult:TI (sign_extend:TI |
2359 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2360 | (sign_extend:TI | |
2361 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2362 | (const_int 64))))] |
2363 | "" | |
aebf2462 | 2364 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2365 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2366 | |
2367 | (define_insn "umuldi3_highpart" | |
0551c32d | 2368 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2369 | (truncate:DI |
2370 | (lshiftrt:TI | |
0551c32d RH |
2371 | (mult:TI (zero_extend:TI |
2372 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2373 | (zero_extend:TI | |
2374 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2375 | (const_int 64))))] |
2376 | "" | |
aebf2462 | 2377 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2378 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2379 | |
2380 | (define_insn "negdi2" | |
0551c32d RH |
2381 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2382 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2383 | "" |
2384 | "sub %0 = r0, %1" | |
52e12ad0 | 2385 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2386 | |
2387 | (define_expand "absdi2" | |
2388 | [(set (match_dup 2) | |
f2f90c63 | 2389 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2390 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2391 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2392 | (neg:DI (match_dup 1)) |
2393 | (match_dup 1)))] | |
c65ebc55 | 2394 | "" |
1d5d7a21 | 2395 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2396 | |
2397 | (define_expand "smindi3" | |
2398 | [(set (match_dup 3) | |
f2f90c63 | 2399 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2400 | (match_operand:DI 2 "gr_register_operand" ""))) |
2401 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2402 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2403 | (match_dup 2) (match_dup 1)))] |
2404 | "" | |
1d5d7a21 | 2405 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2406 | |
2407 | (define_expand "smaxdi3" | |
2408 | [(set (match_dup 3) | |
f2f90c63 | 2409 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2410 | (match_operand:DI 2 "gr_register_operand" ""))) |
2411 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2412 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2413 | (match_dup 1) (match_dup 2)))] |
2414 | "" | |
1d5d7a21 | 2415 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2416 | |
2417 | (define_expand "umindi3" | |
2418 | [(set (match_dup 3) | |
f2f90c63 | 2419 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2420 | (match_operand:DI 2 "gr_register_operand" ""))) |
2421 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2422 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2423 | (match_dup 2) (match_dup 1)))] |
2424 | "" | |
1d5d7a21 | 2425 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2426 | |
2427 | (define_expand "umaxdi3" | |
2428 | [(set (match_dup 3) | |
f2f90c63 | 2429 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2430 | (match_operand:DI 2 "gr_register_operand" ""))) |
2431 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2432 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2433 | (match_dup 1) (match_dup 2)))] |
2434 | "" | |
1d5d7a21 | 2435 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2436 | |
2437 | (define_expand "ffsdi2" | |
2438 | [(set (match_dup 6) | |
f2f90c63 | 2439 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2440 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2441 | (set (match_dup 5) (const_int 0)) | |
2442 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2443 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2444 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2445 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2446 | (match_dup 5) (match_dup 4)))] |
2447 | "" | |
c65ebc55 JW |
2448 | { |
2449 | operands[2] = gen_reg_rtx (DImode); | |
2450 | operands[3] = gen_reg_rtx (DImode); | |
2451 | operands[4] = gen_reg_rtx (DImode); | |
2452 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2453 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2454 | }) |
c65ebc55 | 2455 | |
c407570a RH |
2456 | (define_expand "ctzdi2" |
2457 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2458 | (const_int -1))) | |
2459 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2460 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2461 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2462 | (popcount:DI (match_dup 4)))] | |
2463 | "" | |
2464 | { | |
2465 | operands[2] = gen_reg_rtx (DImode); | |
2466 | operands[3] = gen_reg_rtx (DImode); | |
2467 | operands[4] = gen_reg_rtx (DImode); | |
2468 | }) | |
2469 | ||
c407570a RH |
2470 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2471 | (define_expand "clzdi2" | |
2472 | [(set (match_dup 2) | |
02befdf4 | 2473 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" ""))) |
c407570a RH |
2474 | (set (match_dup 3) |
2475 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2476 | (set (match_dup 4) (const_int 65598)) | |
2477 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2478 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2479 | "" |
c407570a | 2480 | { |
02befdf4 | 2481 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2482 | operands[3] = gen_reg_rtx (DImode); |
2483 | operands[4] = gen_reg_rtx (DImode); | |
2484 | }) | |
2485 | ||
2486 | (define_insn "popcountdi2" | |
0551c32d | 2487 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2488 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2489 | "" |
2490 | "popcnt %0 = %1" | |
52e12ad0 | 2491 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2492 | |
ff848f0e RS |
2493 | (define_insn "bswapdi2" |
2494 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
2495 | (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
2496 | "" | |
2497 | "mux1 %0 = %1, @rev" | |
2498 | [(set_attr "itanium_class" "mmshf")]) | |
2499 | ||
02befdf4 | 2500 | (define_insn "*getf_exp_xf" |
c407570a | 2501 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
02befdf4 | 2502 | (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")] |
c407570a | 2503 | UNSPEC_GETF_EXP))] |
02befdf4 | 2504 | "" |
c407570a RH |
2505 | "getf.exp %0 = %1" |
2506 | [(set_attr "itanium_class" "frfr")]) | |
2507 | ||
655f2eb9 RH |
2508 | (define_expand "divdi3" |
2509 | [(set (match_operand:DI 0 "register_operand" "") | |
2510 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2511 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2512 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2513 | { |
02befdf4 | 2514 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2515 | |
02befdf4 | 2516 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2517 | |
2518 | if (CONSTANT_P (operands[1])) | |
2519 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2520 | op1_xf = gen_reg_rtx (XFmode); |
2521 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2522 | |
2523 | if (CONSTANT_P (operands[2])) | |
2524 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2525 | op2_xf = gen_reg_rtx (XFmode); |
2526 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 | 2527 | |
85199961 L |
2528 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2529 | CONST1_RTX (DImode))); | |
2530 | ||
dbdd120f | 2531 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2532 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2533 | else |
02befdf4 | 2534 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2535 | |
02befdf4 | 2536 | emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2537 | DONE; |
1d5d7a21 | 2538 | }) |
655f2eb9 RH |
2539 | |
2540 | (define_expand "moddi3" | |
2541 | [(set (match_operand:DI 0 "register_operand" "") | |
2542 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2543 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2544 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2545 | { |
2546 | rtx op2_neg, div; | |
2547 | ||
2548 | div = gen_reg_rtx (DImode); | |
2549 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2550 | ||
2551 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2552 | ||
2553 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2554 | DONE; | |
1d5d7a21 | 2555 | }) |
655f2eb9 RH |
2556 | |
2557 | (define_expand "udivdi3" | |
2558 | [(set (match_operand:DI 0 "register_operand" "") | |
2559 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2560 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2561 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2562 | { |
02befdf4 | 2563 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2564 | |
02befdf4 | 2565 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2566 | |
2567 | if (CONSTANT_P (operands[1])) | |
2568 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2569 | op1_xf = gen_reg_rtx (XFmode); |
2570 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2571 | |
2572 | if (CONSTANT_P (operands[2])) | |
2573 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2574 | op2_xf = gen_reg_rtx (XFmode); |
2575 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 | 2576 | |
85199961 L |
2577 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2578 | CONST1_RTX (DImode))); | |
2579 | ||
dbdd120f | 2580 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2581 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2582 | else |
02befdf4 | 2583 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2584 | |
02befdf4 | 2585 | emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2586 | DONE; |
1d5d7a21 | 2587 | }) |
655f2eb9 RH |
2588 | |
2589 | (define_expand "umoddi3" | |
2590 | [(set (match_operand:DI 0 "register_operand" "") | |
2591 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2592 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2593 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2594 | { |
2595 | rtx op2_neg, div; | |
2596 | ||
2597 | div = gen_reg_rtx (DImode); | |
2598 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2599 | ||
2600 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2601 | ||
2602 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2603 | DONE; | |
1d5d7a21 | 2604 | }) |
655f2eb9 RH |
2605 | |
2606 | (define_insn_and_split "divdi3_internal_lat" | |
02befdf4 ZW |
2607 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2608 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2609 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2610 | (clobber (match_scratch:XF 3 "=&f")) | |
2611 | (clobber (match_scratch:XF 4 "=&f")) | |
2612 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2613 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 2614 | "TARGET_INLINE_INT_DIV == INL_MIN_LAT" |
655f2eb9 RH |
2615 | "#" |
2616 | "&& reload_completed" | |
02befdf4 | 2617 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2618 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2619 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2620 | (use (const_int 1))]) |
2621 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2622 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2623 | (minus:XF (match_dup 7) |
2624 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2625 | (use (const_int 1))])) |
2626 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2627 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2628 | (use (const_int 1))])) |
2629 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2630 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2631 | (use (const_int 1))])) |
2632 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2633 | (parallel [(set (match_dup 4) | |
02befdf4 | 2634 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
655f2eb9 RH |
2635 | (match_dup 4))) |
2636 | (use (const_int 1))])) | |
2637 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2638 | (parallel [(set (match_dup 0) | |
02befdf4 | 2639 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2640 | (match_dup 0))) |
2641 | (use (const_int 1))])) | |
2642 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2643 | (parallel [(set (match_dup 3) | |
02befdf4 | 2644 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2645 | (match_dup 4))) |
2646 | (use (const_int 1))])) | |
2647 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2648 | (parallel [(set (match_dup 0) | |
02befdf4 | 2649 | (plus:XF (mult:XF (match_dup 5) (match_dup 0)) |
655f2eb9 RH |
2650 | (match_dup 0))) |
2651 | (use (const_int 1))])) | |
2652 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2653 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2654 | (minus:XF (match_dup 1) |
2655 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2656 | (use (const_int 1))])) |
2657 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2658 | (parallel [(set (match_dup 0) | |
02befdf4 | 2659 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2660 | (match_dup 3))) |
2661 | (use (const_int 1))])) | |
2662 | ] | |
02befdf4 | 2663 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 RH |
2664 | [(set_attr "predicable" "no")]) |
2665 | ||
2666 | (define_insn_and_split "divdi3_internal_thr" | |
02befdf4 ZW |
2667 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2668 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2669 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2670 | (clobber (match_scratch:XF 3 "=&f")) | |
2671 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2672 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2673 | "TARGET_INLINE_INT_DIV == INL_MAX_THR" |
655f2eb9 RH |
2674 | "#" |
2675 | "&& reload_completed" | |
02befdf4 | 2676 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2677 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2678 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2679 | (use (const_int 1))]) |
2680 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2681 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2682 | (minus:XF (match_dup 6) |
2683 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2684 | (use (const_int 1))])) |
2685 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2686 | (parallel [(set (match_dup 0) | |
02befdf4 | 2687 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2688 | (match_dup 0))) |
2689 | (use (const_int 1))])) | |
2690 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2691 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2692 | (use (const_int 1))])) |
2693 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2694 | (parallel [(set (match_dup 0) | |
02befdf4 | 2695 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2696 | (match_dup 0))) |
2697 | (use (const_int 1))])) | |
2698 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2699 | (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1))) |
655f2eb9 RH |
2700 | (use (const_int 1))])) |
2701 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2702 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2703 | (minus:XF (match_dup 1) |
2704 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2705 | (use (const_int 1))])) |
2706 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2707 | (parallel [(set (match_dup 0) | |
02befdf4 | 2708 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2709 | (match_dup 3))) |
2710 | (use (const_int 1))])) | |
2711 | ] | |
02befdf4 | 2712 | "operands[6] = CONST1_RTX (XFmode);" |
655f2eb9 | 2713 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2714 | \f |
2715 | ;; :::::::::::::::::::: | |
2716 | ;; :: | |
27a9b99d | 2717 | ;; :: 128-bit Integer arithmetic |
a71aef0b JB |
2718 | ;; :: |
2719 | ;; :::::::::::::::::::: | |
2720 | ||
2721 | (define_insn "addti3" | |
2722 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2723 | (plus:TI (match_operand:TI 1 "gr_register_operand" "%r") | |
2724 | (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI"))) | |
2725 | (clobber (match_scratch:BI 3 "=&c"))] | |
2726 | "" | |
2727 | "#" | |
2728 | [(set_attr "itanium_class" "unknown")]) | |
2729 | ||
2730 | (define_split | |
2731 | [(set (match_operand:TI 0 "register_operand" "") | |
2732 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2733 | (match_operand:TI 2 "register_operand" ""))) | |
2734 | (clobber (match_scratch:BI 3 ""))] | |
2735 | "reload_completed" | |
2736 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2737 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2738 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2739 | (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6)))) | |
2740 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2741 | (set (match_dup 4) | |
2742 | (plus:DI (plus:DI (match_dup 5) (match_dup 6)) | |
2743 | (const_int 1))))] | |
2744 | { | |
2745 | operands[4] = gen_highpart (DImode, operands[0]); | |
2746 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2747 | operands[5] = gen_highpart (DImode, operands[1]); | |
2748 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2749 | operands[6] = gen_highpart (DImode, operands[2]); | |
2750 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2751 | }) | |
2752 | ||
2753 | (define_split | |
2754 | [(set (match_operand:TI 0 "register_operand" "") | |
2755 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2756 | (match_operand:TI 2 "immediate_operand" ""))) | |
2757 | (clobber (match_scratch:BI 3 ""))] | |
2758 | "reload_completed" | |
2759 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2760 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2761 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2762 | (set (match_dup 4) | |
2763 | (plus:DI (match_dup 5) (match_dup 6)))) | |
2764 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2765 | (set (match_dup 4) | |
2766 | (plus:DI (match_dup 5) (match_dup 7))))] | |
2767 | { | |
2768 | operands[4] = gen_highpart (DImode, operands[0]); | |
2769 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2770 | operands[5] = gen_highpart (DImode, operands[1]); | |
2771 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2772 | operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx; | |
2773 | operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx; | |
2774 | }) | |
2775 | ||
2776 | (define_insn "subti3" | |
2777 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2778 | (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK") | |
2779 | (match_operand:TI 2 "gr_register_operand" "r"))) | |
2780 | (clobber (match_scratch:BI 3 "=&c"))] | |
2781 | "" | |
2782 | "#" | |
2783 | [(set_attr "itanium_class" "unknown")]) | |
2784 | ||
2785 | (define_split | |
2786 | [(set (match_operand:TI 0 "register_operand" "") | |
2787 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
2788 | (match_operand:TI 2 "register_operand" ""))) | |
2789 | (clobber (match_scratch:BI 3 "=&c"))] | |
2790 | "reload_completed" | |
2791 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) | |
2792 | (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0))) | |
2793 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2794 | (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6)))) | |
2795 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2796 | (set (match_dup 4) | |
2797 | (plus:DI (not:DI (match_dup 6)) (match_dup 5))))] | |
2798 | { | |
2799 | operands[4] = gen_highpart (DImode, operands[0]); | |
2800 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2801 | operands[5] = gen_highpart (DImode, operands[1]); | |
2802 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2803 | operands[6] = gen_highpart (DImode, operands[2]); | |
2804 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2805 | }) | |
2806 | ||
2807 | (define_split | |
2808 | [(set (match_operand:TI 0 "register_operand" "") | |
2809 | (minus:TI (match_operand:TI 1 "immediate_operand" "") | |
2810 | (match_operand:TI 2 "register_operand" ""))) | |
2811 | (clobber (match_scratch:BI 3 "=&c"))] | |
13f70342 | 2812 | "reload_completed && satisfies_constraint_K (operands[1])" |
a71aef0b JB |
2813 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) |
2814 | (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1))) | |
2815 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2816 | (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5)))) | |
2817 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2818 | (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))] | |
2819 | { | |
2820 | operands[4] = gen_highpart (DImode, operands[0]); | |
2821 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2822 | operands[5] = gen_highpart (DImode, operands[2]); | |
2823 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2824 | operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx; | |
2825 | operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; | |
2826 | }) | |
2827 | ||
2828 | (define_expand "mulditi3" | |
2829 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2830 | (mult:TI (sign_extend:TI | |
2831 | (match_operand:DI 1 "fr_register_operand" "")) | |
2832 | (sign_extend:TI | |
2833 | (match_operand:DI 2 "fr_register_operand" ""))))] | |
2834 | "" | |
2835 | "") | |
2836 | ||
2837 | (define_insn_and_split "*mulditi3_internal" | |
2838 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2839 | (mult:TI (sign_extend:TI | |
2840 | (match_operand:DI 1 "fr_register_operand" "%f")) | |
2841 | (sign_extend:TI | |
2842 | (match_operand:DI 2 "fr_register_operand" "f"))))] | |
2843 | "" | |
2844 | "#" | |
2845 | "reload_completed" | |
2846 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2847 | (set (match_dup 3) (truncate:DI | |
2848 | (lshiftrt:TI | |
2849 | (mult:TI (sign_extend:TI (match_dup 1)) | |
2850 | (sign_extend:TI (match_dup 2))) | |
2851 | (const_int 64))))] | |
2852 | { | |
2853 | operands[3] = gen_highpart (DImode, operands[0]); | |
2854 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2855 | } | |
2856 | [(set_attr "itanium_class" "unknown")]) | |
2857 | ||
2858 | (define_expand "umulditi3" | |
2859 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2860 | (mult:TI (zero_extend:TI | |
2861 | (match_operand:DI 1 "fr_register_operand" "")) | |
2862 | (zero_extend:TI | |
2863 | (match_operand:DI 2 "fr_register_operand" ""))))] | |
2864 | "" | |
2865 | "") | |
2866 | ||
2867 | (define_insn_and_split "*umulditi3_internal" | |
2868 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2869 | (mult:TI (zero_extend:TI | |
2870 | (match_operand:DI 1 "fr_register_operand" "%f")) | |
2871 | (zero_extend:TI | |
2872 | (match_operand:DI 2 "fr_register_operand" "f"))))] | |
2873 | "" | |
2874 | "#" | |
2875 | "reload_completed" | |
2876 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2877 | (set (match_dup 3) (truncate:DI | |
2878 | (lshiftrt:TI | |
2879 | (mult:TI (zero_extend:TI (match_dup 1)) | |
2880 | (zero_extend:TI (match_dup 2))) | |
2881 | (const_int 64))))] | |
2882 | { | |
2883 | operands[3] = gen_highpart (DImode, operands[0]); | |
2884 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2885 | } | |
2886 | [(set_attr "itanium_class" "unknown")]) | |
2887 | ||
2888 | (define_insn_and_split "negti2" | |
2889 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2890 | (neg:TI (match_operand:TI 1 "gr_register_operand" "r"))) | |
2891 | (clobber (match_scratch:BI 2 "=&c"))] | |
2892 | "" | |
2893 | "#" | |
2894 | "reload_completed" | |
2895 | [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0))) | |
2896 | (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1))) | |
2897 | (cond_exec (eq (match_dup 2) (const_int 0)) | |
2898 | (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4)))) | |
2899 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
2900 | (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))] | |
2901 | { | |
2902 | operands[3] = gen_highpart (DImode, operands[0]); | |
2903 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2904 | operands[4] = gen_highpart (DImode, operands[1]); | |
2905 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2906 | } | |
2907 | [(set_attr "itanium_class" "unknown")]) | |
2908 | \f | |
2909 | ;; :::::::::::::::::::: | |
2910 | ;; :: | |
27a9b99d | 2911 | ;; :: 32-bit floating point arithmetic |
c65ebc55 JW |
2912 | ;; :: |
2913 | ;; :::::::::::::::::::: | |
2914 | ||
2915 | (define_insn "addsf3" | |
0551c32d RH |
2916 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2917 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2918 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2919 | "" |
aebf2462 | 2920 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2921 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2922 | |
2923 | (define_insn "subsf3" | |
0551c32d RH |
2924 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2925 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2926 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2927 | "" |
aebf2462 | 2928 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2929 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2930 | |
2931 | (define_insn "mulsf3" | |
0551c32d RH |
2932 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2933 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2934 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2935 | "" |
aebf2462 | 2936 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2937 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2938 | |
2939 | (define_insn "abssf2" | |
0551c32d RH |
2940 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2941 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2942 | "" |
aebf2462 | 2943 | "fabs %0 = %1" |
52e12ad0 | 2944 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2945 | |
2946 | (define_insn "negsf2" | |
0551c32d RH |
2947 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2948 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2949 | "" |
aebf2462 | 2950 | "fneg %0 = %1" |
52e12ad0 | 2951 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2952 | |
2953 | (define_insn "*nabssf2" | |
0551c32d RH |
2954 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2955 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2956 | "" |
aebf2462 | 2957 | "fnegabs %0 = %1" |
52e12ad0 | 2958 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2959 | |
046625fa RH |
2960 | (define_insn "copysignsf3" |
2961 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2962 | (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2963 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2964 | UNSPEC_COPYSIGN))] | |
2965 | "" | |
2966 | "fmerge.s %0 = %F2, %F1" | |
2967 | [(set_attr "itanium_class" "fmisc")]) | |
2968 | ||
2969 | (define_insn "*ncopysignsf3" | |
2970 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2971 | (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2972 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2973 | UNSPEC_COPYSIGN)))] | |
2974 | "" | |
2975 | "fmerge.ns %0 = %F2, %F1" | |
2976 | [(set_attr "itanium_class" "fmisc")]) | |
2977 | ||
7ae4d8d4 | 2978 | (define_insn "sminsf3" |
0551c32d RH |
2979 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2980 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2981 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2982 | "" |
aebf2462 | 2983 | "fmin %0 = %1, %F2" |
52e12ad0 | 2984 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2985 | |
7ae4d8d4 | 2986 | (define_insn "smaxsf3" |
0551c32d RH |
2987 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2988 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2989 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2990 | "" |
aebf2462 | 2991 | "fmax %0 = %1, %F2" |
52e12ad0 | 2992 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2993 | |
655f2eb9 | 2994 | (define_insn "*maddsf4" |
0551c32d RH |
2995 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2996 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2997 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2998 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2999 | "" |
aebf2462 | 3000 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 3001 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3002 | |
655f2eb9 | 3003 | (define_insn "*msubsf4" |
0551c32d RH |
3004 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3005 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3006 | (match_operand:SF 2 "fr_register_operand" "f")) | |
3007 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3008 | "" |
aebf2462 | 3009 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 3010 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3011 | |
3012 | (define_insn "*nmulsf3" | |
0551c32d RH |
3013 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3014 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3015 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3016 | "" |
aebf2462 | 3017 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 3018 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3019 | |
655f2eb9 | 3020 | (define_insn "*nmaddsf4" |
0551c32d | 3021 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
3022 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") |
3023 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3024 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3025 | "" |
aebf2462 | 3026 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 3027 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3028 | |
52ad4d7b ZW |
3029 | (define_insn "*nmaddsf4_alts" |
3030 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3031 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") | |
3032 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3033 | (match_operand:SF 2 "fr_register_operand" "f")))) | |
3034 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3035 | "" | |
3036 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
3037 | [(set_attr "itanium_class" "fmac")]) | |
3038 | ||
26102535 RH |
3039 | (define_expand "divsf3" |
3040 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
3041 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
3042 | (match_operand:SF 2 "fr_register_operand" "")))] | |
02befdf4 | 3043 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3044 | { |
3045 | rtx insn; | |
dbdd120f | 3046 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3047 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); |
3048 | else | |
3049 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
3050 | emit_insn (insn); | |
3051 | DONE; | |
1d5d7a21 | 3052 | }) |
26102535 RH |
3053 | |
3054 | (define_insn_and_split "divsf3_internal_lat" | |
3055 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3056 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3057 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
3058 | (clobber (match_scratch:XF 3 "=&f")) |
3059 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 3060 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 3061 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
3062 | "#" |
3063 | "&& reload_completed" | |
02befdf4 | 3064 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
3065 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3066 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3067 | (use (const_int 0))]) |
26102535 | 3068 | (cond_exec (ne (match_dup 5) (const_int 0)) |
02befdf4 | 3069 | (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6))) |
26102535 RH |
3070 | (use (const_int 1))])) |
3071 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3072 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3073 | (minus:XF (match_dup 10) |
3074 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
3075 | (use (const_int 1))])) |
3076 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3077 | (parallel [(set (match_dup 3) | |
02befdf4 | 3078 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3079 | (match_dup 3))) |
3080 | (use (const_int 1))])) | |
3081 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 3082 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3083 | (use (const_int 1))])) |
3084 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3085 | (parallel [(set (match_dup 3) | |
02befdf4 | 3086 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3087 | (match_dup 3))) |
3088 | (use (const_int 1))])) | |
3089 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 3090 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3091 | (use (const_int 1))])) |
3092 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3093 | (parallel [(set (match_dup 9) | |
3094 | (float_truncate:DF | |
02befdf4 | 3095 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3096 | (match_dup 3)))) |
3097 | (use (const_int 1))])) | |
3098 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3099 | (set (match_dup 0) | |
3100 | (float_truncate:SF (match_dup 6)))) | |
3101 | ] | |
1d5d7a21 | 3102 | { |
02befdf4 ZW |
3103 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3104 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3105 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 3106 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); |
02befdf4 | 3107 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 3108 | } |
26102535 RH |
3109 | [(set_attr "predicable" "no")]) |
3110 | ||
b38ba463 ZW |
3111 | ;; Inline square root. |
3112 | ||
3113 | (define_insn "*sqrt_approx" | |
3114 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3115 | (div:XF (const_int 1) | |
3116 | (sqrt:XF (match_operand:XF 2 "fr_register_operand" "f")))) | |
3117 | (set (match_operand:BI 1 "register_operand" "=c") | |
3118 | (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3119 | (use (match_operand:SI 3 "const_int_operand" "")) ] | |
3120 | "" | |
3121 | "frsqrta.s%3 %0, %1 = %2" | |
3122 | [(set_attr "itanium_class" "fmisc") | |
3123 | (set_attr "predicable" "no")]) | |
3124 | ||
9aec7fb4 | 3125 | (define_insn "setf_exp_xf" |
b38ba463 ZW |
3126 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3127 | (unspec:XF [(match_operand:DI 1 "register_operand" "r")] | |
3128 | UNSPEC_SETF_EXP))] | |
3129 | "" | |
3130 | "setf.exp %0 = %1" | |
3131 | [(set_attr "itanium_class" "frfr")]) | |
3132 | ||
3133 | (define_expand "sqrtsf2" | |
3134 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3135 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
3136 | "TARGET_INLINE_SQRT" | |
3137 | { | |
3138 | rtx insn; | |
b38ba463 | 3139 | #if 0 |
e820471b | 3140 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3141 | insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]); |
e820471b | 3142 | else |
b38ba463 | 3143 | #else |
e820471b | 3144 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3145 | #endif |
e820471b | 3146 | insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3147 | emit_insn (insn); |
3148 | DONE; | |
3149 | }) | |
3150 | ||
3151 | ;; Latency-optimized square root. | |
3152 | ;; FIXME: Implement. | |
3153 | ||
3154 | ;; Throughput-optimized square root. | |
3155 | ||
3156 | (define_insn_and_split "sqrtsf2_internal_thr" | |
3157 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3158 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f"))) | |
3159 | ;; Register r2 in optimization guide. | |
3160 | (clobber (match_scratch:DI 2 "=r")) | |
3161 | ;; Register f8 in optimization guide | |
3162 | (clobber (match_scratch:XF 3 "=&f")) | |
3163 | ;; Register f9 in optimization guide | |
3164 | (clobber (match_scratch:XF 4 "=&f")) | |
3165 | ;; Register f10 in optimization guide | |
3166 | (clobber (match_scratch:XF 5 "=&f")) | |
3167 | ;; Register p6 in optimization guide. | |
3168 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3169 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3170 | "#" |
3171 | "&& reload_completed" | |
3172 | [ ;; exponent of +1/2 in r2 | |
3173 | (set (match_dup 2) (const_int 65534)) | |
3174 | ;; +1/2 in f8 | |
3175 | (set (match_dup 3) | |
3176 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3177 | ;; Step 1 | |
3178 | ;; y0 = 1/sqrt(a) in f7 | |
3179 | (parallel [(set (match_dup 7) | |
3180 | (div:XF (const_int 1) | |
3181 | (sqrt:XF (match_dup 8)))) | |
3182 | (set (match_dup 6) | |
3183 | (unspec:BI [(match_dup 8)] | |
3184 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3185 | (use (const_int 0))]) | |
3186 | ;; Step 2 | |
3187 | ;; H0 = 1/2 * y0 in f9 | |
3188 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3189 | (parallel [(set (match_dup 4) | |
3190 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3191 | (match_dup 9))) | |
3192 | (use (const_int 1))])) | |
3193 | ;; Step 3 | |
3194 | ;; S0 = a * y0 in f7 | |
3195 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3196 | (parallel [(set (match_dup 7) | |
3197 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3198 | (match_dup 9))) | |
3199 | (use (const_int 1))])) | |
3200 | ;; Step 4 | |
3201 | ;; d = 1/2 - S0 * H0 in f10 | |
3202 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3203 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
3204 | (minus:XF (match_dup 3) |
3205 | (mult:XF (match_dup 7) (match_dup 4)))) | |
b38ba463 ZW |
3206 | (use (const_int 1))])) |
3207 | ;; Step 5 | |
3208 | ;; d' = d + 1/2 * d in f8 | |
3209 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3210 | (parallel [(set (match_dup 3) | |
3211 | (plus:XF (mult:XF (match_dup 3) (match_dup 5)) | |
3212 | (match_dup 5))) | |
3213 | (use (const_int 1))])) | |
3214 | ;; Step 6 | |
3215 | ;; e = d + d * d' in f8 | |
3216 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3217 | (parallel [(set (match_dup 3) | |
3218 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) | |
3219 | (match_dup 5))) | |
3220 | (use (const_int 1))])) | |
3221 | ;; Step 7 | |
3222 | ;; S1 = S0 + e * S0 in f7 | |
3223 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3224 | (parallel [(set (match_dup 0) | |
3225 | (float_truncate:SF | |
3226 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3227 | (match_dup 7)))) | |
3228 | (use (const_int 1))])) | |
3229 | ;; Step 8 | |
3230 | ;; H1 = H0 + e * H0 in f8 | |
3231 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3232 | (parallel [(set (match_dup 3) | |
3233 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
3234 | (match_dup 4))) | |
3235 | (use (const_int 1))])) | |
3236 | ;; Step 9 | |
3237 | ;; d1 = a - S1 * S1 in f9 | |
3238 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3239 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3240 | (minus:XF (match_dup 8) |
3241 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3242 | (use (const_int 1))])) |
3243 | ;; Step 10 | |
3244 | ;; S = S1 + d1 * H1 in f7 | |
3245 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3246 | (parallel [(set (match_dup 0) | |
3247 | (float_truncate:SF | |
3248 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3249 | (match_dup 7)))) | |
3250 | (use (const_int 0))]))] | |
3251 | { | |
3252 | /* Generate 82-bit versions of the input and output operands. */ | |
3253 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3254 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3255 | /* Generate required floating-point constants. */ | |
3256 | operands[9] = CONST0_RTX (XFmode); | |
3257 | } | |
3258 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
3259 | \f |
3260 | ;; :::::::::::::::::::: | |
3261 | ;; :: | |
27a9b99d | 3262 | ;; :: 64-bit floating point arithmetic |
c65ebc55 JW |
3263 | ;; :: |
3264 | ;; :::::::::::::::::::: | |
3265 | ||
3266 | (define_insn "adddf3" | |
0551c32d RH |
3267 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3268 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3269 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3270 | "" |
aebf2462 | 3271 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 3272 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3273 | |
26102535 RH |
3274 | (define_insn "*adddf3_trunc" |
3275 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3276 | (float_truncate:SF | |
3277 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3278 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3279 | "" | |
aebf2462 | 3280 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 3281 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3282 | |
c65ebc55 | 3283 | (define_insn "subdf3" |
0551c32d RH |
3284 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3285 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3286 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3287 | "" |
aebf2462 | 3288 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3289 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3290 | |
26102535 RH |
3291 | (define_insn "*subdf3_trunc" |
3292 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3293 | (float_truncate:SF | |
3294 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3295 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3296 | "" | |
aebf2462 | 3297 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3298 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3299 | |
c65ebc55 | 3300 | (define_insn "muldf3" |
0551c32d RH |
3301 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3302 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3303 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 3304 | "" |
aebf2462 | 3305 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 3306 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3307 | |
26102535 RH |
3308 | (define_insn "*muldf3_trunc" |
3309 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3310 | (float_truncate:SF | |
3311 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3312 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
3313 | "" | |
aebf2462 | 3314 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 3315 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3316 | |
c65ebc55 | 3317 | (define_insn "absdf2" |
0551c32d RH |
3318 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3319 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3320 | "" |
aebf2462 | 3321 | "fabs %0 = %1" |
52e12ad0 | 3322 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3323 | |
3324 | (define_insn "negdf2" | |
0551c32d RH |
3325 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3326 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3327 | "" |
aebf2462 | 3328 | "fneg %0 = %1" |
52e12ad0 | 3329 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3330 | |
3331 | (define_insn "*nabsdf2" | |
0551c32d RH |
3332 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3333 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 3334 | "" |
aebf2462 | 3335 | "fnegabs %0 = %1" |
52e12ad0 | 3336 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3337 | |
046625fa RH |
3338 | (define_insn "copysigndf3" |
3339 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3340 | (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3341 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3342 | UNSPEC_COPYSIGN))] | |
3343 | "" | |
3344 | "fmerge.s %0 = %F2, %F1" | |
3345 | [(set_attr "itanium_class" "fmisc")]) | |
3346 | ||
3347 | (define_insn "*ncopysigndf3" | |
3348 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3349 | (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3350 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3351 | UNSPEC_COPYSIGN)))] | |
3352 | "" | |
3353 | "fmerge.ns %0 = %F2, %F1" | |
3354 | [(set_attr "itanium_class" "fmisc")]) | |
3355 | ||
7ae4d8d4 | 3356 | (define_insn "smindf3" |
0551c32d RH |
3357 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3358 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3359 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3360 | "" |
aebf2462 | 3361 | "fmin %0 = %1, %F2" |
52e12ad0 | 3362 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3363 | |
7ae4d8d4 | 3364 | (define_insn "smaxdf3" |
0551c32d RH |
3365 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3366 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3367 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3368 | "" |
aebf2462 | 3369 | "fmax %0 = %1, %F2" |
52e12ad0 | 3370 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3371 | |
655f2eb9 | 3372 | (define_insn "*madddf4" |
0551c32d RH |
3373 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3374 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3375 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3376 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3377 | "" |
aebf2462 | 3378 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 3379 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3380 | |
26102535 RH |
3381 | (define_insn "*madddf4_trunc" |
3382 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3383 | (float_truncate:SF | |
3384 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3385 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3386 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3387 | "" | |
aebf2462 | 3388 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 3389 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3390 | |
655f2eb9 | 3391 | (define_insn "*msubdf4" |
0551c32d RH |
3392 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3393 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3394 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3395 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3396 | "" |
aebf2462 | 3397 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 3398 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3399 | |
26102535 RH |
3400 | (define_insn "*msubdf4_trunc" |
3401 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3402 | (float_truncate:SF | |
3403 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3404 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3405 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3406 | "" | |
aebf2462 | 3407 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 3408 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3409 | |
c65ebc55 | 3410 | (define_insn "*nmuldf3" |
0551c32d RH |
3411 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3412 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3413 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3414 | "" |
aebf2462 | 3415 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 3416 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3417 | |
26102535 RH |
3418 | (define_insn "*nmuldf3_trunc" |
3419 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3420 | (float_truncate:SF | |
3421 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3422 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
3423 | "" | |
aebf2462 | 3424 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 3425 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3426 | |
655f2eb9 | 3427 | (define_insn "*nmadddf4" |
0551c32d | 3428 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
3429 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3430 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3431 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3432 | "" |
aebf2462 | 3433 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 3434 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3435 | |
3436 | (define_insn "*nmadddf4_alts" | |
3437 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3438 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3439 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3440 | (match_operand:DF 2 "fr_register_operand" "f")))) | |
26102535 RH |
3441 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3442 | "" | |
aebf2462 | 3443 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 3444 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3445 | |
52ad4d7b | 3446 | (define_insn "*nmadddf4_truncsf" |
26102535 RH |
3447 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3448 | (float_truncate:SF | |
52ad4d7b ZW |
3449 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3450 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3451 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
26102535 | 3452 | "" |
aebf2462 | 3453 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 3454 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3455 | |
52ad4d7b ZW |
3456 | (define_insn "*nmadddf4_truncsf_alts" |
3457 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3458 | (float_truncate:SF | |
3459 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") | |
3460 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3461 | (match_operand:DF 2 "fr_register_operand" "f"))))) | |
3462 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3463 | "" | |
3464 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
3465 | [(set_attr "itanium_class" "fmac")]) | |
3466 | ||
26102535 RH |
3467 | (define_expand "divdf3" |
3468 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
3469 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
3470 | (match_operand:DF 2 "fr_register_operand" "")))] | |
02befdf4 | 3471 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3472 | { |
3473 | rtx insn; | |
dbdd120f | 3474 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3475 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); |
3476 | else | |
3477 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
3478 | emit_insn (insn); | |
3479 | DONE; | |
1d5d7a21 | 3480 | }) |
26102535 RH |
3481 | |
3482 | (define_insn_and_split "divdf3_internal_lat" | |
3483 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3484 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3485 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
3486 | (clobber (match_scratch:XF 3 "=&f")) |
3487 | (clobber (match_scratch:XF 4 "=&f")) | |
3488 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 3489 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 3490 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
3491 | "#" |
3492 | "&& reload_completed" | |
02befdf4 | 3493 | [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9))) |
086c0f96 RH |
3494 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] |
3495 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3496 | (use (const_int 0))]) |
26102535 | 3497 | (cond_exec (ne (match_dup 6) (const_int 0)) |
02befdf4 | 3498 | (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7))) |
26102535 RH |
3499 | (use (const_int 1))])) |
3500 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3501 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3502 | (minus:XF (match_dup 12) |
3503 | (mult:XF (match_dup 9) (match_dup 7)))) | |
26102535 RH |
3504 | (use (const_int 1))])) |
3505 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3506 | (parallel [(set (match_dup 3) | |
02befdf4 | 3507 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3508 | (match_dup 3))) |
3509 | (use (const_int 1))])) | |
3510 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3511 | (parallel [(set (match_dup 5) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3512 | (use (const_int 1))])) |
3513 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3514 | (parallel [(set (match_dup 7) | |
02befdf4 | 3515 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3516 | (match_dup 7))) |
3517 | (use (const_int 1))])) | |
3518 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3519 | (parallel [(set (match_dup 3) | |
02befdf4 | 3520 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
3521 | (match_dup 3))) |
3522 | (use (const_int 1))])) | |
3523 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3524 | (parallel [(set (match_dup 4) (mult:XF (match_dup 5) (match_dup 5))) |
26102535 RH |
3525 | (use (const_int 1))])) |
3526 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3527 | (parallel [(set (match_dup 7) | |
02befdf4 | 3528 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3529 | (match_dup 7))) |
3530 | (use (const_int 1))])) | |
3531 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3532 | (parallel [(set (match_dup 10) | |
3533 | (float_truncate:DF | |
02befdf4 | 3534 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3535 | (match_dup 3)))) |
3536 | (use (const_int 1))])) | |
3537 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3538 | (parallel [(set (match_dup 7) | |
02befdf4 | 3539 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3540 | (match_dup 7))) |
3541 | (use (const_int 1))])) | |
3542 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3543 | (parallel [(set (match_dup 11) | |
3544 | (float_truncate:DF | |
52ad4d7b ZW |
3545 | (minus:XF (match_dup 8) |
3546 | (mult:XF (match_dup 9) (match_dup 3))))) | |
26102535 RH |
3547 | (use (const_int 1))])) |
3548 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3549 | (set (match_dup 0) | |
02befdf4 | 3550 | (float_truncate:DF (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3551 | (match_dup 3))))) |
3552 | ] | |
1d5d7a21 | 3553 | { |
02befdf4 ZW |
3554 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3555 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3556 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 RH |
3557 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); |
3558 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
02befdf4 | 3559 | operands[12] = CONST1_RTX (XFmode); |
1d5d7a21 | 3560 | } |
26102535 RH |
3561 | [(set_attr "predicable" "no")]) |
3562 | ||
b38ba463 ZW |
3563 | ;; Inline square root. |
3564 | ||
3565 | (define_expand "sqrtdf2" | |
3566 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3567 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
3568 | "TARGET_INLINE_SQRT" | |
3569 | { | |
3570 | rtx insn; | |
b38ba463 | 3571 | #if 0 |
e820471b | 3572 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3573 | insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]); |
e820471b | 3574 | else |
b38ba463 | 3575 | #else |
e820471b | 3576 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3577 | #endif |
e820471b | 3578 | insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3579 | emit_insn (insn); |
3580 | DONE; | |
3581 | }) | |
3582 | ||
3583 | ;; Latency-optimized square root. | |
3584 | ;; FIXME: Implement. | |
3585 | ||
3586 | ;; Throughput-optimized square root. | |
3587 | ||
3588 | (define_insn_and_split "sqrtdf2_internal_thr" | |
3589 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3590 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f"))) | |
3591 | ;; Register r2 in optimization guide. | |
3592 | (clobber (match_scratch:DI 2 "=r")) | |
3593 | ;; Register f8 in optimization guide | |
3594 | (clobber (match_scratch:XF 3 "=&f")) | |
3595 | ;; Register f9 in optimization guide | |
3596 | (clobber (match_scratch:XF 4 "=&f")) | |
3597 | ;; Register f10 in optimization guide | |
3598 | (clobber (match_scratch:XF 5 "=&f")) | |
3599 | ;; Register p6 in optimization guide. | |
3600 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3601 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3602 | "#" |
3603 | "&& reload_completed" | |
3604 | [ ;; exponent of +1/2 in r2 | |
3605 | (set (match_dup 2) (const_int 65534)) | |
3606 | ;; +1/2 in f10 | |
3607 | (set (match_dup 5) | |
3608 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3609 | ;; Step 1 | |
3610 | ;; y0 = 1/sqrt(a) in f7 | |
3611 | (parallel [(set (match_dup 7) | |
3612 | (div:XF (const_int 1) | |
3613 | (sqrt:XF (match_dup 8)))) | |
3614 | (set (match_dup 6) | |
3615 | (unspec:BI [(match_dup 8)] | |
3616 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3617 | (use (const_int 0))]) | |
3618 | ;; Step 2 | |
3619 | ;; H0 = 1/2 * y0 in f8 | |
3620 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3621 | (parallel [(set (match_dup 3) | |
3622 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) | |
3623 | (match_dup 9))) | |
3624 | (use (const_int 1))])) | |
3625 | ;; Step 3 | |
3626 | ;; G0 = a * y0 in f7 | |
3627 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3628 | (parallel [(set (match_dup 7) | |
3629 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3630 | (match_dup 9))) | |
3631 | (use (const_int 1))])) | |
3632 | ;; Step 4 | |
3633 | ;; r0 = 1/2 - G0 * H0 in f9 | |
3634 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3635 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3636 | (minus:XF (match_dup 5) |
3637 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3638 | (use (const_int 1))])) |
3639 | ;; Step 5 | |
3640 | ;; H1 = H0 + r0 * H0 in f8 | |
3641 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3642 | (parallel [(set (match_dup 3) | |
3643 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3644 | (match_dup 3))) | |
3645 | (use (const_int 1))])) | |
3646 | ;; Step 6 | |
3647 | ;; G1 = G0 + r0 * G0 in f7 | |
3648 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3649 | (parallel [(set (match_dup 7) | |
3650 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3651 | (match_dup 7))) | |
3652 | (use (const_int 1))])) | |
3653 | ;; Step 7 | |
3654 | ;; r1 = 1/2 - G1 * H1 in f9 | |
3655 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3656 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3657 | (minus:XF (match_dup 5) |
3658 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3659 | (use (const_int 1))])) |
3660 | ;; Step 8 | |
3661 | ;; H2 = H1 + r1 * H1 in f8 | |
3662 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3663 | (parallel [(set (match_dup 3) | |
3664 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3665 | (match_dup 3))) | |
3666 | (use (const_int 1))])) | |
3667 | ;; Step 9 | |
3668 | ;; G2 = G1 + r1 * G1 in f7 | |
3669 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3670 | (parallel [(set (match_dup 7) | |
3671 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3672 | (match_dup 7))) | |
3673 | (use (const_int 1))])) | |
3674 | ;; Step 10 | |
3675 | ;; d2 = a - G2 * G2 in f9 | |
3676 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3677 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3678 | (minus:XF (match_dup 8) |
3679 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3680 | (use (const_int 1))])) |
3681 | ;; Step 11 | |
3682 | ;; G3 = G2 + d2 * H2 in f7 | |
3683 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3684 | (parallel [(set (match_dup 7) | |
3685 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3686 | (match_dup 7))) | |
3687 | (use (const_int 1))])) | |
3688 | ;; Step 12 | |
3689 | ;; d3 = a - G3 * G3 in f9 | |
3690 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3691 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3692 | (minus:XF (match_dup 8) |
3693 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3694 | (use (const_int 1))])) |
3695 | ;; Step 13 | |
3696 | ;; S = G3 + d3 * H2 in f7 | |
3697 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3698 | (parallel [(set (match_dup 0) | |
3699 | (float_truncate:DF | |
3700 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3701 | (match_dup 7)))) | |
3702 | (use (const_int 0))]))] | |
3703 | { | |
3704 | /* Generate 82-bit versions of the input and output operands. */ | |
3705 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3706 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3707 | /* Generate required floating-point constants. */ | |
3708 | operands[9] = CONST0_RTX (XFmode); | |
3709 | } | |
3710 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3711 | \f |
3712 | ;; :::::::::::::::::::: | |
3713 | ;; :: | |
27a9b99d | 3714 | ;; :: 80-bit floating point arithmetic |
3f622353 RH |
3715 | ;; :: |
3716 | ;; :::::::::::::::::::: | |
3717 | ||
02befdf4 ZW |
3718 | (define_insn "addxf3" |
3719 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3720 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3721 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3722 | "" | |
aebf2462 | 3723 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3724 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3725 | |
02befdf4 | 3726 | (define_insn "*addxf3_truncsf" |
26102535 RH |
3727 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3728 | (float_truncate:SF | |
02befdf4 ZW |
3729 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3730 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3731 | "" | |
aebf2462 | 3732 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3733 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3734 | |
02befdf4 | 3735 | (define_insn "*addxf3_truncdf" |
26102535 RH |
3736 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3737 | (float_truncate:DF | |
02befdf4 ZW |
3738 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3739 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3740 | "" | |
aebf2462 | 3741 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3742 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3743 | |
02befdf4 ZW |
3744 | (define_insn "subxf3" |
3745 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3746 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3747 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3748 | "" | |
aebf2462 | 3749 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3750 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3751 | |
02befdf4 | 3752 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3753 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3754 | (float_truncate:SF | |
02befdf4 ZW |
3755 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3756 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3757 | "" | |
aebf2462 | 3758 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3759 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3760 | |
02befdf4 | 3761 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3762 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3763 | (float_truncate:DF | |
02befdf4 ZW |
3764 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3765 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3766 | "" | |
aebf2462 | 3767 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3768 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3769 | |
02befdf4 ZW |
3770 | (define_insn "mulxf3" |
3771 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3772 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3773 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3774 | "" | |
aebf2462 | 3775 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3776 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3777 | |
02befdf4 | 3778 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3779 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3780 | (float_truncate:SF | |
02befdf4 ZW |
3781 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3782 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3783 | "" | |
aebf2462 | 3784 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3785 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3786 | |
02befdf4 | 3787 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3788 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3789 | (float_truncate:DF | |
02befdf4 ZW |
3790 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3791 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3792 | "" | |
aebf2462 | 3793 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3794 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3795 | |
02befdf4 ZW |
3796 | (define_insn "*mulxf3_alts" |
3797 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3798 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3799 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3800 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3801 | "" |
aebf2462 | 3802 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3803 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3804 | |
02befdf4 | 3805 | (define_insn "*mulxf3_truncsf_alts" |
26102535 RH |
3806 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3807 | (float_truncate:SF | |
02befdf4 ZW |
3808 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3809 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3810 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3811 | "" |
aebf2462 | 3812 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3813 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3814 | |
02befdf4 | 3815 | (define_insn "*mulxf3_truncdf_alts" |
26102535 RH |
3816 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3817 | (float_truncate:DF | |
02befdf4 ZW |
3818 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3819 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3820 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3821 | "" |
aebf2462 | 3822 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3823 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3824 | |
02befdf4 ZW |
3825 | (define_insn "absxf2" |
3826 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3827 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3828 | "" | |
aebf2462 | 3829 | "fabs %0 = %F1" |
52e12ad0 | 3830 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3831 | |
02befdf4 ZW |
3832 | (define_insn "negxf2" |
3833 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3834 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3835 | "" | |
aebf2462 | 3836 | "fneg %0 = %F1" |
52e12ad0 | 3837 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3838 | |
02befdf4 ZW |
3839 | (define_insn "*nabsxf2" |
3840 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3841 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3842 | "" | |
aebf2462 | 3843 | "fnegabs %0 = %F1" |
52e12ad0 | 3844 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3845 | |
046625fa RH |
3846 | (define_insn "copysignxf3" |
3847 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3848 | (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3849 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3850 | UNSPEC_COPYSIGN))] | |
3851 | "" | |
3852 | "fmerge.s %0 = %F2, %F1" | |
3853 | [(set_attr "itanium_class" "fmisc")]) | |
3854 | ||
3855 | (define_insn "*ncopysignxf3" | |
3856 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3857 | (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3858 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3859 | UNSPEC_COPYSIGN)))] | |
3860 | "" | |
3861 | "fmerge.ns %0 = %F2, %F1" | |
3862 | [(set_attr "itanium_class" "fmisc")]) | |
3863 | ||
7ae4d8d4 | 3864 | (define_insn "sminxf3" |
02befdf4 ZW |
3865 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3866 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3867 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3868 | "" | |
aebf2462 | 3869 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3870 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3871 | |
7ae4d8d4 | 3872 | (define_insn "smaxxf3" |
02befdf4 ZW |
3873 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3874 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3875 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3876 | "" | |
aebf2462 | 3877 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3878 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3879 | |
02befdf4 ZW |
3880 | (define_insn "*maddxf4" |
3881 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3882 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3883 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3884 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3885 | "" | |
aebf2462 | 3886 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3887 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3888 | |
02befdf4 | 3889 | (define_insn "*maddxf4_truncsf" |
26102535 RH |
3890 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3891 | (float_truncate:SF | |
02befdf4 ZW |
3892 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3893 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3894 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3895 | "" | |
aebf2462 | 3896 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3897 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3898 | |
02befdf4 | 3899 | (define_insn "*maddxf4_truncdf" |
26102535 RH |
3900 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3901 | (float_truncate:DF | |
02befdf4 ZW |
3902 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3903 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3904 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3905 | "" | |
aebf2462 | 3906 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3907 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3908 | |
02befdf4 ZW |
3909 | (define_insn "*maddxf4_alts" |
3910 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3911 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3912 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3913 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3914 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3915 | "" |
aebf2462 | 3916 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3917 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3918 | |
b38ba463 ZW |
3919 | (define_insn "*maddxf4_alts_truncsf" |
3920 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3921 | (float_truncate:SF | |
3922 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3923 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3924 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
3925 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3926 | "" | |
3927 | "fma.s.s%4 %0 = %F1, %F2, %F3" | |
3928 | [(set_attr "itanium_class" "fmac")]) | |
3929 | ||
02befdf4 | 3930 | (define_insn "*maddxf4_alts_truncdf" |
26102535 RH |
3931 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3932 | (float_truncate:DF | |
02befdf4 ZW |
3933 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3934 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3935 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3936 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3937 | "" |
aebf2462 | 3938 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3939 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3940 | |
02befdf4 ZW |
3941 | (define_insn "*msubxf4" |
3942 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3943 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3944 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3945 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3946 | "" | |
aebf2462 | 3947 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3948 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3949 | |
02befdf4 | 3950 | (define_insn "*msubxf4_truncsf" |
26102535 RH |
3951 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3952 | (float_truncate:SF | |
02befdf4 ZW |
3953 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3954 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3955 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3956 | "" | |
aebf2462 | 3957 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3958 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3959 | |
02befdf4 | 3960 | (define_insn "*msubxf4_truncdf" |
26102535 RH |
3961 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3962 | (float_truncate:DF | |
02befdf4 ZW |
3963 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3964 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3965 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3966 | "" | |
aebf2462 | 3967 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3968 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3969 | |
02befdf4 ZW |
3970 | (define_insn "*nmulxf3" |
3971 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3972 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3973 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3974 | "" | |
aebf2462 | 3975 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3976 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3977 | |
02befdf4 | 3978 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
3979 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3980 | (float_truncate:SF | |
02befdf4 ZW |
3981 | (neg:XF (mult:XF |
3982 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3983 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3984 | "" | |
aebf2462 | 3985 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3986 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3987 | |
02befdf4 | 3988 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
3989 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3990 | (float_truncate:DF | |
02befdf4 ZW |
3991 | (neg:XF (mult:XF |
3992 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3993 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3994 | "" | |
aebf2462 | 3995 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3996 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3997 | |
02befdf4 ZW |
3998 | (define_insn "*nmaddxf4" |
3999 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
4000 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4001 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4002 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4003 | )))] | |
02befdf4 | 4004 | "" |
aebf2462 | 4005 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 4006 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 4007 | |
02befdf4 | 4008 | (define_insn "*nmaddxf4_truncsf" |
26102535 RH |
4009 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
4010 | (float_truncate:SF | |
52ad4d7b ZW |
4011 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4012 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4013 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4014 | ))))] | |
02befdf4 | 4015 | "" |
aebf2462 | 4016 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 4017 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4018 | |
02befdf4 | 4019 | (define_insn "*nmaddxf4_truncdf" |
26102535 RH |
4020 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4021 | (float_truncate:DF | |
52ad4d7b ZW |
4022 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4023 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4024 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4025 | ))))] | |
02befdf4 | 4026 | "" |
aebf2462 | 4027 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 4028 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4029 | |
02befdf4 ZW |
4030 | (define_insn "*nmaddxf4_alts" |
4031 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
4032 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4033 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4034 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4035 | ))) | |
655f2eb9 | 4036 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4037 | "" |
aebf2462 | 4038 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4039 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 4040 | |
52ad4d7b ZW |
4041 | (define_insn "*nmaddxf4_truncsf_alts" |
4042 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
4043 | (float_truncate:SF | |
4044 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") | |
4045 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4046 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4047 | )))) | |
4048 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
4049 | "" | |
4050 | "fnma.s.s%4 %0 = %F1, %F2, %F3" | |
4051 | [(set_attr "itanium_class" "fmac")]) | |
4052 | ||
02befdf4 | 4053 | (define_insn "*nmaddxf4_truncdf_alts" |
26102535 RH |
4054 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4055 | (float_truncate:DF | |
52ad4d7b ZW |
4056 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4057 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4058 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4059 | )))) | |
26102535 | 4060 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4061 | "" |
aebf2462 | 4062 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4063 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4064 | |
02befdf4 ZW |
4065 | (define_expand "divxf3" |
4066 | [(set (match_operand:XF 0 "fr_register_operand" "") | |
4067 | (div:XF (match_operand:XF 1 "fr_register_operand" "") | |
4068 | (match_operand:XF 2 "fr_register_operand" "")))] | |
4069 | "TARGET_INLINE_FLOAT_DIV" | |
26102535 RH |
4070 | { |
4071 | rtx insn; | |
dbdd120f | 4072 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
02befdf4 | 4073 | insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]); |
26102535 | 4074 | else |
02befdf4 | 4075 | insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]); |
26102535 RH |
4076 | emit_insn (insn); |
4077 | DONE; | |
1d5d7a21 | 4078 | }) |
26102535 | 4079 | |
02befdf4 ZW |
4080 | (define_insn_and_split "divxf3_internal_lat" |
4081 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4082 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
4083 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
4084 | (clobber (match_scratch:XF 3 "=&f")) | |
4085 | (clobber (match_scratch:XF 4 "=&f")) | |
4086 | (clobber (match_scratch:XF 5 "=&f")) | |
4087 | (clobber (match_scratch:XF 6 "=&f")) | |
f2f90c63 | 4088 | (clobber (match_scratch:BI 7 "=c"))] |
dbdd120f | 4089 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
4090 | "#" |
4091 | "&& reload_completed" | |
02befdf4 | 4092 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
4093 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] |
4094 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 4095 | (use (const_int 0))]) |
26102535 RH |
4096 | (cond_exec (ne (match_dup 7) (const_int 0)) |
4097 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4098 | (minus:XF (match_dup 8) |
4099 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4100 | (use (const_int 1))])) |
4101 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 4102 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
4103 | (use (const_int 1))])) |
4104 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 4105 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
4106 | (use (const_int 1))])) |
4107 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4108 | (parallel [(set (match_dup 6) | |
02befdf4 | 4109 | (plus:XF (mult:XF (match_dup 3) (match_dup 3)) |
26102535 RH |
4110 | (match_dup 3))) |
4111 | (use (const_int 1))])) | |
4112 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4113 | (parallel [(set (match_dup 3) | |
02befdf4 | 4114 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
26102535 RH |
4115 | (match_dup 3))) |
4116 | (use (const_int 1))])) | |
4117 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4118 | (parallel [(set (match_dup 5) | |
02befdf4 | 4119 | (plus:XF (mult:XF (match_dup 6) (match_dup 0)) |
26102535 RH |
4120 | (match_dup 0))) |
4121 | (use (const_int 1))])) | |
4122 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4123 | (parallel [(set (match_dup 0) | |
02befdf4 | 4124 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
4125 | (match_dup 0))) |
4126 | (use (const_int 1))])) | |
4127 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4128 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4129 | (minus:XF (match_dup 1) |
4130 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
4131 | (use (const_int 1))])) |
4132 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4133 | (parallel [(set (match_dup 3) | |
02befdf4 | 4134 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4135 | (match_dup 4))) |
4136 | (use (const_int 1))])) | |
4137 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4138 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4139 | (minus:XF (match_dup 8) |
4140 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4141 | (use (const_int 1))])) |
4142 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4143 | (parallel [(set (match_dup 0) | |
02befdf4 | 4144 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4145 | (match_dup 0))) |
4146 | (use (const_int 1))])) | |
4147 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4148 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4149 | (minus:XF (match_dup 1) |
4150 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4151 | (use (const_int 1))])) |
4152 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4153 | (set (match_dup 0) | |
02befdf4 | 4154 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4155 | (match_dup 3)))) |
4156 | ] | |
02befdf4 | 4157 | "operands[8] = CONST1_RTX (XFmode);" |
26102535 RH |
4158 | [(set_attr "predicable" "no")]) |
4159 | ||
02befdf4 ZW |
4160 | (define_insn_and_split "divxf3_internal_thr" |
4161 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4162 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
4163 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
4164 | (clobber (match_scratch:XF 3 "=&f")) | |
4165 | (clobber (match_scratch:XF 4 "=&f")) | |
f2f90c63 | 4166 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 4167 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
4168 | "#" |
4169 | "&& reload_completed" | |
02befdf4 | 4170 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
4171 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
4172 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 4173 | (use (const_int 0))]) |
26102535 RH |
4174 | (cond_exec (ne (match_dup 5) (const_int 0)) |
4175 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4176 | (minus:XF (match_dup 6) |
4177 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4178 | (use (const_int 1))])) |
4179 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4180 | (parallel [(set (match_dup 4) | |
02befdf4 | 4181 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4182 | (match_dup 0))) |
4183 | (use (const_int 1))])) | |
4184 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 4185 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
4186 | (use (const_int 1))])) |
4187 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4188 | (parallel [(set (match_dup 3) | |
02befdf4 | 4189 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
26102535 RH |
4190 | (match_dup 4))) |
4191 | (use (const_int 1))])) | |
4192 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 4193 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
4194 | (use (const_int 1))])) |
4195 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4196 | (parallel [(set (match_dup 0) | |
52ad4d7b ZW |
4197 | (minus:XF (match_dup 6) |
4198 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4199 | (use (const_int 1))])) |
4200 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4201 | (parallel [(set (match_dup 0) | |
02befdf4 | 4202 | (plus:XF (mult:XF (match_dup 0) (match_dup 3)) |
26102535 RH |
4203 | (match_dup 3))) |
4204 | (use (const_int 1))])) | |
4205 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4206 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4207 | (minus:XF (match_dup 1) |
4208 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
4209 | (use (const_int 1))])) |
4210 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4211 | (parallel [(set (match_dup 3) | |
02befdf4 | 4212 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4213 | (match_dup 4))) |
4214 | (use (const_int 1))])) | |
4215 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4216 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4217 | (minus:XF (match_dup 6) |
4218 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4219 | (use (const_int 1))])) |
4220 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4221 | (parallel [(set (match_dup 0) | |
02befdf4 | 4222 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4223 | (match_dup 0))) |
4224 | (use (const_int 1))])) | |
4225 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4226 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4227 | (minus:XF (match_dup 1) |
4228 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4229 | (use (const_int 1))])) |
4230 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4231 | (set (match_dup 0) | |
02befdf4 | 4232 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4233 | (match_dup 3)))) |
4234 | ] | |
02befdf4 | 4235 | "operands[6] = CONST1_RTX (XFmode);" |
26102535 RH |
4236 | [(set_attr "predicable" "no")]) |
4237 | ||
b38ba463 ZW |
4238 | ;; Inline square root. |
4239 | ||
4240 | (define_expand "sqrtxf2" | |
4241 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4242 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))] | |
4243 | "TARGET_INLINE_SQRT" | |
4244 | { | |
4245 | rtx insn; | |
b38ba463 | 4246 | #if 0 |
e820471b | 4247 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 4248 | insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]); |
e820471b | 4249 | else |
b38ba463 | 4250 | #else |
e820471b | 4251 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 4252 | #endif |
e820471b | 4253 | insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
4254 | emit_insn (insn); |
4255 | DONE; | |
4256 | }) | |
4257 | ||
4258 | ;; Latency-optimized square root. | |
4259 | ;; FIXME: Implement. | |
4260 | ||
4261 | ;; Throughput-optimized square root. | |
4262 | ||
4263 | (define_insn_and_split "sqrtxf2_internal_thr" | |
4264 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4265 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f"))) | |
4266 | ;; Register r2 in optimization guide. | |
4267 | (clobber (match_scratch:DI 2 "=r")) | |
4268 | ;; Register f8 in optimization guide | |
4269 | (clobber (match_scratch:XF 3 "=&f")) | |
4270 | ;; Register f9 in optimization guide | |
4271 | (clobber (match_scratch:XF 4 "=&f")) | |
4272 | ;; Register f10 in optimization guide | |
4273 | (clobber (match_scratch:XF 5 "=&f")) | |
4274 | ;; Register f11 in optimization guide | |
4275 | (clobber (match_scratch:XF 6 "=&f")) | |
4276 | ;; Register p6 in optimization guide. | |
4277 | (clobber (match_scratch:BI 7 "=c"))] | |
dbdd120f | 4278 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
4279 | "#" |
4280 | "&& reload_completed" | |
4281 | [ ;; exponent of +1/2 in r2 | |
4282 | (set (match_dup 2) (const_int 65534)) | |
4283 | ;; +1/2 in f8. The Intel manual mistakenly specifies f10. | |
4284 | (set (match_dup 3) | |
4285 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
4286 | ;; Step 1 | |
4287 | ;; y0 = 1/sqrt(a) in f7 | |
4288 | (parallel [(set (match_dup 8) | |
4289 | (div:XF (const_int 1) | |
4290 | (sqrt:XF (match_dup 9)))) | |
4291 | (set (match_dup 7) | |
4292 | (unspec:BI [(match_dup 9)] | |
4293 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
4294 | (use (const_int 0))]) | |
4295 | ;; Step 2 | |
4296 | ;; H0 = 1/2 * y0 in f9 | |
4297 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4298 | (parallel [(set (match_dup 4) | |
4299 | (plus:XF (mult:XF (match_dup 3) (match_dup 8)) | |
4300 | (match_dup 10))) | |
4301 | (use (const_int 1))])) | |
4302 | ;; Step 3 | |
4303 | ;; S0 = a * y0 in f7 | |
4304 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4305 | (parallel [(set (match_dup 8) | |
4306 | (plus:XF (mult:XF (match_dup 9) (match_dup 8)) | |
4307 | (match_dup 10))) | |
4308 | (use (const_int 1))])) | |
4309 | ;; Step 4 | |
4310 | ;; d0 = 1/2 - S0 * H0 in f10 | |
4311 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4312 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4313 | (minus:XF (match_dup 3) |
4314 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4315 | (use (const_int 1))])) |
4316 | ;; Step 5 | |
4317 | ;; H1 = H0 + d0 * H0 in f9 | |
4318 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4319 | (parallel [(set (match_dup 4) | |
4320 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4321 | (match_dup 4))) | |
4322 | (use (const_int 1))])) | |
4323 | ;; Step 6 | |
4324 | ;; S1 = S0 + d0 * S0 in f7 | |
4325 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4326 | (parallel [(set (match_dup 8) | |
4327 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4328 | (match_dup 8))) | |
4329 | (use (const_int 1))])) | |
4330 | ;; Step 7 | |
4331 | ;; d1 = 1/2 - S1 * H1 in f10 | |
4332 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4333 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4334 | (minus:XF (match_dup 3) |
4335 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4336 | (use (const_int 1))])) |
4337 | ;; Step 8 | |
4338 | ;; H2 = H1 + d1 * H1 in f9 | |
4339 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4340 | (parallel [(set (match_dup 4) | |
4341 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4342 | (match_dup 4))) | |
4343 | (use (const_int 1))])) | |
4344 | ;; Step 9 | |
4345 | ;; S2 = S1 + d1 * S1 in f7 | |
4346 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4347 | (parallel [(set (match_dup 8) | |
4348 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4349 | (match_dup 8))) | |
4350 | (use (const_int 1))])) | |
4351 | ;; Step 10 | |
4352 | ;; d2 = 1/2 - S2 * H2 in f10 | |
4353 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4354 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4355 | (minus:XF (match_dup 3) |
4356 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4357 | (use (const_int 1))])) |
4358 | ;; Step 11 | |
4359 | ;; e2 = a - S2 * S2 in f8 | |
4360 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4361 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4362 | (minus:XF (match_dup 9) |
4363 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4364 | (use (const_int 1))])) |
4365 | ;; Step 12 | |
4366 | ;; S3 = S2 + e2 * H2 in f7 | |
4367 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4368 | (parallel [(set (match_dup 8) | |
4369 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4370 | (match_dup 8))) | |
4371 | (use (const_int 1))])) | |
4372 | ;; Step 13 | |
4373 | ;; H3 = H2 + d2 * H2 in f9 | |
4374 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4375 | (parallel [(set (match_dup 4) | |
4376 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4377 | (match_dup 4))) | |
4378 | (use (const_int 1))])) | |
4379 | ;; Step 14 | |
4380 | ;; e3 = a - S3 * S3 in f8 | |
4381 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4382 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4383 | (minus:XF (match_dup 9) |
4384 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4385 | (use (const_int 1))])) |
4386 | ;; Step 15 | |
4387 | ;; S = S3 + e3 * H3 in f7 | |
4388 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4389 | (parallel [(set (match_dup 0) | |
4390 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4391 | (match_dup 8))) | |
4392 | (use (const_int 0))]))] | |
4393 | { | |
4394 | /* Generate 82-bit versions of the input and output operands. */ | |
4395 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
4396 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
4397 | /* Generate required floating-point constants. */ | |
4398 | operands[10] = CONST0_RTX (XFmode); | |
4399 | } | |
4400 | [(set_attr "predicable" "no")]) | |
4401 | ||
26102535 RH |
4402 | ;; ??? frcpa works like cmp.foo.unc. |
4403 | ||
655f2eb9 | 4404 | (define_insn "*recip_approx" |
02befdf4 ZW |
4405 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
4406 | (div:XF (const_int 1) | |
4407 | (match_operand:XF 3 "fr_register_operand" "f"))) | |
f2f90c63 | 4408 | (set (match_operand:BI 1 "register_operand" "=c") |
02befdf4 | 4409 | (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f") |
086c0f96 | 4410 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 4411 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4412 | "" |
655f2eb9 | 4413 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 4414 | [(set_attr "itanium_class" "fmisc") |
26102535 | 4415 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4416 | \f |
4417 | ;; :::::::::::::::::::: | |
4418 | ;; :: | |
27a9b99d | 4419 | ;; :: 32-bit Integer Shifts and Rotates |
c65ebc55 JW |
4420 | ;; :: |
4421 | ;; :::::::::::::::::::: | |
4422 | ||
9c668921 | 4423 | (define_expand "ashlsi3" |
0551c32d RH |
4424 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4425 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
4426 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 4427 | "" |
9c668921 RH |
4428 | { |
4429 | if (GET_CODE (operands[2]) != CONST_INT) | |
4430 | { | |
4431 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
4432 | we've got to get rid of stray bits outside the SImode register. */ | |
4433 | rtx subshift = gen_reg_rtx (DImode); | |
4434 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
4435 | operands[2] = subshift; | |
4436 | } | |
1d5d7a21 | 4437 | }) |
9c668921 RH |
4438 | |
4439 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
4440 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
4441 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
4442 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 4443 | "" |
041f25e6 RH |
4444 | "@ |
4445 | shladd %0 = %1, %2, r0 | |
4446 | dep.z %0 = %1, %2, %E2 | |
4447 | shl %0 = %1, %2" | |
52e12ad0 | 4448 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
4449 | |
4450 | (define_expand "ashrsi3" | |
0551c32d RH |
4451 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4452 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4453 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4454 | "" |
c65ebc55 | 4455 | { |
041f25e6 RH |
4456 | rtx subtarget = gen_reg_rtx (DImode); |
4457 | if (GET_CODE (operands[2]) == CONST_INT) | |
4458 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
4459 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4460 | else | |
4461 | { | |
9c668921 | 4462 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4463 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4464 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4465 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4466 | } |
4467 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4468 | DONE; | |
1d5d7a21 | 4469 | }) |
c65ebc55 | 4470 | |
c65ebc55 | 4471 | (define_expand "lshrsi3" |
0551c32d RH |
4472 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4473 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4474 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4475 | "" |
c65ebc55 | 4476 | { |
041f25e6 RH |
4477 | rtx subtarget = gen_reg_rtx (DImode); |
4478 | if (GET_CODE (operands[2]) == CONST_INT) | |
4479 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
4480 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4481 | else | |
4482 | { | |
9c668921 | 4483 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4484 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4485 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4486 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4487 | } |
4488 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4489 | DONE; | |
1d5d7a21 | 4490 | }) |
c65ebc55 | 4491 | |
c65ebc55 | 4492 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
4493 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
4494 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
4495 | |
4496 | (define_expand "rotrsi3" | |
66db6b45 RH |
4497 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4498 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
4499 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
4500 | "" | |
66db6b45 RH |
4501 | { |
4502 | if (GET_MODE (operands[2]) != VOIDmode) | |
4503 | { | |
4504 | rtx tmp = gen_reg_rtx (DImode); | |
4505 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
4506 | operands[2] = tmp; | |
4507 | } | |
1d5d7a21 | 4508 | }) |
66db6b45 RH |
4509 | |
4510 | (define_insn_and_split "*rotrsi3_internal" | |
4511 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
4512 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4513 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
4514 | "" | |
4515 | "#" | |
4516 | "reload_completed" | |
c65ebc55 | 4517 | [(set (match_dup 3) |
66db6b45 | 4518 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
4519 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
4520 | (set (match_dup 3) | |
66db6b45 RH |
4521 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
4522 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
4523 | ||
4524 | (define_expand "rotlsi3" | |
4525 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
4526 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
4527 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4528 | "" |
c65ebc55 JW |
4529 | { |
4530 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
4531 | { |
4532 | rtx tmp = gen_reg_rtx (SImode); | |
4533 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
4534 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
4535 | DONE; | |
4536 | } | |
1d5d7a21 | 4537 | }) |
66db6b45 RH |
4538 | |
4539 | (define_insn_and_split "*rotlsi3_internal" | |
4540 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
4541 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4542 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
4543 | "" | |
51094457 JB |
4544 | "mux2 %0 = %1, 0xe1" |
4545 | "reload_completed && INTVAL (operands[2]) != 16" | |
66db6b45 RH |
4546 | [(set (match_dup 3) |
4547 | (ior:DI (zero_extend:DI (match_dup 1)) | |
4548 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
4549 | (set (match_dup 3) | |
4550 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
4551 | { |
4552 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
4553 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
51094457 JB |
4554 | } |
4555 | [(set_attr "itanium_class" "mmshf")]) | |
c65ebc55 JW |
4556 | \f |
4557 | ;; :::::::::::::::::::: | |
4558 | ;; :: | |
27a9b99d | 4559 | ;; :: 64-bit Integer Shifts and Rotates |
c65ebc55 JW |
4560 | ;; :: |
4561 | ;; :::::::::::::::::::: | |
4562 | ||
4563 | (define_insn "ashldi3" | |
52e12ad0 BS |
4564 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
4565 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
4566 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 4567 | "" |
041f25e6 RH |
4568 | "@ |
4569 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 4570 | shl %0 = %1, %2 |
041f25e6 | 4571 | shl %0 = %1, %2" |
52e12ad0 | 4572 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
4573 | |
4574 | ;; ??? Maybe combine this with the multiply and add instruction? | |
4575 | ||
4576 | (define_insn "*shladd" | |
0551c32d RH |
4577 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4578 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4579 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 4580 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
4581 | "" |
4582 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 4583 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4584 | |
4585 | ;; This can be created by register elimination if operand3 of shladd is an | |
4586 | ;; eliminable register or has reg_equiv_constant set. | |
4587 | ||
4588 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
4589 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
4590 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
4591 | ;; incorrectly. | |
4592 | ||
5527bf14 | 4593 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
4594 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
4595 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4596 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 4597 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
4598 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
4599 | "reload_in_progress" | |
e820471b | 4600 | "* gcc_unreachable ();" |
c65ebc55 JW |
4601 | "reload_completed" |
4602 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
4603 | (match_dup 3))) | |
c65ebc55 | 4604 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 4605 | "" |
52e12ad0 | 4606 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4607 | |
4608 | (define_insn "ashrdi3" | |
52e12ad0 BS |
4609 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4610 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4611 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4612 | "" |
52e12ad0 BS |
4613 | "@ |
4614 | shr %0 = %1, %2 | |
4615 | shr %0 = %1, %2" | |
4616 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4617 | |
4618 | (define_insn "lshrdi3" | |
52e12ad0 BS |
4619 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4620 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4621 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4622 | "" |
52e12ad0 BS |
4623 | "@ |
4624 | shr.u %0 = %1, %2 | |
4625 | shr.u %0 = %1, %2" | |
4626 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4627 | |
4628 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
4629 | ;; will load the operand into a register and call the pattern if the predicate | |
4630 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
4631 | ;; verify that we have an appropriate constant in the expander. | |
4632 | ||
4633 | (define_expand "rotrdi3" | |
0551c32d RH |
4634 | [(set (match_operand:DI 0 "gr_register_operand" "") |
4635 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
4636 | (match_operand:DI 2 "nonmemory_operand" "")))] |
4637 | "" | |
c65ebc55 JW |
4638 | { |
4639 | if (! shift_count_operand (operands[2], DImode)) | |
4640 | FAIL; | |
1d5d7a21 | 4641 | }) |
c65ebc55 JW |
4642 | |
4643 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
4644 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4645 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4646 | (match_operand:DI 2 "shift_count_operand" "M")))] |
4647 | "" | |
4648 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 4649 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 4650 | |
66db6b45 RH |
4651 | (define_expand "rotldi3" |
4652 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4653 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
4654 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4655 | "" | |
66db6b45 RH |
4656 | { |
4657 | if (! shift_count_operand (operands[2], DImode)) | |
4658 | FAIL; | |
1d5d7a21 | 4659 | }) |
66db6b45 RH |
4660 | |
4661 | (define_insn "*rotldi3_internal" | |
4662 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4663 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
4664 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
4665 | "" | |
4666 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 4667 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
4668 | \f |
4669 | ;; :::::::::::::::::::: | |
4670 | ;; :: | |
27a9b99d | 4671 | ;; :: 128-bit Integer Shifts and Rotates |
f526a3c8 RH |
4672 | ;; :: |
4673 | ;; :::::::::::::::::::: | |
4674 | ||
16d8386b JB |
4675 | (define_expand "ashlti3" |
4676 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4677 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "") | |
4678 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4679 | "" | |
4680 | { | |
4681 | if (!dshift_count_operand (operands[2], DImode)) | |
4682 | FAIL; | |
4683 | }) | |
4684 | ||
4685 | (define_insn_and_split "*ashlti3_internal" | |
4686 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4687 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4688 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4689 | "" | |
4690 | "#" | |
4691 | "reload_completed" | |
4692 | [(const_int 0)] | |
4693 | { | |
4694 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
4695 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4696 | rtx rh = gen_highpart (DImode, operands[0]); | |
4697 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4698 | rtx shiftlo = GEN_INT (shift & 63); | |
4699 | ||
4700 | if (shift & 64) | |
4701 | { | |
4702 | emit_move_insn (rl, const0_rtx); | |
4703 | if (shift & 63) | |
4704 | emit_insn (gen_ashldi3 (rh, lo, shiftlo)); | |
4705 | else | |
4706 | emit_move_insn (rh, lo); | |
4707 | } | |
4708 | else | |
4709 | { | |
4710 | rtx hi = gen_highpart (DImode, operands[1]); | |
4711 | ||
4712 | emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63))); | |
4713 | emit_insn (gen_ashldi3 (rl, lo, shiftlo)); | |
4714 | } | |
4715 | DONE; | |
4716 | }) | |
4717 | ||
f526a3c8 RH |
4718 | (define_expand "ashrti3" |
4719 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4720 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4721 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4722 | "" | |
4723 | { | |
4724 | if (!dshift_count_operand (operands[2], DImode)) | |
4725 | FAIL; | |
4726 | }) | |
4727 | ||
4728 | (define_insn_and_split "*ashrti3_internal" | |
16d8386b | 4729 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4730 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4731 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4732 | "" | |
4733 | "#" | |
4734 | "reload_completed" | |
4735 | [(const_int 0)] | |
4736 | { | |
4737 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4738 | rtx rl = gen_lowpart (DImode, operands[0]); |
4739 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4740 | rtx hi = gen_highpart (DImode, operands[1]); |
4741 | rtx shiftlo = GEN_INT (shift & 63); | |
4742 | ||
4743 | if (shift & 64) | |
4744 | { | |
16d8386b JB |
4745 | if (shift & 63) |
4746 | emit_insn (gen_ashrdi3 (rl, hi, shiftlo)); | |
4747 | else | |
4748 | emit_move_insn (rl, hi); | |
4749 | emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63))); | |
f526a3c8 RH |
4750 | } |
4751 | else | |
4752 | { | |
16d8386b JB |
4753 | rtx lo = gen_lowpart (DImode, operands[1]); |
4754 | ||
4755 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4756 | emit_insn (gen_ashrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4757 | } |
4758 | DONE; | |
4759 | }) | |
4760 | ||
4761 | (define_expand "lshrti3" | |
4762 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4763 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4764 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4765 | "" | |
4766 | { | |
4767 | if (!dshift_count_operand (operands[2], DImode)) | |
4768 | FAIL; | |
4769 | }) | |
4770 | ||
4771 | (define_insn_and_split "*lshrti3_internal" | |
16d8386b | 4772 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4773 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4774 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4775 | "" | |
4776 | "#" | |
4777 | "reload_completed" | |
4778 | [(const_int 0)] | |
4779 | { | |
4780 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4781 | rtx rl = gen_lowpart (DImode, operands[0]); |
4782 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4783 | rtx hi = gen_highpart (DImode, operands[1]); |
4784 | rtx shiftlo = GEN_INT (shift & 63); | |
4785 | ||
4786 | if (shift & 64) | |
4787 | { | |
16d8386b JB |
4788 | if (shift & 63) |
4789 | emit_insn (gen_lshrdi3 (rl, hi, shiftlo)); | |
4790 | else | |
4791 | emit_move_insn (rl, hi); | |
4792 | emit_move_insn (rh, const0_rtx); | |
f526a3c8 RH |
4793 | } |
4794 | else | |
4795 | { | |
16d8386b JB |
4796 | rtx lo = gen_lowpart (DImode, operands[1]); |
4797 | ||
4798 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4799 | emit_insn (gen_lshrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4800 | } |
4801 | DONE; | |
4802 | }) | |
4803 | ||
a71aef0b JB |
4804 | (define_expand "rotlti3" |
4805 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4806 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "") | |
4807 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4808 | "" | |
4809 | { | |
4810 | if (! dshift_count_operand (operands[2], DImode)) | |
4811 | FAIL; | |
4812 | }) | |
4813 | ||
4814 | (define_insn_and_split "*rotlti3_internal" | |
4815 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4816 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4817 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4818 | "" | |
4819 | "#" | |
4820 | "reload_completed" | |
4821 | [(const_int 0)] | |
4822 | { | |
4823 | HOST_WIDE_INT count = INTVAL (operands[2]); | |
4824 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4825 | rtx rh = gen_highpart (DImode, operands[0]); | |
4826 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4827 | rtx hi = gen_highpart (DImode, operands[1]); | |
4828 | rtx countlo = GEN_INT (-count & 63); | |
4829 | ||
4830 | if (count & 64) | |
4831 | { | |
4832 | if (count & 63) | |
4833 | { | |
4834 | emit_insn (gen_shrp (rl, hi, lo, countlo)); | |
4835 | emit_insn (gen_shrp (rh, lo, hi, countlo)); | |
4836 | } | |
4837 | else | |
4838 | { | |
4839 | emit_move_insn (rl, hi); | |
4840 | emit_move_insn (rh, lo); | |
4841 | } | |
4842 | } | |
4843 | else | |
4844 | { | |
4845 | emit_insn (gen_shrp (rl, lo, hi, countlo)); | |
4846 | emit_insn (gen_shrp (rh, hi, lo, countlo)); | |
4847 | } | |
4848 | DONE; | |
4849 | } | |
4850 | [(set_attr "itanium_class" "unknown")]) | |
4851 | ||
f526a3c8 RH |
4852 | (define_insn "shrp" |
4853 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4854 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
4855 | (match_operand:DI 2 "gr_register_operand" "r") | |
4856 | (match_operand:DI 3 "shift_count_operand" "M")] | |
4857 | UNSPEC_SHRP))] | |
4858 | "" | |
4859 | "shrp %0 = %1, %2, %3" | |
4860 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
4861 | \f |
4862 | ;; :::::::::::::::::::: | |
4863 | ;; :: | |
27a9b99d | 4864 | ;; :: 32-bit Integer Logical operations |
c65ebc55 JW |
4865 | ;; :: |
4866 | ;; :::::::::::::::::::: | |
4867 | ||
4868 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
4869 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
4870 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
4871 | ;; This doesn't work for unary logical operations, because we don't call | |
4872 | ;; apply_distributive_law for them. | |
4873 | ||
4874 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
4875 | ;; apply_distributive_law. We get inefficient code for | |
4876 | ;; int sub4 (int i, int j) { return i & ~j; } | |
4877 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
4878 | ;; (zero_extend (and (not A) B)) in combine. | |
4879 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
4880 | ;; one_cmplsi2 pattern. | |
4881 | ||
058557c4 | 4882 | (define_insn "one_cmplsi2" |
0551c32d RH |
4883 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4884 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4885 | "" |
4886 | "andcm %0 = -1, %1" | |
52e12ad0 | 4887 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4888 | \f |
4889 | ;; :::::::::::::::::::: | |
4890 | ;; :: | |
27a9b99d | 4891 | ;; :: 64-bit Integer Logical operations |
c65ebc55 JW |
4892 | ;; :: |
4893 | ;; :::::::::::::::::::: | |
4894 | ||
4895 | (define_insn "anddi3" | |
0551c32d RH |
4896 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4897 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4898 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4899 | "" |
4900 | "@ | |
4901 | and %0 = %2, %1 | |
aebf2462 | 4902 | fand %0 = %2, %1" |
52e12ad0 | 4903 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4904 | |
4905 | (define_insn "*andnot" | |
0551c32d RH |
4906 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4907 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
4908 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4909 | "" |
4910 | "@ | |
4911 | andcm %0 = %2, %1 | |
aebf2462 | 4912 | fandcm %0 = %2, %1" |
52e12ad0 | 4913 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4914 | |
4915 | (define_insn "iordi3" | |
0551c32d RH |
4916 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4917 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4918 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4919 | "" |
4920 | "@ | |
4921 | or %0 = %2, %1 | |
aebf2462 | 4922 | for %0 = %2, %1" |
52e12ad0 | 4923 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4924 | |
4925 | (define_insn "xordi3" | |
0551c32d RH |
4926 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4927 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4928 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4929 | "" |
4930 | "@ | |
4931 | xor %0 = %2, %1 | |
aebf2462 | 4932 | fxor %0 = %2, %1" |
52e12ad0 | 4933 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4934 | |
4935 | (define_insn "one_cmpldi2" | |
0551c32d RH |
4936 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4937 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4938 | "" |
4939 | "andcm %0 = -1, %1" | |
52e12ad0 | 4940 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4941 | \f |
4942 | ;; :::::::::::::::::::: | |
4943 | ;; :: | |
4944 | ;; :: Comparisons | |
4945 | ;; :: | |
4946 | ;; :::::::::::::::::::: | |
4947 | ||
f2f90c63 RH |
4948 | (define_expand "cmpbi" |
4949 | [(set (cc0) | |
4950 | (compare (match_operand:BI 0 "register_operand" "") | |
4951 | (match_operand:BI 1 "const_int_operand" "")))] | |
4952 | "" | |
f2f90c63 RH |
4953 | { |
4954 | ia64_compare_op0 = operands[0]; | |
4955 | ia64_compare_op1 = operands[1]; | |
4956 | DONE; | |
1d5d7a21 | 4957 | }) |
f2f90c63 | 4958 | |
c65ebc55 JW |
4959 | (define_expand "cmpsi" |
4960 | [(set (cc0) | |
0551c32d RH |
4961 | (compare (match_operand:SI 0 "gr_register_operand" "") |
4962 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4963 | "" |
c65ebc55 JW |
4964 | { |
4965 | ia64_compare_op0 = operands[0]; | |
4966 | ia64_compare_op1 = operands[1]; | |
4967 | DONE; | |
1d5d7a21 | 4968 | }) |
c65ebc55 JW |
4969 | |
4970 | (define_expand "cmpdi" | |
4971 | [(set (cc0) | |
0551c32d RH |
4972 | (compare (match_operand:DI 0 "gr_register_operand" "") |
4973 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4974 | "" |
c65ebc55 JW |
4975 | { |
4976 | ia64_compare_op0 = operands[0]; | |
4977 | ia64_compare_op1 = operands[1]; | |
4978 | DONE; | |
1d5d7a21 | 4979 | }) |
c65ebc55 JW |
4980 | |
4981 | (define_expand "cmpsf" | |
4982 | [(set (cc0) | |
0551c32d RH |
4983 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
4984 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4985 | "" |
c65ebc55 JW |
4986 | { |
4987 | ia64_compare_op0 = operands[0]; | |
4988 | ia64_compare_op1 = operands[1]; | |
4989 | DONE; | |
1d5d7a21 | 4990 | }) |
c65ebc55 JW |
4991 | |
4992 | (define_expand "cmpdf" | |
4993 | [(set (cc0) | |
0551c32d RH |
4994 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
4995 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4996 | "" |
c65ebc55 JW |
4997 | { |
4998 | ia64_compare_op0 = operands[0]; | |
4999 | ia64_compare_op1 = operands[1]; | |
5000 | DONE; | |
1d5d7a21 | 5001 | }) |
c65ebc55 | 5002 | |
02befdf4 | 5003 | (define_expand "cmpxf" |
c65ebc55 | 5004 | [(set (cc0) |
02befdf4 ZW |
5005 | (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "") |
5006 | (match_operand:XF 1 "xfreg_or_fp01_operand" "")))] | |
5007 | "" | |
c65ebc55 JW |
5008 | { |
5009 | ia64_compare_op0 = operands[0]; | |
5010 | ia64_compare_op1 = operands[1]; | |
5011 | DONE; | |
1d5d7a21 | 5012 | }) |
c65ebc55 | 5013 | |
24ea7948 ZW |
5014 | (define_expand "cmptf" |
5015 | [(set (cc0) | |
5016 | (compare (match_operand:TF 0 "gr_register_operand" "") | |
5017 | (match_operand:TF 1 "gr_register_operand" "")))] | |
5018 | "TARGET_HPUX" | |
5019 | { | |
5020 | ia64_compare_op0 = operands[0]; | |
5021 | ia64_compare_op1 = operands[1]; | |
5022 | DONE; | |
5023 | }) | |
5024 | ||
c65ebc55 | 5025 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
5026 | [(set (match_operand:BI 0 "register_operand" "=c") |
5027 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
5028 | [(match_operand:SI 2 "gr_register_operand" "r") |
5029 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
5030 | "" |
5031 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 5032 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 5033 | |
18a3c539 JW |
5034 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
5035 | ;; unsigned comparisons don't accept immediate operands of zero. | |
5036 | ||
c65ebc55 | 5037 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
5038 | [(set (match_operand:BI 0 "register_operand" "=c") |
5039 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
5040 | [(match_operand:SI 2 "gr_register_operand" "r") |
5041 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 5042 | "" |
18a3c539 | 5043 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 5044 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
5045 | |
5046 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
5047 | [(set (match_operand:BI 0 "register_operand" "=c") |
5048 | (match_operator:BI 1 "normal_comparison_operator" | |
5049 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 5050 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 5051 | "" |
f2f90c63 | 5052 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 5053 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 5054 | |
18a3c539 JW |
5055 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
5056 | ;; unsigned comparisons don't accept immediate operands of zero. | |
5057 | ||
c65ebc55 | 5058 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
5059 | [(set (match_operand:BI 0 "register_operand" "=c") |
5060 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
5061 | [(match_operand:DI 2 "gr_register_operand" "r") |
5062 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 5063 | "" |
18a3c539 | 5064 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 5065 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
5066 | |
5067 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
5068 | [(set (match_operand:BI 0 "register_operand" "=c") |
5069 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
5070 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
5071 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
5072 | "" |
5073 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 5074 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
5075 | |
5076 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
5077 | [(set (match_operand:BI 0 "register_operand" "=c") |
5078 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
5079 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
5080 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
5081 | "" |
5082 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 5083 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 5084 | |
02befdf4 | 5085 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
5086 | [(set (match_operand:BI 0 "register_operand" "=c") |
5087 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
5088 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
5089 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
5090 | "" | |
3f622353 | 5091 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 5092 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 5093 | |
c65ebc55 JW |
5094 | ;; ??? Can this pattern be generated? |
5095 | ||
5096 | (define_insn "*bit_zero" | |
f2f90c63 RH |
5097 | [(set (match_operand:BI 0 "register_operand" "=c") |
5098 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 5099 | (const_int 1) |
5d48891e | 5100 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
5101 | (const_int 0)))] |
5102 | "" | |
5103 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 5104 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
5105 | |
5106 | (define_insn "*bit_one" | |
f2f90c63 RH |
5107 | [(set (match_operand:BI 0 "register_operand" "=c") |
5108 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 5109 | (const_int 1) |
5d48891e | 5110 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
5111 | (const_int 0)))] |
5112 | "" | |
5113 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 5114 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
5115 | \f |
5116 | ;; :::::::::::::::::::: | |
5117 | ;; :: | |
5118 | ;; :: Branches | |
5119 | ;; :: | |
5120 | ;; :::::::::::::::::::: | |
5121 | ||
5122 | (define_expand "beq" | |
f2f90c63 RH |
5123 | [(set (pc) |
5124 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5125 | (label_ref (match_operand 0 "" "")) |
5126 | (pc)))] | |
5127 | "" | |
f2f90c63 | 5128 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
5129 | |
5130 | (define_expand "bne" | |
f2f90c63 RH |
5131 | [(set (pc) |
5132 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5133 | (label_ref (match_operand 0 "" "")) |
5134 | (pc)))] | |
5135 | "" | |
f2f90c63 | 5136 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
5137 | |
5138 | (define_expand "blt" | |
f2f90c63 RH |
5139 | [(set (pc) |
5140 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5141 | (label_ref (match_operand 0 "" "")) |
5142 | (pc)))] | |
5143 | "" | |
f2f90c63 | 5144 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
5145 | |
5146 | (define_expand "ble" | |
f2f90c63 RH |
5147 | [(set (pc) |
5148 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5149 | (label_ref (match_operand 0 "" "")) |
5150 | (pc)))] | |
5151 | "" | |
f2f90c63 | 5152 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
5153 | |
5154 | (define_expand "bgt" | |
f2f90c63 RH |
5155 | [(set (pc) |
5156 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5157 | (label_ref (match_operand 0 "" "")) |
5158 | (pc)))] | |
5159 | "" | |
f2f90c63 | 5160 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
5161 | |
5162 | (define_expand "bge" | |
f2f90c63 RH |
5163 | [(set (pc) |
5164 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5165 | (label_ref (match_operand 0 "" "")) |
5166 | (pc)))] | |
5167 | "" | |
f2f90c63 | 5168 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
5169 | |
5170 | (define_expand "bltu" | |
f2f90c63 RH |
5171 | [(set (pc) |
5172 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5173 | (label_ref (match_operand 0 "" "")) |
5174 | (pc)))] | |
5175 | "" | |
f2f90c63 | 5176 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
5177 | |
5178 | (define_expand "bleu" | |
f2f90c63 RH |
5179 | [(set (pc) |
5180 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5181 | (label_ref (match_operand 0 "" "")) |
5182 | (pc)))] | |
5183 | "" | |
f2f90c63 | 5184 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
5185 | |
5186 | (define_expand "bgtu" | |
f2f90c63 RH |
5187 | [(set (pc) |
5188 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5189 | (label_ref (match_operand 0 "" "")) |
5190 | (pc)))] | |
5191 | "" | |
f2f90c63 | 5192 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
5193 | |
5194 | (define_expand "bgeu" | |
f2f90c63 RH |
5195 | [(set (pc) |
5196 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5197 | (label_ref (match_operand 0 "" "")) |
5198 | (pc)))] | |
5199 | "" | |
f2f90c63 | 5200 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 5201 | |
e57b9d65 | 5202 | (define_expand "bunordered" |
f2f90c63 RH |
5203 | [(set (pc) |
5204 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5205 | (label_ref (match_operand 0 "" "")) |
5206 | (pc)))] | |
5207 | "" | |
f2f90c63 | 5208 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
5209 | |
5210 | (define_expand "bordered" | |
f2f90c63 RH |
5211 | [(set (pc) |
5212 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5213 | (label_ref (match_operand 0 "" "")) |
5214 | (pc)))] | |
5215 | "" | |
f2f90c63 | 5216 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 5217 | |
6b6c1201 | 5218 | (define_insn "*br_true" |
c65ebc55 | 5219 | [(set (pc) |
6b6c1201 | 5220 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5221 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
5222 | (const_int 0)]) |
5223 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
5224 | (pc)))] |
5225 | "" | |
85548039 | 5226 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 5227 | [(set_attr "itanium_class" "br") |
e5bde68a | 5228 | (set_attr "predicable" "no")]) |
c65ebc55 | 5229 | |
6b6c1201 | 5230 | (define_insn "*br_false" |
c65ebc55 | 5231 | [(set (pc) |
6b6c1201 | 5232 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5233 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5234 | (const_int 0)]) |
c65ebc55 | 5235 | (pc) |
6b6c1201 | 5236 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 5237 | "" |
85548039 | 5238 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 5239 | [(set_attr "itanium_class" "br") |
e5bde68a | 5240 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5241 | \f |
5242 | ;; :::::::::::::::::::: | |
5243 | ;; :: | |
5527bf14 RH |
5244 | ;; :: Counted loop operations |
5245 | ;; :: | |
5246 | ;; :::::::::::::::::::: | |
5247 | ||
5248 | (define_expand "doloop_end" | |
5249 | [(use (match_operand 0 "" "")) ; loop pseudo | |
5250 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
5251 | (use (match_operand 2 "" "")) ; max iterations | |
5252 | (use (match_operand 3 "" "")) ; loop level | |
5253 | (use (match_operand 4 "" ""))] ; label | |
5254 | "" | |
5527bf14 RH |
5255 | { |
5256 | /* Only use cloop on innermost loops. */ | |
5257 | if (INTVAL (operands[3]) > 1) | |
5258 | FAIL; | |
5259 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
5260 | operands[4])); | |
5261 | DONE; | |
1d5d7a21 | 5262 | }) |
5527bf14 RH |
5263 | |
5264 | (define_insn "doloop_end_internal" | |
5265 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
5266 | (const_int 0)) | |
5267 | (label_ref (match_operand 1 "" "")) | |
5268 | (pc))) | |
5269 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
5270 | (plus:DI (match_dup 0) (const_int -1)) |
5271 | (match_dup 0)))] | |
5527bf14 RH |
5272 | "" |
5273 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 5274 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
5275 | (set_attr "predicable" "no")]) |
5276 | \f | |
5277 | ;; :::::::::::::::::::: | |
5278 | ;; :: | |
c65ebc55 JW |
5279 | ;; :: Set flag operations |
5280 | ;; :: | |
5281 | ;; :::::::::::::::::::: | |
5282 | ||
5283 | (define_expand "seq" | |
f2f90c63 | 5284 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5285 | "" |
f2f90c63 | 5286 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
5287 | |
5288 | (define_expand "sne" | |
f2f90c63 | 5289 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5290 | "" |
f2f90c63 | 5291 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
5292 | |
5293 | (define_expand "slt" | |
f2f90c63 | 5294 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5295 | "" |
f2f90c63 | 5296 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
5297 | |
5298 | (define_expand "sle" | |
f2f90c63 | 5299 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5300 | "" |
f2f90c63 | 5301 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
5302 | |
5303 | (define_expand "sgt" | |
f2f90c63 | 5304 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5305 | "" |
f2f90c63 | 5306 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
5307 | |
5308 | (define_expand "sge" | |
f2f90c63 | 5309 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5310 | "" |
f2f90c63 | 5311 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
5312 | |
5313 | (define_expand "sltu" | |
f2f90c63 | 5314 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5315 | "" |
f2f90c63 | 5316 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
5317 | |
5318 | (define_expand "sleu" | |
f2f90c63 | 5319 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5320 | "" |
f2f90c63 | 5321 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
5322 | |
5323 | (define_expand "sgtu" | |
f2f90c63 | 5324 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5325 | "" |
f2f90c63 | 5326 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
5327 | |
5328 | (define_expand "sgeu" | |
f2f90c63 | 5329 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5330 | "" |
f2f90c63 | 5331 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 5332 | |
e57b9d65 | 5333 | (define_expand "sunordered" |
f2f90c63 | 5334 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5335 | "" |
f2f90c63 | 5336 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
5337 | |
5338 | (define_expand "sordered" | |
f2f90c63 | 5339 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5340 | "" |
f2f90c63 | 5341 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 5342 | |
c65ebc55 JW |
5343 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
5344 | ;; efficient than mov/mov/cst/cst. | |
5345 | ||
0551c32d RH |
5346 | (define_insn_and_split "*sne_internal" |
5347 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5348 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5349 | (const_int 0)))] |
5350 | "" | |
5351 | "#" | |
c65ebc55 | 5352 | "reload_completed" |
f2f90c63 RH |
5353 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5354 | (set (match_dup 0) (const_int 1))) | |
5355 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5356 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 5357 | "" |
52e12ad0 | 5358 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 5359 | |
0551c32d RH |
5360 | (define_insn_and_split "*seq_internal" |
5361 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5362 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5363 | (const_int 0)))] |
5364 | "" | |
5365 | "#" | |
c65ebc55 | 5366 | "reload_completed" |
f2f90c63 RH |
5367 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5368 | (set (match_dup 0) (const_int 0))) | |
5369 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5370 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 5371 | "" |
52e12ad0 | 5372 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
5373 | \f |
5374 | ;; :::::::::::::::::::: | |
5375 | ;; :: | |
5376 | ;; :: Conditional move instructions. | |
5377 | ;; :: | |
5378 | ;; :::::::::::::::::::: | |
5379 | ||
5380 | ;; ??? Add movXXcc patterns? | |
5381 | ||
c65ebc55 JW |
5382 | ;; |
5383 | ;; DImode if_then_else patterns. | |
5384 | ;; | |
5385 | ||
75cdbeb8 | 5386 | (define_insn "*cmovdi_internal" |
f2f90c63 | 5387 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 5388 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 5389 | (if_then_else:DI |
f2f90c63 RH |
5390 | (match_operator 4 "predicate_operator" |
5391 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 5392 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 5393 | (const_int 0)]) |
f2f90c63 | 5394 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 5395 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 5396 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 5397 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 5398 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5399 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5400 | { gcc_unreachable (); } |
75cdbeb8 RH |
5401 | [(set_attr "predicable" "no")]) |
5402 | ||
5403 | (define_split | |
f2f90c63 | 5404 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 5405 | (if_then_else |
f2f90c63 RH |
5406 | (match_operator 4 "predicate_operator" |
5407 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 5408 | (const_int 0)]) |
f2f90c63 RH |
5409 | (match_operand 2 "move_operand" "") |
5410 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
5411 | "reload_completed" |
5412 | [(const_int 0)] | |
e5bde68a | 5413 | { |
21515593 RH |
5414 | bool emitted_something = false; |
5415 | rtx dest = operands[0]; | |
5416 | rtx srct = operands[2]; | |
5417 | rtx srcf = operands[3]; | |
5418 | rtx cond = operands[4]; | |
2f937369 | 5419 | |
21515593 | 5420 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 5421 | { |
21515593 RH |
5422 | ia64_emit_cond_move (dest, srct, cond); |
5423 | emitted_something = true; | |
e5bde68a | 5424 | } |
21515593 | 5425 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 5426 | { |
21515593 RH |
5427 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
5428 | VOIDmode, operands[1], const0_rtx); | |
5429 | ia64_emit_cond_move (dest, srcf, cond); | |
5430 | emitted_something = true; | |
3b572406 | 5431 | } |
2f937369 | 5432 | if (! emitted_something) |
f9974026 | 5433 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 5434 | DONE; |
1d5d7a21 | 5435 | }) |
c65ebc55 JW |
5436 | |
5437 | ;; Absolute value pattern. | |
5438 | ||
5439 | (define_insn "*absdi2_internal" | |
0551c32d | 5440 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5441 | (if_then_else:DI |
f2f90c63 RH |
5442 | (match_operator 4 "predicate_operator" |
5443 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5444 | (const_int 0)]) |
0551c32d RH |
5445 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
5446 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5447 | "" |
e5bde68a | 5448 | "#" |
52e12ad0 | 5449 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5450 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5451 | |
5452 | (define_split | |
5453 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 5454 | (if_then_else:DI |
f2f90c63 RH |
5455 | (match_operator 4 "predicate_operator" |
5456 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5457 | (const_int 0)]) |
0551c32d RH |
5458 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5459 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5460 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5461 | [(cond_exec | |
5462 | (match_dup 4) | |
5463 | (set (match_dup 0) | |
5464 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
5465 | "") |
5466 | ||
e5bde68a RH |
5467 | (define_split |
5468 | [(set (match_operand:DI 0 "register_operand" "") | |
5469 | (if_then_else:DI | |
f2f90c63 RH |
5470 | (match_operator 4 "predicate_operator" |
5471 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5472 | (const_int 0)]) |
0551c32d RH |
5473 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5474 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5475 | "reload_completed" |
5476 | [(cond_exec | |
5477 | (match_dup 4) | |
5478 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
5479 | (cond_exec | |
5480 | (match_dup 5) | |
5481 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5482 | { |
5483 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5484 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5485 | }) |
c65ebc55 JW |
5486 | |
5487 | ;; | |
5488 | ;; SImode if_then_else patterns. | |
5489 | ;; | |
5490 | ||
75cdbeb8 | 5491 | (define_insn "*cmovsi_internal" |
f2f90c63 | 5492 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 5493 | (if_then_else:SI |
f2f90c63 RH |
5494 | (match_operator 4 "predicate_operator" |
5495 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 5496 | (const_int 0)]) |
f2f90c63 | 5497 | (match_operand:SI 2 "move_operand" |
3b572406 | 5498 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 5499 | (match_operand:SI 3 "move_operand" |
3b572406 | 5500 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 5501 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5502 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5503 | { gcc_unreachable (); } |
3b572406 | 5504 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
5505 | |
5506 | (define_insn "*abssi2_internal" | |
0551c32d | 5507 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5508 | (if_then_else:SI |
f2f90c63 RH |
5509 | (match_operator 4 "predicate_operator" |
5510 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5511 | (const_int 0)]) |
0551c32d RH |
5512 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
5513 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5514 | "" |
e5bde68a | 5515 | "#" |
52e12ad0 | 5516 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5517 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5518 | |
5519 | (define_split | |
5520 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 5521 | (if_then_else:SI |
f2f90c63 RH |
5522 | (match_operator 4 "predicate_operator" |
5523 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5524 | (const_int 0)]) |
0551c32d RH |
5525 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5526 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5527 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5528 | [(cond_exec | |
5529 | (match_dup 4) | |
5530 | (set (match_dup 0) | |
5531 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
5532 | "") |
5533 | ||
e5bde68a RH |
5534 | (define_split |
5535 | [(set (match_operand:SI 0 "register_operand" "") | |
5536 | (if_then_else:SI | |
f2f90c63 RH |
5537 | (match_operator 4 "predicate_operator" |
5538 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5539 | (const_int 0)]) |
0551c32d RH |
5540 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5541 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5542 | "reload_completed" |
5543 | [(cond_exec | |
5544 | (match_dup 4) | |
5545 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
5546 | (cond_exec | |
5547 | (match_dup 5) | |
5548 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5549 | { |
5550 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5551 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5552 | }) |
e5bde68a | 5553 | |
7dcc803e | 5554 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
5555 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5556 | (match_operator:SI 5 "condop_operator" | |
5557 | [(if_then_else:SI | |
5558 | (match_operator 6 "predicate_operator" | |
5559 | [(match_operand:BI 1 "register_operand" "c") | |
5560 | (const_int 0)]) | |
5561 | (match_operand:SI 2 "gr_register_operand" "r") | |
5562 | (match_operand:SI 3 "gr_register_operand" "r")) | |
5563 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
5564 | "" | |
5565 | "#" | |
acb0638d BS |
5566 | "reload_completed" |
5567 | [(cond_exec | |
5568 | (match_dup 6) | |
5569 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
5570 | (cond_exec | |
5571 | (match_dup 7) | |
5572 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
5573 | { |
5574 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5575 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5576 | } |
7dcc803e BS |
5577 | [(set_attr "itanium_class" "ialu") |
5578 | (set_attr "predicable" "no")]) | |
5579 | ||
acb0638d | 5580 | |
7dcc803e | 5581 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
5582 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5583 | (match_operator:SI 5 "condop_operator" | |
5584 | [(match_operand:SI 4 "gr_register_operand" "r") | |
5585 | (if_then_else:SI | |
5586 | (match_operator 6 "predicate_operator" | |
5587 | [(match_operand:BI 1 "register_operand" "c") | |
5588 | (const_int 0)]) | |
5589 | (match_operand:SI 2 "gr_register_operand" "r") | |
5590 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
5591 | "" | |
5592 | "#" | |
acb0638d BS |
5593 | "reload_completed" |
5594 | [(cond_exec | |
5595 | (match_dup 6) | |
5596 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
5597 | (cond_exec | |
5598 | (match_dup 7) | |
5599 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
5600 | { |
5601 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5602 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5603 | } |
7dcc803e BS |
5604 | [(set_attr "itanium_class" "ialu") |
5605 | (set_attr "predicable" "no")]) | |
acb0638d | 5606 | |
c65ebc55 JW |
5607 | \f |
5608 | ;; :::::::::::::::::::: | |
5609 | ;; :: | |
5610 | ;; :: Call and branch instructions | |
5611 | ;; :: | |
5612 | ;; :::::::::::::::::::: | |
5613 | ||
5614 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
5615 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
5616 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
5617 | ;; registers used as operands. | |
5618 | ||
5619 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
5620 | ;; is supplied for the sake of some RISC machines which need to put this | |
5621 | ;; information into the assembler code; they can put it in the RTL instead of | |
5622 | ;; operand 1. | |
5623 | ||
5624 | (define_expand "call" | |
5625 | [(use (match_operand:DI 0 "" "")) | |
5626 | (use (match_operand 1 "" "")) | |
5627 | (use (match_operand 2 "" "")) | |
5628 | (use (match_operand 3 "" ""))] | |
5629 | "" | |
c65ebc55 | 5630 | { |
599aedd9 | 5631 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 5632 | DONE; |
1d5d7a21 | 5633 | }) |
c65ebc55 | 5634 | |
2ed4af6f RH |
5635 | (define_expand "sibcall" |
5636 | [(use (match_operand:DI 0 "" "")) | |
5637 | (use (match_operand 1 "" "")) | |
5638 | (use (match_operand 2 "" "")) | |
5639 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 5640 | "" |
c65ebc55 | 5641 | { |
599aedd9 | 5642 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 5643 | DONE; |
1d5d7a21 | 5644 | }) |
c65ebc55 | 5645 | |
c65ebc55 | 5646 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
5647 | ;; register in which the value is returned. There are three more operands, |
5648 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 5649 | ;; increased by one). |
2ed4af6f | 5650 | ;; |
c65ebc55 JW |
5651 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
5652 | ||
5653 | (define_expand "call_value" | |
5654 | [(use (match_operand 0 "" "")) | |
5655 | (use (match_operand:DI 1 "" "")) | |
5656 | (use (match_operand 2 "" "")) | |
5657 | (use (match_operand 3 "" "")) | |
5658 | (use (match_operand 4 "" ""))] | |
5659 | "" | |
c65ebc55 | 5660 | { |
599aedd9 | 5661 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 5662 | DONE; |
1d5d7a21 | 5663 | }) |
c65ebc55 | 5664 | |
2ed4af6f RH |
5665 | (define_expand "sibcall_value" |
5666 | [(use (match_operand 0 "" "")) | |
5667 | (use (match_operand:DI 1 "" "")) | |
5668 | (use (match_operand 2 "" "")) | |
5669 | (use (match_operand 3 "" "")) | |
5670 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 5671 | "" |
c65ebc55 | 5672 | { |
599aedd9 | 5673 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 5674 | DONE; |
1d5d7a21 | 5675 | }) |
c65ebc55 | 5676 | |
c65ebc55 JW |
5677 | ;; Call subroutine returning any type. |
5678 | ||
5679 | (define_expand "untyped_call" | |
5680 | [(parallel [(call (match_operand 0 "" "") | |
5681 | (const_int 0)) | |
5682 | (match_operand 1 "" "") | |
5683 | (match_operand 2 "" "")])] | |
5684 | "" | |
c65ebc55 JW |
5685 | { |
5686 | int i; | |
5687 | ||
5688 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
5689 | ||
5690 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
5691 | { | |
5692 | rtx set = XVECEXP (operands[2], 0, i); | |
5693 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
5694 | } | |
5695 | ||
5696 | /* The optimizer does not know that the call sets the function value | |
5697 | registers we stored in the result block. We avoid problems by | |
5698 | claiming that all hard registers are used and clobbered at this | |
5699 | point. */ | |
5700 | emit_insn (gen_blockage ()); | |
5701 | ||
5702 | DONE; | |
1d5d7a21 | 5703 | }) |
c65ebc55 | 5704 | |
599aedd9 RH |
5705 | (define_insn "call_nogp" |
5706 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5707 | (const_int 0)) | |
5708 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 5709 | "" |
599aedd9 | 5710 | "br.call%+.many %1 = %0" |
52e12ad0 | 5711 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5712 | |
599aedd9 | 5713 | (define_insn "call_value_nogp" |
75293ad6 | 5714 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5715 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i")) |
5716 | (const_int 0))) | |
5717 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 5718 | "" |
599aedd9 | 5719 | "br.call%+.many %2 = %1" |
52e12ad0 | 5720 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5721 | |
599aedd9 RH |
5722 | (define_insn "sibcall_nogp" |
5723 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5724 | (const_int 0))] | |
2ed4af6f RH |
5725 | "" |
5726 | "br%+.many %0" | |
52e12ad0 | 5727 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5728 | |
599aedd9 | 5729 | (define_insn "call_gp" |
c8083186 | 5730 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) |
599aedd9 RH |
5731 | (const_int 1)) |
5732 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
5733 | (clobber (match_scratch:DI 2 "=&r,X")) | |
5734 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 5735 | "" |
599aedd9 | 5736 | "#" |
52e12ad0 | 5737 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5738 | |
599aedd9 RH |
5739 | ;; Irritatingly, we don't have access to INSN within the split body. |
5740 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
5741 | (define_split | |
5742 | [(call (mem (match_operand 0 "call_operand" "")) | |
5743 | (const_int 1)) | |
5744 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5745 | (clobber (match_scratch:DI 2 "")) | |
5746 | (clobber (match_scratch:DI 3 ""))] | |
5747 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5748 | [(const_int 0)] | |
5749 | { | |
5750 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5751 | operands[3], true, false); | |
5752 | DONE; | |
5753 | }) | |
5754 | ||
5755 | (define_split | |
5756 | [(call (mem (match_operand 0 "call_operand" "")) | |
5757 | (const_int 1)) | |
5758 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5759 | (clobber (match_scratch:DI 2 "")) | |
5760 | (clobber (match_scratch:DI 3 ""))] | |
5761 | "reload_completed" | |
5762 | [(const_int 0)] | |
5763 | { | |
5764 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5765 | operands[3], false, false); | |
5766 | DONE; | |
5767 | }) | |
5768 | ||
5769 | (define_insn "call_value_gp" | |
75293ad6 | 5770 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5771 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i")) |
5772 | (const_int 1))) | |
5773 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
5774 | (clobber (match_scratch:DI 3 "=&r,X")) | |
5775 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 5776 | "" |
599aedd9 | 5777 | "#" |
52e12ad0 | 5778 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5779 | |
599aedd9 RH |
5780 | (define_split |
5781 | [(set (match_operand 0 "" "") | |
5782 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5783 | (const_int 1))) | |
5784 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5785 | (clobber (match_scratch:DI 3 "")) | |
5786 | (clobber (match_scratch:DI 4 ""))] | |
5787 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5788 | [(const_int 0)] | |
5789 | { | |
5790 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5791 | operands[4], true, false); | |
5792 | DONE; | |
5793 | }) | |
5794 | ||
5795 | (define_split | |
5796 | [(set (match_operand 0 "" "") | |
5797 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5798 | (const_int 1))) | |
5799 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5800 | (clobber (match_scratch:DI 3 "")) | |
5801 | (clobber (match_scratch:DI 4 ""))] | |
5802 | "reload_completed" | |
5803 | [(const_int 0)] | |
5804 | { | |
5805 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5806 | operands[4], false, false); | |
5807 | DONE; | |
5808 | }) | |
5809 | ||
5810 | (define_insn_and_split "sibcall_gp" | |
5811 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) | |
5812 | (const_int 1)) | |
5813 | (clobber (match_scratch:DI 1 "=&r,X")) | |
5814 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 5815 | "" |
599aedd9 RH |
5816 | "#" |
5817 | "reload_completed" | |
5818 | [(const_int 0)] | |
5819 | { | |
5820 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
5821 | operands[2], true, true); | |
5822 | DONE; | |
5823 | } | |
52e12ad0 | 5824 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 5825 | |
c65ebc55 JW |
5826 | (define_insn "return_internal" |
5827 | [(return) | |
5828 | (use (match_operand:DI 0 "register_operand" "b"))] | |
5829 | "" | |
5830 | "br.ret.sptk.many %0" | |
52e12ad0 | 5831 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5832 | |
5833 | (define_insn "return" | |
5834 | [(return)] | |
5835 | "ia64_direct_return ()" | |
5836 | "br.ret.sptk.many rp" | |
52e12ad0 | 5837 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 5838 | |
6b6c1201 | 5839 | (define_insn "*return_true" |
c65ebc55 | 5840 | [(set (pc) |
6b6c1201 | 5841 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5842 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5843 | (const_int 0)]) |
c65ebc55 JW |
5844 | (return) |
5845 | (pc)))] | |
5846 | "ia64_direct_return ()" | |
13da91fd | 5847 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 5848 | [(set_attr "itanium_class" "br") |
e5bde68a | 5849 | (set_attr "predicable" "no")]) |
c65ebc55 | 5850 | |
6b6c1201 | 5851 | (define_insn "*return_false" |
c65ebc55 | 5852 | [(set (pc) |
6b6c1201 | 5853 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5854 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5855 | (const_int 0)]) |
c65ebc55 JW |
5856 | (pc) |
5857 | (return)))] | |
5858 | "ia64_direct_return ()" | |
13da91fd | 5859 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 5860 | [(set_attr "itanium_class" "br") |
e5bde68a | 5861 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5862 | |
5863 | (define_insn "jump" | |
5864 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
5865 | "" | |
5866 | "br %l0" | |
52e12ad0 | 5867 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5868 | |
5869 | (define_insn "indirect_jump" | |
5870 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
5871 | "" | |
5872 | "br %0" | |
52e12ad0 | 5873 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5874 | |
5875 | (define_expand "tablejump" | |
340f7e7c RH |
5876 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
5877 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 5878 | "" |
c65ebc55 | 5879 | { |
340f7e7c RH |
5880 | rtx op0 = operands[0]; |
5881 | rtx addr; | |
5882 | ||
5883 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
5884 | element into a register without bothering to see whether that | |
5885 | is necessary given the operand predicate. Check for MEM just | |
5886 | in case someone fixes this. */ | |
5887 | if (GET_CODE (op0) == MEM) | |
5888 | addr = XEXP (op0, 0); | |
5889 | else | |
5890 | { | |
5891 | /* Otherwise, cheat and guess that the previous insn in the | |
5892 | stream was the memory load. Grab the address from that. | |
5893 | Note we have to momentarily pop out of the sequence started | |
5894 | by the insn-emit wrapper in order to grab the last insn. */ | |
5895 | rtx last, set; | |
5896 | ||
5897 | end_sequence (); | |
5898 | last = get_last_insn (); | |
5899 | start_sequence (); | |
5900 | set = single_set (last); | |
5901 | ||
e820471b NS |
5902 | gcc_assert (rtx_equal_p (SET_DEST (set), op0) |
5903 | && GET_CODE (SET_SRC (set)) == MEM); | |
340f7e7c | 5904 | addr = XEXP (SET_SRC (set), 0); |
e820471b | 5905 | gcc_assert (!rtx_equal_p (addr, op0)); |
340f7e7c | 5906 | } |
c65ebc55 | 5907 | |
340f7e7c RH |
5908 | /* Jump table elements are stored pc-relative. That is, a displacement |
5909 | from the entry to the label. Thus to convert to an absolute address | |
5910 | we add the address of the memory from which the value is loaded. */ | |
5911 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
5912 | NULL_RTX, 1, OPTAB_DIRECT); | |
5913 | }) | |
c65ebc55 | 5914 | |
340f7e7c | 5915 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
5916 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
5917 | (use (label_ref (match_operand 1 "" "")))] | |
5918 | "" | |
5919 | "br %0" | |
52e12ad0 | 5920 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5921 | |
5922 | \f | |
5923 | ;; :::::::::::::::::::: | |
5924 | ;; :: | |
5925 | ;; :: Prologue and Epilogue instructions | |
5926 | ;; :: | |
5927 | ;; :::::::::::::::::::: | |
5928 | ||
5929 | (define_expand "prologue" | |
5930 | [(const_int 1)] | |
5931 | "" | |
c65ebc55 JW |
5932 | { |
5933 | ia64_expand_prologue (); | |
5934 | DONE; | |
1d5d7a21 | 5935 | }) |
c65ebc55 JW |
5936 | |
5937 | (define_expand "epilogue" | |
2ed4af6f RH |
5938 | [(return)] |
5939 | "" | |
2ed4af6f RH |
5940 | { |
5941 | ia64_expand_epilogue (0); | |
5942 | DONE; | |
1d5d7a21 | 5943 | }) |
2ed4af6f RH |
5944 | |
5945 | (define_expand "sibcall_epilogue" | |
5946 | [(return)] | |
c65ebc55 | 5947 | "" |
c65ebc55 | 5948 | { |
2ed4af6f | 5949 | ia64_expand_epilogue (1); |
c65ebc55 | 5950 | DONE; |
1d5d7a21 | 5951 | }) |
c65ebc55 JW |
5952 | |
5953 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
5954 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
5955 | ||
5956 | (define_insn "prologue_allocate_stack" | |
5957 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
5958 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 5959 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 5960 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
5961 | (match_dup 3))] |
5962 | "" | |
5963 | "@ | |
1d5d7a21 RH |
5964 | add %0 = %1, %2 |
5965 | adds %0 = %2, %1 | |
5966 | addl %0 = %2, %1" | |
52e12ad0 | 5967 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
5968 | |
5969 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
5970 | ;; stack accesses. This is similar to movdi plus the extra set. | |
5971 | ||
5972 | (define_insn "epilogue_deallocate_stack" | |
5973 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5974 | (match_operand:DI 1 "register_operand" "+r")) | |
5975 | (set (match_dup 1) (match_dup 1))] | |
5976 | "" | |
5977 | "mov %0 = %1" | |
52e12ad0 | 5978 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 5979 | |
1d5d7a21 RH |
5980 | ;; As USE insns aren't meaningful after reload, this is used instead |
5981 | ;; to prevent deleting instructions setting registers for EH handling | |
5982 | (define_insn "prologue_use" | |
5983 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
5984 | UNSPEC_PROLOGUE_USE)] | |
5985 | "" | |
5986 | "" | |
5987 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
5988 | (set_attr "predicable" "no") |
5989 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 5990 | |
c65ebc55 JW |
5991 | ;; Allocate a new register frame. |
5992 | ||
5993 | (define_insn "alloc" | |
5994 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5995 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
5996 | (use (match_operand:DI 1 "const_int_operand" "i")) |
5997 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
5998 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
5999 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
6000 | "" | |
6001 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 6002 | [(set_attr "itanium_class" "syst_m0") |
68e11b42 JW |
6003 | (set_attr "predicable" "no") |
6004 | (set_attr "first_insn" "yes")]) | |
c65ebc55 | 6005 | |
97e242b0 RH |
6006 | ;; Modifies ar.unat |
6007 | (define_expand "gr_spill" | |
870f9ec0 RH |
6008 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
6009 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
6010 | (match_operand:DI 2 "const_int_operand" "")] |
6011 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 6012 | (clobber (match_dup 3))])] |
97e242b0 | 6013 | "" |
870f9ec0 | 6014 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 6015 | |
870f9ec0 | 6016 | (define_insn "gr_spill_internal" |
b6fb7d46 | 6017 | [(set (match_operand:DI 0 "destination_operand" "=m") |
870f9ec0 | 6018 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
6019 | (match_operand:DI 2 "const_int_operand" "")] |
6020 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 6021 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 6022 | "" |
2130b7fb | 6023 | { |
1d5d7a21 RH |
6024 | /* Note that we use a C output pattern here to avoid the predicate |
6025 | being automatically added before the .mem.offset directive. */ | |
6026 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
6027 | } | |
52e12ad0 | 6028 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 6029 | |
97e242b0 RH |
6030 | ;; Reads ar.unat |
6031 | (define_expand "gr_restore" | |
870f9ec0 RH |
6032 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
6033 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
6034 | (match_operand:DI 2 "const_int_operand" "")] |
6035 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 6036 | (use (match_dup 3))])] |
97e242b0 | 6037 | "" |
870f9ec0 | 6038 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 6039 | |
870f9ec0 | 6040 | (define_insn "gr_restore_internal" |
c65ebc55 | 6041 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 6042 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
6043 | (match_operand:DI 2 "const_int_operand" "")] |
6044 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 6045 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 6046 | "" |
1d5d7a21 | 6047 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 6048 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
6049 | |
6050 | (define_insn "fr_spill" | |
b6fb7d46 | 6051 | [(set (match_operand:XF 0 "destination_operand" "=m") |
02befdf4 | 6052 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] |
086c0f96 | 6053 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
6054 | "" |
6055 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 6056 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
6057 | |
6058 | (define_insn "fr_restore" | |
02befdf4 ZW |
6059 | [(set (match_operand:XF 0 "register_operand" "=f") |
6060 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 6061 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
6062 | "" |
6063 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 6064 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 6065 | |
0024a804 JW |
6066 | ;; ??? The explicit stop is not ideal. It would be better if |
6067 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
6068 | ;; fixed later. This avoids an RSE DV. | |
6069 | ||
0c96007e AM |
6070 | (define_insn "bsp_value" |
6071 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 6072 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 6073 | "" |
582d11e6 JW |
6074 | "* |
6075 | { | |
6076 | return \";;\;%,mov %0 = ar.bsp\"; | |
6077 | }" | |
52e12ad0 | 6078 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
6079 | |
6080 | (define_insn "set_bsp" | |
086c0f96 RH |
6081 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
6082 | UNSPECV_SET_BSP)] | |
0c96007e | 6083 | "" |
1d5d7a21 RH |
6084 | "flushrs |
6085 | mov r19=ar.rsc | |
6086 | ;; | |
6087 | and r19=0x1c,r19 | |
6088 | ;; | |
6089 | mov ar.rsc=r19 | |
6090 | ;; | |
6091 | mov ar.bspstore=%0 | |
6092 | ;; | |
6093 | or r19=0x3,r19 | |
6094 | ;; | |
6095 | loadrs | |
6096 | invala | |
6097 | ;; | |
6098 | mov ar.rsc=r19" | |
52e12ad0 | 6099 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 6100 | (set_attr "predicable" "no")]) |
ce152ef8 | 6101 | |
0024a804 JW |
6102 | ;; ??? The explicit stops are not ideal. It would be better if |
6103 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
6104 | ;; fixed later. This avoids an RSE DV. | |
6105 | ||
ce152ef8 | 6106 | (define_insn "flushrs" |
086c0f96 | 6107 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 6108 | "" |
0024a804 | 6109 | ";;\;flushrs\;;;" |
582d11e6 JW |
6110 | [(set_attr "itanium_class" "rse_m") |
6111 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
6112 | \f |
6113 | ;; :::::::::::::::::::: | |
6114 | ;; :: | |
6115 | ;; :: Miscellaneous instructions | |
6116 | ;; :: | |
6117 | ;; :::::::::::::::::::: | |
6118 | ||
839a4992 | 6119 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
6120 | ;; be emitting ";;" to force a break in the instruction packing. |
6121 | ||
6122 | ;; No operation, needed in case the user uses -g but not -O. | |
6123 | (define_insn "nop" | |
6124 | [(const_int 0)] | |
6125 | "" | |
6126 | "nop 0" | |
30028c85 | 6127 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 6128 | |
2130b7fb BS |
6129 | (define_insn "nop_m" |
6130 | [(const_int 1)] | |
6131 | "" | |
6132 | "nop.m 0" | |
6133 | [(set_attr "itanium_class" "nop_m")]) | |
6134 | ||
6135 | (define_insn "nop_i" | |
6136 | [(const_int 2)] | |
6137 | "" | |
6138 | "nop.i 0" | |
6139 | [(set_attr "itanium_class" "nop_i")]) | |
6140 | ||
6141 | (define_insn "nop_f" | |
6142 | [(const_int 3)] | |
6143 | "" | |
6144 | "nop.f 0" | |
6145 | [(set_attr "itanium_class" "nop_f")]) | |
6146 | ||
6147 | (define_insn "nop_b" | |
6148 | [(const_int 4)] | |
6149 | "" | |
6150 | "nop.b 0" | |
6151 | [(set_attr "itanium_class" "nop_b")]) | |
6152 | ||
6153 | (define_insn "nop_x" | |
6154 | [(const_int 5)] | |
6155 | "" | |
6156 | "" | |
fa978426 AS |
6157 | [(set_attr "itanium_class" "nop_x") |
6158 | (set_attr "empty" "yes")]) | |
2130b7fb | 6159 | |
30028c85 VM |
6160 | ;; The following insn will be never generated. It is used only by |
6161 | ;; insn scheduler to change state before advancing cycle. | |
6162 | (define_insn "pre_cycle" | |
6163 | [(const_int 6)] | |
6164 | "" | |
6165 | "" | |
6166 | [(set_attr "itanium_class" "pre_cycle")]) | |
6167 | ||
2130b7fb | 6168 | (define_insn "bundle_selector" |
086c0f96 | 6169 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 6170 | "" |
1d5d7a21 | 6171 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
6172 | [(set_attr "itanium_class" "ignore") |
6173 | (set_attr "predicable" "no")]) | |
6174 | ||
c65ebc55 JW |
6175 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
6176 | ;; point. | |
6177 | (define_insn "blockage" | |
086c0f96 | 6178 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
6179 | "" |
6180 | "" | |
52e12ad0 | 6181 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 6182 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
6183 | |
6184 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
6185 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
6186 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
6187 | "" |
6188 | ";;" | |
52e12ad0 | 6189 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
6190 | (set_attr "predicable" "no") |
6191 | (set_attr "empty" "yes")]) | |
c65ebc55 | 6192 | |
26406018 RH |
6193 | (define_expand "trap" |
6194 | [(trap_if (const_int 1) (const_int 0))] | |
6195 | "" | |
6196 | "") | |
6197 | ||
6198 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
6199 | ;; produces worse code that setting the slot type to A. | |
6200 | ||
6201 | (define_insn "*trap" | |
6202 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
6203 | "" | |
6204 | "break %0" | |
048d0d36 | 6205 | [(set_attr "itanium_class" "chk_s_i")]) |
26406018 RH |
6206 | |
6207 | (define_expand "conditional_trap" | |
6208 | [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] | |
6209 | "" | |
6210 | { | |
6211 | operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode); | |
6212 | }) | |
6213 | ||
6214 | (define_insn "*conditional_trap" | |
6215 | [(trap_if (match_operator 0 "predicate_operator" | |
6216 | [(match_operand:BI 1 "register_operand" "c") | |
6217 | (const_int 0)]) | |
6218 | (match_operand 2 "const_int_operand" ""))] | |
6219 | "" | |
5cf63e3f | 6220 | "(%J0) break %2" |
048d0d36 | 6221 | [(set_attr "itanium_class" "chk_s_i") |
26406018 RH |
6222 | (set_attr "predicable" "no")]) |
6223 | ||
f12f25a7 | 6224 | (define_insn "break_f" |
086c0f96 | 6225 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
6226 | "" |
6227 | "break.f 0" | |
6228 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
6229 | |
6230 | (define_insn "prefetch" | |
6231 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
6232 | (match_operand:DI 1 "const_int_operand" "n") | |
6233 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6234 | "" | |
6235 | { | |
6236 | static const char * const alt[2][4] = { | |
b3656137 | 6237 | { |
92cbea22 L |
6238 | "%,lfetch.nta [%0]", |
6239 | "%,lfetch.nt1 [%0]", | |
6240 | "%,lfetch.nt2 [%0]", | |
6241 | "%,lfetch [%0]" | |
b3656137 KG |
6242 | }, |
6243 | { | |
92cbea22 L |
6244 | "%,lfetch.excl.nta [%0]", |
6245 | "%,lfetch.excl.nt1 [%0]", | |
6246 | "%,lfetch.excl.nt2 [%0]", | |
6247 | "%,lfetch.excl [%0]" | |
b3656137 | 6248 | } |
44eca121 JJ |
6249 | }; |
6250 | int i = (INTVAL (operands[1])); | |
6251 | int j = (INTVAL (operands[2])); | |
6252 | ||
e820471b NS |
6253 | gcc_assert (i == 0 || i == 1); |
6254 | gcc_assert (j >= 0 && j <= 3); | |
44eca121 JJ |
6255 | return alt[i][j]; |
6256 | } | |
6257 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
6258 | \f |
6259 | ;; Non-local goto support. | |
6260 | ||
6261 | (define_expand "save_stack_nonlocal" | |
6262 | [(use (match_operand:OI 0 "memory_operand" "")) | |
6263 | (use (match_operand:DI 1 "register_operand" ""))] | |
6264 | "" | |
c65ebc55 JW |
6265 | { |
6266 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
6267 | \"__ia64_save_stack_nonlocal\"), | |
6268 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
6269 | operands[1], Pmode); | |
6270 | DONE; | |
1d5d7a21 | 6271 | }) |
c65ebc55 JW |
6272 | |
6273 | (define_expand "nonlocal_goto" | |
6274 | [(use (match_operand 0 "general_operand" "")) | |
6275 | (use (match_operand 1 "general_operand" "")) | |
6276 | (use (match_operand 2 "general_operand" "")) | |
6277 | (use (match_operand 3 "general_operand" ""))] | |
6278 | "" | |
c65ebc55 | 6279 | { |
c65ebc55 | 6280 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 6281 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 6282 | operands[1], Pmode, |
c65ebc55 | 6283 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 6284 | operands[3], Pmode); |
c65ebc55 JW |
6285 | emit_barrier (); |
6286 | DONE; | |
1d5d7a21 | 6287 | }) |
c65ebc55 | 6288 | |
b39eb2f9 RH |
6289 | (define_insn_and_split "builtin_setjmp_receiver" |
6290 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 6291 | "" |
b39eb2f9 RH |
6292 | "#" |
6293 | "reload_completed" | |
6294 | [(const_int 0)] | |
97e242b0 | 6295 | { |
599aedd9 | 6296 | ia64_reload_gp (); |
c65ebc55 | 6297 | DONE; |
1d5d7a21 | 6298 | }) |
c65ebc55 | 6299 | |
0c96007e AM |
6300 | (define_expand "eh_epilogue" |
6301 | [(use (match_operand:DI 0 "register_operand" "r")) | |
6302 | (use (match_operand:DI 1 "register_operand" "r")) | |
6303 | (use (match_operand:DI 2 "register_operand" "r"))] | |
6304 | "" | |
0c96007e AM |
6305 | { |
6306 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
6307 | rtx sp = gen_rtx_REG (Pmode, 9); | |
6308 | ||
6309 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
6310 | { | |
6311 | emit_move_insn (bsp, operands[0]); | |
6312 | operands[0] = bsp; | |
6313 | } | |
6314 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
6315 | { | |
6316 | emit_move_insn (sp, operands[2]); | |
6317 | operands[2] = sp; | |
6318 | } | |
6319 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
6320 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
6321 | ||
6322 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
6323 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 6324 | }) |
9525c690 JW |
6325 | \f |
6326 | ;; Builtin apply support. | |
6327 | ||
6328 | (define_expand "restore_stack_nonlocal" | |
6329 | [(use (match_operand:DI 0 "register_operand" "")) | |
6330 | (use (match_operand:OI 1 "memory_operand" ""))] | |
6331 | "" | |
9525c690 JW |
6332 | { |
6333 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 6334 | "__ia64_restore_stack_nonlocal"), |
9525c690 JW |
6335 | 0, VOIDmode, 1, |
6336 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
6337 | DONE; | |
1d5d7a21 | 6338 | }) |
9525c690 | 6339 | |
e5bde68a RH |
6340 | \f |
6341 | ;; Predication. | |
6342 | ||
6343 | (define_cond_exec | |
6344 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 6345 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
6346 | (const_int 0)])] |
6347 | "" | |
6348 | "(%J0)") | |
3b572406 RH |
6349 | |
6350 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 6351 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 6352 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 6353 | "" |
054451ea | 6354 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 6355 | [(set_attr "itanium_class" "ignore") |
3b572406 | 6356 | (set_attr "predicable" "no")]) |
ca3920ad JW |
6357 | |
6358 | (define_insn "safe_across_calls_all" | |
086c0f96 | 6359 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
6360 | "" |
6361 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 6362 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6363 | (set_attr "predicable" "no")]) |
6364 | ||
6365 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 6366 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 6367 | "" |
ca3920ad | 6368 | { |
1bc7c5b6 | 6369 | emit_safe_across_calls (); |
1d5d7a21 RH |
6370 | return ""; |
6371 | } | |
52e12ad0 | 6372 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6373 | (set_attr "predicable" "no")]) |
6374 | ||
27a9b99d | 6375 | ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit |
6dd12198 SE |
6376 | ;; pointer. This is used by the HP-UX 32 bit mode. |
6377 | ||
6378 | (define_insn "ptr_extend" | |
6379 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
6380 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
6381 | UNSPEC_ADDP4))] | |
6dd12198 SE |
6382 | "" |
6383 | "addp4 %0 = 0,%1" | |
6384 | [(set_attr "itanium_class" "ialu")]) | |
6385 | ||
e206a74f SE |
6386 | ;; |
6387 | ;; Optimizations for ptr_extend | |
6388 | ||
36c216e5 | 6389 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
6390 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6391 | (unspec:DI | |
6392 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
6393 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 6394 | UNSPEC_ADDP4))] |
08744705 | 6395 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6396 | "addp4 %0 = %2, %1" |
6397 | [(set_attr "itanium_class" "ialu")]) | |
6398 | ||
6399 | (define_insn "*ptr_extend_plus_2" | |
6400 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
6401 | (unspec:DI | |
6402 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
6403 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 6404 | UNSPEC_ADDP4))] |
08744705 | 6405 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6406 | "addp4 %0 = %1, %2" |
6407 | [(set_attr "itanium_class" "ialu")]) | |
f61134e8 | 6408 | |
d26afa4f SE |
6409 | ;; |
6410 | ;; Get instruction pointer | |
6411 | ||
6412 | (define_insn "ip_value" | |
6413 | [(set (match_operand:DI 0 "register_operand" "=r") | |
6414 | (pc))] | |
6415 | "" | |
6416 | "mov %0 = ip" | |
6107a6ae | 6417 | [(set_attr "itanium_class" "frbr")]) |
d26afa4f | 6418 | |
f61134e8 RH |
6419 | ;; Vector operations |
6420 | (include "vect.md") | |
af795c3c RH |
6421 | ;; Atomic operations |
6422 | (include "sync.md") | |
4883241c SE |
6423 | ;; New division operations |
6424 | (include "div.md") |