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ba8ab355 | 1 | /* Definitions of target machine for GNU compiler, for Intel 80960 |
16c484c7 | 2 | Copyright (C) 1992, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2002 |
c2749e2d | 3 | Free Software Foundation, Inc. |
ba8ab355 JW |
4 | Contributed by Steven McGeady, Intel Corp. |
5 | Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson | |
6 | Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. | |
7 | ||
8 | This file is part of GNU CC. | |
9 | ||
10 | GNU CC is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GNU CC is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GNU CC; see the file COPYING. If not, write to | |
5b1a918b RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
ba8ab355 JW |
24 | |
25 | /* Note that some other tm.h files may include this one and then override | |
26 | many of the definitions that relate to assembler syntax. */ | |
27 | ||
eaa4b44c VM |
28 | #define MULTILIB_DEFAULTS { "mnumerics" } |
29 | ||
ba8ab355 | 30 | /* Names to predefine in the preprocessor for this target machine. */ |
2b57e919 | 31 | #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu=i960 -Amachine=i960" |
ba8ab355 JW |
32 | |
33 | /* Name to predefine in the preprocessor for processor variations. */ | |
34 | #define CPP_SPEC "%{mic*:-D__i960\ | |
c3eebffb | 35 | %{mka:-D__i960KA}%{mkb:-D__i960KB}\ |
555d459c RK |
36 | %{mja:-D__i960JA}%{mjd:-D__i960JD}%{mjf:-D__i960JF}\ |
37 | %{mrp:-D__i960RP}\ | |
c3eebffb | 38 | %{msa:-D__i960SA}%{msb:-D__i960SB}\ |
ba8ab355 | 39 | %{mmc:-D__i960MC}\ |
c3eebffb | 40 | %{mca:-D__i960CA}%{mcc:-D__i960CC}\ |
ba8ab355 | 41 | %{mcf:-D__i960CF}}\ |
303e979a | 42 | %{msoft-float:-D_SOFT_FLOAT}\ |
ba8ab355 JW |
43 | %{mka:-D__i960KA__ -D__i960_KA__}\ |
44 | %{mkb:-D__i960KB__ -D__i960_KB__}\ | |
ba8ab355 JW |
45 | %{msa:-D__i960SA__ -D__i960_SA__}\ |
46 | %{msb:-D__i960SB__ -D__i960_SB__}\ | |
ba8ab355 JW |
47 | %{mmc:-D__i960MC__ -D__i960_MC__}\ |
48 | %{mca:-D__i960CA__ -D__i960_CA__}\ | |
ba8ab355 JW |
49 | %{mcc:-D__i960CC__ -D__i960_CC__}\ |
50 | %{mcf:-D__i960CF__ -D__i960_CF__}\ | |
c3eebffb | 51 | %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\ |
eaa4b44c VM |
52 | %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}\ |
53 | %{mlong-double-64:-D__LONG_DOUBLE_64__}" | |
ba8ab355 JW |
54 | |
55 | /* -mic* options make characters signed by default. */ | |
0f1d97b8 JW |
56 | /* Use #if rather than ?: because MIPS C compiler rejects ?: in |
57 | initializers. */ | |
58 | #if DEFAULT_SIGNED_CHAR | |
59 | #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}" | |
60 | #else | |
61 | #define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}" | |
62 | #endif | |
ba8ab355 | 63 | |
0e089454 JW |
64 | /* Specs for the compiler, to handle processor variations. |
65 | If the user gives an explicit -gstabs or -gcoff option, then do not | |
66 | try to add an implicit one, as this will fail. */ | |
ba8ab355 | 67 | #define CC1_SPEC \ |
555d459c | 68 | "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-mka}}}}}}}}}}}}\ |
0e089454 JW |
69 | %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\ |
70 | %{mcoff:%{g*:-gcoff}}\ | |
71 | %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}" | |
ba8ab355 JW |
72 | |
73 | /* Specs for the assembler, to handle processor variations. | |
74 | For compatibility with Intel's gnu960 tool chain, pass -A options to | |
75 | the assembler. */ | |
76 | #define ASM_SPEC \ | |
c3eebffb JW |
77 | "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\ |
78 | %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\ | |
555d459c RK |
79 | %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\ |
80 | %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-AKB}}}}}}}}}}}}\ | |
647902e0 | 81 | %{mlink-relax:-linkrelax}" |
ba8ab355 JW |
82 | |
83 | /* Specs for the linker, to handle processor variations. | |
84 | For compatibility with Intel's gnu960 tool chain, pass -F and -A options | |
85 | to the linker. */ | |
86 | #define LINK_SPEC \ | |
c3eebffb JW |
87 | "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\ |
88 | %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\ | |
e9a25f70 | 89 | %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\ |
c3eebffb JW |
90 | %{mbout:-Fbout}%{mcoff:-Fcoff}\ |
91 | %{mlink-relax:-relax}" | |
ba8ab355 JW |
92 | |
93 | /* Specs for the libraries to link with, to handle processor variations. | |
94 | Compatible with Intel's gnu960 tool chain. */ | |
95 | #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\ | |
96 | %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}" | |
97 | ||
bcf783f4 VM |
98 | /* Defining the macro shows we can debug even without a frame pointer. |
99 | Actually, we can debug without FP. But defining the macro results in | |
100 | that -O means FP elimination. Addressing through sp requires | |
101 | negative offset and more one word addressing in the most cases | |
102 | (offsets except for 0-4095 require one more word). Therefore we've | |
e5837c07 | 103 | not defined the macro. */ |
bcf783f4 | 104 | /*#define CAN_DEBUG_WITHOUT_FP*/ |
b0f43a24 RK |
105 | |
106 | /* Do leaf procedure and tail call optimizations for -O2 and higher. */ | |
c6aded7c | 107 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ |
ba8ab355 JW |
108 | { \ |
109 | if ((LEVEL) >= 2) \ | |
110 | { \ | |
ba8ab355 JW |
111 | target_flags |= TARGET_FLAG_LEAFPROC; \ |
112 | target_flags |= TARGET_FLAG_TAILCALL; \ | |
113 | } \ | |
ba8ab355 JW |
114 | } |
115 | ||
116 | /* Print subsidiary information on the compiler version in use. */ | |
117 | #define TARGET_VERSION fprintf (stderr," (intel 80960)"); | |
118 | ||
119 | /* Generate DBX debugging information. */ | |
120 | #define DBX_DEBUGGING_INFO | |
121 | ||
122 | /* Generate SDB style debugging information. */ | |
123 | #define SDB_DEBUGGING_INFO | |
6321d910 | 124 | #define EXTENDED_SDB_BASIC_TYPES |
ba8ab355 JW |
125 | |
126 | /* Generate DBX_DEBUGGING_INFO by default. */ | |
127 | #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG | |
128 | ||
6321d910 JW |
129 | /* Redefine this to print in hex. No value adjustment is necessary |
130 | anymore. */ | |
3c2eb9e1 | 131 | #define PUT_SDB_TYPE(A) \ |
6321d910 | 132 | fprintf (asm_out_file, "\t.type\t0x%x;", A) |
ba8ab355 | 133 | |
c9040e2c | 134 | /* Handle pragmas for compatibility with Intel's compilers. */ |
43fabf7d JW |
135 | |
136 | extern int i960_maxbitalignment; | |
137 | extern int i960_last_maxbitalignment; | |
138 | ||
8b97c5f8 ZW |
139 | #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ |
140 | cpp_register_pragma (PFILE, 0, "align", i960_pr_align); \ | |
141 | cpp_register_pragma (PFILE, 0, "noalign", i960_pr_noalign); \ | |
142 | } while (0) | |
c9040e2c | 143 | |
ba8ab355 JW |
144 | /* Run-time compilation parameters selecting different hardware subsets. */ |
145 | ||
146 | /* 960 architecture with floating-point. */ | |
147 | #define TARGET_FLAG_NUMERICS 0x01 | |
148 | #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS) | |
149 | ||
150 | /* 960 architecture with memory management. */ | |
151 | /* ??? Not used currently. */ | |
152 | #define TARGET_FLAG_PROTECTED 0x02 | |
153 | #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED) | |
154 | ||
155 | /* The following three are mainly used to provide a little sanity checking | |
555d459c | 156 | against the -mARCH flags given. The Jx series, for the purposes of |
e5837c07 | 157 | gcc, is a Kx with a data cache. */ |
ba8ab355 JW |
158 | |
159 | /* Nonzero if we should generate code for the KA and similar processors. | |
160 | No FPU, no microcode instructions. */ | |
161 | #define TARGET_FLAG_K_SERIES 0x04 | |
162 | #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES) | |
163 | ||
164 | /* Nonzero if we should generate code for the MC processor. | |
165 | Not really different from KB for our purposes. */ | |
166 | #define TARGET_FLAG_MC 0x08 | |
167 | #define TARGET_MC (target_flags & TARGET_FLAG_MC) | |
168 | ||
169 | /* Nonzero if we should generate code for the CA processor. | |
170 | Enables different optimization strategies. */ | |
171 | #define TARGET_FLAG_C_SERIES 0x10 | |
172 | #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES) | |
173 | ||
174 | /* Nonzero if we should generate leaf-procedures when we find them. | |
175 | You may not want to do this because leaf-proc entries are | |
176 | slower when not entered via BAL - this would be true when | |
177 | a linker not supporting the optimization is used. */ | |
178 | #define TARGET_FLAG_LEAFPROC 0x20 | |
179 | #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC) | |
180 | ||
181 | /* Nonzero if we should perform tail-call optimizations when we find them. | |
182 | You may not want to do this because the detection of cases where | |
183 | this is not valid is not totally complete. */ | |
184 | #define TARGET_FLAG_TAILCALL 0x40 | |
185 | #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL) | |
186 | ||
187 | /* Nonzero if use of a complex addressing mode is a win on this implementation. | |
188 | Complex addressing modes are probably not worthwhile on the K-series, | |
189 | but they definitely are on the C-series. */ | |
190 | #define TARGET_FLAG_COMPLEX_ADDR 0x80 | |
191 | #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR) | |
192 | ||
193 | /* Align code to 8 byte boundaries for faster fetching. */ | |
194 | #define TARGET_FLAG_CODE_ALIGN 0x100 | |
195 | #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN) | |
196 | ||
197 | /* Append branch prediction suffixes to branch opcodes. */ | |
198 | /* ??? Not used currently. */ | |
199 | #define TARGET_FLAG_BRANCH_PREDICT 0x200 | |
200 | #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT) | |
201 | ||
202 | /* Forces prototype and return promotions. */ | |
203 | /* ??? This does not work. */ | |
204 | #define TARGET_FLAG_CLEAN_LINKAGE 0x400 | |
205 | #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE) | |
206 | ||
207 | /* For compatibility with iC960 v3.0. */ | |
208 | #define TARGET_FLAG_IC_COMPAT3_0 0x800 | |
209 | #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0) | |
210 | ||
211 | /* For compatibility with iC960 v2.0. */ | |
212 | #define TARGET_FLAG_IC_COMPAT2_0 0x1000 | |
213 | #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0) | |
214 | ||
215 | /* If no unaligned accesses are to be permitted. */ | |
216 | #define TARGET_FLAG_STRICT_ALIGN 0x2000 | |
217 | #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN) | |
218 | ||
219 | /* For compatibility with iC960 assembler. */ | |
220 | #define TARGET_FLAG_ASM_COMPAT 0x4000 | |
221 | #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT) | |
222 | ||
223 | /* For compatibility with the gcc960 v1.2 compiler. Use the old structure | |
13d39dbc | 224 | alignment rules. Also, turns on STRICT_ALIGNMENT. */ |
ba8ab355 JW |
225 | #define TARGET_FLAG_OLD_ALIGN 0x8000 |
226 | #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN) | |
227 | ||
eaa4b44c VM |
228 | /* Nonzero if long doubles are to be 64 bits. Useful for soft-float targets |
229 | if 80 bit long double support is missing. */ | |
230 | #define TARGET_FLAG_LONG_DOUBLE_64 0x10000 | |
231 | #define TARGET_LONG_DOUBLE_64 (target_flags & TARGET_FLAG_LONG_DOUBLE_64) | |
232 | ||
ba8ab355 JW |
233 | extern int target_flags; |
234 | ||
235 | /* Macro to define tables used to set the flags. | |
236 | This is a list in braces of pairs in braces, | |
237 | each pair being { "NAME", VALUE } | |
238 | where VALUE is the bits to set or minus the bits to clear. | |
239 | An empty string NAME is used to identify the default VALUE. */ | |
240 | ||
241 | /* ??? Not all ten of these architecture variations actually exist, but I | |
242 | am not sure which are real and which aren't. */ | |
243 | ||
244 | #define TARGET_SWITCHES \ | |
4e8d7ddc | 245 | { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \ |
047142d3 | 246 | N_("Generate SA code")}, \ |
4e8d7ddc JW |
247 | {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ |
248 | TARGET_FLAG_COMPLEX_ADDR), \ | |
047142d3 | 249 | N_("Generate SB code")}, \ |
4e8d7ddc JW |
250 | /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \ |
251 | TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \ | |
047142d3 | 252 | N_("Generate SC code")}, */ \ |
4e8d7ddc | 253 | {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \ |
047142d3 | 254 | N_("Generate KA code")}, \ |
4e8d7ddc JW |
255 | {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ |
256 | TARGET_FLAG_COMPLEX_ADDR), \ | |
047142d3 | 257 | N_("Generate KB code")}, \ |
4e8d7ddc JW |
258 | /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \ |
259 | TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \ | |
047142d3 | 260 | N_("Generate KC code")}, */ \ |
4e8d7ddc | 261 | {"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \ |
047142d3 | 262 | N_("Generate JA code")}, \ |
4e8d7ddc | 263 | {"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \ |
047142d3 | 264 | N_("Generate JD code")}, \ |
4e8d7ddc JW |
265 | {"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ |
266 | TARGET_FLAG_COMPLEX_ADDR), \ | |
047142d3 | 267 | N_("Generate JF code")}, \ |
4e8d7ddc | 268 | {"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \ |
047142d3 | 269 | N_("generate RP code")}, \ |
4e8d7ddc JW |
270 | {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \ |
271 | TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \ | |
047142d3 | 272 | N_("Generate MC code")}, \ |
4e8d7ddc JW |
273 | {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \ |
274 | TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\ | |
047142d3 | 275 | N_("Generate CA code")}, \ |
4e8d7ddc JW |
276 | /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES| \ |
277 | TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN),\ | |
047142d3 | 278 | N_("Generate CB code")}, \ |
4e8d7ddc | 279 | {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \ |
ba8ab355 | 280 | TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ |
4e8d7ddc | 281 | TARGET_FLAG_CODE_ALIGN), \ |
047142d3 | 282 | N_("Generate CC code")}, */ \ |
4e8d7ddc JW |
283 | {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \ |
284 | TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\ | |
047142d3 | 285 | N_("Generate CF code")}, \ |
4e8d7ddc | 286 | {"numerics", (TARGET_FLAG_NUMERICS), \ |
047142d3 | 287 | N_("Use hardware floating point instructions")}, \ |
4e8d7ddc | 288 | {"soft-float", -(TARGET_FLAG_NUMERICS), \ |
047142d3 | 289 | N_("Use software floating point")}, \ |
4e8d7ddc | 290 | {"leaf-procedures", TARGET_FLAG_LEAFPROC, \ |
047142d3 | 291 | N_("Use alternate leaf function entries")}, \ |
4e8d7ddc | 292 | {"no-leaf-procedures", -(TARGET_FLAG_LEAFPROC), \ |
047142d3 | 293 | N_("Do not use alternate leaf function entries")}, \ |
4e8d7ddc | 294 | {"tail-call", TARGET_FLAG_TAILCALL, \ |
047142d3 | 295 | N_("Perform tail call optimization")}, \ |
4e8d7ddc | 296 | {"no-tail-call", -(TARGET_FLAG_TAILCALL), \ |
047142d3 | 297 | N_("Do not perform tail call optimization")}, \ |
4e8d7ddc | 298 | {"complex-addr", TARGET_FLAG_COMPLEX_ADDR, \ |
047142d3 | 299 | N_("Use complex addressing modes")}, \ |
4e8d7ddc | 300 | {"no-complex-addr", -(TARGET_FLAG_COMPLEX_ADDR), \ |
047142d3 | 301 | N_("Do not use complex addressing modes")}, \ |
4e8d7ddc | 302 | {"code-align", TARGET_FLAG_CODE_ALIGN, \ |
047142d3 | 303 | N_("Align code to 8 byte boundary")}, \ |
4e8d7ddc | 304 | {"no-code-align", -(TARGET_FLAG_CODE_ALIGN), \ |
047142d3 | 305 | N_("Do not align code to 8 byte boundary")}, \ |
4e8d7ddc | 306 | /* {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE), \ |
047142d3 | 307 | N_("Force use of prototypes")}, \ |
4e8d7ddc | 308 | {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE), \ |
047142d3 | 309 | N_("Do not force use of prototypes")}, */ \ |
4e8d7ddc | 310 | {"ic-compat", TARGET_FLAG_IC_COMPAT2_0, \ |
047142d3 | 311 | N_("Enable compatibility with iC960 v2.0")}, \ |
4e8d7ddc | 312 | {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0, \ |
047142d3 | 313 | N_("Enable compatibility with iC960 v2.0")}, \ |
4e8d7ddc | 314 | {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0, \ |
047142d3 | 315 | N_("Enable compatibility with iC960 v3.0")}, \ |
4e8d7ddc | 316 | {"asm-compat", TARGET_FLAG_ASM_COMPAT, \ |
047142d3 | 317 | N_("Enable compatibility with ic960 assembler")}, \ |
4e8d7ddc | 318 | {"intel-asm", TARGET_FLAG_ASM_COMPAT, \ |
047142d3 | 319 | N_("Enable compatibility with ic960 assembler")}, \ |
4e8d7ddc | 320 | {"strict-align", TARGET_FLAG_STRICT_ALIGN, \ |
047142d3 | 321 | N_("Do not permit unaligned accesses")}, \ |
4e8d7ddc | 322 | {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN), \ |
047142d3 | 323 | N_("Permit unaligned accesses")}, \ |
4e8d7ddc | 324 | {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \ |
047142d3 | 325 | N_("Layout types like Intel's v1.3 gcc")}, \ |
4e8d7ddc | 326 | {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \ |
047142d3 | 327 | N_("Do not layout types like Intel's v1.3 gcc")}, \ |
4e8d7ddc | 328 | {"long-double-64", TARGET_FLAG_LONG_DOUBLE_64, \ |
047142d3 | 329 | N_("Use 64 bit long doubles")}, \ |
4e8d7ddc | 330 | {"link-relax", 0, \ |
047142d3 | 331 | N_("Enable linker relaxation")}, \ |
4e8d7ddc | 332 | {"no-link-relax", 0, \ |
047142d3 | 333 | N_("Do not enable linker relaxation")}, \ |
5d84b57e | 334 | SUBTARGET_SWITCHES \ |
4e8d7ddc JW |
335 | { "", TARGET_DEFAULT, \ |
336 | NULL}} | |
ba8ab355 | 337 | |
02d7a569 JS |
338 | /* This are meant to be redefined in the host dependent files */ |
339 | #define SUBTARGET_SWITCHES | |
340 | ||
ba8ab355 JW |
341 | /* Override conflicting target switch options. |
342 | Doesn't actually detect if more than one -mARCH option is given, but | |
343 | does handle the case of two blatantly conflicting -mARCH options. */ | |
344 | #define OVERRIDE_OPTIONS \ | |
345 | { \ | |
346 | if (TARGET_K_SERIES && TARGET_C_SERIES) \ | |
347 | { \ | |
3d2cfac6 | 348 | warning ("conflicting architectures defined - using C series"); \ |
ba8ab355 JW |
349 | target_flags &= ~TARGET_FLAG_K_SERIES; \ |
350 | } \ | |
351 | if (TARGET_K_SERIES && TARGET_MC) \ | |
352 | { \ | |
3d2cfac6 | 353 | warning ("conflicting architectures defined - using K series"); \ |
ba8ab355 JW |
354 | target_flags &= ~TARGET_FLAG_MC; \ |
355 | } \ | |
356 | if (TARGET_C_SERIES && TARGET_MC) \ | |
357 | { \ | |
3d2cfac6 | 358 | warning ("conflicting architectures defined - using C series");\ |
ba8ab355 JW |
359 | target_flags &= ~TARGET_FLAG_MC; \ |
360 | } \ | |
361 | if (TARGET_IC_COMPAT3_0) \ | |
362 | { \ | |
363 | flag_short_enums = 1; \ | |
364 | flag_signed_char = 1; \ | |
365 | target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ | |
366 | if (TARGET_IC_COMPAT2_0) \ | |
367 | { \ | |
3d2cfac6 | 368 | warning ("iC2.0 and iC3.0 are incompatible - using iC3.0"); \ |
ba8ab355 JW |
369 | target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \ |
370 | } \ | |
371 | } \ | |
372 | if (TARGET_IC_COMPAT2_0) \ | |
373 | { \ | |
374 | flag_signed_char = 1; \ | |
375 | target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ | |
376 | } \ | |
d86037fa JW |
377 | /* ??? See the LONG_DOUBLE_TYPE_SIZE definition below. */ \ |
378 | if (TARGET_LONG_DOUBLE_64) \ | |
c725bd79 | 379 | warning ("the -mlong-double-64 option does not work yet");\ |
ba8ab355 JW |
380 | i960_initialize (); \ |
381 | } | |
382 | ||
383 | /* Don't enable anything by default. The user is expected to supply a -mARCH | |
555d459c | 384 | option. If none is given, then -mka is added by CC1_SPEC. */ |
ba8ab355 JW |
385 | #define TARGET_DEFAULT 0 |
386 | \f | |
387 | /* Target machine storage layout. */ | |
388 | ||
819f6d59 | 389 | /* Define for cross-compilation from a host with a different float format |
abc95ed3 | 390 | or endianness, as well as to support 80 bit long doubles on the i960. */ |
819f6d59 JW |
391 | #define REAL_ARITHMETIC |
392 | ||
ba8ab355 JW |
393 | /* Define this if most significant bit is lowest numbered |
394 | in instructions that operate on numbered bit-fields. */ | |
395 | #define BITS_BIG_ENDIAN 0 | |
396 | ||
397 | /* Define this if most significant byte of a word is the lowest numbered. | |
398 | The i960 case be either big endian or little endian. We only support | |
399 | little endian, which is the most common. */ | |
400 | #define BYTES_BIG_ENDIAN 0 | |
401 | ||
402 | /* Define this if most significant word of a multiword number is lowest | |
403 | numbered. */ | |
404 | #define WORDS_BIG_ENDIAN 0 | |
405 | ||
c3eebffb | 406 | /* Number of bits in an addressable storage unit. */ |
ba8ab355 JW |
407 | #define BITS_PER_UNIT 8 |
408 | ||
409 | /* Bitfields cannot cross word boundaries. */ | |
410 | #define BITFIELD_NBYTES_LIMITED 1 | |
411 | ||
412 | /* Width in bits of a "word", which is the contents of a machine register. | |
413 | Note that this is not necessarily the width of data type `int'; | |
414 | if using 16-bit ints on a 68000, this would still be 32. | |
415 | But on a machine with 16-bit registers, this would be 16. */ | |
416 | #define BITS_PER_WORD 32 | |
417 | ||
418 | /* Width of a word, in units (bytes). */ | |
419 | #define UNITS_PER_WORD 4 | |
420 | ||
421 | /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ | |
422 | #define POINTER_SIZE 32 | |
423 | ||
eaa4b44c | 424 | /* Width in bits of a long double. Define to 96, and let |
e5837c07 | 425 | ROUND_TYPE_ALIGN adjust the alignment for speed. */ |
eaa4b44c VM |
426 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96) |
427 | ||
d86037fa JW |
428 | /* ??? This must be a constant, because real.c and real.h test it with #if. */ |
429 | #undef LONG_DOUBLE_TYPE_SIZE | |
430 | #define LONG_DOUBLE_TYPE_SIZE 96 | |
431 | ||
eaa4b44c VM |
432 | /* Define this to set long double type size to use in libgcc2.c, which can |
433 | not depend on target_flags. */ | |
434 | #if defined(__LONG_DOUBLE_64__) | |
435 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
436 | #else | |
437 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 | |
438 | #endif | |
ba8ab355 JW |
439 | |
440 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ | |
441 | #define POINTER_BOUNDARY 32 | |
442 | ||
443 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
444 | #define PARM_BOUNDARY 32 | |
445 | ||
446 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
447 | #define STACK_BOUNDARY 128 | |
448 | ||
449 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
450 | #define FUNCTION_BOUNDARY 128 | |
451 | ||
452 | /* Alignment of field after `int : 0' in a structure. */ | |
453 | #define EMPTY_FIELD_BOUNDARY 32 | |
454 | ||
455 | /* This makes zero-length anonymous fields lay the next field | |
456 | at a word boundary. It also makes the whole struct have | |
457 | at least word alignment if there are any bitfields at all. */ | |
458 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
459 | ||
460 | /* Every structure's size must be a multiple of this. */ | |
461 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
462 | ||
463 | /* No data type wants to be aligned rounder than this. | |
464 | Extended precision floats gets 4-word alignment. */ | |
465 | #define BIGGEST_ALIGNMENT 128 | |
466 | ||
467 | /* Define this if move instructions will actually fail to work | |
468 | when given unaligned data. | |
469 | 80960 will work even with unaligned data, but it is slow. */ | |
3a011f48 | 470 | #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN |
ba8ab355 JW |
471 | |
472 | /* Specify alignment for string literals (which might be higher than the | |
13d39dbc | 473 | base type's minimal alignment requirement. This allows strings to be |
ba8ab355 JW |
474 | aligned on word boundaries, and optimizes calls to the str* and mem* |
475 | library functions. */ | |
476 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
ad237340 JW |
477 | (TREE_CODE (EXP) == STRING_CST \ |
478 | && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \ | |
ba8ab355 JW |
479 | ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \ |
480 | : (ALIGN)) | |
481 | ||
b6e78be7 TG |
482 | /* Make XFmode floating point quantities be 128 bit aligned. */ |
483 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
484 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
485 | && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \ | |
486 | && (ALIGN) < 128 ? 128 : (ALIGN)) | |
487 | ||
ba8ab355 JW |
488 | /* Macros to determine size of aggregates (structures and unions |
489 | in C). Normally, these may be defined to simply return the maximum | |
490 | alignment and simple rounded-up size, but on some machines (like | |
491 | the i960), the total size of a structure is based on a non-trivial | |
492 | rounding method. */ | |
493 | ||
494 | #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \ | |
b6e78be7 TG |
495 | ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \ |
496 | ? 128 /* Put 80 bit floating point elements on 128 bit boundaries. */ \ | |
3ddf29de JW |
497 | : ((!TARGET_OLD_ALIGN && !TYPE_PACKED (TYPE) \ |
498 | && TREE_CODE (TYPE) == RECORD_TYPE) \ | |
b6e78be7 TG |
499 | ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \ |
500 | : MAX ((COMPUTED), (SPECIFIED)))) | |
501 | ||
502 | #define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED) \ | |
503 | ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \ | |
fed3cef0 RK |
504 | ? bitsize_int (128) : round_up (COMPUTED, SPECIFIED)) |
505 | #define ROUND_TYPE_SIZE_UNIT(TYPE, COMPUTED, SPECIFIED) \ | |
506 | ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \ | |
42edbfa1 | 507 | ? size_int (16) : round_up (COMPUTED, SPECIFIED)) |
fed3cef0 | 508 | |
ba8ab355 JW |
509 | \f |
510 | /* Standard register usage. */ | |
511 | ||
512 | /* Number of actual hardware registers. | |
513 | The hardware registers are assigned numbers for the compiler | |
514 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
515 | All registers that the compiler knows about must be given numbers, | |
516 | even those that are not normally considered general registers. | |
517 | ||
518 | Registers 0-15 are the global registers (g0-g15). | |
519 | Registers 16-31 are the local registers (r0-r15). | |
520 | Register 32-35 are the fp registers (fp0-fp3). | |
521 | Register 36 is the condition code register. | |
522 | Register 37 is unused. */ | |
523 | ||
524 | #define FIRST_PSEUDO_REGISTER 38 | |
525 | ||
526 | /* 1 for registers that have pervasive standard uses and are not available | |
527 | for the register allocator. On 80960, this includes the frame pointer | |
528 | (g15), the previous FP (r0), the stack pointer (r1), the return | |
529 | instruction pointer (r2), and the argument pointer (g14). */ | |
530 | #define FIXED_REGISTERS \ | |
531 | {0, 0, 0, 0, 0, 0, 0, 0, \ | |
532 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
533 | 1, 1, 1, 0, 0, 0, 0, 0, \ | |
534 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
535 | 0, 0, 0, 0, 1, 1} | |
536 | ||
537 | /* 1 for registers not available across function calls. | |
538 | These must include the FIXED_REGISTERS and also any | |
539 | registers that can be used without being saved. | |
540 | The latter must include the registers where values are returned | |
541 | and the register where structure-value addresses are passed. | |
542 | Aside from that, you can include as many other registers as you like. */ | |
543 | ||
544 | /* On the 80960, note that: | |
545 | g0..g3 are used for return values, | |
546 | g0..g7 may always be used for parameters, | |
547 | g8..g11 may be used for parameters, but are preserved if they aren't, | |
a45f3331 | 548 | g12 is the static chain if needed, otherwise is preserved |
ba8ab355 JW |
549 | g13 is the struct return ptr if used, or temp, but may be trashed, |
550 | g14 is the leaf return ptr or the arg block ptr otherwise zero, | |
551 | must be reset to zero before returning if it was used, | |
552 | g15 is the frame pointer, | |
553 | r0 is the previous FP, | |
554 | r1 is the stack pointer, | |
555 | r2 is the return instruction pointer, | |
556 | r3-r15 are always available, | |
1e39f528 JW |
557 | r3 is clobbered by calls in functions that use the arg pointer |
558 | r4-r11 may be clobbered by the mcount call when profiling | |
559 | r4-r15 if otherwise unused may be used for preserving global registers | |
ba8ab355 JW |
560 | fp0..fp3 are never available. */ |
561 | #define CALL_USED_REGISTERS \ | |
562 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
563 | 0, 0, 0, 0, 0, 1, 1, 1, \ | |
564 | 1, 1, 1, 0, 0, 0, 0, 0, \ | |
565 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
566 | 1, 1, 1, 1, 1, 1} | |
567 | ||
568 | /* If no fp unit, make all of the fp registers fixed so that they can't | |
569 | be used. */ | |
570 | #define CONDITIONAL_REGISTER_USAGE \ | |
571 | if (! TARGET_NUMERICS) { \ | |
572 | fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\ | |
573 | } \ | |
574 | ||
575 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
576 | to hold something of mode MODE. | |
577 | This is ordinarily the length in words of a value of mode MODE | |
578 | but can be less for certain modes in special long registers. | |
579 | ||
580 | On 80960, ordinary registers hold 32 bits worth, but can be ganged | |
581 | together to hold double or extended precision floating point numbers, | |
582 | and the floating point registers hold any size floating point number */ | |
583 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
584 | ((REGNO) < 32 \ | |
585 | ? (((MODE) == VOIDmode) \ | |
586 | ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ | |
587 | : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0) | |
588 | ||
589 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
590 | On 80960, the cpu registers can hold any mode but the float registers | |
b6e78be7 | 591 | can only hold SFmode, DFmode, or XFmode. */ |
2129b081 | 592 | #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE)) |
ba8ab355 JW |
593 | |
594 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
595 | when one has mode MODE1 and one has mode MODE2. | |
596 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
597 | for any hard reg, then this must be 0 for correct output. */ | |
598 | ||
599 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
600 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
601 | ||
602 | /* Specify the registers used for certain standard purposes. | |
603 | The values of these macros are register numbers. */ | |
604 | ||
605 | /* 80960 pc isn't overloaded on a register that the compiler knows about. */ | |
606 | /* #define PC_REGNUM */ | |
607 | ||
608 | /* Register to use for pushing function arguments. */ | |
609 | #define STACK_POINTER_REGNUM 17 | |
610 | ||
611 | /* Actual top-of-stack address is same as | |
612 | the contents of the stack pointer register. */ | |
613 | #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size) | |
614 | ||
615 | /* Base register for access to local variables of the function. */ | |
616 | #define FRAME_POINTER_REGNUM 15 | |
617 | ||
618 | /* Value should be nonzero if functions must have frame pointers. | |
619 | Zero means the frame pointer need not be set up (and parms | |
620 | may be accessed via the stack pointer) in functions that seem suitable. | |
621 | This is computed in `reload', in reload1.c. */ | |
43a92256 JW |
622 | /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since |
623 | fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have | |
624 | caused this to fail. */ | |
4f0a3098 DD |
625 | /* ??? Must check current_function_has_nonlocal_goto, otherwise frame pointer |
626 | elimination messes up nonlocal goto sequences. I think this works for other | |
627 | targets because they use indirect jumps for the return which disables fp | |
628 | elimination. */ | |
629 | #define FRAME_POINTER_REQUIRED \ | |
630 | (! leaf_function_p () || current_function_has_nonlocal_goto) | |
ba8ab355 | 631 | |
bcf783f4 VM |
632 | /* Definitions for register eliminations. |
633 | ||
634 | This is an array of structures. Each structure initializes one pair | |
635 | of eliminable registers. The "from" register number is given first, | |
636 | followed by "to". Eliminations of the same "from" register are listed | |
e5837c07 | 637 | in order of preference.. */ |
bcf783f4 VM |
638 | |
639 | #define ELIMINABLE_REGS {{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} | |
640 | ||
641 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
642 | Frame pointer elimination is automatically handled. */ | |
643 | #define CAN_ELIMINATE(FROM, TO) 1 | |
644 | ||
645 | /* Define the offset between two registers, one to be eliminated, and | |
646 | the other its replacement, at the start of a routine. | |
43a92256 JW |
647 | |
648 | Since the stack grows upward on the i960, this must be a negative number. | |
649 | This includes the 64 byte hardware register save area and the size of | |
650 | the frame. */ | |
ba8ab355 | 651 | |
bcf783f4 VM |
652 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
653 | do { (OFFSET) = - (64 + compute_frame_size (get_frame_size ())); } while (0) | |
ba8ab355 JW |
654 | |
655 | /* Base register for access to arguments of the function. */ | |
656 | #define ARG_POINTER_REGNUM 14 | |
657 | ||
658 | /* Register in which static-chain is passed to a function. | |
a45f3331 JW |
659 | On i960, we use g12. We can't use any local register, because we need |
660 | a register that can be set before a call or before a jump. */ | |
661 | #define STATIC_CHAIN_REGNUM 12 | |
ba8ab355 JW |
662 | |
663 | /* Functions which return large structures get the address | |
664 | to place the wanted value at in g13. */ | |
665 | ||
666 | #define STRUCT_VALUE_REGNUM 13 | |
667 | ||
668 | /* The order in which to allocate registers. */ | |
669 | ||
670 | #define REG_ALLOC_ORDER \ | |
671 | { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \ | |
672 | 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \ | |
673 | 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \ | |
674 | 11, 12, /* g11, g12 */ \ | |
675 | 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \ | |
676 | /* We can't actually allocate these. */ \ | |
677 | 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */ | |
678 | \f | |
679 | /* Define the classes of registers for register constraints in the | |
680 | machine description. Also define ranges of constants. | |
681 | ||
682 | One of the classes must always be named ALL_REGS and include all hard regs. | |
683 | If there is more than one class, another class must be named NO_REGS | |
684 | and contain no registers. | |
685 | ||
686 | The name GENERAL_REGS must be the name of a class (or an alias for | |
687 | another name such as ALL_REGS). This is the class of registers | |
688 | that is allowed by "g" or "r" in a register constraint. | |
689 | Also, registers outside this class are allocated only when | |
690 | instructions express preferences for them. | |
691 | ||
692 | The classes must be numbered in nondecreasing order; that is, | |
693 | a larger-numbered class must never be contained completely | |
694 | in a smaller-numbered class. | |
695 | ||
696 | For any two classes, it is very desirable that there be another | |
697 | class that represents their union. */ | |
698 | ||
699 | /* The 80960 has four kinds of registers, global, local, floating point, | |
700 | and condition code. The cc register is never allocated, so no class | |
701 | needs to be defined for it. */ | |
702 | ||
703 | enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS, | |
704 | FP_REGS, ALL_REGS, LIM_REG_CLASSES }; | |
705 | ||
706 | /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never | |
707 | does. */ | |
708 | #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS) | |
709 | ||
710 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
711 | ||
712 | /* Give names of register classes as strings for dump file. */ | |
713 | ||
714 | #define REG_CLASS_NAMES \ | |
715 | { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \ | |
716 | "FP_REGS", "ALL_REGS" } | |
717 | ||
718 | /* Define which registers fit in which classes. | |
719 | This is an initializer for a vector of HARD_REG_SET | |
720 | of length N_REG_CLASSES. */ | |
721 | ||
722 | #define REG_CLASS_CONTENTS \ | |
723 | { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}} | |
724 | ||
725 | /* The same information, inverted: | |
726 | Return the class number of the smallest class containing | |
727 | reg number REGNO. This could be a conditional expression | |
728 | or could index an array. */ | |
729 | ||
730 | #define REGNO_REG_CLASS(REGNO) \ | |
731 | ((REGNO) < 16 ? GLOBAL_REGS \ | |
732 | : (REGNO) < 32 ? LOCAL_REGS \ | |
733 | : (REGNO) < 36 ? FP_REGS \ | |
734 | : NO_REGS) | |
735 | ||
736 | /* The class value for index registers, and the one for base regs. | |
737 | There is currently no difference between base and index registers on the | |
738 | i960, but this distinction may one day be useful. */ | |
739 | #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS | |
740 | #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS | |
741 | ||
742 | /* Get reg_class from a letter such as appears in the machine description. | |
743 | 'f' is a floating point register (fp0..fp3) | |
744 | 'l' is a local register (r0-r15) | |
745 | 'b' is a global register (g0-g15) | |
746 | 'd' is any local or global register | |
747 | 'r' or 'g' are pre-defined to the class GENERAL_REGS. */ | |
748 | /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not* | |
749 | the same thing, since 'r' may include the fp registers. */ | |
750 | #define REG_CLASS_FROM_LETTER(C) \ | |
751 | (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \ | |
752 | (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS))) | |
753 | ||
754 | /* The letters I, J, K, L and M in a register constraint string | |
755 | can be used to stand for particular ranges of immediate operands. | |
756 | This macro defines what the ranges are. | |
757 | C is the letter, and VALUE is a constant value. | |
758 | Return 1 if VALUE is in the range specified by C. | |
759 | ||
760 | For 80960: | |
761 | 'I' is used for literal values 0..31 | |
762 | 'J' means literal 0 | |
763 | 'K' means 0..-31. */ | |
764 | ||
765 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
766 | ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \ | |
767 | : (C) == 'J' ? ((VALUE) == 0) \ | |
82eaec4a TG |
768 | : (C) == 'K' ? ((VALUE) >= -31 && (VALUE) <= 0) \ |
769 | : (C) == 'M' ? ((VALUE) >= -32 && (VALUE) <= 0) \ | |
770 | : 0) | |
ba8ab355 JW |
771 | |
772 | /* Similar, but for floating constants, and defining letters G and H. | |
773 | Here VALUE is the CONST_DOUBLE rtx itself. | |
774 | For the 80960, G is 0.0 and H is 1.0. */ | |
775 | ||
b6e78be7 TG |
776 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
777 | ((TARGET_NUMERICS) && \ | |
778 | (((C) == 'G' && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \ | |
779 | || ((C) == 'H' && ((VALUE) == CONST1_RTX (GET_MODE (VALUE)))))) | |
ba8ab355 JW |
780 | |
781 | /* Given an rtx X being reloaded into a reg required to be | |
782 | in class CLASS, return the class of reg to actually use. | |
783 | In general this is just CLASS; but on some machines | |
784 | in some cases it is preferable to use a more restrictive class. */ | |
785 | ||
786 | /* On 960, can't load constant into floating-point reg except | |
787 | 0.0 or 1.0. | |
788 | ||
789 | Any hard reg is ok as a src operand of a reload insn. */ | |
790 | ||
791 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
792 | (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \ | |
793 | ? (CLASS) \ | |
794 | : ((CLASS) == FP_REGS && CONSTANT_P (X) \ | |
795 | && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\ | |
796 | && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\ | |
797 | ? NO_REGS \ | |
798 | : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS))) | |
799 | ||
800 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
801 | secondary_reload_class (CLASS, MODE, IN) | |
802 | ||
803 | /* Return the maximum number of consecutive registers | |
804 | needed to represent mode MODE in a register of class CLASS. */ | |
805 | /* On 80960, this is the size of MODE in words, | |
806 | except in the FP regs, where a single reg is always enough. */ | |
807 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
808 | ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE))) | |
809 | \f | |
810 | /* Stack layout; function entry, exit and calling. */ | |
811 | ||
812 | /* Define this if pushing a word on the stack | |
813 | makes the stack pointer a smaller address. */ | |
814 | /* #define STACK_GROWS_DOWNWARD */ | |
815 | ||
816 | /* Define this if the nominal address of the stack frame | |
817 | is at the high-address end of the local variables; | |
818 | that is, each additional local variable allocated | |
819 | goes at a more negative offset in the frame. */ | |
820 | /* #define FRAME_GROWS_DOWNWARD */ | |
821 | ||
822 | /* Offset within stack frame to start allocating local variables at. | |
823 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
824 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
825 | of the first local allocated. | |
826 | ||
827 | The i960 has a 64 byte register save area, plus possibly some extra | |
828 | bytes allocated for varargs functions. */ | |
829 | #define STARTING_FRAME_OFFSET 64 | |
830 | ||
831 | /* If we generate an insn to push BYTES bytes, | |
832 | this says how many the stack pointer really advances by. | |
833 | On 80960, don't define this because there are no push insns. */ | |
834 | /* #define PUSH_ROUNDING(BYTES) BYTES */ | |
835 | ||
836 | /* Offset of first parameter from the argument pointer register value. */ | |
837 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
838 | ||
839 | /* When a parameter is passed in a register, no stack space is | |
840 | allocated for it. However, when args are passed in the | |
841 | stack, space is allocated for every register parameter. */ | |
842 | #define MAYBE_REG_PARM_STACK_SPACE 48 | |
843 | #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \ | |
844 | i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE); | |
845 | #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL) | |
846 | #define OUTGOING_REG_PARM_STACK_SPACE | |
847 | ||
848 | /* Keep the stack pointer constant throughout the function. */ | |
f73ad30e | 849 | #define ACCUMULATE_OUTGOING_ARGS 1 |
ba8ab355 JW |
850 | |
851 | /* Value is 1 if returning from a function call automatically | |
852 | pops the arguments described by the number-of-args field in the call. | |
8b109b37 | 853 | FUNDECL is the declaration node of the function (as a tree), |
ba8ab355 JW |
854 | FUNTYPE is the data type of the function (as a tree), |
855 | or for a library call it is an identifier node for the subroutine name. */ | |
856 | ||
8b109b37 | 857 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
ba8ab355 JW |
858 | |
859 | /* Define how to find the value returned by a library function | |
860 | assuming the value has mode MODE. */ | |
861 | ||
c5c76735 | 862 | #define LIBCALL_VALUE(MODE) gen_rtx_REG ((MODE), 0) |
ba8ab355 JW |
863 | |
864 | /* 1 if N is a possible register number for a function value | |
865 | as seen by the caller. | |
866 | On 80960, returns are in g0..g3 */ | |
867 | ||
cc5ae869 | 868 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) |
ba8ab355 JW |
869 | |
870 | /* 1 if N is a possible register number for function argument passing. | |
871 | On 80960, parameters are passed in g0..g11 */ | |
872 | ||
873 | #define FUNCTION_ARG_REGNO_P(N) ((N) < 12) | |
874 | ||
875 | /* Perform any needed actions needed for a function that is receiving a | |
876 | variable number of arguments. | |
877 | ||
878 | CUM is as above. | |
879 | ||
880 | MODE and TYPE are the mode and type of the current parameter. | |
881 | ||
882 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
883 | that must be pushed by the prolog to pretend that our caller pushed | |
884 | it. | |
885 | ||
886 | Normally, this macro will push all remaining incoming registers on the | |
887 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
888 | ||
889 | #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ | |
890 | i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL) | |
c2749e2d RH |
891 | |
892 | /* Define the `__builtin_va_list' type for the ABI. */ | |
893 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
894 | (VALIST) = i960_build_va_list () | |
895 | ||
896 | /* Implement `va_start' for varargs and stdarg. */ | |
897 | #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \ | |
898 | i960_va_start (stdarg, valist, nextarg) | |
899 | ||
900 | /* Implement `va_arg'. */ | |
901 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
902 | i960_va_arg (valist, type) | |
ba8ab355 JW |
903 | \f |
904 | /* Define a data type for recording info about an argument list | |
905 | during the scan of that argument list. This data type should | |
906 | hold all necessary information about the function itself | |
907 | and about the args processed so far, enough to enable macros | |
908 | such as FUNCTION_ARG to determine where the next arg should go. | |
909 | ||
910 | On 80960, this is two integers, which count the number of register | |
911 | parameters and the number of stack parameters seen so far. */ | |
912 | ||
913 | struct cum_args { int ca_nregparms; int ca_nstackparms; }; | |
914 | ||
915 | #define CUMULATIVE_ARGS struct cum_args | |
916 | ||
917 | /* Define the number of registers that can hold parameters. | |
918 | This macro is used only in macro definitions below and/or i960.c. */ | |
919 | #define NPARM_REGS 12 | |
920 | ||
921 | /* Define how to round to the next parameter boundary. | |
922 | This macro is used only in macro definitions below and/or i960.c. */ | |
b46db6e4 | 923 | #define ROUND_PARM(X, MULTIPLE_OF) \ |
ba8ab355 JW |
924 | ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF) |
925 | ||
926 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
927 | for a call to a function whose data type is FNTYPE. | |
928 | For a library call, FNTYPE is 0. | |
929 | ||
930 | On 80960, the offset always starts at 0; the first parm reg is g0. */ | |
931 | ||
2c7ee1a6 | 932 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
ba8ab355 JW |
933 | ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0) |
934 | ||
935 | /* Update the data in CUM to advance over an argument | |
936 | of mode MODE and data type TYPE. | |
937 | CUM should be advanced to align with the data type accessed and | |
938 | also the size of that data type in # of regs. | |
939 | (TYPE is null for libcalls where that information may not be available.) */ | |
940 | ||
941 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
942 | i960_function_arg_advance(&CUM, MODE, TYPE, NAMED) | |
943 | ||
944 | /* Indicate the alignment boundary for an argument of the specified mode and | |
945 | type. */ | |
946 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
29008b51 JW |
947 | (((TYPE) != 0) \ |
948 | ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \ | |
949 | ? PARM_BOUNDARY \ | |
950 | : TYPE_ALIGN (TYPE)) \ | |
951 | : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \ | |
952 | ? PARM_BOUNDARY \ | |
953 | : GET_MODE_ALIGNMENT (MODE))) | |
ba8ab355 JW |
954 | |
955 | /* Determine where to put an argument to a function. | |
956 | Value is zero to push the argument on the stack, | |
957 | or a hard register in which to store the argument. | |
958 | ||
959 | MODE is the argument's machine mode. | |
960 | TYPE is the data type of the argument (as a tree). | |
961 | This is null for libcalls where that information may | |
962 | not be available. | |
963 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
964 | the preceding args and about the function being called. | |
965 | NAMED is nonzero if this argument is a named parameter | |
966 | (otherwise it is an extra parameter matching an ellipsis). */ | |
967 | ||
ba8ab355 JW |
968 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
969 | i960_function_arg(&CUM, MODE, TYPE, NAMED) | |
970 | ||
971 | /* Define how to find the value returned by a function. | |
972 | VALTYPE is the data type of the value (as a tree). | |
973 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
974 | otherwise, FUNC is 0. */ | |
975 | ||
254f7d80 | 976 | #define FUNCTION_VALUE(TYPE, FUNC) \ |
c5c76735 | 977 | gen_rtx_REG (TYPE_MODE (TYPE), 0) |
ba8ab355 | 978 | |
e14fa9c4 DE |
979 | /* Force aggregates and objects larger than 16 bytes to be returned in memory, |
980 | since we only have 4 registers available for return values. */ | |
ba8ab355 | 981 | |
e14fa9c4 DE |
982 | #define RETURN_IN_MEMORY(TYPE) \ |
983 | (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16) | |
ba8ab355 | 984 | |
40f32220 JW |
985 | /* Don't default to pcc-struct-return, because we have already specified |
986 | exactly how to return structures in the RETURN_IN_MEMORY macro. */ | |
987 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
988 | ||
ba8ab355 JW |
989 | /* For an arg passed partly in registers and partly in memory, |
990 | this is the number of registers used. | |
991 | This never happens on 80960. */ | |
992 | ||
993 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 | |
994 | \f | |
995 | /* Output the label for a function definition. | |
996 | This handles leaf functions and a few other things for the i960. */ | |
997 | ||
998 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ | |
999 | i960_function_name_declare (FILE, NAME, DECL) | |
1000 | ||
ba8ab355 JW |
1001 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1002 | for profiling a function entry. */ | |
1003 | ||
1e39f528 JW |
1004 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1005 | output_function_profiler ((FILE), (LABELNO)); | |
ba8ab355 JW |
1006 | |
1007 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1008 | the stack pointer does not matter. The value is tested only in | |
1009 | functions that have frame pointers. | |
1010 | No definition is equivalent to always zero. */ | |
1011 | ||
1012 | #define EXIT_IGNORE_STACK 1 | |
ba8ab355 JW |
1013 | \f |
1014 | /* Addressing modes, and classification of registers for them. */ | |
1015 | ||
940da324 JL |
1016 | /* #define HAVE_POST_INCREMENT 0 */ |
1017 | /* #define HAVE_POST_DECREMENT 0 */ | |
ba8ab355 | 1018 | |
940da324 JL |
1019 | /* #define HAVE_PRE_DECREMENT 0 */ |
1020 | /* #define HAVE_PRE_INCREMENT 0 */ | |
ba8ab355 JW |
1021 | |
1022 | /* Macros to check register numbers against specific register classes. */ | |
1023 | ||
1024 | /* These assume that REGNO is a hard or pseudo reg number. | |
1025 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1026 | or a pseudo reg currently allocated to a suitable hard reg. | |
1027 | Since they use reg_renumber, they are safe only once reg_renumber | |
1028 | has been allocated, which happens in local-alloc.c. */ | |
1029 | ||
1030 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1031 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) | |
1032 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1033 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) | |
1034 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
1035 | ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36) | |
1036 | ||
1037 | /* Now macros that check whether X is a register and also, | |
1038 | strictly, whether it is in a specified class. | |
1039 | ||
1040 | These macros are specific to the 960, and may be used only | |
1041 | in code for printing assembler insns and in conditions for | |
1042 | define_optimization. */ | |
1043 | ||
1044 | /* 1 if X is an fp register. */ | |
1045 | ||
1046 | #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36) | |
1047 | ||
1048 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1049 | #define MAX_REGS_PER_ADDRESS 2 | |
1050 | ||
6eff269e BK |
1051 | #define CONSTANT_ADDRESS_P(X) \ |
1052 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1053 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1054 | || GET_CODE (X) == HIGH) | |
ba8ab355 JW |
1055 | |
1056 | /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X | |
1057 | is a legitimate general operand. | |
1058 | It is given that X satisfies CONSTANT_P. | |
1059 | ||
819f6d59 JW |
1060 | Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0. |
1061 | ||
1062 | ??? This probably should be defined to 1. */ | |
ba8ab355 JW |
1063 | |
1064 | #define LEGITIMATE_CONSTANT_P(X) \ | |
819f6d59 | 1065 | ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), GET_MODE (X))) |
ba8ab355 JW |
1066 | |
1067 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1068 | and check its validity for a certain class. | |
1069 | We have two alternate definitions for each of them. | |
1070 | The usual definition accepts all pseudo regs; the other rejects | |
1071 | them unless they have been allocated suitable hard regs. | |
1072 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1073 | ||
1074 | Most source files want to accept pseudo regs in the hope that | |
1075 | they will get allocated to the class that the insn wants them to be in. | |
1076 | Source files for reload pass need to be strict. | |
1077 | After reload, it makes no difference, since pseudo regs have | |
1078 | been eliminated by then. */ | |
1079 | ||
1080 | #ifndef REG_OK_STRICT | |
1081 | ||
1082 | /* Nonzero if X is a hard reg that can be used as an index | |
1083 | or if it is a pseudo reg. */ | |
1084 | #define REG_OK_FOR_INDEX_P(X) \ | |
1085 | (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
1086 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1087 | or if it is a pseudo reg. */ | |
1088 | #define REG_OK_FOR_BASE_P(X) \ | |
1089 | (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
1090 | ||
1091 | #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1092 | #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1093 | ||
1094 | #else | |
1095 | ||
1096 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1097 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1098 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1099 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1100 | ||
1101 | #endif | |
1102 | \f | |
1103 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1104 | that is a valid memory address for an instruction. | |
1105 | The MODE argument is the machine mode for the MEM expression | |
1106 | that wants to use this address. | |
1107 | ||
1108 | On 80960, legitimate addresses are: | |
1109 | base ld (g0),r0 | |
1110 | disp (12 or 32 bit) ld foo,r0 | |
1111 | base + index ld (g0)[g1*1],r0 | |
1112 | base + displ ld 0xf00(g0),r0 | |
1113 | base + index*scale + displ ld 0xf00(g0)[g1*4],r0 | |
1114 | index*scale + base ld (g0)[g1*4],r0 | |
1115 | index*scale + displ ld 0xf00[g1*4],r0 | |
1116 | index*scale ld [g1*4],r0 | |
1117 | index + base + displ ld 0xf00(g0)[g1*1],r0 | |
1118 | ||
1119 | In each case, scale can be 1, 2, 4, 8, or 16. */ | |
1120 | ||
e5837c07 | 1121 | /* Returns 1 if the scale factor of an index term is valid. */ |
ba8ab355 JW |
1122 | #define SCALE_TERM_P(X) \ |
1123 | (GET_CODE (X) == CONST_INT \ | |
1124 | && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \ | |
1125 | || INTVAL(X) == 8 || INTVAL (X) == 16)) | |
1126 | ||
1127 | ||
1128 | #ifdef REG_OK_STRICT | |
1129 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1130 | { if (legitimate_address_p (MODE, X, 1)) goto ADDR; } | |
1131 | #else | |
1132 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1133 | { if (legitimate_address_p (MODE, X, 0)) goto ADDR; } | |
1134 | #endif | |
1135 | \f | |
1136 | /* Try machine-dependent ways of modifying an illegitimate address | |
1137 | to be legitimate. If we find one, return the new, valid address. | |
1138 | This macro is used in only one place: `memory_address' in explow.c. | |
1139 | ||
1140 | OLDX is the address as it was before break_out_memory_refs was called. | |
1141 | In some cases it is useful to look at this to decide what needs to be done. | |
1142 | ||
1143 | MODE and WIN are passed so that this macro can use | |
1144 | GO_IF_LEGITIMATE_ADDRESS. | |
1145 | ||
1146 | It is always safe for this macro to do nothing. It exists to recognize | |
1147 | opportunities to optimize the output. */ | |
1148 | ||
13d39dbc | 1149 | /* On 80960, convert non-canonical addresses to canonical form. */ |
ba8ab355 | 1150 | |
ba8ab355 JW |
1151 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
1152 | { rtx orig_x = (X); \ | |
1153 | (X) = legitimize_address (X, OLDX, MODE); \ | |
1154 | if ((X) != orig_x && memory_address_p (MODE, X)) \ | |
1155 | goto WIN; } | |
1156 | ||
1157 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1158 | has an effect that depends on the machine mode it is used for. | |
1159 | On the 960 this is never true. */ | |
1160 | ||
1161 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) | |
1162 | \f | |
1163 | /* Specify the machine mode that this machine uses | |
1164 | for the index in the tablejump instruction. */ | |
1165 | #define CASE_VECTOR_MODE SImode | |
1166 | ||
18543a22 ILT |
1167 | /* Define as C expression which evaluates to nonzero if the tablejump |
1168 | instruction expects the table to contain offsets from the address of the | |
1169 | table. | |
e5837c07 | 1170 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 1171 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ |
ba8ab355 | 1172 | |
ba8ab355 JW |
1173 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1174 | #define DEFAULT_SIGNED_CHAR 0 | |
1175 | ||
1176 | /* Allow and ignore #sccs directives. */ | |
1177 | #define SCCS_DIRECTIVE | |
1178 | ||
1179 | /* Max number of bytes we can move from memory to memory | |
1180 | in one reasonably fast instruction. */ | |
1181 | #define MOVE_MAX 16 | |
1182 | ||
9a63901f RK |
1183 | /* Define if operations between registers always perform the operation |
1184 | on the full register even if a narrower mode is specified. */ | |
1185 | #define WORD_REGISTER_OPERATIONS | |
1186 | ||
1187 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1188 | will either zero-extend or sign-extend. The value of this macro should | |
1189 | be the code that says which one of the two operations is implicitly | |
1190 | done, NIL if none. */ | |
1191 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
ba8ab355 JW |
1192 | |
1193 | /* Nonzero if access to memory by bytes is no faster than for words. | |
8a21007c | 1194 | Value changed to 1 after reports of poor bitfield code with g++. |
e5837c07 | 1195 | Indications are that code is usually as good, sometimes better. */ |
ba8ab355 | 1196 | |
8a21007c | 1197 | #define SLOW_BYTE_ACCESS 1 |
ba8ab355 | 1198 | |
c78358d4 JM |
1199 | /* Force sizeof(bool) == 1 to maintain binary compatibility; otherwise, the |
1200 | change in SLOW_BYTE_ACCESS would have changed it to 4. */ | |
1201 | ||
1202 | #define BOOL_TYPE_SIZE CHAR_TYPE_SIZE | |
1203 | ||
ba8ab355 JW |
1204 | /* We assume that the store-condition-codes instructions store 0 for false |
1205 | and some other value for true. This is the value stored for true. */ | |
1206 | ||
1207 | #define STORE_FLAG_VALUE 1 | |
1208 | ||
d969caf8 | 1209 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
e5837c07 | 1210 | few bits. */ |
82eaec4a | 1211 | #define SHIFT_COUNT_TRUNCATED 0 |
ba8ab355 JW |
1212 | |
1213 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1214 | is done just by pretending it is already truncated. */ | |
1215 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1216 | ||
1217 | /* Specify the machine mode that pointers have. | |
1218 | After generation of rtl, the compiler makes no further distinction | |
1219 | between pointers and any other objects of this machine mode. */ | |
1220 | #define Pmode SImode | |
1221 | ||
1222 | /* Specify the widest mode that BLKmode objects can be promoted to */ | |
1223 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
1224 | \f | |
1225 | /* These global variables are used to pass information between | |
1226 | cc setter and cc user at insn emit time. */ | |
1227 | ||
1228 | extern struct rtx_def *i960_compare_op0, *i960_compare_op1; | |
1229 | ||
ba8ab355 JW |
1230 | /* Add any extra modes needed to represent the condition code. |
1231 | ||
1232 | Also, signed and unsigned comparisons are distinguished, as | |
1233 | are operations which are compatible with chkbit insns. */ | |
aa0b4465 ZW |
1234 | #define EXTRA_CC_MODES \ |
1235 | CC(CC_UNSmode, "CC_UNS") \ | |
1236 | CC(CC_CHKmode, "CC_CHK") | |
ba8ab355 JW |
1237 | |
1238 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
1239 | return the mode to be used for the comparison. For floating-point, CCFPmode | |
1240 | should be used. CC_NOOVmode should be used when the first operand is a | |
1241 | PLUS, MINUS, or NEG. CCmode should be used when no special processing is | |
1242 | needed. */ | |
c3eebffb | 1243 | #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X) |
ba8ab355 JW |
1244 | |
1245 | /* A function address in a call instruction is a byte address | |
1246 | (for indexing purposes) so give the MEM rtx a byte's mode. */ | |
1247 | #define FUNCTION_MODE SImode | |
1248 | ||
1249 | /* Define this if addresses of constant functions | |
1250 | shouldn't be put through pseudo regs where they can be cse'd. | |
1251 | Desirable on machines where ordinary constants are expensive | |
1252 | but a CALL with constant address is cheap. */ | |
1253 | #define NO_FUNCTION_CSE | |
1254 | ||
1255 | /* Use memcpy, etc. instead of bcopy. */ | |
1256 | ||
1257 | #ifndef WIND_RIVER | |
1258 | #define TARGET_MEM_FUNCTIONS 1 | |
1259 | #endif | |
1260 | ||
1261 | /* Compute the cost of computing a constant rtl expression RTX | |
1262 | whose rtx-code is CODE. The body of this macro is a portion | |
1263 | of a switch statement. If the code is computed here, | |
1264 | return it with a return statement. Otherwise, break from the switch. */ | |
1265 | ||
1266 | /* Constants that can be (non-ldconst) insn operands are cost 0. Constants | |
1267 | that can be non-ldconst operands in rare cases are cost 1. Other constants | |
1268 | have higher costs. */ | |
1269 | ||
7a3c92a5 JW |
1270 | /* Must check for OUTER_CODE of SET for power2_operand, because |
1271 | reload_cse_move2add calls us with OUTER_CODE of PLUS to decide when | |
1272 | to replace set with add. */ | |
1273 | ||
ba8ab355 JW |
1274 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
1275 | case CONST_INT: \ | |
1276 | if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \ | |
7a3c92a5 | 1277 | || (OUTER_CODE == SET && power2_operand (RTX, VOIDmode))) \ |
ba8ab355 JW |
1278 | return 0; \ |
1279 | else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \ | |
1280 | return 1; \ | |
1281 | case CONST: \ | |
1282 | case LABEL_REF: \ | |
1283 | case SYMBOL_REF: \ | |
bb210aaf | 1284 | return (TARGET_C_SERIES ? 6 : 8); \ |
ba8ab355 JW |
1285 | case CONST_DOUBLE: \ |
1286 | if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \ | |
1287 | || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\ | |
1288 | return 1; \ | |
1289 | return 12; | |
1290 | ||
1291 | /* The i960 offers addressing modes which are "as cheap as a register". | |
1292 | See i960.c (or gcc.texinfo) for details. */ | |
1293 | ||
1294 | #define ADDRESS_COST(RTX) \ | |
1295 | (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX)) | |
1296 | \f | |
1297 | /* Control the assembler format that we output. */ | |
1298 | ||
1299 | /* Output at beginning of assembler file. */ | |
1300 | ||
1301 | #define ASM_FILE_START(file) | |
1302 | ||
1303 | /* Output to assembler file text saying following lines | |
1304 | may contain character constants, extra white space, comments, etc. */ | |
1305 | ||
1306 | #define ASM_APP_ON "" | |
1307 | ||
1308 | /* Output to assembler file text saying following lines | |
1309 | no longer contain unusual constructs. */ | |
1310 | ||
1311 | #define ASM_APP_OFF "" | |
1312 | ||
1313 | /* Output before read-only data. */ | |
1314 | ||
de323aa1 | 1315 | #define TEXT_SECTION_ASM_OP "\t.text" |
ba8ab355 JW |
1316 | |
1317 | /* Output before writable data. */ | |
1318 | ||
de323aa1 | 1319 | #define DATA_SECTION_ASM_OP "\t.data" |
ba8ab355 JW |
1320 | |
1321 | /* How to refer to registers in assembler output. | |
1322 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1323 | ||
1324 | #define REGISTER_NAMES { \ | |
1325 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \ | |
1326 | "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \ | |
1327 | "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \ | |
1328 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
1329 | "fp0","fp1","fp2", "fp3", "cc", "fake" } | |
1330 | ||
1331 | /* How to renumber registers for dbx and gdb. | |
1332 | In the 960 encoding, g0..g15 are registers 16..31. */ | |
1333 | ||
1334 | #define DBX_REGISTER_NUMBER(REGNO) \ | |
1335 | (((REGNO) < 16) ? (REGNO) + 16 \ | |
1336 | : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16)) | |
1337 | ||
1338 | /* Don't emit dbx records longer than this. This is an arbitrary value. */ | |
1339 | #define DBX_CONTIN_LENGTH 1500 | |
1340 | ||
1341 | /* This is how to output a note to DBX telling it the line number | |
e5837c07 | 1342 | to which the following sequence of instructions corresponds. */ |
ba8ab355 JW |
1343 | |
1344 | #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ | |
1345 | { if (write_symbols == SDB_DEBUG) { \ | |
1346 | fprintf ((FILE), "\t.ln %d\n", \ | |
1347 | (sdb_begin_function_line \ | |
1348 | ? (LINE) - sdb_begin_function_line : 1)); \ | |
1349 | } else if (write_symbols == DBX_DEBUG) { \ | |
1350 | fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \ | |
1351 | } } | |
1352 | ||
1353 | /* This is how to output the definition of a user-level label named NAME, | |
1354 | such as the label on a static function or variable NAME. */ | |
1355 | ||
1356 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1357 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1358 | ||
1359 | /* This is how to output a command to make the user-level label named NAME | |
1360 | defined for reference from other files. */ | |
1361 | ||
1362 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
1363 | { fputs ("\t.globl ", FILE); \ | |
1364 | assemble_name (FILE, NAME); \ | |
1365 | fputs ("\n", FILE); } | |
1366 | ||
e5837c07 | 1367 | /* The prefix to add to user-visible assembler symbols. */ |
ba8ab355 | 1368 | |
4e0c8ad2 | 1369 | #define USER_LABEL_PREFIX "_" |
ba8ab355 JW |
1370 | |
1371 | /* This is how to output an internal numbered label where | |
1372 | PREFIX is the class of label and NUM is the number within the class. */ | |
1373 | ||
1374 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
1375 | fprintf (FILE, "%s%d:\n", PREFIX, NUM) | |
1376 | ||
1377 | /* This is how to store into the string LABEL | |
1378 | the symbol_ref name of an internal numbered label where | |
1379 | PREFIX is the class of label and NUM is the number within the class. | |
1380 | This is suitable for output with `assemble_name'. */ | |
1381 | ||
1382 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
1383 | sprintf (LABEL, "*%s%d", PREFIX, NUM) | |
1384 | ||
ba8ab355 JW |
1385 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ |
1386 | fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO]) | |
1387 | ||
1388 | /* This is how to output an insn to pop a register from the stack. | |
1389 | It need not be very fast code. */ | |
1390 | ||
1391 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
1392 | fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO]) | |
1393 | ||
1394 | /* This is how to output an element of a case-vector that is absolute. */ | |
1395 | ||
1396 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1397 | fprintf (FILE, "\t.word L%d\n", VALUE) | |
1398 | ||
1399 | /* This is how to output an element of a case-vector that is relative. */ | |
1400 | ||
33f7f353 | 1401 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
ba8ab355 JW |
1402 | fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL) |
1403 | ||
1404 | /* This is how to output an assembler line that says to advance the | |
1405 | location counter to a multiple of 2**LOG bytes. */ | |
1406 | ||
1407 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1408 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
1409 | ||
1410 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1411 | fprintf (FILE, "\t.space %d\n", (SIZE)) | |
1412 | ||
1413 | /* This says how to output an assembler line | |
1414 | to define a global common symbol. */ | |
1415 | ||
1416 | /* For common objects, output unpadded size... gld960 & lnk960 both | |
1417 | have code to align each common object at link time. Also, if size | |
1418 | is 0, treat this as a declaration, not a definition - i.e., | |
1419 | do nothing at all. */ | |
1420 | ||
1421 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1422 | { if ((SIZE) != 0) \ | |
1423 | { \ | |
1424 | fputs (".globl ", (FILE)), \ | |
1425 | assemble_name ((FILE), (NAME)), \ | |
1426 | fputs ("\n.comm ", (FILE)), \ | |
1427 | assemble_name ((FILE), (NAME)), \ | |
1bc147fb | 1428 | fprintf ((FILE), ",%d\n", (SIZE)); \ |
ba8ab355 JW |
1429 | } \ |
1430 | } | |
1431 | ||
1432 | /* This says how to output an assembler line to define a local common symbol. | |
1433 | Output unpadded size, with request to linker to align as requested. | |
1434 | 0 size should not be possible here. */ | |
1435 | ||
1436 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ | |
1437 | ( fputs (".bss\t", (FILE)), \ | |
1438 | assemble_name ((FILE), (NAME)), \ | |
1439 | fprintf ((FILE), ",%d,%d\n", (SIZE), \ | |
0ce200e5 JM |
1440 | (floor_log2 ((ALIGN) / BITS_PER_UNIT)))) |
1441 | ||
1442 | /* A C statement (sans semicolon) to output to the stdio stream | |
1443 | FILE the assembler definition of uninitialized global DECL named | |
1444 | NAME whose size is SIZE bytes and alignment is ALIGN bytes. | |
1445 | Try to use asm_output_aligned_bss to implement this macro. */ | |
1446 | ||
1447 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
1448 | do { \ | |
1449 | fputs (".globl ", (FILE)); \ | |
1450 | assemble_name ((FILE), (NAME)); \ | |
1451 | fputs ("\n", (FILE)); \ | |
1452 | ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ | |
1453 | } while (0) | |
ba8ab355 JW |
1454 | |
1455 | /* Output text for an #ident directive. */ | |
1456 | #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR); | |
1457 | ||
1458 | /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */ | |
1459 | ||
fc470718 | 1460 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_CODE_ALIGN ? 3 : 0) |
ba8ab355 JW |
1461 | |
1462 | /* Store in OUTPUT a string (made with alloca) containing | |
1463 | an assembler-name for a local static variable named NAME. | |
1464 | LABELNO is an integer which is different for each call. */ | |
1465 | ||
1466 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1467 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
1468 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
ba8ab355 JW |
1469 | \f |
1470 | /* Output assembler code to FILE to initialize this source file's | |
1471 | basic block profiling info, if that has not already been done. */ | |
1472 | ||
1473 | #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ | |
1474 | { fprintf (FILE, "\tld LPBX0,g12\n"); \ | |
1475 | fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\ | |
1476 | fprintf (FILE, "\tlda LPBX0,g12\n"); \ | |
1477 | fprintf (FILE, "\tcall ___bb_init_func\n"); \ | |
1478 | fprintf (FILE, "LPY%d:\n",LABELNO); } | |
1479 | ||
1480 | /* Output assembler code to FILE to increment the entry-count for | |
1481 | the BLOCKNO'th basic block in this source file. */ | |
1482 | ||
1483 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
1484 | { int blockn = (BLOCKNO); \ | |
1485 | fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \ | |
1486 | fprintf (FILE, "\taddo g12,1,g12\n"); \ | |
1487 | fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); } | |
1488 | \f | |
1489 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1490 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1491 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1492 | ||
1493 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
1494 | i960_print_operand (FILE, X, CODE); | |
1495 | ||
1496 | /* Print a memory address as an operand to reference that memory location. */ | |
1497 | ||
1498 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
1499 | i960_print_operand_addr (FILE, ADDR) | |
eb9c1bb6 RH |
1500 | |
1501 | /* Determine which codes are valid without a following integer. These must | |
1502 | not be alphabetic (the characters are chosen so that | |
1503 | PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when | |
1504 | using ASCII). */ | |
1505 | ||
1506 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '+') | |
ba8ab355 JW |
1507 | \f |
1508 | /* Output assembler code for a block containing the constant parts | |
1509 | of a trampoline, leaving space for the variable parts. */ | |
1510 | ||
1511 | /* On the i960, the trampoline contains three instructions: | |
1512 | ldconst _function, r4 | |
a45f3331 | 1513 | ldconst static addr, g12 |
ba8ab355 JW |
1514 | jump (r4) */ |
1515 | ||
1516 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
1517 | { \ | |
301d03af RS |
1518 | assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x8C203000)); \ |
1519 | assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x00000000)); \ | |
1520 | assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x8CE03000)); \ | |
1521 | assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x00000000)); \ | |
1522 | assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x84212000)); \ | |
ba8ab355 JW |
1523 | } |
1524 | ||
1525 | /* Length in units of the trampoline for entering a nested function. */ | |
1526 | ||
1527 | #define TRAMPOLINE_SIZE 20 | |
1528 | ||
1529 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1530 | FNADDR is an RTX for the address of the function's pure code. | |
1531 | CXT is an RTX for the static chain value for the function. */ | |
1532 | ||
1533 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1534 | { \ | |
c5c76735 JL |
1535 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), FNADDR); \ |
1536 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), CXT); \ | |
ba8ab355 JW |
1537 | } |
1538 | ||
0bc02db4 MS |
1539 | /* Generate RTL to flush the register windows so as to make arbitrary frames |
1540 | available. */ | |
1541 | #define SETUP_FRAME_ADDRESSES() \ | |
1542 | emit_insn (gen_flush_register_windows ()) | |
1543 | ||
1544 | #define BUILTIN_SETJMP_FRAME_VALUE hard_frame_pointer_rtx | |
1545 | ||
ba8ab355 | 1546 | #if 0 |
13d39dbc | 1547 | /* Promote char and short arguments to ints, when want compatibility with |
ba8ab355 JW |
1548 | the iC960 compilers. */ |
1549 | ||
1550 | /* ??? In order for this to work, all users would need to be changed | |
1551 | to test the value of the macro at run time. */ | |
1552 | #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE | |
1553 | /* ??? This does not exist. */ | |
1554 | #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE | |
1555 | #endif | |
1556 | ||
1557 | /* Instruction type definitions. Used to alternate instructions types for | |
1558 | better performance on the C series chips. */ | |
1559 | ||
1560 | enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL }; | |
1561 | ||
1562 | /* Holds the insn type of the last insn output to the assembly file. */ | |
1563 | ||
1564 | extern enum insn_types i960_last_insn_type; | |
1565 | ||
1566 | /* Parse opcodes, and set the insn last insn type based on them. */ | |
1567 | ||
1568 | #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN) | |
1569 | ||
1570 | /* Table listing what rtl codes each predicate in i960.c will accept. */ | |
1571 | ||
1572 | #define PREDICATE_CODES \ | |
1573 | {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ | |
1574 | LABEL_REF, SUBREG, REG, MEM}}, \ | |
1575 | {"arith_operand", {SUBREG, REG, CONST_INT}}, \ | |
82eaec4a | 1576 | {"logic_operand", {SUBREG, REG, CONST_INT}}, \ |
ba8ab355 JW |
1577 | {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \ |
1578 | {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \ | |
1579 | {"literal", {CONST_INT}}, \ | |
1580 | {"fp_literal_one", {CONST_DOUBLE}}, \ | |
1581 | {"fp_literal_double", {CONST_DOUBLE}}, \ | |
1582 | {"fp_literal", {CONST_DOUBLE}}, \ | |
1583 | {"signed_literal", {CONST_INT}}, \ | |
1584 | {"symbolic_memory_operand", {SUBREG, MEM}}, \ | |
1585 | {"eq_or_neq", {EQ, NE}}, \ | |
1586 | {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \ | |
1587 | CONST_DOUBLE, CONST}}, \ | |
f8634644 RK |
1588 | {"power2_operand", {CONST_INT}}, \ |
1589 | {"cmplpower2_operand", {CONST_INT}}, | |
ba8ab355 | 1590 | |
778ebe62 JW |
1591 | /* Defined in reload.c, and used in insn-recog.c. */ |
1592 | ||
1593 | extern int rtx_equal_function_value_matters; | |
3e8d8d4b JM |
1594 | |
1595 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. | |
1596 | Used for C++ multiple inheritance. */ | |
1597 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ | |
1598 | do { \ | |
1599 | int d = (DELTA); \ | |
1600 | if (d < 0 && d > -32) \ | |
1601 | fprintf (FILE, "\tsubo %d,g0,g0\n", -d); \ | |
1602 | else if (d > 0 && d < 32) \ | |
1603 | fprintf (FILE, "\taddo %d,g0,g0\n", d); \ | |
1604 | else \ | |
1605 | { \ | |
1606 | fprintf (FILE, "\tldconst %d,r5\n", d); \ | |
1607 | fprintf (FILE, "\taddo r5,g0,g0\n"); \ | |
1608 | } \ | |
1609 | fprintf (FILE, "\tbx "); \ | |
92d4501f | 1610 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ |
3e8d8d4b JM |
1611 | fprintf (FILE, "\n"); \ |
1612 | } while (0); |