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d2836273 | 1 | ;; GCC machine description for IA-32 and x86-64. |
e03f5d43 | 2 | ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
4592bdcb | 3 | ;; Free Software Foundation, Inc. |
886c62d1 | 4 | ;; Mostly by William Schelter. |
d2836273 | 5 | ;; x86_64 support added by Jan Hubicka |
e075ae69 | 6 | ;; |
886c62d1 | 7 | ;; This file is part of GNU CC. |
e075ae69 | 8 | ;; |
886c62d1 JVA |
9 | ;; GNU CC is free software; you can redistribute it and/or modify |
10 | ;; it under the terms of the GNU General Public License as published by | |
11 | ;; the Free Software Foundation; either version 2, or (at your option) | |
12 | ;; any later version. | |
e075ae69 | 13 | ;; |
886c62d1 JVA |
14 | ;; GNU CC is distributed in the hope that it will be useful, |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
e075ae69 | 18 | ;; |
886c62d1 JVA |
19 | ;; You should have received a copy of the GNU General Public License |
20 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 | 21 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
892a2d68 | 22 | ;; Boston, MA 02111-1307, USA. */ |
e075ae69 | 23 | ;; |
4af3895e JVA |
24 | ;; The original PO technology requires these to be ordered by speed, |
25 | ;; so that assigner will pick the fastest. | |
e075ae69 | 26 | ;; |
4af3895e | 27 | ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. |
e075ae69 | 28 | ;; |
4af3895e JVA |
29 | ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code |
30 | ;; updates for most instructions. | |
e075ae69 | 31 | ;; |
4af3895e JVA |
32 | ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register |
33 | ;; constraint letters. | |
e075ae69 RH |
34 | ;; |
35 | ;; The special asm out single letter directives following a '%' are: | |
4af3895e JVA |
36 | ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of |
37 | ;; operands[1]. | |
38 | ;; 'L' Print the opcode suffix for a 32-bit integer opcode. | |
39 | ;; 'W' Print the opcode suffix for a 16-bit integer opcode. | |
40 | ;; 'B' Print the opcode suffix for an 8-bit integer opcode. | |
4af3895e | 41 | ;; 'Q' Print the opcode suffix for a 64-bit float opcode. |
56710e42 | 42 | ;; 'S' Print the opcode suffix for a 32-bit float opcode. |
b08de47e MM |
43 | ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode. |
44 | ;; 'J' Print the appropriate jump operand. | |
e075ae69 | 45 | ;; |
4af3895e JVA |
46 | ;; 'b' Print the QImode name of the register for the indicated operand. |
47 | ;; %b0 would print %al if operands[0] is reg 0. | |
48 | ;; 'w' Likewise, print the HImode name of the register. | |
49 | ;; 'k' Likewise, print the SImode name of the register. | |
50 | ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. | |
51 | ;; 'y' Print "st(0)" instead of "st" as a register. | |
e075ae69 | 52 | ;; |
4af3895e JVA |
53 | ;; UNSPEC usage: |
54 | ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode. | |
55 | ;; operand 0 is the memory address to scan. | |
56 | ;; operand 1 is a register containing the value to scan for. The mode | |
57 | ;; of the scas opcode will be the same as the mode of this operand. | |
58 | ;; operand 2 is the known alignment of operand 0. | |
a199fdd6 JVA |
59 | ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT. |
60 | ;; operand 0 is the argument for `sin'. | |
61 | ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT. | |
62 | ;; operand 0 is the argument for `cos'. | |
578b58f5 RK |
63 | ;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is |
64 | ;; always SImode. operand 0 is the size of the stack allocation. | |
47d36400 BS |
65 | ;; 4 This is the source of a fake SET of the frame pointer which is used to |
66 | ;; prevent insns referencing it being scheduled across the initial | |
67 | ;; decrement of the stack pointer. | |
ce193852 | 68 | ;; 5 This is a `bsf' operation. |
91bb873f RH |
69 | ;; 6 This is the @GOT offset of a PIC address. |
70 | ;; 7 This is the @GOTOFF offset of a PIC address. | |
71 | ;; 8 This is a reference to a symbol's @PLT address. | |
e075ae69 RH |
72 | ;; 9 This is an `fnstsw' operation. |
73 | ;; 10 This is a `sahf' operation. | |
74 | ;; 11 This is a `fstcw' operation | |
7e08e190 | 75 | ;; 12 This is behaviour of add when setting carry flag. |
1020a5ab | 76 | ;; 13 This is a `eh_return' placeholder. |
915119a5 BS |
77 | |
78 | ;; For SSE/MMX support: | |
79 | ;; 30 This is `fix', guaranteed to be truncating. | |
80 | ;; 31 This is a `emms' operation. | |
81 | ;; 32 This is a `maskmov' operation. | |
82 | ;; 33 This is a `movmsk' operation. | |
83 | ;; 34 This is a `non-temporal' move. | |
7a9aba6c | 84 | ;; 35 This is a `prefetch' (SSE) operation. |
915119a5 BS |
85 | ;; 36 This is used to distinguish COMISS from UCOMISS. |
86 | ;; 37 This is a `ldmxcsr' operation. | |
87 | ;; 38 This is a forced `movaps' instruction (rather than whatever movti does) | |
88 | ;; 39 This is a forced `movups' instruction (rather than whatever movti does) | |
89 | ;; 40 This is a `stmxcsr' operation. | |
90 | ;; 41 This is a `shuffle' operation. | |
91 | ;; 42 This is a `rcp' operation. | |
92 | ;; 43 This is a `rsqsrt' operation. | |
93 | ;; 44 This is a `sfence' operation. | |
94 | ;; 45 This is a noop to prevent excessive combiner cleverness. | |
47f339cf | 95 | ;; 46 This is a `femms' operation. |
47f339cf BS |
96 | ;; 49 This is a 'pavgusb' operation. |
97 | ;; 50 This is a `pfrcp' operation. | |
98 | ;; 51 This is a `pfrcpit1' operation. | |
99 | ;; 52 This is a `pfrcpit2' operation. | |
100 | ;; 53 This is a `pfrsqrt' operation. | |
101 | ;; 54 This is a `pfrsqrit1' operation. | |
915119a5 | 102 | |
6343a50e ZW |
103 | ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls |
104 | ;; from i386.c. | |
105 | ||
1b0c37d7 ZW |
106 | ;; In C guard expressions, put expressions which may be compile-time |
107 | ;; constants first. This allows for better optimization. For | |
108 | ;; example, write "TARGET_64BIT && reload_completed", not | |
109 | ;; "reload_completed && TARGET_64BIT". | |
110 | ||
2ae0f82c | 111 | \f |
e075ae69 RH |
112 | ;; Processor type. This attribute must exactly match the processor_type |
113 | ;; enumeration in i386.h. | |
b4e89e2d | 114 | (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4" |
e075ae69 | 115 | (const (symbol_ref "ix86_cpu"))) |
2ae0f82c | 116 | |
e075ae69 RH |
117 | ;; A basic instruction type. Refinements due to arguments to be |
118 | ;; provided in other attributes. | |
a269a03c | 119 | (define_attr "type" |
22fb740d | 120 | "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp" |
e075ae69 RH |
121 | (const_string "other")) |
122 | ||
6ef67412 | 123 | ;; Main data type used by the insn |
2b04e52b | 124 | (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI" |
6ef67412 JH |
125 | (const_string "unknown")) |
126 | ||
127 | ;; Set for i387 operations. | |
128 | (define_attr "i387" "" | |
22fb740d | 129 | (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp") |
6ef67412 JH |
130 | (const_int 1) |
131 | (const_int 0))) | |
132 | ||
133 | ;; The (bounding maximum) length of an instruction immediate. | |
134 | (define_attr "length_immediate" "" | |
bd793c65 | 135 | (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx") |
6ef67412 JH |
136 | (const_int 0) |
137 | (eq_attr "i387" "1") | |
138 | (const_int 0) | |
139 | (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop") | |
140 | (symbol_ref "ix86_attr_length_immediate_default(insn,1)") | |
141 | (eq_attr "type" "imov,test") | |
142 | (symbol_ref "ix86_attr_length_immediate_default(insn,0)") | |
143 | (eq_attr "type" "call") | |
144 | (if_then_else (match_operand 0 "constant_call_address_operand" "") | |
145 | (const_int 4) | |
146 | (const_int 0)) | |
147 | (eq_attr "type" "callv") | |
148 | (if_then_else (match_operand 1 "constant_call_address_operand" "") | |
149 | (const_int 4) | |
150 | (const_int 0)) | |
151 | (eq_attr "type" "ibr") | |
152 | (if_then_else (and (ge (minus (match_dup 0) (pc)) | |
153 | (const_int -128)) | |
154 | (lt (minus (match_dup 0) (pc)) | |
155 | (const_int 124))) | |
156 | (const_int 1) | |
157 | (const_int 4)) | |
158 | ] | |
159 | (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1"))) | |
e075ae69 | 160 | |
6ef67412 JH |
161 | ;; The (bounding maximum) length of an instruction address. |
162 | (define_attr "length_address" "" | |
163 | (cond [(eq_attr "type" "str,cld,other,multi,fxch") | |
164 | (const_int 0) | |
165 | (and (eq_attr "type" "call") | |
166 | (match_operand 1 "constant_call_address_operand" "")) | |
167 | (const_int 0) | |
168 | (and (eq_attr "type" "callv") | |
169 | (match_operand 1 "constant_call_address_operand" "")) | |
170 | (const_int 0) | |
171 | ] | |
172 | (symbol_ref "ix86_attr_length_address_default (insn)"))) | |
173 | ||
174 | ;; Set when length prefix is used. | |
175 | (define_attr "prefix_data16" "" | |
176 | (if_then_else (eq_attr "mode" "HI") | |
177 | (const_int 1) | |
178 | (const_int 0))) | |
179 | ||
180 | ;; Set when string REP prefix is used. | |
181 | (define_attr "prefix_rep" "" (const_int 0)) | |
182 | ||
183 | ;; Set when 0f opcode prefix is used. | |
184 | (define_attr "prefix_0f" "" | |
bd793c65 | 185 | (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx") |
6ef67412 JH |
186 | (const_int 1) |
187 | (const_int 0))) | |
188 | ||
189 | ;; Set when modrm byte is used. | |
190 | (define_attr "modrm" "" | |
191 | (cond [(eq_attr "type" "str,cld") | |
192 | (const_int 0) | |
193 | (eq_attr "i387" "1") | |
194 | (const_int 0) | |
e075ae69 RH |
195 | (and (eq_attr "type" "incdec") |
196 | (ior (match_operand:SI 1 "register_operand" "") | |
197 | (match_operand:HI 1 "register_operand" ""))) | |
6ef67412 | 198 | (const_int 0) |
e075ae69 RH |
199 | (and (eq_attr "type" "push") |
200 | (not (match_operand 1 "memory_operand" ""))) | |
6ef67412 | 201 | (const_int 0) |
e075ae69 RH |
202 | (and (eq_attr "type" "pop") |
203 | (not (match_operand 0 "memory_operand" ""))) | |
6ef67412 | 204 | (const_int 0) |
e075ae69 RH |
205 | (and (eq_attr "type" "imov") |
206 | (and (match_operand 0 "register_operand" "") | |
207 | (match_operand 1 "immediate_operand" ""))) | |
6ef67412 | 208 | (const_int 0) |
e075ae69 | 209 | ] |
6ef67412 JH |
210 | (const_int 1))) |
211 | ||
212 | ;; The (bounding maximum) length of an instruction in bytes. | |
22fb740d JH |
213 | ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want |
214 | ;; to split it and compute proper length as for other insns. | |
6ef67412 | 215 | (define_attr "length" "" |
22fb740d | 216 | (cond [(eq_attr "type" "other,multi,fistp") |
6ef67412 JH |
217 | (const_int 16) |
218 | ] | |
219 | (plus (plus (attr "modrm") | |
220 | (plus (attr "prefix_0f") | |
221 | (plus (attr "i387") | |
222 | (const_int 1)))) | |
223 | (plus (attr "prefix_rep") | |
224 | (plus (attr "prefix_data16") | |
225 | (plus (attr "length_immediate") | |
226 | (attr "length_address"))))))) | |
e075ae69 RH |
227 | |
228 | ;; The `memory' attribute is `none' if no memory is referenced, `load' or | |
229 | ;; `store' if there is a simple memory reference therein, or `unknown' | |
230 | ;; if the instruction is complex. | |
231 | ||
232 | (define_attr "memory" "none,load,store,both,unknown" | |
7c7ef435 | 233 | (cond [(eq_attr "type" "other,multi,str") |
e075ae69 | 234 | (const_string "unknown") |
7c7ef435 | 235 | (eq_attr "type" "lea,fcmov,fpspc,cld") |
e075ae69 | 236 | (const_string "none") |
22fb740d JH |
237 | (eq_attr "type" "fistp") |
238 | (const_string "both") | |
e075ae69 RH |
239 | (eq_attr "type" "push") |
240 | (if_then_else (match_operand 1 "memory_operand" "") | |
241 | (const_string "both") | |
242 | (const_string "store")) | |
243 | (eq_attr "type" "pop,setcc") | |
244 | (if_then_else (match_operand 0 "memory_operand" "") | |
245 | (const_string "both") | |
246 | (const_string "load")) | |
6ef67412 | 247 | (eq_attr "type" "icmp,test") |
e075ae69 RH |
248 | (if_then_else (ior (match_operand 0 "memory_operand" "") |
249 | (match_operand 1 "memory_operand" "")) | |
250 | (const_string "load") | |
251 | (const_string "none")) | |
252 | (eq_attr "type" "ibr") | |
253 | (if_then_else (match_operand 0 "memory_operand" "") | |
254 | (const_string "load") | |
255 | (const_string "none")) | |
256 | (eq_attr "type" "call") | |
257 | (if_then_else (match_operand 0 "constant_call_address_operand" "") | |
258 | (const_string "none") | |
259 | (const_string "load")) | |
260 | (eq_attr "type" "callv") | |
261 | (if_then_else (match_operand 1 "constant_call_address_operand" "") | |
262 | (const_string "none") | |
263 | (const_string "load")) | |
264 | (and (eq_attr "type" "alu1,negnot") | |
a269a03c | 265 | (match_operand 1 "memory_operand" "")) |
e075ae69 RH |
266 | (const_string "both") |
267 | (and (match_operand 0 "memory_operand" "") | |
268 | (match_operand 1 "memory_operand" "")) | |
269 | (const_string "both") | |
270 | (match_operand 0 "memory_operand" "") | |
271 | (const_string "store") | |
272 | (match_operand 1 "memory_operand" "") | |
273 | (const_string "load") | |
915119a5 | 274 | (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx") |
e075ae69 RH |
275 | (match_operand 2 "memory_operand" "")) |
276 | (const_string "load") | |
277 | (and (eq_attr "type" "icmov") | |
278 | (match_operand 3 "memory_operand" "")) | |
279 | (const_string "load") | |
280 | ] | |
a269a03c JC |
281 | (const_string "none"))) |
282 | ||
e075ae69 RH |
283 | ;; Indicates if an instruction has both an immediate and a displacement. |
284 | ||
285 | (define_attr "imm_disp" "false,true,unknown" | |
286 | (cond [(eq_attr "type" "other,multi") | |
287 | (const_string "unknown") | |
6ef67412 | 288 | (and (eq_attr "type" "icmp,test,imov") |
e075ae69 RH |
289 | (and (match_operand 0 "memory_displacement_operand" "") |
290 | (match_operand 1 "immediate_operand" ""))) | |
291 | (const_string "true") | |
292 | (and (eq_attr "type" "alu,ishift,imul,idiv") | |
293 | (and (match_operand 0 "memory_displacement_operand" "") | |
294 | (match_operand 2 "immediate_operand" ""))) | |
295 | (const_string "true") | |
296 | ] | |
297 | (const_string "false"))) | |
298 | ||
299 | ;; Indicates if an FP operation has an integer source. | |
300 | ||
301 | (define_attr "fp_int_src" "false,true" | |
302 | (const_string "false")) | |
303 | ||
304 | ;; Describe a user's asm statement. | |
305 | (define_asm_attributes | |
306 | [(set_attr "length" "128") | |
307 | (set_attr "type" "multi")]) | |
308 | \f | |
309 | ;; Pentium Scheduling | |
310 | ;; | |
311 | ;; The Pentium is an in-order core with two integer pipelines. | |
312 | ||
6ef67412 JH |
313 | ;; True for insns that behave like prefixed insns on the Pentium. |
314 | (define_attr "pent_prefix" "false,true" | |
315 | (if_then_else (ior (eq_attr "prefix_0f" "1") | |
316 | (ior (eq_attr "prefix_data16" "1") | |
317 | (eq_attr "prefix_rep" "1"))) | |
318 | (const_string "true") | |
319 | (const_string "false"))) | |
320 | ||
e075ae69 RH |
321 | ;; Categorize how an instruction slots. |
322 | ||
323 | ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only, | |
324 | ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium | |
325 | ;; rules, because it results in noticeably better code on non-MMX Pentium | |
326 | ;; and doesn't hurt much on MMX. (Prefixed instructions are not very | |
327 | ;; common, so the scheduler usualy has a non-prefixed insn to pair). | |
328 | ||
329 | (define_attr "pent_pair" "uv,pu,pv,np" | |
330 | (cond [(eq_attr "imm_disp" "true") | |
331 | (const_string "np") | |
6ef67412 JH |
332 | (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec") |
333 | (and (eq_attr "type" "pop,push") | |
334 | (eq_attr "memory" "!both"))) | |
335 | (if_then_else (eq_attr "pent_prefix" "true") | |
e075ae69 RH |
336 | (const_string "pu") |
337 | (const_string "uv")) | |
338 | (eq_attr "type" "ibr") | |
339 | (const_string "pv") | |
340 | (and (eq_attr "type" "ishift") | |
341 | (match_operand 2 "const_int_operand" "")) | |
342 | (const_string "pu") | |
e075ae69 RH |
343 | (and (eq_attr "type" "call") |
344 | (match_operand 0 "constant_call_address_operand" "")) | |
345 | (const_string "pv") | |
346 | (and (eq_attr "type" "callv") | |
347 | (match_operand 1 "constant_call_address_operand" "")) | |
348 | (const_string "pv") | |
349 | ] | |
350 | (const_string "np"))) | |
351 | ||
352 | ;; Rough readiness numbers. Fine tuning happens in i386.c. | |
353 | ;; | |
354 | ;; u describes pipe U | |
355 | ;; v describes pipe V | |
356 | ;; uv describes either pipe U or V for those that can issue to either | |
357 | ;; np describes not paring | |
358 | ;; fpu describes fpu | |
359 | ;; fpm describes fp insns of different types are not pipelined. | |
360 | ;; | |
361 | ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real. | |
2ae0f82c | 362 | |
e075ae69 RH |
363 | (define_function_unit "pent_np" 1 0 |
364 | (and (eq_attr "cpu" "pentium") | |
365 | (eq_attr "type" "imul")) | |
366 | 11 11) | |
36cf4bcf | 367 | |
e075ae69 RH |
368 | (define_function_unit "pent_mul" 1 1 |
369 | (and (eq_attr "cpu" "pentium") | |
370 | (eq_attr "type" "imul")) | |
371 | 11 11) | |
36cf4bcf | 372 | |
7c7ef435 JH |
373 | ;; Rep movs takes minimally 12 cycles. |
374 | (define_function_unit "pent_np" 1 0 | |
375 | (and (eq_attr "cpu" "pentium") | |
376 | (eq_attr "type" "str")) | |
377 | 12 12) | |
378 | ||
e075ae69 RH |
379 | ; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22 |
380 | (define_function_unit "pent_np" 1 0 | |
381 | (and (eq_attr "cpu" "pentium") | |
382 | (eq_attr "type" "idiv")) | |
383 | 46 46) | |
384 | ||
385 | ; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode, | |
386 | ; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF. | |
387 | ; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable. | |
388 | ; The integer <-> fp conversion is not modeled correctly. Fild behaves | |
389 | ; like normal fp operation and fist takes 6 cycles. | |
390 | ||
391 | (define_function_unit "fpu" 1 0 | |
392 | (and (eq_attr "cpu" "pentium") | |
393 | (and (eq_attr "type" "fmov") | |
2b589241 JH |
394 | (and (eq_attr "memory" "load,store") |
395 | (eq_attr "mode" "XF")))) | |
e075ae69 RH |
396 | 3 3) |
397 | ||
398 | (define_function_unit "pent_np" 1 0 | |
399 | (and (eq_attr "cpu" "pentium") | |
400 | (and (eq_attr "type" "fmov") | |
2b589241 JH |
401 | (and (eq_attr "memory" "load,store") |
402 | (eq_attr "mode" "XF")))) | |
e075ae69 RH |
403 | 3 3) |
404 | ||
405 | (define_function_unit "fpu" 1 0 | |
406 | (and (eq_attr "cpu" "pentium") | |
407 | (and (eq_attr "type" "fmov") | |
408 | (ior (match_operand 1 "immediate_operand" "") | |
409 | (eq_attr "memory" "store")))) | |
410 | 2 2) | |
36cf4bcf | 411 | |
e075ae69 RH |
412 | (define_function_unit "pent_np" 1 0 |
413 | (and (eq_attr "cpu" "pentium") | |
414 | (and (eq_attr "type" "fmov") | |
415 | (ior (match_operand 1 "immediate_operand" "") | |
416 | (eq_attr "memory" "store")))) | |
417 | 2 2) | |
2ae0f82c | 418 | |
7c7ef435 JH |
419 | (define_function_unit "pent_np" 1 0 |
420 | (and (eq_attr "cpu" "pentium") | |
421 | (eq_attr "type" "cld")) | |
422 | 2 2) | |
423 | ||
e075ae69 RH |
424 | (define_function_unit "fpu" 1 0 |
425 | (and (eq_attr "cpu" "pentium") | |
426 | (and (eq_attr "type" "fmov") | |
427 | (eq_attr "memory" "none,load"))) | |
428 | 1 1) | |
429 | ||
430 | ; Read/Modify/Write instructions usually take 3 cycles. | |
431 | (define_function_unit "pent_u" 1 0 | |
432 | (and (eq_attr "cpu" "pentium") | |
433 | (and (eq_attr "type" "alu,alu1,ishift") | |
434 | (and (eq_attr "pent_pair" "pu") | |
435 | (eq_attr "memory" "both")))) | |
436 | 3 3) | |
437 | ||
438 | (define_function_unit "pent_uv" 2 0 | |
439 | (and (eq_attr "cpu" "pentium") | |
440 | (and (eq_attr "type" "alu,alu1,ishift") | |
441 | (and (eq_attr "pent_pair" "!np") | |
442 | (eq_attr "memory" "both")))) | |
443 | 3 3) | |
444 | ||
445 | (define_function_unit "pent_np" 1 0 | |
446 | (and (eq_attr "cpu" "pentium") | |
447 | (and (eq_attr "type" "alu,alu1,negnot,ishift") | |
448 | (and (eq_attr "pent_pair" "np") | |
449 | (eq_attr "memory" "both")))) | |
450 | 3 3) | |
451 | ||
452 | ; Read/Modify or Modify/Write instructions usually take 2 cycles. | |
453 | (define_function_unit "pent_u" 1 0 | |
454 | (and (eq_attr "cpu" "pentium") | |
455 | (and (eq_attr "type" "alu,ishift") | |
456 | (and (eq_attr "pent_pair" "pu") | |
457 | (eq_attr "memory" "load,store")))) | |
458 | 2 2) | |
2ae0f82c | 459 | |
e075ae69 RH |
460 | (define_function_unit "pent_uv" 2 0 |
461 | (and (eq_attr "cpu" "pentium") | |
462 | (and (eq_attr "type" "alu,ishift") | |
463 | (and (eq_attr "pent_pair" "!np") | |
464 | (eq_attr "memory" "load,store")))) | |
465 | 2 2) | |
2ae0f82c | 466 | |
e075ae69 RH |
467 | (define_function_unit "pent_np" 1 0 |
468 | (and (eq_attr "cpu" "pentium") | |
469 | (and (eq_attr "type" "alu,ishift") | |
470 | (and (eq_attr "pent_pair" "np") | |
471 | (eq_attr "memory" "load,store")))) | |
472 | 2 2) | |
36cf4bcf | 473 | |
e075ae69 RH |
474 | ; Insns w/o memory operands and move instructions usually take one cycle. |
475 | (define_function_unit "pent_u" 1 0 | |
476 | (and (eq_attr "cpu" "pentium") | |
477 | (eq_attr "pent_pair" "pu")) | |
478 | 1 1) | |
479 | ||
480 | (define_function_unit "pent_v" 1 0 | |
481 | (and (eq_attr "cpu" "pentium") | |
482 | (eq_attr "pent_pair" "pv")) | |
483 | 1 1) | |
484 | ||
485 | (define_function_unit "pent_uv" 2 0 | |
486 | (and (eq_attr "cpu" "pentium") | |
487 | (eq_attr "pent_pair" "!np")) | |
488 | 1 1) | |
489 | ||
490 | (define_function_unit "pent_np" 1 0 | |
491 | (and (eq_attr "cpu" "pentium") | |
492 | (eq_attr "pent_pair" "np")) | |
493 | 1 1) | |
494 | ||
495 | ; Pairable insns only conflict with other non-pairable insns. | |
496 | (define_function_unit "pent_np" 1 0 | |
497 | (and (eq_attr "cpu" "pentium") | |
498 | (and (eq_attr "type" "alu,alu1,ishift") | |
499 | (and (eq_attr "pent_pair" "!np") | |
500 | (eq_attr "memory" "both")))) | |
501 | 3 3 | |
502 | [(eq_attr "pent_pair" "np")]) | |
503 | ||
504 | (define_function_unit "pent_np" 1 0 | |
505 | (and (eq_attr "cpu" "pentium") | |
506 | (and (eq_attr "type" "alu,alu1,ishift") | |
507 | (and (eq_attr "pent_pair" "!np") | |
508 | (eq_attr "memory" "load,store")))) | |
509 | 2 2 | |
510 | [(eq_attr "pent_pair" "np")]) | |
511 | ||
512 | (define_function_unit "pent_np" 1 0 | |
513 | (and (eq_attr "cpu" "pentium") | |
514 | (eq_attr "pent_pair" "!np")) | |
515 | 1 1 | |
516 | [(eq_attr "pent_pair" "np")]) | |
517 | ||
518 | ; Floating point instructions usually blocks cycle longer when combined with | |
519 | ; integer instructions, because of the inpaired fxch instruction. | |
520 | (define_function_unit "pent_np" 1 0 | |
521 | (and (eq_attr "cpu" "pentium") | |
22fb740d | 522 | (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp")) |
e075ae69 | 523 | 2 2 |
22fb740d | 524 | [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp")]) |
e075ae69 RH |
525 | |
526 | (define_function_unit "fpu" 1 0 | |
527 | (and (eq_attr "cpu" "pentium") | |
528 | (eq_attr "type" "fcmp,fxch,fsgn")) | |
529 | 1 1) | |
530 | ||
531 | ; Addition takes 3 cycles; assume other random cruft does as well. | |
532 | ; ??? Trivial fp operations such as fabs or fchs takes only one cycle. | |
533 | (define_function_unit "fpu" 1 0 | |
534 | (and (eq_attr "cpu" "pentium") | |
22fb740d | 535 | (eq_attr "type" "fop,fop1,fistp")) |
e075ae69 RH |
536 | 3 1) |
537 | ||
538 | ; Multiplication takes 3 cycles and is only half pipelined. | |
539 | (define_function_unit "fpu" 1 0 | |
540 | (and (eq_attr "cpu" "pentium") | |
541 | (eq_attr "type" "fmul")) | |
542 | 3 1) | |
543 | ||
544 | (define_function_unit "pent_mul" 1 1 | |
545 | (and (eq_attr "cpu" "pentium") | |
546 | (eq_attr "type" "fmul")) | |
547 | 2 2) | |
36cf4bcf | 548 | |
e075ae69 RH |
549 | ; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles. |
550 | ; They can overlap with integer insns. Only the last two cycles can overlap | |
551 | ; with other fp insns. Only fsin/fcos can overlap with multiplies. | |
552 | ; Only last two cycles of fsin/fcos can overlap with other instructions. | |
553 | (define_function_unit "fpu" 1 0 | |
554 | (and (eq_attr "cpu" "pentium") | |
555 | (eq_attr "type" "fdiv")) | |
556 | 39 37) | |
557 | ||
558 | (define_function_unit "pent_mul" 1 1 | |
559 | (and (eq_attr "cpu" "pentium") | |
560 | (eq_attr "type" "fdiv")) | |
561 | 39 39) | |
562 | ||
563 | (define_function_unit "fpu" 1 0 | |
564 | (and (eq_attr "cpu" "pentium") | |
565 | (eq_attr "type" "fpspc")) | |
566 | 70 68) | |
567 | ||
568 | (define_function_unit "pent_mul" 1 1 | |
569 | (and (eq_attr "cpu" "pentium") | |
570 | (eq_attr "type" "fpspc")) | |
571 | 70 70) | |
572 | \f | |
573 | ;; Pentium Pro/PII Scheduling | |
574 | ;; | |
575 | ;; The PPro has an out-of-order core, but the instruction decoders are | |
576 | ;; naturally in-order and asymmetric. We get best performance by scheduling | |
577 | ;; for the decoders, for in doing so we give the oo execution unit the | |
578 | ;; most choices. | |
579 | ||
580 | ;; Categorize how many uops an ia32 instruction evaluates to: | |
581 | ;; one -- an instruction with 1 uop can be decoded by any of the | |
582 | ;; three decoders. | |
583 | ;; few -- an instruction with 1 to 4 uops can be decoded only by | |
584 | ;; decoder 0. | |
585 | ;; many -- a complex instruction may take an unspecified number of | |
586 | ;; cycles to decode in decoder 0. | |
587 | ||
588 | (define_attr "ppro_uops" "one,few,many" | |
7c7ef435 | 589 | (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str") |
e075ae69 | 590 | (const_string "many") |
7c7ef435 | 591 | (eq_attr "type" "icmov,fcmov,str,cld") |
e075ae69 RH |
592 | (const_string "few") |
593 | (eq_attr "type" "imov") | |
594 | (if_then_else (eq_attr "memory" "store,both") | |
595 | (const_string "few") | |
596 | (const_string "one")) | |
597 | (eq_attr "memory" "!none") | |
598 | (const_string "few") | |
599 | ] | |
600 | (const_string "one"))) | |
601 | ||
602 | ;; Rough readiness numbers. Fine tuning happens in i386.c. | |
603 | ;; | |
604 | ;; p0 describes port 0. | |
605 | ;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either. | |
606 | ;; p2 describes port 2 for loads. | |
607 | ;; p34 describes ports 3 and 4 for stores. | |
608 | ;; fpu describes the fpu accessed via port 0. | |
609 | ;; ??? It is less than clear if there are separate fadd and fmul units | |
610 | ;; that could operate in parallel. | |
611 | ;; | |
612 | ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real. | |
613 | ||
614 | (define_function_unit "ppro_p0" 1 0 | |
615 | (and (eq_attr "cpu" "pentiumpro") | |
7c7ef435 | 616 | (eq_attr "type" "ishift,lea,ibr,cld")) |
e075ae69 RH |
617 | 1 1) |
618 | ||
619 | (define_function_unit "ppro_p0" 1 0 | |
620 | (and (eq_attr "cpu" "pentiumpro") | |
621 | (eq_attr "type" "imul")) | |
622 | 4 1) | |
623 | ||
624 | ;; ??? Does the divider lock out the pipe while it works, | |
625 | ;; or is there a disconnected unit? | |
626 | (define_function_unit "ppro_p0" 1 0 | |
627 | (and (eq_attr "cpu" "pentiumpro") | |
628 | (eq_attr "type" "idiv")) | |
629 | 17 17) | |
36cf4bcf | 630 | |
e075ae69 RH |
631 | (define_function_unit "ppro_p0" 1 0 |
632 | (and (eq_attr "cpu" "pentiumpro") | |
22fb740d | 633 | (eq_attr "type" "fop,fop1,fsgn,fistp")) |
e075ae69 RH |
634 | 3 1) |
635 | ||
636 | (define_function_unit "ppro_p0" 1 0 | |
637 | (and (eq_attr "cpu" "pentiumpro") | |
638 | (eq_attr "type" "fcmov")) | |
639 | 2 1) | |
640 | ||
641 | (define_function_unit "ppro_p0" 1 0 | |
642 | (and (eq_attr "cpu" "pentiumpro") | |
643 | (eq_attr "type" "fcmp")) | |
644 | 1 1) | |
645 | ||
646 | (define_function_unit "ppro_p0" 1 0 | |
647 | (and (eq_attr "cpu" "pentiumpro") | |
648 | (eq_attr "type" "fmov")) | |
649 | 1 1) | |
650 | ||
651 | (define_function_unit "ppro_p0" 1 0 | |
652 | (and (eq_attr "cpu" "pentiumpro") | |
653 | (eq_attr "type" "fmul")) | |
654 | 5 1) | |
655 | ||
656 | (define_function_unit "ppro_p0" 1 0 | |
657 | (and (eq_attr "cpu" "pentiumpro") | |
658 | (eq_attr "type" "fdiv,fpspc")) | |
659 | 56 1) | |
660 | ||
661 | (define_function_unit "ppro_p01" 2 0 | |
662 | (and (eq_attr "cpu" "pentiumpro") | |
663 | (eq_attr "type" "!imov,fmov")) | |
664 | 1 1) | |
665 | ||
666 | (define_function_unit "ppro_p01" 2 0 | |
667 | (and (and (eq_attr "cpu" "pentiumpro") | |
668 | (eq_attr "type" "imov,fmov")) | |
669 | (eq_attr "memory" "none")) | |
670 | 1 1) | |
671 | ||
672 | (define_function_unit "ppro_p2" 1 0 | |
673 | (and (eq_attr "cpu" "pentiumpro") | |
674 | (ior (eq_attr "type" "pop") | |
675 | (eq_attr "memory" "load,both"))) | |
676 | 3 1) | |
677 | ||
678 | (define_function_unit "ppro_p34" 1 0 | |
679 | (and (eq_attr "cpu" "pentiumpro") | |
680 | (ior (eq_attr "type" "push") | |
681 | (eq_attr "memory" "store,both"))) | |
682 | 1 1) | |
683 | ||
684 | (define_function_unit "fpu" 1 0 | |
685 | (and (eq_attr "cpu" "pentiumpro") | |
22fb740d | 686 | (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov,fistp")) |
e075ae69 RH |
687 | 1 1) |
688 | ||
689 | (define_function_unit "fpu" 1 0 | |
690 | (and (eq_attr "cpu" "pentiumpro") | |
691 | (eq_attr "type" "fmul")) | |
692 | 5 2) | |
693 | ||
694 | (define_function_unit "fpu" 1 0 | |
695 | (and (eq_attr "cpu" "pentiumpro") | |
696 | (eq_attr "type" "fdiv,fpspc")) | |
697 | 56 56) | |
698 | ||
699 | ;; imul uses the fpu. ??? does it have the same throughput as fmul? | |
700 | (define_function_unit "fpu" 1 0 | |
701 | (and (eq_attr "cpu" "pentiumpro") | |
702 | (eq_attr "type" "imul")) | |
703 | 4 1) | |
704 | \f | |
705 | ;; AMD K6/K6-2 Scheduling | |
706 | ;; | |
707 | ;; The K6 has similar architecture to PPro. Important difference is, that | |
708 | ;; there are only two decoders and they seems to be much slower than execution | |
709 | ;; units. So we have to pay much more attention to proper decoding for | |
710 | ;; schedulers. We share most of scheduler code for PPro in i386.c | |
711 | ;; | |
712 | ;; The fp unit is not pipelined and do one operation per two cycles including | |
713 | ;; the FXCH. | |
714 | ;; | |
715 | ;; alu describes both ALU units (ALU-X and ALU-Y). | |
716 | ;; alux describes X alu unit | |
717 | ;; fpu describes FPU unit | |
718 | ;; load describes load unit. | |
719 | ;; branch describes branch unit. | |
720 | ;; store decsribes store unit. This unit is not modelled completely and only | |
721 | ;; used to model lea operation. Otherwise it lie outside of the critical | |
722 | ;; path. | |
723 | ;; | |
724 | ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real. | |
36cf4bcf | 725 | |
e075ae69 | 726 | ;; The decoder specification is in the PPro section above! |
2ae0f82c | 727 | |
e075ae69 RH |
728 | ;; Shift instructions and certain arithmetic are issued only to X pipe. |
729 | (define_function_unit "k6_alux" 1 0 | |
730 | (and (eq_attr "cpu" "k6") | |
7c7ef435 | 731 | (eq_attr "type" "ishift,alu1,negnot,cld")) |
e075ae69 | 732 | 1 1) |
2ae0f82c | 733 | |
e075ae69 RH |
734 | ;; The QI mode arithmetic is issued to X pipe only. |
735 | (define_function_unit "k6_alux" 1 0 | |
736 | (and (eq_attr "cpu" "k6") | |
6ef67412 | 737 | (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec") |
e075ae69 RH |
738 | (match_operand:QI 0 "general_operand" ""))) |
739 | 1 1) | |
a269a03c | 740 | |
e075ae69 RH |
741 | (define_function_unit "k6_alu" 2 0 |
742 | (and (eq_attr "cpu" "k6") | |
6ef67412 | 743 | (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea")) |
e075ae69 | 744 | 1 1) |
a269a03c | 745 | |
e075ae69 RH |
746 | (define_function_unit "k6_alu" 2 0 |
747 | (and (eq_attr "cpu" "k6") | |
748 | (and (eq_attr "type" "imov") | |
749 | (eq_attr "memory" "none"))) | |
750 | 1 1) | |
a269a03c | 751 | |
e075ae69 | 752 | (define_function_unit "k6_branch" 1 0 |
a269a03c | 753 | (and (eq_attr "cpu" "k6") |
e075ae69 RH |
754 | (eq_attr "type" "call,callv,ibr")) |
755 | 1 1) | |
a269a03c | 756 | |
e075ae69 RH |
757 | ;; Load unit have two cycle latency, but we take care for it in adjust_cost |
758 | (define_function_unit "k6_load" 1 0 | |
a269a03c | 759 | (and (eq_attr "cpu" "k6") |
e075ae69 RH |
760 | (ior (eq_attr "type" "pop") |
761 | (eq_attr "memory" "load,both"))) | |
762 | 1 1) | |
a269a03c | 763 | |
7c7ef435 JH |
764 | (define_function_unit "k6_load" 1 0 |
765 | (and (eq_attr "cpu" "k6") | |
766 | (and (eq_attr "type" "str") | |
767 | (eq_attr "memory" "load,both"))) | |
768 | 10 10) | |
769 | ||
e075ae69 RH |
770 | ;; Lea have two instructions, so latency is probably 2 |
771 | (define_function_unit "k6_store" 1 0 | |
772 | (and (eq_attr "cpu" "k6") | |
773 | (eq_attr "type" "lea")) | |
774 | 2 1) | |
a269a03c | 775 | |
7c7ef435 JH |
776 | (define_function_unit "k6_store" 1 0 |
777 | (and (eq_attr "cpu" "k6") | |
778 | (eq_attr "type" "str")) | |
779 | 10 10) | |
780 | ||
e075ae69 RH |
781 | (define_function_unit "k6_store" 1 0 |
782 | (and (eq_attr "cpu" "k6") | |
783 | (ior (eq_attr "type" "push") | |
784 | (eq_attr "memory" "store,both"))) | |
785 | 1 1) | |
a269a03c | 786 | |
e075ae69 RH |
787 | (define_function_unit "k6_fpu" 1 1 |
788 | (and (eq_attr "cpu" "k6") | |
22fb740d | 789 | (eq_attr "type" "fop,fop1,fmov,fcmp,fistp")) |
e075ae69 | 790 | 2 2) |
a269a03c | 791 | |
e075ae69 RH |
792 | (define_function_unit "k6_fpu" 1 1 |
793 | (and (eq_attr "cpu" "k6") | |
794 | (eq_attr "type" "fmul")) | |
795 | 2 2) | |
a269a03c | 796 | |
e075ae69 RH |
797 | ;; ??? Guess |
798 | (define_function_unit "k6_fpu" 1 1 | |
799 | (and (eq_attr "cpu" "k6") | |
800 | (eq_attr "type" "fdiv,fpspc")) | |
801 | 56 56) | |
a269a03c | 802 | |
e075ae69 RH |
803 | (define_function_unit "k6_alu" 2 0 |
804 | (and (eq_attr "cpu" "k6") | |
805 | (eq_attr "type" "imul")) | |
806 | 2 2) | |
a269a03c | 807 | |
e075ae69 RH |
808 | (define_function_unit "k6_alux" 1 0 |
809 | (and (eq_attr "cpu" "k6") | |
810 | (eq_attr "type" "imul")) | |
811 | 2 2) | |
a269a03c | 812 | |
e075ae69 RH |
813 | ;; ??? Guess |
814 | (define_function_unit "k6_alu" 2 0 | |
815 | (and (eq_attr "cpu" "k6") | |
816 | (eq_attr "type" "idiv")) | |
817 | 17 17) | |
2ae0f82c | 818 | |
e075ae69 RH |
819 | (define_function_unit "k6_alux" 1 0 |
820 | (and (eq_attr "cpu" "k6") | |
821 | (eq_attr "type" "idiv")) | |
822 | 17 17) | |
886c62d1 | 823 | \f |
309ada50 JH |
824 | ;; AMD Athlon Scheduling |
825 | ;; | |
826 | ;; The Athlon does contain three pipelined FP units, three integer units and | |
827 | ;; three address generation units. | |
828 | ;; | |
829 | ;; The predecode logic is determining boundaries of instructions in the 64 | |
830 | ;; byte cache line. So the cache line straddling problem of K6 might be issue | |
831 | ;; here as well, but it is not noted in the documentation. | |
832 | ;; | |
833 | ;; Three DirectPath instructions decoders and only one VectorPath decoder | |
834 | ;; is available. They can decode three DirectPath instructions or one VectorPath | |
835 | ;; instruction per cycle. | |
836 | ;; Decoded macro instructions are then passed to 72 entry instruction control | |
837 | ;; unit, that passes | |
838 | ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers. | |
839 | ;; | |
840 | ;; The load/store queue unit is not attached to the schedulers but | |
cc712abf | 841 | ;; communicates with all the execution units separately instead. |
309ada50 JH |
842 | |
843 | (define_attr "athlon_decode" "direct,vector" | |
0b5107cf | 844 | (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov") |
309ada50 JH |
845 | (const_string "vector") |
846 | (and (eq_attr "type" "push") | |
847 | (match_operand 1 "memory_operand" "")) | |
848 | (const_string "vector") | |
849 | (and (eq_attr "type" "fmov") | |
2b589241 JH |
850 | (and (eq_attr "memory" "load,store") |
851 | (eq_attr "mode" "XF"))) | |
309ada50 JH |
852 | (const_string "vector")] |
853 | (const_string "direct"))) | |
854 | ||
855 | (define_function_unit "athlon_vectordec" 1 0 | |
856 | (and (eq_attr "cpu" "athlon") | |
857 | (eq_attr "athlon_decode" "vector")) | |
858 | 1 1) | |
859 | ||
860 | (define_function_unit "athlon_directdec" 3 0 | |
861 | (and (eq_attr "cpu" "athlon") | |
862 | (eq_attr "athlon_decode" "direct")) | |
863 | 1 1) | |
864 | ||
865 | (define_function_unit "athlon_vectordec" 1 0 | |
866 | (and (eq_attr "cpu" "athlon") | |
867 | (eq_attr "athlon_decode" "direct")) | |
868 | 1 1 [(eq_attr "athlon_decode" "vector")]) | |
869 | ||
870 | (define_function_unit "athlon_ieu" 3 0 | |
871 | (and (eq_attr "cpu" "athlon") | |
6ef67412 | 872 | (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop")) |
309ada50 JH |
873 | 1 1) |
874 | ||
7c7ef435 JH |
875 | (define_function_unit "athlon_ieu" 3 0 |
876 | (and (eq_attr "cpu" "athlon") | |
877 | (eq_attr "type" "str")) | |
878 | 15 15) | |
879 | ||
309ada50 JH |
880 | (define_function_unit "athlon_ieu" 3 0 |
881 | (and (eq_attr "cpu" "athlon") | |
882 | (eq_attr "type" "imul")) | |
0b5107cf | 883 | 5 0) |
309ada50 JH |
884 | |
885 | (define_function_unit "athlon_ieu" 3 0 | |
886 | (and (eq_attr "cpu" "athlon") | |
887 | (eq_attr "type" "idiv")) | |
0b5107cf | 888 | 42 0) |
309ada50 JH |
889 | |
890 | (define_function_unit "athlon_muldiv" 1 0 | |
891 | (and (eq_attr "cpu" "athlon") | |
892 | (eq_attr "type" "imul")) | |
893 | 5 0) | |
894 | ||
895 | (define_function_unit "athlon_muldiv" 1 0 | |
896 | (and (eq_attr "cpu" "athlon") | |
897 | (eq_attr "type" "idiv")) | |
0b5107cf | 898 | 42 42) |
309ada50 | 899 | |
0b5107cf | 900 | (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any" |
22fb740d | 901 | (cond [(eq_attr "type" "fop,fop1,fcmp,fistp") |
309ada50 | 902 | (const_string "add") |
0b5107cf | 903 | (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov") |
309ada50 | 904 | (const_string "mul") |
0b5107cf | 905 | (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both")) |
309ada50 | 906 | (const_string "store") |
0b5107cf JH |
907 | (and (eq_attr "type" "fmov") (eq_attr "memory" "load")) |
908 | (const_string "any") | |
309ada50 JH |
909 | (and (eq_attr "type" "fmov") |
910 | (ior (match_operand:SI 1 "register_operand" "") | |
911 | (match_operand 1 "immediate_operand" ""))) | |
912 | (const_string "store") | |
913 | (eq_attr "type" "fmov") | |
0b5107cf | 914 | (const_string "muladd")] |
309ada50 JH |
915 | (const_string "none"))) |
916 | ||
0b5107cf JH |
917 | ;; We use latencies 1 for definitions. This is OK to model colisions |
918 | ;; in execution units. The real latencies are modeled in the "fp" pipeline. | |
919 | ||
920 | ;; fsin, fcos: 96-192 | |
921 | ;; fsincos: 107-211 | |
922 | ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode. | |
923 | (define_function_unit "athlon_fp" 3 0 | |
309ada50 | 924 | (and (eq_attr "cpu" "athlon") |
0b5107cf JH |
925 | (eq_attr "type" "fpspc")) |
926 | 100 1) | |
309ada50 | 927 | |
0b5107cf JH |
928 | ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode. |
929 | (define_function_unit "athlon_fp" 3 0 | |
309ada50 | 930 | (and (eq_attr "cpu" "athlon") |
0b5107cf JH |
931 | (eq_attr "type" "fdiv")) |
932 | 24 1) | |
933 | ||
934 | (define_function_unit "athlon_fp" 3 0 | |
935 | (and (eq_attr "cpu" "athlon") | |
22fb740d | 936 | (eq_attr "type" "fop,fop1,fmul,fistp")) |
309ada50 JH |
937 | 4 1) |
938 | ||
0b5107cf JH |
939 | ;; XFmode loads are slow. |
940 | ;; XFmode store is slow too (8 cycles), but we don't need to model it, because | |
941 | ;; there are no dependent instructions. | |
942 | ||
943 | (define_function_unit "athlon_fp" 3 0 | |
309ada50 JH |
944 | (and (eq_attr "cpu" "athlon") |
945 | (and (eq_attr "type" "fmov") | |
2b589241 JH |
946 | (and (eq_attr "memory" "load") |
947 | (eq_attr "mode" "XF")))) | |
0b5107cf JH |
948 | 10 1) |
949 | ||
950 | (define_function_unit "athlon_fp" 3 0 | |
951 | (and (eq_attr "cpu" "athlon") | |
952 | (eq_attr "type" "fmov,fsgn")) | |
309ada50 JH |
953 | 2 1) |
954 | ||
0b5107cf JH |
955 | ;; fcmp and ftst instructions |
956 | (define_function_unit "athlon_fp" 3 0 | |
957 | (and (eq_attr "cpu" "athlon") | |
958 | (and (eq_attr "type" "fcmp") | |
959 | (eq_attr "athlon_decode" "direct"))) | |
960 | 3 1) | |
961 | ||
962 | ;; fcmpi instructions. | |
963 | (define_function_unit "athlon_fp" 3 0 | |
964 | (and (eq_attr "cpu" "athlon") | |
965 | (and (eq_attr "type" "fcmp") | |
966 | (eq_attr "athlon_decode" "vector"))) | |
967 | 3 1) | |
968 | ||
969 | (define_function_unit "athlon_fp" 3 0 | |
970 | (and (eq_attr "cpu" "athlon") | |
971 | (eq_attr "type" "fcmov")) | |
972 | 7 1) | |
973 | ||
974 | (define_function_unit "athlon_fp_mul" 1 0 | |
975 | (and (eq_attr "cpu" "athlon") | |
976 | (eq_attr "athlon_fpunits" "mul")) | |
977 | 1 1) | |
978 | ||
979 | (define_function_unit "athlon_fp_add" 1 0 | |
980 | (and (eq_attr "cpu" "athlon") | |
981 | (eq_attr "athlon_fpunits" "add")) | |
982 | 1 1) | |
983 | ||
309ada50 JH |
984 | (define_function_unit "athlon_fp_muladd" 2 0 |
985 | (and (eq_attr "cpu" "athlon") | |
0b5107cf JH |
986 | (eq_attr "athlon_fpunits" "muladd,mul,add")) |
987 | 1 1) | |
309ada50 JH |
988 | |
989 | (define_function_unit "athlon_fp_store" 1 0 | |
990 | (and (eq_attr "cpu" "athlon") | |
0b5107cf | 991 | (eq_attr "athlon_fpunits" "store")) |
309ada50 JH |
992 | 1 1) |
993 | ||
f710504c | 994 | ;; We don't need to model the Address Generation Unit, since we don't model |
0b5107cf JH |
995 | ;; the re-order buffer yet and thus we never schedule more than three operations |
996 | ;; at time. Later we may want to experiment with MD_SCHED macros modeling the | |
997 | ;; decoders independently on the functional units. | |
998 | ||
999 | ;(define_function_unit "athlon_agu" 3 0 | |
1000 | ; (and (eq_attr "cpu" "athlon") | |
1001 | ; (and (eq_attr "memory" "!none") | |
1002 | ; (eq_attr "athlon_fpunits" "none"))) | |
1003 | ; 1 1) | |
1004 | ||
1005 | ;; Model load unit to avoid too long sequences of loads. We don't need to | |
1006 | ;; model store queue, since it is hardly going to be bottleneck. | |
1007 | ||
1008 | (define_function_unit "athlon_load" 2 0 | |
309ada50 | 1009 | (and (eq_attr "cpu" "athlon") |
0b5107cf | 1010 | (eq_attr "memory" "load,both")) |
309ada50 JH |
1011 | 1 1) |
1012 | ||
1013 | \f | |
e075ae69 | 1014 | ;; Compare instructions. |
886c62d1 | 1015 | |
e075ae69 | 1016 | ;; All compare insns have expanders that save the operands away without |
c572e5ba | 1017 | ;; actually generating RTL. The bCOND or sCOND (emitted immediately |
e075ae69 | 1018 | ;; after the cmp) will actually emit the cmpM. |
886c62d1 | 1019 | |
e075ae69 RH |
1020 | (define_expand "cmpdi" |
1021 | [(set (reg:CC 17) | |
b9b2c339 | 1022 | (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") |
9b70259d | 1023 | (match_operand:DI 1 "x86_64_general_operand" "")))] |
c572e5ba | 1024 | "" |
c572e5ba | 1025 | { |
b9b2c339 | 1026 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
e075ae69 RH |
1027 | operands[0] = force_reg (DImode, operands[0]); |
1028 | ix86_compare_op0 = operands[0]; | |
1029 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 1030 | DONE; |
0f40f9f7 | 1031 | }) |
c572e5ba | 1032 | |
e075ae69 RH |
1033 | (define_expand "cmpsi" |
1034 | [(set (reg:CC 17) | |
1035 | (compare:CC (match_operand:SI 0 "cmpsi_operand" "") | |
1036 | (match_operand:SI 1 "general_operand" "")))] | |
c572e5ba | 1037 | "" |
c572e5ba | 1038 | { |
b9b2c339 | 1039 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
e075ae69 RH |
1040 | operands[0] = force_reg (SImode, operands[0]); |
1041 | ix86_compare_op0 = operands[0]; | |
1042 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 1043 | DONE; |
0f40f9f7 | 1044 | }) |
c572e5ba | 1045 | |
e075ae69 RH |
1046 | (define_expand "cmphi" |
1047 | [(set (reg:CC 17) | |
b9b2c339 | 1048 | (compare:CC (match_operand:HI 0 "nonimmediate_operand" "") |
e075ae69 | 1049 | (match_operand:HI 1 "general_operand" "")))] |
c572e5ba | 1050 | "" |
c572e5ba | 1051 | { |
b9b2c339 | 1052 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
e075ae69 RH |
1053 | operands[0] = force_reg (HImode, operands[0]); |
1054 | ix86_compare_op0 = operands[0]; | |
1055 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 1056 | DONE; |
0f40f9f7 | 1057 | }) |
c572e5ba | 1058 | |
e075ae69 RH |
1059 | (define_expand "cmpqi" |
1060 | [(set (reg:CC 17) | |
b9b2c339 | 1061 | (compare:CC (match_operand:QI 0 "nonimmediate_operand" "") |
e075ae69 | 1062 | (match_operand:QI 1 "general_operand" "")))] |
d9f32422 | 1063 | "TARGET_QIMODE_MATH" |
c572e5ba | 1064 | { |
b9b2c339 | 1065 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
e075ae69 RH |
1066 | operands[0] = force_reg (QImode, operands[0]); |
1067 | ix86_compare_op0 = operands[0]; | |
1068 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 1069 | DONE; |
0f40f9f7 | 1070 | }) |
886c62d1 | 1071 | |
9b70259d JH |
1072 | (define_insn "cmpdi_ccno_1_rex64" |
1073 | [(set (reg 17) | |
1074 | (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr") | |
1075 | (match_operand:DI 1 "const0_operand" "n,n")))] | |
1076 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
1077 | "@ | |
0f40f9f7 ZW |
1078 | test{q}\t{%0, %0|%0, %0} |
1079 | cmp{q}\t{%1, %0|%0, %1}" | |
9b70259d JH |
1080 | [(set_attr "type" "test,icmp") |
1081 | (set_attr "length_immediate" "0,1") | |
1082 | (set_attr "mode" "DI")]) | |
1083 | ||
1084 | (define_insn "*cmpdi_minus_1_rex64" | |
1085 | [(set (reg 17) | |
1086 | (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r") | |
1087 | (match_operand:DI 1 "x86_64_general_operand" "re,mr")) | |
1088 | (const_int 0)))] | |
1b0c37d7 | 1089 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)" |
0f40f9f7 | 1090 | "cmp{q}\t{%1, %0|%0, %1}" |
9b70259d JH |
1091 | [(set_attr "type" "icmp") |
1092 | (set_attr "mode" "DI")]) | |
1093 | ||
1094 | (define_expand "cmpdi_1_rex64" | |
1095 | [(set (reg:CC 17) | |
1096 | (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") | |
1097 | (match_operand:DI 1 "general_operand" "")))] | |
1b0c37d7 | 1098 | "TARGET_64BIT" |
9b70259d JH |
1099 | "") |
1100 | ||
1101 | (define_insn "cmpdi_1_insn_rex64" | |
1102 | [(set (reg 17) | |
1103 | (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r") | |
1104 | (match_operand:DI 1 "x86_64_general_operand" "re,mr")))] | |
1105 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 1106 | "cmp{q}\t{%1, %0|%0, %1}" |
9b70259d JH |
1107 | [(set_attr "type" "icmp") |
1108 | (set_attr "mode" "DI")]) | |
1109 | ||
1110 | ||
9076b9c1 JH |
1111 | (define_insn "*cmpsi_ccno_1" |
1112 | [(set (reg 17) | |
1113 | (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr") | |
1114 | (match_operand:SI 1 "const0_operand" "n,n")))] | |
1115 | "ix86_match_ccmode (insn, CCNOmode)" | |
16189740 | 1116 | "@ |
0f40f9f7 ZW |
1117 | test{l}\t{%0, %0|%0, %0} |
1118 | cmp{l}\t{%1, %0|%0, %1}" | |
6ef67412 JH |
1119 | [(set_attr "type" "test,icmp") |
1120 | (set_attr "length_immediate" "0,1") | |
1121 | (set_attr "mode" "SI")]) | |
16189740 | 1122 | |
9076b9c1 JH |
1123 | (define_insn "*cmpsi_minus_1" |
1124 | [(set (reg 17) | |
1125 | (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r") | |
1126 | (match_operand:SI 1 "general_operand" "ri,mr")) | |
1127 | (const_int 0)))] | |
1128 | "ix86_match_ccmode (insn, CCGOCmode)" | |
0f40f9f7 | 1129 | "cmp{l}\t{%1, %0|%0, %1}" |
9076b9c1 | 1130 | [(set_attr "type" "icmp") |
6ef67412 | 1131 | (set_attr "mode" "SI")]) |
886c62d1 | 1132 | |
9076b9c1 | 1133 | (define_expand "cmpsi_1" |
e075ae69 RH |
1134 | [(set (reg:CC 17) |
1135 | (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r") | |
1136 | (match_operand:SI 1 "general_operand" "ri,mr")))] | |
9076b9c1 JH |
1137 | "" |
1138 | "") | |
1139 | ||
1140 | (define_insn "*cmpsi_1_insn" | |
1141 | [(set (reg 17) | |
1142 | (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r") | |
1143 | (match_operand:SI 1 "general_operand" "ri,mr")))] | |
1144 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
1145 | && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 1146 | "cmp{l}\t{%1, %0|%0, %1}" |
6ef67412 JH |
1147 | [(set_attr "type" "icmp") |
1148 | (set_attr "mode" "SI")]) | |
886c62d1 | 1149 | |
9076b9c1 | 1150 | (define_insn "*cmphi_ccno_1" |
16189740 RH |
1151 | [(set (reg 17) |
1152 | (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr") | |
1153 | (match_operand:HI 1 "const0_operand" "n,n")))] | |
1154 | "ix86_match_ccmode (insn, CCNOmode)" | |
e075ae69 | 1155 | "@ |
0f40f9f7 ZW |
1156 | test{w}\t{%0, %0|%0, %0} |
1157 | cmp{w}\t{%1, %0|%0, %1}" | |
6ef67412 JH |
1158 | [(set_attr "type" "test,icmp") |
1159 | (set_attr "length_immediate" "0,1") | |
1160 | (set_attr "mode" "HI")]) | |
886c62d1 | 1161 | |
9076b9c1 JH |
1162 | (define_insn "*cmphi_minus_1" |
1163 | [(set (reg 17) | |
1164 | (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r") | |
1165 | (match_operand:HI 1 "general_operand" "ri,mr")) | |
1166 | (const_int 0)))] | |
1167 | "ix86_match_ccmode (insn, CCGOCmode)" | |
0f40f9f7 | 1168 | "cmp{w}\t{%1, %0|%0, %1}" |
6ef67412 JH |
1169 | [(set_attr "type" "icmp") |
1170 | (set_attr "mode" "HI")]) | |
e075ae69 | 1171 | |
9076b9c1 JH |
1172 | (define_insn "*cmphi_1" |
1173 | [(set (reg 17) | |
1174 | (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r") | |
1175 | (match_operand:HI 1 "general_operand" "ri,mr")))] | |
1176 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
1177 | && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 1178 | "cmp{w}\t{%1, %0|%0, %1}" |
9076b9c1 JH |
1179 | [(set_attr "type" "icmp") |
1180 | (set_attr "mode" "HI")]) | |
16189740 RH |
1181 | |
1182 | (define_insn "*cmpqi_ccno_1" | |
9076b9c1 JH |
1183 | [(set (reg 17) |
1184 | (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq") | |
1185 | (match_operand:QI 1 "const0_operand" "n,n")))] | |
1186 | "ix86_match_ccmode (insn, CCNOmode)" | |
e075ae69 | 1187 | "@ |
0f40f9f7 ZW |
1188 | test{b}\t{%0, %0|%0, %0} |
1189 | cmp{b}\t{$0, %0|%0, 0}" | |
6ef67412 JH |
1190 | [(set_attr "type" "test,icmp") |
1191 | (set_attr "length_immediate" "0,1") | |
1192 | (set_attr "mode" "QI")]) | |
886c62d1 | 1193 | |
16189740 | 1194 | (define_insn "*cmpqi_1" |
9076b9c1 JH |
1195 | [(set (reg 17) |
1196 | (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q") | |
1197 | (match_operand:QI 1 "general_operand" "qi,mq")))] | |
1198 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
1199 | && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 1200 | "cmp{b}\t{%1, %0|%0, %1}" |
6ef67412 JH |
1201 | [(set_attr "type" "icmp") |
1202 | (set_attr "mode" "QI")]) | |
e075ae69 | 1203 | |
9076b9c1 JH |
1204 | (define_insn "*cmpqi_minus_1" |
1205 | [(set (reg 17) | |
d70401eb JJ |
1206 | (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q") |
1207 | (match_operand:QI 1 "general_operand" "qi,mq")) | |
9076b9c1 JH |
1208 | (const_int 0)))] |
1209 | "ix86_match_ccmode (insn, CCGOCmode)" | |
0f40f9f7 | 1210 | "cmp{b}\t{%1, %0|%0, %1}" |
9076b9c1 JH |
1211 | [(set_attr "type" "icmp") |
1212 | (set_attr "mode" "QI")]) | |
1213 | ||
e075ae69 | 1214 | (define_insn "*cmpqi_ext_1" |
9076b9c1 JH |
1215 | [(set (reg 17) |
1216 | (compare | |
d2836273 | 1217 | (match_operand:QI 0 "general_operand" "Qm") |
e075ae69 RH |
1218 | (subreg:QI |
1219 | (zero_extract:SI | |
d2836273 | 1220 | (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
1221 | (const_int 8) |
1222 | (const_int 8)) 0)))] | |
d2836273 | 1223 | "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" |
0f40f9f7 | 1224 | "cmp{b}\t{%h1, %0|%0, %h1}" |
d2836273 JH |
1225 | [(set_attr "type" "icmp") |
1226 | (set_attr "mode" "QI")]) | |
1227 | ||
1228 | (define_insn "*cmpqi_ext_1_rex64" | |
1229 | [(set (reg 17) | |
1230 | (compare | |
3522082b | 1231 | (match_operand:QI 0 "register_operand" "Q") |
d2836273 JH |
1232 | (subreg:QI |
1233 | (zero_extract:SI | |
1234 | (match_operand 1 "ext_register_operand" "Q") | |
1235 | (const_int 8) | |
1236 | (const_int 8)) 0)))] | |
1237 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 1238 | "cmp{b}\t{%h1, %0|%0, %h1}" |
6ef67412 JH |
1239 | [(set_attr "type" "icmp") |
1240 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
1241 | |
1242 | (define_insn "*cmpqi_ext_2" | |
16189740 RH |
1243 | [(set (reg 17) |
1244 | (compare | |
e075ae69 RH |
1245 | (subreg:QI |
1246 | (zero_extract:SI | |
d2836273 | 1247 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
1248 | (const_int 8) |
1249 | (const_int 8)) 0) | |
1250 | (match_operand:QI 1 "const0_operand" "n")))] | |
16189740 | 1251 | "ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 1252 | "test{b}\t%h0, %h0" |
6ef67412 JH |
1253 | [(set_attr "type" "test") |
1254 | (set_attr "length_immediate" "0") | |
1255 | (set_attr "mode" "QI")]) | |
e075ae69 | 1256 | |
9076b9c1 | 1257 | (define_expand "cmpqi_ext_3" |
e075ae69 RH |
1258 | [(set (reg:CC 17) |
1259 | (compare:CC | |
1260 | (subreg:QI | |
1261 | (zero_extract:SI | |
d2836273 | 1262 | (match_operand 0 "ext_register_operand" "") |
e075ae69 RH |
1263 | (const_int 8) |
1264 | (const_int 8)) 0) | |
d2836273 | 1265 | (match_operand:QI 1 "general_operand" "")))] |
e075ae69 | 1266 | "" |
9076b9c1 JH |
1267 | "") |
1268 | ||
1269 | (define_insn "cmpqi_ext_3_insn" | |
1270 | [(set (reg 17) | |
1271 | (compare | |
1272 | (subreg:QI | |
1273 | (zero_extract:SI | |
d2836273 | 1274 | (match_operand 0 "ext_register_operand" "Q") |
9076b9c1 JH |
1275 | (const_int 8) |
1276 | (const_int 8)) 0) | |
d2836273 JH |
1277 | (match_operand:QI 1 "general_operand" "Qmn")))] |
1278 | "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 1279 | "cmp{b}\t{%1, %h0|%h0, %1}" |
d2836273 JH |
1280 | [(set_attr "type" "icmp") |
1281 | (set_attr "mode" "QI")]) | |
1282 | ||
1283 | (define_insn "cmpqi_ext_3_insn_rex64" | |
1284 | [(set (reg 17) | |
1285 | (compare | |
1286 | (subreg:QI | |
1287 | (zero_extract:SI | |
1288 | (match_operand 0 "ext_register_operand" "Q") | |
1289 | (const_int 8) | |
1290 | (const_int 8)) 0) | |
1291 | (match_operand:QI 1 "nonmemory_operand" "Qn")))] | |
1292 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 1293 | "cmp{b}\t{%1, %h0|%h0, %1}" |
6ef67412 JH |
1294 | [(set_attr "type" "icmp") |
1295 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
1296 | |
1297 | (define_insn "*cmpqi_ext_4" | |
9076b9c1 JH |
1298 | [(set (reg 17) |
1299 | (compare | |
e075ae69 RH |
1300 | (subreg:QI |
1301 | (zero_extract:SI | |
d2836273 | 1302 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
1303 | (const_int 8) |
1304 | (const_int 8)) 0) | |
1305 | (subreg:QI | |
1306 | (zero_extract:SI | |
d2836273 | 1307 | (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
1308 | (const_int 8) |
1309 | (const_int 8)) 0)))] | |
9076b9c1 | 1310 | "ix86_match_ccmode (insn, CCmode)" |
0f40f9f7 | 1311 | "cmp{b}\t{%h1, %h0|%h0, %h1}" |
6ef67412 JH |
1312 | [(set_attr "type" "icmp") |
1313 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
1314 | |
1315 | ;; These implement float point compares. | |
1316 | ;; %%% See if we can get away with VOIDmode operands on the actual insns, | |
1317 | ;; which would allow mix and match FP modes on the compares. Which is what | |
1318 | ;; the old patterns did, but with many more of them. | |
c572e5ba | 1319 | |
e075ae69 RH |
1320 | (define_expand "cmpxf" |
1321 | [(set (reg:CC 17) | |
1322 | (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "") | |
1323 | (match_operand:XF 1 "cmp_fp_expander_operand" "")))] | |
1b0c37d7 | 1324 | "!TARGET_64BIT && TARGET_80387" |
c572e5ba | 1325 | { |
e075ae69 RH |
1326 | ix86_compare_op0 = operands[0]; |
1327 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 1328 | DONE; |
0f40f9f7 | 1329 | }) |
4fb21e90 | 1330 | |
2b589241 JH |
1331 | (define_expand "cmptf" |
1332 | [(set (reg:CC 17) | |
1333 | (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "") | |
1334 | (match_operand:TF 1 "cmp_fp_expander_operand" "")))] | |
1335 | "TARGET_80387" | |
2b589241 JH |
1336 | { |
1337 | ix86_compare_op0 = operands[0]; | |
1338 | ix86_compare_op1 = operands[1]; | |
1339 | DONE; | |
0f40f9f7 | 1340 | }) |
2b589241 | 1341 | |
e075ae69 RH |
1342 | (define_expand "cmpdf" |
1343 | [(set (reg:CC 17) | |
1344 | (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "") | |
1345 | (match_operand:DF 1 "cmp_fp_expander_operand" "")))] | |
0644b628 | 1346 | "TARGET_80387 || TARGET_SSE2" |
4fb21e90 | 1347 | { |
e075ae69 RH |
1348 | ix86_compare_op0 = operands[0]; |
1349 | ix86_compare_op1 = operands[1]; | |
4fb21e90 | 1350 | DONE; |
0f40f9f7 | 1351 | }) |
886c62d1 | 1352 | |
e075ae69 RH |
1353 | (define_expand "cmpsf" |
1354 | [(set (reg:CC 17) | |
1355 | (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "") | |
1356 | (match_operand:SF 1 "cmp_fp_expander_operand" "")))] | |
0644b628 | 1357 | "TARGET_80387 || TARGET_SSE" |
c572e5ba | 1358 | { |
e075ae69 RH |
1359 | ix86_compare_op0 = operands[0]; |
1360 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 1361 | DONE; |
0f40f9f7 | 1362 | }) |
c572e5ba | 1363 | |
e075ae69 RH |
1364 | ;; FP compares, step 1: |
1365 | ;; Set the FP condition codes. | |
1366 | ;; | |
1367 | ;; CCFPmode compare with exceptions | |
1368 | ;; CCFPUmode compare with no exceptions | |
fe4435d9 | 1369 | |
e075ae69 RH |
1370 | ;; %%% It is an unfortunate fact that ftst has no non-popping variant, |
1371 | ;; and that fp moves clobber the condition codes, and that there is | |
1372 | ;; currently no way to describe this fact to reg-stack. So there are | |
1373 | ;; no splitters yet for this. | |
c572e5ba | 1374 | |
e075ae69 RH |
1375 | ;; %%% YIKES! This scheme does not retain a strong connection between |
1376 | ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not | |
1377 | ;; work! Only allow tos/mem with tos in op 0. | |
1378 | ;; | |
1379 | ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps | |
1380 | ;; things aren't as bad as they sound... | |
886c62d1 | 1381 | |
e075ae69 RH |
1382 | (define_insn "*cmpfp_0" |
1383 | [(set (match_operand:HI 0 "register_operand" "=a") | |
1384 | (unspec:HI | |
1385 | [(compare:CCFP (match_operand 1 "register_operand" "f") | |
1386 | (match_operand 2 "const0_operand" "X"))] 9))] | |
1387 | "TARGET_80387 | |
1388 | && FLOAT_MODE_P (GET_MODE (operands[1])) | |
1389 | && GET_MODE (operands[1]) == GET_MODE (operands[2])" | |
c572e5ba | 1390 | { |
e075ae69 | 1391 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) |
0f40f9f7 | 1392 | return "ftst\;fnstsw\t%0\;fstp\t%y0"; |
e075ae69 | 1393 | else |
0f40f9f7 ZW |
1394 | return "ftst\;fnstsw\t%0"; |
1395 | } | |
6ef67412 JH |
1396 | [(set_attr "type" "multi") |
1397 | (set_attr "mode" "unknownfp")]) | |
c572e5ba | 1398 | |
e075ae69 RH |
1399 | ;; We may not use "#" to split and emit these, since the REG_DEAD notes |
1400 | ;; used to manage the reg stack popping would not be preserved. | |
886c62d1 | 1401 | |
e075ae69 RH |
1402 | (define_insn "*cmpfp_2_sf" |
1403 | [(set (reg:CCFP 18) | |
1404 | (compare:CCFP | |
1405 | (match_operand:SF 0 "register_operand" "f") | |
1406 | (match_operand:SF 1 "nonimmediate_operand" "fm")))] | |
cac58785 | 1407 | "TARGET_80387" |
e075ae69 | 1408 | "* return output_fp_compare (insn, operands, 0, 0);" |
6ef67412 JH |
1409 | [(set_attr "type" "fcmp") |
1410 | (set_attr "mode" "SF")]) | |
4fb21e90 | 1411 | |
6343a50e | 1412 | (define_insn "*cmpfp_2_sf_1" |
e075ae69 RH |
1413 | [(set (match_operand:HI 0 "register_operand" "=a") |
1414 | (unspec:HI | |
1415 | [(compare:CCFP | |
1416 | (match_operand:SF 1 "register_operand" "f") | |
1417 | (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))] | |
4fb21e90 | 1418 | "TARGET_80387" |
e075ae69 | 1419 | "* return output_fp_compare (insn, operands, 2, 0);" |
6ef67412 JH |
1420 | [(set_attr "type" "fcmp") |
1421 | (set_attr "mode" "SF")]) | |
e075ae69 RH |
1422 | |
1423 | (define_insn "*cmpfp_2_df" | |
1424 | [(set (reg:CCFP 18) | |
1425 | (compare:CCFP | |
1426 | (match_operand:DF 0 "register_operand" "f") | |
1427 | (match_operand:DF 1 "nonimmediate_operand" "fm")))] | |
926b3fae | 1428 | "TARGET_80387" |
e075ae69 | 1429 | "* return output_fp_compare (insn, operands, 0, 0);" |
6ef67412 JH |
1430 | [(set_attr "type" "fcmp") |
1431 | (set_attr "mode" "DF")]) | |
926b3fae | 1432 | |
6343a50e | 1433 | (define_insn "*cmpfp_2_df_1" |
e075ae69 RH |
1434 | [(set (match_operand:HI 0 "register_operand" "=a") |
1435 | (unspec:HI | |
1436 | [(compare:CCFP | |
1437 | (match_operand:DF 1 "register_operand" "f") | |
1438 | (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))] | |
4fb21e90 | 1439 | "TARGET_80387" |
e075ae69 | 1440 | "* return output_fp_compare (insn, operands, 2, 0);" |
6ef67412 JH |
1441 | [(set_attr "type" "multi") |
1442 | (set_attr "mode" "DF")]) | |
e075ae69 RH |
1443 | |
1444 | (define_insn "*cmpfp_2_xf" | |
1445 | [(set (reg:CCFP 18) | |
1446 | (compare:CCFP | |
1447 | (match_operand:XF 0 "register_operand" "f") | |
1448 | (match_operand:XF 1 "register_operand" "f")))] | |
1b0c37d7 | 1449 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 1450 | "* return output_fp_compare (insn, operands, 0, 0);" |
6ef67412 JH |
1451 | [(set_attr "type" "fcmp") |
1452 | (set_attr "mode" "XF")]) | |
9ec36da5 | 1453 | |
2b589241 JH |
1454 | (define_insn "*cmpfp_2_tf" |
1455 | [(set (reg:CCFP 18) | |
1456 | (compare:CCFP | |
1457 | (match_operand:TF 0 "register_operand" "f") | |
1458 | (match_operand:TF 1 "register_operand" "f")))] | |
1459 | "TARGET_80387" | |
1460 | "* return output_fp_compare (insn, operands, 0, 0);" | |
1461 | [(set_attr "type" "fcmp") | |
1462 | (set_attr "mode" "XF")]) | |
1463 | ||
6343a50e | 1464 | (define_insn "*cmpfp_2_xf_1" |
e075ae69 RH |
1465 | [(set (match_operand:HI 0 "register_operand" "=a") |
1466 | (unspec:HI | |
1467 | [(compare:CCFP | |
1468 | (match_operand:XF 1 "register_operand" "f") | |
1469 | (match_operand:XF 2 "register_operand" "f"))] 9))] | |
1b0c37d7 | 1470 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 1471 | "* return output_fp_compare (insn, operands, 2, 0);" |
6ef67412 JH |
1472 | [(set_attr "type" "multi") |
1473 | (set_attr "mode" "XF")]) | |
e075ae69 | 1474 | |
2b589241 JH |
1475 | (define_insn "*cmpfp_2_tf_1" |
1476 | [(set (match_operand:HI 0 "register_operand" "=a") | |
1477 | (unspec:HI | |
1478 | [(compare:CCFP | |
1479 | (match_operand:TF 1 "register_operand" "f") | |
1480 | (match_operand:TF 2 "register_operand" "f"))] 9))] | |
1481 | "TARGET_80387" | |
1482 | "* return output_fp_compare (insn, operands, 2, 0);" | |
1483 | [(set_attr "type" "multi") | |
1484 | (set_attr "mode" "XF")]) | |
1485 | ||
e075ae69 RH |
1486 | (define_insn "*cmpfp_2u" |
1487 | [(set (reg:CCFPU 18) | |
1488 | (compare:CCFPU | |
1489 | (match_operand 0 "register_operand" "f") | |
1490 | (match_operand 1 "register_operand" "f")))] | |
1491 | "TARGET_80387 | |
1492 | && FLOAT_MODE_P (GET_MODE (operands[0])) | |
1493 | && GET_MODE (operands[0]) == GET_MODE (operands[1])" | |
1494 | "* return output_fp_compare (insn, operands, 0, 1);" | |
6ef67412 JH |
1495 | [(set_attr "type" "fcmp") |
1496 | (set_attr "mode" "unknownfp")]) | |
4fb21e90 | 1497 | |
6343a50e | 1498 | (define_insn "*cmpfp_2u_1" |
e075ae69 RH |
1499 | [(set (match_operand:HI 0 "register_operand" "=a") |
1500 | (unspec:HI | |
1501 | [(compare:CCFPU | |
1502 | (match_operand 1 "register_operand" "f") | |
1503 | (match_operand 2 "register_operand" "f"))] 9))] | |
08a7baac | 1504 | "TARGET_80387 |
e075ae69 RH |
1505 | && FLOAT_MODE_P (GET_MODE (operands[1])) |
1506 | && GET_MODE (operands[1]) == GET_MODE (operands[2])" | |
1507 | "* return output_fp_compare (insn, operands, 2, 1);" | |
6ef67412 JH |
1508 | [(set_attr "type" "multi") |
1509 | (set_attr "mode" "unknownfp")]) | |
08a7baac | 1510 | |
e075ae69 RH |
1511 | ;; Patterns to match the SImode-in-memory ficom instructions. |
1512 | ;; | |
1513 | ;; %%% Play games with accepting gp registers, as otherwise we have to | |
1514 | ;; force them to memory during rtl generation, which is no good. We | |
1515 | ;; can get rid of this once we teach reload to do memory input reloads | |
1516 | ;; via pushes. | |
1517 | ||
6343a50e | 1518 | (define_insn "*ficom_1" |
e075ae69 RH |
1519 | [(set (reg:CCFP 18) |
1520 | (compare:CCFP | |
1521 | (match_operand 0 "register_operand" "f,f") | |
1522 | (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))] | |
1523 | "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0])) | |
1524 | && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])" | |
1525 | "#") | |
08a7baac | 1526 | |
e075ae69 RH |
1527 | ;; Split the not-really-implemented gp register case into a |
1528 | ;; push-op-pop sequence. | |
1529 | ;; | |
1530 | ;; %%% This is most efficient, but am I gonna get in trouble | |
1531 | ;; for separating cc0_setter and cc0_user? | |
2bb7a0f5 | 1532 | |
e075ae69 RH |
1533 | (define_split |
1534 | [(set (reg:CCFP 18) | |
1535 | (compare:CCFP | |
1536 | (match_operand:SF 0 "register_operand" "") | |
1537 | (float (match_operand:SI 1 "register_operand" ""))))] | |
1538 | "0 && TARGET_80387 && reload_completed" | |
1539 | [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1)) | |
1540 | (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2))) | |
1541 | (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) | |
1542 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
1543 | "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx); | |
1544 | operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);") | |
1545 | ||
1546 | ;; FP compares, step 2 | |
1547 | ;; Move the fpsw to ax. | |
1548 | ||
1549 | (define_insn "x86_fnstsw_1" | |
1550 | [(set (match_operand:HI 0 "register_operand" "=a") | |
1551 | (unspec:HI [(reg 18)] 9))] | |
2ae0f82c | 1552 | "TARGET_80387" |
0f40f9f7 | 1553 | "fnstsw\t%0" |
e075ae69 | 1554 | [(set_attr "length" "2") |
6ef67412 JH |
1555 | (set_attr "mode" "SI") |
1556 | (set_attr "i387" "1") | |
e075ae69 RH |
1557 | (set_attr "ppro_uops" "few")]) |
1558 | ||
1559 | ;; FP compares, step 3 | |
1560 | ;; Get ax into flags, general case. | |
1561 | ||
1562 | (define_insn "x86_sahf_1" | |
1563 | [(set (reg:CC 17) | |
1564 | (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))] | |
1e07edd3 | 1565 | "!TARGET_64BIT" |
e075ae69 RH |
1566 | "sahf" |
1567 | [(set_attr "length" "1") | |
0b5107cf | 1568 | (set_attr "athlon_decode" "vector") |
6ef67412 | 1569 | (set_attr "mode" "SI") |
e075ae69 RH |
1570 | (set_attr "ppro_uops" "one")]) |
1571 | ||
1572 | ;; Pentium Pro can do steps 1 through 3 in one go. | |
1573 | ||
1574 | (define_insn "*cmpfp_i" | |
1575 | [(set (reg:CCFP 17) | |
1576 | (compare:CCFP (match_operand 0 "register_operand" "f") | |
1577 | (match_operand 1 "register_operand" "f")))] | |
1578 | "TARGET_80387 && TARGET_CMOVE | |
0644b628 | 1579 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[0])) |
e075ae69 RH |
1580 | && FLOAT_MODE_P (GET_MODE (operands[0])) |
1581 | && GET_MODE (operands[0]) == GET_MODE (operands[0])" | |
1582 | "* return output_fp_compare (insn, operands, 1, 0);" | |
309ada50 | 1583 | [(set_attr "type" "fcmp") |
6ef67412 | 1584 | (set_attr "mode" "unknownfp") |
309ada50 | 1585 | (set_attr "athlon_decode" "vector")]) |
e075ae69 | 1586 | |
0644b628 JH |
1587 | (define_insn "*cmpfp_i_sse" |
1588 | [(set (reg:CCFP 17) | |
1589 | (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f") | |
1590 | (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] | |
1591 | "TARGET_80387 | |
1592 | && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) | |
1593 | && GET_MODE (operands[0]) == GET_MODE (operands[0])" | |
1594 | "* return output_fp_compare (insn, operands, 1, 0);" | |
1595 | [(set_attr "type" "fcmp,sse") | |
1596 | (set_attr "mode" "unknownfp") | |
1597 | (set_attr "athlon_decode" "vector")]) | |
1598 | ||
1599 | (define_insn "*cmpfp_i_sse_only" | |
1600 | [(set (reg:CCFP 17) | |
1601 | (compare:CCFP (match_operand 0 "register_operand" "x") | |
1602 | (match_operand 1 "nonimmediate_operand" "xm")))] | |
1603 | "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) | |
1604 | && GET_MODE (operands[0]) == GET_MODE (operands[0])" | |
1605 | "* return output_fp_compare (insn, operands, 1, 0);" | |
1606 | [(set_attr "type" "sse") | |
1607 | (set_attr "mode" "unknownfp") | |
1608 | (set_attr "athlon_decode" "vector")]) | |
1609 | ||
e075ae69 RH |
1610 | (define_insn "*cmpfp_iu" |
1611 | [(set (reg:CCFPU 17) | |
1612 | (compare:CCFPU (match_operand 0 "register_operand" "f") | |
1613 | (match_operand 1 "register_operand" "f")))] | |
1614 | "TARGET_80387 && TARGET_CMOVE | |
0644b628 | 1615 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[0])) |
e075ae69 RH |
1616 | && FLOAT_MODE_P (GET_MODE (operands[0])) |
1617 | && GET_MODE (operands[0]) == GET_MODE (operands[1])" | |
1618 | "* return output_fp_compare (insn, operands, 1, 1);" | |
309ada50 | 1619 | [(set_attr "type" "fcmp") |
6ef67412 | 1620 | (set_attr "mode" "unknownfp") |
309ada50 | 1621 | (set_attr "athlon_decode" "vector")]) |
0644b628 JH |
1622 | |
1623 | (define_insn "*cmpfp_iu_sse" | |
1624 | [(set (reg:CCFPU 17) | |
1625 | (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f") | |
1626 | (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] | |
1627 | "TARGET_80387 | |
1628 | && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) | |
1629 | && GET_MODE (operands[0]) == GET_MODE (operands[1])" | |
1630 | "* return output_fp_compare (insn, operands, 1, 1);" | |
1631 | [(set_attr "type" "fcmp,sse") | |
1632 | (set_attr "mode" "unknownfp") | |
1633 | (set_attr "athlon_decode" "vector")]) | |
1634 | ||
1635 | (define_insn "*cmpfp_iu_sse_only" | |
1636 | [(set (reg:CCFPU 17) | |
1637 | (compare:CCFPU (match_operand 0 "register_operand" "x") | |
1638 | (match_operand 1 "nonimmediate_operand" "xm")))] | |
1639 | "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) | |
1640 | && GET_MODE (operands[0]) == GET_MODE (operands[1])" | |
1641 | "* return output_fp_compare (insn, operands, 1, 1);" | |
1642 | [(set_attr "type" "sse") | |
1643 | (set_attr "mode" "unknownfp") | |
1644 | (set_attr "athlon_decode" "vector")]) | |
e075ae69 RH |
1645 | \f |
1646 | ;; Move instructions. | |
2ae0f82c | 1647 | |
e075ae69 | 1648 | ;; General case of fullword move. |
886c62d1 | 1649 | |
e075ae69 RH |
1650 | (define_expand "movsi" |
1651 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
1652 | (match_operand:SI 1 "general_operand" ""))] | |
1653 | "" | |
1654 | "ix86_expand_move (SImode, operands); DONE;") | |
08a7baac | 1655 | |
e075ae69 RH |
1656 | ;; Push/pop instructions. They are separate since autoinc/dec is not a |
1657 | ;; general_operand. | |
1658 | ;; | |
1659 | ;; %%% We don't use a post-inc memory reference because x86 is not a | |
1660 | ;; general AUTO_INC_DEC host, which impacts how it is treated in flow. | |
1661 | ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC | |
1662 | ;; targets without our curiosities, and it is just as easy to represent | |
1663 | ;; this differently. | |
886c62d1 | 1664 | |
a4414093 | 1665 | (define_insn "*pushsi2" |
e075ae69 | 1666 | [(set (match_operand:SI 0 "push_operand" "=<") |
2c5a510c | 1667 | (match_operand:SI 1 "general_no_elim_operand" "ri*m"))] |
0ec259ed | 1668 | "!TARGET_64BIT" |
0f40f9f7 | 1669 | "push{l}\t%1" |
6ef67412 JH |
1670 | [(set_attr "type" "push") |
1671 | (set_attr "mode" "SI")]) | |
4fb21e90 | 1672 | |
0ec259ed JH |
1673 | ;; For 64BIT abi we always round up to 8 bytes. |
1674 | (define_insn "*pushsi2_rex64" | |
1675 | [(set (match_operand:SI 0 "push_operand" "=X") | |
1676 | (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))] | |
1677 | "TARGET_64BIT" | |
0f40f9f7 | 1678 | "push{q}\t%q1" |
0ec259ed JH |
1679 | [(set_attr "type" "push") |
1680 | (set_attr "mode" "SI")]) | |
1681 | ||
bdeb029c JH |
1682 | (define_insn "*pushsi2_prologue" |
1683 | [(set (match_operand:SI 0 "push_operand" "=<") | |
1684 | (match_operand:SI 1 "general_no_elim_operand" "ri*m")) | |
f2042df3 | 1685 | (clobber (mem:BLK (scratch)))] |
0ec259ed | 1686 | "!TARGET_64BIT" |
0f40f9f7 | 1687 | "push{l}\t%1" |
6ef67412 JH |
1688 | [(set_attr "type" "push") |
1689 | (set_attr "mode" "SI")]) | |
bdeb029c JH |
1690 | |
1691 | (define_insn "*popsi1_epilogue" | |
1692 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m") | |
1693 | (mem:SI (reg:SI 7))) | |
1694 | (set (reg:SI 7) | |
1695 | (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 | 1696 | (clobber (mem:BLK (scratch)))] |
1e07edd3 | 1697 | "!TARGET_64BIT" |
0f40f9f7 | 1698 | "pop{l}\t%0" |
6ef67412 JH |
1699 | [(set_attr "type" "pop") |
1700 | (set_attr "mode" "SI")]) | |
bdeb029c | 1701 | |
e075ae69 RH |
1702 | (define_insn "popsi1" |
1703 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m") | |
1704 | (mem:SI (reg:SI 7))) | |
1705 | (set (reg:SI 7) | |
1706 | (plus:SI (reg:SI 7) (const_int 4)))] | |
1e07edd3 | 1707 | "!TARGET_64BIT" |
0f40f9f7 | 1708 | "pop{l}\t%0" |
6ef67412 JH |
1709 | [(set_attr "type" "pop") |
1710 | (set_attr "mode" "SI")]) | |
c572e5ba | 1711 | |
a8bac9ab | 1712 | (define_insn "*movsi_xor" |
591702de JH |
1713 | [(set (match_operand:SI 0 "register_operand" "=r") |
1714 | (match_operand:SI 1 "const0_operand" "i")) | |
e075ae69 | 1715 | (clobber (reg:CC 17))] |
591702de | 1716 | "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" |
0f40f9f7 | 1717 | "xor{l}\t{%0, %0|%0, %0}" |
591702de | 1718 | [(set_attr "type" "alu1") |
6ef67412 JH |
1719 | (set_attr "mode" "SI") |
1720 | (set_attr "length_immediate" "0")]) | |
591702de JH |
1721 | |
1722 | (define_insn "*movsi_or" | |
1723 | [(set (match_operand:SI 0 "register_operand" "=r") | |
1724 | (match_operand:SI 1 "immediate_operand" "i")) | |
1725 | (clobber (reg:CC 17))] | |
1726 | "reload_completed && GET_CODE (operands[1]) == CONST_INT | |
1727 | && INTVAL (operands[1]) == -1 | |
1728 | && (TARGET_PENTIUM || optimize_size)" | |
c572e5ba | 1729 | { |
591702de | 1730 | operands[1] = constm1_rtx; |
0f40f9f7 ZW |
1731 | return "or{l}\t{%1, %0|%0, %1}"; |
1732 | } | |
591702de | 1733 | [(set_attr "type" "alu1") |
6ef67412 JH |
1734 | (set_attr "mode" "SI") |
1735 | (set_attr "length_immediate" "1")]) | |
e075ae69 | 1736 | |
591702de | 1737 | (define_insn "*movsi_1" |
141e454b JH |
1738 | [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y") |
1739 | (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))] | |
e075ae69 | 1740 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
886c62d1 | 1741 | { |
e075ae69 | 1742 | switch (get_attr_type (insn)) |
886c62d1 | 1743 | { |
141e454b JH |
1744 | case TYPE_SSE: |
1745 | if (get_attr_mode (insn) == TImode) | |
0f40f9f7 ZW |
1746 | return "movdqa\t{%1, %0|%0, %1}"; |
1747 | return "movd\t{%1, %0|%0, %1}"; | |
141e454b | 1748 | |
915119a5 | 1749 | case TYPE_MMX: |
0f40f9f7 | 1750 | return "movd\t{%1, %0|%0, %1}"; |
915119a5 | 1751 | |
e075ae69 | 1752 | case TYPE_LEA: |
0f40f9f7 | 1753 | return "lea{l}\t{%1, %0|%0, %1}"; |
915119a5 | 1754 | |
e075ae69 RH |
1755 | default: |
1756 | if (flag_pic && SYMBOLIC_CONST (operands[1])) | |
1757 | abort(); | |
0f40f9f7 | 1758 | return "mov{l}\t{%1, %0|%0, %1}"; |
886c62d1 | 1759 | } |
0f40f9f7 | 1760 | } |
e075ae69 | 1761 | [(set (attr "type") |
141e454b | 1762 | (cond [(eq_attr "alternative" "4,5") |
915119a5 | 1763 | (const_string "mmx") |
141e454b JH |
1764 | (eq_attr "alternative" "6,7,8") |
1765 | (const_string "sse") | |
915119a5 | 1766 | (and (ne (symbol_ref "flag_pic") (const_int 0)) |
e075ae69 RH |
1767 | (match_operand:SI 1 "symbolic_operand" "")) |
1768 | (const_string "lea") | |
1769 | ] | |
6ef67412 | 1770 | (const_string "imov"))) |
141e454b JH |
1771 | (set_attr "modrm" "0,*,0,*,*,*,*,*,*") |
1772 | (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")]) | |
e075ae69 | 1773 | |
0ec259ed JH |
1774 | ;; Stores and loads of ax to arbitary constant address. |
1775 | ;; We fake an second form of instruction to force reload to load address | |
1776 | ;; into register when rax is not available | |
1777 | (define_insn "*movabssi_1_rex64" | |
1778 | [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) | |
1779 | (match_operand:SI 1 "nonmemory_operand" "a,er,i"))] | |
1780 | "TARGET_64BIT" | |
1781 | "@ | |
0f40f9f7 ZW |
1782 | movabs{l}\t{%1, %P0|%P0, %1} |
1783 | mov{l}\t{%1, %a0|%a0, %1} | |
1784 | movabs{l}\t{%1, %a0|%a0, %1}" | |
0ec259ed JH |
1785 | [(set_attr "type" "imov") |
1786 | (set_attr "modrm" "0,*,*") | |
1787 | (set_attr "length_address" "8,0,0") | |
1788 | (set_attr "length_immediate" "0,*,*") | |
1789 | (set_attr "memory" "store") | |
1790 | (set_attr "mode" "SI")]) | |
1791 | ||
1792 | (define_insn "*movabssi_2_rex64" | |
1793 | [(set (match_operand:SI 0 "register_operand" "=a,r") | |
1794 | (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] | |
1795 | "TARGET_64BIT" | |
1796 | "@ | |
0f40f9f7 ZW |
1797 | movabs{l}\t{%P1, %0|%0, %P1} |
1798 | mov{l}\t{%a1, %0|%0, %a1}" | |
0ec259ed JH |
1799 | [(set_attr "type" "imov") |
1800 | (set_attr "modrm" "0,*") | |
1801 | (set_attr "length_address" "8,0") | |
1802 | (set_attr "length_immediate" "0") | |
1803 | (set_attr "memory" "load") | |
1804 | (set_attr "mode" "SI")]) | |
1805 | ||
e075ae69 RH |
1806 | (define_insn "*swapsi" |
1807 | [(set (match_operand:SI 0 "register_operand" "+r") | |
1808 | (match_operand:SI 1 "register_operand" "+r")) | |
1809 | (set (match_dup 1) | |
1810 | (match_dup 0))] | |
2bb7a0f5 | 1811 | "" |
0f40f9f7 | 1812 | "xchg{l}\t%1, %0" |
e075ae69 RH |
1813 | [(set_attr "type" "imov") |
1814 | (set_attr "pent_pair" "np") | |
0b5107cf | 1815 | (set_attr "athlon_decode" "vector") |
6ef67412 JH |
1816 | (set_attr "mode" "SI") |
1817 | (set_attr "modrm" "0") | |
e075ae69 | 1818 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 1819 | |
e075ae69 RH |
1820 | (define_expand "movhi" |
1821 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1822 | (match_operand:HI 1 "general_operand" ""))] | |
ca097615 | 1823 | "" |
e075ae69 | 1824 | "ix86_expand_move (HImode, operands); DONE;") |
2f2a49e8 | 1825 | |
a4414093 | 1826 | (define_insn "*pushhi2" |
e075ae69 | 1827 | [(set (match_operand:HI 0 "push_operand" "=<,<") |
2c5a510c | 1828 | (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))] |
1e07edd3 | 1829 | "!TARGET_64BIT" |
e075ae69 | 1830 | "@ |
0f40f9f7 ZW |
1831 | push{w}\t{|WORD PTR }%1 |
1832 | push{w}\t%1" | |
6ef67412 JH |
1833 | [(set_attr "type" "push") |
1834 | (set_attr "mode" "HI")]) | |
e075ae69 | 1835 | |
b3298882 JH |
1836 | ;; For 64BIT abi we always round up to 8 bytes. |
1837 | (define_insn "*pushhi2_rex64" | |
1838 | [(set (match_operand:HI 0 "push_operand" "=X") | |
1839 | (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))] | |
1840 | "TARGET_64BIT" | |
0f40f9f7 | 1841 | "push{q}\t%q1" |
b3298882 JH |
1842 | [(set_attr "type" "push") |
1843 | (set_attr "mode" "QI")]) | |
1844 | ||
e075ae69 | 1845 | (define_insn "*movhi_1" |
6ef67412 JH |
1846 | [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m") |
1847 | (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))] | |
e075ae69 | 1848 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
886c62d1 | 1849 | { |
e075ae69 | 1850 | switch (get_attr_type (insn)) |
886c62d1 | 1851 | { |
e075ae69 RH |
1852 | case TYPE_IMOVX: |
1853 | /* movzwl is faster than movw on p2 due to partial word stalls, | |
1854 | though not as fast as an aligned movl. */ | |
0f40f9f7 | 1855 | return "movz{wl|x}\t{%1, %k0|%k0, %1}"; |
e075ae69 | 1856 | default: |
6ef67412 | 1857 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 1858 | return "mov{l}\t{%k1, %k0|%k0, %k1}"; |
e075ae69 | 1859 | else |
0f40f9f7 | 1860 | return "mov{w}\t{%1, %0|%0, %1}"; |
886c62d1 | 1861 | } |
0f40f9f7 | 1862 | } |
e075ae69 | 1863 | [(set (attr "type") |
6ef67412 | 1864 | (cond [(and (eq_attr "alternative" "0,1") |
0b5107cf JH |
1865 | (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") |
1866 | (const_int 0)) | |
1867 | (eq (symbol_ref "TARGET_HIMODE_MATH") | |
1868 | (const_int 0)))) | |
369e59b1 | 1869 | (const_string "imov") |
6ef67412 | 1870 | (and (eq_attr "alternative" "2,3,4") |
2247f6ed | 1871 | (match_operand:HI 1 "aligned_operand" "")) |
e075ae69 RH |
1872 | (const_string "imov") |
1873 | (and (ne (symbol_ref "TARGET_MOVX") | |
1874 | (const_int 0)) | |
6ef67412 | 1875 | (eq_attr "alternative" "0,1,3,4")) |
e075ae69 RH |
1876 | (const_string "imovx") |
1877 | ] | |
1878 | (const_string "imov"))) | |
6ef67412 | 1879 | (set (attr "mode") |
e075ae69 | 1880 | (cond [(eq_attr "type" "imovx") |
6ef67412 JH |
1881 | (const_string "SI") |
1882 | (and (eq_attr "alternative" "2,3,4") | |
369e59b1 | 1883 | (match_operand:HI 1 "aligned_operand" "")) |
6ef67412 JH |
1884 | (const_string "SI") |
1885 | (and (eq_attr "alternative" "0,1") | |
0b5107cf JH |
1886 | (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") |
1887 | (const_int 0)) | |
1888 | (eq (symbol_ref "TARGET_HIMODE_MATH") | |
1889 | (const_int 0)))) | |
6ef67412 | 1890 | (const_string "SI") |
e075ae69 | 1891 | ] |
6ef67412 JH |
1892 | (const_string "HI"))) |
1893 | (set_attr "modrm" "0,*,*,0,*,*")]) | |
e075ae69 | 1894 | |
0ec259ed JH |
1895 | ;; Stores and loads of ax to arbitary constant address. |
1896 | ;; We fake an second form of instruction to force reload to load address | |
1897 | ;; into register when rax is not available | |
1898 | (define_insn "*movabshi_1_rex64" | |
1899 | [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) | |
1900 | (match_operand:HI 1 "nonmemory_operand" "a,er,i"))] | |
1901 | "TARGET_64BIT" | |
1902 | "@ | |
0f40f9f7 ZW |
1903 | movabs{w}\t{%1, %P0|%P0, %1} |
1904 | mov{w}\t{%1, %a0|%a0, %1} | |
1905 | movabs{w}\t{%1, %a0|%a0, %1}" | |
0ec259ed JH |
1906 | [(set_attr "type" "imov") |
1907 | (set_attr "modrm" "0,*,*") | |
1908 | (set_attr "length_address" "8,0,0") | |
1909 | (set_attr "length_immediate" "0,*,*") | |
1910 | (set_attr "memory" "store") | |
1911 | (set_attr "mode" "HI")]) | |
1912 | ||
1913 | (define_insn "*movabshi_2_rex64" | |
1914 | [(set (match_operand:HI 0 "register_operand" "=a,r") | |
1915 | (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] | |
1916 | "TARGET_64BIT" | |
1917 | "@ | |
0f40f9f7 ZW |
1918 | movabs{w}\t{%P1, %0|%0, %P1} |
1919 | mov{w}\t{%a1, %0|%0, %a1}" | |
0ec259ed JH |
1920 | [(set_attr "type" "imov") |
1921 | (set_attr "modrm" "0,*") | |
1922 | (set_attr "length_address" "8,0") | |
1923 | (set_attr "length_immediate" "0") | |
1924 | (set_attr "memory" "load") | |
1925 | (set_attr "mode" "HI")]) | |
1926 | ||
e075ae69 RH |
1927 | (define_insn "*swaphi_1" |
1928 | [(set (match_operand:HI 0 "register_operand" "+r") | |
1929 | (match_operand:HI 1 "register_operand" "+r")) | |
1930 | (set (match_dup 1) | |
1931 | (match_dup 0))] | |
1932 | "TARGET_PARTIAL_REG_STALL" | |
0f40f9f7 | 1933 | "xchg{w}\t%1, %0" |
e075ae69 RH |
1934 | [(set_attr "type" "imov") |
1935 | (set_attr "pent_pair" "np") | |
6ef67412 JH |
1936 | (set_attr "mode" "HI") |
1937 | (set_attr "modrm" "0") | |
e075ae69 RH |
1938 | (set_attr "ppro_uops" "few")]) |
1939 | ||
1940 | (define_insn "*swaphi_2" | |
1941 | [(set (match_operand:HI 0 "register_operand" "+r") | |
1942 | (match_operand:HI 1 "register_operand" "+r")) | |
1943 | (set (match_dup 1) | |
1944 | (match_dup 0))] | |
1945 | "! TARGET_PARTIAL_REG_STALL" | |
0f40f9f7 | 1946 | "xchg{l}\t%k1, %k0" |
e075ae69 | 1947 | [(set_attr "type" "imov") |
e075ae69 | 1948 | (set_attr "pent_pair" "np") |
6ef67412 JH |
1949 | (set_attr "mode" "SI") |
1950 | (set_attr "modrm" "0") | |
e075ae69 | 1951 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 1952 | |
2f2a49e8 | 1953 | (define_expand "movstricthi" |
e075ae69 | 1954 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "")) |
2f2a49e8 | 1955 | (match_operand:HI 1 "general_operand" ""))] |
b9b2c339 | 1956 | "! TARGET_PARTIAL_REG_STALL || optimize_size" |
2f2a49e8 MM |
1957 | { |
1958 | /* Don't generate memory->memory moves, go through a register */ | |
e075ae69 RH |
1959 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
1960 | operands[1] = force_reg (HImode, operands[1]); | |
0f40f9f7 | 1961 | }) |
2f2a49e8 | 1962 | |
e075ae69 | 1963 | (define_insn "*movstricthi_1" |
fc524c1c | 1964 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r")) |
e075ae69 | 1965 | (match_operand:HI 1 "general_operand" "rn,m"))] |
b9b2c339 | 1966 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) |
e075ae69 | 1967 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" |
0f40f9f7 | 1968 | "mov{w}\t{%1, %0|%0, %1}" |
6ef67412 JH |
1969 | [(set_attr "type" "imov") |
1970 | (set_attr "mode" "HI")]) | |
1971 | ||
1972 | (define_insn "*movstricthi_xor" | |
208b0ab1 | 1973 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) |
6ef67412 JH |
1974 | (match_operand:HI 1 "const0_operand" "i")) |
1975 | (clobber (reg:CC 17))] | |
b9b2c339 JH |
1976 | "reload_completed |
1977 | && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)" | |
0f40f9f7 | 1978 | "xor{w}\t{%0, %0|%0, %0}" |
6ef67412 JH |
1979 | [(set_attr "type" "alu1") |
1980 | (set_attr "mode" "HI") | |
1981 | (set_attr "length_immediate" "0")]) | |
886c62d1 | 1982 | |
2f2a49e8 | 1983 | (define_expand "movqi" |
4cbfbb1b | 1984 | [(set (match_operand:QI 0 "nonimmediate_operand" "") |
2f2a49e8 MM |
1985 | (match_operand:QI 1 "general_operand" ""))] |
1986 | "" | |
e075ae69 RH |
1987 | "ix86_expand_move (QImode, operands); DONE;") |
1988 | ||
7dd4b4a3 JH |
1989 | ;; emit_push_insn when it calls move_by_pieces requires an insn to |
1990 | ;; "push a byte". But actually we use pushw, which has the effect | |
1991 | ;; of rounding the amount pushed up to a halfword. | |
1992 | ||
1993 | (define_insn "*pushqi2" | |
1994 | [(set (match_operand:QI 0 "push_operand" "=X,X") | |
1995 | (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))] | |
1996 | "!TARGET_64BIT" | |
1997 | "@ | |
0f40f9f7 ZW |
1998 | push{w}\t{|word ptr }%1 |
1999 | push{w}\t%w1" | |
7dd4b4a3 JH |
2000 | [(set_attr "type" "push") |
2001 | (set_attr "mode" "HI")]) | |
2002 | ||
b3298882 JH |
2003 | ;; For 64BIT abi we always round up to 8 bytes. |
2004 | (define_insn "*pushqi2_rex64" | |
2005 | [(set (match_operand:QI 0 "push_operand" "=X") | |
2006 | (match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))] | |
2007 | "TARGET_64BIT" | |
0f40f9f7 | 2008 | "push{q}\t%q1" |
b3298882 JH |
2009 | [(set_attr "type" "push") |
2010 | (set_attr "mode" "QI")]) | |
2011 | ||
0b5107cf JH |
2012 | ;; Situation is quite tricky about when to choose full sized (SImode) move |
2013 | ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for | |
2014 | ;; partial register dependency machines (such as AMD Athlon), where QImode | |
2015 | ;; moves issue extra dependency and for partial register stalls machines | |
2016 | ;; that don't use QImode patterns (and QImode move cause stall on the next | |
2017 | ;; instruction). | |
2018 | ;; | |
2019 | ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial | |
2020 | ;; register stall machines with, where we use QImode instructions, since | |
2021 | ;; partial register stall can be caused there. Then we use movzx. | |
e075ae69 | 2022 | (define_insn "*movqi_1" |
0b5107cf JH |
2023 | [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m") |
2024 | (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))] | |
e075ae69 | 2025 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
886c62d1 | 2026 | { |
e075ae69 | 2027 | switch (get_attr_type (insn)) |
b76c90cf | 2028 | { |
e075ae69 | 2029 | case TYPE_IMOVX: |
1a06f5fe | 2030 | if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM) |
e075ae69 | 2031 | abort (); |
0f40f9f7 | 2032 | return "movz{bl|x}\t{%1, %k0|%k0, %1}"; |
e075ae69 | 2033 | default: |
6ef67412 | 2034 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 2035 | return "mov{l}\t{%k1, %k0|%k0, %k1}"; |
b76c90cf | 2036 | else |
0f40f9f7 | 2037 | return "mov{b}\t{%1, %0|%0, %1}"; |
b76c90cf | 2038 | } |
0f40f9f7 | 2039 | } |
e075ae69 | 2040 | [(set (attr "type") |
0b5107cf JH |
2041 | (cond [(and (eq_attr "alternative" "3") |
2042 | (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") | |
2043 | (const_int 0)) | |
2044 | (eq (symbol_ref "TARGET_QIMODE_MATH") | |
2045 | (const_int 0)))) | |
2046 | (const_string "imov") | |
2047 | (eq_attr "alternative" "3,5") | |
e075ae69 RH |
2048 | (const_string "imovx") |
2049 | (and (ne (symbol_ref "TARGET_MOVX") | |
2050 | (const_int 0)) | |
0b5107cf | 2051 | (eq_attr "alternative" "2")) |
e075ae69 RH |
2052 | (const_string "imovx") |
2053 | ] | |
2054 | (const_string "imov"))) | |
6ef67412 JH |
2055 | (set (attr "mode") |
2056 | (cond [(eq_attr "alternative" "3,4,5") | |
2057 | (const_string "SI") | |
2058 | (eq_attr "alternative" "6") | |
2059 | (const_string "QI") | |
2060 | (eq_attr "type" "imovx") | |
2061 | (const_string "SI") | |
0b5107cf | 2062 | (and (eq_attr "type" "imov") |
6ef67412 | 2063 | (and (eq_attr "alternative" "0,1,2") |
0b5107cf JH |
2064 | (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY") |
2065 | (const_int 0)))) | |
6ef67412 | 2066 | (const_string "SI") |
0b5107cf JH |
2067 | ;; Avoid partial register stalls when not using QImode arithmetic |
2068 | (and (eq_attr "type" "imov") | |
6ef67412 | 2069 | (and (eq_attr "alternative" "0,1,2") |
0b5107cf JH |
2070 | (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL") |
2071 | (const_int 0)) | |
2072 | (eq (symbol_ref "TARGET_QIMODE_MATH") | |
2073 | (const_int 0))))) | |
6ef67412 JH |
2074 | (const_string "SI") |
2075 | ] | |
2076 | (const_string "QI")))]) | |
e075ae69 RH |
2077 | |
2078 | (define_expand "reload_outqi" | |
2079 | [(parallel [(match_operand:QI 0 "" "=m") | |
2080 | (match_operand:QI 1 "register_operand" "r") | |
2081 | (match_operand:QI 2 "register_operand" "=&q")])] | |
2082 | "" | |
e075ae69 RH |
2083 | { |
2084 | rtx op0, op1, op2; | |
2085 | op0 = operands[0]; op1 = operands[1]; op2 = operands[2]; | |
886c62d1 | 2086 | |
e075ae69 RH |
2087 | if (reg_overlap_mentioned_p (op2, op0)) |
2088 | abort (); | |
2089 | if (! q_regs_operand (op1, QImode)) | |
2090 | { | |
2091 | emit_insn (gen_movqi (op2, op1)); | |
2092 | op1 = op2; | |
2093 | } | |
2094 | emit_insn (gen_movqi (op0, op1)); | |
2095 | DONE; | |
0f40f9f7 | 2096 | }) |
886c62d1 | 2097 | |
e075ae69 RH |
2098 | (define_insn "*swapqi" |
2099 | [(set (match_operand:QI 0 "register_operand" "+r") | |
2100 | (match_operand:QI 1 "register_operand" "+r")) | |
2101 | (set (match_dup 1) | |
2102 | (match_dup 0))] | |
2103 | "" | |
0f40f9f7 | 2104 | "xchg{b}\t%1, %0" |
e075ae69 RH |
2105 | [(set_attr "type" "imov") |
2106 | (set_attr "pent_pair" "np") | |
6ef67412 JH |
2107 | (set_attr "mode" "QI") |
2108 | (set_attr "modrm" "0") | |
e075ae69 | 2109 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 2110 | |
2f2a49e8 | 2111 | (define_expand "movstrictqi" |
4cbfbb1b | 2112 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) |
2f2a49e8 | 2113 | (match_operand:QI 1 "general_operand" ""))] |
e075ae69 | 2114 | "! TARGET_PARTIAL_REG_STALL" |
2f2a49e8 | 2115 | { |
e03f5d43 | 2116 | /* Don't generate memory->memory moves, go through a register. */ |
e075ae69 RH |
2117 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
2118 | operands[1] = force_reg (QImode, operands[1]); | |
0f40f9f7 | 2119 | }) |
2f2a49e8 | 2120 | |
e075ae69 | 2121 | (define_insn "*movstrictqi_1" |
2ae0f82c | 2122 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) |
c0f06344 | 2123 | (match_operand:QI 1 "general_operand" "*qn,m"))] |
e075ae69 RH |
2124 | "! TARGET_PARTIAL_REG_STALL |
2125 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
0f40f9f7 | 2126 | "mov{b}\t{%1, %0|%0, %1}" |
6ef67412 JH |
2127 | [(set_attr "type" "imov") |
2128 | (set_attr "mode" "QI")]) | |
2129 | ||
2130 | (define_insn "*movstrictqi_xor" | |
5e6d6bf0 | 2131 | [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q")) |
6ef67412 JH |
2132 | (match_operand:QI 1 "const0_operand" "i")) |
2133 | (clobber (reg:CC 17))] | |
2134 | "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" | |
0f40f9f7 | 2135 | "xor{b}\t{%0, %0|%0, %0}" |
6ef67412 JH |
2136 | [(set_attr "type" "alu1") |
2137 | (set_attr "mode" "QI") | |
2138 | (set_attr "length_immediate" "0")]) | |
e075ae69 RH |
2139 | |
2140 | (define_insn "*movsi_extv_1" | |
d2836273 | 2141 | [(set (match_operand:SI 0 "register_operand" "=R") |
3522082b | 2142 | (sign_extract:SI (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
2143 | (const_int 8) |
2144 | (const_int 8)))] | |
2145 | "" | |
0f40f9f7 | 2146 | "movs{bl|x}\t{%h1, %0|%0, %h1}" |
6ef67412 JH |
2147 | [(set_attr "type" "imovx") |
2148 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
2149 | |
2150 | (define_insn "*movhi_extv_1" | |
d2836273 | 2151 | [(set (match_operand:HI 0 "register_operand" "=R") |
3522082b | 2152 | (sign_extract:HI (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
2153 | (const_int 8) |
2154 | (const_int 8)))] | |
2155 | "" | |
0f40f9f7 | 2156 | "movs{bl|x}\t{%h1, %k0|%k0, %h1}" |
6ef67412 JH |
2157 | [(set_attr "type" "imovx") |
2158 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
2159 | |
2160 | (define_insn "*movqi_extv_1" | |
0ec259ed | 2161 | [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r") |
3522082b | 2162 | (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") |
e075ae69 RH |
2163 | (const_int 8) |
2164 | (const_int 8)))] | |
0ec259ed | 2165 | "!TARGET_64BIT" |
886c62d1 | 2166 | { |
e075ae69 | 2167 | switch (get_attr_type (insn)) |
886c62d1 | 2168 | { |
e075ae69 | 2169 | case TYPE_IMOVX: |
0f40f9f7 | 2170 | return "movs{bl|x}\t{%h1, %k0|%k0, %h1}"; |
e075ae69 | 2171 | default: |
0f40f9f7 | 2172 | return "mov{b}\t{%h1, %0|%0, %h1}"; |
886c62d1 | 2173 | } |
0f40f9f7 | 2174 | } |
e075ae69 RH |
2175 | [(set (attr "type") |
2176 | (if_then_else (and (match_operand:QI 0 "register_operand" "") | |
2177 | (ior (not (match_operand:QI 0 "q_regs_operand" "")) | |
2178 | (ne (symbol_ref "TARGET_MOVX") | |
2179 | (const_int 0)))) | |
2180 | (const_string "imovx") | |
6ef67412 JH |
2181 | (const_string "imov"))) |
2182 | (set (attr "mode") | |
2183 | (if_then_else (eq_attr "type" "imovx") | |
2184 | (const_string "SI") | |
2185 | (const_string "QI")))]) | |
e075ae69 | 2186 | |
0ec259ed JH |
2187 | (define_insn "*movqi_extv_1_rex64" |
2188 | [(set (match_operand:QI 0 "register_operand" "=Q,?R") | |
3522082b | 2189 | (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") |
0ec259ed JH |
2190 | (const_int 8) |
2191 | (const_int 8)))] | |
2192 | "TARGET_64BIT" | |
0ec259ed JH |
2193 | { |
2194 | switch (get_attr_type (insn)) | |
2195 | { | |
2196 | case TYPE_IMOVX: | |
0f40f9f7 | 2197 | return "movs{bl|x}\t{%h1, %k0|%k0, %h1}"; |
0ec259ed | 2198 | default: |
0f40f9f7 | 2199 | return "mov{b}\t{%h1, %0|%0, %h1}"; |
0ec259ed | 2200 | } |
0f40f9f7 | 2201 | } |
0ec259ed JH |
2202 | [(set (attr "type") |
2203 | (if_then_else (and (match_operand:QI 0 "register_operand" "") | |
2204 | (ior (not (match_operand:QI 0 "q_regs_operand" "")) | |
2205 | (ne (symbol_ref "TARGET_MOVX") | |
2206 | (const_int 0)))) | |
2207 | (const_string "imovx") | |
2208 | (const_string "imov"))) | |
2209 | (set (attr "mode") | |
2210 | (if_then_else (eq_attr "type" "imovx") | |
2211 | (const_string "SI") | |
2212 | (const_string "QI")))]) | |
2213 | ||
2214 | ;; Stores and loads of ax to arbitary constant address. | |
2215 | ;; We fake an second form of instruction to force reload to load address | |
2216 | ;; into register when rax is not available | |
2217 | (define_insn "*movabsqi_1_rex64" | |
2218 | [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) | |
2219 | (match_operand:QI 1 "nonmemory_operand" "a,er,i"))] | |
2220 | "TARGET_64BIT" | |
2221 | "@ | |
5e2ce672 JH |
2222 | movabs{b}\t{%1, %P0|%P0, %1} |
2223 | mov{b}\t{%1, %a0|%a0, %1} | |
2224 | movabs{b}\t{%1, %a0|%a0, %1}" | |
0ec259ed JH |
2225 | [(set_attr "type" "imov") |
2226 | (set_attr "modrm" "0,*,*") | |
2227 | (set_attr "length_address" "8,0,0") | |
2228 | (set_attr "length_immediate" "0,*,*") | |
2229 | (set_attr "memory" "store") | |
2230 | (set_attr "mode" "QI")]) | |
2231 | ||
2232 | (define_insn "*movabsqi_2_rex64" | |
2233 | [(set (match_operand:QI 0 "register_operand" "=a,r") | |
2234 | (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] | |
2235 | "TARGET_64BIT" | |
2236 | "@ | |
5e2ce672 JH |
2237 | movabs{b}\t{%P1, %0|%0, %P1} |
2238 | mov{b}\t{%a1, %0|%0, %a1}" | |
0ec259ed JH |
2239 | [(set_attr "type" "imov") |
2240 | (set_attr "modrm" "0,*") | |
2241 | (set_attr "length_address" "8,0") | |
2242 | (set_attr "length_immediate" "0") | |
2243 | (set_attr "memory" "load") | |
2244 | (set_attr "mode" "QI")]) | |
2245 | ||
e075ae69 | 2246 | (define_insn "*movsi_extzv_1" |
d2836273 JH |
2247 | [(set (match_operand:SI 0 "register_operand" "=R") |
2248 | (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") | |
e075ae69 RH |
2249 | (const_int 8) |
2250 | (const_int 8)))] | |
2251 | "" | |
0f40f9f7 | 2252 | "movz{bl|x}\t{%h1, %0|%0, %h1}" |
6ef67412 JH |
2253 | [(set_attr "type" "imovx") |
2254 | (set_attr "mode" "SI")]) | |
886c62d1 | 2255 | |
d2836273 JH |
2256 | (define_insn "*movqi_extzv_2" |
2257 | [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R") | |
2258 | (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q") | |
e075ae69 RH |
2259 | (const_int 8) |
2260 | (const_int 8)) 0))] | |
d2836273 | 2261 | "!TARGET_64BIT" |
f31fce3f | 2262 | { |
e075ae69 | 2263 | switch (get_attr_type (insn)) |
f31fce3f | 2264 | { |
e075ae69 | 2265 | case TYPE_IMOVX: |
0f40f9f7 | 2266 | return "movz{bl|x}\t{%h1, %k0|%k0, %h1}"; |
e075ae69 | 2267 | default: |
0f40f9f7 | 2268 | return "mov{b}\t{%h1, %0|%0, %h1}"; |
e075ae69 | 2269 | } |
0f40f9f7 | 2270 | } |
e075ae69 RH |
2271 | [(set (attr "type") |
2272 | (if_then_else (and (match_operand:QI 0 "register_operand" "") | |
2273 | (ior (not (match_operand:QI 0 "q_regs_operand" "")) | |
2274 | (ne (symbol_ref "TARGET_MOVX") | |
2275 | (const_int 0)))) | |
2276 | (const_string "imovx") | |
6ef67412 JH |
2277 | (const_string "imov"))) |
2278 | (set (attr "mode") | |
2279 | (if_then_else (eq_attr "type" "imovx") | |
2280 | (const_string "SI") | |
2281 | (const_string "QI")))]) | |
e075ae69 | 2282 | |
d2836273 JH |
2283 | (define_insn "*movqi_extzv_2_rex64" |
2284 | [(set (match_operand:QI 0 "register_operand" "=Q,?R") | |
2285 | (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q") | |
2286 | (const_int 8) | |
2287 | (const_int 8)) 0))] | |
2288 | "TARGET_64BIT" | |
d2836273 JH |
2289 | { |
2290 | switch (get_attr_type (insn)) | |
2291 | { | |
2292 | case TYPE_IMOVX: | |
0f40f9f7 | 2293 | return "movz{bl|x}\t{%h1, %k0|%k0, %h1}"; |
d2836273 | 2294 | default: |
0f40f9f7 | 2295 | return "mov{b}\t{%h1, %0|%0, %h1}"; |
d2836273 | 2296 | } |
0f40f9f7 | 2297 | } |
d2836273 JH |
2298 | [(set (attr "type") |
2299 | (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" "")) | |
2300 | (ne (symbol_ref "TARGET_MOVX") | |
2301 | (const_int 0))) | |
2302 | (const_string "imovx") | |
2303 | (const_string "imov"))) | |
2304 | (set (attr "mode") | |
2305 | (if_then_else (eq_attr "type" "imovx") | |
2306 | (const_string "SI") | |
2307 | (const_string "QI")))]) | |
2308 | ||
7a2e09f4 | 2309 | (define_insn "movsi_insv_1" |
d2836273 | 2310 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") |
e075ae69 RH |
2311 | (const_int 8) |
2312 | (const_int 8)) | |
f47c8646 | 2313 | (match_operand:SI 1 "general_operand" "Qmn"))] |
d2836273 | 2314 | "!TARGET_64BIT" |
0f40f9f7 | 2315 | "mov{b}\t{%b1, %h0|%h0, %b1}" |
d2836273 JH |
2316 | [(set_attr "type" "imov") |
2317 | (set_attr "mode" "QI")]) | |
2318 | ||
2319 | (define_insn "*movsi_insv_1_rex64" | |
2320 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") | |
2321 | (const_int 8) | |
2322 | (const_int 8)) | |
f47c8646 | 2323 | (match_operand:SI 1 "nonmemory_operand" "Qn"))] |
d2836273 | 2324 | "TARGET_64BIT" |
0f40f9f7 | 2325 | "mov{b}\t{%b1, %h0|%h0, %b1}" |
6ef67412 JH |
2326 | [(set_attr "type" "imov") |
2327 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
2328 | |
2329 | (define_insn "*movqi_insv_2" | |
d2836273 | 2330 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") |
e075ae69 RH |
2331 | (const_int 8) |
2332 | (const_int 8)) | |
3522082b | 2333 | (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q") |
e075ae69 RH |
2334 | (const_int 8)) |
2335 | (const_int 255)))] | |
2336 | "" | |
0f40f9f7 | 2337 | "mov{b}\t{%h1, %h0|%h0, %h1}" |
6ef67412 JH |
2338 | [(set_attr "type" "imov") |
2339 | (set_attr "mode" "QI")]) | |
f31fce3f | 2340 | |
e075ae69 | 2341 | (define_expand "movdi" |
4cbfbb1b | 2342 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
e075ae69 RH |
2343 | (match_operand:DI 1 "general_operand" ""))] |
2344 | "" | |
2345 | "ix86_expand_move (DImode, operands); DONE;") | |
f31fce3f | 2346 | |
e075ae69 RH |
2347 | (define_insn "*pushdi" |
2348 | [(set (match_operand:DI 0 "push_operand" "=<") | |
2c5a510c | 2349 | (match_operand:DI 1 "general_no_elim_operand" "riF*m"))] |
1e07edd3 | 2350 | "!TARGET_64BIT" |
e075ae69 | 2351 | "#") |
f31fce3f | 2352 | |
0ec259ed JH |
2353 | (define_insn "pushdi2_rex64" |
2354 | [(set (match_operand:DI 0 "push_operand" "=<,!<") | |
2355 | (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))] | |
2356 | "TARGET_64BIT" | |
2357 | "@ | |
0f40f9f7 | 2358 | push{q}\t%1 |
0ec259ed JH |
2359 | #" |
2360 | [(set_attr "type" "push,multi") | |
2361 | (set_attr "mode" "DI")]) | |
2362 | ||
2363 | ;; Convert impossible pushes of immediate to existing instructions. | |
f5143c46 | 2364 | ;; First try to get scratch register and go through it. In case this |
0ec259ed JH |
2365 | ;; fails, push sign extended lower part first and then overwrite |
2366 | ;; upper part by 32bit move. | |
2367 | (define_peephole2 | |
2368 | [(match_scratch:DI 2 "r") | |
2369 | (set (match_operand:DI 0 "push_operand" "") | |
2370 | (match_operand:DI 1 "immediate_operand" ""))] | |
2371 | "TARGET_64BIT && !symbolic_operand (operands[1], DImode) | |
2372 | && !x86_64_immediate_operand (operands[1], DImode)" | |
2373 | [(set (match_dup 2) (match_dup 1)) | |
2374 | (set (match_dup 0) (match_dup 2))] | |
2375 | "") | |
2376 | ||
2377 | ;; We need to define this as both peepholer and splitter for case | |
2378 | ;; peephole2 pass is not run. | |
2379 | (define_peephole2 | |
2380 | [(set (match_operand:DI 0 "push_operand" "") | |
2381 | (match_operand:DI 1 "immediate_operand" ""))] | |
2382 | "TARGET_64BIT && !symbolic_operand (operands[1], DImode) | |
2383 | && !x86_64_immediate_operand (operands[1], DImode) && 1" | |
2384 | [(set (match_dup 0) (match_dup 1)) | |
2385 | (set (match_dup 2) (match_dup 3))] | |
2386 | "split_di (operands + 1, 1, operands + 2, operands + 3); | |
2387 | operands[1] = gen_lowpart (DImode, operands[2]); | |
2388 | operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, | |
2389 | GEN_INT (4))); | |
2390 | ") | |
2391 | ||
2392 | (define_split | |
2393 | [(set (match_operand:DI 0 "push_operand" "") | |
2394 | (match_operand:DI 1 "immediate_operand" ""))] | |
2395 | "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2)) | |
2396 | && !symbolic_operand (operands[1], DImode) | |
2397 | && !x86_64_immediate_operand (operands[1], DImode)" | |
2398 | [(set (match_dup 0) (match_dup 1)) | |
2399 | (set (match_dup 2) (match_dup 3))] | |
2400 | "split_di (operands + 1, 1, operands + 2, operands + 3); | |
2401 | operands[1] = gen_lowpart (DImode, operands[2]); | |
2402 | operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, | |
2403 | GEN_INT (4))); | |
2404 | ") | |
2405 | ||
2406 | (define_insn "*pushdi2_prologue_rex64" | |
2407 | [(set (match_operand:DI 0 "push_operand" "=<") | |
2408 | (match_operand:DI 1 "general_no_elim_operand" "re*m")) | |
f2042df3 | 2409 | (clobber (mem:BLK (scratch)))] |
0ec259ed | 2410 | "TARGET_64BIT" |
0f40f9f7 | 2411 | "push{q}\t%1" |
0ec259ed JH |
2412 | [(set_attr "type" "push") |
2413 | (set_attr "mode" "DI")]) | |
2414 | ||
2415 | (define_insn "*popdi1_epilogue_rex64" | |
2416 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m") | |
2417 | (mem:DI (reg:DI 7))) | |
2418 | (set (reg:DI 7) | |
2419 | (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 | 2420 | (clobber (mem:BLK (scratch)))] |
0ec259ed | 2421 | "TARGET_64BIT" |
0f40f9f7 | 2422 | "pop{q}\t%0" |
0ec259ed JH |
2423 | [(set_attr "type" "pop") |
2424 | (set_attr "mode" "DI")]) | |
2425 | ||
2426 | (define_insn "popdi1" | |
2427 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m") | |
2428 | (mem:DI (reg:DI 7))) | |
2429 | (set (reg:DI 7) | |
2430 | (plus:DI (reg:DI 7) (const_int 8)))] | |
2431 | "TARGET_64BIT" | |
0f40f9f7 | 2432 | "pop{q}\t%0" |
0ec259ed JH |
2433 | [(set_attr "type" "pop") |
2434 | (set_attr "mode" "DI")]) | |
2435 | ||
2436 | (define_insn "*movdi_xor_rex64" | |
2437 | [(set (match_operand:DI 0 "register_operand" "=r") | |
2438 | (match_operand:DI 1 "const0_operand" "i")) | |
2439 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
2440 | "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size) |
2441 | && reload_completed" | |
0f40f9f7 | 2442 | "xor{l}\t{%k0, %k0|%k0, %k0}" |
0ec259ed JH |
2443 | [(set_attr "type" "alu1") |
2444 | (set_attr "mode" "SI") | |
2445 | (set_attr "length_immediate" "0")]) | |
2446 | ||
2447 | (define_insn "*movdi_or_rex64" | |
2448 | [(set (match_operand:DI 0 "register_operand" "=r") | |
2449 | (match_operand:DI 1 "const_int_operand" "i")) | |
2450 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
2451 | "TARGET_64BIT && (TARGET_PENTIUM || optimize_size) |
2452 | && reload_completed | |
2453 | && GET_CODE (operands[1]) == CONST_INT | |
2454 | && INTVAL (operands[1]) == -1" | |
0ec259ed JH |
2455 | { |
2456 | operands[1] = constm1_rtx; | |
0f40f9f7 ZW |
2457 | return "or{q}\t{%1, %0|%0, %1}"; |
2458 | } | |
0ec259ed JH |
2459 | [(set_attr "type" "alu1") |
2460 | (set_attr "mode" "DI") | |
2461 | (set_attr "length_immediate" "1")]) | |
2462 | ||
e075ae69 | 2463 | (define_insn "*movdi_2" |
141e454b JH |
2464 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y") |
2465 | (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))] | |
1e07edd3 JH |
2466 | "!TARGET_64BIT |
2467 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
915119a5 BS |
2468 | "@ |
2469 | # | |
2470 | # | |
0f40f9f7 ZW |
2471 | movq\t{%1, %0|%0, %1} |
2472 | movq\t{%1, %0|%0, %1} | |
2473 | movq\t{%1, %0|%0, %1} | |
2474 | movdqa\t{%1, %0|%0, %1} | |
2475 | movq\t{%1, %0|%0, %1}" | |
141e454b JH |
2476 | [(set_attr "type" "*,*,mmx,mmx,sse,sse,sse") |
2477 | (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")]) | |
dc0f0eb8 | 2478 | |
e075ae69 RH |
2479 | (define_split |
2480 | [(set (match_operand:DI 0 "push_operand" "") | |
2481 | (match_operand:DI 1 "general_operand" ""))] | |
6c12e488 JH |
2482 | "!TARGET_64BIT && reload_completed |
2483 | && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))" | |
2450a057 | 2484 | [(const_int 0)] |
26e5b205 | 2485 | "ix86_split_long_move (operands); DONE;") |
f31fce3f | 2486 | |
e075ae69 | 2487 | ;; %%% This multiword shite has got to go. |
e075ae69 | 2488 | (define_split |
c76aab11 | 2489 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
e075ae69 | 2490 | (match_operand:DI 1 "general_operand" ""))] |
6c12e488 JH |
2491 | "!TARGET_64BIT && reload_completed |
2492 | && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0])) | |
2493 | && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))" | |
26e5b205 JH |
2494 | [(const_int 0)] |
2495 | "ix86_split_long_move (operands); DONE;") | |
0ec259ed JH |
2496 | |
2497 | (define_insn "*movdi_1_rex64" | |
141e454b JH |
2498 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y") |
2499 | (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))] | |
1b0c37d7 ZW |
2500 | "TARGET_64BIT |
2501 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
0ec259ed JH |
2502 | { |
2503 | switch (get_attr_type (insn)) | |
2504 | { | |
2505 | case TYPE_SSE: | |
141e454b JH |
2506 | if (register_operand (operands[0], DImode) |
2507 | && register_operand (operands[1], DImode)) | |
0f40f9f7 | 2508 | return "movdqa\t{%1, %0|%0, %1}"; |
141e454b | 2509 | /* FALLTHRU */ |
0ec259ed | 2510 | case TYPE_MMX: |
0f40f9f7 | 2511 | return "movq\t{%1, %0|%0, %1}"; |
0ec259ed | 2512 | case TYPE_MULTI: |
0f40f9f7 | 2513 | return "#"; |
0ec259ed | 2514 | case TYPE_LEA: |
0f40f9f7 | 2515 | return "lea{q}\t{%a1, %0|%0, %a1}"; |
0ec259ed JH |
2516 | default: |
2517 | if (flag_pic && SYMBOLIC_CONST (operands[1])) | |
2518 | abort (); | |
2519 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 2520 | return "mov{l}\t{%k1, %k0|%k0, %k1}"; |
0ec259ed | 2521 | else if (which_alternative == 2) |
0f40f9f7 | 2522 | return "movabs{q}\t{%1, %0|%0, %1}"; |
0ec259ed | 2523 | else |
0f40f9f7 | 2524 | return "mov{q}\t{%1, %0|%0, %1}"; |
0ec259ed | 2525 | } |
0f40f9f7 | 2526 | } |
0ec259ed JH |
2527 | [(set (attr "type") |
2528 | (cond [(eq_attr "alternative" "5,6") | |
2529 | (const_string "mmx") | |
2530 | (eq_attr "alternative" "7,8") | |
2531 | (const_string "sse") | |
2532 | (eq_attr "alternative" "4") | |
2533 | (const_string "multi") | |
2534 | (and (ne (symbol_ref "flag_pic") (const_int 0)) | |
2535 | (match_operand:DI 1 "symbolic_operand" "")) | |
2536 | (const_string "lea") | |
2537 | ] | |
2538 | (const_string "imov"))) | |
141e454b JH |
2539 | (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*") |
2540 | (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*") | |
2541 | (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")]) | |
0ec259ed JH |
2542 | |
2543 | ;; Stores and loads of ax to arbitary constant address. | |
2544 | ;; We fake an second form of instruction to force reload to load address | |
2545 | ;; into register when rax is not available | |
2546 | (define_insn "*movabsdi_1_rex64" | |
2547 | [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) | |
2548 | (match_operand:DI 1 "nonmemory_operand" "a,er,i"))] | |
2549 | "TARGET_64BIT" | |
2550 | "@ | |
0f40f9f7 ZW |
2551 | movabs{q}\t{%1, %P0|%P0, %1} |
2552 | mov{q}\t{%1, %a0|%a0, %1} | |
2553 | movabs{q}\t{%1, %a0|%a0, %1}" | |
0ec259ed JH |
2554 | [(set_attr "type" "imov") |
2555 | (set_attr "modrm" "0,*,*") | |
2556 | (set_attr "length_address" "8,0,0") | |
2557 | (set_attr "length_immediate" "0,*,*") | |
2558 | (set_attr "memory" "store") | |
2559 | (set_attr "mode" "DI")]) | |
2560 | ||
2561 | (define_insn "*movabsdi_2_rex64" | |
2562 | [(set (match_operand:DI 0 "register_operand" "=a,r") | |
2563 | (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] | |
2564 | "TARGET_64BIT" | |
2565 | "@ | |
0f40f9f7 ZW |
2566 | movabs{q}\t{%P1, %0|%0, %P1} |
2567 | mov{q}\t{%a1, %0|%0, %a1}" | |
0ec259ed JH |
2568 | [(set_attr "type" "imov") |
2569 | (set_attr "modrm" "0,*") | |
2570 | (set_attr "length_address" "8,0") | |
2571 | (set_attr "length_immediate" "0") | |
2572 | (set_attr "memory" "load") | |
2573 | (set_attr "mode" "DI")]) | |
2574 | ||
2575 | ;; Convert impossible stores of immediate to existing instructions. | |
f5143c46 | 2576 | ;; First try to get scratch register and go through it. In case this |
0ec259ed JH |
2577 | ;; fails, move by 32bit parts. |
2578 | (define_peephole2 | |
2579 | [(match_scratch:DI 2 "r") | |
2580 | (set (match_operand:DI 0 "memory_operand" "") | |
2581 | (match_operand:DI 1 "immediate_operand" ""))] | |
2582 | "TARGET_64BIT && !symbolic_operand (operands[1], DImode) | |
2583 | && !x86_64_immediate_operand (operands[1], DImode)" | |
2584 | [(set (match_dup 2) (match_dup 1)) | |
2585 | (set (match_dup 0) (match_dup 2))] | |
2586 | "") | |
2587 | ||
2588 | ;; We need to define this as both peepholer and splitter for case | |
2589 | ;; peephole2 pass is not run. | |
2590 | (define_peephole2 | |
2591 | [(set (match_operand:DI 0 "memory_operand" "") | |
2592 | (match_operand:DI 1 "immediate_operand" ""))] | |
2593 | "TARGET_64BIT && !symbolic_operand (operands[1], DImode) | |
2594 | && !x86_64_immediate_operand (operands[1], DImode) && 1" | |
2595 | [(set (match_dup 2) (match_dup 3)) | |
2596 | (set (match_dup 4) (match_dup 5))] | |
2597 | "split_di (operands, 2, operands + 2, operands + 4);") | |
2598 | ||
2599 | (define_split | |
2600 | [(set (match_operand:DI 0 "memory_operand" "") | |
2601 | (match_operand:DI 1 "immediate_operand" ""))] | |
2602 | "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2)) | |
2603 | && !symbolic_operand (operands[1], DImode) | |
2604 | && !x86_64_immediate_operand (operands[1], DImode)" | |
2605 | [(set (match_dup 2) (match_dup 3)) | |
2606 | (set (match_dup 4) (match_dup 5))] | |
2607 | "split_di (operands, 2, operands + 2, operands + 4);") | |
2608 | ||
2609 | (define_insn "*swapdi_rex64" | |
2610 | [(set (match_operand:DI 0 "register_operand" "+r") | |
2611 | (match_operand:DI 1 "register_operand" "+r")) | |
2612 | (set (match_dup 1) | |
2613 | (match_dup 0))] | |
2614 | "TARGET_64BIT" | |
0f40f9f7 | 2615 | "xchg{q}\t%1, %0" |
0ec259ed JH |
2616 | [(set_attr "type" "imov") |
2617 | (set_attr "pent_pair" "np") | |
2618 | (set_attr "athlon_decode" "vector") | |
2619 | (set_attr "mode" "DI") | |
2620 | (set_attr "modrm" "0") | |
2621 | (set_attr "ppro_uops" "few")]) | |
2622 | ||
e075ae69 | 2623 | |
0be5d99f | 2624 | (define_expand "movsf" |
4cbfbb1b | 2625 | [(set (match_operand:SF 0 "nonimmediate_operand" "") |
0be5d99f MM |
2626 | (match_operand:SF 1 "general_operand" ""))] |
2627 | "" | |
e075ae69 RH |
2628 | "ix86_expand_move (SFmode, operands); DONE;") |
2629 | ||
2630 | (define_insn "*pushsf" | |
446988df | 2631 | [(set (match_operand:SF 0 "push_operand" "=<,<,<") |
c6e95f34 | 2632 | (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))] |
0ec259ed | 2633 | "!TARGET_64BIT" |
0be5d99f | 2634 | { |
e075ae69 | 2635 | switch (which_alternative) |
0be5d99f | 2636 | { |
e075ae69 RH |
2637 | case 0: |
2638 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2639 | operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx); | |
2640 | operands[2] = stack_pointer_rtx; | |
2641 | operands[3] = GEN_INT (4); | |
2642 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2643 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
e075ae69 | 2644 | else |
0f40f9f7 | 2645 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
0bb6c81b | 2646 | |
e075ae69 | 2647 | case 1: |
0f40f9f7 | 2648 | return "push{l}\t%1"; |
446988df | 2649 | case 2: |
0f40f9f7 | 2650 | return "#"; |
e075ae69 RH |
2651 | |
2652 | default: | |
2653 | abort (); | |
0bb6c81b | 2654 | } |
0f40f9f7 | 2655 | } |
446988df JH |
2656 | [(set_attr "type" "multi,push,multi") |
2657 | (set_attr "mode" "SF,SI,SF")]) | |
0be5d99f | 2658 | |
0ec259ed JH |
2659 | (define_insn "*pushsf_rex64" |
2660 | [(set (match_operand:SF 0 "push_operand" "=X,X,X") | |
2661 | (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))] | |
2662 | "TARGET_64BIT" | |
0ec259ed JH |
2663 | { |
2664 | switch (which_alternative) | |
2665 | { | |
2666 | case 0: | |
2667 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2668 | operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx); | |
2669 | operands[2] = stack_pointer_rtx; | |
2670 | operands[3] = GEN_INT (8); | |
2671 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2672 | return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 2673 | else |
0f40f9f7 | 2674 | return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
0ec259ed JH |
2675 | |
2676 | case 1: | |
0f40f9f7 | 2677 | return "push{q}\t%q1"; |
0ec259ed JH |
2678 | |
2679 | case 2: | |
0f40f9f7 | 2680 | return "#"; |
0ec259ed JH |
2681 | |
2682 | default: | |
2683 | abort (); | |
2684 | } | |
0f40f9f7 | 2685 | } |
0ec259ed JH |
2686 | [(set_attr "type" "multi,push,multi") |
2687 | (set_attr "mode" "SF,DI,SF")]) | |
2688 | ||
d7a29404 JH |
2689 | (define_split |
2690 | [(set (match_operand:SF 0 "push_operand" "") | |
2691 | (match_operand:SF 1 "memory_operand" ""))] | |
2692 | "reload_completed | |
2693 | && GET_CODE (operands[1]) == MEM | |
2694 | && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF | |
2695 | && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))" | |
2696 | [(set (match_dup 0) | |
2697 | (match_dup 1))] | |
2698 | "operands[1] = get_pool_constant (XEXP (operands[1], 0));") | |
2699 | ||
2700 | ||
e075ae69 RH |
2701 | ;; %%% Kill this when call knows how to work this out. |
2702 | (define_split | |
2703 | [(set (match_operand:SF 0 "push_operand" "") | |
2704 | (match_operand:SF 1 "register_operand" ""))] | |
0ec259ed | 2705 | "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))" |
e075ae69 RH |
2706 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) |
2707 | (set (mem:SF (reg:SI 7)) (match_dup 1))]) | |
2708 | ||
0ec259ed JH |
2709 | (define_split |
2710 | [(set (match_operand:SF 0 "push_operand" "") | |
2711 | (match_operand:SF 1 "register_operand" ""))] | |
2712 | "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))" | |
2713 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) | |
2714 | (set (mem:SF (reg:DI 7)) (match_dup 1))]) | |
2715 | ||
e075ae69 | 2716 | (define_insn "*movsf_1" |
2b04e52b JH |
2717 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m") |
2718 | (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))] | |
d7a29404 JH |
2719 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
2720 | && (reload_in_progress || reload_completed | |
3987b9db | 2721 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
d7a29404 JH |
2722 | || GET_CODE (operands[1]) != CONST_DOUBLE |
2723 | || memory_operand (operands[0], SFmode))" | |
886c62d1 | 2724 | { |
e075ae69 | 2725 | switch (which_alternative) |
886c62d1 | 2726 | { |
e075ae69 | 2727 | case 0: |
0c174a68 AB |
2728 | if (REG_P (operands[1]) |
2729 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2730 | return "fstp\t%y0"; |
e075ae69 | 2731 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2732 | return "fld%z1\t%y1"; |
886c62d1 | 2733 | else |
0f40f9f7 | 2734 | return "fst\t%y0"; |
886c62d1 | 2735 | |
e075ae69 RH |
2736 | case 1: |
2737 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2738 | return "fstp%z0\t%y0"; |
886c62d1 | 2739 | else |
0f40f9f7 | 2740 | return "fst%z0\t%y0"; |
886c62d1 | 2741 | |
e075ae69 RH |
2742 | case 2: |
2743 | switch (standard_80387_constant_p (operands[1])) | |
2744 | { | |
2745 | case 1: | |
0f40f9f7 | 2746 | return "fldz"; |
e075ae69 | 2747 | case 2: |
0f40f9f7 | 2748 | return "fld1"; |
e075ae69 RH |
2749 | } |
2750 | abort(); | |
886c62d1 | 2751 | |
e075ae69 RH |
2752 | case 3: |
2753 | case 4: | |
0f40f9f7 | 2754 | return "mov{l}\t{%1, %0|%0, %1}"; |
446988df | 2755 | case 5: |
0f40f9f7 | 2756 | return "pxor\t%0, %0"; |
446988df | 2757 | case 6: |
2b04e52b | 2758 | if (TARGET_PARTIAL_REG_DEPENDENCY) |
0f40f9f7 | 2759 | return "movaps\t{%1, %0|%0, %1}"; |
2b04e52b | 2760 | else |
0f40f9f7 | 2761 | return "movss\t{%1, %0|%0, %1}"; |
2b04e52b JH |
2762 | case 7: |
2763 | case 8: | |
0f40f9f7 | 2764 | return "movss\t{%1, %0|%0, %1}"; |
886c62d1 | 2765 | |
e075ae69 RH |
2766 | default: |
2767 | abort(); | |
2768 | } | |
0f40f9f7 | 2769 | } |
2b04e52b JH |
2770 | [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse") |
2771 | (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")]) | |
d7a29404 | 2772 | |
a4414093 | 2773 | (define_insn "*swapsf" |
e075ae69 RH |
2774 | [(set (match_operand:SF 0 "register_operand" "+f") |
2775 | (match_operand:SF 1 "register_operand" "+f")) | |
0be5d99f MM |
2776 | (set (match_dup 1) |
2777 | (match_dup 0))] | |
965f5423 | 2778 | "reload_completed || !TARGET_SSE" |
0be5d99f MM |
2779 | { |
2780 | if (STACK_TOP_P (operands[0])) | |
0f40f9f7 | 2781 | return "fxch\t%1"; |
0be5d99f | 2782 | else |
0f40f9f7 ZW |
2783 | return "fxch\t%0"; |
2784 | } | |
6ef67412 JH |
2785 | [(set_attr "type" "fxch") |
2786 | (set_attr "mode" "SF")]) | |
0be5d99f | 2787 | |
e075ae69 | 2788 | (define_expand "movdf" |
4cbfbb1b | 2789 | [(set (match_operand:DF 0 "nonimmediate_operand" "") |
e075ae69 RH |
2790 | (match_operand:DF 1 "general_operand" ""))] |
2791 | "" | |
2792 | "ix86_expand_move (DFmode, operands); DONE;") | |
55953cea | 2793 | |
8fcaaa80 JH |
2794 | ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size. |
2795 | ;; Size of pushdf using integer insturctions is 2+2*memory operand size | |
2796 | ;; On the average, pushdf using integers can be still shorter. Allow this | |
2797 | ;; pattern for optimize_size too. | |
2798 | ||
0b5107cf | 2799 | (define_insn "*pushdf_nointeger" |
446988df | 2800 | [(set (match_operand:DF 0 "push_operand" "=<,<,<,<") |
c6e95f34 | 2801 | (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))] |
0ec259ed | 2802 | "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES" |
0b5107cf JH |
2803 | { |
2804 | switch (which_alternative) | |
2805 | { | |
2806 | case 0: | |
2807 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2808 | operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx); | |
2809 | operands[2] = stack_pointer_rtx; | |
2810 | operands[3] = GEN_INT (8); | |
2811 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2812 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0b5107cf | 2813 | else |
0f40f9f7 | 2814 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
0b5107cf JH |
2815 | |
2816 | case 1: | |
2817 | case 2: | |
446988df | 2818 | case 3: |
0f40f9f7 | 2819 | return "#"; |
0b5107cf JH |
2820 | |
2821 | default: | |
2822 | abort (); | |
2823 | } | |
0f40f9f7 | 2824 | } |
6ef67412 | 2825 | [(set_attr "type" "multi") |
446988df | 2826 | (set_attr "mode" "DF,SI,SI,DF")]) |
0b5107cf JH |
2827 | |
2828 | (define_insn "*pushdf_integer" | |
446988df JH |
2829 | [(set (match_operand:DF 0 "push_operand" "=<,<,<") |
2830 | (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))] | |
0ec259ed | 2831 | "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES" |
f31fce3f | 2832 | { |
e075ae69 | 2833 | switch (which_alternative) |
f31fce3f | 2834 | { |
e075ae69 RH |
2835 | case 0: |
2836 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2837 | operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx); | |
2838 | operands[2] = stack_pointer_rtx; | |
2839 | operands[3] = GEN_INT (8); | |
0ec259ed JH |
2840 | if (TARGET_64BIT) |
2841 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2842 | return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 2843 | else |
0f40f9f7 | 2844 | return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
f31fce3f | 2845 | else |
0ec259ed | 2846 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) |
0f40f9f7 | 2847 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 2848 | else |
0f40f9f7 | 2849 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
0ec259ed | 2850 | |
dc0f0eb8 | 2851 | |
e075ae69 | 2852 | case 1: |
446988df | 2853 | case 2: |
0f40f9f7 | 2854 | return "#"; |
dc0f0eb8 | 2855 | |
e075ae69 RH |
2856 | default: |
2857 | abort (); | |
2858 | } | |
0f40f9f7 | 2859 | } |
6ef67412 | 2860 | [(set_attr "type" "multi") |
446988df | 2861 | (set_attr "mode" "DF,SI,DF")]) |
f31fce3f | 2862 | |
e075ae69 | 2863 | ;; %%% Kill this when call knows how to work this out. |
f72b27a5 JH |
2864 | (define_split |
2865 | [(set (match_operand:DF 0 "push_operand" "") | |
e075ae69 | 2866 | (match_operand:DF 1 "register_operand" ""))] |
0ec259ed | 2867 | "!TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))" |
e075ae69 RH |
2868 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) |
2869 | (set (mem:DF (reg:SI 7)) (match_dup 1))] | |
f72b27a5 | 2870 | "") |
f31fce3f | 2871 | |
0ec259ed JH |
2872 | (define_split |
2873 | [(set (match_operand:DF 0 "push_operand" "") | |
2874 | (match_operand:DF 1 "register_operand" ""))] | |
2875 | "TARGET_64BIT && reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))" | |
2876 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) | |
2877 | (set (mem:DF (reg:DI 7)) (match_dup 1))] | |
2878 | "") | |
2879 | ||
e075ae69 RH |
2880 | (define_split |
2881 | [(set (match_operand:DF 0 "push_operand" "") | |
0be5d99f | 2882 | (match_operand:DF 1 "general_operand" ""))] |
e075ae69 | 2883 | "reload_completed" |
2450a057 | 2884 | [(const_int 0)] |
26e5b205 | 2885 | "ix86_split_long_move (operands); DONE;") |
0be5d99f | 2886 | |
8fcaaa80 JH |
2887 | ;; Moving is usually shorter when only FP registers are used. This separate |
2888 | ;; movdf pattern avoids the use of integer registers for FP operations | |
2889 | ;; when optimizing for size. | |
2890 | ||
2891 | (define_insn "*movdf_nointeger" | |
2b04e52b JH |
2892 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m") |
2893 | (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))] | |
8fcaaa80 | 2894 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
0b5107cf | 2895 | && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES) |
d7a29404 | 2896 | && (reload_in_progress || reload_completed |
3987b9db | 2897 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
d7a29404 JH |
2898 | || GET_CODE (operands[1]) != CONST_DOUBLE |
2899 | || memory_operand (operands[0], DFmode))" | |
8fcaaa80 JH |
2900 | { |
2901 | switch (which_alternative) | |
2902 | { | |
2903 | case 0: | |
2904 | if (REG_P (operands[1]) | |
2905 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2906 | return "fstp\t%y0"; |
8fcaaa80 | 2907 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2908 | return "fld%z1\t%y1"; |
8fcaaa80 | 2909 | else |
0f40f9f7 | 2910 | return "fst\t%y0"; |
8fcaaa80 JH |
2911 | |
2912 | case 1: | |
2913 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2914 | return "fstp%z0\t%y0"; |
8fcaaa80 | 2915 | else |
0f40f9f7 | 2916 | return "fst%z0\t%y0"; |
8fcaaa80 JH |
2917 | |
2918 | case 2: | |
2919 | switch (standard_80387_constant_p (operands[1])) | |
2920 | { | |
2921 | case 1: | |
0f40f9f7 | 2922 | return "fldz"; |
8fcaaa80 | 2923 | case 2: |
0f40f9f7 | 2924 | return "fld1"; |
8fcaaa80 JH |
2925 | } |
2926 | abort(); | |
2927 | ||
2928 | case 3: | |
2929 | case 4: | |
0f40f9f7 | 2930 | return "#"; |
446988df | 2931 | case 5: |
0f40f9f7 | 2932 | return "pxor\t%0, %0"; |
446988df | 2933 | case 6: |
2b04e52b | 2934 | if (TARGET_PARTIAL_REG_DEPENDENCY) |
0f40f9f7 | 2935 | return "movapd\t{%1, %0|%0, %1}"; |
2b04e52b | 2936 | else |
0f40f9f7 | 2937 | return "movsd\t{%1, %0|%0, %1}"; |
2b04e52b JH |
2938 | case 7: |
2939 | case 8: | |
0f40f9f7 | 2940 | return "movsd\t{%1, %0|%0, %1}"; |
8fcaaa80 JH |
2941 | |
2942 | default: | |
2943 | abort(); | |
2944 | } | |
0f40f9f7 | 2945 | } |
2b04e52b JH |
2946 | [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse") |
2947 | (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")]) | |
8fcaaa80 JH |
2948 | |
2949 | (define_insn "*movdf_integer" | |
2b04e52b JH |
2950 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m") |
2951 | (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))] | |
8fcaaa80 | 2952 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
0b5107cf | 2953 | && !optimize_size && TARGET_INTEGER_DFMODE_MOVES |
d7a29404 | 2954 | && (reload_in_progress || reload_completed |
3987b9db | 2955 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
d7a29404 JH |
2956 | || GET_CODE (operands[1]) != CONST_DOUBLE |
2957 | || memory_operand (operands[0], DFmode))" | |
886c62d1 | 2958 | { |
e075ae69 | 2959 | switch (which_alternative) |
886c62d1 | 2960 | { |
e075ae69 | 2961 | case 0: |
0c174a68 AB |
2962 | if (REG_P (operands[1]) |
2963 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2964 | return "fstp\t%y0"; |
e075ae69 | 2965 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2966 | return "fld%z1\t%y1"; |
886c62d1 | 2967 | else |
0f40f9f7 | 2968 | return "fst\t%y0"; |
886c62d1 | 2969 | |
e075ae69 RH |
2970 | case 1: |
2971 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2972 | return "fstp%z0\t%y0"; |
886c62d1 | 2973 | else |
0f40f9f7 | 2974 | return "fst%z0\t%y0"; |
886c62d1 | 2975 | |
e075ae69 RH |
2976 | case 2: |
2977 | switch (standard_80387_constant_p (operands[1])) | |
2978 | { | |
2979 | case 1: | |
0f40f9f7 | 2980 | return "fldz"; |
e075ae69 | 2981 | case 2: |
0f40f9f7 | 2982 | return "fld1"; |
e075ae69 RH |
2983 | } |
2984 | abort(); | |
886c62d1 | 2985 | |
e075ae69 RH |
2986 | case 3: |
2987 | case 4: | |
0f40f9f7 | 2988 | return "#"; |
886c62d1 | 2989 | |
446988df | 2990 | case 5: |
0f40f9f7 | 2991 | return "pxor\t%0, %0"; |
446988df | 2992 | case 6: |
2b04e52b | 2993 | if (TARGET_PARTIAL_REG_DEPENDENCY) |
0f40f9f7 | 2994 | return "movapd\t{%1, %0|%0, %1}"; |
2b04e52b | 2995 | else |
0f40f9f7 | 2996 | return "movsd\t{%1, %0|%0, %1}"; |
2b04e52b JH |
2997 | case 7: |
2998 | case 8: | |
0f40f9f7 | 2999 | return "movsd\t{%1, %0|%0, %1}"; |
446988df | 3000 | |
e075ae69 RH |
3001 | default: |
3002 | abort(); | |
3003 | } | |
0f40f9f7 | 3004 | } |
2b04e52b JH |
3005 | [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse") |
3006 | (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")]) | |
2ae0f82c | 3007 | |
e075ae69 RH |
3008 | (define_split |
3009 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
3010 | (match_operand:DF 1 "general_operand" ""))] | |
3011 | "reload_completed | |
3012 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
446988df | 3013 | && ! (ANY_FP_REG_P (operands[0]) || |
e075ae69 | 3014 | (GET_CODE (operands[0]) == SUBREG |
446988df JH |
3015 | && ANY_FP_REG_P (SUBREG_REG (operands[0])))) |
3016 | && ! (ANY_FP_REG_P (operands[1]) || | |
e075ae69 | 3017 | (GET_CODE (operands[1]) == SUBREG |
446988df | 3018 | && ANY_FP_REG_P (SUBREG_REG (operands[1]))))" |
26e5b205 JH |
3019 | [(const_int 0)] |
3020 | "ix86_split_long_move (operands); DONE;") | |
886c62d1 | 3021 | |
a4414093 | 3022 | (define_insn "*swapdf" |
e075ae69 RH |
3023 | [(set (match_operand:DF 0 "register_operand" "+f") |
3024 | (match_operand:DF 1 "register_operand" "+f")) | |
0be5d99f MM |
3025 | (set (match_dup 1) |
3026 | (match_dup 0))] | |
446988df | 3027 | "reload_completed || !TARGET_SSE2" |
0be5d99f MM |
3028 | { |
3029 | if (STACK_TOP_P (operands[0])) | |
0f40f9f7 | 3030 | return "fxch\t%1"; |
0be5d99f | 3031 | else |
0f40f9f7 ZW |
3032 | return "fxch\t%0"; |
3033 | } | |
6ef67412 JH |
3034 | [(set_attr "type" "fxch") |
3035 | (set_attr "mode" "DF")]) | |
e075ae69 RH |
3036 | |
3037 | (define_expand "movxf" | |
4cbfbb1b | 3038 | [(set (match_operand:XF 0 "nonimmediate_operand" "") |
e075ae69 | 3039 | (match_operand:XF 1 "general_operand" ""))] |
1e07edd3 | 3040 | "!TARGET_64BIT" |
e075ae69 | 3041 | "ix86_expand_move (XFmode, operands); DONE;") |
0be5d99f | 3042 | |
2b589241 JH |
3043 | (define_expand "movtf" |
3044 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
3045 | (match_operand:TF 1 "general_operand" ""))] | |
3046 | "" | |
3047 | "ix86_expand_move (TFmode, operands); DONE;") | |
3048 | ||
8fcaaa80 JH |
3049 | ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size. |
3050 | ;; Size of pushdf using integer insturctions is 3+3*memory operand size | |
3051 | ;; Pushing using integer instructions is longer except for constants | |
3052 | ;; and direct memory references. | |
3053 | ;; (assuming that any given constant is pushed only once, but this ought to be | |
3054 | ;; handled elsewhere). | |
3055 | ||
3056 | (define_insn "*pushxf_nointeger" | |
1e07edd3 | 3057 | [(set (match_operand:XF 0 "push_operand" "=X,X,X") |
2c5a510c | 3058 | (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))] |
1b0c37d7 | 3059 | "!TARGET_64BIT && optimize_size" |
8fcaaa80 JH |
3060 | { |
3061 | switch (which_alternative) | |
3062 | { | |
3063 | case 0: | |
3064 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
3065 | operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); | |
3066 | operands[2] = stack_pointer_rtx; | |
3067 | operands[3] = GEN_INT (12); | |
3068 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3069 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
8fcaaa80 | 3070 | else |
0f40f9f7 | 3071 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
8fcaaa80 JH |
3072 | |
3073 | case 1: | |
3074 | case 2: | |
0f40f9f7 | 3075 | return "#"; |
8fcaaa80 JH |
3076 | |
3077 | default: | |
3078 | abort (); | |
3079 | } | |
0f40f9f7 | 3080 | } |
6ef67412 JH |
3081 | [(set_attr "type" "multi") |
3082 | (set_attr "mode" "XF,SI,SI")]) | |
8fcaaa80 | 3083 | |
2b589241 JH |
3084 | (define_insn "*pushtf_nointeger" |
3085 | [(set (match_operand:TF 0 "push_operand" "=<,<,<") | |
3086 | (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))] | |
3087 | "optimize_size" | |
2b589241 JH |
3088 | { |
3089 | switch (which_alternative) | |
3090 | { | |
3091 | case 0: | |
3092 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
3093 | operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); | |
3094 | operands[2] = stack_pointer_rtx; | |
3095 | operands[3] = GEN_INT (16); | |
3096 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3097 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
2b589241 | 3098 | else |
0f40f9f7 | 3099 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
2b589241 JH |
3100 | |
3101 | case 1: | |
3102 | case 2: | |
0f40f9f7 | 3103 | return "#"; |
2b589241 JH |
3104 | |
3105 | default: | |
3106 | abort (); | |
3107 | } | |
0f40f9f7 | 3108 | } |
2b589241 JH |
3109 | [(set_attr "type" "multi") |
3110 | (set_attr "mode" "XF,SI,SI")]) | |
3111 | ||
8fcaaa80 | 3112 | (define_insn "*pushxf_integer" |
2450a057 | 3113 | [(set (match_operand:XF 0 "push_operand" "=<,<") |
1e07edd3 | 3114 | (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))] |
1b0c37d7 | 3115 | "!TARGET_64BIT && !optimize_size" |
f31fce3f | 3116 | { |
8fcaaa80 JH |
3117 | switch (which_alternative) |
3118 | { | |
3119 | case 0: | |
3120 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
3121 | operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); | |
3122 | operands[2] = stack_pointer_rtx; | |
3123 | operands[3] = GEN_INT (12); | |
3124 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3125 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
8fcaaa80 | 3126 | else |
0f40f9f7 | 3127 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
8fcaaa80 JH |
3128 | |
3129 | case 1: | |
0f40f9f7 | 3130 | return "#"; |
8fcaaa80 JH |
3131 | |
3132 | default: | |
3133 | abort (); | |
3134 | } | |
0f40f9f7 | 3135 | } |
6ef67412 JH |
3136 | [(set_attr "type" "multi") |
3137 | (set_attr "mode" "XF,SI")]) | |
f31fce3f | 3138 | |
2b589241 JH |
3139 | (define_insn "*pushtf_integer" |
3140 | [(set (match_operand:TF 0 "push_operand" "=<,<") | |
3141 | (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))] | |
3142 | "!optimize_size" | |
2b589241 JH |
3143 | { |
3144 | switch (which_alternative) | |
3145 | { | |
3146 | case 0: | |
3147 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
3148 | operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); | |
3149 | operands[2] = stack_pointer_rtx; | |
3150 | operands[3] = GEN_INT (16); | |
0ec259ed JH |
3151 | if (TARGET_64BIT) |
3152 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3153 | return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 3154 | else |
0f40f9f7 | 3155 | return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
2b589241 | 3156 | else |
0ec259ed | 3157 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) |
0f40f9f7 | 3158 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 3159 | else |
0f40f9f7 | 3160 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
2b589241 JH |
3161 | |
3162 | case 1: | |
0f40f9f7 | 3163 | return "#"; |
2b589241 JH |
3164 | |
3165 | default: | |
3166 | abort (); | |
3167 | } | |
0f40f9f7 | 3168 | } |
2b589241 JH |
3169 | [(set_attr "type" "multi") |
3170 | (set_attr "mode" "XF,SI")]) | |
3171 | ||
2450a057 | 3172 | (define_split |
2b589241 JH |
3173 | [(set (match_operand 0 "push_operand" "") |
3174 | (match_operand 1 "general_operand" ""))] | |
2450a057 | 3175 | "reload_completed |
2b589241 JH |
3176 | && (GET_MODE (operands[0]) == XFmode |
3177 | || GET_MODE (operands[0]) == TFmode | |
3178 | || GET_MODE (operands[0]) == DFmode) | |
446988df | 3179 | && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))" |
2450a057 | 3180 | [(const_int 0)] |
26e5b205 | 3181 | "ix86_split_long_move (operands); DONE;") |
2450a057 | 3182 | |
f72b27a5 JH |
3183 | (define_split |
3184 | [(set (match_operand:XF 0 "push_operand" "") | |
e075ae69 | 3185 | (match_operand:XF 1 "register_operand" ""))] |
0ec259ed | 3186 | "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))" |
e075ae69 RH |
3187 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) |
3188 | (set (mem:XF (reg:SI 7)) (match_dup 1))]) | |
f31fce3f | 3189 | |
2b589241 JH |
3190 | (define_split |
3191 | [(set (match_operand:TF 0 "push_operand" "") | |
3192 | (match_operand:TF 1 "register_operand" ""))] | |
0ec259ed | 3193 | "!TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))" |
2b589241 JH |
3194 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) |
3195 | (set (mem:TF (reg:SI 7)) (match_dup 1))]) | |
3196 | ||
0ec259ed JH |
3197 | (define_split |
3198 | [(set (match_operand:TF 0 "push_operand" "") | |
3199 | (match_operand:TF 1 "register_operand" ""))] | |
3200 | "TARGET_64BIT && ANY_FP_REGNO_P (REGNO (operands[1]))" | |
3201 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) | |
3202 | (set (mem:TF (reg:DI 7)) (match_dup 1))]) | |
3203 | ||
8fcaaa80 JH |
3204 | ;; Do not use integer registers when optimizing for size |
3205 | (define_insn "*movxf_nointeger" | |
3206 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o") | |
3207 | (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))] | |
1b0c37d7 | 3208 | "!TARGET_64BIT |
d7a29404 | 3209 | && optimize_size |
1b0c37d7 | 3210 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
d7a29404 JH |
3211 | && (reload_in_progress || reload_completed |
3212 | || GET_CODE (operands[1]) != CONST_DOUBLE | |
3213 | || memory_operand (operands[0], XFmode))" | |
0be5d99f | 3214 | { |
8fcaaa80 JH |
3215 | switch (which_alternative) |
3216 | { | |
3217 | case 0: | |
3218 | if (REG_P (operands[1]) | |
3219 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3220 | return "fstp\t%y0"; |
8fcaaa80 | 3221 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 3222 | return "fld%z1\t%y1"; |
8fcaaa80 | 3223 | else |
0f40f9f7 | 3224 | return "fst\t%y0"; |
0be5d99f | 3225 | |
8fcaaa80 JH |
3226 | case 1: |
3227 | /* There is no non-popping store to memory for XFmode. So if | |
3228 | we need one, follow the store with a load. */ | |
3229 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3230 | return "fstp%z0\t%y0\;fld%z0\t%y0"; |
8fcaaa80 | 3231 | else |
0f40f9f7 | 3232 | return "fstp%z0\t%y0"; |
8fcaaa80 JH |
3233 | |
3234 | case 2: | |
3235 | switch (standard_80387_constant_p (operands[1])) | |
3236 | { | |
3237 | case 1: | |
0f40f9f7 | 3238 | return "fldz"; |
8fcaaa80 | 3239 | case 2: |
0f40f9f7 | 3240 | return "fld1"; |
8fcaaa80 JH |
3241 | } |
3242 | break; | |
3243 | ||
3244 | case 3: case 4: | |
0f40f9f7 | 3245 | return "#"; |
8fcaaa80 JH |
3246 | } |
3247 | abort(); | |
0f40f9f7 | 3248 | } |
6ef67412 JH |
3249 | [(set_attr "type" "fmov,fmov,fmov,multi,multi") |
3250 | (set_attr "mode" "XF,XF,XF,SI,SI")]) | |
8fcaaa80 | 3251 | |
2b589241 JH |
3252 | (define_insn "*movtf_nointeger" |
3253 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o") | |
3254 | (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))] | |
3255 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
3256 | && optimize_size | |
3257 | && (reload_in_progress || reload_completed | |
3258 | || GET_CODE (operands[1]) != CONST_DOUBLE | |
3987b9db | 3259 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
2b589241 | 3260 | || memory_operand (operands[0], TFmode))" |
2b589241 JH |
3261 | { |
3262 | switch (which_alternative) | |
3263 | { | |
3264 | case 0: | |
3265 | if (REG_P (operands[1]) | |
3266 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3267 | return "fstp\t%y0"; |
2b589241 | 3268 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 3269 | return "fld%z1\t%y1"; |
2b589241 | 3270 | else |
0f40f9f7 | 3271 | return "fst\t%y0"; |
2b589241 JH |
3272 | |
3273 | case 1: | |
3274 | /* There is no non-popping store to memory for XFmode. So if | |
3275 | we need one, follow the store with a load. */ | |
3276 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3277 | return "fstp%z0\t%y0\;fld%z0\t%y0"; |
2b589241 | 3278 | else |
0f40f9f7 | 3279 | return "fstp%z0\t%y0"; |
2b589241 JH |
3280 | |
3281 | case 2: | |
3282 | switch (standard_80387_constant_p (operands[1])) | |
3283 | { | |
3284 | case 1: | |
0f40f9f7 | 3285 | return "fldz"; |
2b589241 | 3286 | case 2: |
0f40f9f7 | 3287 | return "fld1"; |
2b589241 JH |
3288 | } |
3289 | break; | |
3290 | ||
3291 | case 3: case 4: | |
0f40f9f7 | 3292 | return "#"; |
2b589241 JH |
3293 | } |
3294 | abort(); | |
0f40f9f7 | 3295 | } |
2b589241 JH |
3296 | [(set_attr "type" "fmov,fmov,fmov,multi,multi") |
3297 | (set_attr "mode" "XF,XF,XF,SI,SI")]) | |
3298 | ||
8fcaaa80 JH |
3299 | (define_insn "*movxf_integer" |
3300 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o") | |
3301 | (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))] | |
1b0c37d7 | 3302 | "!TARGET_64BIT |
d7a29404 | 3303 | && !optimize_size |
1b0c37d7 | 3304 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
d7a29404 JH |
3305 | && (reload_in_progress || reload_completed |
3306 | || GET_CODE (operands[1]) != CONST_DOUBLE | |
3307 | || memory_operand (operands[0], XFmode))" | |
4fb21e90 | 3308 | { |
e075ae69 | 3309 | switch (which_alternative) |
4fb21e90 | 3310 | { |
e075ae69 | 3311 | case 0: |
0c174a68 AB |
3312 | if (REG_P (operands[1]) |
3313 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3314 | return "fstp\t%y0"; |
e075ae69 | 3315 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 3316 | return "fld%z1\t%y1"; |
4fb21e90 | 3317 | else |
0f40f9f7 | 3318 | return "fst\t%y0"; |
4fb21e90 | 3319 | |
e075ae69 RH |
3320 | case 1: |
3321 | /* There is no non-popping store to memory for XFmode. So if | |
3322 | we need one, follow the store with a load. */ | |
3323 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3324 | return "fstp%z0\t%y0\;fld%z0\t%y0"; |
e075ae69 | 3325 | else |
0f40f9f7 | 3326 | return "fstp%z0\t%y0"; |
2f17722a | 3327 | |
e075ae69 RH |
3328 | case 2: |
3329 | switch (standard_80387_constant_p (operands[1])) | |
3330 | { | |
3331 | case 1: | |
0f40f9f7 | 3332 | return "fldz"; |
e075ae69 | 3333 | case 2: |
0f40f9f7 | 3334 | return "fld1"; |
e075ae69 RH |
3335 | } |
3336 | break; | |
467403ca RH |
3337 | |
3338 | case 3: case 4: | |
0f40f9f7 | 3339 | return "#"; |
4fb21e90 | 3340 | } |
e075ae69 | 3341 | abort(); |
0f40f9f7 | 3342 | } |
6ef67412 JH |
3343 | [(set_attr "type" "fmov,fmov,fmov,multi,multi") |
3344 | (set_attr "mode" "XF,XF,XF,SI,SI")]) | |
4fb21e90 | 3345 | |
2b589241 JH |
3346 | (define_insn "*movtf_integer" |
3347 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o") | |
3348 | (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))] | |
3349 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
3350 | && !optimize_size | |
3351 | && (reload_in_progress || reload_completed | |
3352 | || GET_CODE (operands[1]) != CONST_DOUBLE | |
3987b9db | 3353 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
2b589241 | 3354 | || memory_operand (operands[0], TFmode))" |
2b589241 JH |
3355 | { |
3356 | switch (which_alternative) | |
3357 | { | |
3358 | case 0: | |
3359 | if (REG_P (operands[1]) | |
3360 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3361 | return "fstp\t%y0"; |
2b589241 | 3362 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 3363 | return "fld%z1\t%y1"; |
2b589241 | 3364 | else |
0f40f9f7 | 3365 | return "fst\t%y0"; |
2b589241 JH |
3366 | |
3367 | case 1: | |
3368 | /* There is no non-popping store to memory for XFmode. So if | |
3369 | we need one, follow the store with a load. */ | |
3370 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3371 | return "fstp%z0\t%y0\;fld%z0\t%y0"; |
2b589241 | 3372 | else |
0f40f9f7 | 3373 | return "fstp%z0\t%y0"; |
2b589241 JH |
3374 | |
3375 | case 2: | |
3376 | switch (standard_80387_constant_p (operands[1])) | |
3377 | { | |
3378 | case 1: | |
0f40f9f7 | 3379 | return "fldz"; |
2b589241 | 3380 | case 2: |
0f40f9f7 | 3381 | return "fld1"; |
2b589241 JH |
3382 | } |
3383 | break; | |
3384 | ||
3385 | case 3: case 4: | |
0f40f9f7 | 3386 | return "#"; |
2b589241 JH |
3387 | } |
3388 | abort(); | |
0f40f9f7 | 3389 | } |
2b589241 JH |
3390 | [(set_attr "type" "fmov,fmov,fmov,multi,multi") |
3391 | (set_attr "mode" "XF,XF,XF,SI,SI")]) | |
3392 | ||
467403ca | 3393 | (define_split |
2b589241 JH |
3394 | [(set (match_operand 0 "nonimmediate_operand" "") |
3395 | (match_operand 1 "general_operand" ""))] | |
2450a057 | 3396 | "reload_completed |
8fcaaa80 | 3397 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
2b589241 | 3398 | && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode) |
446988df | 3399 | && ! (ANY_FP_REG_P (operands[0]) || |
8fcaaa80 | 3400 | (GET_CODE (operands[0]) == SUBREG |
446988df JH |
3401 | && ANY_FP_REG_P (SUBREG_REG (operands[0])))) |
3402 | && ! (ANY_FP_REG_P (operands[1]) || | |
8fcaaa80 | 3403 | (GET_CODE (operands[1]) == SUBREG |
446988df | 3404 | && ANY_FP_REG_P (SUBREG_REG (operands[1]))))" |
26e5b205 JH |
3405 | [(const_int 0)] |
3406 | "ix86_split_long_move (operands); DONE;") | |
467403ca | 3407 | |
d7a29404 | 3408 | (define_split |
2b589241 JH |
3409 | [(set (match_operand 0 "register_operand" "") |
3410 | (match_operand 1 "memory_operand" ""))] | |
d7a29404 JH |
3411 | "reload_completed |
3412 | && GET_CODE (operands[1]) == MEM | |
2b04e52b JH |
3413 | && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode |
3414 | || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode) | |
d7a29404 JH |
3415 | && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF |
3416 | && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)) | |
2b04e52b JH |
3417 | && (!(SSE_REG_P (operands[0]) || |
3418 | (GET_CODE (operands[0]) == SUBREG | |
3419 | && SSE_REG_P (SUBREG_REG (operands[0])))) | |
3420 | || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0)))) | |
3421 | && (!(FP_REG_P (operands[0]) || | |
3422 | (GET_CODE (operands[0]) == SUBREG | |
3423 | && FP_REG_P (SUBREG_REG (operands[0])))) | |
3424 | || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))" | |
d7a29404 JH |
3425 | [(set (match_dup 0) |
3426 | (match_dup 1))] | |
3427 | "operands[1] = get_pool_constant (XEXP (operands[1], 0));") | |
3428 | ||
e075ae69 RH |
3429 | (define_insn "swapxf" |
3430 | [(set (match_operand:XF 0 "register_operand" "+f") | |
3431 | (match_operand:XF 1 "register_operand" "+f")) | |
0be5d99f MM |
3432 | (set (match_dup 1) |
3433 | (match_dup 0))] | |
3434 | "" | |
0be5d99f MM |
3435 | { |
3436 | if (STACK_TOP_P (operands[0])) | |
0f40f9f7 | 3437 | return "fxch\t%1"; |
0be5d99f | 3438 | else |
0f40f9f7 ZW |
3439 | return "fxch\t%0"; |
3440 | } | |
0b5107cf | 3441 | [(set_attr "type" "fxch") |
6ef67412 | 3442 | (set_attr "mode" "XF")]) |
2b589241 JH |
3443 | |
3444 | (define_insn "swaptf" | |
3445 | [(set (match_operand:TF 0 "register_operand" "+f") | |
3446 | (match_operand:TF 1 "register_operand" "+f")) | |
3447 | (set (match_dup 1) | |
3448 | (match_dup 0))] | |
3449 | "" | |
2b589241 JH |
3450 | { |
3451 | if (STACK_TOP_P (operands[0])) | |
0f40f9f7 | 3452 | return "fxch\t%1"; |
2b589241 | 3453 | else |
0f40f9f7 ZW |
3454 | return "fxch\t%0"; |
3455 | } | |
2b589241 JH |
3456 | [(set_attr "type" "fxch") |
3457 | (set_attr "mode" "XF")]) | |
886c62d1 | 3458 | \f |
e075ae69 | 3459 | ;; Zero extension instructions |
886c62d1 | 3460 | |
8f7661f2 JH |
3461 | (define_expand "zero_extendhisi2" |
3462 | [(set (match_operand:SI 0 "register_operand" "") | |
3463 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
d626200a | 3464 | "" |
e075ae69 | 3465 | { |
8f7661f2 | 3466 | if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) |
2ae0f82c | 3467 | { |
8f7661f2 JH |
3468 | operands[1] = force_reg (HImode, operands[1]); |
3469 | emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1])); | |
3470 | DONE; | |
2ae0f82c | 3471 | } |
0f40f9f7 | 3472 | }) |
886c62d1 | 3473 | |
8f7661f2 JH |
3474 | (define_insn "zero_extendhisi2_and" |
3475 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3476 | (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) | |
e075ae69 | 3477 | (clobber (reg:CC 17))] |
8f7661f2 JH |
3478 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" |
3479 | "#" | |
6ef67412 JH |
3480 | [(set_attr "type" "alu1") |
3481 | (set_attr "mode" "SI")]) | |
2ae0f82c SC |
3482 | |
3483 | (define_split | |
3484 | [(set (match_operand:SI 0 "register_operand" "") | |
8f7661f2 | 3485 | (zero_extend:SI (match_operand:HI 1 "register_operand" ""))) |
e075ae69 | 3486 | (clobber (reg:CC 17))] |
8f7661f2 JH |
3487 | "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" |
3488 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535))) | |
e075ae69 | 3489 | (clobber (reg:CC 17))])] |
d626200a JL |
3490 | "") |
3491 | ||
8f7661f2 JH |
3492 | (define_insn "*zero_extendhisi2_movzwl" |
3493 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3494 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] | |
3495 | "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" | |
0f40f9f7 | 3496 | "movz{wl|x}\t{%1, %0|%0, %1}" |
6ef67412 JH |
3497 | [(set_attr "type" "imovx") |
3498 | (set_attr "mode" "SI")]) | |
8f7661f2 JH |
3499 | |
3500 | (define_expand "zero_extendqihi2" | |
3501 | [(parallel | |
3502 | [(set (match_operand:HI 0 "register_operand" "") | |
3503 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) | |
3504 | (clobber (reg:CC 17))])] | |
e075ae69 | 3505 | "" |
8f7661f2 JH |
3506 | "") |
3507 | ||
3508 | (define_insn "*zero_extendqihi2_and" | |
3509 | [(set (match_operand:HI 0 "register_operand" "=r,?&q") | |
3510 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) | |
3511 | (clobber (reg:CC 17))] | |
3512 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" | |
3513 | "#" | |
6ef67412 JH |
3514 | [(set_attr "type" "alu1") |
3515 | (set_attr "mode" "HI")]) | |
8f7661f2 JH |
3516 | |
3517 | (define_insn "*zero_extendqihi2_movzbw_and" | |
3518 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
3519 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) | |
3520 | (clobber (reg:CC 17))] | |
3521 | "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" | |
3522 | "#" | |
6ef67412 JH |
3523 | [(set_attr "type" "imovx,alu1") |
3524 | (set_attr "mode" "HI")]) | |
886c62d1 | 3525 | |
8f7661f2 JH |
3526 | (define_insn "*zero_extendqihi2_movzbw" |
3527 | [(set (match_operand:HI 0 "register_operand" "=r") | |
3528 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))] | |
1c27d4b2 | 3529 | "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed" |
0f40f9f7 | 3530 | "movz{bw|x}\t{%1, %0|%0, %1}" |
6ef67412 JH |
3531 | [(set_attr "type" "imovx") |
3532 | (set_attr "mode" "HI")]) | |
8f7661f2 JH |
3533 | |
3534 | ;; For the movzbw case strip only the clobber | |
2ae0f82c SC |
3535 | (define_split |
3536 | [(set (match_operand:HI 0 "register_operand" "") | |
e075ae69 RH |
3537 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) |
3538 | (clobber (reg:CC 17))] | |
8f7661f2 JH |
3539 | "reload_completed |
3540 | && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) | |
1a06f5fe | 3541 | && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" |
8f7661f2 JH |
3542 | [(set (match_operand:HI 0 "register_operand" "") |
3543 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]) | |
2ae0f82c | 3544 | |
8f7661f2 JH |
3545 | ;; When source and destination does not overlap, clear destination |
3546 | ;; first and then do the movb | |
2ae0f82c SC |
3547 | (define_split |
3548 | [(set (match_operand:HI 0 "register_operand" "") | |
8f7661f2 | 3549 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) |
e075ae69 RH |
3550 | (clobber (reg:CC 17))] |
3551 | "reload_completed | |
1a06f5fe | 3552 | && ANY_QI_REG_P (operands[0]) |
8f7661f2 JH |
3553 | && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) |
3554 | && !reg_overlap_mentioned_p (operands[0], operands[1])" | |
3555 | [(set (match_dup 0) (const_int 0)) | |
3556 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
3557 | "operands[2] = gen_lowpart (QImode, operands[0]);") | |
2ae0f82c | 3558 | |
8f7661f2 | 3559 | ;; Rest is handled by single and. |
2ae0f82c SC |
3560 | (define_split |
3561 | [(set (match_operand:HI 0 "register_operand" "") | |
e075ae69 RH |
3562 | (zero_extend:HI (match_operand:QI 1 "register_operand" ""))) |
3563 | (clobber (reg:CC 17))] | |
3564 | "reload_completed | |
8f7661f2 JH |
3565 | && true_regnum (operands[0]) == true_regnum (operands[1])" |
3566 | [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255))) | |
e075ae69 | 3567 | (clobber (reg:CC 17))])] |
d626200a JL |
3568 | "") |
3569 | ||
8f7661f2 JH |
3570 | (define_expand "zero_extendqisi2" |
3571 | [(parallel | |
3572 | [(set (match_operand:SI 0 "register_operand" "") | |
3573 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) | |
3574 | (clobber (reg:CC 17))])] | |
e075ae69 | 3575 | "" |
8f7661f2 JH |
3576 | "") |
3577 | ||
3578 | (define_insn "*zero_extendqisi2_and" | |
3579 | [(set (match_operand:SI 0 "register_operand" "=r,?&q") | |
3580 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) | |
3581 | (clobber (reg:CC 17))] | |
3582 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" | |
3583 | "#" | |
6ef67412 JH |
3584 | [(set_attr "type" "alu1") |
3585 | (set_attr "mode" "SI")]) | |
8f7661f2 JH |
3586 | |
3587 | (define_insn "*zero_extendqisi2_movzbw_and" | |
3588 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
3589 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) | |
3590 | (clobber (reg:CC 17))] | |
3591 | "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" | |
3592 | "#" | |
6ef67412 JH |
3593 | [(set_attr "type" "imovx,alu1") |
3594 | (set_attr "mode" "SI")]) | |
2ae0f82c | 3595 | |
8f7661f2 JH |
3596 | (define_insn "*zero_extendqisi2_movzbw" |
3597 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3598 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] | |
3599 | "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed" | |
0f40f9f7 | 3600 | "movz{bl|x}\t{%1, %0|%0, %1}" |
6ef67412 JH |
3601 | [(set_attr "type" "imovx") |
3602 | (set_attr "mode" "SI")]) | |
8f7661f2 JH |
3603 | |
3604 | ;; For the movzbl case strip only the clobber | |
3605 | (define_split | |
3606 | [(set (match_operand:SI 0 "register_operand" "") | |
3607 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) | |
3608 | (clobber (reg:CC 17))] | |
3609 | "reload_completed | |
3610 | && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) | |
1a06f5fe | 3611 | && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" |
8f7661f2 JH |
3612 | [(set (match_dup 0) |
3613 | (zero_extend:SI (match_dup 1)))]) | |
3614 | ||
3615 | ;; When source and destination does not overlap, clear destination | |
3616 | ;; first and then do the movb | |
2ae0f82c SC |
3617 | (define_split |
3618 | [(set (match_operand:SI 0 "register_operand" "") | |
e075ae69 RH |
3619 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) |
3620 | (clobber (reg:CC 17))] | |
3621 | "reload_completed | |
1a06f5fe JH |
3622 | && ANY_QI_REG_P (operands[0]) |
3623 | && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM) | |
8f7661f2 | 3624 | && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) |
e075ae69 | 3625 | && !reg_overlap_mentioned_p (operands[0], operands[1])" |
8f7661f2 JH |
3626 | [(set (match_dup 0) (const_int 0)) |
3627 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
3628 | "operands[2] = gen_lowpart (QImode, operands[0]);") | |
2ae0f82c | 3629 | |
8f7661f2 | 3630 | ;; Rest is handled by single and. |
2ae0f82c SC |
3631 | (define_split |
3632 | [(set (match_operand:SI 0 "register_operand" "") | |
e075ae69 RH |
3633 | (zero_extend:SI (match_operand:QI 1 "register_operand" ""))) |
3634 | (clobber (reg:CC 17))] | |
3635 | "reload_completed | |
8f7661f2 JH |
3636 | && true_regnum (operands[0]) == true_regnum (operands[1])" |
3637 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255))) | |
e075ae69 RH |
3638 | (clobber (reg:CC 17))])] |
3639 | "") | |
2ae0f82c | 3640 | |
e075ae69 | 3641 | ;; %%% Kill me once multi-word ops are sane. |
123bf9e3 JH |
3642 | (define_expand "zero_extendsidi2" |
3643 | [(set (match_operand:DI 0 "register_operand" "=r") | |
3644 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] | |
3645 | "" | |
3646 | "if (!TARGET_64BIT) | |
3647 | { | |
3648 | emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1])); | |
3649 | DONE; | |
3650 | } | |
3651 | ") | |
3652 | ||
3653 | (define_insn "zero_extendsidi2_32" | |
bb62e19a | 3654 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o") |
123bf9e3 | 3655 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r"))) |
e075ae69 | 3656 | (clobber (reg:CC 17))] |
123bf9e3 | 3657 | "!TARGET_64BIT" |
6ef67412 JH |
3658 | "#" |
3659 | [(set_attr "mode" "SI")]) | |
2ae0f82c | 3660 | |
123bf9e3 JH |
3661 | (define_insn "zero_extendsidi2_rex64" |
3662 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") | |
3663 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))] | |
3664 | "TARGET_64BIT" | |
3665 | "@ | |
0f40f9f7 | 3666 | mov\t{%k1, %k0|%k0, %k1} |
123bf9e3 JH |
3667 | #" |
3668 | [(set_attr "type" "imovx,imov") | |
3669 | (set_attr "mode" "SI,DI")]) | |
3670 | ||
3671 | (define_split | |
3672 | [(set (match_operand:DI 0 "memory_operand" "") | |
3673 | (zero_extend:DI (match_dup 0)))] | |
1b0c37d7 | 3674 | "TARGET_64BIT" |
123bf9e3 JH |
3675 | [(set (match_dup 4) (const_int 0))] |
3676 | "split_di (&operands[0], 1, &operands[3], &operands[4]);") | |
3677 | ||
bb62e19a JH |
3678 | (define_split |
3679 | [(set (match_operand:DI 0 "register_operand" "") | |
e075ae69 RH |
3680 | (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) |
3681 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
3682 | "!TARGET_64BIT && reload_completed |
3683 | && true_regnum (operands[0]) == true_regnum (operands[1])" | |
591702de | 3684 | [(set (match_dup 4) (const_int 0))] |
bb62e19a JH |
3685 | "split_di (&operands[0], 1, &operands[3], &operands[4]);") |
3686 | ||
3687 | (define_split | |
3688 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
e075ae69 RH |
3689 | (zero_extend:DI (match_operand:SI 1 "general_operand" ""))) |
3690 | (clobber (reg:CC 17))] | |
1b0c37d7 | 3691 | "!TARGET_64BIT && reload_completed" |
bb62e19a | 3692 | [(set (match_dup 3) (match_dup 1)) |
591702de | 3693 | (set (match_dup 4) (const_int 0))] |
bb62e19a | 3694 | "split_di (&operands[0], 1, &operands[3], &operands[4]);") |
123bf9e3 JH |
3695 | |
3696 | (define_insn "zero_extendhidi2" | |
3697 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
3698 | (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] | |
3699 | "TARGET_64BIT" | |
3700 | "@ | |
0f40f9f7 ZW |
3701 | movz{wl|x}\t{%1, %k0|%k0, %1} |
3702 | movz{wq|x}\t{%1, %0|%0, %1}" | |
123bf9e3 JH |
3703 | [(set_attr "type" "imovx") |
3704 | (set_attr "mode" "SI,DI")]) | |
3705 | ||
3706 | (define_insn "zero_extendqidi2" | |
3707 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
3708 | (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))] | |
3709 | "TARGET_64BIT" | |
3710 | "@ | |
0f40f9f7 ZW |
3711 | movz{bl|x}\t{%1, %k0|%k0, %1} |
3712 | movz{bq|x}\t{%1, %0|%0, %1}" | |
123bf9e3 JH |
3713 | [(set_attr "type" "imovx") |
3714 | (set_attr "mode" "SI,DI")]) | |
886c62d1 | 3715 | \f |
e075ae69 | 3716 | ;; Sign extension instructions |
886c62d1 | 3717 | |
123bf9e3 JH |
3718 | (define_expand "extendsidi2" |
3719 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
3720 | (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) | |
3721 | (clobber (reg:CC 17)) | |
3722 | (clobber (match_scratch:SI 2 ""))])] | |
3723 | "" | |
123bf9e3 JH |
3724 | { |
3725 | if (TARGET_64BIT) | |
3726 | { | |
3727 | emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1])); | |
3728 | DONE; | |
3729 | } | |
0f40f9f7 | 3730 | }) |
123bf9e3 JH |
3731 | |
3732 | (define_insn "*extendsidi2_1" | |
e075ae69 RH |
3733 | [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o") |
3734 | (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r"))) | |
6b29b0e2 JW |
3735 | (clobber (reg:CC 17)) |
3736 | (clobber (match_scratch:SI 2 "=X,X,X,&r"))] | |
123bf9e3 | 3737 | "!TARGET_64BIT" |
724d568a JH |
3738 | "#") |
3739 | ||
123bf9e3 JH |
3740 | (define_insn "extendsidi2_rex64" |
3741 | [(set (match_operand:DI 0 "register_operand" "=*a,r") | |
3742 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))] | |
3743 | "TARGET_64BIT" | |
3744 | "@ | |
3745 | {cltq|cdqe} | |
0f40f9f7 | 3746 | movs{lq|x}\t{%1,%0|%0, %1}" |
123bf9e3 JH |
3747 | [(set_attr "type" "imovx") |
3748 | (set_attr "mode" "DI") | |
3749 | (set_attr "prefix_0f" "0") | |
3750 | (set_attr "modrm" "0,1")]) | |
3751 | ||
3752 | (define_insn "extendhidi2" | |
3753 | [(set (match_operand:DI 0 "register_operand" "=r") | |
3754 | (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] | |
3755 | "TARGET_64BIT" | |
0f40f9f7 | 3756 | "movs{wq|x}\t{%1,%0|%0, %1}" |
123bf9e3 JH |
3757 | [(set_attr "type" "imovx") |
3758 | (set_attr "mode" "DI")]) | |
3759 | ||
3760 | (define_insn "extendqidi2" | |
3761 | [(set (match_operand:DI 0 "register_operand" "=r") | |
3762 | (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))] | |
3763 | "TARGET_64BIT" | |
0f40f9f7 | 3764 | "movs{bq|x}\t{%1,%0|%0, %1}" |
123bf9e3 JH |
3765 | [(set_attr "type" "imovx") |
3766 | (set_attr "mode" "DI")]) | |
3767 | ||
724d568a JH |
3768 | ;; Extend to memory case when source register does die. |
3769 | (define_split | |
3770 | [(set (match_operand:DI 0 "memory_operand" "") | |
3771 | (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) | |
6b29b0e2 JW |
3772 | (clobber (reg:CC 17)) |
3773 | (clobber (match_operand:SI 2 "register_operand" ""))] | |
d7a29404 | 3774 | "(reload_completed |
724d568a JH |
3775 | && dead_or_set_p (insn, operands[1]) |
3776 | && !reg_mentioned_p (operands[1], operands[0]))" | |
3777 | [(set (match_dup 3) (match_dup 1)) | |
e075ae69 RH |
3778 | (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31))) |
3779 | (clobber (reg:CC 17))]) | |
724d568a JH |
3780 | (set (match_dup 4) (match_dup 1))] |
3781 | "split_di (&operands[0], 1, &operands[3], &operands[4]);") | |
3782 | ||
3783 | ;; Extend to memory case when source register does not die. | |
3784 | (define_split | |
3785 | [(set (match_operand:DI 0 "memory_operand" "") | |
3786 | (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) | |
6b29b0e2 JW |
3787 | (clobber (reg:CC 17)) |
3788 | (clobber (match_operand:SI 2 "register_operand" ""))] | |
d7a29404 | 3789 | "reload_completed" |
724d568a | 3790 | [(const_int 0)] |
9c530261 | 3791 | { |
724d568a JH |
3792 | split_di (&operands[0], 1, &operands[3], &operands[4]); |
3793 | ||
3794 | emit_move_insn (operands[3], operands[1]); | |
3795 | ||
3796 | /* Generate a cltd if possible and doing so it profitable. */ | |
3797 | if (true_regnum (operands[1]) == 0 | |
3798 | && true_regnum (operands[2]) == 1 | |
e075ae69 | 3799 | && (optimize_size || TARGET_USE_CLTD)) |
71a247f0 | 3800 | { |
e075ae69 | 3801 | emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31))); |
724d568a JH |
3802 | } |
3803 | else | |
3804 | { | |
3805 | emit_move_insn (operands[2], operands[1]); | |
e075ae69 | 3806 | emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31))); |
71a247f0 | 3807 | } |
724d568a JH |
3808 | emit_move_insn (operands[4], operands[2]); |
3809 | DONE; | |
0f40f9f7 | 3810 | }) |
9c530261 | 3811 | |
724d568a JH |
3812 | ;; Extend to register case. Optimize case where source and destination |
3813 | ;; registers match and cases where we can use cltd. | |
3814 | (define_split | |
3815 | [(set (match_operand:DI 0 "register_operand" "") | |
3816 | (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) | |
6b29b0e2 JW |
3817 | (clobber (reg:CC 17)) |
3818 | (clobber (match_scratch:SI 2 ""))] | |
724d568a JH |
3819 | "reload_completed" |
3820 | [(const_int 0)] | |
724d568a JH |
3821 | { |
3822 | split_di (&operands[0], 1, &operands[3], &operands[4]); | |
3823 | ||
3824 | if (true_regnum (operands[3]) != true_regnum (operands[1])) | |
3825 | emit_move_insn (operands[3], operands[1]); | |
9c530261 | 3826 | |
724d568a JH |
3827 | /* Generate a cltd if possible and doing so it profitable. */ |
3828 | if (true_regnum (operands[3]) == 0 | |
e075ae69 | 3829 | && (optimize_size || TARGET_USE_CLTD)) |
724d568a | 3830 | { |
e075ae69 | 3831 | emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31))); |
724d568a JH |
3832 | DONE; |
3833 | } | |
3834 | ||
3835 | if (true_regnum (operands[4]) != true_regnum (operands[1])) | |
3836 | emit_move_insn (operands[4], operands[1]); | |
3837 | ||
e075ae69 | 3838 | emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31))); |
724d568a | 3839 | DONE; |
0f40f9f7 | 3840 | }) |
886c62d1 | 3841 | |
886c62d1 | 3842 | (define_insn "extendhisi2" |
e075ae69 RH |
3843 | [(set (match_operand:SI 0 "register_operand" "=*a,r") |
3844 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))] | |
886c62d1 | 3845 | "" |
886c62d1 | 3846 | { |
6ef67412 | 3847 | switch (get_attr_prefix_0f (insn)) |
e075ae69 | 3848 | { |
6ef67412 | 3849 | case 0: |
0f40f9f7 | 3850 | return "{cwtl|cwde}"; |
e075ae69 | 3851 | default: |
0f40f9f7 | 3852 | return "movs{wl|x}\t{%1,%0|%0, %1}"; |
e075ae69 | 3853 | } |
0f40f9f7 | 3854 | } |
e075ae69 | 3855 | [(set_attr "type" "imovx") |
6ef67412 JH |
3856 | (set_attr "mode" "SI") |
3857 | (set (attr "prefix_0f") | |
3858 | ;; movsx is short decodable while cwtl is vector decoded. | |
3859 | (if_then_else (and (eq_attr "cpu" "!k6") | |
3860 | (eq_attr "alternative" "0")) | |
3861 | (const_string "0") | |
3862 | (const_string "1"))) | |
3863 | (set (attr "modrm") | |
3864 | (if_then_else (eq_attr "prefix_0f" "0") | |
3865 | (const_string "0") | |
3866 | (const_string "1")))]) | |
886c62d1 | 3867 | |
123bf9e3 JH |
3868 | (define_insn "*extendhisi2_zext" |
3869 | [(set (match_operand:DI 0 "register_operand" "=*a,r") | |
3870 | (zero_extend:DI | |
3871 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))] | |
3872 | "TARGET_64BIT" | |
123bf9e3 JH |
3873 | { |
3874 | switch (get_attr_prefix_0f (insn)) | |
3875 | { | |
3876 | case 0: | |
0f40f9f7 | 3877 | return "{cwtl|cwde}"; |
123bf9e3 | 3878 | default: |
0f40f9f7 | 3879 | return "movs{wl|x}\t{%1,%k0|%k0, %1}"; |
123bf9e3 | 3880 | } |
0f40f9f7 | 3881 | } |
123bf9e3 JH |
3882 | [(set_attr "type" "imovx") |
3883 | (set_attr "mode" "SI") | |
3884 | (set (attr "prefix_0f") | |
3885 | ;; movsx is short decodable while cwtl is vector decoded. | |
3886 | (if_then_else (and (eq_attr "cpu" "!k6") | |
3887 | (eq_attr "alternative" "0")) | |
3888 | (const_string "0") | |
3889 | (const_string "1"))) | |
3890 | (set (attr "modrm") | |
3891 | (if_then_else (eq_attr "prefix_0f" "0") | |
3892 | (const_string "0") | |
3893 | (const_string "1")))]) | |
3894 | ||
886c62d1 | 3895 | (define_insn "extendqihi2" |
e075ae69 RH |
3896 | [(set (match_operand:HI 0 "register_operand" "=*a,r") |
3897 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))] | |
886c62d1 | 3898 | "" |
886c62d1 | 3899 | { |
6ef67412 | 3900 | switch (get_attr_prefix_0f (insn)) |
e075ae69 | 3901 | { |
6ef67412 | 3902 | case 0: |
0f40f9f7 | 3903 | return "{cbtw|cbw}"; |
e075ae69 | 3904 | default: |
0f40f9f7 | 3905 | return "movs{bw|x}\t{%1,%0|%0, %1}"; |
e075ae69 | 3906 | } |
0f40f9f7 | 3907 | } |
e075ae69 | 3908 | [(set_attr "type" "imovx") |
6ef67412 JH |
3909 | (set_attr "mode" "HI") |
3910 | (set (attr "prefix_0f") | |
3911 | ;; movsx is short decodable while cwtl is vector decoded. | |
3912 | (if_then_else (and (eq_attr "cpu" "!k6") | |
3913 | (eq_attr "alternative" "0")) | |
3914 | (const_string "0") | |
3915 | (const_string "1"))) | |
3916 | (set (attr "modrm") | |
3917 | (if_then_else (eq_attr "prefix_0f" "0") | |
3918 | (const_string "0") | |
3919 | (const_string "1")))]) | |
886c62d1 JVA |
3920 | |
3921 | (define_insn "extendqisi2" | |
2ae0f82c SC |
3922 | [(set (match_operand:SI 0 "register_operand" "=r") |
3923 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] | |
886c62d1 | 3924 | "" |
0f40f9f7 | 3925 | "movs{bl|x}\t{%1,%0|%0, %1}" |
6ef67412 JH |
3926 | [(set_attr "type" "imovx") |
3927 | (set_attr "mode" "SI")]) | |
123bf9e3 JH |
3928 | |
3929 | (define_insn "*extendqisi2_zext" | |
3930 | [(set (match_operand:DI 0 "register_operand" "=r") | |
3931 | (zero_extend:DI | |
3932 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))] | |
3933 | "TARGET_64BIT" | |
0f40f9f7 | 3934 | "movs{bl|x}\t{%1,%k0|%k0, %1}" |
123bf9e3 JH |
3935 | [(set_attr "type" "imovx") |
3936 | (set_attr "mode" "SI")]) | |
886c62d1 JVA |
3937 | \f |
3938 | ;; Conversions between float and double. | |
3939 | ||
e075ae69 RH |
3940 | ;; These are all no-ops in the model used for the 80387. So just |
3941 | ;; emit moves. | |
6a4a5d95 | 3942 | |
e075ae69 | 3943 | ;; %%% Kill these when call knows how to work out a DFmode push earlier. |
6343a50e | 3944 | (define_insn "*dummy_extendsfdf2" |
e075ae69 | 3945 | [(set (match_operand:DF 0 "push_operand" "=<") |
42a0aa6f | 3946 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))] |
e075ae69 RH |
3947 | "0" |
3948 | "#") | |
6a4a5d95 JW |
3949 | |
3950 | (define_split | |
e075ae69 RH |
3951 | [(set (match_operand:DF 0 "push_operand" "") |
3952 | (float_extend:DF (match_operand:SF 1 "register_operand" "")))] | |
1b0c37d7 | 3953 | "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))" |
e075ae69 RH |
3954 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) |
3955 | (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))]) | |
0fcad513 | 3956 | |
123bf9e3 JH |
3957 | (define_split |
3958 | [(set (match_operand:DF 0 "push_operand" "") | |
3959 | (float_extend:DF (match_operand:SF 1 "register_operand" "")))] | |
1b0c37d7 | 3960 | "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))" |
123bf9e3 JH |
3961 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) |
3962 | (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))]) | |
3963 | ||
6343a50e | 3964 | (define_insn "*dummy_extendsfxf2" |
e075ae69 RH |
3965 | [(set (match_operand:XF 0 "push_operand" "=<") |
3966 | (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))] | |
3967 | "0" | |
3968 | "#") | |
e4ad1003 JW |
3969 | |
3970 | (define_split | |
e075ae69 RH |
3971 | [(set (match_operand:XF 0 "push_operand" "") |
3972 | (float_extend:XF (match_operand:SF 1 "register_operand" "")))] | |
1b0c37d7 | 3973 | "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))" |
e075ae69 | 3974 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) |
2b589241 JH |
3975 | (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) |
3976 | ||
3977 | (define_insn "*dummy_extendsftf2" | |
3978 | [(set (match_operand:TF 0 "push_operand" "=<") | |
3979 | (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))] | |
3980 | "0" | |
3981 | "#") | |
3982 | ||
3983 | (define_split | |
3984 | [(set (match_operand:TF 0 "push_operand" "") | |
3985 | (float_extend:TF (match_operand:SF 1 "register_operand" "")))] | |
1b0c37d7 | 3986 | "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))" |
2b589241 | 3987 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) |
123bf9e3 JH |
3988 | (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))]) |
3989 | ||
3990 | (define_split | |
3991 | [(set (match_operand:TF 0 "push_operand" "") | |
3992 | (float_extend:TF (match_operand:SF 1 "register_operand" "")))] | |
1b0c37d7 | 3993 | "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))" |
123bf9e3 JH |
3994 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) |
3995 | (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))]) | |
4fb21e90 | 3996 | |
6343a50e | 3997 | (define_insn "*dummy_extenddfxf2" |
e075ae69 RH |
3998 | [(set (match_operand:XF 0 "push_operand" "=<") |
3999 | (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))] | |
4000 | "0" | |
4001 | "#") | |
e4ad1003 JW |
4002 | |
4003 | (define_split | |
e075ae69 RH |
4004 | [(set (match_operand:XF 0 "push_operand" "") |
4005 | (float_extend:XF (match_operand:DF 1 "register_operand" "")))] | |
1b0c37d7 | 4006 | "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))" |
e075ae69 | 4007 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) |
123bf9e3 | 4008 | (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) |
2b589241 JH |
4009 | |
4010 | (define_insn "*dummy_extenddftf2" | |
4011 | [(set (match_operand:TF 0 "push_operand" "=<") | |
4012 | (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))] | |
4013 | "0" | |
4014 | "#") | |
4015 | ||
4016 | (define_split | |
4017 | [(set (match_operand:TF 0 "push_operand" "") | |
4018 | (float_extend:TF (match_operand:DF 1 "register_operand" "")))] | |
1b0c37d7 | 4019 | "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))" |
2b589241 JH |
4020 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) |
4021 | (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) | |
4fb21e90 | 4022 | |
123bf9e3 JH |
4023 | (define_split |
4024 | [(set (match_operand:TF 0 "push_operand" "") | |
4025 | (float_extend:TF (match_operand:DF 1 "register_operand" "")))] | |
1b0c37d7 | 4026 | "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))" |
123bf9e3 | 4027 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) |
a2bafd20 | 4028 | (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))]) |
123bf9e3 | 4029 | |
f97d9ec3 JH |
4030 | (define_expand "extendsfdf2" |
4031 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
4032 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
42a0aa6f | 4033 | "TARGET_80387 || TARGET_SSE2" |
f97d9ec3 JH |
4034 | { |
4035 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) | |
34289d57 | 4036 | operands[1] = force_reg (SFmode, operands[1]); |
0f40f9f7 | 4037 | }) |
f97d9ec3 JH |
4038 | |
4039 | (define_insn "*extendsfdf2_1" | |
a811cc63 JH |
4040 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f") |
4041 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))] | |
42a0aa6f | 4042 | "(TARGET_80387 || TARGET_SSE2) |
f97d9ec3 | 4043 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" |
4fb21e90 | 4044 | { |
e075ae69 | 4045 | switch (which_alternative) |
4fb21e90 | 4046 | { |
e075ae69 | 4047 | case 0: |
0c174a68 AB |
4048 | if (REG_P (operands[1]) |
4049 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4050 | return "fstp\t%y0"; |
e075ae69 | 4051 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 4052 | return "fld%z1\t%y1"; |
e075ae69 | 4053 | else |
0f40f9f7 | 4054 | return "fst\t%y0"; |
886c62d1 | 4055 | |
e075ae69 RH |
4056 | case 1: |
4057 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4058 | return "fstp%z0\t%y0"; |
10195bd8 | 4059 | |
e075ae69 | 4060 | else |
0f40f9f7 | 4061 | return "fst%z0\t%y0"; |
42a0aa6f | 4062 | case 2: |
0f40f9f7 | 4063 | return "cvtss2sd\t{%1, %0|%0, %1}"; |
4fb21e90 | 4064 | |
e075ae69 RH |
4065 | default: |
4066 | abort (); | |
4067 | } | |
0f40f9f7 | 4068 | } |
a811cc63 JH |
4069 | [(set_attr "type" "fmov,fmov,sse") |
4070 | (set_attr "mode" "SF,XF,DF")]) | |
42a0aa6f JH |
4071 | |
4072 | (define_insn "*extendsfdf2_1_sse_only" | |
4073 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
4074 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))] | |
4075 | "!TARGET_80387 && TARGET_SSE2 | |
4076 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
0f40f9f7 | 4077 | "cvtss2sd\t{%1, %0|%0, %1}" |
42a0aa6f JH |
4078 | [(set_attr "type" "sse") |
4079 | (set_attr "mode" "DF")]) | |
e075ae69 | 4080 | |
f97d9ec3 JH |
4081 | (define_expand "extendsfxf2" |
4082 | [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
4083 | (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
1b0c37d7 | 4084 | "!TARGET_64BIT && TARGET_80387" |
f97d9ec3 JH |
4085 | { |
4086 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) | |
34289d57 | 4087 | operands[1] = force_reg (SFmode, operands[1]); |
0f40f9f7 | 4088 | }) |
f97d9ec3 JH |
4089 | |
4090 | (define_insn "*extendsfxf2_1" | |
e075ae69 RH |
4091 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") |
4092 | (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] | |
1b0c37d7 | 4093 | "!TARGET_64BIT && TARGET_80387 |
f97d9ec3 | 4094 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" |
10195bd8 | 4095 | { |
e075ae69 RH |
4096 | switch (which_alternative) |
4097 | { | |
4098 | case 0: | |
0c174a68 AB |
4099 | if (REG_P (operands[1]) |
4100 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4101 | return "fstp\t%y0"; |
e075ae69 | 4102 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 4103 | return "fld%z1\t%y1"; |
e075ae69 | 4104 | else |
0f40f9f7 | 4105 | return "fst\t%y0"; |
886c62d1 | 4106 | |
e075ae69 RH |
4107 | case 1: |
4108 | /* There is no non-popping store to memory for XFmode. So if | |
4109 | we need one, follow the store with a load. */ | |
4110 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4111 | return "fstp%z0\t%y0\n\tfld%z0\t%y0"; |
e075ae69 | 4112 | else |
0f40f9f7 | 4113 | return "fstp%z0\t%y0"; |
886c62d1 | 4114 | |
e075ae69 RH |
4115 | default: |
4116 | abort (); | |
4117 | } | |
0f40f9f7 | 4118 | } |
6ef67412 JH |
4119 | [(set_attr "type" "fmov") |
4120 | (set_attr "mode" "SF,XF")]) | |
886c62d1 | 4121 | |
2b589241 JH |
4122 | (define_expand "extendsftf2" |
4123 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
4124 | (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
4125 | "TARGET_80387" | |
2b589241 JH |
4126 | { |
4127 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) | |
4128 | operands[1] = force_reg (SFmode, operands[1]); | |
0f40f9f7 | 4129 | }) |
2b589241 JH |
4130 | |
4131 | (define_insn "*extendsftf2_1" | |
4132 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m") | |
4133 | (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] | |
4134 | "TARGET_80387 | |
4135 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
2b589241 JH |
4136 | { |
4137 | switch (which_alternative) | |
4138 | { | |
4139 | case 0: | |
4140 | if (REG_P (operands[1]) | |
4141 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4142 | return "fstp\t%y0"; |
2b589241 | 4143 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 4144 | return "fld%z1\t%y1"; |
2b589241 | 4145 | else |
0f40f9f7 | 4146 | return "fst\t%y0"; |
2b589241 JH |
4147 | |
4148 | case 1: | |
4149 | /* There is no non-popping store to memory for XFmode. So if | |
4150 | we need one, follow the store with a load. */ | |
4151 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4152 | return "fstp%z0\t%y0\n\tfld%z0\t%y0"; |
2b589241 | 4153 | else |
0f40f9f7 | 4154 | return "fstp%z0\t%y0"; |
2b589241 JH |
4155 | |
4156 | default: | |
4157 | abort (); | |
4158 | } | |
0f40f9f7 | 4159 | } |
2b589241 JH |
4160 | [(set_attr "type" "fmov") |
4161 | (set_attr "mode" "SF,XF")]) | |
4162 | ||
f97d9ec3 JH |
4163 | (define_expand "extenddfxf2" |
4164 | [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
4165 | (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))] | |
1b0c37d7 | 4166 | "!TARGET_64BIT && TARGET_80387" |
f97d9ec3 JH |
4167 | { |
4168 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) | |
34289d57 | 4169 | operands[1] = force_reg (DFmode, operands[1]); |
0f40f9f7 | 4170 | }) |
f97d9ec3 JH |
4171 | |
4172 | (define_insn "*extenddfxf2_1" | |
e075ae69 RH |
4173 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") |
4174 | (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] | |
1b0c37d7 | 4175 | "!TARGET_64BIT && TARGET_80387 |
f97d9ec3 | 4176 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" |
e075ae69 RH |
4177 | { |
4178 | switch (which_alternative) | |
4179 | { | |
4180 | case 0: | |
0c174a68 AB |
4181 | if (REG_P (operands[1]) |
4182 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4183 | return "fstp\t%y0"; |
e075ae69 | 4184 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 4185 | return "fld%z1\t%y1"; |
e075ae69 | 4186 | else |
0f40f9f7 | 4187 | return "fst\t%y0"; |
bc725565 | 4188 | |
e075ae69 RH |
4189 | case 1: |
4190 | /* There is no non-popping store to memory for XFmode. So if | |
4191 | we need one, follow the store with a load. */ | |
4192 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4193 | return "fstp%z0\t%y0\n\tfld%z0\t%y0"; |
e075ae69 | 4194 | else |
0f40f9f7 | 4195 | return "fstp%z0\t%y0"; |
bc725565 | 4196 | |
e075ae69 RH |
4197 | default: |
4198 | abort (); | |
4199 | } | |
0f40f9f7 | 4200 | } |
6ef67412 JH |
4201 | [(set_attr "type" "fmov") |
4202 | (set_attr "mode" "DF,XF")]) | |
bc725565 | 4203 | |
2b589241 JH |
4204 | (define_expand "extenddftf2" |
4205 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
4206 | (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))] | |
4207 | "TARGET_80387" | |
2b589241 JH |
4208 | { |
4209 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) | |
4210 | operands[1] = force_reg (DFmode, operands[1]); | |
0f40f9f7 | 4211 | }) |
2b589241 JH |
4212 | |
4213 | (define_insn "*extenddftf2_1" | |
4214 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m") | |
4215 | (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] | |
4216 | "TARGET_80387 | |
4217 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
2b589241 JH |
4218 | { |
4219 | switch (which_alternative) | |
4220 | { | |
4221 | case 0: | |
4222 | if (REG_P (operands[1]) | |
4223 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4224 | return "fstp\t%y0"; |
2b589241 | 4225 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 4226 | return "fld%z1\t%y1"; |
2b589241 | 4227 | else |
0f40f9f7 | 4228 | return "fst\t%y0"; |
2b589241 JH |
4229 | |
4230 | case 1: | |
4231 | /* There is no non-popping store to memory for XFmode. So if | |
4232 | we need one, follow the store with a load. */ | |
4233 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4234 | return "fstp%z0\t%y0\n\tfld%z0\t%y0"; |
2b589241 | 4235 | else |
0f40f9f7 | 4236 | return "fstp%z0\t%y0"; |
2b589241 JH |
4237 | |
4238 | default: | |
4239 | abort (); | |
4240 | } | |
0f40f9f7 | 4241 | } |
2b589241 JH |
4242 | [(set_attr "type" "fmov") |
4243 | (set_attr "mode" "DF,XF")]) | |
4244 | ||
e075ae69 RH |
4245 | ;; %%% This seems bad bad news. |
4246 | ;; This cannot output into an f-reg because there is no way to be sure | |
4247 | ;; of truncating in that case. Otherwise this is just like a simple move | |
4248 | ;; insn. So we pretend we can output to a reg in order to get better | |
4249 | ;; register preferencing, but we really use a stack slot. | |
886c62d1 | 4250 | |
e075ae69 RH |
4251 | (define_expand "truncdfsf2" |
4252 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
4253 | (float_truncate:SF | |
4254 | (match_operand:DF 1 "register_operand" ""))) | |
4255 | (clobber (match_dup 2))])] | |
42a0aa6f JH |
4256 | "TARGET_80387 || TARGET_SSE2" |
4257 | " | |
4258 | if (TARGET_80387) | |
4259 | operands[2] = assign_386_stack_local (SFmode, 0); | |
4260 | else | |
4261 | { | |
4262 | emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1])); | |
4263 | DONE; | |
4264 | } | |
4265 | ") | |
bc725565 | 4266 | |
e075ae69 | 4267 | (define_insn "*truncdfsf2_1" |
46ed7963 | 4268 | [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") |
e075ae69 | 4269 | (float_truncate:SF |
46ed7963 JH |
4270 | (match_operand:DF 1 "register_operand" "f,f,f,f"))) |
4271 | (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] | |
42a0aa6f | 4272 | "TARGET_80387 && !TARGET_SSE2" |
e075ae69 RH |
4273 | { |
4274 | switch (which_alternative) | |
4275 | { | |
4276 | case 0: | |
4277 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4278 | return "fstp%z0\t%y0"; |
e075ae69 | 4279 | else |
0f40f9f7 | 4280 | return "fst%z0\t%y0"; |
46ed7963 JH |
4281 | default: |
4282 | abort (); | |
e075ae69 | 4283 | } |
0f40f9f7 | 4284 | } |
46ed7963 JH |
4285 | [(set_attr "type" "fmov,multi,multi,multi") |
4286 | (set_attr "mode" "SF,SF,SF,SF")]) | |
42a0aa6f JH |
4287 | |
4288 | (define_insn "*truncdfsf2_1_sse" | |
46ed7963 | 4289 | [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y") |
42a0aa6f | 4290 | (float_truncate:SF |
46ed7963 JH |
4291 | (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY"))) |
4292 | (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))] | |
42a0aa6f | 4293 | "TARGET_80387 && TARGET_SSE2" |
42a0aa6f JH |
4294 | { |
4295 | switch (which_alternative) | |
4296 | { | |
4297 | case 0: | |
4298 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4299 | return "fstp%z0\t%y0"; |
42a0aa6f | 4300 | else |
0f40f9f7 | 4301 | return "fst%z0\t%y0"; |
46ed7963 | 4302 | case 4: |
0f40f9f7 | 4303 | return "cvtsd2ss\t{%1, %0|%0, %1}"; |
46ed7963 JH |
4304 | default: |
4305 | abort (); | |
42a0aa6f | 4306 | } |
0f40f9f7 | 4307 | } |
46ed7963 JH |
4308 | [(set_attr "type" "fmov,multi,multi,multi,sse") |
4309 | (set_attr "mode" "SF,SF,SF,SF,DF")]) | |
53b5ce19 | 4310 | |
e075ae69 | 4311 | (define_insn "*truncdfsf2_2" |
79005df5 | 4312 | [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m") |
42a0aa6f | 4313 | (float_truncate:SF |
79005df5 JH |
4314 | (match_operand:DF 1 "nonimmediate_operand" "mY,f")))] |
4315 | "TARGET_80387 && TARGET_SSE2 | |
4316 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
42a0aa6f JH |
4317 | { |
4318 | switch (which_alternative) | |
4319 | { | |
4320 | case 0: | |
0f40f9f7 | 4321 | return "cvtsd2ss\t{%1, %0|%0, %1}"; |
79005df5 | 4322 | case 1: |
42a0aa6f | 4323 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) |
0f40f9f7 | 4324 | return "fstp%z0\t%y0"; |
42a0aa6f | 4325 | else |
0f40f9f7 ZW |
4326 | return "fst%z0\t%y0"; |
4327 | default: | |
4328 | abort (); | |
42a0aa6f | 4329 | } |
0f40f9f7 | 4330 | } |
79005df5 JH |
4331 | [(set_attr "type" "sse,fmov") |
4332 | (set_attr "mode" "DF,SF")]) | |
42a0aa6f JH |
4333 | |
4334 | (define_insn "truncdfsf2_3" | |
cc2e591b | 4335 | [(set (match_operand:SF 0 "memory_operand" "=m") |
e075ae69 RH |
4336 | (float_truncate:SF |
4337 | (match_operand:DF 1 "register_operand" "f")))] | |
53b5ce19 | 4338 | "TARGET_80387" |
e075ae69 RH |
4339 | { |
4340 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4341 | return "fstp%z0\t%y0"; |
e075ae69 | 4342 | else |
0f40f9f7 ZW |
4343 | return "fst%z0\t%y0"; |
4344 | } | |
6ef67412 JH |
4345 | [(set_attr "type" "fmov") |
4346 | (set_attr "mode" "SF")]) | |
53b5ce19 | 4347 | |
42a0aa6f JH |
4348 | (define_insn "truncdfsf2_sse_only" |
4349 | [(set (match_operand:SF 0 "register_operand" "=Y") | |
4350 | (float_truncate:SF | |
4351 | (match_operand:DF 1 "nonimmediate_operand" "mY")))] | |
4352 | "!TARGET_80387 && TARGET_SSE2" | |
0f40f9f7 | 4353 | "cvtsd2ss\t{%1, %0|%0, %1}" |
42a0aa6f JH |
4354 | [(set_attr "type" "sse") |
4355 | (set_attr "mode" "DF")]) | |
4356 | ||
53b5ce19 | 4357 | (define_split |
e075ae69 RH |
4358 | [(set (match_operand:SF 0 "memory_operand" "") |
4359 | (float_truncate:SF | |
4360 | (match_operand:DF 1 "register_operand" ""))) | |
4361 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
4362 | "TARGET_80387" | |
4363 | [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] | |
53b5ce19 JW |
4364 | "") |
4365 | ||
42a0aa6f JH |
4366 | (define_split |
4367 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
4368 | (float_truncate:SF | |
4369 | (match_operand:DF 1 "nonimmediate_operand" ""))) | |
4370 | (clobber (match_operand 2 "" ""))] | |
05b432db JH |
4371 | "TARGET_80387 && reload_completed |
4372 | && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])" | |
42a0aa6f JH |
4373 | [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] |
4374 | "") | |
4375 | ||
53b5ce19 JW |
4376 | (define_split |
4377 | [(set (match_operand:SF 0 "register_operand" "") | |
e075ae69 RH |
4378 | (float_truncate:SF |
4379 | (match_operand:DF 1 "register_operand" ""))) | |
4380 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
42a0aa6f | 4381 | "TARGET_80387 && reload_completed |
46ed7963 | 4382 | && FP_REG_P (operands[1])" |
e075ae69 RH |
4383 | [(set (match_dup 2) (float_truncate:SF (match_dup 1))) |
4384 | (set (match_dup 0) (match_dup 2))] | |
53b5ce19 JW |
4385 | "") |
4386 | ||
e075ae69 RH |
4387 | (define_expand "truncxfsf2" |
4388 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
4389 | (float_truncate:SF | |
4390 | (match_operand:XF 1 "register_operand" ""))) | |
4391 | (clobber (match_dup 2))])] | |
1b0c37d7 | 4392 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 4393 | "operands[2] = assign_386_stack_local (SFmode, 0);") |
53b5ce19 | 4394 | |
e075ae69 | 4395 | (define_insn "*truncxfsf2_1" |
46ed7963 | 4396 | [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") |
e075ae69 | 4397 | (float_truncate:SF |
46ed7963 JH |
4398 | (match_operand:XF 1 "register_operand" "f,f,f,f"))) |
4399 | (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] | |
1b0c37d7 | 4400 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
4401 | { |
4402 | switch (which_alternative) | |
4403 | { | |
4404 | case 0: | |
4405 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4406 | return "fstp%z0\t%y0"; |
e075ae69 | 4407 | else |
0f40f9f7 | 4408 | return "fst%z0\t%y0"; |
46ed7963 JH |
4409 | default: |
4410 | abort(); | |
e075ae69 | 4411 | } |
0f40f9f7 | 4412 | } |
46ed7963 | 4413 | [(set_attr "type" "fmov,multi,multi,multi") |
6ef67412 | 4414 | (set_attr "mode" "SF")]) |
886c62d1 | 4415 | |
e075ae69 | 4416 | (define_insn "*truncxfsf2_2" |
dd80b906 | 4417 | [(set (match_operand:SF 0 "memory_operand" "=m") |
e075ae69 RH |
4418 | (float_truncate:SF |
4419 | (match_operand:XF 1 "register_operand" "f")))] | |
1b0c37d7 | 4420 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
4421 | { |
4422 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4423 | return "fstp%z0\t%y0"; |
e075ae69 | 4424 | else |
0f40f9f7 ZW |
4425 | return "fst%z0\t%y0"; |
4426 | } | |
6ef67412 JH |
4427 | [(set_attr "type" "fmov") |
4428 | (set_attr "mode" "SF")]) | |
bc725565 JW |
4429 | |
4430 | (define_split | |
e075ae69 RH |
4431 | [(set (match_operand:SF 0 "memory_operand" "") |
4432 | (float_truncate:SF | |
4433 | (match_operand:XF 1 "register_operand" ""))) | |
4434 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
4435 | "TARGET_80387" | |
4436 | [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] | |
886c62d1 JVA |
4437 | "") |
4438 | ||
bc725565 | 4439 | (define_split |
6a4a5d95 | 4440 | [(set (match_operand:SF 0 "register_operand" "") |
e075ae69 RH |
4441 | (float_truncate:SF |
4442 | (match_operand:XF 1 "register_operand" ""))) | |
4443 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
bc725565 | 4444 | "TARGET_80387 && reload_completed" |
e075ae69 RH |
4445 | [(set (match_dup 2) (float_truncate:SF (match_dup 1))) |
4446 | (set (match_dup 0) (match_dup 2))] | |
886c62d1 JVA |
4447 | "") |
4448 | ||
2b589241 JH |
4449 | (define_expand "trunctfsf2" |
4450 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
4451 | (float_truncate:SF | |
4452 | (match_operand:TF 1 "register_operand" ""))) | |
4453 | (clobber (match_dup 2))])] | |
4454 | "TARGET_80387" | |
4455 | "operands[2] = assign_386_stack_local (SFmode, 0);") | |
4456 | ||
4457 | (define_insn "*trunctfsf2_1" | |
46ed7963 | 4458 | [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") |
2b589241 | 4459 | (float_truncate:SF |
46ed7963 JH |
4460 | (match_operand:TF 1 "register_operand" "f,f,f,f"))) |
4461 | (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] | |
2b589241 | 4462 | "TARGET_80387" |
2b589241 JH |
4463 | { |
4464 | switch (which_alternative) | |
4465 | { | |
4466 | case 0: | |
4467 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4468 | return "fstp%z0\t%y0"; |
2b589241 | 4469 | else |
0f40f9f7 | 4470 | return "fst%z0\t%y0"; |
46ed7963 JH |
4471 | default: |
4472 | abort(); | |
2b589241 | 4473 | } |
0f40f9f7 | 4474 | } |
46ed7963 | 4475 | [(set_attr "type" "fmov,multi,multi,multi") |
2b589241 JH |
4476 | (set_attr "mode" "SF")]) |
4477 | ||
1e07edd3 | 4478 | (define_insn "*trunctfsf2_2" |
cc2e591b | 4479 | [(set (match_operand:SF 0 "memory_operand" "=m") |
2b589241 JH |
4480 | (float_truncate:SF |
4481 | (match_operand:TF 1 "register_operand" "f")))] | |
4482 | "TARGET_80387" | |
2b589241 JH |
4483 | { |
4484 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4485 | return "fstp%z0\t%y0"; |
2b589241 | 4486 | else |
0f40f9f7 ZW |
4487 | return "fst%z0\t%y0"; |
4488 | } | |
2b589241 JH |
4489 | [(set_attr "type" "fmov") |
4490 | (set_attr "mode" "SF")]) | |
4491 | ||
4492 | (define_split | |
4493 | [(set (match_operand:SF 0 "memory_operand" "") | |
4494 | (float_truncate:SF | |
4495 | (match_operand:TF 1 "register_operand" ""))) | |
4496 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
4497 | "TARGET_80387" | |
4498 | [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] | |
4499 | "") | |
4500 | ||
4501 | (define_split | |
4502 | [(set (match_operand:SF 0 "register_operand" "") | |
4503 | (float_truncate:SF | |
4504 | (match_operand:TF 1 "register_operand" ""))) | |
4505 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
4506 | "TARGET_80387 && reload_completed" | |
4507 | [(set (match_dup 2) (float_truncate:SF (match_dup 1))) | |
4508 | (set (match_dup 0) (match_dup 2))] | |
4509 | "") | |
4510 | ||
4511 | ||
e075ae69 RH |
4512 | (define_expand "truncxfdf2" |
4513 | [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
4514 | (float_truncate:DF | |
4515 | (match_operand:XF 1 "register_operand" ""))) | |
4516 | (clobber (match_dup 2))])] | |
1b0c37d7 | 4517 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 4518 | "operands[2] = assign_386_stack_local (DFmode, 0);") |
bc725565 | 4519 | |
e075ae69 | 4520 | (define_insn "*truncxfdf2_1" |
46ed7963 | 4521 | [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf") |
e075ae69 | 4522 | (float_truncate:DF |
46ed7963 JH |
4523 | (match_operand:XF 1 "register_operand" "f,f,f,f"))) |
4524 | (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))] | |
1b0c37d7 | 4525 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
4526 | { |
4527 | switch (which_alternative) | |
4528 | { | |
4529 | case 0: | |
4530 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4531 | return "fstp%z0\t%y0"; |
e075ae69 | 4532 | else |
0f40f9f7 | 4533 | return "fst%z0\t%y0"; |
46ed7963 JH |
4534 | default: |
4535 | abort(); | |
e075ae69 RH |
4536 | } |
4537 | abort (); | |
0f40f9f7 | 4538 | } |
46ed7963 | 4539 | [(set_attr "type" "fmov,multi,multi,multi") |
6ef67412 | 4540 | (set_attr "mode" "DF")]) |
bc725565 | 4541 | |
e075ae69 RH |
4542 | (define_insn "*truncxfdf2_2" |
4543 | [(set (match_operand:DF 0 "memory_operand" "=m") | |
4544 | (float_truncate:DF | |
4545 | (match_operand:XF 1 "register_operand" "f")))] | |
1b0c37d7 | 4546 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
4547 | { |
4548 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4549 | return "fstp%z0\t%y0"; |
e075ae69 | 4550 | else |
0f40f9f7 ZW |
4551 | return "fst%z0\t%y0"; |
4552 | } | |
6ef67412 JH |
4553 | [(set_attr "type" "fmov") |
4554 | (set_attr "mode" "DF")]) | |
bc725565 JW |
4555 | |
4556 | (define_split | |
e075ae69 RH |
4557 | [(set (match_operand:DF 0 "memory_operand" "") |
4558 | (float_truncate:DF | |
4559 | (match_operand:XF 1 "register_operand" ""))) | |
4560 | (clobber (match_operand:DF 2 "memory_operand" ""))] | |
ca285e07 JH |
4561 | "TARGET_80387" |
4562 | [(set (match_dup 0) (float_truncate:DF (match_dup 1)))] | |
4fb21e90 JVA |
4563 | "") |
4564 | ||
bc725565 | 4565 | (define_split |
6a4a5d95 | 4566 | [(set (match_operand:DF 0 "register_operand" "") |
e075ae69 RH |
4567 | (float_truncate:DF |
4568 | (match_operand:XF 1 "register_operand" ""))) | |
4569 | (clobber (match_operand:DF 2 "memory_operand" ""))] | |
bc725565 | 4570 | "TARGET_80387 && reload_completed" |
ca285e07 | 4571 | [(set (match_dup 2) (float_truncate:DF (match_dup 1))) |
e075ae69 | 4572 | (set (match_dup 0) (match_dup 2))] |
4fb21e90 | 4573 | "") |
ca285e07 | 4574 | |
2b589241 JH |
4575 | (define_expand "trunctfdf2" |
4576 | [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
4577 | (float_truncate:DF | |
4578 | (match_operand:TF 1 "register_operand" ""))) | |
4579 | (clobber (match_dup 2))])] | |
4580 | "TARGET_80387" | |
4581 | "operands[2] = assign_386_stack_local (DFmode, 0);") | |
4582 | ||
4583 | (define_insn "*trunctfdf2_1" | |
46ed7963 | 4584 | [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf") |
2b589241 | 4585 | (float_truncate:DF |
46ed7963 JH |
4586 | (match_operand:TF 1 "register_operand" "f,f,f,f"))) |
4587 | (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))] | |
2b589241 | 4588 | "TARGET_80387" |
2b589241 JH |
4589 | { |
4590 | switch (which_alternative) | |
4591 | { | |
4592 | case 0: | |
4593 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4594 | return "fstp%z0\t%y0"; |
2b589241 | 4595 | else |
0f40f9f7 | 4596 | return "fst%z0\t%y0"; |
46ed7963 JH |
4597 | default: |
4598 | abort(); | |
2b589241 JH |
4599 | } |
4600 | abort (); | |
0f40f9f7 | 4601 | } |
46ed7963 | 4602 | [(set_attr "type" "fmov,multi,multi,multi") |
2b589241 JH |
4603 | (set_attr "mode" "DF")]) |
4604 | ||
46ed7963 | 4605 | (define_insn "*trunctfdf2_2" |
2b589241 JH |
4606 | [(set (match_operand:DF 0 "memory_operand" "=m") |
4607 | (float_truncate:DF | |
4608 | (match_operand:TF 1 "register_operand" "f")))] | |
4609 | "TARGET_80387" | |
2b589241 JH |
4610 | { |
4611 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4612 | return "fstp%z0\t%y0"; |
2b589241 | 4613 | else |
0f40f9f7 ZW |
4614 | return "fst%z0\t%y0"; |
4615 | } | |
2b589241 JH |
4616 | [(set_attr "type" "fmov") |
4617 | (set_attr "mode" "DF")]) | |
4618 | ||
4619 | (define_split | |
4620 | [(set (match_operand:DF 0 "memory_operand" "") | |
4621 | (float_truncate:DF | |
4622 | (match_operand:TF 1 "register_operand" ""))) | |
4623 | (clobber (match_operand:DF 2 "memory_operand" ""))] | |
4624 | "TARGET_80387" | |
4625 | [(set (match_dup 0) (float_truncate:DF (match_dup 1)))] | |
4626 | "") | |
4627 | ||
4628 | (define_split | |
4629 | [(set (match_operand:DF 0 "register_operand" "") | |
4630 | (float_truncate:DF | |
4631 | (match_operand:TF 1 "register_operand" ""))) | |
4632 | (clobber (match_operand:DF 2 "memory_operand" ""))] | |
4633 | "TARGET_80387 && reload_completed" | |
4634 | [(set (match_dup 2) (float_truncate:DF (match_dup 1))) | |
4635 | (set (match_dup 0) (match_dup 2))] | |
4636 | "") | |
4637 | ||
e075ae69 RH |
4638 | \f |
4639 | ;; %%% Break up all these bad boys. | |
4fb21e90 | 4640 | |
e075ae69 RH |
4641 | ;; Signed conversion to DImode. |
4642 | ||
2b589241 | 4643 | (define_expand "fix_truncxfdi2" |
22fb740d JH |
4644 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4645 | (fix:DI (match_operand:XF 1 "register_operand" "")))] | |
1b0c37d7 | 4646 | "!TARGET_64BIT && TARGET_80387" |
22fb740d | 4647 | "") |
2b589241 JH |
4648 | |
4649 | (define_expand "fix_trunctfdi2" | |
22fb740d JH |
4650 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4651 | (fix:DI (match_operand:TF 1 "register_operand" "")))] | |
bc725565 | 4652 | "TARGET_80387" |
22fb740d | 4653 | "") |
bc725565 | 4654 | |
e075ae69 | 4655 | (define_expand "fix_truncdfdi2" |
22fb740d JH |
4656 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4657 | (fix:DI (match_operand:DF 1 "register_operand" "")))] | |
46ed7963 | 4658 | "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)" |
46ed7963 | 4659 | { |
1b0c37d7 | 4660 | if (TARGET_64BIT && TARGET_SSE2) |
46ed7963 JH |
4661 | { |
4662 | rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode); | |
4663 | emit_insn (gen_fix_truncdfdi_sse (out, operands[1])); | |
4664 | if (out != operands[0]) | |
4665 | emit_move_insn (operands[0], out); | |
4666 | DONE; | |
4667 | } | |
0f40f9f7 | 4668 | }) |
53b5ce19 | 4669 | |
e075ae69 | 4670 | (define_expand "fix_truncsfdi2" |
22fb740d JH |
4671 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4672 | (fix:DI (match_operand:SF 1 "register_operand" "")))] | |
46ed7963 | 4673 | "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)" |
46ed7963 | 4674 | { |
22fb740d | 4675 | if (TARGET_SSE && TARGET_64BIT) |
46ed7963 JH |
4676 | { |
4677 | rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode); | |
4678 | emit_insn (gen_fix_truncsfdi_sse (out, operands[1])); | |
4679 | if (out != operands[0]) | |
4680 | emit_move_insn (operands[0], out); | |
4681 | DONE; | |
4682 | } | |
0f40f9f7 | 4683 | }) |
e075ae69 | 4684 | |
22fb740d JH |
4685 | ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description |
4686 | ;; of the machinery. | |
4687 | (define_insn_and_split "*fix_truncdi_1" | |
4688 | [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") | |
4689 | (fix:DI (match_operand 1 "register_operand" "f,f")))] | |
4690 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4691 | && !reload_completed && !reload_in_progress | |
4692 | && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" | |
4693 | "#" | |
14f73b5a | 4694 | "&& 1" |
22fb740d JH |
4695 | [(const_int 0)] |
4696 | { | |
4697 | operands[2] = assign_386_stack_local (HImode, 1); | |
4698 | operands[3] = assign_386_stack_local (HImode, 2); | |
4699 | if (memory_operand (operands[0], VOIDmode)) | |
4700 | emit_insn (gen_fix_truncdi_memory (operands[0], operands[1], | |
4701 | operands[2], operands[3])); | |
4702 | else | |
4703 | { | |
4704 | operands[4] = assign_386_stack_local (DImode, 0); | |
4705 | emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1], | |
4706 | operands[2], operands[3], | |
4707 | operands[4])); | |
4708 | } | |
4709 | DONE; | |
4710 | } | |
4711 | [(set_attr "type" "fistp")]) | |
4712 | ||
4713 | (define_insn "fix_truncdi_nomemory" | |
c76aab11 | 4714 | [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") |
e075ae69 | 4715 | (fix:DI (match_operand 1 "register_operand" "f,f"))) |
7a2e09f4 JH |
4716 | (use (match_operand:HI 2 "memory_operand" "m,m")) |
4717 | (use (match_operand:HI 3 "memory_operand" "m,m")) | |
4718 | (clobber (match_operand:DI 4 "memory_operand" "=m,m")) | |
22fb740d | 4719 | (clobber (match_scratch:DF 5 "=&1f,&1f"))] |
46ed7963 | 4720 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) |
22fb740d JH |
4721 | && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" |
4722 | "#" | |
4723 | [(set_attr "type" "fistp")]) | |
4724 | ||
4725 | (define_insn "fix_truncdi_memory" | |
4726 | [(set (match_operand:DI 0 "memory_operand" "=m") | |
4727 | (fix:DI (match_operand 1 "register_operand" "f"))) | |
4728 | (use (match_operand:HI 2 "memory_operand" "m")) | |
4729 | (use (match_operand:HI 3 "memory_operand" "m")) | |
4730 | (clobber (match_scratch:DF 4 "=&1f"))] | |
4731 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4732 | && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" | |
4733 | "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);" | |
4734 | [(set_attr "type" "fistp")]) | |
53b5ce19 | 4735 | |
e075ae69 RH |
4736 | (define_split |
4737 | [(set (match_operand:DI 0 "register_operand" "") | |
4738 | (fix:DI (match_operand 1 "register_operand" ""))) | |
7a2e09f4 JH |
4739 | (use (match_operand:HI 2 "memory_operand" "")) |
4740 | (use (match_operand:HI 3 "memory_operand" "")) | |
4741 | (clobber (match_operand:DI 4 "memory_operand" "")) | |
a05924f9 | 4742 | (clobber (match_scratch 5 ""))] |
7a2e09f4 JH |
4743 | "reload_completed" |
4744 | [(parallel [(set (match_dup 4) (fix:DI (match_dup 1))) | |
4745 | (use (match_dup 2)) | |
4746 | (use (match_dup 3)) | |
e075ae69 | 4747 | (clobber (match_dup 5))]) |
7a2e09f4 | 4748 | (set (match_dup 0) (match_dup 4))] |
53b5ce19 JW |
4749 | "") |
4750 | ||
22fb740d JH |
4751 | (define_split |
4752 | [(set (match_operand:DI 0 "memory_operand" "") | |
4753 | (fix:DI (match_operand 1 "register_operand" ""))) | |
4754 | (use (match_operand:HI 2 "memory_operand" "")) | |
4755 | (use (match_operand:HI 3 "memory_operand" "")) | |
4756 | (clobber (match_operand:DI 4 "memory_operand" "")) | |
4757 | (clobber (match_scratch 5 ""))] | |
4758 | "reload_completed" | |
4759 | [(parallel [(set (match_dup 0) (fix:DI (match_dup 1))) | |
4760 | (use (match_dup 2)) | |
4761 | (use (match_dup 3)) | |
4762 | (clobber (match_dup 5))])] | |
4763 | "") | |
4764 | ||
46ed7963 JH |
4765 | ;; When SSE available, it is always faster to use it! |
4766 | (define_insn "fix_truncsfdi_sse" | |
4767 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4768 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))] | |
1b0c37d7 | 4769 | "TARGET_64BIT && TARGET_SSE" |
0f40f9f7 | 4770 | "cvttss2si{q}\t{%1, %0|%0, %1}" |
46ed7963 JH |
4771 | [(set_attr "type" "sse")]) |
4772 | ||
4773 | (define_insn "fix_truncdfdi_sse" | |
4774 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4775 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))] | |
1b0c37d7 | 4776 | "TARGET_64BIT && TARGET_SSE2" |
0f40f9f7 | 4777 | "cvttsd2si{q}\t{%1, %0|%0, %1}" |
46ed7963 JH |
4778 | [(set_attr "type" "sse")]) |
4779 | ||
e075ae69 | 4780 | ;; Signed conversion to SImode. |
53b5ce19 | 4781 | |
e075ae69 | 4782 | (define_expand "fix_truncxfsi2" |
22fb740d JH |
4783 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
4784 | (fix:SI (match_operand:XF 1 "register_operand" "")))] | |
1b0c37d7 | 4785 | "!TARGET_64BIT && TARGET_80387" |
22fb740d | 4786 | "") |
53b5ce19 | 4787 | |
2b589241 | 4788 | (define_expand "fix_trunctfsi2" |
22fb740d JH |
4789 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
4790 | (fix:SI (match_operand:TF 1 "register_operand" "")))] | |
2b589241 | 4791 | "TARGET_80387" |
22fb740d | 4792 | "") |
2b589241 | 4793 | |
e075ae69 | 4794 | (define_expand "fix_truncdfsi2" |
22fb740d JH |
4795 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
4796 | (fix:SI (match_operand:DF 1 "register_operand" "")))] | |
42a0aa6f | 4797 | "TARGET_80387 || TARGET_SSE2" |
42a0aa6f JH |
4798 | { |
4799 | if (TARGET_SSE2) | |
4800 | { | |
ca9a9b12 | 4801 | rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); |
b1675dbd JH |
4802 | emit_insn (gen_fix_truncdfsi_sse (out, operands[1])); |
4803 | if (out != operands[0]) | |
4804 | emit_move_insn (operands[0], out); | |
42a0aa6f JH |
4805 | DONE; |
4806 | } | |
0f40f9f7 | 4807 | }) |
886c62d1 | 4808 | |
e075ae69 | 4809 | (define_expand "fix_truncsfsi2" |
22fb740d JH |
4810 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
4811 | (fix:SI (match_operand:SF 1 "register_operand" "")))] | |
42a0aa6f | 4812 | "TARGET_80387 || TARGET_SSE" |
42a0aa6f | 4813 | { |
22fb740d | 4814 | if (TARGET_SSE) |
42a0aa6f | 4815 | { |
ca9a9b12 | 4816 | rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); |
46ed7963 | 4817 | emit_insn (gen_fix_truncsfsi_sse (out, operands[1])); |
b1675dbd JH |
4818 | if (out != operands[0]) |
4819 | emit_move_insn (operands[0], out); | |
42a0aa6f JH |
4820 | DONE; |
4821 | } | |
0f40f9f7 | 4822 | }) |
e075ae69 | 4823 | |
22fb740d JH |
4824 | ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description |
4825 | ;; of the machinery. | |
4826 | (define_insn_and_split "*fix_truncsi_1" | |
4827 | [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r") | |
4828 | (fix:SI (match_operand 1 "register_operand" "f,f")))] | |
4829 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4830 | && !reload_completed && !reload_in_progress | |
4831 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" | |
4832 | "#" | |
ab75d1f1 | 4833 | "&& 1" |
22fb740d JH |
4834 | [(const_int 0)] |
4835 | { | |
4836 | operands[2] = assign_386_stack_local (HImode, 1); | |
4837 | operands[3] = assign_386_stack_local (HImode, 2); | |
4838 | if (memory_operand (operands[0], VOIDmode)) | |
4839 | emit_insn (gen_fix_truncsi_memory (operands[0], operands[1], | |
4840 | operands[2], operands[3])); | |
4841 | else | |
4842 | { | |
4843 | operands[4] = assign_386_stack_local (SImode, 0); | |
4844 | emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1], | |
4845 | operands[2], operands[3], | |
4846 | operands[4])); | |
4847 | } | |
4848 | DONE; | |
4849 | } | |
4850 | [(set_attr "type" "fistp")]) | |
4851 | ||
4852 | (define_insn "fix_truncsi_nomemory" | |
c76aab11 | 4853 | [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r") |
e075ae69 | 4854 | (fix:SI (match_operand 1 "register_operand" "f,f"))) |
7a2e09f4 JH |
4855 | (use (match_operand:HI 2 "memory_operand" "m,m")) |
4856 | (use (match_operand:HI 3 "memory_operand" "m,m")) | |
4857 | (clobber (match_operand:SI 4 "memory_operand" "=m,m"))] | |
42a0aa6f | 4858 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) |
22fb740d JH |
4859 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" |
4860 | "#" | |
4861 | [(set_attr "type" "fistp")]) | |
4862 | ||
4863 | (define_insn "fix_truncsi_memory" | |
4864 | [(set (match_operand:SI 0 "memory_operand" "=m") | |
4865 | (fix:SI (match_operand 1 "register_operand" "f"))) | |
4866 | (use (match_operand:HI 2 "memory_operand" "m")) | |
4867 | (use (match_operand:HI 3 "memory_operand" "m"))] | |
4868 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4869 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" | |
e075ae69 | 4870 | "* return output_fix_trunc (insn, operands);" |
22fb740d | 4871 | [(set_attr "type" "fistp")]) |
bc725565 | 4872 | |
42a0aa6f JH |
4873 | ;; When SSE available, it is always faster to use it! |
4874 | (define_insn "fix_truncsfsi_sse" | |
4875 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4876 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))] | |
4877 | "TARGET_SSE" | |
0f40f9f7 | 4878 | "cvttss2si\t{%1, %0|%0, %1}" |
42a0aa6f JH |
4879 | [(set_attr "type" "sse")]) |
4880 | ||
4881 | (define_insn "fix_truncdfsi_sse" | |
4882 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4883 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))] | |
4884 | "TARGET_SSE2" | |
0f40f9f7 | 4885 | "cvttsd2si\t{%1, %0|%0, %1}" |
42a0aa6f JH |
4886 | [(set_attr "type" "sse")]) |
4887 | ||
e075ae69 RH |
4888 | (define_split |
4889 | [(set (match_operand:SI 0 "register_operand" "") | |
4890 | (fix:SI (match_operand 1 "register_operand" ""))) | |
7a2e09f4 JH |
4891 | (use (match_operand:HI 2 "memory_operand" "")) |
4892 | (use (match_operand:HI 3 "memory_operand" "")) | |
4893 | (clobber (match_operand:SI 4 "memory_operand" ""))] | |
e075ae69 | 4894 | "reload_completed" |
7a2e09f4 JH |
4895 | [(parallel [(set (match_dup 4) (fix:SI (match_dup 1))) |
4896 | (use (match_dup 2)) | |
22fb740d | 4897 | (use (match_dup 3))]) |
7a2e09f4 | 4898 | (set (match_dup 0) (match_dup 4))] |
bc725565 | 4899 | "") |
4fb21e90 | 4900 | |
22fb740d JH |
4901 | (define_split |
4902 | [(set (match_operand:SI 0 "memory_operand" "") | |
4903 | (fix:SI (match_operand 1 "register_operand" ""))) | |
4904 | (use (match_operand:HI 2 "memory_operand" "")) | |
4905 | (use (match_operand:HI 3 "memory_operand" "")) | |
4906 | (clobber (match_operand:SI 4 "memory_operand" ""))] | |
4907 | "reload_completed" | |
4908 | [(parallel [(set (match_dup 0) (fix:SI (match_dup 1))) | |
4909 | (use (match_dup 2)) | |
4910 | (use (match_dup 3))])] | |
4911 | "") | |
4912 | ||
46d21d2c JW |
4913 | ;; Signed conversion to HImode. |
4914 | ||
4915 | (define_expand "fix_truncxfhi2" | |
22fb740d JH |
4916 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
4917 | (fix:HI (match_operand:XF 1 "register_operand" "")))] | |
1b0c37d7 | 4918 | "!TARGET_64BIT && TARGET_80387" |
22fb740d | 4919 | "") |
46d21d2c | 4920 | |
2b589241 | 4921 | (define_expand "fix_trunctfhi2" |
22fb740d JH |
4922 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
4923 | (fix:HI (match_operand:TF 1 "register_operand" "")))] | |
2b589241 | 4924 | "TARGET_80387" |
22fb740d | 4925 | "") |
2b589241 | 4926 | |
46d21d2c | 4927 | (define_expand "fix_truncdfhi2" |
22fb740d JH |
4928 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
4929 | (fix:HI (match_operand:DF 1 "register_operand" "")))] | |
42a0aa6f | 4930 | "TARGET_80387 && !TARGET_SSE2" |
22fb740d | 4931 | "") |
46d21d2c JW |
4932 | |
4933 | (define_expand "fix_truncsfhi2" | |
22fb740d JH |
4934 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
4935 | (fix:HI (match_operand:SF 1 "register_operand" "")))] | |
42a0aa6f | 4936 | "TARGET_80387 && !TARGET_SSE" |
22fb740d JH |
4937 | "") |
4938 | ||
4939 | ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description | |
4940 | ;; of the machinery. | |
4941 | (define_insn_and_split "*fix_trunchi_1" | |
4942 | [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r") | |
4943 | (fix:HI (match_operand 1 "register_operand" "f,f")))] | |
4944 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4945 | && !reload_completed && !reload_in_progress | |
4946 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" | |
4947 | "#" | |
4948 | "" | |
4949 | [(const_int 0)] | |
4950 | { | |
4951 | operands[2] = assign_386_stack_local (HImode, 1); | |
4952 | operands[3] = assign_386_stack_local (HImode, 2); | |
4953 | if (memory_operand (operands[0], VOIDmode)) | |
4954 | emit_insn (gen_fix_trunchi_memory (operands[0], operands[1], | |
4955 | operands[2], operands[3])); | |
4956 | else | |
4957 | { | |
4958 | operands[4] = assign_386_stack_local (HImode, 0); | |
4959 | emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1], | |
4960 | operands[2], operands[3], | |
4961 | operands[4])); | |
4962 | } | |
4963 | DONE; | |
4964 | } | |
4965 | [(set_attr "type" "fistp")]) | |
46d21d2c | 4966 | |
22fb740d | 4967 | (define_insn "fix_trunchi_nomemory" |
46d21d2c JW |
4968 | [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r") |
4969 | (fix:HI (match_operand 1 "register_operand" "f,f"))) | |
7a2e09f4 JH |
4970 | (use (match_operand:HI 2 "memory_operand" "m,m")) |
4971 | (use (match_operand:HI 3 "memory_operand" "m,m")) | |
4972 | (clobber (match_operand:HI 4 "memory_operand" "=m,m"))] | |
42a0aa6f | 4973 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) |
22fb740d JH |
4974 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" |
4975 | "#" | |
4976 | [(set_attr "type" "fistp")]) | |
4977 | ||
4978 | (define_insn "fix_trunchi_memory" | |
4979 | [(set (match_operand:HI 0 "memory_operand" "=m") | |
4980 | (fix:HI (match_operand 1 "register_operand" "f"))) | |
4981 | (use (match_operand:HI 2 "memory_operand" "m")) | |
4982 | (use (match_operand:HI 3 "memory_operand" "m"))] | |
4983 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4984 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" | |
46d21d2c | 4985 | "* return output_fix_trunc (insn, operands);" |
22fb740d JH |
4986 | [(set_attr "type" "fistp")]) |
4987 | ||
4988 | (define_split | |
4989 | [(set (match_operand:HI 0 "memory_operand" "") | |
4990 | (fix:HI (match_operand 1 "register_operand" ""))) | |
4991 | (use (match_operand:HI 2 "memory_operand" "")) | |
4992 | (use (match_operand:HI 3 "memory_operand" "")) | |
4993 | (clobber (match_operand:HI 4 "memory_operand" ""))] | |
4994 | "reload_completed" | |
4995 | [(parallel [(set (match_dup 0) (fix:HI (match_dup 1))) | |
4996 | (use (match_dup 2)) | |
4997 | (use (match_dup 3))])] | |
4998 | "") | |
46d21d2c JW |
4999 | |
5000 | (define_split | |
5001 | [(set (match_operand:HI 0 "register_operand" "") | |
5002 | (fix:HI (match_operand 1 "register_operand" ""))) | |
7a2e09f4 JH |
5003 | (use (match_operand:HI 2 "memory_operand" "")) |
5004 | (use (match_operand:HI 3 "memory_operand" "")) | |
5005 | (clobber (match_operand:HI 4 "memory_operand" ""))] | |
46d21d2c | 5006 | "reload_completed" |
7a2e09f4 JH |
5007 | [(parallel [(set (match_dup 4) (fix:HI (match_dup 1))) |
5008 | (use (match_dup 2)) | |
5009 | (use (match_dup 3)) | |
46d21d2c | 5010 | (clobber (match_dup 4))]) |
7a2e09f4 | 5011 | (set (match_dup 0) (match_dup 4))] |
46d21d2c JW |
5012 | "") |
5013 | ||
e075ae69 RH |
5014 | ;; %% Not used yet. |
5015 | (define_insn "x86_fnstcw_1" | |
c76aab11 RH |
5016 | [(set (match_operand:HI 0 "memory_operand" "=m") |
5017 | (unspec:HI [(reg:HI 18)] 11))] | |
e1f998ad | 5018 | "TARGET_80387" |
0f40f9f7 | 5019 | "fnstcw\t%0" |
6ef67412 JH |
5020 | [(set_attr "length" "2") |
5021 | (set_attr "mode" "HI") | |
5022 | (set_attr "i387" "1") | |
e075ae69 | 5023 | (set_attr "ppro_uops" "few")]) |
bc725565 | 5024 | |
e075ae69 RH |
5025 | (define_insn "x86_fldcw_1" |
5026 | [(set (reg:HI 18) | |
c76aab11 | 5027 | (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))] |
bc725565 | 5028 | "TARGET_80387" |
0f40f9f7 | 5029 | "fldcw\t%0" |
6ef67412 JH |
5030 | [(set_attr "length" "2") |
5031 | (set_attr "mode" "HI") | |
5032 | (set_attr "i387" "1") | |
0b5107cf | 5033 | (set_attr "athlon_decode" "vector") |
e075ae69 RH |
5034 | (set_attr "ppro_uops" "few")]) |
5035 | \f | |
5036 | ;; Conversion between fixed point and floating point. | |
886c62d1 | 5037 | |
e075ae69 RH |
5038 | ;; Even though we only accept memory inputs, the backend _really_ |
5039 | ;; wants to be able to do this between registers. | |
5040 | ||
155d8a47 JW |
5041 | (define_insn "floathisf2" |
5042 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
5043 | (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] | |
42a0aa6f | 5044 | "TARGET_80387 && !TARGET_SSE" |
155d8a47 | 5045 | "@ |
0f40f9f7 | 5046 | fild%z1\t%1 |
155d8a47 JW |
5047 | #" |
5048 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 5049 | (set_attr "mode" "SF") |
155d8a47 JW |
5050 | (set_attr "fp_int_src" "true")]) |
5051 | ||
42a0aa6f JH |
5052 | (define_expand "floatsisf2" |
5053 | [(set (match_operand:SF 0 "register_operand" "") | |
5054 | (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] | |
5055 | "TARGET_SSE || TARGET_80387" | |
5056 | "") | |
5057 | ||
5058 | (define_insn "*floatsisf2_i387" | |
5059 | [(set (match_operand:SF 0 "register_operand" "=f,?f,x") | |
5060 | (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))] | |
5061 | "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" | |
e075ae69 | 5062 | "@ |
0f40f9f7 | 5063 | fild%z1\t%1 |
42a0aa6f | 5064 | # |
0f40f9f7 | 5065 | cvtsi2ss\t{%1, %0|%0, %1}" |
42a0aa6f JH |
5066 | [(set_attr "type" "fmov,multi,sse") |
5067 | (set_attr "mode" "SF") | |
5068 | (set_attr "fp_int_src" "true")]) | |
5069 | ||
5070 | (define_insn "*floatsisf2_sse" | |
5071 | [(set (match_operand:SF 0 "register_operand" "=x") | |
5072 | (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))] | |
46ed7963 | 5073 | "TARGET_SSE" |
0f40f9f7 | 5074 | "cvtsi2ss\t{%1, %0|%0, %1}" |
42a0aa6f | 5075 | [(set_attr "type" "sse") |
6ef67412 | 5076 | (set_attr "mode" "SF") |
e075ae69 | 5077 | (set_attr "fp_int_src" "true")]) |
bc725565 | 5078 | |
46ed7963 JH |
5079 | (define_expand "floatdisf2" |
5080 | [(set (match_operand:SF 0 "register_operand" "") | |
5081 | (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] | |
1b0c37d7 | 5082 | "(TARGET_64BIT && TARGET_SSE) || TARGET_80387" |
46ed7963 JH |
5083 | "") |
5084 | ||
ef6257cd JH |
5085 | (define_insn "*floatdisf2_i387_only" |
5086 | [(set (match_operand:SF 0 "register_operand" "=f,?f") | |
5087 | (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] | |
5088 | "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)" | |
5089 | "@ | |
0f40f9f7 | 5090 | fild%z1\t%1 |
ef6257cd JH |
5091 | #" |
5092 | [(set_attr "type" "fmov,multi") | |
5093 | (set_attr "mode" "SF") | |
5094 | (set_attr "fp_int_src" "true")]) | |
5095 | ||
46ed7963 JH |
5096 | (define_insn "*floatdisf2_i387" |
5097 | [(set (match_operand:SF 0 "register_operand" "=f,?f,x") | |
5098 | (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))] | |
1b0c37d7 | 5099 | "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" |
e075ae69 | 5100 | "@ |
0f40f9f7 | 5101 | fild%z1\t%1 |
46ed7963 | 5102 | # |
0f40f9f7 | 5103 | cvtsi2ss{q}\t{%1, %0|%0, %1}" |
46ed7963 JH |
5104 | [(set_attr "type" "fmov,multi,sse") |
5105 | (set_attr "mode" "SF") | |
5106 | (set_attr "fp_int_src" "true")]) | |
5107 | ||
5108 | (define_insn "*floatdisf2_sse" | |
5109 | [(set (match_operand:SF 0 "register_operand" "=x") | |
5110 | (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))] | |
1b0c37d7 | 5111 | "TARGET_64BIT && TARGET_SSE" |
0f40f9f7 | 5112 | "cvtsi2ss{q}\t{%1, %0|%0, %1}" |
46ed7963 | 5113 | [(set_attr "type" "sse") |
6ef67412 | 5114 | (set_attr "mode" "SF") |
e075ae69 | 5115 | (set_attr "fp_int_src" "true")]) |
bc725565 | 5116 | |
155d8a47 JW |
5117 | (define_insn "floathidf2" |
5118 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
5119 | (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] | |
42a0aa6f | 5120 | "TARGET_80387 && !TARGET_SSE2" |
155d8a47 | 5121 | "@ |
0f40f9f7 | 5122 | fild%z1\t%1 |
155d8a47 JW |
5123 | #" |
5124 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 5125 | (set_attr "mode" "DF") |
155d8a47 JW |
5126 | (set_attr "fp_int_src" "true")]) |
5127 | ||
42a0aa6f JH |
5128 | (define_expand "floatsidf2" |
5129 | [(set (match_operand:DF 0 "register_operand" "") | |
5130 | (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))] | |
5131 | "" | |
5132 | "") | |
5133 | ||
5134 | (define_insn "*floatsidf2_i387" | |
5135 | [(set (match_operand:DF 0 "register_operand" "=f,?f,Y") | |
5136 | (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))] | |
5137 | "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" | |
e075ae69 | 5138 | "@ |
0f40f9f7 | 5139 | fild%z1\t%1 |
42a0aa6f | 5140 | # |
0f40f9f7 | 5141 | cvtsi2sd\t{%1, %0|%0, %1}" |
42a0aa6f JH |
5142 | [(set_attr "type" "fmov,multi,sse") |
5143 | (set_attr "mode" "DF") | |
5144 | (set_attr "fp_int_src" "true")]) | |
5145 | ||
5146 | (define_insn "*floatsidf2_sse" | |
5147 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
5148 | (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))] | |
5149 | "TARGET_SSE2" | |
0f40f9f7 | 5150 | "cvtsi2sd\t{%1, %0|%0, %1}" |
42a0aa6f | 5151 | [(set_attr "type" "sse") |
6ef67412 | 5152 | (set_attr "mode" "DF") |
e075ae69 | 5153 | (set_attr "fp_int_src" "true")]) |
e1f998ad | 5154 | |
46ed7963 JH |
5155 | (define_expand "floatdidf2" |
5156 | [(set (match_operand:DF 0 "register_operand" "") | |
5157 | (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))] | |
1b0c37d7 | 5158 | "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387" |
46ed7963 JH |
5159 | "") |
5160 | ||
ef6257cd JH |
5161 | (define_insn "*floatdidf2_i387_only" |
5162 | [(set (match_operand:DF 0 "register_operand" "=f,?f") | |
5163 | (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] | |
5164 | "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)" | |
5165 | "@ | |
0f40f9f7 | 5166 | fild%z1\t%1 |
ef6257cd JH |
5167 | #" |
5168 | [(set_attr "type" "fmov,multi") | |
5169 | (set_attr "mode" "DF") | |
5170 | (set_attr "fp_int_src" "true")]) | |
5171 | ||
46ed7963 JH |
5172 | (define_insn "*floatdidf2_i387" |
5173 | [(set (match_operand:DF 0 "register_operand" "=f,?f,Y") | |
5174 | (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))] | |
1b0c37d7 | 5175 | "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" |
e075ae69 | 5176 | "@ |
0f40f9f7 | 5177 | fild%z1\t%1 |
46ed7963 | 5178 | # |
0f40f9f7 | 5179 | cvtsi2sd{q}\t{%1, %0|%0, %1}" |
46ed7963 JH |
5180 | [(set_attr "type" "fmov,multi,sse") |
5181 | (set_attr "mode" "DF") | |
5182 | (set_attr "fp_int_src" "true")]) | |
5183 | ||
5184 | (define_insn "*floatdidf2_sse" | |
5185 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
5186 | (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))] | |
5187 | "TARGET_SSE2" | |
0f40f9f7 | 5188 | "cvtsi2sd{q}\t{%1, %0|%0, %1}" |
46ed7963 | 5189 | [(set_attr "type" "sse") |
6ef67412 | 5190 | (set_attr "mode" "DF") |
e075ae69 | 5191 | (set_attr "fp_int_src" "true")]) |
bc725565 | 5192 | |
155d8a47 JW |
5193 | (define_insn "floathixf2" |
5194 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
5195 | (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] | |
1b0c37d7 | 5196 | "!TARGET_64BIT && TARGET_80387" |
155d8a47 | 5197 | "@ |
0f40f9f7 | 5198 | fild%z1\t%1 |
155d8a47 JW |
5199 | #" |
5200 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 5201 | (set_attr "mode" "XF") |
155d8a47 JW |
5202 | (set_attr "fp_int_src" "true")]) |
5203 | ||
2b589241 JH |
5204 | (define_insn "floathitf2" |
5205 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
5206 | (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] | |
5207 | "TARGET_80387" | |
5208 | "@ | |
0f40f9f7 | 5209 | fild%z1\t%1 |
2b589241 JH |
5210 | #" |
5211 | [(set_attr "type" "fmov,multi") | |
5212 | (set_attr "mode" "XF") | |
5213 | (set_attr "fp_int_src" "true")]) | |
5214 | ||
e075ae69 RH |
5215 | (define_insn "floatsixf2" |
5216 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
5217 | (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))] | |
1b0c37d7 | 5218 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 5219 | "@ |
0f40f9f7 | 5220 | fild%z1\t%1 |
e075ae69 RH |
5221 | #" |
5222 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 5223 | (set_attr "mode" "XF") |
e075ae69 | 5224 | (set_attr "fp_int_src" "true")]) |
53b5ce19 | 5225 | |
2b589241 JH |
5226 | (define_insn "floatsitf2" |
5227 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
5228 | (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))] | |
5229 | "TARGET_80387" | |
5230 | "@ | |
0f40f9f7 | 5231 | fild%z1\t%1 |
2b589241 JH |
5232 | #" |
5233 | [(set_attr "type" "fmov,multi") | |
5234 | (set_attr "mode" "XF") | |
5235 | (set_attr "fp_int_src" "true")]) | |
5236 | ||
e075ae69 | 5237 | (define_insn "floatdixf2" |
53b5ce19 | 5238 | [(set (match_operand:XF 0 "register_operand" "=f,f") |
e075ae69 | 5239 | (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] |
1b0c37d7 | 5240 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 5241 | "@ |
0f40f9f7 | 5242 | fild%z1\t%1 |
e075ae69 RH |
5243 | #" |
5244 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 5245 | (set_attr "mode" "XF") |
e075ae69 | 5246 | (set_attr "fp_int_src" "true")]) |
53b5ce19 | 5247 | |
2b589241 JH |
5248 | (define_insn "floatditf2" |
5249 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
5250 | (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] | |
5251 | "TARGET_80387" | |
5252 | "@ | |
0f40f9f7 | 5253 | fild%z1\t%1 |
2b589241 JH |
5254 | #" |
5255 | [(set_attr "type" "fmov,multi") | |
5256 | (set_attr "mode" "XF") | |
5257 | (set_attr "fp_int_src" "true")]) | |
5258 | ||
e075ae69 | 5259 | ;; %%% Kill these when reload knows how to do it. |
155d8a47 JW |
5260 | (define_split |
5261 | [(set (match_operand 0 "register_operand" "") | |
4211a8fb | 5262 | (float (match_operand 1 "register_operand" "")))] |
bf71a4f8 JH |
5263 | "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0])) |
5264 | && FP_REG_P (operands[0])" | |
4211a8fb | 5265 | [(const_int 0)] |
4211a8fb JH |
5266 | { |
5267 | operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]); | |
5268 | operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]); | |
5269 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2])); | |
5270 | ix86_free_from_memory (GET_MODE (operands[1])); | |
5271 | DONE; | |
0f40f9f7 | 5272 | }) |
e075ae69 RH |
5273 | \f |
5274 | ;; Add instructions | |
53b5ce19 | 5275 | |
e075ae69 RH |
5276 | ;; %%% splits for addsidi3 |
5277 | ; [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5278 | ; (plus:DI (match_operand:DI 1 "general_operand" "") | |
5279 | ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))] | |
e1f998ad | 5280 | |
9b70259d JH |
5281 | (define_expand "adddi3" |
5282 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5283 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5284 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
5285 | (clobber (reg:CC 17))] | |
5286 | "" | |
5287 | "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;") | |
5288 | ||
5289 | (define_insn "*adddi3_1" | |
e075ae69 RH |
5290 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") |
5291 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
5292 | (match_operand:DI 2 "general_operand" "roiF,riF"))) | |
5293 | (clobber (reg:CC 17))] | |
9b70259d | 5294 | "!TARGET_64BIT" |
bc725565 JW |
5295 | "#") |
5296 | ||
5297 | (define_split | |
e075ae69 | 5298 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4cbfbb1b | 5299 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
e075ae69 RH |
5300 | (match_operand:DI 2 "general_operand" ""))) |
5301 | (clobber (reg:CC 17))] | |
1b0c37d7 | 5302 | "!TARGET_64BIT && reload_completed" |
7e08e190 | 5303 | [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12)) |
e075ae69 RH |
5304 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) |
5305 | (parallel [(set (match_dup 3) | |
7e08e190 | 5306 | (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
9dcbdc7e JH |
5307 | (match_dup 4)) |
5308 | (match_dup 5))) | |
e075ae69 RH |
5309 | (clobber (reg:CC 17))])] |
5310 | "split_di (operands+0, 1, operands+0, operands+3); | |
5311 | split_di (operands+1, 1, operands+1, operands+4); | |
5312 | split_di (operands+2, 1, operands+2, operands+5);") | |
5313 | ||
9b70259d JH |
5314 | (define_insn "*adddi3_carry_rex64" |
5315 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
5316 | (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0)) | |
5317 | (match_operand:DI 1 "nonimmediate_operand" "%0,0")) | |
5318 | (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) | |
5319 | (clobber (reg:CC 17))] | |
1b0c37d7 | 5320 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" |
0f40f9f7 | 5321 | "adc{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
5322 | [(set_attr "type" "alu") |
5323 | (set_attr "pent_pair" "pu") | |
5324 | (set_attr "mode" "DI") | |
5325 | (set_attr "ppro_uops" "few")]) | |
5326 | ||
5327 | (define_insn "*adddi3_cc_rex64" | |
5328 | [(set (reg:CC 17) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
5329 | (match_operand:DI 2 "x86_64_general_operand" "re,rm")] 12)) | |
5330 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
5331 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5332 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" | |
0f40f9f7 | 5333 | "add{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
5334 | [(set_attr "type" "alu") |
5335 | (set_attr "mode" "DI")]) | |
5336 | ||
7abd4e00 | 5337 | (define_insn "*addsi3_carry" |
e075ae69 | 5338 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") |
9dcbdc7e JH |
5339 | (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
5340 | (match_operand:SI 1 "nonimmediate_operand" "%0,0")) | |
5341 | (match_operand:SI 2 "general_operand" "ri,rm"))) | |
e075ae69 | 5342 | (clobber (reg:CC 17))] |
d525dfdf | 5343 | "ix86_binary_operator_ok (PLUS, SImode, operands)" |
0f40f9f7 | 5344 | "adc{l}\t{%2, %0|%0, %2}" |
e075ae69 RH |
5345 | [(set_attr "type" "alu") |
5346 | (set_attr "pent_pair" "pu") | |
6ef67412 | 5347 | (set_attr "mode" "SI") |
e075ae69 | 5348 | (set_attr "ppro_uops" "few")]) |
4fb21e90 | 5349 | |
9b70259d JH |
5350 | (define_insn "*addsi3_carry_zext" |
5351 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5352 | (zero_extend:DI | |
5353 | (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) | |
5354 | (match_operand:SI 1 "nonimmediate_operand" "%0")) | |
5355 | (match_operand:SI 2 "general_operand" "rim")))) | |
5356 | (clobber (reg:CC 17))] | |
5357 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" | |
0f40f9f7 | 5358 | "adc{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
5359 | [(set_attr "type" "alu") |
5360 | (set_attr "pent_pair" "pu") | |
5361 | (set_attr "mode" "SI") | |
5362 | (set_attr "ppro_uops" "few")]) | |
5363 | ||
7e08e190 JH |
5364 | (define_insn "*addsi3_cc" |
5365 | [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
5366 | (match_operand:SI 2 "general_operand" "ri,rm")] 12)) | |
5367 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") | |
5368 | (plus:SI (match_dup 1) (match_dup 2)))] | |
265dab10 | 5369 | "ix86_binary_operator_ok (PLUS, SImode, operands)" |
0f40f9f7 | 5370 | "add{l}\t{%2, %0|%0, %2}" |
265dab10 | 5371 | [(set_attr "type" "alu") |
7e08e190 JH |
5372 | (set_attr "mode" "SI")]) |
5373 | ||
5374 | (define_insn "addqi3_cc" | |
5375 | [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0") | |
5376 | (match_operand:QI 2 "general_operand" "qi,qm")] 12)) | |
5377 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") | |
5378 | (plus:QI (match_dup 1) (match_dup 2)))] | |
5379 | "ix86_binary_operator_ok (PLUS, QImode, operands)" | |
0f40f9f7 | 5380 | "add{b}\t{%2, %0|%0, %2}" |
7e08e190 JH |
5381 | [(set_attr "type" "alu") |
5382 | (set_attr "mode" "QI")]) | |
265dab10 | 5383 | |
e075ae69 RH |
5384 | (define_expand "addsi3" |
5385 | [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5386 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5387 | (match_operand:SI 2 "general_operand" ""))) | |
5388 | (clobber (reg:CC 17))])] | |
5389 | "" | |
5390 | "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;") | |
886c62d1 | 5391 | |
ac62a60e | 5392 | (define_insn "*lea_1" |
e075ae69 | 5393 | [(set (match_operand:SI 0 "register_operand" "=r") |
ad678cb0 | 5394 | (match_operand:SI 1 "address_operand" "p"))] |
ac62a60e | 5395 | "!TARGET_64BIT" |
0f40f9f7 | 5396 | "lea{l}\t{%a1, %0|%0, %a1}" |
6ef67412 JH |
5397 | [(set_attr "type" "lea") |
5398 | (set_attr "mode" "SI")]) | |
2ae0f82c | 5399 | |
ac62a60e JH |
5400 | (define_insn "*lea_1_rex64" |
5401 | [(set (match_operand:SI 0 "register_operand" "=r") | |
5402 | (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))] | |
5403 | "TARGET_64BIT" | |
0f40f9f7 | 5404 | "lea{l}\t{%a1, %0|%0, %a1}" |
ac62a60e JH |
5405 | [(set_attr "type" "lea") |
5406 | (set_attr "mode" "SI")]) | |
5407 | ||
5408 | (define_insn "*lea_1_zext" | |
5409 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5410 | (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))] | |
d4f33f6c | 5411 | "TARGET_64BIT" |
0f40f9f7 | 5412 | "lea{l}\t{%a1, %k0|%k0, %a1}" |
ac62a60e JH |
5413 | [(set_attr "type" "lea") |
5414 | (set_attr "mode" "SI")]) | |
5415 | ||
5416 | (define_insn "*lea_2_rex64" | |
5417 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5418 | (match_operand:DI 1 "address_operand" "p"))] | |
5419 | "TARGET_64BIT" | |
0f40f9f7 | 5420 | "lea{q}\t{%a1, %0|%0, %a1}" |
ac62a60e JH |
5421 | [(set_attr "type" "lea") |
5422 | (set_attr "mode" "DI")]) | |
5423 | ||
58787064 JH |
5424 | ;; The lea patterns for non-Pmodes needs to be matched by several |
5425 | ;; insns converted to real lea by splitters. | |
5426 | ||
5427 | (define_insn_and_split "*lea_general_1" | |
5428 | [(set (match_operand 0 "register_operand" "=r") | |
5429 | (plus (plus (match_operand 1 "register_operand" "r") | |
5430 | (match_operand 2 "register_operand" "r")) | |
5431 | (match_operand 3 "immediate_operand" "i")))] | |
ac62a60e JH |
5432 | "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode |
5433 | || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) | |
58787064 JH |
5434 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) |
5435 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5436 | && GET_MODE (operands[0]) == GET_MODE (operands[2]) | |
5437 | && (GET_MODE (operands[0]) == GET_MODE (operands[3]) | |
5438 | || GET_MODE (operands[3]) == VOIDmode)" | |
5439 | "#" | |
cb694d2c | 5440 | "&& reload_completed" |
58787064 | 5441 | [(const_int 0)] |
58787064 JH |
5442 | { |
5443 | rtx pat; | |
5444 | operands[0] = gen_lowpart (SImode, operands[0]); | |
5445 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5446 | operands[2] = gen_lowpart (Pmode, operands[2]); | |
5447 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
5448 | pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]), | |
5449 | operands[3]); | |
5450 | if (Pmode != SImode) | |
5451 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
5452 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
5453 | DONE; | |
0f40f9f7 | 5454 | } |
58787064 JH |
5455 | [(set_attr "type" "lea") |
5456 | (set_attr "mode" "SI")]) | |
5457 | ||
ac62a60e JH |
5458 | (define_insn_and_split "*lea_general_1_zext" |
5459 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5460 | (zero_extend:DI | |
5461 | (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r") | |
5462 | (match_operand:SI 2 "register_operand" "r")) | |
5463 | (match_operand:SI 3 "immediate_operand" "i"))))] | |
5464 | "TARGET_64BIT" | |
5465 | "#" | |
5466 | "&& reload_completed" | |
5467 | [(set (match_dup 0) | |
5468 | (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1) | |
5469 | (match_dup 2)) | |
5470 | (match_dup 3)) 0)))] | |
ac62a60e JH |
5471 | { |
5472 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5473 | operands[2] = gen_lowpart (Pmode, operands[2]); | |
5474 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
0f40f9f7 | 5475 | } |
ac62a60e JH |
5476 | [(set_attr "type" "lea") |
5477 | (set_attr "mode" "SI")]) | |
5478 | ||
58787064 JH |
5479 | (define_insn_and_split "*lea_general_2" |
5480 | [(set (match_operand 0 "register_operand" "=r") | |
5481 | (plus (mult (match_operand 1 "register_operand" "r") | |
5482 | (match_operand 2 "const248_operand" "i")) | |
5483 | (match_operand 3 "nonmemory_operand" "ri")))] | |
ac62a60e JH |
5484 | "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode |
5485 | || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) | |
58787064 JH |
5486 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) |
5487 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5488 | && (GET_MODE (operands[0]) == GET_MODE (operands[3]) | |
5489 | || GET_MODE (operands[3]) == VOIDmode)" | |
5490 | "#" | |
cb694d2c | 5491 | "&& reload_completed" |
58787064 | 5492 | [(const_int 0)] |
58787064 JH |
5493 | { |
5494 | rtx pat; | |
5495 | operands[0] = gen_lowpart (SImode, operands[0]); | |
5496 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5497 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
5498 | pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]), | |
5499 | operands[3]); | |
5500 | if (Pmode != SImode) | |
5501 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
5502 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
5503 | DONE; | |
0f40f9f7 | 5504 | } |
58787064 JH |
5505 | [(set_attr "type" "lea") |
5506 | (set_attr "mode" "SI")]) | |
5507 | ||
ac62a60e JH |
5508 | (define_insn_and_split "*lea_general_2_zext" |
5509 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5510 | (zero_extend:DI | |
5511 | (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") | |
5512 | (match_operand:SI 2 "const248_operand" "n")) | |
5513 | (match_operand:SI 3 "nonmemory_operand" "ri"))))] | |
5514 | "TARGET_64BIT" | |
5515 | "#" | |
5516 | "&& reload_completed" | |
5517 | [(set (match_dup 0) | |
5518 | (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1) | |
5519 | (match_dup 2)) | |
5520 | (match_dup 3)) 0)))] | |
ac62a60e JH |
5521 | { |
5522 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5523 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
0f40f9f7 | 5524 | } |
ac62a60e JH |
5525 | [(set_attr "type" "lea") |
5526 | (set_attr "mode" "SI")]) | |
5527 | ||
58787064 JH |
5528 | (define_insn_and_split "*lea_general_3" |
5529 | [(set (match_operand 0 "register_operand" "=r") | |
5530 | (plus (plus (mult (match_operand 1 "register_operand" "r") | |
5531 | (match_operand 2 "const248_operand" "i")) | |
5532 | (match_operand 3 "register_operand" "r")) | |
5533 | (match_operand 4 "immediate_operand" "i")))] | |
ac62a60e JH |
5534 | "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode |
5535 | || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) | |
58787064 JH |
5536 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) |
5537 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5538 | && GET_MODE (operands[0]) == GET_MODE (operands[3])" | |
5539 | "#" | |
cb694d2c | 5540 | "&& reload_completed" |
58787064 | 5541 | [(const_int 0)] |
58787064 JH |
5542 | { |
5543 | rtx pat; | |
5544 | operands[0] = gen_lowpart (SImode, operands[0]); | |
5545 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5546 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
5547 | operands[4] = gen_lowpart (Pmode, operands[4]); | |
5548 | pat = gen_rtx_PLUS (Pmode, | |
5549 | gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], | |
5550 | operands[2]), | |
5551 | operands[3]), | |
5552 | operands[4]); | |
5553 | if (Pmode != SImode) | |
5554 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
5555 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
5556 | DONE; | |
0f40f9f7 | 5557 | } |
58787064 JH |
5558 | [(set_attr "type" "lea") |
5559 | (set_attr "mode" "SI")]) | |
5560 | ||
ac62a60e JH |
5561 | (define_insn_and_split "*lea_general_3_zext" |
5562 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5563 | (zero_extend:DI | |
5564 | (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") | |
5565 | (match_operand:SI 2 "const248_operand" "n")) | |
5566 | (match_operand:SI 3 "register_operand" "r")) | |
5567 | (match_operand:SI 4 "immediate_operand" "i"))))] | |
5568 | "TARGET_64BIT" | |
5569 | "#" | |
5570 | "&& reload_completed" | |
5571 | [(set (match_dup 0) | |
5572 | (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1) | |
5573 | (match_dup 2)) | |
5574 | (match_dup 3)) | |
5575 | (match_dup 4)) 0)))] | |
ac62a60e JH |
5576 | { |
5577 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5578 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
5579 | operands[4] = gen_lowpart (Pmode, operands[4]); | |
0f40f9f7 | 5580 | } |
ac62a60e JH |
5581 | [(set_attr "type" "lea") |
5582 | (set_attr "mode" "SI")]) | |
5583 | ||
9b70259d JH |
5584 | (define_insn "*adddi_1_rex64" |
5585 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r") | |
5586 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r") | |
5587 | (match_operand:DI 2 "x86_64_general_operand" "rme,re,re"))) | |
e075ae69 | 5588 | (clobber (reg:CC 17))] |
9b70259d | 5589 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" |
2ae0f82c | 5590 | { |
e075ae69 | 5591 | switch (get_attr_type (insn)) |
2ae0f82c | 5592 | { |
e075ae69 RH |
5593 | case TYPE_LEA: |
5594 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
0f40f9f7 | 5595 | return "lea{q}\t{%a2, %0|%0, %a2}"; |
2ae0f82c | 5596 | |
e075ae69 RH |
5597 | case TYPE_INCDEC: |
5598 | if (! rtx_equal_p (operands[0], operands[1])) | |
5599 | abort (); | |
5600 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5601 | return "inc{q}\t%0"; |
e075ae69 | 5602 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5603 | return "dec{q}\t%0"; |
2ae0f82c | 5604 | else |
9b70259d | 5605 | abort (); |
2ae0f82c | 5606 | |
e075ae69 RH |
5607 | default: |
5608 | if (! rtx_equal_p (operands[0], operands[1])) | |
5609 | abort (); | |
2ae0f82c | 5610 | |
e075ae69 RH |
5611 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. |
5612 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5613 | if (GET_CODE (operands[2]) == CONST_INT | |
ef6257cd | 5614 | /* Avoid overflows. */ |
0f40f9f7 | 5615 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) |
e075ae69 RH |
5616 | && (INTVAL (operands[2]) == 128 |
5617 | || (INTVAL (operands[2]) < 0 | |
5618 | && INTVAL (operands[2]) != -128))) | |
5619 | { | |
5620 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5621 | return "sub{q}\t{%2, %0|%0, %2}"; |
e075ae69 | 5622 | } |
0f40f9f7 | 5623 | return "add{q}\t{%2, %0|%0, %2}"; |
e075ae69 | 5624 | } |
0f40f9f7 | 5625 | } |
e075ae69 RH |
5626 | [(set (attr "type") |
5627 | (cond [(eq_attr "alternative" "2") | |
5628 | (const_string "lea") | |
5629 | ; Current assemblers are broken and do not allow @GOTOFF in | |
5630 | ; ought but a memory context. | |
9b70259d | 5631 | (match_operand:DI 2 "pic_symbolic_operand" "") |
e075ae69 | 5632 | (const_string "lea") |
9b70259d | 5633 | (match_operand:DI 2 "incdec_operand" "") |
e075ae69 RH |
5634 | (const_string "incdec") |
5635 | ] | |
6ef67412 | 5636 | (const_string "alu"))) |
9b70259d | 5637 | (set_attr "mode" "DI")]) |
e075ae69 | 5638 | |
1c27d4b2 JH |
5639 | ;; Convert lea to the lea pattern to avoid flags dependency. |
5640 | (define_split | |
9b70259d JH |
5641 | [(set (match_operand:DI 0 "register_operand" "") |
5642 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5643 | (match_operand:DI 2 "x86_64_nonmemory_operand" ""))) | |
1c27d4b2 | 5644 | (clobber (reg:CC 17))] |
1b0c37d7 | 5645 | "TARGET_64BIT && reload_completed |
abe24fb3 | 5646 | && true_regnum (operands[0]) != true_regnum (operands[1])" |
9b70259d JH |
5647 | [(set (match_dup 0) |
5648 | (plus:DI (match_dup 1) | |
5649 | (match_dup 2)))] | |
5650 | "") | |
1c27d4b2 | 5651 | |
9b70259d | 5652 | (define_insn "*adddi_2_rex64" |
16189740 RH |
5653 | [(set (reg 17) |
5654 | (compare | |
9b70259d JH |
5655 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
5656 | (match_operand:DI 2 "x86_64_general_operand" "rme,re")) | |
e075ae69 | 5657 | (const_int 0))) |
9b70259d JH |
5658 | (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") |
5659 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5660 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
5661 | && ix86_binary_operator_ok (PLUS, DImode, operands) | |
e075ae69 | 5662 | /* Current assemblers are broken and do not allow @GOTOFF in |
892a2d68 | 5663 | ought but a memory context. */ |
e075ae69 | 5664 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
886c62d1 | 5665 | { |
e075ae69 | 5666 | switch (get_attr_type (insn)) |
96f218bb | 5667 | { |
e075ae69 RH |
5668 | case TYPE_INCDEC: |
5669 | if (! rtx_equal_p (operands[0], operands[1])) | |
5670 | abort (); | |
5671 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5672 | return "inc{q}\t%0"; |
e075ae69 | 5673 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5674 | return "dec{q}\t%0"; |
96f218bb | 5675 | else |
9b70259d | 5676 | abort (); |
96f218bb | 5677 | |
e075ae69 RH |
5678 | default: |
5679 | if (! rtx_equal_p (operands[0], operands[1])) | |
5680 | abort (); | |
9b70259d JH |
5681 | /* ???? We ought to handle there the 32bit case too |
5682 | - do we need new constrant? */ | |
e075ae69 RH |
5683 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. |
5684 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5685 | if (GET_CODE (operands[2]) == CONST_INT | |
ef6257cd | 5686 | /* Avoid overflows. */ |
0f40f9f7 | 5687 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) |
e075ae69 RH |
5688 | && (INTVAL (operands[2]) == 128 |
5689 | || (INTVAL (operands[2]) < 0 | |
5690 | && INTVAL (operands[2]) != -128))) | |
5691 | { | |
5692 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5693 | return "sub{q}\t{%2, %0|%0, %2}"; |
e075ae69 | 5694 | } |
0f40f9f7 | 5695 | return "add{q}\t{%2, %0|%0, %2}"; |
9c530261 | 5696 | } |
0f40f9f7 | 5697 | } |
e075ae69 | 5698 | [(set (attr "type") |
9b70259d | 5699 | (if_then_else (match_operand:DI 2 "incdec_operand" "") |
e075ae69 | 5700 | (const_string "incdec") |
6ef67412 | 5701 | (const_string "alu"))) |
9b70259d | 5702 | (set_attr "mode" "DI")]) |
e075ae69 | 5703 | |
e74061a9 | 5704 | (define_insn "*adddi_3_rex64" |
d90ffc8d | 5705 | [(set (reg 17) |
9b70259d JH |
5706 | (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme")) |
5707 | (match_operand:DI 1 "x86_64_general_operand" "%0"))) | |
5708 | (clobber (match_scratch:DI 0 "=r"))] | |
e74061a9 JH |
5709 | "TARGET_64BIT |
5710 | && ix86_match_ccmode (insn, CCZmode) | |
d90ffc8d JH |
5711 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) |
5712 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 5713 | ought but a memory context. */ |
d90ffc8d | 5714 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
d90ffc8d JH |
5715 | { |
5716 | switch (get_attr_type (insn)) | |
5717 | { | |
5718 | case TYPE_INCDEC: | |
5719 | if (! rtx_equal_p (operands[0], operands[1])) | |
5720 | abort (); | |
5721 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5722 | return "inc{q}\t%0"; |
d90ffc8d | 5723 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5724 | return "dec{q}\t%0"; |
d90ffc8d | 5725 | else |
9b70259d | 5726 | abort (); |
d90ffc8d JH |
5727 | |
5728 | default: | |
5729 | if (! rtx_equal_p (operands[0], operands[1])) | |
5730 | abort (); | |
9b70259d JH |
5731 | /* ???? We ought to handle there the 32bit case too |
5732 | - do we need new constrant? */ | |
d90ffc8d JH |
5733 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. |
5734 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5735 | if (GET_CODE (operands[2]) == CONST_INT | |
ef6257cd | 5736 | /* Avoid overflows. */ |
0f40f9f7 | 5737 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) |
d90ffc8d JH |
5738 | && (INTVAL (operands[2]) == 128 |
5739 | || (INTVAL (operands[2]) < 0 | |
5740 | && INTVAL (operands[2]) != -128))) | |
5741 | { | |
5742 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5743 | return "sub{q}\t{%2, %0|%0, %2}"; |
d90ffc8d | 5744 | } |
0f40f9f7 | 5745 | return "add{q}\t{%2, %0|%0, %2}"; |
d90ffc8d | 5746 | } |
0f40f9f7 | 5747 | } |
d90ffc8d | 5748 | [(set (attr "type") |
9b70259d | 5749 | (if_then_else (match_operand:DI 2 "incdec_operand" "") |
d90ffc8d JH |
5750 | (const_string "incdec") |
5751 | (const_string "alu"))) | |
9b70259d | 5752 | (set_attr "mode" "DI")]) |
d90ffc8d | 5753 | |
9b70259d | 5754 | ; For comparisons against 1, -1 and 128, we may generate better code |
7e08e190 JH |
5755 | ; by converting cmp to add, inc or dec as done by peephole2. This pattern |
5756 | ; is matched then. We can't accept general immediate, because for | |
5757 | ; case of overflows, the result is messed up. | |
9b70259d | 5758 | ; This pattern also don't hold of 0x8000000000000000, since the value overflows |
7e08e190 | 5759 | ; when negated. |
d6a7951f | 5760 | ; Also carry flag is reversed compared to cmp, so this conversion is valid |
7e08e190 | 5761 | ; only for comparisons not depending on it. |
e74061a9 | 5762 | (define_insn "*adddi_4_rex64" |
9076b9c1 | 5763 | [(set (reg 17) |
9b70259d JH |
5764 | (compare (match_operand:DI 1 "nonimmediate_operand" "0") |
5765 | (match_operand:DI 2 "x86_64_immediate_operand" "e"))) | |
5766 | (clobber (match_scratch:DI 0 "=rm"))] | |
e74061a9 JH |
5767 | "TARGET_64BIT |
5768 | && ix86_match_ccmode (insn, CCGCmode)" | |
7e08e190 JH |
5769 | { |
5770 | switch (get_attr_type (insn)) | |
5771 | { | |
5772 | case TYPE_INCDEC: | |
5773 | if (operands[2] == constm1_rtx) | |
0f40f9f7 | 5774 | return "inc{q}\t%0"; |
7e08e190 | 5775 | else if (operands[2] == const1_rtx) |
0f40f9f7 | 5776 | return "dec{q}\t%0"; |
7e08e190 JH |
5777 | else |
5778 | abort(); | |
e075ae69 | 5779 | |
7e08e190 JH |
5780 | default: |
5781 | if (! rtx_equal_p (operands[0], operands[1])) | |
5782 | abort (); | |
5783 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5784 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5785 | if ((INTVAL (operands[2]) == -128 | |
5786 | || (INTVAL (operands[2]) > 0 | |
ef6257cd JH |
5787 | && INTVAL (operands[2]) != 128)) |
5788 | /* Avoid overflows. */ | |
0f40f9f7 ZW |
5789 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))) |
5790 | return "sub{q}\t{%2, %0|%0, %2}"; | |
7e08e190 | 5791 | operands[2] = GEN_INT (-INTVAL (operands[2])); |
0f40f9f7 | 5792 | return "add{q}\t{%2, %0|%0, %2}"; |
7e08e190 | 5793 | } |
0f40f9f7 | 5794 | } |
7e08e190 | 5795 | [(set (attr "type") |
9b70259d | 5796 | (if_then_else (match_operand:DI 2 "incdec_operand" "") |
7e08e190 JH |
5797 | (const_string "incdec") |
5798 | (const_string "alu"))) | |
9b70259d | 5799 | (set_attr "mode" "DI")]) |
d90ffc8d | 5800 | |
e74061a9 | 5801 | (define_insn "*adddi_5_rex64" |
9076b9c1 JH |
5802 | [(set (reg 17) |
5803 | (compare | |
9b70259d JH |
5804 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5805 | (match_operand:DI 2 "x86_64_general_operand" "rme")) | |
9076b9c1 | 5806 | (const_int 0))) |
9b70259d | 5807 | (clobber (match_scratch:DI 0 "=r"))] |
e74061a9 JH |
5808 | "TARGET_64BIT |
5809 | && ix86_match_ccmode (insn, CCGOCmode) | |
9076b9c1 JH |
5810 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) |
5811 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 5812 | ought but a memory context. */ |
9076b9c1 | 5813 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9076b9c1 JH |
5814 | { |
5815 | switch (get_attr_type (insn)) | |
5816 | { | |
5817 | case TYPE_INCDEC: | |
5818 | if (! rtx_equal_p (operands[0], operands[1])) | |
5819 | abort (); | |
5820 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5821 | return "inc{q}\t%0"; |
9076b9c1 | 5822 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5823 | return "dec{q}\t%0"; |
9076b9c1 JH |
5824 | else |
5825 | abort(); | |
5826 | ||
5827 | default: | |
5828 | if (! rtx_equal_p (operands[0], operands[1])) | |
5829 | abort (); | |
5830 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5831 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5832 | if (GET_CODE (operands[2]) == CONST_INT | |
ef6257cd | 5833 | /* Avoid overflows. */ |
0f40f9f7 | 5834 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) |
9076b9c1 JH |
5835 | && (INTVAL (operands[2]) == 128 |
5836 | || (INTVAL (operands[2]) < 0 | |
5837 | && INTVAL (operands[2]) != -128))) | |
5838 | { | |
5839 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5840 | return "sub{q}\t{%2, %0|%0, %2}"; |
9076b9c1 | 5841 | } |
0f40f9f7 | 5842 | return "add{q}\t{%2, %0|%0, %2}"; |
9076b9c1 | 5843 | } |
0f40f9f7 | 5844 | } |
9076b9c1 | 5845 | [(set (attr "type") |
9b70259d | 5846 | (if_then_else (match_operand:DI 2 "incdec_operand" "") |
9076b9c1 JH |
5847 | (const_string "incdec") |
5848 | (const_string "alu"))) | |
9b70259d | 5849 | (set_attr "mode" "DI")]) |
2ae0f82c | 5850 | |
e075ae69 | 5851 | |
9b70259d JH |
5852 | (define_insn "*addsi_1" |
5853 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r") | |
5854 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r") | |
5855 | (match_operand:SI 2 "general_operand" "rmni,rni,rni"))) | |
58787064 | 5856 | (clobber (reg:CC 17))] |
9b70259d | 5857 | "ix86_binary_operator_ok (PLUS, SImode, operands)" |
58787064 JH |
5858 | { |
5859 | switch (get_attr_type (insn)) | |
5860 | { | |
5861 | case TYPE_LEA: | |
9b70259d | 5862 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); |
0f40f9f7 | 5863 | return "lea{l}\t{%a2, %0|%0, %a2}"; |
9b70259d | 5864 | |
58787064 | 5865 | case TYPE_INCDEC: |
9b70259d JH |
5866 | if (! rtx_equal_p (operands[0], operands[1])) |
5867 | abort (); | |
58787064 | 5868 | if (operands[2] == const1_rtx) |
0f40f9f7 | 5869 | return "inc{l}\t%0"; |
9b70259d | 5870 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5871 | return "dec{l}\t%0"; |
9b70259d JH |
5872 | else |
5873 | abort(); | |
58787064 JH |
5874 | |
5875 | default: | |
9b70259d JH |
5876 | if (! rtx_equal_p (operands[0], operands[1])) |
5877 | abort (); | |
5878 | ||
58787064 JH |
5879 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. |
5880 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5881 | if (GET_CODE (operands[2]) == CONST_INT | |
5882 | && (INTVAL (operands[2]) == 128 | |
5883 | || (INTVAL (operands[2]) < 0 | |
5884 | && INTVAL (operands[2]) != -128))) | |
9b70259d JH |
5885 | { |
5886 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5887 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5888 | } |
0f40f9f7 | 5889 | return "add{l}\t{%2, %0|%0, %2}"; |
58787064 | 5890 | } |
0f40f9f7 | 5891 | } |
58787064 | 5892 | [(set (attr "type") |
9b70259d JH |
5893 | (cond [(eq_attr "alternative" "2") |
5894 | (const_string "lea") | |
5895 | ; Current assemblers are broken and do not allow @GOTOFF in | |
5896 | ; ought but a memory context. | |
5897 | (match_operand:SI 2 "pic_symbolic_operand" "") | |
5898 | (const_string "lea") | |
5899 | (match_operand:SI 2 "incdec_operand" "") | |
5900 | (const_string "incdec") | |
5901 | ] | |
5902 | (const_string "alu"))) | |
5903 | (set_attr "mode" "SI")]) | |
58787064 | 5904 | |
9b70259d JH |
5905 | ;; Convert lea to the lea pattern to avoid flags dependency. |
5906 | (define_split | |
5907 | [(set (match_operand 0 "register_operand" "") | |
5908 | (plus (match_operand 1 "register_operand" "") | |
5909 | (match_operand 2 "nonmemory_operand" ""))) | |
e075ae69 | 5910 | (clobber (reg:CC 17))] |
9b70259d JH |
5911 | "reload_completed |
5912 | && true_regnum (operands[0]) != true_regnum (operands[1])" | |
5913 | [(const_int 0)] | |
9b70259d JH |
5914 | { |
5915 | rtx pat; | |
5916 | /* In -fPIC mode the constructs like (const (unspec [symbol_ref])) | |
5917 | may confuse gen_lowpart. */ | |
5918 | if (GET_MODE (operands[0]) != Pmode) | |
5919 | { | |
5920 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5921 | operands[2] = gen_lowpart (Pmode, operands[2]); | |
5922 | } | |
5923 | operands[0] = gen_lowpart (SImode, operands[0]); | |
5924 | pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]); | |
5925 | if (Pmode != SImode) | |
5926 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
5927 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
5928 | DONE; | |
0f40f9f7 | 5929 | }) |
9b70259d JH |
5930 | |
5931 | ;; It may seem that nonimmediate operand is proper one for operand 1. | |
5932 | ;; The addsi_1 pattern allows nonimmediate operand at that place and | |
5933 | ;; we take care in ix86_binary_operator_ok to not allow two memory | |
5934 | ;; operands so proper swapping will be done in reload. This allow | |
5935 | ;; patterns constructed from addsi_1 to match. | |
5936 | (define_insn "addsi_1_zext" | |
5937 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
5938 | (zero_extend:DI | |
5939 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r") | |
5940 | (match_operand:SI 2 "general_operand" "rmni,rni")))) | |
5941 | (clobber (reg:CC 17))] | |
5942 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" | |
886c62d1 | 5943 | { |
e075ae69 | 5944 | switch (get_attr_type (insn)) |
7c802a40 | 5945 | { |
9b70259d JH |
5946 | case TYPE_LEA: |
5947 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
0f40f9f7 | 5948 | return "lea{l}\t{%a2, %k0|%k0, %a2}"; |
9b70259d | 5949 | |
e075ae69 RH |
5950 | case TYPE_INCDEC: |
5951 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5952 | return "inc{l}\t%k0"; |
9b70259d | 5953 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5954 | return "dec{l}\t%k0"; |
9b70259d JH |
5955 | else |
5956 | abort(); | |
5957 | ||
5958 | default: | |
5959 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5960 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5961 | if (GET_CODE (operands[2]) == CONST_INT | |
5962 | && (INTVAL (operands[2]) == 128 | |
5963 | || (INTVAL (operands[2]) < 0 | |
5964 | && INTVAL (operands[2]) != -128))) | |
5965 | { | |
5966 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5967 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 5968 | } |
0f40f9f7 | 5969 | return "add{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 5970 | } |
0f40f9f7 | 5971 | } |
9b70259d JH |
5972 | [(set (attr "type") |
5973 | (cond [(eq_attr "alternative" "1") | |
5974 | (const_string "lea") | |
5975 | ; Current assemblers are broken and do not allow @GOTOFF in | |
5976 | ; ought but a memory context. | |
5977 | (match_operand:SI 2 "pic_symbolic_operand" "") | |
5978 | (const_string "lea") | |
5979 | (match_operand:SI 2 "incdec_operand" "") | |
5980 | (const_string "incdec") | |
5981 | ] | |
5982 | (const_string "alu"))) | |
5983 | (set_attr "mode" "SI")]) | |
5984 | ||
5985 | ;; Convert lea to the lea pattern to avoid flags dependency. | |
5986 | (define_split | |
5987 | [(set (match_operand:DI 0 "register_operand" "") | |
5988 | (zero_extend:DI | |
5989 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5990 | (match_operand:SI 2 "nonmemory_operand" "")))) | |
5991 | (clobber (reg:CC 17))] | |
5992 | "reload_completed | |
5993 | && true_regnum (operands[0]) != true_regnum (operands[1])" | |
5994 | [(set (match_dup 0) | |
5995 | (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))] | |
9b70259d JH |
5996 | { |
5997 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5998 | operands[2] = gen_lowpart (Pmode, operands[2]); | |
0f40f9f7 | 5999 | }) |
9b70259d JH |
6000 | |
6001 | (define_insn "*addsi_2" | |
6002 | [(set (reg 17) | |
6003 | (compare | |
6004 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
6005 | (match_operand:SI 2 "general_operand" "rmni,rni")) | |
6006 | (const_int 0))) | |
6007 | (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") | |
6008 | (plus:SI (match_dup 1) (match_dup 2)))] | |
6009 | "ix86_match_ccmode (insn, CCGOCmode) | |
6010 | && ix86_binary_operator_ok (PLUS, SImode, operands) | |
6011 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 6012 | ought but a memory context. */ |
9b70259d | 6013 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
6014 | { |
6015 | switch (get_attr_type (insn)) | |
6016 | { | |
6017 | case TYPE_INCDEC: | |
6018 | if (! rtx_equal_p (operands[0], operands[1])) | |
6019 | abort (); | |
6020 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6021 | return "inc{l}\t%0"; |
9b70259d | 6022 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 6023 | return "dec{l}\t%0"; |
9b70259d JH |
6024 | else |
6025 | abort(); | |
6026 | ||
6027 | default: | |
6028 | if (! rtx_equal_p (operands[0], operands[1])) | |
6029 | abort (); | |
6030 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6031 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6032 | if (GET_CODE (operands[2]) == CONST_INT | |
6033 | && (INTVAL (operands[2]) == 128 | |
6034 | || (INTVAL (operands[2]) < 0 | |
6035 | && INTVAL (operands[2]) != -128))) | |
6036 | { | |
6037 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6038 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 6039 | } |
0f40f9f7 | 6040 | return "add{l}\t{%2, %0|%0, %2}"; |
9b70259d | 6041 | } |
0f40f9f7 | 6042 | } |
9b70259d JH |
6043 | [(set (attr "type") |
6044 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
6045 | (const_string "incdec") | |
6046 | (const_string "alu"))) | |
6047 | (set_attr "mode" "SI")]) | |
6048 | ||
6049 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand | |
6050 | (define_insn "*addsi_2_zext" | |
6051 | [(set (reg 17) | |
6052 | (compare | |
6053 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
6054 | (match_operand:SI 2 "general_operand" "rmni")) | |
6055 | (const_int 0))) | |
6056 | (set (match_operand:DI 0 "register_operand" "=r") | |
6057 | (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] | |
6058 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
6059 | && ix86_binary_operator_ok (PLUS, SImode, operands) | |
6060 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 6061 | ought but a memory context. */ |
9b70259d | 6062 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
6063 | { |
6064 | switch (get_attr_type (insn)) | |
6065 | { | |
6066 | case TYPE_INCDEC: | |
6067 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6068 | return "inc{l}\t%k0"; |
9b70259d | 6069 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 6070 | return "dec{l}\t%k0"; |
9b70259d JH |
6071 | else |
6072 | abort(); | |
6073 | ||
6074 | default: | |
6075 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6076 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6077 | if (GET_CODE (operands[2]) == CONST_INT | |
6078 | && (INTVAL (operands[2]) == 128 | |
6079 | || (INTVAL (operands[2]) < 0 | |
6080 | && INTVAL (operands[2]) != -128))) | |
6081 | { | |
6082 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6083 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 6084 | } |
0f40f9f7 | 6085 | return "add{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 6086 | } |
0f40f9f7 | 6087 | } |
9b70259d JH |
6088 | [(set (attr "type") |
6089 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
6090 | (const_string "incdec") | |
6091 | (const_string "alu"))) | |
6092 | (set_attr "mode" "SI")]) | |
6093 | ||
6094 | (define_insn "*addsi_3" | |
6095 | [(set (reg 17) | |
6096 | (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni")) | |
6097 | (match_operand:SI 1 "nonimmediate_operand" "%0"))) | |
6098 | (clobber (match_scratch:SI 0 "=r"))] | |
6099 | "ix86_match_ccmode (insn, CCZmode) | |
6100 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) | |
6101 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 6102 | ought but a memory context. */ |
9b70259d | 6103 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
6104 | { |
6105 | switch (get_attr_type (insn)) | |
6106 | { | |
6107 | case TYPE_INCDEC: | |
6108 | if (! rtx_equal_p (operands[0], operands[1])) | |
6109 | abort (); | |
6110 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6111 | return "inc{l}\t%0"; |
9b70259d | 6112 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 6113 | return "dec{l}\t%0"; |
9b70259d JH |
6114 | else |
6115 | abort(); | |
6116 | ||
6117 | default: | |
6118 | if (! rtx_equal_p (operands[0], operands[1])) | |
6119 | abort (); | |
6120 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6121 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6122 | if (GET_CODE (operands[2]) == CONST_INT | |
6123 | && (INTVAL (operands[2]) == 128 | |
6124 | || (INTVAL (operands[2]) < 0 | |
6125 | && INTVAL (operands[2]) != -128))) | |
6126 | { | |
6127 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6128 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 6129 | } |
0f40f9f7 | 6130 | return "add{l}\t{%2, %0|%0, %2}"; |
9b70259d | 6131 | } |
0f40f9f7 | 6132 | } |
9b70259d JH |
6133 | [(set (attr "type") |
6134 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
6135 | (const_string "incdec") | |
6136 | (const_string "alu"))) | |
6137 | (set_attr "mode" "SI")]) | |
6138 | ||
6139 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand | |
6140 | (define_insn "*addsi_3_zext" | |
6141 | [(set (reg 17) | |
6142 | (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni")) | |
6143 | (match_operand:SI 1 "nonimmediate_operand" "%0"))) | |
6144 | (set (match_operand:DI 0 "register_operand" "=r") | |
6145 | (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] | |
6146 | "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode) | |
6147 | && ix86_binary_operator_ok (PLUS, SImode, operands) | |
6148 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 6149 | ought but a memory context. */ |
9b70259d | 6150 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
6151 | { |
6152 | switch (get_attr_type (insn)) | |
6153 | { | |
6154 | case TYPE_INCDEC: | |
6155 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6156 | return "inc{l}\t%k0"; |
9b70259d | 6157 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 6158 | return "dec{l}\t%k0"; |
9b70259d JH |
6159 | else |
6160 | abort(); | |
6161 | ||
6162 | default: | |
6163 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6164 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6165 | if (GET_CODE (operands[2]) == CONST_INT | |
6166 | && (INTVAL (operands[2]) == 128 | |
6167 | || (INTVAL (operands[2]) < 0 | |
6168 | && INTVAL (operands[2]) != -128))) | |
6169 | { | |
6170 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6171 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 6172 | } |
0f40f9f7 | 6173 | return "add{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 6174 | } |
0f40f9f7 | 6175 | } |
9b70259d JH |
6176 | [(set (attr "type") |
6177 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
6178 | (const_string "incdec") | |
6179 | (const_string "alu"))) | |
6180 | (set_attr "mode" "SI")]) | |
6181 | ||
6182 | ; For comparisons agains 1, -1 and 128, we may generate better code | |
6183 | ; by converting cmp to add, inc or dec as done by peephole2. This pattern | |
6184 | ; is matched then. We can't accept general immediate, because for | |
6185 | ; case of overflows, the result is messed up. | |
6186 | ; This pattern also don't hold of 0x80000000, since the value overflows | |
6187 | ; when negated. | |
d6a7951f | 6188 | ; Also carry flag is reversed compared to cmp, so this conversion is valid |
9b70259d JH |
6189 | ; only for comparisons not depending on it. |
6190 | (define_insn "*addsi_4" | |
6191 | [(set (reg 17) | |
6192 | (compare (match_operand:SI 1 "nonimmediate_operand" "0") | |
6193 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6194 | (clobber (match_scratch:SI 0 "=rm"))] | |
6195 | "ix86_match_ccmode (insn, CCGCmode) | |
6196 | && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000" | |
9b70259d JH |
6197 | { |
6198 | switch (get_attr_type (insn)) | |
6199 | { | |
6200 | case TYPE_INCDEC: | |
6201 | if (operands[2] == constm1_rtx) | |
0f40f9f7 | 6202 | return "inc{l}\t%0"; |
9b70259d | 6203 | else if (operands[2] == const1_rtx) |
0f40f9f7 | 6204 | return "dec{l}\t%0"; |
9b70259d JH |
6205 | else |
6206 | abort(); | |
6207 | ||
6208 | default: | |
6209 | if (! rtx_equal_p (operands[0], operands[1])) | |
6210 | abort (); | |
6211 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6212 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6213 | if ((INTVAL (operands[2]) == -128 | |
6214 | || (INTVAL (operands[2]) > 0 | |
6215 | && INTVAL (operands[2]) != 128))) | |
0f40f9f7 | 6216 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 6217 | operands[2] = GEN_INT (-INTVAL (operands[2])); |
0f40f9f7 | 6218 | return "add{l}\t{%2, %0|%0, %2}"; |
9b70259d | 6219 | } |
0f40f9f7 | 6220 | } |
9b70259d JH |
6221 | [(set (attr "type") |
6222 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
6223 | (const_string "incdec") | |
6224 | (const_string "alu"))) | |
6225 | (set_attr "mode" "SI")]) | |
6226 | ||
6227 | (define_insn "*addsi_5" | |
6228 | [(set (reg 17) | |
6229 | (compare | |
6230 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
6231 | (match_operand:SI 2 "general_operand" "rmni")) | |
6232 | (const_int 0))) | |
6233 | (clobber (match_scratch:SI 0 "=r"))] | |
6234 | "ix86_match_ccmode (insn, CCGOCmode) | |
6235 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) | |
6236 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 6237 | ought but a memory context. */ |
9b70259d | 6238 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
6239 | { |
6240 | switch (get_attr_type (insn)) | |
6241 | { | |
6242 | case TYPE_INCDEC: | |
6243 | if (! rtx_equal_p (operands[0], operands[1])) | |
6244 | abort (); | |
6245 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6246 | return "inc{l}\t%0"; |
9b70259d | 6247 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 6248 | return "dec{l}\t%0"; |
9b70259d JH |
6249 | else |
6250 | abort(); | |
6251 | ||
6252 | default: | |
6253 | if (! rtx_equal_p (operands[0], operands[1])) | |
6254 | abort (); | |
6255 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6256 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6257 | if (GET_CODE (operands[2]) == CONST_INT | |
6258 | && (INTVAL (operands[2]) == 128 | |
6259 | || (INTVAL (operands[2]) < 0 | |
6260 | && INTVAL (operands[2]) != -128))) | |
6261 | { | |
6262 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6263 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 6264 | } |
0f40f9f7 | 6265 | return "add{l}\t{%2, %0|%0, %2}"; |
9b70259d | 6266 | } |
0f40f9f7 | 6267 | } |
9b70259d JH |
6268 | [(set (attr "type") |
6269 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
6270 | (const_string "incdec") | |
6271 | (const_string "alu"))) | |
6272 | (set_attr "mode" "SI")]) | |
6273 | ||
6274 | (define_expand "addhi3" | |
6275 | [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
6276 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
6277 | (match_operand:HI 2 "general_operand" ""))) | |
6278 | (clobber (reg:CC 17))])] | |
6279 | "TARGET_HIMODE_MATH" | |
6280 | "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;") | |
6281 | ||
6282 | ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah | |
6283 | ;; type optimizations enabled by define-splits. This is not important | |
6284 | ;; for PII, and in fact harmful because of partial register stalls. | |
6285 | ||
6286 | (define_insn "*addhi_1_lea" | |
6287 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") | |
6288 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r") | |
6289 | (match_operand:HI 2 "general_operand" "ri,rm,rni"))) | |
6290 | (clobber (reg:CC 17))] | |
6291 | "!TARGET_PARTIAL_REG_STALL | |
6292 | && ix86_binary_operator_ok (PLUS, HImode, operands)" | |
9b70259d JH |
6293 | { |
6294 | switch (get_attr_type (insn)) | |
6295 | { | |
6296 | case TYPE_LEA: | |
0f40f9f7 | 6297 | return "#"; |
9b70259d JH |
6298 | case TYPE_INCDEC: |
6299 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6300 | return "inc{w}\t%0"; |
9b70259d JH |
6301 | else if (operands[2] == constm1_rtx |
6302 | || (GET_CODE (operands[2]) == CONST_INT | |
6303 | && INTVAL (operands[2]) == 65535)) | |
0f40f9f7 | 6304 | return "dec{w}\t%0"; |
9b70259d JH |
6305 | abort(); |
6306 | ||
6307 | default: | |
6308 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6309 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6310 | if (GET_CODE (operands[2]) == CONST_INT | |
6311 | && (INTVAL (operands[2]) == 128 | |
6312 | || (INTVAL (operands[2]) < 0 | |
6313 | && INTVAL (operands[2]) != -128))) | |
6314 | { | |
6315 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6316 | return "sub{w}\t{%2, %0|%0, %2}"; |
9b70259d | 6317 | } |
0f40f9f7 | 6318 | return "add{w}\t{%2, %0|%0, %2}"; |
9b70259d | 6319 | } |
0f40f9f7 | 6320 | } |
9b70259d JH |
6321 | [(set (attr "type") |
6322 | (if_then_else (eq_attr "alternative" "2") | |
6323 | (const_string "lea") | |
6324 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
6325 | (const_string "incdec") | |
6326 | (const_string "alu")))) | |
6327 | (set_attr "mode" "HI,HI,SI")]) | |
6328 | ||
6329 | (define_insn "*addhi_1" | |
6330 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") | |
6331 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
6332 | (match_operand:HI 2 "general_operand" "ri,rm"))) | |
6333 | (clobber (reg:CC 17))] | |
6334 | "TARGET_PARTIAL_REG_STALL | |
6335 | && ix86_binary_operator_ok (PLUS, HImode, operands)" | |
9b70259d JH |
6336 | { |
6337 | switch (get_attr_type (insn)) | |
6338 | { | |
6339 | case TYPE_INCDEC: | |
6340 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6341 | return "inc{w}\t%0"; |
9b70259d JH |
6342 | else if (operands[2] == constm1_rtx |
6343 | || (GET_CODE (operands[2]) == CONST_INT | |
6344 | && INTVAL (operands[2]) == 65535)) | |
0f40f9f7 | 6345 | return "dec{w}\t%0"; |
e075ae69 | 6346 | abort(); |
7c802a40 | 6347 | |
e075ae69 RH |
6348 | default: |
6349 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6350 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6351 | if (GET_CODE (operands[2]) == CONST_INT | |
6352 | && (INTVAL (operands[2]) == 128 | |
6353 | || (INTVAL (operands[2]) < 0 | |
6354 | && INTVAL (operands[2]) != -128))) | |
6355 | { | |
6356 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6357 | return "sub{w}\t{%2, %0|%0, %2}"; |
e075ae69 | 6358 | } |
0f40f9f7 | 6359 | return "add{w}\t{%2, %0|%0, %2}"; |
7c802a40 | 6360 | } |
0f40f9f7 | 6361 | } |
e075ae69 RH |
6362 | [(set (attr "type") |
6363 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
6364 | (const_string "incdec") | |
6ef67412 JH |
6365 | (const_string "alu"))) |
6366 | (set_attr "mode" "HI")]) | |
7c802a40 | 6367 | |
e075ae69 | 6368 | (define_insn "*addhi_2" |
16189740 RH |
6369 | [(set (reg 17) |
6370 | (compare | |
e075ae69 RH |
6371 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") |
6372 | (match_operand:HI 2 "general_operand" "rmni,rni")) | |
6373 | (const_int 0))) | |
6374 | (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") | |
6375 | (plus:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 6376 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 6377 | && ix86_binary_operator_ok (PLUS, HImode, operands)" |
e075ae69 RH |
6378 | { |
6379 | switch (get_attr_type (insn)) | |
b980bec0 | 6380 | { |
e075ae69 RH |
6381 | case TYPE_INCDEC: |
6382 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6383 | return "inc{w}\t%0"; |
e075ae69 RH |
6384 | else if (operands[2] == constm1_rtx |
6385 | || (GET_CODE (operands[2]) == CONST_INT | |
6386 | && INTVAL (operands[2]) == 65535)) | |
0f40f9f7 | 6387 | return "dec{w}\t%0"; |
e075ae69 | 6388 | abort(); |
b980bec0 | 6389 | |
e075ae69 RH |
6390 | default: |
6391 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6392 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6393 | if (GET_CODE (operands[2]) == CONST_INT | |
6394 | && (INTVAL (operands[2]) == 128 | |
6395 | || (INTVAL (operands[2]) < 0 | |
6396 | && INTVAL (operands[2]) != -128))) | |
6397 | { | |
6398 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6399 | return "sub{w}\t{%2, %0|%0, %2}"; |
e075ae69 | 6400 | } |
0f40f9f7 | 6401 | return "add{w}\t{%2, %0|%0, %2}"; |
b980bec0 | 6402 | } |
0f40f9f7 | 6403 | } |
e075ae69 RH |
6404 | [(set (attr "type") |
6405 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
6406 | (const_string "incdec") | |
6ef67412 JH |
6407 | (const_string "alu"))) |
6408 | (set_attr "mode" "HI")]) | |
e075ae69 RH |
6409 | |
6410 | (define_insn "*addhi_3" | |
d90ffc8d | 6411 | [(set (reg 17) |
7e08e190 JH |
6412 | (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni")) |
6413 | (match_operand:HI 1 "nonimmediate_operand" "%0"))) | |
d90ffc8d | 6414 | (clobber (match_scratch:HI 0 "=r"))] |
7e08e190 | 6415 | "ix86_match_ccmode (insn, CCZmode) |
d90ffc8d | 6416 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
d90ffc8d JH |
6417 | { |
6418 | switch (get_attr_type (insn)) | |
6419 | { | |
6420 | case TYPE_INCDEC: | |
6421 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6422 | return "inc{w}\t%0"; |
d90ffc8d JH |
6423 | else if (operands[2] == constm1_rtx |
6424 | || (GET_CODE (operands[2]) == CONST_INT | |
6425 | && INTVAL (operands[2]) == 65535)) | |
0f40f9f7 | 6426 | return "dec{w}\t%0"; |
d90ffc8d JH |
6427 | abort(); |
6428 | ||
6429 | default: | |
6430 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6431 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6432 | if (GET_CODE (operands[2]) == CONST_INT | |
6433 | && (INTVAL (operands[2]) == 128 | |
6434 | || (INTVAL (operands[2]) < 0 | |
6435 | && INTVAL (operands[2]) != -128))) | |
6436 | { | |
6437 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6438 | return "sub{w}\t{%2, %0|%0, %2}"; |
d90ffc8d | 6439 | } |
0f40f9f7 | 6440 | return "add{w}\t{%2, %0|%0, %2}"; |
d90ffc8d | 6441 | } |
0f40f9f7 | 6442 | } |
d90ffc8d JH |
6443 | [(set (attr "type") |
6444 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
6445 | (const_string "incdec") | |
6446 | (const_string "alu"))) | |
6447 | (set_attr "mode" "HI")]) | |
6448 | ||
7e08e190 | 6449 | ; See comments above addsi_3_imm for details. |
d90ffc8d | 6450 | (define_insn "*addhi_4" |
9076b9c1 | 6451 | [(set (reg 17) |
7e08e190 JH |
6452 | (compare (match_operand:HI 1 "nonimmediate_operand" "0") |
6453 | (match_operand:HI 2 "const_int_operand" "n"))) | |
6454 | (clobber (match_scratch:HI 0 "=rm"))] | |
6455 | "ix86_match_ccmode (insn, CCGCmode) | |
6456 | && (INTVAL (operands[2]) & 0xffff) != 0x8000" | |
7e08e190 JH |
6457 | { |
6458 | switch (get_attr_type (insn)) | |
6459 | { | |
6460 | case TYPE_INCDEC: | |
6461 | if (operands[2] == constm1_rtx | |
6462 | || (GET_CODE (operands[2]) == CONST_INT | |
6463 | && INTVAL (operands[2]) == 65535)) | |
0f40f9f7 | 6464 | return "inc{w}\t%0"; |
7e08e190 | 6465 | else if (operands[2] == const1_rtx) |
0f40f9f7 | 6466 | return "dec{w}\t%0"; |
7e08e190 JH |
6467 | else |
6468 | abort(); | |
6469 | ||
6470 | default: | |
6471 | if (! rtx_equal_p (operands[0], operands[1])) | |
6472 | abort (); | |
6473 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6474 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6475 | if ((INTVAL (operands[2]) == -128 | |
6476 | || (INTVAL (operands[2]) > 0 | |
6477 | && INTVAL (operands[2]) != 128))) | |
0f40f9f7 | 6478 | return "sub{w}\t{%2, %0|%0, %2}"; |
7e08e190 | 6479 | operands[2] = GEN_INT (-INTVAL (operands[2])); |
0f40f9f7 | 6480 | return "add{w}\t{%2, %0|%0, %2}"; |
7e08e190 | 6481 | } |
0f40f9f7 | 6482 | } |
7e08e190 JH |
6483 | [(set (attr "type") |
6484 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
6485 | (const_string "incdec") | |
6486 | (const_string "alu"))) | |
6487 | (set_attr "mode" "SI")]) | |
b980bec0 | 6488 | |
d90ffc8d | 6489 | |
7e08e190 | 6490 | (define_insn "*addhi_5" |
9076b9c1 JH |
6491 | [(set (reg 17) |
6492 | (compare | |
6493 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0") | |
6494 | (match_operand:HI 2 "general_operand" "rmni")) | |
6495 | (const_int 0))) | |
6496 | (clobber (match_scratch:HI 0 "=r"))] | |
6497 | "ix86_match_ccmode (insn, CCGOCmode) | |
6498 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
9076b9c1 JH |
6499 | { |
6500 | switch (get_attr_type (insn)) | |
6501 | { | |
6502 | case TYPE_INCDEC: | |
6503 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6504 | return "inc{w}\t%0"; |
9076b9c1 JH |
6505 | else if (operands[2] == constm1_rtx |
6506 | || (GET_CODE (operands[2]) == CONST_INT | |
6507 | && INTVAL (operands[2]) == 65535)) | |
0f40f9f7 | 6508 | return "dec{w}\t%0"; |
9076b9c1 JH |
6509 | abort(); |
6510 | ||
6511 | default: | |
6512 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6513 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6514 | if (GET_CODE (operands[2]) == CONST_INT | |
6515 | && (INTVAL (operands[2]) == 128 | |
6516 | || (INTVAL (operands[2]) < 0 | |
6517 | && INTVAL (operands[2]) != -128))) | |
6518 | { | |
6519 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6520 | return "sub{w}\t{%2, %0|%0, %2}"; |
9076b9c1 | 6521 | } |
0f40f9f7 | 6522 | return "add{w}\t{%2, %0|%0, %2}"; |
9076b9c1 | 6523 | } |
0f40f9f7 | 6524 | } |
9076b9c1 JH |
6525 | [(set (attr "type") |
6526 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
6527 | (const_string "incdec") | |
6528 | (const_string "alu"))) | |
6529 | (set_attr "mode" "HI")]) | |
6530 | ||
e075ae69 | 6531 | (define_expand "addqi3" |
4cbfbb1b JH |
6532 | [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") |
6533 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
e075ae69 RH |
6534 | (match_operand:QI 2 "general_operand" ""))) |
6535 | (clobber (reg:CC 17))])] | |
d9f32422 | 6536 | "TARGET_QIMODE_MATH" |
e075ae69 RH |
6537 | "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;") |
6538 | ||
6539 | ;; %%% Potential partial reg stall on alternative 2. What to do? | |
58787064 JH |
6540 | (define_insn "*addqi_1_lea" |
6541 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r") | |
6542 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r") | |
6543 | (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn"))) | |
6544 | (clobber (reg:CC 17))] | |
6545 | "!TARGET_PARTIAL_REG_STALL | |
6546 | && ix86_binary_operator_ok (PLUS, QImode, operands)" | |
58787064 JH |
6547 | { |
6548 | int widen = (which_alternative == 2); | |
6549 | switch (get_attr_type (insn)) | |
6550 | { | |
6551 | case TYPE_LEA: | |
0f40f9f7 | 6552 | return "#"; |
58787064 JH |
6553 | case TYPE_INCDEC: |
6554 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6555 | return widen ? "inc{l}\t%k0" : "inc{b}\t%0"; |
58787064 JH |
6556 | else if (operands[2] == constm1_rtx |
6557 | || (GET_CODE (operands[2]) == CONST_INT | |
6558 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6559 | return widen ? "dec{l}\t%k0" : "dec{b}\t%0"; |
58787064 JH |
6560 | abort(); |
6561 | ||
6562 | default: | |
6563 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6564 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6565 | if (GET_CODE (operands[2]) == CONST_INT | |
6566 | && (INTVAL (operands[2]) == 128 | |
6567 | || (INTVAL (operands[2]) < 0 | |
6568 | && INTVAL (operands[2]) != -128))) | |
6569 | { | |
6570 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
6571 | if (widen) | |
0f40f9f7 | 6572 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
58787064 | 6573 | else |
0f40f9f7 | 6574 | return "sub{b}\t{%2, %0|%0, %2}"; |
58787064 JH |
6575 | } |
6576 | if (widen) | |
0f40f9f7 | 6577 | return "add{l}\t{%k2, %k0|%k0, %k2}"; |
58787064 | 6578 | else |
0f40f9f7 | 6579 | return "add{b}\t{%2, %0|%0, %2}"; |
58787064 | 6580 | } |
0f40f9f7 | 6581 | } |
58787064 JH |
6582 | [(set (attr "type") |
6583 | (if_then_else (eq_attr "alternative" "3") | |
6584 | (const_string "lea") | |
adc88131 | 6585 | (if_then_else (match_operand:QI 2 "incdec_operand" "") |
58787064 JH |
6586 | (const_string "incdec") |
6587 | (const_string "alu")))) | |
adc88131 | 6588 | (set_attr "mode" "QI,QI,SI,SI")]) |
58787064 | 6589 | |
e075ae69 | 6590 | (define_insn "*addqi_1" |
7c6b971d | 6591 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") |
e075ae69 | 6592 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") |
7c6b971d | 6593 | (match_operand:QI 2 "general_operand" "qn,qmn,rn"))) |
e075ae69 | 6594 | (clobber (reg:CC 17))] |
58787064 JH |
6595 | "TARGET_PARTIAL_REG_STALL |
6596 | && ix86_binary_operator_ok (PLUS, QImode, operands)" | |
e075ae69 RH |
6597 | { |
6598 | int widen = (which_alternative == 2); | |
6599 | switch (get_attr_type (insn)) | |
5bc7cd8e | 6600 | { |
e075ae69 RH |
6601 | case TYPE_INCDEC: |
6602 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6603 | return widen ? "inc{l}\t%k0" : "inc{b}\t%0"; |
e075ae69 RH |
6604 | else if (operands[2] == constm1_rtx |
6605 | || (GET_CODE (operands[2]) == CONST_INT | |
6606 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6607 | return widen ? "dec{l}\t%k0" : "dec{b}\t%0"; |
e075ae69 | 6608 | abort(); |
5bc7cd8e | 6609 | |
e075ae69 RH |
6610 | default: |
6611 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6612 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6613 | if (GET_CODE (operands[2]) == CONST_INT | |
6614 | && (INTVAL (operands[2]) == 128 | |
6615 | || (INTVAL (operands[2]) < 0 | |
6616 | && INTVAL (operands[2]) != -128))) | |
5bc7cd8e | 6617 | { |
e075ae69 RH |
6618 | operands[2] = GEN_INT (-INTVAL (operands[2])); |
6619 | if (widen) | |
0f40f9f7 | 6620 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
e075ae69 | 6621 | else |
0f40f9f7 | 6622 | return "sub{b}\t{%2, %0|%0, %2}"; |
5bc7cd8e | 6623 | } |
e075ae69 | 6624 | if (widen) |
0f40f9f7 | 6625 | return "add{l}\t{%k2, %k0|%k0, %k2}"; |
e075ae69 | 6626 | else |
0f40f9f7 | 6627 | return "add{b}\t{%2, %0|%0, %2}"; |
5bc7cd8e | 6628 | } |
0f40f9f7 | 6629 | } |
e075ae69 RH |
6630 | [(set (attr "type") |
6631 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6632 | (const_string "incdec") | |
6ef67412 JH |
6633 | (const_string "alu"))) |
6634 | (set_attr "mode" "QI,QI,SI")]) | |
e075ae69 RH |
6635 | |
6636 | (define_insn "*addqi_2" | |
16189740 RH |
6637 | [(set (reg 17) |
6638 | (compare | |
e075ae69 RH |
6639 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") |
6640 | (match_operand:QI 2 "general_operand" "qmni,qni")) | |
6641 | (const_int 0))) | |
6642 | (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") | |
6643 | (plus:QI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 6644 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 6645 | && ix86_binary_operator_ok (PLUS, QImode, operands)" |
e075ae69 RH |
6646 | { |
6647 | switch (get_attr_type (insn)) | |
6648 | { | |
6649 | case TYPE_INCDEC: | |
6650 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6651 | return "inc{b}\t%0"; |
e075ae69 RH |
6652 | else if (operands[2] == constm1_rtx |
6653 | || (GET_CODE (operands[2]) == CONST_INT | |
6654 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6655 | return "dec{b}\t%0"; |
e075ae69 | 6656 | abort(); |
5bc7cd8e | 6657 | |
e075ae69 RH |
6658 | default: |
6659 | /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */ | |
6660 | if (GET_CODE (operands[2]) == CONST_INT | |
6661 | && INTVAL (operands[2]) < 0) | |
6662 | { | |
6663 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6664 | return "sub{b}\t{%2, %0|%0, %2}"; |
e075ae69 | 6665 | } |
0f40f9f7 | 6666 | return "add{b}\t{%2, %0|%0, %2}"; |
e075ae69 | 6667 | } |
0f40f9f7 | 6668 | } |
e075ae69 RH |
6669 | [(set (attr "type") |
6670 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6671 | (const_string "incdec") | |
6ef67412 JH |
6672 | (const_string "alu"))) |
6673 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
6674 | |
6675 | (define_insn "*addqi_3" | |
d90ffc8d | 6676 | [(set (reg 17) |
7e08e190 JH |
6677 | (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni")) |
6678 | (match_operand:QI 1 "nonimmediate_operand" "%0"))) | |
6679 | (clobber (match_scratch:QI 0 "=q"))] | |
6680 | "ix86_match_ccmode (insn, CCZmode) | |
d90ffc8d | 6681 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
d90ffc8d JH |
6682 | { |
6683 | switch (get_attr_type (insn)) | |
6684 | { | |
6685 | case TYPE_INCDEC: | |
6686 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6687 | return "inc{b}\t%0"; |
d90ffc8d JH |
6688 | else if (operands[2] == constm1_rtx |
6689 | || (GET_CODE (operands[2]) == CONST_INT | |
6690 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6691 | return "dec{b}\t%0"; |
d90ffc8d JH |
6692 | abort(); |
6693 | ||
6694 | default: | |
6695 | /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */ | |
6696 | if (GET_CODE (operands[2]) == CONST_INT | |
6697 | && INTVAL (operands[2]) < 0) | |
6698 | { | |
6699 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6700 | return "sub{b}\t{%2, %0|%0, %2}"; |
d90ffc8d | 6701 | } |
0f40f9f7 | 6702 | return "add{b}\t{%2, %0|%0, %2}"; |
d90ffc8d | 6703 | } |
0f40f9f7 | 6704 | } |
d90ffc8d JH |
6705 | [(set (attr "type") |
6706 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6707 | (const_string "incdec") | |
6708 | (const_string "alu"))) | |
6709 | (set_attr "mode" "QI")]) | |
6710 | ||
7e08e190 | 6711 | ; See comments above addsi_3_imm for details. |
d90ffc8d | 6712 | (define_insn "*addqi_4" |
9076b9c1 | 6713 | [(set (reg 17) |
7e08e190 JH |
6714 | (compare (match_operand:QI 1 "nonimmediate_operand" "0") |
6715 | (match_operand:QI 2 "const_int_operand" "n"))) | |
6716 | (clobber (match_scratch:QI 0 "=qm"))] | |
6717 | "ix86_match_ccmode (insn, CCGCmode) | |
6718 | && (INTVAL (operands[2]) & 0xff) != 0x80" | |
7e08e190 JH |
6719 | { |
6720 | switch (get_attr_type (insn)) | |
6721 | { | |
6722 | case TYPE_INCDEC: | |
6723 | if (operands[2] == constm1_rtx | |
6724 | || (GET_CODE (operands[2]) == CONST_INT | |
6725 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6726 | return "inc{b}\t%0"; |
7e08e190 | 6727 | else if (operands[2] == const1_rtx) |
0f40f9f7 | 6728 | return "dec{b}\t%0"; |
7e08e190 JH |
6729 | else |
6730 | abort(); | |
6731 | ||
6732 | default: | |
6733 | if (! rtx_equal_p (operands[0], operands[1])) | |
6734 | abort (); | |
6735 | if (INTVAL (operands[2]) < 0) | |
6736 | { | |
6737 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6738 | return "add{b}\t{%2, %0|%0, %2}"; |
7e08e190 | 6739 | } |
0f40f9f7 | 6740 | return "sub{b}\t{%2, %0|%0, %2}"; |
7e08e190 | 6741 | } |
0f40f9f7 | 6742 | } |
7e08e190 JH |
6743 | [(set (attr "type") |
6744 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
6745 | (const_string "incdec") | |
6746 | (const_string "alu"))) | |
6ef67412 | 6747 | (set_attr "mode" "QI")]) |
886c62d1 | 6748 | |
9dcbdc7e | 6749 | |
d90ffc8d | 6750 | (define_insn "*addqi_5" |
9076b9c1 JH |
6751 | [(set (reg 17) |
6752 | (compare | |
6753 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0") | |
6754 | (match_operand:QI 2 "general_operand" "qmni")) | |
6755 | (const_int 0))) | |
7e08e190 | 6756 | (clobber (match_scratch:QI 0 "=q"))] |
9076b9c1 JH |
6757 | "ix86_match_ccmode (insn, CCGOCmode) |
6758 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
9076b9c1 JH |
6759 | { |
6760 | switch (get_attr_type (insn)) | |
6761 | { | |
6762 | case TYPE_INCDEC: | |
6763 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6764 | return "inc{b}\t%0"; |
9076b9c1 JH |
6765 | else if (operands[2] == constm1_rtx |
6766 | || (GET_CODE (operands[2]) == CONST_INT | |
6767 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6768 | return "dec{b}\t%0"; |
9076b9c1 JH |
6769 | abort(); |
6770 | ||
6771 | default: | |
6772 | /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */ | |
6773 | if (GET_CODE (operands[2]) == CONST_INT | |
6774 | && INTVAL (operands[2]) < 0) | |
6775 | { | |
6776 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6777 | return "sub{b}\t{%2, %0|%0, %2}"; |
9076b9c1 | 6778 | } |
0f40f9f7 | 6779 | return "add{b}\t{%2, %0|%0, %2}"; |
9076b9c1 | 6780 | } |
0f40f9f7 | 6781 | } |
9076b9c1 JH |
6782 | [(set (attr "type") |
6783 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6784 | (const_string "incdec") | |
6785 | (const_string "alu"))) | |
6786 | (set_attr "mode" "QI")]) | |
6787 | ||
e075ae69 RH |
6788 | |
6789 | (define_insn "addqi_ext_1" | |
3522082b | 6790 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
6791 | (const_int 8) |
6792 | (const_int 8)) | |
6793 | (plus:SI | |
6794 | (zero_extract:SI | |
6795 | (match_operand 1 "ext_register_operand" "0") | |
6796 | (const_int 8) | |
6797 | (const_int 8)) | |
3522082b | 6798 | (match_operand:QI 2 "general_operand" "Qmn"))) |
e075ae69 | 6799 | (clobber (reg:CC 17))] |
d2836273 | 6800 | "!TARGET_64BIT" |
d2836273 JH |
6801 | { |
6802 | switch (get_attr_type (insn)) | |
6803 | { | |
6804 | case TYPE_INCDEC: | |
6805 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6806 | return "inc{b}\t%h0"; |
d2836273 JH |
6807 | else if (operands[2] == constm1_rtx |
6808 | || (GET_CODE (operands[2]) == CONST_INT | |
6809 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6810 | return "dec{b}\t%h0"; |
d2836273 JH |
6811 | abort(); |
6812 | ||
6813 | default: | |
0f40f9f7 | 6814 | return "add{b}\t{%2, %h0|%h0, %2}"; |
d2836273 | 6815 | } |
0f40f9f7 | 6816 | } |
d2836273 JH |
6817 | [(set (attr "type") |
6818 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6819 | (const_string "incdec") | |
6820 | (const_string "alu"))) | |
6821 | (set_attr "mode" "QI")]) | |
6822 | ||
6823 | (define_insn "*addqi_ext_1_rex64" | |
6824 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
6825 | (const_int 8) | |
6826 | (const_int 8)) | |
6827 | (plus:SI | |
6828 | (zero_extract:SI | |
6829 | (match_operand 1 "ext_register_operand" "0") | |
6830 | (const_int 8) | |
6831 | (const_int 8)) | |
6832 | (match_operand:QI 2 "nonmemory_operand" "Qn"))) | |
6833 | (clobber (reg:CC 17))] | |
6834 | "TARGET_64BIT" | |
e075ae69 RH |
6835 | { |
6836 | switch (get_attr_type (insn)) | |
6837 | { | |
6838 | case TYPE_INCDEC: | |
6839 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6840 | return "inc{b}\t%h0"; |
e075ae69 RH |
6841 | else if (operands[2] == constm1_rtx |
6842 | || (GET_CODE (operands[2]) == CONST_INT | |
6843 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6844 | return "dec{b}\t%h0"; |
e075ae69 | 6845 | abort(); |
886c62d1 | 6846 | |
e075ae69 | 6847 | default: |
0f40f9f7 | 6848 | return "add{b}\t{%2, %h0|%h0, %2}"; |
e075ae69 | 6849 | } |
0f40f9f7 | 6850 | } |
e075ae69 RH |
6851 | [(set (attr "type") |
6852 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6853 | (const_string "incdec") | |
6ef67412 JH |
6854 | (const_string "alu"))) |
6855 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
6856 | |
6857 | (define_insn "*addqi_ext_2" | |
d2836273 | 6858 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
6859 | (const_int 8) |
6860 | (const_int 8)) | |
6861 | (plus:SI | |
6862 | (zero_extract:SI | |
6863 | (match_operand 1 "ext_register_operand" "%0") | |
6864 | (const_int 8) | |
6865 | (const_int 8)) | |
6866 | (zero_extract:SI | |
d2836273 | 6867 | (match_operand 2 "ext_register_operand" "Q") |
e075ae69 RH |
6868 | (const_int 8) |
6869 | (const_int 8)))) | |
6870 | (clobber (reg:CC 17))] | |
6871 | "" | |
0f40f9f7 | 6872 | "add{b}\t{%h2, %h0|%h0, %h2}" |
6ef67412 JH |
6873 | [(set_attr "type" "alu") |
6874 | (set_attr "mode" "QI")]) | |
886c62d1 | 6875 | |
886c62d1 JVA |
6876 | ;; The patterns that match these are at the end of this file. |
6877 | ||
4fb21e90 JVA |
6878 | (define_expand "addxf3" |
6879 | [(set (match_operand:XF 0 "register_operand" "") | |
2ae0f82c SC |
6880 | (plus:XF (match_operand:XF 1 "register_operand" "") |
6881 | (match_operand:XF 2 "register_operand" "")))] | |
1b0c37d7 | 6882 | "!TARGET_64BIT && TARGET_80387" |
4fb21e90 JVA |
6883 | "") |
6884 | ||
2b589241 JH |
6885 | (define_expand "addtf3" |
6886 | [(set (match_operand:TF 0 "register_operand" "") | |
6887 | (plus:TF (match_operand:TF 1 "register_operand" "") | |
6888 | (match_operand:TF 2 "register_operand" "")))] | |
6889 | "TARGET_80387" | |
6890 | "") | |
6891 | ||
886c62d1 JVA |
6892 | (define_expand "adddf3" |
6893 | [(set (match_operand:DF 0 "register_operand" "") | |
06a964de | 6894 | (plus:DF (match_operand:DF 1 "register_operand" "") |
886c62d1 | 6895 | (match_operand:DF 2 "nonimmediate_operand" "")))] |
965f5423 | 6896 | "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" |
886c62d1 JVA |
6897 | "") |
6898 | ||
6899 | (define_expand "addsf3" | |
6900 | [(set (match_operand:SF 0 "register_operand" "") | |
06a964de | 6901 | (plus:SF (match_operand:SF 1 "register_operand" "") |
886c62d1 | 6902 | (match_operand:SF 2 "nonimmediate_operand" "")))] |
965f5423 | 6903 | "TARGET_80387 || TARGET_SSE_MATH" |
886c62d1 JVA |
6904 | "") |
6905 | \f | |
e075ae69 | 6906 | ;; Subtract instructions |
a269a03c | 6907 | |
e075ae69 | 6908 | ;; %%% splits for subsidi3 |
2ae0f82c | 6909 | |
9b70259d JH |
6910 | (define_expand "subdi3" |
6911 | [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
6912 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
6913 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
6914 | (clobber (reg:CC 17))])] | |
6915 | "" | |
6916 | "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;") | |
6917 | ||
6918 | (define_insn "*subdi3_1" | |
e075ae69 | 6919 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") |
4cbfbb1b | 6920 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") |
e075ae69 RH |
6921 | (match_operand:DI 2 "general_operand" "roiF,riF"))) |
6922 | (clobber (reg:CC 17))] | |
9b70259d | 6923 | "!TARGET_64BIT" |
e075ae69 | 6924 | "#") |
9c530261 | 6925 | |
e075ae69 RH |
6926 | (define_split |
6927 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
4cbfbb1b | 6928 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
e075ae69 RH |
6929 | (match_operand:DI 2 "general_operand" ""))) |
6930 | (clobber (reg:CC 17))] | |
1b0c37d7 | 6931 | "!TARGET_64BIT && reload_completed" |
9dcbdc7e | 6932 | [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2))) |
e075ae69 RH |
6933 | (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) |
6934 | (parallel [(set (match_dup 3) | |
6935 | (minus:SI (match_dup 4) | |
9dcbdc7e JH |
6936 | (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
6937 | (match_dup 5)))) | |
e075ae69 RH |
6938 | (clobber (reg:CC 17))])] |
6939 | "split_di (operands+0, 1, operands+0, operands+3); | |
6940 | split_di (operands+1, 1, operands+1, operands+4); | |
6941 | split_di (operands+2, 1, operands+2, operands+5);") | |
6942 | ||
9b70259d JH |
6943 | (define_insn "subdi3_carry_rex64" |
6944 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
6945 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
6946 | (plus:DI (ltu:DI (reg:CC 17) (const_int 0)) | |
6947 | (match_operand:DI 2 "x86_64_general_operand" "re,rm")))) | |
6948 | (clobber (reg:CC 17))] | |
1b0c37d7 | 6949 | "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" |
0f40f9f7 | 6950 | "sbb{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
6951 | [(set_attr "type" "alu") |
6952 | (set_attr "pent_pair" "pu") | |
6953 | (set_attr "ppro_uops" "few") | |
6954 | (set_attr "mode" "DI")]) | |
6955 | ||
6956 | (define_insn "*subdi_1_rex64" | |
6957 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
6958 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
6959 | (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) | |
6960 | (clobber (reg:CC 17))] | |
6961 | "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" | |
0f40f9f7 | 6962 | "sub{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
6963 | [(set_attr "type" "alu") |
6964 | (set_attr "mode" "DI")]) | |
6965 | ||
6966 | (define_insn "*subdi_2_rex64" | |
6967 | [(set (reg 17) | |
6968 | (compare | |
6969 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
6970 | (match_operand:DI 2 "x86_64_general_operand" "re,rm")) | |
6971 | (const_int 0))) | |
6972 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
6973 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6974 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
6975 | && ix86_binary_operator_ok (MINUS, DImode, operands)" | |
0f40f9f7 | 6976 | "sub{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
6977 | [(set_attr "type" "alu") |
6978 | (set_attr "mode" "DI")]) | |
6979 | ||
6980 | (define_insn "*subdi_3_rex63" | |
6981 | [(set (reg 17) | |
6982 | (compare (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
6983 | (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) | |
6984 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
6985 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6986 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode) | |
6987 | && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 6988 | "sub{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
6989 | [(set_attr "type" "alu") |
6990 | (set_attr "mode" "DI")]) | |
6991 | ||
6992 | ||
7e08e190 | 6993 | (define_insn "subsi3_carry" |
e075ae69 RH |
6994 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") |
6995 | (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
9dcbdc7e JH |
6996 | (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
6997 | (match_operand:SI 2 "general_operand" "ri,rm")))) | |
e075ae69 | 6998 | (clobber (reg:CC 17))] |
d525dfdf | 6999 | "ix86_binary_operator_ok (MINUS, SImode, operands)" |
0f40f9f7 | 7000 | "sbb{l}\t{%2, %0|%0, %2}" |
e075ae69 RH |
7001 | [(set_attr "type" "alu") |
7002 | (set_attr "pent_pair" "pu") | |
6ef67412 JH |
7003 | (set_attr "ppro_uops" "few") |
7004 | (set_attr "mode" "SI")]) | |
886c62d1 | 7005 | |
9b70259d JH |
7006 | (define_insn "subsi3_carry_zext" |
7007 | [(set (match_operand:DI 0 "register_operand" "=rm,r") | |
7008 | (zero_extend:DI | |
7009 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
7010 | (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) | |
7011 | (match_operand:SI 2 "general_operand" "ri,rm"))))) | |
7012 | (clobber (reg:CC 17))] | |
7013 | "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 7014 | "sbb{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
7015 | [(set_attr "type" "alu") |
7016 | (set_attr "pent_pair" "pu") | |
7017 | (set_attr "ppro_uops" "few") | |
7018 | (set_attr "mode" "SI")]) | |
7019 | ||
2ae0f82c | 7020 | (define_expand "subsi3" |
e075ae69 RH |
7021 | [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") |
7022 | (minus:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
7023 | (match_operand:SI 2 "general_operand" ""))) | |
7024 | (clobber (reg:CC 17))])] | |
886c62d1 | 7025 | "" |
e075ae69 | 7026 | "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;") |
2ae0f82c | 7027 | |
e075ae69 | 7028 | (define_insn "*subsi_1" |
2ae0f82c SC |
7029 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") |
7030 | (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
e075ae69 RH |
7031 | (match_operand:SI 2 "general_operand" "ri,rm"))) |
7032 | (clobber (reg:CC 17))] | |
7033 | "ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 7034 | "sub{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
7035 | [(set_attr "type" "alu") |
7036 | (set_attr "mode" "SI")]) | |
e075ae69 | 7037 | |
9b70259d JH |
7038 | (define_insn "*subsi_1_zext" |
7039 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7040 | (zero_extend:DI | |
7041 | (minus:SI (match_operand:SI 1 "register_operand" "0") | |
7042 | (match_operand:SI 2 "general_operand" "rim")))) | |
7043 | (clobber (reg:CC 17))] | |
7044 | "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 7045 | "sub{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
7046 | [(set_attr "type" "alu") |
7047 | (set_attr "mode" "SI")]) | |
7048 | ||
e075ae69 | 7049 | (define_insn "*subsi_2" |
16189740 RH |
7050 | [(set (reg 17) |
7051 | (compare | |
e075ae69 RH |
7052 | (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") |
7053 | (match_operand:SI 2 "general_operand" "ri,rm")) | |
7054 | (const_int 0))) | |
7055 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") | |
7056 | (minus:SI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 7057 | "ix86_match_ccmode (insn, CCGOCmode) |
d90ffc8d | 7058 | && ix86_binary_operator_ok (MINUS, SImode, operands)" |
0f40f9f7 | 7059 | "sub{l}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
7060 | [(set_attr "type" "alu") |
7061 | (set_attr "mode" "SI")]) | |
7062 | ||
9b70259d JH |
7063 | (define_insn "*subsi_2_zext" |
7064 | [(set (reg 17) | |
7065 | (compare | |
7066 | (minus:SI (match_operand:SI 1 "register_operand" "0") | |
7067 | (match_operand:SI 2 "general_operand" "rim")) | |
7068 | (const_int 0))) | |
7069 | (set (match_operand:DI 0 "register_operand" "=r") | |
7070 | (zero_extend:DI | |
7071 | (minus:SI (match_dup 1) | |
7072 | (match_dup 2))))] | |
7073 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
7074 | && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 7075 | "sub{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
7076 | [(set_attr "type" "alu") |
7077 | (set_attr "mode" "SI")]) | |
7078 | ||
d90ffc8d JH |
7079 | (define_insn "*subsi_3" |
7080 | [(set (reg 17) | |
7081 | (compare (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
7082 | (match_operand:SI 2 "general_operand" "ri,rm"))) | |
7083 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") | |
7084 | (minus:SI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
7085 | "ix86_match_ccmode (insn, CCmode) |
7086 | && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 7087 | "sub{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
7088 | [(set_attr "type" "alu") |
7089 | (set_attr "mode" "SI")]) | |
886c62d1 | 7090 | |
9b70259d JH |
7091 | (define_insn "*subsi_3_zext" |
7092 | [(set (reg 17) | |
7093 | (compare (match_operand:SI 1 "nonimmediate_operand" "0") | |
7094 | (match_operand:SI 2 "general_operand" "rim"))) | |
7095 | (set (match_operand:DI 0 "register_operand" "=r") | |
7096 | (zero_extend:DI | |
7097 | (minus:SI (match_dup 1) | |
7098 | (match_dup 2))))] | |
8362f420 | 7099 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode) |
9b70259d | 7100 | && ix86_binary_operator_ok (MINUS, SImode, operands)" |
0f40f9f7 | 7101 | "sub{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
7102 | [(set_attr "type" "alu") |
7103 | (set_attr "mode" "DI")]) | |
7104 | ||
2ae0f82c | 7105 | (define_expand "subhi3" |
4cbfbb1b | 7106 | [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") |
e075ae69 RH |
7107 | (minus:HI (match_operand:HI 1 "nonimmediate_operand" "") |
7108 | (match_operand:HI 2 "general_operand" ""))) | |
7109 | (clobber (reg:CC 17))])] | |
d9f32422 | 7110 | "TARGET_HIMODE_MATH" |
e075ae69 | 7111 | "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;") |
2ae0f82c | 7112 | |
e075ae69 | 7113 | (define_insn "*subhi_1" |
2ae0f82c | 7114 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") |
87fd1847 | 7115 | (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") |
e075ae69 RH |
7116 | (match_operand:HI 2 "general_operand" "ri,rm"))) |
7117 | (clobber (reg:CC 17))] | |
2ae0f82c | 7118 | "ix86_binary_operator_ok (MINUS, HImode, operands)" |
0f40f9f7 | 7119 | "sub{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
7120 | [(set_attr "type" "alu") |
7121 | (set_attr "mode" "HI")]) | |
e075ae69 RH |
7122 | |
7123 | (define_insn "*subhi_2" | |
16189740 RH |
7124 | [(set (reg 17) |
7125 | (compare | |
e075ae69 RH |
7126 | (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") |
7127 | (match_operand:HI 2 "general_operand" "ri,rm")) | |
7128 | (const_int 0))) | |
7129 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") | |
7130 | (minus:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 7131 | "ix86_match_ccmode (insn, CCGOCmode) |
d90ffc8d | 7132 | && ix86_binary_operator_ok (MINUS, HImode, operands)" |
0f40f9f7 | 7133 | "sub{w}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
7134 | [(set_attr "type" "alu") |
7135 | (set_attr "mode" "HI")]) | |
7136 | ||
7137 | (define_insn "*subhi_3" | |
7138 | [(set (reg 17) | |
7139 | (compare (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
7140 | (match_operand:HI 2 "general_operand" "ri,rm"))) | |
7141 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") | |
7142 | (minus:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
7143 | "ix86_match_ccmode (insn, CCmode) |
7144 | && ix86_binary_operator_ok (MINUS, HImode, operands)" | |
0f40f9f7 | 7145 | "sub{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
7146 | [(set_attr "type" "alu") |
7147 | (set_attr "mode" "HI")]) | |
886c62d1 | 7148 | |
2ae0f82c | 7149 | (define_expand "subqi3" |
4cbfbb1b JH |
7150 | [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") |
7151 | (minus:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
e075ae69 RH |
7152 | (match_operand:QI 2 "general_operand" ""))) |
7153 | (clobber (reg:CC 17))])] | |
d9f32422 | 7154 | "TARGET_QIMODE_MATH" |
e075ae69 | 7155 | "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;") |
2ae0f82c | 7156 | |
e075ae69 | 7157 | (define_insn "*subqi_1" |
2ae0f82c SC |
7158 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") |
7159 | (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
e075ae69 RH |
7160 | (match_operand:QI 2 "general_operand" "qn,qmn"))) |
7161 | (clobber (reg:CC 17))] | |
7162 | "ix86_binary_operator_ok (MINUS, QImode, operands)" | |
0f40f9f7 | 7163 | "sub{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
7164 | [(set_attr "type" "alu") |
7165 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
7166 | |
7167 | (define_insn "*subqi_2" | |
16189740 RH |
7168 | [(set (reg 17) |
7169 | (compare | |
e075ae69 RH |
7170 | (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") |
7171 | (match_operand:QI 2 "general_operand" "qi,qm")) | |
7172 | (const_int 0))) | |
7173 | (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q") | |
7174 | (minus:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 7175 | "ix86_match_ccmode (insn, CCGOCmode) |
d90ffc8d | 7176 | && ix86_binary_operator_ok (MINUS, QImode, operands)" |
0f40f9f7 | 7177 | "sub{b}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
7178 | [(set_attr "type" "alu") |
7179 | (set_attr "mode" "QI")]) | |
7180 | ||
7181 | (define_insn "*subqi_3" | |
7182 | [(set (reg 17) | |
7183 | (compare (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
7184 | (match_operand:QI 2 "general_operand" "qi,qm"))) | |
7185 | (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q") | |
7186 | (minus:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
7187 | "ix86_match_ccmode (insn, CCmode) |
7188 | && ix86_binary_operator_ok (MINUS, QImode, operands)" | |
0f40f9f7 | 7189 | "sub{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
7190 | [(set_attr "type" "alu") |
7191 | (set_attr "mode" "QI")]) | |
2ae0f82c | 7192 | |
886c62d1 JVA |
7193 | ;; The patterns that match these are at the end of this file. |
7194 | ||
4fb21e90 JVA |
7195 | (define_expand "subxf3" |
7196 | [(set (match_operand:XF 0 "register_operand" "") | |
2ae0f82c SC |
7197 | (minus:XF (match_operand:XF 1 "register_operand" "") |
7198 | (match_operand:XF 2 "register_operand" "")))] | |
1b0c37d7 | 7199 | "!TARGET_64BIT && TARGET_80387" |
4fb21e90 JVA |
7200 | "") |
7201 | ||
2b589241 JH |
7202 | (define_expand "subtf3" |
7203 | [(set (match_operand:TF 0 "register_operand" "") | |
7204 | (minus:TF (match_operand:TF 1 "register_operand" "") | |
7205 | (match_operand:TF 2 "register_operand" "")))] | |
7206 | "TARGET_80387" | |
7207 | "") | |
7208 | ||
886c62d1 JVA |
7209 | (define_expand "subdf3" |
7210 | [(set (match_operand:DF 0 "register_operand" "") | |
06a964de | 7211 | (minus:DF (match_operand:DF 1 "register_operand" "") |
886c62d1 | 7212 | (match_operand:DF 2 "nonimmediate_operand" "")))] |
965f5423 | 7213 | "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" |
886c62d1 JVA |
7214 | "") |
7215 | ||
7216 | (define_expand "subsf3" | |
7217 | [(set (match_operand:SF 0 "register_operand" "") | |
06a964de | 7218 | (minus:SF (match_operand:SF 1 "register_operand" "") |
886c62d1 | 7219 | (match_operand:SF 2 "nonimmediate_operand" "")))] |
965f5423 | 7220 | "TARGET_80387 || TARGET_SSE_MATH" |
886c62d1 JVA |
7221 | "") |
7222 | \f | |
e075ae69 | 7223 | ;; Multiply instructions |
886c62d1 | 7224 | |
9b70259d JH |
7225 | (define_expand "muldi3" |
7226 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
7227 | (mult:DI (match_operand:DI 1 "register_operand" "") | |
7228 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
7229 | (clobber (reg:CC 17))])] | |
7230 | "TARGET_64BIT" | |
7231 | "") | |
7232 | ||
7233 | (define_insn "*muldi3_1_rex64" | |
7234 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
7235 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0") | |
7236 | (match_operand:DI 2 "x86_64_general_operand" "K,e,mr"))) | |
7237 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
7238 | "TARGET_64BIT |
7239 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
9b70259d | 7240 | "@ |
0f40f9f7 ZW |
7241 | imul{q}\t{%2, %1, %0|%0, %1, %2} |
7242 | imul{q}\t{%2, %1, %0|%0, %1, %2} | |
7243 | imul{q}\t{%2, %0|%0, %2}" | |
9b70259d JH |
7244 | [(set_attr "type" "imul") |
7245 | (set_attr "prefix_0f" "0,0,1") | |
7246 | (set_attr "mode" "DI")]) | |
7247 | ||
d525dfdf JH |
7248 | (define_expand "mulsi3" |
7249 | [(parallel [(set (match_operand:SI 0 "register_operand" "") | |
7250 | (mult:SI (match_operand:SI 1 "register_operand" "") | |
7251 | (match_operand:SI 2 "general_operand" ""))) | |
7252 | (clobber (reg:CC 17))])] | |
7253 | "" | |
7254 | "") | |
7255 | ||
7256 | (define_insn "*mulsi3_1" | |
e075ae69 RH |
7257 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") |
7258 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0") | |
7259 | (match_operand:SI 2 "general_operand" "K,i,mr"))) | |
7260 | (clobber (reg:CC 17))] | |
d525dfdf | 7261 | "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" |
20819a09 MM |
7262 | ; For the {r,0,i} alternative (i.e., register <- register * immediate), |
7263 | ; there are two ways of writing the exact same machine instruction | |
7264 | ; in assembly language. One, for example, is: | |
7265 | ; | |
7266 | ; imul $12, %eax | |
7267 | ; | |
7268 | ; while the other is: | |
7269 | ; | |
7270 | ; imul $12, %eax, %eax | |
7271 | ; | |
7272 | ; The first is simply short-hand for the latter. But, some assemblers, | |
7273 | ; like the SCO OSR5 COFF assembler, don't handle the first form. | |
e075ae69 | 7274 | "@ |
0f40f9f7 ZW |
7275 | imul{l}\t{%2, %1, %0|%0, %1, %2} |
7276 | imul{l}\t{%2, %1, %0|%0, %1, %2} | |
7277 | imul{l}\t{%2, %0|%0, %2}" | |
e075ae69 | 7278 | [(set_attr "type" "imul") |
6ef67412 JH |
7279 | (set_attr "prefix_0f" "0,0,1") |
7280 | (set_attr "mode" "SI")]) | |
886c62d1 | 7281 | |
9b70259d JH |
7282 | (define_insn "*mulsi3_1_zext" |
7283 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
7284 | (zero_extend:DI | |
7285 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0") | |
7286 | (match_operand:SI 2 "general_operand" "K,i,mr")))) | |
7287 | (clobber (reg:CC 17))] | |
7288 | "TARGET_64BIT | |
7289 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
7290 | ; For the {r,0,i} alternative (i.e., register <- register * immediate), | |
7291 | ; there are two ways of writing the exact same machine instruction | |
7292 | ; in assembly language. One, for example, is: | |
7293 | ; | |
7294 | ; imul $12, %eax | |
7295 | ; | |
7296 | ; while the other is: | |
7297 | ; | |
7298 | ; imul $12, %eax, %eax | |
7299 | ; | |
7300 | ; The first is simply short-hand for the latter. But, some assemblers, | |
7301 | ; like the SCO OSR5 COFF assembler, don't handle the first form. | |
7302 | "@ | |
0f40f9f7 ZW |
7303 | imul{l}\t{%2, %1, %k0|%k0, %1, %2} |
7304 | imul{l}\t{%2, %1, %k0|%k0, %1, %2} | |
7305 | imul{l}\t{%2, %k0|%k0, %2}" | |
9b70259d JH |
7306 | [(set_attr "type" "imul") |
7307 | (set_attr "prefix_0f" "0,0,1") | |
7308 | (set_attr "mode" "SI")]) | |
7309 | ||
d525dfdf JH |
7310 | (define_expand "mulhi3" |
7311 | [(parallel [(set (match_operand:HI 0 "register_operand" "") | |
7312 | (mult:HI (match_operand:HI 1 "register_operand" "") | |
7313 | (match_operand:HI 2 "general_operand" ""))) | |
7314 | (clobber (reg:CC 17))])] | |
d9f32422 | 7315 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
7316 | "") |
7317 | ||
7318 | (define_insn "*mulhi3_1" | |
6ef67412 JH |
7319 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") |
7320 | (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0") | |
7321 | (match_operand:HI 2 "general_operand" "K,i,mr"))) | |
e075ae69 | 7322 | (clobber (reg:CC 17))] |
d525dfdf | 7323 | "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" |
e075ae69 RH |
7324 | ; %%% There was a note about "Assembler has weird restrictions", |
7325 | ; concerning alternative 1 when op1 == op0. True? | |
7326 | "@ | |
0f40f9f7 ZW |
7327 | imul{w}\t{%2, %1, %0|%0, %1, %2} |
7328 | imul{w}\t{%2, %1, %0|%0, %1, %2} | |
7329 | imul{w}\t{%2, %0|%0, %2}" | |
6ef67412 JH |
7330 | [(set_attr "type" "imul") |
7331 | (set_attr "prefix_0f" "0,0,1") | |
7332 | (set_attr "mode" "HI")]) | |
886c62d1 | 7333 | |
765a46f9 JH |
7334 | (define_insn "mulqi3" |
7335 | [(set (match_operand:QI 0 "register_operand" "=a") | |
7336 | (mult:QI (match_operand:QI 1 "register_operand" "%0") | |
7337 | (match_operand:QI 2 "nonimmediate_operand" "qm"))) | |
7338 | (clobber (reg:CC 17))] | |
d9f32422 | 7339 | "TARGET_QIMODE_MATH" |
0f40f9f7 | 7340 | "mul{b}\t%2" |
6ef67412 JH |
7341 | [(set_attr "type" "imul") |
7342 | (set_attr "length_immediate" "0") | |
7343 | (set_attr "mode" "QI")]) | |
765a46f9 | 7344 | |
4b71cd6e | 7345 | (define_insn "umulqihi3" |
2ae0f82c SC |
7346 | [(set (match_operand:HI 0 "register_operand" "=a") |
7347 | (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0")) | |
e075ae69 RH |
7348 | (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) |
7349 | (clobber (reg:CC 17))] | |
d9f32422 | 7350 | "TARGET_QIMODE_MATH" |
0f40f9f7 | 7351 | "mul{b}\t%2" |
6ef67412 JH |
7352 | [(set_attr "type" "imul") |
7353 | (set_attr "length_immediate" "0") | |
7354 | (set_attr "mode" "QI")]) | |
886c62d1 | 7355 | |
4b71cd6e | 7356 | (define_insn "mulqihi3" |
2ae0f82c SC |
7357 | [(set (match_operand:HI 0 "register_operand" "=a") |
7358 | (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0")) | |
e075ae69 RH |
7359 | (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) |
7360 | (clobber (reg:CC 17))] | |
d9f32422 | 7361 | "TARGET_QIMODE_MATH" |
0f40f9f7 | 7362 | "imul{b}\t%2" |
6ef67412 JH |
7363 | [(set_attr "type" "imul") |
7364 | (set_attr "length_immediate" "0") | |
7365 | (set_attr "mode" "QI")]) | |
4b71cd6e | 7366 | |
9b70259d JH |
7367 | (define_insn "umulditi3" |
7368 | [(set (match_operand:TI 0 "register_operand" "=A") | |
7369 | (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0")) | |
7370 | (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) | |
1e07edd3 | 7371 | (clobber (reg:CC 17))] |
9b70259d | 7372 | "TARGET_64BIT" |
0f40f9f7 | 7373 | "mul{q}\t%2" |
1e07edd3 JH |
7374 | [(set_attr "type" "imul") |
7375 | (set_attr "ppro_uops" "few") | |
7376 | (set_attr "length_immediate" "0") | |
9b70259d | 7377 | (set_attr "mode" "DI")]) |
1e07edd3 JH |
7378 | |
7379 | ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers | |
4b71cd6e MM |
7380 | (define_insn "umulsidi3" |
7381 | [(set (match_operand:DI 0 "register_operand" "=A") | |
7382 | (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) | |
e075ae69 RH |
7383 | (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) |
7384 | (clobber (reg:CC 17))] | |
1e07edd3 | 7385 | "!TARGET_64BIT" |
0f40f9f7 | 7386 | "mul{l}\t%2" |
e075ae69 | 7387 | [(set_attr "type" "imul") |
6ef67412 JH |
7388 | (set_attr "ppro_uops" "few") |
7389 | (set_attr "length_immediate" "0") | |
7390 | (set_attr "mode" "SI")]) | |
4b71cd6e | 7391 | |
9b70259d JH |
7392 | (define_insn "mulditi3" |
7393 | [(set (match_operand:TI 0 "register_operand" "=A") | |
7394 | (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0")) | |
7395 | (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) | |
7396 | (clobber (reg:CC 17))] | |
7397 | "TARGET_64BIT" | |
0f40f9f7 | 7398 | "imul{q}\t%2" |
9b70259d JH |
7399 | [(set_attr "type" "imul") |
7400 | (set_attr "length_immediate" "0") | |
7401 | (set_attr "mode" "DI")]) | |
7402 | ||
4b71cd6e MM |
7403 | (define_insn "mulsidi3" |
7404 | [(set (match_operand:DI 0 "register_operand" "=A") | |
7405 | (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) | |
e075ae69 RH |
7406 | (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) |
7407 | (clobber (reg:CC 17))] | |
1e07edd3 | 7408 | "!TARGET_64BIT" |
0f40f9f7 | 7409 | "imul{l}\t%2" |
6ef67412 JH |
7410 | [(set_attr "type" "imul") |
7411 | (set_attr "length_immediate" "0") | |
7412 | (set_attr "mode" "SI")]) | |
2f2a49e8 | 7413 | |
9b70259d JH |
7414 | (define_insn "*umuldi3_highpart_rex64" |
7415 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7416 | (truncate:DI | |
7417 | (lshiftrt:TI | |
7418 | (mult:TI (zero_extend:TI | |
7419 | (match_operand:DI 1 "register_operand" "%a")) | |
7420 | (zero_extend:TI | |
7421 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
7422 | (const_int 64)))) | |
7423 | (clobber (match_scratch:DI 3 "=a")) | |
7424 | (clobber (reg:CC 17))] | |
7425 | "TARGET_64BIT" | |
0f40f9f7 | 7426 | "mul{q}\t%2" |
9b70259d JH |
7427 | [(set_attr "type" "imul") |
7428 | (set_attr "ppro_uops" "few") | |
7429 | (set_attr "length_immediate" "0") | |
7430 | (set_attr "mode" "DI")]) | |
7431 | ||
34c659e2 | 7432 | (define_insn "umulsi3_highpart" |
2f2a49e8 | 7433 | [(set (match_operand:SI 0 "register_operand" "=d") |
e075ae69 RH |
7434 | (truncate:SI |
7435 | (lshiftrt:DI | |
7436 | (mult:DI (zero_extend:DI | |
7437 | (match_operand:SI 1 "register_operand" "%a")) | |
7438 | (zero_extend:DI | |
7439 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
7440 | (const_int 32)))) | |
7441 | (clobber (match_scratch:SI 3 "=a")) | |
7442 | (clobber (reg:CC 17))] | |
32ee7d1d | 7443 | "" |
0f40f9f7 | 7444 | "mul{l}\t%2" |
32ee7d1d JH |
7445 | [(set_attr "type" "imul") |
7446 | (set_attr "ppro_uops" "few") | |
7447 | (set_attr "length_immediate" "0") | |
7448 | (set_attr "mode" "SI")]) | |
7449 | ||
7450 | (define_insn "*umulsi3_highpart_zext" | |
7451 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7452 | (zero_extend:DI (truncate:SI | |
7453 | (lshiftrt:DI | |
7454 | (mult:DI (zero_extend:DI | |
7455 | (match_operand:SI 1 "register_operand" "%a")) | |
7456 | (zero_extend:DI | |
7457 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
7458 | (const_int 32))))) | |
7459 | (clobber (match_scratch:SI 3 "=a")) | |
7460 | (clobber (reg:CC 17))] | |
7461 | "TARGET_64BIT" | |
0f40f9f7 | 7462 | "mul{l}\t%2" |
e075ae69 | 7463 | [(set_attr "type" "imul") |
6ef67412 JH |
7464 | (set_attr "ppro_uops" "few") |
7465 | (set_attr "length_immediate" "0") | |
7466 | (set_attr "mode" "SI")]) | |
2f2a49e8 | 7467 | |
9b70259d JH |
7468 | (define_insn "*smuldi3_highpart_rex64" |
7469 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7470 | (truncate:DI | |
7471 | (lshiftrt:TI | |
7472 | (mult:TI (sign_extend:TI | |
7473 | (match_operand:DI 1 "register_operand" "%a")) | |
7474 | (sign_extend:TI | |
7475 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
7476 | (const_int 64)))) | |
7477 | (clobber (match_scratch:DI 3 "=a")) | |
7478 | (clobber (reg:CC 17))] | |
7479 | "TARGET_64BIT" | |
0f40f9f7 | 7480 | "imul{q}\t%2" |
9b70259d JH |
7481 | [(set_attr "type" "imul") |
7482 | (set_attr "ppro_uops" "few") | |
7483 | (set_attr "mode" "DI")]) | |
7484 | ||
34c659e2 | 7485 | (define_insn "smulsi3_highpart" |
2f2a49e8 | 7486 | [(set (match_operand:SI 0 "register_operand" "=d") |
e075ae69 RH |
7487 | (truncate:SI |
7488 | (lshiftrt:DI | |
7489 | (mult:DI (sign_extend:DI | |
7490 | (match_operand:SI 1 "register_operand" "%a")) | |
7491 | (sign_extend:DI | |
7492 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
7493 | (const_int 32)))) | |
7494 | (clobber (match_scratch:SI 3 "=a")) | |
7495 | (clobber (reg:CC 17))] | |
7496 | "" | |
0f40f9f7 | 7497 | "imul{l}\t%2" |
e075ae69 | 7498 | [(set_attr "type" "imul") |
6ef67412 JH |
7499 | (set_attr "ppro_uops" "few") |
7500 | (set_attr "mode" "SI")]) | |
4b71cd6e | 7501 | |
9b70259d JH |
7502 | (define_insn "*smulsi3_highpart_zext" |
7503 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7504 | (zero_extend:DI (truncate:SI | |
7505 | (lshiftrt:DI | |
7506 | (mult:DI (sign_extend:DI | |
7507 | (match_operand:SI 1 "register_operand" "%a")) | |
7508 | (sign_extend:DI | |
7509 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
7510 | (const_int 32))))) | |
7511 | (clobber (match_scratch:SI 3 "=a")) | |
7512 | (clobber (reg:CC 17))] | |
7513 | "TARGET_64BIT" | |
0f40f9f7 | 7514 | "imul{l}\t%2" |
9b70259d JH |
7515 | [(set_attr "type" "imul") |
7516 | (set_attr "ppro_uops" "few") | |
7517 | (set_attr "mode" "SI")]) | |
7518 | ||
886c62d1 JVA |
7519 | ;; The patterns that match these are at the end of this file. |
7520 | ||
4fb21e90 JVA |
7521 | (define_expand "mulxf3" |
7522 | [(set (match_operand:XF 0 "register_operand" "") | |
2ae0f82c SC |
7523 | (mult:XF (match_operand:XF 1 "register_operand" "") |
7524 | (match_operand:XF 2 "register_operand" "")))] | |
1b0c37d7 | 7525 | "!TARGET_64BIT && TARGET_80387" |
4fb21e90 JVA |
7526 | "") |
7527 | ||
2b589241 JH |
7528 | (define_expand "multf3" |
7529 | [(set (match_operand:TF 0 "register_operand" "") | |
7530 | (mult:TF (match_operand:TF 1 "register_operand" "") | |
7531 | (match_operand:TF 2 "register_operand" "")))] | |
7532 | "TARGET_80387" | |
7533 | "") | |
7534 | ||
886c62d1 JVA |
7535 | (define_expand "muldf3" |
7536 | [(set (match_operand:DF 0 "register_operand" "") | |
2ae0f82c | 7537 | (mult:DF (match_operand:DF 1 "register_operand" "") |
886c62d1 | 7538 | (match_operand:DF 2 "nonimmediate_operand" "")))] |
965f5423 | 7539 | "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" |
886c62d1 JVA |
7540 | "") |
7541 | ||
7542 | (define_expand "mulsf3" | |
7543 | [(set (match_operand:SF 0 "register_operand" "") | |
2ae0f82c | 7544 | (mult:SF (match_operand:SF 1 "register_operand" "") |
886c62d1 | 7545 | (match_operand:SF 2 "nonimmediate_operand" "")))] |
965f5423 | 7546 | "TARGET_80387 || TARGET_SSE_MATH" |
886c62d1 JVA |
7547 | "") |
7548 | \f | |
e075ae69 | 7549 | ;; Divide instructions |
886c62d1 JVA |
7550 | |
7551 | (define_insn "divqi3" | |
2ae0f82c SC |
7552 | [(set (match_operand:QI 0 "register_operand" "=a") |
7553 | (div:QI (match_operand:HI 1 "register_operand" "0") | |
e075ae69 RH |
7554 | (match_operand:QI 2 "nonimmediate_operand" "qm"))) |
7555 | (clobber (reg:CC 17))] | |
d9f32422 | 7556 | "TARGET_QIMODE_MATH" |
0f40f9f7 | 7557 | "idiv{b}\t%2" |
e075ae69 | 7558 | [(set_attr "type" "idiv") |
6ef67412 | 7559 | (set_attr "mode" "QI") |
e075ae69 | 7560 | (set_attr "ppro_uops" "few")]) |
886c62d1 JVA |
7561 | |
7562 | (define_insn "udivqi3" | |
2ae0f82c SC |
7563 | [(set (match_operand:QI 0 "register_operand" "=a") |
7564 | (udiv:QI (match_operand:HI 1 "register_operand" "0") | |
e075ae69 RH |
7565 | (match_operand:QI 2 "nonimmediate_operand" "qm"))) |
7566 | (clobber (reg:CC 17))] | |
d9f32422 | 7567 | "TARGET_QIMODE_MATH" |
0f40f9f7 | 7568 | "div{b}\t%2" |
e075ae69 | 7569 | [(set_attr "type" "idiv") |
6ef67412 | 7570 | (set_attr "mode" "QI") |
e075ae69 | 7571 | (set_attr "ppro_uops" "few")]) |
886c62d1 JVA |
7572 | |
7573 | ;; The patterns that match these are at the end of this file. | |
7574 | ||
4fb21e90 JVA |
7575 | (define_expand "divxf3" |
7576 | [(set (match_operand:XF 0 "register_operand" "") | |
2ae0f82c SC |
7577 | (div:XF (match_operand:XF 1 "register_operand" "") |
7578 | (match_operand:XF 2 "register_operand" "")))] | |
1b0c37d7 | 7579 | "!TARGET_64BIT && TARGET_80387" |
886c62d1 JVA |
7580 | "") |
7581 | ||
2b589241 JH |
7582 | (define_expand "divtf3" |
7583 | [(set (match_operand:TF 0 "register_operand" "") | |
7584 | (div:TF (match_operand:TF 1 "register_operand" "") | |
7585 | (match_operand:TF 2 "register_operand" "")))] | |
7586 | "TARGET_80387" | |
7587 | "") | |
7588 | ||
a78cb986 SC |
7589 | (define_expand "divdf3" |
7590 | [(set (match_operand:DF 0 "register_operand" "") | |
7591 | (div:DF (match_operand:DF 1 "register_operand" "") | |
7592 | (match_operand:DF 2 "nonimmediate_operand" "")))] | |
965f5423 | 7593 | "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" |
a78cb986 SC |
7594 | "") |
7595 | ||
886c62d1 JVA |
7596 | (define_expand "divsf3" |
7597 | [(set (match_operand:SF 0 "register_operand" "") | |
2ae0f82c | 7598 | (div:SF (match_operand:SF 1 "register_operand" "") |
886c62d1 | 7599 | (match_operand:SF 2 "nonimmediate_operand" "")))] |
965f5423 | 7600 | "TARGET_80387 || TARGET_SSE_MATH" |
886c62d1 JVA |
7601 | "") |
7602 | \f | |
7603 | ;; Remainder instructions. | |
9b70259d JH |
7604 | |
7605 | (define_expand "divmoddi4" | |
7606 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
7607 | (div:DI (match_operand:DI 1 "register_operand" "") | |
7608 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7609 | (set (match_operand:DI 3 "register_operand" "") | |
7610 | (mod:DI (match_dup 1) (match_dup 2))) | |
7611 | (clobber (reg:CC 17))])] | |
7612 | "TARGET_64BIT" | |
7613 | "") | |
7614 | ||
7615 | ;; Allow to come the parameter in eax or edx to avoid extra moves. | |
7616 | ;; Penalize eax case sligthly because it results in worse scheduling | |
7617 | ;; of code. | |
7618 | (define_insn "*divmoddi4_nocltd_rex64" | |
7619 | [(set (match_operand:DI 0 "register_operand" "=&a,?a") | |
7620 | (div:DI (match_operand:DI 2 "register_operand" "1,0") | |
7621 | (match_operand:DI 3 "nonimmediate_operand" "rm,rm"))) | |
7622 | (set (match_operand:DI 1 "register_operand" "=&d,&d") | |
7623 | (mod:DI (match_dup 2) (match_dup 3))) | |
7624 | (clobber (reg:CC 17))] | |
7625 | "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD" | |
7626 | "#" | |
7627 | [(set_attr "type" "multi")]) | |
7628 | ||
7629 | (define_insn "*divmoddi4_cltd_rex64" | |
7630 | [(set (match_operand:DI 0 "register_operand" "=a") | |
7631 | (div:DI (match_operand:DI 2 "register_operand" "a") | |
7632 | (match_operand:DI 3 "nonimmediate_operand" "rm"))) | |
7633 | (set (match_operand:DI 1 "register_operand" "=&d") | |
7634 | (mod:DI (match_dup 2) (match_dup 3))) | |
7635 | (clobber (reg:CC 17))] | |
7636 | "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)" | |
7637 | "#" | |
7638 | [(set_attr "type" "multi")]) | |
7639 | ||
7640 | (define_insn "*divmoddi_noext_rex64" | |
7641 | [(set (match_operand:DI 0 "register_operand" "=a") | |
7642 | (div:DI (match_operand:DI 1 "register_operand" "0") | |
7643 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
7644 | (set (match_operand:DI 3 "register_operand" "=d") | |
7645 | (mod:DI (match_dup 1) (match_dup 2))) | |
7646 | (use (match_operand:DI 4 "register_operand" "3")) | |
7647 | (clobber (reg:CC 17))] | |
7648 | "TARGET_64BIT" | |
0f40f9f7 | 7649 | "idiv{q}\t%2" |
9b70259d JH |
7650 | [(set_attr "type" "idiv") |
7651 | (set_attr "mode" "DI") | |
7652 | (set_attr "ppro_uops" "few")]) | |
7653 | ||
7654 | (define_split | |
7655 | [(set (match_operand:DI 0 "register_operand" "") | |
7656 | (div:DI (match_operand:DI 1 "register_operand" "") | |
7657 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7658 | (set (match_operand:DI 3 "register_operand" "") | |
7659 | (mod:DI (match_dup 1) (match_dup 2))) | |
7660 | (clobber (reg:CC 17))] | |
7661 | "TARGET_64BIT && reload_completed" | |
7662 | [(parallel [(set (match_dup 3) | |
7663 | (ashiftrt:DI (match_dup 4) (const_int 63))) | |
7664 | (clobber (reg:CC 17))]) | |
7665 | (parallel [(set (match_dup 0) | |
7666 | (div:DI (reg:DI 0) (match_dup 2))) | |
7667 | (set (match_dup 3) | |
7668 | (mod:DI (reg:DI 0) (match_dup 2))) | |
7669 | (use (match_dup 3)) | |
7670 | (clobber (reg:CC 17))])] | |
9b70259d JH |
7671 | { |
7672 | /* Avoid use of cltd in favour of a mov+shift. */ | |
7673 | if (!TARGET_USE_CLTD && !optimize_size) | |
7674 | { | |
7675 | if (true_regnum (operands[1])) | |
7676 | emit_move_insn (operands[0], operands[1]); | |
7677 | else | |
7678 | emit_move_insn (operands[3], operands[1]); | |
7679 | operands[4] = operands[3]; | |
7680 | } | |
7681 | else | |
7682 | { | |
7683 | if (true_regnum (operands[1])) | |
7684 | abort(); | |
7685 | operands[4] = operands[1]; | |
7686 | } | |
0f40f9f7 | 7687 | }) |
9b70259d JH |
7688 | |
7689 | ||
40745eec JH |
7690 | (define_expand "divmodsi4" |
7691 | [(parallel [(set (match_operand:SI 0 "register_operand" "") | |
7692 | (div:SI (match_operand:SI 1 "register_operand" "") | |
7693 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7694 | (set (match_operand:SI 3 "register_operand" "") | |
7695 | (mod:SI (match_dup 1) (match_dup 2))) | |
7696 | (clobber (reg:CC 17))])] | |
7697 | "" | |
7698 | "") | |
7699 | ||
7700 | ;; Allow to come the parameter in eax or edx to avoid extra moves. | |
7701 | ;; Penalize eax case sligthly because it results in worse scheduling | |
7702 | ;; of code. | |
7703 | (define_insn "*divmodsi4_nocltd" | |
7704 | [(set (match_operand:SI 0 "register_operand" "=&a,?a") | |
7705 | (div:SI (match_operand:SI 2 "register_operand" "1,0") | |
7706 | (match_operand:SI 3 "nonimmediate_operand" "rm,rm"))) | |
7707 | (set (match_operand:SI 1 "register_operand" "=&d,&d") | |
7708 | (mod:SI (match_dup 2) (match_dup 3))) | |
7709 | (clobber (reg:CC 17))] | |
7710 | "!optimize_size && !TARGET_USE_CLTD" | |
7711 | "#" | |
7712 | [(set_attr "type" "multi")]) | |
886c62d1 | 7713 | |
40745eec | 7714 | (define_insn "*divmodsi4_cltd" |
2bb7a0f5 | 7715 | [(set (match_operand:SI 0 "register_operand" "=a") |
40745eec JH |
7716 | (div:SI (match_operand:SI 2 "register_operand" "a") |
7717 | (match_operand:SI 3 "nonimmediate_operand" "rm"))) | |
7718 | (set (match_operand:SI 1 "register_operand" "=&d") | |
7719 | (mod:SI (match_dup 2) (match_dup 3))) | |
e075ae69 | 7720 | (clobber (reg:CC 17))] |
40745eec JH |
7721 | "optimize_size || TARGET_USE_CLTD" |
7722 | "#" | |
e075ae69 RH |
7723 | [(set_attr "type" "multi")]) |
7724 | ||
6343a50e | 7725 | (define_insn "*divmodsi_noext" |
e075ae69 | 7726 | [(set (match_operand:SI 0 "register_operand" "=a") |
40745eec | 7727 | (div:SI (match_operand:SI 1 "register_operand" "0") |
e075ae69 RH |
7728 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) |
7729 | (set (match_operand:SI 3 "register_operand" "=d") | |
7730 | (mod:SI (match_dup 1) (match_dup 2))) | |
40745eec | 7731 | (use (match_operand:SI 4 "register_operand" "3")) |
e075ae69 RH |
7732 | (clobber (reg:CC 17))] |
7733 | "" | |
0f40f9f7 | 7734 | "idiv{l}\t%2" |
e075ae69 | 7735 | [(set_attr "type" "idiv") |
6ef67412 | 7736 | (set_attr "mode" "SI") |
e075ae69 RH |
7737 | (set_attr "ppro_uops" "few")]) |
7738 | ||
7739 | (define_split | |
7740 | [(set (match_operand:SI 0 "register_operand" "") | |
7741 | (div:SI (match_operand:SI 1 "register_operand" "") | |
7742 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7743 | (set (match_operand:SI 3 "register_operand" "") | |
7744 | (mod:SI (match_dup 1) (match_dup 2))) | |
7745 | (clobber (reg:CC 17))] | |
7746 | "reload_completed" | |
7747 | [(parallel [(set (match_dup 3) | |
7748 | (ashiftrt:SI (match_dup 4) (const_int 31))) | |
7749 | (clobber (reg:CC 17))]) | |
7750 | (parallel [(set (match_dup 0) | |
40745eec | 7751 | (div:SI (reg:SI 0) (match_dup 2))) |
e075ae69 | 7752 | (set (match_dup 3) |
40745eec | 7753 | (mod:SI (reg:SI 0) (match_dup 2))) |
e075ae69 RH |
7754 | (use (match_dup 3)) |
7755 | (clobber (reg:CC 17))])] | |
886c62d1 | 7756 | { |
e075ae69 | 7757 | /* Avoid use of cltd in favour of a mov+shift. */ |
40745eec | 7758 | if (!TARGET_USE_CLTD && !optimize_size) |
e075ae69 | 7759 | { |
40745eec JH |
7760 | if (true_regnum (operands[1])) |
7761 | emit_move_insn (operands[0], operands[1]); | |
7762 | else | |
7763 | emit_move_insn (operands[3], operands[1]); | |
e075ae69 RH |
7764 | operands[4] = operands[3]; |
7765 | } | |
7766 | else | |
40745eec JH |
7767 | { |
7768 | if (true_regnum (operands[1])) | |
7769 | abort(); | |
7770 | operands[4] = operands[1]; | |
7771 | } | |
0f40f9f7 | 7772 | }) |
e075ae69 | 7773 | ;; %%% Split me. |
886c62d1 | 7774 | (define_insn "divmodhi4" |
2bb7a0f5 RS |
7775 | [(set (match_operand:HI 0 "register_operand" "=a") |
7776 | (div:HI (match_operand:HI 1 "register_operand" "0") | |
2ae0f82c | 7777 | (match_operand:HI 2 "nonimmediate_operand" "rm"))) |
2bb7a0f5 | 7778 | (set (match_operand:HI 3 "register_operand" "=&d") |
e075ae69 RH |
7779 | (mod:HI (match_dup 1) (match_dup 2))) |
7780 | (clobber (reg:CC 17))] | |
d9f32422 | 7781 | "TARGET_HIMODE_MATH" |
0f40f9f7 | 7782 | "cwtd\;idiv{w}\t%2" |
6ef67412 JH |
7783 | [(set_attr "type" "multi") |
7784 | (set_attr "length_immediate" "0") | |
7785 | (set_attr "mode" "SI")]) | |
886c62d1 | 7786 | |
9b70259d JH |
7787 | (define_insn "udivmoddi4" |
7788 | [(set (match_operand:DI 0 "register_operand" "=a") | |
7789 | (udiv:DI (match_operand:DI 1 "register_operand" "0") | |
7790 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
7791 | (set (match_operand:DI 3 "register_operand" "=&d") | |
7792 | (umod:DI (match_dup 1) (match_dup 2))) | |
7793 | (clobber (reg:CC 17))] | |
7794 | "TARGET_64BIT" | |
0f40f9f7 | 7795 | "xor{q}\t%3, %3\;div{q}\t%2" |
9b70259d JH |
7796 | [(set_attr "type" "multi") |
7797 | (set_attr "length_immediate" "0") | |
7798 | (set_attr "mode" "DI")]) | |
7799 | ||
7800 | (define_insn "*udivmoddi4_noext" | |
7801 | [(set (match_operand:DI 0 "register_operand" "=a") | |
7802 | (udiv:DI (match_operand:DI 1 "register_operand" "0") | |
7803 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
7804 | (set (match_operand:DI 3 "register_operand" "=d") | |
7805 | (umod:DI (match_dup 1) (match_dup 2))) | |
7806 | (use (match_dup 3)) | |
7807 | (clobber (reg:CC 17))] | |
7808 | "TARGET_64BIT" | |
0f40f9f7 | 7809 | "div{q}\t%2" |
9b70259d JH |
7810 | [(set_attr "type" "idiv") |
7811 | (set_attr "ppro_uops" "few") | |
7812 | (set_attr "mode" "DI")]) | |
7813 | ||
7814 | (define_split | |
7815 | [(set (match_operand:DI 0 "register_operand" "") | |
7816 | (udiv:DI (match_operand:DI 1 "register_operand" "") | |
7817 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7818 | (set (match_operand:DI 3 "register_operand" "") | |
7819 | (umod:DI (match_dup 1) (match_dup 2))) | |
7820 | (clobber (reg:CC 17))] | |
1b0c37d7 | 7821 | "TARGET_64BIT && reload_completed" |
9b70259d JH |
7822 | [(set (match_dup 3) (const_int 0)) |
7823 | (parallel [(set (match_dup 0) | |
7824 | (udiv:DI (match_dup 1) (match_dup 2))) | |
7825 | (set (match_dup 3) | |
7826 | (umod:DI (match_dup 1) (match_dup 2))) | |
7827 | (use (match_dup 3)) | |
7828 | (clobber (reg:CC 17))])] | |
7829 | "") | |
7830 | ||
886c62d1 | 7831 | (define_insn "udivmodsi4" |
2bb7a0f5 RS |
7832 | [(set (match_operand:SI 0 "register_operand" "=a") |
7833 | (udiv:SI (match_operand:SI 1 "register_operand" "0") | |
2ae0f82c | 7834 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) |
2bb7a0f5 | 7835 | (set (match_operand:SI 3 "register_operand" "=&d") |
e075ae69 RH |
7836 | (umod:SI (match_dup 1) (match_dup 2))) |
7837 | (clobber (reg:CC 17))] | |
886c62d1 | 7838 | "" |
0f40f9f7 | 7839 | "xor{l}\t%3, %3\;div{l}\t%2" |
6ef67412 JH |
7840 | [(set_attr "type" "multi") |
7841 | (set_attr "length_immediate" "0") | |
7842 | (set_attr "mode" "SI")]) | |
886c62d1 | 7843 | |
6343a50e | 7844 | (define_insn "*udivmodsi4_noext" |
2bb7a0f5 | 7845 | [(set (match_operand:SI 0 "register_operand" "=a") |
e075ae69 | 7846 | (udiv:SI (match_operand:SI 1 "register_operand" "0") |
2ae0f82c | 7847 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) |
2bb7a0f5 | 7848 | (set (match_operand:SI 3 "register_operand" "=d") |
e075ae69 RH |
7849 | (umod:SI (match_dup 1) (match_dup 2))) |
7850 | (use (match_dup 3)) | |
7851 | (clobber (reg:CC 17))] | |
886c62d1 | 7852 | "" |
0f40f9f7 | 7853 | "div{l}\t%2" |
e075ae69 | 7854 | [(set_attr "type" "idiv") |
6ef67412 JH |
7855 | (set_attr "ppro_uops" "few") |
7856 | (set_attr "mode" "SI")]) | |
886c62d1 | 7857 | |
e075ae69 RH |
7858 | (define_split |
7859 | [(set (match_operand:SI 0 "register_operand" "") | |
7860 | (udiv:SI (match_operand:SI 1 "register_operand" "") | |
7861 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7862 | (set (match_operand:SI 3 "register_operand" "") | |
7863 | (umod:SI (match_dup 1) (match_dup 2))) | |
7864 | (clobber (reg:CC 17))] | |
7865 | "reload_completed" | |
591702de | 7866 | [(set (match_dup 3) (const_int 0)) |
e075ae69 RH |
7867 | (parallel [(set (match_dup 0) |
7868 | (udiv:SI (match_dup 1) (match_dup 2))) | |
7869 | (set (match_dup 3) | |
7870 | (umod:SI (match_dup 1) (match_dup 2))) | |
7871 | (use (match_dup 3)) | |
7872 | (clobber (reg:CC 17))])] | |
7873 | "") | |
886c62d1 | 7874 | |
e075ae69 | 7875 | (define_expand "udivmodhi4" |
591702de | 7876 | [(set (match_dup 4) (const_int 0)) |
40745eec JH |
7877 | (parallel [(set (match_operand:HI 0 "register_operand" "") |
7878 | (udiv:HI (match_operand:HI 1 "register_operand" "") | |
7879 | (match_operand:HI 2 "nonimmediate_operand" ""))) | |
7880 | (set (match_operand:HI 3 "register_operand" "") | |
e075ae69 RH |
7881 | (umod:HI (match_dup 1) (match_dup 2))) |
7882 | (use (match_dup 4)) | |
7883 | (clobber (reg:CC 17))])] | |
d9f32422 | 7884 | "TARGET_HIMODE_MATH" |
e075ae69 | 7885 | "operands[4] = gen_reg_rtx (HImode);") |
886c62d1 | 7886 | |
6343a50e | 7887 | (define_insn "*udivmodhi_noext" |
e075ae69 RH |
7888 | [(set (match_operand:HI 0 "register_operand" "=a") |
7889 | (udiv:HI (match_operand:HI 1 "register_operand" "0") | |
7890 | (match_operand:HI 2 "nonimmediate_operand" "rm"))) | |
7891 | (set (match_operand:HI 3 "register_operand" "=d") | |
7892 | (umod:HI (match_dup 1) (match_dup 2))) | |
7893 | (use (match_operand:HI 4 "register_operand" "3")) | |
7894 | (clobber (reg:CC 17))] | |
7895 | "" | |
0f40f9f7 | 7896 | "div{w}\t%2" |
e075ae69 | 7897 | [(set_attr "type" "idiv") |
6ef67412 | 7898 | (set_attr "mode" "HI") |
e075ae69 RH |
7899 | (set_attr "ppro_uops" "few")]) |
7900 | ||
7901 | ;; We can not use div/idiv for double division, because it causes | |
7902 | ;; "division by zero" on the overflow and that's not what we expect | |
7903 | ;; from truncate. Because true (non truncating) double division is | |
7904 | ;; never generated, we can't create this insn anyway. | |
7905 | ; | |
7906 | ;(define_insn "" | |
7907 | ; [(set (match_operand:SI 0 "register_operand" "=a") | |
7908 | ; (truncate:SI | |
7909 | ; (udiv:DI (match_operand:DI 1 "register_operand" "A") | |
7910 | ; (zero_extend:DI | |
7911 | ; (match_operand:SI 2 "nonimmediate_operand" "rm"))))) | |
7912 | ; (set (match_operand:SI 3 "register_operand" "=d") | |
7913 | ; (truncate:SI | |
7914 | ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2))))) | |
7915 | ; (clobber (reg:CC 17))] | |
7916 | ; "" | |
0f40f9f7 | 7917 | ; "div{l}\t{%2, %0|%0, %2}" |
e075ae69 RH |
7918 | ; [(set_attr "type" "idiv") |
7919 | ; (set_attr "ppro_uops" "few")]) | |
886c62d1 | 7920 | \f |
e075ae69 RH |
7921 | ;;- Logical AND instructions |
7922 | ||
7923 | ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al. | |
7924 | ;; Note that this excludes ah. | |
7925 | ||
9b70259d JH |
7926 | (define_insn "*testdi_1_rex64" |
7927 | [(set (reg 17) | |
7928 | (compare | |
7929 | (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm") | |
7930 | (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re")) | |
7931 | (const_int 0)))] | |
7932 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
7933 | "@ | |
0f40f9f7 ZW |
7934 | test{l}\t{%k1, %k0|%k0, %k1} |
7935 | test{l}\t{%k1, %k0|%k0, %k1} | |
7936 | test{q}\t{%1, %0|%0, %1} | |
7937 | test{q}\t{%1, %0|%0, %1} | |
7938 | test{q}\t{%1, %0|%0, %1}" | |
9b70259d JH |
7939 | [(set_attr "type" "test") |
7940 | (set_attr "modrm" "0,1,0,1,1") | |
7941 | (set_attr "mode" "SI,SI,DI,DI,DI") | |
7942 | (set_attr "pent_pair" "uv,np,uv,np,uv")]) | |
9076b9c1 JH |
7943 | |
7944 | (define_insn "testsi_1" | |
7945 | [(set (reg 17) | |
7946 | (compare | |
16189740 RH |
7947 | (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm") |
7948 | (match_operand:SI 1 "nonmemory_operand" "in,in,rin")) | |
7949 | (const_int 0)))] | |
9076b9c1 | 7950 | "ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 7951 | "test{l}\t{%1, %0|%0, %1}" |
6ef67412 JH |
7952 | [(set_attr "type" "test") |
7953 | (set_attr "modrm" "0,1,1") | |
7954 | (set_attr "mode" "SI") | |
e075ae69 RH |
7955 | (set_attr "pent_pair" "uv,np,uv")]) |
7956 | ||
9076b9c1 | 7957 | (define_expand "testsi_ccno_1" |
e075ae69 | 7958 | [(set (reg:CCNO 17) |
16189740 | 7959 | (compare:CCNO |
9076b9c1 JH |
7960 | (and:SI (match_operand:SI 0 "nonimmediate_operand" "") |
7961 | (match_operand:SI 1 "nonmemory_operand" "")) | |
16189740 | 7962 | (const_int 0)))] |
a1cbdd7f | 7963 | "" |
9076b9c1 | 7964 | "") |
16189740 RH |
7965 | |
7966 | (define_insn "*testhi_1" | |
7967 | [(set (reg 17) | |
7968 | (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm") | |
7969 | (match_operand:HI 1 "nonmemory_operand" "n,n,rn")) | |
7970 | (const_int 0)))] | |
7971 | "ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 7972 | "test{w}\t{%1, %0|%0, %1}" |
6ef67412 JH |
7973 | [(set_attr "type" "test") |
7974 | (set_attr "modrm" "0,1,1") | |
7975 | (set_attr "mode" "HI") | |
e075ae69 RH |
7976 | (set_attr "pent_pair" "uv,np,uv")]) |
7977 | ||
9076b9c1 | 7978 | (define_expand "testqi_ccz_1" |
16189740 | 7979 | [(set (reg:CCZ 17) |
9076b9c1 JH |
7980 | (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "") |
7981 | (match_operand:QI 1 "nonmemory_operand" "")) | |
7982 | (const_int 0)))] | |
16189740 | 7983 | "" |
9076b9c1 | 7984 | "") |
16189740 | 7985 | |
9076b9c1 JH |
7986 | (define_insn "*testqi_1" |
7987 | [(set (reg 17) | |
7988 | (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r") | |
7989 | (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n")) | |
7990 | (const_int 0)))] | |
7991 | "ix86_match_ccmode (insn, CCNOmode)" | |
adc88131 JJ |
7992 | { |
7993 | if (which_alternative == 3) | |
7994 | { | |
7995 | if (GET_CODE (operands[1]) == CONST_INT | |
7996 | && (INTVAL (operands[1]) & 0xffffff00)) | |
7997 | operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); | |
0f40f9f7 | 7998 | return "test{l}\t{%1, %k0|%k0, %1}"; |
adc88131 | 7999 | } |
0f40f9f7 ZW |
8000 | return "test{b}\t{%1, %0|%0, %1}"; |
8001 | } | |
6ef67412 JH |
8002 | [(set_attr "type" "test") |
8003 | (set_attr "modrm" "0,1,1,1") | |
8004 | (set_attr "mode" "QI,QI,QI,SI") | |
8005 | (set_attr "pent_pair" "uv,np,uv,np")]) | |
e075ae69 | 8006 | |
9076b9c1 JH |
8007 | (define_expand "testqi_ext_ccno_0" |
8008 | [(set (reg:CCNO 17) | |
8009 | (compare:CCNO | |
16189740 RH |
8010 | (and:SI |
8011 | (zero_extract:SI | |
9076b9c1 | 8012 | (match_operand 0 "ext_register_operand" "") |
16189740 RH |
8013 | (const_int 8) |
8014 | (const_int 8)) | |
9076b9c1 | 8015 | (match_operand 1 "const_int_operand" "")) |
16189740 | 8016 | (const_int 0)))] |
9076b9c1 JH |
8017 | "" |
8018 | "") | |
e075ae69 | 8019 | |
9076b9c1 JH |
8020 | (define_insn "*testqi_ext_0" |
8021 | [(set (reg 17) | |
8022 | (compare | |
e075ae69 RH |
8023 | (and:SI |
8024 | (zero_extract:SI | |
d2836273 | 8025 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
8026 | (const_int 8) |
8027 | (const_int 8)) | |
8028 | (match_operand 1 "const_int_operand" "n")) | |
8029 | (const_int 0)))] | |
9076b9c1 JH |
8030 | "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff |
8031 | && ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 8032 | "test{b}\t{%1, %h0|%h0, %1}" |
6ef67412 JH |
8033 | [(set_attr "type" "test") |
8034 | (set_attr "mode" "QI") | |
8035 | (set_attr "length_immediate" "1") | |
e075ae69 RH |
8036 | (set_attr "pent_pair" "np")]) |
8037 | ||
8038 | (define_insn "*testqi_ext_1" | |
16189740 RH |
8039 | [(set (reg 17) |
8040 | (compare | |
e075ae69 RH |
8041 | (and:SI |
8042 | (zero_extract:SI | |
d2836273 | 8043 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
8044 | (const_int 8) |
8045 | (const_int 8)) | |
8046 | (zero_extend:SI | |
d2836273 | 8047 | (match_operand:QI 1 "nonimmediate_operand" "Qm"))) |
e075ae69 | 8048 | (const_int 0)))] |
d2836273 | 8049 | "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 8050 | "test{b}\t{%1, %h0|%h0, %1}" |
d2836273 JH |
8051 | [(set_attr "type" "test") |
8052 | (set_attr "mode" "QI")]) | |
8053 | ||
8054 | (define_insn "*testqi_ext_1_rex64" | |
8055 | [(set (reg 17) | |
8056 | (compare | |
8057 | (and:SI | |
8058 | (zero_extract:SI | |
8059 | (match_operand 0 "ext_register_operand" "Q") | |
8060 | (const_int 8) | |
8061 | (const_int 8)) | |
8062 | (zero_extend:SI | |
3522082b | 8063 | (match_operand:QI 1 "register_operand" "Q"))) |
d2836273 JH |
8064 | (const_int 0)))] |
8065 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 8066 | "test{b}\t{%1, %h0|%h0, %1}" |
6ef67412 JH |
8067 | [(set_attr "type" "test") |
8068 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
8069 | |
8070 | (define_insn "*testqi_ext_2" | |
16189740 RH |
8071 | [(set (reg 17) |
8072 | (compare | |
e075ae69 RH |
8073 | (and:SI |
8074 | (zero_extract:SI | |
d2836273 | 8075 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
8076 | (const_int 8) |
8077 | (const_int 8)) | |
8078 | (zero_extract:SI | |
d2836273 | 8079 | (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
8080 | (const_int 8) |
8081 | (const_int 8))) | |
8082 | (const_int 0)))] | |
16189740 | 8083 | "ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 8084 | "test{b}\t{%h1, %h0|%h0, %h1}" |
6ef67412 JH |
8085 | [(set_attr "type" "test") |
8086 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
8087 | |
8088 | ;; Combine likes to form bit extractions for some tests. Humor it. | |
6343a50e | 8089 | (define_insn "*testqi_ext_3" |
16189740 RH |
8090 | [(set (reg 17) |
8091 | (compare (zero_extract:SI | |
8092 | (match_operand 0 "nonimmediate_operand" "rm") | |
8093 | (match_operand:SI 1 "const_int_operand" "") | |
8094 | (match_operand:SI 2 "const_int_operand" "")) | |
8095 | (const_int 0)))] | |
8096 | "ix86_match_ccmode (insn, CCNOmode) | |
8097 | && (GET_MODE (operands[0]) == SImode | |
9b70259d JH |
8098 | || (TARGET_64BIT && GET_MODE (operands[0]) == DImode) |
8099 | || GET_MODE (operands[0]) == HImode | |
8100 | || GET_MODE (operands[0]) == QImode)" | |
8101 | "#") | |
8102 | ||
8103 | (define_insn "*testqi_ext_3_rex64" | |
8104 | [(set (reg 17) | |
8105 | (compare (zero_extract:DI | |
8106 | (match_operand 0 "nonimmediate_operand" "rm") | |
8107 | (match_operand:DI 1 "const_int_operand" "") | |
8108 | (match_operand:DI 2 "const_int_operand" "")) | |
8109 | (const_int 0)))] | |
1b0c37d7 ZW |
8110 | "TARGET_64BIT |
8111 | && ix86_match_ccmode (insn, CCNOmode) | |
f5143c46 | 8112 | /* The code below cannot deal with constants outside HOST_WIDE_INT. */ |
44cf5b6a JH |
8113 | && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT |
8114 | /* Ensure that resulting mask is zero or sign extended operand. */ | |
8115 | && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 | |
8116 | || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64 | |
8117 | && INTVAL (operands[1]) > 32)) | |
9b70259d JH |
8118 | && (GET_MODE (operands[0]) == SImode |
8119 | || GET_MODE (operands[0]) == DImode | |
16189740 RH |
8120 | || GET_MODE (operands[0]) == HImode |
8121 | || GET_MODE (operands[0]) == QImode)" | |
e075ae69 | 8122 | "#") |
4fce8e83 | 8123 | |
e075ae69 | 8124 | (define_split |
16189740 | 8125 | [(set (reg 17) |
9b70259d | 8126 | (compare (zero_extract |
d5d6a58b | 8127 | (match_operand 0 "nonimmediate_operand" "") |
9b70259d JH |
8128 | (match_operand 1 "const_int_operand" "") |
8129 | (match_operand 2 "const_int_operand" "")) | |
16189740 RH |
8130 | (const_int 0)))] |
8131 | "ix86_match_ccmode (insn, CCNOmode)" | |
e075ae69 | 8132 | [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] |
e075ae69 RH |
8133 | { |
8134 | HOST_WIDE_INT len = INTVAL (operands[1]); | |
8135 | HOST_WIDE_INT pos = INTVAL (operands[2]); | |
8136 | HOST_WIDE_INT mask; | |
592188a5 | 8137 | enum machine_mode mode, submode; |
886c62d1 | 8138 | |
e075ae69 RH |
8139 | mode = GET_MODE (operands[0]); |
8140 | if (GET_CODE (operands[0]) == MEM) | |
5bc7cd8e | 8141 | { |
e075ae69 RH |
8142 | /* ??? Combine likes to put non-volatile mem extractions in QImode |
8143 | no matter the size of the test. So find a mode that works. */ | |
8144 | if (! MEM_VOLATILE_P (operands[0])) | |
8145 | { | |
8146 | mode = smallest_mode_for_size (pos + len, MODE_INT); | |
f4ef873c | 8147 | operands[0] = adjust_address (operands[0], mode, 0); |
e075ae69 | 8148 | } |
5bc7cd8e | 8149 | } |
592188a5 RH |
8150 | else if (GET_CODE (operands[0]) == SUBREG |
8151 | && (submode = GET_MODE (SUBREG_REG (operands[0])), | |
8152 | GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode)) | |
8153 | && pos + len <= GET_MODE_BITSIZE (submode)) | |
8154 | { | |
8155 | /* Narrow a paradoxical subreg to prevent partial register stalls. */ | |
8156 | mode = submode; | |
8157 | operands[0] = SUBREG_REG (operands[0]); | |
8158 | } | |
e075ae69 | 8159 | else if (mode == HImode && pos + len <= 8) |
5bc7cd8e | 8160 | { |
e075ae69 RH |
8161 | /* Small HImode tests can be converted to QImode. */ |
8162 | mode = QImode; | |
8163 | operands[0] = gen_lowpart (QImode, operands[0]); | |
5bc7cd8e SC |
8164 | } |
8165 | ||
e075ae69 RH |
8166 | mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1; |
8167 | mask &= ~(((HOST_WIDE_INT)1 << pos) - 1); | |
886c62d1 | 8168 | |
383252a7 AO |
8169 | operands[3] = gen_rtx_AND (mode, operands[0], |
8170 | GEN_INT (trunc_int_for_mode (mask, mode))); | |
0f40f9f7 | 8171 | }) |
886c62d1 | 8172 | |
e075ae69 RH |
8173 | ;; %%% This used to optimize known byte-wide and operations to memory, |
8174 | ;; and sometimes to QImode registers. If this is considered useful, | |
8175 | ;; it should be done with splitters. | |
8176 | ||
9b70259d JH |
8177 | (define_expand "anddi3" |
8178 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8179 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
8180 | (match_operand:DI 2 "x86_64_szext_general_operand" ""))) | |
8181 | (clobber (reg:CC 17))] | |
8182 | "TARGET_64BIT" | |
8183 | "ix86_expand_binary_operator (AND, DImode, operands); DONE;") | |
8184 | ||
8185 | (define_insn "*anddi_1_rex64" | |
8186 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r") | |
8187 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm") | |
8188 | (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L"))) | |
8189 | (clobber (reg:CC 17))] | |
8190 | "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)" | |
9b70259d JH |
8191 | { |
8192 | switch (get_attr_type (insn)) | |
8193 | { | |
8194 | case TYPE_IMOVX: | |
8195 | { | |
8196 | enum machine_mode mode; | |
8197 | ||
8198 | if (GET_CODE (operands[2]) != CONST_INT) | |
8199 | abort (); | |
8200 | if (INTVAL (operands[2]) == 0xff) | |
8201 | mode = QImode; | |
8202 | else if (INTVAL (operands[2]) == 0xffff) | |
8203 | mode = HImode; | |
8204 | else | |
8205 | abort (); | |
8206 | ||
8207 | operands[1] = gen_lowpart (mode, operands[1]); | |
8208 | if (mode == QImode) | |
0f40f9f7 | 8209 | return "movz{bq|x}\t{%1,%0|%0, %1}"; |
9b70259d | 8210 | else |
0f40f9f7 | 8211 | return "movz{wq|x}\t{%1,%0|%0, %1}"; |
9b70259d JH |
8212 | } |
8213 | ||
8214 | default: | |
8215 | if (! rtx_equal_p (operands[0], operands[1])) | |
8216 | abort (); | |
8217 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 8218 | return "and{l}\t{%k2, %k0|%k0, %k2}"; |
9b70259d | 8219 | else |
0f40f9f7 | 8220 | return "and{q}\t{%2, %0|%0, %2}"; |
9b70259d | 8221 | } |
0f40f9f7 | 8222 | } |
9b70259d JH |
8223 | [(set_attr "type" "alu,alu,alu,imovx") |
8224 | (set_attr "length_immediate" "*,*,*,0") | |
8225 | (set_attr "mode" "SI,DI,DI,DI")]) | |
8226 | ||
8227 | (define_insn "*anddi_2" | |
8228 | [(set (reg 17) | |
8229 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") | |
8230 | (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re")) | |
8231 | (const_int 0))) | |
8232 | (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm") | |
8233 | (and:DI (match_dup 1) (match_dup 2)))] | |
8234 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8235 | && ix86_binary_operator_ok (AND, DImode, operands)" | |
8236 | "@ | |
0f40f9f7 ZW |
8237 | and{l}\t{%k2, %k0|%k0, %k2} |
8238 | and{q}\t{%2, %0|%0, %2} | |
8239 | and{q}\t{%2, %0|%0, %2}" | |
9b70259d JH |
8240 | [(set_attr "type" "alu") |
8241 | (set_attr "mode" "SI,DI,DI")]) | |
8242 | ||
e075ae69 RH |
8243 | (define_expand "andsi3" |
8244 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
8245 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
8246 | (match_operand:SI 2 "general_operand" ""))) | |
8247 | (clobber (reg:CC 17))] | |
8248 | "" | |
8249 | "ix86_expand_binary_operator (AND, SImode, operands); DONE;") | |
8250 | ||
8251 | (define_insn "*andsi_1" | |
8252 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r") | |
8253 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm") | |
8254 | (match_operand:SI 2 "general_operand" "ri,rm,L"))) | |
8255 | (clobber (reg:CC 17))] | |
8256 | "ix86_binary_operator_ok (AND, SImode, operands)" | |
886c62d1 | 8257 | { |
e075ae69 | 8258 | switch (get_attr_type (insn)) |
886c62d1 | 8259 | { |
e075ae69 RH |
8260 | case TYPE_IMOVX: |
8261 | { | |
8262 | enum machine_mode mode; | |
5bc7cd8e | 8263 | |
e075ae69 RH |
8264 | if (GET_CODE (operands[2]) != CONST_INT) |
8265 | abort (); | |
8266 | if (INTVAL (operands[2]) == 0xff) | |
8267 | mode = QImode; | |
8268 | else if (INTVAL (operands[2]) == 0xffff) | |
8269 | mode = HImode; | |
8270 | else | |
8271 | abort (); | |
8272 | ||
8273 | operands[1] = gen_lowpart (mode, operands[1]); | |
8274 | if (mode == QImode) | |
0f40f9f7 | 8275 | return "movz{bl|x}\t{%1,%0|%0, %1}"; |
e075ae69 | 8276 | else |
0f40f9f7 | 8277 | return "movz{wl|x}\t{%1,%0|%0, %1}"; |
e075ae69 | 8278 | } |
5bc7cd8e | 8279 | |
e075ae69 RH |
8280 | default: |
8281 | if (! rtx_equal_p (operands[0], operands[1])) | |
8282 | abort (); | |
0f40f9f7 | 8283 | return "and{l}\t{%2, %0|%0, %2}"; |
886c62d1 | 8284 | } |
0f40f9f7 | 8285 | } |
6ef67412 JH |
8286 | [(set_attr "type" "alu,alu,imovx") |
8287 | (set_attr "length_immediate" "*,*,0") | |
8288 | (set_attr "mode" "SI")]) | |
8289 | ||
8290 | (define_split | |
05b432db | 8291 | [(set (match_operand 0 "register_operand" "") |
9b70259d JH |
8292 | (and (match_dup 0) |
8293 | (const_int -65536))) | |
6ef67412 | 8294 | (clobber (reg:CC 17))] |
3522082b | 8295 | "optimize_size" |
6ef67412 JH |
8296 | [(set (strict_low_part (match_dup 1)) (const_int 0))] |
8297 | "operands[1] = gen_lowpart (HImode, operands[0]);") | |
8298 | ||
8299 | (define_split | |
3522082b | 8300 | [(set (match_operand 0 "ext_register_operand" "") |
5e1a2fc7 | 8301 | (and (match_dup 0) |
9b70259d | 8302 | (const_int -256))) |
6ef67412 | 8303 | (clobber (reg:CC 17))] |
05b432db | 8304 | "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed" |
6ef67412 JH |
8305 | [(set (strict_low_part (match_dup 1)) (const_int 0))] |
8306 | "operands[1] = gen_lowpart (QImode, operands[0]);") | |
8307 | ||
8308 | (define_split | |
3522082b | 8309 | [(set (match_operand 0 "ext_register_operand" "") |
6ef67412 JH |
8310 | (and (match_dup 0) |
8311 | (const_int -65281))) | |
8312 | (clobber (reg:CC 17))] | |
05b432db | 8313 | "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed" |
6ef67412 JH |
8314 | [(parallel [(set (zero_extract:SI (match_dup 0) |
8315 | (const_int 8) | |
8316 | (const_int 8)) | |
8317 | (xor:SI | |
8318 | (zero_extract:SI (match_dup 0) | |
8319 | (const_int 8) | |
8320 | (const_int 8)) | |
8321 | (zero_extract:SI (match_dup 0) | |
8322 | (const_int 8) | |
8323 | (const_int 8)))) | |
8324 | (clobber (reg:CC 17))])] | |
8325 | "operands[0] = gen_lowpart (SImode, operands[0]);") | |
e075ae69 | 8326 | |
9b70259d JH |
8327 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8328 | (define_insn "*andsi_1_zext" | |
8329 | [(set (match_operand:DI 0 "register_operand" "=r") | |
8330 | (zero_extend:DI | |
8331 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8332 | (match_operand:SI 2 "general_operand" "rim")))) | |
8333 | (clobber (reg:CC 17))] | |
8334 | "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)" | |
0f40f9f7 | 8335 | "and{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8336 | [(set_attr "type" "alu") |
8337 | (set_attr "mode" "SI")]) | |
8338 | ||
e075ae69 | 8339 | (define_insn "*andsi_2" |
16189740 RH |
8340 | [(set (reg 17) |
8341 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
8342 | (match_operand:SI 2 "general_operand" "rim,ri")) | |
8343 | (const_int 0))) | |
e075ae69 RH |
8344 | (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") |
8345 | (and:SI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8346 | "ix86_match_ccmode (insn, CCNOmode) |
8347 | && ix86_binary_operator_ok (AND, SImode, operands)" | |
0f40f9f7 | 8348 | "and{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8349 | [(set_attr "type" "alu") |
8350 | (set_attr "mode" "SI")]) | |
e075ae69 | 8351 | |
9b70259d JH |
8352 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8353 | (define_insn "*andsi_2_zext" | |
8354 | [(set (reg 17) | |
8355 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8356 | (match_operand:SI 2 "general_operand" "rim")) | |
8357 | (const_int 0))) | |
8358 | (set (match_operand:DI 0 "register_operand" "=r") | |
8359 | (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] | |
8360 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8361 | && ix86_binary_operator_ok (AND, SImode, operands)" | |
0f40f9f7 | 8362 | "and{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8363 | [(set_attr "type" "alu") |
8364 | (set_attr "mode" "SI")]) | |
8365 | ||
e075ae69 RH |
8366 | (define_expand "andhi3" |
8367 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
8368 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
8369 | (match_operand:HI 2 "general_operand" ""))) | |
8370 | (clobber (reg:CC 17))] | |
d9f32422 | 8371 | "TARGET_HIMODE_MATH" |
e075ae69 RH |
8372 | "ix86_expand_binary_operator (AND, HImode, operands); DONE;") |
8373 | ||
8374 | (define_insn "*andhi_1" | |
8375 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") | |
8376 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm") | |
8377 | (match_operand:HI 2 "general_operand" "ri,rm,L"))) | |
8378 | (clobber (reg:CC 17))] | |
8379 | "ix86_binary_operator_ok (AND, HImode, operands)" | |
886c62d1 | 8380 | { |
e075ae69 | 8381 | switch (get_attr_type (insn)) |
886c62d1 | 8382 | { |
e075ae69 RH |
8383 | case TYPE_IMOVX: |
8384 | if (GET_CODE (operands[2]) != CONST_INT) | |
8385 | abort (); | |
8386 | if (INTVAL (operands[2]) == 0xff) | |
0f40f9f7 | 8387 | return "movz{bl|x}\t{%b1, %k0|%k0, %b1}"; |
e075ae69 | 8388 | abort (); |
886c62d1 | 8389 | |
e075ae69 RH |
8390 | default: |
8391 | if (! rtx_equal_p (operands[0], operands[1])) | |
8392 | abort (); | |
886c62d1 | 8393 | |
0f40f9f7 | 8394 | return "and{w}\t{%2, %0|%0, %2}"; |
5bc7cd8e | 8395 | } |
0f40f9f7 | 8396 | } |
6ef67412 JH |
8397 | [(set_attr "type" "alu,alu,imovx") |
8398 | (set_attr "length_immediate" "*,*,0") | |
8399 | (set_attr "mode" "HI,HI,SI")]) | |
5bc7cd8e | 8400 | |
e075ae69 | 8401 | (define_insn "*andhi_2" |
16189740 RH |
8402 | [(set (reg 17) |
8403 | (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
8404 | (match_operand:HI 2 "general_operand" "rim,ri")) | |
8405 | (const_int 0))) | |
e075ae69 RH |
8406 | (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") |
8407 | (and:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8408 | "ix86_match_ccmode (insn, CCNOmode) |
8409 | && ix86_binary_operator_ok (AND, HImode, operands)" | |
0f40f9f7 | 8410 | "and{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8411 | [(set_attr "type" "alu") |
8412 | (set_attr "mode" "HI")]) | |
5bc7cd8e | 8413 | |
e075ae69 RH |
8414 | (define_expand "andqi3" |
8415 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
8416 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
8417 | (match_operand:QI 2 "general_operand" ""))) | |
8418 | (clobber (reg:CC 17))] | |
d9f32422 | 8419 | "TARGET_QIMODE_MATH" |
e075ae69 RH |
8420 | "ix86_expand_binary_operator (AND, QImode, operands); DONE;") |
8421 | ||
8422 | ;; %%% Potential partial reg stall on alternative 2. What to do? | |
8423 | (define_insn "*andqi_1" | |
7c6b971d | 8424 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") |
e075ae69 | 8425 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") |
7c6b971d | 8426 | (match_operand:QI 2 "general_operand" "qi,qmi,ri"))) |
e075ae69 RH |
8427 | (clobber (reg:CC 17))] |
8428 | "ix86_binary_operator_ok (AND, QImode, operands)" | |
8429 | "@ | |
0f40f9f7 ZW |
8430 | and{b}\t{%2, %0|%0, %2} |
8431 | and{b}\t{%2, %0|%0, %2} | |
8432 | and{l}\t{%k2, %k0|%k0, %k2}" | |
6ef67412 JH |
8433 | [(set_attr "type" "alu") |
8434 | (set_attr "mode" "QI,QI,SI")]) | |
e075ae69 | 8435 | |
a1b8572c JH |
8436 | (define_insn "*andqi_1_slp" |
8437 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) | |
8438 | (and:QI (match_dup 0) | |
8439 | (match_operand:QI 1 "general_operand" "qi,qmi"))) | |
8440 | (clobber (reg:CC 17))] | |
8441 | "" | |
0f40f9f7 | 8442 | "and{b}\t{%1, %0|%0, %1}" |
a1b8572c JH |
8443 | [(set_attr "type" "alu1") |
8444 | (set_attr "mode" "QI")]) | |
8445 | ||
e075ae69 | 8446 | (define_insn "*andqi_2" |
16189740 RH |
8447 | [(set (reg 17) |
8448 | (compare (and:QI | |
8449 | (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
8450 | (match_operand:QI 2 "general_operand" "qim,qi,i")) | |
8451 | (const_int 0))) | |
e075ae69 RH |
8452 | (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r") |
8453 | (and:QI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8454 | "ix86_match_ccmode (insn, CCNOmode) |
8455 | && ix86_binary_operator_ok (AND, QImode, operands)" | |
adc88131 JJ |
8456 | { |
8457 | if (which_alternative == 2) | |
8458 | { | |
8459 | if (GET_CODE (operands[2]) == CONST_INT | |
8460 | && (INTVAL (operands[2]) & 0xffffff00)) | |
8461 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); | |
0f40f9f7 | 8462 | return "and{l}\t{%2, %k0|%k0, %2}"; |
adc88131 | 8463 | } |
0f40f9f7 ZW |
8464 | return "and{b}\t{%2, %0|%0, %2}"; |
8465 | } | |
6ef67412 JH |
8466 | [(set_attr "type" "alu") |
8467 | (set_attr "mode" "QI,QI,SI")]) | |
e075ae69 | 8468 | |
a1b8572c JH |
8469 | (define_insn "*andqi_2_slp" |
8470 | [(set (reg 17) | |
8471 | (compare (and:QI | |
8472 | (match_operand:QI 0 "nonimmediate_operand" "+q,qm") | |
8473 | (match_operand:QI 1 "nonimmediate_operand" "qmi,qi")) | |
8474 | (const_int 0))) | |
8475 | (set (strict_low_part (match_dup 0)) | |
8476 | (and:QI (match_dup 0) (match_dup 1)))] | |
8477 | "ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 8478 | "and{b}\t{%1, %0|%0, %1}" |
a1b8572c JH |
8479 | [(set_attr "type" "alu1") |
8480 | (set_attr "mode" "QI")]) | |
8481 | ||
e075ae69 RH |
8482 | ;; ??? A bug in recog prevents it from recognizing a const_int as an |
8483 | ;; operand to zero_extend in andqi_ext_1. It was checking explicitly | |
8484 | ;; for a QImode operand, which of course failed. | |
8485 | ||
8486 | (define_insn "andqi_ext_0" | |
d2836273 | 8487 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
8488 | (const_int 8) |
8489 | (const_int 8)) | |
8490 | (and:SI | |
8491 | (zero_extract:SI | |
8492 | (match_operand 1 "ext_register_operand" "0") | |
8493 | (const_int 8) | |
8494 | (const_int 8)) | |
8495 | (match_operand 2 "const_int_operand" "n"))) | |
8496 | (clobber (reg:CC 17))] | |
8497 | "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff" | |
0f40f9f7 | 8498 | "and{b}\t{%2, %h0|%h0, %2}" |
6ef67412 JH |
8499 | [(set_attr "type" "alu") |
8500 | (set_attr "length_immediate" "1") | |
8501 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
8502 | |
8503 | ;; Generated by peephole translating test to and. This shows up | |
8504 | ;; often in fp comparisons. | |
8505 | ||
8506 | (define_insn "*andqi_ext_0_cc" | |
16189740 RH |
8507 | [(set (reg 17) |
8508 | (compare | |
e075ae69 RH |
8509 | (and:SI |
8510 | (zero_extract:SI | |
084e679a | 8511 | (match_operand 1 "ext_register_operand" "0") |
3522082b | 8512 | (const_int 8) |
e075ae69 RH |
8513 | (const_int 8)) |
8514 | (match_operand 2 "const_int_operand" "n")) | |
8515 | (const_int 0))) | |
d2836273 | 8516 | (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
8517 | (const_int 8) |
8518 | (const_int 8)) | |
8519 | (and:SI | |
8520 | (zero_extract:SI | |
8521 | (match_dup 1) | |
8522 | (const_int 8) | |
8523 | (const_int 8)) | |
8524 | (match_dup 2)))] | |
16189740 RH |
8525 | "ix86_match_ccmode (insn, CCNOmode) |
8526 | && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff" | |
0f40f9f7 | 8527 | "and{b}\t{%2, %h0|%h0, %2}" |
6ef67412 JH |
8528 | [(set_attr "type" "alu") |
8529 | (set_attr "length_immediate" "1") | |
8530 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
8531 | |
8532 | (define_insn "*andqi_ext_1" | |
d2836273 | 8533 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
8534 | (const_int 8) |
8535 | (const_int 8)) | |
8536 | (and:SI | |
8537 | (zero_extract:SI | |
8538 | (match_operand 1 "ext_register_operand" "0") | |
8539 | (const_int 8) | |
8540 | (const_int 8)) | |
8541 | (zero_extend:SI | |
d2836273 | 8542 | (match_operand:QI 2 "general_operand" "Qm")))) |
e075ae69 | 8543 | (clobber (reg:CC 17))] |
d2836273 | 8544 | "!TARGET_64BIT" |
0f40f9f7 | 8545 | "and{b}\t{%2, %h0|%h0, %2}" |
d2836273 JH |
8546 | [(set_attr "type" "alu") |
8547 | (set_attr "length_immediate" "0") | |
8548 | (set_attr "mode" "QI")]) | |
8549 | ||
8550 | (define_insn "*andqi_ext_1_rex64" | |
8551 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
8552 | (const_int 8) | |
8553 | (const_int 8)) | |
8554 | (and:SI | |
8555 | (zero_extract:SI | |
8556 | (match_operand 1 "ext_register_operand" "0") | |
8557 | (const_int 8) | |
8558 | (const_int 8)) | |
8559 | (zero_extend:SI | |
3522082b | 8560 | (match_operand 2 "ext_register_operand" "Q")))) |
d2836273 JH |
8561 | (clobber (reg:CC 17))] |
8562 | "TARGET_64BIT" | |
0f40f9f7 | 8563 | "and{b}\t{%2, %h0|%h0, %2}" |
6ef67412 JH |
8564 | [(set_attr "type" "alu") |
8565 | (set_attr "length_immediate" "0") | |
8566 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
8567 | |
8568 | (define_insn "*andqi_ext_2" | |
d2836273 | 8569 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
8570 | (const_int 8) |
8571 | (const_int 8)) | |
8572 | (and:SI | |
8573 | (zero_extract:SI | |
8574 | (match_operand 1 "ext_register_operand" "%0") | |
8575 | (const_int 8) | |
8576 | (const_int 8)) | |
8577 | (zero_extract:SI | |
d2836273 | 8578 | (match_operand 2 "ext_register_operand" "Q") |
e075ae69 RH |
8579 | (const_int 8) |
8580 | (const_int 8)))) | |
8581 | (clobber (reg:CC 17))] | |
8582 | "" | |
0f40f9f7 | 8583 | "and{b}\t{%h2, %h0|%h0, %h2}" |
6ef67412 JH |
8584 | [(set_attr "type" "alu") |
8585 | (set_attr "length_immediate" "0") | |
8586 | (set_attr "mode" "QI")]) | |
886c62d1 | 8587 | \f |
e075ae69 | 8588 | ;; Logical inclusive OR instructions |
57dbca5e | 8589 | |
e075ae69 RH |
8590 | ;; %%% This used to optimize known byte-wide and operations to memory. |
8591 | ;; If this is considered useful, it should be done with splitters. | |
8592 | ||
9b70259d JH |
8593 | (define_expand "iordi3" |
8594 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8595 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
8596 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
8597 | (clobber (reg:CC 17))] | |
8598 | "TARGET_64BIT" | |
8599 | "ix86_expand_binary_operator (IOR, DImode, operands); DONE;") | |
8600 | ||
8601 | (define_insn "*iordi_1_rex64" | |
8602 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
8603 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
8604 | (match_operand:DI 2 "x86_64_general_operand" "re,rme"))) | |
8605 | (clobber (reg:CC 17))] | |
8606 | "TARGET_64BIT | |
8607 | && ix86_binary_operator_ok (IOR, DImode, operands)" | |
0f40f9f7 | 8608 | "or{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
8609 | [(set_attr "type" "alu") |
8610 | (set_attr "mode" "DI")]) | |
8611 | ||
8612 | (define_insn "*iordi_2_rex64" | |
8613 | [(set (reg 17) | |
8614 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
8615 | (match_operand:DI 2 "x86_64_general_operand" "rem,re")) | |
8616 | (const_int 0))) | |
8617 | (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") | |
8618 | (ior:DI (match_dup 1) (match_dup 2)))] | |
8619 | "TARGET_64BIT | |
8620 | && ix86_match_ccmode (insn, CCNOmode) | |
8621 | && ix86_binary_operator_ok (IOR, DImode, operands)" | |
0f40f9f7 | 8622 | "or{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
8623 | [(set_attr "type" "alu") |
8624 | (set_attr "mode" "DI")]) | |
8625 | ||
8626 | (define_insn "*iordi_3_rex64" | |
8627 | [(set (reg 17) | |
8628 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
8629 | (match_operand:DI 2 "x86_64_general_operand" "rem")) | |
8630 | (const_int 0))) | |
8631 | (clobber (match_scratch:DI 0 "=r"))] | |
8632 | "TARGET_64BIT | |
8633 | && ix86_match_ccmode (insn, CCNOmode) | |
8634 | && ix86_binary_operator_ok (IOR, DImode, operands)" | |
0f40f9f7 | 8635 | "or{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
8636 | [(set_attr "type" "alu") |
8637 | (set_attr "mode" "DI")]) | |
8638 | ||
8639 | ||
e075ae69 RH |
8640 | (define_expand "iorsi3" |
8641 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
8642 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
8643 | (match_operand:SI 2 "general_operand" ""))) | |
8644 | (clobber (reg:CC 17))] | |
57dbca5e | 8645 | "" |
e075ae69 RH |
8646 | "ix86_expand_binary_operator (IOR, SImode, operands); DONE;") |
8647 | ||
8648 | (define_insn "*iorsi_1" | |
8649 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") | |
8650 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
8651 | (match_operand:SI 2 "general_operand" "ri,rmi"))) | |
8652 | (clobber (reg:CC 17))] | |
8653 | "ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8654 | "or{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8655 | [(set_attr "type" "alu") |
8656 | (set_attr "mode" "SI")]) | |
e075ae69 | 8657 | |
9b70259d JH |
8658 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8659 | (define_insn "*iorsi_1_zext" | |
8660 | [(set (match_operand:DI 0 "register_operand" "=rm") | |
8661 | (zero_extend:DI | |
8662 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8663 | (match_operand:SI 2 "general_operand" "rim")))) | |
8664 | (clobber (reg:CC 17))] | |
8665 | "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8666 | "or{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8667 | [(set_attr "type" "alu") |
8668 | (set_attr "mode" "SI")]) | |
8669 | ||
8670 | (define_insn "*iorsi_1_zext_imm" | |
8671 | [(set (match_operand:DI 0 "register_operand" "=rm") | |
8672 | (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) | |
8673 | (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) | |
8674 | (clobber (reg:CC 17))] | |
8675 | "TARGET_64BIT" | |
0f40f9f7 | 8676 | "or{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8677 | [(set_attr "type" "alu") |
8678 | (set_attr "mode" "SI")]) | |
8679 | ||
e075ae69 | 8680 | (define_insn "*iorsi_2" |
16189740 RH |
8681 | [(set (reg 17) |
8682 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
8683 | (match_operand:SI 2 "general_operand" "rim,ri")) | |
8684 | (const_int 0))) | |
e075ae69 RH |
8685 | (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") |
8686 | (ior:SI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8687 | "ix86_match_ccmode (insn, CCNOmode) |
8688 | && ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8689 | "or{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8690 | [(set_attr "type" "alu") |
8691 | (set_attr "mode" "SI")]) | |
e075ae69 | 8692 | |
9b70259d JH |
8693 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8694 | ;; ??? Special case for immediate operand is missing - it is tricky. | |
8695 | (define_insn "*iorsi_2_zext" | |
8696 | [(set (reg 17) | |
8697 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8698 | (match_operand:SI 2 "general_operand" "rim")) | |
8699 | (const_int 0))) | |
8700 | (set (match_operand:DI 0 "register_operand" "=r") | |
8701 | (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))] | |
8702 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8703 | && ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8704 | "or{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8705 | [(set_attr "type" "alu") |
8706 | (set_attr "mode" "SI")]) | |
8707 | ||
8708 | (define_insn "*iorsi_2_zext_imm" | |
8709 | [(set (reg 17) | |
8710 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8711 | (match_operand 2 "x86_64_zext_immediate_operand" "Z")) | |
8712 | (const_int 0))) | |
8713 | (set (match_operand:DI 0 "register_operand" "=r") | |
8714 | (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] | |
8715 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8716 | && ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8717 | "or{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8718 | [(set_attr "type" "alu") |
8719 | (set_attr "mode" "SI")]) | |
8720 | ||
d90ffc8d JH |
8721 | (define_insn "*iorsi_3" |
8722 | [(set (reg 17) | |
8723 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8724 | (match_operand:SI 2 "general_operand" "rim")) | |
8725 | (const_int 0))) | |
8726 | (clobber (match_scratch:SI 0 "=r"))] | |
8727 | "ix86_match_ccmode (insn, CCNOmode) | |
8728 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8729 | "or{l}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8730 | [(set_attr "type" "alu") |
8731 | (set_attr "mode" "SI")]) | |
8732 | ||
e075ae69 RH |
8733 | (define_expand "iorhi3" |
8734 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
8735 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
8736 | (match_operand:HI 2 "general_operand" ""))) | |
8737 | (clobber (reg:CC 17))] | |
d9f32422 | 8738 | "TARGET_HIMODE_MATH" |
e075ae69 RH |
8739 | "ix86_expand_binary_operator (IOR, HImode, operands); DONE;") |
8740 | ||
8741 | (define_insn "*iorhi_1" | |
8742 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m") | |
8743 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
8744 | (match_operand:HI 2 "general_operand" "rmi,ri"))) | |
8745 | (clobber (reg:CC 17))] | |
8746 | "ix86_binary_operator_ok (IOR, HImode, operands)" | |
0f40f9f7 | 8747 | "or{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8748 | [(set_attr "type" "alu") |
8749 | (set_attr "mode" "HI")]) | |
e075ae69 | 8750 | |
e075ae69 | 8751 | (define_insn "*iorhi_2" |
16189740 RH |
8752 | [(set (reg 17) |
8753 | (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
8754 | (match_operand:HI 2 "general_operand" "rim,ri")) | |
8755 | (const_int 0))) | |
e075ae69 RH |
8756 | (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") |
8757 | (ior:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8758 | "ix86_match_ccmode (insn, CCNOmode) |
8759 | && ix86_binary_operator_ok (IOR, HImode, operands)" | |
0f40f9f7 | 8760 | "or{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8761 | [(set_attr "type" "alu") |
8762 | (set_attr "mode" "HI")]) | |
e075ae69 | 8763 | |
d90ffc8d JH |
8764 | (define_insn "*iorhi_3" |
8765 | [(set (reg 17) | |
8766 | (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0") | |
8767 | (match_operand:HI 2 "general_operand" "rim")) | |
8768 | (const_int 0))) | |
8769 | (clobber (match_scratch:HI 0 "=r"))] | |
8770 | "ix86_match_ccmode (insn, CCNOmode) | |
8771 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8772 | "or{w}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8773 | [(set_attr "type" "alu") |
8774 | (set_attr "mode" "HI")]) | |
8775 | ||
e075ae69 RH |
8776 | (define_expand "iorqi3" |
8777 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
8778 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
8779 | (match_operand:QI 2 "general_operand" ""))) | |
8780 | (clobber (reg:CC 17))] | |
d9f32422 | 8781 | "TARGET_QIMODE_MATH" |
e075ae69 RH |
8782 | "ix86_expand_binary_operator (IOR, QImode, operands); DONE;") |
8783 | ||
8784 | ;; %%% Potential partial reg stall on alternative 2. What to do? | |
8785 | (define_insn "*iorqi_1" | |
7c6b971d | 8786 | [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r") |
e075ae69 | 8787 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") |
7c6b971d | 8788 | (match_operand:QI 2 "general_operand" "qmi,qi,ri"))) |
e075ae69 RH |
8789 | (clobber (reg:CC 17))] |
8790 | "ix86_binary_operator_ok (IOR, QImode, operands)" | |
8791 | "@ | |
0f40f9f7 ZW |
8792 | or{b}\t{%2, %0|%0, %2} |
8793 | or{b}\t{%2, %0|%0, %2} | |
8794 | or{l}\t{%k2, %k0|%k0, %k2}" | |
6ef67412 | 8795 | [(set_attr "type" "alu") |
a1b8572c JH |
8796 | (set_attr "mode" "QI,QI,SI")]) |
8797 | ||
8798 | (define_insn "*iorqi_1_slp" | |
8799 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m")) | |
8800 | (ior:QI (match_dup 0) | |
8801 | (match_operand:QI 1 "general_operand" "qmi,qi"))) | |
8802 | (clobber (reg:CC 17))] | |
8803 | "" | |
0f40f9f7 | 8804 | "or{b}\t{%1, %0|%0, %1}" |
a1b8572c | 8805 | [(set_attr "type" "alu1") |
6ef67412 | 8806 | (set_attr "mode" "QI")]) |
e075ae69 RH |
8807 | |
8808 | (define_insn "*iorqi_2" | |
16189740 RH |
8809 | [(set (reg 17) |
8810 | (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") | |
8811 | (match_operand:QI 2 "general_operand" "qim,qi")) | |
8812 | (const_int 0))) | |
e075ae69 RH |
8813 | (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") |
8814 | (ior:QI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8815 | "ix86_match_ccmode (insn, CCNOmode) |
8816 | && ix86_binary_operator_ok (IOR, QImode, operands)" | |
0f40f9f7 | 8817 | "or{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8818 | [(set_attr "type" "alu") |
8819 | (set_attr "mode" "QI")]) | |
d90ffc8d | 8820 | |
a1b8572c JH |
8821 | (define_insn "*iorqi_2_slp" |
8822 | [(set (reg 17) | |
8823 | (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm") | |
8824 | (match_operand:QI 1 "general_operand" "qim,qi")) | |
8825 | (const_int 0))) | |
8826 | (set (strict_low_part (match_dup 0)) | |
8827 | (ior:QI (match_dup 0) (match_dup 1)))] | |
8828 | "ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 8829 | "or{b}\t{%1, %0|%0, %1}" |
a1b8572c JH |
8830 | [(set_attr "type" "alu1") |
8831 | (set_attr "mode" "QI")]) | |
8832 | ||
d90ffc8d JH |
8833 | (define_insn "*iorqi_3" |
8834 | [(set (reg 17) | |
8835 | (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0") | |
8836 | (match_operand:QI 2 "general_operand" "qim")) | |
8837 | (const_int 0))) | |
7e08e190 | 8838 | (clobber (match_scratch:QI 0 "=q"))] |
d90ffc8d JH |
8839 | "ix86_match_ccmode (insn, CCNOmode) |
8840 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8841 | "or{b}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8842 | [(set_attr "type" "alu") |
8843 | (set_attr "mode" "QI")]) | |
8844 | ||
e075ae69 RH |
8845 | \f |
8846 | ;; Logical XOR instructions | |
a269a03c | 8847 | |
e075ae69 RH |
8848 | ;; %%% This used to optimize known byte-wide and operations to memory. |
8849 | ;; If this is considered useful, it should be done with splitters. | |
57dbca5e | 8850 | |
9b70259d JH |
8851 | (define_expand "xordi3" |
8852 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8853 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
8854 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
8855 | (clobber (reg:CC 17))] | |
8856 | "TARGET_64BIT" | |
8857 | "ix86_expand_binary_operator (XOR, DImode, operands); DONE;") | |
8858 | ||
8859 | (define_insn "*xordi_1_rex64" | |
8860 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
8861 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
8862 | (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) | |
8863 | (clobber (reg:CC 17))] | |
8864 | "TARGET_64BIT | |
8865 | && ix86_binary_operator_ok (XOR, DImode, operands)" | |
8866 | "@ | |
0f40f9f7 ZW |
8867 | xor{q}\t{%2, %0|%0, %2} |
8868 | xor{q}\t{%2, %0|%0, %2}" | |
9b70259d JH |
8869 | [(set_attr "type" "alu") |
8870 | (set_attr "mode" "DI,DI")]) | |
8871 | ||
8872 | (define_insn "*xordi_2_rex64" | |
8873 | [(set (reg 17) | |
8874 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
8875 | (match_operand:DI 2 "x86_64_general_operand" "rem,re")) | |
8876 | (const_int 0))) | |
8877 | (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") | |
8878 | (xor:DI (match_dup 1) (match_dup 2)))] | |
8879 | "TARGET_64BIT | |
8880 | && ix86_match_ccmode (insn, CCNOmode) | |
8881 | && ix86_binary_operator_ok (XOR, DImode, operands)" | |
8882 | "@ | |
0f40f9f7 ZW |
8883 | xor{q}\t{%2, %0|%0, %2} |
8884 | xor{q}\t{%2, %0|%0, %2}" | |
9b70259d JH |
8885 | [(set_attr "type" "alu") |
8886 | (set_attr "mode" "DI,DI")]) | |
8887 | ||
8888 | (define_insn "*xordi_3_rex64" | |
8889 | [(set (reg 17) | |
8890 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
8891 | (match_operand:DI 2 "x86_64_general_operand" "rem")) | |
8892 | (const_int 0))) | |
8893 | (clobber (match_scratch:DI 0 "=r"))] | |
8894 | "TARGET_64BIT | |
8895 | && ix86_match_ccmode (insn, CCNOmode) | |
8896 | && ix86_binary_operator_ok (XOR, DImode, operands)" | |
0f40f9f7 | 8897 | "xor{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
8898 | [(set_attr "type" "alu") |
8899 | (set_attr "mode" "DI")]) | |
8900 | ||
e075ae69 RH |
8901 | (define_expand "xorsi3" |
8902 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
8903 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
8904 | (match_operand:SI 2 "general_operand" ""))) | |
8905 | (clobber (reg:CC 17))] | |
57dbca5e | 8906 | "" |
e075ae69 | 8907 | "ix86_expand_binary_operator (XOR, SImode, operands); DONE;") |
a269a03c | 8908 | |
e075ae69 RH |
8909 | (define_insn "*xorsi_1" |
8910 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") | |
8911 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
8912 | (match_operand:SI 2 "general_operand" "ri,rm"))) | |
8913 | (clobber (reg:CC 17))] | |
8914 | "ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8915 | "xor{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8916 | [(set_attr "type" "alu") |
8917 | (set_attr "mode" "SI")]) | |
e075ae69 | 8918 | |
9b70259d JH |
8919 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8920 | ;; Add speccase for immediates | |
8921 | (define_insn "*xorsi_1_zext" | |
8922 | [(set (match_operand:DI 0 "register_operand" "=r") | |
8923 | (zero_extend:DI | |
8924 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8925 | (match_operand:SI 2 "general_operand" "rim")))) | |
8926 | (clobber (reg:CC 17))] | |
8927 | "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8928 | "xor{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8929 | [(set_attr "type" "alu") |
8930 | (set_attr "mode" "SI")]) | |
8931 | ||
8932 | (define_insn "*xorsi_1_zext_imm" | |
8933 | [(set (match_operand:DI 0 "register_operand" "=r") | |
8934 | (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) | |
8935 | (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) | |
8936 | (clobber (reg:CC 17))] | |
8937 | "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8938 | "xor{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8939 | [(set_attr "type" "alu") |
8940 | (set_attr "mode" "SI")]) | |
8941 | ||
e075ae69 | 8942 | (define_insn "*xorsi_2" |
16189740 RH |
8943 | [(set (reg 17) |
8944 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
8945 | (match_operand:SI 2 "general_operand" "rim,ri")) | |
8946 | (const_int 0))) | |
e075ae69 RH |
8947 | (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") |
8948 | (xor:SI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8949 | "ix86_match_ccmode (insn, CCNOmode) |
8950 | && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8951 | "xor{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8952 | [(set_attr "type" "alu") |
8953 | (set_attr "mode" "SI")]) | |
e075ae69 | 8954 | |
9b70259d JH |
8955 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8956 | ;; ??? Special case for immediate operand is missing - it is tricky. | |
8957 | (define_insn "*xorsi_2_zext" | |
8958 | [(set (reg 17) | |
8959 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8960 | (match_operand:SI 2 "general_operand" "rim")) | |
8961 | (const_int 0))) | |
8962 | (set (match_operand:DI 0 "register_operand" "=r") | |
8963 | (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))] | |
8964 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8965 | && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8966 | "xor{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8967 | [(set_attr "type" "alu") |
8968 | (set_attr "mode" "SI")]) | |
8969 | ||
8970 | (define_insn "*xorsi_2_zext_imm" | |
8971 | [(set (reg 17) | |
8972 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8973 | (match_operand 2 "x86_64_zext_immediate_operand" "Z")) | |
8974 | (const_int 0))) | |
8975 | (set (match_operand:DI 0 "register_operand" "=r") | |
8976 | (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] | |
8977 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8978 | && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8979 | "xor{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8980 | [(set_attr "type" "alu") |
8981 | (set_attr "mode" "SI")]) | |
8982 | ||
d90ffc8d JH |
8983 | (define_insn "*xorsi_3" |
8984 | [(set (reg 17) | |
8985 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8986 | (match_operand:SI 2 "general_operand" "rim")) | |
8987 | (const_int 0))) | |
8988 | (clobber (match_scratch:SI 0 "=r"))] | |
8989 | "ix86_match_ccmode (insn, CCNOmode) | |
8990 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8991 | "xor{l}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8992 | [(set_attr "type" "alu") |
8993 | (set_attr "mode" "SI")]) | |
8994 | ||
e075ae69 RH |
8995 | (define_expand "xorhi3" |
8996 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
8997 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
8998 | (match_operand:HI 2 "general_operand" ""))) | |
8999 | (clobber (reg:CC 17))] | |
d9f32422 | 9000 | "TARGET_HIMODE_MATH" |
e075ae69 RH |
9001 | "ix86_expand_binary_operator (XOR, HImode, operands); DONE;") |
9002 | ||
9003 | (define_insn "*xorhi_1" | |
9004 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m") | |
9005 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
9006 | (match_operand:HI 2 "general_operand" "rmi,ri"))) | |
9007 | (clobber (reg:CC 17))] | |
9008 | "ix86_binary_operator_ok (XOR, HImode, operands)" | |
0f40f9f7 | 9009 | "xor{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
9010 | [(set_attr "type" "alu") |
9011 | (set_attr "mode" "HI")]) | |
57dbca5e | 9012 | |
e075ae69 | 9013 | (define_insn "*xorhi_2" |
16189740 RH |
9014 | [(set (reg 17) |
9015 | (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
9016 | (match_operand:HI 2 "general_operand" "rim,ri")) | |
9017 | (const_int 0))) | |
e075ae69 RH |
9018 | (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") |
9019 | (xor:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
9020 | "ix86_match_ccmode (insn, CCNOmode) |
9021 | && ix86_binary_operator_ok (XOR, HImode, operands)" | |
0f40f9f7 | 9022 | "xor{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
9023 | [(set_attr "type" "alu") |
9024 | (set_attr "mode" "HI")]) | |
e075ae69 | 9025 | |
d90ffc8d JH |
9026 | (define_insn "*xorhi_3" |
9027 | [(set (reg 17) | |
9028 | (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0") | |
9029 | (match_operand:HI 2 "general_operand" "rim")) | |
9030 | (const_int 0))) | |
9031 | (clobber (match_scratch:HI 0 "=r"))] | |
9032 | "ix86_match_ccmode (insn, CCNOmode) | |
9033 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 9034 | "xor{w}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
9035 | [(set_attr "type" "alu") |
9036 | (set_attr "mode" "HI")]) | |
9037 | ||
e075ae69 RH |
9038 | (define_expand "xorqi3" |
9039 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
9040 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
9041 | (match_operand:QI 2 "general_operand" ""))) | |
9042 | (clobber (reg:CC 17))] | |
d9f32422 | 9043 | "TARGET_QIMODE_MATH" |
e075ae69 RH |
9044 | "ix86_expand_binary_operator (XOR, QImode, operands); DONE;") |
9045 | ||
9046 | ;; %%% Potential partial reg stall on alternative 2. What to do? | |
9047 | (define_insn "*xorqi_1" | |
7c6b971d | 9048 | [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r") |
e075ae69 | 9049 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") |
7c6b971d | 9050 | (match_operand:QI 2 "general_operand" "qmi,qi,ri"))) |
e075ae69 RH |
9051 | (clobber (reg:CC 17))] |
9052 | "ix86_binary_operator_ok (XOR, QImode, operands)" | |
9053 | "@ | |
0f40f9f7 ZW |
9054 | xor{b}\t{%2, %0|%0, %2} |
9055 | xor{b}\t{%2, %0|%0, %2} | |
9056 | xor{l}\t{%k2, %k0|%k0, %k2}" | |
6ef67412 JH |
9057 | [(set_attr "type" "alu") |
9058 | (set_attr "mode" "QI,QI,SI")]) | |
9059 | ||
a4414093 | 9060 | (define_insn "*xorqi_ext_1" |
d2836273 | 9061 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
6ef67412 JH |
9062 | (const_int 8) |
9063 | (const_int 8)) | |
9064 | (xor:SI | |
9065 | (zero_extract:SI (match_operand 1 "ext_register_operand" "0") | |
9066 | (const_int 8) | |
9067 | (const_int 8)) | |
d2836273 | 9068 | (zero_extract:SI (match_operand 2 "ext_register_operand" "Q") |
6ef67412 JH |
9069 | (const_int 8) |
9070 | (const_int 8)))) | |
9071 | (clobber (reg:CC 17))] | |
9072 | "" | |
0f40f9f7 | 9073 | "xor{b}\t{%h2, %h0|%h0, %h2}" |
6ef67412 JH |
9074 | [(set_attr "type" "alu") |
9075 | (set_attr "length_immediate" "0") | |
9076 | (set_attr "mode" "QI")]) | |
e075ae69 | 9077 | |
7abd4e00 | 9078 | (define_insn "*xorqi_cc_1" |
16189740 RH |
9079 | [(set (reg 17) |
9080 | (compare | |
e075ae69 RH |
9081 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") |
9082 | (match_operand:QI 2 "general_operand" "qim,qi")) | |
9083 | (const_int 0))) | |
9084 | (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") | |
9085 | (xor:QI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
9086 | "ix86_match_ccmode (insn, CCNOmode) |
9087 | && ix86_binary_operator_ok (XOR, QImode, operands)" | |
0f40f9f7 | 9088 | "xor{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
9089 | [(set_attr "type" "alu") |
9090 | (set_attr "mode" "QI")]) | |
e075ae69 | 9091 | |
d90ffc8d JH |
9092 | (define_insn "*xorqi_cc_2" |
9093 | [(set (reg 17) | |
9094 | (compare | |
9095 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0") | |
9096 | (match_operand:QI 2 "general_operand" "qim")) | |
9097 | (const_int 0))) | |
7e08e190 | 9098 | (clobber (match_scratch:QI 0 "=q"))] |
d90ffc8d JH |
9099 | "ix86_match_ccmode (insn, CCNOmode) |
9100 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 9101 | "xor{b}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
9102 | [(set_attr "type" "alu") |
9103 | (set_attr "mode" "QI")]) | |
9104 | ||
9076b9c1 JH |
9105 | (define_insn "*xorqi_cc_ext_1" |
9106 | [(set (reg 17) | |
9107 | (compare | |
e075ae69 RH |
9108 | (xor:SI |
9109 | (zero_extract:SI | |
9110 | (match_operand 1 "ext_register_operand" "0") | |
9111 | (const_int 8) | |
9112 | (const_int 8)) | |
9113 | (match_operand:QI 2 "general_operand" "qmn")) | |
9114 | (const_int 0))) | |
9115 | (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q") | |
9116 | (const_int 8) | |
9117 | (const_int 8)) | |
9118 | (xor:SI | |
9119 | (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) | |
9120 | (match_dup 2)))] | |
d2836273 | 9121 | "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 9122 | "xor{b}\t{%2, %h0|%h0, %2}" |
d2836273 JH |
9123 | [(set_attr "type" "alu") |
9124 | (set_attr "mode" "QI")]) | |
9125 | ||
9126 | (define_insn "*xorqi_cc_ext_1_rex64" | |
9127 | [(set (reg 17) | |
9128 | (compare | |
9129 | (xor:SI | |
9130 | (zero_extract:SI | |
9131 | (match_operand 1 "ext_register_operand" "0") | |
9132 | (const_int 8) | |
9133 | (const_int 8)) | |
9134 | (match_operand:QI 2 "nonmemory_operand" "Qn")) | |
9135 | (const_int 0))) | |
9136 | (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
9137 | (const_int 8) | |
9138 | (const_int 8)) | |
9139 | (xor:SI | |
9140 | (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) | |
9141 | (match_dup 2)))] | |
9142 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 9143 | "xor{b}\t{%2, %h0|%h0, %2}" |
6ef67412 JH |
9144 | [(set_attr "type" "alu") |
9145 | (set_attr "mode" "QI")]) | |
9076b9c1 JH |
9146 | |
9147 | (define_expand "xorqi_cc_ext_1" | |
9148 | [(parallel [ | |
9149 | (set (reg:CCNO 17) | |
9150 | (compare:CCNO | |
9151 | (xor:SI | |
9152 | (zero_extract:SI | |
9153 | (match_operand 1 "ext_register_operand" "") | |
9154 | (const_int 8) | |
9155 | (const_int 8)) | |
9156 | (match_operand:QI 2 "general_operand" "")) | |
9157 | (const_int 0))) | |
9158 | (set (zero_extract:SI (match_operand 0 "ext_register_operand" "") | |
9159 | (const_int 8) | |
9160 | (const_int 8)) | |
9161 | (xor:SI | |
9162 | (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) | |
9163 | (match_dup 2)))])] | |
9164 | "" | |
9165 | "") | |
e075ae69 RH |
9166 | \f |
9167 | ;; Negation instructions | |
57dbca5e | 9168 | |
06a964de JH |
9169 | (define_expand "negdi2" |
9170 | [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
2756c3d8 | 9171 | (neg:DI (match_operand:DI 1 "nonimmediate_operand" ""))) |
06a964de JH |
9172 | (clobber (reg:CC 17))])] |
9173 | "" | |
9174 | "ix86_expand_unary_operator (NEG, DImode, operands); DONE;") | |
9175 | ||
9176 | (define_insn "*negdi2_1" | |
e075ae69 RH |
9177 | [(set (match_operand:DI 0 "nonimmediate_operand" "=ro") |
9178 | (neg:DI (match_operand:DI 1 "general_operand" "0"))) | |
9179 | (clobber (reg:CC 17))] | |
d2836273 JH |
9180 | "!TARGET_64BIT |
9181 | && ix86_unary_operator_ok (NEG, DImode, operands)" | |
e075ae69 | 9182 | "#") |
886c62d1 | 9183 | |
e075ae69 RH |
9184 | (define_split |
9185 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
9186 | (neg:DI (match_operand:DI 1 "general_operand" ""))) | |
9187 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9188 | "!TARGET_64BIT && reload_completed" |
e075ae69 | 9189 | [(parallel |
16189740 RH |
9190 | [(set (reg:CCZ 17) |
9191 | (compare:CCZ (neg:SI (match_dup 2)) (const_int 0))) | |
e075ae69 RH |
9192 | (set (match_dup 0) (neg:SI (match_dup 2)))]) |
9193 | (parallel | |
9194 | [(set (match_dup 1) | |
7e08e190 | 9195 | (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
9dcbdc7e JH |
9196 | (match_dup 3)) |
9197 | (const_int 0))) | |
e075ae69 RH |
9198 | (clobber (reg:CC 17))]) |
9199 | (parallel | |
9200 | [(set (match_dup 1) | |
9201 | (neg:SI (match_dup 1))) | |
9202 | (clobber (reg:CC 17))])] | |
9203 | "split_di (operands+1, 1, operands+2, operands+3); | |
9204 | split_di (operands+0, 1, operands+0, operands+1);") | |
886c62d1 | 9205 | |
9b70259d JH |
9206 | (define_insn "*negdi2_1_rex64" |
9207 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
9208 | (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))) | |
9209 | (clobber (reg:CC 17))] | |
9210 | "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)" | |
0f40f9f7 | 9211 | "neg{q}\t%0" |
9b70259d JH |
9212 | [(set_attr "type" "negnot") |
9213 | (set_attr "mode" "DI")]) | |
9214 | ||
9215 | ;; The problem with neg is that it does not perform (compare x 0), | |
9216 | ;; it really performs (compare 0 x), which leaves us with the zero | |
9217 | ;; flag being the only useful item. | |
9218 | ||
9219 | (define_insn "*negdi2_cmpz_rex64" | |
9220 | [(set (reg:CCZ 17) | |
9221 | (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")) | |
9222 | (const_int 0))) | |
9223 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
9224 | (neg:DI (match_dup 1)))] | |
9225 | "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)" | |
0f40f9f7 | 9226 | "neg{q}\t%0" |
9b70259d JH |
9227 | [(set_attr "type" "negnot") |
9228 | (set_attr "mode" "DI")]) | |
9229 | ||
9230 | ||
06a964de JH |
9231 | (define_expand "negsi2" |
9232 | [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
2756c3d8 | 9233 | (neg:SI (match_operand:SI 1 "nonimmediate_operand" ""))) |
06a964de JH |
9234 | (clobber (reg:CC 17))])] |
9235 | "" | |
9236 | "ix86_expand_unary_operator (NEG, SImode, operands); DONE;") | |
9237 | ||
9238 | (define_insn "*negsi2_1" | |
2ae0f82c | 9239 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
e075ae69 RH |
9240 | (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))) |
9241 | (clobber (reg:CC 17))] | |
06a964de | 9242 | "ix86_unary_operator_ok (NEG, SImode, operands)" |
0f40f9f7 | 9243 | "neg{l}\t%0" |
6ef67412 JH |
9244 | [(set_attr "type" "negnot") |
9245 | (set_attr "mode" "SI")]) | |
e075ae69 | 9246 | |
9b70259d JH |
9247 | ;; Combine is quite creative about this pattern. |
9248 | (define_insn "*negsi2_1_zext" | |
9249 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9250 | (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
9251 | (const_int 32))) | |
9252 | (const_int 32))) | |
9253 | (clobber (reg:CC 17))] | |
9254 | "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)" | |
0f40f9f7 | 9255 | "neg{l}\t%k0" |
9b70259d JH |
9256 | [(set_attr "type" "negnot") |
9257 | (set_attr "mode" "SI")]) | |
9258 | ||
16189740 RH |
9259 | ;; The problem with neg is that it does not perform (compare x 0), |
9260 | ;; it really performs (compare 0 x), which leaves us with the zero | |
9261 | ;; flag being the only useful item. | |
e075ae69 | 9262 | |
16189740 RH |
9263 | (define_insn "*negsi2_cmpz" |
9264 | [(set (reg:CCZ 17) | |
9265 | (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")) | |
9266 | (const_int 0))) | |
e075ae69 RH |
9267 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
9268 | (neg:SI (match_dup 1)))] | |
06a964de | 9269 | "ix86_unary_operator_ok (NEG, SImode, operands)" |
0f40f9f7 | 9270 | "neg{l}\t%0" |
6ef67412 JH |
9271 | [(set_attr "type" "negnot") |
9272 | (set_attr "mode" "SI")]) | |
886c62d1 | 9273 | |
9b70259d JH |
9274 | (define_insn "*negsi2_cmpz_zext" |
9275 | [(set (reg:CCZ 17) | |
9276 | (compare:CCZ (lshiftrt:DI | |
9277 | (neg:DI (ashift:DI | |
9278 | (match_operand:DI 1 "register_operand" "0") | |
9279 | (const_int 32))) | |
9280 | (const_int 32)) | |
9281 | (const_int 0))) | |
9282 | (set (match_operand:DI 0 "register_operand" "=r") | |
9283 | (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1) | |
9284 | (const_int 32))) | |
9285 | (const_int 32)))] | |
9286 | "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)" | |
0f40f9f7 | 9287 | "neg{l}\t%k0" |
9b70259d JH |
9288 | [(set_attr "type" "negnot") |
9289 | (set_attr "mode" "SI")]) | |
9290 | ||
06a964de JH |
9291 | (define_expand "neghi2" |
9292 | [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2756c3d8 | 9293 | (neg:HI (match_operand:HI 1 "nonimmediate_operand" ""))) |
06a964de | 9294 | (clobber (reg:CC 17))])] |
d9f32422 | 9295 | "TARGET_HIMODE_MATH" |
06a964de JH |
9296 | "ix86_expand_unary_operator (NEG, HImode, operands); DONE;") |
9297 | ||
9298 | (define_insn "*neghi2_1" | |
2ae0f82c | 9299 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
e075ae69 RH |
9300 | (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))) |
9301 | (clobber (reg:CC 17))] | |
06a964de | 9302 | "ix86_unary_operator_ok (NEG, HImode, operands)" |
0f40f9f7 | 9303 | "neg{w}\t%0" |
6ef67412 JH |
9304 | [(set_attr "type" "negnot") |
9305 | (set_attr "mode" "HI")]) | |
e075ae69 | 9306 | |
16189740 RH |
9307 | (define_insn "*neghi2_cmpz" |
9308 | [(set (reg:CCZ 17) | |
9309 | (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")) | |
9310 | (const_int 0))) | |
e075ae69 RH |
9311 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
9312 | (neg:HI (match_dup 1)))] | |
06a964de | 9313 | "ix86_unary_operator_ok (NEG, HImode, operands)" |
0f40f9f7 | 9314 | "neg{w}\t%0" |
6ef67412 JH |
9315 | [(set_attr "type" "negnot") |
9316 | (set_attr "mode" "HI")]) | |
886c62d1 | 9317 | |
06a964de JH |
9318 | (define_expand "negqi2" |
9319 | [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2756c3d8 | 9320 | (neg:QI (match_operand:QI 1 "nonimmediate_operand" ""))) |
06a964de | 9321 | (clobber (reg:CC 17))])] |
d9f32422 | 9322 | "TARGET_QIMODE_MATH" |
06a964de JH |
9323 | "ix86_expand_unary_operator (NEG, QImode, operands); DONE;") |
9324 | ||
9325 | (define_insn "*negqi2_1" | |
2ae0f82c | 9326 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
e075ae69 RH |
9327 | (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))) |
9328 | (clobber (reg:CC 17))] | |
06a964de | 9329 | "ix86_unary_operator_ok (NEG, QImode, operands)" |
0f40f9f7 | 9330 | "neg{b}\t%0" |
6ef67412 JH |
9331 | [(set_attr "type" "negnot") |
9332 | (set_attr "mode" "QI")]) | |
e075ae69 | 9333 | |
16189740 RH |
9334 | (define_insn "*negqi2_cmpz" |
9335 | [(set (reg:CCZ 17) | |
9336 | (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")) | |
9337 | (const_int 0))) | |
e075ae69 RH |
9338 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
9339 | (neg:QI (match_dup 1)))] | |
06a964de | 9340 | "ix86_unary_operator_ok (NEG, QImode, operands)" |
0f40f9f7 | 9341 | "neg{b}\t%0" |
6ef67412 JH |
9342 | [(set_attr "type" "negnot") |
9343 | (set_attr "mode" "QI")]) | |
886c62d1 | 9344 | |
06a964de | 9345 | ;; Changing of sign for FP values is doable using integer unit too. |
1ce485ec | 9346 | |
06a964de JH |
9347 | (define_expand "negsf2" |
9348 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9349 | (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) |
06a964de JH |
9350 | (clobber (reg:CC 17))])] |
9351 | "TARGET_80387" | |
b3298882 JH |
9352 | "if (TARGET_SSE) |
9353 | { | |
9354 | /* In case operand is in memory, we will not use SSE. */ | |
9355 | if (memory_operand (operands[0], VOIDmode) | |
9356 | && rtx_equal_p (operands[0], operands[1])) | |
9357 | emit_insn (gen_negsf2_memory (operands[0], operands[1])); | |
9358 | else | |
9359 | { | |
9360 | /* Using SSE is tricky, since we need bitwise negation of -0 | |
9361 | in register. */ | |
9362 | rtx reg = gen_reg_rtx (SFmode); | |
141e454b JH |
9363 | rtx dest = operands[0]; |
9364 | ||
9365 | operands[1] = force_reg (SFmode, operands[1]); | |
9366 | operands[0] = force_reg (SFmode, operands[0]); | |
b3298882 JH |
9367 | emit_move_insn (reg, |
9368 | gen_lowpart (SFmode, | |
141e454b JH |
9369 | GEN_INT (trunc_int_for_mode (0x80000000, |
9370 | SImode)))); | |
b3298882 | 9371 | emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg)); |
141e454b JH |
9372 | if (dest != operands[0]) |
9373 | emit_move_insn (dest, operands[0]); | |
b3298882 JH |
9374 | } |
9375 | DONE; | |
9376 | } | |
9377 | ix86_expand_unary_operator (NEG, SFmode, operands); DONE;") | |
9378 | ||
9379 | (define_insn "negsf2_memory" | |
9380 | [(set (match_operand:SF 0 "memory_operand" "=m") | |
9381 | (neg:SF (match_operand:SF 1 "memory_operand" "0"))) | |
9382 | (clobber (reg:CC 17))] | |
9383 | "ix86_unary_operator_ok (NEG, SFmode, operands)" | |
9384 | "#") | |
9385 | ||
9386 | (define_insn "negsf2_ifs" | |
141e454b | 9387 | [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf") |
b3298882 | 9388 | (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0"))) |
141e454b | 9389 | (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x")) |
b3298882 | 9390 | (clobber (reg:CC 17))] |
141e454b JH |
9391 | "TARGET_SSE |
9392 | && (reload_in_progress || reload_completed | |
9393 | || (register_operand (operands[0], VOIDmode) | |
9394 | && register_operand (operands[1], VOIDmode)))" | |
b3298882 JH |
9395 | "#") |
9396 | ||
9397 | (define_split | |
9398 | [(set (match_operand:SF 0 "memory_operand" "") | |
9399 | (neg:SF (match_operand:SF 1 "memory_operand" ""))) | |
9400 | (use (match_operand:SF 2 "" "")) | |
9401 | (clobber (reg:CC 17))] | |
9402 | "" | |
9403 | [(parallel [(set (match_dup 0) | |
9404 | (neg:SF (match_dup 1))) | |
9405 | (clobber (reg:CC 17))])]) | |
9406 | ||
9407 | (define_split | |
9408 | [(set (match_operand:SF 0 "register_operand" "") | |
9409 | (neg:SF (match_operand:SF 1 "register_operand" ""))) | |
9410 | (use (match_operand:SF 2 "" "")) | |
9411 | (clobber (reg:CC 17))] | |
9412 | "reload_completed && !SSE_REG_P (operands[0])" | |
9413 | [(parallel [(set (match_dup 0) | |
9414 | (neg:SF (match_dup 1))) | |
9415 | (clobber (reg:CC 17))])]) | |
9416 | ||
9417 | (define_split | |
9418 | [(set (match_operand:SF 0 "register_operand" "") | |
9419 | (neg:SF (match_operand:SF 1 "register_operand" ""))) | |
9420 | (use (match_operand:SF 2 "register_operand" "")) | |
9421 | (clobber (reg:CC 17))] | |
9422 | "reload_completed && SSE_REG_P (operands[0])" | |
9423 | [(set (subreg:TI (match_dup 0) 0) | |
9424 | (xor:TI (subreg:TI (match_dup 1) 0) | |
9425 | (subreg:TI (match_dup 2) 0)))] | |
b3298882 JH |
9426 | { |
9427 | if (operands_match_p (operands[0], operands[2])) | |
9428 | { | |
9429 | rtx tmp; | |
9430 | tmp = operands[1]; | |
9431 | operands[1] = operands[2]; | |
9432 | operands[2] = tmp; | |
9433 | } | |
0f40f9f7 | 9434 | }) |
b3298882 | 9435 | |
06a964de | 9436 | |
e20440c1 JH |
9437 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9438 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9439 | ;; to itself. | |
06a964de | 9440 | (define_insn "*negsf2_if" |
e20440c1 JH |
9441 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") |
9442 | (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 9443 | (clobber (reg:CC 17))] |
b3298882 JH |
9444 | "TARGET_80387 && !TARGET_SSE |
9445 | && ix86_unary_operator_ok (NEG, SFmode, operands)" | |
1ce485ec JH |
9446 | "#") |
9447 | ||
9448 | (define_split | |
9449 | [(set (match_operand:SF 0 "register_operand" "") | |
9450 | (neg:SF (match_operand:SF 1 "register_operand" ""))) | |
9451 | (clobber (reg:CC 17))] | |
9452 | "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed" | |
9453 | [(set (match_dup 0) | |
9454 | (neg:SF (match_dup 1)))] | |
9455 | "") | |
9456 | ||
9457 | (define_split | |
9458 | [(set (match_operand:SF 0 "register_operand" "") | |
9459 | (neg:SF (match_operand:SF 1 "register_operand" ""))) | |
9460 | (clobber (reg:CC 17))] | |
9461 | "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))" | |
9462 | [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) | |
9463 | (clobber (reg:CC 17))])] | |
383252a7 | 9464 | "operands[1] = GEN_INT (trunc_int_for_mode (0x80000000, SImode)); |
1ce485ec JH |
9465 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") |
9466 | ||
9467 | (define_split | |
9468 | [(set (match_operand 0 "memory_operand" "") | |
9469 | (neg (match_operand 1 "memory_operand" ""))) | |
9470 | (clobber (reg:CC 17))] | |
9471 | "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" | |
9472 | [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
9473 | (clobber (reg:CC 17))])] | |
1ce485ec JH |
9474 | { |
9475 | int size = GET_MODE_SIZE (GET_MODE (operands[1])); | |
9476 | ||
b3298882 JH |
9477 | /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */ |
9478 | if (size >= 12) | |
1ce485ec | 9479 | size = 10; |
b72f00af | 9480 | operands[0] = adjust_address (operands[0], QImode, size - 1); |
383252a7 | 9481 | operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode)); |
0f40f9f7 | 9482 | }) |
1ce485ec | 9483 | |
06a964de JH |
9484 | (define_expand "negdf2" |
9485 | [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9486 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) |
06a964de JH |
9487 | (clobber (reg:CC 17))])] |
9488 | "TARGET_80387" | |
141e454b | 9489 | "if (TARGET_SSE2) |
b3298882 JH |
9490 | { |
9491 | /* In case operand is in memory, we will not use SSE. */ | |
9492 | if (memory_operand (operands[0], VOIDmode) | |
9493 | && rtx_equal_p (operands[0], operands[1])) | |
9494 | emit_insn (gen_negdf2_memory (operands[0], operands[1])); | |
9495 | else | |
9496 | { | |
9497 | /* Using SSE is tricky, since we need bitwise negation of -0 | |
9498 | in register. */ | |
9499 | rtx reg = gen_reg_rtx (DFmode); | |
9500 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
141e454b JH |
9501 | rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63, |
9502 | DImode)); | |
b3298882 JH |
9503 | #else |
9504 | rtx imm = immed_double_const (0, 0x80000000, DImode); | |
9505 | #endif | |
141e454b JH |
9506 | rtx dest = operands[0]; |
9507 | ||
9508 | operands[1] = force_reg (DFmode, operands[1]); | |
9509 | operands[0] = force_reg (DFmode, operands[0]); | |
b3298882 JH |
9510 | emit_move_insn (reg, gen_lowpart (DFmode, imm)); |
9511 | emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg)); | |
141e454b JH |
9512 | if (dest != operands[0]) |
9513 | emit_move_insn (dest, operands[0]); | |
b3298882 JH |
9514 | } |
9515 | DONE; | |
9516 | } | |
9517 | ix86_expand_unary_operator (NEG, DFmode, operands); DONE;") | |
9518 | ||
9519 | (define_insn "negdf2_memory" | |
9520 | [(set (match_operand:DF 0 "memory_operand" "=m") | |
9521 | (neg:DF (match_operand:DF 1 "memory_operand" "0"))) | |
9522 | (clobber (reg:CC 17))] | |
9523 | "ix86_unary_operator_ok (NEG, DFmode, operands)" | |
9524 | "#") | |
9525 | ||
9526 | (define_insn "negdf2_ifs" | |
141e454b JH |
9527 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf") |
9528 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0"))) | |
9529 | (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y")) | |
b3298882 | 9530 | (clobber (reg:CC 17))] |
1b0c37d7 | 9531 | "!TARGET_64BIT && TARGET_SSE2 |
141e454b JH |
9532 | && (reload_in_progress || reload_completed |
9533 | || (register_operand (operands[0], VOIDmode) | |
9534 | && register_operand (operands[1], VOIDmode)))" | |
9535 | "#") | |
9536 | ||
9537 | (define_insn "*negdf2_ifs_rex64" | |
9538 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf") | |
9539 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0"))) | |
9540 | (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm")) | |
9541 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9542 | "TARGET_64BIT && TARGET_SSE2 |
141e454b JH |
9543 | && (reload_in_progress || reload_completed |
9544 | || (register_operand (operands[0], VOIDmode) | |
9545 | && register_operand (operands[1], VOIDmode)))" | |
b3298882 JH |
9546 | "#") |
9547 | ||
9548 | (define_split | |
9549 | [(set (match_operand:DF 0 "memory_operand" "") | |
9550 | (neg:DF (match_operand:DF 1 "memory_operand" ""))) | |
9551 | (use (match_operand:DF 2 "" "")) | |
9552 | (clobber (reg:CC 17))] | |
9553 | "" | |
9554 | [(parallel [(set (match_dup 0) | |
9555 | (neg:DF (match_dup 1))) | |
9556 | (clobber (reg:CC 17))])]) | |
9557 | ||
9558 | (define_split | |
9559 | [(set (match_operand:DF 0 "register_operand" "") | |
9560 | (neg:DF (match_operand:DF 1 "register_operand" ""))) | |
9561 | (use (match_operand:DF 2 "" "")) | |
9562 | (clobber (reg:CC 17))] | |
141e454b JH |
9563 | "reload_completed && !SSE_REG_P (operands[0]) |
9564 | && (!TARGET_64BIT || FP_REG_P (operands[0]))" | |
b3298882 JH |
9565 | [(parallel [(set (match_dup 0) |
9566 | (neg:DF (match_dup 1))) | |
9567 | (clobber (reg:CC 17))])]) | |
9568 | ||
141e454b JH |
9569 | (define_split |
9570 | [(set (match_operand:DF 0 "register_operand" "") | |
9571 | (neg:DF (match_operand:DF 1 "register_operand" ""))) | |
9572 | (use (match_operand:DF 2 "" "")) | |
9573 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9574 | "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])" |
141e454b JH |
9575 | [(parallel [(set (match_dup 0) |
9576 | (xor:DI (match_dup 1) (match_dup 2))) | |
9577 | (clobber (reg:CC 17))])] | |
9578 | "operands[0] = gen_lowpart (DImode, operands[0]); | |
9579 | operands[1] = gen_lowpart (DImode, operands[1]); | |
9580 | operands[2] = gen_lowpart (DImode, operands[2]);") | |
9581 | ||
b3298882 JH |
9582 | (define_split |
9583 | [(set (match_operand:DF 0 "register_operand" "") | |
9584 | (neg:DF (match_operand:DF 1 "register_operand" ""))) | |
9585 | (use (match_operand:DF 2 "register_operand" "")) | |
9586 | (clobber (reg:CC 17))] | |
9587 | "reload_completed && SSE_REG_P (operands[0])" | |
9588 | [(set (subreg:TI (match_dup 0) 0) | |
9589 | (xor:TI (subreg:TI (match_dup 1) 0) | |
9590 | (subreg:TI (match_dup 2) 0)))] | |
b3298882 JH |
9591 | { |
9592 | if (operands_match_p (operands[0], operands[2])) | |
9593 | { | |
9594 | rtx tmp; | |
9595 | tmp = operands[1]; | |
9596 | operands[1] = operands[2]; | |
9597 | operands[2] = tmp; | |
9598 | } | |
0f40f9f7 | 9599 | }) |
06a964de | 9600 | |
e20440c1 JH |
9601 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9602 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9603 | ;; to itself. | |
06a964de | 9604 | (define_insn "*negdf2_if" |
e20440c1 JH |
9605 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f") |
9606 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 9607 | (clobber (reg:CC 17))] |
1b0c37d7 | 9608 | "!TARGET_64BIT && TARGET_80387 |
141e454b JH |
9609 | && ix86_unary_operator_ok (NEG, DFmode, operands)" |
9610 | "#") | |
9611 | ||
9612 | ;; FIXME: We should to allow integer registers here. Problem is that | |
9613 | ;; we need another scratch register to get constant from. | |
9614 | ;; Forcing constant to mem if no register available in peep2 should be | |
9615 | ;; safe even for PIC mode, because of RIP relative addressing. | |
9616 | (define_insn "*negdf2_if_rex64" | |
9617 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf") | |
9618 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) | |
9619 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9620 | "TARGET_64BIT && TARGET_80387 |
141e454b | 9621 | && ix86_unary_operator_ok (NEG, DFmode, operands)" |
1ce485ec JH |
9622 | "#") |
9623 | ||
9624 | (define_split | |
9625 | [(set (match_operand:DF 0 "register_operand" "") | |
9626 | (neg:DF (match_operand:DF 1 "register_operand" ""))) | |
9627 | (clobber (reg:CC 17))] | |
9628 | "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed" | |
9629 | [(set (match_dup 0) | |
9630 | (neg:DF (match_dup 1)))] | |
9631 | "") | |
9632 | ||
9633 | (define_split | |
9634 | [(set (match_operand:DF 0 "register_operand" "") | |
9635 | (neg:DF (match_operand:DF 1 "register_operand" ""))) | |
9636 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
9637 | "!TARGET_64BIT && TARGET_80387 && reload_completed |
9638 | && !FP_REGNO_P (REGNO (operands[0]))" | |
1ce485ec JH |
9639 | [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4))) |
9640 | (clobber (reg:CC 17))])] | |
383252a7 | 9641 | "operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode)); |
1ce485ec JH |
9642 | split_di (operands+0, 1, operands+2, operands+3);") |
9643 | ||
06a964de JH |
9644 | (define_expand "negxf2" |
9645 | [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9646 | (neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) |
06a964de | 9647 | (clobber (reg:CC 17))])] |
1b0c37d7 | 9648 | "!TARGET_64BIT && TARGET_80387" |
06a964de JH |
9649 | "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;") |
9650 | ||
2b589241 JH |
9651 | (define_expand "negtf2" |
9652 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
9653 | (neg:TF (match_operand:TF 1 "nonimmediate_operand" ""))) | |
9654 | (clobber (reg:CC 17))])] | |
9655 | "TARGET_80387" | |
9656 | "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;") | |
9657 | ||
e20440c1 JH |
9658 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9659 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9660 | ;; to itself. | |
06a964de | 9661 | (define_insn "*negxf2_if" |
e20440c1 JH |
9662 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") |
9663 | (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 9664 | (clobber (reg:CC 17))] |
1b0c37d7 | 9665 | "!TARGET_64BIT && TARGET_80387 |
1e07edd3 | 9666 | && ix86_unary_operator_ok (NEG, XFmode, operands)" |
1ce485ec JH |
9667 | "#") |
9668 | ||
9669 | (define_split | |
9670 | [(set (match_operand:XF 0 "register_operand" "") | |
9671 | (neg:XF (match_operand:XF 1 "register_operand" ""))) | |
9672 | (clobber (reg:CC 17))] | |
9673 | "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed" | |
9674 | [(set (match_dup 0) | |
9675 | (neg:XF (match_dup 1)))] | |
9676 | "") | |
9677 | ||
9678 | (define_split | |
9679 | [(set (match_operand:XF 0 "register_operand" "") | |
9680 | (neg:XF (match_operand:XF 1 "register_operand" ""))) | |
9681 | (clobber (reg:CC 17))] | |
9682 | "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))" | |
9683 | [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) | |
9684 | (clobber (reg:CC 17))])] | |
9685 | "operands[1] = GEN_INT (0x8000); | |
141e454b JH |
9686 | operands[0] = gen_rtx_REG (SImode, |
9687 | true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") | |
1ce485ec | 9688 | |
2b589241 JH |
9689 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9690 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9691 | ;; to itself. | |
9692 | (define_insn "*negtf2_if" | |
9693 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f") | |
9694 | (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0"))) | |
9695 | (clobber (reg:CC 17))] | |
9696 | "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)" | |
9697 | "#") | |
9698 | ||
9699 | (define_split | |
9700 | [(set (match_operand:TF 0 "register_operand" "") | |
9701 | (neg:TF (match_operand:TF 1 "register_operand" ""))) | |
9702 | (clobber (reg:CC 17))] | |
9703 | "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed" | |
9704 | [(set (match_dup 0) | |
9705 | (neg:TF (match_dup 1)))] | |
9706 | "") | |
9707 | ||
9708 | (define_split | |
9709 | [(set (match_operand:TF 0 "register_operand" "") | |
9710 | (neg:TF (match_operand:TF 1 "register_operand" ""))) | |
9711 | (clobber (reg:CC 17))] | |
9712 | "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))" | |
9713 | [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) | |
9714 | (clobber (reg:CC 17))])] | |
9715 | "operands[1] = GEN_INT (0x8000); | |
141e454b JH |
9716 | operands[0] = gen_rtx_REG (SImode, |
9717 | true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") | |
2b589241 | 9718 | |
1ce485ec JH |
9719 | ;; Conditionize these after reload. If they matches before reload, we |
9720 | ;; lose the clobber and ability to use integer instructions. | |
9721 | ||
9722 | (define_insn "*negsf2_1" | |
886c62d1 | 9723 | [(set (match_operand:SF 0 "register_operand" "=f") |
2ae0f82c | 9724 | (neg:SF (match_operand:SF 1 "register_operand" "0")))] |
1ce485ec | 9725 | "TARGET_80387 && reload_completed" |
10195bd8 | 9726 | "fchs" |
e075ae69 | 9727 | [(set_attr "type" "fsgn") |
6ef67412 | 9728 | (set_attr "mode" "SF") |
e075ae69 | 9729 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 9730 | |
1ce485ec | 9731 | (define_insn "*negdf2_1" |
886c62d1 | 9732 | [(set (match_operand:DF 0 "register_operand" "=f") |
2ae0f82c | 9733 | (neg:DF (match_operand:DF 1 "register_operand" "0")))] |
1ce485ec | 9734 | "TARGET_80387 && reload_completed" |
10195bd8 | 9735 | "fchs" |
e075ae69 | 9736 | [(set_attr "type" "fsgn") |
6ef67412 | 9737 | (set_attr "mode" "DF") |
e075ae69 | 9738 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 9739 | |
6343a50e | 9740 | (define_insn "*negextendsfdf2" |
886c62d1 | 9741 | [(set (match_operand:DF 0 "register_operand" "=f") |
e075ae69 RH |
9742 | (neg:DF (float_extend:DF |
9743 | (match_operand:SF 1 "register_operand" "0"))))] | |
886c62d1 | 9744 | "TARGET_80387" |
10195bd8 | 9745 | "fchs" |
e075ae69 | 9746 | [(set_attr "type" "fsgn") |
6ef67412 | 9747 | (set_attr "mode" "DF") |
e075ae69 | 9748 | (set_attr "ppro_uops" "few")]) |
4fb21e90 | 9749 | |
1ce485ec | 9750 | (define_insn "*negxf2_1" |
4fb21e90 | 9751 | [(set (match_operand:XF 0 "register_operand" "=f") |
2ae0f82c | 9752 | (neg:XF (match_operand:XF 1 "register_operand" "0")))] |
1b0c37d7 | 9753 | "!TARGET_64BIT && TARGET_80387 && reload_completed" |
10195bd8 | 9754 | "fchs" |
e075ae69 | 9755 | [(set_attr "type" "fsgn") |
6ef67412 | 9756 | (set_attr "mode" "XF") |
e075ae69 RH |
9757 | (set_attr "ppro_uops" "few")]) |
9758 | ||
6343a50e | 9759 | (define_insn "*negextenddfxf2" |
e075ae69 RH |
9760 | [(set (match_operand:XF 0 "register_operand" "=f") |
9761 | (neg:XF (float_extend:XF | |
9762 | (match_operand:DF 1 "register_operand" "0"))))] | |
1b0c37d7 | 9763 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
9764 | "fchs" |
9765 | [(set_attr "type" "fsgn") | |
6ef67412 | 9766 | (set_attr "mode" "XF") |
e075ae69 | 9767 | (set_attr "ppro_uops" "few")]) |
4fb21e90 | 9768 | |
6343a50e | 9769 | (define_insn "*negextendsfxf2" |
4fb21e90 | 9770 | [(set (match_operand:XF 0 "register_operand" "=f") |
e075ae69 RH |
9771 | (neg:XF (float_extend:XF |
9772 | (match_operand:SF 1 "register_operand" "0"))))] | |
1b0c37d7 | 9773 | "!TARGET_64BIT && TARGET_80387" |
10195bd8 | 9774 | "fchs" |
e075ae69 | 9775 | [(set_attr "type" "fsgn") |
6ef67412 | 9776 | (set_attr "mode" "XF") |
e075ae69 | 9777 | (set_attr "ppro_uops" "few")]) |
2b589241 JH |
9778 | |
9779 | (define_insn "*negtf2_1" | |
9780 | [(set (match_operand:TF 0 "register_operand" "=f") | |
9781 | (neg:TF (match_operand:TF 1 "register_operand" "0")))] | |
9782 | "TARGET_80387 && reload_completed" | |
9783 | "fchs" | |
9784 | [(set_attr "type" "fsgn") | |
9785 | (set_attr "mode" "XF") | |
9786 | (set_attr "ppro_uops" "few")]) | |
9787 | ||
9788 | (define_insn "*negextenddftf2" | |
9789 | [(set (match_operand:TF 0 "register_operand" "=f") | |
9790 | (neg:TF (float_extend:TF | |
9791 | (match_operand:DF 1 "register_operand" "0"))))] | |
9792 | "TARGET_80387" | |
9793 | "fchs" | |
9794 | [(set_attr "type" "fsgn") | |
9795 | (set_attr "mode" "XF") | |
9796 | (set_attr "ppro_uops" "few")]) | |
9797 | ||
9798 | (define_insn "*negextendsftf2" | |
9799 | [(set (match_operand:TF 0 "register_operand" "=f") | |
9800 | (neg:TF (float_extend:TF | |
9801 | (match_operand:SF 1 "register_operand" "0"))))] | |
9802 | "TARGET_80387" | |
9803 | "fchs" | |
9804 | [(set_attr "type" "fsgn") | |
9805 | (set_attr "mode" "XF") | |
9806 | (set_attr "ppro_uops" "few")]) | |
886c62d1 JVA |
9807 | \f |
9808 | ;; Absolute value instructions | |
9809 | ||
06a964de JH |
9810 | (define_expand "abssf2" |
9811 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9812 | (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) |
06a964de JH |
9813 | (clobber (reg:CC 17))])] |
9814 | "TARGET_80387" | |
ca29d1dc JH |
9815 | "if (TARGET_SSE) |
9816 | { | |
9817 | /* In case operand is in memory, we will not use SSE. */ | |
9818 | if (memory_operand (operands[0], VOIDmode) | |
9819 | && rtx_equal_p (operands[0], operands[1])) | |
9820 | emit_insn (gen_abssf2_memory (operands[0], operands[1])); | |
9821 | else | |
9822 | { | |
9823 | /* Using SSE is tricky, since we need bitwise negation of -0 | |
9824 | in register. */ | |
9825 | rtx reg = gen_reg_rtx (SFmode); | |
141e454b JH |
9826 | rtx dest = operands[0]; |
9827 | ||
9828 | operands[1] = force_reg (SFmode, operands[1]); | |
9829 | operands[0] = force_reg (SFmode, operands[0]); | |
9830 | emit_move_insn (reg, | |
9831 | gen_lowpart (SFmode, | |
9832 | GEN_INT (trunc_int_for_mode (0x80000000, | |
9833 | SImode)))); | |
ca29d1dc | 9834 | emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg)); |
141e454b JH |
9835 | if (dest != operands[0]) |
9836 | emit_move_insn (dest, operands[0]); | |
ca29d1dc JH |
9837 | } |
9838 | DONE; | |
9839 | } | |
9840 | ix86_expand_unary_operator (ABS, SFmode, operands); DONE;") | |
9841 | ||
9842 | (define_insn "abssf2_memory" | |
9843 | [(set (match_operand:SF 0 "memory_operand" "=m") | |
9844 | (abs:SF (match_operand:SF 1 "memory_operand" "0"))) | |
9845 | (clobber (reg:CC 17))] | |
9846 | "ix86_unary_operator_ok (ABS, SFmode, operands)" | |
9847 | "#") | |
9848 | ||
9849 | (define_insn "abssf2_ifs" | |
141e454b | 9850 | [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf") |
ca29d1dc | 9851 | (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0"))) |
141e454b | 9852 | (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x")) |
ca29d1dc | 9853 | (clobber (reg:CC 17))] |
141e454b JH |
9854 | "TARGET_SSE |
9855 | && (reload_in_progress || reload_completed | |
9856 | || (register_operand (operands[0], VOIDmode) | |
9857 | && register_operand (operands[1], VOIDmode)))" | |
ca29d1dc JH |
9858 | "#") |
9859 | ||
9860 | (define_split | |
9861 | [(set (match_operand:SF 0 "memory_operand" "") | |
9862 | (abs:SF (match_operand:SF 1 "memory_operand" ""))) | |
9863 | (use (match_operand:SF 2 "" "")) | |
9864 | (clobber (reg:CC 17))] | |
9865 | "" | |
9866 | [(parallel [(set (match_dup 0) | |
9867 | (abs:SF (match_dup 1))) | |
9868 | (clobber (reg:CC 17))])]) | |
9869 | ||
9870 | (define_split | |
9871 | [(set (match_operand:SF 0 "register_operand" "") | |
9872 | (abs:SF (match_operand:SF 1 "register_operand" ""))) | |
9873 | (use (match_operand:SF 2 "" "")) | |
9874 | (clobber (reg:CC 17))] | |
9875 | "reload_completed && !SSE_REG_P (operands[0])" | |
9876 | [(parallel [(set (match_dup 0) | |
9877 | (abs:SF (match_dup 1))) | |
9878 | (clobber (reg:CC 17))])]) | |
9879 | ||
9880 | (define_split | |
9881 | [(set (match_operand:SF 0 "register_operand" "") | |
9882 | (abs:SF (match_operand:SF 1 "register_operand" ""))) | |
9883 | (use (match_operand:SF 2 "register_operand" "")) | |
9884 | (clobber (reg:CC 17))] | |
9885 | "reload_completed && SSE_REG_P (operands[0])" | |
9886 | [(set (subreg:TI (match_dup 0) 0) | |
9887 | (and:TI (not:TI (subreg:TI (match_dup 2) 0)) | |
9888 | (subreg:TI (match_dup 1) 0)))]) | |
06a964de | 9889 | |
e20440c1 JH |
9890 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9891 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9892 | ;; to itself. | |
06a964de | 9893 | (define_insn "*abssf2_if" |
e20440c1 JH |
9894 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") |
9895 | (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 9896 | (clobber (reg:CC 17))] |
ca29d1dc | 9897 | "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE" |
1ce485ec JH |
9898 | "#") |
9899 | ||
9900 | (define_split | |
9901 | [(set (match_operand:SF 0 "register_operand" "") | |
9902 | (abs:SF (match_operand:SF 1 "register_operand" ""))) | |
9903 | (clobber (reg:CC 17))] | |
9904 | "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))" | |
9905 | [(set (match_dup 0) | |
9906 | (abs:SF (match_dup 1)))] | |
9907 | "") | |
9908 | ||
9909 | (define_split | |
9910 | [(set (match_operand:SF 0 "register_operand" "") | |
9911 | (abs:SF (match_operand:SF 1 "register_operand" ""))) | |
9912 | (clobber (reg:CC 17))] | |
9913 | "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))" | |
9914 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) | |
9915 | (clobber (reg:CC 17))])] | |
383252a7 | 9916 | "operands[1] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode)); |
1ce485ec JH |
9917 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") |
9918 | ||
9919 | (define_split | |
9920 | [(set (match_operand 0 "memory_operand" "") | |
9921 | (abs (match_operand 1 "memory_operand" ""))) | |
9922 | (clobber (reg:CC 17))] | |
9923 | "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" | |
9924 | [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
9925 | (clobber (reg:CC 17))])] | |
1ce485ec JH |
9926 | { |
9927 | int size = GET_MODE_SIZE (GET_MODE (operands[1])); | |
9928 | ||
b3298882 JH |
9929 | /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */ |
9930 | if (size >= 12) | |
1ce485ec | 9931 | size = 10; |
b72f00af | 9932 | operands[0] = adjust_address (operands[0], QImode, size - 1); |
383252a7 | 9933 | operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode)); |
0f40f9f7 | 9934 | }) |
1ce485ec | 9935 | |
06a964de JH |
9936 | (define_expand "absdf2" |
9937 | [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9938 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) |
06a964de | 9939 | (clobber (reg:CC 17))])] |
1ce485ec | 9940 | "TARGET_80387" |
ca29d1dc JH |
9941 | "if (TARGET_SSE2) |
9942 | { | |
9943 | /* In case operand is in memory, we will not use SSE. */ | |
9944 | if (memory_operand (operands[0], VOIDmode) | |
9945 | && rtx_equal_p (operands[0], operands[1])) | |
9946 | emit_insn (gen_absdf2_memory (operands[0], operands[1])); | |
9947 | else | |
9948 | { | |
9949 | /* Using SSE is tricky, since we need bitwise negation of -0 | |
9950 | in register. */ | |
9951 | rtx reg = gen_reg_rtx (DFmode); | |
9952 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
141e454b JH |
9953 | rtx imm = GEN_INT (trunc_int_for_mode(((HOST_WIDE_INT)1) << 63, |
9954 | DImode)); | |
ca29d1dc JH |
9955 | #else |
9956 | rtx imm = immed_double_const (0, 0x80000000, DImode); | |
9957 | #endif | |
141e454b JH |
9958 | rtx dest = operands[0]; |
9959 | ||
9960 | operands[1] = force_reg (DFmode, operands[1]); | |
9961 | operands[0] = force_reg (DFmode, operands[0]); | |
ca29d1dc JH |
9962 | emit_move_insn (reg, gen_lowpart (DFmode, imm)); |
9963 | emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg)); | |
141e454b JH |
9964 | if (dest != operands[0]) |
9965 | emit_move_insn (dest, operands[0]); | |
ca29d1dc JH |
9966 | } |
9967 | DONE; | |
9968 | } | |
9969 | ix86_expand_unary_operator (ABS, DFmode, operands); DONE;") | |
9970 | ||
9971 | (define_insn "absdf2_memory" | |
9972 | [(set (match_operand:DF 0 "memory_operand" "=m") | |
9973 | (abs:DF (match_operand:DF 1 "memory_operand" "0"))) | |
9974 | (clobber (reg:CC 17))] | |
9975 | "ix86_unary_operator_ok (ABS, DFmode, operands)" | |
9976 | "#") | |
9977 | ||
9978 | (define_insn "absdf2_ifs" | |
141e454b | 9979 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf") |
ca29d1dc | 9980 | (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0"))) |
141e454b | 9981 | (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y")) |
ca29d1dc | 9982 | (clobber (reg:CC 17))] |
1b0c37d7 | 9983 | "!TARGET_64BIT && TARGET_SSE2 |
141e454b JH |
9984 | && (reload_in_progress || reload_completed |
9985 | || (register_operand (operands[0], VOIDmode) | |
9986 | && register_operand (operands[1], VOIDmode)))" | |
9987 | "#") | |
9988 | ||
9989 | (define_insn "*absdf2_ifs_rex64" | |
9990 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr") | |
9991 | (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0"))) | |
9992 | (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y")) | |
9993 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9994 | "TARGET_64BIT && TARGET_SSE2 |
141e454b JH |
9995 | && (reload_in_progress || reload_completed |
9996 | || (register_operand (operands[0], VOIDmode) | |
9997 | && register_operand (operands[1], VOIDmode)))" | |
ca29d1dc JH |
9998 | "#") |
9999 | ||
10000 | (define_split | |
10001 | [(set (match_operand:DF 0 "memory_operand" "") | |
10002 | (abs:DF (match_operand:DF 1 "memory_operand" ""))) | |
10003 | (use (match_operand:DF 2 "" "")) | |
10004 | (clobber (reg:CC 17))] | |
10005 | "" | |
10006 | [(parallel [(set (match_dup 0) | |
10007 | (abs:DF (match_dup 1))) | |
10008 | (clobber (reg:CC 17))])]) | |
10009 | ||
10010 | (define_split | |
10011 | [(set (match_operand:DF 0 "register_operand" "") | |
10012 | (abs:DF (match_operand:DF 1 "register_operand" ""))) | |
10013 | (use (match_operand:DF 2 "" "")) | |
10014 | (clobber (reg:CC 17))] | |
10015 | "reload_completed && !SSE_REG_P (operands[0])" | |
10016 | [(parallel [(set (match_dup 0) | |
10017 | (abs:DF (match_dup 1))) | |
10018 | (clobber (reg:CC 17))])]) | |
10019 | ||
10020 | (define_split | |
10021 | [(set (match_operand:DF 0 "register_operand" "") | |
10022 | (abs:DF (match_operand:DF 1 "register_operand" ""))) | |
10023 | (use (match_operand:DF 2 "register_operand" "")) | |
10024 | (clobber (reg:CC 17))] | |
10025 | "reload_completed && SSE_REG_P (operands[0])" | |
10026 | [(set (subreg:TI (match_dup 0) 0) | |
10027 | (and:TI (not:TI (subreg:TI (match_dup 2) 0)) | |
10028 | (subreg:TI (match_dup 1) 0)))]) | |
10029 | ||
06a964de | 10030 | |
e20440c1 JH |
10031 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
10032 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
10033 | ;; to itself. | |
06a964de | 10034 | (define_insn "*absdf2_if" |
e20440c1 JH |
10035 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f") |
10036 | (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) | |
06a964de | 10037 | (clobber (reg:CC 17))] |
1b0c37d7 | 10038 | "!TARGET_64BIT && TARGET_80387 |
141e454b JH |
10039 | && ix86_unary_operator_ok (ABS, DFmode, operands)" |
10040 | "#") | |
10041 | ||
10042 | ;; FIXME: We should to allow integer registers here. Problem is that | |
10043 | ;; we need another scratch register to get constant from. | |
10044 | ;; Forcing constant to mem if no register available in peep2 should be | |
10045 | ;; safe even for PIC mode, because of RIP relative addressing. | |
10046 | (define_insn "*absdf2_if_rex64" | |
10047 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf") | |
10048 | (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) | |
10049 | (clobber (reg:CC 17))] | |
1b0c37d7 | 10050 | "TARGET_64BIT && TARGET_80387 |
141e454b | 10051 | && ix86_unary_operator_ok (ABS, DFmode, operands)" |
1ce485ec JH |
10052 | "#") |
10053 | ||
10054 | (define_split | |
10055 | [(set (match_operand:DF 0 "register_operand" "") | |
10056 | (abs:DF (match_operand:DF 1 "register_operand" ""))) | |
10057 | (clobber (reg:CC 17))] | |
10058 | "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed" | |
10059 | [(set (match_dup 0) | |
10060 | (abs:DF (match_dup 1)))] | |
10061 | "") | |
10062 | ||
10063 | (define_split | |
10064 | [(set (match_operand:DF 0 "register_operand" "") | |
10065 | (abs:DF (match_operand:DF 1 "register_operand" ""))) | |
10066 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
10067 | "!TARGET_64BIT && TARGET_80387 && reload_completed && |
10068 | !FP_REGNO_P (REGNO (operands[0]))" | |
1ce485ec JH |
10069 | [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4))) |
10070 | (clobber (reg:CC 17))])] | |
383252a7 | 10071 | "operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode)); |
1ce485ec JH |
10072 | split_di (operands+0, 1, operands+2, operands+3);") |
10073 | ||
06a964de JH |
10074 | (define_expand "absxf2" |
10075 | [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
2756c3d8 | 10076 | (neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) |
06a964de | 10077 | (clobber (reg:CC 17))])] |
1b0c37d7 | 10078 | "!TARGET_64BIT && TARGET_80387" |
06a964de JH |
10079 | "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;") |
10080 | ||
2b589241 JH |
10081 | (define_expand "abstf2" |
10082 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
10083 | (neg:TF (match_operand:TF 1 "nonimmediate_operand" ""))) | |
10084 | (clobber (reg:CC 17))])] | |
10085 | "TARGET_80387" | |
10086 | "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;") | |
10087 | ||
e20440c1 JH |
10088 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
10089 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
10090 | ;; to itself. | |
06a964de | 10091 | (define_insn "*absxf2_if" |
e20440c1 JH |
10092 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") |
10093 | (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 10094 | (clobber (reg:CC 17))] |
1b0c37d7 | 10095 | "!TARGET_64BIT && TARGET_80387 |
1e07edd3 | 10096 | && ix86_unary_operator_ok (ABS, XFmode, operands)" |
1ce485ec JH |
10097 | "#") |
10098 | ||
10099 | (define_split | |
10100 | [(set (match_operand:XF 0 "register_operand" "") | |
10101 | (abs:XF (match_operand:XF 1 "register_operand" ""))) | |
10102 | (clobber (reg:CC 17))] | |
10103 | "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed" | |
10104 | [(set (match_dup 0) | |
10105 | (abs:XF (match_dup 1)))] | |
10106 | "") | |
10107 | ||
10108 | (define_split | |
10109 | [(set (match_operand:XF 0 "register_operand" "") | |
10110 | (abs:XF (match_operand:XF 1 "register_operand" ""))) | |
10111 | (clobber (reg:CC 17))] | |
10112 | "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))" | |
10113 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) | |
10114 | (clobber (reg:CC 17))])] | |
141e454b JH |
10115 | "operands[1] = GEN_INT (~0x8000); |
10116 | operands[0] = gen_rtx_REG (SImode, | |
10117 | true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") | |
1ce485ec | 10118 | |
2b589241 JH |
10119 | (define_insn "*abstf2_if" |
10120 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f") | |
10121 | (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0"))) | |
10122 | (clobber (reg:CC 17))] | |
10123 | "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)" | |
10124 | "#") | |
10125 | ||
10126 | (define_split | |
10127 | [(set (match_operand:TF 0 "register_operand" "") | |
10128 | (abs:TF (match_operand:TF 1 "register_operand" ""))) | |
10129 | (clobber (reg:CC 17))] | |
10130 | "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed" | |
10131 | [(set (match_dup 0) | |
10132 | (abs:TF (match_dup 1)))] | |
10133 | "") | |
10134 | ||
10135 | (define_split | |
10136 | [(set (match_operand:TF 0 "register_operand" "") | |
10137 | (abs:TF (match_operand:TF 1 "register_operand" ""))) | |
10138 | (clobber (reg:CC 17))] | |
10139 | "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))" | |
10140 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) | |
10141 | (clobber (reg:CC 17))])] | |
141e454b JH |
10142 | "operands[1] = GEN_INT (~0x8000); |
10143 | operands[0] = gen_rtx_REG (SImode, | |
10144 | true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") | |
2b589241 | 10145 | |
1ce485ec | 10146 | (define_insn "*abssf2_1" |
886c62d1 | 10147 | [(set (match_operand:SF 0 "register_operand" "=f") |
2ae0f82c | 10148 | (abs:SF (match_operand:SF 1 "register_operand" "0")))] |
1ce485ec | 10149 | "TARGET_80387 && reload_completed" |
2ae0f82c | 10150 | "fabs" |
6ef67412 JH |
10151 | [(set_attr "type" "fsgn") |
10152 | (set_attr "mode" "SF")]) | |
886c62d1 | 10153 | |
1ce485ec | 10154 | (define_insn "*absdf2_1" |
886c62d1 | 10155 | [(set (match_operand:DF 0 "register_operand" "=f") |
2ae0f82c | 10156 | (abs:DF (match_operand:DF 1 "register_operand" "0")))] |
1ce485ec | 10157 | "TARGET_80387 && reload_completed" |
2ae0f82c | 10158 | "fabs" |
6ef67412 JH |
10159 | [(set_attr "type" "fsgn") |
10160 | (set_attr "mode" "DF")]) | |
886c62d1 | 10161 | |
6343a50e | 10162 | (define_insn "*absextendsfdf2" |
886c62d1 | 10163 | [(set (match_operand:DF 0 "register_operand" "=f") |
e075ae69 RH |
10164 | (abs:DF (float_extend:DF |
10165 | (match_operand:SF 1 "register_operand" "0"))))] | |
886c62d1 | 10166 | "TARGET_80387" |
2ae0f82c | 10167 | "fabs" |
6ef67412 JH |
10168 | [(set_attr "type" "fsgn") |
10169 | (set_attr "mode" "DF")]) | |
886c62d1 | 10170 | |
1ce485ec | 10171 | (define_insn "*absxf2_1" |
4fb21e90 | 10172 | [(set (match_operand:XF 0 "register_operand" "=f") |
2ae0f82c | 10173 | (abs:XF (match_operand:XF 1 "register_operand" "0")))] |
1b0c37d7 | 10174 | "!TARGET_64BIT && TARGET_80387 && reload_completed" |
2ae0f82c | 10175 | "fabs" |
6ef67412 JH |
10176 | [(set_attr "type" "fsgn") |
10177 | (set_attr "mode" "DF")]) | |
4fb21e90 | 10178 | |
6343a50e | 10179 | (define_insn "*absextenddfxf2" |
4fb21e90 | 10180 | [(set (match_operand:XF 0 "register_operand" "=f") |
e075ae69 RH |
10181 | (abs:XF (float_extend:XF |
10182 | (match_operand:DF 1 "register_operand" "0"))))] | |
1b0c37d7 | 10183 | "!TARGET_64BIT && TARGET_80387" |
2ae0f82c | 10184 | "fabs" |
6ef67412 JH |
10185 | [(set_attr "type" "fsgn") |
10186 | (set_attr "mode" "XF")]) | |
a199fdd6 | 10187 | |
6343a50e | 10188 | (define_insn "*absextendsfxf2" |
58733f96 | 10189 | [(set (match_operand:XF 0 "register_operand" "=f") |
e075ae69 RH |
10190 | (abs:XF (float_extend:XF |
10191 | (match_operand:SF 1 "register_operand" "0"))))] | |
1b0c37d7 | 10192 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 10193 | "fabs" |
6ef67412 JH |
10194 | [(set_attr "type" "fsgn") |
10195 | (set_attr "mode" "XF")]) | |
2b589241 JH |
10196 | |
10197 | (define_insn "*abstf2_1" | |
10198 | [(set (match_operand:TF 0 "register_operand" "=f") | |
10199 | (abs:TF (match_operand:TF 1 "register_operand" "0")))] | |
10200 | "TARGET_80387 && reload_completed" | |
10201 | "fabs" | |
10202 | [(set_attr "type" "fsgn") | |
10203 | (set_attr "mode" "DF")]) | |
10204 | ||
10205 | (define_insn "*absextenddftf2" | |
10206 | [(set (match_operand:TF 0 "register_operand" "=f") | |
10207 | (abs:TF (float_extend:TF | |
10208 | (match_operand:DF 1 "register_operand" "0"))))] | |
10209 | "TARGET_80387" | |
10210 | "fabs" | |
10211 | [(set_attr "type" "fsgn") | |
10212 | (set_attr "mode" "XF")]) | |
10213 | ||
10214 | (define_insn "*absextendsftf2" | |
10215 | [(set (match_operand:TF 0 "register_operand" "=f") | |
10216 | (abs:TF (float_extend:TF | |
10217 | (match_operand:SF 1 "register_operand" "0"))))] | |
10218 | "TARGET_80387" | |
10219 | "fabs" | |
10220 | [(set_attr "type" "fsgn") | |
10221 | (set_attr "mode" "XF")]) | |
886c62d1 | 10222 | \f |
e075ae69 | 10223 | ;; One complement instructions |
886c62d1 | 10224 | |
9b70259d JH |
10225 | (define_expand "one_cmpldi2" |
10226 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
10227 | (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))] | |
10228 | "TARGET_64BIT" | |
10229 | "ix86_expand_unary_operator (NOT, DImode, operands); DONE;") | |
10230 | ||
10231 | (define_insn "*one_cmpldi2_1_rex64" | |
10232 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
10233 | (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))] | |
10234 | "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)" | |
0f40f9f7 | 10235 | "not{q}\t%0" |
9b70259d JH |
10236 | [(set_attr "type" "negnot") |
10237 | (set_attr "mode" "DI")]) | |
10238 | ||
10239 | (define_insn "*one_cmpldi2_2_rex64" | |
10240 | [(set (reg 17) | |
10241 | (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")) | |
10242 | (const_int 0))) | |
10243 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
10244 | (not:DI (match_dup 1)))] | |
10245 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
10246 | && ix86_unary_operator_ok (NOT, DImode, operands)" | |
10247 | "#" | |
10248 | [(set_attr "type" "alu1") | |
10249 | (set_attr "mode" "DI")]) | |
10250 | ||
10251 | (define_split | |
10252 | [(set (reg 17) | |
10253 | (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "")) | |
10254 | (const_int 0))) | |
10255 | (set (match_operand:DI 0 "nonimmediate_operand" "") | |
10256 | (not:DI (match_dup 1)))] | |
10257 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
10258 | [(parallel [(set (reg:CCNO 17) | |
10259 | (compare:CCNO (xor:DI (match_dup 1) (const_int -1)) | |
10260 | (const_int 0))) | |
10261 | (set (match_dup 0) | |
10262 | (xor:DI (match_dup 1) (const_int -1)))])] | |
10263 | "") | |
10264 | ||
06a964de | 10265 | (define_expand "one_cmplsi2" |
a1cbdd7f JH |
10266 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
10267 | (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
06a964de JH |
10268 | "" |
10269 | "ix86_expand_unary_operator (NOT, SImode, operands); DONE;") | |
10270 | ||
10271 | (define_insn "*one_cmplsi2_1" | |
2ae0f82c SC |
10272 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
10273 | (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))] | |
a1cbdd7f | 10274 | "ix86_unary_operator_ok (NOT, SImode, operands)" |
0f40f9f7 | 10275 | "not{l}\t%0" |
6ef67412 JH |
10276 | [(set_attr "type" "negnot") |
10277 | (set_attr "mode" "SI")]) | |
bb524860 | 10278 | |
9b70259d JH |
10279 | ;; ??? Currently never generated - xor is used instead. |
10280 | (define_insn "*one_cmplsi2_1_zext" | |
10281 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10282 | (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))] | |
10283 | "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)" | |
0f40f9f7 | 10284 | "not{l}\t%k0" |
9b70259d JH |
10285 | [(set_attr "type" "negnot") |
10286 | (set_attr "mode" "SI")]) | |
10287 | ||
06a964de | 10288 | (define_insn "*one_cmplsi2_2" |
16189740 RH |
10289 | [(set (reg 17) |
10290 | (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")) | |
10291 | (const_int 0))) | |
e075ae69 RH |
10292 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
10293 | (not:SI (match_dup 1)))] | |
16189740 RH |
10294 | "ix86_match_ccmode (insn, CCNOmode) |
10295 | && ix86_unary_operator_ok (NOT, SImode, operands)" | |
e075ae69 | 10296 | "#" |
6ef67412 JH |
10297 | [(set_attr "type" "alu1") |
10298 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
10299 | |
10300 | (define_split | |
16189740 RH |
10301 | [(set (reg 17) |
10302 | (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "")) | |
10303 | (const_int 0))) | |
e075ae69 RH |
10304 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
10305 | (not:SI (match_dup 1)))] | |
16189740 | 10306 | "ix86_match_ccmode (insn, CCNOmode)" |
e075ae69 RH |
10307 | [(parallel [(set (reg:CCNO 17) |
10308 | (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) | |
10309 | (const_int 0))) | |
10310 | (set (match_dup 0) | |
10311 | (xor:SI (match_dup 1) (const_int -1)))])] | |
10312 | "") | |
886c62d1 | 10313 | |
9b70259d JH |
10314 | ;; ??? Currently never generated - xor is used instead. |
10315 | (define_insn "*one_cmplsi2_2_zext" | |
10316 | [(set (reg 17) | |
10317 | (compare (not:SI (match_operand:SI 1 "register_operand" "0")) | |
10318 | (const_int 0))) | |
10319 | (set (match_operand:DI 0 "register_operand" "=r") | |
10320 | (zero_extend:DI (not:SI (match_dup 1))))] | |
10321 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
10322 | && ix86_unary_operator_ok (NOT, SImode, operands)" | |
10323 | "#" | |
10324 | [(set_attr "type" "alu1") | |
10325 | (set_attr "mode" "SI")]) | |
10326 | ||
10327 | (define_split | |
10328 | [(set (reg 17) | |
10329 | (compare (not:SI (match_operand:SI 1 "register_operand" "")) | |
10330 | (const_int 0))) | |
10331 | (set (match_operand:DI 0 "register_operand" "") | |
10332 | (zero_extend:DI (not:SI (match_dup 1))))] | |
10333 | "ix86_match_ccmode (insn, CCNOmode)" | |
10334 | [(parallel [(set (reg:CCNO 17) | |
10335 | (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) | |
10336 | (const_int 0))) | |
10337 | (set (match_dup 0) | |
10338 | (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])] | |
10339 | "") | |
10340 | ||
06a964de | 10341 | (define_expand "one_cmplhi2" |
a1cbdd7f JH |
10342 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
10343 | (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
d9f32422 | 10344 | "TARGET_HIMODE_MATH" |
06a964de JH |
10345 | "ix86_expand_unary_operator (NOT, HImode, operands); DONE;") |
10346 | ||
10347 | (define_insn "*one_cmplhi2_1" | |
2ae0f82c SC |
10348 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
10349 | (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))] | |
a1cbdd7f | 10350 | "ix86_unary_operator_ok (NOT, HImode, operands)" |
0f40f9f7 | 10351 | "not{w}\t%0" |
6ef67412 JH |
10352 | [(set_attr "type" "negnot") |
10353 | (set_attr "mode" "HI")]) | |
bb524860 | 10354 | |
06a964de | 10355 | (define_insn "*one_cmplhi2_2" |
16189740 RH |
10356 | [(set (reg 17) |
10357 | (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")) | |
10358 | (const_int 0))) | |
e075ae69 RH |
10359 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
10360 | (not:HI (match_dup 1)))] | |
16189740 RH |
10361 | "ix86_match_ccmode (insn, CCNOmode) |
10362 | && ix86_unary_operator_ok (NEG, HImode, operands)" | |
e075ae69 | 10363 | "#" |
6ef67412 JH |
10364 | [(set_attr "type" "alu1") |
10365 | (set_attr "mode" "HI")]) | |
e075ae69 RH |
10366 | |
10367 | (define_split | |
16189740 RH |
10368 | [(set (reg 17) |
10369 | (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "")) | |
10370 | (const_int 0))) | |
e075ae69 RH |
10371 | (set (match_operand:HI 0 "nonimmediate_operand" "") |
10372 | (not:HI (match_dup 1)))] | |
16189740 | 10373 | "ix86_match_ccmode (insn, CCNOmode)" |
e075ae69 RH |
10374 | [(parallel [(set (reg:CCNO 17) |
10375 | (compare:CCNO (xor:HI (match_dup 1) (const_int -1)) | |
10376 | (const_int 0))) | |
10377 | (set (match_dup 0) | |
10378 | (xor:HI (match_dup 1) (const_int -1)))])] | |
10379 | "") | |
886c62d1 | 10380 | |
e075ae69 | 10381 | ;; %%% Potential partial reg stall on alternative 1. What to do? |
06a964de | 10382 | (define_expand "one_cmplqi2" |
a1cbdd7f JH |
10383 | [(set (match_operand:QI 0 "nonimmediate_operand" "") |
10384 | (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
d9f32422 | 10385 | "TARGET_QIMODE_MATH" |
06a964de JH |
10386 | "ix86_expand_unary_operator (NOT, QImode, operands); DONE;") |
10387 | ||
10388 | (define_insn "*one_cmplqi2_1" | |
7c6b971d | 10389 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r") |
e075ae69 | 10390 | (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))] |
a1cbdd7f | 10391 | "ix86_unary_operator_ok (NOT, QImode, operands)" |
e075ae69 | 10392 | "@ |
0f40f9f7 ZW |
10393 | not{b}\t%0 |
10394 | not{l}\t%k0" | |
6ef67412 JH |
10395 | [(set_attr "type" "negnot") |
10396 | (set_attr "mode" "QI,SI")]) | |
bb524860 | 10397 | |
06a964de | 10398 | (define_insn "*one_cmplqi2_2" |
16189740 RH |
10399 | [(set (reg 17) |
10400 | (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")) | |
10401 | (const_int 0))) | |
e075ae69 RH |
10402 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
10403 | (not:QI (match_dup 1)))] | |
16189740 RH |
10404 | "ix86_match_ccmode (insn, CCNOmode) |
10405 | && ix86_unary_operator_ok (NOT, QImode, operands)" | |
e075ae69 | 10406 | "#" |
6ef67412 JH |
10407 | [(set_attr "type" "alu1") |
10408 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
10409 | |
10410 | (define_split | |
16189740 RH |
10411 | [(set (reg 17) |
10412 | (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "")) | |
10413 | (const_int 0))) | |
e075ae69 RH |
10414 | (set (match_operand:QI 0 "nonimmediate_operand" "") |
10415 | (not:QI (match_dup 1)))] | |
16189740 | 10416 | "ix86_match_ccmode (insn, CCNOmode)" |
e075ae69 RH |
10417 | [(parallel [(set (reg:CCNO 17) |
10418 | (compare:CCNO (xor:QI (match_dup 1) (const_int -1)) | |
10419 | (const_int 0))) | |
10420 | (set (match_dup 0) | |
10421 | (xor:QI (match_dup 1) (const_int -1)))])] | |
10422 | "") | |
886c62d1 | 10423 | \f |
e075ae69 | 10424 | ;; Arithmetic shift instructions |
886c62d1 JVA |
10425 | |
10426 | ;; DImode shifts are implemented using the i386 "shift double" opcode, | |
10427 | ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count | |
10428 | ;; is variable, then the count is in %cl and the "imm" operand is dropped | |
10429 | ;; from the assembler input. | |
e075ae69 | 10430 | ;; |
886c62d1 JVA |
10431 | ;; This instruction shifts the target reg/mem as usual, but instead of |
10432 | ;; shifting in zeros, bits are shifted in from reg operand. If the insn | |
10433 | ;; is a left shift double, bits are taken from the high order bits of | |
10434 | ;; reg, else if the insn is a shift right double, bits are taken from the | |
10435 | ;; low order bits of reg. So if %eax is "1234" and %edx is "5678", | |
10436 | ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345". | |
e075ae69 | 10437 | ;; |
886c62d1 JVA |
10438 | ;; Since sh[lr]d does not change the `reg' operand, that is done |
10439 | ;; separately, making all shifts emit pairs of shift double and normal | |
10440 | ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to | |
10441 | ;; support a 63 bit shift, each shift where the count is in a reg expands | |
f58acb67 | 10442 | ;; to a pair of shifts, a branch, a shift by 32 and a label. |
e075ae69 | 10443 | ;; |
886c62d1 JVA |
10444 | ;; If the shift count is a constant, we need never emit more than one |
10445 | ;; shift pair, instead using moves and sign extension for counts greater | |
10446 | ;; than 31. | |
10447 | ||
56c0e8fa | 10448 | (define_expand "ashldi3" |
371bc54b JH |
10449 | [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") |
10450 | (ashift:DI (match_operand:DI 1 "shiftdi_operand" "") | |
3d117b30 | 10451 | (match_operand:QI 2 "nonmemory_operand" ""))) |
e075ae69 | 10452 | (clobber (reg:CC 17))])] |
56c0e8fa | 10453 | "" |
56c0e8fa | 10454 | { |
3d117b30 | 10455 | if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) |
56c0e8fa | 10456 | { |
e075ae69 RH |
10457 | emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2])); |
10458 | DONE; | |
56c0e8fa | 10459 | } |
371bc54b JH |
10460 | ix86_expand_binary_operator (ASHIFT, DImode, operands); |
10461 | DONE; | |
0f40f9f7 | 10462 | }) |
56c0e8fa | 10463 | |
371bc54b JH |
10464 | (define_insn "*ashldi3_1_rex64" |
10465 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
10466 | (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r") | |
7c17f553 | 10467 | (match_operand:QI 2 "nonmemory_operand" "cJ,M"))) |
371bc54b JH |
10468 | (clobber (reg:CC 17))] |
10469 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)" | |
371bc54b JH |
10470 | { |
10471 | switch (get_attr_type (insn)) | |
10472 | { | |
10473 | case TYPE_ALU: | |
10474 | if (operands[2] != const1_rtx) | |
10475 | abort (); | |
10476 | if (!rtx_equal_p (operands[0], operands[1])) | |
10477 | abort (); | |
0f40f9f7 | 10478 | return "add{q}\t{%0, %0|%0, %0}"; |
371bc54b JH |
10479 | |
10480 | case TYPE_LEA: | |
10481 | if (GET_CODE (operands[2]) != CONST_INT | |
10482 | || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3) | |
10483 | abort (); | |
10484 | operands[1] = gen_rtx_MULT (DImode, operands[1], | |
10485 | GEN_INT (1 << INTVAL (operands[2]))); | |
0f40f9f7 | 10486 | return "lea{q}\t{%a1, %0|%0, %a1}"; |
371bc54b JH |
10487 | |
10488 | default: | |
10489 | if (REG_P (operands[2])) | |
0f40f9f7 | 10490 | return "sal{q}\t{%b2, %0|%0, %b2}"; |
371bc54b JH |
10491 | else if (GET_CODE (operands[2]) == CONST_INT |
10492 | && INTVAL (operands[2]) == 1 | |
10493 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 10494 | return "sal{q}\t%0"; |
371bc54b | 10495 | else |
0f40f9f7 | 10496 | return "sal{q}\t{%2, %0|%0, %2}"; |
371bc54b | 10497 | } |
0f40f9f7 | 10498 | } |
371bc54b JH |
10499 | [(set (attr "type") |
10500 | (cond [(eq_attr "alternative" "1") | |
10501 | (const_string "lea") | |
10502 | (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10503 | (const_int 0)) | |
10504 | (match_operand 0 "register_operand" "")) | |
10505 | (match_operand 2 "const1_operand" "")) | |
10506 | (const_string "alu") | |
10507 | ] | |
10508 | (const_string "ishift"))) | |
10509 | (set_attr "mode" "DI")]) | |
10510 | ||
10511 | ;; Convert lea to the lea pattern to avoid flags dependency. | |
10512 | (define_split | |
10513 | [(set (match_operand:DI 0 "register_operand" "") | |
10514 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
10515 | (match_operand:QI 2 "immediate_operand" ""))) | |
10516 | (clobber (reg:CC 17))] | |
1b0c37d7 | 10517 | "TARGET_64BIT && reload_completed |
371bc54b JH |
10518 | && true_regnum (operands[0]) != true_regnum (operands[1])" |
10519 | [(set (match_dup 0) | |
10520 | (mult:DI (match_dup 1) | |
10521 | (match_dup 2)))] | |
383252a7 AO |
10522 | "operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]), |
10523 | DImode));") | |
371bc54b JH |
10524 | |
10525 | ;; This pattern can't accept a variable shift count, since shifts by | |
10526 | ;; zero don't affect the flags. We assume that shifts by constant | |
10527 | ;; zero are optimized away. | |
10528 | (define_insn "*ashldi3_cmp_rex64" | |
10529 | [(set (reg 17) | |
10530 | (compare | |
10531 | (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
10532 | (match_operand:QI 2 "immediate_operand" "e")) | |
10533 | (const_int 0))) | |
10534 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
10535 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
10536 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
10537 | && ix86_binary_operator_ok (ASHIFT, DImode, operands)" | |
371bc54b JH |
10538 | { |
10539 | switch (get_attr_type (insn)) | |
10540 | { | |
10541 | case TYPE_ALU: | |
10542 | if (operands[2] != const1_rtx) | |
10543 | abort (); | |
0f40f9f7 | 10544 | return "add{q}\t{%0, %0|%0, %0}"; |
371bc54b JH |
10545 | |
10546 | default: | |
10547 | if (REG_P (operands[2])) | |
0f40f9f7 | 10548 | return "sal{q}\t{%b2, %0|%0, %b2}"; |
371bc54b JH |
10549 | else if (GET_CODE (operands[2]) == CONST_INT |
10550 | && INTVAL (operands[2]) == 1 | |
10551 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 10552 | return "sal{q}\t%0"; |
371bc54b | 10553 | else |
0f40f9f7 | 10554 | return "sal{q}\t{%2, %0|%0, %2}"; |
371bc54b | 10555 | } |
0f40f9f7 | 10556 | } |
371bc54b JH |
10557 | [(set (attr "type") |
10558 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10559 | (const_int 0)) | |
10560 | (match_operand 0 "register_operand" "")) | |
10561 | (match_operand 2 "const1_operand" "")) | |
10562 | (const_string "alu") | |
10563 | ] | |
10564 | (const_string "ishift"))) | |
10565 | (set_attr "mode" "DI")]) | |
10566 | ||
e075ae69 RH |
10567 | (define_insn "ashldi3_1" |
10568 | [(set (match_operand:DI 0 "register_operand" "=r") | |
56c0e8fa | 10569 | (ashift:DI (match_operand:DI 1 "register_operand" "0") |
e075ae69 RH |
10570 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) |
10571 | (clobber (match_scratch:SI 3 "=&r")) | |
10572 | (clobber (reg:CC 17))] | |
371bc54b | 10573 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 RH |
10574 | "#" |
10575 | [(set_attr "type" "multi")]) | |
886c62d1 | 10576 | |
e075ae69 RH |
10577 | (define_insn "*ashldi3_2" |
10578 | [(set (match_operand:DI 0 "register_operand" "=r") | |
56c0e8fa | 10579 | (ashift:DI (match_operand:DI 1 "register_operand" "0") |
e075ae69 RH |
10580 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) |
10581 | (clobber (reg:CC 17))] | |
371bc54b | 10582 | "!TARGET_64BIT" |
e075ae69 RH |
10583 | "#" |
10584 | [(set_attr "type" "multi")]) | |
886c62d1 | 10585 | |
e075ae69 RH |
10586 | (define_split |
10587 | [(set (match_operand:DI 0 "register_operand" "") | |
10588 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
10589 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
10590 | (clobber (match_scratch:SI 3 "")) | |
10591 | (clobber (reg:CC 17))] | |
371bc54b | 10592 | "!TARGET_64BIT && TARGET_CMOVE && reload_completed" |
e075ae69 RH |
10593 | [(const_int 0)] |
10594 | "ix86_split_ashldi (operands, operands[3]); DONE;") | |
47f59fd4 | 10595 | |
e075ae69 RH |
10596 | (define_split |
10597 | [(set (match_operand:DI 0 "register_operand" "") | |
10598 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
10599 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
10600 | (clobber (reg:CC 17))] | |
371bc54b | 10601 | "!TARGET_64BIT && reload_completed" |
e075ae69 RH |
10602 | [(const_int 0)] |
10603 | "ix86_split_ashldi (operands, NULL_RTX); DONE;") | |
6ec6d558 | 10604 | |
e075ae69 RH |
10605 | (define_insn "x86_shld_1" |
10606 | [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m") | |
10607 | (ior:SI (ashift:SI (match_dup 0) | |
10608 | (match_operand:QI 2 "nonmemory_operand" "I,c")) | |
10609 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") | |
10610 | (minus:QI (const_int 32) (match_dup 2))))) | |
10611 | (clobber (reg:CC 17))] | |
6ec6d558 | 10612 | "" |
e075ae69 | 10613 | "@ |
0f40f9f7 ZW |
10614 | shld{l}\t{%2, %1, %0|%0, %1, %2} |
10615 | shld{l}\t{%s2%1, %0|%0, %1, %2}" | |
e075ae69 | 10616 | [(set_attr "type" "ishift") |
6ef67412 JH |
10617 | (set_attr "prefix_0f" "1") |
10618 | (set_attr "mode" "SI") | |
e075ae69 | 10619 | (set_attr "pent_pair" "np") |
309ada50 | 10620 | (set_attr "athlon_decode" "vector") |
e075ae69 RH |
10621 | (set_attr "ppro_uops" "few")]) |
10622 | ||
10623 | (define_expand "x86_shift_adj_1" | |
16189740 RH |
10624 | [(set (reg:CCZ 17) |
10625 | (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "") | |
10626 | (const_int 32)) | |
10627 | (const_int 0))) | |
e075ae69 | 10628 | (set (match_operand:SI 0 "register_operand" "") |
16189740 | 10629 | (if_then_else:SI (ne (reg:CCZ 17) (const_int 0)) |
e075ae69 RH |
10630 | (match_operand:SI 1 "register_operand" "") |
10631 | (match_dup 0))) | |
10632 | (set (match_dup 1) | |
16189740 | 10633 | (if_then_else:SI (ne (reg:CCZ 17) (const_int 0)) |
e075ae69 RH |
10634 | (match_operand:SI 3 "register_operand" "r") |
10635 | (match_dup 1)))] | |
10636 | "TARGET_CMOVE" | |
6ec6d558 JH |
10637 | "") |
10638 | ||
e075ae69 RH |
10639 | (define_expand "x86_shift_adj_2" |
10640 | [(use (match_operand:SI 0 "register_operand" "")) | |
10641 | (use (match_operand:SI 1 "register_operand" "")) | |
10642 | (use (match_operand:QI 2 "register_operand" ""))] | |
886c62d1 | 10643 | "" |
e075ae69 RH |
10644 | { |
10645 | rtx label = gen_label_rtx (); | |
10646 | rtx tmp; | |
886c62d1 | 10647 | |
16189740 | 10648 | emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32))); |
886c62d1 | 10649 | |
16189740 | 10650 | tmp = gen_rtx_REG (CCZmode, FLAGS_REG); |
e075ae69 RH |
10651 | tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); |
10652 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
10653 | gen_rtx_LABEL_REF (VOIDmode, label), | |
10654 | pc_rtx); | |
10655 | tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
10656 | JUMP_LABEL (tmp) = label; | |
886c62d1 | 10657 | |
e075ae69 RH |
10658 | emit_move_insn (operands[0], operands[1]); |
10659 | emit_move_insn (operands[1], const0_rtx); | |
886c62d1 | 10660 | |
e075ae69 RH |
10661 | emit_label (label); |
10662 | LABEL_NUSES (label) = 1; | |
56c0e8fa JVA |
10663 | |
10664 | DONE; | |
0f40f9f7 | 10665 | }) |
56c0e8fa | 10666 | |
d525dfdf JH |
10667 | (define_expand "ashlsi3" |
10668 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
10669 | (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
10670 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
10671 | (clobber (reg:CC 17))] | |
10672 | "" | |
10673 | "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;") | |
10674 | ||
10675 | (define_insn "*ashlsi3_1" | |
e075ae69 RH |
10676 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") |
10677 | (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r") | |
10678 | (match_operand:QI 2 "nonmemory_operand" "cI,M"))) | |
10679 | (clobber (reg:CC 17))] | |
d525dfdf | 10680 | "ix86_binary_operator_ok (ASHIFT, SImode, operands)" |
2ae0f82c | 10681 | { |
e075ae69 RH |
10682 | switch (get_attr_type (insn)) |
10683 | { | |
10684 | case TYPE_ALU: | |
10685 | if (operands[2] != const1_rtx) | |
10686 | abort (); | |
10687 | if (!rtx_equal_p (operands[0], operands[1])) | |
10688 | abort (); | |
0f40f9f7 | 10689 | return "add{l}\t{%0, %0|%0, %0}"; |
2ae0f82c | 10690 | |
e075ae69 | 10691 | case TYPE_LEA: |
0f40f9f7 | 10692 | return "#"; |
2ae0f82c | 10693 | |
e075ae69 RH |
10694 | default: |
10695 | if (REG_P (operands[2])) | |
0f40f9f7 | 10696 | return "sal{l}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
10697 | else if (GET_CODE (operands[2]) == CONST_INT |
10698 | && INTVAL (operands[2]) == 1 | |
10699 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 10700 | return "sal{l}\t%0"; |
e075ae69 | 10701 | else |
0f40f9f7 | 10702 | return "sal{l}\t{%2, %0|%0, %2}"; |
e075ae69 | 10703 | } |
0f40f9f7 | 10704 | } |
e075ae69 RH |
10705 | [(set (attr "type") |
10706 | (cond [(eq_attr "alternative" "1") | |
10707 | (const_string "lea") | |
10708 | (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10709 | (const_int 0)) | |
10710 | (match_operand 0 "register_operand" "")) | |
10711 | (match_operand 2 "const1_operand" "")) | |
10712 | (const_string "alu") | |
10713 | ] | |
6ef67412 JH |
10714 | (const_string "ishift"))) |
10715 | (set_attr "mode" "SI")]) | |
e075ae69 | 10716 | |
1c27d4b2 JH |
10717 | ;; Convert lea to the lea pattern to avoid flags dependency. |
10718 | (define_split | |
58787064 JH |
10719 | [(set (match_operand 0 "register_operand" "") |
10720 | (ashift (match_operand 1 "register_operand" "") | |
ca4ae08d | 10721 | (match_operand:QI 2 "const_int_operand" ""))) |
1c27d4b2 | 10722 | (clobber (reg:CC 17))] |
abe24fb3 JH |
10723 | "reload_completed |
10724 | && true_regnum (operands[0]) != true_regnum (operands[1])" | |
58787064 | 10725 | [(const_int 0)] |
58787064 JH |
10726 | { |
10727 | rtx pat; | |
10728 | operands[0] = gen_lowpart (SImode, operands[0]); | |
10729 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
383252a7 AO |
10730 | operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]), |
10731 | Pmode)); | |
58787064 JH |
10732 | pat = gen_rtx_MULT (Pmode, operands[1], operands[2]); |
10733 | if (Pmode != SImode) | |
10734 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
10735 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
10736 | DONE; | |
0f40f9f7 | 10737 | }) |
1c27d4b2 | 10738 | |
371bc54b JH |
10739 | (define_insn "*ashlsi3_1_zext" |
10740 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
10741 | (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r") | |
10742 | (match_operand:QI 2 "nonmemory_operand" "cI,M")))) | |
10743 | (clobber (reg:CC 17))] | |
1b0c37d7 | 10744 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)" |
371bc54b JH |
10745 | { |
10746 | switch (get_attr_type (insn)) | |
10747 | { | |
10748 | case TYPE_ALU: | |
10749 | if (operands[2] != const1_rtx) | |
10750 | abort (); | |
0f40f9f7 | 10751 | return "add{l}\t{%k0, %k0|%k0, %k0}"; |
371bc54b JH |
10752 | |
10753 | case TYPE_LEA: | |
0f40f9f7 | 10754 | return "#"; |
371bc54b JH |
10755 | |
10756 | default: | |
10757 | if (REG_P (operands[2])) | |
0f40f9f7 | 10758 | return "sal{l}\t{%b2, %k0|%k0, %b2}"; |
371bc54b JH |
10759 | else if (GET_CODE (operands[2]) == CONST_INT |
10760 | && INTVAL (operands[2]) == 1 | |
10761 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 10762 | return "sal{l}\t%k0"; |
371bc54b | 10763 | else |
0f40f9f7 | 10764 | return "sal{l}\t{%2, %k0|%k0, %2}"; |
371bc54b | 10765 | } |
0f40f9f7 | 10766 | } |
371bc54b JH |
10767 | [(set (attr "type") |
10768 | (cond [(eq_attr "alternative" "1") | |
10769 | (const_string "lea") | |
10770 | (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10771 | (const_int 0)) | |
10772 | (match_operand 2 "const1_operand" "")) | |
10773 | (const_string "alu") | |
10774 | ] | |
10775 | (const_string "ishift"))) | |
10776 | (set_attr "mode" "SI")]) | |
10777 | ||
10778 | ;; Convert lea to the lea pattern to avoid flags dependency. | |
10779 | (define_split | |
10780 | [(set (match_operand:DI 0 "register_operand" "") | |
10781 | (zero_extend:DI (ashift (match_operand 1 "register_operand" "") | |
10782 | (match_operand:QI 2 "const_int_operand" "")))) | |
10783 | (clobber (reg:CC 17))] | |
10784 | "reload_completed | |
10785 | && true_regnum (operands[0]) != true_regnum (operands[1])" | |
10786 | [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))] | |
371bc54b JH |
10787 | { |
10788 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
383252a7 AO |
10789 | operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]), |
10790 | Pmode)); | |
0f40f9f7 | 10791 | }) |
371bc54b | 10792 | |
28cefcd2 BS |
10793 | ;; This pattern can't accept a variable shift count, since shifts by |
10794 | ;; zero don't affect the flags. We assume that shifts by constant | |
10795 | ;; zero are optimized away. | |
2c873473 | 10796 | (define_insn "*ashlsi3_cmp" |
16189740 RH |
10797 | [(set (reg 17) |
10798 | (compare | |
e075ae69 | 10799 | (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
28cefcd2 | 10800 | (match_operand:QI 2 "immediate_operand" "I")) |
e075ae69 RH |
10801 | (const_int 0))) |
10802 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
10803 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 10804 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 10805 | && ix86_binary_operator_ok (ASHIFT, SImode, operands)" |
886c62d1 | 10806 | { |
e075ae69 | 10807 | switch (get_attr_type (insn)) |
886c62d1 | 10808 | { |
e075ae69 RH |
10809 | case TYPE_ALU: |
10810 | if (operands[2] != const1_rtx) | |
10811 | abort (); | |
0f40f9f7 | 10812 | return "add{l}\t{%0, %0|%0, %0}"; |
886c62d1 | 10813 | |
e075ae69 RH |
10814 | default: |
10815 | if (REG_P (operands[2])) | |
0f40f9f7 | 10816 | return "sal{l}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
10817 | else if (GET_CODE (operands[2]) == CONST_INT |
10818 | && INTVAL (operands[2]) == 1 | |
10819 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 10820 | return "sal{l}\t%0"; |
e075ae69 | 10821 | else |
0f40f9f7 | 10822 | return "sal{l}\t{%2, %0|%0, %2}"; |
56c0e8fa | 10823 | } |
0f40f9f7 | 10824 | } |
e075ae69 RH |
10825 | [(set (attr "type") |
10826 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10827 | (const_int 0)) | |
10828 | (match_operand 0 "register_operand" "")) | |
10829 | (match_operand 2 "const1_operand" "")) | |
10830 | (const_string "alu") | |
10831 | ] | |
6ef67412 JH |
10832 | (const_string "ishift"))) |
10833 | (set_attr "mode" "SI")]) | |
e075ae69 | 10834 | |
371bc54b JH |
10835 | (define_insn "*ashlsi3_cmp_zext" |
10836 | [(set (reg 17) | |
10837 | (compare | |
10838 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
10839 | (match_operand:QI 2 "immediate_operand" "I")) | |
10840 | (const_int 0))) | |
10841 | (set (match_operand:DI 0 "register_operand" "=r") | |
10842 | (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))] | |
10843 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
10844 | && ix86_binary_operator_ok (ASHIFT, SImode, operands)" | |
371bc54b JH |
10845 | { |
10846 | switch (get_attr_type (insn)) | |
10847 | { | |
10848 | case TYPE_ALU: | |
10849 | if (operands[2] != const1_rtx) | |
10850 | abort (); | |
0f40f9f7 | 10851 | return "add{l}\t{%k0, %k0|%k0, %k0}"; |
371bc54b JH |
10852 | |
10853 | default: | |
10854 | if (REG_P (operands[2])) | |
0f40f9f7 | 10855 | return "sal{l}\t{%b2, %k0|%k0, %b2}"; |
371bc54b JH |
10856 | else if (GET_CODE (operands[2]) == CONST_INT |
10857 | && INTVAL (operands[2]) == 1 | |
10858 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 10859 | return "sal{l}\t%k0"; |
371bc54b | 10860 | else |
0f40f9f7 | 10861 | return "sal{l}\t{%2, %k0|%k0, %2}"; |
371bc54b | 10862 | } |
0f40f9f7 | 10863 | } |
371bc54b JH |
10864 | [(set (attr "type") |
10865 | (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10866 | (const_int 0)) | |
10867 | (match_operand 2 "const1_operand" "")) | |
10868 | (const_string "alu") | |
10869 | ] | |
10870 | (const_string "ishift"))) | |
10871 | (set_attr "mode" "SI")]) | |
10872 | ||
d525dfdf JH |
10873 | (define_expand "ashlhi3" |
10874 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
10875 | (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
10876 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
10877 | (clobber (reg:CC 17))] | |
d9f32422 | 10878 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
10879 | "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;") |
10880 | ||
58787064 JH |
10881 | (define_insn "*ashlhi3_1_lea" |
10882 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") | |
10883 | (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r") | |
10884 | (match_operand:QI 2 "nonmemory_operand" "cI,M"))) | |
10885 | (clobber (reg:CC 17))] | |
10886 | "!TARGET_PARTIAL_REG_STALL | |
10887 | && ix86_binary_operator_ok (ASHIFT, HImode, operands)" | |
58787064 JH |
10888 | { |
10889 | switch (get_attr_type (insn)) | |
10890 | { | |
10891 | case TYPE_LEA: | |
0f40f9f7 | 10892 | return "#"; |
58787064 JH |
10893 | case TYPE_ALU: |
10894 | if (operands[2] != const1_rtx) | |
10895 | abort (); | |
0f40f9f7 | 10896 | return "add{w}\t{%0, %0|%0, %0}"; |
58787064 JH |
10897 | |
10898 | default: | |
10899 | if (REG_P (operands[2])) | |
0f40f9f7 | 10900 | return "sal{w}\t{%b2, %0|%0, %b2}"; |
58787064 JH |
10901 | else if (GET_CODE (operands[2]) == CONST_INT |
10902 | && INTVAL (operands[2]) == 1 | |
10903 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 10904 | return "sal{w}\t%0"; |
58787064 | 10905 | else |
0f40f9f7 | 10906 | return "sal{w}\t{%2, %0|%0, %2}"; |
58787064 | 10907 | } |
0f40f9f7 | 10908 | } |
58787064 JH |
10909 | [(set (attr "type") |
10910 | (cond [(eq_attr "alternative" "1") | |
10911 | (const_string "lea") | |
10912 | (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10913 | (const_int 0)) | |
10914 | (match_operand 0 "register_operand" "")) | |
10915 | (match_operand 2 "const1_operand" "")) | |
10916 | (const_string "alu") | |
10917 | ] | |
10918 | (const_string "ishift"))) | |
10919 | (set_attr "mode" "HI,SI")]) | |
10920 | ||
d525dfdf | 10921 | (define_insn "*ashlhi3_1" |
e075ae69 RH |
10922 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
10923 | (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
10924 | (match_operand:QI 2 "nonmemory_operand" "cI"))) | |
10925 | (clobber (reg:CC 17))] | |
58787064 JH |
10926 | "TARGET_PARTIAL_REG_STALL |
10927 | && ix86_binary_operator_ok (ASHIFT, HImode, operands)" | |
56c0e8fa | 10928 | { |
e075ae69 RH |
10929 | switch (get_attr_type (insn)) |
10930 | { | |
10931 | case TYPE_ALU: | |
10932 | if (operands[2] != const1_rtx) | |
10933 | abort (); | |
0f40f9f7 | 10934 | return "add{w}\t{%0, %0|%0, %0}"; |
886c62d1 | 10935 | |
e075ae69 RH |
10936 | default: |
10937 | if (REG_P (operands[2])) | |
0f40f9f7 | 10938 | return "sal{w}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
10939 | else if (GET_CODE (operands[2]) == CONST_INT |
10940 | && INTVAL (operands[2]) == 1 | |
10941 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 10942 | return "sal{w}\t%0"; |
e075ae69 | 10943 | else |
0f40f9f7 | 10944 | return "sal{w}\t{%2, %0|%0, %2}"; |
e075ae69 | 10945 | } |
0f40f9f7 | 10946 | } |
e075ae69 RH |
10947 | [(set (attr "type") |
10948 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10949 | (const_int 0)) | |
10950 | (match_operand 0 "register_operand" "")) | |
10951 | (match_operand 2 "const1_operand" "")) | |
10952 | (const_string "alu") | |
10953 | ] | |
6ef67412 JH |
10954 | (const_string "ishift"))) |
10955 | (set_attr "mode" "HI")]) | |
bb62e19a | 10956 | |
28cefcd2 BS |
10957 | ;; This pattern can't accept a variable shift count, since shifts by |
10958 | ;; zero don't affect the flags. We assume that shifts by constant | |
10959 | ;; zero are optimized away. | |
2c873473 | 10960 | (define_insn "*ashlhi3_cmp" |
16189740 RH |
10961 | [(set (reg 17) |
10962 | (compare | |
e075ae69 | 10963 | (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
28cefcd2 | 10964 | (match_operand:QI 2 "immediate_operand" "I")) |
e075ae69 RH |
10965 | (const_int 0))) |
10966 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
10967 | (ashift:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 10968 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 10969 | && ix86_binary_operator_ok (ASHIFT, HImode, operands)" |
886c62d1 | 10970 | { |
e075ae69 RH |
10971 | switch (get_attr_type (insn)) |
10972 | { | |
10973 | case TYPE_ALU: | |
10974 | if (operands[2] != const1_rtx) | |
10975 | abort (); | |
0f40f9f7 | 10976 | return "add{w}\t{%0, %0|%0, %0}"; |
886c62d1 | 10977 | |
e075ae69 RH |
10978 | default: |
10979 | if (REG_P (operands[2])) | |
0f40f9f7 | 10980 | return "sal{w}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
10981 | else if (GET_CODE (operands[2]) == CONST_INT |
10982 | && INTVAL (operands[2]) == 1 | |
10983 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 10984 | return "sal{w}\t%0"; |
e075ae69 | 10985 | else |
0f40f9f7 | 10986 | return "sal{w}\t{%2, %0|%0, %2}"; |
e075ae69 | 10987 | } |
0f40f9f7 | 10988 | } |
e075ae69 RH |
10989 | [(set (attr "type") |
10990 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10991 | (const_int 0)) | |
10992 | (match_operand 0 "register_operand" "")) | |
10993 | (match_operand 2 "const1_operand" "")) | |
10994 | (const_string "alu") | |
10995 | ] | |
6ef67412 JH |
10996 | (const_string "ishift"))) |
10997 | (set_attr "mode" "HI")]) | |
e075ae69 | 10998 | |
d525dfdf JH |
10999 | (define_expand "ashlqi3" |
11000 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
11001 | (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
11002 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11003 | (clobber (reg:CC 17))] | |
d9f32422 | 11004 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
11005 | "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;") |
11006 | ||
e075ae69 | 11007 | ;; %%% Potential partial reg stall on alternative 2. What to do? |
58787064 JH |
11008 | |
11009 | (define_insn "*ashlqi3_1_lea" | |
11010 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r") | |
11011 | (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r") | |
91f9a498 | 11012 | (match_operand:QI 2 "nonmemory_operand" "cI,cI,M"))) |
58787064 JH |
11013 | (clobber (reg:CC 17))] |
11014 | "!TARGET_PARTIAL_REG_STALL | |
11015 | && ix86_binary_operator_ok (ASHIFT, QImode, operands)" | |
58787064 JH |
11016 | { |
11017 | switch (get_attr_type (insn)) | |
11018 | { | |
11019 | case TYPE_LEA: | |
0f40f9f7 | 11020 | return "#"; |
58787064 JH |
11021 | case TYPE_ALU: |
11022 | if (operands[2] != const1_rtx) | |
11023 | abort (); | |
1a06f5fe | 11024 | if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1])) |
0f40f9f7 | 11025 | return "add{l}\t{%k0, %k0|%k0, %k0}"; |
58787064 | 11026 | else |
0f40f9f7 | 11027 | return "add{b}\t{%0, %0|%0, %0}"; |
58787064 JH |
11028 | |
11029 | default: | |
11030 | if (REG_P (operands[2])) | |
11031 | { | |
11032 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 11033 | return "sal{l}\t{%b2, %k0|%k0, %b2}"; |
58787064 | 11034 | else |
0f40f9f7 | 11035 | return "sal{b}\t{%b2, %0|%0, %b2}"; |
58787064 JH |
11036 | } |
11037 | else if (GET_CODE (operands[2]) == CONST_INT | |
11038 | && INTVAL (operands[2]) == 1 | |
11039 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
11040 | { | |
11041 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 11042 | return "sal{l}\t%0"; |
58787064 | 11043 | else |
0f40f9f7 | 11044 | return "sal{b}\t%0"; |
58787064 JH |
11045 | } |
11046 | else | |
11047 | { | |
11048 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 11049 | return "sal{l}\t{%2, %k0|%k0, %2}"; |
58787064 | 11050 | else |
0f40f9f7 | 11051 | return "sal{b}\t{%2, %0|%0, %2}"; |
58787064 JH |
11052 | } |
11053 | } | |
0f40f9f7 | 11054 | } |
58787064 JH |
11055 | [(set (attr "type") |
11056 | (cond [(eq_attr "alternative" "2") | |
11057 | (const_string "lea") | |
11058 | (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
11059 | (const_int 0)) | |
11060 | (match_operand 0 "register_operand" "")) | |
11061 | (match_operand 2 "const1_operand" "")) | |
11062 | (const_string "alu") | |
11063 | ] | |
11064 | (const_string "ishift"))) | |
11065 | (set_attr "mode" "QI,SI,SI")]) | |
11066 | ||
d525dfdf JH |
11067 | (define_insn "*ashlqi3_1" |
11068 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r") | |
e075ae69 RH |
11069 | (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") |
11070 | (match_operand:QI 2 "nonmemory_operand" "cI,cI"))) | |
11071 | (clobber (reg:CC 17))] | |
58787064 JH |
11072 | "TARGET_PARTIAL_REG_STALL |
11073 | && ix86_binary_operator_ok (ASHIFT, QImode, operands)" | |
886c62d1 | 11074 | { |
e075ae69 RH |
11075 | switch (get_attr_type (insn)) |
11076 | { | |
11077 | case TYPE_ALU: | |
11078 | if (operands[2] != const1_rtx) | |
11079 | abort (); | |
1a06f5fe | 11080 | if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1])) |
0f40f9f7 | 11081 | return "add{l}\t{%k0, %k0|%k0, %k0}"; |
e075ae69 | 11082 | else |
0f40f9f7 | 11083 | return "add{b}\t{%0, %0|%0, %0}"; |
886c62d1 | 11084 | |
e075ae69 RH |
11085 | default: |
11086 | if (REG_P (operands[2])) | |
11087 | { | |
1a06f5fe | 11088 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 11089 | return "sal{l}\t{%b2, %k0|%k0, %b2}"; |
e075ae69 | 11090 | else |
0f40f9f7 | 11091 | return "sal{b}\t{%b2, %0|%0, %b2}"; |
e075ae69 | 11092 | } |
8bad7136 JL |
11093 | else if (GET_CODE (operands[2]) == CONST_INT |
11094 | && INTVAL (operands[2]) == 1 | |
11095 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
11096 | { | |
1a06f5fe | 11097 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 11098 | return "sal{l}\t%0"; |
8bad7136 | 11099 | else |
0f40f9f7 | 11100 | return "sal{b}\t%0"; |
8bad7136 | 11101 | } |
e075ae69 RH |
11102 | else |
11103 | { | |
1a06f5fe | 11104 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 11105 | return "sal{l}\t{%2, %k0|%k0, %2}"; |
e075ae69 | 11106 | else |
0f40f9f7 | 11107 | return "sal{b}\t{%2, %0|%0, %2}"; |
e075ae69 RH |
11108 | } |
11109 | } | |
0f40f9f7 | 11110 | } |
e075ae69 RH |
11111 | [(set (attr "type") |
11112 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
11113 | (const_int 0)) | |
11114 | (match_operand 0 "register_operand" "")) | |
11115 | (match_operand 2 "const1_operand" "")) | |
11116 | (const_string "alu") | |
11117 | ] | |
6ef67412 JH |
11118 | (const_string "ishift"))) |
11119 | (set_attr "mode" "QI,SI")]) | |
e075ae69 | 11120 | |
28cefcd2 BS |
11121 | ;; This pattern can't accept a variable shift count, since shifts by |
11122 | ;; zero don't affect the flags. We assume that shifts by constant | |
11123 | ;; zero are optimized away. | |
2c873473 | 11124 | (define_insn "*ashlqi3_cmp" |
16189740 RH |
11125 | [(set (reg 17) |
11126 | (compare | |
e075ae69 | 11127 | (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
28cefcd2 | 11128 | (match_operand:QI 2 "immediate_operand" "I")) |
e075ae69 RH |
11129 | (const_int 0))) |
11130 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
11131 | (ashift:QI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 11132 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11133 | && ix86_binary_operator_ok (ASHIFT, QImode, operands)" |
886c62d1 | 11134 | { |
e075ae69 RH |
11135 | switch (get_attr_type (insn)) |
11136 | { | |
11137 | case TYPE_ALU: | |
11138 | if (operands[2] != const1_rtx) | |
11139 | abort (); | |
0f40f9f7 | 11140 | return "add{b}\t{%0, %0|%0, %0}"; |
e075ae69 RH |
11141 | |
11142 | default: | |
11143 | if (REG_P (operands[2])) | |
0f40f9f7 | 11144 | return "sal{b}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
11145 | else if (GET_CODE (operands[2]) == CONST_INT |
11146 | && INTVAL (operands[2]) == 1 | |
11147 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)) | |
0f40f9f7 | 11148 | return "sal{b}\t%0"; |
e075ae69 | 11149 | else |
0f40f9f7 | 11150 | return "sal{b}\t{%2, %0|%0, %2}"; |
e075ae69 | 11151 | } |
0f40f9f7 | 11152 | } |
e075ae69 RH |
11153 | [(set (attr "type") |
11154 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
11155 | (const_int 0)) | |
11156 | (match_operand 0 "register_operand" "")) | |
11157 | (match_operand 2 "const1_operand" "")) | |
11158 | (const_string "alu") | |
11159 | ] | |
6ef67412 JH |
11160 | (const_string "ishift"))) |
11161 | (set_attr "mode" "QI")]) | |
886c62d1 JVA |
11162 | |
11163 | ;; See comment above `ashldi3' about how this works. | |
11164 | ||
e075ae69 | 11165 | (define_expand "ashrdi3" |
371bc54b JH |
11166 | [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") |
11167 | (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") | |
11168 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
e075ae69 | 11169 | (clobber (reg:CC 17))])] |
56c0e8fa | 11170 | "" |
56c0e8fa | 11171 | { |
371bc54b | 11172 | if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) |
56c0e8fa | 11173 | { |
e075ae69 RH |
11174 | emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2])); |
11175 | DONE; | |
56c0e8fa | 11176 | } |
371bc54b JH |
11177 | ix86_expand_binary_operator (ASHIFTRT, DImode, operands); |
11178 | DONE; | |
0f40f9f7 | 11179 | }) |
2ae0f82c | 11180 | |
371bc54b JH |
11181 | (define_insn "ashrdi3_63_rex64" |
11182 | [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm") | |
11183 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0") | |
11184 | (match_operand:DI 2 "const_int_operand" "i,i"))) | |
11185 | (clobber (reg:CC 17))] | |
11186 | "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size) | |
11187 | && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" | |
11188 | "@ | |
11189 | {cqto|cqo} | |
0f40f9f7 | 11190 | sar{q}\t{%2, %0|%0, %2}" |
371bc54b JH |
11191 | [(set_attr "type" "imovx,ishift") |
11192 | (set_attr "prefix_0f" "0,*") | |
11193 | (set_attr "length_immediate" "0,*") | |
11194 | (set_attr "modrm" "0,1") | |
11195 | (set_attr "mode" "DI")]) | |
11196 | ||
11197 | (define_insn "*ashrdi3_1_one_bit_rex64" | |
11198 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11199 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11200 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11201 | (clobber (reg:CC 17))] | |
11202 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands) | |
11203 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11204 | "sar{q}\t%0" |
371bc54b JH |
11205 | [(set_attr "type" "ishift") |
11206 | (set (attr "length") | |
11207 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
11208 | (const_string "2") | |
11209 | (const_string "*")))]) | |
11210 | ||
11211 | (define_insn "*ashrdi3_1_rex64" | |
11212 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") | |
11213 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
7c17f553 | 11214 | (match_operand:QI 2 "nonmemory_operand" "J,c"))) |
371bc54b JH |
11215 | (clobber (reg:CC 17))] |
11216 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" | |
11217 | "@ | |
0f40f9f7 ZW |
11218 | sar{q}\t{%2, %0|%0, %2} |
11219 | sar{q}\t{%b2, %0|%0, %b2}" | |
371bc54b JH |
11220 | [(set_attr "type" "ishift") |
11221 | (set_attr "mode" "DI")]) | |
11222 | ||
11223 | ;; This pattern can't accept a variable shift count, since shifts by | |
11224 | ;; zero don't affect the flags. We assume that shifts by constant | |
11225 | ;; zero are optimized away. | |
11226 | (define_insn "*ashrdi3_one_bit_cmp_rex64" | |
11227 | [(set (reg 17) | |
11228 | (compare | |
11229 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11230 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11231 | (const_int 0))) | |
11232 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11233 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
11234 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11235 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) | |
11236 | && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" | |
0f40f9f7 | 11237 | "sar{q}\t%0" |
371bc54b JH |
11238 | [(set_attr "type" "ishift") |
11239 | (set (attr "length") | |
11240 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
11241 | (const_string "2") | |
11242 | (const_string "*")))]) | |
11243 | ||
11244 | ;; This pattern can't accept a variable shift count, since shifts by | |
11245 | ;; zero don't affect the flags. We assume that shifts by constant | |
11246 | ;; zero are optimized away. | |
11247 | (define_insn "*ashrdi3_cmp_rex64" | |
11248 | [(set (reg 17) | |
11249 | (compare | |
11250 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11251 | (match_operand:QI 2 "const_int_operand" "n")) | |
11252 | (const_int 0))) | |
11253 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11254 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
11255 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11256 | && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" | |
0f40f9f7 | 11257 | "sar{q}\t{%2, %0|%0, %2}" |
371bc54b JH |
11258 | [(set_attr "type" "ishift") |
11259 | (set_attr "mode" "DI")]) | |
11260 | ||
11261 | ||
e075ae69 RH |
11262 | (define_insn "ashrdi3_1" |
11263 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11264 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
11265 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) | |
11266 | (clobber (match_scratch:SI 3 "=&r")) | |
11267 | (clobber (reg:CC 17))] | |
371bc54b | 11268 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 RH |
11269 | "#" |
11270 | [(set_attr "type" "multi")]) | |
886c62d1 | 11271 | |
e075ae69 RH |
11272 | (define_insn "*ashrdi3_2" |
11273 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11274 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
11275 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) | |
11276 | (clobber (reg:CC 17))] | |
371bc54b | 11277 | "!TARGET_64BIT" |
e075ae69 RH |
11278 | "#" |
11279 | [(set_attr "type" "multi")]) | |
886c62d1 | 11280 | |
e075ae69 RH |
11281 | (define_split |
11282 | [(set (match_operand:DI 0 "register_operand" "") | |
11283 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
11284 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11285 | (clobber (match_scratch:SI 3 "")) | |
11286 | (clobber (reg:CC 17))] | |
371bc54b | 11287 | "!TARGET_64BIT && TARGET_CMOVE && reload_completed" |
e075ae69 RH |
11288 | [(const_int 0)] |
11289 | "ix86_split_ashrdi (operands, operands[3]); DONE;") | |
886c62d1 | 11290 | |
e075ae69 RH |
11291 | (define_split |
11292 | [(set (match_operand:DI 0 "register_operand" "") | |
11293 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
11294 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11295 | (clobber (reg:CC 17))] | |
371bc54b | 11296 | "!TARGET_64BIT && reload_completed" |
e075ae69 RH |
11297 | [(const_int 0)] |
11298 | "ix86_split_ashrdi (operands, NULL_RTX); DONE;") | |
886c62d1 | 11299 | |
e075ae69 RH |
11300 | (define_insn "x86_shrd_1" |
11301 | [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m") | |
11302 | (ior:SI (ashiftrt:SI (match_dup 0) | |
11303 | (match_operand:QI 2 "nonmemory_operand" "I,c")) | |
11304 | (ashift:SI (match_operand:SI 1 "register_operand" "r,r") | |
11305 | (minus:QI (const_int 32) (match_dup 2))))) | |
11306 | (clobber (reg:CC 17))] | |
886c62d1 | 11307 | "" |
e075ae69 | 11308 | "@ |
0f40f9f7 ZW |
11309 | shrd{l}\t{%2, %1, %0|%0, %1, %2} |
11310 | shrd{l}\t{%s2%1, %0|%0, %1, %2}" | |
e075ae69 | 11311 | [(set_attr "type" "ishift") |
6ef67412 | 11312 | (set_attr "prefix_0f" "1") |
e075ae69 | 11313 | (set_attr "pent_pair" "np") |
6ef67412 JH |
11314 | (set_attr "ppro_uops" "few") |
11315 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
11316 | |
11317 | (define_expand "x86_shift_adj_3" | |
11318 | [(use (match_operand:SI 0 "register_operand" "")) | |
11319 | (use (match_operand:SI 1 "register_operand" "")) | |
11320 | (use (match_operand:QI 2 "register_operand" ""))] | |
11321 | "" | |
886c62d1 | 11322 | { |
e075ae69 RH |
11323 | rtx label = gen_label_rtx (); |
11324 | rtx tmp; | |
11325 | ||
16189740 | 11326 | emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32))); |
e075ae69 | 11327 | |
16189740 | 11328 | tmp = gen_rtx_REG (CCZmode, FLAGS_REG); |
e075ae69 RH |
11329 | tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); |
11330 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
11331 | gen_rtx_LABEL_REF (VOIDmode, label), | |
11332 | pc_rtx); | |
11333 | tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
11334 | JUMP_LABEL (tmp) = label; | |
11335 | ||
11336 | emit_move_insn (operands[0], operands[1]); | |
11337 | emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31))); | |
11338 | ||
11339 | emit_label (label); | |
11340 | LABEL_NUSES (label) = 1; | |
11341 | ||
11342 | DONE; | |
0f40f9f7 | 11343 | }) |
886c62d1 | 11344 | |
e075ae69 RH |
11345 | (define_insn "ashrsi3_31" |
11346 | [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm") | |
11347 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0") | |
11348 | (match_operand:SI 2 "const_int_operand" "i,i"))) | |
11349 | (clobber (reg:CC 17))] | |
d525dfdf JH |
11350 | "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size) |
11351 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
e075ae69 RH |
11352 | "@ |
11353 | {cltd|cdq} | |
0f40f9f7 | 11354 | sar{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11355 | [(set_attr "type" "imovx,ishift") |
11356 | (set_attr "prefix_0f" "0,*") | |
11357 | (set_attr "length_immediate" "0,*") | |
11358 | (set_attr "modrm" "0,1") | |
11359 | (set_attr "mode" "SI")]) | |
e075ae69 | 11360 | |
371bc54b JH |
11361 | (define_insn "*ashrsi3_31_zext" |
11362 | [(set (match_operand:DI 0 "register_operand" "=*d,r") | |
11363 | (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0") | |
11364 | (match_operand:SI 2 "const_int_operand" "i,i")))) | |
11365 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
11366 | "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size) |
11367 | && INTVAL (operands[2]) == 31 | |
11368 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
371bc54b JH |
11369 | "@ |
11370 | {cltd|cdq} | |
0f40f9f7 | 11371 | sar{l}\t{%2, %k0|%k0, %2}" |
371bc54b JH |
11372 | [(set_attr "type" "imovx,ishift") |
11373 | (set_attr "prefix_0f" "0,*") | |
11374 | (set_attr "length_immediate" "0,*") | |
11375 | (set_attr "modrm" "0,1") | |
11376 | (set_attr "mode" "SI")]) | |
11377 | ||
d525dfdf JH |
11378 | (define_expand "ashrsi3" |
11379 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
155d8a47 | 11380 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") |
d525dfdf JH |
11381 | (match_operand:QI 2 "nonmemory_operand" ""))) |
11382 | (clobber (reg:CC 17))] | |
11383 | "" | |
11384 | "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;") | |
11385 | ||
8bad7136 JL |
11386 | (define_insn "*ashrsi3_1_one_bit" |
11387 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
11388 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
11389 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11390 | (clobber (reg:CC 17))] | |
11391 | "ix86_binary_operator_ok (ASHIFTRT, SImode, operands) | |
11392 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11393 | "sar{l}\t%0" |
8bad7136 JL |
11394 | [(set_attr "type" "ishift") |
11395 | (set (attr "length") | |
11396 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11397 | (const_string "2") | |
11398 | (const_string "*")))]) | |
11399 | ||
371bc54b JH |
11400 | (define_insn "*ashrsi3_1_one_bit_zext" |
11401 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11402 | (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
11403 | (match_operand:QI 2 "const_int_1_operand" "")))) | |
11404 | (clobber (reg:CC 17))] | |
11405 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands) | |
11406 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11407 | "sar{l}\t%k0" |
371bc54b JH |
11408 | [(set_attr "type" "ishift") |
11409 | (set_attr "length" "2")]) | |
11410 | ||
d525dfdf | 11411 | (define_insn "*ashrsi3_1" |
e075ae69 RH |
11412 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") |
11413 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
11414 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11415 | (clobber (reg:CC 17))] | |
d525dfdf | 11416 | "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" |
e075ae69 | 11417 | "@ |
0f40f9f7 ZW |
11418 | sar{l}\t{%2, %0|%0, %2} |
11419 | sar{l}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11420 | [(set_attr "type" "ishift") |
11421 | (set_attr "mode" "SI")]) | |
886c62d1 | 11422 | |
371bc54b JH |
11423 | (define_insn "*ashrsi3_1_zext" |
11424 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
11425 | (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
11426 | (match_operand:QI 2 "nonmemory_operand" "I,c")))) | |
11427 | (clobber (reg:CC 17))] | |
11428 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
11429 | "@ | |
0f40f9f7 ZW |
11430 | sar{l}\t{%2, %k0|%k0, %2} |
11431 | sar{l}\t{%b2, %k0|%k0, %b2}" | |
371bc54b JH |
11432 | [(set_attr "type" "ishift") |
11433 | (set_attr "mode" "SI")]) | |
11434 | ||
8bad7136 JL |
11435 | ;; This pattern can't accept a variable shift count, since shifts by |
11436 | ;; zero don't affect the flags. We assume that shifts by constant | |
11437 | ;; zero are optimized away. | |
2c873473 | 11438 | (define_insn "*ashrsi3_one_bit_cmp" |
8bad7136 JL |
11439 | [(set (reg 17) |
11440 | (compare | |
11441 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
11442 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11443 | (const_int 0))) | |
11444 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
11445 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
2c873473 | 11446 | "ix86_match_ccmode (insn, CCGOCmode) |
8bad7136 JL |
11447 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) |
11448 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
0f40f9f7 | 11449 | "sar{l}\t%0" |
8bad7136 JL |
11450 | [(set_attr "type" "ishift") |
11451 | (set (attr "length") | |
11452 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11453 | (const_string "2") | |
11454 | (const_string "*")))]) | |
11455 | ||
371bc54b JH |
11456 | (define_insn "*ashrsi3_one_bit_cmp_zext" |
11457 | [(set (reg 17) | |
11458 | (compare | |
11459 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
11460 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11461 | (const_int 0))) | |
11462 | (set (match_operand:DI 0 "register_operand" "=r") | |
11463 | (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] | |
11464 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode) | |
11465 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) | |
11466 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
0f40f9f7 | 11467 | "sar{l}\t%k0" |
371bc54b JH |
11468 | [(set_attr "type" "ishift") |
11469 | (set_attr "length" "2")]) | |
11470 | ||
28cefcd2 BS |
11471 | ;; This pattern can't accept a variable shift count, since shifts by |
11472 | ;; zero don't affect the flags. We assume that shifts by constant | |
11473 | ;; zero are optimized away. | |
2c873473 | 11474 | (define_insn "*ashrsi3_cmp" |
16189740 RH |
11475 | [(set (reg 17) |
11476 | (compare | |
28cefcd2 BS |
11477 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
11478 | (match_operand:QI 2 "immediate_operand" "I")) | |
e075ae69 | 11479 | (const_int 0))) |
28cefcd2 | 11480 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
e075ae69 | 11481 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
2c873473 | 11482 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11483 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" |
0f40f9f7 | 11484 | "sar{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11485 | [(set_attr "type" "ishift") |
11486 | (set_attr "mode" "SI")]) | |
886c62d1 | 11487 | |
371bc54b JH |
11488 | (define_insn "*ashrsi3_cmp_zext" |
11489 | [(set (reg 17) | |
11490 | (compare | |
11491 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
11492 | (match_operand:QI 2 "immediate_operand" "I")) | |
11493 | (const_int 0))) | |
11494 | (set (match_operand:DI 0 "register_operand" "=r") | |
11495 | (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] | |
11496 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11497 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
0f40f9f7 | 11498 | "sar{l}\t{%2, %k0|%k0, %2}" |
371bc54b JH |
11499 | [(set_attr "type" "ishift") |
11500 | (set_attr "mode" "SI")]) | |
11501 | ||
d525dfdf JH |
11502 | (define_expand "ashrhi3" |
11503 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
155d8a47 | 11504 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "") |
d525dfdf JH |
11505 | (match_operand:QI 2 "nonmemory_operand" ""))) |
11506 | (clobber (reg:CC 17))] | |
d9f32422 | 11507 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
11508 | "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;") |
11509 | ||
8bad7136 JL |
11510 | (define_insn "*ashrhi3_1_one_bit" |
11511 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
11512 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
11513 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11514 | (clobber (reg:CC 17))] | |
11515 | "ix86_binary_operator_ok (ASHIFTRT, HImode, operands) | |
11516 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11517 | "sar{w}\t%0" |
8bad7136 JL |
11518 | [(set_attr "type" "ishift") |
11519 | (set (attr "length") | |
3d117b30 | 11520 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11521 | (const_string "2") |
11522 | (const_string "*")))]) | |
11523 | ||
d525dfdf | 11524 | (define_insn "*ashrhi3_1" |
e075ae69 RH |
11525 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") |
11526 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
11527 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11528 | (clobber (reg:CC 17))] | |
d525dfdf | 11529 | "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" |
e075ae69 | 11530 | "@ |
0f40f9f7 ZW |
11531 | sar{w}\t{%2, %0|%0, %2} |
11532 | sar{w}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11533 | [(set_attr "type" "ishift") |
11534 | (set_attr "mode" "HI")]) | |
886c62d1 | 11535 | |
8bad7136 JL |
11536 | ;; This pattern can't accept a variable shift count, since shifts by |
11537 | ;; zero don't affect the flags. We assume that shifts by constant | |
11538 | ;; zero are optimized away. | |
2c873473 | 11539 | (define_insn "*ashrhi3_one_bit_cmp" |
8bad7136 JL |
11540 | [(set (reg 17) |
11541 | (compare | |
11542 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
11543 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11544 | (const_int 0))) | |
11545 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
11546 | (ashiftrt:HI (match_dup 1) (match_dup 2)))] | |
2c873473 | 11547 | "ix86_match_ccmode (insn, CCGOCmode) |
8bad7136 JL |
11548 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) |
11549 | && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" | |
0f40f9f7 | 11550 | "sar{w}\t%0" |
8bad7136 JL |
11551 | [(set_attr "type" "ishift") |
11552 | (set (attr "length") | |
3d117b30 | 11553 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11554 | (const_string "2") |
11555 | (const_string "*")))]) | |
11556 | ||
28cefcd2 BS |
11557 | ;; This pattern can't accept a variable shift count, since shifts by |
11558 | ;; zero don't affect the flags. We assume that shifts by constant | |
11559 | ;; zero are optimized away. | |
2c873473 | 11560 | (define_insn "*ashrhi3_cmp" |
16189740 RH |
11561 | [(set (reg 17) |
11562 | (compare | |
28cefcd2 BS |
11563 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
11564 | (match_operand:QI 2 "immediate_operand" "I")) | |
e075ae69 | 11565 | (const_int 0))) |
28cefcd2 | 11566 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
e075ae69 | 11567 | (ashiftrt:HI (match_dup 1) (match_dup 2)))] |
2c873473 | 11568 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11569 | && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" |
0f40f9f7 | 11570 | "sar{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11571 | [(set_attr "type" "ishift") |
11572 | (set_attr "mode" "HI")]) | |
886c62d1 | 11573 | |
d525dfdf JH |
11574 | (define_expand "ashrqi3" |
11575 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
155d8a47 | 11576 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "") |
d525dfdf JH |
11577 | (match_operand:QI 2 "nonmemory_operand" ""))) |
11578 | (clobber (reg:CC 17))] | |
d9f32422 | 11579 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
11580 | "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;") |
11581 | ||
8bad7136 JL |
11582 | (define_insn "*ashrqi3_1_one_bit" |
11583 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
11584 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
11585 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11586 | (clobber (reg:CC 17))] | |
11587 | "ix86_binary_operator_ok (ASHIFTRT, QImode, operands) | |
11588 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11589 | "sar{b}\t%0" |
8bad7136 JL |
11590 | [(set_attr "type" "ishift") |
11591 | (set (attr "length") | |
3d117b30 | 11592 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11593 | (const_string "2") |
11594 | (const_string "*")))]) | |
11595 | ||
d525dfdf | 11596 | (define_insn "*ashrqi3_1" |
e075ae69 RH |
11597 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") |
11598 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
11599 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11600 | (clobber (reg:CC 17))] | |
d525dfdf | 11601 | "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" |
e075ae69 | 11602 | "@ |
0f40f9f7 ZW |
11603 | sar{b}\t{%2, %0|%0, %2} |
11604 | sar{b}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11605 | [(set_attr "type" "ishift") |
11606 | (set_attr "mode" "QI")]) | |
886c62d1 | 11607 | |
8bad7136 JL |
11608 | ;; This pattern can't accept a variable shift count, since shifts by |
11609 | ;; zero don't affect the flags. We assume that shifts by constant | |
11610 | ;; zero are optimized away. | |
2c873473 | 11611 | (define_insn "*ashrqi3_one_bit_cmp" |
8bad7136 JL |
11612 | [(set (reg 17) |
11613 | (compare | |
11614 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
11615 | (match_operand:QI 2 "const_int_1_operand" "I")) | |
11616 | (const_int 0))) | |
11617 | (set (match_operand:QI 0 "nonimmediate_operand" "=rm") | |
11618 | (ashiftrt:QI (match_dup 1) (match_dup 2)))] | |
2c873473 | 11619 | "ix86_match_ccmode (insn, CCGOCmode) |
8bad7136 JL |
11620 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) |
11621 | && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" | |
0f40f9f7 | 11622 | "sar{b}\t%0" |
8bad7136 JL |
11623 | [(set_attr "type" "ishift") |
11624 | (set (attr "length") | |
3d117b30 | 11625 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11626 | (const_string "2") |
11627 | (const_string "*")))]) | |
11628 | ||
28cefcd2 BS |
11629 | ;; This pattern can't accept a variable shift count, since shifts by |
11630 | ;; zero don't affect the flags. We assume that shifts by constant | |
11631 | ;; zero are optimized away. | |
2c873473 | 11632 | (define_insn "*ashrqi3_cmp" |
16189740 RH |
11633 | [(set (reg 17) |
11634 | (compare | |
28cefcd2 BS |
11635 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
11636 | (match_operand:QI 2 "immediate_operand" "I")) | |
e075ae69 | 11637 | (const_int 0))) |
28cefcd2 | 11638 | (set (match_operand:QI 0 "nonimmediate_operand" "=rm") |
e075ae69 | 11639 | (ashiftrt:QI (match_dup 1) (match_dup 2)))] |
2c873473 | 11640 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11641 | && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" |
0f40f9f7 | 11642 | "sar{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11643 | [(set_attr "type" "ishift") |
11644 | (set_attr "mode" "QI")]) | |
886c62d1 | 11645 | \f |
e075ae69 RH |
11646 | ;; Logical shift instructions |
11647 | ||
11648 | ;; See comment above `ashldi3' about how this works. | |
11649 | ||
11650 | (define_expand "lshrdi3" | |
371bc54b JH |
11651 | [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") |
11652 | (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") | |
11653 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
e075ae69 | 11654 | (clobber (reg:CC 17))])] |
886c62d1 | 11655 | "" |
886c62d1 | 11656 | { |
371bc54b | 11657 | if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) |
886c62d1 | 11658 | { |
e075ae69 RH |
11659 | emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2])); |
11660 | DONE; | |
886c62d1 | 11661 | } |
371bc54b JH |
11662 | ix86_expand_binary_operator (LSHIFTRT, DImode, operands); |
11663 | DONE; | |
0f40f9f7 | 11664 | }) |
886c62d1 | 11665 | |
371bc54b JH |
11666 | (define_insn "*lshrdi3_1_one_bit_rex64" |
11667 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11668 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11669 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11670 | (clobber (reg:CC 17))] | |
11671 | "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) | |
11672 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11673 | "shr{q}\t%0" |
371bc54b JH |
11674 | [(set_attr "type" "ishift") |
11675 | (set (attr "length") | |
11676 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
11677 | (const_string "2") | |
11678 | (const_string "*")))]) | |
11679 | ||
11680 | (define_insn "*lshrdi3_1_rex64" | |
11681 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") | |
11682 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
11683 | (match_operand:QI 2 "nonmemory_operand" "J,c"))) | |
11684 | (clobber (reg:CC 17))] | |
11685 | "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
11686 | "@ | |
0f40f9f7 ZW |
11687 | shr{q}\t{%2, %0|%0, %2} |
11688 | shr{q}\t{%b2, %0|%0, %b2}" | |
371bc54b JH |
11689 | [(set_attr "type" "ishift") |
11690 | (set_attr "mode" "DI")]) | |
11691 | ||
11692 | ;; This pattern can't accept a variable shift count, since shifts by | |
11693 | ;; zero don't affect the flags. We assume that shifts by constant | |
11694 | ;; zero are optimized away. | |
11695 | (define_insn "*lshrdi3_cmp_one_bit_rex64" | |
11696 | [(set (reg 17) | |
11697 | (compare | |
11698 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11699 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11700 | (const_int 0))) | |
11701 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11702 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
11703 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11704 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) | |
11705 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
0f40f9f7 | 11706 | "shr{q}\t%0" |
371bc54b JH |
11707 | [(set_attr "type" "ishift") |
11708 | (set (attr "length") | |
11709 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
11710 | (const_string "2") | |
11711 | (const_string "*")))]) | |
11712 | ||
11713 | ;; This pattern can't accept a variable shift count, since shifts by | |
11714 | ;; zero don't affect the flags. We assume that shifts by constant | |
11715 | ;; zero are optimized away. | |
11716 | (define_insn "*lshrdi3_cmp_rex64" | |
11717 | [(set (reg 17) | |
11718 | (compare | |
11719 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11720 | (match_operand:QI 2 "const_int_operand" "e")) | |
11721 | (const_int 0))) | |
11722 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11723 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
11724 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11725 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
0f40f9f7 | 11726 | "shr{q}\t{%2, %0|%0, %2}" |
371bc54b JH |
11727 | [(set_attr "type" "ishift") |
11728 | (set_attr "mode" "DI")]) | |
11729 | ||
e075ae69 RH |
11730 | (define_insn "lshrdi3_1" |
11731 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11732 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
11733 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) | |
11734 | (clobber (match_scratch:SI 3 "=&r")) | |
11735 | (clobber (reg:CC 17))] | |
1e07edd3 | 11736 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 RH |
11737 | "#" |
11738 | [(set_attr "type" "multi")]) | |
886c62d1 | 11739 | |
e075ae69 RH |
11740 | (define_insn "*lshrdi3_2" |
11741 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11742 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
11743 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) | |
11744 | (clobber (reg:CC 17))] | |
1e07edd3 | 11745 | "!TARGET_64BIT" |
e075ae69 RH |
11746 | "#" |
11747 | [(set_attr "type" "multi")]) | |
886c62d1 | 11748 | |
e075ae69 RH |
11749 | (define_split |
11750 | [(set (match_operand:DI 0 "register_operand" "") | |
11751 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
11752 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11753 | (clobber (match_scratch:SI 3 "")) | |
11754 | (clobber (reg:CC 17))] | |
1e07edd3 | 11755 | "!TARGET_64BIT && TARGET_CMOVE && reload_completed" |
e075ae69 RH |
11756 | [(const_int 0)] |
11757 | "ix86_split_lshrdi (operands, operands[3]); DONE;") | |
886c62d1 | 11758 | |
e075ae69 RH |
11759 | (define_split |
11760 | [(set (match_operand:DI 0 "register_operand" "") | |
11761 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
11762 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11763 | (clobber (reg:CC 17))] | |
1e07edd3 | 11764 | "!TARGET_64BIT && reload_completed" |
e075ae69 RH |
11765 | [(const_int 0)] |
11766 | "ix86_split_lshrdi (operands, NULL_RTX); DONE;") | |
886c62d1 | 11767 | |
d525dfdf JH |
11768 | (define_expand "lshrsi3" |
11769 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
11770 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
11771 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11772 | (clobber (reg:CC 17))] | |
11773 | "" | |
11774 | "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;") | |
11775 | ||
8bad7136 JL |
11776 | (define_insn "*lshrsi3_1_one_bit" |
11777 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
11778 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
11779 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11780 | (clobber (reg:CC 17))] | |
11781 | "ix86_binary_operator_ok (LSHIFTRT, HImode, operands) | |
11782 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11783 | "shr{l}\t%0" |
8bad7136 JL |
11784 | [(set_attr "type" "ishift") |
11785 | (set (attr "length") | |
11786 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11787 | (const_string "2") | |
11788 | (const_string "*")))]) | |
11789 | ||
371bc54b JH |
11790 | (define_insn "*lshrsi3_1_one_bit_zext" |
11791 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11792 | (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0")) | |
11793 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11794 | (clobber (reg:CC 17))] | |
11795 | "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) | |
11796 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11797 | "shr{l}\t%k0" |
371bc54b JH |
11798 | [(set_attr "type" "ishift") |
11799 | (set_attr "length" "2")]) | |
11800 | ||
d525dfdf | 11801 | (define_insn "*lshrsi3_1" |
e075ae69 RH |
11802 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") |
11803 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
11804 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11805 | (clobber (reg:CC 17))] | |
d525dfdf | 11806 | "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
e075ae69 | 11807 | "@ |
0f40f9f7 ZW |
11808 | shr{l}\t{%2, %0|%0, %2} |
11809 | shr{l}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11810 | [(set_attr "type" "ishift") |
11811 | (set_attr "mode" "SI")]) | |
886c62d1 | 11812 | |
371bc54b JH |
11813 | (define_insn "*lshrsi3_1_zext" |
11814 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
11815 | (zero_extend:DI | |
11816 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
11817 | (match_operand:QI 2 "nonmemory_operand" "I,c")))) | |
11818 | (clobber (reg:CC 17))] | |
11819 | "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
11820 | "@ | |
0f40f9f7 ZW |
11821 | shr{l}\t{%2, %k0|%k0, %2} |
11822 | shr{l}\t{%b2, %k0|%k0, %b2}" | |
371bc54b JH |
11823 | [(set_attr "type" "ishift") |
11824 | (set_attr "mode" "SI")]) | |
11825 | ||
8bad7136 JL |
11826 | ;; This pattern can't accept a variable shift count, since shifts by |
11827 | ;; zero don't affect the flags. We assume that shifts by constant | |
11828 | ;; zero are optimized away. | |
2c873473 | 11829 | (define_insn "*lshrsi3_one_bit_cmp" |
8bad7136 JL |
11830 | [(set (reg 17) |
11831 | (compare | |
11832 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
11833 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11834 | (const_int 0))) | |
11835 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
11836 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 11837 | "ix86_match_ccmode (insn, CCGOCmode) |
8bad7136 JL |
11838 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) |
11839 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
0f40f9f7 | 11840 | "shr{l}\t%0" |
8bad7136 JL |
11841 | [(set_attr "type" "ishift") |
11842 | (set (attr "length") | |
11843 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11844 | (const_string "2") | |
11845 | (const_string "*")))]) | |
11846 | ||
371bc54b JH |
11847 | (define_insn "*lshrsi3_cmp_one_bit_zext" |
11848 | [(set (reg 17) | |
11849 | (compare | |
11850 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
11851 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11852 | (const_int 0))) | |
11853 | (set (match_operand:DI 0 "register_operand" "=r") | |
11854 | (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] | |
11855 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11856 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) | |
11857 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
0f40f9f7 | 11858 | "shr{l}\t%k0" |
371bc54b JH |
11859 | [(set_attr "type" "ishift") |
11860 | (set_attr "length" "2")]) | |
11861 | ||
28cefcd2 BS |
11862 | ;; This pattern can't accept a variable shift count, since shifts by |
11863 | ;; zero don't affect the flags. We assume that shifts by constant | |
11864 | ;; zero are optimized away. | |
2c873473 | 11865 | (define_insn "*lshrsi3_cmp" |
16189740 RH |
11866 | [(set (reg 17) |
11867 | (compare | |
28cefcd2 BS |
11868 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
11869 | (match_operand:QI 2 "immediate_operand" "I")) | |
e075ae69 | 11870 | (const_int 0))) |
28cefcd2 | 11871 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
e075ae69 | 11872 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
9076b9c1 | 11873 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11874 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
0f40f9f7 | 11875 | "shr{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11876 | [(set_attr "type" "ishift") |
11877 | (set_attr "mode" "SI")]) | |
886c62d1 | 11878 | |
371bc54b JH |
11879 | (define_insn "*lshrsi3_cmp_zext" |
11880 | [(set (reg 17) | |
11881 | (compare | |
11882 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
11883 | (match_operand:QI 2 "immediate_operand" "I")) | |
11884 | (const_int 0))) | |
11885 | (set (match_operand:DI 0 "register_operand" "=r") | |
11886 | (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] | |
11887 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11888 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
0f40f9f7 | 11889 | "shr{l}\t{%2, %k0|%k0, %2}" |
371bc54b JH |
11890 | [(set_attr "type" "ishift") |
11891 | (set_attr "mode" "SI")]) | |
11892 | ||
d525dfdf JH |
11893 | (define_expand "lshrhi3" |
11894 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
11895 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
11896 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11897 | (clobber (reg:CC 17))] | |
d9f32422 | 11898 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
11899 | "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;") |
11900 | ||
8bad7136 JL |
11901 | (define_insn "*lshrhi3_1_one_bit" |
11902 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
11903 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
11904 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11905 | (clobber (reg:CC 17))] | |
11906 | "ix86_binary_operator_ok (LSHIFTRT, HImode, operands) | |
11907 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11908 | "shr{w}\t%0" |
8bad7136 JL |
11909 | [(set_attr "type" "ishift") |
11910 | (set (attr "length") | |
3d117b30 | 11911 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11912 | (const_string "2") |
11913 | (const_string "*")))]) | |
11914 | ||
d525dfdf | 11915 | (define_insn "*lshrhi3_1" |
e075ae69 RH |
11916 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") |
11917 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
11918 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11919 | (clobber (reg:CC 17))] | |
d525dfdf | 11920 | "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
e075ae69 | 11921 | "@ |
0f40f9f7 ZW |
11922 | shr{w}\t{%2, %0|%0, %2} |
11923 | shr{w}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11924 | [(set_attr "type" "ishift") |
11925 | (set_attr "mode" "HI")]) | |
886c62d1 | 11926 | |
8bad7136 JL |
11927 | ;; This pattern can't accept a variable shift count, since shifts by |
11928 | ;; zero don't affect the flags. We assume that shifts by constant | |
11929 | ;; zero are optimized away. | |
2c873473 | 11930 | (define_insn "*lshrhi3_one_bit_cmp" |
8bad7136 JL |
11931 | [(set (reg 17) |
11932 | (compare | |
11933 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
11934 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11935 | (const_int 0))) | |
11936 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
11937 | (lshiftrt:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 11938 | "ix86_match_ccmode (insn, CCGOCmode) |
8bad7136 JL |
11939 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) |
11940 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
0f40f9f7 | 11941 | "shr{w}\t%0" |
8bad7136 JL |
11942 | [(set_attr "type" "ishift") |
11943 | (set (attr "length") | |
11944 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11945 | (const_string "2") | |
11946 | (const_string "*")))]) | |
11947 | ||
28cefcd2 BS |
11948 | ;; This pattern can't accept a variable shift count, since shifts by |
11949 | ;; zero don't affect the flags. We assume that shifts by constant | |
11950 | ;; zero are optimized away. | |
2c873473 | 11951 | (define_insn "*lshrhi3_cmp" |
16189740 RH |
11952 | [(set (reg 17) |
11953 | (compare | |
28cefcd2 BS |
11954 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
11955 | (match_operand:QI 2 "immediate_operand" "I")) | |
e075ae69 | 11956 | (const_int 0))) |
28cefcd2 | 11957 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
e075ae69 | 11958 | (lshiftrt:HI (match_dup 1) (match_dup 2)))] |
9076b9c1 | 11959 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11960 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
0f40f9f7 | 11961 | "shr{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11962 | [(set_attr "type" "ishift") |
11963 | (set_attr "mode" "HI")]) | |
886c62d1 | 11964 | |
d525dfdf JH |
11965 | (define_expand "lshrqi3" |
11966 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
11967 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
11968 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11969 | (clobber (reg:CC 17))] | |
d9f32422 | 11970 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
11971 | "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;") |
11972 | ||
8bad7136 JL |
11973 | (define_insn "*lshrqi3_1_one_bit" |
11974 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
11975 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
11976 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11977 | (clobber (reg:CC 17))] | |
11978 | "ix86_binary_operator_ok (LSHIFTRT, QImode, operands) | |
11979 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 11980 | "shr{b}\t%0" |
8bad7136 JL |
11981 | [(set_attr "type" "ishift") |
11982 | (set (attr "length") | |
3d117b30 | 11983 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11984 | (const_string "2") |
11985 | (const_string "*")))]) | |
11986 | ||
d525dfdf | 11987 | (define_insn "*lshrqi3_1" |
e075ae69 RH |
11988 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") |
11989 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
11990 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11991 | (clobber (reg:CC 17))] | |
d525dfdf | 11992 | "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" |
e075ae69 | 11993 | "@ |
0f40f9f7 ZW |
11994 | shr{b}\t{%2, %0|%0, %2} |
11995 | shr{b}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11996 | [(set_attr "type" "ishift") |
11997 | (set_attr "mode" "QI")]) | |
886c62d1 | 11998 | |
8bad7136 JL |
11999 | ;; This pattern can't accept a variable shift count, since shifts by |
12000 | ;; zero don't affect the flags. We assume that shifts by constant | |
12001 | ;; zero are optimized away. | |
2c873473 | 12002 | (define_insn "*lshrqi2_one_bit_cmp" |
8bad7136 JL |
12003 | [(set (reg 17) |
12004 | (compare | |
12005 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
12006 | (match_operand:QI 2 "const_int_1_operand" "")) | |
12007 | (const_int 0))) | |
12008 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
12009 | (lshiftrt:QI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 12010 | "ix86_match_ccmode (insn, CCGOCmode) |
8bad7136 JL |
12011 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO) |
12012 | && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" | |
0f40f9f7 | 12013 | "shr{b}\t%0" |
8bad7136 JL |
12014 | [(set_attr "type" "ishift") |
12015 | (set (attr "length") | |
12016 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
12017 | (const_string "2") | |
12018 | (const_string "*")))]) | |
12019 | ||
28cefcd2 BS |
12020 | ;; This pattern can't accept a variable shift count, since shifts by |
12021 | ;; zero don't affect the flags. We assume that shifts by constant | |
12022 | ;; zero are optimized away. | |
2c873473 | 12023 | (define_insn "*lshrqi2_cmp" |
16189740 RH |
12024 | [(set (reg 17) |
12025 | (compare | |
28cefcd2 BS |
12026 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
12027 | (match_operand:QI 2 "immediate_operand" "I")) | |
e075ae69 | 12028 | (const_int 0))) |
122ddbf9 | 12029 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
e075ae69 | 12030 | (lshiftrt:QI (match_dup 1) (match_dup 2)))] |
9076b9c1 | 12031 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 12032 | && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" |
0f40f9f7 | 12033 | "shr{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
12034 | [(set_attr "type" "ishift") |
12035 | (set_attr "mode" "QI")]) | |
886c62d1 | 12036 | \f |
e075ae69 | 12037 | ;; Rotate instructions |
886c62d1 | 12038 | |
371bc54b JH |
12039 | (define_expand "rotldi3" |
12040 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
12041 | (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
12042 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12043 | (clobber (reg:CC 17))] | |
12044 | "TARGET_64BIT" | |
12045 | "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;") | |
12046 | ||
12047 | (define_insn "*rotlsi3_1_one_bit_rex64" | |
12048 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
12049 | (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
12050 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12051 | (clobber (reg:CC 17))] | |
12052 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands) | |
12053 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12054 | "rol{q}\t%0" |
371bc54b JH |
12055 | [(set_attr "type" "ishift") |
12056 | (set (attr "length") | |
12057 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
12058 | (const_string "2") | |
12059 | (const_string "*")))]) | |
12060 | ||
12061 | (define_insn "*rotldi3_1_rex64" | |
12062 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") | |
12063 | (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
12064 | (match_operand:QI 2 "nonmemory_operand" "e,c"))) | |
12065 | (clobber (reg:CC 17))] | |
12066 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)" | |
12067 | "@ | |
0f40f9f7 ZW |
12068 | rol{q}\t{%2, %0|%0, %2} |
12069 | rol{q}\t{%b2, %0|%0, %b2}" | |
371bc54b JH |
12070 | [(set_attr "type" "ishift") |
12071 | (set_attr "mode" "DI")]) | |
12072 | ||
d525dfdf JH |
12073 | (define_expand "rotlsi3" |
12074 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
12075 | (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
12076 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12077 | (clobber (reg:CC 17))] | |
12078 | "" | |
12079 | "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;") | |
12080 | ||
8bad7136 JL |
12081 | (define_insn "*rotlsi3_1_one_bit" |
12082 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
12083 | (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
12084 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12085 | (clobber (reg:CC 17))] | |
12086 | "ix86_binary_operator_ok (ROTATE, SImode, operands) | |
12087 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12088 | "rol{l}\t%0" |
8bad7136 JL |
12089 | [(set_attr "type" "ishift") |
12090 | (set (attr "length") | |
12091 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
12092 | (const_string "2") | |
12093 | (const_string "*")))]) | |
12094 | ||
371bc54b JH |
12095 | (define_insn "*rotlsi3_1_one_bit_zext" |
12096 | [(set (match_operand:DI 0 "register_operand" "=r") | |
12097 | (zero_extend:DI | |
12098 | (rotate:SI (match_operand:SI 1 "register_operand" "0") | |
12099 | (match_operand:QI 2 "const_int_1_operand" "")))) | |
12100 | (clobber (reg:CC 17))] | |
12101 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands) | |
12102 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12103 | "rol{l}\t%k0" |
371bc54b JH |
12104 | [(set_attr "type" "ishift") |
12105 | (set_attr "length" "2")]) | |
12106 | ||
d525dfdf | 12107 | (define_insn "*rotlsi3_1" |
e075ae69 RH |
12108 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") |
12109 | (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
12110 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12111 | (clobber (reg:CC 17))] | |
d525dfdf | 12112 | "ix86_binary_operator_ok (ROTATE, SImode, operands)" |
e075ae69 | 12113 | "@ |
0f40f9f7 ZW |
12114 | rol{l}\t{%2, %0|%0, %2} |
12115 | rol{l}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
12116 | [(set_attr "type" "ishift") |
12117 | (set_attr "mode" "SI")]) | |
b4ac57ab | 12118 | |
371bc54b JH |
12119 | (define_insn "*rotlsi3_1_zext" |
12120 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
12121 | (zero_extend:DI | |
12122 | (rotate:SI (match_operand:SI 1 "register_operand" "0,0") | |
12123 | (match_operand:QI 2 "nonmemory_operand" "I,c")))) | |
12124 | (clobber (reg:CC 17))] | |
12125 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)" | |
12126 | "@ | |
0f40f9f7 ZW |
12127 | rol{l}\t{%2, %k0|%k0, %2} |
12128 | rol{l}\t{%b2, %k0|%k0, %b2}" | |
371bc54b JH |
12129 | [(set_attr "type" "ishift") |
12130 | (set_attr "mode" "SI")]) | |
12131 | ||
d525dfdf JH |
12132 | (define_expand "rotlhi3" |
12133 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
12134 | (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
12135 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12136 | (clobber (reg:CC 17))] | |
d9f32422 | 12137 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
12138 | "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;") |
12139 | ||
8bad7136 JL |
12140 | (define_insn "*rotlhi3_1_one_bit" |
12141 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
12142 | (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
12143 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12144 | (clobber (reg:CC 17))] | |
12145 | "ix86_binary_operator_ok (ROTATE, HImode, operands) | |
12146 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12147 | "rol{w}\t%0" |
8bad7136 JL |
12148 | [(set_attr "type" "ishift") |
12149 | (set (attr "length") | |
3d117b30 | 12150 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
12151 | (const_string "2") |
12152 | (const_string "*")))]) | |
12153 | ||
d525dfdf | 12154 | (define_insn "*rotlhi3_1" |
e075ae69 RH |
12155 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") |
12156 | (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
12157 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12158 | (clobber (reg:CC 17))] | |
d525dfdf | 12159 | "ix86_binary_operator_ok (ROTATE, HImode, operands)" |
e075ae69 | 12160 | "@ |
0f40f9f7 ZW |
12161 | rol{w}\t{%2, %0|%0, %2} |
12162 | rol{w}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
12163 | [(set_attr "type" "ishift") |
12164 | (set_attr "mode" "HI")]) | |
47af5d50 | 12165 | |
d525dfdf JH |
12166 | (define_expand "rotlqi3" |
12167 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
12168 | (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
12169 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12170 | (clobber (reg:CC 17))] | |
d9f32422 | 12171 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
12172 | "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;") |
12173 | ||
8bad7136 JL |
12174 | (define_insn "*rotlqi3_1_one_bit" |
12175 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
12176 | (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
12177 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12178 | (clobber (reg:CC 17))] | |
12179 | "ix86_binary_operator_ok (ROTATE, QImode, operands) | |
12180 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12181 | "rol{b}\t%0" |
8bad7136 JL |
12182 | [(set_attr "type" "ishift") |
12183 | (set (attr "length") | |
3d117b30 | 12184 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
12185 | (const_string "2") |
12186 | (const_string "*")))]) | |
12187 | ||
d525dfdf | 12188 | (define_insn "*rotlqi3_1" |
e075ae69 RH |
12189 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") |
12190 | (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
12191 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12192 | (clobber (reg:CC 17))] | |
d525dfdf | 12193 | "ix86_binary_operator_ok (ROTATE, QImode, operands)" |
e075ae69 | 12194 | "@ |
0f40f9f7 ZW |
12195 | rol{b}\t{%2, %0|%0, %2} |
12196 | rol{b}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
12197 | [(set_attr "type" "ishift") |
12198 | (set_attr "mode" "QI")]) | |
47af5d50 | 12199 | |
371bc54b JH |
12200 | (define_expand "rotrdi3" |
12201 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
12202 | (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
12203 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12204 | (clobber (reg:CC 17))] | |
12205 | "TARGET_64BIT" | |
12206 | "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;") | |
12207 | ||
12208 | (define_insn "*rotrdi3_1_one_bit_rex64" | |
12209 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
12210 | (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
12211 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12212 | (clobber (reg:CC 17))] | |
12213 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands) | |
12214 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12215 | "ror{q}\t%0" |
371bc54b JH |
12216 | [(set_attr "type" "ishift") |
12217 | (set (attr "length") | |
12218 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
12219 | (const_string "2") | |
12220 | (const_string "*")))]) | |
12221 | ||
12222 | (define_insn "*rotrdi3_1_rex64" | |
12223 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") | |
12224 | (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
12225 | (match_operand:QI 2 "nonmemory_operand" "J,c"))) | |
12226 | (clobber (reg:CC 17))] | |
12227 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)" | |
12228 | "@ | |
0f40f9f7 ZW |
12229 | ror{q}\t{%2, %0|%0, %2} |
12230 | ror{q}\t{%b2, %0|%0, %b2}" | |
371bc54b JH |
12231 | [(set_attr "type" "ishift") |
12232 | (set_attr "mode" "DI")]) | |
12233 | ||
d525dfdf JH |
12234 | (define_expand "rotrsi3" |
12235 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
12236 | (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
12237 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12238 | (clobber (reg:CC 17))] | |
12239 | "" | |
12240 | "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;") | |
12241 | ||
8bad7136 JL |
12242 | (define_insn "*rotrsi3_1_one_bit" |
12243 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
12244 | (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
12245 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12246 | (clobber (reg:CC 17))] | |
12247 | "ix86_binary_operator_ok (ROTATERT, SImode, operands) | |
12248 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12249 | "ror{l}\t%0" |
8bad7136 JL |
12250 | [(set_attr "type" "ishift") |
12251 | (set (attr "length") | |
12252 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
12253 | (const_string "2") | |
12254 | (const_string "*")))]) | |
12255 | ||
371bc54b JH |
12256 | (define_insn "*rotrsi3_1_one_bit_zext" |
12257 | [(set (match_operand:DI 0 "register_operand" "=r") | |
12258 | (zero_extend:DI | |
12259 | (rotatert:SI (match_operand:SI 1 "register_operand" "0") | |
12260 | (match_operand:QI 2 "const_int_1_operand" "")))) | |
12261 | (clobber (reg:CC 17))] | |
12262 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands) | |
12263 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12264 | "ror{l}\t%k0" |
371bc54b JH |
12265 | [(set_attr "type" "ishift") |
12266 | (set (attr "length") | |
12267 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
12268 | (const_string "2") | |
12269 | (const_string "*")))]) | |
12270 | ||
d525dfdf | 12271 | (define_insn "*rotrsi3_1" |
e075ae69 RH |
12272 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") |
12273 | (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
12274 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12275 | (clobber (reg:CC 17))] | |
d525dfdf | 12276 | "ix86_binary_operator_ok (ROTATERT, SImode, operands)" |
e075ae69 | 12277 | "@ |
0f40f9f7 ZW |
12278 | ror{l}\t{%2, %0|%0, %2} |
12279 | ror{l}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
12280 | [(set_attr "type" "ishift") |
12281 | (set_attr "mode" "SI")]) | |
47af5d50 | 12282 | |
371bc54b JH |
12283 | (define_insn "*rotrsi3_1_zext" |
12284 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
12285 | (zero_extend:DI | |
12286 | (rotatert:SI (match_operand:SI 1 "register_operand" "0,0") | |
12287 | (match_operand:QI 2 "nonmemory_operand" "I,c")))) | |
12288 | (clobber (reg:CC 17))] | |
12289 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)" | |
12290 | "@ | |
0f40f9f7 ZW |
12291 | ror{l}\t{%2, %k0|%k0, %2} |
12292 | ror{l}\t{%b2, %k0|%k0, %b2}" | |
371bc54b JH |
12293 | [(set_attr "type" "ishift") |
12294 | (set_attr "mode" "SI")]) | |
12295 | ||
d525dfdf JH |
12296 | (define_expand "rotrhi3" |
12297 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
12298 | (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
12299 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12300 | (clobber (reg:CC 17))] | |
d9f32422 | 12301 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
12302 | "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;") |
12303 | ||
8bad7136 JL |
12304 | (define_insn "*rotrhi3_one_bit" |
12305 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
12306 | (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
12307 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12308 | (clobber (reg:CC 17))] | |
12309 | "ix86_binary_operator_ok (ROTATERT, HImode, operands) | |
12310 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12311 | "ror{w}\t%0" |
8bad7136 JL |
12312 | [(set_attr "type" "ishift") |
12313 | (set (attr "length") | |
3d117b30 | 12314 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
12315 | (const_string "2") |
12316 | (const_string "*")))]) | |
12317 | ||
d525dfdf | 12318 | (define_insn "*rotrhi3" |
e075ae69 RH |
12319 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") |
12320 | (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
12321 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12322 | (clobber (reg:CC 17))] | |
d525dfdf | 12323 | "ix86_binary_operator_ok (ROTATERT, HImode, operands)" |
e075ae69 | 12324 | "@ |
0f40f9f7 ZW |
12325 | ror{w}\t{%2, %0|%0, %2} |
12326 | ror{w}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
12327 | [(set_attr "type" "ishift") |
12328 | (set_attr "mode" "HI")]) | |
a199fdd6 | 12329 | |
d525dfdf JH |
12330 | (define_expand "rotrqi3" |
12331 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
12332 | (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
12333 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12334 | (clobber (reg:CC 17))] | |
d9f32422 | 12335 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
12336 | "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;") |
12337 | ||
8bad7136 JL |
12338 | (define_insn "*rotrqi3_1_one_bit" |
12339 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
12340 | (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
12341 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12342 | (clobber (reg:CC 17))] | |
12343 | "ix86_binary_operator_ok (ROTATERT, QImode, operands) | |
12344 | && (TARGET_PENTIUM || TARGET_PENTIUMPRO)" | |
0f40f9f7 | 12345 | "ror{b}\t%0" |
8bad7136 JL |
12346 | [(set_attr "type" "ishift") |
12347 | (set (attr "length") | |
3d117b30 | 12348 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
12349 | (const_string "2") |
12350 | (const_string "*")))]) | |
12351 | ||
d525dfdf | 12352 | (define_insn "*rotrqi3_1" |
e075ae69 RH |
12353 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") |
12354 | (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
12355 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12356 | (clobber (reg:CC 17))] | |
d525dfdf | 12357 | "ix86_binary_operator_ok (ROTATERT, QImode, operands)" |
e075ae69 | 12358 | "@ |
0f40f9f7 ZW |
12359 | ror{b}\t{%2, %0|%0, %2} |
12360 | ror{b}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
12361 | [(set_attr "type" "ishift") |
12362 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
12363 | \f |
12364 | ;; Bit set / bit test instructions | |
a199fdd6 | 12365 | |
e075ae69 RH |
12366 | (define_expand "extv" |
12367 | [(set (match_operand:SI 0 "register_operand" "") | |
12368 | (sign_extract:SI (match_operand:SI 1 "register_operand" "") | |
12369 | (match_operand:SI 2 "immediate_operand" "") | |
12370 | (match_operand:SI 3 "immediate_operand" "")))] | |
12371 | "" | |
e075ae69 RH |
12372 | { |
12373 | /* Handle extractions from %ah et al. */ | |
12374 | if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) | |
12375 | FAIL; | |
a199fdd6 | 12376 | |
e075ae69 RH |
12377 | /* From mips.md: extract_bit_field doesn't verify that our source |
12378 | matches the predicate, so check it again here. */ | |
12379 | if (! register_operand (operands[1], VOIDmode)) | |
12380 | FAIL; | |
0f40f9f7 | 12381 | }) |
a199fdd6 | 12382 | |
e075ae69 RH |
12383 | (define_expand "extzv" |
12384 | [(set (match_operand:SI 0 "register_operand" "") | |
12385 | (zero_extract:SI (match_operand 1 "ext_register_operand" "") | |
12386 | (match_operand:SI 2 "immediate_operand" "") | |
12387 | (match_operand:SI 3 "immediate_operand" "")))] | |
12388 | "" | |
e075ae69 RH |
12389 | { |
12390 | /* Handle extractions from %ah et al. */ | |
12391 | if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) | |
12392 | FAIL; | |
a199fdd6 | 12393 | |
e075ae69 RH |
12394 | /* From mips.md: extract_bit_field doesn't verify that our source |
12395 | matches the predicate, so check it again here. */ | |
12396 | if (! register_operand (operands[1], VOIDmode)) | |
12397 | FAIL; | |
0f40f9f7 | 12398 | }) |
a199fdd6 | 12399 | |
e075ae69 RH |
12400 | (define_expand "insv" |
12401 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "") | |
12402 | (match_operand:SI 1 "immediate_operand" "") | |
12403 | (match_operand:SI 2 "immediate_operand" "")) | |
12404 | (match_operand:SI 3 "register_operand" ""))] | |
12405 | "" | |
e075ae69 RH |
12406 | { |
12407 | /* Handle extractions from %ah et al. */ | |
12408 | if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8) | |
12409 | FAIL; | |
a199fdd6 | 12410 | |
e075ae69 RH |
12411 | /* From mips.md: insert_bit_field doesn't verify that our source |
12412 | matches the predicate, so check it again here. */ | |
12413 | if (! register_operand (operands[0], VOIDmode)) | |
12414 | FAIL; | |
0f40f9f7 | 12415 | }) |
e075ae69 RH |
12416 | |
12417 | ;; %%% bts, btr, btc, bt. | |
886c62d1 JVA |
12418 | \f |
12419 | ;; Store-flag instructions. | |
12420 | ||
c572e5ba JVA |
12421 | ;; For all sCOND expanders, also expand the compare or test insn that |
12422 | ;; generates cc0. Generate an equality comparison if `seq' or `sne'. | |
12423 | ||
e075ae69 RH |
12424 | ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way |
12425 | ;; to avoid partial register stalls. Otherwise do things the setcc+movzx | |
12426 | ;; way, which can later delete the movzx if only QImode is needed. | |
12427 | ||
c572e5ba | 12428 | (define_expand "seq" |
b932f770 JH |
12429 | [(set (match_operand:QI 0 "register_operand" "") |
12430 | (eq:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12431 | "" |
3a3677ff | 12432 | "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;") |
c572e5ba | 12433 | |
c572e5ba | 12434 | (define_expand "sne" |
b932f770 JH |
12435 | [(set (match_operand:QI 0 "register_operand" "") |
12436 | (ne:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12437 | "" |
3a3677ff | 12438 | "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;") |
c572e5ba | 12439 | |
c572e5ba | 12440 | (define_expand "sgt" |
b932f770 JH |
12441 | [(set (match_operand:QI 0 "register_operand" "") |
12442 | (gt:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12443 | "" |
3a3677ff | 12444 | "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;") |
c572e5ba | 12445 | |
c572e5ba | 12446 | (define_expand "sgtu" |
b932f770 JH |
12447 | [(set (match_operand:QI 0 "register_operand" "") |
12448 | (gtu:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12449 | "" |
3a3677ff | 12450 | "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;") |
c572e5ba | 12451 | |
c572e5ba | 12452 | (define_expand "slt" |
b932f770 JH |
12453 | [(set (match_operand:QI 0 "register_operand" "") |
12454 | (lt:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12455 | "" |
3a3677ff | 12456 | "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;") |
c572e5ba | 12457 | |
c572e5ba | 12458 | (define_expand "sltu" |
b932f770 JH |
12459 | [(set (match_operand:QI 0 "register_operand" "") |
12460 | (ltu:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12461 | "" |
3a3677ff | 12462 | "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;") |
c572e5ba | 12463 | |
c572e5ba | 12464 | (define_expand "sge" |
b932f770 JH |
12465 | [(set (match_operand:QI 0 "register_operand" "") |
12466 | (ge:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12467 | "" |
3a3677ff | 12468 | "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;") |
c572e5ba | 12469 | |
c572e5ba | 12470 | (define_expand "sgeu" |
b932f770 JH |
12471 | [(set (match_operand:QI 0 "register_operand" "") |
12472 | (geu:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12473 | "" |
3a3677ff | 12474 | "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;") |
c572e5ba | 12475 | |
c572e5ba | 12476 | (define_expand "sle" |
b932f770 JH |
12477 | [(set (match_operand:QI 0 "register_operand" "") |
12478 | (le:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12479 | "" |
3a3677ff | 12480 | "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;") |
c572e5ba | 12481 | |
c785c660 | 12482 | (define_expand "sleu" |
b932f770 JH |
12483 | [(set (match_operand:QI 0 "register_operand" "") |
12484 | (leu:QI (reg:CC 17) (const_int 0)))] | |
c785c660 | 12485 | "" |
3a3677ff RH |
12486 | "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;") |
12487 | ||
12488 | (define_expand "sunordered" | |
b932f770 JH |
12489 | [(set (match_operand:QI 0 "register_operand" "") |
12490 | (unordered:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12491 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12492 | "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;") |
12493 | ||
12494 | (define_expand "sordered" | |
b932f770 JH |
12495 | [(set (match_operand:QI 0 "register_operand" "") |
12496 | (ordered:QI (reg:CC 17) (const_int 0)))] | |
3a3677ff RH |
12497 | "TARGET_80387" |
12498 | "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;") | |
12499 | ||
12500 | (define_expand "suneq" | |
b932f770 JH |
12501 | [(set (match_operand:QI 0 "register_operand" "") |
12502 | (uneq:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12503 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12504 | "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;") |
12505 | ||
12506 | (define_expand "sunge" | |
b932f770 JH |
12507 | [(set (match_operand:QI 0 "register_operand" "") |
12508 | (unge:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12509 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12510 | "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;") |
12511 | ||
12512 | (define_expand "sungt" | |
b932f770 JH |
12513 | [(set (match_operand:QI 0 "register_operand" "") |
12514 | (ungt:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12515 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12516 | "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;") |
12517 | ||
12518 | (define_expand "sunle" | |
b932f770 JH |
12519 | [(set (match_operand:QI 0 "register_operand" "") |
12520 | (unle:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12521 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12522 | "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;") |
12523 | ||
12524 | (define_expand "sunlt" | |
b932f770 JH |
12525 | [(set (match_operand:QI 0 "register_operand" "") |
12526 | (unlt:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12527 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12528 | "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;") |
12529 | ||
12530 | (define_expand "sltgt" | |
b932f770 JH |
12531 | [(set (match_operand:QI 0 "register_operand" "") |
12532 | (ltgt:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12533 | "TARGET_80387 || TARGET_SSE" |
3a3677ff | 12534 | "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;") |
c785c660 | 12535 | |
e075ae69 | 12536 | (define_insn "*setcc_1" |
a269a03c | 12537 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
9076b9c1 | 12538 | (match_operator:QI 1 "ix86_comparison_operator" |
e075ae69 RH |
12539 | [(reg 17) (const_int 0)]))] |
12540 | "" | |
0f40f9f7 | 12541 | "set%C1\t%0" |
6ef67412 JH |
12542 | [(set_attr "type" "setcc") |
12543 | (set_attr "mode" "QI")]) | |
a269a03c | 12544 | |
bd793c65 | 12545 | (define_insn "setcc_2" |
e075ae69 | 12546 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) |
9076b9c1 | 12547 | (match_operator:QI 1 "ix86_comparison_operator" |
e075ae69 RH |
12548 | [(reg 17) (const_int 0)]))] |
12549 | "" | |
0f40f9f7 | 12550 | "set%C1\t%0" |
6ef67412 JH |
12551 | [(set_attr "type" "setcc") |
12552 | (set_attr "mode" "QI")]) | |
e075ae69 | 12553 | |
10978207 RH |
12554 | ;; In general it is not safe to assume too much about CCmode registers, |
12555 | ;; so simplify-rtx stops when it sees a second one. Under certain | |
12556 | ;; conditions this is safe on x86, so help combine not create | |
12557 | ;; | |
12558 | ;; seta %al | |
12559 | ;; testb %al, %al | |
12560 | ;; sete %al | |
12561 | ||
12562 | (define_split | |
12563 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
12564 | (ne:QI (match_operator 1 "ix86_comparison_operator" | |
12565 | [(reg 17) (const_int 0)]) | |
12566 | (const_int 0)))] | |
12567 | "" | |
12568 | [(set (match_dup 0) (match_dup 1))] | |
12569 | { | |
12570 | PUT_MODE (operands[1], QImode); | |
12571 | }) | |
12572 | ||
12573 | (define_split | |
12574 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) | |
12575 | (ne:QI (match_operator 1 "ix86_comparison_operator" | |
12576 | [(reg 17) (const_int 0)]) | |
12577 | (const_int 0)))] | |
12578 | "" | |
12579 | [(set (match_dup 0) (match_dup 1))] | |
12580 | { | |
12581 | PUT_MODE (operands[1], QImode); | |
12582 | }) | |
12583 | ||
12584 | (define_split | |
12585 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
12586 | (eq:QI (match_operator 1 "ix86_comparison_operator" | |
12587 | [(reg 17) (const_int 0)]) | |
12588 | (const_int 0)))] | |
12589 | "" | |
12590 | [(set (match_dup 0) (match_dup 1))] | |
12591 | { | |
12592 | rtx new_op1 = copy_rtx (operands[1]); | |
12593 | operands[1] = new_op1; | |
12594 | PUT_MODE (new_op1, QImode); | |
12595 | PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1), | |
12596 | GET_MODE (XEXP (new_op1, 0)))); | |
12597 | ||
12598 | /* Make sure that (a) the CCmode we have for the flags is strong | |
12599 | enough for the reversed compare or (b) we have a valid FP compare. */ | |
12600 | if (! ix86_comparison_operator (new_op1, VOIDmode)) | |
12601 | FAIL; | |
12602 | }) | |
12603 | ||
12604 | (define_split | |
12605 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) | |
12606 | (eq:QI (match_operator 1 "ix86_comparison_operator" | |
12607 | [(reg 17) (const_int 0)]) | |
12608 | (const_int 0)))] | |
12609 | "" | |
12610 | [(set (match_dup 0) (match_dup 1))] | |
12611 | { | |
12612 | rtx new_op1 = copy_rtx (operands[1]); | |
12613 | operands[1] = new_op1; | |
12614 | PUT_MODE (new_op1, QImode); | |
12615 | PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1), | |
12616 | GET_MODE (XEXP (new_op1, 0)))); | |
12617 | ||
12618 | /* Make sure that (a) the CCmode we have for the flags is strong | |
12619 | enough for the reversed compare or (b) we have a valid FP compare. */ | |
12620 | if (! ix86_comparison_operator (new_op1, VOIDmode)) | |
12621 | FAIL; | |
12622 | }) | |
12623 | ||
a46d1d38 JH |
12624 | ;; The SSE store flag instructions saves 0 or 0xffffffff to the result. |
12625 | ;; subsequent logical operations are used to imitate conditional moves. | |
12626 | ;; 0xffffffff is NaN, but not in normalized form, so we can't represent | |
12627 | ;; it directly. Futher holding this value in pseudo register might bring | |
12628 | ;; problem in implicit normalization in spill code. | |
12629 | ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these | |
12630 | ;; instructions after reload by splitting the conditional move patterns. | |
12631 | ||
12632 | (define_insn "*sse_setccsf" | |
12633 | [(set (match_operand:SF 0 "register_operand" "=x") | |
12634 | (match_operator:SF 1 "sse_comparison_operator" | |
12635 | [(match_operand:SF 2 "register_operand" "0") | |
12636 | (match_operand:SF 3 "nonimmediate_operand" "xm")]))] | |
12637 | "TARGET_SSE && reload_completed" | |
0f40f9f7 | 12638 | "cmp%D1ss\t{%3, %0|%0, %3}" |
a46d1d38 JH |
12639 | [(set_attr "type" "sse") |
12640 | (set_attr "mode" "SF")]) | |
12641 | ||
12642 | (define_insn "*sse_setccdf" | |
12643 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
12644 | (match_operator:DF 1 "sse_comparison_operator" | |
12645 | [(match_operand:DF 2 "register_operand" "0") | |
12646 | (match_operand:DF 3 "nonimmediate_operand" "Ym")]))] | |
12647 | "TARGET_SSE2 && reload_completed" | |
0f40f9f7 | 12648 | "cmp%D1sd\t{%3, %0|%0, %3}" |
a46d1d38 JH |
12649 | [(set_attr "type" "sse") |
12650 | (set_attr "mode" "DF")]) | |
886c62d1 JVA |
12651 | \f |
12652 | ;; Basic conditional jump instructions. | |
12653 | ;; We ignore the overflow flag for signed branch instructions. | |
12654 | ||
c572e5ba | 12655 | ;; For all bCOND expanders, also expand the compare or test insn that |
e075ae69 | 12656 | ;; generates reg 17. Generate an equality comparison if `beq' or `bne'. |
c572e5ba JVA |
12657 | |
12658 | (define_expand "beq" | |
e075ae69 RH |
12659 | [(set (pc) |
12660 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12661 | (label_ref (match_operand 0 "" "")) |
12662 | (pc)))] | |
12663 | "" | |
3a3677ff | 12664 | "ix86_expand_branch (EQ, operands[0]); DONE;") |
c572e5ba | 12665 | |
c572e5ba | 12666 | (define_expand "bne" |
e075ae69 RH |
12667 | [(set (pc) |
12668 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12669 | (label_ref (match_operand 0 "" "")) |
12670 | (pc)))] | |
12671 | "" | |
3a3677ff | 12672 | "ix86_expand_branch (NE, operands[0]); DONE;") |
886c62d1 | 12673 | |
c572e5ba | 12674 | (define_expand "bgt" |
e075ae69 RH |
12675 | [(set (pc) |
12676 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12677 | (label_ref (match_operand 0 "" "")) |
12678 | (pc)))] | |
12679 | "" | |
3a3677ff | 12680 | "ix86_expand_branch (GT, operands[0]); DONE;") |
c572e5ba | 12681 | |
c572e5ba | 12682 | (define_expand "bgtu" |
e075ae69 RH |
12683 | [(set (pc) |
12684 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12685 | (label_ref (match_operand 0 "" "")) |
12686 | (pc)))] | |
12687 | "" | |
3a3677ff | 12688 | "ix86_expand_branch (GTU, operands[0]); DONE;") |
886c62d1 | 12689 | |
886c62d1 | 12690 | (define_expand "blt" |
e075ae69 RH |
12691 | [(set (pc) |
12692 | (if_then_else (match_dup 1) | |
886c62d1 JVA |
12693 | (label_ref (match_operand 0 "" "")) |
12694 | (pc)))] | |
12695 | "" | |
3a3677ff | 12696 | "ix86_expand_branch (LT, operands[0]); DONE;") |
886c62d1 | 12697 | |
c572e5ba | 12698 | (define_expand "bltu" |
e075ae69 RH |
12699 | [(set (pc) |
12700 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12701 | (label_ref (match_operand 0 "" "")) |
12702 | (pc)))] | |
12703 | "" | |
3a3677ff | 12704 | "ix86_expand_branch (LTU, operands[0]); DONE;") |
c572e5ba | 12705 | |
c572e5ba | 12706 | (define_expand "bge" |
e075ae69 RH |
12707 | [(set (pc) |
12708 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12709 | (label_ref (match_operand 0 "" "")) |
12710 | (pc)))] | |
12711 | "" | |
3a3677ff | 12712 | "ix86_expand_branch (GE, operands[0]); DONE;") |
c572e5ba | 12713 | |
c572e5ba | 12714 | (define_expand "bgeu" |
e075ae69 RH |
12715 | [(set (pc) |
12716 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12717 | (label_ref (match_operand 0 "" "")) |
12718 | (pc)))] | |
12719 | "" | |
3a3677ff | 12720 | "ix86_expand_branch (GEU, operands[0]); DONE;") |
886c62d1 | 12721 | |
886c62d1 | 12722 | (define_expand "ble" |
e075ae69 RH |
12723 | [(set (pc) |
12724 | (if_then_else (match_dup 1) | |
886c62d1 JVA |
12725 | (label_ref (match_operand 0 "" "")) |
12726 | (pc)))] | |
12727 | "" | |
3a3677ff | 12728 | "ix86_expand_branch (LE, operands[0]); DONE;") |
886c62d1 | 12729 | |
c572e5ba | 12730 | (define_expand "bleu" |
e075ae69 RH |
12731 | [(set (pc) |
12732 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12733 | (label_ref (match_operand 0 "" "")) |
12734 | (pc)))] | |
12735 | "" | |
3a3677ff RH |
12736 | "ix86_expand_branch (LEU, operands[0]); DONE;") |
12737 | ||
12738 | (define_expand "bunordered" | |
12739 | [(set (pc) | |
12740 | (if_then_else (match_dup 1) | |
12741 | (label_ref (match_operand 0 "" "")) | |
12742 | (pc)))] | |
0644b628 | 12743 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12744 | "ix86_expand_branch (UNORDERED, operands[0]); DONE;") |
12745 | ||
12746 | (define_expand "bordered" | |
12747 | [(set (pc) | |
12748 | (if_then_else (match_dup 1) | |
12749 | (label_ref (match_operand 0 "" "")) | |
12750 | (pc)))] | |
0644b628 | 12751 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12752 | "ix86_expand_branch (ORDERED, operands[0]); DONE;") |
12753 | ||
12754 | (define_expand "buneq" | |
12755 | [(set (pc) | |
12756 | (if_then_else (match_dup 1) | |
12757 | (label_ref (match_operand 0 "" "")) | |
12758 | (pc)))] | |
0644b628 | 12759 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12760 | "ix86_expand_branch (UNEQ, operands[0]); DONE;") |
12761 | ||
12762 | (define_expand "bunge" | |
12763 | [(set (pc) | |
12764 | (if_then_else (match_dup 1) | |
12765 | (label_ref (match_operand 0 "" "")) | |
12766 | (pc)))] | |
0644b628 | 12767 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12768 | "ix86_expand_branch (UNGE, operands[0]); DONE;") |
12769 | ||
12770 | (define_expand "bungt" | |
12771 | [(set (pc) | |
12772 | (if_then_else (match_dup 1) | |
12773 | (label_ref (match_operand 0 "" "")) | |
12774 | (pc)))] | |
0644b628 | 12775 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12776 | "ix86_expand_branch (UNGT, operands[0]); DONE;") |
12777 | ||
12778 | (define_expand "bunle" | |
12779 | [(set (pc) | |
12780 | (if_then_else (match_dup 1) | |
12781 | (label_ref (match_operand 0 "" "")) | |
12782 | (pc)))] | |
0644b628 | 12783 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12784 | "ix86_expand_branch (UNLE, operands[0]); DONE;") |
12785 | ||
12786 | (define_expand "bunlt" | |
12787 | [(set (pc) | |
12788 | (if_then_else (match_dup 1) | |
12789 | (label_ref (match_operand 0 "" "")) | |
12790 | (pc)))] | |
0644b628 | 12791 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12792 | "ix86_expand_branch (UNLT, operands[0]); DONE;") |
12793 | ||
12794 | (define_expand "bltgt" | |
12795 | [(set (pc) | |
12796 | (if_then_else (match_dup 1) | |
12797 | (label_ref (match_operand 0 "" "")) | |
12798 | (pc)))] | |
0644b628 | 12799 | "TARGET_80387 || TARGET_SSE" |
3a3677ff | 12800 | "ix86_expand_branch (LTGT, operands[0]); DONE;") |
886c62d1 | 12801 | |
e075ae69 RH |
12802 | (define_insn "*jcc_1" |
12803 | [(set (pc) | |
9076b9c1 | 12804 | (if_then_else (match_operator 1 "ix86_comparison_operator" |
e075ae69 | 12805 | [(reg 17) (const_int 0)]) |
6ef67412 | 12806 | (label_ref (match_operand 0 "" "")) |
e075ae69 RH |
12807 | (pc)))] |
12808 | "" | |
0f40f9f7 | 12809 | "%+j%C1\t%l0" |
e075ae69 | 12810 | [(set_attr "type" "ibr") |
6ef67412 JH |
12811 | (set (attr "prefix_0f") |
12812 | (if_then_else (and (ge (minus (match_dup 0) (pc)) | |
12813 | (const_int -128)) | |
12814 | (lt (minus (match_dup 0) (pc)) | |
12815 | (const_int 124))) | |
12816 | (const_int 0) | |
12817 | (const_int 1)))]) | |
e075ae69 RH |
12818 | |
12819 | (define_insn "*jcc_2" | |
12820 | [(set (pc) | |
9076b9c1 | 12821 | (if_then_else (match_operator 1 "ix86_comparison_operator" |
e075ae69 RH |
12822 | [(reg 17) (const_int 0)]) |
12823 | (pc) | |
6ef67412 | 12824 | (label_ref (match_operand 0 "" ""))))] |
e075ae69 | 12825 | "" |
0f40f9f7 | 12826 | "%+j%c1\t%l0" |
e075ae69 | 12827 | [(set_attr "type" "ibr") |
6ef67412 JH |
12828 | (set (attr "prefix_0f") |
12829 | (if_then_else (and (ge (minus (match_dup 0) (pc)) | |
12830 | (const_int -128)) | |
12831 | (lt (minus (match_dup 0) (pc)) | |
12832 | (const_int 124))) | |
12833 | (const_int 0) | |
12834 | (const_int 1)))]) | |
e075ae69 | 12835 | |
592188a5 RH |
12836 | ;; In general it is not safe to assume too much about CCmode registers, |
12837 | ;; so simplify-rtx stops when it sees a second one. Under certain | |
12838 | ;; conditions this is safe on x86, so help combine not create | |
12839 | ;; | |
12840 | ;; seta %al | |
12841 | ;; testb %al, %al | |
12842 | ;; je Lfoo | |
12843 | ||
12844 | (define_split | |
12845 | [(set (pc) | |
12846 | (if_then_else (ne (match_operator 0 "ix86_comparison_operator" | |
12847 | [(reg 17) (const_int 0)]) | |
12848 | (const_int 0)) | |
12849 | (label_ref (match_operand 1 "" "")) | |
12850 | (pc)))] | |
12851 | "" | |
12852 | [(set (pc) | |
12853 | (if_then_else (match_dup 0) | |
12854 | (label_ref (match_dup 1)) | |
12855 | (pc)))] | |
12856 | { | |
12857 | PUT_MODE (operands[0], VOIDmode); | |
12858 | }) | |
12859 | ||
12860 | (define_split | |
12861 | [(set (pc) | |
12862 | (if_then_else (eq (match_operator 0 "ix86_comparison_operator" | |
12863 | [(reg 17) (const_int 0)]) | |
12864 | (const_int 0)) | |
12865 | (label_ref (match_operand 1 "" "")) | |
12866 | (pc)))] | |
12867 | "" | |
12868 | [(set (pc) | |
12869 | (if_then_else (match_dup 0) | |
12870 | (label_ref (match_dup 1)) | |
12871 | (pc)))] | |
12872 | { | |
12873 | rtx new_op0 = copy_rtx (operands[0]); | |
12874 | operands[0] = new_op0; | |
12875 | PUT_MODE (new_op0, VOIDmode); | |
12876 | PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0), | |
12877 | GET_MODE (XEXP (new_op0, 0)))); | |
12878 | ||
12879 | /* Make sure that (a) the CCmode we have for the flags is strong | |
12880 | enough for the reversed compare or (b) we have a valid FP compare. */ | |
12881 | if (! ix86_comparison_operator (new_op0, VOIDmode)) | |
12882 | FAIL; | |
12883 | }) | |
12884 | ||
3a3677ff RH |
12885 | ;; Define combination compare-and-branch fp compare instructions to use |
12886 | ;; during early optimization. Splitting the operation apart early makes | |
12887 | ;; for bad code when we want to reverse the operation. | |
12888 | ||
12889 | (define_insn "*fp_jcc_1" | |
12890 | [(set (pc) | |
12891 | (if_then_else (match_operator 0 "comparison_operator" | |
12892 | [(match_operand 1 "register_operand" "f") | |
12893 | (match_operand 2 "register_operand" "f")]) | |
12894 | (label_ref (match_operand 3 "" "")) | |
12895 | (pc))) | |
12896 | (clobber (reg:CCFP 18)) | |
12897 | (clobber (reg:CCFP 17))] | |
12898 | "TARGET_CMOVE && TARGET_80387 | |
0644b628 | 12899 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1])) |
3a3677ff | 12900 | && FLOAT_MODE_P (GET_MODE (operands[1])) |
03598dea JH |
12901 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12902 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
12903 | "#") |
12904 | ||
0644b628 JH |
12905 | (define_insn "*fp_jcc_1_sse" |
12906 | [(set (pc) | |
12907 | (if_then_else (match_operator 0 "comparison_operator" | |
12908 | [(match_operand 1 "register_operand" "f#x,x#f") | |
12909 | (match_operand 2 "nonimmediate_operand" "f#x,xm#f")]) | |
12910 | (label_ref (match_operand 3 "" "")) | |
12911 | (pc))) | |
12912 | (clobber (reg:CCFP 18)) | |
12913 | (clobber (reg:CCFP 17))] | |
12914 | "TARGET_80387 | |
12915 | && SSE_FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
12916 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12917 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
0644b628 JH |
12918 | "#") |
12919 | ||
12920 | (define_insn "*fp_jcc_1_sse_only" | |
12921 | [(set (pc) | |
12922 | (if_then_else (match_operator 0 "comparison_operator" | |
12923 | [(match_operand 1 "register_operand" "x") | |
12924 | (match_operand 2 "nonimmediate_operand" "xm")]) | |
12925 | (label_ref (match_operand 3 "" "")) | |
12926 | (pc))) | |
12927 | (clobber (reg:CCFP 18)) | |
12928 | (clobber (reg:CCFP 17))] | |
12929 | "SSE_FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
12930 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12931 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
0644b628 JH |
12932 | "#") |
12933 | ||
3a3677ff RH |
12934 | (define_insn "*fp_jcc_2" |
12935 | [(set (pc) | |
12936 | (if_then_else (match_operator 0 "comparison_operator" | |
12937 | [(match_operand 1 "register_operand" "f") | |
12938 | (match_operand 2 "register_operand" "f")]) | |
12939 | (pc) | |
12940 | (label_ref (match_operand 3 "" "")))) | |
12941 | (clobber (reg:CCFP 18)) | |
12942 | (clobber (reg:CCFP 17))] | |
12943 | "TARGET_CMOVE && TARGET_80387 | |
0644b628 | 12944 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1])) |
3a3677ff | 12945 | && FLOAT_MODE_P (GET_MODE (operands[1])) |
03598dea JH |
12946 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12947 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
12948 | "#") |
12949 | ||
0644b628 JH |
12950 | (define_insn "*fp_jcc_2_sse" |
12951 | [(set (pc) | |
12952 | (if_then_else (match_operator 0 "comparison_operator" | |
12953 | [(match_operand 1 "register_operand" "f#x,x#f") | |
12954 | (match_operand 2 "nonimmediate_operand" "f#x,xm#f")]) | |
12955 | (pc) | |
12956 | (label_ref (match_operand 3 "" "")))) | |
12957 | (clobber (reg:CCFP 18)) | |
12958 | (clobber (reg:CCFP 17))] | |
12959 | "TARGET_80387 | |
12960 | && SSE_FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
12961 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12962 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
0644b628 JH |
12963 | "#") |
12964 | ||
12965 | (define_insn "*fp_jcc_2_sse_only" | |
12966 | [(set (pc) | |
12967 | (if_then_else (match_operator 0 "comparison_operator" | |
12968 | [(match_operand 1 "register_operand" "x") | |
12969 | (match_operand 2 "nonimmediate_operand" "xm")]) | |
12970 | (pc) | |
12971 | (label_ref (match_operand 3 "" "")))) | |
12972 | (clobber (reg:CCFP 18)) | |
12973 | (clobber (reg:CCFP 17))] | |
12974 | "SSE_FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
12975 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12976 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
0644b628 JH |
12977 | "#") |
12978 | ||
3a3677ff RH |
12979 | (define_insn "*fp_jcc_3" |
12980 | [(set (pc) | |
b1cdafbb | 12981 | (if_then_else (match_operator 0 "comparison_operator" |
3a3677ff RH |
12982 | [(match_operand 1 "register_operand" "f") |
12983 | (match_operand 2 "nonimmediate_operand" "fm")]) | |
12984 | (label_ref (match_operand 3 "" "")) | |
12985 | (pc))) | |
12986 | (clobber (reg:CCFP 18)) | |
12987 | (clobber (reg:CCFP 17)) | |
12988 | (clobber (match_scratch:HI 4 "=a"))] | |
12989 | "TARGET_80387 | |
12990 | && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode) | |
a940d8bd | 12991 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
b1cdafbb JH |
12992 | && !ix86_use_fcomi_compare (GET_CODE (operands[0])) |
12993 | && SELECT_CC_MODE (GET_CODE (operands[0]), | |
03598dea JH |
12994 | operands[1], operands[2]) == CCFPmode |
12995 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
12996 | "#") |
12997 | ||
12998 | (define_insn "*fp_jcc_4" | |
12999 | [(set (pc) | |
b1cdafbb | 13000 | (if_then_else (match_operator 0 "comparison_operator" |
3a3677ff RH |
13001 | [(match_operand 1 "register_operand" "f") |
13002 | (match_operand 2 "nonimmediate_operand" "fm")]) | |
13003 | (pc) | |
13004 | (label_ref (match_operand 3 "" "")))) | |
13005 | (clobber (reg:CCFP 18)) | |
13006 | (clobber (reg:CCFP 17)) | |
13007 | (clobber (match_scratch:HI 4 "=a"))] | |
13008 | "TARGET_80387 | |
13009 | && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode) | |
a940d8bd | 13010 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
b1cdafbb JH |
13011 | && !ix86_use_fcomi_compare (GET_CODE (operands[0])) |
13012 | && SELECT_CC_MODE (GET_CODE (operands[0]), | |
03598dea JH |
13013 | operands[1], operands[2]) == CCFPmode |
13014 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
13015 | "#") |
13016 | ||
13017 | (define_insn "*fp_jcc_5" | |
13018 | [(set (pc) | |
13019 | (if_then_else (match_operator 0 "comparison_operator" | |
13020 | [(match_operand 1 "register_operand" "f") | |
13021 | (match_operand 2 "register_operand" "f")]) | |
13022 | (label_ref (match_operand 3 "" "")) | |
13023 | (pc))) | |
13024 | (clobber (reg:CCFP 18)) | |
13025 | (clobber (reg:CCFP 17)) | |
13026 | (clobber (match_scratch:HI 4 "=a"))] | |
13027 | "TARGET_80387 | |
13028 | && FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
13029 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
13030 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
13031 | "#") |
13032 | ||
13033 | (define_insn "*fp_jcc_6" | |
13034 | [(set (pc) | |
13035 | (if_then_else (match_operator 0 "comparison_operator" | |
13036 | [(match_operand 1 "register_operand" "f") | |
13037 | (match_operand 2 "register_operand" "f")]) | |
13038 | (pc) | |
13039 | (label_ref (match_operand 3 "" "")))) | |
13040 | (clobber (reg:CCFP 18)) | |
13041 | (clobber (reg:CCFP 17)) | |
13042 | (clobber (match_scratch:HI 4 "=a"))] | |
13043 | "TARGET_80387 | |
13044 | && FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
13045 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
13046 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
13047 | "#") |
13048 | ||
13049 | (define_split | |
13050 | [(set (pc) | |
13051 | (if_then_else (match_operator 0 "comparison_operator" | |
13052 | [(match_operand 1 "register_operand" "") | |
13053 | (match_operand 2 "nonimmediate_operand" "")]) | |
13054 | (match_operand 3 "" "") | |
13055 | (match_operand 4 "" ""))) | |
13056 | (clobber (reg:CCFP 18)) | |
13057 | (clobber (reg:CCFP 17))] | |
13058 | "reload_completed" | |
9e7adcb3 | 13059 | [(const_int 0)] |
3a3677ff | 13060 | { |
03598dea | 13061 | ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2], |
9e7adcb3 JH |
13062 | operands[3], operands[4], NULL_RTX); |
13063 | DONE; | |
0f40f9f7 | 13064 | }) |
3a3677ff RH |
13065 | |
13066 | (define_split | |
13067 | [(set (pc) | |
13068 | (if_then_else (match_operator 0 "comparison_operator" | |
13069 | [(match_operand 1 "register_operand" "") | |
13070 | (match_operand 2 "nonimmediate_operand" "")]) | |
13071 | (match_operand 3 "" "") | |
13072 | (match_operand 4 "" ""))) | |
13073 | (clobber (reg:CCFP 18)) | |
13074 | (clobber (reg:CCFP 17)) | |
13075 | (clobber (match_scratch:HI 5 "=a"))] | |
13076 | "reload_completed" | |
13077 | [(set (pc) | |
13078 | (if_then_else (match_dup 6) | |
13079 | (match_dup 3) | |
13080 | (match_dup 4)))] | |
3a3677ff | 13081 | { |
03598dea | 13082 | ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2], |
9e7adcb3 JH |
13083 | operands[3], operands[4], operands[5]); |
13084 | DONE; | |
0f40f9f7 | 13085 | }) |
886c62d1 JVA |
13086 | \f |
13087 | ;; Unconditional and other jump instructions | |
13088 | ||
13089 | (define_insn "jump" | |
13090 | [(set (pc) | |
13091 | (label_ref (match_operand 0 "" "")))] | |
13092 | "" | |
0f40f9f7 | 13093 | "jmp\t%l0" |
6ef67412 | 13094 | [(set_attr "type" "ibr")]) |
886c62d1 | 13095 | |
14f73b5a JH |
13096 | (define_expand "indirect_jump" |
13097 | [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))] | |
886c62d1 | 13098 | "" |
14f73b5a JH |
13099 | "") |
13100 | ||
13101 | (define_insn "*indirect_jump" | |
13102 | [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))] | |
13103 | "!TARGET_64BIT" | |
13104 | "jmp\t%A0" | |
13105 | [(set_attr "type" "ibr") | |
13106 | (set_attr "length_immediate" "0")]) | |
13107 | ||
13108 | (define_insn "*indirect_jump_rtx64" | |
13109 | [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))] | |
13110 | "TARGET_64BIT" | |
0f40f9f7 | 13111 | "jmp\t%A0" |
6ef67412 JH |
13112 | [(set_attr "type" "ibr") |
13113 | (set_attr "length_immediate" "0")]) | |
4801403e | 13114 | |
90675921 | 13115 | (define_expand "tablejump" |
6eb791fc | 13116 | [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm")) |
90675921 RH |
13117 | (use (label_ref (match_operand 1 "" "")))])] |
13118 | "" | |
13119 | { | |
13120 | /* In PIC mode, the table entries are stored GOT-relative. Convert | |
13121 | the relative address to an absolute address. */ | |
13122 | if (flag_pic) | |
13123 | { | |
6eb791fc JH |
13124 | if (TARGET_64BIT) |
13125 | operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], | |
44cf5b6a JH |
13126 | gen_rtx_LABEL_REF (Pmode, operands[1]), |
13127 | NULL_RTX, 0, | |
6eb791fc | 13128 | OPTAB_DIRECT); |
f88c65f7 RH |
13129 | else if (HAVE_AS_GOTOFF_IN_DATA) |
13130 | { | |
13131 | operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], | |
13132 | pic_offset_table_rtx, NULL_RTX, | |
13133 | 1, OPTAB_DIRECT); | |
13134 | current_function_uses_pic_offset_table = 1; | |
13135 | } | |
6eb791fc JH |
13136 | else |
13137 | { | |
13138 | operands[0] = expand_simple_binop (Pmode, MINUS, pic_offset_table_rtx, | |
13139 | operands[0], NULL_RTX, 1, | |
13140 | OPTAB_DIRECT); | |
13141 | current_function_uses_pic_offset_table = 1; | |
13142 | } | |
90675921 | 13143 | } |
0f40f9f7 | 13144 | }) |
2bb7a0f5 | 13145 | |
90675921 | 13146 | (define_insn "*tablejump_1" |
2ae0f82c | 13147 | [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm")) |
886c62d1 | 13148 | (use (label_ref (match_operand 1 "" "")))] |
14f73b5a JH |
13149 | "!TARGET_64BIT" |
13150 | "jmp\t%A0" | |
13151 | [(set_attr "type" "ibr") | |
13152 | (set_attr "length_immediate" "0")]) | |
13153 | ||
13154 | (define_insn "*tablejump_1_rtx64" | |
13155 | [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm")) | |
13156 | (use (label_ref (match_operand 1 "" "")))] | |
13157 | "TARGET_64BIT" | |
0f40f9f7 | 13158 | "jmp\t%A0" |
6ef67412 JH |
13159 | [(set_attr "type" "ibr") |
13160 | (set_attr "length_immediate" "0")]) | |
e075ae69 RH |
13161 | \f |
13162 | ;; Loop instruction | |
13163 | ;; | |
13164 | ;; This is all complicated by the fact that since this is a jump insn | |
13165 | ;; we must handle our own reloads. | |
13166 | ||
5527bf14 RH |
13167 | (define_expand "doloop_end" |
13168 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13169 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13170 | (use (match_operand 2 "" "")) ; max iterations | |
13171 | (use (match_operand 3 "" "")) ; loop level | |
13172 | (use (match_operand 4 "" ""))] ; label | |
1b0c37d7 | 13173 | "!TARGET_64BIT && TARGET_USE_LOOP" |
5527bf14 RH |
13174 | " |
13175 | { | |
13176 | /* Only use cloop on innermost loops. */ | |
13177 | if (INTVAL (operands[3]) > 1) | |
13178 | FAIL; | |
13179 | if (GET_MODE (operands[0]) != SImode) | |
13180 | FAIL; | |
13181 | emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0], | |
13182 | operands[0])); | |
13183 | DONE; | |
13184 | }") | |
e075ae69 | 13185 | |
5527bf14 | 13186 | (define_insn "doloop_end_internal" |
e075ae69 | 13187 | [(set (pc) |
5527bf14 | 13188 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r") |
e075ae69 RH |
13189 | (const_int 1)) |
13190 | (label_ref (match_operand 0 "" "")) | |
13191 | (pc))) | |
5527bf14 | 13192 | (set (match_operand:SI 2 "register_operand" "=1,1,*m*r") |
e075ae69 RH |
13193 | (plus:SI (match_dup 1) |
13194 | (const_int -1))) | |
13195 | (clobber (match_scratch:SI 3 "=X,X,r")) | |
13196 | (clobber (reg:CC 17))] | |
1b0c37d7 | 13197 | "!TARGET_64BIT && TARGET_USE_LOOP" |
e075ae69 RH |
13198 | { |
13199 | if (which_alternative != 0) | |
0f40f9f7 | 13200 | return "#"; |
e075ae69 | 13201 | if (get_attr_length (insn) == 2) |
0f40f9f7 | 13202 | return "%+loop\t%l0"; |
e075ae69 | 13203 | else |
0f40f9f7 ZW |
13204 | return "dec{l}\t%1\;%+jne\t%l0"; |
13205 | } | |
6ef67412 JH |
13206 | [(set_attr "ppro_uops" "many") |
13207 | (set (attr "type") | |
e075ae69 RH |
13208 | (if_then_else (and (eq_attr "alternative" "0") |
13209 | (and (ge (minus (match_dup 0) (pc)) | |
13210 | (const_int -128)) | |
13211 | (lt (minus (match_dup 0) (pc)) | |
13212 | (const_int 124)))) | |
6ef67412 JH |
13213 | (const_string "ibr") |
13214 | (const_string "multi")))]) | |
e075ae69 | 13215 | |
e075ae69 RH |
13216 | (define_split |
13217 | [(set (pc) | |
13218 | (if_then_else (ne (match_operand:SI 1 "register_operand" "") | |
13219 | (const_int 1)) | |
13220 | (match_operand 0 "" "") | |
13221 | (pc))) | |
5527bf14 | 13222 | (set (match_dup 1) |
e075ae69 RH |
13223 | (plus:SI (match_dup 1) |
13224 | (const_int -1))) | |
5527bf14 | 13225 | (clobber (match_scratch:SI 2 "")) |
e075ae69 | 13226 | (clobber (reg:CC 17))] |
1b0c37d7 | 13227 | "!TARGET_64BIT && TARGET_USE_LOOP |
5527bf14 RH |
13228 | && reload_completed |
13229 | && REGNO (operands[1]) != 2" | |
13230 | [(parallel [(set (reg:CCZ 17) | |
13231 | (compare:CCZ (plus:SI (match_dup 1) (const_int -1)) | |
e075ae69 | 13232 | (const_int 0))) |
5527bf14 | 13233 | (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))]) |
16189740 | 13234 | (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0)) |
e075ae69 RH |
13235 | (match_dup 0) |
13236 | (pc)))] | |
13237 | "") | |
13238 | ||
13239 | (define_split | |
13240 | [(set (pc) | |
13241 | (if_then_else (ne (match_operand:SI 1 "register_operand" "") | |
13242 | (const_int 1)) | |
13243 | (match_operand 0 "" "") | |
13244 | (pc))) | |
5527bf14 | 13245 | (set (match_operand:SI 2 "nonimmediate_operand" "") |
e075ae69 RH |
13246 | (plus:SI (match_dup 1) |
13247 | (const_int -1))) | |
13248 | (clobber (match_scratch:SI 3 "")) | |
13249 | (clobber (reg:CC 17))] | |
1b0c37d7 | 13250 | "!TARGET_64BIT && TARGET_USE_LOOP |
5527bf14 RH |
13251 | && reload_completed |
13252 | && (! REG_P (operands[2]) | |
13253 | || ! rtx_equal_p (operands[1], operands[2]))" | |
e075ae69 | 13254 | [(set (match_dup 3) (match_dup 1)) |
16189740 RH |
13255 | (parallel [(set (reg:CCZ 17) |
13256 | (compare:CCZ (plus:SI (match_dup 3) (const_int -1)) | |
13257 | (const_int 0))) | |
e075ae69 RH |
13258 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) |
13259 | (set (match_dup 2) (match_dup 3)) | |
16189740 | 13260 | (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0)) |
e075ae69 RH |
13261 | (match_dup 0) |
13262 | (pc)))] | |
13263 | "") | |
c50e5bc0 RH |
13264 | |
13265 | ;; Convert setcc + movzbl to xor + setcc if operands don't overlap. | |
13266 | ||
13267 | (define_peephole2 | |
13268 | [(set (reg 17) (match_operand 0 "" "")) | |
13269 | (set (match_operand:QI 1 "register_operand" "") | |
13270 | (match_operator:QI 2 "ix86_comparison_operator" | |
13271 | [(reg 17) (const_int 0)])) | |
13272 | (set (match_operand 3 "q_regs_operand" "") | |
13273 | (zero_extend (match_dup 1)))] | |
646ded90 RH |
13274 | "(peep2_reg_dead_p (3, operands[1]) |
13275 | || operands_match_p (operands[1], operands[3])) | |
c50e5bc0 | 13276 | && ! reg_overlap_mentioned_p (operands[3], operands[0])" |
646ded90 RH |
13277 | [(set (match_dup 4) (match_dup 0)) |
13278 | (set (strict_low_part (match_dup 5)) | |
13279 | (match_dup 2))] | |
13280 | { | |
13281 | operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17); | |
13282 | operands[5] = gen_rtx_REG (QImode, REGNO (operands[3])); | |
a8bac9ab | 13283 | ix86_expand_clear (operands[3]); |
646ded90 RH |
13284 | }) |
13285 | ||
13286 | ;; Similar, but match zero_extendhisi2_and, which adds a clobber. | |
13287 | ||
13288 | (define_peephole2 | |
13289 | [(set (reg 17) (match_operand 0 "" "")) | |
13290 | (set (match_operand:QI 1 "register_operand" "") | |
13291 | (match_operator:QI 2 "ix86_comparison_operator" | |
13292 | [(reg 17) (const_int 0)])) | |
13293 | (parallel [(set (match_operand 3 "q_regs_operand" "") | |
13294 | (zero_extend (match_dup 1))) | |
13295 | (clobber (reg:CC 17))])] | |
13296 | "(peep2_reg_dead_p (3, operands[1]) | |
13297 | || operands_match_p (operands[1], operands[3])) | |
13298 | && ! reg_overlap_mentioned_p (operands[3], operands[0])" | |
13299 | [(set (match_dup 4) (match_dup 0)) | |
c50e5bc0 RH |
13300 | (set (strict_low_part (match_dup 5)) |
13301 | (match_dup 2))] | |
646ded90 RH |
13302 | { |
13303 | operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17); | |
13304 | operands[5] = gen_rtx_REG (QImode, REGNO (operands[3])); | |
a8bac9ab | 13305 | ix86_expand_clear (operands[3]); |
646ded90 | 13306 | }) |
e075ae69 RH |
13307 | \f |
13308 | ;; Call instructions. | |
2bb7a0f5 | 13309 | |
cbbf65e0 RH |
13310 | ;; The predicates normally associated with named expanders are not properly |
13311 | ;; checked for calls. This is a bug in the generic code, but it isn't that | |
13312 | ;; easy to fix. Ignore it for now and be prepared to fix things up. | |
2bb7a0f5 | 13313 | |
886c62d1 JVA |
13314 | ;; Call subroutine returning no value. |
13315 | ||
2bb7a0f5 | 13316 | (define_expand "call_pop" |
cbbf65e0 RH |
13317 | [(parallel [(call (match_operand:QI 0 "" "") |
13318 | (match_operand:SI 1 "" "")) | |
2bb7a0f5 RS |
13319 | (set (reg:SI 7) |
13320 | (plus:SI (reg:SI 7) | |
cbbf65e0 | 13321 | (match_operand:SI 3 "" "")))])] |
1e07edd3 | 13322 | "!TARGET_64BIT" |
2bb7a0f5 | 13323 | { |
35e2d030 RH |
13324 | if (operands[3] == const0_rtx) |
13325 | { | |
32ee7d1d | 13326 | emit_insn (gen_call (operands[0], operands[1], constm1_rtx)); |
35e2d030 RH |
13327 | DONE; |
13328 | } | |
b848ded1 JH |
13329 | /* Static functions and indirect calls don't need |
13330 | current_function_uses_pic_offset_table. */ | |
13331 | if (flag_pic | |
2a4bbffa RH |
13332 | && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF |
13333 | && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0))) | |
2bb7a0f5 | 13334 | current_function_uses_pic_offset_table = 1; |
e1ff012c | 13335 | if (! call_insn_operand (XEXP (operands[0], 0), Pmode)) |
cbbf65e0 | 13336 | XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); |
1e07edd3 JH |
13337 | if (TARGET_64BIT) |
13338 | abort(); | |
0f40f9f7 | 13339 | }) |
2bb7a0f5 | 13340 | |
94bb5d0c | 13341 | (define_insn "*call_pop_0" |
e1ff012c | 13342 | [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" "")) |
94bb5d0c RH |
13343 | (match_operand:SI 1 "" "")) |
13344 | (set (reg:SI 7) (plus:SI (reg:SI 7) | |
90d10fb9 | 13345 | (match_operand:SI 2 "immediate_operand" "")))] |
1e07edd3 | 13346 | "!TARGET_64BIT" |
94bb5d0c RH |
13347 | { |
13348 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13349 | return "jmp\t%P0"; |
94bb5d0c | 13350 | else |
0f40f9f7 ZW |
13351 | return "call\t%P0"; |
13352 | } | |
94bb5d0c RH |
13353 | [(set_attr "type" "call")]) |
13354 | ||
cbbf65e0 | 13355 | (define_insn "*call_pop_1" |
e1ff012c | 13356 | [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm")) |
94bb5d0c | 13357 | (match_operand:SI 1 "" "")) |
886c62d1 | 13358 | (set (reg:SI 7) (plus:SI (reg:SI 7) |
90d10fb9 | 13359 | (match_operand:SI 2 "immediate_operand" "i")))] |
1e07edd3 | 13360 | "!TARGET_64BIT" |
886c62d1 | 13361 | { |
e1ff012c | 13362 | if (constant_call_address_operand (operands[0], Pmode)) |
94bb5d0c RH |
13363 | { |
13364 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13365 | return "jmp\t%P0"; |
94bb5d0c | 13366 | else |
0f40f9f7 | 13367 | return "call\t%P0"; |
94bb5d0c | 13368 | } |
94bb5d0c | 13369 | if (SIBLING_CALL_P (insn)) |
0f40f9f7 | 13370 | return "jmp\t%A0"; |
94bb5d0c | 13371 | else |
0f40f9f7 ZW |
13372 | return "call\t%A0"; |
13373 | } | |
e075ae69 | 13374 | [(set_attr "type" "call")]) |
886c62d1 | 13375 | |
2bb7a0f5 | 13376 | (define_expand "call" |
cbbf65e0 | 13377 | [(call (match_operand:QI 0 "" "") |
39d04363 JH |
13378 | (match_operand 1 "" "")) |
13379 | (use (match_operand 2 "" ""))] | |
2bb7a0f5 RS |
13380 | ;; Operand 1 not used on the i386. |
13381 | "" | |
2bb7a0f5 | 13382 | { |
39d04363 | 13383 | rtx insn; |
b848ded1 JH |
13384 | /* Static functions and indirect calls don't need |
13385 | current_function_uses_pic_offset_table. */ | |
13386 | if (flag_pic | |
2a4bbffa RH |
13387 | && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF |
13388 | && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0))) | |
2bb7a0f5 | 13389 | current_function_uses_pic_offset_table = 1; |
32ee7d1d | 13390 | |
e1ff012c | 13391 | if (! call_insn_operand (XEXP (operands[0], 0), Pmode)) |
cbbf65e0 | 13392 | XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); |
32ee7d1d JH |
13393 | if (TARGET_64BIT && INTVAL (operands[2]) >= 0) |
13394 | { | |
32ee7d1d JH |
13395 | rtx reg = gen_rtx_REG (QImode, 0); |
13396 | emit_move_insn (reg, operands[2]); | |
39d04363 | 13397 | insn = emit_call_insn (gen_call_exp (operands[0], operands[1])); |
32ee7d1d JH |
13398 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); |
13399 | DONE; | |
13400 | } | |
39d04363 JH |
13401 | insn = emit_call_insn (gen_call_exp (operands[0], operands[1])); |
13402 | DONE; | |
0f40f9f7 | 13403 | }) |
2bb7a0f5 | 13404 | |
32ee7d1d JH |
13405 | (define_expand "call_exp" |
13406 | [(call (match_operand:QI 0 "" "") | |
13407 | (match_operand 1 "" ""))] | |
13408 | "" | |
13409 | "") | |
13410 | ||
94bb5d0c | 13411 | (define_insn "*call_0" |
32ee7d1d JH |
13412 | [(call (mem:QI (match_operand 0 "constant_call_address_operand" "")) |
13413 | (match_operand 1 "" ""))] | |
94bb5d0c | 13414 | "" |
94bb5d0c RH |
13415 | { |
13416 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13417 | return "jmp\t%P0"; |
94bb5d0c | 13418 | else |
0f40f9f7 ZW |
13419 | return "call\t%P0"; |
13420 | } | |
94bb5d0c RH |
13421 | [(set_attr "type" "call")]) |
13422 | ||
cbbf65e0 | 13423 | (define_insn "*call_1" |
e1ff012c | 13424 | [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm")) |
32ee7d1d | 13425 | (match_operand 1 "" ""))] |
ac62a60e | 13426 | "!TARGET_64BIT" |
32ee7d1d JH |
13427 | { |
13428 | if (constant_call_address_operand (operands[0], QImode)) | |
13429 | { | |
13430 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13431 | return "jmp\t%P0"; |
32ee7d1d | 13432 | else |
0f40f9f7 | 13433 | return "call\t%P0"; |
32ee7d1d JH |
13434 | } |
13435 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13436 | return "jmp\t%A0"; |
32ee7d1d | 13437 | else |
0f40f9f7 ZW |
13438 | return "call\t%A0"; |
13439 | } | |
32ee7d1d JH |
13440 | [(set_attr "type" "call")]) |
13441 | ||
13442 | (define_insn "*call_1_rex64" | |
13443 | [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm")) | |
13444 | (match_operand 1 "" ""))] | |
ac62a60e | 13445 | "TARGET_64BIT" |
886c62d1 | 13446 | { |
94bb5d0c | 13447 | if (constant_call_address_operand (operands[0], QImode)) |
cbbf65e0 RH |
13448 | { |
13449 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13450 | return "jmp\t%P0"; |
cbbf65e0 | 13451 | else |
0f40f9f7 | 13452 | return "call\t%P0"; |
cbbf65e0 | 13453 | } |
cbbf65e0 | 13454 | if (SIBLING_CALL_P (insn)) |
0f40f9f7 | 13455 | return "jmp\t%A0"; |
cbbf65e0 | 13456 | else |
0f40f9f7 ZW |
13457 | return "call\t%A0"; |
13458 | } | |
e075ae69 | 13459 | [(set_attr "type" "call")]) |
886c62d1 JVA |
13460 | |
13461 | ;; Call subroutine, returning value in operand 0 | |
13462 | ;; (which must be a hard register). | |
13463 | ||
2bb7a0f5 RS |
13464 | (define_expand "call_value_pop" |
13465 | [(parallel [(set (match_operand 0 "" "") | |
cbbf65e0 RH |
13466 | (call (match_operand:QI 1 "" "") |
13467 | (match_operand:SI 2 "" ""))) | |
2bb7a0f5 RS |
13468 | (set (reg:SI 7) |
13469 | (plus:SI (reg:SI 7) | |
cbbf65e0 | 13470 | (match_operand:SI 4 "" "")))])] |
1e07edd3 | 13471 | "!TARGET_64BIT" |
2bb7a0f5 | 13472 | { |
35e2d030 RH |
13473 | if (operands[4] == const0_rtx) |
13474 | { | |
32ee7d1d JH |
13475 | emit_insn (gen_call_value (operands[0], operands[1], operands[2], |
13476 | constm1_rtx)); | |
35e2d030 RH |
13477 | DONE; |
13478 | } | |
b848ded1 JH |
13479 | /* Static functions and indirect calls don't need |
13480 | current_function_uses_pic_offset_table. */ | |
13481 | if (flag_pic | |
2a4bbffa RH |
13482 | && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF |
13483 | && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0))) | |
2bb7a0f5 | 13484 | current_function_uses_pic_offset_table = 1; |
e1ff012c | 13485 | if (! call_insn_operand (XEXP (operands[1], 0), Pmode)) |
cbbf65e0 | 13486 | XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); |
0f40f9f7 | 13487 | }) |
2bb7a0f5 | 13488 | |
2bb7a0f5 RS |
13489 | (define_expand "call_value" |
13490 | [(set (match_operand 0 "" "") | |
cbbf65e0 | 13491 | (call (match_operand:QI 1 "" "") |
39d04363 JH |
13492 | (match_operand:SI 2 "" ""))) |
13493 | (use (match_operand:SI 3 "" ""))] | |
2bb7a0f5 RS |
13494 | ;; Operand 2 not used on the i386. |
13495 | "" | |
2bb7a0f5 | 13496 | { |
39d04363 | 13497 | rtx insn; |
b848ded1 JH |
13498 | /* Static functions and indirect calls don't need |
13499 | current_function_uses_pic_offset_table. */ | |
13500 | if (flag_pic | |
2a4bbffa RH |
13501 | && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF |
13502 | && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0))) | |
2bb7a0f5 | 13503 | current_function_uses_pic_offset_table = 1; |
e1ff012c | 13504 | if (! call_insn_operand (XEXP (operands[1], 0), Pmode)) |
cbbf65e0 | 13505 | XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); |
32ee7d1d JH |
13506 | if (TARGET_64BIT && INTVAL (operands[3]) >= 0) |
13507 | { | |
32ee7d1d JH |
13508 | rtx reg = gen_rtx_REG (QImode, 0); |
13509 | emit_move_insn (reg, operands[3]); | |
13510 | insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1], | |
39d04363 | 13511 | operands[2])); |
32ee7d1d JH |
13512 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); |
13513 | DONE; | |
13514 | } | |
39d04363 JH |
13515 | insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1], |
13516 | operands[2])); | |
13517 | DONE; | |
0f40f9f7 | 13518 | }) |
2bb7a0f5 | 13519 | |
32ee7d1d JH |
13520 | (define_expand "call_value_exp" |
13521 | [(set (match_operand 0 "" "") | |
13522 | (call (match_operand:QI 1 "" "") | |
13523 | (match_operand:SI 2 "" "")))] | |
13524 | "" | |
13525 | "") | |
13526 | ||
b840bfb0 MM |
13527 | ;; Call subroutine returning any type. |
13528 | ||
576182a3 | 13529 | (define_expand "untyped_call" |
b840bfb0 | 13530 | [(parallel [(call (match_operand 0 "" "") |
576182a3 | 13531 | (const_int 0)) |
b840bfb0 | 13532 | (match_operand 1 "" "") |
576182a3 TW |
13533 | (match_operand 2 "" "")])] |
13534 | "" | |
576182a3 | 13535 | { |
b840bfb0 | 13536 | int i; |
576182a3 | 13537 | |
d8b679b9 RK |
13538 | /* In order to give reg-stack an easier job in validating two |
13539 | coprocessor registers as containing a possible return value, | |
13540 | simply pretend the untyped call returns a complex long double | |
13541 | value. */ | |
74775c7a | 13542 | |
d8b679b9 | 13543 | emit_call_insn (TARGET_80387 |
f64cecad | 13544 | ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG), |
32ee7d1d JH |
13545 | operands[0], const0_rtx, |
13546 | GEN_INT (SSE_REGPARM_MAX - 1)) | |
13547 | : gen_call (operands[0], const0_rtx, | |
13548 | GEN_INT (SSE_REGPARM_MAX - 1))); | |
576182a3 | 13549 | |
b840bfb0 | 13550 | for (i = 0; i < XVECLEN (operands[2], 0); i++) |
576182a3 | 13551 | { |
b840bfb0 MM |
13552 | rtx set = XVECEXP (operands[2], 0, i); |
13553 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
576182a3 | 13554 | } |
576182a3 | 13555 | |
b840bfb0 MM |
13556 | /* The optimizer does not know that the call sets the function value |
13557 | registers we stored in the result block. We avoid problems by | |
13558 | claiming that all hard registers are used and clobbered at this | |
13559 | point. */ | |
13560 | emit_insn (gen_blockage ()); | |
576182a3 TW |
13561 | |
13562 | DONE; | |
0f40f9f7 | 13563 | }) |
e075ae69 RH |
13564 | \f |
13565 | ;; Prologue and epilogue instructions | |
576182a3 | 13566 | |
b840bfb0 MM |
13567 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
13568 | ;; all of memory. This blocks insns from being moved across this point. | |
13569 | ||
13570 | (define_insn "blockage" | |
13571 | [(unspec_volatile [(const_int 0)] 0)] | |
576182a3 | 13572 | "" |
90aec2cf | 13573 | "" |
e075ae69 | 13574 | [(set_attr "length" "0")]) |
576182a3 | 13575 | |
886c62d1 JVA |
13576 | ;; Insn emitted into the body of a function to return from a function. |
13577 | ;; This is only done if the function's epilogue is known to be simple. | |
182a4620 | 13578 | ;; See comments for ix86_can_use_return_insn_p in i386.c. |
886c62d1 | 13579 | |
5f3d14e3 | 13580 | (define_expand "return" |
886c62d1 | 13581 | [(return)] |
5f3d14e3 | 13582 | "ix86_can_use_return_insn_p ()" |
9a7372d6 RH |
13583 | { |
13584 | if (current_function_pops_args) | |
13585 | { | |
13586 | rtx popc = GEN_INT (current_function_pops_args); | |
13587 | emit_jump_insn (gen_return_pop_internal (popc)); | |
13588 | DONE; | |
13589 | } | |
0f40f9f7 | 13590 | }) |
5f3d14e3 SC |
13591 | |
13592 | (define_insn "return_internal" | |
13593 | [(return)] | |
13594 | "reload_completed" | |
90aec2cf | 13595 | "ret" |
6ef67412 JH |
13596 | [(set_attr "length" "1") |
13597 | (set_attr "length_immediate" "0") | |
13598 | (set_attr "modrm" "0")]) | |
5f3d14e3 | 13599 | |
6cd96118 SC |
13600 | (define_insn "return_pop_internal" |
13601 | [(return) | |
13602 | (use (match_operand:SI 0 "const_int_operand" ""))] | |
13603 | "reload_completed" | |
0f40f9f7 | 13604 | "ret\t%0" |
6ef67412 JH |
13605 | [(set_attr "length" "3") |
13606 | (set_attr "length_immediate" "2") | |
13607 | (set_attr "modrm" "0")]) | |
6cd96118 | 13608 | |
11837777 RH |
13609 | (define_insn "return_indirect_internal" |
13610 | [(return) | |
13611 | (use (match_operand:SI 0 "register_operand" "r"))] | |
13612 | "reload_completed" | |
0f40f9f7 | 13613 | "jmp\t%A0" |
11837777 RH |
13614 | [(set_attr "type" "ibr") |
13615 | (set_attr "length_immediate" "0")]) | |
13616 | ||
5f3d14e3 SC |
13617 | (define_insn "nop" |
13618 | [(const_int 0)] | |
13619 | "" | |
90aec2cf | 13620 | "nop" |
e075ae69 | 13621 | [(set_attr "length" "1") |
6ef67412 JH |
13622 | (set_attr "length_immediate" "0") |
13623 | (set_attr "modrm" "0") | |
e075ae69 | 13624 | (set_attr "ppro_uops" "one")]) |
5f3d14e3 SC |
13625 | |
13626 | (define_expand "prologue" | |
13627 | [(const_int 1)] | |
13628 | "" | |
e075ae69 | 13629 | "ix86_expand_prologue (); DONE;") |
5f3d14e3 | 13630 | |
e075ae69 | 13631 | (define_insn "prologue_set_got" |
69404d6f | 13632 | [(set (match_operand:SI 0 "register_operand" "=r") |
c76aab11 | 13633 | (unspec_volatile:SI |
e075ae69 RH |
13634 | [(plus:SI (match_dup 0) |
13635 | (plus:SI (match_operand:SI 1 "symbolic_operand" "") | |
13636 | (minus:SI (pc) (match_operand 2 "" ""))))] 1)) | |
13637 | (clobber (reg:CC 17))] | |
32ee7d1d | 13638 | "!TARGET_64BIT" |
47d36400 | 13639 | { |
e075ae69 RH |
13640 | if (GET_CODE (operands[2]) == LABEL_REF) |
13641 | operands[2] = XEXP (operands[2], 0); | |
13642 | if (TARGET_DEEP_BRANCH_PREDICTION) | |
0f40f9f7 | 13643 | return "add{l}\t{%1, %0|%0, %1}"; |
e075ae69 | 13644 | else |
0f40f9f7 ZW |
13645 | return "add{l}\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}"; |
13646 | } | |
6ef67412 | 13647 | [(set_attr "type" "alu") |
d731a1da JH |
13648 | ; Since this insn may have two constant operands, we must set the |
13649 | ; length manually. | |
13650 | (set_attr "length_immediate" "4") | |
6ef67412 | 13651 | (set_attr "mode" "SI")]) |
47d36400 | 13652 | |
e075ae69 | 13653 | (define_insn "prologue_get_pc" |
69404d6f | 13654 | [(set (match_operand:SI 0 "register_operand" "=r") |
c76aab11 | 13655 | (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))] |
1e07edd3 | 13656 | "!TARGET_64BIT" |
886c62d1 | 13657 | { |
e075ae69 RH |
13658 | if (GET_CODE (operands[1]) == LABEL_REF) |
13659 | operands[1] = XEXP (operands[1], 0); | |
0f40f9f7 | 13660 | output_asm_insn ("call\t%X1", operands); |
e075ae69 RH |
13661 | if (! TARGET_DEEP_BRANCH_PREDICTION) |
13662 | { | |
0f40f9f7 | 13663 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", |
e075ae69 RH |
13664 | CODE_LABEL_NUMBER (operands[1])); |
13665 | } | |
13666 | RET; | |
0f40f9f7 | 13667 | } |
e075ae69 | 13668 | [(set_attr "type" "multi")]) |
5f3d14e3 | 13669 | |
e075ae69 RH |
13670 | (define_expand "epilogue" |
13671 | [(const_int 1)] | |
13672 | "" | |
cbbf65e0 RH |
13673 | "ix86_expand_epilogue (1); DONE;") |
13674 | ||
13675 | (define_expand "sibcall_epilogue" | |
13676 | [(const_int 1)] | |
13677 | "" | |
13678 | "ix86_expand_epilogue (0); DONE;") | |
e075ae69 | 13679 | |
1020a5ab RH |
13680 | (define_expand "eh_return" |
13681 | [(use (match_operand 0 "register_operand" "")) | |
13682 | (use (match_operand 1 "register_operand" ""))] | |
13683 | "" | |
1020a5ab RH |
13684 | { |
13685 | rtx tmp, sa = operands[0], ra = operands[1]; | |
13686 | ||
13687 | /* Tricky bit: we write the address of the handler to which we will | |
13688 | be returning into someone else's stack frame, one word below the | |
13689 | stack address we wish to restore. */ | |
13690 | tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa); | |
13691 | tmp = plus_constant (tmp, -UNITS_PER_WORD); | |
13692 | tmp = gen_rtx_MEM (Pmode, tmp); | |
13693 | emit_move_insn (tmp, ra); | |
13694 | ||
d5d6a58b RH |
13695 | if (Pmode == SImode) |
13696 | emit_insn (gen_eh_return_si (sa)); | |
13697 | else | |
13698 | emit_insn (gen_eh_return_di (sa)); | |
1020a5ab RH |
13699 | emit_barrier (); |
13700 | DONE; | |
0f40f9f7 | 13701 | }) |
1020a5ab | 13702 | |
d5d6a58b RH |
13703 | (define_insn_and_split "eh_return_si" |
13704 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")] 13)] | |
1b0c37d7 | 13705 | "!TARGET_64BIT" |
d5d6a58b RH |
13706 | "#" |
13707 | "reload_completed" | |
13708 | [(const_int 1)] | |
13709 | "ix86_expand_epilogue (2); DONE;") | |
13710 | ||
13711 | (define_insn_and_split "eh_return_di" | |
13712 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 13)] | |
1b0c37d7 | 13713 | "TARGET_64BIT" |
1020a5ab RH |
13714 | "#" |
13715 | "reload_completed" | |
13716 | [(const_int 1)] | |
13717 | "ix86_expand_epilogue (2); DONE;") | |
13718 | ||
e075ae69 | 13719 | (define_insn "leave" |
669fe758 | 13720 | [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4))) |
6fc5dc67 | 13721 | (set (reg:SI 6) (mem:SI (reg:SI 6))) |
f2042df3 | 13722 | (clobber (mem:BLK (scratch)))] |
1e07edd3 | 13723 | "!TARGET_64BIT" |
e075ae69 | 13724 | "leave" |
6ef67412 JH |
13725 | [(set_attr "length_immediate" "0") |
13726 | (set_attr "length" "1") | |
13727 | (set_attr "modrm" "0") | |
13728 | (set_attr "modrm" "0") | |
0b5107cf | 13729 | (set_attr "athlon_decode" "vector") |
e075ae69 | 13730 | (set_attr "ppro_uops" "few")]) |
8362f420 JH |
13731 | |
13732 | (define_insn "leave_rex64" | |
f283104b | 13733 | [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8))) |
6fc5dc67 | 13734 | (set (reg:DI 6) (mem:DI (reg:DI 6))) |
f2042df3 | 13735 | (clobber (mem:BLK (scratch)))] |
8362f420 JH |
13736 | "TARGET_64BIT" |
13737 | "leave" | |
13738 | [(set_attr "length_immediate" "0") | |
13739 | (set_attr "length" "1") | |
13740 | (set_attr "modrm" "0") | |
13741 | (set_attr "modrm" "0") | |
13742 | (set_attr "athlon_decode" "vector") | |
13743 | (set_attr "ppro_uops" "few")]) | |
e075ae69 RH |
13744 | \f |
13745 | (define_expand "ffssi2" | |
4cbfbb1b | 13746 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
e075ae69 RH |
13747 | (ffs:SI (match_operand:SI 1 "general_operand" "")))] |
13748 | "" | |
e075ae69 RH |
13749 | { |
13750 | rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode); | |
13751 | rtx in = operands[1]; | |
13752 | ||
13753 | if (TARGET_CMOVE) | |
5f3d14e3 | 13754 | { |
e075ae69 RH |
13755 | emit_move_insn (tmp, constm1_rtx); |
13756 | emit_insn (gen_ffssi_1 (out, in)); | |
13757 | emit_insn (gen_rtx_SET (VOIDmode, out, | |
13758 | gen_rtx_IF_THEN_ELSE (SImode, | |
16189740 | 13759 | gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG), |
e075ae69 RH |
13760 | const0_rtx), |
13761 | tmp, | |
13762 | out))); | |
e0dc26ff JH |
13763 | emit_insn (gen_addsi3 (out, out, const1_rtx)); |
13764 | emit_move_insn (operands[0], out); | |
13765 | } | |
13766 | ||
16189740 RH |
13767 | /* Pentium bsf instruction is extremly slow. The following code is |
13768 | recommended by the Intel Optimizing Manual as a reasonable replacement: | |
e0dc26ff JH |
13769 | TEST EAX,EAX |
13770 | JZ SHORT BS2 | |
13771 | XOR ECX,ECX | |
13772 | MOV DWORD PTR [TEMP+4],ECX | |
13773 | SUB ECX,EAX | |
13774 | AND EAX,ECX | |
13775 | MOV DWORD PTR [TEMP],EAX | |
13776 | FILD QWORD PTR [TEMP] | |
13777 | FSTP QWORD PTR [TEMP] | |
13778 | WAIT ; WAIT only needed for compatibility with | |
13779 | ; earlier processors | |
13780 | MOV ECX, DWORD PTR [TEMP+4] | |
13781 | SHR ECX,20 | |
13782 | SUB ECX,3FFH | |
13783 | TEST EAX,EAX ; clear zero flag | |
13784 | BS2: | |
13785 | Following piece of code expand ffs to similar beast. | |
13786 | */ | |
13787 | ||
13788 | else if (TARGET_PENTIUM && !optimize_size && TARGET_80387) | |
13789 | { | |
13790 | rtx label = gen_label_rtx (); | |
13791 | rtx lo, hi; | |
13792 | rtx mem = assign_386_stack_local (DImode, 0); | |
13793 | rtx fptmp = gen_reg_rtx (DFmode); | |
13794 | split_di (&mem, 1, &lo, &hi); | |
13795 | ||
13796 | emit_move_insn (out, const0_rtx); | |
13797 | ||
e790b36a | 13798 | emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, label); |
e0dc26ff JH |
13799 | |
13800 | emit_move_insn (hi, out); | |
13801 | emit_insn (gen_subsi3 (out, out, in)); | |
13802 | emit_insn (gen_andsi3 (out, out, in)); | |
13803 | emit_move_insn (lo, out); | |
13804 | emit_insn (gen_floatdidf2 (fptmp,mem)); | |
13805 | emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp); | |
13806 | emit_move_insn (out, hi); | |
13807 | emit_insn (gen_lshrsi3 (out, out, GEN_INT (20))); | |
16189740 | 13808 | emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1))); |
e0dc26ff JH |
13809 | |
13810 | emit_label (label); | |
13811 | LABEL_NUSES (label) = 1; | |
13812 | ||
13813 | emit_move_insn (operands[0], out); | |
5f3d14e3 | 13814 | } |
e075ae69 | 13815 | else |
5f3d14e3 | 13816 | { |
e075ae69 RH |
13817 | emit_move_insn (tmp, const0_rtx); |
13818 | emit_insn (gen_ffssi_1 (out, in)); | |
13819 | emit_insn (gen_rtx_SET (VOIDmode, | |
13820 | gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)), | |
16189740 | 13821 | gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG), |
e075ae69 RH |
13822 | const0_rtx))); |
13823 | emit_insn (gen_negsi2 (tmp, tmp)); | |
13824 | emit_insn (gen_iorsi3 (out, out, tmp)); | |
e0dc26ff JH |
13825 | emit_insn (gen_addsi3 (out, out, const1_rtx)); |
13826 | emit_move_insn (operands[0], out); | |
e075ae69 | 13827 | } |
e075ae69 | 13828 | DONE; |
0f40f9f7 | 13829 | }) |
886c62d1 | 13830 | |
e075ae69 | 13831 | (define_insn "ffssi_1" |
16189740 RH |
13832 | [(set (reg:CCZ 17) |
13833 | (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm") | |
13834 | (const_int 0))) | |
e075ae69 RH |
13835 | (set (match_operand:SI 0 "register_operand" "=r") |
13836 | (unspec:SI [(match_dup 1)] 5))] | |
13837 | "" | |
0f40f9f7 | 13838 | "bsf{l}\t{%1, %0|%0, %1}" |
6ef67412 | 13839 | [(set_attr "prefix_0f" "1") |
e075ae69 RH |
13840 | (set_attr "ppro_uops" "few")]) |
13841 | ||
13842 | ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger | |
13843 | ;; and slower than the two-byte movzx insn needed to do the work in SImode. | |
13844 | \f | |
13845 | ;; These patterns match the binary 387 instructions for addM3, subM3, | |
13846 | ;; mulM3 and divM3. There are three patterns for each of DFmode and | |
13847 | ;; SFmode. The first is the normal insn, the second the same insn but | |
13848 | ;; with one operand a conversion, and the third the same insn but with | |
13849 | ;; the other operand a conversion. The conversion may be SFmode or | |
13850 | ;; SImode if the target mode DFmode, but only SImode if the target mode | |
13851 | ;; is SFmode. | |
13852 | ||
caa6ec8d JH |
13853 | ;; Gcc is slightly more smart about handling normal two address instructions |
13854 | ;; so use special patterns for add and mull. | |
965f5423 JH |
13855 | (define_insn "*fop_sf_comm_nosse" |
13856 | [(set (match_operand:SF 0 "register_operand" "=f") | |
13857 | (match_operator:SF 3 "binary_fp_operator" | |
13858 | [(match_operand:SF 1 "register_operand" "%0") | |
13859 | (match_operand:SF 2 "nonimmediate_operand" "fm")]))] | |
13860 | "TARGET_80387 && !TARGET_SSE_MATH | |
13861 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" | |
13862 | "* return output_387_binary_op (insn, operands);" | |
13863 | [(set (attr "type") | |
13864 | (if_then_else (match_operand:SF 3 "mult_operator" "") | |
13865 | (const_string "fmul") | |
13866 | (const_string "fop"))) | |
13867 | (set_attr "mode" "SF")]) | |
13868 | ||
caa6ec8d | 13869 | (define_insn "*fop_sf_comm" |
1deaa899 | 13870 | [(set (match_operand:SF 0 "register_operand" "=f#x,x#f") |
caa6ec8d | 13871 | (match_operator:SF 3 "binary_fp_operator" |
1deaa899 JH |
13872 | [(match_operand:SF 1 "register_operand" "%0,0") |
13873 | (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))] | |
965f5423 | 13874 | "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 |
1deaa899 | 13875 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" |
caa6ec8d JH |
13876 | "* return output_387_binary_op (insn, operands);" |
13877 | [(set (attr "type") | |
1deaa899 JH |
13878 | (if_then_else (eq_attr "alternative" "1") |
13879 | (const_string "sse") | |
13880 | (if_then_else (match_operand:SF 3 "mult_operator" "") | |
13881 | (const_string "fmul") | |
13882 | (const_string "fop")))) | |
13883 | (set_attr "mode" "SF")]) | |
13884 | ||
13885 | (define_insn "*fop_sf_comm_sse" | |
13886 | [(set (match_operand:SF 0 "register_operand" "=x") | |
13887 | (match_operator:SF 3 "binary_fp_operator" | |
13888 | [(match_operand:SF 1 "register_operand" "%0") | |
13889 | (match_operand:SF 2 "nonimmediate_operand" "xm")]))] | |
965f5423 | 13890 | "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" |
1deaa899 JH |
13891 | "* return output_387_binary_op (insn, operands);" |
13892 | [(set_attr "type" "sse") | |
6ef67412 | 13893 | (set_attr "mode" "SF")]) |
caa6ec8d | 13894 | |
965f5423 JH |
13895 | (define_insn "*fop_df_comm_nosse" |
13896 | [(set (match_operand:DF 0 "register_operand" "=f") | |
13897 | (match_operator:DF 3 "binary_fp_operator" | |
13898 | [(match_operand:DF 1 "register_operand" "%0") | |
13899 | (match_operand:DF 2 "nonimmediate_operand" "fm")]))] | |
13900 | "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) | |
13901 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" | |
13902 | "* return output_387_binary_op (insn, operands);" | |
13903 | [(set (attr "type") | |
13904 | (if_then_else (match_operand:SF 3 "mult_operator" "") | |
13905 | (const_string "fmul") | |
13906 | (const_string "fop"))) | |
13907 | (set_attr "mode" "DF")]) | |
13908 | ||
caa6ec8d | 13909 | (define_insn "*fop_df_comm" |
1deaa899 | 13910 | [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") |
caa6ec8d | 13911 | (match_operator:DF 3 "binary_fp_operator" |
1deaa899 JH |
13912 | [(match_operand:DF 1 "register_operand" "%0,0") |
13913 | (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))] | |
965f5423 | 13914 | "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387 |
1deaa899 | 13915 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" |
caa6ec8d JH |
13916 | "* return output_387_binary_op (insn, operands);" |
13917 | [(set (attr "type") | |
1deaa899 JH |
13918 | (if_then_else (eq_attr "alternative" "1") |
13919 | (const_string "sse") | |
13920 | (if_then_else (match_operand:SF 3 "mult_operator" "") | |
13921 | (const_string "fmul") | |
13922 | (const_string "fop")))) | |
13923 | (set_attr "mode" "DF")]) | |
13924 | ||
13925 | (define_insn "*fop_df_comm_sse" | |
13926 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
13927 | (match_operator:DF 3 "binary_fp_operator" | |
13928 | [(match_operand:DF 1 "register_operand" "%0") | |
13929 | (match_operand:DF 2 "nonimmediate_operand" "Ym")]))] | |
965f5423 | 13930 | "TARGET_SSE2 && TARGET_SSE_MATH |
1deaa899 JH |
13931 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" |
13932 | "* return output_387_binary_op (insn, operands);" | |
13933 | [(set_attr "type" "sse") | |
6ef67412 | 13934 | (set_attr "mode" "DF")]) |
caa6ec8d JH |
13935 | |
13936 | (define_insn "*fop_xf_comm" | |
13937 | [(set (match_operand:XF 0 "register_operand" "=f") | |
13938 | (match_operator:XF 3 "binary_fp_operator" | |
13939 | [(match_operand:XF 1 "register_operand" "%0") | |
13940 | (match_operand:XF 2 "register_operand" "f")]))] | |
1b0c37d7 | 13941 | "!TARGET_64BIT && TARGET_80387 |
1e07edd3 | 13942 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" |
caa6ec8d JH |
13943 | "* return output_387_binary_op (insn, operands);" |
13944 | [(set (attr "type") | |
13945 | (if_then_else (match_operand:XF 3 "mult_operator" "") | |
13946 | (const_string "fmul") | |
6ef67412 JH |
13947 | (const_string "fop"))) |
13948 | (set_attr "mode" "XF")]) | |
caa6ec8d | 13949 | |
2b589241 JH |
13950 | (define_insn "*fop_tf_comm" |
13951 | [(set (match_operand:TF 0 "register_operand" "=f") | |
13952 | (match_operator:TF 3 "binary_fp_operator" | |
13953 | [(match_operand:TF 1 "register_operand" "%0") | |
13954 | (match_operand:TF 2 "register_operand" "f")]))] | |
13955 | "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" | |
13956 | "* return output_387_binary_op (insn, operands);" | |
13957 | [(set (attr "type") | |
13958 | (if_then_else (match_operand:TF 3 "mult_operator" "") | |
13959 | (const_string "fmul") | |
13960 | (const_string "fop"))) | |
13961 | (set_attr "mode" "XF")]) | |
13962 | ||
965f5423 JH |
13963 | (define_insn "*fop_sf_1_nosse" |
13964 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
13965 | (match_operator:SF 3 "binary_fp_operator" | |
13966 | [(match_operand:SF 1 "nonimmediate_operand" "0,fm") | |
13967 | (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))] | |
13968 | "TARGET_80387 && !TARGET_SSE_MATH | |
13969 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' | |
13970 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
13971 | "* return output_387_binary_op (insn, operands);" | |
13972 | [(set (attr "type") | |
13973 | (cond [(match_operand:SF 3 "mult_operator" "") | |
13974 | (const_string "fmul") | |
13975 | (match_operand:SF 3 "div_operator" "") | |
13976 | (const_string "fdiv") | |
13977 | ] | |
13978 | (const_string "fop"))) | |
13979 | (set_attr "mode" "SF")]) | |
13980 | ||
e075ae69 | 13981 | (define_insn "*fop_sf_1" |
1deaa899 | 13982 | [(set (match_operand:SF 0 "register_operand" "=f,f,x") |
e075ae69 | 13983 | (match_operator:SF 3 "binary_fp_operator" |
1deaa899 JH |
13984 | [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0") |
13985 | (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))] | |
965f5423 | 13986 | "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 |
caa6ec8d | 13987 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' |
f97d9ec3 | 13988 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
e075ae69 RH |
13989 | "* return output_387_binary_op (insn, operands);" |
13990 | [(set (attr "type") | |
1deaa899 JH |
13991 | (cond [(eq_attr "alternative" "2") |
13992 | (const_string "sse") | |
13993 | (match_operand:SF 3 "mult_operator" "") | |
e075ae69 RH |
13994 | (const_string "fmul") |
13995 | (match_operand:SF 3 "div_operator" "") | |
13996 | (const_string "fdiv") | |
13997 | ] | |
6ef67412 JH |
13998 | (const_string "fop"))) |
13999 | (set_attr "mode" "SF")]) | |
e075ae69 | 14000 | |
1deaa899 JH |
14001 | (define_insn "*fop_sf_1_sse" |
14002 | [(set (match_operand:SF 0 "register_operand" "=x") | |
14003 | (match_operator:SF 3 "binary_fp_operator" | |
14004 | [(match_operand:SF 1 "register_operand" "0") | |
14005 | (match_operand:SF 2 "nonimmediate_operand" "xm")]))] | |
965f5423 | 14006 | "TARGET_SSE_MATH |
1deaa899 JH |
14007 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" |
14008 | "* return output_387_binary_op (insn, operands);" | |
14009 | [(set_attr "type" "sse") | |
14010 | (set_attr "mode" "SF")]) | |
14011 | ||
14012 | ;; ??? Add SSE splitters for these! | |
e075ae69 RH |
14013 | (define_insn "*fop_sf_2" |
14014 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
14015 | (match_operator:SF 3 "binary_fp_operator" | |
14016 | [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) | |
14017 | (match_operand:SF 2 "register_operand" "0,0")]))] | |
965f5423 | 14018 | "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH" |
e075ae69 RH |
14019 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14020 | [(set (attr "type") | |
14021 | (cond [(match_operand:SF 3 "mult_operator" "") | |
14022 | (const_string "fmul") | |
14023 | (match_operand:SF 3 "div_operator" "") | |
14024 | (const_string "fdiv") | |
14025 | ] | |
14026 | (const_string "fop"))) | |
14027 | (set_attr "fp_int_src" "true") | |
6ef67412 JH |
14028 | (set_attr "ppro_uops" "many") |
14029 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
14030 | |
14031 | (define_insn "*fop_sf_3" | |
14032 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
14033 | (match_operator:SF 3 "binary_fp_operator" | |
14034 | [(match_operand:SF 1 "register_operand" "0,0") | |
14035 | (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] | |
965f5423 | 14036 | "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH" |
e075ae69 RH |
14037 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14038 | [(set (attr "type") | |
14039 | (cond [(match_operand:SF 3 "mult_operator" "") | |
14040 | (const_string "fmul") | |
14041 | (match_operand:SF 3 "div_operator" "") | |
14042 | (const_string "fdiv") | |
14043 | ] | |
14044 | (const_string "fop"))) | |
14045 | (set_attr "fp_int_src" "true") | |
6ef67412 JH |
14046 | (set_attr "ppro_uops" "many") |
14047 | (set_attr "mode" "SI")]) | |
e075ae69 | 14048 | |
965f5423 JH |
14049 | (define_insn "*fop_df_1_nosse" |
14050 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14051 | (match_operator:DF 3 "binary_fp_operator" | |
14052 | [(match_operand:DF 1 "nonimmediate_operand" "0,fm") | |
14053 | (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))] | |
14054 | "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) | |
14055 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' | |
14056 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
14057 | "* return output_387_binary_op (insn, operands);" | |
14058 | [(set (attr "type") | |
14059 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14060 | (const_string "fmul") | |
14061 | (match_operand:DF 3 "div_operator" "") | |
14062 | (const_string "fdiv") | |
14063 | ] | |
14064 | (const_string "fop"))) | |
14065 | (set_attr "mode" "DF")]) | |
14066 | ||
14067 | ||
e075ae69 | 14068 | (define_insn "*fop_df_1" |
1deaa899 | 14069 | [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f") |
e075ae69 | 14070 | (match_operator:DF 3 "binary_fp_operator" |
1deaa899 JH |
14071 | [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0") |
14072 | (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))] | |
965f5423 | 14073 | "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 |
caa6ec8d | 14074 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' |
f97d9ec3 | 14075 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
e075ae69 RH |
14076 | "* return output_387_binary_op (insn, operands);" |
14077 | [(set (attr "type") | |
1deaa899 JH |
14078 | (cond [(eq_attr "alternative" "2") |
14079 | (const_string "sse") | |
14080 | (match_operand:DF 3 "mult_operator" "") | |
e075ae69 RH |
14081 | (const_string "fmul") |
14082 | (match_operand:DF 3 "div_operator" "") | |
14083 | (const_string "fdiv") | |
14084 | ] | |
6ef67412 JH |
14085 | (const_string "fop"))) |
14086 | (set_attr "mode" "DF")]) | |
e075ae69 | 14087 | |
1deaa899 JH |
14088 | (define_insn "*fop_df_1_sse" |
14089 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
14090 | (match_operator:DF 3 "binary_fp_operator" | |
14091 | [(match_operand:DF 1 "register_operand" "0") | |
14092 | (match_operand:DF 2 "nonimmediate_operand" "Ym")]))] | |
965f5423 | 14093 | "TARGET_SSE2 && TARGET_SSE_MATH |
1deaa899 JH |
14094 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" |
14095 | "* return output_387_binary_op (insn, operands);" | |
14096 | [(set_attr "type" "sse")]) | |
14097 | ||
14098 | ;; ??? Add SSE splitters for these! | |
e075ae69 RH |
14099 | (define_insn "*fop_df_2" |
14100 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14101 | (match_operator:DF 3 "binary_fp_operator" | |
14102 | [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) | |
14103 | (match_operand:DF 2 "register_operand" "0,0")]))] | |
965f5423 | 14104 | "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)" |
e075ae69 RH |
14105 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14106 | [(set (attr "type") | |
14107 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14108 | (const_string "fmul") | |
14109 | (match_operand:DF 3 "div_operator" "") | |
14110 | (const_string "fdiv") | |
14111 | ] | |
14112 | (const_string "fop"))) | |
14113 | (set_attr "fp_int_src" "true") | |
6ef67412 JH |
14114 | (set_attr "ppro_uops" "many") |
14115 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
14116 | |
14117 | (define_insn "*fop_df_3" | |
14118 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14119 | (match_operator:DF 3 "binary_fp_operator" | |
14120 | [(match_operand:DF 1 "register_operand" "0,0") | |
14121 | (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] | |
965f5423 | 14122 | "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)" |
e075ae69 RH |
14123 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14124 | [(set (attr "type") | |
14125 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14126 | (const_string "fmul") | |
14127 | (match_operand:DF 3 "div_operator" "") | |
14128 | (const_string "fdiv") | |
14129 | ] | |
14130 | (const_string "fop"))) | |
14131 | (set_attr "fp_int_src" "true") | |
6ef67412 JH |
14132 | (set_attr "ppro_uops" "many") |
14133 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
14134 | |
14135 | (define_insn "*fop_df_4" | |
14136 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14137 | (match_operator:DF 3 "binary_fp_operator" | |
14138 | [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) | |
14139 | (match_operand:DF 2 "register_operand" "0,f")]))] | |
3987b9db | 14140 | "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) |
f97d9ec3 | 14141 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
e075ae69 RH |
14142 | "* return output_387_binary_op (insn, operands);" |
14143 | [(set (attr "type") | |
14144 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14145 | (const_string "fmul") | |
14146 | (match_operand:DF 3 "div_operator" "") | |
14147 | (const_string "fdiv") | |
14148 | ] | |
6ef67412 JH |
14149 | (const_string "fop"))) |
14150 | (set_attr "mode" "SF")]) | |
e075ae69 RH |
14151 | |
14152 | (define_insn "*fop_df_5" | |
14153 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14154 | (match_operator:DF 3 "binary_fp_operator" | |
14155 | [(match_operand:DF 1 "register_operand" "0,f") | |
14156 | (float_extend:DF | |
14157 | (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] | |
965f5423 | 14158 | "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)" |
e075ae69 RH |
14159 | "* return output_387_binary_op (insn, operands);" |
14160 | [(set (attr "type") | |
14161 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14162 | (const_string "fmul") | |
14163 | (match_operand:DF 3 "div_operator" "") | |
14164 | (const_string "fdiv") | |
14165 | ] | |
6ef67412 JH |
14166 | (const_string "fop"))) |
14167 | (set_attr "mode" "SF")]) | |
e075ae69 RH |
14168 | |
14169 | (define_insn "*fop_xf_1" | |
14170 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14171 | (match_operator:XF 3 "binary_fp_operator" | |
14172 | [(match_operand:XF 1 "register_operand" "0,f") | |
14173 | (match_operand:XF 2 "register_operand" "f,0")]))] | |
1b0c37d7 | 14174 | "!TARGET_64BIT && TARGET_80387 |
caa6ec8d | 14175 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" |
e075ae69 RH |
14176 | "* return output_387_binary_op (insn, operands);" |
14177 | [(set (attr "type") | |
ca285e07 | 14178 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14179 | (const_string "fmul") |
ca285e07 | 14180 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14181 | (const_string "fdiv") |
14182 | ] | |
6ef67412 JH |
14183 | (const_string "fop"))) |
14184 | (set_attr "mode" "XF")]) | |
e075ae69 | 14185 | |
2b589241 JH |
14186 | (define_insn "*fop_tf_1" |
14187 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14188 | (match_operator:TF 3 "binary_fp_operator" | |
14189 | [(match_operand:TF 1 "register_operand" "0,f") | |
14190 | (match_operand:TF 2 "register_operand" "f,0")]))] | |
14191 | "TARGET_80387 | |
14192 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" | |
14193 | "* return output_387_binary_op (insn, operands);" | |
14194 | [(set (attr "type") | |
14195 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14196 | (const_string "fmul") | |
14197 | (match_operand:TF 3 "div_operator" "") | |
14198 | (const_string "fdiv") | |
14199 | ] | |
14200 | (const_string "fop"))) | |
14201 | (set_attr "mode" "XF")]) | |
14202 | ||
e075ae69 RH |
14203 | (define_insn "*fop_xf_2" |
14204 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14205 | (match_operator:XF 3 "binary_fp_operator" | |
14206 | [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) | |
14207 | (match_operand:XF 2 "register_operand" "0,0")]))] | |
1b0c37d7 | 14208 | "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP" |
e075ae69 RH |
14209 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14210 | [(set (attr "type") | |
ca285e07 | 14211 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14212 | (const_string "fmul") |
ca285e07 | 14213 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14214 | (const_string "fdiv") |
14215 | ] | |
14216 | (const_string "fop"))) | |
14217 | (set_attr "fp_int_src" "true") | |
6ef67412 | 14218 | (set_attr "mode" "SI") |
e075ae69 RH |
14219 | (set_attr "ppro_uops" "many")]) |
14220 | ||
2b589241 JH |
14221 | (define_insn "*fop_tf_2" |
14222 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14223 | (match_operator:TF 3 "binary_fp_operator" | |
14224 | [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) | |
14225 | (match_operand:TF 2 "register_operand" "0,0")]))] | |
14226 | "TARGET_80387 && TARGET_USE_FIOP" | |
14227 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" | |
14228 | [(set (attr "type") | |
14229 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14230 | (const_string "fmul") | |
14231 | (match_operand:TF 3 "div_operator" "") | |
14232 | (const_string "fdiv") | |
14233 | ] | |
14234 | (const_string "fop"))) | |
14235 | (set_attr "fp_int_src" "true") | |
14236 | (set_attr "mode" "SI") | |
14237 | (set_attr "ppro_uops" "many")]) | |
14238 | ||
e075ae69 RH |
14239 | (define_insn "*fop_xf_3" |
14240 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14241 | (match_operator:XF 3 "binary_fp_operator" | |
14242 | [(match_operand:XF 1 "register_operand" "0,0") | |
14243 | (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] | |
1b0c37d7 | 14244 | "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP" |
e075ae69 RH |
14245 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14246 | [(set (attr "type") | |
ca285e07 | 14247 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14248 | (const_string "fmul") |
ca285e07 | 14249 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14250 | (const_string "fdiv") |
14251 | ] | |
14252 | (const_string "fop"))) | |
14253 | (set_attr "fp_int_src" "true") | |
6ef67412 | 14254 | (set_attr "mode" "SI") |
e075ae69 RH |
14255 | (set_attr "ppro_uops" "many")]) |
14256 | ||
2b589241 JH |
14257 | (define_insn "*fop_tf_3" |
14258 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14259 | (match_operator:TF 3 "binary_fp_operator" | |
14260 | [(match_operand:TF 1 "register_operand" "0,0") | |
14261 | (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] | |
14262 | "TARGET_80387 && TARGET_USE_FIOP" | |
14263 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" | |
14264 | [(set (attr "type") | |
14265 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14266 | (const_string "fmul") | |
14267 | (match_operand:TF 3 "div_operator" "") | |
14268 | (const_string "fdiv") | |
14269 | ] | |
14270 | (const_string "fop"))) | |
14271 | (set_attr "fp_int_src" "true") | |
14272 | (set_attr "mode" "SI") | |
14273 | (set_attr "ppro_uops" "many")]) | |
14274 | ||
e075ae69 RH |
14275 | (define_insn "*fop_xf_4" |
14276 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14277 | (match_operator:XF 3 "binary_fp_operator" | |
14278 | [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) | |
14279 | (match_operand:XF 2 "register_operand" "0,f")]))] | |
1b0c37d7 | 14280 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
14281 | "* return output_387_binary_op (insn, operands);" |
14282 | [(set (attr "type") | |
ca285e07 | 14283 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14284 | (const_string "fmul") |
ca285e07 | 14285 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14286 | (const_string "fdiv") |
14287 | ] | |
6ef67412 JH |
14288 | (const_string "fop"))) |
14289 | (set_attr "mode" "SF")]) | |
e075ae69 | 14290 | |
2b589241 JH |
14291 | (define_insn "*fop_tf_4" |
14292 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14293 | (match_operator:TF 3 "binary_fp_operator" | |
14294 | [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) | |
14295 | (match_operand:TF 2 "register_operand" "0,f")]))] | |
14296 | "TARGET_80387" | |
14297 | "* return output_387_binary_op (insn, operands);" | |
14298 | [(set (attr "type") | |
14299 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14300 | (const_string "fmul") | |
14301 | (match_operand:TF 3 "div_operator" "") | |
14302 | (const_string "fdiv") | |
14303 | ] | |
14304 | (const_string "fop"))) | |
14305 | (set_attr "mode" "SF")]) | |
14306 | ||
e075ae69 RH |
14307 | (define_insn "*fop_xf_5" |
14308 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14309 | (match_operator:XF 3 "binary_fp_operator" | |
14310 | [(match_operand:XF 1 "register_operand" "0,f") | |
14311 | (float_extend:XF | |
14312 | (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] | |
1b0c37d7 | 14313 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
14314 | "* return output_387_binary_op (insn, operands);" |
14315 | [(set (attr "type") | |
ca285e07 | 14316 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14317 | (const_string "fmul") |
ca285e07 | 14318 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14319 | (const_string "fdiv") |
14320 | ] | |
6ef67412 JH |
14321 | (const_string "fop"))) |
14322 | (set_attr "mode" "SF")]) | |
e075ae69 | 14323 | |
2b589241 JH |
14324 | (define_insn "*fop_tf_5" |
14325 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14326 | (match_operator:TF 3 "binary_fp_operator" | |
14327 | [(match_operand:TF 1 "register_operand" "0,f") | |
14328 | (float_extend:TF | |
14329 | (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] | |
14330 | "TARGET_80387" | |
14331 | "* return output_387_binary_op (insn, operands);" | |
14332 | [(set (attr "type") | |
14333 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14334 | (const_string "fmul") | |
14335 | (match_operand:TF 3 "div_operator" "") | |
14336 | (const_string "fdiv") | |
14337 | ] | |
14338 | (const_string "fop"))) | |
14339 | (set_attr "mode" "SF")]) | |
14340 | ||
e075ae69 RH |
14341 | (define_insn "*fop_xf_6" |
14342 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14343 | (match_operator:XF 3 "binary_fp_operator" | |
14344 | [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0")) | |
14345 | (match_operand:XF 2 "register_operand" "0,f")]))] | |
1b0c37d7 | 14346 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
14347 | "* return output_387_binary_op (insn, operands);" |
14348 | [(set (attr "type") | |
ca285e07 | 14349 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14350 | (const_string "fmul") |
ca285e07 | 14351 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14352 | (const_string "fdiv") |
14353 | ] | |
6ef67412 JH |
14354 | (const_string "fop"))) |
14355 | (set_attr "mode" "DF")]) | |
e075ae69 | 14356 | |
2b589241 JH |
14357 | (define_insn "*fop_tf_6" |
14358 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14359 | (match_operator:TF 3 "binary_fp_operator" | |
14360 | [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0")) | |
14361 | (match_operand:TF 2 "register_operand" "0,f")]))] | |
14362 | "TARGET_80387" | |
14363 | "* return output_387_binary_op (insn, operands);" | |
14364 | [(set (attr "type") | |
14365 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14366 | (const_string "fmul") | |
14367 | (match_operand:TF 3 "div_operator" "") | |
14368 | (const_string "fdiv") | |
14369 | ] | |
14370 | (const_string "fop"))) | |
14371 | (set_attr "mode" "DF")]) | |
14372 | ||
e075ae69 RH |
14373 | (define_insn "*fop_xf_7" |
14374 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14375 | (match_operator:XF 3 "binary_fp_operator" | |
14376 | [(match_operand:XF 1 "register_operand" "0,f") | |
14377 | (float_extend:XF | |
14378 | (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))] | |
1b0c37d7 | 14379 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
14380 | "* return output_387_binary_op (insn, operands);" |
14381 | [(set (attr "type") | |
ca285e07 | 14382 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14383 | (const_string "fmul") |
ca285e07 | 14384 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14385 | (const_string "fdiv") |
14386 | ] | |
6ef67412 JH |
14387 | (const_string "fop"))) |
14388 | (set_attr "mode" "DF")]) | |
e075ae69 | 14389 | |
2b589241 JH |
14390 | (define_insn "*fop_tf_7" |
14391 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14392 | (match_operator:TF 3 "binary_fp_operator" | |
14393 | [(match_operand:TF 1 "register_operand" "0,f") | |
14394 | (float_extend:TF | |
14395 | (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))] | |
14396 | "TARGET_80387" | |
14397 | "* return output_387_binary_op (insn, operands);" | |
14398 | [(set (attr "type") | |
14399 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14400 | (const_string "fmul") | |
14401 | (match_operand:TF 3 "div_operator" "") | |
14402 | (const_string "fdiv") | |
14403 | ] | |
14404 | (const_string "fop"))) | |
14405 | (set_attr "mode" "DF")]) | |
14406 | ||
e075ae69 RH |
14407 | (define_split |
14408 | [(set (match_operand 0 "register_operand" "") | |
14409 | (match_operator 3 "binary_fp_operator" | |
14410 | [(float (match_operand:SI 1 "register_operand" "")) | |
14411 | (match_operand 2 "register_operand" "")]))] | |
14412 | "TARGET_80387 && reload_completed | |
14413 | && FLOAT_MODE_P (GET_MODE (operands[0]))" | |
4211a8fb | 14414 | [(const_int 0)] |
4211a8fb JH |
14415 | { |
14416 | operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]); | |
14417 | operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]); | |
14418 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
14419 | gen_rtx_fmt_ee (GET_CODE (operands[3]), | |
14420 | GET_MODE (operands[3]), | |
14421 | operands[4], | |
14422 | operands[2]))); | |
14423 | ix86_free_from_memory (GET_MODE (operands[1])); | |
14424 | DONE; | |
0f40f9f7 | 14425 | }) |
e075ae69 RH |
14426 | |
14427 | (define_split | |
14428 | [(set (match_operand 0 "register_operand" "") | |
14429 | (match_operator 3 "binary_fp_operator" | |
14430 | [(match_operand 1 "register_operand" "") | |
14431 | (float (match_operand:SI 2 "register_operand" ""))]))] | |
14432 | "TARGET_80387 && reload_completed | |
14433 | && FLOAT_MODE_P (GET_MODE (operands[0]))" | |
4211a8fb | 14434 | [(const_int 0)] |
4211a8fb JH |
14435 | { |
14436 | operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]); | |
14437 | operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]); | |
14438 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2b66da3c | 14439 | gen_rtx_fmt_ee (GET_CODE (operands[3]), |
4211a8fb JH |
14440 | GET_MODE (operands[3]), |
14441 | operands[1], | |
14442 | operands[4]))); | |
14443 | ix86_free_from_memory (GET_MODE (operands[2])); | |
14444 | DONE; | |
0f40f9f7 | 14445 | }) |
e075ae69 RH |
14446 | \f |
14447 | ;; FPU special functions. | |
14448 | ||
a8083431 JH |
14449 | (define_expand "sqrtsf2" |
14450 | [(set (match_operand:SF 0 "register_operand" "") | |
14451 | (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
abf80f8f | 14452 | "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH" |
a8083431 | 14453 | { |
abf80f8f | 14454 | if (!TARGET_SSE_MATH) |
a8083431 | 14455 | operands[1] = force_reg (SFmode, operands[1]); |
0f40f9f7 | 14456 | }) |
a8083431 JH |
14457 | |
14458 | (define_insn "sqrtsf2_1" | |
ca9a9b12 JH |
14459 | [(set (match_operand:SF 0 "register_operand" "=f#x,x#f") |
14460 | (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))] | |
a8083431 | 14461 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
abf80f8f | 14462 | && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" |
a8083431 JH |
14463 | "@ |
14464 | fsqrt | |
0f40f9f7 | 14465 | sqrtss\t{%1, %0|%0, %1}" |
a8083431 JH |
14466 | [(set_attr "type" "fpspc,sse") |
14467 | (set_attr "mode" "SF,SF") | |
14468 | (set_attr "athlon_decode" "direct,*")]) | |
14469 | ||
14470 | (define_insn "sqrtsf2_1_sse_only" | |
ca9a9b12 JH |
14471 | [(set (match_operand:SF 0 "register_operand" "=x") |
14472 | (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))] | |
abf80f8f | 14473 | "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)" |
0f40f9f7 | 14474 | "sqrtss\t{%1, %0|%0, %1}" |
a8083431 JH |
14475 | [(set_attr "type" "sse") |
14476 | (set_attr "mode" "SF") | |
14477 | (set_attr "athlon_decode" "*")]) | |
14478 | ||
14479 | (define_insn "sqrtsf2_i387" | |
e075ae69 RH |
14480 | [(set (match_operand:SF 0 "register_operand" "=f") |
14481 | (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] | |
a8083431 | 14482 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
abf80f8f | 14483 | && !TARGET_SSE_MATH" |
e075ae69 | 14484 | "fsqrt" |
0b5107cf | 14485 | [(set_attr "type" "fpspc") |
6ef67412 | 14486 | (set_attr "mode" "SF") |
0b5107cf | 14487 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14488 | |
a8083431 JH |
14489 | (define_expand "sqrtdf2" |
14490 | [(set (match_operand:DF 0 "register_operand" "") | |
14491 | (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))] | |
965f5423 JH |
14492 | "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) |
14493 | || (TARGET_SSE2 && TARGET_SSE_MATH)" | |
a8083431 | 14494 | { |
965f5423 | 14495 | if (!TARGET_SSE2 || !TARGET_SSE_MATH) |
2406cfed | 14496 | operands[1] = force_reg (DFmode, operands[1]); |
0f40f9f7 | 14497 | }) |
a8083431 JH |
14498 | |
14499 | (define_insn "sqrtdf2_1" | |
14500 | [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") | |
14501 | (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))] | |
14502 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 | |
965f5423 | 14503 | && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" |
a8083431 JH |
14504 | "@ |
14505 | fsqrt | |
0f40f9f7 | 14506 | sqrtsd\t{%1, %0|%0, %1}" |
a8083431 JH |
14507 | [(set_attr "type" "fpspc,sse") |
14508 | (set_attr "mode" "DF,DF") | |
14509 | (set_attr "athlon_decode" "direct,*")]) | |
14510 | ||
14511 | (define_insn "sqrtdf2_1_sse_only" | |
14512 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
14513 | (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))] | |
965f5423 | 14514 | "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)" |
0f40f9f7 | 14515 | "sqrtsd\t{%1, %0|%0, %1}" |
a8083431 JH |
14516 | [(set_attr "type" "sse") |
14517 | (set_attr "mode" "DF") | |
14518 | (set_attr "athlon_decode" "*")]) | |
14519 | ||
14520 | (define_insn "sqrtdf2_i387" | |
e075ae69 RH |
14521 | [(set (match_operand:DF 0 "register_operand" "=f") |
14522 | (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] | |
14523 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 | |
abf80f8f | 14524 | && (!TARGET_SSE2 || !TARGET_SSE_MATH)" |
e075ae69 | 14525 | "fsqrt" |
0b5107cf | 14526 | [(set_attr "type" "fpspc") |
6ef67412 | 14527 | (set_attr "mode" "DF") |
0b5107cf | 14528 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14529 | |
6343a50e | 14530 | (define_insn "*sqrtextendsfdf2" |
e075ae69 RH |
14531 | [(set (match_operand:DF 0 "register_operand" "=f") |
14532 | (sqrt:DF (float_extend:DF | |
14533 | (match_operand:SF 1 "register_operand" "0"))))] | |
965f5423 JH |
14534 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14535 | && !(TARGET_SSE2 && TARGET_SSE_MATH)" | |
e075ae69 | 14536 | "fsqrt" |
0b5107cf | 14537 | [(set_attr "type" "fpspc") |
6ef67412 | 14538 | (set_attr "mode" "DF") |
0b5107cf | 14539 | (set_attr "athlon_decode" "direct")]) |
e075ae69 RH |
14540 | |
14541 | (define_insn "sqrtxf2" | |
14542 | [(set (match_operand:XF 0 "register_operand" "=f") | |
14543 | (sqrt:XF (match_operand:XF 1 "register_operand" "0")))] | |
1b0c37d7 | 14544 | "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 |
de6c5979 | 14545 | && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) " |
e075ae69 | 14546 | "fsqrt" |
0b5107cf | 14547 | [(set_attr "type" "fpspc") |
6ef67412 | 14548 | (set_attr "mode" "XF") |
0b5107cf | 14549 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14550 | |
2b589241 JH |
14551 | (define_insn "sqrttf2" |
14552 | [(set (match_operand:TF 0 "register_operand" "=f") | |
14553 | (sqrt:TF (match_operand:TF 1 "register_operand" "0")))] | |
14554 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 | |
de6c5979 | 14555 | && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) " |
2b589241 JH |
14556 | "fsqrt" |
14557 | [(set_attr "type" "fpspc") | |
14558 | (set_attr "mode" "XF") | |
14559 | (set_attr "athlon_decode" "direct")]) | |
14560 | ||
6343a50e | 14561 | (define_insn "*sqrtextenddfxf2" |
e075ae69 RH |
14562 | [(set (match_operand:XF 0 "register_operand" "=f") |
14563 | (sqrt:XF (float_extend:XF | |
14564 | (match_operand:DF 1 "register_operand" "0"))))] | |
1b0c37d7 | 14565 | "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387" |
e075ae69 | 14566 | "fsqrt" |
0b5107cf | 14567 | [(set_attr "type" "fpspc") |
6ef67412 | 14568 | (set_attr "mode" "XF") |
0b5107cf | 14569 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14570 | |
2b589241 JH |
14571 | (define_insn "*sqrtextenddftf2" |
14572 | [(set (match_operand:TF 0 "register_operand" "=f") | |
14573 | (sqrt:TF (float_extend:TF | |
14574 | (match_operand:DF 1 "register_operand" "0"))))] | |
14575 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" | |
14576 | "fsqrt" | |
14577 | [(set_attr "type" "fpspc") | |
14578 | (set_attr "mode" "XF") | |
14579 | (set_attr "athlon_decode" "direct")]) | |
14580 | ||
6343a50e | 14581 | (define_insn "*sqrtextendsfxf2" |
e075ae69 RH |
14582 | [(set (match_operand:XF 0 "register_operand" "=f") |
14583 | (sqrt:XF (float_extend:XF | |
14584 | (match_operand:SF 1 "register_operand" "0"))))] | |
1b0c37d7 | 14585 | "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387" |
e075ae69 | 14586 | "fsqrt" |
0b5107cf | 14587 | [(set_attr "type" "fpspc") |
6ef67412 | 14588 | (set_attr "mode" "XF") |
0b5107cf | 14589 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14590 | |
2b589241 JH |
14591 | (define_insn "*sqrtextendsftf2" |
14592 | [(set (match_operand:TF 0 "register_operand" "=f") | |
14593 | (sqrt:TF (float_extend:TF | |
14594 | (match_operand:SF 1 "register_operand" "0"))))] | |
14595 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" | |
14596 | "fsqrt" | |
14597 | [(set_attr "type" "fpspc") | |
14598 | (set_attr "mode" "XF") | |
14599 | (set_attr "athlon_decode" "direct")]) | |
14600 | ||
e075ae69 RH |
14601 | (define_insn "sindf2" |
14602 | [(set (match_operand:DF 0 "register_operand" "=f") | |
14603 | (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))] | |
de6c5979 BL |
14604 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14605 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14606 | "fsin" |
6ef67412 JH |
14607 | [(set_attr "type" "fpspc") |
14608 | (set_attr "mode" "DF")]) | |
e075ae69 RH |
14609 | |
14610 | (define_insn "sinsf2" | |
14611 | [(set (match_operand:SF 0 "register_operand" "=f") | |
14612 | (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))] | |
de6c5979 BL |
14613 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14614 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14615 | "fsin" |
6ef67412 JH |
14616 | [(set_attr "type" "fpspc") |
14617 | (set_attr "mode" "SF")]) | |
5f3d14e3 | 14618 | |
6343a50e | 14619 | (define_insn "*sinextendsfdf2" |
e075ae69 RH |
14620 | [(set (match_operand:DF 0 "register_operand" "=f") |
14621 | (unspec:DF [(float_extend:DF | |
14622 | (match_operand:SF 1 "register_operand" "0"))] 1))] | |
de6c5979 BL |
14623 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14624 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14625 | "fsin" |
6ef67412 JH |
14626 | [(set_attr "type" "fpspc") |
14627 | (set_attr "mode" "DF")]) | |
4f9ca067 | 14628 | |
e075ae69 RH |
14629 | (define_insn "sinxf2" |
14630 | [(set (match_operand:XF 0 "register_operand" "=f") | |
14631 | (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))] | |
1b0c37d7 | 14632 | "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387 |
de6c5979 | 14633 | && flag_unsafe_math_optimizations" |
e075ae69 | 14634 | "fsin" |
6ef67412 JH |
14635 | [(set_attr "type" "fpspc") |
14636 | (set_attr "mode" "XF")]) | |
5f3d14e3 | 14637 | |
2b589241 JH |
14638 | (define_insn "sintf2" |
14639 | [(set (match_operand:TF 0 "register_operand" "=f") | |
14640 | (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))] | |
de6c5979 BL |
14641 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14642 | && flag_unsafe_math_optimizations" | |
2b589241 JH |
14643 | "fsin" |
14644 | [(set_attr "type" "fpspc") | |
14645 | (set_attr "mode" "XF")]) | |
14646 | ||
e075ae69 RH |
14647 | (define_insn "cosdf2" |
14648 | [(set (match_operand:DF 0 "register_operand" "=f") | |
14649 | (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))] | |
de6c5979 BL |
14650 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14651 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14652 | "fcos" |
6ef67412 JH |
14653 | [(set_attr "type" "fpspc") |
14654 | (set_attr "mode" "DF")]) | |
bca7cce2 | 14655 | |
e075ae69 RH |
14656 | (define_insn "cossf2" |
14657 | [(set (match_operand:SF 0 "register_operand" "=f") | |
14658 | (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))] | |
de6c5979 BL |
14659 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14660 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14661 | "fcos" |
6ef67412 JH |
14662 | [(set_attr "type" "fpspc") |
14663 | (set_attr "mode" "SF")]) | |
bca7cce2 | 14664 | |
6343a50e | 14665 | (define_insn "*cosextendsfdf2" |
e075ae69 RH |
14666 | [(set (match_operand:DF 0 "register_operand" "=f") |
14667 | (unspec:DF [(float_extend:DF | |
14668 | (match_operand:SF 1 "register_operand" "0"))] 2))] | |
de6c5979 BL |
14669 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14670 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14671 | "fcos" |
6ef67412 JH |
14672 | [(set_attr "type" "fpspc") |
14673 | (set_attr "mode" "DF")]) | |
5f3d14e3 | 14674 | |
e075ae69 RH |
14675 | (define_insn "cosxf2" |
14676 | [(set (match_operand:XF 0 "register_operand" "=f") | |
14677 | (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))] | |
1e07edd3 | 14678 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
de6c5979 | 14679 | && flag_unsafe_math_optimizations" |
e075ae69 | 14680 | "fcos" |
6ef67412 JH |
14681 | [(set_attr "type" "fpspc") |
14682 | (set_attr "mode" "XF")]) | |
2b589241 JH |
14683 | |
14684 | (define_insn "costf2" | |
14685 | [(set (match_operand:TF 0 "register_operand" "=f") | |
14686 | (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))] | |
de6c5979 BL |
14687 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14688 | && flag_unsafe_math_optimizations" | |
2b589241 JH |
14689 | "fcos" |
14690 | [(set_attr "type" "fpspc") | |
14691 | (set_attr "mode" "XF")]) | |
e075ae69 RH |
14692 | \f |
14693 | ;; Block operation instructions | |
886c62d1 | 14694 | |
7c7ef435 JH |
14695 | (define_insn "cld" |
14696 | [(set (reg:SI 19) (const_int 0))] | |
14697 | "" | |
14698 | "cld" | |
14699 | [(set_attr "type" "cld")]) | |
14700 | ||
886c62d1 | 14701 | (define_expand "movstrsi" |
f90800f8 JH |
14702 | [(use (match_operand:BLK 0 "memory_operand" "")) |
14703 | (use (match_operand:BLK 1 "memory_operand" "")) | |
79f05c19 | 14704 | (use (match_operand:SI 2 "nonmemory_operand" "")) |
f90800f8 | 14705 | (use (match_operand:SI 3 "const_int_operand" ""))] |
886c62d1 | 14706 | "" |
886c62d1 | 14707 | { |
0945b39d JH |
14708 | if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3])) |
14709 | DONE; | |
14710 | else | |
14711 | FAIL; | |
0f40f9f7 | 14712 | }) |
79f05c19 | 14713 | |
0945b39d JH |
14714 | (define_expand "movstrdi" |
14715 | [(use (match_operand:BLK 0 "memory_operand" "")) | |
14716 | (use (match_operand:BLK 1 "memory_operand" "")) | |
14717 | (use (match_operand:DI 2 "nonmemory_operand" "")) | |
14718 | (use (match_operand:DI 3 "const_int_operand" ""))] | |
14719 | "TARGET_64BIT" | |
0945b39d JH |
14720 | { |
14721 | if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3])) | |
14722 | DONE; | |
14723 | else | |
14724 | FAIL; | |
0f40f9f7 | 14725 | }) |
79f05c19 | 14726 | |
0945b39d JH |
14727 | ;; Most CPUs don't like single string operations |
14728 | ;; Handle this case here to simplify previous expander. | |
79f05c19 | 14729 | |
0945b39d JH |
14730 | (define_expand "strmovdi_rex64" |
14731 | [(set (match_dup 2) | |
14732 | (mem:DI (match_operand:DI 1 "register_operand" ""))) | |
14733 | (set (mem:DI (match_operand:DI 0 "register_operand" "")) | |
14734 | (match_dup 2)) | |
14735 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8))) | |
14736 | (clobber (reg:CC 17))]) | |
14737 | (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8))) | |
14738 | (clobber (reg:CC 17))])] | |
14739 | "TARGET_64BIT" | |
0945b39d JH |
14740 | { |
14741 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
79f05c19 | 14742 | { |
0945b39d JH |
14743 | emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0], |
14744 | operands[1])); | |
14745 | DONE; | |
79f05c19 | 14746 | } |
0945b39d JH |
14747 | else |
14748 | operands[2] = gen_reg_rtx (DImode); | |
0f40f9f7 | 14749 | }) |
886c62d1 | 14750 | |
56c0e8fa | 14751 | |
79f05c19 JH |
14752 | (define_expand "strmovsi" |
14753 | [(set (match_dup 2) | |
14754 | (mem:SI (match_operand:SI 1 "register_operand" ""))) | |
14755 | (set (mem:SI (match_operand:SI 0 "register_operand" "")) | |
14756 | (match_dup 2)) | |
14757 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4))) | |
14758 | (clobber (reg:CC 17))]) | |
14759 | (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4))) | |
14760 | (clobber (reg:CC 17))])] | |
14761 | "" | |
79f05c19 | 14762 | { |
0945b39d JH |
14763 | if (TARGET_64BIT) |
14764 | { | |
14765 | emit_insn (gen_strmovsi_rex64 (operands[0], operands[1])); | |
14766 | DONE; | |
14767 | } | |
79f05c19 JH |
14768 | if (TARGET_SINGLE_STRINGOP || optimize_size) |
14769 | { | |
14770 | emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0], | |
14771 | operands[1])); | |
14772 | DONE; | |
14773 | } | |
14774 | else | |
14775 | operands[2] = gen_reg_rtx (SImode); | |
0f40f9f7 | 14776 | }) |
79f05c19 | 14777 | |
0945b39d JH |
14778 | (define_expand "strmovsi_rex64" |
14779 | [(set (match_dup 2) | |
14780 | (mem:SI (match_operand:DI 1 "register_operand" ""))) | |
14781 | (set (mem:SI (match_operand:DI 0 "register_operand" "")) | |
14782 | (match_dup 2)) | |
14783 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4))) | |
14784 | (clobber (reg:CC 17))]) | |
14785 | (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4))) | |
14786 | (clobber (reg:CC 17))])] | |
14787 | "TARGET_64BIT" | |
0945b39d JH |
14788 | { |
14789 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
14790 | { | |
14791 | emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0], | |
14792 | operands[1])); | |
14793 | DONE; | |
14794 | } | |
14795 | else | |
14796 | operands[2] = gen_reg_rtx (SImode); | |
0f40f9f7 | 14797 | }) |
0945b39d | 14798 | |
f90800f8 JH |
14799 | (define_expand "strmovhi" |
14800 | [(set (match_dup 2) | |
14801 | (mem:HI (match_operand:SI 1 "register_operand" ""))) | |
14802 | (set (mem:HI (match_operand:SI 0 "register_operand" "")) | |
14803 | (match_dup 2)) | |
14804 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2))) | |
14805 | (clobber (reg:CC 17))]) | |
14806 | (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2))) | |
14807 | (clobber (reg:CC 17))])] | |
886c62d1 | 14808 | "" |
886c62d1 | 14809 | { |
0945b39d JH |
14810 | if (TARGET_64BIT) |
14811 | { | |
14812 | emit_insn (gen_strmovhi_rex64 (operands[0], operands[1])); | |
14813 | DONE; | |
14814 | } | |
f90800f8 | 14815 | if (TARGET_SINGLE_STRINGOP || optimize_size) |
886c62d1 | 14816 | { |
f90800f8 JH |
14817 | emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0], |
14818 | operands[1])); | |
14819 | DONE; | |
14820 | } | |
14821 | else | |
14822 | operands[2] = gen_reg_rtx (HImode); | |
0f40f9f7 | 14823 | }) |
886c62d1 | 14824 | |
0945b39d JH |
14825 | (define_expand "strmovhi_rex64" |
14826 | [(set (match_dup 2) | |
14827 | (mem:HI (match_operand:DI 1 "register_operand" ""))) | |
14828 | (set (mem:HI (match_operand:DI 0 "register_operand" "")) | |
14829 | (match_dup 2)) | |
14830 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2))) | |
14831 | (clobber (reg:CC 17))]) | |
14832 | (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2))) | |
14833 | (clobber (reg:CC 17))])] | |
14834 | "TARGET_64BIT" | |
0945b39d JH |
14835 | { |
14836 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
14837 | { | |
14838 | emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0], | |
14839 | operands[1])); | |
14840 | DONE; | |
14841 | } | |
14842 | else | |
14843 | operands[2] = gen_reg_rtx (HImode); | |
0f40f9f7 | 14844 | }) |
0945b39d | 14845 | |
f90800f8 JH |
14846 | (define_expand "strmovqi" |
14847 | [(set (match_dup 2) | |
14848 | (mem:QI (match_operand:SI 1 "register_operand" ""))) | |
14849 | (set (mem:QI (match_operand:SI 0 "register_operand" "")) | |
14850 | (match_dup 2)) | |
14851 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) | |
14852 | (clobber (reg:CC 17))]) | |
14853 | (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1))) | |
14854 | (clobber (reg:CC 17))])] | |
14855 | "" | |
f90800f8 | 14856 | { |
0945b39d JH |
14857 | if (TARGET_64BIT) |
14858 | { | |
14859 | emit_insn (gen_strmovqi_rex64 (operands[0], operands[1])); | |
14860 | DONE; | |
14861 | } | |
f90800f8 JH |
14862 | if (TARGET_SINGLE_STRINGOP || optimize_size) |
14863 | { | |
14864 | emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0], | |
14865 | operands[1])); | |
14866 | DONE; | |
886c62d1 | 14867 | } |
f90800f8 JH |
14868 | else |
14869 | operands[2] = gen_reg_rtx (QImode); | |
0f40f9f7 | 14870 | }) |
f90800f8 | 14871 | |
0945b39d JH |
14872 | (define_expand "strmovqi_rex64" |
14873 | [(set (match_dup 2) | |
14874 | (mem:QI (match_operand:DI 1 "register_operand" ""))) | |
14875 | (set (mem:QI (match_operand:DI 0 "register_operand" "")) | |
14876 | (match_dup 2)) | |
14877 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1))) | |
14878 | (clobber (reg:CC 17))]) | |
14879 | (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1))) | |
14880 | (clobber (reg:CC 17))])] | |
1b0c37d7 | 14881 | "TARGET_64BIT" |
0945b39d JH |
14882 | { |
14883 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
14884 | { | |
14885 | emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0], | |
14886 | operands[1])); | |
14887 | DONE; | |
14888 | } | |
14889 | else | |
14890 | operands[2] = gen_reg_rtx (QImode); | |
0f40f9f7 | 14891 | }) |
0945b39d JH |
14892 | |
14893 | (define_insn "strmovdi_rex_1" | |
14894 | [(set (mem:DI (match_operand:DI 2 "register_operand" "0")) | |
14895 | (mem:DI (match_operand:DI 3 "register_operand" "1"))) | |
14896 | (set (match_operand:DI 0 "register_operand" "=D") | |
14897 | (plus:DI (match_dup 2) | |
14898 | (const_int 8))) | |
14899 | (set (match_operand:DI 1 "register_operand" "=S") | |
14900 | (plus:DI (match_dup 3) | |
14901 | (const_int 8))) | |
14902 | (use (reg:SI 19))] | |
14903 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
14904 | "movsq" | |
14905 | [(set_attr "type" "str") | |
14906 | (set_attr "mode" "DI") | |
14907 | (set_attr "memory" "both")]) | |
14908 | ||
79f05c19 JH |
14909 | (define_insn "strmovsi_1" |
14910 | [(set (mem:SI (match_operand:SI 2 "register_operand" "0")) | |
14911 | (mem:SI (match_operand:SI 3 "register_operand" "1"))) | |
14912 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 14913 | (plus:SI (match_dup 2) |
79f05c19 JH |
14914 | (const_int 4))) |
14915 | (set (match_operand:SI 1 "register_operand" "=S") | |
b1cdafbb | 14916 | (plus:SI (match_dup 3) |
79f05c19 JH |
14917 | (const_int 4))) |
14918 | (use (reg:SI 19))] | |
0945b39d | 14919 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
371bc54b | 14920 | "{movsl|movsd}" |
0945b39d JH |
14921 | [(set_attr "type" "str") |
14922 | (set_attr "mode" "SI") | |
14923 | (set_attr "memory" "both")]) | |
14924 | ||
14925 | (define_insn "strmovsi_rex_1" | |
14926 | [(set (mem:SI (match_operand:DI 2 "register_operand" "0")) | |
14927 | (mem:SI (match_operand:DI 3 "register_operand" "1"))) | |
14928 | (set (match_operand:DI 0 "register_operand" "=D") | |
14929 | (plus:DI (match_dup 2) | |
14930 | (const_int 4))) | |
14931 | (set (match_operand:DI 1 "register_operand" "=S") | |
14932 | (plus:DI (match_dup 3) | |
14933 | (const_int 4))) | |
14934 | (use (reg:SI 19))] | |
14935 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
371bc54b | 14936 | "{movsl|movsd}" |
79f05c19 | 14937 | [(set_attr "type" "str") |
6ef67412 | 14938 | (set_attr "mode" "SI") |
79f05c19 JH |
14939 | (set_attr "memory" "both")]) |
14940 | ||
f90800f8 JH |
14941 | (define_insn "strmovhi_1" |
14942 | [(set (mem:HI (match_operand:SI 2 "register_operand" "0")) | |
14943 | (mem:HI (match_operand:SI 3 "register_operand" "1"))) | |
14944 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 14945 | (plus:SI (match_dup 2) |
f90800f8 JH |
14946 | (const_int 2))) |
14947 | (set (match_operand:SI 1 "register_operand" "=S") | |
b1cdafbb | 14948 | (plus:SI (match_dup 3) |
f90800f8 JH |
14949 | (const_int 2))) |
14950 | (use (reg:SI 19))] | |
0945b39d JH |
14951 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
14952 | "movsw" | |
14953 | [(set_attr "type" "str") | |
14954 | (set_attr "memory" "both") | |
14955 | (set_attr "mode" "HI")]) | |
14956 | ||
14957 | (define_insn "strmovhi_rex_1" | |
14958 | [(set (mem:HI (match_operand:DI 2 "register_operand" "0")) | |
14959 | (mem:HI (match_operand:DI 3 "register_operand" "1"))) | |
14960 | (set (match_operand:DI 0 "register_operand" "=D") | |
14961 | (plus:DI (match_dup 2) | |
14962 | (const_int 2))) | |
14963 | (set (match_operand:DI 1 "register_operand" "=S") | |
14964 | (plus:DI (match_dup 3) | |
14965 | (const_int 2))) | |
14966 | (use (reg:SI 19))] | |
14967 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
f90800f8 JH |
14968 | "movsw" |
14969 | [(set_attr "type" "str") | |
14970 | (set_attr "memory" "both") | |
6ef67412 | 14971 | (set_attr "mode" "HI")]) |
f90800f8 JH |
14972 | |
14973 | (define_insn "strmovqi_1" | |
14974 | [(set (mem:QI (match_operand:SI 2 "register_operand" "0")) | |
14975 | (mem:QI (match_operand:SI 3 "register_operand" "1"))) | |
14976 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 14977 | (plus:SI (match_dup 2) |
f90800f8 JH |
14978 | (const_int 1))) |
14979 | (set (match_operand:SI 1 "register_operand" "=S") | |
b1cdafbb | 14980 | (plus:SI (match_dup 3) |
f90800f8 JH |
14981 | (const_int 1))) |
14982 | (use (reg:SI 19))] | |
0945b39d | 14983 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
f90800f8 JH |
14984 | "movsb" |
14985 | [(set_attr "type" "str") | |
6ef67412 JH |
14986 | (set_attr "memory" "both") |
14987 | (set_attr "mode" "QI")]) | |
f90800f8 | 14988 | |
0945b39d JH |
14989 | (define_insn "strmovqi_rex_1" |
14990 | [(set (mem:QI (match_operand:DI 2 "register_operand" "0")) | |
14991 | (mem:QI (match_operand:DI 3 "register_operand" "1"))) | |
14992 | (set (match_operand:DI 0 "register_operand" "=D") | |
14993 | (plus:DI (match_dup 2) | |
14994 | (const_int 1))) | |
14995 | (set (match_operand:DI 1 "register_operand" "=S") | |
14996 | (plus:DI (match_dup 3) | |
14997 | (const_int 1))) | |
14998 | (use (reg:SI 19))] | |
14999 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
15000 | "movsb" | |
15001 | [(set_attr "type" "str") | |
15002 | (set_attr "memory" "both") | |
15003 | (set_attr "mode" "QI")]) | |
15004 | ||
15005 | (define_insn "rep_movdi_rex64" | |
15006 | [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) | |
15007 | (set (match_operand:DI 0 "register_operand" "=D") | |
15008 | (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2") | |
15009 | (const_int 3)) | |
15010 | (match_operand:DI 3 "register_operand" "0"))) | |
15011 | (set (match_operand:DI 1 "register_operand" "=S") | |
15012 | (plus:DI (ashift:DI (match_dup 5) (const_int 3)) | |
15013 | (match_operand:DI 4 "register_operand" "1"))) | |
15014 | (set (mem:BLK (match_dup 3)) | |
15015 | (mem:BLK (match_dup 4))) | |
15016 | (use (match_dup 5)) | |
15017 | (use (reg:SI 19))] | |
15018 | "TARGET_64BIT" | |
8554d9a4 | 15019 | "{rep\;movsq|rep movsq}" |
0945b39d JH |
15020 | [(set_attr "type" "str") |
15021 | (set_attr "prefix_rep" "1") | |
15022 | (set_attr "memory" "both") | |
15023 | (set_attr "mode" "DI")]) | |
15024 | ||
f90800f8 JH |
15025 | (define_insn "rep_movsi" |
15026 | [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0)) | |
f90800f8 | 15027 | (set (match_operand:SI 0 "register_operand" "=D") |
b1cdafbb JH |
15028 | (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2") |
15029 | (const_int 2)) | |
15030 | (match_operand:SI 3 "register_operand" "0"))) | |
f90800f8 | 15031 | (set (match_operand:SI 1 "register_operand" "=S") |
b1cdafbb JH |
15032 | (plus:SI (ashift:SI (match_dup 5) (const_int 2)) |
15033 | (match_operand:SI 4 "register_operand" "1"))) | |
f90800f8 JH |
15034 | (set (mem:BLK (match_dup 3)) |
15035 | (mem:BLK (match_dup 4))) | |
b1cdafbb | 15036 | (use (match_dup 5)) |
f90800f8 | 15037 | (use (reg:SI 19))] |
0945b39d | 15038 | "!TARGET_64BIT" |
8554d9a4 | 15039 | "{rep\;movsl|rep movsd}" |
0945b39d JH |
15040 | [(set_attr "type" "str") |
15041 | (set_attr "prefix_rep" "1") | |
15042 | (set_attr "memory" "both") | |
15043 | (set_attr "mode" "SI")]) | |
15044 | ||
15045 | (define_insn "rep_movsi_rex64" | |
15046 | [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) | |
15047 | (set (match_operand:DI 0 "register_operand" "=D") | |
15048 | (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2") | |
15049 | (const_int 2)) | |
15050 | (match_operand:DI 3 "register_operand" "0"))) | |
15051 | (set (match_operand:DI 1 "register_operand" "=S") | |
15052 | (plus:DI (ashift:DI (match_dup 5) (const_int 2)) | |
15053 | (match_operand:DI 4 "register_operand" "1"))) | |
15054 | (set (mem:BLK (match_dup 3)) | |
15055 | (mem:BLK (match_dup 4))) | |
15056 | (use (match_dup 5)) | |
15057 | (use (reg:SI 19))] | |
15058 | "TARGET_64BIT" | |
8554d9a4 | 15059 | "{rep\;movsl|rep movsd}" |
f90800f8 | 15060 | [(set_attr "type" "str") |
6ef67412 JH |
15061 | (set_attr "prefix_rep" "1") |
15062 | (set_attr "memory" "both") | |
15063 | (set_attr "mode" "SI")]) | |
f90800f8 JH |
15064 | |
15065 | (define_insn "rep_movqi" | |
15066 | [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0)) | |
f90800f8 | 15067 | (set (match_operand:SI 0 "register_operand" "=D") |
b1cdafbb JH |
15068 | (plus:SI (match_operand:SI 3 "register_operand" "0") |
15069 | (match_operand:SI 5 "register_operand" "2"))) | |
f90800f8 | 15070 | (set (match_operand:SI 1 "register_operand" "=S") |
b1cdafbb | 15071 | (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5))) |
f90800f8 JH |
15072 | (set (mem:BLK (match_dup 3)) |
15073 | (mem:BLK (match_dup 4))) | |
b1cdafbb | 15074 | (use (match_dup 5)) |
f90800f8 | 15075 | (use (reg:SI 19))] |
0945b39d | 15076 | "!TARGET_64BIT" |
8554d9a4 | 15077 | "{rep\;movsb|rep movsb}" |
0945b39d JH |
15078 | [(set_attr "type" "str") |
15079 | (set_attr "prefix_rep" "1") | |
15080 | (set_attr "memory" "both") | |
15081 | (set_attr "mode" "SI")]) | |
15082 | ||
15083 | (define_insn "rep_movqi_rex64" | |
15084 | [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) | |
15085 | (set (match_operand:DI 0 "register_operand" "=D") | |
15086 | (plus:DI (match_operand:DI 3 "register_operand" "0") | |
15087 | (match_operand:DI 5 "register_operand" "2"))) | |
15088 | (set (match_operand:DI 1 "register_operand" "=S") | |
15089 | (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5))) | |
15090 | (set (mem:BLK (match_dup 3)) | |
15091 | (mem:BLK (match_dup 4))) | |
15092 | (use (match_dup 5)) | |
15093 | (use (reg:SI 19))] | |
15094 | "TARGET_64BIT" | |
8554d9a4 | 15095 | "{rep\;movsb|rep movsb}" |
f90800f8 | 15096 | [(set_attr "type" "str") |
6ef67412 JH |
15097 | (set_attr "prefix_rep" "1") |
15098 | (set_attr "memory" "both") | |
15099 | (set_attr "mode" "SI")]) | |
886c62d1 | 15100 | |
0ae40045 | 15101 | (define_expand "clrstrsi" |
e2e52e1b | 15102 | [(use (match_operand:BLK 0 "memory_operand" "")) |
79f05c19 | 15103 | (use (match_operand:SI 1 "nonmemory_operand" "")) |
0945b39d | 15104 | (use (match_operand 2 "const_int_operand" ""))] |
0ae40045 | 15105 | "" |
0ae40045 | 15106 | { |
0945b39d JH |
15107 | if (ix86_expand_clrstr (operands[0], operands[1], operands[2])) |
15108 | DONE; | |
15109 | else | |
15110 | FAIL; | |
0f40f9f7 | 15111 | }) |
e2e52e1b | 15112 | |
0945b39d JH |
15113 | (define_expand "clrstrdi" |
15114 | [(use (match_operand:BLK 0 "memory_operand" "")) | |
15115 | (use (match_operand:DI 1 "nonmemory_operand" "")) | |
15116 | (use (match_operand 2 "const_int_operand" ""))] | |
15117 | "TARGET_64BIT" | |
0945b39d JH |
15118 | { |
15119 | if (ix86_expand_clrstr (operands[0], operands[1], operands[2])) | |
15120 | DONE; | |
15121 | else | |
15122 | FAIL; | |
0f40f9f7 | 15123 | }) |
e2e52e1b | 15124 | |
0945b39d JH |
15125 | ;; Most CPUs don't like single string operations |
15126 | ;; Handle this case here to simplify previous expander. | |
79f05c19 | 15127 | |
0945b39d JH |
15128 | (define_expand "strsetdi_rex64" |
15129 | [(set (mem:DI (match_operand:DI 0 "register_operand" "")) | |
15130 | (match_operand:DI 1 "register_operand" "")) | |
15131 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8))) | |
15132 | (clobber (reg:CC 17))])] | |
15133 | "TARGET_64BIT" | |
0945b39d JH |
15134 | { |
15135 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
79f05c19 | 15136 | { |
0945b39d JH |
15137 | emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1])); |
15138 | DONE; | |
79f05c19 | 15139 | } |
0f40f9f7 | 15140 | }) |
e2e52e1b | 15141 | |
79f05c19 JH |
15142 | (define_expand "strsetsi" |
15143 | [(set (mem:SI (match_operand:SI 0 "register_operand" "")) | |
15144 | (match_operand:SI 1 "register_operand" "")) | |
15145 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4))) | |
15146 | (clobber (reg:CC 17))])] | |
15147 | "" | |
79f05c19 | 15148 | { |
0945b39d JH |
15149 | if (TARGET_64BIT) |
15150 | { | |
15151 | emit_insn (gen_strsetsi_rex64 (operands[0], operands[1])); | |
15152 | DONE; | |
15153 | } | |
15154 | else if (TARGET_SINGLE_STRINGOP || optimize_size) | |
79f05c19 JH |
15155 | { |
15156 | emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1])); | |
15157 | DONE; | |
15158 | } | |
0f40f9f7 | 15159 | }) |
79f05c19 | 15160 | |
0945b39d JH |
15161 | (define_expand "strsetsi_rex64" |
15162 | [(set (mem:SI (match_operand:DI 0 "register_operand" "")) | |
15163 | (match_operand:SI 1 "register_operand" "")) | |
15164 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4))) | |
15165 | (clobber (reg:CC 17))])] | |
15166 | "TARGET_64BIT" | |
0945b39d JH |
15167 | { |
15168 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
15169 | { | |
15170 | emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1])); | |
15171 | DONE; | |
15172 | } | |
0f40f9f7 | 15173 | }) |
0945b39d | 15174 | |
e2e52e1b JH |
15175 | (define_expand "strsethi" |
15176 | [(set (mem:HI (match_operand:SI 0 "register_operand" "")) | |
15177 | (match_operand:HI 1 "register_operand" "")) | |
15178 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2))) | |
15179 | (clobber (reg:CC 17))])] | |
15180 | "" | |
e2e52e1b | 15181 | { |
0945b39d JH |
15182 | if (TARGET_64BIT) |
15183 | { | |
15184 | emit_insn (gen_strsethi_rex64 (operands[0], operands[1])); | |
15185 | DONE; | |
15186 | } | |
15187 | else if (TARGET_SINGLE_STRINGOP || optimize_size) | |
e2e52e1b JH |
15188 | { |
15189 | emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1])); | |
15190 | DONE; | |
15191 | } | |
0f40f9f7 | 15192 | }) |
0ae40045 | 15193 | |
0945b39d JH |
15194 | (define_expand "strsethi_rex64" |
15195 | [(set (mem:HI (match_operand:DI 0 "register_operand" "")) | |
15196 | (match_operand:HI 1 "register_operand" "")) | |
15197 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2))) | |
15198 | (clobber (reg:CC 17))])] | |
15199 | "TARGET_64BIT" | |
0945b39d JH |
15200 | { |
15201 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
15202 | { | |
15203 | emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1])); | |
15204 | DONE; | |
15205 | } | |
0f40f9f7 | 15206 | }) |
0945b39d | 15207 | |
e2e52e1b JH |
15208 | (define_expand "strsetqi" |
15209 | [(set (mem:QI (match_operand:SI 0 "register_operand" "")) | |
15210 | (match_operand:QI 1 "register_operand" "")) | |
15211 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) | |
15212 | (clobber (reg:CC 17))])] | |
15213 | "" | |
e2e52e1b | 15214 | { |
0945b39d JH |
15215 | if (TARGET_64BIT) |
15216 | { | |
15217 | emit_insn (gen_strsetqi_rex64 (operands[0], operands[1])); | |
15218 | DONE; | |
15219 | } | |
15220 | else if (TARGET_SINGLE_STRINGOP || optimize_size) | |
e2e52e1b JH |
15221 | { |
15222 | emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1])); | |
15223 | DONE; | |
15224 | } | |
0f40f9f7 | 15225 | }) |
0ae40045 | 15226 | |
0945b39d JH |
15227 | (define_expand "strsetqi_rex64" |
15228 | [(set (mem:QI (match_operand:DI 0 "register_operand" "")) | |
15229 | (match_operand:QI 1 "register_operand" "")) | |
15230 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1))) | |
15231 | (clobber (reg:CC 17))])] | |
15232 | "TARGET_64BIT" | |
0945b39d JH |
15233 | { |
15234 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
15235 | { | |
15236 | emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1])); | |
15237 | DONE; | |
15238 | } | |
0f40f9f7 | 15239 | }) |
0945b39d JH |
15240 | |
15241 | (define_insn "strsetdi_rex_1" | |
15242 | [(set (mem:SI (match_operand:DI 1 "register_operand" "0")) | |
15243 | (match_operand:SI 2 "register_operand" "a")) | |
15244 | (set (match_operand:DI 0 "register_operand" "=D") | |
15245 | (plus:DI (match_dup 1) | |
15246 | (const_int 8))) | |
15247 | (use (reg:SI 19))] | |
15248 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
15249 | "stosq" | |
15250 | [(set_attr "type" "str") | |
15251 | (set_attr "memory" "store") | |
15252 | (set_attr "mode" "DI")]) | |
15253 | ||
79f05c19 JH |
15254 | (define_insn "strsetsi_1" |
15255 | [(set (mem:SI (match_operand:SI 1 "register_operand" "0")) | |
15256 | (match_operand:SI 2 "register_operand" "a")) | |
15257 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 15258 | (plus:SI (match_dup 1) |
79f05c19 JH |
15259 | (const_int 4))) |
15260 | (use (reg:SI 19))] | |
0945b39d | 15261 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
8554d9a4 | 15262 | "{stosl|stosd}" |
0945b39d JH |
15263 | [(set_attr "type" "str") |
15264 | (set_attr "memory" "store") | |
15265 | (set_attr "mode" "SI")]) | |
15266 | ||
15267 | (define_insn "strsetsi_rex_1" | |
15268 | [(set (mem:SI (match_operand:DI 1 "register_operand" "0")) | |
15269 | (match_operand:SI 2 "register_operand" "a")) | |
15270 | (set (match_operand:DI 0 "register_operand" "=D") | |
15271 | (plus:DI (match_dup 1) | |
15272 | (const_int 4))) | |
15273 | (use (reg:SI 19))] | |
15274 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
8554d9a4 | 15275 | "{stosl|stosd}" |
79f05c19 | 15276 | [(set_attr "type" "str") |
6ef67412 JH |
15277 | (set_attr "memory" "store") |
15278 | (set_attr "mode" "SI")]) | |
79f05c19 | 15279 | |
e2e52e1b JH |
15280 | (define_insn "strsethi_1" |
15281 | [(set (mem:HI (match_operand:SI 1 "register_operand" "0")) | |
15282 | (match_operand:HI 2 "register_operand" "a")) | |
15283 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 15284 | (plus:SI (match_dup 1) |
e2e52e1b JH |
15285 | (const_int 2))) |
15286 | (use (reg:SI 19))] | |
0945b39d JH |
15287 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
15288 | "stosw" | |
15289 | [(set_attr "type" "str") | |
15290 | (set_attr "memory" "store") | |
15291 | (set_attr "mode" "HI")]) | |
15292 | ||
15293 | (define_insn "strsethi_rex_1" | |
15294 | [(set (mem:HI (match_operand:DI 1 "register_operand" "0")) | |
15295 | (match_operand:HI 2 "register_operand" "a")) | |
15296 | (set (match_operand:DI 0 "register_operand" "=D") | |
15297 | (plus:DI (match_dup 1) | |
15298 | (const_int 2))) | |
15299 | (use (reg:SI 19))] | |
15300 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
e2e52e1b JH |
15301 | "stosw" |
15302 | [(set_attr "type" "str") | |
15303 | (set_attr "memory" "store") | |
6ef67412 | 15304 | (set_attr "mode" "HI")]) |
e2e52e1b JH |
15305 | |
15306 | (define_insn "strsetqi_1" | |
15307 | [(set (mem:QI (match_operand:SI 1 "register_operand" "0")) | |
15308 | (match_operand:QI 2 "register_operand" "a")) | |
15309 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 15310 | (plus:SI (match_dup 1) |
e2e52e1b JH |
15311 | (const_int 1))) |
15312 | (use (reg:SI 19))] | |
0945b39d JH |
15313 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
15314 | "stosb" | |
15315 | [(set_attr "type" "str") | |
15316 | (set_attr "memory" "store") | |
15317 | (set_attr "mode" "QI")]) | |
15318 | ||
15319 | (define_insn "strsetqi_rex_1" | |
15320 | [(set (mem:QI (match_operand:DI 1 "register_operand" "0")) | |
15321 | (match_operand:QI 2 "register_operand" "a")) | |
15322 | (set (match_operand:DI 0 "register_operand" "=D") | |
15323 | (plus:DI (match_dup 1) | |
15324 | (const_int 1))) | |
15325 | (use (reg:SI 19))] | |
15326 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
e2e52e1b JH |
15327 | "stosb" |
15328 | [(set_attr "type" "str") | |
6ef67412 JH |
15329 | (set_attr "memory" "store") |
15330 | (set_attr "mode" "QI")]) | |
e2e52e1b | 15331 | |
0945b39d JH |
15332 | (define_insn "rep_stosdi_rex64" |
15333 | [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) | |
15334 | (set (match_operand:DI 0 "register_operand" "=D") | |
15335 | (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1") | |
15336 | (const_int 3)) | |
15337 | (match_operand:DI 3 "register_operand" "0"))) | |
15338 | (set (mem:BLK (match_dup 3)) | |
15339 | (const_int 0)) | |
15340 | (use (match_operand:DI 2 "register_operand" "a")) | |
15341 | (use (match_dup 4)) | |
15342 | (use (reg:SI 19))] | |
15343 | "TARGET_64BIT" | |
8554d9a4 | 15344 | "{rep\;stosq|rep stosq}" |
0945b39d JH |
15345 | [(set_attr "type" "str") |
15346 | (set_attr "prefix_rep" "1") | |
15347 | (set_attr "memory" "store") | |
15348 | (set_attr "mode" "DI")]) | |
15349 | ||
e2e52e1b JH |
15350 | (define_insn "rep_stossi" |
15351 | [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0)) | |
e2e52e1b | 15352 | (set (match_operand:SI 0 "register_operand" "=D") |
b1cdafbb JH |
15353 | (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1") |
15354 | (const_int 2)) | |
15355 | (match_operand:SI 3 "register_operand" "0"))) | |
e2e52e1b | 15356 | (set (mem:BLK (match_dup 3)) |
0ae40045 | 15357 | (const_int 0)) |
b1cdafbb JH |
15358 | (use (match_operand:SI 2 "register_operand" "a")) |
15359 | (use (match_dup 4)) | |
e2e52e1b | 15360 | (use (reg:SI 19))] |
0945b39d | 15361 | "!TARGET_64BIT" |
8554d9a4 | 15362 | "{rep\;stosl|rep stosd}" |
0945b39d JH |
15363 | [(set_attr "type" "str") |
15364 | (set_attr "prefix_rep" "1") | |
15365 | (set_attr "memory" "store") | |
15366 | (set_attr "mode" "SI")]) | |
15367 | ||
15368 | (define_insn "rep_stossi_rex64" | |
15369 | [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) | |
15370 | (set (match_operand:DI 0 "register_operand" "=D") | |
15371 | (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1") | |
15372 | (const_int 2)) | |
15373 | (match_operand:DI 3 "register_operand" "0"))) | |
15374 | (set (mem:BLK (match_dup 3)) | |
15375 | (const_int 0)) | |
15376 | (use (match_operand:SI 2 "register_operand" "a")) | |
15377 | (use (match_dup 4)) | |
15378 | (use (reg:SI 19))] | |
15379 | "TARGET_64BIT" | |
8554d9a4 | 15380 | "{rep\;stosl|rep stosd}" |
e2e52e1b | 15381 | [(set_attr "type" "str") |
6ef67412 JH |
15382 | (set_attr "prefix_rep" "1") |
15383 | (set_attr "memory" "store") | |
15384 | (set_attr "mode" "SI")]) | |
0ae40045 | 15385 | |
e2e52e1b JH |
15386 | (define_insn "rep_stosqi" |
15387 | [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0)) | |
e2e52e1b | 15388 | (set (match_operand:SI 0 "register_operand" "=D") |
b1cdafbb JH |
15389 | (plus:SI (match_operand:SI 3 "register_operand" "0") |
15390 | (match_operand:SI 4 "register_operand" "1"))) | |
e2e52e1b JH |
15391 | (set (mem:BLK (match_dup 3)) |
15392 | (const_int 0)) | |
b1cdafbb JH |
15393 | (use (match_operand:QI 2 "register_operand" "a")) |
15394 | (use (match_dup 4)) | |
e2e52e1b | 15395 | (use (reg:SI 19))] |
0945b39d | 15396 | "!TARGET_64BIT" |
8554d9a4 | 15397 | "{rep\;stosb|rep stosb}" |
0945b39d JH |
15398 | [(set_attr "type" "str") |
15399 | (set_attr "prefix_rep" "1") | |
15400 | (set_attr "memory" "store") | |
15401 | (set_attr "mode" "QI")]) | |
15402 | ||
15403 | (define_insn "rep_stosqi_rex64" | |
15404 | [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) | |
15405 | (set (match_operand:DI 0 "register_operand" "=D") | |
15406 | (plus:DI (match_operand:DI 3 "register_operand" "0") | |
15407 | (match_operand:DI 4 "register_operand" "1"))) | |
15408 | (set (mem:BLK (match_dup 3)) | |
15409 | (const_int 0)) | |
15410 | (use (match_operand:QI 2 "register_operand" "a")) | |
15411 | (use (match_dup 4)) | |
15412 | (use (reg:DI 19))] | |
15413 | "TARGET_64BIT" | |
8554d9a4 | 15414 | "{rep\;stosb|rep stosb}" |
e2e52e1b | 15415 | [(set_attr "type" "str") |
6ef67412 JH |
15416 | (set_attr "prefix_rep" "1") |
15417 | (set_attr "memory" "store") | |
15418 | (set_attr "mode" "QI")]) | |
0ae40045 | 15419 | |
886c62d1 | 15420 | (define_expand "cmpstrsi" |
e075ae69 RH |
15421 | [(set (match_operand:SI 0 "register_operand" "") |
15422 | (compare:SI (match_operand:BLK 1 "general_operand" "") | |
15423 | (match_operand:BLK 2 "general_operand" ""))) | |
0945b39d JH |
15424 | (use (match_operand 3 "general_operand" "")) |
15425 | (use (match_operand 4 "immediate_operand" ""))] | |
886c62d1 | 15426 | "" |
886c62d1 | 15427 | { |
e075ae69 RH |
15428 | rtx addr1, addr2, out, outlow, count, countreg, align; |
15429 | ||
15430 | out = operands[0]; | |
15431 | if (GET_CODE (out) != REG) | |
15432 | out = gen_reg_rtx (SImode); | |
783cdf65 JVA |
15433 | |
15434 | addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); | |
15435 | addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); | |
e075ae69 RH |
15436 | |
15437 | count = operands[3]; | |
d24b3457 | 15438 | countreg = ix86_zero_extend_to_Pmode (count); |
e075ae69 RH |
15439 | |
15440 | /* %%% Iff we are testing strict equality, we can use known alignment | |
15441 | to good advantage. This may be possible with combine, particularly | |
15442 | once cc0 is dead. */ | |
15443 | align = operands[4]; | |
783cdf65 | 15444 | |
7c7ef435 | 15445 | emit_insn (gen_cld ()); |
e075ae69 RH |
15446 | if (GET_CODE (count) == CONST_INT) |
15447 | { | |
15448 | if (INTVAL (count) == 0) | |
15449 | { | |
15450 | emit_move_insn (operands[0], const0_rtx); | |
15451 | DONE; | |
15452 | } | |
0945b39d JH |
15453 | if (TARGET_64BIT) |
15454 | emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align, | |
15455 | addr1, addr2, countreg)); | |
15456 | else | |
15457 | emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align, | |
15458 | addr1, addr2, countreg)); | |
e075ae69 RH |
15459 | } |
15460 | else | |
e2e52e1b | 15461 | { |
0945b39d JH |
15462 | if (TARGET_64BIT) |
15463 | { | |
15464 | emit_insn (gen_cmpdi_1_rex64 (countreg, countreg)); | |
15465 | emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align, | |
15466 | addr1, addr2, countreg)); | |
15467 | } | |
15468 | else | |
15469 | { | |
15470 | emit_insn (gen_cmpsi_1 (countreg, countreg)); | |
15471 | emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align, | |
15472 | addr1, addr2, countreg)); | |
15473 | } | |
e2e52e1b | 15474 | } |
e075ae69 RH |
15475 | |
15476 | outlow = gen_lowpart (QImode, out); | |
15477 | emit_insn (gen_cmpintqi (outlow)); | |
15478 | emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow)); | |
783cdf65 | 15479 | |
e075ae69 RH |
15480 | if (operands[0] != out) |
15481 | emit_move_insn (operands[0], out); | |
783cdf65 | 15482 | |
e075ae69 | 15483 | DONE; |
0f40f9f7 | 15484 | }) |
886c62d1 | 15485 | |
e075ae69 RH |
15486 | ;; Produce a tri-state integer (-1, 0, 1) from condition codes. |
15487 | ||
15488 | (define_expand "cmpintqi" | |
15489 | [(set (match_dup 1) | |
15490 | (gtu:QI (reg:CC 17) (const_int 0))) | |
15491 | (set (match_dup 2) | |
15492 | (ltu:QI (reg:CC 17) (const_int 0))) | |
15493 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
15494 | (minus:QI (match_dup 1) | |
15495 | (match_dup 2))) | |
15496 | (clobber (reg:CC 17))])] | |
15497 | "" | |
15498 | "operands[1] = gen_reg_rtx (QImode); | |
15499 | operands[2] = gen_reg_rtx (QImode);") | |
15500 | ||
f76e3b05 JVA |
15501 | ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is |
15502 | ;; zero. Emit extra code to make sure that a zero-length compare is EQ. | |
56c0e8fa | 15503 | |
0945b39d | 15504 | (define_insn "cmpstrqi_nz_1" |
e075ae69 | 15505 | [(set (reg:CC 17) |
b1cdafbb JH |
15506 | (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0")) |
15507 | (mem:BLK (match_operand:SI 5 "register_operand" "1")))) | |
15508 | (use (match_operand:SI 6 "register_operand" "2")) | |
886c62d1 | 15509 | (use (match_operand:SI 3 "immediate_operand" "i")) |
7c7ef435 | 15510 | (use (reg:SI 19)) |
b1cdafbb JH |
15511 | (clobber (match_operand:SI 0 "register_operand" "=S")) |
15512 | (clobber (match_operand:SI 1 "register_operand" "=D")) | |
15513 | (clobber (match_operand:SI 2 "register_operand" "=c"))] | |
0945b39d JH |
15514 | "!TARGET_64BIT" |
15515 | "repz{\;| }cmpsb" | |
15516 | [(set_attr "type" "str") | |
15517 | (set_attr "mode" "QI") | |
15518 | (set_attr "prefix_rep" "1")]) | |
15519 | ||
15520 | (define_insn "cmpstrqi_nz_rex_1" | |
15521 | [(set (reg:CC 17) | |
15522 | (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0")) | |
15523 | (mem:BLK (match_operand:DI 5 "register_operand" "1")))) | |
15524 | (use (match_operand:DI 6 "register_operand" "2")) | |
15525 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
15526 | (use (reg:SI 19)) | |
15527 | (clobber (match_operand:DI 0 "register_operand" "=S")) | |
15528 | (clobber (match_operand:DI 1 "register_operand" "=D")) | |
15529 | (clobber (match_operand:DI 2 "register_operand" "=c"))] | |
15530 | "TARGET_64BIT" | |
7c7ef435 | 15531 | "repz{\;| }cmpsb" |
e2e52e1b | 15532 | [(set_attr "type" "str") |
6ef67412 JH |
15533 | (set_attr "mode" "QI") |
15534 | (set_attr "prefix_rep" "1")]) | |
886c62d1 | 15535 | |
e075ae69 | 15536 | ;; The same, but the count is not known to not be zero. |
886c62d1 | 15537 | |
0945b39d | 15538 | (define_insn "cmpstrqi_1" |
e075ae69 | 15539 | [(set (reg:CC 17) |
b1cdafbb | 15540 | (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2") |
e075ae69 | 15541 | (const_int 0)) |
2bed3391 | 15542 | (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0")) |
b1cdafbb | 15543 | (mem:BLK (match_operand:SI 5 "register_operand" "1"))) |
e075ae69 RH |
15544 | (const_int 0))) |
15545 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
e2e52e1b | 15546 | (use (reg:CC 17)) |
7c7ef435 | 15547 | (use (reg:SI 19)) |
b1cdafbb JH |
15548 | (clobber (match_operand:SI 0 "register_operand" "=S")) |
15549 | (clobber (match_operand:SI 1 "register_operand" "=D")) | |
15550 | (clobber (match_operand:SI 2 "register_operand" "=c"))] | |
0945b39d JH |
15551 | "!TARGET_64BIT" |
15552 | "repz{\;| }cmpsb" | |
15553 | [(set_attr "type" "str") | |
15554 | (set_attr "mode" "QI") | |
15555 | (set_attr "prefix_rep" "1")]) | |
15556 | ||
15557 | (define_insn "cmpstrqi_rex_1" | |
15558 | [(set (reg:CC 17) | |
15559 | (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2") | |
15560 | (const_int 0)) | |
15561 | (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0")) | |
15562 | (mem:BLK (match_operand:DI 5 "register_operand" "1"))) | |
15563 | (const_int 0))) | |
15564 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
15565 | (use (reg:CC 17)) | |
15566 | (use (reg:SI 19)) | |
15567 | (clobber (match_operand:DI 0 "register_operand" "=S")) | |
15568 | (clobber (match_operand:DI 1 "register_operand" "=D")) | |
15569 | (clobber (match_operand:DI 2 "register_operand" "=c"))] | |
15570 | "TARGET_64BIT" | |
e2e52e1b JH |
15571 | "repz{\;| }cmpsb" |
15572 | [(set_attr "type" "str") | |
6ef67412 JH |
15573 | (set_attr "mode" "QI") |
15574 | (set_attr "prefix_rep" "1")]) | |
886c62d1 | 15575 | |
e075ae69 RH |
15576 | (define_expand "strlensi" |
15577 | [(set (match_operand:SI 0 "register_operand" "") | |
15578 | (unspec:SI [(match_operand:BLK 1 "general_operand" "") | |
15579 | (match_operand:QI 2 "immediate_operand" "") | |
0945b39d | 15580 | (match_operand 3 "immediate_operand" "")] 0))] |
886c62d1 | 15581 | "" |
886c62d1 | 15582 | { |
0945b39d JH |
15583 | if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3])) |
15584 | DONE; | |
15585 | else | |
15586 | FAIL; | |
0f40f9f7 | 15587 | }) |
e075ae69 | 15588 | |
0945b39d JH |
15589 | (define_expand "strlendi" |
15590 | [(set (match_operand:DI 0 "register_operand" "") | |
15591 | (unspec:DI [(match_operand:BLK 1 "general_operand" "") | |
15592 | (match_operand:QI 2 "immediate_operand" "") | |
15593 | (match_operand 3 "immediate_operand" "")] 0))] | |
15594 | "" | |
0945b39d JH |
15595 | { |
15596 | if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3])) | |
15597 | DONE; | |
15598 | else | |
15599 | FAIL; | |
0f40f9f7 | 15600 | }) |
19c3fc24 | 15601 | |
0945b39d | 15602 | (define_insn "strlenqi_1" |
e075ae69 | 15603 | [(set (match_operand:SI 0 "register_operand" "=&c") |
b1cdafbb | 15604 | (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1")) |
0945b39d | 15605 | (match_operand:QI 2 "register_operand" "a") |
e075ae69 | 15606 | (match_operand:SI 3 "immediate_operand" "i") |
0945b39d | 15607 | (match_operand:SI 4 "register_operand" "0")] 0)) |
7c7ef435 | 15608 | (use (reg:SI 19)) |
b1cdafbb | 15609 | (clobber (match_operand:SI 1 "register_operand" "=D")) |
e075ae69 | 15610 | (clobber (reg:CC 17))] |
0945b39d JH |
15611 | "!TARGET_64BIT" |
15612 | "repnz{\;| }scasb" | |
15613 | [(set_attr "type" "str") | |
15614 | (set_attr "mode" "QI") | |
15615 | (set_attr "prefix_rep" "1")]) | |
15616 | ||
15617 | (define_insn "strlenqi_rex_1" | |
15618 | [(set (match_operand:DI 0 "register_operand" "=&c") | |
15619 | (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1")) | |
15620 | (match_operand:QI 2 "register_operand" "a") | |
15621 | (match_operand:DI 3 "immediate_operand" "i") | |
15622 | (match_operand:DI 4 "register_operand" "0")] 0)) | |
15623 | (use (reg:SI 19)) | |
15624 | (clobber (match_operand:DI 1 "register_operand" "=D")) | |
15625 | (clobber (reg:CC 17))] | |
15626 | "TARGET_64BIT" | |
7c7ef435 | 15627 | "repnz{\;| }scasb" |
e2e52e1b | 15628 | [(set_attr "type" "str") |
6ef67412 JH |
15629 | (set_attr "mode" "QI") |
15630 | (set_attr "prefix_rep" "1")]) | |
a3e991f2 ZW |
15631 | |
15632 | ;; Peephole optimizations to clean up after cmpstr*. This should be | |
15633 | ;; handled in combine, but it is not currently up to the task. | |
15634 | ;; When used for their truth value, the cmpstr* expanders generate | |
15635 | ;; code like this: | |
15636 | ;; | |
15637 | ;; repz cmpsb | |
15638 | ;; seta %al | |
15639 | ;; setb %dl | |
15640 | ;; cmpb %al, %dl | |
15641 | ;; jcc label | |
15642 | ;; | |
15643 | ;; The intermediate three instructions are unnecessary. | |
15644 | ||
15645 | ;; This one handles cmpstr*_nz_1... | |
15646 | (define_peephole2 | |
15647 | [(parallel[ | |
15648 | (set (reg:CC 17) | |
15649 | (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) | |
15650 | (mem:BLK (match_operand 5 "register_operand" "")))) | |
15651 | (use (match_operand 6 "register_operand" "")) | |
15652 | (use (match_operand:SI 3 "immediate_operand" "")) | |
15653 | (use (reg:SI 19)) | |
15654 | (clobber (match_operand 0 "register_operand" "")) | |
15655 | (clobber (match_operand 1 "register_operand" "")) | |
15656 | (clobber (match_operand 2 "register_operand" ""))]) | |
15657 | (set (match_operand:QI 7 "register_operand" "") | |
15658 | (gtu:QI (reg:CC 17) (const_int 0))) | |
15659 | (set (match_operand:QI 8 "register_operand" "") | |
15660 | (ltu:QI (reg:CC 17) (const_int 0))) | |
15661 | (set (reg 17) | |
15662 | (compare (match_dup 7) (match_dup 8))) | |
15663 | ] | |
244ec848 | 15664 | "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])" |
a3e991f2 ZW |
15665 | [(parallel[ |
15666 | (set (reg:CC 17) | |
15667 | (compare:CC (mem:BLK (match_dup 4)) | |
15668 | (mem:BLK (match_dup 5)))) | |
15669 | (use (match_dup 6)) | |
15670 | (use (match_dup 3)) | |
15671 | (use (reg:SI 19)) | |
15672 | (clobber (match_dup 0)) | |
15673 | (clobber (match_dup 1)) | |
244ec848 | 15674 | (clobber (match_dup 2))])] |
a3e991f2 ZW |
15675 | "") |
15676 | ||
15677 | ;; ...and this one handles cmpstr*_1. | |
15678 | (define_peephole2 | |
15679 | [(parallel[ | |
15680 | (set (reg:CC 17) | |
15681 | (if_then_else:CC (ne (match_operand 6 "register_operand" "") | |
15682 | (const_int 0)) | |
15683 | (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) | |
15684 | (mem:BLK (match_operand 5 "register_operand" ""))) | |
15685 | (const_int 0))) | |
15686 | (use (match_operand:SI 3 "immediate_operand" "")) | |
15687 | (use (reg:CC 17)) | |
15688 | (use (reg:SI 19)) | |
15689 | (clobber (match_operand 0 "register_operand" "")) | |
15690 | (clobber (match_operand 1 "register_operand" "")) | |
15691 | (clobber (match_operand 2 "register_operand" ""))]) | |
15692 | (set (match_operand:QI 7 "register_operand" "") | |
15693 | (gtu:QI (reg:CC 17) (const_int 0))) | |
15694 | (set (match_operand:QI 8 "register_operand" "") | |
15695 | (ltu:QI (reg:CC 17) (const_int 0))) | |
15696 | (set (reg 17) | |
15697 | (compare (match_dup 7) (match_dup 8))) | |
15698 | ] | |
244ec848 | 15699 | "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])" |
a3e991f2 ZW |
15700 | [(parallel[ |
15701 | (set (reg:CC 17) | |
15702 | (if_then_else:CC (ne (match_dup 6) | |
15703 | (const_int 0)) | |
15704 | (compare:CC (mem:BLK (match_dup 4)) | |
15705 | (mem:BLK (match_dup 5))) | |
15706 | (const_int 0))) | |
15707 | (use (match_dup 3)) | |
15708 | (use (reg:CC 17)) | |
15709 | (use (reg:SI 19)) | |
15710 | (clobber (match_dup 0)) | |
15711 | (clobber (match_dup 1)) | |
244ec848 | 15712 | (clobber (match_dup 2))])] |
a3e991f2 ZW |
15713 | "") |
15714 | ||
15715 | ||
e075ae69 RH |
15716 | \f |
15717 | ;; Conditional move instructions. | |
726e2d54 | 15718 | |
44cf5b6a | 15719 | (define_expand "movdicc" |
885a70fd JH |
15720 | [(set (match_operand:DI 0 "register_operand" "") |
15721 | (if_then_else:DI (match_operand 1 "comparison_operator" "") | |
44cf5b6a JH |
15722 | (match_operand:DI 2 "general_operand" "") |
15723 | (match_operand:DI 3 "general_operand" "")))] | |
885a70fd JH |
15724 | "TARGET_64BIT" |
15725 | "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;") | |
15726 | ||
e74061a9 | 15727 | (define_insn "x86_movdicc_0_m1_rex64" |
885a70fd JH |
15728 | [(set (match_operand:DI 0 "register_operand" "=r") |
15729 | (if_then_else:DI (ltu (reg:CC 17) (const_int 0)) | |
15730 | (const_int -1) | |
15731 | (const_int 0))) | |
15732 | (clobber (reg:CC 17))] | |
15733 | "TARGET_64BIT" | |
0f40f9f7 | 15734 | "sbb{q}\t%0, %0" |
885a70fd JH |
15735 | ; Since we don't have the proper number of operands for an alu insn, |
15736 | ; fill in all the blanks. | |
15737 | [(set_attr "type" "alu") | |
15738 | (set_attr "memory" "none") | |
15739 | (set_attr "imm_disp" "false") | |
15740 | (set_attr "mode" "DI") | |
15741 | (set_attr "length_immediate" "0")]) | |
15742 | ||
15743 | (define_insn "*movdicc_c_rex64" | |
15744 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
15745 | (if_then_else:DI (match_operator 1 "ix86_comparison_operator" | |
15746 | [(reg 17) (const_int 0)]) | |
15747 | (match_operand:DI 2 "nonimmediate_operand" "rm,0") | |
15748 | (match_operand:DI 3 "nonimmediate_operand" "0,rm")))] | |
15749 | "TARGET_64BIT && TARGET_CMOVE | |
15750 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
15751 | "@ | |
0f40f9f7 ZW |
15752 | cmov%C1\t{%2, %0|%0, %2} |
15753 | cmov%c1\t{%3, %0|%0, %3}" | |
885a70fd JH |
15754 | [(set_attr "type" "icmov") |
15755 | (set_attr "mode" "DI")]) | |
15756 | ||
e075ae69 | 15757 | (define_expand "movsicc" |
6a4a5d95 | 15758 | [(set (match_operand:SI 0 "register_operand" "") |
e075ae69 RH |
15759 | (if_then_else:SI (match_operand 1 "comparison_operator" "") |
15760 | (match_operand:SI 2 "general_operand" "") | |
15761 | (match_operand:SI 3 "general_operand" "")))] | |
15762 | "" | |
15763 | "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;") | |
726e2d54 | 15764 | |
e075ae69 RH |
15765 | ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing |
15766 | ;; the register first winds up with `sbbl $0,reg', which is also weird. | |
15767 | ;; So just document what we're doing explicitly. | |
15768 | ||
15769 | (define_insn "x86_movsicc_0_m1" | |
15770 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15771 | (if_then_else:SI (ltu (reg:CC 17) (const_int 0)) | |
15772 | (const_int -1) | |
15773 | (const_int 0))) | |
15774 | (clobber (reg:CC 17))] | |
15775 | "" | |
0f40f9f7 | 15776 | "sbb{l}\t%0, %0" |
e075ae69 RH |
15777 | ; Since we don't have the proper number of operands for an alu insn, |
15778 | ; fill in all the blanks. | |
15779 | [(set_attr "type" "alu") | |
15780 | (set_attr "memory" "none") | |
15781 | (set_attr "imm_disp" "false") | |
6ef67412 JH |
15782 | (set_attr "mode" "SI") |
15783 | (set_attr "length_immediate" "0")]) | |
e075ae69 | 15784 | |
6343a50e | 15785 | (define_insn "*movsicc_noc" |
e075ae69 | 15786 | [(set (match_operand:SI 0 "register_operand" "=r,r") |
9076b9c1 | 15787 | (if_then_else:SI (match_operator 1 "ix86_comparison_operator" |
e075ae69 RH |
15788 | [(reg 17) (const_int 0)]) |
15789 | (match_operand:SI 2 "nonimmediate_operand" "rm,0") | |
15790 | (match_operand:SI 3 "nonimmediate_operand" "0,rm")))] | |
d525dfdf JH |
15791 | "TARGET_CMOVE |
15792 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
e075ae69 | 15793 | "@ |
0f40f9f7 ZW |
15794 | cmov%C1\t{%2, %0|%0, %2} |
15795 | cmov%c1\t{%3, %0|%0, %3}" | |
6ef67412 JH |
15796 | [(set_attr "type" "icmov") |
15797 | (set_attr "mode" "SI")]) | |
726e2d54 | 15798 | |
726e2d54 JW |
15799 | (define_expand "movhicc" |
15800 | [(set (match_operand:HI 0 "register_operand" "") | |
15801 | (if_then_else:HI (match_operand 1 "comparison_operator" "") | |
15802 | (match_operand:HI 2 "nonimmediate_operand" "") | |
15803 | (match_operand:HI 3 "nonimmediate_operand" "")))] | |
d9f32422 | 15804 | "TARGET_CMOVE && TARGET_HIMODE_MATH" |
e075ae69 | 15805 | "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;") |
726e2d54 | 15806 | |
6343a50e | 15807 | (define_insn "*movhicc_noc" |
e075ae69 | 15808 | [(set (match_operand:HI 0 "register_operand" "=r,r") |
9076b9c1 | 15809 | (if_then_else:HI (match_operator 1 "ix86_comparison_operator" |
e075ae69 RH |
15810 | [(reg 17) (const_int 0)]) |
15811 | (match_operand:HI 2 "nonimmediate_operand" "rm,0") | |
15812 | (match_operand:HI 3 "nonimmediate_operand" "0,rm")))] | |
d525dfdf JH |
15813 | "TARGET_CMOVE |
15814 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
e075ae69 | 15815 | "@ |
0f40f9f7 ZW |
15816 | cmov%C1\t{%2, %0|%0, %2} |
15817 | cmov%c1\t{%3, %0|%0, %3}" | |
6ef67412 JH |
15818 | [(set_attr "type" "icmov") |
15819 | (set_attr "mode" "HI")]) | |
726e2d54 | 15820 | |
56710e42 | 15821 | (define_expand "movsfcc" |
726e2d54 | 15822 | [(set (match_operand:SF 0 "register_operand" "") |
56710e42 | 15823 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
e5e809f4 JL |
15824 | (match_operand:SF 2 "register_operand" "") |
15825 | (match_operand:SF 3 "register_operand" "")))] | |
726e2d54 | 15826 | "TARGET_CMOVE" |
e075ae69 | 15827 | "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") |
726e2d54 | 15828 | |
6343a50e | 15829 | (define_insn "*movsfcc_1" |
7093c9ea | 15830 | [(set (match_operand:SF 0 "register_operand" "=f,f,r,r") |
e075ae69 RH |
15831 | (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" |
15832 | [(reg 17) (const_int 0)]) | |
7093c9ea JH |
15833 | (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0") |
15834 | (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))] | |
15835 | "TARGET_CMOVE | |
15836 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
e075ae69 | 15837 | "@ |
0f40f9f7 ZW |
15838 | fcmov%F1\t{%2, %0|%0, %2} |
15839 | fcmov%f1\t{%3, %0|%0, %3} | |
15840 | cmov%C1\t{%2, %0|%0, %2} | |
15841 | cmov%c1\t{%3, %0|%0, %3}" | |
7093c9ea JH |
15842 | [(set_attr "type" "fcmov,fcmov,icmov,icmov") |
15843 | (set_attr "mode" "SF,SF,SI,SI")]) | |
56710e42 SC |
15844 | |
15845 | (define_expand "movdfcc" | |
726e2d54 | 15846 | [(set (match_operand:DF 0 "register_operand" "") |
56710e42 | 15847 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
e5e809f4 JL |
15848 | (match_operand:DF 2 "register_operand" "") |
15849 | (match_operand:DF 3 "register_operand" "")))] | |
726e2d54 | 15850 | "TARGET_CMOVE" |
e075ae69 | 15851 | "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") |
726e2d54 | 15852 | |
6343a50e | 15853 | (define_insn "*movdfcc_1" |
7093c9ea | 15854 | [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r") |
e075ae69 RH |
15855 | (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" |
15856 | [(reg 17) (const_int 0)]) | |
7093c9ea JH |
15857 | (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0") |
15858 | (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))] | |
1b0c37d7 | 15859 | "!TARGET_64BIT && TARGET_CMOVE |
7093c9ea | 15860 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" |
e075ae69 | 15861 | "@ |
0f40f9f7 ZW |
15862 | fcmov%F1\t{%2, %0|%0, %2} |
15863 | fcmov%f1\t{%3, %0|%0, %3} | |
7093c9ea JH |
15864 | # |
15865 | #" | |
15866 | [(set_attr "type" "fcmov,fcmov,multi,multi") | |
6ef67412 | 15867 | (set_attr "mode" "DF")]) |
56710e42 | 15868 | |
1e07edd3 JH |
15869 | (define_insn "*movdfcc_1_rex64" |
15870 | [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r") | |
15871 | (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" | |
15872 | [(reg 17) (const_int 0)]) | |
15873 | (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0") | |
15874 | (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))] | |
1b0c37d7 | 15875 | "TARGET_64BIT && TARGET_CMOVE |
1e07edd3 JH |
15876 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" |
15877 | "@ | |
0f40f9f7 ZW |
15878 | fcmov%F1\t{%2, %0|%0, %2} |
15879 | fcmov%f1\t{%3, %0|%0, %3} | |
15880 | cmov%C1\t{%2, %0|%0, %2} | |
15881 | cmov%c1\t{%3, %0|%0, %3}" | |
1e07edd3 JH |
15882 | [(set_attr "type" "fcmov,fcmov,icmov,icmov") |
15883 | (set_attr "mode" "DF")]) | |
15884 | ||
7093c9ea JH |
15885 | (define_split |
15886 | [(set (match_operand:DF 0 "register_operand" "") | |
15887 | (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" | |
15888 | [(match_operand 4 "" "") (const_int 0)]) | |
15889 | (match_operand:DF 2 "nonimmediate_operand" "") | |
15890 | (match_operand:DF 3 "nonimmediate_operand" "")))] | |
1b0c37d7 | 15891 | "!TARGET_64BIT && !ANY_FP_REG_P (operands[0]) && reload_completed" |
7093c9ea JH |
15892 | [(set (match_dup 2) |
15893 | (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)]) | |
15894 | (match_dup 5) | |
15895 | (match_dup 7))) | |
15896 | (set (match_dup 3) | |
15897 | (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)]) | |
15898 | (match_dup 6) | |
15899 | (match_dup 8)))] | |
15900 | "split_di (operands+2, 1, operands+5, operands+6); | |
15901 | split_di (operands+3, 1, operands+7, operands+8); | |
15902 | split_di (operands, 1, operands+2, operands+3);") | |
15903 | ||
56710e42 | 15904 | (define_expand "movxfcc" |
726e2d54 | 15905 | [(set (match_operand:XF 0 "register_operand" "") |
56710e42 | 15906 | (if_then_else:XF (match_operand 1 "comparison_operator" "") |
e5e809f4 JL |
15907 | (match_operand:XF 2 "register_operand" "") |
15908 | (match_operand:XF 3 "register_operand" "")))] | |
1b0c37d7 | 15909 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 | 15910 | "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") |
726e2d54 | 15911 | |
2b589241 JH |
15912 | (define_expand "movtfcc" |
15913 | [(set (match_operand:TF 0 "register_operand" "") | |
15914 | (if_then_else:TF (match_operand 1 "comparison_operator" "") | |
15915 | (match_operand:TF 2 "register_operand" "") | |
15916 | (match_operand:TF 3 "register_operand" "")))] | |
15917 | "TARGET_CMOVE" | |
15918 | "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") | |
15919 | ||
6343a50e | 15920 | (define_insn "*movxfcc_1" |
3aeae608 | 15921 | [(set (match_operand:XF 0 "register_operand" "=f,f") |
e075ae69 RH |
15922 | (if_then_else:XF (match_operator 1 "fcmov_comparison_operator" |
15923 | [(reg 17) (const_int 0)]) | |
3aeae608 JW |
15924 | (match_operand:XF 2 "register_operand" "f,0") |
15925 | (match_operand:XF 3 "register_operand" "0,f")))] | |
1b0c37d7 | 15926 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 | 15927 | "@ |
0f40f9f7 ZW |
15928 | fcmov%F1\t{%2, %0|%0, %2} |
15929 | fcmov%f1\t{%3, %0|%0, %3}" | |
6ef67412 JH |
15930 | [(set_attr "type" "fcmov") |
15931 | (set_attr "mode" "XF")]) | |
2b589241 JH |
15932 | |
15933 | (define_insn "*movtfcc_1" | |
15934 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
15935 | (if_then_else:TF (match_operator 1 "fcmov_comparison_operator" | |
15936 | [(reg 17) (const_int 0)]) | |
15937 | (match_operand:TF 2 "register_operand" "f,0") | |
15938 | (match_operand:TF 3 "register_operand" "0,f")))] | |
15939 | "TARGET_CMOVE" | |
15940 | "@ | |
0f40f9f7 ZW |
15941 | fcmov%F1\t{%2, %0|%0, %2} |
15942 | fcmov%f1\t{%3, %0|%0, %3}" | |
2b589241 JH |
15943 | [(set_attr "type" "fcmov") |
15944 | (set_attr "mode" "XF")]) | |
7ada6625 JH |
15945 | |
15946 | (define_expand "minsf3" | |
15947 | [(parallel [ | |
15948 | (set (match_operand:SF 0 "register_operand" "") | |
15949 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") | |
15950 | (match_operand:SF 2 "nonimmediate_operand" "")) | |
15951 | (match_dup 1) | |
15952 | (match_dup 2))) | |
15953 | (clobber (reg:CC 17))])] | |
15954 | "TARGET_SSE" | |
15955 | "") | |
15956 | ||
15957 | (define_insn "*minsf" | |
15958 | [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x") | |
15959 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x") | |
15960 | (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0")) | |
15961 | (match_dup 1) | |
15962 | (match_dup 2))) | |
15963 | (clobber (reg:CC 17))] | |
15964 | "TARGET_SSE && TARGET_IEEE_FP" | |
15965 | "#") | |
15966 | ||
15967 | (define_insn "*minsf_nonieee" | |
15968 | [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") | |
15969 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0") | |
3987b9db | 15970 | (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) |
7ada6625 JH |
15971 | (match_dup 1) |
15972 | (match_dup 2))) | |
15973 | (clobber (reg:CC 17))] | |
15974 | "TARGET_SSE && !TARGET_IEEE_FP" | |
15975 | "#") | |
15976 | ||
15977 | (define_split | |
15978 | [(set (match_operand:SF 0 "register_operand" "") | |
15979 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") | |
15980 | (match_operand:SF 2 "nonimmediate_operand" "")) | |
138b7342 JH |
15981 | (match_operand:SF 3 "register_operand" "") |
15982 | (match_operand:SF 4 "nonimmediate_operand" ""))) | |
ef6257cd JH |
15983 | (clobber (reg:CC 17))] |
15984 | "SSE_REG_P (operands[0]) && reload_completed | |
15985 | && ((operands_match_p (operands[1], operands[3]) | |
15986 | && operands_match_p (operands[2], operands[4])) | |
15987 | || (operands_match_p (operands[1], operands[4]) | |
15988 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
15989 | [(set (match_dup 0) |
15990 | (if_then_else:SF (lt (match_dup 1) | |
15991 | (match_dup 2)) | |
15992 | (match_dup 1) | |
15993 | (match_dup 2)))]) | |
15994 | ||
15995 | ;; We can't represent the LT test directly. Do this by swapping the operands. | |
ef6257cd | 15996 | |
7ada6625 JH |
15997 | (define_split |
15998 | [(set (match_operand:SF 0 "register_operand" "") | |
15999 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") | |
16000 | (match_operand:SF 2 "register_operand" "")) | |
ef6257cd JH |
16001 | (match_operand:DF 3 "register_operand" "") |
16002 | (match_operand:DF 4 "register_operand" ""))) | |
16003 | (clobber (reg:CC 17))] | |
16004 | "FP_REG_P (operands[0]) && reload_completed | |
16005 | && ((operands_match_p (operands[1], operands[3]) | |
16006 | && operands_match_p (operands[2], operands[4])) | |
16007 | || (operands_match_p (operands[1], operands[4]) | |
16008 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16009 | [(set (reg:CCFP 17) |
16010 | (compare:CCFP (match_dup 2) | |
16011 | (match_dup 1))) | |
16012 | (set (match_dup 0) | |
16013 | (if_then_else:SF (ge (reg:CCFP 17) (const_int 0)) | |
16014 | (match_dup 1) | |
16015 | (match_dup 2)))]) | |
16016 | ||
16017 | (define_insn "*minsf_sse" | |
16018 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16019 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0") | |
16020 | (match_operand:SF 2 "nonimmediate_operand" "xm")) | |
16021 | (match_dup 1) | |
16022 | (match_dup 2)))] | |
16023 | "TARGET_SSE && reload_completed" | |
0f40f9f7 | 16024 | "minss\t{%2, %0|%0, %2}" |
7ada6625 JH |
16025 | [(set_attr "type" "sse") |
16026 | (set_attr "mode" "SF")]) | |
16027 | ||
16028 | (define_expand "mindf3" | |
16029 | [(parallel [ | |
16030 | (set (match_operand:DF 0 "register_operand" "") | |
16031 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") | |
16032 | (match_operand:DF 2 "nonimmediate_operand" "")) | |
16033 | (match_dup 1) | |
16034 | (match_dup 2))) | |
16035 | (clobber (reg:CC 17))])] | |
965f5423 | 16036 | "TARGET_SSE2 && TARGET_SSE_MATH" |
7ada6625 JH |
16037 | "#") |
16038 | ||
16039 | (define_insn "*mindf" | |
16040 | [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y") | |
16041 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y") | |
16042 | (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0")) | |
16043 | (match_dup 1) | |
16044 | (match_dup 2))) | |
16045 | (clobber (reg:CC 17))] | |
965f5423 | 16046 | "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH" |
7ada6625 JH |
16047 | "#") |
16048 | ||
16049 | (define_insn "*mindf_nonieee" | |
16050 | [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") | |
16051 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0") | |
3987b9db | 16052 | (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) |
7ada6625 JH |
16053 | (match_dup 1) |
16054 | (match_dup 2))) | |
16055 | (clobber (reg:CC 17))] | |
965f5423 | 16056 | "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP" |
7ada6625 JH |
16057 | "#") |
16058 | ||
16059 | (define_split | |
16060 | [(set (match_operand:DF 0 "register_operand" "") | |
16061 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") | |
16062 | (match_operand:DF 2 "nonimmediate_operand" "")) | |
ef6257cd JH |
16063 | (match_operand:DF 3 "register_operand" "") |
16064 | (match_operand:DF 4 "nonimmediate_operand" ""))) | |
16065 | (clobber (reg:CC 17))] | |
16066 | "SSE_REG_P (operands[0]) && reload_completed | |
16067 | && ((operands_match_p (operands[1], operands[3]) | |
16068 | && operands_match_p (operands[2], operands[4])) | |
16069 | || (operands_match_p (operands[1], operands[4]) | |
16070 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16071 | [(set (match_dup 0) |
16072 | (if_then_else:DF (lt (match_dup 1) | |
16073 | (match_dup 2)) | |
16074 | (match_dup 1) | |
16075 | (match_dup 2)))]) | |
16076 | ||
16077 | ;; We can't represent the LT test directly. Do this by swapping the operands. | |
16078 | (define_split | |
16079 | [(set (match_operand:DF 0 "register_operand" "") | |
16080 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") | |
16081 | (match_operand:DF 2 "register_operand" "")) | |
ef6257cd JH |
16082 | (match_operand:DF 3 "register_operand" "") |
16083 | (match_operand:DF 4 "register_operand" ""))) | |
16084 | (clobber (reg:CC 17))] | |
16085 | "FP_REG_P (operands[0]) && reload_completed | |
16086 | && ((operands_match_p (operands[1], operands[3]) | |
16087 | && operands_match_p (operands[2], operands[4])) | |
16088 | || (operands_match_p (operands[1], operands[4]) | |
16089 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16090 | [(set (reg:CCFP 17) |
16091 | (compare:CCFP (match_dup 2) | |
16092 | (match_dup 2))) | |
16093 | (set (match_dup 0) | |
16094 | (if_then_else:DF (ge (reg:CCFP 17) (const_int 0)) | |
16095 | (match_dup 1) | |
16096 | (match_dup 2)))]) | |
16097 | ||
16098 | (define_insn "*mindf_sse" | |
16099 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
16100 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0") | |
16101 | (match_operand:DF 2 "nonimmediate_operand" "Ym")) | |
16102 | (match_dup 1) | |
16103 | (match_dup 2)))] | |
965f5423 | 16104 | "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed" |
0f40f9f7 | 16105 | "minsd\t{%2, %0|%0, %2}" |
7ada6625 JH |
16106 | [(set_attr "type" "sse") |
16107 | (set_attr "mode" "DF")]) | |
16108 | ||
16109 | (define_expand "maxsf3" | |
16110 | [(parallel [ | |
16111 | (set (match_operand:SF 0 "register_operand" "") | |
16112 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") | |
16113 | (match_operand:SF 2 "nonimmediate_operand" "")) | |
16114 | (match_dup 1) | |
16115 | (match_dup 2))) | |
16116 | (clobber (reg:CC 17))])] | |
16117 | "TARGET_SSE" | |
16118 | "#") | |
16119 | ||
16120 | (define_insn "*maxsf" | |
16121 | [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x") | |
16122 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x") | |
3987b9db | 16123 | (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0")) |
7ada6625 JH |
16124 | (match_dup 1) |
16125 | (match_dup 2))) | |
16126 | (clobber (reg:CC 17))] | |
16127 | "TARGET_SSE && TARGET_IEEE_FP" | |
16128 | "#") | |
16129 | ||
16130 | (define_insn "*maxsf_nonieee" | |
16131 | [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") | |
16132 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0") | |
3987b9db | 16133 | (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) |
7ada6625 JH |
16134 | (match_dup 1) |
16135 | (match_dup 2))) | |
16136 | (clobber (reg:CC 17))] | |
16137 | "TARGET_SSE && !TARGET_IEEE_FP" | |
16138 | "#") | |
16139 | ||
16140 | (define_split | |
16141 | [(set (match_operand:SF 0 "register_operand" "") | |
16142 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") | |
16143 | (match_operand:SF 2 "nonimmediate_operand" "")) | |
ef6257cd JH |
16144 | (match_operand:SF 3 "register_operand" "") |
16145 | (match_operand:SF 4 "nonimmediate_operand" ""))) | |
16146 | (clobber (reg:CC 17))] | |
16147 | "SSE_REG_P (operands[0]) && reload_completed | |
16148 | && ((operands_match_p (operands[1], operands[3]) | |
16149 | && operands_match_p (operands[2], operands[4])) | |
16150 | || (operands_match_p (operands[1], operands[4]) | |
16151 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16152 | [(set (match_dup 0) |
16153 | (if_then_else:SF (gt (match_dup 1) | |
16154 | (match_dup 2)) | |
16155 | (match_dup 1) | |
16156 | (match_dup 2)))]) | |
16157 | ||
16158 | (define_split | |
16159 | [(set (match_operand:SF 0 "register_operand" "") | |
16160 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") | |
16161 | (match_operand:SF 2 "register_operand" "")) | |
ef6257cd JH |
16162 | (match_operand:SF 3 "register_operand" "") |
16163 | (match_operand:SF 4 "register_operand" ""))) | |
16164 | (clobber (reg:CC 17))] | |
16165 | "FP_REG_P (operands[0]) && reload_completed | |
16166 | && ((operands_match_p (operands[1], operands[3]) | |
16167 | && operands_match_p (operands[2], operands[4])) | |
16168 | || (operands_match_p (operands[1], operands[4]) | |
16169 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16170 | [(set (reg:CCFP 17) |
16171 | (compare:CCFP (match_dup 1) | |
16172 | (match_dup 2))) | |
16173 | (set (match_dup 0) | |
16174 | (if_then_else:SF (gt (reg:CCFP 17) (const_int 0)) | |
16175 | (match_dup 1) | |
16176 | (match_dup 2)))]) | |
16177 | ||
16178 | (define_insn "*maxsf_sse" | |
16179 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16180 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0") | |
16181 | (match_operand:SF 2 "nonimmediate_operand" "xm")) | |
16182 | (match_dup 1) | |
16183 | (match_dup 2)))] | |
16184 | "TARGET_SSE && reload_completed" | |
0f40f9f7 | 16185 | "maxss\t{%2, %0|%0, %2}" |
7ada6625 JH |
16186 | [(set_attr "type" "sse") |
16187 | (set_attr "mode" "SF")]) | |
16188 | ||
16189 | (define_expand "maxdf3" | |
16190 | [(parallel [ | |
16191 | (set (match_operand:DF 0 "register_operand" "") | |
16192 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") | |
16193 | (match_operand:DF 2 "nonimmediate_operand" "")) | |
16194 | (match_dup 1) | |
16195 | (match_dup 2))) | |
16196 | (clobber (reg:CC 17))])] | |
965f5423 | 16197 | "TARGET_SSE2 && TARGET_SSE_MATH" |
7ada6625 JH |
16198 | "#") |
16199 | ||
16200 | (define_insn "*maxdf" | |
16201 | [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y") | |
16202 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y") | |
3987b9db | 16203 | (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0")) |
7ada6625 JH |
16204 | (match_dup 1) |
16205 | (match_dup 2))) | |
16206 | (clobber (reg:CC 17))] | |
965f5423 | 16207 | "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP" |
7ada6625 JH |
16208 | "#") |
16209 | ||
16210 | (define_insn "*maxdf_nonieee" | |
16211 | [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") | |
16212 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0") | |
3987b9db | 16213 | (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) |
7ada6625 JH |
16214 | (match_dup 1) |
16215 | (match_dup 2))) | |
16216 | (clobber (reg:CC 17))] | |
965f5423 | 16217 | "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP" |
7ada6625 JH |
16218 | "#") |
16219 | ||
16220 | (define_split | |
16221 | [(set (match_operand:DF 0 "register_operand" "") | |
16222 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") | |
16223 | (match_operand:DF 2 "nonimmediate_operand" "")) | |
ef6257cd JH |
16224 | (match_operand:DF 3 "register_operand" "") |
16225 | (match_operand:DF 4 "nonimmediate_operand" ""))) | |
16226 | (clobber (reg:CC 17))] | |
16227 | "SSE_REG_P (operands[0]) && reload_completed | |
16228 | && ((operands_match_p (operands[1], operands[3]) | |
16229 | && operands_match_p (operands[2], operands[4])) | |
16230 | || (operands_match_p (operands[1], operands[4]) | |
16231 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16232 | [(set (match_dup 0) |
16233 | (if_then_else:DF (gt (match_dup 1) | |
16234 | (match_dup 2)) | |
16235 | (match_dup 1) | |
16236 | (match_dup 2)))]) | |
16237 | ||
16238 | (define_split | |
16239 | [(set (match_operand:DF 0 "register_operand" "") | |
16240 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") | |
16241 | (match_operand:DF 2 "register_operand" "")) | |
ef6257cd JH |
16242 | (match_operand:DF 3 "register_operand" "") |
16243 | (match_operand:DF 4 "register_operand" ""))) | |
16244 | (clobber (reg:CC 17))] | |
16245 | "FP_REG_P (operands[0]) && reload_completed | |
16246 | && ((operands_match_p (operands[1], operands[3]) | |
16247 | && operands_match_p (operands[2], operands[4])) | |
16248 | || (operands_match_p (operands[1], operands[4]) | |
16249 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16250 | [(set (reg:CCFP 17) |
16251 | (compare:CCFP (match_dup 1) | |
16252 | (match_dup 2))) | |
16253 | (set (match_dup 0) | |
16254 | (if_then_else:DF (gt (reg:CCFP 17) (const_int 0)) | |
16255 | (match_dup 1) | |
16256 | (match_dup 2)))]) | |
16257 | ||
16258 | (define_insn "*maxdf_sse" | |
16259 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
16260 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0") | |
16261 | (match_operand:DF 2 "nonimmediate_operand" "Ym")) | |
16262 | (match_dup 1) | |
16263 | (match_dup 2)))] | |
965f5423 | 16264 | "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed" |
0f40f9f7 | 16265 | "maxsd\t{%2, %0|%0, %2}" |
7ada6625 JH |
16266 | [(set_attr "type" "sse") |
16267 | (set_attr "mode" "DF")]) | |
e075ae69 RH |
16268 | \f |
16269 | ;; Misc patterns (?) | |
726e2d54 | 16270 | |
f5143c46 | 16271 | ;; This pattern exists to put a dependency on all ebp-based memory accesses. |
e075ae69 RH |
16272 | ;; Otherwise there will be nothing to keep |
16273 | ;; | |
16274 | ;; [(set (reg ebp) (reg esp))] | |
16275 | ;; [(set (reg esp) (plus (reg esp) (const_int -160000))) | |
16276 | ;; (clobber (eflags)] | |
16277 | ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))] | |
16278 | ;; | |
16279 | ;; in proper program order. | |
8362f420 JH |
16280 | (define_expand "pro_epilogue_adjust_stack" |
16281 | [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r") | |
16282 | (plus:SI (match_operand:SI 1 "register_operand" "0,r") | |
16283 | (match_operand:SI 2 "immediate_operand" "i,i"))) | |
f2042df3 RH |
16284 | (clobber (reg:CC 17)) |
16285 | (clobber (mem:BLK (scratch)))])] | |
8362f420 | 16286 | "" |
8362f420 JH |
16287 | { |
16288 | if (TARGET_64BIT) | |
16289 | { | |
f2042df3 RH |
16290 | emit_insn (gen_pro_epilogue_adjust_stack_rex64 |
16291 | (operands[0], operands[1], operands[2])); | |
8362f420 JH |
16292 | DONE; |
16293 | } | |
0f40f9f7 | 16294 | }) |
726e2d54 | 16295 | |
8362f420 | 16296 | (define_insn "*pro_epilogue_adjust_stack_1" |
1c71e60e JH |
16297 | [(set (match_operand:SI 0 "register_operand" "=r,r") |
16298 | (plus:SI (match_operand:SI 1 "register_operand" "0,r") | |
16299 | (match_operand:SI 2 "immediate_operand" "i,i"))) | |
f2042df3 RH |
16300 | (clobber (reg:CC 17)) |
16301 | (clobber (mem:BLK (scratch)))] | |
8362f420 | 16302 | "!TARGET_64BIT" |
e075ae69 | 16303 | { |
1c71e60e | 16304 | switch (get_attr_type (insn)) |
e075ae69 | 16305 | { |
1c71e60e | 16306 | case TYPE_IMOV: |
0f40f9f7 | 16307 | return "mov{l}\t{%1, %0|%0, %1}"; |
1c71e60e JH |
16308 | |
16309 | case TYPE_ALU: | |
16310 | if (GET_CODE (operands[2]) == CONST_INT | |
16311 | && (INTVAL (operands[2]) == 128 | |
16312 | || (INTVAL (operands[2]) < 0 | |
16313 | && INTVAL (operands[2]) != -128))) | |
16314 | { | |
16315 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 16316 | return "sub{l}\t{%2, %0|%0, %2}"; |
1c71e60e | 16317 | } |
0f40f9f7 | 16318 | return "add{l}\t{%2, %0|%0, %2}"; |
1c71e60e JH |
16319 | |
16320 | case TYPE_LEA: | |
16321 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
0f40f9f7 | 16322 | return "lea{l}\t{%a2, %0|%0, %a2}"; |
1c71e60e JH |
16323 | |
16324 | default: | |
16325 | abort (); | |
e075ae69 | 16326 | } |
0f40f9f7 | 16327 | } |
1c71e60e JH |
16328 | [(set (attr "type") |
16329 | (cond [(eq_attr "alternative" "0") | |
16330 | (const_string "alu") | |
16331 | (match_operand:SI 2 "const0_operand" "") | |
16332 | (const_string "imov") | |
16333 | ] | |
6ef67412 JH |
16334 | (const_string "lea"))) |
16335 | (set_attr "mode" "SI")]) | |
578b58f5 | 16336 | |
8362f420 JH |
16337 | (define_insn "pro_epilogue_adjust_stack_rex64" |
16338 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
16339 | (plus:DI (match_operand:DI 1 "register_operand" "0,r") | |
16340 | (match_operand:DI 2 "x86_64_immediate_operand" "e,e"))) | |
f2042df3 RH |
16341 | (clobber (reg:CC 17)) |
16342 | (clobber (mem:BLK (scratch)))] | |
8362f420 | 16343 | "TARGET_64BIT" |
8362f420 JH |
16344 | { |
16345 | switch (get_attr_type (insn)) | |
16346 | { | |
16347 | case TYPE_IMOV: | |
0f40f9f7 | 16348 | return "mov{q}\t{%1, %0|%0, %1}"; |
8362f420 JH |
16349 | |
16350 | case TYPE_ALU: | |
16351 | if (GET_CODE (operands[2]) == CONST_INT | |
16352 | && (INTVAL (operands[2]) == 128 | |
16353 | || (INTVAL (operands[2]) < 0 | |
16354 | && INTVAL (operands[2]) != -128))) | |
16355 | { | |
16356 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 16357 | return "sub{q}\t{%2, %0|%0, %2}"; |
8362f420 | 16358 | } |
0f40f9f7 | 16359 | return "add{q}\t{%2, %0|%0, %2}"; |
8362f420 JH |
16360 | |
16361 | case TYPE_LEA: | |
16362 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
0f40f9f7 | 16363 | return "lea{q}\t{%a2, %0|%0, %a2}"; |
8362f420 JH |
16364 | |
16365 | default: | |
16366 | abort (); | |
16367 | } | |
0f40f9f7 | 16368 | } |
8362f420 JH |
16369 | [(set (attr "type") |
16370 | (cond [(eq_attr "alternative" "0") | |
16371 | (const_string "alu") | |
16372 | (match_operand:DI 2 "const0_operand" "") | |
16373 | (const_string "imov") | |
16374 | ] | |
16375 | (const_string "lea"))) | |
16376 | (set_attr "mode" "DI")]) | |
16377 | ||
16378 | ||
d6a7951f | 16379 | ;; Placeholder for the conditional moves. This one is split either to SSE |
0073023d JH |
16380 | ;; based moves emulation or to usual cmove sequence. Little bit unfortunate |
16381 | ;; fact is that compares supported by the cmp??ss instructions are exactly | |
16382 | ;; swapped of those supported by cmove sequence. | |
fa9f36a1 JH |
16383 | ;; The EQ/NE comparisons also needs bit care, since they are not directly |
16384 | ;; supported by i387 comparisons and we do need to emit two conditional moves | |
16385 | ;; in tandem. | |
0073023d JH |
16386 | |
16387 | (define_insn "sse_movsfcc" | |
16388 | [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf") | |
16389 | (if_then_else:SF (match_operator 1 "sse_comparison_operator" | |
16390 | [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f") | |
16391 | (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")]) | |
16392 | (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx") | |
16393 | (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx"))) | |
bf71a4f8 | 16394 | (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X")) |
0073023d | 16395 | (clobber (reg:CC 17))] |
fa9f36a1 JH |
16396 | "TARGET_SSE |
16397 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) | |
16398 | && (!TARGET_IEEE_FP | |
16399 | || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" | |
16400 | "#") | |
16401 | ||
16402 | (define_insn "sse_movsfcc_eq" | |
16403 | [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf") | |
16404 | (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f") | |
16405 | (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f")) | |
16406 | (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx") | |
16407 | (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) | |
f021d6fc | 16408 | (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X")) |
fa9f36a1 | 16409 | (clobber (reg:CC 17))] |
0073023d JH |
16410 | "TARGET_SSE |
16411 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
16412 | "#") | |
16413 | ||
16414 | (define_insn "sse_movdfcc" | |
16415 | [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf") | |
16416 | (if_then_else:DF (match_operator 1 "sse_comparison_operator" | |
16417 | [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f") | |
16418 | (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")]) | |
16419 | (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx") | |
16420 | (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx"))) | |
bf71a4f8 | 16421 | (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X")) |
0073023d JH |
16422 | (clobber (reg:CC 17))] |
16423 | "TARGET_SSE2 | |
fa9f36a1 JH |
16424 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) |
16425 | && (!TARGET_IEEE_FP | |
16426 | || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" | |
16427 | "#") | |
16428 | ||
16429 | (define_insn "sse_movdfcc_eq" | |
16430 | [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf") | |
16431 | (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f") | |
16432 | (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f")) | |
16433 | (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx") | |
16434 | (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) | |
16435 | (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X")) | |
16436 | (clobber (reg:CC 17))] | |
16437 | "TARGET_SSE | |
0073023d JH |
16438 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" |
16439 | "#") | |
16440 | ||
16441 | ;; For non-sse moves just expand the usual cmove sequence. | |
16442 | (define_split | |
16443 | [(set (match_operand 0 "register_operand" "") | |
16444 | (if_then_else (match_operator 1 "comparison_operator" | |
16445 | [(match_operand 4 "nonimmediate_operand" "") | |
16446 | (match_operand 5 "register_operand" "")]) | |
16447 | (match_operand 2 "nonimmediate_operand" "") | |
16448 | (match_operand 3 "nonimmediate_operand" ""))) | |
16449 | (clobber (match_operand 6 "" "")) | |
16450 | (clobber (reg:CC 17))] | |
16451 | "!SSE_REG_P (operands[0]) && reload_completed | |
16452 | && VALID_SSE_REG_MODE (GET_MODE (operands[0]))" | |
16453 | [(const_int 0)] | |
0073023d JH |
16454 | { |
16455 | ix86_compare_op0 = operands[5]; | |
16456 | ix86_compare_op1 = operands[4]; | |
16457 | operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])), | |
16458 | VOIDmode, operands[5], operands[4]); | |
16459 | ix86_expand_fp_movcc (operands); | |
16460 | DONE; | |
0f40f9f7 | 16461 | }) |
0073023d JH |
16462 | |
16463 | ;; Split SSE based conditional move into seqence: | |
16464 | ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison | |
16465 | ;; and op2, op0 - zero op2 if comparison was false | |
16466 | ;; nand op0, op3 - load op3 to op0 if comparison was false | |
16467 | ;; or op2, op0 - get the non-zero one into the result. | |
16468 | (define_split | |
16469 | [(set (match_operand 0 "register_operand" "") | |
16470 | (if_then_else (match_operator 1 "sse_comparison_operator" | |
16471 | [(match_operand 4 "register_operand" "") | |
16472 | (match_operand 5 "nonimmediate_operand" "")]) | |
16473 | (match_operand 2 "register_operand" "") | |
16474 | (match_operand 3 "register_operand" ""))) | |
bf71a4f8 | 16475 | (clobber (match_operand 6 "" "")) |
0073023d JH |
16476 | (clobber (reg:CC 17))] |
16477 | "SSE_REG_P (operands[0]) && reload_completed" | |
16478 | [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)])) | |
16479 | (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0) | |
f021d6fc JH |
16480 | (subreg:TI (match_dup 4) 0))) |
16481 | (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0)) | |
0073023d JH |
16482 | (subreg:TI (match_dup 3) 0))) |
16483 | (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0) | |
16484 | (subreg:TI (match_dup 7) 0)))] | |
0073023d JH |
16485 | { |
16486 | PUT_MODE (operands[1], GET_MODE (operands[0])); | |
f021d6fc | 16487 | if (operands_match_p (operands[0], operands[4])) |
0073023d JH |
16488 | operands[6] = operands[4], operands[7] = operands[2]; |
16489 | else | |
f021d6fc | 16490 | operands[6] = operands[2], operands[7] = operands[4]; |
0f40f9f7 | 16491 | }) |
0073023d JH |
16492 | |
16493 | ;; Special case of conditional move we can handle effectivly. | |
16494 | ;; Do not brother with the integer/floating point case, since these are | |
16495 | ;; bot considerably slower, unlike in the generic case. | |
16496 | (define_insn "*sse_movsfcc_const0_1" | |
16497 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16498 | (if_then_else:SF (match_operator 1 "sse_comparison_operator" | |
16499 | [(match_operand:SF 4 "register_operand" "0") | |
16500 | (match_operand:SF 5 "nonimmediate_operand" "xm")]) | |
16501 | (match_operand:SF 2 "register_operand" "x") | |
16502 | (match_operand:SF 3 "const0_operand" "X")))] | |
16503 | "TARGET_SSE" | |
16504 | "#") | |
16505 | ||
16506 | (define_insn "*sse_movsfcc_const0_2" | |
16507 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16508 | (if_then_else:SF (match_operator 1 "sse_comparison_operator" | |
16509 | [(match_operand:SF 4 "register_operand" "0") | |
16510 | (match_operand:SF 5 "nonimmediate_operand" "xm")]) | |
adc7fcb8 JH |
16511 | (match_operand:SF 2 "const0_operand" "X") |
16512 | (match_operand:SF 3 "register_operand" "x")))] | |
0073023d JH |
16513 | "TARGET_SSE" |
16514 | "#") | |
16515 | ||
16516 | (define_insn "*sse_movsfcc_const0_3" | |
16517 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16518 | (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" | |
16519 | [(match_operand:SF 4 "nonimmediate_operand" "xm") | |
16520 | (match_operand:SF 5 "register_operand" "0")]) | |
16521 | (match_operand:SF 2 "register_operand" "x") | |
16522 | (match_operand:SF 3 "const0_operand" "X")))] | |
16523 | "TARGET_SSE" | |
16524 | "#") | |
16525 | ||
16526 | (define_insn "*sse_movsfcc_const0_4" | |
16527 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16528 | (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" | |
16529 | [(match_operand:SF 4 "nonimmediate_operand" "xm") | |
16530 | (match_operand:SF 5 "register_operand" "0")]) | |
adc7fcb8 JH |
16531 | (match_operand:SF 2 "const0_operand" "X") |
16532 | (match_operand:SF 3 "register_operand" "x")))] | |
0073023d JH |
16533 | "TARGET_SSE" |
16534 | "#") | |
16535 | ||
16536 | (define_insn "*sse_movdfcc_const0_1" | |
16537 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16538 | (if_then_else:SF (match_operator 1 "sse_comparison_operator" | |
16539 | [(match_operand:SF 4 "register_operand" "0") | |
16540 | (match_operand:SF 5 "nonimmediate_operand" "xm")]) | |
16541 | (match_operand:SF 2 "register_operand" "x") | |
16542 | (match_operand:SF 3 "const0_operand" "X")))] | |
16543 | "TARGET_SSE2" | |
16544 | "#") | |
16545 | ||
16546 | (define_insn "*sse_movdfcc_const0_2" | |
16547 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16548 | (if_then_else:SF (match_operator 1 "sse_comparison_operator" | |
16549 | [(match_operand:SF 4 "register_operand" "0") | |
16550 | (match_operand:SF 5 "nonimmediate_operand" "xm")]) | |
adc7fcb8 JH |
16551 | (match_operand:SF 2 "const0_operand" "X") |
16552 | (match_operand:SF 3 "register_operand" "x")))] | |
0073023d JH |
16553 | "TARGET_SSE2" |
16554 | "#") | |
16555 | ||
16556 | (define_insn "*sse_movdfcc_const0_3" | |
16557 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16558 | (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" | |
16559 | [(match_operand:SF 4 "nonimmediate_operand" "xm") | |
16560 | (match_operand:SF 5 "register_operand" "0")]) | |
16561 | (match_operand:SF 2 "register_operand" "x") | |
16562 | (match_operand:SF 3 "const0_operand" "X")))] | |
16563 | "TARGET_SSE2" | |
16564 | "#") | |
16565 | ||
16566 | (define_insn "*sse_movdfcc_const0_4" | |
16567 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16568 | (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" | |
16569 | [(match_operand:SF 4 "nonimmediate_operand" "xm") | |
16570 | (match_operand:SF 5 "register_operand" "0")]) | |
adc7fcb8 JH |
16571 | (match_operand:SF 2 "const0_operand" "X") |
16572 | (match_operand:SF 3 "register_operand" "x")))] | |
0073023d JH |
16573 | "TARGET_SSE2" |
16574 | "#") | |
16575 | ||
16576 | (define_split | |
16577 | [(set (match_operand 0 "register_operand" "") | |
16578 | (if_then_else (match_operator 1 "comparison_operator" | |
16579 | [(match_operand 4 "register_operand" "") | |
16580 | (match_operand 5 "nonimmediate_operand" "")]) | |
16581 | (match_operand 2 "nonmemory_operand" "") | |
16582 | (match_operand 3 "nonmemory_operand" "")))] | |
16583 | "SSE_REG_P (operands[0]) && reload_completed | |
16584 | && (const0_operand (operands[2], GET_MODE (operands[0])) | |
16585 | || const0_operand (operands[3], GET_MODE (operands[0])))" | |
16586 | [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)])) | |
16587 | (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6) | |
16588 | (subreg:TI (match_dup 7) 0)))] | |
0073023d JH |
16589 | { |
16590 | PUT_MODE (operands[1], GET_MODE (operands[0])); | |
16591 | if (!sse_comparison_operator (operands[1], VOIDmode)) | |
16592 | { | |
16593 | rtx tmp = operands[5]; | |
16594 | operands[5] = operands[4]; | |
16595 | operands[4] = tmp; | |
16596 | PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1]))); | |
16597 | } | |
16598 | if (const0_operand (operands[2], GET_MODE (operands[0]))) | |
16599 | { | |
16600 | operands[7] = operands[3]; | |
16601 | operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0], | |
16602 | 0)); | |
16603 | } | |
16604 | else | |
16605 | { | |
16606 | operands[7] = operands[2]; | |
16607 | operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0); | |
16608 | } | |
0f40f9f7 | 16609 | }) |
0073023d | 16610 | |
885a70fd JH |
16611 | (define_expand "allocate_stack_worker" |
16612 | [(match_operand:SI 0 "register_operand" "")] | |
16613 | "TARGET_STACK_PROBE" | |
885a70fd JH |
16614 | { |
16615 | if (TARGET_64BIT) | |
16616 | emit_insn (gen_allocate_stack_worker_rex64 (operands[0])); | |
16617 | else | |
16618 | emit_insn (gen_allocate_stack_worker_1 (operands[0])); | |
16619 | DONE; | |
0f40f9f7 | 16620 | }) |
885a70fd JH |
16621 | |
16622 | (define_insn "allocate_stack_worker_1" | |
578b58f5 RK |
16623 | [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3) |
16624 | (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0))) | |
e075ae69 RH |
16625 | (clobber (match_dup 0)) |
16626 | (clobber (reg:CC 17))] | |
1b0c37d7 | 16627 | "!TARGET_64BIT && TARGET_STACK_PROBE" |
0f40f9f7 | 16628 | "call\t__alloca" |
885a70fd JH |
16629 | [(set_attr "type" "multi") |
16630 | (set_attr "length" "5")]) | |
16631 | ||
16632 | (define_insn "allocate_stack_worker_rex64" | |
16633 | [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3) | |
16634 | (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0))) | |
16635 | (clobber (match_dup 0)) | |
16636 | (clobber (reg:CC 17))] | |
1b0c37d7 | 16637 | "TARGET_64BIT && TARGET_STACK_PROBE" |
0f40f9f7 | 16638 | "call\t__alloca" |
e075ae69 RH |
16639 | [(set_attr "type" "multi") |
16640 | (set_attr "length" "5")]) | |
578b58f5 RK |
16641 | |
16642 | (define_expand "allocate_stack" | |
e075ae69 RH |
16643 | [(parallel [(set (match_operand:SI 0 "register_operand" "=r") |
16644 | (minus:SI (reg:SI 7) | |
16645 | (match_operand:SI 1 "general_operand" ""))) | |
16646 | (clobber (reg:CC 17))]) | |
16647 | (parallel [(set (reg:SI 7) | |
16648 | (minus:SI (reg:SI 7) (match_dup 1))) | |
16649 | (clobber (reg:CC 17))])] | |
16650 | "TARGET_STACK_PROBE" | |
578b58f5 RK |
16651 | { |
16652 | #ifdef CHECK_STACK_LIMIT | |
e9a25f70 JL |
16653 | if (GET_CODE (operands[1]) == CONST_INT |
16654 | && INTVAL (operands[1]) < CHECK_STACK_LIMIT) | |
578b58f5 | 16655 | emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, |
e9a25f70 | 16656 | operands[1])); |
578b58f5 RK |
16657 | else |
16658 | #endif | |
16659 | emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode, | |
e9a25f70 | 16660 | operands[1]))); |
578b58f5 | 16661 | |
e9a25f70 JL |
16662 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
16663 | DONE; | |
0f40f9f7 | 16664 | }) |
e31ca113 | 16665 | |
fb754025 AG |
16666 | (define_expand "builtin_setjmp_receiver" |
16667 | [(label_ref (match_operand 0 "" ""))] | |
1b0c37d7 | 16668 | "!TARGET_64BIT && flag_pic" |
fb754025 AG |
16669 | { |
16670 | load_pic_register (); | |
16671 | DONE; | |
0f40f9f7 | 16672 | }) |
e9e80858 JH |
16673 | \f |
16674 | ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode. | |
16675 | ||
16676 | (define_split | |
16677 | [(set (match_operand 0 "register_operand" "") | |
16678 | (match_operator 3 "promotable_binary_operator" | |
16679 | [(match_operand 1 "register_operand" "") | |
2247f6ed | 16680 | (match_operand 2 "aligned_operand" "")])) |
e9e80858 JH |
16681 | (clobber (reg:CC 17))] |
16682 | "! TARGET_PARTIAL_REG_STALL && reload_completed | |
16683 | && ((GET_MODE (operands[0]) == HImode | |
16684 | && (!optimize_size || GET_CODE (operands[2]) != CONST_INT | |
16685 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))) | |
16686 | || (GET_MODE (operands[0]) == QImode | |
16687 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16688 | [(parallel [(set (match_dup 0) | |
16689 | (match_op_dup 3 [(match_dup 1) (match_dup 2)])) | |
16690 | (clobber (reg:CC 17))])] | |
16691 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
16692 | operands[1] = gen_lowpart (SImode, operands[1]); | |
16693 | if (GET_CODE (operands[3]) != ASHIFT) | |
16694 | operands[2] = gen_lowpart (SImode, operands[2]); | |
dbbbbf3b | 16695 | PUT_MODE (operands[3], SImode);") |
e9e80858 JH |
16696 | |
16697 | (define_split | |
16189740 RH |
16698 | [(set (reg 17) |
16699 | (compare (and (match_operand 1 "aligned_operand" "") | |
16700 | (match_operand 2 "const_int_operand" "")) | |
16701 | (const_int 0))) | |
e9e80858 JH |
16702 | (set (match_operand 0 "register_operand" "") |
16703 | (and (match_dup 1) (match_dup 2)))] | |
16704 | "! TARGET_PARTIAL_REG_STALL && reload_completed | |
16189740 | 16705 | && ix86_match_ccmode (insn, CCNOmode) |
e9e80858 JH |
16706 | && (GET_MODE (operands[0]) == HImode |
16707 | || (GET_MODE (operands[0]) == QImode | |
16708 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16709 | [(parallel [(set (reg:CCNO 17) | |
16710 | (compare:CCNO (and:SI (match_dup 1) (match_dup 2)) | |
16711 | (const_int 0))) | |
16712 | (set (match_dup 0) | |
16713 | (and:SI (match_dup 1) (match_dup 2)))])] | |
d9f0b960 | 16714 | "operands[2] |
383252a7 AO |
16715 | = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]) |
16716 | & GET_MODE_MASK (GET_MODE (operands[0])), | |
16717 | SImode)); | |
d9f0b960 RH |
16718 | operands[0] = gen_lowpart (SImode, operands[0]); |
16719 | operands[1] = gen_lowpart (SImode, operands[1]);") | |
e9e80858 JH |
16720 | |
16721 | (define_split | |
16189740 RH |
16722 | [(set (reg 17) |
16723 | (compare (and (match_operand 0 "aligned_operand" "") | |
16724 | (match_operand 1 "const_int_operand" "")) | |
16725 | (const_int 0)))] | |
e9e80858 | 16726 | "! TARGET_PARTIAL_REG_STALL && reload_completed |
16189740 | 16727 | && ix86_match_ccmode (insn, CCNOmode) |
e9e80858 JH |
16728 | && (GET_MODE (operands[0]) == HImode |
16729 | || (GET_MODE (operands[0]) == QImode | |
16730 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16731 | [(set (reg:CCNO 17) | |
16732 | (compare:CCNO (and:SI (match_dup 0) (match_dup 1)) | |
16733 | (const_int 0)))] | |
d9f0b960 | 16734 | "operands[1] |
383252a7 AO |
16735 | = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]) |
16736 | & GET_MODE_MASK (GET_MODE (operands[0])), | |
16737 | SImode)); | |
d9f0b960 | 16738 | operands[0] = gen_lowpart (SImode, operands[0]);") |
e9e80858 JH |
16739 | |
16740 | (define_split | |
16741 | [(set (match_operand 0 "register_operand" "") | |
16742 | (neg (match_operand 1 "register_operand" ""))) | |
16743 | (clobber (reg:CC 17))] | |
16744 | "! TARGET_PARTIAL_REG_STALL && reload_completed | |
16745 | && (GET_MODE (operands[0]) == HImode | |
16746 | || (GET_MODE (operands[0]) == QImode | |
16747 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16748 | [(parallel [(set (match_dup 0) | |
16749 | (neg:SI (match_dup 1))) | |
16750 | (clobber (reg:CC 17))])] | |
16751 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
16752 | operands[1] = gen_lowpart (SImode, operands[1]);") | |
16753 | ||
16754 | (define_split | |
16755 | [(set (match_operand 0 "register_operand" "") | |
16756 | (not (match_operand 1 "register_operand" "")))] | |
16757 | "! TARGET_PARTIAL_REG_STALL && reload_completed | |
16758 | && (GET_MODE (operands[0]) == HImode | |
16759 | || (GET_MODE (operands[0]) == QImode | |
16760 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16761 | [(set (match_dup 0) | |
16762 | (not:SI (match_dup 1)))] | |
16763 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
16764 | operands[1] = gen_lowpart (SImode, operands[1]);") | |
16765 | ||
16766 | (define_split | |
16767 | [(set (match_operand 0 "register_operand" "") | |
16768 | (if_then_else (match_operator 1 "comparison_operator" | |
16769 | [(reg 17) (const_int 0)]) | |
16770 | (match_operand 2 "register_operand" "") | |
16771 | (match_operand 3 "register_operand" "")))] | |
16772 | "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE | |
16773 | && (GET_MODE (operands[0]) == HImode | |
16774 | || (GET_MODE (operands[0]) == QImode | |
16775 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16776 | [(set (match_dup 0) | |
16777 | (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
16778 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
16779 | operands[2] = gen_lowpart (SImode, operands[2]); | |
16780 | operands[3] = gen_lowpart (SImode, operands[3]);") | |
16781 | ||
e075ae69 RH |
16782 | \f |
16783 | ;; RTL Peephole optimizations, run before sched2. These primarily look to | |
16784 | ;; transform a complex memory operation into two memory to register operations. | |
16785 | ||
16786 | ;; Don't push memory operands | |
16787 | (define_peephole2 | |
3071fab5 RH |
16788 | [(set (match_operand:SI 0 "push_operand" "") |
16789 | (match_operand:SI 1 "memory_operand" "")) | |
16790 | (match_scratch:SI 2 "r")] | |
e075ae69 RH |
16791 | "! optimize_size && ! TARGET_PUSH_MEMORY" |
16792 | [(set (match_dup 2) (match_dup 1)) | |
16793 | (set (match_dup 0) (match_dup 2))] | |
16794 | "") | |
16795 | ||
cc2e591b JH |
16796 | (define_peephole2 |
16797 | [(set (match_operand:DI 0 "push_operand" "") | |
16798 | (match_operand:DI 1 "memory_operand" "")) | |
16799 | (match_scratch:DI 2 "r")] | |
16800 | "! optimize_size && ! TARGET_PUSH_MEMORY" | |
16801 | [(set (match_dup 2) (match_dup 1)) | |
16802 | (set (match_dup 0) (match_dup 2))] | |
16803 | "") | |
16804 | ||
e9e80858 JH |
16805 | ;; We need to handle SFmode only, because DFmode and XFmode is split to |
16806 | ;; SImode pushes. | |
16807 | (define_peephole2 | |
16808 | [(set (match_operand:SF 0 "push_operand" "") | |
16809 | (match_operand:SF 1 "memory_operand" "")) | |
16810 | (match_scratch:SF 2 "r")] | |
16811 | "! optimize_size && ! TARGET_PUSH_MEMORY" | |
16812 | [(set (match_dup 2) (match_dup 1)) | |
16813 | (set (match_dup 0) (match_dup 2))] | |
16814 | "") | |
16815 | ||
e075ae69 | 16816 | (define_peephole2 |
3071fab5 RH |
16817 | [(set (match_operand:HI 0 "push_operand" "") |
16818 | (match_operand:HI 1 "memory_operand" "")) | |
16819 | (match_scratch:HI 2 "r")] | |
e075ae69 RH |
16820 | "! optimize_size && ! TARGET_PUSH_MEMORY" |
16821 | [(set (match_dup 2) (match_dup 1)) | |
16822 | (set (match_dup 0) (match_dup 2))] | |
16823 | "") | |
16824 | ||
16825 | (define_peephole2 | |
3071fab5 RH |
16826 | [(set (match_operand:QI 0 "push_operand" "") |
16827 | (match_operand:QI 1 "memory_operand" "")) | |
16828 | (match_scratch:QI 2 "q")] | |
e075ae69 RH |
16829 | "! optimize_size && ! TARGET_PUSH_MEMORY" |
16830 | [(set (match_dup 2) (match_dup 1)) | |
16831 | (set (match_dup 0) (match_dup 2))] | |
16832 | "") | |
16833 | ||
16834 | ;; Don't move an immediate directly to memory when the instruction | |
16835 | ;; gets too big. | |
16836 | (define_peephole2 | |
16837 | [(match_scratch:SI 1 "r") | |
16838 | (set (match_operand:SI 0 "memory_operand" "") | |
16839 | (const_int 0))] | |
23280139 | 16840 | "! optimize_size |
591702de | 16841 | && ! TARGET_USE_MOV0 |
23280139 RH |
16842 | && TARGET_SPLIT_LONG_MOVES |
16843 | && get_attr_length (insn) >= ix86_cost->large_insn | |
16844 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
e075ae69 RH |
16845 | [(parallel [(set (match_dup 1) (const_int 0)) |
16846 | (clobber (reg:CC 17))]) | |
16847 | (set (match_dup 0) (match_dup 1))] | |
16848 | "") | |
16849 | ||
16850 | (define_peephole2 | |
16851 | [(match_scratch:HI 1 "r") | |
16852 | (set (match_operand:HI 0 "memory_operand" "") | |
16853 | (const_int 0))] | |
23280139 | 16854 | "! optimize_size |
591702de | 16855 | && ! TARGET_USE_MOV0 |
23280139 RH |
16856 | && TARGET_SPLIT_LONG_MOVES |
16857 | && get_attr_length (insn) >= ix86_cost->large_insn | |
16858 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
591702de | 16859 | [(parallel [(set (match_dup 2) (const_int 0)) |
e075ae69 RH |
16860 | (clobber (reg:CC 17))]) |
16861 | (set (match_dup 0) (match_dup 1))] | |
591702de | 16862 | "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));") |
e075ae69 RH |
16863 | |
16864 | (define_peephole2 | |
16865 | [(match_scratch:QI 1 "q") | |
16866 | (set (match_operand:QI 0 "memory_operand" "") | |
16867 | (const_int 0))] | |
23280139 | 16868 | "! optimize_size |
591702de | 16869 | && ! TARGET_USE_MOV0 |
23280139 RH |
16870 | && TARGET_SPLIT_LONG_MOVES |
16871 | && get_attr_length (insn) >= ix86_cost->large_insn | |
16872 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
591702de | 16873 | [(parallel [(set (match_dup 2) (const_int 0)) |
e075ae69 RH |
16874 | (clobber (reg:CC 17))]) |
16875 | (set (match_dup 0) (match_dup 1))] | |
591702de | 16876 | "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));") |
e075ae69 RH |
16877 | |
16878 | (define_peephole2 | |
16879 | [(match_scratch:SI 2 "r") | |
16880 | (set (match_operand:SI 0 "memory_operand" "") | |
16881 | (match_operand:SI 1 "immediate_operand" ""))] | |
23280139 RH |
16882 | "! optimize_size |
16883 | && get_attr_length (insn) >= ix86_cost->large_insn | |
16884 | && TARGET_SPLIT_LONG_MOVES" | |
e075ae69 RH |
16885 | [(set (match_dup 2) (match_dup 1)) |
16886 | (set (match_dup 0) (match_dup 2))] | |
16887 | "") | |
16888 | ||
16889 | (define_peephole2 | |
16890 | [(match_scratch:HI 2 "r") | |
16891 | (set (match_operand:HI 0 "memory_operand" "") | |
16892 | (match_operand:HI 1 "immediate_operand" ""))] | |
16893 | "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn | |
16894 | && TARGET_SPLIT_LONG_MOVES" | |
16895 | [(set (match_dup 2) (match_dup 1)) | |
16896 | (set (match_dup 0) (match_dup 2))] | |
16897 | "") | |
16898 | ||
16899 | (define_peephole2 | |
16900 | [(match_scratch:QI 2 "q") | |
16901 | (set (match_operand:QI 0 "memory_operand" "") | |
16902 | (match_operand:QI 1 "immediate_operand" ""))] | |
16903 | "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn | |
16904 | && TARGET_SPLIT_LONG_MOVES" | |
16905 | [(set (match_dup 2) (match_dup 1)) | |
16906 | (set (match_dup 0) (match_dup 2))] | |
16907 | "") | |
16908 | ||
16909 | ;; Don't compare memory with zero, load and use a test instead. | |
16910 | (define_peephole2 | |
16189740 RH |
16911 | [(set (reg 17) |
16912 | (compare (match_operand:SI 0 "memory_operand" "") | |
16913 | (const_int 0))) | |
3071fab5 | 16914 | (match_scratch:SI 3 "r")] |
16189740 RH |
16915 | "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size" |
16916 | [(set (match_dup 3) (match_dup 0)) | |
16917 | (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] | |
e075ae69 RH |
16918 | "") |
16919 | ||
16920 | ;; NOT is not pairable on Pentium, while XOR is, but one byte longer. | |
16921 | ;; Don't split NOTs with a displacement operand, because resulting XOR | |
16922 | ;; will not be pariable anyway. | |
16923 | ;; | |
16924 | ;; On AMD K6, NOT is vector decoded with memory operand that can not be | |
16925 | ;; represented using a modRM byte. The XOR replacement is long decoded, | |
16926 | ;; so this split helps here as well. | |
16927 | ;; | |
23280139 RH |
16928 | ;; Note: Can't do this as a regular split because we can't get proper |
16929 | ;; lifetime information then. | |
e075ae69 RH |
16930 | |
16931 | (define_peephole2 | |
d5d6a58b RH |
16932 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
16933 | (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
e075ae69 | 16934 | "!optimize_size |
23280139 | 16935 | && peep2_regno_dead_p (0, FLAGS_REG) |
e075ae69 RH |
16936 | && ((TARGET_PENTIUM |
16937 | && (GET_CODE (operands[0]) != MEM | |
16938 | || !memory_displacement_operand (operands[0], SImode))) | |
16939 | || (TARGET_K6 && long_memory_operand (operands[0], SImode)))" | |
16940 | [(parallel [(set (match_dup 0) | |
16941 | (xor:SI (match_dup 1) (const_int -1))) | |
16942 | (clobber (reg:CC 17))])] | |
16943 | "") | |
16944 | ||
16945 | (define_peephole2 | |
d5d6a58b RH |
16946 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
16947 | (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
e075ae69 | 16948 | "!optimize_size |
23280139 | 16949 | && peep2_regno_dead_p (0, FLAGS_REG) |
e075ae69 RH |
16950 | && ((TARGET_PENTIUM |
16951 | && (GET_CODE (operands[0]) != MEM | |
16952 | || !memory_displacement_operand (operands[0], HImode))) | |
16953 | || (TARGET_K6 && long_memory_operand (operands[0], HImode)))" | |
16954 | [(parallel [(set (match_dup 0) | |
16955 | (xor:HI (match_dup 1) (const_int -1))) | |
16956 | (clobber (reg:CC 17))])] | |
16957 | "") | |
16958 | ||
16959 | (define_peephole2 | |
d5d6a58b RH |
16960 | [(set (match_operand:QI 0 "nonimmediate_operand" "") |
16961 | (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
e075ae69 | 16962 | "!optimize_size |
23280139 | 16963 | && peep2_regno_dead_p (0, FLAGS_REG) |
e075ae69 RH |
16964 | && ((TARGET_PENTIUM |
16965 | && (GET_CODE (operands[0]) != MEM | |
16966 | || !memory_displacement_operand (operands[0], QImode))) | |
16967 | || (TARGET_K6 && long_memory_operand (operands[0], QImode)))" | |
16968 | [(parallel [(set (match_dup 0) | |
16969 | (xor:QI (match_dup 1) (const_int -1))) | |
16970 | (clobber (reg:CC 17))])] | |
16971 | "") | |
16972 | ||
16973 | ;; Non pairable "test imm, reg" instructions can be translated to | |
16974 | ;; "and imm, reg" if reg dies. The "and" form is also shorter (one | |
16975 | ;; byte opcode instead of two, have a short form for byte operands), | |
16976 | ;; so do it for other CPUs as well. Given that the value was dead, | |
f5143c46 | 16977 | ;; this should not create any new dependencies. Pass on the sub-word |
e075ae69 RH |
16978 | ;; versions if we're concerned about partial register stalls. |
16979 | ||
16980 | (define_peephole2 | |
16189740 RH |
16981 | [(set (reg 17) |
16982 | (compare (and:SI (match_operand:SI 0 "register_operand" "") | |
16983 | (match_operand:SI 1 "immediate_operand" "")) | |
16984 | (const_int 0)))] | |
16985 | "ix86_match_ccmode (insn, CCNOmode) | |
16986 | && (true_regnum (operands[0]) != 0 | |
16987 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')) | |
e075ae69 RH |
16988 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" |
16989 | [(parallel | |
16990 | [(set (reg:CCNO 17) | |
16991 | (compare:CCNO (and:SI (match_dup 0) | |
16992 | (match_dup 1)) | |
16993 | (const_int 0))) | |
16994 | (set (match_dup 0) | |
16995 | (and:SI (match_dup 0) (match_dup 1)))])] | |
16996 | "") | |
16997 | ||
e9e80858 JH |
16998 | ;; We don't need to handle HImode case, because it will be promoted to SImode |
16999 | ;; on ! TARGET_PARTIAL_REG_STALL | |
e075ae69 RH |
17000 | |
17001 | (define_peephole2 | |
16189740 RH |
17002 | [(set (reg 17) |
17003 | (compare (and:QI (match_operand:QI 0 "register_operand" "") | |
17004 | (match_operand:QI 1 "immediate_operand" "")) | |
17005 | (const_int 0)))] | |
e075ae69 | 17006 | "! TARGET_PARTIAL_REG_STALL |
16189740 | 17007 | && ix86_match_ccmode (insn, CCNOmode) |
e075ae69 RH |
17008 | && true_regnum (operands[0]) != 0 |
17009 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17010 | [(parallel | |
17011 | [(set (reg:CCNO 17) | |
17012 | (compare:CCNO (and:QI (match_dup 0) | |
17013 | (match_dup 1)) | |
17014 | (const_int 0))) | |
17015 | (set (match_dup 0) | |
17016 | (and:QI (match_dup 0) (match_dup 1)))])] | |
17017 | "") | |
17018 | ||
17019 | (define_peephole2 | |
16189740 RH |
17020 | [(set (reg 17) |
17021 | (compare | |
e075ae69 RH |
17022 | (and:SI |
17023 | (zero_extract:SI | |
3522082b | 17024 | (match_operand 0 "ext_register_operand" "") |
e075ae69 RH |
17025 | (const_int 8) |
17026 | (const_int 8)) | |
3522082b | 17027 | (match_operand 1 "const_int_operand" "")) |
e075ae69 RH |
17028 | (const_int 0)))] |
17029 | "! TARGET_PARTIAL_REG_STALL | |
16189740 | 17030 | && ix86_match_ccmode (insn, CCNOmode) |
e075ae69 RH |
17031 | && true_regnum (operands[0]) != 0 |
17032 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17033 | [(parallel [(set (reg:CCNO 17) | |
17034 | (compare:CCNO | |
17035 | (and:SI | |
17036 | (zero_extract:SI | |
17037 | (match_dup 0) | |
17038 | (const_int 8) | |
17039 | (const_int 8)) | |
17040 | (match_dup 1)) | |
17041 | (const_int 0))) | |
17042 | (set (zero_extract:SI (match_dup 0) | |
17043 | (const_int 8) | |
17044 | (const_int 8)) | |
17045 | (and:SI | |
17046 | (zero_extract:SI | |
17047 | (match_dup 0) | |
17048 | (const_int 8) | |
17049 | (const_int 8)) | |
17050 | (match_dup 1)))])] | |
17051 | "") | |
17052 | ||
17053 | ;; Don't do logical operations with memory inputs. | |
17054 | (define_peephole2 | |
17055 | [(match_scratch:SI 2 "r") | |
17056 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
17057 | (match_operator:SI 3 "arith_or_logical_operator" | |
17058 | [(match_dup 0) | |
17059 | (match_operand:SI 1 "memory_operand" "")])) | |
17060 | (clobber (reg:CC 17))])] | |
17061 | "! optimize_size && ! TARGET_READ_MODIFY" | |
17062 | [(set (match_dup 2) (match_dup 1)) | |
17063 | (parallel [(set (match_dup 0) | |
17064 | (match_op_dup 3 [(match_dup 0) (match_dup 2)])) | |
17065 | (clobber (reg:CC 17))])] | |
17066 | "") | |
17067 | ||
17068 | (define_peephole2 | |
17069 | [(match_scratch:SI 2 "r") | |
17070 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
17071 | (match_operator:SI 3 "arith_or_logical_operator" | |
17072 | [(match_operand:SI 1 "memory_operand" "") | |
17073 | (match_dup 0)])) | |
17074 | (clobber (reg:CC 17))])] | |
17075 | "! optimize_size && ! TARGET_READ_MODIFY" | |
17076 | [(set (match_dup 2) (match_dup 1)) | |
17077 | (parallel [(set (match_dup 0) | |
17078 | (match_op_dup 3 [(match_dup 2) (match_dup 0)])) | |
17079 | (clobber (reg:CC 17))])] | |
17080 | "") | |
17081 | ||
17082 | ; Don't do logical operations with memory outputs | |
17083 | ; | |
17084 | ; These two don't make sense for PPro/PII -- we're expanding a 4-uop | |
17085 | ; instruction into two 1-uop insns plus a 2-uop insn. That last has | |
17086 | ; the same decoder scheduling characteristics as the original. | |
17087 | ||
17088 | (define_peephole2 | |
17089 | [(match_scratch:SI 2 "r") | |
17090 | (parallel [(set (match_operand:SI 0 "memory_operand" "") | |
17091 | (match_operator:SI 3 "arith_or_logical_operator" | |
17092 | [(match_dup 0) | |
17093 | (match_operand:SI 1 "nonmemory_operand" "")])) | |
17094 | (clobber (reg:CC 17))])] | |
17095 | "! optimize_size && ! TARGET_READ_MODIFY_WRITE" | |
17096 | [(set (match_dup 2) (match_dup 0)) | |
17097 | (parallel [(set (match_dup 2) | |
17098 | (match_op_dup 3 [(match_dup 2) (match_dup 1)])) | |
17099 | (clobber (reg:CC 17))]) | |
17100 | (set (match_dup 0) (match_dup 2))] | |
17101 | "") | |
17102 | ||
17103 | (define_peephole2 | |
17104 | [(match_scratch:SI 2 "r") | |
17105 | (parallel [(set (match_operand:SI 0 "memory_operand" "") | |
17106 | (match_operator:SI 3 "arith_or_logical_operator" | |
17107 | [(match_operand:SI 1 "nonmemory_operand" "") | |
17108 | (match_dup 0)])) | |
17109 | (clobber (reg:CC 17))])] | |
17110 | "! optimize_size && ! TARGET_READ_MODIFY_WRITE" | |
17111 | [(set (match_dup 2) (match_dup 0)) | |
17112 | (parallel [(set (match_dup 2) | |
17113 | (match_op_dup 3 [(match_dup 1) (match_dup 2)])) | |
17114 | (clobber (reg:CC 17))]) | |
17115 | (set (match_dup 0) (match_dup 2))] | |
17116 | "") | |
17117 | ||
17118 | ;; Attempt to always use XOR for zeroing registers. | |
17119 | (define_peephole2 | |
17120 | [(set (match_operand 0 "register_operand" "") | |
17121 | (const_int 0))] | |
17122 | "(GET_MODE (operands[0]) == QImode | |
17123 | || GET_MODE (operands[0]) == HImode | |
cc2e591b JH |
17124 | || GET_MODE (operands[0]) == SImode |
17125 | || (GET_MODE (operands[0]) == DImode && TARGET_64BIT)) | |
e075ae69 | 17126 | && (! TARGET_USE_MOV0 || optimize_size) |
23280139 | 17127 | && peep2_regno_dead_p (0, FLAGS_REG)" |
e075ae69 RH |
17128 | [(parallel [(set (match_dup 0) (const_int 0)) |
17129 | (clobber (reg:CC 17))])] | |
cc2e591b JH |
17130 | "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode, |
17131 | true_regnum (operands[0]));") | |
d3a923ee | 17132 | |
6ef67412 JH |
17133 | (define_peephole2 |
17134 | [(set (strict_low_part (match_operand 0 "register_operand" "")) | |
17135 | (const_int 0))] | |
17136 | "(GET_MODE (operands[0]) == QImode | |
17137 | || GET_MODE (operands[0]) == HImode) | |
17138 | && (! TARGET_USE_MOV0 || optimize_size) | |
17139 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
17140 | [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0)) | |
17141 | (clobber (reg:CC 17))])]) | |
17142 | ||
e075ae69 RH |
17143 | ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg. |
17144 | (define_peephole2 | |
591702de | 17145 | [(set (match_operand 0 "register_operand" "") |
e075ae69 | 17146 | (const_int -1))] |
591702de | 17147 | "(GET_MODE (operands[0]) == HImode |
cc2e591b JH |
17148 | || GET_MODE (operands[0]) == SImode |
17149 | || (GET_MODE (operands[0]) == DImode && TARGET_64BIT)) | |
591702de | 17150 | && (optimize_size || TARGET_PENTIUM) |
23280139 | 17151 | && peep2_regno_dead_p (0, FLAGS_REG)" |
591702de | 17152 | [(parallel [(set (match_dup 0) (const_int -1)) |
e075ae69 | 17153 | (clobber (reg:CC 17))])] |
cc2e591b JH |
17154 | "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode, |
17155 | true_regnum (operands[0]));") | |
1c27d4b2 JH |
17156 | |
17157 | ;; Attempt to convert simple leas to adds. These can be created by | |
17158 | ;; move expanders. | |
17159 | (define_peephole2 | |
17160 | [(set (match_operand:SI 0 "register_operand" "") | |
17161 | (plus:SI (match_dup 0) | |
17162 | (match_operand:SI 1 "nonmemory_operand" "")))] | |
23280139 | 17163 | "peep2_regno_dead_p (0, FLAGS_REG)" |
1c27d4b2 JH |
17164 | [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) |
17165 | (clobber (reg:CC 17))])] | |
17166 | "") | |
17167 | ||
cc2e591b JH |
17168 | (define_peephole2 |
17169 | [(set (match_operand:SI 0 "register_operand" "") | |
17170 | (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "") | |
17171 | (match_operand:DI 2 "nonmemory_operand" "")) 0))] | |
17172 | "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])" | |
17173 | [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
17174 | (clobber (reg:CC 17))])] | |
17175 | "operands[2] = gen_lowpart (SImode, operands[2]);") | |
17176 | ||
17177 | (define_peephole2 | |
17178 | [(set (match_operand:DI 0 "register_operand" "") | |
17179 | (plus:DI (match_dup 0) | |
17180 | (match_operand:DI 1 "x86_64_general_operand" "")))] | |
17181 | "peep2_regno_dead_p (0, FLAGS_REG)" | |
17182 | [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) | |
17183 | (clobber (reg:CC 17))])] | |
17184 | "") | |
17185 | ||
1c27d4b2 JH |
17186 | (define_peephole2 |
17187 | [(set (match_operand:SI 0 "register_operand" "") | |
17188 | (mult:SI (match_dup 0) | |
cc2e591b | 17189 | (match_operand:SI 1 "const_int_operand" "")))] |
23280139 RH |
17190 | "exact_log2 (INTVAL (operands[1])) >= 0 |
17191 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
1c27d4b2 JH |
17192 | [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2))) |
17193 | (clobber (reg:CC 17))])] | |
17194 | "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") | |
bdeb029c | 17195 | |
cc2e591b JH |
17196 | (define_peephole2 |
17197 | [(set (match_operand:DI 0 "register_operand" "") | |
17198 | (mult:DI (match_dup 0) | |
17199 | (match_operand:DI 1 "const_int_operand" "")))] | |
17200 | "exact_log2 (INTVAL (operands[1])) >= 0 | |
17201 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
17202 | [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2))) | |
17203 | (clobber (reg:CC 17))])] | |
17204 | "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") | |
17205 | ||
17206 | (define_peephole2 | |
17207 | [(set (match_operand:SI 0 "register_operand" "") | |
17208 | (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "") | |
17209 | (match_operand:DI 2 "const_int_operand" "")) 0))] | |
17210 | "exact_log2 (INTVAL (operands[1])) >= 0 | |
17211 | && REGNO (operands[0]) == REGNO (operands[1]) | |
17212 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
17213 | [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2))) | |
17214 | (clobber (reg:CC 17))])] | |
17215 | "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));") | |
17216 | ||
bdeb029c JH |
17217 | ;; The ESP adjustments can be done by the push and pop instructions. Resulting |
17218 | ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On | |
17219 | ;; many CPUs it is also faster, since special hardware to avoid esp | |
f5143c46 | 17220 | ;; dependencies is present. |
bdeb029c | 17221 | |
d6a7951f | 17222 | ;; While some of these conversions may be done using splitters, we use peepholes |
bdeb029c JH |
17223 | ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL. |
17224 | ||
f5143c46 | 17225 | ;; Convert prologue esp subtractions to push. |
bdeb029c JH |
17226 | ;; We need register to push. In order to keep verify_flow_info happy we have |
17227 | ;; two choices | |
17228 | ;; - use scratch and clobber it in order to avoid dependencies | |
17229 | ;; - use already live register | |
17230 | ;; We can't use the second way right now, since there is no reliable way how to | |
17231 | ;; verify that given register is live. First choice will also most likely in | |
17232 | ;; fewer dependencies. On the place of esp adjustments it is very likely that | |
17233 | ;; call clobbered registers are dead. We may want to use base pointer as an | |
17234 | ;; alternative when no register is available later. | |
17235 | ||
17236 | (define_peephole2 | |
17237 | [(match_scratch:SI 0 "r") | |
17238 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) | |
f2042df3 RH |
17239 | (clobber (reg:CC 17)) |
17240 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17241 | "optimize_size || !TARGET_SUB_ESP_4" |
17242 | [(clobber (match_dup 0)) | |
17243 | (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) | |
f2042df3 | 17244 | (clobber (mem:BLK (scratch)))])]) |
bdeb029c JH |
17245 | |
17246 | (define_peephole2 | |
17247 | [(match_scratch:SI 0 "r") | |
17248 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
f2042df3 RH |
17249 | (clobber (reg:CC 17)) |
17250 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17251 | "optimize_size || !TARGET_SUB_ESP_8" |
17252 | [(clobber (match_dup 0)) | |
17253 | (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) | |
17254 | (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) | |
f2042df3 | 17255 | (clobber (mem:BLK (scratch)))])]) |
bdeb029c | 17256 | |
f5143c46 | 17257 | ;; Convert esp subtractions to push. |
bdeb029c JH |
17258 | (define_peephole2 |
17259 | [(match_scratch:SI 0 "r") | |
17260 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) | |
17261 | (clobber (reg:CC 17))])] | |
17262 | "optimize_size || !TARGET_SUB_ESP_4" | |
17263 | [(clobber (match_dup 0)) | |
17264 | (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]) | |
17265 | ||
17266 | (define_peephole2 | |
17267 | [(match_scratch:SI 0 "r") | |
17268 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
17269 | (clobber (reg:CC 17))])] | |
17270 | "optimize_size || !TARGET_SUB_ESP_8" | |
17271 | [(clobber (match_dup 0)) | |
17272 | (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) | |
17273 | (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]) | |
17274 | ||
17275 | ;; Convert epilogue deallocator to pop. | |
17276 | (define_peephole2 | |
17277 | [(match_scratch:SI 0 "r") | |
17278 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 RH |
17279 | (clobber (reg:CC 17)) |
17280 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17281 | "optimize_size || !TARGET_ADD_ESP_4" |
17282 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17283 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 | 17284 | (clobber (mem:BLK (scratch)))])] |
bdeb029c JH |
17285 | "") |
17286 | ||
17287 | ;; Two pops case is tricky, since pop causes dependency on destination register. | |
17288 | ;; We use two registers if available. | |
17289 | (define_peephole2 | |
17290 | [(match_scratch:SI 0 "r") | |
17291 | (match_scratch:SI 1 "r") | |
17292 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) | |
f2042df3 RH |
17293 | (clobber (reg:CC 17)) |
17294 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17295 | "optimize_size || !TARGET_ADD_ESP_8" |
17296 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17297 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 | 17298 | (clobber (mem:BLK (scratch)))]) |
bdeb029c JH |
17299 | (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) |
17300 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17301 | "") | |
17302 | ||
17303 | (define_peephole2 | |
17304 | [(match_scratch:SI 0 "r") | |
17305 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) | |
f2042df3 RH |
17306 | (clobber (reg:CC 17)) |
17307 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17308 | "optimize_size" |
17309 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17310 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 | 17311 | (clobber (mem:BLK (scratch)))]) |
bdeb029c JH |
17312 | (parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) |
17313 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17314 | "") | |
17315 | ||
17316 | ;; Convert esp additions to pop. | |
17317 | (define_peephole2 | |
17318 | [(match_scratch:SI 0 "r") | |
17319 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
17320 | (clobber (reg:CC 17))])] | |
17321 | "" | |
17322 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17323 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17324 | "") | |
17325 | ||
17326 | ;; Two pops case is tricky, since pop causes dependency on destination register. | |
17327 | ;; We use two registers if available. | |
17328 | (define_peephole2 | |
17329 | [(match_scratch:SI 0 "r") | |
17330 | (match_scratch:SI 1 "r") | |
17331 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) | |
17332 | (clobber (reg:CC 17))])] | |
17333 | "" | |
17334 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17335 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]) | |
17336 | (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) | |
17337 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17338 | "") | |
17339 | ||
17340 | (define_peephole2 | |
17341 | [(match_scratch:SI 0 "r") | |
17342 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) | |
17343 | (clobber (reg:CC 17))])] | |
17344 | "optimize_size" | |
17345 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17346 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]) | |
17347 | (parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17348 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17349 | "") | |
69404d6f | 17350 | \f |
9dcbdc7e JH |
17351 | ;; Convert compares with 1 to shorter inc/dec operations when CF is not |
17352 | ;; required and register dies. | |
17353 | (define_peephole2 | |
17354 | [(set (reg 17) | |
17355 | (compare (match_operand:SI 0 "register_operand" "") | |
17356 | (match_operand:SI 1 "incdec_operand" "")))] | |
17357 | "ix86_match_ccmode (insn, CCGCmode) | |
17358 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17359 | [(parallel [(set (reg:CCGC 17) | |
265dab10 | 17360 | (compare:CCGC (match_dup 0) |
7e08e190 | 17361 | (match_dup 1))) |
9dcbdc7e | 17362 | (clobber (match_dup 0))])] |
7e08e190 | 17363 | "") |
9dcbdc7e JH |
17364 | |
17365 | (define_peephole2 | |
17366 | [(set (reg 17) | |
17367 | (compare (match_operand:HI 0 "register_operand" "") | |
17368 | (match_operand:HI 1 "incdec_operand" "")))] | |
17369 | "ix86_match_ccmode (insn, CCGCmode) | |
17370 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17371 | [(parallel [(set (reg:CCGC 17) | |
265dab10 | 17372 | (compare:CCGC (match_dup 0) |
7e08e190 | 17373 | (match_dup 1))) |
9dcbdc7e | 17374 | (clobber (match_dup 0))])] |
7e08e190 | 17375 | "") |
9dcbdc7e JH |
17376 | |
17377 | (define_peephole2 | |
17378 | [(set (reg 17) | |
17379 | (compare (match_operand:QI 0 "register_operand" "") | |
17380 | (match_operand:QI 1 "incdec_operand" "")))] | |
17381 | "ix86_match_ccmode (insn, CCGCmode) | |
17382 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17383 | [(parallel [(set (reg:CCGC 17) | |
265dab10 | 17384 | (compare:CCGC (match_dup 0) |
7e08e190 | 17385 | (match_dup 1))) |
9dcbdc7e | 17386 | (clobber (match_dup 0))])] |
7e08e190 | 17387 | "") |
9dcbdc7e JH |
17388 | |
17389 | ;; Convert compares with 128 to shorter add -128 | |
17390 | (define_peephole2 | |
17391 | [(set (reg 17) | |
17392 | (compare (match_operand:SI 0 "register_operand" "") | |
17393 | (const_int 128)))] | |
7e08e190 | 17394 | "ix86_match_ccmode (insn, CCGCmode) |
9dcbdc7e | 17395 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" |
7e08e190 JH |
17396 | [(parallel [(set (reg:CCGC 17) |
17397 | (compare:CCGC (match_dup 0) | |
17398 | (const_int 128))) | |
9dcbdc7e JH |
17399 | (clobber (match_dup 0))])] |
17400 | "") | |
17401 | ||
17402 | (define_peephole2 | |
17403 | [(set (reg 17) | |
17404 | (compare (match_operand:HI 0 "register_operand" "") | |
17405 | (const_int 128)))] | |
7e08e190 | 17406 | "ix86_match_ccmode (insn, CCGCmode) |
9dcbdc7e | 17407 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" |
7e08e190 JH |
17408 | [(parallel [(set (reg:CCGC 17) |
17409 | (compare:CCGC (match_dup 0) | |
17410 | (const_int 128))) | |
9dcbdc7e JH |
17411 | (clobber (match_dup 0))])] |
17412 | "") | |
17413 | \f | |
cc2e591b JH |
17414 | (define_peephole2 |
17415 | [(match_scratch:DI 0 "r") | |
17416 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) | |
f2042df3 RH |
17417 | (clobber (reg:CC 17)) |
17418 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17419 | "optimize_size || !TARGET_SUB_ESP_4" |
17420 | [(clobber (match_dup 0)) | |
17421 | (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) | |
f2042df3 | 17422 | (clobber (mem:BLK (scratch)))])]) |
cc2e591b JH |
17423 | |
17424 | (define_peephole2 | |
17425 | [(match_scratch:DI 0 "r") | |
17426 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) | |
f2042df3 RH |
17427 | (clobber (reg:CC 17)) |
17428 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17429 | "optimize_size || !TARGET_SUB_ESP_8" |
17430 | [(clobber (match_dup 0)) | |
17431 | (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) | |
17432 | (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) | |
f2042df3 | 17433 | (clobber (mem:BLK (scratch)))])]) |
cc2e591b | 17434 | |
f5143c46 | 17435 | ;; Convert esp subtractions to push. |
cc2e591b JH |
17436 | (define_peephole2 |
17437 | [(match_scratch:DI 0 "r") | |
17438 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) | |
17439 | (clobber (reg:CC 17))])] | |
17440 | "optimize_size || !TARGET_SUB_ESP_4" | |
17441 | [(clobber (match_dup 0)) | |
17442 | (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))]) | |
17443 | ||
17444 | (define_peephole2 | |
17445 | [(match_scratch:DI 0 "r") | |
17446 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) | |
17447 | (clobber (reg:CC 17))])] | |
17448 | "optimize_size || !TARGET_SUB_ESP_8" | |
17449 | [(clobber (match_dup 0)) | |
17450 | (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) | |
17451 | (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))]) | |
17452 | ||
17453 | ;; Convert epilogue deallocator to pop. | |
17454 | (define_peephole2 | |
17455 | [(match_scratch:DI 0 "r") | |
17456 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 RH |
17457 | (clobber (reg:CC 17)) |
17458 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17459 | "optimize_size || !TARGET_ADD_ESP_4" |
17460 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17461 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 | 17462 | (clobber (mem:BLK (scratch)))])] |
cc2e591b JH |
17463 | "") |
17464 | ||
17465 | ;; Two pops case is tricky, since pop causes dependency on destination register. | |
17466 | ;; We use two registers if available. | |
17467 | (define_peephole2 | |
17468 | [(match_scratch:DI 0 "r") | |
17469 | (match_scratch:DI 1 "r") | |
17470 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) | |
f2042df3 RH |
17471 | (clobber (reg:CC 17)) |
17472 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17473 | "optimize_size || !TARGET_ADD_ESP_8" |
17474 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17475 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 | 17476 | (clobber (mem:BLK (scratch)))]) |
cc2e591b JH |
17477 | (parallel [(set (match_dup 1) (mem:DI (reg:DI 7))) |
17478 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17479 | "") | |
17480 | ||
17481 | (define_peephole2 | |
17482 | [(match_scratch:DI 0 "r") | |
17483 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) | |
f2042df3 RH |
17484 | (clobber (reg:CC 17)) |
17485 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17486 | "optimize_size" |
17487 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17488 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 | 17489 | (clobber (mem:BLK (scratch)))]) |
cc2e591b JH |
17490 | (parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) |
17491 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17492 | "") | |
17493 | ||
17494 | ;; Convert esp additions to pop. | |
17495 | (define_peephole2 | |
17496 | [(match_scratch:DI 0 "r") | |
17497 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
17498 | (clobber (reg:CC 17))])] | |
17499 | "" | |
17500 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17501 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17502 | "") | |
17503 | ||
17504 | ;; Two pops case is tricky, since pop causes dependency on destination register. | |
17505 | ;; We use two registers if available. | |
17506 | (define_peephole2 | |
17507 | [(match_scratch:DI 0 "r") | |
17508 | (match_scratch:DI 1 "r") | |
17509 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) | |
17510 | (clobber (reg:CC 17))])] | |
17511 | "" | |
17512 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17513 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))]) | |
17514 | (parallel [(set (match_dup 1) (mem:DI (reg:DI 7))) | |
17515 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17516 | "") | |
17517 | ||
17518 | (define_peephole2 | |
17519 | [(match_scratch:DI 0 "r") | |
17520 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) | |
17521 | (clobber (reg:CC 17))])] | |
17522 | "optimize_size" | |
17523 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17524 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))]) | |
17525 | (parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17526 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17527 | "") | |
17528 | \f | |
69404d6f RH |
17529 | ;; Call-value patterns last so that the wildcard operand does not |
17530 | ;; disrupt insn-recog's switch tables. | |
17531 | ||
94bb5d0c RH |
17532 | (define_insn "*call_value_pop_0" |
17533 | [(set (match_operand 0 "" "") | |
e1ff012c | 17534 | (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" "")) |
94bb5d0c RH |
17535 | (match_operand:SI 2 "" ""))) |
17536 | (set (reg:SI 7) (plus:SI (reg:SI 7) | |
90d10fb9 | 17537 | (match_operand:SI 3 "immediate_operand" "")))] |
1e07edd3 | 17538 | "!TARGET_64BIT" |
94bb5d0c RH |
17539 | { |
17540 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17541 | return "jmp\t%P1"; |
94bb5d0c | 17542 | else |
0f40f9f7 ZW |
17543 | return "call\t%P1"; |
17544 | } | |
94bb5d0c RH |
17545 | [(set_attr "type" "callv")]) |
17546 | ||
69404d6f RH |
17547 | (define_insn "*call_value_pop_1" |
17548 | [(set (match_operand 0 "" "") | |
e1ff012c | 17549 | (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm")) |
94bb5d0c | 17550 | (match_operand:SI 2 "" ""))) |
69404d6f | 17551 | (set (reg:SI 7) (plus:SI (reg:SI 7) |
90d10fb9 | 17552 | (match_operand:SI 3 "immediate_operand" "i")))] |
1e07edd3 | 17553 | "!TARGET_64BIT" |
69404d6f | 17554 | { |
94bb5d0c RH |
17555 | if (constant_call_address_operand (operands[1], QImode)) |
17556 | { | |
17557 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17558 | return "jmp\t%P1"; |
94bb5d0c | 17559 | else |
0f40f9f7 | 17560 | return "call\t%P1"; |
94bb5d0c | 17561 | } |
94bb5d0c | 17562 | if (SIBLING_CALL_P (insn)) |
0f40f9f7 | 17563 | return "jmp\t%A1"; |
94bb5d0c | 17564 | else |
0f40f9f7 ZW |
17565 | return "call\t%A1"; |
17566 | } | |
94bb5d0c RH |
17567 | [(set_attr "type" "callv")]) |
17568 | ||
17569 | (define_insn "*call_value_0" | |
17570 | [(set (match_operand 0 "" "") | |
e1ff012c | 17571 | (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" "")) |
94bb5d0c | 17572 | (match_operand:SI 2 "" "")))] |
32ee7d1d | 17573 | "!TARGET_64BIT" |
32ee7d1d JH |
17574 | { |
17575 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17576 | return "jmp\t%P1"; |
32ee7d1d | 17577 | else |
0f40f9f7 ZW |
17578 | return "call\t%P1"; |
17579 | } | |
32ee7d1d JH |
17580 | [(set_attr "type" "callv")]) |
17581 | ||
17582 | (define_insn "*call_value_0_rex64" | |
17583 | [(set (match_operand 0 "" "") | |
17584 | (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" "")) | |
17585 | (match_operand:DI 2 "const_int_operand" "")))] | |
17586 | "TARGET_64BIT" | |
94bb5d0c RH |
17587 | { |
17588 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17589 | return "jmp\t%P1"; |
94bb5d0c | 17590 | else |
0f40f9f7 ZW |
17591 | return "call\t%P1"; |
17592 | } | |
69404d6f RH |
17593 | [(set_attr "type" "callv")]) |
17594 | ||
69404d6f RH |
17595 | (define_insn "*call_value_1" |
17596 | [(set (match_operand 0 "" "") | |
e1ff012c | 17597 | (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm")) |
94bb5d0c | 17598 | (match_operand:SI 2 "" "")))] |
32ee7d1d | 17599 | "!TARGET_64BIT" |
32ee7d1d JH |
17600 | { |
17601 | if (constant_call_address_operand (operands[1], QImode)) | |
17602 | { | |
17603 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17604 | return "jmp\t%P1"; |
32ee7d1d | 17605 | else |
0f40f9f7 | 17606 | return "call\t%P1"; |
32ee7d1d JH |
17607 | } |
17608 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17609 | return "jmp\t%*%1"; |
32ee7d1d | 17610 | else |
0f40f9f7 ZW |
17611 | return "call\t%*%1"; |
17612 | } | |
32ee7d1d JH |
17613 | [(set_attr "type" "callv")]) |
17614 | ||
17615 | (define_insn "*call_value_1_rex64" | |
17616 | [(set (match_operand 0 "" "") | |
17617 | (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm")) | |
17618 | (match_operand:DI 2 "" "")))] | |
17619 | "TARGET_64BIT" | |
69404d6f | 17620 | { |
94bb5d0c | 17621 | if (constant_call_address_operand (operands[1], QImode)) |
cbbf65e0 RH |
17622 | { |
17623 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17624 | return "jmp\t%P1"; |
cbbf65e0 | 17625 | else |
0f40f9f7 | 17626 | return "call\t%P1"; |
cbbf65e0 | 17627 | } |
cbbf65e0 | 17628 | if (SIBLING_CALL_P (insn)) |
0f40f9f7 | 17629 | return "jmp\t%A1"; |
cbbf65e0 | 17630 | else |
0f40f9f7 ZW |
17631 | return "call\t%A1"; |
17632 | } | |
69404d6f | 17633 | [(set_attr "type" "callv")]) |
9e3e266c GM |
17634 | \f |
17635 | (define_insn "trap" | |
17636 | [(trap_if (const_int 1) (const_int 5))] | |
17637 | "" | |
0f40f9f7 | 17638 | "int\t$5") |
9e3e266c GM |
17639 | |
17640 | ;;; ix86 doesn't have conditional trap instructions, but we fake them | |
17641 | ;;; for the sake of bounds checking. By emitting bounds checks as | |
17642 | ;;; conditional traps rather than as conditional jumps around | |
17643 | ;;; unconditional traps we avoid introducing spurious basic-block | |
17644 | ;;; boundaries and facilitate elimination of redundant checks. In | |
17645 | ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use | |
17646 | ;;; interrupt 5. | |
17647 | ;;; | |
17648 | ;;; FIXME: Static branch prediction rules for ix86 are such that | |
17649 | ;;; forward conditional branches predict as untaken. As implemented | |
17650 | ;;; below, pseudo conditional traps violate that rule. We should use | |
17651 | ;;; .pushsection/.popsection to place all of the `int 5's in a special | |
17652 | ;;; section loaded at the end of the text segment and branch forward | |
17653 | ;;; there on bounds-failure, and then jump back immediately (in case | |
17654 | ;;; the system chooses to ignore bounds violations, or to report | |
17655 | ;;; violations and continue execution). | |
17656 | ||
17657 | (define_expand "conditional_trap" | |
17658 | [(trap_if (match_operator 0 "comparison_operator" | |
17659 | [(match_dup 2) (const_int 0)]) | |
17660 | (match_operand 1 "const_int_operand" ""))] | |
17661 | "" | |
9e3e266c GM |
17662 | { |
17663 | emit_insn (gen_rtx_TRAP_IF (VOIDmode, | |
a1b8572c | 17664 | ix86_expand_compare (GET_CODE (operands[0]), |
df4ae160 | 17665 | NULL, NULL), |
9e3e266c GM |
17666 | operands[1])); |
17667 | DONE; | |
0f40f9f7 | 17668 | }) |
9e3e266c | 17669 | |
0f40f9f7 | 17670 | (define_insn "*conditional_trap_1" |
9e3e266c GM |
17671 | [(trap_if (match_operator 0 "comparison_operator" |
17672 | [(reg 17) (const_int 0)]) | |
17673 | (match_operand 1 "const_int_operand" ""))] | |
17674 | "" | |
9e3e266c GM |
17675 | { |
17676 | operands[2] = gen_label_rtx (); | |
0f40f9f7 ZW |
17677 | output_asm_insn ("j%c0\t%l2\; int\t%1", operands); |
17678 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", | |
9e3e266c GM |
17679 | CODE_LABEL_NUMBER (operands[2])); |
17680 | RET; | |
0f40f9f7 | 17681 | }) |
915119a5 BS |
17682 | |
17683 | ;; Pentium III SIMD instructions. | |
17684 | ||
17685 | ;; Moves for SSE/MMX regs. | |
17686 | ||
17687 | (define_insn "movv4sf_internal" | |
17688 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
17689 | (match_operand:V4SF 1 "general_operand" "xm,x"))] | |
17690 | "TARGET_SSE" | |
17691 | ;; @@@ let's try to use movaps here. | |
0f40f9f7 | 17692 | "movaps\t{%1, %0|%0, %1}" |
915119a5 BS |
17693 | [(set_attr "type" "sse")]) |
17694 | ||
17695 | (define_insn "movv4si_internal" | |
17696 | [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m") | |
17697 | (match_operand:V4SI 1 "general_operand" "xm,x"))] | |
17698 | "TARGET_SSE" | |
17699 | ;; @@@ let's try to use movaps here. | |
0f40f9f7 | 17700 | "movaps\t{%1, %0|%0, %1}" |
915119a5 BS |
17701 | [(set_attr "type" "sse")]) |
17702 | ||
17703 | (define_insn "movv8qi_internal" | |
17704 | [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m") | |
17705 | (match_operand:V8QI 1 "general_operand" "ym,y"))] | |
17706 | "TARGET_MMX" | |
0f40f9f7 | 17707 | "movq\t{%1, %0|%0, %1}" |
915119a5 BS |
17708 | [(set_attr "type" "mmx")]) |
17709 | ||
17710 | (define_insn "movv4hi_internal" | |
17711 | [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m") | |
17712 | (match_operand:V4HI 1 "general_operand" "ym,y"))] | |
17713 | "TARGET_MMX" | |
0f40f9f7 | 17714 | "movq\t{%1, %0|%0, %1}" |
915119a5 BS |
17715 | [(set_attr "type" "mmx")]) |
17716 | ||
17717 | (define_insn "movv2si_internal" | |
17718 | [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m") | |
17719 | (match_operand:V2SI 1 "general_operand" "ym,y"))] | |
17720 | "TARGET_MMX" | |
0f40f9f7 | 17721 | "movq\t{%1, %0|%0, %1}" |
915119a5 BS |
17722 | [(set_attr "type" "mmx")]) |
17723 | ||
47f339cf BS |
17724 | (define_insn "movv2sf_internal" |
17725 | [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m") | |
17726 | (match_operand:V2SF 1 "general_operand" "ym,y"))] | |
17727 | "TARGET_3DNOW" | |
17728 | "movq\\t{%1, %0|%0, %1}" | |
17729 | [(set_attr "type" "mmx")]) | |
17730 | ||
915119a5 BS |
17731 | (define_expand "movti" |
17732 | [(set (match_operand:TI 0 "general_operand" "") | |
17733 | (match_operand:TI 1 "general_operand" ""))] | |
44cf5b6a | 17734 | "TARGET_SSE || TARGET_64BIT" |
915119a5 | 17735 | { |
44cf5b6a JH |
17736 | if (TARGET_64BIT) |
17737 | { | |
17738 | ix86_expand_move (TImode, operands); | |
17739 | DONE; | |
17740 | } | |
915119a5 BS |
17741 | /* For constants other than zero into memory. We do not know how the |
17742 | instructions used to build constants modify the upper 64 bits | |
17743 | of the register, once we have that information we may be able | |
17744 | to handle some of them more efficiently. */ | |
17745 | if ((reload_in_progress | reload_completed) == 0 | |
17746 | && register_operand (operands[0], TImode) | |
17747 | && CONSTANT_P (operands[1])) | |
17748 | { | |
17749 | rtx addr = gen_reg_rtx (Pmode); | |
17750 | ||
17751 | emit_move_insn (addr, XEXP (force_const_mem (TImode, operands[1]), 0)); | |
17752 | operands[1] = gen_rtx_MEM (TImode, addr); | |
17753 | } | |
17754 | ||
17755 | /* Make operand1 a register if it isn't already. */ | |
17756 | if ((reload_in_progress | reload_completed) == 0 | |
17757 | && !register_operand (operands[0], TImode) | |
17758 | && !register_operand (operands[1], TImode) | |
17759 | && operands[1] != CONST0_RTX (TImode)) | |
17760 | { | |
17761 | rtx temp = force_reg (TImode, operands[1]); | |
17762 | emit_move_insn (operands[0], temp); | |
17763 | DONE; | |
17764 | } | |
0f40f9f7 | 17765 | }) |
915119a5 BS |
17766 | |
17767 | (define_expand "movv4sf" | |
17768 | [(set (match_operand:V4SF 0 "general_operand" "") | |
17769 | (match_operand:V4SF 1 "general_operand" ""))] | |
17770 | "TARGET_SSE" | |
915119a5 BS |
17771 | { |
17772 | /* For constants other than zero into memory. We do not know how the | |
17773 | instructions used to build constants modify the upper 64 bits | |
17774 | of the register, once we have that information we may be able | |
17775 | to handle some of them more efficiently. */ | |
17776 | if ((reload_in_progress | reload_completed) == 0 | |
17777 | && register_operand (operands[0], V4SFmode) | |
17778 | && CONSTANT_P (operands[1])) | |
17779 | { | |
17780 | rtx addr = gen_reg_rtx (Pmode); | |
17781 | ||
17782 | emit_move_insn (addr, XEXP (force_const_mem (V4SFmode, operands[1]), 0)); | |
17783 | operands[1] = gen_rtx_MEM (V4SFmode, addr); | |
17784 | } | |
17785 | ||
17786 | /* Make operand1 a register if it isn't already. */ | |
17787 | if ((reload_in_progress | reload_completed) == 0 | |
17788 | && !register_operand (operands[0], V4SFmode) | |
17789 | && !register_operand (operands[1], V4SFmode) | |
17790 | && operands[1] != CONST0_RTX (V4SFmode)) | |
17791 | { | |
17792 | rtx temp = force_reg (V4SFmode, operands[1]); | |
17793 | emit_move_insn (operands[0], temp); | |
17794 | DONE; | |
17795 | } | |
0f40f9f7 | 17796 | }) |
915119a5 BS |
17797 | |
17798 | (define_expand "movv4si" | |
17799 | [(set (match_operand:V4SI 0 "general_operand" "") | |
17800 | (match_operand:V4SI 1 "general_operand" ""))] | |
17801 | "TARGET_MMX" | |
915119a5 BS |
17802 | { |
17803 | /* For constants other than zero into memory. We do not know how the | |
17804 | instructions used to build constants modify the upper 64 bits | |
17805 | of the register, once we have that information we may be able | |
17806 | to handle some of them more efficiently. */ | |
17807 | if ((reload_in_progress | reload_completed) == 0 | |
17808 | && register_operand (operands[0], V4SImode) | |
17809 | && CONSTANT_P (operands[1])) | |
17810 | { | |
17811 | rtx addr = gen_reg_rtx (Pmode); | |
17812 | ||
17813 | emit_move_insn (addr, XEXP (force_const_mem (V4SImode, operands[1]), 0)); | |
17814 | operands[1] = gen_rtx_MEM (V4SImode, addr); | |
17815 | } | |
17816 | ||
17817 | /* Make operand1 a register if it isn't already. */ | |
17818 | if ((reload_in_progress | reload_completed) == 0 | |
17819 | && !register_operand (operands[0], V4SImode) | |
17820 | && !register_operand (operands[1], V4SImode) | |
17821 | && operands[1] != CONST0_RTX (V4SImode)) | |
17822 | { | |
17823 | rtx temp = force_reg (V4SImode, operands[1]); | |
17824 | emit_move_insn (operands[0], temp); | |
17825 | DONE; | |
17826 | } | |
0f40f9f7 | 17827 | }) |
915119a5 BS |
17828 | |
17829 | (define_expand "movv2si" | |
17830 | [(set (match_operand:V2SI 0 "general_operand" "") | |
17831 | (match_operand:V2SI 1 "general_operand" ""))] | |
17832 | "TARGET_MMX" | |
915119a5 BS |
17833 | { |
17834 | /* For constants other than zero into memory. We do not know how the | |
17835 | instructions used to build constants modify the upper 64 bits | |
17836 | of the register, once we have that information we may be able | |
17837 | to handle some of them more efficiently. */ | |
17838 | if ((reload_in_progress | reload_completed) == 0 | |
17839 | && register_operand (operands[0], V2SImode) | |
17840 | && CONSTANT_P (operands[1])) | |
17841 | { | |
17842 | rtx addr = gen_reg_rtx (Pmode); | |
17843 | ||
17844 | emit_move_insn (addr, XEXP (force_const_mem (V2SImode, operands[1]), 0)); | |
17845 | operands[1] = gen_rtx_MEM (V2SImode, addr); | |
17846 | } | |
17847 | ||
17848 | /* Make operand1 a register if it isn't already. */ | |
17849 | if ((reload_in_progress | reload_completed) == 0 | |
17850 | && !register_operand (operands[0], V2SImode) | |
17851 | && !register_operand (operands[1], V2SImode) | |
17852 | && operands[1] != CONST0_RTX (V2SImode)) | |
17853 | { | |
17854 | rtx temp = force_reg (V2SImode, operands[1]); | |
17855 | emit_move_insn (operands[0], temp); | |
17856 | DONE; | |
17857 | } | |
0f40f9f7 | 17858 | }) |
915119a5 BS |
17859 | |
17860 | (define_expand "movv4hi" | |
17861 | [(set (match_operand:V4HI 0 "general_operand" "") | |
17862 | (match_operand:V4HI 1 "general_operand" ""))] | |
17863 | "TARGET_MMX" | |
915119a5 BS |
17864 | { |
17865 | /* For constants other than zero into memory. We do not know how the | |
17866 | instructions used to build constants modify the upper 64 bits | |
17867 | of the register, once we have that information we may be able | |
17868 | to handle some of them more efficiently. */ | |
17869 | if ((reload_in_progress | reload_completed) == 0 | |
17870 | && register_operand (operands[0], V4HImode) | |
17871 | && CONSTANT_P (operands[1])) | |
17872 | { | |
17873 | rtx addr = gen_reg_rtx (Pmode); | |
17874 | ||
17875 | emit_move_insn (addr, XEXP (force_const_mem (V4HImode, operands[1]), 0)); | |
17876 | operands[1] = gen_rtx_MEM (V4HImode, addr); | |
17877 | } | |
17878 | ||
17879 | /* Make operand1 a register if it isn't already. */ | |
17880 | if ((reload_in_progress | reload_completed) == 0 | |
17881 | && !register_operand (operands[0], V4HImode) | |
17882 | && !register_operand (operands[1], V4HImode) | |
17883 | && operands[1] != CONST0_RTX (V4HImode)) | |
17884 | { | |
17885 | rtx temp = force_reg (V4HImode, operands[1]); | |
17886 | emit_move_insn (operands[0], temp); | |
17887 | DONE; | |
17888 | } | |
0f40f9f7 | 17889 | }) |
915119a5 BS |
17890 | |
17891 | (define_expand "movv8qi" | |
17892 | [(set (match_operand:V8QI 0 "general_operand" "") | |
17893 | (match_operand:V8QI 1 "general_operand" ""))] | |
17894 | "TARGET_MMX" | |
915119a5 BS |
17895 | { |
17896 | /* For constants other than zero into memory. We do not know how the | |
17897 | instructions used to build constants modify the upper 64 bits | |
17898 | of the register, once we have that information we may be able | |
17899 | to handle some of them more efficiently. */ | |
17900 | if ((reload_in_progress | reload_completed) == 0 | |
17901 | && register_operand (operands[0], V8QImode) | |
17902 | && CONSTANT_P (operands[1])) | |
17903 | { | |
17904 | rtx addr = gen_reg_rtx (Pmode); | |
17905 | ||
17906 | emit_move_insn (addr, XEXP (force_const_mem (V8QImode, operands[1]), 0)); | |
17907 | operands[1] = gen_rtx_MEM (V8QImode, addr); | |
17908 | } | |
17909 | ||
17910 | /* Make operand1 a register if it isn't already. */ | |
17911 | if ((reload_in_progress | reload_completed) == 0 | |
17912 | && !register_operand (operands[0], V8QImode) | |
17913 | && !register_operand (operands[1], V8QImode) | |
17914 | && operands[1] != CONST0_RTX (V8QImode)) | |
17915 | { | |
17916 | rtx temp = force_reg (V8QImode, operands[1]); | |
17917 | emit_move_insn (operands[0], temp); | |
17918 | DONE; | |
17919 | } | |
0f40f9f7 | 17920 | }) |
915119a5 | 17921 | |
47f339cf BS |
17922 | (define_expand "movv2sf" |
17923 | [(set (match_operand:V2SF 0 "general_operand" "") | |
17924 | (match_operand:V2SF 1 "general_operand" ""))] | |
17925 | "TARGET_3DNOW" | |
17926 | " | |
17927 | { | |
17928 | /* For constants other than zero into memory. We do not know how the | |
17929 | instructions used to build constants modify the upper 64 bits | |
17930 | of the register, once we have that information we may be able | |
17931 | to handle some of them more efficiently. */ | |
17932 | if ((reload_in_progress | reload_completed) == 0 | |
17933 | && register_operand (operands[0], V2SFmode) | |
17934 | && CONSTANT_P (operands[1])) | |
17935 | { | |
17936 | rtx addr = gen_reg_rtx (Pmode); | |
17937 | ||
17938 | emit_move_insn (addr, | |
17939 | XEXP (force_const_mem (V2SFmode, operands[1]), 0)); | |
17940 | operands[1] = gen_rtx_MEM (V2SFmode, addr); | |
17941 | } | |
17942 | ||
17943 | /* Make operand1 a register is it isn't already. */ | |
17944 | if ((reload_in_progress | reload_completed) == 0 | |
17945 | && !register_operand (operands[0], V2SFmode) | |
17946 | && !register_operand (operands[1], V2SFmode) | |
17947 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) | |
17948 | && operands[1] != CONST0_RTX (V2SFmode)) | |
17949 | { | |
17950 | rtx temp = force_reg (V2SFmode, operands[1]); | |
17951 | emit_move_insn (operands[0], temp); | |
17952 | DONE; | |
17953 | } | |
17954 | }") | |
17955 | ||
915119a5 BS |
17956 | (define_insn_and_split "*pushti" |
17957 | [(set (match_operand:TI 0 "push_operand" "=<") | |
17958 | (match_operand:TI 1 "nonmemory_operand" "x"))] | |
17959 | "TARGET_SSE" | |
17960 | "#" | |
17961 | "" | |
17962 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) | |
17963 | (set (mem:TI (reg:SI 7)) (match_dup 1))] | |
17964 | "" | |
17965 | [(set_attr "type" "sse")]) | |
17966 | ||
17967 | (define_insn_and_split "*pushv4sf" | |
17968 | [(set (match_operand:V4SF 0 "push_operand" "=<") | |
17969 | (match_operand:V4SF 1 "nonmemory_operand" "x"))] | |
17970 | "TARGET_SSE" | |
17971 | "#" | |
17972 | "" | |
17973 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) | |
17974 | (set (mem:V4SF (reg:SI 7)) (match_dup 1))] | |
17975 | "" | |
17976 | [(set_attr "type" "sse")]) | |
17977 | ||
17978 | (define_insn_and_split "*pushv4si" | |
17979 | [(set (match_operand:V4SI 0 "push_operand" "=<") | |
17980 | (match_operand:V4SI 1 "nonmemory_operand" "x"))] | |
17981 | "TARGET_SSE" | |
17982 | "#" | |
17983 | "" | |
17984 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) | |
17985 | (set (mem:V4SI (reg:SI 7)) (match_dup 1))] | |
17986 | "" | |
17987 | [(set_attr "type" "sse")]) | |
17988 | ||
17989 | (define_insn_and_split "*pushv2si" | |
17990 | [(set (match_operand:V2SI 0 "push_operand" "=<") | |
17991 | (match_operand:V2SI 1 "nonmemory_operand" "y"))] | |
17992 | "TARGET_MMX" | |
17993 | "#" | |
17994 | "" | |
17995 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
17996 | (set (mem:V2SI (reg:SI 7)) (match_dup 1))] | |
17997 | "" | |
17998 | [(set_attr "type" "mmx")]) | |
17999 | ||
18000 | (define_insn_and_split "*pushv4hi" | |
18001 | [(set (match_operand:V4HI 0 "push_operand" "=<") | |
18002 | (match_operand:V4HI 1 "nonmemory_operand" "y"))] | |
18003 | "TARGET_MMX" | |
18004 | "#" | |
18005 | "" | |
18006 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
18007 | (set (mem:V4HI (reg:SI 7)) (match_dup 1))] | |
18008 | "" | |
18009 | [(set_attr "type" "mmx")]) | |
18010 | ||
18011 | (define_insn_and_split "*pushv8qi" | |
18012 | [(set (match_operand:V8QI 0 "push_operand" "=<") | |
18013 | (match_operand:V8QI 1 "nonmemory_operand" "y"))] | |
18014 | "TARGET_MMX" | |
18015 | "#" | |
18016 | "" | |
18017 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
18018 | (set (mem:V8QI (reg:SI 7)) (match_dup 1))] | |
18019 | "" | |
18020 | [(set_attr "type" "mmx")]) | |
18021 | ||
47f339cf BS |
18022 | (define_insn_and_split "*pushv2sf" |
18023 | [(set (match_operand:V2SF 0 "push_operand" "=<") | |
18024 | (match_operand:V2SF 1 "nonmemory_operand" "y"))] | |
18025 | "TARGET_3DNOW" | |
18026 | "#" | |
18027 | "" | |
18028 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
18029 | (set (mem:V2SF (reg:SI 7)) (match_dup 1))] | |
18030 | "" | |
18031 | [(set_attr "type" "mmx")]) | |
18032 | ||
915119a5 BS |
18033 | (define_insn "movti_internal" |
18034 | [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m") | |
18035 | (match_operand:TI 1 "general_operand" "xm,x"))] | |
44cf5b6a | 18036 | "TARGET_SSE && !TARGET_64BIT" |
915119a5 | 18037 | "@ |
0f40f9f7 ZW |
18038 | movaps\t{%1, %0|%0, %1} |
18039 | movaps\t{%1, %0|%0, %1}" | |
915119a5 BS |
18040 | [(set_attr "type" "sse")]) |
18041 | ||
44cf5b6a | 18042 | (define_insn "*movti_rex64" |
92b78122 JH |
18043 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,mx,x") |
18044 | (match_operand:TI 1 "general_operand" "riFo,riF,x,m"))] | |
44cf5b6a JH |
18045 | "TARGET_64BIT |
18046 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
18047 | "@ | |
18048 | # | |
18049 | # | |
18050 | movaps\\t{%1, %0|%0, %1} | |
18051 | movaps\\t{%1, %0|%0, %1}" | |
18052 | [(set_attr "type" "*,*,sse,sse") | |
18053 | (set_attr "mode" "TI")]) | |
18054 | ||
18055 | (define_split | |
18056 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
18057 | (match_operand:TI 1 "general_operand" ""))] | |
4fe8523b JH |
18058 | "reload_completed && !SSE_REG_P (operands[0]) |
18059 | && !SSE_REG_P (operands[1])" | |
44cf5b6a JH |
18060 | [(const_int 0)] |
18061 | "ix86_split_long_move (operands); DONE;") | |
18062 | ||
915119a5 BS |
18063 | ;; These two patterns are useful for specifying exactly whether to use |
18064 | ;; movaps or movups | |
18065 | (define_insn "sse_movaps" | |
18066 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
18067 | (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))] | |
18068 | "TARGET_SSE" | |
18069 | "@ | |
0f40f9f7 ZW |
18070 | movaps\t{%1, %0|%0, %1} |
18071 | movaps\t{%1, %0|%0, %1}" | |
915119a5 BS |
18072 | [(set_attr "type" "sse")]) |
18073 | ||
18074 | (define_insn "sse_movups" | |
18075 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
18076 | (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))] | |
18077 | "TARGET_SSE" | |
18078 | "@ | |
0f40f9f7 ZW |
18079 | movups\t{%1, %0|%0, %1} |
18080 | movups\t{%1, %0|%0, %1}" | |
915119a5 BS |
18081 | [(set_attr "type" "sse")]) |
18082 | ||
18083 | ||
18084 | ;; SSE Strange Moves. | |
18085 | ||
18086 | (define_insn "sse_movmskps" | |
18087 | [(set (match_operand:SI 0 "register_operand" "=r") | |
18088 | (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))] | |
18089 | "TARGET_SSE" | |
0f40f9f7 | 18090 | "movmskps\t{%1, %0|%0, %1}" |
915119a5 BS |
18091 | [(set_attr "type" "sse")]) |
18092 | ||
18093 | (define_insn "mmx_pmovmskb" | |
18094 | [(set (match_operand:SI 0 "register_operand" "=r") | |
18095 | (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))] | |
47f339cf | 18096 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 18097 | "pmovmskb\t{%1, %0|%0, %1}" |
915119a5 BS |
18098 | [(set_attr "type" "sse")]) |
18099 | ||
18100 | (define_insn "mmx_maskmovq" | |
18101 | [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D")) | |
18102 | (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") | |
18103 | (match_operand:V8QI 2 "register_operand" "y")] 32))] | |
47f339cf | 18104 | "TARGET_SSE || TARGET_3DNOW_A" |
915119a5 | 18105 | ;; @@@ check ordering of operands in intel/nonintel syntax |
0f40f9f7 | 18106 | "maskmovq\t{%2, %1|%1, %2}" |
915119a5 BS |
18107 | [(set_attr "type" "sse")]) |
18108 | ||
18109 | (define_insn "sse_movntv4sf" | |
18110 | [(set (match_operand:V4SF 0 "memory_operand" "=m") | |
18111 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))] | |
18112 | "TARGET_SSE" | |
0f40f9f7 | 18113 | "movntps\t{%1, %0|%0, %1}" |
915119a5 BS |
18114 | [(set_attr "type" "sse")]) |
18115 | ||
18116 | (define_insn "sse_movntdi" | |
18117 | [(set (match_operand:DI 0 "memory_operand" "=m") | |
332316cd | 18118 | (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))] |
47f339cf | 18119 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 18120 | "movntq\t{%1, %0|%0, %1}" |
915119a5 BS |
18121 | [(set_attr "type" "sse")]) |
18122 | ||
18123 | (define_insn "sse_movhlps" | |
18124 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18125 | (vec_merge:V4SF | |
18126 | (match_operand:V4SF 1 "register_operand" "0") | |
18127 | (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") | |
18128 | (parallel [(const_int 2) | |
18129 | (const_int 3) | |
18130 | (const_int 0) | |
18131 | (const_int 1)])) | |
18132 | (const_int 3)))] | |
18133 | "TARGET_SSE" | |
0f40f9f7 | 18134 | "movhlps\t{%2, %0|%0, %2}" |
915119a5 BS |
18135 | [(set_attr "type" "sse")]) |
18136 | ||
18137 | (define_insn "sse_movlhps" | |
18138 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18139 | (vec_merge:V4SF | |
18140 | (match_operand:V4SF 1 "register_operand" "0") | |
18141 | (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") | |
18142 | (parallel [(const_int 2) | |
18143 | (const_int 3) | |
18144 | (const_int 0) | |
18145 | (const_int 1)])) | |
18146 | (const_int 12)))] | |
18147 | "TARGET_SSE" | |
0f40f9f7 | 18148 | "movlhps\t{%2, %0|%0, %2}" |
915119a5 BS |
18149 | [(set_attr "type" "sse")]) |
18150 | ||
18151 | (define_insn "sse_movhps" | |
18152 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
18153 | (vec_merge:V4SF | |
18154 | (match_operand:V4SF 1 "nonimmediate_operand" "0,0") | |
18155 | (match_operand:V4SF 2 "nonimmediate_operand" "m,x") | |
18156 | (const_int 12)))] | |
18157 | "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" | |
0f40f9f7 | 18158 | "movhps\t{%2, %0|%0, %2}" |
915119a5 BS |
18159 | [(set_attr "type" "sse")]) |
18160 | ||
18161 | (define_insn "sse_movlps" | |
18162 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
18163 | (vec_merge:V4SF | |
18164 | (match_operand:V4SF 1 "nonimmediate_operand" "0,0") | |
18165 | (match_operand:V4SF 2 "nonimmediate_operand" "m,x") | |
18166 | (const_int 3)))] | |
18167 | "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" | |
0f40f9f7 | 18168 | "movlps\t{%2, %0|%0, %2}" |
915119a5 BS |
18169 | [(set_attr "type" "sse")]) |
18170 | ||
18171 | (define_insn "sse_loadss" | |
18172 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18173 | (vec_merge:V4SF | |
18174 | (match_operand:V4SF 1 "memory_operand" "m") | |
18175 | (vec_duplicate:V4SF (float:SF (const_int 0))) | |
18176 | (const_int 1)))] | |
18177 | "TARGET_SSE" | |
0f40f9f7 | 18178 | "movss\t{%1, %0|%0, %1}" |
915119a5 BS |
18179 | [(set_attr "type" "sse")]) |
18180 | ||
18181 | (define_insn "sse_movss" | |
18182 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18183 | (vec_merge:V4SF | |
18184 | (match_operand:V4SF 1 "register_operand" "0") | |
18185 | (match_operand:V4SF 2 "register_operand" "x") | |
18186 | (const_int 1)))] | |
18187 | "TARGET_SSE" | |
0f40f9f7 | 18188 | "movss\t{%2, %0|%0, %2}" |
915119a5 BS |
18189 | [(set_attr "type" "sse")]) |
18190 | ||
18191 | (define_insn "sse_storess" | |
18192 | [(set (match_operand:SF 0 "memory_operand" "=m") | |
18193 | (vec_select:SF | |
18194 | (match_operand:V4SF 1 "register_operand" "x") | |
18195 | (parallel [(const_int 0)])))] | |
18196 | "TARGET_SSE" | |
0f40f9f7 | 18197 | "movss\t{%1, %0|%0, %1}" |
915119a5 BS |
18198 | [(set_attr "type" "sse")]) |
18199 | ||
18200 | (define_insn "sse_shufps" | |
18201 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18202 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") | |
18203 | (match_operand:V4SF 2 "nonimmediate_operand" "xm") | |
18204 | (match_operand:SI 3 "immediate_operand" "i")] 41))] | |
18205 | "TARGET_SSE" | |
18206 | ;; @@@ check operand order for intel/nonintel syntax | |
0f40f9f7 | 18207 | "shufps\t{%3, %2, %0|%0, %2, %3}" |
915119a5 BS |
18208 | [(set_attr "type" "sse")]) |
18209 | ||
18210 | ||
18211 | ;; SSE arithmetic | |
18212 | ||
18213 | (define_insn "addv4sf3" | |
18214 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18215 | (plus:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18216 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18217 | "TARGET_SSE" | |
0f40f9f7 | 18218 | "addps\t{%2, %0|%0, %2}" |
915119a5 BS |
18219 | [(set_attr "type" "sse")]) |
18220 | ||
18221 | (define_insn "vmaddv4sf3" | |
18222 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18223 | (vec_merge:V4SF (plus:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18224 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18225 | (match_dup 1) | |
18226 | (const_int 1)))] | |
18227 | "TARGET_SSE" | |
0f40f9f7 | 18228 | "addss\t{%2, %0|%0, %2}" |
915119a5 BS |
18229 | [(set_attr "type" "sse")]) |
18230 | ||
18231 | (define_insn "subv4sf3" | |
18232 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18233 | (minus:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18234 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18235 | "TARGET_SSE" | |
0f40f9f7 | 18236 | "subps\t{%2, %0|%0, %2}" |
915119a5 BS |
18237 | [(set_attr "type" "sse")]) |
18238 | ||
18239 | (define_insn "vmsubv4sf3" | |
18240 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18241 | (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18242 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18243 | (match_dup 1) | |
18244 | (const_int 1)))] | |
18245 | "TARGET_SSE" | |
0f40f9f7 | 18246 | "subss\t{%2, %0|%0, %2}" |
915119a5 BS |
18247 | [(set_attr "type" "sse")]) |
18248 | ||
18249 | (define_insn "mulv4sf3" | |
18250 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18251 | (mult:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18252 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18253 | "TARGET_SSE" | |
0f40f9f7 | 18254 | "mulps\t{%2, %0|%0, %2}" |
915119a5 BS |
18255 | [(set_attr "type" "sse")]) |
18256 | ||
18257 | (define_insn "vmmulv4sf3" | |
18258 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18259 | (vec_merge:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18260 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18261 | (match_dup 1) | |
18262 | (const_int 1)))] | |
18263 | "TARGET_SSE" | |
0f40f9f7 | 18264 | "mulss\t{%2, %0|%0, %2}" |
915119a5 BS |
18265 | [(set_attr "type" "sse")]) |
18266 | ||
18267 | (define_insn "divv4sf3" | |
18268 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18269 | (div:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18270 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18271 | "TARGET_SSE" | |
0f40f9f7 | 18272 | "divps\t{%2, %0|%0, %2}" |
915119a5 BS |
18273 | [(set_attr "type" "sse")]) |
18274 | ||
18275 | (define_insn "vmdivv4sf3" | |
18276 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18277 | (vec_merge:V4SF (div:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18278 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18279 | (match_dup 1) | |
18280 | (const_int 1)))] | |
18281 | "TARGET_SSE" | |
0f40f9f7 | 18282 | "divss\t{%2, %0|%0, %2}" |
915119a5 BS |
18283 | [(set_attr "type" "sse")]) |
18284 | ||
18285 | ||
18286 | ;; SSE square root/reciprocal | |
18287 | ||
18288 | (define_insn "rcpv4sf2" | |
18289 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18290 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))] | |
18291 | "TARGET_SSE" | |
0f40f9f7 | 18292 | "rcpps\t{%1, %0|%0, %1}" |
915119a5 BS |
18293 | [(set_attr "type" "sse")]) |
18294 | ||
18295 | (define_insn "vmrcpv4sf2" | |
18296 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18297 | (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42) | |
18298 | (match_operand:V4SF 2 "register_operand" "0") | |
18299 | (const_int 1)))] | |
18300 | "TARGET_SSE" | |
0f40f9f7 | 18301 | "rcpss\t{%1, %0|%0, %1}" |
915119a5 BS |
18302 | [(set_attr "type" "sse")]) |
18303 | ||
18304 | (define_insn "rsqrtv4sf2" | |
18305 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18306 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))] | |
18307 | "TARGET_SSE" | |
0f40f9f7 | 18308 | "rsqrtps\t{%1, %0|%0, %1}" |
915119a5 BS |
18309 | [(set_attr "type" "sse")]) |
18310 | ||
18311 | (define_insn "vmrsqrtv4sf2" | |
18312 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18313 | (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43) | |
18314 | (match_operand:V4SF 2 "register_operand" "0") | |
18315 | (const_int 1)))] | |
18316 | "TARGET_SSE" | |
0f40f9f7 | 18317 | "rsqrtss\t{%1, %0|%0, %1}" |
915119a5 BS |
18318 | [(set_attr "type" "sse")]) |
18319 | ||
18320 | (define_insn "sqrtv4sf2" | |
18321 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18322 | (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))] | |
18323 | "TARGET_SSE" | |
0f40f9f7 | 18324 | "sqrtps\t{%1, %0|%0, %1}" |
915119a5 BS |
18325 | [(set_attr "type" "sse")]) |
18326 | ||
18327 | (define_insn "vmsqrtv4sf2" | |
18328 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18329 | (vec_merge:V4SF (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")) | |
18330 | (match_operand:V4SF 2 "register_operand" "0") | |
18331 | (const_int 1)))] | |
18332 | "TARGET_SSE" | |
0f40f9f7 | 18333 | "sqrtss\t{%1, %0|%0, %1}" |
915119a5 BS |
18334 | [(set_attr "type" "sse")]) |
18335 | ||
18336 | ||
18337 | ;; SSE logical operations. | |
18338 | ||
18339 | ;; These are not called andti3 etc. because we really really don't want | |
18340 | ;; the compiler to widen DImode ands to TImode ands and then try to move | |
18341 | ;; into DImode subregs of SSE registers, and them together, and move out | |
18342 | ;; of DImode subregs again! | |
18343 | ||
c679d048 JH |
18344 | (define_insn "*sse_andti3_df_1" |
18345 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18346 | (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0) | |
18347 | (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))] | |
18348 | "TARGET_SSE2" | |
0f40f9f7 | 18349 | "andpd\t{%2, %0|%0, %2}" |
c679d048 JH |
18350 | [(set_attr "type" "sse")]) |
18351 | ||
18352 | (define_insn "*sse_andti3_df_2" | |
18353 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18354 | (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0) | |
18355 | (match_operand:TI 2 "nonimmediate_operand" "Ym")))] | |
18356 | "TARGET_SSE2" | |
0f40f9f7 | 18357 | "andpd\t{%2, %0|%0, %2}" |
c679d048 JH |
18358 | [(set_attr "type" "sse")]) |
18359 | ||
18360 | (define_insn "*sse_andti3_sf_1" | |
18361 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18362 | (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0) | |
18363 | (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))] | |
18364 | "TARGET_SSE" | |
0f40f9f7 | 18365 | "andps\t{%2, %0|%0, %2}" |
c679d048 JH |
18366 | [(set_attr "type" "sse")]) |
18367 | ||
18368 | (define_insn "*sse_andti3_sf_2" | |
18369 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18370 | (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0) | |
18371 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18372 | "TARGET_SSE" | |
0f40f9f7 | 18373 | "andps\t{%2, %0|%0, %2}" |
c679d048 JH |
18374 | [(set_attr "type" "sse")]) |
18375 | ||
915119a5 BS |
18376 | (define_insn "sse_andti3" |
18377 | [(set (match_operand:TI 0 "register_operand" "=x") | |
c679d048 | 18378 | (and:TI (match_operand:TI 1 "register_operand" "%0") |
915119a5 | 18379 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
c679d048 | 18380 | "TARGET_SSE && !TARGET_SSE2" |
0f40f9f7 | 18381 | "andps\t{%2, %0|%0, %2}" |
915119a5 BS |
18382 | [(set_attr "type" "sse")]) |
18383 | ||
c679d048 JH |
18384 | (define_insn "*sse_andti3_sse2" |
18385 | [(set (match_operand:TI 0 "register_operand" "=x") | |
18386 | (and:TI (match_operand:TI 1 "register_operand" "%0") | |
18387 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18388 | "TARGET_SSE2" | |
0f40f9f7 | 18389 | "pand\t{%2, %0|%0, %2}" |
c679d048 JH |
18390 | [(set_attr "type" "sse")]) |
18391 | ||
18392 | (define_insn "*sse_nandti3_df" | |
18393 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18394 | (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)) | |
18395 | (match_operand:TI 2 "nonimmediate_operand" "Ym")))] | |
18396 | "TARGET_SSE2" | |
0f40f9f7 | 18397 | "andnpd\t{%2, %0|%0, %2}" |
c679d048 JH |
18398 | [(set_attr "type" "sse")]) |
18399 | ||
18400 | (define_insn "*sse_nandti3_sf" | |
18401 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18402 | (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)) | |
18403 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18404 | "TARGET_SSE" | |
0f40f9f7 | 18405 | "andnps\t{%2, %0|%0, %2}" |
c679d048 JH |
18406 | [(set_attr "type" "sse")]) |
18407 | ||
915119a5 BS |
18408 | (define_insn "sse_nandti3" |
18409 | [(set (match_operand:TI 0 "register_operand" "=x") | |
18410 | (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) | |
18411 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
c679d048 | 18412 | "TARGET_SSE && !TARGET_SSE2" |
0f40f9f7 | 18413 | "andnps\t{%2, %0|%0, %2}" |
915119a5 BS |
18414 | [(set_attr "type" "sse")]) |
18415 | ||
c679d048 JH |
18416 | (define_insn "*sse_nandti3_sse2" |
18417 | [(set (match_operand:TI 0 "register_operand" "=x") | |
18418 | (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) | |
18419 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18420 | "TARGET_SSE2" | |
0f40f9f7 | 18421 | "pnand\t{%2, %0|%0, %2}" |
c679d048 JH |
18422 | [(set_attr "type" "sse")]) |
18423 | ||
18424 | (define_insn "*sse_iorti3_df_1" | |
18425 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18426 | (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0) | |
18427 | (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))] | |
18428 | "TARGET_SSE2" | |
0f40f9f7 | 18429 | "orpd\t{%2, %0|%0, %2}" |
c679d048 JH |
18430 | [(set_attr "type" "sse")]) |
18431 | ||
18432 | (define_insn "*sse_iorti3_df_2" | |
18433 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18434 | (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0) | |
18435 | (match_operand:TI 2 "nonimmediate_operand" "Ym")))] | |
18436 | "TARGET_SSE2" | |
0f40f9f7 | 18437 | "orpd\t{%2, %0|%0, %2}" |
c679d048 JH |
18438 | [(set_attr "type" "sse")]) |
18439 | ||
18440 | (define_insn "*sse_iorti3_sf_1" | |
18441 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18442 | (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0) | |
18443 | (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))] | |
18444 | "TARGET_SSE" | |
0f40f9f7 | 18445 | "orps\t{%2, %0|%0, %2}" |
c679d048 JH |
18446 | [(set_attr "type" "sse")]) |
18447 | ||
18448 | (define_insn "*sse_iorti3_sf_2" | |
18449 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18450 | (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0) | |
18451 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18452 | "TARGET_SSE" | |
0f40f9f7 | 18453 | "orps\t{%2, %0|%0, %2}" |
c679d048 JH |
18454 | [(set_attr "type" "sse")]) |
18455 | ||
915119a5 BS |
18456 | (define_insn "sse_iorti3" |
18457 | [(set (match_operand:TI 0 "register_operand" "=x") | |
c679d048 JH |
18458 | (ior:TI (match_operand:TI 1 "register_operand" "%0") |
18459 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18460 | "TARGET_SSE && !TARGET_SSE2" | |
0f40f9f7 | 18461 | "orps\t{%2, %0|%0, %2}" |
c679d048 JH |
18462 | [(set_attr "type" "sse")]) |
18463 | ||
18464 | (define_insn "*sse_iorti3_sse2" | |
18465 | [(set (match_operand:TI 0 "register_operand" "=x") | |
18466 | (ior:TI (match_operand:TI 1 "register_operand" "%0") | |
18467 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18468 | "TARGET_SSE2" | |
0f40f9f7 | 18469 | "por\t{%2, %0|%0, %2}" |
c679d048 JH |
18470 | [(set_attr "type" "sse")]) |
18471 | ||
18472 | (define_insn "*sse_xorti3_df_1" | |
18473 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18474 | (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0) | |
18475 | (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))] | |
18476 | "TARGET_SSE2" | |
0f40f9f7 | 18477 | "xorpd\t{%2, %0|%0, %2}" |
c679d048 JH |
18478 | [(set_attr "type" "sse")]) |
18479 | ||
18480 | (define_insn "*sse_xorti3_df_2" | |
18481 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18482 | (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0) | |
18483 | (match_operand:TI 2 "nonimmediate_operand" "Ym")))] | |
18484 | "TARGET_SSE2" | |
0f40f9f7 | 18485 | "xorpd\t{%2, %0|%0, %2}" |
c679d048 JH |
18486 | [(set_attr "type" "sse")]) |
18487 | ||
18488 | (define_insn "*sse_xorti3_sf_1" | |
18489 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18490 | (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0) | |
18491 | (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))] | |
18492 | "TARGET_SSE" | |
0f40f9f7 | 18493 | "xorps\t{%2, %0|%0, %2}" |
c679d048 JH |
18494 | [(set_attr "type" "sse")]) |
18495 | ||
18496 | (define_insn "*sse_xorti3_sf_2" | |
18497 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18498 | (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0) | |
915119a5 BS |
18499 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
18500 | "TARGET_SSE" | |
0f40f9f7 | 18501 | "xorps\t{%2, %0|%0, %2}" |
915119a5 BS |
18502 | [(set_attr "type" "sse")]) |
18503 | ||
18504 | (define_insn "sse_xorti3" | |
18505 | [(set (match_operand:TI 0 "register_operand" "=x") | |
c679d048 | 18506 | (xor:TI (match_operand:TI 1 "register_operand" "%0") |
915119a5 | 18507 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
c679d048 | 18508 | "TARGET_SSE && !TARGET_SSE2" |
0f40f9f7 | 18509 | "xorps\t{%2, %0|%0, %2}" |
915119a5 BS |
18510 | [(set_attr "type" "sse")]) |
18511 | ||
c679d048 JH |
18512 | (define_insn "*sse_xorti3_sse2" |
18513 | [(set (match_operand:TI 0 "register_operand" "=x") | |
18514 | (xor:TI (match_operand:TI 1 "register_operand" "%0") | |
18515 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18516 | "TARGET_SSE2" | |
0f40f9f7 | 18517 | "pxor\t{%2, %0|%0, %2}" |
c679d048 JH |
18518 | [(set_attr "type" "sse")]) |
18519 | ||
915119a5 BS |
18520 | ;; Use xor, but don't show input operands so they aren't live before |
18521 | ;; this insn. | |
18522 | (define_insn "sse_clrti" | |
18523 | [(set (match_operand:TI 0 "register_operand" "=x") | |
18524 | (unspec:TI [(const_int 0)] 45))] | |
18525 | "TARGET_SSE" | |
0f40f9f7 | 18526 | "xorps\t{%0, %0|%0, %0}" |
29628f27 BS |
18527 | [(set_attr "type" "sse") |
18528 | (set_attr "memory" "none")]) | |
915119a5 BS |
18529 | |
18530 | ;; SSE mask-generating compares | |
18531 | ||
18532 | (define_insn "maskcmpv4sf3" | |
18533 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
18534 | (match_operator:V4SI 3 "sse_comparison_operator" | |
18535 | [(match_operand:V4SF 1 "register_operand" "0") | |
18536 | (match_operand:V4SF 2 "nonimmediate_operand" "x")]))] | |
18537 | "TARGET_SSE" | |
0f40f9f7 | 18538 | "cmp%D3ps\t{%2, %0|%0, %2}" |
915119a5 BS |
18539 | [(set_attr "type" "sse")]) |
18540 | ||
18541 | (define_insn "maskncmpv4sf3" | |
18542 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
18543 | (not:V4SI | |
18544 | (match_operator:V4SI 3 "sse_comparison_operator" | |
18545 | [(match_operand:V4SF 1 "register_operand" "0") | |
18546 | (match_operand:V4SF 2 "nonimmediate_operand" "x")])))] | |
18547 | "TARGET_SSE" | |
29628f27 BS |
18548 | "* |
18549 | { | |
18550 | if (GET_CODE (operands[3]) == UNORDERED) | |
18551 | return \"cmpordps\t{%2, %0|%0, %2}\"; | |
18552 | ||
18553 | return \"cmpn%D3ps\t{%2, %0|%0, %2}\"; | |
18554 | }" | |
915119a5 BS |
18555 | [(set_attr "type" "sse")]) |
18556 | ||
18557 | (define_insn "vmmaskcmpv4sf3" | |
18558 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
18559 | (vec_merge:V4SI | |
18560 | (match_operator:V4SI 3 "sse_comparison_operator" | |
18561 | [(match_operand:V4SF 1 "register_operand" "0") | |
18562 | (match_operand:V4SF 2 "nonimmediate_operand" "x")]) | |
18563 | (match_dup 1) | |
18564 | (const_int 1)))] | |
18565 | "TARGET_SSE" | |
0f40f9f7 | 18566 | "cmp%D3ss\t{%2, %0|%0, %2}" |
915119a5 BS |
18567 | [(set_attr "type" "sse")]) |
18568 | ||
18569 | (define_insn "vmmaskncmpv4sf3" | |
18570 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
18571 | (vec_merge:V4SI | |
18572 | (not:V4SI | |
18573 | (match_operator:V4SI 3 "sse_comparison_operator" | |
18574 | [(match_operand:V4SF 1 "register_operand" "0") | |
18575 | (match_operand:V4SF 2 "nonimmediate_operand" "x")])) | |
18576 | (subreg:V4SI (match_dup 1) 0) | |
18577 | (const_int 1)))] | |
18578 | "TARGET_SSE" | |
29628f27 BS |
18579 | "* |
18580 | { | |
18581 | if (GET_CODE (operands[3]) == UNORDERED) | |
18582 | return \"cmpordss\t{%2, %0|%0, %2}\"; | |
18583 | ||
18584 | return \"cmpn%D3ss\t{%2, %0|%0, %2}\"; | |
18585 | }" | |
915119a5 BS |
18586 | [(set_attr "type" "sse")]) |
18587 | ||
18588 | (define_insn "sse_comi" | |
18589 | [(set (reg:CCFP 17) | |
18590 | (match_operator:CCFP 2 "sse_comparison_operator" | |
18591 | [(vec_select:SF | |
18592 | (match_operand:V4SF 0 "register_operand" "x") | |
18593 | (parallel [(const_int 0)])) | |
18594 | (vec_select:SF | |
18595 | (match_operand:V4SF 1 "register_operand" "x") | |
18596 | (parallel [(const_int 0)]))]))] | |
18597 | "TARGET_SSE" | |
21e1b5f1 | 18598 | "comiss\t{%1, %0|%0, %1}" |
915119a5 BS |
18599 | [(set_attr "type" "sse")]) |
18600 | ||
18601 | (define_insn "sse_ucomi" | |
18602 | [(set (reg:CCFPU 17) | |
18603 | (match_operator:CCFPU 2 "sse_comparison_operator" | |
18604 | [(vec_select:SF | |
18605 | (match_operand:V4SF 0 "register_operand" "x") | |
18606 | (parallel [(const_int 0)])) | |
18607 | (vec_select:SF | |
18608 | (match_operand:V4SF 1 "register_operand" "x") | |
18609 | (parallel [(const_int 0)]))]))] | |
18610 | "TARGET_SSE" | |
21e1b5f1 | 18611 | "ucomiss\t{%1, %0|%0, %1}" |
915119a5 BS |
18612 | [(set_attr "type" "sse")]) |
18613 | ||
18614 | ||
18615 | ;; SSE unpack | |
18616 | ||
18617 | (define_insn "sse_unpckhps" | |
18618 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18619 | (vec_merge:V4SF | |
18620 | (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18621 | (parallel [(const_int 2) | |
18622 | (const_int 0) | |
18623 | (const_int 3) | |
18624 | (const_int 1)])) | |
21e1b5f1 | 18625 | (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") |
915119a5 BS |
18626 | (parallel [(const_int 0) |
18627 | (const_int 2) | |
18628 | (const_int 1) | |
18629 | (const_int 3)])) | |
18630 | (const_int 5)))] | |
18631 | "TARGET_SSE" | |
0f40f9f7 | 18632 | "unpckhps\t{%2, %0|%0, %2}" |
915119a5 BS |
18633 | [(set_attr "type" "sse")]) |
18634 | ||
18635 | (define_insn "sse_unpcklps" | |
18636 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18637 | (vec_merge:V4SF | |
18638 | (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18639 | (parallel [(const_int 0) | |
18640 | (const_int 2) | |
18641 | (const_int 1) | |
18642 | (const_int 3)])) | |
21e1b5f1 | 18643 | (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") |
915119a5 BS |
18644 | (parallel [(const_int 2) |
18645 | (const_int 0) | |
18646 | (const_int 3) | |
18647 | (const_int 1)])) | |
18648 | (const_int 5)))] | |
18649 | "TARGET_SSE" | |
0f40f9f7 | 18650 | "unpcklps\t{%2, %0|%0, %2}" |
915119a5 BS |
18651 | [(set_attr "type" "sse")]) |
18652 | ||
18653 | ||
18654 | ;; SSE min/max | |
18655 | ||
18656 | (define_insn "smaxv4sf3" | |
18657 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18658 | (smax:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18659 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18660 | "TARGET_SSE" | |
0f40f9f7 | 18661 | "maxps\t{%2, %0|%0, %2}" |
915119a5 BS |
18662 | [(set_attr "type" "sse")]) |
18663 | ||
18664 | (define_insn "vmsmaxv4sf3" | |
18665 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18666 | (vec_merge:V4SF (smax:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18667 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18668 | (match_dup 1) | |
18669 | (const_int 1)))] | |
18670 | "TARGET_SSE" | |
0f40f9f7 | 18671 | "maxss\t{%2, %0|%0, %2}" |
915119a5 BS |
18672 | [(set_attr "type" "sse")]) |
18673 | ||
18674 | (define_insn "sminv4sf3" | |
18675 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18676 | (smin:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18677 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18678 | "TARGET_SSE" | |
0f40f9f7 | 18679 | "minps\t{%2, %0|%0, %2}" |
915119a5 BS |
18680 | [(set_attr "type" "sse")]) |
18681 | ||
18682 | (define_insn "vmsminv4sf3" | |
18683 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18684 | (vec_merge:V4SF (smin:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18685 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18686 | (match_dup 1) | |
18687 | (const_int 1)))] | |
18688 | "TARGET_SSE" | |
0f40f9f7 | 18689 | "minss\t{%2, %0|%0, %2}" |
915119a5 BS |
18690 | [(set_attr "type" "sse")]) |
18691 | ||
18692 | ||
18693 | ;; SSE <-> integer/MMX conversions | |
18694 | ||
18695 | (define_insn "cvtpi2ps" | |
18696 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18697 | (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18698 | (vec_duplicate:V4SF | |
18699 | (float:V2SF (match_operand:V2SI 2 "register_operand" "ym"))) | |
18700 | (const_int 12)))] | |
18701 | "TARGET_SSE" | |
0f40f9f7 | 18702 | "cvtpi2ps\t{%2, %0|%0, %2}" |
915119a5 BS |
18703 | [(set_attr "type" "sse")]) |
18704 | ||
18705 | (define_insn "cvtps2pi" | |
18706 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
18707 | (vec_select:V2SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm")) | |
18708 | (parallel | |
18709 | [(const_int 0) | |
18710 | (const_int 1)])))] | |
18711 | "TARGET_SSE" | |
0f40f9f7 | 18712 | "cvtps2pi\t{%1, %0|%0, %1}" |
915119a5 BS |
18713 | [(set_attr "type" "sse")]) |
18714 | ||
18715 | (define_insn "cvttps2pi" | |
18716 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
18717 | (vec_select:V2SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30) | |
18718 | (parallel | |
18719 | [(const_int 0) | |
18720 | (const_int 1)])))] | |
18721 | "TARGET_SSE" | |
0f40f9f7 | 18722 | "cvttps2pi\t{%1, %0|%0, %1}" |
915119a5 BS |
18723 | [(set_attr "type" "sse")]) |
18724 | ||
18725 | (define_insn "cvtsi2ss" | |
18726 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18727 | (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18728 | (vec_duplicate:V4SF | |
18729 | (float:SF (match_operand:SI 2 "register_operand" "rm"))) | |
29628f27 | 18730 | (const_int 14)))] |
915119a5 | 18731 | "TARGET_SSE" |
0f40f9f7 | 18732 | "cvtsi2ss\t{%2, %0|%0, %2}" |
915119a5 BS |
18733 | [(set_attr "type" "sse")]) |
18734 | ||
18735 | (define_insn "cvtss2si" | |
21e1b5f1 | 18736 | [(set (match_operand:SI 0 "register_operand" "=r") |
915119a5 BS |
18737 | (vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm")) |
18738 | (parallel [(const_int 0)])))] | |
18739 | "TARGET_SSE" | |
0f40f9f7 | 18740 | "cvtss2si\t{%1, %0|%0, %1}" |
915119a5 BS |
18741 | [(set_attr "type" "sse")]) |
18742 | ||
18743 | (define_insn "cvttss2si" | |
21e1b5f1 | 18744 | [(set (match_operand:SI 0 "register_operand" "=r") |
915119a5 BS |
18745 | (vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30) |
18746 | (parallel [(const_int 0)])))] | |
18747 | "TARGET_SSE" | |
0f40f9f7 | 18748 | "cvttss2si\t{%1, %0|%0, %1}" |
915119a5 BS |
18749 | [(set_attr "type" "sse")]) |
18750 | ||
18751 | ||
18752 | ;; MMX insns | |
18753 | ||
18754 | ;; MMX arithmetic | |
18755 | ||
18756 | (define_insn "addv8qi3" | |
18757 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
18758 | (plus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
18759 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
18760 | "TARGET_MMX" | |
0f40f9f7 | 18761 | "paddb\t{%2, %0|%0, %2}" |
915119a5 BS |
18762 | [(set_attr "type" "mmx")]) |
18763 | ||
18764 | (define_insn "addv4hi3" | |
18765 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18766 | (plus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
18767 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
18768 | "TARGET_MMX" | |
0f40f9f7 | 18769 | "paddw\t{%2, %0|%0, %2}" |
915119a5 BS |
18770 | [(set_attr "type" "mmx")]) |
18771 | ||
18772 | (define_insn "addv2si3" | |
18773 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
18774 | (plus:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
18775 | (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] | |
18776 | "TARGET_MMX" | |
0f40f9f7 | 18777 | "paddd\t{%2, %0|%0, %2}" |
915119a5 BS |
18778 | [(set_attr "type" "mmx")]) |
18779 | ||
18780 | (define_insn "ssaddv8qi3" | |
18781 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
18782 | (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
18783 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
18784 | "TARGET_MMX" | |
0f40f9f7 | 18785 | "paddsb\t{%2, %0|%0, %2}" |
915119a5 BS |
18786 | [(set_attr "type" "mmx")]) |
18787 | ||
18788 | (define_insn "ssaddv4hi3" | |
18789 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18790 | (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
18791 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
18792 | "TARGET_MMX" | |
0f40f9f7 | 18793 | "paddsw\t{%2, %0|%0, %2}" |
915119a5 BS |
18794 | [(set_attr "type" "mmx")]) |
18795 | ||
18796 | (define_insn "usaddv8qi3" | |
18797 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
18798 | (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
18799 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
18800 | "TARGET_MMX" | |
0f40f9f7 | 18801 | "paddusb\t{%2, %0|%0, %2}" |
915119a5 BS |
18802 | [(set_attr "type" "mmx")]) |
18803 | ||
18804 | (define_insn "usaddv4hi3" | |
18805 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18806 | (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
18807 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
18808 | "TARGET_MMX" | |
0f40f9f7 | 18809 | "paddusw\t{%2, %0|%0, %2}" |
915119a5 BS |
18810 | [(set_attr "type" "mmx")]) |
18811 | ||
18812 | (define_insn "subv8qi3" | |
18813 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
18814 | (minus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
18815 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
18816 | "TARGET_MMX" | |
0f40f9f7 | 18817 | "psubb\t{%2, %0|%0, %2}" |
915119a5 BS |
18818 | [(set_attr "type" "mmx")]) |
18819 | ||
18820 | (define_insn "subv4hi3" | |
18821 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18822 | (minus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
18823 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
18824 | "TARGET_MMX" | |
0f40f9f7 | 18825 | "psubw\t{%2, %0|%0, %2}" |
915119a5 BS |
18826 | [(set_attr "type" "mmx")]) |
18827 | ||
18828 | (define_insn "subv2si3" | |
18829 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
18830 | (minus:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
18831 | (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] | |
18832 | "TARGET_MMX" | |
0f40f9f7 | 18833 | "psubd\t{%2, %0|%0, %2}" |
915119a5 BS |
18834 | [(set_attr "type" "mmx")]) |
18835 | ||
18836 | (define_insn "sssubv8qi3" | |
18837 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
18838 | (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
18839 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
18840 | "TARGET_MMX" | |
0f40f9f7 | 18841 | "psubsb\t{%2, %0|%0, %2}" |
915119a5 BS |
18842 | [(set_attr "type" "mmx")]) |
18843 | ||
18844 | (define_insn "sssubv4hi3" | |
18845 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18846 | (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
18847 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
18848 | "TARGET_MMX" | |
0f40f9f7 | 18849 | "psubsw\t{%2, %0|%0, %2}" |
915119a5 BS |
18850 | [(set_attr "type" "mmx")]) |
18851 | ||
18852 | (define_insn "ussubv8qi3" | |
18853 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
18854 | (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
18855 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
18856 | "TARGET_MMX" | |
0f40f9f7 | 18857 | "psubusb\t{%2, %0|%0, %2}" |
915119a5 BS |
18858 | [(set_attr "type" "mmx")]) |
18859 | ||
18860 | (define_insn "ussubv4hi3" | |
18861 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18862 | (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
18863 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
18864 | "TARGET_MMX" | |
0f40f9f7 | 18865 | "psubusw\t{%2, %0|%0, %2}" |
915119a5 BS |
18866 | [(set_attr "type" "mmx")]) |
18867 | ||
18868 | (define_insn "mulv4hi3" | |
18869 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18870 | (mult:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
18871 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
18872 | "TARGET_MMX" | |
0f40f9f7 | 18873 | "pmullw\t{%2, %0|%0, %2}" |
915119a5 BS |
18874 | [(set_attr "type" "mmx")]) |
18875 | ||
18876 | (define_insn "smulv4hi3_highpart" | |
18877 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18878 | (truncate:V4HI | |
18879 | (lshiftrt:V4SI | |
18880 | (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "0")) | |
18881 | (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
18882 | (const_int 16))))] | |
18883 | "TARGET_MMX" | |
0f40f9f7 | 18884 | "pmulhw\t{%2, %0|%0, %2}" |
915119a5 BS |
18885 | [(set_attr "type" "mmx")]) |
18886 | ||
18887 | (define_insn "umulv4hi3_highpart" | |
18888 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18889 | (truncate:V4HI | |
18890 | (lshiftrt:V4SI | |
18891 | (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "0")) | |
18892 | (zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
18893 | (const_int 16))))] | |
47f339cf | 18894 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 18895 | "pmulhuw\t{%2, %0|%0, %2}" |
915119a5 BS |
18896 | [(set_attr "type" "mmx")]) |
18897 | ||
18898 | (define_insn "mmx_pmaddwd" | |
18899 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
18900 | (plus:V2SI | |
18901 | (mult:V2SI | |
18902 | (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0") | |
18903 | (parallel [(const_int 0) | |
18904 | (const_int 2)]))) | |
18905 | (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym") | |
18906 | (parallel [(const_int 0) | |
18907 | (const_int 2)])))) | |
18908 | (mult:V2SI | |
18909 | (sign_extend:V2SI (vec_select:V2HI (match_dup 1) | |
18910 | (parallel [(const_int 1) | |
18911 | (const_int 3)]))) | |
18912 | (sign_extend:V2SI (vec_select:V2HI (match_dup 2) | |
18913 | (parallel [(const_int 1) | |
18914 | (const_int 3)]))))))] | |
18915 | "TARGET_MMX" | |
0f40f9f7 | 18916 | "pmaddwd\t{%2, %0|%0, %2}" |
915119a5 BS |
18917 | [(set_attr "type" "mmx")]) |
18918 | ||
18919 | ||
18920 | ;; MMX logical operations | |
18921 | ;; Note we don't want to declare these as regular iordi3 insns to prevent | |
18922 | ;; normal code that also wants to use the FPU from getting broken. | |
18923 | ;; The UNSPECs are there to prevent the combiner from getting overly clever. | |
18924 | (define_insn "mmx_iordi3" | |
18925 | [(set (match_operand:DI 0 "register_operand" "=y") | |
18926 | (unspec:DI | |
18927 | [(ior:DI (match_operand:DI 1 "register_operand" "0") | |
18928 | (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))] | |
18929 | "TARGET_MMX" | |
0f40f9f7 | 18930 | "por\t{%2, %0|%0, %2}" |
915119a5 BS |
18931 | [(set_attr "type" "mmx")]) |
18932 | ||
18933 | (define_insn "mmx_xordi3" | |
18934 | [(set (match_operand:DI 0 "register_operand" "=y") | |
18935 | (unspec:DI | |
18936 | [(xor:DI (match_operand:DI 1 "register_operand" "0") | |
18937 | (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))] | |
18938 | "TARGET_MMX" | |
0f40f9f7 | 18939 | "pxor\t{%2, %0|%0, %2}" |
29628f27 BS |
18940 | [(set_attr "type" "mmx") |
18941 | (set_attr "memory" "none")]) | |
915119a5 BS |
18942 | |
18943 | ;; Same as pxor, but don't show input operands so that we don't think | |
18944 | ;; they are live. | |
18945 | (define_insn "mmx_clrdi" | |
18946 | [(set (match_operand:DI 0 "register_operand" "=y") | |
18947 | (unspec:DI [(const_int 0)] 45))] | |
18948 | "TARGET_MMX" | |
0f40f9f7 | 18949 | "pxor\t{%0, %0|%0, %0}" |
915119a5 BS |
18950 | [(set_attr "type" "mmx")]) |
18951 | ||
18952 | (define_insn "mmx_anddi3" | |
18953 | [(set (match_operand:DI 0 "register_operand" "=y") | |
18954 | (unspec:DI | |
18955 | [(and:DI (match_operand:DI 1 "register_operand" "0") | |
18956 | (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))] | |
18957 | "TARGET_MMX" | |
0f40f9f7 | 18958 | "pand\t{%2, %0|%0, %2}" |
915119a5 BS |
18959 | [(set_attr "type" "mmx")]) |
18960 | ||
18961 | (define_insn "mmx_nanddi3" | |
18962 | [(set (match_operand:DI 0 "register_operand" "=y") | |
18963 | (unspec:DI | |
18964 | [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0")) | |
18965 | (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))] | |
18966 | "TARGET_MMX" | |
0f40f9f7 | 18967 | "pandn\t{%2, %0|%0, %2}" |
915119a5 BS |
18968 | [(set_attr "type" "mmx")]) |
18969 | ||
18970 | ||
18971 | ;; MMX unsigned averages/sum of absolute differences | |
18972 | ||
18973 | (define_insn "mmx_uavgv8qi3" | |
18974 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
18975 | (ashiftrt:V8QI | |
18976 | (plus:V8QI (plus:V8QI | |
18977 | (match_operand:V8QI 1 "register_operand" "0") | |
18978 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")) | |
18979 | (vec_const:V8QI (parallel [(const_int 1) | |
18980 | (const_int 1) | |
18981 | (const_int 1) | |
18982 | (const_int 1) | |
18983 | (const_int 1) | |
18984 | (const_int 1) | |
18985 | (const_int 1) | |
18986 | (const_int 1)]))) | |
18987 | (const_int 1)))] | |
47f339cf | 18988 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 18989 | "pavgb\t{%2, %0|%0, %2}" |
915119a5 BS |
18990 | [(set_attr "type" "sse")]) |
18991 | ||
18992 | (define_insn "mmx_uavgv4hi3" | |
18993 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18994 | (ashiftrt:V4HI | |
18995 | (plus:V4HI (plus:V4HI | |
18996 | (match_operand:V4HI 1 "register_operand" "0") | |
18997 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")) | |
18998 | (vec_const:V4HI (parallel [(const_int 1) | |
18999 | (const_int 1) | |
19000 | (const_int 1) | |
19001 | (const_int 1)]))) | |
19002 | (const_int 1)))] | |
47f339cf | 19003 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19004 | "pavgw\t{%2, %0|%0, %2}" |
915119a5 BS |
19005 | [(set_attr "type" "sse")]) |
19006 | ||
19007 | (define_insn "mmx_psadbw" | |
19008 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
332316cd BS |
19009 | (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0") |
19010 | (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))] | |
47f339cf | 19011 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19012 | "psadbw\t{%2, %0|%0, %2}" |
915119a5 BS |
19013 | [(set_attr "type" "sse")]) |
19014 | ||
19015 | ||
19016 | ;; MMX insert/extract/shuffle | |
19017 | ||
19018 | (define_insn "mmx_pinsrw" | |
19019 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19020 | (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19021 | (vec_duplicate:V4HI | |
19022 | (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
19023 | (match_operand:SI 3 "immediate_operand" "i")))] | |
47f339cf | 19024 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19025 | "pinsrw\t{%3, %2, %0|%0, %2, %3}" |
915119a5 BS |
19026 | [(set_attr "type" "sse")]) |
19027 | ||
19028 | (define_insn "mmx_pextrw" | |
19029 | [(set (match_operand:SI 0 "register_operand" "=r") | |
19030 | (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") | |
19031 | (parallel | |
19032 | [(match_operand:SI 2 "immediate_operand" "i")]))))] | |
47f339cf | 19033 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19034 | "pextrw\t{%2, %1, %0|%0, %1, %2}" |
915119a5 BS |
19035 | [(set_attr "type" "sse")]) |
19036 | ||
19037 | (define_insn "mmx_pshufw" | |
19038 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19039 | (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0") | |
29628f27 | 19040 | (match_operand:SI 2 "immediate_operand" "i")] 41))] |
47f339cf | 19041 | "TARGET_SSE || TARGET_3DNOW_A" |
29628f27 | 19042 | "pshufw\t{%2, %1, %0|%0, %1, %2}" |
915119a5 BS |
19043 | [(set_attr "type" "sse")]) |
19044 | ||
19045 | ||
19046 | ;; MMX mask-generating comparisons | |
19047 | ||
19048 | (define_insn "eqv8qi3" | |
19049 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19050 | (eq:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19051 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
19052 | "TARGET_MMX" | |
0f40f9f7 | 19053 | "pcmpeqb\t{%2, %0|%0, %2}" |
915119a5 BS |
19054 | [(set_attr "type" "mmx")]) |
19055 | ||
19056 | (define_insn "eqv4hi3" | |
19057 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19058 | (eq:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19059 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19060 | "TARGET_MMX" | |
0f40f9f7 | 19061 | "pcmpeqw\t{%2, %0|%0, %2}" |
915119a5 BS |
19062 | [(set_attr "type" "mmx")]) |
19063 | ||
19064 | (define_insn "eqv2si3" | |
19065 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19066 | (eq:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19067 | (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] | |
19068 | "TARGET_MMX" | |
0f40f9f7 | 19069 | "pcmpeqd\t{%2, %0|%0, %2}" |
915119a5 BS |
19070 | [(set_attr "type" "mmx")]) |
19071 | ||
19072 | (define_insn "gtv8qi3" | |
19073 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19074 | (gt:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19075 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
19076 | "TARGET_MMX" | |
0f40f9f7 | 19077 | "pcmpgtb\t{%2, %0|%0, %2}" |
915119a5 BS |
19078 | [(set_attr "type" "mmx")]) |
19079 | ||
19080 | (define_insn "gtv4hi3" | |
19081 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19082 | (gt:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19083 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19084 | "TARGET_MMX" | |
0f40f9f7 | 19085 | "pcmpgtw\t{%2, %0|%0, %2}" |
915119a5 BS |
19086 | [(set_attr "type" "mmx")]) |
19087 | ||
19088 | (define_insn "gtv2si3" | |
19089 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19090 | (gt:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19091 | (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] | |
19092 | "TARGET_MMX" | |
0f40f9f7 | 19093 | "pcmpgtd\t{%2, %0|%0, %2}" |
915119a5 BS |
19094 | [(set_attr "type" "mmx")]) |
19095 | ||
19096 | ||
19097 | ;; MMX max/min insns | |
19098 | ||
19099 | (define_insn "umaxv8qi3" | |
19100 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19101 | (umax:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19102 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
47f339cf | 19103 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19104 | "pmaxub\t{%2, %0|%0, %2}" |
915119a5 BS |
19105 | [(set_attr "type" "sse")]) |
19106 | ||
19107 | (define_insn "smaxv4hi3" | |
19108 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19109 | (smax:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19110 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
47f339cf | 19111 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19112 | "pmaxsw\t{%2, %0|%0, %2}" |
915119a5 BS |
19113 | [(set_attr "type" "sse")]) |
19114 | ||
19115 | (define_insn "uminv8qi3" | |
19116 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19117 | (umin:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19118 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
47f339cf | 19119 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19120 | "pminub\t{%2, %0|%0, %2}" |
915119a5 BS |
19121 | [(set_attr "type" "sse")]) |
19122 | ||
19123 | (define_insn "sminv4hi3" | |
19124 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19125 | (smin:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19126 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
47f339cf | 19127 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19128 | "pminsw\t{%2, %0|%0, %2}" |
915119a5 BS |
19129 | [(set_attr "type" "sse")]) |
19130 | ||
19131 | ||
19132 | ;; MMX shifts | |
19133 | ||
19134 | (define_insn "ashrv4hi3" | |
19135 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19136 | (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19137 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19138 | "TARGET_MMX" | |
0f40f9f7 | 19139 | "psraw\t{%2, %0|%0, %2}" |
915119a5 BS |
19140 | [(set_attr "type" "mmx")]) |
19141 | ||
19142 | (define_insn "ashrv2si3" | |
19143 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19144 | (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19145 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19146 | "TARGET_MMX" | |
0f40f9f7 | 19147 | "psrad\t{%2, %0|%0, %2}" |
915119a5 BS |
19148 | [(set_attr "type" "mmx")]) |
19149 | ||
19150 | (define_insn "lshrv4hi3" | |
19151 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19152 | (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19153 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19154 | "TARGET_MMX" | |
0f40f9f7 | 19155 | "psrlw\t{%2, %0|%0, %2}" |
915119a5 BS |
19156 | [(set_attr "type" "mmx")]) |
19157 | ||
19158 | (define_insn "lshrv2si3" | |
19159 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19160 | (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19161 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19162 | "TARGET_MMX" | |
0f40f9f7 | 19163 | "psrld\t{%2, %0|%0, %2}" |
915119a5 BS |
19164 | [(set_attr "type" "mmx")]) |
19165 | ||
19166 | ;; See logical MMX insns. | |
19167 | (define_insn "mmx_lshrdi3" | |
19168 | [(set (match_operand:DI 0 "register_operand" "=y") | |
2b71bf37 JH |
19169 | (unspec:DI |
19170 | [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
19171 | (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))] | |
915119a5 | 19172 | "TARGET_MMX" |
0f40f9f7 | 19173 | "psrlq\t{%2, %0|%0, %2}" |
915119a5 BS |
19174 | [(set_attr "type" "mmx")]) |
19175 | ||
19176 | (define_insn "ashlv4hi3" | |
19177 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19178 | (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19179 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19180 | "TARGET_MMX" | |
0f40f9f7 | 19181 | "psllw\t{%2, %0|%0, %2}" |
915119a5 BS |
19182 | [(set_attr "type" "mmx")]) |
19183 | ||
19184 | (define_insn "ashlv2si3" | |
19185 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19186 | (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19187 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19188 | "TARGET_MMX" | |
0f40f9f7 | 19189 | "pslld\t{%2, %0|%0, %2}" |
915119a5 BS |
19190 | [(set_attr "type" "mmx")]) |
19191 | ||
19192 | ;; See logical MMX insns. | |
19193 | (define_insn "mmx_ashldi3" | |
19194 | [(set (match_operand:DI 0 "register_operand" "=y") | |
2b71bf37 JH |
19195 | (unspec:DI |
19196 | [(ashift:DI (match_operand:DI 1 "register_operand" "0") | |
19197 | (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))] | |
915119a5 | 19198 | "TARGET_MMX" |
0f40f9f7 | 19199 | "psllq\t{%2, %0|%0, %2}" |
915119a5 BS |
19200 | [(set_attr "type" "mmx")]) |
19201 | ||
19202 | ||
19203 | ;; MMX pack/unpack insns. | |
19204 | ||
19205 | (define_insn "mmx_packsswb" | |
19206 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19207 | (vec_concat:V8QI | |
19208 | (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0")) | |
19209 | (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] | |
19210 | "TARGET_MMX" | |
0f40f9f7 | 19211 | "packsswb\t{%2, %0|%0, %2}" |
915119a5 BS |
19212 | [(set_attr "type" "mmx")]) |
19213 | ||
19214 | (define_insn "mmx_packssdw" | |
19215 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19216 | (vec_concat:V4HI | |
19217 | (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0")) | |
19218 | (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] | |
19219 | "TARGET_MMX" | |
0f40f9f7 | 19220 | "packssdw\t{%2, %0|%0, %2}" |
915119a5 BS |
19221 | [(set_attr "type" "mmx")]) |
19222 | ||
19223 | (define_insn "mmx_packuswb" | |
19224 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19225 | (vec_concat:V8QI | |
19226 | (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0")) | |
19227 | (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] | |
19228 | "TARGET_MMX" | |
0f40f9f7 | 19229 | "packuswb\t{%2, %0|%0, %2}" |
915119a5 BS |
19230 | [(set_attr "type" "mmx")]) |
19231 | ||
19232 | (define_insn "mmx_punpckhbw" | |
19233 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19234 | (vec_merge:V8QI | |
19235 | (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19236 | (parallel [(const_int 4) | |
19237 | (const_int 0) | |
19238 | (const_int 5) | |
19239 | (const_int 1) | |
19240 | (const_int 6) | |
19241 | (const_int 2) | |
19242 | (const_int 7) | |
19243 | (const_int 3)])) | |
19244 | (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") | |
19245 | (parallel [(const_int 0) | |
19246 | (const_int 4) | |
19247 | (const_int 1) | |
19248 | (const_int 5) | |
19249 | (const_int 2) | |
19250 | (const_int 6) | |
19251 | (const_int 3) | |
19252 | (const_int 7)])) | |
19253 | (const_int 85)))] | |
19254 | "TARGET_MMX" | |
0f40f9f7 | 19255 | "punpckhbw\t{%2, %0|%0, %2}" |
915119a5 BS |
19256 | [(set_attr "type" "mmx")]) |
19257 | ||
19258 | (define_insn "mmx_punpckhwd" | |
19259 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19260 | (vec_merge:V4HI | |
19261 | (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19262 | (parallel [(const_int 0) | |
19263 | (const_int 2) | |
19264 | (const_int 1) | |
19265 | (const_int 3)])) | |
19266 | (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") | |
19267 | (parallel [(const_int 2) | |
19268 | (const_int 0) | |
19269 | (const_int 3) | |
19270 | (const_int 1)])) | |
19271 | (const_int 5)))] | |
19272 | "TARGET_MMX" | |
0f40f9f7 | 19273 | "punpckhwd\t{%2, %0|%0, %2}" |
915119a5 BS |
19274 | [(set_attr "type" "mmx")]) |
19275 | ||
19276 | (define_insn "mmx_punpckhdq" | |
19277 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19278 | (vec_merge:V2SI | |
19279 | (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19280 | (parallel [(const_int 0) | |
19281 | (const_int 1)])) | |
19282 | (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") | |
19283 | (parallel [(const_int 1) | |
19284 | (const_int 0)])) | |
19285 | (const_int 1)))] | |
19286 | "TARGET_MMX" | |
0f40f9f7 | 19287 | "punpckhdq\t{%2, %0|%0, %2}" |
915119a5 BS |
19288 | [(set_attr "type" "mmx")]) |
19289 | ||
19290 | (define_insn "mmx_punpcklbw" | |
19291 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19292 | (vec_merge:V8QI | |
19293 | (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19294 | (parallel [(const_int 0) | |
19295 | (const_int 4) | |
19296 | (const_int 1) | |
19297 | (const_int 5) | |
19298 | (const_int 2) | |
19299 | (const_int 6) | |
19300 | (const_int 3) | |
19301 | (const_int 7)])) | |
19302 | (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") | |
19303 | (parallel [(const_int 4) | |
19304 | (const_int 0) | |
19305 | (const_int 5) | |
19306 | (const_int 1) | |
19307 | (const_int 6) | |
19308 | (const_int 2) | |
19309 | (const_int 7) | |
19310 | (const_int 3)])) | |
19311 | (const_int 85)))] | |
19312 | "TARGET_MMX" | |
0f40f9f7 | 19313 | "punpcklbw\t{%2, %0|%0, %2}" |
915119a5 BS |
19314 | [(set_attr "type" "mmx")]) |
19315 | ||
19316 | (define_insn "mmx_punpcklwd" | |
19317 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19318 | (vec_merge:V4HI | |
19319 | (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19320 | (parallel [(const_int 2) | |
19321 | (const_int 0) | |
19322 | (const_int 3) | |
19323 | (const_int 1)])) | |
19324 | (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") | |
19325 | (parallel [(const_int 0) | |
19326 | (const_int 2) | |
19327 | (const_int 1) | |
19328 | (const_int 3)])) | |
19329 | (const_int 5)))] | |
19330 | "TARGET_MMX" | |
0f40f9f7 | 19331 | "punpcklwd\t{%2, %0|%0, %2}" |
915119a5 BS |
19332 | [(set_attr "type" "mmx")]) |
19333 | ||
19334 | (define_insn "mmx_punpckldq" | |
19335 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19336 | (vec_merge:V2SI | |
19337 | (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19338 | (parallel [(const_int 1) | |
19339 | (const_int 0)])) | |
19340 | (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") | |
19341 | (parallel [(const_int 0) | |
19342 | (const_int 1)])) | |
19343 | (const_int 1)))] | |
19344 | "TARGET_MMX" | |
0f40f9f7 | 19345 | "punpckldq\t{%2, %0|%0, %2}" |
915119a5 BS |
19346 | [(set_attr "type" "mmx")]) |
19347 | ||
19348 | ||
19349 | ;; Miscellaneous stuff | |
19350 | ||
19351 | (define_insn "emms" | |
19352 | [(unspec_volatile [(const_int 0)] 31) | |
19353 | (clobber (reg:XF 8)) | |
19354 | (clobber (reg:XF 9)) | |
19355 | (clobber (reg:XF 10)) | |
19356 | (clobber (reg:XF 11)) | |
19357 | (clobber (reg:XF 12)) | |
19358 | (clobber (reg:XF 13)) | |
19359 | (clobber (reg:XF 14)) | |
19360 | (clobber (reg:XF 15)) | |
915119a5 BS |
19361 | (clobber (reg:DI 29)) |
19362 | (clobber (reg:DI 30)) | |
19363 | (clobber (reg:DI 31)) | |
19364 | (clobber (reg:DI 32)) | |
19365 | (clobber (reg:DI 33)) | |
bd793c65 BS |
19366 | (clobber (reg:DI 34)) |
19367 | (clobber (reg:DI 35)) | |
19368 | (clobber (reg:DI 36))] | |
915119a5 BS |
19369 | "TARGET_MMX" |
19370 | "emms" | |
bd793c65 BS |
19371 | [(set_attr "type" "mmx") |
19372 | (set_attr "memory" "unknown")]) | |
915119a5 BS |
19373 | |
19374 | (define_insn "ldmxcsr" | |
19375 | [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)] | |
19376 | "TARGET_MMX" | |
0f40f9f7 | 19377 | "ldmxcsr\t%0" |
29628f27 BS |
19378 | [(set_attr "type" "mmx") |
19379 | (set_attr "memory" "load")]) | |
915119a5 BS |
19380 | |
19381 | (define_insn "stmxcsr" | |
19382 | [(set (match_operand:SI 0 "memory_operand" "=m") | |
19383 | (unspec_volatile:SI [(const_int 0)] 40))] | |
19384 | "TARGET_MMX" | |
0f40f9f7 | 19385 | "stmxcsr\t%0" |
29628f27 BS |
19386 | [(set_attr "type" "mmx") |
19387 | (set_attr "memory" "store")]) | |
915119a5 BS |
19388 | |
19389 | (define_expand "sfence" | |
19390 | [(set (match_dup 0) | |
19391 | (unspec:BLK [(match_dup 0)] 44))] | |
47f339cf | 19392 | "TARGET_SSE || TARGET_3DNOW_A" |
915119a5 BS |
19393 | { |
19394 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
19395 | MEM_VOLATILE_P (operands[0]) = 1; | |
0f40f9f7 | 19396 | }) |
915119a5 BS |
19397 | |
19398 | (define_insn "*sfence_insn" | |
19399 | [(set (match_operand:BLK 0 "" "") | |
19400 | (unspec:BLK [(match_dup 0)] 44))] | |
47f339cf | 19401 | "TARGET_SSE || TARGET_3DNOW_A" |
915119a5 | 19402 | "sfence" |
bd793c65 BS |
19403 | [(set_attr "type" "sse") |
19404 | (set_attr "memory" "unknown")]) | |
915119a5 | 19405 | |
f4365627 JH |
19406 | (define_expand "prefetch" |
19407 | [(prefetch (match_operand:SI 0 "address_operand" "p") | |
19408 | (match_operand:SI 1 "const_int_operand" "n") | |
19409 | (match_operand:SI 2 "const_int_operand" "n"))] | |
19410 | "TARGET_PREFETCH_SSE || TARGET_3DNOW" | |
19411 | " | |
19412 | { | |
19413 | int rw = INTVAL (operands[1]); | |
19414 | int locality = INTVAL (operands[2]); | |
19415 | if (rw != 0 && rw != 1) | |
19416 | abort (); | |
19417 | if (locality < 0 || locality > 3) | |
19418 | abort (); | |
19419 | /* Use 3dNOW prefetch in case we are asking for write prefetch not | |
19420 | suported by SSE counterpart or the SSE prefetch is not available | |
19421 | (K6 machines). Otherwise use SSE prefetch as it allows specifying | |
19422 | of locality. */ | |
19423 | if (TARGET_3DNOW | |
19424 | && (!TARGET_PREFETCH_SSE || rw)) | |
19425 | { | |
19426 | emit_insn (gen_prefetch_3dnow (operands[0], operands[1])); | |
19427 | } | |
19428 | else | |
19429 | { | |
19430 | int i; | |
19431 | switch (locality) | |
19432 | { | |
19433 | case 0: /* No temporal locality. */ | |
19434 | i = 0; | |
19435 | break; | |
19436 | case 1: /* Lowest level of temporal locality. */ | |
19437 | i = 3; | |
19438 | break; | |
19439 | case 2: /* Moderate level of temporal locality. */ | |
19440 | i = 2; | |
19441 | break; | |
19442 | case 3: /* Highest level of temporal locality. */ | |
19443 | i = 1; | |
19444 | break; | |
19445 | default: | |
19446 | abort (); /* We already checked for valid values above. */ | |
19447 | break; | |
19448 | } | |
19449 | emit_insn (gen_prefetch_sse (operands[0], GEN_INT (i))); | |
19450 | } | |
19451 | DONE; | |
19452 | }") | |
19453 | ||
7a9aba6c | 19454 | (define_insn "prefetch_sse" |
915119a5 | 19455 | [(unspec [(match_operand:SI 0 "address_operand" "p") |
332316cd | 19456 | (match_operand:SI 1 "immediate_operand" "n")] 35)] |
f4365627 | 19457 | "TARGET_PREFETCH_SSE" |
915119a5 BS |
19458 | { |
19459 | switch (INTVAL (operands[1])) | |
19460 | { | |
19461 | case 0: | |
0f40f9f7 | 19462 | return "prefetchnta\t%a0"; |
915119a5 | 19463 | case 1: |
0f40f9f7 | 19464 | return "prefetcht0\t%a0"; |
915119a5 | 19465 | case 2: |
0f40f9f7 | 19466 | return "prefetcht1\t%a0"; |
915119a5 | 19467 | case 3: |
0f40f9f7 | 19468 | return "prefetcht2\t%a0"; |
915119a5 BS |
19469 | default: |
19470 | abort (); | |
19471 | } | |
0f40f9f7 | 19472 | } |
915119a5 BS |
19473 | [(set_attr "type" "sse")]) |
19474 | ||
ad919812 JH |
19475 | (define_expand "sse_prologue_save" |
19476 | [(parallel [(set (match_operand:BLK 0 "" "") | |
19477 | (unspec:BLK [(reg:DI 21) | |
19478 | (reg:DI 22) | |
19479 | (reg:DI 23) | |
19480 | (reg:DI 24) | |
19481 | (reg:DI 25) | |
19482 | (reg:DI 26) | |
19483 | (reg:DI 27) | |
19484 | (reg:DI 28)] 13)) | |
19485 | (use (match_operand:DI 1 "register_operand" "")) | |
19486 | (use (match_operand:DI 2 "immediate_operand" "")) | |
19487 | (use (label_ref:DI (match_operand 3 "" "")))])] | |
19488 | "TARGET_64BIT" | |
19489 | "") | |
19490 | ||
19491 | (define_insn "*sse_prologue_save_insn" | |
19492 | [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R") | |
19493 | (match_operand:DI 4 "const_int_operand" "n"))) | |
19494 | (unspec:BLK [(reg:DI 21) | |
19495 | (reg:DI 22) | |
19496 | (reg:DI 23) | |
19497 | (reg:DI 24) | |
19498 | (reg:DI 25) | |
19499 | (reg:DI 26) | |
19500 | (reg:DI 27) | |
19501 | (reg:DI 28)] 13)) | |
19502 | (use (match_operand:DI 1 "register_operand" "r")) | |
19503 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
19504 | (use (label_ref:DI (match_operand 3 "" "X")))] | |
19505 | "TARGET_64BIT | |
19506 | && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128 | |
19507 | && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128" | |
19508 | "* | |
19509 | { | |
19510 | int i; | |
19511 | operands[0] = gen_rtx_MEM (Pmode, | |
19512 | gen_rtx_PLUS (Pmode, operands[0], operands[4])); | |
19513 | output_asm_insn (\"jmp\\t%A1\", operands); | |
19514 | for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--) | |
19515 | { | |
19516 | operands[4] = adjust_address (operands[0], DImode, i*16); | |
19517 | operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i)); | |
19518 | PUT_MODE (operands[4], TImode); | |
19519 | if (GET_CODE (XEXP (operands[0], 0)) != PLUS) | |
19520 | output_asm_insn (\"rex\", operands); | |
19521 | output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands); | |
19522 | } | |
19523 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", | |
19524 | CODE_LABEL_NUMBER (operands[3])); | |
19525 | RET; | |
19526 | } | |
19527 | " | |
19528 | [(set_attr "type" "other") | |
19529 | (set_attr "length_immediate" "0") | |
19530 | (set_attr "length_address" "0") | |
19531 | (set_attr "length" "135") | |
19532 | (set_attr "memory" "store") | |
19533 | (set_attr "modrm" "0") | |
19534 | (set_attr "mode" "DI")]) | |
47f339cf BS |
19535 | |
19536 | ;; 3Dnow! instructions | |
19537 | ||
19538 | (define_insn "addv2sf3" | |
19539 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19540 | (plus:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19541 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19542 | "TARGET_3DNOW" | |
19543 | "pfadd\\t{%2, %0|%0, %2}" | |
19544 | [(set_attr "type" "mmx")]) | |
19545 | ||
19546 | (define_insn "subv2sf3" | |
19547 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19548 | (minus:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19549 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19550 | "TARGET_3DNOW" | |
19551 | "pfsub\\t{%2, %0|%0, %2}" | |
19552 | [(set_attr "type" "mmx")]) | |
19553 | ||
19554 | (define_insn "subrv2sf3" | |
19555 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19556 | (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym") | |
19557 | (match_operand:V2SF 1 "register_operand" "0")))] | |
19558 | "TARGET_3DNOW" | |
19559 | "pfsubr\\t{%2, %0|%0, %2}" | |
19560 | [(set_attr "type" "mmx")]) | |
19561 | ||
19562 | (define_insn "gtv2sf3" | |
19563 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19564 | (gt:V2SI (match_operand:V2SF 1 "register_operand" "0") | |
19565 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19566 | "TARGET_3DNOW" | |
19567 | "pfcmpgt\\t{%2, %0|%0, %2}" | |
19568 | [(set_attr "type" "mmx")]) | |
19569 | ||
19570 | (define_insn "gev2sf3" | |
19571 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19572 | (ge:V2SI (match_operand:V2SF 1 "register_operand" "0") | |
19573 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19574 | "TARGET_3DNOW" | |
19575 | "pfcmpge\\t{%2, %0|%0, %2}" | |
19576 | [(set_attr "type" "mmx")]) | |
19577 | ||
19578 | (define_insn "eqv2sf3" | |
19579 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19580 | (eq:V2SI (match_operand:V2SF 1 "register_operand" "0") | |
19581 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19582 | "TARGET_3DNOW" | |
19583 | "pfcmpeq\\t{%2, %0|%0, %2}" | |
19584 | [(set_attr "type" "mmx")]) | |
19585 | ||
19586 | (define_insn "pfmaxv2sf3" | |
19587 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19588 | (smax:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19589 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19590 | "TARGET_3DNOW" | |
19591 | "pfmax\\t{%2, %0|%0, %2}" | |
19592 | [(set_attr "type" "mmx")]) | |
19593 | ||
19594 | (define_insn "pfminv2sf3" | |
19595 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19596 | (smin:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19597 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19598 | "TARGET_3DNOW" | |
19599 | "pfmin\\t{%2, %0|%0, %2}" | |
19600 | [(set_attr "type" "mmx")]) | |
19601 | ||
19602 | (define_insn "mulv2sf3" | |
19603 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19604 | (mult:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19605 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19606 | "TARGET_3DNOW" | |
19607 | "pfmul\\t{%2, %0|%0, %2}" | |
19608 | [(set_attr "type" "mmx")]) | |
19609 | ||
19610 | (define_insn "femms" | |
19611 | [(unspec_volatile [(const_int 0)] 46) | |
19612 | (clobber (reg:XF 8)) | |
19613 | (clobber (reg:XF 9)) | |
19614 | (clobber (reg:XF 10)) | |
19615 | (clobber (reg:XF 11)) | |
19616 | (clobber (reg:XF 12)) | |
19617 | (clobber (reg:XF 13)) | |
19618 | (clobber (reg:XF 14)) | |
19619 | (clobber (reg:XF 15)) | |
19620 | (clobber (reg:DI 29)) | |
19621 | (clobber (reg:DI 30)) | |
19622 | (clobber (reg:DI 31)) | |
19623 | (clobber (reg:DI 32)) | |
19624 | (clobber (reg:DI 33)) | |
19625 | (clobber (reg:DI 34)) | |
19626 | (clobber (reg:DI 35)) | |
19627 | (clobber (reg:DI 36))] | |
19628 | "TARGET_3DNOW" | |
19629 | "femms" | |
19630 | [(set_attr "type" "mmx")]) | |
19631 | ||
19632 | (define_insn "prefetch_3dnow" | |
f4365627 JH |
19633 | [(prefetch (match_operand:SI 0 "address_operand" "p") |
19634 | (match_operand:SI 1 "const_int_operand" "n") | |
19635 | (const_int 0))] | |
47f339cf | 19636 | "TARGET_3DNOW" |
f4365627 JH |
19637 | { |
19638 | if (INTVAL (operands[1]) == 0) | |
19639 | return "prefetch\t%a0"; | |
19640 | else | |
19641 | return "prefetchw\t%a0"; | |
19642 | } | |
47f339cf BS |
19643 | [(set_attr "type" "mmx")]) |
19644 | ||
19645 | (define_insn "pf2id" | |
19646 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19647 | (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))] | |
19648 | "TARGET_3DNOW" | |
19649 | "pf2id\\t{%1, %0|%0, %1}" | |
19650 | [(set_attr "type" "mmx")]) | |
19651 | ||
19652 | (define_insn "pf2iw" | |
19653 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19654 | (sign_extend:V2SI | |
19655 | (ss_truncate:V2HI | |
19656 | (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))] | |
19657 | "TARGET_3DNOW_A" | |
19658 | "pf2iw\\t{%1, %0|%0, %1}" | |
19659 | [(set_attr "type" "mmx")]) | |
19660 | ||
19661 | (define_insn "pfacc" | |
19662 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19663 | (vec_concat:V2SF | |
19664 | (plus:SF | |
19665 | (vec_select:SF (match_operand:V2SF 1 "register_operand" "0") | |
19666 | (parallel [(const_int 0)])) | |
19667 | (vec_select:SF (match_dup 1) | |
19668 | (parallel [(const_int 1)]))) | |
19669 | (plus:SF | |
19670 | (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y") | |
19671 | (parallel [(const_int 0)])) | |
19672 | (vec_select:SF (match_dup 2) | |
19673 | (parallel [(const_int 1)])))))] | |
19674 | "TARGET_3DNOW" | |
19675 | "pfacc\\t{%2, %0|%0, %2}" | |
19676 | [(set_attr "type" "mmx")]) | |
19677 | ||
19678 | (define_insn "pfnacc" | |
19679 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19680 | (vec_concat:V2SF | |
19681 | (minus:SF | |
19682 | (vec_select:SF (match_operand:V2SF 1 "register_operand" "0") | |
19683 | (parallel [(const_int 0)])) | |
19684 | (vec_select:SF (match_dup 1) | |
19685 | (parallel [(const_int 1)]))) | |
19686 | (minus:SF | |
19687 | (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y") | |
19688 | (parallel [(const_int 0)])) | |
19689 | (vec_select:SF (match_dup 2) | |
19690 | (parallel [(const_int 1)])))))] | |
19691 | "TARGET_3DNOW_A" | |
19692 | "pfnacc\\t{%2, %0|%0, %2}" | |
19693 | [(set_attr "type" "mmx")]) | |
19694 | ||
19695 | (define_insn "pfpnacc" | |
19696 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19697 | (vec_concat:V2SF | |
19698 | (minus:SF | |
19699 | (vec_select:SF (match_operand:V2SF 1 "register_operand" "0") | |
19700 | (parallel [(const_int 0)])) | |
19701 | (vec_select:SF (match_dup 1) | |
19702 | (parallel [(const_int 1)]))) | |
19703 | (plus:SF | |
19704 | (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y") | |
19705 | (parallel [(const_int 0)])) | |
19706 | (vec_select:SF (match_dup 2) | |
19707 | (parallel [(const_int 1)])))))] | |
19708 | "TARGET_3DNOW_A" | |
19709 | "pfpnacc\\t{%2, %0|%0, %2}" | |
19710 | [(set_attr "type" "mmx")]) | |
19711 | ||
19712 | (define_insn "pi2fw" | |
19713 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19714 | (float:V2SF | |
19715 | (vec_concat:V2SI | |
19716 | (sign_extend:SI | |
19717 | (truncate:HI | |
19718 | (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym") | |
19719 | (parallel [(const_int 0)])))) | |
19720 | (sign_extend:SI | |
19721 | (truncate:HI | |
19722 | (vec_select:SI (match_dup 1) | |
19723 | (parallel [(const_int 1)])))))))] | |
19724 | "TARGET_3DNOW_A" | |
19725 | "pi2fw\\t{%1, %0|%0, %1}" | |
19726 | [(set_attr "type" "mmx")]) | |
19727 | ||
19728 | (define_insn "floatv2si2" | |
19729 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19730 | (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))] | |
19731 | "TARGET_3DNOW" | |
19732 | "pi2fd\\t{%1, %0|%0, %1}" | |
19733 | [(set_attr "type" "mmx")]) | |
19734 | ||
19735 | ;; This insn is identical to pavgb in operation, but the opcode is | |
19736 | ;; different. To avoid accidentally matching pavgb, use an unspec. | |
19737 | ||
19738 | (define_insn "pavgusb" | |
19739 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19740 | (unspec:V8QI | |
19741 | [(match_operand:V8QI 1 "register_operand" "0") | |
19742 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")] 49))] | |
19743 | "TARGET_3DNOW" | |
19744 | "pavgusb\\t{%2, %0|%0, %2}" | |
19745 | [(set_attr "type" "mmx")]) | |
19746 | ||
19747 | ;; 3DNow reciprical and sqrt | |
19748 | ||
19749 | (define_insn "pfrcpv2sf2" | |
19750 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19751 | (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 50))] | |
19752 | "TARGET_3DNOW" | |
19753 | "pfrcp\\t{%1, %0|%0, %1}" | |
19754 | [(set_attr "type" "mmx")]) | |
19755 | ||
19756 | (define_insn "pfrcpit1v2sf3" | |
19757 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19758 | (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") | |
19759 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 51))] | |
19760 | "TARGET_3DNOW" | |
19761 | "pfrcpit1\\t{%2, %0|%0, %2}" | |
19762 | [(set_attr "type" "mmx")]) | |
19763 | ||
19764 | (define_insn "pfrcpit2v2sf3" | |
19765 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19766 | (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") | |
19767 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 52))] | |
19768 | "TARGET_3DNOW" | |
19769 | "pfrcpit2\\t{%2, %0|%0, %2}" | |
19770 | [(set_attr "type" "mmx")]) | |
19771 | ||
19772 | (define_insn "pfrsqrtv2sf2" | |
19773 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19774 | (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 53))] | |
19775 | "TARGET_3DNOW" | |
19776 | "pfrsqrt\\t{%1, %0|%0, %1}" | |
19777 | [(set_attr "type" "mmx")]) | |
19778 | ||
19779 | (define_insn "pfrsqit1v2sf3" | |
19780 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19781 | (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") | |
19782 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")] 54))] | |
19783 | "TARGET_3DNOW" | |
19784 | "pfrsqit1\\t{%2, %0|%0, %2}" | |
19785 | [(set_attr "type" "mmx")]) | |
19786 | ||
19787 | (define_insn "pmulhrwv4hi3" | |
19788 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19789 | (truncate:V4HI | |
19790 | (lshiftrt:V4SI | |
19791 | (plus:V4SI | |
19792 | (mult:V4SI | |
19793 | (sign_extend:V4SI | |
19794 | (match_operand:V4HI 1 "register_operand" "0")) | |
19795 | (sign_extend:V4SI | |
19796 | (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
19797 | (vec_const:V4SI | |
53c98b1f DD |
19798 | (parallel [(const_int 32768) |
19799 | (const_int 32768) | |
19800 | (const_int 32768) | |
19801 | (const_int 32768)]))) | |
47f339cf BS |
19802 | (const_int 16))))] |
19803 | "TARGET_3DNOW" | |
19804 | "pmulhrw\\t{%2, %0|%0, %2}" | |
19805 | [(set_attr "type" "mmx")]) | |
19806 | ||
19807 | (define_insn "pswapdv2si2" | |
19808 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19809 | (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym") | |
19810 | (parallel [(const_int 1) (const_int 0)])))] | |
19811 | "TARGET_3DNOW_A" | |
19812 | "pswapd\\t{%1, %0|%0, %1}" | |
19813 | [(set_attr "type" "mmx")]) | |
19814 | ||
19815 | (define_insn "pswapdv2sf2" | |
19816 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19817 | (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym") | |
19818 | (parallel [(const_int 1) (const_int 0)])))] | |
19819 | "TARGET_3DNOW_A" | |
19820 | "pswapd\\t{%1, %0|%0, %1}" | |
19821 | [(set_attr "type" "mmx")]) |