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d2836273 | 1 | ;; GCC machine description for IA-32 and x86-64. |
e03f5d43 | 2 | ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
4592bdcb | 3 | ;; Free Software Foundation, Inc. |
886c62d1 | 4 | ;; Mostly by William Schelter. |
d2836273 | 5 | ;; x86_64 support added by Jan Hubicka |
e075ae69 | 6 | ;; |
886c62d1 | 7 | ;; This file is part of GNU CC. |
e075ae69 | 8 | ;; |
886c62d1 JVA |
9 | ;; GNU CC is free software; you can redistribute it and/or modify |
10 | ;; it under the terms of the GNU General Public License as published by | |
11 | ;; the Free Software Foundation; either version 2, or (at your option) | |
12 | ;; any later version. | |
e075ae69 | 13 | ;; |
886c62d1 JVA |
14 | ;; GNU CC is distributed in the hope that it will be useful, |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
e075ae69 | 18 | ;; |
886c62d1 JVA |
19 | ;; You should have received a copy of the GNU General Public License |
20 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 | 21 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
892a2d68 | 22 | ;; Boston, MA 02111-1307, USA. */ |
e075ae69 | 23 | ;; |
4af3895e JVA |
24 | ;; The original PO technology requires these to be ordered by speed, |
25 | ;; so that assigner will pick the fastest. | |
e075ae69 | 26 | ;; |
4af3895e | 27 | ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. |
e075ae69 | 28 | ;; |
4af3895e JVA |
29 | ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code |
30 | ;; updates for most instructions. | |
e075ae69 | 31 | ;; |
4af3895e JVA |
32 | ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register |
33 | ;; constraint letters. | |
e075ae69 RH |
34 | ;; |
35 | ;; The special asm out single letter directives following a '%' are: | |
4af3895e JVA |
36 | ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of |
37 | ;; operands[1]. | |
38 | ;; 'L' Print the opcode suffix for a 32-bit integer opcode. | |
39 | ;; 'W' Print the opcode suffix for a 16-bit integer opcode. | |
40 | ;; 'B' Print the opcode suffix for an 8-bit integer opcode. | |
4af3895e | 41 | ;; 'Q' Print the opcode suffix for a 64-bit float opcode. |
56710e42 | 42 | ;; 'S' Print the opcode suffix for a 32-bit float opcode. |
b08de47e MM |
43 | ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode. |
44 | ;; 'J' Print the appropriate jump operand. | |
e075ae69 | 45 | ;; |
4af3895e JVA |
46 | ;; 'b' Print the QImode name of the register for the indicated operand. |
47 | ;; %b0 would print %al if operands[0] is reg 0. | |
48 | ;; 'w' Likewise, print the HImode name of the register. | |
49 | ;; 'k' Likewise, print the SImode name of the register. | |
50 | ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. | |
51 | ;; 'y' Print "st(0)" instead of "st" as a register. | |
8ee41eaf | 52 | |
4af3895e | 53 | ;; UNSPEC usage: |
8ee41eaf RH |
54 | |
55 | (define_constants | |
f996902d RH |
56 | [; Relocation specifiers |
57 | (UNSPEC_GOT 0) | |
58 | (UNSPEC_GOTOFF 1) | |
59 | (UNSPEC_GOTPCREL 2) | |
60 | (UNSPEC_GOTTPOFF 3) | |
61 | (UNSPEC_TPOFF 4) | |
62 | (UNSPEC_NTPOFF 5) | |
63 | (UNSPEC_DTPOFF 6) | |
dea73790 JJ |
64 | (UNSPEC_GOTNTPOFF 7) |
65 | (UNSPEC_INDNTPOFF 8) | |
f996902d RH |
66 | |
67 | ; Prologue support | |
68 | (UNSPEC_STACK_PROBE 10) | |
69 | (UNSPEC_STACK_ALLOC 11) | |
70 | (UNSPEC_SET_GOT 12) | |
8ee41eaf | 71 | (UNSPEC_SSE_PROLOGUE_SAVE 13) |
f996902d RH |
72 | |
73 | ; TLS support | |
74 | (UNSPEC_TP 15) | |
75 | (UNSPEC_TLS_GD 16) | |
76 | (UNSPEC_TLS_LD_BASE 17) | |
77 | ||
78 | ; Other random patterns | |
79 | (UNSPEC_SCAS 20) | |
80 | (UNSPEC_SIN 21) | |
81 | (UNSPEC_COS 22) | |
82 | (UNSPEC_BSF 23) | |
83 | (UNSPEC_FNSTSW 24) | |
84 | (UNSPEC_SAHF 25) | |
85 | (UNSPEC_FSTCW 26) | |
86 | (UNSPEC_ADD_CARRY 27) | |
87 | (UNSPEC_FLDCW 28) | |
8ee41eaf RH |
88 | |
89 | ; For SSE/MMX support: | |
90 | (UNSPEC_FIX 30) | |
91 | (UNSPEC_MASKMOV 32) | |
92 | (UNSPEC_MOVMSK 33) | |
93 | (UNSPEC_MOVNT 34) | |
94 | (UNSPEC_MOVA 38) | |
95 | (UNSPEC_MOVU 39) | |
96 | (UNSPEC_SHUFFLE 41) | |
97 | (UNSPEC_RCP 42) | |
98 | (UNSPEC_RSQRT 43) | |
99 | (UNSPEC_SFENCE 44) | |
100 | (UNSPEC_NOP 45) ; prevents combiner cleverness | |
101 | (UNSPEC_PAVGUSB 49) | |
102 | (UNSPEC_PFRCP 50) | |
103 | (UNSPEC_PFRCPIT1 51) | |
104 | (UNSPEC_PFRCPIT2 52) | |
105 | (UNSPEC_PFRSQRT 53) | |
106 | (UNSPEC_PFRSQIT1 54) | |
107 | (UNSPEC_PSHUFLW 55) | |
108 | (UNSPEC_PSHUFHW 56) | |
109 | (UNSPEC_MFENCE 59) | |
110 | (UNSPEC_LFENCE 60) | |
111 | (UNSPEC_PSADBW 61) | |
112 | ]) | |
113 | ||
114 | (define_constants | |
115 | [(UNSPECV_BLOCKAGE 0) | |
8ee41eaf RH |
116 | (UNSPECV_EH_RETURN 13) |
117 | (UNSPECV_EMMS 31) | |
118 | (UNSPECV_LDMXCSR 37) | |
119 | (UNSPECV_STMXCSR 40) | |
120 | (UNSPECV_FEMMS 46) | |
121 | (UNSPECV_CLFLUSH 57) | |
122 | ]) | |
915119a5 | 123 | |
6343a50e ZW |
124 | ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls |
125 | ;; from i386.c. | |
126 | ||
1b0c37d7 ZW |
127 | ;; In C guard expressions, put expressions which may be compile-time |
128 | ;; constants first. This allows for better optimization. For | |
129 | ;; example, write "TARGET_64BIT && reload_completed", not | |
130 | ;; "reload_completed && TARGET_64BIT". | |
131 | ||
2ae0f82c | 132 | \f |
e075ae69 RH |
133 | ;; Processor type. This attribute must exactly match the processor_type |
134 | ;; enumeration in i386.h. | |
b4e89e2d | 135 | (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4" |
e075ae69 | 136 | (const (symbol_ref "ix86_cpu"))) |
2ae0f82c | 137 | |
e075ae69 RH |
138 | ;; A basic instruction type. Refinements due to arguments to be |
139 | ;; provided in other attributes. | |
a269a03c | 140 | (define_attr "type" |
9a5834ae ZW |
141 | "other,multi, |
142 | alu,alu1,negnot,imov,imovx,lea, | |
143 | incdec,ishift,rotate,imul,idiv, | |
144 | icmp,test,ibr,setcc,icmov, | |
145 | push,pop,call,callv, | |
146 | str,cld, | |
147 | fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp, | |
148 | sselog,sseiadd,sseishft,sseimul, | |
149 | sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv, | |
150 | mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft" | |
e075ae69 RH |
151 | (const_string "other")) |
152 | ||
6ef67412 | 153 | ;; Main data type used by the insn |
9a5834ae ZW |
154 | (define_attr "mode" |
155 | "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI,V4SF,V2DF,V2SF" | |
6ef67412 JH |
156 | (const_string "unknown")) |
157 | ||
3d34cd91 JH |
158 | ;; The CPU unit operations uses. |
159 | (define_attr "unit" "integer,i387,sse,mmx,unknown" | |
160 | (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp") | |
161 | (const_string "i387") | |
9a5834ae ZW |
162 | (eq_attr "type" "sselog,sseiadd,sseishft,sseimul, |
163 | sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv") | |
3d34cd91 | 164 | (const_string "sse") |
9a5834ae | 165 | (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft") |
3d34cd91 JH |
166 | (const_string "mmx")] |
167 | (const_string "integer"))) | |
6ef67412 JH |
168 | |
169 | ;; The (bounding maximum) length of an instruction immediate. | |
170 | (define_attr "length_immediate" "" | |
c7375e61 | 171 | (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv") |
6ef67412 | 172 | (const_int 0) |
3d34cd91 | 173 | (eq_attr "unit" "i387,sse,mmx") |
6ef67412 | 174 | (const_int 0) |
9a5834ae ZW |
175 | (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,imul, |
176 | icmp,push,pop") | |
6ef67412 JH |
177 | (symbol_ref "ix86_attr_length_immediate_default(insn,1)") |
178 | (eq_attr "type" "imov,test") | |
179 | (symbol_ref "ix86_attr_length_immediate_default(insn,0)") | |
180 | (eq_attr "type" "call") | |
181 | (if_then_else (match_operand 0 "constant_call_address_operand" "") | |
182 | (const_int 4) | |
183 | (const_int 0)) | |
184 | (eq_attr "type" "callv") | |
185 | (if_then_else (match_operand 1 "constant_call_address_operand" "") | |
186 | (const_int 4) | |
187 | (const_int 0)) | |
188 | (eq_attr "type" "ibr") | |
189 | (if_then_else (and (ge (minus (match_dup 0) (pc)) | |
190 | (const_int -128)) | |
191 | (lt (minus (match_dup 0) (pc)) | |
192 | (const_int 124))) | |
193 | (const_int 1) | |
194 | (const_int 4)) | |
195 | ] | |
9a5834ae ZW |
196 | (symbol_ref "/* Update immediate_length and other attributes! */ |
197 | abort(),1"))) | |
e075ae69 | 198 | |
6ef67412 JH |
199 | ;; The (bounding maximum) length of an instruction address. |
200 | (define_attr "length_address" "" | |
201 | (cond [(eq_attr "type" "str,cld,other,multi,fxch") | |
202 | (const_int 0) | |
203 | (and (eq_attr "type" "call") | |
c7375e61 | 204 | (match_operand 0 "constant_call_address_operand" "")) |
6ef67412 JH |
205 | (const_int 0) |
206 | (and (eq_attr "type" "callv") | |
207 | (match_operand 1 "constant_call_address_operand" "")) | |
208 | (const_int 0) | |
209 | ] | |
210 | (symbol_ref "ix86_attr_length_address_default (insn)"))) | |
211 | ||
212 | ;; Set when length prefix is used. | |
213 | (define_attr "prefix_data16" "" | |
3d34cd91 JH |
214 | (if_then_else (ior (eq_attr "mode" "HI") |
215 | (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF"))) | |
6ef67412 JH |
216 | (const_int 1) |
217 | (const_int 0))) | |
218 | ||
219 | ;; Set when string REP prefix is used. | |
3d34cd91 JH |
220 | (define_attr "prefix_rep" "" |
221 | (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF")) | |
222 | (const_int 1) | |
223 | (const_int 0))) | |
6ef67412 JH |
224 | |
225 | ;; Set when 0f opcode prefix is used. | |
226 | (define_attr "prefix_0f" "" | |
9a5834ae ZW |
227 | (if_then_else |
228 | (eq_attr "type" | |
229 | "imovx,setcc,icmov, | |
230 | sselog,sseiadd,sseishft,sseimul, | |
231 | sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv, | |
232 | mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft") | |
6ef67412 JH |
233 | (const_int 1) |
234 | (const_int 0))) | |
235 | ||
236 | ;; Set when modrm byte is used. | |
237 | (define_attr "modrm" "" | |
238 | (cond [(eq_attr "type" "str,cld") | |
239 | (const_int 0) | |
3d34cd91 | 240 | (eq_attr "unit" "i387") |
6ef67412 | 241 | (const_int 0) |
e075ae69 RH |
242 | (and (eq_attr "type" "incdec") |
243 | (ior (match_operand:SI 1 "register_operand" "") | |
244 | (match_operand:HI 1 "register_operand" ""))) | |
6ef67412 | 245 | (const_int 0) |
e075ae69 RH |
246 | (and (eq_attr "type" "push") |
247 | (not (match_operand 1 "memory_operand" ""))) | |
6ef67412 | 248 | (const_int 0) |
e075ae69 RH |
249 | (and (eq_attr "type" "pop") |
250 | (not (match_operand 0 "memory_operand" ""))) | |
6ef67412 | 251 | (const_int 0) |
e075ae69 RH |
252 | (and (eq_attr "type" "imov") |
253 | (and (match_operand 0 "register_operand" "") | |
254 | (match_operand 1 "immediate_operand" ""))) | |
6ef67412 | 255 | (const_int 0) |
c7375e61 EB |
256 | (and (eq_attr "type" "call") |
257 | (match_operand 0 "constant_call_address_operand" "")) | |
258 | (const_int 0) | |
259 | (and (eq_attr "type" "callv") | |
260 | (match_operand 1 "constant_call_address_operand" "")) | |
261 | (const_int 0) | |
e075ae69 | 262 | ] |
6ef67412 JH |
263 | (const_int 1))) |
264 | ||
265 | ;; The (bounding maximum) length of an instruction in bytes. | |
22fb740d JH |
266 | ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want |
267 | ;; to split it and compute proper length as for other insns. | |
6ef67412 | 268 | (define_attr "length" "" |
22fb740d | 269 | (cond [(eq_attr "type" "other,multi,fistp") |
6ef67412 | 270 | (const_int 16) |
3d34cd91 JH |
271 | (eq_attr "unit" "i387") |
272 | (plus (const_int 2) | |
273 | (plus (attr "prefix_data16") | |
274 | (attr "length_address")))] | |
6ef67412 JH |
275 | (plus (plus (attr "modrm") |
276 | (plus (attr "prefix_0f") | |
3d34cd91 | 277 | (const_int 1))) |
6ef67412 JH |
278 | (plus (attr "prefix_rep") |
279 | (plus (attr "prefix_data16") | |
280 | (plus (attr "length_immediate") | |
281 | (attr "length_address"))))))) | |
e075ae69 RH |
282 | |
283 | ;; The `memory' attribute is `none' if no memory is referenced, `load' or | |
284 | ;; `store' if there is a simple memory reference therein, or `unknown' | |
285 | ;; if the instruction is complex. | |
286 | ||
287 | (define_attr "memory" "none,load,store,both,unknown" | |
7c7ef435 | 288 | (cond [(eq_attr "type" "other,multi,str") |
e075ae69 | 289 | (const_string "unknown") |
7c7ef435 | 290 | (eq_attr "type" "lea,fcmov,fpspc,cld") |
e075ae69 | 291 | (const_string "none") |
22fb740d JH |
292 | (eq_attr "type" "fistp") |
293 | (const_string "both") | |
e075ae69 RH |
294 | (eq_attr "type" "push") |
295 | (if_then_else (match_operand 1 "memory_operand" "") | |
296 | (const_string "both") | |
297 | (const_string "store")) | |
298 | (eq_attr "type" "pop,setcc") | |
299 | (if_then_else (match_operand 0 "memory_operand" "") | |
300 | (const_string "both") | |
301 | (const_string "load")) | |
3b4961bd | 302 | (eq_attr "type" "icmp,test,ssecmp,mmxcmp,fcmp") |
e075ae69 RH |
303 | (if_then_else (ior (match_operand 0 "memory_operand" "") |
304 | (match_operand 1 "memory_operand" "")) | |
305 | (const_string "load") | |
306 | (const_string "none")) | |
307 | (eq_attr "type" "ibr") | |
308 | (if_then_else (match_operand 0 "memory_operand" "") | |
309 | (const_string "load") | |
310 | (const_string "none")) | |
311 | (eq_attr "type" "call") | |
312 | (if_then_else (match_operand 0 "constant_call_address_operand" "") | |
313 | (const_string "none") | |
314 | (const_string "load")) | |
315 | (eq_attr "type" "callv") | |
316 | (if_then_else (match_operand 1 "constant_call_address_operand" "") | |
317 | (const_string "none") | |
318 | (const_string "load")) | |
319 | (and (eq_attr "type" "alu1,negnot") | |
a269a03c | 320 | (match_operand 1 "memory_operand" "")) |
e075ae69 RH |
321 | (const_string "both") |
322 | (and (match_operand 0 "memory_operand" "") | |
323 | (match_operand 1 "memory_operand" "")) | |
324 | (const_string "both") | |
325 | (match_operand 0 "memory_operand" "") | |
326 | (const_string "store") | |
327 | (match_operand 1 "memory_operand" "") | |
328 | (const_string "load") | |
9a5834ae ZW |
329 | (and (eq_attr "type" |
330 | "!alu1,negnot, | |
331 | imov,imovx,icmp,test, | |
332 | fmov,fcmp,fsgn, | |
333 | sse,ssemov,ssecmp,ssecvt, | |
334 | mmx,mmxmov,mmxcmp,mmxcvt") | |
e075ae69 RH |
335 | (match_operand 2 "memory_operand" "")) |
336 | (const_string "load") | |
337 | (and (eq_attr "type" "icmov") | |
338 | (match_operand 3 "memory_operand" "")) | |
339 | (const_string "load") | |
340 | ] | |
a269a03c JC |
341 | (const_string "none"))) |
342 | ||
e075ae69 RH |
343 | ;; Indicates if an instruction has both an immediate and a displacement. |
344 | ||
345 | (define_attr "imm_disp" "false,true,unknown" | |
346 | (cond [(eq_attr "type" "other,multi") | |
347 | (const_string "unknown") | |
6ef67412 | 348 | (and (eq_attr "type" "icmp,test,imov") |
e075ae69 RH |
349 | (and (match_operand 0 "memory_displacement_operand" "") |
350 | (match_operand 1 "immediate_operand" ""))) | |
351 | (const_string "true") | |
890d52e8 | 352 | (and (eq_attr "type" "alu,ishift,rotate,imul,idiv") |
e075ae69 RH |
353 | (and (match_operand 0 "memory_displacement_operand" "") |
354 | (match_operand 2 "immediate_operand" ""))) | |
355 | (const_string "true") | |
356 | ] | |
357 | (const_string "false"))) | |
358 | ||
359 | ;; Indicates if an FP operation has an integer source. | |
360 | ||
361 | (define_attr "fp_int_src" "false,true" | |
362 | (const_string "false")) | |
363 | ||
364 | ;; Describe a user's asm statement. | |
365 | (define_asm_attributes | |
366 | [(set_attr "length" "128") | |
367 | (set_attr "type" "multi")]) | |
368 | \f | |
af2728a4 JL |
369 | (include "pentium.md") |
370 | (include "ppro.md") | |
371 | (include "k6.md") | |
372 | (include "athlon.md") | |
309ada50 | 373 | \f |
e075ae69 | 374 | ;; Compare instructions. |
886c62d1 | 375 | |
e075ae69 | 376 | ;; All compare insns have expanders that save the operands away without |
c572e5ba | 377 | ;; actually generating RTL. The bCOND or sCOND (emitted immediately |
e075ae69 | 378 | ;; after the cmp) will actually emit the cmpM. |
886c62d1 | 379 | |
e075ae69 RH |
380 | (define_expand "cmpdi" |
381 | [(set (reg:CC 17) | |
b9b2c339 | 382 | (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") |
9b70259d | 383 | (match_operand:DI 1 "x86_64_general_operand" "")))] |
c572e5ba | 384 | "" |
c572e5ba | 385 | { |
b9b2c339 | 386 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
e075ae69 RH |
387 | operands[0] = force_reg (DImode, operands[0]); |
388 | ix86_compare_op0 = operands[0]; | |
389 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 390 | DONE; |
0f40f9f7 | 391 | }) |
c572e5ba | 392 | |
e075ae69 RH |
393 | (define_expand "cmpsi" |
394 | [(set (reg:CC 17) | |
395 | (compare:CC (match_operand:SI 0 "cmpsi_operand" "") | |
396 | (match_operand:SI 1 "general_operand" "")))] | |
c572e5ba | 397 | "" |
c572e5ba | 398 | { |
b9b2c339 | 399 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
e075ae69 RH |
400 | operands[0] = force_reg (SImode, operands[0]); |
401 | ix86_compare_op0 = operands[0]; | |
402 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 403 | DONE; |
0f40f9f7 | 404 | }) |
c572e5ba | 405 | |
e075ae69 RH |
406 | (define_expand "cmphi" |
407 | [(set (reg:CC 17) | |
b9b2c339 | 408 | (compare:CC (match_operand:HI 0 "nonimmediate_operand" "") |
e075ae69 | 409 | (match_operand:HI 1 "general_operand" "")))] |
c572e5ba | 410 | "" |
c572e5ba | 411 | { |
b9b2c339 | 412 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
e075ae69 RH |
413 | operands[0] = force_reg (HImode, operands[0]); |
414 | ix86_compare_op0 = operands[0]; | |
415 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 416 | DONE; |
0f40f9f7 | 417 | }) |
c572e5ba | 418 | |
e075ae69 RH |
419 | (define_expand "cmpqi" |
420 | [(set (reg:CC 17) | |
b9b2c339 | 421 | (compare:CC (match_operand:QI 0 "nonimmediate_operand" "") |
e075ae69 | 422 | (match_operand:QI 1 "general_operand" "")))] |
d9f32422 | 423 | "TARGET_QIMODE_MATH" |
c572e5ba | 424 | { |
b9b2c339 | 425 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
e075ae69 RH |
426 | operands[0] = force_reg (QImode, operands[0]); |
427 | ix86_compare_op0 = operands[0]; | |
428 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 429 | DONE; |
0f40f9f7 | 430 | }) |
886c62d1 | 431 | |
9b70259d JH |
432 | (define_insn "cmpdi_ccno_1_rex64" |
433 | [(set (reg 17) | |
434 | (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr") | |
435 | (match_operand:DI 1 "const0_operand" "n,n")))] | |
436 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
437 | "@ | |
0f40f9f7 ZW |
438 | test{q}\t{%0, %0|%0, %0} |
439 | cmp{q}\t{%1, %0|%0, %1}" | |
9b70259d JH |
440 | [(set_attr "type" "test,icmp") |
441 | (set_attr "length_immediate" "0,1") | |
442 | (set_attr "mode" "DI")]) | |
443 | ||
444 | (define_insn "*cmpdi_minus_1_rex64" | |
445 | [(set (reg 17) | |
446 | (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r") | |
447 | (match_operand:DI 1 "x86_64_general_operand" "re,mr")) | |
448 | (const_int 0)))] | |
1b0c37d7 | 449 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)" |
0f40f9f7 | 450 | "cmp{q}\t{%1, %0|%0, %1}" |
9b70259d JH |
451 | [(set_attr "type" "icmp") |
452 | (set_attr "mode" "DI")]) | |
453 | ||
454 | (define_expand "cmpdi_1_rex64" | |
455 | [(set (reg:CC 17) | |
456 | (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") | |
457 | (match_operand:DI 1 "general_operand" "")))] | |
1b0c37d7 | 458 | "TARGET_64BIT" |
9b70259d JH |
459 | "") |
460 | ||
461 | (define_insn "cmpdi_1_insn_rex64" | |
462 | [(set (reg 17) | |
463 | (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r") | |
464 | (match_operand:DI 1 "x86_64_general_operand" "re,mr")))] | |
465 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 466 | "cmp{q}\t{%1, %0|%0, %1}" |
9b70259d JH |
467 | [(set_attr "type" "icmp") |
468 | (set_attr "mode" "DI")]) | |
469 | ||
470 | ||
9076b9c1 JH |
471 | (define_insn "*cmpsi_ccno_1" |
472 | [(set (reg 17) | |
473 | (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr") | |
474 | (match_operand:SI 1 "const0_operand" "n,n")))] | |
475 | "ix86_match_ccmode (insn, CCNOmode)" | |
16189740 | 476 | "@ |
0f40f9f7 ZW |
477 | test{l}\t{%0, %0|%0, %0} |
478 | cmp{l}\t{%1, %0|%0, %1}" | |
6ef67412 JH |
479 | [(set_attr "type" "test,icmp") |
480 | (set_attr "length_immediate" "0,1") | |
481 | (set_attr "mode" "SI")]) | |
16189740 | 482 | |
9076b9c1 JH |
483 | (define_insn "*cmpsi_minus_1" |
484 | [(set (reg 17) | |
485 | (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r") | |
486 | (match_operand:SI 1 "general_operand" "ri,mr")) | |
487 | (const_int 0)))] | |
488 | "ix86_match_ccmode (insn, CCGOCmode)" | |
0f40f9f7 | 489 | "cmp{l}\t{%1, %0|%0, %1}" |
9076b9c1 | 490 | [(set_attr "type" "icmp") |
6ef67412 | 491 | (set_attr "mode" "SI")]) |
886c62d1 | 492 | |
9076b9c1 | 493 | (define_expand "cmpsi_1" |
e075ae69 RH |
494 | [(set (reg:CC 17) |
495 | (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r") | |
496 | (match_operand:SI 1 "general_operand" "ri,mr")))] | |
9076b9c1 JH |
497 | "" |
498 | "") | |
499 | ||
500 | (define_insn "*cmpsi_1_insn" | |
501 | [(set (reg 17) | |
502 | (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r") | |
503 | (match_operand:SI 1 "general_operand" "ri,mr")))] | |
504 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
505 | && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 506 | "cmp{l}\t{%1, %0|%0, %1}" |
6ef67412 JH |
507 | [(set_attr "type" "icmp") |
508 | (set_attr "mode" "SI")]) | |
886c62d1 | 509 | |
9076b9c1 | 510 | (define_insn "*cmphi_ccno_1" |
16189740 RH |
511 | [(set (reg 17) |
512 | (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr") | |
513 | (match_operand:HI 1 "const0_operand" "n,n")))] | |
514 | "ix86_match_ccmode (insn, CCNOmode)" | |
e075ae69 | 515 | "@ |
0f40f9f7 ZW |
516 | test{w}\t{%0, %0|%0, %0} |
517 | cmp{w}\t{%1, %0|%0, %1}" | |
6ef67412 JH |
518 | [(set_attr "type" "test,icmp") |
519 | (set_attr "length_immediate" "0,1") | |
520 | (set_attr "mode" "HI")]) | |
886c62d1 | 521 | |
9076b9c1 JH |
522 | (define_insn "*cmphi_minus_1" |
523 | [(set (reg 17) | |
524 | (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r") | |
525 | (match_operand:HI 1 "general_operand" "ri,mr")) | |
526 | (const_int 0)))] | |
527 | "ix86_match_ccmode (insn, CCGOCmode)" | |
0f40f9f7 | 528 | "cmp{w}\t{%1, %0|%0, %1}" |
6ef67412 JH |
529 | [(set_attr "type" "icmp") |
530 | (set_attr "mode" "HI")]) | |
e075ae69 | 531 | |
9076b9c1 JH |
532 | (define_insn "*cmphi_1" |
533 | [(set (reg 17) | |
534 | (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r") | |
535 | (match_operand:HI 1 "general_operand" "ri,mr")))] | |
536 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
537 | && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 538 | "cmp{w}\t{%1, %0|%0, %1}" |
9076b9c1 JH |
539 | [(set_attr "type" "icmp") |
540 | (set_attr "mode" "HI")]) | |
16189740 RH |
541 | |
542 | (define_insn "*cmpqi_ccno_1" | |
9076b9c1 JH |
543 | [(set (reg 17) |
544 | (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq") | |
545 | (match_operand:QI 1 "const0_operand" "n,n")))] | |
546 | "ix86_match_ccmode (insn, CCNOmode)" | |
e075ae69 | 547 | "@ |
0f40f9f7 ZW |
548 | test{b}\t{%0, %0|%0, %0} |
549 | cmp{b}\t{$0, %0|%0, 0}" | |
6ef67412 JH |
550 | [(set_attr "type" "test,icmp") |
551 | (set_attr "length_immediate" "0,1") | |
552 | (set_attr "mode" "QI")]) | |
886c62d1 | 553 | |
16189740 | 554 | (define_insn "*cmpqi_1" |
9076b9c1 JH |
555 | [(set (reg 17) |
556 | (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q") | |
557 | (match_operand:QI 1 "general_operand" "qi,mq")))] | |
558 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
559 | && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 560 | "cmp{b}\t{%1, %0|%0, %1}" |
6ef67412 JH |
561 | [(set_attr "type" "icmp") |
562 | (set_attr "mode" "QI")]) | |
e075ae69 | 563 | |
9076b9c1 JH |
564 | (define_insn "*cmpqi_minus_1" |
565 | [(set (reg 17) | |
d70401eb JJ |
566 | (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q") |
567 | (match_operand:QI 1 "general_operand" "qi,mq")) | |
9076b9c1 JH |
568 | (const_int 0)))] |
569 | "ix86_match_ccmode (insn, CCGOCmode)" | |
0f40f9f7 | 570 | "cmp{b}\t{%1, %0|%0, %1}" |
9076b9c1 JH |
571 | [(set_attr "type" "icmp") |
572 | (set_attr "mode" "QI")]) | |
573 | ||
e075ae69 | 574 | (define_insn "*cmpqi_ext_1" |
9076b9c1 JH |
575 | [(set (reg 17) |
576 | (compare | |
d2836273 | 577 | (match_operand:QI 0 "general_operand" "Qm") |
e075ae69 RH |
578 | (subreg:QI |
579 | (zero_extract:SI | |
d2836273 | 580 | (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
581 | (const_int 8) |
582 | (const_int 8)) 0)))] | |
d2836273 | 583 | "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" |
0f40f9f7 | 584 | "cmp{b}\t{%h1, %0|%0, %h1}" |
d2836273 JH |
585 | [(set_attr "type" "icmp") |
586 | (set_attr "mode" "QI")]) | |
587 | ||
588 | (define_insn "*cmpqi_ext_1_rex64" | |
589 | [(set (reg 17) | |
590 | (compare | |
3522082b | 591 | (match_operand:QI 0 "register_operand" "Q") |
d2836273 JH |
592 | (subreg:QI |
593 | (zero_extract:SI | |
594 | (match_operand 1 "ext_register_operand" "Q") | |
595 | (const_int 8) | |
596 | (const_int 8)) 0)))] | |
597 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 598 | "cmp{b}\t{%h1, %0|%0, %h1}" |
6ef67412 JH |
599 | [(set_attr "type" "icmp") |
600 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
601 | |
602 | (define_insn "*cmpqi_ext_2" | |
16189740 RH |
603 | [(set (reg 17) |
604 | (compare | |
e075ae69 RH |
605 | (subreg:QI |
606 | (zero_extract:SI | |
d2836273 | 607 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
608 | (const_int 8) |
609 | (const_int 8)) 0) | |
610 | (match_operand:QI 1 "const0_operand" "n")))] | |
16189740 | 611 | "ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 612 | "test{b}\t%h0, %h0" |
6ef67412 JH |
613 | [(set_attr "type" "test") |
614 | (set_attr "length_immediate" "0") | |
615 | (set_attr "mode" "QI")]) | |
e075ae69 | 616 | |
9076b9c1 | 617 | (define_expand "cmpqi_ext_3" |
e075ae69 RH |
618 | [(set (reg:CC 17) |
619 | (compare:CC | |
620 | (subreg:QI | |
621 | (zero_extract:SI | |
d2836273 | 622 | (match_operand 0 "ext_register_operand" "") |
e075ae69 RH |
623 | (const_int 8) |
624 | (const_int 8)) 0) | |
d2836273 | 625 | (match_operand:QI 1 "general_operand" "")))] |
e075ae69 | 626 | "" |
9076b9c1 JH |
627 | "") |
628 | ||
629 | (define_insn "cmpqi_ext_3_insn" | |
630 | [(set (reg 17) | |
631 | (compare | |
632 | (subreg:QI | |
633 | (zero_extract:SI | |
d2836273 | 634 | (match_operand 0 "ext_register_operand" "Q") |
9076b9c1 JH |
635 | (const_int 8) |
636 | (const_int 8)) 0) | |
d2836273 JH |
637 | (match_operand:QI 1 "general_operand" "Qmn")))] |
638 | "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 639 | "cmp{b}\t{%1, %h0|%h0, %1}" |
d2836273 JH |
640 | [(set_attr "type" "icmp") |
641 | (set_attr "mode" "QI")]) | |
642 | ||
643 | (define_insn "cmpqi_ext_3_insn_rex64" | |
644 | [(set (reg 17) | |
645 | (compare | |
646 | (subreg:QI | |
647 | (zero_extract:SI | |
648 | (match_operand 0 "ext_register_operand" "Q") | |
649 | (const_int 8) | |
650 | (const_int 8)) 0) | |
651 | (match_operand:QI 1 "nonmemory_operand" "Qn")))] | |
652 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)" | |
0f40f9f7 | 653 | "cmp{b}\t{%1, %h0|%h0, %1}" |
6ef67412 JH |
654 | [(set_attr "type" "icmp") |
655 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
656 | |
657 | (define_insn "*cmpqi_ext_4" | |
9076b9c1 JH |
658 | [(set (reg 17) |
659 | (compare | |
e075ae69 RH |
660 | (subreg:QI |
661 | (zero_extract:SI | |
d2836273 | 662 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
663 | (const_int 8) |
664 | (const_int 8)) 0) | |
665 | (subreg:QI | |
666 | (zero_extract:SI | |
d2836273 | 667 | (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
668 | (const_int 8) |
669 | (const_int 8)) 0)))] | |
9076b9c1 | 670 | "ix86_match_ccmode (insn, CCmode)" |
0f40f9f7 | 671 | "cmp{b}\t{%h1, %h0|%h0, %h1}" |
6ef67412 JH |
672 | [(set_attr "type" "icmp") |
673 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
674 | |
675 | ;; These implement float point compares. | |
676 | ;; %%% See if we can get away with VOIDmode operands on the actual insns, | |
677 | ;; which would allow mix and match FP modes on the compares. Which is what | |
678 | ;; the old patterns did, but with many more of them. | |
c572e5ba | 679 | |
e075ae69 RH |
680 | (define_expand "cmpxf" |
681 | [(set (reg:CC 17) | |
682 | (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "") | |
683 | (match_operand:XF 1 "cmp_fp_expander_operand" "")))] | |
1b0c37d7 | 684 | "!TARGET_64BIT && TARGET_80387" |
c572e5ba | 685 | { |
e075ae69 RH |
686 | ix86_compare_op0 = operands[0]; |
687 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 688 | DONE; |
0f40f9f7 | 689 | }) |
4fb21e90 | 690 | |
2b589241 JH |
691 | (define_expand "cmptf" |
692 | [(set (reg:CC 17) | |
693 | (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "") | |
694 | (match_operand:TF 1 "cmp_fp_expander_operand" "")))] | |
695 | "TARGET_80387" | |
2b589241 JH |
696 | { |
697 | ix86_compare_op0 = operands[0]; | |
698 | ix86_compare_op1 = operands[1]; | |
699 | DONE; | |
0f40f9f7 | 700 | }) |
2b589241 | 701 | |
e075ae69 RH |
702 | (define_expand "cmpdf" |
703 | [(set (reg:CC 17) | |
704 | (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "") | |
705 | (match_operand:DF 1 "cmp_fp_expander_operand" "")))] | |
0644b628 | 706 | "TARGET_80387 || TARGET_SSE2" |
4fb21e90 | 707 | { |
e075ae69 RH |
708 | ix86_compare_op0 = operands[0]; |
709 | ix86_compare_op1 = operands[1]; | |
4fb21e90 | 710 | DONE; |
0f40f9f7 | 711 | }) |
886c62d1 | 712 | |
e075ae69 RH |
713 | (define_expand "cmpsf" |
714 | [(set (reg:CC 17) | |
715 | (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "") | |
716 | (match_operand:SF 1 "cmp_fp_expander_operand" "")))] | |
0644b628 | 717 | "TARGET_80387 || TARGET_SSE" |
c572e5ba | 718 | { |
e075ae69 RH |
719 | ix86_compare_op0 = operands[0]; |
720 | ix86_compare_op1 = operands[1]; | |
c572e5ba | 721 | DONE; |
0f40f9f7 | 722 | }) |
c572e5ba | 723 | |
e075ae69 RH |
724 | ;; FP compares, step 1: |
725 | ;; Set the FP condition codes. | |
726 | ;; | |
727 | ;; CCFPmode compare with exceptions | |
728 | ;; CCFPUmode compare with no exceptions | |
fe4435d9 | 729 | |
e075ae69 RH |
730 | ;; %%% It is an unfortunate fact that ftst has no non-popping variant, |
731 | ;; and that fp moves clobber the condition codes, and that there is | |
732 | ;; currently no way to describe this fact to reg-stack. So there are | |
733 | ;; no splitters yet for this. | |
c572e5ba | 734 | |
e075ae69 RH |
735 | ;; %%% YIKES! This scheme does not retain a strong connection between |
736 | ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not | |
737 | ;; work! Only allow tos/mem with tos in op 0. | |
738 | ;; | |
739 | ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps | |
740 | ;; things aren't as bad as they sound... | |
886c62d1 | 741 | |
e075ae69 RH |
742 | (define_insn "*cmpfp_0" |
743 | [(set (match_operand:HI 0 "register_operand" "=a") | |
744 | (unspec:HI | |
745 | [(compare:CCFP (match_operand 1 "register_operand" "f") | |
8ee41eaf RH |
746 | (match_operand 2 "const0_operand" "X"))] |
747 | UNSPEC_FNSTSW))] | |
e075ae69 RH |
748 | "TARGET_80387 |
749 | && FLOAT_MODE_P (GET_MODE (operands[1])) | |
750 | && GET_MODE (operands[1]) == GET_MODE (operands[2])" | |
c572e5ba | 751 | { |
e075ae69 | 752 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) |
0f40f9f7 | 753 | return "ftst\;fnstsw\t%0\;fstp\t%y0"; |
e075ae69 | 754 | else |
0f40f9f7 ZW |
755 | return "ftst\;fnstsw\t%0"; |
756 | } | |
6ef67412 JH |
757 | [(set_attr "type" "multi") |
758 | (set_attr "mode" "unknownfp")]) | |
c572e5ba | 759 | |
e075ae69 RH |
760 | ;; We may not use "#" to split and emit these, since the REG_DEAD notes |
761 | ;; used to manage the reg stack popping would not be preserved. | |
886c62d1 | 762 | |
e075ae69 RH |
763 | (define_insn "*cmpfp_2_sf" |
764 | [(set (reg:CCFP 18) | |
765 | (compare:CCFP | |
766 | (match_operand:SF 0 "register_operand" "f") | |
767 | (match_operand:SF 1 "nonimmediate_operand" "fm")))] | |
cac58785 | 768 | "TARGET_80387" |
e075ae69 | 769 | "* return output_fp_compare (insn, operands, 0, 0);" |
6ef67412 JH |
770 | [(set_attr "type" "fcmp") |
771 | (set_attr "mode" "SF")]) | |
4fb21e90 | 772 | |
6343a50e | 773 | (define_insn "*cmpfp_2_sf_1" |
e075ae69 RH |
774 | [(set (match_operand:HI 0 "register_operand" "=a") |
775 | (unspec:HI | |
776 | [(compare:CCFP | |
777 | (match_operand:SF 1 "register_operand" "f") | |
8ee41eaf RH |
778 | (match_operand:SF 2 "nonimmediate_operand" "fm"))] |
779 | UNSPEC_FNSTSW))] | |
4fb21e90 | 780 | "TARGET_80387" |
e075ae69 | 781 | "* return output_fp_compare (insn, operands, 2, 0);" |
6ef67412 JH |
782 | [(set_attr "type" "fcmp") |
783 | (set_attr "mode" "SF")]) | |
e075ae69 RH |
784 | |
785 | (define_insn "*cmpfp_2_df" | |
786 | [(set (reg:CCFP 18) | |
787 | (compare:CCFP | |
788 | (match_operand:DF 0 "register_operand" "f") | |
789 | (match_operand:DF 1 "nonimmediate_operand" "fm")))] | |
926b3fae | 790 | "TARGET_80387" |
e075ae69 | 791 | "* return output_fp_compare (insn, operands, 0, 0);" |
6ef67412 JH |
792 | [(set_attr "type" "fcmp") |
793 | (set_attr "mode" "DF")]) | |
926b3fae | 794 | |
6343a50e | 795 | (define_insn "*cmpfp_2_df_1" |
e075ae69 RH |
796 | [(set (match_operand:HI 0 "register_operand" "=a") |
797 | (unspec:HI | |
798 | [(compare:CCFP | |
799 | (match_operand:DF 1 "register_operand" "f") | |
8ee41eaf RH |
800 | (match_operand:DF 2 "nonimmediate_operand" "fm"))] |
801 | UNSPEC_FNSTSW))] | |
4fb21e90 | 802 | "TARGET_80387" |
e075ae69 | 803 | "* return output_fp_compare (insn, operands, 2, 0);" |
6ef67412 JH |
804 | [(set_attr "type" "multi") |
805 | (set_attr "mode" "DF")]) | |
e075ae69 RH |
806 | |
807 | (define_insn "*cmpfp_2_xf" | |
808 | [(set (reg:CCFP 18) | |
809 | (compare:CCFP | |
810 | (match_operand:XF 0 "register_operand" "f") | |
811 | (match_operand:XF 1 "register_operand" "f")))] | |
1b0c37d7 | 812 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 813 | "* return output_fp_compare (insn, operands, 0, 0);" |
6ef67412 JH |
814 | [(set_attr "type" "fcmp") |
815 | (set_attr "mode" "XF")]) | |
9ec36da5 | 816 | |
2b589241 JH |
817 | (define_insn "*cmpfp_2_tf" |
818 | [(set (reg:CCFP 18) | |
819 | (compare:CCFP | |
820 | (match_operand:TF 0 "register_operand" "f") | |
821 | (match_operand:TF 1 "register_operand" "f")))] | |
822 | "TARGET_80387" | |
823 | "* return output_fp_compare (insn, operands, 0, 0);" | |
824 | [(set_attr "type" "fcmp") | |
825 | (set_attr "mode" "XF")]) | |
826 | ||
6343a50e | 827 | (define_insn "*cmpfp_2_xf_1" |
e075ae69 RH |
828 | [(set (match_operand:HI 0 "register_operand" "=a") |
829 | (unspec:HI | |
830 | [(compare:CCFP | |
831 | (match_operand:XF 1 "register_operand" "f") | |
8ee41eaf RH |
832 | (match_operand:XF 2 "register_operand" "f"))] |
833 | UNSPEC_FNSTSW))] | |
1b0c37d7 | 834 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 835 | "* return output_fp_compare (insn, operands, 2, 0);" |
6ef67412 JH |
836 | [(set_attr "type" "multi") |
837 | (set_attr "mode" "XF")]) | |
e075ae69 | 838 | |
2b589241 JH |
839 | (define_insn "*cmpfp_2_tf_1" |
840 | [(set (match_operand:HI 0 "register_operand" "=a") | |
841 | (unspec:HI | |
842 | [(compare:CCFP | |
843 | (match_operand:TF 1 "register_operand" "f") | |
8ee41eaf RH |
844 | (match_operand:TF 2 "register_operand" "f"))] |
845 | UNSPEC_FNSTSW))] | |
2b589241 JH |
846 | "TARGET_80387" |
847 | "* return output_fp_compare (insn, operands, 2, 0);" | |
848 | [(set_attr "type" "multi") | |
849 | (set_attr "mode" "XF")]) | |
850 | ||
e075ae69 RH |
851 | (define_insn "*cmpfp_2u" |
852 | [(set (reg:CCFPU 18) | |
853 | (compare:CCFPU | |
854 | (match_operand 0 "register_operand" "f") | |
855 | (match_operand 1 "register_operand" "f")))] | |
856 | "TARGET_80387 | |
857 | && FLOAT_MODE_P (GET_MODE (operands[0])) | |
858 | && GET_MODE (operands[0]) == GET_MODE (operands[1])" | |
859 | "* return output_fp_compare (insn, operands, 0, 1);" | |
6ef67412 JH |
860 | [(set_attr "type" "fcmp") |
861 | (set_attr "mode" "unknownfp")]) | |
4fb21e90 | 862 | |
6343a50e | 863 | (define_insn "*cmpfp_2u_1" |
e075ae69 RH |
864 | [(set (match_operand:HI 0 "register_operand" "=a") |
865 | (unspec:HI | |
866 | [(compare:CCFPU | |
867 | (match_operand 1 "register_operand" "f") | |
8ee41eaf RH |
868 | (match_operand 2 "register_operand" "f"))] |
869 | UNSPEC_FNSTSW))] | |
08a7baac | 870 | "TARGET_80387 |
e075ae69 RH |
871 | && FLOAT_MODE_P (GET_MODE (operands[1])) |
872 | && GET_MODE (operands[1]) == GET_MODE (operands[2])" | |
873 | "* return output_fp_compare (insn, operands, 2, 1);" | |
6ef67412 JH |
874 | [(set_attr "type" "multi") |
875 | (set_attr "mode" "unknownfp")]) | |
08a7baac | 876 | |
e075ae69 RH |
877 | ;; Patterns to match the SImode-in-memory ficom instructions. |
878 | ;; | |
879 | ;; %%% Play games with accepting gp registers, as otherwise we have to | |
880 | ;; force them to memory during rtl generation, which is no good. We | |
881 | ;; can get rid of this once we teach reload to do memory input reloads | |
882 | ;; via pushes. | |
883 | ||
6343a50e | 884 | (define_insn "*ficom_1" |
e075ae69 RH |
885 | [(set (reg:CCFP 18) |
886 | (compare:CCFP | |
887 | (match_operand 0 "register_operand" "f,f") | |
888 | (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))] | |
889 | "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0])) | |
890 | && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])" | |
891 | "#") | |
08a7baac | 892 | |
e075ae69 RH |
893 | ;; Split the not-really-implemented gp register case into a |
894 | ;; push-op-pop sequence. | |
895 | ;; | |
896 | ;; %%% This is most efficient, but am I gonna get in trouble | |
897 | ;; for separating cc0_setter and cc0_user? | |
2bb7a0f5 | 898 | |
e075ae69 RH |
899 | (define_split |
900 | [(set (reg:CCFP 18) | |
901 | (compare:CCFP | |
902 | (match_operand:SF 0 "register_operand" "") | |
903 | (float (match_operand:SI 1 "register_operand" ""))))] | |
904 | "0 && TARGET_80387 && reload_completed" | |
905 | [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1)) | |
906 | (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2))) | |
907 | (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) | |
908 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
909 | "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx); | |
910 | operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);") | |
911 | ||
912 | ;; FP compares, step 2 | |
913 | ;; Move the fpsw to ax. | |
914 | ||
915 | (define_insn "x86_fnstsw_1" | |
916 | [(set (match_operand:HI 0 "register_operand" "=a") | |
8ee41eaf | 917 | (unspec:HI [(reg 18)] UNSPEC_FNSTSW))] |
2ae0f82c | 918 | "TARGET_80387" |
0f40f9f7 | 919 | "fnstsw\t%0" |
e075ae69 | 920 | [(set_attr "length" "2") |
6ef67412 | 921 | (set_attr "mode" "SI") |
3d34cd91 | 922 | (set_attr "unit" "i387") |
e075ae69 RH |
923 | (set_attr "ppro_uops" "few")]) |
924 | ||
925 | ;; FP compares, step 3 | |
926 | ;; Get ax into flags, general case. | |
927 | ||
928 | (define_insn "x86_sahf_1" | |
929 | [(set (reg:CC 17) | |
8ee41eaf | 930 | (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))] |
1e07edd3 | 931 | "!TARGET_64BIT" |
e075ae69 RH |
932 | "sahf" |
933 | [(set_attr "length" "1") | |
0b5107cf | 934 | (set_attr "athlon_decode" "vector") |
6ef67412 | 935 | (set_attr "mode" "SI") |
e075ae69 RH |
936 | (set_attr "ppro_uops" "one")]) |
937 | ||
938 | ;; Pentium Pro can do steps 1 through 3 in one go. | |
939 | ||
940 | (define_insn "*cmpfp_i" | |
941 | [(set (reg:CCFP 17) | |
942 | (compare:CCFP (match_operand 0 "register_operand" "f") | |
943 | (match_operand 1 "register_operand" "f")))] | |
944 | "TARGET_80387 && TARGET_CMOVE | |
0644b628 | 945 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[0])) |
e075ae69 RH |
946 | && FLOAT_MODE_P (GET_MODE (operands[0])) |
947 | && GET_MODE (operands[0]) == GET_MODE (operands[0])" | |
948 | "* return output_fp_compare (insn, operands, 1, 0);" | |
309ada50 | 949 | [(set_attr "type" "fcmp") |
6ef67412 | 950 | (set_attr "mode" "unknownfp") |
309ada50 | 951 | (set_attr "athlon_decode" "vector")]) |
e075ae69 | 952 | |
0644b628 JH |
953 | (define_insn "*cmpfp_i_sse" |
954 | [(set (reg:CCFP 17) | |
955 | (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f") | |
956 | (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] | |
957 | "TARGET_80387 | |
958 | && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) | |
959 | && GET_MODE (operands[0]) == GET_MODE (operands[0])" | |
960 | "* return output_fp_compare (insn, operands, 1, 0);" | |
3d34cd91 | 961 | [(set_attr "type" "fcmp,ssecmp") |
0644b628 JH |
962 | (set_attr "mode" "unknownfp") |
963 | (set_attr "athlon_decode" "vector")]) | |
964 | ||
965 | (define_insn "*cmpfp_i_sse_only" | |
966 | [(set (reg:CCFP 17) | |
967 | (compare:CCFP (match_operand 0 "register_operand" "x") | |
968 | (match_operand 1 "nonimmediate_operand" "xm")))] | |
969 | "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) | |
970 | && GET_MODE (operands[0]) == GET_MODE (operands[0])" | |
971 | "* return output_fp_compare (insn, operands, 1, 0);" | |
3d34cd91 | 972 | [(set_attr "type" "ssecmp") |
0644b628 JH |
973 | (set_attr "mode" "unknownfp") |
974 | (set_attr "athlon_decode" "vector")]) | |
975 | ||
e075ae69 RH |
976 | (define_insn "*cmpfp_iu" |
977 | [(set (reg:CCFPU 17) | |
978 | (compare:CCFPU (match_operand 0 "register_operand" "f") | |
979 | (match_operand 1 "register_operand" "f")))] | |
980 | "TARGET_80387 && TARGET_CMOVE | |
0644b628 | 981 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[0])) |
e075ae69 RH |
982 | && FLOAT_MODE_P (GET_MODE (operands[0])) |
983 | && GET_MODE (operands[0]) == GET_MODE (operands[1])" | |
984 | "* return output_fp_compare (insn, operands, 1, 1);" | |
309ada50 | 985 | [(set_attr "type" "fcmp") |
6ef67412 | 986 | (set_attr "mode" "unknownfp") |
309ada50 | 987 | (set_attr "athlon_decode" "vector")]) |
0644b628 JH |
988 | |
989 | (define_insn "*cmpfp_iu_sse" | |
990 | [(set (reg:CCFPU 17) | |
991 | (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f") | |
992 | (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] | |
993 | "TARGET_80387 | |
994 | && SSE_FLOAT_MODE_P (GET_MODE (operands[0])) | |
995 | && GET_MODE (operands[0]) == GET_MODE (operands[1])" | |
996 | "* return output_fp_compare (insn, operands, 1, 1);" | |
3d34cd91 | 997 | [(set_attr "type" "fcmp,ssecmp") |
0644b628 JH |
998 | (set_attr "mode" "unknownfp") |
999 | (set_attr "athlon_decode" "vector")]) | |
1000 | ||
1001 | (define_insn "*cmpfp_iu_sse_only" | |
1002 | [(set (reg:CCFPU 17) | |
1003 | (compare:CCFPU (match_operand 0 "register_operand" "x") | |
1004 | (match_operand 1 "nonimmediate_operand" "xm")))] | |
1005 | "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) | |
1006 | && GET_MODE (operands[0]) == GET_MODE (operands[1])" | |
1007 | "* return output_fp_compare (insn, operands, 1, 1);" | |
3d34cd91 | 1008 | [(set_attr "type" "ssecmp") |
0644b628 JH |
1009 | (set_attr "mode" "unknownfp") |
1010 | (set_attr "athlon_decode" "vector")]) | |
e075ae69 RH |
1011 | \f |
1012 | ;; Move instructions. | |
2ae0f82c | 1013 | |
e075ae69 | 1014 | ;; General case of fullword move. |
886c62d1 | 1015 | |
e075ae69 RH |
1016 | (define_expand "movsi" |
1017 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
1018 | (match_operand:SI 1 "general_operand" ""))] | |
1019 | "" | |
1020 | "ix86_expand_move (SImode, operands); DONE;") | |
08a7baac | 1021 | |
e075ae69 RH |
1022 | ;; Push/pop instructions. They are separate since autoinc/dec is not a |
1023 | ;; general_operand. | |
1024 | ;; | |
1025 | ;; %%% We don't use a post-inc memory reference because x86 is not a | |
1026 | ;; general AUTO_INC_DEC host, which impacts how it is treated in flow. | |
1027 | ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC | |
1028 | ;; targets without our curiosities, and it is just as easy to represent | |
1029 | ;; this differently. | |
886c62d1 | 1030 | |
a4414093 | 1031 | (define_insn "*pushsi2" |
e075ae69 | 1032 | [(set (match_operand:SI 0 "push_operand" "=<") |
2c5a510c | 1033 | (match_operand:SI 1 "general_no_elim_operand" "ri*m"))] |
0ec259ed | 1034 | "!TARGET_64BIT" |
0f40f9f7 | 1035 | "push{l}\t%1" |
6ef67412 JH |
1036 | [(set_attr "type" "push") |
1037 | (set_attr "mode" "SI")]) | |
4fb21e90 | 1038 | |
0ec259ed JH |
1039 | ;; For 64BIT abi we always round up to 8 bytes. |
1040 | (define_insn "*pushsi2_rex64" | |
1041 | [(set (match_operand:SI 0 "push_operand" "=X") | |
1042 | (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))] | |
1043 | "TARGET_64BIT" | |
0f40f9f7 | 1044 | "push{q}\t%q1" |
0ec259ed JH |
1045 | [(set_attr "type" "push") |
1046 | (set_attr "mode" "SI")]) | |
1047 | ||
bdeb029c JH |
1048 | (define_insn "*pushsi2_prologue" |
1049 | [(set (match_operand:SI 0 "push_operand" "=<") | |
1050 | (match_operand:SI 1 "general_no_elim_operand" "ri*m")) | |
f2042df3 | 1051 | (clobber (mem:BLK (scratch)))] |
0ec259ed | 1052 | "!TARGET_64BIT" |
0f40f9f7 | 1053 | "push{l}\t%1" |
6ef67412 JH |
1054 | [(set_attr "type" "push") |
1055 | (set_attr "mode" "SI")]) | |
bdeb029c JH |
1056 | |
1057 | (define_insn "*popsi1_epilogue" | |
1058 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m") | |
1059 | (mem:SI (reg:SI 7))) | |
1060 | (set (reg:SI 7) | |
1061 | (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 | 1062 | (clobber (mem:BLK (scratch)))] |
1e07edd3 | 1063 | "!TARGET_64BIT" |
0f40f9f7 | 1064 | "pop{l}\t%0" |
6ef67412 JH |
1065 | [(set_attr "type" "pop") |
1066 | (set_attr "mode" "SI")]) | |
bdeb029c | 1067 | |
e075ae69 RH |
1068 | (define_insn "popsi1" |
1069 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m") | |
1070 | (mem:SI (reg:SI 7))) | |
1071 | (set (reg:SI 7) | |
1072 | (plus:SI (reg:SI 7) (const_int 4)))] | |
1e07edd3 | 1073 | "!TARGET_64BIT" |
0f40f9f7 | 1074 | "pop{l}\t%0" |
6ef67412 JH |
1075 | [(set_attr "type" "pop") |
1076 | (set_attr "mode" "SI")]) | |
c572e5ba | 1077 | |
a8bac9ab | 1078 | (define_insn "*movsi_xor" |
591702de JH |
1079 | [(set (match_operand:SI 0 "register_operand" "=r") |
1080 | (match_operand:SI 1 "const0_operand" "i")) | |
e075ae69 | 1081 | (clobber (reg:CC 17))] |
591702de | 1082 | "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" |
0f40f9f7 | 1083 | "xor{l}\t{%0, %0|%0, %0}" |
591702de | 1084 | [(set_attr "type" "alu1") |
6ef67412 JH |
1085 | (set_attr "mode" "SI") |
1086 | (set_attr "length_immediate" "0")]) | |
591702de JH |
1087 | |
1088 | (define_insn "*movsi_or" | |
1089 | [(set (match_operand:SI 0 "register_operand" "=r") | |
1090 | (match_operand:SI 1 "immediate_operand" "i")) | |
1091 | (clobber (reg:CC 17))] | |
1092 | "reload_completed && GET_CODE (operands[1]) == CONST_INT | |
1093 | && INTVAL (operands[1]) == -1 | |
1094 | && (TARGET_PENTIUM || optimize_size)" | |
c572e5ba | 1095 | { |
591702de | 1096 | operands[1] = constm1_rtx; |
0f40f9f7 ZW |
1097 | return "or{l}\t{%1, %0|%0, %1}"; |
1098 | } | |
591702de | 1099 | [(set_attr "type" "alu1") |
6ef67412 JH |
1100 | (set_attr "mode" "SI") |
1101 | (set_attr "length_immediate" "1")]) | |
e075ae69 | 1102 | |
de80110b JH |
1103 | ; The first alternative is used only to compute proper length of instruction. |
1104 | ; Reload's algorithm does not take into account the cost of spill instructions | |
1105 | ; needed to free register in given class, so avoid it from choosing the first | |
1106 | ; alternative when eax is not available. | |
1107 | ||
591702de | 1108 | (define_insn "*movsi_1" |
de80110b | 1109 | [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y") |
e5a20888 | 1110 | (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))] |
e075ae69 | 1111 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
886c62d1 | 1112 | { |
e075ae69 | 1113 | switch (get_attr_type (insn)) |
886c62d1 | 1114 | { |
5f90a099 | 1115 | case TYPE_SSEMOV: |
141e454b | 1116 | if (get_attr_mode (insn) == TImode) |
0f40f9f7 ZW |
1117 | return "movdqa\t{%1, %0|%0, %1}"; |
1118 | return "movd\t{%1, %0|%0, %1}"; | |
141e454b | 1119 | |
5f90a099 | 1120 | case TYPE_MMXMOV: |
e5a20888 JJ |
1121 | if (get_attr_mode (insn) == DImode) |
1122 | return "movq\t{%1, %0|%0, %1}"; | |
0f40f9f7 | 1123 | return "movd\t{%1, %0|%0, %1}"; |
915119a5 | 1124 | |
e075ae69 | 1125 | case TYPE_LEA: |
0f40f9f7 | 1126 | return "lea{l}\t{%1, %0|%0, %1}"; |
915119a5 | 1127 | |
e075ae69 | 1128 | default: |
57d47446 | 1129 | if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1])) |
e075ae69 | 1130 | abort(); |
0f40f9f7 | 1131 | return "mov{l}\t{%1, %0|%0, %1}"; |
886c62d1 | 1132 | } |
0f40f9f7 | 1133 | } |
e075ae69 | 1134 | [(set (attr "type") |
e5a20888 | 1135 | (cond [(eq_attr "alternative" "4,5,6") |
3d34cd91 | 1136 | (const_string "mmxmov") |
e5a20888 | 1137 | (eq_attr "alternative" "7,8,9") |
3d34cd91 | 1138 | (const_string "ssemov") |
915119a5 | 1139 | (and (ne (symbol_ref "flag_pic") (const_int 0)) |
e075ae69 RH |
1140 | (match_operand:SI 1 "symbolic_operand" "")) |
1141 | (const_string "lea") | |
1142 | ] | |
6ef67412 | 1143 | (const_string "imov"))) |
e5a20888 JJ |
1144 | (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*") |
1145 | (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")]) | |
e075ae69 | 1146 | |
0ec259ed JH |
1147 | ;; Stores and loads of ax to arbitary constant address. |
1148 | ;; We fake an second form of instruction to force reload to load address | |
1149 | ;; into register when rax is not available | |
1150 | (define_insn "*movabssi_1_rex64" | |
1151 | [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) | |
1152 | (match_operand:SI 1 "nonmemory_operand" "a,er,i"))] | |
1153 | "TARGET_64BIT" | |
1154 | "@ | |
0f40f9f7 ZW |
1155 | movabs{l}\t{%1, %P0|%P0, %1} |
1156 | mov{l}\t{%1, %a0|%a0, %1} | |
1157 | movabs{l}\t{%1, %a0|%a0, %1}" | |
0ec259ed JH |
1158 | [(set_attr "type" "imov") |
1159 | (set_attr "modrm" "0,*,*") | |
1160 | (set_attr "length_address" "8,0,0") | |
1161 | (set_attr "length_immediate" "0,*,*") | |
1162 | (set_attr "memory" "store") | |
1163 | (set_attr "mode" "SI")]) | |
1164 | ||
1165 | (define_insn "*movabssi_2_rex64" | |
1166 | [(set (match_operand:SI 0 "register_operand" "=a,r") | |
1167 | (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] | |
1168 | "TARGET_64BIT" | |
1169 | "@ | |
0f40f9f7 ZW |
1170 | movabs{l}\t{%P1, %0|%0, %P1} |
1171 | mov{l}\t{%a1, %0|%0, %a1}" | |
0ec259ed JH |
1172 | [(set_attr "type" "imov") |
1173 | (set_attr "modrm" "0,*") | |
1174 | (set_attr "length_address" "8,0") | |
1175 | (set_attr "length_immediate" "0") | |
1176 | (set_attr "memory" "load") | |
1177 | (set_attr "mode" "SI")]) | |
1178 | ||
e075ae69 RH |
1179 | (define_insn "*swapsi" |
1180 | [(set (match_operand:SI 0 "register_operand" "+r") | |
1181 | (match_operand:SI 1 "register_operand" "+r")) | |
1182 | (set (match_dup 1) | |
1183 | (match_dup 0))] | |
2bb7a0f5 | 1184 | "" |
0f40f9f7 | 1185 | "xchg{l}\t%1, %0" |
e075ae69 RH |
1186 | [(set_attr "type" "imov") |
1187 | (set_attr "pent_pair" "np") | |
0b5107cf | 1188 | (set_attr "athlon_decode" "vector") |
6ef67412 JH |
1189 | (set_attr "mode" "SI") |
1190 | (set_attr "modrm" "0") | |
e075ae69 | 1191 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 1192 | |
e075ae69 RH |
1193 | (define_expand "movhi" |
1194 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1195 | (match_operand:HI 1 "general_operand" ""))] | |
ca097615 | 1196 | "" |
e075ae69 | 1197 | "ix86_expand_move (HImode, operands); DONE;") |
2f2a49e8 | 1198 | |
a4414093 | 1199 | (define_insn "*pushhi2" |
e075ae69 | 1200 | [(set (match_operand:HI 0 "push_operand" "=<,<") |
2c5a510c | 1201 | (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))] |
1e07edd3 | 1202 | "!TARGET_64BIT" |
e075ae69 | 1203 | "@ |
0f40f9f7 ZW |
1204 | push{w}\t{|WORD PTR }%1 |
1205 | push{w}\t%1" | |
6ef67412 JH |
1206 | [(set_attr "type" "push") |
1207 | (set_attr "mode" "HI")]) | |
e075ae69 | 1208 | |
b3298882 JH |
1209 | ;; For 64BIT abi we always round up to 8 bytes. |
1210 | (define_insn "*pushhi2_rex64" | |
1211 | [(set (match_operand:HI 0 "push_operand" "=X") | |
1212 | (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))] | |
1213 | "TARGET_64BIT" | |
0f40f9f7 | 1214 | "push{q}\t%q1" |
b3298882 JH |
1215 | [(set_attr "type" "push") |
1216 | (set_attr "mode" "QI")]) | |
1217 | ||
de80110b JH |
1218 | ; The first alternative is used only to compute proper length of instruction. |
1219 | ; Reload's algorithm does not take into account the cost of spill instructions | |
1220 | ; needed to free register in given class, so avoid it from choosing the first | |
1221 | ; alternative when eax is not available. | |
1222 | ||
e075ae69 | 1223 | (define_insn "*movhi_1" |
de80110b | 1224 | [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m") |
6ef67412 | 1225 | (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))] |
e075ae69 | 1226 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
886c62d1 | 1227 | { |
e075ae69 | 1228 | switch (get_attr_type (insn)) |
886c62d1 | 1229 | { |
e075ae69 RH |
1230 | case TYPE_IMOVX: |
1231 | /* movzwl is faster than movw on p2 due to partial word stalls, | |
1232 | though not as fast as an aligned movl. */ | |
0f40f9f7 | 1233 | return "movz{wl|x}\t{%1, %k0|%k0, %1}"; |
e075ae69 | 1234 | default: |
6ef67412 | 1235 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 1236 | return "mov{l}\t{%k1, %k0|%k0, %k1}"; |
e075ae69 | 1237 | else |
0f40f9f7 | 1238 | return "mov{w}\t{%1, %0|%0, %1}"; |
886c62d1 | 1239 | } |
0f40f9f7 | 1240 | } |
e075ae69 | 1241 | [(set (attr "type") |
6ef67412 | 1242 | (cond [(and (eq_attr "alternative" "0,1") |
0b5107cf JH |
1243 | (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") |
1244 | (const_int 0)) | |
1245 | (eq (symbol_ref "TARGET_HIMODE_MATH") | |
1246 | (const_int 0)))) | |
369e59b1 | 1247 | (const_string "imov") |
6ef67412 | 1248 | (and (eq_attr "alternative" "2,3,4") |
2247f6ed | 1249 | (match_operand:HI 1 "aligned_operand" "")) |
e075ae69 RH |
1250 | (const_string "imov") |
1251 | (and (ne (symbol_ref "TARGET_MOVX") | |
1252 | (const_int 0)) | |
6ef67412 | 1253 | (eq_attr "alternative" "0,1,3,4")) |
e075ae69 RH |
1254 | (const_string "imovx") |
1255 | ] | |
1256 | (const_string "imov"))) | |
6ef67412 | 1257 | (set (attr "mode") |
e075ae69 | 1258 | (cond [(eq_attr "type" "imovx") |
6ef67412 JH |
1259 | (const_string "SI") |
1260 | (and (eq_attr "alternative" "2,3,4") | |
369e59b1 | 1261 | (match_operand:HI 1 "aligned_operand" "")) |
6ef67412 JH |
1262 | (const_string "SI") |
1263 | (and (eq_attr "alternative" "0,1") | |
0b5107cf JH |
1264 | (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") |
1265 | (const_int 0)) | |
1266 | (eq (symbol_ref "TARGET_HIMODE_MATH") | |
1267 | (const_int 0)))) | |
6ef67412 | 1268 | (const_string "SI") |
e075ae69 | 1269 | ] |
6ef67412 JH |
1270 | (const_string "HI"))) |
1271 | (set_attr "modrm" "0,*,*,0,*,*")]) | |
e075ae69 | 1272 | |
0ec259ed JH |
1273 | ;; Stores and loads of ax to arbitary constant address. |
1274 | ;; We fake an second form of instruction to force reload to load address | |
1275 | ;; into register when rax is not available | |
1276 | (define_insn "*movabshi_1_rex64" | |
1277 | [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) | |
1278 | (match_operand:HI 1 "nonmemory_operand" "a,er,i"))] | |
1279 | "TARGET_64BIT" | |
1280 | "@ | |
0f40f9f7 ZW |
1281 | movabs{w}\t{%1, %P0|%P0, %1} |
1282 | mov{w}\t{%1, %a0|%a0, %1} | |
1283 | movabs{w}\t{%1, %a0|%a0, %1}" | |
0ec259ed JH |
1284 | [(set_attr "type" "imov") |
1285 | (set_attr "modrm" "0,*,*") | |
1286 | (set_attr "length_address" "8,0,0") | |
1287 | (set_attr "length_immediate" "0,*,*") | |
1288 | (set_attr "memory" "store") | |
1289 | (set_attr "mode" "HI")]) | |
1290 | ||
1291 | (define_insn "*movabshi_2_rex64" | |
1292 | [(set (match_operand:HI 0 "register_operand" "=a,r") | |
1293 | (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] | |
1294 | "TARGET_64BIT" | |
1295 | "@ | |
0f40f9f7 ZW |
1296 | movabs{w}\t{%P1, %0|%0, %P1} |
1297 | mov{w}\t{%a1, %0|%0, %a1}" | |
0ec259ed JH |
1298 | [(set_attr "type" "imov") |
1299 | (set_attr "modrm" "0,*") | |
1300 | (set_attr "length_address" "8,0") | |
1301 | (set_attr "length_immediate" "0") | |
1302 | (set_attr "memory" "load") | |
1303 | (set_attr "mode" "HI")]) | |
1304 | ||
e075ae69 RH |
1305 | (define_insn "*swaphi_1" |
1306 | [(set (match_operand:HI 0 "register_operand" "+r") | |
1307 | (match_operand:HI 1 "register_operand" "+r")) | |
1308 | (set (match_dup 1) | |
1309 | (match_dup 0))] | |
1310 | "TARGET_PARTIAL_REG_STALL" | |
0f40f9f7 | 1311 | "xchg{w}\t%1, %0" |
e075ae69 RH |
1312 | [(set_attr "type" "imov") |
1313 | (set_attr "pent_pair" "np") | |
6ef67412 JH |
1314 | (set_attr "mode" "HI") |
1315 | (set_attr "modrm" "0") | |
e075ae69 RH |
1316 | (set_attr "ppro_uops" "few")]) |
1317 | ||
1318 | (define_insn "*swaphi_2" | |
1319 | [(set (match_operand:HI 0 "register_operand" "+r") | |
1320 | (match_operand:HI 1 "register_operand" "+r")) | |
1321 | (set (match_dup 1) | |
1322 | (match_dup 0))] | |
1323 | "! TARGET_PARTIAL_REG_STALL" | |
0f40f9f7 | 1324 | "xchg{l}\t%k1, %k0" |
e075ae69 | 1325 | [(set_attr "type" "imov") |
e075ae69 | 1326 | (set_attr "pent_pair" "np") |
6ef67412 JH |
1327 | (set_attr "mode" "SI") |
1328 | (set_attr "modrm" "0") | |
e075ae69 | 1329 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 1330 | |
2f2a49e8 | 1331 | (define_expand "movstricthi" |
e075ae69 | 1332 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "")) |
2f2a49e8 | 1333 | (match_operand:HI 1 "general_operand" ""))] |
b9b2c339 | 1334 | "! TARGET_PARTIAL_REG_STALL || optimize_size" |
2f2a49e8 MM |
1335 | { |
1336 | /* Don't generate memory->memory moves, go through a register */ | |
e075ae69 RH |
1337 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
1338 | operands[1] = force_reg (HImode, operands[1]); | |
0f40f9f7 | 1339 | }) |
2f2a49e8 | 1340 | |
e075ae69 | 1341 | (define_insn "*movstricthi_1" |
fc524c1c | 1342 | [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r")) |
e075ae69 | 1343 | (match_operand:HI 1 "general_operand" "rn,m"))] |
b9b2c339 | 1344 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) |
e075ae69 | 1345 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" |
0f40f9f7 | 1346 | "mov{w}\t{%1, %0|%0, %1}" |
6ef67412 JH |
1347 | [(set_attr "type" "imov") |
1348 | (set_attr "mode" "HI")]) | |
1349 | ||
1350 | (define_insn "*movstricthi_xor" | |
208b0ab1 | 1351 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) |
6ef67412 JH |
1352 | (match_operand:HI 1 "const0_operand" "i")) |
1353 | (clobber (reg:CC 17))] | |
b9b2c339 JH |
1354 | "reload_completed |
1355 | && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)" | |
0f40f9f7 | 1356 | "xor{w}\t{%0, %0|%0, %0}" |
6ef67412 JH |
1357 | [(set_attr "type" "alu1") |
1358 | (set_attr "mode" "HI") | |
1359 | (set_attr "length_immediate" "0")]) | |
886c62d1 | 1360 | |
2f2a49e8 | 1361 | (define_expand "movqi" |
4cbfbb1b | 1362 | [(set (match_operand:QI 0 "nonimmediate_operand" "") |
2f2a49e8 MM |
1363 | (match_operand:QI 1 "general_operand" ""))] |
1364 | "" | |
e075ae69 RH |
1365 | "ix86_expand_move (QImode, operands); DONE;") |
1366 | ||
7dd4b4a3 JH |
1367 | ;; emit_push_insn when it calls move_by_pieces requires an insn to |
1368 | ;; "push a byte". But actually we use pushw, which has the effect | |
1369 | ;; of rounding the amount pushed up to a halfword. | |
1370 | ||
1371 | (define_insn "*pushqi2" | |
1372 | [(set (match_operand:QI 0 "push_operand" "=X,X") | |
1373 | (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))] | |
1374 | "!TARGET_64BIT" | |
1375 | "@ | |
0f40f9f7 ZW |
1376 | push{w}\t{|word ptr }%1 |
1377 | push{w}\t%w1" | |
7dd4b4a3 JH |
1378 | [(set_attr "type" "push") |
1379 | (set_attr "mode" "HI")]) | |
1380 | ||
b3298882 JH |
1381 | ;; For 64BIT abi we always round up to 8 bytes. |
1382 | (define_insn "*pushqi2_rex64" | |
1383 | [(set (match_operand:QI 0 "push_operand" "=X") | |
5f90a099 | 1384 | (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))] |
b3298882 | 1385 | "TARGET_64BIT" |
0f40f9f7 | 1386 | "push{q}\t%q1" |
b3298882 JH |
1387 | [(set_attr "type" "push") |
1388 | (set_attr "mode" "QI")]) | |
1389 | ||
0b5107cf JH |
1390 | ;; Situation is quite tricky about when to choose full sized (SImode) move |
1391 | ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for | |
1392 | ;; partial register dependency machines (such as AMD Athlon), where QImode | |
1393 | ;; moves issue extra dependency and for partial register stalls machines | |
1394 | ;; that don't use QImode patterns (and QImode move cause stall on the next | |
1395 | ;; instruction). | |
1396 | ;; | |
1397 | ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial | |
1398 | ;; register stall machines with, where we use QImode instructions, since | |
1399 | ;; partial register stall can be caused there. Then we use movzx. | |
e075ae69 | 1400 | (define_insn "*movqi_1" |
0b5107cf JH |
1401 | [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m") |
1402 | (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))] | |
e075ae69 | 1403 | "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" |
886c62d1 | 1404 | { |
e075ae69 | 1405 | switch (get_attr_type (insn)) |
b76c90cf | 1406 | { |
e075ae69 | 1407 | case TYPE_IMOVX: |
1a06f5fe | 1408 | if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM) |
e075ae69 | 1409 | abort (); |
0f40f9f7 | 1410 | return "movz{bl|x}\t{%1, %k0|%k0, %1}"; |
e075ae69 | 1411 | default: |
6ef67412 | 1412 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 1413 | return "mov{l}\t{%k1, %k0|%k0, %k1}"; |
b76c90cf | 1414 | else |
0f40f9f7 | 1415 | return "mov{b}\t{%1, %0|%0, %1}"; |
b76c90cf | 1416 | } |
0f40f9f7 | 1417 | } |
e075ae69 | 1418 | [(set (attr "type") |
0b5107cf JH |
1419 | (cond [(and (eq_attr "alternative" "3") |
1420 | (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL") | |
1421 | (const_int 0)) | |
1422 | (eq (symbol_ref "TARGET_QIMODE_MATH") | |
1423 | (const_int 0)))) | |
1424 | (const_string "imov") | |
1425 | (eq_attr "alternative" "3,5") | |
e075ae69 RH |
1426 | (const_string "imovx") |
1427 | (and (ne (symbol_ref "TARGET_MOVX") | |
1428 | (const_int 0)) | |
0b5107cf | 1429 | (eq_attr "alternative" "2")) |
e075ae69 RH |
1430 | (const_string "imovx") |
1431 | ] | |
1432 | (const_string "imov"))) | |
6ef67412 JH |
1433 | (set (attr "mode") |
1434 | (cond [(eq_attr "alternative" "3,4,5") | |
1435 | (const_string "SI") | |
1436 | (eq_attr "alternative" "6") | |
1437 | (const_string "QI") | |
1438 | (eq_attr "type" "imovx") | |
1439 | (const_string "SI") | |
0b5107cf | 1440 | (and (eq_attr "type" "imov") |
6ef67412 | 1441 | (and (eq_attr "alternative" "0,1,2") |
0b5107cf JH |
1442 | (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY") |
1443 | (const_int 0)))) | |
6ef67412 | 1444 | (const_string "SI") |
0b5107cf JH |
1445 | ;; Avoid partial register stalls when not using QImode arithmetic |
1446 | (and (eq_attr "type" "imov") | |
6ef67412 | 1447 | (and (eq_attr "alternative" "0,1,2") |
0b5107cf JH |
1448 | (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL") |
1449 | (const_int 0)) | |
1450 | (eq (symbol_ref "TARGET_QIMODE_MATH") | |
1451 | (const_int 0))))) | |
6ef67412 JH |
1452 | (const_string "SI") |
1453 | ] | |
1454 | (const_string "QI")))]) | |
e075ae69 RH |
1455 | |
1456 | (define_expand "reload_outqi" | |
1457 | [(parallel [(match_operand:QI 0 "" "=m") | |
1458 | (match_operand:QI 1 "register_operand" "r") | |
1459 | (match_operand:QI 2 "register_operand" "=&q")])] | |
1460 | "" | |
e075ae69 RH |
1461 | { |
1462 | rtx op0, op1, op2; | |
1463 | op0 = operands[0]; op1 = operands[1]; op2 = operands[2]; | |
886c62d1 | 1464 | |
e075ae69 RH |
1465 | if (reg_overlap_mentioned_p (op2, op0)) |
1466 | abort (); | |
1467 | if (! q_regs_operand (op1, QImode)) | |
1468 | { | |
1469 | emit_insn (gen_movqi (op2, op1)); | |
1470 | op1 = op2; | |
1471 | } | |
1472 | emit_insn (gen_movqi (op0, op1)); | |
1473 | DONE; | |
0f40f9f7 | 1474 | }) |
886c62d1 | 1475 | |
e075ae69 RH |
1476 | (define_insn "*swapqi" |
1477 | [(set (match_operand:QI 0 "register_operand" "+r") | |
1478 | (match_operand:QI 1 "register_operand" "+r")) | |
1479 | (set (match_dup 1) | |
1480 | (match_dup 0))] | |
1481 | "" | |
0f40f9f7 | 1482 | "xchg{b}\t%1, %0" |
e075ae69 RH |
1483 | [(set_attr "type" "imov") |
1484 | (set_attr "pent_pair" "np") | |
6ef67412 JH |
1485 | (set_attr "mode" "QI") |
1486 | (set_attr "modrm" "0") | |
e075ae69 | 1487 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 1488 | |
2f2a49e8 | 1489 | (define_expand "movstrictqi" |
4cbfbb1b | 1490 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) |
2f2a49e8 | 1491 | (match_operand:QI 1 "general_operand" ""))] |
e075ae69 | 1492 | "! TARGET_PARTIAL_REG_STALL" |
2f2a49e8 | 1493 | { |
e03f5d43 | 1494 | /* Don't generate memory->memory moves, go through a register. */ |
e075ae69 RH |
1495 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
1496 | operands[1] = force_reg (QImode, operands[1]); | |
0f40f9f7 | 1497 | }) |
2f2a49e8 | 1498 | |
e075ae69 | 1499 | (define_insn "*movstrictqi_1" |
2ae0f82c | 1500 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) |
c0f06344 | 1501 | (match_operand:QI 1 "general_operand" "*qn,m"))] |
e075ae69 RH |
1502 | "! TARGET_PARTIAL_REG_STALL |
1503 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
0f40f9f7 | 1504 | "mov{b}\t{%1, %0|%0, %1}" |
6ef67412 JH |
1505 | [(set_attr "type" "imov") |
1506 | (set_attr "mode" "QI")]) | |
1507 | ||
1508 | (define_insn "*movstrictqi_xor" | |
5e6d6bf0 | 1509 | [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q")) |
6ef67412 JH |
1510 | (match_operand:QI 1 "const0_operand" "i")) |
1511 | (clobber (reg:CC 17))] | |
1512 | "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" | |
0f40f9f7 | 1513 | "xor{b}\t{%0, %0|%0, %0}" |
6ef67412 JH |
1514 | [(set_attr "type" "alu1") |
1515 | (set_attr "mode" "QI") | |
1516 | (set_attr "length_immediate" "0")]) | |
e075ae69 RH |
1517 | |
1518 | (define_insn "*movsi_extv_1" | |
d2836273 | 1519 | [(set (match_operand:SI 0 "register_operand" "=R") |
3522082b | 1520 | (sign_extract:SI (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
1521 | (const_int 8) |
1522 | (const_int 8)))] | |
1523 | "" | |
0f40f9f7 | 1524 | "movs{bl|x}\t{%h1, %0|%0, %h1}" |
6ef67412 JH |
1525 | [(set_attr "type" "imovx") |
1526 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
1527 | |
1528 | (define_insn "*movhi_extv_1" | |
d2836273 | 1529 | [(set (match_operand:HI 0 "register_operand" "=R") |
3522082b | 1530 | (sign_extract:HI (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
1531 | (const_int 8) |
1532 | (const_int 8)))] | |
1533 | "" | |
0f40f9f7 | 1534 | "movs{bl|x}\t{%h1, %k0|%k0, %h1}" |
6ef67412 JH |
1535 | [(set_attr "type" "imovx") |
1536 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
1537 | |
1538 | (define_insn "*movqi_extv_1" | |
0ec259ed | 1539 | [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r") |
3522082b | 1540 | (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") |
e075ae69 RH |
1541 | (const_int 8) |
1542 | (const_int 8)))] | |
0ec259ed | 1543 | "!TARGET_64BIT" |
886c62d1 | 1544 | { |
e075ae69 | 1545 | switch (get_attr_type (insn)) |
886c62d1 | 1546 | { |
e075ae69 | 1547 | case TYPE_IMOVX: |
0f40f9f7 | 1548 | return "movs{bl|x}\t{%h1, %k0|%k0, %h1}"; |
e075ae69 | 1549 | default: |
0f40f9f7 | 1550 | return "mov{b}\t{%h1, %0|%0, %h1}"; |
886c62d1 | 1551 | } |
0f40f9f7 | 1552 | } |
e075ae69 RH |
1553 | [(set (attr "type") |
1554 | (if_then_else (and (match_operand:QI 0 "register_operand" "") | |
1555 | (ior (not (match_operand:QI 0 "q_regs_operand" "")) | |
1556 | (ne (symbol_ref "TARGET_MOVX") | |
1557 | (const_int 0)))) | |
1558 | (const_string "imovx") | |
6ef67412 JH |
1559 | (const_string "imov"))) |
1560 | (set (attr "mode") | |
1561 | (if_then_else (eq_attr "type" "imovx") | |
1562 | (const_string "SI") | |
1563 | (const_string "QI")))]) | |
e075ae69 | 1564 | |
0ec259ed JH |
1565 | (define_insn "*movqi_extv_1_rex64" |
1566 | [(set (match_operand:QI 0 "register_operand" "=Q,?R") | |
3522082b | 1567 | (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q") |
0ec259ed JH |
1568 | (const_int 8) |
1569 | (const_int 8)))] | |
1570 | "TARGET_64BIT" | |
0ec259ed JH |
1571 | { |
1572 | switch (get_attr_type (insn)) | |
1573 | { | |
1574 | case TYPE_IMOVX: | |
0f40f9f7 | 1575 | return "movs{bl|x}\t{%h1, %k0|%k0, %h1}"; |
0ec259ed | 1576 | default: |
0f40f9f7 | 1577 | return "mov{b}\t{%h1, %0|%0, %h1}"; |
0ec259ed | 1578 | } |
0f40f9f7 | 1579 | } |
0ec259ed JH |
1580 | [(set (attr "type") |
1581 | (if_then_else (and (match_operand:QI 0 "register_operand" "") | |
1582 | (ior (not (match_operand:QI 0 "q_regs_operand" "")) | |
1583 | (ne (symbol_ref "TARGET_MOVX") | |
1584 | (const_int 0)))) | |
1585 | (const_string "imovx") | |
1586 | (const_string "imov"))) | |
1587 | (set (attr "mode") | |
1588 | (if_then_else (eq_attr "type" "imovx") | |
1589 | (const_string "SI") | |
1590 | (const_string "QI")))]) | |
1591 | ||
1592 | ;; Stores and loads of ax to arbitary constant address. | |
1593 | ;; We fake an second form of instruction to force reload to load address | |
1594 | ;; into register when rax is not available | |
1595 | (define_insn "*movabsqi_1_rex64" | |
1596 | [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) | |
1597 | (match_operand:QI 1 "nonmemory_operand" "a,er,i"))] | |
1598 | "TARGET_64BIT" | |
1599 | "@ | |
5e2ce672 JH |
1600 | movabs{b}\t{%1, %P0|%P0, %1} |
1601 | mov{b}\t{%1, %a0|%a0, %1} | |
1602 | movabs{b}\t{%1, %a0|%a0, %1}" | |
0ec259ed JH |
1603 | [(set_attr "type" "imov") |
1604 | (set_attr "modrm" "0,*,*") | |
1605 | (set_attr "length_address" "8,0,0") | |
1606 | (set_attr "length_immediate" "0,*,*") | |
1607 | (set_attr "memory" "store") | |
1608 | (set_attr "mode" "QI")]) | |
1609 | ||
1610 | (define_insn "*movabsqi_2_rex64" | |
1611 | [(set (match_operand:QI 0 "register_operand" "=a,r") | |
1612 | (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] | |
1613 | "TARGET_64BIT" | |
1614 | "@ | |
5e2ce672 JH |
1615 | movabs{b}\t{%P1, %0|%0, %P1} |
1616 | mov{b}\t{%a1, %0|%0, %a1}" | |
0ec259ed JH |
1617 | [(set_attr "type" "imov") |
1618 | (set_attr "modrm" "0,*") | |
1619 | (set_attr "length_address" "8,0") | |
1620 | (set_attr "length_immediate" "0") | |
1621 | (set_attr "memory" "load") | |
1622 | (set_attr "mode" "QI")]) | |
1623 | ||
e075ae69 | 1624 | (define_insn "*movsi_extzv_1" |
d2836273 JH |
1625 | [(set (match_operand:SI 0 "register_operand" "=R") |
1626 | (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") | |
e075ae69 RH |
1627 | (const_int 8) |
1628 | (const_int 8)))] | |
1629 | "" | |
0f40f9f7 | 1630 | "movz{bl|x}\t{%h1, %0|%0, %h1}" |
6ef67412 JH |
1631 | [(set_attr "type" "imovx") |
1632 | (set_attr "mode" "SI")]) | |
886c62d1 | 1633 | |
d2836273 JH |
1634 | (define_insn "*movqi_extzv_2" |
1635 | [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R") | |
1636 | (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q") | |
e075ae69 RH |
1637 | (const_int 8) |
1638 | (const_int 8)) 0))] | |
d2836273 | 1639 | "!TARGET_64BIT" |
f31fce3f | 1640 | { |
e075ae69 | 1641 | switch (get_attr_type (insn)) |
f31fce3f | 1642 | { |
e075ae69 | 1643 | case TYPE_IMOVX: |
0f40f9f7 | 1644 | return "movz{bl|x}\t{%h1, %k0|%k0, %h1}"; |
e075ae69 | 1645 | default: |
0f40f9f7 | 1646 | return "mov{b}\t{%h1, %0|%0, %h1}"; |
e075ae69 | 1647 | } |
0f40f9f7 | 1648 | } |
e075ae69 RH |
1649 | [(set (attr "type") |
1650 | (if_then_else (and (match_operand:QI 0 "register_operand" "") | |
1651 | (ior (not (match_operand:QI 0 "q_regs_operand" "")) | |
1652 | (ne (symbol_ref "TARGET_MOVX") | |
1653 | (const_int 0)))) | |
1654 | (const_string "imovx") | |
6ef67412 JH |
1655 | (const_string "imov"))) |
1656 | (set (attr "mode") | |
1657 | (if_then_else (eq_attr "type" "imovx") | |
1658 | (const_string "SI") | |
1659 | (const_string "QI")))]) | |
e075ae69 | 1660 | |
d2836273 JH |
1661 | (define_insn "*movqi_extzv_2_rex64" |
1662 | [(set (match_operand:QI 0 "register_operand" "=Q,?R") | |
1663 | (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q") | |
1664 | (const_int 8) | |
1665 | (const_int 8)) 0))] | |
1666 | "TARGET_64BIT" | |
d2836273 JH |
1667 | { |
1668 | switch (get_attr_type (insn)) | |
1669 | { | |
1670 | case TYPE_IMOVX: | |
0f40f9f7 | 1671 | return "movz{bl|x}\t{%h1, %k0|%k0, %h1}"; |
d2836273 | 1672 | default: |
0f40f9f7 | 1673 | return "mov{b}\t{%h1, %0|%0, %h1}"; |
d2836273 | 1674 | } |
0f40f9f7 | 1675 | } |
d2836273 JH |
1676 | [(set (attr "type") |
1677 | (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" "")) | |
1678 | (ne (symbol_ref "TARGET_MOVX") | |
1679 | (const_int 0))) | |
1680 | (const_string "imovx") | |
1681 | (const_string "imov"))) | |
1682 | (set (attr "mode") | |
1683 | (if_then_else (eq_attr "type" "imovx") | |
1684 | (const_string "SI") | |
1685 | (const_string "QI")))]) | |
1686 | ||
7a2e09f4 | 1687 | (define_insn "movsi_insv_1" |
d2836273 | 1688 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") |
e075ae69 RH |
1689 | (const_int 8) |
1690 | (const_int 8)) | |
f47c8646 | 1691 | (match_operand:SI 1 "general_operand" "Qmn"))] |
d2836273 | 1692 | "!TARGET_64BIT" |
0f40f9f7 | 1693 | "mov{b}\t{%b1, %h0|%h0, %b1}" |
d2836273 JH |
1694 | [(set_attr "type" "imov") |
1695 | (set_attr "mode" "QI")]) | |
1696 | ||
1697 | (define_insn "*movsi_insv_1_rex64" | |
1698 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") | |
1699 | (const_int 8) | |
1700 | (const_int 8)) | |
f47c8646 | 1701 | (match_operand:SI 1 "nonmemory_operand" "Qn"))] |
d2836273 | 1702 | "TARGET_64BIT" |
0f40f9f7 | 1703 | "mov{b}\t{%b1, %h0|%h0, %b1}" |
6ef67412 JH |
1704 | [(set_attr "type" "imov") |
1705 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
1706 | |
1707 | (define_insn "*movqi_insv_2" | |
d2836273 | 1708 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q") |
e075ae69 RH |
1709 | (const_int 8) |
1710 | (const_int 8)) | |
3522082b | 1711 | (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q") |
e075ae69 RH |
1712 | (const_int 8)) |
1713 | (const_int 255)))] | |
1714 | "" | |
0f40f9f7 | 1715 | "mov{b}\t{%h1, %h0|%h0, %h1}" |
6ef67412 JH |
1716 | [(set_attr "type" "imov") |
1717 | (set_attr "mode" "QI")]) | |
f31fce3f | 1718 | |
e075ae69 | 1719 | (define_expand "movdi" |
4cbfbb1b | 1720 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
e075ae69 RH |
1721 | (match_operand:DI 1 "general_operand" ""))] |
1722 | "" | |
1723 | "ix86_expand_move (DImode, operands); DONE;") | |
f31fce3f | 1724 | |
e075ae69 RH |
1725 | (define_insn "*pushdi" |
1726 | [(set (match_operand:DI 0 "push_operand" "=<") | |
2c5a510c | 1727 | (match_operand:DI 1 "general_no_elim_operand" "riF*m"))] |
1e07edd3 | 1728 | "!TARGET_64BIT" |
e075ae69 | 1729 | "#") |
f31fce3f | 1730 | |
0ec259ed JH |
1731 | (define_insn "pushdi2_rex64" |
1732 | [(set (match_operand:DI 0 "push_operand" "=<,!<") | |
1733 | (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))] | |
1734 | "TARGET_64BIT" | |
1735 | "@ | |
0f40f9f7 | 1736 | push{q}\t%1 |
0ec259ed JH |
1737 | #" |
1738 | [(set_attr "type" "push,multi") | |
1739 | (set_attr "mode" "DI")]) | |
1740 | ||
1741 | ;; Convert impossible pushes of immediate to existing instructions. | |
f5143c46 | 1742 | ;; First try to get scratch register and go through it. In case this |
0ec259ed JH |
1743 | ;; fails, push sign extended lower part first and then overwrite |
1744 | ;; upper part by 32bit move. | |
1745 | (define_peephole2 | |
1746 | [(match_scratch:DI 2 "r") | |
1747 | (set (match_operand:DI 0 "push_operand" "") | |
1748 | (match_operand:DI 1 "immediate_operand" ""))] | |
1749 | "TARGET_64BIT && !symbolic_operand (operands[1], DImode) | |
1750 | && !x86_64_immediate_operand (operands[1], DImode)" | |
1751 | [(set (match_dup 2) (match_dup 1)) | |
1752 | (set (match_dup 0) (match_dup 2))] | |
1753 | "") | |
1754 | ||
1755 | ;; We need to define this as both peepholer and splitter for case | |
1756 | ;; peephole2 pass is not run. | |
1757 | (define_peephole2 | |
1758 | [(set (match_operand:DI 0 "push_operand" "") | |
1759 | (match_operand:DI 1 "immediate_operand" ""))] | |
1760 | "TARGET_64BIT && !symbolic_operand (operands[1], DImode) | |
1761 | && !x86_64_immediate_operand (operands[1], DImode) && 1" | |
1762 | [(set (match_dup 0) (match_dup 1)) | |
1763 | (set (match_dup 2) (match_dup 3))] | |
1764 | "split_di (operands + 1, 1, operands + 2, operands + 3); | |
1765 | operands[1] = gen_lowpart (DImode, operands[2]); | |
1766 | operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, | |
1767 | GEN_INT (4))); | |
1768 | ") | |
1769 | ||
1770 | (define_split | |
1771 | [(set (match_operand:DI 0 "push_operand" "") | |
1772 | (match_operand:DI 1 "immediate_operand" ""))] | |
1773 | "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2)) | |
1774 | && !symbolic_operand (operands[1], DImode) | |
1775 | && !x86_64_immediate_operand (operands[1], DImode)" | |
1776 | [(set (match_dup 0) (match_dup 1)) | |
1777 | (set (match_dup 2) (match_dup 3))] | |
1778 | "split_di (operands + 1, 1, operands + 2, operands + 3); | |
1779 | operands[1] = gen_lowpart (DImode, operands[2]); | |
1780 | operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx, | |
1781 | GEN_INT (4))); | |
1782 | ") | |
1783 | ||
1784 | (define_insn "*pushdi2_prologue_rex64" | |
1785 | [(set (match_operand:DI 0 "push_operand" "=<") | |
1786 | (match_operand:DI 1 "general_no_elim_operand" "re*m")) | |
f2042df3 | 1787 | (clobber (mem:BLK (scratch)))] |
0ec259ed | 1788 | "TARGET_64BIT" |
0f40f9f7 | 1789 | "push{q}\t%1" |
0ec259ed JH |
1790 | [(set_attr "type" "push") |
1791 | (set_attr "mode" "DI")]) | |
1792 | ||
1793 | (define_insn "*popdi1_epilogue_rex64" | |
1794 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m") | |
1795 | (mem:DI (reg:DI 7))) | |
1796 | (set (reg:DI 7) | |
1797 | (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 | 1798 | (clobber (mem:BLK (scratch)))] |
0ec259ed | 1799 | "TARGET_64BIT" |
0f40f9f7 | 1800 | "pop{q}\t%0" |
0ec259ed JH |
1801 | [(set_attr "type" "pop") |
1802 | (set_attr "mode" "DI")]) | |
1803 | ||
1804 | (define_insn "popdi1" | |
1805 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m") | |
1806 | (mem:DI (reg:DI 7))) | |
1807 | (set (reg:DI 7) | |
1808 | (plus:DI (reg:DI 7) (const_int 8)))] | |
1809 | "TARGET_64BIT" | |
0f40f9f7 | 1810 | "pop{q}\t%0" |
0ec259ed JH |
1811 | [(set_attr "type" "pop") |
1812 | (set_attr "mode" "DI")]) | |
1813 | ||
1814 | (define_insn "*movdi_xor_rex64" | |
1815 | [(set (match_operand:DI 0 "register_operand" "=r") | |
1816 | (match_operand:DI 1 "const0_operand" "i")) | |
1817 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
1818 | "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size) |
1819 | && reload_completed" | |
0f40f9f7 | 1820 | "xor{l}\t{%k0, %k0|%k0, %k0}" |
0ec259ed JH |
1821 | [(set_attr "type" "alu1") |
1822 | (set_attr "mode" "SI") | |
1823 | (set_attr "length_immediate" "0")]) | |
1824 | ||
1825 | (define_insn "*movdi_or_rex64" | |
1826 | [(set (match_operand:DI 0 "register_operand" "=r") | |
1827 | (match_operand:DI 1 "const_int_operand" "i")) | |
1828 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
1829 | "TARGET_64BIT && (TARGET_PENTIUM || optimize_size) |
1830 | && reload_completed | |
1831 | && GET_CODE (operands[1]) == CONST_INT | |
1832 | && INTVAL (operands[1]) == -1" | |
0ec259ed JH |
1833 | { |
1834 | operands[1] = constm1_rtx; | |
0f40f9f7 ZW |
1835 | return "or{q}\t{%1, %0|%0, %1}"; |
1836 | } | |
0ec259ed JH |
1837 | [(set_attr "type" "alu1") |
1838 | (set_attr "mode" "DI") | |
1839 | (set_attr "length_immediate" "1")]) | |
1840 | ||
e075ae69 | 1841 | (define_insn "*movdi_2" |
749e7b80 | 1842 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y") |
141e454b | 1843 | (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))] |
1e07edd3 JH |
1844 | "!TARGET_64BIT |
1845 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
915119a5 BS |
1846 | "@ |
1847 | # | |
1848 | # | |
0f40f9f7 ZW |
1849 | movq\t{%1, %0|%0, %1} |
1850 | movq\t{%1, %0|%0, %1} | |
1851 | movq\t{%1, %0|%0, %1} | |
1852 | movdqa\t{%1, %0|%0, %1} | |
1853 | movq\t{%1, %0|%0, %1}" | |
3d34cd91 | 1854 | [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov") |
141e454b | 1855 | (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")]) |
dc0f0eb8 | 1856 | |
e075ae69 RH |
1857 | (define_split |
1858 | [(set (match_operand:DI 0 "push_operand" "") | |
1859 | (match_operand:DI 1 "general_operand" ""))] | |
6c12e488 JH |
1860 | "!TARGET_64BIT && reload_completed |
1861 | && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))" | |
2450a057 | 1862 | [(const_int 0)] |
26e5b205 | 1863 | "ix86_split_long_move (operands); DONE;") |
f31fce3f | 1864 | |
e075ae69 | 1865 | ;; %%% This multiword shite has got to go. |
e075ae69 | 1866 | (define_split |
c76aab11 | 1867 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
e075ae69 | 1868 | (match_operand:DI 1 "general_operand" ""))] |
6c12e488 JH |
1869 | "!TARGET_64BIT && reload_completed |
1870 | && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0])) | |
1871 | && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))" | |
26e5b205 JH |
1872 | [(const_int 0)] |
1873 | "ix86_split_long_move (operands); DONE;") | |
0ec259ed JH |
1874 | |
1875 | (define_insn "*movdi_1_rex64" | |
141e454b JH |
1876 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y") |
1877 | (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))] | |
1b0c37d7 ZW |
1878 | "TARGET_64BIT |
1879 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
0ec259ed JH |
1880 | { |
1881 | switch (get_attr_type (insn)) | |
1882 | { | |
5f90a099 | 1883 | case TYPE_SSEMOV: |
141e454b JH |
1884 | if (register_operand (operands[0], DImode) |
1885 | && register_operand (operands[1], DImode)) | |
0f40f9f7 | 1886 | return "movdqa\t{%1, %0|%0, %1}"; |
141e454b | 1887 | /* FALLTHRU */ |
5f90a099 | 1888 | case TYPE_MMXMOV: |
0f40f9f7 | 1889 | return "movq\t{%1, %0|%0, %1}"; |
0ec259ed | 1890 | case TYPE_MULTI: |
0f40f9f7 | 1891 | return "#"; |
0ec259ed | 1892 | case TYPE_LEA: |
0f40f9f7 | 1893 | return "lea{q}\t{%a1, %0|%0, %a1}"; |
0ec259ed | 1894 | default: |
57d47446 | 1895 | if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1])) |
0ec259ed JH |
1896 | abort (); |
1897 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 1898 | return "mov{l}\t{%k1, %k0|%k0, %k1}"; |
0ec259ed | 1899 | else if (which_alternative == 2) |
0f40f9f7 | 1900 | return "movabs{q}\t{%1, %0|%0, %1}"; |
0ec259ed | 1901 | else |
0f40f9f7 | 1902 | return "mov{q}\t{%1, %0|%0, %1}"; |
0ec259ed | 1903 | } |
0f40f9f7 | 1904 | } |
0ec259ed JH |
1905 | [(set (attr "type") |
1906 | (cond [(eq_attr "alternative" "5,6") | |
3d34cd91 | 1907 | (const_string "mmxmov") |
0ec259ed | 1908 | (eq_attr "alternative" "7,8") |
3d34cd91 | 1909 | (const_string "ssemov") |
0ec259ed JH |
1910 | (eq_attr "alternative" "4") |
1911 | (const_string "multi") | |
1912 | (and (ne (symbol_ref "flag_pic") (const_int 0)) | |
1913 | (match_operand:DI 1 "symbolic_operand" "")) | |
1914 | (const_string "lea") | |
1915 | ] | |
1916 | (const_string "imov"))) | |
141e454b JH |
1917 | (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*") |
1918 | (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*") | |
1919 | (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")]) | |
0ec259ed JH |
1920 | |
1921 | ;; Stores and loads of ax to arbitary constant address. | |
1922 | ;; We fake an second form of instruction to force reload to load address | |
1923 | ;; into register when rax is not available | |
1924 | (define_insn "*movabsdi_1_rex64" | |
1925 | [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r")) | |
1926 | (match_operand:DI 1 "nonmemory_operand" "a,er,i"))] | |
1927 | "TARGET_64BIT" | |
1928 | "@ | |
0f40f9f7 ZW |
1929 | movabs{q}\t{%1, %P0|%P0, %1} |
1930 | mov{q}\t{%1, %a0|%a0, %1} | |
1931 | movabs{q}\t{%1, %a0|%a0, %1}" | |
0ec259ed JH |
1932 | [(set_attr "type" "imov") |
1933 | (set_attr "modrm" "0,*,*") | |
1934 | (set_attr "length_address" "8,0,0") | |
1935 | (set_attr "length_immediate" "0,*,*") | |
1936 | (set_attr "memory" "store") | |
1937 | (set_attr "mode" "DI")]) | |
1938 | ||
1939 | (define_insn "*movabsdi_2_rex64" | |
1940 | [(set (match_operand:DI 0 "register_operand" "=a,r") | |
1941 | (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] | |
1942 | "TARGET_64BIT" | |
1943 | "@ | |
0f40f9f7 ZW |
1944 | movabs{q}\t{%P1, %0|%0, %P1} |
1945 | mov{q}\t{%a1, %0|%0, %a1}" | |
0ec259ed JH |
1946 | [(set_attr "type" "imov") |
1947 | (set_attr "modrm" "0,*") | |
1948 | (set_attr "length_address" "8,0") | |
1949 | (set_attr "length_immediate" "0") | |
1950 | (set_attr "memory" "load") | |
1951 | (set_attr "mode" "DI")]) | |
1952 | ||
1953 | ;; Convert impossible stores of immediate to existing instructions. | |
f5143c46 | 1954 | ;; First try to get scratch register and go through it. In case this |
0ec259ed JH |
1955 | ;; fails, move by 32bit parts. |
1956 | (define_peephole2 | |
1957 | [(match_scratch:DI 2 "r") | |
1958 | (set (match_operand:DI 0 "memory_operand" "") | |
1959 | (match_operand:DI 1 "immediate_operand" ""))] | |
1960 | "TARGET_64BIT && !symbolic_operand (operands[1], DImode) | |
1961 | && !x86_64_immediate_operand (operands[1], DImode)" | |
1962 | [(set (match_dup 2) (match_dup 1)) | |
1963 | (set (match_dup 0) (match_dup 2))] | |
1964 | "") | |
1965 | ||
1966 | ;; We need to define this as both peepholer and splitter for case | |
1967 | ;; peephole2 pass is not run. | |
1968 | (define_peephole2 | |
1969 | [(set (match_operand:DI 0 "memory_operand" "") | |
1970 | (match_operand:DI 1 "immediate_operand" ""))] | |
1971 | "TARGET_64BIT && !symbolic_operand (operands[1], DImode) | |
1972 | && !x86_64_immediate_operand (operands[1], DImode) && 1" | |
1973 | [(set (match_dup 2) (match_dup 3)) | |
1974 | (set (match_dup 4) (match_dup 5))] | |
1975 | "split_di (operands, 2, operands + 2, operands + 4);") | |
1976 | ||
1977 | (define_split | |
1978 | [(set (match_operand:DI 0 "memory_operand" "") | |
1979 | (match_operand:DI 1 "immediate_operand" ""))] | |
1980 | "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2)) | |
1981 | && !symbolic_operand (operands[1], DImode) | |
1982 | && !x86_64_immediate_operand (operands[1], DImode)" | |
1983 | [(set (match_dup 2) (match_dup 3)) | |
1984 | (set (match_dup 4) (match_dup 5))] | |
1985 | "split_di (operands, 2, operands + 2, operands + 4);") | |
1986 | ||
1987 | (define_insn "*swapdi_rex64" | |
1988 | [(set (match_operand:DI 0 "register_operand" "+r") | |
1989 | (match_operand:DI 1 "register_operand" "+r")) | |
1990 | (set (match_dup 1) | |
1991 | (match_dup 0))] | |
1992 | "TARGET_64BIT" | |
0f40f9f7 | 1993 | "xchg{q}\t%1, %0" |
0ec259ed JH |
1994 | [(set_attr "type" "imov") |
1995 | (set_attr "pent_pair" "np") | |
1996 | (set_attr "athlon_decode" "vector") | |
1997 | (set_attr "mode" "DI") | |
1998 | (set_attr "modrm" "0") | |
1999 | (set_attr "ppro_uops" "few")]) | |
2000 | ||
e075ae69 | 2001 | |
0be5d99f | 2002 | (define_expand "movsf" |
4cbfbb1b | 2003 | [(set (match_operand:SF 0 "nonimmediate_operand" "") |
0be5d99f MM |
2004 | (match_operand:SF 1 "general_operand" ""))] |
2005 | "" | |
e075ae69 RH |
2006 | "ix86_expand_move (SFmode, operands); DONE;") |
2007 | ||
2008 | (define_insn "*pushsf" | |
446988df | 2009 | [(set (match_operand:SF 0 "push_operand" "=<,<,<") |
c6e95f34 | 2010 | (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))] |
0ec259ed | 2011 | "!TARGET_64BIT" |
0be5d99f | 2012 | { |
e075ae69 | 2013 | switch (which_alternative) |
0be5d99f | 2014 | { |
e075ae69 RH |
2015 | case 0: |
2016 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2017 | operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx); | |
2018 | operands[2] = stack_pointer_rtx; | |
2019 | operands[3] = GEN_INT (4); | |
2020 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2021 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
e075ae69 | 2022 | else |
0f40f9f7 | 2023 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
0bb6c81b | 2024 | |
e075ae69 | 2025 | case 1: |
0f40f9f7 | 2026 | return "push{l}\t%1"; |
446988df | 2027 | case 2: |
0f40f9f7 | 2028 | return "#"; |
e075ae69 RH |
2029 | |
2030 | default: | |
2031 | abort (); | |
0bb6c81b | 2032 | } |
0f40f9f7 | 2033 | } |
446988df JH |
2034 | [(set_attr "type" "multi,push,multi") |
2035 | (set_attr "mode" "SF,SI,SF")]) | |
0be5d99f | 2036 | |
0ec259ed JH |
2037 | (define_insn "*pushsf_rex64" |
2038 | [(set (match_operand:SF 0 "push_operand" "=X,X,X") | |
2039 | (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))] | |
2040 | "TARGET_64BIT" | |
0ec259ed JH |
2041 | { |
2042 | switch (which_alternative) | |
2043 | { | |
2044 | case 0: | |
2045 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2046 | operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx); | |
2047 | operands[2] = stack_pointer_rtx; | |
2048 | operands[3] = GEN_INT (8); | |
2049 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2050 | return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 2051 | else |
0f40f9f7 | 2052 | return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
0ec259ed JH |
2053 | |
2054 | case 1: | |
0f40f9f7 | 2055 | return "push{q}\t%q1"; |
0ec259ed JH |
2056 | |
2057 | case 2: | |
0f40f9f7 | 2058 | return "#"; |
0ec259ed JH |
2059 | |
2060 | default: | |
2061 | abort (); | |
2062 | } | |
0f40f9f7 | 2063 | } |
0ec259ed JH |
2064 | [(set_attr "type" "multi,push,multi") |
2065 | (set_attr "mode" "SF,DI,SF")]) | |
2066 | ||
d7a29404 JH |
2067 | (define_split |
2068 | [(set (match_operand:SF 0 "push_operand" "") | |
2069 | (match_operand:SF 1 "memory_operand" ""))] | |
2070 | "reload_completed | |
2071 | && GET_CODE (operands[1]) == MEM | |
2072 | && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF | |
2073 | && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))" | |
2074 | [(set (match_dup 0) | |
2075 | (match_dup 1))] | |
2076 | "operands[1] = get_pool_constant (XEXP (operands[1], 0));") | |
2077 | ||
2078 | ||
e075ae69 RH |
2079 | ;; %%% Kill this when call knows how to work this out. |
2080 | (define_split | |
2081 | [(set (match_operand:SF 0 "push_operand" "") | |
c3c637e3 GS |
2082 | (match_operand:SF 1 "any_fp_register_operand" ""))] |
2083 | "!TARGET_64BIT" | |
e075ae69 RH |
2084 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) |
2085 | (set (mem:SF (reg:SI 7)) (match_dup 1))]) | |
2086 | ||
0ec259ed JH |
2087 | (define_split |
2088 | [(set (match_operand:SF 0 "push_operand" "") | |
c3c637e3 GS |
2089 | (match_operand:SF 1 "any_fp_register_operand" ""))] |
2090 | "TARGET_64BIT" | |
0ec259ed JH |
2091 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) |
2092 | (set (mem:SF (reg:DI 7)) (match_dup 1))]) | |
2093 | ||
e075ae69 | 2094 | (define_insn "*movsf_1" |
e5a20888 JJ |
2095 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y") |
2096 | (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))] | |
d7a29404 JH |
2097 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
2098 | && (reload_in_progress || reload_completed | |
3987b9db | 2099 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
d7a29404 JH |
2100 | || GET_CODE (operands[1]) != CONST_DOUBLE |
2101 | || memory_operand (operands[0], SFmode))" | |
886c62d1 | 2102 | { |
e075ae69 | 2103 | switch (which_alternative) |
886c62d1 | 2104 | { |
e075ae69 | 2105 | case 0: |
0c174a68 AB |
2106 | if (REG_P (operands[1]) |
2107 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2108 | return "fstp\t%y0"; |
e075ae69 | 2109 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2110 | return "fld%z1\t%y1"; |
886c62d1 | 2111 | else |
0f40f9f7 | 2112 | return "fst\t%y0"; |
886c62d1 | 2113 | |
e075ae69 RH |
2114 | case 1: |
2115 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2116 | return "fstp%z0\t%y0"; |
886c62d1 | 2117 | else |
0f40f9f7 | 2118 | return "fst%z0\t%y0"; |
886c62d1 | 2119 | |
e075ae69 RH |
2120 | case 2: |
2121 | switch (standard_80387_constant_p (operands[1])) | |
2122 | { | |
2123 | case 1: | |
0f40f9f7 | 2124 | return "fldz"; |
e075ae69 | 2125 | case 2: |
0f40f9f7 | 2126 | return "fld1"; |
e075ae69 RH |
2127 | } |
2128 | abort(); | |
886c62d1 | 2129 | |
e075ae69 RH |
2130 | case 3: |
2131 | case 4: | |
0f40f9f7 | 2132 | return "mov{l}\t{%1, %0|%0, %1}"; |
446988df | 2133 | case 5: |
052c96b1 | 2134 | if (TARGET_SSE2 && !TARGET_ATHLON) |
692efa8e JJ |
2135 | return "pxor\t%0, %0"; |
2136 | else | |
2137 | return "xorps\t%0, %0"; | |
446988df | 2138 | case 6: |
2b04e52b | 2139 | if (TARGET_PARTIAL_REG_DEPENDENCY) |
0f40f9f7 | 2140 | return "movaps\t{%1, %0|%0, %1}"; |
2b04e52b | 2141 | else |
0f40f9f7 | 2142 | return "movss\t{%1, %0|%0, %1}"; |
2b04e52b JH |
2143 | case 7: |
2144 | case 8: | |
0f40f9f7 | 2145 | return "movss\t{%1, %0|%0, %1}"; |
886c62d1 | 2146 | |
ac300a45 JJ |
2147 | case 9: |
2148 | case 10: | |
2149 | return "movd\t{%1, %0|%0, %1}"; | |
2150 | ||
e5a20888 JJ |
2151 | case 11: |
2152 | return "movq\t{%1, %0|%0, %1}"; | |
2153 | ||
e075ae69 RH |
2154 | default: |
2155 | abort(); | |
2156 | } | |
0f40f9f7 | 2157 | } |
3d34cd91 | 2158 | [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov") |
e5a20888 | 2159 | (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")]) |
d7a29404 | 2160 | |
a4414093 | 2161 | (define_insn "*swapsf" |
e075ae69 RH |
2162 | [(set (match_operand:SF 0 "register_operand" "+f") |
2163 | (match_operand:SF 1 "register_operand" "+f")) | |
0be5d99f MM |
2164 | (set (match_dup 1) |
2165 | (match_dup 0))] | |
965f5423 | 2166 | "reload_completed || !TARGET_SSE" |
0be5d99f MM |
2167 | { |
2168 | if (STACK_TOP_P (operands[0])) | |
0f40f9f7 | 2169 | return "fxch\t%1"; |
0be5d99f | 2170 | else |
0f40f9f7 ZW |
2171 | return "fxch\t%0"; |
2172 | } | |
6ef67412 JH |
2173 | [(set_attr "type" "fxch") |
2174 | (set_attr "mode" "SF")]) | |
0be5d99f | 2175 | |
e075ae69 | 2176 | (define_expand "movdf" |
4cbfbb1b | 2177 | [(set (match_operand:DF 0 "nonimmediate_operand" "") |
e075ae69 RH |
2178 | (match_operand:DF 1 "general_operand" ""))] |
2179 | "" | |
2180 | "ix86_expand_move (DFmode, operands); DONE;") | |
55953cea | 2181 | |
8fcaaa80 JH |
2182 | ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size. |
2183 | ;; Size of pushdf using integer insturctions is 2+2*memory operand size | |
2184 | ;; On the average, pushdf using integers can be still shorter. Allow this | |
2185 | ;; pattern for optimize_size too. | |
2186 | ||
0b5107cf | 2187 | (define_insn "*pushdf_nointeger" |
446988df | 2188 | [(set (match_operand:DF 0 "push_operand" "=<,<,<,<") |
c6e95f34 | 2189 | (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))] |
0ec259ed | 2190 | "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES" |
0b5107cf JH |
2191 | { |
2192 | switch (which_alternative) | |
2193 | { | |
2194 | case 0: | |
2195 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2196 | operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx); | |
2197 | operands[2] = stack_pointer_rtx; | |
2198 | operands[3] = GEN_INT (8); | |
2199 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2200 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0b5107cf | 2201 | else |
0f40f9f7 | 2202 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
0b5107cf JH |
2203 | |
2204 | case 1: | |
2205 | case 2: | |
446988df | 2206 | case 3: |
0f40f9f7 | 2207 | return "#"; |
0b5107cf JH |
2208 | |
2209 | default: | |
2210 | abort (); | |
2211 | } | |
0f40f9f7 | 2212 | } |
6ef67412 | 2213 | [(set_attr "type" "multi") |
446988df | 2214 | (set_attr "mode" "DF,SI,SI,DF")]) |
0b5107cf JH |
2215 | |
2216 | (define_insn "*pushdf_integer" | |
446988df JH |
2217 | [(set (match_operand:DF 0 "push_operand" "=<,<,<") |
2218 | (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))] | |
0ec259ed | 2219 | "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES" |
f31fce3f | 2220 | { |
e075ae69 | 2221 | switch (which_alternative) |
f31fce3f | 2222 | { |
e075ae69 RH |
2223 | case 0: |
2224 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2225 | operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx); | |
2226 | operands[2] = stack_pointer_rtx; | |
2227 | operands[3] = GEN_INT (8); | |
0ec259ed JH |
2228 | if (TARGET_64BIT) |
2229 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2230 | return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 2231 | else |
0f40f9f7 | 2232 | return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
f31fce3f | 2233 | else |
0ec259ed | 2234 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) |
0f40f9f7 | 2235 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 2236 | else |
0f40f9f7 | 2237 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
0ec259ed | 2238 | |
dc0f0eb8 | 2239 | |
e075ae69 | 2240 | case 1: |
446988df | 2241 | case 2: |
0f40f9f7 | 2242 | return "#"; |
dc0f0eb8 | 2243 | |
e075ae69 RH |
2244 | default: |
2245 | abort (); | |
2246 | } | |
0f40f9f7 | 2247 | } |
6ef67412 | 2248 | [(set_attr "type" "multi") |
446988df | 2249 | (set_attr "mode" "DF,SI,DF")]) |
f31fce3f | 2250 | |
e075ae69 | 2251 | ;; %%% Kill this when call knows how to work this out. |
f72b27a5 JH |
2252 | (define_split |
2253 | [(set (match_operand:DF 0 "push_operand" "") | |
c3c637e3 GS |
2254 | (match_operand:DF 1 "any_fp_register_operand" ""))] |
2255 | "!TARGET_64BIT && reload_completed" | |
e075ae69 RH |
2256 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) |
2257 | (set (mem:DF (reg:SI 7)) (match_dup 1))] | |
f72b27a5 | 2258 | "") |
f31fce3f | 2259 | |
0ec259ed JH |
2260 | (define_split |
2261 | [(set (match_operand:DF 0 "push_operand" "") | |
c3c637e3 GS |
2262 | (match_operand:DF 1 "any_fp_register_operand" ""))] |
2263 | "TARGET_64BIT && reload_completed" | |
0ec259ed JH |
2264 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) |
2265 | (set (mem:DF (reg:DI 7)) (match_dup 1))] | |
2266 | "") | |
2267 | ||
e075ae69 RH |
2268 | (define_split |
2269 | [(set (match_operand:DF 0 "push_operand" "") | |
0be5d99f | 2270 | (match_operand:DF 1 "general_operand" ""))] |
e075ae69 | 2271 | "reload_completed" |
2450a057 | 2272 | [(const_int 0)] |
26e5b205 | 2273 | "ix86_split_long_move (operands); DONE;") |
0be5d99f | 2274 | |
8fcaaa80 JH |
2275 | ;; Moving is usually shorter when only FP registers are used. This separate |
2276 | ;; movdf pattern avoids the use of integer registers for FP operations | |
2277 | ;; when optimizing for size. | |
2278 | ||
2279 | (define_insn "*movdf_nointeger" | |
2b04e52b JH |
2280 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m") |
2281 | (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))] | |
8fcaaa80 | 2282 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
0b5107cf | 2283 | && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES) |
d7a29404 | 2284 | && (reload_in_progress || reload_completed |
3987b9db | 2285 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
d7a29404 JH |
2286 | || GET_CODE (operands[1]) != CONST_DOUBLE |
2287 | || memory_operand (operands[0], DFmode))" | |
8fcaaa80 JH |
2288 | { |
2289 | switch (which_alternative) | |
2290 | { | |
2291 | case 0: | |
2292 | if (REG_P (operands[1]) | |
2293 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2294 | return "fstp\t%y0"; |
8fcaaa80 | 2295 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2296 | return "fld%z1\t%y1"; |
8fcaaa80 | 2297 | else |
0f40f9f7 | 2298 | return "fst\t%y0"; |
8fcaaa80 JH |
2299 | |
2300 | case 1: | |
2301 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2302 | return "fstp%z0\t%y0"; |
8fcaaa80 | 2303 | else |
0f40f9f7 | 2304 | return "fst%z0\t%y0"; |
8fcaaa80 JH |
2305 | |
2306 | case 2: | |
2307 | switch (standard_80387_constant_p (operands[1])) | |
2308 | { | |
2309 | case 1: | |
0f40f9f7 | 2310 | return "fldz"; |
8fcaaa80 | 2311 | case 2: |
0f40f9f7 | 2312 | return "fld1"; |
8fcaaa80 JH |
2313 | } |
2314 | abort(); | |
2315 | ||
2316 | case 3: | |
2317 | case 4: | |
0f40f9f7 | 2318 | return "#"; |
446988df | 2319 | case 5: |
052c96b1 JH |
2320 | if (TARGET_ATHLON) |
2321 | return "xorpd\t%0, %0"; | |
2322 | else | |
2323 | return "pxor\t%0, %0"; | |
446988df | 2324 | case 6: |
2b04e52b | 2325 | if (TARGET_PARTIAL_REG_DEPENDENCY) |
0f40f9f7 | 2326 | return "movapd\t{%1, %0|%0, %1}"; |
2b04e52b | 2327 | else |
0f40f9f7 | 2328 | return "movsd\t{%1, %0|%0, %1}"; |
2b04e52b JH |
2329 | case 7: |
2330 | case 8: | |
0f40f9f7 | 2331 | return "movsd\t{%1, %0|%0, %1}"; |
8fcaaa80 JH |
2332 | |
2333 | default: | |
2334 | abort(); | |
2335 | } | |
0f40f9f7 | 2336 | } |
3d34cd91 | 2337 | [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov") |
2b04e52b | 2338 | (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")]) |
8fcaaa80 JH |
2339 | |
2340 | (define_insn "*movdf_integer" | |
2b04e52b JH |
2341 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m") |
2342 | (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))] | |
8fcaaa80 | 2343 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
0b5107cf | 2344 | && !optimize_size && TARGET_INTEGER_DFMODE_MOVES |
d7a29404 | 2345 | && (reload_in_progress || reload_completed |
3987b9db | 2346 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
d7a29404 JH |
2347 | || GET_CODE (operands[1]) != CONST_DOUBLE |
2348 | || memory_operand (operands[0], DFmode))" | |
886c62d1 | 2349 | { |
e075ae69 | 2350 | switch (which_alternative) |
886c62d1 | 2351 | { |
e075ae69 | 2352 | case 0: |
0c174a68 AB |
2353 | if (REG_P (operands[1]) |
2354 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2355 | return "fstp\t%y0"; |
e075ae69 | 2356 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2357 | return "fld%z1\t%y1"; |
886c62d1 | 2358 | else |
0f40f9f7 | 2359 | return "fst\t%y0"; |
886c62d1 | 2360 | |
e075ae69 RH |
2361 | case 1: |
2362 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2363 | return "fstp%z0\t%y0"; |
886c62d1 | 2364 | else |
0f40f9f7 | 2365 | return "fst%z0\t%y0"; |
886c62d1 | 2366 | |
e075ae69 RH |
2367 | case 2: |
2368 | switch (standard_80387_constant_p (operands[1])) | |
2369 | { | |
2370 | case 1: | |
0f40f9f7 | 2371 | return "fldz"; |
e075ae69 | 2372 | case 2: |
0f40f9f7 | 2373 | return "fld1"; |
e075ae69 RH |
2374 | } |
2375 | abort(); | |
886c62d1 | 2376 | |
e075ae69 RH |
2377 | case 3: |
2378 | case 4: | |
0f40f9f7 | 2379 | return "#"; |
886c62d1 | 2380 | |
446988df | 2381 | case 5: |
052c96b1 JH |
2382 | if (TARGET_ATHLON) |
2383 | return "xorpd\t%0, %0"; | |
2384 | else | |
2385 | return "pxor\t%0, %0"; | |
446988df | 2386 | case 6: |
2b04e52b | 2387 | if (TARGET_PARTIAL_REG_DEPENDENCY) |
0f40f9f7 | 2388 | return "movapd\t{%1, %0|%0, %1}"; |
2b04e52b | 2389 | else |
0f40f9f7 | 2390 | return "movsd\t{%1, %0|%0, %1}"; |
2b04e52b JH |
2391 | case 7: |
2392 | case 8: | |
0f40f9f7 | 2393 | return "movsd\t{%1, %0|%0, %1}"; |
446988df | 2394 | |
e075ae69 RH |
2395 | default: |
2396 | abort(); | |
2397 | } | |
0f40f9f7 | 2398 | } |
3d34cd91 | 2399 | [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov") |
2b04e52b | 2400 | (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")]) |
2ae0f82c | 2401 | |
e075ae69 RH |
2402 | (define_split |
2403 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
2404 | (match_operand:DF 1 "general_operand" ""))] | |
2405 | "reload_completed | |
2406 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
446988df | 2407 | && ! (ANY_FP_REG_P (operands[0]) || |
e075ae69 | 2408 | (GET_CODE (operands[0]) == SUBREG |
446988df JH |
2409 | && ANY_FP_REG_P (SUBREG_REG (operands[0])))) |
2410 | && ! (ANY_FP_REG_P (operands[1]) || | |
e075ae69 | 2411 | (GET_CODE (operands[1]) == SUBREG |
446988df | 2412 | && ANY_FP_REG_P (SUBREG_REG (operands[1]))))" |
26e5b205 JH |
2413 | [(const_int 0)] |
2414 | "ix86_split_long_move (operands); DONE;") | |
886c62d1 | 2415 | |
a4414093 | 2416 | (define_insn "*swapdf" |
e075ae69 RH |
2417 | [(set (match_operand:DF 0 "register_operand" "+f") |
2418 | (match_operand:DF 1 "register_operand" "+f")) | |
0be5d99f MM |
2419 | (set (match_dup 1) |
2420 | (match_dup 0))] | |
446988df | 2421 | "reload_completed || !TARGET_SSE2" |
0be5d99f MM |
2422 | { |
2423 | if (STACK_TOP_P (operands[0])) | |
0f40f9f7 | 2424 | return "fxch\t%1"; |
0be5d99f | 2425 | else |
0f40f9f7 ZW |
2426 | return "fxch\t%0"; |
2427 | } | |
6ef67412 JH |
2428 | [(set_attr "type" "fxch") |
2429 | (set_attr "mode" "DF")]) | |
e075ae69 RH |
2430 | |
2431 | (define_expand "movxf" | |
4cbfbb1b | 2432 | [(set (match_operand:XF 0 "nonimmediate_operand" "") |
e075ae69 | 2433 | (match_operand:XF 1 "general_operand" ""))] |
1e07edd3 | 2434 | "!TARGET_64BIT" |
e075ae69 | 2435 | "ix86_expand_move (XFmode, operands); DONE;") |
0be5d99f | 2436 | |
2b589241 JH |
2437 | (define_expand "movtf" |
2438 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
2439 | (match_operand:TF 1 "general_operand" ""))] | |
2440 | "" | |
2441 | "ix86_expand_move (TFmode, operands); DONE;") | |
2442 | ||
8fcaaa80 JH |
2443 | ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size. |
2444 | ;; Size of pushdf using integer insturctions is 3+3*memory operand size | |
2445 | ;; Pushing using integer instructions is longer except for constants | |
2446 | ;; and direct memory references. | |
2447 | ;; (assuming that any given constant is pushed only once, but this ought to be | |
2448 | ;; handled elsewhere). | |
2449 | ||
2450 | (define_insn "*pushxf_nointeger" | |
1e07edd3 | 2451 | [(set (match_operand:XF 0 "push_operand" "=X,X,X") |
2c5a510c | 2452 | (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))] |
1b0c37d7 | 2453 | "!TARGET_64BIT && optimize_size" |
8fcaaa80 JH |
2454 | { |
2455 | switch (which_alternative) | |
2456 | { | |
2457 | case 0: | |
2458 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2459 | operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); | |
2460 | operands[2] = stack_pointer_rtx; | |
2461 | operands[3] = GEN_INT (12); | |
2462 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2463 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
8fcaaa80 | 2464 | else |
0f40f9f7 | 2465 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
8fcaaa80 JH |
2466 | |
2467 | case 1: | |
2468 | case 2: | |
0f40f9f7 | 2469 | return "#"; |
8fcaaa80 JH |
2470 | |
2471 | default: | |
2472 | abort (); | |
2473 | } | |
0f40f9f7 | 2474 | } |
6ef67412 JH |
2475 | [(set_attr "type" "multi") |
2476 | (set_attr "mode" "XF,SI,SI")]) | |
8fcaaa80 | 2477 | |
2b589241 JH |
2478 | (define_insn "*pushtf_nointeger" |
2479 | [(set (match_operand:TF 0 "push_operand" "=<,<,<") | |
2480 | (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))] | |
2481 | "optimize_size" | |
2b589241 JH |
2482 | { |
2483 | switch (which_alternative) | |
2484 | { | |
2485 | case 0: | |
2486 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2487 | operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); | |
2488 | operands[2] = stack_pointer_rtx; | |
2489 | operands[3] = GEN_INT (16); | |
2490 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2491 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
2b589241 | 2492 | else |
0f40f9f7 | 2493 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
2b589241 JH |
2494 | |
2495 | case 1: | |
2496 | case 2: | |
0f40f9f7 | 2497 | return "#"; |
2b589241 JH |
2498 | |
2499 | default: | |
2500 | abort (); | |
2501 | } | |
0f40f9f7 | 2502 | } |
2b589241 JH |
2503 | [(set_attr "type" "multi") |
2504 | (set_attr "mode" "XF,SI,SI")]) | |
2505 | ||
8fcaaa80 | 2506 | (define_insn "*pushxf_integer" |
2450a057 | 2507 | [(set (match_operand:XF 0 "push_operand" "=<,<") |
1e07edd3 | 2508 | (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))] |
1b0c37d7 | 2509 | "!TARGET_64BIT && !optimize_size" |
f31fce3f | 2510 | { |
8fcaaa80 JH |
2511 | switch (which_alternative) |
2512 | { | |
2513 | case 0: | |
2514 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2515 | operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); | |
2516 | operands[2] = stack_pointer_rtx; | |
2517 | operands[3] = GEN_INT (12); | |
2518 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2519 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
8fcaaa80 | 2520 | else |
0f40f9f7 | 2521 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
8fcaaa80 JH |
2522 | |
2523 | case 1: | |
0f40f9f7 | 2524 | return "#"; |
8fcaaa80 JH |
2525 | |
2526 | default: | |
2527 | abort (); | |
2528 | } | |
0f40f9f7 | 2529 | } |
6ef67412 JH |
2530 | [(set_attr "type" "multi") |
2531 | (set_attr "mode" "XF,SI")]) | |
f31fce3f | 2532 | |
2b589241 JH |
2533 | (define_insn "*pushtf_integer" |
2534 | [(set (match_operand:TF 0 "push_operand" "=<,<") | |
2535 | (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))] | |
2536 | "!optimize_size" | |
2b589241 JH |
2537 | { |
2538 | switch (which_alternative) | |
2539 | { | |
2540 | case 0: | |
2541 | /* %%% We loose REG_DEAD notes for controling pops if we split late. */ | |
2542 | operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx); | |
2543 | operands[2] = stack_pointer_rtx; | |
2544 | operands[3] = GEN_INT (16); | |
0ec259ed JH |
2545 | if (TARGET_64BIT) |
2546 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2547 | return "sub{q}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 2548 | else |
0f40f9f7 | 2549 | return "sub{q}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
2b589241 | 2550 | else |
0ec259ed | 2551 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) |
0f40f9f7 | 2552 | return "sub{l}\t{%3, %2|%2, %3}\;fstp%z0\t%y0"; |
0ec259ed | 2553 | else |
0f40f9f7 | 2554 | return "sub{l}\t{%3, %2|%2, %3}\;fst%z0\t%y0"; |
2b589241 JH |
2555 | |
2556 | case 1: | |
0f40f9f7 | 2557 | return "#"; |
2b589241 JH |
2558 | |
2559 | default: | |
2560 | abort (); | |
2561 | } | |
0f40f9f7 | 2562 | } |
2b589241 JH |
2563 | [(set_attr "type" "multi") |
2564 | (set_attr "mode" "XF,SI")]) | |
2565 | ||
2450a057 | 2566 | (define_split |
2b589241 JH |
2567 | [(set (match_operand 0 "push_operand" "") |
2568 | (match_operand 1 "general_operand" ""))] | |
2450a057 | 2569 | "reload_completed |
2b589241 JH |
2570 | && (GET_MODE (operands[0]) == XFmode |
2571 | || GET_MODE (operands[0]) == TFmode | |
2572 | || GET_MODE (operands[0]) == DFmode) | |
c3c637e3 | 2573 | && !ANY_FP_REG_P (operands[1])" |
2450a057 | 2574 | [(const_int 0)] |
26e5b205 | 2575 | "ix86_split_long_move (operands); DONE;") |
2450a057 | 2576 | |
f72b27a5 JH |
2577 | (define_split |
2578 | [(set (match_operand:XF 0 "push_operand" "") | |
c3c637e3 GS |
2579 | (match_operand:XF 1 "any_fp_register_operand" ""))] |
2580 | "!TARGET_64BIT" | |
e075ae69 RH |
2581 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) |
2582 | (set (mem:XF (reg:SI 7)) (match_dup 1))]) | |
f31fce3f | 2583 | |
2b589241 JH |
2584 | (define_split |
2585 | [(set (match_operand:TF 0 "push_operand" "") | |
c3c637e3 GS |
2586 | (match_operand:TF 1 "any_fp_register_operand" ""))] |
2587 | "!TARGET_64BIT" | |
2b589241 JH |
2588 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) |
2589 | (set (mem:TF (reg:SI 7)) (match_dup 1))]) | |
2590 | ||
0ec259ed JH |
2591 | (define_split |
2592 | [(set (match_operand:TF 0 "push_operand" "") | |
c3c637e3 GS |
2593 | (match_operand:TF 1 "any_fp_register_operand" ""))] |
2594 | "TARGET_64BIT" | |
0ec259ed JH |
2595 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) |
2596 | (set (mem:TF (reg:DI 7)) (match_dup 1))]) | |
2597 | ||
8fcaaa80 JH |
2598 | ;; Do not use integer registers when optimizing for size |
2599 | (define_insn "*movxf_nointeger" | |
2600 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o") | |
2601 | (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))] | |
1b0c37d7 | 2602 | "!TARGET_64BIT |
d7a29404 | 2603 | && optimize_size |
1b0c37d7 | 2604 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
d7a29404 JH |
2605 | && (reload_in_progress || reload_completed |
2606 | || GET_CODE (operands[1]) != CONST_DOUBLE | |
2607 | || memory_operand (operands[0], XFmode))" | |
0be5d99f | 2608 | { |
8fcaaa80 JH |
2609 | switch (which_alternative) |
2610 | { | |
2611 | case 0: | |
2612 | if (REG_P (operands[1]) | |
2613 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2614 | return "fstp\t%y0"; |
8fcaaa80 | 2615 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2616 | return "fld%z1\t%y1"; |
8fcaaa80 | 2617 | else |
0f40f9f7 | 2618 | return "fst\t%y0"; |
0be5d99f | 2619 | |
8fcaaa80 JH |
2620 | case 1: |
2621 | /* There is no non-popping store to memory for XFmode. So if | |
2622 | we need one, follow the store with a load. */ | |
2623 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2624 | return "fstp%z0\t%y0\;fld%z0\t%y0"; |
8fcaaa80 | 2625 | else |
0f40f9f7 | 2626 | return "fstp%z0\t%y0"; |
8fcaaa80 JH |
2627 | |
2628 | case 2: | |
2629 | switch (standard_80387_constant_p (operands[1])) | |
2630 | { | |
2631 | case 1: | |
0f40f9f7 | 2632 | return "fldz"; |
8fcaaa80 | 2633 | case 2: |
0f40f9f7 | 2634 | return "fld1"; |
8fcaaa80 JH |
2635 | } |
2636 | break; | |
2637 | ||
2638 | case 3: case 4: | |
0f40f9f7 | 2639 | return "#"; |
8fcaaa80 JH |
2640 | } |
2641 | abort(); | |
0f40f9f7 | 2642 | } |
6ef67412 JH |
2643 | [(set_attr "type" "fmov,fmov,fmov,multi,multi") |
2644 | (set_attr "mode" "XF,XF,XF,SI,SI")]) | |
8fcaaa80 | 2645 | |
2b589241 JH |
2646 | (define_insn "*movtf_nointeger" |
2647 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o") | |
2648 | (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))] | |
2649 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
2650 | && optimize_size | |
2651 | && (reload_in_progress || reload_completed | |
2652 | || GET_CODE (operands[1]) != CONST_DOUBLE | |
3987b9db | 2653 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
2b589241 | 2654 | || memory_operand (operands[0], TFmode))" |
2b589241 JH |
2655 | { |
2656 | switch (which_alternative) | |
2657 | { | |
2658 | case 0: | |
2659 | if (REG_P (operands[1]) | |
2660 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2661 | return "fstp\t%y0"; |
2b589241 | 2662 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2663 | return "fld%z1\t%y1"; |
2b589241 | 2664 | else |
0f40f9f7 | 2665 | return "fst\t%y0"; |
2b589241 JH |
2666 | |
2667 | case 1: | |
2668 | /* There is no non-popping store to memory for XFmode. So if | |
2669 | we need one, follow the store with a load. */ | |
2670 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2671 | return "fstp%z0\t%y0\;fld%z0\t%y0"; |
2b589241 | 2672 | else |
0f40f9f7 | 2673 | return "fstp%z0\t%y0"; |
2b589241 JH |
2674 | |
2675 | case 2: | |
2676 | switch (standard_80387_constant_p (operands[1])) | |
2677 | { | |
2678 | case 1: | |
0f40f9f7 | 2679 | return "fldz"; |
2b589241 | 2680 | case 2: |
0f40f9f7 | 2681 | return "fld1"; |
2b589241 JH |
2682 | } |
2683 | break; | |
2684 | ||
2685 | case 3: case 4: | |
0f40f9f7 | 2686 | return "#"; |
2b589241 JH |
2687 | } |
2688 | abort(); | |
0f40f9f7 | 2689 | } |
2b589241 JH |
2690 | [(set_attr "type" "fmov,fmov,fmov,multi,multi") |
2691 | (set_attr "mode" "XF,XF,XF,SI,SI")]) | |
2692 | ||
8fcaaa80 JH |
2693 | (define_insn "*movxf_integer" |
2694 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o") | |
2695 | (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))] | |
1b0c37d7 | 2696 | "!TARGET_64BIT |
d7a29404 | 2697 | && !optimize_size |
1b0c37d7 | 2698 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
d7a29404 JH |
2699 | && (reload_in_progress || reload_completed |
2700 | || GET_CODE (operands[1]) != CONST_DOUBLE | |
2701 | || memory_operand (operands[0], XFmode))" | |
4fb21e90 | 2702 | { |
e075ae69 | 2703 | switch (which_alternative) |
4fb21e90 | 2704 | { |
e075ae69 | 2705 | case 0: |
0c174a68 AB |
2706 | if (REG_P (operands[1]) |
2707 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2708 | return "fstp\t%y0"; |
e075ae69 | 2709 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2710 | return "fld%z1\t%y1"; |
4fb21e90 | 2711 | else |
0f40f9f7 | 2712 | return "fst\t%y0"; |
4fb21e90 | 2713 | |
e075ae69 RH |
2714 | case 1: |
2715 | /* There is no non-popping store to memory for XFmode. So if | |
2716 | we need one, follow the store with a load. */ | |
2717 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2718 | return "fstp%z0\t%y0\;fld%z0\t%y0"; |
e075ae69 | 2719 | else |
0f40f9f7 | 2720 | return "fstp%z0\t%y0"; |
2f17722a | 2721 | |
e075ae69 RH |
2722 | case 2: |
2723 | switch (standard_80387_constant_p (operands[1])) | |
2724 | { | |
2725 | case 1: | |
0f40f9f7 | 2726 | return "fldz"; |
e075ae69 | 2727 | case 2: |
0f40f9f7 | 2728 | return "fld1"; |
e075ae69 RH |
2729 | } |
2730 | break; | |
467403ca RH |
2731 | |
2732 | case 3: case 4: | |
0f40f9f7 | 2733 | return "#"; |
4fb21e90 | 2734 | } |
e075ae69 | 2735 | abort(); |
0f40f9f7 | 2736 | } |
6ef67412 JH |
2737 | [(set_attr "type" "fmov,fmov,fmov,multi,multi") |
2738 | (set_attr "mode" "XF,XF,XF,SI,SI")]) | |
4fb21e90 | 2739 | |
2b589241 JH |
2740 | (define_insn "*movtf_integer" |
2741 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o") | |
2742 | (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))] | |
2743 | "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) | |
2744 | && !optimize_size | |
2745 | && (reload_in_progress || reload_completed | |
2746 | || GET_CODE (operands[1]) != CONST_DOUBLE | |
3987b9db | 2747 | || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) |
2b589241 | 2748 | || memory_operand (operands[0], TFmode))" |
2b589241 JH |
2749 | { |
2750 | switch (which_alternative) | |
2751 | { | |
2752 | case 0: | |
2753 | if (REG_P (operands[1]) | |
2754 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2755 | return "fstp\t%y0"; |
2b589241 | 2756 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 2757 | return "fld%z1\t%y1"; |
2b589241 | 2758 | else |
0f40f9f7 | 2759 | return "fst\t%y0"; |
2b589241 JH |
2760 | |
2761 | case 1: | |
2762 | /* There is no non-popping store to memory for XFmode. So if | |
2763 | we need one, follow the store with a load. */ | |
2764 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 2765 | return "fstp%z0\t%y0\;fld%z0\t%y0"; |
2b589241 | 2766 | else |
0f40f9f7 | 2767 | return "fstp%z0\t%y0"; |
2b589241 JH |
2768 | |
2769 | case 2: | |
2770 | switch (standard_80387_constant_p (operands[1])) | |
2771 | { | |
2772 | case 1: | |
0f40f9f7 | 2773 | return "fldz"; |
2b589241 | 2774 | case 2: |
0f40f9f7 | 2775 | return "fld1"; |
2b589241 JH |
2776 | } |
2777 | break; | |
2778 | ||
2779 | case 3: case 4: | |
0f40f9f7 | 2780 | return "#"; |
2b589241 JH |
2781 | } |
2782 | abort(); | |
0f40f9f7 | 2783 | } |
2b589241 JH |
2784 | [(set_attr "type" "fmov,fmov,fmov,multi,multi") |
2785 | (set_attr "mode" "XF,XF,XF,SI,SI")]) | |
2786 | ||
467403ca | 2787 | (define_split |
2b589241 JH |
2788 | [(set (match_operand 0 "nonimmediate_operand" "") |
2789 | (match_operand 1 "general_operand" ""))] | |
2450a057 | 2790 | "reload_completed |
8fcaaa80 | 2791 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) |
2b589241 | 2792 | && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode) |
446988df | 2793 | && ! (ANY_FP_REG_P (operands[0]) || |
8fcaaa80 | 2794 | (GET_CODE (operands[0]) == SUBREG |
446988df JH |
2795 | && ANY_FP_REG_P (SUBREG_REG (operands[0])))) |
2796 | && ! (ANY_FP_REG_P (operands[1]) || | |
8fcaaa80 | 2797 | (GET_CODE (operands[1]) == SUBREG |
446988df | 2798 | && ANY_FP_REG_P (SUBREG_REG (operands[1]))))" |
26e5b205 JH |
2799 | [(const_int 0)] |
2800 | "ix86_split_long_move (operands); DONE;") | |
467403ca | 2801 | |
d7a29404 | 2802 | (define_split |
2b589241 JH |
2803 | [(set (match_operand 0 "register_operand" "") |
2804 | (match_operand 1 "memory_operand" ""))] | |
d7a29404 JH |
2805 | "reload_completed |
2806 | && GET_CODE (operands[1]) == MEM | |
2b04e52b JH |
2807 | && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode |
2808 | || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode) | |
d7a29404 JH |
2809 | && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF |
2810 | && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)) | |
2b04e52b JH |
2811 | && (!(SSE_REG_P (operands[0]) || |
2812 | (GET_CODE (operands[0]) == SUBREG | |
2813 | && SSE_REG_P (SUBREG_REG (operands[0])))) | |
2814 | || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0)))) | |
2815 | && (!(FP_REG_P (operands[0]) || | |
2816 | (GET_CODE (operands[0]) == SUBREG | |
2817 | && FP_REG_P (SUBREG_REG (operands[0])))) | |
2818 | || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))" | |
d7a29404 JH |
2819 | [(set (match_dup 0) |
2820 | (match_dup 1))] | |
2821 | "operands[1] = get_pool_constant (XEXP (operands[1], 0));") | |
2822 | ||
e075ae69 RH |
2823 | (define_insn "swapxf" |
2824 | [(set (match_operand:XF 0 "register_operand" "+f") | |
2825 | (match_operand:XF 1 "register_operand" "+f")) | |
0be5d99f MM |
2826 | (set (match_dup 1) |
2827 | (match_dup 0))] | |
2828 | "" | |
0be5d99f MM |
2829 | { |
2830 | if (STACK_TOP_P (operands[0])) | |
0f40f9f7 | 2831 | return "fxch\t%1"; |
0be5d99f | 2832 | else |
0f40f9f7 ZW |
2833 | return "fxch\t%0"; |
2834 | } | |
0b5107cf | 2835 | [(set_attr "type" "fxch") |
6ef67412 | 2836 | (set_attr "mode" "XF")]) |
2b589241 JH |
2837 | |
2838 | (define_insn "swaptf" | |
2839 | [(set (match_operand:TF 0 "register_operand" "+f") | |
2840 | (match_operand:TF 1 "register_operand" "+f")) | |
2841 | (set (match_dup 1) | |
2842 | (match_dup 0))] | |
2843 | "" | |
2b589241 JH |
2844 | { |
2845 | if (STACK_TOP_P (operands[0])) | |
0f40f9f7 | 2846 | return "fxch\t%1"; |
2b589241 | 2847 | else |
0f40f9f7 ZW |
2848 | return "fxch\t%0"; |
2849 | } | |
2b589241 JH |
2850 | [(set_attr "type" "fxch") |
2851 | (set_attr "mode" "XF")]) | |
886c62d1 | 2852 | \f |
e075ae69 | 2853 | ;; Zero extension instructions |
886c62d1 | 2854 | |
8f7661f2 JH |
2855 | (define_expand "zero_extendhisi2" |
2856 | [(set (match_operand:SI 0 "register_operand" "") | |
2857 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
d626200a | 2858 | "" |
e075ae69 | 2859 | { |
8f7661f2 | 2860 | if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) |
2ae0f82c | 2861 | { |
8f7661f2 JH |
2862 | operands[1] = force_reg (HImode, operands[1]); |
2863 | emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1])); | |
2864 | DONE; | |
2ae0f82c | 2865 | } |
0f40f9f7 | 2866 | }) |
886c62d1 | 2867 | |
8f7661f2 JH |
2868 | (define_insn "zero_extendhisi2_and" |
2869 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2870 | (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) | |
e075ae69 | 2871 | (clobber (reg:CC 17))] |
8f7661f2 JH |
2872 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" |
2873 | "#" | |
6ef67412 JH |
2874 | [(set_attr "type" "alu1") |
2875 | (set_attr "mode" "SI")]) | |
2ae0f82c SC |
2876 | |
2877 | (define_split | |
2878 | [(set (match_operand:SI 0 "register_operand" "") | |
8f7661f2 | 2879 | (zero_extend:SI (match_operand:HI 1 "register_operand" ""))) |
e075ae69 | 2880 | (clobber (reg:CC 17))] |
8f7661f2 JH |
2881 | "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" |
2882 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535))) | |
e075ae69 | 2883 | (clobber (reg:CC 17))])] |
d626200a JL |
2884 | "") |
2885 | ||
8f7661f2 JH |
2886 | (define_insn "*zero_extendhisi2_movzwl" |
2887 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2888 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] | |
2889 | "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" | |
0f40f9f7 | 2890 | "movz{wl|x}\t{%1, %0|%0, %1}" |
6ef67412 JH |
2891 | [(set_attr "type" "imovx") |
2892 | (set_attr "mode" "SI")]) | |
8f7661f2 JH |
2893 | |
2894 | (define_expand "zero_extendqihi2" | |
2895 | [(parallel | |
2896 | [(set (match_operand:HI 0 "register_operand" "") | |
2897 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) | |
2898 | (clobber (reg:CC 17))])] | |
e075ae69 | 2899 | "" |
8f7661f2 JH |
2900 | "") |
2901 | ||
2902 | (define_insn "*zero_extendqihi2_and" | |
2903 | [(set (match_operand:HI 0 "register_operand" "=r,?&q") | |
2904 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) | |
2905 | (clobber (reg:CC 17))] | |
2906 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" | |
2907 | "#" | |
6ef67412 JH |
2908 | [(set_attr "type" "alu1") |
2909 | (set_attr "mode" "HI")]) | |
8f7661f2 JH |
2910 | |
2911 | (define_insn "*zero_extendqihi2_movzbw_and" | |
2912 | [(set (match_operand:HI 0 "register_operand" "=r,r") | |
2913 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) | |
2914 | (clobber (reg:CC 17))] | |
2915 | "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" | |
2916 | "#" | |
6ef67412 JH |
2917 | [(set_attr "type" "imovx,alu1") |
2918 | (set_attr "mode" "HI")]) | |
886c62d1 | 2919 | |
8f7661f2 JH |
2920 | (define_insn "*zero_extendqihi2_movzbw" |
2921 | [(set (match_operand:HI 0 "register_operand" "=r") | |
2922 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))] | |
1c27d4b2 | 2923 | "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed" |
0f40f9f7 | 2924 | "movz{bw|x}\t{%1, %0|%0, %1}" |
6ef67412 JH |
2925 | [(set_attr "type" "imovx") |
2926 | (set_attr "mode" "HI")]) | |
8f7661f2 JH |
2927 | |
2928 | ;; For the movzbw case strip only the clobber | |
2ae0f82c SC |
2929 | (define_split |
2930 | [(set (match_operand:HI 0 "register_operand" "") | |
e075ae69 RH |
2931 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) |
2932 | (clobber (reg:CC 17))] | |
8f7661f2 JH |
2933 | "reload_completed |
2934 | && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) | |
1a06f5fe | 2935 | && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" |
8f7661f2 JH |
2936 | [(set (match_operand:HI 0 "register_operand" "") |
2937 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]) | |
2ae0f82c | 2938 | |
8f7661f2 JH |
2939 | ;; When source and destination does not overlap, clear destination |
2940 | ;; first and then do the movb | |
2ae0f82c SC |
2941 | (define_split |
2942 | [(set (match_operand:HI 0 "register_operand" "") | |
8f7661f2 | 2943 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) |
e075ae69 RH |
2944 | (clobber (reg:CC 17))] |
2945 | "reload_completed | |
1a06f5fe | 2946 | && ANY_QI_REG_P (operands[0]) |
8f7661f2 JH |
2947 | && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) |
2948 | && !reg_overlap_mentioned_p (operands[0], operands[1])" | |
2949 | [(set (match_dup 0) (const_int 0)) | |
2950 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2951 | "operands[2] = gen_lowpart (QImode, operands[0]);") | |
2ae0f82c | 2952 | |
8f7661f2 | 2953 | ;; Rest is handled by single and. |
2ae0f82c SC |
2954 | (define_split |
2955 | [(set (match_operand:HI 0 "register_operand" "") | |
e075ae69 RH |
2956 | (zero_extend:HI (match_operand:QI 1 "register_operand" ""))) |
2957 | (clobber (reg:CC 17))] | |
2958 | "reload_completed | |
8f7661f2 JH |
2959 | && true_regnum (operands[0]) == true_regnum (operands[1])" |
2960 | [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255))) | |
e075ae69 | 2961 | (clobber (reg:CC 17))])] |
d626200a JL |
2962 | "") |
2963 | ||
8f7661f2 JH |
2964 | (define_expand "zero_extendqisi2" |
2965 | [(parallel | |
2966 | [(set (match_operand:SI 0 "register_operand" "") | |
2967 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) | |
2968 | (clobber (reg:CC 17))])] | |
e075ae69 | 2969 | "" |
8f7661f2 JH |
2970 | "") |
2971 | ||
2972 | (define_insn "*zero_extendqisi2_and" | |
2973 | [(set (match_operand:SI 0 "register_operand" "=r,?&q") | |
2974 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) | |
2975 | (clobber (reg:CC 17))] | |
2976 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" | |
2977 | "#" | |
6ef67412 JH |
2978 | [(set_attr "type" "alu1") |
2979 | (set_attr "mode" "SI")]) | |
8f7661f2 JH |
2980 | |
2981 | (define_insn "*zero_extendqisi2_movzbw_and" | |
2982 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
2983 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) | |
2984 | (clobber (reg:CC 17))] | |
2985 | "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" | |
2986 | "#" | |
6ef67412 JH |
2987 | [(set_attr "type" "imovx,alu1") |
2988 | (set_attr "mode" "SI")]) | |
2ae0f82c | 2989 | |
8f7661f2 JH |
2990 | (define_insn "*zero_extendqisi2_movzbw" |
2991 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2992 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] | |
2993 | "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed" | |
0f40f9f7 | 2994 | "movz{bl|x}\t{%1, %0|%0, %1}" |
6ef67412 JH |
2995 | [(set_attr "type" "imovx") |
2996 | (set_attr "mode" "SI")]) | |
8f7661f2 JH |
2997 | |
2998 | ;; For the movzbl case strip only the clobber | |
2999 | (define_split | |
3000 | [(set (match_operand:SI 0 "register_operand" "") | |
3001 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) | |
3002 | (clobber (reg:CC 17))] | |
3003 | "reload_completed | |
3004 | && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) | |
1a06f5fe | 3005 | && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" |
8f7661f2 JH |
3006 | [(set (match_dup 0) |
3007 | (zero_extend:SI (match_dup 1)))]) | |
3008 | ||
3009 | ;; When source and destination does not overlap, clear destination | |
3010 | ;; first and then do the movb | |
2ae0f82c SC |
3011 | (define_split |
3012 | [(set (match_operand:SI 0 "register_operand" "") | |
e075ae69 RH |
3013 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) |
3014 | (clobber (reg:CC 17))] | |
3015 | "reload_completed | |
1a06f5fe JH |
3016 | && ANY_QI_REG_P (operands[0]) |
3017 | && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM) | |
8f7661f2 | 3018 | && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) |
e075ae69 | 3019 | && !reg_overlap_mentioned_p (operands[0], operands[1])" |
8f7661f2 JH |
3020 | [(set (match_dup 0) (const_int 0)) |
3021 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
3022 | "operands[2] = gen_lowpart (QImode, operands[0]);") | |
2ae0f82c | 3023 | |
8f7661f2 | 3024 | ;; Rest is handled by single and. |
2ae0f82c SC |
3025 | (define_split |
3026 | [(set (match_operand:SI 0 "register_operand" "") | |
e075ae69 RH |
3027 | (zero_extend:SI (match_operand:QI 1 "register_operand" ""))) |
3028 | (clobber (reg:CC 17))] | |
3029 | "reload_completed | |
8f7661f2 JH |
3030 | && true_regnum (operands[0]) == true_regnum (operands[1])" |
3031 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255))) | |
e075ae69 RH |
3032 | (clobber (reg:CC 17))])] |
3033 | "") | |
2ae0f82c | 3034 | |
e075ae69 | 3035 | ;; %%% Kill me once multi-word ops are sane. |
123bf9e3 JH |
3036 | (define_expand "zero_extendsidi2" |
3037 | [(set (match_operand:DI 0 "register_operand" "=r") | |
3038 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))] | |
3039 | "" | |
3040 | "if (!TARGET_64BIT) | |
3041 | { | |
3042 | emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1])); | |
3043 | DONE; | |
3044 | } | |
3045 | ") | |
3046 | ||
3047 | (define_insn "zero_extendsidi2_32" | |
bb62e19a | 3048 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o") |
123bf9e3 | 3049 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r"))) |
e075ae69 | 3050 | (clobber (reg:CC 17))] |
123bf9e3 | 3051 | "!TARGET_64BIT" |
6ef67412 JH |
3052 | "#" |
3053 | [(set_attr "mode" "SI")]) | |
2ae0f82c | 3054 | |
123bf9e3 JH |
3055 | (define_insn "zero_extendsidi2_rex64" |
3056 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") | |
3057 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))] | |
3058 | "TARGET_64BIT" | |
3059 | "@ | |
0f40f9f7 | 3060 | mov\t{%k1, %k0|%k0, %k1} |
123bf9e3 JH |
3061 | #" |
3062 | [(set_attr "type" "imovx,imov") | |
3063 | (set_attr "mode" "SI,DI")]) | |
3064 | ||
3065 | (define_split | |
3066 | [(set (match_operand:DI 0 "memory_operand" "") | |
3067 | (zero_extend:DI (match_dup 0)))] | |
1b0c37d7 | 3068 | "TARGET_64BIT" |
123bf9e3 JH |
3069 | [(set (match_dup 4) (const_int 0))] |
3070 | "split_di (&operands[0], 1, &operands[3], &operands[4]);") | |
3071 | ||
bb62e19a JH |
3072 | (define_split |
3073 | [(set (match_operand:DI 0 "register_operand" "") | |
e075ae69 RH |
3074 | (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) |
3075 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
3076 | "!TARGET_64BIT && reload_completed |
3077 | && true_regnum (operands[0]) == true_regnum (operands[1])" | |
591702de | 3078 | [(set (match_dup 4) (const_int 0))] |
bb62e19a JH |
3079 | "split_di (&operands[0], 1, &operands[3], &operands[4]);") |
3080 | ||
3081 | (define_split | |
3082 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
e075ae69 RH |
3083 | (zero_extend:DI (match_operand:SI 1 "general_operand" ""))) |
3084 | (clobber (reg:CC 17))] | |
1b0c37d7 | 3085 | "!TARGET_64BIT && reload_completed" |
bb62e19a | 3086 | [(set (match_dup 3) (match_dup 1)) |
591702de | 3087 | (set (match_dup 4) (const_int 0))] |
bb62e19a | 3088 | "split_di (&operands[0], 1, &operands[3], &operands[4]);") |
123bf9e3 JH |
3089 | |
3090 | (define_insn "zero_extendhidi2" | |
3091 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
3092 | (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] | |
3093 | "TARGET_64BIT" | |
3094 | "@ | |
0f40f9f7 ZW |
3095 | movz{wl|x}\t{%1, %k0|%k0, %1} |
3096 | movz{wq|x}\t{%1, %0|%0, %1}" | |
123bf9e3 JH |
3097 | [(set_attr "type" "imovx") |
3098 | (set_attr "mode" "SI,DI")]) | |
3099 | ||
3100 | (define_insn "zero_extendqidi2" | |
3101 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
3102 | (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))] | |
3103 | "TARGET_64BIT" | |
3104 | "@ | |
0f40f9f7 ZW |
3105 | movz{bl|x}\t{%1, %k0|%k0, %1} |
3106 | movz{bq|x}\t{%1, %0|%0, %1}" | |
123bf9e3 JH |
3107 | [(set_attr "type" "imovx") |
3108 | (set_attr "mode" "SI,DI")]) | |
886c62d1 | 3109 | \f |
e075ae69 | 3110 | ;; Sign extension instructions |
886c62d1 | 3111 | |
123bf9e3 JH |
3112 | (define_expand "extendsidi2" |
3113 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
3114 | (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) | |
3115 | (clobber (reg:CC 17)) | |
3116 | (clobber (match_scratch:SI 2 ""))])] | |
3117 | "" | |
123bf9e3 JH |
3118 | { |
3119 | if (TARGET_64BIT) | |
3120 | { | |
3121 | emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1])); | |
3122 | DONE; | |
3123 | } | |
0f40f9f7 | 3124 | }) |
123bf9e3 JH |
3125 | |
3126 | (define_insn "*extendsidi2_1" | |
e075ae69 RH |
3127 | [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o") |
3128 | (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r"))) | |
6b29b0e2 JW |
3129 | (clobber (reg:CC 17)) |
3130 | (clobber (match_scratch:SI 2 "=X,X,X,&r"))] | |
123bf9e3 | 3131 | "!TARGET_64BIT" |
724d568a JH |
3132 | "#") |
3133 | ||
123bf9e3 JH |
3134 | (define_insn "extendsidi2_rex64" |
3135 | [(set (match_operand:DI 0 "register_operand" "=*a,r") | |
3136 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))] | |
3137 | "TARGET_64BIT" | |
3138 | "@ | |
3139 | {cltq|cdqe} | |
0f40f9f7 | 3140 | movs{lq|x}\t{%1,%0|%0, %1}" |
123bf9e3 JH |
3141 | [(set_attr "type" "imovx") |
3142 | (set_attr "mode" "DI") | |
3143 | (set_attr "prefix_0f" "0") | |
3144 | (set_attr "modrm" "0,1")]) | |
3145 | ||
3146 | (define_insn "extendhidi2" | |
3147 | [(set (match_operand:DI 0 "register_operand" "=r") | |
3148 | (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))] | |
3149 | "TARGET_64BIT" | |
0f40f9f7 | 3150 | "movs{wq|x}\t{%1,%0|%0, %1}" |
123bf9e3 JH |
3151 | [(set_attr "type" "imovx") |
3152 | (set_attr "mode" "DI")]) | |
3153 | ||
3154 | (define_insn "extendqidi2" | |
3155 | [(set (match_operand:DI 0 "register_operand" "=r") | |
3156 | (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))] | |
3157 | "TARGET_64BIT" | |
0f40f9f7 | 3158 | "movs{bq|x}\t{%1,%0|%0, %1}" |
123bf9e3 JH |
3159 | [(set_attr "type" "imovx") |
3160 | (set_attr "mode" "DI")]) | |
3161 | ||
724d568a JH |
3162 | ;; Extend to memory case when source register does die. |
3163 | (define_split | |
3164 | [(set (match_operand:DI 0 "memory_operand" "") | |
3165 | (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) | |
6b29b0e2 JW |
3166 | (clobber (reg:CC 17)) |
3167 | (clobber (match_operand:SI 2 "register_operand" ""))] | |
d7a29404 | 3168 | "(reload_completed |
724d568a JH |
3169 | && dead_or_set_p (insn, operands[1]) |
3170 | && !reg_mentioned_p (operands[1], operands[0]))" | |
3171 | [(set (match_dup 3) (match_dup 1)) | |
e075ae69 RH |
3172 | (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31))) |
3173 | (clobber (reg:CC 17))]) | |
724d568a JH |
3174 | (set (match_dup 4) (match_dup 1))] |
3175 | "split_di (&operands[0], 1, &operands[3], &operands[4]);") | |
3176 | ||
3177 | ;; Extend to memory case when source register does not die. | |
3178 | (define_split | |
3179 | [(set (match_operand:DI 0 "memory_operand" "") | |
3180 | (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) | |
6b29b0e2 JW |
3181 | (clobber (reg:CC 17)) |
3182 | (clobber (match_operand:SI 2 "register_operand" ""))] | |
d7a29404 | 3183 | "reload_completed" |
724d568a | 3184 | [(const_int 0)] |
9c530261 | 3185 | { |
724d568a JH |
3186 | split_di (&operands[0], 1, &operands[3], &operands[4]); |
3187 | ||
3188 | emit_move_insn (operands[3], operands[1]); | |
3189 | ||
3190 | /* Generate a cltd if possible and doing so it profitable. */ | |
3191 | if (true_regnum (operands[1]) == 0 | |
3192 | && true_regnum (operands[2]) == 1 | |
e075ae69 | 3193 | && (optimize_size || TARGET_USE_CLTD)) |
71a247f0 | 3194 | { |
e075ae69 | 3195 | emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31))); |
724d568a JH |
3196 | } |
3197 | else | |
3198 | { | |
3199 | emit_move_insn (operands[2], operands[1]); | |
e075ae69 | 3200 | emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31))); |
71a247f0 | 3201 | } |
724d568a JH |
3202 | emit_move_insn (operands[4], operands[2]); |
3203 | DONE; | |
0f40f9f7 | 3204 | }) |
9c530261 | 3205 | |
724d568a JH |
3206 | ;; Extend to register case. Optimize case where source and destination |
3207 | ;; registers match and cases where we can use cltd. | |
3208 | (define_split | |
3209 | [(set (match_operand:DI 0 "register_operand" "") | |
3210 | (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) | |
6b29b0e2 JW |
3211 | (clobber (reg:CC 17)) |
3212 | (clobber (match_scratch:SI 2 ""))] | |
724d568a JH |
3213 | "reload_completed" |
3214 | [(const_int 0)] | |
724d568a JH |
3215 | { |
3216 | split_di (&operands[0], 1, &operands[3], &operands[4]); | |
3217 | ||
3218 | if (true_regnum (operands[3]) != true_regnum (operands[1])) | |
3219 | emit_move_insn (operands[3], operands[1]); | |
9c530261 | 3220 | |
724d568a JH |
3221 | /* Generate a cltd if possible and doing so it profitable. */ |
3222 | if (true_regnum (operands[3]) == 0 | |
e075ae69 | 3223 | && (optimize_size || TARGET_USE_CLTD)) |
724d568a | 3224 | { |
e075ae69 | 3225 | emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31))); |
724d568a JH |
3226 | DONE; |
3227 | } | |
3228 | ||
3229 | if (true_regnum (operands[4]) != true_regnum (operands[1])) | |
3230 | emit_move_insn (operands[4], operands[1]); | |
3231 | ||
e075ae69 | 3232 | emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31))); |
724d568a | 3233 | DONE; |
0f40f9f7 | 3234 | }) |
886c62d1 | 3235 | |
886c62d1 | 3236 | (define_insn "extendhisi2" |
e075ae69 RH |
3237 | [(set (match_operand:SI 0 "register_operand" "=*a,r") |
3238 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))] | |
886c62d1 | 3239 | "" |
886c62d1 | 3240 | { |
6ef67412 | 3241 | switch (get_attr_prefix_0f (insn)) |
e075ae69 | 3242 | { |
6ef67412 | 3243 | case 0: |
0f40f9f7 | 3244 | return "{cwtl|cwde}"; |
e075ae69 | 3245 | default: |
0f40f9f7 | 3246 | return "movs{wl|x}\t{%1,%0|%0, %1}"; |
e075ae69 | 3247 | } |
0f40f9f7 | 3248 | } |
e075ae69 | 3249 | [(set_attr "type" "imovx") |
6ef67412 JH |
3250 | (set_attr "mode" "SI") |
3251 | (set (attr "prefix_0f") | |
3252 | ;; movsx is short decodable while cwtl is vector decoded. | |
3253 | (if_then_else (and (eq_attr "cpu" "!k6") | |
3254 | (eq_attr "alternative" "0")) | |
3255 | (const_string "0") | |
3256 | (const_string "1"))) | |
3257 | (set (attr "modrm") | |
3258 | (if_then_else (eq_attr "prefix_0f" "0") | |
3259 | (const_string "0") | |
3260 | (const_string "1")))]) | |
886c62d1 | 3261 | |
123bf9e3 JH |
3262 | (define_insn "*extendhisi2_zext" |
3263 | [(set (match_operand:DI 0 "register_operand" "=*a,r") | |
3264 | (zero_extend:DI | |
3265 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))] | |
3266 | "TARGET_64BIT" | |
123bf9e3 JH |
3267 | { |
3268 | switch (get_attr_prefix_0f (insn)) | |
3269 | { | |
3270 | case 0: | |
0f40f9f7 | 3271 | return "{cwtl|cwde}"; |
123bf9e3 | 3272 | default: |
0f40f9f7 | 3273 | return "movs{wl|x}\t{%1,%k0|%k0, %1}"; |
123bf9e3 | 3274 | } |
0f40f9f7 | 3275 | } |
123bf9e3 JH |
3276 | [(set_attr "type" "imovx") |
3277 | (set_attr "mode" "SI") | |
3278 | (set (attr "prefix_0f") | |
3279 | ;; movsx is short decodable while cwtl is vector decoded. | |
3280 | (if_then_else (and (eq_attr "cpu" "!k6") | |
3281 | (eq_attr "alternative" "0")) | |
3282 | (const_string "0") | |
3283 | (const_string "1"))) | |
3284 | (set (attr "modrm") | |
3285 | (if_then_else (eq_attr "prefix_0f" "0") | |
3286 | (const_string "0") | |
3287 | (const_string "1")))]) | |
3288 | ||
886c62d1 | 3289 | (define_insn "extendqihi2" |
e075ae69 RH |
3290 | [(set (match_operand:HI 0 "register_operand" "=*a,r") |
3291 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))] | |
886c62d1 | 3292 | "" |
886c62d1 | 3293 | { |
6ef67412 | 3294 | switch (get_attr_prefix_0f (insn)) |
e075ae69 | 3295 | { |
6ef67412 | 3296 | case 0: |
0f40f9f7 | 3297 | return "{cbtw|cbw}"; |
e075ae69 | 3298 | default: |
0f40f9f7 | 3299 | return "movs{bw|x}\t{%1,%0|%0, %1}"; |
e075ae69 | 3300 | } |
0f40f9f7 | 3301 | } |
e075ae69 | 3302 | [(set_attr "type" "imovx") |
6ef67412 JH |
3303 | (set_attr "mode" "HI") |
3304 | (set (attr "prefix_0f") | |
3305 | ;; movsx is short decodable while cwtl is vector decoded. | |
3306 | (if_then_else (and (eq_attr "cpu" "!k6") | |
3307 | (eq_attr "alternative" "0")) | |
3308 | (const_string "0") | |
3309 | (const_string "1"))) | |
3310 | (set (attr "modrm") | |
3311 | (if_then_else (eq_attr "prefix_0f" "0") | |
3312 | (const_string "0") | |
3313 | (const_string "1")))]) | |
886c62d1 JVA |
3314 | |
3315 | (define_insn "extendqisi2" | |
2ae0f82c SC |
3316 | [(set (match_operand:SI 0 "register_operand" "=r") |
3317 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] | |
886c62d1 | 3318 | "" |
0f40f9f7 | 3319 | "movs{bl|x}\t{%1,%0|%0, %1}" |
6ef67412 JH |
3320 | [(set_attr "type" "imovx") |
3321 | (set_attr "mode" "SI")]) | |
123bf9e3 JH |
3322 | |
3323 | (define_insn "*extendqisi2_zext" | |
3324 | [(set (match_operand:DI 0 "register_operand" "=r") | |
3325 | (zero_extend:DI | |
3326 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))] | |
3327 | "TARGET_64BIT" | |
0f40f9f7 | 3328 | "movs{bl|x}\t{%1,%k0|%k0, %1}" |
123bf9e3 JH |
3329 | [(set_attr "type" "imovx") |
3330 | (set_attr "mode" "SI")]) | |
886c62d1 JVA |
3331 | \f |
3332 | ;; Conversions between float and double. | |
3333 | ||
e075ae69 RH |
3334 | ;; These are all no-ops in the model used for the 80387. So just |
3335 | ;; emit moves. | |
6a4a5d95 | 3336 | |
e075ae69 | 3337 | ;; %%% Kill these when call knows how to work out a DFmode push earlier. |
6343a50e | 3338 | (define_insn "*dummy_extendsfdf2" |
e075ae69 | 3339 | [(set (match_operand:DF 0 "push_operand" "=<") |
42a0aa6f | 3340 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))] |
e075ae69 RH |
3341 | "0" |
3342 | "#") | |
6a4a5d95 JW |
3343 | |
3344 | (define_split | |
e075ae69 | 3345 | [(set (match_operand:DF 0 "push_operand" "") |
c3c637e3 GS |
3346 | (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] |
3347 | "!TARGET_64BIT" | |
e075ae69 RH |
3348 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) |
3349 | (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))]) | |
0fcad513 | 3350 | |
123bf9e3 JH |
3351 | (define_split |
3352 | [(set (match_operand:DF 0 "push_operand" "") | |
c3c637e3 GS |
3353 | (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] |
3354 | "TARGET_64BIT" | |
123bf9e3 JH |
3355 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) |
3356 | (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))]) | |
3357 | ||
6343a50e | 3358 | (define_insn "*dummy_extendsfxf2" |
e075ae69 RH |
3359 | [(set (match_operand:XF 0 "push_operand" "=<") |
3360 | (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))] | |
3361 | "0" | |
3362 | "#") | |
e4ad1003 JW |
3363 | |
3364 | (define_split | |
e075ae69 | 3365 | [(set (match_operand:XF 0 "push_operand" "") |
c3c637e3 GS |
3366 | (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))] |
3367 | "!TARGET_64BIT" | |
e075ae69 | 3368 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) |
2b589241 JH |
3369 | (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) |
3370 | ||
3371 | (define_insn "*dummy_extendsftf2" | |
3372 | [(set (match_operand:TF 0 "push_operand" "=<") | |
3373 | (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))] | |
3374 | "0" | |
3375 | "#") | |
3376 | ||
3377 | (define_split | |
3378 | [(set (match_operand:TF 0 "push_operand" "") | |
c3c637e3 GS |
3379 | (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))] |
3380 | "!TARGET_64BIT" | |
2b589241 | 3381 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) |
123bf9e3 JH |
3382 | (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))]) |
3383 | ||
3384 | (define_split | |
3385 | [(set (match_operand:TF 0 "push_operand" "") | |
c3c637e3 GS |
3386 | (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))] |
3387 | "TARGET_64BIT" | |
123bf9e3 JH |
3388 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) |
3389 | (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))]) | |
4fb21e90 | 3390 | |
6343a50e | 3391 | (define_insn "*dummy_extenddfxf2" |
e075ae69 RH |
3392 | [(set (match_operand:XF 0 "push_operand" "=<") |
3393 | (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))] | |
3394 | "0" | |
3395 | "#") | |
e4ad1003 JW |
3396 | |
3397 | (define_split | |
e075ae69 | 3398 | [(set (match_operand:XF 0 "push_operand" "") |
c3c637e3 GS |
3399 | (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))] |
3400 | "!TARGET_64BIT" | |
e075ae69 | 3401 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) |
123bf9e3 | 3402 | (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) |
2b589241 JH |
3403 | |
3404 | (define_insn "*dummy_extenddftf2" | |
3405 | [(set (match_operand:TF 0 "push_operand" "=<") | |
3406 | (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))] | |
3407 | "0" | |
3408 | "#") | |
3409 | ||
3410 | (define_split | |
3411 | [(set (match_operand:TF 0 "push_operand" "") | |
c3c637e3 GS |
3412 | (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))] |
3413 | "!TARGET_64BIT" | |
2b589241 JH |
3414 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) |
3415 | (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) | |
4fb21e90 | 3416 | |
123bf9e3 JH |
3417 | (define_split |
3418 | [(set (match_operand:TF 0 "push_operand" "") | |
c3c637e3 GS |
3419 | (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))] |
3420 | "TARGET_64BIT" | |
123bf9e3 | 3421 | [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) |
a2bafd20 | 3422 | (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))]) |
123bf9e3 | 3423 | |
f97d9ec3 JH |
3424 | (define_expand "extendsfdf2" |
3425 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
51286de6 | 3426 | (float_extend:DF (match_operand:SF 1 "general_operand" "")))] |
42a0aa6f | 3427 | "TARGET_80387 || TARGET_SSE2" |
f97d9ec3 | 3428 | { |
51286de6 RH |
3429 | /* ??? Needed for compress_float_constant since all fp constants |
3430 | are LEGITIMATE_CONSTANT_P. */ | |
3431 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
3432 | operands[1] = validize_mem (force_const_mem (SFmode, operands[1])); | |
f97d9ec3 | 3433 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
34289d57 | 3434 | operands[1] = force_reg (SFmode, operands[1]); |
0f40f9f7 | 3435 | }) |
f97d9ec3 JH |
3436 | |
3437 | (define_insn "*extendsfdf2_1" | |
a811cc63 JH |
3438 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f") |
3439 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))] | |
42a0aa6f | 3440 | "(TARGET_80387 || TARGET_SSE2) |
f97d9ec3 | 3441 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" |
4fb21e90 | 3442 | { |
e075ae69 | 3443 | switch (which_alternative) |
4fb21e90 | 3444 | { |
e075ae69 | 3445 | case 0: |
0c174a68 AB |
3446 | if (REG_P (operands[1]) |
3447 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3448 | return "fstp\t%y0"; |
e075ae69 | 3449 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 3450 | return "fld%z1\t%y1"; |
e075ae69 | 3451 | else |
0f40f9f7 | 3452 | return "fst\t%y0"; |
886c62d1 | 3453 | |
e075ae69 RH |
3454 | case 1: |
3455 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3456 | return "fstp%z0\t%y0"; |
10195bd8 | 3457 | |
e075ae69 | 3458 | else |
0f40f9f7 | 3459 | return "fst%z0\t%y0"; |
42a0aa6f | 3460 | case 2: |
0f40f9f7 | 3461 | return "cvtss2sd\t{%1, %0|%0, %1}"; |
4fb21e90 | 3462 | |
e075ae69 RH |
3463 | default: |
3464 | abort (); | |
3465 | } | |
0f40f9f7 | 3466 | } |
3d34cd91 | 3467 | [(set_attr "type" "fmov,fmov,ssecvt") |
a811cc63 | 3468 | (set_attr "mode" "SF,XF,DF")]) |
42a0aa6f JH |
3469 | |
3470 | (define_insn "*extendsfdf2_1_sse_only" | |
3471 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
3472 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))] | |
3473 | "!TARGET_80387 && TARGET_SSE2 | |
3474 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
0f40f9f7 | 3475 | "cvtss2sd\t{%1, %0|%0, %1}" |
3d34cd91 | 3476 | [(set_attr "type" "ssecvt") |
42a0aa6f | 3477 | (set_attr "mode" "DF")]) |
e075ae69 | 3478 | |
f97d9ec3 JH |
3479 | (define_expand "extendsfxf2" |
3480 | [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
51286de6 | 3481 | (float_extend:XF (match_operand:SF 1 "general_operand" "")))] |
1b0c37d7 | 3482 | "!TARGET_64BIT && TARGET_80387" |
f97d9ec3 | 3483 | { |
51286de6 RH |
3484 | /* ??? Needed for compress_float_constant since all fp constants |
3485 | are LEGITIMATE_CONSTANT_P. */ | |
3486 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
3487 | operands[1] = validize_mem (force_const_mem (SFmode, operands[1])); | |
f97d9ec3 | 3488 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
34289d57 | 3489 | operands[1] = force_reg (SFmode, operands[1]); |
0f40f9f7 | 3490 | }) |
f97d9ec3 JH |
3491 | |
3492 | (define_insn "*extendsfxf2_1" | |
e075ae69 RH |
3493 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") |
3494 | (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] | |
1b0c37d7 | 3495 | "!TARGET_64BIT && TARGET_80387 |
f97d9ec3 | 3496 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" |
10195bd8 | 3497 | { |
e075ae69 RH |
3498 | switch (which_alternative) |
3499 | { | |
3500 | case 0: | |
0c174a68 AB |
3501 | if (REG_P (operands[1]) |
3502 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3503 | return "fstp\t%y0"; |
e075ae69 | 3504 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 3505 | return "fld%z1\t%y1"; |
e075ae69 | 3506 | else |
0f40f9f7 | 3507 | return "fst\t%y0"; |
886c62d1 | 3508 | |
e075ae69 RH |
3509 | case 1: |
3510 | /* There is no non-popping store to memory for XFmode. So if | |
3511 | we need one, follow the store with a load. */ | |
3512 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3513 | return "fstp%z0\t%y0\n\tfld%z0\t%y0"; |
e075ae69 | 3514 | else |
0f40f9f7 | 3515 | return "fstp%z0\t%y0"; |
886c62d1 | 3516 | |
e075ae69 RH |
3517 | default: |
3518 | abort (); | |
3519 | } | |
0f40f9f7 | 3520 | } |
6ef67412 JH |
3521 | [(set_attr "type" "fmov") |
3522 | (set_attr "mode" "SF,XF")]) | |
886c62d1 | 3523 | |
2b589241 JH |
3524 | (define_expand "extendsftf2" |
3525 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
51286de6 | 3526 | (float_extend:TF (match_operand:SF 1 "general_operand" "")))] |
2b589241 | 3527 | "TARGET_80387" |
2b589241 | 3528 | { |
51286de6 RH |
3529 | /* ??? Needed for compress_float_constant since all fp constants |
3530 | are LEGITIMATE_CONSTANT_P. */ | |
3531 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
3532 | operands[1] = validize_mem (force_const_mem (SFmode, operands[1])); | |
2b589241 JH |
3533 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
3534 | operands[1] = force_reg (SFmode, operands[1]); | |
0f40f9f7 | 3535 | }) |
2b589241 JH |
3536 | |
3537 | (define_insn "*extendsftf2_1" | |
3538 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m") | |
3539 | (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] | |
3540 | "TARGET_80387 | |
3541 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
2b589241 JH |
3542 | { |
3543 | switch (which_alternative) | |
3544 | { | |
3545 | case 0: | |
3546 | if (REG_P (operands[1]) | |
3547 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3548 | return "fstp\t%y0"; |
2b589241 | 3549 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 3550 | return "fld%z1\t%y1"; |
2b589241 | 3551 | else |
0f40f9f7 | 3552 | return "fst\t%y0"; |
2b589241 JH |
3553 | |
3554 | case 1: | |
3555 | /* There is no non-popping store to memory for XFmode. So if | |
3556 | we need one, follow the store with a load. */ | |
3557 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3558 | return "fstp%z0\t%y0\n\tfld%z0\t%y0"; |
2b589241 | 3559 | else |
0f40f9f7 | 3560 | return "fstp%z0\t%y0"; |
2b589241 JH |
3561 | |
3562 | default: | |
3563 | abort (); | |
3564 | } | |
0f40f9f7 | 3565 | } |
2b589241 JH |
3566 | [(set_attr "type" "fmov") |
3567 | (set_attr "mode" "SF,XF")]) | |
3568 | ||
f97d9ec3 JH |
3569 | (define_expand "extenddfxf2" |
3570 | [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
51286de6 | 3571 | (float_extend:XF (match_operand:DF 1 "general_operand" "")))] |
1b0c37d7 | 3572 | "!TARGET_64BIT && TARGET_80387" |
f97d9ec3 | 3573 | { |
51286de6 RH |
3574 | /* ??? Needed for compress_float_constant since all fp constants |
3575 | are LEGITIMATE_CONSTANT_P. */ | |
3576 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
110b3faa | 3577 | operands[1] = validize_mem (force_const_mem (DFmode, operands[1])); |
f97d9ec3 | 3578 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
34289d57 | 3579 | operands[1] = force_reg (DFmode, operands[1]); |
0f40f9f7 | 3580 | }) |
f97d9ec3 JH |
3581 | |
3582 | (define_insn "*extenddfxf2_1" | |
e075ae69 RH |
3583 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") |
3584 | (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] | |
1b0c37d7 | 3585 | "!TARGET_64BIT && TARGET_80387 |
f97d9ec3 | 3586 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" |
e075ae69 RH |
3587 | { |
3588 | switch (which_alternative) | |
3589 | { | |
3590 | case 0: | |
0c174a68 AB |
3591 | if (REG_P (operands[1]) |
3592 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3593 | return "fstp\t%y0"; |
e075ae69 | 3594 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 3595 | return "fld%z1\t%y1"; |
e075ae69 | 3596 | else |
0f40f9f7 | 3597 | return "fst\t%y0"; |
bc725565 | 3598 | |
e075ae69 RH |
3599 | case 1: |
3600 | /* There is no non-popping store to memory for XFmode. So if | |
3601 | we need one, follow the store with a load. */ | |
3602 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3603 | return "fstp%z0\t%y0\n\tfld%z0\t%y0"; |
e075ae69 | 3604 | else |
0f40f9f7 | 3605 | return "fstp%z0\t%y0"; |
bc725565 | 3606 | |
e075ae69 RH |
3607 | default: |
3608 | abort (); | |
3609 | } | |
0f40f9f7 | 3610 | } |
6ef67412 JH |
3611 | [(set_attr "type" "fmov") |
3612 | (set_attr "mode" "DF,XF")]) | |
bc725565 | 3613 | |
2b589241 JH |
3614 | (define_expand "extenddftf2" |
3615 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
51286de6 | 3616 | (float_extend:TF (match_operand:DF 1 "general_operand" "")))] |
2b589241 | 3617 | "TARGET_80387" |
2b589241 | 3618 | { |
51286de6 RH |
3619 | /* ??? Needed for compress_float_constant since all fp constants |
3620 | are LEGITIMATE_CONSTANT_P. */ | |
3621 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
110b3faa | 3622 | operands[1] = validize_mem (force_const_mem (DFmode, operands[1])); |
2b589241 JH |
3623 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) |
3624 | operands[1] = force_reg (DFmode, operands[1]); | |
0f40f9f7 | 3625 | }) |
2b589241 JH |
3626 | |
3627 | (define_insn "*extenddftf2_1" | |
3628 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m") | |
3629 | (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] | |
3630 | "TARGET_80387 | |
3631 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
2b589241 JH |
3632 | { |
3633 | switch (which_alternative) | |
3634 | { | |
3635 | case 0: | |
3636 | if (REG_P (operands[1]) | |
3637 | && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3638 | return "fstp\t%y0"; |
2b589241 | 3639 | else if (STACK_TOP_P (operands[0])) |
0f40f9f7 | 3640 | return "fld%z1\t%y1"; |
2b589241 | 3641 | else |
0f40f9f7 | 3642 | return "fst\t%y0"; |
2b589241 JH |
3643 | |
3644 | case 1: | |
3645 | /* There is no non-popping store to memory for XFmode. So if | |
3646 | we need one, follow the store with a load. */ | |
3647 | if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3648 | return "fstp%z0\t%y0\n\tfld%z0\t%y0"; |
2b589241 | 3649 | else |
0f40f9f7 | 3650 | return "fstp%z0\t%y0"; |
2b589241 JH |
3651 | |
3652 | default: | |
3653 | abort (); | |
3654 | } | |
0f40f9f7 | 3655 | } |
2b589241 JH |
3656 | [(set_attr "type" "fmov") |
3657 | (set_attr "mode" "DF,XF")]) | |
3658 | ||
e075ae69 RH |
3659 | ;; %%% This seems bad bad news. |
3660 | ;; This cannot output into an f-reg because there is no way to be sure | |
3661 | ;; of truncating in that case. Otherwise this is just like a simple move | |
3662 | ;; insn. So we pretend we can output to a reg in order to get better | |
3663 | ;; register preferencing, but we really use a stack slot. | |
886c62d1 | 3664 | |
e075ae69 RH |
3665 | (define_expand "truncdfsf2" |
3666 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
3667 | (float_truncate:SF | |
3668 | (match_operand:DF 1 "register_operand" ""))) | |
3669 | (clobber (match_dup 2))])] | |
42a0aa6f JH |
3670 | "TARGET_80387 || TARGET_SSE2" |
3671 | " | |
3672 | if (TARGET_80387) | |
3673 | operands[2] = assign_386_stack_local (SFmode, 0); | |
3674 | else | |
3675 | { | |
3676 | emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1])); | |
3677 | DONE; | |
3678 | } | |
3679 | ") | |
bc725565 | 3680 | |
e075ae69 | 3681 | (define_insn "*truncdfsf2_1" |
46ed7963 | 3682 | [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") |
e075ae69 | 3683 | (float_truncate:SF |
46ed7963 JH |
3684 | (match_operand:DF 1 "register_operand" "f,f,f,f"))) |
3685 | (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] | |
42a0aa6f | 3686 | "TARGET_80387 && !TARGET_SSE2" |
e075ae69 RH |
3687 | { |
3688 | switch (which_alternative) | |
3689 | { | |
3690 | case 0: | |
3691 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3692 | return "fstp%z0\t%y0"; |
e075ae69 | 3693 | else |
0f40f9f7 | 3694 | return "fst%z0\t%y0"; |
46ed7963 JH |
3695 | default: |
3696 | abort (); | |
e075ae69 | 3697 | } |
0f40f9f7 | 3698 | } |
46ed7963 JH |
3699 | [(set_attr "type" "fmov,multi,multi,multi") |
3700 | (set_attr "mode" "SF,SF,SF,SF")]) | |
42a0aa6f JH |
3701 | |
3702 | (define_insn "*truncdfsf2_1_sse" | |
46ed7963 | 3703 | [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,Y") |
42a0aa6f | 3704 | (float_truncate:SF |
46ed7963 JH |
3705 | (match_operand:DF 1 "nonimmediate_operand" "f,f,f,f,mY"))) |
3706 | (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))] | |
42a0aa6f | 3707 | "TARGET_80387 && TARGET_SSE2" |
42a0aa6f JH |
3708 | { |
3709 | switch (which_alternative) | |
3710 | { | |
3711 | case 0: | |
3712 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3713 | return "fstp%z0\t%y0"; |
42a0aa6f | 3714 | else |
0f40f9f7 | 3715 | return "fst%z0\t%y0"; |
46ed7963 | 3716 | case 4: |
0f40f9f7 | 3717 | return "cvtsd2ss\t{%1, %0|%0, %1}"; |
46ed7963 JH |
3718 | default: |
3719 | abort (); | |
42a0aa6f | 3720 | } |
0f40f9f7 | 3721 | } |
3d34cd91 | 3722 | [(set_attr "type" "fmov,multi,multi,multi,ssecvt") |
46ed7963 | 3723 | (set_attr "mode" "SF,SF,SF,SF,DF")]) |
53b5ce19 | 3724 | |
e075ae69 | 3725 | (define_insn "*truncdfsf2_2" |
79005df5 | 3726 | [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m") |
42a0aa6f | 3727 | (float_truncate:SF |
79005df5 JH |
3728 | (match_operand:DF 1 "nonimmediate_operand" "mY,f")))] |
3729 | "TARGET_80387 && TARGET_SSE2 | |
3730 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
42a0aa6f JH |
3731 | { |
3732 | switch (which_alternative) | |
3733 | { | |
3734 | case 0: | |
0f40f9f7 | 3735 | return "cvtsd2ss\t{%1, %0|%0, %1}"; |
79005df5 | 3736 | case 1: |
42a0aa6f | 3737 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) |
0f40f9f7 | 3738 | return "fstp%z0\t%y0"; |
42a0aa6f | 3739 | else |
0f40f9f7 ZW |
3740 | return "fst%z0\t%y0"; |
3741 | default: | |
3742 | abort (); | |
42a0aa6f | 3743 | } |
0f40f9f7 | 3744 | } |
3d34cd91 | 3745 | [(set_attr "type" "ssecvt,fmov") |
79005df5 | 3746 | (set_attr "mode" "DF,SF")]) |
42a0aa6f JH |
3747 | |
3748 | (define_insn "truncdfsf2_3" | |
cc2e591b | 3749 | [(set (match_operand:SF 0 "memory_operand" "=m") |
e075ae69 RH |
3750 | (float_truncate:SF |
3751 | (match_operand:DF 1 "register_operand" "f")))] | |
53b5ce19 | 3752 | "TARGET_80387" |
e075ae69 RH |
3753 | { |
3754 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3755 | return "fstp%z0\t%y0"; |
e075ae69 | 3756 | else |
0f40f9f7 ZW |
3757 | return "fst%z0\t%y0"; |
3758 | } | |
6ef67412 JH |
3759 | [(set_attr "type" "fmov") |
3760 | (set_attr "mode" "SF")]) | |
53b5ce19 | 3761 | |
42a0aa6f JH |
3762 | (define_insn "truncdfsf2_sse_only" |
3763 | [(set (match_operand:SF 0 "register_operand" "=Y") | |
3764 | (float_truncate:SF | |
3765 | (match_operand:DF 1 "nonimmediate_operand" "mY")))] | |
3766 | "!TARGET_80387 && TARGET_SSE2" | |
0f40f9f7 | 3767 | "cvtsd2ss\t{%1, %0|%0, %1}" |
3d34cd91 | 3768 | [(set_attr "type" "ssecvt") |
42a0aa6f JH |
3769 | (set_attr "mode" "DF")]) |
3770 | ||
53b5ce19 | 3771 | (define_split |
e075ae69 RH |
3772 | [(set (match_operand:SF 0 "memory_operand" "") |
3773 | (float_truncate:SF | |
3774 | (match_operand:DF 1 "register_operand" ""))) | |
3775 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
3776 | "TARGET_80387" | |
3777 | [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] | |
53b5ce19 JW |
3778 | "") |
3779 | ||
42a0aa6f JH |
3780 | (define_split |
3781 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
3782 | (float_truncate:SF | |
3783 | (match_operand:DF 1 "nonimmediate_operand" ""))) | |
3784 | (clobber (match_operand 2 "" ""))] | |
05b432db JH |
3785 | "TARGET_80387 && reload_completed |
3786 | && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])" | |
42a0aa6f JH |
3787 | [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] |
3788 | "") | |
3789 | ||
53b5ce19 JW |
3790 | (define_split |
3791 | [(set (match_operand:SF 0 "register_operand" "") | |
e075ae69 | 3792 | (float_truncate:SF |
c3c637e3 | 3793 | (match_operand:DF 1 "fp_register_operand" ""))) |
e075ae69 | 3794 | (clobber (match_operand:SF 2 "memory_operand" ""))] |
c3c637e3 | 3795 | "TARGET_80387 && reload_completed" |
e075ae69 RH |
3796 | [(set (match_dup 2) (float_truncate:SF (match_dup 1))) |
3797 | (set (match_dup 0) (match_dup 2))] | |
53b5ce19 JW |
3798 | "") |
3799 | ||
e075ae69 RH |
3800 | (define_expand "truncxfsf2" |
3801 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
3802 | (float_truncate:SF | |
3803 | (match_operand:XF 1 "register_operand" ""))) | |
3804 | (clobber (match_dup 2))])] | |
1b0c37d7 | 3805 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 3806 | "operands[2] = assign_386_stack_local (SFmode, 0);") |
53b5ce19 | 3807 | |
e075ae69 | 3808 | (define_insn "*truncxfsf2_1" |
46ed7963 | 3809 | [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") |
e075ae69 | 3810 | (float_truncate:SF |
46ed7963 JH |
3811 | (match_operand:XF 1 "register_operand" "f,f,f,f"))) |
3812 | (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] | |
1b0c37d7 | 3813 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
3814 | { |
3815 | switch (which_alternative) | |
3816 | { | |
3817 | case 0: | |
3818 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3819 | return "fstp%z0\t%y0"; |
e075ae69 | 3820 | else |
0f40f9f7 | 3821 | return "fst%z0\t%y0"; |
46ed7963 JH |
3822 | default: |
3823 | abort(); | |
e075ae69 | 3824 | } |
0f40f9f7 | 3825 | } |
46ed7963 | 3826 | [(set_attr "type" "fmov,multi,multi,multi") |
6ef67412 | 3827 | (set_attr "mode" "SF")]) |
886c62d1 | 3828 | |
e075ae69 | 3829 | (define_insn "*truncxfsf2_2" |
dd80b906 | 3830 | [(set (match_operand:SF 0 "memory_operand" "=m") |
e075ae69 RH |
3831 | (float_truncate:SF |
3832 | (match_operand:XF 1 "register_operand" "f")))] | |
1b0c37d7 | 3833 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
3834 | { |
3835 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3836 | return "fstp%z0\t%y0"; |
e075ae69 | 3837 | else |
0f40f9f7 ZW |
3838 | return "fst%z0\t%y0"; |
3839 | } | |
6ef67412 JH |
3840 | [(set_attr "type" "fmov") |
3841 | (set_attr "mode" "SF")]) | |
bc725565 JW |
3842 | |
3843 | (define_split | |
e075ae69 RH |
3844 | [(set (match_operand:SF 0 "memory_operand" "") |
3845 | (float_truncate:SF | |
3846 | (match_operand:XF 1 "register_operand" ""))) | |
3847 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
3848 | "TARGET_80387" | |
3849 | [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] | |
886c62d1 JVA |
3850 | "") |
3851 | ||
bc725565 | 3852 | (define_split |
6a4a5d95 | 3853 | [(set (match_operand:SF 0 "register_operand" "") |
e075ae69 RH |
3854 | (float_truncate:SF |
3855 | (match_operand:XF 1 "register_operand" ""))) | |
3856 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
bc725565 | 3857 | "TARGET_80387 && reload_completed" |
e075ae69 RH |
3858 | [(set (match_dup 2) (float_truncate:SF (match_dup 1))) |
3859 | (set (match_dup 0) (match_dup 2))] | |
886c62d1 JVA |
3860 | "") |
3861 | ||
2b589241 JH |
3862 | (define_expand "trunctfsf2" |
3863 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
3864 | (float_truncate:SF | |
3865 | (match_operand:TF 1 "register_operand" ""))) | |
3866 | (clobber (match_dup 2))])] | |
3867 | "TARGET_80387" | |
3868 | "operands[2] = assign_386_stack_local (SFmode, 0);") | |
3869 | ||
3870 | (define_insn "*trunctfsf2_1" | |
46ed7963 | 3871 | [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") |
2b589241 | 3872 | (float_truncate:SF |
46ed7963 JH |
3873 | (match_operand:TF 1 "register_operand" "f,f,f,f"))) |
3874 | (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] | |
2b589241 | 3875 | "TARGET_80387" |
2b589241 JH |
3876 | { |
3877 | switch (which_alternative) | |
3878 | { | |
3879 | case 0: | |
3880 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3881 | return "fstp%z0\t%y0"; |
2b589241 | 3882 | else |
0f40f9f7 | 3883 | return "fst%z0\t%y0"; |
46ed7963 JH |
3884 | default: |
3885 | abort(); | |
2b589241 | 3886 | } |
0f40f9f7 | 3887 | } |
46ed7963 | 3888 | [(set_attr "type" "fmov,multi,multi,multi") |
2b589241 JH |
3889 | (set_attr "mode" "SF")]) |
3890 | ||
1e07edd3 | 3891 | (define_insn "*trunctfsf2_2" |
cc2e591b | 3892 | [(set (match_operand:SF 0 "memory_operand" "=m") |
2b589241 JH |
3893 | (float_truncate:SF |
3894 | (match_operand:TF 1 "register_operand" "f")))] | |
3895 | "TARGET_80387" | |
2b589241 JH |
3896 | { |
3897 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3898 | return "fstp%z0\t%y0"; |
2b589241 | 3899 | else |
0f40f9f7 ZW |
3900 | return "fst%z0\t%y0"; |
3901 | } | |
2b589241 JH |
3902 | [(set_attr "type" "fmov") |
3903 | (set_attr "mode" "SF")]) | |
3904 | ||
3905 | (define_split | |
3906 | [(set (match_operand:SF 0 "memory_operand" "") | |
3907 | (float_truncate:SF | |
3908 | (match_operand:TF 1 "register_operand" ""))) | |
3909 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
3910 | "TARGET_80387" | |
3911 | [(set (match_dup 0) (float_truncate:SF (match_dup 1)))] | |
3912 | "") | |
3913 | ||
3914 | (define_split | |
3915 | [(set (match_operand:SF 0 "register_operand" "") | |
3916 | (float_truncate:SF | |
3917 | (match_operand:TF 1 "register_operand" ""))) | |
3918 | (clobber (match_operand:SF 2 "memory_operand" ""))] | |
3919 | "TARGET_80387 && reload_completed" | |
3920 | [(set (match_dup 2) (float_truncate:SF (match_dup 1))) | |
3921 | (set (match_dup 0) (match_dup 2))] | |
3922 | "") | |
3923 | ||
3924 | ||
e075ae69 RH |
3925 | (define_expand "truncxfdf2" |
3926 | [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
3927 | (float_truncate:DF | |
3928 | (match_operand:XF 1 "register_operand" ""))) | |
3929 | (clobber (match_dup 2))])] | |
1b0c37d7 | 3930 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 3931 | "operands[2] = assign_386_stack_local (DFmode, 0);") |
bc725565 | 3932 | |
e075ae69 | 3933 | (define_insn "*truncxfdf2_1" |
46ed7963 | 3934 | [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf") |
e075ae69 | 3935 | (float_truncate:DF |
46ed7963 JH |
3936 | (match_operand:XF 1 "register_operand" "f,f,f,f"))) |
3937 | (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))] | |
1b0c37d7 | 3938 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
3939 | { |
3940 | switch (which_alternative) | |
3941 | { | |
3942 | case 0: | |
3943 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3944 | return "fstp%z0\t%y0"; |
e075ae69 | 3945 | else |
0f40f9f7 | 3946 | return "fst%z0\t%y0"; |
46ed7963 JH |
3947 | default: |
3948 | abort(); | |
e075ae69 RH |
3949 | } |
3950 | abort (); | |
0f40f9f7 | 3951 | } |
46ed7963 | 3952 | [(set_attr "type" "fmov,multi,multi,multi") |
6ef67412 | 3953 | (set_attr "mode" "DF")]) |
bc725565 | 3954 | |
e075ae69 RH |
3955 | (define_insn "*truncxfdf2_2" |
3956 | [(set (match_operand:DF 0 "memory_operand" "=m") | |
3957 | (float_truncate:DF | |
3958 | (match_operand:XF 1 "register_operand" "f")))] | |
1b0c37d7 | 3959 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
3960 | { |
3961 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 3962 | return "fstp%z0\t%y0"; |
e075ae69 | 3963 | else |
0f40f9f7 ZW |
3964 | return "fst%z0\t%y0"; |
3965 | } | |
6ef67412 JH |
3966 | [(set_attr "type" "fmov") |
3967 | (set_attr "mode" "DF")]) | |
bc725565 JW |
3968 | |
3969 | (define_split | |
e075ae69 RH |
3970 | [(set (match_operand:DF 0 "memory_operand" "") |
3971 | (float_truncate:DF | |
3972 | (match_operand:XF 1 "register_operand" ""))) | |
3973 | (clobber (match_operand:DF 2 "memory_operand" ""))] | |
ca285e07 JH |
3974 | "TARGET_80387" |
3975 | [(set (match_dup 0) (float_truncate:DF (match_dup 1)))] | |
4fb21e90 JVA |
3976 | "") |
3977 | ||
bc725565 | 3978 | (define_split |
6a4a5d95 | 3979 | [(set (match_operand:DF 0 "register_operand" "") |
e075ae69 RH |
3980 | (float_truncate:DF |
3981 | (match_operand:XF 1 "register_operand" ""))) | |
3982 | (clobber (match_operand:DF 2 "memory_operand" ""))] | |
bc725565 | 3983 | "TARGET_80387 && reload_completed" |
ca285e07 | 3984 | [(set (match_dup 2) (float_truncate:DF (match_dup 1))) |
e075ae69 | 3985 | (set (match_dup 0) (match_dup 2))] |
4fb21e90 | 3986 | "") |
ca285e07 | 3987 | |
2b589241 JH |
3988 | (define_expand "trunctfdf2" |
3989 | [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
3990 | (float_truncate:DF | |
3991 | (match_operand:TF 1 "register_operand" ""))) | |
3992 | (clobber (match_dup 2))])] | |
3993 | "TARGET_80387" | |
3994 | "operands[2] = assign_386_stack_local (DFmode, 0);") | |
3995 | ||
3996 | (define_insn "*trunctfdf2_1" | |
46ed7963 | 3997 | [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf") |
2b589241 | 3998 | (float_truncate:DF |
46ed7963 JH |
3999 | (match_operand:TF 1 "register_operand" "f,f,f,f"))) |
4000 | (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))] | |
2b589241 | 4001 | "TARGET_80387" |
2b589241 JH |
4002 | { |
4003 | switch (which_alternative) | |
4004 | { | |
4005 | case 0: | |
4006 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4007 | return "fstp%z0\t%y0"; |
2b589241 | 4008 | else |
0f40f9f7 | 4009 | return "fst%z0\t%y0"; |
46ed7963 JH |
4010 | default: |
4011 | abort(); | |
2b589241 JH |
4012 | } |
4013 | abort (); | |
0f40f9f7 | 4014 | } |
46ed7963 | 4015 | [(set_attr "type" "fmov,multi,multi,multi") |
2b589241 JH |
4016 | (set_attr "mode" "DF")]) |
4017 | ||
46ed7963 | 4018 | (define_insn "*trunctfdf2_2" |
2b589241 JH |
4019 | [(set (match_operand:DF 0 "memory_operand" "=m") |
4020 | (float_truncate:DF | |
4021 | (match_operand:TF 1 "register_operand" "f")))] | |
4022 | "TARGET_80387" | |
2b589241 JH |
4023 | { |
4024 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
0f40f9f7 | 4025 | return "fstp%z0\t%y0"; |
2b589241 | 4026 | else |
0f40f9f7 ZW |
4027 | return "fst%z0\t%y0"; |
4028 | } | |
2b589241 JH |
4029 | [(set_attr "type" "fmov") |
4030 | (set_attr "mode" "DF")]) | |
4031 | ||
4032 | (define_split | |
4033 | [(set (match_operand:DF 0 "memory_operand" "") | |
4034 | (float_truncate:DF | |
4035 | (match_operand:TF 1 "register_operand" ""))) | |
4036 | (clobber (match_operand:DF 2 "memory_operand" ""))] | |
4037 | "TARGET_80387" | |
4038 | [(set (match_dup 0) (float_truncate:DF (match_dup 1)))] | |
4039 | "") | |
4040 | ||
4041 | (define_split | |
4042 | [(set (match_operand:DF 0 "register_operand" "") | |
4043 | (float_truncate:DF | |
4044 | (match_operand:TF 1 "register_operand" ""))) | |
4045 | (clobber (match_operand:DF 2 "memory_operand" ""))] | |
4046 | "TARGET_80387 && reload_completed" | |
4047 | [(set (match_dup 2) (float_truncate:DF (match_dup 1))) | |
4048 | (set (match_dup 0) (match_dup 2))] | |
4049 | "") | |
4050 | ||
e075ae69 RH |
4051 | \f |
4052 | ;; %%% Break up all these bad boys. | |
4fb21e90 | 4053 | |
e075ae69 RH |
4054 | ;; Signed conversion to DImode. |
4055 | ||
2b589241 | 4056 | (define_expand "fix_truncxfdi2" |
22fb740d JH |
4057 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4058 | (fix:DI (match_operand:XF 1 "register_operand" "")))] | |
1b0c37d7 | 4059 | "!TARGET_64BIT && TARGET_80387" |
22fb740d | 4060 | "") |
2b589241 JH |
4061 | |
4062 | (define_expand "fix_trunctfdi2" | |
22fb740d JH |
4063 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4064 | (fix:DI (match_operand:TF 1 "register_operand" "")))] | |
bc725565 | 4065 | "TARGET_80387" |
22fb740d | 4066 | "") |
bc725565 | 4067 | |
e075ae69 | 4068 | (define_expand "fix_truncdfdi2" |
22fb740d JH |
4069 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4070 | (fix:DI (match_operand:DF 1 "register_operand" "")))] | |
46ed7963 | 4071 | "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)" |
46ed7963 | 4072 | { |
1b0c37d7 | 4073 | if (TARGET_64BIT && TARGET_SSE2) |
46ed7963 JH |
4074 | { |
4075 | rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode); | |
4076 | emit_insn (gen_fix_truncdfdi_sse (out, operands[1])); | |
4077 | if (out != operands[0]) | |
4078 | emit_move_insn (operands[0], out); | |
4079 | DONE; | |
4080 | } | |
0f40f9f7 | 4081 | }) |
53b5ce19 | 4082 | |
e075ae69 | 4083 | (define_expand "fix_truncsfdi2" |
22fb740d JH |
4084 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4085 | (fix:DI (match_operand:SF 1 "register_operand" "")))] | |
46ed7963 | 4086 | "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)" |
46ed7963 | 4087 | { |
22fb740d | 4088 | if (TARGET_SSE && TARGET_64BIT) |
46ed7963 JH |
4089 | { |
4090 | rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode); | |
4091 | emit_insn (gen_fix_truncsfdi_sse (out, operands[1])); | |
4092 | if (out != operands[0]) | |
4093 | emit_move_insn (operands[0], out); | |
4094 | DONE; | |
4095 | } | |
0f40f9f7 | 4096 | }) |
e075ae69 | 4097 | |
22fb740d JH |
4098 | ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description |
4099 | ;; of the machinery. | |
4100 | (define_insn_and_split "*fix_truncdi_1" | |
4101 | [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") | |
4102 | (fix:DI (match_operand 1 "register_operand" "f,f")))] | |
4103 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4104 | && !reload_completed && !reload_in_progress | |
4105 | && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" | |
4106 | "#" | |
14f73b5a | 4107 | "&& 1" |
22fb740d JH |
4108 | [(const_int 0)] |
4109 | { | |
4110 | operands[2] = assign_386_stack_local (HImode, 1); | |
4111 | operands[3] = assign_386_stack_local (HImode, 2); | |
4112 | if (memory_operand (operands[0], VOIDmode)) | |
4113 | emit_insn (gen_fix_truncdi_memory (operands[0], operands[1], | |
4114 | operands[2], operands[3])); | |
4115 | else | |
4116 | { | |
4117 | operands[4] = assign_386_stack_local (DImode, 0); | |
4118 | emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1], | |
4119 | operands[2], operands[3], | |
4120 | operands[4])); | |
4121 | } | |
4122 | DONE; | |
4123 | } | |
4124 | [(set_attr "type" "fistp")]) | |
4125 | ||
4126 | (define_insn "fix_truncdi_nomemory" | |
c76aab11 | 4127 | [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") |
e075ae69 | 4128 | (fix:DI (match_operand 1 "register_operand" "f,f"))) |
7a2e09f4 JH |
4129 | (use (match_operand:HI 2 "memory_operand" "m,m")) |
4130 | (use (match_operand:HI 3 "memory_operand" "m,m")) | |
4131 | (clobber (match_operand:DI 4 "memory_operand" "=m,m")) | |
22fb740d | 4132 | (clobber (match_scratch:DF 5 "=&1f,&1f"))] |
46ed7963 | 4133 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) |
22fb740d JH |
4134 | && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" |
4135 | "#" | |
4136 | [(set_attr "type" "fistp")]) | |
4137 | ||
4138 | (define_insn "fix_truncdi_memory" | |
4139 | [(set (match_operand:DI 0 "memory_operand" "=m") | |
4140 | (fix:DI (match_operand 1 "register_operand" "f"))) | |
4141 | (use (match_operand:HI 2 "memory_operand" "m")) | |
4142 | (use (match_operand:HI 3 "memory_operand" "m")) | |
4143 | (clobber (match_scratch:DF 4 "=&1f"))] | |
4144 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4145 | && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" | |
4146 | "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);" | |
4147 | [(set_attr "type" "fistp")]) | |
53b5ce19 | 4148 | |
e075ae69 RH |
4149 | (define_split |
4150 | [(set (match_operand:DI 0 "register_operand" "") | |
4151 | (fix:DI (match_operand 1 "register_operand" ""))) | |
7a2e09f4 JH |
4152 | (use (match_operand:HI 2 "memory_operand" "")) |
4153 | (use (match_operand:HI 3 "memory_operand" "")) | |
4154 | (clobber (match_operand:DI 4 "memory_operand" "")) | |
a05924f9 | 4155 | (clobber (match_scratch 5 ""))] |
7a2e09f4 JH |
4156 | "reload_completed" |
4157 | [(parallel [(set (match_dup 4) (fix:DI (match_dup 1))) | |
4158 | (use (match_dup 2)) | |
4159 | (use (match_dup 3)) | |
e075ae69 | 4160 | (clobber (match_dup 5))]) |
7a2e09f4 | 4161 | (set (match_dup 0) (match_dup 4))] |
53b5ce19 JW |
4162 | "") |
4163 | ||
22fb740d JH |
4164 | (define_split |
4165 | [(set (match_operand:DI 0 "memory_operand" "") | |
4166 | (fix:DI (match_operand 1 "register_operand" ""))) | |
4167 | (use (match_operand:HI 2 "memory_operand" "")) | |
4168 | (use (match_operand:HI 3 "memory_operand" "")) | |
4169 | (clobber (match_operand:DI 4 "memory_operand" "")) | |
4170 | (clobber (match_scratch 5 ""))] | |
4171 | "reload_completed" | |
4172 | [(parallel [(set (match_dup 0) (fix:DI (match_dup 1))) | |
4173 | (use (match_dup 2)) | |
4174 | (use (match_dup 3)) | |
4175 | (clobber (match_dup 5))])] | |
4176 | "") | |
4177 | ||
46ed7963 JH |
4178 | ;; When SSE available, it is always faster to use it! |
4179 | (define_insn "fix_truncsfdi_sse" | |
4180 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4181 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))] | |
1b0c37d7 | 4182 | "TARGET_64BIT && TARGET_SSE" |
0f40f9f7 | 4183 | "cvttss2si{q}\t{%1, %0|%0, %1}" |
3d34cd91 | 4184 | [(set_attr "type" "ssecvt")]) |
46ed7963 JH |
4185 | |
4186 | (define_insn "fix_truncdfdi_sse" | |
4187 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4188 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))] | |
1b0c37d7 | 4189 | "TARGET_64BIT && TARGET_SSE2" |
0f40f9f7 | 4190 | "cvttsd2si{q}\t{%1, %0|%0, %1}" |
3d34cd91 | 4191 | [(set_attr "type" "ssecvt")]) |
46ed7963 | 4192 | |
e075ae69 | 4193 | ;; Signed conversion to SImode. |
53b5ce19 | 4194 | |
e075ae69 | 4195 | (define_expand "fix_truncxfsi2" |
22fb740d JH |
4196 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
4197 | (fix:SI (match_operand:XF 1 "register_operand" "")))] | |
1b0c37d7 | 4198 | "!TARGET_64BIT && TARGET_80387" |
22fb740d | 4199 | "") |
53b5ce19 | 4200 | |
2b589241 | 4201 | (define_expand "fix_trunctfsi2" |
22fb740d JH |
4202 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
4203 | (fix:SI (match_operand:TF 1 "register_operand" "")))] | |
2b589241 | 4204 | "TARGET_80387" |
22fb740d | 4205 | "") |
2b589241 | 4206 | |
e075ae69 | 4207 | (define_expand "fix_truncdfsi2" |
22fb740d JH |
4208 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
4209 | (fix:SI (match_operand:DF 1 "register_operand" "")))] | |
42a0aa6f | 4210 | "TARGET_80387 || TARGET_SSE2" |
42a0aa6f JH |
4211 | { |
4212 | if (TARGET_SSE2) | |
4213 | { | |
ca9a9b12 | 4214 | rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); |
b1675dbd JH |
4215 | emit_insn (gen_fix_truncdfsi_sse (out, operands[1])); |
4216 | if (out != operands[0]) | |
4217 | emit_move_insn (operands[0], out); | |
42a0aa6f JH |
4218 | DONE; |
4219 | } | |
0f40f9f7 | 4220 | }) |
886c62d1 | 4221 | |
e075ae69 | 4222 | (define_expand "fix_truncsfsi2" |
22fb740d JH |
4223 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
4224 | (fix:SI (match_operand:SF 1 "register_operand" "")))] | |
42a0aa6f | 4225 | "TARGET_80387 || TARGET_SSE" |
42a0aa6f | 4226 | { |
22fb740d | 4227 | if (TARGET_SSE) |
42a0aa6f | 4228 | { |
ca9a9b12 | 4229 | rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode); |
46ed7963 | 4230 | emit_insn (gen_fix_truncsfsi_sse (out, operands[1])); |
b1675dbd JH |
4231 | if (out != operands[0]) |
4232 | emit_move_insn (operands[0], out); | |
42a0aa6f JH |
4233 | DONE; |
4234 | } | |
0f40f9f7 | 4235 | }) |
e075ae69 | 4236 | |
22fb740d JH |
4237 | ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description |
4238 | ;; of the machinery. | |
4239 | (define_insn_and_split "*fix_truncsi_1" | |
4240 | [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r") | |
4241 | (fix:SI (match_operand 1 "register_operand" "f,f")))] | |
4242 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4243 | && !reload_completed && !reload_in_progress | |
4244 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" | |
4245 | "#" | |
ab75d1f1 | 4246 | "&& 1" |
22fb740d JH |
4247 | [(const_int 0)] |
4248 | { | |
4249 | operands[2] = assign_386_stack_local (HImode, 1); | |
4250 | operands[3] = assign_386_stack_local (HImode, 2); | |
4251 | if (memory_operand (operands[0], VOIDmode)) | |
4252 | emit_insn (gen_fix_truncsi_memory (operands[0], operands[1], | |
4253 | operands[2], operands[3])); | |
4254 | else | |
4255 | { | |
4256 | operands[4] = assign_386_stack_local (SImode, 0); | |
4257 | emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1], | |
4258 | operands[2], operands[3], | |
4259 | operands[4])); | |
4260 | } | |
4261 | DONE; | |
4262 | } | |
4263 | [(set_attr "type" "fistp")]) | |
4264 | ||
4265 | (define_insn "fix_truncsi_nomemory" | |
c76aab11 | 4266 | [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r") |
e075ae69 | 4267 | (fix:SI (match_operand 1 "register_operand" "f,f"))) |
7a2e09f4 JH |
4268 | (use (match_operand:HI 2 "memory_operand" "m,m")) |
4269 | (use (match_operand:HI 3 "memory_operand" "m,m")) | |
4270 | (clobber (match_operand:SI 4 "memory_operand" "=m,m"))] | |
42a0aa6f | 4271 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) |
22fb740d JH |
4272 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" |
4273 | "#" | |
4274 | [(set_attr "type" "fistp")]) | |
4275 | ||
4276 | (define_insn "fix_truncsi_memory" | |
4277 | [(set (match_operand:SI 0 "memory_operand" "=m") | |
4278 | (fix:SI (match_operand 1 "register_operand" "f"))) | |
4279 | (use (match_operand:HI 2 "memory_operand" "m")) | |
4280 | (use (match_operand:HI 3 "memory_operand" "m"))] | |
4281 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4282 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" | |
e075ae69 | 4283 | "* return output_fix_trunc (insn, operands);" |
22fb740d | 4284 | [(set_attr "type" "fistp")]) |
bc725565 | 4285 | |
42a0aa6f JH |
4286 | ;; When SSE available, it is always faster to use it! |
4287 | (define_insn "fix_truncsfsi_sse" | |
4288 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4289 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))] | |
4290 | "TARGET_SSE" | |
0f40f9f7 | 4291 | "cvttss2si\t{%1, %0|%0, %1}" |
3d34cd91 | 4292 | [(set_attr "type" "ssecvt")]) |
42a0aa6f JH |
4293 | |
4294 | (define_insn "fix_truncdfsi_sse" | |
4295 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4296 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))] | |
4297 | "TARGET_SSE2" | |
0f40f9f7 | 4298 | "cvttsd2si\t{%1, %0|%0, %1}" |
3d34cd91 | 4299 | [(set_attr "type" "ssecvt")]) |
42a0aa6f | 4300 | |
e075ae69 RH |
4301 | (define_split |
4302 | [(set (match_operand:SI 0 "register_operand" "") | |
4303 | (fix:SI (match_operand 1 "register_operand" ""))) | |
7a2e09f4 JH |
4304 | (use (match_operand:HI 2 "memory_operand" "")) |
4305 | (use (match_operand:HI 3 "memory_operand" "")) | |
4306 | (clobber (match_operand:SI 4 "memory_operand" ""))] | |
e075ae69 | 4307 | "reload_completed" |
7a2e09f4 JH |
4308 | [(parallel [(set (match_dup 4) (fix:SI (match_dup 1))) |
4309 | (use (match_dup 2)) | |
22fb740d | 4310 | (use (match_dup 3))]) |
7a2e09f4 | 4311 | (set (match_dup 0) (match_dup 4))] |
bc725565 | 4312 | "") |
4fb21e90 | 4313 | |
22fb740d JH |
4314 | (define_split |
4315 | [(set (match_operand:SI 0 "memory_operand" "") | |
4316 | (fix:SI (match_operand 1 "register_operand" ""))) | |
4317 | (use (match_operand:HI 2 "memory_operand" "")) | |
4318 | (use (match_operand:HI 3 "memory_operand" "")) | |
4319 | (clobber (match_operand:SI 4 "memory_operand" ""))] | |
4320 | "reload_completed" | |
4321 | [(parallel [(set (match_dup 0) (fix:SI (match_dup 1))) | |
4322 | (use (match_dup 2)) | |
4323 | (use (match_dup 3))])] | |
4324 | "") | |
4325 | ||
46d21d2c JW |
4326 | ;; Signed conversion to HImode. |
4327 | ||
4328 | (define_expand "fix_truncxfhi2" | |
22fb740d JH |
4329 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
4330 | (fix:HI (match_operand:XF 1 "register_operand" "")))] | |
1b0c37d7 | 4331 | "!TARGET_64BIT && TARGET_80387" |
22fb740d | 4332 | "") |
46d21d2c | 4333 | |
2b589241 | 4334 | (define_expand "fix_trunctfhi2" |
22fb740d JH |
4335 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
4336 | (fix:HI (match_operand:TF 1 "register_operand" "")))] | |
2b589241 | 4337 | "TARGET_80387" |
22fb740d | 4338 | "") |
2b589241 | 4339 | |
46d21d2c | 4340 | (define_expand "fix_truncdfhi2" |
22fb740d JH |
4341 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
4342 | (fix:HI (match_operand:DF 1 "register_operand" "")))] | |
42a0aa6f | 4343 | "TARGET_80387 && !TARGET_SSE2" |
22fb740d | 4344 | "") |
46d21d2c JW |
4345 | |
4346 | (define_expand "fix_truncsfhi2" | |
22fb740d JH |
4347 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
4348 | (fix:HI (match_operand:SF 1 "register_operand" "")))] | |
42a0aa6f | 4349 | "TARGET_80387 && !TARGET_SSE" |
22fb740d JH |
4350 | "") |
4351 | ||
4352 | ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description | |
4353 | ;; of the machinery. | |
4354 | (define_insn_and_split "*fix_trunchi_1" | |
4355 | [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r") | |
4356 | (fix:HI (match_operand 1 "register_operand" "f,f")))] | |
4357 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4358 | && !reload_completed && !reload_in_progress | |
4359 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" | |
4360 | "#" | |
4361 | "" | |
4362 | [(const_int 0)] | |
4363 | { | |
4364 | operands[2] = assign_386_stack_local (HImode, 1); | |
4365 | operands[3] = assign_386_stack_local (HImode, 2); | |
4366 | if (memory_operand (operands[0], VOIDmode)) | |
4367 | emit_insn (gen_fix_trunchi_memory (operands[0], operands[1], | |
4368 | operands[2], operands[3])); | |
4369 | else | |
4370 | { | |
4371 | operands[4] = assign_386_stack_local (HImode, 0); | |
4372 | emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1], | |
4373 | operands[2], operands[3], | |
4374 | operands[4])); | |
4375 | } | |
4376 | DONE; | |
4377 | } | |
4378 | [(set_attr "type" "fistp")]) | |
46d21d2c | 4379 | |
22fb740d | 4380 | (define_insn "fix_trunchi_nomemory" |
46d21d2c JW |
4381 | [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r") |
4382 | (fix:HI (match_operand 1 "register_operand" "f,f"))) | |
7a2e09f4 JH |
4383 | (use (match_operand:HI 2 "memory_operand" "m,m")) |
4384 | (use (match_operand:HI 3 "memory_operand" "m,m")) | |
4385 | (clobber (match_operand:HI 4 "memory_operand" "=m,m"))] | |
42a0aa6f | 4386 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) |
22fb740d JH |
4387 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" |
4388 | "#" | |
4389 | [(set_attr "type" "fistp")]) | |
4390 | ||
4391 | (define_insn "fix_trunchi_memory" | |
4392 | [(set (match_operand:HI 0 "memory_operand" "=m") | |
4393 | (fix:HI (match_operand 1 "register_operand" "f"))) | |
4394 | (use (match_operand:HI 2 "memory_operand" "m")) | |
4395 | (use (match_operand:HI 3 "memory_operand" "m"))] | |
4396 | "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) | |
4397 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" | |
46d21d2c | 4398 | "* return output_fix_trunc (insn, operands);" |
22fb740d JH |
4399 | [(set_attr "type" "fistp")]) |
4400 | ||
4401 | (define_split | |
4402 | [(set (match_operand:HI 0 "memory_operand" "") | |
4403 | (fix:HI (match_operand 1 "register_operand" ""))) | |
4404 | (use (match_operand:HI 2 "memory_operand" "")) | |
4405 | (use (match_operand:HI 3 "memory_operand" "")) | |
4406 | (clobber (match_operand:HI 4 "memory_operand" ""))] | |
4407 | "reload_completed" | |
4408 | [(parallel [(set (match_dup 0) (fix:HI (match_dup 1))) | |
4409 | (use (match_dup 2)) | |
4410 | (use (match_dup 3))])] | |
4411 | "") | |
46d21d2c JW |
4412 | |
4413 | (define_split | |
4414 | [(set (match_operand:HI 0 "register_operand" "") | |
4415 | (fix:HI (match_operand 1 "register_operand" ""))) | |
7a2e09f4 JH |
4416 | (use (match_operand:HI 2 "memory_operand" "")) |
4417 | (use (match_operand:HI 3 "memory_operand" "")) | |
4418 | (clobber (match_operand:HI 4 "memory_operand" ""))] | |
46d21d2c | 4419 | "reload_completed" |
7a2e09f4 JH |
4420 | [(parallel [(set (match_dup 4) (fix:HI (match_dup 1))) |
4421 | (use (match_dup 2)) | |
4422 | (use (match_dup 3)) | |
46d21d2c | 4423 | (clobber (match_dup 4))]) |
7a2e09f4 | 4424 | (set (match_dup 0) (match_dup 4))] |
46d21d2c JW |
4425 | "") |
4426 | ||
e075ae69 RH |
4427 | ;; %% Not used yet. |
4428 | (define_insn "x86_fnstcw_1" | |
c76aab11 | 4429 | [(set (match_operand:HI 0 "memory_operand" "=m") |
8ee41eaf | 4430 | (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))] |
e1f998ad | 4431 | "TARGET_80387" |
0f40f9f7 | 4432 | "fnstcw\t%0" |
6ef67412 JH |
4433 | [(set_attr "length" "2") |
4434 | (set_attr "mode" "HI") | |
3d34cd91 | 4435 | (set_attr "unit" "i387") |
e075ae69 | 4436 | (set_attr "ppro_uops" "few")]) |
bc725565 | 4437 | |
e075ae69 RH |
4438 | (define_insn "x86_fldcw_1" |
4439 | [(set (reg:HI 18) | |
8ee41eaf | 4440 | (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))] |
bc725565 | 4441 | "TARGET_80387" |
0f40f9f7 | 4442 | "fldcw\t%0" |
6ef67412 JH |
4443 | [(set_attr "length" "2") |
4444 | (set_attr "mode" "HI") | |
3d34cd91 | 4445 | (set_attr "unit" "i387") |
0b5107cf | 4446 | (set_attr "athlon_decode" "vector") |
e075ae69 RH |
4447 | (set_attr "ppro_uops" "few")]) |
4448 | \f | |
4449 | ;; Conversion between fixed point and floating point. | |
886c62d1 | 4450 | |
e075ae69 RH |
4451 | ;; Even though we only accept memory inputs, the backend _really_ |
4452 | ;; wants to be able to do this between registers. | |
4453 | ||
155d8a47 JW |
4454 | (define_insn "floathisf2" |
4455 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4456 | (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] | |
42a0aa6f | 4457 | "TARGET_80387 && !TARGET_SSE" |
155d8a47 | 4458 | "@ |
0f40f9f7 | 4459 | fild%z1\t%1 |
155d8a47 JW |
4460 | #" |
4461 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 4462 | (set_attr "mode" "SF") |
155d8a47 JW |
4463 | (set_attr "fp_int_src" "true")]) |
4464 | ||
42a0aa6f JH |
4465 | (define_expand "floatsisf2" |
4466 | [(set (match_operand:SF 0 "register_operand" "") | |
4467 | (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4468 | "TARGET_SSE || TARGET_80387" | |
4469 | "") | |
4470 | ||
4471 | (define_insn "*floatsisf2_i387" | |
4472 | [(set (match_operand:SF 0 "register_operand" "=f,?f,x") | |
4473 | (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))] | |
4474 | "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" | |
e075ae69 | 4475 | "@ |
0f40f9f7 | 4476 | fild%z1\t%1 |
42a0aa6f | 4477 | # |
0f40f9f7 | 4478 | cvtsi2ss\t{%1, %0|%0, %1}" |
3d34cd91 | 4479 | [(set_attr "type" "fmov,multi,ssecvt") |
42a0aa6f JH |
4480 | (set_attr "mode" "SF") |
4481 | (set_attr "fp_int_src" "true")]) | |
4482 | ||
4483 | (define_insn "*floatsisf2_sse" | |
4484 | [(set (match_operand:SF 0 "register_operand" "=x") | |
4485 | (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))] | |
46ed7963 | 4486 | "TARGET_SSE" |
0f40f9f7 | 4487 | "cvtsi2ss\t{%1, %0|%0, %1}" |
3d34cd91 | 4488 | [(set_attr "type" "ssecvt") |
6ef67412 | 4489 | (set_attr "mode" "SF") |
e075ae69 | 4490 | (set_attr "fp_int_src" "true")]) |
bc725565 | 4491 | |
46ed7963 JH |
4492 | (define_expand "floatdisf2" |
4493 | [(set (match_operand:SF 0 "register_operand" "") | |
4494 | (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] | |
1b0c37d7 | 4495 | "(TARGET_64BIT && TARGET_SSE) || TARGET_80387" |
46ed7963 JH |
4496 | "") |
4497 | ||
ef6257cd JH |
4498 | (define_insn "*floatdisf2_i387_only" |
4499 | [(set (match_operand:SF 0 "register_operand" "=f,?f") | |
4500 | (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] | |
4501 | "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)" | |
4502 | "@ | |
0f40f9f7 | 4503 | fild%z1\t%1 |
ef6257cd JH |
4504 | #" |
4505 | [(set_attr "type" "fmov,multi") | |
4506 | (set_attr "mode" "SF") | |
4507 | (set_attr "fp_int_src" "true")]) | |
4508 | ||
46ed7963 JH |
4509 | (define_insn "*floatdisf2_i387" |
4510 | [(set (match_operand:SF 0 "register_operand" "=f,?f,x") | |
4511 | (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))] | |
1b0c37d7 | 4512 | "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" |
e075ae69 | 4513 | "@ |
0f40f9f7 | 4514 | fild%z1\t%1 |
46ed7963 | 4515 | # |
0f40f9f7 | 4516 | cvtsi2ss{q}\t{%1, %0|%0, %1}" |
3d34cd91 | 4517 | [(set_attr "type" "fmov,multi,ssecvt") |
46ed7963 JH |
4518 | (set_attr "mode" "SF") |
4519 | (set_attr "fp_int_src" "true")]) | |
4520 | ||
4521 | (define_insn "*floatdisf2_sse" | |
4522 | [(set (match_operand:SF 0 "register_operand" "=x") | |
4523 | (float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))] | |
1b0c37d7 | 4524 | "TARGET_64BIT && TARGET_SSE" |
0f40f9f7 | 4525 | "cvtsi2ss{q}\t{%1, %0|%0, %1}" |
3d34cd91 | 4526 | [(set_attr "type" "ssecvt") |
6ef67412 | 4527 | (set_attr "mode" "SF") |
e075ae69 | 4528 | (set_attr "fp_int_src" "true")]) |
bc725565 | 4529 | |
155d8a47 JW |
4530 | (define_insn "floathidf2" |
4531 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4532 | (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] | |
42a0aa6f | 4533 | "TARGET_80387 && !TARGET_SSE2" |
155d8a47 | 4534 | "@ |
0f40f9f7 | 4535 | fild%z1\t%1 |
155d8a47 JW |
4536 | #" |
4537 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 4538 | (set_attr "mode" "DF") |
155d8a47 JW |
4539 | (set_attr "fp_int_src" "true")]) |
4540 | ||
42a0aa6f JH |
4541 | (define_expand "floatsidf2" |
4542 | [(set (match_operand:DF 0 "register_operand" "") | |
4543 | (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))] | |
6185f217 | 4544 | "TARGET_80387 || TARGET_SSE2" |
42a0aa6f JH |
4545 | "") |
4546 | ||
4547 | (define_insn "*floatsidf2_i387" | |
4548 | [(set (match_operand:DF 0 "register_operand" "=f,?f,Y") | |
4549 | (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))] | |
4550 | "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" | |
e075ae69 | 4551 | "@ |
0f40f9f7 | 4552 | fild%z1\t%1 |
42a0aa6f | 4553 | # |
0f40f9f7 | 4554 | cvtsi2sd\t{%1, %0|%0, %1}" |
3d34cd91 | 4555 | [(set_attr "type" "fmov,multi,ssecvt") |
42a0aa6f JH |
4556 | (set_attr "mode" "DF") |
4557 | (set_attr "fp_int_src" "true")]) | |
4558 | ||
4559 | (define_insn "*floatsidf2_sse" | |
4560 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
4561 | (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))] | |
4562 | "TARGET_SSE2" | |
0f40f9f7 | 4563 | "cvtsi2sd\t{%1, %0|%0, %1}" |
3d34cd91 | 4564 | [(set_attr "type" "ssecvt") |
6ef67412 | 4565 | (set_attr "mode" "DF") |
e075ae69 | 4566 | (set_attr "fp_int_src" "true")]) |
e1f998ad | 4567 | |
46ed7963 JH |
4568 | (define_expand "floatdidf2" |
4569 | [(set (match_operand:DF 0 "register_operand" "") | |
4570 | (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))] | |
1b0c37d7 | 4571 | "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387" |
46ed7963 JH |
4572 | "") |
4573 | ||
ef6257cd JH |
4574 | (define_insn "*floatdidf2_i387_only" |
4575 | [(set (match_operand:DF 0 "register_operand" "=f,?f") | |
4576 | (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] | |
4577 | "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)" | |
4578 | "@ | |
0f40f9f7 | 4579 | fild%z1\t%1 |
ef6257cd JH |
4580 | #" |
4581 | [(set_attr "type" "fmov,multi") | |
4582 | (set_attr "mode" "DF") | |
4583 | (set_attr "fp_int_src" "true")]) | |
4584 | ||
46ed7963 JH |
4585 | (define_insn "*floatdidf2_i387" |
4586 | [(set (match_operand:DF 0 "register_operand" "=f,?f,Y") | |
4587 | (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))] | |
1b0c37d7 | 4588 | "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" |
e075ae69 | 4589 | "@ |
0f40f9f7 | 4590 | fild%z1\t%1 |
46ed7963 | 4591 | # |
0f40f9f7 | 4592 | cvtsi2sd{q}\t{%1, %0|%0, %1}" |
3d34cd91 | 4593 | [(set_attr "type" "fmov,multi,ssecvt") |
46ed7963 JH |
4594 | (set_attr "mode" "DF") |
4595 | (set_attr "fp_int_src" "true")]) | |
4596 | ||
4597 | (define_insn "*floatdidf2_sse" | |
4598 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
4599 | (float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))] | |
4600 | "TARGET_SSE2" | |
0f40f9f7 | 4601 | "cvtsi2sd{q}\t{%1, %0|%0, %1}" |
3d34cd91 | 4602 | [(set_attr "type" "ssecvt") |
6ef67412 | 4603 | (set_attr "mode" "DF") |
e075ae69 | 4604 | (set_attr "fp_int_src" "true")]) |
bc725565 | 4605 | |
155d8a47 JW |
4606 | (define_insn "floathixf2" |
4607 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
4608 | (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] | |
1b0c37d7 | 4609 | "!TARGET_64BIT && TARGET_80387" |
155d8a47 | 4610 | "@ |
0f40f9f7 | 4611 | fild%z1\t%1 |
155d8a47 JW |
4612 | #" |
4613 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 4614 | (set_attr "mode" "XF") |
155d8a47 JW |
4615 | (set_attr "fp_int_src" "true")]) |
4616 | ||
2b589241 JH |
4617 | (define_insn "floathitf2" |
4618 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
4619 | (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] | |
4620 | "TARGET_80387" | |
4621 | "@ | |
0f40f9f7 | 4622 | fild%z1\t%1 |
2b589241 JH |
4623 | #" |
4624 | [(set_attr "type" "fmov,multi") | |
4625 | (set_attr "mode" "XF") | |
4626 | (set_attr "fp_int_src" "true")]) | |
4627 | ||
e075ae69 RH |
4628 | (define_insn "floatsixf2" |
4629 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
4630 | (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))] | |
1b0c37d7 | 4631 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 4632 | "@ |
0f40f9f7 | 4633 | fild%z1\t%1 |
e075ae69 RH |
4634 | #" |
4635 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 4636 | (set_attr "mode" "XF") |
e075ae69 | 4637 | (set_attr "fp_int_src" "true")]) |
53b5ce19 | 4638 | |
2b589241 JH |
4639 | (define_insn "floatsitf2" |
4640 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
4641 | (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))] | |
4642 | "TARGET_80387" | |
4643 | "@ | |
0f40f9f7 | 4644 | fild%z1\t%1 |
2b589241 JH |
4645 | #" |
4646 | [(set_attr "type" "fmov,multi") | |
4647 | (set_attr "mode" "XF") | |
4648 | (set_attr "fp_int_src" "true")]) | |
4649 | ||
e075ae69 | 4650 | (define_insn "floatdixf2" |
53b5ce19 | 4651 | [(set (match_operand:XF 0 "register_operand" "=f,f") |
e075ae69 | 4652 | (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] |
1b0c37d7 | 4653 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 4654 | "@ |
0f40f9f7 | 4655 | fild%z1\t%1 |
e075ae69 RH |
4656 | #" |
4657 | [(set_attr "type" "fmov,multi") | |
6ef67412 | 4658 | (set_attr "mode" "XF") |
e075ae69 | 4659 | (set_attr "fp_int_src" "true")]) |
53b5ce19 | 4660 | |
2b589241 JH |
4661 | (define_insn "floatditf2" |
4662 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
4663 | (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] | |
4664 | "TARGET_80387" | |
4665 | "@ | |
0f40f9f7 | 4666 | fild%z1\t%1 |
2b589241 JH |
4667 | #" |
4668 | [(set_attr "type" "fmov,multi") | |
4669 | (set_attr "mode" "XF") | |
4670 | (set_attr "fp_int_src" "true")]) | |
4671 | ||
e075ae69 | 4672 | ;; %%% Kill these when reload knows how to do it. |
155d8a47 | 4673 | (define_split |
c3c637e3 | 4674 | [(set (match_operand 0 "fp_register_operand" "") |
4211a8fb | 4675 | (float (match_operand 1 "register_operand" "")))] |
c3c637e3 | 4676 | "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" |
4211a8fb | 4677 | [(const_int 0)] |
4211a8fb JH |
4678 | { |
4679 | operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]); | |
4680 | operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]); | |
4681 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2])); | |
4682 | ix86_free_from_memory (GET_MODE (operands[1])); | |
4683 | DONE; | |
0f40f9f7 | 4684 | }) |
e075ae69 RH |
4685 | \f |
4686 | ;; Add instructions | |
53b5ce19 | 4687 | |
e075ae69 RH |
4688 | ;; %%% splits for addsidi3 |
4689 | ; [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
4690 | ; (plus:DI (match_operand:DI 1 "general_operand" "") | |
4691 | ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))] | |
e1f998ad | 4692 | |
9b70259d JH |
4693 | (define_expand "adddi3" |
4694 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
4695 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
4696 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
4697 | (clobber (reg:CC 17))] | |
4698 | "" | |
4699 | "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;") | |
4700 | ||
4701 | (define_insn "*adddi3_1" | |
e075ae69 RH |
4702 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") |
4703 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4704 | (match_operand:DI 2 "general_operand" "roiF,riF"))) | |
4705 | (clobber (reg:CC 17))] | |
9b70259d | 4706 | "!TARGET_64BIT" |
bc725565 JW |
4707 | "#") |
4708 | ||
4709 | (define_split | |
e075ae69 | 4710 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
4cbfbb1b | 4711 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
e075ae69 RH |
4712 | (match_operand:DI 2 "general_operand" ""))) |
4713 | (clobber (reg:CC 17))] | |
1b0c37d7 | 4714 | "!TARGET_64BIT && reload_completed" |
8ee41eaf RH |
4715 | [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] |
4716 | UNSPEC_ADD_CARRY)) | |
e075ae69 RH |
4717 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) |
4718 | (parallel [(set (match_dup 3) | |
7e08e190 | 4719 | (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
9dcbdc7e JH |
4720 | (match_dup 4)) |
4721 | (match_dup 5))) | |
e075ae69 RH |
4722 | (clobber (reg:CC 17))])] |
4723 | "split_di (operands+0, 1, operands+0, operands+3); | |
4724 | split_di (operands+1, 1, operands+1, operands+4); | |
4725 | split_di (operands+2, 1, operands+2, operands+5);") | |
4726 | ||
9b70259d JH |
4727 | (define_insn "*adddi3_carry_rex64" |
4728 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
4729 | (plus:DI (plus:DI (ltu:DI (reg:CC 17) (const_int 0)) | |
4730 | (match_operand:DI 1 "nonimmediate_operand" "%0,0")) | |
4731 | (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) | |
4732 | (clobber (reg:CC 17))] | |
1b0c37d7 | 4733 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" |
0f40f9f7 | 4734 | "adc{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
4735 | [(set_attr "type" "alu") |
4736 | (set_attr "pent_pair" "pu") | |
4737 | (set_attr "mode" "DI") | |
4738 | (set_attr "ppro_uops" "few")]) | |
4739 | ||
4740 | (define_insn "*adddi3_cc_rex64" | |
8ee41eaf RH |
4741 | [(set (reg:CC 17) |
4742 | (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4743 | (match_operand:DI 2 "x86_64_general_operand" "re,rm")] | |
4744 | UNSPEC_ADD_CARRY)) | |
9b70259d JH |
4745 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") |
4746 | (plus:DI (match_dup 1) (match_dup 2)))] | |
4747 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" | |
0f40f9f7 | 4748 | "add{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
4749 | [(set_attr "type" "alu") |
4750 | (set_attr "mode" "DI")]) | |
4751 | ||
7abd4e00 | 4752 | (define_insn "*addsi3_carry" |
e075ae69 | 4753 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") |
9dcbdc7e JH |
4754 | (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
4755 | (match_operand:SI 1 "nonimmediate_operand" "%0,0")) | |
4756 | (match_operand:SI 2 "general_operand" "ri,rm"))) | |
e075ae69 | 4757 | (clobber (reg:CC 17))] |
d525dfdf | 4758 | "ix86_binary_operator_ok (PLUS, SImode, operands)" |
0f40f9f7 | 4759 | "adc{l}\t{%2, %0|%0, %2}" |
e075ae69 RH |
4760 | [(set_attr "type" "alu") |
4761 | (set_attr "pent_pair" "pu") | |
6ef67412 | 4762 | (set_attr "mode" "SI") |
e075ae69 | 4763 | (set_attr "ppro_uops" "few")]) |
4fb21e90 | 4764 | |
9b70259d JH |
4765 | (define_insn "*addsi3_carry_zext" |
4766 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4767 | (zero_extend:DI | |
4768 | (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) | |
4769 | (match_operand:SI 1 "nonimmediate_operand" "%0")) | |
4770 | (match_operand:SI 2 "general_operand" "rim")))) | |
4771 | (clobber (reg:CC 17))] | |
4772 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" | |
0f40f9f7 | 4773 | "adc{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
4774 | [(set_attr "type" "alu") |
4775 | (set_attr "pent_pair" "pu") | |
4776 | (set_attr "mode" "SI") | |
4777 | (set_attr "ppro_uops" "few")]) | |
4778 | ||
7e08e190 | 4779 | (define_insn "*addsi3_cc" |
8ee41eaf RH |
4780 | [(set (reg:CC 17) |
4781 | (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4782 | (match_operand:SI 2 "general_operand" "ri,rm")] | |
4783 | UNSPEC_ADD_CARRY)) | |
7e08e190 JH |
4784 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") |
4785 | (plus:SI (match_dup 1) (match_dup 2)))] | |
265dab10 | 4786 | "ix86_binary_operator_ok (PLUS, SImode, operands)" |
0f40f9f7 | 4787 | "add{l}\t{%2, %0|%0, %2}" |
265dab10 | 4788 | [(set_attr "type" "alu") |
7e08e190 JH |
4789 | (set_attr "mode" "SI")]) |
4790 | ||
4791 | (define_insn "addqi3_cc" | |
8ee41eaf RH |
4792 | [(set (reg:CC 17) |
4793 | (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0") | |
4794 | (match_operand:QI 2 "general_operand" "qi,qm")] | |
4795 | UNSPEC_ADD_CARRY)) | |
7e08e190 JH |
4796 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") |
4797 | (plus:QI (match_dup 1) (match_dup 2)))] | |
4798 | "ix86_binary_operator_ok (PLUS, QImode, operands)" | |
0f40f9f7 | 4799 | "add{b}\t{%2, %0|%0, %2}" |
7e08e190 JH |
4800 | [(set_attr "type" "alu") |
4801 | (set_attr "mode" "QI")]) | |
265dab10 | 4802 | |
e075ae69 RH |
4803 | (define_expand "addsi3" |
4804 | [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
4805 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4806 | (match_operand:SI 2 "general_operand" ""))) | |
4807 | (clobber (reg:CC 17))])] | |
4808 | "" | |
4809 | "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;") | |
886c62d1 | 4810 | |
ac62a60e | 4811 | (define_insn "*lea_1" |
e075ae69 | 4812 | [(set (match_operand:SI 0 "register_operand" "=r") |
ad678cb0 | 4813 | (match_operand:SI 1 "address_operand" "p"))] |
ac62a60e | 4814 | "!TARGET_64BIT" |
0f40f9f7 | 4815 | "lea{l}\t{%a1, %0|%0, %a1}" |
6ef67412 JH |
4816 | [(set_attr "type" "lea") |
4817 | (set_attr "mode" "SI")]) | |
2ae0f82c | 4818 | |
ac62a60e JH |
4819 | (define_insn "*lea_1_rex64" |
4820 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4821 | (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))] | |
4822 | "TARGET_64BIT" | |
0f40f9f7 | 4823 | "lea{l}\t{%a1, %0|%0, %a1}" |
ac62a60e JH |
4824 | [(set_attr "type" "lea") |
4825 | (set_attr "mode" "SI")]) | |
4826 | ||
4827 | (define_insn "*lea_1_zext" | |
4828 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4829 | (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))] | |
d4f33f6c | 4830 | "TARGET_64BIT" |
0f40f9f7 | 4831 | "lea{l}\t{%a1, %k0|%k0, %a1}" |
ac62a60e JH |
4832 | [(set_attr "type" "lea") |
4833 | (set_attr "mode" "SI")]) | |
4834 | ||
4835 | (define_insn "*lea_2_rex64" | |
4836 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4837 | (match_operand:DI 1 "address_operand" "p"))] | |
4838 | "TARGET_64BIT" | |
0f40f9f7 | 4839 | "lea{q}\t{%a1, %0|%0, %a1}" |
ac62a60e JH |
4840 | [(set_attr "type" "lea") |
4841 | (set_attr "mode" "DI")]) | |
4842 | ||
58787064 JH |
4843 | ;; The lea patterns for non-Pmodes needs to be matched by several |
4844 | ;; insns converted to real lea by splitters. | |
4845 | ||
4846 | (define_insn_and_split "*lea_general_1" | |
4847 | [(set (match_operand 0 "register_operand" "=r") | |
7ec70495 | 4848 | (plus (plus (match_operand 1 "index_register_operand" "r") |
58787064 JH |
4849 | (match_operand 2 "register_operand" "r")) |
4850 | (match_operand 3 "immediate_operand" "i")))] | |
ac62a60e JH |
4851 | "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode |
4852 | || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) | |
58787064 JH |
4853 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) |
4854 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
4855 | && GET_MODE (operands[0]) == GET_MODE (operands[2]) | |
4856 | && (GET_MODE (operands[0]) == GET_MODE (operands[3]) | |
4857 | || GET_MODE (operands[3]) == VOIDmode)" | |
4858 | "#" | |
cb694d2c | 4859 | "&& reload_completed" |
58787064 | 4860 | [(const_int 0)] |
58787064 JH |
4861 | { |
4862 | rtx pat; | |
4863 | operands[0] = gen_lowpart (SImode, operands[0]); | |
4864 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
4865 | operands[2] = gen_lowpart (Pmode, operands[2]); | |
4866 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
4867 | pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]), | |
4868 | operands[3]); | |
4869 | if (Pmode != SImode) | |
4870 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
4871 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
4872 | DONE; | |
0f40f9f7 | 4873 | } |
58787064 JH |
4874 | [(set_attr "type" "lea") |
4875 | (set_attr "mode" "SI")]) | |
4876 | ||
ac62a60e JH |
4877 | (define_insn_and_split "*lea_general_1_zext" |
4878 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4879 | (zero_extend:DI | |
7ec70495 | 4880 | (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r") |
ac62a60e JH |
4881 | (match_operand:SI 2 "register_operand" "r")) |
4882 | (match_operand:SI 3 "immediate_operand" "i"))))] | |
4883 | "TARGET_64BIT" | |
4884 | "#" | |
4885 | "&& reload_completed" | |
4886 | [(set (match_dup 0) | |
4887 | (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1) | |
4888 | (match_dup 2)) | |
4889 | (match_dup 3)) 0)))] | |
ac62a60e JH |
4890 | { |
4891 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
4892 | operands[2] = gen_lowpart (Pmode, operands[2]); | |
4893 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
0f40f9f7 | 4894 | } |
ac62a60e JH |
4895 | [(set_attr "type" "lea") |
4896 | (set_attr "mode" "SI")]) | |
4897 | ||
58787064 JH |
4898 | (define_insn_and_split "*lea_general_2" |
4899 | [(set (match_operand 0 "register_operand" "=r") | |
7ec70495 | 4900 | (plus (mult (match_operand 1 "index_register_operand" "r") |
58787064 JH |
4901 | (match_operand 2 "const248_operand" "i")) |
4902 | (match_operand 3 "nonmemory_operand" "ri")))] | |
ac62a60e JH |
4903 | "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode |
4904 | || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) | |
58787064 JH |
4905 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) |
4906 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
4907 | && (GET_MODE (operands[0]) == GET_MODE (operands[3]) | |
4908 | || GET_MODE (operands[3]) == VOIDmode)" | |
4909 | "#" | |
cb694d2c | 4910 | "&& reload_completed" |
58787064 | 4911 | [(const_int 0)] |
58787064 JH |
4912 | { |
4913 | rtx pat; | |
4914 | operands[0] = gen_lowpart (SImode, operands[0]); | |
4915 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
4916 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
4917 | pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]), | |
4918 | operands[3]); | |
4919 | if (Pmode != SImode) | |
4920 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
4921 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
4922 | DONE; | |
0f40f9f7 | 4923 | } |
58787064 JH |
4924 | [(set_attr "type" "lea") |
4925 | (set_attr "mode" "SI")]) | |
4926 | ||
ac62a60e JH |
4927 | (define_insn_and_split "*lea_general_2_zext" |
4928 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4929 | (zero_extend:DI | |
7ec70495 | 4930 | (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r") |
ac62a60e JH |
4931 | (match_operand:SI 2 "const248_operand" "n")) |
4932 | (match_operand:SI 3 "nonmemory_operand" "ri"))))] | |
4933 | "TARGET_64BIT" | |
4934 | "#" | |
4935 | "&& reload_completed" | |
4936 | [(set (match_dup 0) | |
4937 | (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1) | |
4938 | (match_dup 2)) | |
4939 | (match_dup 3)) 0)))] | |
ac62a60e JH |
4940 | { |
4941 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
4942 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
0f40f9f7 | 4943 | } |
ac62a60e JH |
4944 | [(set_attr "type" "lea") |
4945 | (set_attr "mode" "SI")]) | |
4946 | ||
58787064 JH |
4947 | (define_insn_and_split "*lea_general_3" |
4948 | [(set (match_operand 0 "register_operand" "=r") | |
7ec70495 | 4949 | (plus (plus (mult (match_operand 1 "index_register_operand" "r") |
58787064 JH |
4950 | (match_operand 2 "const248_operand" "i")) |
4951 | (match_operand 3 "register_operand" "r")) | |
4952 | (match_operand 4 "immediate_operand" "i")))] | |
ac62a60e JH |
4953 | "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode |
4954 | || (TARGET_64BIT && GET_MODE (operands[0]) == SImode)) | |
58787064 JH |
4955 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) |
4956 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
4957 | && GET_MODE (operands[0]) == GET_MODE (operands[3])" | |
4958 | "#" | |
cb694d2c | 4959 | "&& reload_completed" |
58787064 | 4960 | [(const_int 0)] |
58787064 JH |
4961 | { |
4962 | rtx pat; | |
4963 | operands[0] = gen_lowpart (SImode, operands[0]); | |
4964 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
4965 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
4966 | operands[4] = gen_lowpart (Pmode, operands[4]); | |
4967 | pat = gen_rtx_PLUS (Pmode, | |
4968 | gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], | |
4969 | operands[2]), | |
4970 | operands[3]), | |
4971 | operands[4]); | |
4972 | if (Pmode != SImode) | |
4973 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
4974 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
4975 | DONE; | |
0f40f9f7 | 4976 | } |
58787064 JH |
4977 | [(set_attr "type" "lea") |
4978 | (set_attr "mode" "SI")]) | |
4979 | ||
ac62a60e JH |
4980 | (define_insn_and_split "*lea_general_3_zext" |
4981 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4982 | (zero_extend:DI | |
7ec70495 | 4983 | (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r") |
ac62a60e JH |
4984 | (match_operand:SI 2 "const248_operand" "n")) |
4985 | (match_operand:SI 3 "register_operand" "r")) | |
4986 | (match_operand:SI 4 "immediate_operand" "i"))))] | |
4987 | "TARGET_64BIT" | |
4988 | "#" | |
4989 | "&& reload_completed" | |
4990 | [(set (match_dup 0) | |
4991 | (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1) | |
4992 | (match_dup 2)) | |
4993 | (match_dup 3)) | |
4994 | (match_dup 4)) 0)))] | |
ac62a60e JH |
4995 | { |
4996 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
4997 | operands[3] = gen_lowpart (Pmode, operands[3]); | |
4998 | operands[4] = gen_lowpart (Pmode, operands[4]); | |
0f40f9f7 | 4999 | } |
ac62a60e JH |
5000 | [(set_attr "type" "lea") |
5001 | (set_attr "mode" "SI")]) | |
5002 | ||
9b70259d JH |
5003 | (define_insn "*adddi_1_rex64" |
5004 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r") | |
5005 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r") | |
5006 | (match_operand:DI 2 "x86_64_general_operand" "rme,re,re"))) | |
e075ae69 | 5007 | (clobber (reg:CC 17))] |
9b70259d | 5008 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" |
2ae0f82c | 5009 | { |
e075ae69 | 5010 | switch (get_attr_type (insn)) |
2ae0f82c | 5011 | { |
e075ae69 RH |
5012 | case TYPE_LEA: |
5013 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
0f40f9f7 | 5014 | return "lea{q}\t{%a2, %0|%0, %a2}"; |
2ae0f82c | 5015 | |
e075ae69 RH |
5016 | case TYPE_INCDEC: |
5017 | if (! rtx_equal_p (operands[0], operands[1])) | |
5018 | abort (); | |
5019 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5020 | return "inc{q}\t%0"; |
e075ae69 | 5021 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5022 | return "dec{q}\t%0"; |
2ae0f82c | 5023 | else |
9b70259d | 5024 | abort (); |
2ae0f82c | 5025 | |
e075ae69 RH |
5026 | default: |
5027 | if (! rtx_equal_p (operands[0], operands[1])) | |
5028 | abort (); | |
2ae0f82c | 5029 | |
e075ae69 RH |
5030 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. |
5031 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5032 | if (GET_CODE (operands[2]) == CONST_INT | |
ef6257cd | 5033 | /* Avoid overflows. */ |
0f40f9f7 | 5034 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) |
e075ae69 RH |
5035 | && (INTVAL (operands[2]) == 128 |
5036 | || (INTVAL (operands[2]) < 0 | |
5037 | && INTVAL (operands[2]) != -128))) | |
5038 | { | |
5039 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5040 | return "sub{q}\t{%2, %0|%0, %2}"; |
e075ae69 | 5041 | } |
0f40f9f7 | 5042 | return "add{q}\t{%2, %0|%0, %2}"; |
e075ae69 | 5043 | } |
0f40f9f7 | 5044 | } |
e075ae69 RH |
5045 | [(set (attr "type") |
5046 | (cond [(eq_attr "alternative" "2") | |
5047 | (const_string "lea") | |
5048 | ; Current assemblers are broken and do not allow @GOTOFF in | |
5049 | ; ought but a memory context. | |
9b70259d | 5050 | (match_operand:DI 2 "pic_symbolic_operand" "") |
e075ae69 | 5051 | (const_string "lea") |
9b70259d | 5052 | (match_operand:DI 2 "incdec_operand" "") |
e075ae69 RH |
5053 | (const_string "incdec") |
5054 | ] | |
6ef67412 | 5055 | (const_string "alu"))) |
9b70259d | 5056 | (set_attr "mode" "DI")]) |
e075ae69 | 5057 | |
1c27d4b2 JH |
5058 | ;; Convert lea to the lea pattern to avoid flags dependency. |
5059 | (define_split | |
9b70259d JH |
5060 | [(set (match_operand:DI 0 "register_operand" "") |
5061 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5062 | (match_operand:DI 2 "x86_64_nonmemory_operand" ""))) | |
1c27d4b2 | 5063 | (clobber (reg:CC 17))] |
1b0c37d7 | 5064 | "TARGET_64BIT && reload_completed |
abe24fb3 | 5065 | && true_regnum (operands[0]) != true_regnum (operands[1])" |
9b70259d JH |
5066 | [(set (match_dup 0) |
5067 | (plus:DI (match_dup 1) | |
5068 | (match_dup 2)))] | |
5069 | "") | |
1c27d4b2 | 5070 | |
9b70259d | 5071 | (define_insn "*adddi_2_rex64" |
16189740 RH |
5072 | [(set (reg 17) |
5073 | (compare | |
9b70259d JH |
5074 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
5075 | (match_operand:DI 2 "x86_64_general_operand" "rme,re")) | |
e075ae69 | 5076 | (const_int 0))) |
9b70259d JH |
5077 | (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") |
5078 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5079 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
5080 | && ix86_binary_operator_ok (PLUS, DImode, operands) | |
e075ae69 | 5081 | /* Current assemblers are broken and do not allow @GOTOFF in |
892a2d68 | 5082 | ought but a memory context. */ |
e075ae69 | 5083 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
886c62d1 | 5084 | { |
e075ae69 | 5085 | switch (get_attr_type (insn)) |
96f218bb | 5086 | { |
e075ae69 RH |
5087 | case TYPE_INCDEC: |
5088 | if (! rtx_equal_p (operands[0], operands[1])) | |
5089 | abort (); | |
5090 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5091 | return "inc{q}\t%0"; |
e075ae69 | 5092 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5093 | return "dec{q}\t%0"; |
96f218bb | 5094 | else |
9b70259d | 5095 | abort (); |
96f218bb | 5096 | |
e075ae69 RH |
5097 | default: |
5098 | if (! rtx_equal_p (operands[0], operands[1])) | |
5099 | abort (); | |
9b70259d JH |
5100 | /* ???? We ought to handle there the 32bit case too |
5101 | - do we need new constrant? */ | |
e075ae69 RH |
5102 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. |
5103 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5104 | if (GET_CODE (operands[2]) == CONST_INT | |
ef6257cd | 5105 | /* Avoid overflows. */ |
0f40f9f7 | 5106 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) |
e075ae69 RH |
5107 | && (INTVAL (operands[2]) == 128 |
5108 | || (INTVAL (operands[2]) < 0 | |
5109 | && INTVAL (operands[2]) != -128))) | |
5110 | { | |
5111 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5112 | return "sub{q}\t{%2, %0|%0, %2}"; |
e075ae69 | 5113 | } |
0f40f9f7 | 5114 | return "add{q}\t{%2, %0|%0, %2}"; |
9c530261 | 5115 | } |
0f40f9f7 | 5116 | } |
e075ae69 | 5117 | [(set (attr "type") |
9b70259d | 5118 | (if_then_else (match_operand:DI 2 "incdec_operand" "") |
e075ae69 | 5119 | (const_string "incdec") |
6ef67412 | 5120 | (const_string "alu"))) |
9b70259d | 5121 | (set_attr "mode" "DI")]) |
e075ae69 | 5122 | |
e74061a9 | 5123 | (define_insn "*adddi_3_rex64" |
d90ffc8d | 5124 | [(set (reg 17) |
9b70259d JH |
5125 | (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme")) |
5126 | (match_operand:DI 1 "x86_64_general_operand" "%0"))) | |
5127 | (clobber (match_scratch:DI 0 "=r"))] | |
e74061a9 JH |
5128 | "TARGET_64BIT |
5129 | && ix86_match_ccmode (insn, CCZmode) | |
d90ffc8d JH |
5130 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) |
5131 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 5132 | ought but a memory context. */ |
d90ffc8d | 5133 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
d90ffc8d JH |
5134 | { |
5135 | switch (get_attr_type (insn)) | |
5136 | { | |
5137 | case TYPE_INCDEC: | |
5138 | if (! rtx_equal_p (operands[0], operands[1])) | |
5139 | abort (); | |
5140 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5141 | return "inc{q}\t%0"; |
d90ffc8d | 5142 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5143 | return "dec{q}\t%0"; |
d90ffc8d | 5144 | else |
9b70259d | 5145 | abort (); |
d90ffc8d JH |
5146 | |
5147 | default: | |
5148 | if (! rtx_equal_p (operands[0], operands[1])) | |
5149 | abort (); | |
9b70259d JH |
5150 | /* ???? We ought to handle there the 32bit case too |
5151 | - do we need new constrant? */ | |
d90ffc8d JH |
5152 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. |
5153 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5154 | if (GET_CODE (operands[2]) == CONST_INT | |
ef6257cd | 5155 | /* Avoid overflows. */ |
0f40f9f7 | 5156 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) |
d90ffc8d JH |
5157 | && (INTVAL (operands[2]) == 128 |
5158 | || (INTVAL (operands[2]) < 0 | |
5159 | && INTVAL (operands[2]) != -128))) | |
5160 | { | |
5161 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5162 | return "sub{q}\t{%2, %0|%0, %2}"; |
d90ffc8d | 5163 | } |
0f40f9f7 | 5164 | return "add{q}\t{%2, %0|%0, %2}"; |
d90ffc8d | 5165 | } |
0f40f9f7 | 5166 | } |
d90ffc8d | 5167 | [(set (attr "type") |
9b70259d | 5168 | (if_then_else (match_operand:DI 2 "incdec_operand" "") |
d90ffc8d JH |
5169 | (const_string "incdec") |
5170 | (const_string "alu"))) | |
9b70259d | 5171 | (set_attr "mode" "DI")]) |
d90ffc8d | 5172 | |
9b70259d | 5173 | ; For comparisons against 1, -1 and 128, we may generate better code |
7e08e190 JH |
5174 | ; by converting cmp to add, inc or dec as done by peephole2. This pattern |
5175 | ; is matched then. We can't accept general immediate, because for | |
5176 | ; case of overflows, the result is messed up. | |
9b70259d | 5177 | ; This pattern also don't hold of 0x8000000000000000, since the value overflows |
7e08e190 | 5178 | ; when negated. |
d6a7951f | 5179 | ; Also carry flag is reversed compared to cmp, so this conversion is valid |
7e08e190 | 5180 | ; only for comparisons not depending on it. |
e74061a9 | 5181 | (define_insn "*adddi_4_rex64" |
9076b9c1 | 5182 | [(set (reg 17) |
9b70259d JH |
5183 | (compare (match_operand:DI 1 "nonimmediate_operand" "0") |
5184 | (match_operand:DI 2 "x86_64_immediate_operand" "e"))) | |
5185 | (clobber (match_scratch:DI 0 "=rm"))] | |
e74061a9 JH |
5186 | "TARGET_64BIT |
5187 | && ix86_match_ccmode (insn, CCGCmode)" | |
7e08e190 JH |
5188 | { |
5189 | switch (get_attr_type (insn)) | |
5190 | { | |
5191 | case TYPE_INCDEC: | |
5192 | if (operands[2] == constm1_rtx) | |
0f40f9f7 | 5193 | return "inc{q}\t%0"; |
7e08e190 | 5194 | else if (operands[2] == const1_rtx) |
0f40f9f7 | 5195 | return "dec{q}\t%0"; |
7e08e190 JH |
5196 | else |
5197 | abort(); | |
e075ae69 | 5198 | |
7e08e190 JH |
5199 | default: |
5200 | if (! rtx_equal_p (operands[0], operands[1])) | |
5201 | abort (); | |
5202 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5203 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5204 | if ((INTVAL (operands[2]) == -128 | |
5205 | || (INTVAL (operands[2]) > 0 | |
ef6257cd JH |
5206 | && INTVAL (operands[2]) != 128)) |
5207 | /* Avoid overflows. */ | |
0f40f9f7 ZW |
5208 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))) |
5209 | return "sub{q}\t{%2, %0|%0, %2}"; | |
7e08e190 | 5210 | operands[2] = GEN_INT (-INTVAL (operands[2])); |
0f40f9f7 | 5211 | return "add{q}\t{%2, %0|%0, %2}"; |
7e08e190 | 5212 | } |
0f40f9f7 | 5213 | } |
7e08e190 | 5214 | [(set (attr "type") |
9b70259d | 5215 | (if_then_else (match_operand:DI 2 "incdec_operand" "") |
7e08e190 JH |
5216 | (const_string "incdec") |
5217 | (const_string "alu"))) | |
9b70259d | 5218 | (set_attr "mode" "DI")]) |
d90ffc8d | 5219 | |
e74061a9 | 5220 | (define_insn "*adddi_5_rex64" |
9076b9c1 JH |
5221 | [(set (reg 17) |
5222 | (compare | |
9b70259d JH |
5223 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5224 | (match_operand:DI 2 "x86_64_general_operand" "rme")) | |
9076b9c1 | 5225 | (const_int 0))) |
9b70259d | 5226 | (clobber (match_scratch:DI 0 "=r"))] |
e74061a9 JH |
5227 | "TARGET_64BIT |
5228 | && ix86_match_ccmode (insn, CCGOCmode) | |
9076b9c1 JH |
5229 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) |
5230 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 5231 | ought but a memory context. */ |
9076b9c1 | 5232 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9076b9c1 JH |
5233 | { |
5234 | switch (get_attr_type (insn)) | |
5235 | { | |
5236 | case TYPE_INCDEC: | |
5237 | if (! rtx_equal_p (operands[0], operands[1])) | |
5238 | abort (); | |
5239 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5240 | return "inc{q}\t%0"; |
9076b9c1 | 5241 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5242 | return "dec{q}\t%0"; |
9076b9c1 JH |
5243 | else |
5244 | abort(); | |
5245 | ||
5246 | default: | |
5247 | if (! rtx_equal_p (operands[0], operands[1])) | |
5248 | abort (); | |
5249 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5250 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5251 | if (GET_CODE (operands[2]) == CONST_INT | |
ef6257cd | 5252 | /* Avoid overflows. */ |
0f40f9f7 | 5253 | && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))) |
9076b9c1 JH |
5254 | && (INTVAL (operands[2]) == 128 |
5255 | || (INTVAL (operands[2]) < 0 | |
5256 | && INTVAL (operands[2]) != -128))) | |
5257 | { | |
5258 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5259 | return "sub{q}\t{%2, %0|%0, %2}"; |
9076b9c1 | 5260 | } |
0f40f9f7 | 5261 | return "add{q}\t{%2, %0|%0, %2}"; |
9076b9c1 | 5262 | } |
0f40f9f7 | 5263 | } |
9076b9c1 | 5264 | [(set (attr "type") |
9b70259d | 5265 | (if_then_else (match_operand:DI 2 "incdec_operand" "") |
9076b9c1 JH |
5266 | (const_string "incdec") |
5267 | (const_string "alu"))) | |
9b70259d | 5268 | (set_attr "mode" "DI")]) |
2ae0f82c | 5269 | |
e075ae69 | 5270 | |
9b70259d JH |
5271 | (define_insn "*addsi_1" |
5272 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r") | |
5273 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r") | |
5274 | (match_operand:SI 2 "general_operand" "rmni,rni,rni"))) | |
58787064 | 5275 | (clobber (reg:CC 17))] |
9b70259d | 5276 | "ix86_binary_operator_ok (PLUS, SImode, operands)" |
58787064 JH |
5277 | { |
5278 | switch (get_attr_type (insn)) | |
5279 | { | |
5280 | case TYPE_LEA: | |
9b70259d | 5281 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); |
0f40f9f7 | 5282 | return "lea{l}\t{%a2, %0|%0, %a2}"; |
9b70259d | 5283 | |
58787064 | 5284 | case TYPE_INCDEC: |
9b70259d JH |
5285 | if (! rtx_equal_p (operands[0], operands[1])) |
5286 | abort (); | |
58787064 | 5287 | if (operands[2] == const1_rtx) |
0f40f9f7 | 5288 | return "inc{l}\t%0"; |
9b70259d | 5289 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5290 | return "dec{l}\t%0"; |
9b70259d JH |
5291 | else |
5292 | abort(); | |
58787064 JH |
5293 | |
5294 | default: | |
9b70259d JH |
5295 | if (! rtx_equal_p (operands[0], operands[1])) |
5296 | abort (); | |
5297 | ||
58787064 JH |
5298 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. |
5299 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5300 | if (GET_CODE (operands[2]) == CONST_INT | |
5301 | && (INTVAL (operands[2]) == 128 | |
5302 | || (INTVAL (operands[2]) < 0 | |
5303 | && INTVAL (operands[2]) != -128))) | |
9b70259d JH |
5304 | { |
5305 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5306 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5307 | } |
0f40f9f7 | 5308 | return "add{l}\t{%2, %0|%0, %2}"; |
58787064 | 5309 | } |
0f40f9f7 | 5310 | } |
58787064 | 5311 | [(set (attr "type") |
9b70259d JH |
5312 | (cond [(eq_attr "alternative" "2") |
5313 | (const_string "lea") | |
5314 | ; Current assemblers are broken and do not allow @GOTOFF in | |
5315 | ; ought but a memory context. | |
5316 | (match_operand:SI 2 "pic_symbolic_operand" "") | |
5317 | (const_string "lea") | |
5318 | (match_operand:SI 2 "incdec_operand" "") | |
5319 | (const_string "incdec") | |
5320 | ] | |
5321 | (const_string "alu"))) | |
5322 | (set_attr "mode" "SI")]) | |
58787064 | 5323 | |
9b70259d JH |
5324 | ;; Convert lea to the lea pattern to avoid flags dependency. |
5325 | (define_split | |
5326 | [(set (match_operand 0 "register_operand" "") | |
5327 | (plus (match_operand 1 "register_operand" "") | |
5328 | (match_operand 2 "nonmemory_operand" ""))) | |
e075ae69 | 5329 | (clobber (reg:CC 17))] |
9b70259d JH |
5330 | "reload_completed |
5331 | && true_regnum (operands[0]) != true_regnum (operands[1])" | |
5332 | [(const_int 0)] | |
9b70259d JH |
5333 | { |
5334 | rtx pat; | |
5335 | /* In -fPIC mode the constructs like (const (unspec [symbol_ref])) | |
5336 | may confuse gen_lowpart. */ | |
5337 | if (GET_MODE (operands[0]) != Pmode) | |
5338 | { | |
5339 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5340 | operands[2] = gen_lowpart (Pmode, operands[2]); | |
5341 | } | |
5342 | operands[0] = gen_lowpart (SImode, operands[0]); | |
5343 | pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]); | |
5344 | if (Pmode != SImode) | |
5345 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
5346 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
5347 | DONE; | |
0f40f9f7 | 5348 | }) |
9b70259d JH |
5349 | |
5350 | ;; It may seem that nonimmediate operand is proper one for operand 1. | |
5351 | ;; The addsi_1 pattern allows nonimmediate operand at that place and | |
5352 | ;; we take care in ix86_binary_operator_ok to not allow two memory | |
5353 | ;; operands so proper swapping will be done in reload. This allow | |
5354 | ;; patterns constructed from addsi_1 to match. | |
5355 | (define_insn "addsi_1_zext" | |
5356 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
5357 | (zero_extend:DI | |
5358 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r") | |
5359 | (match_operand:SI 2 "general_operand" "rmni,rni")))) | |
5360 | (clobber (reg:CC 17))] | |
5361 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" | |
886c62d1 | 5362 | { |
e075ae69 | 5363 | switch (get_attr_type (insn)) |
7c802a40 | 5364 | { |
9b70259d JH |
5365 | case TYPE_LEA: |
5366 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
0f40f9f7 | 5367 | return "lea{l}\t{%a2, %k0|%k0, %a2}"; |
9b70259d | 5368 | |
e075ae69 RH |
5369 | case TYPE_INCDEC: |
5370 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5371 | return "inc{l}\t%k0"; |
9b70259d | 5372 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5373 | return "dec{l}\t%k0"; |
9b70259d JH |
5374 | else |
5375 | abort(); | |
5376 | ||
5377 | default: | |
5378 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5379 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5380 | if (GET_CODE (operands[2]) == CONST_INT | |
5381 | && (INTVAL (operands[2]) == 128 | |
5382 | || (INTVAL (operands[2]) < 0 | |
5383 | && INTVAL (operands[2]) != -128))) | |
5384 | { | |
5385 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5386 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 5387 | } |
0f40f9f7 | 5388 | return "add{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 5389 | } |
0f40f9f7 | 5390 | } |
9b70259d JH |
5391 | [(set (attr "type") |
5392 | (cond [(eq_attr "alternative" "1") | |
5393 | (const_string "lea") | |
5394 | ; Current assemblers are broken and do not allow @GOTOFF in | |
5395 | ; ought but a memory context. | |
5396 | (match_operand:SI 2 "pic_symbolic_operand" "") | |
5397 | (const_string "lea") | |
5398 | (match_operand:SI 2 "incdec_operand" "") | |
5399 | (const_string "incdec") | |
5400 | ] | |
5401 | (const_string "alu"))) | |
5402 | (set_attr "mode" "SI")]) | |
5403 | ||
5404 | ;; Convert lea to the lea pattern to avoid flags dependency. | |
5405 | (define_split | |
5406 | [(set (match_operand:DI 0 "register_operand" "") | |
5407 | (zero_extend:DI | |
5408 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5409 | (match_operand:SI 2 "nonmemory_operand" "")))) | |
5410 | (clobber (reg:CC 17))] | |
5411 | "reload_completed | |
5412 | && true_regnum (operands[0]) != true_regnum (operands[1])" | |
5413 | [(set (match_dup 0) | |
5414 | (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))] | |
9b70259d JH |
5415 | { |
5416 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
5417 | operands[2] = gen_lowpart (Pmode, operands[2]); | |
0f40f9f7 | 5418 | }) |
9b70259d JH |
5419 | |
5420 | (define_insn "*addsi_2" | |
5421 | [(set (reg 17) | |
5422 | (compare | |
5423 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
5424 | (match_operand:SI 2 "general_operand" "rmni,rni")) | |
5425 | (const_int 0))) | |
5426 | (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") | |
5427 | (plus:SI (match_dup 1) (match_dup 2)))] | |
5428 | "ix86_match_ccmode (insn, CCGOCmode) | |
5429 | && ix86_binary_operator_ok (PLUS, SImode, operands) | |
5430 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 5431 | ought but a memory context. */ |
9b70259d | 5432 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
5433 | { |
5434 | switch (get_attr_type (insn)) | |
5435 | { | |
5436 | case TYPE_INCDEC: | |
5437 | if (! rtx_equal_p (operands[0], operands[1])) | |
5438 | abort (); | |
5439 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5440 | return "inc{l}\t%0"; |
9b70259d | 5441 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5442 | return "dec{l}\t%0"; |
9b70259d JH |
5443 | else |
5444 | abort(); | |
5445 | ||
5446 | default: | |
5447 | if (! rtx_equal_p (operands[0], operands[1])) | |
5448 | abort (); | |
5449 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5450 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5451 | if (GET_CODE (operands[2]) == CONST_INT | |
5452 | && (INTVAL (operands[2]) == 128 | |
5453 | || (INTVAL (operands[2]) < 0 | |
5454 | && INTVAL (operands[2]) != -128))) | |
5455 | { | |
5456 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5457 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5458 | } |
0f40f9f7 | 5459 | return "add{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5460 | } |
0f40f9f7 | 5461 | } |
9b70259d JH |
5462 | [(set (attr "type") |
5463 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
5464 | (const_string "incdec") | |
5465 | (const_string "alu"))) | |
5466 | (set_attr "mode" "SI")]) | |
5467 | ||
5468 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand | |
5469 | (define_insn "*addsi_2_zext" | |
5470 | [(set (reg 17) | |
5471 | (compare | |
5472 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
5473 | (match_operand:SI 2 "general_operand" "rmni")) | |
5474 | (const_int 0))) | |
5475 | (set (match_operand:DI 0 "register_operand" "=r") | |
5476 | (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] | |
5477 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
5478 | && ix86_binary_operator_ok (PLUS, SImode, operands) | |
5479 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 5480 | ought but a memory context. */ |
9b70259d | 5481 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
5482 | { |
5483 | switch (get_attr_type (insn)) | |
5484 | { | |
5485 | case TYPE_INCDEC: | |
5486 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5487 | return "inc{l}\t%k0"; |
9b70259d | 5488 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5489 | return "dec{l}\t%k0"; |
9b70259d JH |
5490 | else |
5491 | abort(); | |
5492 | ||
5493 | default: | |
5494 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5495 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5496 | if (GET_CODE (operands[2]) == CONST_INT | |
5497 | && (INTVAL (operands[2]) == 128 | |
5498 | || (INTVAL (operands[2]) < 0 | |
5499 | && INTVAL (operands[2]) != -128))) | |
5500 | { | |
5501 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5502 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 5503 | } |
0f40f9f7 | 5504 | return "add{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 5505 | } |
0f40f9f7 | 5506 | } |
9b70259d JH |
5507 | [(set (attr "type") |
5508 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
5509 | (const_string "incdec") | |
5510 | (const_string "alu"))) | |
5511 | (set_attr "mode" "SI")]) | |
5512 | ||
5513 | (define_insn "*addsi_3" | |
5514 | [(set (reg 17) | |
5515 | (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni")) | |
5516 | (match_operand:SI 1 "nonimmediate_operand" "%0"))) | |
5517 | (clobber (match_scratch:SI 0 "=r"))] | |
5518 | "ix86_match_ccmode (insn, CCZmode) | |
5519 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) | |
5520 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 5521 | ought but a memory context. */ |
9b70259d | 5522 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
5523 | { |
5524 | switch (get_attr_type (insn)) | |
5525 | { | |
5526 | case TYPE_INCDEC: | |
5527 | if (! rtx_equal_p (operands[0], operands[1])) | |
5528 | abort (); | |
5529 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5530 | return "inc{l}\t%0"; |
9b70259d | 5531 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5532 | return "dec{l}\t%0"; |
9b70259d JH |
5533 | else |
5534 | abort(); | |
5535 | ||
5536 | default: | |
5537 | if (! rtx_equal_p (operands[0], operands[1])) | |
5538 | abort (); | |
5539 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5540 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5541 | if (GET_CODE (operands[2]) == CONST_INT | |
5542 | && (INTVAL (operands[2]) == 128 | |
5543 | || (INTVAL (operands[2]) < 0 | |
5544 | && INTVAL (operands[2]) != -128))) | |
5545 | { | |
5546 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5547 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5548 | } |
0f40f9f7 | 5549 | return "add{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5550 | } |
0f40f9f7 | 5551 | } |
9b70259d JH |
5552 | [(set (attr "type") |
5553 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
5554 | (const_string "incdec") | |
5555 | (const_string "alu"))) | |
5556 | (set_attr "mode" "SI")]) | |
5557 | ||
5558 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand | |
5559 | (define_insn "*addsi_3_zext" | |
5560 | [(set (reg 17) | |
5561 | (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni")) | |
5562 | (match_operand:SI 1 "nonimmediate_operand" "%0"))) | |
5563 | (set (match_operand:DI 0 "register_operand" "=r") | |
5564 | (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))] | |
5565 | "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode) | |
5566 | && ix86_binary_operator_ok (PLUS, SImode, operands) | |
5567 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 5568 | ought but a memory context. */ |
9b70259d | 5569 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
5570 | { |
5571 | switch (get_attr_type (insn)) | |
5572 | { | |
5573 | case TYPE_INCDEC: | |
5574 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5575 | return "inc{l}\t%k0"; |
9b70259d | 5576 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5577 | return "dec{l}\t%k0"; |
9b70259d JH |
5578 | else |
5579 | abort(); | |
5580 | ||
5581 | default: | |
5582 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5583 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5584 | if (GET_CODE (operands[2]) == CONST_INT | |
5585 | && (INTVAL (operands[2]) == 128 | |
5586 | || (INTVAL (operands[2]) < 0 | |
5587 | && INTVAL (operands[2]) != -128))) | |
5588 | { | |
5589 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5590 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 5591 | } |
0f40f9f7 | 5592 | return "add{l}\t{%2, %k0|%k0, %2}"; |
9b70259d | 5593 | } |
0f40f9f7 | 5594 | } |
9b70259d JH |
5595 | [(set (attr "type") |
5596 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
5597 | (const_string "incdec") | |
5598 | (const_string "alu"))) | |
5599 | (set_attr "mode" "SI")]) | |
5600 | ||
5601 | ; For comparisons agains 1, -1 and 128, we may generate better code | |
5602 | ; by converting cmp to add, inc or dec as done by peephole2. This pattern | |
5603 | ; is matched then. We can't accept general immediate, because for | |
5604 | ; case of overflows, the result is messed up. | |
5605 | ; This pattern also don't hold of 0x80000000, since the value overflows | |
5606 | ; when negated. | |
d6a7951f | 5607 | ; Also carry flag is reversed compared to cmp, so this conversion is valid |
9b70259d JH |
5608 | ; only for comparisons not depending on it. |
5609 | (define_insn "*addsi_4" | |
5610 | [(set (reg 17) | |
5611 | (compare (match_operand:SI 1 "nonimmediate_operand" "0") | |
5612 | (match_operand:SI 2 "const_int_operand" "n"))) | |
5613 | (clobber (match_scratch:SI 0 "=rm"))] | |
5614 | "ix86_match_ccmode (insn, CCGCmode) | |
5615 | && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000" | |
9b70259d JH |
5616 | { |
5617 | switch (get_attr_type (insn)) | |
5618 | { | |
5619 | case TYPE_INCDEC: | |
5620 | if (operands[2] == constm1_rtx) | |
0f40f9f7 | 5621 | return "inc{l}\t%0"; |
9b70259d | 5622 | else if (operands[2] == const1_rtx) |
0f40f9f7 | 5623 | return "dec{l}\t%0"; |
9b70259d JH |
5624 | else |
5625 | abort(); | |
5626 | ||
5627 | default: | |
5628 | if (! rtx_equal_p (operands[0], operands[1])) | |
5629 | abort (); | |
5630 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5631 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5632 | if ((INTVAL (operands[2]) == -128 | |
5633 | || (INTVAL (operands[2]) > 0 | |
5634 | && INTVAL (operands[2]) != 128))) | |
0f40f9f7 | 5635 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5636 | operands[2] = GEN_INT (-INTVAL (operands[2])); |
0f40f9f7 | 5637 | return "add{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5638 | } |
0f40f9f7 | 5639 | } |
9b70259d JH |
5640 | [(set (attr "type") |
5641 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
5642 | (const_string "incdec") | |
5643 | (const_string "alu"))) | |
5644 | (set_attr "mode" "SI")]) | |
5645 | ||
5646 | (define_insn "*addsi_5" | |
5647 | [(set (reg 17) | |
5648 | (compare | |
5649 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
5650 | (match_operand:SI 2 "general_operand" "rmni")) | |
5651 | (const_int 0))) | |
5652 | (clobber (match_scratch:SI 0 "=r"))] | |
5653 | "ix86_match_ccmode (insn, CCGOCmode) | |
5654 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM) | |
5655 | /* Current assemblers are broken and do not allow @GOTOFF in | |
892a2d68 | 5656 | ought but a memory context. */ |
9b70259d | 5657 | && ! pic_symbolic_operand (operands[2], VOIDmode)" |
9b70259d JH |
5658 | { |
5659 | switch (get_attr_type (insn)) | |
5660 | { | |
5661 | case TYPE_INCDEC: | |
5662 | if (! rtx_equal_p (operands[0], operands[1])) | |
5663 | abort (); | |
5664 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5665 | return "inc{l}\t%0"; |
9b70259d | 5666 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5667 | return "dec{l}\t%0"; |
9b70259d JH |
5668 | else |
5669 | abort(); | |
5670 | ||
5671 | default: | |
5672 | if (! rtx_equal_p (operands[0], operands[1])) | |
5673 | abort (); | |
5674 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5675 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5676 | if (GET_CODE (operands[2]) == CONST_INT | |
5677 | && (INTVAL (operands[2]) == 128 | |
5678 | || (INTVAL (operands[2]) < 0 | |
5679 | && INTVAL (operands[2]) != -128))) | |
5680 | { | |
5681 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5682 | return "sub{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5683 | } |
0f40f9f7 | 5684 | return "add{l}\t{%2, %0|%0, %2}"; |
9b70259d | 5685 | } |
0f40f9f7 | 5686 | } |
9b70259d JH |
5687 | [(set (attr "type") |
5688 | (if_then_else (match_operand:SI 2 "incdec_operand" "") | |
5689 | (const_string "incdec") | |
5690 | (const_string "alu"))) | |
5691 | (set_attr "mode" "SI")]) | |
5692 | ||
5693 | (define_expand "addhi3" | |
5694 | [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5695 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5696 | (match_operand:HI 2 "general_operand" ""))) | |
5697 | (clobber (reg:CC 17))])] | |
5698 | "TARGET_HIMODE_MATH" | |
5699 | "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;") | |
5700 | ||
5701 | ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah | |
5702 | ;; type optimizations enabled by define-splits. This is not important | |
5703 | ;; for PII, and in fact harmful because of partial register stalls. | |
5704 | ||
5705 | (define_insn "*addhi_1_lea" | |
5706 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") | |
5707 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r") | |
5708 | (match_operand:HI 2 "general_operand" "ri,rm,rni"))) | |
5709 | (clobber (reg:CC 17))] | |
5710 | "!TARGET_PARTIAL_REG_STALL | |
5711 | && ix86_binary_operator_ok (PLUS, HImode, operands)" | |
9b70259d JH |
5712 | { |
5713 | switch (get_attr_type (insn)) | |
5714 | { | |
5715 | case TYPE_LEA: | |
0f40f9f7 | 5716 | return "#"; |
9b70259d JH |
5717 | case TYPE_INCDEC: |
5718 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5719 | return "inc{w}\t%0"; |
2f41793e | 5720 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5721 | return "dec{w}\t%0"; |
9b70259d JH |
5722 | abort(); |
5723 | ||
5724 | default: | |
5725 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5726 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5727 | if (GET_CODE (operands[2]) == CONST_INT | |
5728 | && (INTVAL (operands[2]) == 128 | |
5729 | || (INTVAL (operands[2]) < 0 | |
5730 | && INTVAL (operands[2]) != -128))) | |
5731 | { | |
5732 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5733 | return "sub{w}\t{%2, %0|%0, %2}"; |
9b70259d | 5734 | } |
0f40f9f7 | 5735 | return "add{w}\t{%2, %0|%0, %2}"; |
9b70259d | 5736 | } |
0f40f9f7 | 5737 | } |
9b70259d JH |
5738 | [(set (attr "type") |
5739 | (if_then_else (eq_attr "alternative" "2") | |
5740 | (const_string "lea") | |
5741 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
5742 | (const_string "incdec") | |
5743 | (const_string "alu")))) | |
5744 | (set_attr "mode" "HI,HI,SI")]) | |
5745 | ||
5746 | (define_insn "*addhi_1" | |
5747 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") | |
5748 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
5749 | (match_operand:HI 2 "general_operand" "ri,rm"))) | |
5750 | (clobber (reg:CC 17))] | |
5751 | "TARGET_PARTIAL_REG_STALL | |
5752 | && ix86_binary_operator_ok (PLUS, HImode, operands)" | |
9b70259d JH |
5753 | { |
5754 | switch (get_attr_type (insn)) | |
5755 | { | |
5756 | case TYPE_INCDEC: | |
5757 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5758 | return "inc{w}\t%0"; |
2f41793e | 5759 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5760 | return "dec{w}\t%0"; |
e075ae69 | 5761 | abort(); |
7c802a40 | 5762 | |
e075ae69 RH |
5763 | default: |
5764 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5765 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5766 | if (GET_CODE (operands[2]) == CONST_INT | |
5767 | && (INTVAL (operands[2]) == 128 | |
5768 | || (INTVAL (operands[2]) < 0 | |
5769 | && INTVAL (operands[2]) != -128))) | |
5770 | { | |
5771 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5772 | return "sub{w}\t{%2, %0|%0, %2}"; |
e075ae69 | 5773 | } |
0f40f9f7 | 5774 | return "add{w}\t{%2, %0|%0, %2}"; |
7c802a40 | 5775 | } |
0f40f9f7 | 5776 | } |
e075ae69 RH |
5777 | [(set (attr "type") |
5778 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
5779 | (const_string "incdec") | |
6ef67412 JH |
5780 | (const_string "alu"))) |
5781 | (set_attr "mode" "HI")]) | |
7c802a40 | 5782 | |
e075ae69 | 5783 | (define_insn "*addhi_2" |
16189740 RH |
5784 | [(set (reg 17) |
5785 | (compare | |
e075ae69 RH |
5786 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") |
5787 | (match_operand:HI 2 "general_operand" "rmni,rni")) | |
5788 | (const_int 0))) | |
5789 | (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") | |
5790 | (plus:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 5791 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 5792 | && ix86_binary_operator_ok (PLUS, HImode, operands)" |
e075ae69 RH |
5793 | { |
5794 | switch (get_attr_type (insn)) | |
b980bec0 | 5795 | { |
e075ae69 RH |
5796 | case TYPE_INCDEC: |
5797 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5798 | return "inc{w}\t%0"; |
2f41793e | 5799 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5800 | return "dec{w}\t%0"; |
e075ae69 | 5801 | abort(); |
b980bec0 | 5802 | |
e075ae69 RH |
5803 | default: |
5804 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5805 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5806 | if (GET_CODE (operands[2]) == CONST_INT | |
5807 | && (INTVAL (operands[2]) == 128 | |
5808 | || (INTVAL (operands[2]) < 0 | |
5809 | && INTVAL (operands[2]) != -128))) | |
5810 | { | |
5811 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5812 | return "sub{w}\t{%2, %0|%0, %2}"; |
e075ae69 | 5813 | } |
0f40f9f7 | 5814 | return "add{w}\t{%2, %0|%0, %2}"; |
b980bec0 | 5815 | } |
0f40f9f7 | 5816 | } |
e075ae69 RH |
5817 | [(set (attr "type") |
5818 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
5819 | (const_string "incdec") | |
6ef67412 JH |
5820 | (const_string "alu"))) |
5821 | (set_attr "mode" "HI")]) | |
e075ae69 RH |
5822 | |
5823 | (define_insn "*addhi_3" | |
d90ffc8d | 5824 | [(set (reg 17) |
7e08e190 JH |
5825 | (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni")) |
5826 | (match_operand:HI 1 "nonimmediate_operand" "%0"))) | |
d90ffc8d | 5827 | (clobber (match_scratch:HI 0 "=r"))] |
7e08e190 | 5828 | "ix86_match_ccmode (insn, CCZmode) |
d90ffc8d | 5829 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
d90ffc8d JH |
5830 | { |
5831 | switch (get_attr_type (insn)) | |
5832 | { | |
5833 | case TYPE_INCDEC: | |
5834 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5835 | return "inc{w}\t%0"; |
2f41793e | 5836 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5837 | return "dec{w}\t%0"; |
d90ffc8d JH |
5838 | abort(); |
5839 | ||
5840 | default: | |
5841 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5842 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5843 | if (GET_CODE (operands[2]) == CONST_INT | |
5844 | && (INTVAL (operands[2]) == 128 | |
5845 | || (INTVAL (operands[2]) < 0 | |
5846 | && INTVAL (operands[2]) != -128))) | |
5847 | { | |
5848 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5849 | return "sub{w}\t{%2, %0|%0, %2}"; |
d90ffc8d | 5850 | } |
0f40f9f7 | 5851 | return "add{w}\t{%2, %0|%0, %2}"; |
d90ffc8d | 5852 | } |
0f40f9f7 | 5853 | } |
d90ffc8d JH |
5854 | [(set (attr "type") |
5855 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
5856 | (const_string "incdec") | |
5857 | (const_string "alu"))) | |
5858 | (set_attr "mode" "HI")]) | |
5859 | ||
7e08e190 | 5860 | ; See comments above addsi_3_imm for details. |
d90ffc8d | 5861 | (define_insn "*addhi_4" |
9076b9c1 | 5862 | [(set (reg 17) |
7e08e190 JH |
5863 | (compare (match_operand:HI 1 "nonimmediate_operand" "0") |
5864 | (match_operand:HI 2 "const_int_operand" "n"))) | |
5865 | (clobber (match_scratch:HI 0 "=rm"))] | |
5866 | "ix86_match_ccmode (insn, CCGCmode) | |
5867 | && (INTVAL (operands[2]) & 0xffff) != 0x8000" | |
7e08e190 JH |
5868 | { |
5869 | switch (get_attr_type (insn)) | |
5870 | { | |
5871 | case TYPE_INCDEC: | |
2f41793e | 5872 | if (operands[2] == constm1_rtx) |
0f40f9f7 | 5873 | return "inc{w}\t%0"; |
7e08e190 | 5874 | else if (operands[2] == const1_rtx) |
0f40f9f7 | 5875 | return "dec{w}\t%0"; |
7e08e190 JH |
5876 | else |
5877 | abort(); | |
5878 | ||
5879 | default: | |
5880 | if (! rtx_equal_p (operands[0], operands[1])) | |
5881 | abort (); | |
5882 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5883 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5884 | if ((INTVAL (operands[2]) == -128 | |
5885 | || (INTVAL (operands[2]) > 0 | |
5886 | && INTVAL (operands[2]) != 128))) | |
0f40f9f7 | 5887 | return "sub{w}\t{%2, %0|%0, %2}"; |
7e08e190 | 5888 | operands[2] = GEN_INT (-INTVAL (operands[2])); |
0f40f9f7 | 5889 | return "add{w}\t{%2, %0|%0, %2}"; |
7e08e190 | 5890 | } |
0f40f9f7 | 5891 | } |
7e08e190 JH |
5892 | [(set (attr "type") |
5893 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
5894 | (const_string "incdec") | |
5895 | (const_string "alu"))) | |
5896 | (set_attr "mode" "SI")]) | |
b980bec0 | 5897 | |
d90ffc8d | 5898 | |
7e08e190 | 5899 | (define_insn "*addhi_5" |
9076b9c1 JH |
5900 | [(set (reg 17) |
5901 | (compare | |
5902 | (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0") | |
5903 | (match_operand:HI 2 "general_operand" "rmni")) | |
5904 | (const_int 0))) | |
5905 | (clobber (match_scratch:HI 0 "=r"))] | |
5906 | "ix86_match_ccmode (insn, CCGOCmode) | |
5907 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
9076b9c1 JH |
5908 | { |
5909 | switch (get_attr_type (insn)) | |
5910 | { | |
5911 | case TYPE_INCDEC: | |
5912 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5913 | return "inc{w}\t%0"; |
2f41793e | 5914 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5915 | return "dec{w}\t%0"; |
9076b9c1 JH |
5916 | abort(); |
5917 | ||
5918 | default: | |
5919 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5920 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5921 | if (GET_CODE (operands[2]) == CONST_INT | |
5922 | && (INTVAL (operands[2]) == 128 | |
5923 | || (INTVAL (operands[2]) < 0 | |
5924 | && INTVAL (operands[2]) != -128))) | |
5925 | { | |
5926 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 5927 | return "sub{w}\t{%2, %0|%0, %2}"; |
9076b9c1 | 5928 | } |
0f40f9f7 | 5929 | return "add{w}\t{%2, %0|%0, %2}"; |
9076b9c1 | 5930 | } |
0f40f9f7 | 5931 | } |
9076b9c1 JH |
5932 | [(set (attr "type") |
5933 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
5934 | (const_string "incdec") | |
5935 | (const_string "alu"))) | |
5936 | (set_attr "mode" "HI")]) | |
5937 | ||
e075ae69 | 5938 | (define_expand "addqi3" |
4cbfbb1b JH |
5939 | [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") |
5940 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
e075ae69 RH |
5941 | (match_operand:QI 2 "general_operand" ""))) |
5942 | (clobber (reg:CC 17))])] | |
d9f32422 | 5943 | "TARGET_QIMODE_MATH" |
e075ae69 RH |
5944 | "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;") |
5945 | ||
5946 | ;; %%% Potential partial reg stall on alternative 2. What to do? | |
58787064 JH |
5947 | (define_insn "*addqi_1_lea" |
5948 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r") | |
5949 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r") | |
5950 | (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn"))) | |
5951 | (clobber (reg:CC 17))] | |
5952 | "!TARGET_PARTIAL_REG_STALL | |
5953 | && ix86_binary_operator_ok (PLUS, QImode, operands)" | |
58787064 JH |
5954 | { |
5955 | int widen = (which_alternative == 2); | |
5956 | switch (get_attr_type (insn)) | |
5957 | { | |
5958 | case TYPE_LEA: | |
0f40f9f7 | 5959 | return "#"; |
58787064 JH |
5960 | case TYPE_INCDEC: |
5961 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 5962 | return widen ? "inc{l}\t%k0" : "inc{b}\t%0"; |
2f41793e | 5963 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 5964 | return widen ? "dec{l}\t%k0" : "dec{b}\t%0"; |
58787064 JH |
5965 | abort(); |
5966 | ||
5967 | default: | |
5968 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
5969 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
5970 | if (GET_CODE (operands[2]) == CONST_INT | |
5971 | && (INTVAL (operands[2]) == 128 | |
5972 | || (INTVAL (operands[2]) < 0 | |
5973 | && INTVAL (operands[2]) != -128))) | |
5974 | { | |
5975 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
5976 | if (widen) | |
0f40f9f7 | 5977 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
58787064 | 5978 | else |
0f40f9f7 | 5979 | return "sub{b}\t{%2, %0|%0, %2}"; |
58787064 JH |
5980 | } |
5981 | if (widen) | |
0f40f9f7 | 5982 | return "add{l}\t{%k2, %k0|%k0, %k2}"; |
58787064 | 5983 | else |
0f40f9f7 | 5984 | return "add{b}\t{%2, %0|%0, %2}"; |
58787064 | 5985 | } |
0f40f9f7 | 5986 | } |
58787064 JH |
5987 | [(set (attr "type") |
5988 | (if_then_else (eq_attr "alternative" "3") | |
5989 | (const_string "lea") | |
adc88131 | 5990 | (if_then_else (match_operand:QI 2 "incdec_operand" "") |
58787064 JH |
5991 | (const_string "incdec") |
5992 | (const_string "alu")))) | |
adc88131 | 5993 | (set_attr "mode" "QI,QI,SI,SI")]) |
58787064 | 5994 | |
e075ae69 | 5995 | (define_insn "*addqi_1" |
7c6b971d | 5996 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") |
e075ae69 | 5997 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") |
7c6b971d | 5998 | (match_operand:QI 2 "general_operand" "qn,qmn,rn"))) |
e075ae69 | 5999 | (clobber (reg:CC 17))] |
58787064 JH |
6000 | "TARGET_PARTIAL_REG_STALL |
6001 | && ix86_binary_operator_ok (PLUS, QImode, operands)" | |
e075ae69 RH |
6002 | { |
6003 | int widen = (which_alternative == 2); | |
6004 | switch (get_attr_type (insn)) | |
5bc7cd8e | 6005 | { |
e075ae69 RH |
6006 | case TYPE_INCDEC: |
6007 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6008 | return widen ? "inc{l}\t%k0" : "inc{b}\t%0"; |
2f41793e | 6009 | else if (operands[2] == constm1_rtx) |
0f40f9f7 | 6010 | return widen ? "dec{l}\t%k0" : "dec{b}\t%0"; |
e075ae69 | 6011 | abort(); |
5bc7cd8e | 6012 | |
e075ae69 RH |
6013 | default: |
6014 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
6015 | Exceptions: -128 encodes smaller than 128, so swap sign and op. */ | |
6016 | if (GET_CODE (operands[2]) == CONST_INT | |
6017 | && (INTVAL (operands[2]) == 128 | |
6018 | || (INTVAL (operands[2]) < 0 | |
6019 | && INTVAL (operands[2]) != -128))) | |
5bc7cd8e | 6020 | { |
e075ae69 RH |
6021 | operands[2] = GEN_INT (-INTVAL (operands[2])); |
6022 | if (widen) | |
0f40f9f7 | 6023 | return "sub{l}\t{%2, %k0|%k0, %2}"; |
e075ae69 | 6024 | else |
0f40f9f7 | 6025 | return "sub{b}\t{%2, %0|%0, %2}"; |
5bc7cd8e | 6026 | } |
e075ae69 | 6027 | if (widen) |
0f40f9f7 | 6028 | return "add{l}\t{%k2, %k0|%k0, %k2}"; |
e075ae69 | 6029 | else |
0f40f9f7 | 6030 | return "add{b}\t{%2, %0|%0, %2}"; |
5bc7cd8e | 6031 | } |
0f40f9f7 | 6032 | } |
e075ae69 RH |
6033 | [(set (attr "type") |
6034 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6035 | (const_string "incdec") | |
6ef67412 JH |
6036 | (const_string "alu"))) |
6037 | (set_attr "mode" "QI,QI,SI")]) | |
e075ae69 | 6038 | |
2f41793e JH |
6039 | (define_insn "*addqi_1_slp" |
6040 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) | |
6041 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") | |
6042 | (match_operand:QI 2 "general_operand" "qn,qnm"))) | |
6043 | (clobber (reg:CC 17))] | |
6044 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
6045 | && ix86_binary_operator_ok (PLUS, QImode, operands)" | |
6046 | { | |
6047 | switch (get_attr_type (insn)) | |
6048 | { | |
6049 | case TYPE_INCDEC: | |
6050 | if (operands[2] == const1_rtx) | |
6051 | return "inc{b}\t%0"; | |
6052 | else if (operands[2] == constm1_rtx) | |
6053 | return "dec{b}\t%0"; | |
6054 | abort(); | |
6055 | ||
6056 | default: | |
6057 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */ | |
6058 | if (GET_CODE (operands[2]) == CONST_INT | |
6059 | && INTVAL (operands[2]) < 0) | |
6060 | { | |
6061 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
6062 | return "sub{b}\t{%2, %0|%0, %2}"; | |
6063 | } | |
6064 | return "add{b}\t{%2, %0|%0, %2}"; | |
6065 | } | |
6066 | } | |
6067 | [(set (attr "type") | |
6068 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6069 | (const_string "incdec") | |
6070 | (const_string "alu"))) | |
6071 | (set_attr "mode" "QI")]) | |
6072 | ||
e075ae69 | 6073 | (define_insn "*addqi_2" |
16189740 RH |
6074 | [(set (reg 17) |
6075 | (compare | |
e075ae69 RH |
6076 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") |
6077 | (match_operand:QI 2 "general_operand" "qmni,qni")) | |
6078 | (const_int 0))) | |
6079 | (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") | |
6080 | (plus:QI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 6081 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 6082 | && ix86_binary_operator_ok (PLUS, QImode, operands)" |
e075ae69 RH |
6083 | { |
6084 | switch (get_attr_type (insn)) | |
6085 | { | |
6086 | case TYPE_INCDEC: | |
6087 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6088 | return "inc{b}\t%0"; |
e075ae69 RH |
6089 | else if (operands[2] == constm1_rtx |
6090 | || (GET_CODE (operands[2]) == CONST_INT | |
6091 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6092 | return "dec{b}\t%0"; |
e075ae69 | 6093 | abort(); |
5bc7cd8e | 6094 | |
e075ae69 RH |
6095 | default: |
6096 | /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */ | |
6097 | if (GET_CODE (operands[2]) == CONST_INT | |
6098 | && INTVAL (operands[2]) < 0) | |
6099 | { | |
6100 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6101 | return "sub{b}\t{%2, %0|%0, %2}"; |
e075ae69 | 6102 | } |
0f40f9f7 | 6103 | return "add{b}\t{%2, %0|%0, %2}"; |
e075ae69 | 6104 | } |
0f40f9f7 | 6105 | } |
e075ae69 RH |
6106 | [(set (attr "type") |
6107 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6108 | (const_string "incdec") | |
6ef67412 JH |
6109 | (const_string "alu"))) |
6110 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
6111 | |
6112 | (define_insn "*addqi_3" | |
d90ffc8d | 6113 | [(set (reg 17) |
7e08e190 JH |
6114 | (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni")) |
6115 | (match_operand:QI 1 "nonimmediate_operand" "%0"))) | |
6116 | (clobber (match_scratch:QI 0 "=q"))] | |
6117 | "ix86_match_ccmode (insn, CCZmode) | |
d90ffc8d | 6118 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
d90ffc8d JH |
6119 | { |
6120 | switch (get_attr_type (insn)) | |
6121 | { | |
6122 | case TYPE_INCDEC: | |
6123 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6124 | return "inc{b}\t%0"; |
d90ffc8d JH |
6125 | else if (operands[2] == constm1_rtx |
6126 | || (GET_CODE (operands[2]) == CONST_INT | |
6127 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6128 | return "dec{b}\t%0"; |
d90ffc8d JH |
6129 | abort(); |
6130 | ||
6131 | default: | |
6132 | /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */ | |
6133 | if (GET_CODE (operands[2]) == CONST_INT | |
6134 | && INTVAL (operands[2]) < 0) | |
6135 | { | |
6136 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6137 | return "sub{b}\t{%2, %0|%0, %2}"; |
d90ffc8d | 6138 | } |
0f40f9f7 | 6139 | return "add{b}\t{%2, %0|%0, %2}"; |
d90ffc8d | 6140 | } |
0f40f9f7 | 6141 | } |
d90ffc8d JH |
6142 | [(set (attr "type") |
6143 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6144 | (const_string "incdec") | |
6145 | (const_string "alu"))) | |
6146 | (set_attr "mode" "QI")]) | |
6147 | ||
7e08e190 | 6148 | ; See comments above addsi_3_imm for details. |
d90ffc8d | 6149 | (define_insn "*addqi_4" |
9076b9c1 | 6150 | [(set (reg 17) |
7e08e190 JH |
6151 | (compare (match_operand:QI 1 "nonimmediate_operand" "0") |
6152 | (match_operand:QI 2 "const_int_operand" "n"))) | |
6153 | (clobber (match_scratch:QI 0 "=qm"))] | |
6154 | "ix86_match_ccmode (insn, CCGCmode) | |
6155 | && (INTVAL (operands[2]) & 0xff) != 0x80" | |
7e08e190 JH |
6156 | { |
6157 | switch (get_attr_type (insn)) | |
6158 | { | |
6159 | case TYPE_INCDEC: | |
6160 | if (operands[2] == constm1_rtx | |
6161 | || (GET_CODE (operands[2]) == CONST_INT | |
6162 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6163 | return "inc{b}\t%0"; |
7e08e190 | 6164 | else if (operands[2] == const1_rtx) |
0f40f9f7 | 6165 | return "dec{b}\t%0"; |
7e08e190 JH |
6166 | else |
6167 | abort(); | |
6168 | ||
6169 | default: | |
6170 | if (! rtx_equal_p (operands[0], operands[1])) | |
6171 | abort (); | |
6172 | if (INTVAL (operands[2]) < 0) | |
6173 | { | |
6174 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6175 | return "add{b}\t{%2, %0|%0, %2}"; |
7e08e190 | 6176 | } |
0f40f9f7 | 6177 | return "sub{b}\t{%2, %0|%0, %2}"; |
7e08e190 | 6178 | } |
0f40f9f7 | 6179 | } |
7e08e190 JH |
6180 | [(set (attr "type") |
6181 | (if_then_else (match_operand:HI 2 "incdec_operand" "") | |
6182 | (const_string "incdec") | |
6183 | (const_string "alu"))) | |
6ef67412 | 6184 | (set_attr "mode" "QI")]) |
886c62d1 | 6185 | |
9dcbdc7e | 6186 | |
d90ffc8d | 6187 | (define_insn "*addqi_5" |
9076b9c1 JH |
6188 | [(set (reg 17) |
6189 | (compare | |
6190 | (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0") | |
6191 | (match_operand:QI 2 "general_operand" "qmni")) | |
6192 | (const_int 0))) | |
7e08e190 | 6193 | (clobber (match_scratch:QI 0 "=q"))] |
9076b9c1 JH |
6194 | "ix86_match_ccmode (insn, CCGOCmode) |
6195 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
9076b9c1 JH |
6196 | { |
6197 | switch (get_attr_type (insn)) | |
6198 | { | |
6199 | case TYPE_INCDEC: | |
6200 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6201 | return "inc{b}\t%0"; |
9076b9c1 JH |
6202 | else if (operands[2] == constm1_rtx |
6203 | || (GET_CODE (operands[2]) == CONST_INT | |
6204 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6205 | return "dec{b}\t%0"; |
9076b9c1 JH |
6206 | abort(); |
6207 | ||
6208 | default: | |
6209 | /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */ | |
6210 | if (GET_CODE (operands[2]) == CONST_INT | |
6211 | && INTVAL (operands[2]) < 0) | |
6212 | { | |
6213 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 6214 | return "sub{b}\t{%2, %0|%0, %2}"; |
9076b9c1 | 6215 | } |
0f40f9f7 | 6216 | return "add{b}\t{%2, %0|%0, %2}"; |
9076b9c1 | 6217 | } |
0f40f9f7 | 6218 | } |
9076b9c1 JH |
6219 | [(set (attr "type") |
6220 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6221 | (const_string "incdec") | |
6222 | (const_string "alu"))) | |
6223 | (set_attr "mode" "QI")]) | |
6224 | ||
e075ae69 RH |
6225 | |
6226 | (define_insn "addqi_ext_1" | |
3522082b | 6227 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
6228 | (const_int 8) |
6229 | (const_int 8)) | |
6230 | (plus:SI | |
6231 | (zero_extract:SI | |
6232 | (match_operand 1 "ext_register_operand" "0") | |
6233 | (const_int 8) | |
6234 | (const_int 8)) | |
3522082b | 6235 | (match_operand:QI 2 "general_operand" "Qmn"))) |
e075ae69 | 6236 | (clobber (reg:CC 17))] |
d2836273 | 6237 | "!TARGET_64BIT" |
d2836273 JH |
6238 | { |
6239 | switch (get_attr_type (insn)) | |
6240 | { | |
6241 | case TYPE_INCDEC: | |
6242 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6243 | return "inc{b}\t%h0"; |
d2836273 JH |
6244 | else if (operands[2] == constm1_rtx |
6245 | || (GET_CODE (operands[2]) == CONST_INT | |
6246 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6247 | return "dec{b}\t%h0"; |
d2836273 JH |
6248 | abort(); |
6249 | ||
6250 | default: | |
0f40f9f7 | 6251 | return "add{b}\t{%2, %h0|%h0, %2}"; |
d2836273 | 6252 | } |
0f40f9f7 | 6253 | } |
d2836273 JH |
6254 | [(set (attr "type") |
6255 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6256 | (const_string "incdec") | |
6257 | (const_string "alu"))) | |
6258 | (set_attr "mode" "QI")]) | |
6259 | ||
6260 | (define_insn "*addqi_ext_1_rex64" | |
6261 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
6262 | (const_int 8) | |
6263 | (const_int 8)) | |
6264 | (plus:SI | |
6265 | (zero_extract:SI | |
6266 | (match_operand 1 "ext_register_operand" "0") | |
6267 | (const_int 8) | |
6268 | (const_int 8)) | |
6269 | (match_operand:QI 2 "nonmemory_operand" "Qn"))) | |
6270 | (clobber (reg:CC 17))] | |
6271 | "TARGET_64BIT" | |
e075ae69 RH |
6272 | { |
6273 | switch (get_attr_type (insn)) | |
6274 | { | |
6275 | case TYPE_INCDEC: | |
6276 | if (operands[2] == const1_rtx) | |
0f40f9f7 | 6277 | return "inc{b}\t%h0"; |
e075ae69 RH |
6278 | else if (operands[2] == constm1_rtx |
6279 | || (GET_CODE (operands[2]) == CONST_INT | |
6280 | && INTVAL (operands[2]) == 255)) | |
0f40f9f7 | 6281 | return "dec{b}\t%h0"; |
e075ae69 | 6282 | abort(); |
886c62d1 | 6283 | |
e075ae69 | 6284 | default: |
0f40f9f7 | 6285 | return "add{b}\t{%2, %h0|%h0, %2}"; |
e075ae69 | 6286 | } |
0f40f9f7 | 6287 | } |
e075ae69 RH |
6288 | [(set (attr "type") |
6289 | (if_then_else (match_operand:QI 2 "incdec_operand" "") | |
6290 | (const_string "incdec") | |
6ef67412 JH |
6291 | (const_string "alu"))) |
6292 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
6293 | |
6294 | (define_insn "*addqi_ext_2" | |
d2836273 | 6295 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
6296 | (const_int 8) |
6297 | (const_int 8)) | |
6298 | (plus:SI | |
6299 | (zero_extract:SI | |
6300 | (match_operand 1 "ext_register_operand" "%0") | |
6301 | (const_int 8) | |
6302 | (const_int 8)) | |
6303 | (zero_extract:SI | |
d2836273 | 6304 | (match_operand 2 "ext_register_operand" "Q") |
e075ae69 RH |
6305 | (const_int 8) |
6306 | (const_int 8)))) | |
6307 | (clobber (reg:CC 17))] | |
6308 | "" | |
0f40f9f7 | 6309 | "add{b}\t{%h2, %h0|%h0, %h2}" |
6ef67412 JH |
6310 | [(set_attr "type" "alu") |
6311 | (set_attr "mode" "QI")]) | |
886c62d1 | 6312 | |
886c62d1 JVA |
6313 | ;; The patterns that match these are at the end of this file. |
6314 | ||
4fb21e90 JVA |
6315 | (define_expand "addxf3" |
6316 | [(set (match_operand:XF 0 "register_operand" "") | |
2ae0f82c SC |
6317 | (plus:XF (match_operand:XF 1 "register_operand" "") |
6318 | (match_operand:XF 2 "register_operand" "")))] | |
1b0c37d7 | 6319 | "!TARGET_64BIT && TARGET_80387" |
4fb21e90 JVA |
6320 | "") |
6321 | ||
2b589241 JH |
6322 | (define_expand "addtf3" |
6323 | [(set (match_operand:TF 0 "register_operand" "") | |
6324 | (plus:TF (match_operand:TF 1 "register_operand" "") | |
6325 | (match_operand:TF 2 "register_operand" "")))] | |
6326 | "TARGET_80387" | |
6327 | "") | |
6328 | ||
886c62d1 JVA |
6329 | (define_expand "adddf3" |
6330 | [(set (match_operand:DF 0 "register_operand" "") | |
06a964de | 6331 | (plus:DF (match_operand:DF 1 "register_operand" "") |
886c62d1 | 6332 | (match_operand:DF 2 "nonimmediate_operand" "")))] |
965f5423 | 6333 | "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" |
886c62d1 JVA |
6334 | "") |
6335 | ||
6336 | (define_expand "addsf3" | |
6337 | [(set (match_operand:SF 0 "register_operand" "") | |
06a964de | 6338 | (plus:SF (match_operand:SF 1 "register_operand" "") |
886c62d1 | 6339 | (match_operand:SF 2 "nonimmediate_operand" "")))] |
965f5423 | 6340 | "TARGET_80387 || TARGET_SSE_MATH" |
886c62d1 JVA |
6341 | "") |
6342 | \f | |
e075ae69 | 6343 | ;; Subtract instructions |
a269a03c | 6344 | |
e075ae69 | 6345 | ;; %%% splits for subsidi3 |
2ae0f82c | 6346 | |
9b70259d JH |
6347 | (define_expand "subdi3" |
6348 | [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
6349 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
6350 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
6351 | (clobber (reg:CC 17))])] | |
6352 | "" | |
6353 | "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;") | |
6354 | ||
6355 | (define_insn "*subdi3_1" | |
e075ae69 | 6356 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") |
4cbfbb1b | 6357 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") |
e075ae69 RH |
6358 | (match_operand:DI 2 "general_operand" "roiF,riF"))) |
6359 | (clobber (reg:CC 17))] | |
9b70259d | 6360 | "!TARGET_64BIT" |
e075ae69 | 6361 | "#") |
9c530261 | 6362 | |
e075ae69 RH |
6363 | (define_split |
6364 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
4cbfbb1b | 6365 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
e075ae69 RH |
6366 | (match_operand:DI 2 "general_operand" ""))) |
6367 | (clobber (reg:CC 17))] | |
1b0c37d7 | 6368 | "!TARGET_64BIT && reload_completed" |
9dcbdc7e | 6369 | [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2))) |
e075ae69 RH |
6370 | (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) |
6371 | (parallel [(set (match_dup 3) | |
6372 | (minus:SI (match_dup 4) | |
9dcbdc7e JH |
6373 | (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
6374 | (match_dup 5)))) | |
e075ae69 RH |
6375 | (clobber (reg:CC 17))])] |
6376 | "split_di (operands+0, 1, operands+0, operands+3); | |
6377 | split_di (operands+1, 1, operands+1, operands+4); | |
6378 | split_di (operands+2, 1, operands+2, operands+5);") | |
6379 | ||
9b70259d JH |
6380 | (define_insn "subdi3_carry_rex64" |
6381 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
6382 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
6383 | (plus:DI (ltu:DI (reg:CC 17) (const_int 0)) | |
6384 | (match_operand:DI 2 "x86_64_general_operand" "re,rm")))) | |
6385 | (clobber (reg:CC 17))] | |
1b0c37d7 | 6386 | "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" |
0f40f9f7 | 6387 | "sbb{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
6388 | [(set_attr "type" "alu") |
6389 | (set_attr "pent_pair" "pu") | |
6390 | (set_attr "ppro_uops" "few") | |
6391 | (set_attr "mode" "DI")]) | |
6392 | ||
6393 | (define_insn "*subdi_1_rex64" | |
6394 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
6395 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
6396 | (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) | |
6397 | (clobber (reg:CC 17))] | |
6398 | "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" | |
0f40f9f7 | 6399 | "sub{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
6400 | [(set_attr "type" "alu") |
6401 | (set_attr "mode" "DI")]) | |
6402 | ||
6403 | (define_insn "*subdi_2_rex64" | |
6404 | [(set (reg 17) | |
6405 | (compare | |
6406 | (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
6407 | (match_operand:DI 2 "x86_64_general_operand" "re,rm")) | |
6408 | (const_int 0))) | |
6409 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
6410 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6411 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
6412 | && ix86_binary_operator_ok (MINUS, DImode, operands)" | |
0f40f9f7 | 6413 | "sub{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
6414 | [(set_attr "type" "alu") |
6415 | (set_attr "mode" "DI")]) | |
6416 | ||
6417 | (define_insn "*subdi_3_rex63" | |
6418 | [(set (reg 17) | |
6419 | (compare (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
6420 | (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) | |
6421 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
6422 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6423 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode) | |
6424 | && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 6425 | "sub{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
6426 | [(set_attr "type" "alu") |
6427 | (set_attr "mode" "DI")]) | |
6428 | ||
6429 | ||
7e08e190 | 6430 | (define_insn "subsi3_carry" |
e075ae69 RH |
6431 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") |
6432 | (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
9dcbdc7e JH |
6433 | (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
6434 | (match_operand:SI 2 "general_operand" "ri,rm")))) | |
e075ae69 | 6435 | (clobber (reg:CC 17))] |
d525dfdf | 6436 | "ix86_binary_operator_ok (MINUS, SImode, operands)" |
0f40f9f7 | 6437 | "sbb{l}\t{%2, %0|%0, %2}" |
e075ae69 RH |
6438 | [(set_attr "type" "alu") |
6439 | (set_attr "pent_pair" "pu") | |
6ef67412 JH |
6440 | (set_attr "ppro_uops" "few") |
6441 | (set_attr "mode" "SI")]) | |
886c62d1 | 6442 | |
9b70259d JH |
6443 | (define_insn "subsi3_carry_zext" |
6444 | [(set (match_operand:DI 0 "register_operand" "=rm,r") | |
6445 | (zero_extend:DI | |
6446 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6447 | (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) | |
6448 | (match_operand:SI 2 "general_operand" "ri,rm"))))) | |
6449 | (clobber (reg:CC 17))] | |
6450 | "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 6451 | "sbb{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
6452 | [(set_attr "type" "alu") |
6453 | (set_attr "pent_pair" "pu") | |
6454 | (set_attr "ppro_uops" "few") | |
6455 | (set_attr "mode" "SI")]) | |
6456 | ||
2ae0f82c | 6457 | (define_expand "subsi3" |
e075ae69 RH |
6458 | [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") |
6459 | (minus:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
6460 | (match_operand:SI 2 "general_operand" ""))) | |
6461 | (clobber (reg:CC 17))])] | |
886c62d1 | 6462 | "" |
e075ae69 | 6463 | "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;") |
2ae0f82c | 6464 | |
e075ae69 | 6465 | (define_insn "*subsi_1" |
2ae0f82c SC |
6466 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") |
6467 | (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
e075ae69 RH |
6468 | (match_operand:SI 2 "general_operand" "ri,rm"))) |
6469 | (clobber (reg:CC 17))] | |
6470 | "ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 6471 | "sub{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
6472 | [(set_attr "type" "alu") |
6473 | (set_attr "mode" "SI")]) | |
e075ae69 | 6474 | |
9b70259d JH |
6475 | (define_insn "*subsi_1_zext" |
6476 | [(set (match_operand:DI 0 "register_operand" "=r") | |
6477 | (zero_extend:DI | |
6478 | (minus:SI (match_operand:SI 1 "register_operand" "0") | |
6479 | (match_operand:SI 2 "general_operand" "rim")))) | |
6480 | (clobber (reg:CC 17))] | |
6481 | "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 6482 | "sub{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
6483 | [(set_attr "type" "alu") |
6484 | (set_attr "mode" "SI")]) | |
6485 | ||
e075ae69 | 6486 | (define_insn "*subsi_2" |
16189740 RH |
6487 | [(set (reg 17) |
6488 | (compare | |
e075ae69 RH |
6489 | (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") |
6490 | (match_operand:SI 2 "general_operand" "ri,rm")) | |
6491 | (const_int 0))) | |
6492 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") | |
6493 | (minus:SI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 6494 | "ix86_match_ccmode (insn, CCGOCmode) |
d90ffc8d | 6495 | && ix86_binary_operator_ok (MINUS, SImode, operands)" |
0f40f9f7 | 6496 | "sub{l}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
6497 | [(set_attr "type" "alu") |
6498 | (set_attr "mode" "SI")]) | |
6499 | ||
9b70259d JH |
6500 | (define_insn "*subsi_2_zext" |
6501 | [(set (reg 17) | |
6502 | (compare | |
6503 | (minus:SI (match_operand:SI 1 "register_operand" "0") | |
6504 | (match_operand:SI 2 "general_operand" "rim")) | |
6505 | (const_int 0))) | |
6506 | (set (match_operand:DI 0 "register_operand" "=r") | |
6507 | (zero_extend:DI | |
6508 | (minus:SI (match_dup 1) | |
6509 | (match_dup 2))))] | |
6510 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
6511 | && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 6512 | "sub{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
6513 | [(set_attr "type" "alu") |
6514 | (set_attr "mode" "SI")]) | |
6515 | ||
d90ffc8d JH |
6516 | (define_insn "*subsi_3" |
6517 | [(set (reg 17) | |
6518 | (compare (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
6519 | (match_operand:SI 2 "general_operand" "ri,rm"))) | |
6520 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") | |
6521 | (minus:SI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
6522 | "ix86_match_ccmode (insn, CCmode) |
6523 | && ix86_binary_operator_ok (MINUS, SImode, operands)" | |
0f40f9f7 | 6524 | "sub{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
6525 | [(set_attr "type" "alu") |
6526 | (set_attr "mode" "SI")]) | |
886c62d1 | 6527 | |
9b70259d JH |
6528 | (define_insn "*subsi_3_zext" |
6529 | [(set (reg 17) | |
6530 | (compare (match_operand:SI 1 "nonimmediate_operand" "0") | |
6531 | (match_operand:SI 2 "general_operand" "rim"))) | |
6532 | (set (match_operand:DI 0 "register_operand" "=r") | |
6533 | (zero_extend:DI | |
6534 | (minus:SI (match_dup 1) | |
6535 | (match_dup 2))))] | |
8362f420 | 6536 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode) |
9b70259d | 6537 | && ix86_binary_operator_ok (MINUS, SImode, operands)" |
0f40f9f7 | 6538 | "sub{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
6539 | [(set_attr "type" "alu") |
6540 | (set_attr "mode" "DI")]) | |
6541 | ||
2ae0f82c | 6542 | (define_expand "subhi3" |
4cbfbb1b | 6543 | [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") |
e075ae69 RH |
6544 | (minus:HI (match_operand:HI 1 "nonimmediate_operand" "") |
6545 | (match_operand:HI 2 "general_operand" ""))) | |
6546 | (clobber (reg:CC 17))])] | |
d9f32422 | 6547 | "TARGET_HIMODE_MATH" |
e075ae69 | 6548 | "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;") |
2ae0f82c | 6549 | |
e075ae69 | 6550 | (define_insn "*subhi_1" |
2ae0f82c | 6551 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") |
87fd1847 | 6552 | (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") |
e075ae69 RH |
6553 | (match_operand:HI 2 "general_operand" "ri,rm"))) |
6554 | (clobber (reg:CC 17))] | |
2ae0f82c | 6555 | "ix86_binary_operator_ok (MINUS, HImode, operands)" |
0f40f9f7 | 6556 | "sub{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
6557 | [(set_attr "type" "alu") |
6558 | (set_attr "mode" "HI")]) | |
e075ae69 RH |
6559 | |
6560 | (define_insn "*subhi_2" | |
16189740 RH |
6561 | [(set (reg 17) |
6562 | (compare | |
e075ae69 RH |
6563 | (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") |
6564 | (match_operand:HI 2 "general_operand" "ri,rm")) | |
6565 | (const_int 0))) | |
6566 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") | |
6567 | (minus:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 6568 | "ix86_match_ccmode (insn, CCGOCmode) |
d90ffc8d | 6569 | && ix86_binary_operator_ok (MINUS, HImode, operands)" |
0f40f9f7 | 6570 | "sub{w}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
6571 | [(set_attr "type" "alu") |
6572 | (set_attr "mode" "HI")]) | |
6573 | ||
6574 | (define_insn "*subhi_3" | |
6575 | [(set (reg 17) | |
6576 | (compare (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
6577 | (match_operand:HI 2 "general_operand" "ri,rm"))) | |
6578 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") | |
6579 | (minus:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
6580 | "ix86_match_ccmode (insn, CCmode) |
6581 | && ix86_binary_operator_ok (MINUS, HImode, operands)" | |
0f40f9f7 | 6582 | "sub{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
6583 | [(set_attr "type" "alu") |
6584 | (set_attr "mode" "HI")]) | |
886c62d1 | 6585 | |
2ae0f82c | 6586 | (define_expand "subqi3" |
4cbfbb1b JH |
6587 | [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") |
6588 | (minus:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
e075ae69 RH |
6589 | (match_operand:QI 2 "general_operand" ""))) |
6590 | (clobber (reg:CC 17))])] | |
d9f32422 | 6591 | "TARGET_QIMODE_MATH" |
e075ae69 | 6592 | "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;") |
2ae0f82c | 6593 | |
e075ae69 | 6594 | (define_insn "*subqi_1" |
2ae0f82c SC |
6595 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") |
6596 | (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
e075ae69 RH |
6597 | (match_operand:QI 2 "general_operand" "qn,qmn"))) |
6598 | (clobber (reg:CC 17))] | |
6599 | "ix86_binary_operator_ok (MINUS, QImode, operands)" | |
0f40f9f7 | 6600 | "sub{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
6601 | [(set_attr "type" "alu") |
6602 | (set_attr "mode" "QI")]) | |
e075ae69 | 6603 | |
2f41793e JH |
6604 | (define_insn "*subqi_1_slp" |
6605 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) | |
6606 | (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
6607 | (match_operand:QI 2 "general_operand" "qn,qmn"))) | |
6608 | (clobber (reg:CC 17))] | |
6609 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
6610 | && ix86_binary_operator_ok (MINUS, QImode, operands)" | |
6611 | "sub{b}\t{%2, %0|%0, %2}" | |
6612 | [(set_attr "type" "alu") | |
6613 | (set_attr "mode" "QI")]) | |
6614 | ||
e075ae69 | 6615 | (define_insn "*subqi_2" |
16189740 RH |
6616 | [(set (reg 17) |
6617 | (compare | |
e075ae69 RH |
6618 | (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") |
6619 | (match_operand:QI 2 "general_operand" "qi,qm")) | |
6620 | (const_int 0))) | |
6621 | (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q") | |
6622 | (minus:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 6623 | "ix86_match_ccmode (insn, CCGOCmode) |
d90ffc8d | 6624 | && ix86_binary_operator_ok (MINUS, QImode, operands)" |
0f40f9f7 | 6625 | "sub{b}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
6626 | [(set_attr "type" "alu") |
6627 | (set_attr "mode" "QI")]) | |
6628 | ||
6629 | (define_insn "*subqi_3" | |
6630 | [(set (reg 17) | |
6631 | (compare (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
6632 | (match_operand:QI 2 "general_operand" "qi,qm"))) | |
6633 | (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q") | |
6634 | (minus:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
6635 | "ix86_match_ccmode (insn, CCmode) |
6636 | && ix86_binary_operator_ok (MINUS, QImode, operands)" | |
0f40f9f7 | 6637 | "sub{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
6638 | [(set_attr "type" "alu") |
6639 | (set_attr "mode" "QI")]) | |
2ae0f82c | 6640 | |
886c62d1 JVA |
6641 | ;; The patterns that match these are at the end of this file. |
6642 | ||
4fb21e90 JVA |
6643 | (define_expand "subxf3" |
6644 | [(set (match_operand:XF 0 "register_operand" "") | |
2ae0f82c SC |
6645 | (minus:XF (match_operand:XF 1 "register_operand" "") |
6646 | (match_operand:XF 2 "register_operand" "")))] | |
1b0c37d7 | 6647 | "!TARGET_64BIT && TARGET_80387" |
4fb21e90 JVA |
6648 | "") |
6649 | ||
2b589241 JH |
6650 | (define_expand "subtf3" |
6651 | [(set (match_operand:TF 0 "register_operand" "") | |
6652 | (minus:TF (match_operand:TF 1 "register_operand" "") | |
6653 | (match_operand:TF 2 "register_operand" "")))] | |
6654 | "TARGET_80387" | |
6655 | "") | |
6656 | ||
886c62d1 JVA |
6657 | (define_expand "subdf3" |
6658 | [(set (match_operand:DF 0 "register_operand" "") | |
06a964de | 6659 | (minus:DF (match_operand:DF 1 "register_operand" "") |
886c62d1 | 6660 | (match_operand:DF 2 "nonimmediate_operand" "")))] |
965f5423 | 6661 | "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" |
886c62d1 JVA |
6662 | "") |
6663 | ||
6664 | (define_expand "subsf3" | |
6665 | [(set (match_operand:SF 0 "register_operand" "") | |
06a964de | 6666 | (minus:SF (match_operand:SF 1 "register_operand" "") |
886c62d1 | 6667 | (match_operand:SF 2 "nonimmediate_operand" "")))] |
965f5423 | 6668 | "TARGET_80387 || TARGET_SSE_MATH" |
886c62d1 JVA |
6669 | "") |
6670 | \f | |
e075ae69 | 6671 | ;; Multiply instructions |
886c62d1 | 6672 | |
9b70259d JH |
6673 | (define_expand "muldi3" |
6674 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
6675 | (mult:DI (match_operand:DI 1 "register_operand" "") | |
6676 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
6677 | (clobber (reg:CC 17))])] | |
6678 | "TARGET_64BIT" | |
6679 | "") | |
6680 | ||
6681 | (define_insn "*muldi3_1_rex64" | |
6682 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
6683 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0") | |
6684 | (match_operand:DI 2 "x86_64_general_operand" "K,e,mr"))) | |
6685 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
6686 | "TARGET_64BIT |
6687 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
9b70259d | 6688 | "@ |
0f40f9f7 ZW |
6689 | imul{q}\t{%2, %1, %0|%0, %1, %2} |
6690 | imul{q}\t{%2, %1, %0|%0, %1, %2} | |
6691 | imul{q}\t{%2, %0|%0, %2}" | |
9b70259d JH |
6692 | [(set_attr "type" "imul") |
6693 | (set_attr "prefix_0f" "0,0,1") | |
6694 | (set_attr "mode" "DI")]) | |
6695 | ||
d525dfdf JH |
6696 | (define_expand "mulsi3" |
6697 | [(parallel [(set (match_operand:SI 0 "register_operand" "") | |
6698 | (mult:SI (match_operand:SI 1 "register_operand" "") | |
6699 | (match_operand:SI 2 "general_operand" ""))) | |
6700 | (clobber (reg:CC 17))])] | |
6701 | "" | |
6702 | "") | |
6703 | ||
6704 | (define_insn "*mulsi3_1" | |
e075ae69 RH |
6705 | [(set (match_operand:SI 0 "register_operand" "=r,r,r") |
6706 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0") | |
6707 | (match_operand:SI 2 "general_operand" "K,i,mr"))) | |
6708 | (clobber (reg:CC 17))] | |
d525dfdf | 6709 | "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" |
20819a09 MM |
6710 | ; For the {r,0,i} alternative (i.e., register <- register * immediate), |
6711 | ; there are two ways of writing the exact same machine instruction | |
6712 | ; in assembly language. One, for example, is: | |
6713 | ; | |
6714 | ; imul $12, %eax | |
6715 | ; | |
6716 | ; while the other is: | |
6717 | ; | |
6718 | ; imul $12, %eax, %eax | |
6719 | ; | |
6720 | ; The first is simply short-hand for the latter. But, some assemblers, | |
6721 | ; like the SCO OSR5 COFF assembler, don't handle the first form. | |
e075ae69 | 6722 | "@ |
0f40f9f7 ZW |
6723 | imul{l}\t{%2, %1, %0|%0, %1, %2} |
6724 | imul{l}\t{%2, %1, %0|%0, %1, %2} | |
6725 | imul{l}\t{%2, %0|%0, %2}" | |
e075ae69 | 6726 | [(set_attr "type" "imul") |
6ef67412 JH |
6727 | (set_attr "prefix_0f" "0,0,1") |
6728 | (set_attr "mode" "SI")]) | |
886c62d1 | 6729 | |
9b70259d JH |
6730 | (define_insn "*mulsi3_1_zext" |
6731 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
6732 | (zero_extend:DI | |
6733 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0") | |
6734 | (match_operand:SI 2 "general_operand" "K,i,mr")))) | |
6735 | (clobber (reg:CC 17))] | |
6736 | "TARGET_64BIT | |
6737 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
6738 | ; For the {r,0,i} alternative (i.e., register <- register * immediate), | |
6739 | ; there are two ways of writing the exact same machine instruction | |
6740 | ; in assembly language. One, for example, is: | |
6741 | ; | |
6742 | ; imul $12, %eax | |
6743 | ; | |
6744 | ; while the other is: | |
6745 | ; | |
6746 | ; imul $12, %eax, %eax | |
6747 | ; | |
6748 | ; The first is simply short-hand for the latter. But, some assemblers, | |
6749 | ; like the SCO OSR5 COFF assembler, don't handle the first form. | |
6750 | "@ | |
0f40f9f7 ZW |
6751 | imul{l}\t{%2, %1, %k0|%k0, %1, %2} |
6752 | imul{l}\t{%2, %1, %k0|%k0, %1, %2} | |
6753 | imul{l}\t{%2, %k0|%k0, %2}" | |
9b70259d JH |
6754 | [(set_attr "type" "imul") |
6755 | (set_attr "prefix_0f" "0,0,1") | |
6756 | (set_attr "mode" "SI")]) | |
6757 | ||
d525dfdf JH |
6758 | (define_expand "mulhi3" |
6759 | [(parallel [(set (match_operand:HI 0 "register_operand" "") | |
6760 | (mult:HI (match_operand:HI 1 "register_operand" "") | |
6761 | (match_operand:HI 2 "general_operand" ""))) | |
6762 | (clobber (reg:CC 17))])] | |
d9f32422 | 6763 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
6764 | "") |
6765 | ||
6766 | (define_insn "*mulhi3_1" | |
6ef67412 JH |
6767 | [(set (match_operand:HI 0 "register_operand" "=r,r,r") |
6768 | (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0") | |
6769 | (match_operand:HI 2 "general_operand" "K,i,mr"))) | |
e075ae69 | 6770 | (clobber (reg:CC 17))] |
d525dfdf | 6771 | "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" |
e075ae69 RH |
6772 | ; %%% There was a note about "Assembler has weird restrictions", |
6773 | ; concerning alternative 1 when op1 == op0. True? | |
6774 | "@ | |
0f40f9f7 ZW |
6775 | imul{w}\t{%2, %1, %0|%0, %1, %2} |
6776 | imul{w}\t{%2, %1, %0|%0, %1, %2} | |
6777 | imul{w}\t{%2, %0|%0, %2}" | |
6ef67412 JH |
6778 | [(set_attr "type" "imul") |
6779 | (set_attr "prefix_0f" "0,0,1") | |
6780 | (set_attr "mode" "HI")]) | |
886c62d1 | 6781 | |
558740bf JH |
6782 | (define_expand "mulqi3" |
6783 | [(parallel [(set (match_operand:QI 0 "register_operand" "") | |
6784 | (mult:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
6785 | (match_operand:QI 2 "register_operand" ""))) | |
6786 | (clobber (reg:CC 17))])] | |
6787 | "TARGET_QIMODE_MATH" | |
6788 | "") | |
6789 | ||
6790 | (define_insn "*mulqi3_1" | |
765a46f9 | 6791 | [(set (match_operand:QI 0 "register_operand" "=a") |
558740bf | 6792 | (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0") |
765a46f9 JH |
6793 | (match_operand:QI 2 "nonimmediate_operand" "qm"))) |
6794 | (clobber (reg:CC 17))] | |
558740bf JH |
6795 | "TARGET_QIMODE_MATH |
6796 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 6797 | "mul{b}\t%2" |
6ef67412 JH |
6798 | [(set_attr "type" "imul") |
6799 | (set_attr "length_immediate" "0") | |
6800 | (set_attr "mode" "QI")]) | |
765a46f9 | 6801 | |
558740bf JH |
6802 | (define_expand "umulqihi3" |
6803 | [(parallel [(set (match_operand:HI 0 "register_operand" "") | |
6804 | (mult:HI (zero_extend:HI | |
6805 | (match_operand:QI 1 "nonimmediate_operand" "")) | |
6806 | (zero_extend:HI | |
6807 | (match_operand:QI 2 "register_operand" "")))) | |
6808 | (clobber (reg:CC 17))])] | |
6809 | "TARGET_QIMODE_MATH" | |
6810 | "") | |
6811 | ||
6812 | (define_insn "*umulqihi3_1" | |
2ae0f82c | 6813 | [(set (match_operand:HI 0 "register_operand" "=a") |
558740bf | 6814 | (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) |
e075ae69 RH |
6815 | (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) |
6816 | (clobber (reg:CC 17))] | |
558740bf JH |
6817 | "TARGET_QIMODE_MATH |
6818 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 6819 | "mul{b}\t%2" |
6ef67412 JH |
6820 | [(set_attr "type" "imul") |
6821 | (set_attr "length_immediate" "0") | |
6822 | (set_attr "mode" "QI")]) | |
886c62d1 | 6823 | |
558740bf JH |
6824 | (define_expand "mulqihi3" |
6825 | [(parallel [(set (match_operand:HI 0 "register_operand" "") | |
6826 | (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")) | |
6827 | (sign_extend:HI (match_operand:QI 2 "register_operand" "")))) | |
6828 | (clobber (reg:CC 17))])] | |
6829 | "TARGET_QIMODE_MATH" | |
6830 | "") | |
6831 | ||
6832 | (define_insn "*mulqihi3_insn" | |
2ae0f82c | 6833 | [(set (match_operand:HI 0 "register_operand" "=a") |
558740bf | 6834 | (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) |
e075ae69 RH |
6835 | (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) |
6836 | (clobber (reg:CC 17))] | |
558740bf JH |
6837 | "TARGET_QIMODE_MATH |
6838 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 6839 | "imul{b}\t%2" |
6ef67412 JH |
6840 | [(set_attr "type" "imul") |
6841 | (set_attr "length_immediate" "0") | |
6842 | (set_attr "mode" "QI")]) | |
4b71cd6e | 6843 | |
558740bf JH |
6844 | (define_expand "umulditi3" |
6845 | [(parallel [(set (match_operand:TI 0 "register_operand" "") | |
6846 | (mult:TI (zero_extend:TI | |
6847 | (match_operand:DI 1 "nonimmediate_operand" "")) | |
6848 | (zero_extend:TI | |
6849 | (match_operand:DI 2 "register_operand" "")))) | |
6850 | (clobber (reg:CC 17))])] | |
6851 | "TARGET_64BIT" | |
6852 | "") | |
6853 | ||
6854 | (define_insn "*umulditi3_insn" | |
9b70259d | 6855 | [(set (match_operand:TI 0 "register_operand" "=A") |
558740bf | 6856 | (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) |
9b70259d | 6857 | (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) |
1e07edd3 | 6858 | (clobber (reg:CC 17))] |
558740bf JH |
6859 | "TARGET_64BIT |
6860 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 6861 | "mul{q}\t%2" |
1e07edd3 JH |
6862 | [(set_attr "type" "imul") |
6863 | (set_attr "ppro_uops" "few") | |
6864 | (set_attr "length_immediate" "0") | |
9b70259d | 6865 | (set_attr "mode" "DI")]) |
1e07edd3 JH |
6866 | |
6867 | ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers | |
558740bf JH |
6868 | (define_expand "umulsidi3" |
6869 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
6870 | (mult:DI (zero_extend:DI | |
6871 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
6872 | (zero_extend:DI | |
6873 | (match_operand:SI 2 "register_operand" "")))) | |
6874 | (clobber (reg:CC 17))])] | |
6875 | "!TARGET_64BIT" | |
6876 | "") | |
6877 | ||
6878 | (define_insn "*umulsidi3_insn" | |
4b71cd6e | 6879 | [(set (match_operand:DI 0 "register_operand" "=A") |
558740bf | 6880 | (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) |
e075ae69 RH |
6881 | (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) |
6882 | (clobber (reg:CC 17))] | |
558740bf JH |
6883 | "!TARGET_64BIT |
6884 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 6885 | "mul{l}\t%2" |
e075ae69 | 6886 | [(set_attr "type" "imul") |
6ef67412 JH |
6887 | (set_attr "ppro_uops" "few") |
6888 | (set_attr "length_immediate" "0") | |
6889 | (set_attr "mode" "SI")]) | |
4b71cd6e | 6890 | |
558740bf JH |
6891 | (define_expand "mulditi3" |
6892 | [(parallel [(set (match_operand:TI 0 "register_operand" "") | |
6893 | (mult:TI (sign_extend:TI | |
6894 | (match_operand:DI 1 "nonimmediate_operand" "")) | |
6895 | (sign_extend:TI | |
6896 | (match_operand:DI 2 "register_operand" "")))) | |
6897 | (clobber (reg:CC 17))])] | |
6898 | "TARGET_64BIT" | |
6899 | "") | |
6900 | ||
6901 | (define_insn "*mulditi3_insn" | |
9b70259d | 6902 | [(set (match_operand:TI 0 "register_operand" "=A") |
558740bf | 6903 | (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) |
9b70259d JH |
6904 | (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) |
6905 | (clobber (reg:CC 17))] | |
558740bf JH |
6906 | "TARGET_64BIT |
6907 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 6908 | "imul{q}\t%2" |
9b70259d JH |
6909 | [(set_attr "type" "imul") |
6910 | (set_attr "length_immediate" "0") | |
6911 | (set_attr "mode" "DI")]) | |
6912 | ||
558740bf JH |
6913 | (define_expand "mulsidi3" |
6914 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
6915 | (mult:DI (sign_extend:DI | |
6916 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
6917 | (sign_extend:DI | |
6918 | (match_operand:SI 2 "register_operand" "")))) | |
6919 | (clobber (reg:CC 17))])] | |
6920 | "!TARGET_64BIT" | |
6921 | "") | |
6922 | ||
6923 | (define_insn "*mulsidi3_insn" | |
4b71cd6e | 6924 | [(set (match_operand:DI 0 "register_operand" "=A") |
558740bf | 6925 | (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) |
e075ae69 RH |
6926 | (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) |
6927 | (clobber (reg:CC 17))] | |
558740bf JH |
6928 | "!TARGET_64BIT |
6929 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 6930 | "imul{l}\t%2" |
6ef67412 JH |
6931 | [(set_attr "type" "imul") |
6932 | (set_attr "length_immediate" "0") | |
6933 | (set_attr "mode" "SI")]) | |
2f2a49e8 | 6934 | |
558740bf JH |
6935 | (define_expand "umuldi3_highpart" |
6936 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
6937 | (truncate:DI | |
6938 | (lshiftrt:TI | |
6939 | (mult:TI (zero_extend:TI | |
6940 | (match_operand:DI 1 "nonimmediate_operand" "")) | |
6941 | (zero_extend:TI | |
6942 | (match_operand:DI 2 "register_operand" ""))) | |
6943 | (const_int 64)))) | |
6944 | (clobber (match_scratch:DI 3 "")) | |
6945 | (clobber (reg:CC 17))])] | |
6946 | "TARGET_64BIT" | |
6947 | "") | |
6948 | ||
9b70259d JH |
6949 | (define_insn "*umuldi3_highpart_rex64" |
6950 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6951 | (truncate:DI | |
6952 | (lshiftrt:TI | |
6953 | (mult:TI (zero_extend:TI | |
558740bf | 6954 | (match_operand:DI 1 "nonimmediate_operand" "%a")) |
9b70259d JH |
6955 | (zero_extend:TI |
6956 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
6957 | (const_int 64)))) | |
558740bf | 6958 | (clobber (match_scratch:DI 3 "=1")) |
9b70259d | 6959 | (clobber (reg:CC 17))] |
558740bf JH |
6960 | "TARGET_64BIT |
6961 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 6962 | "mul{q}\t%2" |
9b70259d JH |
6963 | [(set_attr "type" "imul") |
6964 | (set_attr "ppro_uops" "few") | |
6965 | (set_attr "length_immediate" "0") | |
6966 | (set_attr "mode" "DI")]) | |
6967 | ||
558740bf JH |
6968 | (define_expand "umulsi3_highpart" |
6969 | [(parallel [(set (match_operand:SI 0 "register_operand" "") | |
6970 | (truncate:SI | |
6971 | (lshiftrt:DI | |
6972 | (mult:DI (zero_extend:DI | |
6973 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
6974 | (zero_extend:DI | |
6975 | (match_operand:SI 2 "register_operand" ""))) | |
6976 | (const_int 32)))) | |
6977 | (clobber (match_scratch:SI 3 "")) | |
6978 | (clobber (reg:CC 17))])] | |
6979 | "" | |
6980 | "") | |
6981 | ||
6982 | (define_insn "*umulsi3_highpart_insn" | |
2f2a49e8 | 6983 | [(set (match_operand:SI 0 "register_operand" "=d") |
e075ae69 RH |
6984 | (truncate:SI |
6985 | (lshiftrt:DI | |
6986 | (mult:DI (zero_extend:DI | |
558740bf | 6987 | (match_operand:SI 1 "nonimmediate_operand" "%a")) |
e075ae69 RH |
6988 | (zero_extend:DI |
6989 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
6990 | (const_int 32)))) | |
558740bf | 6991 | (clobber (match_scratch:SI 3 "=1")) |
e075ae69 | 6992 | (clobber (reg:CC 17))] |
558740bf | 6993 | "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" |
0f40f9f7 | 6994 | "mul{l}\t%2" |
32ee7d1d JH |
6995 | [(set_attr "type" "imul") |
6996 | (set_attr "ppro_uops" "few") | |
6997 | (set_attr "length_immediate" "0") | |
6998 | (set_attr "mode" "SI")]) | |
6999 | ||
7000 | (define_insn "*umulsi3_highpart_zext" | |
7001 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7002 | (zero_extend:DI (truncate:SI | |
7003 | (lshiftrt:DI | |
7004 | (mult:DI (zero_extend:DI | |
558740bf | 7005 | (match_operand:SI 1 "nonimmediate_operand" "%a")) |
32ee7d1d JH |
7006 | (zero_extend:DI |
7007 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
7008 | (const_int 32))))) | |
558740bf | 7009 | (clobber (match_scratch:SI 3 "=1")) |
32ee7d1d | 7010 | (clobber (reg:CC 17))] |
558740bf JH |
7011 | "TARGET_64BIT |
7012 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 7013 | "mul{l}\t%2" |
e075ae69 | 7014 | [(set_attr "type" "imul") |
6ef67412 JH |
7015 | (set_attr "ppro_uops" "few") |
7016 | (set_attr "length_immediate" "0") | |
7017 | (set_attr "mode" "SI")]) | |
2f2a49e8 | 7018 | |
558740bf JH |
7019 | (define_expand "smuldi3_highpart" |
7020 | [(parallel [(set (match_operand:DI 0 "register_operand" "=d") | |
7021 | (truncate:DI | |
7022 | (lshiftrt:TI | |
7023 | (mult:TI (sign_extend:TI | |
7024 | (match_operand:DI 1 "nonimmediate_operand" "")) | |
7025 | (sign_extend:TI | |
7026 | (match_operand:DI 2 "register_operand" ""))) | |
7027 | (const_int 64)))) | |
7028 | (clobber (match_scratch:DI 3 "")) | |
7029 | (clobber (reg:CC 17))])] | |
7030 | "TARGET_64BIT" | |
7031 | "") | |
7032 | ||
9b70259d JH |
7033 | (define_insn "*smuldi3_highpart_rex64" |
7034 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7035 | (truncate:DI | |
7036 | (lshiftrt:TI | |
7037 | (mult:TI (sign_extend:TI | |
558740bf | 7038 | (match_operand:DI 1 "nonimmediate_operand" "%a")) |
9b70259d JH |
7039 | (sign_extend:TI |
7040 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
7041 | (const_int 64)))) | |
558740bf | 7042 | (clobber (match_scratch:DI 3 "=1")) |
9b70259d | 7043 | (clobber (reg:CC 17))] |
558740bf JH |
7044 | "TARGET_64BIT |
7045 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 7046 | "imul{q}\t%2" |
9b70259d JH |
7047 | [(set_attr "type" "imul") |
7048 | (set_attr "ppro_uops" "few") | |
7049 | (set_attr "mode" "DI")]) | |
7050 | ||
558740bf JH |
7051 | (define_expand "smulsi3_highpart" |
7052 | [(parallel [(set (match_operand:SI 0 "register_operand" "") | |
7053 | (truncate:SI | |
7054 | (lshiftrt:DI | |
7055 | (mult:DI (sign_extend:DI | |
7056 | (match_operand:SI 1 "nonimmediate_operand" "")) | |
7057 | (sign_extend:DI | |
7058 | (match_operand:SI 2 "register_operand" ""))) | |
7059 | (const_int 32)))) | |
7060 | (clobber (match_scratch:SI 3 "")) | |
7061 | (clobber (reg:CC 17))])] | |
7062 | "" | |
7063 | "") | |
7064 | ||
7065 | (define_insn "*smulsi3_highpart_insn" | |
2f2a49e8 | 7066 | [(set (match_operand:SI 0 "register_operand" "=d") |
e075ae69 RH |
7067 | (truncate:SI |
7068 | (lshiftrt:DI | |
7069 | (mult:DI (sign_extend:DI | |
558740bf | 7070 | (match_operand:SI 1 "nonimmediate_operand" "%a")) |
e075ae69 RH |
7071 | (sign_extend:DI |
7072 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
7073 | (const_int 32)))) | |
558740bf | 7074 | (clobber (match_scratch:SI 3 "=1")) |
e075ae69 | 7075 | (clobber (reg:CC 17))] |
558740bf | 7076 | "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" |
0f40f9f7 | 7077 | "imul{l}\t%2" |
e075ae69 | 7078 | [(set_attr "type" "imul") |
6ef67412 JH |
7079 | (set_attr "ppro_uops" "few") |
7080 | (set_attr "mode" "SI")]) | |
4b71cd6e | 7081 | |
9b70259d JH |
7082 | (define_insn "*smulsi3_highpart_zext" |
7083 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7084 | (zero_extend:DI (truncate:SI | |
7085 | (lshiftrt:DI | |
7086 | (mult:DI (sign_extend:DI | |
558740bf | 7087 | (match_operand:SI 1 "nonimmediate_operand" "%a")) |
9b70259d JH |
7088 | (sign_extend:DI |
7089 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
7090 | (const_int 32))))) | |
558740bf | 7091 | (clobber (match_scratch:SI 3 "=1")) |
9b70259d | 7092 | (clobber (reg:CC 17))] |
558740bf JH |
7093 | "TARGET_64BIT |
7094 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 7095 | "imul{l}\t%2" |
9b70259d JH |
7096 | [(set_attr "type" "imul") |
7097 | (set_attr "ppro_uops" "few") | |
7098 | (set_attr "mode" "SI")]) | |
7099 | ||
886c62d1 JVA |
7100 | ;; The patterns that match these are at the end of this file. |
7101 | ||
4fb21e90 JVA |
7102 | (define_expand "mulxf3" |
7103 | [(set (match_operand:XF 0 "register_operand" "") | |
2ae0f82c SC |
7104 | (mult:XF (match_operand:XF 1 "register_operand" "") |
7105 | (match_operand:XF 2 "register_operand" "")))] | |
1b0c37d7 | 7106 | "!TARGET_64BIT && TARGET_80387" |
4fb21e90 JVA |
7107 | "") |
7108 | ||
2b589241 JH |
7109 | (define_expand "multf3" |
7110 | [(set (match_operand:TF 0 "register_operand" "") | |
7111 | (mult:TF (match_operand:TF 1 "register_operand" "") | |
7112 | (match_operand:TF 2 "register_operand" "")))] | |
7113 | "TARGET_80387" | |
7114 | "") | |
7115 | ||
886c62d1 JVA |
7116 | (define_expand "muldf3" |
7117 | [(set (match_operand:DF 0 "register_operand" "") | |
2ae0f82c | 7118 | (mult:DF (match_operand:DF 1 "register_operand" "") |
886c62d1 | 7119 | (match_operand:DF 2 "nonimmediate_operand" "")))] |
965f5423 | 7120 | "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" |
886c62d1 JVA |
7121 | "") |
7122 | ||
7123 | (define_expand "mulsf3" | |
7124 | [(set (match_operand:SF 0 "register_operand" "") | |
2ae0f82c | 7125 | (mult:SF (match_operand:SF 1 "register_operand" "") |
886c62d1 | 7126 | (match_operand:SF 2 "nonimmediate_operand" "")))] |
965f5423 | 7127 | "TARGET_80387 || TARGET_SSE_MATH" |
886c62d1 JVA |
7128 | "") |
7129 | \f | |
e075ae69 | 7130 | ;; Divide instructions |
886c62d1 JVA |
7131 | |
7132 | (define_insn "divqi3" | |
2ae0f82c SC |
7133 | [(set (match_operand:QI 0 "register_operand" "=a") |
7134 | (div:QI (match_operand:HI 1 "register_operand" "0") | |
e075ae69 RH |
7135 | (match_operand:QI 2 "nonimmediate_operand" "qm"))) |
7136 | (clobber (reg:CC 17))] | |
d9f32422 | 7137 | "TARGET_QIMODE_MATH" |
0f40f9f7 | 7138 | "idiv{b}\t%2" |
e075ae69 | 7139 | [(set_attr "type" "idiv") |
6ef67412 | 7140 | (set_attr "mode" "QI") |
e075ae69 | 7141 | (set_attr "ppro_uops" "few")]) |
886c62d1 JVA |
7142 | |
7143 | (define_insn "udivqi3" | |
2ae0f82c SC |
7144 | [(set (match_operand:QI 0 "register_operand" "=a") |
7145 | (udiv:QI (match_operand:HI 1 "register_operand" "0") | |
e075ae69 RH |
7146 | (match_operand:QI 2 "nonimmediate_operand" "qm"))) |
7147 | (clobber (reg:CC 17))] | |
d9f32422 | 7148 | "TARGET_QIMODE_MATH" |
0f40f9f7 | 7149 | "div{b}\t%2" |
e075ae69 | 7150 | [(set_attr "type" "idiv") |
6ef67412 | 7151 | (set_attr "mode" "QI") |
e075ae69 | 7152 | (set_attr "ppro_uops" "few")]) |
886c62d1 JVA |
7153 | |
7154 | ;; The patterns that match these are at the end of this file. | |
7155 | ||
4fb21e90 JVA |
7156 | (define_expand "divxf3" |
7157 | [(set (match_operand:XF 0 "register_operand" "") | |
2ae0f82c SC |
7158 | (div:XF (match_operand:XF 1 "register_operand" "") |
7159 | (match_operand:XF 2 "register_operand" "")))] | |
1b0c37d7 | 7160 | "!TARGET_64BIT && TARGET_80387" |
886c62d1 JVA |
7161 | "") |
7162 | ||
2b589241 JH |
7163 | (define_expand "divtf3" |
7164 | [(set (match_operand:TF 0 "register_operand" "") | |
7165 | (div:TF (match_operand:TF 1 "register_operand" "") | |
7166 | (match_operand:TF 2 "register_operand" "")))] | |
7167 | "TARGET_80387" | |
7168 | "") | |
7169 | ||
a78cb986 SC |
7170 | (define_expand "divdf3" |
7171 | [(set (match_operand:DF 0 "register_operand" "") | |
7172 | (div:DF (match_operand:DF 1 "register_operand" "") | |
7173 | (match_operand:DF 2 "nonimmediate_operand" "")))] | |
965f5423 | 7174 | "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" |
a78cb986 SC |
7175 | "") |
7176 | ||
886c62d1 JVA |
7177 | (define_expand "divsf3" |
7178 | [(set (match_operand:SF 0 "register_operand" "") | |
2ae0f82c | 7179 | (div:SF (match_operand:SF 1 "register_operand" "") |
886c62d1 | 7180 | (match_operand:SF 2 "nonimmediate_operand" "")))] |
965f5423 | 7181 | "TARGET_80387 || TARGET_SSE_MATH" |
886c62d1 JVA |
7182 | "") |
7183 | \f | |
7184 | ;; Remainder instructions. | |
9b70259d JH |
7185 | |
7186 | (define_expand "divmoddi4" | |
7187 | [(parallel [(set (match_operand:DI 0 "register_operand" "") | |
7188 | (div:DI (match_operand:DI 1 "register_operand" "") | |
7189 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7190 | (set (match_operand:DI 3 "register_operand" "") | |
7191 | (mod:DI (match_dup 1) (match_dup 2))) | |
7192 | (clobber (reg:CC 17))])] | |
7193 | "TARGET_64BIT" | |
7194 | "") | |
7195 | ||
7196 | ;; Allow to come the parameter in eax or edx to avoid extra moves. | |
7197 | ;; Penalize eax case sligthly because it results in worse scheduling | |
7198 | ;; of code. | |
7199 | (define_insn "*divmoddi4_nocltd_rex64" | |
7200 | [(set (match_operand:DI 0 "register_operand" "=&a,?a") | |
7201 | (div:DI (match_operand:DI 2 "register_operand" "1,0") | |
7202 | (match_operand:DI 3 "nonimmediate_operand" "rm,rm"))) | |
7203 | (set (match_operand:DI 1 "register_operand" "=&d,&d") | |
7204 | (mod:DI (match_dup 2) (match_dup 3))) | |
7205 | (clobber (reg:CC 17))] | |
7206 | "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD" | |
7207 | "#" | |
7208 | [(set_attr "type" "multi")]) | |
7209 | ||
7210 | (define_insn "*divmoddi4_cltd_rex64" | |
7211 | [(set (match_operand:DI 0 "register_operand" "=a") | |
7212 | (div:DI (match_operand:DI 2 "register_operand" "a") | |
7213 | (match_operand:DI 3 "nonimmediate_operand" "rm"))) | |
7214 | (set (match_operand:DI 1 "register_operand" "=&d") | |
7215 | (mod:DI (match_dup 2) (match_dup 3))) | |
7216 | (clobber (reg:CC 17))] | |
7217 | "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)" | |
7218 | "#" | |
7219 | [(set_attr "type" "multi")]) | |
7220 | ||
7221 | (define_insn "*divmoddi_noext_rex64" | |
7222 | [(set (match_operand:DI 0 "register_operand" "=a") | |
7223 | (div:DI (match_operand:DI 1 "register_operand" "0") | |
7224 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
7225 | (set (match_operand:DI 3 "register_operand" "=d") | |
7226 | (mod:DI (match_dup 1) (match_dup 2))) | |
7227 | (use (match_operand:DI 4 "register_operand" "3")) | |
7228 | (clobber (reg:CC 17))] | |
7229 | "TARGET_64BIT" | |
0f40f9f7 | 7230 | "idiv{q}\t%2" |
9b70259d JH |
7231 | [(set_attr "type" "idiv") |
7232 | (set_attr "mode" "DI") | |
7233 | (set_attr "ppro_uops" "few")]) | |
7234 | ||
7235 | (define_split | |
7236 | [(set (match_operand:DI 0 "register_operand" "") | |
7237 | (div:DI (match_operand:DI 1 "register_operand" "") | |
7238 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7239 | (set (match_operand:DI 3 "register_operand" "") | |
7240 | (mod:DI (match_dup 1) (match_dup 2))) | |
7241 | (clobber (reg:CC 17))] | |
7242 | "TARGET_64BIT && reload_completed" | |
7243 | [(parallel [(set (match_dup 3) | |
7244 | (ashiftrt:DI (match_dup 4) (const_int 63))) | |
7245 | (clobber (reg:CC 17))]) | |
7246 | (parallel [(set (match_dup 0) | |
7247 | (div:DI (reg:DI 0) (match_dup 2))) | |
7248 | (set (match_dup 3) | |
7249 | (mod:DI (reg:DI 0) (match_dup 2))) | |
7250 | (use (match_dup 3)) | |
7251 | (clobber (reg:CC 17))])] | |
9b70259d | 7252 | { |
9cd10576 | 7253 | /* Avoid use of cltd in favor of a mov+shift. */ |
9b70259d JH |
7254 | if (!TARGET_USE_CLTD && !optimize_size) |
7255 | { | |
7256 | if (true_regnum (operands[1])) | |
7257 | emit_move_insn (operands[0], operands[1]); | |
7258 | else | |
7259 | emit_move_insn (operands[3], operands[1]); | |
7260 | operands[4] = operands[3]; | |
7261 | } | |
7262 | else | |
7263 | { | |
7264 | if (true_regnum (operands[1])) | |
7265 | abort(); | |
7266 | operands[4] = operands[1]; | |
7267 | } | |
0f40f9f7 | 7268 | }) |
9b70259d JH |
7269 | |
7270 | ||
40745eec JH |
7271 | (define_expand "divmodsi4" |
7272 | [(parallel [(set (match_operand:SI 0 "register_operand" "") | |
7273 | (div:SI (match_operand:SI 1 "register_operand" "") | |
7274 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7275 | (set (match_operand:SI 3 "register_operand" "") | |
7276 | (mod:SI (match_dup 1) (match_dup 2))) | |
7277 | (clobber (reg:CC 17))])] | |
7278 | "" | |
7279 | "") | |
7280 | ||
7281 | ;; Allow to come the parameter in eax or edx to avoid extra moves. | |
7282 | ;; Penalize eax case sligthly because it results in worse scheduling | |
7283 | ;; of code. | |
7284 | (define_insn "*divmodsi4_nocltd" | |
7285 | [(set (match_operand:SI 0 "register_operand" "=&a,?a") | |
7286 | (div:SI (match_operand:SI 2 "register_operand" "1,0") | |
7287 | (match_operand:SI 3 "nonimmediate_operand" "rm,rm"))) | |
7288 | (set (match_operand:SI 1 "register_operand" "=&d,&d") | |
7289 | (mod:SI (match_dup 2) (match_dup 3))) | |
7290 | (clobber (reg:CC 17))] | |
7291 | "!optimize_size && !TARGET_USE_CLTD" | |
7292 | "#" | |
7293 | [(set_attr "type" "multi")]) | |
886c62d1 | 7294 | |
40745eec | 7295 | (define_insn "*divmodsi4_cltd" |
2bb7a0f5 | 7296 | [(set (match_operand:SI 0 "register_operand" "=a") |
40745eec JH |
7297 | (div:SI (match_operand:SI 2 "register_operand" "a") |
7298 | (match_operand:SI 3 "nonimmediate_operand" "rm"))) | |
7299 | (set (match_operand:SI 1 "register_operand" "=&d") | |
7300 | (mod:SI (match_dup 2) (match_dup 3))) | |
e075ae69 | 7301 | (clobber (reg:CC 17))] |
40745eec JH |
7302 | "optimize_size || TARGET_USE_CLTD" |
7303 | "#" | |
e075ae69 RH |
7304 | [(set_attr "type" "multi")]) |
7305 | ||
6343a50e | 7306 | (define_insn "*divmodsi_noext" |
e075ae69 | 7307 | [(set (match_operand:SI 0 "register_operand" "=a") |
40745eec | 7308 | (div:SI (match_operand:SI 1 "register_operand" "0") |
e075ae69 RH |
7309 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) |
7310 | (set (match_operand:SI 3 "register_operand" "=d") | |
7311 | (mod:SI (match_dup 1) (match_dup 2))) | |
40745eec | 7312 | (use (match_operand:SI 4 "register_operand" "3")) |
e075ae69 RH |
7313 | (clobber (reg:CC 17))] |
7314 | "" | |
0f40f9f7 | 7315 | "idiv{l}\t%2" |
e075ae69 | 7316 | [(set_attr "type" "idiv") |
6ef67412 | 7317 | (set_attr "mode" "SI") |
e075ae69 RH |
7318 | (set_attr "ppro_uops" "few")]) |
7319 | ||
7320 | (define_split | |
7321 | [(set (match_operand:SI 0 "register_operand" "") | |
7322 | (div:SI (match_operand:SI 1 "register_operand" "") | |
7323 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7324 | (set (match_operand:SI 3 "register_operand" "") | |
7325 | (mod:SI (match_dup 1) (match_dup 2))) | |
7326 | (clobber (reg:CC 17))] | |
7327 | "reload_completed" | |
7328 | [(parallel [(set (match_dup 3) | |
7329 | (ashiftrt:SI (match_dup 4) (const_int 31))) | |
7330 | (clobber (reg:CC 17))]) | |
7331 | (parallel [(set (match_dup 0) | |
40745eec | 7332 | (div:SI (reg:SI 0) (match_dup 2))) |
e075ae69 | 7333 | (set (match_dup 3) |
40745eec | 7334 | (mod:SI (reg:SI 0) (match_dup 2))) |
e075ae69 RH |
7335 | (use (match_dup 3)) |
7336 | (clobber (reg:CC 17))])] | |
886c62d1 | 7337 | { |
9cd10576 | 7338 | /* Avoid use of cltd in favor of a mov+shift. */ |
40745eec | 7339 | if (!TARGET_USE_CLTD && !optimize_size) |
e075ae69 | 7340 | { |
40745eec JH |
7341 | if (true_regnum (operands[1])) |
7342 | emit_move_insn (operands[0], operands[1]); | |
7343 | else | |
7344 | emit_move_insn (operands[3], operands[1]); | |
e075ae69 RH |
7345 | operands[4] = operands[3]; |
7346 | } | |
7347 | else | |
40745eec JH |
7348 | { |
7349 | if (true_regnum (operands[1])) | |
7350 | abort(); | |
7351 | operands[4] = operands[1]; | |
7352 | } | |
0f40f9f7 | 7353 | }) |
e075ae69 | 7354 | ;; %%% Split me. |
886c62d1 | 7355 | (define_insn "divmodhi4" |
2bb7a0f5 RS |
7356 | [(set (match_operand:HI 0 "register_operand" "=a") |
7357 | (div:HI (match_operand:HI 1 "register_operand" "0") | |
2ae0f82c | 7358 | (match_operand:HI 2 "nonimmediate_operand" "rm"))) |
2bb7a0f5 | 7359 | (set (match_operand:HI 3 "register_operand" "=&d") |
e075ae69 RH |
7360 | (mod:HI (match_dup 1) (match_dup 2))) |
7361 | (clobber (reg:CC 17))] | |
d9f32422 | 7362 | "TARGET_HIMODE_MATH" |
0f40f9f7 | 7363 | "cwtd\;idiv{w}\t%2" |
6ef67412 JH |
7364 | [(set_attr "type" "multi") |
7365 | (set_attr "length_immediate" "0") | |
7366 | (set_attr "mode" "SI")]) | |
886c62d1 | 7367 | |
9b70259d JH |
7368 | (define_insn "udivmoddi4" |
7369 | [(set (match_operand:DI 0 "register_operand" "=a") | |
7370 | (udiv:DI (match_operand:DI 1 "register_operand" "0") | |
7371 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
7372 | (set (match_operand:DI 3 "register_operand" "=&d") | |
7373 | (umod:DI (match_dup 1) (match_dup 2))) | |
7374 | (clobber (reg:CC 17))] | |
7375 | "TARGET_64BIT" | |
0f40f9f7 | 7376 | "xor{q}\t%3, %3\;div{q}\t%2" |
9b70259d JH |
7377 | [(set_attr "type" "multi") |
7378 | (set_attr "length_immediate" "0") | |
7379 | (set_attr "mode" "DI")]) | |
7380 | ||
7381 | (define_insn "*udivmoddi4_noext" | |
7382 | [(set (match_operand:DI 0 "register_operand" "=a") | |
7383 | (udiv:DI (match_operand:DI 1 "register_operand" "0") | |
7384 | (match_operand:DI 2 "nonimmediate_operand" "rm"))) | |
7385 | (set (match_operand:DI 3 "register_operand" "=d") | |
7386 | (umod:DI (match_dup 1) (match_dup 2))) | |
7387 | (use (match_dup 3)) | |
7388 | (clobber (reg:CC 17))] | |
7389 | "TARGET_64BIT" | |
0f40f9f7 | 7390 | "div{q}\t%2" |
9b70259d JH |
7391 | [(set_attr "type" "idiv") |
7392 | (set_attr "ppro_uops" "few") | |
7393 | (set_attr "mode" "DI")]) | |
7394 | ||
7395 | (define_split | |
7396 | [(set (match_operand:DI 0 "register_operand" "") | |
7397 | (udiv:DI (match_operand:DI 1 "register_operand" "") | |
7398 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7399 | (set (match_operand:DI 3 "register_operand" "") | |
7400 | (umod:DI (match_dup 1) (match_dup 2))) | |
7401 | (clobber (reg:CC 17))] | |
1b0c37d7 | 7402 | "TARGET_64BIT && reload_completed" |
9b70259d JH |
7403 | [(set (match_dup 3) (const_int 0)) |
7404 | (parallel [(set (match_dup 0) | |
7405 | (udiv:DI (match_dup 1) (match_dup 2))) | |
7406 | (set (match_dup 3) | |
7407 | (umod:DI (match_dup 1) (match_dup 2))) | |
7408 | (use (match_dup 3)) | |
7409 | (clobber (reg:CC 17))])] | |
7410 | "") | |
7411 | ||
886c62d1 | 7412 | (define_insn "udivmodsi4" |
2bb7a0f5 RS |
7413 | [(set (match_operand:SI 0 "register_operand" "=a") |
7414 | (udiv:SI (match_operand:SI 1 "register_operand" "0") | |
2ae0f82c | 7415 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) |
2bb7a0f5 | 7416 | (set (match_operand:SI 3 "register_operand" "=&d") |
e075ae69 RH |
7417 | (umod:SI (match_dup 1) (match_dup 2))) |
7418 | (clobber (reg:CC 17))] | |
886c62d1 | 7419 | "" |
0f40f9f7 | 7420 | "xor{l}\t%3, %3\;div{l}\t%2" |
6ef67412 JH |
7421 | [(set_attr "type" "multi") |
7422 | (set_attr "length_immediate" "0") | |
7423 | (set_attr "mode" "SI")]) | |
886c62d1 | 7424 | |
6343a50e | 7425 | (define_insn "*udivmodsi4_noext" |
2bb7a0f5 | 7426 | [(set (match_operand:SI 0 "register_operand" "=a") |
e075ae69 | 7427 | (udiv:SI (match_operand:SI 1 "register_operand" "0") |
2ae0f82c | 7428 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) |
2bb7a0f5 | 7429 | (set (match_operand:SI 3 "register_operand" "=d") |
e075ae69 RH |
7430 | (umod:SI (match_dup 1) (match_dup 2))) |
7431 | (use (match_dup 3)) | |
7432 | (clobber (reg:CC 17))] | |
886c62d1 | 7433 | "" |
0f40f9f7 | 7434 | "div{l}\t%2" |
e075ae69 | 7435 | [(set_attr "type" "idiv") |
6ef67412 JH |
7436 | (set_attr "ppro_uops" "few") |
7437 | (set_attr "mode" "SI")]) | |
886c62d1 | 7438 | |
e075ae69 RH |
7439 | (define_split |
7440 | [(set (match_operand:SI 0 "register_operand" "") | |
7441 | (udiv:SI (match_operand:SI 1 "register_operand" "") | |
7442 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7443 | (set (match_operand:SI 3 "register_operand" "") | |
7444 | (umod:SI (match_dup 1) (match_dup 2))) | |
7445 | (clobber (reg:CC 17))] | |
7446 | "reload_completed" | |
591702de | 7447 | [(set (match_dup 3) (const_int 0)) |
e075ae69 RH |
7448 | (parallel [(set (match_dup 0) |
7449 | (udiv:SI (match_dup 1) (match_dup 2))) | |
7450 | (set (match_dup 3) | |
7451 | (umod:SI (match_dup 1) (match_dup 2))) | |
7452 | (use (match_dup 3)) | |
7453 | (clobber (reg:CC 17))])] | |
7454 | "") | |
886c62d1 | 7455 | |
e075ae69 | 7456 | (define_expand "udivmodhi4" |
591702de | 7457 | [(set (match_dup 4) (const_int 0)) |
40745eec JH |
7458 | (parallel [(set (match_operand:HI 0 "register_operand" "") |
7459 | (udiv:HI (match_operand:HI 1 "register_operand" "") | |
7460 | (match_operand:HI 2 "nonimmediate_operand" ""))) | |
7461 | (set (match_operand:HI 3 "register_operand" "") | |
e075ae69 RH |
7462 | (umod:HI (match_dup 1) (match_dup 2))) |
7463 | (use (match_dup 4)) | |
7464 | (clobber (reg:CC 17))])] | |
d9f32422 | 7465 | "TARGET_HIMODE_MATH" |
e075ae69 | 7466 | "operands[4] = gen_reg_rtx (HImode);") |
886c62d1 | 7467 | |
6343a50e | 7468 | (define_insn "*udivmodhi_noext" |
e075ae69 RH |
7469 | [(set (match_operand:HI 0 "register_operand" "=a") |
7470 | (udiv:HI (match_operand:HI 1 "register_operand" "0") | |
7471 | (match_operand:HI 2 "nonimmediate_operand" "rm"))) | |
7472 | (set (match_operand:HI 3 "register_operand" "=d") | |
7473 | (umod:HI (match_dup 1) (match_dup 2))) | |
7474 | (use (match_operand:HI 4 "register_operand" "3")) | |
7475 | (clobber (reg:CC 17))] | |
7476 | "" | |
0f40f9f7 | 7477 | "div{w}\t%2" |
e075ae69 | 7478 | [(set_attr "type" "idiv") |
6ef67412 | 7479 | (set_attr "mode" "HI") |
e075ae69 RH |
7480 | (set_attr "ppro_uops" "few")]) |
7481 | ||
7482 | ;; We can not use div/idiv for double division, because it causes | |
7483 | ;; "division by zero" on the overflow and that's not what we expect | |
7484 | ;; from truncate. Because true (non truncating) double division is | |
7485 | ;; never generated, we can't create this insn anyway. | |
7486 | ; | |
7487 | ;(define_insn "" | |
7488 | ; [(set (match_operand:SI 0 "register_operand" "=a") | |
7489 | ; (truncate:SI | |
7490 | ; (udiv:DI (match_operand:DI 1 "register_operand" "A") | |
7491 | ; (zero_extend:DI | |
7492 | ; (match_operand:SI 2 "nonimmediate_operand" "rm"))))) | |
7493 | ; (set (match_operand:SI 3 "register_operand" "=d") | |
7494 | ; (truncate:SI | |
7495 | ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2))))) | |
7496 | ; (clobber (reg:CC 17))] | |
7497 | ; "" | |
0f40f9f7 | 7498 | ; "div{l}\t{%2, %0|%0, %2}" |
e075ae69 RH |
7499 | ; [(set_attr "type" "idiv") |
7500 | ; (set_attr "ppro_uops" "few")]) | |
886c62d1 | 7501 | \f |
e075ae69 RH |
7502 | ;;- Logical AND instructions |
7503 | ||
7504 | ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al. | |
7505 | ;; Note that this excludes ah. | |
7506 | ||
9b70259d JH |
7507 | (define_insn "*testdi_1_rex64" |
7508 | [(set (reg 17) | |
7509 | (compare | |
7510 | (and:DI (match_operand:DI 0 "nonimmediate_operand" "%*a,r,*a,r,rm") | |
7511 | (match_operand:DI 1 "x86_64_szext_nonmemory_operand" "Z,Z,e,e,re")) | |
7512 | (const_int 0)))] | |
7513 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
7514 | "@ | |
0f40f9f7 ZW |
7515 | test{l}\t{%k1, %k0|%k0, %k1} |
7516 | test{l}\t{%k1, %k0|%k0, %k1} | |
7517 | test{q}\t{%1, %0|%0, %1} | |
7518 | test{q}\t{%1, %0|%0, %1} | |
7519 | test{q}\t{%1, %0|%0, %1}" | |
9b70259d JH |
7520 | [(set_attr "type" "test") |
7521 | (set_attr "modrm" "0,1,0,1,1") | |
7522 | (set_attr "mode" "SI,SI,DI,DI,DI") | |
7523 | (set_attr "pent_pair" "uv,np,uv,np,uv")]) | |
9076b9c1 JH |
7524 | |
7525 | (define_insn "testsi_1" | |
7526 | [(set (reg 17) | |
7527 | (compare | |
16189740 RH |
7528 | (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm") |
7529 | (match_operand:SI 1 "nonmemory_operand" "in,in,rin")) | |
7530 | (const_int 0)))] | |
9076b9c1 | 7531 | "ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 7532 | "test{l}\t{%1, %0|%0, %1}" |
6ef67412 JH |
7533 | [(set_attr "type" "test") |
7534 | (set_attr "modrm" "0,1,1") | |
7535 | (set_attr "mode" "SI") | |
e075ae69 RH |
7536 | (set_attr "pent_pair" "uv,np,uv")]) |
7537 | ||
9076b9c1 | 7538 | (define_expand "testsi_ccno_1" |
e075ae69 | 7539 | [(set (reg:CCNO 17) |
16189740 | 7540 | (compare:CCNO |
9076b9c1 JH |
7541 | (and:SI (match_operand:SI 0 "nonimmediate_operand" "") |
7542 | (match_operand:SI 1 "nonmemory_operand" "")) | |
16189740 | 7543 | (const_int 0)))] |
a1cbdd7f | 7544 | "" |
9076b9c1 | 7545 | "") |
16189740 RH |
7546 | |
7547 | (define_insn "*testhi_1" | |
7548 | [(set (reg 17) | |
7549 | (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm") | |
7550 | (match_operand:HI 1 "nonmemory_operand" "n,n,rn")) | |
7551 | (const_int 0)))] | |
7552 | "ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 7553 | "test{w}\t{%1, %0|%0, %1}" |
6ef67412 JH |
7554 | [(set_attr "type" "test") |
7555 | (set_attr "modrm" "0,1,1") | |
7556 | (set_attr "mode" "HI") | |
e075ae69 RH |
7557 | (set_attr "pent_pair" "uv,np,uv")]) |
7558 | ||
9076b9c1 | 7559 | (define_expand "testqi_ccz_1" |
16189740 | 7560 | [(set (reg:CCZ 17) |
9076b9c1 JH |
7561 | (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "") |
7562 | (match_operand:QI 1 "nonmemory_operand" "")) | |
7563 | (const_int 0)))] | |
16189740 | 7564 | "" |
9076b9c1 | 7565 | "") |
16189740 | 7566 | |
9076b9c1 JH |
7567 | (define_insn "*testqi_1" |
7568 | [(set (reg 17) | |
7569 | (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r") | |
7570 | (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n")) | |
7571 | (const_int 0)))] | |
7572 | "ix86_match_ccmode (insn, CCNOmode)" | |
adc88131 JJ |
7573 | { |
7574 | if (which_alternative == 3) | |
7575 | { | |
7576 | if (GET_CODE (operands[1]) == CONST_INT | |
7577 | && (INTVAL (operands[1]) & 0xffffff00)) | |
7578 | operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); | |
0f40f9f7 | 7579 | return "test{l}\t{%1, %k0|%k0, %1}"; |
adc88131 | 7580 | } |
0f40f9f7 ZW |
7581 | return "test{b}\t{%1, %0|%0, %1}"; |
7582 | } | |
6ef67412 JH |
7583 | [(set_attr "type" "test") |
7584 | (set_attr "modrm" "0,1,1,1") | |
7585 | (set_attr "mode" "QI,QI,QI,SI") | |
7586 | (set_attr "pent_pair" "uv,np,uv,np")]) | |
e075ae69 | 7587 | |
9076b9c1 JH |
7588 | (define_expand "testqi_ext_ccno_0" |
7589 | [(set (reg:CCNO 17) | |
7590 | (compare:CCNO | |
16189740 RH |
7591 | (and:SI |
7592 | (zero_extract:SI | |
9076b9c1 | 7593 | (match_operand 0 "ext_register_operand" "") |
16189740 RH |
7594 | (const_int 8) |
7595 | (const_int 8)) | |
9076b9c1 | 7596 | (match_operand 1 "const_int_operand" "")) |
16189740 | 7597 | (const_int 0)))] |
9076b9c1 JH |
7598 | "" |
7599 | "") | |
e075ae69 | 7600 | |
9076b9c1 JH |
7601 | (define_insn "*testqi_ext_0" |
7602 | [(set (reg 17) | |
7603 | (compare | |
e075ae69 RH |
7604 | (and:SI |
7605 | (zero_extract:SI | |
d2836273 | 7606 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
7607 | (const_int 8) |
7608 | (const_int 8)) | |
7609 | (match_operand 1 "const_int_operand" "n")) | |
7610 | (const_int 0)))] | |
2f41793e | 7611 | "ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 7612 | "test{b}\t{%1, %h0|%h0, %1}" |
6ef67412 JH |
7613 | [(set_attr "type" "test") |
7614 | (set_attr "mode" "QI") | |
7615 | (set_attr "length_immediate" "1") | |
e075ae69 RH |
7616 | (set_attr "pent_pair" "np")]) |
7617 | ||
7618 | (define_insn "*testqi_ext_1" | |
16189740 RH |
7619 | [(set (reg 17) |
7620 | (compare | |
e075ae69 RH |
7621 | (and:SI |
7622 | (zero_extract:SI | |
d2836273 | 7623 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
7624 | (const_int 8) |
7625 | (const_int 8)) | |
7626 | (zero_extend:SI | |
d2836273 | 7627 | (match_operand:QI 1 "nonimmediate_operand" "Qm"))) |
e075ae69 | 7628 | (const_int 0)))] |
d2836273 | 7629 | "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 7630 | "test{b}\t{%1, %h0|%h0, %1}" |
d2836273 JH |
7631 | [(set_attr "type" "test") |
7632 | (set_attr "mode" "QI")]) | |
7633 | ||
7634 | (define_insn "*testqi_ext_1_rex64" | |
7635 | [(set (reg 17) | |
7636 | (compare | |
7637 | (and:SI | |
7638 | (zero_extract:SI | |
7639 | (match_operand 0 "ext_register_operand" "Q") | |
7640 | (const_int 8) | |
7641 | (const_int 8)) | |
7642 | (zero_extend:SI | |
3522082b | 7643 | (match_operand:QI 1 "register_operand" "Q"))) |
d2836273 JH |
7644 | (const_int 0)))] |
7645 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 7646 | "test{b}\t{%1, %h0|%h0, %1}" |
6ef67412 JH |
7647 | [(set_attr "type" "test") |
7648 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
7649 | |
7650 | (define_insn "*testqi_ext_2" | |
16189740 RH |
7651 | [(set (reg 17) |
7652 | (compare | |
e075ae69 RH |
7653 | (and:SI |
7654 | (zero_extract:SI | |
d2836273 | 7655 | (match_operand 0 "ext_register_operand" "Q") |
e075ae69 RH |
7656 | (const_int 8) |
7657 | (const_int 8)) | |
7658 | (zero_extract:SI | |
d2836273 | 7659 | (match_operand 1 "ext_register_operand" "Q") |
e075ae69 RH |
7660 | (const_int 8) |
7661 | (const_int 8))) | |
7662 | (const_int 0)))] | |
16189740 | 7663 | "ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 7664 | "test{b}\t{%h1, %h0|%h0, %h1}" |
6ef67412 JH |
7665 | [(set_attr "type" "test") |
7666 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
7667 | |
7668 | ;; Combine likes to form bit extractions for some tests. Humor it. | |
6343a50e | 7669 | (define_insn "*testqi_ext_3" |
16189740 RH |
7670 | [(set (reg 17) |
7671 | (compare (zero_extract:SI | |
7672 | (match_operand 0 "nonimmediate_operand" "rm") | |
7673 | (match_operand:SI 1 "const_int_operand" "") | |
7674 | (match_operand:SI 2 "const_int_operand" "")) | |
7675 | (const_int 0)))] | |
7676 | "ix86_match_ccmode (insn, CCNOmode) | |
7677 | && (GET_MODE (operands[0]) == SImode | |
9b70259d JH |
7678 | || (TARGET_64BIT && GET_MODE (operands[0]) == DImode) |
7679 | || GET_MODE (operands[0]) == HImode | |
7680 | || GET_MODE (operands[0]) == QImode)" | |
7681 | "#") | |
7682 | ||
7683 | (define_insn "*testqi_ext_3_rex64" | |
7684 | [(set (reg 17) | |
7685 | (compare (zero_extract:DI | |
7686 | (match_operand 0 "nonimmediate_operand" "rm") | |
7687 | (match_operand:DI 1 "const_int_operand" "") | |
7688 | (match_operand:DI 2 "const_int_operand" "")) | |
7689 | (const_int 0)))] | |
1b0c37d7 ZW |
7690 | "TARGET_64BIT |
7691 | && ix86_match_ccmode (insn, CCNOmode) | |
f5143c46 | 7692 | /* The code below cannot deal with constants outside HOST_WIDE_INT. */ |
44cf5b6a JH |
7693 | && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT |
7694 | /* Ensure that resulting mask is zero or sign extended operand. */ | |
7695 | && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 | |
7696 | || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64 | |
7697 | && INTVAL (operands[1]) > 32)) | |
9b70259d JH |
7698 | && (GET_MODE (operands[0]) == SImode |
7699 | || GET_MODE (operands[0]) == DImode | |
16189740 RH |
7700 | || GET_MODE (operands[0]) == HImode |
7701 | || GET_MODE (operands[0]) == QImode)" | |
e075ae69 | 7702 | "#") |
4fce8e83 | 7703 | |
e075ae69 | 7704 | (define_split |
16189740 | 7705 | [(set (reg 17) |
9b70259d | 7706 | (compare (zero_extract |
d5d6a58b | 7707 | (match_operand 0 "nonimmediate_operand" "") |
9b70259d JH |
7708 | (match_operand 1 "const_int_operand" "") |
7709 | (match_operand 2 "const_int_operand" "")) | |
16189740 RH |
7710 | (const_int 0)))] |
7711 | "ix86_match_ccmode (insn, CCNOmode)" | |
e075ae69 | 7712 | [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] |
e075ae69 RH |
7713 | { |
7714 | HOST_WIDE_INT len = INTVAL (operands[1]); | |
7715 | HOST_WIDE_INT pos = INTVAL (operands[2]); | |
7716 | HOST_WIDE_INT mask; | |
592188a5 | 7717 | enum machine_mode mode, submode; |
886c62d1 | 7718 | |
e075ae69 RH |
7719 | mode = GET_MODE (operands[0]); |
7720 | if (GET_CODE (operands[0]) == MEM) | |
5bc7cd8e | 7721 | { |
e075ae69 RH |
7722 | /* ??? Combine likes to put non-volatile mem extractions in QImode |
7723 | no matter the size of the test. So find a mode that works. */ | |
7724 | if (! MEM_VOLATILE_P (operands[0])) | |
7725 | { | |
7726 | mode = smallest_mode_for_size (pos + len, MODE_INT); | |
f4ef873c | 7727 | operands[0] = adjust_address (operands[0], mode, 0); |
e075ae69 | 7728 | } |
5bc7cd8e | 7729 | } |
592188a5 RH |
7730 | else if (GET_CODE (operands[0]) == SUBREG |
7731 | && (submode = GET_MODE (SUBREG_REG (operands[0])), | |
7732 | GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode)) | |
7733 | && pos + len <= GET_MODE_BITSIZE (submode)) | |
7734 | { | |
7735 | /* Narrow a paradoxical subreg to prevent partial register stalls. */ | |
7736 | mode = submode; | |
7737 | operands[0] = SUBREG_REG (operands[0]); | |
7738 | } | |
e075ae69 | 7739 | else if (mode == HImode && pos + len <= 8) |
5bc7cd8e | 7740 | { |
e075ae69 RH |
7741 | /* Small HImode tests can be converted to QImode. */ |
7742 | mode = QImode; | |
7743 | operands[0] = gen_lowpart (QImode, operands[0]); | |
5bc7cd8e SC |
7744 | } |
7745 | ||
e075ae69 RH |
7746 | mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1; |
7747 | mask &= ~(((HOST_WIDE_INT)1 << pos) - 1); | |
886c62d1 | 7748 | |
d8bf17f9 | 7749 | operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode)); |
0f40f9f7 | 7750 | }) |
886c62d1 | 7751 | |
6c81a490 JH |
7752 | ;; Convert HImode/SImode test instructions with immediate to QImode ones. |
7753 | ;; i386 does not allow to encode test with 8bit sign extended immediate, so | |
7754 | ;; this is relatively important trick. | |
7755 | ;; Do the converison only post-reload to avoid limiting of the register class | |
7756 | ;; to QI regs. | |
7757 | (define_split | |
7758 | [(set (reg 17) | |
7759 | (compare | |
7760 | (and (match_operand 0 "register_operand" "") | |
7761 | (match_operand 1 "const_int_operand" "")) | |
7762 | (const_int 0)))] | |
2f41793e | 7763 | "reload_completed |
6c81a490 JH |
7764 | && QI_REG_P (operands[0]) |
7765 | && ((ix86_match_ccmode (insn, CCZmode) | |
7766 | && !(INTVAL (operands[1]) & ~(255 << 8))) | |
7767 | || (ix86_match_ccmode (insn, CCNOmode) | |
7768 | && !(INTVAL (operands[1]) & ~(127 << 8)))) | |
7769 | && GET_MODE (operands[0]) != QImode" | |
7770 | [(set (reg:CCNO 17) | |
7771 | (compare:CCNO | |
7772 | (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) | |
7773 | (match_dup 1)) | |
7774 | (const_int 0)))] | |
7775 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
b18b06ed | 7776 | operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);") |
6c81a490 JH |
7777 | |
7778 | (define_split | |
7779 | [(set (reg 17) | |
7780 | (compare | |
7781 | (and (match_operand 0 "nonimmediate_operand" "") | |
7782 | (match_operand 1 "const_int_operand" "")) | |
7783 | (const_int 0)))] | |
2f41793e | 7784 | "reload_completed |
6c81a490 JH |
7785 | && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0])) |
7786 | && ((ix86_match_ccmode (insn, CCZmode) | |
7787 | && !(INTVAL (operands[1]) & ~255)) | |
7788 | || (ix86_match_ccmode (insn, CCNOmode) | |
7789 | && !(INTVAL (operands[1]) & ~127))) | |
7790 | && GET_MODE (operands[0]) != QImode" | |
7791 | [(set (reg:CCNO 17) | |
7792 | (compare:CCNO | |
7793 | (and:QI (match_dup 0) | |
7794 | (match_dup 1)) | |
7795 | (const_int 0)))] | |
7796 | "operands[0] = gen_lowpart (QImode, operands[0]); | |
7797 | operands[1] = gen_lowpart (QImode, operands[1]);") | |
7798 | ||
7799 | ||
e075ae69 RH |
7800 | ;; %%% This used to optimize known byte-wide and operations to memory, |
7801 | ;; and sometimes to QImode registers. If this is considered useful, | |
7802 | ;; it should be done with splitters. | |
7803 | ||
9b70259d JH |
7804 | (define_expand "anddi3" |
7805 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
7806 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
7807 | (match_operand:DI 2 "x86_64_szext_general_operand" ""))) | |
7808 | (clobber (reg:CC 17))] | |
7809 | "TARGET_64BIT" | |
7810 | "ix86_expand_binary_operator (AND, DImode, operands); DONE;") | |
7811 | ||
7812 | (define_insn "*anddi_1_rex64" | |
7813 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r") | |
7814 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm") | |
7815 | (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L"))) | |
7816 | (clobber (reg:CC 17))] | |
7817 | "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)" | |
9b70259d JH |
7818 | { |
7819 | switch (get_attr_type (insn)) | |
7820 | { | |
7821 | case TYPE_IMOVX: | |
7822 | { | |
7823 | enum machine_mode mode; | |
7824 | ||
7825 | if (GET_CODE (operands[2]) != CONST_INT) | |
7826 | abort (); | |
7827 | if (INTVAL (operands[2]) == 0xff) | |
7828 | mode = QImode; | |
7829 | else if (INTVAL (operands[2]) == 0xffff) | |
7830 | mode = HImode; | |
7831 | else | |
7832 | abort (); | |
7833 | ||
7834 | operands[1] = gen_lowpart (mode, operands[1]); | |
7835 | if (mode == QImode) | |
0f40f9f7 | 7836 | return "movz{bq|x}\t{%1,%0|%0, %1}"; |
9b70259d | 7837 | else |
0f40f9f7 | 7838 | return "movz{wq|x}\t{%1,%0|%0, %1}"; |
9b70259d JH |
7839 | } |
7840 | ||
7841 | default: | |
7842 | if (! rtx_equal_p (operands[0], operands[1])) | |
7843 | abort (); | |
7844 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 7845 | return "and{l}\t{%k2, %k0|%k0, %k2}"; |
9b70259d | 7846 | else |
0f40f9f7 | 7847 | return "and{q}\t{%2, %0|%0, %2}"; |
9b70259d | 7848 | } |
0f40f9f7 | 7849 | } |
9b70259d JH |
7850 | [(set_attr "type" "alu,alu,alu,imovx") |
7851 | (set_attr "length_immediate" "*,*,*,0") | |
7852 | (set_attr "mode" "SI,DI,DI,DI")]) | |
7853 | ||
7854 | (define_insn "*anddi_2" | |
7855 | [(set (reg 17) | |
7856 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") | |
7857 | (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re")) | |
7858 | (const_int 0))) | |
7859 | (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm") | |
7860 | (and:DI (match_dup 1) (match_dup 2)))] | |
7861 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
7862 | && ix86_binary_operator_ok (AND, DImode, operands)" | |
7863 | "@ | |
0f40f9f7 ZW |
7864 | and{l}\t{%k2, %k0|%k0, %k2} |
7865 | and{q}\t{%2, %0|%0, %2} | |
7866 | and{q}\t{%2, %0|%0, %2}" | |
9b70259d JH |
7867 | [(set_attr "type" "alu") |
7868 | (set_attr "mode" "SI,DI,DI")]) | |
7869 | ||
e075ae69 RH |
7870 | (define_expand "andsi3" |
7871 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
7872 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
7873 | (match_operand:SI 2 "general_operand" ""))) | |
7874 | (clobber (reg:CC 17))] | |
7875 | "" | |
7876 | "ix86_expand_binary_operator (AND, SImode, operands); DONE;") | |
7877 | ||
7878 | (define_insn "*andsi_1" | |
7879 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r") | |
7880 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm") | |
7881 | (match_operand:SI 2 "general_operand" "ri,rm,L"))) | |
7882 | (clobber (reg:CC 17))] | |
7883 | "ix86_binary_operator_ok (AND, SImode, operands)" | |
886c62d1 | 7884 | { |
e075ae69 | 7885 | switch (get_attr_type (insn)) |
886c62d1 | 7886 | { |
e075ae69 RH |
7887 | case TYPE_IMOVX: |
7888 | { | |
7889 | enum machine_mode mode; | |
5bc7cd8e | 7890 | |
e075ae69 RH |
7891 | if (GET_CODE (operands[2]) != CONST_INT) |
7892 | abort (); | |
7893 | if (INTVAL (operands[2]) == 0xff) | |
7894 | mode = QImode; | |
7895 | else if (INTVAL (operands[2]) == 0xffff) | |
7896 | mode = HImode; | |
7897 | else | |
7898 | abort (); | |
7899 | ||
7900 | operands[1] = gen_lowpart (mode, operands[1]); | |
7901 | if (mode == QImode) | |
0f40f9f7 | 7902 | return "movz{bl|x}\t{%1,%0|%0, %1}"; |
e075ae69 | 7903 | else |
0f40f9f7 | 7904 | return "movz{wl|x}\t{%1,%0|%0, %1}"; |
e075ae69 | 7905 | } |
5bc7cd8e | 7906 | |
e075ae69 RH |
7907 | default: |
7908 | if (! rtx_equal_p (operands[0], operands[1])) | |
7909 | abort (); | |
0f40f9f7 | 7910 | return "and{l}\t{%2, %0|%0, %2}"; |
886c62d1 | 7911 | } |
0f40f9f7 | 7912 | } |
6ef67412 JH |
7913 | [(set_attr "type" "alu,alu,imovx") |
7914 | (set_attr "length_immediate" "*,*,0") | |
7915 | (set_attr "mode" "SI")]) | |
7916 | ||
7917 | (define_split | |
05b432db | 7918 | [(set (match_operand 0 "register_operand" "") |
9b70259d JH |
7919 | (and (match_dup 0) |
7920 | (const_int -65536))) | |
6ef67412 | 7921 | (clobber (reg:CC 17))] |
285464d0 | 7922 | "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)" |
6ef67412 JH |
7923 | [(set (strict_low_part (match_dup 1)) (const_int 0))] |
7924 | "operands[1] = gen_lowpart (HImode, operands[0]);") | |
7925 | ||
7926 | (define_split | |
3522082b | 7927 | [(set (match_operand 0 "ext_register_operand" "") |
5e1a2fc7 | 7928 | (and (match_dup 0) |
9b70259d | 7929 | (const_int -256))) |
6ef67412 | 7930 | (clobber (reg:CC 17))] |
05b432db | 7931 | "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed" |
6ef67412 JH |
7932 | [(set (strict_low_part (match_dup 1)) (const_int 0))] |
7933 | "operands[1] = gen_lowpart (QImode, operands[0]);") | |
7934 | ||
7935 | (define_split | |
3522082b | 7936 | [(set (match_operand 0 "ext_register_operand" "") |
6ef67412 JH |
7937 | (and (match_dup 0) |
7938 | (const_int -65281))) | |
7939 | (clobber (reg:CC 17))] | |
05b432db | 7940 | "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed" |
6ef67412 JH |
7941 | [(parallel [(set (zero_extract:SI (match_dup 0) |
7942 | (const_int 8) | |
7943 | (const_int 8)) | |
7944 | (xor:SI | |
7945 | (zero_extract:SI (match_dup 0) | |
7946 | (const_int 8) | |
7947 | (const_int 8)) | |
7948 | (zero_extract:SI (match_dup 0) | |
7949 | (const_int 8) | |
7950 | (const_int 8)))) | |
7951 | (clobber (reg:CC 17))])] | |
7952 | "operands[0] = gen_lowpart (SImode, operands[0]);") | |
e075ae69 | 7953 | |
9b70259d JH |
7954 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
7955 | (define_insn "*andsi_1_zext" | |
7956 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7957 | (zero_extend:DI | |
7958 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
7959 | (match_operand:SI 2 "general_operand" "rim")))) | |
7960 | (clobber (reg:CC 17))] | |
7961 | "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)" | |
0f40f9f7 | 7962 | "and{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
7963 | [(set_attr "type" "alu") |
7964 | (set_attr "mode" "SI")]) | |
7965 | ||
e075ae69 | 7966 | (define_insn "*andsi_2" |
16189740 RH |
7967 | [(set (reg 17) |
7968 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
7969 | (match_operand:SI 2 "general_operand" "rim,ri")) | |
7970 | (const_int 0))) | |
e075ae69 RH |
7971 | (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") |
7972 | (and:SI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
7973 | "ix86_match_ccmode (insn, CCNOmode) |
7974 | && ix86_binary_operator_ok (AND, SImode, operands)" | |
0f40f9f7 | 7975 | "and{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
7976 | [(set_attr "type" "alu") |
7977 | (set_attr "mode" "SI")]) | |
e075ae69 | 7978 | |
9b70259d JH |
7979 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
7980 | (define_insn "*andsi_2_zext" | |
7981 | [(set (reg 17) | |
7982 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
7983 | (match_operand:SI 2 "general_operand" "rim")) | |
7984 | (const_int 0))) | |
7985 | (set (match_operand:DI 0 "register_operand" "=r") | |
7986 | (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] | |
7987 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
7988 | && ix86_binary_operator_ok (AND, SImode, operands)" | |
0f40f9f7 | 7989 | "and{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
7990 | [(set_attr "type" "alu") |
7991 | (set_attr "mode" "SI")]) | |
7992 | ||
e075ae69 RH |
7993 | (define_expand "andhi3" |
7994 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
7995 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
7996 | (match_operand:HI 2 "general_operand" ""))) | |
7997 | (clobber (reg:CC 17))] | |
d9f32422 | 7998 | "TARGET_HIMODE_MATH" |
e075ae69 RH |
7999 | "ix86_expand_binary_operator (AND, HImode, operands); DONE;") |
8000 | ||
8001 | (define_insn "*andhi_1" | |
8002 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") | |
8003 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm") | |
8004 | (match_operand:HI 2 "general_operand" "ri,rm,L"))) | |
8005 | (clobber (reg:CC 17))] | |
8006 | "ix86_binary_operator_ok (AND, HImode, operands)" | |
886c62d1 | 8007 | { |
e075ae69 | 8008 | switch (get_attr_type (insn)) |
886c62d1 | 8009 | { |
e075ae69 RH |
8010 | case TYPE_IMOVX: |
8011 | if (GET_CODE (operands[2]) != CONST_INT) | |
8012 | abort (); | |
8013 | if (INTVAL (operands[2]) == 0xff) | |
0f40f9f7 | 8014 | return "movz{bl|x}\t{%b1, %k0|%k0, %b1}"; |
e075ae69 | 8015 | abort (); |
886c62d1 | 8016 | |
e075ae69 RH |
8017 | default: |
8018 | if (! rtx_equal_p (operands[0], operands[1])) | |
8019 | abort (); | |
886c62d1 | 8020 | |
0f40f9f7 | 8021 | return "and{w}\t{%2, %0|%0, %2}"; |
5bc7cd8e | 8022 | } |
0f40f9f7 | 8023 | } |
6ef67412 JH |
8024 | [(set_attr "type" "alu,alu,imovx") |
8025 | (set_attr "length_immediate" "*,*,0") | |
8026 | (set_attr "mode" "HI,HI,SI")]) | |
5bc7cd8e | 8027 | |
e075ae69 | 8028 | (define_insn "*andhi_2" |
16189740 RH |
8029 | [(set (reg 17) |
8030 | (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
8031 | (match_operand:HI 2 "general_operand" "rim,ri")) | |
8032 | (const_int 0))) | |
e075ae69 RH |
8033 | (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") |
8034 | (and:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8035 | "ix86_match_ccmode (insn, CCNOmode) |
8036 | && ix86_binary_operator_ok (AND, HImode, operands)" | |
0f40f9f7 | 8037 | "and{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8038 | [(set_attr "type" "alu") |
8039 | (set_attr "mode" "HI")]) | |
5bc7cd8e | 8040 | |
e075ae69 RH |
8041 | (define_expand "andqi3" |
8042 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
8043 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
8044 | (match_operand:QI 2 "general_operand" ""))) | |
8045 | (clobber (reg:CC 17))] | |
d9f32422 | 8046 | "TARGET_QIMODE_MATH" |
e075ae69 RH |
8047 | "ix86_expand_binary_operator (AND, QImode, operands); DONE;") |
8048 | ||
8049 | ;; %%% Potential partial reg stall on alternative 2. What to do? | |
8050 | (define_insn "*andqi_1" | |
7c6b971d | 8051 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") |
e075ae69 | 8052 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") |
7c6b971d | 8053 | (match_operand:QI 2 "general_operand" "qi,qmi,ri"))) |
e075ae69 RH |
8054 | (clobber (reg:CC 17))] |
8055 | "ix86_binary_operator_ok (AND, QImode, operands)" | |
8056 | "@ | |
0f40f9f7 ZW |
8057 | and{b}\t{%2, %0|%0, %2} |
8058 | and{b}\t{%2, %0|%0, %2} | |
8059 | and{l}\t{%k2, %k0|%k0, %k2}" | |
6ef67412 JH |
8060 | [(set_attr "type" "alu") |
8061 | (set_attr "mode" "QI,QI,SI")]) | |
e075ae69 | 8062 | |
a1b8572c JH |
8063 | (define_insn "*andqi_1_slp" |
8064 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) | |
8065 | (and:QI (match_dup 0) | |
8066 | (match_operand:QI 1 "general_operand" "qi,qmi"))) | |
8067 | (clobber (reg:CC 17))] | |
2f41793e | 8068 | "! TARGET_PARTIAL_REG_STALL || optimize_size" |
0f40f9f7 | 8069 | "and{b}\t{%1, %0|%0, %1}" |
a1b8572c JH |
8070 | [(set_attr "type" "alu1") |
8071 | (set_attr "mode" "QI")]) | |
8072 | ||
e075ae69 | 8073 | (define_insn "*andqi_2" |
16189740 RH |
8074 | [(set (reg 17) |
8075 | (compare (and:QI | |
8076 | (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
8077 | (match_operand:QI 2 "general_operand" "qim,qi,i")) | |
8078 | (const_int 0))) | |
e075ae69 RH |
8079 | (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r") |
8080 | (and:QI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8081 | "ix86_match_ccmode (insn, CCNOmode) |
8082 | && ix86_binary_operator_ok (AND, QImode, operands)" | |
adc88131 JJ |
8083 | { |
8084 | if (which_alternative == 2) | |
8085 | { | |
8086 | if (GET_CODE (operands[2]) == CONST_INT | |
8087 | && (INTVAL (operands[2]) & 0xffffff00)) | |
8088 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); | |
0f40f9f7 | 8089 | return "and{l}\t{%2, %k0|%k0, %2}"; |
adc88131 | 8090 | } |
0f40f9f7 ZW |
8091 | return "and{b}\t{%2, %0|%0, %2}"; |
8092 | } | |
6ef67412 JH |
8093 | [(set_attr "type" "alu") |
8094 | (set_attr "mode" "QI,QI,SI")]) | |
e075ae69 | 8095 | |
a1b8572c JH |
8096 | (define_insn "*andqi_2_slp" |
8097 | [(set (reg 17) | |
8098 | (compare (and:QI | |
8099 | (match_operand:QI 0 "nonimmediate_operand" "+q,qm") | |
8100 | (match_operand:QI 1 "nonimmediate_operand" "qmi,qi")) | |
8101 | (const_int 0))) | |
8102 | (set (strict_low_part (match_dup 0)) | |
8103 | (and:QI (match_dup 0) (match_dup 1)))] | |
2f41793e JH |
8104 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) |
8105 | && ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 8106 | "and{b}\t{%1, %0|%0, %1}" |
a1b8572c JH |
8107 | [(set_attr "type" "alu1") |
8108 | (set_attr "mode" "QI")]) | |
8109 | ||
e075ae69 RH |
8110 | ;; ??? A bug in recog prevents it from recognizing a const_int as an |
8111 | ;; operand to zero_extend in andqi_ext_1. It was checking explicitly | |
8112 | ;; for a QImode operand, which of course failed. | |
8113 | ||
8114 | (define_insn "andqi_ext_0" | |
d2836273 | 8115 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
8116 | (const_int 8) |
8117 | (const_int 8)) | |
8118 | (and:SI | |
8119 | (zero_extract:SI | |
8120 | (match_operand 1 "ext_register_operand" "0") | |
8121 | (const_int 8) | |
8122 | (const_int 8)) | |
8123 | (match_operand 2 "const_int_operand" "n"))) | |
8124 | (clobber (reg:CC 17))] | |
2f41793e | 8125 | "" |
0f40f9f7 | 8126 | "and{b}\t{%2, %h0|%h0, %2}" |
6ef67412 JH |
8127 | [(set_attr "type" "alu") |
8128 | (set_attr "length_immediate" "1") | |
8129 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
8130 | |
8131 | ;; Generated by peephole translating test to and. This shows up | |
8132 | ;; often in fp comparisons. | |
8133 | ||
8134 | (define_insn "*andqi_ext_0_cc" | |
16189740 RH |
8135 | [(set (reg 17) |
8136 | (compare | |
e075ae69 RH |
8137 | (and:SI |
8138 | (zero_extract:SI | |
084e679a | 8139 | (match_operand 1 "ext_register_operand" "0") |
3522082b | 8140 | (const_int 8) |
e075ae69 RH |
8141 | (const_int 8)) |
8142 | (match_operand 2 "const_int_operand" "n")) | |
8143 | (const_int 0))) | |
d2836273 | 8144 | (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
8145 | (const_int 8) |
8146 | (const_int 8)) | |
8147 | (and:SI | |
8148 | (zero_extract:SI | |
8149 | (match_dup 1) | |
8150 | (const_int 8) | |
8151 | (const_int 8)) | |
8152 | (match_dup 2)))] | |
2f41793e | 8153 | "ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 8154 | "and{b}\t{%2, %h0|%h0, %2}" |
6ef67412 JH |
8155 | [(set_attr "type" "alu") |
8156 | (set_attr "length_immediate" "1") | |
8157 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
8158 | |
8159 | (define_insn "*andqi_ext_1" | |
d2836273 | 8160 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
8161 | (const_int 8) |
8162 | (const_int 8)) | |
8163 | (and:SI | |
8164 | (zero_extract:SI | |
8165 | (match_operand 1 "ext_register_operand" "0") | |
8166 | (const_int 8) | |
8167 | (const_int 8)) | |
8168 | (zero_extend:SI | |
d2836273 | 8169 | (match_operand:QI 2 "general_operand" "Qm")))) |
e075ae69 | 8170 | (clobber (reg:CC 17))] |
d2836273 | 8171 | "!TARGET_64BIT" |
0f40f9f7 | 8172 | "and{b}\t{%2, %h0|%h0, %2}" |
d2836273 JH |
8173 | [(set_attr "type" "alu") |
8174 | (set_attr "length_immediate" "0") | |
8175 | (set_attr "mode" "QI")]) | |
8176 | ||
8177 | (define_insn "*andqi_ext_1_rex64" | |
8178 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
8179 | (const_int 8) | |
8180 | (const_int 8)) | |
8181 | (and:SI | |
8182 | (zero_extract:SI | |
8183 | (match_operand 1 "ext_register_operand" "0") | |
8184 | (const_int 8) | |
8185 | (const_int 8)) | |
8186 | (zero_extend:SI | |
3522082b | 8187 | (match_operand 2 "ext_register_operand" "Q")))) |
d2836273 JH |
8188 | (clobber (reg:CC 17))] |
8189 | "TARGET_64BIT" | |
0f40f9f7 | 8190 | "and{b}\t{%2, %h0|%h0, %2}" |
6ef67412 JH |
8191 | [(set_attr "type" "alu") |
8192 | (set_attr "length_immediate" "0") | |
8193 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
8194 | |
8195 | (define_insn "*andqi_ext_2" | |
d2836273 | 8196 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
e075ae69 RH |
8197 | (const_int 8) |
8198 | (const_int 8)) | |
8199 | (and:SI | |
8200 | (zero_extract:SI | |
8201 | (match_operand 1 "ext_register_operand" "%0") | |
8202 | (const_int 8) | |
8203 | (const_int 8)) | |
8204 | (zero_extract:SI | |
d2836273 | 8205 | (match_operand 2 "ext_register_operand" "Q") |
e075ae69 RH |
8206 | (const_int 8) |
8207 | (const_int 8)))) | |
8208 | (clobber (reg:CC 17))] | |
8209 | "" | |
0f40f9f7 | 8210 | "and{b}\t{%h2, %h0|%h0, %h2}" |
6ef67412 JH |
8211 | [(set_attr "type" "alu") |
8212 | (set_attr "length_immediate" "0") | |
8213 | (set_attr "mode" "QI")]) | |
2f41793e JH |
8214 | |
8215 | ;; Convert wide AND instructions with immediate operand to shorter QImode | |
8216 | ;; equivalents when possible. | |
8217 | ;; Don't do the splitting with memory operands, since it intoduces risc | |
8218 | ;; of memory mismatch stalls. We may want to do the splitting for optimizing | |
8219 | ;; for size, but that can (should?) be handled by generic code instead. | |
8220 | (define_split | |
8221 | [(set (match_operand 0 "register_operand" "") | |
8222 | (and (match_operand 1 "register_operand" "") | |
8223 | (match_operand 2 "const_int_operand" ""))) | |
8224 | (clobber (reg:CC 17))] | |
8225 | "reload_completed | |
8226 | && QI_REG_P (operands[0]) | |
8227 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) | |
8228 | && !(~INTVAL (operands[2]) & ~(255 << 8)) | |
8229 | && GET_MODE (operands[0]) != QImode" | |
8230 | [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) | |
8231 | (and:SI (zero_extract:SI (match_dup 1) | |
8232 | (const_int 8) (const_int 8)) | |
8233 | (match_dup 2))) | |
8234 | (clobber (reg:CC 17))])] | |
8235 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
8236 | operands[1] = gen_lowpart (SImode, operands[1]); | |
8237 | operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") | |
8238 | ||
8239 | ;; Since AND can be encoded with sign extended immediate, this is only | |
8240 | ;; profitable when 7th bit is not set. | |
8241 | (define_split | |
8242 | [(set (match_operand 0 "register_operand" "") | |
8243 | (and (match_operand 1 "general_operand" "") | |
8244 | (match_operand 2 "const_int_operand" ""))) | |
8245 | (clobber (reg:CC 17))] | |
8246 | "reload_completed | |
8247 | && ANY_QI_REG_P (operands[0]) | |
8248 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) | |
8249 | && !(~INTVAL (operands[2]) & ~255) | |
8250 | && !(INTVAL (operands[2]) & 128) | |
8251 | && GET_MODE (operands[0]) != QImode" | |
8252 | [(parallel [(set (strict_low_part (match_dup 0)) | |
8253 | (and:QI (match_dup 1) | |
8254 | (match_dup 2))) | |
8255 | (clobber (reg:CC 17))])] | |
8256 | "operands[0] = gen_lowpart (QImode, operands[0]); | |
8257 | operands[1] = gen_lowpart (QImode, operands[1]); | |
8258 | operands[2] = gen_lowpart (QImode, operands[2]);") | |
886c62d1 | 8259 | \f |
e075ae69 | 8260 | ;; Logical inclusive OR instructions |
57dbca5e | 8261 | |
e075ae69 RH |
8262 | ;; %%% This used to optimize known byte-wide and operations to memory. |
8263 | ;; If this is considered useful, it should be done with splitters. | |
8264 | ||
9b70259d JH |
8265 | (define_expand "iordi3" |
8266 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8267 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
8268 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
8269 | (clobber (reg:CC 17))] | |
8270 | "TARGET_64BIT" | |
8271 | "ix86_expand_binary_operator (IOR, DImode, operands); DONE;") | |
8272 | ||
8273 | (define_insn "*iordi_1_rex64" | |
8274 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
8275 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
8276 | (match_operand:DI 2 "x86_64_general_operand" "re,rme"))) | |
8277 | (clobber (reg:CC 17))] | |
8278 | "TARGET_64BIT | |
8279 | && ix86_binary_operator_ok (IOR, DImode, operands)" | |
0f40f9f7 | 8280 | "or{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
8281 | [(set_attr "type" "alu") |
8282 | (set_attr "mode" "DI")]) | |
8283 | ||
8284 | (define_insn "*iordi_2_rex64" | |
8285 | [(set (reg 17) | |
8286 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
8287 | (match_operand:DI 2 "x86_64_general_operand" "rem,re")) | |
8288 | (const_int 0))) | |
8289 | (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") | |
8290 | (ior:DI (match_dup 1) (match_dup 2)))] | |
8291 | "TARGET_64BIT | |
8292 | && ix86_match_ccmode (insn, CCNOmode) | |
8293 | && ix86_binary_operator_ok (IOR, DImode, operands)" | |
0f40f9f7 | 8294 | "or{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
8295 | [(set_attr "type" "alu") |
8296 | (set_attr "mode" "DI")]) | |
8297 | ||
8298 | (define_insn "*iordi_3_rex64" | |
8299 | [(set (reg 17) | |
8300 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
8301 | (match_operand:DI 2 "x86_64_general_operand" "rem")) | |
8302 | (const_int 0))) | |
8303 | (clobber (match_scratch:DI 0 "=r"))] | |
8304 | "TARGET_64BIT | |
8305 | && ix86_match_ccmode (insn, CCNOmode) | |
8306 | && ix86_binary_operator_ok (IOR, DImode, operands)" | |
0f40f9f7 | 8307 | "or{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
8308 | [(set_attr "type" "alu") |
8309 | (set_attr "mode" "DI")]) | |
8310 | ||
8311 | ||
e075ae69 RH |
8312 | (define_expand "iorsi3" |
8313 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
8314 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
8315 | (match_operand:SI 2 "general_operand" ""))) | |
8316 | (clobber (reg:CC 17))] | |
57dbca5e | 8317 | "" |
e075ae69 RH |
8318 | "ix86_expand_binary_operator (IOR, SImode, operands); DONE;") |
8319 | ||
8320 | (define_insn "*iorsi_1" | |
8321 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") | |
8322 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
8323 | (match_operand:SI 2 "general_operand" "ri,rmi"))) | |
8324 | (clobber (reg:CC 17))] | |
8325 | "ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8326 | "or{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8327 | [(set_attr "type" "alu") |
8328 | (set_attr "mode" "SI")]) | |
e075ae69 | 8329 | |
9b70259d JH |
8330 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8331 | (define_insn "*iorsi_1_zext" | |
8332 | [(set (match_operand:DI 0 "register_operand" "=rm") | |
8333 | (zero_extend:DI | |
8334 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8335 | (match_operand:SI 2 "general_operand" "rim")))) | |
8336 | (clobber (reg:CC 17))] | |
8337 | "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8338 | "or{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8339 | [(set_attr "type" "alu") |
8340 | (set_attr "mode" "SI")]) | |
8341 | ||
8342 | (define_insn "*iorsi_1_zext_imm" | |
8343 | [(set (match_operand:DI 0 "register_operand" "=rm") | |
8344 | (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) | |
8345 | (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) | |
8346 | (clobber (reg:CC 17))] | |
8347 | "TARGET_64BIT" | |
0f40f9f7 | 8348 | "or{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8349 | [(set_attr "type" "alu") |
8350 | (set_attr "mode" "SI")]) | |
8351 | ||
e075ae69 | 8352 | (define_insn "*iorsi_2" |
16189740 RH |
8353 | [(set (reg 17) |
8354 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
8355 | (match_operand:SI 2 "general_operand" "rim,ri")) | |
8356 | (const_int 0))) | |
e075ae69 RH |
8357 | (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") |
8358 | (ior:SI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8359 | "ix86_match_ccmode (insn, CCNOmode) |
8360 | && ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8361 | "or{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8362 | [(set_attr "type" "alu") |
8363 | (set_attr "mode" "SI")]) | |
e075ae69 | 8364 | |
9b70259d JH |
8365 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8366 | ;; ??? Special case for immediate operand is missing - it is tricky. | |
8367 | (define_insn "*iorsi_2_zext" | |
8368 | [(set (reg 17) | |
8369 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8370 | (match_operand:SI 2 "general_operand" "rim")) | |
8371 | (const_int 0))) | |
8372 | (set (match_operand:DI 0 "register_operand" "=r") | |
8373 | (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))] | |
8374 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8375 | && ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8376 | "or{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8377 | [(set_attr "type" "alu") |
8378 | (set_attr "mode" "SI")]) | |
8379 | ||
8380 | (define_insn "*iorsi_2_zext_imm" | |
8381 | [(set (reg 17) | |
8382 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8383 | (match_operand 2 "x86_64_zext_immediate_operand" "Z")) | |
8384 | (const_int 0))) | |
8385 | (set (match_operand:DI 0 "register_operand" "=r") | |
8386 | (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] | |
8387 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8388 | && ix86_binary_operator_ok (IOR, SImode, operands)" | |
0f40f9f7 | 8389 | "or{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8390 | [(set_attr "type" "alu") |
8391 | (set_attr "mode" "SI")]) | |
8392 | ||
d90ffc8d JH |
8393 | (define_insn "*iorsi_3" |
8394 | [(set (reg 17) | |
8395 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8396 | (match_operand:SI 2 "general_operand" "rim")) | |
8397 | (const_int 0))) | |
8398 | (clobber (match_scratch:SI 0 "=r"))] | |
8399 | "ix86_match_ccmode (insn, CCNOmode) | |
8400 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8401 | "or{l}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8402 | [(set_attr "type" "alu") |
8403 | (set_attr "mode" "SI")]) | |
8404 | ||
e075ae69 RH |
8405 | (define_expand "iorhi3" |
8406 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
8407 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
8408 | (match_operand:HI 2 "general_operand" ""))) | |
8409 | (clobber (reg:CC 17))] | |
d9f32422 | 8410 | "TARGET_HIMODE_MATH" |
e075ae69 RH |
8411 | "ix86_expand_binary_operator (IOR, HImode, operands); DONE;") |
8412 | ||
8413 | (define_insn "*iorhi_1" | |
8414 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m") | |
8415 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
8416 | (match_operand:HI 2 "general_operand" "rmi,ri"))) | |
8417 | (clobber (reg:CC 17))] | |
8418 | "ix86_binary_operator_ok (IOR, HImode, operands)" | |
0f40f9f7 | 8419 | "or{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8420 | [(set_attr "type" "alu") |
8421 | (set_attr "mode" "HI")]) | |
e075ae69 | 8422 | |
e075ae69 | 8423 | (define_insn "*iorhi_2" |
16189740 RH |
8424 | [(set (reg 17) |
8425 | (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
8426 | (match_operand:HI 2 "general_operand" "rim,ri")) | |
8427 | (const_int 0))) | |
e075ae69 RH |
8428 | (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") |
8429 | (ior:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8430 | "ix86_match_ccmode (insn, CCNOmode) |
8431 | && ix86_binary_operator_ok (IOR, HImode, operands)" | |
0f40f9f7 | 8432 | "or{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8433 | [(set_attr "type" "alu") |
8434 | (set_attr "mode" "HI")]) | |
e075ae69 | 8435 | |
d90ffc8d JH |
8436 | (define_insn "*iorhi_3" |
8437 | [(set (reg 17) | |
8438 | (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0") | |
8439 | (match_operand:HI 2 "general_operand" "rim")) | |
8440 | (const_int 0))) | |
8441 | (clobber (match_scratch:HI 0 "=r"))] | |
8442 | "ix86_match_ccmode (insn, CCNOmode) | |
8443 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8444 | "or{w}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8445 | [(set_attr "type" "alu") |
8446 | (set_attr "mode" "HI")]) | |
8447 | ||
e075ae69 RH |
8448 | (define_expand "iorqi3" |
8449 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
8450 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
8451 | (match_operand:QI 2 "general_operand" ""))) | |
8452 | (clobber (reg:CC 17))] | |
d9f32422 | 8453 | "TARGET_QIMODE_MATH" |
e075ae69 RH |
8454 | "ix86_expand_binary_operator (IOR, QImode, operands); DONE;") |
8455 | ||
8456 | ;; %%% Potential partial reg stall on alternative 2. What to do? | |
8457 | (define_insn "*iorqi_1" | |
7c6b971d | 8458 | [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r") |
e075ae69 | 8459 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") |
7c6b971d | 8460 | (match_operand:QI 2 "general_operand" "qmi,qi,ri"))) |
e075ae69 RH |
8461 | (clobber (reg:CC 17))] |
8462 | "ix86_binary_operator_ok (IOR, QImode, operands)" | |
8463 | "@ | |
0f40f9f7 ZW |
8464 | or{b}\t{%2, %0|%0, %2} |
8465 | or{b}\t{%2, %0|%0, %2} | |
8466 | or{l}\t{%k2, %k0|%k0, %k2}" | |
6ef67412 | 8467 | [(set_attr "type" "alu") |
a1b8572c JH |
8468 | (set_attr "mode" "QI,QI,SI")]) |
8469 | ||
8470 | (define_insn "*iorqi_1_slp" | |
8471 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m")) | |
8472 | (ior:QI (match_dup 0) | |
8473 | (match_operand:QI 1 "general_operand" "qmi,qi"))) | |
8474 | (clobber (reg:CC 17))] | |
2f41793e | 8475 | "! TARGET_PARTIAL_REG_STALL || optimize_size" |
0f40f9f7 | 8476 | "or{b}\t{%1, %0|%0, %1}" |
a1b8572c | 8477 | [(set_attr "type" "alu1") |
6ef67412 | 8478 | (set_attr "mode" "QI")]) |
e075ae69 RH |
8479 | |
8480 | (define_insn "*iorqi_2" | |
16189740 RH |
8481 | [(set (reg 17) |
8482 | (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") | |
8483 | (match_operand:QI 2 "general_operand" "qim,qi")) | |
8484 | (const_int 0))) | |
e075ae69 RH |
8485 | (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") |
8486 | (ior:QI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8487 | "ix86_match_ccmode (insn, CCNOmode) |
8488 | && ix86_binary_operator_ok (IOR, QImode, operands)" | |
0f40f9f7 | 8489 | "or{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8490 | [(set_attr "type" "alu") |
8491 | (set_attr "mode" "QI")]) | |
d90ffc8d | 8492 | |
a1b8572c JH |
8493 | (define_insn "*iorqi_2_slp" |
8494 | [(set (reg 17) | |
8495 | (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm") | |
8496 | (match_operand:QI 1 "general_operand" "qim,qi")) | |
8497 | (const_int 0))) | |
8498 | (set (strict_low_part (match_dup 0)) | |
8499 | (ior:QI (match_dup 0) (match_dup 1)))] | |
2f41793e JH |
8500 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) |
8501 | && ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 8502 | "or{b}\t{%1, %0|%0, %1}" |
a1b8572c JH |
8503 | [(set_attr "type" "alu1") |
8504 | (set_attr "mode" "QI")]) | |
8505 | ||
d90ffc8d JH |
8506 | (define_insn "*iorqi_3" |
8507 | [(set (reg 17) | |
8508 | (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0") | |
8509 | (match_operand:QI 2 "general_operand" "qim")) | |
8510 | (const_int 0))) | |
7e08e190 | 8511 | (clobber (match_scratch:QI 0 "=q"))] |
d90ffc8d JH |
8512 | "ix86_match_ccmode (insn, CCNOmode) |
8513 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8514 | "or{b}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8515 | [(set_attr "type" "alu") |
8516 | (set_attr "mode" "QI")]) | |
8517 | ||
2f41793e JH |
8518 | (define_insn "iorqi_ext_0" |
8519 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
8520 | (const_int 8) | |
8521 | (const_int 8)) | |
8522 | (ior:SI | |
8523 | (zero_extract:SI | |
8524 | (match_operand 1 "ext_register_operand" "0") | |
8525 | (const_int 8) | |
8526 | (const_int 8)) | |
8527 | (match_operand 2 "const_int_operand" "n"))) | |
8528 | (clobber (reg:CC 17))] | |
8529 | "(!TARGET_PARTIAL_REG_STALL || optimize_size)" | |
8530 | "or{b}\t{%2, %h0|%h0, %2}" | |
8531 | [(set_attr "type" "alu") | |
8532 | (set_attr "length_immediate" "1") | |
8533 | (set_attr "mode" "QI")]) | |
8534 | ||
8535 | (define_insn "*iorqi_ext_1" | |
8536 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
8537 | (const_int 8) | |
8538 | (const_int 8)) | |
8539 | (ior:SI | |
8540 | (zero_extract:SI | |
8541 | (match_operand 1 "ext_register_operand" "0") | |
8542 | (const_int 8) | |
8543 | (const_int 8)) | |
8544 | (zero_extend:SI | |
8545 | (match_operand:QI 2 "general_operand" "Qm")))) | |
8546 | (clobber (reg:CC 17))] | |
8547 | "!TARGET_64BIT | |
8548 | && (!TARGET_PARTIAL_REG_STALL || optimize_size)" | |
8549 | "or{b}\t{%2, %h0|%h0, %2}" | |
8550 | [(set_attr "type" "alu") | |
8551 | (set_attr "length_immediate" "0") | |
8552 | (set_attr "mode" "QI")]) | |
8553 | ||
8554 | (define_insn "*iorqi_ext_1_rex64" | |
8555 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
8556 | (const_int 8) | |
8557 | (const_int 8)) | |
8558 | (ior:SI | |
8559 | (zero_extract:SI | |
8560 | (match_operand 1 "ext_register_operand" "0") | |
8561 | (const_int 8) | |
8562 | (const_int 8)) | |
8563 | (zero_extend:SI | |
8564 | (match_operand 2 "ext_register_operand" "Q")))) | |
8565 | (clobber (reg:CC 17))] | |
8566 | "TARGET_64BIT | |
8567 | && (!TARGET_PARTIAL_REG_STALL || optimize_size)" | |
8568 | "or{b}\t{%2, %h0|%h0, %2}" | |
8569 | [(set_attr "type" "alu") | |
8570 | (set_attr "length_immediate" "0") | |
8571 | (set_attr "mode" "QI")]) | |
8572 | ||
8573 | (define_insn "*iorqi_ext_2" | |
8574 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
8575 | (const_int 8) | |
8576 | (const_int 8)) | |
8577 | (ior:SI | |
8578 | (zero_extract:SI (match_operand 1 "ext_register_operand" "0") | |
8579 | (const_int 8) | |
8580 | (const_int 8)) | |
8581 | (zero_extract:SI (match_operand 2 "ext_register_operand" "Q") | |
8582 | (const_int 8) | |
8583 | (const_int 8)))) | |
8584 | (clobber (reg:CC 17))] | |
8585 | "(!TARGET_PARTIAL_REG_STALL || optimize_size)" | |
8586 | "ior{b}\t{%h2, %h0|%h0, %h2}" | |
8587 | [(set_attr "type" "alu") | |
8588 | (set_attr "length_immediate" "0") | |
8589 | (set_attr "mode" "QI")]) | |
8590 | ||
8591 | (define_split | |
8592 | [(set (match_operand 0 "register_operand" "") | |
8593 | (ior (match_operand 1 "register_operand" "") | |
8594 | (match_operand 2 "const_int_operand" ""))) | |
8595 | (clobber (reg:CC 17))] | |
8596 | "reload_completed | |
8597 | && QI_REG_P (operands[0]) | |
8598 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) | |
8599 | && !(INTVAL (operands[2]) & ~(255 << 8)) | |
8600 | && GET_MODE (operands[0]) != QImode" | |
8601 | [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) | |
8602 | (ior:SI (zero_extract:SI (match_dup 1) | |
8603 | (const_int 8) (const_int 8)) | |
8604 | (match_dup 2))) | |
8605 | (clobber (reg:CC 17))])] | |
8606 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
8607 | operands[1] = gen_lowpart (SImode, operands[1]); | |
8608 | operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") | |
8609 | ||
8610 | ;; Since OR can be encoded with sign extended immediate, this is only | |
8611 | ;; profitable when 7th bit is set. | |
8612 | (define_split | |
8613 | [(set (match_operand 0 "register_operand" "") | |
8614 | (ior (match_operand 1 "general_operand" "") | |
8615 | (match_operand 2 "const_int_operand" ""))) | |
8616 | (clobber (reg:CC 17))] | |
8617 | "reload_completed | |
8618 | && ANY_QI_REG_P (operands[0]) | |
8619 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) | |
8620 | && !(INTVAL (operands[2]) & ~255) | |
8621 | && (INTVAL (operands[2]) & 128) | |
8622 | && GET_MODE (operands[0]) != QImode" | |
8623 | [(parallel [(set (strict_low_part (match_dup 0)) | |
8624 | (ior:QI (match_dup 1) | |
8625 | (match_dup 2))) | |
8626 | (clobber (reg:CC 17))])] | |
8627 | "operands[0] = gen_lowpart (QImode, operands[0]); | |
8628 | operands[1] = gen_lowpart (QImode, operands[1]); | |
8629 | operands[2] = gen_lowpart (QImode, operands[2]);") | |
e075ae69 RH |
8630 | \f |
8631 | ;; Logical XOR instructions | |
a269a03c | 8632 | |
e075ae69 RH |
8633 | ;; %%% This used to optimize known byte-wide and operations to memory. |
8634 | ;; If this is considered useful, it should be done with splitters. | |
57dbca5e | 8635 | |
9b70259d JH |
8636 | (define_expand "xordi3" |
8637 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8638 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
8639 | (match_operand:DI 2 "x86_64_general_operand" ""))) | |
8640 | (clobber (reg:CC 17))] | |
8641 | "TARGET_64BIT" | |
8642 | "ix86_expand_binary_operator (XOR, DImode, operands); DONE;") | |
8643 | ||
8644 | (define_insn "*xordi_1_rex64" | |
8645 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
8646 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
8647 | (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) | |
8648 | (clobber (reg:CC 17))] | |
8649 | "TARGET_64BIT | |
8650 | && ix86_binary_operator_ok (XOR, DImode, operands)" | |
8651 | "@ | |
0f40f9f7 ZW |
8652 | xor{q}\t{%2, %0|%0, %2} |
8653 | xor{q}\t{%2, %0|%0, %2}" | |
9b70259d JH |
8654 | [(set_attr "type" "alu") |
8655 | (set_attr "mode" "DI,DI")]) | |
8656 | ||
8657 | (define_insn "*xordi_2_rex64" | |
8658 | [(set (reg 17) | |
8659 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
8660 | (match_operand:DI 2 "x86_64_general_operand" "rem,re")) | |
8661 | (const_int 0))) | |
8662 | (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm") | |
8663 | (xor:DI (match_dup 1) (match_dup 2)))] | |
8664 | "TARGET_64BIT | |
8665 | && ix86_match_ccmode (insn, CCNOmode) | |
8666 | && ix86_binary_operator_ok (XOR, DImode, operands)" | |
8667 | "@ | |
0f40f9f7 ZW |
8668 | xor{q}\t{%2, %0|%0, %2} |
8669 | xor{q}\t{%2, %0|%0, %2}" | |
9b70259d JH |
8670 | [(set_attr "type" "alu") |
8671 | (set_attr "mode" "DI,DI")]) | |
8672 | ||
8673 | (define_insn "*xordi_3_rex64" | |
8674 | [(set (reg 17) | |
8675 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
8676 | (match_operand:DI 2 "x86_64_general_operand" "rem")) | |
8677 | (const_int 0))) | |
8678 | (clobber (match_scratch:DI 0 "=r"))] | |
8679 | "TARGET_64BIT | |
8680 | && ix86_match_ccmode (insn, CCNOmode) | |
8681 | && ix86_binary_operator_ok (XOR, DImode, operands)" | |
0f40f9f7 | 8682 | "xor{q}\t{%2, %0|%0, %2}" |
9b70259d JH |
8683 | [(set_attr "type" "alu") |
8684 | (set_attr "mode" "DI")]) | |
8685 | ||
e075ae69 RH |
8686 | (define_expand "xorsi3" |
8687 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
8688 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
8689 | (match_operand:SI 2 "general_operand" ""))) | |
8690 | (clobber (reg:CC 17))] | |
57dbca5e | 8691 | "" |
e075ae69 | 8692 | "ix86_expand_binary_operator (XOR, SImode, operands); DONE;") |
a269a03c | 8693 | |
e075ae69 RH |
8694 | (define_insn "*xorsi_1" |
8695 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") | |
8696 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
8697 | (match_operand:SI 2 "general_operand" "ri,rm"))) | |
8698 | (clobber (reg:CC 17))] | |
8699 | "ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8700 | "xor{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8701 | [(set_attr "type" "alu") |
8702 | (set_attr "mode" "SI")]) | |
e075ae69 | 8703 | |
9b70259d JH |
8704 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8705 | ;; Add speccase for immediates | |
8706 | (define_insn "*xorsi_1_zext" | |
8707 | [(set (match_operand:DI 0 "register_operand" "=r") | |
8708 | (zero_extend:DI | |
8709 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8710 | (match_operand:SI 2 "general_operand" "rim")))) | |
8711 | (clobber (reg:CC 17))] | |
8712 | "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8713 | "xor{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8714 | [(set_attr "type" "alu") |
8715 | (set_attr "mode" "SI")]) | |
8716 | ||
8717 | (define_insn "*xorsi_1_zext_imm" | |
8718 | [(set (match_operand:DI 0 "register_operand" "=r") | |
8719 | (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) | |
8720 | (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) | |
8721 | (clobber (reg:CC 17))] | |
8722 | "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8723 | "xor{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8724 | [(set_attr "type" "alu") |
8725 | (set_attr "mode" "SI")]) | |
8726 | ||
e075ae69 | 8727 | (define_insn "*xorsi_2" |
16189740 RH |
8728 | [(set (reg 17) |
8729 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
8730 | (match_operand:SI 2 "general_operand" "rim,ri")) | |
8731 | (const_int 0))) | |
e075ae69 RH |
8732 | (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm") |
8733 | (xor:SI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8734 | "ix86_match_ccmode (insn, CCNOmode) |
8735 | && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8736 | "xor{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8737 | [(set_attr "type" "alu") |
8738 | (set_attr "mode" "SI")]) | |
e075ae69 | 8739 | |
9b70259d JH |
8740 | ;; See comment for addsi_1_zext why we do use nonimmediate_operand |
8741 | ;; ??? Special case for immediate operand is missing - it is tricky. | |
8742 | (define_insn "*xorsi_2_zext" | |
8743 | [(set (reg 17) | |
8744 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8745 | (match_operand:SI 2 "general_operand" "rim")) | |
8746 | (const_int 0))) | |
8747 | (set (match_operand:DI 0 "register_operand" "=r") | |
8748 | (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))] | |
8749 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8750 | && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8751 | "xor{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8752 | [(set_attr "type" "alu") |
8753 | (set_attr "mode" "SI")]) | |
8754 | ||
8755 | (define_insn "*xorsi_2_zext_imm" | |
8756 | [(set (reg 17) | |
8757 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8758 | (match_operand 2 "x86_64_zext_immediate_operand" "Z")) | |
8759 | (const_int 0))) | |
8760 | (set (match_operand:DI 0 "register_operand" "=r") | |
8761 | (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] | |
8762 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
8763 | && ix86_binary_operator_ok (XOR, SImode, operands)" | |
0f40f9f7 | 8764 | "xor{l}\t{%2, %k0|%k0, %2}" |
9b70259d JH |
8765 | [(set_attr "type" "alu") |
8766 | (set_attr "mode" "SI")]) | |
8767 | ||
d90ffc8d JH |
8768 | (define_insn "*xorsi_3" |
8769 | [(set (reg 17) | |
8770 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") | |
8771 | (match_operand:SI 2 "general_operand" "rim")) | |
8772 | (const_int 0))) | |
8773 | (clobber (match_scratch:SI 0 "=r"))] | |
8774 | "ix86_match_ccmode (insn, CCNOmode) | |
8775 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8776 | "xor{l}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8777 | [(set_attr "type" "alu") |
8778 | (set_attr "mode" "SI")]) | |
8779 | ||
e075ae69 RH |
8780 | (define_expand "xorhi3" |
8781 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
8782 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
8783 | (match_operand:HI 2 "general_operand" ""))) | |
8784 | (clobber (reg:CC 17))] | |
d9f32422 | 8785 | "TARGET_HIMODE_MATH" |
e075ae69 RH |
8786 | "ix86_expand_binary_operator (XOR, HImode, operands); DONE;") |
8787 | ||
8788 | (define_insn "*xorhi_1" | |
8789 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m") | |
8790 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
8791 | (match_operand:HI 2 "general_operand" "rmi,ri"))) | |
8792 | (clobber (reg:CC 17))] | |
8793 | "ix86_binary_operator_ok (XOR, HImode, operands)" | |
0f40f9f7 | 8794 | "xor{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8795 | [(set_attr "type" "alu") |
8796 | (set_attr "mode" "HI")]) | |
57dbca5e | 8797 | |
e075ae69 | 8798 | (define_insn "*xorhi_2" |
16189740 RH |
8799 | [(set (reg 17) |
8800 | (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
8801 | (match_operand:HI 2 "general_operand" "rim,ri")) | |
8802 | (const_int 0))) | |
e075ae69 RH |
8803 | (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm") |
8804 | (xor:HI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8805 | "ix86_match_ccmode (insn, CCNOmode) |
8806 | && ix86_binary_operator_ok (XOR, HImode, operands)" | |
0f40f9f7 | 8807 | "xor{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8808 | [(set_attr "type" "alu") |
8809 | (set_attr "mode" "HI")]) | |
e075ae69 | 8810 | |
d90ffc8d JH |
8811 | (define_insn "*xorhi_3" |
8812 | [(set (reg 17) | |
8813 | (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0") | |
8814 | (match_operand:HI 2 "general_operand" "rim")) | |
8815 | (const_int 0))) | |
8816 | (clobber (match_scratch:HI 0 "=r"))] | |
8817 | "ix86_match_ccmode (insn, CCNOmode) | |
8818 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8819 | "xor{w}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8820 | [(set_attr "type" "alu") |
8821 | (set_attr "mode" "HI")]) | |
8822 | ||
e075ae69 RH |
8823 | (define_expand "xorqi3" |
8824 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
8825 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
8826 | (match_operand:QI 2 "general_operand" ""))) | |
8827 | (clobber (reg:CC 17))] | |
d9f32422 | 8828 | "TARGET_QIMODE_MATH" |
e075ae69 RH |
8829 | "ix86_expand_binary_operator (XOR, QImode, operands); DONE;") |
8830 | ||
8831 | ;; %%% Potential partial reg stall on alternative 2. What to do? | |
8832 | (define_insn "*xorqi_1" | |
7c6b971d | 8833 | [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r") |
e075ae69 | 8834 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") |
7c6b971d | 8835 | (match_operand:QI 2 "general_operand" "qmi,qi,ri"))) |
e075ae69 RH |
8836 | (clobber (reg:CC 17))] |
8837 | "ix86_binary_operator_ok (XOR, QImode, operands)" | |
8838 | "@ | |
0f40f9f7 ZW |
8839 | xor{b}\t{%2, %0|%0, %2} |
8840 | xor{b}\t{%2, %0|%0, %2} | |
8841 | xor{l}\t{%k2, %k0|%k0, %k2}" | |
6ef67412 JH |
8842 | [(set_attr "type" "alu") |
8843 | (set_attr "mode" "QI,QI,SI")]) | |
8844 | ||
b6bb1d56 JH |
8845 | (define_insn "*xorqi_1_slp" |
8846 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) | |
8847 | (xor:QI (match_dup 0) | |
8848 | (match_operand:QI 1 "general_operand" "qi,qmi"))) | |
8849 | (clobber (reg:CC 17))] | |
8850 | "! TARGET_PARTIAL_REG_STALL || optimize_size" | |
8851 | "xor{b}\t{%1, %0|%0, %1}" | |
8852 | [(set_attr "type" "alu1") | |
8853 | (set_attr "mode" "QI")]) | |
8854 | ||
2f41793e JH |
8855 | (define_insn "xorqi_ext_0" |
8856 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
8857 | (const_int 8) | |
8858 | (const_int 8)) | |
8859 | (xor:SI | |
8860 | (zero_extract:SI | |
8861 | (match_operand 1 "ext_register_operand" "0") | |
8862 | (const_int 8) | |
8863 | (const_int 8)) | |
8864 | (match_operand 2 "const_int_operand" "n"))) | |
8865 | (clobber (reg:CC 17))] | |
8866 | "(!TARGET_PARTIAL_REG_STALL || optimize_size)" | |
8867 | "xor{b}\t{%2, %h0|%h0, %2}" | |
8868 | [(set_attr "type" "alu") | |
8869 | (set_attr "length_immediate" "1") | |
8870 | (set_attr "mode" "QI")]) | |
8871 | ||
a4414093 | 8872 | (define_insn "*xorqi_ext_1" |
2f41793e JH |
8873 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
8874 | (const_int 8) | |
8875 | (const_int 8)) | |
8876 | (xor:SI | |
8877 | (zero_extract:SI | |
8878 | (match_operand 1 "ext_register_operand" "0") | |
8879 | (const_int 8) | |
8880 | (const_int 8)) | |
8881 | (zero_extend:SI | |
8882 | (match_operand:QI 2 "general_operand" "Qm")))) | |
8883 | (clobber (reg:CC 17))] | |
8884 | "!TARGET_64BIT | |
8885 | && (!TARGET_PARTIAL_REG_STALL || optimize_size)" | |
8886 | "xor{b}\t{%2, %h0|%h0, %2}" | |
8887 | [(set_attr "type" "alu") | |
8888 | (set_attr "length_immediate" "0") | |
8889 | (set_attr "mode" "QI")]) | |
8890 | ||
8891 | (define_insn "*xorqi_ext_1_rex64" | |
8892 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
8893 | (const_int 8) | |
8894 | (const_int 8)) | |
8895 | (xor:SI | |
8896 | (zero_extract:SI | |
8897 | (match_operand 1 "ext_register_operand" "0") | |
8898 | (const_int 8) | |
8899 | (const_int 8)) | |
8900 | (zero_extend:SI | |
8901 | (match_operand 2 "ext_register_operand" "Q")))) | |
8902 | (clobber (reg:CC 17))] | |
8903 | "TARGET_64BIT | |
8904 | && (!TARGET_PARTIAL_REG_STALL || optimize_size)" | |
8905 | "xor{b}\t{%2, %h0|%h0, %2}" | |
8906 | [(set_attr "type" "alu") | |
8907 | (set_attr "length_immediate" "0") | |
8908 | (set_attr "mode" "QI")]) | |
8909 | ||
8910 | (define_insn "*xorqi_ext_2" | |
d2836273 | 8911 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") |
6ef67412 JH |
8912 | (const_int 8) |
8913 | (const_int 8)) | |
8914 | (xor:SI | |
8915 | (zero_extract:SI (match_operand 1 "ext_register_operand" "0") | |
8916 | (const_int 8) | |
8917 | (const_int 8)) | |
d2836273 | 8918 | (zero_extract:SI (match_operand 2 "ext_register_operand" "Q") |
6ef67412 JH |
8919 | (const_int 8) |
8920 | (const_int 8)))) | |
8921 | (clobber (reg:CC 17))] | |
2f41793e | 8922 | "(!TARGET_PARTIAL_REG_STALL || optimize_size)" |
0f40f9f7 | 8923 | "xor{b}\t{%h2, %h0|%h0, %h2}" |
6ef67412 JH |
8924 | [(set_attr "type" "alu") |
8925 | (set_attr "length_immediate" "0") | |
8926 | (set_attr "mode" "QI")]) | |
e075ae69 | 8927 | |
7abd4e00 | 8928 | (define_insn "*xorqi_cc_1" |
16189740 RH |
8929 | [(set (reg 17) |
8930 | (compare | |
e075ae69 RH |
8931 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") |
8932 | (match_operand:QI 2 "general_operand" "qim,qi")) | |
8933 | (const_int 0))) | |
8934 | (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") | |
8935 | (xor:QI (match_dup 1) (match_dup 2)))] | |
16189740 RH |
8936 | "ix86_match_ccmode (insn, CCNOmode) |
8937 | && ix86_binary_operator_ok (XOR, QImode, operands)" | |
0f40f9f7 | 8938 | "xor{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
8939 | [(set_attr "type" "alu") |
8940 | (set_attr "mode" "QI")]) | |
e075ae69 | 8941 | |
b6bb1d56 JH |
8942 | (define_insn "*xorqi_2_slp" |
8943 | [(set (reg 17) | |
8944 | (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm") | |
8945 | (match_operand:QI 1 "general_operand" "qim,qi")) | |
8946 | (const_int 0))) | |
8947 | (set (strict_low_part (match_dup 0)) | |
8948 | (xor:QI (match_dup 0) (match_dup 1)))] | |
8949 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
8950 | && ix86_match_ccmode (insn, CCNOmode)" | |
8951 | "xor{b}\t{%1, %0|%0, %1}" | |
8952 | [(set_attr "type" "alu1") | |
8953 | (set_attr "mode" "QI")]) | |
8954 | ||
d90ffc8d JH |
8955 | (define_insn "*xorqi_cc_2" |
8956 | [(set (reg 17) | |
8957 | (compare | |
8958 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0") | |
8959 | (match_operand:QI 2 "general_operand" "qim")) | |
8960 | (const_int 0))) | |
7e08e190 | 8961 | (clobber (match_scratch:QI 0 "=q"))] |
d90ffc8d JH |
8962 | "ix86_match_ccmode (insn, CCNOmode) |
8963 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 8964 | "xor{b}\t{%2, %0|%0, %2}" |
d90ffc8d JH |
8965 | [(set_attr "type" "alu") |
8966 | (set_attr "mode" "QI")]) | |
8967 | ||
9076b9c1 JH |
8968 | (define_insn "*xorqi_cc_ext_1" |
8969 | [(set (reg 17) | |
8970 | (compare | |
e075ae69 RH |
8971 | (xor:SI |
8972 | (zero_extract:SI | |
8973 | (match_operand 1 "ext_register_operand" "0") | |
8974 | (const_int 8) | |
8975 | (const_int 8)) | |
8976 | (match_operand:QI 2 "general_operand" "qmn")) | |
8977 | (const_int 0))) | |
8978 | (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q") | |
8979 | (const_int 8) | |
8980 | (const_int 8)) | |
8981 | (xor:SI | |
8982 | (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) | |
8983 | (match_dup 2)))] | |
d2836273 | 8984 | "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" |
0f40f9f7 | 8985 | "xor{b}\t{%2, %h0|%h0, %2}" |
d2836273 JH |
8986 | [(set_attr "type" "alu") |
8987 | (set_attr "mode" "QI")]) | |
8988 | ||
8989 | (define_insn "*xorqi_cc_ext_1_rex64" | |
8990 | [(set (reg 17) | |
8991 | (compare | |
8992 | (xor:SI | |
8993 | (zero_extract:SI | |
8994 | (match_operand 1 "ext_register_operand" "0") | |
8995 | (const_int 8) | |
8996 | (const_int 8)) | |
8997 | (match_operand:QI 2 "nonmemory_operand" "Qn")) | |
8998 | (const_int 0))) | |
8999 | (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") | |
9000 | (const_int 8) | |
9001 | (const_int 8)) | |
9002 | (xor:SI | |
9003 | (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) | |
9004 | (match_dup 2)))] | |
9005 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
0f40f9f7 | 9006 | "xor{b}\t{%2, %h0|%h0, %2}" |
6ef67412 JH |
9007 | [(set_attr "type" "alu") |
9008 | (set_attr "mode" "QI")]) | |
9076b9c1 JH |
9009 | |
9010 | (define_expand "xorqi_cc_ext_1" | |
9011 | [(parallel [ | |
9012 | (set (reg:CCNO 17) | |
9013 | (compare:CCNO | |
9014 | (xor:SI | |
9015 | (zero_extract:SI | |
9016 | (match_operand 1 "ext_register_operand" "") | |
9017 | (const_int 8) | |
9018 | (const_int 8)) | |
9019 | (match_operand:QI 2 "general_operand" "")) | |
9020 | (const_int 0))) | |
9021 | (set (zero_extract:SI (match_operand 0 "ext_register_operand" "") | |
9022 | (const_int 8) | |
9023 | (const_int 8)) | |
9024 | (xor:SI | |
9025 | (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) | |
9026 | (match_dup 2)))])] | |
9027 | "" | |
9028 | "") | |
2f41793e JH |
9029 | |
9030 | (define_split | |
9031 | [(set (match_operand 0 "register_operand" "") | |
9032 | (xor (match_operand 1 "register_operand" "") | |
9033 | (match_operand 2 "const_int_operand" ""))) | |
9034 | (clobber (reg:CC 17))] | |
9035 | "reload_completed | |
9036 | && QI_REG_P (operands[0]) | |
9037 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) | |
9038 | && !(INTVAL (operands[2]) & ~(255 << 8)) | |
9039 | && GET_MODE (operands[0]) != QImode" | |
9040 | [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) | |
9041 | (xor:SI (zero_extract:SI (match_dup 1) | |
9042 | (const_int 8) (const_int 8)) | |
9043 | (match_dup 2))) | |
9044 | (clobber (reg:CC 17))])] | |
9045 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
9046 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9047 | operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") | |
9048 | ||
9049 | ;; Since XOR can be encoded with sign extended immediate, this is only | |
9050 | ;; profitable when 7th bit is set. | |
9051 | (define_split | |
9052 | [(set (match_operand 0 "register_operand" "") | |
9053 | (xor (match_operand 1 "general_operand" "") | |
9054 | (match_operand 2 "const_int_operand" ""))) | |
9055 | (clobber (reg:CC 17))] | |
9056 | "reload_completed | |
9057 | && ANY_QI_REG_P (operands[0]) | |
9058 | && (!TARGET_PARTIAL_REG_STALL || optimize_size) | |
9059 | && !(INTVAL (operands[2]) & ~255) | |
9060 | && (INTVAL (operands[2]) & 128) | |
9061 | && GET_MODE (operands[0]) != QImode" | |
9062 | [(parallel [(set (strict_low_part (match_dup 0)) | |
9063 | (xor:QI (match_dup 1) | |
9064 | (match_dup 2))) | |
9065 | (clobber (reg:CC 17))])] | |
9066 | "operands[0] = gen_lowpart (QImode, operands[0]); | |
9067 | operands[1] = gen_lowpart (QImode, operands[1]); | |
9068 | operands[2] = gen_lowpart (QImode, operands[2]);") | |
e075ae69 RH |
9069 | \f |
9070 | ;; Negation instructions | |
57dbca5e | 9071 | |
06a964de JH |
9072 | (define_expand "negdi2" |
9073 | [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
2756c3d8 | 9074 | (neg:DI (match_operand:DI 1 "nonimmediate_operand" ""))) |
06a964de JH |
9075 | (clobber (reg:CC 17))])] |
9076 | "" | |
9077 | "ix86_expand_unary_operator (NEG, DImode, operands); DONE;") | |
9078 | ||
9079 | (define_insn "*negdi2_1" | |
e075ae69 RH |
9080 | [(set (match_operand:DI 0 "nonimmediate_operand" "=ro") |
9081 | (neg:DI (match_operand:DI 1 "general_operand" "0"))) | |
9082 | (clobber (reg:CC 17))] | |
d2836273 JH |
9083 | "!TARGET_64BIT |
9084 | && ix86_unary_operator_ok (NEG, DImode, operands)" | |
e075ae69 | 9085 | "#") |
886c62d1 | 9086 | |
e075ae69 RH |
9087 | (define_split |
9088 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
9089 | (neg:DI (match_operand:DI 1 "general_operand" ""))) | |
9090 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9091 | "!TARGET_64BIT && reload_completed" |
e075ae69 | 9092 | [(parallel |
16189740 RH |
9093 | [(set (reg:CCZ 17) |
9094 | (compare:CCZ (neg:SI (match_dup 2)) (const_int 0))) | |
e075ae69 RH |
9095 | (set (match_dup 0) (neg:SI (match_dup 2)))]) |
9096 | (parallel | |
9097 | [(set (match_dup 1) | |
7e08e190 | 9098 | (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) |
9dcbdc7e JH |
9099 | (match_dup 3)) |
9100 | (const_int 0))) | |
e075ae69 RH |
9101 | (clobber (reg:CC 17))]) |
9102 | (parallel | |
9103 | [(set (match_dup 1) | |
9104 | (neg:SI (match_dup 1))) | |
9105 | (clobber (reg:CC 17))])] | |
9106 | "split_di (operands+1, 1, operands+2, operands+3); | |
9107 | split_di (operands+0, 1, operands+0, operands+1);") | |
886c62d1 | 9108 | |
9b70259d JH |
9109 | (define_insn "*negdi2_1_rex64" |
9110 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
9111 | (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))) | |
9112 | (clobber (reg:CC 17))] | |
9113 | "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)" | |
0f40f9f7 | 9114 | "neg{q}\t%0" |
9b70259d JH |
9115 | [(set_attr "type" "negnot") |
9116 | (set_attr "mode" "DI")]) | |
9117 | ||
9118 | ;; The problem with neg is that it does not perform (compare x 0), | |
9119 | ;; it really performs (compare 0 x), which leaves us with the zero | |
9120 | ;; flag being the only useful item. | |
9121 | ||
9122 | (define_insn "*negdi2_cmpz_rex64" | |
9123 | [(set (reg:CCZ 17) | |
9124 | (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")) | |
9125 | (const_int 0))) | |
9126 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
9127 | (neg:DI (match_dup 1)))] | |
9128 | "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)" | |
0f40f9f7 | 9129 | "neg{q}\t%0" |
9b70259d JH |
9130 | [(set_attr "type" "negnot") |
9131 | (set_attr "mode" "DI")]) | |
9132 | ||
9133 | ||
06a964de JH |
9134 | (define_expand "negsi2" |
9135 | [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
2756c3d8 | 9136 | (neg:SI (match_operand:SI 1 "nonimmediate_operand" ""))) |
06a964de JH |
9137 | (clobber (reg:CC 17))])] |
9138 | "" | |
9139 | "ix86_expand_unary_operator (NEG, SImode, operands); DONE;") | |
9140 | ||
9141 | (define_insn "*negsi2_1" | |
2ae0f82c | 9142 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
e075ae69 RH |
9143 | (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))) |
9144 | (clobber (reg:CC 17))] | |
06a964de | 9145 | "ix86_unary_operator_ok (NEG, SImode, operands)" |
0f40f9f7 | 9146 | "neg{l}\t%0" |
6ef67412 JH |
9147 | [(set_attr "type" "negnot") |
9148 | (set_attr "mode" "SI")]) | |
e075ae69 | 9149 | |
9b70259d JH |
9150 | ;; Combine is quite creative about this pattern. |
9151 | (define_insn "*negsi2_1_zext" | |
9152 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9153 | (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
9154 | (const_int 32))) | |
9155 | (const_int 32))) | |
9156 | (clobber (reg:CC 17))] | |
9157 | "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)" | |
0f40f9f7 | 9158 | "neg{l}\t%k0" |
9b70259d JH |
9159 | [(set_attr "type" "negnot") |
9160 | (set_attr "mode" "SI")]) | |
9161 | ||
16189740 RH |
9162 | ;; The problem with neg is that it does not perform (compare x 0), |
9163 | ;; it really performs (compare 0 x), which leaves us with the zero | |
9164 | ;; flag being the only useful item. | |
e075ae69 | 9165 | |
16189740 RH |
9166 | (define_insn "*negsi2_cmpz" |
9167 | [(set (reg:CCZ 17) | |
9168 | (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")) | |
9169 | (const_int 0))) | |
e075ae69 RH |
9170 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
9171 | (neg:SI (match_dup 1)))] | |
06a964de | 9172 | "ix86_unary_operator_ok (NEG, SImode, operands)" |
0f40f9f7 | 9173 | "neg{l}\t%0" |
6ef67412 JH |
9174 | [(set_attr "type" "negnot") |
9175 | (set_attr "mode" "SI")]) | |
886c62d1 | 9176 | |
9b70259d JH |
9177 | (define_insn "*negsi2_cmpz_zext" |
9178 | [(set (reg:CCZ 17) | |
9179 | (compare:CCZ (lshiftrt:DI | |
9180 | (neg:DI (ashift:DI | |
9181 | (match_operand:DI 1 "register_operand" "0") | |
9182 | (const_int 32))) | |
9183 | (const_int 32)) | |
9184 | (const_int 0))) | |
9185 | (set (match_operand:DI 0 "register_operand" "=r") | |
9186 | (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1) | |
9187 | (const_int 32))) | |
9188 | (const_int 32)))] | |
9189 | "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)" | |
0f40f9f7 | 9190 | "neg{l}\t%k0" |
9b70259d JH |
9191 | [(set_attr "type" "negnot") |
9192 | (set_attr "mode" "SI")]) | |
9193 | ||
06a964de JH |
9194 | (define_expand "neghi2" |
9195 | [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2756c3d8 | 9196 | (neg:HI (match_operand:HI 1 "nonimmediate_operand" ""))) |
06a964de | 9197 | (clobber (reg:CC 17))])] |
d9f32422 | 9198 | "TARGET_HIMODE_MATH" |
06a964de JH |
9199 | "ix86_expand_unary_operator (NEG, HImode, operands); DONE;") |
9200 | ||
9201 | (define_insn "*neghi2_1" | |
2ae0f82c | 9202 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
e075ae69 RH |
9203 | (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))) |
9204 | (clobber (reg:CC 17))] | |
06a964de | 9205 | "ix86_unary_operator_ok (NEG, HImode, operands)" |
0f40f9f7 | 9206 | "neg{w}\t%0" |
6ef67412 JH |
9207 | [(set_attr "type" "negnot") |
9208 | (set_attr "mode" "HI")]) | |
e075ae69 | 9209 | |
16189740 RH |
9210 | (define_insn "*neghi2_cmpz" |
9211 | [(set (reg:CCZ 17) | |
9212 | (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")) | |
9213 | (const_int 0))) | |
e075ae69 RH |
9214 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
9215 | (neg:HI (match_dup 1)))] | |
06a964de | 9216 | "ix86_unary_operator_ok (NEG, HImode, operands)" |
0f40f9f7 | 9217 | "neg{w}\t%0" |
6ef67412 JH |
9218 | [(set_attr "type" "negnot") |
9219 | (set_attr "mode" "HI")]) | |
886c62d1 | 9220 | |
06a964de JH |
9221 | (define_expand "negqi2" |
9222 | [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2756c3d8 | 9223 | (neg:QI (match_operand:QI 1 "nonimmediate_operand" ""))) |
06a964de | 9224 | (clobber (reg:CC 17))])] |
d9f32422 | 9225 | "TARGET_QIMODE_MATH" |
06a964de JH |
9226 | "ix86_expand_unary_operator (NEG, QImode, operands); DONE;") |
9227 | ||
9228 | (define_insn "*negqi2_1" | |
2ae0f82c | 9229 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
e075ae69 RH |
9230 | (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))) |
9231 | (clobber (reg:CC 17))] | |
06a964de | 9232 | "ix86_unary_operator_ok (NEG, QImode, operands)" |
0f40f9f7 | 9233 | "neg{b}\t%0" |
6ef67412 JH |
9234 | [(set_attr "type" "negnot") |
9235 | (set_attr "mode" "QI")]) | |
e075ae69 | 9236 | |
16189740 RH |
9237 | (define_insn "*negqi2_cmpz" |
9238 | [(set (reg:CCZ 17) | |
9239 | (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")) | |
9240 | (const_int 0))) | |
e075ae69 RH |
9241 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
9242 | (neg:QI (match_dup 1)))] | |
06a964de | 9243 | "ix86_unary_operator_ok (NEG, QImode, operands)" |
0f40f9f7 | 9244 | "neg{b}\t%0" |
6ef67412 JH |
9245 | [(set_attr "type" "negnot") |
9246 | (set_attr "mode" "QI")]) | |
886c62d1 | 9247 | |
06a964de | 9248 | ;; Changing of sign for FP values is doable using integer unit too. |
1ce485ec | 9249 | |
06a964de JH |
9250 | (define_expand "negsf2" |
9251 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9252 | (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) |
06a964de JH |
9253 | (clobber (reg:CC 17))])] |
9254 | "TARGET_80387" | |
b3298882 JH |
9255 | "if (TARGET_SSE) |
9256 | { | |
9257 | /* In case operand is in memory, we will not use SSE. */ | |
9258 | if (memory_operand (operands[0], VOIDmode) | |
9259 | && rtx_equal_p (operands[0], operands[1])) | |
9260 | emit_insn (gen_negsf2_memory (operands[0], operands[1])); | |
9261 | else | |
9262 | { | |
9263 | /* Using SSE is tricky, since we need bitwise negation of -0 | |
9264 | in register. */ | |
9265 | rtx reg = gen_reg_rtx (SFmode); | |
141e454b JH |
9266 | rtx dest = operands[0]; |
9267 | ||
9268 | operands[1] = force_reg (SFmode, operands[1]); | |
9269 | operands[0] = force_reg (SFmode, operands[0]); | |
b3298882 JH |
9270 | emit_move_insn (reg, |
9271 | gen_lowpart (SFmode, | |
d8bf17f9 | 9272 | gen_int_mode (0x80000000, SImode))); |
b3298882 | 9273 | emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg)); |
141e454b JH |
9274 | if (dest != operands[0]) |
9275 | emit_move_insn (dest, operands[0]); | |
b3298882 JH |
9276 | } |
9277 | DONE; | |
9278 | } | |
9279 | ix86_expand_unary_operator (NEG, SFmode, operands); DONE;") | |
9280 | ||
9281 | (define_insn "negsf2_memory" | |
9282 | [(set (match_operand:SF 0 "memory_operand" "=m") | |
9283 | (neg:SF (match_operand:SF 1 "memory_operand" "0"))) | |
9284 | (clobber (reg:CC 17))] | |
9285 | "ix86_unary_operator_ok (NEG, SFmode, operands)" | |
9286 | "#") | |
9287 | ||
9288 | (define_insn "negsf2_ifs" | |
141e454b | 9289 | [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf") |
b3298882 | 9290 | (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0"))) |
141e454b | 9291 | (use (match_operand:SF 2 "nonmemory_operand" "x,0#x,*g#x,*g#x")) |
b3298882 | 9292 | (clobber (reg:CC 17))] |
141e454b JH |
9293 | "TARGET_SSE |
9294 | && (reload_in_progress || reload_completed | |
9295 | || (register_operand (operands[0], VOIDmode) | |
9296 | && register_operand (operands[1], VOIDmode)))" | |
b3298882 JH |
9297 | "#") |
9298 | ||
9299 | (define_split | |
9300 | [(set (match_operand:SF 0 "memory_operand" "") | |
9301 | (neg:SF (match_operand:SF 1 "memory_operand" ""))) | |
9302 | (use (match_operand:SF 2 "" "")) | |
9303 | (clobber (reg:CC 17))] | |
9304 | "" | |
9305 | [(parallel [(set (match_dup 0) | |
9306 | (neg:SF (match_dup 1))) | |
9307 | (clobber (reg:CC 17))])]) | |
9308 | ||
9309 | (define_split | |
9310 | [(set (match_operand:SF 0 "register_operand" "") | |
9311 | (neg:SF (match_operand:SF 1 "register_operand" ""))) | |
9312 | (use (match_operand:SF 2 "" "")) | |
9313 | (clobber (reg:CC 17))] | |
9314 | "reload_completed && !SSE_REG_P (operands[0])" | |
9315 | [(parallel [(set (match_dup 0) | |
9316 | (neg:SF (match_dup 1))) | |
9317 | (clobber (reg:CC 17))])]) | |
9318 | ||
9319 | (define_split | |
9320 | [(set (match_operand:SF 0 "register_operand" "") | |
9321 | (neg:SF (match_operand:SF 1 "register_operand" ""))) | |
9322 | (use (match_operand:SF 2 "register_operand" "")) | |
9323 | (clobber (reg:CC 17))] | |
9324 | "reload_completed && SSE_REG_P (operands[0])" | |
9325 | [(set (subreg:TI (match_dup 0) 0) | |
9326 | (xor:TI (subreg:TI (match_dup 1) 0) | |
9327 | (subreg:TI (match_dup 2) 0)))] | |
b3298882 JH |
9328 | { |
9329 | if (operands_match_p (operands[0], operands[2])) | |
9330 | { | |
9331 | rtx tmp; | |
9332 | tmp = operands[1]; | |
9333 | operands[1] = operands[2]; | |
9334 | operands[2] = tmp; | |
9335 | } | |
0f40f9f7 | 9336 | }) |
b3298882 | 9337 | |
06a964de | 9338 | |
e20440c1 JH |
9339 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9340 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9341 | ;; to itself. | |
06a964de | 9342 | (define_insn "*negsf2_if" |
e20440c1 JH |
9343 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") |
9344 | (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 9345 | (clobber (reg:CC 17))] |
b3298882 JH |
9346 | "TARGET_80387 && !TARGET_SSE |
9347 | && ix86_unary_operator_ok (NEG, SFmode, operands)" | |
1ce485ec JH |
9348 | "#") |
9349 | ||
9350 | (define_split | |
c3c637e3 | 9351 | [(set (match_operand:SF 0 "fp_register_operand" "") |
1ce485ec JH |
9352 | (neg:SF (match_operand:SF 1 "register_operand" ""))) |
9353 | (clobber (reg:CC 17))] | |
c3c637e3 | 9354 | "TARGET_80387 && reload_completed" |
1ce485ec JH |
9355 | [(set (match_dup 0) |
9356 | (neg:SF (match_dup 1)))] | |
9357 | "") | |
9358 | ||
9359 | (define_split | |
c3c637e3 | 9360 | [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "") |
1ce485ec JH |
9361 | (neg:SF (match_operand:SF 1 "register_operand" ""))) |
9362 | (clobber (reg:CC 17))] | |
c3c637e3 | 9363 | "TARGET_80387 && reload_completed" |
1ce485ec JH |
9364 | [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) |
9365 | (clobber (reg:CC 17))])] | |
d8bf17f9 | 9366 | "operands[1] = gen_int_mode (0x80000000, SImode); |
1ce485ec JH |
9367 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") |
9368 | ||
9369 | (define_split | |
9370 | [(set (match_operand 0 "memory_operand" "") | |
9371 | (neg (match_operand 1 "memory_operand" ""))) | |
9372 | (clobber (reg:CC 17))] | |
9373 | "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" | |
9374 | [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
9375 | (clobber (reg:CC 17))])] | |
1ce485ec JH |
9376 | { |
9377 | int size = GET_MODE_SIZE (GET_MODE (operands[1])); | |
9378 | ||
b3298882 JH |
9379 | /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */ |
9380 | if (size >= 12) | |
1ce485ec | 9381 | size = 10; |
b72f00af | 9382 | operands[0] = adjust_address (operands[0], QImode, size - 1); |
d8bf17f9 | 9383 | operands[1] = gen_int_mode (0x80, QImode); |
0f40f9f7 | 9384 | }) |
1ce485ec | 9385 | |
06a964de JH |
9386 | (define_expand "negdf2" |
9387 | [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9388 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) |
06a964de JH |
9389 | (clobber (reg:CC 17))])] |
9390 | "TARGET_80387" | |
141e454b | 9391 | "if (TARGET_SSE2) |
b3298882 JH |
9392 | { |
9393 | /* In case operand is in memory, we will not use SSE. */ | |
9394 | if (memory_operand (operands[0], VOIDmode) | |
9395 | && rtx_equal_p (operands[0], operands[1])) | |
9396 | emit_insn (gen_negdf2_memory (operands[0], operands[1])); | |
9397 | else | |
9398 | { | |
9399 | /* Using SSE is tricky, since we need bitwise negation of -0 | |
9400 | in register. */ | |
9401 | rtx reg = gen_reg_rtx (DFmode); | |
9402 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
d8bf17f9 | 9403 | rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode); |
b3298882 JH |
9404 | #else |
9405 | rtx imm = immed_double_const (0, 0x80000000, DImode); | |
9406 | #endif | |
141e454b JH |
9407 | rtx dest = operands[0]; |
9408 | ||
9409 | operands[1] = force_reg (DFmode, operands[1]); | |
9410 | operands[0] = force_reg (DFmode, operands[0]); | |
b3298882 JH |
9411 | emit_move_insn (reg, gen_lowpart (DFmode, imm)); |
9412 | emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg)); | |
141e454b JH |
9413 | if (dest != operands[0]) |
9414 | emit_move_insn (dest, operands[0]); | |
b3298882 JH |
9415 | } |
9416 | DONE; | |
9417 | } | |
9418 | ix86_expand_unary_operator (NEG, DFmode, operands); DONE;") | |
9419 | ||
9420 | (define_insn "negdf2_memory" | |
9421 | [(set (match_operand:DF 0 "memory_operand" "=m") | |
9422 | (neg:DF (match_operand:DF 1 "memory_operand" "0"))) | |
9423 | (clobber (reg:CC 17))] | |
9424 | "ix86_unary_operator_ok (NEG, DFmode, operands)" | |
9425 | "#") | |
9426 | ||
9427 | (define_insn "negdf2_ifs" | |
141e454b JH |
9428 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf") |
9429 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0"))) | |
9430 | (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y")) | |
b3298882 | 9431 | (clobber (reg:CC 17))] |
1b0c37d7 | 9432 | "!TARGET_64BIT && TARGET_SSE2 |
141e454b JH |
9433 | && (reload_in_progress || reload_completed |
9434 | || (register_operand (operands[0], VOIDmode) | |
9435 | && register_operand (operands[1], VOIDmode)))" | |
9436 | "#") | |
9437 | ||
9438 | (define_insn "*negdf2_ifs_rex64" | |
9439 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,fm#Yr,r#Yf") | |
9440 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0"))) | |
9441 | (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm")) | |
9442 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9443 | "TARGET_64BIT && TARGET_SSE2 |
141e454b JH |
9444 | && (reload_in_progress || reload_completed |
9445 | || (register_operand (operands[0], VOIDmode) | |
9446 | && register_operand (operands[1], VOIDmode)))" | |
b3298882 JH |
9447 | "#") |
9448 | ||
9449 | (define_split | |
9450 | [(set (match_operand:DF 0 "memory_operand" "") | |
9451 | (neg:DF (match_operand:DF 1 "memory_operand" ""))) | |
9452 | (use (match_operand:DF 2 "" "")) | |
9453 | (clobber (reg:CC 17))] | |
9454 | "" | |
9455 | [(parallel [(set (match_dup 0) | |
9456 | (neg:DF (match_dup 1))) | |
9457 | (clobber (reg:CC 17))])]) | |
9458 | ||
9459 | (define_split | |
9460 | [(set (match_operand:DF 0 "register_operand" "") | |
9461 | (neg:DF (match_operand:DF 1 "register_operand" ""))) | |
9462 | (use (match_operand:DF 2 "" "")) | |
9463 | (clobber (reg:CC 17))] | |
141e454b JH |
9464 | "reload_completed && !SSE_REG_P (operands[0]) |
9465 | && (!TARGET_64BIT || FP_REG_P (operands[0]))" | |
b3298882 JH |
9466 | [(parallel [(set (match_dup 0) |
9467 | (neg:DF (match_dup 1))) | |
9468 | (clobber (reg:CC 17))])]) | |
9469 | ||
141e454b JH |
9470 | (define_split |
9471 | [(set (match_operand:DF 0 "register_operand" "") | |
9472 | (neg:DF (match_operand:DF 1 "register_operand" ""))) | |
9473 | (use (match_operand:DF 2 "" "")) | |
9474 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9475 | "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])" |
141e454b JH |
9476 | [(parallel [(set (match_dup 0) |
9477 | (xor:DI (match_dup 1) (match_dup 2))) | |
9478 | (clobber (reg:CC 17))])] | |
9479 | "operands[0] = gen_lowpart (DImode, operands[0]); | |
9480 | operands[1] = gen_lowpart (DImode, operands[1]); | |
9481 | operands[2] = gen_lowpart (DImode, operands[2]);") | |
9482 | ||
b3298882 JH |
9483 | (define_split |
9484 | [(set (match_operand:DF 0 "register_operand" "") | |
9485 | (neg:DF (match_operand:DF 1 "register_operand" ""))) | |
9486 | (use (match_operand:DF 2 "register_operand" "")) | |
9487 | (clobber (reg:CC 17))] | |
9488 | "reload_completed && SSE_REG_P (operands[0])" | |
9489 | [(set (subreg:TI (match_dup 0) 0) | |
9490 | (xor:TI (subreg:TI (match_dup 1) 0) | |
9491 | (subreg:TI (match_dup 2) 0)))] | |
b3298882 JH |
9492 | { |
9493 | if (operands_match_p (operands[0], operands[2])) | |
9494 | { | |
9495 | rtx tmp; | |
9496 | tmp = operands[1]; | |
9497 | operands[1] = operands[2]; | |
9498 | operands[2] = tmp; | |
9499 | } | |
0f40f9f7 | 9500 | }) |
06a964de | 9501 | |
e20440c1 JH |
9502 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9503 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9504 | ;; to itself. | |
06a964de | 9505 | (define_insn "*negdf2_if" |
e20440c1 JH |
9506 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f") |
9507 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 9508 | (clobber (reg:CC 17))] |
1b0c37d7 | 9509 | "!TARGET_64BIT && TARGET_80387 |
141e454b JH |
9510 | && ix86_unary_operator_ok (NEG, DFmode, operands)" |
9511 | "#") | |
9512 | ||
9513 | ;; FIXME: We should to allow integer registers here. Problem is that | |
9514 | ;; we need another scratch register to get constant from. | |
9515 | ;; Forcing constant to mem if no register available in peep2 should be | |
9516 | ;; safe even for PIC mode, because of RIP relative addressing. | |
9517 | (define_insn "*negdf2_if_rex64" | |
9518 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf") | |
9519 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) | |
9520 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9521 | "TARGET_64BIT && TARGET_80387 |
141e454b | 9522 | && ix86_unary_operator_ok (NEG, DFmode, operands)" |
1ce485ec JH |
9523 | "#") |
9524 | ||
9525 | (define_split | |
c3c637e3 | 9526 | [(set (match_operand:DF 0 "fp_register_operand" "") |
1ce485ec JH |
9527 | (neg:DF (match_operand:DF 1 "register_operand" ""))) |
9528 | (clobber (reg:CC 17))] | |
c3c637e3 | 9529 | "TARGET_80387 && reload_completed" |
1ce485ec JH |
9530 | [(set (match_dup 0) |
9531 | (neg:DF (match_dup 1)))] | |
9532 | "") | |
9533 | ||
9534 | (define_split | |
c3c637e3 | 9535 | [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "") |
1ce485ec JH |
9536 | (neg:DF (match_operand:DF 1 "register_operand" ""))) |
9537 | (clobber (reg:CC 17))] | |
c3c637e3 | 9538 | "!TARGET_64BIT && TARGET_80387 && reload_completed" |
1ce485ec JH |
9539 | [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4))) |
9540 | (clobber (reg:CC 17))])] | |
d8bf17f9 | 9541 | "operands[4] = gen_int_mode (0x80000000, SImode); |
1ce485ec JH |
9542 | split_di (operands+0, 1, operands+2, operands+3);") |
9543 | ||
06a964de JH |
9544 | (define_expand "negxf2" |
9545 | [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9546 | (neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) |
06a964de | 9547 | (clobber (reg:CC 17))])] |
1b0c37d7 | 9548 | "!TARGET_64BIT && TARGET_80387" |
06a964de JH |
9549 | "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;") |
9550 | ||
2b589241 JH |
9551 | (define_expand "negtf2" |
9552 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
9553 | (neg:TF (match_operand:TF 1 "nonimmediate_operand" ""))) | |
9554 | (clobber (reg:CC 17))])] | |
9555 | "TARGET_80387" | |
9556 | "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;") | |
9557 | ||
e20440c1 JH |
9558 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9559 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9560 | ;; to itself. | |
06a964de | 9561 | (define_insn "*negxf2_if" |
e20440c1 JH |
9562 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") |
9563 | (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 9564 | (clobber (reg:CC 17))] |
1b0c37d7 | 9565 | "!TARGET_64BIT && TARGET_80387 |
1e07edd3 | 9566 | && ix86_unary_operator_ok (NEG, XFmode, operands)" |
1ce485ec JH |
9567 | "#") |
9568 | ||
9569 | (define_split | |
c3c637e3 | 9570 | [(set (match_operand:XF 0 "fp_register_operand" "") |
1ce485ec JH |
9571 | (neg:XF (match_operand:XF 1 "register_operand" ""))) |
9572 | (clobber (reg:CC 17))] | |
c3c637e3 | 9573 | "TARGET_80387 && reload_completed" |
1ce485ec JH |
9574 | [(set (match_dup 0) |
9575 | (neg:XF (match_dup 1)))] | |
9576 | "") | |
9577 | ||
9578 | (define_split | |
c3c637e3 | 9579 | [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "") |
1ce485ec JH |
9580 | (neg:XF (match_operand:XF 1 "register_operand" ""))) |
9581 | (clobber (reg:CC 17))] | |
c3c637e3 | 9582 | "TARGET_80387 && reload_completed" |
1ce485ec JH |
9583 | [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) |
9584 | (clobber (reg:CC 17))])] | |
9585 | "operands[1] = GEN_INT (0x8000); | |
141e454b JH |
9586 | operands[0] = gen_rtx_REG (SImode, |
9587 | true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") | |
1ce485ec | 9588 | |
2b589241 JH |
9589 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9590 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9591 | ;; to itself. | |
9592 | (define_insn "*negtf2_if" | |
9593 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f") | |
9594 | (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0"))) | |
9595 | (clobber (reg:CC 17))] | |
9596 | "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)" | |
9597 | "#") | |
9598 | ||
9599 | (define_split | |
c3c637e3 | 9600 | [(set (match_operand:TF 0 "fp_register_operand" "") |
2b589241 JH |
9601 | (neg:TF (match_operand:TF 1 "register_operand" ""))) |
9602 | (clobber (reg:CC 17))] | |
c3c637e3 | 9603 | "TARGET_80387 && reload_completed" |
2b589241 JH |
9604 | [(set (match_dup 0) |
9605 | (neg:TF (match_dup 1)))] | |
9606 | "") | |
9607 | ||
9608 | (define_split | |
c3c637e3 | 9609 | [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "") |
2b589241 JH |
9610 | (neg:TF (match_operand:TF 1 "register_operand" ""))) |
9611 | (clobber (reg:CC 17))] | |
c3c637e3 | 9612 | "TARGET_80387 && reload_completed" |
2b589241 JH |
9613 | [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) |
9614 | (clobber (reg:CC 17))])] | |
9615 | "operands[1] = GEN_INT (0x8000); | |
141e454b JH |
9616 | operands[0] = gen_rtx_REG (SImode, |
9617 | true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") | |
2b589241 | 9618 | |
1ce485ec JH |
9619 | ;; Conditionize these after reload. If they matches before reload, we |
9620 | ;; lose the clobber and ability to use integer instructions. | |
9621 | ||
9622 | (define_insn "*negsf2_1" | |
886c62d1 | 9623 | [(set (match_operand:SF 0 "register_operand" "=f") |
2ae0f82c | 9624 | (neg:SF (match_operand:SF 1 "register_operand" "0")))] |
1ce485ec | 9625 | "TARGET_80387 && reload_completed" |
10195bd8 | 9626 | "fchs" |
e075ae69 | 9627 | [(set_attr "type" "fsgn") |
6ef67412 | 9628 | (set_attr "mode" "SF") |
e075ae69 | 9629 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 9630 | |
1ce485ec | 9631 | (define_insn "*negdf2_1" |
886c62d1 | 9632 | [(set (match_operand:DF 0 "register_operand" "=f") |
2ae0f82c | 9633 | (neg:DF (match_operand:DF 1 "register_operand" "0")))] |
1ce485ec | 9634 | "TARGET_80387 && reload_completed" |
10195bd8 | 9635 | "fchs" |
e075ae69 | 9636 | [(set_attr "type" "fsgn") |
6ef67412 | 9637 | (set_attr "mode" "DF") |
e075ae69 | 9638 | (set_attr "ppro_uops" "few")]) |
886c62d1 | 9639 | |
6343a50e | 9640 | (define_insn "*negextendsfdf2" |
886c62d1 | 9641 | [(set (match_operand:DF 0 "register_operand" "=f") |
e075ae69 RH |
9642 | (neg:DF (float_extend:DF |
9643 | (match_operand:SF 1 "register_operand" "0"))))] | |
886c62d1 | 9644 | "TARGET_80387" |
10195bd8 | 9645 | "fchs" |
e075ae69 | 9646 | [(set_attr "type" "fsgn") |
6ef67412 | 9647 | (set_attr "mode" "DF") |
e075ae69 | 9648 | (set_attr "ppro_uops" "few")]) |
4fb21e90 | 9649 | |
1ce485ec | 9650 | (define_insn "*negxf2_1" |
4fb21e90 | 9651 | [(set (match_operand:XF 0 "register_operand" "=f") |
2ae0f82c | 9652 | (neg:XF (match_operand:XF 1 "register_operand" "0")))] |
1b0c37d7 | 9653 | "!TARGET_64BIT && TARGET_80387 && reload_completed" |
10195bd8 | 9654 | "fchs" |
e075ae69 | 9655 | [(set_attr "type" "fsgn") |
6ef67412 | 9656 | (set_attr "mode" "XF") |
e075ae69 RH |
9657 | (set_attr "ppro_uops" "few")]) |
9658 | ||
6343a50e | 9659 | (define_insn "*negextenddfxf2" |
e075ae69 RH |
9660 | [(set (match_operand:XF 0 "register_operand" "=f") |
9661 | (neg:XF (float_extend:XF | |
9662 | (match_operand:DF 1 "register_operand" "0"))))] | |
1b0c37d7 | 9663 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
9664 | "fchs" |
9665 | [(set_attr "type" "fsgn") | |
6ef67412 | 9666 | (set_attr "mode" "XF") |
e075ae69 | 9667 | (set_attr "ppro_uops" "few")]) |
4fb21e90 | 9668 | |
6343a50e | 9669 | (define_insn "*negextendsfxf2" |
4fb21e90 | 9670 | [(set (match_operand:XF 0 "register_operand" "=f") |
e075ae69 RH |
9671 | (neg:XF (float_extend:XF |
9672 | (match_operand:SF 1 "register_operand" "0"))))] | |
1b0c37d7 | 9673 | "!TARGET_64BIT && TARGET_80387" |
10195bd8 | 9674 | "fchs" |
e075ae69 | 9675 | [(set_attr "type" "fsgn") |
6ef67412 | 9676 | (set_attr "mode" "XF") |
e075ae69 | 9677 | (set_attr "ppro_uops" "few")]) |
2b589241 JH |
9678 | |
9679 | (define_insn "*negtf2_1" | |
9680 | [(set (match_operand:TF 0 "register_operand" "=f") | |
9681 | (neg:TF (match_operand:TF 1 "register_operand" "0")))] | |
9682 | "TARGET_80387 && reload_completed" | |
9683 | "fchs" | |
9684 | [(set_attr "type" "fsgn") | |
9685 | (set_attr "mode" "XF") | |
9686 | (set_attr "ppro_uops" "few")]) | |
9687 | ||
9688 | (define_insn "*negextenddftf2" | |
9689 | [(set (match_operand:TF 0 "register_operand" "=f") | |
9690 | (neg:TF (float_extend:TF | |
9691 | (match_operand:DF 1 "register_operand" "0"))))] | |
9692 | "TARGET_80387" | |
9693 | "fchs" | |
9694 | [(set_attr "type" "fsgn") | |
9695 | (set_attr "mode" "XF") | |
9696 | (set_attr "ppro_uops" "few")]) | |
9697 | ||
9698 | (define_insn "*negextendsftf2" | |
9699 | [(set (match_operand:TF 0 "register_operand" "=f") | |
9700 | (neg:TF (float_extend:TF | |
9701 | (match_operand:SF 1 "register_operand" "0"))))] | |
9702 | "TARGET_80387" | |
9703 | "fchs" | |
9704 | [(set_attr "type" "fsgn") | |
9705 | (set_attr "mode" "XF") | |
9706 | (set_attr "ppro_uops" "few")]) | |
886c62d1 JVA |
9707 | \f |
9708 | ;; Absolute value instructions | |
9709 | ||
06a964de JH |
9710 | (define_expand "abssf2" |
9711 | [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9712 | (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) |
06a964de JH |
9713 | (clobber (reg:CC 17))])] |
9714 | "TARGET_80387" | |
ca29d1dc JH |
9715 | "if (TARGET_SSE) |
9716 | { | |
9717 | /* In case operand is in memory, we will not use SSE. */ | |
9718 | if (memory_operand (operands[0], VOIDmode) | |
9719 | && rtx_equal_p (operands[0], operands[1])) | |
9720 | emit_insn (gen_abssf2_memory (operands[0], operands[1])); | |
9721 | else | |
9722 | { | |
9723 | /* Using SSE is tricky, since we need bitwise negation of -0 | |
9724 | in register. */ | |
9725 | rtx reg = gen_reg_rtx (SFmode); | |
141e454b JH |
9726 | rtx dest = operands[0]; |
9727 | ||
9728 | operands[1] = force_reg (SFmode, operands[1]); | |
9729 | operands[0] = force_reg (SFmode, operands[0]); | |
9730 | emit_move_insn (reg, | |
9731 | gen_lowpart (SFmode, | |
d8bf17f9 | 9732 | gen_int_mode (0x80000000, SImode))); |
ca29d1dc | 9733 | emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg)); |
141e454b JH |
9734 | if (dest != operands[0]) |
9735 | emit_move_insn (dest, operands[0]); | |
ca29d1dc JH |
9736 | } |
9737 | DONE; | |
9738 | } | |
9739 | ix86_expand_unary_operator (ABS, SFmode, operands); DONE;") | |
9740 | ||
9741 | (define_insn "abssf2_memory" | |
9742 | [(set (match_operand:SF 0 "memory_operand" "=m") | |
9743 | (abs:SF (match_operand:SF 1 "memory_operand" "0"))) | |
9744 | (clobber (reg:CC 17))] | |
9745 | "ix86_unary_operator_ok (ABS, SFmode, operands)" | |
9746 | "#") | |
9747 | ||
9748 | (define_insn "abssf2_ifs" | |
141e454b | 9749 | [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,f#xr,rm#xf") |
ca29d1dc | 9750 | (abs:SF (match_operand:SF 1 "nonimmediate_operand" "x,0,0"))) |
141e454b | 9751 | (use (match_operand:SF 2 "nonmemory_operand" "*0#x,*g#x,*g#x")) |
ca29d1dc | 9752 | (clobber (reg:CC 17))] |
141e454b JH |
9753 | "TARGET_SSE |
9754 | && (reload_in_progress || reload_completed | |
9755 | || (register_operand (operands[0], VOIDmode) | |
9756 | && register_operand (operands[1], VOIDmode)))" | |
ca29d1dc JH |
9757 | "#") |
9758 | ||
9759 | (define_split | |
9760 | [(set (match_operand:SF 0 "memory_operand" "") | |
9761 | (abs:SF (match_operand:SF 1 "memory_operand" ""))) | |
9762 | (use (match_operand:SF 2 "" "")) | |
9763 | (clobber (reg:CC 17))] | |
9764 | "" | |
9765 | [(parallel [(set (match_dup 0) | |
9766 | (abs:SF (match_dup 1))) | |
9767 | (clobber (reg:CC 17))])]) | |
9768 | ||
9769 | (define_split | |
9770 | [(set (match_operand:SF 0 "register_operand" "") | |
9771 | (abs:SF (match_operand:SF 1 "register_operand" ""))) | |
9772 | (use (match_operand:SF 2 "" "")) | |
9773 | (clobber (reg:CC 17))] | |
9774 | "reload_completed && !SSE_REG_P (operands[0])" | |
9775 | [(parallel [(set (match_dup 0) | |
9776 | (abs:SF (match_dup 1))) | |
9777 | (clobber (reg:CC 17))])]) | |
9778 | ||
9779 | (define_split | |
9780 | [(set (match_operand:SF 0 "register_operand" "") | |
9781 | (abs:SF (match_operand:SF 1 "register_operand" ""))) | |
9782 | (use (match_operand:SF 2 "register_operand" "")) | |
9783 | (clobber (reg:CC 17))] | |
9784 | "reload_completed && SSE_REG_P (operands[0])" | |
9785 | [(set (subreg:TI (match_dup 0) 0) | |
9786 | (and:TI (not:TI (subreg:TI (match_dup 2) 0)) | |
9787 | (subreg:TI (match_dup 1) 0)))]) | |
06a964de | 9788 | |
e20440c1 JH |
9789 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9790 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9791 | ;; to itself. | |
06a964de | 9792 | (define_insn "*abssf2_if" |
e20440c1 JH |
9793 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") |
9794 | (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 9795 | (clobber (reg:CC 17))] |
ca29d1dc | 9796 | "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE" |
1ce485ec JH |
9797 | "#") |
9798 | ||
9799 | (define_split | |
c3c637e3 | 9800 | [(set (match_operand:SF 0 "fp_register_operand" "") |
1ce485ec JH |
9801 | (abs:SF (match_operand:SF 1 "register_operand" ""))) |
9802 | (clobber (reg:CC 17))] | |
c3c637e3 | 9803 | "TARGET_80387" |
1ce485ec JH |
9804 | [(set (match_dup 0) |
9805 | (abs:SF (match_dup 1)))] | |
9806 | "") | |
9807 | ||
9808 | (define_split | |
c3c637e3 | 9809 | [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "") |
1ce485ec JH |
9810 | (abs:SF (match_operand:SF 1 "register_operand" ""))) |
9811 | (clobber (reg:CC 17))] | |
c3c637e3 | 9812 | "TARGET_80387 && reload_completed" |
1ce485ec JH |
9813 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) |
9814 | (clobber (reg:CC 17))])] | |
d8bf17f9 | 9815 | "operands[1] = gen_int_mode (~0x80000000, SImode); |
1ce485ec JH |
9816 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));") |
9817 | ||
9818 | (define_split | |
9819 | [(set (match_operand 0 "memory_operand" "") | |
9820 | (abs (match_operand 1 "memory_operand" ""))) | |
9821 | (clobber (reg:CC 17))] | |
9822 | "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" | |
9823 | [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
9824 | (clobber (reg:CC 17))])] | |
1ce485ec JH |
9825 | { |
9826 | int size = GET_MODE_SIZE (GET_MODE (operands[1])); | |
9827 | ||
b3298882 JH |
9828 | /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */ |
9829 | if (size >= 12) | |
1ce485ec | 9830 | size = 10; |
b72f00af | 9831 | operands[0] = adjust_address (operands[0], QImode, size - 1); |
d8bf17f9 | 9832 | operands[1] = gen_int_mode (~0x80, QImode); |
0f40f9f7 | 9833 | }) |
1ce485ec | 9834 | |
06a964de JH |
9835 | (define_expand "absdf2" |
9836 | [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9837 | (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) |
06a964de | 9838 | (clobber (reg:CC 17))])] |
1ce485ec | 9839 | "TARGET_80387" |
ca29d1dc JH |
9840 | "if (TARGET_SSE2) |
9841 | { | |
9842 | /* In case operand is in memory, we will not use SSE. */ | |
9843 | if (memory_operand (operands[0], VOIDmode) | |
9844 | && rtx_equal_p (operands[0], operands[1])) | |
9845 | emit_insn (gen_absdf2_memory (operands[0], operands[1])); | |
9846 | else | |
9847 | { | |
9848 | /* Using SSE is tricky, since we need bitwise negation of -0 | |
9849 | in register. */ | |
9850 | rtx reg = gen_reg_rtx (DFmode); | |
9851 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
d8bf17f9 | 9852 | rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode); |
ca29d1dc JH |
9853 | #else |
9854 | rtx imm = immed_double_const (0, 0x80000000, DImode); | |
9855 | #endif | |
141e454b JH |
9856 | rtx dest = operands[0]; |
9857 | ||
9858 | operands[1] = force_reg (DFmode, operands[1]); | |
9859 | operands[0] = force_reg (DFmode, operands[0]); | |
ca29d1dc JH |
9860 | emit_move_insn (reg, gen_lowpart (DFmode, imm)); |
9861 | emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg)); | |
141e454b JH |
9862 | if (dest != operands[0]) |
9863 | emit_move_insn (dest, operands[0]); | |
ca29d1dc JH |
9864 | } |
9865 | DONE; | |
9866 | } | |
9867 | ix86_expand_unary_operator (ABS, DFmode, operands); DONE;") | |
9868 | ||
9869 | (define_insn "absdf2_memory" | |
9870 | [(set (match_operand:DF 0 "memory_operand" "=m") | |
9871 | (abs:DF (match_operand:DF 1 "memory_operand" "0"))) | |
9872 | (clobber (reg:CC 17))] | |
9873 | "ix86_unary_operator_ok (ABS, DFmode, operands)" | |
9874 | "#") | |
9875 | ||
9876 | (define_insn "absdf2_ifs" | |
141e454b | 9877 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr,mr#Yf") |
ca29d1dc | 9878 | (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0"))) |
141e454b | 9879 | (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y")) |
ca29d1dc | 9880 | (clobber (reg:CC 17))] |
1b0c37d7 | 9881 | "!TARGET_64BIT && TARGET_SSE2 |
141e454b JH |
9882 | && (reload_in_progress || reload_completed |
9883 | || (register_operand (operands[0], VOIDmode) | |
9884 | && register_operand (operands[1], VOIDmode)))" | |
9885 | "#") | |
9886 | ||
9887 | (define_insn "*absdf2_ifs_rex64" | |
9888 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,mf#Yr") | |
9889 | (abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0"))) | |
9890 | (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y")) | |
9891 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9892 | "TARGET_64BIT && TARGET_SSE2 |
141e454b JH |
9893 | && (reload_in_progress || reload_completed |
9894 | || (register_operand (operands[0], VOIDmode) | |
9895 | && register_operand (operands[1], VOIDmode)))" | |
ca29d1dc JH |
9896 | "#") |
9897 | ||
9898 | (define_split | |
9899 | [(set (match_operand:DF 0 "memory_operand" "") | |
9900 | (abs:DF (match_operand:DF 1 "memory_operand" ""))) | |
9901 | (use (match_operand:DF 2 "" "")) | |
9902 | (clobber (reg:CC 17))] | |
9903 | "" | |
9904 | [(parallel [(set (match_dup 0) | |
9905 | (abs:DF (match_dup 1))) | |
9906 | (clobber (reg:CC 17))])]) | |
9907 | ||
9908 | (define_split | |
9909 | [(set (match_operand:DF 0 "register_operand" "") | |
9910 | (abs:DF (match_operand:DF 1 "register_operand" ""))) | |
9911 | (use (match_operand:DF 2 "" "")) | |
9912 | (clobber (reg:CC 17))] | |
9913 | "reload_completed && !SSE_REG_P (operands[0])" | |
9914 | [(parallel [(set (match_dup 0) | |
9915 | (abs:DF (match_dup 1))) | |
9916 | (clobber (reg:CC 17))])]) | |
9917 | ||
9918 | (define_split | |
9919 | [(set (match_operand:DF 0 "register_operand" "") | |
9920 | (abs:DF (match_operand:DF 1 "register_operand" ""))) | |
9921 | (use (match_operand:DF 2 "register_operand" "")) | |
9922 | (clobber (reg:CC 17))] | |
9923 | "reload_completed && SSE_REG_P (operands[0])" | |
9924 | [(set (subreg:TI (match_dup 0) 0) | |
9925 | (and:TI (not:TI (subreg:TI (match_dup 2) 0)) | |
9926 | (subreg:TI (match_dup 1) 0)))]) | |
9927 | ||
06a964de | 9928 | |
e20440c1 JH |
9929 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9930 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9931 | ;; to itself. | |
06a964de | 9932 | (define_insn "*absdf2_if" |
e20440c1 JH |
9933 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f") |
9934 | (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) | |
06a964de | 9935 | (clobber (reg:CC 17))] |
1b0c37d7 | 9936 | "!TARGET_64BIT && TARGET_80387 |
141e454b JH |
9937 | && ix86_unary_operator_ok (ABS, DFmode, operands)" |
9938 | "#") | |
9939 | ||
9940 | ;; FIXME: We should to allow integer registers here. Problem is that | |
9941 | ;; we need another scratch register to get constant from. | |
9942 | ;; Forcing constant to mem if no register available in peep2 should be | |
9943 | ;; safe even for PIC mode, because of RIP relative addressing. | |
9944 | (define_insn "*absdf2_if_rex64" | |
9945 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf") | |
9946 | (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) | |
9947 | (clobber (reg:CC 17))] | |
1b0c37d7 | 9948 | "TARGET_64BIT && TARGET_80387 |
141e454b | 9949 | && ix86_unary_operator_ok (ABS, DFmode, operands)" |
1ce485ec JH |
9950 | "#") |
9951 | ||
9952 | (define_split | |
c3c637e3 | 9953 | [(set (match_operand:DF 0 "fp_register_operand" "") |
1ce485ec JH |
9954 | (abs:DF (match_operand:DF 1 "register_operand" ""))) |
9955 | (clobber (reg:CC 17))] | |
c3c637e3 | 9956 | "TARGET_80387 && reload_completed" |
1ce485ec JH |
9957 | [(set (match_dup 0) |
9958 | (abs:DF (match_dup 1)))] | |
9959 | "") | |
9960 | ||
9961 | (define_split | |
c3c637e3 | 9962 | [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "") |
1ce485ec JH |
9963 | (abs:DF (match_operand:DF 1 "register_operand" ""))) |
9964 | (clobber (reg:CC 17))] | |
c3c637e3 | 9965 | "!TARGET_64BIT && TARGET_80387 && reload_completed" |
1ce485ec JH |
9966 | [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4))) |
9967 | (clobber (reg:CC 17))])] | |
d8bf17f9 | 9968 | "operands[4] = gen_int_mode (~0x80000000, SImode); |
1ce485ec JH |
9969 | split_di (operands+0, 1, operands+2, operands+3);") |
9970 | ||
06a964de JH |
9971 | (define_expand "absxf2" |
9972 | [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") | |
2756c3d8 | 9973 | (neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) |
06a964de | 9974 | (clobber (reg:CC 17))])] |
1b0c37d7 | 9975 | "!TARGET_64BIT && TARGET_80387" |
06a964de JH |
9976 | "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;") |
9977 | ||
2b589241 JH |
9978 | (define_expand "abstf2" |
9979 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
9980 | (neg:TF (match_operand:TF 1 "nonimmediate_operand" ""))) | |
9981 | (clobber (reg:CC 17))])] | |
9982 | "TARGET_80387" | |
9983 | "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;") | |
9984 | ||
e20440c1 JH |
9985 | ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems |
9986 | ;; because of secondary memory needed to reload from class FLOAT_INT_REGS | |
9987 | ;; to itself. | |
06a964de | 9988 | (define_insn "*absxf2_if" |
e20440c1 JH |
9989 | [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") |
9990 | (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) | |
1ce485ec | 9991 | (clobber (reg:CC 17))] |
1b0c37d7 | 9992 | "!TARGET_64BIT && TARGET_80387 |
1e07edd3 | 9993 | && ix86_unary_operator_ok (ABS, XFmode, operands)" |
1ce485ec JH |
9994 | "#") |
9995 | ||
9996 | (define_split | |
c3c637e3 | 9997 | [(set (match_operand:XF 0 "fp_register_operand" "") |
1ce485ec JH |
9998 | (abs:XF (match_operand:XF 1 "register_operand" ""))) |
9999 | (clobber (reg:CC 17))] | |
c3c637e3 | 10000 | "TARGET_80387 && reload_completed" |
1ce485ec JH |
10001 | [(set (match_dup 0) |
10002 | (abs:XF (match_dup 1)))] | |
10003 | "") | |
10004 | ||
10005 | (define_split | |
c3c637e3 | 10006 | [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "") |
1ce485ec JH |
10007 | (abs:XF (match_operand:XF 1 "register_operand" ""))) |
10008 | (clobber (reg:CC 17))] | |
c3c637e3 | 10009 | "TARGET_80387 && reload_completed" |
1ce485ec JH |
10010 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) |
10011 | (clobber (reg:CC 17))])] | |
141e454b JH |
10012 | "operands[1] = GEN_INT (~0x8000); |
10013 | operands[0] = gen_rtx_REG (SImode, | |
10014 | true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") | |
1ce485ec | 10015 | |
2b589241 JH |
10016 | (define_insn "*abstf2_if" |
10017 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f") | |
10018 | (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0"))) | |
10019 | (clobber (reg:CC 17))] | |
10020 | "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)" | |
10021 | "#") | |
10022 | ||
10023 | (define_split | |
c3c637e3 | 10024 | [(set (match_operand:TF 0 "fp_register_operand" "") |
2b589241 JH |
10025 | (abs:TF (match_operand:TF 1 "register_operand" ""))) |
10026 | (clobber (reg:CC 17))] | |
c3c637e3 | 10027 | "TARGET_80387 && reload_completed" |
2b589241 JH |
10028 | [(set (match_dup 0) |
10029 | (abs:TF (match_dup 1)))] | |
10030 | "") | |
10031 | ||
10032 | (define_split | |
c3c637e3 | 10033 | [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "") |
2b589241 JH |
10034 | (abs:TF (match_operand:TF 1 "register_operand" ""))) |
10035 | (clobber (reg:CC 17))] | |
c3c637e3 | 10036 | "TARGET_80387 && reload_completed" |
2b589241 JH |
10037 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) |
10038 | (clobber (reg:CC 17))])] | |
141e454b JH |
10039 | "operands[1] = GEN_INT (~0x8000); |
10040 | operands[0] = gen_rtx_REG (SImode, | |
10041 | true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") | |
2b589241 | 10042 | |
1ce485ec | 10043 | (define_insn "*abssf2_1" |
886c62d1 | 10044 | [(set (match_operand:SF 0 "register_operand" "=f") |
2ae0f82c | 10045 | (abs:SF (match_operand:SF 1 "register_operand" "0")))] |
1ce485ec | 10046 | "TARGET_80387 && reload_completed" |
2ae0f82c | 10047 | "fabs" |
6ef67412 JH |
10048 | [(set_attr "type" "fsgn") |
10049 | (set_attr "mode" "SF")]) | |
886c62d1 | 10050 | |
1ce485ec | 10051 | (define_insn "*absdf2_1" |
886c62d1 | 10052 | [(set (match_operand:DF 0 "register_operand" "=f") |
2ae0f82c | 10053 | (abs:DF (match_operand:DF 1 "register_operand" "0")))] |
1ce485ec | 10054 | "TARGET_80387 && reload_completed" |
2ae0f82c | 10055 | "fabs" |
6ef67412 JH |
10056 | [(set_attr "type" "fsgn") |
10057 | (set_attr "mode" "DF")]) | |
886c62d1 | 10058 | |
6343a50e | 10059 | (define_insn "*absextendsfdf2" |
886c62d1 | 10060 | [(set (match_operand:DF 0 "register_operand" "=f") |
e075ae69 RH |
10061 | (abs:DF (float_extend:DF |
10062 | (match_operand:SF 1 "register_operand" "0"))))] | |
886c62d1 | 10063 | "TARGET_80387" |
2ae0f82c | 10064 | "fabs" |
6ef67412 JH |
10065 | [(set_attr "type" "fsgn") |
10066 | (set_attr "mode" "DF")]) | |
886c62d1 | 10067 | |
1ce485ec | 10068 | (define_insn "*absxf2_1" |
4fb21e90 | 10069 | [(set (match_operand:XF 0 "register_operand" "=f") |
2ae0f82c | 10070 | (abs:XF (match_operand:XF 1 "register_operand" "0")))] |
1b0c37d7 | 10071 | "!TARGET_64BIT && TARGET_80387 && reload_completed" |
2ae0f82c | 10072 | "fabs" |
6ef67412 JH |
10073 | [(set_attr "type" "fsgn") |
10074 | (set_attr "mode" "DF")]) | |
4fb21e90 | 10075 | |
6343a50e | 10076 | (define_insn "*absextenddfxf2" |
4fb21e90 | 10077 | [(set (match_operand:XF 0 "register_operand" "=f") |
e075ae69 RH |
10078 | (abs:XF (float_extend:XF |
10079 | (match_operand:DF 1 "register_operand" "0"))))] | |
1b0c37d7 | 10080 | "!TARGET_64BIT && TARGET_80387" |
2ae0f82c | 10081 | "fabs" |
6ef67412 JH |
10082 | [(set_attr "type" "fsgn") |
10083 | (set_attr "mode" "XF")]) | |
a199fdd6 | 10084 | |
6343a50e | 10085 | (define_insn "*absextendsfxf2" |
58733f96 | 10086 | [(set (match_operand:XF 0 "register_operand" "=f") |
e075ae69 RH |
10087 | (abs:XF (float_extend:XF |
10088 | (match_operand:SF 1 "register_operand" "0"))))] | |
1b0c37d7 | 10089 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 | 10090 | "fabs" |
6ef67412 JH |
10091 | [(set_attr "type" "fsgn") |
10092 | (set_attr "mode" "XF")]) | |
2b589241 JH |
10093 | |
10094 | (define_insn "*abstf2_1" | |
10095 | [(set (match_operand:TF 0 "register_operand" "=f") | |
10096 | (abs:TF (match_operand:TF 1 "register_operand" "0")))] | |
10097 | "TARGET_80387 && reload_completed" | |
10098 | "fabs" | |
10099 | [(set_attr "type" "fsgn") | |
10100 | (set_attr "mode" "DF")]) | |
10101 | ||
10102 | (define_insn "*absextenddftf2" | |
10103 | [(set (match_operand:TF 0 "register_operand" "=f") | |
10104 | (abs:TF (float_extend:TF | |
10105 | (match_operand:DF 1 "register_operand" "0"))))] | |
10106 | "TARGET_80387" | |
10107 | "fabs" | |
10108 | [(set_attr "type" "fsgn") | |
10109 | (set_attr "mode" "XF")]) | |
10110 | ||
10111 | (define_insn "*absextendsftf2" | |
10112 | [(set (match_operand:TF 0 "register_operand" "=f") | |
10113 | (abs:TF (float_extend:TF | |
10114 | (match_operand:SF 1 "register_operand" "0"))))] | |
10115 | "TARGET_80387" | |
10116 | "fabs" | |
10117 | [(set_attr "type" "fsgn") | |
10118 | (set_attr "mode" "XF")]) | |
886c62d1 | 10119 | \f |
e075ae69 | 10120 | ;; One complement instructions |
886c62d1 | 10121 | |
9b70259d JH |
10122 | (define_expand "one_cmpldi2" |
10123 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
10124 | (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))] | |
10125 | "TARGET_64BIT" | |
10126 | "ix86_expand_unary_operator (NOT, DImode, operands); DONE;") | |
10127 | ||
10128 | (define_insn "*one_cmpldi2_1_rex64" | |
10129 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
10130 | (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))] | |
10131 | "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)" | |
0f40f9f7 | 10132 | "not{q}\t%0" |
9b70259d JH |
10133 | [(set_attr "type" "negnot") |
10134 | (set_attr "mode" "DI")]) | |
10135 | ||
10136 | (define_insn "*one_cmpldi2_2_rex64" | |
10137 | [(set (reg 17) | |
10138 | (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")) | |
10139 | (const_int 0))) | |
10140 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
10141 | (not:DI (match_dup 1)))] | |
10142 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
10143 | && ix86_unary_operator_ok (NOT, DImode, operands)" | |
10144 | "#" | |
10145 | [(set_attr "type" "alu1") | |
10146 | (set_attr "mode" "DI")]) | |
10147 | ||
10148 | (define_split | |
10149 | [(set (reg 17) | |
10150 | (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "")) | |
10151 | (const_int 0))) | |
10152 | (set (match_operand:DI 0 "nonimmediate_operand" "") | |
10153 | (not:DI (match_dup 1)))] | |
10154 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" | |
10155 | [(parallel [(set (reg:CCNO 17) | |
10156 | (compare:CCNO (xor:DI (match_dup 1) (const_int -1)) | |
10157 | (const_int 0))) | |
10158 | (set (match_dup 0) | |
10159 | (xor:DI (match_dup 1) (const_int -1)))])] | |
10160 | "") | |
10161 | ||
06a964de | 10162 | (define_expand "one_cmplsi2" |
a1cbdd7f JH |
10163 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
10164 | (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
06a964de JH |
10165 | "" |
10166 | "ix86_expand_unary_operator (NOT, SImode, operands); DONE;") | |
10167 | ||
10168 | (define_insn "*one_cmplsi2_1" | |
2ae0f82c SC |
10169 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
10170 | (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))] | |
a1cbdd7f | 10171 | "ix86_unary_operator_ok (NOT, SImode, operands)" |
0f40f9f7 | 10172 | "not{l}\t%0" |
6ef67412 JH |
10173 | [(set_attr "type" "negnot") |
10174 | (set_attr "mode" "SI")]) | |
bb524860 | 10175 | |
9b70259d JH |
10176 | ;; ??? Currently never generated - xor is used instead. |
10177 | (define_insn "*one_cmplsi2_1_zext" | |
10178 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10179 | (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))] | |
10180 | "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)" | |
0f40f9f7 | 10181 | "not{l}\t%k0" |
9b70259d JH |
10182 | [(set_attr "type" "negnot") |
10183 | (set_attr "mode" "SI")]) | |
10184 | ||
06a964de | 10185 | (define_insn "*one_cmplsi2_2" |
16189740 RH |
10186 | [(set (reg 17) |
10187 | (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")) | |
10188 | (const_int 0))) | |
e075ae69 RH |
10189 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
10190 | (not:SI (match_dup 1)))] | |
16189740 RH |
10191 | "ix86_match_ccmode (insn, CCNOmode) |
10192 | && ix86_unary_operator_ok (NOT, SImode, operands)" | |
e075ae69 | 10193 | "#" |
6ef67412 JH |
10194 | [(set_attr "type" "alu1") |
10195 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
10196 | |
10197 | (define_split | |
16189740 RH |
10198 | [(set (reg 17) |
10199 | (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "")) | |
10200 | (const_int 0))) | |
e075ae69 RH |
10201 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
10202 | (not:SI (match_dup 1)))] | |
16189740 | 10203 | "ix86_match_ccmode (insn, CCNOmode)" |
e075ae69 RH |
10204 | [(parallel [(set (reg:CCNO 17) |
10205 | (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) | |
10206 | (const_int 0))) | |
10207 | (set (match_dup 0) | |
10208 | (xor:SI (match_dup 1) (const_int -1)))])] | |
10209 | "") | |
886c62d1 | 10210 | |
9b70259d JH |
10211 | ;; ??? Currently never generated - xor is used instead. |
10212 | (define_insn "*one_cmplsi2_2_zext" | |
10213 | [(set (reg 17) | |
10214 | (compare (not:SI (match_operand:SI 1 "register_operand" "0")) | |
10215 | (const_int 0))) | |
10216 | (set (match_operand:DI 0 "register_operand" "=r") | |
10217 | (zero_extend:DI (not:SI (match_dup 1))))] | |
10218 | "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) | |
10219 | && ix86_unary_operator_ok (NOT, SImode, operands)" | |
10220 | "#" | |
10221 | [(set_attr "type" "alu1") | |
10222 | (set_attr "mode" "SI")]) | |
10223 | ||
10224 | (define_split | |
10225 | [(set (reg 17) | |
10226 | (compare (not:SI (match_operand:SI 1 "register_operand" "")) | |
10227 | (const_int 0))) | |
10228 | (set (match_operand:DI 0 "register_operand" "") | |
10229 | (zero_extend:DI (not:SI (match_dup 1))))] | |
10230 | "ix86_match_ccmode (insn, CCNOmode)" | |
10231 | [(parallel [(set (reg:CCNO 17) | |
10232 | (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) | |
10233 | (const_int 0))) | |
10234 | (set (match_dup 0) | |
10235 | (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])] | |
10236 | "") | |
10237 | ||
06a964de | 10238 | (define_expand "one_cmplhi2" |
a1cbdd7f JH |
10239 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
10240 | (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
d9f32422 | 10241 | "TARGET_HIMODE_MATH" |
06a964de JH |
10242 | "ix86_expand_unary_operator (NOT, HImode, operands); DONE;") |
10243 | ||
10244 | (define_insn "*one_cmplhi2_1" | |
2ae0f82c SC |
10245 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
10246 | (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))] | |
a1cbdd7f | 10247 | "ix86_unary_operator_ok (NOT, HImode, operands)" |
0f40f9f7 | 10248 | "not{w}\t%0" |
6ef67412 JH |
10249 | [(set_attr "type" "negnot") |
10250 | (set_attr "mode" "HI")]) | |
bb524860 | 10251 | |
06a964de | 10252 | (define_insn "*one_cmplhi2_2" |
16189740 RH |
10253 | [(set (reg 17) |
10254 | (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")) | |
10255 | (const_int 0))) | |
e075ae69 RH |
10256 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
10257 | (not:HI (match_dup 1)))] | |
16189740 RH |
10258 | "ix86_match_ccmode (insn, CCNOmode) |
10259 | && ix86_unary_operator_ok (NEG, HImode, operands)" | |
e075ae69 | 10260 | "#" |
6ef67412 JH |
10261 | [(set_attr "type" "alu1") |
10262 | (set_attr "mode" "HI")]) | |
e075ae69 RH |
10263 | |
10264 | (define_split | |
16189740 RH |
10265 | [(set (reg 17) |
10266 | (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "")) | |
10267 | (const_int 0))) | |
e075ae69 RH |
10268 | (set (match_operand:HI 0 "nonimmediate_operand" "") |
10269 | (not:HI (match_dup 1)))] | |
16189740 | 10270 | "ix86_match_ccmode (insn, CCNOmode)" |
e075ae69 RH |
10271 | [(parallel [(set (reg:CCNO 17) |
10272 | (compare:CCNO (xor:HI (match_dup 1) (const_int -1)) | |
10273 | (const_int 0))) | |
10274 | (set (match_dup 0) | |
10275 | (xor:HI (match_dup 1) (const_int -1)))])] | |
10276 | "") | |
886c62d1 | 10277 | |
e075ae69 | 10278 | ;; %%% Potential partial reg stall on alternative 1. What to do? |
06a964de | 10279 | (define_expand "one_cmplqi2" |
a1cbdd7f JH |
10280 | [(set (match_operand:QI 0 "nonimmediate_operand" "") |
10281 | (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
d9f32422 | 10282 | "TARGET_QIMODE_MATH" |
06a964de JH |
10283 | "ix86_expand_unary_operator (NOT, QImode, operands); DONE;") |
10284 | ||
10285 | (define_insn "*one_cmplqi2_1" | |
7c6b971d | 10286 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r") |
e075ae69 | 10287 | (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))] |
a1cbdd7f | 10288 | "ix86_unary_operator_ok (NOT, QImode, operands)" |
e075ae69 | 10289 | "@ |
0f40f9f7 ZW |
10290 | not{b}\t%0 |
10291 | not{l}\t%k0" | |
6ef67412 JH |
10292 | [(set_attr "type" "negnot") |
10293 | (set_attr "mode" "QI,SI")]) | |
bb524860 | 10294 | |
06a964de | 10295 | (define_insn "*one_cmplqi2_2" |
16189740 RH |
10296 | [(set (reg 17) |
10297 | (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")) | |
10298 | (const_int 0))) | |
e075ae69 RH |
10299 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
10300 | (not:QI (match_dup 1)))] | |
16189740 RH |
10301 | "ix86_match_ccmode (insn, CCNOmode) |
10302 | && ix86_unary_operator_ok (NOT, QImode, operands)" | |
e075ae69 | 10303 | "#" |
6ef67412 JH |
10304 | [(set_attr "type" "alu1") |
10305 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
10306 | |
10307 | (define_split | |
16189740 RH |
10308 | [(set (reg 17) |
10309 | (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "")) | |
10310 | (const_int 0))) | |
e075ae69 RH |
10311 | (set (match_operand:QI 0 "nonimmediate_operand" "") |
10312 | (not:QI (match_dup 1)))] | |
16189740 | 10313 | "ix86_match_ccmode (insn, CCNOmode)" |
e075ae69 RH |
10314 | [(parallel [(set (reg:CCNO 17) |
10315 | (compare:CCNO (xor:QI (match_dup 1) (const_int -1)) | |
10316 | (const_int 0))) | |
10317 | (set (match_dup 0) | |
10318 | (xor:QI (match_dup 1) (const_int -1)))])] | |
10319 | "") | |
886c62d1 | 10320 | \f |
e075ae69 | 10321 | ;; Arithmetic shift instructions |
886c62d1 JVA |
10322 | |
10323 | ;; DImode shifts are implemented using the i386 "shift double" opcode, | |
10324 | ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count | |
10325 | ;; is variable, then the count is in %cl and the "imm" operand is dropped | |
10326 | ;; from the assembler input. | |
e075ae69 | 10327 | ;; |
886c62d1 JVA |
10328 | ;; This instruction shifts the target reg/mem as usual, but instead of |
10329 | ;; shifting in zeros, bits are shifted in from reg operand. If the insn | |
10330 | ;; is a left shift double, bits are taken from the high order bits of | |
10331 | ;; reg, else if the insn is a shift right double, bits are taken from the | |
10332 | ;; low order bits of reg. So if %eax is "1234" and %edx is "5678", | |
10333 | ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345". | |
e075ae69 | 10334 | ;; |
886c62d1 JVA |
10335 | ;; Since sh[lr]d does not change the `reg' operand, that is done |
10336 | ;; separately, making all shifts emit pairs of shift double and normal | |
10337 | ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to | |
10338 | ;; support a 63 bit shift, each shift where the count is in a reg expands | |
f58acb67 | 10339 | ;; to a pair of shifts, a branch, a shift by 32 and a label. |
e075ae69 | 10340 | ;; |
886c62d1 JVA |
10341 | ;; If the shift count is a constant, we need never emit more than one |
10342 | ;; shift pair, instead using moves and sign extension for counts greater | |
10343 | ;; than 31. | |
10344 | ||
56c0e8fa | 10345 | (define_expand "ashldi3" |
371bc54b JH |
10346 | [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") |
10347 | (ashift:DI (match_operand:DI 1 "shiftdi_operand" "") | |
3d117b30 | 10348 | (match_operand:QI 2 "nonmemory_operand" ""))) |
e075ae69 | 10349 | (clobber (reg:CC 17))])] |
56c0e8fa | 10350 | "" |
56c0e8fa | 10351 | { |
3d117b30 | 10352 | if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) |
56c0e8fa | 10353 | { |
e075ae69 RH |
10354 | emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2])); |
10355 | DONE; | |
56c0e8fa | 10356 | } |
371bc54b JH |
10357 | ix86_expand_binary_operator (ASHIFT, DImode, operands); |
10358 | DONE; | |
0f40f9f7 | 10359 | }) |
56c0e8fa | 10360 | |
371bc54b JH |
10361 | (define_insn "*ashldi3_1_rex64" |
10362 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") | |
10363 | (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r") | |
7c17f553 | 10364 | (match_operand:QI 2 "nonmemory_operand" "cJ,M"))) |
371bc54b JH |
10365 | (clobber (reg:CC 17))] |
10366 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)" | |
371bc54b JH |
10367 | { |
10368 | switch (get_attr_type (insn)) | |
10369 | { | |
10370 | case TYPE_ALU: | |
10371 | if (operands[2] != const1_rtx) | |
10372 | abort (); | |
10373 | if (!rtx_equal_p (operands[0], operands[1])) | |
10374 | abort (); | |
0f40f9f7 | 10375 | return "add{q}\t{%0, %0|%0, %0}"; |
371bc54b JH |
10376 | |
10377 | case TYPE_LEA: | |
10378 | if (GET_CODE (operands[2]) != CONST_INT | |
10379 | || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3) | |
10380 | abort (); | |
10381 | operands[1] = gen_rtx_MULT (DImode, operands[1], | |
10382 | GEN_INT (1 << INTVAL (operands[2]))); | |
0f40f9f7 | 10383 | return "lea{q}\t{%a1, %0|%0, %a1}"; |
371bc54b JH |
10384 | |
10385 | default: | |
10386 | if (REG_P (operands[2])) | |
0f40f9f7 | 10387 | return "sal{q}\t{%b2, %0|%0, %b2}"; |
371bc54b JH |
10388 | else if (GET_CODE (operands[2]) == CONST_INT |
10389 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10390 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 10391 | return "sal{q}\t%0"; |
371bc54b | 10392 | else |
0f40f9f7 | 10393 | return "sal{q}\t{%2, %0|%0, %2}"; |
371bc54b | 10394 | } |
0f40f9f7 | 10395 | } |
371bc54b JH |
10396 | [(set (attr "type") |
10397 | (cond [(eq_attr "alternative" "1") | |
10398 | (const_string "lea") | |
10399 | (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10400 | (const_int 0)) | |
10401 | (match_operand 0 "register_operand" "")) | |
10402 | (match_operand 2 "const1_operand" "")) | |
10403 | (const_string "alu") | |
10404 | ] | |
10405 | (const_string "ishift"))) | |
10406 | (set_attr "mode" "DI")]) | |
10407 | ||
10408 | ;; Convert lea to the lea pattern to avoid flags dependency. | |
10409 | (define_split | |
10410 | [(set (match_operand:DI 0 "register_operand" "") | |
10411 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
10412 | (match_operand:QI 2 "immediate_operand" ""))) | |
10413 | (clobber (reg:CC 17))] | |
1b0c37d7 | 10414 | "TARGET_64BIT && reload_completed |
371bc54b JH |
10415 | && true_regnum (operands[0]) != true_regnum (operands[1])" |
10416 | [(set (match_dup 0) | |
10417 | (mult:DI (match_dup 1) | |
10418 | (match_dup 2)))] | |
d8bf17f9 | 10419 | "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);") |
371bc54b JH |
10420 | |
10421 | ;; This pattern can't accept a variable shift count, since shifts by | |
10422 | ;; zero don't affect the flags. We assume that shifts by constant | |
10423 | ;; zero are optimized away. | |
10424 | (define_insn "*ashldi3_cmp_rex64" | |
10425 | [(set (reg 17) | |
10426 | (compare | |
10427 | (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
10428 | (match_operand:QI 2 "immediate_operand" "e")) | |
10429 | (const_int 0))) | |
10430 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
10431 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
10432 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
10433 | && ix86_binary_operator_ok (ASHIFT, DImode, operands)" | |
371bc54b JH |
10434 | { |
10435 | switch (get_attr_type (insn)) | |
10436 | { | |
10437 | case TYPE_ALU: | |
10438 | if (operands[2] != const1_rtx) | |
10439 | abort (); | |
0f40f9f7 | 10440 | return "add{q}\t{%0, %0|%0, %0}"; |
371bc54b JH |
10441 | |
10442 | default: | |
10443 | if (REG_P (operands[2])) | |
0f40f9f7 | 10444 | return "sal{q}\t{%b2, %0|%0, %b2}"; |
371bc54b JH |
10445 | else if (GET_CODE (operands[2]) == CONST_INT |
10446 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10447 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 10448 | return "sal{q}\t%0"; |
371bc54b | 10449 | else |
0f40f9f7 | 10450 | return "sal{q}\t{%2, %0|%0, %2}"; |
371bc54b | 10451 | } |
0f40f9f7 | 10452 | } |
371bc54b JH |
10453 | [(set (attr "type") |
10454 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10455 | (const_int 0)) | |
10456 | (match_operand 0 "register_operand" "")) | |
10457 | (match_operand 2 "const1_operand" "")) | |
10458 | (const_string "alu") | |
10459 | ] | |
10460 | (const_string "ishift"))) | |
10461 | (set_attr "mode" "DI")]) | |
10462 | ||
e075ae69 RH |
10463 | (define_insn "ashldi3_1" |
10464 | [(set (match_operand:DI 0 "register_operand" "=r") | |
56c0e8fa | 10465 | (ashift:DI (match_operand:DI 1 "register_operand" "0") |
e075ae69 RH |
10466 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) |
10467 | (clobber (match_scratch:SI 3 "=&r")) | |
10468 | (clobber (reg:CC 17))] | |
371bc54b | 10469 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 RH |
10470 | "#" |
10471 | [(set_attr "type" "multi")]) | |
886c62d1 | 10472 | |
e075ae69 RH |
10473 | (define_insn "*ashldi3_2" |
10474 | [(set (match_operand:DI 0 "register_operand" "=r") | |
56c0e8fa | 10475 | (ashift:DI (match_operand:DI 1 "register_operand" "0") |
e075ae69 RH |
10476 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) |
10477 | (clobber (reg:CC 17))] | |
371bc54b | 10478 | "!TARGET_64BIT" |
e075ae69 RH |
10479 | "#" |
10480 | [(set_attr "type" "multi")]) | |
886c62d1 | 10481 | |
e075ae69 RH |
10482 | (define_split |
10483 | [(set (match_operand:DI 0 "register_operand" "") | |
10484 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
10485 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
10486 | (clobber (match_scratch:SI 3 "")) | |
10487 | (clobber (reg:CC 17))] | |
371bc54b | 10488 | "!TARGET_64BIT && TARGET_CMOVE && reload_completed" |
e075ae69 RH |
10489 | [(const_int 0)] |
10490 | "ix86_split_ashldi (operands, operands[3]); DONE;") | |
47f59fd4 | 10491 | |
e075ae69 RH |
10492 | (define_split |
10493 | [(set (match_operand:DI 0 "register_operand" "") | |
10494 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
10495 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
10496 | (clobber (reg:CC 17))] | |
371bc54b | 10497 | "!TARGET_64BIT && reload_completed" |
e075ae69 RH |
10498 | [(const_int 0)] |
10499 | "ix86_split_ashldi (operands, NULL_RTX); DONE;") | |
6ec6d558 | 10500 | |
e075ae69 RH |
10501 | (define_insn "x86_shld_1" |
10502 | [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m") | |
10503 | (ior:SI (ashift:SI (match_dup 0) | |
10504 | (match_operand:QI 2 "nonmemory_operand" "I,c")) | |
10505 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") | |
10506 | (minus:QI (const_int 32) (match_dup 2))))) | |
10507 | (clobber (reg:CC 17))] | |
6ec6d558 | 10508 | "" |
e075ae69 | 10509 | "@ |
0f40f9f7 ZW |
10510 | shld{l}\t{%2, %1, %0|%0, %1, %2} |
10511 | shld{l}\t{%s2%1, %0|%0, %1, %2}" | |
e075ae69 | 10512 | [(set_attr "type" "ishift") |
6ef67412 JH |
10513 | (set_attr "prefix_0f" "1") |
10514 | (set_attr "mode" "SI") | |
e075ae69 | 10515 | (set_attr "pent_pair" "np") |
309ada50 | 10516 | (set_attr "athlon_decode" "vector") |
e075ae69 RH |
10517 | (set_attr "ppro_uops" "few")]) |
10518 | ||
10519 | (define_expand "x86_shift_adj_1" | |
16189740 RH |
10520 | [(set (reg:CCZ 17) |
10521 | (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "") | |
10522 | (const_int 32)) | |
10523 | (const_int 0))) | |
e075ae69 | 10524 | (set (match_operand:SI 0 "register_operand" "") |
16189740 | 10525 | (if_then_else:SI (ne (reg:CCZ 17) (const_int 0)) |
e075ae69 RH |
10526 | (match_operand:SI 1 "register_operand" "") |
10527 | (match_dup 0))) | |
10528 | (set (match_dup 1) | |
16189740 | 10529 | (if_then_else:SI (ne (reg:CCZ 17) (const_int 0)) |
e075ae69 RH |
10530 | (match_operand:SI 3 "register_operand" "r") |
10531 | (match_dup 1)))] | |
10532 | "TARGET_CMOVE" | |
6ec6d558 JH |
10533 | "") |
10534 | ||
e075ae69 RH |
10535 | (define_expand "x86_shift_adj_2" |
10536 | [(use (match_operand:SI 0 "register_operand" "")) | |
10537 | (use (match_operand:SI 1 "register_operand" "")) | |
10538 | (use (match_operand:QI 2 "register_operand" ""))] | |
886c62d1 | 10539 | "" |
e075ae69 RH |
10540 | { |
10541 | rtx label = gen_label_rtx (); | |
10542 | rtx tmp; | |
886c62d1 | 10543 | |
16189740 | 10544 | emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32))); |
886c62d1 | 10545 | |
16189740 | 10546 | tmp = gen_rtx_REG (CCZmode, FLAGS_REG); |
e075ae69 RH |
10547 | tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); |
10548 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
10549 | gen_rtx_LABEL_REF (VOIDmode, label), | |
10550 | pc_rtx); | |
10551 | tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
10552 | JUMP_LABEL (tmp) = label; | |
886c62d1 | 10553 | |
e075ae69 RH |
10554 | emit_move_insn (operands[0], operands[1]); |
10555 | emit_move_insn (operands[1], const0_rtx); | |
886c62d1 | 10556 | |
e075ae69 RH |
10557 | emit_label (label); |
10558 | LABEL_NUSES (label) = 1; | |
56c0e8fa JVA |
10559 | |
10560 | DONE; | |
0f40f9f7 | 10561 | }) |
56c0e8fa | 10562 | |
d525dfdf JH |
10563 | (define_expand "ashlsi3" |
10564 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
10565 | (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
10566 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
10567 | (clobber (reg:CC 17))] | |
10568 | "" | |
10569 | "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;") | |
10570 | ||
10571 | (define_insn "*ashlsi3_1" | |
e075ae69 RH |
10572 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") |
10573 | (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r") | |
10574 | (match_operand:QI 2 "nonmemory_operand" "cI,M"))) | |
10575 | (clobber (reg:CC 17))] | |
d525dfdf | 10576 | "ix86_binary_operator_ok (ASHIFT, SImode, operands)" |
2ae0f82c | 10577 | { |
e075ae69 RH |
10578 | switch (get_attr_type (insn)) |
10579 | { | |
10580 | case TYPE_ALU: | |
10581 | if (operands[2] != const1_rtx) | |
10582 | abort (); | |
10583 | if (!rtx_equal_p (operands[0], operands[1])) | |
10584 | abort (); | |
0f40f9f7 | 10585 | return "add{l}\t{%0, %0|%0, %0}"; |
2ae0f82c | 10586 | |
e075ae69 | 10587 | case TYPE_LEA: |
0f40f9f7 | 10588 | return "#"; |
2ae0f82c | 10589 | |
e075ae69 RH |
10590 | default: |
10591 | if (REG_P (operands[2])) | |
0f40f9f7 | 10592 | return "sal{l}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
10593 | else if (GET_CODE (operands[2]) == CONST_INT |
10594 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10595 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 10596 | return "sal{l}\t%0"; |
e075ae69 | 10597 | else |
0f40f9f7 | 10598 | return "sal{l}\t{%2, %0|%0, %2}"; |
e075ae69 | 10599 | } |
0f40f9f7 | 10600 | } |
e075ae69 RH |
10601 | [(set (attr "type") |
10602 | (cond [(eq_attr "alternative" "1") | |
10603 | (const_string "lea") | |
10604 | (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10605 | (const_int 0)) | |
10606 | (match_operand 0 "register_operand" "")) | |
10607 | (match_operand 2 "const1_operand" "")) | |
10608 | (const_string "alu") | |
10609 | ] | |
6ef67412 JH |
10610 | (const_string "ishift"))) |
10611 | (set_attr "mode" "SI")]) | |
e075ae69 | 10612 | |
1c27d4b2 JH |
10613 | ;; Convert lea to the lea pattern to avoid flags dependency. |
10614 | (define_split | |
58787064 | 10615 | [(set (match_operand 0 "register_operand" "") |
7ec70495 | 10616 | (ashift (match_operand 1 "index_register_operand" "") |
ca4ae08d | 10617 | (match_operand:QI 2 "const_int_operand" ""))) |
1c27d4b2 | 10618 | (clobber (reg:CC 17))] |
abe24fb3 JH |
10619 | "reload_completed |
10620 | && true_regnum (operands[0]) != true_regnum (operands[1])" | |
58787064 | 10621 | [(const_int 0)] |
58787064 JH |
10622 | { |
10623 | rtx pat; | |
10624 | operands[0] = gen_lowpart (SImode, operands[0]); | |
10625 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
d8bf17f9 | 10626 | operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode); |
58787064 JH |
10627 | pat = gen_rtx_MULT (Pmode, operands[1], operands[2]); |
10628 | if (Pmode != SImode) | |
10629 | pat = gen_rtx_SUBREG (SImode, pat, 0); | |
10630 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat)); | |
10631 | DONE; | |
0f40f9f7 | 10632 | }) |
1c27d4b2 | 10633 | |
7ec70495 JH |
10634 | ;; Rare case of shifting RSP is handled by generating move and shift |
10635 | (define_split | |
10636 | [(set (match_operand 0 "register_operand" "") | |
10637 | (ashift (match_operand 1 "register_operand" "") | |
10638 | (match_operand:QI 2 "const_int_operand" ""))) | |
10639 | (clobber (reg:CC 17))] | |
10640 | "reload_completed | |
10641 | && true_regnum (operands[0]) != true_regnum (operands[1])" | |
10642 | [(const_int 0)] | |
10643 | { | |
10644 | rtx pat, clob; | |
10645 | emit_move_insn (operands[1], operands[0]); | |
10646 | pat = gen_rtx_SET (VOIDmode, operands[0], | |
10647 | gen_rtx_ASHIFT (GET_MODE (operands[0]), | |
10648 | operands[0], operands[2])); | |
10649 | clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG)); | |
10650 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob))); | |
10651 | DONE; | |
10652 | }) | |
10653 | ||
371bc54b JH |
10654 | (define_insn "*ashlsi3_1_zext" |
10655 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
10656 | (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r") | |
10657 | (match_operand:QI 2 "nonmemory_operand" "cI,M")))) | |
10658 | (clobber (reg:CC 17))] | |
1b0c37d7 | 10659 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)" |
371bc54b JH |
10660 | { |
10661 | switch (get_attr_type (insn)) | |
10662 | { | |
10663 | case TYPE_ALU: | |
10664 | if (operands[2] != const1_rtx) | |
10665 | abort (); | |
0f40f9f7 | 10666 | return "add{l}\t{%k0, %k0|%k0, %k0}"; |
371bc54b JH |
10667 | |
10668 | case TYPE_LEA: | |
0f40f9f7 | 10669 | return "#"; |
371bc54b JH |
10670 | |
10671 | default: | |
10672 | if (REG_P (operands[2])) | |
0f40f9f7 | 10673 | return "sal{l}\t{%b2, %k0|%k0, %b2}"; |
371bc54b JH |
10674 | else if (GET_CODE (operands[2]) == CONST_INT |
10675 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10676 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 10677 | return "sal{l}\t%k0"; |
371bc54b | 10678 | else |
0f40f9f7 | 10679 | return "sal{l}\t{%2, %k0|%k0, %2}"; |
371bc54b | 10680 | } |
0f40f9f7 | 10681 | } |
371bc54b JH |
10682 | [(set (attr "type") |
10683 | (cond [(eq_attr "alternative" "1") | |
10684 | (const_string "lea") | |
10685 | (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10686 | (const_int 0)) | |
10687 | (match_operand 2 "const1_operand" "")) | |
10688 | (const_string "alu") | |
10689 | ] | |
10690 | (const_string "ishift"))) | |
10691 | (set_attr "mode" "SI")]) | |
10692 | ||
10693 | ;; Convert lea to the lea pattern to avoid flags dependency. | |
10694 | (define_split | |
10695 | [(set (match_operand:DI 0 "register_operand" "") | |
10696 | (zero_extend:DI (ashift (match_operand 1 "register_operand" "") | |
10697 | (match_operand:QI 2 "const_int_operand" "")))) | |
10698 | (clobber (reg:CC 17))] | |
10699 | "reload_completed | |
10700 | && true_regnum (operands[0]) != true_regnum (operands[1])" | |
10701 | [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))] | |
371bc54b JH |
10702 | { |
10703 | operands[1] = gen_lowpart (Pmode, operands[1]); | |
d8bf17f9 | 10704 | operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode); |
0f40f9f7 | 10705 | }) |
371bc54b | 10706 | |
28cefcd2 BS |
10707 | ;; This pattern can't accept a variable shift count, since shifts by |
10708 | ;; zero don't affect the flags. We assume that shifts by constant | |
10709 | ;; zero are optimized away. | |
2c873473 | 10710 | (define_insn "*ashlsi3_cmp" |
16189740 RH |
10711 | [(set (reg 17) |
10712 | (compare | |
e075ae69 | 10713 | (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
794a292d | 10714 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
e075ae69 RH |
10715 | (const_int 0))) |
10716 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
10717 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 10718 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 10719 | && ix86_binary_operator_ok (ASHIFT, SImode, operands)" |
886c62d1 | 10720 | { |
e075ae69 | 10721 | switch (get_attr_type (insn)) |
886c62d1 | 10722 | { |
e075ae69 RH |
10723 | case TYPE_ALU: |
10724 | if (operands[2] != const1_rtx) | |
10725 | abort (); | |
0f40f9f7 | 10726 | return "add{l}\t{%0, %0|%0, %0}"; |
886c62d1 | 10727 | |
e075ae69 RH |
10728 | default: |
10729 | if (REG_P (operands[2])) | |
0f40f9f7 | 10730 | return "sal{l}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
10731 | else if (GET_CODE (operands[2]) == CONST_INT |
10732 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10733 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 10734 | return "sal{l}\t%0"; |
e075ae69 | 10735 | else |
0f40f9f7 | 10736 | return "sal{l}\t{%2, %0|%0, %2}"; |
56c0e8fa | 10737 | } |
0f40f9f7 | 10738 | } |
e075ae69 RH |
10739 | [(set (attr "type") |
10740 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10741 | (const_int 0)) | |
10742 | (match_operand 0 "register_operand" "")) | |
10743 | (match_operand 2 "const1_operand" "")) | |
10744 | (const_string "alu") | |
10745 | ] | |
6ef67412 JH |
10746 | (const_string "ishift"))) |
10747 | (set_attr "mode" "SI")]) | |
e075ae69 | 10748 | |
371bc54b JH |
10749 | (define_insn "*ashlsi3_cmp_zext" |
10750 | [(set (reg 17) | |
10751 | (compare | |
10752 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
794a292d | 10753 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
371bc54b JH |
10754 | (const_int 0))) |
10755 | (set (match_operand:DI 0 "register_operand" "=r") | |
10756 | (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))] | |
10757 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
10758 | && ix86_binary_operator_ok (ASHIFT, SImode, operands)" | |
371bc54b JH |
10759 | { |
10760 | switch (get_attr_type (insn)) | |
10761 | { | |
10762 | case TYPE_ALU: | |
10763 | if (operands[2] != const1_rtx) | |
10764 | abort (); | |
0f40f9f7 | 10765 | return "add{l}\t{%k0, %k0|%k0, %k0}"; |
371bc54b JH |
10766 | |
10767 | default: | |
10768 | if (REG_P (operands[2])) | |
0f40f9f7 | 10769 | return "sal{l}\t{%b2, %k0|%k0, %b2}"; |
371bc54b JH |
10770 | else if (GET_CODE (operands[2]) == CONST_INT |
10771 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10772 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 10773 | return "sal{l}\t%k0"; |
371bc54b | 10774 | else |
0f40f9f7 | 10775 | return "sal{l}\t{%2, %k0|%k0, %2}"; |
371bc54b | 10776 | } |
0f40f9f7 | 10777 | } |
371bc54b JH |
10778 | [(set (attr "type") |
10779 | (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10780 | (const_int 0)) | |
10781 | (match_operand 2 "const1_operand" "")) | |
10782 | (const_string "alu") | |
10783 | ] | |
10784 | (const_string "ishift"))) | |
10785 | (set_attr "mode" "SI")]) | |
10786 | ||
d525dfdf JH |
10787 | (define_expand "ashlhi3" |
10788 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
10789 | (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
10790 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
10791 | (clobber (reg:CC 17))] | |
d9f32422 | 10792 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
10793 | "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;") |
10794 | ||
58787064 JH |
10795 | (define_insn "*ashlhi3_1_lea" |
10796 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") | |
10797 | (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r") | |
10798 | (match_operand:QI 2 "nonmemory_operand" "cI,M"))) | |
10799 | (clobber (reg:CC 17))] | |
10800 | "!TARGET_PARTIAL_REG_STALL | |
10801 | && ix86_binary_operator_ok (ASHIFT, HImode, operands)" | |
58787064 JH |
10802 | { |
10803 | switch (get_attr_type (insn)) | |
10804 | { | |
10805 | case TYPE_LEA: | |
0f40f9f7 | 10806 | return "#"; |
58787064 JH |
10807 | case TYPE_ALU: |
10808 | if (operands[2] != const1_rtx) | |
10809 | abort (); | |
0f40f9f7 | 10810 | return "add{w}\t{%0, %0|%0, %0}"; |
58787064 JH |
10811 | |
10812 | default: | |
10813 | if (REG_P (operands[2])) | |
0f40f9f7 | 10814 | return "sal{w}\t{%b2, %0|%0, %b2}"; |
58787064 JH |
10815 | else if (GET_CODE (operands[2]) == CONST_INT |
10816 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10817 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 10818 | return "sal{w}\t%0"; |
58787064 | 10819 | else |
0f40f9f7 | 10820 | return "sal{w}\t{%2, %0|%0, %2}"; |
58787064 | 10821 | } |
0f40f9f7 | 10822 | } |
58787064 JH |
10823 | [(set (attr "type") |
10824 | (cond [(eq_attr "alternative" "1") | |
10825 | (const_string "lea") | |
10826 | (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10827 | (const_int 0)) | |
10828 | (match_operand 0 "register_operand" "")) | |
10829 | (match_operand 2 "const1_operand" "")) | |
10830 | (const_string "alu") | |
10831 | ] | |
10832 | (const_string "ishift"))) | |
10833 | (set_attr "mode" "HI,SI")]) | |
10834 | ||
d525dfdf | 10835 | (define_insn "*ashlhi3_1" |
e075ae69 RH |
10836 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
10837 | (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
10838 | (match_operand:QI 2 "nonmemory_operand" "cI"))) | |
10839 | (clobber (reg:CC 17))] | |
58787064 JH |
10840 | "TARGET_PARTIAL_REG_STALL |
10841 | && ix86_binary_operator_ok (ASHIFT, HImode, operands)" | |
56c0e8fa | 10842 | { |
e075ae69 RH |
10843 | switch (get_attr_type (insn)) |
10844 | { | |
10845 | case TYPE_ALU: | |
10846 | if (operands[2] != const1_rtx) | |
10847 | abort (); | |
0f40f9f7 | 10848 | return "add{w}\t{%0, %0|%0, %0}"; |
886c62d1 | 10849 | |
e075ae69 RH |
10850 | default: |
10851 | if (REG_P (operands[2])) | |
0f40f9f7 | 10852 | return "sal{w}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
10853 | else if (GET_CODE (operands[2]) == CONST_INT |
10854 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10855 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 10856 | return "sal{w}\t%0"; |
e075ae69 | 10857 | else |
0f40f9f7 | 10858 | return "sal{w}\t{%2, %0|%0, %2}"; |
e075ae69 | 10859 | } |
0f40f9f7 | 10860 | } |
e075ae69 RH |
10861 | [(set (attr "type") |
10862 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10863 | (const_int 0)) | |
10864 | (match_operand 0 "register_operand" "")) | |
10865 | (match_operand 2 "const1_operand" "")) | |
10866 | (const_string "alu") | |
10867 | ] | |
6ef67412 JH |
10868 | (const_string "ishift"))) |
10869 | (set_attr "mode" "HI")]) | |
bb62e19a | 10870 | |
28cefcd2 BS |
10871 | ;; This pattern can't accept a variable shift count, since shifts by |
10872 | ;; zero don't affect the flags. We assume that shifts by constant | |
10873 | ;; zero are optimized away. | |
2c873473 | 10874 | (define_insn "*ashlhi3_cmp" |
16189740 RH |
10875 | [(set (reg 17) |
10876 | (compare | |
e075ae69 | 10877 | (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
794a292d | 10878 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
e075ae69 RH |
10879 | (const_int 0))) |
10880 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
10881 | (ashift:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 10882 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 10883 | && ix86_binary_operator_ok (ASHIFT, HImode, operands)" |
886c62d1 | 10884 | { |
e075ae69 RH |
10885 | switch (get_attr_type (insn)) |
10886 | { | |
10887 | case TYPE_ALU: | |
10888 | if (operands[2] != const1_rtx) | |
10889 | abort (); | |
0f40f9f7 | 10890 | return "add{w}\t{%0, %0|%0, %0}"; |
886c62d1 | 10891 | |
e075ae69 RH |
10892 | default: |
10893 | if (REG_P (operands[2])) | |
0f40f9f7 | 10894 | return "sal{w}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
10895 | else if (GET_CODE (operands[2]) == CONST_INT |
10896 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10897 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 10898 | return "sal{w}\t%0"; |
e075ae69 | 10899 | else |
0f40f9f7 | 10900 | return "sal{w}\t{%2, %0|%0, %2}"; |
e075ae69 | 10901 | } |
0f40f9f7 | 10902 | } |
e075ae69 RH |
10903 | [(set (attr "type") |
10904 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10905 | (const_int 0)) | |
10906 | (match_operand 0 "register_operand" "")) | |
10907 | (match_operand 2 "const1_operand" "")) | |
10908 | (const_string "alu") | |
10909 | ] | |
6ef67412 JH |
10910 | (const_string "ishift"))) |
10911 | (set_attr "mode" "HI")]) | |
e075ae69 | 10912 | |
d525dfdf JH |
10913 | (define_expand "ashlqi3" |
10914 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
10915 | (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
10916 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
10917 | (clobber (reg:CC 17))] | |
d9f32422 | 10918 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
10919 | "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;") |
10920 | ||
e075ae69 | 10921 | ;; %%% Potential partial reg stall on alternative 2. What to do? |
58787064 JH |
10922 | |
10923 | (define_insn "*ashlqi3_1_lea" | |
10924 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r") | |
10925 | (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r") | |
91f9a498 | 10926 | (match_operand:QI 2 "nonmemory_operand" "cI,cI,M"))) |
58787064 JH |
10927 | (clobber (reg:CC 17))] |
10928 | "!TARGET_PARTIAL_REG_STALL | |
10929 | && ix86_binary_operator_ok (ASHIFT, QImode, operands)" | |
58787064 JH |
10930 | { |
10931 | switch (get_attr_type (insn)) | |
10932 | { | |
10933 | case TYPE_LEA: | |
0f40f9f7 | 10934 | return "#"; |
58787064 JH |
10935 | case TYPE_ALU: |
10936 | if (operands[2] != const1_rtx) | |
10937 | abort (); | |
1a06f5fe | 10938 | if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1])) |
0f40f9f7 | 10939 | return "add{l}\t{%k0, %k0|%k0, %k0}"; |
58787064 | 10940 | else |
0f40f9f7 | 10941 | return "add{b}\t{%0, %0|%0, %0}"; |
58787064 JH |
10942 | |
10943 | default: | |
10944 | if (REG_P (operands[2])) | |
10945 | { | |
10946 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 10947 | return "sal{l}\t{%b2, %k0|%k0, %b2}"; |
58787064 | 10948 | else |
0f40f9f7 | 10949 | return "sal{b}\t{%b2, %0|%0, %b2}"; |
58787064 JH |
10950 | } |
10951 | else if (GET_CODE (operands[2]) == CONST_INT | |
10952 | && INTVAL (operands[2]) == 1 | |
495333a6 | 10953 | && (TARGET_SHIFT1 || optimize_size)) |
58787064 JH |
10954 | { |
10955 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 10956 | return "sal{l}\t%0"; |
58787064 | 10957 | else |
0f40f9f7 | 10958 | return "sal{b}\t%0"; |
58787064 JH |
10959 | } |
10960 | else | |
10961 | { | |
10962 | if (get_attr_mode (insn) == MODE_SI) | |
0f40f9f7 | 10963 | return "sal{l}\t{%2, %k0|%k0, %2}"; |
58787064 | 10964 | else |
0f40f9f7 | 10965 | return "sal{b}\t{%2, %0|%0, %2}"; |
58787064 JH |
10966 | } |
10967 | } | |
0f40f9f7 | 10968 | } |
58787064 JH |
10969 | [(set (attr "type") |
10970 | (cond [(eq_attr "alternative" "2") | |
10971 | (const_string "lea") | |
10972 | (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
10973 | (const_int 0)) | |
10974 | (match_operand 0 "register_operand" "")) | |
10975 | (match_operand 2 "const1_operand" "")) | |
10976 | (const_string "alu") | |
10977 | ] | |
10978 | (const_string "ishift"))) | |
10979 | (set_attr "mode" "QI,SI,SI")]) | |
10980 | ||
d525dfdf JH |
10981 | (define_insn "*ashlqi3_1" |
10982 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r") | |
e075ae69 RH |
10983 | (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") |
10984 | (match_operand:QI 2 "nonmemory_operand" "cI,cI"))) | |
10985 | (clobber (reg:CC 17))] | |
58787064 JH |
10986 | "TARGET_PARTIAL_REG_STALL |
10987 | && ix86_binary_operator_ok (ASHIFT, QImode, operands)" | |
886c62d1 | 10988 | { |
e075ae69 RH |
10989 | switch (get_attr_type (insn)) |
10990 | { | |
10991 | case TYPE_ALU: | |
10992 | if (operands[2] != const1_rtx) | |
10993 | abort (); | |
1a06f5fe | 10994 | if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1])) |
0f40f9f7 | 10995 | return "add{l}\t{%k0, %k0|%k0, %k0}"; |
e075ae69 | 10996 | else |
0f40f9f7 | 10997 | return "add{b}\t{%0, %0|%0, %0}"; |
886c62d1 | 10998 | |
e075ae69 RH |
10999 | default: |
11000 | if (REG_P (operands[2])) | |
11001 | { | |
1a06f5fe | 11002 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 11003 | return "sal{l}\t{%b2, %k0|%k0, %b2}"; |
e075ae69 | 11004 | else |
0f40f9f7 | 11005 | return "sal{b}\t{%b2, %0|%0, %b2}"; |
e075ae69 | 11006 | } |
8bad7136 JL |
11007 | else if (GET_CODE (operands[2]) == CONST_INT |
11008 | && INTVAL (operands[2]) == 1 | |
495333a6 | 11009 | && (TARGET_SHIFT1 || optimize_size)) |
8bad7136 | 11010 | { |
1a06f5fe | 11011 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 11012 | return "sal{l}\t%0"; |
8bad7136 | 11013 | else |
0f40f9f7 | 11014 | return "sal{b}\t%0"; |
8bad7136 | 11015 | } |
e075ae69 RH |
11016 | else |
11017 | { | |
1a06f5fe | 11018 | if (get_attr_mode (insn) == MODE_SI) |
0f40f9f7 | 11019 | return "sal{l}\t{%2, %k0|%k0, %2}"; |
e075ae69 | 11020 | else |
0f40f9f7 | 11021 | return "sal{b}\t{%2, %0|%0, %2}"; |
e075ae69 RH |
11022 | } |
11023 | } | |
0f40f9f7 | 11024 | } |
e075ae69 RH |
11025 | [(set (attr "type") |
11026 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
11027 | (const_int 0)) | |
11028 | (match_operand 0 "register_operand" "")) | |
11029 | (match_operand 2 "const1_operand" "")) | |
11030 | (const_string "alu") | |
11031 | ] | |
6ef67412 JH |
11032 | (const_string "ishift"))) |
11033 | (set_attr "mode" "QI,SI")]) | |
e075ae69 | 11034 | |
28cefcd2 BS |
11035 | ;; This pattern can't accept a variable shift count, since shifts by |
11036 | ;; zero don't affect the flags. We assume that shifts by constant | |
11037 | ;; zero are optimized away. | |
2c873473 | 11038 | (define_insn "*ashlqi3_cmp" |
16189740 RH |
11039 | [(set (reg 17) |
11040 | (compare | |
e075ae69 | 11041 | (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
794a292d | 11042 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
e075ae69 RH |
11043 | (const_int 0))) |
11044 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
11045 | (ashift:QI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 11046 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11047 | && ix86_binary_operator_ok (ASHIFT, QImode, operands)" |
886c62d1 | 11048 | { |
e075ae69 RH |
11049 | switch (get_attr_type (insn)) |
11050 | { | |
11051 | case TYPE_ALU: | |
11052 | if (operands[2] != const1_rtx) | |
11053 | abort (); | |
0f40f9f7 | 11054 | return "add{b}\t{%0, %0|%0, %0}"; |
e075ae69 RH |
11055 | |
11056 | default: | |
11057 | if (REG_P (operands[2])) | |
0f40f9f7 | 11058 | return "sal{b}\t{%b2, %0|%0, %b2}"; |
8bad7136 JL |
11059 | else if (GET_CODE (operands[2]) == CONST_INT |
11060 | && INTVAL (operands[2]) == 1 | |
495333a6 | 11061 | && (TARGET_SHIFT1 || optimize_size)) |
0f40f9f7 | 11062 | return "sal{b}\t%0"; |
e075ae69 | 11063 | else |
0f40f9f7 | 11064 | return "sal{b}\t{%2, %0|%0, %2}"; |
e075ae69 | 11065 | } |
0f40f9f7 | 11066 | } |
e075ae69 RH |
11067 | [(set (attr "type") |
11068 | (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD") | |
11069 | (const_int 0)) | |
11070 | (match_operand 0 "register_operand" "")) | |
11071 | (match_operand 2 "const1_operand" "")) | |
11072 | (const_string "alu") | |
11073 | ] | |
6ef67412 JH |
11074 | (const_string "ishift"))) |
11075 | (set_attr "mode" "QI")]) | |
886c62d1 JVA |
11076 | |
11077 | ;; See comment above `ashldi3' about how this works. | |
11078 | ||
e075ae69 | 11079 | (define_expand "ashrdi3" |
371bc54b JH |
11080 | [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") |
11081 | (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") | |
11082 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
e075ae69 | 11083 | (clobber (reg:CC 17))])] |
56c0e8fa | 11084 | "" |
56c0e8fa | 11085 | { |
371bc54b | 11086 | if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) |
56c0e8fa | 11087 | { |
e075ae69 RH |
11088 | emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2])); |
11089 | DONE; | |
56c0e8fa | 11090 | } |
371bc54b JH |
11091 | ix86_expand_binary_operator (ASHIFTRT, DImode, operands); |
11092 | DONE; | |
0f40f9f7 | 11093 | }) |
2ae0f82c | 11094 | |
371bc54b JH |
11095 | (define_insn "ashrdi3_63_rex64" |
11096 | [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm") | |
11097 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0") | |
11098 | (match_operand:DI 2 "const_int_operand" "i,i"))) | |
11099 | (clobber (reg:CC 17))] | |
11100 | "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size) | |
11101 | && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" | |
11102 | "@ | |
11103 | {cqto|cqo} | |
0f40f9f7 | 11104 | sar{q}\t{%2, %0|%0, %2}" |
371bc54b JH |
11105 | [(set_attr "type" "imovx,ishift") |
11106 | (set_attr "prefix_0f" "0,*") | |
11107 | (set_attr "length_immediate" "0,*") | |
11108 | (set_attr "modrm" "0,1") | |
11109 | (set_attr "mode" "DI")]) | |
11110 | ||
11111 | (define_insn "*ashrdi3_1_one_bit_rex64" | |
11112 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11113 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11114 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11115 | (clobber (reg:CC 17))] | |
11116 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands) | |
495333a6 | 11117 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11118 | "sar{q}\t%0" |
371bc54b JH |
11119 | [(set_attr "type" "ishift") |
11120 | (set (attr "length") | |
11121 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
11122 | (const_string "2") | |
11123 | (const_string "*")))]) | |
11124 | ||
11125 | (define_insn "*ashrdi3_1_rex64" | |
11126 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") | |
11127 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
7c17f553 | 11128 | (match_operand:QI 2 "nonmemory_operand" "J,c"))) |
371bc54b JH |
11129 | (clobber (reg:CC 17))] |
11130 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" | |
11131 | "@ | |
0f40f9f7 ZW |
11132 | sar{q}\t{%2, %0|%0, %2} |
11133 | sar{q}\t{%b2, %0|%0, %b2}" | |
371bc54b JH |
11134 | [(set_attr "type" "ishift") |
11135 | (set_attr "mode" "DI")]) | |
11136 | ||
11137 | ;; This pattern can't accept a variable shift count, since shifts by | |
11138 | ;; zero don't affect the flags. We assume that shifts by constant | |
11139 | ;; zero are optimized away. | |
11140 | (define_insn "*ashrdi3_one_bit_cmp_rex64" | |
11141 | [(set (reg 17) | |
11142 | (compare | |
11143 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11144 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11145 | (const_int 0))) | |
11146 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11147 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
11148 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
495333a6 | 11149 | && (TARGET_SHIFT1 || optimize_size) |
371bc54b | 11150 | && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" |
0f40f9f7 | 11151 | "sar{q}\t%0" |
371bc54b JH |
11152 | [(set_attr "type" "ishift") |
11153 | (set (attr "length") | |
11154 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
11155 | (const_string "2") | |
11156 | (const_string "*")))]) | |
11157 | ||
11158 | ;; This pattern can't accept a variable shift count, since shifts by | |
11159 | ;; zero don't affect the flags. We assume that shifts by constant | |
11160 | ;; zero are optimized away. | |
11161 | (define_insn "*ashrdi3_cmp_rex64" | |
11162 | [(set (reg 17) | |
11163 | (compare | |
11164 | (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11165 | (match_operand:QI 2 "const_int_operand" "n")) | |
11166 | (const_int 0))) | |
11167 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11168 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
11169 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11170 | && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" | |
0f40f9f7 | 11171 | "sar{q}\t{%2, %0|%0, %2}" |
371bc54b JH |
11172 | [(set_attr "type" "ishift") |
11173 | (set_attr "mode" "DI")]) | |
11174 | ||
11175 | ||
e075ae69 RH |
11176 | (define_insn "ashrdi3_1" |
11177 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11178 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
11179 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) | |
11180 | (clobber (match_scratch:SI 3 "=&r")) | |
11181 | (clobber (reg:CC 17))] | |
371bc54b | 11182 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 RH |
11183 | "#" |
11184 | [(set_attr "type" "multi")]) | |
886c62d1 | 11185 | |
e075ae69 RH |
11186 | (define_insn "*ashrdi3_2" |
11187 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11188 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
11189 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) | |
11190 | (clobber (reg:CC 17))] | |
371bc54b | 11191 | "!TARGET_64BIT" |
e075ae69 RH |
11192 | "#" |
11193 | [(set_attr "type" "multi")]) | |
886c62d1 | 11194 | |
e075ae69 RH |
11195 | (define_split |
11196 | [(set (match_operand:DI 0 "register_operand" "") | |
11197 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
11198 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11199 | (clobber (match_scratch:SI 3 "")) | |
11200 | (clobber (reg:CC 17))] | |
371bc54b | 11201 | "!TARGET_64BIT && TARGET_CMOVE && reload_completed" |
e075ae69 RH |
11202 | [(const_int 0)] |
11203 | "ix86_split_ashrdi (operands, operands[3]); DONE;") | |
886c62d1 | 11204 | |
e075ae69 RH |
11205 | (define_split |
11206 | [(set (match_operand:DI 0 "register_operand" "") | |
11207 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
11208 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11209 | (clobber (reg:CC 17))] | |
371bc54b | 11210 | "!TARGET_64BIT && reload_completed" |
e075ae69 RH |
11211 | [(const_int 0)] |
11212 | "ix86_split_ashrdi (operands, NULL_RTX); DONE;") | |
886c62d1 | 11213 | |
e075ae69 RH |
11214 | (define_insn "x86_shrd_1" |
11215 | [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m") | |
11216 | (ior:SI (ashiftrt:SI (match_dup 0) | |
11217 | (match_operand:QI 2 "nonmemory_operand" "I,c")) | |
11218 | (ashift:SI (match_operand:SI 1 "register_operand" "r,r") | |
11219 | (minus:QI (const_int 32) (match_dup 2))))) | |
11220 | (clobber (reg:CC 17))] | |
886c62d1 | 11221 | "" |
e075ae69 | 11222 | "@ |
0f40f9f7 ZW |
11223 | shrd{l}\t{%2, %1, %0|%0, %1, %2} |
11224 | shrd{l}\t{%s2%1, %0|%0, %1, %2}" | |
e075ae69 | 11225 | [(set_attr "type" "ishift") |
6ef67412 | 11226 | (set_attr "prefix_0f" "1") |
e075ae69 | 11227 | (set_attr "pent_pair" "np") |
6ef67412 JH |
11228 | (set_attr "ppro_uops" "few") |
11229 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
11230 | |
11231 | (define_expand "x86_shift_adj_3" | |
11232 | [(use (match_operand:SI 0 "register_operand" "")) | |
11233 | (use (match_operand:SI 1 "register_operand" "")) | |
11234 | (use (match_operand:QI 2 "register_operand" ""))] | |
11235 | "" | |
886c62d1 | 11236 | { |
e075ae69 RH |
11237 | rtx label = gen_label_rtx (); |
11238 | rtx tmp; | |
11239 | ||
16189740 | 11240 | emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32))); |
e075ae69 | 11241 | |
16189740 | 11242 | tmp = gen_rtx_REG (CCZmode, FLAGS_REG); |
e075ae69 RH |
11243 | tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); |
11244 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
11245 | gen_rtx_LABEL_REF (VOIDmode, label), | |
11246 | pc_rtx); | |
11247 | tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
11248 | JUMP_LABEL (tmp) = label; | |
11249 | ||
11250 | emit_move_insn (operands[0], operands[1]); | |
11251 | emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31))); | |
11252 | ||
11253 | emit_label (label); | |
11254 | LABEL_NUSES (label) = 1; | |
11255 | ||
11256 | DONE; | |
0f40f9f7 | 11257 | }) |
886c62d1 | 11258 | |
e075ae69 RH |
11259 | (define_insn "ashrsi3_31" |
11260 | [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm") | |
11261 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0") | |
11262 | (match_operand:SI 2 "const_int_operand" "i,i"))) | |
11263 | (clobber (reg:CC 17))] | |
d525dfdf JH |
11264 | "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size) |
11265 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
e075ae69 RH |
11266 | "@ |
11267 | {cltd|cdq} | |
0f40f9f7 | 11268 | sar{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11269 | [(set_attr "type" "imovx,ishift") |
11270 | (set_attr "prefix_0f" "0,*") | |
11271 | (set_attr "length_immediate" "0,*") | |
11272 | (set_attr "modrm" "0,1") | |
11273 | (set_attr "mode" "SI")]) | |
e075ae69 | 11274 | |
371bc54b JH |
11275 | (define_insn "*ashrsi3_31_zext" |
11276 | [(set (match_operand:DI 0 "register_operand" "=*d,r") | |
11277 | (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0") | |
11278 | (match_operand:SI 2 "const_int_operand" "i,i")))) | |
11279 | (clobber (reg:CC 17))] | |
1b0c37d7 ZW |
11280 | "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size) |
11281 | && INTVAL (operands[2]) == 31 | |
11282 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
371bc54b JH |
11283 | "@ |
11284 | {cltd|cdq} | |
0f40f9f7 | 11285 | sar{l}\t{%2, %k0|%k0, %2}" |
371bc54b JH |
11286 | [(set_attr "type" "imovx,ishift") |
11287 | (set_attr "prefix_0f" "0,*") | |
11288 | (set_attr "length_immediate" "0,*") | |
11289 | (set_attr "modrm" "0,1") | |
11290 | (set_attr "mode" "SI")]) | |
11291 | ||
d525dfdf JH |
11292 | (define_expand "ashrsi3" |
11293 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
155d8a47 | 11294 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") |
d525dfdf JH |
11295 | (match_operand:QI 2 "nonmemory_operand" ""))) |
11296 | (clobber (reg:CC 17))] | |
11297 | "" | |
11298 | "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;") | |
11299 | ||
8bad7136 JL |
11300 | (define_insn "*ashrsi3_1_one_bit" |
11301 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
11302 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
11303 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11304 | (clobber (reg:CC 17))] | |
11305 | "ix86_binary_operator_ok (ASHIFTRT, SImode, operands) | |
495333a6 | 11306 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11307 | "sar{l}\t%0" |
8bad7136 JL |
11308 | [(set_attr "type" "ishift") |
11309 | (set (attr "length") | |
11310 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11311 | (const_string "2") | |
11312 | (const_string "*")))]) | |
11313 | ||
371bc54b JH |
11314 | (define_insn "*ashrsi3_1_one_bit_zext" |
11315 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11316 | (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
11317 | (match_operand:QI 2 "const_int_1_operand" "")))) | |
11318 | (clobber (reg:CC 17))] | |
11319 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands) | |
495333a6 | 11320 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11321 | "sar{l}\t%k0" |
371bc54b JH |
11322 | [(set_attr "type" "ishift") |
11323 | (set_attr "length" "2")]) | |
11324 | ||
d525dfdf | 11325 | (define_insn "*ashrsi3_1" |
e075ae69 RH |
11326 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") |
11327 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
11328 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11329 | (clobber (reg:CC 17))] | |
d525dfdf | 11330 | "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" |
e075ae69 | 11331 | "@ |
0f40f9f7 ZW |
11332 | sar{l}\t{%2, %0|%0, %2} |
11333 | sar{l}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11334 | [(set_attr "type" "ishift") |
11335 | (set_attr "mode" "SI")]) | |
886c62d1 | 11336 | |
371bc54b JH |
11337 | (define_insn "*ashrsi3_1_zext" |
11338 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
11339 | (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
11340 | (match_operand:QI 2 "nonmemory_operand" "I,c")))) | |
11341 | (clobber (reg:CC 17))] | |
11342 | "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
11343 | "@ | |
0f40f9f7 ZW |
11344 | sar{l}\t{%2, %k0|%k0, %2} |
11345 | sar{l}\t{%b2, %k0|%k0, %b2}" | |
371bc54b JH |
11346 | [(set_attr "type" "ishift") |
11347 | (set_attr "mode" "SI")]) | |
11348 | ||
8bad7136 JL |
11349 | ;; This pattern can't accept a variable shift count, since shifts by |
11350 | ;; zero don't affect the flags. We assume that shifts by constant | |
11351 | ;; zero are optimized away. | |
2c873473 | 11352 | (define_insn "*ashrsi3_one_bit_cmp" |
8bad7136 JL |
11353 | [(set (reg 17) |
11354 | (compare | |
11355 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
11356 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11357 | (const_int 0))) | |
11358 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
11359 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
2c873473 | 11360 | "ix86_match_ccmode (insn, CCGOCmode) |
495333a6 | 11361 | && (TARGET_SHIFT1 || optimize_size) |
8bad7136 | 11362 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" |
0f40f9f7 | 11363 | "sar{l}\t%0" |
8bad7136 JL |
11364 | [(set_attr "type" "ishift") |
11365 | (set (attr "length") | |
11366 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11367 | (const_string "2") | |
11368 | (const_string "*")))]) | |
11369 | ||
371bc54b JH |
11370 | (define_insn "*ashrsi3_one_bit_cmp_zext" |
11371 | [(set (reg 17) | |
11372 | (compare | |
11373 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
11374 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11375 | (const_int 0))) | |
11376 | (set (match_operand:DI 0 "register_operand" "=r") | |
11377 | (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] | |
11378 | "TARGET_64BIT && ix86_match_ccmode (insn, CCmode) | |
495333a6 | 11379 | && (TARGET_SHIFT1 || optimize_size) |
371bc54b | 11380 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" |
0f40f9f7 | 11381 | "sar{l}\t%k0" |
371bc54b JH |
11382 | [(set_attr "type" "ishift") |
11383 | (set_attr "length" "2")]) | |
11384 | ||
28cefcd2 BS |
11385 | ;; This pattern can't accept a variable shift count, since shifts by |
11386 | ;; zero don't affect the flags. We assume that shifts by constant | |
11387 | ;; zero are optimized away. | |
2c873473 | 11388 | (define_insn "*ashrsi3_cmp" |
16189740 RH |
11389 | [(set (reg 17) |
11390 | (compare | |
28cefcd2 | 11391 | (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
794a292d | 11392 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
e075ae69 | 11393 | (const_int 0))) |
28cefcd2 | 11394 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
e075ae69 | 11395 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
2c873473 | 11396 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11397 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" |
0f40f9f7 | 11398 | "sar{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11399 | [(set_attr "type" "ishift") |
11400 | (set_attr "mode" "SI")]) | |
886c62d1 | 11401 | |
371bc54b JH |
11402 | (define_insn "*ashrsi3_cmp_zext" |
11403 | [(set (reg 17) | |
11404 | (compare | |
11405 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
794a292d | 11406 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
371bc54b JH |
11407 | (const_int 0))) |
11408 | (set (match_operand:DI 0 "register_operand" "=r") | |
11409 | (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] | |
11410 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11411 | && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" | |
0f40f9f7 | 11412 | "sar{l}\t{%2, %k0|%k0, %2}" |
371bc54b JH |
11413 | [(set_attr "type" "ishift") |
11414 | (set_attr "mode" "SI")]) | |
11415 | ||
d525dfdf JH |
11416 | (define_expand "ashrhi3" |
11417 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
155d8a47 | 11418 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "") |
d525dfdf JH |
11419 | (match_operand:QI 2 "nonmemory_operand" ""))) |
11420 | (clobber (reg:CC 17))] | |
d9f32422 | 11421 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
11422 | "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;") |
11423 | ||
8bad7136 JL |
11424 | (define_insn "*ashrhi3_1_one_bit" |
11425 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
11426 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
11427 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11428 | (clobber (reg:CC 17))] | |
11429 | "ix86_binary_operator_ok (ASHIFTRT, HImode, operands) | |
495333a6 | 11430 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11431 | "sar{w}\t%0" |
8bad7136 JL |
11432 | [(set_attr "type" "ishift") |
11433 | (set (attr "length") | |
3d117b30 | 11434 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11435 | (const_string "2") |
11436 | (const_string "*")))]) | |
11437 | ||
d525dfdf | 11438 | (define_insn "*ashrhi3_1" |
e075ae69 RH |
11439 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") |
11440 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
11441 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11442 | (clobber (reg:CC 17))] | |
d525dfdf | 11443 | "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" |
e075ae69 | 11444 | "@ |
0f40f9f7 ZW |
11445 | sar{w}\t{%2, %0|%0, %2} |
11446 | sar{w}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11447 | [(set_attr "type" "ishift") |
11448 | (set_attr "mode" "HI")]) | |
886c62d1 | 11449 | |
8bad7136 JL |
11450 | ;; This pattern can't accept a variable shift count, since shifts by |
11451 | ;; zero don't affect the flags. We assume that shifts by constant | |
11452 | ;; zero are optimized away. | |
2c873473 | 11453 | (define_insn "*ashrhi3_one_bit_cmp" |
8bad7136 JL |
11454 | [(set (reg 17) |
11455 | (compare | |
11456 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
11457 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11458 | (const_int 0))) | |
11459 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
11460 | (ashiftrt:HI (match_dup 1) (match_dup 2)))] | |
2c873473 | 11461 | "ix86_match_ccmode (insn, CCGOCmode) |
495333a6 | 11462 | && (TARGET_SHIFT1 || optimize_size) |
8bad7136 | 11463 | && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" |
0f40f9f7 | 11464 | "sar{w}\t%0" |
8bad7136 JL |
11465 | [(set_attr "type" "ishift") |
11466 | (set (attr "length") | |
3d117b30 | 11467 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11468 | (const_string "2") |
11469 | (const_string "*")))]) | |
11470 | ||
28cefcd2 BS |
11471 | ;; This pattern can't accept a variable shift count, since shifts by |
11472 | ;; zero don't affect the flags. We assume that shifts by constant | |
11473 | ;; zero are optimized away. | |
2c873473 | 11474 | (define_insn "*ashrhi3_cmp" |
16189740 RH |
11475 | [(set (reg 17) |
11476 | (compare | |
28cefcd2 | 11477 | (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
794a292d | 11478 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
e075ae69 | 11479 | (const_int 0))) |
28cefcd2 | 11480 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
e075ae69 | 11481 | (ashiftrt:HI (match_dup 1) (match_dup 2)))] |
2c873473 | 11482 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11483 | && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" |
0f40f9f7 | 11484 | "sar{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11485 | [(set_attr "type" "ishift") |
11486 | (set_attr "mode" "HI")]) | |
886c62d1 | 11487 | |
d525dfdf JH |
11488 | (define_expand "ashrqi3" |
11489 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
155d8a47 | 11490 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "") |
d525dfdf JH |
11491 | (match_operand:QI 2 "nonmemory_operand" ""))) |
11492 | (clobber (reg:CC 17))] | |
d9f32422 | 11493 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
11494 | "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;") |
11495 | ||
8bad7136 JL |
11496 | (define_insn "*ashrqi3_1_one_bit" |
11497 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
11498 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
11499 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11500 | (clobber (reg:CC 17))] | |
11501 | "ix86_binary_operator_ok (ASHIFTRT, QImode, operands) | |
495333a6 | 11502 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11503 | "sar{b}\t%0" |
8bad7136 JL |
11504 | [(set_attr "type" "ishift") |
11505 | (set (attr "length") | |
3d117b30 | 11506 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11507 | (const_string "2") |
11508 | (const_string "*")))]) | |
11509 | ||
2f41793e JH |
11510 | (define_insn "*ashrqi3_1_one_bit_slp" |
11511 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) | |
11512 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
11513 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11514 | (clobber (reg:CC 17))] | |
11515 | "ix86_binary_operator_ok (ASHIFTRT, QImode, operands) | |
11516 | && (! TARGET_PARTIAL_REG_STALL || optimize_size) | |
495333a6 | 11517 | && (TARGET_SHIFT1 || optimize_size)" |
2f41793e JH |
11518 | "sar{b}\t%0" |
11519 | [(set_attr "type" "ishift") | |
11520 | (set (attr "length") | |
11521 | (if_then_else (match_operand 0 "register_operand" "") | |
11522 | (const_string "2") | |
11523 | (const_string "*")))]) | |
11524 | ||
d525dfdf | 11525 | (define_insn "*ashrqi3_1" |
e075ae69 RH |
11526 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") |
11527 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
11528 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11529 | (clobber (reg:CC 17))] | |
d525dfdf | 11530 | "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" |
e075ae69 | 11531 | "@ |
0f40f9f7 ZW |
11532 | sar{b}\t{%2, %0|%0, %2} |
11533 | sar{b}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11534 | [(set_attr "type" "ishift") |
11535 | (set_attr "mode" "QI")]) | |
886c62d1 | 11536 | |
2f41793e JH |
11537 | (define_insn "*ashrqi3_1_slp" |
11538 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) | |
11539 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
11540 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11541 | (clobber (reg:CC 17))] | |
11542 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
11543 | && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" | |
11544 | "@ | |
11545 | sar{b}\t{%2, %0|%0, %2} | |
11546 | sar{b}\t{%b2, %0|%0, %b2}" | |
11547 | [(set_attr "type" "ishift") | |
11548 | (set_attr "mode" "QI")]) | |
11549 | ||
8bad7136 JL |
11550 | ;; This pattern can't accept a variable shift count, since shifts by |
11551 | ;; zero don't affect the flags. We assume that shifts by constant | |
11552 | ;; zero are optimized away. | |
2c873473 | 11553 | (define_insn "*ashrqi3_one_bit_cmp" |
8bad7136 JL |
11554 | [(set (reg 17) |
11555 | (compare | |
11556 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
11557 | (match_operand:QI 2 "const_int_1_operand" "I")) | |
11558 | (const_int 0))) | |
5f90a099 | 11559 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
8bad7136 | 11560 | (ashiftrt:QI (match_dup 1) (match_dup 2)))] |
2c873473 | 11561 | "ix86_match_ccmode (insn, CCGOCmode) |
495333a6 | 11562 | && (TARGET_SHIFT1 || optimize_size) |
8bad7136 | 11563 | && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" |
0f40f9f7 | 11564 | "sar{b}\t%0" |
8bad7136 JL |
11565 | [(set_attr "type" "ishift") |
11566 | (set (attr "length") | |
3d117b30 | 11567 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11568 | (const_string "2") |
11569 | (const_string "*")))]) | |
11570 | ||
28cefcd2 BS |
11571 | ;; This pattern can't accept a variable shift count, since shifts by |
11572 | ;; zero don't affect the flags. We assume that shifts by constant | |
11573 | ;; zero are optimized away. | |
2c873473 | 11574 | (define_insn "*ashrqi3_cmp" |
16189740 RH |
11575 | [(set (reg 17) |
11576 | (compare | |
28cefcd2 | 11577 | (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
794a292d | 11578 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
e075ae69 | 11579 | (const_int 0))) |
5f90a099 | 11580 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
e075ae69 | 11581 | (ashiftrt:QI (match_dup 1) (match_dup 2)))] |
2c873473 | 11582 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11583 | && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" |
0f40f9f7 | 11584 | "sar{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11585 | [(set_attr "type" "ishift") |
11586 | (set_attr "mode" "QI")]) | |
886c62d1 | 11587 | \f |
e075ae69 RH |
11588 | ;; Logical shift instructions |
11589 | ||
11590 | ;; See comment above `ashldi3' about how this works. | |
11591 | ||
11592 | (define_expand "lshrdi3" | |
371bc54b JH |
11593 | [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") |
11594 | (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") | |
11595 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
e075ae69 | 11596 | (clobber (reg:CC 17))])] |
886c62d1 | 11597 | "" |
886c62d1 | 11598 | { |
371bc54b | 11599 | if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) |
886c62d1 | 11600 | { |
e075ae69 RH |
11601 | emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2])); |
11602 | DONE; | |
886c62d1 | 11603 | } |
371bc54b JH |
11604 | ix86_expand_binary_operator (LSHIFTRT, DImode, operands); |
11605 | DONE; | |
0f40f9f7 | 11606 | }) |
886c62d1 | 11607 | |
371bc54b JH |
11608 | (define_insn "*lshrdi3_1_one_bit_rex64" |
11609 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11610 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11611 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11612 | (clobber (reg:CC 17))] | |
11613 | "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) | |
495333a6 | 11614 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11615 | "shr{q}\t%0" |
371bc54b JH |
11616 | [(set_attr "type" "ishift") |
11617 | (set (attr "length") | |
11618 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
11619 | (const_string "2") | |
11620 | (const_string "*")))]) | |
11621 | ||
11622 | (define_insn "*lshrdi3_1_rex64" | |
11623 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") | |
11624 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
11625 | (match_operand:QI 2 "nonmemory_operand" "J,c"))) | |
11626 | (clobber (reg:CC 17))] | |
11627 | "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
11628 | "@ | |
0f40f9f7 ZW |
11629 | shr{q}\t{%2, %0|%0, %2} |
11630 | shr{q}\t{%b2, %0|%0, %b2}" | |
371bc54b JH |
11631 | [(set_attr "type" "ishift") |
11632 | (set_attr "mode" "DI")]) | |
11633 | ||
11634 | ;; This pattern can't accept a variable shift count, since shifts by | |
11635 | ;; zero don't affect the flags. We assume that shifts by constant | |
11636 | ;; zero are optimized away. | |
11637 | (define_insn "*lshrdi3_cmp_one_bit_rex64" | |
11638 | [(set (reg 17) | |
11639 | (compare | |
11640 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11641 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11642 | (const_int 0))) | |
11643 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11644 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
11645 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
495333a6 | 11646 | && (TARGET_SHIFT1 || optimize_size) |
371bc54b | 11647 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
0f40f9f7 | 11648 | "shr{q}\t%0" |
371bc54b JH |
11649 | [(set_attr "type" "ishift") |
11650 | (set (attr "length") | |
11651 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
11652 | (const_string "2") | |
11653 | (const_string "*")))]) | |
11654 | ||
11655 | ;; This pattern can't accept a variable shift count, since shifts by | |
11656 | ;; zero don't affect the flags. We assume that shifts by constant | |
11657 | ;; zero are optimized away. | |
11658 | (define_insn "*lshrdi3_cmp_rex64" | |
11659 | [(set (reg 17) | |
11660 | (compare | |
11661 | (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
11662 | (match_operand:QI 2 "const_int_operand" "e")) | |
11663 | (const_int 0))) | |
11664 | (set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
11665 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
11666 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11667 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
0f40f9f7 | 11668 | "shr{q}\t{%2, %0|%0, %2}" |
371bc54b JH |
11669 | [(set_attr "type" "ishift") |
11670 | (set_attr "mode" "DI")]) | |
11671 | ||
e075ae69 RH |
11672 | (define_insn "lshrdi3_1" |
11673 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11674 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
11675 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) | |
11676 | (clobber (match_scratch:SI 3 "=&r")) | |
11677 | (clobber (reg:CC 17))] | |
1e07edd3 | 11678 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 RH |
11679 | "#" |
11680 | [(set_attr "type" "multi")]) | |
886c62d1 | 11681 | |
e075ae69 RH |
11682 | (define_insn "*lshrdi3_2" |
11683 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11684 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
11685 | (match_operand:QI 2 "nonmemory_operand" "Jc"))) | |
11686 | (clobber (reg:CC 17))] | |
1e07edd3 | 11687 | "!TARGET_64BIT" |
e075ae69 RH |
11688 | "#" |
11689 | [(set_attr "type" "multi")]) | |
886c62d1 | 11690 | |
e075ae69 RH |
11691 | (define_split |
11692 | [(set (match_operand:DI 0 "register_operand" "") | |
11693 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
11694 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11695 | (clobber (match_scratch:SI 3 "")) | |
11696 | (clobber (reg:CC 17))] | |
1e07edd3 | 11697 | "!TARGET_64BIT && TARGET_CMOVE && reload_completed" |
e075ae69 RH |
11698 | [(const_int 0)] |
11699 | "ix86_split_lshrdi (operands, operands[3]); DONE;") | |
886c62d1 | 11700 | |
e075ae69 RH |
11701 | (define_split |
11702 | [(set (match_operand:DI 0 "register_operand" "") | |
11703 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
11704 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11705 | (clobber (reg:CC 17))] | |
1e07edd3 | 11706 | "!TARGET_64BIT && reload_completed" |
e075ae69 RH |
11707 | [(const_int 0)] |
11708 | "ix86_split_lshrdi (operands, NULL_RTX); DONE;") | |
886c62d1 | 11709 | |
d525dfdf JH |
11710 | (define_expand "lshrsi3" |
11711 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
11712 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
11713 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11714 | (clobber (reg:CC 17))] | |
11715 | "" | |
11716 | "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;") | |
11717 | ||
8bad7136 JL |
11718 | (define_insn "*lshrsi3_1_one_bit" |
11719 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
11720 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
11721 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11722 | (clobber (reg:CC 17))] | |
11723 | "ix86_binary_operator_ok (LSHIFTRT, HImode, operands) | |
495333a6 | 11724 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11725 | "shr{l}\t%0" |
8bad7136 JL |
11726 | [(set_attr "type" "ishift") |
11727 | (set (attr "length") | |
11728 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11729 | (const_string "2") | |
11730 | (const_string "*")))]) | |
11731 | ||
371bc54b JH |
11732 | (define_insn "*lshrsi3_1_one_bit_zext" |
11733 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11734 | (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0")) | |
11735 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11736 | (clobber (reg:CC 17))] | |
11737 | "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) | |
495333a6 | 11738 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11739 | "shr{l}\t%k0" |
371bc54b JH |
11740 | [(set_attr "type" "ishift") |
11741 | (set_attr "length" "2")]) | |
11742 | ||
d525dfdf | 11743 | (define_insn "*lshrsi3_1" |
e075ae69 RH |
11744 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") |
11745 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
11746 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11747 | (clobber (reg:CC 17))] | |
d525dfdf | 11748 | "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
e075ae69 | 11749 | "@ |
0f40f9f7 ZW |
11750 | shr{l}\t{%2, %0|%0, %2} |
11751 | shr{l}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11752 | [(set_attr "type" "ishift") |
11753 | (set_attr "mode" "SI")]) | |
886c62d1 | 11754 | |
371bc54b JH |
11755 | (define_insn "*lshrsi3_1_zext" |
11756 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
11757 | (zero_extend:DI | |
11758 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
11759 | (match_operand:QI 2 "nonmemory_operand" "I,c")))) | |
11760 | (clobber (reg:CC 17))] | |
11761 | "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
11762 | "@ | |
0f40f9f7 ZW |
11763 | shr{l}\t{%2, %k0|%k0, %2} |
11764 | shr{l}\t{%b2, %k0|%k0, %b2}" | |
371bc54b JH |
11765 | [(set_attr "type" "ishift") |
11766 | (set_attr "mode" "SI")]) | |
11767 | ||
8bad7136 JL |
11768 | ;; This pattern can't accept a variable shift count, since shifts by |
11769 | ;; zero don't affect the flags. We assume that shifts by constant | |
11770 | ;; zero are optimized away. | |
2c873473 | 11771 | (define_insn "*lshrsi3_one_bit_cmp" |
8bad7136 JL |
11772 | [(set (reg 17) |
11773 | (compare | |
11774 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
11775 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11776 | (const_int 0))) | |
11777 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
11778 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 11779 | "ix86_match_ccmode (insn, CCGOCmode) |
495333a6 | 11780 | && (TARGET_SHIFT1 || optimize_size) |
8bad7136 | 11781 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
0f40f9f7 | 11782 | "shr{l}\t%0" |
8bad7136 JL |
11783 | [(set_attr "type" "ishift") |
11784 | (set (attr "length") | |
11785 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11786 | (const_string "2") | |
11787 | (const_string "*")))]) | |
11788 | ||
371bc54b JH |
11789 | (define_insn "*lshrsi3_cmp_one_bit_zext" |
11790 | [(set (reg 17) | |
11791 | (compare | |
11792 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
11793 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11794 | (const_int 0))) | |
11795 | (set (match_operand:DI 0 "register_operand" "=r") | |
11796 | (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] | |
11797 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
495333a6 | 11798 | && (TARGET_SHIFT1 || optimize_size) |
371bc54b | 11799 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
0f40f9f7 | 11800 | "shr{l}\t%k0" |
371bc54b JH |
11801 | [(set_attr "type" "ishift") |
11802 | (set_attr "length" "2")]) | |
11803 | ||
28cefcd2 BS |
11804 | ;; This pattern can't accept a variable shift count, since shifts by |
11805 | ;; zero don't affect the flags. We assume that shifts by constant | |
11806 | ;; zero are optimized away. | |
2c873473 | 11807 | (define_insn "*lshrsi3_cmp" |
16189740 RH |
11808 | [(set (reg 17) |
11809 | (compare | |
28cefcd2 | 11810 | (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
794a292d | 11811 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
e075ae69 | 11812 | (const_int 0))) |
28cefcd2 | 11813 | (set (match_operand:SI 0 "nonimmediate_operand" "=rm") |
e075ae69 | 11814 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
9076b9c1 | 11815 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11816 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
0f40f9f7 | 11817 | "shr{l}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11818 | [(set_attr "type" "ishift") |
11819 | (set_attr "mode" "SI")]) | |
886c62d1 | 11820 | |
371bc54b JH |
11821 | (define_insn "*lshrsi3_cmp_zext" |
11822 | [(set (reg 17) | |
11823 | (compare | |
11824 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
794a292d | 11825 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
371bc54b JH |
11826 | (const_int 0))) |
11827 | (set (match_operand:DI 0 "register_operand" "=r") | |
11828 | (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] | |
11829 | "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) | |
11830 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" | |
0f40f9f7 | 11831 | "shr{l}\t{%2, %k0|%k0, %2}" |
371bc54b JH |
11832 | [(set_attr "type" "ishift") |
11833 | (set_attr "mode" "SI")]) | |
11834 | ||
d525dfdf JH |
11835 | (define_expand "lshrhi3" |
11836 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
11837 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
11838 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11839 | (clobber (reg:CC 17))] | |
d9f32422 | 11840 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
11841 | "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;") |
11842 | ||
8bad7136 JL |
11843 | (define_insn "*lshrhi3_1_one_bit" |
11844 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
11845 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
11846 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11847 | (clobber (reg:CC 17))] | |
11848 | "ix86_binary_operator_ok (LSHIFTRT, HImode, operands) | |
495333a6 | 11849 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11850 | "shr{w}\t%0" |
8bad7136 JL |
11851 | [(set_attr "type" "ishift") |
11852 | (set (attr "length") | |
3d117b30 | 11853 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11854 | (const_string "2") |
11855 | (const_string "*")))]) | |
11856 | ||
d525dfdf | 11857 | (define_insn "*lshrhi3_1" |
e075ae69 RH |
11858 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") |
11859 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
11860 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11861 | (clobber (reg:CC 17))] | |
d525dfdf | 11862 | "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
e075ae69 | 11863 | "@ |
0f40f9f7 ZW |
11864 | shr{w}\t{%2, %0|%0, %2} |
11865 | shr{w}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11866 | [(set_attr "type" "ishift") |
11867 | (set_attr "mode" "HI")]) | |
886c62d1 | 11868 | |
8bad7136 JL |
11869 | ;; This pattern can't accept a variable shift count, since shifts by |
11870 | ;; zero don't affect the flags. We assume that shifts by constant | |
11871 | ;; zero are optimized away. | |
2c873473 | 11872 | (define_insn "*lshrhi3_one_bit_cmp" |
8bad7136 JL |
11873 | [(set (reg 17) |
11874 | (compare | |
11875 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
11876 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11877 | (const_int 0))) | |
11878 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
11879 | (lshiftrt:HI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 11880 | "ix86_match_ccmode (insn, CCGOCmode) |
495333a6 | 11881 | && (TARGET_SHIFT1 || optimize_size) |
8bad7136 | 11882 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
0f40f9f7 | 11883 | "shr{w}\t%0" |
8bad7136 JL |
11884 | [(set_attr "type" "ishift") |
11885 | (set (attr "length") | |
11886 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11887 | (const_string "2") | |
11888 | (const_string "*")))]) | |
11889 | ||
28cefcd2 BS |
11890 | ;; This pattern can't accept a variable shift count, since shifts by |
11891 | ;; zero don't affect the flags. We assume that shifts by constant | |
11892 | ;; zero are optimized away. | |
2c873473 | 11893 | (define_insn "*lshrhi3_cmp" |
16189740 RH |
11894 | [(set (reg 17) |
11895 | (compare | |
28cefcd2 | 11896 | (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") |
794a292d | 11897 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
e075ae69 | 11898 | (const_int 0))) |
28cefcd2 | 11899 | (set (match_operand:HI 0 "nonimmediate_operand" "=rm") |
e075ae69 | 11900 | (lshiftrt:HI (match_dup 1) (match_dup 2)))] |
9076b9c1 | 11901 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 11902 | && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" |
0f40f9f7 | 11903 | "shr{w}\t{%2, %0|%0, %2}" |
6ef67412 JH |
11904 | [(set_attr "type" "ishift") |
11905 | (set_attr "mode" "HI")]) | |
886c62d1 | 11906 | |
d525dfdf JH |
11907 | (define_expand "lshrqi3" |
11908 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
11909 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
11910 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
11911 | (clobber (reg:CC 17))] | |
d9f32422 | 11912 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
11913 | "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;") |
11914 | ||
8bad7136 JL |
11915 | (define_insn "*lshrqi3_1_one_bit" |
11916 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
11917 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
11918 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11919 | (clobber (reg:CC 17))] | |
11920 | "ix86_binary_operator_ok (LSHIFTRT, QImode, operands) | |
495333a6 | 11921 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 11922 | "shr{b}\t%0" |
8bad7136 JL |
11923 | [(set_attr "type" "ishift") |
11924 | (set (attr "length") | |
3d117b30 | 11925 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
11926 | (const_string "2") |
11927 | (const_string "*")))]) | |
11928 | ||
2f41793e JH |
11929 | (define_insn "*lshrqi3_1_one_bit_slp" |
11930 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) | |
11931 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
11932 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
11933 | (clobber (reg:CC 17))] | |
11934 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
11935 | && ix86_binary_operator_ok (LSHIFTRT, QImode, operands) | |
495333a6 | 11936 | && (TARGET_SHIFT1 || optimize_size)" |
2f41793e JH |
11937 | "shr{b}\t%0" |
11938 | [(set_attr "type" "ishift") | |
11939 | (set (attr "length") | |
11940 | (if_then_else (match_operand 0 "register_operand" "") | |
11941 | (const_string "2") | |
11942 | (const_string "*")))]) | |
11943 | ||
d525dfdf | 11944 | (define_insn "*lshrqi3_1" |
e075ae69 RH |
11945 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") |
11946 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
11947 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11948 | (clobber (reg:CC 17))] | |
d525dfdf | 11949 | "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" |
e075ae69 | 11950 | "@ |
0f40f9f7 ZW |
11951 | shr{b}\t{%2, %0|%0, %2} |
11952 | shr{b}\t{%b2, %0|%0, %b2}" | |
6ef67412 JH |
11953 | [(set_attr "type" "ishift") |
11954 | (set_attr "mode" "QI")]) | |
886c62d1 | 11955 | |
2f41793e JH |
11956 | (define_insn "*lshrqi3_1_slp" |
11957 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) | |
11958 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
11959 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
11960 | (clobber (reg:CC 17))] | |
11961 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
11962 | && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" | |
11963 | "@ | |
11964 | shr{b}\t{%2, %0|%0, %2} | |
11965 | shr{b}\t{%b2, %0|%0, %b2}" | |
11966 | [(set_attr "type" "ishift") | |
11967 | (set_attr "mode" "QI")]) | |
11968 | ||
8bad7136 JL |
11969 | ;; This pattern can't accept a variable shift count, since shifts by |
11970 | ;; zero don't affect the flags. We assume that shifts by constant | |
11971 | ;; zero are optimized away. | |
2c873473 | 11972 | (define_insn "*lshrqi2_one_bit_cmp" |
8bad7136 JL |
11973 | [(set (reg 17) |
11974 | (compare | |
11975 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
11976 | (match_operand:QI 2 "const_int_1_operand" "")) | |
11977 | (const_int 0))) | |
11978 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
11979 | (lshiftrt:QI (match_dup 1) (match_dup 2)))] | |
9076b9c1 | 11980 | "ix86_match_ccmode (insn, CCGOCmode) |
495333a6 | 11981 | && (TARGET_SHIFT1 || optimize_size) |
8bad7136 | 11982 | && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" |
0f40f9f7 | 11983 | "shr{b}\t%0" |
8bad7136 JL |
11984 | [(set_attr "type" "ishift") |
11985 | (set (attr "length") | |
11986 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
11987 | (const_string "2") | |
11988 | (const_string "*")))]) | |
11989 | ||
28cefcd2 BS |
11990 | ;; This pattern can't accept a variable shift count, since shifts by |
11991 | ;; zero don't affect the flags. We assume that shifts by constant | |
11992 | ;; zero are optimized away. | |
2c873473 | 11993 | (define_insn "*lshrqi2_cmp" |
16189740 RH |
11994 | [(set (reg 17) |
11995 | (compare | |
28cefcd2 | 11996 | (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") |
794a292d | 11997 | (match_operand:QI 2 "const_int_1_31_operand" "I")) |
e075ae69 | 11998 | (const_int 0))) |
122ddbf9 | 11999 | (set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
e075ae69 | 12000 | (lshiftrt:QI (match_dup 1) (match_dup 2)))] |
9076b9c1 | 12001 | "ix86_match_ccmode (insn, CCGOCmode) |
16189740 | 12002 | && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" |
0f40f9f7 | 12003 | "shr{b}\t{%2, %0|%0, %2}" |
6ef67412 JH |
12004 | [(set_attr "type" "ishift") |
12005 | (set_attr "mode" "QI")]) | |
886c62d1 | 12006 | \f |
e075ae69 | 12007 | ;; Rotate instructions |
886c62d1 | 12008 | |
371bc54b JH |
12009 | (define_expand "rotldi3" |
12010 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
12011 | (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
12012 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12013 | (clobber (reg:CC 17))] | |
12014 | "TARGET_64BIT" | |
12015 | "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;") | |
12016 | ||
12017 | (define_insn "*rotlsi3_1_one_bit_rex64" | |
12018 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
12019 | (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
12020 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12021 | (clobber (reg:CC 17))] | |
12022 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands) | |
495333a6 | 12023 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12024 | "rol{q}\t%0" |
890d52e8 | 12025 | [(set_attr "type" "rotate") |
371bc54b JH |
12026 | (set (attr "length") |
12027 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
12028 | (const_string "2") | |
12029 | (const_string "*")))]) | |
12030 | ||
12031 | (define_insn "*rotldi3_1_rex64" | |
12032 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") | |
12033 | (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
12034 | (match_operand:QI 2 "nonmemory_operand" "e,c"))) | |
12035 | (clobber (reg:CC 17))] | |
12036 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)" | |
12037 | "@ | |
0f40f9f7 ZW |
12038 | rol{q}\t{%2, %0|%0, %2} |
12039 | rol{q}\t{%b2, %0|%0, %b2}" | |
890d52e8 | 12040 | [(set_attr "type" "rotate") |
371bc54b JH |
12041 | (set_attr "mode" "DI")]) |
12042 | ||
d525dfdf JH |
12043 | (define_expand "rotlsi3" |
12044 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
12045 | (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
12046 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12047 | (clobber (reg:CC 17))] | |
12048 | "" | |
12049 | "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;") | |
12050 | ||
8bad7136 JL |
12051 | (define_insn "*rotlsi3_1_one_bit" |
12052 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
12053 | (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
12054 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12055 | (clobber (reg:CC 17))] | |
12056 | "ix86_binary_operator_ok (ROTATE, SImode, operands) | |
495333a6 | 12057 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12058 | "rol{l}\t%0" |
890d52e8 | 12059 | [(set_attr "type" "rotate") |
8bad7136 JL |
12060 | (set (attr "length") |
12061 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
12062 | (const_string "2") | |
12063 | (const_string "*")))]) | |
12064 | ||
371bc54b JH |
12065 | (define_insn "*rotlsi3_1_one_bit_zext" |
12066 | [(set (match_operand:DI 0 "register_operand" "=r") | |
12067 | (zero_extend:DI | |
12068 | (rotate:SI (match_operand:SI 1 "register_operand" "0") | |
12069 | (match_operand:QI 2 "const_int_1_operand" "")))) | |
12070 | (clobber (reg:CC 17))] | |
12071 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands) | |
495333a6 | 12072 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12073 | "rol{l}\t%k0" |
890d52e8 | 12074 | [(set_attr "type" "rotate") |
371bc54b JH |
12075 | (set_attr "length" "2")]) |
12076 | ||
d525dfdf | 12077 | (define_insn "*rotlsi3_1" |
e075ae69 RH |
12078 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") |
12079 | (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
12080 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12081 | (clobber (reg:CC 17))] | |
d525dfdf | 12082 | "ix86_binary_operator_ok (ROTATE, SImode, operands)" |
e075ae69 | 12083 | "@ |
0f40f9f7 ZW |
12084 | rol{l}\t{%2, %0|%0, %2} |
12085 | rol{l}\t{%b2, %0|%0, %b2}" | |
890d52e8 | 12086 | [(set_attr "type" "rotate") |
6ef67412 | 12087 | (set_attr "mode" "SI")]) |
b4ac57ab | 12088 | |
371bc54b JH |
12089 | (define_insn "*rotlsi3_1_zext" |
12090 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
12091 | (zero_extend:DI | |
12092 | (rotate:SI (match_operand:SI 1 "register_operand" "0,0") | |
12093 | (match_operand:QI 2 "nonmemory_operand" "I,c")))) | |
12094 | (clobber (reg:CC 17))] | |
12095 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)" | |
12096 | "@ | |
0f40f9f7 ZW |
12097 | rol{l}\t{%2, %k0|%k0, %2} |
12098 | rol{l}\t{%b2, %k0|%k0, %b2}" | |
890d52e8 | 12099 | [(set_attr "type" "rotate") |
371bc54b JH |
12100 | (set_attr "mode" "SI")]) |
12101 | ||
d525dfdf JH |
12102 | (define_expand "rotlhi3" |
12103 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
12104 | (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
12105 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12106 | (clobber (reg:CC 17))] | |
d9f32422 | 12107 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
12108 | "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;") |
12109 | ||
8bad7136 JL |
12110 | (define_insn "*rotlhi3_1_one_bit" |
12111 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
12112 | (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
12113 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12114 | (clobber (reg:CC 17))] | |
12115 | "ix86_binary_operator_ok (ROTATE, HImode, operands) | |
495333a6 | 12116 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12117 | "rol{w}\t%0" |
890d52e8 | 12118 | [(set_attr "type" "rotate") |
8bad7136 | 12119 | (set (attr "length") |
3d117b30 | 12120 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
12121 | (const_string "2") |
12122 | (const_string "*")))]) | |
12123 | ||
d525dfdf | 12124 | (define_insn "*rotlhi3_1" |
e075ae69 RH |
12125 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") |
12126 | (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
12127 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12128 | (clobber (reg:CC 17))] | |
d525dfdf | 12129 | "ix86_binary_operator_ok (ROTATE, HImode, operands)" |
e075ae69 | 12130 | "@ |
0f40f9f7 ZW |
12131 | rol{w}\t{%2, %0|%0, %2} |
12132 | rol{w}\t{%b2, %0|%0, %b2}" | |
890d52e8 | 12133 | [(set_attr "type" "rotate") |
6ef67412 | 12134 | (set_attr "mode" "HI")]) |
47af5d50 | 12135 | |
d525dfdf JH |
12136 | (define_expand "rotlqi3" |
12137 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
12138 | (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
12139 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12140 | (clobber (reg:CC 17))] | |
d9f32422 | 12141 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
12142 | "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;") |
12143 | ||
2f41793e JH |
12144 | (define_insn "*rotlqi3_1_one_bit_slp" |
12145 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) | |
12146 | (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
12147 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12148 | (clobber (reg:CC 17))] | |
12149 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
12150 | && ix86_binary_operator_ok (ROTATE, QImode, operands) | |
495333a6 | 12151 | && (TARGET_SHIFT1 || optimize_size)" |
2f41793e JH |
12152 | "rol{b}\t%0" |
12153 | [(set_attr "type" "rotate") | |
12154 | (set (attr "length") | |
12155 | (if_then_else (match_operand 0 "register_operand" "") | |
12156 | (const_string "2") | |
12157 | (const_string "*")))]) | |
12158 | ||
8bad7136 JL |
12159 | (define_insn "*rotlqi3_1_one_bit" |
12160 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
12161 | (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
12162 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12163 | (clobber (reg:CC 17))] | |
12164 | "ix86_binary_operator_ok (ROTATE, QImode, operands) | |
495333a6 | 12165 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12166 | "rol{b}\t%0" |
890d52e8 | 12167 | [(set_attr "type" "rotate") |
8bad7136 | 12168 | (set (attr "length") |
3d117b30 | 12169 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
12170 | (const_string "2") |
12171 | (const_string "*")))]) | |
12172 | ||
2f41793e JH |
12173 | (define_insn "*rotlqi3_1_slp" |
12174 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) | |
12175 | (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
12176 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12177 | (clobber (reg:CC 17))] | |
12178 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
12179 | && ix86_binary_operator_ok (ROTATE, QImode, operands)" | |
12180 | "@ | |
12181 | rol{b}\t{%2, %0|%0, %2} | |
12182 | rol{b}\t{%b2, %0|%0, %b2}" | |
12183 | [(set_attr "type" "rotate") | |
12184 | (set_attr "mode" "QI")]) | |
12185 | ||
d525dfdf | 12186 | (define_insn "*rotlqi3_1" |
e075ae69 RH |
12187 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") |
12188 | (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
12189 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12190 | (clobber (reg:CC 17))] | |
d525dfdf | 12191 | "ix86_binary_operator_ok (ROTATE, QImode, operands)" |
e075ae69 | 12192 | "@ |
0f40f9f7 ZW |
12193 | rol{b}\t{%2, %0|%0, %2} |
12194 | rol{b}\t{%b2, %0|%0, %b2}" | |
890d52e8 | 12195 | [(set_attr "type" "rotate") |
6ef67412 | 12196 | (set_attr "mode" "QI")]) |
47af5d50 | 12197 | |
371bc54b JH |
12198 | (define_expand "rotrdi3" |
12199 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
12200 | (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
12201 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12202 | (clobber (reg:CC 17))] | |
12203 | "TARGET_64BIT" | |
12204 | "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;") | |
12205 | ||
12206 | (define_insn "*rotrdi3_1_one_bit_rex64" | |
12207 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") | |
12208 | (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
12209 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12210 | (clobber (reg:CC 17))] | |
12211 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands) | |
495333a6 | 12212 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12213 | "ror{q}\t%0" |
890d52e8 | 12214 | [(set_attr "type" "rotate") |
371bc54b JH |
12215 | (set (attr "length") |
12216 | (if_then_else (match_operand:DI 0 "register_operand" "") | |
12217 | (const_string "2") | |
12218 | (const_string "*")))]) | |
12219 | ||
12220 | (define_insn "*rotrdi3_1_rex64" | |
12221 | [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") | |
12222 | (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
12223 | (match_operand:QI 2 "nonmemory_operand" "J,c"))) | |
12224 | (clobber (reg:CC 17))] | |
12225 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)" | |
12226 | "@ | |
0f40f9f7 ZW |
12227 | ror{q}\t{%2, %0|%0, %2} |
12228 | ror{q}\t{%b2, %0|%0, %b2}" | |
890d52e8 | 12229 | [(set_attr "type" "rotate") |
371bc54b JH |
12230 | (set_attr "mode" "DI")]) |
12231 | ||
d525dfdf JH |
12232 | (define_expand "rotrsi3" |
12233 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
12234 | (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
12235 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12236 | (clobber (reg:CC 17))] | |
12237 | "" | |
12238 | "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;") | |
12239 | ||
8bad7136 JL |
12240 | (define_insn "*rotrsi3_1_one_bit" |
12241 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") | |
12242 | (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
12243 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12244 | (clobber (reg:CC 17))] | |
12245 | "ix86_binary_operator_ok (ROTATERT, SImode, operands) | |
495333a6 | 12246 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12247 | "ror{l}\t%0" |
890d52e8 | 12248 | [(set_attr "type" "rotate") |
8bad7136 JL |
12249 | (set (attr "length") |
12250 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
12251 | (const_string "2") | |
12252 | (const_string "*")))]) | |
12253 | ||
371bc54b JH |
12254 | (define_insn "*rotrsi3_1_one_bit_zext" |
12255 | [(set (match_operand:DI 0 "register_operand" "=r") | |
12256 | (zero_extend:DI | |
12257 | (rotatert:SI (match_operand:SI 1 "register_operand" "0") | |
12258 | (match_operand:QI 2 "const_int_1_operand" "")))) | |
12259 | (clobber (reg:CC 17))] | |
12260 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands) | |
495333a6 | 12261 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12262 | "ror{l}\t%k0" |
890d52e8 | 12263 | [(set_attr "type" "rotate") |
371bc54b JH |
12264 | (set (attr "length") |
12265 | (if_then_else (match_operand:SI 0 "register_operand" "") | |
12266 | (const_string "2") | |
12267 | (const_string "*")))]) | |
12268 | ||
d525dfdf | 12269 | (define_insn "*rotrsi3_1" |
e075ae69 RH |
12270 | [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") |
12271 | (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
12272 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12273 | (clobber (reg:CC 17))] | |
d525dfdf | 12274 | "ix86_binary_operator_ok (ROTATERT, SImode, operands)" |
e075ae69 | 12275 | "@ |
0f40f9f7 ZW |
12276 | ror{l}\t{%2, %0|%0, %2} |
12277 | ror{l}\t{%b2, %0|%0, %b2}" | |
890d52e8 | 12278 | [(set_attr "type" "rotate") |
6ef67412 | 12279 | (set_attr "mode" "SI")]) |
47af5d50 | 12280 | |
371bc54b JH |
12281 | (define_insn "*rotrsi3_1_zext" |
12282 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
12283 | (zero_extend:DI | |
12284 | (rotatert:SI (match_operand:SI 1 "register_operand" "0,0") | |
12285 | (match_operand:QI 2 "nonmemory_operand" "I,c")))) | |
12286 | (clobber (reg:CC 17))] | |
12287 | "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)" | |
12288 | "@ | |
0f40f9f7 ZW |
12289 | ror{l}\t{%2, %k0|%k0, %2} |
12290 | ror{l}\t{%b2, %k0|%k0, %b2}" | |
890d52e8 | 12291 | [(set_attr "type" "rotate") |
371bc54b JH |
12292 | (set_attr "mode" "SI")]) |
12293 | ||
d525dfdf JH |
12294 | (define_expand "rotrhi3" |
12295 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
12296 | (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
12297 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12298 | (clobber (reg:CC 17))] | |
d9f32422 | 12299 | "TARGET_HIMODE_MATH" |
d525dfdf JH |
12300 | "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;") |
12301 | ||
8bad7136 JL |
12302 | (define_insn "*rotrhi3_one_bit" |
12303 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") | |
12304 | (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0") | |
12305 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12306 | (clobber (reg:CC 17))] | |
12307 | "ix86_binary_operator_ok (ROTATERT, HImode, operands) | |
495333a6 | 12308 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12309 | "ror{w}\t%0" |
890d52e8 | 12310 | [(set_attr "type" "rotate") |
8bad7136 | 12311 | (set (attr "length") |
3d117b30 | 12312 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
12313 | (const_string "2") |
12314 | (const_string "*")))]) | |
12315 | ||
d525dfdf | 12316 | (define_insn "*rotrhi3" |
e075ae69 RH |
12317 | [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") |
12318 | (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") | |
12319 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12320 | (clobber (reg:CC 17))] | |
d525dfdf | 12321 | "ix86_binary_operator_ok (ROTATERT, HImode, operands)" |
e075ae69 | 12322 | "@ |
0f40f9f7 ZW |
12323 | ror{w}\t{%2, %0|%0, %2} |
12324 | ror{w}\t{%b2, %0|%0, %b2}" | |
890d52e8 | 12325 | [(set_attr "type" "rotate") |
6ef67412 | 12326 | (set_attr "mode" "HI")]) |
a199fdd6 | 12327 | |
d525dfdf JH |
12328 | (define_expand "rotrqi3" |
12329 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
12330 | (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
12331 | (match_operand:QI 2 "nonmemory_operand" ""))) | |
12332 | (clobber (reg:CC 17))] | |
d9f32422 | 12333 | "TARGET_QIMODE_MATH" |
d525dfdf JH |
12334 | "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;") |
12335 | ||
8bad7136 JL |
12336 | (define_insn "*rotrqi3_1_one_bit" |
12337 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") | |
12338 | (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
12339 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12340 | (clobber (reg:CC 17))] | |
12341 | "ix86_binary_operator_ok (ROTATERT, QImode, operands) | |
495333a6 | 12342 | && (TARGET_SHIFT1 || optimize_size)" |
0f40f9f7 | 12343 | "ror{b}\t%0" |
890d52e8 | 12344 | [(set_attr "type" "rotate") |
8bad7136 | 12345 | (set (attr "length") |
3d117b30 | 12346 | (if_then_else (match_operand 0 "register_operand" "") |
8bad7136 JL |
12347 | (const_string "2") |
12348 | (const_string "*")))]) | |
12349 | ||
2f41793e JH |
12350 | (define_insn "*rotrqi3_1_one_bit_slp" |
12351 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) | |
12352 | (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0") | |
12353 | (match_operand:QI 2 "const_int_1_operand" ""))) | |
12354 | (clobber (reg:CC 17))] | |
12355 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
12356 | && ix86_binary_operator_ok (ROTATERT, QImode, operands) | |
495333a6 | 12357 | && (TARGET_SHIFT1 || optimize_size)" |
2f41793e JH |
12358 | "ror{b}\t%0" |
12359 | [(set_attr "type" "rotate") | |
12360 | (set (attr "length") | |
12361 | (if_then_else (match_operand 0 "register_operand" "") | |
12362 | (const_string "2") | |
12363 | (const_string "*")))]) | |
12364 | ||
d525dfdf | 12365 | (define_insn "*rotrqi3_1" |
e075ae69 RH |
12366 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") |
12367 | (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
12368 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12369 | (clobber (reg:CC 17))] | |
d525dfdf | 12370 | "ix86_binary_operator_ok (ROTATERT, QImode, operands)" |
e075ae69 | 12371 | "@ |
0f40f9f7 ZW |
12372 | ror{b}\t{%2, %0|%0, %2} |
12373 | ror{b}\t{%b2, %0|%0, %b2}" | |
890d52e8 | 12374 | [(set_attr "type" "rotate") |
6ef67412 | 12375 | (set_attr "mode" "QI")]) |
2f41793e JH |
12376 | |
12377 | (define_insn "*rotrqi3_1_slp" | |
12378 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) | |
12379 | (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") | |
12380 | (match_operand:QI 2 "nonmemory_operand" "I,c"))) | |
12381 | (clobber (reg:CC 17))] | |
12382 | "(! TARGET_PARTIAL_REG_STALL || optimize_size) | |
12383 | && ix86_binary_operator_ok (ROTATERT, QImode, operands)" | |
12384 | "@ | |
12385 | ror{b}\t{%2, %0|%0, %2} | |
12386 | ror{b}\t{%b2, %0|%0, %b2}" | |
12387 | [(set_attr "type" "rotate") | |
12388 | (set_attr "mode" "QI")]) | |
e075ae69 RH |
12389 | \f |
12390 | ;; Bit set / bit test instructions | |
a199fdd6 | 12391 | |
e075ae69 RH |
12392 | (define_expand "extv" |
12393 | [(set (match_operand:SI 0 "register_operand" "") | |
12394 | (sign_extract:SI (match_operand:SI 1 "register_operand" "") | |
12395 | (match_operand:SI 2 "immediate_operand" "") | |
12396 | (match_operand:SI 3 "immediate_operand" "")))] | |
12397 | "" | |
e075ae69 RH |
12398 | { |
12399 | /* Handle extractions from %ah et al. */ | |
12400 | if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) | |
12401 | FAIL; | |
a199fdd6 | 12402 | |
e075ae69 RH |
12403 | /* From mips.md: extract_bit_field doesn't verify that our source |
12404 | matches the predicate, so check it again here. */ | |
12405 | if (! register_operand (operands[1], VOIDmode)) | |
12406 | FAIL; | |
0f40f9f7 | 12407 | }) |
a199fdd6 | 12408 | |
e075ae69 RH |
12409 | (define_expand "extzv" |
12410 | [(set (match_operand:SI 0 "register_operand" "") | |
12411 | (zero_extract:SI (match_operand 1 "ext_register_operand" "") | |
12412 | (match_operand:SI 2 "immediate_operand" "") | |
12413 | (match_operand:SI 3 "immediate_operand" "")))] | |
12414 | "" | |
e075ae69 RH |
12415 | { |
12416 | /* Handle extractions from %ah et al. */ | |
12417 | if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8) | |
12418 | FAIL; | |
a199fdd6 | 12419 | |
e075ae69 RH |
12420 | /* From mips.md: extract_bit_field doesn't verify that our source |
12421 | matches the predicate, so check it again here. */ | |
12422 | if (! register_operand (operands[1], VOIDmode)) | |
12423 | FAIL; | |
0f40f9f7 | 12424 | }) |
a199fdd6 | 12425 | |
e075ae69 RH |
12426 | (define_expand "insv" |
12427 | [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "") | |
12428 | (match_operand:SI 1 "immediate_operand" "") | |
12429 | (match_operand:SI 2 "immediate_operand" "")) | |
12430 | (match_operand:SI 3 "register_operand" ""))] | |
12431 | "" | |
e075ae69 RH |
12432 | { |
12433 | /* Handle extractions from %ah et al. */ | |
12434 | if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8) | |
12435 | FAIL; | |
a199fdd6 | 12436 | |
e075ae69 RH |
12437 | /* From mips.md: insert_bit_field doesn't verify that our source |
12438 | matches the predicate, so check it again here. */ | |
12439 | if (! register_operand (operands[0], VOIDmode)) | |
12440 | FAIL; | |
0f40f9f7 | 12441 | }) |
e075ae69 RH |
12442 | |
12443 | ;; %%% bts, btr, btc, bt. | |
886c62d1 JVA |
12444 | \f |
12445 | ;; Store-flag instructions. | |
12446 | ||
c572e5ba JVA |
12447 | ;; For all sCOND expanders, also expand the compare or test insn that |
12448 | ;; generates cc0. Generate an equality comparison if `seq' or `sne'. | |
12449 | ||
e075ae69 RH |
12450 | ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way |
12451 | ;; to avoid partial register stalls. Otherwise do things the setcc+movzx | |
12452 | ;; way, which can later delete the movzx if only QImode is needed. | |
12453 | ||
c572e5ba | 12454 | (define_expand "seq" |
b932f770 JH |
12455 | [(set (match_operand:QI 0 "register_operand" "") |
12456 | (eq:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12457 | "" |
3a3677ff | 12458 | "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;") |
c572e5ba | 12459 | |
c572e5ba | 12460 | (define_expand "sne" |
b932f770 JH |
12461 | [(set (match_operand:QI 0 "register_operand" "") |
12462 | (ne:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12463 | "" |
3a3677ff | 12464 | "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;") |
c572e5ba | 12465 | |
c572e5ba | 12466 | (define_expand "sgt" |
b932f770 JH |
12467 | [(set (match_operand:QI 0 "register_operand" "") |
12468 | (gt:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12469 | "" |
3a3677ff | 12470 | "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;") |
c572e5ba | 12471 | |
c572e5ba | 12472 | (define_expand "sgtu" |
b932f770 JH |
12473 | [(set (match_operand:QI 0 "register_operand" "") |
12474 | (gtu:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12475 | "" |
3a3677ff | 12476 | "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;") |
c572e5ba | 12477 | |
c572e5ba | 12478 | (define_expand "slt" |
b932f770 JH |
12479 | [(set (match_operand:QI 0 "register_operand" "") |
12480 | (lt:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12481 | "" |
3a3677ff | 12482 | "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;") |
c572e5ba | 12483 | |
c572e5ba | 12484 | (define_expand "sltu" |
b932f770 JH |
12485 | [(set (match_operand:QI 0 "register_operand" "") |
12486 | (ltu:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12487 | "" |
3a3677ff | 12488 | "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;") |
c572e5ba | 12489 | |
c572e5ba | 12490 | (define_expand "sge" |
b932f770 JH |
12491 | [(set (match_operand:QI 0 "register_operand" "") |
12492 | (ge:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12493 | "" |
3a3677ff | 12494 | "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;") |
c572e5ba | 12495 | |
c572e5ba | 12496 | (define_expand "sgeu" |
b932f770 JH |
12497 | [(set (match_operand:QI 0 "register_operand" "") |
12498 | (geu:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12499 | "" |
3a3677ff | 12500 | "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;") |
c572e5ba | 12501 | |
c572e5ba | 12502 | (define_expand "sle" |
b932f770 JH |
12503 | [(set (match_operand:QI 0 "register_operand" "") |
12504 | (le:QI (reg:CC 17) (const_int 0)))] | |
c572e5ba | 12505 | "" |
3a3677ff | 12506 | "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;") |
c572e5ba | 12507 | |
c785c660 | 12508 | (define_expand "sleu" |
b932f770 JH |
12509 | [(set (match_operand:QI 0 "register_operand" "") |
12510 | (leu:QI (reg:CC 17) (const_int 0)))] | |
c785c660 | 12511 | "" |
3a3677ff RH |
12512 | "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;") |
12513 | ||
12514 | (define_expand "sunordered" | |
b932f770 JH |
12515 | [(set (match_operand:QI 0 "register_operand" "") |
12516 | (unordered:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12517 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12518 | "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;") |
12519 | ||
12520 | (define_expand "sordered" | |
b932f770 JH |
12521 | [(set (match_operand:QI 0 "register_operand" "") |
12522 | (ordered:QI (reg:CC 17) (const_int 0)))] | |
3a3677ff RH |
12523 | "TARGET_80387" |
12524 | "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;") | |
12525 | ||
12526 | (define_expand "suneq" | |
b932f770 JH |
12527 | [(set (match_operand:QI 0 "register_operand" "") |
12528 | (uneq:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12529 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12530 | "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;") |
12531 | ||
12532 | (define_expand "sunge" | |
b932f770 JH |
12533 | [(set (match_operand:QI 0 "register_operand" "") |
12534 | (unge:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12535 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12536 | "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;") |
12537 | ||
12538 | (define_expand "sungt" | |
b932f770 JH |
12539 | [(set (match_operand:QI 0 "register_operand" "") |
12540 | (ungt:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12541 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12542 | "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;") |
12543 | ||
12544 | (define_expand "sunle" | |
b932f770 JH |
12545 | [(set (match_operand:QI 0 "register_operand" "") |
12546 | (unle:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12547 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12548 | "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;") |
12549 | ||
12550 | (define_expand "sunlt" | |
b932f770 JH |
12551 | [(set (match_operand:QI 0 "register_operand" "") |
12552 | (unlt:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12553 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12554 | "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;") |
12555 | ||
12556 | (define_expand "sltgt" | |
b932f770 JH |
12557 | [(set (match_operand:QI 0 "register_operand" "") |
12558 | (ltgt:QI (reg:CC 17) (const_int 0)))] | |
0644b628 | 12559 | "TARGET_80387 || TARGET_SSE" |
3a3677ff | 12560 | "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;") |
c785c660 | 12561 | |
e075ae69 | 12562 | (define_insn "*setcc_1" |
a269a03c | 12563 | [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") |
9076b9c1 | 12564 | (match_operator:QI 1 "ix86_comparison_operator" |
e075ae69 RH |
12565 | [(reg 17) (const_int 0)]))] |
12566 | "" | |
0f40f9f7 | 12567 | "set%C1\t%0" |
6ef67412 JH |
12568 | [(set_attr "type" "setcc") |
12569 | (set_attr "mode" "QI")]) | |
a269a03c | 12570 | |
bd793c65 | 12571 | (define_insn "setcc_2" |
e075ae69 | 12572 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) |
9076b9c1 | 12573 | (match_operator:QI 1 "ix86_comparison_operator" |
e075ae69 RH |
12574 | [(reg 17) (const_int 0)]))] |
12575 | "" | |
0f40f9f7 | 12576 | "set%C1\t%0" |
6ef67412 JH |
12577 | [(set_attr "type" "setcc") |
12578 | (set_attr "mode" "QI")]) | |
e075ae69 | 12579 | |
10978207 RH |
12580 | ;; In general it is not safe to assume too much about CCmode registers, |
12581 | ;; so simplify-rtx stops when it sees a second one. Under certain | |
12582 | ;; conditions this is safe on x86, so help combine not create | |
12583 | ;; | |
12584 | ;; seta %al | |
12585 | ;; testb %al, %al | |
12586 | ;; sete %al | |
12587 | ||
12588 | (define_split | |
12589 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
12590 | (ne:QI (match_operator 1 "ix86_comparison_operator" | |
12591 | [(reg 17) (const_int 0)]) | |
12592 | (const_int 0)))] | |
12593 | "" | |
12594 | [(set (match_dup 0) (match_dup 1))] | |
12595 | { | |
12596 | PUT_MODE (operands[1], QImode); | |
12597 | }) | |
12598 | ||
12599 | (define_split | |
12600 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) | |
12601 | (ne:QI (match_operator 1 "ix86_comparison_operator" | |
12602 | [(reg 17) (const_int 0)]) | |
12603 | (const_int 0)))] | |
12604 | "" | |
12605 | [(set (match_dup 0) (match_dup 1))] | |
12606 | { | |
12607 | PUT_MODE (operands[1], QImode); | |
12608 | }) | |
12609 | ||
12610 | (define_split | |
12611 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
12612 | (eq:QI (match_operator 1 "ix86_comparison_operator" | |
12613 | [(reg 17) (const_int 0)]) | |
12614 | (const_int 0)))] | |
12615 | "" | |
12616 | [(set (match_dup 0) (match_dup 1))] | |
12617 | { | |
12618 | rtx new_op1 = copy_rtx (operands[1]); | |
12619 | operands[1] = new_op1; | |
12620 | PUT_MODE (new_op1, QImode); | |
12621 | PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1), | |
12622 | GET_MODE (XEXP (new_op1, 0)))); | |
12623 | ||
12624 | /* Make sure that (a) the CCmode we have for the flags is strong | |
12625 | enough for the reversed compare or (b) we have a valid FP compare. */ | |
12626 | if (! ix86_comparison_operator (new_op1, VOIDmode)) | |
12627 | FAIL; | |
12628 | }) | |
12629 | ||
12630 | (define_split | |
12631 | [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) | |
12632 | (eq:QI (match_operator 1 "ix86_comparison_operator" | |
12633 | [(reg 17) (const_int 0)]) | |
12634 | (const_int 0)))] | |
12635 | "" | |
12636 | [(set (match_dup 0) (match_dup 1))] | |
12637 | { | |
12638 | rtx new_op1 = copy_rtx (operands[1]); | |
12639 | operands[1] = new_op1; | |
12640 | PUT_MODE (new_op1, QImode); | |
12641 | PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1), | |
12642 | GET_MODE (XEXP (new_op1, 0)))); | |
12643 | ||
12644 | /* Make sure that (a) the CCmode we have for the flags is strong | |
12645 | enough for the reversed compare or (b) we have a valid FP compare. */ | |
12646 | if (! ix86_comparison_operator (new_op1, VOIDmode)) | |
12647 | FAIL; | |
12648 | }) | |
12649 | ||
a46d1d38 JH |
12650 | ;; The SSE store flag instructions saves 0 or 0xffffffff to the result. |
12651 | ;; subsequent logical operations are used to imitate conditional moves. | |
12652 | ;; 0xffffffff is NaN, but not in normalized form, so we can't represent | |
12653 | ;; it directly. Futher holding this value in pseudo register might bring | |
12654 | ;; problem in implicit normalization in spill code. | |
12655 | ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these | |
12656 | ;; instructions after reload by splitting the conditional move patterns. | |
12657 | ||
12658 | (define_insn "*sse_setccsf" | |
12659 | [(set (match_operand:SF 0 "register_operand" "=x") | |
12660 | (match_operator:SF 1 "sse_comparison_operator" | |
12661 | [(match_operand:SF 2 "register_operand" "0") | |
12662 | (match_operand:SF 3 "nonimmediate_operand" "xm")]))] | |
12663 | "TARGET_SSE && reload_completed" | |
0f40f9f7 | 12664 | "cmp%D1ss\t{%3, %0|%0, %3}" |
3d34cd91 | 12665 | [(set_attr "type" "ssecmp") |
a46d1d38 JH |
12666 | (set_attr "mode" "SF")]) |
12667 | ||
12668 | (define_insn "*sse_setccdf" | |
12669 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
12670 | (match_operator:DF 1 "sse_comparison_operator" | |
12671 | [(match_operand:DF 2 "register_operand" "0") | |
12672 | (match_operand:DF 3 "nonimmediate_operand" "Ym")]))] | |
12673 | "TARGET_SSE2 && reload_completed" | |
0f40f9f7 | 12674 | "cmp%D1sd\t{%3, %0|%0, %3}" |
3d34cd91 | 12675 | [(set_attr "type" "ssecmp") |
a46d1d38 | 12676 | (set_attr "mode" "DF")]) |
886c62d1 JVA |
12677 | \f |
12678 | ;; Basic conditional jump instructions. | |
12679 | ;; We ignore the overflow flag for signed branch instructions. | |
12680 | ||
c572e5ba | 12681 | ;; For all bCOND expanders, also expand the compare or test insn that |
e075ae69 | 12682 | ;; generates reg 17. Generate an equality comparison if `beq' or `bne'. |
c572e5ba JVA |
12683 | |
12684 | (define_expand "beq" | |
e075ae69 RH |
12685 | [(set (pc) |
12686 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12687 | (label_ref (match_operand 0 "" "")) |
12688 | (pc)))] | |
12689 | "" | |
3a3677ff | 12690 | "ix86_expand_branch (EQ, operands[0]); DONE;") |
c572e5ba | 12691 | |
c572e5ba | 12692 | (define_expand "bne" |
e075ae69 RH |
12693 | [(set (pc) |
12694 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12695 | (label_ref (match_operand 0 "" "")) |
12696 | (pc)))] | |
12697 | "" | |
3a3677ff | 12698 | "ix86_expand_branch (NE, operands[0]); DONE;") |
886c62d1 | 12699 | |
c572e5ba | 12700 | (define_expand "bgt" |
e075ae69 RH |
12701 | [(set (pc) |
12702 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12703 | (label_ref (match_operand 0 "" "")) |
12704 | (pc)))] | |
12705 | "" | |
3a3677ff | 12706 | "ix86_expand_branch (GT, operands[0]); DONE;") |
c572e5ba | 12707 | |
c572e5ba | 12708 | (define_expand "bgtu" |
e075ae69 RH |
12709 | [(set (pc) |
12710 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12711 | (label_ref (match_operand 0 "" "")) |
12712 | (pc)))] | |
12713 | "" | |
3a3677ff | 12714 | "ix86_expand_branch (GTU, operands[0]); DONE;") |
886c62d1 | 12715 | |
886c62d1 | 12716 | (define_expand "blt" |
e075ae69 RH |
12717 | [(set (pc) |
12718 | (if_then_else (match_dup 1) | |
886c62d1 JVA |
12719 | (label_ref (match_operand 0 "" "")) |
12720 | (pc)))] | |
12721 | "" | |
3a3677ff | 12722 | "ix86_expand_branch (LT, operands[0]); DONE;") |
886c62d1 | 12723 | |
c572e5ba | 12724 | (define_expand "bltu" |
e075ae69 RH |
12725 | [(set (pc) |
12726 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12727 | (label_ref (match_operand 0 "" "")) |
12728 | (pc)))] | |
12729 | "" | |
3a3677ff | 12730 | "ix86_expand_branch (LTU, operands[0]); DONE;") |
c572e5ba | 12731 | |
c572e5ba | 12732 | (define_expand "bge" |
e075ae69 RH |
12733 | [(set (pc) |
12734 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12735 | (label_ref (match_operand 0 "" "")) |
12736 | (pc)))] | |
12737 | "" | |
3a3677ff | 12738 | "ix86_expand_branch (GE, operands[0]); DONE;") |
c572e5ba | 12739 | |
c572e5ba | 12740 | (define_expand "bgeu" |
e075ae69 RH |
12741 | [(set (pc) |
12742 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12743 | (label_ref (match_operand 0 "" "")) |
12744 | (pc)))] | |
12745 | "" | |
3a3677ff | 12746 | "ix86_expand_branch (GEU, operands[0]); DONE;") |
886c62d1 | 12747 | |
886c62d1 | 12748 | (define_expand "ble" |
e075ae69 RH |
12749 | [(set (pc) |
12750 | (if_then_else (match_dup 1) | |
886c62d1 JVA |
12751 | (label_ref (match_operand 0 "" "")) |
12752 | (pc)))] | |
12753 | "" | |
3a3677ff | 12754 | "ix86_expand_branch (LE, operands[0]); DONE;") |
886c62d1 | 12755 | |
c572e5ba | 12756 | (define_expand "bleu" |
e075ae69 RH |
12757 | [(set (pc) |
12758 | (if_then_else (match_dup 1) | |
c572e5ba JVA |
12759 | (label_ref (match_operand 0 "" "")) |
12760 | (pc)))] | |
12761 | "" | |
3a3677ff RH |
12762 | "ix86_expand_branch (LEU, operands[0]); DONE;") |
12763 | ||
12764 | (define_expand "bunordered" | |
12765 | [(set (pc) | |
12766 | (if_then_else (match_dup 1) | |
12767 | (label_ref (match_operand 0 "" "")) | |
12768 | (pc)))] | |
0644b628 | 12769 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12770 | "ix86_expand_branch (UNORDERED, operands[0]); DONE;") |
12771 | ||
12772 | (define_expand "bordered" | |
12773 | [(set (pc) | |
12774 | (if_then_else (match_dup 1) | |
12775 | (label_ref (match_operand 0 "" "")) | |
12776 | (pc)))] | |
0644b628 | 12777 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12778 | "ix86_expand_branch (ORDERED, operands[0]); DONE;") |
12779 | ||
12780 | (define_expand "buneq" | |
12781 | [(set (pc) | |
12782 | (if_then_else (match_dup 1) | |
12783 | (label_ref (match_operand 0 "" "")) | |
12784 | (pc)))] | |
0644b628 | 12785 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12786 | "ix86_expand_branch (UNEQ, operands[0]); DONE;") |
12787 | ||
12788 | (define_expand "bunge" | |
12789 | [(set (pc) | |
12790 | (if_then_else (match_dup 1) | |
12791 | (label_ref (match_operand 0 "" "")) | |
12792 | (pc)))] | |
0644b628 | 12793 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12794 | "ix86_expand_branch (UNGE, operands[0]); DONE;") |
12795 | ||
12796 | (define_expand "bungt" | |
12797 | [(set (pc) | |
12798 | (if_then_else (match_dup 1) | |
12799 | (label_ref (match_operand 0 "" "")) | |
12800 | (pc)))] | |
0644b628 | 12801 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12802 | "ix86_expand_branch (UNGT, operands[0]); DONE;") |
12803 | ||
12804 | (define_expand "bunle" | |
12805 | [(set (pc) | |
12806 | (if_then_else (match_dup 1) | |
12807 | (label_ref (match_operand 0 "" "")) | |
12808 | (pc)))] | |
0644b628 | 12809 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12810 | "ix86_expand_branch (UNLE, operands[0]); DONE;") |
12811 | ||
12812 | (define_expand "bunlt" | |
12813 | [(set (pc) | |
12814 | (if_then_else (match_dup 1) | |
12815 | (label_ref (match_operand 0 "" "")) | |
12816 | (pc)))] | |
0644b628 | 12817 | "TARGET_80387 || TARGET_SSE" |
3a3677ff RH |
12818 | "ix86_expand_branch (UNLT, operands[0]); DONE;") |
12819 | ||
12820 | (define_expand "bltgt" | |
12821 | [(set (pc) | |
12822 | (if_then_else (match_dup 1) | |
12823 | (label_ref (match_operand 0 "" "")) | |
12824 | (pc)))] | |
0644b628 | 12825 | "TARGET_80387 || TARGET_SSE" |
3a3677ff | 12826 | "ix86_expand_branch (LTGT, operands[0]); DONE;") |
886c62d1 | 12827 | |
e075ae69 RH |
12828 | (define_insn "*jcc_1" |
12829 | [(set (pc) | |
9076b9c1 | 12830 | (if_then_else (match_operator 1 "ix86_comparison_operator" |
e075ae69 | 12831 | [(reg 17) (const_int 0)]) |
6ef67412 | 12832 | (label_ref (match_operand 0 "" "")) |
e075ae69 RH |
12833 | (pc)))] |
12834 | "" | |
0f40f9f7 | 12835 | "%+j%C1\t%l0" |
e075ae69 | 12836 | [(set_attr "type" "ibr") |
c7375e61 | 12837 | (set_attr "modrm" "0") |
6ef67412 JH |
12838 | (set (attr "prefix_0f") |
12839 | (if_then_else (and (ge (minus (match_dup 0) (pc)) | |
12840 | (const_int -128)) | |
12841 | (lt (minus (match_dup 0) (pc)) | |
12842 | (const_int 124))) | |
12843 | (const_int 0) | |
12844 | (const_int 1)))]) | |
e075ae69 RH |
12845 | |
12846 | (define_insn "*jcc_2" | |
12847 | [(set (pc) | |
9076b9c1 | 12848 | (if_then_else (match_operator 1 "ix86_comparison_operator" |
e075ae69 RH |
12849 | [(reg 17) (const_int 0)]) |
12850 | (pc) | |
6ef67412 | 12851 | (label_ref (match_operand 0 "" ""))))] |
e075ae69 | 12852 | "" |
0f40f9f7 | 12853 | "%+j%c1\t%l0" |
e075ae69 | 12854 | [(set_attr "type" "ibr") |
c7375e61 | 12855 | (set_attr "modrm" "0") |
6ef67412 JH |
12856 | (set (attr "prefix_0f") |
12857 | (if_then_else (and (ge (minus (match_dup 0) (pc)) | |
12858 | (const_int -128)) | |
12859 | (lt (minus (match_dup 0) (pc)) | |
12860 | (const_int 124))) | |
12861 | (const_int 0) | |
12862 | (const_int 1)))]) | |
e075ae69 | 12863 | |
592188a5 RH |
12864 | ;; In general it is not safe to assume too much about CCmode registers, |
12865 | ;; so simplify-rtx stops when it sees a second one. Under certain | |
12866 | ;; conditions this is safe on x86, so help combine not create | |
12867 | ;; | |
12868 | ;; seta %al | |
12869 | ;; testb %al, %al | |
12870 | ;; je Lfoo | |
12871 | ||
12872 | (define_split | |
12873 | [(set (pc) | |
12874 | (if_then_else (ne (match_operator 0 "ix86_comparison_operator" | |
12875 | [(reg 17) (const_int 0)]) | |
12876 | (const_int 0)) | |
12877 | (label_ref (match_operand 1 "" "")) | |
12878 | (pc)))] | |
12879 | "" | |
12880 | [(set (pc) | |
12881 | (if_then_else (match_dup 0) | |
12882 | (label_ref (match_dup 1)) | |
12883 | (pc)))] | |
12884 | { | |
12885 | PUT_MODE (operands[0], VOIDmode); | |
12886 | }) | |
12887 | ||
12888 | (define_split | |
12889 | [(set (pc) | |
12890 | (if_then_else (eq (match_operator 0 "ix86_comparison_operator" | |
12891 | [(reg 17) (const_int 0)]) | |
12892 | (const_int 0)) | |
12893 | (label_ref (match_operand 1 "" "")) | |
12894 | (pc)))] | |
12895 | "" | |
12896 | [(set (pc) | |
12897 | (if_then_else (match_dup 0) | |
12898 | (label_ref (match_dup 1)) | |
12899 | (pc)))] | |
12900 | { | |
12901 | rtx new_op0 = copy_rtx (operands[0]); | |
12902 | operands[0] = new_op0; | |
12903 | PUT_MODE (new_op0, VOIDmode); | |
12904 | PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0), | |
12905 | GET_MODE (XEXP (new_op0, 0)))); | |
12906 | ||
12907 | /* Make sure that (a) the CCmode we have for the flags is strong | |
12908 | enough for the reversed compare or (b) we have a valid FP compare. */ | |
12909 | if (! ix86_comparison_operator (new_op0, VOIDmode)) | |
12910 | FAIL; | |
12911 | }) | |
12912 | ||
3a3677ff RH |
12913 | ;; Define combination compare-and-branch fp compare instructions to use |
12914 | ;; during early optimization. Splitting the operation apart early makes | |
12915 | ;; for bad code when we want to reverse the operation. | |
12916 | ||
12917 | (define_insn "*fp_jcc_1" | |
12918 | [(set (pc) | |
12919 | (if_then_else (match_operator 0 "comparison_operator" | |
12920 | [(match_operand 1 "register_operand" "f") | |
12921 | (match_operand 2 "register_operand" "f")]) | |
12922 | (label_ref (match_operand 3 "" "")) | |
12923 | (pc))) | |
12924 | (clobber (reg:CCFP 18)) | |
12925 | (clobber (reg:CCFP 17))] | |
12926 | "TARGET_CMOVE && TARGET_80387 | |
0644b628 | 12927 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1])) |
3a3677ff | 12928 | && FLOAT_MODE_P (GET_MODE (operands[1])) |
03598dea JH |
12929 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12930 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
12931 | "#") |
12932 | ||
0644b628 JH |
12933 | (define_insn "*fp_jcc_1_sse" |
12934 | [(set (pc) | |
12935 | (if_then_else (match_operator 0 "comparison_operator" | |
12936 | [(match_operand 1 "register_operand" "f#x,x#f") | |
12937 | (match_operand 2 "nonimmediate_operand" "f#x,xm#f")]) | |
12938 | (label_ref (match_operand 3 "" "")) | |
12939 | (pc))) | |
12940 | (clobber (reg:CCFP 18)) | |
12941 | (clobber (reg:CCFP 17))] | |
12942 | "TARGET_80387 | |
12943 | && SSE_FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
12944 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12945 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
0644b628 JH |
12946 | "#") |
12947 | ||
12948 | (define_insn "*fp_jcc_1_sse_only" | |
12949 | [(set (pc) | |
12950 | (if_then_else (match_operator 0 "comparison_operator" | |
12951 | [(match_operand 1 "register_operand" "x") | |
12952 | (match_operand 2 "nonimmediate_operand" "xm")]) | |
12953 | (label_ref (match_operand 3 "" "")) | |
12954 | (pc))) | |
12955 | (clobber (reg:CCFP 18)) | |
12956 | (clobber (reg:CCFP 17))] | |
12957 | "SSE_FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
12958 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12959 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
0644b628 JH |
12960 | "#") |
12961 | ||
3a3677ff RH |
12962 | (define_insn "*fp_jcc_2" |
12963 | [(set (pc) | |
12964 | (if_then_else (match_operator 0 "comparison_operator" | |
12965 | [(match_operand 1 "register_operand" "f") | |
12966 | (match_operand 2 "register_operand" "f")]) | |
12967 | (pc) | |
12968 | (label_ref (match_operand 3 "" "")))) | |
12969 | (clobber (reg:CCFP 18)) | |
12970 | (clobber (reg:CCFP 17))] | |
12971 | "TARGET_CMOVE && TARGET_80387 | |
0644b628 | 12972 | && !SSE_FLOAT_MODE_P (GET_MODE (operands[1])) |
3a3677ff | 12973 | && FLOAT_MODE_P (GET_MODE (operands[1])) |
03598dea JH |
12974 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12975 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
12976 | "#") |
12977 | ||
0644b628 JH |
12978 | (define_insn "*fp_jcc_2_sse" |
12979 | [(set (pc) | |
12980 | (if_then_else (match_operator 0 "comparison_operator" | |
12981 | [(match_operand 1 "register_operand" "f#x,x#f") | |
12982 | (match_operand 2 "nonimmediate_operand" "f#x,xm#f")]) | |
12983 | (pc) | |
12984 | (label_ref (match_operand 3 "" "")))) | |
12985 | (clobber (reg:CCFP 18)) | |
12986 | (clobber (reg:CCFP 17))] | |
12987 | "TARGET_80387 | |
12988 | && SSE_FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
12989 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
12990 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
0644b628 JH |
12991 | "#") |
12992 | ||
12993 | (define_insn "*fp_jcc_2_sse_only" | |
12994 | [(set (pc) | |
12995 | (if_then_else (match_operator 0 "comparison_operator" | |
12996 | [(match_operand 1 "register_operand" "x") | |
12997 | (match_operand 2 "nonimmediate_operand" "xm")]) | |
12998 | (pc) | |
12999 | (label_ref (match_operand 3 "" "")))) | |
13000 | (clobber (reg:CCFP 18)) | |
13001 | (clobber (reg:CCFP 17))] | |
13002 | "SSE_FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
13003 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
13004 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
0644b628 JH |
13005 | "#") |
13006 | ||
3a3677ff RH |
13007 | (define_insn "*fp_jcc_3" |
13008 | [(set (pc) | |
b1cdafbb | 13009 | (if_then_else (match_operator 0 "comparison_operator" |
3a3677ff RH |
13010 | [(match_operand 1 "register_operand" "f") |
13011 | (match_operand 2 "nonimmediate_operand" "fm")]) | |
13012 | (label_ref (match_operand 3 "" "")) | |
13013 | (pc))) | |
13014 | (clobber (reg:CCFP 18)) | |
13015 | (clobber (reg:CCFP 17)) | |
13016 | (clobber (match_scratch:HI 4 "=a"))] | |
13017 | "TARGET_80387 | |
13018 | && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode) | |
a940d8bd | 13019 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
b1cdafbb JH |
13020 | && !ix86_use_fcomi_compare (GET_CODE (operands[0])) |
13021 | && SELECT_CC_MODE (GET_CODE (operands[0]), | |
03598dea JH |
13022 | operands[1], operands[2]) == CCFPmode |
13023 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
13024 | "#") |
13025 | ||
13026 | (define_insn "*fp_jcc_4" | |
13027 | [(set (pc) | |
b1cdafbb | 13028 | (if_then_else (match_operator 0 "comparison_operator" |
3a3677ff RH |
13029 | [(match_operand 1 "register_operand" "f") |
13030 | (match_operand 2 "nonimmediate_operand" "fm")]) | |
13031 | (pc) | |
13032 | (label_ref (match_operand 3 "" "")))) | |
13033 | (clobber (reg:CCFP 18)) | |
13034 | (clobber (reg:CCFP 17)) | |
13035 | (clobber (match_scratch:HI 4 "=a"))] | |
13036 | "TARGET_80387 | |
13037 | && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode) | |
a940d8bd | 13038 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
b1cdafbb JH |
13039 | && !ix86_use_fcomi_compare (GET_CODE (operands[0])) |
13040 | && SELECT_CC_MODE (GET_CODE (operands[0]), | |
03598dea JH |
13041 | operands[1], operands[2]) == CCFPmode |
13042 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
13043 | "#") |
13044 | ||
13045 | (define_insn "*fp_jcc_5" | |
13046 | [(set (pc) | |
13047 | (if_then_else (match_operator 0 "comparison_operator" | |
13048 | [(match_operand 1 "register_operand" "f") | |
13049 | (match_operand 2 "register_operand" "f")]) | |
13050 | (label_ref (match_operand 3 "" "")) | |
13051 | (pc))) | |
13052 | (clobber (reg:CCFP 18)) | |
13053 | (clobber (reg:CCFP 17)) | |
13054 | (clobber (match_scratch:HI 4 "=a"))] | |
13055 | "TARGET_80387 | |
13056 | && FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
13057 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
13058 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
13059 | "#") |
13060 | ||
13061 | (define_insn "*fp_jcc_6" | |
13062 | [(set (pc) | |
13063 | (if_then_else (match_operator 0 "comparison_operator" | |
13064 | [(match_operand 1 "register_operand" "f") | |
13065 | (match_operand 2 "register_operand" "f")]) | |
13066 | (pc) | |
13067 | (label_ref (match_operand 3 "" "")))) | |
13068 | (clobber (reg:CCFP 18)) | |
13069 | (clobber (reg:CCFP 17)) | |
13070 | (clobber (match_scratch:HI 4 "=a"))] | |
13071 | "TARGET_80387 | |
13072 | && FLOAT_MODE_P (GET_MODE (operands[1])) | |
03598dea JH |
13073 | && GET_MODE (operands[1]) == GET_MODE (operands[2]) |
13074 | && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" | |
3a3677ff RH |
13075 | "#") |
13076 | ||
13077 | (define_split | |
13078 | [(set (pc) | |
13079 | (if_then_else (match_operator 0 "comparison_operator" | |
13080 | [(match_operand 1 "register_operand" "") | |
13081 | (match_operand 2 "nonimmediate_operand" "")]) | |
13082 | (match_operand 3 "" "") | |
13083 | (match_operand 4 "" ""))) | |
13084 | (clobber (reg:CCFP 18)) | |
13085 | (clobber (reg:CCFP 17))] | |
13086 | "reload_completed" | |
9e7adcb3 | 13087 | [(const_int 0)] |
3a3677ff | 13088 | { |
03598dea | 13089 | ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2], |
9e7adcb3 JH |
13090 | operands[3], operands[4], NULL_RTX); |
13091 | DONE; | |
0f40f9f7 | 13092 | }) |
3a3677ff RH |
13093 | |
13094 | (define_split | |
13095 | [(set (pc) | |
13096 | (if_then_else (match_operator 0 "comparison_operator" | |
13097 | [(match_operand 1 "register_operand" "") | |
13098 | (match_operand 2 "nonimmediate_operand" "")]) | |
13099 | (match_operand 3 "" "") | |
13100 | (match_operand 4 "" ""))) | |
13101 | (clobber (reg:CCFP 18)) | |
13102 | (clobber (reg:CCFP 17)) | |
13103 | (clobber (match_scratch:HI 5 "=a"))] | |
13104 | "reload_completed" | |
13105 | [(set (pc) | |
13106 | (if_then_else (match_dup 6) | |
13107 | (match_dup 3) | |
13108 | (match_dup 4)))] | |
3a3677ff | 13109 | { |
03598dea | 13110 | ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2], |
9e7adcb3 JH |
13111 | operands[3], operands[4], operands[5]); |
13112 | DONE; | |
0f40f9f7 | 13113 | }) |
886c62d1 JVA |
13114 | \f |
13115 | ;; Unconditional and other jump instructions | |
13116 | ||
13117 | (define_insn "jump" | |
13118 | [(set (pc) | |
13119 | (label_ref (match_operand 0 "" "")))] | |
13120 | "" | |
0f40f9f7 | 13121 | "jmp\t%l0" |
c7375e61 EB |
13122 | [(set_attr "type" "ibr") |
13123 | (set_attr "modrm" "0")]) | |
886c62d1 | 13124 | |
14f73b5a JH |
13125 | (define_expand "indirect_jump" |
13126 | [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))] | |
886c62d1 | 13127 | "" |
14f73b5a JH |
13128 | "") |
13129 | ||
13130 | (define_insn "*indirect_jump" | |
13131 | [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))] | |
13132 | "!TARGET_64BIT" | |
13133 | "jmp\t%A0" | |
13134 | [(set_attr "type" "ibr") | |
13135 | (set_attr "length_immediate" "0")]) | |
13136 | ||
13137 | (define_insn "*indirect_jump_rtx64" | |
13138 | [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))] | |
13139 | "TARGET_64BIT" | |
0f40f9f7 | 13140 | "jmp\t%A0" |
6ef67412 JH |
13141 | [(set_attr "type" "ibr") |
13142 | (set_attr "length_immediate" "0")]) | |
4801403e | 13143 | |
90675921 | 13144 | (define_expand "tablejump" |
6eb791fc | 13145 | [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm")) |
90675921 RH |
13146 | (use (label_ref (match_operand 1 "" "")))])] |
13147 | "" | |
13148 | { | |
66edd3b4 RH |
13149 | /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit) |
13150 | relative. Convert the relative address to an absolute address. */ | |
90675921 RH |
13151 | if (flag_pic) |
13152 | { | |
66edd3b4 RH |
13153 | rtx op0, op1; |
13154 | enum rtx_code code; | |
13155 | ||
6eb791fc | 13156 | if (TARGET_64BIT) |
66edd3b4 RH |
13157 | { |
13158 | code = PLUS; | |
13159 | op0 = operands[0]; | |
13160 | op1 = gen_rtx_LABEL_REF (Pmode, operands[1]); | |
13161 | } | |
b069de3b | 13162 | else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA) |
f88c65f7 | 13163 | { |
66edd3b4 RH |
13164 | code = PLUS; |
13165 | op0 = operands[0]; | |
13166 | op1 = pic_offset_table_rtx; | |
f88c65f7 | 13167 | } |
6eb791fc JH |
13168 | else |
13169 | { | |
66edd3b4 RH |
13170 | code = MINUS; |
13171 | op0 = pic_offset_table_rtx; | |
13172 | op1 = operands[0]; | |
6eb791fc | 13173 | } |
66edd3b4 | 13174 | |
c16576e6 | 13175 | operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0, |
66edd3b4 | 13176 | OPTAB_DIRECT); |
90675921 | 13177 | } |
0f40f9f7 | 13178 | }) |
2bb7a0f5 | 13179 | |
90675921 | 13180 | (define_insn "*tablejump_1" |
2ae0f82c | 13181 | [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm")) |
886c62d1 | 13182 | (use (label_ref (match_operand 1 "" "")))] |
14f73b5a JH |
13183 | "!TARGET_64BIT" |
13184 | "jmp\t%A0" | |
13185 | [(set_attr "type" "ibr") | |
13186 | (set_attr "length_immediate" "0")]) | |
13187 | ||
13188 | (define_insn "*tablejump_1_rtx64" | |
13189 | [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm")) | |
13190 | (use (label_ref (match_operand 1 "" "")))] | |
13191 | "TARGET_64BIT" | |
0f40f9f7 | 13192 | "jmp\t%A0" |
6ef67412 JH |
13193 | [(set_attr "type" "ibr") |
13194 | (set_attr "length_immediate" "0")]) | |
e075ae69 RH |
13195 | \f |
13196 | ;; Loop instruction | |
13197 | ;; | |
13198 | ;; This is all complicated by the fact that since this is a jump insn | |
13199 | ;; we must handle our own reloads. | |
13200 | ||
5527bf14 RH |
13201 | (define_expand "doloop_end" |
13202 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13203 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13204 | (use (match_operand 2 "" "")) ; max iterations | |
13205 | (use (match_operand 3 "" "")) ; loop level | |
13206 | (use (match_operand 4 "" ""))] ; label | |
1b0c37d7 | 13207 | "!TARGET_64BIT && TARGET_USE_LOOP" |
5527bf14 RH |
13208 | " |
13209 | { | |
13210 | /* Only use cloop on innermost loops. */ | |
13211 | if (INTVAL (operands[3]) > 1) | |
13212 | FAIL; | |
13213 | if (GET_MODE (operands[0]) != SImode) | |
13214 | FAIL; | |
13215 | emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0], | |
13216 | operands[0])); | |
13217 | DONE; | |
13218 | }") | |
e075ae69 | 13219 | |
5527bf14 | 13220 | (define_insn "doloop_end_internal" |
e075ae69 | 13221 | [(set (pc) |
5527bf14 | 13222 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r") |
e075ae69 RH |
13223 | (const_int 1)) |
13224 | (label_ref (match_operand 0 "" "")) | |
13225 | (pc))) | |
5527bf14 | 13226 | (set (match_operand:SI 2 "register_operand" "=1,1,*m*r") |
e075ae69 RH |
13227 | (plus:SI (match_dup 1) |
13228 | (const_int -1))) | |
13229 | (clobber (match_scratch:SI 3 "=X,X,r")) | |
13230 | (clobber (reg:CC 17))] | |
1b0c37d7 | 13231 | "!TARGET_64BIT && TARGET_USE_LOOP" |
e075ae69 RH |
13232 | { |
13233 | if (which_alternative != 0) | |
0f40f9f7 | 13234 | return "#"; |
e075ae69 | 13235 | if (get_attr_length (insn) == 2) |
0f40f9f7 | 13236 | return "%+loop\t%l0"; |
e075ae69 | 13237 | else |
0f40f9f7 ZW |
13238 | return "dec{l}\t%1\;%+jne\t%l0"; |
13239 | } | |
6ef67412 | 13240 | [(set_attr "ppro_uops" "many") |
c7375e61 EB |
13241 | (set (attr "length") |
13242 | (if_then_else (and (eq_attr "alternative" "0") | |
13243 | (and (ge (minus (match_dup 0) (pc)) | |
13244 | (const_int -128)) | |
13245 | (lt (minus (match_dup 0) (pc)) | |
13246 | (const_int 124)))) | |
13247 | (const_int 2) | |
13248 | (const_int 16))) | |
6ef67412 | 13249 | (set (attr "type") |
e075ae69 RH |
13250 | (if_then_else (and (eq_attr "alternative" "0") |
13251 | (and (ge (minus (match_dup 0) (pc)) | |
13252 | (const_int -128)) | |
13253 | (lt (minus (match_dup 0) (pc)) | |
13254 | (const_int 124)))) | |
6ef67412 JH |
13255 | (const_string "ibr") |
13256 | (const_string "multi")))]) | |
e075ae69 | 13257 | |
e075ae69 RH |
13258 | (define_split |
13259 | [(set (pc) | |
13260 | (if_then_else (ne (match_operand:SI 1 "register_operand" "") | |
13261 | (const_int 1)) | |
13262 | (match_operand 0 "" "") | |
13263 | (pc))) | |
5527bf14 | 13264 | (set (match_dup 1) |
e075ae69 RH |
13265 | (plus:SI (match_dup 1) |
13266 | (const_int -1))) | |
5527bf14 | 13267 | (clobber (match_scratch:SI 2 "")) |
e075ae69 | 13268 | (clobber (reg:CC 17))] |
1b0c37d7 | 13269 | "!TARGET_64BIT && TARGET_USE_LOOP |
5527bf14 RH |
13270 | && reload_completed |
13271 | && REGNO (operands[1]) != 2" | |
13272 | [(parallel [(set (reg:CCZ 17) | |
13273 | (compare:CCZ (plus:SI (match_dup 1) (const_int -1)) | |
e075ae69 | 13274 | (const_int 0))) |
5527bf14 | 13275 | (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))]) |
16189740 | 13276 | (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0)) |
e075ae69 RH |
13277 | (match_dup 0) |
13278 | (pc)))] | |
13279 | "") | |
13280 | ||
13281 | (define_split | |
13282 | [(set (pc) | |
13283 | (if_then_else (ne (match_operand:SI 1 "register_operand" "") | |
13284 | (const_int 1)) | |
13285 | (match_operand 0 "" "") | |
13286 | (pc))) | |
5527bf14 | 13287 | (set (match_operand:SI 2 "nonimmediate_operand" "") |
e075ae69 RH |
13288 | (plus:SI (match_dup 1) |
13289 | (const_int -1))) | |
13290 | (clobber (match_scratch:SI 3 "")) | |
13291 | (clobber (reg:CC 17))] | |
1b0c37d7 | 13292 | "!TARGET_64BIT && TARGET_USE_LOOP |
5527bf14 RH |
13293 | && reload_completed |
13294 | && (! REG_P (operands[2]) | |
13295 | || ! rtx_equal_p (operands[1], operands[2]))" | |
e075ae69 | 13296 | [(set (match_dup 3) (match_dup 1)) |
16189740 RH |
13297 | (parallel [(set (reg:CCZ 17) |
13298 | (compare:CCZ (plus:SI (match_dup 3) (const_int -1)) | |
13299 | (const_int 0))) | |
e075ae69 RH |
13300 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) |
13301 | (set (match_dup 2) (match_dup 3)) | |
16189740 | 13302 | (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0)) |
e075ae69 RH |
13303 | (match_dup 0) |
13304 | (pc)))] | |
13305 | "") | |
c50e5bc0 RH |
13306 | |
13307 | ;; Convert setcc + movzbl to xor + setcc if operands don't overlap. | |
13308 | ||
13309 | (define_peephole2 | |
13310 | [(set (reg 17) (match_operand 0 "" "")) | |
13311 | (set (match_operand:QI 1 "register_operand" "") | |
13312 | (match_operator:QI 2 "ix86_comparison_operator" | |
13313 | [(reg 17) (const_int 0)])) | |
13314 | (set (match_operand 3 "q_regs_operand" "") | |
13315 | (zero_extend (match_dup 1)))] | |
646ded90 RH |
13316 | "(peep2_reg_dead_p (3, operands[1]) |
13317 | || operands_match_p (operands[1], operands[3])) | |
c50e5bc0 | 13318 | && ! reg_overlap_mentioned_p (operands[3], operands[0])" |
646ded90 RH |
13319 | [(set (match_dup 4) (match_dup 0)) |
13320 | (set (strict_low_part (match_dup 5)) | |
13321 | (match_dup 2))] | |
13322 | { | |
13323 | operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17); | |
13324 | operands[5] = gen_rtx_REG (QImode, REGNO (operands[3])); | |
a8bac9ab | 13325 | ix86_expand_clear (operands[3]); |
646ded90 RH |
13326 | }) |
13327 | ||
13328 | ;; Similar, but match zero_extendhisi2_and, which adds a clobber. | |
13329 | ||
13330 | (define_peephole2 | |
13331 | [(set (reg 17) (match_operand 0 "" "")) | |
13332 | (set (match_operand:QI 1 "register_operand" "") | |
13333 | (match_operator:QI 2 "ix86_comparison_operator" | |
13334 | [(reg 17) (const_int 0)])) | |
13335 | (parallel [(set (match_operand 3 "q_regs_operand" "") | |
13336 | (zero_extend (match_dup 1))) | |
13337 | (clobber (reg:CC 17))])] | |
13338 | "(peep2_reg_dead_p (3, operands[1]) | |
13339 | || operands_match_p (operands[1], operands[3])) | |
13340 | && ! reg_overlap_mentioned_p (operands[3], operands[0])" | |
13341 | [(set (match_dup 4) (match_dup 0)) | |
c50e5bc0 RH |
13342 | (set (strict_low_part (match_dup 5)) |
13343 | (match_dup 2))] | |
646ded90 RH |
13344 | { |
13345 | operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17); | |
13346 | operands[5] = gen_rtx_REG (QImode, REGNO (operands[3])); | |
a8bac9ab | 13347 | ix86_expand_clear (operands[3]); |
646ded90 | 13348 | }) |
e075ae69 RH |
13349 | \f |
13350 | ;; Call instructions. | |
2bb7a0f5 | 13351 | |
cbbf65e0 RH |
13352 | ;; The predicates normally associated with named expanders are not properly |
13353 | ;; checked for calls. This is a bug in the generic code, but it isn't that | |
13354 | ;; easy to fix. Ignore it for now and be prepared to fix things up. | |
2bb7a0f5 | 13355 | |
886c62d1 JVA |
13356 | ;; Call subroutine returning no value. |
13357 | ||
2bb7a0f5 | 13358 | (define_expand "call_pop" |
cbbf65e0 RH |
13359 | [(parallel [(call (match_operand:QI 0 "" "") |
13360 | (match_operand:SI 1 "" "")) | |
2bb7a0f5 RS |
13361 | (set (reg:SI 7) |
13362 | (plus:SI (reg:SI 7) | |
cbbf65e0 | 13363 | (match_operand:SI 3 "" "")))])] |
1e07edd3 | 13364 | "!TARGET_64BIT" |
2bb7a0f5 | 13365 | { |
0e07aff3 RH |
13366 | ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3]); |
13367 | DONE; | |
0f40f9f7 | 13368 | }) |
2bb7a0f5 | 13369 | |
94bb5d0c | 13370 | (define_insn "*call_pop_0" |
e1ff012c | 13371 | [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" "")) |
94bb5d0c RH |
13372 | (match_operand:SI 1 "" "")) |
13373 | (set (reg:SI 7) (plus:SI (reg:SI 7) | |
90d10fb9 | 13374 | (match_operand:SI 2 "immediate_operand" "")))] |
1e07edd3 | 13375 | "!TARGET_64BIT" |
94bb5d0c RH |
13376 | { |
13377 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13378 | return "jmp\t%P0"; |
94bb5d0c | 13379 | else |
0f40f9f7 ZW |
13380 | return "call\t%P0"; |
13381 | } | |
94bb5d0c RH |
13382 | [(set_attr "type" "call")]) |
13383 | ||
cbbf65e0 | 13384 | (define_insn "*call_pop_1" |
e1ff012c | 13385 | [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm")) |
94bb5d0c | 13386 | (match_operand:SI 1 "" "")) |
886c62d1 | 13387 | (set (reg:SI 7) (plus:SI (reg:SI 7) |
90d10fb9 | 13388 | (match_operand:SI 2 "immediate_operand" "i")))] |
1e07edd3 | 13389 | "!TARGET_64BIT" |
886c62d1 | 13390 | { |
e1ff012c | 13391 | if (constant_call_address_operand (operands[0], Pmode)) |
94bb5d0c RH |
13392 | { |
13393 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13394 | return "jmp\t%P0"; |
94bb5d0c | 13395 | else |
0f40f9f7 | 13396 | return "call\t%P0"; |
94bb5d0c | 13397 | } |
94bb5d0c | 13398 | if (SIBLING_CALL_P (insn)) |
0f40f9f7 | 13399 | return "jmp\t%A0"; |
94bb5d0c | 13400 | else |
0f40f9f7 ZW |
13401 | return "call\t%A0"; |
13402 | } | |
e075ae69 | 13403 | [(set_attr "type" "call")]) |
886c62d1 | 13404 | |
2bb7a0f5 | 13405 | (define_expand "call" |
cbbf65e0 | 13406 | [(call (match_operand:QI 0 "" "") |
39d04363 JH |
13407 | (match_operand 1 "" "")) |
13408 | (use (match_operand 2 "" ""))] | |
2bb7a0f5 | 13409 | "" |
2bb7a0f5 | 13410 | { |
0e07aff3 RH |
13411 | ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL); |
13412 | DONE; | |
0f40f9f7 | 13413 | }) |
2bb7a0f5 | 13414 | |
94bb5d0c | 13415 | (define_insn "*call_0" |
32ee7d1d JH |
13416 | [(call (mem:QI (match_operand 0 "constant_call_address_operand" "")) |
13417 | (match_operand 1 "" ""))] | |
94bb5d0c | 13418 | "" |
94bb5d0c RH |
13419 | { |
13420 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13421 | return "jmp\t%P0"; |
94bb5d0c | 13422 | else |
0f40f9f7 ZW |
13423 | return "call\t%P0"; |
13424 | } | |
94bb5d0c RH |
13425 | [(set_attr "type" "call")]) |
13426 | ||
cbbf65e0 | 13427 | (define_insn "*call_1" |
e1ff012c | 13428 | [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm")) |
32ee7d1d | 13429 | (match_operand 1 "" ""))] |
ac62a60e | 13430 | "!TARGET_64BIT" |
32ee7d1d JH |
13431 | { |
13432 | if (constant_call_address_operand (operands[0], QImode)) | |
13433 | { | |
13434 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13435 | return "jmp\t%P0"; |
32ee7d1d | 13436 | else |
0f40f9f7 | 13437 | return "call\t%P0"; |
32ee7d1d JH |
13438 | } |
13439 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13440 | return "jmp\t%A0"; |
32ee7d1d | 13441 | else |
0f40f9f7 ZW |
13442 | return "call\t%A0"; |
13443 | } | |
32ee7d1d JH |
13444 | [(set_attr "type" "call")]) |
13445 | ||
13446 | (define_insn "*call_1_rex64" | |
13447 | [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm")) | |
13448 | (match_operand 1 "" ""))] | |
ac62a60e | 13449 | "TARGET_64BIT" |
886c62d1 | 13450 | { |
94bb5d0c | 13451 | if (constant_call_address_operand (operands[0], QImode)) |
cbbf65e0 RH |
13452 | { |
13453 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 13454 | return "jmp\t%P0"; |
cbbf65e0 | 13455 | else |
0f40f9f7 | 13456 | return "call\t%P0"; |
cbbf65e0 | 13457 | } |
cbbf65e0 | 13458 | if (SIBLING_CALL_P (insn)) |
0f40f9f7 | 13459 | return "jmp\t%A0"; |
cbbf65e0 | 13460 | else |
0f40f9f7 ZW |
13461 | return "call\t%A0"; |
13462 | } | |
e075ae69 | 13463 | [(set_attr "type" "call")]) |
886c62d1 JVA |
13464 | |
13465 | ;; Call subroutine, returning value in operand 0 | |
886c62d1 | 13466 | |
2bb7a0f5 RS |
13467 | (define_expand "call_value_pop" |
13468 | [(parallel [(set (match_operand 0 "" "") | |
cbbf65e0 RH |
13469 | (call (match_operand:QI 1 "" "") |
13470 | (match_operand:SI 2 "" ""))) | |
2bb7a0f5 RS |
13471 | (set (reg:SI 7) |
13472 | (plus:SI (reg:SI 7) | |
cbbf65e0 | 13473 | (match_operand:SI 4 "" "")))])] |
1e07edd3 | 13474 | "!TARGET_64BIT" |
2bb7a0f5 | 13475 | { |
0e07aff3 RH |
13476 | ix86_expand_call (operands[0], operands[1], operands[2], |
13477 | operands[3], operands[4]); | |
13478 | DONE; | |
0f40f9f7 | 13479 | }) |
2bb7a0f5 | 13480 | |
2bb7a0f5 RS |
13481 | (define_expand "call_value" |
13482 | [(set (match_operand 0 "" "") | |
cbbf65e0 | 13483 | (call (match_operand:QI 1 "" "") |
39d04363 JH |
13484 | (match_operand:SI 2 "" ""))) |
13485 | (use (match_operand:SI 3 "" ""))] | |
2bb7a0f5 RS |
13486 | ;; Operand 2 not used on the i386. |
13487 | "" | |
2bb7a0f5 | 13488 | { |
0e07aff3 | 13489 | ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL); |
39d04363 | 13490 | DONE; |
0f40f9f7 | 13491 | }) |
2bb7a0f5 | 13492 | |
b840bfb0 MM |
13493 | ;; Call subroutine returning any type. |
13494 | ||
576182a3 | 13495 | (define_expand "untyped_call" |
b840bfb0 | 13496 | [(parallel [(call (match_operand 0 "" "") |
576182a3 | 13497 | (const_int 0)) |
b840bfb0 | 13498 | (match_operand 1 "" "") |
576182a3 TW |
13499 | (match_operand 2 "" "")])] |
13500 | "" | |
576182a3 | 13501 | { |
b840bfb0 | 13502 | int i; |
576182a3 | 13503 | |
d8b679b9 RK |
13504 | /* In order to give reg-stack an easier job in validating two |
13505 | coprocessor registers as containing a possible return value, | |
13506 | simply pretend the untyped call returns a complex long double | |
13507 | value. */ | |
74775c7a | 13508 | |
0e07aff3 RH |
13509 | ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387 |
13510 | ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL), | |
13511 | operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1), | |
13512 | NULL); | |
576182a3 | 13513 | |
b840bfb0 | 13514 | for (i = 0; i < XVECLEN (operands[2], 0); i++) |
576182a3 | 13515 | { |
b840bfb0 MM |
13516 | rtx set = XVECEXP (operands[2], 0, i); |
13517 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
576182a3 | 13518 | } |
576182a3 | 13519 | |
b840bfb0 MM |
13520 | /* The optimizer does not know that the call sets the function value |
13521 | registers we stored in the result block. We avoid problems by | |
13522 | claiming that all hard registers are used and clobbered at this | |
13523 | point. */ | |
66edd3b4 | 13524 | emit_insn (gen_blockage (const0_rtx)); |
576182a3 TW |
13525 | |
13526 | DONE; | |
0f40f9f7 | 13527 | }) |
e075ae69 RH |
13528 | \f |
13529 | ;; Prologue and epilogue instructions | |
576182a3 | 13530 | |
b840bfb0 MM |
13531 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
13532 | ;; all of memory. This blocks insns from being moved across this point. | |
13533 | ||
13534 | (define_insn "blockage" | |
66edd3b4 | 13535 | [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)] |
576182a3 | 13536 | "" |
90aec2cf | 13537 | "" |
e075ae69 | 13538 | [(set_attr "length" "0")]) |
576182a3 | 13539 | |
886c62d1 JVA |
13540 | ;; Insn emitted into the body of a function to return from a function. |
13541 | ;; This is only done if the function's epilogue is known to be simple. | |
182a4620 | 13542 | ;; See comments for ix86_can_use_return_insn_p in i386.c. |
886c62d1 | 13543 | |
5f3d14e3 | 13544 | (define_expand "return" |
886c62d1 | 13545 | [(return)] |
5f3d14e3 | 13546 | "ix86_can_use_return_insn_p ()" |
9a7372d6 RH |
13547 | { |
13548 | if (current_function_pops_args) | |
13549 | { | |
13550 | rtx popc = GEN_INT (current_function_pops_args); | |
13551 | emit_jump_insn (gen_return_pop_internal (popc)); | |
13552 | DONE; | |
13553 | } | |
0f40f9f7 | 13554 | }) |
5f3d14e3 SC |
13555 | |
13556 | (define_insn "return_internal" | |
13557 | [(return)] | |
13558 | "reload_completed" | |
90aec2cf | 13559 | "ret" |
6ef67412 JH |
13560 | [(set_attr "length" "1") |
13561 | (set_attr "length_immediate" "0") | |
13562 | (set_attr "modrm" "0")]) | |
5f3d14e3 | 13563 | |
6cd96118 SC |
13564 | (define_insn "return_pop_internal" |
13565 | [(return) | |
13566 | (use (match_operand:SI 0 "const_int_operand" ""))] | |
13567 | "reload_completed" | |
0f40f9f7 | 13568 | "ret\t%0" |
6ef67412 JH |
13569 | [(set_attr "length" "3") |
13570 | (set_attr "length_immediate" "2") | |
13571 | (set_attr "modrm" "0")]) | |
6cd96118 | 13572 | |
11837777 RH |
13573 | (define_insn "return_indirect_internal" |
13574 | [(return) | |
13575 | (use (match_operand:SI 0 "register_operand" "r"))] | |
13576 | "reload_completed" | |
0f40f9f7 | 13577 | "jmp\t%A0" |
11837777 RH |
13578 | [(set_attr "type" "ibr") |
13579 | (set_attr "length_immediate" "0")]) | |
13580 | ||
5f3d14e3 SC |
13581 | (define_insn "nop" |
13582 | [(const_int 0)] | |
13583 | "" | |
90aec2cf | 13584 | "nop" |
e075ae69 | 13585 | [(set_attr "length" "1") |
6ef67412 JH |
13586 | (set_attr "length_immediate" "0") |
13587 | (set_attr "modrm" "0") | |
e075ae69 | 13588 | (set_attr "ppro_uops" "one")]) |
5f3d14e3 SC |
13589 | |
13590 | (define_expand "prologue" | |
13591 | [(const_int 1)] | |
13592 | "" | |
e075ae69 | 13593 | "ix86_expand_prologue (); DONE;") |
5f3d14e3 | 13594 | |
bd09bdeb | 13595 | (define_insn "set_got" |
69404d6f | 13596 | [(set (match_operand:SI 0 "register_operand" "=r") |
c8c03509 RH |
13597 | (unspec:SI [(const_int 0)] UNSPEC_SET_GOT)) |
13598 | (clobber (reg:CC 17))] | |
1e07edd3 | 13599 | "!TARGET_64BIT" |
c8c03509 RH |
13600 | { return output_set_got (operands[0]); } |
13601 | [(set_attr "type" "multi") | |
13602 | (set_attr "length" "12")]) | |
5f3d14e3 | 13603 | |
e075ae69 RH |
13604 | (define_expand "epilogue" |
13605 | [(const_int 1)] | |
13606 | "" | |
cbbf65e0 RH |
13607 | "ix86_expand_epilogue (1); DONE;") |
13608 | ||
13609 | (define_expand "sibcall_epilogue" | |
13610 | [(const_int 1)] | |
13611 | "" | |
13612 | "ix86_expand_epilogue (0); DONE;") | |
e075ae69 | 13613 | |
1020a5ab RH |
13614 | (define_expand "eh_return" |
13615 | [(use (match_operand 0 "register_operand" "")) | |
13616 | (use (match_operand 1 "register_operand" ""))] | |
13617 | "" | |
1020a5ab RH |
13618 | { |
13619 | rtx tmp, sa = operands[0], ra = operands[1]; | |
13620 | ||
13621 | /* Tricky bit: we write the address of the handler to which we will | |
13622 | be returning into someone else's stack frame, one word below the | |
13623 | stack address we wish to restore. */ | |
13624 | tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa); | |
13625 | tmp = plus_constant (tmp, -UNITS_PER_WORD); | |
13626 | tmp = gen_rtx_MEM (Pmode, tmp); | |
13627 | emit_move_insn (tmp, ra); | |
13628 | ||
d5d6a58b RH |
13629 | if (Pmode == SImode) |
13630 | emit_insn (gen_eh_return_si (sa)); | |
13631 | else | |
13632 | emit_insn (gen_eh_return_di (sa)); | |
1020a5ab RH |
13633 | emit_barrier (); |
13634 | DONE; | |
0f40f9f7 | 13635 | }) |
1020a5ab | 13636 | |
d5d6a58b | 13637 | (define_insn_and_split "eh_return_si" |
8ee41eaf RH |
13638 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")] |
13639 | UNSPECV_EH_RETURN)] | |
1b0c37d7 | 13640 | "!TARGET_64BIT" |
d5d6a58b RH |
13641 | "#" |
13642 | "reload_completed" | |
13643 | [(const_int 1)] | |
13644 | "ix86_expand_epilogue (2); DONE;") | |
13645 | ||
13646 | (define_insn_and_split "eh_return_di" | |
8ee41eaf RH |
13647 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")] |
13648 | UNSPECV_EH_RETURN)] | |
1b0c37d7 | 13649 | "TARGET_64BIT" |
1020a5ab RH |
13650 | "#" |
13651 | "reload_completed" | |
13652 | [(const_int 1)] | |
13653 | "ix86_expand_epilogue (2); DONE;") | |
13654 | ||
e075ae69 | 13655 | (define_insn "leave" |
669fe758 | 13656 | [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4))) |
6fc5dc67 | 13657 | (set (reg:SI 6) (mem:SI (reg:SI 6))) |
f2042df3 | 13658 | (clobber (mem:BLK (scratch)))] |
1e07edd3 | 13659 | "!TARGET_64BIT" |
e075ae69 | 13660 | "leave" |
6ef67412 JH |
13661 | [(set_attr "length_immediate" "0") |
13662 | (set_attr "length" "1") | |
13663 | (set_attr "modrm" "0") | |
0b5107cf | 13664 | (set_attr "athlon_decode" "vector") |
e075ae69 | 13665 | (set_attr "ppro_uops" "few")]) |
8362f420 JH |
13666 | |
13667 | (define_insn "leave_rex64" | |
f283104b | 13668 | [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8))) |
6fc5dc67 | 13669 | (set (reg:DI 6) (mem:DI (reg:DI 6))) |
f2042df3 | 13670 | (clobber (mem:BLK (scratch)))] |
8362f420 JH |
13671 | "TARGET_64BIT" |
13672 | "leave" | |
13673 | [(set_attr "length_immediate" "0") | |
13674 | (set_attr "length" "1") | |
13675 | (set_attr "modrm" "0") | |
8362f420 JH |
13676 | (set_attr "athlon_decode" "vector") |
13677 | (set_attr "ppro_uops" "few")]) | |
e075ae69 RH |
13678 | \f |
13679 | (define_expand "ffssi2" | |
4cbfbb1b | 13680 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
e075ae69 RH |
13681 | (ffs:SI (match_operand:SI 1 "general_operand" "")))] |
13682 | "" | |
e075ae69 RH |
13683 | { |
13684 | rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode); | |
13685 | rtx in = operands[1]; | |
13686 | ||
13687 | if (TARGET_CMOVE) | |
5f3d14e3 | 13688 | { |
e075ae69 RH |
13689 | emit_move_insn (tmp, constm1_rtx); |
13690 | emit_insn (gen_ffssi_1 (out, in)); | |
13691 | emit_insn (gen_rtx_SET (VOIDmode, out, | |
13692 | gen_rtx_IF_THEN_ELSE (SImode, | |
16189740 | 13693 | gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG), |
e075ae69 RH |
13694 | const0_rtx), |
13695 | tmp, | |
13696 | out))); | |
e0dc26ff JH |
13697 | emit_insn (gen_addsi3 (out, out, const1_rtx)); |
13698 | emit_move_insn (operands[0], out); | |
13699 | } | |
13700 | ||
16189740 RH |
13701 | /* Pentium bsf instruction is extremly slow. The following code is |
13702 | recommended by the Intel Optimizing Manual as a reasonable replacement: | |
e0dc26ff JH |
13703 | TEST EAX,EAX |
13704 | JZ SHORT BS2 | |
13705 | XOR ECX,ECX | |
13706 | MOV DWORD PTR [TEMP+4],ECX | |
13707 | SUB ECX,EAX | |
13708 | AND EAX,ECX | |
13709 | MOV DWORD PTR [TEMP],EAX | |
13710 | FILD QWORD PTR [TEMP] | |
13711 | FSTP QWORD PTR [TEMP] | |
13712 | WAIT ; WAIT only needed for compatibility with | |
13713 | ; earlier processors | |
13714 | MOV ECX, DWORD PTR [TEMP+4] | |
13715 | SHR ECX,20 | |
13716 | SUB ECX,3FFH | |
13717 | TEST EAX,EAX ; clear zero flag | |
13718 | BS2: | |
13719 | Following piece of code expand ffs to similar beast. | |
13720 | */ | |
13721 | ||
13722 | else if (TARGET_PENTIUM && !optimize_size && TARGET_80387) | |
13723 | { | |
13724 | rtx label = gen_label_rtx (); | |
13725 | rtx lo, hi; | |
13726 | rtx mem = assign_386_stack_local (DImode, 0); | |
13727 | rtx fptmp = gen_reg_rtx (DFmode); | |
13728 | split_di (&mem, 1, &lo, &hi); | |
13729 | ||
13730 | emit_move_insn (out, const0_rtx); | |
13731 | ||
e790b36a | 13732 | emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, label); |
e0dc26ff JH |
13733 | |
13734 | emit_move_insn (hi, out); | |
13735 | emit_insn (gen_subsi3 (out, out, in)); | |
13736 | emit_insn (gen_andsi3 (out, out, in)); | |
13737 | emit_move_insn (lo, out); | |
13738 | emit_insn (gen_floatdidf2 (fptmp,mem)); | |
13739 | emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp); | |
13740 | emit_move_insn (out, hi); | |
13741 | emit_insn (gen_lshrsi3 (out, out, GEN_INT (20))); | |
16189740 | 13742 | emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1))); |
e0dc26ff JH |
13743 | |
13744 | emit_label (label); | |
13745 | LABEL_NUSES (label) = 1; | |
13746 | ||
13747 | emit_move_insn (operands[0], out); | |
5f3d14e3 | 13748 | } |
e075ae69 | 13749 | else |
5f3d14e3 | 13750 | { |
e075ae69 RH |
13751 | emit_move_insn (tmp, const0_rtx); |
13752 | emit_insn (gen_ffssi_1 (out, in)); | |
13753 | emit_insn (gen_rtx_SET (VOIDmode, | |
13754 | gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)), | |
16189740 | 13755 | gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG), |
e075ae69 RH |
13756 | const0_rtx))); |
13757 | emit_insn (gen_negsi2 (tmp, tmp)); | |
13758 | emit_insn (gen_iorsi3 (out, out, tmp)); | |
e0dc26ff JH |
13759 | emit_insn (gen_addsi3 (out, out, const1_rtx)); |
13760 | emit_move_insn (operands[0], out); | |
e075ae69 | 13761 | } |
e075ae69 | 13762 | DONE; |
0f40f9f7 | 13763 | }) |
886c62d1 | 13764 | |
e075ae69 | 13765 | (define_insn "ffssi_1" |
16189740 RH |
13766 | [(set (reg:CCZ 17) |
13767 | (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm") | |
13768 | (const_int 0))) | |
e075ae69 | 13769 | (set (match_operand:SI 0 "register_operand" "=r") |
8ee41eaf | 13770 | (unspec:SI [(match_dup 1)] UNSPEC_BSF))] |
e075ae69 | 13771 | "" |
0f40f9f7 | 13772 | "bsf{l}\t{%1, %0|%0, %1}" |
6ef67412 | 13773 | [(set_attr "prefix_0f" "1") |
e075ae69 RH |
13774 | (set_attr "ppro_uops" "few")]) |
13775 | ||
13776 | ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger | |
13777 | ;; and slower than the two-byte movzx insn needed to do the work in SImode. | |
13778 | \f | |
f996902d RH |
13779 | ;; Thread-local storage patterns for ELF. |
13780 | ;; | |
13781 | ;; Note that these code sequences must appear exactly as shown | |
13782 | ;; in order to allow linker relaxation. | |
13783 | ||
13784 | (define_insn "*tls_global_dynamic_gnu" | |
13785 | [(set (match_operand:SI 0 "register_operand" "=a") | |
13786 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
13787 | (match_operand:SI 2 "tls_symbolic_operand" "") | |
13788 | (match_operand:SI 3 "call_insn_operand" "")] | |
13789 | UNSPEC_TLS_GD)) | |
13790 | (clobber (match_scratch:SI 4 "=d")) | |
13791 | (clobber (match_scratch:SI 5 "=c")) | |
13792 | (clobber (reg:CC 17))] | |
13793 | "TARGET_GNU_TLS" | |
13794 | "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3" | |
13795 | [(set_attr "type" "multi") | |
13796 | (set_attr "length" "12")]) | |
13797 | ||
13798 | (define_insn "*tls_global_dynamic_sun" | |
13799 | [(set (match_operand:SI 0 "register_operand" "=a") | |
13800 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
13801 | (match_operand:SI 2 "tls_symbolic_operand" "") | |
13802 | (match_operand:SI 3 "call_insn_operand" "")] | |
13803 | UNSPEC_TLS_GD)) | |
13804 | (clobber (match_scratch:SI 4 "=d")) | |
13805 | (clobber (match_scratch:SI 5 "=c")) | |
13806 | (clobber (reg:CC 17))] | |
13807 | "TARGET_SUN_TLS" | |
13808 | "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]} | |
13809 | push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop" | |
13810 | [(set_attr "type" "multi") | |
13811 | (set_attr "length" "14")]) | |
13812 | ||
13813 | (define_expand "tls_global_dynamic" | |
13814 | [(parallel [(set (match_operand:SI 0 "register_operand" "") | |
13815 | (unspec:SI | |
13816 | [(match_dup 2) | |
13817 | (match_operand:SI 1 "tls_symbolic_operand" "") | |
13818 | (match_dup 3)] | |
13819 | UNSPEC_TLS_GD)) | |
13820 | (clobber (match_scratch:SI 4 "")) | |
13821 | (clobber (match_scratch:SI 5 "")) | |
13822 | (clobber (reg:CC 17))])] | |
13823 | "" | |
13824 | { | |
dce81a1a JJ |
13825 | if (flag_pic) |
13826 | operands[2] = pic_offset_table_rtx; | |
13827 | else | |
13828 | { | |
13829 | operands[2] = gen_reg_rtx (Pmode); | |
13830 | emit_insn (gen_set_got (operands[2])); | |
13831 | } | |
f996902d RH |
13832 | operands[3] = ix86_tls_get_addr (); |
13833 | }) | |
13834 | ||
13835 | (define_insn "*tls_local_dynamic_base_gnu" | |
13836 | [(set (match_operand:SI 0 "register_operand" "=a") | |
13837 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
13838 | (match_operand:SI 2 "call_insn_operand" "")] | |
13839 | UNSPEC_TLS_LD_BASE)) | |
13840 | (clobber (match_scratch:SI 3 "=d")) | |
13841 | (clobber (match_scratch:SI 4 "=c")) | |
13842 | (clobber (reg:CC 17))] | |
13843 | "TARGET_GNU_TLS" | |
13844 | "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2" | |
13845 | [(set_attr "type" "multi") | |
13846 | (set_attr "length" "11")]) | |
13847 | ||
13848 | (define_insn "*tls_local_dynamic_base_sun" | |
13849 | [(set (match_operand:SI 0 "register_operand" "=a") | |
13850 | (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
13851 | (match_operand:SI 2 "call_insn_operand" "")] | |
13852 | UNSPEC_TLS_LD_BASE)) | |
13853 | (clobber (match_scratch:SI 3 "=d")) | |
13854 | (clobber (match_scratch:SI 4 "=c")) | |
13855 | (clobber (reg:CC 17))] | |
13856 | "TARGET_SUN_TLS" | |
13857 | "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]} | |
13858 | push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3" | |
13859 | [(set_attr "type" "multi") | |
13860 | (set_attr "length" "13")]) | |
13861 | ||
13862 | (define_expand "tls_local_dynamic_base" | |
13863 | [(parallel [(set (match_operand:SI 0 "register_operand" "") | |
13864 | (unspec:SI [(match_dup 1) (match_dup 2)] | |
13865 | UNSPEC_TLS_LD_BASE)) | |
13866 | (clobber (match_scratch:SI 3 "")) | |
13867 | (clobber (match_scratch:SI 4 "")) | |
13868 | (clobber (reg:CC 17))])] | |
13869 | "" | |
13870 | { | |
dce81a1a JJ |
13871 | if (flag_pic) |
13872 | operands[2] = pic_offset_table_rtx; | |
13873 | else | |
13874 | { | |
13875 | operands[2] = gen_reg_rtx (Pmode); | |
13876 | emit_insn (gen_set_got (operands[2])); | |
13877 | } | |
f996902d RH |
13878 | operands[1] = pic_offset_table_rtx; |
13879 | operands[2] = ix86_tls_get_addr (); | |
13880 | }) | |
13881 | ||
13882 | ;; Local dynamic of a single variable is a lose. Show combine how | |
13883 | ;; to convert that back to global dynamic. | |
13884 | ||
13885 | (define_insn_and_split "*tls_local_dynamic_once" | |
13886 | [(set (match_operand:SI 0 "register_operand" "=a") | |
13887 | (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b") | |
13888 | (match_operand:SI 2 "call_insn_operand" "")] | |
13889 | UNSPEC_TLS_LD_BASE) | |
13890 | (const:SI (unspec:SI | |
13891 | [(match_operand:SI 3 "tls_symbolic_operand" "")] | |
13892 | UNSPEC_DTPOFF)))) | |
13893 | (clobber (match_scratch:SI 4 "=d")) | |
13894 | (clobber (match_scratch:SI 5 "=c")) | |
13895 | (clobber (reg:CC 17))] | |
13896 | "" | |
13897 | "#" | |
13898 | "" | |
13899 | [(parallel [(set (match_dup 0) | |
13900 | (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)] | |
13901 | UNSPEC_TLS_GD)) | |
13902 | (clobber (match_dup 4)) | |
13903 | (clobber (match_dup 5)) | |
13904 | (clobber (reg:CC 17))])] | |
13905 | "") | |
13906 | \f | |
e075ae69 RH |
13907 | ;; These patterns match the binary 387 instructions for addM3, subM3, |
13908 | ;; mulM3 and divM3. There are three patterns for each of DFmode and | |
13909 | ;; SFmode. The first is the normal insn, the second the same insn but | |
13910 | ;; with one operand a conversion, and the third the same insn but with | |
13911 | ;; the other operand a conversion. The conversion may be SFmode or | |
13912 | ;; SImode if the target mode DFmode, but only SImode if the target mode | |
13913 | ;; is SFmode. | |
13914 | ||
caa6ec8d JH |
13915 | ;; Gcc is slightly more smart about handling normal two address instructions |
13916 | ;; so use special patterns for add and mull. | |
965f5423 JH |
13917 | (define_insn "*fop_sf_comm_nosse" |
13918 | [(set (match_operand:SF 0 "register_operand" "=f") | |
13919 | (match_operator:SF 3 "binary_fp_operator" | |
aebfea10 | 13920 | [(match_operand:SF 1 "nonimmediate_operand" "%0") |
965f5423 JH |
13921 | (match_operand:SF 2 "nonimmediate_operand" "fm")]))] |
13922 | "TARGET_80387 && !TARGET_SSE_MATH | |
aebfea10 JH |
13923 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' |
13924 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
965f5423 JH |
13925 | "* return output_387_binary_op (insn, operands);" |
13926 | [(set (attr "type") | |
13927 | (if_then_else (match_operand:SF 3 "mult_operator" "") | |
13928 | (const_string "fmul") | |
13929 | (const_string "fop"))) | |
13930 | (set_attr "mode" "SF")]) | |
13931 | ||
caa6ec8d | 13932 | (define_insn "*fop_sf_comm" |
1deaa899 | 13933 | [(set (match_operand:SF 0 "register_operand" "=f#x,x#f") |
caa6ec8d | 13934 | (match_operator:SF 3 "binary_fp_operator" |
aebfea10 | 13935 | [(match_operand:SF 1 "nonimmediate_operand" "%0,0") |
1deaa899 | 13936 | (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))] |
965f5423 | 13937 | "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 |
aebfea10 JH |
13938 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' |
13939 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
caa6ec8d JH |
13940 | "* return output_387_binary_op (insn, operands);" |
13941 | [(set (attr "type") | |
1deaa899 | 13942 | (if_then_else (eq_attr "alternative" "1") |
3d34cd91 JH |
13943 | (if_then_else (match_operand:SF 3 "mult_operator" "") |
13944 | (const_string "ssemul") | |
13945 | (const_string "sseadd")) | |
1deaa899 JH |
13946 | (if_then_else (match_operand:SF 3 "mult_operator" "") |
13947 | (const_string "fmul") | |
13948 | (const_string "fop")))) | |
13949 | (set_attr "mode" "SF")]) | |
13950 | ||
13951 | (define_insn "*fop_sf_comm_sse" | |
13952 | [(set (match_operand:SF 0 "register_operand" "=x") | |
13953 | (match_operator:SF 3 "binary_fp_operator" | |
aebfea10 | 13954 | [(match_operand:SF 1 "nonimmediate_operand" "%0") |
1deaa899 | 13955 | (match_operand:SF 2 "nonimmediate_operand" "xm")]))] |
aebfea10 JH |
13956 | "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' |
13957 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
1deaa899 | 13958 | "* return output_387_binary_op (insn, operands);" |
3d34cd91 JH |
13959 | [(set (attr "type") |
13960 | (if_then_else (match_operand:SF 3 "mult_operator" "") | |
13961 | (const_string "ssemul") | |
13962 | (const_string "sseadd"))) | |
6ef67412 | 13963 | (set_attr "mode" "SF")]) |
caa6ec8d | 13964 | |
965f5423 JH |
13965 | (define_insn "*fop_df_comm_nosse" |
13966 | [(set (match_operand:DF 0 "register_operand" "=f") | |
13967 | (match_operator:DF 3 "binary_fp_operator" | |
aebfea10 | 13968 | [(match_operand:DF 1 "nonimmediate_operand" "%0") |
965f5423 JH |
13969 | (match_operand:DF 2 "nonimmediate_operand" "fm")]))] |
13970 | "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) | |
aebfea10 JH |
13971 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' |
13972 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
965f5423 JH |
13973 | "* return output_387_binary_op (insn, operands);" |
13974 | [(set (attr "type") | |
13975 | (if_then_else (match_operand:SF 3 "mult_operator" "") | |
13976 | (const_string "fmul") | |
13977 | (const_string "fop"))) | |
13978 | (set_attr "mode" "DF")]) | |
13979 | ||
caa6ec8d | 13980 | (define_insn "*fop_df_comm" |
1deaa899 | 13981 | [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") |
caa6ec8d | 13982 | (match_operator:DF 3 "binary_fp_operator" |
aebfea10 | 13983 | [(match_operand:DF 1 "nonimmediate_operand" "%0,0") |
1deaa899 | 13984 | (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))] |
965f5423 | 13985 | "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387 |
aebfea10 JH |
13986 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' |
13987 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
caa6ec8d JH |
13988 | "* return output_387_binary_op (insn, operands);" |
13989 | [(set (attr "type") | |
1deaa899 | 13990 | (if_then_else (eq_attr "alternative" "1") |
3d34cd91 JH |
13991 | (if_then_else (match_operand:SF 3 "mult_operator" "") |
13992 | (const_string "ssemul") | |
13993 | (const_string "sseadd")) | |
1deaa899 JH |
13994 | (if_then_else (match_operand:SF 3 "mult_operator" "") |
13995 | (const_string "fmul") | |
13996 | (const_string "fop")))) | |
13997 | (set_attr "mode" "DF")]) | |
13998 | ||
13999 | (define_insn "*fop_df_comm_sse" | |
14000 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
14001 | (match_operator:DF 3 "binary_fp_operator" | |
aebfea10 | 14002 | [(match_operand:DF 1 "nonimmediate_operand" "%0") |
1deaa899 | 14003 | (match_operand:DF 2 "nonimmediate_operand" "Ym")]))] |
965f5423 | 14004 | "TARGET_SSE2 && TARGET_SSE_MATH |
aebfea10 JH |
14005 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' |
14006 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
1deaa899 | 14007 | "* return output_387_binary_op (insn, operands);" |
3d34cd91 JH |
14008 | [(set (attr "type") |
14009 | (if_then_else (match_operand:SF 3 "mult_operator" "") | |
14010 | (const_string "ssemul") | |
14011 | (const_string "sseadd"))) | |
6ef67412 | 14012 | (set_attr "mode" "DF")]) |
caa6ec8d JH |
14013 | |
14014 | (define_insn "*fop_xf_comm" | |
14015 | [(set (match_operand:XF 0 "register_operand" "=f") | |
14016 | (match_operator:XF 3 "binary_fp_operator" | |
14017 | [(match_operand:XF 1 "register_operand" "%0") | |
14018 | (match_operand:XF 2 "register_operand" "f")]))] | |
1b0c37d7 | 14019 | "!TARGET_64BIT && TARGET_80387 |
1e07edd3 | 14020 | && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" |
caa6ec8d JH |
14021 | "* return output_387_binary_op (insn, operands);" |
14022 | [(set (attr "type") | |
14023 | (if_then_else (match_operand:XF 3 "mult_operator" "") | |
14024 | (const_string "fmul") | |
6ef67412 JH |
14025 | (const_string "fop"))) |
14026 | (set_attr "mode" "XF")]) | |
caa6ec8d | 14027 | |
2b589241 JH |
14028 | (define_insn "*fop_tf_comm" |
14029 | [(set (match_operand:TF 0 "register_operand" "=f") | |
14030 | (match_operator:TF 3 "binary_fp_operator" | |
14031 | [(match_operand:TF 1 "register_operand" "%0") | |
14032 | (match_operand:TF 2 "register_operand" "f")]))] | |
14033 | "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" | |
14034 | "* return output_387_binary_op (insn, operands);" | |
14035 | [(set (attr "type") | |
14036 | (if_then_else (match_operand:TF 3 "mult_operator" "") | |
14037 | (const_string "fmul") | |
14038 | (const_string "fop"))) | |
14039 | (set_attr "mode" "XF")]) | |
14040 | ||
965f5423 JH |
14041 | (define_insn "*fop_sf_1_nosse" |
14042 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
14043 | (match_operator:SF 3 "binary_fp_operator" | |
14044 | [(match_operand:SF 1 "nonimmediate_operand" "0,fm") | |
14045 | (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))] | |
14046 | "TARGET_80387 && !TARGET_SSE_MATH | |
14047 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' | |
14048 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
14049 | "* return output_387_binary_op (insn, operands);" | |
14050 | [(set (attr "type") | |
14051 | (cond [(match_operand:SF 3 "mult_operator" "") | |
14052 | (const_string "fmul") | |
14053 | (match_operand:SF 3 "div_operator" "") | |
14054 | (const_string "fdiv") | |
14055 | ] | |
14056 | (const_string "fop"))) | |
14057 | (set_attr "mode" "SF")]) | |
14058 | ||
e075ae69 | 14059 | (define_insn "*fop_sf_1" |
1deaa899 | 14060 | [(set (match_operand:SF 0 "register_operand" "=f,f,x") |
e075ae69 | 14061 | (match_operator:SF 3 "binary_fp_operator" |
1deaa899 JH |
14062 | [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0") |
14063 | (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))] | |
965f5423 | 14064 | "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 |
caa6ec8d | 14065 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' |
f97d9ec3 | 14066 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
e075ae69 RH |
14067 | "* return output_387_binary_op (insn, operands);" |
14068 | [(set (attr "type") | |
3d34cd91 JH |
14069 | (cond [(and (eq_attr "alternative" "2") |
14070 | (match_operand:SF 3 "mult_operator" "")) | |
14071 | (const_string "ssemul") | |
14072 | (and (eq_attr "alternative" "2") | |
14073 | (match_operand:SF 3 "div_operator" "")) | |
14074 | (const_string "ssediv") | |
14075 | (eq_attr "alternative" "2") | |
14076 | (const_string "sseadd") | |
1deaa899 | 14077 | (match_operand:SF 3 "mult_operator" "") |
e075ae69 RH |
14078 | (const_string "fmul") |
14079 | (match_operand:SF 3 "div_operator" "") | |
14080 | (const_string "fdiv") | |
14081 | ] | |
6ef67412 JH |
14082 | (const_string "fop"))) |
14083 | (set_attr "mode" "SF")]) | |
e075ae69 | 14084 | |
1deaa899 JH |
14085 | (define_insn "*fop_sf_1_sse" |
14086 | [(set (match_operand:SF 0 "register_operand" "=x") | |
14087 | (match_operator:SF 3 "binary_fp_operator" | |
14088 | [(match_operand:SF 1 "register_operand" "0") | |
14089 | (match_operand:SF 2 "nonimmediate_operand" "xm")]))] | |
965f5423 | 14090 | "TARGET_SSE_MATH |
1deaa899 JH |
14091 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" |
14092 | "* return output_387_binary_op (insn, operands);" | |
3d34cd91 JH |
14093 | [(set (attr "type") |
14094 | (cond [(match_operand:SF 3 "mult_operator" "") | |
14095 | (const_string "ssemul") | |
14096 | (match_operand:SF 3 "div_operator" "") | |
14097 | (const_string "ssediv") | |
14098 | ] | |
14099 | (const_string "sseadd"))) | |
1deaa899 JH |
14100 | (set_attr "mode" "SF")]) |
14101 | ||
14102 | ;; ??? Add SSE splitters for these! | |
e075ae69 RH |
14103 | (define_insn "*fop_sf_2" |
14104 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
14105 | (match_operator:SF 3 "binary_fp_operator" | |
14106 | [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) | |
14107 | (match_operand:SF 2 "register_operand" "0,0")]))] | |
965f5423 | 14108 | "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH" |
e075ae69 RH |
14109 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14110 | [(set (attr "type") | |
14111 | (cond [(match_operand:SF 3 "mult_operator" "") | |
14112 | (const_string "fmul") | |
14113 | (match_operand:SF 3 "div_operator" "") | |
14114 | (const_string "fdiv") | |
14115 | ] | |
14116 | (const_string "fop"))) | |
14117 | (set_attr "fp_int_src" "true") | |
6ef67412 JH |
14118 | (set_attr "ppro_uops" "many") |
14119 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
14120 | |
14121 | (define_insn "*fop_sf_3" | |
14122 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
14123 | (match_operator:SF 3 "binary_fp_operator" | |
14124 | [(match_operand:SF 1 "register_operand" "0,0") | |
14125 | (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] | |
965f5423 | 14126 | "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH" |
e075ae69 RH |
14127 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14128 | [(set (attr "type") | |
14129 | (cond [(match_operand:SF 3 "mult_operator" "") | |
14130 | (const_string "fmul") | |
14131 | (match_operand:SF 3 "div_operator" "") | |
14132 | (const_string "fdiv") | |
14133 | ] | |
14134 | (const_string "fop"))) | |
14135 | (set_attr "fp_int_src" "true") | |
6ef67412 JH |
14136 | (set_attr "ppro_uops" "many") |
14137 | (set_attr "mode" "SI")]) | |
e075ae69 | 14138 | |
965f5423 JH |
14139 | (define_insn "*fop_df_1_nosse" |
14140 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14141 | (match_operator:DF 3 "binary_fp_operator" | |
14142 | [(match_operand:DF 1 "nonimmediate_operand" "0,fm") | |
14143 | (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))] | |
14144 | "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) | |
14145 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' | |
14146 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
14147 | "* return output_387_binary_op (insn, operands);" | |
14148 | [(set (attr "type") | |
14149 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14150 | (const_string "fmul") | |
3d34cd91 | 14151 | (match_operand:DF 3 "div_operator" "") |
965f5423 JH |
14152 | (const_string "fdiv") |
14153 | ] | |
14154 | (const_string "fop"))) | |
14155 | (set_attr "mode" "DF")]) | |
14156 | ||
14157 | ||
e075ae69 | 14158 | (define_insn "*fop_df_1" |
1deaa899 | 14159 | [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f") |
e075ae69 | 14160 | (match_operator:DF 3 "binary_fp_operator" |
1deaa899 JH |
14161 | [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0") |
14162 | (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))] | |
965f5423 | 14163 | "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 |
caa6ec8d | 14164 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c' |
f97d9ec3 | 14165 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
e075ae69 RH |
14166 | "* return output_387_binary_op (insn, operands);" |
14167 | [(set (attr "type") | |
3d34cd91 JH |
14168 | (cond [(and (eq_attr "alternative" "2") |
14169 | (match_operand:SF 3 "mult_operator" "")) | |
14170 | (const_string "ssemul") | |
14171 | (and (eq_attr "alternative" "2") | |
14172 | (match_operand:SF 3 "div_operator" "")) | |
14173 | (const_string "ssediv") | |
14174 | (eq_attr "alternative" "2") | |
14175 | (const_string "sseadd") | |
1deaa899 | 14176 | (match_operand:DF 3 "mult_operator" "") |
e075ae69 RH |
14177 | (const_string "fmul") |
14178 | (match_operand:DF 3 "div_operator" "") | |
14179 | (const_string "fdiv") | |
14180 | ] | |
6ef67412 JH |
14181 | (const_string "fop"))) |
14182 | (set_attr "mode" "DF")]) | |
e075ae69 | 14183 | |
1deaa899 JH |
14184 | (define_insn "*fop_df_1_sse" |
14185 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
14186 | (match_operator:DF 3 "binary_fp_operator" | |
14187 | [(match_operand:DF 1 "register_operand" "0") | |
14188 | (match_operand:DF 2 "nonimmediate_operand" "Ym")]))] | |
965f5423 | 14189 | "TARGET_SSE2 && TARGET_SSE_MATH |
1deaa899 JH |
14190 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" |
14191 | "* return output_387_binary_op (insn, operands);" | |
3d34cd91 JH |
14192 | [(set_attr "mode" "DF") |
14193 | (set (attr "type") | |
14194 | (cond [(match_operand:SF 3 "mult_operator" "") | |
14195 | (const_string "ssemul") | |
14196 | (match_operand:SF 3 "div_operator" "") | |
14197 | (const_string "ssediv") | |
14198 | ] | |
14199 | (const_string "sseadd")))]) | |
1deaa899 JH |
14200 | |
14201 | ;; ??? Add SSE splitters for these! | |
e075ae69 RH |
14202 | (define_insn "*fop_df_2" |
14203 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14204 | (match_operator:DF 3 "binary_fp_operator" | |
14205 | [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) | |
14206 | (match_operand:DF 2 "register_operand" "0,0")]))] | |
965f5423 | 14207 | "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)" |
e075ae69 RH |
14208 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14209 | [(set (attr "type") | |
14210 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14211 | (const_string "fmul") | |
14212 | (match_operand:DF 3 "div_operator" "") | |
14213 | (const_string "fdiv") | |
14214 | ] | |
14215 | (const_string "fop"))) | |
14216 | (set_attr "fp_int_src" "true") | |
6ef67412 JH |
14217 | (set_attr "ppro_uops" "many") |
14218 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
14219 | |
14220 | (define_insn "*fop_df_3" | |
14221 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14222 | (match_operator:DF 3 "binary_fp_operator" | |
14223 | [(match_operand:DF 1 "register_operand" "0,0") | |
14224 | (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] | |
965f5423 | 14225 | "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)" |
e075ae69 RH |
14226 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14227 | [(set (attr "type") | |
14228 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14229 | (const_string "fmul") | |
14230 | (match_operand:DF 3 "div_operator" "") | |
14231 | (const_string "fdiv") | |
14232 | ] | |
14233 | (const_string "fop"))) | |
14234 | (set_attr "fp_int_src" "true") | |
6ef67412 JH |
14235 | (set_attr "ppro_uops" "many") |
14236 | (set_attr "mode" "SI")]) | |
e075ae69 RH |
14237 | |
14238 | (define_insn "*fop_df_4" | |
14239 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14240 | (match_operator:DF 3 "binary_fp_operator" | |
14241 | [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) | |
14242 | (match_operand:DF 2 "register_operand" "0,f")]))] | |
3987b9db | 14243 | "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) |
f97d9ec3 | 14244 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" |
e075ae69 RH |
14245 | "* return output_387_binary_op (insn, operands);" |
14246 | [(set (attr "type") | |
14247 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14248 | (const_string "fmul") | |
14249 | (match_operand:DF 3 "div_operator" "") | |
14250 | (const_string "fdiv") | |
14251 | ] | |
6ef67412 JH |
14252 | (const_string "fop"))) |
14253 | (set_attr "mode" "SF")]) | |
e075ae69 RH |
14254 | |
14255 | (define_insn "*fop_df_5" | |
14256 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
14257 | (match_operator:DF 3 "binary_fp_operator" | |
14258 | [(match_operand:DF 1 "register_operand" "0,f") | |
14259 | (float_extend:DF | |
14260 | (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] | |
965f5423 | 14261 | "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)" |
e075ae69 RH |
14262 | "* return output_387_binary_op (insn, operands);" |
14263 | [(set (attr "type") | |
14264 | (cond [(match_operand:DF 3 "mult_operator" "") | |
14265 | (const_string "fmul") | |
14266 | (match_operand:DF 3 "div_operator" "") | |
14267 | (const_string "fdiv") | |
14268 | ] | |
6ef67412 JH |
14269 | (const_string "fop"))) |
14270 | (set_attr "mode" "SF")]) | |
e075ae69 RH |
14271 | |
14272 | (define_insn "*fop_xf_1" | |
14273 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14274 | (match_operator:XF 3 "binary_fp_operator" | |
14275 | [(match_operand:XF 1 "register_operand" "0,f") | |
14276 | (match_operand:XF 2 "register_operand" "f,0")]))] | |
1b0c37d7 | 14277 | "!TARGET_64BIT && TARGET_80387 |
caa6ec8d | 14278 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" |
e075ae69 RH |
14279 | "* return output_387_binary_op (insn, operands);" |
14280 | [(set (attr "type") | |
ca285e07 | 14281 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14282 | (const_string "fmul") |
ca285e07 | 14283 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14284 | (const_string "fdiv") |
14285 | ] | |
6ef67412 JH |
14286 | (const_string "fop"))) |
14287 | (set_attr "mode" "XF")]) | |
e075ae69 | 14288 | |
2b589241 JH |
14289 | (define_insn "*fop_tf_1" |
14290 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14291 | (match_operator:TF 3 "binary_fp_operator" | |
14292 | [(match_operand:TF 1 "register_operand" "0,f") | |
14293 | (match_operand:TF 2 "register_operand" "f,0")]))] | |
14294 | "TARGET_80387 | |
14295 | && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" | |
14296 | "* return output_387_binary_op (insn, operands);" | |
14297 | [(set (attr "type") | |
14298 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14299 | (const_string "fmul") | |
14300 | (match_operand:TF 3 "div_operator" "") | |
14301 | (const_string "fdiv") | |
14302 | ] | |
14303 | (const_string "fop"))) | |
14304 | (set_attr "mode" "XF")]) | |
14305 | ||
e075ae69 RH |
14306 | (define_insn "*fop_xf_2" |
14307 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14308 | (match_operator:XF 3 "binary_fp_operator" | |
14309 | [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) | |
14310 | (match_operand:XF 2 "register_operand" "0,0")]))] | |
1b0c37d7 | 14311 | "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP" |
e075ae69 RH |
14312 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14313 | [(set (attr "type") | |
ca285e07 | 14314 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14315 | (const_string "fmul") |
ca285e07 | 14316 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14317 | (const_string "fdiv") |
14318 | ] | |
14319 | (const_string "fop"))) | |
14320 | (set_attr "fp_int_src" "true") | |
6ef67412 | 14321 | (set_attr "mode" "SI") |
e075ae69 RH |
14322 | (set_attr "ppro_uops" "many")]) |
14323 | ||
2b589241 JH |
14324 | (define_insn "*fop_tf_2" |
14325 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14326 | (match_operator:TF 3 "binary_fp_operator" | |
14327 | [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) | |
14328 | (match_operand:TF 2 "register_operand" "0,0")]))] | |
14329 | "TARGET_80387 && TARGET_USE_FIOP" | |
14330 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" | |
14331 | [(set (attr "type") | |
14332 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14333 | (const_string "fmul") | |
14334 | (match_operand:TF 3 "div_operator" "") | |
14335 | (const_string "fdiv") | |
14336 | ] | |
14337 | (const_string "fop"))) | |
14338 | (set_attr "fp_int_src" "true") | |
14339 | (set_attr "mode" "SI") | |
14340 | (set_attr "ppro_uops" "many")]) | |
14341 | ||
e075ae69 RH |
14342 | (define_insn "*fop_xf_3" |
14343 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14344 | (match_operator:XF 3 "binary_fp_operator" | |
14345 | [(match_operand:XF 1 "register_operand" "0,0") | |
14346 | (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] | |
1b0c37d7 | 14347 | "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP" |
e075ae69 RH |
14348 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" |
14349 | [(set (attr "type") | |
ca285e07 | 14350 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14351 | (const_string "fmul") |
ca285e07 | 14352 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14353 | (const_string "fdiv") |
14354 | ] | |
14355 | (const_string "fop"))) | |
14356 | (set_attr "fp_int_src" "true") | |
6ef67412 | 14357 | (set_attr "mode" "SI") |
e075ae69 RH |
14358 | (set_attr "ppro_uops" "many")]) |
14359 | ||
2b589241 JH |
14360 | (define_insn "*fop_tf_3" |
14361 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14362 | (match_operator:TF 3 "binary_fp_operator" | |
14363 | [(match_operand:TF 1 "register_operand" "0,0") | |
14364 | (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] | |
14365 | "TARGET_80387 && TARGET_USE_FIOP" | |
14366 | "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" | |
14367 | [(set (attr "type") | |
14368 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14369 | (const_string "fmul") | |
14370 | (match_operand:TF 3 "div_operator" "") | |
14371 | (const_string "fdiv") | |
14372 | ] | |
14373 | (const_string "fop"))) | |
14374 | (set_attr "fp_int_src" "true") | |
14375 | (set_attr "mode" "SI") | |
14376 | (set_attr "ppro_uops" "many")]) | |
14377 | ||
e075ae69 RH |
14378 | (define_insn "*fop_xf_4" |
14379 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14380 | (match_operator:XF 3 "binary_fp_operator" | |
14381 | [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) | |
14382 | (match_operand:XF 2 "register_operand" "0,f")]))] | |
1b0c37d7 | 14383 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
14384 | "* return output_387_binary_op (insn, operands);" |
14385 | [(set (attr "type") | |
ca285e07 | 14386 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14387 | (const_string "fmul") |
ca285e07 | 14388 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14389 | (const_string "fdiv") |
14390 | ] | |
6ef67412 JH |
14391 | (const_string "fop"))) |
14392 | (set_attr "mode" "SF")]) | |
e075ae69 | 14393 | |
2b589241 JH |
14394 | (define_insn "*fop_tf_4" |
14395 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14396 | (match_operator:TF 3 "binary_fp_operator" | |
14397 | [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0")) | |
14398 | (match_operand:TF 2 "register_operand" "0,f")]))] | |
14399 | "TARGET_80387" | |
14400 | "* return output_387_binary_op (insn, operands);" | |
14401 | [(set (attr "type") | |
14402 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14403 | (const_string "fmul") | |
14404 | (match_operand:TF 3 "div_operator" "") | |
14405 | (const_string "fdiv") | |
14406 | ] | |
14407 | (const_string "fop"))) | |
14408 | (set_attr "mode" "SF")]) | |
14409 | ||
e075ae69 RH |
14410 | (define_insn "*fop_xf_5" |
14411 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14412 | (match_operator:XF 3 "binary_fp_operator" | |
14413 | [(match_operand:XF 1 "register_operand" "0,f") | |
14414 | (float_extend:XF | |
14415 | (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] | |
1b0c37d7 | 14416 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
14417 | "* return output_387_binary_op (insn, operands);" |
14418 | [(set (attr "type") | |
ca285e07 | 14419 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14420 | (const_string "fmul") |
ca285e07 | 14421 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14422 | (const_string "fdiv") |
14423 | ] | |
6ef67412 JH |
14424 | (const_string "fop"))) |
14425 | (set_attr "mode" "SF")]) | |
e075ae69 | 14426 | |
2b589241 JH |
14427 | (define_insn "*fop_tf_5" |
14428 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14429 | (match_operator:TF 3 "binary_fp_operator" | |
14430 | [(match_operand:TF 1 "register_operand" "0,f") | |
14431 | (float_extend:TF | |
14432 | (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))] | |
14433 | "TARGET_80387" | |
14434 | "* return output_387_binary_op (insn, operands);" | |
14435 | [(set (attr "type") | |
14436 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14437 | (const_string "fmul") | |
14438 | (match_operand:TF 3 "div_operator" "") | |
14439 | (const_string "fdiv") | |
14440 | ] | |
14441 | (const_string "fop"))) | |
14442 | (set_attr "mode" "SF")]) | |
14443 | ||
e075ae69 RH |
14444 | (define_insn "*fop_xf_6" |
14445 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14446 | (match_operator:XF 3 "binary_fp_operator" | |
14447 | [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0")) | |
14448 | (match_operand:XF 2 "register_operand" "0,f")]))] | |
1b0c37d7 | 14449 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
14450 | "* return output_387_binary_op (insn, operands);" |
14451 | [(set (attr "type") | |
ca285e07 | 14452 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14453 | (const_string "fmul") |
ca285e07 | 14454 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14455 | (const_string "fdiv") |
14456 | ] | |
6ef67412 JH |
14457 | (const_string "fop"))) |
14458 | (set_attr "mode" "DF")]) | |
e075ae69 | 14459 | |
2b589241 JH |
14460 | (define_insn "*fop_tf_6" |
14461 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14462 | (match_operator:TF 3 "binary_fp_operator" | |
14463 | [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0")) | |
14464 | (match_operand:TF 2 "register_operand" "0,f")]))] | |
14465 | "TARGET_80387" | |
14466 | "* return output_387_binary_op (insn, operands);" | |
14467 | [(set (attr "type") | |
14468 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14469 | (const_string "fmul") | |
14470 | (match_operand:TF 3 "div_operator" "") | |
14471 | (const_string "fdiv") | |
14472 | ] | |
14473 | (const_string "fop"))) | |
14474 | (set_attr "mode" "DF")]) | |
14475 | ||
e075ae69 RH |
14476 | (define_insn "*fop_xf_7" |
14477 | [(set (match_operand:XF 0 "register_operand" "=f,f") | |
14478 | (match_operator:XF 3 "binary_fp_operator" | |
14479 | [(match_operand:XF 1 "register_operand" "0,f") | |
14480 | (float_extend:XF | |
14481 | (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))] | |
1b0c37d7 | 14482 | "!TARGET_64BIT && TARGET_80387" |
e075ae69 RH |
14483 | "* return output_387_binary_op (insn, operands);" |
14484 | [(set (attr "type") | |
ca285e07 | 14485 | (cond [(match_operand:XF 3 "mult_operator" "") |
e075ae69 | 14486 | (const_string "fmul") |
ca285e07 | 14487 | (match_operand:XF 3 "div_operator" "") |
e075ae69 RH |
14488 | (const_string "fdiv") |
14489 | ] | |
6ef67412 JH |
14490 | (const_string "fop"))) |
14491 | (set_attr "mode" "DF")]) | |
e075ae69 | 14492 | |
2b589241 JH |
14493 | (define_insn "*fop_tf_7" |
14494 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
14495 | (match_operator:TF 3 "binary_fp_operator" | |
14496 | [(match_operand:TF 1 "register_operand" "0,f") | |
14497 | (float_extend:TF | |
14498 | (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))] | |
14499 | "TARGET_80387" | |
14500 | "* return output_387_binary_op (insn, operands);" | |
14501 | [(set (attr "type") | |
14502 | (cond [(match_operand:TF 3 "mult_operator" "") | |
14503 | (const_string "fmul") | |
14504 | (match_operand:TF 3 "div_operator" "") | |
14505 | (const_string "fdiv") | |
14506 | ] | |
14507 | (const_string "fop"))) | |
14508 | (set_attr "mode" "DF")]) | |
14509 | ||
e075ae69 RH |
14510 | (define_split |
14511 | [(set (match_operand 0 "register_operand" "") | |
14512 | (match_operator 3 "binary_fp_operator" | |
14513 | [(float (match_operand:SI 1 "register_operand" "")) | |
14514 | (match_operand 2 "register_operand" "")]))] | |
14515 | "TARGET_80387 && reload_completed | |
14516 | && FLOAT_MODE_P (GET_MODE (operands[0]))" | |
4211a8fb | 14517 | [(const_int 0)] |
4211a8fb JH |
14518 | { |
14519 | operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]); | |
14520 | operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]); | |
14521 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
14522 | gen_rtx_fmt_ee (GET_CODE (operands[3]), | |
14523 | GET_MODE (operands[3]), | |
14524 | operands[4], | |
14525 | operands[2]))); | |
14526 | ix86_free_from_memory (GET_MODE (operands[1])); | |
14527 | DONE; | |
0f40f9f7 | 14528 | }) |
e075ae69 RH |
14529 | |
14530 | (define_split | |
14531 | [(set (match_operand 0 "register_operand" "") | |
14532 | (match_operator 3 "binary_fp_operator" | |
14533 | [(match_operand 1 "register_operand" "") | |
14534 | (float (match_operand:SI 2 "register_operand" ""))]))] | |
14535 | "TARGET_80387 && reload_completed | |
14536 | && FLOAT_MODE_P (GET_MODE (operands[0]))" | |
4211a8fb | 14537 | [(const_int 0)] |
4211a8fb JH |
14538 | { |
14539 | operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]); | |
14540 | operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]); | |
14541 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2b66da3c | 14542 | gen_rtx_fmt_ee (GET_CODE (operands[3]), |
4211a8fb JH |
14543 | GET_MODE (operands[3]), |
14544 | operands[1], | |
14545 | operands[4]))); | |
14546 | ix86_free_from_memory (GET_MODE (operands[2])); | |
14547 | DONE; | |
0f40f9f7 | 14548 | }) |
e075ae69 RH |
14549 | \f |
14550 | ;; FPU special functions. | |
14551 | ||
a8083431 JH |
14552 | (define_expand "sqrtsf2" |
14553 | [(set (match_operand:SF 0 "register_operand" "") | |
14554 | (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
abf80f8f | 14555 | "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH" |
a8083431 | 14556 | { |
abf80f8f | 14557 | if (!TARGET_SSE_MATH) |
a8083431 | 14558 | operands[1] = force_reg (SFmode, operands[1]); |
0f40f9f7 | 14559 | }) |
a8083431 JH |
14560 | |
14561 | (define_insn "sqrtsf2_1" | |
ca9a9b12 JH |
14562 | [(set (match_operand:SF 0 "register_operand" "=f#x,x#f") |
14563 | (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))] | |
a8083431 | 14564 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
abf80f8f | 14565 | && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" |
a8083431 JH |
14566 | "@ |
14567 | fsqrt | |
0f40f9f7 | 14568 | sqrtss\t{%1, %0|%0, %1}" |
a8083431 JH |
14569 | [(set_attr "type" "fpspc,sse") |
14570 | (set_attr "mode" "SF,SF") | |
14571 | (set_attr "athlon_decode" "direct,*")]) | |
14572 | ||
14573 | (define_insn "sqrtsf2_1_sse_only" | |
ca9a9b12 JH |
14574 | [(set (match_operand:SF 0 "register_operand" "=x") |
14575 | (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))] | |
abf80f8f | 14576 | "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)" |
0f40f9f7 | 14577 | "sqrtss\t{%1, %0|%0, %1}" |
a8083431 JH |
14578 | [(set_attr "type" "sse") |
14579 | (set_attr "mode" "SF") | |
14580 | (set_attr "athlon_decode" "*")]) | |
14581 | ||
14582 | (define_insn "sqrtsf2_i387" | |
e075ae69 RH |
14583 | [(set (match_operand:SF 0 "register_operand" "=f") |
14584 | (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] | |
a8083431 | 14585 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
abf80f8f | 14586 | && !TARGET_SSE_MATH" |
e075ae69 | 14587 | "fsqrt" |
0b5107cf | 14588 | [(set_attr "type" "fpspc") |
6ef67412 | 14589 | (set_attr "mode" "SF") |
0b5107cf | 14590 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14591 | |
a8083431 JH |
14592 | (define_expand "sqrtdf2" |
14593 | [(set (match_operand:DF 0 "register_operand" "") | |
14594 | (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))] | |
965f5423 JH |
14595 | "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) |
14596 | || (TARGET_SSE2 && TARGET_SSE_MATH)" | |
a8083431 | 14597 | { |
965f5423 | 14598 | if (!TARGET_SSE2 || !TARGET_SSE_MATH) |
2406cfed | 14599 | operands[1] = force_reg (DFmode, operands[1]); |
0f40f9f7 | 14600 | }) |
a8083431 JH |
14601 | |
14602 | (define_insn "sqrtdf2_1" | |
14603 | [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") | |
14604 | (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))] | |
14605 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 | |
965f5423 | 14606 | && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)" |
a8083431 JH |
14607 | "@ |
14608 | fsqrt | |
0f40f9f7 | 14609 | sqrtsd\t{%1, %0|%0, %1}" |
a8083431 JH |
14610 | [(set_attr "type" "fpspc,sse") |
14611 | (set_attr "mode" "DF,DF") | |
14612 | (set_attr "athlon_decode" "direct,*")]) | |
14613 | ||
14614 | (define_insn "sqrtdf2_1_sse_only" | |
14615 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
14616 | (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))] | |
965f5423 | 14617 | "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)" |
0f40f9f7 | 14618 | "sqrtsd\t{%1, %0|%0, %1}" |
a8083431 JH |
14619 | [(set_attr "type" "sse") |
14620 | (set_attr "mode" "DF") | |
14621 | (set_attr "athlon_decode" "*")]) | |
14622 | ||
14623 | (define_insn "sqrtdf2_i387" | |
e075ae69 RH |
14624 | [(set (match_operand:DF 0 "register_operand" "=f") |
14625 | (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] | |
14626 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 | |
abf80f8f | 14627 | && (!TARGET_SSE2 || !TARGET_SSE_MATH)" |
e075ae69 | 14628 | "fsqrt" |
0b5107cf | 14629 | [(set_attr "type" "fpspc") |
6ef67412 | 14630 | (set_attr "mode" "DF") |
0b5107cf | 14631 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14632 | |
6343a50e | 14633 | (define_insn "*sqrtextendsfdf2" |
e075ae69 RH |
14634 | [(set (match_operand:DF 0 "register_operand" "=f") |
14635 | (sqrt:DF (float_extend:DF | |
14636 | (match_operand:SF 1 "register_operand" "0"))))] | |
965f5423 JH |
14637 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14638 | && !(TARGET_SSE2 && TARGET_SSE_MATH)" | |
e075ae69 | 14639 | "fsqrt" |
0b5107cf | 14640 | [(set_attr "type" "fpspc") |
6ef67412 | 14641 | (set_attr "mode" "DF") |
0b5107cf | 14642 | (set_attr "athlon_decode" "direct")]) |
e075ae69 RH |
14643 | |
14644 | (define_insn "sqrtxf2" | |
14645 | [(set (match_operand:XF 0 "register_operand" "=f") | |
14646 | (sqrt:XF (match_operand:XF 1 "register_operand" "0")))] | |
1b0c37d7 | 14647 | "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 |
de6c5979 | 14648 | && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) " |
e075ae69 | 14649 | "fsqrt" |
0b5107cf | 14650 | [(set_attr "type" "fpspc") |
6ef67412 | 14651 | (set_attr "mode" "XF") |
0b5107cf | 14652 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14653 | |
2b589241 JH |
14654 | (define_insn "sqrttf2" |
14655 | [(set (match_operand:TF 0 "register_operand" "=f") | |
14656 | (sqrt:TF (match_operand:TF 1 "register_operand" "0")))] | |
14657 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 | |
de6c5979 | 14658 | && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) " |
2b589241 JH |
14659 | "fsqrt" |
14660 | [(set_attr "type" "fpspc") | |
14661 | (set_attr "mode" "XF") | |
14662 | (set_attr "athlon_decode" "direct")]) | |
14663 | ||
6343a50e | 14664 | (define_insn "*sqrtextenddfxf2" |
e075ae69 RH |
14665 | [(set (match_operand:XF 0 "register_operand" "=f") |
14666 | (sqrt:XF (float_extend:XF | |
14667 | (match_operand:DF 1 "register_operand" "0"))))] | |
30c99a84 | 14668 | "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" |
e075ae69 | 14669 | "fsqrt" |
0b5107cf | 14670 | [(set_attr "type" "fpspc") |
6ef67412 | 14671 | (set_attr "mode" "XF") |
0b5107cf | 14672 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14673 | |
2b589241 JH |
14674 | (define_insn "*sqrtextenddftf2" |
14675 | [(set (match_operand:TF 0 "register_operand" "=f") | |
14676 | (sqrt:TF (float_extend:TF | |
14677 | (match_operand:DF 1 "register_operand" "0"))))] | |
14678 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" | |
14679 | "fsqrt" | |
14680 | [(set_attr "type" "fpspc") | |
14681 | (set_attr "mode" "XF") | |
14682 | (set_attr "athlon_decode" "direct")]) | |
14683 | ||
6343a50e | 14684 | (define_insn "*sqrtextendsfxf2" |
e075ae69 RH |
14685 | [(set (match_operand:XF 0 "register_operand" "=f") |
14686 | (sqrt:XF (float_extend:XF | |
14687 | (match_operand:SF 1 "register_operand" "0"))))] | |
30c99a84 | 14688 | "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" |
e075ae69 | 14689 | "fsqrt" |
0b5107cf | 14690 | [(set_attr "type" "fpspc") |
6ef67412 | 14691 | (set_attr "mode" "XF") |
0b5107cf | 14692 | (set_attr "athlon_decode" "direct")]) |
e075ae69 | 14693 | |
2b589241 JH |
14694 | (define_insn "*sqrtextendsftf2" |
14695 | [(set (match_operand:TF 0 "register_operand" "=f") | |
14696 | (sqrt:TF (float_extend:TF | |
14697 | (match_operand:SF 1 "register_operand" "0"))))] | |
14698 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387" | |
14699 | "fsqrt" | |
14700 | [(set_attr "type" "fpspc") | |
14701 | (set_attr "mode" "XF") | |
14702 | (set_attr "athlon_decode" "direct")]) | |
14703 | ||
e075ae69 RH |
14704 | (define_insn "sindf2" |
14705 | [(set (match_operand:DF 0 "register_operand" "=f") | |
8ee41eaf | 14706 | (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))] |
de6c5979 BL |
14707 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14708 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14709 | "fsin" |
6ef67412 JH |
14710 | [(set_attr "type" "fpspc") |
14711 | (set_attr "mode" "DF")]) | |
e075ae69 RH |
14712 | |
14713 | (define_insn "sinsf2" | |
14714 | [(set (match_operand:SF 0 "register_operand" "=f") | |
8ee41eaf | 14715 | (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))] |
de6c5979 BL |
14716 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14717 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14718 | "fsin" |
6ef67412 JH |
14719 | [(set_attr "type" "fpspc") |
14720 | (set_attr "mode" "SF")]) | |
5f3d14e3 | 14721 | |
6343a50e | 14722 | (define_insn "*sinextendsfdf2" |
e075ae69 RH |
14723 | [(set (match_operand:DF 0 "register_operand" "=f") |
14724 | (unspec:DF [(float_extend:DF | |
8ee41eaf RH |
14725 | (match_operand:SF 1 "register_operand" "0"))] |
14726 | UNSPEC_SIN))] | |
de6c5979 BL |
14727 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14728 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14729 | "fsin" |
6ef67412 JH |
14730 | [(set_attr "type" "fpspc") |
14731 | (set_attr "mode" "DF")]) | |
4f9ca067 | 14732 | |
e075ae69 RH |
14733 | (define_insn "sinxf2" |
14734 | [(set (match_operand:XF 0 "register_operand" "=f") | |
8ee41eaf | 14735 | (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))] |
30c99a84 | 14736 | "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 |
de6c5979 | 14737 | && flag_unsafe_math_optimizations" |
e075ae69 | 14738 | "fsin" |
6ef67412 JH |
14739 | [(set_attr "type" "fpspc") |
14740 | (set_attr "mode" "XF")]) | |
5f3d14e3 | 14741 | |
2b589241 JH |
14742 | (define_insn "sintf2" |
14743 | [(set (match_operand:TF 0 "register_operand" "=f") | |
8ee41eaf | 14744 | (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))] |
de6c5979 BL |
14745 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14746 | && flag_unsafe_math_optimizations" | |
2b589241 JH |
14747 | "fsin" |
14748 | [(set_attr "type" "fpspc") | |
14749 | (set_attr "mode" "XF")]) | |
14750 | ||
e075ae69 RH |
14751 | (define_insn "cosdf2" |
14752 | [(set (match_operand:DF 0 "register_operand" "=f") | |
8ee41eaf | 14753 | (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))] |
de6c5979 BL |
14754 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14755 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14756 | "fcos" |
6ef67412 JH |
14757 | [(set_attr "type" "fpspc") |
14758 | (set_attr "mode" "DF")]) | |
bca7cce2 | 14759 | |
e075ae69 RH |
14760 | (define_insn "cossf2" |
14761 | [(set (match_operand:SF 0 "register_operand" "=f") | |
8ee41eaf | 14762 | (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))] |
de6c5979 BL |
14763 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14764 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14765 | "fcos" |
6ef67412 JH |
14766 | [(set_attr "type" "fpspc") |
14767 | (set_attr "mode" "SF")]) | |
bca7cce2 | 14768 | |
6343a50e | 14769 | (define_insn "*cosextendsfdf2" |
e075ae69 RH |
14770 | [(set (match_operand:DF 0 "register_operand" "=f") |
14771 | (unspec:DF [(float_extend:DF | |
8ee41eaf RH |
14772 | (match_operand:SF 1 "register_operand" "0"))] |
14773 | UNSPEC_COS))] | |
de6c5979 BL |
14774 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14775 | && flag_unsafe_math_optimizations" | |
e075ae69 | 14776 | "fcos" |
6ef67412 JH |
14777 | [(set_attr "type" "fpspc") |
14778 | (set_attr "mode" "DF")]) | |
5f3d14e3 | 14779 | |
e075ae69 RH |
14780 | (define_insn "cosxf2" |
14781 | [(set (match_operand:XF 0 "register_operand" "=f") | |
8ee41eaf | 14782 | (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))] |
1e07edd3 | 14783 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
de6c5979 | 14784 | && flag_unsafe_math_optimizations" |
e075ae69 | 14785 | "fcos" |
6ef67412 JH |
14786 | [(set_attr "type" "fpspc") |
14787 | (set_attr "mode" "XF")]) | |
2b589241 JH |
14788 | |
14789 | (define_insn "costf2" | |
14790 | [(set (match_operand:TF 0 "register_operand" "=f") | |
8ee41eaf | 14791 | (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))] |
de6c5979 BL |
14792 | "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 |
14793 | && flag_unsafe_math_optimizations" | |
2b589241 JH |
14794 | "fcos" |
14795 | [(set_attr "type" "fpspc") | |
14796 | (set_attr "mode" "XF")]) | |
e075ae69 RH |
14797 | \f |
14798 | ;; Block operation instructions | |
886c62d1 | 14799 | |
7c7ef435 JH |
14800 | (define_insn "cld" |
14801 | [(set (reg:SI 19) (const_int 0))] | |
14802 | "" | |
14803 | "cld" | |
14804 | [(set_attr "type" "cld")]) | |
14805 | ||
886c62d1 | 14806 | (define_expand "movstrsi" |
f90800f8 JH |
14807 | [(use (match_operand:BLK 0 "memory_operand" "")) |
14808 | (use (match_operand:BLK 1 "memory_operand" "")) | |
79f05c19 | 14809 | (use (match_operand:SI 2 "nonmemory_operand" "")) |
f90800f8 | 14810 | (use (match_operand:SI 3 "const_int_operand" ""))] |
886c62d1 | 14811 | "" |
886c62d1 | 14812 | { |
0945b39d JH |
14813 | if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3])) |
14814 | DONE; | |
14815 | else | |
14816 | FAIL; | |
0f40f9f7 | 14817 | }) |
79f05c19 | 14818 | |
0945b39d JH |
14819 | (define_expand "movstrdi" |
14820 | [(use (match_operand:BLK 0 "memory_operand" "")) | |
14821 | (use (match_operand:BLK 1 "memory_operand" "")) | |
14822 | (use (match_operand:DI 2 "nonmemory_operand" "")) | |
14823 | (use (match_operand:DI 3 "const_int_operand" ""))] | |
14824 | "TARGET_64BIT" | |
0945b39d JH |
14825 | { |
14826 | if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3])) | |
14827 | DONE; | |
14828 | else | |
14829 | FAIL; | |
0f40f9f7 | 14830 | }) |
79f05c19 | 14831 | |
0945b39d JH |
14832 | ;; Most CPUs don't like single string operations |
14833 | ;; Handle this case here to simplify previous expander. | |
79f05c19 | 14834 | |
0945b39d JH |
14835 | (define_expand "strmovdi_rex64" |
14836 | [(set (match_dup 2) | |
14837 | (mem:DI (match_operand:DI 1 "register_operand" ""))) | |
14838 | (set (mem:DI (match_operand:DI 0 "register_operand" "")) | |
14839 | (match_dup 2)) | |
14840 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8))) | |
14841 | (clobber (reg:CC 17))]) | |
14842 | (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8))) | |
14843 | (clobber (reg:CC 17))])] | |
14844 | "TARGET_64BIT" | |
0945b39d JH |
14845 | { |
14846 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
79f05c19 | 14847 | { |
0945b39d JH |
14848 | emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0], |
14849 | operands[1])); | |
14850 | DONE; | |
79f05c19 | 14851 | } |
0945b39d JH |
14852 | else |
14853 | operands[2] = gen_reg_rtx (DImode); | |
0f40f9f7 | 14854 | }) |
886c62d1 | 14855 | |
56c0e8fa | 14856 | |
79f05c19 JH |
14857 | (define_expand "strmovsi" |
14858 | [(set (match_dup 2) | |
14859 | (mem:SI (match_operand:SI 1 "register_operand" ""))) | |
14860 | (set (mem:SI (match_operand:SI 0 "register_operand" "")) | |
14861 | (match_dup 2)) | |
14862 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4))) | |
14863 | (clobber (reg:CC 17))]) | |
14864 | (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4))) | |
14865 | (clobber (reg:CC 17))])] | |
14866 | "" | |
79f05c19 | 14867 | { |
0945b39d JH |
14868 | if (TARGET_64BIT) |
14869 | { | |
14870 | emit_insn (gen_strmovsi_rex64 (operands[0], operands[1])); | |
14871 | DONE; | |
14872 | } | |
79f05c19 JH |
14873 | if (TARGET_SINGLE_STRINGOP || optimize_size) |
14874 | { | |
14875 | emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0], | |
14876 | operands[1])); | |
14877 | DONE; | |
14878 | } | |
14879 | else | |
14880 | operands[2] = gen_reg_rtx (SImode); | |
0f40f9f7 | 14881 | }) |
79f05c19 | 14882 | |
0945b39d JH |
14883 | (define_expand "strmovsi_rex64" |
14884 | [(set (match_dup 2) | |
14885 | (mem:SI (match_operand:DI 1 "register_operand" ""))) | |
14886 | (set (mem:SI (match_operand:DI 0 "register_operand" "")) | |
14887 | (match_dup 2)) | |
14888 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4))) | |
14889 | (clobber (reg:CC 17))]) | |
14890 | (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4))) | |
14891 | (clobber (reg:CC 17))])] | |
14892 | "TARGET_64BIT" | |
0945b39d JH |
14893 | { |
14894 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
14895 | { | |
14896 | emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0], | |
14897 | operands[1])); | |
14898 | DONE; | |
14899 | } | |
14900 | else | |
14901 | operands[2] = gen_reg_rtx (SImode); | |
0f40f9f7 | 14902 | }) |
0945b39d | 14903 | |
f90800f8 JH |
14904 | (define_expand "strmovhi" |
14905 | [(set (match_dup 2) | |
14906 | (mem:HI (match_operand:SI 1 "register_operand" ""))) | |
14907 | (set (mem:HI (match_operand:SI 0 "register_operand" "")) | |
14908 | (match_dup 2)) | |
14909 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2))) | |
14910 | (clobber (reg:CC 17))]) | |
14911 | (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2))) | |
14912 | (clobber (reg:CC 17))])] | |
886c62d1 | 14913 | "" |
886c62d1 | 14914 | { |
0945b39d JH |
14915 | if (TARGET_64BIT) |
14916 | { | |
14917 | emit_insn (gen_strmovhi_rex64 (operands[0], operands[1])); | |
14918 | DONE; | |
14919 | } | |
f90800f8 | 14920 | if (TARGET_SINGLE_STRINGOP || optimize_size) |
886c62d1 | 14921 | { |
f90800f8 JH |
14922 | emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0], |
14923 | operands[1])); | |
14924 | DONE; | |
14925 | } | |
14926 | else | |
14927 | operands[2] = gen_reg_rtx (HImode); | |
0f40f9f7 | 14928 | }) |
886c62d1 | 14929 | |
0945b39d JH |
14930 | (define_expand "strmovhi_rex64" |
14931 | [(set (match_dup 2) | |
14932 | (mem:HI (match_operand:DI 1 "register_operand" ""))) | |
14933 | (set (mem:HI (match_operand:DI 0 "register_operand" "")) | |
14934 | (match_dup 2)) | |
14935 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2))) | |
14936 | (clobber (reg:CC 17))]) | |
14937 | (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2))) | |
14938 | (clobber (reg:CC 17))])] | |
14939 | "TARGET_64BIT" | |
0945b39d JH |
14940 | { |
14941 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
14942 | { | |
14943 | emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0], | |
14944 | operands[1])); | |
14945 | DONE; | |
14946 | } | |
14947 | else | |
14948 | operands[2] = gen_reg_rtx (HImode); | |
0f40f9f7 | 14949 | }) |
0945b39d | 14950 | |
f90800f8 JH |
14951 | (define_expand "strmovqi" |
14952 | [(set (match_dup 2) | |
14953 | (mem:QI (match_operand:SI 1 "register_operand" ""))) | |
14954 | (set (mem:QI (match_operand:SI 0 "register_operand" "")) | |
14955 | (match_dup 2)) | |
14956 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) | |
14957 | (clobber (reg:CC 17))]) | |
14958 | (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1))) | |
14959 | (clobber (reg:CC 17))])] | |
14960 | "" | |
f90800f8 | 14961 | { |
0945b39d JH |
14962 | if (TARGET_64BIT) |
14963 | { | |
14964 | emit_insn (gen_strmovqi_rex64 (operands[0], operands[1])); | |
14965 | DONE; | |
14966 | } | |
f90800f8 JH |
14967 | if (TARGET_SINGLE_STRINGOP || optimize_size) |
14968 | { | |
14969 | emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0], | |
14970 | operands[1])); | |
14971 | DONE; | |
886c62d1 | 14972 | } |
f90800f8 JH |
14973 | else |
14974 | operands[2] = gen_reg_rtx (QImode); | |
0f40f9f7 | 14975 | }) |
f90800f8 | 14976 | |
0945b39d JH |
14977 | (define_expand "strmovqi_rex64" |
14978 | [(set (match_dup 2) | |
14979 | (mem:QI (match_operand:DI 1 "register_operand" ""))) | |
14980 | (set (mem:QI (match_operand:DI 0 "register_operand" "")) | |
14981 | (match_dup 2)) | |
14982 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1))) | |
14983 | (clobber (reg:CC 17))]) | |
14984 | (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1))) | |
14985 | (clobber (reg:CC 17))])] | |
1b0c37d7 | 14986 | "TARGET_64BIT" |
0945b39d JH |
14987 | { |
14988 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
14989 | { | |
14990 | emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0], | |
14991 | operands[1])); | |
14992 | DONE; | |
14993 | } | |
14994 | else | |
14995 | operands[2] = gen_reg_rtx (QImode); | |
0f40f9f7 | 14996 | }) |
0945b39d JH |
14997 | |
14998 | (define_insn "strmovdi_rex_1" | |
14999 | [(set (mem:DI (match_operand:DI 2 "register_operand" "0")) | |
15000 | (mem:DI (match_operand:DI 3 "register_operand" "1"))) | |
15001 | (set (match_operand:DI 0 "register_operand" "=D") | |
15002 | (plus:DI (match_dup 2) | |
15003 | (const_int 8))) | |
15004 | (set (match_operand:DI 1 "register_operand" "=S") | |
15005 | (plus:DI (match_dup 3) | |
15006 | (const_int 8))) | |
15007 | (use (reg:SI 19))] | |
15008 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
15009 | "movsq" | |
15010 | [(set_attr "type" "str") | |
15011 | (set_attr "mode" "DI") | |
15012 | (set_attr "memory" "both")]) | |
15013 | ||
79f05c19 JH |
15014 | (define_insn "strmovsi_1" |
15015 | [(set (mem:SI (match_operand:SI 2 "register_operand" "0")) | |
15016 | (mem:SI (match_operand:SI 3 "register_operand" "1"))) | |
15017 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 15018 | (plus:SI (match_dup 2) |
79f05c19 JH |
15019 | (const_int 4))) |
15020 | (set (match_operand:SI 1 "register_operand" "=S") | |
b1cdafbb | 15021 | (plus:SI (match_dup 3) |
79f05c19 JH |
15022 | (const_int 4))) |
15023 | (use (reg:SI 19))] | |
0945b39d | 15024 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
371bc54b | 15025 | "{movsl|movsd}" |
0945b39d JH |
15026 | [(set_attr "type" "str") |
15027 | (set_attr "mode" "SI") | |
15028 | (set_attr "memory" "both")]) | |
15029 | ||
15030 | (define_insn "strmovsi_rex_1" | |
15031 | [(set (mem:SI (match_operand:DI 2 "register_operand" "0")) | |
15032 | (mem:SI (match_operand:DI 3 "register_operand" "1"))) | |
15033 | (set (match_operand:DI 0 "register_operand" "=D") | |
15034 | (plus:DI (match_dup 2) | |
15035 | (const_int 4))) | |
15036 | (set (match_operand:DI 1 "register_operand" "=S") | |
15037 | (plus:DI (match_dup 3) | |
15038 | (const_int 4))) | |
15039 | (use (reg:SI 19))] | |
15040 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
371bc54b | 15041 | "{movsl|movsd}" |
79f05c19 | 15042 | [(set_attr "type" "str") |
6ef67412 | 15043 | (set_attr "mode" "SI") |
79f05c19 JH |
15044 | (set_attr "memory" "both")]) |
15045 | ||
f90800f8 JH |
15046 | (define_insn "strmovhi_1" |
15047 | [(set (mem:HI (match_operand:SI 2 "register_operand" "0")) | |
15048 | (mem:HI (match_operand:SI 3 "register_operand" "1"))) | |
15049 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 15050 | (plus:SI (match_dup 2) |
f90800f8 JH |
15051 | (const_int 2))) |
15052 | (set (match_operand:SI 1 "register_operand" "=S") | |
b1cdafbb | 15053 | (plus:SI (match_dup 3) |
f90800f8 JH |
15054 | (const_int 2))) |
15055 | (use (reg:SI 19))] | |
0945b39d JH |
15056 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
15057 | "movsw" | |
15058 | [(set_attr "type" "str") | |
15059 | (set_attr "memory" "both") | |
15060 | (set_attr "mode" "HI")]) | |
15061 | ||
15062 | (define_insn "strmovhi_rex_1" | |
15063 | [(set (mem:HI (match_operand:DI 2 "register_operand" "0")) | |
15064 | (mem:HI (match_operand:DI 3 "register_operand" "1"))) | |
15065 | (set (match_operand:DI 0 "register_operand" "=D") | |
15066 | (plus:DI (match_dup 2) | |
15067 | (const_int 2))) | |
15068 | (set (match_operand:DI 1 "register_operand" "=S") | |
15069 | (plus:DI (match_dup 3) | |
15070 | (const_int 2))) | |
15071 | (use (reg:SI 19))] | |
15072 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
f90800f8 JH |
15073 | "movsw" |
15074 | [(set_attr "type" "str") | |
15075 | (set_attr "memory" "both") | |
6ef67412 | 15076 | (set_attr "mode" "HI")]) |
f90800f8 JH |
15077 | |
15078 | (define_insn "strmovqi_1" | |
15079 | [(set (mem:QI (match_operand:SI 2 "register_operand" "0")) | |
15080 | (mem:QI (match_operand:SI 3 "register_operand" "1"))) | |
15081 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 15082 | (plus:SI (match_dup 2) |
f90800f8 JH |
15083 | (const_int 1))) |
15084 | (set (match_operand:SI 1 "register_operand" "=S") | |
b1cdafbb | 15085 | (plus:SI (match_dup 3) |
f90800f8 JH |
15086 | (const_int 1))) |
15087 | (use (reg:SI 19))] | |
0945b39d | 15088 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
f90800f8 JH |
15089 | "movsb" |
15090 | [(set_attr "type" "str") | |
6ef67412 JH |
15091 | (set_attr "memory" "both") |
15092 | (set_attr "mode" "QI")]) | |
f90800f8 | 15093 | |
0945b39d JH |
15094 | (define_insn "strmovqi_rex_1" |
15095 | [(set (mem:QI (match_operand:DI 2 "register_operand" "0")) | |
15096 | (mem:QI (match_operand:DI 3 "register_operand" "1"))) | |
15097 | (set (match_operand:DI 0 "register_operand" "=D") | |
15098 | (plus:DI (match_dup 2) | |
15099 | (const_int 1))) | |
15100 | (set (match_operand:DI 1 "register_operand" "=S") | |
15101 | (plus:DI (match_dup 3) | |
15102 | (const_int 1))) | |
15103 | (use (reg:SI 19))] | |
15104 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
15105 | "movsb" | |
15106 | [(set_attr "type" "str") | |
15107 | (set_attr "memory" "both") | |
15108 | (set_attr "mode" "QI")]) | |
15109 | ||
15110 | (define_insn "rep_movdi_rex64" | |
15111 | [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) | |
15112 | (set (match_operand:DI 0 "register_operand" "=D") | |
15113 | (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2") | |
15114 | (const_int 3)) | |
15115 | (match_operand:DI 3 "register_operand" "0"))) | |
15116 | (set (match_operand:DI 1 "register_operand" "=S") | |
15117 | (plus:DI (ashift:DI (match_dup 5) (const_int 3)) | |
15118 | (match_operand:DI 4 "register_operand" "1"))) | |
15119 | (set (mem:BLK (match_dup 3)) | |
15120 | (mem:BLK (match_dup 4))) | |
15121 | (use (match_dup 5)) | |
15122 | (use (reg:SI 19))] | |
15123 | "TARGET_64BIT" | |
8554d9a4 | 15124 | "{rep\;movsq|rep movsq}" |
0945b39d JH |
15125 | [(set_attr "type" "str") |
15126 | (set_attr "prefix_rep" "1") | |
15127 | (set_attr "memory" "both") | |
15128 | (set_attr "mode" "DI")]) | |
15129 | ||
f90800f8 JH |
15130 | (define_insn "rep_movsi" |
15131 | [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0)) | |
f90800f8 | 15132 | (set (match_operand:SI 0 "register_operand" "=D") |
b1cdafbb JH |
15133 | (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2") |
15134 | (const_int 2)) | |
15135 | (match_operand:SI 3 "register_operand" "0"))) | |
f90800f8 | 15136 | (set (match_operand:SI 1 "register_operand" "=S") |
b1cdafbb JH |
15137 | (plus:SI (ashift:SI (match_dup 5) (const_int 2)) |
15138 | (match_operand:SI 4 "register_operand" "1"))) | |
f90800f8 JH |
15139 | (set (mem:BLK (match_dup 3)) |
15140 | (mem:BLK (match_dup 4))) | |
b1cdafbb | 15141 | (use (match_dup 5)) |
f90800f8 | 15142 | (use (reg:SI 19))] |
0945b39d | 15143 | "!TARGET_64BIT" |
8554d9a4 | 15144 | "{rep\;movsl|rep movsd}" |
0945b39d JH |
15145 | [(set_attr "type" "str") |
15146 | (set_attr "prefix_rep" "1") | |
15147 | (set_attr "memory" "both") | |
15148 | (set_attr "mode" "SI")]) | |
15149 | ||
15150 | (define_insn "rep_movsi_rex64" | |
15151 | [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) | |
15152 | (set (match_operand:DI 0 "register_operand" "=D") | |
15153 | (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2") | |
15154 | (const_int 2)) | |
15155 | (match_operand:DI 3 "register_operand" "0"))) | |
15156 | (set (match_operand:DI 1 "register_operand" "=S") | |
15157 | (plus:DI (ashift:DI (match_dup 5) (const_int 2)) | |
15158 | (match_operand:DI 4 "register_operand" "1"))) | |
15159 | (set (mem:BLK (match_dup 3)) | |
15160 | (mem:BLK (match_dup 4))) | |
15161 | (use (match_dup 5)) | |
15162 | (use (reg:SI 19))] | |
15163 | "TARGET_64BIT" | |
8554d9a4 | 15164 | "{rep\;movsl|rep movsd}" |
f90800f8 | 15165 | [(set_attr "type" "str") |
6ef67412 JH |
15166 | (set_attr "prefix_rep" "1") |
15167 | (set_attr "memory" "both") | |
15168 | (set_attr "mode" "SI")]) | |
f90800f8 JH |
15169 | |
15170 | (define_insn "rep_movqi" | |
15171 | [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0)) | |
f90800f8 | 15172 | (set (match_operand:SI 0 "register_operand" "=D") |
b1cdafbb JH |
15173 | (plus:SI (match_operand:SI 3 "register_operand" "0") |
15174 | (match_operand:SI 5 "register_operand" "2"))) | |
f90800f8 | 15175 | (set (match_operand:SI 1 "register_operand" "=S") |
b1cdafbb | 15176 | (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5))) |
f90800f8 JH |
15177 | (set (mem:BLK (match_dup 3)) |
15178 | (mem:BLK (match_dup 4))) | |
b1cdafbb | 15179 | (use (match_dup 5)) |
f90800f8 | 15180 | (use (reg:SI 19))] |
0945b39d | 15181 | "!TARGET_64BIT" |
8554d9a4 | 15182 | "{rep\;movsb|rep movsb}" |
0945b39d JH |
15183 | [(set_attr "type" "str") |
15184 | (set_attr "prefix_rep" "1") | |
15185 | (set_attr "memory" "both") | |
15186 | (set_attr "mode" "SI")]) | |
15187 | ||
15188 | (define_insn "rep_movqi_rex64" | |
15189 | [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) | |
15190 | (set (match_operand:DI 0 "register_operand" "=D") | |
15191 | (plus:DI (match_operand:DI 3 "register_operand" "0") | |
15192 | (match_operand:DI 5 "register_operand" "2"))) | |
15193 | (set (match_operand:DI 1 "register_operand" "=S") | |
15194 | (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5))) | |
15195 | (set (mem:BLK (match_dup 3)) | |
15196 | (mem:BLK (match_dup 4))) | |
15197 | (use (match_dup 5)) | |
15198 | (use (reg:SI 19))] | |
15199 | "TARGET_64BIT" | |
8554d9a4 | 15200 | "{rep\;movsb|rep movsb}" |
f90800f8 | 15201 | [(set_attr "type" "str") |
6ef67412 JH |
15202 | (set_attr "prefix_rep" "1") |
15203 | (set_attr "memory" "both") | |
15204 | (set_attr "mode" "SI")]) | |
886c62d1 | 15205 | |
0ae40045 | 15206 | (define_expand "clrstrsi" |
e2e52e1b | 15207 | [(use (match_operand:BLK 0 "memory_operand" "")) |
79f05c19 | 15208 | (use (match_operand:SI 1 "nonmemory_operand" "")) |
0945b39d | 15209 | (use (match_operand 2 "const_int_operand" ""))] |
0ae40045 | 15210 | "" |
0ae40045 | 15211 | { |
0945b39d JH |
15212 | if (ix86_expand_clrstr (operands[0], operands[1], operands[2])) |
15213 | DONE; | |
15214 | else | |
15215 | FAIL; | |
0f40f9f7 | 15216 | }) |
e2e52e1b | 15217 | |
0945b39d JH |
15218 | (define_expand "clrstrdi" |
15219 | [(use (match_operand:BLK 0 "memory_operand" "")) | |
15220 | (use (match_operand:DI 1 "nonmemory_operand" "")) | |
15221 | (use (match_operand 2 "const_int_operand" ""))] | |
15222 | "TARGET_64BIT" | |
0945b39d JH |
15223 | { |
15224 | if (ix86_expand_clrstr (operands[0], operands[1], operands[2])) | |
15225 | DONE; | |
15226 | else | |
15227 | FAIL; | |
0f40f9f7 | 15228 | }) |
e2e52e1b | 15229 | |
0945b39d JH |
15230 | ;; Most CPUs don't like single string operations |
15231 | ;; Handle this case here to simplify previous expander. | |
79f05c19 | 15232 | |
0945b39d JH |
15233 | (define_expand "strsetdi_rex64" |
15234 | [(set (mem:DI (match_operand:DI 0 "register_operand" "")) | |
15235 | (match_operand:DI 1 "register_operand" "")) | |
15236 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8))) | |
15237 | (clobber (reg:CC 17))])] | |
15238 | "TARGET_64BIT" | |
0945b39d JH |
15239 | { |
15240 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
79f05c19 | 15241 | { |
0945b39d JH |
15242 | emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1])); |
15243 | DONE; | |
79f05c19 | 15244 | } |
0f40f9f7 | 15245 | }) |
e2e52e1b | 15246 | |
79f05c19 JH |
15247 | (define_expand "strsetsi" |
15248 | [(set (mem:SI (match_operand:SI 0 "register_operand" "")) | |
15249 | (match_operand:SI 1 "register_operand" "")) | |
15250 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4))) | |
15251 | (clobber (reg:CC 17))])] | |
15252 | "" | |
79f05c19 | 15253 | { |
0945b39d JH |
15254 | if (TARGET_64BIT) |
15255 | { | |
15256 | emit_insn (gen_strsetsi_rex64 (operands[0], operands[1])); | |
15257 | DONE; | |
15258 | } | |
15259 | else if (TARGET_SINGLE_STRINGOP || optimize_size) | |
79f05c19 JH |
15260 | { |
15261 | emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1])); | |
15262 | DONE; | |
15263 | } | |
0f40f9f7 | 15264 | }) |
79f05c19 | 15265 | |
0945b39d JH |
15266 | (define_expand "strsetsi_rex64" |
15267 | [(set (mem:SI (match_operand:DI 0 "register_operand" "")) | |
15268 | (match_operand:SI 1 "register_operand" "")) | |
15269 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4))) | |
15270 | (clobber (reg:CC 17))])] | |
15271 | "TARGET_64BIT" | |
0945b39d JH |
15272 | { |
15273 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
15274 | { | |
15275 | emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1])); | |
15276 | DONE; | |
15277 | } | |
0f40f9f7 | 15278 | }) |
0945b39d | 15279 | |
e2e52e1b JH |
15280 | (define_expand "strsethi" |
15281 | [(set (mem:HI (match_operand:SI 0 "register_operand" "")) | |
15282 | (match_operand:HI 1 "register_operand" "")) | |
15283 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2))) | |
15284 | (clobber (reg:CC 17))])] | |
15285 | "" | |
e2e52e1b | 15286 | { |
0945b39d JH |
15287 | if (TARGET_64BIT) |
15288 | { | |
15289 | emit_insn (gen_strsethi_rex64 (operands[0], operands[1])); | |
15290 | DONE; | |
15291 | } | |
15292 | else if (TARGET_SINGLE_STRINGOP || optimize_size) | |
e2e52e1b JH |
15293 | { |
15294 | emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1])); | |
15295 | DONE; | |
15296 | } | |
0f40f9f7 | 15297 | }) |
0ae40045 | 15298 | |
0945b39d JH |
15299 | (define_expand "strsethi_rex64" |
15300 | [(set (mem:HI (match_operand:DI 0 "register_operand" "")) | |
15301 | (match_operand:HI 1 "register_operand" "")) | |
15302 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2))) | |
15303 | (clobber (reg:CC 17))])] | |
15304 | "TARGET_64BIT" | |
0945b39d JH |
15305 | { |
15306 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
15307 | { | |
15308 | emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1])); | |
15309 | DONE; | |
15310 | } | |
0f40f9f7 | 15311 | }) |
0945b39d | 15312 | |
e2e52e1b JH |
15313 | (define_expand "strsetqi" |
15314 | [(set (mem:QI (match_operand:SI 0 "register_operand" "")) | |
15315 | (match_operand:QI 1 "register_operand" "")) | |
15316 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) | |
15317 | (clobber (reg:CC 17))])] | |
15318 | "" | |
e2e52e1b | 15319 | { |
0945b39d JH |
15320 | if (TARGET_64BIT) |
15321 | { | |
15322 | emit_insn (gen_strsetqi_rex64 (operands[0], operands[1])); | |
15323 | DONE; | |
15324 | } | |
15325 | else if (TARGET_SINGLE_STRINGOP || optimize_size) | |
e2e52e1b JH |
15326 | { |
15327 | emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1])); | |
15328 | DONE; | |
15329 | } | |
0f40f9f7 | 15330 | }) |
0ae40045 | 15331 | |
0945b39d JH |
15332 | (define_expand "strsetqi_rex64" |
15333 | [(set (mem:QI (match_operand:DI 0 "register_operand" "")) | |
15334 | (match_operand:QI 1 "register_operand" "")) | |
15335 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1))) | |
15336 | (clobber (reg:CC 17))])] | |
15337 | "TARGET_64BIT" | |
0945b39d JH |
15338 | { |
15339 | if (TARGET_SINGLE_STRINGOP || optimize_size) | |
15340 | { | |
15341 | emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1])); | |
15342 | DONE; | |
15343 | } | |
0f40f9f7 | 15344 | }) |
0945b39d JH |
15345 | |
15346 | (define_insn "strsetdi_rex_1" | |
15347 | [(set (mem:SI (match_operand:DI 1 "register_operand" "0")) | |
15348 | (match_operand:SI 2 "register_operand" "a")) | |
15349 | (set (match_operand:DI 0 "register_operand" "=D") | |
15350 | (plus:DI (match_dup 1) | |
15351 | (const_int 8))) | |
15352 | (use (reg:SI 19))] | |
15353 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
15354 | "stosq" | |
15355 | [(set_attr "type" "str") | |
15356 | (set_attr "memory" "store") | |
15357 | (set_attr "mode" "DI")]) | |
15358 | ||
79f05c19 JH |
15359 | (define_insn "strsetsi_1" |
15360 | [(set (mem:SI (match_operand:SI 1 "register_operand" "0")) | |
15361 | (match_operand:SI 2 "register_operand" "a")) | |
15362 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 15363 | (plus:SI (match_dup 1) |
79f05c19 JH |
15364 | (const_int 4))) |
15365 | (use (reg:SI 19))] | |
0945b39d | 15366 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
8554d9a4 | 15367 | "{stosl|stosd}" |
0945b39d JH |
15368 | [(set_attr "type" "str") |
15369 | (set_attr "memory" "store") | |
15370 | (set_attr "mode" "SI")]) | |
15371 | ||
15372 | (define_insn "strsetsi_rex_1" | |
15373 | [(set (mem:SI (match_operand:DI 1 "register_operand" "0")) | |
15374 | (match_operand:SI 2 "register_operand" "a")) | |
15375 | (set (match_operand:DI 0 "register_operand" "=D") | |
15376 | (plus:DI (match_dup 1) | |
15377 | (const_int 4))) | |
15378 | (use (reg:SI 19))] | |
15379 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
8554d9a4 | 15380 | "{stosl|stosd}" |
79f05c19 | 15381 | [(set_attr "type" "str") |
6ef67412 JH |
15382 | (set_attr "memory" "store") |
15383 | (set_attr "mode" "SI")]) | |
79f05c19 | 15384 | |
e2e52e1b JH |
15385 | (define_insn "strsethi_1" |
15386 | [(set (mem:HI (match_operand:SI 1 "register_operand" "0")) | |
15387 | (match_operand:HI 2 "register_operand" "a")) | |
15388 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 15389 | (plus:SI (match_dup 1) |
e2e52e1b JH |
15390 | (const_int 2))) |
15391 | (use (reg:SI 19))] | |
0945b39d JH |
15392 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
15393 | "stosw" | |
15394 | [(set_attr "type" "str") | |
15395 | (set_attr "memory" "store") | |
15396 | (set_attr "mode" "HI")]) | |
15397 | ||
15398 | (define_insn "strsethi_rex_1" | |
15399 | [(set (mem:HI (match_operand:DI 1 "register_operand" "0")) | |
15400 | (match_operand:HI 2 "register_operand" "a")) | |
15401 | (set (match_operand:DI 0 "register_operand" "=D") | |
15402 | (plus:DI (match_dup 1) | |
15403 | (const_int 2))) | |
15404 | (use (reg:SI 19))] | |
15405 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
e2e52e1b JH |
15406 | "stosw" |
15407 | [(set_attr "type" "str") | |
15408 | (set_attr "memory" "store") | |
6ef67412 | 15409 | (set_attr "mode" "HI")]) |
e2e52e1b JH |
15410 | |
15411 | (define_insn "strsetqi_1" | |
15412 | [(set (mem:QI (match_operand:SI 1 "register_operand" "0")) | |
15413 | (match_operand:QI 2 "register_operand" "a")) | |
15414 | (set (match_operand:SI 0 "register_operand" "=D") | |
b1cdafbb | 15415 | (plus:SI (match_dup 1) |
e2e52e1b JH |
15416 | (const_int 1))) |
15417 | (use (reg:SI 19))] | |
0945b39d JH |
15418 | "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" |
15419 | "stosb" | |
15420 | [(set_attr "type" "str") | |
15421 | (set_attr "memory" "store") | |
15422 | (set_attr "mode" "QI")]) | |
15423 | ||
15424 | (define_insn "strsetqi_rex_1" | |
15425 | [(set (mem:QI (match_operand:DI 1 "register_operand" "0")) | |
15426 | (match_operand:QI 2 "register_operand" "a")) | |
15427 | (set (match_operand:DI 0 "register_operand" "=D") | |
15428 | (plus:DI (match_dup 1) | |
15429 | (const_int 1))) | |
15430 | (use (reg:SI 19))] | |
15431 | "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" | |
e2e52e1b JH |
15432 | "stosb" |
15433 | [(set_attr "type" "str") | |
6ef67412 JH |
15434 | (set_attr "memory" "store") |
15435 | (set_attr "mode" "QI")]) | |
e2e52e1b | 15436 | |
0945b39d JH |
15437 | (define_insn "rep_stosdi_rex64" |
15438 | [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) | |
15439 | (set (match_operand:DI 0 "register_operand" "=D") | |
15440 | (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1") | |
15441 | (const_int 3)) | |
15442 | (match_operand:DI 3 "register_operand" "0"))) | |
15443 | (set (mem:BLK (match_dup 3)) | |
15444 | (const_int 0)) | |
15445 | (use (match_operand:DI 2 "register_operand" "a")) | |
15446 | (use (match_dup 4)) | |
15447 | (use (reg:SI 19))] | |
15448 | "TARGET_64BIT" | |
8554d9a4 | 15449 | "{rep\;stosq|rep stosq}" |
0945b39d JH |
15450 | [(set_attr "type" "str") |
15451 | (set_attr "prefix_rep" "1") | |
15452 | (set_attr "memory" "store") | |
15453 | (set_attr "mode" "DI")]) | |
15454 | ||
e2e52e1b JH |
15455 | (define_insn "rep_stossi" |
15456 | [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0)) | |
e2e52e1b | 15457 | (set (match_operand:SI 0 "register_operand" "=D") |
b1cdafbb JH |
15458 | (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1") |
15459 | (const_int 2)) | |
15460 | (match_operand:SI 3 "register_operand" "0"))) | |
e2e52e1b | 15461 | (set (mem:BLK (match_dup 3)) |
0ae40045 | 15462 | (const_int 0)) |
b1cdafbb JH |
15463 | (use (match_operand:SI 2 "register_operand" "a")) |
15464 | (use (match_dup 4)) | |
e2e52e1b | 15465 | (use (reg:SI 19))] |
0945b39d | 15466 | "!TARGET_64BIT" |
8554d9a4 | 15467 | "{rep\;stosl|rep stosd}" |
0945b39d JH |
15468 | [(set_attr "type" "str") |
15469 | (set_attr "prefix_rep" "1") | |
15470 | (set_attr "memory" "store") | |
15471 | (set_attr "mode" "SI")]) | |
15472 | ||
15473 | (define_insn "rep_stossi_rex64" | |
15474 | [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) | |
15475 | (set (match_operand:DI 0 "register_operand" "=D") | |
15476 | (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1") | |
15477 | (const_int 2)) | |
15478 | (match_operand:DI 3 "register_operand" "0"))) | |
15479 | (set (mem:BLK (match_dup 3)) | |
15480 | (const_int 0)) | |
15481 | (use (match_operand:SI 2 "register_operand" "a")) | |
15482 | (use (match_dup 4)) | |
15483 | (use (reg:SI 19))] | |
15484 | "TARGET_64BIT" | |
8554d9a4 | 15485 | "{rep\;stosl|rep stosd}" |
e2e52e1b | 15486 | [(set_attr "type" "str") |
6ef67412 JH |
15487 | (set_attr "prefix_rep" "1") |
15488 | (set_attr "memory" "store") | |
15489 | (set_attr "mode" "SI")]) | |
0ae40045 | 15490 | |
e2e52e1b JH |
15491 | (define_insn "rep_stosqi" |
15492 | [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0)) | |
e2e52e1b | 15493 | (set (match_operand:SI 0 "register_operand" "=D") |
b1cdafbb JH |
15494 | (plus:SI (match_operand:SI 3 "register_operand" "0") |
15495 | (match_operand:SI 4 "register_operand" "1"))) | |
e2e52e1b JH |
15496 | (set (mem:BLK (match_dup 3)) |
15497 | (const_int 0)) | |
b1cdafbb JH |
15498 | (use (match_operand:QI 2 "register_operand" "a")) |
15499 | (use (match_dup 4)) | |
e2e52e1b | 15500 | (use (reg:SI 19))] |
0945b39d | 15501 | "!TARGET_64BIT" |
8554d9a4 | 15502 | "{rep\;stosb|rep stosb}" |
0945b39d JH |
15503 | [(set_attr "type" "str") |
15504 | (set_attr "prefix_rep" "1") | |
15505 | (set_attr "memory" "store") | |
15506 | (set_attr "mode" "QI")]) | |
15507 | ||
15508 | (define_insn "rep_stosqi_rex64" | |
15509 | [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) | |
15510 | (set (match_operand:DI 0 "register_operand" "=D") | |
15511 | (plus:DI (match_operand:DI 3 "register_operand" "0") | |
15512 | (match_operand:DI 4 "register_operand" "1"))) | |
15513 | (set (mem:BLK (match_dup 3)) | |
15514 | (const_int 0)) | |
15515 | (use (match_operand:QI 2 "register_operand" "a")) | |
15516 | (use (match_dup 4)) | |
15517 | (use (reg:DI 19))] | |
15518 | "TARGET_64BIT" | |
8554d9a4 | 15519 | "{rep\;stosb|rep stosb}" |
e2e52e1b | 15520 | [(set_attr "type" "str") |
6ef67412 JH |
15521 | (set_attr "prefix_rep" "1") |
15522 | (set_attr "memory" "store") | |
15523 | (set_attr "mode" "QI")]) | |
0ae40045 | 15524 | |
886c62d1 | 15525 | (define_expand "cmpstrsi" |
e075ae69 RH |
15526 | [(set (match_operand:SI 0 "register_operand" "") |
15527 | (compare:SI (match_operand:BLK 1 "general_operand" "") | |
15528 | (match_operand:BLK 2 "general_operand" ""))) | |
0945b39d JH |
15529 | (use (match_operand 3 "general_operand" "")) |
15530 | (use (match_operand 4 "immediate_operand" ""))] | |
886c62d1 | 15531 | "" |
886c62d1 | 15532 | { |
e075ae69 RH |
15533 | rtx addr1, addr2, out, outlow, count, countreg, align; |
15534 | ||
15535 | out = operands[0]; | |
15536 | if (GET_CODE (out) != REG) | |
15537 | out = gen_reg_rtx (SImode); | |
783cdf65 JVA |
15538 | |
15539 | addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); | |
15540 | addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); | |
e075ae69 RH |
15541 | |
15542 | count = operands[3]; | |
d24b3457 | 15543 | countreg = ix86_zero_extend_to_Pmode (count); |
e075ae69 RH |
15544 | |
15545 | /* %%% Iff we are testing strict equality, we can use known alignment | |
15546 | to good advantage. This may be possible with combine, particularly | |
15547 | once cc0 is dead. */ | |
15548 | align = operands[4]; | |
783cdf65 | 15549 | |
7c7ef435 | 15550 | emit_insn (gen_cld ()); |
e075ae69 RH |
15551 | if (GET_CODE (count) == CONST_INT) |
15552 | { | |
15553 | if (INTVAL (count) == 0) | |
15554 | { | |
15555 | emit_move_insn (operands[0], const0_rtx); | |
15556 | DONE; | |
15557 | } | |
0945b39d JH |
15558 | if (TARGET_64BIT) |
15559 | emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align, | |
15560 | addr1, addr2, countreg)); | |
15561 | else | |
15562 | emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align, | |
15563 | addr1, addr2, countreg)); | |
e075ae69 RH |
15564 | } |
15565 | else | |
e2e52e1b | 15566 | { |
0945b39d JH |
15567 | if (TARGET_64BIT) |
15568 | { | |
15569 | emit_insn (gen_cmpdi_1_rex64 (countreg, countreg)); | |
15570 | emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align, | |
15571 | addr1, addr2, countreg)); | |
15572 | } | |
15573 | else | |
15574 | { | |
15575 | emit_insn (gen_cmpsi_1 (countreg, countreg)); | |
15576 | emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align, | |
15577 | addr1, addr2, countreg)); | |
15578 | } | |
e2e52e1b | 15579 | } |
e075ae69 RH |
15580 | |
15581 | outlow = gen_lowpart (QImode, out); | |
15582 | emit_insn (gen_cmpintqi (outlow)); | |
15583 | emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow)); | |
783cdf65 | 15584 | |
e075ae69 RH |
15585 | if (operands[0] != out) |
15586 | emit_move_insn (operands[0], out); | |
783cdf65 | 15587 | |
e075ae69 | 15588 | DONE; |
0f40f9f7 | 15589 | }) |
886c62d1 | 15590 | |
e075ae69 RH |
15591 | ;; Produce a tri-state integer (-1, 0, 1) from condition codes. |
15592 | ||
15593 | (define_expand "cmpintqi" | |
15594 | [(set (match_dup 1) | |
15595 | (gtu:QI (reg:CC 17) (const_int 0))) | |
15596 | (set (match_dup 2) | |
15597 | (ltu:QI (reg:CC 17) (const_int 0))) | |
15598 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
15599 | (minus:QI (match_dup 1) | |
15600 | (match_dup 2))) | |
15601 | (clobber (reg:CC 17))])] | |
15602 | "" | |
15603 | "operands[1] = gen_reg_rtx (QImode); | |
15604 | operands[2] = gen_reg_rtx (QImode);") | |
15605 | ||
f76e3b05 JVA |
15606 | ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is |
15607 | ;; zero. Emit extra code to make sure that a zero-length compare is EQ. | |
56c0e8fa | 15608 | |
0945b39d | 15609 | (define_insn "cmpstrqi_nz_1" |
e075ae69 | 15610 | [(set (reg:CC 17) |
b1cdafbb JH |
15611 | (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0")) |
15612 | (mem:BLK (match_operand:SI 5 "register_operand" "1")))) | |
15613 | (use (match_operand:SI 6 "register_operand" "2")) | |
886c62d1 | 15614 | (use (match_operand:SI 3 "immediate_operand" "i")) |
7c7ef435 | 15615 | (use (reg:SI 19)) |
b1cdafbb JH |
15616 | (clobber (match_operand:SI 0 "register_operand" "=S")) |
15617 | (clobber (match_operand:SI 1 "register_operand" "=D")) | |
15618 | (clobber (match_operand:SI 2 "register_operand" "=c"))] | |
0945b39d JH |
15619 | "!TARGET_64BIT" |
15620 | "repz{\;| }cmpsb" | |
15621 | [(set_attr "type" "str") | |
15622 | (set_attr "mode" "QI") | |
15623 | (set_attr "prefix_rep" "1")]) | |
15624 | ||
15625 | (define_insn "cmpstrqi_nz_rex_1" | |
15626 | [(set (reg:CC 17) | |
15627 | (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0")) | |
15628 | (mem:BLK (match_operand:DI 5 "register_operand" "1")))) | |
15629 | (use (match_operand:DI 6 "register_operand" "2")) | |
15630 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
15631 | (use (reg:SI 19)) | |
15632 | (clobber (match_operand:DI 0 "register_operand" "=S")) | |
15633 | (clobber (match_operand:DI 1 "register_operand" "=D")) | |
15634 | (clobber (match_operand:DI 2 "register_operand" "=c"))] | |
15635 | "TARGET_64BIT" | |
7c7ef435 | 15636 | "repz{\;| }cmpsb" |
e2e52e1b | 15637 | [(set_attr "type" "str") |
6ef67412 JH |
15638 | (set_attr "mode" "QI") |
15639 | (set_attr "prefix_rep" "1")]) | |
886c62d1 | 15640 | |
e075ae69 | 15641 | ;; The same, but the count is not known to not be zero. |
886c62d1 | 15642 | |
0945b39d | 15643 | (define_insn "cmpstrqi_1" |
e075ae69 | 15644 | [(set (reg:CC 17) |
b1cdafbb | 15645 | (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2") |
e075ae69 | 15646 | (const_int 0)) |
2bed3391 | 15647 | (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0")) |
b1cdafbb | 15648 | (mem:BLK (match_operand:SI 5 "register_operand" "1"))) |
e075ae69 RH |
15649 | (const_int 0))) |
15650 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
e2e52e1b | 15651 | (use (reg:CC 17)) |
7c7ef435 | 15652 | (use (reg:SI 19)) |
b1cdafbb JH |
15653 | (clobber (match_operand:SI 0 "register_operand" "=S")) |
15654 | (clobber (match_operand:SI 1 "register_operand" "=D")) | |
15655 | (clobber (match_operand:SI 2 "register_operand" "=c"))] | |
0945b39d JH |
15656 | "!TARGET_64BIT" |
15657 | "repz{\;| }cmpsb" | |
15658 | [(set_attr "type" "str") | |
15659 | (set_attr "mode" "QI") | |
15660 | (set_attr "prefix_rep" "1")]) | |
15661 | ||
15662 | (define_insn "cmpstrqi_rex_1" | |
15663 | [(set (reg:CC 17) | |
15664 | (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2") | |
15665 | (const_int 0)) | |
15666 | (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0")) | |
15667 | (mem:BLK (match_operand:DI 5 "register_operand" "1"))) | |
15668 | (const_int 0))) | |
15669 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
15670 | (use (reg:CC 17)) | |
15671 | (use (reg:SI 19)) | |
15672 | (clobber (match_operand:DI 0 "register_operand" "=S")) | |
15673 | (clobber (match_operand:DI 1 "register_operand" "=D")) | |
15674 | (clobber (match_operand:DI 2 "register_operand" "=c"))] | |
15675 | "TARGET_64BIT" | |
e2e52e1b JH |
15676 | "repz{\;| }cmpsb" |
15677 | [(set_attr "type" "str") | |
6ef67412 JH |
15678 | (set_attr "mode" "QI") |
15679 | (set_attr "prefix_rep" "1")]) | |
886c62d1 | 15680 | |
e075ae69 RH |
15681 | (define_expand "strlensi" |
15682 | [(set (match_operand:SI 0 "register_operand" "") | |
15683 | (unspec:SI [(match_operand:BLK 1 "general_operand" "") | |
15684 | (match_operand:QI 2 "immediate_operand" "") | |
8ee41eaf | 15685 | (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))] |
886c62d1 | 15686 | "" |
886c62d1 | 15687 | { |
0945b39d JH |
15688 | if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3])) |
15689 | DONE; | |
15690 | else | |
15691 | FAIL; | |
0f40f9f7 | 15692 | }) |
e075ae69 | 15693 | |
0945b39d JH |
15694 | (define_expand "strlendi" |
15695 | [(set (match_operand:DI 0 "register_operand" "") | |
15696 | (unspec:DI [(match_operand:BLK 1 "general_operand" "") | |
15697 | (match_operand:QI 2 "immediate_operand" "") | |
8ee41eaf | 15698 | (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))] |
0945b39d | 15699 | "" |
0945b39d JH |
15700 | { |
15701 | if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3])) | |
15702 | DONE; | |
15703 | else | |
15704 | FAIL; | |
0f40f9f7 | 15705 | }) |
19c3fc24 | 15706 | |
0945b39d | 15707 | (define_insn "strlenqi_1" |
e075ae69 | 15708 | [(set (match_operand:SI 0 "register_operand" "=&c") |
b1cdafbb | 15709 | (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1")) |
0945b39d | 15710 | (match_operand:QI 2 "register_operand" "a") |
e075ae69 | 15711 | (match_operand:SI 3 "immediate_operand" "i") |
8ee41eaf | 15712 | (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS)) |
7c7ef435 | 15713 | (use (reg:SI 19)) |
b1cdafbb | 15714 | (clobber (match_operand:SI 1 "register_operand" "=D")) |
e075ae69 | 15715 | (clobber (reg:CC 17))] |
0945b39d JH |
15716 | "!TARGET_64BIT" |
15717 | "repnz{\;| }scasb" | |
15718 | [(set_attr "type" "str") | |
15719 | (set_attr "mode" "QI") | |
15720 | (set_attr "prefix_rep" "1")]) | |
15721 | ||
15722 | (define_insn "strlenqi_rex_1" | |
15723 | [(set (match_operand:DI 0 "register_operand" "=&c") | |
15724 | (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1")) | |
15725 | (match_operand:QI 2 "register_operand" "a") | |
15726 | (match_operand:DI 3 "immediate_operand" "i") | |
8ee41eaf | 15727 | (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS)) |
0945b39d JH |
15728 | (use (reg:SI 19)) |
15729 | (clobber (match_operand:DI 1 "register_operand" "=D")) | |
15730 | (clobber (reg:CC 17))] | |
15731 | "TARGET_64BIT" | |
7c7ef435 | 15732 | "repnz{\;| }scasb" |
e2e52e1b | 15733 | [(set_attr "type" "str") |
6ef67412 JH |
15734 | (set_attr "mode" "QI") |
15735 | (set_attr "prefix_rep" "1")]) | |
a3e991f2 ZW |
15736 | |
15737 | ;; Peephole optimizations to clean up after cmpstr*. This should be | |
15738 | ;; handled in combine, but it is not currently up to the task. | |
15739 | ;; When used for their truth value, the cmpstr* expanders generate | |
15740 | ;; code like this: | |
15741 | ;; | |
15742 | ;; repz cmpsb | |
15743 | ;; seta %al | |
15744 | ;; setb %dl | |
15745 | ;; cmpb %al, %dl | |
15746 | ;; jcc label | |
15747 | ;; | |
15748 | ;; The intermediate three instructions are unnecessary. | |
15749 | ||
15750 | ;; This one handles cmpstr*_nz_1... | |
15751 | (define_peephole2 | |
15752 | [(parallel[ | |
15753 | (set (reg:CC 17) | |
15754 | (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) | |
15755 | (mem:BLK (match_operand 5 "register_operand" "")))) | |
15756 | (use (match_operand 6 "register_operand" "")) | |
15757 | (use (match_operand:SI 3 "immediate_operand" "")) | |
15758 | (use (reg:SI 19)) | |
15759 | (clobber (match_operand 0 "register_operand" "")) | |
15760 | (clobber (match_operand 1 "register_operand" "")) | |
15761 | (clobber (match_operand 2 "register_operand" ""))]) | |
15762 | (set (match_operand:QI 7 "register_operand" "") | |
15763 | (gtu:QI (reg:CC 17) (const_int 0))) | |
15764 | (set (match_operand:QI 8 "register_operand" "") | |
15765 | (ltu:QI (reg:CC 17) (const_int 0))) | |
15766 | (set (reg 17) | |
15767 | (compare (match_dup 7) (match_dup 8))) | |
15768 | ] | |
244ec848 | 15769 | "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])" |
a3e991f2 ZW |
15770 | [(parallel[ |
15771 | (set (reg:CC 17) | |
15772 | (compare:CC (mem:BLK (match_dup 4)) | |
15773 | (mem:BLK (match_dup 5)))) | |
15774 | (use (match_dup 6)) | |
15775 | (use (match_dup 3)) | |
15776 | (use (reg:SI 19)) | |
15777 | (clobber (match_dup 0)) | |
15778 | (clobber (match_dup 1)) | |
244ec848 | 15779 | (clobber (match_dup 2))])] |
a3e991f2 ZW |
15780 | "") |
15781 | ||
15782 | ;; ...and this one handles cmpstr*_1. | |
15783 | (define_peephole2 | |
15784 | [(parallel[ | |
15785 | (set (reg:CC 17) | |
15786 | (if_then_else:CC (ne (match_operand 6 "register_operand" "") | |
15787 | (const_int 0)) | |
15788 | (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) | |
15789 | (mem:BLK (match_operand 5 "register_operand" ""))) | |
15790 | (const_int 0))) | |
15791 | (use (match_operand:SI 3 "immediate_operand" "")) | |
15792 | (use (reg:CC 17)) | |
15793 | (use (reg:SI 19)) | |
15794 | (clobber (match_operand 0 "register_operand" "")) | |
15795 | (clobber (match_operand 1 "register_operand" "")) | |
15796 | (clobber (match_operand 2 "register_operand" ""))]) | |
15797 | (set (match_operand:QI 7 "register_operand" "") | |
15798 | (gtu:QI (reg:CC 17) (const_int 0))) | |
15799 | (set (match_operand:QI 8 "register_operand" "") | |
15800 | (ltu:QI (reg:CC 17) (const_int 0))) | |
15801 | (set (reg 17) | |
15802 | (compare (match_dup 7) (match_dup 8))) | |
15803 | ] | |
244ec848 | 15804 | "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])" |
a3e991f2 ZW |
15805 | [(parallel[ |
15806 | (set (reg:CC 17) | |
15807 | (if_then_else:CC (ne (match_dup 6) | |
15808 | (const_int 0)) | |
15809 | (compare:CC (mem:BLK (match_dup 4)) | |
15810 | (mem:BLK (match_dup 5))) | |
15811 | (const_int 0))) | |
15812 | (use (match_dup 3)) | |
15813 | (use (reg:CC 17)) | |
15814 | (use (reg:SI 19)) | |
15815 | (clobber (match_dup 0)) | |
15816 | (clobber (match_dup 1)) | |
244ec848 | 15817 | (clobber (match_dup 2))])] |
a3e991f2 ZW |
15818 | "") |
15819 | ||
15820 | ||
e075ae69 RH |
15821 | \f |
15822 | ;; Conditional move instructions. | |
726e2d54 | 15823 | |
44cf5b6a | 15824 | (define_expand "movdicc" |
885a70fd JH |
15825 | [(set (match_operand:DI 0 "register_operand" "") |
15826 | (if_then_else:DI (match_operand 1 "comparison_operator" "") | |
44cf5b6a JH |
15827 | (match_operand:DI 2 "general_operand" "") |
15828 | (match_operand:DI 3 "general_operand" "")))] | |
885a70fd JH |
15829 | "TARGET_64BIT" |
15830 | "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;") | |
15831 | ||
e74061a9 | 15832 | (define_insn "x86_movdicc_0_m1_rex64" |
885a70fd JH |
15833 | [(set (match_operand:DI 0 "register_operand" "=r") |
15834 | (if_then_else:DI (ltu (reg:CC 17) (const_int 0)) | |
15835 | (const_int -1) | |
15836 | (const_int 0))) | |
15837 | (clobber (reg:CC 17))] | |
15838 | "TARGET_64BIT" | |
0f40f9f7 | 15839 | "sbb{q}\t%0, %0" |
885a70fd JH |
15840 | ; Since we don't have the proper number of operands for an alu insn, |
15841 | ; fill in all the blanks. | |
15842 | [(set_attr "type" "alu") | |
890d52e8 | 15843 | (set_attr "pent_pair" "pu") |
885a70fd JH |
15844 | (set_attr "memory" "none") |
15845 | (set_attr "imm_disp" "false") | |
15846 | (set_attr "mode" "DI") | |
15847 | (set_attr "length_immediate" "0")]) | |
15848 | ||
15849 | (define_insn "*movdicc_c_rex64" | |
15850 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
15851 | (if_then_else:DI (match_operator 1 "ix86_comparison_operator" | |
15852 | [(reg 17) (const_int 0)]) | |
15853 | (match_operand:DI 2 "nonimmediate_operand" "rm,0") | |
15854 | (match_operand:DI 3 "nonimmediate_operand" "0,rm")))] | |
15855 | "TARGET_64BIT && TARGET_CMOVE | |
15856 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
15857 | "@ | |
048b1c95 JJ |
15858 | cmov%O2%C1\t{%2, %0|%0, %2} |
15859 | cmov%O2%c1\t{%3, %0|%0, %3}" | |
885a70fd JH |
15860 | [(set_attr "type" "icmov") |
15861 | (set_attr "mode" "DI")]) | |
15862 | ||
e075ae69 | 15863 | (define_expand "movsicc" |
6a4a5d95 | 15864 | [(set (match_operand:SI 0 "register_operand" "") |
e075ae69 RH |
15865 | (if_then_else:SI (match_operand 1 "comparison_operator" "") |
15866 | (match_operand:SI 2 "general_operand" "") | |
15867 | (match_operand:SI 3 "general_operand" "")))] | |
15868 | "" | |
15869 | "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;") | |
726e2d54 | 15870 | |
e075ae69 RH |
15871 | ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing |
15872 | ;; the register first winds up with `sbbl $0,reg', which is also weird. | |
15873 | ;; So just document what we're doing explicitly. | |
15874 | ||
15875 | (define_insn "x86_movsicc_0_m1" | |
15876 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15877 | (if_then_else:SI (ltu (reg:CC 17) (const_int 0)) | |
15878 | (const_int -1) | |
15879 | (const_int 0))) | |
15880 | (clobber (reg:CC 17))] | |
15881 | "" | |
0f40f9f7 | 15882 | "sbb{l}\t%0, %0" |
e075ae69 RH |
15883 | ; Since we don't have the proper number of operands for an alu insn, |
15884 | ; fill in all the blanks. | |
15885 | [(set_attr "type" "alu") | |
890d52e8 | 15886 | (set_attr "pent_pair" "pu") |
e075ae69 RH |
15887 | (set_attr "memory" "none") |
15888 | (set_attr "imm_disp" "false") | |
6ef67412 JH |
15889 | (set_attr "mode" "SI") |
15890 | (set_attr "length_immediate" "0")]) | |
e075ae69 | 15891 | |
6343a50e | 15892 | (define_insn "*movsicc_noc" |
e075ae69 | 15893 | [(set (match_operand:SI 0 "register_operand" "=r,r") |
9076b9c1 | 15894 | (if_then_else:SI (match_operator 1 "ix86_comparison_operator" |
e075ae69 RH |
15895 | [(reg 17) (const_int 0)]) |
15896 | (match_operand:SI 2 "nonimmediate_operand" "rm,0") | |
15897 | (match_operand:SI 3 "nonimmediate_operand" "0,rm")))] | |
d525dfdf JH |
15898 | "TARGET_CMOVE |
15899 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
e075ae69 | 15900 | "@ |
048b1c95 JJ |
15901 | cmov%O2%C1\t{%2, %0|%0, %2} |
15902 | cmov%O2%c1\t{%3, %0|%0, %3}" | |
6ef67412 JH |
15903 | [(set_attr "type" "icmov") |
15904 | (set_attr "mode" "SI")]) | |
726e2d54 | 15905 | |
726e2d54 JW |
15906 | (define_expand "movhicc" |
15907 | [(set (match_operand:HI 0 "register_operand" "") | |
15908 | (if_then_else:HI (match_operand 1 "comparison_operator" "") | |
15909 | (match_operand:HI 2 "nonimmediate_operand" "") | |
15910 | (match_operand:HI 3 "nonimmediate_operand" "")))] | |
d9f32422 | 15911 | "TARGET_CMOVE && TARGET_HIMODE_MATH" |
e075ae69 | 15912 | "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;") |
726e2d54 | 15913 | |
6343a50e | 15914 | (define_insn "*movhicc_noc" |
e075ae69 | 15915 | [(set (match_operand:HI 0 "register_operand" "=r,r") |
9076b9c1 | 15916 | (if_then_else:HI (match_operator 1 "ix86_comparison_operator" |
e075ae69 RH |
15917 | [(reg 17) (const_int 0)]) |
15918 | (match_operand:HI 2 "nonimmediate_operand" "rm,0") | |
15919 | (match_operand:HI 3 "nonimmediate_operand" "0,rm")))] | |
d525dfdf JH |
15920 | "TARGET_CMOVE |
15921 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
e075ae69 | 15922 | "@ |
048b1c95 JJ |
15923 | cmov%O2%C1\t{%2, %0|%0, %2} |
15924 | cmov%O2%c1\t{%3, %0|%0, %3}" | |
6ef67412 JH |
15925 | [(set_attr "type" "icmov") |
15926 | (set_attr "mode" "HI")]) | |
726e2d54 | 15927 | |
56710e42 | 15928 | (define_expand "movsfcc" |
726e2d54 | 15929 | [(set (match_operand:SF 0 "register_operand" "") |
56710e42 | 15930 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
e5e809f4 JL |
15931 | (match_operand:SF 2 "register_operand" "") |
15932 | (match_operand:SF 3 "register_operand" "")))] | |
726e2d54 | 15933 | "TARGET_CMOVE" |
e075ae69 | 15934 | "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") |
726e2d54 | 15935 | |
6343a50e | 15936 | (define_insn "*movsfcc_1" |
7093c9ea | 15937 | [(set (match_operand:SF 0 "register_operand" "=f,f,r,r") |
e075ae69 RH |
15938 | (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" |
15939 | [(reg 17) (const_int 0)]) | |
7093c9ea JH |
15940 | (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0") |
15941 | (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))] | |
15942 | "TARGET_CMOVE | |
15943 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
e075ae69 | 15944 | "@ |
0f40f9f7 ZW |
15945 | fcmov%F1\t{%2, %0|%0, %2} |
15946 | fcmov%f1\t{%3, %0|%0, %3} | |
048b1c95 JJ |
15947 | cmov%O2%C1\t{%2, %0|%0, %2} |
15948 | cmov%O2%c1\t{%3, %0|%0, %3}" | |
7093c9ea JH |
15949 | [(set_attr "type" "fcmov,fcmov,icmov,icmov") |
15950 | (set_attr "mode" "SF,SF,SI,SI")]) | |
56710e42 SC |
15951 | |
15952 | (define_expand "movdfcc" | |
726e2d54 | 15953 | [(set (match_operand:DF 0 "register_operand" "") |
56710e42 | 15954 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
e5e809f4 JL |
15955 | (match_operand:DF 2 "register_operand" "") |
15956 | (match_operand:DF 3 "register_operand" "")))] | |
726e2d54 | 15957 | "TARGET_CMOVE" |
e075ae69 | 15958 | "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") |
726e2d54 | 15959 | |
6343a50e | 15960 | (define_insn "*movdfcc_1" |
7093c9ea | 15961 | [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r") |
e075ae69 RH |
15962 | (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" |
15963 | [(reg 17) (const_int 0)]) | |
7093c9ea JH |
15964 | (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0") |
15965 | (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))] | |
1b0c37d7 | 15966 | "!TARGET_64BIT && TARGET_CMOVE |
7093c9ea | 15967 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" |
e075ae69 | 15968 | "@ |
0f40f9f7 ZW |
15969 | fcmov%F1\t{%2, %0|%0, %2} |
15970 | fcmov%f1\t{%3, %0|%0, %3} | |
7093c9ea JH |
15971 | # |
15972 | #" | |
15973 | [(set_attr "type" "fcmov,fcmov,multi,multi") | |
6ef67412 | 15974 | (set_attr "mode" "DF")]) |
56710e42 | 15975 | |
1e07edd3 JH |
15976 | (define_insn "*movdfcc_1_rex64" |
15977 | [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r") | |
15978 | (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" | |
15979 | [(reg 17) (const_int 0)]) | |
15980 | (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0") | |
15981 | (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))] | |
1b0c37d7 | 15982 | "TARGET_64BIT && TARGET_CMOVE |
1e07edd3 JH |
15983 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" |
15984 | "@ | |
0f40f9f7 ZW |
15985 | fcmov%F1\t{%2, %0|%0, %2} |
15986 | fcmov%f1\t{%3, %0|%0, %3} | |
048b1c95 JJ |
15987 | cmov%O2%C1\t{%2, %0|%0, %2} |
15988 | cmov%O2%c1\t{%3, %0|%0, %3}" | |
1e07edd3 JH |
15989 | [(set_attr "type" "fcmov,fcmov,icmov,icmov") |
15990 | (set_attr "mode" "DF")]) | |
15991 | ||
7093c9ea | 15992 | (define_split |
c3c637e3 | 15993 | [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "") |
7093c9ea JH |
15994 | (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" |
15995 | [(match_operand 4 "" "") (const_int 0)]) | |
15996 | (match_operand:DF 2 "nonimmediate_operand" "") | |
15997 | (match_operand:DF 3 "nonimmediate_operand" "")))] | |
c3c637e3 | 15998 | "!TARGET_64BIT && reload_completed" |
7093c9ea JH |
15999 | [(set (match_dup 2) |
16000 | (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)]) | |
16001 | (match_dup 5) | |
16002 | (match_dup 7))) | |
16003 | (set (match_dup 3) | |
16004 | (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)]) | |
16005 | (match_dup 6) | |
16006 | (match_dup 8)))] | |
16007 | "split_di (operands+2, 1, operands+5, operands+6); | |
16008 | split_di (operands+3, 1, operands+7, operands+8); | |
16009 | split_di (operands, 1, operands+2, operands+3);") | |
16010 | ||
56710e42 | 16011 | (define_expand "movxfcc" |
726e2d54 | 16012 | [(set (match_operand:XF 0 "register_operand" "") |
56710e42 | 16013 | (if_then_else:XF (match_operand 1 "comparison_operator" "") |
e5e809f4 JL |
16014 | (match_operand:XF 2 "register_operand" "") |
16015 | (match_operand:XF 3 "register_operand" "")))] | |
1b0c37d7 | 16016 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 | 16017 | "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") |
726e2d54 | 16018 | |
2b589241 JH |
16019 | (define_expand "movtfcc" |
16020 | [(set (match_operand:TF 0 "register_operand" "") | |
16021 | (if_then_else:TF (match_operand 1 "comparison_operator" "") | |
16022 | (match_operand:TF 2 "register_operand" "") | |
16023 | (match_operand:TF 3 "register_operand" "")))] | |
16024 | "TARGET_CMOVE" | |
16025 | "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") | |
16026 | ||
6343a50e | 16027 | (define_insn "*movxfcc_1" |
3aeae608 | 16028 | [(set (match_operand:XF 0 "register_operand" "=f,f") |
e075ae69 RH |
16029 | (if_then_else:XF (match_operator 1 "fcmov_comparison_operator" |
16030 | [(reg 17) (const_int 0)]) | |
3aeae608 JW |
16031 | (match_operand:XF 2 "register_operand" "f,0") |
16032 | (match_operand:XF 3 "register_operand" "0,f")))] | |
1b0c37d7 | 16033 | "!TARGET_64BIT && TARGET_CMOVE" |
e075ae69 | 16034 | "@ |
0f40f9f7 ZW |
16035 | fcmov%F1\t{%2, %0|%0, %2} |
16036 | fcmov%f1\t{%3, %0|%0, %3}" | |
6ef67412 JH |
16037 | [(set_attr "type" "fcmov") |
16038 | (set_attr "mode" "XF")]) | |
2b589241 JH |
16039 | |
16040 | (define_insn "*movtfcc_1" | |
16041 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
16042 | (if_then_else:TF (match_operator 1 "fcmov_comparison_operator" | |
16043 | [(reg 17) (const_int 0)]) | |
16044 | (match_operand:TF 2 "register_operand" "f,0") | |
16045 | (match_operand:TF 3 "register_operand" "0,f")))] | |
16046 | "TARGET_CMOVE" | |
16047 | "@ | |
0f40f9f7 ZW |
16048 | fcmov%F1\t{%2, %0|%0, %2} |
16049 | fcmov%f1\t{%3, %0|%0, %3}" | |
2b589241 JH |
16050 | [(set_attr "type" "fcmov") |
16051 | (set_attr "mode" "XF")]) | |
7ada6625 JH |
16052 | |
16053 | (define_expand "minsf3" | |
16054 | [(parallel [ | |
16055 | (set (match_operand:SF 0 "register_operand" "") | |
16056 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") | |
16057 | (match_operand:SF 2 "nonimmediate_operand" "")) | |
16058 | (match_dup 1) | |
16059 | (match_dup 2))) | |
16060 | (clobber (reg:CC 17))])] | |
16061 | "TARGET_SSE" | |
16062 | "") | |
16063 | ||
16064 | (define_insn "*minsf" | |
16065 | [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x") | |
16066 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x") | |
16067 | (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0")) | |
16068 | (match_dup 1) | |
16069 | (match_dup 2))) | |
16070 | (clobber (reg:CC 17))] | |
16071 | "TARGET_SSE && TARGET_IEEE_FP" | |
16072 | "#") | |
16073 | ||
16074 | (define_insn "*minsf_nonieee" | |
16075 | [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") | |
558740bf | 16076 | (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
3987b9db | 16077 | (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) |
7ada6625 JH |
16078 | (match_dup 1) |
16079 | (match_dup 2))) | |
16080 | (clobber (reg:CC 17))] | |
558740bf JH |
16081 | "TARGET_SSE && !TARGET_IEEE_FP |
16082 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
7ada6625 JH |
16083 | "#") |
16084 | ||
16085 | (define_split | |
16086 | [(set (match_operand:SF 0 "register_operand" "") | |
16087 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") | |
16088 | (match_operand:SF 2 "nonimmediate_operand" "")) | |
138b7342 JH |
16089 | (match_operand:SF 3 "register_operand" "") |
16090 | (match_operand:SF 4 "nonimmediate_operand" ""))) | |
ef6257cd JH |
16091 | (clobber (reg:CC 17))] |
16092 | "SSE_REG_P (operands[0]) && reload_completed | |
16093 | && ((operands_match_p (operands[1], operands[3]) | |
16094 | && operands_match_p (operands[2], operands[4])) | |
16095 | || (operands_match_p (operands[1], operands[4]) | |
16096 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16097 | [(set (match_dup 0) |
16098 | (if_then_else:SF (lt (match_dup 1) | |
16099 | (match_dup 2)) | |
16100 | (match_dup 1) | |
16101 | (match_dup 2)))]) | |
16102 | ||
16103 | ;; We can't represent the LT test directly. Do this by swapping the operands. | |
ef6257cd | 16104 | |
7ada6625 | 16105 | (define_split |
c3c637e3 | 16106 | [(set (match_operand:SF 0 "fp_register_operand" "") |
7ada6625 JH |
16107 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "") |
16108 | (match_operand:SF 2 "register_operand" "")) | |
14d920c0 JH |
16109 | (match_operand:SF 3 "register_operand" "") |
16110 | (match_operand:SF 4 "register_operand" ""))) | |
ef6257cd | 16111 | (clobber (reg:CC 17))] |
c3c637e3 | 16112 | "reload_completed |
ef6257cd JH |
16113 | && ((operands_match_p (operands[1], operands[3]) |
16114 | && operands_match_p (operands[2], operands[4])) | |
16115 | || (operands_match_p (operands[1], operands[4]) | |
16116 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16117 | [(set (reg:CCFP 17) |
16118 | (compare:CCFP (match_dup 2) | |
16119 | (match_dup 1))) | |
16120 | (set (match_dup 0) | |
16121 | (if_then_else:SF (ge (reg:CCFP 17) (const_int 0)) | |
16122 | (match_dup 1) | |
16123 | (match_dup 2)))]) | |
16124 | ||
16125 | (define_insn "*minsf_sse" | |
16126 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16127 | (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0") | |
16128 | (match_operand:SF 2 "nonimmediate_operand" "xm")) | |
16129 | (match_dup 1) | |
16130 | (match_dup 2)))] | |
16131 | "TARGET_SSE && reload_completed" | |
0f40f9f7 | 16132 | "minss\t{%2, %0|%0, %2}" |
7ada6625 JH |
16133 | [(set_attr "type" "sse") |
16134 | (set_attr "mode" "SF")]) | |
16135 | ||
16136 | (define_expand "mindf3" | |
16137 | [(parallel [ | |
16138 | (set (match_operand:DF 0 "register_operand" "") | |
16139 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") | |
16140 | (match_operand:DF 2 "nonimmediate_operand" "")) | |
16141 | (match_dup 1) | |
16142 | (match_dup 2))) | |
16143 | (clobber (reg:CC 17))])] | |
965f5423 | 16144 | "TARGET_SSE2 && TARGET_SSE_MATH" |
7ada6625 JH |
16145 | "#") |
16146 | ||
16147 | (define_insn "*mindf" | |
16148 | [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y") | |
16149 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y") | |
16150 | (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0")) | |
16151 | (match_dup 1) | |
16152 | (match_dup 2))) | |
16153 | (clobber (reg:CC 17))] | |
965f5423 | 16154 | "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH" |
7ada6625 JH |
16155 | "#") |
16156 | ||
16157 | (define_insn "*mindf_nonieee" | |
16158 | [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") | |
558740bf | 16159 | (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
3987b9db | 16160 | (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) |
7ada6625 JH |
16161 | (match_dup 1) |
16162 | (match_dup 2))) | |
16163 | (clobber (reg:CC 17))] | |
558740bf JH |
16164 | "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP |
16165 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
7ada6625 JH |
16166 | "#") |
16167 | ||
16168 | (define_split | |
16169 | [(set (match_operand:DF 0 "register_operand" "") | |
16170 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") | |
16171 | (match_operand:DF 2 "nonimmediate_operand" "")) | |
ef6257cd JH |
16172 | (match_operand:DF 3 "register_operand" "") |
16173 | (match_operand:DF 4 "nonimmediate_operand" ""))) | |
16174 | (clobber (reg:CC 17))] | |
16175 | "SSE_REG_P (operands[0]) && reload_completed | |
16176 | && ((operands_match_p (operands[1], operands[3]) | |
16177 | && operands_match_p (operands[2], operands[4])) | |
16178 | || (operands_match_p (operands[1], operands[4]) | |
16179 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16180 | [(set (match_dup 0) |
16181 | (if_then_else:DF (lt (match_dup 1) | |
16182 | (match_dup 2)) | |
16183 | (match_dup 1) | |
16184 | (match_dup 2)))]) | |
16185 | ||
16186 | ;; We can't represent the LT test directly. Do this by swapping the operands. | |
16187 | (define_split | |
c3c637e3 | 16188 | [(set (match_operand:DF 0 "fp_register_operand" "") |
7ada6625 JH |
16189 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "") |
16190 | (match_operand:DF 2 "register_operand" "")) | |
ef6257cd JH |
16191 | (match_operand:DF 3 "register_operand" "") |
16192 | (match_operand:DF 4 "register_operand" ""))) | |
16193 | (clobber (reg:CC 17))] | |
c3c637e3 | 16194 | "reload_completed |
ef6257cd JH |
16195 | && ((operands_match_p (operands[1], operands[3]) |
16196 | && operands_match_p (operands[2], operands[4])) | |
16197 | || (operands_match_p (operands[1], operands[4]) | |
16198 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16199 | [(set (reg:CCFP 17) |
16200 | (compare:CCFP (match_dup 2) | |
16201 | (match_dup 2))) | |
16202 | (set (match_dup 0) | |
16203 | (if_then_else:DF (ge (reg:CCFP 17) (const_int 0)) | |
16204 | (match_dup 1) | |
16205 | (match_dup 2)))]) | |
16206 | ||
16207 | (define_insn "*mindf_sse" | |
16208 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
16209 | (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0") | |
16210 | (match_operand:DF 2 "nonimmediate_operand" "Ym")) | |
16211 | (match_dup 1) | |
16212 | (match_dup 2)))] | |
965f5423 | 16213 | "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed" |
0f40f9f7 | 16214 | "minsd\t{%2, %0|%0, %2}" |
7ada6625 JH |
16215 | [(set_attr "type" "sse") |
16216 | (set_attr "mode" "DF")]) | |
16217 | ||
16218 | (define_expand "maxsf3" | |
16219 | [(parallel [ | |
16220 | (set (match_operand:SF 0 "register_operand" "") | |
16221 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") | |
16222 | (match_operand:SF 2 "nonimmediate_operand" "")) | |
16223 | (match_dup 1) | |
16224 | (match_dup 2))) | |
16225 | (clobber (reg:CC 17))])] | |
16226 | "TARGET_SSE" | |
16227 | "#") | |
16228 | ||
16229 | (define_insn "*maxsf" | |
16230 | [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x") | |
16231 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x") | |
3987b9db | 16232 | (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0")) |
7ada6625 JH |
16233 | (match_dup 1) |
16234 | (match_dup 2))) | |
16235 | (clobber (reg:CC 17))] | |
16236 | "TARGET_SSE && TARGET_IEEE_FP" | |
16237 | "#") | |
16238 | ||
16239 | (define_insn "*maxsf_nonieee" | |
16240 | [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") | |
558740bf | 16241 | (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
3987b9db | 16242 | (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) |
7ada6625 JH |
16243 | (match_dup 1) |
16244 | (match_dup 2))) | |
16245 | (clobber (reg:CC 17))] | |
558740bf JH |
16246 | "TARGET_SSE && !TARGET_IEEE_FP |
16247 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
7ada6625 JH |
16248 | "#") |
16249 | ||
16250 | (define_split | |
16251 | [(set (match_operand:SF 0 "register_operand" "") | |
16252 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") | |
16253 | (match_operand:SF 2 "nonimmediate_operand" "")) | |
ef6257cd JH |
16254 | (match_operand:SF 3 "register_operand" "") |
16255 | (match_operand:SF 4 "nonimmediate_operand" ""))) | |
16256 | (clobber (reg:CC 17))] | |
16257 | "SSE_REG_P (operands[0]) && reload_completed | |
16258 | && ((operands_match_p (operands[1], operands[3]) | |
16259 | && operands_match_p (operands[2], operands[4])) | |
16260 | || (operands_match_p (operands[1], operands[4]) | |
16261 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16262 | [(set (match_dup 0) |
16263 | (if_then_else:SF (gt (match_dup 1) | |
16264 | (match_dup 2)) | |
16265 | (match_dup 1) | |
16266 | (match_dup 2)))]) | |
16267 | ||
16268 | (define_split | |
c3c637e3 | 16269 | [(set (match_operand:SF 0 "fp_register_operand" "") |
7ada6625 JH |
16270 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "") |
16271 | (match_operand:SF 2 "register_operand" "")) | |
ef6257cd JH |
16272 | (match_operand:SF 3 "register_operand" "") |
16273 | (match_operand:SF 4 "register_operand" ""))) | |
16274 | (clobber (reg:CC 17))] | |
c3c637e3 | 16275 | "reload_completed |
ef6257cd JH |
16276 | && ((operands_match_p (operands[1], operands[3]) |
16277 | && operands_match_p (operands[2], operands[4])) | |
16278 | || (operands_match_p (operands[1], operands[4]) | |
16279 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16280 | [(set (reg:CCFP 17) |
16281 | (compare:CCFP (match_dup 1) | |
16282 | (match_dup 2))) | |
16283 | (set (match_dup 0) | |
16284 | (if_then_else:SF (gt (reg:CCFP 17) (const_int 0)) | |
16285 | (match_dup 1) | |
16286 | (match_dup 2)))]) | |
16287 | ||
16288 | (define_insn "*maxsf_sse" | |
16289 | [(set (match_operand:SF 0 "register_operand" "=x") | |
16290 | (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0") | |
16291 | (match_operand:SF 2 "nonimmediate_operand" "xm")) | |
16292 | (match_dup 1) | |
16293 | (match_dup 2)))] | |
16294 | "TARGET_SSE && reload_completed" | |
0f40f9f7 | 16295 | "maxss\t{%2, %0|%0, %2}" |
7ada6625 JH |
16296 | [(set_attr "type" "sse") |
16297 | (set_attr "mode" "SF")]) | |
16298 | ||
16299 | (define_expand "maxdf3" | |
16300 | [(parallel [ | |
16301 | (set (match_operand:DF 0 "register_operand" "") | |
16302 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") | |
16303 | (match_operand:DF 2 "nonimmediate_operand" "")) | |
16304 | (match_dup 1) | |
16305 | (match_dup 2))) | |
16306 | (clobber (reg:CC 17))])] | |
965f5423 | 16307 | "TARGET_SSE2 && TARGET_SSE_MATH" |
7ada6625 JH |
16308 | "#") |
16309 | ||
16310 | (define_insn "*maxdf" | |
16311 | [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y") | |
16312 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y") | |
3987b9db | 16313 | (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0")) |
7ada6625 JH |
16314 | (match_dup 1) |
16315 | (match_dup 2))) | |
16316 | (clobber (reg:CC 17))] | |
965f5423 | 16317 | "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP" |
7ada6625 JH |
16318 | "#") |
16319 | ||
16320 | (define_insn "*maxdf_nonieee" | |
16321 | [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") | |
558740bf | 16322 | (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
3987b9db | 16323 | (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) |
7ada6625 JH |
16324 | (match_dup 1) |
16325 | (match_dup 2))) | |
16326 | (clobber (reg:CC 17))] | |
558740bf JH |
16327 | "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP |
16328 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
7ada6625 JH |
16329 | "#") |
16330 | ||
16331 | (define_split | |
16332 | [(set (match_operand:DF 0 "register_operand" "") | |
16333 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") | |
16334 | (match_operand:DF 2 "nonimmediate_operand" "")) | |
ef6257cd JH |
16335 | (match_operand:DF 3 "register_operand" "") |
16336 | (match_operand:DF 4 "nonimmediate_operand" ""))) | |
16337 | (clobber (reg:CC 17))] | |
16338 | "SSE_REG_P (operands[0]) && reload_completed | |
16339 | && ((operands_match_p (operands[1], operands[3]) | |
16340 | && operands_match_p (operands[2], operands[4])) | |
16341 | || (operands_match_p (operands[1], operands[4]) | |
16342 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16343 | [(set (match_dup 0) |
16344 | (if_then_else:DF (gt (match_dup 1) | |
16345 | (match_dup 2)) | |
16346 | (match_dup 1) | |
16347 | (match_dup 2)))]) | |
16348 | ||
16349 | (define_split | |
c3c637e3 | 16350 | [(set (match_operand:DF 0 "fp_register_operand" "") |
7ada6625 JH |
16351 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "") |
16352 | (match_operand:DF 2 "register_operand" "")) | |
ef6257cd JH |
16353 | (match_operand:DF 3 "register_operand" "") |
16354 | (match_operand:DF 4 "register_operand" ""))) | |
16355 | (clobber (reg:CC 17))] | |
c3c637e3 | 16356 | "reload_completed |
ef6257cd JH |
16357 | && ((operands_match_p (operands[1], operands[3]) |
16358 | && operands_match_p (operands[2], operands[4])) | |
16359 | || (operands_match_p (operands[1], operands[4]) | |
16360 | && operands_match_p (operands[2], operands[3])))" | |
7ada6625 JH |
16361 | [(set (reg:CCFP 17) |
16362 | (compare:CCFP (match_dup 1) | |
16363 | (match_dup 2))) | |
16364 | (set (match_dup 0) | |
16365 | (if_then_else:DF (gt (reg:CCFP 17) (const_int 0)) | |
16366 | (match_dup 1) | |
16367 | (match_dup 2)))]) | |
16368 | ||
16369 | (define_insn "*maxdf_sse" | |
16370 | [(set (match_operand:DF 0 "register_operand" "=Y") | |
16371 | (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0") | |
16372 | (match_operand:DF 2 "nonimmediate_operand" "Ym")) | |
16373 | (match_dup 1) | |
16374 | (match_dup 2)))] | |
965f5423 | 16375 | "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed" |
0f40f9f7 | 16376 | "maxsd\t{%2, %0|%0, %2}" |
7ada6625 JH |
16377 | [(set_attr "type" "sse") |
16378 | (set_attr "mode" "DF")]) | |
e075ae69 RH |
16379 | \f |
16380 | ;; Misc patterns (?) | |
726e2d54 | 16381 | |
f5143c46 | 16382 | ;; This pattern exists to put a dependency on all ebp-based memory accesses. |
e075ae69 RH |
16383 | ;; Otherwise there will be nothing to keep |
16384 | ;; | |
16385 | ;; [(set (reg ebp) (reg esp))] | |
16386 | ;; [(set (reg esp) (plus (reg esp) (const_int -160000))) | |
16387 | ;; (clobber (eflags)] | |
16388 | ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))] | |
16389 | ;; | |
16390 | ;; in proper program order. | |
8362f420 JH |
16391 | (define_expand "pro_epilogue_adjust_stack" |
16392 | [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r") | |
16393 | (plus:SI (match_operand:SI 1 "register_operand" "0,r") | |
16394 | (match_operand:SI 2 "immediate_operand" "i,i"))) | |
f2042df3 RH |
16395 | (clobber (reg:CC 17)) |
16396 | (clobber (mem:BLK (scratch)))])] | |
8362f420 | 16397 | "" |
8362f420 JH |
16398 | { |
16399 | if (TARGET_64BIT) | |
16400 | { | |
f2042df3 RH |
16401 | emit_insn (gen_pro_epilogue_adjust_stack_rex64 |
16402 | (operands[0], operands[1], operands[2])); | |
8362f420 JH |
16403 | DONE; |
16404 | } | |
0f40f9f7 | 16405 | }) |
726e2d54 | 16406 | |
8362f420 | 16407 | (define_insn "*pro_epilogue_adjust_stack_1" |
1c71e60e JH |
16408 | [(set (match_operand:SI 0 "register_operand" "=r,r") |
16409 | (plus:SI (match_operand:SI 1 "register_operand" "0,r") | |
16410 | (match_operand:SI 2 "immediate_operand" "i,i"))) | |
f2042df3 RH |
16411 | (clobber (reg:CC 17)) |
16412 | (clobber (mem:BLK (scratch)))] | |
8362f420 | 16413 | "!TARGET_64BIT" |
e075ae69 | 16414 | { |
1c71e60e | 16415 | switch (get_attr_type (insn)) |
e075ae69 | 16416 | { |
1c71e60e | 16417 | case TYPE_IMOV: |
0f40f9f7 | 16418 | return "mov{l}\t{%1, %0|%0, %1}"; |
1c71e60e JH |
16419 | |
16420 | case TYPE_ALU: | |
16421 | if (GET_CODE (operands[2]) == CONST_INT | |
16422 | && (INTVAL (operands[2]) == 128 | |
16423 | || (INTVAL (operands[2]) < 0 | |
16424 | && INTVAL (operands[2]) != -128))) | |
16425 | { | |
16426 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 16427 | return "sub{l}\t{%2, %0|%0, %2}"; |
1c71e60e | 16428 | } |
0f40f9f7 | 16429 | return "add{l}\t{%2, %0|%0, %2}"; |
1c71e60e JH |
16430 | |
16431 | case TYPE_LEA: | |
16432 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
0f40f9f7 | 16433 | return "lea{l}\t{%a2, %0|%0, %a2}"; |
1c71e60e JH |
16434 | |
16435 | default: | |
16436 | abort (); | |
e075ae69 | 16437 | } |
0f40f9f7 | 16438 | } |
1c71e60e JH |
16439 | [(set (attr "type") |
16440 | (cond [(eq_attr "alternative" "0") | |
16441 | (const_string "alu") | |
16442 | (match_operand:SI 2 "const0_operand" "") | |
16443 | (const_string "imov") | |
16444 | ] | |
6ef67412 JH |
16445 | (const_string "lea"))) |
16446 | (set_attr "mode" "SI")]) | |
578b58f5 | 16447 | |
8362f420 JH |
16448 | (define_insn "pro_epilogue_adjust_stack_rex64" |
16449 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
16450 | (plus:DI (match_operand:DI 1 "register_operand" "0,r") | |
16451 | (match_operand:DI 2 "x86_64_immediate_operand" "e,e"))) | |
f2042df3 RH |
16452 | (clobber (reg:CC 17)) |
16453 | (clobber (mem:BLK (scratch)))] | |
8362f420 | 16454 | "TARGET_64BIT" |
8362f420 JH |
16455 | { |
16456 | switch (get_attr_type (insn)) | |
16457 | { | |
16458 | case TYPE_IMOV: | |
0f40f9f7 | 16459 | return "mov{q}\t{%1, %0|%0, %1}"; |
8362f420 JH |
16460 | |
16461 | case TYPE_ALU: | |
16462 | if (GET_CODE (operands[2]) == CONST_INT | |
16463 | && (INTVAL (operands[2]) == 128 | |
16464 | || (INTVAL (operands[2]) < 0 | |
16465 | && INTVAL (operands[2]) != -128))) | |
16466 | { | |
16467 | operands[2] = GEN_INT (-INTVAL (operands[2])); | |
0f40f9f7 | 16468 | return "sub{q}\t{%2, %0|%0, %2}"; |
8362f420 | 16469 | } |
0f40f9f7 | 16470 | return "add{q}\t{%2, %0|%0, %2}"; |
8362f420 JH |
16471 | |
16472 | case TYPE_LEA: | |
16473 | operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); | |
0f40f9f7 | 16474 | return "lea{q}\t{%a2, %0|%0, %a2}"; |
8362f420 JH |
16475 | |
16476 | default: | |
16477 | abort (); | |
16478 | } | |
0f40f9f7 | 16479 | } |
8362f420 JH |
16480 | [(set (attr "type") |
16481 | (cond [(eq_attr "alternative" "0") | |
16482 | (const_string "alu") | |
16483 | (match_operand:DI 2 "const0_operand" "") | |
16484 | (const_string "imov") | |
16485 | ] | |
16486 | (const_string "lea"))) | |
16487 | (set_attr "mode" "DI")]) | |
16488 | ||
16489 | ||
d6a7951f | 16490 | ;; Placeholder for the conditional moves. This one is split either to SSE |
0073023d JH |
16491 | ;; based moves emulation or to usual cmove sequence. Little bit unfortunate |
16492 | ;; fact is that compares supported by the cmp??ss instructions are exactly | |
16493 | ;; swapped of those supported by cmove sequence. | |
fa9f36a1 JH |
16494 | ;; The EQ/NE comparisons also needs bit care, since they are not directly |
16495 | ;; supported by i387 comparisons and we do need to emit two conditional moves | |
16496 | ;; in tandem. | |
0073023d JH |
16497 | |
16498 | (define_insn "sse_movsfcc" | |
16499 | [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf") | |
16500 | (if_then_else:SF (match_operator 1 "sse_comparison_operator" | |
44aefada JH |
16501 | [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f") |
16502 | (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")]) | |
0073023d JH |
16503 | (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx") |
16504 | (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx"))) | |
bf71a4f8 | 16505 | (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X")) |
0073023d | 16506 | (clobber (reg:CC 17))] |
fa9f36a1 JH |
16507 | "TARGET_SSE |
16508 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) | |
16509 | && (!TARGET_IEEE_FP | |
16510 | || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" | |
16511 | "#") | |
16512 | ||
16513 | (define_insn "sse_movsfcc_eq" | |
16514 | [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf") | |
44aefada JH |
16515 | (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f") |
16516 | (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f")) | |
fa9f36a1 JH |
16517 | (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx") |
16518 | (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) | |
f021d6fc | 16519 | (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X")) |
fa9f36a1 | 16520 | (clobber (reg:CC 17))] |
0073023d JH |
16521 | "TARGET_SSE |
16522 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" | |
16523 | "#") | |
16524 | ||
16525 | (define_insn "sse_movdfcc" | |
66b408f2 | 16526 | [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf") |
0073023d | 16527 | (if_then_else:DF (match_operator 1 "sse_comparison_operator" |
66b408f2 JJ |
16528 | [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f") |
16529 | (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")]) | |
16530 | (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY") | |
16531 | (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY"))) | |
bf71a4f8 | 16532 | (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X")) |
0073023d JH |
16533 | (clobber (reg:CC 17))] |
16534 | "TARGET_SSE2 | |
fa9f36a1 JH |
16535 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) |
16536 | && (!TARGET_IEEE_FP | |
16537 | || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))" | |
16538 | "#") | |
16539 | ||
16540 | (define_insn "sse_movdfcc_eq" | |
66b408f2 JJ |
16541 | [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf") |
16542 | (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f") | |
16543 | (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f")) | |
16544 | (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY") | |
16545 | (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY"))) | |
fa9f36a1 JH |
16546 | (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X")) |
16547 | (clobber (reg:CC 17))] | |
16548 | "TARGET_SSE | |
0073023d JH |
16549 | && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" |
16550 | "#") | |
16551 | ||
16552 | ;; For non-sse moves just expand the usual cmove sequence. | |
16553 | (define_split | |
16554 | [(set (match_operand 0 "register_operand" "") | |
16555 | (if_then_else (match_operator 1 "comparison_operator" | |
16556 | [(match_operand 4 "nonimmediate_operand" "") | |
44aefada | 16557 | (match_operand 5 "register_operand" "")]) |
0073023d JH |
16558 | (match_operand 2 "nonimmediate_operand" "") |
16559 | (match_operand 3 "nonimmediate_operand" ""))) | |
16560 | (clobber (match_operand 6 "" "")) | |
16561 | (clobber (reg:CC 17))] | |
16562 | "!SSE_REG_P (operands[0]) && reload_completed | |
16563 | && VALID_SSE_REG_MODE (GET_MODE (operands[0]))" | |
16564 | [(const_int 0)] | |
0073023d JH |
16565 | { |
16566 | ix86_compare_op0 = operands[5]; | |
16567 | ix86_compare_op1 = operands[4]; | |
16568 | operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])), | |
16569 | VOIDmode, operands[5], operands[4]); | |
16570 | ix86_expand_fp_movcc (operands); | |
16571 | DONE; | |
0f40f9f7 | 16572 | }) |
0073023d JH |
16573 | |
16574 | ;; Split SSE based conditional move into seqence: | |
16575 | ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison | |
16576 | ;; and op2, op0 - zero op2 if comparison was false | |
16577 | ;; nand op0, op3 - load op3 to op0 if comparison was false | |
9cd10576 | 16578 | ;; or op2, op0 - get the nonzero one into the result. |
0073023d JH |
16579 | (define_split |
16580 | [(set (match_operand 0 "register_operand" "") | |
16581 | (if_then_else (match_operator 1 "sse_comparison_operator" | |
16582 | [(match_operand 4 "register_operand" "") | |
16583 | (match_operand 5 "nonimmediate_operand" "")]) | |
16584 | (match_operand 2 "register_operand" "") | |
16585 | (match_operand 3 "register_operand" ""))) | |
bf71a4f8 | 16586 | (clobber (match_operand 6 "" "")) |
0073023d JH |
16587 | (clobber (reg:CC 17))] |
16588 | "SSE_REG_P (operands[0]) && reload_completed" | |
16589 | [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)])) | |
16590 | (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0) | |
f021d6fc JH |
16591 | (subreg:TI (match_dup 4) 0))) |
16592 | (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0)) | |
0073023d JH |
16593 | (subreg:TI (match_dup 3) 0))) |
16594 | (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0) | |
16595 | (subreg:TI (match_dup 7) 0)))] | |
0073023d | 16596 | { |
66b408f2 JJ |
16597 | /* If op2 == op3, op3 will be clobbered before it is used. |
16598 | This should be optimized out though. */ | |
16599 | if (operands_match_p (operands[2], operands[3])) | |
16600 | abort (); | |
0073023d | 16601 | PUT_MODE (operands[1], GET_MODE (operands[0])); |
f021d6fc | 16602 | if (operands_match_p (operands[0], operands[4])) |
0073023d JH |
16603 | operands[6] = operands[4], operands[7] = operands[2]; |
16604 | else | |
f021d6fc | 16605 | operands[6] = operands[2], operands[7] = operands[4]; |
0f40f9f7 | 16606 | }) |
0073023d JH |
16607 | |
16608 | ;; Special case of conditional move we can handle effectivly. | |
16609 | ;; Do not brother with the integer/floating point case, since these are | |
16610 | ;; bot considerably slower, unlike in the generic case. | |
16611 | (define_insn "*sse_movsfcc_const0_1" | |
66b408f2 | 16612 | [(set (match_operand:SF 0 "register_operand" "=&x") |
0073023d JH |
16613 | (if_then_else:SF (match_operator 1 "sse_comparison_operator" |
16614 | [(match_operand:SF 4 "register_operand" "0") | |
16615 | (match_operand:SF 5 "nonimmediate_operand" "xm")]) | |
16616 | (match_operand:SF 2 "register_operand" "x") | |
16617 | (match_operand:SF 3 "const0_operand" "X")))] | |
16618 | "TARGET_SSE" | |
16619 | "#") | |
16620 | ||
16621 | (define_insn "*sse_movsfcc_const0_2" | |
66b408f2 | 16622 | [(set (match_operand:SF 0 "register_operand" "=&x") |
0073023d JH |
16623 | (if_then_else:SF (match_operator 1 "sse_comparison_operator" |
16624 | [(match_operand:SF 4 "register_operand" "0") | |
16625 | (match_operand:SF 5 "nonimmediate_operand" "xm")]) | |
adc7fcb8 JH |
16626 | (match_operand:SF 2 "const0_operand" "X") |
16627 | (match_operand:SF 3 "register_operand" "x")))] | |
0073023d JH |
16628 | "TARGET_SSE" |
16629 | "#") | |
16630 | ||
16631 | (define_insn "*sse_movsfcc_const0_3" | |
66b408f2 | 16632 | [(set (match_operand:SF 0 "register_operand" "=&x") |
0073023d JH |
16633 | (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" |
16634 | [(match_operand:SF 4 "nonimmediate_operand" "xm") | |
16635 | (match_operand:SF 5 "register_operand" "0")]) | |
16636 | (match_operand:SF 2 "register_operand" "x") | |
16637 | (match_operand:SF 3 "const0_operand" "X")))] | |
16638 | "TARGET_SSE" | |
16639 | "#") | |
16640 | ||
16641 | (define_insn "*sse_movsfcc_const0_4" | |
66b408f2 | 16642 | [(set (match_operand:SF 0 "register_operand" "=&x") |
0073023d JH |
16643 | (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" |
16644 | [(match_operand:SF 4 "nonimmediate_operand" "xm") | |
16645 | (match_operand:SF 5 "register_operand" "0")]) | |
adc7fcb8 JH |
16646 | (match_operand:SF 2 "const0_operand" "X") |
16647 | (match_operand:SF 3 "register_operand" "x")))] | |
0073023d JH |
16648 | "TARGET_SSE" |
16649 | "#") | |
16650 | ||
16651 | (define_insn "*sse_movdfcc_const0_1" | |
66b408f2 JJ |
16652 | [(set (match_operand:DF 0 "register_operand" "=&Y") |
16653 | (if_then_else:DF (match_operator 1 "sse_comparison_operator" | |
16654 | [(match_operand:DF 4 "register_operand" "0") | |
16655 | (match_operand:DF 5 "nonimmediate_operand" "Ym")]) | |
16656 | (match_operand:DF 2 "register_operand" "Y") | |
16657 | (match_operand:DF 3 "const0_operand" "X")))] | |
0073023d JH |
16658 | "TARGET_SSE2" |
16659 | "#") | |
16660 | ||
16661 | (define_insn "*sse_movdfcc_const0_2" | |
66b408f2 JJ |
16662 | [(set (match_operand:DF 0 "register_operand" "=&Y") |
16663 | (if_then_else:DF (match_operator 1 "sse_comparison_operator" | |
16664 | [(match_operand:DF 4 "register_operand" "0") | |
16665 | (match_operand:DF 5 "nonimmediate_operand" "Ym")]) | |
16666 | (match_operand:DF 2 "const0_operand" "X") | |
16667 | (match_operand:DF 3 "register_operand" "Y")))] | |
0073023d JH |
16668 | "TARGET_SSE2" |
16669 | "#") | |
16670 | ||
16671 | (define_insn "*sse_movdfcc_const0_3" | |
66b408f2 JJ |
16672 | [(set (match_operand:DF 0 "register_operand" "=&Y") |
16673 | (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" | |
16674 | [(match_operand:DF 4 "nonimmediate_operand" "Ym") | |
16675 | (match_operand:DF 5 "register_operand" "0")]) | |
16676 | (match_operand:DF 2 "register_operand" "Y") | |
16677 | (match_operand:DF 3 "const0_operand" "X")))] | |
0073023d JH |
16678 | "TARGET_SSE2" |
16679 | "#") | |
16680 | ||
16681 | (define_insn "*sse_movdfcc_const0_4" | |
66b408f2 JJ |
16682 | [(set (match_operand:DF 0 "register_operand" "=&Y") |
16683 | (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" | |
16684 | [(match_operand:DF 4 "nonimmediate_operand" "Ym") | |
16685 | (match_operand:DF 5 "register_operand" "0")]) | |
16686 | (match_operand:DF 2 "const0_operand" "X") | |
16687 | (match_operand:DF 3 "register_operand" "Y")))] | |
0073023d JH |
16688 | "TARGET_SSE2" |
16689 | "#") | |
16690 | ||
16691 | (define_split | |
16692 | [(set (match_operand 0 "register_operand" "") | |
16693 | (if_then_else (match_operator 1 "comparison_operator" | |
16694 | [(match_operand 4 "register_operand" "") | |
16695 | (match_operand 5 "nonimmediate_operand" "")]) | |
16696 | (match_operand 2 "nonmemory_operand" "") | |
16697 | (match_operand 3 "nonmemory_operand" "")))] | |
16698 | "SSE_REG_P (operands[0]) && reload_completed | |
16699 | && (const0_operand (operands[2], GET_MODE (operands[0])) | |
16700 | || const0_operand (operands[3], GET_MODE (operands[0])))" | |
16701 | [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)])) | |
16702 | (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6) | |
16703 | (subreg:TI (match_dup 7) 0)))] | |
0073023d JH |
16704 | { |
16705 | PUT_MODE (operands[1], GET_MODE (operands[0])); | |
16706 | if (!sse_comparison_operator (operands[1], VOIDmode)) | |
16707 | { | |
16708 | rtx tmp = operands[5]; | |
16709 | operands[5] = operands[4]; | |
16710 | operands[4] = tmp; | |
16711 | PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1]))); | |
16712 | } | |
16713 | if (const0_operand (operands[2], GET_MODE (operands[0]))) | |
16714 | { | |
16715 | operands[7] = operands[3]; | |
16716 | operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0], | |
16717 | 0)); | |
16718 | } | |
16719 | else | |
16720 | { | |
16721 | operands[7] = operands[2]; | |
16722 | operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0); | |
16723 | } | |
0f40f9f7 | 16724 | }) |
0073023d | 16725 | |
885a70fd JH |
16726 | (define_expand "allocate_stack_worker" |
16727 | [(match_operand:SI 0 "register_operand" "")] | |
16728 | "TARGET_STACK_PROBE" | |
885a70fd JH |
16729 | { |
16730 | if (TARGET_64BIT) | |
16731 | emit_insn (gen_allocate_stack_worker_rex64 (operands[0])); | |
16732 | else | |
16733 | emit_insn (gen_allocate_stack_worker_1 (operands[0])); | |
16734 | DONE; | |
0f40f9f7 | 16735 | }) |
885a70fd JH |
16736 | |
16737 | (define_insn "allocate_stack_worker_1" | |
8ee41eaf | 16738 | [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE) |
578b58f5 | 16739 | (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0))) |
e075ae69 RH |
16740 | (clobber (match_dup 0)) |
16741 | (clobber (reg:CC 17))] | |
1b0c37d7 | 16742 | "!TARGET_64BIT && TARGET_STACK_PROBE" |
0f40f9f7 | 16743 | "call\t__alloca" |
885a70fd JH |
16744 | [(set_attr "type" "multi") |
16745 | (set_attr "length" "5")]) | |
16746 | ||
16747 | (define_insn "allocate_stack_worker_rex64" | |
8ee41eaf | 16748 | [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE) |
885a70fd JH |
16749 | (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0))) |
16750 | (clobber (match_dup 0)) | |
16751 | (clobber (reg:CC 17))] | |
1b0c37d7 | 16752 | "TARGET_64BIT && TARGET_STACK_PROBE" |
0f40f9f7 | 16753 | "call\t__alloca" |
e075ae69 RH |
16754 | [(set_attr "type" "multi") |
16755 | (set_attr "length" "5")]) | |
578b58f5 RK |
16756 | |
16757 | (define_expand "allocate_stack" | |
e075ae69 RH |
16758 | [(parallel [(set (match_operand:SI 0 "register_operand" "=r") |
16759 | (minus:SI (reg:SI 7) | |
16760 | (match_operand:SI 1 "general_operand" ""))) | |
16761 | (clobber (reg:CC 17))]) | |
16762 | (parallel [(set (reg:SI 7) | |
16763 | (minus:SI (reg:SI 7) (match_dup 1))) | |
16764 | (clobber (reg:CC 17))])] | |
16765 | "TARGET_STACK_PROBE" | |
578b58f5 RK |
16766 | { |
16767 | #ifdef CHECK_STACK_LIMIT | |
e9a25f70 JL |
16768 | if (GET_CODE (operands[1]) == CONST_INT |
16769 | && INTVAL (operands[1]) < CHECK_STACK_LIMIT) | |
578b58f5 | 16770 | emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, |
e9a25f70 | 16771 | operands[1])); |
578b58f5 RK |
16772 | else |
16773 | #endif | |
16774 | emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode, | |
e9a25f70 | 16775 | operands[1]))); |
578b58f5 | 16776 | |
e9a25f70 JL |
16777 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
16778 | DONE; | |
0f40f9f7 | 16779 | }) |
e31ca113 | 16780 | |
fb754025 AG |
16781 | (define_expand "builtin_setjmp_receiver" |
16782 | [(label_ref (match_operand 0 "" ""))] | |
1b0c37d7 | 16783 | "!TARGET_64BIT && flag_pic" |
fb754025 | 16784 | { |
c8c03509 | 16785 | emit_insn (gen_set_got (pic_offset_table_rtx)); |
fb754025 | 16786 | DONE; |
0f40f9f7 | 16787 | }) |
e9e80858 JH |
16788 | \f |
16789 | ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode. | |
16790 | ||
16791 | (define_split | |
16792 | [(set (match_operand 0 "register_operand" "") | |
16793 | (match_operator 3 "promotable_binary_operator" | |
16794 | [(match_operand 1 "register_operand" "") | |
2247f6ed | 16795 | (match_operand 2 "aligned_operand" "")])) |
e9e80858 JH |
16796 | (clobber (reg:CC 17))] |
16797 | "! TARGET_PARTIAL_REG_STALL && reload_completed | |
16798 | && ((GET_MODE (operands[0]) == HImode | |
285464d0 JH |
16799 | && ((!optimize_size && !TARGET_FAST_PREFIX) |
16800 | || GET_CODE (operands[2]) != CONST_INT | |
e9e80858 JH |
16801 | || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))) |
16802 | || (GET_MODE (operands[0]) == QImode | |
16803 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16804 | [(parallel [(set (match_dup 0) | |
16805 | (match_op_dup 3 [(match_dup 1) (match_dup 2)])) | |
16806 | (clobber (reg:CC 17))])] | |
16807 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
16808 | operands[1] = gen_lowpart (SImode, operands[1]); | |
16809 | if (GET_CODE (operands[3]) != ASHIFT) | |
16810 | operands[2] = gen_lowpart (SImode, operands[2]); | |
dbbbbf3b | 16811 | PUT_MODE (operands[3], SImode);") |
e9e80858 JH |
16812 | |
16813 | (define_split | |
16189740 RH |
16814 | [(set (reg 17) |
16815 | (compare (and (match_operand 1 "aligned_operand" "") | |
16816 | (match_operand 2 "const_int_operand" "")) | |
16817 | (const_int 0))) | |
e9e80858 JH |
16818 | (set (match_operand 0 "register_operand" "") |
16819 | (and (match_dup 1) (match_dup 2)))] | |
16820 | "! TARGET_PARTIAL_REG_STALL && reload_completed | |
16189740 | 16821 | && ix86_match_ccmode (insn, CCNOmode) |
e9e80858 JH |
16822 | && (GET_MODE (operands[0]) == HImode |
16823 | || (GET_MODE (operands[0]) == QImode | |
0d682900 JH |
16824 | /* Ensure that the operand will remain sign extended immedaite. */ |
16825 | && INTVAL (operands[2]) >= 0 | |
e9e80858 JH |
16826 | && (TARGET_PROMOTE_QImode || optimize_size)))" |
16827 | [(parallel [(set (reg:CCNO 17) | |
16828 | (compare:CCNO (and:SI (match_dup 1) (match_dup 2)) | |
16829 | (const_int 0))) | |
16830 | (set (match_dup 0) | |
16831 | (and:SI (match_dup 1) (match_dup 2)))])] | |
d9f0b960 | 16832 | "operands[2] |
d8bf17f9 LB |
16833 | = gen_int_mode (INTVAL (operands[2]) |
16834 | & GET_MODE_MASK (GET_MODE (operands[0])), | |
16835 | SImode); | |
d9f0b960 RH |
16836 | operands[0] = gen_lowpart (SImode, operands[0]); |
16837 | operands[1] = gen_lowpart (SImode, operands[1]);") | |
e9e80858 | 16838 | |
0d682900 JH |
16839 | ; Don't promote the QImode tests, as i386 don't have encoding of |
16840 | ; the test instruction with 32bit sign extended immediate and thus | |
16841 | ; the code grows. | |
e9e80858 | 16842 | (define_split |
16189740 | 16843 | [(set (reg 17) |
0d682900 JH |
16844 | (compare (and (match_operand:HI 0 "aligned_operand" "") |
16845 | (match_operand:HI 1 "const_int_operand" "")) | |
16189740 | 16846 | (const_int 0)))] |
e9e80858 | 16847 | "! TARGET_PARTIAL_REG_STALL && reload_completed |
16189740 | 16848 | && ix86_match_ccmode (insn, CCNOmode) |
0d682900 | 16849 | && GET_MODE (operands[0]) == HImode" |
e9e80858 JH |
16850 | [(set (reg:CCNO 17) |
16851 | (compare:CCNO (and:SI (match_dup 0) (match_dup 1)) | |
16852 | (const_int 0)))] | |
d9f0b960 | 16853 | "operands[1] |
d8bf17f9 LB |
16854 | = gen_int_mode (INTVAL (operands[1]) |
16855 | & GET_MODE_MASK (GET_MODE (operands[0])), | |
16856 | SImode); | |
d9f0b960 | 16857 | operands[0] = gen_lowpart (SImode, operands[0]);") |
e9e80858 JH |
16858 | |
16859 | (define_split | |
16860 | [(set (match_operand 0 "register_operand" "") | |
16861 | (neg (match_operand 1 "register_operand" ""))) | |
16862 | (clobber (reg:CC 17))] | |
16863 | "! TARGET_PARTIAL_REG_STALL && reload_completed | |
16864 | && (GET_MODE (operands[0]) == HImode | |
16865 | || (GET_MODE (operands[0]) == QImode | |
16866 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16867 | [(parallel [(set (match_dup 0) | |
16868 | (neg:SI (match_dup 1))) | |
16869 | (clobber (reg:CC 17))])] | |
16870 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
16871 | operands[1] = gen_lowpart (SImode, operands[1]);") | |
16872 | ||
16873 | (define_split | |
16874 | [(set (match_operand 0 "register_operand" "") | |
16875 | (not (match_operand 1 "register_operand" "")))] | |
16876 | "! TARGET_PARTIAL_REG_STALL && reload_completed | |
16877 | && (GET_MODE (operands[0]) == HImode | |
16878 | || (GET_MODE (operands[0]) == QImode | |
16879 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16880 | [(set (match_dup 0) | |
16881 | (not:SI (match_dup 1)))] | |
16882 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
16883 | operands[1] = gen_lowpart (SImode, operands[1]);") | |
16884 | ||
16885 | (define_split | |
16886 | [(set (match_operand 0 "register_operand" "") | |
16887 | (if_then_else (match_operator 1 "comparison_operator" | |
16888 | [(reg 17) (const_int 0)]) | |
16889 | (match_operand 2 "register_operand" "") | |
16890 | (match_operand 3 "register_operand" "")))] | |
16891 | "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE | |
16892 | && (GET_MODE (operands[0]) == HImode | |
16893 | || (GET_MODE (operands[0]) == QImode | |
16894 | && (TARGET_PROMOTE_QImode || optimize_size)))" | |
16895 | [(set (match_dup 0) | |
16896 | (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
16897 | "operands[0] = gen_lowpart (SImode, operands[0]); | |
16898 | operands[2] = gen_lowpart (SImode, operands[2]); | |
16899 | operands[3] = gen_lowpart (SImode, operands[3]);") | |
16900 | ||
e075ae69 RH |
16901 | \f |
16902 | ;; RTL Peephole optimizations, run before sched2. These primarily look to | |
16903 | ;; transform a complex memory operation into two memory to register operations. | |
16904 | ||
16905 | ;; Don't push memory operands | |
16906 | (define_peephole2 | |
3071fab5 RH |
16907 | [(set (match_operand:SI 0 "push_operand" "") |
16908 | (match_operand:SI 1 "memory_operand" "")) | |
16909 | (match_scratch:SI 2 "r")] | |
e075ae69 RH |
16910 | "! optimize_size && ! TARGET_PUSH_MEMORY" |
16911 | [(set (match_dup 2) (match_dup 1)) | |
16912 | (set (match_dup 0) (match_dup 2))] | |
16913 | "") | |
16914 | ||
cc2e591b JH |
16915 | (define_peephole2 |
16916 | [(set (match_operand:DI 0 "push_operand" "") | |
16917 | (match_operand:DI 1 "memory_operand" "")) | |
16918 | (match_scratch:DI 2 "r")] | |
16919 | "! optimize_size && ! TARGET_PUSH_MEMORY" | |
16920 | [(set (match_dup 2) (match_dup 1)) | |
16921 | (set (match_dup 0) (match_dup 2))] | |
16922 | "") | |
16923 | ||
e9e80858 JH |
16924 | ;; We need to handle SFmode only, because DFmode and XFmode is split to |
16925 | ;; SImode pushes. | |
16926 | (define_peephole2 | |
16927 | [(set (match_operand:SF 0 "push_operand" "") | |
16928 | (match_operand:SF 1 "memory_operand" "")) | |
16929 | (match_scratch:SF 2 "r")] | |
16930 | "! optimize_size && ! TARGET_PUSH_MEMORY" | |
16931 | [(set (match_dup 2) (match_dup 1)) | |
16932 | (set (match_dup 0) (match_dup 2))] | |
16933 | "") | |
16934 | ||
e075ae69 | 16935 | (define_peephole2 |
3071fab5 RH |
16936 | [(set (match_operand:HI 0 "push_operand" "") |
16937 | (match_operand:HI 1 "memory_operand" "")) | |
16938 | (match_scratch:HI 2 "r")] | |
e075ae69 RH |
16939 | "! optimize_size && ! TARGET_PUSH_MEMORY" |
16940 | [(set (match_dup 2) (match_dup 1)) | |
16941 | (set (match_dup 0) (match_dup 2))] | |
16942 | "") | |
16943 | ||
16944 | (define_peephole2 | |
3071fab5 RH |
16945 | [(set (match_operand:QI 0 "push_operand" "") |
16946 | (match_operand:QI 1 "memory_operand" "")) | |
16947 | (match_scratch:QI 2 "q")] | |
e075ae69 RH |
16948 | "! optimize_size && ! TARGET_PUSH_MEMORY" |
16949 | [(set (match_dup 2) (match_dup 1)) | |
16950 | (set (match_dup 0) (match_dup 2))] | |
16951 | "") | |
16952 | ||
16953 | ;; Don't move an immediate directly to memory when the instruction | |
16954 | ;; gets too big. | |
16955 | (define_peephole2 | |
16956 | [(match_scratch:SI 1 "r") | |
16957 | (set (match_operand:SI 0 "memory_operand" "") | |
16958 | (const_int 0))] | |
23280139 | 16959 | "! optimize_size |
591702de | 16960 | && ! TARGET_USE_MOV0 |
23280139 RH |
16961 | && TARGET_SPLIT_LONG_MOVES |
16962 | && get_attr_length (insn) >= ix86_cost->large_insn | |
16963 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
e075ae69 RH |
16964 | [(parallel [(set (match_dup 1) (const_int 0)) |
16965 | (clobber (reg:CC 17))]) | |
16966 | (set (match_dup 0) (match_dup 1))] | |
16967 | "") | |
16968 | ||
16969 | (define_peephole2 | |
16970 | [(match_scratch:HI 1 "r") | |
16971 | (set (match_operand:HI 0 "memory_operand" "") | |
16972 | (const_int 0))] | |
23280139 | 16973 | "! optimize_size |
591702de | 16974 | && ! TARGET_USE_MOV0 |
23280139 RH |
16975 | && TARGET_SPLIT_LONG_MOVES |
16976 | && get_attr_length (insn) >= ix86_cost->large_insn | |
16977 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
591702de | 16978 | [(parallel [(set (match_dup 2) (const_int 0)) |
e075ae69 RH |
16979 | (clobber (reg:CC 17))]) |
16980 | (set (match_dup 0) (match_dup 1))] | |
591702de | 16981 | "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));") |
e075ae69 RH |
16982 | |
16983 | (define_peephole2 | |
16984 | [(match_scratch:QI 1 "q") | |
16985 | (set (match_operand:QI 0 "memory_operand" "") | |
16986 | (const_int 0))] | |
23280139 | 16987 | "! optimize_size |
591702de | 16988 | && ! TARGET_USE_MOV0 |
23280139 RH |
16989 | && TARGET_SPLIT_LONG_MOVES |
16990 | && get_attr_length (insn) >= ix86_cost->large_insn | |
16991 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
591702de | 16992 | [(parallel [(set (match_dup 2) (const_int 0)) |
e075ae69 RH |
16993 | (clobber (reg:CC 17))]) |
16994 | (set (match_dup 0) (match_dup 1))] | |
591702de | 16995 | "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));") |
e075ae69 RH |
16996 | |
16997 | (define_peephole2 | |
16998 | [(match_scratch:SI 2 "r") | |
16999 | (set (match_operand:SI 0 "memory_operand" "") | |
17000 | (match_operand:SI 1 "immediate_operand" ""))] | |
23280139 RH |
17001 | "! optimize_size |
17002 | && get_attr_length (insn) >= ix86_cost->large_insn | |
17003 | && TARGET_SPLIT_LONG_MOVES" | |
e075ae69 RH |
17004 | [(set (match_dup 2) (match_dup 1)) |
17005 | (set (match_dup 0) (match_dup 2))] | |
17006 | "") | |
17007 | ||
17008 | (define_peephole2 | |
17009 | [(match_scratch:HI 2 "r") | |
17010 | (set (match_operand:HI 0 "memory_operand" "") | |
17011 | (match_operand:HI 1 "immediate_operand" ""))] | |
17012 | "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn | |
17013 | && TARGET_SPLIT_LONG_MOVES" | |
17014 | [(set (match_dup 2) (match_dup 1)) | |
17015 | (set (match_dup 0) (match_dup 2))] | |
17016 | "") | |
17017 | ||
17018 | (define_peephole2 | |
17019 | [(match_scratch:QI 2 "q") | |
17020 | (set (match_operand:QI 0 "memory_operand" "") | |
17021 | (match_operand:QI 1 "immediate_operand" ""))] | |
17022 | "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn | |
17023 | && TARGET_SPLIT_LONG_MOVES" | |
17024 | [(set (match_dup 2) (match_dup 1)) | |
17025 | (set (match_dup 0) (match_dup 2))] | |
17026 | "") | |
17027 | ||
17028 | ;; Don't compare memory with zero, load and use a test instead. | |
17029 | (define_peephole2 | |
16189740 RH |
17030 | [(set (reg 17) |
17031 | (compare (match_operand:SI 0 "memory_operand" "") | |
17032 | (const_int 0))) | |
3071fab5 | 17033 | (match_scratch:SI 3 "r")] |
16189740 RH |
17034 | "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size" |
17035 | [(set (match_dup 3) (match_dup 0)) | |
17036 | (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] | |
e075ae69 RH |
17037 | "") |
17038 | ||
17039 | ;; NOT is not pairable on Pentium, while XOR is, but one byte longer. | |
17040 | ;; Don't split NOTs with a displacement operand, because resulting XOR | |
17041 | ;; will not be pariable anyway. | |
17042 | ;; | |
17043 | ;; On AMD K6, NOT is vector decoded with memory operand that can not be | |
17044 | ;; represented using a modRM byte. The XOR replacement is long decoded, | |
17045 | ;; so this split helps here as well. | |
17046 | ;; | |
23280139 RH |
17047 | ;; Note: Can't do this as a regular split because we can't get proper |
17048 | ;; lifetime information then. | |
e075ae69 RH |
17049 | |
17050 | (define_peephole2 | |
d5d6a58b RH |
17051 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
17052 | (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
e075ae69 | 17053 | "!optimize_size |
23280139 | 17054 | && peep2_regno_dead_p (0, FLAGS_REG) |
e075ae69 RH |
17055 | && ((TARGET_PENTIUM |
17056 | && (GET_CODE (operands[0]) != MEM | |
17057 | || !memory_displacement_operand (operands[0], SImode))) | |
17058 | || (TARGET_K6 && long_memory_operand (operands[0], SImode)))" | |
17059 | [(parallel [(set (match_dup 0) | |
17060 | (xor:SI (match_dup 1) (const_int -1))) | |
17061 | (clobber (reg:CC 17))])] | |
17062 | "") | |
17063 | ||
17064 | (define_peephole2 | |
d5d6a58b RH |
17065 | [(set (match_operand:HI 0 "nonimmediate_operand" "") |
17066 | (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
e075ae69 | 17067 | "!optimize_size |
23280139 | 17068 | && peep2_regno_dead_p (0, FLAGS_REG) |
e075ae69 RH |
17069 | && ((TARGET_PENTIUM |
17070 | && (GET_CODE (operands[0]) != MEM | |
17071 | || !memory_displacement_operand (operands[0], HImode))) | |
17072 | || (TARGET_K6 && long_memory_operand (operands[0], HImode)))" | |
17073 | [(parallel [(set (match_dup 0) | |
17074 | (xor:HI (match_dup 1) (const_int -1))) | |
17075 | (clobber (reg:CC 17))])] | |
17076 | "") | |
17077 | ||
17078 | (define_peephole2 | |
d5d6a58b RH |
17079 | [(set (match_operand:QI 0 "nonimmediate_operand" "") |
17080 | (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
e075ae69 | 17081 | "!optimize_size |
23280139 | 17082 | && peep2_regno_dead_p (0, FLAGS_REG) |
e075ae69 RH |
17083 | && ((TARGET_PENTIUM |
17084 | && (GET_CODE (operands[0]) != MEM | |
17085 | || !memory_displacement_operand (operands[0], QImode))) | |
17086 | || (TARGET_K6 && long_memory_operand (operands[0], QImode)))" | |
17087 | [(parallel [(set (match_dup 0) | |
17088 | (xor:QI (match_dup 1) (const_int -1))) | |
17089 | (clobber (reg:CC 17))])] | |
17090 | "") | |
17091 | ||
17092 | ;; Non pairable "test imm, reg" instructions can be translated to | |
17093 | ;; "and imm, reg" if reg dies. The "and" form is also shorter (one | |
17094 | ;; byte opcode instead of two, have a short form for byte operands), | |
17095 | ;; so do it for other CPUs as well. Given that the value was dead, | |
f5143c46 | 17096 | ;; this should not create any new dependencies. Pass on the sub-word |
e075ae69 RH |
17097 | ;; versions if we're concerned about partial register stalls. |
17098 | ||
17099 | (define_peephole2 | |
16189740 RH |
17100 | [(set (reg 17) |
17101 | (compare (and:SI (match_operand:SI 0 "register_operand" "") | |
17102 | (match_operand:SI 1 "immediate_operand" "")) | |
17103 | (const_int 0)))] | |
17104 | "ix86_match_ccmode (insn, CCNOmode) | |
17105 | && (true_regnum (operands[0]) != 0 | |
6c81a490 JH |
17106 | || (GET_CODE (operands[1]) == CONST_INT |
17107 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))) | |
e075ae69 RH |
17108 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" |
17109 | [(parallel | |
17110 | [(set (reg:CCNO 17) | |
17111 | (compare:CCNO (and:SI (match_dup 0) | |
17112 | (match_dup 1)) | |
17113 | (const_int 0))) | |
17114 | (set (match_dup 0) | |
17115 | (and:SI (match_dup 0) (match_dup 1)))])] | |
17116 | "") | |
17117 | ||
e9e80858 JH |
17118 | ;; We don't need to handle HImode case, because it will be promoted to SImode |
17119 | ;; on ! TARGET_PARTIAL_REG_STALL | |
e075ae69 RH |
17120 | |
17121 | (define_peephole2 | |
16189740 RH |
17122 | [(set (reg 17) |
17123 | (compare (and:QI (match_operand:QI 0 "register_operand" "") | |
17124 | (match_operand:QI 1 "immediate_operand" "")) | |
17125 | (const_int 0)))] | |
e075ae69 | 17126 | "! TARGET_PARTIAL_REG_STALL |
16189740 | 17127 | && ix86_match_ccmode (insn, CCNOmode) |
e075ae69 RH |
17128 | && true_regnum (operands[0]) != 0 |
17129 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17130 | [(parallel | |
17131 | [(set (reg:CCNO 17) | |
17132 | (compare:CCNO (and:QI (match_dup 0) | |
17133 | (match_dup 1)) | |
17134 | (const_int 0))) | |
17135 | (set (match_dup 0) | |
17136 | (and:QI (match_dup 0) (match_dup 1)))])] | |
17137 | "") | |
17138 | ||
17139 | (define_peephole2 | |
16189740 RH |
17140 | [(set (reg 17) |
17141 | (compare | |
e075ae69 RH |
17142 | (and:SI |
17143 | (zero_extract:SI | |
3522082b | 17144 | (match_operand 0 "ext_register_operand" "") |
e075ae69 RH |
17145 | (const_int 8) |
17146 | (const_int 8)) | |
3522082b | 17147 | (match_operand 1 "const_int_operand" "")) |
e075ae69 RH |
17148 | (const_int 0)))] |
17149 | "! TARGET_PARTIAL_REG_STALL | |
16189740 | 17150 | && ix86_match_ccmode (insn, CCNOmode) |
e075ae69 RH |
17151 | && true_regnum (operands[0]) != 0 |
17152 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17153 | [(parallel [(set (reg:CCNO 17) | |
17154 | (compare:CCNO | |
17155 | (and:SI | |
17156 | (zero_extract:SI | |
17157 | (match_dup 0) | |
17158 | (const_int 8) | |
17159 | (const_int 8)) | |
17160 | (match_dup 1)) | |
17161 | (const_int 0))) | |
17162 | (set (zero_extract:SI (match_dup 0) | |
17163 | (const_int 8) | |
17164 | (const_int 8)) | |
17165 | (and:SI | |
17166 | (zero_extract:SI | |
17167 | (match_dup 0) | |
17168 | (const_int 8) | |
17169 | (const_int 8)) | |
17170 | (match_dup 1)))])] | |
17171 | "") | |
17172 | ||
17173 | ;; Don't do logical operations with memory inputs. | |
17174 | (define_peephole2 | |
17175 | [(match_scratch:SI 2 "r") | |
17176 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
17177 | (match_operator:SI 3 "arith_or_logical_operator" | |
17178 | [(match_dup 0) | |
17179 | (match_operand:SI 1 "memory_operand" "")])) | |
17180 | (clobber (reg:CC 17))])] | |
17181 | "! optimize_size && ! TARGET_READ_MODIFY" | |
17182 | [(set (match_dup 2) (match_dup 1)) | |
17183 | (parallel [(set (match_dup 0) | |
17184 | (match_op_dup 3 [(match_dup 0) (match_dup 2)])) | |
17185 | (clobber (reg:CC 17))])] | |
17186 | "") | |
17187 | ||
17188 | (define_peephole2 | |
17189 | [(match_scratch:SI 2 "r") | |
17190 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
17191 | (match_operator:SI 3 "arith_or_logical_operator" | |
17192 | [(match_operand:SI 1 "memory_operand" "") | |
17193 | (match_dup 0)])) | |
17194 | (clobber (reg:CC 17))])] | |
17195 | "! optimize_size && ! TARGET_READ_MODIFY" | |
17196 | [(set (match_dup 2) (match_dup 1)) | |
17197 | (parallel [(set (match_dup 0) | |
17198 | (match_op_dup 3 [(match_dup 2) (match_dup 0)])) | |
17199 | (clobber (reg:CC 17))])] | |
17200 | "") | |
17201 | ||
17202 | ; Don't do logical operations with memory outputs | |
17203 | ; | |
17204 | ; These two don't make sense for PPro/PII -- we're expanding a 4-uop | |
17205 | ; instruction into two 1-uop insns plus a 2-uop insn. That last has | |
17206 | ; the same decoder scheduling characteristics as the original. | |
17207 | ||
17208 | (define_peephole2 | |
17209 | [(match_scratch:SI 2 "r") | |
17210 | (parallel [(set (match_operand:SI 0 "memory_operand" "") | |
17211 | (match_operator:SI 3 "arith_or_logical_operator" | |
17212 | [(match_dup 0) | |
17213 | (match_operand:SI 1 "nonmemory_operand" "")])) | |
17214 | (clobber (reg:CC 17))])] | |
17215 | "! optimize_size && ! TARGET_READ_MODIFY_WRITE" | |
17216 | [(set (match_dup 2) (match_dup 0)) | |
17217 | (parallel [(set (match_dup 2) | |
17218 | (match_op_dup 3 [(match_dup 2) (match_dup 1)])) | |
17219 | (clobber (reg:CC 17))]) | |
17220 | (set (match_dup 0) (match_dup 2))] | |
17221 | "") | |
17222 | ||
17223 | (define_peephole2 | |
17224 | [(match_scratch:SI 2 "r") | |
17225 | (parallel [(set (match_operand:SI 0 "memory_operand" "") | |
17226 | (match_operator:SI 3 "arith_or_logical_operator" | |
17227 | [(match_operand:SI 1 "nonmemory_operand" "") | |
17228 | (match_dup 0)])) | |
17229 | (clobber (reg:CC 17))])] | |
17230 | "! optimize_size && ! TARGET_READ_MODIFY_WRITE" | |
17231 | [(set (match_dup 2) (match_dup 0)) | |
17232 | (parallel [(set (match_dup 2) | |
17233 | (match_op_dup 3 [(match_dup 1) (match_dup 2)])) | |
17234 | (clobber (reg:CC 17))]) | |
17235 | (set (match_dup 0) (match_dup 2))] | |
17236 | "") | |
17237 | ||
17238 | ;; Attempt to always use XOR for zeroing registers. | |
17239 | (define_peephole2 | |
17240 | [(set (match_operand 0 "register_operand" "") | |
17241 | (const_int 0))] | |
17242 | "(GET_MODE (operands[0]) == QImode | |
17243 | || GET_MODE (operands[0]) == HImode | |
cc2e591b JH |
17244 | || GET_MODE (operands[0]) == SImode |
17245 | || (GET_MODE (operands[0]) == DImode && TARGET_64BIT)) | |
e075ae69 | 17246 | && (! TARGET_USE_MOV0 || optimize_size) |
23280139 | 17247 | && peep2_regno_dead_p (0, FLAGS_REG)" |
e075ae69 RH |
17248 | [(parallel [(set (match_dup 0) (const_int 0)) |
17249 | (clobber (reg:CC 17))])] | |
cc2e591b JH |
17250 | "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode, |
17251 | true_regnum (operands[0]));") | |
d3a923ee | 17252 | |
6ef67412 JH |
17253 | (define_peephole2 |
17254 | [(set (strict_low_part (match_operand 0 "register_operand" "")) | |
17255 | (const_int 0))] | |
17256 | "(GET_MODE (operands[0]) == QImode | |
17257 | || GET_MODE (operands[0]) == HImode) | |
17258 | && (! TARGET_USE_MOV0 || optimize_size) | |
17259 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
17260 | [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0)) | |
17261 | (clobber (reg:CC 17))])]) | |
17262 | ||
e075ae69 RH |
17263 | ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg. |
17264 | (define_peephole2 | |
591702de | 17265 | [(set (match_operand 0 "register_operand" "") |
e075ae69 | 17266 | (const_int -1))] |
591702de | 17267 | "(GET_MODE (operands[0]) == HImode |
cc2e591b JH |
17268 | || GET_MODE (operands[0]) == SImode |
17269 | || (GET_MODE (operands[0]) == DImode && TARGET_64BIT)) | |
591702de | 17270 | && (optimize_size || TARGET_PENTIUM) |
23280139 | 17271 | && peep2_regno_dead_p (0, FLAGS_REG)" |
591702de | 17272 | [(parallel [(set (match_dup 0) (const_int -1)) |
e075ae69 | 17273 | (clobber (reg:CC 17))])] |
cc2e591b JH |
17274 | "operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode, |
17275 | true_regnum (operands[0]));") | |
1c27d4b2 JH |
17276 | |
17277 | ;; Attempt to convert simple leas to adds. These can be created by | |
17278 | ;; move expanders. | |
17279 | (define_peephole2 | |
17280 | [(set (match_operand:SI 0 "register_operand" "") | |
17281 | (plus:SI (match_dup 0) | |
17282 | (match_operand:SI 1 "nonmemory_operand" "")))] | |
23280139 | 17283 | "peep2_regno_dead_p (0, FLAGS_REG)" |
1c27d4b2 JH |
17284 | [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) |
17285 | (clobber (reg:CC 17))])] | |
17286 | "") | |
17287 | ||
cc2e591b JH |
17288 | (define_peephole2 |
17289 | [(set (match_operand:SI 0 "register_operand" "") | |
17290 | (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "") | |
17291 | (match_operand:DI 2 "nonmemory_operand" "")) 0))] | |
17292 | "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])" | |
17293 | [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
17294 | (clobber (reg:CC 17))])] | |
17295 | "operands[2] = gen_lowpart (SImode, operands[2]);") | |
17296 | ||
17297 | (define_peephole2 | |
17298 | [(set (match_operand:DI 0 "register_operand" "") | |
17299 | (plus:DI (match_dup 0) | |
17300 | (match_operand:DI 1 "x86_64_general_operand" "")))] | |
17301 | "peep2_regno_dead_p (0, FLAGS_REG)" | |
17302 | [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) | |
17303 | (clobber (reg:CC 17))])] | |
17304 | "") | |
17305 | ||
1c27d4b2 JH |
17306 | (define_peephole2 |
17307 | [(set (match_operand:SI 0 "register_operand" "") | |
17308 | (mult:SI (match_dup 0) | |
cc2e591b | 17309 | (match_operand:SI 1 "const_int_operand" "")))] |
23280139 RH |
17310 | "exact_log2 (INTVAL (operands[1])) >= 0 |
17311 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
1c27d4b2 JH |
17312 | [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2))) |
17313 | (clobber (reg:CC 17))])] | |
17314 | "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") | |
bdeb029c | 17315 | |
cc2e591b JH |
17316 | (define_peephole2 |
17317 | [(set (match_operand:DI 0 "register_operand" "") | |
17318 | (mult:DI (match_dup 0) | |
17319 | (match_operand:DI 1 "const_int_operand" "")))] | |
17320 | "exact_log2 (INTVAL (operands[1])) >= 0 | |
17321 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
17322 | [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2))) | |
17323 | (clobber (reg:CC 17))])] | |
17324 | "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") | |
17325 | ||
17326 | (define_peephole2 | |
17327 | [(set (match_operand:SI 0 "register_operand" "") | |
17328 | (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "") | |
17329 | (match_operand:DI 2 "const_int_operand" "")) 0))] | |
17330 | "exact_log2 (INTVAL (operands[1])) >= 0 | |
17331 | && REGNO (operands[0]) == REGNO (operands[1]) | |
17332 | && peep2_regno_dead_p (0, FLAGS_REG)" | |
17333 | [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2))) | |
17334 | (clobber (reg:CC 17))])] | |
17335 | "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));") | |
17336 | ||
bdeb029c JH |
17337 | ;; The ESP adjustments can be done by the push and pop instructions. Resulting |
17338 | ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On | |
17339 | ;; many CPUs it is also faster, since special hardware to avoid esp | |
f5143c46 | 17340 | ;; dependencies is present. |
bdeb029c | 17341 | |
d6a7951f | 17342 | ;; While some of these conversions may be done using splitters, we use peepholes |
bdeb029c JH |
17343 | ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL. |
17344 | ||
f5143c46 | 17345 | ;; Convert prologue esp subtractions to push. |
bdeb029c JH |
17346 | ;; We need register to push. In order to keep verify_flow_info happy we have |
17347 | ;; two choices | |
17348 | ;; - use scratch and clobber it in order to avoid dependencies | |
17349 | ;; - use already live register | |
17350 | ;; We can't use the second way right now, since there is no reliable way how to | |
17351 | ;; verify that given register is live. First choice will also most likely in | |
17352 | ;; fewer dependencies. On the place of esp adjustments it is very likely that | |
17353 | ;; call clobbered registers are dead. We may want to use base pointer as an | |
17354 | ;; alternative when no register is available later. | |
17355 | ||
17356 | (define_peephole2 | |
17357 | [(match_scratch:SI 0 "r") | |
17358 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) | |
f2042df3 RH |
17359 | (clobber (reg:CC 17)) |
17360 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17361 | "optimize_size || !TARGET_SUB_ESP_4" |
17362 | [(clobber (match_dup 0)) | |
17363 | (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) | |
f2042df3 | 17364 | (clobber (mem:BLK (scratch)))])]) |
bdeb029c JH |
17365 | |
17366 | (define_peephole2 | |
17367 | [(match_scratch:SI 0 "r") | |
17368 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
f2042df3 RH |
17369 | (clobber (reg:CC 17)) |
17370 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17371 | "optimize_size || !TARGET_SUB_ESP_8" |
17372 | [(clobber (match_dup 0)) | |
17373 | (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) | |
17374 | (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) | |
f2042df3 | 17375 | (clobber (mem:BLK (scratch)))])]) |
bdeb029c | 17376 | |
f5143c46 | 17377 | ;; Convert esp subtractions to push. |
bdeb029c JH |
17378 | (define_peephole2 |
17379 | [(match_scratch:SI 0 "r") | |
17380 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) | |
17381 | (clobber (reg:CC 17))])] | |
17382 | "optimize_size || !TARGET_SUB_ESP_4" | |
17383 | [(clobber (match_dup 0)) | |
17384 | (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]) | |
17385 | ||
17386 | (define_peephole2 | |
17387 | [(match_scratch:SI 0 "r") | |
17388 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
17389 | (clobber (reg:CC 17))])] | |
17390 | "optimize_size || !TARGET_SUB_ESP_8" | |
17391 | [(clobber (match_dup 0)) | |
17392 | (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) | |
17393 | (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]) | |
17394 | ||
17395 | ;; Convert epilogue deallocator to pop. | |
17396 | (define_peephole2 | |
17397 | [(match_scratch:SI 0 "r") | |
17398 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 RH |
17399 | (clobber (reg:CC 17)) |
17400 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17401 | "optimize_size || !TARGET_ADD_ESP_4" |
17402 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17403 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 | 17404 | (clobber (mem:BLK (scratch)))])] |
bdeb029c JH |
17405 | "") |
17406 | ||
17407 | ;; Two pops case is tricky, since pop causes dependency on destination register. | |
17408 | ;; We use two registers if available. | |
17409 | (define_peephole2 | |
17410 | [(match_scratch:SI 0 "r") | |
17411 | (match_scratch:SI 1 "r") | |
17412 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) | |
f2042df3 RH |
17413 | (clobber (reg:CC 17)) |
17414 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17415 | "optimize_size || !TARGET_ADD_ESP_8" |
17416 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17417 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 | 17418 | (clobber (mem:BLK (scratch)))]) |
bdeb029c JH |
17419 | (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) |
17420 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17421 | "") | |
17422 | ||
17423 | (define_peephole2 | |
17424 | [(match_scratch:SI 0 "r") | |
17425 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) | |
f2042df3 RH |
17426 | (clobber (reg:CC 17)) |
17427 | (clobber (mem:BLK (scratch)))])] | |
bdeb029c JH |
17428 | "optimize_size" |
17429 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17430 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
f2042df3 | 17431 | (clobber (mem:BLK (scratch)))]) |
bdeb029c JH |
17432 | (parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) |
17433 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17434 | "") | |
17435 | ||
17436 | ;; Convert esp additions to pop. | |
17437 | (define_peephole2 | |
17438 | [(match_scratch:SI 0 "r") | |
17439 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) | |
17440 | (clobber (reg:CC 17))])] | |
17441 | "" | |
17442 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17443 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17444 | "") | |
17445 | ||
17446 | ;; Two pops case is tricky, since pop causes dependency on destination register. | |
17447 | ;; We use two registers if available. | |
17448 | (define_peephole2 | |
17449 | [(match_scratch:SI 0 "r") | |
17450 | (match_scratch:SI 1 "r") | |
17451 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) | |
17452 | (clobber (reg:CC 17))])] | |
17453 | "" | |
17454 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17455 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]) | |
17456 | (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) | |
17457 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17458 | "") | |
17459 | ||
17460 | (define_peephole2 | |
17461 | [(match_scratch:SI 0 "r") | |
17462 | (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) | |
17463 | (clobber (reg:CC 17))])] | |
17464 | "optimize_size" | |
17465 | [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17466 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]) | |
17467 | (parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) | |
17468 | (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] | |
17469 | "") | |
69404d6f | 17470 | \f |
9dcbdc7e JH |
17471 | ;; Convert compares with 1 to shorter inc/dec operations when CF is not |
17472 | ;; required and register dies. | |
17473 | (define_peephole2 | |
17474 | [(set (reg 17) | |
17475 | (compare (match_operand:SI 0 "register_operand" "") | |
17476 | (match_operand:SI 1 "incdec_operand" "")))] | |
17477 | "ix86_match_ccmode (insn, CCGCmode) | |
17478 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17479 | [(parallel [(set (reg:CCGC 17) | |
265dab10 | 17480 | (compare:CCGC (match_dup 0) |
7e08e190 | 17481 | (match_dup 1))) |
9dcbdc7e | 17482 | (clobber (match_dup 0))])] |
7e08e190 | 17483 | "") |
9dcbdc7e JH |
17484 | |
17485 | (define_peephole2 | |
17486 | [(set (reg 17) | |
17487 | (compare (match_operand:HI 0 "register_operand" "") | |
17488 | (match_operand:HI 1 "incdec_operand" "")))] | |
17489 | "ix86_match_ccmode (insn, CCGCmode) | |
17490 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17491 | [(parallel [(set (reg:CCGC 17) | |
265dab10 | 17492 | (compare:CCGC (match_dup 0) |
7e08e190 | 17493 | (match_dup 1))) |
9dcbdc7e | 17494 | (clobber (match_dup 0))])] |
7e08e190 | 17495 | "") |
9dcbdc7e JH |
17496 | |
17497 | (define_peephole2 | |
17498 | [(set (reg 17) | |
17499 | (compare (match_operand:QI 0 "register_operand" "") | |
17500 | (match_operand:QI 1 "incdec_operand" "")))] | |
17501 | "ix86_match_ccmode (insn, CCGCmode) | |
17502 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" | |
17503 | [(parallel [(set (reg:CCGC 17) | |
265dab10 | 17504 | (compare:CCGC (match_dup 0) |
7e08e190 | 17505 | (match_dup 1))) |
9dcbdc7e | 17506 | (clobber (match_dup 0))])] |
7e08e190 | 17507 | "") |
9dcbdc7e JH |
17508 | |
17509 | ;; Convert compares with 128 to shorter add -128 | |
17510 | (define_peephole2 | |
17511 | [(set (reg 17) | |
17512 | (compare (match_operand:SI 0 "register_operand" "") | |
17513 | (const_int 128)))] | |
7e08e190 | 17514 | "ix86_match_ccmode (insn, CCGCmode) |
9dcbdc7e | 17515 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" |
7e08e190 JH |
17516 | [(parallel [(set (reg:CCGC 17) |
17517 | (compare:CCGC (match_dup 0) | |
17518 | (const_int 128))) | |
9dcbdc7e JH |
17519 | (clobber (match_dup 0))])] |
17520 | "") | |
17521 | ||
17522 | (define_peephole2 | |
17523 | [(set (reg 17) | |
17524 | (compare (match_operand:HI 0 "register_operand" "") | |
17525 | (const_int 128)))] | |
7e08e190 | 17526 | "ix86_match_ccmode (insn, CCGCmode) |
9dcbdc7e | 17527 | && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" |
7e08e190 JH |
17528 | [(parallel [(set (reg:CCGC 17) |
17529 | (compare:CCGC (match_dup 0) | |
17530 | (const_int 128))) | |
9dcbdc7e JH |
17531 | (clobber (match_dup 0))])] |
17532 | "") | |
17533 | \f | |
cc2e591b JH |
17534 | (define_peephole2 |
17535 | [(match_scratch:DI 0 "r") | |
17536 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) | |
f2042df3 RH |
17537 | (clobber (reg:CC 17)) |
17538 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17539 | "optimize_size || !TARGET_SUB_ESP_4" |
17540 | [(clobber (match_dup 0)) | |
17541 | (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) | |
f2042df3 | 17542 | (clobber (mem:BLK (scratch)))])]) |
cc2e591b JH |
17543 | |
17544 | (define_peephole2 | |
17545 | [(match_scratch:DI 0 "r") | |
17546 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) | |
f2042df3 RH |
17547 | (clobber (reg:CC 17)) |
17548 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17549 | "optimize_size || !TARGET_SUB_ESP_8" |
17550 | [(clobber (match_dup 0)) | |
17551 | (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) | |
17552 | (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) | |
f2042df3 | 17553 | (clobber (mem:BLK (scratch)))])]) |
cc2e591b | 17554 | |
f5143c46 | 17555 | ;; Convert esp subtractions to push. |
cc2e591b JH |
17556 | (define_peephole2 |
17557 | [(match_scratch:DI 0 "r") | |
17558 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) | |
17559 | (clobber (reg:CC 17))])] | |
17560 | "optimize_size || !TARGET_SUB_ESP_4" | |
17561 | [(clobber (match_dup 0)) | |
17562 | (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))]) | |
17563 | ||
17564 | (define_peephole2 | |
17565 | [(match_scratch:DI 0 "r") | |
17566 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) | |
17567 | (clobber (reg:CC 17))])] | |
17568 | "optimize_size || !TARGET_SUB_ESP_8" | |
17569 | [(clobber (match_dup 0)) | |
17570 | (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) | |
17571 | (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))]) | |
17572 | ||
17573 | ;; Convert epilogue deallocator to pop. | |
17574 | (define_peephole2 | |
17575 | [(match_scratch:DI 0 "r") | |
17576 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 RH |
17577 | (clobber (reg:CC 17)) |
17578 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17579 | "optimize_size || !TARGET_ADD_ESP_4" |
17580 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17581 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 | 17582 | (clobber (mem:BLK (scratch)))])] |
cc2e591b JH |
17583 | "") |
17584 | ||
17585 | ;; Two pops case is tricky, since pop causes dependency on destination register. | |
17586 | ;; We use two registers if available. | |
17587 | (define_peephole2 | |
17588 | [(match_scratch:DI 0 "r") | |
17589 | (match_scratch:DI 1 "r") | |
17590 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) | |
f2042df3 RH |
17591 | (clobber (reg:CC 17)) |
17592 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17593 | "optimize_size || !TARGET_ADD_ESP_8" |
17594 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17595 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 | 17596 | (clobber (mem:BLK (scratch)))]) |
cc2e591b JH |
17597 | (parallel [(set (match_dup 1) (mem:DI (reg:DI 7))) |
17598 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17599 | "") | |
17600 | ||
17601 | (define_peephole2 | |
17602 | [(match_scratch:DI 0 "r") | |
17603 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) | |
f2042df3 RH |
17604 | (clobber (reg:CC 17)) |
17605 | (clobber (mem:BLK (scratch)))])] | |
cc2e591b JH |
17606 | "optimize_size" |
17607 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17608 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
f2042df3 | 17609 | (clobber (mem:BLK (scratch)))]) |
cc2e591b JH |
17610 | (parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) |
17611 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17612 | "") | |
17613 | ||
17614 | ;; Convert esp additions to pop. | |
17615 | (define_peephole2 | |
17616 | [(match_scratch:DI 0 "r") | |
17617 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) | |
17618 | (clobber (reg:CC 17))])] | |
17619 | "" | |
17620 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17621 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17622 | "") | |
17623 | ||
17624 | ;; Two pops case is tricky, since pop causes dependency on destination register. | |
17625 | ;; We use two registers if available. | |
17626 | (define_peephole2 | |
17627 | [(match_scratch:DI 0 "r") | |
17628 | (match_scratch:DI 1 "r") | |
17629 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) | |
17630 | (clobber (reg:CC 17))])] | |
17631 | "" | |
17632 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17633 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))]) | |
17634 | (parallel [(set (match_dup 1) (mem:DI (reg:DI 7))) | |
17635 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17636 | "") | |
17637 | ||
17638 | (define_peephole2 | |
17639 | [(match_scratch:DI 0 "r") | |
17640 | (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) | |
17641 | (clobber (reg:CC 17))])] | |
17642 | "optimize_size" | |
17643 | [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17644 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))]) | |
17645 | (parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) | |
17646 | (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] | |
17647 | "") | |
17648 | \f | |
69404d6f RH |
17649 | ;; Call-value patterns last so that the wildcard operand does not |
17650 | ;; disrupt insn-recog's switch tables. | |
17651 | ||
94bb5d0c RH |
17652 | (define_insn "*call_value_pop_0" |
17653 | [(set (match_operand 0 "" "") | |
e1ff012c | 17654 | (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" "")) |
94bb5d0c RH |
17655 | (match_operand:SI 2 "" ""))) |
17656 | (set (reg:SI 7) (plus:SI (reg:SI 7) | |
90d10fb9 | 17657 | (match_operand:SI 3 "immediate_operand" "")))] |
1e07edd3 | 17658 | "!TARGET_64BIT" |
94bb5d0c RH |
17659 | { |
17660 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17661 | return "jmp\t%P1"; |
94bb5d0c | 17662 | else |
0f40f9f7 ZW |
17663 | return "call\t%P1"; |
17664 | } | |
94bb5d0c RH |
17665 | [(set_attr "type" "callv")]) |
17666 | ||
69404d6f RH |
17667 | (define_insn "*call_value_pop_1" |
17668 | [(set (match_operand 0 "" "") | |
e1ff012c | 17669 | (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm")) |
94bb5d0c | 17670 | (match_operand:SI 2 "" ""))) |
69404d6f | 17671 | (set (reg:SI 7) (plus:SI (reg:SI 7) |
90d10fb9 | 17672 | (match_operand:SI 3 "immediate_operand" "i")))] |
1e07edd3 | 17673 | "!TARGET_64BIT" |
69404d6f | 17674 | { |
94bb5d0c RH |
17675 | if (constant_call_address_operand (operands[1], QImode)) |
17676 | { | |
17677 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17678 | return "jmp\t%P1"; |
94bb5d0c | 17679 | else |
0f40f9f7 | 17680 | return "call\t%P1"; |
94bb5d0c | 17681 | } |
94bb5d0c | 17682 | if (SIBLING_CALL_P (insn)) |
0f40f9f7 | 17683 | return "jmp\t%A1"; |
94bb5d0c | 17684 | else |
0f40f9f7 ZW |
17685 | return "call\t%A1"; |
17686 | } | |
94bb5d0c RH |
17687 | [(set_attr "type" "callv")]) |
17688 | ||
17689 | (define_insn "*call_value_0" | |
17690 | [(set (match_operand 0 "" "") | |
e1ff012c | 17691 | (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" "")) |
94bb5d0c | 17692 | (match_operand:SI 2 "" "")))] |
32ee7d1d | 17693 | "!TARGET_64BIT" |
32ee7d1d JH |
17694 | { |
17695 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17696 | return "jmp\t%P1"; |
32ee7d1d | 17697 | else |
0f40f9f7 ZW |
17698 | return "call\t%P1"; |
17699 | } | |
32ee7d1d JH |
17700 | [(set_attr "type" "callv")]) |
17701 | ||
17702 | (define_insn "*call_value_0_rex64" | |
17703 | [(set (match_operand 0 "" "") | |
17704 | (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" "")) | |
17705 | (match_operand:DI 2 "const_int_operand" "")))] | |
17706 | "TARGET_64BIT" | |
94bb5d0c RH |
17707 | { |
17708 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17709 | return "jmp\t%P1"; |
94bb5d0c | 17710 | else |
0f40f9f7 ZW |
17711 | return "call\t%P1"; |
17712 | } | |
69404d6f RH |
17713 | [(set_attr "type" "callv")]) |
17714 | ||
69404d6f RH |
17715 | (define_insn "*call_value_1" |
17716 | [(set (match_operand 0 "" "") | |
e1ff012c | 17717 | (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm")) |
94bb5d0c | 17718 | (match_operand:SI 2 "" "")))] |
32ee7d1d | 17719 | "!TARGET_64BIT" |
32ee7d1d JH |
17720 | { |
17721 | if (constant_call_address_operand (operands[1], QImode)) | |
17722 | { | |
17723 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17724 | return "jmp\t%P1"; |
32ee7d1d | 17725 | else |
0f40f9f7 | 17726 | return "call\t%P1"; |
32ee7d1d JH |
17727 | } |
17728 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17729 | return "jmp\t%*%1"; |
32ee7d1d | 17730 | else |
0f40f9f7 ZW |
17731 | return "call\t%*%1"; |
17732 | } | |
32ee7d1d JH |
17733 | [(set_attr "type" "callv")]) |
17734 | ||
17735 | (define_insn "*call_value_1_rex64" | |
17736 | [(set (match_operand 0 "" "") | |
17737 | (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm")) | |
17738 | (match_operand:DI 2 "" "")))] | |
17739 | "TARGET_64BIT" | |
69404d6f | 17740 | { |
94bb5d0c | 17741 | if (constant_call_address_operand (operands[1], QImode)) |
cbbf65e0 RH |
17742 | { |
17743 | if (SIBLING_CALL_P (insn)) | |
0f40f9f7 | 17744 | return "jmp\t%P1"; |
cbbf65e0 | 17745 | else |
0f40f9f7 | 17746 | return "call\t%P1"; |
cbbf65e0 | 17747 | } |
cbbf65e0 | 17748 | if (SIBLING_CALL_P (insn)) |
0f40f9f7 | 17749 | return "jmp\t%A1"; |
cbbf65e0 | 17750 | else |
0f40f9f7 ZW |
17751 | return "call\t%A1"; |
17752 | } | |
69404d6f | 17753 | [(set_attr "type" "callv")]) |
9e3e266c GM |
17754 | \f |
17755 | (define_insn "trap" | |
17756 | [(trap_if (const_int 1) (const_int 5))] | |
17757 | "" | |
0f40f9f7 | 17758 | "int\t$5") |
9e3e266c GM |
17759 | |
17760 | ;;; ix86 doesn't have conditional trap instructions, but we fake them | |
17761 | ;;; for the sake of bounds checking. By emitting bounds checks as | |
17762 | ;;; conditional traps rather than as conditional jumps around | |
17763 | ;;; unconditional traps we avoid introducing spurious basic-block | |
17764 | ;;; boundaries and facilitate elimination of redundant checks. In | |
17765 | ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use | |
17766 | ;;; interrupt 5. | |
17767 | ;;; | |
17768 | ;;; FIXME: Static branch prediction rules for ix86 are such that | |
17769 | ;;; forward conditional branches predict as untaken. As implemented | |
17770 | ;;; below, pseudo conditional traps violate that rule. We should use | |
17771 | ;;; .pushsection/.popsection to place all of the `int 5's in a special | |
17772 | ;;; section loaded at the end of the text segment and branch forward | |
17773 | ;;; there on bounds-failure, and then jump back immediately (in case | |
17774 | ;;; the system chooses to ignore bounds violations, or to report | |
17775 | ;;; violations and continue execution). | |
17776 | ||
17777 | (define_expand "conditional_trap" | |
17778 | [(trap_if (match_operator 0 "comparison_operator" | |
17779 | [(match_dup 2) (const_int 0)]) | |
17780 | (match_operand 1 "const_int_operand" ""))] | |
17781 | "" | |
9e3e266c GM |
17782 | { |
17783 | emit_insn (gen_rtx_TRAP_IF (VOIDmode, | |
a1b8572c | 17784 | ix86_expand_compare (GET_CODE (operands[0]), |
df4ae160 | 17785 | NULL, NULL), |
9e3e266c GM |
17786 | operands[1])); |
17787 | DONE; | |
0f40f9f7 | 17788 | }) |
9e3e266c | 17789 | |
0f40f9f7 | 17790 | (define_insn "*conditional_trap_1" |
9e3e266c GM |
17791 | [(trap_if (match_operator 0 "comparison_operator" |
17792 | [(reg 17) (const_int 0)]) | |
17793 | (match_operand 1 "const_int_operand" ""))] | |
17794 | "" | |
9e3e266c GM |
17795 | { |
17796 | operands[2] = gen_label_rtx (); | |
0f40f9f7 ZW |
17797 | output_asm_insn ("j%c0\t%l2\; int\t%1", operands); |
17798 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", | |
9e3e266c GM |
17799 | CODE_LABEL_NUMBER (operands[2])); |
17800 | RET; | |
0f40f9f7 | 17801 | }) |
915119a5 BS |
17802 | |
17803 | ;; Pentium III SIMD instructions. | |
17804 | ||
17805 | ;; Moves for SSE/MMX regs. | |
17806 | ||
17807 | (define_insn "movv4sf_internal" | |
17808 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
e37af218 | 17809 | (match_operand:V4SF 1 "nonimmediate_operand" "xm,x"))] |
915119a5 BS |
17810 | "TARGET_SSE" |
17811 | ;; @@@ let's try to use movaps here. | |
0f40f9f7 | 17812 | "movaps\t{%1, %0|%0, %1}" |
3d34cd91 JH |
17813 | [(set_attr "type" "ssemov") |
17814 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
17815 | |
17816 | (define_insn "movv4si_internal" | |
17817 | [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m") | |
e37af218 | 17818 | (match_operand:V4SI 1 "nonimmediate_operand" "xm,x"))] |
915119a5 BS |
17819 | "TARGET_SSE" |
17820 | ;; @@@ let's try to use movaps here. | |
0f40f9f7 | 17821 | "movaps\t{%1, %0|%0, %1}" |
3d34cd91 JH |
17822 | [(set_attr "type" "ssemov") |
17823 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
17824 | |
17825 | (define_insn "movv8qi_internal" | |
17826 | [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m") | |
e37af218 | 17827 | (match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))] |
915119a5 | 17828 | "TARGET_MMX" |
0f40f9f7 | 17829 | "movq\t{%1, %0|%0, %1}" |
3d34cd91 JH |
17830 | [(set_attr "type" "mmxmov") |
17831 | (set_attr "mode" "DI")]) | |
915119a5 BS |
17832 | |
17833 | (define_insn "movv4hi_internal" | |
17834 | [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m") | |
e37af218 | 17835 | (match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))] |
915119a5 | 17836 | "TARGET_MMX" |
0f40f9f7 | 17837 | "movq\t{%1, %0|%0, %1}" |
3d34cd91 JH |
17838 | [(set_attr "type" "mmxmov") |
17839 | (set_attr "mode" "DI")]) | |
915119a5 BS |
17840 | |
17841 | (define_insn "movv2si_internal" | |
17842 | [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m") | |
e37af218 | 17843 | (match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))] |
915119a5 | 17844 | "TARGET_MMX" |
0f40f9f7 | 17845 | "movq\t{%1, %0|%0, %1}" |
3d34cd91 JH |
17846 | [(set_attr "type" "mmxcvt") |
17847 | (set_attr "mode" "DI")]) | |
915119a5 | 17848 | |
47f339cf BS |
17849 | (define_insn "movv2sf_internal" |
17850 | [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m") | |
e37af218 | 17851 | (match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))] |
47f339cf BS |
17852 | "TARGET_3DNOW" |
17853 | "movq\\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
17854 | [(set_attr "type" "mmxcvt") |
17855 | (set_attr "mode" "DI")]) | |
47f339cf | 17856 | |
915119a5 BS |
17857 | (define_expand "movti" |
17858 | [(set (match_operand:TI 0 "general_operand" "") | |
17859 | (match_operand:TI 1 "general_operand" ""))] | |
44cf5b6a | 17860 | "TARGET_SSE || TARGET_64BIT" |
915119a5 | 17861 | { |
44cf5b6a | 17862 | if (TARGET_64BIT) |
e37af218 RH |
17863 | ix86_expand_move (TImode, operands); |
17864 | else | |
17865 | ix86_expand_vector_move (TImode, operands); | |
17866 | DONE; | |
0f40f9f7 | 17867 | }) |
915119a5 | 17868 | |
fbe5eb6d BS |
17869 | (define_insn "movv2df_internal" |
17870 | [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") | |
17871 | (match_operand:V2DF 1 "general_operand" "xm,x"))] | |
17872 | "TARGET_SSE2" | |
17873 | ;; @@@ let's try to use movaps here. | |
17874 | "movapd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
17875 | [(set_attr "type" "ssemov") |
17876 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
17877 | |
17878 | (define_insn "movv8hi_internal" | |
17879 | [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m") | |
17880 | (match_operand:V8HI 1 "general_operand" "xm,x"))] | |
17881 | "TARGET_SSE2" | |
17882 | ;; @@@ let's try to use movaps here. | |
17883 | "movaps\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
17884 | [(set_attr "type" "ssemov") |
17885 | (set_attr "mode" "V4SF")]) | |
fbe5eb6d BS |
17886 | |
17887 | (define_insn "movv16qi_internal" | |
17888 | [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m") | |
17889 | (match_operand:V16QI 1 "general_operand" "xm,x"))] | |
17890 | "TARGET_SSE2" | |
17891 | ;; @@@ let's try to use movaps here. | |
17892 | "movaps\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
17893 | [(set_attr "type" "ssemov") |
17894 | (set_attr "mode" "V4SF")]) | |
fbe5eb6d BS |
17895 | |
17896 | (define_expand "movv2df" | |
17897 | [(set (match_operand:V2DF 0 "general_operand" "") | |
17898 | (match_operand:V2DF 1 "general_operand" ""))] | |
17899 | "TARGET_SSE2" | |
17900 | { | |
17901 | ix86_expand_vector_move (V2DFmode, operands); | |
17902 | DONE; | |
17903 | }) | |
17904 | ||
17905 | (define_expand "movv8hi" | |
17906 | [(set (match_operand:V8HI 0 "general_operand" "") | |
17907 | (match_operand:V8HI 1 "general_operand" ""))] | |
17908 | "TARGET_SSE2" | |
17909 | { | |
17910 | ix86_expand_vector_move (V8HImode, operands); | |
17911 | DONE; | |
17912 | }) | |
17913 | ||
17914 | (define_expand "movv16qi" | |
17915 | [(set (match_operand:V16QI 0 "general_operand" "") | |
17916 | (match_operand:V16QI 1 "general_operand" ""))] | |
17917 | "TARGET_SSE2" | |
17918 | { | |
17919 | ix86_expand_vector_move (V16QImode, operands); | |
17920 | DONE; | |
17921 | }) | |
17922 | ||
915119a5 BS |
17923 | (define_expand "movv4sf" |
17924 | [(set (match_operand:V4SF 0 "general_operand" "") | |
17925 | (match_operand:V4SF 1 "general_operand" ""))] | |
17926 | "TARGET_SSE" | |
915119a5 | 17927 | { |
e37af218 RH |
17928 | ix86_expand_vector_move (V4SFmode, operands); |
17929 | DONE; | |
0f40f9f7 | 17930 | }) |
915119a5 BS |
17931 | |
17932 | (define_expand "movv4si" | |
17933 | [(set (match_operand:V4SI 0 "general_operand" "") | |
17934 | (match_operand:V4SI 1 "general_operand" ""))] | |
17935 | "TARGET_MMX" | |
915119a5 | 17936 | { |
e37af218 RH |
17937 | ix86_expand_vector_move (V4SImode, operands); |
17938 | DONE; | |
0f40f9f7 | 17939 | }) |
915119a5 BS |
17940 | |
17941 | (define_expand "movv2si" | |
17942 | [(set (match_operand:V2SI 0 "general_operand" "") | |
17943 | (match_operand:V2SI 1 "general_operand" ""))] | |
17944 | "TARGET_MMX" | |
915119a5 | 17945 | { |
e37af218 RH |
17946 | ix86_expand_vector_move (V2SImode, operands); |
17947 | DONE; | |
0f40f9f7 | 17948 | }) |
915119a5 BS |
17949 | |
17950 | (define_expand "movv4hi" | |
17951 | [(set (match_operand:V4HI 0 "general_operand" "") | |
17952 | (match_operand:V4HI 1 "general_operand" ""))] | |
17953 | "TARGET_MMX" | |
915119a5 | 17954 | { |
e37af218 RH |
17955 | ix86_expand_vector_move (V4HImode, operands); |
17956 | DONE; | |
0f40f9f7 | 17957 | }) |
915119a5 BS |
17958 | |
17959 | (define_expand "movv8qi" | |
17960 | [(set (match_operand:V8QI 0 "general_operand" "") | |
17961 | (match_operand:V8QI 1 "general_operand" ""))] | |
17962 | "TARGET_MMX" | |
915119a5 | 17963 | { |
e37af218 RH |
17964 | ix86_expand_vector_move (V8QImode, operands); |
17965 | DONE; | |
0f40f9f7 | 17966 | }) |
915119a5 | 17967 | |
47f339cf BS |
17968 | (define_expand "movv2sf" |
17969 | [(set (match_operand:V2SF 0 "general_operand" "") | |
17970 | (match_operand:V2SF 1 "general_operand" ""))] | |
17971 | "TARGET_3DNOW" | |
47f339cf | 17972 | { |
e37af218 RH |
17973 | ix86_expand_vector_move (V2SFmode, operands); |
17974 | DONE; | |
17975 | }) | |
47f339cf | 17976 | |
915119a5 BS |
17977 | (define_insn_and_split "*pushti" |
17978 | [(set (match_operand:TI 0 "push_operand" "=<") | |
17979 | (match_operand:TI 1 "nonmemory_operand" "x"))] | |
17980 | "TARGET_SSE" | |
17981 | "#" | |
17982 | "" | |
17983 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) | |
17984 | (set (mem:TI (reg:SI 7)) (match_dup 1))] | |
17985 | "" | |
3d34cd91 | 17986 | [(set_attr "type" "multi")]) |
915119a5 | 17987 | |
fbe5eb6d BS |
17988 | (define_insn_and_split "*pushv2df" |
17989 | [(set (match_operand:V2DF 0 "push_operand" "=<") | |
17990 | (match_operand:V2DF 1 "nonmemory_operand" "x"))] | |
17991 | "TARGET_SSE2" | |
17992 | "#" | |
17993 | "" | |
17994 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) | |
17995 | (set (mem:V2DF (reg:SI 7)) (match_dup 1))] | |
17996 | "" | |
3d34cd91 | 17997 | [(set_attr "type" "multi")]) |
fbe5eb6d BS |
17998 | |
17999 | (define_insn_and_split "*pushv8hi" | |
18000 | [(set (match_operand:V8HI 0 "push_operand" "=<") | |
18001 | (match_operand:V8HI 1 "nonmemory_operand" "x"))] | |
18002 | "TARGET_SSE2" | |
18003 | "#" | |
18004 | "" | |
18005 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) | |
18006 | (set (mem:V8HI (reg:SI 7)) (match_dup 1))] | |
18007 | "" | |
3d34cd91 | 18008 | [(set_attr "type" "multi")]) |
fbe5eb6d BS |
18009 | |
18010 | (define_insn_and_split "*pushv16qi" | |
18011 | [(set (match_operand:V16QI 0 "push_operand" "=<") | |
18012 | (match_operand:V16QI 1 "nonmemory_operand" "x"))] | |
18013 | "TARGET_SSE2" | |
18014 | "#" | |
18015 | "" | |
18016 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) | |
18017 | (set (mem:V16QI (reg:SI 7)) (match_dup 1))] | |
18018 | "" | |
3d34cd91 | 18019 | [(set_attr "type" "multi")]) |
fbe5eb6d | 18020 | |
915119a5 BS |
18021 | (define_insn_and_split "*pushv4sf" |
18022 | [(set (match_operand:V4SF 0 "push_operand" "=<") | |
18023 | (match_operand:V4SF 1 "nonmemory_operand" "x"))] | |
18024 | "TARGET_SSE" | |
18025 | "#" | |
18026 | "" | |
18027 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) | |
18028 | (set (mem:V4SF (reg:SI 7)) (match_dup 1))] | |
18029 | "" | |
3d34cd91 | 18030 | [(set_attr "type" "multi")]) |
915119a5 BS |
18031 | |
18032 | (define_insn_and_split "*pushv4si" | |
18033 | [(set (match_operand:V4SI 0 "push_operand" "=<") | |
18034 | (match_operand:V4SI 1 "nonmemory_operand" "x"))] | |
18035 | "TARGET_SSE" | |
18036 | "#" | |
18037 | "" | |
18038 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) | |
18039 | (set (mem:V4SI (reg:SI 7)) (match_dup 1))] | |
18040 | "" | |
3d34cd91 | 18041 | [(set_attr "type" "multi")]) |
915119a5 BS |
18042 | |
18043 | (define_insn_and_split "*pushv2si" | |
18044 | [(set (match_operand:V2SI 0 "push_operand" "=<") | |
18045 | (match_operand:V2SI 1 "nonmemory_operand" "y"))] | |
18046 | "TARGET_MMX" | |
18047 | "#" | |
18048 | "" | |
18049 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
18050 | (set (mem:V2SI (reg:SI 7)) (match_dup 1))] | |
18051 | "" | |
18052 | [(set_attr "type" "mmx")]) | |
18053 | ||
18054 | (define_insn_and_split "*pushv4hi" | |
18055 | [(set (match_operand:V4HI 0 "push_operand" "=<") | |
18056 | (match_operand:V4HI 1 "nonmemory_operand" "y"))] | |
18057 | "TARGET_MMX" | |
18058 | "#" | |
18059 | "" | |
18060 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
18061 | (set (mem:V4HI (reg:SI 7)) (match_dup 1))] | |
18062 | "" | |
18063 | [(set_attr "type" "mmx")]) | |
18064 | ||
18065 | (define_insn_and_split "*pushv8qi" | |
18066 | [(set (match_operand:V8QI 0 "push_operand" "=<") | |
18067 | (match_operand:V8QI 1 "nonmemory_operand" "y"))] | |
18068 | "TARGET_MMX" | |
18069 | "#" | |
18070 | "" | |
18071 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
18072 | (set (mem:V8QI (reg:SI 7)) (match_dup 1))] | |
18073 | "" | |
18074 | [(set_attr "type" "mmx")]) | |
18075 | ||
47f339cf BS |
18076 | (define_insn_and_split "*pushv2sf" |
18077 | [(set (match_operand:V2SF 0 "push_operand" "=<") | |
18078 | (match_operand:V2SF 1 "nonmemory_operand" "y"))] | |
18079 | "TARGET_3DNOW" | |
18080 | "#" | |
18081 | "" | |
18082 | [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) | |
18083 | (set (mem:V2SF (reg:SI 7)) (match_dup 1))] | |
18084 | "" | |
18085 | [(set_attr "type" "mmx")]) | |
18086 | ||
915119a5 | 18087 | (define_insn "movti_internal" |
e37af218 RH |
18088 | [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m") |
18089 | (match_operand:TI 1 "general_operand" "O,xm,x"))] | |
44cf5b6a | 18090 | "TARGET_SSE && !TARGET_64BIT" |
915119a5 | 18091 | "@ |
e37af218 | 18092 | xorps\t%0, %0 |
0f40f9f7 ZW |
18093 | movaps\t{%1, %0|%0, %1} |
18094 | movaps\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
18095 | [(set_attr "type" "ssemov,ssemov,ssemov") |
18096 | (set_attr "mode" "V4SF")]) | |
915119a5 | 18097 | |
44cf5b6a | 18098 | (define_insn "*movti_rex64" |
e37af218 RH |
18099 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x") |
18100 | (match_operand:TI 1 "general_operand" "riFo,riF,O,x,m"))] | |
44cf5b6a JH |
18101 | "TARGET_64BIT |
18102 | && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" | |
18103 | "@ | |
18104 | # | |
18105 | # | |
e37af218 | 18106 | xorps\t%0, %0 |
44cf5b6a JH |
18107 | movaps\\t{%1, %0|%0, %1} |
18108 | movaps\\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
18109 | [(set_attr "type" "*,*,ssemov,ssemov,ssemov") |
18110 | (set_attr "mode" "V4SF")]) | |
44cf5b6a JH |
18111 | |
18112 | (define_split | |
18113 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
18114 | (match_operand:TI 1 "general_operand" ""))] | |
4fe8523b JH |
18115 | "reload_completed && !SSE_REG_P (operands[0]) |
18116 | && !SSE_REG_P (operands[1])" | |
44cf5b6a JH |
18117 | [(const_int 0)] |
18118 | "ix86_split_long_move (operands); DONE;") | |
18119 | ||
915119a5 BS |
18120 | ;; These two patterns are useful for specifying exactly whether to use |
18121 | ;; movaps or movups | |
18122 | (define_insn "sse_movaps" | |
18123 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
8ee41eaf RH |
18124 | (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] |
18125 | UNSPEC_MOVA))] | |
915119a5 BS |
18126 | "TARGET_SSE" |
18127 | "@ | |
0f40f9f7 ZW |
18128 | movaps\t{%1, %0|%0, %1} |
18129 | movaps\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
18130 | [(set_attr "type" "ssemov,ssemov") |
18131 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18132 | |
18133 | (define_insn "sse_movups" | |
18134 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
8ee41eaf RH |
18135 | (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")] |
18136 | UNSPEC_MOVU))] | |
915119a5 BS |
18137 | "TARGET_SSE" |
18138 | "@ | |
0f40f9f7 ZW |
18139 | movups\t{%1, %0|%0, %1} |
18140 | movups\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
18141 | [(set_attr "type" "ssecvt,ssecvt") |
18142 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18143 | |
18144 | ||
18145 | ;; SSE Strange Moves. | |
18146 | ||
18147 | (define_insn "sse_movmskps" | |
18148 | [(set (match_operand:SI 0 "register_operand" "=r") | |
8ee41eaf RH |
18149 | (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] |
18150 | UNSPEC_MOVMSK))] | |
915119a5 | 18151 | "TARGET_SSE" |
0f40f9f7 | 18152 | "movmskps\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18153 | [(set_attr "type" "ssecvt") |
18154 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18155 | |
18156 | (define_insn "mmx_pmovmskb" | |
18157 | [(set (match_operand:SI 0 "register_operand" "=r") | |
8ee41eaf RH |
18158 | (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] |
18159 | UNSPEC_MOVMSK))] | |
47f339cf | 18160 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 18161 | "pmovmskb\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18162 | [(set_attr "type" "ssecvt") |
18163 | (set_attr "mode" "V4SF")]) | |
18164 | ||
915119a5 BS |
18165 | |
18166 | (define_insn "mmx_maskmovq" | |
18167 | [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D")) | |
18168 | (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") | |
8ee41eaf RH |
18169 | (match_operand:V8QI 2 "register_operand" "y")] |
18170 | UNSPEC_MASKMOV))] | |
e95d6b23 JH |
18171 | "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT" |
18172 | ;; @@@ check ordering of operands in intel/nonintel syntax | |
18173 | "maskmovq\t{%2, %1|%1, %2}" | |
3d34cd91 JH |
18174 | [(set_attr "type" "mmxcvt") |
18175 | (set_attr "mode" "DI")]) | |
e95d6b23 JH |
18176 | |
18177 | (define_insn "mmx_maskmovq_rex" | |
18178 | [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D")) | |
18179 | (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") | |
8ee41eaf RH |
18180 | (match_operand:V8QI 2 "register_operand" "y")] |
18181 | UNSPEC_MASKMOV))] | |
e95d6b23 | 18182 | "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT" |
915119a5 | 18183 | ;; @@@ check ordering of operands in intel/nonintel syntax |
0f40f9f7 | 18184 | "maskmovq\t{%2, %1|%1, %2}" |
3d34cd91 JH |
18185 | [(set_attr "type" "mmxcvt") |
18186 | (set_attr "mode" "DI")]) | |
915119a5 BS |
18187 | |
18188 | (define_insn "sse_movntv4sf" | |
18189 | [(set (match_operand:V4SF 0 "memory_operand" "=m") | |
8ee41eaf RH |
18190 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] |
18191 | UNSPEC_MOVNT))] | |
915119a5 | 18192 | "TARGET_SSE" |
0f40f9f7 | 18193 | "movntps\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18194 | [(set_attr "type" "ssemov") |
18195 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18196 | |
18197 | (define_insn "sse_movntdi" | |
18198 | [(set (match_operand:DI 0 "memory_operand" "=m") | |
8ee41eaf RH |
18199 | (unspec:DI [(match_operand:DI 1 "register_operand" "y")] |
18200 | UNSPEC_MOVNT))] | |
47f339cf | 18201 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 18202 | "movntq\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18203 | [(set_attr "type" "mmxmov") |
18204 | (set_attr "mode" "DI")]) | |
915119a5 BS |
18205 | |
18206 | (define_insn "sse_movhlps" | |
18207 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18208 | (vec_merge:V4SF | |
18209 | (match_operand:V4SF 1 "register_operand" "0") | |
18210 | (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") | |
18211 | (parallel [(const_int 2) | |
18212 | (const_int 3) | |
18213 | (const_int 0) | |
18214 | (const_int 1)])) | |
18215 | (const_int 3)))] | |
18216 | "TARGET_SSE" | |
0f40f9f7 | 18217 | "movhlps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18218 | [(set_attr "type" "ssecvt") |
18219 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18220 | |
18221 | (define_insn "sse_movlhps" | |
18222 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18223 | (vec_merge:V4SF | |
18224 | (match_operand:V4SF 1 "register_operand" "0") | |
18225 | (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") | |
18226 | (parallel [(const_int 2) | |
18227 | (const_int 3) | |
18228 | (const_int 0) | |
18229 | (const_int 1)])) | |
18230 | (const_int 12)))] | |
18231 | "TARGET_SSE" | |
0f40f9f7 | 18232 | "movlhps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18233 | [(set_attr "type" "ssecvt") |
18234 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18235 | |
18236 | (define_insn "sse_movhps" | |
18237 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
18238 | (vec_merge:V4SF | |
18239 | (match_operand:V4SF 1 "nonimmediate_operand" "0,0") | |
18240 | (match_operand:V4SF 2 "nonimmediate_operand" "m,x") | |
18241 | (const_int 12)))] | |
e37af218 RH |
18242 | "TARGET_SSE |
18243 | && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" | |
0f40f9f7 | 18244 | "movhps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18245 | [(set_attr "type" "ssecvt") |
18246 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18247 | |
18248 | (define_insn "sse_movlps" | |
18249 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m") | |
18250 | (vec_merge:V4SF | |
18251 | (match_operand:V4SF 1 "nonimmediate_operand" "0,0") | |
18252 | (match_operand:V4SF 2 "nonimmediate_operand" "m,x") | |
18253 | (const_int 3)))] | |
e37af218 RH |
18254 | "TARGET_SSE |
18255 | && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" | |
0f40f9f7 | 18256 | "movlps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18257 | [(set_attr "type" "ssecvt") |
18258 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18259 | |
18260 | (define_insn "sse_loadss" | |
18261 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18262 | (vec_merge:V4SF | |
18263 | (match_operand:V4SF 1 "memory_operand" "m") | |
18264 | (vec_duplicate:V4SF (float:SF (const_int 0))) | |
18265 | (const_int 1)))] | |
18266 | "TARGET_SSE" | |
0f40f9f7 | 18267 | "movss\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18268 | [(set_attr "type" "ssemov") |
18269 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18270 | |
18271 | (define_insn "sse_movss" | |
18272 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18273 | (vec_merge:V4SF | |
18274 | (match_operand:V4SF 1 "register_operand" "0") | |
18275 | (match_operand:V4SF 2 "register_operand" "x") | |
18276 | (const_int 1)))] | |
18277 | "TARGET_SSE" | |
0f40f9f7 | 18278 | "movss\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18279 | [(set_attr "type" "ssemov") |
18280 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18281 | |
18282 | (define_insn "sse_storess" | |
18283 | [(set (match_operand:SF 0 "memory_operand" "=m") | |
18284 | (vec_select:SF | |
18285 | (match_operand:V4SF 1 "register_operand" "x") | |
18286 | (parallel [(const_int 0)])))] | |
18287 | "TARGET_SSE" | |
0f40f9f7 | 18288 | "movss\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18289 | [(set_attr "type" "ssemov") |
18290 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18291 | |
18292 | (define_insn "sse_shufps" | |
18293 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18294 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") | |
18295 | (match_operand:V4SF 2 "nonimmediate_operand" "xm") | |
8ee41eaf RH |
18296 | (match_operand:SI 3 "immediate_operand" "i")] |
18297 | UNSPEC_SHUFFLE))] | |
915119a5 BS |
18298 | "TARGET_SSE" |
18299 | ;; @@@ check operand order for intel/nonintel syntax | |
0f40f9f7 | 18300 | "shufps\t{%3, %2, %0|%0, %2, %3}" |
3d34cd91 JH |
18301 | [(set_attr "type" "ssecvt") |
18302 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18303 | |
18304 | ||
18305 | ;; SSE arithmetic | |
18306 | ||
18307 | (define_insn "addv4sf3" | |
18308 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18309 | (plus:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18310 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18311 | "TARGET_SSE" | |
0f40f9f7 | 18312 | "addps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18313 | [(set_attr "type" "sseadd") |
18314 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18315 | |
18316 | (define_insn "vmaddv4sf3" | |
18317 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 RH |
18318 | (vec_merge:V4SF |
18319 | (plus:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18320 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18321 | (match_dup 1) | |
18322 | (const_int 1)))] | |
915119a5 | 18323 | "TARGET_SSE" |
0f40f9f7 | 18324 | "addss\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18325 | [(set_attr "type" "sseadd") |
18326 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18327 | |
18328 | (define_insn "subv4sf3" | |
18329 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18330 | (minus:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
e37af218 | 18331 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] |
915119a5 | 18332 | "TARGET_SSE" |
0f40f9f7 | 18333 | "subps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18334 | [(set_attr "type" "sseadd") |
18335 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18336 | |
18337 | (define_insn "vmsubv4sf3" | |
18338 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 RH |
18339 | (vec_merge:V4SF |
18340 | (minus:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18341 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18342 | (match_dup 1) | |
18343 | (const_int 1)))] | |
915119a5 | 18344 | "TARGET_SSE" |
0f40f9f7 | 18345 | "subss\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18346 | [(set_attr "type" "sseadd") |
18347 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18348 | |
18349 | (define_insn "mulv4sf3" | |
18350 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18351 | (mult:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18352 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18353 | "TARGET_SSE" | |
0f40f9f7 | 18354 | "mulps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18355 | [(set_attr "type" "ssemul") |
18356 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18357 | |
18358 | (define_insn "vmmulv4sf3" | |
18359 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 RH |
18360 | (vec_merge:V4SF |
18361 | (mult:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18362 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18363 | (match_dup 1) | |
18364 | (const_int 1)))] | |
915119a5 | 18365 | "TARGET_SSE" |
0f40f9f7 | 18366 | "mulss\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18367 | [(set_attr "type" "ssemul") |
18368 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18369 | |
18370 | (define_insn "divv4sf3" | |
18371 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18372 | (div:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18373 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18374 | "TARGET_SSE" | |
0f40f9f7 | 18375 | "divps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18376 | [(set_attr "type" "ssediv") |
18377 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18378 | |
18379 | (define_insn "vmdivv4sf3" | |
18380 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 RH |
18381 | (vec_merge:V4SF |
18382 | (div:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18383 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18384 | (match_dup 1) | |
18385 | (const_int 1)))] | |
915119a5 | 18386 | "TARGET_SSE" |
0f40f9f7 | 18387 | "divss\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18388 | [(set_attr "type" "ssediv") |
18389 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18390 | |
18391 | ||
18392 | ;; SSE square root/reciprocal | |
18393 | ||
18394 | (define_insn "rcpv4sf2" | |
18395 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 | 18396 | (unspec:V4SF |
8ee41eaf | 18397 | [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))] |
915119a5 | 18398 | "TARGET_SSE" |
0f40f9f7 | 18399 | "rcpps\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18400 | [(set_attr "type" "sse") |
18401 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18402 | |
18403 | (define_insn "vmrcpv4sf2" | |
18404 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 | 18405 | (vec_merge:V4SF |
8ee41eaf RH |
18406 | (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] |
18407 | UNSPEC_RCP) | |
e37af218 RH |
18408 | (match_operand:V4SF 2 "register_operand" "0") |
18409 | (const_int 1)))] | |
915119a5 | 18410 | "TARGET_SSE" |
0f40f9f7 | 18411 | "rcpss\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18412 | [(set_attr "type" "sse") |
18413 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18414 | |
18415 | (define_insn "rsqrtv4sf2" | |
18416 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 | 18417 | (unspec:V4SF |
8ee41eaf | 18418 | [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))] |
915119a5 | 18419 | "TARGET_SSE" |
0f40f9f7 | 18420 | "rsqrtps\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18421 | [(set_attr "type" "sse") |
18422 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18423 | |
18424 | (define_insn "vmrsqrtv4sf2" | |
18425 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 | 18426 | (vec_merge:V4SF |
8ee41eaf RH |
18427 | (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] |
18428 | UNSPEC_RSQRT) | |
e37af218 RH |
18429 | (match_operand:V4SF 2 "register_operand" "0") |
18430 | (const_int 1)))] | |
915119a5 | 18431 | "TARGET_SSE" |
0f40f9f7 | 18432 | "rsqrtss\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18433 | [(set_attr "type" "sse") |
18434 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18435 | |
18436 | (define_insn "sqrtv4sf2" | |
18437 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 | 18438 | (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))] |
915119a5 | 18439 | "TARGET_SSE" |
0f40f9f7 | 18440 | "sqrtps\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18441 | [(set_attr "type" "sse") |
18442 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18443 | |
18444 | (define_insn "vmsqrtv4sf2" | |
18445 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 RH |
18446 | (vec_merge:V4SF |
18447 | (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")) | |
18448 | (match_operand:V4SF 2 "register_operand" "0") | |
18449 | (const_int 1)))] | |
915119a5 | 18450 | "TARGET_SSE" |
0f40f9f7 | 18451 | "sqrtss\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18452 | [(set_attr "type" "sse") |
18453 | (set_attr "mode" "SF")]) | |
915119a5 | 18454 | |
915119a5 BS |
18455 | ;; SSE logical operations. |
18456 | ||
18457 | ;; These are not called andti3 etc. because we really really don't want | |
18458 | ;; the compiler to widen DImode ands to TImode ands and then try to move | |
18459 | ;; into DImode subregs of SSE registers, and them together, and move out | |
18460 | ;; of DImode subregs again! | |
18461 | ||
c679d048 JH |
18462 | (define_insn "*sse_andti3_df_1" |
18463 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18464 | (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0) | |
18465 | (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))] | |
18466 | "TARGET_SSE2" | |
0f40f9f7 | 18467 | "andpd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18468 | [(set_attr "type" "sselog") |
18469 | (set_attr "mode" "V2DF")]) | |
c679d048 JH |
18470 | |
18471 | (define_insn "*sse_andti3_df_2" | |
18472 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18473 | (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0) | |
18474 | (match_operand:TI 2 "nonimmediate_operand" "Ym")))] | |
18475 | "TARGET_SSE2" | |
0f40f9f7 | 18476 | "andpd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18477 | [(set_attr "type" "sselog") |
18478 | (set_attr "mode" "V2DF")]) | |
c679d048 JH |
18479 | |
18480 | (define_insn "*sse_andti3_sf_1" | |
18481 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18482 | (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0) | |
18483 | (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))] | |
18484 | "TARGET_SSE" | |
0f40f9f7 | 18485 | "andps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18486 | [(set_attr "type" "sselog") |
18487 | (set_attr "mode" "V4SF")]) | |
c679d048 JH |
18488 | |
18489 | (define_insn "*sse_andti3_sf_2" | |
18490 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18491 | (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0) | |
18492 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18493 | "TARGET_SSE" | |
0f40f9f7 | 18494 | "andps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18495 | [(set_attr "type" "sselog") |
18496 | (set_attr "mode" "V4SF")]) | |
c679d048 | 18497 | |
915119a5 BS |
18498 | (define_insn "sse_andti3" |
18499 | [(set (match_operand:TI 0 "register_operand" "=x") | |
558740bf | 18500 | (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
915119a5 | 18501 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
558740bf JH |
18502 | "TARGET_SSE && !TARGET_SSE2 |
18503 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 18504 | "andps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18505 | [(set_attr "type" "sselog") |
18506 | (set_attr "mode" "V4SF")]) | |
915119a5 | 18507 | |
fbe5eb6d | 18508 | (define_insn "sse2_andti3" |
c679d048 | 18509 | [(set (match_operand:TI 0 "register_operand" "=x") |
558740bf | 18510 | (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
c679d048 | 18511 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
558740bf JH |
18512 | "TARGET_SSE2 |
18513 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 18514 | "pand\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18515 | [(set_attr "type" "sselog") |
18516 | (set_attr "mode" "TI")]) | |
c679d048 | 18517 | |
916b60b7 BS |
18518 | (define_insn "sse2_andv2di3" |
18519 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
18520 | (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0") | |
18521 | (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] | |
18522 | "TARGET_SSE2 | |
18523 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
18524 | "pand\t{%2, %0|%0, %2}" | |
5f90a099 JH |
18525 | [(set_attr "type" "sselog") |
18526 | (set_attr "mode" "TI")]) | |
916b60b7 | 18527 | |
c679d048 JH |
18528 | (define_insn "*sse_nandti3_df" |
18529 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18530 | (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)) | |
18531 | (match_operand:TI 2 "nonimmediate_operand" "Ym")))] | |
18532 | "TARGET_SSE2" | |
0f40f9f7 | 18533 | "andnpd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18534 | [(set_attr "type" "sselog") |
18535 | (set_attr "mode" "V2DF")]) | |
c679d048 JH |
18536 | |
18537 | (define_insn "*sse_nandti3_sf" | |
18538 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18539 | (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)) | |
18540 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18541 | "TARGET_SSE" | |
0f40f9f7 | 18542 | "andnps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18543 | [(set_attr "type" "sselog") |
18544 | (set_attr "mode" "V4SF")]) | |
c679d048 | 18545 | |
915119a5 BS |
18546 | (define_insn "sse_nandti3" |
18547 | [(set (match_operand:TI 0 "register_operand" "=x") | |
18548 | (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) | |
18549 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
c679d048 | 18550 | "TARGET_SSE && !TARGET_SSE2" |
0f40f9f7 | 18551 | "andnps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18552 | [(set_attr "type" "sselog") |
18553 | (set_attr "mode" "V4SF")]) | |
915119a5 | 18554 | |
fbe5eb6d | 18555 | (define_insn "sse2_nandti3" |
c679d048 JH |
18556 | [(set (match_operand:TI 0 "register_operand" "=x") |
18557 | (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) | |
18558 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18559 | "TARGET_SSE2" | |
fbe5eb6d | 18560 | "pandn\t{%2, %0|%0, %2}" |
5f90a099 JH |
18561 | [(set_attr "type" "sselog") |
18562 | (set_attr "mode" "TI")]) | |
c679d048 | 18563 | |
916b60b7 BS |
18564 | (define_insn "sse2_nandv2di3" |
18565 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
18566 | (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")) | |
18567 | (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] | |
18568 | "TARGET_SSE2 | |
18569 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
18570 | "pandn\t{%2, %0|%0, %2}" | |
5f90a099 JH |
18571 | [(set_attr "type" "sselog") |
18572 | (set_attr "mode" "TI")]) | |
916b60b7 | 18573 | |
c679d048 JH |
18574 | (define_insn "*sse_iorti3_df_1" |
18575 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18576 | (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0) | |
18577 | (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))] | |
18578 | "TARGET_SSE2" | |
0f40f9f7 | 18579 | "orpd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18580 | [(set_attr "type" "sselog") |
18581 | (set_attr "mode" "V2DF")]) | |
c679d048 JH |
18582 | |
18583 | (define_insn "*sse_iorti3_df_2" | |
18584 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18585 | (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0) | |
18586 | (match_operand:TI 2 "nonimmediate_operand" "Ym")))] | |
18587 | "TARGET_SSE2" | |
0f40f9f7 | 18588 | "orpd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18589 | [(set_attr "type" "sselog") |
18590 | (set_attr "mode" "V2DF")]) | |
c679d048 JH |
18591 | |
18592 | (define_insn "*sse_iorti3_sf_1" | |
18593 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18594 | (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0) | |
18595 | (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))] | |
18596 | "TARGET_SSE" | |
0f40f9f7 | 18597 | "orps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18598 | [(set_attr "type" "sselog") |
18599 | (set_attr "mode" "V4SF")]) | |
c679d048 JH |
18600 | |
18601 | (define_insn "*sse_iorti3_sf_2" | |
18602 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18603 | (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0) | |
18604 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] | |
18605 | "TARGET_SSE" | |
0f40f9f7 | 18606 | "orps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18607 | [(set_attr "type" "sselog") |
18608 | (set_attr "mode" "V4SF")]) | |
c679d048 | 18609 | |
915119a5 BS |
18610 | (define_insn "sse_iorti3" |
18611 | [(set (match_operand:TI 0 "register_operand" "=x") | |
558740bf | 18612 | (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
c679d048 | 18613 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
558740bf JH |
18614 | "TARGET_SSE && !TARGET_SSE2 |
18615 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 18616 | "orps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18617 | [(set_attr "type" "sselog") |
18618 | (set_attr "mode" "V4SF")]) | |
c679d048 | 18619 | |
fbe5eb6d | 18620 | (define_insn "sse2_iorti3" |
c679d048 | 18621 | [(set (match_operand:TI 0 "register_operand" "=x") |
558740bf | 18622 | (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
c679d048 | 18623 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
558740bf JH |
18624 | "TARGET_SSE2 |
18625 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 18626 | "por\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18627 | [(set_attr "type" "sselog") |
18628 | (set_attr "mode" "TI")]) | |
c679d048 | 18629 | |
916b60b7 BS |
18630 | (define_insn "sse2_iorv2di3" |
18631 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
18632 | (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0") | |
18633 | (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] | |
18634 | "TARGET_SSE2 | |
18635 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
18636 | "por\t{%2, %0|%0, %2}" | |
5f90a099 JH |
18637 | [(set_attr "type" "sselog") |
18638 | (set_attr "mode" "TI")]) | |
916b60b7 | 18639 | |
c679d048 JH |
18640 | (define_insn "*sse_xorti3_df_1" |
18641 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18642 | (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0) | |
18643 | (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))] | |
18644 | "TARGET_SSE2" | |
0f40f9f7 | 18645 | "xorpd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18646 | [(set_attr "type" "sselog") |
18647 | (set_attr "mode" "V2DF")]) | |
c679d048 JH |
18648 | |
18649 | (define_insn "*sse_xorti3_df_2" | |
18650 | [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) | |
18651 | (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0) | |
18652 | (match_operand:TI 2 "nonimmediate_operand" "Ym")))] | |
18653 | "TARGET_SSE2" | |
0f40f9f7 | 18654 | "xorpd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18655 | [(set_attr "type" "sselog") |
18656 | (set_attr "mode" "V2DF")]) | |
c679d048 JH |
18657 | |
18658 | (define_insn "*sse_xorti3_sf_1" | |
18659 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18660 | (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0) | |
18661 | (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))] | |
18662 | "TARGET_SSE" | |
0f40f9f7 | 18663 | "xorps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18664 | [(set_attr "type" "sselog") |
18665 | (set_attr "mode" "V4SF")]) | |
c679d048 JH |
18666 | |
18667 | (define_insn "*sse_xorti3_sf_2" | |
18668 | [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) | |
18669 | (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0) | |
915119a5 BS |
18670 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
18671 | "TARGET_SSE" | |
0f40f9f7 | 18672 | "xorps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18673 | [(set_attr "type" "sselog") |
18674 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18675 | |
18676 | (define_insn "sse_xorti3" | |
18677 | [(set (match_operand:TI 0 "register_operand" "=x") | |
558740bf | 18678 | (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
915119a5 | 18679 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
558740bf JH |
18680 | "TARGET_SSE && !TARGET_SSE2 |
18681 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 18682 | "xorps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18683 | [(set_attr "type" "sselog") |
18684 | (set_attr "mode" "V4SF")]) | |
915119a5 | 18685 | |
fbe5eb6d | 18686 | (define_insn "sse2_xorti3" |
c679d048 | 18687 | [(set (match_operand:TI 0 "register_operand" "=x") |
558740bf | 18688 | (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
c679d048 | 18689 | (match_operand:TI 2 "nonimmediate_operand" "xm")))] |
558740bf JH |
18690 | "TARGET_SSE2 |
18691 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
0f40f9f7 | 18692 | "pxor\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18693 | [(set_attr "type" "sselog") |
18694 | (set_attr "mode" "TI")]) | |
c679d048 | 18695 | |
916b60b7 BS |
18696 | (define_insn "sse2_xorv2di3" |
18697 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
18698 | (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0") | |
18699 | (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] | |
18700 | "TARGET_SSE2 | |
18701 | && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" | |
18702 | "pxor\t{%2, %0|%0, %2}" | |
5f90a099 JH |
18703 | [(set_attr "type" "sselog") |
18704 | (set_attr "mode" "TI")]) | |
916b60b7 | 18705 | |
915119a5 BS |
18706 | ;; Use xor, but don't show input operands so they aren't live before |
18707 | ;; this insn. | |
e37af218 RH |
18708 | (define_insn "sse_clrv4sf" |
18709 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
8ee41eaf | 18710 | (unspec:V4SF [(const_int 0)] UNSPEC_NOP))] |
915119a5 | 18711 | "TARGET_SSE" |
0f40f9f7 | 18712 | "xorps\t{%0, %0|%0, %0}" |
3d34cd91 | 18713 | [(set_attr "type" "sselog") |
19cba4a0 | 18714 | (set_attr "memory" "none") |
3d34cd91 | 18715 | (set_attr "mode" "V4SF")]) |
915119a5 BS |
18716 | |
18717 | ;; SSE mask-generating compares | |
18718 | ||
18719 | (define_insn "maskcmpv4sf3" | |
18720 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
18721 | (match_operator:V4SI 3 "sse_comparison_operator" | |
e37af218 RH |
18722 | [(match_operand:V4SF 1 "register_operand" "0") |
18723 | (match_operand:V4SF 2 "register_operand" "x")]))] | |
915119a5 | 18724 | "TARGET_SSE" |
0f40f9f7 | 18725 | "cmp%D3ps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18726 | [(set_attr "type" "ssecmp") |
18727 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18728 | |
18729 | (define_insn "maskncmpv4sf3" | |
18730 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
18731 | (not:V4SI | |
18732 | (match_operator:V4SI 3 "sse_comparison_operator" | |
e37af218 RH |
18733 | [(match_operand:V4SF 1 "register_operand" "0") |
18734 | (match_operand:V4SF 2 "register_operand" "x")])))] | |
915119a5 | 18735 | "TARGET_SSE" |
29628f27 BS |
18736 | { |
18737 | if (GET_CODE (operands[3]) == UNORDERED) | |
e37af218 RH |
18738 | return "cmpordps\t{%2, %0|%0, %2}"; |
18739 | else | |
18740 | return "cmpn%D3ps\t{%2, %0|%0, %2}"; | |
18741 | } | |
3d34cd91 JH |
18742 | [(set_attr "type" "ssecmp") |
18743 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18744 | |
18745 | (define_insn "vmmaskcmpv4sf3" | |
18746 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
18747 | (vec_merge:V4SI | |
18748 | (match_operator:V4SI 3 "sse_comparison_operator" | |
e37af218 RH |
18749 | [(match_operand:V4SF 1 "register_operand" "0") |
18750 | (match_operand:V4SF 2 "register_operand" "x")]) | |
915119a5 BS |
18751 | (match_dup 1) |
18752 | (const_int 1)))] | |
18753 | "TARGET_SSE" | |
0f40f9f7 | 18754 | "cmp%D3ss\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18755 | [(set_attr "type" "ssecmp") |
18756 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18757 | |
18758 | (define_insn "vmmaskncmpv4sf3" | |
18759 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
18760 | (vec_merge:V4SI | |
18761 | (not:V4SI | |
18762 | (match_operator:V4SI 3 "sse_comparison_operator" | |
e37af218 RH |
18763 | [(match_operand:V4SF 1 "register_operand" "0") |
18764 | (match_operand:V4SF 2 "register_operand" "x")])) | |
915119a5 BS |
18765 | (subreg:V4SI (match_dup 1) 0) |
18766 | (const_int 1)))] | |
18767 | "TARGET_SSE" | |
29628f27 BS |
18768 | { |
18769 | if (GET_CODE (operands[3]) == UNORDERED) | |
e37af218 RH |
18770 | return "cmpordss\t{%2, %0|%0, %2}"; |
18771 | else | |
18772 | return "cmpn%D3ss\t{%2, %0|%0, %2}"; | |
18773 | } | |
3d34cd91 JH |
18774 | [(set_attr "type" "ssecmp") |
18775 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18776 | |
18777 | (define_insn "sse_comi" | |
18778 | [(set (reg:CCFP 17) | |
18779 | (match_operator:CCFP 2 "sse_comparison_operator" | |
18780 | [(vec_select:SF | |
18781 | (match_operand:V4SF 0 "register_operand" "x") | |
18782 | (parallel [(const_int 0)])) | |
18783 | (vec_select:SF | |
18784 | (match_operand:V4SF 1 "register_operand" "x") | |
18785 | (parallel [(const_int 0)]))]))] | |
18786 | "TARGET_SSE" | |
21e1b5f1 | 18787 | "comiss\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18788 | [(set_attr "type" "ssecmp") |
18789 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18790 | |
18791 | (define_insn "sse_ucomi" | |
18792 | [(set (reg:CCFPU 17) | |
18793 | (match_operator:CCFPU 2 "sse_comparison_operator" | |
18794 | [(vec_select:SF | |
18795 | (match_operand:V4SF 0 "register_operand" "x") | |
18796 | (parallel [(const_int 0)])) | |
18797 | (vec_select:SF | |
18798 | (match_operand:V4SF 1 "register_operand" "x") | |
18799 | (parallel [(const_int 0)]))]))] | |
18800 | "TARGET_SSE" | |
21e1b5f1 | 18801 | "ucomiss\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18802 | [(set_attr "type" "ssecmp") |
18803 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18804 | |
18805 | ||
18806 | ;; SSE unpack | |
18807 | ||
18808 | (define_insn "sse_unpckhps" | |
18809 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18810 | (vec_merge:V4SF | |
18811 | (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18812 | (parallel [(const_int 2) | |
18813 | (const_int 0) | |
18814 | (const_int 3) | |
18815 | (const_int 1)])) | |
21e1b5f1 | 18816 | (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") |
915119a5 BS |
18817 | (parallel [(const_int 0) |
18818 | (const_int 2) | |
18819 | (const_int 1) | |
18820 | (const_int 3)])) | |
18821 | (const_int 5)))] | |
18822 | "TARGET_SSE" | |
0f40f9f7 | 18823 | "unpckhps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18824 | [(set_attr "type" "ssecvt") |
18825 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18826 | |
18827 | (define_insn "sse_unpcklps" | |
18828 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18829 | (vec_merge:V4SF | |
18830 | (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18831 | (parallel [(const_int 0) | |
18832 | (const_int 2) | |
18833 | (const_int 1) | |
18834 | (const_int 3)])) | |
21e1b5f1 | 18835 | (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x") |
915119a5 BS |
18836 | (parallel [(const_int 2) |
18837 | (const_int 0) | |
18838 | (const_int 3) | |
18839 | (const_int 1)])) | |
18840 | (const_int 5)))] | |
18841 | "TARGET_SSE" | |
0f40f9f7 | 18842 | "unpcklps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18843 | [(set_attr "type" "ssecvt") |
18844 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18845 | |
18846 | ||
18847 | ;; SSE min/max | |
18848 | ||
18849 | (define_insn "smaxv4sf3" | |
18850 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18851 | (smax:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18852 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18853 | "TARGET_SSE" | |
0f40f9f7 | 18854 | "maxps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18855 | [(set_attr "type" "sse") |
18856 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18857 | |
18858 | (define_insn "vmsmaxv4sf3" | |
18859 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 RH |
18860 | (vec_merge:V4SF |
18861 | (smax:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18862 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18863 | (match_dup 1) | |
18864 | (const_int 1)))] | |
915119a5 | 18865 | "TARGET_SSE" |
0f40f9f7 | 18866 | "maxss\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18867 | [(set_attr "type" "sse") |
18868 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18869 | |
18870 | (define_insn "sminv4sf3" | |
18871 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
18872 | (smin:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18873 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] | |
18874 | "TARGET_SSE" | |
0f40f9f7 | 18875 | "minps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18876 | [(set_attr "type" "sse") |
18877 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18878 | |
18879 | (define_insn "vmsminv4sf3" | |
18880 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 RH |
18881 | (vec_merge:V4SF |
18882 | (smin:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
18883 | (match_operand:V4SF 2 "nonimmediate_operand" "xm")) | |
18884 | (match_dup 1) | |
18885 | (const_int 1)))] | |
915119a5 | 18886 | "TARGET_SSE" |
0f40f9f7 | 18887 | "minss\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18888 | [(set_attr "type" "sse") |
18889 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18890 | |
18891 | ||
18892 | ;; SSE <-> integer/MMX conversions | |
18893 | ||
18894 | (define_insn "cvtpi2ps" | |
18895 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 RH |
18896 | (vec_merge:V4SF |
18897 | (match_operand:V4SF 1 "register_operand" "0") | |
18898 | (vec_duplicate:V4SF | |
18899 | (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym"))) | |
18900 | (const_int 12)))] | |
915119a5 | 18901 | "TARGET_SSE" |
0f40f9f7 | 18902 | "cvtpi2ps\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18903 | [(set_attr "type" "ssecvt") |
18904 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18905 | |
18906 | (define_insn "cvtps2pi" | |
18907 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
e37af218 RH |
18908 | (vec_select:V2SI |
18909 | (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")) | |
18910 | (parallel [(const_int 0) (const_int 1)])))] | |
915119a5 | 18911 | "TARGET_SSE" |
0f40f9f7 | 18912 | "cvtps2pi\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18913 | [(set_attr "type" "ssecvt") |
18914 | (set_attr "mode" "V4SF")]) | |
915119a5 BS |
18915 | |
18916 | (define_insn "cvttps2pi" | |
18917 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
e37af218 | 18918 | (vec_select:V2SI |
8ee41eaf RH |
18919 | (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] |
18920 | UNSPEC_FIX) | |
e37af218 | 18921 | (parallel [(const_int 0) (const_int 1)])))] |
915119a5 | 18922 | "TARGET_SSE" |
0f40f9f7 | 18923 | "cvttps2pi\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18924 | [(set_attr "type" "ssecvt") |
18925 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18926 | |
18927 | (define_insn "cvtsi2ss" | |
18928 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
e37af218 RH |
18929 | (vec_merge:V4SF |
18930 | (match_operand:V4SF 1 "register_operand" "0") | |
18931 | (vec_duplicate:V4SF | |
18932 | (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
18933 | (const_int 14)))] | |
915119a5 | 18934 | "TARGET_SSE" |
0f40f9f7 | 18935 | "cvtsi2ss\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18936 | [(set_attr "type" "ssecvt") |
18937 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18938 | |
18939 | (define_insn "cvtss2si" | |
21e1b5f1 | 18940 | [(set (match_operand:SI 0 "register_operand" "=r") |
e37af218 RH |
18941 | (vec_select:SI |
18942 | (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")) | |
18943 | (parallel [(const_int 0)])))] | |
915119a5 | 18944 | "TARGET_SSE" |
0f40f9f7 | 18945 | "cvtss2si\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18946 | [(set_attr "type" "ssecvt") |
18947 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18948 | |
18949 | (define_insn "cvttss2si" | |
21e1b5f1 | 18950 | [(set (match_operand:SI 0 "register_operand" "=r") |
e37af218 | 18951 | (vec_select:SI |
8ee41eaf RH |
18952 | (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] |
18953 | UNSPEC_FIX) | |
e37af218 | 18954 | (parallel [(const_int 0)])))] |
915119a5 | 18955 | "TARGET_SSE" |
0f40f9f7 | 18956 | "cvttss2si\t{%1, %0|%0, %1}" |
3d34cd91 JH |
18957 | [(set_attr "type" "ssecvt") |
18958 | (set_attr "mode" "SF")]) | |
915119a5 BS |
18959 | |
18960 | ||
18961 | ;; MMX insns | |
18962 | ||
18963 | ;; MMX arithmetic | |
18964 | ||
18965 | (define_insn "addv8qi3" | |
18966 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
18967 | (plus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
18968 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
18969 | "TARGET_MMX" | |
0f40f9f7 | 18970 | "paddb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18971 | [(set_attr "type" "mmxadd") |
18972 | (set_attr "mode" "DI")]) | |
915119a5 BS |
18973 | |
18974 | (define_insn "addv4hi3" | |
18975 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
18976 | (plus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
18977 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
18978 | "TARGET_MMX" | |
0f40f9f7 | 18979 | "paddw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18980 | [(set_attr "type" "mmxadd") |
18981 | (set_attr "mode" "DI")]) | |
915119a5 BS |
18982 | |
18983 | (define_insn "addv2si3" | |
18984 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
18985 | (plus:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
18986 | (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] | |
18987 | "TARGET_MMX" | |
0f40f9f7 | 18988 | "paddd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18989 | [(set_attr "type" "mmxadd") |
18990 | (set_attr "mode" "DI")]) | |
915119a5 BS |
18991 | |
18992 | (define_insn "ssaddv8qi3" | |
18993 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
18994 | (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
18995 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
18996 | "TARGET_MMX" | |
0f40f9f7 | 18997 | "paddsb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
18998 | [(set_attr "type" "mmxadd") |
18999 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19000 | |
19001 | (define_insn "ssaddv4hi3" | |
19002 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19003 | (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19004 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19005 | "TARGET_MMX" | |
0f40f9f7 | 19006 | "paddsw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19007 | [(set_attr "type" "mmxadd") |
19008 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19009 | |
19010 | (define_insn "usaddv8qi3" | |
19011 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19012 | (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19013 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
19014 | "TARGET_MMX" | |
0f40f9f7 | 19015 | "paddusb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19016 | [(set_attr "type" "mmxadd") |
19017 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19018 | |
19019 | (define_insn "usaddv4hi3" | |
19020 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19021 | (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19022 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19023 | "TARGET_MMX" | |
0f40f9f7 | 19024 | "paddusw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19025 | [(set_attr "type" "mmxadd") |
19026 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19027 | |
19028 | (define_insn "subv8qi3" | |
19029 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19030 | (minus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19031 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
19032 | "TARGET_MMX" | |
0f40f9f7 | 19033 | "psubb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19034 | [(set_attr "type" "mmxadd") |
19035 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19036 | |
19037 | (define_insn "subv4hi3" | |
19038 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19039 | (minus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19040 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19041 | "TARGET_MMX" | |
0f40f9f7 | 19042 | "psubw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19043 | [(set_attr "type" "mmxadd") |
19044 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19045 | |
19046 | (define_insn "subv2si3" | |
19047 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19048 | (minus:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19049 | (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] | |
19050 | "TARGET_MMX" | |
0f40f9f7 | 19051 | "psubd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19052 | [(set_attr "type" "mmxadd") |
19053 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19054 | |
19055 | (define_insn "sssubv8qi3" | |
19056 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19057 | (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19058 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
19059 | "TARGET_MMX" | |
0f40f9f7 | 19060 | "psubsb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19061 | [(set_attr "type" "mmxadd") |
19062 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19063 | |
19064 | (define_insn "sssubv4hi3" | |
19065 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19066 | (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19067 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19068 | "TARGET_MMX" | |
0f40f9f7 | 19069 | "psubsw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19070 | [(set_attr "type" "mmxadd") |
19071 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19072 | |
19073 | (define_insn "ussubv8qi3" | |
19074 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19075 | (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19076 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
19077 | "TARGET_MMX" | |
0f40f9f7 | 19078 | "psubusb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19079 | [(set_attr "type" "mmxadd") |
19080 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19081 | |
19082 | (define_insn "ussubv4hi3" | |
19083 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19084 | (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19085 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19086 | "TARGET_MMX" | |
0f40f9f7 | 19087 | "psubusw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19088 | [(set_attr "type" "mmxadd") |
19089 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19090 | |
19091 | (define_insn "mulv4hi3" | |
19092 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19093 | (mult:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19094 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19095 | "TARGET_MMX" | |
0f40f9f7 | 19096 | "pmullw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19097 | [(set_attr "type" "mmxmul") |
19098 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19099 | |
19100 | (define_insn "smulv4hi3_highpart" | |
19101 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19102 | (truncate:V4HI | |
19103 | (lshiftrt:V4SI | |
e37af218 RH |
19104 | (mult:V4SI (sign_extend:V4SI |
19105 | (match_operand:V4HI 1 "register_operand" "0")) | |
19106 | (sign_extend:V4SI | |
19107 | (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
915119a5 BS |
19108 | (const_int 16))))] |
19109 | "TARGET_MMX" | |
0f40f9f7 | 19110 | "pmulhw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19111 | [(set_attr "type" "mmxmul") |
19112 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19113 | |
19114 | (define_insn "umulv4hi3_highpart" | |
19115 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19116 | (truncate:V4HI | |
19117 | (lshiftrt:V4SI | |
e37af218 RH |
19118 | (mult:V4SI (zero_extend:V4SI |
19119 | (match_operand:V4HI 1 "register_operand" "0")) | |
19120 | (zero_extend:V4SI | |
19121 | (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
915119a5 | 19122 | (const_int 16))))] |
47f339cf | 19123 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19124 | "pmulhuw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19125 | [(set_attr "type" "mmxmul") |
19126 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19127 | |
19128 | (define_insn "mmx_pmaddwd" | |
19129 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19130 | (plus:V2SI | |
19131 | (mult:V2SI | |
e37af218 RH |
19132 | (sign_extend:V2SI |
19133 | (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0") | |
19134 | (parallel [(const_int 0) (const_int 2)]))) | |
19135 | (sign_extend:V2SI | |
19136 | (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym") | |
19137 | (parallel [(const_int 0) (const_int 2)])))) | |
915119a5 BS |
19138 | (mult:V2SI |
19139 | (sign_extend:V2SI (vec_select:V2HI (match_dup 1) | |
19140 | (parallel [(const_int 1) | |
19141 | (const_int 3)]))) | |
19142 | (sign_extend:V2SI (vec_select:V2HI (match_dup 2) | |
19143 | (parallel [(const_int 1) | |
19144 | (const_int 3)]))))))] | |
19145 | "TARGET_MMX" | |
0f40f9f7 | 19146 | "pmaddwd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19147 | [(set_attr "type" "mmxmul") |
19148 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19149 | |
19150 | ||
19151 | ;; MMX logical operations | |
19152 | ;; Note we don't want to declare these as regular iordi3 insns to prevent | |
19153 | ;; normal code that also wants to use the FPU from getting broken. | |
19154 | ;; The UNSPECs are there to prevent the combiner from getting overly clever. | |
19155 | (define_insn "mmx_iordi3" | |
19156 | [(set (match_operand:DI 0 "register_operand" "=y") | |
19157 | (unspec:DI | |
19158 | [(ior:DI (match_operand:DI 1 "register_operand" "0") | |
8ee41eaf RH |
19159 | (match_operand:DI 2 "nonimmediate_operand" "ym"))] |
19160 | UNSPEC_NOP))] | |
915119a5 | 19161 | "TARGET_MMX" |
0f40f9f7 | 19162 | "por\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19163 | [(set_attr "type" "mmxadd") |
19164 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19165 | |
19166 | (define_insn "mmx_xordi3" | |
19167 | [(set (match_operand:DI 0 "register_operand" "=y") | |
19168 | (unspec:DI | |
19169 | [(xor:DI (match_operand:DI 1 "register_operand" "0") | |
8ee41eaf RH |
19170 | (match_operand:DI 2 "nonimmediate_operand" "ym"))] |
19171 | UNSPEC_NOP))] | |
915119a5 | 19172 | "TARGET_MMX" |
0f40f9f7 | 19173 | "pxor\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19174 | [(set_attr "type" "mmxadd") |
19175 | (set_attr "mode" "DI") | |
29628f27 | 19176 | (set_attr "memory" "none")]) |
915119a5 BS |
19177 | |
19178 | ;; Same as pxor, but don't show input operands so that we don't think | |
19179 | ;; they are live. | |
19180 | (define_insn "mmx_clrdi" | |
19181 | [(set (match_operand:DI 0 "register_operand" "=y") | |
8ee41eaf | 19182 | (unspec:DI [(const_int 0)] UNSPEC_NOP))] |
915119a5 | 19183 | "TARGET_MMX" |
0f40f9f7 | 19184 | "pxor\t{%0, %0|%0, %0}" |
3d34cd91 JH |
19185 | [(set_attr "type" "mmxadd") |
19186 | (set_attr "mode" "DI") | |
6f1a6c5b | 19187 | (set_attr "memory" "none")]) |
915119a5 BS |
19188 | |
19189 | (define_insn "mmx_anddi3" | |
19190 | [(set (match_operand:DI 0 "register_operand" "=y") | |
19191 | (unspec:DI | |
19192 | [(and:DI (match_operand:DI 1 "register_operand" "0") | |
8ee41eaf RH |
19193 | (match_operand:DI 2 "nonimmediate_operand" "ym"))] |
19194 | UNSPEC_NOP))] | |
915119a5 | 19195 | "TARGET_MMX" |
0f40f9f7 | 19196 | "pand\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19197 | [(set_attr "type" "mmxadd") |
19198 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19199 | |
19200 | (define_insn "mmx_nanddi3" | |
19201 | [(set (match_operand:DI 0 "register_operand" "=y") | |
19202 | (unspec:DI | |
19203 | [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0")) | |
8ee41eaf RH |
19204 | (match_operand:DI 2 "nonimmediate_operand" "ym"))] |
19205 | UNSPEC_NOP))] | |
915119a5 | 19206 | "TARGET_MMX" |
0f40f9f7 | 19207 | "pandn\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19208 | [(set_attr "type" "mmxadd") |
19209 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19210 | |
19211 | ||
19212 | ;; MMX unsigned averages/sum of absolute differences | |
19213 | ||
19214 | (define_insn "mmx_uavgv8qi3" | |
19215 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19216 | (ashiftrt:V8QI | |
19217 | (plus:V8QI (plus:V8QI | |
19218 | (match_operand:V8QI 1 "register_operand" "0") | |
19219 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")) | |
69ef87e2 AH |
19220 | (const_vector:V8QI [(const_int 1) |
19221 | (const_int 1) | |
19222 | (const_int 1) | |
19223 | (const_int 1) | |
19224 | (const_int 1) | |
19225 | (const_int 1) | |
19226 | (const_int 1) | |
19227 | (const_int 1)])) | |
915119a5 | 19228 | (const_int 1)))] |
47f339cf | 19229 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19230 | "pavgb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19231 | [(set_attr "type" "mmxshft") |
19232 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19233 | |
19234 | (define_insn "mmx_uavgv4hi3" | |
19235 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19236 | (ashiftrt:V4HI | |
19237 | (plus:V4HI (plus:V4HI | |
19238 | (match_operand:V4HI 1 "register_operand" "0") | |
19239 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")) | |
69ef87e2 AH |
19240 | (const_vector:V4HI [(const_int 1) |
19241 | (const_int 1) | |
19242 | (const_int 1) | |
19243 | (const_int 1)])) | |
915119a5 | 19244 | (const_int 1)))] |
47f339cf | 19245 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19246 | "pavgw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19247 | [(set_attr "type" "mmxshft") |
19248 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19249 | |
19250 | (define_insn "mmx_psadbw" | |
916b60b7 BS |
19251 | [(set (match_operand:DI 0 "register_operand" "=y") |
19252 | (unspec:DI [(match_operand:V8QI 1 "register_operand" "0") | |
8ee41eaf RH |
19253 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")] |
19254 | UNSPEC_PSADBW))] | |
47f339cf | 19255 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19256 | "psadbw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19257 | [(set_attr "type" "mmxshft") |
19258 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19259 | |
19260 | ||
19261 | ;; MMX insert/extract/shuffle | |
19262 | ||
19263 | (define_insn "mmx_pinsrw" | |
19264 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19265 | (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19266 | (vec_duplicate:V4HI | |
19267 | (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
19268 | (match_operand:SI 3 "immediate_operand" "i")))] | |
47f339cf | 19269 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19270 | "pinsrw\t{%3, %2, %0|%0, %2, %3}" |
3d34cd91 JH |
19271 | [(set_attr "type" "mmxcvt") |
19272 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19273 | |
19274 | (define_insn "mmx_pextrw" | |
19275 | [(set (match_operand:SI 0 "register_operand" "=r") | |
19276 | (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") | |
19277 | (parallel | |
19278 | [(match_operand:SI 2 "immediate_operand" "i")]))))] | |
47f339cf | 19279 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19280 | "pextrw\t{%2, %1, %0|%0, %1, %2}" |
3d34cd91 JH |
19281 | [(set_attr "type" "mmxcvt") |
19282 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19283 | |
19284 | (define_insn "mmx_pshufw" | |
19285 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19286 | (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0") | |
8ee41eaf RH |
19287 | (match_operand:SI 2 "immediate_operand" "i")] |
19288 | UNSPEC_SHUFFLE))] | |
47f339cf | 19289 | "TARGET_SSE || TARGET_3DNOW_A" |
29628f27 | 19290 | "pshufw\t{%2, %1, %0|%0, %1, %2}" |
3d34cd91 JH |
19291 | [(set_attr "type" "mmxcvt") |
19292 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19293 | |
19294 | ||
19295 | ;; MMX mask-generating comparisons | |
19296 | ||
19297 | (define_insn "eqv8qi3" | |
19298 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19299 | (eq:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19300 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
19301 | "TARGET_MMX" | |
0f40f9f7 | 19302 | "pcmpeqb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19303 | [(set_attr "type" "mmxcmp") |
19304 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19305 | |
19306 | (define_insn "eqv4hi3" | |
19307 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19308 | (eq:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19309 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19310 | "TARGET_MMX" | |
0f40f9f7 | 19311 | "pcmpeqw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19312 | [(set_attr "type" "mmxcmp") |
19313 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19314 | |
19315 | (define_insn "eqv2si3" | |
19316 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19317 | (eq:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19318 | (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] | |
19319 | "TARGET_MMX" | |
0f40f9f7 | 19320 | "pcmpeqd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19321 | [(set_attr "type" "mmxcmp") |
19322 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19323 | |
19324 | (define_insn "gtv8qi3" | |
19325 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19326 | (gt:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19327 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
19328 | "TARGET_MMX" | |
0f40f9f7 | 19329 | "pcmpgtb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19330 | [(set_attr "type" "mmxcmp") |
19331 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19332 | |
19333 | (define_insn "gtv4hi3" | |
19334 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19335 | (gt:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19336 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
19337 | "TARGET_MMX" | |
0f40f9f7 | 19338 | "pcmpgtw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19339 | [(set_attr "type" "mmxcmp") |
19340 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19341 | |
19342 | (define_insn "gtv2si3" | |
19343 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19344 | (gt:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19345 | (match_operand:V2SI 2 "nonimmediate_operand" "ym")))] | |
19346 | "TARGET_MMX" | |
0f40f9f7 | 19347 | "pcmpgtd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19348 | [(set_attr "type" "mmxcmp") |
19349 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19350 | |
19351 | ||
19352 | ;; MMX max/min insns | |
19353 | ||
19354 | (define_insn "umaxv8qi3" | |
19355 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19356 | (umax:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19357 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
47f339cf | 19358 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19359 | "pmaxub\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19360 | [(set_attr "type" "mmxadd") |
19361 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19362 | |
19363 | (define_insn "smaxv4hi3" | |
19364 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19365 | (smax:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19366 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
47f339cf | 19367 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19368 | "pmaxsw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19369 | [(set_attr "type" "mmxadd") |
19370 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19371 | |
19372 | (define_insn "uminv8qi3" | |
19373 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19374 | (umin:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19375 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] | |
47f339cf | 19376 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19377 | "pminub\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19378 | [(set_attr "type" "mmxadd") |
19379 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19380 | |
19381 | (define_insn "sminv4hi3" | |
19382 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19383 | (smin:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19384 | (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] | |
47f339cf | 19385 | "TARGET_SSE || TARGET_3DNOW_A" |
0f40f9f7 | 19386 | "pminsw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19387 | [(set_attr "type" "mmxadd") |
19388 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19389 | |
19390 | ||
19391 | ;; MMX shifts | |
19392 | ||
19393 | (define_insn "ashrv4hi3" | |
19394 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19395 | (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19396 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19397 | "TARGET_MMX" | |
0f40f9f7 | 19398 | "psraw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19399 | [(set_attr "type" "mmxshft") |
19400 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19401 | |
19402 | (define_insn "ashrv2si3" | |
19403 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19404 | (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19405 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19406 | "TARGET_MMX" | |
0f40f9f7 | 19407 | "psrad\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19408 | [(set_attr "type" "mmxshft") |
19409 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19410 | |
19411 | (define_insn "lshrv4hi3" | |
19412 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19413 | (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19414 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19415 | "TARGET_MMX" | |
0f40f9f7 | 19416 | "psrlw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19417 | [(set_attr "type" "mmxshft") |
19418 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19419 | |
19420 | (define_insn "lshrv2si3" | |
19421 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19422 | (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19423 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19424 | "TARGET_MMX" | |
0f40f9f7 | 19425 | "psrld\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19426 | [(set_attr "type" "mmxshft") |
19427 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19428 | |
19429 | ;; See logical MMX insns. | |
19430 | (define_insn "mmx_lshrdi3" | |
19431 | [(set (match_operand:DI 0 "register_operand" "=y") | |
2b71bf37 JH |
19432 | (unspec:DI |
19433 | [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8ee41eaf RH |
19434 | (match_operand:DI 2 "nonmemory_operand" "yi"))] |
19435 | UNSPEC_NOP))] | |
915119a5 | 19436 | "TARGET_MMX" |
0f40f9f7 | 19437 | "psrlq\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19438 | [(set_attr "type" "mmxshft") |
19439 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19440 | |
19441 | (define_insn "ashlv4hi3" | |
19442 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19443 | (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19444 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19445 | "TARGET_MMX" | |
0f40f9f7 | 19446 | "psllw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19447 | [(set_attr "type" "mmxshft") |
19448 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19449 | |
19450 | (define_insn "ashlv2si3" | |
19451 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19452 | (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19453 | (match_operand:DI 2 "nonmemory_operand" "yi")))] | |
19454 | "TARGET_MMX" | |
0f40f9f7 | 19455 | "pslld\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19456 | [(set_attr "type" "mmxshft") |
19457 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19458 | |
19459 | ;; See logical MMX insns. | |
19460 | (define_insn "mmx_ashldi3" | |
19461 | [(set (match_operand:DI 0 "register_operand" "=y") | |
2b71bf37 JH |
19462 | (unspec:DI |
19463 | [(ashift:DI (match_operand:DI 1 "register_operand" "0") | |
8ee41eaf RH |
19464 | (match_operand:DI 2 "nonmemory_operand" "yi"))] |
19465 | UNSPEC_NOP))] | |
915119a5 | 19466 | "TARGET_MMX" |
0f40f9f7 | 19467 | "psllq\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19468 | [(set_attr "type" "mmxshft") |
19469 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19470 | |
19471 | ||
19472 | ;; MMX pack/unpack insns. | |
19473 | ||
19474 | (define_insn "mmx_packsswb" | |
19475 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19476 | (vec_concat:V8QI | |
19477 | (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0")) | |
19478 | (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] | |
19479 | "TARGET_MMX" | |
0f40f9f7 | 19480 | "packsswb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19481 | [(set_attr "type" "mmxshft") |
19482 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19483 | |
19484 | (define_insn "mmx_packssdw" | |
19485 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19486 | (vec_concat:V4HI | |
19487 | (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0")) | |
19488 | (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] | |
19489 | "TARGET_MMX" | |
0f40f9f7 | 19490 | "packssdw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19491 | [(set_attr "type" "mmxshft") |
19492 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19493 | |
19494 | (define_insn "mmx_packuswb" | |
19495 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19496 | (vec_concat:V8QI | |
19497 | (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0")) | |
19498 | (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] | |
19499 | "TARGET_MMX" | |
0f40f9f7 | 19500 | "packuswb\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19501 | [(set_attr "type" "mmxshft") |
19502 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19503 | |
19504 | (define_insn "mmx_punpckhbw" | |
19505 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19506 | (vec_merge:V8QI | |
19507 | (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19508 | (parallel [(const_int 4) | |
19509 | (const_int 0) | |
19510 | (const_int 5) | |
19511 | (const_int 1) | |
19512 | (const_int 6) | |
19513 | (const_int 2) | |
19514 | (const_int 7) | |
19515 | (const_int 3)])) | |
19516 | (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") | |
19517 | (parallel [(const_int 0) | |
19518 | (const_int 4) | |
19519 | (const_int 1) | |
19520 | (const_int 5) | |
19521 | (const_int 2) | |
19522 | (const_int 6) | |
19523 | (const_int 3) | |
19524 | (const_int 7)])) | |
19525 | (const_int 85)))] | |
19526 | "TARGET_MMX" | |
0f40f9f7 | 19527 | "punpckhbw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19528 | [(set_attr "type" "mmxcvt") |
19529 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19530 | |
19531 | (define_insn "mmx_punpckhwd" | |
19532 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19533 | (vec_merge:V4HI | |
19534 | (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19535 | (parallel [(const_int 0) | |
19536 | (const_int 2) | |
19537 | (const_int 1) | |
19538 | (const_int 3)])) | |
19539 | (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") | |
19540 | (parallel [(const_int 2) | |
19541 | (const_int 0) | |
19542 | (const_int 3) | |
19543 | (const_int 1)])) | |
19544 | (const_int 5)))] | |
19545 | "TARGET_MMX" | |
0f40f9f7 | 19546 | "punpckhwd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19547 | [(set_attr "type" "mmxcvt") |
19548 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19549 | |
19550 | (define_insn "mmx_punpckhdq" | |
19551 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19552 | (vec_merge:V2SI | |
19553 | (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19554 | (parallel [(const_int 0) | |
19555 | (const_int 1)])) | |
19556 | (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") | |
19557 | (parallel [(const_int 1) | |
19558 | (const_int 0)])) | |
19559 | (const_int 1)))] | |
19560 | "TARGET_MMX" | |
0f40f9f7 | 19561 | "punpckhdq\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19562 | [(set_attr "type" "mmxcvt") |
19563 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19564 | |
19565 | (define_insn "mmx_punpcklbw" | |
19566 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19567 | (vec_merge:V8QI | |
19568 | (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0") | |
19569 | (parallel [(const_int 0) | |
19570 | (const_int 4) | |
19571 | (const_int 1) | |
19572 | (const_int 5) | |
19573 | (const_int 2) | |
19574 | (const_int 6) | |
19575 | (const_int 3) | |
19576 | (const_int 7)])) | |
19577 | (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") | |
19578 | (parallel [(const_int 4) | |
19579 | (const_int 0) | |
19580 | (const_int 5) | |
19581 | (const_int 1) | |
19582 | (const_int 6) | |
19583 | (const_int 2) | |
19584 | (const_int 7) | |
19585 | (const_int 3)])) | |
19586 | (const_int 85)))] | |
19587 | "TARGET_MMX" | |
0f40f9f7 | 19588 | "punpcklbw\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19589 | [(set_attr "type" "mmxcvt") |
19590 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19591 | |
19592 | (define_insn "mmx_punpcklwd" | |
19593 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
19594 | (vec_merge:V4HI | |
19595 | (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0") | |
19596 | (parallel [(const_int 2) | |
19597 | (const_int 0) | |
19598 | (const_int 3) | |
19599 | (const_int 1)])) | |
19600 | (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") | |
19601 | (parallel [(const_int 0) | |
19602 | (const_int 2) | |
19603 | (const_int 1) | |
19604 | (const_int 3)])) | |
19605 | (const_int 5)))] | |
19606 | "TARGET_MMX" | |
0f40f9f7 | 19607 | "punpcklwd\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19608 | [(set_attr "type" "mmxcvt") |
19609 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19610 | |
19611 | (define_insn "mmx_punpckldq" | |
19612 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19613 | (vec_merge:V2SI | |
19614 | (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0") | |
19615 | (parallel [(const_int 1) | |
19616 | (const_int 0)])) | |
19617 | (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") | |
19618 | (parallel [(const_int 0) | |
19619 | (const_int 1)])) | |
19620 | (const_int 1)))] | |
19621 | "TARGET_MMX" | |
0f40f9f7 | 19622 | "punpckldq\t{%2, %0|%0, %2}" |
3d34cd91 JH |
19623 | [(set_attr "type" "mmxcvt") |
19624 | (set_attr "mode" "DI")]) | |
915119a5 BS |
19625 | |
19626 | ||
19627 | ;; Miscellaneous stuff | |
19628 | ||
19629 | (define_insn "emms" | |
8ee41eaf | 19630 | [(unspec_volatile [(const_int 0)] UNSPECV_EMMS) |
915119a5 BS |
19631 | (clobber (reg:XF 8)) |
19632 | (clobber (reg:XF 9)) | |
19633 | (clobber (reg:XF 10)) | |
19634 | (clobber (reg:XF 11)) | |
19635 | (clobber (reg:XF 12)) | |
19636 | (clobber (reg:XF 13)) | |
19637 | (clobber (reg:XF 14)) | |
19638 | (clobber (reg:XF 15)) | |
915119a5 BS |
19639 | (clobber (reg:DI 29)) |
19640 | (clobber (reg:DI 30)) | |
19641 | (clobber (reg:DI 31)) | |
19642 | (clobber (reg:DI 32)) | |
19643 | (clobber (reg:DI 33)) | |
bd793c65 BS |
19644 | (clobber (reg:DI 34)) |
19645 | (clobber (reg:DI 35)) | |
19646 | (clobber (reg:DI 36))] | |
915119a5 BS |
19647 | "TARGET_MMX" |
19648 | "emms" | |
bd793c65 BS |
19649 | [(set_attr "type" "mmx") |
19650 | (set_attr "memory" "unknown")]) | |
915119a5 BS |
19651 | |
19652 | (define_insn "ldmxcsr" | |
8ee41eaf RH |
19653 | [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] |
19654 | UNSPECV_LDMXCSR)] | |
915119a5 | 19655 | "TARGET_MMX" |
0f40f9f7 | 19656 | "ldmxcsr\t%0" |
29628f27 BS |
19657 | [(set_attr "type" "mmx") |
19658 | (set_attr "memory" "load")]) | |
915119a5 BS |
19659 | |
19660 | (define_insn "stmxcsr" | |
19661 | [(set (match_operand:SI 0 "memory_operand" "=m") | |
8ee41eaf | 19662 | (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))] |
915119a5 | 19663 | "TARGET_MMX" |
0f40f9f7 | 19664 | "stmxcsr\t%0" |
29628f27 BS |
19665 | [(set_attr "type" "mmx") |
19666 | (set_attr "memory" "store")]) | |
915119a5 BS |
19667 | |
19668 | (define_expand "sfence" | |
19669 | [(set (match_dup 0) | |
8ee41eaf | 19670 | (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))] |
47f339cf | 19671 | "TARGET_SSE || TARGET_3DNOW_A" |
915119a5 BS |
19672 | { |
19673 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
19674 | MEM_VOLATILE_P (operands[0]) = 1; | |
0f40f9f7 | 19675 | }) |
915119a5 BS |
19676 | |
19677 | (define_insn "*sfence_insn" | |
19678 | [(set (match_operand:BLK 0 "" "") | |
8ee41eaf | 19679 | (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))] |
47f339cf | 19680 | "TARGET_SSE || TARGET_3DNOW_A" |
915119a5 | 19681 | "sfence" |
bd793c65 BS |
19682 | [(set_attr "type" "sse") |
19683 | (set_attr "memory" "unknown")]) | |
915119a5 | 19684 | |
ad919812 JH |
19685 | (define_expand "sse_prologue_save" |
19686 | [(parallel [(set (match_operand:BLK 0 "" "") | |
19687 | (unspec:BLK [(reg:DI 21) | |
19688 | (reg:DI 22) | |
19689 | (reg:DI 23) | |
19690 | (reg:DI 24) | |
19691 | (reg:DI 25) | |
19692 | (reg:DI 26) | |
19693 | (reg:DI 27) | |
8ee41eaf | 19694 | (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE)) |
ad919812 JH |
19695 | (use (match_operand:DI 1 "register_operand" "")) |
19696 | (use (match_operand:DI 2 "immediate_operand" "")) | |
19697 | (use (label_ref:DI (match_operand 3 "" "")))])] | |
19698 | "TARGET_64BIT" | |
19699 | "") | |
19700 | ||
19701 | (define_insn "*sse_prologue_save_insn" | |
19702 | [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R") | |
19703 | (match_operand:DI 4 "const_int_operand" "n"))) | |
19704 | (unspec:BLK [(reg:DI 21) | |
19705 | (reg:DI 22) | |
19706 | (reg:DI 23) | |
19707 | (reg:DI 24) | |
19708 | (reg:DI 25) | |
19709 | (reg:DI 26) | |
19710 | (reg:DI 27) | |
8ee41eaf | 19711 | (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE)) |
ad919812 JH |
19712 | (use (match_operand:DI 1 "register_operand" "r")) |
19713 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
19714 | (use (label_ref:DI (match_operand 3 "" "X")))] | |
19715 | "TARGET_64BIT | |
19716 | && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128 | |
19717 | && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128" | |
19718 | "* | |
19719 | { | |
19720 | int i; | |
19721 | operands[0] = gen_rtx_MEM (Pmode, | |
19722 | gen_rtx_PLUS (Pmode, operands[0], operands[4])); | |
19723 | output_asm_insn (\"jmp\\t%A1\", operands); | |
19724 | for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--) | |
19725 | { | |
19726 | operands[4] = adjust_address (operands[0], DImode, i*16); | |
19727 | operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i)); | |
19728 | PUT_MODE (operands[4], TImode); | |
19729 | if (GET_CODE (XEXP (operands[0], 0)) != PLUS) | |
19730 | output_asm_insn (\"rex\", operands); | |
19731 | output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands); | |
19732 | } | |
19733 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", | |
19734 | CODE_LABEL_NUMBER (operands[3])); | |
19735 | RET; | |
19736 | } | |
19737 | " | |
19738 | [(set_attr "type" "other") | |
19739 | (set_attr "length_immediate" "0") | |
19740 | (set_attr "length_address" "0") | |
19741 | (set_attr "length" "135") | |
19742 | (set_attr "memory" "store") | |
19743 | (set_attr "modrm" "0") | |
19744 | (set_attr "mode" "DI")]) | |
47f339cf BS |
19745 | |
19746 | ;; 3Dnow! instructions | |
19747 | ||
19748 | (define_insn "addv2sf3" | |
19749 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19750 | (plus:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19751 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19752 | "TARGET_3DNOW" | |
19753 | "pfadd\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19754 | [(set_attr "type" "mmxadd") |
19755 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19756 | |
19757 | (define_insn "subv2sf3" | |
19758 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19759 | (minus:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19760 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19761 | "TARGET_3DNOW" | |
19762 | "pfsub\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19763 | [(set_attr "type" "mmxadd") |
19764 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19765 | |
19766 | (define_insn "subrv2sf3" | |
19767 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19768 | (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym") | |
19769 | (match_operand:V2SF 1 "register_operand" "0")))] | |
19770 | "TARGET_3DNOW" | |
19771 | "pfsubr\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19772 | [(set_attr "type" "mmxadd") |
19773 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19774 | |
19775 | (define_insn "gtv2sf3" | |
19776 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19777 | (gt:V2SI (match_operand:V2SF 1 "register_operand" "0") | |
19778 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19779 | "TARGET_3DNOW" | |
19780 | "pfcmpgt\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19781 | [(set_attr "type" "mmxcmp") |
19782 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19783 | |
19784 | (define_insn "gev2sf3" | |
19785 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19786 | (ge:V2SI (match_operand:V2SF 1 "register_operand" "0") | |
19787 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19788 | "TARGET_3DNOW" | |
19789 | "pfcmpge\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19790 | [(set_attr "type" "mmxcmp") |
19791 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19792 | |
19793 | (define_insn "eqv2sf3" | |
19794 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19795 | (eq:V2SI (match_operand:V2SF 1 "register_operand" "0") | |
19796 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19797 | "TARGET_3DNOW" | |
19798 | "pfcmpeq\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19799 | [(set_attr "type" "mmxcmp") |
19800 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19801 | |
19802 | (define_insn "pfmaxv2sf3" | |
19803 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19804 | (smax:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19805 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19806 | "TARGET_3DNOW" | |
19807 | "pfmax\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19808 | [(set_attr "type" "mmxadd") |
19809 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19810 | |
19811 | (define_insn "pfminv2sf3" | |
19812 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19813 | (smin:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19814 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19815 | "TARGET_3DNOW" | |
19816 | "pfmin\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19817 | [(set_attr "type" "mmxadd") |
19818 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19819 | |
19820 | (define_insn "mulv2sf3" | |
19821 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19822 | (mult:V2SF (match_operand:V2SF 1 "register_operand" "0") | |
19823 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] | |
19824 | "TARGET_3DNOW" | |
19825 | "pfmul\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19826 | [(set_attr "type" "mmxmul") |
19827 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19828 | |
19829 | (define_insn "femms" | |
8ee41eaf | 19830 | [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS) |
47f339cf BS |
19831 | (clobber (reg:XF 8)) |
19832 | (clobber (reg:XF 9)) | |
19833 | (clobber (reg:XF 10)) | |
19834 | (clobber (reg:XF 11)) | |
19835 | (clobber (reg:XF 12)) | |
19836 | (clobber (reg:XF 13)) | |
19837 | (clobber (reg:XF 14)) | |
19838 | (clobber (reg:XF 15)) | |
19839 | (clobber (reg:DI 29)) | |
19840 | (clobber (reg:DI 30)) | |
19841 | (clobber (reg:DI 31)) | |
19842 | (clobber (reg:DI 32)) | |
19843 | (clobber (reg:DI 33)) | |
19844 | (clobber (reg:DI 34)) | |
19845 | (clobber (reg:DI 35)) | |
19846 | (clobber (reg:DI 36))] | |
19847 | "TARGET_3DNOW" | |
19848 | "femms" | |
d82283d5 GS |
19849 | [(set_attr "type" "mmx") |
19850 | (set_attr "memory" "none")]) | |
47f339cf | 19851 | |
47f339cf BS |
19852 | (define_insn "pf2id" |
19853 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19854 | (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))] | |
19855 | "TARGET_3DNOW" | |
19856 | "pf2id\\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
19857 | [(set_attr "type" "mmxcvt") |
19858 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19859 | |
19860 | (define_insn "pf2iw" | |
19861 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
19862 | (sign_extend:V2SI | |
19863 | (ss_truncate:V2HI | |
19864 | (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))] | |
19865 | "TARGET_3DNOW_A" | |
19866 | "pf2iw\\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
19867 | [(set_attr "type" "mmxcvt") |
19868 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19869 | |
19870 | (define_insn "pfacc" | |
19871 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19872 | (vec_concat:V2SF | |
19873 | (plus:SF | |
19874 | (vec_select:SF (match_operand:V2SF 1 "register_operand" "0") | |
19875 | (parallel [(const_int 0)])) | |
19876 | (vec_select:SF (match_dup 1) | |
19877 | (parallel [(const_int 1)]))) | |
19878 | (plus:SF | |
19879 | (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y") | |
19880 | (parallel [(const_int 0)])) | |
19881 | (vec_select:SF (match_dup 2) | |
19882 | (parallel [(const_int 1)])))))] | |
19883 | "TARGET_3DNOW" | |
19884 | "pfacc\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19885 | [(set_attr "type" "mmxadd") |
19886 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19887 | |
19888 | (define_insn "pfnacc" | |
19889 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19890 | (vec_concat:V2SF | |
19891 | (minus:SF | |
19892 | (vec_select:SF (match_operand:V2SF 1 "register_operand" "0") | |
19893 | (parallel [(const_int 0)])) | |
19894 | (vec_select:SF (match_dup 1) | |
19895 | (parallel [(const_int 1)]))) | |
19896 | (minus:SF | |
19897 | (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y") | |
19898 | (parallel [(const_int 0)])) | |
19899 | (vec_select:SF (match_dup 2) | |
19900 | (parallel [(const_int 1)])))))] | |
19901 | "TARGET_3DNOW_A" | |
19902 | "pfnacc\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19903 | [(set_attr "type" "mmxadd") |
19904 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19905 | |
19906 | (define_insn "pfpnacc" | |
19907 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19908 | (vec_concat:V2SF | |
19909 | (minus:SF | |
19910 | (vec_select:SF (match_operand:V2SF 1 "register_operand" "0") | |
19911 | (parallel [(const_int 0)])) | |
19912 | (vec_select:SF (match_dup 1) | |
19913 | (parallel [(const_int 1)]))) | |
19914 | (plus:SF | |
19915 | (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y") | |
19916 | (parallel [(const_int 0)])) | |
19917 | (vec_select:SF (match_dup 2) | |
19918 | (parallel [(const_int 1)])))))] | |
19919 | "TARGET_3DNOW_A" | |
19920 | "pfpnacc\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19921 | [(set_attr "type" "mmxadd") |
19922 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19923 | |
19924 | (define_insn "pi2fw" | |
19925 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19926 | (float:V2SF | |
19927 | (vec_concat:V2SI | |
19928 | (sign_extend:SI | |
19929 | (truncate:HI | |
19930 | (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym") | |
19931 | (parallel [(const_int 0)])))) | |
19932 | (sign_extend:SI | |
19933 | (truncate:HI | |
19934 | (vec_select:SI (match_dup 1) | |
19935 | (parallel [(const_int 1)])))))))] | |
19936 | "TARGET_3DNOW_A" | |
19937 | "pi2fw\\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
19938 | [(set_attr "type" "mmxcvt") |
19939 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19940 | |
19941 | (define_insn "floatv2si2" | |
19942 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19943 | (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))] | |
19944 | "TARGET_3DNOW" | |
19945 | "pi2fd\\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
19946 | [(set_attr "type" "mmxcvt") |
19947 | (set_attr "mode" "V2SF")]) | |
47f339cf BS |
19948 | |
19949 | ;; This insn is identical to pavgb in operation, but the opcode is | |
19950 | ;; different. To avoid accidentally matching pavgb, use an unspec. | |
19951 | ||
19952 | (define_insn "pavgusb" | |
19953 | [(set (match_operand:V8QI 0 "register_operand" "=y") | |
19954 | (unspec:V8QI | |
19955 | [(match_operand:V8QI 1 "register_operand" "0") | |
8ee41eaf RH |
19956 | (match_operand:V8QI 2 "nonimmediate_operand" "ym")] |
19957 | UNSPEC_PAVGUSB))] | |
47f339cf BS |
19958 | "TARGET_3DNOW" |
19959 | "pavgusb\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19960 | [(set_attr "type" "mmxshft") |
19961 | (set_attr "mode" "TI")]) | |
47f339cf BS |
19962 | |
19963 | ;; 3DNow reciprical and sqrt | |
19964 | ||
19965 | (define_insn "pfrcpv2sf2" | |
19966 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
8ee41eaf RH |
19967 | (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] |
19968 | UNSPEC_PFRCP))] | |
47f339cf BS |
19969 | "TARGET_3DNOW" |
19970 | "pfrcp\\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
19971 | [(set_attr "type" "mmx") |
19972 | (set_attr "mode" "TI")]) | |
47f339cf BS |
19973 | |
19974 | (define_insn "pfrcpit1v2sf3" | |
19975 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19976 | (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") | |
8ee41eaf RH |
19977 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")] |
19978 | UNSPEC_PFRCPIT1))] | |
47f339cf BS |
19979 | "TARGET_3DNOW" |
19980 | "pfrcpit1\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19981 | [(set_attr "type" "mmx") |
19982 | (set_attr "mode" "TI")]) | |
47f339cf BS |
19983 | |
19984 | (define_insn "pfrcpit2v2sf3" | |
19985 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
19986 | (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") | |
8ee41eaf RH |
19987 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")] |
19988 | UNSPEC_PFRCPIT2))] | |
47f339cf BS |
19989 | "TARGET_3DNOW" |
19990 | "pfrcpit2\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
19991 | [(set_attr "type" "mmx") |
19992 | (set_attr "mode" "TI")]) | |
47f339cf BS |
19993 | |
19994 | (define_insn "pfrsqrtv2sf2" | |
19995 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
8ee41eaf RH |
19996 | (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] |
19997 | UNSPEC_PFRSQRT))] | |
47f339cf | 19998 | "TARGET_3DNOW" |
3d34cd91 JH |
19999 | "pfrsqrt\\t{%1, %0|%0, %1}" |
20000 | [(set_attr "type" "mmx") | |
20001 | (set_attr "mode" "TI")]) | |
47f339cf BS |
20002 | |
20003 | (define_insn "pfrsqit1v2sf3" | |
20004 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
20005 | (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0") | |
8ee41eaf RH |
20006 | (match_operand:V2SF 2 "nonimmediate_operand" "ym")] |
20007 | UNSPEC_PFRSQIT1))] | |
47f339cf BS |
20008 | "TARGET_3DNOW" |
20009 | "pfrsqit1\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20010 | [(set_attr "type" "mmx") |
20011 | (set_attr "mode" "TI")]) | |
47f339cf BS |
20012 | |
20013 | (define_insn "pmulhrwv4hi3" | |
20014 | [(set (match_operand:V4HI 0 "register_operand" "=y") | |
20015 | (truncate:V4HI | |
20016 | (lshiftrt:V4SI | |
20017 | (plus:V4SI | |
20018 | (mult:V4SI | |
20019 | (sign_extend:V4SI | |
20020 | (match_operand:V4HI 1 "register_operand" "0")) | |
20021 | (sign_extend:V4SI | |
20022 | (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) | |
69ef87e2 AH |
20023 | (const_vector:V4SI [(const_int 32768) |
20024 | (const_int 32768) | |
20025 | (const_int 32768) | |
20026 | (const_int 32768)])) | |
20027 | (const_int 16))))] | |
47f339cf BS |
20028 | "TARGET_3DNOW" |
20029 | "pmulhrw\\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20030 | [(set_attr "type" "mmxmul") |
20031 | (set_attr "mode" "TI")]) | |
47f339cf BS |
20032 | |
20033 | (define_insn "pswapdv2si2" | |
20034 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
20035 | (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym") | |
20036 | (parallel [(const_int 1) (const_int 0)])))] | |
20037 | "TARGET_3DNOW_A" | |
20038 | "pswapd\\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20039 | [(set_attr "type" "mmxcvt") |
20040 | (set_attr "mode" "TI")]) | |
47f339cf BS |
20041 | |
20042 | (define_insn "pswapdv2sf2" | |
20043 | [(set (match_operand:V2SF 0 "register_operand" "=y") | |
20044 | (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym") | |
20045 | (parallel [(const_int 1) (const_int 0)])))] | |
20046 | "TARGET_3DNOW_A" | |
20047 | "pswapd\\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20048 | [(set_attr "type" "mmxcvt") |
20049 | (set_attr "mode" "TI")]) | |
e37af218 RH |
20050 | |
20051 | (define_expand "prefetch" | |
052c96b1 | 20052 | [(prefetch (match_operand 0 "address_operand" "") |
e37af218 RH |
20053 | (match_operand:SI 1 "const_int_operand" "") |
20054 | (match_operand:SI 2 "const_int_operand" ""))] | |
20055 | "TARGET_PREFETCH_SSE || TARGET_3DNOW" | |
20056 | { | |
20057 | int rw = INTVAL (operands[1]); | |
20058 | int locality = INTVAL (operands[2]); | |
7d378549 | 20059 | |
e37af218 RH |
20060 | if (rw != 0 && rw != 1) |
20061 | abort (); | |
20062 | if (locality < 0 || locality > 3) | |
20063 | abort (); | |
052c96b1 JH |
20064 | if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode) |
20065 | abort (); | |
e37af218 RH |
20066 | |
20067 | /* Use 3dNOW prefetch in case we are asking for write prefetch not | |
20068 | suported by SSE counterpart or the SSE prefetch is not available | |
20069 | (K6 machines). Otherwise use SSE prefetch as it allows specifying | |
20070 | of locality. */ | |
20071 | if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw)) | |
7d378549 | 20072 | operands[2] = GEN_INT (3); |
e37af218 | 20073 | else |
7d378549 | 20074 | operands[1] = const0_rtx; |
e37af218 RH |
20075 | }) |
20076 | ||
20077 | (define_insn "*prefetch_sse" | |
e8d52ba0 | 20078 | [(prefetch (match_operand:SI 0 "address_operand" "p") |
e37af218 RH |
20079 | (const_int 0) |
20080 | (match_operand:SI 1 "const_int_operand" ""))] | |
052c96b1 JH |
20081 | "TARGET_PREFETCH_SSE && !TARGET_64BIT" |
20082 | { | |
20083 | static const char * const patterns[4] = { | |
20084 | "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0" | |
20085 | }; | |
20086 | ||
20087 | int locality = INTVAL (operands[1]); | |
20088 | if (locality < 0 || locality > 3) | |
20089 | abort (); | |
20090 | ||
20091 | return patterns[locality]; | |
20092 | } | |
20093 | [(set_attr "type" "sse") | |
20094 | (set_attr "memory" "none")]) | |
20095 | ||
20096 | (define_insn "*prefetch_sse_rex" | |
20097 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
20098 | (const_int 0) | |
20099 | (match_operand:SI 1 "const_int_operand" ""))] | |
20100 | "TARGET_PREFETCH_SSE && TARGET_64BIT" | |
e37af218 RH |
20101 | { |
20102 | static const char * const patterns[4] = { | |
20103 | "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0" | |
20104 | }; | |
20105 | ||
20106 | int locality = INTVAL (operands[1]); | |
20107 | if (locality < 0 || locality > 3) | |
20108 | abort (); | |
20109 | ||
20110 | return patterns[locality]; | |
20111 | } | |
3d34cd91 JH |
20112 | [(set_attr "type" "sse") |
20113 | (set_attr "memory" "none")]) | |
e37af218 RH |
20114 | |
20115 | (define_insn "*prefetch_3dnow" | |
20116 | [(prefetch (match_operand:SI 0 "address_operand" "p") | |
20117 | (match_operand:SI 1 "const_int_operand" "n") | |
7d378549 | 20118 | (const_int 3))] |
052c96b1 JH |
20119 | "TARGET_3DNOW && !TARGET_64BIT" |
20120 | { | |
20121 | if (INTVAL (operands[1]) == 0) | |
20122 | return "prefetch\t%a0"; | |
20123 | else | |
20124 | return "prefetchw\t%a0"; | |
20125 | } | |
20126 | [(set_attr "type" "mmx") | |
20127 | (set_attr "memory" "none")]) | |
20128 | ||
20129 | (define_insn "*prefetch_3dnow_rex" | |
20130 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
20131 | (match_operand:SI 1 "const_int_operand" "n") | |
20132 | (const_int 3))] | |
20133 | "TARGET_3DNOW && TARGET_64BIT" | |
e37af218 RH |
20134 | { |
20135 | if (INTVAL (operands[1]) == 0) | |
20136 | return "prefetch\t%a0"; | |
20137 | else | |
20138 | return "prefetchw\t%a0"; | |
20139 | } | |
3d34cd91 JH |
20140 | [(set_attr "type" "mmx") |
20141 | (set_attr "memory" "none")]) | |
fbe5eb6d BS |
20142 | |
20143 | ;; SSE2 support | |
20144 | ||
20145 | (define_insn "addv2df3" | |
20146 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20147 | (plus:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20148 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] | |
20149 | "TARGET_SSE2" | |
20150 | "addpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20151 | [(set_attr "type" "sseadd") |
20152 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20153 | |
20154 | (define_insn "vmaddv2df3" | |
20155 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20156 | (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20157 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")) | |
20158 | (match_dup 1) | |
20159 | (const_int 1)))] | |
20160 | "TARGET_SSE2" | |
20161 | "addsd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20162 | [(set_attr "type" "sseadd") |
20163 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20164 | |
20165 | (define_insn "subv2df3" | |
20166 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20167 | (minus:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20168 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] | |
20169 | "TARGET_SSE2" | |
20170 | "subpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20171 | [(set_attr "type" "sseadd") |
20172 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20173 | |
20174 | (define_insn "vmsubv2df3" | |
20175 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20176 | (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20177 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")) | |
20178 | (match_dup 1) | |
20179 | (const_int 1)))] | |
20180 | "TARGET_SSE2" | |
20181 | "subsd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20182 | [(set_attr "type" "sseadd") |
20183 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20184 | |
20185 | (define_insn "mulv2df3" | |
20186 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20187 | (mult:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20188 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] | |
20189 | "TARGET_SSE2" | |
20190 | "mulpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20191 | [(set_attr "type" "ssemul") |
20192 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20193 | |
20194 | (define_insn "vmmulv2df3" | |
20195 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20196 | (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20197 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")) | |
20198 | (match_dup 1) | |
20199 | (const_int 1)))] | |
20200 | "TARGET_SSE2" | |
20201 | "mulsd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20202 | [(set_attr "type" "ssemul") |
20203 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20204 | |
20205 | (define_insn "divv2df3" | |
20206 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20207 | (div:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20208 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] | |
20209 | "TARGET_SSE2" | |
20210 | "divpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20211 | [(set_attr "type" "ssediv") |
20212 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20213 | |
20214 | (define_insn "vmdivv2df3" | |
20215 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20216 | (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20217 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")) | |
20218 | (match_dup 1) | |
20219 | (const_int 1)))] | |
20220 | "TARGET_SSE2" | |
20221 | "divsd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20222 | [(set_attr "type" "ssediv") |
20223 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20224 | |
20225 | ;; SSE min/max | |
20226 | ||
20227 | (define_insn "smaxv2df3" | |
20228 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20229 | (smax:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20230 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] | |
20231 | "TARGET_SSE2" | |
20232 | "maxpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20233 | [(set_attr "type" "sseadd") |
20234 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20235 | |
20236 | (define_insn "vmsmaxv2df3" | |
20237 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20238 | (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20239 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")) | |
20240 | (match_dup 1) | |
20241 | (const_int 1)))] | |
20242 | "TARGET_SSE2" | |
20243 | "maxsd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20244 | [(set_attr "type" "sseadd") |
20245 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20246 | |
20247 | (define_insn "sminv2df3" | |
20248 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20249 | (smin:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20250 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] | |
20251 | "TARGET_SSE2" | |
20252 | "minpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20253 | [(set_attr "type" "sseadd") |
20254 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20255 | |
20256 | (define_insn "vmsminv2df3" | |
20257 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20258 | (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20259 | (match_operand:V2DF 2 "nonimmediate_operand" "xm")) | |
20260 | (match_dup 1) | |
20261 | (const_int 1)))] | |
20262 | "TARGET_SSE2" | |
20263 | "minsd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20264 | [(set_attr "type" "sseadd") |
20265 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20266 | |
20267 | (define_insn "sse2_anddf3" | |
20268 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
916b60b7 BS |
20269 | (subreg:V2DF (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0) |
20270 | (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))] | |
fbe5eb6d BS |
20271 | "TARGET_SSE2" |
20272 | "andpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20273 | [(set_attr "type" "sselog") |
20274 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20275 | |
20276 | (define_insn "sse2_nanddf3" | |
20277 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
916b60b7 BS |
20278 | (subreg:V2DF (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "0") 0)) |
20279 | (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))] | |
fbe5eb6d BS |
20280 | "TARGET_SSE2" |
20281 | "andnpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20282 | [(set_attr "type" "sselog") |
20283 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20284 | |
20285 | (define_insn "sse2_iordf3" | |
20286 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
916b60b7 BS |
20287 | (subreg:V2DF (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0) |
20288 | (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))] | |
fbe5eb6d BS |
20289 | "TARGET_SSE2" |
20290 | "orpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20291 | [(set_attr "type" "sselog") |
20292 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20293 | |
20294 | (define_insn "sse2_xordf3" | |
20295 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
916b60b7 BS |
20296 | (subreg:V2DF (xor:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "%0") 0) |
20297 | (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "xm") 0)) 0))] | |
fbe5eb6d BS |
20298 | "TARGET_SSE2" |
20299 | "xorpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20300 | [(set_attr "type" "sselog") |
20301 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20302 | ;; SSE2 square root. There doesn't appear to be an extension for the |
20303 | ;; reciprocal/rsqrt instructions if the Intel manual is to be believed. | |
20304 | ||
20305 | (define_insn "sqrtv2df2" | |
20306 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20307 | (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))] | |
20308 | "TARGET_SSE2" | |
20309 | "sqrtpd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20310 | [(set_attr "type" "sse") |
20311 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20312 | |
20313 | (define_insn "vmsqrtv2df2" | |
20314 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20315 | (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")) | |
20316 | (match_operand:V2DF 2 "register_operand" "0") | |
20317 | (const_int 1)))] | |
20318 | "TARGET_SSE2" | |
20319 | "sqrtsd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20320 | [(set_attr "type" "sse") |
20321 | (set_attr "mode" "SF")]) | |
fbe5eb6d BS |
20322 | |
20323 | ;; SSE mask-generating compares | |
20324 | ||
20325 | (define_insn "maskcmpv2df3" | |
20326 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
20327 | (match_operator:V2DI 3 "sse_comparison_operator" | |
20328 | [(match_operand:V2DF 1 "register_operand" "0") | |
20329 | (match_operand:V2DF 2 "nonimmediate_operand" "x")]))] | |
20330 | "TARGET_SSE2" | |
20331 | "cmp%D3pd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20332 | [(set_attr "type" "ssecmp") |
20333 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20334 | |
20335 | (define_insn "maskncmpv2df3" | |
20336 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
20337 | (not:V2DI | |
20338 | (match_operator:V2DI 3 "sse_comparison_operator" | |
20339 | [(match_operand:V2DF 1 "register_operand" "0") | |
20340 | (match_operand:V2DF 2 "nonimmediate_operand" "x")])))] | |
20341 | "TARGET_SSE2" | |
20342 | "cmpn%D3pd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20343 | [(set_attr "type" "ssecmp") |
20344 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20345 | |
20346 | (define_insn "vmmaskcmpv2df3" | |
20347 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
20348 | (vec_merge:V2DI | |
20349 | (match_operator:V2DI 3 "sse_comparison_operator" | |
20350 | [(match_operand:V2DF 1 "register_operand" "0") | |
20351 | (match_operand:V2DF 2 "nonimmediate_operand" "x")]) | |
20352 | (match_dup 1) | |
20353 | (const_int 1)))] | |
20354 | "TARGET_SSE2" | |
20355 | "cmp%D3sd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20356 | [(set_attr "type" "ssecmp") |
20357 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20358 | |
20359 | (define_insn "vmmaskncmpv2df3" | |
20360 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
20361 | (vec_merge:V2DI | |
20362 | (not:V2DI | |
20363 | (match_operator:V2DI 3 "sse_comparison_operator" | |
20364 | [(match_operand:V2DF 1 "register_operand" "0") | |
20365 | (match_operand:V2DF 2 "nonimmediate_operand" "x")])) | |
20366 | (subreg:V2DI (match_dup 1) 0) | |
20367 | (const_int 1)))] | |
20368 | "TARGET_SSE2" | |
20369 | "cmp%D3sd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20370 | [(set_attr "type" "ssecmp") |
20371 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20372 | |
20373 | (define_insn "sse2_comi" | |
20374 | [(set (reg:CCFP 17) | |
20375 | (match_operator:CCFP 2 "sse_comparison_operator" | |
20376 | [(vec_select:DF | |
20377 | (match_operand:V2DF 0 "register_operand" "x") | |
20378 | (parallel [(const_int 0)])) | |
20379 | (vec_select:DF | |
20380 | (match_operand:V2DF 1 "register_operand" "x") | |
20381 | (parallel [(const_int 0)]))]))] | |
20382 | "TARGET_SSE2" | |
20383 | "comisd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20384 | [(set_attr "type" "ssecmp") |
20385 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20386 | |
20387 | (define_insn "sse2_ucomi" | |
20388 | [(set (reg:CCFPU 17) | |
20389 | (match_operator:CCFPU 2 "sse_comparison_operator" | |
20390 | [(vec_select:DF | |
20391 | (match_operand:V2DF 0 "register_operand" "x") | |
20392 | (parallel [(const_int 0)])) | |
20393 | (vec_select:DF | |
20394 | (match_operand:V2DF 1 "register_operand" "x") | |
20395 | (parallel [(const_int 0)]))]))] | |
20396 | "TARGET_SSE2" | |
20397 | "ucomisd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20398 | [(set_attr "type" "ssecmp") |
20399 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20400 | |
20401 | ;; SSE Strange Moves. | |
20402 | ||
20403 | (define_insn "sse2_movmskpd" | |
20404 | [(set (match_operand:SI 0 "register_operand" "=r") | |
8ee41eaf RH |
20405 | (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")] |
20406 | UNSPEC_MOVMSK))] | |
fbe5eb6d BS |
20407 | "TARGET_SSE2" |
20408 | "movmskpd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20409 | [(set_attr "type" "ssecvt") |
20410 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20411 | |
20412 | (define_insn "sse2_pmovmskb" | |
20413 | [(set (match_operand:SI 0 "register_operand" "=r") | |
8ee41eaf RH |
20414 | (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")] |
20415 | UNSPEC_MOVMSK))] | |
fbe5eb6d BS |
20416 | "TARGET_SSE2" |
20417 | "pmovmskb\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20418 | [(set_attr "type" "ssecvt") |
20419 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20420 | |
20421 | (define_insn "sse2_maskmovdqu" | |
20422 | [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D")) | |
20423 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x") | |
8ee41eaf RH |
20424 | (match_operand:V16QI 2 "register_operand" "x")] |
20425 | UNSPEC_MASKMOV))] | |
fbe5eb6d BS |
20426 | "TARGET_SSE2" |
20427 | ;; @@@ check ordering of operands in intel/nonintel syntax | |
20428 | "maskmovdqu\t{%2, %1|%1, %2}" | |
3d34cd91 JH |
20429 | [(set_attr "type" "ssecvt") |
20430 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20431 | |
20432 | (define_insn "sse2_movntv2df" | |
20433 | [(set (match_operand:V2DF 0 "memory_operand" "=m") | |
8ee41eaf RH |
20434 | (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")] |
20435 | UNSPEC_MOVNT))] | |
fbe5eb6d BS |
20436 | "TARGET_SSE2" |
20437 | "movntpd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20438 | [(set_attr "type" "ssecvt") |
20439 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d | 20440 | |
916b60b7 BS |
20441 | (define_insn "sse2_movntv2di" |
20442 | [(set (match_operand:V2DI 0 "memory_operand" "=m") | |
8ee41eaf RH |
20443 | (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")] |
20444 | UNSPEC_MOVNT))] | |
fbe5eb6d BS |
20445 | "TARGET_SSE2" |
20446 | "movntdq\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20447 | [(set_attr "type" "ssecvt") |
20448 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20449 | |
20450 | (define_insn "sse2_movntsi" | |
20451 | [(set (match_operand:SI 0 "memory_operand" "=m") | |
8ee41eaf RH |
20452 | (unspec:SI [(match_operand:SI 1 "register_operand" "r")] |
20453 | UNSPEC_MOVNT))] | |
fbe5eb6d BS |
20454 | "TARGET_SSE2" |
20455 | "movnti\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20456 | [(set_attr "type" "ssecvt") |
20457 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20458 | |
20459 | ;; SSE <-> integer/MMX conversions | |
20460 | ||
20461 | ;; Conversions between SI and SF | |
20462 | ||
20463 | (define_insn "cvtdq2ps" | |
20464 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
20465 | (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))] | |
20466 | "TARGET_SSE2" | |
20467 | "cvtdq2ps\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20468 | [(set_attr "type" "ssecvt") |
20469 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20470 | |
20471 | (define_insn "cvtps2dq" | |
20472 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
20473 | (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))] | |
20474 | "TARGET_SSE2" | |
20475 | "cvtps2dq\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20476 | [(set_attr "type" "ssecvt") |
20477 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20478 | |
20479 | (define_insn "cvttps2dq" | |
20480 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
8ee41eaf RH |
20481 | (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] |
20482 | UNSPEC_FIX))] | |
fbe5eb6d BS |
20483 | "TARGET_SSE2" |
20484 | "cvttps2dq\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20485 | [(set_attr "type" "ssecvt") |
20486 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20487 | |
20488 | ;; Conversions between SI and DF | |
20489 | ||
20490 | (define_insn "cvtdq2pd" | |
20491 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20492 | (float:V2DF (vec_select:V2SI | |
916b60b7 | 20493 | (match_operand:V4SI 1 "nonimmediate_operand" "xm") |
fbe5eb6d BS |
20494 | (parallel |
20495 | [(const_int 0) | |
20496 | (const_int 1)]))))] | |
20497 | "TARGET_SSE2" | |
20498 | "cvtdq2pd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20499 | [(set_attr "type" "ssecvt") |
20500 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20501 | |
20502 | (define_insn "cvtpd2dq" | |
20503 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
20504 | (vec_concat:V4SI | |
20505 | (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")) | |
20506 | (const_vector:V2SI [(const_int 0) (const_int 0)])))] | |
20507 | "TARGET_SSE2" | |
20508 | "cvtpd2dq\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20509 | [(set_attr "type" "ssecvt") |
20510 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20511 | |
20512 | (define_insn "cvttpd2dq" | |
20513 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
20514 | (vec_concat:V4SI | |
8ee41eaf RH |
20515 | (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] |
20516 | UNSPEC_FIX) | |
fbe5eb6d BS |
20517 | (const_vector:V2SI [(const_int 0) (const_int 0)])))] |
20518 | "TARGET_SSE2" | |
20519 | "cvttpd2dq\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20520 | [(set_attr "type" "ssecvt") |
20521 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20522 | |
20523 | (define_insn "cvtpd2pi" | |
20524 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
20525 | (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))] | |
20526 | "TARGET_SSE2" | |
20527 | "cvtpd2pi\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20528 | [(set_attr "type" "ssecvt") |
20529 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20530 | |
20531 | (define_insn "cvttpd2pi" | |
20532 | [(set (match_operand:V2SI 0 "register_operand" "=y") | |
8ee41eaf RH |
20533 | (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] |
20534 | UNSPEC_FIX))] | |
fbe5eb6d BS |
20535 | "TARGET_SSE2" |
20536 | "cvttpd2pi\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20537 | [(set_attr "type" "ssecvt") |
20538 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20539 | |
20540 | (define_insn "cvtpi2pd" | |
20541 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20542 | (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))] | |
20543 | "TARGET_SSE2" | |
20544 | "cvtpi2pd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20545 | [(set_attr "type" "ssecvt") |
20546 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20547 | |
20548 | ;; Conversions between SI and DF | |
20549 | ||
20550 | (define_insn "cvtsd2si" | |
20551 | [(set (match_operand:SI 0 "register_operand" "=r") | |
20552 | (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "xm") | |
20553 | (parallel [(const_int 0)]))))] | |
20554 | "TARGET_SSE2" | |
20555 | "cvtsd2si\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20556 | [(set_attr "type" "ssecvt") |
20557 | (set_attr "mode" "SI")]) | |
fbe5eb6d BS |
20558 | |
20559 | (define_insn "cvttsd2si" | |
20560 | [(set (match_operand:SI 0 "register_operand" "=r") | |
20561 | (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm") | |
8ee41eaf | 20562 | (parallel [(const_int 0)]))] UNSPEC_FIX))] |
fbe5eb6d BS |
20563 | "TARGET_SSE2" |
20564 | "cvttsd2si\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20565 | [(set_attr "type" "ssecvt") |
20566 | (set_attr "mode" "SI")]) | |
fbe5eb6d BS |
20567 | |
20568 | (define_insn "cvtsi2sd" | |
20569 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20570 | (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20571 | (vec_duplicate:V2DF | |
20572 | (float:DF | |
20573 | (match_operand:SI 2 "nonimmediate_operand" "rm"))) | |
20574 | (const_int 2)))] | |
20575 | "TARGET_SSE2" | |
20576 | "cvtsd2si\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20577 | [(set_attr "type" "ssecvt") |
20578 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20579 | |
20580 | ;; Conversions between SF and DF | |
20581 | ||
20582 | (define_insn "cvtsd2ss" | |
20583 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
20584 | (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0") | |
20585 | (vec_duplicate:V4SF | |
20586 | (float_truncate:V2SF | |
20587 | (match_operand:V2DF 2 "register_operand" "xm"))) | |
20588 | (const_int 14)))] | |
20589 | "TARGET_SSE2" | |
20590 | "cvtsd2ss\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20591 | [(set_attr "type" "ssecvt") |
20592 | (set_attr "mode" "SF")]) | |
fbe5eb6d BS |
20593 | |
20594 | (define_insn "cvtss2sd" | |
20595 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20596 | (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
20597 | (float_extend:V2DF | |
20598 | (vec_select:V2SF | |
20599 | (match_operand:V4SF 2 "register_operand" "xm") | |
20600 | (parallel [(const_int 0) | |
20601 | (const_int 1)]))) | |
20602 | (const_int 2)))] | |
20603 | "TARGET_SSE2" | |
20604 | "cvtss2sd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20605 | [(set_attr "type" "ssecvt") |
20606 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
20607 | |
20608 | (define_insn "cvtpd2ps" | |
20609 | [(set (match_operand:V4SF 0 "register_operand" "=x") | |
20610 | (subreg:V4SF | |
20611 | (vec_concat:V4SI | |
20612 | (subreg:V2SI (float_truncate:V2SF | |
20613 | (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0) | |
20614 | (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))] | |
20615 | "TARGET_SSE2" | |
20616 | "cvtpd2ps\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20617 | [(set_attr "type" "ssecvt") |
20618 | (set_attr "mode" "V4SF")]) | |
fbe5eb6d BS |
20619 | |
20620 | (define_insn "cvtps2pd" | |
20621 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
20622 | (float_extend:V2DF | |
20623 | (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm") | |
20624 | (parallel [(const_int 0) | |
20625 | (const_int 1)]))))] | |
20626 | "TARGET_SSE2" | |
20627 | "cvtps2pd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
20628 | [(set_attr "type" "ssecvt") |
20629 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
20630 | |
20631 | ;; SSE2 variants of MMX insns | |
20632 | ||
20633 | ;; MMX arithmetic | |
20634 | ||
20635 | (define_insn "addv16qi3" | |
20636 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
20637 | (plus:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
20638 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
20639 | "TARGET_SSE2" | |
20640 | "paddb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20641 | [(set_attr "type" "sseiadd") |
20642 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20643 | |
20644 | (define_insn "addv8hi3" | |
20645 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20646 | (plus:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
20647 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
20648 | "TARGET_SSE2" | |
20649 | "paddw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20650 | [(set_attr "type" "sseiadd") |
20651 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20652 | |
20653 | (define_insn "addv4si3" | |
20654 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
20655 | (plus:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
20656 | (match_operand:V4SI 2 "nonimmediate_operand" "xm")))] | |
20657 | "TARGET_SSE2" | |
20658 | "paddd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20659 | [(set_attr "type" "sseiadd") |
20660 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20661 | |
20662 | (define_insn "addv2di3" | |
20663 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
20664 | (plus:V2DI (match_operand:V2DI 1 "register_operand" "0") | |
20665 | (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] | |
20666 | "TARGET_SSE2" | |
20667 | "paddq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20668 | [(set_attr "type" "sseiadd") |
20669 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20670 | |
20671 | (define_insn "ssaddv16qi3" | |
20672 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
20673 | (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
20674 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
20675 | "TARGET_SSE2" | |
20676 | "paddsb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20677 | [(set_attr "type" "sseiadd") |
20678 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20679 | |
20680 | (define_insn "ssaddv8hi3" | |
20681 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20682 | (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
20683 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
20684 | "TARGET_SSE2" | |
20685 | "paddsw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20686 | [(set_attr "type" "sseiadd") |
20687 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20688 | |
20689 | (define_insn "usaddv16qi3" | |
20690 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
20691 | (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
20692 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
20693 | "TARGET_SSE2" | |
20694 | "paddusb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20695 | [(set_attr "type" "sseiadd") |
20696 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20697 | |
20698 | (define_insn "usaddv8hi3" | |
20699 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20700 | (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
20701 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
20702 | "TARGET_SSE2" | |
20703 | "paddusw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20704 | [(set_attr "type" "sseiadd") |
20705 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20706 | |
20707 | (define_insn "subv16qi3" | |
20708 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
20709 | (minus:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
20710 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
20711 | "TARGET_SSE2" | |
20712 | "psubb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20713 | [(set_attr "type" "sseiadd") |
20714 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20715 | |
20716 | (define_insn "subv8hi3" | |
20717 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20718 | (minus:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
20719 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
20720 | "TARGET_SSE2" | |
20721 | "psubw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20722 | [(set_attr "type" "sseiadd") |
20723 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20724 | |
20725 | (define_insn "subv4si3" | |
20726 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
20727 | (minus:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
20728 | (match_operand:V4SI 2 "nonimmediate_operand" "xm")))] | |
20729 | "TARGET_SSE2" | |
20730 | "psubd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20731 | [(set_attr "type" "sseiadd") |
20732 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20733 | |
20734 | (define_insn "subv2di3" | |
20735 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
20736 | (minus:V2DI (match_operand:V2DI 1 "register_operand" "0") | |
20737 | (match_operand:V2DI 2 "nonimmediate_operand" "xm")))] | |
20738 | "TARGET_SSE2" | |
20739 | "psubq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20740 | [(set_attr "type" "sseiadd") |
20741 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20742 | |
20743 | (define_insn "sssubv16qi3" | |
20744 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
20745 | (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
20746 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
20747 | "TARGET_SSE2" | |
20748 | "psubsb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20749 | [(set_attr "type" "sseiadd") |
20750 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20751 | |
20752 | (define_insn "sssubv8hi3" | |
20753 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20754 | (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
20755 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
20756 | "TARGET_SSE2" | |
20757 | "psubsw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20758 | [(set_attr "type" "sseiadd") |
20759 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20760 | |
20761 | (define_insn "ussubv16qi3" | |
20762 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
20763 | (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
20764 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
20765 | "TARGET_SSE2" | |
20766 | "psubusb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20767 | [(set_attr "type" "sseiadd") |
20768 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20769 | |
20770 | (define_insn "ussubv8hi3" | |
20771 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20772 | (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
20773 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
20774 | "TARGET_SSE2" | |
20775 | "psubusw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20776 | [(set_attr "type" "sseiadd") |
20777 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20778 | |
20779 | (define_insn "mulv8hi3" | |
20780 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20781 | (mult:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
20782 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
20783 | "TARGET_SSE2" | |
20784 | "pmullw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20785 | [(set_attr "type" "sseimul") |
20786 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20787 | |
20788 | (define_insn "smulv8hi3_highpart" | |
20789 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20790 | (truncate:V8HI | |
20791 | (lshiftrt:V8SI | |
20792 | (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0")) | |
20793 | (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm"))) | |
20794 | (const_int 16))))] | |
20795 | "TARGET_SSE2" | |
20796 | "pmulhw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20797 | [(set_attr "type" "sseimul") |
20798 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20799 | |
20800 | (define_insn "umulv8hi3_highpart" | |
20801 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20802 | (truncate:V8HI | |
20803 | (lshiftrt:V8SI | |
20804 | (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0")) | |
20805 | (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm"))) | |
20806 | (const_int 16))))] | |
20807 | "TARGET_SSE2" | |
20808 | "pmulhuw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20809 | [(set_attr "type" "sseimul") |
20810 | (set_attr "mode" "TI")]) | |
fbe5eb6d | 20811 | |
fbe5eb6d BS |
20812 | (define_insn "sse2_umulsidi3" |
20813 | [(set (match_operand:DI 0 "register_operand" "=y") | |
916b60b7 BS |
20814 | (mult:DI (zero_extend:DI (vec_select:SI |
20815 | (match_operand:V2SI 1 "register_operand" "0") | |
20816 | (parallel [(const_int 0)]))) | |
20817 | (zero_extend:DI (vec_select:SI | |
20818 | (match_operand:V2SI 2 "nonimmediate_operand" "ym") | |
20819 | (parallel [(const_int 0)])))))] | |
fbe5eb6d BS |
20820 | "TARGET_SSE2" |
20821 | "pmuludq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20822 | [(set_attr "type" "sseimul") |
20823 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20824 | |
20825 | (define_insn "sse2_umulv2siv2di3" | |
20826 | [(set (match_operand:V2DI 0 "register_operand" "=y") | |
20827 | (mult:V2DI (zero_extend:V2DI | |
20828 | (vec_select:V2SI | |
20829 | (match_operand:V4SI 1 "register_operand" "0") | |
20830 | (parallel [(const_int 0) (const_int 2)]))) | |
20831 | (zero_extend:V2DI | |
20832 | (vec_select:V2SI | |
20833 | (match_operand:V4SI 2 "nonimmediate_operand" "ym") | |
20834 | (parallel [(const_int 0) (const_int 2)])))))] | |
20835 | "TARGET_SSE2" | |
20836 | "pmuludq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20837 | [(set_attr "type" "sseimul") |
20838 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20839 | |
20840 | (define_insn "sse2_pmaddwd" | |
20841 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
20842 | (plus:V4SI | |
20843 | (mult:V4SI | |
20844 | (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0") | |
20845 | (parallel [(const_int 0) | |
20846 | (const_int 2) | |
20847 | (const_int 4) | |
20848 | (const_int 6)]))) | |
20849 | (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm") | |
20850 | (parallel [(const_int 0) | |
20851 | (const_int 2) | |
20852 | (const_int 4) | |
20853 | (const_int 6)])))) | |
20854 | (mult:V4SI | |
20855 | (sign_extend:V4SI (vec_select:V4HI (match_dup 1) | |
20856 | (parallel [(const_int 1) | |
20857 | (const_int 3) | |
20858 | (const_int 5) | |
20859 | (const_int 7)]))) | |
20860 | (sign_extend:V4SI (vec_select:V4HI (match_dup 2) | |
20861 | (parallel [(const_int 1) | |
20862 | (const_int 3) | |
20863 | (const_int 5) | |
20864 | (const_int 7)]))))))] | |
20865 | "TARGET_SSE2" | |
20866 | "pmaddwd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20867 | [(set_attr "type" "sseiadd") |
20868 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20869 | |
20870 | ;; Same as pxor, but don't show input operands so that we don't think | |
20871 | ;; they are live. | |
20872 | (define_insn "sse2_clrti" | |
20873 | [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))] | |
20874 | "TARGET_SSE2" | |
20875 | "pxor\t{%0, %0|%0, %0}" | |
3d34cd91 | 20876 | [(set_attr "type" "sseiadd") |
19cba4a0 | 20877 | (set_attr "memory" "none") |
3d34cd91 | 20878 | (set_attr "mode" "TI")]) |
fbe5eb6d BS |
20879 | |
20880 | ;; MMX unsigned averages/sum of absolute differences | |
20881 | ||
20882 | (define_insn "sse2_uavgv16qi3" | |
20883 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
20884 | (ashiftrt:V16QI | |
20885 | (plus:V16QI (plus:V16QI | |
20886 | (match_operand:V16QI 1 "register_operand" "0") | |
20887 | (match_operand:V16QI 2 "nonimmediate_operand" "ym")) | |
20888 | (const_vector:V16QI [(const_int 1) (const_int 1) | |
20889 | (const_int 1) (const_int 1) | |
20890 | (const_int 1) (const_int 1) | |
20891 | (const_int 1) (const_int 1) | |
20892 | (const_int 1) (const_int 1) | |
20893 | (const_int 1) (const_int 1) | |
20894 | (const_int 1) (const_int 1) | |
20895 | (const_int 1) (const_int 1)])) | |
20896 | (const_int 1)))] | |
20897 | "TARGET_SSE2" | |
20898 | "pavgb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20899 | [(set_attr "type" "sseiadd") |
20900 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20901 | |
20902 | (define_insn "sse2_uavgv8hi3" | |
20903 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20904 | (ashiftrt:V8HI | |
20905 | (plus:V8HI (plus:V8HI | |
20906 | (match_operand:V8HI 1 "register_operand" "0") | |
20907 | (match_operand:V8HI 2 "nonimmediate_operand" "ym")) | |
20908 | (const_vector:V8HI [(const_int 1) (const_int 1) | |
20909 | (const_int 1) (const_int 1) | |
20910 | (const_int 1) (const_int 1) | |
20911 | (const_int 1) (const_int 1)])) | |
20912 | (const_int 1)))] | |
20913 | "TARGET_SSE2" | |
20914 | "pavgw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20915 | [(set_attr "type" "sseiadd") |
20916 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20917 | |
20918 | ;; @@@ this isn't the right representation. | |
20919 | (define_insn "sse2_psadbw" | |
916b60b7 BS |
20920 | [(set (match_operand:V2DI 0 "register_operand" "=x") |
20921 | (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0") | |
8ee41eaf RH |
20922 | (match_operand:V16QI 2 "nonimmediate_operand" "ym")] |
20923 | UNSPEC_PSADBW))] | |
fbe5eb6d BS |
20924 | "TARGET_SSE2" |
20925 | "psadbw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20926 | [(set_attr "type" "sseiadd") |
20927 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20928 | |
20929 | ||
20930 | ;; MMX insert/extract/shuffle | |
20931 | ||
20932 | (define_insn "sse2_pinsrw" | |
20933 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20934 | (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
20935 | (vec_duplicate:V8HI | |
20936 | (match_operand:SI 2 "nonimmediate_operand" "rm")) | |
20937 | (match_operand:SI 3 "immediate_operand" "i")))] | |
20938 | "TARGET_SSE2" | |
20939 | "pinsrw\t{%3, %2, %0|%0, %2, %3}" | |
3d34cd91 JH |
20940 | [(set_attr "type" "ssecvt") |
20941 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20942 | |
20943 | (define_insn "sse2_pextrw" | |
20944 | [(set (match_operand:SI 0 "register_operand" "=r") | |
20945 | (zero_extend:SI | |
20946 | (vec_select:HI (match_operand:V8HI 1 "register_operand" "x") | |
20947 | (parallel | |
20948 | [(match_operand:SI 2 "immediate_operand" "i")]))))] | |
20949 | "TARGET_SSE2" | |
20950 | "pextrw\t{%2, %1, %0|%0, %1, %2}" | |
3d34cd91 JH |
20951 | [(set_attr "type" "ssecvt") |
20952 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20953 | |
20954 | (define_insn "sse2_pshufd" | |
20955 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
20956 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") | |
8ee41eaf RH |
20957 | (match_operand:SI 2 "immediate_operand" "i")] |
20958 | UNSPEC_SHUFFLE))] | |
fbe5eb6d BS |
20959 | "TARGET_SSE2" |
20960 | "pshufd\t{%2, %1, %0|%0, %1, %2}" | |
3d34cd91 JH |
20961 | [(set_attr "type" "ssecvt") |
20962 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20963 | |
20964 | (define_insn "sse2_pshuflw" | |
20965 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20966 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0") | |
8ee41eaf RH |
20967 | (match_operand:SI 2 "immediate_operand" "i")] |
20968 | UNSPEC_PSHUFLW))] | |
fbe5eb6d BS |
20969 | "TARGET_SSE2" |
20970 | "pshuflw\t{%2, %1, %0|%0, %1, %2}" | |
3d34cd91 JH |
20971 | [(set_attr "type" "ssecvt") |
20972 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20973 | |
20974 | (define_insn "sse2_pshufhw" | |
20975 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20976 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0") | |
8ee41eaf RH |
20977 | (match_operand:SI 2 "immediate_operand" "i")] |
20978 | UNSPEC_PSHUFHW))] | |
fbe5eb6d BS |
20979 | "TARGET_SSE2" |
20980 | "pshufhw\t{%2, %1, %0|%0, %1, %2}" | |
3d34cd91 JH |
20981 | [(set_attr "type" "ssecvt") |
20982 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20983 | |
20984 | ;; MMX mask-generating comparisons | |
20985 | ||
20986 | (define_insn "eqv16qi3" | |
20987 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
20988 | (eq:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
20989 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
20990 | "TARGET_SSE2" | |
20991 | "pcmpeqb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
20992 | [(set_attr "type" "ssecmp") |
20993 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
20994 | |
20995 | (define_insn "eqv8hi3" | |
20996 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
20997 | (eq:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
20998 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
20999 | "TARGET_SSE2" | |
21000 | "pcmpeqw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21001 | [(set_attr "type" "ssecmp") |
21002 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21003 | |
21004 | (define_insn "eqv4si3" | |
21005 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21006 | (eq:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
21007 | (match_operand:V4SI 2 "nonimmediate_operand" "xm")))] | |
21008 | "TARGET_SSE2" | |
21009 | "pcmpeqd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21010 | [(set_attr "type" "ssecmp") |
21011 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21012 | |
21013 | (define_insn "gtv16qi3" | |
21014 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
21015 | (gt:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
21016 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
21017 | "TARGET_SSE2" | |
21018 | "pcmpgtb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21019 | [(set_attr "type" "ssecmp") |
21020 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21021 | |
21022 | (define_insn "gtv8hi3" | |
21023 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21024 | (gt:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
21025 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
21026 | "TARGET_SSE2" | |
21027 | "pcmpgtw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21028 | [(set_attr "type" "ssecmp") |
21029 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21030 | |
21031 | (define_insn "gtv4si3" | |
21032 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21033 | (gt:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
21034 | (match_operand:V4SI 2 "nonimmediate_operand" "xm")))] | |
21035 | "TARGET_SSE2" | |
21036 | "pcmpgtd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21037 | [(set_attr "type" "ssecmp") |
21038 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21039 | |
21040 | ||
21041 | ;; MMX max/min insns | |
21042 | ||
21043 | (define_insn "umaxv16qi3" | |
21044 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
21045 | (umax:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
21046 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
21047 | "TARGET_SSE2" | |
21048 | "pmaxub\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21049 | [(set_attr "type" "sseiadd") |
21050 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21051 | |
21052 | (define_insn "smaxv8hi3" | |
21053 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21054 | (smax:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
21055 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
21056 | "TARGET_SSE2" | |
21057 | "pmaxsw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21058 | [(set_attr "type" "sseiadd") |
21059 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21060 | |
21061 | (define_insn "uminv16qi3" | |
21062 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
21063 | (umin:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
21064 | (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] | |
21065 | "TARGET_SSE2" | |
21066 | "pminub\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21067 | [(set_attr "type" "sseiadd") |
21068 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21069 | |
21070 | (define_insn "sminv8hi3" | |
21071 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21072 | (smin:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
21073 | (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] | |
21074 | "TARGET_SSE2" | |
21075 | "pminsw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21076 | [(set_attr "type" "sseiadd") |
21077 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21078 | |
21079 | ||
21080 | ;; MMX shifts | |
21081 | ||
21082 | (define_insn "ashrv8hi3" | |
21083 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21084 | (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
916b60b7 | 21085 | (match_operand:SI 2 "nonmemory_operand" "ri")))] |
fbe5eb6d BS |
21086 | "TARGET_SSE2" |
21087 | "psraw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21088 | [(set_attr "type" "sseishft") |
21089 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21090 | |
21091 | (define_insn "ashrv4si3" | |
21092 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21093 | (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
916b60b7 | 21094 | (match_operand:SI 2 "nonmemory_operand" "ri")))] |
fbe5eb6d BS |
21095 | "TARGET_SSE2" |
21096 | "psrad\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21097 | [(set_attr "type" "sseishft") |
21098 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21099 | |
21100 | (define_insn "lshrv8hi3" | |
21101 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21102 | (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
916b60b7 | 21103 | (match_operand:SI 2 "nonmemory_operand" "ri")))] |
fbe5eb6d BS |
21104 | "TARGET_SSE2" |
21105 | "psrlw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21106 | [(set_attr "type" "sseishft") |
21107 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21108 | |
21109 | (define_insn "lshrv4si3" | |
21110 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21111 | (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
916b60b7 | 21112 | (match_operand:SI 2 "nonmemory_operand" "ri")))] |
fbe5eb6d BS |
21113 | "TARGET_SSE2" |
21114 | "psrld\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21115 | [(set_attr "type" "sseishft") |
21116 | (set_attr "mode" "TI")]) | |
fbe5eb6d | 21117 | |
916b60b7 | 21118 | (define_insn "lshrv2di3" |
fbe5eb6d BS |
21119 | [(set (match_operand:V2DI 0 "register_operand" "=x") |
21120 | (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0") | |
916b60b7 | 21121 | (match_operand:SI 2 "nonmemory_operand" "ri")))] |
fbe5eb6d BS |
21122 | "TARGET_SSE2" |
21123 | "psrlq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21124 | [(set_attr "type" "sseishft") |
21125 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21126 | |
21127 | (define_insn "ashlv8hi3" | |
21128 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21129 | (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
916b60b7 | 21130 | (match_operand:SI 2 "nonmemory_operand" "ri")))] |
fbe5eb6d BS |
21131 | "TARGET_SSE2" |
21132 | "psllw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21133 | [(set_attr "type" "sseishft") |
21134 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21135 | |
21136 | (define_insn "ashlv4si3" | |
21137 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21138 | (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
916b60b7 BS |
21139 | (match_operand:SI 2 "nonmemory_operand" "ri")))] |
21140 | "TARGET_SSE2" | |
21141 | "pslld\t{%2, %0|%0, %2}" | |
5f90a099 JH |
21142 | [(set_attr "type" "sseishft") |
21143 | (set_attr "mode" "TI")]) | |
916b60b7 BS |
21144 | |
21145 | (define_insn "ashlv2di3" | |
21146 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
21147 | (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0") | |
21148 | (match_operand:SI 2 "nonmemory_operand" "ri")))] | |
21149 | "TARGET_SSE2" | |
21150 | "psllq\t{%2, %0|%0, %2}" | |
5f90a099 JH |
21151 | [(set_attr "type" "sseishft") |
21152 | (set_attr "mode" "TI")]) | |
916b60b7 BS |
21153 | |
21154 | (define_insn "ashrv8hi3_ti" | |
21155 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21156 | (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
21157 | (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] | |
21158 | "TARGET_SSE2" | |
21159 | "psraw\t{%2, %0|%0, %2}" | |
5f90a099 JH |
21160 | [(set_attr "type" "sseishft") |
21161 | (set_attr "mode" "TI")]) | |
916b60b7 BS |
21162 | |
21163 | (define_insn "ashrv4si3_ti" | |
21164 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21165 | (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
21166 | (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] | |
21167 | "TARGET_SSE2" | |
21168 | "psrad\t{%2, %0|%0, %2}" | |
5f90a099 JH |
21169 | [(set_attr "type" "sseishft") |
21170 | (set_attr "mode" "TI")]) | |
916b60b7 BS |
21171 | |
21172 | (define_insn "lshrv8hi3_ti" | |
21173 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21174 | (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
21175 | (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] | |
21176 | "TARGET_SSE2" | |
21177 | "psrlw\t{%2, %0|%0, %2}" | |
5f90a099 JH |
21178 | [(set_attr "type" "sseishft") |
21179 | (set_attr "mode" "TI")]) | |
916b60b7 BS |
21180 | |
21181 | (define_insn "lshrv4si3_ti" | |
21182 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21183 | (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
21184 | (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] | |
21185 | "TARGET_SSE2" | |
21186 | "psrld\t{%2, %0|%0, %2}" | |
5f90a099 JH |
21187 | [(set_attr "type" "sseishft") |
21188 | (set_attr "mode" "TI")]) | |
916b60b7 BS |
21189 | |
21190 | (define_insn "lshrv2di3_ti" | |
21191 | [(set (match_operand:V2DI 0 "register_operand" "=x") | |
21192 | (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0") | |
21193 | (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] | |
21194 | "TARGET_SSE2" | |
21195 | "psrlq\t{%2, %0|%0, %2}" | |
5f90a099 JH |
21196 | [(set_attr "type" "sseishft") |
21197 | (set_attr "mode" "TI")]) | |
916b60b7 BS |
21198 | |
21199 | (define_insn "ashlv8hi3_ti" | |
21200 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21201 | (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
21202 | (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] | |
21203 | "TARGET_SSE2" | |
21204 | "psllw\t{%2, %0|%0, %2}" | |
5f90a099 JH |
21205 | [(set_attr "type" "sseishft") |
21206 | (set_attr "mode" "TI")]) | |
916b60b7 BS |
21207 | |
21208 | (define_insn "ashlv4si3_ti" | |
21209 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21210 | (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
21211 | (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] | |
fbe5eb6d BS |
21212 | "TARGET_SSE2" |
21213 | "pslld\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21214 | [(set_attr "type" "sseishft") |
21215 | (set_attr "mode" "TI")]) | |
fbe5eb6d | 21216 | |
916b60b7 | 21217 | (define_insn "ashlv2di3_ti" |
fbe5eb6d BS |
21218 | [(set (match_operand:V2DI 0 "register_operand" "=x") |
21219 | (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0") | |
916b60b7 | 21220 | (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))] |
fbe5eb6d BS |
21221 | "TARGET_SSE2" |
21222 | "psllq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21223 | [(set_attr "type" "sseishft") |
21224 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21225 | |
21226 | ;; See logical MMX insns for the reason for the unspec. Strictly speaking | |
21227 | ;; we wouldn't need here it since we never generate TImode arithmetic. | |
21228 | ||
21229 | ;; There has to be some kind of prize for the weirdest new instruction... | |
21230 | (define_insn "sse2_ashlti3" | |
21231 | [(set (match_operand:TI 0 "register_operand" "=x") | |
21232 | (unspec:TI | |
21233 | [(ashift:TI (match_operand:TI 1 "register_operand" "0") | |
21234 | (mult:SI (match_operand:SI 2 "immediate_operand" "i") | |
8ee41eaf | 21235 | (const_int 8)))] UNSPEC_NOP))] |
fbe5eb6d BS |
21236 | "TARGET_SSE2" |
21237 | "pslldq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21238 | [(set_attr "type" "sseishft") |
21239 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21240 | |
21241 | (define_insn "sse2_lshrti3" | |
21242 | [(set (match_operand:TI 0 "register_operand" "=x") | |
21243 | (unspec:TI | |
21244 | [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0") | |
21245 | (mult:SI (match_operand:SI 2 "immediate_operand" "i") | |
8ee41eaf | 21246 | (const_int 8)))] UNSPEC_NOP))] |
fbe5eb6d BS |
21247 | "TARGET_SSE2" |
21248 | "pslrdq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21249 | [(set_attr "type" "sseishft") |
21250 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21251 | |
21252 | ;; SSE unpack | |
21253 | ||
21254 | (define_insn "sse2_unpckhpd" | |
21255 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
21256 | (vec_concat:V2DF | |
21257 | (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
21258 | (parallel [(const_int 1)])) | |
21259 | (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x") | |
21260 | (parallel [(const_int 0)]))))] | |
21261 | "TARGET_SSE2" | |
21262 | "unpckhpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21263 | [(set_attr "type" "ssecvt") |
21264 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21265 | |
21266 | (define_insn "sse2_unpcklpd" | |
21267 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
21268 | (vec_concat:V2DF | |
21269 | (vec_select:V2DF (match_operand:V2DF 1 "register_operand" "0") | |
21270 | (parallel [(const_int 0)])) | |
21271 | (vec_select:V2DF (match_operand:V2DF 2 "register_operand" "x") | |
21272 | (parallel [(const_int 1)]))))] | |
21273 | "TARGET_SSE2" | |
21274 | "unpcklpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21275 | [(set_attr "type" "ssecvt") |
21276 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21277 | |
21278 | ;; MMX pack/unpack insns. | |
21279 | ||
21280 | (define_insn "sse2_packsswb" | |
21281 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
21282 | (vec_concat:V16QI | |
21283 | (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0")) | |
21284 | (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))] | |
21285 | "TARGET_SSE2" | |
21286 | "packsswb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21287 | [(set_attr "type" "ssecvt") |
21288 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21289 | |
21290 | (define_insn "sse2_packssdw" | |
21291 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21292 | (vec_concat:V8HI | |
21293 | (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0")) | |
21294 | (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))] | |
21295 | "TARGET_SSE2" | |
21296 | "packssdw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21297 | [(set_attr "type" "ssecvt") |
21298 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21299 | |
21300 | (define_insn "sse2_packuswb" | |
21301 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
21302 | (vec_concat:V16QI | |
21303 | (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0")) | |
21304 | (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))] | |
21305 | "TARGET_SSE2" | |
21306 | "packuswb\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21307 | [(set_attr "type" "ssecvt") |
21308 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21309 | |
21310 | (define_insn "sse2_punpckhbw" | |
21311 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
21312 | (vec_merge:V16QI | |
21313 | (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
21314 | (parallel [(const_int 8) (const_int 0) | |
21315 | (const_int 9) (const_int 1) | |
21316 | (const_int 10) (const_int 2) | |
21317 | (const_int 11) (const_int 3) | |
21318 | (const_int 12) (const_int 4) | |
21319 | (const_int 13) (const_int 5) | |
21320 | (const_int 14) (const_int 6) | |
21321 | (const_int 15) (const_int 7)])) | |
21322 | (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x") | |
21323 | (parallel [(const_int 0) (const_int 8) | |
21324 | (const_int 1) (const_int 9) | |
21325 | (const_int 2) (const_int 10) | |
21326 | (const_int 3) (const_int 11) | |
21327 | (const_int 4) (const_int 12) | |
21328 | (const_int 5) (const_int 13) | |
21329 | (const_int 6) (const_int 14) | |
21330 | (const_int 7) (const_int 15)])) | |
21331 | (const_int 21845)))] | |
21332 | "TARGET_SSE2" | |
21333 | "punpckhbw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21334 | [(set_attr "type" "ssecvt") |
21335 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21336 | |
21337 | (define_insn "sse2_punpckhwd" | |
21338 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21339 | (vec_merge:V8HI | |
21340 | (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
21341 | (parallel [(const_int 4) (const_int 0) | |
21342 | (const_int 5) (const_int 1) | |
21343 | (const_int 6) (const_int 2) | |
21344 | (const_int 7) (const_int 3)])) | |
21345 | (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x") | |
21346 | (parallel [(const_int 0) (const_int 4) | |
21347 | (const_int 1) (const_int 5) | |
21348 | (const_int 2) (const_int 6) | |
21349 | (const_int 3) (const_int 7)])) | |
21350 | (const_int 85)))] | |
21351 | "TARGET_SSE2" | |
21352 | "punpckhwd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21353 | [(set_attr "type" "ssecvt") |
21354 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21355 | |
21356 | (define_insn "sse2_punpckhdq" | |
21357 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21358 | (vec_merge:V4SI | |
21359 | (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
21360 | (parallel [(const_int 2) (const_int 0) | |
21361 | (const_int 3) (const_int 1)])) | |
21362 | (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x") | |
21363 | (parallel [(const_int 0) (const_int 2) | |
21364 | (const_int 1) (const_int 3)])) | |
21365 | (const_int 5)))] | |
21366 | "TARGET_SSE2" | |
21367 | "punpckhdq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21368 | [(set_attr "type" "ssecvt") |
21369 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21370 | |
21371 | (define_insn "sse2_punpcklbw" | |
21372 | [(set (match_operand:V16QI 0 "register_operand" "=x") | |
21373 | (vec_merge:V16QI | |
21374 | (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0") | |
21375 | (parallel [(const_int 0) (const_int 8) | |
21376 | (const_int 1) (const_int 9) | |
21377 | (const_int 2) (const_int 10) | |
21378 | (const_int 3) (const_int 11) | |
21379 | (const_int 4) (const_int 12) | |
21380 | (const_int 5) (const_int 13) | |
21381 | (const_int 6) (const_int 14) | |
21382 | (const_int 7) (const_int 15)])) | |
21383 | (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x") | |
21384 | (parallel [(const_int 8) (const_int 0) | |
21385 | (const_int 9) (const_int 1) | |
21386 | (const_int 10) (const_int 2) | |
21387 | (const_int 11) (const_int 3) | |
21388 | (const_int 12) (const_int 4) | |
21389 | (const_int 13) (const_int 5) | |
21390 | (const_int 14) (const_int 6) | |
21391 | (const_int 15) (const_int 7)])) | |
21392 | (const_int 21845)))] | |
21393 | "TARGET_SSE2" | |
21394 | "punpcklbw\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21395 | [(set_attr "type" "ssecvt") |
21396 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21397 | |
21398 | (define_insn "sse2_punpcklwd" | |
21399 | [(set (match_operand:V8HI 0 "register_operand" "=x") | |
21400 | (vec_merge:V8HI | |
21401 | (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0") | |
21402 | (parallel [(const_int 0) (const_int 4) | |
21403 | (const_int 1) (const_int 5) | |
21404 | (const_int 2) (const_int 6) | |
21405 | (const_int 3) (const_int 7)])) | |
21406 | (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x") | |
21407 | (parallel [(const_int 4) (const_int 0) | |
21408 | (const_int 5) (const_int 1) | |
21409 | (const_int 6) (const_int 2) | |
21410 | (const_int 7) (const_int 3)])) | |
21411 | (const_int 85)))] | |
21412 | "TARGET_SSE2" | |
21413 | "punpcklwd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21414 | [(set_attr "type" "ssecvt") |
21415 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21416 | |
21417 | (define_insn "sse2_punpckldq" | |
21418 | [(set (match_operand:V4SI 0 "register_operand" "=x") | |
21419 | (vec_merge:V4SI | |
21420 | (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0") | |
21421 | (parallel [(const_int 0) (const_int 2) | |
21422 | (const_int 1) (const_int 3)])) | |
21423 | (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x") | |
21424 | (parallel [(const_int 2) (const_int 0) | |
21425 | (const_int 3) (const_int 1)])) | |
21426 | (const_int 5)))] | |
21427 | "TARGET_SSE2" | |
21428 | "punpckldq\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21429 | [(set_attr "type" "ssecvt") |
21430 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21431 | |
21432 | ;; SSE2 moves | |
21433 | ||
21434 | (define_insn "sse2_movapd" | |
21435 | [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") | |
8ee41eaf RH |
21436 | (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")] |
21437 | UNSPEC_MOVA))] | |
fbe5eb6d BS |
21438 | "TARGET_SSE2" |
21439 | "@ | |
21440 | movapd\t{%1, %0|%0, %1} | |
21441 | movapd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
21442 | [(set_attr "type" "ssemov") |
21443 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
21444 | |
21445 | (define_insn "sse2_movupd" | |
21446 | [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") | |
8ee41eaf RH |
21447 | (unspec:V2DF [(match_operand:V2DF 1 "general_operand" "xm,x")] |
21448 | UNSPEC_MOVU))] | |
fbe5eb6d BS |
21449 | "TARGET_SSE2" |
21450 | "@ | |
21451 | movupd\t{%1, %0|%0, %1} | |
21452 | movupd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
21453 | [(set_attr "type" "ssecvt") |
21454 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
21455 | |
21456 | (define_insn "sse2_movdqa" | |
21457 | [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m") | |
8ee41eaf RH |
21458 | (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")] |
21459 | UNSPEC_MOVA))] | |
fbe5eb6d BS |
21460 | "TARGET_SSE2" |
21461 | "@ | |
21462 | movdqa\t{%1, %0|%0, %1} | |
21463 | movdqa\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
21464 | [(set_attr "type" "ssemov") |
21465 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21466 | |
21467 | (define_insn "sse2_movdqu" | |
21468 | [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m") | |
8ee41eaf RH |
21469 | (unspec:TI [(match_operand:TI 1 "general_operand" "xm,x")] |
21470 | UNSPEC_MOVU))] | |
fbe5eb6d BS |
21471 | "TARGET_SSE2" |
21472 | "@ | |
21473 | movdqu\t{%1, %0|%0, %1} | |
21474 | movdqu\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
21475 | [(set_attr "type" "ssecvt") |
21476 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21477 | |
21478 | (define_insn "sse2_movdq2q" | |
21479 | [(set (match_operand:DI 0 "nonimmediate_operand" "=y") | |
21480 | (vec_select:DI (match_operand:V2DI 1 "general_operand" "x") | |
21481 | (parallel [(const_int 0)])))] | |
21482 | "TARGET_SSE2" | |
21483 | "movdq2q\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
21484 | [(set_attr "type" "ssecvt") |
21485 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21486 | |
21487 | (define_insn "sse2_movq2dq" | |
21488 | [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x") | |
21489 | (vec_concat:V2DI (match_operand:DI 1 "general_operand" "y") | |
21490 | (const_vector:DI [(const_int 0)])))] | |
21491 | "TARGET_SSE2" | |
21492 | "movq2dq\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
21493 | [(set_attr "type" "ssecvt") |
21494 | (set_attr "mode" "TI")]) | |
fbe5eb6d BS |
21495 | |
21496 | (define_insn "sse2_movhpd" | |
21497 | [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") | |
21498 | (vec_merge:V2DF | |
21499 | (match_operand:V2DF 1 "nonimmediate_operand" "0,0") | |
21500 | (match_operand:V2DF 2 "nonimmediate_operand" "m,x") | |
21501 | (const_int 2)))] | |
21502 | "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" | |
21503 | "movhpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21504 | [(set_attr "type" "ssecvt") |
21505 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
21506 | |
21507 | (define_insn "sse2_movlpd" | |
21508 | [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m") | |
21509 | (vec_merge:V2DF | |
21510 | (match_operand:V2DF 1 "nonimmediate_operand" "0,0") | |
21511 | (match_operand:V2DF 2 "nonimmediate_operand" "m,x") | |
21512 | (const_int 1)))] | |
21513 | "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)" | |
21514 | "movlpd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21515 | [(set_attr "type" "ssecvt") |
21516 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
21517 | |
21518 | (define_insn "sse2_loadsd" | |
21519 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
21520 | (vec_merge:V2DF | |
21521 | (match_operand:DF 1 "memory_operand" "m") | |
21522 | (vec_duplicate:DF (float:DF (const_int 0))) | |
21523 | (const_int 1)))] | |
21524 | "TARGET_SSE2" | |
21525 | "movsd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
21526 | [(set_attr "type" "ssecvt") |
21527 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
21528 | |
21529 | (define_insn "sse2_movsd" | |
21530 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
21531 | (vec_merge:V2DF | |
21532 | (match_operand:V2DF 1 "register_operand" "0") | |
21533 | (match_operand:V2DF 2 "register_operand" "x") | |
21534 | (const_int 1)))] | |
21535 | "TARGET_SSE2" | |
21536 | "movsd\t{%2, %0|%0, %2}" | |
3d34cd91 JH |
21537 | [(set_attr "type" "ssecvt") |
21538 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
21539 | |
21540 | (define_insn "sse2_storesd" | |
21541 | [(set (match_operand:DF 0 "memory_operand" "=m") | |
21542 | (vec_select:DF | |
21543 | (match_operand:V2DF 1 "register_operand" "x") | |
21544 | (parallel [(const_int 0)])))] | |
21545 | "TARGET_SSE2" | |
21546 | "movsd\t{%1, %0|%0, %1}" | |
3d34cd91 JH |
21547 | [(set_attr "type" "ssecvt") |
21548 | (set_attr "mode" "DF")]) | |
fbe5eb6d BS |
21549 | |
21550 | (define_insn "sse2_shufpd" | |
21551 | [(set (match_operand:V2DF 0 "register_operand" "=x") | |
21552 | (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") | |
21553 | (match_operand:V2DF 2 "nonimmediate_operand" "xm") | |
8ee41eaf RH |
21554 | (match_operand:SI 3 "immediate_operand" "i")] |
21555 | UNSPEC_SHUFFLE))] | |
fbe5eb6d BS |
21556 | "TARGET_SSE2" |
21557 | ;; @@@ check operand order for intel/nonintel syntax | |
21558 | "shufpd\t{%3, %2, %0|%0, %2, %3}" | |
3d34cd91 JH |
21559 | [(set_attr "type" "ssecvt") |
21560 | (set_attr "mode" "V2DF")]) | |
fbe5eb6d BS |
21561 | |
21562 | (define_insn "sse2_clflush" | |
8ee41eaf RH |
21563 | [(unspec_volatile [(match_operand:SI 0 "address_operand" "p")] |
21564 | UNSPECV_CLFLUSH)] | |
fbe5eb6d BS |
21565 | "TARGET_SSE2" |
21566 | "clflush %0" | |
3d34cd91 JH |
21567 | [(set_attr "type" "sse") |
21568 | (set_attr "memory" "unknown")]) | |
fbe5eb6d BS |
21569 | |
21570 | (define_expand "sse2_mfence" | |
21571 | [(set (match_dup 0) | |
8ee41eaf | 21572 | (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] |
fbe5eb6d BS |
21573 | "TARGET_SSE2" |
21574 | { | |
21575 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
21576 | MEM_VOLATILE_P (operands[0]) = 1; | |
21577 | }) | |
21578 | ||
21579 | (define_insn "*mfence_insn" | |
21580 | [(set (match_operand:BLK 0 "" "") | |
8ee41eaf | 21581 | (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] |
fbe5eb6d BS |
21582 | "TARGET_SSE2" |
21583 | "mfence" | |
21584 | [(set_attr "type" "sse") | |
21585 | (set_attr "memory" "unknown")]) | |
21586 | ||
21587 | (define_expand "sse2_lfence" | |
21588 | [(set (match_dup 0) | |
8ee41eaf | 21589 | (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))] |
fbe5eb6d BS |
21590 | "TARGET_SSE2" |
21591 | { | |
21592 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
21593 | MEM_VOLATILE_P (operands[0]) = 1; | |
21594 | }) | |
21595 | ||
21596 | (define_insn "*lfence_insn" | |
21597 | [(set (match_operand:BLK 0 "" "") | |
8ee41eaf | 21598 | (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))] |
fbe5eb6d BS |
21599 | "TARGET_SSE2" |
21600 | "lfence" | |
21601 | [(set_attr "type" "sse") | |
21602 | (set_attr "memory" "unknown")]) |