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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
cf011243 | 2 | Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
9184f892 | 3 | 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
c98f8742 | 4 | |
188fc5b5 | 5 | This file is part of GCC. |
c98f8742 | 6 | |
188fc5b5 | 7 | GCC is free software; you can redistribute it and/or modify |
c98f8742 JVA |
8 | it under the terms of the GNU General Public License as published by |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
188fc5b5 | 12 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
188fc5b5 | 18 | along with GCC; see the file COPYING. If not, write to |
97aadbb9 | 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
892a2d68 | 20 | Boston, MA 02111-1307, USA. */ |
c98f8742 JVA |
21 | |
22 | /* The purpose of this file is to define the characteristics of the i386, | |
b4ac57ab | 23 | independent of assembler syntax or operating system. |
c98f8742 JVA |
24 | |
25 | Three other files build on this one to describe a specific assembler syntax: | |
26 | bsd386.h, att386.h, and sun386.h. | |
27 | ||
28 | The actual tm.h file for a particular system should include | |
29 | this file, and then the file for the appropriate assembler syntax. | |
30 | ||
31 | Many macros that specify assembler syntax are omitted entirely from | |
32 | this file because they really belong in the files for particular | |
e075ae69 RH |
33 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, |
34 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
35 | that start with ASM_ or end in ASM_OP. */ | |
c98f8742 | 36 | |
d4ba09c0 SC |
37 | /* Define the specific costs for a given cpu */ |
38 | ||
39 | struct processor_costs { | |
8b60264b KG |
40 | const int add; /* cost of an add instruction */ |
41 | const int lea; /* cost of a lea instruction */ | |
42 | const int shift_var; /* variable shift costs */ | |
43 | const int shift_const; /* constant shift costs */ | |
f676971a | 44 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 45 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 46 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 47 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 48 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
49 | int movsx; /* The cost of movsx operation. */ |
50 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
51 | const int large_insn; /* insns larger than this cost more */ |
52 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 53 | memory-to-memory move insns. */ |
8b60264b KG |
54 | const int movzbl_load; /* cost of loading using movzbl */ |
55 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
56 | in QImode, HImode and SImode relative |
57 | to reg-reg move (2). */ | |
8b60264b | 58 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 59 | in QImode, HImode and SImode */ |
8b60264b KG |
60 | const int fp_move; /* cost of reg,reg fld/fst */ |
61 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 62 | in SFmode, DFmode and XFmode */ |
8b60264b | 63 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 64 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
65 | const int mmx_move; /* cost of moving MMX register. */ |
66 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 67 | in SImode and DImode */ |
8b60264b | 68 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 69 | in SImode and DImode */ |
8b60264b KG |
70 | const int sse_move; /* cost of moving SSE register. */ |
71 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 72 | in SImode, DImode and TImode*/ |
8b60264b | 73 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 74 | in SImode, DImode and TImode*/ |
8b60264b | 75 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 76 | integer and vice versa. */ |
f4365627 JH |
77 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
78 | const int simultaneous_prefetches; /* number of parallel prefetch | |
79 | operations. */ | |
4977bab6 | 80 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
81 | const int fadd; /* cost of FADD and FSUB instructions. */ |
82 | const int fmul; /* cost of FMUL instruction. */ | |
83 | const int fdiv; /* cost of FDIV instruction. */ | |
84 | const int fabs; /* cost of FABS instruction. */ | |
85 | const int fchs; /* cost of FCHS instruction. */ | |
86 | const int fsqrt; /* cost of FSQRT instruction. */ | |
d4ba09c0 SC |
87 | }; |
88 | ||
8b60264b | 89 | extern const struct processor_costs *ix86_cost; |
d4ba09c0 | 90 | |
c98f8742 JVA |
91 | /* Run-time compilation parameters selecting different hardware subsets. */ |
92 | ||
93 | extern int target_flags; | |
94 | ||
95 | /* Macros used in the machine description to test the flags. */ | |
96 | ||
ddd5a7c1 | 97 | /* configure can arrange to make this 2, to force a 486. */ |
e075ae69 | 98 | |
35b528be | 99 | #ifndef TARGET_CPU_DEFAULT |
10e9fecc JH |
100 | #ifdef TARGET_64BIT_DEFAULT |
101 | #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8 | |
102 | #else | |
35b528be RS |
103 | #define TARGET_CPU_DEFAULT 0 |
104 | #endif | |
10e9fecc | 105 | #endif |
35b528be | 106 | |
3b3c6a3f | 107 | /* Masks for the -m switches */ |
e075ae69 RH |
108 | #define MASK_80387 0x00000001 /* Hardware floating point */ |
109 | #define MASK_RTD 0x00000002 /* Use ret that pops args */ | |
110 | #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ | |
111 | #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ | |
112 | #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ | |
113 | #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ | |
114 | #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ | |
115 | #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ | |
116 | #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ | |
0dd0e980 JH |
117 | #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ |
118 | #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ | |
119 | #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ | |
120 | #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ | |
9ef1b13a RH |
121 | #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */ |
122 | #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */ | |
123 | #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */ | |
9e200aaf | 124 | #define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */ |
22c7c85e L |
125 | #define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */ |
126 | #define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */ | |
127 | #define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */ | |
128 | #define MASK_64BIT 0x00100000 /* Produce 64bit code */ | |
129 | #define MASK_MS_BITFIELD_LAYOUT 0x00200000 /* Use native (MS) bitfield layout */ | |
130 | #define MASK_TLS_DIRECT_SEG_REFS 0x00400000 /* Avoid adding %gs:0 */ | |
9ef1b13a | 131 | |
4977bab6 | 132 | /* Unused: 0x03e0000 */ |
9ef1b13a | 133 | |
c93e80a5 JH |
134 | /* ... overlap with subtarget options starts by 0x04000000. */ |
135 | #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ | |
3b3c6a3f MM |
136 | |
137 | /* Use the floating point instructions */ | |
138 | #define TARGET_80387 (target_flags & MASK_80387) | |
139 | ||
c98f8742 JVA |
140 | /* Compile using ret insn that pops args. |
141 | This will not work unless you use prototypes at least | |
fce5a9f2 | 142 | for all functions that can take varying numbers of args. */ |
3b3c6a3f MM |
143 | #define TARGET_RTD (target_flags & MASK_RTD) |
144 | ||
b08de47e MM |
145 | /* Align doubles to a two word boundary. This breaks compatibility with |
146 | the published ABI's for structures containing doubles, but produces | |
147 | faster code on the pentium. */ | |
148 | #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) | |
c98f8742 | 149 | |
f73ad30e JH |
150 | /* Use push instructions to save outgoing args. */ |
151 | #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) | |
152 | ||
153 | /* Accumulate stack adjustments to prologue/epilogue. */ | |
154 | #define TARGET_ACCUMULATE_OUTGOING_ARGS \ | |
155 | (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) | |
156 | ||
d7cd15e9 RS |
157 | /* Put uninitialized locals into bss, not data. |
158 | Meaningful only on svr3. */ | |
3b3c6a3f | 159 | #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) |
d7cd15e9 | 160 | |
c572e5ba JVA |
161 | /* Use IEEE floating point comparisons. These handle correctly the cases |
162 | where the result of a comparison is unordered. Normally SIGFPE is | |
163 | generated in such cases, in which case this isn't needed. */ | |
3b3c6a3f | 164 | #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) |
c572e5ba | 165 | |
8c2bf92a JVA |
166 | /* Functions that return a floating point value may return that value |
167 | in the 387 FPU or in 386 integer registers. If set, this flag causes | |
892a2d68 | 168 | the 387 to be used, which is compatible with most calling conventions. */ |
3b3c6a3f | 169 | #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) |
8c2bf92a | 170 | |
2b589241 | 171 | /* Long double is 128bit instead of 96bit, even when only 80bits are used. |
f5143c46 | 172 | This mode wastes cache, but avoid misaligned data accesses and simplifies |
2b589241 JH |
173 | address calculations. */ |
174 | #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) | |
175 | ||
099800e3 RK |
176 | /* Disable generation of FP sin, cos and sqrt operations for 387. |
177 | This is because FreeBSD lacks these in the math-emulator-code */ | |
3b3c6a3f MM |
178 | #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) |
179 | ||
ba2baa55 RS |
180 | /* Generate 387 floating point intrinsics for the current target. */ |
181 | #define TARGET_USE_FANCY_MATH_387 (! TARGET_NO_FANCY_MATH_387) | |
182 | ||
2f2fa5b1 | 183 | /* Don't create frame pointers for leaf functions */ |
e075ae69 RH |
184 | #define TARGET_OMIT_LEAF_FRAME_POINTER \ |
185 | (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) | |
f6f58ba3 | 186 | |
3b3c6a3f | 187 | /* Debug GO_IF_LEGITIMATE_ADDRESS */ |
c93e80a5 | 188 | #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) |
3b3c6a3f | 189 | |
b08de47e | 190 | /* Debug FUNCTION_ARG macros */ |
c93e80a5 | 191 | #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) |
b08de47e | 192 | |
5791cc29 JT |
193 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
194 | compile-time constant. */ | |
195 | #ifdef IN_LIBGCC2 | |
196 | #ifdef __x86_64__ | |
197 | #define TARGET_64BIT 1 | |
198 | #else | |
199 | #define TARGET_64BIT 0 | |
200 | #endif | |
201 | #else | |
0c2dc519 | 202 | #ifdef TARGET_BI_ARCH |
25f94bb5 | 203 | #define TARGET_64BIT (target_flags & MASK_64BIT) |
0c2dc519 | 204 | #else |
67adf6a9 | 205 | #if TARGET_64BIT_DEFAULT |
0c2dc519 JH |
206 | #define TARGET_64BIT 1 |
207 | #else | |
208 | #define TARGET_64BIT 0 | |
209 | #endif | |
210 | #endif | |
5791cc29 | 211 | #endif |
25f94bb5 | 212 | |
750054a2 CT |
213 | #define HAS_LONG_COND_BRANCH 1 |
214 | #define HAS_LONG_UNCOND_BRANCH 1 | |
215 | ||
74dc3e94 RH |
216 | /* Avoid adding %gs:0 in TLS references; use %gs:address directly. */ |
217 | #define TARGET_TLS_DIRECT_SEG_REFS (target_flags & MASK_TLS_DIRECT_SEG_REFS) | |
218 | ||
9e555526 RH |
219 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
220 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
221 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
222 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
223 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) | |
224 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
225 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
226 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
4977bab6 | 227 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
89c43c0a | 228 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
a269a03c | 229 | |
9e555526 | 230 | #define TUNEMASK (1 << ix86_tune) |
a269a03c JC |
231 | extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; |
232 | extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; | |
ef6257cd | 233 | extern const int x86_branch_hints, x86_unroll_strlen; |
e075ae69 RH |
234 | extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; |
235 | extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; | |
236 | extern const int x86_use_cltd, x86_read_modify_write; | |
237 | extern const int x86_read_modify, x86_split_long_moves; | |
285464d0 | 238 | extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; |
d9f32422 | 239 | extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; |
0b5107cf | 240 | extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; |
bdeb029c | 241 | extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; |
0b5107cf | 242 | extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; |
c6036a37 | 243 | extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; |
b972dd02 | 244 | extern const int x86_epilogue_using_move, x86_decompose_lea; |
495333a6 | 245 | extern const int x86_arch_always_fancy_math_387, x86_shift1; |
4977bab6 ZW |
246 | extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs; |
247 | extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; | |
248 | extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss; | |
ad7b96a9 | 249 | extern const int x86_inter_unit_moves, x86_schedule; |
7cacf53e | 250 | extern const int x86_use_bt; |
f4365627 | 251 | extern int x86_prefetch_sse; |
a269a03c | 252 | |
9e555526 RH |
253 | #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) |
254 | #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) | |
255 | #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK) | |
256 | #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK) | |
257 | #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK) | |
0644b628 JH |
258 | /* For sane SSE instruction set generation we need fcomi instruction. It is |
259 | safe to enable all CMOVE instructions. */ | |
260 | #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) | |
9e555526 RH |
261 | #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK) |
262 | #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK) | |
263 | #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK) | |
264 | #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) | |
265 | #define TARGET_MOVX (x86_movx & TUNEMASK) | |
266 | #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) | |
267 | #define TARGET_USE_LOOP (x86_use_loop & TUNEMASK) | |
268 | #define TARGET_USE_FIOP (x86_use_fiop & TUNEMASK) | |
269 | #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) | |
270 | #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK) | |
271 | #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK) | |
272 | #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK) | |
273 | #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK) | |
274 | #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK) | |
275 | #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK) | |
276 | #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK) | |
277 | #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK) | |
278 | #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK) | |
279 | #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK) | |
280 | #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK) | |
281 | #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK) | |
282 | #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK) | |
283 | #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK) | |
284 | #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK) | |
285 | #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK) | |
286 | #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) | |
4977bab6 | 287 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ |
9e555526 RH |
288 | (x86_sse_partial_reg_dependency & TUNEMASK) |
289 | #define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & TUNEMASK) | |
4977bab6 | 290 | #define TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS \ |
9e555526 RH |
291 | (x86_sse_partial_regs_for_cvtsd2ss & TUNEMASK) |
292 | #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) | |
293 | #define TARGET_SSE_TYPELESS_LOAD0 (x86_sse_typeless_load0 & TUNEMASK) | |
294 | #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) | |
295 | #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) | |
296 | #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK) | |
297 | #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK) | |
298 | #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK) | |
f4365627 | 299 | #define TARGET_PREFETCH_SSE (x86_prefetch_sse) |
9e555526 RH |
300 | #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK) |
301 | #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK) | |
302 | #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK) | |
303 | #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK) | |
be04394b | 304 | #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK) |
ad7b96a9 | 305 | #define TARGET_SCHEDULE (x86_schedule & TUNEMASK) |
7cacf53e | 306 | #define TARGET_USE_BT (x86_use_bt & TUNEMASK) |
a269a03c | 307 | |
8c9be447 | 308 | #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) |
3b3c6a3f | 309 | |
79f05c19 JH |
310 | #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) |
311 | #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) | |
312 | ||
c93e80a5 | 313 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
e075ae69 | 314 | |
37f22004 | 315 | #define TARGET_SSE ((target_flags & MASK_SSE) != 0) |
446988df | 316 | #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) |
9e200aaf | 317 | #define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0) |
965f5423 JH |
318 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) |
319 | #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ | |
320 | && (ix86_fpmath & FPMATH_387)) | |
a7180f70 | 321 | #define TARGET_MMX ((target_flags & MASK_MMX) != 0) |
47f339cf BS |
322 | #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) |
323 | #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) | |
a7180f70 | 324 | |
8362f420 JH |
325 | #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) |
326 | ||
4977bab6 ZW |
327 | #define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT) |
328 | ||
f996902d RH |
329 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) |
330 | #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) | |
331 | ||
a5d17ff3 PT |
332 | /* WARNING: Do not mark empty strings for translation, as calling |
333 | gettext on an empty string does NOT return an empty | |
43f3a59d | 334 | string. */ |
a5d17ff3 PT |
335 | |
336 | ||
e075ae69 | 337 | #define TARGET_SWITCHES \ |
047142d3 PT |
338 | { { "80387", MASK_80387, N_("Use hardware fp") }, \ |
339 | { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ | |
340 | { "hard-float", MASK_80387, N_("Use hardware fp") }, \ | |
341 | { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ | |
342 | { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ | |
a5d17ff3 PT |
343 | { "386", 0, "" /*Deprecated.*/}, \ |
344 | { "486", 0, "" /*Deprecated.*/}, \ | |
345 | { "pentium", 0, "" /*Deprecated.*/}, \ | |
346 | { "pentiumpro", 0, "" /*Deprecated.*/}, \ | |
347 | { "intel-syntax", 0, "" /*Deprecated.*/}, \ | |
348 | { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ | |
047142d3 PT |
349 | { "rtd", MASK_RTD, \ |
350 | N_("Alternate calling convention") }, \ | |
351 | { "no-rtd", -MASK_RTD, \ | |
352 | N_("Use normal calling convention") }, \ | |
e075ae69 | 353 | { "align-double", MASK_ALIGN_DOUBLE, \ |
047142d3 | 354 | N_("Align some doubles on dword boundary") }, \ |
e075ae69 | 355 | { "no-align-double", -MASK_ALIGN_DOUBLE, \ |
047142d3 | 356 | N_("Align doubles on word boundary") }, \ |
e075ae69 | 357 | { "svr3-shlib", MASK_SVR3_SHLIB, \ |
047142d3 | 358 | N_("Uninitialized locals in .bss") }, \ |
e075ae69 | 359 | { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ |
047142d3 | 360 | N_("Uninitialized locals in .data") }, \ |
e075ae69 | 361 | { "ieee-fp", MASK_IEEE_FP, \ |
047142d3 | 362 | N_("Use IEEE math for fp comparisons") }, \ |
e075ae69 | 363 | { "no-ieee-fp", -MASK_IEEE_FP, \ |
047142d3 | 364 | N_("Do not use IEEE math for fp comparisons") }, \ |
e075ae69 | 365 | { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ |
047142d3 | 366 | N_("Return values of functions in FPU registers") }, \ |
e075ae69 | 367 | { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ |
047142d3 | 368 | N_("Do not return values of functions in FPU registers")}, \ |
e075ae69 | 369 | { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ |
047142d3 | 370 | N_("Do not generate sin, cos, sqrt for FPU") }, \ |
e075ae69 | 371 | { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ |
047142d3 | 372 | N_("Generate sin, cos, sqrt for FPU")}, \ |
e075ae69 | 373 | { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ |
047142d3 | 374 | N_("Omit the frame pointer in leaf functions") }, \ |
e075ae69 | 375 | { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ |
047142d3 PT |
376 | { "stack-arg-probe", MASK_STACK_PROBE, \ |
377 | N_("Enable stack probing") }, \ | |
e075ae69 RH |
378 | { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ |
379 | { "windows", 0, 0 /* undocumented */ }, \ | |
380 | { "dll", 0, 0 /* undocumented */ }, \ | |
79f05c19 | 381 | { "align-stringops", -MASK_NO_ALIGN_STROPS, \ |
047142d3 | 382 | N_("Align destination of the string operations") }, \ |
79f05c19 | 383 | { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ |
047142d3 | 384 | N_("Do not align destination of the string operations") }, \ |
4be2e5d9 | 385 | { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ |
047142d3 | 386 | N_("Inline all known string operations") }, \ |
79f05c19 | 387 | { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ |
047142d3 | 388 | N_("Do not inline all known string operations") }, \ |
f73ad30e | 389 | { "push-args", -MASK_NO_PUSH_ARGS, \ |
047142d3 | 390 | N_("Use push instructions to save outgoing arguments") }, \ |
053f1126 | 391 | { "no-push-args", MASK_NO_PUSH_ARGS, \ |
047142d3 | 392 | N_("Do not use push instructions to save outgoing arguments") }, \ |
9ef1b13a | 393 | { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \ |
047142d3 | 394 | N_("Use push instructions to save outgoing arguments") }, \ |
9ef1b13a | 395 | { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \ |
047142d3 | 396 | N_("Do not use push instructions to save outgoing arguments") }, \ |
9ef1b13a | 397 | { "mmx", MASK_MMX, \ |
b0287a90 | 398 | N_("Support MMX built-in functions") }, \ |
0dd0e980 | 399 | { "no-mmx", -MASK_MMX, \ |
b0287a90 | 400 | N_("Do not support MMX built-in functions") }, \ |
9ef1b13a | 401 | { "3dnow", MASK_3DNOW, \ |
b0287a90 | 402 | N_("Support 3DNow! built-in functions") }, \ |
9ef1b13a | 403 | { "no-3dnow", -MASK_3DNOW, \ |
b0287a90 | 404 | N_("Do not support 3DNow! built-in functions") }, \ |
9ef1b13a | 405 | { "sse", MASK_SSE, \ |
b0287a90 | 406 | N_("Support MMX and SSE built-in functions and code generation") }, \ |
9ef1b13a | 407 | { "no-sse", -MASK_SSE, \ |
b0287a90 | 408 | N_("Do not support MMX and SSE built-in functions and code generation") },\ |
22c7c85e | 409 | { "sse2", MASK_SSE2, \ |
b0287a90 | 410 | N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ |
9ef1b13a | 411 | { "no-sse2", -MASK_SSE2, \ |
b0287a90 | 412 | N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ |
9e200aaf KC |
413 | { "sse3", MASK_SSE3, \ |
414 | N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\ | |
415 | { "no-sse3", -MASK_SSE3, \ | |
416 | N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\ | |
2b589241 | 417 | { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ |
c725bd79 | 418 | N_("sizeof(long double) is 16") }, \ |
2b589241 | 419 | { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ |
c725bd79 | 420 | N_("sizeof(long double) is 12") }, \ |
25f94bb5 JH |
421 | { "64", MASK_64BIT, \ |
422 | N_("Generate 64bit x86-64 code") }, \ | |
423 | { "32", -MASK_64BIT, \ | |
424 | N_("Generate 32bit i386 code") }, \ | |
4977bab6 ZW |
425 | { "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \ |
426 | N_("Use native (MS) bitfield layout") }, \ | |
427 | { "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \ | |
428 | N_("Use gcc default bitfield layout") }, \ | |
8362f420 JH |
429 | { "red-zone", -MASK_NO_RED_ZONE, \ |
430 | N_("Use red-zone in the x86-64 code") }, \ | |
431 | { "no-red-zone", MASK_NO_RED_ZONE, \ | |
4cba3b67 | 432 | N_("Do not use red-zone in the x86-64 code") }, \ |
74dc3e94 RH |
433 | { "tls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS, \ |
434 | N_("Use direct references against %gs when accessing tls data") }, \ | |
435 | { "no-tls-direct-seg-refs", -MASK_TLS_DIRECT_SEG_REFS, \ | |
436 | N_("Do not use direct references against %gs when accessing tls data") }, \ | |
e075ae69 | 437 | SUBTARGET_SWITCHES \ |
74dc3e94 RH |
438 | { "", \ |
439 | TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT \ | |
440 | | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT, 0 }} | |
241e1a89 | 441 | |
67adf6a9 RH |
442 | #ifndef TARGET_64BIT_DEFAULT |
443 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 444 | #endif |
74dc3e94 RH |
445 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
446 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
447 | #endif | |
25f94bb5 | 448 | |
0ed4a390 JL |
449 | /* Once GDB has been enhanced to deal with functions without frame |
450 | pointers, we can change this to allow for elimination of | |
451 | the frame pointer in leaf functions. */ | |
452 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 453 | |
b069de3b SS |
454 | /* This is not really a target flag, but is done this way so that |
455 | it's analogous to similar code for Mach-O on PowerPC. darwin.h | |
456 | redefines this to 1. */ | |
457 | #define TARGET_MACHO 0 | |
458 | ||
cc69336f RH |
459 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
460 | with the rounding mode forced to 53 bits. */ | |
461 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
462 | ||
f5316dfe MM |
463 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
464 | command options that have values. Its definition is an | |
465 | initializer with a subgrouping for each command option. | |
466 | ||
467 | Each subgrouping contains a string constant, that defines the | |
468 | fixed part of the option name, and the address of a variable. The | |
469 | variable, type `char *', is set to the variable part of the given | |
470 | option if the fixed part matches. The actual option name is made | |
471 | by appending `-m' to the specified name. */ | |
e075ae69 | 472 | #define TARGET_OPTIONS \ |
9e555526 | 473 | { { "tune=", &ix86_tune_string, \ |
c409ea0d | 474 | N_("Schedule code for given CPU"), 0}, \ |
965f5423 | 475 | { "fpmath=", &ix86_fpmath_string, \ |
c409ea0d | 476 | N_("Generate floating point mathematics using given instruction set"), 0},\ |
e075ae69 | 477 | { "arch=", &ix86_arch_string, \ |
c409ea0d | 478 | N_("Generate code for given CPU"), 0}, \ |
e075ae69 | 479 | { "regparm=", &ix86_regparm_string, \ |
c409ea0d | 480 | N_("Number of registers used to pass integer arguments"), 0},\ |
e075ae69 | 481 | { "align-loops=", &ix86_align_loops_string, \ |
c409ea0d | 482 | N_("Loop code aligned to this power of 2"), 0}, \ |
e075ae69 | 483 | { "align-jumps=", &ix86_align_jumps_string, \ |
c409ea0d | 484 | N_("Jump targets are aligned to this power of 2"), 0}, \ |
e075ae69 | 485 | { "align-functions=", &ix86_align_funcs_string, \ |
c409ea0d | 486 | N_("Function starts are aligned to this power of 2"), 0}, \ |
e075ae69 RH |
487 | { "preferred-stack-boundary=", \ |
488 | &ix86_preferred_stack_boundary_string, \ | |
c409ea0d | 489 | N_("Attempt to keep stack aligned to this power of 2"), 0}, \ |
e075ae69 | 490 | { "branch-cost=", &ix86_branch_cost_string, \ |
c409ea0d | 491 | N_("Branches are this expensive (1-5, arbitrary units)"), 0},\ |
6189a572 | 492 | { "cmodel=", &ix86_cmodel_string, \ |
c409ea0d | 493 | N_("Use given x86-64 code model"), 0}, \ |
c93e80a5 | 494 | { "debug-arg", &ix86_debug_arg_string, \ |
43f3a59d | 495 | "" /* Undocumented. */, 0}, \ |
c93e80a5 | 496 | { "debug-addr", &ix86_debug_addr_string, \ |
43f3a59d | 497 | "" /* Undocumented. */, 0}, \ |
c93e80a5 | 498 | { "asm=", &ix86_asm_string, \ |
c409ea0d | 499 | N_("Use given assembler dialect"), 0}, \ |
f996902d | 500 | { "tls-dialect=", &ix86_tls_dialect_string, \ |
c409ea0d | 501 | N_("Use given thread-local storage dialect"), 0}, \ |
e075ae69 | 502 | SUBTARGET_OPTIONS \ |
b08de47e | 503 | } |
f5316dfe MM |
504 | |
505 | /* Sometimes certain combinations of command options do not make | |
506 | sense on a particular target machine. You can define a macro | |
507 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
508 | defined, is executed once just after all the command options have | |
509 | been parsed. | |
510 | ||
511 | Don't use this macro to turn on various extra optimizations for | |
512 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
513 | ||
514 | #define OVERRIDE_OPTIONS override_options () | |
515 | ||
516 | /* These are meant to be redefined in the host dependent files */ | |
95393dfd | 517 | #define SUBTARGET_SWITCHES |
f5316dfe | 518 | #define SUBTARGET_OPTIONS |
95393dfd | 519 | |
d4ba09c0 | 520 | /* Define this to change the optimizations performed by default. */ |
d9a5f180 GS |
521 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
522 | optimization_options ((LEVEL), (SIZE)) | |
d4ba09c0 | 523 | |
7816bea0 DJ |
524 | /* Support for configure-time defaults of some command line options. */ |
525 | #define OPTION_DEFAULT_SPECS \ | |
526 | {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
da2d4c01 JH |
527 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
528 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" } | |
7816bea0 | 529 | |
241e1a89 SC |
530 | /* Specs for the compiler proper */ |
531 | ||
628714d8 RK |
532 | #ifndef CC1_CPU_SPEC |
533 | #define CC1_CPU_SPEC "\ | |
9d913bbf KC |
534 | %{!mtune*: \ |
535 | %{m386:mtune=i386 \ | |
536 | %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \ | |
537 | %{m486:-mtune=i486 \ | |
538 | %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \ | |
539 | %{mpentium:-mtune=pentium \ | |
540 | %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \ | |
541 | %{mpentiumpro:-mtune=pentiumpro \ | |
542 | %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \ | |
543 | %{mcpu=*:-mtune=%* \ | |
544 | %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \ | |
545 | %<mcpu=* \ | |
c93e80a5 JH |
546 | %{mintel-syntax:-masm=intel \ |
547 | %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ | |
548 | %{mno-intel-syntax:-masm=att \ | |
549 | %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" | |
241e1a89 | 550 | #endif |
c98f8742 | 551 | \f |
30efe578 | 552 | /* Target CPU builtins. */ |
1ba7b414 NB |
553 | #define TARGET_CPU_CPP_BUILTINS() \ |
554 | do \ | |
555 | { \ | |
556 | size_t arch_len = strlen (ix86_arch_string); \ | |
9e555526 | 557 | size_t tune_len = strlen (ix86_tune_string); \ |
1ba7b414 | 558 | int last_arch_char = ix86_arch_string[arch_len - 1]; \ |
9e555526 | 559 | int last_tune_char = ix86_tune_string[tune_len - 1]; \ |
1ba7b414 NB |
560 | \ |
561 | if (TARGET_64BIT) \ | |
562 | { \ | |
563 | builtin_assert ("cpu=x86_64"); \ | |
26b0ad13 | 564 | builtin_assert ("machine=x86_64"); \ |
97242ddc JH |
565 | builtin_define ("__amd64"); \ |
566 | builtin_define ("__amd64__"); \ | |
1ba7b414 NB |
567 | builtin_define ("__x86_64"); \ |
568 | builtin_define ("__x86_64__"); \ | |
569 | } \ | |
570 | else \ | |
571 | { \ | |
572 | builtin_assert ("cpu=i386"); \ | |
573 | builtin_assert ("machine=i386"); \ | |
574 | builtin_define_std ("i386"); \ | |
575 | } \ | |
576 | \ | |
9d913bbf | 577 | /* Built-ins based on -mtune= (or -march= if no \ |
9e555526 | 578 | -mtune= given). */ \ |
1ba7b414 NB |
579 | if (TARGET_386) \ |
580 | builtin_define ("__tune_i386__"); \ | |
581 | else if (TARGET_486) \ | |
582 | builtin_define ("__tune_i486__"); \ | |
583 | else if (TARGET_PENTIUM) \ | |
584 | { \ | |
585 | builtin_define ("__tune_i586__"); \ | |
586 | builtin_define ("__tune_pentium__"); \ | |
9e555526 | 587 | if (last_tune_char == 'x') \ |
1ba7b414 NB |
588 | builtin_define ("__tune_pentium_mmx__"); \ |
589 | } \ | |
590 | else if (TARGET_PENTIUMPRO) \ | |
591 | { \ | |
592 | builtin_define ("__tune_i686__"); \ | |
593 | builtin_define ("__tune_pentiumpro__"); \ | |
9e555526 | 594 | switch (last_tune_char) \ |
2e37b0ce RH |
595 | { \ |
596 | case '3': \ | |
597 | builtin_define ("__tune_pentium3__"); \ | |
5efb1046 | 598 | /* FALLTHRU */ \ |
2e37b0ce RH |
599 | case '2': \ |
600 | builtin_define ("__tune_pentium2__"); \ | |
601 | break; \ | |
602 | } \ | |
1ba7b414 NB |
603 | } \ |
604 | else if (TARGET_K6) \ | |
605 | { \ | |
606 | builtin_define ("__tune_k6__"); \ | |
9e555526 | 607 | if (last_tune_char == '2') \ |
1ba7b414 | 608 | builtin_define ("__tune_k6_2__"); \ |
9e555526 | 609 | else if (last_tune_char == '3') \ |
1ba7b414 NB |
610 | builtin_define ("__tune_k6_3__"); \ |
611 | } \ | |
612 | else if (TARGET_ATHLON) \ | |
613 | { \ | |
614 | builtin_define ("__tune_athlon__"); \ | |
615 | /* Only plain "athlon" lacks SSE. */ \ | |
9e555526 | 616 | if (last_tune_char != 'n') \ |
1ba7b414 NB |
617 | builtin_define ("__tune_athlon_sse__"); \ |
618 | } \ | |
4977bab6 ZW |
619 | else if (TARGET_K8) \ |
620 | builtin_define ("__tune_k8__"); \ | |
1ba7b414 NB |
621 | else if (TARGET_PENTIUM4) \ |
622 | builtin_define ("__tune_pentium4__"); \ | |
89c43c0a VM |
623 | else if (TARGET_NOCONA) \ |
624 | builtin_define ("__tune_nocona__"); \ | |
1ba7b414 NB |
625 | \ |
626 | if (TARGET_MMX) \ | |
627 | builtin_define ("__MMX__"); \ | |
628 | if (TARGET_3DNOW) \ | |
629 | builtin_define ("__3dNOW__"); \ | |
630 | if (TARGET_3DNOW_A) \ | |
631 | builtin_define ("__3dNOW_A__"); \ | |
632 | if (TARGET_SSE) \ | |
633 | builtin_define ("__SSE__"); \ | |
634 | if (TARGET_SSE2) \ | |
635 | builtin_define ("__SSE2__"); \ | |
9e200aaf KC |
636 | if (TARGET_SSE3) \ |
637 | builtin_define ("__SSE3__"); \ | |
48ddd46c JH |
638 | if (TARGET_SSE_MATH && TARGET_SSE) \ |
639 | builtin_define ("__SSE_MATH__"); \ | |
640 | if (TARGET_SSE_MATH && TARGET_SSE2) \ | |
641 | builtin_define ("__SSE2_MATH__"); \ | |
1ba7b414 NB |
642 | \ |
643 | /* Built-ins based on -march=. */ \ | |
644 | if (ix86_arch == PROCESSOR_I486) \ | |
645 | { \ | |
646 | builtin_define ("__i486"); \ | |
647 | builtin_define ("__i486__"); \ | |
648 | } \ | |
649 | else if (ix86_arch == PROCESSOR_PENTIUM) \ | |
650 | { \ | |
651 | builtin_define ("__i586"); \ | |
652 | builtin_define ("__i586__"); \ | |
653 | builtin_define ("__pentium"); \ | |
654 | builtin_define ("__pentium__"); \ | |
655 | if (last_arch_char == 'x') \ | |
656 | builtin_define ("__pentium_mmx__"); \ | |
657 | } \ | |
658 | else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ | |
659 | { \ | |
660 | builtin_define ("__i686"); \ | |
661 | builtin_define ("__i686__"); \ | |
662 | builtin_define ("__pentiumpro"); \ | |
663 | builtin_define ("__pentiumpro__"); \ | |
664 | } \ | |
665 | else if (ix86_arch == PROCESSOR_K6) \ | |
666 | { \ | |
667 | \ | |
668 | builtin_define ("__k6"); \ | |
669 | builtin_define ("__k6__"); \ | |
670 | if (last_arch_char == '2') \ | |
671 | builtin_define ("__k6_2__"); \ | |
672 | else if (last_arch_char == '3') \ | |
673 | builtin_define ("__k6_3__"); \ | |
674 | } \ | |
675 | else if (ix86_arch == PROCESSOR_ATHLON) \ | |
676 | { \ | |
677 | builtin_define ("__athlon"); \ | |
678 | builtin_define ("__athlon__"); \ | |
679 | /* Only plain "athlon" lacks SSE. */ \ | |
680 | if (last_arch_char != 'n') \ | |
681 | builtin_define ("__athlon_sse__"); \ | |
682 | } \ | |
4977bab6 ZW |
683 | else if (ix86_arch == PROCESSOR_K8) \ |
684 | { \ | |
685 | builtin_define ("__k8"); \ | |
686 | builtin_define ("__k8__"); \ | |
687 | } \ | |
1ba7b414 NB |
688 | else if (ix86_arch == PROCESSOR_PENTIUM4) \ |
689 | { \ | |
690 | builtin_define ("__pentium4"); \ | |
691 | builtin_define ("__pentium4__"); \ | |
692 | } \ | |
89c43c0a VM |
693 | else if (ix86_arch == PROCESSOR_NOCONA) \ |
694 | { \ | |
695 | builtin_define ("__nocona"); \ | |
696 | builtin_define ("__nocona__"); \ | |
697 | } \ | |
1ba7b414 | 698 | } \ |
30efe578 NB |
699 | while (0) |
700 | ||
f4365627 JH |
701 | #define TARGET_CPU_DEFAULT_i386 0 |
702 | #define TARGET_CPU_DEFAULT_i486 1 | |
703 | #define TARGET_CPU_DEFAULT_pentium 2 | |
91d2f4ba JH |
704 | #define TARGET_CPU_DEFAULT_pentium_mmx 3 |
705 | #define TARGET_CPU_DEFAULT_pentiumpro 4 | |
706 | #define TARGET_CPU_DEFAULT_pentium2 5 | |
707 | #define TARGET_CPU_DEFAULT_pentium3 6 | |
708 | #define TARGET_CPU_DEFAULT_pentium4 7 | |
709 | #define TARGET_CPU_DEFAULT_k6 8 | |
710 | #define TARGET_CPU_DEFAULT_k6_2 9 | |
711 | #define TARGET_CPU_DEFAULT_k6_3 10 | |
712 | #define TARGET_CPU_DEFAULT_athlon 11 | |
713 | #define TARGET_CPU_DEFAULT_athlon_sse 12 | |
4977bab6 | 714 | #define TARGET_CPU_DEFAULT_k8 13 |
5bbeea44 JH |
715 | #define TARGET_CPU_DEFAULT_pentium_m 14 |
716 | #define TARGET_CPU_DEFAULT_prescott 15 | |
eb3d7f9d | 717 | #define TARGET_CPU_DEFAULT_nocona 16 |
f4365627 JH |
718 | |
719 | #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ | |
720 | "pentiumpro", "pentium2", "pentium3", \ | |
721 | "pentium4", "k6", "k6-2", "k6-3",\ | |
5bbeea44 JH |
722 | "athlon", "athlon-4", "k8", \ |
723 | "pentium-m", "prescott", "nocona"} | |
0c2dc519 | 724 | |
628714d8 | 725 | #ifndef CC1_SPEC |
8015b78d | 726 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
727 | #endif |
728 | ||
729 | /* This macro defines names of additional specifications to put in the | |
730 | specs that can be used in various specifications like CC1_SPEC. Its | |
731 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
732 | |
733 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 734 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
735 | program. |
736 | ||
737 | Do not define this macro if it does not need to do anything. */ | |
738 | ||
739 | #ifndef SUBTARGET_EXTRA_SPECS | |
740 | #define SUBTARGET_EXTRA_SPECS | |
741 | #endif | |
742 | ||
743 | #define EXTRA_SPECS \ | |
628714d8 | 744 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
745 | SUBTARGET_EXTRA_SPECS |
746 | \f | |
c98f8742 JVA |
747 | /* target machine storage layout */ |
748 | ||
968a7562 | 749 | #define LONG_DOUBLE_TYPE_SIZE 80 |
2b589241 | 750 | |
d57a4b98 RH |
751 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
752 | FPU, assume that the fpcw is set to extended precision; when using | |
753 | only SSE, rounding is correct; when using both SSE and the FPU, | |
754 | the rounding precision is indeterminate, since either may be chosen | |
755 | apparently at random. */ | |
756 | #define TARGET_FLT_EVAL_METHOD \ | |
5ccd517a | 757 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) |
0038aea6 | 758 | |
65d9c0ab JH |
759 | #define SHORT_TYPE_SIZE 16 |
760 | #define INT_TYPE_SIZE 32 | |
761 | #define FLOAT_TYPE_SIZE 32 | |
762 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
65d9c0ab JH |
763 | #define DOUBLE_TYPE_SIZE 64 |
764 | #define LONG_LONG_TYPE_SIZE 64 | |
765 | ||
67adf6a9 | 766 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 767 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
768 | #else |
769 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
770 | #endif |
771 | ||
c98f8742 JVA |
772 | /* Define this if most significant byte of a word is the lowest numbered. */ |
773 | /* That is true on the 80386. */ | |
774 | ||
775 | #define BITS_BIG_ENDIAN 0 | |
776 | ||
777 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
778 | /* That is not true on the 80386. */ | |
779 | #define BYTES_BIG_ENDIAN 0 | |
780 | ||
781 | /* Define this if most significant word of a multiword number is the lowest | |
782 | numbered. */ | |
783 | /* Not true for 80386 */ | |
784 | #define WORDS_BIG_ENDIAN 0 | |
785 | ||
c98f8742 | 786 | /* Width of a word, in units (bytes). */ |
65d9c0ab | 787 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
2e64c636 JH |
788 | #ifdef IN_LIBGCC2 |
789 | #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
790 | #else | |
791 | #define MIN_UNITS_PER_WORD 4 | |
792 | #endif | |
c98f8742 | 793 | |
c98f8742 | 794 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 795 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 796 | |
e075ae69 | 797 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
65d9c0ab | 798 | #define STACK_BOUNDARY BITS_PER_WORD |
c98f8742 | 799 | |
d1f87653 | 800 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 801 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 802 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 803 | |
1d482056 | 804 | /* As of July 2001, many runtimes to not align the stack properly when |
d1f87653 | 805 | entering main. This causes expand_main_function to forcibly align |
1d482056 RH |
806 | the stack, which results in aligned frames for functions called from |
807 | main, though it does nothing for the alignment of main itself. */ | |
808 | #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ | |
14f73b5a | 809 | (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) |
1d482056 | 810 | |
f963b5d9 RS |
811 | /* Minimum allocation boundary for the code of a function. */ |
812 | #define FUNCTION_BOUNDARY 8 | |
813 | ||
814 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
815 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 816 | |
892a2d68 | 817 | /* Alignment of field after `int : 0' in a structure. */ |
c98f8742 | 818 | |
65d9c0ab | 819 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD |
c98f8742 JVA |
820 | |
821 | /* Minimum size in bits of the largest boundary to which any | |
822 | and all fundamental data types supported by the hardware | |
823 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 824 | rounder than this. |
fce5a9f2 | 825 | |
d1f87653 | 826 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
17f24ff0 JH |
827 | and Pentium Pro XFmode values at 128 bit boundaries. */ |
828 | ||
829 | #define BIGGEST_ALIGNMENT 128 | |
830 | ||
822eda12 | 831 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 832 | #define ALIGN_MODE_128(MODE) \ |
822eda12 | 833 | ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 834 | |
17f24ff0 | 835 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 836 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 837 | -malign-double is set. */ |
e932b21b | 838 | |
e83f3cff RH |
839 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
840 | supports no vector modes, cut out the complexity and fall back | |
841 | on BIGGEST_FIELD_ALIGNMENT. */ | |
842 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
843 | #ifdef __x86_64__ |
844 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
845 | #else | |
e83f3cff | 846 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 847 | #endif |
e83f3cff | 848 | #else |
e932b21b JH |
849 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
850 | x86_field_alignment (FIELD, COMPUTED) | |
e83f3cff | 851 | #endif |
c98f8742 | 852 | |
e5e8a8bf | 853 | /* If defined, a C expression to compute the alignment given to a |
a7180f70 | 854 | constant that is being placed in memory. EXP is the constant |
e5e8a8bf JW |
855 | and ALIGN is the alignment that the object would ordinarily have. |
856 | The value of this macro is used instead of that alignment to align | |
857 | the object. | |
858 | ||
859 | If this macro is not defined, then ALIGN is used. | |
860 | ||
861 | The typical use of this macro is to increase alignment for string | |
862 | constants to be word aligned so that `strcpy' calls that copy | |
863 | constants can be done inline. */ | |
864 | ||
d9a5f180 | 865 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
d4ba09c0 | 866 | |
8a022443 JW |
867 | /* If defined, a C expression to compute the alignment for a static |
868 | variable. TYPE is the data type, and ALIGN is the alignment that | |
869 | the object would ordinarily have. The value of this macro is used | |
870 | instead of that alignment to align the object. | |
871 | ||
872 | If this macro is not defined, then ALIGN is used. | |
873 | ||
874 | One use of this macro is to increase alignment of medium-size | |
875 | data to make it all fit in fewer cache lines. Another is to | |
876 | cause character arrays to be word-aligned so that `strcpy' calls | |
877 | that copy constants to character arrays can be done inline. */ | |
878 | ||
d9a5f180 | 879 | #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) |
d16790f2 JW |
880 | |
881 | /* If defined, a C expression to compute the alignment for a local | |
882 | variable. TYPE is the data type, and ALIGN is the alignment that | |
883 | the object would ordinarily have. The value of this macro is used | |
884 | instead of that alignment to align the object. | |
885 | ||
886 | If this macro is not defined, then ALIGN is used. | |
887 | ||
888 | One use of this macro is to increase alignment of medium-size | |
889 | data to make it all fit in fewer cache lines. */ | |
890 | ||
d9a5f180 | 891 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) |
8a022443 | 892 | |
53c17031 JH |
893 | /* If defined, a C expression that gives the alignment boundary, in |
894 | bits, of an argument with the specified mode and type. If it is | |
895 | not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
896 | ||
d9a5f180 GS |
897 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
898 | ix86_function_arg_boundary ((MODE), (TYPE)) | |
53c17031 | 899 | |
9cd10576 | 900 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 901 | when given unaligned data. */ |
b4ac57ab | 902 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
903 | |
904 | /* If bit field type is int, don't let it cross an int, | |
905 | and give entire struct the alignment of an int. */ | |
43a88a8c | 906 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 907 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
908 | \f |
909 | /* Standard register usage. */ | |
910 | ||
911 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 912 | for details. */ |
c98f8742 JVA |
913 | |
914 | #define STACK_REGS | |
d9a5f180 | 915 | #define IS_STACK_MODE(MODE) \ |
f8a1ebc6 | 916 | ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \ |
c98f8742 JVA |
917 | |
918 | /* Number of actual hardware registers. | |
919 | The hardware registers are assigned numbers for the compiler | |
920 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
921 | All registers that the compiler knows about must be given numbers, | |
922 | even those that are not normally considered general registers. | |
923 | ||
924 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
925 | We number the floating point registers 8-15. | |
926 | Note that registers 0-7 can be accessed as a short or int, | |
927 | while only 0-3 may be used with byte `mov' instructions. | |
928 | ||
929 | Reg 16 does not correspond to any hardware register, but instead | |
930 | appears in the RTL as an argument pointer prior to reload, and is | |
931 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 932 | pointer. */ |
c98f8742 | 933 | |
3f3f2124 | 934 | #define FIRST_PSEUDO_REGISTER 53 |
c98f8742 | 935 | |
3073d01c ML |
936 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
937 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
938 | ||
939 | #define DWARF_FRAME_REGISTERS 17 | |
940 | ||
c98f8742 JVA |
941 | /* 1 for registers that have pervasive standard uses |
942 | and are not available for the register allocator. | |
3f3f2124 | 943 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 944 | |
3a4416fb RS |
945 | The value is zero if the register is not fixed on either 32 or |
946 | 64 bit targets, one if the register if fixed on both 32 and 64 | |
947 | bit targets, two if it is only fixed on 32bit targets and three | |
948 | if its only fixed on 64bit targets. | |
949 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
3f3f2124 | 950 | */ |
a7180f70 BS |
951 | #define FIXED_REGISTERS \ |
952 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 953 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
a7180f70 | 954 | /*arg,flags,fpsr,dir,frame*/ \ |
3a4416fb | 955 | 1, 1, 1, 1, 1, \ |
a7180f70 BS |
956 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
957 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
958 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ | |
3f3f2124 JH |
959 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
960 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
3a4416fb | 961 | 2, 2, 2, 2, 2, 2, 2, 2, \ |
3f3f2124 | 962 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3a4416fb | 963 | 2, 2, 2, 2, 2, 2, 2, 2} |
fce5a9f2 | 964 | |
c98f8742 JVA |
965 | |
966 | /* 1 for registers not available across function calls. | |
967 | These must include the FIXED_REGISTERS and also any | |
968 | registers that can be used without being saved. | |
969 | The latter must include the registers where values are returned | |
970 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
971 | Aside from that, you can include as many other registers as you like. |
972 | ||
3a4416fb RS |
973 | The value is zero if the register is not fixed on either 32 or |
974 | 64 bit targets, one if the register if fixed on both 32 and 64 | |
975 | bit targets, two if it is only fixed on 32bit targets and three | |
976 | if its only fixed on 64bit targets. | |
977 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
3f3f2124 | 978 | */ |
a7180f70 BS |
979 | #define CALL_USED_REGISTERS \ |
980 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 981 | { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
a7180f70 | 982 | /*arg,flags,fpsr,dir,frame*/ \ |
3a4416fb | 983 | 1, 1, 1, 1, 1, \ |
a7180f70 | 984 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
3a4416fb | 985 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
a7180f70 | 986 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ |
3a4416fb | 987 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 988 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 989 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 990 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3a4416fb | 991 | 1, 1, 1, 1, 1, 1, 1, 1} \ |
c98f8742 | 992 | |
3b3c6a3f MM |
993 | /* Order in which to allocate registers. Each register must be |
994 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
995 | late and fixed registers last. Note that, in general, we prefer | |
996 | registers listed in CALL_USED_REGISTERS, keeping the others | |
997 | available for storage of persistent values. | |
998 | ||
162f023b JH |
999 | The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, |
1000 | so this is just empty initializer for array. */ | |
3b3c6a3f | 1001 | |
162f023b JH |
1002 | #define REG_ALLOC_ORDER \ |
1003 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
1004 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
1005 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
1006 | 48, 49, 50, 51, 52 } | |
3b3c6a3f | 1007 | |
162f023b JH |
1008 | /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order |
1009 | to be rearranged based on a particular function. When using sse math, | |
d1f87653 | 1010 | we want to allocate SSE before x87 registers and vice vera. */ |
3b3c6a3f | 1011 | |
162f023b | 1012 | #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () |
3b3c6a3f | 1013 | |
f5316dfe | 1014 | |
c98f8742 | 1015 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
a7180f70 | 1016 | #define CONDITIONAL_REGISTER_USAGE \ |
d9a5f180 | 1017 | do { \ |
3f3f2124 JH |
1018 | int i; \ |
1019 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
1020 | { \ | |
3a4416fb RS |
1021 | if (fixed_regs[i] > 1) \ |
1022 | fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ | |
1023 | if (call_used_regs[i] > 1) \ | |
1024 | call_used_regs[i] = (call_used_regs[i] \ | |
1025 | == (TARGET_64BIT ? 3 : 2)); \ | |
3f3f2124 | 1026 | } \ |
5b43fed1 | 1027 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
a7180f70 BS |
1028 | { \ |
1029 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
1030 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
1031 | } \ | |
1032 | if (! TARGET_MMX) \ | |
1033 | { \ | |
1034 | int i; \ | |
1035 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
1036 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ | |
1037 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
1038 | } \ | |
1039 | if (! TARGET_SSE) \ | |
1040 | { \ | |
1041 | int i; \ | |
1042 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
1043 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ | |
1044 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
1045 | } \ | |
1046 | if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ | |
1047 | { \ | |
1048 | int i; \ | |
1049 | HARD_REG_SET x; \ | |
1050 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ | |
1051 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
1052 | if (TEST_HARD_REG_BIT (x, i)) \ | |
1053 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
1054 | } \ | |
d9a5f180 | 1055 | } while (0) |
c98f8742 JVA |
1056 | |
1057 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
1058 | to hold something of mode MODE. | |
1059 | This is ordinarily the length in words of a value of mode MODE | |
1060 | but can be less for certain modes in special long registers. | |
1061 | ||
fce5a9f2 | 1062 | Actually there are no two word move instructions for consecutive |
c98f8742 JVA |
1063 | registers. And only registers 0-3 may have mov byte instructions |
1064 | applied to them. | |
1065 | */ | |
1066 | ||
1067 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
92d0fb09 JH |
1068 | (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
1069 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
f8a1ebc6 | 1070 | : ((MODE) == XFmode \ |
92d0fb09 | 1071 | ? (TARGET_64BIT ? 2 : 3) \ |
f8a1ebc6 | 1072 | : (MODE) == XCmode \ |
92d0fb09 | 1073 | ? (TARGET_64BIT ? 4 : 6) \ |
2b589241 | 1074 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
c98f8742 | 1075 | |
fbe5eb6d BS |
1076 | #define VALID_SSE2_REG_MODE(MODE) \ |
1077 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
dcbca208 RH |
1078 | || (MODE) == V2DImode || (MODE) == DFmode \ |
1079 | || VALID_MMX_REG_MODE (MODE)) | |
fbe5eb6d | 1080 | |
d9a5f180 GS |
1081 | #define VALID_SSE_REG_MODE(MODE) \ |
1082 | ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
dcbca208 | 1083 | || (MODE) == SFmode || (MODE) == TFmode) |
a7180f70 | 1084 | |
47f339cf BS |
1085 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
1086 | ((MODE) == V2SFmode || (MODE) == SFmode) | |
1087 | ||
d9a5f180 GS |
1088 | #define VALID_MMX_REG_MODE(MODE) \ |
1089 | ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ | |
a7180f70 BS |
1090 | || (MODE) == V2SImode || (MODE) == SImode) |
1091 | ||
0bf43309 DN |
1092 | #define UNITS_PER_SIMD_WORD \ |
1093 | (TARGET_SSE ? 16 : TARGET_MMX || TARGET_3DNOW ? 8 : 0) | |
1094 | ||
d9a5f180 | 1095 | #define VALID_FP_MODE_P(MODE) \ |
f8a1ebc6 JH |
1096 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
1097 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
a946dd00 | 1098 | |
d9a5f180 GS |
1099 | #define VALID_INT_MODE_P(MODE) \ |
1100 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ | |
1101 | || (MODE) == DImode \ | |
1102 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1103 | || (MODE) == CDImode \ | |
f8a1ebc6 JH |
1104 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ |
1105 | || (MODE) == TFmode || (MODE) == TCmode))) | |
a946dd00 | 1106 | |
822eda12 JH |
1107 | /* Return true for modes passed in SSE registers. */ |
1108 | #define SSE_REG_MODE_P(MODE) \ | |
f8a1ebc6 | 1109 | ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ |
822eda12 JH |
1110 | || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ |
1111 | || (MODE) == V4SFmode || (MODE) == V4SImode) | |
1112 | ||
1113 | /* Return true for modes passed in MMX registers. */ | |
1114 | #define MMX_REG_MODE_P(MODE) \ | |
1115 | ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \ | |
1116 | || (MODE) == V2SFmode) | |
1117 | ||
e075ae69 | 1118 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 1119 | |
a946dd00 | 1120 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
d9a5f180 | 1121 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
c98f8742 JVA |
1122 | |
1123 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1124 | when one has mode MODE1 and one has mode MODE2. | |
1125 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1126 | for any hard reg, then this must be 0 for correct output. */ | |
1127 | ||
95912252 RH |
1128 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
1129 | ((MODE1) == (MODE2) \ | |
d2836273 JH |
1130 | || (((MODE1) == HImode || (MODE1) == SImode \ |
1131 | || ((MODE1) == QImode \ | |
1132 | && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ | |
1133 | || ((MODE1) == DImode && TARGET_64BIT)) \ | |
1134 | && ((MODE2) == HImode || (MODE2) == SImode \ | |
a64d0bc6 | 1135 | || ((MODE2) == QImode \ |
d2836273 JH |
1136 | && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ |
1137 | || ((MODE2) == DImode && TARGET_64BIT)))) | |
1138 | ||
ff25ef99 ZD |
1139 | /* It is possible to write patterns to move flags; but until someone |
1140 | does it, */ | |
1141 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 1142 | |
e075ae69 | 1143 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1144 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1145 | |
787dc842 JH |
1146 | Kill any attempts to combine saving of modes. */ |
1147 | ||
d9a5f180 GS |
1148 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1149 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1150 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
fee226d2 | 1151 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\ |
d9a5f180 GS |
1152 | : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ |
1153 | : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ | |
d2836273 | 1154 | : (MODE)) |
c98f8742 JVA |
1155 | /* Specify the registers used for certain standard purposes. |
1156 | The values of these macros are register numbers. */ | |
1157 | ||
1158 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1159 | register. The ordinary mov instructions won't work */ | |
1160 | /* #define PC_REGNUM */ | |
1161 | ||
1162 | /* Register to use for pushing function arguments. */ | |
1163 | #define STACK_POINTER_REGNUM 7 | |
1164 | ||
1165 | /* Base register for access to local variables of the function. */ | |
564d80f4 JH |
1166 | #define HARD_FRAME_POINTER_REGNUM 6 |
1167 | ||
1168 | /* Base register for access to local variables of the function. */ | |
1169 | #define FRAME_POINTER_REGNUM 20 | |
c98f8742 JVA |
1170 | |
1171 | /* First floating point reg */ | |
1172 | #define FIRST_FLOAT_REG 8 | |
1173 | ||
1174 | /* First & last stack-like regs */ | |
1175 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
1176 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
1177 | ||
a7180f70 BS |
1178 | #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) |
1179 | #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
fce5a9f2 | 1180 | |
a7180f70 BS |
1181 | #define FIRST_MMX_REG (LAST_SSE_REG + 1) |
1182 | #define LAST_MMX_REG (FIRST_MMX_REG + 7) | |
1183 | ||
3f3f2124 JH |
1184 | #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) |
1185 | #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) | |
1186 | ||
1187 | #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) | |
1188 | #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) | |
1189 | ||
c98f8742 JVA |
1190 | /* Value should be nonzero if functions must have frame pointers. |
1191 | Zero means the frame pointer need not be set up (and parms | |
1192 | may be accessed via the stack pointer) in functions that seem suitable. | |
1193 | This is computed in `reload', in reload1.c. */ | |
6fca22eb RH |
1194 | #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () |
1195 | ||
1196 | /* Override this in other tm.h files to cope with various OS losage | |
1197 | requiring a frame pointer. */ | |
1198 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1199 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1200 | #endif | |
1201 | ||
1202 | /* Make sure we can access arbitrary call frames. */ | |
1203 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 JVA |
1204 | |
1205 | /* Base register for access to arguments of the function. */ | |
1206 | #define ARG_POINTER_REGNUM 16 | |
1207 | ||
d2836273 JH |
1208 | /* Register in which static-chain is passed to a function. |
1209 | We do use ECX as static chain register for 32 bit ABI. On the | |
1210 | 64bit ABI, ECX is an argument register, so we use R10 instead. */ | |
1211 | #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) | |
c98f8742 JVA |
1212 | |
1213 | /* Register to hold the addressing base for position independent | |
5b43fed1 RH |
1214 | code access to data items. We don't use PIC pointer for 64bit |
1215 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1216 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1217 | |
1218 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1219 | the pic register when possible. The change is visible after the | |
1220 | prologue has been emitted. */ | |
1221 | ||
1222 | #define REAL_PIC_OFFSET_TABLE_REGNUM 3 | |
1223 | ||
1224 | #define PIC_OFFSET_TABLE_REGNUM \ | |
1225 | (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \ | |
1226 | : reload_completed ? REGNO (pic_offset_table_rtx) \ | |
1227 | : REAL_PIC_OFFSET_TABLE_REGNUM) | |
c98f8742 | 1228 | |
5fc0e5df KW |
1229 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1230 | ||
713225d4 MM |
1231 | /* A C expression which can inhibit the returning of certain function |
1232 | values in registers, based on the type of value. A nonzero value | |
1233 | says to return the function value in memory, just as large | |
1234 | structures are always returned. Here TYPE will be a C expression | |
1235 | of type `tree', representing the data type of the value. | |
1236 | ||
1237 | Note that values of mode `BLKmode' must be explicitly handled by | |
1238 | this macro. Also, the option `-fpcc-struct-return' takes effect | |
1239 | regardless of this macro. On most systems, it is possible to | |
1240 | leave the macro undefined; this causes a default definition to be | |
1241 | used, whose value is the constant 1 for `BLKmode' values, and 0 | |
1242 | otherwise. | |
1243 | ||
1244 | Do not use this macro to indicate that structures and unions | |
1245 | should always be returned in memory. You should instead use | |
1246 | `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ | |
1247 | ||
d9a5f180 | 1248 | #define RETURN_IN_MEMORY(TYPE) \ |
53c17031 | 1249 | ix86_return_in_memory (TYPE) |
713225d4 | 1250 | |
c51e6d85 | 1251 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1252 | #define MS_AGGREGATE_RETURN 0 |
1253 | ||
61fec9ff JB |
1254 | /* This is overridden by <netware.h>. */ |
1255 | #define KEEP_AGGREGATE_RETURN_POINTER 0 | |
c98f8742 JVA |
1256 | \f |
1257 | /* Define the classes of registers for register constraints in the | |
1258 | machine description. Also define ranges of constants. | |
1259 | ||
1260 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1261 | If there is more than one class, another class must be named NO_REGS | |
1262 | and contain no registers. | |
1263 | ||
1264 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1265 | another name such as ALL_REGS). This is the class of registers | |
1266 | that is allowed by "g" or "r" in a register constraint. | |
1267 | Also, registers outside this class are allocated only when | |
1268 | instructions express preferences for them. | |
1269 | ||
1270 | The classes must be numbered in nondecreasing order; that is, | |
1271 | a larger-numbered class must never be contained completely | |
1272 | in a smaller-numbered class. | |
1273 | ||
1274 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1275 | class that represents their union. |
1276 | ||
1277 | It might seem that class BREG is unnecessary, since no useful 386 | |
1278 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1279 | and the "b" register constraint is useful in asms for syscalls. |
1280 | ||
1281 | The flags and fpsr registers are in no class. */ | |
c98f8742 JVA |
1282 | |
1283 | enum reg_class | |
1284 | { | |
1285 | NO_REGS, | |
e075ae69 | 1286 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1287 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 | 1288 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1289 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 | 1290 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 JH |
1291 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
1292 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ | |
c98f8742 JVA |
1293 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1294 | FLOAT_REGS, | |
a7180f70 BS |
1295 | SSE_REGS, |
1296 | MMX_REGS, | |
446988df JH |
1297 | FP_TOP_SSE_REGS, |
1298 | FP_SECOND_SSE_REGS, | |
1299 | FLOAT_SSE_REGS, | |
1300 | FLOAT_INT_REGS, | |
1301 | INT_SSE_REGS, | |
1302 | FLOAT_INT_SSE_REGS, | |
c98f8742 JVA |
1303 | ALL_REGS, LIM_REG_CLASSES |
1304 | }; | |
1305 | ||
d9a5f180 GS |
1306 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1307 | ||
1308 | #define INTEGER_CLASS_P(CLASS) \ | |
1309 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1310 | #define FLOAT_CLASS_P(CLASS) \ | |
1311 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1312 | #define SSE_CLASS_P(CLASS) \ | |
1313 | reg_class_subset_p ((CLASS), SSE_REGS) | |
1314 | #define MMX_CLASS_P(CLASS) \ | |
1315 | reg_class_subset_p ((CLASS), MMX_REGS) | |
1316 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ | |
1317 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1318 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1319 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1320 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
1321 | reg_classes_intersect_p (SSE_REGS, (CLASS)) | |
1322 | #define MAYBE_MMX_CLASS_P(CLASS) \ | |
1323 | reg_classes_intersect_p (MMX_REGS, (CLASS)) | |
1324 | ||
1325 | #define Q_CLASS_P(CLASS) \ | |
1326 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1327 | |
43f3a59d | 1328 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1329 | |
1330 | #define REG_CLASS_NAMES \ | |
1331 | { "NO_REGS", \ | |
ab408a86 | 1332 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1333 | "SIREG", "DIREG", \ |
e075ae69 RH |
1334 | "AD_REGS", \ |
1335 | "Q_REGS", "NON_Q_REGS", \ | |
c98f8742 | 1336 | "INDEX_REGS", \ |
3f3f2124 | 1337 | "LEGACY_REGS", \ |
c98f8742 JVA |
1338 | "GENERAL_REGS", \ |
1339 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1340 | "FLOAT_REGS", \ | |
a7180f70 BS |
1341 | "SSE_REGS", \ |
1342 | "MMX_REGS", \ | |
446988df JH |
1343 | "FP_TOP_SSE_REGS", \ |
1344 | "FP_SECOND_SSE_REGS", \ | |
1345 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1346 | "FLOAT_INT_REGS", \ |
446988df JH |
1347 | "INT_SSE_REGS", \ |
1348 | "FLOAT_INT_SSE_REGS", \ | |
c98f8742 JVA |
1349 | "ALL_REGS" } |
1350 | ||
1351 | /* Define which registers fit in which classes. | |
1352 | This is an initializer for a vector of HARD_REG_SET | |
1353 | of length N_REG_CLASSES. */ | |
1354 | ||
a7180f70 | 1355 | #define REG_CLASS_CONTENTS \ |
3f3f2124 JH |
1356 | { { 0x00, 0x0 }, \ |
1357 | { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ | |
1358 | { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ | |
1359 | { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ | |
1360 | { 0x03, 0x0 }, /* AD_REGS */ \ | |
1361 | { 0x0f, 0x0 }, /* Q_REGS */ \ | |
1362 | { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ | |
1363 | { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ | |
1364 | { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ | |
1365 | { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ | |
1366 | { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ | |
1367 | { 0xff00, 0x0 }, /* FLOAT_REGS */ \ | |
1368 | { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ | |
1369 | { 0xe0000000, 0x1f }, /* MMX_REGS */ \ | |
1370 | { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ | |
1371 | { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ | |
1372 | { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ | |
1373 | { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ | |
1374 | { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ | |
1375 | { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ | |
1376 | { 0xffffffff,0x1fffff } \ | |
e075ae69 | 1377 | } |
c98f8742 JVA |
1378 | |
1379 | /* The same information, inverted: | |
1380 | Return the class number of the smallest class containing | |
1381 | reg number REGNO. This could be a conditional expression | |
1382 | or could index an array. */ | |
1383 | ||
c98f8742 JVA |
1384 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1385 | ||
1386 | /* When defined, the compiler allows registers explicitly used in the | |
1387 | rtl to be used as spill registers but prevents the compiler from | |
892a2d68 | 1388 | extending the lifetime of these registers. */ |
c98f8742 | 1389 | |
2922fe9e | 1390 | #define SMALL_REGISTER_CLASSES 1 |
c98f8742 JVA |
1391 | |
1392 | #define QI_REG_P(X) \ | |
1393 | (REG_P (X) && REGNO (X) < 4) | |
3f3f2124 | 1394 | |
d9a5f180 GS |
1395 | #define GENERAL_REGNO_P(N) \ |
1396 | ((N) < 8 || REX_INT_REGNO_P (N)) | |
3f3f2124 JH |
1397 | |
1398 | #define GENERAL_REG_P(X) \ | |
6189a572 | 1399 | (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
3f3f2124 JH |
1400 | |
1401 | #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) | |
1402 | ||
c98f8742 JVA |
1403 | #define NON_QI_REG_P(X) \ |
1404 | (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) | |
1405 | ||
d9a5f180 | 1406 | #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) |
3f3f2124 JH |
1407 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) |
1408 | ||
c98f8742 | 1409 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) |
d9a5f180 | 1410 | #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) |
446988df | 1411 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
d9a5f180 | 1412 | #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) |
a7180f70 | 1413 | |
d9a5f180 GS |
1414 | #define SSE_REGNO_P(N) \ |
1415 | (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ | |
1416 | || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) | |
3f3f2124 | 1417 | |
4977bab6 ZW |
1418 | #define REX_SSE_REGNO_P(N) \ |
1419 | ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG) | |
1420 | ||
d9a5f180 GS |
1421 | #define SSE_REGNO(N) \ |
1422 | ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) | |
1423 | #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) | |
446988df | 1424 | |
d9a5f180 | 1425 | #define SSE_FLOAT_MODE_P(MODE) \ |
91da27c5 | 1426 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) |
a7180f70 | 1427 | |
d9a5f180 GS |
1428 | #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) |
1429 | #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) | |
fce5a9f2 | 1430 | |
d9a5f180 GS |
1431 | #define STACK_REG_P(XOP) \ |
1432 | (REG_P (XOP) && \ | |
1433 | REGNO (XOP) >= FIRST_STACK_REG && \ | |
1434 | REGNO (XOP) <= LAST_STACK_REG) | |
c98f8742 | 1435 | |
d9a5f180 | 1436 | #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) |
c98f8742 | 1437 | |
d9a5f180 | 1438 | #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) |
c98f8742 | 1439 | |
e075ae69 RH |
1440 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1441 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1442 | ||
c98f8742 JVA |
1443 | /* The class value for index registers, and the one for base regs. */ |
1444 | ||
1445 | #define INDEX_REG_CLASS INDEX_REGS | |
1446 | #define BASE_REG_CLASS GENERAL_REGS | |
1447 | ||
9a9286af RH |
1448 | /* Unused letters: |
1449 | B TU W | |
1450 | h jk vw z | |
1451 | */ | |
1452 | ||
c98f8742 JVA |
1453 | /* Get reg_class from a letter such as appears in the machine description. */ |
1454 | ||
1455 | #define REG_CLASS_FROM_LETTER(C) \ | |
8c2bf92a | 1456 | ((C) == 'r' ? GENERAL_REGS : \ |
3f3f2124 JH |
1457 | (C) == 'R' ? LEGACY_REGS : \ |
1458 | (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ | |
1459 | (C) == 'Q' ? Q_REGS : \ | |
8c2bf92a JVA |
1460 | (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ |
1461 | ? FLOAT_REGS \ | |
1462 | : NO_REGS) : \ | |
1463 | (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
1464 | ? FP_TOP_REG \ | |
1465 | : NO_REGS) : \ | |
1466 | (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
1467 | ? FP_SECOND_REG \ | |
1468 | : NO_REGS) : \ | |
1469 | (C) == 'a' ? AREG : \ | |
1470 | (C) == 'b' ? BREG : \ | |
1471 | (C) == 'c' ? CREG : \ | |
1472 | (C) == 'd' ? DREG : \ | |
446988df JH |
1473 | (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ |
1474 | (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ | |
1475 | (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ | |
4b71cd6e | 1476 | (C) == 'A' ? AD_REGS : \ |
8c2bf92a | 1477 | (C) == 'D' ? DIREG : \ |
9a9286af RH |
1478 | (C) == 'S' ? SIREG : \ |
1479 | (C) == 'l' ? INDEX_REGS : \ | |
1480 | NO_REGS) | |
c98f8742 JVA |
1481 | |
1482 | /* The letters I, J, K, L and M in a register constraint string | |
1483 | can be used to stand for particular ranges of immediate operands. | |
1484 | This macro defines what the ranges are. | |
1485 | C is the letter, and VALUE is a constant value. | |
1486 | Return 1 if VALUE is in the range specified by C. | |
1487 | ||
1488 | I is for non-DImode shifts. | |
1489 | J is for DImode shifts. | |
e075ae69 RH |
1490 | K is for signed imm8 operands. |
1491 | L is for andsi as zero-extending move. | |
c98f8742 | 1492 | M is for shifts that can be executed by the "lea" opcode. |
d1f87653 | 1493 | N is for immediate operands for out/in instructions (0-255) |
c98f8742 JVA |
1494 | */ |
1495 | ||
e075ae69 RH |
1496 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
1497 | ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ | |
1498 | : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ | |
1499 | : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ | |
1500 | : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ | |
1501 | : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ | |
1aa9fd24 | 1502 | : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ |
e075ae69 | 1503 | : 0) |
c98f8742 JVA |
1504 | |
1505 | /* Similar, but for floating constants, and defining letters G and H. | |
b4ac57ab RS |
1506 | Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if |
1507 | TARGET_387 isn't set, because the stack register converter may need to | |
c47f5ea5 | 1508 | load 0.0 into the function value register. */ |
c98f8742 JVA |
1509 | |
1510 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
2b04e52b | 1511 | ((C) == 'G' ? standard_80387_constant_p (VALUE) \ |
f8ca7923 | 1512 | : 0) |
c98f8742 | 1513 | |
6189a572 JH |
1514 | /* A C expression that defines the optional machine-dependent |
1515 | constraint letters that can be used to segregate specific types of | |
1516 | operands, usually memory references, for the target machine. Any | |
1517 | letter that is not elsewhere defined and not matched by | |
1518 | `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not | |
1519 | be defined. | |
1520 | ||
1521 | If it is required for a particular target machine, it should | |
1522 | return 1 if VALUE corresponds to the operand type represented by | |
1523 | the constraint letter C. If C is not defined as an extra | |
1524 | constraint, the value returned should be 0 regardless of VALUE. */ | |
1525 | ||
8fe75e43 RH |
1526 | #define EXTRA_CONSTRAINT(VALUE, D) \ |
1527 | ((D) == 'e' ? x86_64_immediate_operand (VALUE, VOIDmode) \ | |
1528 | : (D) == 'Z' ? x86_64_zext_immediate_operand (VALUE, VOIDmode) \ | |
1529 | : (D) == 'C' ? standard_sse_constant_p (VALUE) \ | |
6189a572 JH |
1530 | : 0) |
1531 | ||
c98f8742 | 1532 | /* Place additional restrictions on the register class to use when it |
4cbb525c | 1533 | is necessary to be able to hold a value of mode MODE in a reload |
892a2d68 | 1534 | register for which class CLASS would ordinarily be used. */ |
c98f8742 | 1535 | |
d2836273 JH |
1536 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
1537 | ((MODE) == QImode && !TARGET_64BIT \ | |
3b8d200e JJ |
1538 | && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ |
1539 | || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ | |
c98f8742 JVA |
1540 | ? Q_REGS : (CLASS)) |
1541 | ||
1542 | /* Given an rtx X being reloaded into a reg required to be | |
1543 | in class CLASS, return the class of reg to actually use. | |
1544 | In general this is just CLASS; but on some machines | |
1545 | in some cases it is preferable to use a more restrictive class. | |
1546 | On the 80386 series, we prevent floating constants from being | |
1547 | reloaded into floating registers (since no move-insn can do that) | |
1548 | and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
1549 | ||
d398b3b1 | 1550 | /* Put float CONST_DOUBLE in the constant pool instead of fp regs. |
c98f8742 | 1551 | QImode must go into class Q_REGS. |
d398b3b1 | 1552 | Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and |
892a2d68 | 1553 | movdf to do mem-to-mem moves through integer regs. */ |
c98f8742 | 1554 | |
d9a5f180 GS |
1555 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
1556 | ix86_preferred_reload_class ((X), (CLASS)) | |
85ff473e JVA |
1557 | |
1558 | /* If we are copying between general and FP registers, we need a memory | |
f84aa48a | 1559 | location. The same is true for SSE and MMX registers. */ |
d9a5f180 GS |
1560 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1561 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
e075ae69 RH |
1562 | |
1563 | /* QImode spills from non-QI registers need a scratch. This does not | |
fce5a9f2 | 1564 | happen often -- the only example so far requires an uninitialized |
e075ae69 RH |
1565 | pseudo. */ |
1566 | ||
d9a5f180 | 1567 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ |
3b8d200e JJ |
1568 | (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ |
1569 | || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ | |
d2836273 | 1570 | ? Q_REGS : NO_REGS) |
c98f8742 JVA |
1571 | |
1572 | /* Return the maximum number of consecutive registers | |
1573 | needed to represent mode MODE in a register of class CLASS. */ | |
1574 | /* On the 80386, this is the size of MODE in words, | |
f8a1ebc6 | 1575 | except in the FP regs, where a single reg is always enough. */ |
a7180f70 | 1576 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
92d0fb09 JH |
1577 | (!MAYBE_INTEGER_CLASS_P (CLASS) \ |
1578 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
f8a1ebc6 JH |
1579 | : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ |
1580 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
f5316dfe MM |
1581 | |
1582 | /* A C expression whose value is nonzero if pseudos that have been | |
1583 | assigned to registers of class CLASS would likely be spilled | |
1584 | because registers of CLASS are needed for spill registers. | |
1585 | ||
1586 | The default value of this macro returns 1 if CLASS has exactly one | |
1587 | register and zero otherwise. On most machines, this default | |
1588 | should be used. Only define this macro to some other expression | |
1589 | if pseudo allocated by `local-alloc.c' end up in memory because | |
ddd5a7c1 | 1590 | their hard registers were needed for spill registers. If this |
f5316dfe MM |
1591 | macro returns nonzero for those classes, those pseudos will only |
1592 | be allocated by `global.c', which knows how to reallocate the | |
1593 | pseudo to another register. If there would not be another | |
1594 | register available for reallocation, you should not change the | |
1595 | definition of this macro since the only effect of such a | |
1596 | definition would be to slow down register allocation. */ | |
1597 | ||
1598 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1599 | (((CLASS) == AREG) \ | |
1600 | || ((CLASS) == DREG) \ | |
1601 | || ((CLASS) == CREG) \ | |
1602 | || ((CLASS) == BREG) \ | |
1603 | || ((CLASS) == AD_REGS) \ | |
1604 | || ((CLASS) == SIREG) \ | |
b0af5c03 JH |
1605 | || ((CLASS) == DIREG) \ |
1606 | || ((CLASS) == FP_TOP_REG) \ | |
1607 | || ((CLASS) == FP_SECOND_REG)) | |
f5316dfe | 1608 | |
b0c42aed | 1609 | /* Return a class of registers that cannot change FROM mode to TO mode. |
f676971a | 1610 | |
b0c42aed JH |
1611 | x87 registers can't do subreg as all values are reformated to extended |
1612 | precision. XMM registers does not support with nonzero offsets equal | |
1613 | to 4, 8 and 12 otherwise valid for integer registers. Since we can't | |
1614 | determine these, prohibit all nonparadoxical subregs changing size. */ | |
1615 | ||
1616 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1617 | (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \ | |
1618 | ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \ | |
1619 | || MAYBE_MMX_CLASS_P (CLASS) \ | |
1620 | : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
1621 | ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0) | |
c98f8742 JVA |
1622 | \f |
1623 | /* Stack layout; function entry, exit and calling. */ | |
1624 | ||
1625 | /* Define this if pushing a word on the stack | |
1626 | makes the stack pointer a smaller address. */ | |
1627 | #define STACK_GROWS_DOWNWARD | |
1628 | ||
1629 | /* Define this if the nominal address of the stack frame | |
1630 | is at the high-address end of the local variables; | |
1631 | that is, each additional local variable allocated | |
1632 | goes at a more negative offset in the frame. */ | |
1633 | #define FRAME_GROWS_DOWNWARD | |
1634 | ||
1635 | /* Offset within stack frame to start allocating local variables at. | |
1636 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1637 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1638 | of the first local allocated. */ | |
1639 | #define STARTING_FRAME_OFFSET 0 | |
1640 | ||
1641 | /* If we generate an insn to push BYTES bytes, | |
1642 | this says how many the stack pointer really advances by. | |
1643 | On 386 pushw decrements by exactly 2 no matter what the position was. | |
1644 | On the 386 there is no pushb; we use pushw instead, and this | |
d2836273 | 1645 | has the effect of rounding up to 2. |
fce5a9f2 | 1646 | |
d2836273 JH |
1647 | For 64bit ABI we round up to 8 bytes. |
1648 | */ | |
c98f8742 | 1649 | |
d2836273 JH |
1650 | #define PUSH_ROUNDING(BYTES) \ |
1651 | (TARGET_64BIT \ | |
1652 | ? (((BYTES) + 7) & (-8)) \ | |
1653 | : (((BYTES) + 1) & (-2))) | |
c98f8742 | 1654 | |
f73ad30e JH |
1655 | /* If defined, the maximum amount of space required for outgoing arguments will |
1656 | be computed and placed into the variable | |
1657 | `current_function_outgoing_args_size'. No space will be pushed onto the | |
1658 | stack for each call; instead, the function prologue should increase the stack | |
1659 | frame size by this amount. */ | |
1660 | ||
1661 | #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS | |
1662 | ||
1663 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1664 | instructions to pass outgoing arguments. */ | |
1665 | ||
1666 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1667 | ||
2da4124d L |
1668 | /* We want the stack and args grow in opposite directions, even if |
1669 | PUSH_ARGS is 0. */ | |
1670 | #define PUSH_ARGS_REVERSED 1 | |
1671 | ||
c98f8742 JVA |
1672 | /* Offset of first parameter from the argument pointer register value. */ |
1673 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1674 | ||
a7180f70 BS |
1675 | /* Define this macro if functions should assume that stack space has been |
1676 | allocated for arguments even when their values are passed in registers. | |
1677 | ||
1678 | The value of this macro is the size, in bytes, of the area reserved for | |
1679 | arguments passed in registers for the function represented by FNDECL. | |
1680 | ||
1681 | This space can be allocated by the caller, or be a part of the | |
1682 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1683 | which. */ | |
1684 | #define REG_PARM_STACK_SPACE(FNDECL) 0 | |
1685 | ||
c98f8742 JVA |
1686 | /* Value is the number of bytes of arguments automatically |
1687 | popped when returning from a subroutine call. | |
8b109b37 | 1688 | FUNDECL is the declaration node of the function (as a tree), |
c98f8742 JVA |
1689 | FUNTYPE is the data type of the function (as a tree), |
1690 | or for a library call it is an identifier node for the subroutine name. | |
1691 | SIZE is the number of bytes of arguments passed on the stack. | |
1692 | ||
1693 | On the 80386, the RTD insn may be used to pop them if the number | |
1694 | of args is fixed, but if the number is variable then the caller | |
1695 | must pop them all. RTD can't be used for library calls now | |
1696 | because the library is compiled with the Unix compiler. | |
1697 | Use of RTD is a selectable option, since it is incompatible with | |
1698 | standard Unix calling sequences. If the option is not selected, | |
b08de47e MM |
1699 | the caller must always pop the args. |
1700 | ||
1701 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
c98f8742 | 1702 | |
d9a5f180 GS |
1703 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ |
1704 | ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) | |
c98f8742 | 1705 | |
8c2bf92a JVA |
1706 | /* Define how to find the value returned by a function. |
1707 | VALTYPE is the data type of the value (as a tree). | |
1708 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1709 | otherwise, FUNC is 0. */ | |
c98f8742 | 1710 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
53c17031 JH |
1711 | ix86_function_value (VALTYPE) |
1712 | ||
1713 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
1714 | ix86_function_value_regno_p (N) | |
c98f8742 JVA |
1715 | |
1716 | /* Define how to find the value returned by a library function | |
1717 | assuming the value has mode MODE. */ | |
1718 | ||
1719 | #define LIBCALL_VALUE(MODE) \ | |
53c17031 | 1720 | ix86_libcall_value (MODE) |
c98f8742 | 1721 | |
e9125c09 TW |
1722 | /* Define the size of the result block used for communication between |
1723 | untyped_call and untyped_return. The block contains a DImode value | |
1724 | followed by the block used by fnsave and frstor. */ | |
1725 | ||
1726 | #define APPLY_RESULT_SIZE (8+108) | |
1727 | ||
b08de47e | 1728 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1729 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1730 | |
1731 | /* Define a data type for recording info about an argument list | |
1732 | during the scan of that argument list. This data type should | |
1733 | hold all necessary information about the function itself | |
1734 | and about the args processed so far, enough to enable macros | |
b08de47e | 1735 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1736 | |
e075ae69 | 1737 | typedef struct ix86_args { |
b08de47e MM |
1738 | int words; /* # words passed so far */ |
1739 | int nregs; /* # registers available for passing */ | |
1740 | int regno; /* next available register number */ | |
e91f04de | 1741 | int fastcall; /* fastcall calling convention is used */ |
a7180f70 BS |
1742 | int sse_words; /* # sse words passed so far */ |
1743 | int sse_nregs; /* # sse registers available for passing */ | |
e1be55d0 JH |
1744 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
1745 | int warn_mmx; /* True when we want to warn about MMX ABI. */ | |
a7180f70 | 1746 | int sse_regno; /* next available sse register number */ |
bcf17554 JH |
1747 | int mmx_words; /* # mmx words passed so far */ |
1748 | int mmx_nregs; /* # mmx registers available for passing */ | |
1749 | int mmx_regno; /* next available mmx register number */ | |
892a2d68 | 1750 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
b08de47e | 1751 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1752 | |
1753 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1754 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1755 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1756 | |
0f6937fe | 1757 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
dafc5b82 | 1758 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
c98f8742 JVA |
1759 | |
1760 | /* Update the data in CUM to advance over an argument | |
1761 | of mode MODE and data type TYPE. | |
1762 | (TYPE is null for libcalls where that information may not be available.) */ | |
1763 | ||
d9a5f180 GS |
1764 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
1765 | function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
c98f8742 JVA |
1766 | |
1767 | /* Define where to put the arguments to a function. | |
1768 | Value is zero to push the argument on the stack, | |
1769 | or a hard register in which to store the argument. | |
1770 | ||
1771 | MODE is the argument's machine mode. | |
1772 | TYPE is the data type of the argument (as a tree). | |
1773 | This is null for libcalls where that information may | |
1774 | not be available. | |
1775 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1776 | the preceding args and about the function being called. | |
1777 | NAMED is nonzero if this argument is a named parameter | |
1778 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1779 | ||
c98f8742 | 1780 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
d9a5f180 | 1781 | function_arg (&(CUM), (MODE), (TYPE), (NAMED)) |
c98f8742 JVA |
1782 | |
1783 | /* For an arg passed partly in registers and partly in memory, | |
1784 | this is the number of registers used. | |
1785 | For args passed entirely in registers or entirely in memory, zero. */ | |
1786 | ||
e075ae69 | 1787 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 |
c98f8742 | 1788 | |
ad919812 | 1789 | /* Implement `va_start' for varargs and stdarg. */ |
e5faf155 ZW |
1790 | #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ |
1791 | ix86_va_start (VALIST, NEXTARG) | |
ad919812 | 1792 | |
a5fe455b ZW |
1793 | #define TARGET_ASM_FILE_END ix86_file_end |
1794 | #define NEED_INDICATE_EXEC_STACK 0 | |
3a0433fd | 1795 | |
c98f8742 JVA |
1796 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1797 | for profiling a function entry. */ | |
1798 | ||
a5fa1ecd JH |
1799 | #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) |
1800 | ||
1801 | #define MCOUNT_NAME "_mcount" | |
1802 | ||
1803 | #define PROFILE_COUNT_REGISTER "edx" | |
c98f8742 JVA |
1804 | |
1805 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1806 | the stack pointer does not matter. The value is tested only in | |
1807 | functions that have frame pointers. | |
1808 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1809 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1810 | we have to restore it ourselves from the frame pointer, in order to |
1811 | use pop */ | |
1812 | ||
1813 | #define EXIT_IGNORE_STACK 1 | |
1814 | ||
c98f8742 JVA |
1815 | /* Output assembler code for a block containing the constant parts |
1816 | of a trampoline, leaving space for the variable parts. */ | |
1817 | ||
a269a03c | 1818 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1819 | mov #STATIC,ecx |
a269a03c JC |
1820 | jmp FUNCTION |
1821 | The trampoline is generated entirely at runtime. The operand of JMP | |
1822 | is the address of FUNCTION relative to the instruction following the | |
1823 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1824 | |
1825 | /* Length in units of the trampoline for entering a nested function. */ | |
1826 | ||
39d04363 | 1827 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) |
c98f8742 JVA |
1828 | |
1829 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1830 | FNADDR is an RTX for the address of the function's pure code. | |
1831 | CXT is an RTX for the static chain value for the function. */ | |
1832 | ||
d9a5f180 GS |
1833 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1834 | x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
c98f8742 JVA |
1835 | \f |
1836 | /* Definitions for register eliminations. | |
1837 | ||
1838 | This is an array of structures. Each structure initializes one pair | |
1839 | of eliminable registers. The "from" register number is given first, | |
1840 | followed by "to". Eliminations of the same "from" register are listed | |
1841 | in order of preference. | |
1842 | ||
afc2cd05 NC |
1843 | There are two registers that can always be eliminated on the i386. |
1844 | The frame pointer and the arg pointer can be replaced by either the | |
1845 | hard frame pointer or to the stack pointer, depending upon the | |
1846 | circumstances. The hard frame pointer is not used before reload and | |
1847 | so it is not eligible for elimination. */ | |
c98f8742 | 1848 | |
564d80f4 JH |
1849 | #define ELIMINABLE_REGS \ |
1850 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1851 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1852 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1853 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1854 | |
2c5a510c RH |
1855 | /* Given FROM and TO register numbers, say whether this elimination is |
1856 | allowed. Frame pointer elimination is automatically handled. | |
c98f8742 JVA |
1857 | |
1858 | All other eliminations are valid. */ | |
1859 | ||
2c5a510c RH |
1860 | #define CAN_ELIMINATE(FROM, TO) \ |
1861 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) | |
c98f8742 JVA |
1862 | |
1863 | /* Define the offset between two registers, one to be eliminated, and the other | |
1864 | its replacement, at the start of a routine. */ | |
1865 | ||
d9a5f180 GS |
1866 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1867 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1868 | \f |
1869 | /* Addressing modes, and classification of registers for them. */ | |
1870 | ||
c98f8742 JVA |
1871 | /* Macros to check register numbers against specific register classes. */ |
1872 | ||
1873 | /* These assume that REGNO is a hard or pseudo reg number. | |
1874 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1875 | or a pseudo reg currently allocated to a suitable hard reg. | |
1876 | Since they use reg_renumber, they are safe only once reg_renumber | |
1877 | has been allocated, which happens in local-alloc.c. */ | |
1878 | ||
3f3f2124 JH |
1879 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1880 | ((REGNO) < STACK_POINTER_REGNUM \ | |
1881 | || (REGNO >= FIRST_REX_INT_REG \ | |
1882 | && (REGNO) <= LAST_REX_INT_REG) \ | |
d9a5f180 GS |
1883 | || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ |
1884 | && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ | |
1885 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) | |
c98f8742 | 1886 | |
3f3f2124 JH |
1887 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
1888 | ((REGNO) <= STACK_POINTER_REGNUM \ | |
1889 | || (REGNO) == ARG_POINTER_REGNUM \ | |
1890 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
1891 | || (REGNO >= FIRST_REX_INT_REG \ | |
1892 | && (REGNO) <= LAST_REX_INT_REG) \ | |
d9a5f180 GS |
1893 | || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ |
1894 | && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ | |
1895 | || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) | |
c98f8742 | 1896 | |
d9a5f180 GS |
1897 | #define REGNO_OK_FOR_SIREG_P(REGNO) \ |
1898 | ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) | |
1899 | #define REGNO_OK_FOR_DIREG_P(REGNO) \ | |
1900 | ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) | |
c98f8742 JVA |
1901 | |
1902 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1903 | and check its validity for a certain class. | |
1904 | We have two alternate definitions for each of them. | |
1905 | The usual definition accepts all pseudo regs; the other rejects | |
1906 | them unless they have been allocated suitable hard regs. | |
1907 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1908 | ||
1909 | Most source files want to accept pseudo regs in the hope that | |
1910 | they will get allocated to the class that the insn wants them to be in. | |
1911 | Source files for reload pass need to be strict. | |
1912 | After reload, it makes no difference, since pseudo regs have | |
1913 | been eliminated by then. */ | |
1914 | ||
c98f8742 | 1915 | |
ff482c8d | 1916 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1917 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1918 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
3f3f2124 JH |
1919 | || (REGNO (X) >= FIRST_REX_INT_REG \ |
1920 | && REGNO (X) <= LAST_REX_INT_REG) \ | |
c98f8742 JVA |
1921 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1922 | ||
3b3c6a3f MM |
1923 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
1924 | (REGNO (X) <= STACK_POINTER_REGNUM \ | |
1925 | || REGNO (X) == ARG_POINTER_REGNUM \ | |
3f3f2124 JH |
1926 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
1927 | || (REGNO (X) >= FIRST_REX_INT_REG \ | |
1928 | && REGNO (X) <= LAST_REX_INT_REG) \ | |
3b3c6a3f | 1929 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1930 | |
3b3c6a3f MM |
1931 | /* Strict versions, hard registers only */ |
1932 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1933 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1934 | |
3b3c6a3f | 1935 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1936 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1937 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1938 | |
1939 | #else | |
d9a5f180 GS |
1940 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1941 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1942 | #endif |
1943 | ||
1944 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1945 | that is a valid memory address for an instruction. | |
1946 | The MODE argument is the machine mode for the MEM expression | |
1947 | that wants to use this address. | |
1948 | ||
1949 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1950 | except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1951 | ||
1952 | See legitimize_pic_address in i386.c for details as to what | |
1953 | constitutes a legitimate address when -fpic is used. */ | |
1954 | ||
1955 | #define MAX_REGS_PER_ADDRESS 2 | |
1956 | ||
f996902d | 1957 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 JVA |
1958 | |
1959 | /* Nonzero if the constant value X is a legitimate general operand. | |
1960 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1961 | ||
f996902d | 1962 | #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) |
c98f8742 | 1963 | |
3b3c6a3f MM |
1964 | #ifdef REG_OK_STRICT |
1965 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1966 | do { \ |
1967 | if (legitimate_address_p ((MODE), (X), 1)) \ | |
3b3c6a3f | 1968 | goto ADDR; \ |
d9a5f180 | 1969 | } while (0) |
c98f8742 | 1970 | |
3b3c6a3f MM |
1971 | #else |
1972 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1973 | do { \ |
1974 | if (legitimate_address_p ((MODE), (X), 0)) \ | |
c98f8742 | 1975 | goto ADDR; \ |
d9a5f180 | 1976 | } while (0) |
c98f8742 | 1977 | |
3b3c6a3f MM |
1978 | #endif |
1979 | ||
b949ea8b JW |
1980 | /* If defined, a C expression to determine the base term of address X. |
1981 | This macro is used in only one place: `find_base_term' in alias.c. | |
1982 | ||
1983 | It is always safe for this macro to not be defined. It exists so | |
1984 | that alias analysis can understand machine-dependent addresses. | |
1985 | ||
1986 | The typical use of this macro is to handle addresses containing | |
1987 | a label_ref or symbol_ref within an UNSPEC. */ | |
1988 | ||
d9a5f180 | 1989 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1990 | |
c98f8742 JVA |
1991 | /* Try machine-dependent ways of modifying an illegitimate address |
1992 | to be legitimate. If we find one, return the new, valid address. | |
1993 | This macro is used in only one place: `memory_address' in explow.c. | |
1994 | ||
1995 | OLDX is the address as it was before break_out_memory_refs was called. | |
1996 | In some cases it is useful to look at this to decide what needs to be done. | |
1997 | ||
1998 | MODE and WIN are passed so that this macro can use | |
1999 | GO_IF_LEGITIMATE_ADDRESS. | |
2000 | ||
2001 | It is always safe for this macro to do nothing. It exists to recognize | |
2002 | opportunities to optimize the output. | |
2003 | ||
2004 | For the 80386, we handle X+REG by loading X into a register R and | |
2005 | using R+REG. R will go in a general reg and indexing will be used. | |
2006 | However, if REG is a broken-out memory address or multiplication, | |
2007 | nothing needs to be done because REG can certainly go in a general reg. | |
2008 | ||
2009 | When -fpic is used, special handling is needed for symbolic references. | |
2010 | See comments by legitimize_pic_address in i386.c for details. */ | |
2011 | ||
3b3c6a3f | 2012 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
d9a5f180 GS |
2013 | do { \ |
2014 | (X) = legitimize_address ((X), (OLDX), (MODE)); \ | |
2015 | if (memory_address_p ((MODE), (X))) \ | |
3b3c6a3f | 2016 | goto WIN; \ |
d9a5f180 | 2017 | } while (0) |
c98f8742 | 2018 | |
d9a5f180 | 2019 | #define REWRITE_ADDRESS(X) rewrite_address (X) |
d4ba09c0 | 2020 | |
c98f8742 | 2021 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 2022 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
2023 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
2024 | ||
f996902d | 2025 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
2026 | |
2027 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
2028 | (GET_CODE (X) == SYMBOL_REF \ |
2029 | || GET_CODE (X) == LABEL_REF \ | |
2030 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 JVA |
2031 | |
2032 | /* Go to LABEL if ADDR (a legitimate address expression) | |
2033 | has an effect that depends on the machine mode it is used for. | |
2034 | On the 80386, only postdecrement and postincrement address depend thus | |
2035 | (the amount of decrement or increment being the length of the operand). */ | |
d9a5f180 GS |
2036 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
2037 | do { \ | |
2038 | if (GET_CODE (ADDR) == POST_INC \ | |
2039 | || GET_CODE (ADDR) == POST_DEC) \ | |
2040 | goto LABEL; \ | |
2041 | } while (0) | |
c98f8742 | 2042 | \f |
bd793c65 BS |
2043 | /* Codes for all the SSE/MMX builtins. */ |
2044 | enum ix86_builtins | |
2045 | { | |
2046 | IX86_BUILTIN_ADDPS, | |
2047 | IX86_BUILTIN_ADDSS, | |
2048 | IX86_BUILTIN_DIVPS, | |
2049 | IX86_BUILTIN_DIVSS, | |
2050 | IX86_BUILTIN_MULPS, | |
2051 | IX86_BUILTIN_MULSS, | |
2052 | IX86_BUILTIN_SUBPS, | |
2053 | IX86_BUILTIN_SUBSS, | |
2054 | ||
2055 | IX86_BUILTIN_CMPEQPS, | |
2056 | IX86_BUILTIN_CMPLTPS, | |
2057 | IX86_BUILTIN_CMPLEPS, | |
2058 | IX86_BUILTIN_CMPGTPS, | |
2059 | IX86_BUILTIN_CMPGEPS, | |
2060 | IX86_BUILTIN_CMPNEQPS, | |
2061 | IX86_BUILTIN_CMPNLTPS, | |
2062 | IX86_BUILTIN_CMPNLEPS, | |
2063 | IX86_BUILTIN_CMPNGTPS, | |
2064 | IX86_BUILTIN_CMPNGEPS, | |
2065 | IX86_BUILTIN_CMPORDPS, | |
2066 | IX86_BUILTIN_CMPUNORDPS, | |
2067 | IX86_BUILTIN_CMPNEPS, | |
2068 | IX86_BUILTIN_CMPEQSS, | |
2069 | IX86_BUILTIN_CMPLTSS, | |
2070 | IX86_BUILTIN_CMPLESS, | |
bd793c65 BS |
2071 | IX86_BUILTIN_CMPNEQSS, |
2072 | IX86_BUILTIN_CMPNLTSS, | |
2073 | IX86_BUILTIN_CMPNLESS, | |
bd793c65 BS |
2074 | IX86_BUILTIN_CMPORDSS, |
2075 | IX86_BUILTIN_CMPUNORDSS, | |
2076 | IX86_BUILTIN_CMPNESS, | |
2077 | ||
2078 | IX86_BUILTIN_COMIEQSS, | |
2079 | IX86_BUILTIN_COMILTSS, | |
2080 | IX86_BUILTIN_COMILESS, | |
2081 | IX86_BUILTIN_COMIGTSS, | |
2082 | IX86_BUILTIN_COMIGESS, | |
2083 | IX86_BUILTIN_COMINEQSS, | |
2084 | IX86_BUILTIN_UCOMIEQSS, | |
2085 | IX86_BUILTIN_UCOMILTSS, | |
2086 | IX86_BUILTIN_UCOMILESS, | |
2087 | IX86_BUILTIN_UCOMIGTSS, | |
2088 | IX86_BUILTIN_UCOMIGESS, | |
2089 | IX86_BUILTIN_UCOMINEQSS, | |
2090 | ||
2091 | IX86_BUILTIN_CVTPI2PS, | |
2092 | IX86_BUILTIN_CVTPS2PI, | |
2093 | IX86_BUILTIN_CVTSI2SS, | |
453ee231 | 2094 | IX86_BUILTIN_CVTSI642SS, |
bd793c65 | 2095 | IX86_BUILTIN_CVTSS2SI, |
453ee231 | 2096 | IX86_BUILTIN_CVTSS2SI64, |
bd793c65 BS |
2097 | IX86_BUILTIN_CVTTPS2PI, |
2098 | IX86_BUILTIN_CVTTSS2SI, | |
453ee231 | 2099 | IX86_BUILTIN_CVTTSS2SI64, |
bd793c65 BS |
2100 | |
2101 | IX86_BUILTIN_MAXPS, | |
2102 | IX86_BUILTIN_MAXSS, | |
2103 | IX86_BUILTIN_MINPS, | |
2104 | IX86_BUILTIN_MINSS, | |
2105 | ||
2106 | IX86_BUILTIN_LOADAPS, | |
2107 | IX86_BUILTIN_LOADUPS, | |
2108 | IX86_BUILTIN_STOREAPS, | |
2109 | IX86_BUILTIN_STOREUPS, | |
2110 | IX86_BUILTIN_LOADSS, | |
2111 | IX86_BUILTIN_STORESS, | |
2112 | IX86_BUILTIN_MOVSS, | |
2113 | ||
2114 | IX86_BUILTIN_MOVHLPS, | |
2115 | IX86_BUILTIN_MOVLHPS, | |
2116 | IX86_BUILTIN_LOADHPS, | |
2117 | IX86_BUILTIN_LOADLPS, | |
2118 | IX86_BUILTIN_STOREHPS, | |
2119 | IX86_BUILTIN_STORELPS, | |
2120 | ||
2121 | IX86_BUILTIN_MASKMOVQ, | |
2122 | IX86_BUILTIN_MOVMSKPS, | |
2123 | IX86_BUILTIN_PMOVMSKB, | |
2124 | ||
2125 | IX86_BUILTIN_MOVNTPS, | |
2126 | IX86_BUILTIN_MOVNTQ, | |
2127 | ||
f02e1358 JH |
2128 | IX86_BUILTIN_LOADDQA, |
2129 | IX86_BUILTIN_LOADDQU, | |
2130 | IX86_BUILTIN_STOREDQA, | |
2131 | IX86_BUILTIN_STOREDQU, | |
2132 | IX86_BUILTIN_MOVQ, | |
2133 | IX86_BUILTIN_LOADD, | |
2134 | IX86_BUILTIN_STORED, | |
2135 | ||
2136 | IX86_BUILTIN_CLRTI, | |
2137 | ||
bd793c65 BS |
2138 | IX86_BUILTIN_PACKSSWB, |
2139 | IX86_BUILTIN_PACKSSDW, | |
2140 | IX86_BUILTIN_PACKUSWB, | |
2141 | ||
2142 | IX86_BUILTIN_PADDB, | |
2143 | IX86_BUILTIN_PADDW, | |
2144 | IX86_BUILTIN_PADDD, | |
d50672ef | 2145 | IX86_BUILTIN_PADDQ, |
bd793c65 BS |
2146 | IX86_BUILTIN_PADDSB, |
2147 | IX86_BUILTIN_PADDSW, | |
2148 | IX86_BUILTIN_PADDUSB, | |
2149 | IX86_BUILTIN_PADDUSW, | |
2150 | IX86_BUILTIN_PSUBB, | |
2151 | IX86_BUILTIN_PSUBW, | |
2152 | IX86_BUILTIN_PSUBD, | |
d50672ef | 2153 | IX86_BUILTIN_PSUBQ, |
bd793c65 BS |
2154 | IX86_BUILTIN_PSUBSB, |
2155 | IX86_BUILTIN_PSUBSW, | |
2156 | IX86_BUILTIN_PSUBUSB, | |
2157 | IX86_BUILTIN_PSUBUSW, | |
2158 | ||
2159 | IX86_BUILTIN_PAND, | |
2160 | IX86_BUILTIN_PANDN, | |
2161 | IX86_BUILTIN_POR, | |
2162 | IX86_BUILTIN_PXOR, | |
2163 | ||
2164 | IX86_BUILTIN_PAVGB, | |
2165 | IX86_BUILTIN_PAVGW, | |
2166 | ||
2167 | IX86_BUILTIN_PCMPEQB, | |
2168 | IX86_BUILTIN_PCMPEQW, | |
2169 | IX86_BUILTIN_PCMPEQD, | |
2170 | IX86_BUILTIN_PCMPGTB, | |
2171 | IX86_BUILTIN_PCMPGTW, | |
2172 | IX86_BUILTIN_PCMPGTD, | |
2173 | ||
2174 | IX86_BUILTIN_PEXTRW, | |
2175 | IX86_BUILTIN_PINSRW, | |
2176 | ||
2177 | IX86_BUILTIN_PMADDWD, | |
2178 | ||
2179 | IX86_BUILTIN_PMAXSW, | |
2180 | IX86_BUILTIN_PMAXUB, | |
2181 | IX86_BUILTIN_PMINSW, | |
2182 | IX86_BUILTIN_PMINUB, | |
2183 | ||
2184 | IX86_BUILTIN_PMULHUW, | |
2185 | IX86_BUILTIN_PMULHW, | |
2186 | IX86_BUILTIN_PMULLW, | |
2187 | ||
2188 | IX86_BUILTIN_PSADBW, | |
2189 | IX86_BUILTIN_PSHUFW, | |
2190 | ||
2191 | IX86_BUILTIN_PSLLW, | |
2192 | IX86_BUILTIN_PSLLD, | |
2193 | IX86_BUILTIN_PSLLQ, | |
2194 | IX86_BUILTIN_PSRAW, | |
2195 | IX86_BUILTIN_PSRAD, | |
2196 | IX86_BUILTIN_PSRLW, | |
2197 | IX86_BUILTIN_PSRLD, | |
2198 | IX86_BUILTIN_PSRLQ, | |
2199 | IX86_BUILTIN_PSLLWI, | |
2200 | IX86_BUILTIN_PSLLDI, | |
2201 | IX86_BUILTIN_PSLLQI, | |
2202 | IX86_BUILTIN_PSRAWI, | |
2203 | IX86_BUILTIN_PSRADI, | |
2204 | IX86_BUILTIN_PSRLWI, | |
2205 | IX86_BUILTIN_PSRLDI, | |
2206 | IX86_BUILTIN_PSRLQI, | |
2207 | ||
2208 | IX86_BUILTIN_PUNPCKHBW, | |
2209 | IX86_BUILTIN_PUNPCKHWD, | |
2210 | IX86_BUILTIN_PUNPCKHDQ, | |
2211 | IX86_BUILTIN_PUNPCKLBW, | |
2212 | IX86_BUILTIN_PUNPCKLWD, | |
2213 | IX86_BUILTIN_PUNPCKLDQ, | |
2214 | ||
2215 | IX86_BUILTIN_SHUFPS, | |
2216 | ||
2217 | IX86_BUILTIN_RCPPS, | |
2218 | IX86_BUILTIN_RCPSS, | |
2219 | IX86_BUILTIN_RSQRTPS, | |
2220 | IX86_BUILTIN_RSQRTSS, | |
2221 | IX86_BUILTIN_SQRTPS, | |
2222 | IX86_BUILTIN_SQRTSS, | |
fce5a9f2 | 2223 | |
bd793c65 BS |
2224 | IX86_BUILTIN_UNPCKHPS, |
2225 | IX86_BUILTIN_UNPCKLPS, | |
2226 | ||
2227 | IX86_BUILTIN_ANDPS, | |
2228 | IX86_BUILTIN_ANDNPS, | |
2229 | IX86_BUILTIN_ORPS, | |
2230 | IX86_BUILTIN_XORPS, | |
2231 | ||
2232 | IX86_BUILTIN_EMMS, | |
2233 | IX86_BUILTIN_LDMXCSR, | |
2234 | IX86_BUILTIN_STMXCSR, | |
2235 | IX86_BUILTIN_SFENCE, | |
bd793c65 | 2236 | |
47f339cf BS |
2237 | /* 3DNow! Original */ |
2238 | IX86_BUILTIN_FEMMS, | |
2239 | IX86_BUILTIN_PAVGUSB, | |
2240 | IX86_BUILTIN_PF2ID, | |
2241 | IX86_BUILTIN_PFACC, | |
2242 | IX86_BUILTIN_PFADD, | |
2243 | IX86_BUILTIN_PFCMPEQ, | |
2244 | IX86_BUILTIN_PFCMPGE, | |
2245 | IX86_BUILTIN_PFCMPGT, | |
2246 | IX86_BUILTIN_PFMAX, | |
2247 | IX86_BUILTIN_PFMIN, | |
2248 | IX86_BUILTIN_PFMUL, | |
2249 | IX86_BUILTIN_PFRCP, | |
2250 | IX86_BUILTIN_PFRCPIT1, | |
2251 | IX86_BUILTIN_PFRCPIT2, | |
2252 | IX86_BUILTIN_PFRSQIT1, | |
2253 | IX86_BUILTIN_PFRSQRT, | |
2254 | IX86_BUILTIN_PFSUB, | |
2255 | IX86_BUILTIN_PFSUBR, | |
2256 | IX86_BUILTIN_PI2FD, | |
2257 | IX86_BUILTIN_PMULHRW, | |
47f339cf BS |
2258 | |
2259 | /* 3DNow! Athlon Extensions */ | |
2260 | IX86_BUILTIN_PF2IW, | |
2261 | IX86_BUILTIN_PFNACC, | |
2262 | IX86_BUILTIN_PFPNACC, | |
2263 | IX86_BUILTIN_PI2FW, | |
2264 | IX86_BUILTIN_PSWAPDSI, | |
2265 | IX86_BUILTIN_PSWAPDSF, | |
2266 | ||
e37af218 | 2267 | IX86_BUILTIN_SSE_ZERO, |
bd793c65 BS |
2268 | IX86_BUILTIN_MMX_ZERO, |
2269 | ||
fbe5eb6d BS |
2270 | /* SSE2 */ |
2271 | IX86_BUILTIN_ADDPD, | |
2272 | IX86_BUILTIN_ADDSD, | |
2273 | IX86_BUILTIN_DIVPD, | |
2274 | IX86_BUILTIN_DIVSD, | |
2275 | IX86_BUILTIN_MULPD, | |
2276 | IX86_BUILTIN_MULSD, | |
2277 | IX86_BUILTIN_SUBPD, | |
2278 | IX86_BUILTIN_SUBSD, | |
2279 | ||
2280 | IX86_BUILTIN_CMPEQPD, | |
2281 | IX86_BUILTIN_CMPLTPD, | |
2282 | IX86_BUILTIN_CMPLEPD, | |
2283 | IX86_BUILTIN_CMPGTPD, | |
2284 | IX86_BUILTIN_CMPGEPD, | |
2285 | IX86_BUILTIN_CMPNEQPD, | |
2286 | IX86_BUILTIN_CMPNLTPD, | |
2287 | IX86_BUILTIN_CMPNLEPD, | |
2288 | IX86_BUILTIN_CMPNGTPD, | |
2289 | IX86_BUILTIN_CMPNGEPD, | |
2290 | IX86_BUILTIN_CMPORDPD, | |
2291 | IX86_BUILTIN_CMPUNORDPD, | |
2292 | IX86_BUILTIN_CMPNEPD, | |
2293 | IX86_BUILTIN_CMPEQSD, | |
2294 | IX86_BUILTIN_CMPLTSD, | |
2295 | IX86_BUILTIN_CMPLESD, | |
fbe5eb6d BS |
2296 | IX86_BUILTIN_CMPNEQSD, |
2297 | IX86_BUILTIN_CMPNLTSD, | |
2298 | IX86_BUILTIN_CMPNLESD, | |
fbe5eb6d BS |
2299 | IX86_BUILTIN_CMPORDSD, |
2300 | IX86_BUILTIN_CMPUNORDSD, | |
2301 | IX86_BUILTIN_CMPNESD, | |
2302 | ||
2303 | IX86_BUILTIN_COMIEQSD, | |
2304 | IX86_BUILTIN_COMILTSD, | |
2305 | IX86_BUILTIN_COMILESD, | |
2306 | IX86_BUILTIN_COMIGTSD, | |
2307 | IX86_BUILTIN_COMIGESD, | |
2308 | IX86_BUILTIN_COMINEQSD, | |
2309 | IX86_BUILTIN_UCOMIEQSD, | |
2310 | IX86_BUILTIN_UCOMILTSD, | |
2311 | IX86_BUILTIN_UCOMILESD, | |
2312 | IX86_BUILTIN_UCOMIGTSD, | |
2313 | IX86_BUILTIN_UCOMIGESD, | |
2314 | IX86_BUILTIN_UCOMINEQSD, | |
2315 | ||
2316 | IX86_BUILTIN_MAXPD, | |
2317 | IX86_BUILTIN_MAXSD, | |
2318 | IX86_BUILTIN_MINPD, | |
2319 | IX86_BUILTIN_MINSD, | |
2320 | ||
2321 | IX86_BUILTIN_ANDPD, | |
2322 | IX86_BUILTIN_ANDNPD, | |
2323 | IX86_BUILTIN_ORPD, | |
2324 | IX86_BUILTIN_XORPD, | |
2325 | ||
2326 | IX86_BUILTIN_SQRTPD, | |
2327 | IX86_BUILTIN_SQRTSD, | |
2328 | ||
2329 | IX86_BUILTIN_UNPCKHPD, | |
2330 | IX86_BUILTIN_UNPCKLPD, | |
2331 | ||
2332 | IX86_BUILTIN_SHUFPD, | |
2333 | ||
2334 | IX86_BUILTIN_LOADAPD, | |
2335 | IX86_BUILTIN_LOADUPD, | |
2336 | IX86_BUILTIN_STOREAPD, | |
2337 | IX86_BUILTIN_STOREUPD, | |
2338 | IX86_BUILTIN_LOADSD, | |
2339 | IX86_BUILTIN_STORESD, | |
2340 | IX86_BUILTIN_MOVSD, | |
2341 | ||
2342 | IX86_BUILTIN_LOADHPD, | |
2343 | IX86_BUILTIN_LOADLPD, | |
2344 | IX86_BUILTIN_STOREHPD, | |
2345 | IX86_BUILTIN_STORELPD, | |
2346 | ||
2347 | IX86_BUILTIN_CVTDQ2PD, | |
2348 | IX86_BUILTIN_CVTDQ2PS, | |
2349 | ||
2350 | IX86_BUILTIN_CVTPD2DQ, | |
2351 | IX86_BUILTIN_CVTPD2PI, | |
2352 | IX86_BUILTIN_CVTPD2PS, | |
2353 | IX86_BUILTIN_CVTTPD2DQ, | |
2354 | IX86_BUILTIN_CVTTPD2PI, | |
2355 | ||
2356 | IX86_BUILTIN_CVTPI2PD, | |
2357 | IX86_BUILTIN_CVTSI2SD, | |
453ee231 | 2358 | IX86_BUILTIN_CVTSI642SD, |
fbe5eb6d BS |
2359 | |
2360 | IX86_BUILTIN_CVTSD2SI, | |
453ee231 | 2361 | IX86_BUILTIN_CVTSD2SI64, |
fbe5eb6d BS |
2362 | IX86_BUILTIN_CVTSD2SS, |
2363 | IX86_BUILTIN_CVTSS2SD, | |
2364 | IX86_BUILTIN_CVTTSD2SI, | |
453ee231 | 2365 | IX86_BUILTIN_CVTTSD2SI64, |
fbe5eb6d BS |
2366 | |
2367 | IX86_BUILTIN_CVTPS2DQ, | |
2368 | IX86_BUILTIN_CVTPS2PD, | |
2369 | IX86_BUILTIN_CVTTPS2DQ, | |
2370 | ||
2371 | IX86_BUILTIN_MOVNTI, | |
2372 | IX86_BUILTIN_MOVNTPD, | |
2373 | IX86_BUILTIN_MOVNTDQ, | |
2374 | ||
2375 | IX86_BUILTIN_SETPD1, | |
2376 | IX86_BUILTIN_SETPD, | |
2377 | IX86_BUILTIN_CLRPD, | |
2378 | IX86_BUILTIN_SETRPD, | |
2379 | IX86_BUILTIN_LOADPD1, | |
2380 | IX86_BUILTIN_LOADRPD, | |
2381 | IX86_BUILTIN_STOREPD1, | |
2382 | IX86_BUILTIN_STORERPD, | |
2383 | ||
2384 | /* SSE2 MMX */ | |
2385 | IX86_BUILTIN_MASKMOVDQU, | |
2386 | IX86_BUILTIN_MOVMSKPD, | |
2387 | IX86_BUILTIN_PMOVMSKB128, | |
2388 | IX86_BUILTIN_MOVQ2DQ, | |
f02e1358 | 2389 | IX86_BUILTIN_MOVDQ2Q, |
fbe5eb6d BS |
2390 | |
2391 | IX86_BUILTIN_PACKSSWB128, | |
2392 | IX86_BUILTIN_PACKSSDW128, | |
2393 | IX86_BUILTIN_PACKUSWB128, | |
2394 | ||
2395 | IX86_BUILTIN_PADDB128, | |
2396 | IX86_BUILTIN_PADDW128, | |
2397 | IX86_BUILTIN_PADDD128, | |
2398 | IX86_BUILTIN_PADDQ128, | |
2399 | IX86_BUILTIN_PADDSB128, | |
2400 | IX86_BUILTIN_PADDSW128, | |
2401 | IX86_BUILTIN_PADDUSB128, | |
2402 | IX86_BUILTIN_PADDUSW128, | |
2403 | IX86_BUILTIN_PSUBB128, | |
2404 | IX86_BUILTIN_PSUBW128, | |
2405 | IX86_BUILTIN_PSUBD128, | |
2406 | IX86_BUILTIN_PSUBQ128, | |
2407 | IX86_BUILTIN_PSUBSB128, | |
2408 | IX86_BUILTIN_PSUBSW128, | |
2409 | IX86_BUILTIN_PSUBUSB128, | |
2410 | IX86_BUILTIN_PSUBUSW128, | |
2411 | ||
2412 | IX86_BUILTIN_PAND128, | |
2413 | IX86_BUILTIN_PANDN128, | |
2414 | IX86_BUILTIN_POR128, | |
2415 | IX86_BUILTIN_PXOR128, | |
2416 | ||
2417 | IX86_BUILTIN_PAVGB128, | |
2418 | IX86_BUILTIN_PAVGW128, | |
2419 | ||
2420 | IX86_BUILTIN_PCMPEQB128, | |
2421 | IX86_BUILTIN_PCMPEQW128, | |
2422 | IX86_BUILTIN_PCMPEQD128, | |
2423 | IX86_BUILTIN_PCMPGTB128, | |
2424 | IX86_BUILTIN_PCMPGTW128, | |
2425 | IX86_BUILTIN_PCMPGTD128, | |
2426 | ||
2427 | IX86_BUILTIN_PEXTRW128, | |
2428 | IX86_BUILTIN_PINSRW128, | |
2429 | ||
2430 | IX86_BUILTIN_PMADDWD128, | |
2431 | ||
2432 | IX86_BUILTIN_PMAXSW128, | |
2433 | IX86_BUILTIN_PMAXUB128, | |
2434 | IX86_BUILTIN_PMINSW128, | |
2435 | IX86_BUILTIN_PMINUB128, | |
2436 | ||
2437 | IX86_BUILTIN_PMULUDQ, | |
2438 | IX86_BUILTIN_PMULUDQ128, | |
2439 | IX86_BUILTIN_PMULHUW128, | |
2440 | IX86_BUILTIN_PMULHW128, | |
2441 | IX86_BUILTIN_PMULLW128, | |
2442 | ||
2443 | IX86_BUILTIN_PSADBW128, | |
2444 | IX86_BUILTIN_PSHUFHW, | |
2445 | IX86_BUILTIN_PSHUFLW, | |
2446 | IX86_BUILTIN_PSHUFD, | |
2447 | ||
2448 | IX86_BUILTIN_PSLLW128, | |
2449 | IX86_BUILTIN_PSLLD128, | |
2450 | IX86_BUILTIN_PSLLQ128, | |
2451 | IX86_BUILTIN_PSRAW128, | |
2452 | IX86_BUILTIN_PSRAD128, | |
2453 | IX86_BUILTIN_PSRLW128, | |
2454 | IX86_BUILTIN_PSRLD128, | |
2455 | IX86_BUILTIN_PSRLQ128, | |
ab3146fd | 2456 | IX86_BUILTIN_PSLLDQI128, |
fbe5eb6d BS |
2457 | IX86_BUILTIN_PSLLWI128, |
2458 | IX86_BUILTIN_PSLLDI128, | |
2459 | IX86_BUILTIN_PSLLQI128, | |
2460 | IX86_BUILTIN_PSRAWI128, | |
2461 | IX86_BUILTIN_PSRADI128, | |
ab3146fd | 2462 | IX86_BUILTIN_PSRLDQI128, |
fbe5eb6d BS |
2463 | IX86_BUILTIN_PSRLWI128, |
2464 | IX86_BUILTIN_PSRLDI128, | |
2465 | IX86_BUILTIN_PSRLQI128, | |
2466 | ||
2467 | IX86_BUILTIN_PUNPCKHBW128, | |
2468 | IX86_BUILTIN_PUNPCKHWD128, | |
2469 | IX86_BUILTIN_PUNPCKHDQ128, | |
077084dd | 2470 | IX86_BUILTIN_PUNPCKHQDQ128, |
fbe5eb6d BS |
2471 | IX86_BUILTIN_PUNPCKLBW128, |
2472 | IX86_BUILTIN_PUNPCKLWD128, | |
2473 | IX86_BUILTIN_PUNPCKLDQ128, | |
f02e1358 | 2474 | IX86_BUILTIN_PUNPCKLQDQ128, |
fbe5eb6d BS |
2475 | |
2476 | IX86_BUILTIN_CLFLUSH, | |
2477 | IX86_BUILTIN_MFENCE, | |
2478 | IX86_BUILTIN_LFENCE, | |
2479 | ||
22c7c85e L |
2480 | /* Prescott New Instructions. */ |
2481 | IX86_BUILTIN_ADDSUBPS, | |
2482 | IX86_BUILTIN_HADDPS, | |
2483 | IX86_BUILTIN_HSUBPS, | |
2484 | IX86_BUILTIN_MOVSHDUP, | |
2485 | IX86_BUILTIN_MOVSLDUP, | |
2486 | IX86_BUILTIN_ADDSUBPD, | |
2487 | IX86_BUILTIN_HADDPD, | |
2488 | IX86_BUILTIN_HSUBPD, | |
2489 | IX86_BUILTIN_LOADDDUP, | |
2490 | IX86_BUILTIN_MOVDDUP, | |
2491 | IX86_BUILTIN_LDDQU, | |
2492 | ||
2493 | IX86_BUILTIN_MONITOR, | |
2494 | IX86_BUILTIN_MWAIT, | |
2495 | ||
bd793c65 BS |
2496 | IX86_BUILTIN_MAX |
2497 | }; | |
bd793c65 | 2498 | \f |
b08de47e MM |
2499 | /* Max number of args passed in registers. If this is more than 3, we will |
2500 | have problems with ebx (register #4), since it is a caller save register and | |
2501 | is also used as the pic register in ELF. So for now, don't allow more than | |
2502 | 3 registers to be passed in registers. */ | |
2503 | ||
d2836273 JH |
2504 | #define REGPARM_MAX (TARGET_64BIT ? 6 : 3) |
2505 | ||
bcf17554 JH |
2506 | #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) |
2507 | ||
2508 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
b08de47e | 2509 | |
c98f8742 JVA |
2510 | \f |
2511 | /* Specify the machine mode that this machine uses | |
2512 | for the index in the tablejump instruction. */ | |
6eb791fc | 2513 | #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) |
c98f8742 | 2514 | |
c98f8742 JVA |
2515 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
2516 | #define DEFAULT_SIGNED_CHAR 1 | |
2517 | ||
f4365627 JH |
2518 | /* Number of bytes moved into a data cache for a single prefetch operation. */ |
2519 | #define PREFETCH_BLOCK ix86_cost->prefetch_block | |
2520 | ||
2521 | /* Number of prefetch operations that can be done in parallel. */ | |
2522 | #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches | |
2523 | ||
c98f8742 JVA |
2524 | /* Max number of bytes we can move from memory to memory |
2525 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
2526 | #define MOVE_MAX 16 |
2527 | ||
2528 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
2529 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
892a2d68 | 2530 | number of bytes we can move with a single instruction. */ |
65d9c0ab | 2531 | #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) |
c98f8742 | 2532 | |
7e24ffc9 | 2533 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 2534 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
2535 | Increasing the value will always make code faster, but eventually |
2536 | incurs high cost in increased code size. | |
c98f8742 | 2537 | |
e2e52e1b | 2538 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 2539 | |
e2e52e1b | 2540 | #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) |
c98f8742 | 2541 | |
45d78e7f JJ |
2542 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
2543 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
2544 | ||
2545 | #define CLEAR_RATIO (optimize_size ? 2 \ | |
2546 | : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio) | |
2547 | ||
c98f8742 JVA |
2548 | /* Define if shifts truncate the shift count |
2549 | which implies one can omit a sign-extension or zero-extension | |
2550 | of a shift count. */ | |
892a2d68 | 2551 | /* On i386, shifts do truncate the count. But bit opcodes don't. */ |
c98f8742 JVA |
2552 | |
2553 | /* #define SHIFT_COUNT_TRUNCATED */ | |
2554 | ||
2555 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
2556 | is done just by pretending it is already truncated. */ | |
2557 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2558 | ||
d9f32422 JH |
2559 | /* A macro to update M and UNSIGNEDP when an object whose type is |
2560 | TYPE and which has the specified mode and signedness is to be | |
2561 | stored in a register. This macro is only called when TYPE is a | |
2562 | scalar type. | |
2563 | ||
f710504c | 2564 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
2565 | quantities to SImode. The choice depends on target type. */ |
2566 | ||
2567 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 2568 | do { \ |
d9f32422 JH |
2569 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
2570 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
2571 | (MODE) = SImode; \ |
2572 | } while (0) | |
d9f32422 | 2573 | |
c98f8742 JVA |
2574 | /* Specify the machine mode that pointers have. |
2575 | After generation of rtl, the compiler makes no further distinction | |
2576 | between pointers and any other objects of this machine mode. */ | |
65d9c0ab | 2577 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
c98f8742 JVA |
2578 | |
2579 | /* A function address in a call instruction | |
2580 | is a byte address (for indexing purposes) | |
2581 | so give the MEM rtx a byte's mode. */ | |
2582 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 2583 | \f |
96e7ae40 JH |
2584 | /* A C expression for the cost of moving data from a register in class FROM to |
2585 | one in class TO. The classes are expressed using the enumeration values | |
2586 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
2587 | interpreted relative to that. | |
d4ba09c0 | 2588 | |
96e7ae40 JH |
2589 | It is not required that the cost always equal 2 when FROM is the same as TO; |
2590 | on some machines it is expensive to move between registers if they are not | |
f84aa48a | 2591 | general registers. */ |
d4ba09c0 | 2592 | |
f84aa48a | 2593 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
d9a5f180 | 2594 | ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) |
d4ba09c0 SC |
2595 | |
2596 | /* A C expression for the cost of moving data of mode M between a | |
2597 | register and memory. A value of 2 is the default; this cost is | |
2598 | relative to those in `REGISTER_MOVE_COST'. | |
2599 | ||
2600 | If moving between registers and memory is more expensive than | |
2601 | between two registers, you should define this macro to express the | |
fa79946e | 2602 | relative cost. */ |
d4ba09c0 | 2603 | |
d9a5f180 GS |
2604 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ |
2605 | ix86_memory_move_cost ((MODE), (CLASS), (IN)) | |
d4ba09c0 SC |
2606 | |
2607 | /* A C expression for the cost of a branch instruction. A value of 1 | |
2608 | is the default; other values are interpreted relative to that. */ | |
2609 | ||
e075ae69 | 2610 | #define BRANCH_COST ix86_branch_cost |
d4ba09c0 SC |
2611 | |
2612 | /* Define this macro as a C expression which is nonzero if accessing | |
2613 | less than a word of memory (i.e. a `char' or a `short') is no | |
2614 | faster than accessing a word of memory, i.e., if such access | |
2615 | require more than one instruction or if there is no difference in | |
2616 | cost between byte and (aligned) word loads. | |
2617 | ||
2618 | When this macro is not defined, the compiler will access a field by | |
2619 | finding the smallest containing object; when it is defined, a | |
2620 | fullword load will be used if alignment permits. Unless bytes | |
2621 | accesses are faster than word accesses, using word accesses is | |
2622 | preferable since it may eliminate subsequent memory access if | |
2623 | subsequent accesses occur to other fields in the same word of the | |
2624 | structure, but to different bytes. */ | |
2625 | ||
2626 | #define SLOW_BYTE_ACCESS 0 | |
2627 | ||
2628 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
2629 | #define SLOW_SHORT_ACCESS 0 | |
2630 | ||
d4ba09c0 SC |
2631 | /* Define this macro to be the value 1 if unaligned accesses have a |
2632 | cost many times greater than aligned accesses, for example if they | |
2633 | are emulated in a trap handler. | |
2634 | ||
9cd10576 KH |
2635 | When this macro is nonzero, the compiler will act as if |
2636 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
d4ba09c0 | 2637 | moves. This can cause significantly more instructions to be |
9cd10576 | 2638 | produced. Therefore, do not set this macro nonzero if unaligned |
d4ba09c0 SC |
2639 | accesses only add a cycle or two to the time for a memory access. |
2640 | ||
2641 | If the value of this macro is always zero, it need not be defined. */ | |
2642 | ||
e1565e65 | 2643 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 | 2644 | |
d4ba09c0 SC |
2645 | /* Define this macro if it is as good or better to call a constant |
2646 | function address than to call an address kept in a register. | |
2647 | ||
2648 | Desirable on the 386 because a CALL with a constant address is | |
2649 | faster than one with a register address. */ | |
2650 | ||
2651 | #define NO_FUNCTION_CSE | |
c98f8742 | 2652 | \f |
c572e5ba JVA |
2653 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2654 | return the mode to be used for the comparison. | |
2655 | ||
2656 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 2657 | VOIDmode should be used in all other cases. |
c572e5ba | 2658 | |
16189740 | 2659 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 2660 | possible, to allow for more combinations. */ |
c98f8742 | 2661 | |
d9a5f180 | 2662 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 2663 | |
9cd10576 | 2664 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
2665 | reversed. */ |
2666 | ||
2667 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2668 | ||
2669 | /* A C expression whose value is reversed condition code of the CODE for | |
2670 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 2671 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 2672 | |
c98f8742 JVA |
2673 | \f |
2674 | /* Control the assembler format that we output, to the extent | |
2675 | this does not vary between assemblers. */ | |
2676 | ||
2677 | /* How to refer to registers in assembler output. | |
892a2d68 | 2678 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 JVA |
2679 | |
2680 | /* In order to refer to the first 8 regs as 32 bit regs prefix an "e" | |
2681 | For non floating point regs, the following are the HImode names. | |
2682 | ||
2683 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
a55f4481 | 2684 | instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ |
c98f8742 | 2685 | |
a7180f70 BS |
2686 | #define HI_REGISTER_NAMES \ |
2687 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 ZW |
2688 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
2689 | "argp", "flags", "fpsr", "dirflag", "frame", \ | |
a7180f70 | 2690 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
3f3f2124 JH |
2691 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ |
2692 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
2693 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} | |
a7180f70 | 2694 | |
c98f8742 JVA |
2695 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2696 | ||
2697 | /* Table of additional register names to use in user input. */ | |
2698 | ||
2699 | #define ADDITIONAL_REGISTER_NAMES \ | |
54d26233 MH |
2700 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2701 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
3f3f2124 JH |
2702 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ |
2703 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
54d26233 | 2704 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ |
a7180f70 BS |
2705 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ |
2706 | { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ | |
2707 | { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } | |
c98f8742 JVA |
2708 | |
2709 | /* Note we are omitting these since currently I don't know how | |
2710 | to get gcc to use these, since they want the same but different | |
2711 | number as al, and ax. | |
2712 | */ | |
2713 | ||
c98f8742 | 2714 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 2715 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
2716 | |
2717 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 2718 | of regs 0 through 3. */ |
c98f8742 JVA |
2719 | |
2720 | #define QI_HIGH_REGISTER_NAMES \ | |
2721 | {"ah", "dh", "ch", "bh", } | |
2722 | ||
2723 | /* How to renumber registers for dbx and gdb. */ | |
2724 | ||
d9a5f180 GS |
2725 | #define DBX_REGISTER_NUMBER(N) \ |
2726 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 RH |
2727 | |
2728 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
0f7fa3d0 | 2729 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; |
83774849 | 2730 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; |
c98f8742 | 2731 | |
469ac993 JM |
2732 | /* Before the prologue, RA is at 0(%esp). */ |
2733 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 2734 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
fce5a9f2 | 2735 | |
e414ab29 | 2736 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1020a5ab RH |
2737 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2738 | ((COUNT) == 0 \ | |
2739 | ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ | |
2740 | : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
e414ab29 | 2741 | |
892a2d68 | 2742 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2743 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2744 | |
a6ab3aad | 2745 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
0f7fa3d0 | 2746 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
a6ab3aad | 2747 | |
1020a5ab RH |
2748 | /* Describe how we implement __builtin_eh_return. */ |
2749 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
2750 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
2751 | ||
ad919812 | 2752 | |
e4c4ebeb RH |
2753 | /* Select a format to encode pointers in exception handling data. CODE |
2754 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2755 | true if the symbol may be affected by dynamic relocations. | |
2756 | ||
2757 | ??? All x86 object file formats are capable of representing this. | |
2758 | After all, the relocation needed is the same as for the call insn. | |
2759 | Whether or not a particular assembler allows us to enter such, I | |
2760 | guess we'll have to see. */ | |
d9a5f180 | 2761 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
b932f770 | 2762 | (flag_pic \ |
d9a5f180 | 2763 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ |
e4c4ebeb RH |
2764 | : DW_EH_PE_absptr) |
2765 | ||
c98f8742 JVA |
2766 | /* This is how to output an insn to push a register on the stack. |
2767 | It need not be very fast code. */ | |
2768 | ||
d9a5f180 | 2769 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
0d1c5774 JJ |
2770 | do { \ |
2771 | if (TARGET_64BIT) \ | |
2772 | asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
2773 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2774 | else \ | |
2775 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2776 | } while (0) | |
c98f8742 JVA |
2777 | |
2778 | /* This is how to output an insn to pop a register from the stack. | |
2779 | It need not be very fast code. */ | |
2780 | ||
d9a5f180 | 2781 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
0d1c5774 JJ |
2782 | do { \ |
2783 | if (TARGET_64BIT) \ | |
2784 | asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
2785 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2786 | else \ | |
2787 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2788 | } while (0) | |
c98f8742 | 2789 | |
f88c65f7 | 2790 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2791 | |
2792 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2793 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2794 | |
f88c65f7 | 2795 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2796 | |
33f7f353 | 2797 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2798 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 RH |
2799 | |
2800 | /* Under some conditions we need jump tables in the text section, because | |
2801 | the assembler cannot handle label differences between sections. */ | |
2802 | ||
2803 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
2804 | (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) | |
c98f8742 | 2805 | |
b9203463 RH |
2806 | /* Emit a dtp-relative reference to a TLS variable. */ |
2807 | ||
2808 | #ifdef HAVE_AS_TLS | |
2809 | #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ | |
2810 | i386_output_dwarf_dtprel (FILE, SIZE, X) | |
2811 | #endif | |
2812 | ||
cea3bd3e RH |
2813 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2814 | and switch back. For x86 we do this only to save a few bytes that | |
2815 | would otherwise be unused in the text section. */ | |
2816 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2817 | asm (SECTION_OP "\n\t" \ | |
2818 | "call " USER_LABEL_PREFIX #FUNC "\n" \ | |
2819 | TEXT_SECTION_ASM_OP); | |
74b42c8b | 2820 | \f |
c98f8742 JVA |
2821 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2822 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
ef6257cd JH |
2823 | Effect of various CODE letters is described in i386.c near |
2824 | print_operand function. */ | |
c98f8742 | 2825 | |
d9a5f180 | 2826 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
f996902d | 2827 | ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') |
c98f8742 JVA |
2828 | |
2829 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
d9a5f180 | 2830 | print_operand ((FILE), (X), (CODE)) |
c98f8742 JVA |
2831 | |
2832 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
d9a5f180 | 2833 | print_operand_address ((FILE), (ADDR)) |
c98f8742 | 2834 | |
f996902d RH |
2835 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ |
2836 | do { \ | |
2837 | if (! output_addr_const_extra (FILE, (X))) \ | |
2838 | goto FAIL; \ | |
2839 | } while (0); | |
2840 | ||
c98f8742 JVA |
2841 | /* a letter which is not needed by the normal asm syntax, which |
2842 | we can use for operand syntax in the extended asm */ | |
2843 | ||
2844 | #define ASM_OPERAND_LETTER '#' | |
c98f8742 | 2845 | #define RET return "" |
d9a5f180 | 2846 | #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) |
d4ba09c0 | 2847 | \f |
5bf0ebab RH |
2848 | /* Which processor to schedule for. The cpu attribute defines a list that |
2849 | mirrors this list, so changes to i386.md must be made at the same time. */ | |
2850 | ||
2851 | enum processor_type | |
2852 | { | |
2853 | PROCESSOR_I386, /* 80386 */ | |
2854 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ | |
2855 | PROCESSOR_PENTIUM, | |
2856 | PROCESSOR_PENTIUMPRO, | |
2857 | PROCESSOR_K6, | |
2858 | PROCESSOR_ATHLON, | |
2859 | PROCESSOR_PENTIUM4, | |
4977bab6 | 2860 | PROCESSOR_K8, |
89c43c0a | 2861 | PROCESSOR_NOCONA, |
5bf0ebab RH |
2862 | PROCESSOR_max |
2863 | }; | |
2864 | ||
9e555526 RH |
2865 | extern enum processor_type ix86_tune; |
2866 | extern const char *ix86_tune_string; | |
5bf0ebab RH |
2867 | |
2868 | extern enum processor_type ix86_arch; | |
2869 | extern const char *ix86_arch_string; | |
2870 | ||
2871 | enum fpmath_unit | |
2872 | { | |
2873 | FPMATH_387 = 1, | |
2874 | FPMATH_SSE = 2 | |
2875 | }; | |
2876 | ||
2877 | extern enum fpmath_unit ix86_fpmath; | |
2878 | extern const char *ix86_fpmath_string; | |
2879 | ||
f996902d RH |
2880 | enum tls_dialect |
2881 | { | |
2882 | TLS_DIALECT_GNU, | |
2883 | TLS_DIALECT_SUN | |
2884 | }; | |
2885 | ||
2886 | extern enum tls_dialect ix86_tls_dialect; | |
2887 | extern const char *ix86_tls_dialect_string; | |
2888 | ||
6189a572 | 2889 | enum cmodel { |
5bf0ebab RH |
2890 | CM_32, /* The traditional 32-bit ABI. */ |
2891 | CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ | |
2892 | CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ | |
2893 | CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ | |
2894 | CM_LARGE, /* No assumptions. */ | |
2895 | CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */ | |
6189a572 JH |
2896 | }; |
2897 | ||
5bf0ebab RH |
2898 | extern enum cmodel ix86_cmodel; |
2899 | extern const char *ix86_cmodel_string; | |
2900 | ||
8362f420 JH |
2901 | /* Size of the RED_ZONE area. */ |
2902 | #define RED_ZONE_SIZE 128 | |
2903 | /* Reserved area of the red zone for temporaries. */ | |
2904 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 JH |
2905 | |
2906 | enum asm_dialect { | |
2907 | ASM_ATT, | |
2908 | ASM_INTEL | |
2909 | }; | |
5bf0ebab | 2910 | |
c93e80a5 | 2911 | extern const char *ix86_asm_string; |
80f33d06 | 2912 | extern enum asm_dialect ix86_asm_dialect; |
5bf0ebab RH |
2913 | |
2914 | extern int ix86_regparm; | |
fce5a9f2 | 2915 | extern const char *ix86_regparm_string; |
5bf0ebab | 2916 | |
95899b34 | 2917 | extern unsigned int ix86_preferred_stack_boundary; |
5bf0ebab RH |
2918 | extern const char *ix86_preferred_stack_boundary_string; |
2919 | ||
2920 | extern int ix86_branch_cost; | |
2921 | extern const char *ix86_branch_cost_string; | |
2922 | ||
2923 | extern const char *ix86_debug_arg_string; | |
2924 | extern const char *ix86_debug_addr_string; | |
2925 | ||
2926 | /* Obsoleted by -f options. Remove before 3.2 ships. */ | |
2927 | extern const char *ix86_align_loops_string; | |
2928 | extern const char *ix86_align_jumps_string; | |
2929 | extern const char *ix86_align_funcs_string; | |
2930 | ||
2931 | /* Smallest class containing REGNO. */ | |
2932 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2933 | ||
d9a5f180 GS |
2934 | extern rtx ix86_compare_op0; /* operand 0 for comparisons */ |
2935 | extern rtx ix86_compare_op1; /* operand 1 for comparisons */ | |
22fb740d JH |
2936 | \f |
2937 | /* To properly truncate FP values into integers, we need to set i387 control | |
2938 | word. We can't emit proper mode switching code before reload, as spills | |
2939 | generated by reload may truncate values incorrectly, but we still can avoid | |
2940 | redundant computation of new control word by the mode switching pass. | |
2941 | The fldcw instructions are still emitted redundantly, but this is probably | |
2942 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2943 | the sequence. |
22fb740d JH |
2944 | |
2945 | The machinery is to emit simple truncation instructions and split them | |
2946 | before reload to instructions having USEs of two memory locations that | |
2947 | are filled by this code to old and new control word. | |
fce5a9f2 | 2948 | |
22fb740d JH |
2949 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2950 | needed. */ | |
2951 | ||
22fb740d JH |
2952 | |
2953 | /* Define this macro if the port needs extra instructions inserted | |
2954 | for mode switching in an optimizing compilation. */ | |
2955 | ||
fa1a0d02 | 2956 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) ix86_optimize_mode_switching |
22fb740d JH |
2957 | |
2958 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2959 | initializer for an array of integers. Each initializer element N | |
2960 | refers to an entity that needs mode switching, and specifies the | |
2961 | number of different modes that might need to be set for this | |
2962 | entity. The position of the initializer in the initializer - | |
2963 | starting counting at zero - determines the integer that is used to | |
2964 | refer to the mode-switched entity in question. */ | |
2965 | ||
edeacc14 | 2966 | #define NUM_MODES_FOR_MODE_SWITCHING { I387_CW_ANY } |
22fb740d JH |
2967 | |
2968 | /* ENTITY is an integer specifying a mode-switched entity. If | |
2969 | `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to | |
2970 | return an integer value not larger than the corresponding element | |
2971 | in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY | |
1d1df0df JH |
2972 | must be switched into prior to the execution of INSN. |
2973 | ||
2974 | The mode UNINITIALIZED is used to force re-load of possibly previously | |
2975 | stored control word after function call. The mode ANY specify that | |
2976 | function has no requirements on the control word and make no changes | |
2977 | in the bits we are interested in. */ | |
22fb740d JH |
2978 | |
2979 | #define MODE_NEEDED(ENTITY, I) \ | |
2980 | (GET_CODE (I) == CALL_INSN \ | |
2981 | || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ | |
2982 | || GET_CODE (PATTERN (I)) == ASM_INPUT))\ | |
1d1df0df | 2983 | ? I387_CW_UNINITIALIZED \ |
edeacc14 UB |
2984 | : recog_memoized (I) < 0 \ |
2985 | ? I387_CW_ANY \ | |
2986 | : get_attr_i387_cw (I)) | |
22fb740d JH |
2987 | |
2988 | /* This macro specifies the order in which modes for ENTITY are | |
2989 | processed. 0 is the highest priority. */ | |
2990 | ||
d9a5f180 | 2991 | #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) |
22fb740d JH |
2992 | |
2993 | /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE | |
2994 | is the set of hard registers live at the point where the insn(s) | |
2995 | are to be inserted. */ | |
2996 | ||
2997 | #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
1d1df0df | 2998 | ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ |
22fb740d | 2999 | ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ |
edeacc14 UB |
3000 | assign_386_stack_local (HImode, 2), \ |
3001 | MODE), 0 \ | |
22fb740d | 3002 | : 0) |
0f0138b6 JH |
3003 | \f |
3004 | /* Avoid renaming of stack registers, as doing so in combination with | |
3005 | scheduling just increases amount of live registers at time and in | |
3006 | the turn amount of fxch instructions needed. | |
3007 | ||
43f3a59d | 3008 | ??? Maybe Pentium chips benefits from renaming, someone can try.... */ |
0f0138b6 | 3009 | |
d9a5f180 GS |
3010 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
3011 | ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) | |
22fb740d | 3012 | |
3b3c6a3f | 3013 | \f |
e91f04de CH |
3014 | #define DLL_IMPORT_EXPORT_PREFIX '#' |
3015 | ||
3016 | #define FASTCALL_PREFIX '@' | |
fa1a0d02 JH |
3017 | \f |
3018 | struct machine_function GTY(()) | |
3019 | { | |
3020 | struct stack_local_entry *stack_locals; | |
3021 | const char *some_ld_name; | |
3022 | int save_varrargs_registers; | |
3023 | int accesses_prev_frame; | |
3024 | int optimize_mode_switching; | |
d9b40e8d JH |
3025 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to |
3026 | determine the style used. */ | |
3027 | int use_fast_prologue_epilogue; | |
d7394366 JH |
3028 | /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed |
3029 | for. */ | |
3030 | int use_fast_prologue_epilogue_nregs; | |
fa1a0d02 JH |
3031 | }; |
3032 | ||
3033 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
3034 | #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) | |
3035 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) | |
249e6b63 | 3036 | |
1bc7c5b6 ZW |
3037 | /* Control behavior of x86_file_start. */ |
3038 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
3039 | #define X86_FILE_START_FLTUSED false | |
3040 | ||
c98f8742 JVA |
3041 | /* |
3042 | Local variables: | |
3043 | version-control: t | |
3044 | End: | |
3045 | */ |