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e075ae69 | 1 | /* Subroutines used for code generation on IA-32. |
0ef2e39a | 2 | Copyright (C) 1988, 92, 94-99, 2000 Free Software Foundation, Inc. |
2a2ab3f9 JVA |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
97aadbb9 | 18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
32b5b1aa | 19 | Boston, MA 02111-1307, USA. */ |
2a2ab3f9 | 20 | |
0b6b2900 | 21 | #include <setjmp.h> |
2a2ab3f9 | 22 | #include "config.h" |
bb5177ac | 23 | #include "system.h" |
2a2ab3f9 | 24 | #include "rtl.h" |
6baf1cc8 BS |
25 | #include "tree.h" |
26 | #include "tm_p.h" | |
2a2ab3f9 JVA |
27 | #include "regs.h" |
28 | #include "hard-reg-set.h" | |
29 | #include "real.h" | |
30 | #include "insn-config.h" | |
31 | #include "conditions.h" | |
32 | #include "insn-flags.h" | |
33 | #include "output.h" | |
34 | #include "insn-attr.h" | |
2a2ab3f9 | 35 | #include "flags.h" |
a8ffcc81 | 36 | #include "except.h" |
ecbc4695 | 37 | #include "function.h" |
00c79232 | 38 | #include "recog.h" |
ced8dd8c | 39 | #include "expr.h" |
f103890b | 40 | #include "toplev.h" |
e075ae69 | 41 | #include "basic-block.h" |
1526a060 | 42 | #include "ggc.h" |
2a2ab3f9 | 43 | |
997de79c JVA |
44 | #ifdef EXTRA_CONSTRAINT |
45 | /* If EXTRA_CONSTRAINT is defined, then the 'S' | |
46 | constraint in REG_CLASS_FROM_LETTER will no longer work, and various | |
47 | asm statements that need 'S' for class SIREG will break. */ | |
ad5a6adc RS |
48 | error EXTRA_CONSTRAINT conflicts with S constraint letter |
49 | /* The previous line used to be #error, but some compilers barf | |
50 | even if the conditional was untrue. */ | |
997de79c JVA |
51 | #endif |
52 | ||
8dfe5673 RK |
53 | #ifndef CHECK_STACK_LIMIT |
54 | #define CHECK_STACK_LIMIT -1 | |
55 | #endif | |
56 | ||
32b5b1aa SC |
57 | /* Processor costs (relative to an add) */ |
58 | struct processor_costs i386_cost = { /* 386 specific costs */ | |
e9a25f70 | 59 | 1, /* cost of an add instruction */ |
32b5b1aa SC |
60 | 1, /* cost of a lea instruction */ |
61 | 3, /* variable shift costs */ | |
62 | 2, /* constant shift costs */ | |
63 | 6, /* cost of starting a multiply */ | |
64 | 1, /* cost of multiply per each bit set */ | |
e075ae69 | 65 | 23, /* cost of a divide/mod */ |
96e7ae40 | 66 | 15, /* "large" insn */ |
e2e52e1b | 67 | 3, /* MOVE_RATIO */ |
7c6b971d | 68 | 4, /* cost for loading QImode using movzbl */ |
96e7ae40 JH |
69 | {2, 4, 2}, /* cost of loading integer registers |
70 | in QImode, HImode and SImode. | |
71 | Relative to reg-reg move (2). */ | |
72 | {2, 4, 2}, /* cost of storing integer registers */ | |
73 | 2, /* cost of reg,reg fld/fst */ | |
74 | {8, 8, 8}, /* cost of loading fp registers | |
75 | in SFmode, DFmode and XFmode */ | |
76 | {8, 8, 8} /* cost of loading integer registers */ | |
32b5b1aa SC |
77 | }; |
78 | ||
79 | struct processor_costs i486_cost = { /* 486 specific costs */ | |
80 | 1, /* cost of an add instruction */ | |
81 | 1, /* cost of a lea instruction */ | |
82 | 3, /* variable shift costs */ | |
83 | 2, /* constant shift costs */ | |
84 | 12, /* cost of starting a multiply */ | |
85 | 1, /* cost of multiply per each bit set */ | |
e075ae69 | 86 | 40, /* cost of a divide/mod */ |
96e7ae40 | 87 | 15, /* "large" insn */ |
e2e52e1b | 88 | 3, /* MOVE_RATIO */ |
7c6b971d | 89 | 4, /* cost for loading QImode using movzbl */ |
96e7ae40 JH |
90 | {2, 4, 2}, /* cost of loading integer registers |
91 | in QImode, HImode and SImode. | |
92 | Relative to reg-reg move (2). */ | |
93 | {2, 4, 2}, /* cost of storing integer registers */ | |
94 | 2, /* cost of reg,reg fld/fst */ | |
95 | {8, 8, 8}, /* cost of loading fp registers | |
96 | in SFmode, DFmode and XFmode */ | |
97 | {8, 8, 8} /* cost of loading integer registers */ | |
32b5b1aa SC |
98 | }; |
99 | ||
e5cb57e8 | 100 | struct processor_costs pentium_cost = { |
32b5b1aa SC |
101 | 1, /* cost of an add instruction */ |
102 | 1, /* cost of a lea instruction */ | |
856b07a1 | 103 | 4, /* variable shift costs */ |
e5cb57e8 | 104 | 1, /* constant shift costs */ |
856b07a1 SC |
105 | 11, /* cost of starting a multiply */ |
106 | 0, /* cost of multiply per each bit set */ | |
e075ae69 | 107 | 25, /* cost of a divide/mod */ |
96e7ae40 | 108 | 8, /* "large" insn */ |
e2e52e1b | 109 | 6, /* MOVE_RATIO */ |
7c6b971d | 110 | 6, /* cost for loading QImode using movzbl */ |
96e7ae40 JH |
111 | {2, 4, 2}, /* cost of loading integer registers |
112 | in QImode, HImode and SImode. | |
113 | Relative to reg-reg move (2). */ | |
114 | {2, 4, 2}, /* cost of storing integer registers */ | |
115 | 2, /* cost of reg,reg fld/fst */ | |
116 | {2, 2, 6}, /* cost of loading fp registers | |
117 | in SFmode, DFmode and XFmode */ | |
118 | {4, 4, 6} /* cost of loading integer registers */ | |
32b5b1aa SC |
119 | }; |
120 | ||
856b07a1 SC |
121 | struct processor_costs pentiumpro_cost = { |
122 | 1, /* cost of an add instruction */ | |
123 | 1, /* cost of a lea instruction */ | |
e075ae69 | 124 | 1, /* variable shift costs */ |
856b07a1 | 125 | 1, /* constant shift costs */ |
e075ae69 | 126 | 1, /* cost of starting a multiply */ |
856b07a1 | 127 | 0, /* cost of multiply per each bit set */ |
e075ae69 | 128 | 17, /* cost of a divide/mod */ |
96e7ae40 | 129 | 8, /* "large" insn */ |
e2e52e1b | 130 | 6, /* MOVE_RATIO */ |
7c6b971d | 131 | 2, /* cost for loading QImode using movzbl */ |
96e7ae40 JH |
132 | {4, 4, 4}, /* cost of loading integer registers |
133 | in QImode, HImode and SImode. | |
134 | Relative to reg-reg move (2). */ | |
135 | {2, 2, 2}, /* cost of storing integer registers */ | |
136 | 2, /* cost of reg,reg fld/fst */ | |
137 | {2, 2, 6}, /* cost of loading fp registers | |
138 | in SFmode, DFmode and XFmode */ | |
139 | {4, 4, 6} /* cost of loading integer registers */ | |
856b07a1 SC |
140 | }; |
141 | ||
a269a03c JC |
142 | struct processor_costs k6_cost = { |
143 | 1, /* cost of an add instruction */ | |
e075ae69 | 144 | 2, /* cost of a lea instruction */ |
a269a03c JC |
145 | 1, /* variable shift costs */ |
146 | 1, /* constant shift costs */ | |
73fe76e4 | 147 | 3, /* cost of starting a multiply */ |
a269a03c | 148 | 0, /* cost of multiply per each bit set */ |
e075ae69 | 149 | 18, /* cost of a divide/mod */ |
96e7ae40 | 150 | 8, /* "large" insn */ |
e2e52e1b | 151 | 4, /* MOVE_RATIO */ |
7c6b971d | 152 | 3, /* cost for loading QImode using movzbl */ |
96e7ae40 JH |
153 | {4, 5, 4}, /* cost of loading integer registers |
154 | in QImode, HImode and SImode. | |
155 | Relative to reg-reg move (2). */ | |
156 | {2, 3, 2}, /* cost of storing integer registers */ | |
157 | 4, /* cost of reg,reg fld/fst */ | |
158 | {6, 6, 6}, /* cost of loading fp registers | |
159 | in SFmode, DFmode and XFmode */ | |
160 | {4, 4, 4} /* cost of loading integer registers */ | |
a269a03c JC |
161 | }; |
162 | ||
309ada50 JH |
163 | struct processor_costs athlon_cost = { |
164 | 1, /* cost of an add instruction */ | |
165 | 1, /* cost of a lea instruction */ | |
166 | 1, /* variable shift costs */ | |
167 | 1, /* constant shift costs */ | |
168 | 5, /* cost of starting a multiply */ | |
169 | 0, /* cost of multiply per each bit set */ | |
170 | 19, /* cost of a divide/mod */ | |
171 | 8, /* "large" insn */ | |
e2e52e1b | 172 | 9, /* MOVE_RATIO */ |
309ada50 JH |
173 | 4, /* cost for loading QImode using movzbl */ |
174 | {4, 5, 4}, /* cost of loading integer registers | |
175 | in QImode, HImode and SImode. | |
176 | Relative to reg-reg move (2). */ | |
177 | {2, 3, 2}, /* cost of storing integer registers */ | |
178 | 4, /* cost of reg,reg fld/fst */ | |
179 | {6, 6, 6}, /* cost of loading fp registers | |
180 | in SFmode, DFmode and XFmode */ | |
181 | {4, 4, 4} /* cost of loading integer registers */ | |
182 | }; | |
183 | ||
32b5b1aa SC |
184 | struct processor_costs *ix86_cost = &pentium_cost; |
185 | ||
a269a03c JC |
186 | /* Processor feature/optimization bitmasks. */ |
187 | #define m_386 (1<<PROCESSOR_I386) | |
188 | #define m_486 (1<<PROCESSOR_I486) | |
189 | #define m_PENT (1<<PROCESSOR_PENTIUM) | |
190 | #define m_PPRO (1<<PROCESSOR_PENTIUMPRO) | |
191 | #define m_K6 (1<<PROCESSOR_K6) | |
309ada50 | 192 | #define m_ATHLON (1<<PROCESSOR_ATHLON) |
a269a03c | 193 | |
309ada50 JH |
194 | const int x86_use_leave = m_386 | m_K6 | m_ATHLON; |
195 | const int x86_push_memory = m_386 | m_K6 | m_ATHLON; | |
a269a03c | 196 | const int x86_zero_extend_with_and = m_486 | m_PENT; |
309ada50 | 197 | const int x86_movx = m_ATHLON /* m_386 | m_PPRO | m_K6 */; |
e075ae69 | 198 | const int x86_double_with_add = ~m_386; |
a269a03c | 199 | const int x86_use_bit_test = m_386; |
e2e52e1b | 200 | const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON | m_K6; |
a269a03c JC |
201 | const int x86_use_q_reg = m_PENT | m_PPRO | m_K6; |
202 | const int x86_use_any_reg = m_486; | |
309ada50 JH |
203 | const int x86_cmove = m_PPRO | m_ATHLON; |
204 | const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON; | |
205 | const int x86_use_sahf = m_PPRO | m_K6 | m_ATHLON; | |
e075ae69 RH |
206 | const int x86_partial_reg_stall = m_PPRO; |
207 | const int x86_use_loop = m_K6; | |
309ada50 | 208 | const int x86_use_fiop = ~(m_PPRO | m_ATHLON | m_PENT); |
e075ae69 RH |
209 | const int x86_use_mov0 = m_K6; |
210 | const int x86_use_cltd = ~(m_PENT | m_K6); | |
211 | const int x86_read_modify_write = ~m_PENT; | |
212 | const int x86_read_modify = ~(m_PENT | m_PPRO); | |
213 | const int x86_split_long_moves = m_PPRO; | |
e9e80858 | 214 | const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486; |
f90800f8 | 215 | const int x86_single_stringop = m_386; |
a269a03c | 216 | |
564d80f4 | 217 | #define AT_BP(mode) (gen_rtx_MEM ((mode), hard_frame_pointer_rtx)) |
2a2ab3f9 | 218 | |
e075ae69 RH |
219 | const char * const hi_reg_name[] = HI_REGISTER_NAMES; |
220 | const char * const qi_reg_name[] = QI_REGISTER_NAMES; | |
221 | const char * const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES; | |
4c0d89b5 RS |
222 | |
223 | /* Array of the smallest class containing reg number REGNO, indexed by | |
224 | REGNO. Used by REGNO_REG_CLASS in i386.h. */ | |
225 | ||
e075ae69 | 226 | enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] = |
4c0d89b5 RS |
227 | { |
228 | /* ax, dx, cx, bx */ | |
ab408a86 | 229 | AREG, DREG, CREG, BREG, |
4c0d89b5 | 230 | /* si, di, bp, sp */ |
e075ae69 | 231 | SIREG, DIREG, NON_Q_REGS, NON_Q_REGS, |
4c0d89b5 RS |
232 | /* FP registers */ |
233 | FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS, | |
79325812 | 234 | FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, |
4c0d89b5 | 235 | /* arg pointer */ |
83774849 | 236 | NON_Q_REGS, |
564d80f4 JH |
237 | /* flags, fpsr, dirflag, frame */ |
238 | NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS | |
4c0d89b5 | 239 | }; |
c572e5ba | 240 | |
83774849 RH |
241 | /* The "default" register map. */ |
242 | ||
243 | int const dbx_register_map[FIRST_PSEUDO_REGISTER] = | |
244 | { | |
245 | 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */ | |
246 | 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */ | |
247 | -1, -1, -1, -1, /* arg, flags, fpsr, dir */ | |
248 | }; | |
249 | ||
250 | /* Define the register numbers to be used in Dwarf debugging information. | |
251 | The SVR4 reference port C compiler uses the following register numbers | |
252 | in its Dwarf output code: | |
253 | 0 for %eax (gcc regno = 0) | |
254 | 1 for %ecx (gcc regno = 2) | |
255 | 2 for %edx (gcc regno = 1) | |
256 | 3 for %ebx (gcc regno = 3) | |
257 | 4 for %esp (gcc regno = 7) | |
258 | 5 for %ebp (gcc regno = 6) | |
259 | 6 for %esi (gcc regno = 4) | |
260 | 7 for %edi (gcc regno = 5) | |
261 | The following three DWARF register numbers are never generated by | |
262 | the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4 | |
263 | believes these numbers have these meanings. | |
264 | 8 for %eip (no gcc equivalent) | |
265 | 9 for %eflags (gcc regno = 17) | |
266 | 10 for %trapno (no gcc equivalent) | |
267 | It is not at all clear how we should number the FP stack registers | |
268 | for the x86 architecture. If the version of SDB on x86/svr4 were | |
269 | a bit less brain dead with respect to floating-point then we would | |
270 | have a precedent to follow with respect to DWARF register numbers | |
271 | for x86 FP registers, but the SDB on x86/svr4 is so completely | |
272 | broken with respect to FP registers that it is hardly worth thinking | |
273 | of it as something to strive for compatibility with. | |
274 | The version of x86/svr4 SDB I have at the moment does (partially) | |
275 | seem to believe that DWARF register number 11 is associated with | |
276 | the x86 register %st(0), but that's about all. Higher DWARF | |
277 | register numbers don't seem to be associated with anything in | |
278 | particular, and even for DWARF regno 11, SDB only seems to under- | |
279 | stand that it should say that a variable lives in %st(0) (when | |
280 | asked via an `=' command) if we said it was in DWARF regno 11, | |
281 | but SDB still prints garbage when asked for the value of the | |
282 | variable in question (via a `/' command). | |
283 | (Also note that the labels SDB prints for various FP stack regs | |
284 | when doing an `x' command are all wrong.) | |
285 | Note that these problems generally don't affect the native SVR4 | |
286 | C compiler because it doesn't allow the use of -O with -g and | |
287 | because when it is *not* optimizing, it allocates a memory | |
288 | location for each floating-point variable, and the memory | |
289 | location is what gets described in the DWARF AT_location | |
290 | attribute for the variable in question. | |
291 | Regardless of the severe mental illness of the x86/svr4 SDB, we | |
292 | do something sensible here and we use the following DWARF | |
293 | register numbers. Note that these are all stack-top-relative | |
294 | numbers. | |
295 | 11 for %st(0) (gcc regno = 8) | |
296 | 12 for %st(1) (gcc regno = 9) | |
297 | 13 for %st(2) (gcc regno = 10) | |
298 | 14 for %st(3) (gcc regno = 11) | |
299 | 15 for %st(4) (gcc regno = 12) | |
300 | 16 for %st(5) (gcc regno = 13) | |
301 | 17 for %st(6) (gcc regno = 14) | |
302 | 18 for %st(7) (gcc regno = 15) | |
303 | */ | |
304 | int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] = | |
305 | { | |
306 | 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */ | |
307 | 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */ | |
308 | -1, 9, -1, -1, /* arg, flags, fpsr, dir */ | |
309 | }; | |
310 | ||
311 | ||
312 | ||
c572e5ba JVA |
313 | /* Test and compare insns in i386.md store the information needed to |
314 | generate branch and scc insns here. */ | |
315 | ||
e075ae69 RH |
316 | struct rtx_def *ix86_compare_op0 = NULL_RTX; |
317 | struct rtx_def *ix86_compare_op1 = NULL_RTX; | |
f5316dfe | 318 | |
36edd3cc BS |
319 | #define MAX_386_STACK_LOCALS 2 |
320 | ||
321 | /* Define the structure for the machine field in struct function. */ | |
322 | struct machine_function | |
323 | { | |
324 | rtx stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; | |
325 | }; | |
326 | ||
01d939e8 | 327 | #define ix86_stack_locals (cfun->machine->stack_locals) |
36edd3cc | 328 | |
c8c5cb99 | 329 | /* which cpu are we scheduling for */ |
e42ea7f9 | 330 | enum processor_type ix86_cpu; |
c8c5cb99 SC |
331 | |
332 | /* which instruction set architecture to use. */ | |
c942177e | 333 | int ix86_arch; |
c8c5cb99 SC |
334 | |
335 | /* Strings to hold which cpu and instruction set architecture to use. */ | |
9c23aa47 ZW |
336 | const char *ix86_cpu_string; /* for -mcpu=<xxx> */ |
337 | const char *ix86_arch_string; /* for -march=<xxx> */ | |
c8c5cb99 | 338 | |
f5316dfe | 339 | /* Register allocation order */ |
e075ae69 | 340 | const char *ix86_reg_alloc_order; |
f5316dfe MM |
341 | static char regs_allocated[FIRST_PSEUDO_REGISTER]; |
342 | ||
b08de47e | 343 | /* # of registers to use to pass arguments. */ |
e075ae69 | 344 | const char *ix86_regparm_string; |
e9a25f70 | 345 | |
e075ae69 RH |
346 | /* ix86_regparm_string as a number */ |
347 | int ix86_regparm; | |
e9a25f70 JL |
348 | |
349 | /* Alignment to use for loops and jumps: */ | |
350 | ||
351 | /* Power of two alignment for loops. */ | |
e075ae69 | 352 | const char *ix86_align_loops_string; |
e9a25f70 JL |
353 | |
354 | /* Power of two alignment for non-loop jumps. */ | |
e075ae69 | 355 | const char *ix86_align_jumps_string; |
e9a25f70 | 356 | |
3af4bd89 | 357 | /* Power of two alignment for stack boundary in bytes. */ |
e075ae69 | 358 | const char *ix86_preferred_stack_boundary_string; |
3af4bd89 JH |
359 | |
360 | /* Preferred alignment for stack boundary in bits. */ | |
e075ae69 | 361 | int ix86_preferred_stack_boundary; |
3af4bd89 | 362 | |
e9a25f70 | 363 | /* Values 1-5: see jump.c */ |
e075ae69 RH |
364 | int ix86_branch_cost; |
365 | const char *ix86_branch_cost_string; | |
e9a25f70 JL |
366 | |
367 | /* Power of two alignment for functions. */ | |
e075ae69 RH |
368 | int ix86_align_funcs; |
369 | const char *ix86_align_funcs_string; | |
b08de47e | 370 | |
e9a25f70 | 371 | /* Power of two alignment for loops. */ |
e075ae69 | 372 | int ix86_align_loops; |
b08de47e | 373 | |
e9a25f70 | 374 | /* Power of two alignment for non-loop jumps. */ |
e075ae69 RH |
375 | int ix86_align_jumps; |
376 | \f | |
f6da8bc3 KG |
377 | static void output_pic_addr_const PARAMS ((FILE *, rtx, int)); |
378 | static void put_condition_code PARAMS ((enum rtx_code, enum machine_mode, | |
e075ae69 | 379 | int, int, FILE *)); |
f6da8bc3 KG |
380 | static enum rtx_code unsigned_comparison PARAMS ((enum rtx_code code)); |
381 | static rtx ix86_expand_int_compare PARAMS ((enum rtx_code, rtx, rtx)); | |
382 | static rtx ix86_expand_fp_compare PARAMS ((enum rtx_code, rtx, rtx, int)); | |
383 | static rtx ix86_expand_compare PARAMS ((enum rtx_code, int)); | |
384 | static rtx gen_push PARAMS ((rtx)); | |
385 | static int memory_address_length PARAMS ((rtx addr)); | |
386 | static int ix86_flags_dependant PARAMS ((rtx, rtx, enum attr_type)); | |
387 | static int ix86_agi_dependant PARAMS ((rtx, rtx, enum attr_type)); | |
388 | static int ix86_safe_length PARAMS ((rtx)); | |
389 | static enum attr_memory ix86_safe_memory PARAMS ((rtx)); | |
390 | static enum attr_pent_pair ix86_safe_pent_pair PARAMS ((rtx)); | |
391 | static enum attr_ppro_uops ix86_safe_ppro_uops PARAMS ((rtx)); | |
392 | static void ix86_dump_ppro_packet PARAMS ((FILE *)); | |
393 | static void ix86_reorder_insn PARAMS ((rtx *, rtx *)); | |
394 | static rtx * ix86_pent_find_pair PARAMS ((rtx *, rtx *, enum attr_pent_pair, | |
e075ae69 | 395 | rtx)); |
f6da8bc3 KG |
396 | static void ix86_init_machine_status PARAMS ((struct function *)); |
397 | static void ix86_mark_machine_status PARAMS ((struct function *)); | |
398 | static void ix86_split_to_parts PARAMS ((rtx, rtx *, enum machine_mode)); | |
399 | static int ix86_safe_length_prefix PARAMS ((rtx)); | |
564d80f4 JH |
400 | static HOST_WIDE_INT ix86_compute_frame_size PARAMS((HOST_WIDE_INT, |
401 | int *, int *, int *)); | |
0903fcab JH |
402 | static int ix86_nsaved_regs PARAMS((void)); |
403 | static void ix86_emit_save_regs PARAMS((void)); | |
da2d1d3a | 404 | static void ix86_emit_restore_regs_using_mov PARAMS ((rtx, int)); |
0903fcab | 405 | static void ix86_emit_epilogue_esp_adjustment PARAMS((int)); |
c6991660 KG |
406 | static void ix86_sched_reorder_pentium PARAMS((rtx *, rtx *)); |
407 | static void ix86_sched_reorder_ppro PARAMS((rtx *, rtx *)); | |
e075ae69 RH |
408 | |
409 | struct ix86_address | |
410 | { | |
411 | rtx base, index, disp; | |
412 | HOST_WIDE_INT scale; | |
413 | }; | |
b08de47e | 414 | |
e075ae69 RH |
415 | static int ix86_decompose_address PARAMS ((rtx, struct ix86_address *)); |
416 | \f | |
f5316dfe MM |
417 | /* Sometimes certain combinations of command options do not make |
418 | sense on a particular target machine. You can define a macro | |
419 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
420 | defined, is executed once just after all the command options have | |
421 | been parsed. | |
422 | ||
423 | Don't use this macro to turn on various extra optimizations for | |
424 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
425 | ||
426 | void | |
427 | override_options () | |
428 | { | |
e075ae69 RH |
429 | /* Comes from final.c -- no real reason to change it. */ |
430 | #define MAX_CODE_ALIGN 16 | |
f5316dfe | 431 | |
c8c5cb99 SC |
432 | static struct ptt |
433 | { | |
e075ae69 RH |
434 | struct processor_costs *cost; /* Processor costs */ |
435 | int target_enable; /* Target flags to enable. */ | |
436 | int target_disable; /* Target flags to disable. */ | |
437 | int align_loop; /* Default alignments. */ | |
438 | int align_jump; | |
439 | int align_func; | |
440 | int branch_cost; | |
441 | } | |
442 | const processor_target_table[PROCESSOR_max] = | |
443 | { | |
444 | {&i386_cost, 0, 0, 2, 2, 2, 1}, | |
445 | {&i486_cost, 0, 0, 4, 4, 4, 1}, | |
446 | {&pentium_cost, 0, 0, -4, -4, -4, 1}, | |
447 | {&pentiumpro_cost, 0, 0, 4, -4, 4, 1}, | |
309ada50 JH |
448 | {&k6_cost, 0, 0, -5, -5, 4, 1}, |
449 | {&athlon_cost, 0, 0, 4, -4, 4, 1} | |
e075ae69 RH |
450 | }; |
451 | ||
452 | static struct pta | |
453 | { | |
69ddee61 | 454 | const char *name; /* processor name or nickname. */ |
e075ae69 RH |
455 | enum processor_type processor; |
456 | } | |
457 | const processor_alias_table[] = | |
458 | { | |
459 | {"i386", PROCESSOR_I386}, | |
460 | {"i486", PROCESSOR_I486}, | |
461 | {"i586", PROCESSOR_PENTIUM}, | |
462 | {"pentium", PROCESSOR_PENTIUM}, | |
463 | {"i686", PROCESSOR_PENTIUMPRO}, | |
464 | {"pentiumpro", PROCESSOR_PENTIUMPRO}, | |
e075ae69 | 465 | {"k6", PROCESSOR_K6}, |
309ada50 | 466 | {"athlon", PROCESSOR_ATHLON}, |
3af4bd89 | 467 | }; |
c8c5cb99 | 468 | |
e075ae69 | 469 | int const pta_size = sizeof(processor_alias_table)/sizeof(struct pta); |
c8c5cb99 | 470 | |
f5316dfe MM |
471 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
472 | SUBTARGET_OVERRIDE_OPTIONS; | |
473 | #endif | |
474 | ||
5a6ee819 | 475 | ix86_arch = PROCESSOR_I386; |
e075ae69 RH |
476 | ix86_cpu = (enum processor_type) TARGET_CPU_DEFAULT; |
477 | ||
478 | if (ix86_arch_string != 0) | |
479 | { | |
480 | int i; | |
481 | for (i = 0; i < pta_size; i++) | |
482 | if (! strcmp (ix86_arch_string, processor_alias_table[i].name)) | |
483 | { | |
484 | ix86_arch = processor_alias_table[i].processor; | |
485 | /* Default cpu tuning to the architecture. */ | |
486 | ix86_cpu = ix86_arch; | |
487 | break; | |
488 | } | |
489 | if (i == pta_size) | |
490 | error ("bad value (%s) for -march= switch", ix86_arch_string); | |
491 | } | |
492 | ||
493 | if (ix86_cpu_string != 0) | |
494 | { | |
495 | int i; | |
496 | for (i = 0; i < pta_size; i++) | |
497 | if (! strcmp (ix86_cpu_string, processor_alias_table[i].name)) | |
498 | { | |
499 | ix86_cpu = processor_alias_table[i].processor; | |
500 | break; | |
501 | } | |
502 | if (i == pta_size) | |
503 | error ("bad value (%s) for -mcpu= switch", ix86_cpu_string); | |
504 | } | |
505 | ||
506 | ix86_cost = processor_target_table[ix86_cpu].cost; | |
507 | target_flags |= processor_target_table[ix86_cpu].target_enable; | |
508 | target_flags &= ~processor_target_table[ix86_cpu].target_disable; | |
509 | ||
36edd3cc BS |
510 | /* Arrange to set up i386_stack_locals for all functions. */ |
511 | init_machine_status = ix86_init_machine_status; | |
1526a060 | 512 | mark_machine_status = ix86_mark_machine_status; |
36edd3cc | 513 | |
e9a25f70 | 514 | /* Validate registers in register allocation order. */ |
e075ae69 | 515 | if (ix86_reg_alloc_order) |
f5316dfe | 516 | { |
e075ae69 RH |
517 | int i, ch; |
518 | for (i = 0; (ch = ix86_reg_alloc_order[i]) != '\0'; i++) | |
f5316dfe | 519 | { |
00c79232 | 520 | int regno = 0; |
79325812 | 521 | |
f5316dfe MM |
522 | switch (ch) |
523 | { | |
524 | case 'a': regno = 0; break; | |
525 | case 'd': regno = 1; break; | |
526 | case 'c': regno = 2; break; | |
527 | case 'b': regno = 3; break; | |
528 | case 'S': regno = 4; break; | |
529 | case 'D': regno = 5; break; | |
530 | case 'B': regno = 6; break; | |
531 | ||
532 | default: fatal ("Register '%c' is unknown", ch); | |
533 | } | |
534 | ||
535 | if (regs_allocated[regno]) | |
e9a25f70 | 536 | fatal ("Register '%c' already specified in allocation order", ch); |
f5316dfe MM |
537 | |
538 | regs_allocated[regno] = 1; | |
539 | } | |
540 | } | |
b08de47e | 541 | |
e9a25f70 | 542 | /* Validate -mregparm= value. */ |
e075ae69 | 543 | if (ix86_regparm_string) |
b08de47e | 544 | { |
e075ae69 RH |
545 | ix86_regparm = atoi (ix86_regparm_string); |
546 | if (ix86_regparm < 0 || ix86_regparm > REGPARM_MAX) | |
e9a25f70 | 547 | fatal ("-mregparm=%d is not between 0 and %d", |
e075ae69 | 548 | ix86_regparm, REGPARM_MAX); |
b08de47e MM |
549 | } |
550 | ||
e9a25f70 | 551 | /* Validate -malign-loops= value, or provide default. */ |
e075ae69 RH |
552 | ix86_align_loops = processor_target_table[ix86_cpu].align_loop; |
553 | if (ix86_align_loops_string) | |
b08de47e | 554 | { |
e075ae69 RH |
555 | ix86_align_loops = atoi (ix86_align_loops_string); |
556 | if (ix86_align_loops < 0 || ix86_align_loops > MAX_CODE_ALIGN) | |
b08de47e | 557 | fatal ("-malign-loops=%d is not between 0 and %d", |
e075ae69 | 558 | ix86_align_loops, MAX_CODE_ALIGN); |
b08de47e | 559 | } |
3af4bd89 JH |
560 | |
561 | /* Validate -malign-jumps= value, or provide default. */ | |
e075ae69 RH |
562 | ix86_align_jumps = processor_target_table[ix86_cpu].align_jump; |
563 | if (ix86_align_jumps_string) | |
b08de47e | 564 | { |
e075ae69 RH |
565 | ix86_align_jumps = atoi (ix86_align_jumps_string); |
566 | if (ix86_align_jumps < 0 || ix86_align_jumps > MAX_CODE_ALIGN) | |
b08de47e | 567 | fatal ("-malign-jumps=%d is not between 0 and %d", |
e075ae69 | 568 | ix86_align_jumps, MAX_CODE_ALIGN); |
b08de47e | 569 | } |
b08de47e | 570 | |
e9a25f70 | 571 | /* Validate -malign-functions= value, or provide default. */ |
e075ae69 RH |
572 | ix86_align_funcs = processor_target_table[ix86_cpu].align_func; |
573 | if (ix86_align_funcs_string) | |
b08de47e | 574 | { |
e075ae69 RH |
575 | ix86_align_funcs = atoi (ix86_align_funcs_string); |
576 | if (ix86_align_funcs < 0 || ix86_align_funcs > MAX_CODE_ALIGN) | |
b08de47e | 577 | fatal ("-malign-functions=%d is not between 0 and %d", |
e075ae69 | 578 | ix86_align_funcs, MAX_CODE_ALIGN); |
b08de47e | 579 | } |
3af4bd89 | 580 | |
e4c0478d | 581 | /* Validate -mpreferred-stack-boundary= value, or provide default. |
3af4bd89 | 582 | The default of 128 bits is for Pentium III's SSE __m128. */ |
e075ae69 RH |
583 | ix86_preferred_stack_boundary = 128; |
584 | if (ix86_preferred_stack_boundary_string) | |
3af4bd89 | 585 | { |
e075ae69 | 586 | int i = atoi (ix86_preferred_stack_boundary_string); |
3af4bd89 | 587 | if (i < 2 || i > 31) |
e4c0478d | 588 | fatal ("-mpreferred-stack-boundary=%d is not between 2 and 31", i); |
e075ae69 | 589 | ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT; |
3af4bd89 | 590 | } |
77a989d1 | 591 | |
e9a25f70 | 592 | /* Validate -mbranch-cost= value, or provide default. */ |
e075ae69 RH |
593 | ix86_branch_cost = processor_target_table[ix86_cpu].branch_cost; |
594 | if (ix86_branch_cost_string) | |
804a8ee0 | 595 | { |
e075ae69 RH |
596 | ix86_branch_cost = atoi (ix86_branch_cost_string); |
597 | if (ix86_branch_cost < 0 || ix86_branch_cost > 5) | |
598 | fatal ("-mbranch-cost=%d is not between 0 and 5", | |
599 | ix86_branch_cost); | |
804a8ee0 | 600 | } |
804a8ee0 | 601 | |
e9a25f70 JL |
602 | /* Keep nonleaf frame pointers. */ |
603 | if (TARGET_OMIT_LEAF_FRAME_POINTER) | |
77a989d1 | 604 | flag_omit_frame_pointer = 1; |
e075ae69 RH |
605 | |
606 | /* If we're doing fast math, we don't care about comparison order | |
607 | wrt NaNs. This lets us use a shorter comparison sequence. */ | |
608 | if (flag_fast_math) | |
609 | target_flags &= ~MASK_IEEE_FP; | |
610 | ||
611 | /* If we're planning on using `loop', use it. */ | |
612 | if (TARGET_USE_LOOP && optimize) | |
613 | flag_branch_on_count_reg = 1; | |
f5316dfe MM |
614 | } |
615 | \f | |
616 | /* A C statement (sans semicolon) to choose the order in which to | |
617 | allocate hard registers for pseudo-registers local to a basic | |
618 | block. | |
619 | ||
620 | Store the desired register order in the array `reg_alloc_order'. | |
621 | Element 0 should be the register to allocate first; element 1, the | |
622 | next register; and so on. | |
623 | ||
624 | The macro body should not assume anything about the contents of | |
625 | `reg_alloc_order' before execution of the macro. | |
626 | ||
627 | On most machines, it is not necessary to define this macro. */ | |
628 | ||
629 | void | |
630 | order_regs_for_local_alloc () | |
631 | { | |
00c79232 | 632 | int i, ch, order; |
f5316dfe | 633 | |
e9a25f70 JL |
634 | /* User specified the register allocation order. */ |
635 | ||
e075ae69 | 636 | if (ix86_reg_alloc_order) |
f5316dfe | 637 | { |
e075ae69 | 638 | for (i = order = 0; (ch = ix86_reg_alloc_order[i]) != '\0'; i++) |
f5316dfe | 639 | { |
00c79232 | 640 | int regno = 0; |
79325812 | 641 | |
f5316dfe MM |
642 | switch (ch) |
643 | { | |
644 | case 'a': regno = 0; break; | |
645 | case 'd': regno = 1; break; | |
646 | case 'c': regno = 2; break; | |
647 | case 'b': regno = 3; break; | |
648 | case 'S': regno = 4; break; | |
649 | case 'D': regno = 5; break; | |
650 | case 'B': regno = 6; break; | |
651 | } | |
652 | ||
653 | reg_alloc_order[order++] = regno; | |
654 | } | |
655 | ||
656 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
657 | { | |
e9a25f70 | 658 | if (! regs_allocated[i]) |
f5316dfe MM |
659 | reg_alloc_order[order++] = i; |
660 | } | |
661 | } | |
662 | ||
e9a25f70 | 663 | /* If user did not specify a register allocation order, use natural order. */ |
f5316dfe MM |
664 | else |
665 | { | |
666 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
667 | reg_alloc_order[i] = i; | |
f5316dfe MM |
668 | } |
669 | } | |
32b5b1aa SC |
670 | \f |
671 | void | |
c6aded7c | 672 | optimization_options (level, size) |
32b5b1aa | 673 | int level; |
bb5177ac | 674 | int size ATTRIBUTE_UNUSED; |
32b5b1aa | 675 | { |
e9a25f70 JL |
676 | /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to |
677 | make the problem with not enough registers even worse. */ | |
32b5b1aa SC |
678 | #ifdef INSN_SCHEDULING |
679 | if (level > 1) | |
680 | flag_schedule_insns = 0; | |
681 | #endif | |
682 | } | |
b08de47e MM |
683 | \f |
684 | /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific | |
685 | attribute for DECL. The attributes in ATTRIBUTES have previously been | |
686 | assigned to DECL. */ | |
687 | ||
688 | int | |
e075ae69 | 689 | ix86_valid_decl_attribute_p (decl, attributes, identifier, args) |
bb5177ac RL |
690 | tree decl ATTRIBUTE_UNUSED; |
691 | tree attributes ATTRIBUTE_UNUSED; | |
692 | tree identifier ATTRIBUTE_UNUSED; | |
693 | tree args ATTRIBUTE_UNUSED; | |
b08de47e MM |
694 | { |
695 | return 0; | |
696 | } | |
697 | ||
698 | /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific | |
699 | attribute for TYPE. The attributes in ATTRIBUTES have previously been | |
700 | assigned to TYPE. */ | |
701 | ||
702 | int | |
e075ae69 | 703 | ix86_valid_type_attribute_p (type, attributes, identifier, args) |
b08de47e | 704 | tree type; |
bb5177ac | 705 | tree attributes ATTRIBUTE_UNUSED; |
b08de47e MM |
706 | tree identifier; |
707 | tree args; | |
708 | { | |
709 | if (TREE_CODE (type) != FUNCTION_TYPE | |
ac478ac0 | 710 | && TREE_CODE (type) != METHOD_TYPE |
b08de47e MM |
711 | && TREE_CODE (type) != FIELD_DECL |
712 | && TREE_CODE (type) != TYPE_DECL) | |
713 | return 0; | |
714 | ||
715 | /* Stdcall attribute says callee is responsible for popping arguments | |
716 | if they are not variable. */ | |
717 | if (is_attribute_p ("stdcall", identifier)) | |
718 | return (args == NULL_TREE); | |
719 | ||
e9a25f70 | 720 | /* Cdecl attribute says the callee is a normal C declaration. */ |
b08de47e MM |
721 | if (is_attribute_p ("cdecl", identifier)) |
722 | return (args == NULL_TREE); | |
723 | ||
724 | /* Regparm attribute specifies how many integer arguments are to be | |
e9a25f70 | 725 | passed in registers. */ |
b08de47e MM |
726 | if (is_attribute_p ("regparm", identifier)) |
727 | { | |
728 | tree cst; | |
729 | ||
e9a25f70 | 730 | if (! args || TREE_CODE (args) != TREE_LIST |
b08de47e MM |
731 | || TREE_CHAIN (args) != NULL_TREE |
732 | || TREE_VALUE (args) == NULL_TREE) | |
733 | return 0; | |
734 | ||
735 | cst = TREE_VALUE (args); | |
736 | if (TREE_CODE (cst) != INTEGER_CST) | |
737 | return 0; | |
738 | ||
739 | if (TREE_INT_CST_HIGH (cst) != 0 | |
740 | || TREE_INT_CST_LOW (cst) < 0 | |
741 | || TREE_INT_CST_LOW (cst) > REGPARM_MAX) | |
742 | return 0; | |
743 | ||
744 | return 1; | |
745 | } | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | /* Return 0 if the attributes for two types are incompatible, 1 if they | |
751 | are compatible, and 2 if they are nearly compatible (which causes a | |
752 | warning to be generated). */ | |
753 | ||
754 | int | |
e075ae69 | 755 | ix86_comp_type_attributes (type1, type2) |
afcfe58c MM |
756 | tree type1; |
757 | tree type2; | |
b08de47e | 758 | { |
afcfe58c | 759 | /* Check for mismatch of non-default calling convention. */ |
69ddee61 | 760 | const char *rtdstr = TARGET_RTD ? "cdecl" : "stdcall"; |
afcfe58c MM |
761 | |
762 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
763 | return 1; | |
764 | ||
765 | /* Check for mismatched return types (cdecl vs stdcall). */ | |
6093f019 RH |
766 | if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1)) |
767 | != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2))) | |
afcfe58c | 768 | return 0; |
b08de47e MM |
769 | return 1; |
770 | } | |
b08de47e MM |
771 | \f |
772 | /* Value is the number of bytes of arguments automatically | |
773 | popped when returning from a subroutine call. | |
774 | FUNDECL is the declaration node of the function (as a tree), | |
775 | FUNTYPE is the data type of the function (as a tree), | |
776 | or for a library call it is an identifier node for the subroutine name. | |
777 | SIZE is the number of bytes of arguments passed on the stack. | |
778 | ||
779 | On the 80386, the RTD insn may be used to pop them if the number | |
780 | of args is fixed, but if the number is variable then the caller | |
781 | must pop them all. RTD can't be used for library calls now | |
782 | because the library is compiled with the Unix compiler. | |
783 | Use of RTD is a selectable option, since it is incompatible with | |
784 | standard Unix calling sequences. If the option is not selected, | |
785 | the caller must always pop the args. | |
786 | ||
787 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
788 | ||
789 | int | |
e075ae69 | 790 | ix86_return_pops_args (fundecl, funtype, size) |
b08de47e MM |
791 | tree fundecl; |
792 | tree funtype; | |
793 | int size; | |
79325812 | 794 | { |
3345ee7d | 795 | int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE); |
b08de47e | 796 | |
e9a25f70 JL |
797 | /* Cdecl functions override -mrtd, and never pop the stack. */ |
798 | if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) { | |
79325812 | 799 | |
e9a25f70 | 800 | /* Stdcall functions will pop the stack if not variable args. */ |
698cdd84 SC |
801 | if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))) |
802 | rtd = 1; | |
79325812 | 803 | |
698cdd84 SC |
804 | if (rtd |
805 | && (TYPE_ARG_TYPES (funtype) == NULL_TREE | |
e9a25f70 JL |
806 | || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype))) |
807 | == void_type_node))) | |
698cdd84 SC |
808 | return size; |
809 | } | |
79325812 | 810 | |
e9a25f70 | 811 | /* Lose any fake structure return argument. */ |
698cdd84 SC |
812 | if (aggregate_value_p (TREE_TYPE (funtype))) |
813 | return GET_MODE_SIZE (Pmode); | |
79325812 | 814 | |
2614aac6 | 815 | return 0; |
b08de47e | 816 | } |
b08de47e MM |
817 | \f |
818 | /* Argument support functions. */ | |
819 | ||
820 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
821 | for a call to a function whose data type is FNTYPE. | |
822 | For a library call, FNTYPE is 0. */ | |
823 | ||
824 | void | |
825 | init_cumulative_args (cum, fntype, libname) | |
e9a25f70 | 826 | CUMULATIVE_ARGS *cum; /* Argument info to initialize */ |
b08de47e MM |
827 | tree fntype; /* tree ptr for function decl */ |
828 | rtx libname; /* SYMBOL_REF of library name or 0 */ | |
829 | { | |
830 | static CUMULATIVE_ARGS zero_cum; | |
831 | tree param, next_param; | |
832 | ||
833 | if (TARGET_DEBUG_ARG) | |
834 | { | |
835 | fprintf (stderr, "\ninit_cumulative_args ("); | |
836 | if (fntype) | |
e9a25f70 JL |
837 | fprintf (stderr, "fntype code = %s, ret code = %s", |
838 | tree_code_name[(int) TREE_CODE (fntype)], | |
839 | tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]); | |
b08de47e MM |
840 | else |
841 | fprintf (stderr, "no fntype"); | |
842 | ||
843 | if (libname) | |
844 | fprintf (stderr, ", libname = %s", XSTR (libname, 0)); | |
845 | } | |
846 | ||
847 | *cum = zero_cum; | |
848 | ||
849 | /* Set up the number of registers to use for passing arguments. */ | |
e075ae69 | 850 | cum->nregs = ix86_regparm; |
b08de47e MM |
851 | if (fntype) |
852 | { | |
853 | tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype)); | |
e9a25f70 | 854 | |
b08de47e MM |
855 | if (attr) |
856 | cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr))); | |
857 | } | |
858 | ||
859 | /* Determine if this function has variable arguments. This is | |
860 | indicated by the last argument being 'void_type_mode' if there | |
861 | are no variable arguments. If there are variable arguments, then | |
862 | we won't pass anything in registers */ | |
863 | ||
864 | if (cum->nregs) | |
865 | { | |
866 | for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0; | |
e9a25f70 | 867 | param != 0; param = next_param) |
b08de47e MM |
868 | { |
869 | next_param = TREE_CHAIN (param); | |
e9a25f70 | 870 | if (next_param == 0 && TREE_VALUE (param) != void_type_node) |
b08de47e MM |
871 | cum->nregs = 0; |
872 | } | |
873 | } | |
874 | ||
875 | if (TARGET_DEBUG_ARG) | |
876 | fprintf (stderr, ", nregs=%d )\n", cum->nregs); | |
877 | ||
878 | return; | |
879 | } | |
880 | ||
881 | /* Update the data in CUM to advance over an argument | |
882 | of mode MODE and data type TYPE. | |
883 | (TYPE is null for libcalls where that information may not be available.) */ | |
884 | ||
885 | void | |
886 | function_arg_advance (cum, mode, type, named) | |
887 | CUMULATIVE_ARGS *cum; /* current arg information */ | |
888 | enum machine_mode mode; /* current arg mode */ | |
889 | tree type; /* type of the argument or 0 if lib support */ | |
890 | int named; /* whether or not the argument was named */ | |
891 | { | |
e9a25f70 JL |
892 | int bytes |
893 | = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
b08de47e MM |
894 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; |
895 | ||
896 | if (TARGET_DEBUG_ARG) | |
897 | fprintf (stderr, | |
e9a25f70 | 898 | "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n", |
b08de47e MM |
899 | words, cum->words, cum->nregs, GET_MODE_NAME (mode), named); |
900 | ||
901 | cum->words += words; | |
902 | cum->nregs -= words; | |
903 | cum->regno += words; | |
904 | ||
905 | if (cum->nregs <= 0) | |
906 | { | |
907 | cum->nregs = 0; | |
908 | cum->regno = 0; | |
909 | } | |
910 | ||
911 | return; | |
912 | } | |
913 | ||
914 | /* Define where to put the arguments to a function. | |
915 | Value is zero to push the argument on the stack, | |
916 | or a hard register in which to store the argument. | |
917 | ||
918 | MODE is the argument's machine mode. | |
919 | TYPE is the data type of the argument (as a tree). | |
920 | This is null for libcalls where that information may | |
921 | not be available. | |
922 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
923 | the preceding args and about the function being called. | |
924 | NAMED is nonzero if this argument is a named parameter | |
925 | (otherwise it is an extra parameter matching an ellipsis). */ | |
926 | ||
927 | struct rtx_def * | |
928 | function_arg (cum, mode, type, named) | |
929 | CUMULATIVE_ARGS *cum; /* current arg information */ | |
930 | enum machine_mode mode; /* current arg mode */ | |
931 | tree type; /* type of the argument or 0 if lib support */ | |
932 | int named; /* != 0 for normal args, == 0 for ... args */ | |
933 | { | |
934 | rtx ret = NULL_RTX; | |
e9a25f70 JL |
935 | int bytes |
936 | = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
b08de47e MM |
937 | int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; |
938 | ||
939 | switch (mode) | |
940 | { | |
e9a25f70 JL |
941 | /* For now, pass fp/complex values on the stack. */ |
942 | default: | |
b08de47e MM |
943 | break; |
944 | ||
945 | case BLKmode: | |
946 | case DImode: | |
947 | case SImode: | |
948 | case HImode: | |
949 | case QImode: | |
950 | if (words <= cum->nregs) | |
f64cecad | 951 | ret = gen_rtx_REG (mode, cum->regno); |
b08de47e MM |
952 | break; |
953 | } | |
954 | ||
955 | if (TARGET_DEBUG_ARG) | |
956 | { | |
957 | fprintf (stderr, | |
e9a25f70 | 958 | "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d", |
b08de47e MM |
959 | words, cum->words, cum->nregs, GET_MODE_NAME (mode), named); |
960 | ||
961 | if (ret) | |
962 | fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]); | |
963 | else | |
964 | fprintf (stderr, ", stack"); | |
965 | ||
966 | fprintf (stderr, " )\n"); | |
967 | } | |
968 | ||
969 | return ret; | |
970 | } | |
e075ae69 RH |
971 | \f |
972 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
973 | reference and a constant. */ | |
b08de47e MM |
974 | |
975 | int | |
e075ae69 RH |
976 | symbolic_operand (op, mode) |
977 | register rtx op; | |
978 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
2a2ab3f9 | 979 | { |
e075ae69 | 980 | switch (GET_CODE (op)) |
2a2ab3f9 | 981 | { |
e075ae69 RH |
982 | case SYMBOL_REF: |
983 | case LABEL_REF: | |
984 | return 1; | |
985 | ||
986 | case CONST: | |
987 | op = XEXP (op, 0); | |
988 | if (GET_CODE (op) == SYMBOL_REF | |
989 | || GET_CODE (op) == LABEL_REF | |
990 | || (GET_CODE (op) == UNSPEC | |
991 | && XINT (op, 1) >= 6 | |
992 | && XINT (op, 1) <= 7)) | |
993 | return 1; | |
994 | if (GET_CODE (op) != PLUS | |
995 | || GET_CODE (XEXP (op, 1)) != CONST_INT) | |
996 | return 0; | |
997 | ||
998 | op = XEXP (op, 0); | |
999 | if (GET_CODE (op) == SYMBOL_REF | |
1000 | || GET_CODE (op) == LABEL_REF) | |
1001 | return 1; | |
1002 | /* Only @GOTOFF gets offsets. */ | |
1003 | if (GET_CODE (op) != UNSPEC | |
1004 | || XINT (op, 1) != 7) | |
1005 | return 0; | |
1006 | ||
1007 | op = XVECEXP (op, 0, 0); | |
1008 | if (GET_CODE (op) == SYMBOL_REF | |
1009 | || GET_CODE (op) == LABEL_REF) | |
1010 | return 1; | |
1011 | return 0; | |
1012 | ||
1013 | default: | |
1014 | return 0; | |
2a2ab3f9 JVA |
1015 | } |
1016 | } | |
2a2ab3f9 | 1017 | |
e075ae69 | 1018 | /* Return true if the operand contains a @GOT or @GOTOFF reference. */ |
3b3c6a3f | 1019 | |
e075ae69 RH |
1020 | int |
1021 | pic_symbolic_operand (op, mode) | |
1022 | register rtx op; | |
1023 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1024 | { | |
1025 | if (GET_CODE (op) == CONST) | |
2a2ab3f9 | 1026 | { |
e075ae69 RH |
1027 | op = XEXP (op, 0); |
1028 | if (GET_CODE (op) == UNSPEC) | |
1029 | return 1; | |
1030 | if (GET_CODE (op) != PLUS | |
1031 | || GET_CODE (XEXP (op, 1)) != CONST_INT) | |
1032 | return 0; | |
1033 | op = XEXP (op, 0); | |
1034 | if (GET_CODE (op) == UNSPEC) | |
1035 | return 1; | |
2a2ab3f9 | 1036 | } |
e075ae69 | 1037 | return 0; |
2a2ab3f9 | 1038 | } |
2a2ab3f9 | 1039 | |
28d52ffb RH |
1040 | /* Test for a valid operand for a call instruction. Don't allow the |
1041 | arg pointer register or virtual regs since they may decay into | |
1042 | reg + const, which the patterns can't handle. */ | |
2a2ab3f9 | 1043 | |
e075ae69 RH |
1044 | int |
1045 | call_insn_operand (op, mode) | |
1046 | rtx op; | |
1047 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1048 | { | |
1049 | if (GET_CODE (op) != MEM) | |
1050 | return 0; | |
1051 | op = XEXP (op, 0); | |
2a2ab3f9 | 1052 | |
e075ae69 RH |
1053 | /* Disallow indirect through a virtual register. This leads to |
1054 | compiler aborts when trying to eliminate them. */ | |
1055 | if (GET_CODE (op) == REG | |
1056 | && (op == arg_pointer_rtx | |
564d80f4 | 1057 | || op == frame_pointer_rtx |
e075ae69 RH |
1058 | || (REGNO (op) >= FIRST_PSEUDO_REGISTER |
1059 | && REGNO (op) <= LAST_VIRTUAL_REGISTER))) | |
1060 | return 0; | |
2a2ab3f9 | 1061 | |
28d52ffb RH |
1062 | /* Disallow `call 1234'. Due to varying assembler lameness this |
1063 | gets either rejected or translated to `call .+1234'. */ | |
1064 | if (GET_CODE (op) == CONST_INT) | |
1065 | return 0; | |
1066 | ||
e075ae69 RH |
1067 | /* Otherwise we can allow any general_operand in the address. */ |
1068 | return general_operand (op, Pmode); | |
1069 | } | |
2a2ab3f9 | 1070 | |
28d52ffb | 1071 | /* Like call_insn_operand but allow (mem (symbol_ref ...)) even if pic. */ |
5f1ec3e6 | 1072 | |
e075ae69 RH |
1073 | int |
1074 | expander_call_insn_operand (op, mode) | |
1075 | rtx op; | |
28d52ffb | 1076 | enum machine_mode mode; |
e075ae69 | 1077 | { |
28d52ffb RH |
1078 | if (GET_CODE (op) == MEM |
1079 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF) | |
e075ae69 | 1080 | return 1; |
2a2ab3f9 | 1081 | |
28d52ffb | 1082 | return call_insn_operand (op, mode); |
e075ae69 | 1083 | } |
79325812 | 1084 | |
e075ae69 RH |
1085 | int |
1086 | constant_call_address_operand (op, mode) | |
1087 | rtx op; | |
1088 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1089 | { | |
1090 | return GET_CODE (op) == MEM && CONSTANT_ADDRESS_P (XEXP (op, 0)); | |
1091 | } | |
2a2ab3f9 | 1092 | |
e075ae69 | 1093 | /* Match exactly zero and one. */ |
e9a25f70 | 1094 | |
e075ae69 RH |
1095 | int |
1096 | const0_operand (op, mode) | |
1097 | register rtx op; | |
1098 | enum machine_mode mode; | |
1099 | { | |
1100 | return op == CONST0_RTX (mode); | |
1101 | } | |
e9a25f70 | 1102 | |
e075ae69 RH |
1103 | int |
1104 | const1_operand (op, mode) | |
1105 | register rtx op; | |
1106 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1107 | { | |
1108 | return op == const1_rtx; | |
1109 | } | |
2a2ab3f9 | 1110 | |
e075ae69 | 1111 | /* Match 2, 4, or 8. Used for leal multiplicands. */ |
e9a25f70 | 1112 | |
e075ae69 RH |
1113 | int |
1114 | const248_operand (op, mode) | |
1115 | register rtx op; | |
1116 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1117 | { | |
1118 | return (GET_CODE (op) == CONST_INT | |
1119 | && (INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8)); | |
1120 | } | |
e9a25f70 | 1121 | |
e075ae69 | 1122 | /* True if this is a constant appropriate for an increment or decremenmt. */ |
81fd0956 | 1123 | |
e075ae69 RH |
1124 | int |
1125 | incdec_operand (op, mode) | |
1126 | register rtx op; | |
1127 | enum machine_mode mode; | |
1128 | { | |
1129 | if (op == const1_rtx || op == constm1_rtx) | |
1130 | return 1; | |
1131 | if (GET_CODE (op) != CONST_INT) | |
1132 | return 0; | |
1133 | if (mode == SImode && INTVAL (op) == (HOST_WIDE_INT) 0xffffffff) | |
1134 | return 1; | |
1135 | if (mode == HImode && INTVAL (op) == (HOST_WIDE_INT) 0xffff) | |
1136 | return 1; | |
1137 | if (mode == QImode && INTVAL (op) == (HOST_WIDE_INT) 0xff) | |
1138 | return 1; | |
1139 | return 0; | |
1140 | } | |
2a2ab3f9 | 1141 | |
e075ae69 RH |
1142 | /* Return false if this is the stack pointer, or any other fake |
1143 | register eliminable to the stack pointer. Otherwise, this is | |
1144 | a register operand. | |
2a2ab3f9 | 1145 | |
e075ae69 RH |
1146 | This is used to prevent esp from being used as an index reg. |
1147 | Which would only happen in pathological cases. */ | |
5f1ec3e6 | 1148 | |
e075ae69 RH |
1149 | int |
1150 | reg_no_sp_operand (op, mode) | |
1151 | register rtx op; | |
1152 | enum machine_mode mode; | |
1153 | { | |
1154 | rtx t = op; | |
1155 | if (GET_CODE (t) == SUBREG) | |
1156 | t = SUBREG_REG (t); | |
564d80f4 | 1157 | if (t == stack_pointer_rtx || t == arg_pointer_rtx || t == frame_pointer_rtx) |
e075ae69 | 1158 | return 0; |
2a2ab3f9 | 1159 | |
e075ae69 | 1160 | return register_operand (op, mode); |
2a2ab3f9 | 1161 | } |
b840bfb0 | 1162 | |
2c5a510c RH |
1163 | /* Return false if this is any eliminable register. Otherwise |
1164 | general_operand. */ | |
1165 | ||
1166 | int | |
1167 | general_no_elim_operand (op, mode) | |
1168 | register rtx op; | |
1169 | enum machine_mode mode; | |
1170 | { | |
1171 | rtx t = op; | |
1172 | if (GET_CODE (t) == SUBREG) | |
1173 | t = SUBREG_REG (t); | |
1174 | if (t == arg_pointer_rtx || t == frame_pointer_rtx | |
1175 | || t == virtual_incoming_args_rtx || t == virtual_stack_vars_rtx | |
1176 | || t == virtual_stack_dynamic_rtx) | |
1177 | return 0; | |
1178 | ||
1179 | return general_operand (op, mode); | |
1180 | } | |
1181 | ||
1182 | /* Return false if this is any eliminable register. Otherwise | |
1183 | register_operand or const_int. */ | |
1184 | ||
1185 | int | |
1186 | nonmemory_no_elim_operand (op, mode) | |
1187 | register rtx op; | |
1188 | enum machine_mode mode; | |
1189 | { | |
1190 | rtx t = op; | |
1191 | if (GET_CODE (t) == SUBREG) | |
1192 | t = SUBREG_REG (t); | |
1193 | if (t == arg_pointer_rtx || t == frame_pointer_rtx | |
1194 | || t == virtual_incoming_args_rtx || t == virtual_stack_vars_rtx | |
1195 | || t == virtual_stack_dynamic_rtx) | |
1196 | return 0; | |
1197 | ||
1198 | return GET_CODE (op) == CONST_INT || register_operand (op, mode); | |
1199 | } | |
1200 | ||
e075ae69 | 1201 | /* Return true if op is a Q_REGS class register. */ |
b840bfb0 | 1202 | |
e075ae69 RH |
1203 | int |
1204 | q_regs_operand (op, mode) | |
1205 | register rtx op; | |
1206 | enum machine_mode mode; | |
b840bfb0 | 1207 | { |
e075ae69 RH |
1208 | if (mode != VOIDmode && GET_MODE (op) != mode) |
1209 | return 0; | |
1210 | if (GET_CODE (op) == SUBREG) | |
1211 | op = SUBREG_REG (op); | |
1212 | return QI_REG_P (op); | |
1213 | } | |
b840bfb0 | 1214 | |
e075ae69 | 1215 | /* Return true if op is a NON_Q_REGS class register. */ |
b840bfb0 | 1216 | |
e075ae69 RH |
1217 | int |
1218 | non_q_regs_operand (op, mode) | |
1219 | register rtx op; | |
1220 | enum machine_mode mode; | |
1221 | { | |
1222 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1223 | return 0; | |
1224 | if (GET_CODE (op) == SUBREG) | |
1225 | op = SUBREG_REG (op); | |
1226 | return NON_QI_REG_P (op); | |
1227 | } | |
b840bfb0 | 1228 | |
e075ae69 RH |
1229 | /* Return 1 if OP is a comparison operator that can use the condition code |
1230 | generated by a logical operation, which characteristicly does not set | |
1231 | overflow or carry. To be used with CCNOmode. */ | |
b840bfb0 | 1232 | |
e075ae69 RH |
1233 | int |
1234 | no_comparison_operator (op, mode) | |
1235 | register rtx op; | |
1236 | enum machine_mode mode; | |
1237 | { | |
1238 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
1239 | && GET_RTX_CLASS (GET_CODE (op)) == '<' | |
1240 | && GET_CODE (op) != LE | |
1241 | && GET_CODE (op) != GT); | |
1242 | } | |
b840bfb0 | 1243 | |
e075ae69 | 1244 | /* Return 1 if OP is a comparison operator that can be issued by fcmov. */ |
b840bfb0 | 1245 | |
e075ae69 RH |
1246 | int |
1247 | fcmov_comparison_operator (op, mode) | |
1248 | register rtx op; | |
1249 | enum machine_mode mode; | |
1250 | { | |
1251 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
1252 | && GET_RTX_CLASS (GET_CODE (op)) == '<' | |
1253 | && GET_CODE (op) == unsigned_condition (GET_CODE (op))); | |
1254 | } | |
b840bfb0 | 1255 | |
e9e80858 JH |
1256 | /* Return 1 if OP is a binary operator that can be promoted to wider mode. */ |
1257 | ||
1258 | int | |
1259 | promotable_binary_operator (op, mode) | |
1260 | register rtx op; | |
1261 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1262 | { | |
1263 | switch (GET_CODE (op)) | |
1264 | { | |
1265 | case MULT: | |
1266 | /* Modern CPUs have same latency for HImode and SImode multiply, | |
1267 | but 386 and 486 do HImode multiply faster. */ | |
1268 | return ix86_cpu > PROCESSOR_I486; | |
1269 | case PLUS: | |
1270 | case AND: | |
1271 | case IOR: | |
1272 | case XOR: | |
1273 | case ASHIFT: | |
1274 | return 1; | |
1275 | default: | |
1276 | return 0; | |
1277 | } | |
1278 | } | |
1279 | ||
e075ae69 RH |
1280 | /* Nearly general operand, but accept any const_double, since we wish |
1281 | to be able to drop them into memory rather than have them get pulled | |
1282 | into registers. */ | |
b840bfb0 | 1283 | |
2a2ab3f9 | 1284 | int |
e075ae69 RH |
1285 | cmp_fp_expander_operand (op, mode) |
1286 | register rtx op; | |
1287 | enum machine_mode mode; | |
2a2ab3f9 | 1288 | { |
e075ae69 | 1289 | if (mode != VOIDmode && mode != GET_MODE (op)) |
0b6b2900 | 1290 | return 0; |
e075ae69 | 1291 | if (GET_CODE (op) == CONST_DOUBLE) |
2a2ab3f9 | 1292 | return 1; |
e075ae69 | 1293 | return general_operand (op, mode); |
2a2ab3f9 JVA |
1294 | } |
1295 | ||
e075ae69 | 1296 | /* Match an SI or HImode register for a zero_extract. */ |
2a2ab3f9 JVA |
1297 | |
1298 | int | |
e075ae69 | 1299 | ext_register_operand (op, mode) |
2a2ab3f9 | 1300 | register rtx op; |
bb5177ac | 1301 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2a2ab3f9 | 1302 | { |
e075ae69 RH |
1303 | if (GET_MODE (op) != SImode && GET_MODE (op) != HImode) |
1304 | return 0; | |
1305 | return register_operand (op, VOIDmode); | |
1306 | } | |
1307 | ||
1308 | /* Return 1 if this is a valid binary floating-point operation. | |
1309 | OP is the expression matched, and MODE is its mode. */ | |
1310 | ||
1311 | int | |
1312 | binary_fp_operator (op, mode) | |
1313 | register rtx op; | |
1314 | enum machine_mode mode; | |
1315 | { | |
1316 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
1317 | return 0; | |
1318 | ||
2a2ab3f9 JVA |
1319 | switch (GET_CODE (op)) |
1320 | { | |
e075ae69 RH |
1321 | case PLUS: |
1322 | case MINUS: | |
1323 | case MULT: | |
1324 | case DIV: | |
1325 | return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; | |
e9a25f70 | 1326 | |
2a2ab3f9 JVA |
1327 | default: |
1328 | return 0; | |
1329 | } | |
1330 | } | |
fee2770d | 1331 | |
e075ae69 RH |
1332 | int |
1333 | mult_operator(op, mode) | |
1334 | register rtx op; | |
1335 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1336 | { | |
1337 | return GET_CODE (op) == MULT; | |
1338 | } | |
1339 | ||
1340 | int | |
1341 | div_operator(op, mode) | |
1342 | register rtx op; | |
1343 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1344 | { | |
1345 | return GET_CODE (op) == DIV; | |
1346 | } | |
0a726ef1 JL |
1347 | |
1348 | int | |
e075ae69 RH |
1349 | arith_or_logical_operator (op, mode) |
1350 | rtx op; | |
1351 | enum machine_mode mode; | |
0a726ef1 | 1352 | { |
e075ae69 RH |
1353 | return ((mode == VOIDmode || GET_MODE (op) == mode) |
1354 | && (GET_RTX_CLASS (GET_CODE (op)) == 'c' | |
1355 | || GET_RTX_CLASS (GET_CODE (op)) == '2')); | |
0a726ef1 JL |
1356 | } |
1357 | ||
e075ae69 | 1358 | /* Returns 1 if OP is memory operand with a displacement. */ |
fee2770d RS |
1359 | |
1360 | int | |
e075ae69 RH |
1361 | memory_displacement_operand (op, mode) |
1362 | register rtx op; | |
1363 | enum machine_mode mode; | |
4f2c8ebb | 1364 | { |
e075ae69 | 1365 | struct ix86_address parts; |
e9a25f70 | 1366 | |
e075ae69 RH |
1367 | if (! memory_operand (op, mode)) |
1368 | return 0; | |
1369 | ||
1370 | if (! ix86_decompose_address (XEXP (op, 0), &parts)) | |
1371 | abort (); | |
1372 | ||
1373 | return parts.disp != NULL_RTX; | |
4f2c8ebb RS |
1374 | } |
1375 | ||
e075ae69 RH |
1376 | /* To avoid problems when jump re-emits comparisons like testqi_ext_0, |
1377 | re-recognize the operand to avoid a copy_to_mode_reg that will fail. | |
1378 | ||
1379 | ??? It seems likely that this will only work because cmpsi is an | |
1380 | expander, and no actual insns use this. */ | |
4f2c8ebb RS |
1381 | |
1382 | int | |
e075ae69 RH |
1383 | cmpsi_operand (op, mode) |
1384 | rtx op; | |
1385 | enum machine_mode mode; | |
fee2770d | 1386 | { |
e075ae69 RH |
1387 | if (general_operand (op, mode)) |
1388 | return 1; | |
1389 | ||
1390 | if (GET_CODE (op) == AND | |
1391 | && GET_MODE (op) == SImode | |
1392 | && GET_CODE (XEXP (op, 0)) == ZERO_EXTRACT | |
1393 | && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT | |
1394 | && GET_CODE (XEXP (XEXP (op, 0), 2)) == CONST_INT | |
1395 | && INTVAL (XEXP (XEXP (op, 0), 1)) == 8 | |
1396 | && INTVAL (XEXP (XEXP (op, 0), 2)) == 8 | |
1397 | && GET_CODE (XEXP (op, 1)) == CONST_INT) | |
fee2770d | 1398 | return 1; |
e9a25f70 | 1399 | |
fee2770d RS |
1400 | return 0; |
1401 | } | |
d784886d | 1402 | |
e075ae69 RH |
1403 | /* Returns 1 if OP is memory operand that can not be represented by the |
1404 | modRM array. */ | |
d784886d RK |
1405 | |
1406 | int | |
e075ae69 | 1407 | long_memory_operand (op, mode) |
d784886d RK |
1408 | register rtx op; |
1409 | enum machine_mode mode; | |
1410 | { | |
e075ae69 | 1411 | if (! memory_operand (op, mode)) |
d784886d RK |
1412 | return 0; |
1413 | ||
e075ae69 | 1414 | return memory_address_length (op) != 0; |
d784886d | 1415 | } |
2247f6ed JH |
1416 | |
1417 | /* Return nonzero if the rtx is known aligned. */ | |
1418 | ||
1419 | int | |
1420 | aligned_operand (op, mode) | |
1421 | rtx op; | |
1422 | enum machine_mode mode; | |
1423 | { | |
1424 | struct ix86_address parts; | |
1425 | ||
1426 | if (!general_operand (op, mode)) | |
1427 | return 0; | |
1428 | ||
1429 | /* Registers and immediate operands are always "aligned". */ | |
1430 | if (GET_CODE (op) != MEM) | |
1431 | return 1; | |
1432 | ||
1433 | /* Don't even try to do any aligned optimizations with volatiles. */ | |
1434 | if (MEM_VOLATILE_P (op)) | |
1435 | return 0; | |
1436 | ||
1437 | op = XEXP (op, 0); | |
1438 | ||
1439 | /* Pushes and pops are only valid on the stack pointer. */ | |
1440 | if (GET_CODE (op) == PRE_DEC | |
1441 | || GET_CODE (op) == POST_INC) | |
1442 | return 1; | |
1443 | ||
1444 | /* Decode the address. */ | |
1445 | if (! ix86_decompose_address (op, &parts)) | |
1446 | abort (); | |
1447 | ||
1448 | /* Look for some component that isn't known to be aligned. */ | |
1449 | if (parts.index) | |
1450 | { | |
1451 | if (parts.scale < 4 | |
1452 | && REGNO_POINTER_ALIGN (REGNO (parts.index)) < 4) | |
1453 | return 0; | |
1454 | } | |
1455 | if (parts.base) | |
1456 | { | |
1457 | if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 4) | |
1458 | return 0; | |
1459 | } | |
1460 | if (parts.disp) | |
1461 | { | |
1462 | if (GET_CODE (parts.disp) != CONST_INT | |
1463 | || (INTVAL (parts.disp) & 3) != 0) | |
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | /* Didn't find one -- this must be an aligned address. */ | |
1468 | return 1; | |
1469 | } | |
e075ae69 RH |
1470 | \f |
1471 | /* Return true if the constant is something that can be loaded with | |
1472 | a special instruction. Only handle 0.0 and 1.0; others are less | |
1473 | worthwhile. */ | |
57dbca5e BS |
1474 | |
1475 | int | |
e075ae69 RH |
1476 | standard_80387_constant_p (x) |
1477 | rtx x; | |
57dbca5e | 1478 | { |
e075ae69 RH |
1479 | if (GET_CODE (x) != CONST_DOUBLE) |
1480 | return -1; | |
1481 | ||
1482 | #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) | |
1483 | { | |
1484 | REAL_VALUE_TYPE d; | |
1485 | jmp_buf handler; | |
1486 | int is0, is1; | |
1487 | ||
1488 | if (setjmp (handler)) | |
1489 | return 0; | |
1490 | ||
1491 | set_float_handler (handler); | |
1492 | REAL_VALUE_FROM_CONST_DOUBLE (d, x); | |
1493 | is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d); | |
1494 | is1 = REAL_VALUES_EQUAL (d, dconst1); | |
1495 | set_float_handler (NULL_PTR); | |
1496 | ||
1497 | if (is0) | |
1498 | return 1; | |
1499 | ||
1500 | if (is1) | |
1501 | return 2; | |
1502 | ||
1503 | /* Note that on the 80387, other constants, such as pi, | |
1504 | are much slower to load as standard constants | |
1505 | than to load from doubles in memory! */ | |
1506 | /* ??? Not true on K6: all constants are equal cost. */ | |
1507 | } | |
1508 | #endif | |
1509 | ||
1510 | return 0; | |
57dbca5e BS |
1511 | } |
1512 | ||
2a2ab3f9 JVA |
1513 | /* Returns 1 if OP contains a symbol reference */ |
1514 | ||
1515 | int | |
1516 | symbolic_reference_mentioned_p (op) | |
1517 | rtx op; | |
1518 | { | |
6f7d635c | 1519 | register const char *fmt; |
2a2ab3f9 JVA |
1520 | register int i; |
1521 | ||
1522 | if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) | |
1523 | return 1; | |
1524 | ||
1525 | fmt = GET_RTX_FORMAT (GET_CODE (op)); | |
1526 | for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) | |
1527 | { | |
1528 | if (fmt[i] == 'E') | |
1529 | { | |
1530 | register int j; | |
1531 | ||
1532 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
1533 | if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) | |
1534 | return 1; | |
1535 | } | |
e9a25f70 | 1536 | |
2a2ab3f9 JVA |
1537 | else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) |
1538 | return 1; | |
1539 | } | |
1540 | ||
1541 | return 0; | |
1542 | } | |
e075ae69 RH |
1543 | |
1544 | /* Return 1 if it is appropriate to emit `ret' instructions in the | |
1545 | body of a function. Do this only if the epilogue is simple, needing a | |
1546 | couple of insns. Prior to reloading, we can't tell how many registers | |
1547 | must be saved, so return 0 then. Return 0 if there is no frame | |
1548 | marker to de-allocate. | |
1549 | ||
1550 | If NON_SAVING_SETJMP is defined and true, then it is not possible | |
1551 | for the epilogue to be simple, so return 0. This is a special case | |
1552 | since NON_SAVING_SETJMP will not cause regs_ever_live to change | |
1553 | until final, but jump_optimize may need to know sooner if a | |
1554 | `return' is OK. */ | |
32b5b1aa SC |
1555 | |
1556 | int | |
e075ae69 | 1557 | ix86_can_use_return_insn_p () |
32b5b1aa | 1558 | { |
9a7372d6 RH |
1559 | HOST_WIDE_INT tsize; |
1560 | int nregs; | |
1561 | ||
e075ae69 RH |
1562 | #ifdef NON_SAVING_SETJMP |
1563 | if (NON_SAVING_SETJMP && current_function_calls_setjmp) | |
1564 | return 0; | |
1565 | #endif | |
9a7372d6 RH |
1566 | #ifdef FUNCTION_BLOCK_PROFILER_EXIT |
1567 | if (profile_block_flag == 2) | |
1568 | return 0; | |
1569 | #endif | |
1570 | ||
1571 | if (! reload_completed || frame_pointer_needed) | |
1572 | return 0; | |
32b5b1aa | 1573 | |
9a7372d6 RH |
1574 | /* Don't allow more than 32 pop, since that's all we can do |
1575 | with one instruction. */ | |
1576 | if (current_function_pops_args | |
1577 | && current_function_args_size >= 32768) | |
e075ae69 | 1578 | return 0; |
32b5b1aa | 1579 | |
9a7372d6 RH |
1580 | tsize = ix86_compute_frame_size (get_frame_size (), &nregs, NULL, NULL); |
1581 | return tsize == 0 && nregs == 0; | |
e075ae69 RH |
1582 | } |
1583 | \f | |
21a427cc | 1584 | static char *pic_label_name; |
e075ae69 | 1585 | static int pic_label_output; |
21a427cc | 1586 | static char *global_offset_table_name; |
e9a25f70 | 1587 | |
e075ae69 RH |
1588 | /* This function generates code for -fpic that loads %ebx with |
1589 | the return address of the caller and then returns. */ | |
1590 | ||
1591 | void | |
1592 | asm_output_function_prefix (file, name) | |
1593 | FILE *file; | |
1594 | char *name ATTRIBUTE_UNUSED; | |
1595 | { | |
1596 | rtx xops[2]; | |
1597 | int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table | |
1598 | || current_function_uses_const_pool); | |
1599 | xops[0] = pic_offset_table_rtx; | |
1600 | xops[1] = stack_pointer_rtx; | |
32b5b1aa | 1601 | |
e075ae69 RH |
1602 | /* Deep branch prediction favors having a return for every call. */ |
1603 | if (pic_reg_used && TARGET_DEEP_BRANCH_PREDICTION) | |
32b5b1aa | 1604 | { |
e075ae69 RH |
1605 | if (!pic_label_output) |
1606 | { | |
1607 | /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an | |
1608 | internal (non-global) label that's being emitted, it didn't make | |
1609 | sense to have .type information for local labels. This caused | |
1610 | the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving | |
1611 | me debug info for a label that you're declaring non-global?) this | |
1612 | was changed to call ASM_OUTPUT_LABEL() instead. */ | |
32b5b1aa | 1613 | |
e075ae69 | 1614 | ASM_OUTPUT_LABEL (file, pic_label_name); |
e9a25f70 | 1615 | |
e075ae69 RH |
1616 | xops[1] = gen_rtx_MEM (SImode, xops[1]); |
1617 | output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops); | |
1618 | output_asm_insn ("ret", xops); | |
0afeb08a | 1619 | |
e075ae69 | 1620 | pic_label_output = 1; |
32b5b1aa | 1621 | } |
32b5b1aa | 1622 | } |
32b5b1aa | 1623 | } |
32b5b1aa | 1624 | |
e075ae69 RH |
1625 | void |
1626 | load_pic_register () | |
32b5b1aa | 1627 | { |
e075ae69 | 1628 | rtx gotsym, pclab; |
32b5b1aa | 1629 | |
21a427cc AS |
1630 | if (global_offset_table_name == NULL) |
1631 | { | |
1632 | global_offset_table_name = | |
1633 | ggc_alloc_string ("_GLOBAL_OFFSET_TABLE_", 21); | |
1634 | ggc_add_string_root (&global_offset_table_name, 1); | |
1635 | } | |
1636 | gotsym = gen_rtx_SYMBOL_REF (Pmode, global_offset_table_name); | |
32b5b1aa | 1637 | |
e075ae69 | 1638 | if (TARGET_DEEP_BRANCH_PREDICTION) |
32b5b1aa | 1639 | { |
21a427cc AS |
1640 | if (pic_label_name == NULL) |
1641 | { | |
1642 | pic_label_name = ggc_alloc_string (NULL, 32); | |
1643 | ggc_add_string_root (&pic_label_name, 1); | |
1644 | ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", 0); | |
1645 | } | |
e075ae69 | 1646 | pclab = gen_rtx_MEM (QImode, gen_rtx_SYMBOL_REF (Pmode, pic_label_name)); |
32b5b1aa | 1647 | } |
e075ae69 | 1648 | else |
e5cb57e8 | 1649 | { |
e075ae69 | 1650 | pclab = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); |
e5cb57e8 | 1651 | } |
e5cb57e8 | 1652 | |
e075ae69 | 1653 | emit_insn (gen_prologue_get_pc (pic_offset_table_rtx, pclab)); |
2a2ab3f9 | 1654 | |
e075ae69 RH |
1655 | if (! TARGET_DEEP_BRANCH_PREDICTION) |
1656 | emit_insn (gen_popsi1 (pic_offset_table_rtx)); | |
79325812 | 1657 | |
e075ae69 | 1658 | emit_insn (gen_prologue_set_got (pic_offset_table_rtx, gotsym, pclab)); |
e9a25f70 | 1659 | } |
8dfe5673 | 1660 | |
e075ae69 | 1661 | /* Generate an SImode "push" pattern for input ARG. */ |
e9a25f70 | 1662 | |
e075ae69 RH |
1663 | static rtx |
1664 | gen_push (arg) | |
1665 | rtx arg; | |
e9a25f70 | 1666 | { |
c5c76735 JL |
1667 | return gen_rtx_SET (VOIDmode, |
1668 | gen_rtx_MEM (SImode, | |
1669 | gen_rtx_PRE_DEC (SImode, | |
1670 | stack_pointer_rtx)), | |
1671 | arg); | |
e9a25f70 JL |
1672 | } |
1673 | ||
0903fcab JH |
1674 | /* Return number of registers to be saved on the stack. */ |
1675 | ||
1676 | static int | |
1677 | ix86_nsaved_regs () | |
1678 | { | |
1679 | int nregs = 0; | |
1680 | int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table | |
1681 | || current_function_uses_const_pool); | |
1682 | int limit = (frame_pointer_needed | |
1683 | ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); | |
1684 | int regno; | |
1685 | ||
1686 | for (regno = limit - 1; regno >= 0; regno--) | |
1687 | if ((regs_ever_live[regno] && ! call_used_regs[regno]) | |
1688 | || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) | |
1689 | { | |
1690 | nregs ++; | |
1691 | } | |
1692 | return nregs; | |
1693 | } | |
1694 | ||
1695 | /* Return the offset between two registers, one to be eliminated, and the other | |
1696 | its replacement, at the start of a routine. */ | |
1697 | ||
1698 | HOST_WIDE_INT | |
1699 | ix86_initial_elimination_offset (from, to) | |
1700 | int from; | |
1701 | int to; | |
1702 | { | |
564d80f4 JH |
1703 | int padding1; |
1704 | int nregs; | |
1705 | ||
1706 | /* Stack grows downward: | |
1707 | ||
1708 | [arguments] | |
1709 | <- ARG_POINTER | |
1710 | saved pc | |
1711 | ||
1712 | saved frame pointer if frame_pointer_needed | |
1713 | <- HARD_FRAME_POINTER | |
1c71e60e | 1714 | [saved regs] |
564d80f4 JH |
1715 | |
1716 | [padding1] \ | |
1717 | | <- FRAME_POINTER | |
1718 | [frame] > tsize | |
1719 | | | |
1720 | [padding2] / | |
564d80f4 JH |
1721 | */ |
1722 | ||
1723 | if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
1724 | /* Skip saved PC and previous frame pointer. | |
1725 | Executed only when frame_pointer_needed. */ | |
1726 | return 8; | |
1727 | else if (from == FRAME_POINTER_REGNUM | |
1728 | && to == HARD_FRAME_POINTER_REGNUM) | |
1729 | { | |
1730 | ix86_compute_frame_size (get_frame_size (), &nregs, &padding1, (int *)0); | |
1c71e60e | 1731 | padding1 += nregs * UNITS_PER_WORD; |
564d80f4 JH |
1732 | return -padding1; |
1733 | } | |
0903fcab JH |
1734 | else |
1735 | { | |
564d80f4 JH |
1736 | /* ARG_POINTER or FRAME_POINTER to STACK_POINTER elimination. */ |
1737 | int frame_size = frame_pointer_needed ? 8 : 4; | |
0903fcab | 1738 | HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), |
564d80f4 | 1739 | &nregs, &padding1, (int *)0); |
0903fcab | 1740 | |
0903fcab | 1741 | |
564d80f4 JH |
1742 | if (to != STACK_POINTER_REGNUM) |
1743 | abort (); | |
1744 | else if (from == ARG_POINTER_REGNUM) | |
1745 | return tsize + nregs * UNITS_PER_WORD + frame_size; | |
1746 | else if (from != FRAME_POINTER_REGNUM) | |
1747 | abort (); | |
0903fcab | 1748 | else |
1c71e60e | 1749 | return tsize - padding1; |
0903fcab JH |
1750 | } |
1751 | } | |
1752 | ||
65954bd8 JL |
1753 | /* Compute the size of local storage taking into consideration the |
1754 | desired stack alignment which is to be maintained. Also determine | |
564d80f4 JH |
1755 | the number of registers saved below the local storage. |
1756 | ||
1757 | PADDING1 returns padding before stack frame and PADDING2 returns | |
1758 | padding after stack frame; | |
1759 | */ | |
1760 | ||
1761 | static HOST_WIDE_INT | |
1762 | ix86_compute_frame_size (size, nregs_on_stack, rpadding1, rpadding2) | |
65954bd8 JL |
1763 | HOST_WIDE_INT size; |
1764 | int *nregs_on_stack; | |
564d80f4 JH |
1765 | int *rpadding1; |
1766 | int *rpadding2; | |
65954bd8 | 1767 | { |
65954bd8 | 1768 | int nregs; |
564d80f4 JH |
1769 | int padding1 = 0; |
1770 | int padding2 = 0; | |
65954bd8 | 1771 | HOST_WIDE_INT total_size; |
564d80f4 | 1772 | int stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT; |
44affdae JH |
1773 | int offset; |
1774 | int preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT; | |
65954bd8 | 1775 | |
564d80f4 | 1776 | nregs = ix86_nsaved_regs (); |
564d80f4 | 1777 | total_size = size; |
65954bd8 | 1778 | |
44affdae | 1779 | offset = frame_pointer_needed ? 8 : 4; |
564d80f4 | 1780 | |
44affdae JH |
1781 | /* Do some sanity checking of stack_alignment_needed and preferred_alignment, |
1782 | since i386 port is the only using those features that may break easilly. */ | |
564d80f4 | 1783 | |
44affdae JH |
1784 | if (size && !stack_alignment_needed) |
1785 | abort (); | |
1786 | if (!size && stack_alignment_needed) | |
1787 | abort (); | |
1788 | if (preferred_alignment < STACK_BOUNDARY / BITS_PER_UNIT) | |
1789 | abort (); | |
1790 | if (preferred_alignment > PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT) | |
1791 | abort (); | |
1792 | if (stack_alignment_needed > PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT) | |
1793 | abort (); | |
564d80f4 | 1794 | |
44affdae JH |
1795 | if (stack_alignment_needed < 4) |
1796 | stack_alignment_needed = 4; | |
564d80f4 | 1797 | |
44affdae | 1798 | offset += nregs * UNITS_PER_WORD; |
65954bd8 | 1799 | |
44affdae | 1800 | total_size += offset; |
65954bd8 | 1801 | |
44affdae JH |
1802 | /* Align start of frame for local function. */ |
1803 | padding1 = ((offset + stack_alignment_needed - 1) | |
1804 | & -stack_alignment_needed) - offset; | |
1805 | total_size += padding1; | |
54ff41b7 | 1806 | |
44affdae JH |
1807 | /* Align stack boundary. */ |
1808 | padding2 = ((total_size + preferred_alignment - 1) | |
1809 | & -preferred_alignment) - total_size; | |
65954bd8 JL |
1810 | |
1811 | if (nregs_on_stack) | |
1812 | *nregs_on_stack = nregs; | |
564d80f4 JH |
1813 | if (rpadding1) |
1814 | *rpadding1 = padding1; | |
564d80f4 JH |
1815 | if (rpadding2) |
1816 | *rpadding2 = padding2; | |
1817 | ||
1818 | return size + padding1 + padding2; | |
65954bd8 JL |
1819 | } |
1820 | ||
0903fcab JH |
1821 | /* Emit code to save registers in the prologue. */ |
1822 | ||
1823 | static void | |
1824 | ix86_emit_save_regs () | |
1825 | { | |
1826 | register int regno; | |
1827 | int limit; | |
1828 | rtx insn; | |
1829 | int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table | |
1830 | || current_function_uses_const_pool); | |
1831 | limit = (frame_pointer_needed | |
564d80f4 | 1832 | ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); |
0903fcab JH |
1833 | |
1834 | for (regno = limit - 1; regno >= 0; regno--) | |
1835 | if ((regs_ever_live[regno] && !call_used_regs[regno]) | |
1836 | || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) | |
1837 | { | |
1838 | insn = emit_insn (gen_push (gen_rtx_REG (SImode, regno))); | |
1839 | RTX_FRAME_RELATED_P (insn) = 1; | |
1840 | } | |
1841 | } | |
1842 | ||
e075ae69 RH |
1843 | /* Expand the prologue into a bunch of separate insns. */ |
1844 | ||
1845 | void | |
1846 | ix86_expand_prologue () | |
2a2ab3f9 | 1847 | { |
564d80f4 JH |
1848 | HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), (int *)0, (int *)0, |
1849 | (int *)0); | |
1850 | rtx insn; | |
aae75261 JVA |
1851 | int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table |
1852 | || current_function_uses_const_pool); | |
79325812 | 1853 | |
e075ae69 RH |
1854 | /* Note: AT&T enter does NOT have reversed args. Enter is probably |
1855 | slower on all targets. Also sdb doesn't like it. */ | |
e9a25f70 | 1856 | |
2a2ab3f9 JVA |
1857 | if (frame_pointer_needed) |
1858 | { | |
564d80f4 | 1859 | insn = emit_insn (gen_push (hard_frame_pointer_rtx)); |
e075ae69 | 1860 | RTX_FRAME_RELATED_P (insn) = 1; |
e9a25f70 | 1861 | |
564d80f4 | 1862 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); |
e075ae69 | 1863 | RTX_FRAME_RELATED_P (insn) = 1; |
2a2ab3f9 JVA |
1864 | } |
1865 | ||
1c71e60e | 1866 | ix86_emit_save_regs (); |
564d80f4 | 1867 | |
8dfe5673 RK |
1868 | if (tsize == 0) |
1869 | ; | |
1870 | else if (! TARGET_STACK_PROBE || tsize < CHECK_STACK_LIMIT) | |
469ac993 | 1871 | { |
e075ae69 | 1872 | if (frame_pointer_needed) |
1c71e60e JH |
1873 | insn = emit_insn (gen_pro_epilogue_adjust_stack |
1874 | (stack_pointer_rtx, stack_pointer_rtx, | |
1875 | GEN_INT (-tsize), hard_frame_pointer_rtx)); | |
79325812 | 1876 | else |
e075ae69 RH |
1877 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
1878 | GEN_INT (-tsize))); | |
1879 | RTX_FRAME_RELATED_P (insn) = 1; | |
469ac993 | 1880 | } |
79325812 | 1881 | else |
8dfe5673 | 1882 | { |
e075ae69 | 1883 | /* ??? Is this only valid for Win32? */ |
e9a25f70 | 1884 | |
e075ae69 | 1885 | rtx arg0, sym; |
e9a25f70 | 1886 | |
e075ae69 RH |
1887 | arg0 = gen_rtx_REG (SImode, 0); |
1888 | emit_move_insn (arg0, GEN_INT (tsize)); | |
77a989d1 | 1889 | |
e075ae69 RH |
1890 | sym = gen_rtx_MEM (FUNCTION_MODE, |
1891 | gen_rtx_SYMBOL_REF (Pmode, "_alloca")); | |
1892 | insn = emit_call_insn (gen_call (sym, const0_rtx)); | |
1893 | ||
1894 | CALL_INSN_FUNCTION_USAGE (insn) | |
276ab4a4 RH |
1895 | = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, arg0), |
1896 | CALL_INSN_FUNCTION_USAGE (insn)); | |
e075ae69 | 1897 | } |
e9a25f70 | 1898 | |
84530511 SC |
1899 | #ifdef SUBTARGET_PROLOGUE |
1900 | SUBTARGET_PROLOGUE; | |
1901 | #endif | |
1902 | ||
e9a25f70 | 1903 | if (pic_reg_used) |
e075ae69 | 1904 | load_pic_register (); |
77a989d1 | 1905 | |
e9a25f70 JL |
1906 | /* If we are profiling, make sure no instructions are scheduled before |
1907 | the call to mcount. However, if -fpic, the above call will have | |
1908 | done that. */ | |
e075ae69 | 1909 | if ((profile_flag || profile_block_flag) && ! pic_reg_used) |
e9a25f70 | 1910 | emit_insn (gen_blockage ()); |
77a989d1 SC |
1911 | } |
1912 | ||
0903fcab JH |
1913 | /* Emit code to add TSIZE to esp value. Use POP instruction when |
1914 | profitable. */ | |
1915 | ||
1916 | static void | |
1917 | ix86_emit_epilogue_esp_adjustment (tsize) | |
1918 | int tsize; | |
1919 | { | |
1920 | /* Intel's docs say that for 4 or 8 bytes of stack frame one should | |
1921 | use `pop' and not `add'. */ | |
1922 | int use_pop = tsize == 4; | |
1923 | rtx edx = 0, ecx; | |
1924 | ||
1925 | /* Use two pops only for the Pentium processors. */ | |
1926 | if (tsize == 8 && !TARGET_386 && !TARGET_486) | |
1927 | { | |
1928 | rtx retval = current_function_return_rtx; | |
1929 | ||
1930 | edx = gen_rtx_REG (SImode, 1); | |
1931 | ||
1932 | /* This case is a bit more complex. Since we cannot pop into | |
1933 | %ecx twice we need a second register. But this is only | |
1934 | available if the return value is not of DImode in which | |
1935 | case the %edx register is not available. */ | |
1936 | use_pop = (retval == NULL | |
1937 | || !reg_overlap_mentioned_p (edx, retval)); | |
1938 | } | |
1939 | ||
1940 | if (use_pop) | |
1941 | { | |
1942 | ecx = gen_rtx_REG (SImode, 2); | |
1943 | ||
1944 | /* We have to prevent the two pops here from being scheduled. | |
1945 | GCC otherwise would try in some situation to put other | |
1946 | instructions in between them which has a bad effect. */ | |
1947 | emit_insn (gen_blockage ()); | |
1948 | emit_insn (gen_popsi1 (ecx)); | |
1949 | if (tsize == 8) | |
1950 | emit_insn (gen_popsi1 (edx)); | |
1951 | } | |
1952 | else | |
1953 | { | |
1c71e60e JH |
1954 | /* If a frame pointer is present, we must be sure to tie the sp |
1955 | to the fp so that we don't mis-schedule. */ | |
1956 | if (frame_pointer_needed) | |
1957 | emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx, | |
1958 | stack_pointer_rtx, | |
1959 | GEN_INT (tsize), | |
1960 | hard_frame_pointer_rtx)); | |
1961 | else | |
1962 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1963 | GEN_INT (tsize))); | |
0903fcab JH |
1964 | } |
1965 | } | |
1966 | ||
da2d1d3a JH |
1967 | /* Emit code to restore saved registers using MOV insns. First register |
1968 | is restored from POINTER + OFFSET. */ | |
1969 | static void | |
1970 | ix86_emit_restore_regs_using_mov (pointer, offset) | |
1971 | rtx pointer; | |
1972 | int offset; | |
1973 | { | |
1974 | int regno; | |
1975 | int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table | |
1976 | || current_function_uses_const_pool); | |
1977 | int limit = (frame_pointer_needed | |
1978 | ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); | |
1979 | ||
1980 | for (regno = 0; regno < limit; regno++) | |
1981 | if ((regs_ever_live[regno] && !call_used_regs[regno]) | |
1982 | || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) | |
1983 | { | |
1984 | emit_move_insn (gen_rtx_REG (SImode, regno), | |
1985 | adj_offsettable_operand (gen_rtx_MEM (SImode, | |
1986 | pointer), | |
1987 | offset)); | |
1988 | offset += 4; | |
1989 | } | |
1990 | } | |
1991 | ||
79325812 | 1992 | /* Restore function stack, frame, and registers. */ |
e9a25f70 | 1993 | |
2a2ab3f9 | 1994 | void |
77a989d1 | 1995 | ix86_expand_epilogue () |
2a2ab3f9 | 1996 | { |
65954bd8 | 1997 | int nregs; |
1c71e60e JH |
1998 | int regno; |
1999 | ||
aae75261 JVA |
2000 | int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table |
2001 | || current_function_uses_const_pool); | |
fdb8a883 | 2002 | int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging; |
65954bd8 | 2003 | HOST_WIDE_INT offset; |
1c71e60e JH |
2004 | HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), &nregs, |
2005 | (int *)0, (int *)0); | |
2a2ab3f9 | 2006 | |
2a2ab3f9 | 2007 | |
1c71e60e JH |
2008 | /* Calculate start of saved registers relative to ebp. */ |
2009 | offset = -nregs * UNITS_PER_WORD; | |
2a2ab3f9 | 2010 | |
1c71e60e JH |
2011 | #ifdef FUNCTION_BLOCK_PROFILER_EXIT |
2012 | if (profile_block_flag == 2) | |
564d80f4 | 2013 | { |
1c71e60e | 2014 | FUNCTION_BLOCK_PROFILER_EXIT; |
564d80f4 | 2015 | } |
1c71e60e | 2016 | #endif |
564d80f4 | 2017 | |
fdb8a883 JW |
2018 | /* If we're only restoring one register and sp is not valid then |
2019 | using a move instruction to restore the register since it's | |
da2d1d3a JH |
2020 | less work than reloading sp and popping the register. |
2021 | ||
2022 | The default code result in stack adjustment using add/lea instruction, | |
2023 | while this code results in LEAVE instruction (or discrete equivalent), | |
2024 | so it is profitable in some other cases as well. Especially when there | |
2025 | are no registers to restore. We also use this code when TARGET_USE_LEAVE | |
2026 | and there is exactly one register to pop. This heruistic may need some | |
2027 | tuning in future. */ | |
2028 | if ((!sp_valid && nregs <= 1) | |
2029 | || (frame_pointer_needed && !nregs && tsize) | |
2030 | || (frame_pointer_needed && TARGET_USE_LEAVE && !optimize_size | |
2031 | && nregs == 1)) | |
2a2ab3f9 | 2032 | { |
da2d1d3a JH |
2033 | /* Restore registers. We can use ebp or esp to address the memory |
2034 | locations. If both are available, default to ebp, since offsets | |
2035 | are known to be small. Only exception is esp pointing directly to the | |
2036 | end of block of saved registers, where we may simplify addressing | |
2037 | mode. */ | |
2038 | ||
2039 | if (!frame_pointer_needed || (sp_valid && !tsize)) | |
2040 | ix86_emit_restore_regs_using_mov (stack_pointer_rtx, tsize); | |
2041 | else | |
2042 | ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx, offset); | |
2a2ab3f9 | 2043 | |
da2d1d3a JH |
2044 | if (!frame_pointer_needed) |
2045 | ix86_emit_epilogue_esp_adjustment (tsize + nregs * UNITS_PER_WORD); | |
c8c5cb99 | 2046 | /* If not an i386, mov & pop is faster than "leave". */ |
da2d1d3a | 2047 | else if (TARGET_USE_LEAVE || optimize_size) |
564d80f4 | 2048 | emit_insn (gen_leave ()); |
c8c5cb99 | 2049 | else |
2a2ab3f9 | 2050 | { |
1c71e60e JH |
2051 | emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx, |
2052 | hard_frame_pointer_rtx, | |
2053 | const0_rtx, | |
2054 | hard_frame_pointer_rtx)); | |
564d80f4 | 2055 | emit_insn (gen_popsi1 (hard_frame_pointer_rtx)); |
e9a25f70 JL |
2056 | } |
2057 | } | |
1c71e60e | 2058 | else |
68f654ec | 2059 | { |
1c71e60e JH |
2060 | /* First step is to deallocate the stack frame so that we can |
2061 | pop the registers. */ | |
2062 | if (!sp_valid) | |
2063 | { | |
2064 | if (!frame_pointer_needed) | |
2065 | abort (); | |
2066 | emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx, | |
2067 | hard_frame_pointer_rtx, | |
2068 | GEN_INT (offset), | |
2069 | hard_frame_pointer_rtx)); | |
2070 | } | |
2071 | else if (tsize) | |
2072 | ix86_emit_epilogue_esp_adjustment (tsize); | |
2073 | ||
2074 | for (regno = 0; regno < STACK_POINTER_REGNUM; regno++) | |
2075 | if ((regs_ever_live[regno] && !call_used_regs[regno]) | |
2076 | || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) | |
2077 | emit_insn (gen_popsi1 (gen_rtx_REG (SImode, regno))); | |
68f654ec | 2078 | } |
68f654ec | 2079 | |
2a2ab3f9 JVA |
2080 | if (current_function_pops_args && current_function_args_size) |
2081 | { | |
e075ae69 | 2082 | rtx popc = GEN_INT (current_function_pops_args); |
2a2ab3f9 JVA |
2083 | |
2084 | /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If | |
2085 | asked to pop more, pop return address, do explicit add, and jump | |
2086 | indirectly to the caller. */ | |
2087 | ||
2088 | if (current_function_pops_args >= 32768) | |
2089 | { | |
e075ae69 | 2090 | rtx ecx = gen_rtx_REG (SImode, 2); |
e9a25f70 | 2091 | |
e075ae69 RH |
2092 | emit_insn (gen_popsi1 (ecx)); |
2093 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc)); | |
2094 | emit_indirect_jump (ecx); | |
e9a25f70 | 2095 | } |
79325812 | 2096 | else |
e075ae69 RH |
2097 | emit_jump_insn (gen_return_pop_internal (popc)); |
2098 | } | |
2099 | else | |
2100 | emit_jump_insn (gen_return_internal ()); | |
2101 | } | |
2102 | \f | |
2103 | /* Extract the parts of an RTL expression that is a valid memory address | |
2104 | for an instruction. Return false if the structure of the address is | |
2105 | grossly off. */ | |
2106 | ||
2107 | static int | |
2108 | ix86_decompose_address (addr, out) | |
2109 | register rtx addr; | |
2110 | struct ix86_address *out; | |
2111 | { | |
2112 | rtx base = NULL_RTX; | |
2113 | rtx index = NULL_RTX; | |
2114 | rtx disp = NULL_RTX; | |
2115 | HOST_WIDE_INT scale = 1; | |
2116 | rtx scale_rtx = NULL_RTX; | |
2117 | ||
2118 | if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG) | |
2119 | base = addr; | |
2120 | else if (GET_CODE (addr) == PLUS) | |
2121 | { | |
2122 | rtx op0 = XEXP (addr, 0); | |
2123 | rtx op1 = XEXP (addr, 1); | |
2124 | enum rtx_code code0 = GET_CODE (op0); | |
2125 | enum rtx_code code1 = GET_CODE (op1); | |
2126 | ||
2127 | if (code0 == REG || code0 == SUBREG) | |
2128 | { | |
2129 | if (code1 == REG || code1 == SUBREG) | |
2130 | index = op0, base = op1; /* index + base */ | |
2131 | else | |
2132 | base = op0, disp = op1; /* base + displacement */ | |
2133 | } | |
2134 | else if (code0 == MULT) | |
e9a25f70 | 2135 | { |
e075ae69 RH |
2136 | index = XEXP (op0, 0); |
2137 | scale_rtx = XEXP (op0, 1); | |
2138 | if (code1 == REG || code1 == SUBREG) | |
2139 | base = op1; /* index*scale + base */ | |
e9a25f70 | 2140 | else |
e075ae69 RH |
2141 | disp = op1; /* index*scale + disp */ |
2142 | } | |
2143 | else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT) | |
2144 | { | |
2145 | index = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */ | |
2146 | scale_rtx = XEXP (XEXP (op0, 0), 1); | |
2147 | base = XEXP (op0, 1); | |
2148 | disp = op1; | |
2a2ab3f9 | 2149 | } |
e075ae69 RH |
2150 | else if (code0 == PLUS) |
2151 | { | |
2152 | index = XEXP (op0, 0); /* index + base + disp */ | |
2153 | base = XEXP (op0, 1); | |
2154 | disp = op1; | |
2155 | } | |
2156 | else | |
2157 | return FALSE; | |
2158 | } | |
2159 | else if (GET_CODE (addr) == MULT) | |
2160 | { | |
2161 | index = XEXP (addr, 0); /* index*scale */ | |
2162 | scale_rtx = XEXP (addr, 1); | |
2163 | } | |
2164 | else if (GET_CODE (addr) == ASHIFT) | |
2165 | { | |
2166 | rtx tmp; | |
2167 | ||
2168 | /* We're called for lea too, which implements ashift on occasion. */ | |
2169 | index = XEXP (addr, 0); | |
2170 | tmp = XEXP (addr, 1); | |
2171 | if (GET_CODE (tmp) != CONST_INT) | |
2172 | return FALSE; | |
2173 | scale = INTVAL (tmp); | |
2174 | if ((unsigned HOST_WIDE_INT) scale > 3) | |
2175 | return FALSE; | |
2176 | scale = 1 << scale; | |
2a2ab3f9 | 2177 | } |
2a2ab3f9 | 2178 | else |
e075ae69 RH |
2179 | disp = addr; /* displacement */ |
2180 | ||
2181 | /* Extract the integral value of scale. */ | |
2182 | if (scale_rtx) | |
e9a25f70 | 2183 | { |
e075ae69 RH |
2184 | if (GET_CODE (scale_rtx) != CONST_INT) |
2185 | return FALSE; | |
2186 | scale = INTVAL (scale_rtx); | |
e9a25f70 | 2187 | } |
3b3c6a3f | 2188 | |
e075ae69 RH |
2189 | /* Allow arg pointer and stack pointer as index if there is not scaling */ |
2190 | if (base && index && scale == 1 | |
564d80f4 JH |
2191 | && (index == arg_pointer_rtx || index == frame_pointer_rtx |
2192 | || index == stack_pointer_rtx)) | |
e075ae69 RH |
2193 | { |
2194 | rtx tmp = base; | |
2195 | base = index; | |
2196 | index = tmp; | |
2197 | } | |
2198 | ||
2199 | /* Special case: %ebp cannot be encoded as a base without a displacement. */ | |
564d80f4 JH |
2200 | if ((base == hard_frame_pointer_rtx |
2201 | || base == frame_pointer_rtx | |
2202 | || base == arg_pointer_rtx) && !disp) | |
e075ae69 RH |
2203 | disp = const0_rtx; |
2204 | ||
2205 | /* Special case: on K6, [%esi] makes the instruction vector decoded. | |
2206 | Avoid this by transforming to [%esi+0]. */ | |
2207 | if (ix86_cpu == PROCESSOR_K6 && !optimize_size | |
2208 | && base && !index && !disp | |
329e1d01 | 2209 | && REG_P (base) |
e075ae69 RH |
2210 | && REGNO_REG_CLASS (REGNO (base)) == SIREG) |
2211 | disp = const0_rtx; | |
2212 | ||
2213 | /* Special case: encode reg+reg instead of reg*2. */ | |
2214 | if (!base && index && scale && scale == 2) | |
2215 | base = index, scale = 1; | |
2216 | ||
2217 | /* Special case: scaling cannot be encoded without base or displacement. */ | |
2218 | if (!base && !disp && index && scale != 1) | |
2219 | disp = const0_rtx; | |
2220 | ||
2221 | out->base = base; | |
2222 | out->index = index; | |
2223 | out->disp = disp; | |
2224 | out->scale = scale; | |
3b3c6a3f | 2225 | |
e075ae69 RH |
2226 | return TRUE; |
2227 | } | |
3b3c6a3f | 2228 | |
e075ae69 RH |
2229 | /* Determine if a given CONST RTX is a valid memory displacement |
2230 | in PIC mode. */ | |
2231 | ||
59be65f6 | 2232 | int |
91bb873f RH |
2233 | legitimate_pic_address_disp_p (disp) |
2234 | register rtx disp; | |
2235 | { | |
2236 | if (GET_CODE (disp) != CONST) | |
2237 | return 0; | |
2238 | disp = XEXP (disp, 0); | |
2239 | ||
2240 | if (GET_CODE (disp) == PLUS) | |
2241 | { | |
2242 | if (GET_CODE (XEXP (disp, 1)) != CONST_INT) | |
2243 | return 0; | |
2244 | disp = XEXP (disp, 0); | |
2245 | } | |
2246 | ||
2247 | if (GET_CODE (disp) != UNSPEC | |
2248 | || XVECLEN (disp, 0) != 1) | |
2249 | return 0; | |
2250 | ||
2251 | /* Must be @GOT or @GOTOFF. */ | |
2252 | if (XINT (disp, 1) != 6 | |
2253 | && XINT (disp, 1) != 7) | |
2254 | return 0; | |
2255 | ||
2256 | if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF | |
2257 | && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF) | |
2258 | return 0; | |
2259 | ||
2260 | return 1; | |
2261 | } | |
2262 | ||
e075ae69 RH |
2263 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid |
2264 | memory address for an instruction. The MODE argument is the machine mode | |
2265 | for the MEM expression that wants to use this address. | |
2266 | ||
2267 | It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should | |
2268 | convert common non-canonical forms to canonical form so that they will | |
2269 | be recognized. */ | |
2270 | ||
3b3c6a3f MM |
2271 | int |
2272 | legitimate_address_p (mode, addr, strict) | |
2273 | enum machine_mode mode; | |
2274 | register rtx addr; | |
2275 | int strict; | |
2276 | { | |
e075ae69 RH |
2277 | struct ix86_address parts; |
2278 | rtx base, index, disp; | |
2279 | HOST_WIDE_INT scale; | |
2280 | const char *reason = NULL; | |
2281 | rtx reason_rtx = NULL_RTX; | |
3b3c6a3f MM |
2282 | |
2283 | if (TARGET_DEBUG_ADDR) | |
2284 | { | |
2285 | fprintf (stderr, | |
e9a25f70 | 2286 | "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n", |
3b3c6a3f | 2287 | GET_MODE_NAME (mode), strict); |
3b3c6a3f MM |
2288 | debug_rtx (addr); |
2289 | } | |
2290 | ||
e075ae69 | 2291 | if (! ix86_decompose_address (addr, &parts)) |
3b3c6a3f | 2292 | { |
e075ae69 RH |
2293 | reason = "decomposition failed"; |
2294 | goto error; | |
3b3c6a3f MM |
2295 | } |
2296 | ||
e075ae69 RH |
2297 | base = parts.base; |
2298 | index = parts.index; | |
2299 | disp = parts.disp; | |
2300 | scale = parts.scale; | |
91f0226f | 2301 | |
e075ae69 | 2302 | /* Validate base register. |
e9a25f70 JL |
2303 | |
2304 | Don't allow SUBREG's here, it can lead to spill failures when the base | |
3d771dfd MM |
2305 | is one word out of a two word structure, which is represented internally |
2306 | as a DImode int. */ | |
e9a25f70 | 2307 | |
3b3c6a3f MM |
2308 | if (base) |
2309 | { | |
e075ae69 RH |
2310 | reason_rtx = base; |
2311 | ||
3d771dfd | 2312 | if (GET_CODE (base) != REG) |
3b3c6a3f | 2313 | { |
e075ae69 RH |
2314 | reason = "base is not a register"; |
2315 | goto error; | |
3b3c6a3f MM |
2316 | } |
2317 | ||
c954bd01 RH |
2318 | if (GET_MODE (base) != Pmode) |
2319 | { | |
e075ae69 RH |
2320 | reason = "base is not in Pmode"; |
2321 | goto error; | |
c954bd01 RH |
2322 | } |
2323 | ||
e9a25f70 JL |
2324 | if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base)) |
2325 | || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base))) | |
3b3c6a3f | 2326 | { |
e075ae69 RH |
2327 | reason = "base is not valid"; |
2328 | goto error; | |
3b3c6a3f MM |
2329 | } |
2330 | } | |
2331 | ||
e075ae69 | 2332 | /* Validate index register. |
e9a25f70 JL |
2333 | |
2334 | Don't allow SUBREG's here, it can lead to spill failures when the index | |
3d771dfd MM |
2335 | is one word out of a two word structure, which is represented internally |
2336 | as a DImode int. */ | |
e075ae69 RH |
2337 | |
2338 | if (index) | |
3b3c6a3f | 2339 | { |
e075ae69 RH |
2340 | reason_rtx = index; |
2341 | ||
2342 | if (GET_CODE (index) != REG) | |
3b3c6a3f | 2343 | { |
e075ae69 RH |
2344 | reason = "index is not a register"; |
2345 | goto error; | |
3b3c6a3f MM |
2346 | } |
2347 | ||
e075ae69 | 2348 | if (GET_MODE (index) != Pmode) |
c954bd01 | 2349 | { |
e075ae69 RH |
2350 | reason = "index is not in Pmode"; |
2351 | goto error; | |
c954bd01 RH |
2352 | } |
2353 | ||
e075ae69 RH |
2354 | if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (index)) |
2355 | || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (index))) | |
3b3c6a3f | 2356 | { |
e075ae69 RH |
2357 | reason = "index is not valid"; |
2358 | goto error; | |
3b3c6a3f MM |
2359 | } |
2360 | } | |
3b3c6a3f | 2361 | |
e075ae69 RH |
2362 | /* Validate scale factor. */ |
2363 | if (scale != 1) | |
3b3c6a3f | 2364 | { |
e075ae69 RH |
2365 | reason_rtx = GEN_INT (scale); |
2366 | if (!index) | |
3b3c6a3f | 2367 | { |
e075ae69 RH |
2368 | reason = "scale without index"; |
2369 | goto error; | |
3b3c6a3f MM |
2370 | } |
2371 | ||
e075ae69 | 2372 | if (scale != 2 && scale != 4 && scale != 8) |
3b3c6a3f | 2373 | { |
e075ae69 RH |
2374 | reason = "scale is not a valid multiplier"; |
2375 | goto error; | |
3b3c6a3f MM |
2376 | } |
2377 | } | |
2378 | ||
91bb873f | 2379 | /* Validate displacement. */ |
3b3c6a3f MM |
2380 | if (disp) |
2381 | { | |
e075ae69 RH |
2382 | reason_rtx = disp; |
2383 | ||
91bb873f | 2384 | if (!CONSTANT_ADDRESS_P (disp)) |
3b3c6a3f | 2385 | { |
e075ae69 RH |
2386 | reason = "displacement is not constant"; |
2387 | goto error; | |
3b3c6a3f MM |
2388 | } |
2389 | ||
e075ae69 | 2390 | if (GET_CODE (disp) == CONST_DOUBLE) |
3b3c6a3f | 2391 | { |
e075ae69 RH |
2392 | reason = "displacement is a const_double"; |
2393 | goto error; | |
3b3c6a3f MM |
2394 | } |
2395 | ||
91bb873f | 2396 | if (flag_pic && SYMBOLIC_CONST (disp)) |
3b3c6a3f | 2397 | { |
91bb873f RH |
2398 | if (! legitimate_pic_address_disp_p (disp)) |
2399 | { | |
e075ae69 RH |
2400 | reason = "displacement is an invalid pic construct"; |
2401 | goto error; | |
91bb873f RH |
2402 | } |
2403 | ||
e075ae69 RH |
2404 | /* Verify that a symbolic pic displacement includes |
2405 | the pic_offset_table_rtx register. */ | |
91bb873f | 2406 | if (base != pic_offset_table_rtx |
e075ae69 | 2407 | && (index != pic_offset_table_rtx || scale != 1)) |
91bb873f | 2408 | { |
e075ae69 RH |
2409 | reason = "pic displacement against invalid base"; |
2410 | goto error; | |
91bb873f | 2411 | } |
3b3c6a3f | 2412 | } |
91bb873f | 2413 | else if (HALF_PIC_P ()) |
3b3c6a3f | 2414 | { |
91bb873f | 2415 | if (! HALF_PIC_ADDRESS_P (disp) |
e075ae69 | 2416 | || (base != NULL_RTX || index != NULL_RTX)) |
91bb873f | 2417 | { |
e075ae69 RH |
2418 | reason = "displacement is an invalid half-pic reference"; |
2419 | goto error; | |
91bb873f | 2420 | } |
3b3c6a3f MM |
2421 | } |
2422 | } | |
2423 | ||
e075ae69 | 2424 | /* Everything looks valid. */ |
3b3c6a3f | 2425 | if (TARGET_DEBUG_ADDR) |
e075ae69 | 2426 | fprintf (stderr, "Success.\n"); |
3b3c6a3f | 2427 | return TRUE; |
e075ae69 RH |
2428 | |
2429 | error: | |
2430 | if (TARGET_DEBUG_ADDR) | |
2431 | { | |
2432 | fprintf (stderr, "Error: %s\n", reason); | |
2433 | debug_rtx (reason_rtx); | |
2434 | } | |
2435 | return FALSE; | |
3b3c6a3f | 2436 | } |
3b3c6a3f MM |
2437 | \f |
2438 | /* Return a legitimate reference for ORIG (an address) using the | |
2439 | register REG. If REG is 0, a new pseudo is generated. | |
2440 | ||
91bb873f | 2441 | There are two types of references that must be handled: |
3b3c6a3f MM |
2442 | |
2443 | 1. Global data references must load the address from the GOT, via | |
2444 | the PIC reg. An insn is emitted to do this load, and the reg is | |
2445 | returned. | |
2446 | ||
91bb873f RH |
2447 | 2. Static data references, constant pool addresses, and code labels |
2448 | compute the address as an offset from the GOT, whose base is in | |
2449 | the PIC reg. Static data objects have SYMBOL_REF_FLAG set to | |
2450 | differentiate them from global data objects. The returned | |
2451 | address is the PIC reg + an unspec constant. | |
3b3c6a3f MM |
2452 | |
2453 | GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC | |
91bb873f | 2454 | reg also appears in the address. */ |
3b3c6a3f MM |
2455 | |
2456 | rtx | |
2457 | legitimize_pic_address (orig, reg) | |
2458 | rtx orig; | |
2459 | rtx reg; | |
2460 | { | |
2461 | rtx addr = orig; | |
2462 | rtx new = orig; | |
91bb873f | 2463 | rtx base; |
3b3c6a3f | 2464 | |
91bb873f RH |
2465 | if (GET_CODE (addr) == LABEL_REF |
2466 | || (GET_CODE (addr) == SYMBOL_REF | |
2467 | && (CONSTANT_POOL_ADDRESS_P (addr) | |
2468 | || SYMBOL_REF_FLAG (addr)))) | |
3b3c6a3f | 2469 | { |
91bb873f RH |
2470 | /* This symbol may be referenced via a displacement from the PIC |
2471 | base address (@GOTOFF). */ | |
3b3c6a3f | 2472 | |
91bb873f RH |
2473 | current_function_uses_pic_offset_table = 1; |
2474 | new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 7); | |
2475 | new = gen_rtx_CONST (VOIDmode, new); | |
2476 | new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); | |
3b3c6a3f | 2477 | |
91bb873f RH |
2478 | if (reg != 0) |
2479 | { | |
3b3c6a3f | 2480 | emit_move_insn (reg, new); |
91bb873f | 2481 | new = reg; |
3b3c6a3f | 2482 | } |
3b3c6a3f | 2483 | } |
91bb873f | 2484 | else if (GET_CODE (addr) == SYMBOL_REF) |
3b3c6a3f | 2485 | { |
91bb873f RH |
2486 | /* This symbol must be referenced via a load from the |
2487 | Global Offset Table (@GOT). */ | |
3b3c6a3f | 2488 | |
91bb873f RH |
2489 | current_function_uses_pic_offset_table = 1; |
2490 | new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 6); | |
2491 | new = gen_rtx_CONST (VOIDmode, new); | |
2492 | new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); | |
2493 | new = gen_rtx_MEM (Pmode, new); | |
2494 | RTX_UNCHANGING_P (new) = 1; | |
3b3c6a3f MM |
2495 | |
2496 | if (reg == 0) | |
2497 | reg = gen_reg_rtx (Pmode); | |
91bb873f RH |
2498 | emit_move_insn (reg, new); |
2499 | new = reg; | |
2500 | } | |
2501 | else | |
2502 | { | |
2503 | if (GET_CODE (addr) == CONST) | |
3b3c6a3f | 2504 | { |
91bb873f RH |
2505 | addr = XEXP (addr, 0); |
2506 | if (GET_CODE (addr) == UNSPEC) | |
2507 | { | |
2508 | /* Check that the unspec is one of the ones we generate? */ | |
2509 | } | |
2510 | else if (GET_CODE (addr) != PLUS) | |
564d80f4 | 2511 | abort (); |
3b3c6a3f | 2512 | } |
91bb873f RH |
2513 | if (GET_CODE (addr) == PLUS) |
2514 | { | |
2515 | rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1); | |
e9a25f70 | 2516 | |
91bb873f RH |
2517 | /* Check first to see if this is a constant offset from a @GOTOFF |
2518 | symbol reference. */ | |
2519 | if ((GET_CODE (op0) == LABEL_REF | |
2520 | || (GET_CODE (op0) == SYMBOL_REF | |
2521 | && (CONSTANT_POOL_ADDRESS_P (op0) | |
2522 | || SYMBOL_REF_FLAG (op0)))) | |
2523 | && GET_CODE (op1) == CONST_INT) | |
2524 | { | |
2525 | current_function_uses_pic_offset_table = 1; | |
2526 | new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, op0), 7); | |
2527 | new = gen_rtx_PLUS (VOIDmode, new, op1); | |
2528 | new = gen_rtx_CONST (VOIDmode, new); | |
2529 | new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); | |
2530 | ||
2531 | if (reg != 0) | |
2532 | { | |
2533 | emit_move_insn (reg, new); | |
2534 | new = reg; | |
2535 | } | |
2536 | } | |
2537 | else | |
2538 | { | |
2539 | base = legitimize_pic_address (XEXP (addr, 0), reg); | |
2540 | new = legitimize_pic_address (XEXP (addr, 1), | |
2541 | base == reg ? NULL_RTX : reg); | |
2542 | ||
2543 | if (GET_CODE (new) == CONST_INT) | |
2544 | new = plus_constant (base, INTVAL (new)); | |
2545 | else | |
2546 | { | |
2547 | if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1))) | |
2548 | { | |
2549 | base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0)); | |
2550 | new = XEXP (new, 1); | |
2551 | } | |
2552 | new = gen_rtx_PLUS (Pmode, base, new); | |
2553 | } | |
2554 | } | |
2555 | } | |
3b3c6a3f MM |
2556 | } |
2557 | return new; | |
2558 | } | |
2559 | \f | |
3b3c6a3f MM |
2560 | /* Try machine-dependent ways of modifying an illegitimate address |
2561 | to be legitimate. If we find one, return the new, valid address. | |
2562 | This macro is used in only one place: `memory_address' in explow.c. | |
2563 | ||
2564 | OLDX is the address as it was before break_out_memory_refs was called. | |
2565 | In some cases it is useful to look at this to decide what needs to be done. | |
2566 | ||
2567 | MODE and WIN are passed so that this macro can use | |
2568 | GO_IF_LEGITIMATE_ADDRESS. | |
2569 | ||
2570 | It is always safe for this macro to do nothing. It exists to recognize | |
2571 | opportunities to optimize the output. | |
2572 | ||
2573 | For the 80386, we handle X+REG by loading X into a register R and | |
2574 | using R+REG. R will go in a general reg and indexing will be used. | |
2575 | However, if REG is a broken-out memory address or multiplication, | |
2576 | nothing needs to be done because REG can certainly go in a general reg. | |
2577 | ||
2578 | When -fpic is used, special handling is needed for symbolic references. | |
2579 | See comments by legitimize_pic_address in i386.c for details. */ | |
2580 | ||
2581 | rtx | |
2582 | legitimize_address (x, oldx, mode) | |
2583 | register rtx x; | |
bb5177ac | 2584 | register rtx oldx ATTRIBUTE_UNUSED; |
3b3c6a3f MM |
2585 | enum machine_mode mode; |
2586 | { | |
2587 | int changed = 0; | |
2588 | unsigned log; | |
2589 | ||
2590 | if (TARGET_DEBUG_ADDR) | |
2591 | { | |
e9a25f70 JL |
2592 | fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", |
2593 | GET_MODE_NAME (mode)); | |
3b3c6a3f MM |
2594 | debug_rtx (x); |
2595 | } | |
2596 | ||
2597 | if (flag_pic && SYMBOLIC_CONST (x)) | |
2598 | return legitimize_pic_address (x, 0); | |
2599 | ||
2600 | /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ | |
2601 | if (GET_CODE (x) == ASHIFT | |
2602 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2603 | && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4) | |
2604 | { | |
2605 | changed = 1; | |
a269a03c JC |
2606 | x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)), |
2607 | GEN_INT (1 << log)); | |
3b3c6a3f MM |
2608 | } |
2609 | ||
2610 | if (GET_CODE (x) == PLUS) | |
2611 | { | |
e9a25f70 JL |
2612 | /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */ |
2613 | ||
3b3c6a3f MM |
2614 | if (GET_CODE (XEXP (x, 0)) == ASHIFT |
2615 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2616 | && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4) | |
2617 | { | |
2618 | changed = 1; | |
c5c76735 JL |
2619 | XEXP (x, 0) = gen_rtx_MULT (Pmode, |
2620 | force_reg (Pmode, XEXP (XEXP (x, 0), 0)), | |
2621 | GEN_INT (1 << log)); | |
3b3c6a3f MM |
2622 | } |
2623 | ||
2624 | if (GET_CODE (XEXP (x, 1)) == ASHIFT | |
2625 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
2626 | && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4) | |
2627 | { | |
2628 | changed = 1; | |
c5c76735 JL |
2629 | XEXP (x, 1) = gen_rtx_MULT (Pmode, |
2630 | force_reg (Pmode, XEXP (XEXP (x, 1), 0)), | |
2631 | GEN_INT (1 << log)); | |
3b3c6a3f MM |
2632 | } |
2633 | ||
e9a25f70 | 2634 | /* Put multiply first if it isn't already. */ |
3b3c6a3f MM |
2635 | if (GET_CODE (XEXP (x, 1)) == MULT) |
2636 | { | |
2637 | rtx tmp = XEXP (x, 0); | |
2638 | XEXP (x, 0) = XEXP (x, 1); | |
2639 | XEXP (x, 1) = tmp; | |
2640 | changed = 1; | |
2641 | } | |
2642 | ||
2643 | /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) | |
2644 | into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be | |
2645 | created by virtual register instantiation, register elimination, and | |
2646 | similar optimizations. */ | |
2647 | if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS) | |
2648 | { | |
2649 | changed = 1; | |
c5c76735 JL |
2650 | x = gen_rtx_PLUS (Pmode, |
2651 | gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
2652 | XEXP (XEXP (x, 1), 0)), | |
2653 | XEXP (XEXP (x, 1), 1)); | |
3b3c6a3f MM |
2654 | } |
2655 | ||
e9a25f70 JL |
2656 | /* Canonicalize |
2657 | (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) | |
3b3c6a3f MM |
2658 | into (plus (plus (mult (reg) (const)) (reg)) (const)). */ |
2659 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS | |
2660 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
2661 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS | |
2662 | && CONSTANT_P (XEXP (x, 1))) | |
2663 | { | |
00c79232 ML |
2664 | rtx constant; |
2665 | rtx other = NULL_RTX; | |
3b3c6a3f MM |
2666 | |
2667 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2668 | { | |
2669 | constant = XEXP (x, 1); | |
2670 | other = XEXP (XEXP (XEXP (x, 0), 1), 1); | |
2671 | } | |
2672 | else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) | |
2673 | { | |
2674 | constant = XEXP (XEXP (XEXP (x, 0), 1), 1); | |
2675 | other = XEXP (x, 1); | |
2676 | } | |
2677 | else | |
2678 | constant = 0; | |
2679 | ||
2680 | if (constant) | |
2681 | { | |
2682 | changed = 1; | |
c5c76735 JL |
2683 | x = gen_rtx_PLUS (Pmode, |
2684 | gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0), | |
2685 | XEXP (XEXP (XEXP (x, 0), 1), 0)), | |
2686 | plus_constant (other, INTVAL (constant))); | |
3b3c6a3f MM |
2687 | } |
2688 | } | |
2689 | ||
2690 | if (changed && legitimate_address_p (mode, x, FALSE)) | |
2691 | return x; | |
2692 | ||
2693 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
2694 | { | |
2695 | changed = 1; | |
2696 | XEXP (x, 0) = force_operand (XEXP (x, 0), 0); | |
2697 | } | |
2698 | ||
2699 | if (GET_CODE (XEXP (x, 1)) == MULT) | |
2700 | { | |
2701 | changed = 1; | |
2702 | XEXP (x, 1) = force_operand (XEXP (x, 1), 0); | |
2703 | } | |
2704 | ||
2705 | if (changed | |
2706 | && GET_CODE (XEXP (x, 1)) == REG | |
2707 | && GET_CODE (XEXP (x, 0)) == REG) | |
2708 | return x; | |
2709 | ||
2710 | if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1))) | |
2711 | { | |
2712 | changed = 1; | |
2713 | x = legitimize_pic_address (x, 0); | |
2714 | } | |
2715 | ||
2716 | if (changed && legitimate_address_p (mode, x, FALSE)) | |
2717 | return x; | |
2718 | ||
2719 | if (GET_CODE (XEXP (x, 0)) == REG) | |
2720 | { | |
2721 | register rtx temp = gen_reg_rtx (Pmode); | |
2722 | register rtx val = force_operand (XEXP (x, 1), temp); | |
2723 | if (val != temp) | |
2724 | emit_move_insn (temp, val); | |
2725 | ||
2726 | XEXP (x, 1) = temp; | |
2727 | return x; | |
2728 | } | |
2729 | ||
2730 | else if (GET_CODE (XEXP (x, 1)) == REG) | |
2731 | { | |
2732 | register rtx temp = gen_reg_rtx (Pmode); | |
2733 | register rtx val = force_operand (XEXP (x, 0), temp); | |
2734 | if (val != temp) | |
2735 | emit_move_insn (temp, val); | |
2736 | ||
2737 | XEXP (x, 0) = temp; | |
2738 | return x; | |
2739 | } | |
2740 | } | |
2741 | ||
2742 | return x; | |
2743 | } | |
2a2ab3f9 JVA |
2744 | \f |
2745 | /* Print an integer constant expression in assembler syntax. Addition | |
2746 | and subtraction are the only arithmetic that may appear in these | |
2747 | expressions. FILE is the stdio stream to write to, X is the rtx, and | |
2748 | CODE is the operand print code from the output string. */ | |
2749 | ||
2750 | static void | |
2751 | output_pic_addr_const (file, x, code) | |
2752 | FILE *file; | |
2753 | rtx x; | |
2754 | int code; | |
2755 | { | |
2756 | char buf[256]; | |
2757 | ||
2758 | switch (GET_CODE (x)) | |
2759 | { | |
2760 | case PC: | |
2761 | if (flag_pic) | |
2762 | putc ('.', file); | |
2763 | else | |
2764 | abort (); | |
2765 | break; | |
2766 | ||
2767 | case SYMBOL_REF: | |
91bb873f RH |
2768 | assemble_name (file, XSTR (x, 0)); |
2769 | if (code == 'P' && ! SYMBOL_REF_FLAG (x)) | |
2770 | fputs ("@PLT", file); | |
2a2ab3f9 JVA |
2771 | break; |
2772 | ||
91bb873f RH |
2773 | case LABEL_REF: |
2774 | x = XEXP (x, 0); | |
2775 | /* FALLTHRU */ | |
2a2ab3f9 JVA |
2776 | case CODE_LABEL: |
2777 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); | |
2778 | assemble_name (asm_out_file, buf); | |
2779 | break; | |
2780 | ||
2781 | case CONST_INT: | |
f64cecad | 2782 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); |
2a2ab3f9 JVA |
2783 | break; |
2784 | ||
2785 | case CONST: | |
2786 | /* This used to output parentheses around the expression, | |
2787 | but that does not work on the 386 (either ATT or BSD assembler). */ | |
2788 | output_pic_addr_const (file, XEXP (x, 0), code); | |
2789 | break; | |
2790 | ||
2791 | case CONST_DOUBLE: | |
2792 | if (GET_MODE (x) == VOIDmode) | |
2793 | { | |
2794 | /* We can use %d if the number is <32 bits and positive. */ | |
2795 | if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) | |
f64cecad JC |
2796 | fprintf (file, "0x%lx%08lx", |
2797 | (unsigned long) CONST_DOUBLE_HIGH (x), | |
2798 | (unsigned long) CONST_DOUBLE_LOW (x)); | |
2a2ab3f9 | 2799 | else |
f64cecad | 2800 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x)); |
2a2ab3f9 JVA |
2801 | } |
2802 | else | |
2803 | /* We can't handle floating point constants; | |
2804 | PRINT_OPERAND must handle them. */ | |
2805 | output_operand_lossage ("floating constant misused"); | |
2806 | break; | |
2807 | ||
2808 | case PLUS: | |
e9a25f70 | 2809 | /* Some assemblers need integer constants to appear first. */ |
2a2ab3f9 JVA |
2810 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
2811 | { | |
2a2ab3f9 | 2812 | output_pic_addr_const (file, XEXP (x, 0), code); |
e075ae69 | 2813 | putc ('+', file); |
e9a25f70 | 2814 | output_pic_addr_const (file, XEXP (x, 1), code); |
2a2ab3f9 | 2815 | } |
91bb873f | 2816 | else if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
2a2ab3f9 | 2817 | { |
2a2ab3f9 | 2818 | output_pic_addr_const (file, XEXP (x, 1), code); |
e075ae69 | 2819 | putc ('+', file); |
e9a25f70 | 2820 | output_pic_addr_const (file, XEXP (x, 0), code); |
2a2ab3f9 | 2821 | } |
91bb873f RH |
2822 | else |
2823 | abort (); | |
2a2ab3f9 JVA |
2824 | break; |
2825 | ||
2826 | case MINUS: | |
e075ae69 | 2827 | putc (ASSEMBLER_DIALECT ? '(' : '[', file); |
2a2ab3f9 | 2828 | output_pic_addr_const (file, XEXP (x, 0), code); |
e075ae69 | 2829 | putc ('-', file); |
2a2ab3f9 | 2830 | output_pic_addr_const (file, XEXP (x, 1), code); |
e075ae69 | 2831 | putc (ASSEMBLER_DIALECT ? ')' : ']', file); |
2a2ab3f9 JVA |
2832 | break; |
2833 | ||
91bb873f RH |
2834 | case UNSPEC: |
2835 | if (XVECLEN (x, 0) != 1) | |
2836 | abort (); | |
2837 | output_pic_addr_const (file, XVECEXP (x, 0, 0), code); | |
2838 | switch (XINT (x, 1)) | |
2839 | { | |
2840 | case 6: | |
2841 | fputs ("@GOT", file); | |
2842 | break; | |
2843 | case 7: | |
2844 | fputs ("@GOTOFF", file); | |
2845 | break; | |
2846 | case 8: | |
2847 | fputs ("@PLT", file); | |
2848 | break; | |
2849 | default: | |
2850 | output_operand_lossage ("invalid UNSPEC as operand"); | |
2851 | break; | |
2852 | } | |
2853 | break; | |
2854 | ||
2a2ab3f9 JVA |
2855 | default: |
2856 | output_operand_lossage ("invalid expression as operand"); | |
2857 | } | |
2858 | } | |
1865dbb5 JM |
2859 | |
2860 | /* This is called from dwarfout.c via ASM_OUTPUT_DWARF_ADDR_CONST. | |
2861 | We need to handle our special PIC relocations. */ | |
2862 | ||
2863 | void | |
2864 | i386_dwarf_output_addr_const (file, x) | |
2865 | FILE *file; | |
2866 | rtx x; | |
2867 | { | |
2868 | fprintf (file, "\t%s\t", INT_ASM_OP); | |
2869 | if (flag_pic) | |
2870 | output_pic_addr_const (file, x, '\0'); | |
2871 | else | |
2872 | output_addr_const (file, x); | |
2873 | fputc ('\n', file); | |
2874 | } | |
2875 | ||
2876 | /* In the name of slightly smaller debug output, and to cater to | |
2877 | general assembler losage, recognize PIC+GOTOFF and turn it back | |
2878 | into a direct symbol reference. */ | |
2879 | ||
2880 | rtx | |
2881 | i386_simplify_dwarf_addr (orig_x) | |
2882 | rtx orig_x; | |
2883 | { | |
2884 | rtx x = orig_x; | |
2885 | ||
2886 | if (GET_CODE (x) != PLUS | |
2887 | || GET_CODE (XEXP (x, 0)) != REG | |
2888 | || GET_CODE (XEXP (x, 1)) != CONST) | |
2889 | return orig_x; | |
2890 | ||
2891 | x = XEXP (XEXP (x, 1), 0); | |
2892 | if (GET_CODE (x) == UNSPEC | |
2893 | && XINT (x, 1) == 7) | |
2894 | return XVECEXP (x, 0, 0); | |
2895 | ||
2896 | if (GET_CODE (x) == PLUS | |
2897 | && GET_CODE (XEXP (x, 0)) == UNSPEC | |
2898 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2899 | && XINT (XEXP (x, 0), 1) == 7) | |
2900 | return gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1)); | |
2901 | ||
2902 | return orig_x; | |
2903 | } | |
2a2ab3f9 | 2904 | \f |
a269a03c | 2905 | static void |
e075ae69 | 2906 | put_condition_code (code, mode, reverse, fp, file) |
a269a03c | 2907 | enum rtx_code code; |
e075ae69 RH |
2908 | enum machine_mode mode; |
2909 | int reverse, fp; | |
a269a03c JC |
2910 | FILE *file; |
2911 | { | |
a269a03c JC |
2912 | const char *suffix; |
2913 | ||
a269a03c JC |
2914 | if (reverse) |
2915 | code = reverse_condition (code); | |
e075ae69 | 2916 | |
a269a03c JC |
2917 | switch (code) |
2918 | { | |
2919 | case EQ: | |
2920 | suffix = "e"; | |
2921 | break; | |
a269a03c JC |
2922 | case NE: |
2923 | suffix = "ne"; | |
2924 | break; | |
a269a03c | 2925 | case GT: |
e075ae69 RH |
2926 | if (mode == CCNOmode) |
2927 | abort (); | |
2928 | suffix = "g"; | |
a269a03c | 2929 | break; |
a269a03c | 2930 | case GTU: |
e075ae69 RH |
2931 | /* ??? Use "nbe" instead of "a" for fcmov losage on some assemblers. |
2932 | Those same assemblers have the same but opposite losage on cmov. */ | |
2933 | suffix = fp ? "nbe" : "a"; | |
a269a03c | 2934 | break; |
a269a03c | 2935 | case LT: |
e075ae69 | 2936 | if (mode == CCNOmode) |
a269a03c JC |
2937 | suffix = "s"; |
2938 | else | |
e075ae69 | 2939 | suffix = "l"; |
a269a03c | 2940 | break; |
a269a03c JC |
2941 | case LTU: |
2942 | suffix = "b"; | |
2943 | break; | |
a269a03c | 2944 | case GE: |
e075ae69 | 2945 | if (mode == CCNOmode) |
a269a03c JC |
2946 | suffix = "ns"; |
2947 | else | |
e075ae69 | 2948 | suffix = "ge"; |
a269a03c | 2949 | break; |
a269a03c | 2950 | case GEU: |
e075ae69 RH |
2951 | /* ??? As above. */ |
2952 | suffix = fp ? "nb" : "ae"; | |
a269a03c | 2953 | break; |
a269a03c | 2954 | case LE: |
e075ae69 RH |
2955 | if (mode == CCNOmode) |
2956 | abort (); | |
2957 | suffix = "le"; | |
a269a03c | 2958 | break; |
a269a03c JC |
2959 | case LEU: |
2960 | suffix = "be"; | |
2961 | break; | |
a269a03c JC |
2962 | default: |
2963 | abort (); | |
2964 | } | |
2965 | fputs (suffix, file); | |
2966 | } | |
2967 | ||
e075ae69 RH |
2968 | void |
2969 | print_reg (x, code, file) | |
2970 | rtx x; | |
2971 | int code; | |
2972 | FILE *file; | |
e5cb57e8 | 2973 | { |
e075ae69 | 2974 | if (REGNO (x) == ARG_POINTER_REGNUM |
564d80f4 | 2975 | || REGNO (x) == FRAME_POINTER_REGNUM |
e075ae69 RH |
2976 | || REGNO (x) == FLAGS_REG |
2977 | || REGNO (x) == FPSR_REG) | |
2978 | abort (); | |
e9a25f70 | 2979 | |
e075ae69 RH |
2980 | if (ASSEMBLER_DIALECT == 0 || USER_LABEL_PREFIX[0] == 0) |
2981 | putc ('%', file); | |
2982 | ||
2983 | if (code == 'w') | |
2984 | code = 2; | |
2985 | else if (code == 'b') | |
2986 | code = 1; | |
2987 | else if (code == 'k') | |
2988 | code = 4; | |
2989 | else if (code == 'y') | |
2990 | code = 3; | |
2991 | else if (code == 'h') | |
2992 | code = 0; | |
2993 | else | |
2994 | code = GET_MODE_SIZE (GET_MODE (x)); | |
e9a25f70 | 2995 | |
e075ae69 RH |
2996 | switch (code) |
2997 | { | |
2998 | case 3: | |
2999 | if (STACK_TOP_P (x)) | |
3000 | { | |
3001 | fputs ("st(0)", file); | |
3002 | break; | |
3003 | } | |
3004 | /* FALLTHRU */ | |
3005 | case 4: | |
3006 | case 8: | |
3007 | case 12: | |
3008 | if (! FP_REG_P (x)) | |
3009 | putc ('e', file); | |
3010 | /* FALLTHRU */ | |
3011 | case 2: | |
3012 | fputs (hi_reg_name[REGNO (x)], file); | |
3013 | break; | |
3014 | case 1: | |
3015 | fputs (qi_reg_name[REGNO (x)], file); | |
3016 | break; | |
3017 | case 0: | |
3018 | fputs (qi_high_reg_name[REGNO (x)], file); | |
3019 | break; | |
3020 | default: | |
3021 | abort (); | |
fe25fea3 | 3022 | } |
e5cb57e8 SC |
3023 | } |
3024 | ||
2a2ab3f9 | 3025 | /* Meaning of CODE: |
fe25fea3 | 3026 | L,W,B,Q,S,T -- print the opcode suffix for specified size of operand. |
e5cb57e8 | 3027 | C -- print opcode suffix for set/cmov insn. |
fe25fea3 | 3028 | c -- like C, but print reversed condition |
2a2ab3f9 JVA |
3029 | R -- print the prefix for register names. |
3030 | z -- print the opcode suffix for the size of the current operand. | |
3031 | * -- print a star (in certain assembler syntax) | |
3032 | w -- print the operand as if it's a "word" (HImode) even if it isn't. | |
2d49677f SC |
3033 | s -- print a shift double count, followed by the assemblers argument |
3034 | delimiter. | |
fe25fea3 SC |
3035 | b -- print the QImode name of the register for the indicated operand. |
3036 | %b0 would print %al if operands[0] is reg 0. | |
3037 | w -- likewise, print the HImode name of the register. | |
3038 | k -- likewise, print the SImode name of the register. | |
3039 | h -- print the QImode name for a "high" register, either ah, bh, ch or dh. | |
e075ae69 | 3040 | y -- print "st(0)" instead of "st" as a register. */ |
2a2ab3f9 JVA |
3041 | |
3042 | void | |
3043 | print_operand (file, x, code) | |
3044 | FILE *file; | |
3045 | rtx x; | |
3046 | int code; | |
3047 | { | |
3048 | if (code) | |
3049 | { | |
3050 | switch (code) | |
3051 | { | |
3052 | case '*': | |
e075ae69 | 3053 | if (ASSEMBLER_DIALECT == 0) |
2a2ab3f9 JVA |
3054 | putc ('*', file); |
3055 | return; | |
3056 | ||
2a2ab3f9 | 3057 | case 'L': |
e075ae69 RH |
3058 | if (ASSEMBLER_DIALECT == 0) |
3059 | putc ('l', file); | |
2a2ab3f9 JVA |
3060 | return; |
3061 | ||
3062 | case 'W': | |
e075ae69 RH |
3063 | if (ASSEMBLER_DIALECT == 0) |
3064 | putc ('w', file); | |
2a2ab3f9 JVA |
3065 | return; |
3066 | ||
3067 | case 'B': | |
e075ae69 RH |
3068 | if (ASSEMBLER_DIALECT == 0) |
3069 | putc ('b', file); | |
2a2ab3f9 JVA |
3070 | return; |
3071 | ||
3072 | case 'Q': | |
e075ae69 RH |
3073 | if (ASSEMBLER_DIALECT == 0) |
3074 | putc ('l', file); | |
2a2ab3f9 JVA |
3075 | return; |
3076 | ||
3077 | case 'S': | |
e075ae69 RH |
3078 | if (ASSEMBLER_DIALECT == 0) |
3079 | putc ('s', file); | |
2a2ab3f9 JVA |
3080 | return; |
3081 | ||
5f1ec3e6 | 3082 | case 'T': |
e075ae69 RH |
3083 | if (ASSEMBLER_DIALECT == 0) |
3084 | putc ('t', file); | |
5f1ec3e6 JVA |
3085 | return; |
3086 | ||
2a2ab3f9 JVA |
3087 | case 'z': |
3088 | /* 387 opcodes don't get size suffixes if the operands are | |
3089 | registers. */ | |
3090 | ||
3091 | if (STACK_REG_P (x)) | |
3092 | return; | |
3093 | ||
e075ae69 RH |
3094 | /* Intel syntax has no truck with instruction suffixes. */ |
3095 | if (ASSEMBLER_DIALECT != 0) | |
3096 | return; | |
3097 | ||
2a2ab3f9 JVA |
3098 | /* this is the size of op from size of operand */ |
3099 | switch (GET_MODE_SIZE (GET_MODE (x))) | |
3100 | { | |
e075ae69 RH |
3101 | case 1: |
3102 | putc ('b', file); | |
3103 | return; | |
3104 | ||
2a2ab3f9 | 3105 | case 2: |
e075ae69 | 3106 | putc ('w', file); |
2a2ab3f9 JVA |
3107 | return; |
3108 | ||
3109 | case 4: | |
3110 | if (GET_MODE (x) == SFmode) | |
3111 | { | |
e075ae69 | 3112 | putc ('s', file); |
2a2ab3f9 JVA |
3113 | return; |
3114 | } | |
3115 | else | |
e075ae69 | 3116 | putc ('l', file); |
2a2ab3f9 JVA |
3117 | return; |
3118 | ||
5f1ec3e6 | 3119 | case 12: |
e075ae69 RH |
3120 | putc ('t', file); |
3121 | return; | |
5f1ec3e6 | 3122 | |
2a2ab3f9 JVA |
3123 | case 8: |
3124 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) | |
56c0e8fa JVA |
3125 | { |
3126 | #ifdef GAS_MNEMONICS | |
e075ae69 | 3127 | putc ('q', file); |
56c0e8fa | 3128 | #else |
e075ae69 RH |
3129 | putc ('l', file); |
3130 | putc ('l', file); | |
56c0e8fa JVA |
3131 | #endif |
3132 | } | |
e075ae69 RH |
3133 | else |
3134 | putc ('l', file); | |
2a2ab3f9 JVA |
3135 | return; |
3136 | } | |
4af3895e JVA |
3137 | |
3138 | case 'b': | |
3139 | case 'w': | |
3140 | case 'k': | |
3141 | case 'h': | |
3142 | case 'y': | |
5cb6195d | 3143 | case 'X': |
e075ae69 | 3144 | case 'P': |
4af3895e JVA |
3145 | break; |
3146 | ||
2d49677f SC |
3147 | case 's': |
3148 | if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT) | |
3149 | { | |
3150 | PRINT_OPERAND (file, x, 0); | |
e075ae69 | 3151 | putc (',', file); |
2d49677f | 3152 | } |
a269a03c JC |
3153 | return; |
3154 | ||
1853aadd | 3155 | case 'C': |
e075ae69 | 3156 | put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file); |
1853aadd | 3157 | return; |
fe25fea3 | 3158 | case 'F': |
e075ae69 | 3159 | put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file); |
fe25fea3 SC |
3160 | return; |
3161 | ||
e9a25f70 | 3162 | /* Like above, but reverse condition */ |
e075ae69 RH |
3163 | case 'c': |
3164 | put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file); | |
3165 | return; | |
fe25fea3 | 3166 | case 'f': |
e075ae69 | 3167 | put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file); |
1853aadd | 3168 | return; |
e5cb57e8 | 3169 | |
4af3895e | 3170 | default: |
68daafd4 JVA |
3171 | { |
3172 | char str[50]; | |
68daafd4 JVA |
3173 | sprintf (str, "invalid operand code `%c'", code); |
3174 | output_operand_lossage (str); | |
3175 | } | |
2a2ab3f9 JVA |
3176 | } |
3177 | } | |
e9a25f70 | 3178 | |
2a2ab3f9 JVA |
3179 | if (GET_CODE (x) == REG) |
3180 | { | |
3181 | PRINT_REG (x, code, file); | |
3182 | } | |
e9a25f70 | 3183 | |
2a2ab3f9 JVA |
3184 | else if (GET_CODE (x) == MEM) |
3185 | { | |
e075ae69 RH |
3186 | /* No `byte ptr' prefix for call instructions. */ |
3187 | if (ASSEMBLER_DIALECT != 0 && code != 'X' && code != 'P') | |
2a2ab3f9 | 3188 | { |
69ddee61 | 3189 | const char * size; |
e075ae69 RH |
3190 | switch (GET_MODE_SIZE (GET_MODE (x))) |
3191 | { | |
3192 | case 1: size = "BYTE"; break; | |
3193 | case 2: size = "WORD"; break; | |
3194 | case 4: size = "DWORD"; break; | |
3195 | case 8: size = "QWORD"; break; | |
3196 | case 12: size = "XWORD"; break; | |
3197 | default: | |
564d80f4 | 3198 | abort (); |
e075ae69 RH |
3199 | } |
3200 | fputs (size, file); | |
3201 | fputs (" PTR ", file); | |
2a2ab3f9 | 3202 | } |
e075ae69 RH |
3203 | |
3204 | x = XEXP (x, 0); | |
3205 | if (flag_pic && CONSTANT_ADDRESS_P (x)) | |
3206 | output_pic_addr_const (file, x, code); | |
2a2ab3f9 | 3207 | else |
e075ae69 | 3208 | output_address (x); |
2a2ab3f9 | 3209 | } |
e9a25f70 | 3210 | |
2a2ab3f9 JVA |
3211 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
3212 | { | |
e9a25f70 JL |
3213 | REAL_VALUE_TYPE r; |
3214 | long l; | |
3215 | ||
5f1ec3e6 JVA |
3216 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
3217 | REAL_VALUE_TO_TARGET_SINGLE (r, l); | |
e075ae69 RH |
3218 | |
3219 | if (ASSEMBLER_DIALECT == 0) | |
3220 | putc ('$', file); | |
52267fcb | 3221 | fprintf (file, "0x%lx", l); |
5f1ec3e6 | 3222 | } |
e9a25f70 | 3223 | |
5f1ec3e6 JVA |
3224 | /* These float cases don't actually occur as immediate operands. */ |
3225 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
3226 | { | |
e9a25f70 JL |
3227 | REAL_VALUE_TYPE r; |
3228 | char dstr[30]; | |
3229 | ||
5f1ec3e6 JVA |
3230 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
3231 | REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); | |
3232 | fprintf (file, "%s", dstr); | |
2a2ab3f9 | 3233 | } |
e9a25f70 | 3234 | |
5f1ec3e6 | 3235 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode) |
2a2ab3f9 | 3236 | { |
e9a25f70 JL |
3237 | REAL_VALUE_TYPE r; |
3238 | char dstr[30]; | |
3239 | ||
5f1ec3e6 JVA |
3240 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
3241 | REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); | |
3242 | fprintf (file, "%s", dstr); | |
2a2ab3f9 | 3243 | } |
79325812 | 3244 | else |
2a2ab3f9 | 3245 | { |
4af3895e | 3246 | if (code != 'P') |
2a2ab3f9 | 3247 | { |
695dac07 | 3248 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
e075ae69 RH |
3249 | { |
3250 | if (ASSEMBLER_DIALECT == 0) | |
3251 | putc ('$', file); | |
3252 | } | |
2a2ab3f9 JVA |
3253 | else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF |
3254 | || GET_CODE (x) == LABEL_REF) | |
e075ae69 RH |
3255 | { |
3256 | if (ASSEMBLER_DIALECT == 0) | |
3257 | putc ('$', file); | |
3258 | else | |
3259 | fputs ("OFFSET FLAT:", file); | |
3260 | } | |
2a2ab3f9 | 3261 | } |
e075ae69 RH |
3262 | if (GET_CODE (x) == CONST_INT) |
3263 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
3264 | else if (flag_pic) | |
2a2ab3f9 JVA |
3265 | output_pic_addr_const (file, x, code); |
3266 | else | |
3267 | output_addr_const (file, x); | |
3268 | } | |
3269 | } | |
3270 | \f | |
3271 | /* Print a memory operand whose address is ADDR. */ | |
3272 | ||
3273 | void | |
3274 | print_operand_address (file, addr) | |
3275 | FILE *file; | |
3276 | register rtx addr; | |
3277 | { | |
e075ae69 RH |
3278 | struct ix86_address parts; |
3279 | rtx base, index, disp; | |
3280 | int scale; | |
e9a25f70 | 3281 | |
e075ae69 RH |
3282 | if (! ix86_decompose_address (addr, &parts)) |
3283 | abort (); | |
e9a25f70 | 3284 | |
e075ae69 RH |
3285 | base = parts.base; |
3286 | index = parts.index; | |
3287 | disp = parts.disp; | |
3288 | scale = parts.scale; | |
e9a25f70 | 3289 | |
e075ae69 RH |
3290 | if (!base && !index) |
3291 | { | |
3292 | /* Displacement only requires special attention. */ | |
e9a25f70 | 3293 | |
e075ae69 | 3294 | if (GET_CODE (disp) == CONST_INT) |
2a2ab3f9 | 3295 | { |
e075ae69 RH |
3296 | if (ASSEMBLER_DIALECT != 0) |
3297 | fputs ("ds:", file); | |
3298 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); | |
2a2ab3f9 | 3299 | } |
e075ae69 RH |
3300 | else if (flag_pic) |
3301 | output_pic_addr_const (file, addr, 0); | |
3302 | else | |
3303 | output_addr_const (file, addr); | |
3304 | } | |
3305 | else | |
3306 | { | |
3307 | if (ASSEMBLER_DIALECT == 0) | |
2a2ab3f9 | 3308 | { |
e075ae69 | 3309 | if (disp) |
2a2ab3f9 | 3310 | { |
c399861d | 3311 | if (flag_pic) |
e075ae69 RH |
3312 | output_pic_addr_const (file, disp, 0); |
3313 | else if (GET_CODE (disp) == LABEL_REF) | |
3314 | output_asm_label (disp); | |
2a2ab3f9 | 3315 | else |
e075ae69 | 3316 | output_addr_const (file, disp); |
2a2ab3f9 JVA |
3317 | } |
3318 | ||
e075ae69 RH |
3319 | putc ('(', file); |
3320 | if (base) | |
3321 | PRINT_REG (base, 0, file); | |
3322 | if (index) | |
2a2ab3f9 | 3323 | { |
e075ae69 RH |
3324 | putc (',', file); |
3325 | PRINT_REG (index, 0, file); | |
3326 | if (scale != 1) | |
3327 | fprintf (file, ",%d", scale); | |
2a2ab3f9 | 3328 | } |
e075ae69 | 3329 | putc (')', file); |
2a2ab3f9 | 3330 | } |
2a2ab3f9 JVA |
3331 | else |
3332 | { | |
e075ae69 | 3333 | rtx offset = NULL_RTX; |
e9a25f70 | 3334 | |
e075ae69 RH |
3335 | if (disp) |
3336 | { | |
3337 | /* Pull out the offset of a symbol; print any symbol itself. */ | |
3338 | if (GET_CODE (disp) == CONST | |
3339 | && GET_CODE (XEXP (disp, 0)) == PLUS | |
3340 | && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT) | |
3341 | { | |
3342 | offset = XEXP (XEXP (disp, 0), 1); | |
3343 | disp = gen_rtx_CONST (VOIDmode, | |
3344 | XEXP (XEXP (disp, 0), 0)); | |
3345 | } | |
ce193852 | 3346 | |
e075ae69 RH |
3347 | if (flag_pic) |
3348 | output_pic_addr_const (file, disp, 0); | |
3349 | else if (GET_CODE (disp) == LABEL_REF) | |
3350 | output_asm_label (disp); | |
3351 | else if (GET_CODE (disp) == CONST_INT) | |
3352 | offset = disp; | |
3353 | else | |
3354 | output_addr_const (file, disp); | |
3355 | } | |
e9a25f70 | 3356 | |
e075ae69 RH |
3357 | putc ('[', file); |
3358 | if (base) | |
a8620236 | 3359 | { |
e075ae69 RH |
3360 | PRINT_REG (base, 0, file); |
3361 | if (offset) | |
3362 | { | |
3363 | if (INTVAL (offset) >= 0) | |
3364 | putc ('+', file); | |
3365 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset)); | |
3366 | } | |
a8620236 | 3367 | } |
e075ae69 RH |
3368 | else if (offset) |
3369 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset)); | |
2247a58c | 3370 | else |
e075ae69 | 3371 | putc ('0', file); |
e9a25f70 | 3372 | |
e075ae69 RH |
3373 | if (index) |
3374 | { | |
3375 | putc ('+', file); | |
3376 | PRINT_REG (index, 0, file); | |
3377 | if (scale != 1) | |
3378 | fprintf (file, "*%d", scale); | |
3379 | } | |
3380 | putc (']', file); | |
3381 | } | |
2a2ab3f9 JVA |
3382 | } |
3383 | } | |
3384 | \f | |
3385 | /* Split one or more DImode RTL references into pairs of SImode | |
3386 | references. The RTL can be REG, offsettable MEM, integer constant, or | |
3387 | CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to | |
3388 | split and "num" is its length. lo_half and hi_half are output arrays | |
3389 | that parallel "operands". */ | |
3390 | ||
3391 | void | |
3392 | split_di (operands, num, lo_half, hi_half) | |
3393 | rtx operands[]; | |
3394 | int num; | |
3395 | rtx lo_half[], hi_half[]; | |
3396 | { | |
3397 | while (num--) | |
3398 | { | |
57dbca5e | 3399 | rtx op = operands[num]; |
e075ae69 RH |
3400 | if (CONSTANT_P (op)) |
3401 | split_double (op, &lo_half[num], &hi_half[num]); | |
3402 | else if (! reload_completed) | |
a269a03c JC |
3403 | { |
3404 | lo_half[num] = gen_lowpart (SImode, op); | |
3405 | hi_half[num] = gen_highpart (SImode, op); | |
3406 | } | |
3407 | else if (GET_CODE (op) == REG) | |
2a2ab3f9 | 3408 | { |
57dbca5e BS |
3409 | lo_half[num] = gen_rtx_REG (SImode, REGNO (op)); |
3410 | hi_half[num] = gen_rtx_REG (SImode, REGNO (op) + 1); | |
2a2ab3f9 | 3411 | } |
57dbca5e | 3412 | else if (offsettable_memref_p (op)) |
2a2ab3f9 | 3413 | { |
57dbca5e BS |
3414 | rtx lo_addr = XEXP (op, 0); |
3415 | rtx hi_addr = XEXP (adj_offsettable_operand (op, 4), 0); | |
3416 | lo_half[num] = change_address (op, SImode, lo_addr); | |
3417 | hi_half[num] = change_address (op, SImode, hi_addr); | |
2a2ab3f9 JVA |
3418 | } |
3419 | else | |
564d80f4 | 3420 | abort (); |
2a2ab3f9 JVA |
3421 | } |
3422 | } | |
3423 | \f | |
2a2ab3f9 JVA |
3424 | /* Output code to perform a 387 binary operation in INSN, one of PLUS, |
3425 | MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] | |
3426 | is the expression of the binary operation. The output may either be | |
3427 | emitted here, or returned to the caller, like all output_* functions. | |
3428 | ||
3429 | There is no guarantee that the operands are the same mode, as they | |
3430 | might be within FLOAT or FLOAT_EXTEND expressions. */ | |
3431 | ||
69ddee61 | 3432 | const char * |
2a2ab3f9 JVA |
3433 | output_387_binary_op (insn, operands) |
3434 | rtx insn; | |
3435 | rtx *operands; | |
3436 | { | |
2a2ab3f9 | 3437 | static char buf[100]; |
e075ae69 | 3438 | rtx temp; |
69ddee61 | 3439 | const char *p; |
2a2ab3f9 JVA |
3440 | |
3441 | switch (GET_CODE (operands[3])) | |
3442 | { | |
3443 | case PLUS: | |
e075ae69 RH |
3444 | if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT |
3445 | || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) | |
3446 | p = "fiadd"; | |
3447 | else | |
3448 | p = "fadd"; | |
2a2ab3f9 JVA |
3449 | break; |
3450 | ||
3451 | case MINUS: | |
e075ae69 RH |
3452 | if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT |
3453 | || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) | |
3454 | p = "fisub"; | |
3455 | else | |
3456 | p = "fsub"; | |
2a2ab3f9 JVA |
3457 | break; |
3458 | ||
3459 | case MULT: | |
e075ae69 RH |
3460 | if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT |
3461 | || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) | |
3462 | p = "fimul"; | |
3463 | else | |
3464 | p = "fmul"; | |
2a2ab3f9 JVA |
3465 | break; |
3466 | ||
3467 | case DIV: | |
e075ae69 RH |
3468 | if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT |
3469 | || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) | |
3470 | p = "fidiv"; | |
3471 | else | |
3472 | p = "fdiv"; | |
2a2ab3f9 JVA |
3473 | break; |
3474 | ||
3475 | default: | |
3476 | abort (); | |
3477 | } | |
3478 | ||
e075ae69 | 3479 | strcpy (buf, p); |
2a2ab3f9 JVA |
3480 | |
3481 | switch (GET_CODE (operands[3])) | |
3482 | { | |
3483 | case MULT: | |
3484 | case PLUS: | |
3485 | if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) | |
3486 | { | |
3487 | temp = operands[2]; | |
3488 | operands[2] = operands[1]; | |
3489 | operands[1] = temp; | |
3490 | } | |
3491 | ||
3492 | if (GET_CODE (operands[2]) == MEM) | |
e075ae69 RH |
3493 | { |
3494 | p = "%z2\t%2"; | |
3495 | break; | |
3496 | } | |
2a2ab3f9 JVA |
3497 | |
3498 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) | |
6b28fd63 JL |
3499 | { |
3500 | if (STACK_TOP_P (operands[0])) | |
e075ae69 | 3501 | p = "p\t{%0,%2|%2, %0}"; |
6b28fd63 | 3502 | else |
e075ae69 RH |
3503 | p = "p\t{%2,%0|%0, %2}"; |
3504 | break; | |
6b28fd63 | 3505 | } |
2a2ab3f9 JVA |
3506 | |
3507 | if (STACK_TOP_P (operands[0])) | |
e075ae69 | 3508 | p = "\t{%y2,%0|%0, %y2}"; |
2a2ab3f9 | 3509 | else |
e075ae69 RH |
3510 | p = "\t{%2,%0|%0, %2}"; |
3511 | break; | |
2a2ab3f9 JVA |
3512 | |
3513 | case MINUS: | |
3514 | case DIV: | |
3515 | if (GET_CODE (operands[1]) == MEM) | |
e075ae69 RH |
3516 | { |
3517 | p = "r%z1\t%1"; | |
3518 | break; | |
3519 | } | |
2a2ab3f9 JVA |
3520 | |
3521 | if (GET_CODE (operands[2]) == MEM) | |
e075ae69 RH |
3522 | { |
3523 | p = "%z2\t%2"; | |
3524 | break; | |
3525 | } | |
2a2ab3f9 | 3526 | |
2a2ab3f9 JVA |
3527 | if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) |
3528 | abort (); | |
3529 | ||
e075ae69 RH |
3530 | /* Note that the Unixware assembler, and the AT&T assembler before |
3531 | that, are confusingly not reversed from Intel syntax in this | |
3532 | area. */ | |
2a2ab3f9 | 3533 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) |
6b28fd63 JL |
3534 | { |
3535 | if (STACK_TOP_P (operands[0])) | |
e075ae69 | 3536 | p = "p\t%0,%2"; |
6b28fd63 | 3537 | else |
e075ae69 RH |
3538 | p = "rp\t%2,%0"; |
3539 | break; | |
6b28fd63 | 3540 | } |
2a2ab3f9 JVA |
3541 | |
3542 | if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) | |
6b28fd63 JL |
3543 | { |
3544 | if (STACK_TOP_P (operands[0])) | |
e075ae69 | 3545 | p = "rp\t%0,%1"; |
6b28fd63 | 3546 | else |
e075ae69 RH |
3547 | p = "p\t%1,%0"; |
3548 | break; | |
6b28fd63 | 3549 | } |
2a2ab3f9 JVA |
3550 | |
3551 | if (STACK_TOP_P (operands[0])) | |
3552 | { | |
3553 | if (STACK_TOP_P (operands[1])) | |
e075ae69 | 3554 | p = "\t%y2,%0"; |
2a2ab3f9 | 3555 | else |
e075ae69 RH |
3556 | p = "r\t%y1,%0"; |
3557 | break; | |
2a2ab3f9 JVA |
3558 | } |
3559 | else if (STACK_TOP_P (operands[1])) | |
e075ae69 | 3560 | p = "\t%1,%0"; |
2a2ab3f9 | 3561 | else |
e075ae69 RH |
3562 | p = "r\t%2,%0"; |
3563 | break; | |
2a2ab3f9 JVA |
3564 | |
3565 | default: | |
3566 | abort (); | |
3567 | } | |
e075ae69 RH |
3568 | |
3569 | strcat (buf, p); | |
3570 | return buf; | |
2a2ab3f9 | 3571 | } |
e075ae69 | 3572 | |
2a2ab3f9 | 3573 | /* Output code for INSN to convert a float to a signed int. OPERANDS |
e075ae69 RH |
3574 | are the insn operands. The output may be [SD]Imode and the input |
3575 | operand may be [SDX]Fmode. */ | |
2a2ab3f9 | 3576 | |
69ddee61 | 3577 | const char * |
2a2ab3f9 JVA |
3578 | output_fix_trunc (insn, operands) |
3579 | rtx insn; | |
3580 | rtx *operands; | |
3581 | { | |
3582 | int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; | |
e075ae69 RH |
3583 | int dimode_p = GET_MODE (operands[0]) == DImode; |
3584 | rtx xops[4]; | |
2a2ab3f9 | 3585 | |
e075ae69 RH |
3586 | /* Jump through a hoop or two for DImode, since the hardware has no |
3587 | non-popping instruction. We used to do this a different way, but | |
3588 | that was somewhat fragile and broke with post-reload splitters. */ | |
a05924f9 JH |
3589 | if (dimode_p && !stack_top_dies) |
3590 | output_asm_insn ("fld\t%y1", operands); | |
e075ae69 RH |
3591 | |
3592 | if (! STACK_TOP_P (operands[1])) | |
10195bd8 JW |
3593 | abort (); |
3594 | ||
e075ae69 RH |
3595 | xops[0] = GEN_INT (12); |
3596 | xops[1] = adj_offsettable_operand (operands[2], 1); | |
3597 | xops[1] = change_address (xops[1], QImode, NULL_RTX); | |
305f097e | 3598 | |
e075ae69 RH |
3599 | xops[2] = operands[0]; |
3600 | if (GET_CODE (operands[0]) != MEM) | |
3601 | xops[2] = operands[3]; | |
2a2ab3f9 | 3602 | |
e075ae69 RH |
3603 | output_asm_insn ("fnstcw\t%2", operands); |
3604 | output_asm_insn ("mov{l}\t{%2, %4|%4, %2}", operands); | |
3605 | output_asm_insn ("mov{b}\t{%0, %1|%1, %0}", xops); | |
3606 | output_asm_insn ("fldcw\t%2", operands); | |
3607 | output_asm_insn ("mov{l}\t{%4, %2|%2, %4}", operands); | |
e9a25f70 | 3608 | |
e075ae69 RH |
3609 | if (stack_top_dies || dimode_p) |
3610 | output_asm_insn ("fistp%z2\t%2", xops); | |
10195bd8 | 3611 | else |
e075ae69 RH |
3612 | output_asm_insn ("fist%z2\t%2", xops); |
3613 | ||
3614 | output_asm_insn ("fldcw\t%2", operands); | |
10195bd8 | 3615 | |
e075ae69 | 3616 | if (GET_CODE (operands[0]) != MEM) |
2a2ab3f9 | 3617 | { |
e075ae69 | 3618 | if (dimode_p) |
2e14a41b | 3619 | { |
e075ae69 RH |
3620 | split_di (operands+0, 1, xops+0, xops+1); |
3621 | split_di (operands+3, 1, xops+2, xops+3); | |
3622 | output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops); | |
3623 | output_asm_insn ("mov{l}\t{%3, %1|%1, %3}", xops); | |
2e14a41b | 3624 | } |
e075ae69 RH |
3625 | else |
3626 | output_asm_insn ("mov{l}\t{%3,%0|%0, %3}", operands); | |
2a2ab3f9 | 3627 | } |
2a2ab3f9 | 3628 | |
e075ae69 | 3629 | return ""; |
2a2ab3f9 | 3630 | } |
cda749b1 | 3631 | |
e075ae69 RH |
3632 | /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi |
3633 | should be used and 2 when fnstsw should be used. UNORDERED_P is true | |
3634 | when fucom should be used. */ | |
3635 | ||
69ddee61 | 3636 | const char * |
e075ae69 | 3637 | output_fp_compare (insn, operands, eflags_p, unordered_p) |
cda749b1 JW |
3638 | rtx insn; |
3639 | rtx *operands; | |
e075ae69 | 3640 | int eflags_p, unordered_p; |
cda749b1 | 3641 | { |
e075ae69 RH |
3642 | int stack_top_dies; |
3643 | rtx cmp_op0 = operands[0]; | |
3644 | rtx cmp_op1 = operands[1]; | |
3645 | ||
3646 | if (eflags_p == 2) | |
3647 | { | |
3648 | cmp_op0 = cmp_op1; | |
3649 | cmp_op1 = operands[2]; | |
3650 | } | |
cda749b1 | 3651 | |
e075ae69 | 3652 | if (! STACK_TOP_P (cmp_op0)) |
cda749b1 JW |
3653 | abort (); |
3654 | ||
e075ae69 | 3655 | stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; |
cda749b1 | 3656 | |
e075ae69 RH |
3657 | if (STACK_REG_P (cmp_op1) |
3658 | && stack_top_dies | |
3659 | && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1)) | |
3660 | && REGNO (cmp_op1) != FIRST_STACK_REG) | |
cda749b1 | 3661 | { |
e075ae69 RH |
3662 | /* If both the top of the 387 stack dies, and the other operand |
3663 | is also a stack register that dies, then this must be a | |
3664 | `fcompp' float compare */ | |
3665 | ||
3666 | if (eflags_p == 1) | |
3667 | { | |
3668 | /* There is no double popping fcomi variant. Fortunately, | |
3669 | eflags is immune from the fstp's cc clobbering. */ | |
3670 | if (unordered_p) | |
3671 | output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands); | |
3672 | else | |
3673 | output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands); | |
3674 | return "fstp\t%y0"; | |
3675 | } | |
3676 | else | |
cda749b1 | 3677 | { |
e075ae69 RH |
3678 | if (eflags_p == 2) |
3679 | { | |
3680 | if (unordered_p) | |
3681 | return "fucompp\n\tfnstsw\t%0"; | |
3682 | else | |
3683 | return "fcompp\n\tfnstsw\t%0"; | |
3684 | } | |
cda749b1 JW |
3685 | else |
3686 | { | |
e075ae69 RH |
3687 | if (unordered_p) |
3688 | return "fucompp"; | |
3689 | else | |
3690 | return "fcompp"; | |
cda749b1 JW |
3691 | } |
3692 | } | |
cda749b1 JW |
3693 | } |
3694 | else | |
3695 | { | |
e075ae69 | 3696 | /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */ |
cda749b1 | 3697 | |
69ddee61 | 3698 | static const char * const alt[24] = |
e075ae69 RH |
3699 | { |
3700 | "fcom%z1\t%y1", | |
3701 | "fcomp%z1\t%y1", | |
3702 | "fucom%z1\t%y1", | |
3703 | "fucomp%z1\t%y1", | |
3704 | ||
3705 | "ficom%z1\t%y1", | |
3706 | "ficomp%z1\t%y1", | |
3707 | NULL, | |
3708 | NULL, | |
3709 | ||
3710 | "fcomi\t{%y1, %0|%0, %y1}", | |
3711 | "fcomip\t{%y1, %0|%0, %y1}", | |
3712 | "fucomi\t{%y1, %0|%0, %y1}", | |
3713 | "fucomip\t{%y1, %0|%0, %y1}", | |
3714 | ||
3715 | NULL, | |
3716 | NULL, | |
3717 | NULL, | |
3718 | NULL, | |
3719 | ||
3720 | "fcom%z2\t%y2\n\tfnstsw\t%0", | |
3721 | "fcomp%z2\t%y2\n\tfnstsw\t%0", | |
3722 | "fucom%z2\t%y2\n\tfnstsw\t%0", | |
3723 | "fucomp%z2\t%y2\n\tfnstsw\t%0", | |
3724 | ||
3725 | "ficom%z2\t%y2\n\tfnstsw\t%0", | |
3726 | "ficomp%z2\t%y2\n\tfnstsw\t%0", | |
3727 | NULL, | |
3728 | NULL | |
3729 | }; | |
3730 | ||
3731 | int mask; | |
69ddee61 | 3732 | const char *ret; |
e075ae69 RH |
3733 | |
3734 | mask = eflags_p << 3; | |
3735 | mask |= (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT) << 2; | |
3736 | mask |= unordered_p << 1; | |
3737 | mask |= stack_top_dies; | |
3738 | ||
3739 | if (mask >= 24) | |
3740 | abort (); | |
3741 | ret = alt[mask]; | |
3742 | if (ret == NULL) | |
3743 | abort (); | |
cda749b1 | 3744 | |
e075ae69 | 3745 | return ret; |
cda749b1 JW |
3746 | } |
3747 | } | |
2a2ab3f9 | 3748 | |
e075ae69 | 3749 | /* Output assembler code to FILE to initialize basic-block profiling. |
2a2ab3f9 | 3750 | |
e075ae69 | 3751 | If profile_block_flag == 2 |
2a2ab3f9 | 3752 | |
e075ae69 RH |
3753 | Output code to call the subroutine `__bb_init_trace_func' |
3754 | and pass two parameters to it. The first parameter is | |
3755 | the address of a block allocated in the object module. | |
3756 | The second parameter is the number of the first basic block | |
3757 | of the function. | |
2a2ab3f9 | 3758 | |
e075ae69 RH |
3759 | The name of the block is a local symbol made with this statement: |
3760 | ||
3761 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
2a2ab3f9 | 3762 | |
e075ae69 RH |
3763 | Of course, since you are writing the definition of |
3764 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
3765 | can take a short cut in the definition of this macro and use the | |
3766 | name that you know will result. | |
2a2ab3f9 | 3767 | |
e075ae69 RH |
3768 | The number of the first basic block of the function is |
3769 | passed to the macro in BLOCK_OR_LABEL. | |
2a2ab3f9 | 3770 | |
e075ae69 RH |
3771 | If described in a virtual assembler language the code to be |
3772 | output looks like: | |
2a2ab3f9 | 3773 | |
e075ae69 RH |
3774 | parameter1 <- LPBX0 |
3775 | parameter2 <- BLOCK_OR_LABEL | |
3776 | call __bb_init_trace_func | |
2a2ab3f9 | 3777 | |
e075ae69 | 3778 | else if profile_block_flag != 0 |
e74389ff | 3779 | |
e075ae69 RH |
3780 | Output code to call the subroutine `__bb_init_func' |
3781 | and pass one single parameter to it, which is the same | |
3782 | as the first parameter to `__bb_init_trace_func'. | |
e74389ff | 3783 | |
e075ae69 RH |
3784 | The first word of this parameter is a flag which will be nonzero if |
3785 | the object module has already been initialized. So test this word | |
3786 | first, and do not call `__bb_init_func' if the flag is nonzero. | |
3787 | Note: When profile_block_flag == 2 the test need not be done | |
3788 | but `__bb_init_trace_func' *must* be called. | |
e74389ff | 3789 | |
e075ae69 RH |
3790 | BLOCK_OR_LABEL may be used to generate a label number as a |
3791 | branch destination in case `__bb_init_func' will not be called. | |
e74389ff | 3792 | |
e075ae69 RH |
3793 | If described in a virtual assembler language the code to be |
3794 | output looks like: | |
2a2ab3f9 | 3795 | |
e075ae69 RH |
3796 | cmp (LPBX0),0 |
3797 | jne local_label | |
3798 | parameter1 <- LPBX0 | |
3799 | call __bb_init_func | |
3800 | local_label: | |
3801 | */ | |
c572e5ba | 3802 | |
e075ae69 RH |
3803 | void |
3804 | ix86_output_function_block_profiler (file, block_or_label) | |
3805 | FILE *file; | |
3806 | int block_or_label; | |
c572e5ba | 3807 | { |
e075ae69 RH |
3808 | static int num_func = 0; |
3809 | rtx xops[8]; | |
3810 | char block_table[80], false_label[80]; | |
c572e5ba | 3811 | |
e075ae69 | 3812 | ASM_GENERATE_INTERNAL_LABEL (block_table, "LPBX", 0); |
e9a25f70 | 3813 | |
e075ae69 RH |
3814 | xops[1] = gen_rtx_SYMBOL_REF (VOIDmode, block_table); |
3815 | xops[5] = stack_pointer_rtx; | |
3816 | xops[7] = gen_rtx_REG (Pmode, 0); /* eax */ | |
2a2ab3f9 | 3817 | |
e075ae69 | 3818 | CONSTANT_POOL_ADDRESS_P (xops[1]) = TRUE; |
c572e5ba | 3819 | |
e075ae69 | 3820 | switch (profile_block_flag) |
c572e5ba | 3821 | { |
e075ae69 RH |
3822 | case 2: |
3823 | xops[2] = GEN_INT (block_or_label); | |
3824 | xops[3] = gen_rtx_MEM (Pmode, | |
3825 | gen_rtx_SYMBOL_REF (VOIDmode, "__bb_init_trace_func")); | |
3826 | xops[6] = GEN_INT (8); | |
e9a25f70 | 3827 | |
e075ae69 RH |
3828 | output_asm_insn ("push{l}\t%2", xops); |
3829 | if (!flag_pic) | |
3830 | output_asm_insn ("push{l}\t%1", xops); | |
e9a25f70 | 3831 | else |
870a0c2c | 3832 | { |
e075ae69 RH |
3833 | output_asm_insn ("lea{l}\t{%a1, %7|%7, %a1}", xops); |
3834 | output_asm_insn ("push{l}\t%7", xops); | |
870a0c2c | 3835 | } |
e075ae69 RH |
3836 | output_asm_insn ("call\t%P3", xops); |
3837 | output_asm_insn ("add{l}\t{%6, %5|%5, %6}", xops); | |
3838 | break; | |
c572e5ba | 3839 | |
e075ae69 RH |
3840 | default: |
3841 | ASM_GENERATE_INTERNAL_LABEL (false_label, "LPBZ", num_func); | |
c572e5ba | 3842 | |
e075ae69 RH |
3843 | xops[0] = const0_rtx; |
3844 | xops[2] = gen_rtx_MEM (Pmode, | |
3845 | gen_rtx_SYMBOL_REF (VOIDmode, false_label)); | |
3846 | xops[3] = gen_rtx_MEM (Pmode, | |
3847 | gen_rtx_SYMBOL_REF (VOIDmode, "__bb_init_func")); | |
3848 | xops[4] = gen_rtx_MEM (Pmode, xops[1]); | |
3849 | xops[6] = GEN_INT (4); | |
a14003ee | 3850 | |
e075ae69 | 3851 | CONSTANT_POOL_ADDRESS_P (xops[2]) = TRUE; |
446ba526 | 3852 | |
e075ae69 RH |
3853 | output_asm_insn ("cmp{l}\t{%0, %4|%4, %0}", xops); |
3854 | output_asm_insn ("jne\t%2", xops); | |
870a0c2c | 3855 | |
e075ae69 RH |
3856 | if (!flag_pic) |
3857 | output_asm_insn ("push{l}\t%1", xops); | |
3858 | else | |
3859 | { | |
3860 | output_asm_insn ("lea{l}\t{%a1, %7|%7, %a2}", xops); | |
3861 | output_asm_insn ("push{l}\t%7", xops); | |
870a0c2c | 3862 | } |
e075ae69 RH |
3863 | output_asm_insn ("call\t%P3", xops); |
3864 | output_asm_insn ("add{l}\t{%6, %5|%5, %6}", xops); | |
3865 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPBZ", num_func); | |
3866 | num_func++; | |
3867 | break; | |
c572e5ba | 3868 | } |
2a2ab3f9 | 3869 | } |
305f097e | 3870 | |
e075ae69 RH |
3871 | /* Output assembler code to FILE to increment a counter associated |
3872 | with basic block number BLOCKNO. | |
305f097e | 3873 | |
e075ae69 | 3874 | If profile_block_flag == 2 |
ecbc4695 | 3875 | |
e075ae69 RH |
3876 | Output code to initialize the global structure `__bb' and |
3877 | call the function `__bb_trace_func' which will increment the | |
3878 | counter. | |
ecbc4695 | 3879 | |
e075ae69 RH |
3880 | `__bb' consists of two words. In the first word the number |
3881 | of the basic block has to be stored. In the second word | |
3882 | the address of a block allocated in the object module | |
3883 | has to be stored. | |
ecbc4695 | 3884 | |
e075ae69 | 3885 | The basic block number is given by BLOCKNO. |
ecbc4695 | 3886 | |
e075ae69 | 3887 | The address of the block is given by the label created with |
305f097e | 3888 | |
e075ae69 | 3889 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); |
305f097e | 3890 | |
e075ae69 | 3891 | by FUNCTION_BLOCK_PROFILER. |
ecbc4695 | 3892 | |
e075ae69 RH |
3893 | Of course, since you are writing the definition of |
3894 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
3895 | can take a short cut in the definition of this macro and use the | |
3896 | name that you know will result. | |
305f097e | 3897 | |
e075ae69 RH |
3898 | If described in a virtual assembler language the code to be |
3899 | output looks like: | |
305f097e | 3900 | |
e075ae69 RH |
3901 | move BLOCKNO -> (__bb) |
3902 | move LPBX0 -> (__bb+4) | |
3903 | call __bb_trace_func | |
305f097e | 3904 | |
e075ae69 RH |
3905 | Note that function `__bb_trace_func' must not change the |
3906 | machine state, especially the flag register. To grant | |
3907 | this, you must output code to save and restore registers | |
3908 | either in this macro or in the macros MACHINE_STATE_SAVE | |
3909 | and MACHINE_STATE_RESTORE. The last two macros will be | |
3910 | used in the function `__bb_trace_func', so you must make | |
3911 | sure that the function prologue does not change any | |
3912 | register prior to saving it with MACHINE_STATE_SAVE. | |
305f097e | 3913 | |
e075ae69 | 3914 | else if profile_block_flag != 0 |
305f097e | 3915 | |
e075ae69 RH |
3916 | Output code to increment the counter directly. |
3917 | Basic blocks are numbered separately from zero within each | |
3918 | compiled object module. The count associated with block number | |
3919 | BLOCKNO is at index BLOCKNO in an array of words; the name of | |
3920 | this array is a local symbol made with this statement: | |
32b5b1aa | 3921 | |
e075ae69 | 3922 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); |
32b5b1aa | 3923 | |
e075ae69 RH |
3924 | Of course, since you are writing the definition of |
3925 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
3926 | can take a short cut in the definition of this macro and use the | |
3927 | name that you know will result. | |
32b5b1aa | 3928 | |
e075ae69 RH |
3929 | If described in a virtual assembler language the code to be |
3930 | output looks like: | |
32b5b1aa | 3931 | |
e075ae69 RH |
3932 | inc (LPBX2+4*BLOCKNO) |
3933 | */ | |
32b5b1aa | 3934 | |
e075ae69 RH |
3935 | void |
3936 | ix86_output_block_profiler (file, blockno) | |
3937 | FILE *file ATTRIBUTE_UNUSED; | |
3938 | int blockno; | |
3939 | { | |
3940 | rtx xops[8], cnt_rtx; | |
3941 | char counts[80]; | |
3942 | char *block_table = counts; | |
3943 | ||
3944 | switch (profile_block_flag) | |
3945 | { | |
3946 | case 2: | |
3947 | ASM_GENERATE_INTERNAL_LABEL (block_table, "LPBX", 0); | |
32b5b1aa | 3948 | |
e075ae69 RH |
3949 | xops[1] = gen_rtx_SYMBOL_REF (VOIDmode, block_table); |
3950 | xops[2] = GEN_INT (blockno); | |
3951 | xops[3] = gen_rtx_MEM (Pmode, | |
3952 | gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_func")); | |
3953 | xops[4] = gen_rtx_SYMBOL_REF (VOIDmode, "__bb"); | |
3954 | xops[5] = plus_constant (xops[4], 4); | |
3955 | xops[0] = gen_rtx_MEM (SImode, xops[4]); | |
3956 | xops[6] = gen_rtx_MEM (SImode, xops[5]); | |
79325812 | 3957 | |
e075ae69 | 3958 | CONSTANT_POOL_ADDRESS_P (xops[1]) = TRUE; |
32b5b1aa | 3959 | |
e075ae69 RH |
3960 | output_asm_insn ("pushf", xops); |
3961 | output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops); | |
3962 | if (flag_pic) | |
32b5b1aa | 3963 | { |
e075ae69 RH |
3964 | xops[7] = gen_rtx_REG (Pmode, 0); /* eax */ |
3965 | output_asm_insn ("push{l}\t%7", xops); | |
3966 | output_asm_insn ("lea{l}\t{%a1, %7|%7, %a1}", xops); | |
3967 | output_asm_insn ("mov{l}\t{%7, %6|%6, %7}", xops); | |
3968 | output_asm_insn ("pop{l}\t%7", xops); | |
3969 | } | |
3970 | else | |
3971 | output_asm_insn ("mov{l}\t{%1, %6|%6, %1}", xops); | |
3972 | output_asm_insn ("call\t%P3", xops); | |
3973 | output_asm_insn ("popf", xops); | |
32b5b1aa | 3974 | |
e075ae69 | 3975 | break; |
32b5b1aa | 3976 | |
e075ae69 RH |
3977 | default: |
3978 | ASM_GENERATE_INTERNAL_LABEL (counts, "LPBX", 2); | |
3979 | cnt_rtx = gen_rtx_SYMBOL_REF (VOIDmode, counts); | |
3980 | SYMBOL_REF_FLAG (cnt_rtx) = TRUE; | |
32b5b1aa | 3981 | |
e075ae69 RH |
3982 | if (blockno) |
3983 | cnt_rtx = plus_constant (cnt_rtx, blockno*4); | |
32b5b1aa | 3984 | |
e075ae69 RH |
3985 | if (flag_pic) |
3986 | cnt_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, cnt_rtx); | |
32b5b1aa | 3987 | |
e075ae69 RH |
3988 | xops[0] = gen_rtx_MEM (SImode, cnt_rtx); |
3989 | output_asm_insn ("inc{l}\t%0", xops); | |
32b5b1aa | 3990 | |
e075ae69 | 3991 | break; |
32b5b1aa | 3992 | } |
32b5b1aa | 3993 | } |
32b5b1aa | 3994 | \f |
79325812 | 3995 | void |
e075ae69 RH |
3996 | ix86_expand_move (mode, operands) |
3997 | enum machine_mode mode; | |
3998 | rtx operands[]; | |
32b5b1aa | 3999 | { |
e075ae69 | 4000 | int strict = (reload_in_progress || reload_completed); |
e075ae69 | 4001 | rtx insn; |
e9a25f70 | 4002 | |
e075ae69 | 4003 | if (flag_pic && mode == Pmode && symbolic_operand (operands[1], Pmode)) |
32b5b1aa | 4004 | { |
e075ae69 | 4005 | /* Emit insns to move operands[1] into operands[0]. */ |
e9a25f70 | 4006 | |
e075ae69 RH |
4007 | if (GET_CODE (operands[0]) == MEM) |
4008 | operands[1] = force_reg (Pmode, operands[1]); | |
4009 | else | |
32b5b1aa | 4010 | { |
e075ae69 RH |
4011 | rtx temp = operands[0]; |
4012 | if (GET_CODE (temp) != REG) | |
4013 | temp = gen_reg_rtx (Pmode); | |
4014 | temp = legitimize_pic_address (operands[1], temp); | |
4015 | if (temp == operands[0]) | |
4016 | return; | |
4017 | operands[1] = temp; | |
32b5b1aa | 4018 | } |
e075ae69 RH |
4019 | } |
4020 | else | |
4021 | { | |
d7a29404 JH |
4022 | if (GET_CODE (operands[0]) == MEM |
4023 | && (GET_MODE (operands[0]) == QImode | |
4024 | || !push_operand (operands[0], mode)) | |
4025 | && GET_CODE (operands[1]) == MEM) | |
e075ae69 | 4026 | operands[1] = force_reg (mode, operands[1]); |
e9a25f70 | 4027 | |
2c5a510c RH |
4028 | if (push_operand (operands[0], mode) |
4029 | && ! general_no_elim_operand (operands[1], mode)) | |
4030 | operands[1] = copy_to_mode_reg (mode, operands[1]); | |
4031 | ||
e075ae69 | 4032 | if (FLOAT_MODE_P (mode)) |
32b5b1aa | 4033 | { |
d7a29404 JH |
4034 | /* If we are loading a floating point constant to a register, |
4035 | force the value to memory now, since we'll get better code | |
4036 | out the back end. */ | |
e075ae69 RH |
4037 | |
4038 | if (strict) | |
4039 | ; | |
e075ae69 | 4040 | else if (GET_CODE (operands[1]) == CONST_DOUBLE |
d7a29404 | 4041 | && register_operand (operands[0], mode)) |
e075ae69 | 4042 | operands[1] = validize_mem (force_const_mem (mode, operands[1])); |
32b5b1aa | 4043 | } |
32b5b1aa | 4044 | } |
e9a25f70 | 4045 | |
e075ae69 | 4046 | insn = gen_rtx_SET (VOIDmode, operands[0], operands[1]); |
e9a25f70 | 4047 | |
e075ae69 RH |
4048 | emit_insn (insn); |
4049 | } | |
e9a25f70 | 4050 | |
e075ae69 RH |
4051 | /* Attempt to expand a binary operator. Make the expansion closer to the |
4052 | actual machine, then just general_operand, which will allow 3 separate | |
9d81fc27 | 4053 | memory references (one output, two input) in a single insn. */ |
e9a25f70 | 4054 | |
e075ae69 RH |
4055 | void |
4056 | ix86_expand_binary_operator (code, mode, operands) | |
4057 | enum rtx_code code; | |
4058 | enum machine_mode mode; | |
4059 | rtx operands[]; | |
4060 | { | |
4061 | int matching_memory; | |
4062 | rtx src1, src2, dst, op, clob; | |
4063 | ||
4064 | dst = operands[0]; | |
4065 | src1 = operands[1]; | |
4066 | src2 = operands[2]; | |
4067 | ||
4068 | /* Recognize <var1> = <value> <op> <var1> for commutative operators */ | |
4069 | if (GET_RTX_CLASS (code) == 'c' | |
4070 | && (rtx_equal_p (dst, src2) | |
4071 | || immediate_operand (src1, mode))) | |
4072 | { | |
4073 | rtx temp = src1; | |
4074 | src1 = src2; | |
4075 | src2 = temp; | |
32b5b1aa | 4076 | } |
e9a25f70 | 4077 | |
e075ae69 RH |
4078 | /* If the destination is memory, and we do not have matching source |
4079 | operands, do things in registers. */ | |
4080 | matching_memory = 0; | |
4081 | if (GET_CODE (dst) == MEM) | |
32b5b1aa | 4082 | { |
e075ae69 RH |
4083 | if (rtx_equal_p (dst, src1)) |
4084 | matching_memory = 1; | |
4085 | else if (GET_RTX_CLASS (code) == 'c' | |
4086 | && rtx_equal_p (dst, src2)) | |
4087 | matching_memory = 2; | |
4088 | else | |
4089 | dst = gen_reg_rtx (mode); | |
4090 | } | |
4091 | ||
4092 | /* Both source operands cannot be in memory. */ | |
4093 | if (GET_CODE (src1) == MEM && GET_CODE (src2) == MEM) | |
4094 | { | |
4095 | if (matching_memory != 2) | |
4096 | src2 = force_reg (mode, src2); | |
4097 | else | |
4098 | src1 = force_reg (mode, src1); | |
32b5b1aa | 4099 | } |
e9a25f70 | 4100 | |
06a964de JH |
4101 | /* If the operation is not commutable, source 1 cannot be a constant |
4102 | or non-matching memory. */ | |
4103 | if ((CONSTANT_P (src1) | |
4104 | || (!matching_memory && GET_CODE (src1) == MEM)) | |
4105 | && GET_RTX_CLASS (code) != 'c') | |
e075ae69 RH |
4106 | src1 = force_reg (mode, src1); |
4107 | ||
4108 | /* If optimizing, copy to regs to improve CSE */ | |
4109 | if (optimize && !reload_in_progress && !reload_completed) | |
32b5b1aa | 4110 | { |
e075ae69 RH |
4111 | if (GET_CODE (dst) == MEM) |
4112 | dst = gen_reg_rtx (mode); | |
4113 | if (GET_CODE (src1) == MEM) | |
4114 | src1 = force_reg (mode, src1); | |
4115 | if (GET_CODE (src2) == MEM) | |
4116 | src2 = force_reg (mode, src2); | |
32b5b1aa | 4117 | } |
e9a25f70 | 4118 | |
e075ae69 RH |
4119 | /* Emit the instruction. */ |
4120 | ||
4121 | op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2)); | |
4122 | if (reload_in_progress) | |
4123 | { | |
4124 | /* Reload doesn't know about the flags register, and doesn't know that | |
4125 | it doesn't want to clobber it. We can only do this with PLUS. */ | |
4126 | if (code != PLUS) | |
4127 | abort (); | |
4128 | emit_insn (op); | |
4129 | } | |
4130 | else | |
32b5b1aa | 4131 | { |
e075ae69 RH |
4132 | clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG)); |
4133 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); | |
32b5b1aa | 4134 | } |
e9a25f70 | 4135 | |
e075ae69 RH |
4136 | /* Fix up the destination if needed. */ |
4137 | if (dst != operands[0]) | |
4138 | emit_move_insn (operands[0], dst); | |
4139 | } | |
4140 | ||
4141 | /* Return TRUE or FALSE depending on whether the binary operator meets the | |
4142 | appropriate constraints. */ | |
4143 | ||
4144 | int | |
4145 | ix86_binary_operator_ok (code, mode, operands) | |
4146 | enum rtx_code code; | |
4147 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4148 | rtx operands[3]; | |
4149 | { | |
4150 | /* Both source operands cannot be in memory. */ | |
4151 | if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM) | |
4152 | return 0; | |
4153 | /* If the operation is not commutable, source 1 cannot be a constant. */ | |
4154 | if (CONSTANT_P (operands[1]) && GET_RTX_CLASS (code) != 'c') | |
4155 | return 0; | |
4156 | /* If the destination is memory, we must have a matching source operand. */ | |
4157 | if (GET_CODE (operands[0]) == MEM | |
4158 | && ! (rtx_equal_p (operands[0], operands[1]) | |
4159 | || (GET_RTX_CLASS (code) == 'c' | |
4160 | && rtx_equal_p (operands[0], operands[2])))) | |
4161 | return 0; | |
06a964de JH |
4162 | /* If the operation is not commutable and the source 1 is memory, we must |
4163 | have a matching destionation. */ | |
4164 | if (GET_CODE (operands[1]) == MEM | |
4165 | && GET_RTX_CLASS (code) != 'c' | |
4166 | && ! rtx_equal_p (operands[0], operands[1])) | |
4167 | return 0; | |
e075ae69 RH |
4168 | return 1; |
4169 | } | |
4170 | ||
4171 | /* Attempt to expand a unary operator. Make the expansion closer to the | |
4172 | actual machine, then just general_operand, which will allow 2 separate | |
9d81fc27 | 4173 | memory references (one output, one input) in a single insn. */ |
e075ae69 | 4174 | |
9d81fc27 | 4175 | void |
e075ae69 RH |
4176 | ix86_expand_unary_operator (code, mode, operands) |
4177 | enum rtx_code code; | |
4178 | enum machine_mode mode; | |
4179 | rtx operands[]; | |
4180 | { | |
06a964de JH |
4181 | int matching_memory; |
4182 | rtx src, dst, op, clob; | |
4183 | ||
4184 | dst = operands[0]; | |
4185 | src = operands[1]; | |
e075ae69 | 4186 | |
06a964de JH |
4187 | /* If the destination is memory, and we do not have matching source |
4188 | operands, do things in registers. */ | |
4189 | matching_memory = 0; | |
4190 | if (GET_CODE (dst) == MEM) | |
32b5b1aa | 4191 | { |
06a964de JH |
4192 | if (rtx_equal_p (dst, src)) |
4193 | matching_memory = 1; | |
e075ae69 | 4194 | else |
06a964de | 4195 | dst = gen_reg_rtx (mode); |
32b5b1aa | 4196 | } |
e9a25f70 | 4197 | |
06a964de JH |
4198 | /* When source operand is memory, destination must match. */ |
4199 | if (!matching_memory && GET_CODE (src) == MEM) | |
4200 | src = force_reg (mode, src); | |
4201 | ||
4202 | /* If optimizing, copy to regs to improve CSE */ | |
4203 | if (optimize && !reload_in_progress && !reload_completed) | |
4204 | { | |
4205 | if (GET_CODE (dst) == MEM) | |
4206 | dst = gen_reg_rtx (mode); | |
4207 | if (GET_CODE (src) == MEM) | |
4208 | src = force_reg (mode, src); | |
4209 | } | |
4210 | ||
4211 | /* Emit the instruction. */ | |
4212 | ||
4213 | op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src)); | |
4214 | if (reload_in_progress || code == NOT) | |
4215 | { | |
4216 | /* Reload doesn't know about the flags register, and doesn't know that | |
4217 | it doesn't want to clobber it. */ | |
4218 | if (code != NOT) | |
4219 | abort (); | |
4220 | emit_insn (op); | |
4221 | } | |
4222 | else | |
4223 | { | |
4224 | clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG)); | |
4225 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); | |
4226 | } | |
4227 | ||
4228 | /* Fix up the destination if needed. */ | |
4229 | if (dst != operands[0]) | |
4230 | emit_move_insn (operands[0], dst); | |
e075ae69 RH |
4231 | } |
4232 | ||
4233 | /* Return TRUE or FALSE depending on whether the unary operator meets the | |
4234 | appropriate constraints. */ | |
4235 | ||
4236 | int | |
4237 | ix86_unary_operator_ok (code, mode, operands) | |
4238 | enum rtx_code code ATTRIBUTE_UNUSED; | |
4239 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4240 | rtx operands[2] ATTRIBUTE_UNUSED; | |
4241 | { | |
06a964de JH |
4242 | /* If one of operands is memory, source and destination must match. */ |
4243 | if ((GET_CODE (operands[0]) == MEM | |
4244 | || GET_CODE (operands[1]) == MEM) | |
4245 | && ! rtx_equal_p (operands[0], operands[1])) | |
4246 | return FALSE; | |
e075ae69 RH |
4247 | return TRUE; |
4248 | } | |
4249 | ||
4250 | /* Produce an unsigned comparison for a given signed comparison. */ | |
4251 | ||
4252 | static enum rtx_code | |
4253 | unsigned_comparison (code) | |
4254 | enum rtx_code code; | |
4255 | { | |
4256 | switch (code) | |
32b5b1aa | 4257 | { |
e075ae69 RH |
4258 | case GT: |
4259 | code = GTU; | |
4260 | break; | |
4261 | case LT: | |
4262 | code = LTU; | |
4263 | break; | |
4264 | case GE: | |
4265 | code = GEU; | |
4266 | break; | |
4267 | case LE: | |
4268 | code = LEU; | |
4269 | break; | |
4270 | case EQ: | |
4271 | case NE: | |
4272 | case LEU: | |
4273 | case LTU: | |
4274 | case GEU: | |
4275 | case GTU: | |
4276 | break; | |
4277 | default: | |
4278 | abort (); | |
4279 | } | |
4280 | return code; | |
4281 | } | |
4282 | ||
4283 | /* Generate insn patterns to do an integer compare of OPERANDS. */ | |
4284 | ||
4285 | static rtx | |
4286 | ix86_expand_int_compare (code, op0, op1) | |
4287 | enum rtx_code code; | |
4288 | rtx op0, op1; | |
4289 | { | |
4290 | enum machine_mode cmpmode; | |
4291 | rtx tmp, flags; | |
4292 | ||
4293 | cmpmode = SELECT_CC_MODE (code, op0, op1); | |
4294 | flags = gen_rtx_REG (cmpmode, FLAGS_REG); | |
4295 | ||
4296 | /* This is very simple, but making the interface the same as in the | |
4297 | FP case makes the rest of the code easier. */ | |
4298 | tmp = gen_rtx_COMPARE (cmpmode, op0, op1); | |
4299 | emit_insn (gen_rtx_SET (VOIDmode, flags, tmp)); | |
4300 | ||
4301 | /* Return the test that should be put into the flags user, i.e. | |
4302 | the bcc, scc, or cmov instruction. */ | |
4303 | return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx); | |
4304 | } | |
4305 | ||
4306 | /* Generate insn patterns to do a floating point compare of OPERANDS. | |
4307 | If UNORDERED, allow for unordered compares. */ | |
4308 | ||
4309 | static rtx | |
4310 | ix86_expand_fp_compare (code, op0, op1, unordered) | |
4311 | enum rtx_code code; | |
4312 | rtx op0, op1; | |
4313 | int unordered; | |
4314 | { | |
4315 | enum machine_mode fpcmp_mode; | |
4316 | enum machine_mode intcmp_mode; | |
4317 | rtx tmp; | |
4318 | ||
4319 | /* When not doing IEEE compliant compares, disable unordered. */ | |
4320 | if (! TARGET_IEEE_FP) | |
4321 | unordered = 0; | |
4322 | fpcmp_mode = unordered ? CCFPUmode : CCFPmode; | |
4323 | ||
4324 | /* ??? If we knew whether invalid-operand exceptions were masked, | |
4325 | we could rely on fcom to raise an exception and take care of | |
4326 | NaNs. But we don't. We could know this from c9x math bits. */ | |
4327 | if (TARGET_IEEE_FP) | |
4328 | unordered = 1; | |
4329 | ||
4330 | /* All of the unordered compare instructions only work on registers. | |
4331 | The same is true of the XFmode compare instructions. */ | |
4332 | if (unordered || GET_MODE (op0) == XFmode) | |
4333 | { | |
4334 | op0 = force_reg (GET_MODE (op0), op0); | |
4335 | op1 = force_reg (GET_MODE (op1), op1); | |
4336 | } | |
4337 | else | |
4338 | { | |
4339 | /* %%% We only allow op1 in memory; op0 must be st(0). So swap | |
4340 | things around if they appear profitable, otherwise force op0 | |
4341 | into a register. */ | |
4342 | ||
4343 | if (standard_80387_constant_p (op0) == 0 | |
4344 | || (GET_CODE (op0) == MEM | |
4345 | && ! (standard_80387_constant_p (op1) == 0 | |
4346 | || GET_CODE (op1) == MEM))) | |
32b5b1aa | 4347 | { |
e075ae69 RH |
4348 | rtx tmp; |
4349 | tmp = op0, op0 = op1, op1 = tmp; | |
4350 | code = swap_condition (code); | |
4351 | } | |
4352 | ||
4353 | if (GET_CODE (op0) != REG) | |
4354 | op0 = force_reg (GET_MODE (op0), op0); | |
4355 | ||
4356 | if (CONSTANT_P (op1)) | |
4357 | { | |
4358 | if (standard_80387_constant_p (op1)) | |
4359 | op1 = force_reg (GET_MODE (op1), op1); | |
4360 | else | |
4361 | op1 = validize_mem (force_const_mem (GET_MODE (op1), op1)); | |
32b5b1aa SC |
4362 | } |
4363 | } | |
e9a25f70 | 4364 | |
e075ae69 RH |
4365 | /* %%% fcomi is probably always faster, even when dealing with memory, |
4366 | since compare-and-branch would be three insns instead of four. */ | |
4367 | if (TARGET_CMOVE && !unordered) | |
32b5b1aa | 4368 | { |
e075ae69 RH |
4369 | if (GET_CODE (op0) != REG) |
4370 | op0 = force_reg (GET_MODE (op0), op0); | |
4371 | if (GET_CODE (op1) != REG) | |
4372 | op1 = force_reg (GET_MODE (op1), op1); | |
4373 | ||
4374 | tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1); | |
4375 | tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG), tmp); | |
4376 | emit_insn (tmp); | |
4377 | ||
4378 | /* The FP codes work out to act like unsigned. */ | |
4379 | code = unsigned_comparison (code); | |
4380 | intcmp_mode = fpcmp_mode; | |
4381 | } | |
4382 | else | |
4383 | { | |
4384 | /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */ | |
e9a25f70 | 4385 | |
e075ae69 RH |
4386 | rtx tmp2; |
4387 | tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1); | |
4388 | tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), 9); | |
4389 | tmp = gen_reg_rtx (HImode); | |
4390 | emit_insn (gen_rtx_SET (VOIDmode, tmp, tmp2)); | |
4391 | ||
4392 | if (! unordered) | |
32b5b1aa | 4393 | { |
e075ae69 RH |
4394 | /* We have two options here -- use sahf, or testing bits of ah |
4395 | directly. On PPRO, they are equivalent, sahf being one byte | |
4396 | smaller. On Pentium, sahf is non-pairable while test is UV | |
4397 | pairable. */ | |
4398 | ||
4399 | if (TARGET_USE_SAHF || optimize_size) | |
32b5b1aa | 4400 | { |
e075ae69 | 4401 | do_sahf: |
e9a25f70 | 4402 | |
e075ae69 RH |
4403 | /* The FP codes work out to act like unsigned. */ |
4404 | code = unsigned_comparison (code); | |
4405 | emit_insn (gen_x86_sahf_1 (tmp)); | |
4406 | intcmp_mode = CCmode; | |
32b5b1aa SC |
4407 | } |
4408 | else | |
4409 | { | |
e075ae69 RH |
4410 | /* |
4411 | * The numbers below correspond to the bits of the FPSW in AH. | |
d22ce03d | 4412 | * C3, C2, and C0 are in bits 0x40, 0x4, and 0x01 respectively. |
e075ae69 RH |
4413 | * |
4414 | * cmp C3 C2 C0 | |
4415 | * > 0 0 0 | |
4416 | * < 0 0 1 | |
4417 | * = 1 0 0 | |
4418 | * un 1 1 1 | |
4419 | */ | |
4420 | ||
4421 | int mask; | |
4422 | ||
4423 | switch (code) | |
32b5b1aa | 4424 | { |
e075ae69 | 4425 | case GT: |
d22ce03d | 4426 | mask = 0x41; |
e075ae69 RH |
4427 | code = EQ; |
4428 | break; | |
4429 | case LT: | |
4430 | mask = 0x01; | |
4431 | code = NE; | |
4432 | break; | |
4433 | case GE: | |
4434 | /* We'd have to use `xorb 1,ah; andb 0x41,ah', so it's | |
4435 | faster in all cases to just fall back on sahf. */ | |
4436 | goto do_sahf; | |
4437 | case LE: | |
4438 | mask = 0x41; | |
4439 | code = NE; | |
4440 | break; | |
4441 | case EQ: | |
4442 | mask = 0x40; | |
4443 | code = NE; | |
4444 | break; | |
4445 | case NE: | |
4446 | mask = 0x40; | |
4447 | code = EQ; | |
4448 | break; | |
4449 | default: | |
4450 | abort (); | |
32b5b1aa | 4451 | } |
e075ae69 RH |
4452 | |
4453 | emit_insn (gen_testqi_ext_0 (tmp, GEN_INT (mask))); | |
4454 | intcmp_mode = CCNOmode; | |
32b5b1aa SC |
4455 | } |
4456 | } | |
4457 | else | |
4458 | { | |
e075ae69 RH |
4459 | /* In the unordered case, we have to check C2 for NaN's, which |
4460 | doesn't happen to work out to anything nice combination-wise. | |
4461 | So do some bit twiddling on the value we've got in AH to come | |
4462 | up with an appropriate set of condition codes. */ | |
4463 | ||
4464 | intcmp_mode = CCNOmode; | |
4465 | switch (code) | |
32b5b1aa | 4466 | { |
e075ae69 RH |
4467 | case GT: |
4468 | emit_insn (gen_testqi_ext_0 (tmp, GEN_INT (0x45))); | |
4469 | code = EQ; | |
4470 | break; | |
4471 | case LT: | |
4472 | emit_insn (gen_andqi_ext_0 (tmp, tmp, GEN_INT (0x45))); | |
4473 | emit_insn (gen_cmpqi_ext_3 (tmp, GEN_INT (0x01))); | |
4474 | intcmp_mode = CCmode; | |
4475 | code = EQ; | |
4476 | break; | |
4477 | case GE: | |
4478 | emit_insn (gen_testqi_ext_0 (tmp, GEN_INT (0x05))); | |
4479 | code = EQ; | |
4480 | break; | |
4481 | case LE: | |
4482 | emit_insn (gen_andqi_ext_0 (tmp, tmp, GEN_INT (0x45))); | |
4483 | emit_insn (gen_addqi_ext_1 (tmp, tmp, constm1_rtx)); | |
4484 | emit_insn (gen_cmpqi_ext_3 (tmp, GEN_INT (0x40))); | |
4485 | intcmp_mode = CCmode; | |
4486 | code = LTU; | |
4487 | break; | |
4488 | case EQ: | |
4489 | emit_insn (gen_andqi_ext_0 (tmp, tmp, GEN_INT (0x45))); | |
4490 | emit_insn (gen_cmpqi_ext_3 (tmp, GEN_INT (0x40))); | |
4491 | intcmp_mode = CCmode; | |
4492 | code = EQ; | |
4493 | break; | |
4494 | case NE: | |
4495 | emit_insn (gen_andqi_ext_0 (tmp, tmp, GEN_INT (0x45))); | |
7abd4e00 | 4496 | emit_insn (gen_xorqi_cc_ext_1 (tmp, tmp, GEN_INT (0x40))); |
e075ae69 RH |
4497 | code = NE; |
4498 | break; | |
4499 | default: | |
4500 | abort (); | |
32b5b1aa SC |
4501 | } |
4502 | } | |
32b5b1aa | 4503 | } |
e075ae69 RH |
4504 | |
4505 | /* Return the test that should be put into the flags user, i.e. | |
4506 | the bcc, scc, or cmov instruction. */ | |
4507 | return gen_rtx_fmt_ee (code, VOIDmode, | |
4508 | gen_rtx_REG (intcmp_mode, FLAGS_REG), | |
4509 | const0_rtx); | |
4510 | } | |
4511 | ||
4512 | static rtx | |
4513 | ix86_expand_compare (code, unordered) | |
4514 | enum rtx_code code; | |
4515 | int unordered; | |
4516 | { | |
4517 | rtx op0, op1, ret; | |
4518 | op0 = ix86_compare_op0; | |
4519 | op1 = ix86_compare_op1; | |
4520 | ||
4521 | if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT) | |
4522 | ret = ix86_expand_fp_compare (code, op0, op1, unordered); | |
32b5b1aa | 4523 | else |
e075ae69 RH |
4524 | ret = ix86_expand_int_compare (code, op0, op1); |
4525 | ||
4526 | return ret; | |
4527 | } | |
4528 | ||
4529 | void | |
4530 | ix86_expand_branch (code, unordered, label) | |
4531 | enum rtx_code code; | |
4532 | int unordered; | |
4533 | rtx label; | |
4534 | { | |
4535 | rtx tmp, lo[2], hi[2], label2; | |
4536 | enum rtx_code code1, code2, code3; | |
4537 | ||
4538 | if (GET_MODE (ix86_compare_op0) != DImode) | |
32b5b1aa | 4539 | { |
e075ae69 RH |
4540 | tmp = ix86_expand_compare (code, unordered); |
4541 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
4542 | gen_rtx_LABEL_REF (VOIDmode, label), | |
4543 | pc_rtx); | |
4544 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
32b5b1aa SC |
4545 | return; |
4546 | } | |
32b5b1aa | 4547 | |
e075ae69 RH |
4548 | /* Expand DImode branch into multiple compare+branch. */ |
4549 | ||
4550 | if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1)) | |
32b5b1aa | 4551 | { |
e075ae69 RH |
4552 | tmp = ix86_compare_op0; |
4553 | ix86_compare_op0 = ix86_compare_op1; | |
4554 | ix86_compare_op1 = tmp; | |
4555 | code = swap_condition (code); | |
4556 | } | |
4557 | split_di (&ix86_compare_op0, 1, lo+0, hi+0); | |
4558 | split_di (&ix86_compare_op1, 1, lo+1, hi+1); | |
32b5b1aa | 4559 | |
e075ae69 RH |
4560 | /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to avoid |
4561 | two branches. This costs one extra insn, so disable when optimizing | |
4562 | for size. */ | |
32b5b1aa | 4563 | |
e075ae69 RH |
4564 | if ((code == EQ || code == NE) |
4565 | && (!optimize_size | |
4566 | || hi[1] == const0_rtx || lo[1] == const0_rtx)) | |
4567 | { | |
4568 | rtx xor0, xor1; | |
32b5b1aa | 4569 | |
e075ae69 RH |
4570 | xor1 = hi[0]; |
4571 | if (hi[1] != const0_rtx) | |
4572 | { | |
4573 | xor1 = expand_binop (SImode, xor_optab, xor1, hi[1], | |
4574 | NULL_RTX, 0, OPTAB_WIDEN); | |
4575 | } | |
32b5b1aa | 4576 | |
e075ae69 RH |
4577 | xor0 = lo[0]; |
4578 | if (lo[1] != const0_rtx) | |
4579 | { | |
4580 | xor0 = expand_binop (SImode, xor_optab, xor0, lo[1], | |
4581 | NULL_RTX, 0, OPTAB_WIDEN); | |
32b5b1aa SC |
4582 | } |
4583 | ||
e075ae69 RH |
4584 | tmp = expand_binop (SImode, ior_optab, xor1, xor0, |
4585 | NULL_RTX, 0, OPTAB_WIDEN); | |
32b5b1aa | 4586 | |
e075ae69 RH |
4587 | ix86_compare_op0 = tmp; |
4588 | ix86_compare_op1 = const0_rtx; | |
4589 | ix86_expand_branch (code, unordered, label); | |
4590 | return; | |
32b5b1aa SC |
4591 | } |
4592 | ||
e075ae69 RH |
4593 | /* Otherwise, if we are doing less-than, op1 is a constant and the |
4594 | low word is zero, then we can just examine the high word. */ | |
4595 | ||
4596 | if (GET_CODE (hi[1]) == CONST_INT && lo[1] == const0_rtx | |
4597 | && (code == LT || code == LTU)) | |
32b5b1aa | 4598 | { |
e075ae69 RH |
4599 | ix86_compare_op0 = hi[0]; |
4600 | ix86_compare_op1 = hi[1]; | |
4601 | ix86_expand_branch (code, unordered, label); | |
4602 | return; | |
4603 | } | |
32b5b1aa | 4604 | |
e075ae69 RH |
4605 | /* Otherwise, we need two or three jumps. */ |
4606 | ||
4607 | label2 = gen_label_rtx (); | |
32b5b1aa | 4608 | |
e075ae69 RH |
4609 | code1 = code; |
4610 | code2 = swap_condition (code); | |
4611 | code3 = unsigned_condition (code); | |
4612 | ||
4613 | switch (code) | |
4614 | { | |
4615 | case LT: case GT: case LTU: case GTU: | |
4616 | break; | |
4617 | ||
4618 | case LE: code1 = LT; code2 = GT; break; | |
4619 | case GE: code1 = GT; code2 = LT; break; | |
4620 | case LEU: code1 = LTU; code2 = GTU; break; | |
4621 | case GEU: code1 = GTU; code2 = LTU; break; | |
4622 | ||
4623 | case EQ: code1 = NIL; code2 = NE; break; | |
4624 | case NE: code2 = NIL; break; | |
4625 | ||
4626 | default: | |
4627 | abort (); | |
32b5b1aa | 4628 | } |
e075ae69 RH |
4629 | |
4630 | /* | |
4631 | * a < b => | |
4632 | * if (hi(a) < hi(b)) goto true; | |
4633 | * if (hi(a) > hi(b)) goto false; | |
4634 | * if (lo(a) < lo(b)) goto true; | |
4635 | * false: | |
4636 | */ | |
4637 | ||
4638 | ix86_compare_op0 = hi[0]; | |
4639 | ix86_compare_op1 = hi[1]; | |
4640 | ||
4641 | if (code1 != NIL) | |
4642 | ix86_expand_branch (code1, unordered, label); | |
4643 | if (code2 != NIL) | |
4644 | ix86_expand_branch (code2, unordered, label2); | |
4645 | ||
4646 | ix86_compare_op0 = lo[0]; | |
4647 | ix86_compare_op1 = lo[1]; | |
4648 | ix86_expand_branch (code3, unordered, label); | |
4649 | ||
4650 | if (code2 != NIL) | |
4651 | emit_label (label2); | |
32b5b1aa | 4652 | } |
e075ae69 | 4653 | |
32b5b1aa | 4654 | int |
e075ae69 RH |
4655 | ix86_expand_setcc (code, unordered, dest) |
4656 | enum rtx_code code; | |
4657 | int unordered; | |
4658 | rtx dest; | |
32b5b1aa | 4659 | { |
e075ae69 RH |
4660 | rtx ret, tmp; |
4661 | int type; | |
4662 | ||
4663 | if (GET_MODE (ix86_compare_op0) == DImode) | |
4664 | return 0; /* FAIL */ | |
4665 | ||
4666 | /* Three modes of generation: | |
4667 | 0 -- destination does not overlap compare sources: | |
4668 | clear dest first, emit strict_low_part setcc. | |
4669 | 1 -- destination does overlap compare sources: | |
4670 | emit subreg setcc, zero extend. | |
4671 | 2 -- destination is in QImode: | |
4672 | emit setcc only. | |
4673 | */ | |
4674 | ||
4675 | type = 0; | |
e075ae69 RH |
4676 | |
4677 | if (GET_MODE (dest) == QImode) | |
4678 | type = 2; | |
4679 | else if (reg_overlap_mentioned_p (dest, ix86_compare_op0) | |
a500c31b | 4680 | || reg_overlap_mentioned_p (dest, ix86_compare_op1)) |
e075ae69 RH |
4681 | type = 1; |
4682 | ||
4683 | if (type == 0) | |
4684 | emit_move_insn (dest, const0_rtx); | |
4685 | ||
4686 | ret = ix86_expand_compare (code, unordered); | |
4687 | PUT_MODE (ret, QImode); | |
4688 | ||
4689 | tmp = dest; | |
4690 | if (type == 0) | |
32b5b1aa | 4691 | { |
e075ae69 RH |
4692 | tmp = gen_lowpart (QImode, dest); |
4693 | tmp = gen_rtx_STRICT_LOW_PART (VOIDmode, tmp); | |
4694 | } | |
4695 | else if (type == 1) | |
4696 | { | |
4697 | if (!cse_not_expected) | |
4698 | tmp = gen_reg_rtx (QImode); | |
4699 | else | |
4700 | tmp = gen_lowpart (QImode, dest); | |
4701 | } | |
32b5b1aa | 4702 | |
e075ae69 RH |
4703 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ret)); |
4704 | ||
4705 | if (type == 1) | |
4706 | { | |
4707 | rtx clob; | |
4708 | ||
4709 | tmp = gen_rtx_ZERO_EXTEND (GET_MODE (dest), tmp); | |
4710 | tmp = gen_rtx_SET (VOIDmode, dest, tmp); | |
4711 | clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG)); | |
4712 | tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob)); | |
4713 | emit_insn (tmp); | |
32b5b1aa | 4714 | } |
e075ae69 RH |
4715 | |
4716 | return 1; /* DONE */ | |
32b5b1aa | 4717 | } |
e075ae69 | 4718 | |
32b5b1aa | 4719 | int |
e075ae69 RH |
4720 | ix86_expand_int_movcc (operands) |
4721 | rtx operands[]; | |
32b5b1aa | 4722 | { |
e075ae69 RH |
4723 | enum rtx_code code = GET_CODE (operands[1]), compare_code; |
4724 | rtx compare_seq, compare_op; | |
32b5b1aa | 4725 | |
36583fea JH |
4726 | /* When the compare code is not LTU or GEU, we can not use sbbl case. |
4727 | In case comparsion is done with immediate, we can convert it to LTU or | |
4728 | GEU by altering the integer. */ | |
4729 | ||
4730 | if ((code == LEU || code == GTU) | |
4731 | && GET_CODE (ix86_compare_op1) == CONST_INT | |
4732 | && GET_MODE (operands[0]) != HImode | |
4733 | && (unsigned int)INTVAL (ix86_compare_op1) != 0xffffffff | |
4734 | && GET_CODE (operands[2]) == CONST_INT | |
4735 | && GET_CODE (operands[3]) == CONST_INT) | |
4736 | { | |
4737 | if (code == LEU) | |
4738 | code = LTU; | |
4739 | else | |
4740 | code = GEU; | |
4741 | ix86_compare_op1 = GEN_INT (INTVAL (ix86_compare_op1) + 1); | |
4742 | } | |
e075ae69 RH |
4743 | start_sequence (); |
4744 | compare_op = ix86_expand_compare (code, code == EQ || code == NE); | |
4745 | compare_seq = gen_sequence (); | |
4746 | end_sequence (); | |
4747 | ||
4748 | compare_code = GET_CODE (compare_op); | |
4749 | ||
4750 | /* Don't attempt mode expansion here -- if we had to expand 5 or 6 | |
4751 | HImode insns, we'd be swallowed in word prefix ops. */ | |
4752 | ||
4753 | if (GET_MODE (operands[0]) != HImode | |
4754 | && GET_CODE (operands[2]) == CONST_INT | |
4755 | && GET_CODE (operands[3]) == CONST_INT) | |
4756 | { | |
4757 | rtx out = operands[0]; | |
4758 | HOST_WIDE_INT ct = INTVAL (operands[2]); | |
4759 | HOST_WIDE_INT cf = INTVAL (operands[3]); | |
4760 | HOST_WIDE_INT diff; | |
4761 | ||
36583fea | 4762 | if (compare_code == LTU || compare_code == GEU) |
e075ae69 | 4763 | { |
e075ae69 RH |
4764 | |
4765 | /* Detect overlap between destination and compare sources. */ | |
4766 | rtx tmp = out; | |
4767 | ||
36583fea JH |
4768 | /* To simplify rest of code, restrict to the GEU case. */ |
4769 | if (compare_code == LTU) | |
4770 | { | |
4771 | int tmp = ct; | |
4772 | ct = cf; | |
4773 | cf = tmp; | |
4774 | compare_code = reverse_condition (compare_code); | |
4775 | code = reverse_condition (code); | |
4776 | } | |
4777 | diff = ct - cf; | |
4778 | ||
e075ae69 | 4779 | if (reg_overlap_mentioned_p (out, ix86_compare_op0) |
a500c31b | 4780 | || reg_overlap_mentioned_p (out, ix86_compare_op1)) |
e075ae69 RH |
4781 | tmp = gen_reg_rtx (SImode); |
4782 | ||
4783 | emit_insn (compare_seq); | |
4784 | emit_insn (gen_x86_movsicc_0_m1 (tmp)); | |
4785 | ||
36583fea JH |
4786 | if (diff == 1) |
4787 | { | |
4788 | /* | |
4789 | * cmpl op0,op1 | |
4790 | * sbbl dest,dest | |
4791 | * [addl dest, ct] | |
4792 | * | |
4793 | * Size 5 - 8. | |
4794 | */ | |
4795 | if (ct) | |
4796 | emit_insn (gen_addsi3 (out, out, GEN_INT (ct))); | |
4797 | } | |
4798 | else if (cf == -1) | |
4799 | { | |
4800 | /* | |
4801 | * cmpl op0,op1 | |
4802 | * sbbl dest,dest | |
4803 | * orl $ct, dest | |
4804 | * | |
4805 | * Size 8. | |
4806 | */ | |
4807 | emit_insn (gen_iorsi3 (out, out, GEN_INT (ct))); | |
4808 | } | |
4809 | else if (diff == -1 && ct) | |
4810 | { | |
4811 | /* | |
4812 | * cmpl op0,op1 | |
4813 | * sbbl dest,dest | |
4814 | * xorl $-1, dest | |
4815 | * [addl dest, cf] | |
4816 | * | |
4817 | * Size 8 - 11. | |
4818 | */ | |
4819 | emit_insn (gen_one_cmplsi2 (tmp, tmp)); | |
4820 | if (cf) | |
4821 | emit_insn (gen_addsi3 (out, out, GEN_INT (cf))); | |
4822 | } | |
4823 | else | |
4824 | { | |
4825 | /* | |
4826 | * cmpl op0,op1 | |
4827 | * sbbl dest,dest | |
4828 | * andl cf - ct, dest | |
4829 | * [addl dest, ct] | |
4830 | * | |
4831 | * Size 8 - 11. | |
4832 | */ | |
4833 | emit_insn (gen_andsi3 (out, out, GEN_INT (cf - ct))); | |
4834 | if (ct) | |
4835 | emit_insn (gen_addsi3 (out, out, GEN_INT (ct))); | |
4836 | } | |
e075ae69 RH |
4837 | |
4838 | if (tmp != out) | |
4839 | emit_move_insn (out, tmp); | |
4840 | ||
4841 | return 1; /* DONE */ | |
4842 | } | |
4843 | ||
4844 | diff = ct - cf; | |
4845 | if (diff < 0) | |
4846 | { | |
4847 | HOST_WIDE_INT tmp; | |
4848 | tmp = ct, ct = cf, cf = tmp; | |
4849 | diff = -diff; | |
4850 | compare_code = reverse_condition (compare_code); | |
4851 | code = reverse_condition (code); | |
4852 | } | |
4853 | if (diff == 1 || diff == 2 || diff == 4 || diff == 8 | |
4854 | || diff == 3 || diff == 5 || diff == 9) | |
4855 | { | |
4856 | /* | |
4857 | * xorl dest,dest | |
4858 | * cmpl op1,op2 | |
4859 | * setcc dest | |
4860 | * lea cf(dest*(ct-cf)),dest | |
4861 | * | |
4862 | * Size 14. | |
4863 | * | |
4864 | * This also catches the degenerate setcc-only case. | |
4865 | */ | |
4866 | ||
4867 | rtx tmp; | |
4868 | int nops; | |
4869 | ||
4870 | out = emit_store_flag (out, code, ix86_compare_op0, | |
4871 | ix86_compare_op1, VOIDmode, 0, 1); | |
4872 | ||
4873 | nops = 0; | |
4874 | if (diff == 1) | |
4875 | tmp = out; | |
4876 | else | |
4877 | { | |
4878 | tmp = gen_rtx_MULT (SImode, out, GEN_INT (diff & ~1)); | |
4879 | nops++; | |
4880 | if (diff & 1) | |
4881 | { | |
4882 | tmp = gen_rtx_PLUS (SImode, tmp, out); | |
4883 | nops++; | |
4884 | } | |
4885 | } | |
4886 | if (cf != 0) | |
4887 | { | |
4888 | tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (cf)); | |
4889 | nops++; | |
4890 | } | |
4891 | if (tmp != out) | |
4892 | { | |
4893 | if (nops == 0) | |
4894 | emit_move_insn (out, tmp); | |
4895 | else if (nops == 1) | |
4896 | { | |
4897 | rtx clob; | |
4898 | ||
4899 | clob = gen_rtx_REG (CCmode, FLAGS_REG); | |
4900 | clob = gen_rtx_CLOBBER (VOIDmode, clob); | |
4901 | ||
4902 | tmp = gen_rtx_SET (VOIDmode, out, tmp); | |
4903 | tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob)); | |
4904 | emit_insn (tmp); | |
4905 | } | |
4906 | else | |
4907 | emit_insn (gen_rtx_SET (VOIDmode, out, tmp)); | |
4908 | } | |
4909 | if (out != operands[0]) | |
4910 | emit_move_insn (operands[0], out); | |
4911 | ||
4912 | return 1; /* DONE */ | |
4913 | } | |
4914 | ||
4915 | /* | |
4916 | * General case: Jumpful: | |
4917 | * xorl dest,dest cmpl op1, op2 | |
4918 | * cmpl op1, op2 movl ct, dest | |
4919 | * setcc dest jcc 1f | |
4920 | * decl dest movl cf, dest | |
4921 | * andl (cf-ct),dest 1: | |
4922 | * addl ct,dest | |
4923 | * | |
4924 | * Size 20. Size 14. | |
4925 | * | |
4926 | * This is reasonably steep, but branch mispredict costs are | |
4927 | * high on modern cpus, so consider failing only if optimizing | |
4928 | * for space. | |
4929 | * | |
4930 | * %%% Parameterize branch_cost on the tuning architecture, then | |
4931 | * use that. The 80386 couldn't care less about mispredicts. | |
4932 | */ | |
4933 | ||
4934 | if (!optimize_size && !TARGET_CMOVE) | |
4935 | { | |
4936 | if (ct == 0) | |
4937 | { | |
4938 | ct = cf; | |
4939 | cf = 0; | |
4940 | compare_code = reverse_condition (compare_code); | |
4941 | code = reverse_condition (code); | |
4942 | } | |
4943 | ||
4944 | out = emit_store_flag (out, code, ix86_compare_op0, | |
4945 | ix86_compare_op1, VOIDmode, 0, 1); | |
4946 | ||
4947 | emit_insn (gen_addsi3 (out, out, constm1_rtx)); | |
4948 | emit_insn (gen_andsi3 (out, out, GEN_INT (cf-ct))); | |
4949 | if (ct != 0) | |
4950 | emit_insn (gen_addsi3 (out, out, GEN_INT (ct))); | |
4951 | if (out != operands[0]) | |
4952 | emit_move_insn (operands[0], out); | |
4953 | ||
4954 | return 1; /* DONE */ | |
4955 | } | |
4956 | } | |
4957 | ||
4958 | if (!TARGET_CMOVE) | |
4959 | { | |
4960 | /* Try a few things more with specific constants and a variable. */ | |
4961 | ||
78a0d70c | 4962 | optab op; |
e075ae69 RH |
4963 | rtx var, orig_out, out, tmp; |
4964 | ||
4965 | if (optimize_size) | |
4966 | return 0; /* FAIL */ | |
4967 | ||
4968 | /* If one of the two operands is an interesting constant, load a | |
4969 | constant with the above and mask it in with a logical operation. */ | |
4970 | ||
4971 | if (GET_CODE (operands[2]) == CONST_INT) | |
4972 | { | |
4973 | var = operands[3]; | |
4974 | if (INTVAL (operands[2]) == 0) | |
4975 | operands[3] = constm1_rtx, op = and_optab; | |
4976 | else if (INTVAL (operands[2]) == -1) | |
4977 | operands[3] = const0_rtx, op = ior_optab; | |
78a0d70c ZW |
4978 | else |
4979 | return 0; /* FAIL */ | |
e075ae69 RH |
4980 | } |
4981 | else if (GET_CODE (operands[3]) == CONST_INT) | |
4982 | { | |
4983 | var = operands[2]; | |
4984 | if (INTVAL (operands[3]) == 0) | |
4985 | operands[2] = constm1_rtx, op = and_optab; | |
4986 | else if (INTVAL (operands[3]) == -1) | |
4987 | operands[2] = const0_rtx, op = ior_optab; | |
78a0d70c ZW |
4988 | else |
4989 | return 0; /* FAIL */ | |
e075ae69 | 4990 | } |
78a0d70c | 4991 | else |
e075ae69 RH |
4992 | return 0; /* FAIL */ |
4993 | ||
4994 | orig_out = operands[0]; | |
4995 | tmp = gen_reg_rtx (GET_MODE (orig_out)); | |
4996 | operands[0] = tmp; | |
4997 | ||
4998 | /* Recurse to get the constant loaded. */ | |
4999 | if (ix86_expand_int_movcc (operands) == 0) | |
5000 | return 0; /* FAIL */ | |
5001 | ||
5002 | /* Mask in the interesting variable. */ | |
5003 | out = expand_binop (GET_MODE (orig_out), op, var, tmp, orig_out, 0, | |
5004 | OPTAB_WIDEN); | |
5005 | if (out != orig_out) | |
5006 | emit_move_insn (orig_out, out); | |
5007 | ||
5008 | return 1; /* DONE */ | |
5009 | } | |
5010 | ||
5011 | /* | |
5012 | * For comparison with above, | |
5013 | * | |
5014 | * movl cf,dest | |
5015 | * movl ct,tmp | |
5016 | * cmpl op1,op2 | |
5017 | * cmovcc tmp,dest | |
5018 | * | |
5019 | * Size 15. | |
5020 | */ | |
5021 | ||
5022 | if (! nonimmediate_operand (operands[2], GET_MODE (operands[0]))) | |
5023 | operands[2] = force_reg (GET_MODE (operands[0]), operands[2]); | |
5024 | if (! nonimmediate_operand (operands[3], GET_MODE (operands[0]))) | |
5025 | operands[3] = force_reg (GET_MODE (operands[0]), operands[3]); | |
5026 | ||
5027 | emit_insn (compare_seq); | |
5028 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
5029 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
5030 | compare_op, operands[2], | |
5031 | operands[3]))); | |
5032 | ||
5033 | return 1; /* DONE */ | |
e9a25f70 | 5034 | } |
e075ae69 | 5035 | |
32b5b1aa | 5036 | int |
e075ae69 RH |
5037 | ix86_expand_fp_movcc (operands) |
5038 | rtx operands[]; | |
32b5b1aa | 5039 | { |
e075ae69 RH |
5040 | enum rtx_code code; |
5041 | enum machine_mode mode; | |
5042 | rtx tmp; | |
32b5b1aa | 5043 | |
e075ae69 RH |
5044 | /* The floating point conditional move instructions don't directly |
5045 | support conditions resulting from a signed integer comparison. */ | |
32b5b1aa | 5046 | |
e075ae69 RH |
5047 | code = GET_CODE (operands[1]); |
5048 | switch (code) | |
5049 | { | |
5050 | case LT: | |
5051 | case LE: | |
5052 | case GE: | |
5053 | case GT: | |
5054 | tmp = gen_reg_rtx (QImode); | |
5055 | ix86_expand_setcc (code, 0, tmp); | |
5056 | code = NE; | |
5057 | ix86_compare_op0 = tmp; | |
5058 | ix86_compare_op1 = const0_rtx; | |
5059 | break; | |
5060 | ||
5061 | default: | |
5062 | break; | |
5063 | } | |
e9a25f70 | 5064 | |
e075ae69 RH |
5065 | mode = SELECT_CC_MODE (code, ix86_compare_op0, ix86_compare_op1); |
5066 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, FLAGS_REG), | |
5067 | gen_rtx_COMPARE (mode, | |
5068 | ix86_compare_op0, | |
5069 | ix86_compare_op1))); | |
5070 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
5071 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
5072 | gen_rtx_fmt_ee (code, VOIDmode, | |
5073 | gen_rtx_REG (mode, FLAGS_REG), | |
5074 | const0_rtx), | |
5075 | operands[2], | |
5076 | operands[3]))); | |
32b5b1aa | 5077 | |
e075ae69 | 5078 | return 1; |
32b5b1aa SC |
5079 | } |
5080 | ||
2450a057 JH |
5081 | /* Split operands 0 and 1 into SImode parts. Similar to split_di, but |
5082 | works for floating pointer parameters and nonoffsetable memories. | |
5083 | For pushes, it returns just stack offsets; the values will be saved | |
5084 | in the right order. Maximally three parts are generated. */ | |
5085 | ||
5086 | static void | |
5087 | ix86_split_to_parts (operand, parts, mode) | |
5088 | rtx operand; | |
5089 | rtx *parts; | |
5090 | enum machine_mode mode; | |
32b5b1aa | 5091 | { |
2450a057 JH |
5092 | int size = GET_MODE_SIZE (mode) / 4; |
5093 | ||
5094 | if (size < 2 || size > 3) | |
5095 | abort (); | |
5096 | ||
d7a29404 JH |
5097 | /* Optimize constant pool reference to immediates. This is used by fp moves, |
5098 | that force all constants to memory to allow combining. */ | |
5099 | ||
5100 | if (GET_CODE (operand) == MEM | |
5101 | && GET_CODE (XEXP (operand, 0)) == SYMBOL_REF | |
5102 | && CONSTANT_POOL_ADDRESS_P (XEXP (operand, 0))) | |
5103 | operand = get_pool_constant (XEXP (operand, 0)); | |
5104 | ||
2450a057 | 5105 | if (GET_CODE (operand) == MEM && !offsettable_memref_p (operand)) |
e075ae69 | 5106 | { |
2450a057 JH |
5107 | /* The only non-offsetable memories we handle are pushes. */ |
5108 | if (! push_operand (operand, VOIDmode)) | |
5109 | abort (); | |
5110 | ||
5111 | PUT_MODE (operand, SImode); | |
5112 | parts[0] = parts[1] = parts[2] = operand; | |
5113 | } | |
5114 | else | |
5115 | { | |
5116 | if (mode == DImode) | |
5117 | split_di (&operand, 1, &parts[0], &parts[1]); | |
5118 | else | |
e075ae69 | 5119 | { |
2450a057 JH |
5120 | if (REG_P (operand)) |
5121 | { | |
5122 | if (!reload_completed) | |
5123 | abort (); | |
5124 | parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0); | |
5125 | parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1); | |
5126 | if (size == 3) | |
5127 | parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2); | |
5128 | } | |
5129 | else if (offsettable_memref_p (operand)) | |
5130 | { | |
5131 | PUT_MODE (operand, SImode); | |
5132 | parts[0] = operand; | |
5133 | parts[1] = adj_offsettable_operand (operand, 4); | |
5134 | if (size == 3) | |
5135 | parts[2] = adj_offsettable_operand (operand, 8); | |
5136 | } | |
5137 | else if (GET_CODE (operand) == CONST_DOUBLE) | |
5138 | { | |
5139 | REAL_VALUE_TYPE r; | |
5140 | long l[3]; | |
5141 | ||
5142 | REAL_VALUE_FROM_CONST_DOUBLE (r, operand); | |
5143 | switch (mode) | |
5144 | { | |
5145 | case XFmode: | |
5146 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
5147 | parts[2] = GEN_INT (l[2]); | |
5148 | break; | |
5149 | case DFmode: | |
5150 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); | |
5151 | break; | |
5152 | default: | |
5153 | abort (); | |
5154 | } | |
5155 | parts[1] = GEN_INT (l[1]); | |
5156 | parts[0] = GEN_INT (l[0]); | |
5157 | } | |
5158 | else | |
5159 | abort (); | |
e075ae69 | 5160 | } |
2450a057 JH |
5161 | } |
5162 | ||
5163 | return; | |
5164 | } | |
5165 | ||
5166 | /* Emit insns to perform a move or push of DI, DF, and XF values. | |
5167 | Return false when normal moves are needed; true when all required | |
5168 | insns have been emitted. Operands 2-4 contain the input values | |
5169 | int the correct order; operands 5-7 contain the output values. */ | |
5170 | ||
5171 | int | |
5172 | ix86_split_long_move (operands1) | |
5173 | rtx operands1[]; | |
5174 | { | |
5175 | rtx part[2][3]; | |
5176 | rtx operands[2]; | |
5177 | int size = GET_MODE_SIZE (GET_MODE (operands1[0])) / 4; | |
5178 | int push = 0; | |
5179 | int collisions = 0; | |
5180 | ||
5181 | /* Make our own copy to avoid clobbering the operands. */ | |
5182 | operands[0] = copy_rtx (operands1[0]); | |
5183 | operands[1] = copy_rtx (operands1[1]); | |
5184 | ||
5185 | if (size < 2 || size > 3) | |
5186 | abort (); | |
5187 | ||
5188 | /* The only non-offsettable memory we handle is push. */ | |
5189 | if (push_operand (operands[0], VOIDmode)) | |
5190 | push = 1; | |
5191 | else if (GET_CODE (operands[0]) == MEM | |
5192 | && ! offsettable_memref_p (operands[0])) | |
5193 | abort (); | |
5194 | ||
5195 | ix86_split_to_parts (operands[0], part[0], GET_MODE (operands1[0])); | |
5196 | ix86_split_to_parts (operands[1], part[1], GET_MODE (operands1[0])); | |
5197 | ||
5198 | /* When emitting push, take care for source operands on the stack. */ | |
5199 | if (push && GET_CODE (operands[1]) == MEM | |
5200 | && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) | |
5201 | { | |
5202 | if (size == 3) | |
5203 | part[1][1] = part[1][2]; | |
5204 | part[1][0] = part[1][1]; | |
5205 | } | |
5206 | ||
5207 | /* We need to do copy in the right order in case an address register | |
5208 | of the source overlaps the destination. */ | |
5209 | if (REG_P (part[0][0]) && GET_CODE (part[1][0]) == MEM) | |
5210 | { | |
5211 | if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))) | |
5212 | collisions++; | |
5213 | if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0))) | |
5214 | collisions++; | |
5215 | if (size == 3 | |
5216 | && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0))) | |
5217 | collisions++; | |
5218 | ||
5219 | /* Collision in the middle part can be handled by reordering. */ | |
5220 | if (collisions == 1 && size == 3 | |
5221 | && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0))) | |
e075ae69 | 5222 | { |
2450a057 JH |
5223 | rtx tmp; |
5224 | tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp; | |
5225 | tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp; | |
5226 | } | |
e075ae69 | 5227 | |
2450a057 JH |
5228 | /* If there are more collisions, we can't handle it by reordering. |
5229 | Do an lea to the last part and use only one colliding move. */ | |
5230 | else if (collisions > 1) | |
5231 | { | |
5232 | collisions = 1; | |
5233 | emit_insn (gen_rtx_SET (VOIDmode, part[0][size - 1], | |
5234 | XEXP (part[1][0], 0))); | |
5235 | part[1][0] = change_address (part[1][0], SImode, part[0][size - 1]); | |
5236 | part[1][1] = adj_offsettable_operand (part[1][0], 4); | |
5237 | if (size == 3) | |
5238 | part[1][2] = adj_offsettable_operand (part[1][0], 8); | |
5239 | } | |
5240 | } | |
5241 | ||
5242 | if (push) | |
5243 | { | |
5244 | if (size == 3) | |
5245 | emit_insn (gen_push (part[1][2])); | |
5246 | emit_insn (gen_push (part[1][1])); | |
5247 | emit_insn (gen_push (part[1][0])); | |
5248 | return 1; | |
5249 | } | |
5250 | ||
5251 | /* Choose correct order to not overwrite the source before it is copied. */ | |
5252 | if ((REG_P (part[0][0]) | |
5253 | && REG_P (part[1][1]) | |
5254 | && (REGNO (part[0][0]) == REGNO (part[1][1]) | |
5255 | || (size == 3 | |
5256 | && REGNO (part[0][0]) == REGNO (part[1][2])))) | |
5257 | || (collisions > 0 | |
5258 | && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))) | |
5259 | { | |
5260 | if (size == 3) | |
5261 | { | |
5262 | operands1[2] = part[0][2]; | |
5263 | operands1[3] = part[0][1]; | |
5264 | operands1[4] = part[0][0]; | |
5265 | operands1[5] = part[1][2]; | |
5266 | operands1[6] = part[1][1]; | |
5267 | operands1[7] = part[1][0]; | |
5268 | } | |
5269 | else | |
5270 | { | |
5271 | operands1[2] = part[0][1]; | |
5272 | operands1[3] = part[0][0]; | |
5273 | operands1[5] = part[1][1]; | |
5274 | operands1[6] = part[1][0]; | |
5275 | } | |
5276 | } | |
5277 | else | |
5278 | { | |
5279 | if (size == 3) | |
5280 | { | |
5281 | operands1[2] = part[0][0]; | |
5282 | operands1[3] = part[0][1]; | |
5283 | operands1[4] = part[0][2]; | |
5284 | operands1[5] = part[1][0]; | |
5285 | operands1[6] = part[1][1]; | |
5286 | operands1[7] = part[1][2]; | |
5287 | } | |
5288 | else | |
5289 | { | |
5290 | operands1[2] = part[0][0]; | |
5291 | operands1[3] = part[0][1]; | |
5292 | operands1[5] = part[1][0]; | |
5293 | operands1[6] = part[1][1]; | |
e075ae69 RH |
5294 | } |
5295 | } | |
32b5b1aa | 5296 | |
e9a25f70 | 5297 | return 0; |
32b5b1aa | 5298 | } |
32b5b1aa | 5299 | |
e075ae69 RH |
5300 | void |
5301 | ix86_split_ashldi (operands, scratch) | |
5302 | rtx *operands, scratch; | |
32b5b1aa | 5303 | { |
e075ae69 RH |
5304 | rtx low[2], high[2]; |
5305 | int count; | |
b985a30f | 5306 | |
e075ae69 RH |
5307 | if (GET_CODE (operands[2]) == CONST_INT) |
5308 | { | |
5309 | split_di (operands, 2, low, high); | |
5310 | count = INTVAL (operands[2]) & 63; | |
32b5b1aa | 5311 | |
e075ae69 RH |
5312 | if (count >= 32) |
5313 | { | |
5314 | emit_move_insn (high[0], low[1]); | |
5315 | emit_move_insn (low[0], const0_rtx); | |
b985a30f | 5316 | |
e075ae69 RH |
5317 | if (count > 32) |
5318 | emit_insn (gen_ashlsi3 (high[0], high[0], GEN_INT (count - 32))); | |
5319 | } | |
5320 | else | |
5321 | { | |
5322 | if (!rtx_equal_p (operands[0], operands[1])) | |
5323 | emit_move_insn (operands[0], operands[1]); | |
5324 | emit_insn (gen_x86_shld_1 (high[0], low[0], GEN_INT (count))); | |
5325 | emit_insn (gen_ashlsi3 (low[0], low[0], GEN_INT (count))); | |
5326 | } | |
5327 | } | |
5328 | else | |
5329 | { | |
5330 | if (!rtx_equal_p (operands[0], operands[1])) | |
5331 | emit_move_insn (operands[0], operands[1]); | |
b985a30f | 5332 | |
e075ae69 | 5333 | split_di (operands, 1, low, high); |
b985a30f | 5334 | |
e075ae69 RH |
5335 | emit_insn (gen_x86_shld_1 (high[0], low[0], operands[2])); |
5336 | emit_insn (gen_ashlsi3 (low[0], low[0], operands[2])); | |
32b5b1aa | 5337 | |
e075ae69 RH |
5338 | if (TARGET_CMOVE && (! reload_completed || scratch)) |
5339 | { | |
5340 | if (! reload_completed) | |
5341 | scratch = force_reg (SImode, const0_rtx); | |
5342 | else | |
5343 | emit_move_insn (scratch, const0_rtx); | |
5344 | ||
5345 | emit_insn (gen_x86_shift_adj_1 (high[0], low[0], operands[2], | |
5346 | scratch)); | |
5347 | } | |
5348 | else | |
5349 | emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2])); | |
5350 | } | |
e9a25f70 | 5351 | } |
32b5b1aa | 5352 | |
e075ae69 RH |
5353 | void |
5354 | ix86_split_ashrdi (operands, scratch) | |
5355 | rtx *operands, scratch; | |
32b5b1aa | 5356 | { |
e075ae69 RH |
5357 | rtx low[2], high[2]; |
5358 | int count; | |
32b5b1aa | 5359 | |
e075ae69 RH |
5360 | if (GET_CODE (operands[2]) == CONST_INT) |
5361 | { | |
5362 | split_di (operands, 2, low, high); | |
5363 | count = INTVAL (operands[2]) & 63; | |
32b5b1aa | 5364 | |
e075ae69 RH |
5365 | if (count >= 32) |
5366 | { | |
5367 | emit_move_insn (low[0], high[1]); | |
32b5b1aa | 5368 | |
e075ae69 RH |
5369 | if (! reload_completed) |
5370 | emit_insn (gen_ashrsi3 (high[0], low[0], GEN_INT (31))); | |
5371 | else | |
5372 | { | |
5373 | emit_move_insn (high[0], low[0]); | |
5374 | emit_insn (gen_ashrsi3 (high[0], high[0], GEN_INT (31))); | |
5375 | } | |
5376 | ||
5377 | if (count > 32) | |
5378 | emit_insn (gen_ashrsi3 (low[0], low[0], GEN_INT (count - 32))); | |
5379 | } | |
5380 | else | |
5381 | { | |
5382 | if (!rtx_equal_p (operands[0], operands[1])) | |
5383 | emit_move_insn (operands[0], operands[1]); | |
5384 | emit_insn (gen_x86_shrd_1 (low[0], high[0], GEN_INT (count))); | |
5385 | emit_insn (gen_ashrsi3 (high[0], high[0], GEN_INT (count))); | |
5386 | } | |
5387 | } | |
5388 | else | |
32b5b1aa | 5389 | { |
e075ae69 RH |
5390 | if (!rtx_equal_p (operands[0], operands[1])) |
5391 | emit_move_insn (operands[0], operands[1]); | |
5392 | ||
5393 | split_di (operands, 1, low, high); | |
5394 | ||
5395 | emit_insn (gen_x86_shrd_1 (low[0], high[0], operands[2])); | |
5396 | emit_insn (gen_ashrsi3 (high[0], high[0], operands[2])); | |
5397 | ||
5398 | if (TARGET_CMOVE && (!reload_completed || scratch)) | |
5399 | { | |
5400 | if (! reload_completed) | |
5401 | scratch = gen_reg_rtx (SImode); | |
5402 | emit_move_insn (scratch, high[0]); | |
5403 | emit_insn (gen_ashrsi3 (scratch, scratch, GEN_INT (31))); | |
5404 | emit_insn (gen_x86_shift_adj_1 (low[0], high[0], operands[2], | |
5405 | scratch)); | |
5406 | } | |
5407 | else | |
5408 | emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2])); | |
32b5b1aa | 5409 | } |
e075ae69 | 5410 | } |
32b5b1aa | 5411 | |
e075ae69 RH |
5412 | void |
5413 | ix86_split_lshrdi (operands, scratch) | |
5414 | rtx *operands, scratch; | |
5415 | { | |
5416 | rtx low[2], high[2]; | |
5417 | int count; | |
32b5b1aa | 5418 | |
e075ae69 | 5419 | if (GET_CODE (operands[2]) == CONST_INT) |
32b5b1aa | 5420 | { |
e075ae69 RH |
5421 | split_di (operands, 2, low, high); |
5422 | count = INTVAL (operands[2]) & 63; | |
5423 | ||
5424 | if (count >= 32) | |
c7271385 | 5425 | { |
e075ae69 RH |
5426 | emit_move_insn (low[0], high[1]); |
5427 | emit_move_insn (high[0], const0_rtx); | |
32b5b1aa | 5428 | |
e075ae69 RH |
5429 | if (count > 32) |
5430 | emit_insn (gen_lshrsi3 (low[0], low[0], GEN_INT (count - 32))); | |
5431 | } | |
5432 | else | |
5433 | { | |
5434 | if (!rtx_equal_p (operands[0], operands[1])) | |
5435 | emit_move_insn (operands[0], operands[1]); | |
5436 | emit_insn (gen_x86_shrd_1 (low[0], high[0], GEN_INT (count))); | |
5437 | emit_insn (gen_lshrsi3 (high[0], high[0], GEN_INT (count))); | |
5438 | } | |
32b5b1aa | 5439 | } |
e075ae69 RH |
5440 | else |
5441 | { | |
5442 | if (!rtx_equal_p (operands[0], operands[1])) | |
5443 | emit_move_insn (operands[0], operands[1]); | |
32b5b1aa | 5444 | |
e075ae69 RH |
5445 | split_di (operands, 1, low, high); |
5446 | ||
5447 | emit_insn (gen_x86_shrd_1 (low[0], high[0], operands[2])); | |
5448 | emit_insn (gen_lshrsi3 (high[0], high[0], operands[2])); | |
5449 | ||
5450 | /* Heh. By reversing the arguments, we can reuse this pattern. */ | |
5451 | if (TARGET_CMOVE && (! reload_completed || scratch)) | |
5452 | { | |
5453 | if (! reload_completed) | |
5454 | scratch = force_reg (SImode, const0_rtx); | |
5455 | else | |
5456 | emit_move_insn (scratch, const0_rtx); | |
5457 | ||
5458 | emit_insn (gen_x86_shift_adj_1 (low[0], high[0], operands[2], | |
5459 | scratch)); | |
5460 | } | |
5461 | else | |
5462 | emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2])); | |
5463 | } | |
32b5b1aa | 5464 | } |
3f803cd9 | 5465 | |
e075ae69 RH |
5466 | /* Expand the appropriate insns for doing strlen if not just doing |
5467 | repnz; scasb | |
5468 | ||
5469 | out = result, initialized with the start address | |
5470 | align_rtx = alignment of the address. | |
5471 | scratch = scratch register, initialized with the startaddress when | |
5472 | not aligned, otherwise undefined | |
3f803cd9 SC |
5473 | |
5474 | This is just the body. It needs the initialisations mentioned above and | |
5475 | some address computing at the end. These things are done in i386.md. */ | |
5476 | ||
e075ae69 RH |
5477 | void |
5478 | ix86_expand_strlensi_unroll_1 (out, align_rtx, scratch) | |
5479 | rtx out, align_rtx, scratch; | |
3f803cd9 | 5480 | { |
e075ae69 RH |
5481 | int align; |
5482 | rtx tmp; | |
5483 | rtx align_2_label = NULL_RTX; | |
5484 | rtx align_3_label = NULL_RTX; | |
5485 | rtx align_4_label = gen_label_rtx (); | |
5486 | rtx end_0_label = gen_label_rtx (); | |
e075ae69 RH |
5487 | rtx mem; |
5488 | rtx flags = gen_rtx_REG (CCNOmode, FLAGS_REG); | |
e2e52e1b | 5489 | rtx tmpreg = gen_reg_rtx (SImode); |
e075ae69 RH |
5490 | |
5491 | align = 0; | |
5492 | if (GET_CODE (align_rtx) == CONST_INT) | |
5493 | align = INTVAL (align_rtx); | |
3f803cd9 | 5494 | |
e9a25f70 | 5495 | /* Loop to check 1..3 bytes for null to get an aligned pointer. */ |
3f803cd9 | 5496 | |
e9a25f70 | 5497 | /* Is there a known alignment and is it less than 4? */ |
e075ae69 | 5498 | if (align < 4) |
3f803cd9 | 5499 | { |
e9a25f70 | 5500 | /* Is there a known alignment and is it not 2? */ |
e075ae69 | 5501 | if (align != 2) |
3f803cd9 | 5502 | { |
e075ae69 RH |
5503 | align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */ |
5504 | align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */ | |
5505 | ||
5506 | /* Leave just the 3 lower bits. */ | |
5507 | align_rtx = expand_binop (SImode, and_optab, scratch, GEN_INT (3), | |
5508 | NULL_RTX, 0, OPTAB_WIDEN); | |
5509 | ||
5510 | emit_insn (gen_cmpsi_0 (align_rtx, const0_rtx)); | |
5511 | ||
5512 | tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx); | |
5513 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
5514 | gen_rtx_LABEL_REF (VOIDmode, | |
5515 | align_4_label), | |
5516 | pc_rtx); | |
5517 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
5518 | ||
5519 | emit_insn (gen_cmpsi_1 (align_rtx, GEN_INT (2))); | |
5520 | ||
5521 | tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx); | |
5522 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
5523 | gen_rtx_LABEL_REF (VOIDmode, | |
5524 | align_2_label), | |
5525 | pc_rtx); | |
5526 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
5527 | ||
5528 | tmp = gen_rtx_GTU (VOIDmode, flags, const0_rtx); | |
5529 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
5530 | gen_rtx_LABEL_REF (VOIDmode, | |
5531 | align_3_label), | |
5532 | pc_rtx); | |
5533 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
3f803cd9 SC |
5534 | } |
5535 | else | |
5536 | { | |
e9a25f70 JL |
5537 | /* Since the alignment is 2, we have to check 2 or 0 bytes; |
5538 | check if is aligned to 4 - byte. */ | |
e9a25f70 | 5539 | |
e075ae69 RH |
5540 | align_rtx = expand_binop (SImode, and_optab, scratch, GEN_INT (2), |
5541 | NULL_RTX, 0, OPTAB_WIDEN); | |
5542 | ||
5543 | emit_insn (gen_cmpsi_0 (align_rtx, const0_rtx)); | |
5544 | ||
5545 | tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx); | |
5546 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
5547 | gen_rtx_LABEL_REF (VOIDmode, | |
5548 | align_4_label), | |
5549 | pc_rtx); | |
5550 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
3f803cd9 SC |
5551 | } |
5552 | ||
e075ae69 | 5553 | mem = gen_rtx_MEM (QImode, out); |
e9a25f70 | 5554 | |
e075ae69 | 5555 | /* Now compare the bytes. */ |
e9a25f70 | 5556 | |
e075ae69 RH |
5557 | /* Compare the first n unaligned byte on a byte per byte basis. */ |
5558 | emit_insn (gen_cmpqi_0 (mem, const0_rtx)); | |
e9a25f70 | 5559 | |
e075ae69 RH |
5560 | tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx); |
5561 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
5562 | gen_rtx_LABEL_REF (VOIDmode, end_0_label), | |
5563 | pc_rtx); | |
5564 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
3f803cd9 | 5565 | |
e075ae69 RH |
5566 | /* Increment the address. */ |
5567 | emit_insn (gen_addsi3 (out, out, const1_rtx)); | |
e9a25f70 | 5568 | |
e075ae69 RH |
5569 | /* Not needed with an alignment of 2 */ |
5570 | if (align != 2) | |
5571 | { | |
5572 | emit_label (align_2_label); | |
3f803cd9 | 5573 | |
e075ae69 | 5574 | emit_insn (gen_cmpqi_0 (mem, const0_rtx)); |
3f803cd9 | 5575 | |
e075ae69 RH |
5576 | tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx); |
5577 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
5578 | gen_rtx_LABEL_REF (VOIDmode, | |
5579 | end_0_label), | |
5580 | pc_rtx); | |
5581 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
5582 | ||
5583 | emit_insn (gen_addsi3 (out, out, const1_rtx)); | |
5584 | ||
5585 | emit_label (align_3_label); | |
5586 | } | |
5587 | ||
5588 | emit_insn (gen_cmpqi_0 (mem, const0_rtx)); | |
e9a25f70 | 5589 | |
e075ae69 RH |
5590 | tmp = gen_rtx_EQ (VOIDmode, flags, const0_rtx); |
5591 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
5592 | gen_rtx_LABEL_REF (VOIDmode, end_0_label), | |
5593 | pc_rtx); | |
5594 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
5595 | ||
5596 | emit_insn (gen_addsi3 (out, out, const1_rtx)); | |
3f803cd9 SC |
5597 | } |
5598 | ||
e075ae69 RH |
5599 | /* Generate loop to check 4 bytes at a time. It is not a good idea to |
5600 | align this loop. It gives only huge programs, but does not help to | |
5601 | speed up. */ | |
5602 | emit_label (align_4_label); | |
3f803cd9 | 5603 | |
e075ae69 RH |
5604 | mem = gen_rtx_MEM (SImode, out); |
5605 | emit_move_insn (scratch, mem); | |
e075ae69 | 5606 | emit_insn (gen_addsi3 (out, out, GEN_INT (4))); |
e075ae69 | 5607 | |
e2e52e1b JH |
5608 | /* This formula yields a nonzero result iff one of the bytes is zero. |
5609 | This saves three branches inside loop and many cycles. */ | |
5610 | ||
5611 | emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101))); | |
5612 | emit_insn (gen_one_cmplsi2 (scratch, scratch)); | |
5613 | emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch)); | |
5614 | emit_insn (gen_andsi3 (tmpreg, tmpreg, GEN_INT (0x80808080))); | |
5615 | emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1, 0, align_4_label); | |
5616 | ||
5617 | if (TARGET_CMOVE) | |
5618 | { | |
5619 | rtx reg = gen_reg_rtx (SImode); | |
5620 | emit_move_insn (reg, tmpreg); | |
5621 | emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16))); | |
5622 | ||
5623 | /* If zero is not in the first two bytes, move two bytes forward. */ | |
5624 | emit_insn (gen_testsi_1 (tmpreg, GEN_INT (0x8080))); | |
5625 | tmp = gen_rtx_REG (CCNOmode, FLAGS_REG); | |
5626 | tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); | |
5627 | emit_insn (gen_rtx_SET (VOIDmode, tmpreg, | |
5628 | gen_rtx_IF_THEN_ELSE (SImode, tmp, | |
5629 | reg, | |
5630 | tmpreg))); | |
5631 | /* Emit lea manually to avoid clobbering of flags. */ | |
5632 | emit_insn (gen_rtx_SET (SImode, reg, | |
5633 | gen_rtx_PLUS (SImode, out, GEN_INT (2)))); | |
5634 | ||
5635 | tmp = gen_rtx_REG (CCNOmode, FLAGS_REG); | |
5636 | tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); | |
5637 | emit_insn (gen_rtx_SET (VOIDmode, out, | |
5638 | gen_rtx_IF_THEN_ELSE (SImode, tmp, | |
5639 | reg, | |
5640 | out))); | |
5641 | ||
5642 | } | |
5643 | else | |
5644 | { | |
5645 | rtx end_2_label = gen_label_rtx (); | |
5646 | /* Is zero in the first two bytes? */ | |
5647 | ||
5648 | emit_insn (gen_testsi_1 (tmpreg, GEN_INT (0x8080))); | |
5649 | tmp = gen_rtx_REG (CCNOmode, FLAGS_REG); | |
5650 | tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx); | |
5651 | tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, | |
5652 | gen_rtx_LABEL_REF (VOIDmode, end_2_label), | |
5653 | pc_rtx); | |
5654 | tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); | |
5655 | JUMP_LABEL (tmp) = end_2_label; | |
5656 | ||
5657 | /* Not in the first two. Move two bytes forward. */ | |
5658 | emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16))); | |
5659 | emit_insn (gen_addsi3 (out, out, GEN_INT (2))); | |
5660 | ||
5661 | emit_label (end_2_label); | |
5662 | ||
5663 | } | |
5664 | ||
5665 | /* Avoid branch in fixing the byte. */ | |
5666 | tmpreg = gen_lowpart (QImode, tmpreg); | |
5667 | emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg)); | |
5668 | emit_insn (gen_subsi3_carry (out, out, GEN_INT (3))); | |
e075ae69 RH |
5669 | |
5670 | emit_label (end_0_label); | |
5671 | } | |
5672 | \f | |
e075ae69 RH |
5673 | /* Clear stack slot assignments remembered from previous functions. |
5674 | This is called from INIT_EXPANDERS once before RTL is emitted for each | |
5675 | function. */ | |
5676 | ||
36edd3cc BS |
5677 | static void |
5678 | ix86_init_machine_status (p) | |
1526a060 | 5679 | struct function *p; |
e075ae69 RH |
5680 | { |
5681 | enum machine_mode mode; | |
5682 | int n; | |
36edd3cc BS |
5683 | p->machine |
5684 | = (struct machine_function *) xmalloc (sizeof (struct machine_function)); | |
e075ae69 RH |
5685 | |
5686 | for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; | |
5687 | mode = (enum machine_mode) ((int) mode + 1)) | |
5688 | for (n = 0; n < MAX_386_STACK_LOCALS; n++) | |
5689 | ix86_stack_locals[(int) mode][n] = NULL_RTX; | |
e075ae69 RH |
5690 | } |
5691 | ||
1526a060 BS |
5692 | /* Mark machine specific bits of P for GC. */ |
5693 | static void | |
5694 | ix86_mark_machine_status (p) | |
5695 | struct function *p; | |
5696 | { | |
5697 | enum machine_mode mode; | |
5698 | int n; | |
5699 | ||
5700 | for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; | |
5701 | mode = (enum machine_mode) ((int) mode + 1)) | |
5702 | for (n = 0; n < MAX_386_STACK_LOCALS; n++) | |
5703 | ggc_mark_rtx (p->machine->stack_locals[(int) mode][n]); | |
5704 | } | |
5705 | ||
e075ae69 RH |
5706 | /* Return a MEM corresponding to a stack slot with mode MODE. |
5707 | Allocate a new slot if necessary. | |
5708 | ||
5709 | The RTL for a function can have several slots available: N is | |
5710 | which slot to use. */ | |
5711 | ||
5712 | rtx | |
5713 | assign_386_stack_local (mode, n) | |
5714 | enum machine_mode mode; | |
5715 | int n; | |
5716 | { | |
5717 | if (n < 0 || n >= MAX_386_STACK_LOCALS) | |
5718 | abort (); | |
5719 | ||
5720 | if (ix86_stack_locals[(int) mode][n] == NULL_RTX) | |
5721 | ix86_stack_locals[(int) mode][n] | |
5722 | = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
5723 | ||
5724 | return ix86_stack_locals[(int) mode][n]; | |
5725 | } | |
5726 | \f | |
5727 | /* Calculate the length of the memory address in the instruction | |
5728 | encoding. Does not include the one-byte modrm, opcode, or prefix. */ | |
5729 | ||
5730 | static int | |
5731 | memory_address_length (addr) | |
5732 | rtx addr; | |
5733 | { | |
5734 | struct ix86_address parts; | |
5735 | rtx base, index, disp; | |
5736 | int len; | |
5737 | ||
5738 | if (GET_CODE (addr) == PRE_DEC | |
5739 | || GET_CODE (addr) == POST_INC) | |
5740 | return 0; | |
3f803cd9 | 5741 | |
e075ae69 RH |
5742 | if (! ix86_decompose_address (addr, &parts)) |
5743 | abort (); | |
3f803cd9 | 5744 | |
e075ae69 RH |
5745 | base = parts.base; |
5746 | index = parts.index; | |
5747 | disp = parts.disp; | |
5748 | len = 0; | |
3f803cd9 | 5749 | |
e075ae69 RH |
5750 | /* Register Indirect. */ |
5751 | if (base && !index && !disp) | |
5752 | { | |
5753 | /* Special cases: ebp and esp need the two-byte modrm form. */ | |
5754 | if (addr == stack_pointer_rtx | |
5755 | || addr == arg_pointer_rtx | |
564d80f4 JH |
5756 | || addr == frame_pointer_rtx |
5757 | || addr == hard_frame_pointer_rtx) | |
e075ae69 | 5758 | len = 1; |
3f803cd9 | 5759 | } |
e9a25f70 | 5760 | |
e075ae69 RH |
5761 | /* Direct Addressing. */ |
5762 | else if (disp && !base && !index) | |
5763 | len = 4; | |
5764 | ||
3f803cd9 SC |
5765 | else |
5766 | { | |
e075ae69 RH |
5767 | /* Find the length of the displacement constant. */ |
5768 | if (disp) | |
5769 | { | |
5770 | if (GET_CODE (disp) == CONST_INT | |
5771 | && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K')) | |
5772 | len = 1; | |
5773 | else | |
5774 | len = 4; | |
5775 | } | |
3f803cd9 | 5776 | |
e075ae69 RH |
5777 | /* An index requires the two-byte modrm form. */ |
5778 | if (index) | |
5779 | len += 1; | |
3f803cd9 SC |
5780 | } |
5781 | ||
e075ae69 RH |
5782 | return len; |
5783 | } | |
79325812 | 5784 | |
e075ae69 RH |
5785 | int |
5786 | ix86_attr_length_default (insn) | |
5787 | rtx insn; | |
5788 | { | |
5789 | enum attr_type type; | |
5790 | int len = 0, i; | |
5791 | ||
5792 | type = get_attr_type (insn); | |
5793 | extract_insn (insn); | |
5794 | switch (type) | |
5795 | { | |
5796 | case TYPE_INCDEC: | |
5797 | case TYPE_SETCC: | |
5798 | case TYPE_ICMOV: | |
5799 | case TYPE_FMOV: | |
5800 | case TYPE_FOP: | |
5801 | case TYPE_FCMP: | |
5802 | case TYPE_FOP1: | |
5803 | case TYPE_FMUL: | |
5804 | case TYPE_FDIV: | |
5805 | case TYPE_FSGN: | |
5806 | case TYPE_FPSPC: | |
5807 | case TYPE_FCMOV: | |
5808 | case TYPE_IBR: | |
5809 | break; | |
7c7ef435 JH |
5810 | case TYPE_STR: |
5811 | case TYPE_CLD: | |
5812 | len = 0; | |
3f803cd9 | 5813 | |
e075ae69 RH |
5814 | case TYPE_ALU1: |
5815 | case TYPE_NEGNOT: | |
5816 | case TYPE_ALU: | |
5817 | case TYPE_ICMP: | |
5818 | case TYPE_IMOVX: | |
5819 | case TYPE_ISHIFT: | |
5820 | case TYPE_IMUL: | |
5821 | case TYPE_IDIV: | |
5822 | case TYPE_PUSH: | |
5823 | case TYPE_POP: | |
1ccbefce RH |
5824 | for (i = recog_data.n_operands - 1; i >= 0; --i) |
5825 | if (CONSTANT_P (recog_data.operand[i])) | |
e075ae69 | 5826 | { |
1ccbefce RH |
5827 | if (GET_CODE (recog_data.operand[i]) == CONST_INT |
5828 | && CONST_OK_FOR_LETTER_P (INTVAL (recog_data.operand[i]), 'K')) | |
e075ae69 RH |
5829 | len += 1; |
5830 | else | |
1ccbefce | 5831 | len += GET_MODE_SIZE (GET_MODE (recog_data.operand[0])); |
e075ae69 RH |
5832 | } |
5833 | break; | |
5834 | ||
5835 | case TYPE_IMOV: | |
1ccbefce RH |
5836 | if (CONSTANT_P (recog_data.operand[1])) |
5837 | len += GET_MODE_SIZE (GET_MODE (recog_data.operand[0])); | |
e075ae69 RH |
5838 | break; |
5839 | ||
5840 | case TYPE_CALL: | |
6baf1cc8 BS |
5841 | if (constant_call_address_operand (recog_data.operand[0], |
5842 | GET_MODE (recog_data.operand[0]))) | |
e075ae69 RH |
5843 | return 5; |
5844 | break; | |
3f803cd9 | 5845 | |
e075ae69 | 5846 | case TYPE_CALLV: |
6baf1cc8 BS |
5847 | if (constant_call_address_operand (recog_data.operand[1], |
5848 | GET_MODE (recog_data.operand[1]))) | |
e075ae69 RH |
5849 | return 5; |
5850 | break; | |
3f803cd9 | 5851 | |
e075ae69 | 5852 | case TYPE_LEA: |
3071fab5 RH |
5853 | { |
5854 | /* Irritatingly, single_set doesn't work with REG_UNUSED present, | |
5855 | as we'll get from running life_analysis during reg-stack when | |
1c71e60e JH |
5856 | not optimizing. Not that it matters anyway, now that |
5857 | pro_epilogue_adjust_stack uses lea, and is by design not | |
5858 | single_set. */ | |
3071fab5 RH |
5859 | rtx set = PATTERN (insn); |
5860 | if (GET_CODE (set) == SET) | |
5861 | ; | |
5862 | else if (GET_CODE (set) == PARALLEL | |
1c71e60e | 5863 | && GET_CODE (XVECEXP (set, 0, 0)) == SET) |
3071fab5 RH |
5864 | set = XVECEXP (set, 0, 0); |
5865 | else | |
5866 | abort (); | |
5867 | ||
5868 | len += memory_address_length (SET_SRC (set)); | |
5869 | goto just_opcode; | |
5870 | } | |
3f803cd9 | 5871 | |
e075ae69 RH |
5872 | case TYPE_OTHER: |
5873 | case TYPE_MULTI: | |
5874 | return 15; | |
3f803cd9 | 5875 | |
5d3c4797 | 5876 | case TYPE_FXCH: |
1ccbefce RH |
5877 | if (STACK_TOP_P (recog_data.operand[0])) |
5878 | return 2 + (REGNO (recog_data.operand[1]) != FIRST_STACK_REG + 1); | |
5d3c4797 | 5879 | else |
1ccbefce | 5880 | return 2 + (REGNO (recog_data.operand[0]) != FIRST_STACK_REG + 1); |
5d3c4797 | 5881 | |
e075ae69 RH |
5882 | default: |
5883 | abort (); | |
5884 | } | |
5885 | ||
1ccbefce RH |
5886 | for (i = recog_data.n_operands - 1; i >= 0; --i) |
5887 | if (GET_CODE (recog_data.operand[i]) == MEM) | |
e075ae69 | 5888 | { |
1ccbefce | 5889 | len += memory_address_length (XEXP (recog_data.operand[i], 0)); |
e075ae69 RH |
5890 | break; |
5891 | } | |
5892 | ||
5893 | just_opcode: | |
5894 | len += get_attr_length_opcode (insn); | |
5895 | len += get_attr_length_prefix (insn); | |
5896 | ||
5897 | return len; | |
3f803cd9 | 5898 | } |
e075ae69 RH |
5899 | \f |
5900 | /* Return the maximum number of instructions a cpu can issue. */ | |
b657fc39 | 5901 | |
e075ae69 RH |
5902 | int |
5903 | ix86_issue_rate () | |
b657fc39 | 5904 | { |
e075ae69 | 5905 | switch (ix86_cpu) |
b657fc39 | 5906 | { |
e075ae69 RH |
5907 | case PROCESSOR_PENTIUM: |
5908 | case PROCESSOR_K6: | |
5909 | return 2; | |
79325812 | 5910 | |
e075ae69 RH |
5911 | case PROCESSOR_PENTIUMPRO: |
5912 | return 3; | |
b657fc39 | 5913 | |
b657fc39 | 5914 | default: |
e075ae69 | 5915 | return 1; |
b657fc39 | 5916 | } |
b657fc39 L |
5917 | } |
5918 | ||
e075ae69 RH |
5919 | /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set |
5920 | by DEP_INSN and nothing set by DEP_INSN. */ | |
b657fc39 | 5921 | |
e075ae69 RH |
5922 | static int |
5923 | ix86_flags_dependant (insn, dep_insn, insn_type) | |
5924 | rtx insn, dep_insn; | |
5925 | enum attr_type insn_type; | |
5926 | { | |
5927 | rtx set, set2; | |
b657fc39 | 5928 | |
e075ae69 RH |
5929 | /* Simplify the test for uninteresting insns. */ |
5930 | if (insn_type != TYPE_SETCC | |
5931 | && insn_type != TYPE_ICMOV | |
5932 | && insn_type != TYPE_FCMOV | |
5933 | && insn_type != TYPE_IBR) | |
5934 | return 0; | |
b657fc39 | 5935 | |
e075ae69 RH |
5936 | if ((set = single_set (dep_insn)) != 0) |
5937 | { | |
5938 | set = SET_DEST (set); | |
5939 | set2 = NULL_RTX; | |
5940 | } | |
5941 | else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL | |
5942 | && XVECLEN (PATTERN (dep_insn), 0) == 2 | |
5943 | && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET | |
5944 | && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET) | |
5945 | { | |
5946 | set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0)); | |
5947 | set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0)); | |
5948 | } | |
78a0d70c ZW |
5949 | else |
5950 | return 0; | |
b657fc39 | 5951 | |
78a0d70c ZW |
5952 | if (GET_CODE (set) != REG || REGNO (set) != FLAGS_REG) |
5953 | return 0; | |
b657fc39 | 5954 | |
78a0d70c ZW |
5955 | /* This test is true if the dependant insn reads the flags but |
5956 | not any other potentially set register. */ | |
5957 | if (!reg_overlap_mentioned_p (set, PATTERN (insn))) | |
5958 | return 0; | |
5959 | ||
5960 | if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn))) | |
5961 | return 0; | |
5962 | ||
5963 | return 1; | |
e075ae69 | 5964 | } |
b657fc39 | 5965 | |
e075ae69 RH |
5966 | /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory |
5967 | address with operands set by DEP_INSN. */ | |
5968 | ||
5969 | static int | |
5970 | ix86_agi_dependant (insn, dep_insn, insn_type) | |
5971 | rtx insn, dep_insn; | |
5972 | enum attr_type insn_type; | |
5973 | { | |
5974 | rtx addr; | |
5975 | ||
5976 | if (insn_type == TYPE_LEA) | |
5fbdde42 RH |
5977 | { |
5978 | addr = PATTERN (insn); | |
5979 | if (GET_CODE (addr) == SET) | |
5980 | ; | |
5981 | else if (GET_CODE (addr) == PARALLEL | |
5982 | && GET_CODE (XVECEXP (addr, 0, 0)) == SET) | |
5983 | addr = XVECEXP (addr, 0, 0); | |
5984 | else | |
5985 | abort (); | |
5986 | addr = SET_SRC (addr); | |
5987 | } | |
e075ae69 RH |
5988 | else |
5989 | { | |
5990 | int i; | |
5991 | extract_insn (insn); | |
1ccbefce RH |
5992 | for (i = recog_data.n_operands - 1; i >= 0; --i) |
5993 | if (GET_CODE (recog_data.operand[i]) == MEM) | |
e075ae69 | 5994 | { |
1ccbefce | 5995 | addr = XEXP (recog_data.operand[i], 0); |
e075ae69 RH |
5996 | goto found; |
5997 | } | |
5998 | return 0; | |
5999 | found:; | |
b657fc39 L |
6000 | } |
6001 | ||
e075ae69 | 6002 | return modified_in_p (addr, dep_insn); |
b657fc39 | 6003 | } |
a269a03c JC |
6004 | |
6005 | int | |
e075ae69 | 6006 | ix86_adjust_cost (insn, link, dep_insn, cost) |
a269a03c JC |
6007 | rtx insn, link, dep_insn; |
6008 | int cost; | |
6009 | { | |
e075ae69 RH |
6010 | enum attr_type insn_type, dep_insn_type; |
6011 | rtx set, set2; | |
9b00189f | 6012 | int dep_insn_code_number; |
a269a03c | 6013 | |
309ada50 | 6014 | /* Anti and output depenancies have zero cost on all CPUs. */ |
e075ae69 | 6015 | if (REG_NOTE_KIND (link) != 0) |
309ada50 | 6016 | return 0; |
a269a03c | 6017 | |
9b00189f JH |
6018 | dep_insn_code_number = recog_memoized (dep_insn); |
6019 | ||
e075ae69 | 6020 | /* If we can't recognize the insns, we can't really do anything. */ |
9b00189f | 6021 | if (dep_insn_code_number < 0 || recog_memoized (insn) < 0) |
e075ae69 | 6022 | return cost; |
a269a03c | 6023 | |
1c71e60e JH |
6024 | insn_type = get_attr_type (insn); |
6025 | dep_insn_type = get_attr_type (dep_insn); | |
9b00189f | 6026 | |
1c71e60e JH |
6027 | /* Prologue and epilogue allocators can have a false dependency on ebp. |
6028 | This results in one cycle extra stall on Pentium prologue scheduling, | |
6029 | so handle this important case manually. */ | |
6030 | if (dep_insn_code_number == CODE_FOR_pro_epilogue_adjust_stack | |
6031 | && dep_insn_type == TYPE_ALU | |
9b00189f JH |
6032 | && !reg_mentioned_p (stack_pointer_rtx, insn)) |
6033 | return 0; | |
6034 | ||
a269a03c JC |
6035 | switch (ix86_cpu) |
6036 | { | |
6037 | case PROCESSOR_PENTIUM: | |
e075ae69 RH |
6038 | /* Address Generation Interlock adds a cycle of latency. */ |
6039 | if (ix86_agi_dependant (insn, dep_insn, insn_type)) | |
6040 | cost += 1; | |
6041 | ||
6042 | /* ??? Compares pair with jump/setcc. */ | |
6043 | if (ix86_flags_dependant (insn, dep_insn, insn_type)) | |
6044 | cost = 0; | |
6045 | ||
6046 | /* Floating point stores require value to be ready one cycle ealier. */ | |
6047 | if (insn_type == TYPE_FMOV | |
6048 | && get_attr_memory (insn) == MEMORY_STORE | |
6049 | && !ix86_agi_dependant (insn, dep_insn, insn_type)) | |
6050 | cost += 1; | |
6051 | break; | |
a269a03c | 6052 | |
e075ae69 RH |
6053 | case PROCESSOR_PENTIUMPRO: |
6054 | /* Since we can't represent delayed latencies of load+operation, | |
6055 | increase the cost here for non-imov insns. */ | |
6056 | if (dep_insn_type != TYPE_IMOV | |
6057 | && dep_insn_type != TYPE_FMOV | |
6058 | && get_attr_memory (dep_insn) == MEMORY_LOAD) | |
6059 | cost += 1; | |
6060 | ||
6061 | /* INT->FP conversion is expensive. */ | |
6062 | if (get_attr_fp_int_src (dep_insn)) | |
6063 | cost += 5; | |
6064 | ||
6065 | /* There is one cycle extra latency between an FP op and a store. */ | |
6066 | if (insn_type == TYPE_FMOV | |
6067 | && (set = single_set (dep_insn)) != NULL_RTX | |
6068 | && (set2 = single_set (insn)) != NULL_RTX | |
6069 | && rtx_equal_p (SET_DEST (set), SET_SRC (set2)) | |
6070 | && GET_CODE (SET_DEST (set2)) == MEM) | |
6071 | cost += 1; | |
6072 | break; | |
a269a03c | 6073 | |
e075ae69 RH |
6074 | case PROCESSOR_K6: |
6075 | /* The esp dependency is resolved before the instruction is really | |
6076 | finished. */ | |
6077 | if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP) | |
6078 | && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP)) | |
6079 | return 1; | |
a269a03c | 6080 | |
e075ae69 RH |
6081 | /* Since we can't represent delayed latencies of load+operation, |
6082 | increase the cost here for non-imov insns. */ | |
6083 | if (get_attr_memory (dep_insn) == MEMORY_LOAD) | |
6084 | cost += (dep_insn_type != TYPE_IMOV) ? 2 : 1; | |
6085 | ||
6086 | /* INT->FP conversion is expensive. */ | |
6087 | if (get_attr_fp_int_src (dep_insn)) | |
6088 | cost += 5; | |
a14003ee | 6089 | break; |
e075ae69 | 6090 | |
309ada50 JH |
6091 | case PROCESSOR_ATHLON: |
6092 | /* Address Generation Interlock cause problems on the Athlon CPU because | |
6093 | the loads and stores are done in order so once one load or store has | |
6094 | to wait, others must too, so penalize the AGIs slightly by one cycle. | |
6095 | We might experiment with this value later. */ | |
6096 | if (ix86_agi_dependant (insn, dep_insn, insn_type)) | |
6097 | cost += 1; | |
6098 | ||
6099 | /* Since we can't represent delayed latencies of load+operation, | |
6100 | increase the cost here for non-imov insns. */ | |
6101 | if (dep_insn_type != TYPE_IMOV | |
6102 | && dep_insn_type != TYPE_FMOV | |
6103 | && get_attr_memory (dep_insn) == MEMORY_LOAD) | |
6104 | cost += 2; | |
a269a03c | 6105 | default: |
a269a03c JC |
6106 | break; |
6107 | } | |
6108 | ||
6109 | return cost; | |
6110 | } | |
0a726ef1 | 6111 | |
e075ae69 RH |
6112 | static union |
6113 | { | |
6114 | struct ppro_sched_data | |
6115 | { | |
6116 | rtx decode[3]; | |
6117 | int issued_this_cycle; | |
6118 | } ppro; | |
6119 | } ix86_sched_data; | |
0a726ef1 | 6120 | |
e075ae69 RH |
6121 | static int |
6122 | ix86_safe_length (insn) | |
6123 | rtx insn; | |
6124 | { | |
6125 | if (recog_memoized (insn) >= 0) | |
6126 | return get_attr_length(insn); | |
6127 | else | |
6128 | return 128; | |
6129 | } | |
0a726ef1 | 6130 | |
e075ae69 RH |
6131 | static int |
6132 | ix86_safe_length_prefix (insn) | |
6133 | rtx insn; | |
6134 | { | |
6135 | if (recog_memoized (insn) >= 0) | |
6136 | return get_attr_length(insn); | |
6137 | else | |
6138 | return 0; | |
6139 | } | |
6140 | ||
6141 | static enum attr_memory | |
6142 | ix86_safe_memory (insn) | |
6143 | rtx insn; | |
6144 | { | |
6145 | if (recog_memoized (insn) >= 0) | |
6146 | return get_attr_memory(insn); | |
6147 | else | |
6148 | return MEMORY_UNKNOWN; | |
6149 | } | |
0a726ef1 | 6150 | |
e075ae69 RH |
6151 | static enum attr_pent_pair |
6152 | ix86_safe_pent_pair (insn) | |
6153 | rtx insn; | |
6154 | { | |
6155 | if (recog_memoized (insn) >= 0) | |
6156 | return get_attr_pent_pair(insn); | |
6157 | else | |
6158 | return PENT_PAIR_NP; | |
6159 | } | |
0a726ef1 | 6160 | |
e075ae69 RH |
6161 | static enum attr_ppro_uops |
6162 | ix86_safe_ppro_uops (insn) | |
6163 | rtx insn; | |
6164 | { | |
6165 | if (recog_memoized (insn) >= 0) | |
6166 | return get_attr_ppro_uops (insn); | |
6167 | else | |
6168 | return PPRO_UOPS_MANY; | |
6169 | } | |
0a726ef1 | 6170 | |
e075ae69 RH |
6171 | static void |
6172 | ix86_dump_ppro_packet (dump) | |
6173 | FILE *dump; | |
0a726ef1 | 6174 | { |
e075ae69 | 6175 | if (ix86_sched_data.ppro.decode[0]) |
0a726ef1 | 6176 | { |
e075ae69 RH |
6177 | fprintf (dump, "PPRO packet: %d", |
6178 | INSN_UID (ix86_sched_data.ppro.decode[0])); | |
6179 | if (ix86_sched_data.ppro.decode[1]) | |
6180 | fprintf (dump, " %d", INSN_UID (ix86_sched_data.ppro.decode[1])); | |
6181 | if (ix86_sched_data.ppro.decode[2]) | |
6182 | fprintf (dump, " %d", INSN_UID (ix86_sched_data.ppro.decode[2])); | |
6183 | fputc ('\n', dump); | |
6184 | } | |
6185 | } | |
0a726ef1 | 6186 | |
e075ae69 | 6187 | /* We're beginning a new block. Initialize data structures as necessary. */ |
0a726ef1 | 6188 | |
e075ae69 RH |
6189 | void |
6190 | ix86_sched_init (dump, sched_verbose) | |
6191 | FILE *dump ATTRIBUTE_UNUSED; | |
6192 | int sched_verbose ATTRIBUTE_UNUSED; | |
6193 | { | |
6194 | memset (&ix86_sched_data, 0, sizeof (ix86_sched_data)); | |
6195 | } | |
6196 | ||
6197 | /* Shift INSN to SLOT, and shift everything else down. */ | |
6198 | ||
6199 | static void | |
6200 | ix86_reorder_insn (insnp, slot) | |
6201 | rtx *insnp, *slot; | |
6202 | { | |
6203 | if (insnp != slot) | |
6204 | { | |
6205 | rtx insn = *insnp; | |
6206 | do | |
6207 | insnp[0] = insnp[1]; | |
6208 | while (++insnp != slot); | |
6209 | *insnp = insn; | |
0a726ef1 | 6210 | } |
e075ae69 RH |
6211 | } |
6212 | ||
6213 | /* Find an instruction with given pairability and minimal amount of cycles | |
6214 | lost by the fact that the CPU waits for both pipelines to finish before | |
6215 | reading next instructions. Also take care that both instructions together | |
6216 | can not exceed 7 bytes. */ | |
6217 | ||
6218 | static rtx * | |
6219 | ix86_pent_find_pair (e_ready, ready, type, first) | |
6220 | rtx *e_ready; | |
6221 | rtx *ready; | |
6222 | enum attr_pent_pair type; | |
6223 | rtx first; | |
6224 | { | |
6225 | int mincycles, cycles; | |
6226 | enum attr_pent_pair tmp; | |
6227 | enum attr_memory memory; | |
6228 | rtx *insnp, *bestinsnp = NULL; | |
0a726ef1 | 6229 | |
e075ae69 RH |
6230 | if (ix86_safe_length (first) > 7 + ix86_safe_length_prefix (first)) |
6231 | return NULL; | |
0a726ef1 | 6232 | |
e075ae69 RH |
6233 | memory = ix86_safe_memory (first); |
6234 | cycles = result_ready_cost (first); | |
6235 | mincycles = INT_MAX; | |
6236 | ||
6237 | for (insnp = e_ready; insnp >= ready && mincycles; --insnp) | |
6238 | if ((tmp = ix86_safe_pent_pair (*insnp)) == type | |
6239 | && ix86_safe_length (*insnp) <= 7 + ix86_safe_length_prefix (*insnp)) | |
6ec6d558 | 6240 | { |
e075ae69 RH |
6241 | enum attr_memory second_memory; |
6242 | int secondcycles, currentcycles; | |
6243 | ||
6244 | second_memory = ix86_safe_memory (*insnp); | |
6245 | secondcycles = result_ready_cost (*insnp); | |
6246 | currentcycles = abs (cycles - secondcycles); | |
6247 | ||
6248 | if (secondcycles >= 1 && cycles >= 1) | |
6ec6d558 | 6249 | { |
e075ae69 RH |
6250 | /* Two read/modify/write instructions together takes two |
6251 | cycles longer. */ | |
6252 | if (memory == MEMORY_BOTH && second_memory == MEMORY_BOTH) | |
6253 | currentcycles += 2; | |
6254 | ||
6255 | /* Read modify/write instruction followed by read/modify | |
6256 | takes one cycle longer. */ | |
6257 | if (memory == MEMORY_BOTH && second_memory == MEMORY_LOAD | |
6258 | && tmp != PENT_PAIR_UV | |
6259 | && ix86_safe_pent_pair (first) != PENT_PAIR_UV) | |
6260 | currentcycles += 1; | |
6ec6d558 | 6261 | } |
e075ae69 RH |
6262 | if (currentcycles < mincycles) |
6263 | bestinsnp = insnp, mincycles = currentcycles; | |
6ec6d558 | 6264 | } |
0a726ef1 | 6265 | |
e075ae69 RH |
6266 | return bestinsnp; |
6267 | } | |
6268 | ||
78a0d70c | 6269 | /* Subroutines of ix86_sched_reorder. */ |
e075ae69 | 6270 | |
c6991660 | 6271 | static void |
78a0d70c | 6272 | ix86_sched_reorder_pentium (ready, e_ready) |
e075ae69 | 6273 | rtx *ready; |
78a0d70c | 6274 | rtx *e_ready; |
e075ae69 | 6275 | { |
78a0d70c | 6276 | enum attr_pent_pair pair1, pair2; |
e075ae69 | 6277 | rtx *insnp; |
e075ae69 | 6278 | |
78a0d70c ZW |
6279 | /* This wouldn't be necessary if Haifa knew that static insn ordering |
6280 | is important to which pipe an insn is issued to. So we have to make | |
6281 | some minor rearrangements. */ | |
e075ae69 | 6282 | |
78a0d70c ZW |
6283 | pair1 = ix86_safe_pent_pair (*e_ready); |
6284 | ||
6285 | /* If the first insn is non-pairable, let it be. */ | |
6286 | if (pair1 == PENT_PAIR_NP) | |
6287 | return; | |
6288 | ||
6289 | pair2 = PENT_PAIR_NP; | |
6290 | insnp = 0; | |
6291 | ||
6292 | /* If the first insn is UV or PV pairable, search for a PU | |
6293 | insn to go with. */ | |
6294 | if (pair1 == PENT_PAIR_UV || pair1 == PENT_PAIR_PV) | |
e075ae69 | 6295 | { |
78a0d70c ZW |
6296 | insnp = ix86_pent_find_pair (e_ready-1, ready, |
6297 | PENT_PAIR_PU, *e_ready); | |
6298 | if (insnp) | |
6299 | pair2 = PENT_PAIR_PU; | |
6300 | } | |
e075ae69 | 6301 | |
78a0d70c ZW |
6302 | /* If the first insn is PU or UV pairable, search for a PV |
6303 | insn to go with. */ | |
6304 | if (pair2 == PENT_PAIR_NP | |
6305 | && (pair1 == PENT_PAIR_PU || pair1 == PENT_PAIR_UV)) | |
6306 | { | |
6307 | insnp = ix86_pent_find_pair (e_ready-1, ready, | |
6308 | PENT_PAIR_PV, *e_ready); | |
6309 | if (insnp) | |
6310 | pair2 = PENT_PAIR_PV; | |
6311 | } | |
e075ae69 | 6312 | |
78a0d70c ZW |
6313 | /* If the first insn is pairable, search for a UV |
6314 | insn to go with. */ | |
6315 | if (pair2 == PENT_PAIR_NP) | |
6316 | { | |
6317 | insnp = ix86_pent_find_pair (e_ready-1, ready, | |
6318 | PENT_PAIR_UV, *e_ready); | |
6319 | if (insnp) | |
6320 | pair2 = PENT_PAIR_UV; | |
6321 | } | |
e075ae69 | 6322 | |
78a0d70c ZW |
6323 | if (pair2 == PENT_PAIR_NP) |
6324 | return; | |
e075ae69 | 6325 | |
78a0d70c ZW |
6326 | /* Found something! Decide if we need to swap the order. */ |
6327 | if (pair1 == PENT_PAIR_PV || pair2 == PENT_PAIR_PU | |
6328 | || (pair1 == PENT_PAIR_UV && pair2 == PENT_PAIR_UV | |
6329 | && ix86_safe_memory (*e_ready) == MEMORY_BOTH | |
6330 | && ix86_safe_memory (*insnp) == MEMORY_LOAD)) | |
6331 | ix86_reorder_insn (insnp, e_ready); | |
6332 | else | |
6333 | ix86_reorder_insn (insnp, e_ready - 1); | |
6334 | } | |
e075ae69 | 6335 | |
c6991660 | 6336 | static void |
78a0d70c ZW |
6337 | ix86_sched_reorder_ppro (ready, e_ready) |
6338 | rtx *ready; | |
6339 | rtx *e_ready; | |
6340 | { | |
6341 | rtx decode[3]; | |
6342 | enum attr_ppro_uops cur_uops; | |
6343 | int issued_this_cycle; | |
6344 | rtx *insnp; | |
6345 | int i; | |
e075ae69 | 6346 | |
78a0d70c ZW |
6347 | /* At this point .ppro.decode contains the state of the three |
6348 | decoders from last "cycle". That is, those insns that were | |
6349 | actually independent. But here we're scheduling for the | |
6350 | decoder, and we may find things that are decodable in the | |
6351 | same cycle. */ | |
e075ae69 | 6352 | |
78a0d70c ZW |
6353 | memcpy (decode, ix86_sched_data.ppro.decode, sizeof(decode)); |
6354 | issued_this_cycle = 0; | |
e075ae69 | 6355 | |
78a0d70c ZW |
6356 | insnp = e_ready; |
6357 | cur_uops = ix86_safe_ppro_uops (*insnp); | |
0a726ef1 | 6358 | |
78a0d70c ZW |
6359 | /* If the decoders are empty, and we've a complex insn at the |
6360 | head of the priority queue, let it issue without complaint. */ | |
6361 | if (decode[0] == NULL) | |
6362 | { | |
6363 | if (cur_uops == PPRO_UOPS_MANY) | |
6364 | { | |
6365 | decode[0] = *insnp; | |
6366 | goto ppro_done; | |
6367 | } | |
6368 | ||
6369 | /* Otherwise, search for a 2-4 uop unsn to issue. */ | |
6370 | while (cur_uops != PPRO_UOPS_FEW) | |
6371 | { | |
6372 | if (insnp == ready) | |
6373 | break; | |
6374 | cur_uops = ix86_safe_ppro_uops (*--insnp); | |
6375 | } | |
6376 | ||
6377 | /* If so, move it to the head of the line. */ | |
6378 | if (cur_uops == PPRO_UOPS_FEW) | |
6379 | ix86_reorder_insn (insnp, e_ready); | |
0a726ef1 | 6380 | |
78a0d70c ZW |
6381 | /* Issue the head of the queue. */ |
6382 | issued_this_cycle = 1; | |
6383 | decode[0] = *e_ready--; | |
6384 | } | |
fb693d44 | 6385 | |
78a0d70c ZW |
6386 | /* Look for simple insns to fill in the other two slots. */ |
6387 | for (i = 1; i < 3; ++i) | |
6388 | if (decode[i] == NULL) | |
6389 | { | |
6390 | if (ready >= e_ready) | |
6391 | goto ppro_done; | |
fb693d44 | 6392 | |
e075ae69 RH |
6393 | insnp = e_ready; |
6394 | cur_uops = ix86_safe_ppro_uops (*insnp); | |
78a0d70c ZW |
6395 | while (cur_uops != PPRO_UOPS_ONE) |
6396 | { | |
6397 | if (insnp == ready) | |
6398 | break; | |
6399 | cur_uops = ix86_safe_ppro_uops (*--insnp); | |
6400 | } | |
fb693d44 | 6401 | |
78a0d70c ZW |
6402 | /* Found one. Move it to the head of the queue and issue it. */ |
6403 | if (cur_uops == PPRO_UOPS_ONE) | |
e075ae69 | 6404 | { |
78a0d70c ZW |
6405 | ix86_reorder_insn (insnp, e_ready); |
6406 | decode[i] = *e_ready--; | |
6407 | issued_this_cycle++; | |
6408 | continue; | |
6409 | } | |
fb693d44 | 6410 | |
78a0d70c ZW |
6411 | /* ??? Didn't find one. Ideally, here we would do a lazy split |
6412 | of 2-uop insns, issue one and queue the other. */ | |
6413 | } | |
fb693d44 | 6414 | |
78a0d70c ZW |
6415 | ppro_done: |
6416 | if (issued_this_cycle == 0) | |
6417 | issued_this_cycle = 1; | |
6418 | ix86_sched_data.ppro.issued_this_cycle = issued_this_cycle; | |
6419 | } | |
fb693d44 | 6420 | |
78a0d70c ZW |
6421 | |
6422 | /* We are about to being issuing insns for this clock cycle. | |
6423 | Override the default sort algorithm to better slot instructions. */ | |
6424 | int | |
6425 | ix86_sched_reorder (dump, sched_verbose, ready, n_ready, clock_var) | |
6426 | FILE *dump ATTRIBUTE_UNUSED; | |
6427 | int sched_verbose ATTRIBUTE_UNUSED; | |
6428 | rtx *ready; | |
6429 | int n_ready; | |
6430 | int clock_var ATTRIBUTE_UNUSED; | |
6431 | { | |
6432 | rtx *e_ready = ready + n_ready - 1; | |
fb693d44 | 6433 | |
78a0d70c ZW |
6434 | if (n_ready < 2) |
6435 | goto out; | |
e075ae69 | 6436 | |
78a0d70c ZW |
6437 | switch (ix86_cpu) |
6438 | { | |
6439 | default: | |
6440 | break; | |
e075ae69 | 6441 | |
78a0d70c ZW |
6442 | case PROCESSOR_PENTIUM: |
6443 | ix86_sched_reorder_pentium (ready, e_ready); | |
6444 | break; | |
e075ae69 | 6445 | |
78a0d70c ZW |
6446 | case PROCESSOR_PENTIUMPRO: |
6447 | ix86_sched_reorder_ppro (ready, e_ready); | |
e075ae69 | 6448 | break; |
fb693d44 RH |
6449 | } |
6450 | ||
e075ae69 RH |
6451 | out: |
6452 | return ix86_issue_rate (); | |
6453 | } | |
fb693d44 | 6454 | |
e075ae69 RH |
6455 | /* We are about to issue INSN. Return the number of insns left on the |
6456 | ready queue that can be issued this cycle. */ | |
b222082e | 6457 | |
e075ae69 RH |
6458 | int |
6459 | ix86_variable_issue (dump, sched_verbose, insn, can_issue_more) | |
6460 | FILE *dump; | |
6461 | int sched_verbose; | |
6462 | rtx insn; | |
6463 | int can_issue_more; | |
6464 | { | |
6465 | int i; | |
6466 | switch (ix86_cpu) | |
fb693d44 | 6467 | { |
e075ae69 RH |
6468 | default: |
6469 | return can_issue_more - 1; | |
fb693d44 | 6470 | |
e075ae69 RH |
6471 | case PROCESSOR_PENTIUMPRO: |
6472 | { | |
6473 | enum attr_ppro_uops uops = ix86_safe_ppro_uops (insn); | |
fb693d44 | 6474 | |
e075ae69 RH |
6475 | if (uops == PPRO_UOPS_MANY) |
6476 | { | |
6477 | if (sched_verbose) | |
6478 | ix86_dump_ppro_packet (dump); | |
6479 | ix86_sched_data.ppro.decode[0] = insn; | |
6480 | ix86_sched_data.ppro.decode[1] = NULL; | |
6481 | ix86_sched_data.ppro.decode[2] = NULL; | |
6482 | if (sched_verbose) | |
6483 | ix86_dump_ppro_packet (dump); | |
6484 | ix86_sched_data.ppro.decode[0] = NULL; | |
6485 | } | |
6486 | else if (uops == PPRO_UOPS_FEW) | |
6487 | { | |
6488 | if (sched_verbose) | |
6489 | ix86_dump_ppro_packet (dump); | |
6490 | ix86_sched_data.ppro.decode[0] = insn; | |
6491 | ix86_sched_data.ppro.decode[1] = NULL; | |
6492 | ix86_sched_data.ppro.decode[2] = NULL; | |
6493 | } | |
6494 | else | |
6495 | { | |
6496 | for (i = 0; i < 3; ++i) | |
6497 | if (ix86_sched_data.ppro.decode[i] == NULL) | |
6498 | { | |
6499 | ix86_sched_data.ppro.decode[i] = insn; | |
6500 | break; | |
6501 | } | |
6502 | if (i == 3) | |
6503 | abort (); | |
6504 | if (i == 2) | |
6505 | { | |
6506 | if (sched_verbose) | |
6507 | ix86_dump_ppro_packet (dump); | |
6508 | ix86_sched_data.ppro.decode[0] = NULL; | |
6509 | ix86_sched_data.ppro.decode[1] = NULL; | |
6510 | ix86_sched_data.ppro.decode[2] = NULL; | |
6511 | } | |
6512 | } | |
6513 | } | |
6514 | return --ix86_sched_data.ppro.issued_this_cycle; | |
6515 | } | |
fb693d44 | 6516 | } |