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* config/h8300/h8300.md (extendqisi2): Remove constraints.
[gcc.git] / gcc / config / h8300 / h8300.md
CommitLineData
b4d2cd97 1;; GCC machine description for Hitachi H8/300
63a262f1 2;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
8ccf5d5f 3;; 2001, 2002, 2003 Free Software Foundation, Inc.
b4d2cd97
DE		 4
5;; Contributed by Steve Chamberlain (sac@cygnus.com),
6;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
f82eca4d 7
8aa063fb 8;; This file is part of GCC.
f82eca4d 9
8aa063fb 10;; GCC is free software; you can redistribute it and/or modify
f82eca4d
SC		 11;; it under the terms of the GNU General Public License as published by
12;; the Free Software Foundation; either version 2, or (at your option)
13;; any later version.
14
8aa063fb 15;; GCC is distributed in the hope that it will be useful,
f82eca4d
SC		 16;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18;; GNU General Public License for more details.
19
20;; You should have received a copy of the GNU General Public License
8aa063fb 21;; along with GCC; see the file COPYING. If not, write to
a8f1399a 22;; the Free Software Foundation, 59 Temple Place - Suite 330,
6d85f32b 23;; Boston, MA 02111-1307, USA.
f82eca4d 24
caf7f21a
KH		 25;; We compute exact length on each instruction for most of the time.
26;; In some case, most notably bit operations that may involve memory
27;; operands, the lengths in this file are "worst case".
ec497122 28
3db11b5c 29;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
d10dd44c
KH		 30;; registers. Right now GCC doesn't expose the "e" half to the
31;; compiler, so using add/subs for addhi and subhi is safe. Long
32;; term, we want to expose the "e" half to the compiler (gives us 8
33;; more 16bit registers). At that point addhi and subhi can't use
34;; adds/subs.
953b10d0 35
43aa4e05 36;; There's currently no way to have an insv/extzv expander for the H8/300H
1898584f 37;; because word_mode is different for the H8/300 and H8/300H.
bd93f126 38
dd4fd0a0
JL		 39;; Shifts/rotates by small constants should be handled by special
40;; patterns so we get the length and cc status correct.
41
42;; Bitfield operations no longer accept memory operands. We need
43;; to add variants which operate on memory back to the MD.
44
bd93f126 45;; ??? Implement remaining bit ops available on the h8300
2accfbc7 46
d8fd4914
KH		 47;; ----------------------------------------------------------------------
48;; CONSTANTS
49;; ----------------------------------------------------------------------
50
f9d2de4d 51(define_constants
68ee6df6
KH		 52 [(UNSPEC_INCDEC 0)
53 (UNSPEC_MONITOR 1)])
f9d2de4d 54
d8fd4914 55(define_constants
1c11abc4
KH		 56 [(SC_REG 3)
57 (FP_REG 6)
58 (SP_REG 7)
59 (MAC_REG 8)
60 (AP_REG 9)
61 (RAP_REG 10)])
d8fd4914 62
ed863595
KH		 63;; ----------------------------------------------------------------------
64;; ATTRIBUTES
65;; ----------------------------------------------------------------------
66
67(define_attr "cpu" "h8300,h8300h"
68 (const (symbol_ref "cpu_type")))
69
e1aa1a6c 70(define_attr "type" "branch,arith"
f82eca4d
SC		 71 (const_string "arith"))
72
73;; The size of instructions in bytes.
74
c127c127 75(define_attr "length" ""
f82eca4d 76 (cond [(eq_attr "type" "branch")
16c96304
KH		 77 (if_then_else (and (ge (minus (match_dup 0) (pc))
78 (const_int -126))
79 (le (minus (match_dup 0) (pc))
80 (const_int 126)))
f82eca4d 81 (const_int 2)
b4d2cd97
DE		 82 (if_then_else (and (eq_attr "cpu" "h8300h")
83 (and (ge (minus (pc) (match_dup 0))
84 (const_int -32000))
85 (le (minus (pc) (match_dup 0))
86 (const_int 32000))))
87 (const_int 4)
e1aa1a6c 88 (const_int 6)))]
f82eca4d
SC		 89 (const_int 200)))
90
269c14e1 91;; Condition code settings.
ed863595 92;;
269c14e1
DE		 93;; none - insn does not affect cc
94;; none_0hit - insn does not affect cc but it does modify operand 0
95;; This attribute is used to keep track of when operand 0 changes.
8bd06267 96;; See the description of NOTICE_UPDATE_CC for more info.
065bbfe6
JL		 97;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
98;; set_zn - insn sets z,n to usable values; v,c are unknown.
269c14e1
DE		 99;; compare - compare instruction
100;; clobber - value of cc is unknown
ed863595 101
065bbfe6 102(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
269c14e1 103 (const_string "clobber"))
cf48cabb
KH		 104
105;; Provide the maximum length of an assembly instruction in an asm
106;; statement. The maximum length of 14 bytes is achieved on H8SX.
107
108(define_asm_attributes
5e46c560
KH		 109 [(set (attr "length")
110 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
111 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
112 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
113 (const_int 14)))])
269c14e1 114\f
f82eca4d 115;; ----------------------------------------------------------------------
b4d2cd97 116;; MOVE INSTRUCTIONS
f82eca4d
SC		 117;; ----------------------------------------------------------------------
118
b4d2cd97 119;; movqi
f82eca4d 120
5660465a 121(define_insn "pushqi1_h8300"
d8fd4914 122 [(parallel [(set (reg:HI SP_REG)
4d5ad877
KH		 123 (plus:HI (reg:HI SP_REG) (const_int -2)))
124 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
125 (match_operand:QI 0 "register_operand" "r"))])]
191ff852 126 "TARGET_H8300
a62a282b 127 && operands[0] != stack_pointer_rtx"
a1bf0a16 128 "mov.w\\t%T0,@-r7"
5660465a
KH		 129 [(set_attr "length" "2")
130 (set_attr "cc" "clobber")])
131
132(define_insn "pushqi1_h8300hs"
d8fd4914 133 [(parallel [(set (reg:SI SP_REG)
4d5ad877
KH		 134 (plus:SI (reg:SI SP_REG) (const_int -4)))
135 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
136 (match_operand:QI 0 "register_operand" "r"))])]
191ff852 137 "(TARGET_H8300H || TARGET_H8300S)
a62a282b 138 && operands[0] != stack_pointer_rtx"
b275810a 139 "mov.l\\t%S0,@-er7"
5660465a
KH		 140 [(set_attr "length" "4")
141 (set_attr "cc" "clobber")])
142
f24f0897
KH		 143(define_insn "pushqi1_h8300hs_normal"
144 [(parallel [(set (reg:HI SP_REG)
145 (plus:HI (reg:HI SP_REG) (const_int -4)))
146 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
147 (match_operand:QI 0 "register_operand" "r"))])]
148 "(TARGET_H8300H || TARGET_H8300S)
149 && operands[0] != stack_pointer_rtx"
150 "mov.l\\t%S0,@-er7"
151 [(set_attr "length" "4")
152 (set_attr "cc" "clobber")])
153
5660465a 154(define_expand "pushqi1"
08a02ffa 155 [(use (match_operand:QI 0 "register_operand" ""))]
5660465a
KH		 156 ""
157 "
158{
159 if (TARGET_H8300)
160 emit_insn (gen_pushqi1_h8300 (operands[0]));
f24f0897 161 else if (!TARGET_NORMAL_MODE)
5660465a 162 emit_insn (gen_pushqi1_h8300hs (operands[0]));
f24f0897
KH		 163 else
164 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
5660465a
KH		 165 DONE;
166}")
167
61f33c67 168(define_insn "*movqi_h8300"
5660465a 169 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
7fcd4787 170 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
ba412630 171 "TARGET_H8300
20c907b0 172 && (register_operand (operands[0], QImode)
ba412630
KH		 173 || register_operand (operands[1], QImode))"
174 "@
175 sub.b %X0,%X0
176 mov.b %R1,%X0
177 mov.b %X1,%R0
ba412630
KH		 178 mov.b %R1,%X0
179 mov.b %R1,%X0
180 mov.b %X1,%R0"
5660465a
KH		 181 [(set_attr "length" "2,2,2,2,4,4")
182 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
f82eca4d 183
61f33c67 184(define_insn "*movqi_h8300hs"
5660465a 185 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
7fcd4787 186 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
ba412630 187 "(TARGET_H8300H || TARGET_H8300S)
20c907b0 188 && (register_operand (operands[0], QImode)
ba412630 189 || register_operand (operands[1], QImode))"
b4d2cd97
DE		 190 "@
191 sub.b %X0,%X0
15dc331e
JL		 192 mov.b %R1,%X0
193 mov.b %X1,%R0
194 mov.b %R1,%X0
887a8bd9 195 mov.b %R1,%X0
15dc331e 196 mov.b %X1,%R0"
7948a9ea
KH		 197 [(set (attr "length")
198 (symbol_ref "compute_mov_length (operands)"))
5660465a 199 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
b4d2cd97
DE		 200
201(define_expand "movqi"
5660465a 202 [(set (match_operand:QI 0 "general_operand_dst" "")
b4d2cd97
DE		 203 (match_operand:QI 1 "general_operand_src" ""))]
204 ""
205 "
206{
1a63219b
KH		 207 /* One of the ops has to be in a register. */
208 if (!register_operand (operand0, QImode)
209 && !register_operand (operand1, QImode))
b4d2cd97 210 {
1a63219b 211 operands[1] = copy_to_mode_reg (QImode, operand1);
b4d2cd97
DE		 212 }
213}")
214
215(define_insn "movstrictqi"
4843bda9 216 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
bf63e3a2 217 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
f82eca4d
SC		 218 ""
219 "@
b4d2cd97
DE		 220 sub.b %X0,%X0
221 mov.b %X1,%X0
887a8bd9 222 mov.b %R1,%X0
15dc331e 223 mov.b %R1,%X0"
7948a9ea
KH		 224 [(set (attr "length")
225 (symbol_ref "compute_mov_length (operands)"))
065bbfe6 226 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
c127c127 227
b4d2cd97
DE		 228;; movhi
229
5660465a 230(define_expand "pushhi1_h8300"
232bd029 231 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
4d5ad877 232 (match_operand:HI 0 "register_operand" ""))]
191ff852 233 "TARGET_H8300
a62a282b 234 && operands[0] != stack_pointer_rtx"
5660465a
KH		 235 "")
236
237(define_insn "pushhi1_h8300hs"
d8fd4914 238 [(parallel [(set (reg:SI SP_REG)
4d5ad877
KH		 239 (plus:SI (reg:SI SP_REG) (const_int -4)))
240 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
241 (match_operand:HI 0 "register_operand" "r"))])]
191ff852 242 "(TARGET_H8300H || TARGET_H8300S)
a62a282b 243 && operands[0] != stack_pointer_rtx"
b275810a 244 "mov.l\\t%S0,@-er7"
5660465a
KH		 245 [(set_attr "length" "4")
246 (set_attr "cc" "clobber")])
247
f24f0897
KH		 248(define_insn "pushhi1_h8300hs_normal"
249 [(parallel [(set (reg:HI SP_REG)
250 (plus:HI (reg:HI SP_REG) (const_int -4)))
251 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
252 (match_operand:HI 0 "register_operand" "r"))])]
253 "(TARGET_H8300H || TARGET_H8300S)
254 && operands[0] != stack_pointer_rtx"
255 "mov.l\\t%S0,@-er7"
256 [(set_attr "length" "4")
257 (set_attr "cc" "clobber")])
258
5660465a 259(define_expand "pushhi1"
232bd029 260 [(use (match_operand:HI 0 "register_operand" ""))]
5660465a
KH		 261 ""
262 "
263{
264 if (TARGET_H8300)
265 emit_insn (gen_pushhi1_h8300 (operands[0]));
f24f0897 266 else if (!TARGET_NORMAL_MODE)
5660465a 267 emit_insn (gen_pushhi1_h8300hs (operands[0]));
f24f0897
KH		 268 else
269 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
5660465a
KH		 270 DONE;
271}")
272
61f33c67 273(define_insn "*movhi_h8300"
bf63e3a2
JL		 274 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
275 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
ba412630 276 "TARGET_H8300
20c907b0 277 && (register_operand (operands[0], HImode)
0cb3708d
KH		 278 || register_operand (operands[1], HImode))
279 && !(GET_CODE (operands[0]) == MEM
280 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
281 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
282 && GET_CODE (operands[1]) == REG
283 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
f82eca4d
SC		 284 "@
285 sub.w %T0,%T0
286 mov.w %T1,%T0
287 mov.w %T1,%T0
288 mov.w %T1,%T0
887a8bd9 289 mov.w %T1,%T0
f82eca4d 290 mov.w %T1,%T0"
7948a9ea
KH		 291 [(set (attr "length")
292 (symbol_ref "compute_mov_length (operands)"))
065bbfe6 293 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
f82eca4d 294
61f33c67 295(define_insn "*movhi_h8300hs"
5660465a
KH		 296 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
297 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
ba412630 298 "(TARGET_H8300H || TARGET_H8300S)
20c907b0 299 && (register_operand (operands[0], HImode)
ba412630
KH		 300 || register_operand (operands[1], HImode))"
301 "@
302 sub.w %T0,%T0
303 mov.w %T1,%T0
304 mov.w %T1,%T0
ba412630
KH		 305 mov.w %T1,%T0
306 mov.w %T1,%T0
307 mov.w %T1,%T0"
7948a9ea
KH		 308 [(set (attr "length")
309 (symbol_ref "compute_mov_length (operands)"))
5660465a 310 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
ba412630 311
f82eca4d 312(define_expand "movhi"
5660465a 313 [(set (match_operand:HI 0 "general_operand_dst" "")
f82eca4d
SC		 314 (match_operand:HI 1 "general_operand_src" ""))]
315 ""
316 "
317{
1a63219b
KH		 318 /* One of the ops has to be in a register. */
319 if (!register_operand (operand1, HImode)
320 && !register_operand (operand0, HImode))
b4d2cd97 321 {
1a63219b 322 operands[1] = copy_to_mode_reg (HImode, operand1);
b4d2cd97 323 }
f82eca4d
SC		 324}")
325
b4d2cd97 326(define_insn "movstricthi"
4843bda9 327 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
bf63e3a2 328 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
f82eca4d
SC		 329 ""
330 "@
b4d2cd97
DE		 331 sub.w %T0,%T0
332 mov.w %T1,%T0
887a8bd9 333 mov.w %T1,%T0
b4d2cd97 334 mov.w %T1,%T0"
7948a9ea
KH		 335 [(set (attr "length")
336 (symbol_ref "compute_mov_length (operands)"))
065bbfe6 337 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
f82eca4d 338
b4d2cd97 339;; movsi
f82eca4d 340
b4d2cd97
DE		 341(define_expand "movsi"
342 [(set (match_operand:SI 0 "general_operand_dst" "")
343 (match_operand:SI 1 "general_operand_src" ""))]
f82eca4d
SC		 344 ""
345 "
346{
b4d2cd97
DE		 347 if (TARGET_H8300)
348 {
349 if (do_movsi (operands))
350 DONE;
351 }
a1616dd9 352 else
b4d2cd97
DE		 353 {
354 /* One of the ops has to be in a register. */
355 if (!register_operand (operand1, SImode)
356 && !register_operand (operand0, SImode))
357 {
358 operands[1] = copy_to_mode_reg (SImode, operand1);
359 }
360 }
f82eca4d
SC		 361}")
362
b4d2cd97
DE		 363(define_expand "movsf"
364 [(set (match_operand:SF 0 "general_operand_dst" "")
365 (match_operand:SF 1 "general_operand_src" ""))]
f82eca4d 366 ""
b4d2cd97
DE		 367 "
368{
369 if (TARGET_H8300)
370 {
371 if (do_movsi (operands))
372 DONE;
373 }
a1616dd9 374 else
b4d2cd97
DE		 375 {
376 /* One of the ops has to be in a register. */
377 if (!register_operand (operand1, SFmode)
378 && !register_operand (operand0, SFmode))
379 {
380 operands[1] = copy_to_mode_reg (SFmode, operand1);
381 }
382 }
383}")
384
61f33c67 385(define_insn "*movsi_h8300"
b4d2cd97 386 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
e6219736 387 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
b4d2cd97
DE		 388 "TARGET_H8300
389 && (register_operand (operands[0], SImode)
390 || register_operand (operands[1], SImode))"
f82eca4d
SC		 391 "*
392{
4977bab6 393 unsigned int rn = -1;
f82eca4d
SC		 394 switch (which_alternative)
395 {
396 case 0:
397 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
398 case 1:
c127c127 399 if (REGNO (operands[0]) < REGNO (operands[1]))
b4d2cd97 400 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
c127c127 401 else
b4d2cd97 402 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
f82eca4d
SC		 403 case 2:
404 /* Make sure we don't trample the register we index with. */
c127c127 405 if (GET_CODE (operands[1]) == MEM)
f82eca4d 406 {
20c907b0 407 rtx inside = XEXP (operands[1], 0);
c127c127 408 if (REG_P (inside))
b4d2cd97 409 {
c127c127 410 rn = REGNO (inside);
b4d2cd97 411 }
c127c127 412 else if (GET_CODE (inside) == PLUS)
f82eca4d 413 {
20c907b0
KH		 414 rtx lhs = XEXP (inside, 0);
415 rtx rhs = XEXP (inside, 1);
b4d2cd97
DE		 416 if (REG_P (lhs)) rn = REGNO (lhs);
417 if (REG_P (rhs)) rn = REGNO (rhs);
f82eca4d
SC		 418 }
419 }
c127c127 420 if (rn == REGNO (operands[0]))
b4d2cd97
DE		 421 {
422 /* Move the second word first. */
423 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
424 }
c127c127 425 else
b4d2cd97 426 {
c127c127
KH		 427 if (GET_CODE (operands[1]) == CONST_INT)
428 {
f5139cc5
KH		 429 /* If either half is zero, use sub.w to clear that
430 half. */
c127c127
KH		 431 if ((INTVAL (operands[1]) & 0xffff) == 0)
432 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
433 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
434 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
f5139cc5
KH		 435 /* If the upper half and the lower half are the same,
436 copy one half to the other. */
437 if ((INTVAL (operands[1]) & 0xffff)
438 == ((INTVAL (operands[1]) >> 16) & 0xffff))
439 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
c127c127
KH		 440 }
441 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
b4d2cd97 442 }
f82eca4d 443 case 3:
c127c127 444 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
f82eca4d
SC		 445 case 4:
446 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
b4d2cd97
DE		 447 case 5:
448 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
441d04c6 449 default:
da1775d6 450 abort ();
f82eca4d
SC		 451 }
452}"
7948a9ea
KH		 453 [(set (attr "length")
454 (symbol_ref "compute_mov_length (operands)"))
f82eca4d
SC		 455 (set_attr "cc" "clobber")])
456
61f33c67 457(define_insn "*movsf_h8300"
b4d2cd97 458 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
fad37371 459 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
b4d2cd97
DE		 460 "TARGET_H8300
461 && (register_operand (operands[0], SFmode)
462 || register_operand (operands[1], SFmode))"
f82eca4d
SC		 463 "*
464{
c127c127 465 /* Copy of the movsi stuff. */
4977bab6 466 unsigned int rn = -1;
f82eca4d
SC		 467 switch (which_alternative)
468 {
469 case 0:
470 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
471 case 1:
c127c127 472 if (REGNO (operands[0]) < REGNO (operands[1]))
b4d2cd97 473 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
c127c127 474 else
b4d2cd97 475 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
f82eca4d
SC		 476 case 2:
477 /* Make sure we don't trample the register we index with. */
c127c127 478 if (GET_CODE (operands[1]) == MEM)
f82eca4d 479 {
20c907b0 480 rtx inside = XEXP (operands[1], 0);
f82eca4d 481 if (REG_P (inside))
b4d2cd97
DE		 482 {
483 rn = REGNO (inside);
484 }
c127c127 485 else if (GET_CODE (inside) == PLUS)
f82eca4d 486 {
20c907b0
KH		 487 rtx lhs = XEXP (inside, 0);
488 rtx rhs = XEXP (inside, 1);
b4d2cd97
DE		 489 if (REG_P (lhs)) rn = REGNO (lhs);
490 if (REG_P (rhs)) rn = REGNO (rhs);
f82eca4d
SC		 491 }
492 }
493 if (rn == REGNO (operands[0]))
c127c127
KH		 494 /* Move the second word first. */
495 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
496 else
497 /* Move the first word first. */
498 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
499
f82eca4d
SC		 500 case 3:
501 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
502 case 4:
503 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
b4d2cd97
DE		 504 case 5:
505 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
441d04c6 506 default:
da1775d6 507 abort ();
b4d2cd97 508 }
f82eca4d 509}"
7948a9ea
KH		 510 [(set (attr "length")
511 (symbol_ref "compute_mov_length (operands)"))
f82eca4d
SC		 512 (set_attr "cc" "clobber")])
513
61f33c67 514(define_insn "*movsi_h8300hs"
b8bbda91
KH		 515 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
516 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
7d9f07f4 517 "(TARGET_H8300S || TARGET_H8300H)
b4d2cd97 518 && (register_operand (operands[0], SImode)
0cb3708d
KH		 519 || register_operand (operands[1], SImode))
520 && !(GET_CODE (operands[0]) == MEM
521 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
522 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
523 && GET_CODE (operands[1]) == REG
524 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
3b7d443c
JL		 525 "*
526{
b5eaf9ba 527 switch (which_alternative)
3b7d443c 528 {
b5eaf9ba
KH		 529 case 0:
530 return \"sub.l %S0,%S0\";
b5eaf9ba 531 case 7:
b5f1747c 532 return \"clrmac\";
b5eaf9ba 533 case 8:
b5f1747c
KH		 534 return \"clrmac\;ldmac %1,macl\";
535 case 9:
b5eaf9ba
KH		 536 return \"stmac macl,%0\";
537 default:
538 if (GET_CODE (operands[1]) == CONST_INT)
3b7d443c 539 {
b5eaf9ba
KH		 540 int val = INTVAL (operands[1]);
541
542 /* Look for constants which can be made by adding an 8-bit
543 number to zero in one of the two low bytes. */
544 if (val == (val & 0xff))
545 {
c127c127 546 operands[1] = GEN_INT ((char) val & 0xff);
1a63219b 547 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
b5eaf9ba 548 }
c127c127 549
b5eaf9ba
KH		 550 if (val == (val & 0xff00))
551 {
c127c127 552 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
1a63219b 553 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
b5eaf9ba 554 }
3b7d443c 555
b3a68dba 556 /* Look for constants that can be obtained by subs, inc, and
4d5ad877 557 dec to 0. */
5965bbf8 558 switch (val & 0xffffffff)
b5eaf9ba 559 {
b3a68dba
KH		 560 case 0xffffffff:
561 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
562 case 0xfffffffe:
563 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
564 case 0xfffffffc:
565 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
566
567 case 0x0000ffff:
568 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
569 case 0x0000fffe:
570 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
571
572 case 0xffff0000:
573 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
574 case 0xfffe0000:
575 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
576
577 case 0x00010000:
578 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
579 case 0x00020000:
580 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
b5eaf9ba 581 }
3b7d443c
JL		 582 }
583 }
584 return \"mov.l %S1,%S0\";
585}"
7948a9ea
KH		 586 [(set (attr "length")
587 (symbol_ref "compute_mov_length (operands)"))
b5f1747c 588 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
f82eca4d 589
61f33c67 590(define_insn "*movsf_h8300h"
bf63e3a2 591 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
fad37371 592 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
a1616dd9 593 "(TARGET_H8300H || TARGET_H8300S)
b4d2cd97
DE		 594 && (register_operand (operands[0], SFmode)
595 || register_operand (operands[1], SFmode))"
596 "@
597 sub.l %S0,%S0
598 mov.l %S1,%S0
599 mov.l %S1,%S0
600 mov.l %S1,%S0
74880096 601 mov.l %S1,%S0
b4d2cd97 602 mov.l %S1,%S0"
7948a9ea
KH		 603 [(set (attr "length")
604 (symbol_ref "compute_mov_length (operands)"))
065bbfe6 605 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
269c14e1 606\f
f82eca4d 607;; ----------------------------------------------------------------------
b4d2cd97 608;; TEST INSTRUCTIONS
f82eca4d
SC		 609;; ----------------------------------------------------------------------
610
3fb9e749 611(define_insn ""
8d795882 612 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
3fb9e749 613 (const_int 1)
cd74ec59
KH		 614 (match_operand 1 "const_int_operand" "n,n")))]
615 "TARGET_H8300"
3fb9e749 616 "btst %Z1,%Y0"
cd74ec59 617 [(set_attr "length" "2,4")
8d795882 618 (set_attr "cc" "set_zn,set_zn")])
3fb9e749
JL		 619
620(define_insn ""
cd74ec59 621 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
3fb9e749 622 (const_int 1)
cd74ec59
KH		 623 (match_operand 1 "const_int_operand" "n")))]
624 "TARGET_H8300"
3fb9e749 625 "btst %Z1,%Y0"
ec497122 626 [(set_attr "length" "2")
065bbfe6 627 (set_attr "cc" "set_zn")])
c127c127 628
681a664b 629(define_insn_and_split "*tst_extzv_1_n"
82b4dc2e
KH		 630 [(set (cc0)
631 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
632 (const_int 1)
633 (match_operand 1 "const_int_operand" "n,n,n")))
634 (clobber (match_scratch:QI 2 "=X,X,&r"))]
3c042316 635 "(TARGET_H8300H || TARGET_H8300S)"
82b4dc2e
KH		 636 "@
637 btst\\t%Z1,%Y0
638 btst\\t%Z1,%Y0
639 #"
681a664b 640 "&& reload_completed
3c042316 641 && !EXTRA_CONSTRAINT (operands[0], 'U')"
d23dff51
KH		 642 [(set (match_dup 2)
643 (match_dup 0))
82b4dc2e
KH		 644 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
645 (const_int 1)
646 (match_dup 1)))
647 (clobber (scratch:QI))])]
681a664b
KH		 648 ""
649 [(set_attr "length" "2,8,10")
650 (set_attr "cc" "set_zn,set_zn,set_zn")])
d23dff51 651
e1aa1a6c 652(define_insn ""
cd74ec59 653 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
e1aa1a6c 654 (const_int 1)
cd74ec59
KH		 655 (match_operand 1 "const_int_operand" "n")))]
656 "(TARGET_H8300H || TARGET_H8300S)
657 && INTVAL (operands[1]) <= 15"
e1aa1a6c
JL		 658 "btst %Z1,%Y0"
659 [(set_attr "length" "2")
065bbfe6 660 (set_attr "cc" "set_zn")])
e1aa1a6c 661
c5979bc6
KH		 662(define_insn_and_split "*tstsi_upper_bit"
663 [(set (cc0)
664 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
665 (const_int 1)
666 (match_operand 1 "const_int_operand" "n")))
667 (clobber (match_scratch:SI 2 "=&r"))]
668 "(TARGET_H8300H || TARGET_H8300S)
669 && INTVAL (operands[1]) >= 16"
670 "#"
671 "&& reload_completed"
672 [(set (match_dup 2)
673 (ior:SI (and:SI (match_dup 2)
674 (const_int -65536))
675 (lshiftrt:SI (match_dup 0)
676 (const_int 16))))
677 (set (cc0)
678 (zero_extract:SI (match_dup 2)
679 (const_int 1)
680 (match_dup 3)))]
681 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
682
22a3d55f
KH		 683(define_insn "*tstsi_variable_bit"
684 [(set (cc0)
685 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
686 (const_int 1)
687 (and:SI (match_operand:SI 1 "register_operand" "r")
688 (const_int 7))))]
689 "TARGET_H8300H || TARGET_H8300S"
690 "btst %w1,%w0"
691 [(set_attr "length" "2")
692 (set_attr "cc" "set_zn")])
693
694(define_insn_and_split "*tstsi_variable_bit_qi"
695 [(set (cc0)
696 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
697 (const_int 1)
698 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
699 (const_int 7))))
700 (clobber (match_scratch:QI 2 "=X,X,&r"))]
701 "(TARGET_H8300H || TARGET_H8300S)"
702 "@
703 btst\\t%w1,%X0
704 btst\\t%w1,%X0
705 #"
706 "&& reload_completed
707 && !EXTRA_CONSTRAINT (operands[0], 'U')"
708 [(set (match_dup 2)
709 (match_dup 0))
710 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
711 (const_int 1)
712 (and:SI (match_dup 1)
713 (const_int 7))))
714 (clobber (scratch:QI))])]
715 ""
716 [(set_attr "length" "2,8,10")
717 (set_attr "cc" "set_zn,set_zn,set_zn")])
718
f82eca4d 719(define_insn "tstqi"
e6219736 720 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
f82eca4d 721 ""
2accfbc7 722 "mov.b %X0,%X0"
ec497122 723 [(set_attr "length" "2")
065bbfe6 724 (set_attr "cc" "set_znv")])
f82eca4d
SC		 725
726(define_insn "tsthi"
e6219736 727 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
b4d2cd97 728 ""
269c14e1 729 "mov.w %T0,%T0"
ec497122 730 [(set_attr "length" "2")
065bbfe6 731 (set_attr "cc" "set_znv")])
b4d2cd97 732
ffdf5eae
KH		 733(define_insn ""
734 [(set (cc0)
735 (and:HI (match_operand:HI 0 "register_operand" "r")
736 (const_int -256)))]
737 ""
738 "mov.b %t0,%t0"
739 [(set_attr "length" "2")
740 (set_attr "cc" "set_znv")])
741
b4d2cd97 742(define_insn "tstsi"
e6219736 743 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
a1616dd9 744 "TARGET_H8300H || TARGET_H8300S"
269c14e1 745 "mov.l %S0,%S0"
ec497122 746 [(set_attr "length" "2")
ffdf5eae
KH		 747 (set_attr "cc" "set_znv")])
748
749(define_insn ""
750 [(set (cc0)
751 (and:SI (match_operand:SI 0 "register_operand" "r")
752 (const_int -65536)))]
753 ""
754 "mov.w %e0,%e0"
755 [(set_attr "length" "2")
065bbfe6 756 (set_attr "cc" "set_znv")])
b4d2cd97
DE		 757
758(define_insn "cmpqi"
f82eca4d 759 [(set (cc0)
6dc50366
KH		 760 (compare (match_operand:QI 0 "register_operand" "r")
761 (match_operand:QI 1 "nonmemory_operand" "rn")))]
f82eca4d 762 ""
b4d2cd97 763 "cmp.b %X1,%X0"
ec497122 764 [(set_attr "length" "2")
b4d2cd97
DE		 765 (set_attr "cc" "compare")])
766
2accfbc7
JL		 767(define_expand "cmphi"
768 [(set (cc0)
6dc50366
KH		 769 (compare (match_operand:HI 0 "register_operand" "")
770 (match_operand:HI 1 "nonmemory_operand" "")))]
2accfbc7
JL		 771 ""
772 "
773{
774 /* Force operand1 into a register if we're compiling
1898584f 775 for the H8/300. */
a1616dd9 776 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
2accfbc7
JL		 777 operands[1] = force_reg (HImode, operands[1]);
778}")
f82eca4d 779
6dc50366 780(define_insn "*cmphi_h8300"
f82eca4d 781 [(set (cc0)
6dc50366
KH		 782 (compare (match_operand:HI 0 "register_operand" "r")
783 (match_operand:HI 1 "register_operand" "r")))]
dd4fd0a0 784 "TARGET_H8300"
f82eca4d 785 "cmp.w %T1,%T0"
ec497122 786 [(set_attr "length" "2")
f82eca4d
SC		 787 (set_attr "cc" "compare")])
788
6dc50366 789(define_insn "*cmphi_h8300hs"
2accfbc7 790 [(set (cc0)
6dc50366
KH		 791 (compare (match_operand:HI 0 "register_operand" "r,r")
792 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
a1616dd9 793 "TARGET_H8300H || TARGET_H8300S"
2accfbc7 794 "cmp.w %T1,%T0"
dd4fd0a0
JL		 795 [(set_attr "length" "2,4")
796 (set_attr "cc" "compare,compare")])
b4d2cd97
DE		 797
798(define_insn "cmpsi"
f82eca4d 799 [(set (cc0)
6dc50366
KH		 800 (compare (match_operand:SI 0 "register_operand" "r,r")
801 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
a1616dd9 802 "TARGET_H8300H || TARGET_H8300S"
b4d2cd97 803 "cmp.l %S1,%S0"
dd4fd0a0
JL		 804 [(set_attr "length" "2,6")
805 (set_attr "cc" "compare,compare")])
269c14e1 806\f
f82eca4d 807;; ----------------------------------------------------------------------
b4d2cd97 808;; ADD INSTRUCTIONS
f82eca4d
SC		 809;; ----------------------------------------------------------------------
810
b4d2cd97
DE		 811(define_insn "addqi3"
812 [(set (match_operand:QI 0 "register_operand" "=r")
813 (plus:QI (match_operand:QI 1 "register_operand" "%0")
bf63e3a2 814 (match_operand:QI 2 "nonmemory_operand" "rn")))]
b4d2cd97
DE		 815 ""
816 "add.b %X2,%X0"
ec497122 817 [(set_attr "length" "2")
065bbfe6 818 (set_attr "cc" "set_zn")])
b4d2cd97 819
3b7d443c
JL		 820(define_expand "addhi3"
821 [(set (match_operand:HI 0 "register_operand" "")
822 (plus:HI (match_operand:HI 1 "register_operand" "")
823 (match_operand:HI 2 "nonmemory_operand" "")))]
824 ""
825 "")
826
8cc5359b 827(define_insn "*addhi3_h8300"
697d8028
KH		 828 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
829 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
830 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
3b7d443c 831 "TARGET_H8300"
f82eca4d 832 "@
9bf25b09
KH		 833 adds %2,%T0
834 subs %G2,%T0
8cc5359b 835 add.b %t2,%t0
c127c127 836 add.b %s2,%s0\;addx %t2,%t0
697d8028
KH		 837 add.w %T2,%T0"
838 [(set_attr "length" "2,2,2,4,2")
839 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
3b7d443c 840
8ccf5d5f
KH		 841;; This splitter is very important to make the stack adjustment
842;; interrupt-safe. The combination of add.b and addx is unsafe!
843;;
844;; We apply this split after the peephole2 pass so that we won't end
845;; up creating too many adds/subs when a scratch register is
846;; available, which is actually a common case because stack unrolling
847;; tends to happen immediately after a function call.
848
849(define_split
850 [(set (match_operand:HI 0 "stack_pointer_operand" "")
851 (plus:HI (match_dup 0)
852 (match_operand 1 "const_int_gt_2_operand" "")))]
853 "TARGET_H8300 && flow2_completed"
854 [(const_int 0)]
590734b6 855 "split_adds_subs (HImode, operands); DONE;")
8ccf5d5f
KH		 856
857(define_peephole2
858 [(match_scratch:HI 2 "r")
859 (set (match_operand:HI 0 "stack_pointer_operand" "")
860 (plus:HI (match_dup 0)
861 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
862 "TARGET_H8300"
863 [(set (match_dup 2)
864 (match_dup 1))
865 (set (match_dup 0)
866 (plus:HI (match_dup 0)
867 (match_dup 2)))]
868 "")
869
8cc5359b
KH		 870(define_insn "*addhi3_h8300hs"
871 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
872 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
873 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
a1616dd9 874 "TARGET_H8300H || TARGET_H8300S"
3b7d443c 875 "@
9bf25b09
KH		 876 adds %2,%S0
877 subs %G2,%S0
8cc5359b 878 add.b %t2,%t0
3b7d443c
JL		 879 add.w %T2,%T0
880 add.w %T2,%T0"
8cc5359b
KH		 881 [(set_attr "length" "2,2,2,4,2")
882 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
009ac3d3 883
d64f6f86 884(define_insn "*addhi3_incdec"
f9d2de4d
KH		 885 [(set (match_operand:HI 0 "register_operand" "=r,r")
886 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
887 (match_operand:HI 2 "incdec_operand" "M,O")]
888 UNSPEC_INCDEC))]
889 "TARGET_H8300H || TARGET_H8300S"
890 "@
891 inc.w %2,%T0
892 dec.w %G2,%T0"
893 [(set_attr "length" "2,2")
894 (set_attr "cc" "set_zn,set_zn")])
895
009ac3d3
RH		 896(define_split
897 [(set (match_operand:HI 0 "register_operand" "")
898 (plus:HI (match_dup 0)
899 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
900 ""
901 [(const_int 0)]
590734b6 902 "split_adds_subs (HImode, operands); DONE;")
f82eca4d 903
b4d2cd97
DE		 904(define_expand "addsi3"
905 [(set (match_operand:SI 0 "register_operand" "")
906 (plus:SI (match_operand:SI 1 "register_operand" "")
907 (match_operand:SI 2 "nonmemory_operand" "")))]
f82eca4d 908 ""
b4d2cd97 909 "")
f82eca4d 910
b4d2cd97 911(define_insn "addsi_h8300"
309c52b5
KH		 912 [(set (match_operand:SI 0 "register_operand" "=r,r")
913 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
914 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
b4d2cd97 915 "TARGET_H8300"
cfedf91b
KH		 916 "* return output_plussi (operands);"
917 [(set (attr "length")
918 (symbol_ref "compute_plussi_length (operands)"))
919 (set (attr "cc")
920 (symbol_ref "compute_plussi_cc (operands)"))])
f82eca4d 921
b4d2cd97 922(define_insn "addsi_h8300h"
7d6ac401
KH		 923 [(set (match_operand:SI 0 "register_operand" "=r,r")
924 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
925 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
a1616dd9 926 "TARGET_H8300H || TARGET_H8300S"
7d6ac401
KH		 927 "* return output_plussi (operands);"
928 [(set (attr "length")
929 (symbol_ref "compute_plussi_length (operands)"))
930 (set (attr "cc")
931 (symbol_ref "compute_plussi_cc (operands)"))])
009ac3d3 932
d64f6f86 933(define_insn "*addsi3_incdec"
f9d2de4d
KH		 934 [(set (match_operand:SI 0 "register_operand" "=r,r")
935 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
936 (match_operand:SI 2 "incdec_operand" "M,O")]
937 UNSPEC_INCDEC))]
938 "TARGET_H8300H || TARGET_H8300S"
939 "@
940 inc.l %2,%S0
941 dec.l %G2,%S0"
942 [(set_attr "length" "2,2")
943 (set_attr "cc" "set_zn,set_zn")])
944
009ac3d3
RH		 945(define_split
946 [(set (match_operand:SI 0 "register_operand" "")
947 (plus:SI (match_dup 0)
948 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
949 "TARGET_H8300H || TARGET_H8300S"
950 [(const_int 0)]
590734b6 951 "split_adds_subs (SImode, operands); DONE;")
f82eca4d 952
f82eca4d 953;; ----------------------------------------------------------------------
b4d2cd97
DE		 954;; SUBTRACT INSTRUCTIONS
955;; ----------------------------------------------------------------------
f82eca4d
SC		 956
957(define_insn "subqi3"
e1429da0
KH		 958 [(set (match_operand:QI 0 "register_operand" "=r")
959 (minus:QI (match_operand:QI 1 "register_operand" "0")
960 (match_operand:QI 2 "register_operand" "r")))]
f82eca4d 961 ""
e1429da0 962 "sub.b %X2,%X0"
ec497122 963 [(set_attr "length" "2")
065bbfe6 964 (set_attr "cc" "set_zn")])
f82eca4d 965
17b706a6
JL		 966(define_expand "subhi3"
967 [(set (match_operand:HI 0 "register_operand" "")
968 (minus:HI (match_operand:HI 1 "general_operand" "")
969 (match_operand:HI 2 "nonmemory_operand" "")))]
b4d2cd97 970 ""
17b706a6
JL		 971 "")
972
17b706a6 973(define_insn ""
bd93f126 974 [(set (match_operand:HI 0 "register_operand" "=r,&r")
17b706a6 975 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
bd93f126 976 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
17b706a6 977 "TARGET_H8300"
b4d2cd97 978 "@
b4d2cd97 979 sub.w %T2,%T0
dd4fd0a0 980 add.b %E2,%s0\;addx %F2,%t0"
ec497122 981 [(set_attr "length" "2,4")
065bbfe6 982 (set_attr "cc" "set_zn,clobber")])
17b706a6
JL		 983
984(define_insn ""
bd93f126 985 [(set (match_operand:HI 0 "register_operand" "=r,&r")
17b706a6 986 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
bf63e3a2 987 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
a1616dd9 988 "TARGET_H8300H || TARGET_H8300S"
17b706a6
JL		 989 "@
990 sub.w %T2,%T0
991 sub.w %T2,%T0"
ec497122 992 [(set_attr "length" "2,4")
065bbfe6 993 (set_attr "cc" "set_zn,set_zn")])
f82eca4d 994
b4d2cd97
DE		 995(define_expand "subsi3"
996 [(set (match_operand:SI 0 "register_operand" "")
997 (minus:SI (match_operand:SI 1 "register_operand" "")
998 (match_operand:SI 2 "nonmemory_operand" "")))]
f82eca4d 999 ""
b4d2cd97
DE		 1000 "")
1001
1002(define_insn "subsi3_h8300"
1003 [(set (match_operand:SI 0 "register_operand" "=r")
1004 (minus:SI (match_operand:SI 1 "register_operand" "0")
1005 (match_operand:SI 2 "register_operand" "r")))]
1006 "TARGET_H8300"
f82eca4d 1007 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
ec497122 1008 [(set_attr "length" "6")
f82eca4d
SC		 1009 (set_attr "cc" "clobber")])
1010
b4d2cd97 1011(define_insn "subsi3_h8300h"
bd93f126 1012 [(set (match_operand:SI 0 "register_operand" "=r,r")
17b706a6 1013 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
bd93f126 1014 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
a1616dd9 1015 "TARGET_H8300H || TARGET_H8300S"
b4d2cd97 1016 "@
b4d2cd97
DE		 1017 sub.l %S2,%S0
1018 sub.l %S2,%S0"
ec497122 1019 [(set_attr "length" "2,6")
065bbfe6 1020 (set_attr "cc" "set_zn,set_zn")])
269c14e1 1021\f
f82eca4d 1022;; ----------------------------------------------------------------------
b4d2cd97 1023;; MULTIPLY INSTRUCTIONS
f82eca4d
SC		 1024;; ----------------------------------------------------------------------
1025
1898584f 1026;; Note that the H8/300 can only handle umulqihi3.
b4d2cd97
DE		 1027
1028(define_insn "mulqihi3"
1029 [(set (match_operand:HI 0 "register_operand" "=r")
35dad9f1 1030 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
b4d2cd97 1031 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
a1616dd9 1032 "TARGET_H8300H || TARGET_H8300S"
b4d2cd97 1033 "mulxs.b %X2,%T0"
ec497122 1034 [(set_attr "length" "4")
065bbfe6 1035 (set_attr "cc" "set_zn")])
b4d2cd97
DE		 1036
1037(define_insn "mulhisi3"
1038 [(set (match_operand:SI 0 "register_operand" "=r")
35dad9f1 1039 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
b4d2cd97 1040 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
a1616dd9 1041 "TARGET_H8300H || TARGET_H8300S"
b4d2cd97 1042 "mulxs.w %T2,%S0"
ec497122 1043 [(set_attr "length" "4")
065bbfe6 1044 (set_attr "cc" "set_zn")])
b4d2cd97 1045
f82eca4d
SC		 1046(define_insn "umulqihi3"
1047 [(set (match_operand:HI 0 "register_operand" "=r")
35dad9f1 1048 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
b4d2cd97 1049 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
f82eca4d
SC		 1050 ""
1051 "mulxu %X2,%T0"
ec497122 1052 [(set_attr "length" "2")
f82eca4d
SC		 1053 (set_attr "cc" "none_0hit")])
1054
b4d2cd97
DE		 1055(define_insn "umulhisi3"
1056 [(set (match_operand:SI 0 "register_operand" "=r")
35dad9f1 1057 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
b4d2cd97 1058 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
a1616dd9 1059 "TARGET_H8300H || TARGET_H8300S"
b4d2cd97 1060 "mulxu.w %T2,%S0"
ec497122 1061 [(set_attr "length" "2")
b4d2cd97
DE		 1062 (set_attr "cc" "none_0hit")])
1063
7d9f07f4
JL		 1064;; This is a "bridge" instruction. Combine can't cram enough insns
1065;; together to crate a MAC instruction directly, but it can create
1066;; this instruction, which then allows combine to create the real
1067;; MAC insn.
1068;;
1069;; Unfortunately, if combine doesn't create a MAC instruction, this
1070;; insn must generate reasonably correct code. Egad.
1071(define_insn ""
1072 [(set (match_operand:SI 0 "register_operand" "=a")
1073 (mult:SI
1074 (sign_extend:SI
1075 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1076 (sign_extend:SI
1077 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
17f0f8fa 1078 "TARGET_MAC"
69ff85f3 1079 "clrmac\;mac @%2+,@%1+"
7d9f07f4
JL		 1080 [(set_attr "length" "6")
1081 (set_attr "cc" "none_0hit")])
1082
1083(define_insn ""
1084 [(set (match_operand:SI 0 "register_operand" "=a")
103c41c1 1085 (plus:SI (mult:SI
7d9f07f4
JL		 1086 (sign_extend:SI (mem:HI
1087 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1088 (sign_extend:SI (mem:HI
1089 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1090 (match_operand:SI 3 "register_operand" "0")))]
17f0f8fa 1091 "TARGET_MAC"
69ff85f3 1092 "mac @%2+,@%1+"
7d9f07f4
JL		 1093 [(set_attr "length" "4")
1094 (set_attr "cc" "none_0hit")])
1095
f82eca4d 1096;; ----------------------------------------------------------------------
05fb1639 1097;; DIVIDE/MOD INSTRUCTIONS
f82eca4d
SC		 1098;; ----------------------------------------------------------------------
1099
d0029ebd 1100(define_insn "udivmodqi4"
f82eca4d 1101 [(set (match_operand:QI 0 "register_operand" "=r")
cca19830
JL		 1102 (truncate:QI
1103 (udiv:HI
4915d3aa 1104 (match_operand:HI 1 "register_operand" "0")
05fb1639
KH		 1105 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1106 (set (match_operand:QI 3 "register_operand" "=r")
cca19830 1107 (truncate:QI
05fb1639
KH		 1108 (umod:HI
1109 (match_dup 1)
1110 (zero_extend:HI (match_dup 2)))))]
6588987e 1111 ""
05fb1639
KH		 1112 "*
1113{
1114 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1115 return \"divxu.b\\t%X2,%T0\";
1116 else
1117 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1118}"
ec497122 1119 [(set_attr "length" "4")
b4d2cd97
DE		 1120 (set_attr "cc" "clobber")])
1121
05fb1639 1122(define_insn "divmodqi4"
b4d2cd97 1123 [(set (match_operand:QI 0 "register_operand" "=r")
cca19830 1124 (truncate:QI
05fb1639 1125 (div:HI
4915d3aa 1126 (match_operand:HI 1 "register_operand" "0")
05fb1639
KH		 1127 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1128 (set (match_operand:QI 3 "register_operand" "=r")
cca19830
JL		 1129 (truncate:QI
1130 (mod:HI
05fb1639
KH		 1131 (match_dup 1)
1132 (sign_extend:HI (match_dup 2)))))]
a1616dd9 1133 "TARGET_H8300H || TARGET_H8300S"
05fb1639
KH		 1134 "*
1135{
1136 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1137 return \"divxs.b\\t%X2,%T0\";
1138 else
1139 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1140}"
ec497122 1141 [(set_attr "length" "6")
b4d2cd97
DE		 1142 (set_attr "cc" "clobber")])
1143
d0029ebd 1144(define_insn "udivmodhi4"
b4d2cd97 1145 [(set (match_operand:HI 0 "register_operand" "=r")
cca19830 1146 (truncate:HI
05fb1639 1147 (udiv:SI
4915d3aa 1148 (match_operand:SI 1 "register_operand" "0")
05fb1639
KH		 1149 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1150 (set (match_operand:HI 3 "register_operand" "=r")
1151 (truncate:HI
1152 (umod:SI
1153 (match_dup 1)
1154 (zero_extend:SI (match_dup 2)))))]
a1616dd9 1155 "TARGET_H8300H || TARGET_H8300S"
05fb1639
KH		 1156 "*
1157{
1158 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1159 return \"divxu.w\\t%T2,%S0\";
1160 else
1161 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1162}"
ec497122 1163 [(set_attr "length" "4")
b4d2cd97
DE		 1164 (set_attr "cc" "clobber")])
1165
05fb1639 1166(define_insn "divmodhi4"
b4d2cd97 1167 [(set (match_operand:HI 0 "register_operand" "=r")
cca19830 1168 (truncate:HI
05fb1639 1169 (div:SI
4915d3aa 1170 (match_operand:SI 1 "register_operand" "0")
05fb1639
KH		 1171 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1172 (set (match_operand:HI 3 "register_operand" "=r")
1173 (truncate:HI
1174 (mod:SI
1175 (match_dup 1)
1176 (sign_extend:SI (match_dup 2)))))]
a1616dd9 1177 "TARGET_H8300H || TARGET_H8300S"
05fb1639
KH		 1178 "*
1179{
1180 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1181 return \"divxs.w\\t%T2,%S0\";
1182 else
1183 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1184}"
ec497122 1185 [(set_attr "length" "6")
b4d2cd97 1186 (set_attr "cc" "clobber")])
269c14e1 1187\f
b4d2cd97
DE		 1188;; ----------------------------------------------------------------------
1189;; AND INSTRUCTIONS
1190;; ----------------------------------------------------------------------
1191
dd4fd0a0 1192(define_insn ""
b4d2cd97
DE		 1193 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1194 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
46be79e7 1195 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
4d4d89e2
KH		 1196 "register_operand (operands[0], QImode)
1197 || single_zero_operand (operands[2], QImode)"
b4d2cd97
DE		 1198 "@
1199 and %X2,%X0
15dc331e 1200 bclr %W2,%R0"
8d795882 1201 [(set_attr "length" "2,8")
065bbfe6 1202 (set_attr "cc" "set_znv,none_0hit")])
b4d2cd97
DE		 1203
1204(define_expand "andqi3"
dd4fd0a0
JL		 1205 [(set (match_operand:QI 0 "bit_operand" "")
1206 (and:QI (match_operand:QI 1 "bit_operand" "")
1207 (match_operand:QI 2 "nonmemory_operand" "")))]
b4d2cd97
DE		 1208 ""
1209 "
1210{
2e760b15 1211 if (fix_bit_operand (operands, 0, AND))
b4d2cd97
DE		 1212 DONE;
1213}")
1214
366a7b27
KH		 1215(define_expand "andhi3"
1216 [(set (match_operand:HI 0 "register_operand" "")
1217 (and:HI (match_operand:HI 1 "register_operand" "")
1218 (match_operand:HI 2 "nonmemory_operand" "")))]
1219 ""
1220 "")
1221
f6d45746
KH		 1222(define_insn "*andorqi3"
1223 [(set (match_operand:QI 0 "register_operand" "=r")
1224 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
4d4d89e2 1225 (match_operand:QI 3 "single_one_operand" "n"))
f6d45746 1226 (match_operand:QI 1 "register_operand" "0")))]
4d4d89e2 1227 ""
ac655495
KH		 1228 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1229 [(set_attr "length" "6")
f6d45746
KH		 1230 (set_attr "cc" "clobber")])
1231
ee437932
R		 1232(define_insn "*andorhi3"
1233 [(set (match_operand:HI 0 "register_operand" "=r")
1234 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
4d4d89e2 1235 (match_operand:HI 3 "single_one_operand" "n"))
6d55e887 1236 (match_operand:HI 1 "register_operand" "0")))]
4d4d89e2 1237 ""
ee437932
R		 1238 "*
1239{
d1e76310 1240 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
ee437932
R		 1241 if (INTVAL (operands[3]) > 128)
1242 {
1243 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
ac655495 1244 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
ee437932 1245 }
ac655495 1246 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
ee437932 1247}"
ac655495 1248 [(set_attr "length" "6")
ee437932
R		 1249 (set_attr "cc" "clobber")])
1250
eed13f9b
KH		 1251(define_insn "*andorsi3"
1252 [(set (match_operand:SI 0 "register_operand" "=r")
1253 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1254 (match_operand:SI 3 "single_one_operand" "n"))
6d55e887 1255 (match_operand:SI 1 "register_operand" "0")))]
eed13f9b
KH		 1256 "(INTVAL (operands[3]) & 0xffff) != 0"
1257 "*
1258{
1259 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1260 if (INTVAL (operands[3]) > 128)
1261 {
1262 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
ac655495 1263 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
eed13f9b 1264 }
ac655495 1265 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
eed13f9b 1266}"
ac655495 1267 [(set_attr "length" "6")
eed13f9b
KH		 1268 (set_attr "cc" "clobber")])
1269
94f09825
KH		 1270(define_insn "*andorsi3_shift_8"
1271 [(set (match_operand:SI 0 "register_operand" "=r")
1272 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1273 (const_int 8))
1274 (const_int 65280))
1275 (match_operand:SI 1 "register_operand" "0")))]
1276 ""
1277 "or.b\\t%w2,%x0"
1278 [(set_attr "length" "2")
1279 (set_attr "cc" "clobber")])
1280
366a7b27
KH		 1281(define_expand "andsi3"
1282 [(set (match_operand:SI 0 "register_operand" "")
1283 (and:SI (match_operand:SI 1 "register_operand" "")
1284 (match_operand:SI 2 "nonmemory_operand" "")))]
1285 ""
1286 "")
1287
f82eca4d 1288;; ----------------------------------------------------------------------
b4d2cd97 1289;; OR INSTRUCTIONS
f82eca4d
SC		 1290;; ----------------------------------------------------------------------
1291
dd4fd0a0 1292(define_insn ""
953b10d0 1293 [(set (match_operand:QI 0 "bit_operand" "=r,U")
b4d2cd97 1294 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
dc271dbe
KH		 1295 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1296 "register_operand (operands[0], QImode)
4d4d89e2
KH		 1297 || single_one_operand (operands[2], QImode)"
1298 "@
1299 or\\t%X2,%X0
1300 bset\\t%V2,%R0"
8d795882 1301 [(set_attr "length" "2,8")
065bbfe6 1302 (set_attr "cc" "set_znv,none_0hit")])
b4d2cd97
DE		 1303
1304(define_expand "iorqi3"
7fcd4787
KH		 1305 [(set (match_operand:QI 0 "bit_operand" "")
1306 (ior:QI (match_operand:QI 1 "bit_operand" "")
1307 (match_operand:QI 2 "nonmemory_operand" "")))]
b4d2cd97
DE		 1308 ""
1309 "
1310{
2e760b15 1311 if (fix_bit_operand (operands, 1, IOR))
b4d2cd97
DE		 1312 DONE;
1313}")
1314
366a7b27 1315(define_expand "iorhi3"
a364bc90
KH		 1316 [(set (match_operand:HI 0 "register_operand" "")
1317 (ior:HI (match_operand:HI 1 "register_operand" "")
1318 (match_operand:HI 2 "nonmemory_operand" "")))]
f82eca4d 1319 ""
366a7b27 1320 "")
953b10d0 1321
366a7b27
KH		 1322(define_expand "iorsi3"
1323 [(set (match_operand:SI 0 "register_operand" "")
1324 (ior:SI (match_operand:SI 1 "register_operand" "")
1325 (match_operand:SI 2 "nonmemory_operand" "")))]
1326 ""
1327 "")
1328
f82eca4d 1329;; ----------------------------------------------------------------------
b4d2cd97 1330;; XOR INSTRUCTIONS
f82eca4d
SC		 1331;; ----------------------------------------------------------------------
1332
dd4fd0a0 1333(define_insn ""
b4d2cd97
DE		 1334 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1335 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
dc271dbe
KH		 1336 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1337 "register_operand (operands[0], QImode)
4d4d89e2
KH		 1338 || single_one_operand (operands[2], QImode)"
1339 "@
1340 xor\\t%X2,%X0
1341 bnot\\t%V2,%R0"
8d795882 1342 [(set_attr "length" "2,8")
065bbfe6 1343 (set_attr "cc" "set_znv,none_0hit")])
b4d2cd97
DE		 1344
1345(define_expand "xorqi3"
7fcd4787
KH		 1346 [(set (match_operand:QI 0 "bit_operand" "")
1347 (xor:QI (match_operand:QI 1 "bit_operand" "")
1348 (match_operand:QI 2 "nonmemory_operand" "")))]
b4d2cd97
DE		 1349 ""
1350 "
1351{
2e760b15 1352 if (fix_bit_operand (operands, 1, XOR))
b4d2cd97
DE		 1353 DONE;
1354}")
f82eca4d 1355
366a7b27
KH		 1356(define_expand "xorhi3"
1357 [(set (match_operand:HI 0 "register_operand" "")
eceb1755 1358 (xor:HI (match_operand:HI 1 "register_operand" "")
366a7b27
KH		 1359 (match_operand:HI 2 "nonmemory_operand" "")))]
1360 ""
1361 "")
1362
366a7b27
KH		 1363(define_expand "xorsi3"
1364 [(set (match_operand:SI 0 "register_operand" "")
1365 (xor:SI (match_operand:SI 1 "register_operand" "")
1366 (match_operand:SI 2 "nonmemory_operand" "")))]
1367 ""
1368 "")
1369
b42cff6b
KH		 1370;; ----------------------------------------------------------------------
1371;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1372;; ----------------------------------------------------------------------
1373
366a7b27 1374(define_insn ""
b42cff6b
KH		 1375 [(set (match_operand:HI 0 "register_operand" "=r")
1376 (match_operator:HI 3 "bit_operator"
1377 [(match_operand:HI 1 "register_operand" "%0")
1378 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1379 ""
1380 "* return output_logical_op (HImode, operands);"
40367e2d 1381 [(set (attr "length")
b42cff6b
KH		 1382 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1383 (set (attr "cc")
1384 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
366a7b27
KH		 1385
1386(define_insn ""
b42cff6b
KH		 1387 [(set (match_operand:SI 0 "register_operand" "=r")
1388 (match_operator:SI 3 "bit_operator"
1389 [(match_operand:SI 1 "register_operand" "%0")
1390 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1391 ""
1392 "* return output_logical_op (SImode, operands);"
40367e2d 1393 [(set (attr "length")
b42cff6b
KH		 1394 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1395 (set (attr "cc")
1396 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
269c14e1 1397\f
f82eca4d 1398;; ----------------------------------------------------------------------
b4d2cd97 1399;; NEGATION INSTRUCTIONS
f82eca4d
SC		 1400;; ----------------------------------------------------------------------
1401
1402(define_insn "negqi2"
1403 [(set (match_operand:QI 0 "register_operand" "=r")
c4df4ceb 1404 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
f82eca4d
SC		 1405 ""
1406 "neg %X0"
ec497122 1407 [(set_attr "length" "2")
065bbfe6 1408 (set_attr "cc" "set_zn")])
f82eca4d
SC		 1409
1410(define_expand "neghi2"
08a02ffa 1411 [(set (match_operand:HI 0 "register_operand" "")
c4df4ceb 1412 (neg:HI (match_operand:HI 1 "register_operand" "")))]
b4d2cd97
DE		 1413 ""
1414 "
1415{
1416 if (TARGET_H8300)
1417 {
1418 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1419 DONE;
1420 }
1421}")
1422
1423(define_expand "neghi2_h8300"
f82eca4d 1424 [(set (match_dup 2)
08a02ffa 1425 (not:HI (match_operand:HI 1 "register_operand" "")))
f82eca4d 1426 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
08a02ffa 1427 (set (match_operand:HI 0 "register_operand" "")
f82eca4d
SC		 1428 (match_dup 2))]
1429 ""
da1775d6 1430 "operands[2] = gen_reg_rtx (HImode);")
b4d2cd97
DE		 1431
1432(define_insn "neghi2_h8300h"
1433 [(set (match_operand:HI 0 "register_operand" "=r")
c4df4ceb 1434 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
a1616dd9 1435 "TARGET_H8300H || TARGET_H8300S"
b4d2cd97 1436 "neg %T0"
ec497122 1437 [(set_attr "length" "2")
065bbfe6 1438 (set_attr "cc" "set_zn")])
f82eca4d
SC		 1439
1440(define_expand "negsi2"
08a02ffa 1441 [(set (match_operand:SI 0 "register_operand" "")
c4df4ceb 1442 (neg:SI (match_operand:SI 1 "register_operand" "")))]
b4d2cd97
DE		 1443 ""
1444 "
1445{
1446 if (TARGET_H8300)
1447 {
1448 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1449 DONE;
1450 }
1451}")
1452
1453(define_expand "negsi2_h8300"
f82eca4d 1454 [(set (match_dup 2)
08a02ffa 1455 (not:SI (match_operand:SI 1 "register_operand" "")))
f82eca4d 1456 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
08a02ffa 1457 (set (match_operand:SI 0 "register_operand" "")
f82eca4d
SC		 1458 (match_dup 2))]
1459 ""
da1775d6 1460 "operands[2] = gen_reg_rtx (SImode);")
b4d2cd97
DE		 1461
1462(define_insn "negsi2_h8300h"
1463 [(set (match_operand:SI 0 "register_operand" "=r")
c4df4ceb 1464 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
a1616dd9 1465 "TARGET_H8300H || TARGET_H8300S"
b4d2cd97 1466 "neg %S0"
ec497122 1467 [(set_attr "length" "2")
065bbfe6 1468 (set_attr "cc" "set_zn")])
b4d2cd97 1469
8fb52ad1
KH		 1470(define_expand "negsf2"
1471 [(set (match_operand:SF 0 "register_operand" "")
1472 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1473 ""
1474 "")
1475
1476(define_insn "*negsf2_h8300"
1477 [(set (match_operand:SF 0 "register_operand" "=r")
1478 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1479 "TARGET_H8300"
e8e8c1e5 1480 "xor.b\\t#128,%z0"
8fb52ad1
KH		 1481 [(set_attr "cc" "clobber")
1482 (set_attr "length" "2")])
1483
1484(define_insn "*negsf2_h8300hs"
1485 [(set (match_operand:SF 0 "register_operand" "=r")
1486 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1487 "TARGET_H8300H || TARGET_H8300S"
e8e8c1e5 1488 "xor.w\\t#32768,%e0"
8fb52ad1
KH		 1489 [(set_attr "cc" "clobber")
1490 (set_attr "length" "4")])
2a4e6df4
KH		 1491\f
1492;; ----------------------------------------------------------------------
1493;; ABSOLUTE VALUE INSTRUCTIONS
1494;; ----------------------------------------------------------------------
8fb52ad1 1495
2a4e6df4
KH		 1496(define_expand "abssf2"
1497 [(set (match_operand:SF 0 "register_operand" "")
1498 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1499 ""
1500 "")
1501
1502(define_insn "*abssf2_h8300"
1503 [(set (match_operand:SF 0 "register_operand" "=r")
1504 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1505 "TARGET_H8300"
1506 "and.b\\t#127,%z0"
1507 [(set_attr "cc" "clobber")
1508 (set_attr "length" "2")])
1509
1510(define_insn "*abssf2_h8300hs"
1511 [(set (match_operand:SF 0 "register_operand" "=r")
1512 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1513 "TARGET_H8300H || TARGET_H8300S"
1514 "and.w\\t#32767,%e0"
1515 [(set_attr "cc" "clobber")
1516 (set_attr "length" "4")])
1517\f
f82eca4d 1518;; ----------------------------------------------------------------------
b4d2cd97 1519;; NOT INSTRUCTIONS
f82eca4d
SC		 1520;; ----------------------------------------------------------------------
1521
1522(define_insn "one_cmplqi2"
1523 [(set (match_operand:QI 0 "register_operand" "=r")
54175a44 1524 (not:QI (match_operand:QI 1 "register_operand" "0")))]
f82eca4d
SC		 1525 ""
1526 "not %X0"
ec497122 1527 [(set_attr "length" "2")
065bbfe6 1528 (set_attr "cc" "set_znv")])
f82eca4d 1529
54175a44 1530(define_expand "one_cmplhi2"
f82eca4d 1531 [(set (match_operand:HI 0 "register_operand" "=r")
54175a44 1532 (not:HI (match_operand:HI 1 "register_operand" "0")))]
f82eca4d 1533 ""
54175a44
KH		 1534 "")
1535
1536(define_insn ""
1537 [(set (match_operand:HI 0 "register_operand" "=r")
1538 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1539 "TARGET_H8300"
1540 "not %s0\;not %t0"
ec497122 1541 [(set_attr "cc" "clobber")
54175a44
KH		 1542 (set_attr "length" "4")])
1543
1544(define_insn ""
1545 [(set (match_operand:HI 0 "register_operand" "=r")
1546 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1547 "TARGET_H8300H || TARGET_H8300S"
1548 "not %T0"
1549 [(set_attr "cc" "set_znv")
1550 (set_attr "length" "2")])
f82eca4d 1551
54175a44 1552(define_expand "one_cmplsi2"
f82eca4d 1553 [(set (match_operand:SI 0 "register_operand" "=r")
54175a44 1554 (not:SI (match_operand:SI 1 "register_operand" "0")))]
f82eca4d 1555 ""
54175a44
KH		 1556 "")
1557
1558(define_insn ""
1559 [(set (match_operand:SI 0 "register_operand" "=r")
1560 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1561 "TARGET_H8300"
1562 "not %w0\;not %x0\;not %y0\;not %z0"
ec497122 1563 [(set_attr "cc" "clobber")
54175a44
KH		 1564 (set_attr "length" "8")])
1565
1566(define_insn ""
1567 [(set (match_operand:SI 0 "register_operand" "=r")
1568 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1569 "TARGET_H8300H || TARGET_H8300S"
1570 "not %S0"
1571 [(set_attr "cc" "set_znv")
1572 (set_attr "length" "2")])
269c14e1 1573\f
f82eca4d 1574;; ----------------------------------------------------------------------
b4d2cd97 1575;; JUMP INSTRUCTIONS
f82eca4d
SC		 1576;; ----------------------------------------------------------------------
1577
b4d2cd97
DE		 1578;; Conditional jump instructions
1579
f82eca4d
SC		 1580(define_expand "ble"
1581 [(set (pc)
1582 (if_then_else (le (cc0)
1583 (const_int 0))
1584 (label_ref (match_operand 0 "" ""))
1585 (pc)))]
1586 ""
1587 "")
1588
1589(define_expand "bleu"
1590 [(set (pc)
1591 (if_then_else (leu (cc0)
1592 (const_int 0))
1593 (label_ref (match_operand 0 "" ""))
1594 (pc)))]
1595 ""
1596 "")
1597
1598(define_expand "bge"
1599 [(set (pc)
1600 (if_then_else (ge (cc0)
1601 (const_int 0))
1602 (label_ref (match_operand 0 "" ""))
1603 (pc)))]
1604 ""
1605 "")
1606
1607(define_expand "bgeu"
1608 [(set (pc)
1609 (if_then_else (geu (cc0)
1610 (const_int 0))
1611 (label_ref (match_operand 0 "" ""))
1612 (pc)))]
1613 ""
1614 "")
1615
1616(define_expand "blt"
1617 [(set (pc)
1618 (if_then_else (lt (cc0)
1619 (const_int 0))
1620 (label_ref (match_operand 0 "" ""))
1621 (pc)))]
1622 ""
1623 "")
1624
1625(define_expand "bltu"
1626 [(set (pc)
1627 (if_then_else (ltu (cc0)
1628 (const_int 0))
1629 (label_ref (match_operand 0 "" ""))
1630 (pc)))]
1631 ""
1632 "")
1633
1634(define_expand "bgt"
1635 [(set (pc)
1636 (if_then_else (gt (cc0)
1637 (const_int 0))
1638 (label_ref (match_operand 0 "" ""))
1639 (pc)))]
1640 ""
1641 "")
1642
1643(define_expand "bgtu"
1644 [(set (pc)
1645 (if_then_else (gtu (cc0)
1646 (const_int 0))
1647 (label_ref (match_operand 0 "" ""))
1648 (pc)))]
1649 ""
1650 "")
1651
1652(define_expand "beq"
1653 [(set (pc)
1654 (if_then_else (eq (cc0)
1655 (const_int 0))
1656 (label_ref (match_operand 0 "" ""))
1657 (pc)))]
1658 ""
1659 "")
1660
1661(define_expand "bne"
1662 [(set (pc)
1663 (if_then_else (ne (cc0)
1664 (const_int 0))
1665 (label_ref (match_operand 0 "" ""))
1666 (pc)))]
1667 ""
1668 "")
1669
b4d2cd97 1670(define_insn "branch_true"
f82eca4d 1671 [(set (pc)
b4d2cd97
DE		 1672 (if_then_else (match_operator 1 "comparison_operator"
1673 [(cc0) (const_int 0)])
1674 (label_ref (match_operand 0 "" ""))
1675 (pc)))]
f82eca4d
SC		 1676 ""
1677 "*
1678{
065bbfe6
JL		 1679 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1680 && (GET_CODE (operands[1]) == GT
4d5ad877
KH		 1681 || GET_CODE (operands[1]) == GE
1682 || GET_CODE (operands[1]) == LE
1683 || GET_CODE (operands[1]) == LT))
065bbfe6
JL		 1684 {
1685 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1686 return 0;
1687 }
1688
c127c127 1689 if (get_attr_length (insn) == 2)
b4d2cd97 1690 return \"b%j1 %l0\";
c127c127 1691 else if (get_attr_length (insn) == 4)
b4d2cd97 1692 return \"b%j1 %l0:16\";
f82eca4d 1693 else
4c95db67 1694 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
c127c127 1695}"
b4d2cd97 1696 [(set_attr "type" "branch")
f82eca4d
SC		 1697 (set_attr "cc" "none")])
1698
b4d2cd97 1699(define_insn "branch_false"
f82eca4d 1700 [(set (pc)
b4d2cd97
DE		 1701 (if_then_else (match_operator 1 "comparison_operator"
1702 [(cc0) (const_int 0)])
1703 (pc)
1704 (label_ref (match_operand 0 "" ""))))]
f82eca4d
SC		 1705 ""
1706 "*
1707{
065bbfe6
JL		 1708 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1709 && (GET_CODE (operands[1]) == GT
4d5ad877
KH		 1710 || GET_CODE (operands[1]) == GE
1711 || GET_CODE (operands[1]) == LE
1712 || GET_CODE (operands[1]) == LT))
065bbfe6
JL		 1713 {
1714 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1715 return 0;
1716 }
1717
c127c127 1718 if (get_attr_length (insn) == 2)
b4d2cd97 1719 return \"b%k1 %l0\";
c127c127 1720 else if (get_attr_length (insn) == 4)
b4d2cd97 1721 return \"b%k1 %l0:16\";
f82eca4d 1722 else
4c95db67 1723 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
f82eca4d
SC		 1724}"
1725 [(set_attr "type" "branch")
1726 (set_attr "cc" "none")])
b4d2cd97
DE		 1727
1728;; Unconditional and other jump instructions.
f82eca4d
SC		 1729
1730(define_insn "jump"
1731 [(set (pc)
1732 (label_ref (match_operand 0 "" "")))]
1733 ""
1734 "*
1735{
b4d2cd97
DE		 1736 if (get_attr_length (insn) == 2)
1737 return \"bra %l0\";
1738 else if (get_attr_length (insn) == 4)
1739 return \"bra %l0:16\";
f82eca4d 1740 else
b4d2cd97 1741 return \"jmp @%l0\";
f82eca4d
SC		 1742}"
1743 [(set_attr "type" "branch")
1744 (set_attr "cc" "none")])
1745
b4d2cd97
DE		 1746;; This is a define expand, because pointers may be either 16 or 32 bits.
1747
1748(define_expand "tablejump"
08a02ffa 1749 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
b4d2cd97
DE		 1750 (use (label_ref (match_operand 1 "" "")))])]
1751 ""
1752 "")
1753
0980ad79 1754(define_insn "*tablejump_h8300"
80c838cd 1755 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
f82eca4d 1756 (use (label_ref (match_operand 1 "" "")))]
b4d2cd97 1757 "TARGET_H8300"
f82eca4d 1758 "jmp @%0"
ec497122 1759 [(set_attr "cc" "none")
f82eca4d
SC		 1760 (set_attr "length" "2")])
1761
0980ad79 1762(define_insn "*tablejump_h8300hs_advanced"
80c838cd 1763 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
b4d2cd97 1764 (use (label_ref (match_operand 1 "" "")))]
a1616dd9 1765 "TARGET_H8300H || TARGET_H8300S"
b4d2cd97 1766 "jmp @%0"
ec497122 1767 [(set_attr "cc" "none")
b4d2cd97 1768 (set_attr "length" "2")])
f82eca4d 1769
0980ad79 1770(define_insn "*tablejump_h8300hs_normal"
39ba95b5
VK		 1771 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1772 (use (label_ref (match_operand 1 "" "")))]
1773 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1774 "jmp @%S0"
1775 [(set_attr "cc" "none")
1776 (set_attr "length" "2")])
1777
b4d2cd97
DE		 1778;; This is a define expand, because pointers may be either 16 or 32 bits.
1779
b4d2cd97 1780(define_expand "indirect_jump"
dd4fd0a0 1781 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
b4d2cd97
DE		 1782 ""
1783 "")
1784
0980ad79 1785(define_insn "*indirect_jump_h8300"
dd4fd0a0 1786 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
b4d2cd97 1787 "TARGET_H8300"
dd4fd0a0 1788 "jmp @%0"
ec497122 1789 [(set_attr "cc" "none")
b4d2cd97
DE		 1790 (set_attr "length" "2")])
1791
0980ad79 1792(define_insn "*indirect_jump_h8300hs_advanced"
dd4fd0a0 1793 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
a1616dd9 1794 "TARGET_H8300H || TARGET_H8300S"
dd4fd0a0 1795 "jmp @%0"
ec497122 1796 [(set_attr "cc" "none")
b4d2cd97
DE		 1797 (set_attr "length" "2")])
1798
0980ad79 1799(define_insn "*indirect_jump_h8300hs_normal"
39ba95b5
VK		 1800 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1801 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1802 "jmp @%S0"
1803 [(set_attr "cc" "none")
1804 (set_attr "length" "2")])
1805
b4d2cd97
DE		 1806;; Call subroutine with no return value.
1807
3db11b5c 1808;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
b4d2cd97
DE		 1809
1810(define_insn "call"
1811 [(call (match_operand:QI 0 "call_insn_operand" "or")
1812 (match_operand:HI 1 "general_operand" "g"))]
f82eca4d 1813 ""
f5b65a56
JL		 1814 "*
1815{
1816 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1817 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
7fcd4787 1818 return \"jsr\\t@%0:8\";
f5b65a56
JL		 1819 else
1820 return \"jsr\\t%0\";
1821}"
ec497122 1822 [(set_attr "cc" "clobber")
f5b65a56 1823 (set (attr "length")
da1775d6 1824 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
7f8b3eb0
KH		 1825 (const_int 2)
1826 (const_int 4)))])
f82eca4d
SC		 1827
1828;; Call subroutine, returning value in operand 0
1829;; (which must be a hard register).
1830
3db11b5c 1831;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
b4d2cd97 1832
f82eca4d
SC		 1833(define_insn "call_value"
1834 [(set (match_operand 0 "" "=r")
b4d2cd97 1835 (call (match_operand:QI 1 "call_insn_operand" "or")
f82eca4d
SC		 1836 (match_operand:HI 2 "general_operand" "g")))]
1837 ""
f5b65a56
JL		 1838 "*
1839{
1840 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1841 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
7fcd4787 1842 return \"jsr\\t@%1:8\";
f5b65a56
JL		 1843 else
1844 return \"jsr\\t%1\";
1845}"
ec497122 1846 [(set_attr "cc" "clobber")
f5b65a56 1847 (set (attr "length")
da1775d6 1848 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
7f8b3eb0
KH		 1849 (const_int 2)
1850 (const_int 4)))])
f82eca4d
SC		 1851
1852(define_insn "nop"
1853 [(const_int 0)]
1854 ""
1855 "nop"
ec497122 1856 [(set_attr "cc" "none")
f82eca4d 1857 (set_attr "length" "2")])
269c14e1 1858\f
b4d2cd97 1859;; ----------------------------------------------------------------------
0a2a0a58
KH		 1860;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1861;; ----------------------------------------------------------------------
1862
68ee6df6
KH		 1863(define_expand "push_h8300"
1864 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
7ed7f009 1865 (match_operand:HI 0 "register_operand" ""))]
68ee6df6
KH		 1866
1867 "TARGET_H8300"
1868 "")
1869
1870(define_expand "push_h8300hs"
1871 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
7ed7f009 1872 (match_operand:SI 0 "register_operand" ""))]
68ee6df6
KH		 1873 "TARGET_H8300H && TARGET_H8300S"
1874 "")
1875
f24f0897
KH		 1876(define_expand "push_h8300hs_normal"
1877 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
7ed7f009 1878 (match_operand:SI 0 "register_operand" ""))]
f24f0897
KH		 1879 "TARGET_NORMAL_MODE"
1880 "")
1881
68ee6df6 1882(define_expand "pop_h8300"
7ed7f009 1883 [(set (match_operand:HI 0 "register_operand" "")
68ee6df6
KH		 1884 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1885 "TARGET_H8300"
1886 "")
1887
1888(define_expand "pop_h8300hs"
7ed7f009 1889 [(set (match_operand:SI 0 "register_operand" "")
68ee6df6
KH		 1890 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1891 "TARGET_H8300H && TARGET_H8300S"
1892 "")
1893
f24f0897 1894(define_expand "pop_h8300hs_normal"
7ed7f009 1895 [(set (match_operand:SI 0 "register_operand" "")
f24f0897
KH		 1896 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
1897 "TARGET_NORMAL_MODE"
1898 "")
1899
bc02597b 1900(define_insn "stm_h8300s_2_advanced"
0a2a0a58
KH		 1901 [(parallel
1902 [(set (reg:SI SP_REG)
1903 (plus:SI (reg:SI SP_REG) (const_int -8)))
1904 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1905 (match_operand:SI 0 "register_operand" ""))
1906 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1907 (match_operand:SI 1 "register_operand" ""))])]
bc02597b
KH		 1908 "TARGET_H8300S && !TARGET_NORMAL_MODE
1909 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1910 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1911 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1912 "stm.l\\t%S0-%S1,@-er7"
1913 [(set_attr "cc" "none")
1914 (set_attr "length" "4")])
1915
1916(define_insn "stm_h8300s_2_normal"
1917 [(parallel
1918 [(set (reg:HI SP_REG)
1919 (plus:HI (reg:HI SP_REG) (const_int -8)))
1920 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1921 (match_operand:SI 0 "register_operand" ""))
1922 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1923 (match_operand:SI 1 "register_operand" ""))])]
1924 "TARGET_H8300S && TARGET_NORMAL_MODE
0a2a0a58
KH		 1925 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1926 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1927 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1928 "stm.l\\t%S0-%S1,@-er7"
1929 [(set_attr "cc" "none")
1930 (set_attr "length" "4")])
1931
bc02597b
KH		 1932(define_expand "stm_h8300s_2"
1933 [(use (match_operand:SI 0 "register_operand" ""))
1934 (use (match_operand:SI 1 "register_operand" ""))]
1935 "TARGET_H8300S
1936 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1937 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1938 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1939 "
1940{
1941 if (!TARGET_NORMAL_MODE)
1942 emit_insn (gen_stm_h8300s_2_advanced (operands[0], operands[1]));
1943 else
1944 emit_insn (gen_stm_h8300s_2_normal (operands[0], operands[1]));
1945 DONE;
1946}")
1947
1948(define_insn "stm_h8300s_3_advanced"
0a2a0a58
KH		 1949 [(parallel
1950 [(set (reg:SI SP_REG)
1951 (plus:SI (reg:SI SP_REG) (const_int -12)))
1952 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1953 (match_operand:SI 0 "register_operand" ""))
1954 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1955 (match_operand:SI 1 "register_operand" ""))
1956 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1957 (match_operand:SI 2 "register_operand" ""))])]
bc02597b 1958 "TARGET_H8300S && !TARGET_NORMAL_MODE
0a2a0a58
KH		 1959 && ((REGNO (operands[0]) == 0
1960 && REGNO (operands[1]) == 1
1961 && REGNO (operands[2]) == 2)
1962 || (REGNO (operands[0]) == 4
1963 && REGNO (operands[1]) == 5
1964 && REGNO (operands[2]) == 6))"
1965 "stm.l\\t%S0-%S2,@-er7"
1966 [(set_attr "cc" "none")
1967 (set_attr "length" "4")])
1968
bc02597b
KH		 1969(define_insn "stm_h8300s_3_normal"
1970 [(parallel
1971 [(set (reg:HI SP_REG)
1972 (plus:HI (reg:HI SP_REG) (const_int -12)))
1973 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1974 (match_operand:SI 0 "register_operand" ""))
1975 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1976 (match_operand:SI 1 "register_operand" ""))
1977 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1978 (match_operand:SI 2 "register_operand" ""))])]
1979 "TARGET_H8300S && TARGET_NORMAL_MODE
1980 && ((REGNO (operands[0]) == 0
1981 && REGNO (operands[1]) == 1
1982 && REGNO (operands[2]) == 2)
1983 || (REGNO (operands[0]) == 4
1984 && REGNO (operands[1]) == 5
1985 && REGNO (operands[2]) == 6))"
1986 "stm.l\\t%S0-%S2,@-er7"
1987 [(set_attr "cc" "none")
1988 (set_attr "length" "4")])
1989
1990(define_expand "stm_h8300s_3"
1991 [(use (match_operand:SI 0 "register_operand" ""))
1992 (use (match_operand:SI 1 "register_operand" ""))
1993 (use (match_operand:SI 2 "register_operand" ""))]
1994 "TARGET_H8300S
1995 && ((REGNO (operands[0]) == 0
1996 && REGNO (operands[1]) == 1
1997 && REGNO (operands[2]) == 2)
1998 || (REGNO (operands[0]) == 4
1999 && REGNO (operands[1]) == 5
2000 && REGNO (operands[2]) == 6))"
2001 "
2002{
2003 if (!TARGET_NORMAL_MODE)
2004 emit_insn (gen_stm_h8300s_3_advanced (operands[0], operands[1],
2005 operands[2]));
2006 else
2007 emit_insn (gen_stm_h8300s_3_normal (operands[0], operands[1],
2008 operands[2]));
2009 DONE;
2010}")
2011
2012(define_insn "stm_h8300s_4_advanced"
0a2a0a58
KH		 2013 [(parallel
2014 [(set (reg:SI SP_REG)
2015 (plus:SI (reg:SI SP_REG) (const_int -16)))
2016 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2017 (match_operand:SI 0 "register_operand" ""))
2018 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2019 (match_operand:SI 1 "register_operand" ""))
2020 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
2021 (match_operand:SI 2 "register_operand" ""))
2022 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
2023 (match_operand:SI 3 "register_operand" ""))])]
bc02597b 2024 "TARGET_H8300S && !TARGET_NORMAL_MODE
0a2a0a58
KH		 2025 && REGNO (operands[0]) == 0
2026 && REGNO (operands[1]) == 1
2027 && REGNO (operands[2]) == 2
2028 && REGNO (operands[3]) == 3"
2029 "stm.l\\t%S0-%S3,@-er7"
2030 [(set_attr "cc" "none")
2031 (set_attr "length" "4")])
68ee6df6 2032
bc02597b
KH		 2033(define_insn "stm_h8300s_4_normal"
2034 [(parallel
2035 [(set (reg:HI SP_REG)
2036 (plus:HI (reg:HI SP_REG) (const_int -16)))
2037 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
2038 (match_operand:SI 0 "register_operand" ""))
2039 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
2040 (match_operand:SI 1 "register_operand" ""))
2041 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
2042 (match_operand:SI 2 "register_operand" ""))
2043 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
2044 (match_operand:SI 3 "register_operand" ""))])]
2045 "TARGET_H8300S && TARGET_NORMAL_MODE
2046 && REGNO (operands[0]) == 0
2047 && REGNO (operands[1]) == 1
2048 && REGNO (operands[2]) == 2
2049 && REGNO (operands[3]) == 3"
2050 "stm.l\\t%S0-%S3,@-er7"
2051 [(set_attr "cc" "none")
2052 (set_attr "length" "4")])
2053
2054(define_expand "stm_h8300s_4"
2055 [(use (match_operand:SI 0 "register_operand" ""))
2056 (use (match_operand:SI 1 "register_operand" ""))
2057 (use (match_operand:SI 2 "register_operand" ""))
2058 (use (match_operand:SI 3 "register_operand" ""))]
2059 "TARGET_H8300S
2060 && REGNO (operands[0]) == 0
2061 && REGNO (operands[1]) == 1
2062 && REGNO (operands[2]) == 2
2063 && REGNO (operands[3]) == 3"
2064 "
2065{
2066 if (!TARGET_NORMAL_MODE)
2067 emit_insn (gen_stm_h8300s_4_advanced (operands[0], operands[1],
2068 operands[2], operands[3]));
2069 else
2070 emit_insn (gen_stm_h8300s_4_normal (operands[0], operands[1],
2071 operands[2], operands[3]));
2072 DONE;
2073}")
2074
2075(define_insn "ldm_h8300s_2_advanced"
68ee6df6
KH		 2076 [(parallel
2077 [(set (reg:SI SP_REG)
2078 (plus:SI (reg:SI SP_REG) (const_int 8)))
2079 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2080 (match_operand:SI 0 "register_operand" ""))
2081 (set (mem:SI (reg:SI SP_REG))
2082 (match_operand:SI 1 "register_operand" ""))])]
bc02597b
KH		 2083 "TARGET_H8300S && !TARGET_NORMAL_MODE
2084 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2085 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2086 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2087 "ldm.l\\t@er7+,%S0-%S1"
2088 [(set_attr "cc" "none")
2089 (set_attr "length" "4")])
2090
2091(define_insn "ldm_h8300s_2_normal"
2092 [(parallel
2093 [(set (reg:SI SP_REG)
2094 (plus:SI (reg:SI SP_REG) (const_int 8)))
2095 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2096 (match_operand:SI 0 "register_operand" ""))
2097 (set (mem:SI (reg:SI SP_REG))
2098 (match_operand:SI 1 "register_operand" ""))])]
2099 "TARGET_H8300S && TARGET_NORMAL_MODE
68ee6df6
KH		 2100 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2101 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2102 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2103 "ldm.l\\t@er7+,%S0-%S1"
2104 [(set_attr "cc" "none")
2105 (set_attr "length" "4")])
2106
bc02597b
KH		 2107(define_expand "ldm_h8300s_2"
2108 [(use (match_operand:SI 0 "register_operand" ""))
2109 (use (match_operand:SI 1 "register_operand" ""))]
2110 "TARGET_H8300S
2111 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2112 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2113 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2114 "
2115{
2116 if (!TARGET_NORMAL_MODE)
2117 emit_insn (gen_ldm_h8300s_2_advanced (operands[0], operands[1]));
2118 else
2119 emit_insn (gen_ldm_h8300s_2_normal (operands[0], operands[1]));
2120 DONE;
2121}")
2122
2123(define_insn "ldm_h8300s_3_advanced"
68ee6df6
KH		 2124 [(parallel
2125 [(set (reg:SI SP_REG)
2126 (plus:SI (reg:SI SP_REG) (const_int 12)))
2127 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2128 (match_operand:SI 0 "register_operand" ""))
2129 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2130 (match_operand:SI 1 "register_operand" ""))
2131 (set (mem:SI (reg:SI SP_REG))
2132 (match_operand:SI 2 "register_operand" ""))])]
bc02597b 2133 "TARGET_H8300S && !TARGET_NORMAL_MODE
68ee6df6
KH		 2134 && ((REGNO (operands[0]) == 0
2135 && REGNO (operands[1]) == 1
2136 && REGNO (operands[2]) == 2)
2137 || (REGNO (operands[0]) == 4
2138 && REGNO (operands[1]) == 5
2139 && REGNO (operands[2]) == 6))"
2140 "ldm.l\\t@er7+,%S0-%S2"
2141 [(set_attr "cc" "none")
2142 (set_attr "length" "4")])
2143
bc02597b
KH		 2144(define_insn "ldm_h8300s_3_normal"
2145 [(parallel
2146 [(set (reg:HI SP_REG)
2147 (plus:HI (reg:HI SP_REG) (const_int 12)))
2148 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2149 (match_operand:SI 0 "register_operand" ""))
2150 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2151 (match_operand:SI 1 "register_operand" ""))
2152 (set (mem:SI (reg:HI SP_REG))
2153 (match_operand:SI 2 "register_operand" ""))])]
2154 "TARGET_H8300S && TARGET_NORMAL_MODE
2155 && ((REGNO (operands[0]) == 0
2156 && REGNO (operands[1]) == 1
2157 && REGNO (operands[2]) == 2)
2158 || (REGNO (operands[0]) == 4
2159 && REGNO (operands[1]) == 5
2160 && REGNO (operands[2]) == 6))"
2161 "ldm.l\\t@er7+,%S0-%S2"
2162 [(set_attr "cc" "none")
2163 (set_attr "length" "4")])
2164
2165(define_expand "ldm_h8300s_3"
2166 [(use (match_operand:SI 0 "register_operand" ""))
2167 (use (match_operand:SI 1 "register_operand" ""))
2168 (use (match_operand:SI 2 "register_operand" ""))]
2169 "TARGET_H8300S
2170 && ((REGNO (operands[0]) == 0
2171 && REGNO (operands[1]) == 1
2172 && REGNO (operands[2]) == 2)
2173 || (REGNO (operands[0]) == 4
2174 && REGNO (operands[1]) == 5
2175 && REGNO (operands[2]) == 6))"
2176 "
2177{
2178 if (!TARGET_NORMAL_MODE)
2179 emit_insn (gen_ldm_h8300s_3_advanced (operands[0], operands[1],
2180 operands[2]));
2181 else
2182 emit_insn (gen_ldm_h8300s_3_normal (operands[0], operands[1],
2183 operands[2]));
2184 DONE;
2185}")
2186
2187(define_insn "ldm_h8300s_4_advanced"
68ee6df6
KH		 2188 [(parallel
2189 [(set (reg:SI SP_REG)
2190 (plus:SI (reg:SI SP_REG) (const_int 16)))
2191 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
2192 (match_operand:SI 0 "register_operand" ""))
2193 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2194 (match_operand:SI 1 "register_operand" ""))
2195 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2196 (match_operand:SI 2 "register_operand" ""))
2197 (set (mem:SI (reg:SI SP_REG))
2198 (match_operand:SI 3 "register_operand" ""))])]
bc02597b
KH		 2199 "TARGET_H8300S && !TARGET_NORMAL_MODE
2200 && REGNO (operands[0]) == 0
2201 && REGNO (operands[1]) == 1
2202 && REGNO (operands[2]) == 2
2203 && REGNO (operands[3]) == 3"
2204 "ldm.l\\t@er7+,%S0-%S3"
2205 [(set_attr "cc" "none")
2206 (set_attr "length" "4")])
2207
2208(define_insn "ldm_h8300s_4_normal"
2209 [(parallel
2210 [(set (reg:HI SP_REG)
2211 (plus:HI (reg:HI SP_REG) (const_int 16)))
2212 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
2213 (match_operand:SI 0 "register_operand" ""))
2214 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2215 (match_operand:SI 1 "register_operand" ""))
2216 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2217 (match_operand:SI 2 "register_operand" ""))
2218 (set (mem:SI (reg:HI SP_REG))
2219 (match_operand:SI 3 "register_operand" ""))])]
2220 "TARGET_H8300S && !TARGET_NORMAL_MODE
68ee6df6
KH		 2221 && REGNO (operands[0]) == 0
2222 && REGNO (operands[1]) == 1
2223 && REGNO (operands[2]) == 2
2224 && REGNO (operands[3]) == 3"
2225 "ldm.l\\t@er7+,%S0-%S3"
2226 [(set_attr "cc" "none")
2227 (set_attr "length" "4")])
2228
bc02597b
KH		 2229(define_expand "ldm_h8300s_4"
2230 [(use (match_operand:SI 0 "register_operand" ""))
2231 (use (match_operand:SI 1 "register_operand" ""))
2232 (use (match_operand:SI 2 "register_operand" ""))
2233 (use (match_operand:SI 3 "register_operand" ""))]
2234 "TARGET_H8300S && !TARGET_NORMAL_MODE
2235 && REGNO (operands[0]) == 0
2236 && REGNO (operands[1]) == 1
2237 && REGNO (operands[2]) == 2
2238 && REGNO (operands[3]) == 3"
2239 "
2240{
2241 if (!TARGET_NORMAL_MODE)
2242 emit_insn (gen_ldm_h8300s_4_advanced (operands[0], operands[1],
2243 operands[2], operands[3]));
2244 else
2245 emit_insn (gen_ldm_h8300s_4_normal (operands[0], operands[1],
2246 operands[2], operands[3]));
2247 DONE;
2248}")
2249
68ee6df6
KH		 2250(define_expand "return"
2251 [(return)]
2252 "h8300_can_use_return_insn_p ()"
2253 "")
2254
2255(define_insn "*return_1"
2256 [(return)]
2257 "reload_completed"
2258 "*
2259{
2260 if (h8300_current_function_interrupt_function_p ())
2261 return \"rte\";
2262 else
2263 return \"rts\";
2264}"
2265 [(set_attr "cc" "none")
2266 (set_attr "length" "2")])
2267
2268(define_expand "prologue"
2269 [(const_int 0)]
2270 ""
2271 "h8300_expand_prologue (); DONE;")
2272
2273(define_expand "epilogue"
2274 [(return)]
2275 ""
2276 "h8300_expand_epilogue ();")
2277
2278(define_insn "monitor_prologue"
2279 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2280 ""
2281 "*
2282{
2283 if (TARGET_H8300)
2284 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2285 else if (TARGET_H8300H)
2286 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2287 else if (TARGET_H8300S)
2288 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
87a902e4 2289 abort ();
68ee6df6
KH		 2290}"
2291 [(set_attr "length" "20")
2292 (set_attr "cc" "clobber")])
0a2a0a58
KH		 2293\f
2294;; ----------------------------------------------------------------------
b4d2cd97
DE		 2295;; EXTEND INSTRUCTIONS
2296;; ----------------------------------------------------------------------
f82eca4d 2297
6f41623f
KH		 2298(define_expand "zero_extendqihi2"
2299 [(set (match_operand:HI 0 "register_operand" "")
2300 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2301 ""
2302 "")
2303
f7e42925 2304(define_insn "*zero_extendqihi2_h8300"
b4d2cd97 2305 [(set (match_operand:HI 0 "register_operand" "=r,r")
bd93f126 2306 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
6f41623f 2307 "TARGET_H8300"
ec497122
JL		 2308 "@
2309 mov.b #0,%t0
f7e42925 2310 #"
7ba7767b 2311 [(set_attr "length" "2,10")
ec497122 2312 (set_attr "cc" "clobber,clobber")])
f82eca4d 2313
f7e42925 2314(define_insn "*zero_extendqihi2_h8300hs"
6f41623f
KH		 2315 [(set (match_operand:HI 0 "register_operand" "=r,r")
2316 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2317 "TARGET_H8300H || TARGET_H8300S"
2318 "@
2319 extu.w %T0
f7e42925 2320 #"
6f41623f
KH		 2321 [(set_attr "length" "2,10")
2322 (set_attr "cc" "set_znv,set_znv")])
2323
f7e42925
KH		 2324;; Split the zero extension of a general operand (actually a memory
2325;; operand) into a load of the operand and the actual zero extension
2326;; so that 1) the length will be accurate, and 2) the zero extensions
2327;; appearing at the end of basic blocks may be merged.
2328
2329(define_split
2330 [(set (match_operand:HI 0 "register_operand" "")
2331 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2332 "reload_completed"
2333 [(set (match_dup 2)
2334 (match_dup 1))
2335 (set (match_dup 0)
2336 (zero_extend:HI (match_dup 2)))]
2337 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2338
23cdb465
KH		 2339(define_expand "zero_extendqisi2"
2340 [(set (match_operand:SI 0 "register_operand" "")
2341 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2342 ""
2343 "")
2344
2345(define_insn "*zero_extendqisi2_h8300"
bd93f126
JL		 2346 [(set (match_operand:SI 0 "register_operand" "=r,r")
2347 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2348 "TARGET_H8300"
2349 "@
b054460b
KH		 2350 mov.b #0,%x0\;sub.w %e0,%e0
2351 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
5d750136 2352 [(set_attr "length" "4,8")
bd93f126
JL		 2353 (set_attr "cc" "clobber,clobber")])
2354
23cdb465
KH		 2355(define_insn "*zero_extendqisi2_h8300hs"
2356 [(set (match_operand:SI 0 "register_operand" "=r,r")
2357 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2358 "TARGET_H8300H || TARGET_H8300S"
093b05b6 2359 "#")
23cdb465
KH		 2360
2361(define_split
2362 [(set (match_operand:SI 0 "register_operand" "")
2363 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2364 "(TARGET_H8300H || TARGET_H8300S)
2365 && reg_overlap_mentioned_p (operands[0], operands[1])
cb713a8d 2366 && reload_completed"
23cdb465
KH		 2367 [(set (match_dup 2)
2368 (match_dup 1))
093b05b6
KH		 2369 (set (match_dup 3)
2370 (zero_extend:HI (match_dup 2)))
23cdb465 2371 (set (match_dup 0)
093b05b6
KH		 2372 (zero_extend:SI (match_dup 3)))]
2373 "operands[2] = gen_lowpart (QImode, operands[0]);
2374 operands[3] = gen_lowpart (HImode, operands[0]);")
23cdb465
KH		 2375
2376(define_split
2377 [(set (match_operand:SI 0 "register_operand" "")
2378 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2379 "(TARGET_H8300H || TARGET_H8300S)
2380 && !reg_overlap_mentioned_p (operands[0], operands[1])
cb713a8d 2381 && reload_completed"
23cdb465
KH		 2382 [(set (match_dup 0)
2383 (const_int 0))
2384 (set (strict_low_part (match_dup 2))
2385 (match_dup 1))]
2386 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2387
ec497122
JL		 2388(define_expand "zero_extendhisi2"
2389 [(set (match_operand:SI 0 "register_operand" "")
7b7de7c0 2390 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
ec497122 2391 ""
ec497122
JL		 2392 "")
2393
01d5caad 2394;; %e prints the high part of a CONST_INT, not the low part. Arggh.
6b00cbc7 2395(define_insn "*zero_extendhisi2_h8300"
01d5caad
JL		 2396 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2397 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
ec497122
JL		 2398 "TARGET_H8300"
2399 "@
2400 sub.w %e0,%e0
07e0fe3d
KH		 2401 mov.w %f1,%f0\;sub.w %e0,%e0
2402 mov.w %e1,%f0\;sub.w %e0,%e0"
6b00cbc7 2403 [(set_attr "length" "2,4,6")
01d5caad 2404 (set_attr "cc" "clobber,clobber,clobber")])
ec497122
JL		 2405
2406(define_insn ""
7b7de7c0
WC		 2407 [(set (match_operand:SI 0 "register_operand" "=r")
2408 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
a1616dd9 2409 "TARGET_H8300H || TARGET_H8300S"
7b7de7c0
WC		 2410 "extu.l %S0"
2411 [(set_attr "length" "2")
2412 (set_attr "cc" "set_znv")])
f82eca4d 2413
ec497122
JL		 2414(define_expand "extendqihi2"
2415 [(set (match_operand:HI 0 "register_operand" "")
7b7de7c0 2416 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
f82eca4d 2417 ""
ec497122
JL		 2418 "")
2419
2420(define_insn ""
2421 [(set (match_operand:HI 0 "register_operand" "=r,r")
bd93f126 2422 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
ec497122
JL		 2423 "TARGET_H8300"
2424 "@
2425 bld #7,%s0\;subx %t0,%t0
2426 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
8763a465 2427 [(set_attr "length" "4,8")
ec497122
JL		 2428 (set_attr "cc" "clobber,clobber")])
2429
2430(define_insn ""
7b7de7c0
WC		 2431 [(set (match_operand:HI 0 "register_operand" "=r")
2432 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
a1616dd9 2433 "TARGET_H8300H || TARGET_H8300S"
7b7de7c0
WC		 2434 "exts.w %T0"
2435 [(set_attr "length" "2")
2436 (set_attr "cc" "set_znv")])
f82eca4d 2437
f4c07fbf 2438(define_expand "extendqisi2"
da7959a8 2439 [(set (match_operand:SI 0 "register_operand" "")
f4c07fbf
KH		 2440 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2441 ""
2442 "")
2443
2444(define_insn "*extendqisi2_h8300"
2445 [(set (match_operand:SI 0 "register_operand" "")
bd93f126
JL		 2446 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2447 "TARGET_H8300"
2448 "@
2449 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
b054460b 2450 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
6b00cbc7 2451 [(set_attr "length" "8,12")
bd93f126
JL		 2452 (set_attr "cc" "clobber,clobber")])
2453
f4c07fbf
KH		 2454;; The following pattern is needed because without the pattern, the
2455;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2456;; shifts, one ashift and one ashiftrt.
2457
2458(define_insn_and_split "*extendqisi2_h8300hs"
2459 [(set (match_operand:SI 0 "register_operand" "=r")
2460 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2461 "(TARGET_H8300H || TARGET_H8300S)"
2462 "#"
2463 "&& reload_completed"
2464 [(set (match_dup 2)
2465 (sign_extend:HI (match_dup 1)))
2466 (set (match_dup 0)
2467 (sign_extend:SI (match_dup 2)))]
2468 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2469
b4d2cd97
DE		 2470(define_expand "extendhisi2"
2471 [(set (match_operand:SI 0 "register_operand" "")
7b7de7c0 2472 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
f82eca4d 2473 ""
b4d2cd97 2474 "")
f82eca4d 2475
6b00cbc7 2476(define_insn "*extendhisi2_h8300"
ec497122 2477 [(set (match_operand:SI 0 "register_operand" "=r,r")
bd93f126 2478 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
b4d2cd97 2479 "TARGET_H8300"
ec497122
JL		 2480 "@
2481 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2482 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
6b00cbc7 2483 [(set_attr "length" "6,10")
ec497122 2484 (set_attr "cc" "clobber,clobber")])
f82eca4d 2485
ec497122 2486(define_insn ""
7b7de7c0
WC		 2487 [(set (match_operand:SI 0 "register_operand" "=r")
2488 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
a1616dd9 2489 "TARGET_H8300H || TARGET_H8300S"
7b7de7c0
WC		 2490 "exts.l %S0"
2491 [(set_attr "length" "2")
2492 (set_attr "cc" "set_znv")])
269c14e1 2493\f
b4d2cd97
DE		 2494;; ----------------------------------------------------------------------
2495;; SHIFTS
2496;; ----------------------------------------------------------------------
2497;;
2498;; We make some attempt to provide real efficient shifting. One example is
2499;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2500;; reg and moving 0 into the former reg.
2501;;
2502;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2503;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2504;; give the optimizer more cracks at the code. However, we wish to do things
2505;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1898584f 2506;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
b4d2cd97
DE		 2507;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2508;; to detect cases it can optimize.
2509;;
2510;; For these and other fuzzy reasons, I've decided to go the less pretty but
2511;; easier "do it at insn emit time" route.
2512
2513;; QI BIT SHIFTS
2514
2515(define_expand "ashlqi3"
2516 [(set (match_operand:QI 0 "register_operand" "")
2517 (ashift:QI (match_operand:QI 1 "register_operand" "")
2518 (match_operand:QI 2 "nonmemory_operand" "")))]
f82eca4d 2519 ""
317d21e9 2520 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
f82eca4d 2521
b4d2cd97
DE		 2522(define_expand "ashrqi3"
2523 [(set (match_operand:QI 0 "register_operand" "")
2524 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2525 (match_operand:QI 2 "nonmemory_operand" "")))]
f82eca4d 2526 ""
317d21e9 2527 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
f82eca4d 2528
b4d2cd97
DE		 2529(define_expand "lshrqi3"
2530 [(set (match_operand:QI 0 "register_operand" "")
2531 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2532 (match_operand:QI 2 "nonmemory_operand" "")))]
f82eca4d 2533 ""
317d21e9 2534 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
f82eca4d 2535
dd4fd0a0 2536(define_insn ""
b4d2cd97 2537 [(set (match_operand:QI 0 "register_operand" "=r,r")
c127c127 2538 (match_operator:QI 3 "nshift_operator"
b4d2cd97 2539 [ (match_operand:QI 1 "register_operand" "0,0")
be1e06df 2540 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
b4d2cd97 2541 (clobber (match_scratch:QI 4 "=X,&r"))]
f82eca4d 2542 ""
1a275226 2543 "* return output_a_shift (operands);"
86855e8c
KH		 2544 [(set (attr "length")
2545 (symbol_ref "compute_a_shift_length (insn, operands)"))
45ca2106
KH		 2546 (set (attr "cc")
2547 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
f82eca4d 2548
b4d2cd97 2549;; HI BIT SHIFTS
f82eca4d 2550
b4d2cd97
DE		 2551(define_expand "ashlhi3"
2552 [(set (match_operand:HI 0 "register_operand" "")
2553 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2554 (match_operand:QI 2 "nonmemory_operand" "")))]
f82eca4d 2555 ""
317d21e9 2556 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
b4d2cd97
DE		 2557
2558(define_expand "lshrhi3"
2559 [(set (match_operand:HI 0 "register_operand" "")
bd93f126 2560 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
b4d2cd97
DE		 2561 (match_operand:QI 2 "nonmemory_operand" "")))]
2562 ""
317d21e9 2563 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
f82eca4d
SC		 2564
2565(define_expand "ashrhi3"
2566 [(set (match_operand:HI 0 "register_operand" "")
b4d2cd97
DE		 2567 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2568 (match_operand:QI 2 "nonmemory_operand" "")))]
f82eca4d 2569 ""
317d21e9 2570 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
f82eca4d 2571
dd4fd0a0 2572(define_insn ""
b4d2cd97 2573 [(set (match_operand:HI 0 "register_operand" "=r,r")
c127c127 2574 (match_operator:HI 3 "nshift_operator"
b4d2cd97 2575 [ (match_operand:HI 1 "register_operand" "0,0")
be1e06df 2576 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
b4d2cd97 2577 (clobber (match_scratch:QI 4 "=X,&r"))]
f82eca4d 2578 ""
1a275226 2579 "* return output_a_shift (operands);"
86855e8c
KH		 2580 [(set (attr "length")
2581 (symbol_ref "compute_a_shift_length (insn, operands)"))
45ca2106
KH		 2582 (set (attr "cc")
2583 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
f82eca4d 2584
b4d2cd97
DE		 2585;; SI BIT SHIFTS
2586
f82eca4d
SC		 2587(define_expand "ashlsi3"
2588 [(set (match_operand:SI 0 "register_operand" "")
7a27efc4
KH		 2589 (ashift:SI (match_operand:SI 1 "general_operand" "")
2590 (match_operand:QI 2 "nonmemory_operand" "")))]
f82eca4d 2591 ""
317d21e9 2592 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
f82eca4d
SC		 2593
2594(define_expand "lshrsi3"
2595 [(set (match_operand:SI 0 "register_operand" "")
7a27efc4
KH		 2596 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2597 (match_operand:QI 2 "nonmemory_operand" "")))]
f82eca4d 2598 ""
317d21e9 2599 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
f82eca4d
SC		 2600
2601(define_expand "ashrsi3"
2602 [(set (match_operand:SI 0 "register_operand" "")
7a27efc4
KH		 2603 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2604 (match_operand:QI 2 "nonmemory_operand" "")))]
f82eca4d 2605 ""
317d21e9 2606 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
f82eca4d 2607
dd4fd0a0 2608(define_insn ""
b4d2cd97 2609 [(set (match_operand:SI 0 "register_operand" "=r,r")
c127c127 2610 (match_operator:SI 3 "nshift_operator"
b4d2cd97 2611 [ (match_operand:SI 1 "register_operand" "0,0")
be1e06df 2612 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
b4d2cd97 2613 (clobber (match_scratch:QI 4 "=X,&r"))]
f82eca4d 2614 ""
1a275226 2615 "* return output_a_shift (operands);"
86855e8c
KH		 2616 [(set (attr "length")
2617 (symbol_ref "compute_a_shift_length (insn, operands)"))
45ca2106
KH		 2618 (set (attr "cc")
2619 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
cd9b5ca8
KH		 2620
2621;; Split a variable shift into a loop. If the register containing
2622;; the shift count dies, then we just use that register.
2623
2624(define_split
2625 [(parallel
2626 [(set (match_operand 0 "register_operand" "")
2627 (match_operator 2 "nshift_operator"
2628 [(match_dup 0)
2629 (match_operand:QI 1 "register_operand" "")]))
2630 (clobber (match_operand:QI 3 "register_operand" ""))])]
2631 "flow2_completed
2632 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2633 [(set (cc0)
2634 (match_dup 1))
2635 (set (pc)
2636 (if_then_else (le (cc0) (const_int 0))
2637 (label_ref (match_dup 5))
2638 (pc)))
2639 (match_dup 4)
2640 (parallel
2641 [(set (match_dup 0)
2642 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2643 (clobber (scratch:QI))])
2644 (set (match_dup 1)
2645 (plus:QI (match_dup 1) (const_int -1)))
2646 (set (cc0)
2647 (match_dup 1))
2648 (set (pc)
2649 (if_then_else (ne (cc0) (const_int 0))
2650 (label_ref (match_dup 4))
2651 (pc)))
2652 (match_dup 5)]
2653 "operands[4] = gen_label_rtx ();
2654 operands[5] = gen_label_rtx ();")
2655
2656(define_split
2657 [(parallel
2658 [(set (match_operand 0 "register_operand" "")
2659 (match_operator 2 "nshift_operator"
2660 [(match_dup 0)
2661 (match_operand:QI 1 "register_operand" "")]))
2662 (clobber (match_operand:QI 3 "register_operand" ""))])]
2663 "flow2_completed
2664 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2665 [(set (match_dup 3)
2666 (match_dup 1))
2667 (set (cc0)
2668 (match_dup 3))
2669 (set (pc)
2670 (if_then_else (le (cc0) (const_int 0))
2671 (label_ref (match_dup 5))
2672 (pc)))
2673 (match_dup 4)
2674 (parallel
2675 [(set (match_dup 0)
2676 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2677 (clobber (scratch:QI))])
2678 (set (match_dup 3)
2679 (plus:QI (match_dup 3) (const_int -1)))
2680 (set (cc0)
2681 (match_dup 3))
2682 (set (pc)
2683 (if_then_else (ne (cc0) (const_int 0))
2684 (label_ref (match_dup 4))
2685 (pc)))
2686 (match_dup 5)]
2687 "operands[4] = gen_label_rtx ();
2688 operands[5] = gen_label_rtx ();")
269c14e1 2689\f
edd71f0f
KH		 2690;; ----------------------------------------------------------------------
2691;; ROTATIONS
2692;; ----------------------------------------------------------------------
2693
2694(define_expand "rotlqi3"
2695 [(set (match_operand:QI 0 "register_operand" "")
2696 (rotate:QI (match_operand:QI 1 "register_operand" "")
2697 (match_operand:QI 2 "nonmemory_operand" "")))]
2698 ""
20c907b0 2699 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
edd71f0f
KH		 2700
2701(define_insn "*rotlqi3_1"
2702 [(set (match_operand:QI 0 "register_operand" "=r")
2703 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2704 (match_operand:QI 2 "immediate_operand" "")))]
2705 ""
caf7f21a
KH		 2706 "* return output_a_rotate (ROTATE, operands);"
2707 [(set (attr "length")
2708 (symbol_ref "compute_a_rotate_length (operands)"))
edd71f0f
KH		 2709 (set_attr "cc" "clobber")])
2710
2711(define_expand "rotlhi3"
2712 [(set (match_operand:HI 0 "register_operand" "")
2713 (rotate:HI (match_operand:HI 1 "register_operand" "")
2714 (match_operand:QI 2 "nonmemory_operand" "")))]
2715 ""
20c907b0 2716 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
edd71f0f
KH		 2717
2718(define_insn "*rotlhi3_1"
2719 [(set (match_operand:HI 0 "register_operand" "=r")
2720 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2721 (match_operand:QI 2 "immediate_operand" "")))]
2722 ""
caf7f21a
KH		 2723 "* return output_a_rotate (ROTATE, operands);"
2724 [(set (attr "length")
2725 (symbol_ref "compute_a_rotate_length (operands)"))
edd71f0f
KH		 2726 (set_attr "cc" "clobber")])
2727
2728(define_expand "rotlsi3"
2729 [(set (match_operand:SI 0 "register_operand" "")
2730 (rotate:SI (match_operand:SI 1 "register_operand" "")
2731 (match_operand:QI 2 "nonmemory_operand" "")))]
2732 "TARGET_H8300H || TARGET_H8300S"
20c907b0 2733 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
edd71f0f
KH		 2734
2735(define_insn "*rotlsi3_1"
2736 [(set (match_operand:SI 0 "register_operand" "=r")
2737 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2738 (match_operand:QI 2 "immediate_operand" "")))]
2739 "TARGET_H8300H || TARGET_H8300S"
caf7f21a
KH		 2740 "* return output_a_rotate (ROTATE, operands);"
2741 [(set (attr "length")
2742 (symbol_ref "compute_a_rotate_length (operands)"))
edd71f0f
KH		 2743 (set_attr "cc" "clobber")])
2744\f
b4d2cd97
DE		 2745;; -----------------------------------------------------------------
2746;; BIT FIELDS
2747;; -----------------------------------------------------------------
2748;; The H8/300 has given 1/8th of its opcode space to bitfield
269c14e1 2749;; instructions so let's use them as well as we can.
f82eca4d 2750
bd93f126
JL		 2751;; You'll never believe all these patterns perform one basic action --
2752;; load a bit from the source, optionally invert the bit, then store it
c127c127 2753;; in the destination (which is known to be zero).
bd93f126
JL		 2754;;
2755;; Combine obviously need some work to better identify this situation and
2756;; canonicalize the form better.
2757
c127c127 2758;;
bd93f126 2759;; Normal loads with a 16bit destination.
c127c127 2760;;
1d788fb6 2761
bd93f126 2762(define_insn ""
b4d2cd97 2763 [(set (match_operand:HI 0 "register_operand" "=&r")
bd93f126 2764 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
b4d2cd97 2765 (const_int 1)
bf63e3a2 2766 (match_operand:HI 2 "immediate_operand" "n")))]
1d788fb6 2767 "TARGET_H8300"
ec497122
JL		 2768 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2769 [(set_attr "cc" "clobber")
2770 (set_attr "length" "6")])
f82eca4d 2771
c127c127 2772;;
bd93f126 2773;; Inverted loads with a 16bit destination.
c127c127 2774;;
bd93f126
JL		 2775
2776(define_insn ""
2777 [(set (match_operand:HI 0 "register_operand" "=&r")
2778 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
82be00ee 2779 (match_operand:HI 3 "const_int_operand" "n"))
b4d2cd97 2780 (const_int 1)
bd93f126 2781 (match_operand:HI 2 "const_int_operand" "n")))]
1d788fb6
KH		 2782 "TARGET_H8300
2783 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
bd93f126
JL		 2784 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2785 [(set_attr "cc" "clobber")
2786 (set_attr "length" "8")])
b4d2cd97 2787
c127c127 2788;;
bd93f126 2789;; Normal loads with a 32bit destination.
c127c127 2790;;
8ed43adf 2791
fc182093 2792(define_insn "*extzv_1_r_h8300"
bd93f126
JL		 2793 [(set (match_operand:SI 0 "register_operand" "=&r")
2794 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2795 (const_int 1)
8ed43adf
KH		 2796 (match_operand 2 "const_int_operand" "n")))]
2797 "TARGET_H8300
2798 && INTVAL (operands[2]) < 16"
871f73e3 2799 "* return output_simode_bld (0, operands);"
ec497122 2800 [(set_attr "cc" "clobber")
fc182093 2801 (set_attr "length" "8")])
b4d2cd97 2802
fc182093 2803(define_insn "*extzv_1_r_h8300hs"
0eb933a0
KH		 2804 [(set (match_operand:SI 0 "register_operand" "=r,r")
2805 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
8ed43adf 2806 (const_int 1)
0eb933a0 2807 (match_operand 2 "const_int_operand" "n,n")))]
8ed43adf
KH		 2808 "(TARGET_H8300H || TARGET_H8300S)
2809 && INTVAL (operands[2]) < 16"
871f73e3 2810 "* return output_simode_bld (0, operands);"
802a9907 2811 [(set_attr "cc" "set_znv,set_znv")
0eb933a0 2812 (set_attr "length" "8,6")])
b4d2cd97 2813
c127c127 2814;;
bd93f126 2815;; Inverted loads with a 32bit destination.
c127c127 2816;;
b4d2cd97 2817
fc182093 2818(define_insn "*extzv_1_r_inv_h8300"
bd93f126 2819 [(set (match_operand:SI 0 "register_operand" "=&r")
8ed43adf
KH		 2820 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2821 (match_operand:HI 3 "const_int_operand" "n"))
2822 (const_int 1)
2823 (match_operand 2 "const_int_operand" "n")))]
2824 "TARGET_H8300
2825 && INTVAL (operands[2]) < 16
2826 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
871f73e3 2827 "* return output_simode_bld (1, operands);"
bd93f126 2828 [(set_attr "cc" "clobber")
fc182093 2829 (set_attr "length" "8")])
b4d2cd97 2830
fc182093 2831(define_insn "*extzv_1_r_inv_h8300hs"
0eb933a0
KH		 2832 [(set (match_operand:SI 0 "register_operand" "=r,r")
2833 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2834 (match_operand 3 "const_int_operand" "n,n"))
bd93f126 2835 (const_int 1)
0eb933a0 2836 (match_operand 2 "const_int_operand" "n,n")))]
8ed43adf
KH		 2837 "(TARGET_H8300H || TARGET_H8300S)
2838 && INTVAL (operands[2]) < 16
2839 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
871f73e3 2840 "* return output_simode_bld (1, operands);"
802a9907 2841 [(set_attr "cc" "set_znv,set_znv")
0eb933a0 2842 (set_attr "length" "8,6")])
b4d2cd97
DE		 2843
2844(define_expand "insv"
bd93f126
JL		 2845 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2846 (match_operand:HI 1 "general_operand" "")
2847 (match_operand:HI 2 "general_operand" ""))
2848 (match_operand:HI 3 "general_operand" ""))]
b4d2cd97
DE		 2849 "TARGET_H8300"
2850 "
f82eca4d 2851{
43a88a8c 2852 /* We only have single bit bit-field instructions. */
b4d2cd97
DE		 2853 if (INTVAL (operands[1]) != 1)
2854 FAIL;
2855
bd93f126
JL		 2856 /* For now, we don't allow memory operands. */
2857 if (GET_CODE (operands[0]) == MEM
2858 || GET_CODE (operands[3]) == MEM)
b4d2cd97 2859 FAIL;
b4d2cd97
DE		 2860}")
2861
bd93f126
JL		 2862(define_insn ""
2863 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2864 (const_int 1)
bf63e3a2 2865 (match_operand:HI 1 "immediate_operand" "n"))
bd93f126
JL		 2866 (match_operand:HI 2 "register_operand" "r"))]
2867 ""
2868 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2869 [(set_attr "cc" "clobber")
2870 (set_attr "length" "4")])
b4d2cd97
DE		 2871
2872(define_expand "extzv"
c127c127 2873 [(set (match_operand:HI 0 "register_operand" "")
bd93f126
JL		 2874 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2875 (match_operand:HI 2 "general_operand" "")
2876 (match_operand:HI 3 "general_operand" "")))]
b4d2cd97
DE		 2877 "TARGET_H8300"
2878 "
2879{
43a88a8c 2880 /* We only have single bit bit-field instructions. */
b4d2cd97
DE		 2881 if (INTVAL (operands[2]) != 1)
2882 FAIL;
2883
bd93f126
JL		 2884 /* For now, we don't allow memory operands. */
2885 if (GET_CODE (operands[1]) == MEM)
2886 FAIL;
b4d2cd97 2887}")
b4d2cd97 2888
bd93f126 2889;; BAND, BOR, and BXOR patterns
b4d2cd97 2890
bd93f126
JL		 2891(define_insn ""
2892 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2893 (match_operator:HI 4 "bit_operator"
2894 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2895 (const_int 1)
bf63e3a2 2896 (match_operand:HI 2 "immediate_operand" "n"))
bd93f126
JL		 2897 (match_operand:HI 3 "bit_operand" "0")]))]
2898 ""
46dfb7aa 2899 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
bd93f126 2900 [(set_attr "cc" "clobber")
caf7f21a 2901 (set_attr "length" "6")])
f82eca4d 2902
bd93f126
JL		 2903(define_insn ""
2904 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2905 (match_operator:HI 5 "bit_operator"
2906 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2907 (const_int 1)
bf63e3a2 2908 (match_operand:HI 2 "immediate_operand" "n"))
bd93f126
JL		 2909 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2910 (const_int 1)
bf63e3a2 2911 (match_operand:HI 4 "immediate_operand" "n"))]))]
bd93f126 2912 ""
46dfb7aa 2913 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
bd93f126 2914 [(set_attr "cc" "clobber")
caf7f21a 2915 (set_attr "length" "6")])
11a802bf
KH		 2916\f
2917;; -----------------------------------------------------------------
2918;; COMBINE PATTERNS
2919;; -----------------------------------------------------------------
2920
d0940a55
KH		 2921;; insv:SI
2922
2923(define_insn "*insv_si_1_n"
2924 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2925 (const_int 1)
2926 (match_operand:SI 1 "const_int_operand" "n"))
2927 (match_operand:SI 2 "register_operand" "r"))]
2928 "(TARGET_H8300H || TARGET_H8300S)
2929 && INTVAL (operands[1]) < 16"
2930 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2931 [(set_attr "cc" "clobber")
2932 (set_attr "length" "4")])
2933
2934(define_insn "*insv_si_1_n_lshiftrt"
2935 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2936 (const_int 1)
2937 (match_operand:SI 1 "const_int_operand" "n"))
2938 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2939 (match_operand:SI 3 "const_int_operand" "n")))]
2940 "(TARGET_H8300H || TARGET_H8300S)
86a36a0e
KH		 2941 && INTVAL (operands[1]) < 16
2942 && INTVAL (operands[3]) < 16"
d0940a55
KH		 2943 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2944 [(set_attr "cc" "clobber")
2945 (set_attr "length" "4")])
2946
5c1c25f0
KH		 2947(define_insn "*insv_si_1_n_lshiftrt_16"
2948 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2949 (const_int 1)
2950 (match_operand:SI 1 "const_int_operand" "n"))
2951 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2952 (const_int 16)))]
2953 "(TARGET_H8300H || TARGET_H8300S)
2954 && INTVAL (operands[1]) < 16"
2955 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2956 [(set_attr "cc" "clobber")
2957 (set_attr "length" "6")])
2958
d4048ff6
KH		 2959(define_insn "*insv_si_8_8"
2960 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2961 (const_int 8)
2962 (const_int 8))
2963 (match_operand:SI 1 "register_operand" "r"))]
2964 "TARGET_H8300H || TARGET_H8300S"
2965 "mov.b\\t%w1,%x0"
2966 [(set_attr "cc" "clobber")
2967 (set_attr "length" "2")])
2968
2969(define_insn "*insv_si_8_8_lshiftrt_8"
2970 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2971 (const_int 8)
2972 (const_int 8))
2973 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2974 (const_int 8)))]
2975 "TARGET_H8300H || TARGET_H8300S"
2976 "mov.b\\t%x1,%x0"
2977 [(set_attr "cc" "clobber")
2978 (set_attr "length" "2")])
2979
dff0ea43
KH		 2980;; extzv:SI
2981
6bd6fd35 2982(define_insn "*extzv_8_8"
0d9bf032
KH		 2983 [(set (match_operand:SI 0 "register_operand" "=r,r")
2984 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
6bd6fd35
KH		 2985 (const_int 8)
2986 (const_int 8)))]
2987 "TARGET_H8300H || TARGET_H8300S"
0d9bf032
KH		 2988 "@
2989 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2990 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
a8f0e848
KH		 2991 [(set_attr "cc" "set_znv,clobber")
2992 (set_attr "length" "6,4")])
6bd6fd35
KH		 2993
2994(define_insn "*extzv_8_16"
2995 [(set (match_operand:SI 0 "register_operand" "=r")
2996 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2997 (const_int 8)
2998 (const_int 16)))]
2999 "TARGET_H8300H || TARGET_H8300S"
3000 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3001 [(set_attr "cc" "set_znv")
3002 (set_attr "length" "6")])
3003
9571a6b9
KH		 3004(define_insn "*extzv_16_8"
3005 [(set (match_operand:SI 0 "register_operand" "=r")
3006 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3007 (const_int 16)
3008 (const_int 8)))
3009 (clobber (match_scratch:SI 2 "=&r"))]
3010 "TARGET_H8300H"
3011 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3012 [(set_attr "length" "8")
3013 (set_attr "cc" "set_znv")])
3014
dff0ea43
KH		 3015;; Extract the exponent of a float.
3016
3017(define_insn_and_split "*extzv_8_23"
3018 [(set (match_operand:SI 0 "register_operand" "=r")
3019 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3020 (const_int 8)
3021 (const_int 23)))]
3022 "(TARGET_H8300H || TARGET_H8300S)"
3023 "#"
3024 "&& reload_completed"
3025 [(parallel [(set (match_dup 0)
3026 (ashift:SI (match_dup 0)
3027 (const_int 1)))
3028 (clobber (scratch:QI))])
3029 (parallel [(set (match_dup 0)
3030 (lshiftrt:SI (match_dup 0)
3031 (const_int 24)))
3032 (clobber (scratch:QI))])]
3033 "")
3034
efbd757f
KH		 3035;; and:SI
3036
3037;; ((SImode) HImode) << 15
3038
3039(define_insn_and_split "*twoshifts_l16_r1"
3040 [(set (match_operand:SI 0 "register_operand" "=r")
3041 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3042 (const_int 15))
3043 (const_int 2147450880)))]
3044 "(TARGET_H8300H || TARGET_H8300S)"
3045 "#"
3046 "&& reload_completed"
3047 [(parallel [(set (match_dup 0)
3048 (ashift:SI (match_dup 0)
3049 (const_int 16)))
3050 (clobber (scratch:QI))])
3051 (parallel [(set (match_dup 0)
3052 (lshiftrt:SI (match_dup 0)
3053 (const_int 1)))
3054 (clobber (scratch:QI))])]
3055 "")
3056
dff23a65
KH		 3057;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3058
3059(define_insn_and_split "*andsi3_ashift_n_lower"
3060 [(set (match_operand:SI 0 "register_operand" "=r,r")
3061 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3062 (match_operand:QI 2 "const_int_operand" "S,n"))
3063 (match_operand:SI 3 "const_int_operand" "n,n")))
3064 (clobber (match_scratch:QI 4 "=X,&r"))]
3065 "(TARGET_H8300H || TARGET_H8300S)
3066 && INTVAL (operands[2]) <= 15
3067 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3068 "#"
3069 "&& reload_completed"
3070 [(parallel [(set (match_dup 5)
3071 (ashift:HI (match_dup 5)
3072 (match_dup 2)))
3073 (clobber (match_dup 4))])
3074 (set (match_dup 0)
3075 (zero_extend:SI (match_dup 5)))]
3076 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3077
98dc53e3
KH		 3078;; Accept (A >> 30) & 2 and the like.
3079
3080(define_insn "*andsi3_lshiftrt_n_sb"
3081 [(set (match_operand:SI 0 "register_operand" "=r")
3082 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3083 (match_operand:SI 2 "const_int_operand" "n"))
3084 (match_operand:SI 3 "single_one_operand" "n")))]
3085 "(TARGET_H8300H || TARGET_H8300S)
3086 && exact_log2 (INTVAL (operands[3])) < 16
3087 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3088 "*
3089{
3090 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3091 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
3092}"
3093 [(set_attr "length" "8")
3094 (set_attr "cc" "clobber")])
3095
4d77fda2
KH		 3096(define_insn_and_split "*andsi3_lshiftrt_9_sb"
3097 [(set (match_operand:SI 0 "register_operand" "=r")
3098 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3099 (const_int 9))
3100 (const_int 4194304)))]
3101 "(TARGET_H8300H || TARGET_H8300S)"
3102 "#"
3103 "&& reload_completed"
3104 [(set (match_dup 0)
3105 (and:SI (lshiftrt:SI (match_dup 0)
3106 (const_int 25))
3107 (const_int 64)))
3108 (parallel [(set (match_dup 0)
3109 (ashift:SI (match_dup 0)
3110 (const_int 16)))
3111 (clobber (scratch:QI))])]
3112 "")
3113
3cc3e1cd
KH		 3114;; plus:SI
3115
867504e6
KH		 3116(define_insn "*addsi3_upper"
3117 [(set (match_operand:SI 0 "register_operand" "=r")
3118 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3119 (const_int 65536))
3120 (match_operand:SI 2 "register_operand" "0")))]
3121 "TARGET_H8300H || TARGET_H8300S"
3122 "add.w\\t%f1,%e0"
3123 [(set_attr "length" "2")
3124 (set_attr "cc" "clobber")])
3125
3cc3e1cd
KH		 3126(define_insn "*addsi3_lshiftrt_16_zexthi"
3127 [(set (match_operand:SI 0 "register_operand" "=r")
3128 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3129 (const_int 16))
3130 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3131 "TARGET_H8300H || TARGET_H8300S"
a35abc3c 3132 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3cc3e1cd
KH		 3133 [(set_attr "cc" "clobber")
3134 (set_attr "length" "6")])
3135
12f76820
KH		 3136(define_insn_and_split "*addsi3_and_r_1"
3137 [(set (match_operand:SI 0 "register_operand" "=r")
3138 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3139 (const_int 1))
3140 (match_operand:SI 2 "register_operand" "0")))]
3141 "(TARGET_H8300H || TARGET_H8300S)"
3142 "#"
3143 "&& reload_completed"
3144 [(set (cc0)
3145 (zero_extract:SI (match_dup 1)
3146 (const_int 1)
3147 (const_int 0)))
3148 (set (pc)
3149 (if_then_else (eq (cc0)
3150 (const_int 0))
3151 (label_ref (match_dup 3))
3152 (pc)))
3153 (set (match_dup 2)
3154 (plus:SI (match_dup 2)
3155 (const_int 1)))
3156 (match_dup 3)]
3157 "operands[3] = gen_label_rtx ();")
3158
3159(define_insn_and_split "*addsi3_and_not_r_1"
3160 [(set (match_operand:SI 0 "register_operand" "=r")
3161 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3162 (const_int 1))
3163 (match_operand:SI 2 "register_operand" "0")))]
3164 "(TARGET_H8300H || TARGET_H8300S)"
3165 "#"
3166 "&& reload_completed"
3167 [(set (cc0)
3168 (zero_extract:SI (match_dup 1)
3169 (const_int 1)
3170 (const_int 0)))
3171 (set (pc)
3172 (if_then_else (ne (cc0)
3173 (const_int 0))
3174 (label_ref (match_dup 3))
3175 (pc)))
3176 (set (match_dup 2)
3177 (plus:SI (match_dup 2)
3178 (const_int 1)))
3179 (match_dup 3)]
3180 "operands[3] = gen_label_rtx ();")
3181
b059c02a 3182;; [ix]or:HI
fbcb02cd 3183
b059c02a 3184(define_insn "*ixorhi3_zext"
11a802bf 3185 [(set (match_operand:HI 0 "register_operand" "=r")
b059c02a
KH		 3186 (match_operator:HI 1 "iorxor_operator"
3187 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3188 (match_operand:HI 3 "register_operand" "0")]))]
3189 ""
3190 "%c1.b\\t%X2,%s0"
3191 [(set_attr "cc" "clobber")
3192 (set_attr "length" "2")])
3193
3194;; [ix]or:SI
3195
3196(define_insn "*ixorsi3_zext_qi"
3197 [(set (match_operand:SI 0 "register_operand" "=r")
3198 (match_operator:SI 1 "iorxor_operator"
3199 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3200 (match_operand:SI 3 "register_operand" "0")]))]
3201 ""
3202 "%c1.b\\t%X2,%w0"
3203 [(set_attr "cc" "clobber")
3204 (set_attr "length" "2")])
3205
3206(define_insn "*ixorsi3_zext_hi"
3207 [(set (match_operand:SI 0 "register_operand" "=r")
3208 (match_operator:SI 1 "iorxor_operator"
3209 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3210 (match_operand:SI 3 "register_operand" "0")]))]
426ace7f 3211 "TARGET_H8300H || TARGET_H8300S"
b059c02a 3212 "%c1.w\\t%T2,%f0"
11a802bf
KH		 3213 [(set_attr "cc" "clobber")
3214 (set_attr "length" "2")])
3215
8dfb356f
KH		 3216(define_insn "*ixorsi3_ashift_16"
3217 [(set (match_operand:SI 0 "register_operand" "=r")
3218 (match_operator:SI 1 "iorxor_operator"
3219 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3220 (const_int 16))
3221 (match_operand:SI 3 "register_operand" "0")]))]
3222 "TARGET_H8300H || TARGET_H8300S"
3223 "%c1.w\\t%f2,%e0"
3224 [(set_attr "cc" "clobber")
3225 (set_attr "length" "2")])
3226
3227(define_insn "*ixorsi3_lshiftrt_16"
3228 [(set (match_operand:SI 0 "register_operand" "=r")
3229 (match_operator:SI 1 "iorxor_operator"
3230 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3231 (const_int 16))
3232 (match_operand:SI 3 "register_operand" "0")]))]
3233 "TARGET_H8300H || TARGET_H8300S"
3234 "%c1.w\\t%e2,%f0"
3235 [(set_attr "cc" "clobber")
3236 (set_attr "length" "2")])
3237
b059c02a
KH		 3238;; ior:HI
3239
fbcb02cd
KH		 3240(define_insn "*iorhi3_ashift_8"
3241 [(set (match_operand:HI 0 "register_operand" "=r")
3242 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3243 (const_int 8))
3244 (match_operand:HI 2 "register_operand" "0")))]
3245 ""
3246 "or.b\\t%s1,%t0"
3247 [(set_attr "cc" "clobber")
3248 (set_attr "length" "2")])
3249
3250(define_insn "*iorhi3_lshiftrt_8"
3251 [(set (match_operand:HI 0 "register_operand" "=r")
3252 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3253 (const_int 8))
3254 (match_operand:HI 2 "register_operand" "0")))]
3255 ""
e8e8c1e5 3256 "or.b\\t%t1,%s0"
fbcb02cd
KH		 3257 [(set_attr "cc" "clobber")
3258 (set_attr "length" "2")])
3259
3260(define_insn "*iorhi3_two_qi"
3261 [(set (match_operand:HI 0 "register_operand" "=r")
3262 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3263 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3264 (const_int 8))))]
bf16e745 3265 ""
fbcb02cd
KH		 3266 "mov.b\\t%s2,%t0"
3267 [(set_attr "cc" "clobber")
3268 (set_attr "length" "2")])
3269
9b98dc74
KH		 3270(define_insn "*iorhi3_two_qi_mem"
3271 [(set (match_operand:HI 0 "register_operand" "=&r")
3272 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3273 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3274 (const_int 8))))]
3275 ""
3276 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3277 [(set_attr "cc" "clobber")
3278 (set_attr "length" "16")])
3279
3280(define_split
3281 [(set (match_operand:HI 0 "register_operand" "")
3282 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3283 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3284 (const_int 8))))]
3285 "(TARGET_H8300H || TARGET_H8300S)
3286 && reload_completed
3287 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3288 [(set (match_dup 0)
3289 (match_dup 3))]
3290 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3291
fbcb02cd
KH		 3292;; ior:SI
3293
1b9f0361
KH		 3294(define_insn "*iorsi3_two_hi"
3295 [(set (match_operand:SI 0 "register_operand" "=r")
3296 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3297 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3298 (const_int 16))))]
3299 "TARGET_H8300H || TARGET_H8300S"
3300 "mov.w\\t%f2,%e0"
3301 [(set_attr "cc" "clobber")
3302 (set_attr "length" "2")])
3303
1e788887
KH		 3304(define_insn_and_split "*iorsi3_two_qi_zext"
3305 [(set (match_operand:SI 0 "register_operand" "=&r")
3306 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3307
3308 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3309 (const_int 8))
3310 (const_int 65280))))]
3311 "(TARGET_H8300H || TARGET_H8300S)"
3312 "#"
3313 "&& reload_completed"
3314 [(set (match_dup 3)
3315 (ior:HI (zero_extend:HI (match_dup 1))
3316 (ashift:HI (subreg:HI (match_dup 2) 0)
3317 (const_int 8))))
3318 (set (match_dup 0)
3319 (zero_extend:SI (match_dup 3)))]
3320 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3321
c5979bc6
KH		 3322(define_insn "*iorsi3_e2f"
3323 [(set (match_operand:SI 0 "register_operand" "=r")
3324 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3325 (const_int -65536))
3326 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3327 (const_int 16))))]
3328 "TARGET_H8300H || TARGET_H8300S"
3329 "mov.w\\t%e2,%f0"
3330 [(set_attr "length" "2")
3331 (set_attr "cc" "clobber")])
3332
be9d08c2
KH		 3333(define_insn_and_split "*iorsi3_two_qi_sext"
3334 [(set (match_operand:SI 0 "register_operand" "=r")
3335 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3336 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3337 (const_int 8))))]
3338 "(TARGET_H8300H || TARGET_H8300S)"
3339 "#"
3340 "&& reload_completed"
3341 [(set (match_dup 3)
3342 (ior:HI (zero_extend:HI (match_dup 1))
3343 (ashift:HI (match_dup 4)
3344 (const_int 8))))
3345 (set (match_dup 0)
3346 (sign_extend:SI (match_dup 3)))]
3347 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3348 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3349
2dd5df7c
KH		 3350(define_insn "*iorsi3_w"
3351 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3352 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3353 (const_int -256))
3354 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3355 "TARGET_H8300H || TARGET_H8300S"
3356 "mov.b\\t%X2,%w0"
3357 [(set_attr "length" "2,8")
3358 (set_attr "cc" "clobber,clobber")])
3359
1f450138
KH		 3360(define_insn "*iorsi3_ashift_31"
3361 [(set (match_operand:SI 0 "register_operand" "=&r")
3362 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3363 (const_int 31))
3364 (match_operand:SI 2 "register_operand" "0")))]
3365 "TARGET_H8300H || TARGET_H8300S"
3366 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3367 [(set_attr "length" "6")
3368 (set_attr "cc" "set_znv")])
3369
39ecf301
KH		 3370(define_insn "*iorsi3_and_ashift"
3371 [(set (match_operand:SI 0 "register_operand" "=r")
3372 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3373 (match_operand:SI 2 "const_int_operand" "n"))
3374 (match_operand:SI 3 "single_one_operand" "n"))
3375 (match_operand:SI 4 "register_operand" "0")))]
3376 "(TARGET_H8300H || TARGET_H8300S)
3377 && (INTVAL (operands[3]) & ~0xffff) == 0"
3378 "*
3379{
3380 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3381 - INTVAL (operands[2]));
3382 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3383 operands[2] = srcpos;
3384 operands[3] = dstpos;
3385 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3386}"
3387 [(set_attr "length" "6")
3388 (set_attr "cc" "clobber")])
3389
3390(define_insn "*iorsi3_and_lshiftrt"
3391 [(set (match_operand:SI 0 "register_operand" "=r")
3392 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3393 (match_operand:SI 2 "const_int_operand" "n"))
3394 (match_operand:SI 3 "single_one_operand" "n"))
3395 (match_operand:SI 4 "register_operand" "0")))]
3396 "(TARGET_H8300H || TARGET_H8300S)
3397 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3398 "*
3399{
3400 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3401 + INTVAL (operands[2]));
3402 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3403 operands[2] = srcpos;
3404 operands[3] = dstpos;
3405 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3406}"
3407 [(set_attr "length" "6")
3408 (set_attr "cc" "clobber")])
3409
3410(define_insn "*iorsi3_zero_extract"
3411 [(set (match_operand:SI 0 "register_operand" "=r")
3412 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3413 (const_int 1)
3414 (match_operand:SI 2 "const_int_operand" "n"))
3415 (match_operand:SI 3 "register_operand" "0")))]
3416 "(TARGET_H8300H || TARGET_H8300S)
3417 && INTVAL (operands[2]) < 16"
3418 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3419 [(set_attr "length" "6")
3420 (set_attr "cc" "clobber")])
3421
98dc53e3
KH		 3422(define_insn "*iorsi3_and_lshiftrt_n_sb"
3423 [(set (match_operand:SI 0 "register_operand" "=r")
3424 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3425 (const_int 30))
3426 (const_int 2))
3427 (match_operand:SI 2 "register_operand" "0")))]
3428 "(TARGET_H8300H || TARGET_H8300S)"
3429 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3430 [(set_attr "length" "8")
3431 (set_attr "cc" "clobber")])
4d77fda2
KH		 3432
3433(define_insn "*iorsi3_and_lshiftrt_9_sb"
3434 [(set (match_operand:SI 0 "register_operand" "=r")
3435 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3436 (const_int 9))
3437 (const_int 4194304))
3438 (match_operand:SI 2 "register_operand" "0")))
3439 (clobber (match_scratch:HI 3 "=&r"))]
3440 "(TARGET_H8300H || TARGET_H8300S)"
3441 "*
3442{
3443 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3444 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3445 else
3446 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3447}"
3448 [(set_attr "length" "10")
3449 (set_attr "cc" "clobber")])
98dc53e3 3450
867504e6
KH		 3451;; Used to OR the exponent of a float.
3452
3453(define_insn "*iorsi3_shift"
3454 [(set (match_operand:SI 0 "register_operand" "=r")
3455 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3456 (const_int 23))
3457 (match_operand:SI 2 "register_operand" "0")))
3458 (clobber (match_scratch:SI 3 "=&r"))]
3459 "TARGET_H8300H || TARGET_H8300S"
3460 "#")
3461
3462(define_split
3463 [(parallel
3464 [(set (match_operand:SI 0 "register_operand" "")
3465 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3466 (const_int 23))
3467 (match_dup 0)))
3468 (clobber (match_operand:SI 2 "register_operand" ""))])]
3469 "(TARGET_H8300H || TARGET_H8300S)
3470 && flow2_completed
3471 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3472 && REGNO (operands[0]) != REGNO (operands[1])"
3473 [(parallel [(set (match_dup 3)
3474 (ashift:HI (match_dup 3)
3475 (const_int 7)))
3476 (clobber (scratch:QI))])
3477 (set (match_dup 0)
3478 (ior:SI (ashift:SI (match_dup 1)
3479 (const_int 16))
3480 (match_dup 0)))]
3481 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3482
3483(define_split
3484 [(parallel
3485 [(set (match_operand:SI 0 "register_operand" "")
3486 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3487 (const_int 23))
3488 (match_dup 0)))
3489 (clobber (match_operand:SI 2 "register_operand" ""))])]
3490 "(TARGET_H8300H || TARGET_H8300S)
3491 && flow2_completed
3492 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3493 && REGNO (operands[0]) != REGNO (operands[1]))"
3494 [(set (match_dup 2)
3495 (match_dup 1))
3496 (parallel [(set (match_dup 3)
3497 (ashift:HI (match_dup 3)
3498 (const_int 7)))
3499 (clobber (scratch:QI))])
3500 (set (match_dup 0)
3501 (ior:SI (ashift:SI (match_dup 2)
3502 (const_int 16))
3503 (match_dup 0)))]
3504 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3505
60f469fa
KH		 3506(define_insn "*iorsi2_and_1_lshiftrt_1"
3507 [(set (match_operand:SI 0 "register_operand" "=r")
3508 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3509 (const_int 1))
3510 (lshiftrt:SI (match_dup 1)
3511 (const_int 1))))]
3512 "TARGET_H8300H || TARGET_H8300S"
3513 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3514 [(set_attr "length" "6")
3515 (set_attr "cc" "clobber")])
3516
9b98dc74
KH		 3517(define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3518 [(set (match_operand:SI 0 "register_operand" "=r")
3519 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3520 (const_int 16))
3521 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3522 (const_int 24))))]
3523 "(TARGET_H8300H || TARGET_H8300S)"
3524 "#"
3525 "&& reload_completed"
3526 [(set (match_dup 3)
3527 (ior:HI (ashift:HI (match_dup 4)
3528 (const_int 8))
3529 (match_dup 3)))
3530 (parallel [(set (match_dup 0)
3531 (ashift:SI (match_dup 0)
3532 (const_int 16)))
3533 (clobber (scratch:QI))])]
3534 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3535 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3536
3537(define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3538 [(set (match_operand:SI 0 "register_operand" "=&r")
3539 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3540 (const_int 16))
3541 (const_int 16711680))
3542 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3543 (const_int 24))))]
3544 "(TARGET_H8300H || TARGET_H8300S)"
3545 "#"
3546 "&& reload_completed"
3547 [(set (match_dup 3)
3548 (ior:HI (zero_extend:HI (match_dup 1))
3549 (ashift:HI (subreg:HI (match_dup 2) 0)
3550 (const_int 8))))
3551 (parallel [(set (match_dup 0)
3552 (ashift:SI (match_dup 0)
3553 (const_int 16)))
3554 (clobber (scratch:QI))])]
3555 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3556
867504e6
KH		 3557;; Used to add the exponent of a float.
3558
3559(define_insn "*addsi3_shift"
3560 [(set (match_operand:SI 0 "register_operand" "=r")
3561 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3562 (const_int 8388608))
3563 (match_operand:SI 2 "register_operand" "0")))
3564 (clobber (match_scratch:SI 3 "=&r"))]
3565 "TARGET_H8300H || TARGET_H8300S"
3566 "#")
3567
3568(define_split
3569 [(parallel
3570 [(set (match_operand:SI 0 "register_operand" "")
3571 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3572 (const_int 8388608))
3573 (match_dup 0)))
3574 (clobber (match_operand:SI 2 "register_operand" ""))])]
3575 "(TARGET_H8300H || TARGET_H8300S)
3576 && flow2_completed
3577 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3578 && REGNO (operands[0]) != REGNO (operands[1])"
3579 [(parallel [(set (match_dup 3)
3580 (ashift:HI (match_dup 3)
3581 (const_int 7)))
3582 (clobber (scratch:QI))])
3583 (set (match_dup 0)
3584 (plus:SI (mult:SI (match_dup 1)
3585 (const_int 65536))
3586 (match_dup 0)))]
3587 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3588
3589(define_split
3590 [(parallel
3591 [(set (match_operand:SI 0 "register_operand" "")
3592 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3593 (const_int 8388608))
3594 (match_dup 0)))
3595 (clobber (match_operand:SI 2 "register_operand" ""))])]
3596 "(TARGET_H8300H || TARGET_H8300S)
3597 && flow2_completed
3598 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3599 && REGNO (operands[0]) != REGNO (operands[1]))"
3600 [(set (match_dup 2)
3601 (match_dup 1))
3602 (parallel [(set (match_dup 3)
3603 (ashift:HI (match_dup 3)
3604 (const_int 7)))
3605 (clobber (scratch:QI))])
3606 (set (match_dup 0)
3607 (plus:SI (mult:SI (match_dup 2)
3608 (const_int 65536))
3609 (match_dup 0)))]
3610 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3611
be9d08c2
KH		 3612;; ashift:SI
3613
3614(define_insn_and_split "*ashiftsi_sextqi_7"
3615 [(set (match_operand:SI 0 "register_operand" "=r")
3616 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3617 (const_int 7)))]
3618 "(TARGET_H8300H || TARGET_H8300S)"
3619 "#"
3620 "&& reload_completed"
3621 [(parallel [(set (match_dup 2)
3622 (ashift:HI (match_dup 2)
3623 (const_int 8)))
3624 (clobber (scratch:QI))])
3625 (set (match_dup 0)
3626 (sign_extend:SI (match_dup 2)))
3627 (parallel [(set (match_dup 0)
3628 (ashiftrt:SI (match_dup 0)
3629 (const_int 1)))
3630 (clobber (scratch:QI))])]
3631 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3632
6368a493
KH		 3633;; Storing a part of HImode to QImode.
3634
3635(define_insn ""
3636 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3637 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3638 (const_int 8)) 1))]
3639 ""
3640 "mov.b\\t%t1,%R0"
3641 [(set_attr "cc" "set_znv")
3642 (set_attr "length" "8")])
3643
3644;; Storing a part of SImode to QImode.
3645
3646(define_insn ""
3647 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3648 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3649 (const_int 8)) 3))]
3650 ""
3651 "mov.b\\t%x1,%R0"
3652 [(set_attr "cc" "set_znv")
3653 (set_attr "length" "8")])
3654
3655(define_insn ""
3656 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3657 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3658 (const_int 16)) 3))
3659 (clobber (match_scratch:SI 2 "=&r"))]
3660 "TARGET_H8300H || TARGET_H8300S"
3661 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3662 [(set_attr "cc" "set_znv")
cf0cec73 3663 (set_attr "length" "10")])
6368a493
KH		 3664
3665(define_insn ""
3666 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3667 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3668 (const_int 24)) 3))
3669 (clobber (match_scratch:SI 2 "=&r"))]
3670 "TARGET_H8300H || TARGET_H8300S"
3671 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3672 [(set_attr "cc" "set_znv")
cf0cec73 3673 (set_attr "length" "10")])
6368a493 3674
ae12a094
KH		 3675(define_insn_and_split ""
3676 [(set (pc)
3677 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3678 (const_int 1)
3679 (const_int 7))
3680 (const_int 0))
3681 (label_ref (match_operand 1 "" ""))
3682 (pc)))]
3683 ""
3684 "#"
3685 ""
3686 [(set (cc0)
3687 (match_dup 0))
3688 (set (pc)
3689 (if_then_else (ge (cc0)
3690 (const_int 0))
3691 (label_ref (match_dup 1))
3692 (pc)))]
3693 "")
3694
3695(define_insn_and_split ""
3696 [(set (pc)
3697 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3698 (const_int 1)
3699 (const_int 7))
3700 (const_int 0))
3701 (label_ref (match_operand 1 "" ""))
3702 (pc)))]
3703 ""
3704 "#"
3705 ""
3706 [(set (cc0)
3707 (match_dup 0))
3708 (set (pc)
3709 (if_then_else (lt (cc0)
3710 (const_int 0))
3711 (label_ref (match_dup 1))
3712 (pc)))]
3713 "")
7957fde4
KH		 3714\f
3715;; -----------------------------------------------------------------
3716;; PEEPHOLE PATTERNS
3717;; -----------------------------------------------------------------
3718
96cc06af
KH		 3719;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3720
7957fde4
KH		 3721(define_peephole2
3722 [(parallel
3723 [(set (match_operand:HI 0 "register_operand" "")
3724 (lshiftrt:HI (match_dup 0)
3725 (match_operand:HI 1 "const_int_operand" "")))
3726 (clobber (match_operand:HI 2 "" ""))])
3727 (set (match_dup 0)
3728 (and:HI (match_dup 0)
3729 (match_operand:HI 3 "const_int_operand" "")))]
3730 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3731 [(set (match_dup 0)
3732 (and:HI (match_dup 0)
3733 (const_int 255)))
3734 (parallel
3735 [(set (match_dup 0)
3736 (lshiftrt:HI (match_dup 0)
3737 (match_dup 1)))
3738 (clobber (match_dup 2))])]
3739 "")
3740
96cc06af
KH		 3741;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3742
7957fde4
KH		 3743(define_peephole2
3744 [(parallel
3745 [(set (match_operand:HI 0 "register_operand" "")
3746 (ashift:HI (match_dup 0)
3747 (match_operand:HI 1 "const_int_operand" "")))
3748 (clobber (match_operand:HI 2 "" ""))])
3749 (set (match_dup 0)
3750 (and:HI (match_dup 0)
3751 (match_operand:HI 3 "const_int_operand" "")))]
3752 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3753 [(set (match_dup 0)
3754 (and:HI (match_dup 0)
3755 (const_int 255)))
3756 (parallel
3757 [(set (match_dup 0)
3758 (ashift:HI (match_dup 0)
3759 (match_dup 1)))
3760 (clobber (match_dup 2))])]
3761 "")
3762
96cc06af
KH		 3763;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3764
7957fde4
KH		 3765(define_peephole2
3766 [(parallel
3767 [(set (match_operand:SI 0 "register_operand" "")
3768 (lshiftrt:SI (match_dup 0)
3769 (match_operand:SI 1 "const_int_operand" "")))
3770 (clobber (match_operand:SI 2 "" ""))])
3771 (set (match_dup 0)
3772 (and:SI (match_dup 0)
3773 (match_operand:SI 3 "const_int_operand" "")))]
3774 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3775 [(set (match_dup 0)
3776 (and:SI (match_dup 0)
3777 (const_int 255)))
3778 (parallel
3779 [(set (match_dup 0)
3780 (lshiftrt:SI (match_dup 0)
3781 (match_dup 1)))
3782 (clobber (match_dup 2))])]
3783 "")
3784
96cc06af
KH		 3785;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3786
7957fde4
KH		 3787(define_peephole2
3788 [(parallel
3789 [(set (match_operand:SI 0 "register_operand" "")
3790 (ashift:SI (match_dup 0)
3791 (match_operand:SI 1 "const_int_operand" "")))
3792 (clobber (match_operand:SI 2 "" ""))])
3793 (set (match_dup 0)
3794 (and:SI (match_dup 0)
3795 (match_operand:SI 3 "const_int_operand" "")))]
3796 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3797 [(set (match_dup 0)
3798 (and:SI (match_dup 0)
3799 (const_int 255)))
3800 (parallel
3801 [(set (match_dup 0)
3802 (ashift:SI (match_dup 0)
3803 (match_dup 1)))
3804 (clobber (match_dup 2))])]
3805 "")
3806
96cc06af
KH		 3807;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3808
7957fde4
KH		 3809(define_peephole2
3810 [(parallel
3811 [(set (match_operand:SI 0 "register_operand" "")
3812 (lshiftrt:SI (match_dup 0)
3813 (match_operand:SI 1 "const_int_operand" "")))
3814 (clobber (match_operand:SI 2 "" ""))])
3815 (set (match_dup 0)
3816 (and:SI (match_dup 0)
3817 (match_operand:SI 3 "const_int_operand" "")))]
3818 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3819 [(set (match_dup 0)
3820 (and:SI (match_dup 0)
3821 (const_int 65535)))
3822 (parallel
3823 [(set (match_dup 0)
3824 (lshiftrt:SI (match_dup 0)
3825 (match_dup 1)))
3826 (clobber (match_dup 2))])]
3827 "")
3828
96cc06af
KH		 3829;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3830
7957fde4
KH		 3831(define_peephole2
3832 [(parallel
3833 [(set (match_operand:SI 0 "register_operand" "")
3834 (ashift:SI (match_dup 0)
3835 (match_operand:SI 1 "const_int_operand" "")))
3836 (clobber (match_operand:SI 2 "" ""))])
3837 (set (match_dup 0)
3838 (and:SI (match_dup 0)
3839 (match_operand:SI 3 "const_int_operand" "")))]
3840 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3841 [(set (match_dup 0)
3842 (and:SI (match_dup 0)
3843 (const_int 65535)))
3844 (parallel
3845 [(set (match_dup 0)
3846 (ashift:SI (match_dup 0)
3847 (match_dup 1)))
3848 (clobber (match_dup 2))])]
3849 "")
0a2a0a58
KH		 3850
3851;; Convert a QImode push into an SImode push so that the
3852;; define_peephole2 below can cram multiple pushes into one stm.l.
3853
3854(define_peephole2
3855 [(parallel [(set (reg:SI SP_REG)
3856 (plus:SI (reg:SI SP_REG) (const_int -4)))
3857 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3858 (match_operand:QI 0 "register_operand" ""))])]
bc02597b 3859 "TARGET_H8300S && !TARGET_NORMAL_MODE"
0a2a0a58
KH		 3860 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3861 (match_dup 0))]
3862 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3863
bc02597b
KH		 3864(define_peephole2
3865 [(parallel [(set (reg:HI SP_REG)
3866 (plus:HI (reg:HI SP_REG) (const_int -4)))
3867 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
3868 (match_operand:QI 0 "register_operand" ""))])]
3869 "TARGET_H8300S && TARGET_NORMAL_MODE"
3870 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3871 (match_dup 0))]
3872 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3873
0a2a0a58
KH		 3874;; Convert a HImode push into an SImode push so that the
3875;; define_peephole2 below can cram multiple pushes into one stm.l.
3876
3877(define_peephole2
3878 [(parallel [(set (reg:SI SP_REG)
3879 (plus:SI (reg:SI SP_REG) (const_int -4)))
3880 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3881 (match_operand:HI 0 "register_operand" ""))])]
bc02597b 3882 "TARGET_H8300S && !TARGET_NORMAL_MODE"
0a2a0a58
KH		 3883 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3884 (match_dup 0))]
3885 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3886
bc02597b
KH		 3887(define_peephole2
3888 [(parallel [(set (reg:HI SP_REG)
3889 (plus:HI (reg:HI SP_REG) (const_int -4)))
3890 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
3891 (match_operand:HI 0 "register_operand" ""))])]
3892 "TARGET_H8300S && TARGET_NORMAL_MODE"
3893 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3894 (match_dup 0))]
3895 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3896
0a2a0a58
KH		 3897;; Cram four pushes into stm.l.
3898
3899(define_peephole2
3900 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3901 (match_operand:SI 0 "register_operand" ""))
3902 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3903 (match_operand:SI 1 "register_operand" ""))
3904 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3905 (match_operand:SI 2 "register_operand" ""))
3906 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3907 (match_operand:SI 3 "register_operand" ""))]
bc02597b 3908 "TARGET_H8300S && !TARGET_NORMAL_MODE
0a2a0a58
KH		 3909 && REGNO (operands[0]) == 0
3910 && REGNO (operands[1]) == 1
3911 && REGNO (operands[2]) == 2
3912 && REGNO (operands[3]) == 3"
3913 [(parallel [(set (reg:SI SP_REG)
3914 (plus:SI (reg:SI SP_REG)
3915 (const_int -16)))
3916 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3917 (match_dup 0))
3918 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3919 (match_dup 1))
3920 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3921 (match_dup 2))
3922 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3923 (match_dup 3))])]
3924 "")
3925
bc02597b
KH		 3926(define_peephole2
3927 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3928 (match_operand:SI 0 "register_operand" ""))
3929 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3930 (match_operand:SI 1 "register_operand" ""))
3931 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3932 (match_operand:SI 2 "register_operand" ""))
3933 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3934 (match_operand:SI 3 "register_operand" ""))]
3935 "TARGET_H8300S && TARGET_NORMAL_MODE
3936 && REGNO (operands[0]) == 0
3937 && REGNO (operands[1]) == 1
3938 && REGNO (operands[2]) == 2
3939 && REGNO (operands[3]) == 3"
3940 [(parallel [(set (reg:HI SP_REG)
3941 (plus:HI (reg:HI SP_REG)
3942 (const_int -16)))
3943 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3944 (match_dup 0))
3945 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3946 (match_dup 1))
3947 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3948 (match_dup 2))
3949 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
3950 (match_dup 3))])]
3951 "")
3952
0a2a0a58
KH		 3953;; Cram three pushes into stm.l.
3954
3955(define_peephole2
3956 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3957 (match_operand:SI 0 "register_operand" ""))
3958 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3959 (match_operand:SI 1 "register_operand" ""))
3960 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3961 (match_operand:SI 2 "register_operand" ""))]
bc02597b 3962 "TARGET_H8300S && !TARGET_NORMAL_MODE
0a2a0a58
KH		 3963 && ((REGNO (operands[0]) == 0
3964 && REGNO (operands[1]) == 1
3965 && REGNO (operands[2]) == 2)
3966 || (REGNO (operands[0]) == 4
3967 && REGNO (operands[1]) == 5
3968 && REGNO (operands[2]) == 6))"
3969 [(parallel [(set (reg:SI SP_REG)
3970 (plus:SI (reg:SI SP_REG)
3971 (const_int -12)))
3972 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3973 (match_dup 0))
3974 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3975 (match_dup 1))
3976 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3977 (match_dup 2))])]
3978 "")
3979
bc02597b
KH		 3980(define_peephole2
3981 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3982 (match_operand:SI 0 "register_operand" ""))
3983 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3984 (match_operand:SI 1 "register_operand" ""))
3985 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3986 (match_operand:SI 2 "register_operand" ""))]
3987 "TARGET_H8300S && TARGET_NORMAL_MODE
3988 && ((REGNO (operands[0]) == 0
3989 && REGNO (operands[1]) == 1
3990 && REGNO (operands[2]) == 2)
3991 || (REGNO (operands[0]) == 4
3992 && REGNO (operands[1]) == 5
3993 && REGNO (operands[2]) == 6))"
3994 [(parallel [(set (reg:HI SP_REG)
3995 (plus:HI (reg:HI SP_REG)
3996 (const_int -12)))
3997 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3998 (match_dup 0))
3999 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4000 (match_dup 1))
4001 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4002 (match_dup 2))])]
4003 "")
4004
0a2a0a58
KH		 4005;; Cram two pushes into stm.l.
4006
4007(define_peephole2
4008 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4009 (match_operand:SI 0 "register_operand" ""))
4010 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4011 (match_operand:SI 1 "register_operand" ""))]
bc02597b 4012 "TARGET_H8300S && !TARGET_NORMAL_MODE
0a2a0a58
KH		 4013 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4014 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4015 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
4016 [(parallel [(set (reg:SI SP_REG)
4017 (plus:SI (reg:SI SP_REG)
4018 (const_int -8)))
4019 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4020 (match_dup 0))
4021 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4022 (match_dup 1))])]
4023 "")
68d0a3d2 4024
bc02597b
KH		 4025(define_peephole2
4026 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4027 (match_operand:SI 0 "register_operand" ""))
4028 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4029 (match_operand:SI 1 "register_operand" ""))]
4030 "TARGET_H8300S && TARGET_NORMAL_MODE
4031 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4032 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4033 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
4034 [(parallel [(set (reg:HI SP_REG)
4035 (plus:HI (reg:HI SP_REG)
4036 (const_int -8)))
4037 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4038 (match_dup 0))
4039 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4040 (match_dup 1))])]
4041 "")
4042
68d0a3d2
KH		 4043;; Turn
4044;;
4045;; mov.w #2,r0
4046;; add.w r7,r0 (6 bytes)
4047;;
4048;; into
4049;;
4050;; mov.w r7,r0
4051;; adds #2,r0 (4 bytes)
4052
4053(define_peephole2
4054 [(set (match_operand:HI 0 "register_operand" "")
4055 (match_operand:HI 1 "const_int_operand" ""))
4056 (set (match_dup 0)
4057 (plus:HI (match_dup 0)
4058 (match_operand:HI 2 "register_operand" "")))]
4059 "REG_P (operands[0]) && REG_P (operands[2])
4060 && REGNO (operands[0]) != REGNO (operands[2])
59578c84
KH		 4061 && (CONST_OK_FOR_J (INTVAL (operands[1]))
4062 || CONST_OK_FOR_L (INTVAL (operands[1]))
68d0a3d2
KH		 4063 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4064 [(set (match_dup 0)
4065 (match_dup 2))
4066 (set (match_dup 0)
4067 (plus:HI (match_dup 0)
4068 (match_dup 1)))]
4069 "")
4070
4071;; Turn
4072;;
4073;; sub.l er0,er0
4074;; add.b #4,r0l
4075;; add.l er7,er0 (6 bytes)
4076;;
4077;; into
4078;;
4079;; mov.l er7,er0
4080;; adds #4,er0 (4 bytes)
4081
4082(define_peephole2
4083 [(set (match_operand:SI 0 "register_operand" "")
4084 (match_operand:SI 1 "const_int_operand" ""))
4085 (set (match_dup 0)
4086 (plus:SI (match_dup 0)
4087 (match_operand:SI 2 "register_operand" "")))]
4088 "(TARGET_H8300H || TARGET_H8300S)
4089 && REG_P (operands[0]) && REG_P (operands[2])
4090 && REGNO (operands[0]) != REGNO (operands[2])
4091 && (CONST_OK_FOR_L (INTVAL (operands[1]))
4092 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4093 [(set (match_dup 0)
4094 (match_dup 2))
4095 (set (match_dup 0)
4096 (plus:SI (match_dup 0)
4097 (match_dup 1)))]
4098 "")
7930523d
KH		 4099
4100;; Turn
4101;;
4102;; mov.l er7,er0
4103;; add.l #10,er0 (takes 8 bytes)
4104;;
4105;; into
4106;;
4107;; sub.l er0,er0
4108;; add.b #10,r0l
4109;; add.l er7,er0 (takes 6 bytes)
4110
4111(define_peephole2
4112 [(set (match_operand:SI 0 "register_operand" "")
4113 (match_operand:SI 1 "register_operand" ""))
4114 (set (match_dup 0)
4115 (plus:SI (match_dup 0)
4116 (match_operand:SI 2 "const_int_operand" "")))]
4117 "(TARGET_H8300H || TARGET_H8300S)
4118 && REG_P (operands[0]) && REG_P (operands[1])
4119 && REGNO (operands[0]) != REGNO (operands[1])
4120 && !CONST_OK_FOR_L (INTVAL (operands[2]))
4121 && !CONST_OK_FOR_N (INTVAL (operands[2]))
4122 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4123 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4124 || INTVAL (operands[2]) == 0xffff
4125 || INTVAL (operands[2]) == 0xfffe)"
4126 [(set (match_dup 0)
4127 (match_dup 2))
4128 (set (match_dup 0)
4129 (plus:SI (match_dup 0)
4130 (match_dup 1)))]
4131 "")
f9d2de4d
KH		 4132
4133;; Turn
4134;;
4135;; subs #1,er4
4136;; mov.w r4,r4
4137;; bne .L2028
4138;;
4139;; into
4140;;
4141;; dec.w #1,r4
4142;; bne .L2028
4143
4144(define_peephole2
4145 [(set (match_operand:HI 0 "register_operand" "")
4146 (plus:HI (match_dup 0)
4147 (match_operand 1 "incdec_operand" "")))
4148 (set (cc0)
4149 (match_dup 0))
4150 (set (pc)
4151 (if_then_else (match_operator 3 "eqne_operator"
4152 [(cc0) (const_int 0)])
4153 (label_ref (match_operand 2 "" ""))
4154 (pc)))]
4155 "TARGET_H8300H || TARGET_H8300S"
4156 [(set (match_operand:HI 0 "register_operand" "")
4157 (unspec:HI [(match_dup 0)
4158 (match_dup 1)]
4159 UNSPEC_INCDEC))
4160 (set (cc0)
4161 (match_dup 0))
4162 (set (pc)
4163 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4164 (label_ref (match_dup 2))
4165 (pc)))]
4166 "")
4167
4168;; The SImode version of the previous pattern.
4169
4170(define_peephole2
4171 [(set (match_operand:SI 0 "register_operand" "")
4172 (plus:SI (match_dup 0)
4173 (match_operand 1 "incdec_operand" "")))
4174 (set (cc0)
4175 (match_dup 0))
4176 (set (pc)
4177 (if_then_else (match_operator 3 "eqne_operator"
4178 [(cc0) (const_int 0)])
4179 (label_ref (match_operand 2 "" ""))
4180 (pc)))]
4181 "TARGET_H8300H || TARGET_H8300S"
4182 [(set (match_operand:SI 0 "register_operand" "")
4183 (unspec:SI [(match_dup 0)
4184 (match_dup 1)]
4185 UNSPEC_INCDEC))
4186 (set (cc0)
4187 (match_dup 0))
4188 (set (pc)
4189 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4190 (label_ref (match_dup 2))
4191 (pc)))]
4192 "")
3cee1a78 4193
3c042316 4194(define_peephole2
82b4dc2e
KH		 4195 [(parallel [(set (cc0)
4196 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4197 (const_int 1)
4198 (const_int 7)))
4199 (clobber (scratch:QI))])
3c042316
KH		 4200 (set (pc)
4201 (if_then_else (match_operator 1 "eqne_operator"
4202 [(cc0) (const_int 0)])
4203 (label_ref (match_operand 2 "" ""))
4204 (pc)))]
4205 "(TARGET_H8300H || TARGET_H8300S)"
4206 [(set (cc0)
4207 (match_dup 0))
4208 (set (pc)
4209 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4210 (label_ref (match_dup 2))
4211 (pc)))]
4212 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4213 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4214 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4215
beb14cfe
KH		 4216;; The next three peephole2's will try to transform
4217;;
4218;; mov.b A,r0l (or mov.l A,er0)
4219;; and.l #CST,er0
4220;;
4221;; into
4222;;
4223;; sub.l er0
4224;; mov.b A,r0l
4225;; and.b #CST,r0l (if CST is not 255)
4226
b980d725
KH		 4227(define_peephole2
4228 [(set (match_operand:QI 0 "register_operand" "")
4229 (match_operand:QI 1 "general_operand" ""))
4230 (set (match_operand:SI 2 "register_operand" "")
4231 (and:SI (match_dup 2)
4232 (const_int 255)))]
4233 "(TARGET_H8300H || TARGET_H8300S)
4234 && !reg_overlap_mentioned_p (operands[2], operands[1])
4235 && REGNO (operands[0]) == REGNO (operands[2])"
4236 [(set (match_dup 2)
4237 (const_int 0))
4238 (set (strict_low_part (match_dup 0))
4239 (match_dup 1))]
4240 "")
4241
6967a126
KH		 4242(define_peephole2
4243 [(set (match_operand:SI 0 "register_operand" "")
8b41a8da 4244 (match_operand:SI 1 "general_operand" ""))
6967a126
KH		 4245 (set (match_dup 0)
4246 (and:SI (match_dup 0)
4247 (const_int 255)))]
4248 "(TARGET_H8300H || TARGET_H8300S)
8b41a8da
KH		 4249 && !reg_overlap_mentioned_p (operands[0], operands[1])
4250 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
6967a126
KH		 4251 [(set (match_dup 0)
4252 (const_int 0))
4253 (set (strict_low_part (match_dup 2))
4254 (match_dup 3))]
8b41a8da
KH		 4255 "operands[2] = gen_lowpart (QImode, operands[0]);
4256 operands[3] = gen_lowpart (QImode, operands[1]);")
6967a126 4257
101cb92a 4258(define_peephole2
beb14cfe
KH		 4259 [(set (match_operand 0 "register_operand" "")
4260 (match_operand 1 "general_operand" ""))
4261 (set (match_operand:SI 2 "register_operand" "")
4262 (and:SI (match_dup 2)
4263 (match_operand:SI 3 "const_int_qi_operand" "")))]
101cb92a 4264 "(TARGET_H8300H || TARGET_H8300S)
beb14cfe
KH		 4265 && (GET_MODE (operands[0]) == QImode
4266 || GET_MODE (operands[0]) == HImode
4267 || GET_MODE (operands[0]) == SImode)
4268 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4269 && REGNO (operands[0]) == REGNO (operands[2])
4270 && !reg_overlap_mentioned_p (operands[2], operands[1])
4271 && !(GET_MODE (operands[1]) != QImode
4272 && GET_CODE (operands[1]) == MEM
4273 && MEM_VOLATILE_P (operands[1]))"
4274 [(set (match_dup 2)
101cb92a 4275 (const_int 0))
beb14cfe
KH		 4276 (set (strict_low_part (match_dup 4))
4277 (match_dup 5))
4278 (set (match_dup 2)
4279 (and:SI (match_dup 2)
4280 (match_dup 6)))]
4281 "operands[4] = gen_lowpart (QImode, operands[0]);
4282 operands[5] = gen_lowpart (QImode, operands[1]);
4283 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
101cb92a 4284
d4048ff6
KH		 4285(define_peephole2
4286 [(set (match_operand:SI 0 "register_operand" "")
4287 (match_operand:SI 1 "register_operand" ""))
4288 (set (match_dup 0)
4289 (and:SI (match_dup 0)
4290 (const_int 65280)))]
4291 "(TARGET_H8300H || TARGET_H8300S)
4292 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4293 [(set (match_dup 0)
4294 (const_int 0))
4295 (set (zero_extract:SI (match_dup 0)
4296 (const_int 8)
4297 (const_int 8))
4298 (lshiftrt:SI (match_dup 1)
4299 (const_int 8)))]
4300 "")
4301
f3926c48
KH		 4302;; If a load of mem:SI is followed by an AND that turns off the upper
4303;; half, then we can load mem:HI instead.
4304
0135f343
KH		 4305(define_peephole2
4306 [(set (match_operand:SI 0 "register_operand" "")
4307 (match_operand:SI 1 "memory_operand" ""))
4308 (set (match_dup 0)
4309 (and:SI (match_dup 0)
4310 (match_operand:SI 2 "const_int_operand" "")))]
4311 "(TARGET_H8300H || TARGET_H8300S)
f3926c48 4312 && !MEM_VOLATILE_P (operands[1])
0135f343
KH		 4313 && (INTVAL (operands[2]) & ~0xffff) == 0
4314 && INTVAL (operands[2]) != 255"
4315 [(set (match_dup 3)
4316 (match_dup 4))
4317 (set (match_dup 0)
4318 (and:SI (match_dup 0)
4319 (match_dup 2)))]
4320 "operands[3] = gen_lowpart (HImode, operands[0]);
4321 operands[4] = gen_lowpart (HImode, operands[1]);")
4322
155de338
KH		 4323;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4324;; the equivalent with shorter sequences. Here is the summary. Cases
4325;; are grouped for each define_peephole2.
4326;;
4327;; reg const_int use insn
4328;; --------------------------------------------------------
4329;; dead -2 eq/ne inc.l
4330;; dead -1 eq/ne inc.l
4331;; dead 1 eq/ne dec.l
4332;; dead 2 eq/ne dec.l
4333;;
02529902
KH		 4334;; dead 1 geu/ltu shar.l
4335;; dead 3 (H8S) geu/ltu shar.l
155de338 4336;;
212d9313
KH		 4337;; ---- 255 geu/ltu mov.b
4338
4339;; Transform
4340;;
4341;; cmp.w #1,r0
4342;; bne .L1
4343;;
4344;; into
4345;;
4346;; dec.w #1,r0
4347;; bne .L1
4348
4349(define_peephole2
4350 [(set (cc0)
4351 (compare (match_operand:HI 0 "register_operand" "")
4352 (match_operand:HI 1 "incdec_operand" "")))
4353 (set (pc)
4354 (if_then_else (match_operator 3 "eqne_operator"
4355 [(cc0) (const_int 0)])
4356 (label_ref (match_operand 2 "" ""))
4357 (pc)))]
4358 "(TARGET_H8300H || TARGET_H8300S)
4359 && peep2_reg_dead_p (1, operands[0])"
4360 [(set (match_dup 0)
4361 (unspec:HI [(match_dup 0)
4362 (match_dup 4)]
4363 UNSPEC_INCDEC))
4364 (set (cc0)
4365 (match_dup 0))
4366 (set (pc)
4367 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4368 (label_ref (match_dup 2))
4369 (pc)))]
4370 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4371
4372;; Transform
4373;;
4374;; cmp.w #1,r0
4375;; bhi .L1
4376;;
4377;; into
4378;;
02529902 4379;; shar.w r0
212d9313 4380;; bne .L1
155de338
KH		 4381
4382(define_peephole2
4383 [(set (cc0)
4384 (compare (match_operand:HI 0 "register_operand" "")
4385 (match_operand:HI 1 "const_int_operand" "")))
4386 (set (pc)
02529902 4387 (if_then_else (match_operator 2 "gtle_operator"
155de338
KH		 4388 [(cc0) (const_int 0)])
4389 (label_ref (match_operand 3 "" ""))
4390 (pc)))]
4391 "(TARGET_H8300H || TARGET_H8300S)
4392 && peep2_reg_dead_p (1, operands[0])
4393 && (INTVAL (operands[1]) == 1
4394 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4395 [(parallel [(set (match_dup 0)
02529902 4396 (ashiftrt:HI (match_dup 0)
155de338
KH		 4397 (match_dup 5)))
4398 (clobber (scratch:QI))])
4399 (set (cc0)
4400 (match_dup 0))
4401 (set (pc)
4402 (if_then_else (match_dup 4)
4403 (label_ref (match_dup 3))
4404 (pc)))]
02529902
KH		 4405 "switch (GET_CODE (operands[2]))
4406 {
4407 case GTU:
4408 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4409 break;
4410 case LEU:
4411 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4412 break;
4413 default:
4414 operands[4] = operands[2];
4415 break;
4416 }
155de338
KH		 4417 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4418
212d9313
KH		 4419;; Transform
4420;;
4421;; cmp.w #255,r0
4422;; bhi .L1
4423;;
4424;; into
4425;;
4426;; mov.b r0h,r0h
4427;; bne .L1
4428
4429(define_peephole2
4430 [(set (cc0)
4431 (compare (match_operand:HI 0 "register_operand" "")
4432 (const_int 255)))
4433 (set (pc)
203dcb74 4434 (if_then_else (match_operator 1 "gtle_operator"
212d9313
KH		 4435 [(cc0) (const_int 0)])
4436 (label_ref (match_operand 2 "" ""))
4437 (pc)))]
4438 "TARGET_H8300H || TARGET_H8300S"
4439 [(set (cc0)
4440 (and:HI (match_dup 0)
4441 (const_int -256)))
4442 (set (pc)
203dcb74 4443 (if_then_else (match_dup 3)
212d9313
KH		 4444 (label_ref (match_dup 2))
4445 (pc)))]
203dcb74
KH		 4446 "switch (GET_CODE (operands[1]))
4447 {
4448 case GTU:
4449 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4450 break;
4451 case LEU:
4452 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4453 break;
4454 default:
4455 operands[3] = operands[1];
4456 break;
4457 }")
212d9313 4458
6dc50366 4459;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
590734b6
KH		 4460;; the equivalent with shorter sequences. Here is the summary. Cases
4461;; are grouped for each define_peephole2.
4302db79 4462;;
590734b6
KH		 4463;; reg const_int use insn
4464;; --------------------------------------------------------
4465;; live -2 eq/ne copy and inc.l
4466;; live -1 eq/ne copy and inc.l
4467;; live 1 eq/ne copy and dec.l
4468;; live 2 eq/ne copy and dec.l
4469;;
4470;; dead -2 eq/ne inc.l
4471;; dead -1 eq/ne inc.l
4472;; dead 1 eq/ne dec.l
4473;; dead 2 eq/ne dec.l
4474;;
e5258f85
KH		 4475;; dead -131072 eq/ne inc.w and test
4476;; dead -65536 eq/ne inc.w and test
4d1da12a
KH		 4477;; dead 65536 eq/ne dec.w and test
4478;; dead 131072 eq/ne dec.w and test
e5258f85 4479;;
590734b6
KH		 4480;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4481;; dead 0x0000??00 eq/ne xor.b and test
4482;; dead 0x0000ffff eq/ne not.w and test
590734b6
KH		 4483;;
4484;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4485;; dead 0xffff??ff eq/ne xor.b and not.l
ae12c666
KH		 4486;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
4487;; dead 0x80000000 eq/ne rotl.l and dec.l
590734b6 4488;;
02529902
KH		 4489;; live 1 geu/ltu copy and shar.l
4490;; live 3 (H8S) geu/ltu copy and shar.l
d98cd543 4491;;
02529902
KH		 4492;; dead 1 geu/ltu shar.l
4493;; dead 3 (H8S) geu/ltu shar.l
ef3a7d56
KH		 4494;;
4495;; dead 3 (H8/300H) geu/ltu and.b and test
590734b6
KH		 4496;; dead 7 geu/ltu and.b and test
4497;; dead 15 geu/ltu and.b and test
4498;; dead 31 geu/ltu and.b and test
4499;; dead 63 geu/ltu and.b and test
4500;; dead 127 geu/ltu and.b and test
4501;; dead 255 geu/ltu and.b and test
4502;;
4503;; dead 65535 geu/ltu mov.w
4302db79 4504
3cee1a78
KH		 4505;; For a small constant, it is cheaper to actually do the subtraction
4506;; and then test the register.
4507
3cee1a78
KH		 4508(define_peephole2
4509 [(set (cc0)
6dc50366 4510 (compare (match_operand:SI 0 "register_operand" "")
590734b6 4511 (match_operand:SI 1 "incdec_operand" "")))
3cee1a78
KH		 4512 (set (pc)
4513 (if_then_else (match_operator 3 "eqne_operator"
4514 [(cc0) (const_int 0)])
4515 (label_ref (match_operand 2 "" ""))
4516 (pc)))]
4517 "(TARGET_H8300H || TARGET_H8300S)
86bc9b19 4518 && peep2_reg_dead_p (1, operands[0])"
590734b6
KH		 4519 [(set (match_dup 0)
4520 (unspec:SI [(match_dup 0)
4521 (match_dup 4)]
4522 UNSPEC_INCDEC))
4523 (set (cc0)
3cee1a78
KH		 4524 (match_dup 0))
4525 (set (pc)
4526 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
871d6a01 4527 (label_ref (match_dup 2))
3cee1a78 4528 (pc)))]
590734b6 4529 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
2873836b 4530
e5258f85
KH		 4531(define_peephole2
4532 [(set (cc0)
4533 (compare (match_operand:SI 0 "register_operand" "")
4534 (match_operand:SI 1 "const_int_operand" "")))
4535 (set (pc)
4536 (if_then_else (match_operator 3 "eqne_operator"
4537 [(cc0) (const_int 0)])
4538 (label_ref (match_operand 2 "" ""))
4539 (pc)))]
4540 "(TARGET_H8300H || TARGET_H8300S)
4541 && peep2_reg_dead_p (1, operands[0])
4542 && (INTVAL (operands[1]) == -131072
4543 || INTVAL (operands[1]) == -65536
4544 || INTVAL (operands[1]) == 65536
4545 || INTVAL (operands[1]) == 131072)"
4546 [(set (match_dup 0)
4547 (plus:SI (match_dup 0)
4548 (match_dup 4)))
4549 (set (cc0)
4550 (match_dup 0))
4551 (set (pc)
4552 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4553 (label_ref (match_dup 2))
4554 (pc)))]
4555 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4556
2a43945f 4557;; For certain (in)equality comparisons against a constant, we can
4302db79
KH		 4558;; XOR the register with the constant, and test the register against
4559;; 0.
4560
4561(define_peephole2
4562 [(set (cc0)
6dc50366
KH		 4563 (compare (match_operand:SI 0 "register_operand" "")
4564 (match_operand:SI 1 "const_int_operand" "")))
4302db79
KH		 4565 (set (pc)
4566 (if_then_else (match_operator 3 "eqne_operator"
4567 [(cc0) (const_int 0)])
4568 (label_ref (match_operand 2 "" ""))
4569 (pc)))]
4570 "(TARGET_H8300H || TARGET_H8300S)
4571 && peep2_reg_dead_p (1, operands[0])
4572 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4573 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
36bf3f1b 4574 || INTVAL (operands[1]) == 0x0000ffff)
4302db79
KH		 4575 && INTVAL (operands[1]) != 1
4576 && INTVAL (operands[1]) != 2"
4577 [(set (match_dup 0)
4578 (xor:SI (match_dup 0)
4579 (match_dup 1)))
4580 (set (cc0)
4581 (match_dup 0))
4582 (set (pc)
4583 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4584 (label_ref (match_dup 2))
4585 (pc)))]
4586 "")
4587
590734b6
KH		 4588(define_peephole2
4589 [(set (cc0)
4590 (compare (match_operand:SI 0 "register_operand" "")
4591 (match_operand:SI 1 "const_int_operand" "")))
4592 (set (pc)
4593 (if_then_else (match_operator 3 "eqne_operator"
4594 [(cc0) (const_int 0)])
4595 (label_ref (match_operand 2 "" ""))
4596 (pc)))]
4597 "(TARGET_H8300H || TARGET_H8300S)
4598 && peep2_reg_dead_p (1, operands[0])
4599 && ((INTVAL (operands[1]) | 0x00ff) == -1
4600 || (INTVAL (operands[1]) | 0xff00) == -1)
4601 && INTVAL (operands[1]) != -1
4602 && INTVAL (operands[1]) != -2"
4603 [(set (match_dup 0)
4604 (xor:SI (match_dup 0)
4605 (match_dup 4)))
4606 (set (match_dup 0)
4607 (not:SI (match_dup 0)))
4608 (set (cc0)
4609 (match_dup 0))
4610 (set (pc)
4611 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4612 (label_ref (match_dup 2))
4613 (pc)))]
4614 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4615
ae12c666
KH		 4616(define_peephole2
4617 [(set (cc0)
4618 (compare (match_operand:SI 0 "register_operand" "")
4619 (match_operand:SI 1 "const_int_operand" "")))
4620 (set (pc)
4621 (if_then_else (match_operator 3 "eqne_operator"
4622 [(cc0) (const_int 0)])
4623 (label_ref (match_operand 2 "" ""))
4624 (pc)))]
4625 "(TARGET_H8300H || TARGET_H8300S)
4626 && peep2_reg_dead_p (1, operands[0])
60731ce5 4627 && (INTVAL (operands[1]) == -2147483647 - 1
ae12c666
KH		 4628 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
4629 [(set (match_dup 0)
4630 (rotate:SI (match_dup 0)
4631 (match_dup 4)))
4632 (set (match_dup 0)
4633 (unspec:SI [(match_dup 0)
4634 (const_int -1)]
4635 UNSPEC_INCDEC))
4636 (set (cc0)
4637 (match_dup 0))
4638 (set (pc)
4639 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4640 (label_ref (match_dup 2))
4641 (pc)))]
60731ce5 4642 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
ae12c666 4643
d98cd543
KH		 4644;; Transform
4645;;
4646;; cmp.l #1,er0
4647;; bhi .L1
4648;;
4649;; into
4650;;
4651;; mov.l er0,er1
02529902 4652;; shar.l er1
d98cd543
KH		 4653;; bne .L1
4654
02529902
KH		 4655;; We avoid this transformation if we see more than one copy of the
4656;; same compare insn immediately before this one.
4657
d98cd543
KH		 4658(define_peephole2
4659 [(match_scratch:SI 4 "r")
4660 (set (cc0)
4661 (compare (match_operand:SI 0 "register_operand" "")
4662 (match_operand:SI 1 "const_int_operand" "")))
4663 (set (pc)
02529902 4664 (if_then_else (match_operator 2 "gtle_operator"
d98cd543
KH		 4665 [(cc0) (const_int 0)])
4666 (label_ref (match_operand 3 "" ""))
4667 (pc)))]
4668 "(TARGET_H8300H || TARGET_H8300S)
4669 && !peep2_reg_dead_p (1, operands[0])
4670 && (INTVAL (operands[1]) == 1
02529902
KH		 4671 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4672 && !same_cmp_preceding_p (insn)"
d98cd543
KH		 4673 [(set (match_dup 4)
4674 (match_dup 0))
4675 (parallel [(set (match_dup 4)
02529902 4676 (ashiftrt:SI (match_dup 4)
d98cd543
KH		 4677 (match_dup 6)))
4678 (clobber (scratch:QI))])
4679 (set (cc0)
4680 (match_dup 4))
4681 (set (pc)
4682 (if_then_else (match_dup 5)
4683 (label_ref (match_dup 3))
4684 (pc)))]
02529902
KH		 4685 "switch (GET_CODE (operands[2]))
4686 {
4687 case GTU:
4688 operands[5] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4689 break;
4690 case LEU:
4691 operands[5] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4692 break;
4693 default:
4694 operands[5] = operands[2];
4695 break;
4696 }
d98cd543
KH		 4697 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4698
ef3a7d56
KH		 4699;; Transform
4700;;
4701;; cmp.l #1,er0
4702;; bhi .L1
4703;;
4704;; into
4705;;
02529902 4706;; shar.l er0
ef3a7d56
KH		 4707;; bne .L1
4708
4709(define_peephole2
4710 [(set (cc0)
4711 (compare (match_operand:SI 0 "register_operand" "")
4712 (match_operand:SI 1 "const_int_operand" "")))
4713 (set (pc)
02529902 4714 (if_then_else (match_operator 2 "gtle_operator"
ef3a7d56
KH		 4715 [(cc0) (const_int 0)])
4716 (label_ref (match_operand 3 "" ""))
4717 (pc)))]
4718 "(TARGET_H8300H || TARGET_H8300S)
4719 && peep2_reg_dead_p (1, operands[0])
4720 && (INTVAL (operands[1]) == 1
4721 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4722 [(parallel [(set (match_dup 0)
02529902 4723 (ashiftrt:SI (match_dup 0)
ef3a7d56
KH		 4724 (match_dup 5)))
4725 (clobber (scratch:QI))])
4726 (set (cc0)
4727 (match_dup 0))
4728 (set (pc)
4729 (if_then_else (match_dup 4)
4730 (label_ref (match_dup 3))
4731 (pc)))]
02529902
KH		 4732 "switch (GET_CODE (operands[2]))
4733 {
4734 case GTU:
4735 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4736 break;
4737 case LEU:
4738 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4739 break;
4740 default:
4741 operands[4] = operands[2];
4742 break;
4743 }
ef3a7d56
KH		 4744 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4745
8fc9a7ba
KH		 4746;; Transform
4747;;
4748;; cmp.l #15,er0
4749;; bhi .L1
4750;;
4751;; into
4752;;
4753;; and #240,r0l
4754;; mov.l er0,er0
4755;; bne .L1
717d8b71
KH		 4756
4757(define_peephole2
4758 [(set (cc0)
6dc50366
KH		 4759 (compare (match_operand:SI 0 "register_operand" "")
4760 (match_operand:SI 1 "const_int_operand" "")))
717d8b71 4761 (set (pc)
9a2dd2dd 4762 (if_then_else (match_operator 2 "gtle_operator"
717d8b71
KH		 4763 [(cc0) (const_int 0)])
4764 (label_ref (match_operand 3 "" ""))
4765 (pc)))]
4766 "(TARGET_H8300H || TARGET_H8300S)
86bc9b19 4767 && peep2_reg_dead_p (1, operands[0])
8fc9a7ba 4768 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
717d8b71
KH		 4769 || INTVAL (operands[1]) == 7
4770 || INTVAL (operands[1]) == 15
4771 || INTVAL (operands[1]) == 31
a05566a3 4772 || INTVAL (operands[1]) == 63
717d8b71 4773 || INTVAL (operands[1]) == 127
9083b5da 4774 || INTVAL (operands[1]) == 255)"
717d8b71
KH		 4775 [(set (match_dup 0)
4776 (and:SI (match_dup 0)
4777 (match_dup 5)))
4778 (set (cc0)
4779 (match_dup 0))
4780 (set (pc)
4781 (if_then_else (match_dup 4)
4782 (label_ref (match_dup 3))
4783 (pc)))]
9a2dd2dd
KH		 4784 "switch (GET_CODE (operands[2]))
4785 {
4786 case GTU:
4787 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4788 break;
4789 case LEU:
4790 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4791 break;
4792 default:
4793 operands[4] = operands[2];
4794 break;
4795 }
717d8b71
KH		 4796 operands[5] = GEN_INT (~INTVAL (operands[1]));")
4797
9083b5da
KH		 4798;; Transform A <= 65535 to (A & 0xffff0000) == 0.
4799
4800(define_peephole2
4801 [(set (cc0)
6dc50366
KH		 4802 (compare (match_operand:SI 0 "register_operand" "")
4803 (const_int 65535)))
9083b5da 4804 (set (pc)
203dcb74 4805 (if_then_else (match_operator 1 "gtle_operator"
9083b5da
KH		 4806 [(cc0) (const_int 0)])
4807 (label_ref (match_operand 2 "" ""))
4808 (pc)))]
4809 "TARGET_H8300H || TARGET_H8300S"
4810 [(set (cc0)
4811 (and:SI (match_dup 0)
4812 (const_int -65536)))
4813 (set (pc)
203dcb74 4814 (if_then_else (match_dup 3)
9083b5da
KH		 4815 (label_ref (match_dup 2))
4816 (pc)))]
203dcb74
KH		 4817 "switch (GET_CODE (operands[1]))
4818 {
4819 case GTU:
4820 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4821 break;
4822 case LEU:
4823 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4824 break;
4825 default:
4826 operands[3] = operands[1];
4827 break;
4828 }")
9083b5da 4829
2bbfc542
KH		 4830;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
4831;; of the register being tested, do the subtraction on the copy, and
4832;; then test the copy. We avoid this transformation if we see more
4833;; than one copy of the same compare insn.
4834
4835(define_peephole2
4836 [(match_scratch:SI 4 "r")
4837 (set (cc0)
6dc50366
KH		 4838 (compare (match_operand:SI 0 "register_operand" "")
4839 (match_operand:SI 1 "incdec_operand" "")))
2bbfc542
KH		 4840 (set (pc)
4841 (if_then_else (match_operator 3 "eqne_operator"
4842 [(cc0) (const_int 0)])
4843 (label_ref (match_operand 2 "" ""))
4844 (pc)))]
4845 "(TARGET_H8300H || TARGET_H8300S)
4846 && !peep2_reg_dead_p (1, operands[0])
c06d5c85 4847 && !same_cmp_following_p (insn)"
590734b6 4848 [(set (match_dup 4)
2bbfc542 4849 (match_dup 0))
590734b6
KH		 4850 (set (match_dup 4)
4851 (unspec:SI [(match_dup 4)
4852 (match_dup 5)]
4853 UNSPEC_INCDEC))
4854 (set (cc0)
4855 (match_dup 4))
2bbfc542
KH		 4856 (set (pc)
4857 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4858 (label_ref (match_dup 2))
4859 (pc)))]
590734b6 4860 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
2bbfc542 4861
2873836b
KH		 4862;; Narrow the mode of testing if possible.
4863
4864(define_peephole2
4865 [(set (match_operand:HI 0 "register_operand" "")
4866 (and:HI (match_dup 0)
4867 (match_operand:HI 1 "const_int_qi_operand" "")))
4868 (set (cc0)
4869 (match_dup 0))
4870 (set (pc)
4871 (if_then_else (match_operator 3 "eqne_operator"
4872 [(cc0) (const_int 0)])
4873 (label_ref (match_operand 2 "" ""))
4874 (pc)))]
86bc9b19 4875 "peep2_reg_dead_p (2, operands[0])"
2873836b
KH		 4876 [(set (match_dup 4)
4877 (and:QI (match_dup 4)
4878 (match_dup 5)))
4879 (set (cc0)
4880 (match_dup 4))
4881 (set (pc)
4882 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4883 (label_ref (match_dup 2))
4884 (pc)))]
4885 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
273fc01e 4886 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
2873836b
KH		 4887
4888(define_peephole2
4889 [(set (match_operand:SI 0 "register_operand" "")
4890 (and:SI (match_dup 0)
4891 (match_operand:SI 1 "const_int_qi_operand" "")))
4892 (set (cc0)
4893 (match_dup 0))
4894 (set (pc)
4895 (if_then_else (match_operator 3 "eqne_operator"
4896 [(cc0) (const_int 0)])
4897 (label_ref (match_operand 2 "" ""))
4898 (pc)))]
86bc9b19 4899 "peep2_reg_dead_p (2, operands[0])"
2873836b
KH		 4900 [(set (match_dup 4)
4901 (and:QI (match_dup 4)
4902 (match_dup 5)))
4903 (set (cc0)
4904 (match_dup 4))
4905 (set (pc)
4906 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4907 (label_ref (match_dup 2))
4908 (pc)))]
4909 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
273fc01e 4910 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
2873836b
KH		 4911
4912(define_peephole2
4913 [(set (match_operand:SI 0 "register_operand" "")
4914 (and:SI (match_dup 0)
4915 (match_operand:SI 1 "const_int_hi_operand" "")))
4916 (set (cc0)
4917 (match_dup 0))
4918 (set (pc)
4919 (if_then_else (match_operator 3 "eqne_operator"
4920 [(cc0) (const_int 0)])
4921 (label_ref (match_operand 2 "" ""))
4922 (pc)))]
86bc9b19 4923 "peep2_reg_dead_p (2, operands[0])"
2873836b
KH		 4924 [(set (match_dup 4)
4925 (and:HI (match_dup 4)
4926 (match_dup 5)))
4927 (set (cc0)
4928 (match_dup 4))
4929 (set (pc)
4930 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4931 (label_ref (match_dup 2))
4932 (pc)))]
4933 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
273fc01e 4934 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
902ac719
KH		 4935
4936(define_peephole2
4937 [(set (match_operand:SI 0 "register_operand" "")
4938 (and:SI (match_dup 0)
4939 (match_operand:SI 1 "const_int_qi_operand" "")))
4940 (set (match_dup 0)
4941 (xor:SI (match_dup 0)
4942 (match_operand:SI 2 "const_int_qi_operand" "")))
4943 (set (cc0)
4944 (match_dup 0))
4945 (set (pc)
4946 (if_then_else (match_operator 4 "eqne_operator"
4947 [(cc0) (const_int 0)])
4948 (label_ref (match_operand 3 "" ""))
4949 (pc)))]
4950 "peep2_reg_dead_p (3, operands[0])
4951 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4952 [(set (match_dup 5)
4953 (and:QI (match_dup 5)
4954 (match_dup 6)))
4955 (set (match_dup 5)
4956 (xor:QI (match_dup 5)
4957 (match_dup 7)))
4958 (set (cc0)
4959 (match_dup 5))
4960 (set (pc)
4961 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4962 (label_ref (match_dup 3))
4963 (pc)))]
4964 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
273fc01e
KH		 4965 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
4966 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
GNU Compiler Collection
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