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f0b6f9a6 | 1 | /* Definitions of target machine for GNU compiler. |
340f6494 | 2 | Renesas H8/300 (generic) |
cf011243 | 3 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, |
6d6b0a12 | 4 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
7bc8cb2b DE |
5 | Contributed by Steve Chamberlain (sac@cygnus.com), |
6 | Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). | |
07aae5c2 | 7 | |
8aa063fb | 8 | This file is part of GCC. |
07aae5c2 | 9 | |
8aa063fb | 10 | GCC is free software; you can redistribute it and/or modify |
07aae5c2 SC |
11 | it under the terms of the GNU General Public License as published by |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
8aa063fb | 15 | GCC is distributed in the hope that it will be useful, |
07aae5c2 SC |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
8aa063fb | 21 | along with GCC; see the file COPYING. If not, write to |
97aadbb9 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
07aae5c2 | 24 | |
8b97c5f8 ZW |
25 | #ifndef GCC_H8300_H |
26 | #define GCC_H8300_H | |
27 | ||
2c54abce | 28 | /* Which CPU to compile for. |
7bc8cb2b DE |
29 | We use int for CPU_TYPE to avoid lots of casts. */ |
30 | #if 0 /* defined in insn-attr.h, here for documentation */ | |
31 | enum attr_cpu { CPU_H8300, CPU_H8300H }; | |
32 | #endif | |
33 | extern int cpu_type; | |
34 | ||
35 | /* Various globals defined in h8300.c. */ | |
36 | ||
07e4d94e | 37 | extern const char *h8_push_op, *h8_pop_op, *h8_mov_op; |
441d04c6 | 38 | extern const char * const *h8_reg_names; |
7bc8cb2b | 39 | |
537fc532 NB |
40 | /* Target CPU builtins. */ |
41 | #define TARGET_CPU_CPP_BUILTINS() \ | |
42 | do \ | |
43 | { \ | |
44 | if (TARGET_H8300H) \ | |
920e86b8 | 45 | { \ |
537fc532 NB |
46 | builtin_define ("__H8300H__"); \ |
47 | builtin_assert ("cpu=h8300h"); \ | |
48 | builtin_assert ("machine=h8300h"); \ | |
39ba95b5 VK |
49 | if (TARGET_NORMAL_MODE) \ |
50 | { \ | |
51 | builtin_define ("__NORMAL_MODE__"); \ | |
52 | } \ | |
537fc532 NB |
53 | } \ |
54 | else if (TARGET_H8300S) \ | |
920e86b8 | 55 | { \ |
537fc532 NB |
56 | builtin_define ("__H8300S__"); \ |
57 | builtin_assert ("cpu=h8300s"); \ | |
58 | builtin_assert ("machine=h8300s"); \ | |
39ba95b5 VK |
59 | if (TARGET_NORMAL_MODE) \ |
60 | { \ | |
61 | builtin_define ("__NORMAL_MODE__"); \ | |
62 | } \ | |
537fc532 NB |
63 | } \ |
64 | else \ | |
920e86b8 | 65 | { \ |
537fc532 NB |
66 | builtin_define ("__H8300__"); \ |
67 | builtin_assert ("cpu=h8300"); \ | |
68 | builtin_assert ("machine=h8300"); \ | |
69 | } \ | |
537fc532 NB |
70 | } \ |
71 | while (0) | |
7bc8cb2b | 72 | |
5c29d24c | 73 | #define LINK_SPEC "%{mh:%{mn:-m h8300hn}} %{mh:%{!mn:-m h8300h}} %{ms:%{mn:-m h8300sn}} %{ms:%{!mn:-m h8300s}}" |
7bc8cb2b DE |
74 | |
75 | #define LIB_SPEC "%{mrelax:-relax} %{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" | |
07aae5c2 | 76 | |
920e86b8 KH |
77 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
78 | do \ | |
79 | { \ | |
80 | /* Basic block reordering is only beneficial on targets with cache \ | |
81 | and/or variable-cycle branches where (cycle count taken != \ | |
82 | cycle count not taken). */ \ | |
83 | flag_reorder_blocks = 0; \ | |
84 | } \ | |
25a533a0 TM |
85 | while (0) |
86 | ||
07aae5c2 | 87 | /* Print subsidiary information on the compiler version in use. */ |
7bc8cb2b | 88 | |
340f6494 | 89 | #define TARGET_VERSION fprintf (stderr, " (Renesas H8/300)"); |
7bc8cb2b | 90 | |
07aae5c2 | 91 | /* Run-time compilation parameters selecting different hardware subsets. */ |
7bc8cb2b DE |
92 | |
93 | extern int target_flags; | |
07aae5c2 | 94 | |
1862869d KH |
95 | /* Masks for the -m switches. */ |
96 | #define MASK_H8300S 0x00000001 | |
97 | #define MASK_MAC 0x00000002 | |
98 | #define MASK_INT32 0x00000008 | |
99 | #define MASK_ADDRESSES 0x00000040 | |
100 | #define MASK_QUICKCALL 0x00000080 | |
101 | #define MASK_SLOWBYTE 0x00000100 | |
39ba95b5 | 102 | #define MASK_NORMAL_MODE 0x00000200 |
1862869d | 103 | #define MASK_RELAX 0x00000400 |
1862869d KH |
104 | #define MASK_H8300H 0x00001000 |
105 | #define MASK_ALIGN_300 0x00002000 | |
106 | ||
07aae5c2 SC |
107 | /* Macros used in the machine description to test the flags. */ |
108 | ||
7bc8cb2b | 109 | /* Make int's 32 bits. */ |
1862869d | 110 | #define TARGET_INT32 (target_flags & MASK_INT32) |
7bc8cb2b DE |
111 | |
112 | /* Dump recorded insn lengths into the output file. This helps debug the | |
113 | md file. */ | |
1862869d | 114 | #define TARGET_ADDRESSES (target_flags & MASK_ADDRESSES) |
7bc8cb2b DE |
115 | |
116 | /* Pass the first few arguments in registers. */ | |
1862869d | 117 | #define TARGET_QUICKCALL (target_flags & MASK_QUICKCALL) |
7bc8cb2b DE |
118 | |
119 | /* Pretend byte accesses are slow. */ | |
1862869d | 120 | #define TARGET_SLOWBYTE (target_flags & MASK_SLOWBYTE) |
7bc8cb2b | 121 | |
1898584f | 122 | /* Select between the H8/300 and H8/300H CPUs. */ |
a1616dd9 | 123 | #define TARGET_H8300 (! TARGET_H8300H && ! TARGET_H8300S) |
1862869d KH |
124 | #define TARGET_H8300H (target_flags & MASK_H8300H) |
125 | #define TARGET_H8300S (target_flags & MASK_H8300S) | |
39ba95b5 | 126 | #define TARGET_NORMAL_MODE (target_flags & MASK_NORMAL_MODE) |
7bc8cb2b | 127 | |
17f0f8fa | 128 | /* mac register and relevant instructions are available. */ |
1862869d | 129 | #define TARGET_MAC (target_flags & MASK_MAC) |
17f0f8fa | 130 | |
1898584f | 131 | /* Align all values on the H8/300H the same way as the H8/300. Specifically, |
20d1e666 | 132 | 32 bit and larger values are aligned on 16 bit boundaries. |
46eefac4 | 133 | This is all the hardware requires, but the default is 32 bits for the H8/300H. |
a6cc0d48 DE |
134 | ??? Now watch someone add hardware floating point requiring 32 bit |
135 | alignment. */ | |
1862869d | 136 | #define TARGET_ALIGN_300 (target_flags & MASK_ALIGN_300) |
a6cc0d48 | 137 | |
07aae5c2 SC |
138 | /* Macro to define tables used to set the flags. |
139 | This is a list in braces of pairs in braces, | |
140 | each pair being { "NAME", VALUE } | |
141 | where VALUE is the bits to set or minus the bits to clear. | |
142 | An empty string NAME is used to identify the default VALUE. */ | |
143 | ||
1862869d KH |
144 | #define TARGET_SWITCHES \ |
145 | { {"s", MASK_H8300S, N_("Generate H8S code")}, \ | |
146 | {"no-s", -MASK_H8300S, N_("Do not generate H8S code")}, \ | |
147 | {"s2600", MASK_MAC, N_("Generate H8S/2600 code")}, \ | |
148 | {"no-s2600", -MASK_MAC, N_("Do not generate H8S/2600 code")}, \ | |
149 | {"int32", MASK_INT32, N_("Make integers 32 bits wide")}, \ | |
150 | {"addresses", MASK_ADDRESSES, NULL}, \ | |
151 | {"quickcall", MASK_QUICKCALL, \ | |
152 | N_("Use registers for argument passing")}, \ | |
153 | {"no-quickcall", -MASK_QUICKCALL, \ | |
154 | N_("Do not use registers for argument passing")}, \ | |
155 | {"slowbyte", MASK_SLOWBYTE, \ | |
156 | N_("Consider access to byte sized memory slow")}, \ | |
157 | {"relax", MASK_RELAX, N_("Enable linker relaxing")}, \ | |
1862869d | 158 | {"h", MASK_H8300H, N_("Generate H8/300H code")}, \ |
920e86b8 | 159 | {"n", MASK_NORMAL_MODE, N_("Enable the normal mode")}, \ |
1862869d KH |
160 | {"no-h", -MASK_H8300H, N_("Do not generate H8/300H code")}, \ |
161 | {"align-300", MASK_ALIGN_300, N_("Use H8/300 alignment rules")}, \ | |
162 | { "", TARGET_DEFAULT, NULL}} | |
07aae5c2 | 163 | |
996ed075 JJ |
164 | #ifdef IN_LIBGCC2 |
165 | #undef TARGET_H8300H | |
166 | #undef TARGET_H8300S | |
39ba95b5 | 167 | #undef TARGET_NORMAL_MODE |
996ed075 JJ |
168 | /* If compiling libgcc2, make these compile time constants based on what |
169 | flags are we actually compiling with. */ | |
170 | #ifdef __H8300H__ | |
171 | #define TARGET_H8300H 1 | |
172 | #else | |
173 | #define TARGET_H8300H 0 | |
174 | #endif | |
175 | #ifdef __H8300S__ | |
176 | #define TARGET_H8300S 1 | |
177 | #else | |
178 | #define TARGET_H8300S 0 | |
179 | #endif | |
39ba95b5 VK |
180 | #ifdef __NORMAL_MODE__ |
181 | #define TARGET_NORMAL_MODE 1 | |
182 | #else | |
183 | #define TARGET_NORMAL_MODE 0 | |
184 | #endif | |
996ed075 JJ |
185 | #endif /* !IN_LIBGCC2 */ |
186 | ||
43074b10 | 187 | /* Do things that must be done once at start up. */ |
3511415d | 188 | |
2c54abce KH |
189 | #define OVERRIDE_OPTIONS \ |
190 | do \ | |
191 | { \ | |
192 | h8300_init_once (); \ | |
193 | } \ | |
194 | while (0) | |
7bc8cb2b DE |
195 | |
196 | /* Default target_flags if no switches specified. */ | |
197 | ||
198 | #ifndef TARGET_DEFAULT | |
3950794d | 199 | #define TARGET_DEFAULT (MASK_QUICKCALL) |
7bc8cb2b DE |
200 | #endif |
201 | ||
faa2075e | 202 | /* Show we can debug even without a frame pointer. */ |
7bc8cb2b | 203 | /* #define CAN_DEBUG_WITHOUT_FP */ |
07aae5c2 | 204 | |
faa2075e RK |
205 | /* Define this if addresses of constant functions |
206 | shouldn't be put through pseudo regs where they can be cse'd. | |
207 | Desirable on machines where ordinary constants are expensive | |
f0b6f9a6 | 208 | but a CALL with constant address is cheap. |
bd93f126 JL |
209 | |
210 | Calls through a register are cheaper than calls to named | |
211 | functions; however, the register pressure this causes makes | |
212 | CSEing of function addresses generally a lose. */ | |
07e4d94e | 213 | #define NO_FUNCTION_CSE |
07aae5c2 | 214 | \f |
7bc8cb2b DE |
215 | /* Target machine storage layout */ |
216 | ||
07aae5c2 SC |
217 | /* Define this if most significant bit is lowest numbered |
218 | in instructions that operate on numbered bit-fields. | |
219 | This is not true on the H8/300. */ | |
220 | #define BITS_BIG_ENDIAN 0 | |
221 | ||
222 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
223 | /* That is true on the H8/300. */ | |
224 | #define BYTES_BIG_ENDIAN 1 | |
225 | ||
226 | /* Define this if most significant word of a multiword number is lowest | |
3f69c502 | 227 | numbered. */ |
07aae5c2 SC |
228 | #define WORDS_BIG_ENDIAN 1 |
229 | ||
7bc8cb2b | 230 | #define MAX_BITS_PER_WORD 32 |
07aae5c2 SC |
231 | |
232 | /* Width of a word, in units (bytes). */ | |
a1616dd9 | 233 | #define UNITS_PER_WORD (TARGET_H8300H || TARGET_H8300S ? 4 : 2) |
ef0e53ce | 234 | #define MIN_UNITS_PER_WORD 2 |
07aae5c2 | 235 | |
f9477efd KH |
236 | #define SHORT_TYPE_SIZE 16 |
237 | #define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16) | |
238 | #define LONG_TYPE_SIZE 32 | |
5d39821d | 239 | #define LONG_LONG_TYPE_SIZE 64 |
f9477efd KH |
240 | #define FLOAT_TYPE_SIZE 32 |
241 | #define DOUBLE_TYPE_SIZE 32 | |
242 | #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE | |
07aae5c2 | 243 | |
f9477efd | 244 | #define MAX_FIXED_MODE_SIZE 32 |
07aae5c2 SC |
245 | |
246 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
a1616dd9 | 247 | #define PARM_BOUNDARY (TARGET_H8300H || TARGET_H8300S ? 32 : 16) |
07aae5c2 SC |
248 | |
249 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
250 | #define FUNCTION_BOUNDARY 16 | |
251 | ||
252 | /* Alignment of field after `int : 0' in a structure. */ | |
a6cc0d48 DE |
253 | /* One can argue this should be 32 for -mint32, but since 32 bit ints only |
254 | need 16 bit alignment, this is left as is so that -mint32 doesn't change | |
255 | structure layouts. */ | |
7bc8cb2b | 256 | #define EMPTY_FIELD_BOUNDARY 16 |
07aae5c2 | 257 | |
a6cc0d48 | 258 | /* No data type wants to be aligned rounder than this. |
3db11b5c | 259 | 32 bit values are aligned as such on the H8/300H and H8S for speed. */ |
20d1e666 | 260 | #define BIGGEST_ALIGNMENT \ |
a1616dd9 | 261 | (((TARGET_H8300H || TARGET_H8300S) && ! TARGET_ALIGN_300) ? 32 : 16) |
07aae5c2 | 262 | |
7bc8cb2b DE |
263 | /* The stack goes in 16/32 bit lumps. */ |
264 | #define STACK_BOUNDARY (TARGET_H8300 ? 16 : 32) | |
07aae5c2 SC |
265 | |
266 | /* Define this if move instructions will actually fail to work | |
267 | when given unaligned data. */ | |
7bc8cb2b DE |
268 | /* On the H8/300, longs can be aligned on halfword boundaries, but not |
269 | byte boundaries. */ | |
07aae5c2 SC |
270 | #define STRICT_ALIGNMENT 1 |
271 | \f | |
272 | /* Standard register usage. */ | |
273 | ||
274 | /* Number of actual hardware registers. | |
275 | The hardware registers are assigned numbers for the compiler | |
276 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
277 | ||
278 | All registers that the compiler knows about must be given numbers, | |
f0b6f9a6 | 279 | even those that are not normally considered general registers. |
07aae5c2 | 280 | |
7d9f07f4 | 281 | Reg 9 does not correspond to any hardware register, but instead |
07aae5c2 SC |
282 | appears in the RTL as an argument pointer prior to reload, and is |
283 | eliminated during reloading in favor of either the stack or frame | |
284 | pointer. */ | |
7bc8cb2b | 285 | |
1807b726 | 286 | #define FIRST_PSEUDO_REGISTER 12 |
07aae5c2 SC |
287 | |
288 | /* 1 for registers that have pervasive standard uses | |
7bc8cb2b | 289 | and are not available for the register allocator. */ |
07aae5c2 | 290 | |
ef3f573f KH |
291 | #define FIXED_REGISTERS \ |
292 | /* r0 r1 r2 r3 r4 r5 r6 r7 mac ap rap fp */ \ | |
293 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1 } | |
07aae5c2 SC |
294 | |
295 | /* 1 for registers not available across function calls. | |
296 | These must include the FIXED_REGISTERS and also any | |
297 | registers that can be used without being saved. | |
298 | The latter must include the registers where values are returned | |
299 | and the register where structure-value addresses are passed. | |
300 | Aside from that, you can include as many other registers as you | |
f0b6f9a6 | 301 | like. |
07aae5c2 | 302 | |
2c54abce | 303 | H8 destroys r0,r1,r2,r3. */ |
07aae5c2 | 304 | |
ef3f573f KH |
305 | #define CALL_USED_REGISTERS \ |
306 | /* r0 r1 r2 r3 r4 r5 r6 r7 mac ap rap fp */ \ | |
307 | { 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1 } | |
07aae5c2 | 308 | |
ef3f573f KH |
309 | #define REG_ALLOC_ORDER \ |
310 | /* r0 r1 r2 r3 r4 r5 r6 r7 mac ap rap fp */ \ | |
311 | { 2, 3, 0, 1, 4, 5, 6, 8, 7, 9, 10, 11 } | |
7d9f07f4 | 312 | |
1c11abc4 KH |
313 | #define CONDITIONAL_REGISTER_USAGE \ |
314 | { \ | |
315 | if (!TARGET_MAC) \ | |
316 | fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1; \ | |
7d9f07f4 | 317 | } |
07aae5c2 | 318 | |
07ee3b58 KH |
319 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
320 | h8300_hard_regno_nregs ((REGNO), (MODE)) | |
07aae5c2 | 321 | |
07ee3b58 KH |
322 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
323 | h8300_hard_regno_mode_ok ((REGNO), (MODE)) | |
07aae5c2 SC |
324 | |
325 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
326 | when one has mode MODE1 and one has mode MODE2. | |
327 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
328 | for any hard reg, then this must be 0 for correct output. */ | |
c283e63f KH |
329 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
330 | ((MODE1) == (MODE2) \ | |
331 | || (((MODE1) == QImode || (MODE1) == HImode \ | |
332 | || ((TARGET_H8300H || TARGET_H8300S) && (MODE1) == SImode)) \ | |
333 | && ((MODE2) == QImode || (MODE2) == HImode \ | |
334 | || ((TARGET_H8300H || TARGET_H8300S) && (MODE2) == SImode)))) | |
07aae5c2 | 335 | |
c87ec0ba NY |
336 | /* A C expression that is nonzero if hard register NEW_REG can be |
337 | considered for use as a rename register for OLD_REG register */ | |
338 | ||
339 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ | |
340 | h8300_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
341 | ||
07aae5c2 SC |
342 | /* Specify the registers used for certain standard purposes. |
343 | The values of these macros are register numbers. */ | |
344 | ||
345 | /* H8/300 pc is not overloaded on a register. */ | |
7bc8cb2b | 346 | |
07aae5c2 SC |
347 | /*#define PC_REGNUM 15*/ |
348 | ||
349 | /* Register to use for pushing function arguments. */ | |
72431aef | 350 | #define STACK_POINTER_REGNUM SP_REG |
07aae5c2 | 351 | |
1807b726 KH |
352 | /* Base register for access to local variables of the function. */ |
353 | #define HARD_FRAME_POINTER_REGNUM HFP_REG | |
354 | ||
07aae5c2 | 355 | /* Base register for access to local variables of the function. */ |
72431aef | 356 | #define FRAME_POINTER_REGNUM FP_REG |
07aae5c2 SC |
357 | |
358 | /* Value should be nonzero if functions must have frame pointers. | |
359 | Zero means the frame pointer need not be set up (and parms | |
360 | may be accessed via the stack pointer) in functions that seem suitable. | |
361 | This is computed in `reload', in reload1.c. */ | |
362 | #define FRAME_POINTER_REQUIRED 0 | |
363 | ||
364 | /* Base register for access to arguments of the function. */ | |
1c11abc4 | 365 | #define ARG_POINTER_REGNUM AP_REG |
07aae5c2 SC |
366 | |
367 | /* Register in which static-chain is passed to a function. */ | |
1c11abc4 | 368 | #define STATIC_CHAIN_REGNUM SC_REG |
1aae372e JL |
369 | |
370 | /* Fake register that holds the address on the stack of the | |
371 | current function's return address. */ | |
1c11abc4 | 372 | #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG |
1aae372e JL |
373 | |
374 | /* A C expression whose value is RTL representing the value of the return | |
375 | address for the frame COUNT steps up from the current frame. | |
376 | FRAMEADDR is already the frame pointer of the COUNT frame, assuming | |
377 | a stack layout with the frame pointer as the first saved register. */ | |
378 | #define RETURN_ADDR_RTX(COUNT, FRAME) h8300_return_addr_rtx ((COUNT), (FRAME)) | |
07aae5c2 SC |
379 | \f |
380 | /* Define the classes of registers for register constraints in the | |
381 | machine description. Also define ranges of constants. | |
382 | ||
383 | One of the classes must always be named ALL_REGS and include all hard regs. | |
384 | If there is more than one class, another class must be named NO_REGS | |
385 | and contain no registers. | |
386 | ||
387 | The name GENERAL_REGS must be the name of a class (or an alias for | |
388 | another name such as ALL_REGS). This is the class of registers | |
389 | that is allowed by "g" or "r" in a register constraint. | |
390 | Also, registers outside this class are allocated only when | |
391 | instructions express preferences for them. | |
392 | ||
393 | The classes must be numbered in nondecreasing order; that is, | |
394 | a larger-numbered class must never be contained completely | |
395 | in a smaller-numbered class. | |
396 | ||
397 | For any two classes, it is very desirable that there be another | |
398 | class that represents their union. */ | |
07e4d94e | 399 | |
269c14e1 | 400 | enum reg_class { |
7d9f07f4 | 401 | NO_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES |
269c14e1 | 402 | }; |
07aae5c2 | 403 | |
2918c993 | 404 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
07aae5c2 | 405 | |
ed168e45 | 406 | /* Give names of register classes as strings for dump file. */ |
07aae5c2 SC |
407 | |
408 | #define REG_CLASS_NAMES \ | |
7d9f07f4 | 409 | { "NO_REGS", "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" } |
07aae5c2 SC |
410 | |
411 | /* Define which registers fit in which classes. | |
412 | This is an initializer for a vector of HARD_REG_SET | |
413 | of length N_REG_CLASSES. */ | |
414 | ||
f9477efd | 415 | #define REG_CLASS_CONTENTS \ |
441d04c6 | 416 | { {0}, /* No regs */ \ |
ef3f573f | 417 | {0xeff}, /* GENERAL_REGS */ \ |
8bd06267 | 418 | {0x100}, /* MAC_REGS */ \ |
ef3f573f | 419 | {0xfff}, /* ALL_REGS */ \ |
07aae5c2 SC |
420 | } |
421 | ||
7bc8cb2b DE |
422 | /* The same information, inverted: |
423 | Return the class number of the smallest class containing | |
424 | reg number REGNO. This could be a conditional expression | |
7d9f07f4 | 425 | or could index an array. */ |
bd93f126 | 426 | |
39ea5704 | 427 | #define REGNO_REG_CLASS(REGNO) (REGNO != MAC_REG ? GENERAL_REGS : MAC_REGS) |
07aae5c2 SC |
428 | |
429 | /* The class value for index registers, and the one for base regs. */ | |
430 | ||
431 | #define INDEX_REG_CLASS NO_REGS | |
432 | #define BASE_REG_CLASS GENERAL_REGS | |
433 | ||
f0b6f9a6 | 434 | /* Get reg_class from a letter such as appears in the machine description. |
7d9f07f4 JL |
435 | |
436 | 'a' is the MAC register. */ | |
07aae5c2 | 437 | |
7d9f07f4 | 438 | #define REG_CLASS_FROM_LETTER(C) ((C) == 'a' ? MAC_REGS : NO_REGS) |
07aae5c2 SC |
439 | |
440 | /* The letters I, J, K, L, M, N, O, P in a register constraint string | |
441 | can be used to stand for particular ranges of immediate operands. | |
442 | This macro defines what the ranges are. | |
443 | C is the letter, and VALUE is a constant value. | |
444 | Return 1 if VALUE is in the range specified by C. */ | |
445 | ||
7bc8cb2b | 446 | #define CONST_OK_FOR_I(VALUE) ((VALUE) == 0) |
8cc5359b | 447 | #define CONST_OK_FOR_J(VALUE) (((VALUE) & 0xff) == 0) |
1a63219b KH |
448 | #define CONST_OK_FOR_L(VALUE) \ |
449 | (TARGET_H8300H || TARGET_H8300S \ | |
450 | ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 4 \ | |
009ac3d3 | 451 | : (VALUE) == 1 || (VALUE) == 2) |
f9d2de4d KH |
452 | #define CONST_OK_FOR_M(VALUE) \ |
453 | ((VALUE) == 1 || (VALUE) == 2) | |
1a63219b KH |
454 | #define CONST_OK_FOR_N(VALUE) \ |
455 | (TARGET_H8300H || TARGET_H8300S \ | |
456 | ? (VALUE) == -1 || (VALUE) == -2 || (VALUE) == -4 \ | |
009ac3d3 | 457 | : (VALUE) == -1 || (VALUE) == -2) |
f9d2de4d KH |
458 | #define CONST_OK_FOR_O(VALUE) \ |
459 | ((VALUE) == -1 || (VALUE) == -2) | |
7bc8cb2b | 460 | |
1a63219b KH |
461 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
462 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \ | |
8cc5359b | 463 | (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \ |
1a63219b | 464 | (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \ |
f9d2de4d | 465 | (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \ |
1a63219b | 466 | (C) == 'N' ? CONST_OK_FOR_N (VALUE) : \ |
f9d2de4d | 467 | (C) == 'O' ? CONST_OK_FOR_O (VALUE) : \ |
07aae5c2 SC |
468 | 0) |
469 | ||
470 | /* Similar, but for floating constants, and defining letters G and H. | |
f0b6f9a6 KH |
471 | Here VALUE is the CONST_DOUBLE rtx itself. |
472 | ||
7bc8cb2b | 473 | `G' is a floating-point zero. */ |
07aae5c2 | 474 | |
1a63219b | 475 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
fad37371 | 476 | ((C) == 'G' ? (VALUE) == CONST0_RTX (SFmode) \ |
07aae5c2 SC |
477 | : 0) |
478 | ||
479 | /* Given an rtx X being reloaded into a reg required to be | |
480 | in class CLASS, return the class of reg to actually use. | |
481 | In general this is just CLASS; but on some machines | |
482 | in some cases it is preferable to use a more restrictive class. */ | |
7bc8cb2b | 483 | |
f48f56b1 | 484 | #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) |
07aae5c2 SC |
485 | |
486 | /* Return the maximum number of consecutive registers | |
487 | needed to represent mode MODE in a register of class CLASS. */ | |
488 | ||
7bc8cb2b DE |
489 | /* On the H8, this is the size of MODE in words. */ |
490 | ||
07aae5c2 SC |
491 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
492 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
493 | ||
f0b6f9a6 | 494 | /* Any SI register-to-register move may need to be reloaded, |
07aae5c2 SC |
495 | so define REGISTER_MOVE_COST to be > 2 so that reload never |
496 | shortcuts. */ | |
7bc8cb2b | 497 | |
cf011243 | 498 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
7d9f07f4 | 499 | (CLASS1 == MAC_REGS || CLASS2 == MAC_REGS ? 6 : 3) |
07aae5c2 SC |
500 | \f |
501 | /* Stack layout; function entry, exit and calling. */ | |
502 | ||
503 | /* Define this if pushing a word on the stack | |
504 | makes the stack pointer a smaller address. */ | |
7bc8cb2b | 505 | |
07aae5c2 SC |
506 | #define STACK_GROWS_DOWNWARD |
507 | ||
508 | /* Define this if the nominal address of the stack frame | |
509 | is at the high-address end of the local variables; | |
510 | that is, each additional local variable allocated | |
511 | goes at a more negative offset in the frame. */ | |
7bc8cb2b | 512 | |
07aae5c2 SC |
513 | #define FRAME_GROWS_DOWNWARD |
514 | ||
515 | /* Offset within stack frame to start allocating local variables at. | |
516 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
517 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
518 | of the first local allocated. */ | |
7bc8cb2b | 519 | |
07aae5c2 SC |
520 | #define STARTING_FRAME_OFFSET 0 |
521 | ||
522 | /* If we generate an insn to push BYTES bytes, | |
523 | this says how many the stack pointer really advances by. | |
524 | ||
525 | On the H8/300, @-sp really pushes a byte if you ask it to - but that's | |
526 | dangerous, so we claim that it always pushes a word, then we catch | |
7bc8cb2b | 527 | the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output. |
07aae5c2 | 528 | |
1120a1d3 KH |
529 | On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4 |
530 | and doing a similar thing. */ | |
07aae5c2 | 531 | |
7bc8cb2b | 532 | #define PUSH_ROUNDING(BYTES) \ |
1120a1d3 | 533 | (((BYTES) + PARM_BOUNDARY / 8 - 1) & -PARM_BOUNDARY / 8) |
7bc8cb2b DE |
534 | |
535 | /* Offset of first parameter from the argument pointer register value. */ | |
07aae5c2 SC |
536 | /* Is equal to the size of the saved fp + pc, even if an fp isn't |
537 | saved since the value is used before we know. */ | |
7bc8cb2b | 538 | |
07aae5c2 SC |
539 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
540 | ||
541 | /* Value is the number of bytes of arguments automatically | |
542 | popped when returning from a subroutine call. | |
8b109b37 | 543 | FUNDECL is the declaration node of the function (as a tree), |
07aae5c2 SC |
544 | FUNTYPE is the data type of the function (as a tree), |
545 | or for a library call it is an identifier node for the subroutine name. | |
546 | SIZE is the number of bytes of arguments passed on the stack. | |
547 | ||
7bc8cb2b DE |
548 | On the H8 the return does not pop anything. */ |
549 | ||
f48f56b1 | 550 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 |
07aae5c2 SC |
551 | |
552 | /* Definitions for register eliminations. | |
553 | ||
554 | This is an array of structures. Each structure initializes one pair | |
555 | of eliminable registers. The "from" register number is given first, | |
556 | followed by "to". Eliminations of the same "from" register are listed | |
557 | in order of preference. | |
558 | ||
7e920754 KH |
559 | We have three registers that can be eliminated on the h8300. |
560 | First, the frame pointer register can often be eliminated in favor | |
561 | of the stack pointer register. Secondly, the argument pointer | |
562 | register and the return address pointer register are always | |
563 | eliminated; they are replaced with either the stack or frame | |
564 | pointer. */ | |
7bc8cb2b | 565 | |
1807b726 KH |
566 | #define ELIMINABLE_REGS \ |
567 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
568 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
569 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
570 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
571 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
572 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
07aae5c2 | 573 | |
7bc8cb2b DE |
574 | /* Given FROM and TO register numbers, say whether this elimination is allowed. |
575 | Frame pointer elimination is automatically handled. | |
576 | ||
577 | For the h8300, if frame pointer elimination is being done, we would like to | |
1aae372e | 578 | convert ap and rp into sp, not fp. |
7bc8cb2b DE |
579 | |
580 | All other eliminations are valid. */ | |
581 | ||
07aae5c2 | 582 | #define CAN_ELIMINATE(FROM, TO) \ |
616dc555 | 583 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) |
07aae5c2 SC |
584 | |
585 | /* Define the offset between two registers, one to be eliminated, and the other | |
586 | its replacement, at the start of a routine. */ | |
7bc8cb2b | 587 | |
d7af42bc KH |
588 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
589 | ((OFFSET) = h8300_initial_elimination_offset ((FROM), (TO))) | |
07aae5c2 SC |
590 | |
591 | /* Define how to find the value returned by a function. | |
592 | VALTYPE is the data type of the value (as a tree). | |
593 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
f0b6f9a6 KH |
594 | otherwise, FUNC is 0. |
595 | ||
7bc8cb2b DE |
596 | On the H8 the return value is in R0/R1. */ |
597 | ||
07aae5c2 | 598 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
ef3b9941 | 599 | gen_rtx_REG (TYPE_MODE (VALTYPE), R0_REG) |
07aae5c2 SC |
600 | |
601 | /* Define how to find the value returned by a library function | |
602 | assuming the value has mode MODE. */ | |
603 | ||
1120a1d3 | 604 | /* On the H8 the return value is in R0/R1. */ |
7bc8cb2b | 605 | |
07aae5c2 | 606 | #define LIBCALL_VALUE(MODE) \ |
a1dce8d1 | 607 | gen_rtx_REG (MODE, R0_REG) |
07aae5c2 SC |
608 | |
609 | /* 1 if N is a possible register number for a function value. | |
7bc8cb2b DE |
610 | On the H8, R0 is the only register thus used. */ |
611 | ||
ef3b9941 | 612 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == R0_REG) |
07aae5c2 SC |
613 | |
614 | /* Define this if PCC uses the nonreentrant convention for returning | |
615 | structure and union values. */ | |
7bc8cb2b DE |
616 | |
617 | /*#define PCC_STATIC_STRUCT_RETURN*/ | |
07aae5c2 SC |
618 | |
619 | /* 1 if N is a possible register number for function argument passing. | |
7bc8cb2b | 620 | On the H8, no registers are used in this way. */ |
7bc8cb2b | 621 | |
3b7d443c | 622 | #define FUNCTION_ARG_REGNO_P(N) (TARGET_QUICKCALL ? N < 3 : 0) |
07aae5c2 | 623 | |
07aae5c2 SC |
624 | /* When defined, the compiler allows registers explicitly used in the |
625 | rtl to be used as spill registers but prevents the compiler from | |
9bf7ec4e | 626 | extending the lifetime of these registers. */ |
7bc8cb2b | 627 | |
2922fe9e | 628 | #define SMALL_REGISTER_CLASSES 1 |
07aae5c2 SC |
629 | \f |
630 | /* Define a data type for recording info about an argument list | |
631 | during the scan of that argument list. This data type should | |
7bc8cb2b | 632 | hold all necessary information about the function itself |
07aae5c2 SC |
633 | and about the args processed so far, enough to enable macros |
634 | such as FUNCTION_ARG to determine where the next arg should go. | |
635 | ||
1120a1d3 KH |
636 | On the H8/300, this is a two item struct, the first is the number |
637 | of bytes scanned so far and the second is the rtx of the called | |
638 | library function if any. */ | |
07aae5c2 SC |
639 | |
640 | #define CUMULATIVE_ARGS struct cum_arg | |
07e4d94e KH |
641 | struct cum_arg |
642 | { | |
643 | int nbytes; | |
644 | struct rtx_def *libcall; | |
645 | }; | |
07aae5c2 SC |
646 | |
647 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
648 | for a call to a function whose data type is FNTYPE. | |
649 | For a library call, FNTYPE is 0. | |
650 | ||
651 | On the H8/300, the offset starts at 0. */ | |
7bc8cb2b | 652 | |
0f6937fe | 653 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
7bc8cb2b | 654 | ((CUM).nbytes = 0, (CUM).libcall = LIBNAME) |
07aae5c2 SC |
655 | |
656 | /* Update the data in CUM to advance over an argument | |
657 | of mode MODE and data type TYPE. | |
7bc8cb2b | 658 | (TYPE is null for libcalls where that information may not be available.) */ |
07aae5c2 | 659 | |
1a63219b KH |
660 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
661 | ((CUM).nbytes += ((MODE) != BLKmode \ | |
7bc8cb2b DE |
662 | ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD \ |
663 | : (int_size_in_bytes (TYPE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)) | |
07aae5c2 SC |
664 | |
665 | /* Define where to put the arguments to a function. | |
666 | Value is zero to push the argument on the stack, | |
667 | or a hard register in which to store the argument. | |
668 | ||
669 | MODE is the argument's machine mode. | |
670 | TYPE is the data type of the argument (as a tree). | |
671 | This is null for libcalls where that information may | |
672 | not be available. | |
673 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
674 | the preceding args and about the function being called. | |
675 | NAMED is nonzero if this argument is a named parameter | |
676 | (otherwise it is an extra parameter matching an ellipsis). */ | |
677 | ||
7bc8cb2b DE |
678 | /* On the H8/300 all normal args are pushed, unless -mquickcall in which |
679 | case the first 3 arguments are passed in registers. | |
680 | See function `function_arg'. */ | |
07aae5c2 | 681 | |
07aae5c2 SC |
682 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
683 | function_arg (&CUM, MODE, TYPE, NAMED) | |
684 | ||
07aae5c2 SC |
685 | /* Output assembler code to FILE to increment profiler label # LABELNO |
686 | for profiling a function entry. */ | |
687 | ||
7bc8cb2b DE |
688 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
689 | fprintf (FILE, "\t%s\t#LP%d,%s\n\tjsr @mcount\n", \ | |
690 | h8_mov_op, (LABELNO), h8_reg_names[0]); | |
07aae5c2 | 691 | |
07aae5c2 SC |
692 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
693 | the stack pointer does not matter. The value is tested only in | |
694 | functions that have frame pointers. | |
695 | No definition is equivalent to always zero. */ | |
696 | ||
697 | #define EXIT_IGNORE_STACK 0 | |
698 | ||
9e56a932 KH |
699 | /* We emit the entire trampoline with INITIALIZE_TRAMPOLINE. |
700 | Depending on the pointer size, we use a different trampoline. | |
7bc8cb2b | 701 | |
9e56a932 | 702 | Pmode == HImode |
7bc8cb2b | 703 | vvvv context |
59d7c857 | 704 | 1 0000 7903xxxx mov.w #0x1234,r3 |
8bd06267 | 705 | 2 0004 5A00xxxx jmp @0x1234 |
7bc8cb2b DE |
706 | ^^^^ function |
707 | ||
9e56a932 | 708 | Pmode == SImode |
7bc8cb2b | 709 | vvvvvvvv context |
59d7c857 | 710 | 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 |
8bd06267 | 711 | 3 0006 5Axxxxxx jmp @0x123456 |
7bc8cb2b DE |
712 | ^^^^^^ function |
713 | */ | |
714 | ||
07aae5c2 SC |
715 | /* Length in units of the trampoline for entering a nested function. */ |
716 | ||
32da7865 | 717 | #define TRAMPOLINE_SIZE ((Pmode == HImode) ? 8 : 12) |
07aae5c2 | 718 | |
9e56a932 | 719 | /* Emit RTL insns to build a trampoline. |
07aae5c2 SC |
720 | FNADDR is an RTX for the address of the function's pure code. |
721 | CXT is an RTX for the static chain value for the function. */ | |
722 | ||
3494f1b4 | 723 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
9e56a932 KH |
724 | do \ |
725 | { \ | |
726 | if (Pmode == HImode) \ | |
727 | { \ | |
728 | emit_move_insn (gen_rtx_MEM (HImode, (TRAMP)), GEN_INT (0x7903)); \ | |
729 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 2)), \ | |
730 | (CXT)); \ | |
731 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 4)), \ | |
732 | GEN_INT (0x5a00)); \ | |
733 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 6)), \ | |
734 | (FNADDR)); \ | |
735 | } \ | |
736 | else \ | |
737 | { \ | |
738 | rtx tem = gen_reg_rtx (Pmode); \ | |
739 | \ | |
740 | emit_move_insn (gen_rtx_MEM (HImode, (TRAMP)), GEN_INT (0x7a03)); \ | |
741 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 2)), \ | |
742 | (CXT)); \ | |
743 | emit_move_insn (tem, (FNADDR)); \ | |
744 | emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); \ | |
745 | emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); \ | |
746 | emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 6)), \ | |
747 | tem); \ | |
748 | } \ | |
749 | } \ | |
750 | while (0) | |
07aae5c2 | 751 | \f |
7bc8cb2b | 752 | /* Addressing modes, and classification of registers for them. */ |
07aae5c2 | 753 | |
940da324 | 754 | #define HAVE_POST_INCREMENT 1 |
940da324 | 755 | #define HAVE_PRE_DECREMENT 1 |
07aae5c2 SC |
756 | |
757 | /* Macros to check register numbers against specific register classes. */ | |
758 | ||
759 | /* These assume that REGNO is a hard or pseudo reg number. | |
760 | They give nonzero only if REGNO is a hard reg of the suitable class | |
761 | or a pseudo reg currently allocated to a suitable hard reg. | |
762 | Since they use reg_renumber, they are safe only once reg_renumber | |
763 | has been allocated, which happens in local-alloc.c. */ | |
07e4d94e | 764 | |
7bc8cb2b | 765 | #define REGNO_OK_FOR_INDEX_P(regno) 0 |
07aae5c2 | 766 | |
d60004ee KH |
767 | #define REGNO_OK_FOR_BASE_P(regno) \ |
768 | (((regno) < FIRST_PSEUDO_REGISTER && regno != MAC_REG) \ | |
769 | || reg_renumber[regno] >= 0) | |
07aae5c2 SC |
770 | \f |
771 | /* Maximum number of registers that can appear in a valid memory address. */ | |
772 | ||
773 | #define MAX_REGS_PER_ADDRESS 1 | |
774 | ||
775 | /* 1 if X is an rtx for a constant that is a valid address. */ | |
776 | ||
1a63219b | 777 | #define CONSTANT_ADDRESS_P(X) \ |
7bc8cb2b DE |
778 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ |
779 | || (GET_CODE (X) == CONST_INT \ | |
780 | /* We handle signed and unsigned offsets here. */ \ | |
781 | && INTVAL (X) > (TARGET_H8300 ? -0x10000 : -0x1000000) \ | |
782 | && INTVAL (X) < (TARGET_H8300 ? 0x10000 : 0x1000000)) \ | |
eb8a8ec4 | 783 | || (GET_CODE (X) == HIGH || GET_CODE (X) == CONST)) |
07aae5c2 SC |
784 | |
785 | /* Nonzero if the constant value X is a legitimate general operand. | |
786 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
787 | ||
d0022200 | 788 | #define LEGITIMATE_CONSTANT_P(X) (h8300_legitimate_constant_p (X)) |
07aae5c2 SC |
789 | |
790 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
791 | and check its validity for a certain class. | |
792 | We have two alternate definitions for each of them. | |
793 | The usual definition accepts all pseudo regs; the other rejects | |
794 | them unless they have been allocated suitable hard regs. | |
795 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
796 | ||
797 | Most source files want to accept pseudo regs in the hope that | |
798 | they will get allocated to the class that the insn wants them to be in. | |
799 | Source files for reload pass need to be strict. | |
800 | After reload, it makes no difference, since pseudo regs have | |
801 | been eliminated by then. */ | |
802 | ||
ca04c5a9 KH |
803 | /* Non-strict versions. */ |
804 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) 0 | |
805 | /* Don't use REGNO_OK_FOR_BASE_P here because it uses reg_renumber. */ | |
806 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ | |
2dca8ddb | 807 | (REGNO (X) >= FIRST_PSEUDO_REGISTER || REGNO (X) != MAC_REG) |
ca04c5a9 KH |
808 | |
809 | /* Strict versions. */ | |
810 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
811 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
812 | ||
07aae5c2 SC |
813 | #ifndef REG_OK_STRICT |
814 | ||
ca04c5a9 KH |
815 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
816 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
07aae5c2 SC |
817 | |
818 | #else | |
819 | ||
ca04c5a9 KH |
820 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
821 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
07aae5c2 SC |
822 | |
823 | #endif | |
7bc8cb2b | 824 | |
c59ff527 KH |
825 | /* Extra constraints. */ |
826 | ||
be1e06df KH |
827 | #define OK_FOR_R(OP) \ |
828 | (GET_CODE (OP) == CONST_INT \ | |
829 | ? !h8300_shift_needs_scratch_p (INTVAL (OP), QImode) \ | |
830 | : 0) | |
831 | ||
832 | #define OK_FOR_S(OP) \ | |
833 | (GET_CODE (OP) == CONST_INT \ | |
834 | ? !h8300_shift_needs_scratch_p (INTVAL (OP), HImode) \ | |
835 | : 0) | |
836 | ||
837 | #define OK_FOR_T(OP) \ | |
838 | (GET_CODE (OP) == CONST_INT \ | |
839 | ? !h8300_shift_needs_scratch_p (INTVAL (OP), SImode) \ | |
840 | : 0) | |
841 | ||
0a02170f | 842 | /* 'U' if valid for a bset destination; |
c59ff527 KH |
843 | i.e. a register, register indirect, or the eightbit memory region |
844 | (a SYMBOL_REF with an SYMBOL_REF_FLAG set). | |
c05330a9 | 845 | |
3db11b5c | 846 | On the H8S 'U' can also be a 16bit or 32bit absolute. */ |
cda4bd43 KH |
847 | #define OK_FOR_U(OP) \ |
848 | ((GET_CODE (OP) == REG && REG_OK_FOR_BASE_P (OP)) \ | |
849 | || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ | |
850 | && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \ | |
851 | || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
9675a91e | 852 | && TARGET_H8300S) \ |
f248423a KH |
853 | || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST \ |
854 | && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \ | |
855 | && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == SYMBOL_REF \ | |
856 | && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT \ | |
920e86b8 KH |
857 | && (TARGET_H8300S \ |
858 | || SYMBOL_REF_FLAG (XEXP (XEXP (XEXP (OP, 0), 0), 0)))) \ | |
9f9f0e4f | 859 | || (GET_CODE (OP) == MEM \ |
7c143ed2 | 860 | && h8300_eightbit_constant_address_p (XEXP (OP, 0))) \ |
cda4bd43 | 861 | || (GET_CODE (OP) == MEM && TARGET_H8300S \ |
e8205901 | 862 | && GET_CODE (XEXP (OP, 0)) == CONST_INT)) |
07e4d94e | 863 | |
c59ff527 | 864 | #define EXTRA_CONSTRAINT(OP, C) \ |
be1e06df KH |
865 | ((C) == 'R' ? OK_FOR_R (OP) : \ |
866 | (C) == 'S' ? OK_FOR_S (OP) : \ | |
867 | (C) == 'T' ? OK_FOR_T (OP) : \ | |
868 | (C) == 'U' ? OK_FOR_U (OP) : \ | |
c59ff527 | 869 | 0) |
07aae5c2 | 870 | \f |
d0022200 KH |
871 | #ifndef REG_OK_STRICT |
872 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
873 | do \ | |
874 | { \ | |
875 | if (h8300_legitimate_address_p ((X), 0)) \ | |
876 | goto ADDR; \ | |
877 | } \ | |
878 | while (0) | |
879 | #else | |
880 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
881 | do \ | |
882 | { \ | |
883 | if (h8300_legitimate_address_p ((X), 1)) \ | |
884 | goto ADDR; \ | |
885 | } \ | |
886 | while (0) | |
887 | #endif | |
07aae5c2 | 888 | \f |
07aae5c2 SC |
889 | /* Go to LABEL if ADDR (a legitimate address expression) |
890 | has an effect that depends on the machine mode it is used for. | |
891 | ||
892 | On the H8/300, the predecrement and postincrement address depend thus | |
18543a22 | 893 | (the amount of decrement or increment being the length of the operand). */ |
07aae5c2 | 894 | |
f48f56b1 | 895 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
7bc8cb2b | 896 | if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL; |
07aae5c2 SC |
897 | \f |
898 | /* Specify the machine mode that this machine uses | |
899 | for the index in the tablejump instruction. */ | |
7bc8cb2b | 900 | #define CASE_VECTOR_MODE Pmode |
07aae5c2 | 901 | |
07aae5c2 SC |
902 | /* Define this as 1 if `char' should by default be signed; else as 0. |
903 | ||
904 | On the H8/300, sign extension is expensive, so we'll say that chars | |
905 | are unsigned. */ | |
906 | #define DEFAULT_SIGNED_CHAR 0 | |
907 | ||
908 | /* This flag, if defined, says the same insns that convert to a signed fixnum | |
909 | also convert validly to an unsigned one. */ | |
910 | #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
911 | ||
912 | /* Max number of bytes we can move from memory to memory | |
913 | in one reasonably fast instruction. */ | |
a1616dd9 | 914 | #define MOVE_MAX (TARGET_H8300H || TARGET_H8300S ? 4 : 2) |
7bc8cb2b | 915 | #define MAX_MOVE_MAX 4 |
07aae5c2 | 916 | |
07aae5c2 SC |
917 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
918 | #define SLOW_BYTE_ACCESS TARGET_SLOWBYTE | |
919 | ||
920 | /* Define if shifts truncate the shift count | |
921 | which implies one can omit a sign-extension or zero-extension | |
922 | of a shift count. */ | |
923 | /* #define SHIFT_COUNT_TRUNCATED */ | |
924 | ||
925 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
926 | is done just by pretending it is already truncated. */ | |
927 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
928 | ||
929 | /* Specify the machine mode that pointers have. | |
930 | After generation of rtl, the compiler makes no further distinction | |
931 | between pointers and any other objects of this machine mode. */ | |
39ba95b5 VK |
932 | #define Pmode \ |
933 | ((TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE ? SImode : HImode) | |
7bc8cb2b DE |
934 | |
935 | /* ANSI C types. | |
46eefac4 | 936 | We use longs for the H8/300H and the H8S because ints can be 16 or 32. |
7bc8cb2b | 937 | GCC requires SIZE_TYPE to be the same size as pointers. */ |
39ba95b5 VK |
938 | #define SIZE_TYPE \ |
939 | (TARGET_H8300 || TARGET_NORMAL_MODE ? "unsigned int" : "long unsigned int") | |
940 | #define PTRDIFF_TYPE \ | |
941 | (TARGET_H8300 || TARGET_NORMAL_MODE ? "int" : "long int") | |
942 | ||
943 | #define POINTER_SIZE \ | |
944 | ((TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE ? 32 : 16) | |
07aae5c2 | 945 | |
7bc8cb2b DE |
946 | #define WCHAR_TYPE "short unsigned int" |
947 | #define WCHAR_TYPE_SIZE 16 | |
07aae5c2 SC |
948 | |
949 | /* A function address in a call instruction | |
950 | is a byte address (for indexing purposes) | |
951 | so give the MEM rtx a byte's mode. */ | |
952 | #define FUNCTION_MODE QImode | |
953 | ||
7bc8cb2b DE |
954 | #define BRANCH_COST 0 |
955 | ||
07aae5c2 | 956 | /* Tell final.c how to eliminate redundant test instructions. */ |
7bc8cb2b DE |
957 | |
958 | /* Here we define machine-dependent flags and fields in cc_status | |
18543a22 | 959 | (see `conditions.h'). No extra ones are needed for the h8300. */ |
7bc8cb2b DE |
960 | |
961 | /* Store in cc_status the expressions | |
962 | that the condition codes will describe | |
963 | after execution of an instruction whose pattern is EXP. | |
964 | Do not alter them if the instruction would not alter the cc's. */ | |
965 | ||
f48f56b1 | 966 | #define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc (EXP, INSN) |
7bc8cb2b | 967 | |
269c14e1 DE |
968 | /* The add insns don't set overflow in a usable way. */ |
969 | #define CC_OVERFLOW_UNUSABLE 01000 | |
f48f56b1 | 970 | /* The mov,and,or,xor insns don't set carry. That's OK though as the |
269c14e1 DE |
971 | Z bit is all we need when doing unsigned comparisons on the result of |
972 | these insns (since they're always with 0). However, conditions.h has | |
973 | CC_NO_OVERFLOW defined for this purpose. Rename it to something more | |
974 | understandable. */ | |
975 | #define CC_NO_CARRY CC_NO_OVERFLOW | |
07aae5c2 SC |
976 | \f |
977 | /* Control the assembler format that we output. */ | |
978 | ||
07aae5c2 SC |
979 | /* Output to assembler file text saying following lines |
980 | may contain character constants, extra white space, comments, etc. */ | |
981 | ||
7bc8cb2b | 982 | #define ASM_APP_ON "; #APP\n" |
07aae5c2 SC |
983 | |
984 | /* Output to assembler file text saying following lines | |
985 | no longer contain unusual constructs. */ | |
986 | ||
7bc8cb2b | 987 | #define ASM_APP_OFF "; #NO_APP\n" |
07aae5c2 | 988 | |
7bc8cb2b | 989 | #define FILE_ASM_OP "\t.file\n" |
7bc8cb2b DE |
990 | |
991 | /* The assembler op to get a word, 2 bytes for the H8/300, 4 for H8/300H. */ | |
39ba95b5 VK |
992 | #define ASM_WORD_OP \ |
993 | (TARGET_H8300 || TARGET_NORMAL_MODE ? "\t.word\t" : "\t.long\t") | |
07aae5c2 | 994 | |
07aae5c2 SC |
995 | #define TEXT_SECTION_ASM_OP "\t.section .text" |
996 | #define DATA_SECTION_ASM_OP "\t.section .data" | |
7bc8cb2b | 997 | #define BSS_SECTION_ASM_OP "\t.section .bss" |
7bc8cb2b | 998 | |
07e4d94e | 999 | #undef DO_GLOBAL_CTORS_BODY |
7bc8cb2b DE |
1000 | #define DO_GLOBAL_CTORS_BODY \ |
1001 | { \ | |
4cd0866d KH |
1002 | extern func_ptr __ctors[]; \ |
1003 | extern func_ptr __ctors_end[]; \ | |
1004 | func_ptr *p; \ | |
c1fe41cb | 1005 | for (p = __ctors_end; p > __ctors; ) \ |
7bc8cb2b | 1006 | { \ |
c1fe41cb | 1007 | (*--p)(); \ |
7bc8cb2b | 1008 | } \ |
07e4d94e | 1009 | } |
7bc8cb2b | 1010 | |
07e4d94e | 1011 | #undef DO_GLOBAL_DTORS_BODY |
2cc07db4 | 1012 | #define DO_GLOBAL_DTORS_BODY \ |
7bc8cb2b | 1013 | { \ |
4cd0866d KH |
1014 | extern func_ptr __dtors[]; \ |
1015 | extern func_ptr __dtors_end[]; \ | |
1016 | func_ptr *p; \ | |
7bc8cb2b DE |
1017 | for (p = __dtors; p < __dtors_end; p++) \ |
1018 | { \ | |
1019 | (*p)(); \ | |
1020 | } \ | |
07e4d94e | 1021 | } |
07aae5c2 SC |
1022 | |
1023 | /* How to refer to registers in assembler output. | |
1024 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1025 | ||
1026 | #define REGISTER_NAMES \ | |
1807b726 | 1027 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "mac", "ap", "rap", "fp" } |
3511415d | 1028 | |
8b05263d JL |
1029 | #define ADDITIONAL_REGISTER_NAMES \ |
1030 | { {"er0", 0}, {"er1", 1}, {"er2", 2}, {"er3", 3}, {"er4", 4}, \ | |
1031 | {"er5", 5}, {"er6", 6}, {"er7", 7}, {"r7", 7} } | |
07aae5c2 | 1032 | |
07e4d94e | 1033 | #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) |
07aae5c2 | 1034 | |
506a61b1 KG |
1035 | /* Globalizing directive for a label. */ |
1036 | #define GLOBAL_ASM_OP "\t.global " | |
07aae5c2 | 1037 | |
7bc8cb2b | 1038 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ |
da1775d6 | 1039 | ASM_OUTPUT_LABEL (FILE, NAME) |
07aae5c2 | 1040 | |
9bf7ec4e | 1041 | /* The prefix to add to user-visible assembler symbols. */ |
fa8cc22d | 1042 | |
4e0c8ad2 | 1043 | #define USER_LABEL_PREFIX "_" |
07aae5c2 | 1044 | |
07aae5c2 SC |
1045 | /* This is how to store into the string LABEL |
1046 | the symbol_ref name of an internal numbered label where | |
1047 | PREFIX is the class of label and NUM is the number within the class. | |
cb713a8d | 1048 | This is suitable for output with `assemble_name'. |
07aae5c2 | 1049 | |
4977bab6 ZW |
1050 | N.B.: The h8300.md branch_true and branch_false patterns also know |
1051 | how to generate internal labels. */ | |
07aae5c2 | 1052 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ |
74eda121 | 1053 | sprintf (LABEL, "*.%s%lu", PREFIX, (unsigned long)(NUM)) |
07aae5c2 | 1054 | |
07aae5c2 SC |
1055 | /* This is how to output an insn to push a register on the stack. |
1056 | It need not be very fast code. */ | |
7bc8cb2b DE |
1057 | |
1058 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ | |
1059 | fprintf (FILE, "\t%s\t%s\n", h8_push_op, h8_reg_names[REGNO]) | |
07aae5c2 SC |
1060 | |
1061 | /* This is how to output an insn to pop a register from the stack. | |
1062 | It need not be very fast code. */ | |
07aae5c2 | 1063 | |
f48f56b1 | 1064 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
7bc8cb2b DE |
1065 | fprintf (FILE, "\t%s\t%s\n", h8_pop_op, h8_reg_names[REGNO]) |
1066 | ||
1067 | /* This is how to output an element of a case-vector that is absolute. */ | |
1068 | ||
1069 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
761c70aa | 1070 | fprintf (FILE, "%s.L%d\n", ASM_WORD_OP, VALUE) |
07aae5c2 SC |
1071 | |
1072 | /* This is how to output an element of a case-vector that is relative. */ | |
7bc8cb2b | 1073 | |
33f7f353 | 1074 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
f0ca81d2 | 1075 | fprintf (FILE, "%s.L%d-.L%d\n", ASM_WORD_OP, VALUE, REL) |
07aae5c2 SC |
1076 | |
1077 | /* This is how to output an assembler line | |
1078 | that says to advance the location counter | |
1079 | to a multiple of 2**LOG bytes. */ | |
7bc8cb2b | 1080 | |
f48f56b1 | 1081 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ |
1a63219b | 1082 | if ((LOG) != 0) \ |
3511415d | 1083 | fprintf (FILE, "\t.align %d\n", (LOG)) |
07aae5c2 | 1084 | |
7bc8cb2b | 1085 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ |
58e15542 | 1086 | fprintf (FILE, "\t.space %d\n", (int)(SIZE)) |
07aae5c2 SC |
1087 | |
1088 | /* This says how to output an assembler line | |
1089 | to define a global common symbol. */ | |
7bc8cb2b | 1090 | |
1a63219b KH |
1091 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ |
1092 | ( fputs ("\t.comm ", (FILE)), \ | |
1093 | assemble_name ((FILE), (NAME)), \ | |
74eda121 | 1094 | fprintf ((FILE), ",%lu\n", (unsigned long)(SIZE))) |
07aae5c2 | 1095 | |
f4778f92 DE |
1096 | /* This says how to output the assembler to define a global |
1097 | uninitialized but not common symbol. | |
1098 | Try to use asm_output_bss to implement this macro. */ | |
1099 | ||
1a63219b | 1100 | #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ROUNDED) \ |
fbbc7519 | 1101 | asm_output_bss ((FILE), (DECL), (NAME), (SIZE), (ROUNDED)) |
f4778f92 | 1102 | |
6cdd2721 DD |
1103 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
1104 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
1105 | ||
07aae5c2 SC |
1106 | /* This says how to output an assembler line |
1107 | to define a local common symbol. */ | |
7bc8cb2b | 1108 | |
f48f56b1 | 1109 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ |
07aae5c2 SC |
1110 | ( fputs ("\t.lcomm ", (FILE)), \ |
1111 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 1112 | fprintf ((FILE), ",%d\n", (int)(SIZE))) |
07aae5c2 | 1113 | |
4977bab6 | 1114 | #define ASM_PN_FORMAT "%s___%lu" |
07aae5c2 | 1115 | |
7bc8cb2b | 1116 | /* Print an instruction operand X on file FILE. |
1120a1d3 | 1117 | Look in h8300.c for details. */ |
7bc8cb2b DE |
1118 | |
1119 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
07aae5c2 SC |
1120 | ((CODE) == '#') |
1121 | ||
f48f56b1 | 1122 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
07aae5c2 SC |
1123 | |
1124 | /* Print a memory operand whose address is X, on file FILE. | |
18543a22 | 1125 | This uses a function in h8300.c. */ |
07aae5c2 | 1126 | |
7bc8cb2b | 1127 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
07aae5c2 | 1128 | |
8b97c5f8 | 1129 | /* H8300 specific pragmas. */ |
c58b209a NB |
1130 | #define REGISTER_TARGET_PRAGMAS() \ |
1131 | do \ | |
1132 | { \ | |
1133 | c_register_pragma (0, "saveall", h8300_pr_saveall); \ | |
1134 | c_register_pragma (0, "interrupt", h8300_pr_interrupt); \ | |
1135 | } \ | |
1120a1d3 | 1136 | while (0) |
07aae5c2 | 1137 | |
1120a1d3 KH |
1138 | #define FINAL_PRESCAN_INSN(insn, operand, nop) \ |
1139 | final_prescan_insn (insn, operand, nop) | |
07aae5c2 | 1140 | |
07aae5c2 | 1141 | #define MOVE_RATIO 3 |
8b97c5f8 | 1142 | |
3b1c9927 KH |
1143 | /* Define the codes that are matched by predicates in h8300.c. */ |
1144 | ||
0889116d KH |
1145 | #define PREDICATE_CODES \ |
1146 | {"general_operand_src", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ | |
8fff4fc1 | 1147 | LABEL_REF, SUBREG, REG, MEM}}, \ |
0889116d | 1148 | {"general_operand_dst", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ |
8fff4fc1 | 1149 | LABEL_REF, SUBREG, REG, MEM}}, \ |
0889116d KH |
1150 | {"single_one_operand", {CONST_INT}}, \ |
1151 | {"single_zero_operand", {CONST_INT}}, \ | |
1152 | {"call_insn_operand", {MEM}}, \ | |
1153 | {"small_call_insn_operand", {MEM}}, \ | |
1154 | {"jump_address_operand", {REG, MEM}}, \ | |
1155 | {"two_insn_adds_subs_operand", {CONST_INT}}, \ | |
1156 | {"bit_operand", {REG, SUBREG, MEM}}, \ | |
1157 | {"bit_memory_operand", {MEM}}, \ | |
1158 | {"stack_pointer_operand", {REG}}, \ | |
0889116d KH |
1159 | {"const_int_gt_2_operand", {CONST_INT}}, \ |
1160 | {"const_int_ge_8_operand", {CONST_INT}}, \ | |
1161 | {"const_int_qi_operand", {CONST_INT}}, \ | |
1162 | {"const_int_hi_operand", {CONST_INT}}, \ | |
1163 | {"incdec_operand", {CONST_INT}}, \ | |
1164 | {"bit_operator", {XOR, AND, IOR}}, \ | |
1165 | {"nshift_operator", {ASHIFTRT, LSHIFTRT, ASHIFT}}, \ | |
717d8b71 | 1166 | {"eqne_operator", {EQ, NE}}, \ |
9a2dd2dd | 1167 | {"gtle_operator", {GT, LE, GTU, LEU}}, \ |
b059c02a KH |
1168 | {"gtuleu_operator", {GTU, LEU}}, \ |
1169 | {"iorxor_operator", {IOR, XOR}}, | |
3b1c9927 | 1170 | |
88657302 | 1171 | #endif /* ! GCC_H8300_H */ |