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946730d0 | 1 | /* Definitions of target machine for GNU compiler. AT&T DSP1600. |
e03f5d43 | 2 | Copyright (C) 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002 |
cfb857f1 | 3 | Free Software Foundation, Inc. |
dff06f62 | 4 | Contributed by Michael Collison (collison@isisinc.net). |
946730d0 RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
c30b6330 | 10 | the Free Software Foundation; either version 2, or (at your option) |
946730d0 RK |
11 | any later version. |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
97aadbb9 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
946730d0 | 22 | |
69985118 KG |
23 | extern const char *low_reg_names[]; |
24 | extern const char *text_seg_name; | |
25 | extern const char *rsect_text; | |
26 | extern const char *data_seg_name; | |
27 | extern const char *rsect_data; | |
28 | extern const char *bss_seg_name; | |
29 | extern const char *rsect_bss; | |
30 | extern const char *const_seg_name; | |
31 | extern const char *rsect_const; | |
32 | extern const char *chip_name; | |
33 | extern const char *save_chip_name; | |
946730d0 | 34 | extern struct rtx_def *dsp16xx_compare_op0, *dsp16xx_compare_op1; |
946730d0 RK |
35 | extern struct rtx_def *dsp16xx_addhf3_libcall; |
36 | extern struct rtx_def *dsp16xx_subhf3_libcall; | |
37 | extern struct rtx_def *dsp16xx_mulhf3_libcall; | |
38 | extern struct rtx_def *dsp16xx_divhf3_libcall; | |
39 | extern struct rtx_def *dsp16xx_cmphf3_libcall; | |
40 | extern struct rtx_def *dsp16xx_fixhfhi2_libcall; | |
41 | extern struct rtx_def *dsp16xx_floathihf2_libcall; | |
42 | extern struct rtx_def *dsp16xx_neghf2_libcall; | |
43 | extern struct rtx_def *dsp16xx_umulhi3_libcall; | |
44 | extern struct rtx_def *dsp16xx_mulhi3_libcall; | |
45 | extern struct rtx_def *dsp16xx_udivqi3_libcall; | |
46 | extern struct rtx_def *dsp16xx_udivhi3_libcall; | |
47 | extern struct rtx_def *dsp16xx_divqi3_libcall; | |
48 | extern struct rtx_def *dsp16xx_divhi3_libcall; | |
49 | extern struct rtx_def *dsp16xx_modqi3_libcall; | |
50 | extern struct rtx_def *dsp16xx_modhi3_libcall; | |
51 | extern struct rtx_def *dsp16xx_umodqi3_libcall; | |
52 | extern struct rtx_def *dsp16xx_umodhi3_libcall; | |
53 | ||
54 | extern struct rtx_def *dsp16xx_ashrhi3_libcall; | |
55 | extern struct rtx_def *dsp16xx_ashlhi3_libcall; | |
56 | extern struct rtx_def *dsp16xx_lshrhi3_libcall; | |
57 | ||
946730d0 RK |
58 | /* RUN-TIME TARGET SPECIFICATION */ |
59 | #define DSP16XX 1 | |
60 | ||
61 | /* Name of the AT&T assembler */ | |
62 | ||
63 | #define ASM_PROG "as1600" | |
64 | ||
65 | /* Name of the AT&T linker */ | |
66 | ||
67 | #define LD_PROG "ld1600" | |
68 | ||
69 | /* Define which switches take word arguments */ | |
70 | #define WORD_SWITCH_TAKES_ARG(STR) \ | |
71 | (!strcmp (STR, "ifile") ? 1 : \ | |
72 | 0) | |
73 | ||
74 | #ifdef CC1_SPEC | |
75 | #undef CC1_SPEC | |
76 | #endif | |
dff06f62 MC |
77 | #define CC1_SPEC "%{!O*:-O}" |
78 | ||
79 | #define CPP_SPEC "%{!O*:-D__OPTIMIZE__}" | |
946730d0 RK |
80 | |
81 | /* Define this as a spec to call the AT&T assembler */ | |
82 | ||
83 | #define CROSS_ASM_SPEC "%{!S:as1600 %a %i\n }" | |
84 | ||
85 | /* Define this as a spec to call the AT&T linker */ | |
86 | ||
87 | #define CROSS_LINK_SPEC "%{!c:%{!M:%{!MM:%{!E:%{!S:ld1600 %l %X %{o*} %{m} \ | |
88 | %{r} %{s} %{t} %{u*} %{x}\ | |
a9821774 | 89 | %{!A:%{!nostdlib:%{!nostartfiles:%S}}} %{static:}\ |
a7c508fe | 90 | %{L*} %D %o %{!nostdlib:-le1600 %L -le1600}\ |
a9821774 | 91 | %{!A:%{!nostdlib:%{!nostartfiles:%E}}}\n }}}}}" |
946730d0 RK |
92 | |
93 | /* Nothing complicated here, just link with libc.a under normal | |
94 | circumstances */ | |
95 | #define LIB_SPEC "-lc" | |
96 | ||
bf0e974b | 97 | /* Specify the startup file to link with. */ |
946730d0 RK |
98 | #define STARTFILE_SPEC "%{mmap1:m1_crt0.o%s} \ |
99 | %{mmap2:m2_crt0.o%s} \ | |
100 | %{mmap3:m3_crt0.o%s} \ | |
101 | %{mmap4:m4_crt0.o%s} \ | |
102 | %{!mmap*: %{!ifile*: m4_crt0.o%s} %{ifile*: \ | |
c725bd79 | 103 | %ea -ifile option requires a -map option}}" |
946730d0 RK |
104 | |
105 | /* Specify the end file to link with */ | |
106 | ||
107 | #define ENDFILE_SPEC "%{mmap1:m1_crtn.o%s} \ | |
108 | %{mmap2:m2_crtn.o%s} \ | |
109 | %{mmap3:m3_crtn.o%s} \ | |
110 | %{mmap4:m4_crtn.o%s} \ | |
111 | %{!mmap*: %{!ifile*: m4_crtn.o%s} %{ifile*: \ | |
c725bd79 | 112 | %ea -ifile option requires a -map option}}" |
946730d0 RK |
113 | |
114 | ||
115 | /* Tell gcc where to look for the startfile */ | |
dff06f62 | 116 | /*#define STANDARD_STARTFILE_PREFIX "/d1600/lib"*/ |
946730d0 | 117 | |
dff06f62 MC |
118 | /* Tell gcc where to look for it's executables */ |
119 | /*#define STANDARD_EXEC_PREFIX "/d1600/bin"*/ | |
946730d0 RK |
120 | |
121 | /* Command line options to the AT&T assembler */ | |
dff06f62 | 122 | #define ASM_SPEC "%{V} %{v:%{!V:-V}} %{g*:-g}" |
946730d0 RK |
123 | |
124 | /* Command line options for the AT&T linker */ | |
dff06f62 MC |
125 | |
126 | #define LINK_SPEC "%{V} %{v:%{!V:-V}} %{minit:-i} \ | |
127 | %{!ifile*:%{mmap1:m1_deflt.if%s} \ | |
128 | %{mmap2:m2_deflt.if%s} \ | |
129 | %{mmap3:m3_deflt.if%s} \ | |
130 | %{mmap4:m4_deflt.if%s} \ | |
131 | %{!mmap*:m4_deflt.if%s}} \ | |
132 | %{ifile*:%*} %{r}" | |
133 | ||
134 | /* Include path is determined from the environment variable */ | |
135 | #define INCLUDE_DEFAULTS \ | |
136 | { \ | |
137 | { 0, 0, 0 } \ | |
138 | } | |
946730d0 RK |
139 | |
140 | /* Names to predefine in the preprocessor for this target machine. */ | |
141 | #ifdef __MSDOS__ | |
142 | #define CPP_PREDEFINES "-Ddsp1600 -DDSP1600 -DMSDOS" | |
143 | #else | |
144 | #define CPP_PREDEFINES "-Ddsp1600 -DDSP1600 -Ddsp1610 -DDSP1610" | |
145 | #endif | |
146 | ||
147 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
148 | ||
149 | extern int target_flags; | |
150 | ||
151 | /* Macros used in the machine description to test the flags. */ | |
152 | ||
153 | #define MASK_REGPARM 0x00000001 /* Pass parameters in registers */ | |
154 | #define MASK_NEAR_CALL 0x00000002 /* The call is on the same 4k page */ | |
155 | #define MASK_NEAR_JUMP 0x00000004 /* The jump is on the same 4k page */ | |
156 | #define MASK_BMU 0x00000008 /* Use the 'bmu' shift instructions */ | |
946730d0 RK |
157 | #define MASK_MAP1 0x00000040 /* Link with map1 */ |
158 | #define MASK_MAP2 0x00000080 /* Link with map2 */ | |
159 | #define MASK_MAP3 0x00000100 /* Link with map3 */ | |
160 | #define MASK_MAP4 0x00000200 /* Link with map4 */ | |
161 | #define MASK_YBASE_HIGH 0x00000400 /* The ybase register window starts high */ | |
162 | #define MASK_INIT 0x00000800 /* Have the linker generate tables to | |
163 | initialize data at startup */ | |
946730d0 | 164 | #define MASK_RESERVE_YBASE 0x00002000 /* Reserved the ybase registers */ |
dff06f62 MC |
165 | #define MASK_DEBUG 0x00004000 /* Debugging turned on*/ |
166 | #define MASK_SAVE_TEMPS 0x00008000 /* Save temps. option seen */ | |
946730d0 RK |
167 | |
168 | /* Compile passing first two args in regs 0 and 1. | |
169 | This exists only to test compiler features that will | |
170 | be needed for RISC chips. It is not usable | |
171 | and is not intended to be usable on this cpu. */ | |
172 | #define TARGET_REGPARM (target_flags & MASK_REGPARM) | |
173 | ||
174 | /* The call is on the same 4k page, so instead of loading | |
175 | the 'pt' register and branching, we can branch directly */ | |
176 | ||
177 | #define TARGET_NEAR_CALL (target_flags & MASK_NEAR_CALL) | |
178 | ||
179 | /* The jump is on the same 4k page, so instead of loading | |
180 | the 'pt' register and branching, we can branch directly */ | |
181 | ||
182 | #define TARGET_NEAR_JUMP (target_flags & MASK_NEAR_JUMP) | |
183 | ||
184 | /* Generate shift instructions to use the 1610 Bit Manipulation | |
bf0e974b | 185 | Unit. */ |
946730d0 RK |
186 | #define TARGET_BMU (target_flags & MASK_BMU) |
187 | ||
946730d0 RK |
188 | #define TARGET_YBASE_HIGH (target_flags & MASK_YBASE_HIGH) |
189 | ||
190 | /* Direct the linker to output extra info for initialized data */ | |
191 | #define TARGET_MASK_INIT (target_flags & MASK_INIT) | |
192 | ||
193 | #define TARGET_INLINE_MULT (target_flags & MASK_INLINE_MULT) | |
194 | ||
195 | /* Reserve the ybase registers *(0) - *(31) */ | |
196 | #define TARGET_RESERVE_YBASE (target_flags & MASK_RESERVE_YBASE) | |
197 | ||
dff06f62 MC |
198 | /* We turn this option on internally after seeing "-g" */ |
199 | #define TARGET_DEBUG (target_flags & MASK_DEBUG) | |
200 | ||
201 | /* We turn this option on internally after seeing "-save-temps */ | |
202 | #define TARGET_SAVE_TEMPS (target_flags & MASK_SAVE_TEMPS) | |
203 | ||
204 | ||
946730d0 RK |
205 | /* Macro to define tables used to set the flags. |
206 | This is a list in braces of pairs in braces, | |
207 | each pair being { "NAME", VALUE } | |
208 | where VALUE is the bits to set or minus the bits to clear. | |
209 | An empty string NAME is used to identify the default VALUE. */ | |
210 | ||
211 | ||
dff06f62 MC |
212 | #define TARGET_SWITCHES \ |
213 | { \ | |
214 | { "regparm", MASK_REGPARM, \ | |
215 | N_("Pass parameters in registers (default)") }, \ | |
216 | { "no-regparm", -MASK_REGPARM, \ | |
217 | N_("Don't pass parameters in registers") }, \ | |
218 | { "near-call", MASK_NEAR_JUMP, \ | |
219 | N_("Generate code for near calls") }, \ | |
220 | { "no-near-call", -MASK_NEAR_CALL, \ | |
221 | N_("Don't generate code for near calls") }, \ | |
222 | { "near-jump", MASK_NEAR_JUMP, \ | |
223 | N_("Generate code for near jumps") }, \ | |
224 | { "no-near-jump", -MASK_NEAR_JUMP, \ | |
225 | N_("Don't generate code for near jumps") }, \ | |
226 | { "bmu", MASK_BMU, \ | |
227 | N_("Generate code for a bit-manipulation unit") }, \ | |
228 | { "no-bmu", -MASK_BMU, \ | |
229 | N_("Don't generate code for a bit-manipulation unit") }, \ | |
230 | { "map1", MASK_MAP1, \ | |
231 | N_("Generate code for memory map1") }, \ | |
232 | { "map2", MASK_MAP2, \ | |
233 | N_("Generate code for memory map2") }, \ | |
234 | { "map3", MASK_MAP3, \ | |
235 | N_("Generate code for memory map3") }, \ | |
236 | { "map4", MASK_MAP4, \ | |
237 | N_("Generate code for memory map4") }, \ | |
238 | { "init", MASK_INIT, \ | |
239 | N_("Ouput extra code for initialized data") }, \ | |
240 | { "reserve-ybase", MASK_RESERVE_YBASE, \ | |
241 | N_("Don't let reg. allocator use ybase registers") }, \ | |
242 | { "debug", MASK_DEBUG, \ | |
243 | N_("Output extra debug info in Luxworks environment") }, \ | |
244 | { "save-temporaries", MASK_SAVE_TEMPS, \ | |
245 | N_("Save temp. files in Luxworks environment") }, \ | |
246 | { "", TARGET_DEFAULT, ""} \ | |
946730d0 RK |
247 | } |
248 | ||
249 | /* Default target_flags if no switches are specified */ | |
250 | #ifndef TARGET_DEFAULT | |
dff06f62 | 251 | #define TARGET_DEFAULT MASK_REGPARM|MASK_YBASE_HIGH |
946730d0 RK |
252 | #endif |
253 | ||
254 | /* This macro is similar to `TARGET_SWITCHES' but defines names of | |
255 | command options that have values. Its definition is an | |
256 | initializer with a subgrouping for each command option. | |
257 | ||
258 | Each subgrouping contains a string constant, that defines the | |
259 | fixed part of the option name, and the address of a variable. | |
260 | The variable, type `char *', is set to the variable part of the | |
261 | given option if the fixed part matches. The actual option name | |
262 | is made by appending `-m' to the specified name. | |
263 | ||
264 | Here is an example which defines `-mshort-data-NUMBER'. If the | |
265 | given option is `-mshort-data-512', the variable `m88k_short_data' | |
266 | will be set to the string `"512"'. | |
267 | ||
268 | extern char *m88k_short_data; | |
269 | #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */ | |
270 | ||
271 | #define TARGET_OPTIONS \ | |
272 | { \ | |
dff06f62 MC |
273 | { "text=", &text_seg_name, \ |
274 | N_("Specify alternate name for text section") }, \ | |
275 | { "data=", &data_seg_name, \ | |
276 | N_("Specify alternate name for data section") }, \ | |
277 | { "bss=", &bss_seg_name, \ | |
278 | N_("Specify alternate name for bss section") }, \ | |
279 | { "const=", &const_seg_name, \ | |
280 | N_("Specify alternate name for constant section") }, \ | |
281 | { "chip=", &chip_name, \ | |
282 | N_("Specify alternate name for dsp16xx chip") }, \ | |
946730d0 RK |
283 | } |
284 | ||
285 | /* Sometimes certain combinations of command options do not make sense | |
286 | on a particular target machine. You can define a macro | |
287 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
288 | defined, is executed once just after all the command options have | |
a596f4d7 CW |
289 | been parsed. |
290 | ||
291 | Don't use this macro to turn on various extra optimizations for | |
292 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
946730d0 RK |
293 | |
294 | #define OVERRIDE_OPTIONS override_options () | |
295 | ||
dff06f62 MC |
296 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ |
297 | { \ | |
298 | flag_gnu_linker = FALSE; \ | |
299 | \ | |
300 | if (LEVEL >= 2) \ | |
301 | { \ | |
302 | /* The dsp16xx family has so few registers \ | |
303 | * that running the first instruction \ | |
304 | * scheduling is bad for reg. allocation \ | |
305 | * since it increases lifetimes of pseudos. \ | |
306 | * So turn of first scheduling pass. \ | |
307 | */ \ | |
308 | flag_schedule_insns = FALSE; \ | |
309 | } \ | |
310 | } | |
946730d0 RK |
311 | \f |
312 | /* STORAGE LAYOUT */ | |
313 | ||
314 | /* Define if you don't want extended real, but do want to use the | |
315 | software floating point emulator for REAL_ARITHMETIC and | |
bf0e974b | 316 | decimal <-> binary conversion. */ |
946730d0 RK |
317 | #define REAL_ARITHMETIC |
318 | ||
319 | /* Define this if most significant bit is lowest numbered | |
320 | in instructions that operate on numbered bit-fields. | |
321 | */ | |
dff06f62 | 322 | #define BITS_BIG_ENDIAN 0 |
946730d0 RK |
323 | |
324 | /* Define this if most significant byte of a word is the lowest numbered. | |
325 | We define big-endian, but since the 1600 series cannot address bytes | |
bf0e974b | 326 | it does not matter. */ |
946730d0 RK |
327 | #define BYTES_BIG_ENDIAN 1 |
328 | ||
329 | /* Define this if most significant word of a multiword number is numbered. | |
bf0e974b | 330 | For the 1600 we can decide arbitrarily since there are no machine instructions for them. */ |
946730d0 RK |
331 | #define WORDS_BIG_ENDIAN 1 |
332 | ||
ddd5a7c1 | 333 | /* number of bits in an addressable storage unit */ |
946730d0 RK |
334 | #define BITS_PER_UNIT 16 |
335 | ||
336 | /* Width in bits of a "word", which is the contents of a machine register. | |
337 | Note that this is not necessarily the width of data type `int'; | |
338 | if using 16-bit ints on a 68000, this would still be 32. | |
339 | But on a machine with 16-bit registers, this would be 16. */ | |
340 | #define BITS_PER_WORD 16 | |
341 | ||
bf0e974b | 342 | /* Maximum number of bits in a word. */ |
946730d0 RK |
343 | #define MAX_BITS_PER_WORD 16 |
344 | ||
345 | /* Width of a word, in units (bytes). */ | |
346 | #define UNITS_PER_WORD 1 | |
347 | ||
348 | /* Width in bits of a pointer. | |
349 | See also the macro `Pmode' defined below. */ | |
350 | #define POINTER_SIZE 16 | |
351 | ||
352 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ | |
353 | #define POINTER_BOUNDARY 16 | |
354 | ||
355 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
356 | #define PARM_BOUNDARY 16 | |
357 | ||
358 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
359 | #define STACK_BOUNDARY 16 | |
360 | ||
361 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
362 | #define FUNCTION_BOUNDARY 16 | |
363 | ||
364 | /* Biggest alignment that any data type can require on this machine, in bits. */ | |
365 | #define BIGGEST_ALIGNMENT 16 | |
366 | ||
367 | /* Biggest alignment that any structure field can require on this machine, in bits */ | |
368 | #define BIGGEST_FIELD_ALIGNMENT 16 | |
369 | ||
370 | /* Alignment of field after `int : 0' in a structure. */ | |
371 | #define EMPTY_FIELD_BOUNDARY 16 | |
372 | ||
373 | /* Number of bits which any structure or union's size must be a multiple of. Each structure | |
374 | or union's size is rounded up to a multiple of this */ | |
375 | #define STRUCTURE_SIZE_BOUNDARY 16 | |
376 | ||
377 | /* Define this if move instructions will actually fail to work | |
378 | when given unaligned data. */ | |
379 | #define STRICT_ALIGNMENT 1 | |
380 | ||
381 | /* An integer expression for the size in bits of the largest integer machine mode that | |
382 | should actually be used. All integer machine modes of this size or smaller can be | |
bf0e974b | 383 | used for structures and unions with the appropriate sizes. */ |
946730d0 RK |
384 | #define MAX_FIXED_MODE_SIZE 32 |
385 | \f | |
386 | /* LAYOUT OF SOURCE LANGUAGE DATA TYPES */ | |
387 | ||
388 | #define CHAR_TYPE_SIZE 16 | |
389 | #define SHORT_TYPE_SIZE 16 | |
390 | #define INT_TYPE_SIZE 16 | |
391 | #define LONG_TYPE_SIZE 32 | |
392 | #define LONG_LONG_TYPE_SIZE 32 | |
393 | #define FLOAT_TYPE_SIZE 32 | |
394 | #define DOUBLE_TYPE_SIZE 32 | |
395 | #define LONG_DOUBLE_TYPE_SIZE 32 | |
396 | ||
397 | /* An expression whose value is 1 or 0, according to whether the type char should be | |
bf0e974b | 398 | signed or unsigned by default. */ |
946730d0 RK |
399 | |
400 | #define DEFAULT_SIGNED_CHAR 1 | |
401 | ||
402 | /* A C expression to determine whether to give an enum type only as many bytes | |
403 | as it takes to represent the range of possible values of that type. A nonzero | |
404 | value means to do that; a zero value means all enum types should be allocated | |
bf0e974b | 405 | like int. */ |
946730d0 RK |
406 | |
407 | #define DEFAULT_SHORT_ENUMS 0 | |
408 | ||
409 | /* A C expression for a string describing the name of the data type to use for | |
bf0e974b | 410 | size values. */ |
946730d0 | 411 | |
dff06f62 | 412 | #define SIZE_TYPE "unsigned int" |
946730d0 | 413 | |
dff06f62 | 414 | /* A C expression for a string describing the name of the data type to use for the |
946730d0 RK |
415 | result of subtracting two pointers */ |
416 | ||
dff06f62 MC |
417 | #define PTRDIFF_TYPE "int" |
418 | ||
946730d0 RK |
419 | \f |
420 | /* REGISTER USAGE. */ | |
421 | ||
422 | #define ALL_16_BIT_REGISTERS 1 | |
423 | ||
424 | /* Number of actual hardware registers. | |
425 | The hardware registers are assigned numbers for the compiler | |
426 | from 0 to FIRST_PSEUDO_REGISTER-1 */ | |
427 | ||
d2a0c2ee | 428 | #define FIRST_PSEUDO_REGISTER (REG_YBASE31 + 1) |
946730d0 RK |
429 | |
430 | /* 1 for registers that have pervasive standard uses | |
431 | and are not available for the register allocator. | |
432 | ||
18543a22 | 433 | The registers are laid out as follows: |
946730d0 RK |
434 | |
435 | {a0,a0l,a1,a1l,x,y,yl,p,pl} - Data Arithmetic Unit | |
436 | {r0,r1,r2,r3,j,k,ybase} - Y Space Address Arithmetic Unit | |
437 | {pt} - X Space Address Arithmetic Unit | |
438 | {ar0,ar1,ar2,ar3} - Bit Manipulation UNit | |
439 | {pr} - Return Address Register | |
440 | ||
441 | We reserve r2 for the Stack Pointer. | |
442 | We specify r3 for the Frame Pointer but allow the compiler | |
bf0e974b | 443 | to omit it when possible since we have so few pointer registers. */ |
946730d0 RK |
444 | |
445 | #define REG_A0 0 | |
446 | #define REG_A0L 1 | |
447 | #define REG_A1 2 | |
448 | #define REG_A1L 3 | |
449 | #define REG_X 4 | |
450 | #define REG_Y 5 | |
451 | #define REG_YL 6 | |
452 | #define REG_PROD 7 | |
453 | #define REG_PRODL 8 | |
454 | #define REG_R0 9 | |
455 | #define REG_R1 10 | |
456 | #define REG_R2 11 | |
457 | #define REG_R3 12 | |
458 | #define REG_J 13 | |
459 | #define REG_K 14 | |
460 | #define REG_YBASE 15 | |
461 | #define REG_PT 16 | |
462 | #define REG_AR0 17 | |
463 | #define REG_AR1 18 | |
464 | #define REG_AR2 19 | |
465 | #define REG_AR3 20 | |
466 | #define REG_C0 21 | |
467 | #define REG_C1 22 | |
468 | #define REG_C2 23 | |
469 | #define REG_PR 24 | |
470 | #define REG_RB 25 | |
471 | #define REG_YBASE0 26 | |
472 | #define REG_YBASE1 27 | |
473 | #define REG_YBASE2 28 | |
474 | #define REG_YBASE3 29 | |
475 | #define REG_YBASE4 30 | |
476 | #define REG_YBASE5 31 | |
477 | #define REG_YBASE6 32 | |
478 | #define REG_YBASE7 33 | |
479 | #define REG_YBASE8 34 | |
480 | #define REG_YBASE9 35 | |
481 | #define REG_YBASE10 36 | |
482 | #define REG_YBASE11 37 | |
483 | #define REG_YBASE12 38 | |
484 | #define REG_YBASE13 39 | |
485 | #define REG_YBASE14 40 | |
486 | #define REG_YBASE15 41 | |
487 | #define REG_YBASE16 42 | |
488 | #define REG_YBASE17 43 | |
489 | #define REG_YBASE18 44 | |
490 | #define REG_YBASE19 45 | |
491 | #define REG_YBASE20 46 | |
492 | #define REG_YBASE21 47 | |
493 | #define REG_YBASE22 48 | |
494 | #define REG_YBASE23 49 | |
495 | #define REG_YBASE24 50 | |
496 | #define REG_YBASE25 51 | |
497 | #define REG_YBASE26 52 | |
498 | #define REG_YBASE27 53 | |
499 | #define REG_YBASE28 54 | |
500 | #define REG_YBASE29 55 | |
501 | #define REG_YBASE30 56 | |
502 | #define REG_YBASE31 57 | |
503 | ||
e03f5d43 | 504 | /* Do we have an accumulator register? */ |
55710451 | 505 | #define IS_ACCUM_REG(REGNO) IN_RANGE ((REGNO), REG_A0, REG_A1L) |
946730d0 RK |
506 | #define IS_ACCUM_LOW_REG(REGNO) ((REGNO) == REG_A0L || (REGNO) == REG_A1L) |
507 | ||
508 | /* Do we have a virtual ybase register */ | |
509 | #define IS_YBASE_REGISTER_WINDOW(REGNO) ((REGNO) >= REG_YBASE0 && (REGNO) <= REG_YBASE31) | |
510 | ||
dff06f62 MC |
511 | #define IS_YBASE_ELIGIBLE_REG(REGNO) (IS_ACCUM_REG (REGNO) || IS_ADDRESS_REGISTER(REGNO) \ |
512 | || REGNO == REG_X || REGNO == REG_Y || REGNO == REG_YL \ | |
513 | || REGNO == REG_PROD || REGNO == REG_PRODL) | |
514 | ||
946730d0 RK |
515 | #define IS_ADDRESS_REGISTER(REGNO) ((REGNO) >= REG_R0 && (REGNO) <= REG_R3) |
516 | ||
517 | #define FIXED_REGISTERS \ | |
518 | {0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
519 | 0, 0, 0, 1, 0, 0, 1, \ | |
520 | 1, \ | |
521 | 0, 0, 0, 0, \ | |
522 | 1, 1, 1, \ | |
dff06f62 | 523 | 1, 0, \ |
946730d0 RK |
524 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
525 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
526 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
527 | 0, 0, 0, 0, 0, 0, 0, 0} | |
528 | ||
529 | /* 1 for registers not available across function calls. | |
530 | These must include the FIXED_REGISTERS and also any | |
531 | registers that can be used without being saved. | |
532 | The latter must include the registers where values are returned | |
533 | and the register where structure-value addresses are passed. | |
534 | On the 1610 'a0' holds return values from functions. 'r0' holds | |
535 | structure-value addresses. | |
536 | ||
537 | In addition we don't save either j, k, ybase or any of the | |
538 | bit manipulation registers. */ | |
539 | ||
540 | ||
dff06f62 MC |
541 | #define CALL_USED_REGISTERS \ |
542 | {1, 1, 1, 1, 0, 1, 1, 1, 1, /* 0-8 */ \ | |
543 | 1, 0, 0, 1, 1, 1, 1, /* 9-15 */ \ | |
544 | 1, /* 16 */ \ | |
545 | 0, 0, 1, 1, /* 17-20 */ \ | |
546 | 1, 1, 1, /* 21-23 */ \ | |
547 | 1, 1, /* 24-25 */ \ | |
548 | 0, 0, 0, 0, 0, 0, 0, 0, /* 26-33 */ \ | |
549 | 0, 0, 0, 0, 0, 0, 0, 0, /* 34-41 */ \ | |
550 | 0, 0, 0, 0, 0, 0, 0, 0, /* 42-49 */ \ | |
551 | 0, 0, 0, 0, 0, 0, 0, 0} /* 50-57 */ | |
946730d0 RK |
552 | |
553 | /* List the order in which to allocate registers. Each register must be | |
554 | listed once, even those in FIXED_REGISTERS. | |
555 | ||
556 | We allocate in the following order: | |
557 | */ | |
558 | ||
dff06f62 | 559 | #if 0 |
946730d0 RK |
560 | #define REG_ALLOC_ORDER \ |
561 | { REG_R0, REG_R1, REG_R2, REG_PROD, REG_Y, REG_X, \ | |
562 | REG_PRODL, REG_YL, REG_AR0, REG_AR1, \ | |
563 | REG_RB, REG_A0, REG_A1, REG_A0L, \ | |
564 | REG_A1L, REG_AR2, REG_AR3, \ | |
565 | REG_YBASE, REG_J, REG_K, REG_PR, REG_PT, REG_C0, \ | |
566 | REG_C1, REG_C2, REG_R3, \ | |
567 | REG_YBASE0, REG_YBASE1, REG_YBASE2, REG_YBASE3, \ | |
568 | REG_YBASE4, REG_YBASE5, REG_YBASE6, REG_YBASE7, \ | |
569 | REG_YBASE8, REG_YBASE9, REG_YBASE10, REG_YBASE11, \ | |
570 | REG_YBASE12, REG_YBASE13, REG_YBASE14, REG_YBASE15, \ | |
571 | REG_YBASE16, REG_YBASE17, REG_YBASE18, REG_YBASE19, \ | |
572 | REG_YBASE20, REG_YBASE21, REG_YBASE22, REG_YBASE23, \ | |
573 | REG_YBASE24, REG_YBASE25, REG_YBASE26, REG_YBASE27, \ | |
574 | REG_YBASE28, REG_YBASE29, REG_YBASE30, REG_YBASE31 } | |
dff06f62 MC |
575 | #else |
576 | #define REG_ALLOC_ORDER \ | |
577 | { \ | |
578 | REG_A0, REG_A0L, REG_A1, REG_A1L, REG_Y, REG_YL, \ | |
579 | REG_PROD, \ | |
580 | REG_PRODL, REG_R0, REG_J, REG_K, REG_AR2, REG_AR3, \ | |
581 | REG_X, REG_R1, REG_R2, REG_RB, REG_AR0, REG_AR1, \ | |
582 | REG_YBASE0, REG_YBASE1, REG_YBASE2, REG_YBASE3, \ | |
583 | REG_YBASE4, REG_YBASE5, REG_YBASE6, REG_YBASE7, \ | |
584 | REG_YBASE8, REG_YBASE9, REG_YBASE10, REG_YBASE11, \ | |
585 | REG_YBASE12, REG_YBASE13, REG_YBASE14, REG_YBASE15, \ | |
586 | REG_YBASE16, REG_YBASE17, REG_YBASE18, REG_YBASE19, \ | |
587 | REG_YBASE20, REG_YBASE21, REG_YBASE22, REG_YBASE23, \ | |
588 | REG_YBASE24, REG_YBASE25, REG_YBASE26, REG_YBASE27, \ | |
589 | REG_YBASE28, REG_YBASE29, REG_YBASE30, REG_YBASE31, \ | |
590 | REG_R3, REG_YBASE, REG_PT, REG_C0, REG_C1, REG_C2, \ | |
591 | REG_PR } | |
592 | #endif | |
946730d0 RK |
593 | /* Zero or more C statements that may conditionally modify two |
594 | variables `fixed_regs' and `call_used_regs' (both of type `char | |
595 | []') after they have been initialized from the two preceding | |
596 | macros. | |
597 | ||
598 | This is necessary in case the fixed or call-clobbered registers | |
599 | depend on target flags. | |
600 | ||
601 | You need not define this macro if it has no work to do. | |
602 | ||
603 | If the usage of an entire class of registers depends on the target | |
604 | flags, you may indicate this to GCC by using this macro to modify | |
605 | `fixed_regs' and `call_used_regs' to 1 for each of the registers in | |
606 | the classes which should not be used by GCC. Also define the macro | |
607 | `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a | |
608 | letter for a class that shouldn't be used. | |
609 | ||
610 | (However, if this class is not included in `GENERAL_REGS' and all | |
611 | of the insn patterns whose constraints permit this class are | |
612 | controlled by target switches, then GCC will automatically avoid | |
613 | using these registers when the target switches are opposed to | |
614 | them.) If the user tells us there is no BMU, we can't use | |
ddd5a7c1 | 615 | ar0-ar3 for register allocation */ |
946730d0 RK |
616 | |
617 | #define CONDITIONAL_REGISTER_USAGE \ | |
618 | do \ | |
619 | { \ | |
620 | if (!TARGET_BMU) \ | |
621 | { \ | |
622 | int regno; \ | |
623 | \ | |
624 | for (regno = REG_AR0; regno <= REG_AR3; regno++) \ | |
625 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
626 | } \ | |
627 | if (TARGET_RESERVE_YBASE) \ | |
628 | { \ | |
629 | int regno; \ | |
630 | \ | |
631 | for (regno = REG_YBASE0; regno <= REG_YBASE31; regno++) \ | |
632 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
633 | } \ | |
634 | } \ | |
635 | while (0) | |
636 | ||
637 | /* Determine which register classes are very likely used by spill registers. | |
638 | local-alloc.c won't allocate pseudos that have these classes as their | |
639 | preferred class unless they are "preferred or nothing". */ | |
640 | ||
641 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
642 | ((CLASS) != ALL_REGS && (CLASS) != YBASE_VIRT_REGS) | |
643 | ||
644 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
645 | to hold something of mode MODE. | |
646 | This is ordinarily the length in words of a value of mode MODE | |
bf0e974b | 647 | but can be less for certain modes in special long registers. */ |
946730d0 RK |
648 | |
649 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
650 | (GET_MODE_SIZE(MODE)) | |
651 | ||
bf0e974b | 652 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
946730d0 RK |
653 | |
654 | #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok(REGNO, MODE) | |
655 | ||
656 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
657 | when one has mode MODE1 and one has mode MODE2. | |
658 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
659 | for any hard reg, then this must be 0 for correct output. */ | |
660 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
661 | (((MODE1) == (MODE2)) || \ | |
662 | (GET_MODE_CLASS((MODE1)) == MODE_FLOAT) \ | |
663 | == (GET_MODE_CLASS((MODE2)) == MODE_FLOAT)) | |
664 | ||
665 | /* Specify the registers used for certain standard purposes. | |
666 | The values of these macros are register numbers. */ | |
667 | ||
668 | /* DSP1600 pc isn't overloaded on a register. */ | |
669 | /* #define PC_REGNUM */ | |
670 | ||
671 | /* Register to use for pushing function arguments. | |
672 | This is r3 in our case */ | |
673 | #define STACK_POINTER_REGNUM REG_R3 | |
674 | ||
675 | /* Base register for access to local variables of the function. | |
676 | This is r2 in our case */ | |
677 | #define FRAME_POINTER_REGNUM REG_R2 | |
678 | ||
679 | /* We can debug without the frame pointer */ | |
680 | #define CAN_DEBUG_WITHOUT_FP 1 | |
681 | ||
682 | /* The 1610 saves the return address in this register */ | |
683 | #define RETURN_ADDRESS_REGNUM REG_PR | |
684 | ||
685 | /* Base register for access to arguments of the function. */ | |
686 | #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM | |
687 | ||
688 | /* Register in which static-chain is passed to a function. */ | |
689 | ||
690 | #define STATIC_CHAIN_REGNUM 4 | |
691 | ||
692 | /* Register in which address to store a structure value | |
693 | is passed to a function. This is 'r0' in our case */ | |
694 | #define STRUCT_VALUE_REGNUM REG_R0 | |
695 | \f | |
696 | /* Define the classes of registers for register constraints in the | |
697 | machine description. Also define ranges of constants. | |
698 | ||
699 | One of the classes must always be named ALL_REGS and include all hard regs. | |
700 | If there is more than one class, another class must be named NO_REGS | |
701 | and contain no registers. | |
702 | ||
703 | The name GENERAL_REGS must be the name of a class (or an alias for | |
704 | another name such as ALL_REGS). This is the class of registers | |
705 | that is allowed by "g" or "r" in a register constraint. | |
706 | Also, registers outside this class are allocated only when | |
707 | instructions express preferences for them. | |
708 | ||
709 | The classes must be numbered in nondecreasing order; that is, | |
710 | a larger-numbered class must never be contained completely | |
711 | in a smaller-numbered class. | |
712 | ||
713 | For any two classes, it is very desirable that there be another | |
714 | class that represents their union. */ | |
715 | ||
716 | ||
717 | enum reg_class | |
718 | { | |
719 | NO_REGS, | |
720 | A0H_REG, | |
721 | A0L_REG, | |
722 | A0_REG, | |
723 | A1H_REG, | |
724 | ACCUM_HIGH_REGS, | |
725 | A1L_REG, | |
726 | ACCUM_LOW_REGS, | |
727 | A1_REG, | |
728 | ACCUM_REGS, | |
729 | X_REG, | |
730 | X_OR_ACCUM_LOW_REGS, | |
731 | X_OR_ACCUM_REGS, | |
732 | YH_REG, | |
733 | YH_OR_ACCUM_HIGH_REGS, | |
734 | X_OR_YH_REGS, | |
735 | YL_REG, | |
736 | YL_OR_ACCUM_LOW_REGS, | |
737 | X_OR_YL_REGS, | |
738 | X_OR_Y_REGS, | |
739 | Y_REG, | |
740 | ACCUM_OR_Y_REGS, | |
741 | PH_REG, | |
742 | X_OR_PH_REGS, | |
743 | PL_REG, | |
744 | PL_OR_ACCUM_LOW_REGS, | |
745 | X_OR_PL_REGS, | |
746 | YL_OR_PL_OR_ACCUM_LOW_REGS, | |
747 | P_REG, | |
748 | ACCUM_OR_P_REGS, | |
749 | YL_OR_P_REGS, | |
750 | ACCUM_LOW_OR_YL_OR_P_REGS, | |
751 | Y_OR_P_REGS, | |
752 | ACCUM_Y_OR_P_REGS, | |
753 | NO_FRAME_Y_ADDR_REGS, | |
754 | Y_ADDR_REGS, | |
755 | ACCUM_LOW_OR_Y_ADDR_REGS, | |
756 | ACCUM_OR_Y_ADDR_REGS, | |
757 | X_OR_Y_ADDR_REGS, | |
758 | Y_OR_Y_ADDR_REGS, | |
759 | P_OR_Y_ADDR_REGS, | |
760 | NON_HIGH_YBASE_ELIGIBLE_REGS, | |
761 | YBASE_ELIGIBLE_REGS, | |
762 | J_REG, | |
763 | J_OR_DAU_16_BIT_REGS, | |
764 | BMU_REGS, | |
765 | NOHIGH_NON_ADDR_REGS, | |
766 | NON_ADDR_REGS, | |
767 | SLOW_MEM_LOAD_REGS, | |
768 | NOHIGH_NON_YBASE_REGS, | |
769 | NO_ACCUM_NON_YBASE_REGS, | |
770 | NON_YBASE_REGS, | |
771 | YBASE_VIRT_REGS, | |
772 | ACCUM_LOW_OR_YBASE_REGS, | |
773 | ACCUM_OR_YBASE_REGS, | |
774 | X_OR_YBASE_REGS, | |
775 | Y_OR_YBASE_REGS, | |
776 | ACCUM_LOW_YL_PL_OR_YBASE_REGS, | |
777 | P_OR_YBASE_REGS, | |
778 | ACCUM_Y_P_OR_YBASE_REGS, | |
779 | Y_ADDR_OR_YBASE_REGS, | |
780 | YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS, | |
781 | YBASE_OR_YBASE_ELIGIBLE_REGS, | |
782 | NO_HIGH_ALL_REGS, | |
783 | ALL_REGS, | |
784 | LIM_REG_CLASSES | |
785 | }; | |
786 | ||
787 | /* GENERAL_REGS must be the name of a register class */ | |
788 | #define GENERAL_REGS ALL_REGS | |
789 | ||
790 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
791 | ||
bf0e974b | 792 | /* Give names of register classes as strings for dump file. */ |
946730d0 RK |
793 | |
794 | #define REG_CLASS_NAMES \ | |
795 | { \ | |
796 | "NO_REGS", \ | |
797 | "A0H_REG", \ | |
798 | "A0L_REG", \ | |
799 | "A0_REG", \ | |
800 | "A1H_REG", \ | |
801 | "ACCUM_HIGH_REGS", \ | |
802 | "A1L_REG", \ | |
803 | "ACCUM_LOW_REGS", \ | |
804 | "A1_REG", \ | |
805 | "ACCUM_REGS", \ | |
806 | "X_REG", \ | |
807 | "X_OR_ACCUM_LOW_REGS", \ | |
808 | "X_OR_ACCUM_REGS", \ | |
809 | "YH_REG", \ | |
810 | "YH_OR_ACCUM_HIGH_REGS", \ | |
811 | "X_OR_YH_REGS", \ | |
812 | "YL_REG", \ | |
813 | "YL_OR_ACCUM_LOW_REGS", \ | |
814 | "X_OR_YL_REGS", \ | |
815 | "X_OR_Y_REGS", \ | |
816 | "Y_REG", \ | |
817 | "ACCUM_OR_Y_REGS", \ | |
818 | "PH_REG", \ | |
819 | "X_OR_PH_REGS", \ | |
820 | "PL_REG", \ | |
821 | "PL_OR_ACCUM_LOW_REGS", \ | |
822 | "X_OR_PL_REGS", \ | |
823 | "PL_OR_YL_OR_ACCUM_LOW_REGS", \ | |
824 | "P_REG", \ | |
825 | "ACCUM_OR_P_REGS", \ | |
826 | "YL_OR_P_REGS", \ | |
827 | "ACCUM_LOW_OR_YL_OR_P_REGS", \ | |
828 | "Y_OR_P_REGS", \ | |
829 | "ACCUM_Y_OR_P_REGS", \ | |
830 | "NO_FRAME_Y_ADDR_REGS", \ | |
831 | "Y_ADDR_REGS", \ | |
832 | "ACCUM_LOW_OR_Y_ADDR_REGS", \ | |
833 | "ACCUM_OR_Y_ADDR_REGS", \ | |
834 | "X_OR_Y_ADDR_REGS", \ | |
835 | "Y_OR_Y_ADDR_REGS", \ | |
836 | "P_OR_Y_ADDR_REGS", \ | |
837 | "NON_HIGH_YBASE_ELIGIBLE_REGS", \ | |
838 | "YBASE_ELIGIBLE_REGS", \ | |
839 | "J_REG", \ | |
840 | "J_OR_DAU_16_BIT_REGS", \ | |
841 | "BMU_REGS", \ | |
842 | "NOHIGH_NON_ADDR_REGS", \ | |
843 | "NON_ADDR_REGS", \ | |
844 | "SLOW_MEM_LOAD_REGS", \ | |
845 | "NOHIGH_NON_YBASE_REGS", \ | |
846 | "NO_ACCUM_NON_YBASE_REGS", \ | |
847 | "NON_YBASE_REGS", \ | |
848 | "YBASE_VIRT_REGS", \ | |
849 | "ACCUM_LOW_OR_YBASE_REGS", \ | |
850 | "ACCUM_OR_YBASE_REGS", \ | |
851 | "X_OR_YBASE_REGS", \ | |
852 | "Y_OR_YBASE_REGS", \ | |
853 | "ACCUM_LOW_YL_PL_OR_YBASE_REGS", \ | |
854 | "P_OR_YBASE_REGS", \ | |
855 | "ACCUM_Y_P_OR_YBASE_REGS", \ | |
856 | "Y_ADDR_OR_YBASE_REGS", \ | |
857 | "YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS", \ | |
858 | "YBASE_OR_YBASE_ELIGIBLE_REGS", \ | |
859 | "NO_HIGH_ALL_REGS", \ | |
860 | "ALL_REGS" \ | |
861 | } | |
862 | ||
863 | /* Define which registers fit in which classes. | |
864 | This is an initializer for a vector of HARD_REG_SET | |
865 | of length N_REG_CLASSES. */ | |
866 | ||
867 | #define REG_CLASS_CONTENTS \ | |
868 | { \ | |
869 | {0x00000000, 0x00000000}, /* no reg */ \ | |
870 | {0x00000001, 0x00000000}, /* a0h */ \ | |
871 | {0x00000002, 0x00000000}, /* a0l */ \ | |
872 | {0x00000003, 0x00000000}, /* a0h:a0l */ \ | |
873 | {0x00000004, 0x00000000}, /* a1h */ \ | |
874 | {0x00000005, 0x00000000}, /* accum high */ \ | |
875 | {0x00000008, 0x00000000}, /* a1l */ \ | |
876 | {0x0000000A, 0x00000000}, /* accum low */ \ | |
877 | {0x0000000c, 0x00000000}, /* a1h:a1l */ \ | |
878 | {0x0000000f, 0x00000000}, /* accum regs */ \ | |
879 | {0x00000010, 0x00000000}, /* x reg */ \ | |
880 | {0x0000001A, 0x00000000}, /* x & accum_low_regs */ \ | |
881 | {0x0000001f, 0x00000000}, /* x & accum regs */ \ | |
882 | {0x00000020, 0x00000000}, /* y high */ \ | |
883 | {0x00000025, 0x00000000}, /* yh, accum high */ \ | |
884 | {0x00000030, 0x00000000}, /* x & yh */ \ | |
885 | {0x00000040, 0x00000000}, /* y low */ \ | |
886 | {0x0000004A, 0x00000000}, /* y low, accum_low */ \ | |
887 | {0x00000050, 0x00000000}, /* x & yl */ \ | |
888 | {0x00000060, 0x00000000}, /* yl:yh */ \ | |
889 | {0x00000070, 0x00000000}, /* x, yh,a nd yl */ \ | |
890 | {0x0000006F, 0x00000000}, /* accum, y */ \ | |
891 | {0x00000080, 0x00000000}, /* p high */ \ | |
892 | {0x00000090, 0x00000000}, /* x & ph */ \ | |
893 | {0x00000100, 0x00000000}, /* p low */ \ | |
894 | {0x0000010A, 0x00000000}, /* p_low and accum_low */ \ | |
895 | {0x00000110, 0x00000000}, /* x & pl */ \ | |
896 | {0x0000014A, 0x00000000}, /* pl,yl,a1l,a0l */ \ | |
897 | {0x00000180, 0x00000000}, /* pl:ph */ \ | |
898 | {0x0000018F, 0x00000000}, /* accum, p */ \ | |
899 | {0x000001C0, 0x00000000}, /* pl:ph and yl */ \ | |
900 | {0x000001CA, 0x00000000}, /* pl:ph, yl, a0l, a1l */ \ | |
901 | {0x000001E0, 0x00000000}, /* y or p */ \ | |
902 | {0x000001EF, 0x00000000}, /* accum, y or p */ \ | |
903 | {0x00000E00, 0x00000000}, /* r0-r2 */ \ | |
904 | {0x00001E00, 0x00000000}, /* r0-r3 */ \ | |
905 | {0x00001E0A, 0x00000000}, /* r0-r3, accum_low */ \ | |
906 | {0x00001E0F, 0x00000000}, /* accum,r0-r3 */ \ | |
907 | {0x00001E10, 0x00000000}, /* x,r0-r3 */ \ | |
908 | {0x00001E60, 0x00000000}, /* y,r0-r3 */ \ | |
909 | {0x00001F80, 0x00000000}, /* p,r0-r3 */ \ | |
910 | {0x00001FDA, 0x00000000}, /* ph:pl, r0-r3, x,a0l,a1l */ \ | |
911 | {0x00001fff, 0x00000000}, /* accum,x,y,p,r0-r3 */ \ | |
912 | {0x00002000, 0x00000000}, /* j */ \ | |
913 | {0x00002025, 0x00000000}, /* j, yh, a1h, a0h */ \ | |
914 | {0x001E0000, 0x00000000}, /* ar0-ar3 */ \ | |
915 | {0x03FFE1DA, 0x00000000}, /* non_addr except yh,a0h,a1h */ \ | |
916 | {0x03FFE1FF, 0x00000000}, /* non_addr regs */ \ | |
917 | {0x03FFFF8F, 0x00000000}, /* non ybase except yh, yl, and x */ \ | |
918 | {0x03FFFFDA, 0x00000000}, /* non ybase regs except yh,a0h,a1h */ \ | |
919 | {0x03FFFFF0, 0x00000000}, /* non ybase except a0,a0l,a1,a1l */ \ | |
920 | {0x03FFFFFF, 0x00000000}, /* non ybase regs */ \ | |
921 | {0xFC000000, 0x03FFFFFF}, /* virt ybase regs */ \ | |
922 | {0xFC00000A, 0x03FFFFFF}, /* accum_low, virt ybase regs */ \ | |
923 | {0xFC00000F, 0x03FFFFFF}, /* accum, virt ybase regs */ \ | |
924 | {0xFC000010, 0x03FFFFFF}, /* x,virt ybase regs */ \ | |
925 | {0xFC000060, 0x03FFFFFF}, /* y,virt ybase regs */ \ | |
926 | {0xFC00014A, 0x03FFFFFF}, /* accum_low, yl, pl, ybase */ \ | |
927 | {0xFC000180, 0x03FFFFFF}, /* p,virt ybase regs */ \ | |
928 | {0xFC0001EF, 0x03FFFFFF}, /* accum,y,p,ybase regs */ \ | |
929 | {0xFC001E00, 0x03FFFFFF}, /* r0-r3, ybase regs */ \ | |
930 | {0xFC001FDA, 0x03FFFFFF}, /* r0-r3, pl:ph,yl,x,a1l,a0l */ \ | |
931 | {0xFC001FFF, 0x03FFFFFF}, /* virt ybase, ybase eligible regs */ \ | |
932 | {0xFCFFFFDA, 0x03FFFFFF}, /* all regs except yh,a0h,a1h */ \ | |
933 | {0xFFFFFFFF, 0x03FFFFFF} /* all regs */ \ | |
934 | } | |
935 | ||
936 | ||
937 | /* The same information, inverted: | |
938 | Return the class number of the smallest class containing | |
939 | reg number REGNO. This could be a conditional expression | |
940 | or could index an array. */ | |
941 | ||
942 | #define REGNO_REG_CLASS(REGNO) regno_reg_class(REGNO) | |
943 | ||
944 | /* The class value for index registers, and the one for base regs. */ | |
945 | ||
946 | #define INDEX_REG_CLASS NO_REGS | |
947 | #define BASE_REG_CLASS Y_ADDR_REGS | |
948 | ||
bf0e974b | 949 | /* Get reg_class from a letter such as appears in the machine description. */ |
946730d0 RK |
950 | |
951 | #define REG_CLASS_FROM_LETTER(C) \ | |
952 | dsp16xx_reg_class_from_letter(C) | |
953 | ||
954 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ | |
955 | secondary_reload_class(CLASS, MODE, X) | |
956 | ||
957 | /* When defined, the compiler allows registers explicitly used in the | |
958 | rtl to be used as spill registers but prevents the compiler from | |
bf0e974b | 959 | extending the lifetime of these registers. */ |
946730d0 | 960 | |
2922fe9e | 961 | #define SMALL_REGISTER_CLASSES 1 |
946730d0 RK |
962 | |
963 | /* Macros to check register numbers against specific register classes. */ | |
964 | ||
965 | /* These assume that REGNO is a hard or pseudo reg number. | |
966 | They give nonzero only if REGNO is a hard reg of the suitable class | |
967 | or a pseudo reg currently allocated to a suitable hard reg. | |
968 | Since they use reg_renumber, they are safe only once reg_renumber | |
969 | has been allocated, which happens in local-alloc.c. */ | |
970 | ||
971 | /* A C expression which is nonzero if register REGNO is suitable for use | |
972 | as a base register in operand addresses. It may be either a suitable | |
973 | hard register or a pseudo register that has been allocated such a | |
974 | hard register. | |
975 | ||
976 | On the 1610 the Y address pointers can be used as a base registers */ | |
977 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
978 | (((REGNO) >= REG_R0 && (REGNO) < REG_R3 + 1) || ((unsigned) reg_renumber[REGNO] >= REG_R0 \ | |
979 | && (unsigned) reg_renumber[REGNO] < REG_R3 + 1)) | |
980 | ||
981 | #define REGNO_OK_FOR_YBASE_P(REGNO) \ | |
982 | (((REGNO) == REG_YBASE) || ((unsigned) reg_renumber[REGNO] == REG_YBASE)) | |
983 | ||
984 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
985 | ||
986 | #ifdef ALL_16_BIT_REGISTERS | |
987 | #define IS_32_BIT_REG(REGNO) 0 | |
988 | #else | |
989 | #define IS_32_BIT_REG(REGNO) \ | |
990 | ((REGNO) == REG_A0 || (REGNO) == REG_A1 || (REGNO) == REG_Y || (REGNO) == REG_PROD) | |
991 | #endif | |
992 | ||
993 | /* Given an rtx X being reloaded into a reg required to be | |
994 | in class CLASS, return the class of reg to actually use. | |
995 | In general this is just CLASS; but on some machines | |
996 | in some cases it is preferable to use a more restrictive class. | |
997 | Also, we must ensure that a PLUS is reloaded either | |
998 | into an accumulator or an address register. */ | |
999 | ||
1000 | #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class (X, CLASS) | |
1001 | ||
1002 | /* A C expression that places additional restrictions on the register | |
1003 | class to use when it is necessary to be able to hold a value of | |
1004 | mode MODE in a reload register for which class CLASS would | |
1005 | ordinarily be used. | |
1006 | ||
1007 | Unlike `PREFERRED_RELOAD_CLASS', this macro should be used when | |
1008 | there are certain modes that simply can't go in certain reload | |
1009 | classes. | |
1010 | ||
1011 | The value is a register class; perhaps CLASS, or perhaps another, | |
1012 | smaller class. | |
1013 | ||
1014 | Don't define this macro unless the target machine has limitations | |
bf0e974b | 1015 | which require the macro to do something nontrivial. */ |
946730d0 RK |
1016 | |
1017 | #if 0 | |
1018 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) dsp16xx_limit_reload_class (MODE, CLASS) | |
1019 | #endif | |
1020 | ||
1021 | /* A C expression for the maximum number of consecutive registers of class CLASS | |
abc95ed3 | 1022 | needed to hold a value of mode MODE */ |
946730d0 RK |
1023 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
1024 | class_max_nregs(CLASS, MODE) | |
1025 | ||
1026 | /* The letters 'I' through 'P' in a register constraint string | |
1027 | can be used to stand for particular ranges of immediate operands. | |
1028 | This macro defines what the ranges are. | |
1029 | C is the letter, and VALUE is a constant value. | |
1030 | Return 1 if VALUE is in the range specified by C. | |
1031 | ||
1032 | For the 16xx, the following constraints are used: | |
1033 | 'I' requires a non-negative 16-bit value. | |
1034 | 'J' requires a non-negative 9-bit value | |
1035 | 'K' requires a constant 0 operand. | |
dff06f62 | 1036 | 'L' constant for use in add or sub from low 16-bits |
946730d0 | 1037 | 'M' 32-bit value -- low 16-bits zero |
e03f5d43 | 1038 | 'N' constant for use incrementing or decrementing an address register |
dff06f62 MC |
1039 | 'O' constant for use with and'ing only high 16-bit |
1040 | 'P' constant for use with and'ing only low 16-bit | |
946730d0 RK |
1041 | */ |
1042 | ||
1043 | #define SMALL_INT(X) (SMALL_INTVAL (INTVAL (X))) | |
1044 | #define SMALL_INTVAL(I) ((unsigned) (I) < 0x10000) | |
1045 | #define SHORT_IMMEDIATE(X) (SHORT_INTVAL (INTVAL(X))) | |
1046 | #define SHORT_INTVAL(I) ((unsigned) (I) < 0x100) | |
dff06f62 MC |
1047 | #define ADD_LOW_16(I) ((I) >= 0 && (I) <= 32767) |
1048 | #define ADD_HIGH_16(I) (((I) & 0x0000ffff) == 0) | |
1049 | #define AND_LOW_16(I) ((I) >= 0 && (I) <= 32767) | |
1050 | #define AND_HIGH_16(I) (((I) & 0x0000ffff) == 0) | |
946730d0 RK |
1051 | |
1052 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1053 | ((C) == 'I' ? (SMALL_INTVAL(VALUE)) \ | |
1054 | : (C) == 'J' ? (SHORT_INTVAL(VALUE)) \ | |
1055 | : (C) == 'K' ? ((VALUE) == 0) \ | |
dff06f62 MC |
1056 | : (C) == 'L' ? ((VALUE) >= 0 && (VALUE) <= 32767) \ |
1057 | : (C) == 'M' ? (((VALUE) & 0x0000ffff) == 0) \ | |
1058 | : (C) == 'N' ? ((VALUE) == -1 || (VALUE) == 1 \ | |
1059 | || (VALUE) == -2 || (VALUE) == 2) \ | |
1060 | : (C) == 'O' ? (((VALUE) & 0xffff0000) == 0xffff0000) \ | |
1061 | : (C) == 'P' ? (((VALUE) & 0x0000ffff) == 0xffff) \ | |
946730d0 RK |
1062 | : 0) |
1063 | ||
1064 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 | |
1065 | ||
1066 | /* Optional extra constraints for this machine */ | |
1067 | #define EXTRA_CONSTRAINT(OP,C) \ | |
1068 | ((C) == 'R' ? symbolic_address_p (OP) \ | |
1069 | : 0) | |
1070 | \f | |
1071 | /* DESCRIBING STACK LAYOUT AND CALLING CONVENTIONS */ | |
1072 | ||
1073 | /* Define this if pushing a word on the stack | |
1074 | makes the stack pointer a smaller address. */ | |
1075 | /* #define STACK_GROWS_DOWNWARD */ | |
1076 | ||
1077 | /* Define this if the nominal address of the stack frame | |
1078 | is at the high-address end of the local variables; | |
1079 | that is, each additional local variable allocated | |
1080 | goes at a more negative offset in the frame. */ | |
1081 | /* #define FRAME_GROWS_DOWNWARD */ | |
1082 | ||
1083 | #define ARGS_GROW_DOWNWARD | |
1084 | ||
1085 | /* We use post decrement on the 1600 because there isn't | |
1086 | a pre-decrement addressing mode. This means that we | |
1087 | assume the stack pointer always points at the next | |
bf0e974b | 1088 | FREE location on the stack. */ |
946730d0 RK |
1089 | #define STACK_PUSH_CODE POST_INC |
1090 | ||
1091 | /* Offset within stack frame to start allocating local variables at. | |
1092 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1093 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1094 | of the first local allocated. */ | |
1095 | #define STARTING_FRAME_OFFSET 0 | |
1096 | ||
1097 | /* Offset from the stack pointer register to the first | |
bf0e974b | 1098 | location at which outgoing arguments are placed. */ |
946730d0 RK |
1099 | #define STACK_POINTER_OFFSET (0) |
1100 | ||
1101 | struct dsp16xx_frame_info | |
1102 | { | |
1103 | unsigned long total_size; /* # bytes that the entire frame takes up */ | |
1104 | unsigned long var_size; /* # bytes that variables take up */ | |
1105 | unsigned long args_size; /* # bytes that outgoing arguments take up */ | |
1106 | unsigned long extra_size; /* # bytes of extra gunk */ | |
1107 | unsigned int reg_size; /* # bytes needed to store regs */ | |
1108 | long fp_save_offset; /* offset from vfp to store registers */ | |
1109 | unsigned long sp_save_offset; /* offset from new sp to store registers */ | |
dff06f62 | 1110 | int pr_save_offset; /* offset to saved PR */ |
946730d0 RK |
1111 | int initialized; /* != 0 if frame size already calculated */ |
1112 | int num_regs; /* number of registers saved */ | |
1113 | int function_makes_calls; /* Does the function make calls */ | |
1114 | }; | |
1115 | ||
1116 | extern struct dsp16xx_frame_info current_frame_info; | |
1117 | ||
dff06f62 MC |
1118 | #define RETURN_ADDR_OFF current_frame_info.pr_save_offset |
1119 | ||
946730d0 | 1120 | /* If we generate an insn to push BYTES bytes, |
bf0e974b | 1121 | this says how many the stack pointer really advances by. */ |
946730d0 RK |
1122 | /* #define PUSH_ROUNDING(BYTES) ((BYTES)) */ |
1123 | ||
1124 | /* If defined, the maximum amount of space required for outgoing | |
1125 | arguments will be computed and placed into the variable | |
1126 | 'current_function_outgoing_args_size'. No space will be pushed | |
1127 | onto the stack for each call; instead, the function prologue should | |
1128 | increase the stack frame size by this amount. | |
1129 | ||
1130 | It is not proper to define both 'PUSH_ROUNDING' and | |
bf0e974b | 1131 | 'ACCUMULATE_OUTGOING_ARGS'. */ |
f73ad30e | 1132 | #define ACCUMULATE_OUTGOING_ARGS 1 |
946730d0 RK |
1133 | |
1134 | /* Offset of first parameter from the argument pointer | |
bf0e974b | 1135 | register value. */ |
946730d0 RK |
1136 | |
1137 | #define FIRST_PARM_OFFSET(FNDECL) (0) | |
1138 | ||
1139 | /* Value is 1 if returning from a function call automatically | |
1140 | pops the arguments described by the number-of-args field in the call. | |
8b109b37 | 1141 | FUNDECL is the declaration node of the function (as a tree), |
946730d0 | 1142 | FUNTYPE is the data type of the function (as a tree), |
bf0e974b | 1143 | or for a library call it is an identifier node for the subroutine name. */ |
946730d0 | 1144 | |
8b109b37 | 1145 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
946730d0 RK |
1146 | |
1147 | /* Define how to find the value returned by a function. | |
1148 | VALTYPE is the data type of the value (as a tree). | |
1149 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1150 | otherwise, FUNC is 0. On the 1610 all function return their values | |
1151 | in a0 (i.e. the upper 16 bits). If the return value is 32-bits the | |
bf0e974b | 1152 | entire register is significant. */ |
946730d0 RK |
1153 | |
1154 | #define VALUE_REGNO(MODE) (REG_Y) | |
1155 | ||
1156 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
d2a0c2ee | 1157 | gen_rtx_REG (TYPE_MODE (VALTYPE), VALUE_REGNO(TYPE_MODE(VALTYPE))) |
946730d0 RK |
1158 | |
1159 | /* Define how to find the value returned by a library function | |
1160 | assuming the value has mode MODE. */ | |
d2a0c2ee | 1161 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) |
946730d0 | 1162 | |
bf0e974b | 1163 | /* 1 if N is a possible register number for a function value. */ |
946730d0 RK |
1164 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_Y) |
1165 | \f | |
1166 | ||
1167 | /* Define where to put the arguments to a function. | |
1168 | Value is zero to push the argument on the stack, | |
1169 | or a hard register in which to store the argument. | |
1170 | ||
1171 | MODE is the argument's machine mode. | |
1172 | TYPE is the data type of the argument (as a tree). | |
1173 | This is null for libcalls where that information may | |
1174 | not be available. | |
1175 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1176 | the preceding args and about the function being called. | |
1177 | NAMED is nonzero if this argument is a named parameter | |
1178 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1179 | ||
1180 | /* On the 1610 all args are pushed, except if -mregparm is specified | |
bf0e974b | 1181 | then the first two words of arguments are passed in a0, a1. */ |
946730d0 RK |
1182 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1183 | dsp16xx_function_arg (CUM, MODE, TYPE, NAMED) | |
1184 | ||
1185 | /* Define the first register to be used for argument passing */ | |
1186 | #define FIRST_REG_FOR_FUNCTION_ARG REG_Y | |
1187 | ||
ddd5a7c1 RK |
1188 | /* Define the profitability of saving registers around calls. |
1189 | NOTE: For now we turn this off because of a bug in the | |
946730d0 | 1190 | caller-saves code and also because i'm not sure it is helpful |
bf0e974b | 1191 | on the 1610. */ |
946730d0 RK |
1192 | |
1193 | #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 | |
1194 | ||
1195 | /* This indicates that an argument is to be passed with an invisible reference | |
1196 | (i.e., a pointer to the object is passed). | |
1197 | ||
1198 | On the dsp16xx, we do this if it must be passed on the stack. */ | |
1199 | ||
1200 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
1201 | (MUST_PASS_IN_STACK (MODE, TYPE)) | |
1202 | ||
1203 | /* For an arg passed partly in registers and partly in memory, | |
1204 | this is the number of registers used. | |
1205 | For args passed entirely in registers or entirely in memory, zero. */ | |
1206 | ||
1207 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0) | |
1208 | ||
1209 | /* Define a data type for recording info about an argument list | |
1210 | during the scan of that argument list. This data type should | |
1211 | hold all necessary information about the function itself | |
1212 | and about the args processed so far, enough to enable macros | |
bf0e974b | 1213 | such as FUNCTION_ARG to determine where the next arg should go. */ |
946730d0 RK |
1214 | #define CUMULATIVE_ARGS int |
1215 | ||
1216 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1217 | for a call to a function whose data type is FNTYPE. | |
bf0e974b | 1218 | For a library call, FNTYPE is 0. */ |
2c7ee1a6 | 1219 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) ((CUM) = 0) |
946730d0 RK |
1220 | |
1221 | /* Update the data in CUM to advance over an argument | |
1222 | of mode MODE and data type TYPE. | |
1223 | (TYPE is null for libcalls where that information may not be available.) */ | |
1224 | ||
1225 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1226 | dsp16xx_function_arg_advance (&CUM, MODE,TYPE, NAMED) | |
1227 | ||
bf0e974b | 1228 | /* 1 if N is a possible register number for function argument passing. */ |
946730d0 RK |
1229 | #define FUNCTION_ARG_REGNO_P(N) \ |
1230 | ((N) == REG_Y || (N) == REG_YL || (N) == REG_PROD || (N) == REG_PRODL) | |
1231 | ||
946730d0 | 1232 | /* Output assembler code to FILE to increment profiler label # LABELNO |
bf0e974b | 1233 | for profiling a function entry. */ |
946730d0 | 1234 | |
c4636dd1 | 1235 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
c725bd79 | 1236 | internal_error ("profiling not implemented yet") |
946730d0 RK |
1237 | |
1238 | /* Output assembler code to FILE to initialize this source file's | |
bf0e974b | 1239 | basic block profiling info, if that has not already been done. */ |
c4636dd1 | 1240 | #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ |
c725bd79 | 1241 | internal_error ("profiling not implemented yet") |
946730d0 RK |
1242 | |
1243 | /* Output assembler code to FILE to increment the entry-count for | |
bf0e974b | 1244 | the BLOCKNO'th basic block in this source file. */ |
c4636dd1 | 1245 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ |
c725bd79 | 1246 | internal_error ("profiling not implemented yet") |
946730d0 RK |
1247 | |
1248 | ||
1249 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1250 | the stack pointer does not matter. The value is tested only in | |
1251 | functions that have frame pointers. | |
1252 | No definition is equivalent to always zero. */ | |
1253 | ||
1254 | #define EXIT_IGNORE_STACK (0) | |
1255 | ||
c4636dd1 | 1256 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
c725bd79 | 1257 | internal_error ("trampolines not yet implemented"); |
946730d0 RK |
1258 | |
1259 | /* Length in units of the trampoline for entering a nested function. | |
1260 | This is a dummy value */ | |
1261 | ||
1262 | #define TRAMPOLINE_SIZE 20 | |
1263 | ||
1264 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1265 | FNADDR is an RTX for the address of the function's pure code. | |
bf0e974b | 1266 | CXT is an RTX for the static chain value for the function. */ |
946730d0 RK |
1267 | |
1268 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
c725bd79 | 1269 | internal_error ("trampolines not yet implemented"); |
946730d0 | 1270 | |
946730d0 RK |
1271 | /* A C expression which is nonzero if a function must have and use a |
1272 | frame pointer. If its value is nonzero the functions will have a | |
bf0e974b | 1273 | frame pointer. */ |
946730d0 RK |
1274 | #define FRAME_POINTER_REQUIRED (current_function_calls_alloca) |
1275 | ||
1276 | /* A C statement to store in the variable 'DEPTH' the difference | |
1277 | between the frame pointer and the stack pointer values immediately | |
bf0e974b | 1278 | after the function prologue. */ |
946730d0 RK |
1279 | #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ |
1280 | { (DEPTH) = initial_frame_pointer_offset(); \ | |
1281 | } | |
1282 | \f | |
1283 | /* IMPLICIT CALLS TO LIBRARY ROUTINES */ | |
1284 | ||
1285 | #define ADDHF3_LIBCALL "__Emulate_addhf3" | |
1286 | #define SUBHF3_LIBCALL "__Emulate_subhf3" | |
1287 | #define MULHF3_LIBCALL "__Emulate_mulhf3" | |
1288 | #define DIVHF3_LIBCALL "__Emulate_divhf3" | |
1289 | #define CMPHF3_LIBCALL "__Emulate_cmphf3" | |
1290 | #define FIXHFHI2_LIBCALL "__Emulate_fixhfhi2" | |
1291 | #define FLOATHIHF2_LIBCALL "__Emulate_floathihf2" | |
1292 | #define NEGHF2_LIBCALL "__Emulate_neghf2" | |
1293 | ||
1294 | #define UMULHI3_LIBCALL "__Emulate_umulhi3" | |
1295 | #define MULHI3_LIBCALL "__Emulate_mulhi3" | |
1296 | #define UDIVQI3_LIBCALL "__Emulate_udivqi3" | |
1297 | #define UDIVHI3_LIBCALL "__Emulate_udivhi3" | |
1298 | #define DIVQI3_LIBCALL "__Emulate_divqi3" | |
1299 | #define DIVHI3_LIBCALL "__Emulate_divhi3" | |
1300 | #define MODQI3_LIBCALL "__Emulate_modqi3" | |
1301 | #define MODHI3_LIBCALL "__Emulate_modhi3" | |
1302 | #define UMODQI3_LIBCALL "__Emulate_umodqi3" | |
1303 | #define UMODHI3_LIBCALL "__Emulate_umodhi3" | |
1304 | #define ASHRHI3_LIBCALL "__Emulate_ashrhi3" | |
1305 | #define LSHRHI3_LIBCALL "__Emulate_lshrhi3" | |
1306 | #define ASHLHI3_LIBCALL "__Emulate_ashlhi3" | |
1307 | #define LSHLHI3_LIBCALL "__Emulate_lshlhi3" /* NOT USED */ | |
1308 | ||
1309 | /* Define this macro if calls to the ANSI C library functions memcpy and | |
bf0e974b | 1310 | memset should be generated instead of the BSD function bcopy & bzero. */ |
946730d0 RK |
1311 | #define TARGET_MEM_FUNCTIONS |
1312 | ||
1313 | \f | |
1314 | /* ADDRESSING MODES */ | |
1315 | ||
1316 | /* The 1610 has post-increment and decrement, but no pre-modify */ | |
940da324 JL |
1317 | #define HAVE_POST_INCREMENT 1 |
1318 | #define HAVE_POST_DECREMENT 1 | |
946730d0 | 1319 | |
940da324 JL |
1320 | /* #define HAVE_PRE_DECREMENT 0 */ |
1321 | /* #define HAVE_PRE_INCREMENT 0 */ | |
946730d0 RK |
1322 | |
1323 | /* Recognize any constant value that is a valid address. */ | |
1324 | #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X) | |
1325 | ||
1326 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1327 | #define MAX_REGS_PER_ADDRESS 1 | |
1328 | ||
1329 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1330 | and check its validity for a certain class. | |
1331 | We have two alternate definitions for each of them. | |
1332 | The usual definition accepts all pseudo regs; the other rejects | |
1333 | them unless they have been allocated suitable hard regs. | |
1334 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1335 | ||
1336 | Most source files want to accept pseudo regs in the hope that | |
1337 | they will get allocated to the class that the insn wants them to be in. | |
1338 | Source files for reload pass need to be strict. | |
1339 | After reload, it makes no difference, since pseudo regs have | |
1340 | been eliminated by then. */ | |
1341 | ||
1342 | #ifndef REG_OK_STRICT | |
1343 | ||
1344 | /* Nonzero if X is a hard reg that can be used as an index | |
1345 | or if it is a pseudo reg. */ | |
1346 | #define REG_OK_FOR_INDEX_P(X) 0 | |
1347 | ||
1348 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1349 | or if it is a pseudo reg. */ | |
1350 | #define REG_OK_FOR_BASE_P(X) \ | |
1351 | ((REGNO (X) >= REG_R0 && REGNO (X) < REG_R3 + 1 ) \ | |
1352 | || (REGNO (X) >= FIRST_PSEUDO_REGISTER)) | |
1353 | ||
1354 | /* Nonzero if X is the 'ybase' register */ | |
1355 | #define REG_OK_FOR_YBASE_P(X) \ | |
1356 | (REGNO(X) == REG_YBASE || (REGNO (X) >= FIRST_PSEUDO_REGISTER)) | |
1357 | #else | |
1358 | ||
1359 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1360 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1361 | ||
1362 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1363 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1364 | ||
1365 | /* Nonzero if X is the 'ybase' register */ | |
1366 | #define REG_OK_FOR_YBASE_P(X) REGNO_OK_FOR_YBASE_P (REGNO(X)) | |
1367 | ||
1368 | #endif | |
1369 | \f | |
1370 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1371 | that is a valid memory address for an instruction. | |
1372 | The MODE argument is the machine mode for the MEM expression | |
1373 | that wants to use this address. | |
1374 | ||
1375 | On the 1610, the actual legitimate addresses must be N (N must fit in | |
1376 | 5 bits), *rn (register indirect), *rn++, or *rn-- */ | |
1377 | ||
1378 | #define INT_FITS_5_BITS(I) ((unsigned long) (I) < 0x20) | |
1379 | #define INT_FITS_16_BITS(I) ((unsigned long) (I) < 0x10000) | |
1380 | #define YBASE_CONST_OFFSET(I) ((I) >= -31 && (I) <= 0) | |
1381 | #define YBASE_OFFSET(X) (GET_CODE (X) == CONST_INT && YBASE_CONST_OFFSET (INTVAL(X))) | |
1382 | ||
1383 | #define FITS_16_BITS(X) (GET_CODE (X) == CONST_INT && INT_FITS_16_BITS(INTVAL(X))) | |
1384 | #define FITS_5_BITS(X) (GET_CODE (X) == CONST_INT && INT_FITS_5_BITS(INTVAL(X))) | |
1385 | #define ILLEGAL_HIMODE_ADDR(MODE, CONST) ((MODE) == HImode && CONST == -31) | |
1386 | ||
1387 | #define INDIRECTABLE_ADDRESS_P(X) \ | |
1388 | ((GET_CODE(X) == REG && REG_OK_FOR_BASE_P(X)) \ | |
1389 | || ((GET_CODE(X) == POST_DEC || GET_CODE(X) == POST_INC) \ | |
1390 | && REG_P(XEXP(X,0)) && REG_OK_FOR_BASE_P(XEXP(X,0))) \ | |
1391 | || (GET_CODE(X) == CONST_INT && (unsigned long) (X) < 0x20)) | |
1392 | ||
1393 | ||
1394 | #define INDEXABLE_ADDRESS_P(X,MODE) \ | |
1395 | ((GET_CODE(X) == PLUS && GET_CODE (XEXP (X,0)) == REG && \ | |
1396 | XEXP(X,0) == stack_pointer_rtx && YBASE_OFFSET(XEXP(X,1)) && \ | |
1397 | !ILLEGAL_HIMODE_ADDR(MODE, INTVAL(XEXP(X,1)))) || \ | |
1398 | (GET_CODE(X) == PLUS && GET_CODE (XEXP (X,1)) == REG && \ | |
1399 | XEXP(X,1) == stack_pointer_rtx && YBASE_OFFSET(XEXP(X,0)) && \ | |
1400 | !ILLEGAL_HIMODE_ADDR(MODE, INTVAL(XEXP(X,0))))) | |
1401 | ||
1402 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1403 | { \ | |
1404 | if (INDIRECTABLE_ADDRESS_P(X)) \ | |
1405 | goto ADDR; \ | |
1406 | } | |
1407 | ||
1408 | \f | |
1409 | /* Try machine-dependent ways of modifying an illegitimate address | |
1410 | to be legitimate. If we find one, return the new, valid address. | |
1411 | This macro is used in only one place: `memory_address' in explow.c. | |
1412 | ||
1413 | OLDX is the address as it was before break_out_memory_refs was called. | |
1414 | In some cases it is useful to look at this to decide what needs to be done. | |
1415 | ||
1416 | MODE and WIN are passed so that this macro can use | |
1417 | GO_IF_LEGITIMATE_ADDRESS. | |
1418 | ||
1419 | It is always safe for this macro to do nothing. It exists to recognize | |
1420 | opportunities to optimize the output. | |
1421 | ||
1422 | For the 1610, we need not do anything. However, if we don't, | |
1423 | `memory_address' will try lots of things to get a valid address, most of | |
1424 | which will result in dead code and extra pseudos. So we make the address | |
1425 | valid here. | |
1426 | ||
1427 | This is easy: The only valid addresses are an offset from a register | |
1428 | and we know the address isn't valid. So just call either `force_operand' | |
1429 | or `force_reg' unless this is a (plus (reg ...) (const_int 0)). */ | |
1430 | ||
1431 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1432 | { if (GET_CODE (X) == PLUS && XEXP (X, 1) == const0_rtx) \ | |
1433 | X = XEXP (x, 0); \ | |
1434 | if (GET_CODE (X) == MULT || GET_CODE (X) == PLUS) \ | |
1435 | X = force_operand (X, 0); \ | |
1436 | else \ | |
1437 | X = force_reg (Pmode, X); \ | |
1438 | goto WIN; \ | |
1439 | } | |
1440 | ||
1441 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1442 | has an effect that depends on the machine mode it is used for. | |
1443 | On the 1610, only postdecrement and postincrement address depend thus | |
1444 | (the amount of decrement or increment being the length of the operand). */ | |
1445 | ||
1446 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1447 | if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL | |
1448 | ||
1449 | /* Nonzero if the constant value X is a legitimate general operand. | |
1450 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1451 | #define LEGITIMATE_CONSTANT_P(X) (1) | |
1452 | ||
1453 | \f | |
1454 | /* CONDITION CODE INFORMATION */ | |
1455 | ||
1456 | /* Store in cc_status the expressions | |
1457 | that the condition codes will describe | |
1458 | after execution of an instruction whose pattern is EXP. | |
bf0e974b | 1459 | Do not alter them if the instruction would not alter the cc's. */ |
946730d0 RK |
1460 | |
1461 | #define NOTICE_UPDATE_CC(EXP, INSN) \ | |
1462 | notice_update_cc( (EXP) ) | |
1463 | \f | |
1464 | /* DESCRIBING RELATIVE COSTS OF OPERATIONS */ | |
1465 | ||
1466 | /* Compute the cost of computing a constant rtl expression RTX | |
1467 | whose rtx-code is CODE. The body of this macro is a portion | |
1468 | of a switch statement. If the code is computed here, | |
bf0e974b | 1469 | return it with a return statement. */ |
946730d0 RK |
1470 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
1471 | case CONST_INT: \ | |
dff06f62 | 1472 | return (unsigned) INTVAL (RTX) < 65536 ? 0 : 2; \ |
946730d0 RK |
1473 | case LABEL_REF: \ |
1474 | case SYMBOL_REF: \ | |
1475 | case CONST: \ | |
1476 | return COSTS_N_INSNS (1); \ | |
1477 | \ | |
1478 | case CONST_DOUBLE: \ | |
1479 | return COSTS_N_INSNS (2); | |
1480 | ||
ddd5a7c1 | 1481 | /* Like CONST_COSTS but applies to nonconstant RTL expressions. |
946730d0 | 1482 | This can be used, for example to indicate how costly a multiply |
bf0e974b | 1483 | instruction is. */ |
946730d0 RK |
1484 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
1485 | case MEM: \ | |
1486 | return GET_MODE (X) == QImode ? COSTS_N_INSNS (2) : \ | |
1487 | COSTS_N_INSNS (4); \ | |
1488 | case DIV: \ | |
1489 | case MOD: \ | |
1490 | return COSTS_N_INSNS (38); \ | |
1491 | case MULT: \ | |
1492 | if (GET_MODE (X) == QImode) \ | |
1493 | return COSTS_N_INSNS (2); \ | |
1494 | else \ | |
1495 | return COSTS_N_INSNS (38); \ | |
1496 | case PLUS: \ | |
946730d0 RK |
1497 | case MINUS: \ |
1498 | if (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ | |
946730d0 | 1499 | { \ |
dff06f62 MC |
1500 | return (1 + \ |
1501 | rtx_cost (XEXP (X, 0), CODE) + \ | |
1502 | rtx_cost (XEXP (X, 1), CODE)); \ | |
946730d0 | 1503 | } \ |
946730d0 RK |
1504 | else \ |
1505 | return COSTS_N_INSNS (38); \ | |
dff06f62 | 1506 | \ |
946730d0 | 1507 | case AND: case IOR: case XOR: \ |
dff06f62 MC |
1508 | return (1 + \ |
1509 | rtx_cost (XEXP (X, 0), CODE) + \ | |
1510 | rtx_cost (XEXP (X, 1), CODE)); \ | |
1511 | \ | |
946730d0 RK |
1512 | case NEG: case NOT: \ |
1513 | return COSTS_N_INSNS (1); \ | |
1514 | case ASHIFT: \ | |
1515 | case ASHIFTRT: \ | |
946730d0 RK |
1516 | case LSHIFTRT: \ |
1517 | if (GET_CODE (XEXP (X,1)) == CONST_INT) \ | |
1518 | { \ | |
1519 | int number = INTVAL(XEXP (X,1)); \ | |
1520 | if (number == 1 || number == 4 || number == 8 || \ | |
1521 | number == 16) \ | |
1522 | return COSTS_N_INSNS (1); \ | |
1523 | else \ | |
dff06f62 MC |
1524 | { \ |
1525 | if (TARGET_BMU) \ | |
946730d0 | 1526 | return COSTS_N_INSNS (2); \ |
dff06f62 MC |
1527 | else \ |
1528 | return COSTS_N_INSNS (num_1600_core_shifts(number)); \ | |
1529 | } \ | |
946730d0 | 1530 | } \ |
dff06f62 MC |
1531 | if (TARGET_BMU) \ |
1532 | return COSTS_N_INSNS (1); \ | |
1533 | else \ | |
1534 | return COSTS_N_INSNS (15); | |
946730d0 RK |
1535 | |
1536 | /* An expression giving the cost of an addressing mode that contains | |
bf0e974b | 1537 | address. */ |
946730d0 RK |
1538 | #define ADDRESS_COST(ADDR) dsp16xx_address_cost (ADDR) |
1539 | ||
1540 | /* A c expression for the cost of moving data from a register in | |
1541 | class FROM to one in class TO. The classes are expressed using | |
1542 | the enumeration values such as GENERAL_REGS. A value of 2 is | |
bf0e974b | 1543 | the default. */ |
cf011243 | 1544 | #define REGISTER_MOVE_COST(MODE,FROM,TO) dsp16xx_register_move_cost (FROM, TO) |
946730d0 RK |
1545 | |
1546 | /* A C expression for the cost of moving data of mode MODE between | |
bf0e974b | 1547 | a register and memory. A value of 2 is the default. */ |
f5963e61 | 1548 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ |
946730d0 RK |
1549 | (GET_MODE_CLASS(MODE) == MODE_INT && MODE == QImode ? 12 \ |
1550 | : 16) | |
1551 | ||
1552 | /* A C expression for the cost of a branch instruction. A value of | |
1553 | 1 is the default; */ | |
dff06f62 | 1554 | #define BRANCH_COST 1 |
946730d0 RK |
1555 | \f |
1556 | ||
1557 | /* Define this because otherwise gcc will try to put the function address | |
bf0e974b | 1558 | in any old pseudo register. We can only use pt. */ |
946730d0 RK |
1559 | #define NO_FUNCTION_CSE |
1560 | ||
1561 | /* Define this macro as a C expression which is nonzero if accessing less | |
1562 | than a word of memory (i.e a char or short) is no faster than accessing | |
1563 | a word of memory, i.e if such access require more than one instruction | |
1564 | or if ther is no difference in cost between byte and (aligned) word | |
bf0e974b | 1565 | loads. */ |
946730d0 RK |
1566 | #define SLOW_BYTE_ACCESS 1 |
1567 | ||
1568 | /* Define this macro if zero-extension (of a char or short to an int) can | |
bf0e974b | 1569 | be done faster if the destination is a register that is know to be zero. */ |
946730d0 RK |
1570 | /* #define SLOW_ZERO_EXTEND */ |
1571 | ||
1572 | /* Define this macro if unaligned accesses have a cost many times greater than | |
1573 | aligned accesses, for example if they are emulated in a trap handler */ | |
e1565e65 | 1574 | /* define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) */ |
946730d0 RK |
1575 | |
1576 | /* Define this macro to inhibit strength reduction of memory addresses */ | |
1577 | /* #define DONT_REDUCE_ADDR */ | |
1578 | ||
1579 | \f | |
1580 | /* DIVIDING THE OUTPUT IN SECTIONS */ | |
1581 | /* Output before read-only data. */ | |
1582 | ||
1583 | #define DEFAULT_TEXT_SEG_NAME ".text" | |
1584 | #define TEXT_SECTION_ASM_OP rsect_text | |
1585 | ||
1586 | /* Output before constants and strings */ | |
1587 | #define DEFAULT_CONST_SEG_NAME ".const" | |
1588 | #define READONLY_SECTION_ASM_OP rsect_const | |
1589 | #define READONLY_DATA_SECTION const_section | |
1590 | ||
1591 | /* Output before writable data. */ | |
1592 | #define DEFAULT_DATA_SEG_NAME ".data" | |
1593 | #define DATA_SECTION_ASM_OP rsect_data | |
1594 | ||
1595 | #define DEFAULT_BSS_SEG_NAME ".bss" | |
1596 | #define BSS_SECTION_ASM_OP rsect_bss | |
1597 | ||
1598 | /* We will default to using 1610 if the user doesn't | |
bf0e974b | 1599 | specify it. */ |
946730d0 RK |
1600 | #define DEFAULT_CHIP_NAME "1610" |
1601 | ||
a02303b8 | 1602 | /* A list of names for sections other than the standard ones, which are |
bf0e974b | 1603 | 'in_text' and 'in_data' (and .bss if BSS_SECTION_ASM_OP is defined). */ |
a02303b8 | 1604 | #define EXTRA_SECTIONS in_const |
946730d0 RK |
1605 | |
1606 | #define EXTRA_SECTION_FUNCTIONS \ | |
55710451 | 1607 | extern void const_section PARAMS ((void)); \ |
946730d0 RK |
1608 | void \ |
1609 | const_section () \ | |
1610 | { \ | |
1611 | if (in_section != in_const) \ | |
1612 | { \ | |
1613 | fprintf (asm_out_file, "%s\n", READONLY_SECTION_ASM_OP); \ | |
1614 | in_section = in_const; \ | |
1615 | } \ | |
946730d0 | 1616 | } |
946730d0 RK |
1617 | \f |
1618 | /* THE OVERALL FRAMEWORK OF AN ASSEMBLER FILE */ | |
1619 | ||
1620 | /* Output at beginning of assembler file. */ | |
dff06f62 MC |
1621 | #define ASM_FILE_START(FILE) coff_dsp16xx_file_start (FILE) |
1622 | ||
1623 | /* Prevent output of .gcc_compiled */ | |
1624 | #define ASM_IDENTIFY_GCC(FILE) | |
946730d0 | 1625 | |
946730d0 | 1626 | /* A C string constant describing how to begin a comment in the target |
bf0e974b | 1627 | assembler language. */ |
dff06f62 MC |
1628 | #define ASM_COMMENT_START "" |
1629 | #define ASM_COMMENT_END "" | |
946730d0 RK |
1630 | |
1631 | /* Output to assembler file text saying following lines | |
1632 | may contain character constants, extra white space, comments, etc. */ | |
1633 | #define ASM_APP_ON "" | |
1634 | ||
1635 | /* Output to assembler file text saying following lines | |
1636 | no longer contain unusual constructs. */ | |
1637 | #define ASM_APP_OFF "" | |
1638 | \f | |
1639 | /* OUTPUT OF DATA */ | |
1640 | ||
946730d0 RK |
1641 | /* This is how we output a 'c' character string. For the 16xx |
1642 | assembler we have to do it one letter at a time */ | |
1643 | ||
1644 | #define ASCII_LENGTH 10 | |
1645 | ||
1646 | #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ | |
1647 | do { \ | |
1648 | FILE *_hide_asm_out_file = (MYFILE); \ | |
69985118 | 1649 | const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \ |
946730d0 RK |
1650 | int _hide_thissize = (MYLENGTH); \ |
1651 | { \ | |
1652 | FILE *asm_out_file = _hide_asm_out_file; \ | |
69985118 | 1653 | const unsigned char *p = _hide_p; \ |
946730d0 RK |
1654 | int thissize = _hide_thissize; \ |
1655 | int i; \ | |
1656 | \ | |
1657 | for (i = 0; i < thissize; i++) \ | |
1658 | { \ | |
1659 | register int c = p[i]; \ | |
1660 | \ | |
1661 | if (i % ASCII_LENGTH == 0) \ | |
1662 | fprintf (asm_out_file, "\tint "); \ | |
1663 | \ | |
1664 | if (c >= ' ' && c < 0177 && c != '\'') \ | |
1665 | { \ | |
1666 | putc ('\'', asm_out_file); \ | |
1667 | putc (c, asm_out_file); \ | |
1668 | putc ('\'', asm_out_file); \ | |
1669 | } \ | |
1670 | else \ | |
1671 | { \ | |
1672 | fprintf (asm_out_file, "%d", c); \ | |
1673 | /* After an octal-escape, if a digit follows, \ | |
1674 | terminate one string constant and start another. \ | |
dff06f62 | 1675 | The Vax assembler fails to stop reading the escape \ |
946730d0 RK |
1676 | after three digits, so this is the only way we \ |
1677 | can get it to parse the data properly. \ | |
0df6c2c7 | 1678 | if (i < thissize - 1 && ISDIGIT (p[i + 1])) \ |
946730d0 RK |
1679 | fprintf (asm_out_file, "\'\n\tint \'"); \ |
1680 | */ \ | |
1681 | } \ | |
1682 | /* if: \ | |
1683 | we are not at the last char (i != thissize -1) \ | |
1684 | and (we are not at a line break multiple \ | |
1685 | but i == 0) (it will be the very first time) \ | |
1686 | then put out a comma to extend. \ | |
1687 | */ \ | |
1688 | if ((i != thissize - 1) && ((i + 1) % ASCII_LENGTH)) \ | |
1689 | fprintf(asm_out_file, ","); \ | |
1690 | if (!((i + 1) % ASCII_LENGTH)) \ | |
1691 | fprintf (asm_out_file, "\n"); \ | |
1692 | } \ | |
1693 | fprintf (asm_out_file, "\n"); \ | |
1694 | } \ | |
1695 | } \ | |
1696 | while (0) | |
1697 | ||
1698 | /* Store in OUTPUT a string (made with alloca) containing | |
1699 | an assembler-name for a local static variable or function | |
1700 | named NAME. LABELNO is an integer which is different for | |
bf0e974b | 1701 | each call. */ |
946730d0 RK |
1702 | |
1703 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1704 | do { \ | |
1705 | int len = strlen (NAME); \ | |
1706 | char *temp = (char *) alloca (len + 3); \ | |
1707 | temp[0] = 'L'; \ | |
1708 | strcpy (&temp[1], (NAME)); \ | |
1709 | temp[len + 1] = '_'; \ | |
1710 | temp[len + 2] = 0; \ | |
1711 | (OUTPUT) = (char *) alloca (strlen (NAME) + 11); \ | |
1712 | ASM_GENERATE_INTERNAL_LABEL (OUTPUT, temp, LABELNO); \ | |
1713 | } while (0) | |
946730d0 RK |
1714 | \f |
1715 | /* OUTPUT OF UNINITIALIZED VARIABLES */ | |
1716 | ||
1717 | /* This says how to output an assembler line | |
1718 | to define a global common symbol. */ | |
1719 | ||
1720 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1721 | asm_output_common (FILE, NAME, SIZE, ROUNDED); | |
1722 | ||
1723 | /* This says how to output an assembler line | |
1724 | to define a local common symbol. */ | |
1725 | ||
1726 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1727 | asm_output_local (FILE, NAME, SIZE, ROUNDED); | |
1728 | \f | |
1729 | /* OUTPUT AND GENERATION OF LABELS */ | |
1730 | ||
1731 | /* This is how to output the definition of a user-level label named NAME, | |
1732 | such as the label on a static function or variable NAME. */ | |
1733 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1734 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1735 | ||
1736 | /* This is how to output a command to make the user-level label named NAME | |
1737 | defined for reference from other files. */ | |
1738 | ||
1739 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
1740 | do { fputs (".global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) | |
1741 | ||
1742 | /* A C statement to output to the stdio stream any text necessary | |
1743 | for declaring the name of an external symbol named name which | |
bf0e974b | 1744 | is referenced in this compilation but not defined. */ |
946730d0 RK |
1745 | |
1746 | #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ | |
1747 | { \ | |
1748 | fprintf (FILE, ".extern "); \ | |
1749 | assemble_name (FILE, NAME); \ | |
1750 | fprintf (FILE, "\n"); \ | |
1751 | } | |
1752 | /* A C statement to output on stream an assembler pseudo-op to | |
bf0e974b | 1753 | declare a library function named external. */ |
946730d0 RK |
1754 | |
1755 | #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ | |
1756 | { \ | |
1757 | fprintf (FILE, ".extern "); \ | |
1758 | assemble_name (FILE, XSTR (FUN, 0)); \ | |
1759 | fprintf (FILE, "\n"); \ | |
1760 | } | |
4e0c8ad2 | 1761 | |
bf0e974b | 1762 | /* The prefix to add to user-visible assembler symbols. */ |
4e0c8ad2 RK |
1763 | |
1764 | #define USER_LABEL_PREFIX "_" | |
946730d0 RK |
1765 | |
1766 | /* This is how to output an internal numbered label where | |
1767 | PREFIX is the class of label and NUM is the number within the class. */ | |
1768 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
1769 | fprintf (FILE, "%s%d:\n", PREFIX, NUM) | |
1770 | ||
1771 | /* This is how to store into the string LABEL | |
1772 | the symbol_ref name of an internal numbered label where | |
1773 | PREFIX is the class of label and NUM is the number within the class. | |
1774 | This is suitable for output with `assemble_name'. */ | |
1775 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
1776 | sprintf (LABEL, "*%s%d", PREFIX, NUM) | |
1777 | ||
1778 | \f | |
1779 | /* OUTPUT OF ASSEMBLER INSTRUCTIONS */ | |
1780 | ||
1781 | /* How to refer to registers in assembler output. | |
1782 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1783 | ||
1784 | #define REGISTER_NAMES \ | |
1785 | {"a0", "a0l", "a1", "a1l", "x", "y", "yl", "p", "pl", \ | |
1786 | "r0", "r1", "r2", "r3", "j", "k", "ybase", "pt", \ | |
1787 | "ar0", "ar1", "ar2", "ar3", \ | |
1788 | "c0", "c1", "c2", "pr", "rb", \ | |
1789 | "*(0)", "*(1)", "*(2)", "*(3)", "*(4)", "*(5)", \ | |
1790 | "*(6)", "*(7)", "*(8)", "*(9)", "*(10)", "*(11)", \ | |
1791 | "*(12)", "*(13)", "*(14)", "*(15)", "*(16)", "*(17)", \ | |
1792 | "*(18)", "*(19)", "*(20)", "*(21)", "*(22)", "*(23)", \ | |
1793 | "*(24)", "*(25)", "*(26)", "*(27)", "*(28)", "*(29)", \ | |
1794 | "*(30)", "*(31)" } | |
1795 | ||
1796 | #define HIMODE_REGISTER_NAMES \ | |
1797 | {"a0", "a0", "a1", "a1", "x", "y", "y", "p", "p", \ | |
1798 | "r0", "r1", "r2", "r3", "j", "k", "ybase", "pt", \ | |
1799 | "ar0", "ar1", "ar2", "ar3", \ | |
1800 | "c0", "c1", "c2", "pr", "rb", \ | |
1801 | "*(0)", "*(1)", "*(2)", "*(3)", "*(4)", "*(5)", \ | |
1802 | "*(6)", "*(7)", "*(8)", "*(9)", "*(10)", "*(11)", \ | |
1803 | "*(12)", "*(13)", "*(14)", "*(15)", "*(16)", "*(17)", \ | |
1804 | "*(18)", "*(19)", "*(20)", "*(21)", "*(22)", "*(23)", \ | |
1805 | "*(24)", "*(25)", "*(26)", "*(27)", "*(28)", "*(29)", \ | |
1806 | "*(30)", "*(31)" } | |
1807 | ||
1808 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) 0 | |
1809 | ||
1810 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1811 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1812 | For `%' followed by punctuation, CODE is the punctuation and X is null. | |
1813 | ||
1814 | DSP1610 extensions for operand codes: | |
1815 | ||
1816 | %H - print lower 16 bits of constant | |
1817 | %U - print upper 16 bits of constant | |
1818 | %w - print low half of register (e.g 'a0l') | |
1819 | %u - print upper half of register (e.g 'a0') | |
1820 | %b - print high half of accumulator for F3 ALU instructions | |
1821 | %h - print constant in decimal */ | |
1822 | ||
1823 | #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) | |
1824 | ||
1825 | ||
bf0e974b | 1826 | /* Print a memory address as an operand to reference that memory location. */ |
946730d0 RK |
1827 | |
1828 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
1829 | ||
1830 | /* This is how to output an insn to push a register on the stack. | |
1831 | It need not be very fast code since it is used only for profiling */ | |
c4636dd1 | 1832 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ |
c725bd79 | 1833 | internal_error ("profiling not implemented yet"); |
946730d0 RK |
1834 | |
1835 | /* This is how to output an insn to pop a register from the stack. | |
1836 | It need not be very fast code since it is used only for profiling */ | |
c4636dd1 | 1837 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ |
c725bd79 | 1838 | internal_error ("profiling not implemented yet"); |
946730d0 RK |
1839 | \f |
1840 | /* OUTPUT OF DISPATCH TABLES */ | |
1841 | ||
1842 | /* This macro should be provided on machines where the addresses in a dispatch | |
bf0e974b | 1843 | table are relative to the table's own address. */ |
33f7f353 | 1844 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
946730d0 RK |
1845 | fprintf (FILE, "\tint L%d-L%d\n", VALUE, REL) |
1846 | ||
1847 | /* This macro should be provided on machines where the addresses in a dispatch | |
bf0e974b | 1848 | table are absolute. */ |
946730d0 RK |
1849 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ |
1850 | fprintf (FILE, "\tint L%d\n", VALUE) | |
1851 | ||
1852 | /* ASSEMBLER COMMANDS FOR ALIGNMENT */ | |
1853 | ||
1854 | /* This is how to output an assembler line that says to advance | |
1855 | the location counter to a multiple of 2**LOG bytes. We should | |
bf0e974b | 1856 | not have to do any alignment since the 1610 is a word machine. */ |
946730d0 RK |
1857 | #define ASM_OUTPUT_ALIGN(FILE,LOG) |
1858 | ||
1859 | /* Define this macro if ASM_OUTPUT_SKIP should not be used in the text section | |
bf0e974b | 1860 | because it fails to put zero1 in the bytes that are skipped. */ |
946730d0 RK |
1861 | #define ASM_NO_SKIP_IN_TEXT 1 |
1862 | ||
1863 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1864 | fprintf (FILE, "\t%d * int 0\n", (SIZE)) | |
1865 | ||
1866 | /* CONTROLLING DEBUGGING INFORMATION FORMAT */ | |
1867 | ||
dff06f62 | 1868 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG |
946730d0 | 1869 | |
dff06f62 MC |
1870 | #define ASM_OUTPUT_DEF(asm_out_file, LABEL1, LABEL2) \ |
1871 | do { \ | |
1872 | fprintf (asm_out_file, ".alias " ); \ | |
1873 | ASM_OUTPUT_LABELREF(asm_out_file, LABEL1); \ | |
1874 | fprintf (asm_out_file, "=" ); \ | |
1875 | ASM_OUTPUT_LABELREF(asm_out_file, LABEL2); \ | |
1876 | fprintf (asm_out_file, "\n" ); \ | |
1877 | } while (0) | |
946730d0 | 1878 | |
946730d0 RK |
1879 | \f |
1880 | /* MISCELLANEOUS PARAMETERS */ | |
1881 | ||
1882 | /* Specify the machine mode that this machine uses | |
1883 | for the index in the tablejump instruction. */ | |
1884 | #define CASE_VECTOR_MODE QImode | |
1885 | ||
18543a22 ILT |
1886 | /* Define as C expression which evaluates to nonzero if the tablejump |
1887 | instruction expects the table to contain offsets from the address of the | |
1888 | table. | |
bf0e974b | 1889 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 1890 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ |
946730d0 RK |
1891 | |
1892 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1893 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1894 | ||
1895 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1896 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1897 | ||
946730d0 RK |
1898 | /* Max number of bytes we can move from memory to memory |
1899 | in one reasonably fast instruction. */ | |
1900 | #define MOVE_MAX 1 | |
1901 | ||
1902 | /* Defining this macro causes the compiler to omit a sign-extend, zero-extend, | |
1903 | or bitwise 'and' instruction that truncates the count of a shift operation | |
1904 | to a width equal to the number of bits needed to represent the size of the | |
ddd5a7c1 | 1905 | object being shifted. Do not define this macro unless the truncation applies |
bf0e974b | 1906 | to both shift operations and bit-field operations (if any). */ |
946730d0 RK |
1907 | /* #define SHIFT_COUNT_TRUNCATED */ |
1908 | ||
1909 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1910 | is done just by pretending it is already truncated. */ | |
1911 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1912 | ||
1913 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
cb560352 | 1914 | #define PROMOTE_PROTOTYPES 1 |
946730d0 RK |
1915 | |
1916 | /* An alias for the machine mode used for pointers */ | |
1917 | #define Pmode QImode | |
1918 | ||
1919 | /* A function address in a call instruction | |
1920 | is a byte address (for indexing purposes) | |
1921 | so give the MEM rtx a byte's mode. */ | |
1922 | #define FUNCTION_MODE QImode | |
1923 | ||
1924 | #if !defined(__DATE__) | |
1925 | #define TARGET_VERSION fprintf (stderr, " (%s)", VERSION_INFO1) | |
1926 | #else | |
1927 | #define TARGET_VERSION fprintf (stderr, " (%s, %s)", VERSION_INFO1, __DATE__) | |
1928 | #endif | |
1929 | ||
dff06f62 | 1930 | #define VERSION_INFO1 "Lucent DSP16xx C Cross Compiler, version 1.3.0b" |
946730d0 RK |
1931 | |
1932 | ||
1933 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1934 | #define DEFAULT_SIGNED_CHAR 1 | |
1935 | ||
946730d0 | 1936 | /* Define this so gcc does not output a call to __main, since we |
bf0e974b | 1937 | are not currently supporting c++. */ |
946730d0 | 1938 | #define INIT_SECTION_ASM_OP 1 |
ab87f8c8 | 1939 |