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35d965d5 1/* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
8b109b37 2 Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
35d965d5 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 4 and Martin Simmons (@harleqn.co.uk).
ff9940b0
RE		 5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
35d965d5
RS		 7This file is part of GNU CC.
8
9GNU CC is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14GNU CC is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with GNU CC; see the file COPYING. If not, write to
21the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
ea7273ae 23/* Sometimes the directive `riscos' is checked. This does not imply that this
35d965d5
RS		 24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
7bc7696c
RE		 27extern void output_func_prologue ();
28extern void output_func_epilogue ();
35d965d5
RS		 29extern char *output_add_immediate ();
30extern char *output_call ();
ff9940b0 31extern char *output_call_mem ();
35d965d5
RS		 32extern char *output_move_double ();
33extern char *output_mov_double_fpu_from_arm ();
34extern char *output_mov_double_arm_from_fpu ();
7fc6c9f0
RK		 35extern char *output_mov_long_double_fpu_from_arm ();
36extern char *output_mov_long_double_arm_from_fpu ();
37extern char *output_mov_long_double_arm_from_arm ();
35d965d5
RS		 38extern char *output_mov_immediate ();
39extern char *output_multi_immediate ();
ff9940b0
RE		 40extern char *output_return_instruction ();
41extern char *output_load_symbol ();
42extern char *fp_immediate_constant ();
43extern struct rtx_def *gen_compare_reg ();
44extern struct rtx_def *arm_gen_store_multiple ();
45extern struct rtx_def *arm_gen_load_multiple ();
46
47extern char *arm_condition_codes[];
48
49/* This is needed by the tail-calling peepholes */
50extern int frame_pointer_needed;
51
35d965d5 52\f
ff9940b0
RE		 53#ifndef CPP_PREDEFINES
54#define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
55#endif
35d965d5 56
ff9940b0
RE		 57#ifndef CPP_SPEC
58#define CPP_SPEC "%{m6:-D__arm6__}"
35d965d5
RS		 59#endif
60\f
61/* Run-time Target Specification. */
ff9940b0 62#ifndef TARGET_VERSION
35d965d5 63#define TARGET_VERSION \
ff9940b0
RE		 64 fputs (" (ARM/generic)", stderr);
65#endif
35d965d5
RS		 66
67/* Run-time compilation parameters selecting different hardware subsets.
68 On the ARM, misuse it in a different way. */
69extern int target_flags;
70
71/* Nonzero if the function prologue (and epilogue) should obey
72 the ARM Procedure Call Standard. */
73#define TARGET_APCS (target_flags & 1)
74
75/* Nonzero if the function prologue should output the function name to enable
76 the post mortem debugger to print a backtrace (very useful on RISCOS,
77 unused on RISCiX). Specifying this flag also enables -mapcs.
78 XXX Must still be implemented in the prologue. */
79#define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
80
81/* Nonzero if floating point instructions are emulated by the FPE, in which
82 case instruction scheduling becomes very uninteresting. */
83#define TARGET_FPE (target_flags & 4)
84
ff9940b0
RE		 85/* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
86 of condition flags when returning from a branch & link (ie. a function) */
87#define TARGET_6 (target_flags & 8)
88
2ce9c1b9
RE		 89/* Leave some bits for new processor variants */
90
91/* Nonzero if shorts must be loaded byte at a time. This is not necessary
92 for the arm processor chip, but it is needed for some MMU chips. */
93#define TARGET_SHORT_BY_BYTES (target_flags & 0x200)
94
3ada8e17
DE		 95/* Nonzero if GCC should use a floating point library.
96 GCC will assume the fp regs don't exist and will not emit any fp insns.
97 Note that this is different than fp emulation which still uses fp regs
98 and insns - the kernel catches the trap and performs the operation. */
99#define TARGET_SOFT_FLOAT (target_flags & 0x400)
100#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
101
102/* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
103 Bit 31 is reserved. See riscix.h. */
104#ifndef SUBTARGET_SWITCHES
105#define SUBTARGET_SWITCHES
ff9940b0
RE		 106#endif
107
2ce9c1b9
RE		 108#define TARGET_SWITCHES \
109{ \
110 {"apcs", 1}, \
111 {"poke-function-name", 2}, \
112 {"fpe", 4}, \
113 {"6", 8}, \
114 {"2", -8}, \
115 {"3", -8}, \
116 {"short-load-bytes", (0x200)}, \
117 {"no-short-load-bytes", -(0x200)}, \
118 {"short-load-words", -(0x200)}, \
119 {"no-short-load-words", (0x200)}, \
3ada8e17
DE		 120 {"soft-float", (0x400)}, \
121 {"hard-float", -(0x400)}, \
122 SUBTARGET_SWITCHES \
2ce9c1b9 123 {"", TARGET_DEFAULT } \
35d965d5
RS		 124}
125
ff9940b0
RE		 126/* Which processor we are running on. Currently this is only used to
127 get the condition code clobbering attribute right when we are running on
128 an arm 6 */
129
130enum processor_type
131{
132 PROCESSOR_ARM2,
133 PROCESSOR_ARM3,
134 PROCESSOR_ARM6
135};
136
137/* Recast the cpu class to be the cpu attribute. */
138
139/* Recast the cpu class to be the cpu attribute. */
140#define arm_cpu_attr ((enum attr_cpu)arm_cpu)
141
142extern enum processor_type arm_cpu;
143
24f0c1b4
RE		 144/* What sort of floating point unit do we have? Hardware or software. */
145enum floating_point_type
146{
147 FP_HARD,
148 FP_SOFT
149};
150
151/* Recast the floating point class to be the floating point attribute. */
152#define arm_fpu_attr ((enum attr_fpu) arm_fpu)
153
154extern enum floating_point_type arm_fpu;
155
2ce9c1b9 156#ifndef TARGET_DEFAULT
35d965d5 157#define TARGET_DEFAULT 0
2ce9c1b9 158#endif
35d965d5
RS		 159
160#define TARGET_MEM_FUNCTIONS 1
161
162/* OVERRIDE_OPTIONS takes care of the following:
163 - if -mpoke-function-name, then -mapcs.
164 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
165 - if floating point is done by emulation, forget about instruction
166 scheduling. Note that this only saves compilation time; it doesn't
167 matter for the final code. */
35d965d5
RS		 168
169#define OVERRIDE_OPTIONS \
170{ \
ff9940b0
RE		 171 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
172 warning ("-g without a frame pointer may not give sensible debugging");\
173 if (TARGET_POKE_FUNCTION_NAME) \
35d965d5
RS		 174 target_flags |= 1; \
175 if (TARGET_FPE) \
176 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
ff9940b0 177 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
35d965d5 178}
35d965d5
RS		 179\f
180/* Target machine storage Layout. */
181
ff9940b0
RE		 182
183/* Define this macro if it is advisable to hold scalars in registers
184 in a wider mode than that declared by the program. In such cases,
185 the value is constrained to be within the bounds of the declared
186 type, but kept valid in the wider mode. The signedness of the
187 extension may differ from that of the type. */
188
189/* It is far faster to zero extend chars than to sign extend them */
190
191#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
2ce9c1b9
RE		 192 if (GET_MODE_CLASS (MODE) == MODE_INT \
193 && GET_MODE_SIZE (MODE) < 4) \
194 { \
195 if (MODE == QImode) \
196 UNSIGNEDP = 1; \
197 else if (MODE == HImode) \
198 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
199 (MODE) = SImode; \
ff9940b0
RE		 200 }
201
202/* Define for XFmode extended real floating point support.
203 This will automatically cause REAL_ARITHMETIC to be defined. */
204/* For the ARM:
205 I think I have added all the code to make this work. Unfortunately,
206 early releases of the floating point emulation code on RISCiX used a
207 different format for extended precision numbers. On my RISCiX box there
208 is a bug somewhere which causes the machine to lock up when running enquire
209 with long doubles. There is the additional aspect that Norcroft C
210 treats long doubles as doubles and we ought to remain compatible.
211 Perhaps someone with an FPA coprocessor and not running RISCiX would like
212 to try this someday. */
213/* #define LONG_DOUBLE_TYPE_SIZE 96 */
214
215/* Disable XFmode patterns in md file */
216#define ENABLE_XF_PATTERNS 0
217
218/* Define if you don't want extended real, but do want to use the
219 software floating point emulator for REAL_ARITHMETIC and
220 decimal <-> binary conversion. */
221/* See comment above */
222#define REAL_ARITHMETIC
223
35d965d5
RS		 224/* Define this if most significant bit is lowest numbered
225 in instructions that operate on numbered bit-fields. */
226#define BITS_BIG_ENDIAN 0
227
9c872872 228/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 229 Most ARM processors are run in little endian mode, so that is the default.
230 If you want to have it run-time selectable, change the definition in a
231 cover file to be TARGET_BIG_ENDIAN. */
35d965d5
RS		 232#define BYTES_BIG_ENDIAN 0
233
234/* Define this if most significant word of a multiword number is the lowest
235 numbered. */
236#define WORDS_BIG_ENDIAN 0
237
7fc6c9f0
RK		 238/* Define this if most significant word of doubles is the lowest numbered */
239#define FLOAT_WORDS_BIG_ENDIAN 1
240
b4ac57ab 241/* Number of bits in an addressable storage unit */
35d965d5
RS		 242#define BITS_PER_UNIT 8
243
244#define BITS_PER_WORD 32
245
246#define UNITS_PER_WORD 4
247
248#define POINTER_SIZE 32
249
250#define PARM_BOUNDARY 32
251
252#define STACK_BOUNDARY 32
253
254#define FUNCTION_BOUNDARY 32
255
256#define EMPTY_FIELD_BOUNDARY 32
257
258#define BIGGEST_ALIGNMENT 32
259
ff9940b0
RE		 260/* Make strings word-aligned so strcpy from constants will be faster. */
261#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
262 (TREE_CODE (EXP) == STRING_CST \
263 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
264
b4ac57ab
RS		 265/* Every structures size must be a multiple of 32 bits. */
266#define STRUCTURE_SIZE_BOUNDARY 32
267
ff9940b0
RE		 268/* Non-zero if move instructions will actually fail to work
269 when given unaligned data. */
35d965d5
RS		 270#define STRICT_ALIGNMENT 1
271
ff9940b0
RE		 272#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
273
35d965d5
RS		 274/* Define number of bits in most basic integer type.
275 (If undefined, default is BITS_PER_WORD). */
276/* #define INT_TYPE_SIZE */
277\f
278/* Standard register usage. */
279
280/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
281 (S - saved over call).
282
283 r0 * argument word/integer result
284 r1-r3 argument word
285
286 r4-r8 S register variable
287 r9 S (rfp) register variable (real frame pointer)
288
289 r10 F S (sl) stack limit (not currently used)
290 r11 F S (fp) argument pointer
291 r12 (ip) temp workspace
292 r13 F S (sp) lower end of current stack frame
293 r14 (lr) link address/workspace
294 r15 F (pc) program counter
295
296 f0 floating point result
297 f1-f3 floating point scratch
298
299 f4-f7 S floating point variable
300
ff9940b0
RE		 301 cc This is NOT a real register, but is used internally
302 to represent things that use or set the condition
303 codes.
304 sfp This isn't either. It is used during rtl generation
305 since the offset between the frame pointer and the
306 auto's isn't known until after register allocation.
307 afp Nor this, we only need this because of non-local
308 goto. Without it fp appears to be used and the
309 elimination code won't get rid of sfp. It tracks
310 fp exactly at all times.
311
35d965d5
RS		 312 *: See CONDITIONAL_REGISTER_USAGE */
313
ff9940b0
RE		 314/* The stack backtrace structure is as follows:
315 fp points to here: | save code pointer | [fp]
316 | return link value | [fp, #-4]
317 | return sp value | [fp, #-8]
318 | return fp value | [fp, #-12]
319 [| saved r10 value |]
320 [| saved r9 value |]
321 [| saved r8 value |]
322 [| saved r7 value |]
323 [| saved r6 value |]
324 [| saved r5 value |]
325 [| saved r4 value |]
326 [| saved r3 value |]
327 [| saved r2 value |]
328 [| saved r1 value |]
329 [| saved r0 value |]
330 [| saved f7 value |] three words
331 [| saved f6 value |] three words
332 [| saved f5 value |] three words
333 [| saved f4 value |] three words
334 r0-r3 are not normally saved in a C function. */
335
336/* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
337#define FIRST_PSEUDO_REGISTER 27
35d965d5
RS		 338
339/* 1 for registers that have pervasive standard uses
340 and are not available for the register allocator. */
341#define FIXED_REGISTERS \
342{ \
343 0,0,0,0,0,0,0,0, \
344 0,0,1,1,0,1,0,1, \
ff9940b0
RE		 345 0,0,0,0,0,0,0,0, \
346 1,1,1 \
35d965d5
RS		 347}
348
349/* 1 for registers not available across function calls.
350 These must include the FIXED_REGISTERS and also any
351 registers that can be used without being saved.
352 The latter must include the registers where values are returned
353 and the register where structure-value addresses are passed.
ff9940b0
RE		 354 Aside from that, you can include as many other registers as you like.
355 The CC is not preserved over function calls on the ARM 6, so it is
356 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 357#define CALL_USED_REGISTERS \
358{ \
359 1,1,1,1,0,0,0,0, \
360 0,0,1,1,1,1,1,1, \
ff9940b0
RE		 361 1,1,1,1,0,0,0,0, \
362 1,1,1 \
35d965d5
RS		 363}
364
365/* If doing stupid life analysis, avoid a bug causing a return value r0 to be
366 trampled. This effectively reduces the number of available registers by 1.
367 XXX It is a hack, I know.
368 XXX Is this still needed? */
369#define CONDITIONAL_REGISTER_USAGE \
3ada8e17
DE		 370{ \
371 if (obey_regdecls) \
372 fixed_regs[0] = 1; \
373 if (TARGET_SOFT_FLOAT) \
374 { \
375 int regno; \
376 for (regno = 16; regno < 24; ++regno) \
377 fixed_regs[regno] = call_used_regs[regno] = 1; \
378 } \
35d965d5
RS		 379}
380
381/* Return number of consecutive hard regs needed starting at reg REGNO
382 to hold something of mode MODE.
383 This is ordinarily the length in words of a value of mode MODE
384 but can be less for certain modes in special long registers.
385
386 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
387 mode. */
ff9940b0
RE		 388#define HARD_REGNO_NREGS(REGNO, MODE) \
389 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
390 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
35d965d5
RS		 391 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
392
393/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
394 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
395 regs holding FP. */
ff9940b0
RE		 396#define HARD_REGNO_MODE_OK(REGNO, MODE) \
397 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
398 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
399 || REGNO == ARG_POINTER_REGNUM \
400 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
35d965d5
RS		 401
402/* Value is 1 if it is a good idea to tie two pseudo registers
403 when one has mode MODE1 and one has mode MODE2.
404 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
405 for any hard reg, then this must be 0 for correct output. */
406#define MODES_TIEABLE_P(MODE1, MODE2) \
3967692c 407 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
35d965d5
RS		 408
409/* Specify the registers used for certain standard purposes.
410 The values of these macros are register numbers. */
411
412/* Define this if the program counter is overloaded on a register. */
413#define PC_REGNUM 15
414
415/* Register to use for pushing function arguments. */
416#define STACK_POINTER_REGNUM 13
417
418/* Base register for access to local variables of the function. */
ff9940b0
RE		 419#define FRAME_POINTER_REGNUM 25
420
421/* Define this to be where the real frame pointer is if it is not possible to
422 work out the offset between the frame pointer and the automatic variables
423 until after register allocation has taken place. FRAME_POINTER_REGNUM
424 should point to a special register that we will make sure is eliminated. */
425#define HARD_FRAME_POINTER_REGNUM 11
35d965d5
RS		 426
427/* Value should be nonzero if functions must have frame pointers.
428 Zero means the frame pointer need not be set up (and parms may be accessed
ff9940b0
RE		 429 via the stack pointer) in functions that seem suitable.
430 If we have to have a frame pointer we might as well make use of it.
431 APCS says that the frame pointer does not need to be pushed in leaf
432 functions. */
688743e7
RE		 433#define FRAME_POINTER_REQUIRED \
434 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
35d965d5
RS		 435
436/* Base register for access to arguments of the function. */
ff9940b0 437#define ARG_POINTER_REGNUM 26
35d965d5
RS		 438
439/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
440 as an invisible last argument (possible since varargs don't exist in
441 Pascal), so the following is not true. */
442#define STATIC_CHAIN_REGNUM 8
443
444/* Register in which address to store a structure value
445 is passed to a function. */
446#define STRUCT_VALUE_REGNUM 0
447
ff9940b0
RE		 448/* Internal, so that we don't need to refer to a raw number */
449#define CC_REGNUM 24
450
35d965d5 451/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 452 since no saving is required (though calls clobber it) and it never contains
453 function parameters. It is quite good to use lr since other calls may
454 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
455 least likely to contain a function parameter; in addition results are
456 returned in r0.
457 */
35d965d5
RS		 458#define REG_ALLOC_ORDER \
459{ \
ff9940b0 460 3, 2, 1, 0, 12, 14, 4, 5, \
35d965d5 461 6, 7, 8, 10, 9, 11, 13, 15, \
ff9940b0
RE		 462 16, 17, 18, 19, 20, 21, 22, 23, \
463 24, 25 \
35d965d5
RS		 464}
465\f
466/* Register and constant classes. */
467
468/* Register classes: all ARM regs or all FPU regs---simple! */
469enum reg_class
470{
471 NO_REGS,
472 FPU_REGS,
473 GENERAL_REGS,
474 ALL_REGS,
475 LIM_REG_CLASSES
476};
477
478#define N_REG_CLASSES (int) LIM_REG_CLASSES
479
480/* Give names of register classes as strings for dump file. */
481#define REG_CLASS_NAMES \
482{ \
483 "NO_REGS", \
484 "FPU_REGS", \
485 "GENERAL_REGS", \
486 "ALL_REGS", \
487}
488
489/* Define which registers fit in which classes.
490 This is an initializer for a vector of HARD_REG_SET
491 of length N_REG_CLASSES. */
492#define REG_CLASS_CONTENTS \
493{ \
ff9940b0
RE		 494 0x0000000, /* NO_REGS */ \
495 0x0FF0000, /* FPU_REGS */ \
496 0x200FFFF, /* GENERAL_REGS */ \
497 0x2FFFFFF /* ALL_REGS */ \
35d965d5
RS		 498}
499
500/* The same information, inverted:
501 Return the class number of the smallest class containing
502 reg number REGNO. This could be a conditional expression
503 or could index an array. */
ff9940b0
RE		 504#define REGNO_REG_CLASS(REGNO) \
505 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
506 || REGNO == ARG_POINTER_REGNUM) \
507 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
508 ? NO_REGS : FPU_REGS)
35d965d5
RS		 509
510/* The class value for index registers, and the one for base regs. */
511#define INDEX_REG_CLASS GENERAL_REGS
512#define BASE_REG_CLASS GENERAL_REGS
513
514/* Get reg_class from a letter such as appears in the machine description.
515 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
516#define REG_CLASS_FROM_LETTER(C) \
517 ((C)=='f' ? FPU_REGS : NO_REGS)
518
519/* The letters I, J, K, L and M in a register constraint string
520 can be used to stand for particular ranges of immediate operands.
521 This macro defines what the ranges are.
522 C is the letter, and VALUE is a constant value.
523 Return 1 if VALUE is in the range specified by C.
b4ac57ab 524 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
ff9940b0 525 J: valid indexing constants.
aef1764c 526 K: ~value ok in rhs argument of data operand.
3967692c
RE		 527 L: -value ok in rhs argument of data operand.
528 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
aef1764c
RE		 529#define CONST_OK_FOR_LETTER_P(VALUE, C) \
530 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
531 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
532 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
3967692c
RE		 533 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
534 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
535 || (((VALUE) & ((VALUE) - 1)) == 0)) \
536 : 0)
ff9940b0
RE		 537
538/* For the ARM, `Q' means that this is a memory operand that is just
539 an offset from a register.
540 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
541 address. This means that the symbol is in the text segment and can be
542 accessed without using a load. */
543
544#define EXTRA_CONSTRAINT(OP, C) \
545 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
008cf58a
RE		 546 : (C) == 'R' ? (GET_CODE (OP) == MEM \
547 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
548 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
549 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0)
ff9940b0
RE		 550
551/* Constant letter 'G' for the FPU immediate constants.
552 'H' means the same constant negated. */
553#define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
554 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
555 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
35d965d5
RS		 556
557/* Given an rtx X being reloaded into a reg required to be
558 in class CLASS, return the class of reg to actually use.
559 In general this is just CLASS; but on some machines
560 in some cases it is preferable to use a more restrictive class. */
561#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
562
ff9940b0
RE		 563/* Return the register class of a scratch register needed to copy IN into
564 or out of a register in CLASS in MODE. If it can be done directly,
565 NO_REGS is returned. */
566#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
567 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
c383667d
DE		 568 && true_regnum (X) == -1 && TARGET_HARD_FLOAT) \
569 ? GENERAL_REGS \
7fc6c9f0 570 : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS)
ff9940b0 571
2ce9c1b9
RE		 572/* If we need to load shorts byte-at-a-time, then we need a scratch. */
573#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
574 (((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \
575 ? GENERAL_REGS : NO_REGS)
576
35d965d5
RS		 577/* Return the maximum number of consecutive registers
578 needed to represent mode MODE in a register of class CLASS.
579 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
580#define CLASS_MAX_NREGS(CLASS, MODE) \
581 ((CLASS) == FPU_REGS ? 1 \
582 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
583
ff9940b0 584/* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
35d965d5
RS		 585#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
586 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
587 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
ff9940b0 588 ? 20 : 2)
35d965d5
RS		 589\f
590/* Stack layout; function entry, exit and calling. */
591
592/* Define this if pushing a word on the stack
593 makes the stack pointer a smaller address. */
594#define STACK_GROWS_DOWNWARD 1
595
596/* Define this if the nominal address of the stack frame
597 is at the high-address end of the local variables;
598 that is, each additional local variable allocated
599 goes at a more negative offset in the frame. */
600#define FRAME_GROWS_DOWNWARD 1
601
602/* Offset within stack frame to start allocating local variables at.
603 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
604 first local allocated. Otherwise, it is the offset to the BEGINNING
605 of the first local allocated. */
606#define STARTING_FRAME_OFFSET 0
607
608/* If we generate an insn to push BYTES bytes,
609 this says how many the stack pointer really advances by. */
610#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
611
612/* Offset of first parameter from the argument pointer register value. */
613#define FIRST_PARM_OFFSET(FNDECL) 4
614
615/* Value is the number of byte of arguments automatically
616 popped when returning from a subroutine call.
8b109b37 617 FUNDECL is the declaration node of the function (as a tree),
35d965d5
RS		 618 FUNTYPE is the data type of the function (as a tree),
619 or for a library call it is an identifier node for the subroutine name.
620 SIZE is the number of bytes of arguments passed on the stack.
621
622 On the ARM, the caller does not pop any of its arguments that were passed
623 on the stack. */
8b109b37 624#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
35d965d5
RS		 625
626/* Define how to find the value returned by a function.
627 VALTYPE is the data type of the value (as a tree).
628 If the precise function being called is known, FUNC is its FUNCTION_DECL;
629 otherwise, FUNC is 0. */
630#define FUNCTION_VALUE(VALTYPE, FUNC) \
3ada8e17
DE		 631 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \
632 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
35d965d5
RS		 633 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
634
635/* Define how to find the value returned by a library function
636 assuming the value has mode MODE. */
637#define LIBCALL_VALUE(MODE) \
3ada8e17
DE		 638 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
639 ? gen_rtx (REG, MODE, 16) \
35d965d5
RS		 640 : gen_rtx (REG, MODE, 0))
641
642/* 1 if N is a possible register number for a function value.
643 On the ARM, only r0 and f0 can return results. */
644#define FUNCTION_VALUE_REGNO_P(REGNO) \
3ada8e17 645 ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT)
35d965d5
RS		 646
647/* Define where to put the arguments to a function.
648 Value is zero to push the argument on the stack,
649 or a hard register in which to store the argument.
650
651 MODE is the argument's machine mode.
652 TYPE is the data type of the argument (as a tree).
653 This is null for libcalls where that information may
654 not be available.
655 CUM is a variable of type CUMULATIVE_ARGS which gives info about
656 the preceding args and about the function being called.
657 NAMED is nonzero if this argument is a named parameter
658 (otherwise it is an extra parameter matching an ellipsis).
659
660 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
661 other arguments are passed on the stack. If (NAMED == 0) (which happens
662 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
663 passed in the stack (function_prologue will indeed make it pass in the
664 stack if necessary). */
665#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
666 ((NAMED) \
667 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
668 : 0)
669
670/* For an arg passed partly in registers and partly in memory,
671 this is the number of registers used.
672 For args passed entirely in registers or entirely in memory, zero. */
673#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
674 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
675 ? GET_MODE_SIZE (MODE) \
676 : int_size_in_bytes (TYPE)) \
677 ? 4 - (CUM) / 4 : 0)
678
679/* A C type for declaring a variable that is used as the first argument of
680 `FUNCTION_ARG' and other related values. For some target machines, the
681 type `int' suffices and can hold the number of bytes of argument so far.
682
683 On the ARM, this is the number of bytes of arguments scanned so far. */
684#define CUMULATIVE_ARGS int
685
686/* Initialize a variable CUM of type CUMULATIVE_ARGS
687 for a call to a function whose data type is FNTYPE.
688 For a library call, FNTYPE is 0.
689 On the ARM, the offset starts at 0. */
690#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
ff9940b0 691 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
35d965d5
RS		 692
693/* Update the data in CUM to advance over an argument
694 of mode MODE and data type TYPE.
695 (TYPE is null for libcalls where that information may not be available.) */
696#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
697 (CUM) += ((MODE) != BLKmode \
698 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
699 : (int_size_in_bytes (TYPE) + 3) & ~3) \
700
701/* 1 if N is a possible register number for function argument passing.
702 On the ARM, r0-r3 are used to pass args. */
703#define FUNCTION_ARG_REGNO_P(REGNO) \
704 ((REGNO) >= 0 && (REGNO) <= 3)
705
706/* Perform any actions needed for a function that is receiving a variable
707 number of arguments. CUM is as above. MODE and TYPE are the mode and type
708 of the current parameter. PRETEND_SIZE is a variable that should be set to
709 the amount of stack that must be pushed by the prolog to pretend that our
710 caller pushed it.
711
712 Normally, this macro will push all remaining incoming registers on the
713 stack and set PRETEND_SIZE to the length of the registers pushed.
714
715 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
716 named arg and all anonymous args onto the stack.
717 XXX I know the prologue shouldn't be pushing registers, but it is faster
718 that way. */
719#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
720{ \
721 extern int current_function_anonymous_args; \
722 current_function_anonymous_args = 1; \
723 if ((CUM) < 16) \
724 (PRETEND_SIZE) = 16 - (CUM); \
725}
726
727/* Generate assembly output for the start of a function. */
728#define FUNCTION_PROLOGUE(STREAM, SIZE) \
008cf58a 729 output_func_prologue ((STREAM), (SIZE))
35d965d5
RS		 730
731/* Call the function profiler with a given profile label. The Acorn compiler
732 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
733 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
734 to mind about this! */
4eda77ec
RE		 735#define FUNCTION_PROFILER(STREAM,LABELNO) \
736{ \
c383667d 737 fprintf(STREAM, "\tmov\t%sip, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX); \
4eda77ec
RE		 738 fprintf(STREAM, "\tbl\tmcount\n"); \
739 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
35d965d5
RS		 740}
741
742/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
743 the stack pointer does not matter. The value is tested only in
744 functions that have frame pointers.
745 No definition is equivalent to always zero.
746
747 On the ARM, the function epilogue recovers the stack pointer from the
748 frame. */
749#define EXIT_IGNORE_STACK 1
750
751/* Generate the assembly code for function exit. */
752#define FUNCTION_EPILOGUE(STREAM, SIZE) \
008cf58a 753 output_func_epilogue ((STREAM), (SIZE))
35d965d5
RS		 754
755/* Determine if the epilogue should be output as RTL.
756 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
ff9940b0
RE		 757#define USE_RETURN_INSN use_return_insn ()
758
759/* Definitions for register eliminations.
760
761 This is an array of structures. Each structure initializes one pair
762 of eliminable registers. The "from" register number is given first,
763 followed by "to". Eliminations of the same "from" register are listed
764 in order of preference.
765
766 We have two registers that can be eliminated on the ARM. First, the
767 arg pointer register can often be eliminated in favor of the stack
768 pointer register. Secondly, the pseudo frame pointer register can always
769 be eliminated; it is replaced with either the stack or the real frame
770 pointer. */
771
772#define ELIMINABLE_REGS \
773{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
774 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
775 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
776 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
777
778/* Given FROM and TO register numbers, say whether this elimination is allowed.
779 Frame pointer elimination is automatically handled.
780
781 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
782 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
783 pointer, we must eliminate FRAME_POINTER_REGNUM into
784 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
785#define CAN_ELIMINATE(FROM, TO) \
786 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
787
788/* Define the offset between two registers, one to be eliminated, and the other
789 its replacement, at the start of a routine. */
790#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
791{ \
3967692c 792 int volatile_func = arm_volatile_func (); \
ff9940b0
RE		 793 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
794 (OFFSET) = 0; \
795 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
796 (OFFSET) = (get_frame_size () + 3 & ~3); \
797 else \
798 { \
799 int regno; \
800 int offset = 12; \
008cf58a 801 int saved_hard_reg = 0; \
ff9940b0 802 \
3967692c
RE		 803 if (! volatile_func) \
804 { \
805 for (regno = 0; regno <= 10; regno++) \
806 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
807 saved_hard_reg = 1, offset += 4; \
808 for (regno = 16; regno <=23; regno++) \
809 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
810 offset += 12; \
811 } \
ff9940b0
RE		 812 if ((FROM) == FRAME_POINTER_REGNUM) \
813 (OFFSET) = -offset; \
814 else \
815 { \
bd4d60ce 816 if (! frame_pointer_needed) \
ff9940b0 817 offset -= 16; \
3967692c 818 if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \
ff9940b0
RE		 819 offset += 4; \
820 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
821 } \
822 } \
823}
35d965d5 824
35d965d5
RS		 825/* Output assembler code for a block containing the constant parts
826 of a trampoline, leaving space for the variable parts.
827
828 On the ARM, (if r8 is the static chain regnum, and remembering that
829 referencing pc adds an offset of 8) the trampoline looks like:
830 ldr r8, [pc, #0]
831 ldr pc, [pc]
832 .word static chain value
833 .word function's address */
4eda77ec
RE		 834#define TRAMPOLINE_TEMPLATE(FILE) \
835{ \
c383667d
DE		 836 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", \
837 REGISTER_PREFIX, REGISTER_PREFIX); \
838 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", \
839 REGISTER_PREFIX, REGISTER_PREFIX); \
4eda77ec
RE		 840 fprintf ((FILE), "\t.word\t0\n"); \
841 fprintf ((FILE), "\t.word\t0\n"); \
35d965d5
RS		 842}
843
844/* Length in units of the trampoline for entering a nested function. */
845#define TRAMPOLINE_SIZE 16
846
847/* Alignment required for a trampoline in units. */
848#define TRAMPOLINE_ALIGN 4
849
850/* Emit RTL insns to initialize the variable parts of a trampoline.
851 FNADDR is an RTX for the address of the function's pure code.
852 CXT is an RTX for the static chain value for the function. */
853#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
854{ \
855 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
856 (CXT)); \
857 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
858 (FNADDR)); \
859}
860
35d965d5
RS		 861\f
862/* Addressing modes, and classification of registers for them. */
863
864#define HAVE_POST_INCREMENT 1
865#define HAVE_PRE_INCREMENT 1
866#define HAVE_POST_DECREMENT 1
867#define HAVE_PRE_DECREMENT 1
868
869/* Macros to check register numbers against specific register classes. */
870
871/* These assume that REGNO is a hard or pseudo reg number.
872 They give nonzero only if REGNO is a hard reg of the suitable class
873 or a pseudo reg currently allocated to a suitable hard reg.
874 Since they use reg_renumber, they are safe only once reg_renumber
875 has been allocated, which happens in local-alloc.c.
876
877 On the ARM, don't allow the pc to be used. */
ff9940b0
RE		 878#define REGNO_OK_FOR_BASE_P(REGNO) \
879 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
880 || (REGNO) == ARG_POINTER_REGNUM \
881 || (unsigned) reg_renumber[(REGNO)] < 15 \
882 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
883 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
884#define REGNO_OK_FOR_INDEX_P(REGNO) \
35d965d5
RS		 885 REGNO_OK_FOR_BASE_P(REGNO)
886
887/* Maximum number of registers that can appear in a valid memory address.
ff9940b0
RE		 888 Shifts in addresses can't be by a register. */
889
890#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 891
892/* Recognize any constant value that is a valid address. */
893/* XXX We can address any constant, eventually... */
894#if 0
895#define CONSTANT_ADDRESS_P(X) \
896 ( GET_CODE(X) == LABEL_REF \
897 || GET_CODE(X) == SYMBOL_REF \
898 || GET_CODE(X) == CONST_INT \
899 || GET_CODE(X) == CONST )
900#endif
901
008cf58a
RE		 902#define CONSTANT_ADDRESS_P(X) \
903 (GET_CODE (X) == SYMBOL_REF \
904 && (CONSTANT_POOL_ADDRESS_P (X) \
905 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5
RS		 906
907/* Nonzero if the constant value X is a legitimate general operand.
908 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
909
910 On the ARM, allow any integer (invalid ones are removed later by insn
911 patterns), nice doubles and symbol_refs which refer to the function's
912 constant pool XXX. */
913#define LEGITIMATE_CONSTANT_P(X) \
914 (GET_CODE (X) == CONST_INT \
915 || (GET_CODE (X) == CONST_DOUBLE \
ff9940b0
RE		 916 && (const_double_rtx_ok_for_fpu (X) \
917 || neg_const_double_rtx_ok_for_fpu (X))) \
918 || CONSTANT_ADDRESS_P (X))
919
920/* Symbols in the text segment can be accessed without indirecting via the
921 constant pool; it may take an extra binary operation, but this is still
008cf58a
RE		 922 faster than indirecting via memory. Don't do this when not optimizing,
923 since we won't be calculating al of the offsets necessary to do this
924 simplification. */
ff9940b0
RE		 925
926#define ENCODE_SECTION_INFO(decl) \
927{ \
008cf58a 928 if (optimize > 0 && TREE_CONSTANT (decl) \
ff9940b0 929 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
228b6a3f
RS		 930 { \
931 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
932 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
933 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
934 } \
ff9940b0 935}
35d965d5
RS		 936
937/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
938 and check its validity for a certain class.
939 We have two alternate definitions for each of them.
940 The usual definition accepts all pseudo regs; the other rejects
941 them unless they have been allocated suitable hard regs.
942 The symbol REG_OK_STRICT causes the latter definition to be used. */
943#ifndef REG_OK_STRICT
ff9940b0 944
35d965d5
RS		 945/* Nonzero if X is a hard reg that can be used as a base reg
946 or if it is a pseudo reg. */
ff9940b0
RE		 947#define REG_OK_FOR_BASE_P(X) \
948 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
949 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
950
35d965d5
RS		 951/* Nonzero if X is a hard reg that can be used as an index
952 or if it is a pseudo reg. */
953#define REG_OK_FOR_INDEX_P(X) \
954 REG_OK_FOR_BASE_P(X)
ff9940b0
RE		 955
956#define REG_OK_FOR_PRE_POST_P(X) \
957 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
958 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
959
35d965d5 960#else
ff9940b0 961
35d965d5
RS		 962/* Nonzero if X is a hard reg that can be used as a base reg. */
963#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 964
35d965d5
RS		 965/* Nonzero if X is a hard reg that can be used as an index. */
966#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
ff9940b0
RE		 967
968#define REG_OK_FOR_PRE_POST_P(X) \
969 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
970 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
971 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
972 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
973
35d965d5
RS		 974#endif
975\f
976/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
977 that is a valid memory address for an instruction.
978 The MODE argument is the machine mode for the MEM expression
979 that wants to use this address.
980
981 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
982#define BASE_REGISTER_RTX_P(X) \
983 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
984
985#define INDEX_REGISTER_RTX_P(X) \
986 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
987
988/* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
989 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
990 only be small constants. */
ff9940b0 991#define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
4d01c30f
RS		 992do \
993{ \
008cf58a
RE		 994 HOST_WIDE_INT range; \
995 enum rtx_code code = GET_CODE (INDEX); \
4d01c30f
RS		 996 \
997 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
ff9940b0
RE		 998 { \
999 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1000 && INTVAL (INDEX) > -1024 \
1001 && (INTVAL (INDEX) & 3) == 0) \
1002 goto LABEL; \
1003 } \
4d01c30f
RS		 1004 else \
1005 { \
ff9940b0 1006 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
4d01c30f 1007 goto LABEL; \
ff9940b0 1008 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
4d01c30f
RS		 1009 { \
1010 rtx xiop0 = XEXP (INDEX, 0); \
1011 rtx xiop1 = XEXP (INDEX, 1); \
1012 if (INDEX_REGISTER_RTX_P (xiop0) \
1013 && power_of_two_operand (xiop1, SImode)) \
1014 goto LABEL; \
1015 if (INDEX_REGISTER_RTX_P (xiop1) \
1016 && power_of_two_operand (xiop0, SImode)) \
1017 goto LABEL; \
1018 } \
ff9940b0 1019 if (GET_MODE_SIZE (MODE) <= 4 \
996a5f59 1020 && (code == LSHIFTRT || code == ASHIFTRT \
ff9940b0
RE		 1021 || code == ASHIFT || code == ROTATERT)) \
1022 { \
1023 rtx op = XEXP (INDEX, 1); \
1024 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1025 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1026 && INTVAL (op) <= 31) \
1027 goto LABEL; \
1028 } \
1029 range = (MODE) == HImode ? 4095 : 4096; \
1030 if (code == CONST_INT && INTVAL (INDEX) < range \
1031 && INTVAL (INDEX) > -range) \
1032 goto LABEL; \
4d01c30f 1033 } \
35d965d5
RS		 1034} while (0)
1035
1036/* Jump to LABEL if X is a valid address RTX. This must also take
1037 REG_OK_STRICT into account when deciding about valid registers, but it uses
1038 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1039 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
ff9940b0
RE		 1040 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1041 refs must be forced though a static cell to ensure addressability. */
35d965d5
RS		 1042#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1043{ \
1044 if (BASE_REGISTER_RTX_P (X)) \
1045 goto LABEL; \
1046 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1047 && GET_CODE (XEXP (X, 0)) == REG \
1048 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1049 goto LABEL; \
1050 else if ((MODE) == TImode) \
1051 ; \
1052 else if (GET_CODE (X) == PLUS) \
1053 { \
1054 rtx xop0 = XEXP(X,0); \
1055 rtx xop1 = XEXP(X,1); \
1056 \
1057 if (BASE_REGISTER_RTX_P (xop0)) \
1058 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1059 else if (BASE_REGISTER_RTX_P (xop1)) \
1060 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1061 } \
1062 else if (GET_CODE (X) == MINUS) \
1063 { \
1064 rtx xop0 = XEXP (X,0); \
1065 rtx xop1 = XEXP (X,1); \
1066 \
1067 if (BASE_REGISTER_RTX_P (xop0)) \
1068 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1069 } \
1070 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1071 && GET_CODE (X) == SYMBOL_REF \
1072 && CONSTANT_POOL_ADDRESS_P (X)) \
1073 goto LABEL; \
1074 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1075 && GET_CODE (XEXP (X, 0)) == REG \
1076 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1077 goto LABEL; \
1078}
1079\f
1080/* Try machine-dependent ways of modifying an illegitimate address
1081 to be legitimate. If we find one, return the new, valid address.
1082 This macro is used in only one place: `memory_address' in explow.c.
1083
1084 OLDX is the address as it was before break_out_memory_refs was called.
1085 In some cases it is useful to look at this to decide what needs to be done.
1086
1087 MODE and WIN are passed so that this macro can use
1088 GO_IF_LEGITIMATE_ADDRESS.
1089
1090 It is always safe for this macro to do nothing. It exists to recognize
1091 opportunities to optimize the output.
1092
1093 On the ARM, try to convert [REG, #BIGCONST]
1094 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1095 where VALIDCONST == 0 in case of TImode. */
3967692c
RE		 1096#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1097{ \
1098 if (GET_CODE (X) == PLUS) \
1099 { \
1100 rtx xop0 = XEXP (X, 0); \
1101 rtx xop1 = XEXP (X, 1); \
1102 \
1103 if (CONSTANT_P (xop0) && ! LEGITIMATE_CONSTANT_P (xop0)) \
1104 xop0 = force_reg (SImode, xop0); \
1105 if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \
1106 xop1 = force_reg (SImode, xop1); \
1107 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1108 { \
1109 HOST_WIDE_INT n, low_n; \
1110 rtx base_reg, val; \
1111 n = INTVAL (xop1); \
1112 \
1113 if (MODE == DImode) \
1114 { \
1115 low_n = n & 0x0f; \
1116 n &= ~0x0f; \
1117 if (low_n > 4) \
1118 { \
1119 n += 16; \
1120 low_n -= 16; \
1121 } \
1122 } \
1123 else \
1124 { \
1125 low_n = ((MODE) == TImode ? 0 \
1126 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1127 n -= low_n; \
1128 } \
1129 base_reg = gen_reg_rtx (SImode); \
1130 val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1131 GEN_INT (n)), NULL_RTX); \
1132 emit_move_insn (base_reg, val); \
1133 (X) = (low_n == 0 ? base_reg \
1134 : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \
1135 } \
1136 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1137 (X) = gen_rtx (PLUS, SImode, xop0, xop1); \
1138 } \
1139 else if (GET_CODE (X) == MINUS) \
1140 { \
1141 rtx xop0 = XEXP (X, 0); \
1142 rtx xop1 = XEXP (X, 1); \
1143 \
1144 if (CONSTANT_P (xop0)) \
1145 xop0 = force_reg (SImode, xop0); \
1146 if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \
1147 xop1 = force_reg (SImode, xop1); \
1148 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1149 (X) = gen_rtx (MINUS, SImode, xop0, xop1); \
1150 } \
1151 if (memory_address_p (MODE, X)) \
1152 goto WIN; \
35d965d5
RS		 1153}
1154
3967692c 1155
35d965d5
RS		 1156/* Go to LABEL if ADDR (a legitimate address expression)
1157 has an effect that depends on the machine mode it is used for. */
1158#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1159{ \
1160 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1161 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1162 goto LABEL; \
1163}
1164\f
1165/* Specify the machine mode that this machine uses
1166 for the index in the tablejump instruction. */
1167#define CASE_VECTOR_MODE SImode
1168
1169/* Define this if the tablejump instruction expects the table
1170 to contain offsets from the address of the table.
1171 Do not define this if the table should contain absolute addresses. */
1172/* #define CASE_VECTOR_PC_RELATIVE */
1173
1174/* Specify the tree operation to be used to convert reals to integers. */
1175#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1176
1177/* This is the kind of divide that is easiest to do in the general case. */
1178#define EASY_DIV_EXPR TRUNC_DIV_EXPR
1179
ff9940b0
RE		 1180/* signed 'char' is most compatible, but RISC OS wants it unsigned.
1181 unsigned is probably best, but may break some code. */
1182#ifndef DEFAULT_SIGNED_CHAR
3967692c 1183#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 1184#endif
1185
1186/* Don't cse the address of the function being compiled. */
1187#define NO_RECURSIVE_FUNCTION_CSE 1
1188
1189/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 1190 in one reasonably fast instruction. */
1191#define MOVE_MAX 4
35d965d5 1192
ff9940b0
RE		 1193/* Define if operations between registers always perform the operation
1194 on the full register even if a narrower mode is specified. */
1195#define WORD_REGISTER_OPERATIONS
1196
1197/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1198 will either zero-extend or sign-extend. The value of this macro should
1199 be the code that says which one of the two operations is implicitly
1200 done, NIL if none. */
9c872872
RE		 1201#define LOAD_EXTEND_OP(MODE) \
1202 ((MODE) == QImode ? ZERO_EXTEND \
1203 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
ff9940b0 1204
35d965d5
RS		 1205/* Define this if zero-extension is slow (more than one real instruction).
1206 On the ARM, it is more than one instruction only if not fetching from
1207 memory. */
1208/* #define SLOW_ZERO_EXTEND */
1209
1210/* Nonzero if access to memory by bytes is slow and undesirable. */
1211#define SLOW_BYTE_ACCESS 0
1212
1213/* Immediate shift counts are truncated by the output routines (or was it
1214 the assembler?). Shift counts in a register are truncated by ARM. Note
1215 that the native compiler puts too large (> 32) immediate shift counts
1216 into a register and shifts by the register, letting the ARM decide what
1217 to do instead of doing that itself. */
ff9940b0
RE		 1218/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1219 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1220 On the arm, Y in a register is used modulo 256 for the shift. Only for
1221 rotates is modulo 32 used. */
1222/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5
RS		 1223
1224/* XX This is not true, is it? */
1225/* All integers have the same format so truncation is easy. */
1226#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1227
1228/* Calling from registers is a massive pain. */
1229#define NO_FUNCTION_CSE 1
1230
1231/* Chars and shorts should be passed as ints. */
1232#define PROMOTE_PROTOTYPES 1
1233
35d965d5
RS		 1234/* The machine modes of pointers and functions */
1235#define Pmode SImode
1236#define FUNCTION_MODE Pmode
1237
1238/* The structure type of the machine dependent info field of insns
1239 No uses for this yet. */
1240/* #define INSN_MACHINE_INFO struct machine_info */
1241
1242/* The relative costs of various types of constants. Note that cse.c defines
1243 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
ff9940b0
RE		 1244#define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1245 case CONST_INT: \
1246 if (const_ok_for_arm (INTVAL (RTX))) \
1247 return (OUTER_CODE) == SET ? 2 : -1; \
1248 else if (OUTER_CODE == AND \
1249 && const_ok_for_arm (~INTVAL (RTX))) \
1250 return -1; \
1251 else if ((OUTER_CODE == COMPARE \
1252 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1253 && const_ok_for_arm (-INTVAL (RTX))) \
1254 return -1; \
1255 else \
1256 return 5; \
1257 case CONST: \
1258 case LABEL_REF: \
1259 case SYMBOL_REF: \
1260 return 6; \
1261 case CONST_DOUBLE: \
1262 if (const_double_rtx_ok_for_fpu (RTX)) \
1263 return (OUTER_CODE) == SET ? 2 : -1; \
1264 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1265 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1266 return -1; \
1267 return(7);
1268
3967692c
RE		 1269#define ARM_FRAME_RTX(X) \
1270 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1271 || (X) == arg_pointer_rtx)
1272
ff9940b0 1273#define RTX_COSTS(X,CODE,OUTER_CODE) \
3967692c
RE		 1274 default: \
1275 return arm_rtx_costs (X, CODE, OUTER_CODE);
ff9940b0
RE		 1276
1277/* Moves to and from memory are quite expensive */
1278#define MEMORY_MOVE_COST(MODE) 10
1279
3967692c 1280/* All address computations that can be done are free, but rtx cost returns
ddd5a7c1 1281 the same for practically all of them. So we weight the different types
3967692c
RE		 1282 of address here in the order (most pref first):
1283 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1284#define ADDRESS_COST(X) \
1285 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1286 || GET_CODE (X) == SYMBOL_REF) \
1287 ? 0 \
1288 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1289 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1290 ? 10 \
1291 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1292 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1293 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1294 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1295 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1296 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1297 ? 1 : 0)) \
1298 : 4)))))
1299
1300
ff9940b0
RE		 1301
1302/* Try to generate sequences that don't involve branches, we can then use
1303 conditional instructions */
1304#define BRANCH_COST 4
35d965d5 1305\f
ff9940b0
RE		 1306/* Condition code information. */
1307/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1308 return the mode to be used for the comparison.
ddd5a7c1 1309 CCFPEmode should be used with floating inequalities,
ff9940b0 1310 CCFPmode should be used with floating equalities.
ddd5a7c1 1311 CC_NOOVmode should be used with SImode integer equalities.
ff9940b0
RE		 1312 CCmode should be used otherwise. */
1313
1314#define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1315
1316#define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1317
1318#define SELECT_CC_MODE(OP,X,Y) \
1319 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1320 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1321 : ((GET_MODE (X) == SImode) \
1322 && ((OP) == EQ || (OP) == NE) \
1323 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1324 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1325 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1326 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
996a5f59 1327 || GET_CODE (X) == LSHIFTRT \
ff9940b0
RE		 1328 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1329 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1330 ? CC_NOOVmode \
1331 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1332
008cf58a
RE		 1333#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1334
ff9940b0
RE		 1335#define STORE_FLAG_VALUE 1
1336
1337/* Define the information needed to generate branch insns. This is
1338 stored from the compare operation. Note that we can't use "rtx" here
1339 since it hasn't been defined! */
1340
1341extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1342extern int arm_compare_fp;
1343
1344/* Define the codes that are matched by predicates in arm.c */
1345#define PREDICATE_CODES \
1346 {"s_register_operand", {SUBREG, REG}}, \
1347 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1348 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1349 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1350 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1351 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1352 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1353 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
3967692c 1354 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
ff9940b0 1355 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
c383667d 1356 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
ff9940b0
RE		 1357 {"load_multiple_operation", {PARALLEL}}, \
1358 {"store_multiple_operation", {PARALLEL}}, \
1359 {"equality_operator", {EQ, NE}}, \
1360 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1361 {"const_shift_operand", {CONST_INT}}, \
1362 {"index_operand", {SUBREG, REG, CONST_INT}}, \
3967692c
RE		 1363 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1364 {"multi_register_push", {PARALLEL}}, \
31e6408a
RE		 1365 {"cc_register", {REG}}, \
1366 {"reversible_cc_register", {REG}},
ff9940b0 1367
35d965d5
RS		 1368\f
1369/* Assembler output control */
1370
ff9940b0
RE		 1371#ifndef ARM_OS_NAME
1372#define ARM_OS_NAME "(generic)"
1373#endif
1374
35d965d5 1375/* The text to go at the start of the assembler file */
4eda77ec
RE		 1376#define ASM_FILE_START(STREAM) \
1377{ \
1378 extern char *version_string; \
c383667d
DE		 1379 fprintf (STREAM,"%s Generated by gcc %s for ARM/%s\n", \
1380 ASM_COMMENT_START, version_string, ARM_OS_NAME); \
1381 fprintf (STREAM,"%srfp\t.req\t%sr9\n", REGISTER_PREFIX, REGISTER_PREFIX); \
1382 fprintf (STREAM,"%ssl\t.req\t%sr10\n", REGISTER_PREFIX, REGISTER_PREFIX); \
1383 fprintf (STREAM,"%sfp\t.req\t%sr11\n", REGISTER_PREFIX, REGISTER_PREFIX); \
1384 fprintf (STREAM,"%sip\t.req\t%sr12\n", REGISTER_PREFIX, REGISTER_PREFIX); \
1385 fprintf (STREAM,"%ssp\t.req\t%sr13\n", REGISTER_PREFIX, REGISTER_PREFIX); \
1386 fprintf (STREAM,"%slr\t.req\t%sr14\n", REGISTER_PREFIX, REGISTER_PREFIX); \
1387 fprintf (STREAM,"%spc\t.req\t%sr15\n", REGISTER_PREFIX, REGISTER_PREFIX); \
35d965d5
RS		 1388}
1389
1390#define ASM_APP_ON ""
1391#define ASM_APP_OFF ""
1392
1393/* Switch to the text or data segment. */
8cf6b9ca
RS		 1394#define TEXT_SECTION_ASM_OP ".text"
1395#define DATA_SECTION_ASM_OP ".data"
35d965d5 1396
c383667d
DE		 1397#define REGISTER_PREFIX ""
1398#define USER_LABEL_PREFIX "_"
1399#define LOCAL_LABEL_PREFIX ""
1400
4eda77ec
RE		 1401/* The assembler's names for the registers. */
1402#ifndef REGISTER_NAMES
35d965d5
RS		 1403#define REGISTER_NAMES \
1404{ \
1405 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
4eda77ec 1406 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
ff9940b0
RE		 1407 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1408 "cc", "sfp", "afp" \
35d965d5 1409}
4eda77ec
RE		 1410#endif
1411
1412#ifndef ADDITIONAL_REGISTER_NAMES
1413#define ADDITIONAL_REGISTER_NAMES \
1414{ \
1415 {"a1", 0}, \
1416 {"a2", 1}, \
1417 {"a3", 2}, \
1418 {"a4", 3}, \
1419 {"v1", 4}, \
1420 {"v2", 5}, \
1421 {"v3", 6}, \
1422 {"v4", 7}, \
1423 {"v5", 8}, \
1424 {"v6", 9}, \
1425 {"rfp", 9}, /* Gcc used to call it this */ \
1426 {"sb", 9}, \
1427 {"v7", 10}, \
1428 {"r10", 10}, \
1429 {"r11", 11}, /* fp */ \
1430 {"r12", 12}, /* ip */ \
1431 {"r13", 13}, /* sp */ \
1432 {"r14", 14}, /* lr */ \
1433 {"r15", 15} /* pc */ \
1434}
1435#endif
35d965d5 1436
ff9940b0
RE		 1437/* Arm Assembler barfs on dollars */
1438#define DOLLARS_IN_IDENTIFIERS 0
1439
1440#define NO_DOLLAR_IN_LABEL
1441
35d965d5
RS		 1442/* DBX register number for a given compiler register number */
1443#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1444
ff9940b0
RE		 1445/* Generate DBX debugging information. riscix.h will undefine this because
1446 the native assembler does not support stabs. */
35d965d5
RS		 1447#define DBX_DEBUGGING_INFO 1
1448
1449/* Acorn dbx moans about continuation chars, so don't use any. */
3967692c 1450#ifndef DBX_CONTIN_LENGTH
35d965d5 1451#define DBX_CONTIN_LENGTH 0
3967692c 1452#endif
35d965d5 1453
ff9940b0
RE		 1454/* Output a source filename for the debugger. RISCiX dbx insists that the
1455 ``desc'' field is set to compiler version number >= 315 (sic). */
1456#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1457do { \
1458 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1459 &ltext_label_name[1]); \
1460 text_section (); \
1461 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1462} while (0)
1463
35d965d5
RS		 1464/* Output a label definition. */
1465#define ASM_OUTPUT_LABEL(STREAM,NAME) \
1466 arm_asm_output_label ((STREAM), (NAME))
1467
1468/* Output a function label definition. */
1469#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1470 ASM_OUTPUT_LABEL(STREAM, NAME)
1471
1472/* Output a globalising directive for a label. */
1473#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1474 (fprintf (STREAM, "\t.global\t"), \
1475 assemble_name (STREAM, NAME), \
1476 fputc ('\n',STREAM)) \
1477
1478/* Output a reference to a label. */
1479#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
c383667d 1480 fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, NAME)
35d965d5
RS		 1481
1482/* Make an internal label into a string. */
1483#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1484 sprintf (STRING, "*%s%d", PREFIX, NUM)
1485
1486/* Output an internal label definition. */
1487#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1488 do \
1489 { \
1490 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1491 extern int arm_target_label, arm_ccfsm_state; \
26563586 1492 extern rtx arm_target_insn; \
35d965d5 1493 \
ff9940b0
RE		 1494 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1495 && !strcmp (PREFIX, "L")) \
1496 { \
1497 arm_ccfsm_state = 0; \
26563586 1498 arm_target_insn = NULL; \
ff9940b0
RE		 1499 } \
1500 strcpy (s, "*"); \
1501 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1502 arm_asm_output_label (STREAM, s); \
35d965d5
RS		 1503 } while (0)
1504
1505/* Nothing special is done about jump tables */
1506/* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1507/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1508
1509/* Construct a private name. */
1510#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1511 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1512 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1513
1514/* Output a push or a pop instruction (only used when profiling). */
c383667d
DE		 1515#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1516 fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \
1517 REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO])
35d965d5 1518
c383667d
DE		 1519#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1520 fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \
1521 REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO])
35d965d5
RS		 1522
1523/* Output a relative address. Not needed since jump tables are absolute
1524 but we must define it anyway. */
1525#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1526 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1527
1528/* Output an element of a dispatch table. */
1529#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
008cf58a 1530 fprintf (STREAM, "\t.word\tL%d\n", VALUE)
35d965d5 1531
7fc6c9f0
RK		 1532/* Output various types of constants. For real numbers we output hex, with
1533 a comment containing the "human" value, this allows us to pass NaN's which
1534 the riscix assembler doesn't understand (it also makes cross-assembling
1535 less likely to fail). */
1536
ff9940b0 1537#define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
7fc6c9f0
RK		 1538do { char dstr[30]; \
1539 long l[3]; \
ff9940b0
RE		 1540 arm_increase_location (12); \
1541 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
7fc6c9f0 1542 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
ff9940b0 1543 if (sizeof (int) == sizeof (long)) \
c383667d
DE		 1544 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t%s long double %s\n", \
1545 l[2], l[1], l[0], ASM_COMMENT_START, dstr); \
ff9940b0 1546 else \
c383667d
DE		 1547 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%s long double %s\n",\
1548 l[0], l[1], l[2], ASM_COMMENT_START, dstr); \
ff9940b0
RE		 1549 } while (0)
1550
1551
7fc6c9f0
RK		 1552#define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1553do { char dstr[30]; \
1554 long l[2]; \
1555 arm_increase_location (8); \
1556 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1557 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
1558 if (sizeof (int) == sizeof (long)) \
c383667d
DE		 1559 fprintf (STREAM, "\t.long 0x%x, 0x%x\t%s double %s\n", l[0], \
1560 l[1], ASM_COMMENT_START, dstr); \
7fc6c9f0 1561 else \
c383667d
DE		 1562 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%s double %s\n", l[0], \
1563 l[1], ASM_COMMENT_START, dstr); \
ff9940b0
RE		 1564 } while (0)
1565
7fc6c9f0
RK		 1566#define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1567do { char dstr[30]; \
1568 long l; \
1569 arm_increase_location (4); \
1570 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1571 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
1572 if (sizeof (int) == sizeof (long)) \
c383667d
DE		 1573 fprintf (STREAM, "\t.word 0x%x\t%s float %s\n", l, \
1574 ASM_COMMENT_START, dstr); \
7fc6c9f0 1575 else \
c383667d
DE		 1576 fprintf (STREAM, "\t.word 0x%lx\t%s float %s\n", l, \
1577 ASM_COMMENT_START, dstr); \
ff9940b0 1578 } while (0);
35d965d5 1579
7fc6c9f0
RK		 1580#define ASM_OUTPUT_INT(STREAM, EXP) \
1581 (fprintf (STREAM, "\t.word\t"), \
1582 output_addr_const (STREAM, (EXP)), \
1583 arm_increase_location (4), \
35d965d5
RS		 1584 fputc ('\n', STREAM))
1585
1586#define ASM_OUTPUT_SHORT(STREAM, EXP) \
1587 (fprintf (STREAM, "\t.short\t"), \
1588 output_addr_const (STREAM, (EXP)), \
1589 arm_increase_location (2), \
1590 fputc ('\n', STREAM))
1591
1592#define ASM_OUTPUT_CHAR(STREAM, EXP) \
1593 (fprintf (STREAM, "\t.byte\t"), \
1594 output_addr_const (STREAM, (EXP)), \
1595 arm_increase_location (1), \
1596 fputc ('\n', STREAM))
1597
1598#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1599 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1600 arm_increase_location (1))
1601
1602#define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
f70bf59e 1603 output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN))
35d965d5
RS		 1604
1605/* Output a gap. In fact we fill it with nulls. */
1606#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1607 (arm_increase_location (NBYTES), \
1608 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1609
1610/* Align output to a power of two. Horrible /bin/as. */
1611#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1612 do \
1613 { \
1614 register int amount = 1 << (POWER); \
1615 extern int arm_text_location; \
1616 \
1617 if (amount == 2) \
1618 fprintf (STREAM, "\t.even\n"); \
1619 else \
1620 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1621 \
1622 if (in_text_section ()) \
1623 arm_text_location = ((arm_text_location + amount - 1) \
1624 & ~(amount - 1)); \
1625 } while (0)
1626
1627/* Output a common block */
4eda77ec
RE		 1628#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1629 (fprintf (STREAM, "\t.comm\t"), \
1630 assemble_name ((STREAM), (NAME)), \
c383667d 1631 fprintf(STREAM, ", %d\t%s %d\n", ROUNDED, ASM_COMMENT_START, SIZE))
35d965d5
RS		 1632
1633/* Output a local common block. /bin/as can't do this, so hack a `.space' into
1634 the bss segment. Note that this is *bad* practice. */
1635#define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1636 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1637
35d965d5
RS		 1638/* Output a source line for the debugger. */
1639/* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1640
1641/* Output a #ident directive. */
1642#define ASM_OUTPUT_IDENT(STREAM,STRING) \
1643 fprintf (STREAM,"- - - ident %s\n",STRING)
1644
1645/* The assembler's parentheses characters. */
1646#define ASM_OPEN_PAREN "("
1647#define ASM_CLOSE_PAREN ")"
1648
1649/* Target characters. */
1650#define TARGET_BELL 007
1651#define TARGET_BS 010
1652#define TARGET_TAB 011
1653#define TARGET_NEWLINE 012
1654#define TARGET_VT 013
1655#define TARGET_FF 014
1656#define TARGET_CR 015
1657\f
35d965d5
RS		 1658/* Only perform branch elimination (by making instructions conditional) if
1659 we're optimising. Otherwise it's of no use anyway. */
1660#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1661 if (optimize) \
1662 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1663
c383667d
DE		 1664#ifndef ASM_COMMENT_START
1665#define ASM_COMMENT_START "@"
7bc7696c
RE		 1666#endif
1667
1668#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1669 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1670/* Output an operand of an instruction. */
35d965d5 1671#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 1672 arm_print_operand (STREAM, X, CODE)
1673
1674#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1675 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1676 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1677 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1678 ? ((~ (HOST_WIDE_INT) 0) \
1679 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1680 : 0))))
35d965d5
RS		 1681
1682/* Output the address of an operand. */
1683#define PRINT_OPERAND_ADDRESS(STREAM,X) \
1684{ \
1685 int is_minus = GET_CODE (X) == MINUS; \
1686 \
1687 if (GET_CODE (X) == REG) \
c383667d 1688 fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \
4eda77ec 1689 reg_names[REGNO (X)]); \
35d965d5
RS		 1690 else if (GET_CODE (X) == PLUS || is_minus) \
1691 { \
1692 rtx base = XEXP (X, 0); \
1693 rtx index = XEXP (X, 1); \
1694 char *base_reg_name; \
7bc7696c 1695 HOST_WIDE_INT offset = 0; \
35d965d5
RS		 1696 if (GET_CODE (base) != REG) \
1697 { \
1698 /* Ensure that BASE is a register (one of them must be). */ \
1699 rtx temp = base; \
1700 base = index; \
1701 index = temp; \
1702 } \
1703 base_reg_name = reg_names[REGNO (base)]; \
1704 switch (GET_CODE (index)) \
1705 { \
1706 case CONST_INT: \
1707 offset = INTVAL (index); \
1708 if (is_minus) \
1709 offset = -offset; \
c383667d 1710 fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \
4eda77ec 1711 base_reg_name, offset); \
35d965d5
RS		 1712 break; \
1713 \
1714 case REG: \
c383667d 1715 fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \
4eda77ec 1716 base_reg_name, is_minus ? "-" : "", \
c383667d 1717 REGISTER_PREFIX, reg_names[REGNO (index)] ); \
35d965d5
RS		 1718 break; \
1719 \
1720 case MULT: \
ff9940b0
RE		 1721 case ASHIFTRT: \
1722 case LSHIFTRT: \
1723 case ASHIFT: \
ff9940b0
RE		 1724 case ROTATERT: \
1725 { \
c383667d
DE		 1726 fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \
1727 base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\
7bc7696c
RE		 1728 reg_names[REGNO (XEXP (index, 0))]); \
1729 arm_print_operand (STREAM, index, 'S'); \
1730 fputs ("]", STREAM); \
ff9940b0
RE		 1731 break; \
1732 } \
35d965d5
RS		 1733 \
1734 default: \
1735 abort(); \
1736 } \
1737 } \
1738 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1739 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1740 { \
1741 extern int output_memory_reference_mode; \
1742 \
1743 if (GET_CODE (XEXP (X, 0)) != REG) \
1744 abort (); \
1745 \
1746 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
c383667d 1747 fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \
4eda77ec 1748 reg_names[REGNO (XEXP (X, 0))], \
35d965d5
RS		 1749 GET_CODE (X) == PRE_DEC ? "-" : "", \
1750 GET_MODE_SIZE (output_memory_reference_mode)); \
1751 else \
c383667d 1752 fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \
4eda77ec 1753 reg_names[REGNO (XEXP (X, 0))], \
35d965d5
RS		 1754 GET_CODE (X) == POST_DEC ? "-" : "", \
1755 GET_MODE_SIZE (output_memory_reference_mode)); \
1756 } \
1757 else output_addr_const(STREAM, X); \
1758}
GNU Compiler Collection
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