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Added arg to RETURN_POPS_ARGS.
[gcc.git] / gcc / config / arm / arm.h
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35d965d5 1/* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
8b109b37 2 Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
35d965d5 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 4 and Martin Simmons (@harleqn.co.uk).
ff9940b0
RE		 5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
35d965d5
RS		 7This file is part of GNU CC.
8
9GNU CC is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14GNU CC is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with GNU CC; see the file COPYING. If not, write to
21the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
ea7273ae 23/* Sometimes the directive `riscos' is checked. This does not imply that this
35d965d5
RS		 24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
7bc7696c
RE		 27extern void output_func_prologue ();
28extern void output_func_epilogue ();
35d965d5
RS		 29extern char *output_add_immediate ();
30extern char *output_call ();
ff9940b0 31extern char *output_call_mem ();
35d965d5
RS		 32extern char *output_move_double ();
33extern char *output_mov_double_fpu_from_arm ();
34extern char *output_mov_double_arm_from_fpu ();
7fc6c9f0
RK		 35extern char *output_mov_long_double_fpu_from_arm ();
36extern char *output_mov_long_double_arm_from_fpu ();
37extern char *output_mov_long_double_arm_from_arm ();
35d965d5
RS		 38extern char *output_mov_immediate ();
39extern char *output_multi_immediate ();
ff9940b0
RE		 40extern char *output_return_instruction ();
41extern char *output_load_symbol ();
42extern char *fp_immediate_constant ();
43extern struct rtx_def *gen_compare_reg ();
44extern struct rtx_def *arm_gen_store_multiple ();
45extern struct rtx_def *arm_gen_load_multiple ();
46
47extern char *arm_condition_codes[];
48
49/* This is needed by the tail-calling peepholes */
50extern int frame_pointer_needed;
51
35d965d5 52\f
ff9940b0
RE		 53#ifndef CPP_PREDEFINES
54#define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
55#endif
35d965d5 56
ff9940b0
RE		 57#ifndef CPP_SPEC
58#define CPP_SPEC "%{m6:-D__arm6__}"
35d965d5
RS		 59#endif
60\f
61/* Run-time Target Specification. */
ff9940b0 62#ifndef TARGET_VERSION
35d965d5 63#define TARGET_VERSION \
ff9940b0
RE		 64 fputs (" (ARM/generic)", stderr);
65#endif
35d965d5
RS		 66
67/* Run-time compilation parameters selecting different hardware subsets.
68 On the ARM, misuse it in a different way. */
69extern int target_flags;
70
71/* Nonzero if the function prologue (and epilogue) should obey
72 the ARM Procedure Call Standard. */
73#define TARGET_APCS (target_flags & 1)
74
75/* Nonzero if the function prologue should output the function name to enable
76 the post mortem debugger to print a backtrace (very useful on RISCOS,
77 unused on RISCiX). Specifying this flag also enables -mapcs.
78 XXX Must still be implemented in the prologue. */
79#define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
80
81/* Nonzero if floating point instructions are emulated by the FPE, in which
82 case instruction scheduling becomes very uninteresting. */
83#define TARGET_FPE (target_flags & 4)
84
ff9940b0
RE		 85/* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
86 of condition flags when returning from a branch & link (ie. a function) */
87#define TARGET_6 (target_flags & 8)
88
2ce9c1b9
RE		 89/* Leave some bits for new processor variants */
90
91/* Nonzero if shorts must be loaded byte at a time. This is not necessary
92 for the arm processor chip, but it is needed for some MMU chips. */
93#define TARGET_SHORT_BY_BYTES (target_flags & 0x200)
94
ff9940b0
RE		 95/* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which
96 are passed to the preprocessor and the assembler post-processor. They
97 aren't needed in the main pass of the compiler, but if we don't define
98 them in target switches cc1 complains about them. For the sake of
99 argument lets allocate bit 31 of target flags for such options. */
100
101#ifndef ARM_EXTRA_TARGET_SWITCHES
102#define ARM_EXTRA_TARGET_SWITCHES
103#endif
104
2ce9c1b9
RE		 105#define TARGET_SWITCHES \
106{ \
107 {"apcs", 1}, \
108 {"poke-function-name", 2}, \
109 {"fpe", 4}, \
110 {"6", 8}, \
111 {"2", -8}, \
112 {"3", -8}, \
113 {"short-load-bytes", (0x200)}, \
114 {"no-short-load-bytes", -(0x200)}, \
115 {"short-load-words", -(0x200)}, \
116 {"no-short-load-words", (0x200)}, \
117 ARM_EXTRA_TARGET_SWITCHES \
118 {"", TARGET_DEFAULT } \
35d965d5
RS		 119}
120
ff9940b0
RE		 121/* Which processor we are running on. Currently this is only used to
122 get the condition code clobbering attribute right when we are running on
123 an arm 6 */
124
125enum processor_type
126{
127 PROCESSOR_ARM2,
128 PROCESSOR_ARM3,
129 PROCESSOR_ARM6
130};
131
132/* Recast the cpu class to be the cpu attribute. */
133
134/* Recast the cpu class to be the cpu attribute. */
135#define arm_cpu_attr ((enum attr_cpu)arm_cpu)
136
137extern enum processor_type arm_cpu;
138
24f0c1b4
RE		 139/* What sort of floating point unit do we have? Hardware or software. */
140enum floating_point_type
141{
142 FP_HARD,
143 FP_SOFT
144};
145
146/* Recast the floating point class to be the floating point attribute. */
147#define arm_fpu_attr ((enum attr_fpu) arm_fpu)
148
149extern enum floating_point_type arm_fpu;
150
2ce9c1b9 151#ifndef TARGET_DEFAULT
35d965d5 152#define TARGET_DEFAULT 0
2ce9c1b9 153#endif
35d965d5
RS		 154
155#define TARGET_MEM_FUNCTIONS 1
156
157/* OVERRIDE_OPTIONS takes care of the following:
158 - if -mpoke-function-name, then -mapcs.
159 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
160 - if floating point is done by emulation, forget about instruction
161 scheduling. Note that this only saves compilation time; it doesn't
162 matter for the final code. */
35d965d5
RS		 163
164#define OVERRIDE_OPTIONS \
165{ \
ff9940b0
RE		 166 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
167 warning ("-g without a frame pointer may not give sensible debugging");\
168 if (TARGET_POKE_FUNCTION_NAME) \
35d965d5
RS		 169 target_flags |= 1; \
170 if (TARGET_FPE) \
171 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
ff9940b0 172 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
35d965d5 173}
35d965d5
RS		 174\f
175/* Target machine storage Layout. */
176
ff9940b0
RE		 177
178/* Define this macro if it is advisable to hold scalars in registers
179 in a wider mode than that declared by the program. In such cases,
180 the value is constrained to be within the bounds of the declared
181 type, but kept valid in the wider mode. The signedness of the
182 extension may differ from that of the type. */
183
184/* It is far faster to zero extend chars than to sign extend them */
185
186#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
2ce9c1b9
RE		 187 if (GET_MODE_CLASS (MODE) == MODE_INT \
188 && GET_MODE_SIZE (MODE) < 4) \
189 { \
190 if (MODE == QImode) \
191 UNSIGNEDP = 1; \
192 else if (MODE == HImode) \
193 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
194 (MODE) = SImode; \
ff9940b0
RE		 195 }
196
197/* Define for XFmode extended real floating point support.
198 This will automatically cause REAL_ARITHMETIC to be defined. */
199/* For the ARM:
200 I think I have added all the code to make this work. Unfortunately,
201 early releases of the floating point emulation code on RISCiX used a
202 different format for extended precision numbers. On my RISCiX box there
203 is a bug somewhere which causes the machine to lock up when running enquire
204 with long doubles. There is the additional aspect that Norcroft C
205 treats long doubles as doubles and we ought to remain compatible.
206 Perhaps someone with an FPA coprocessor and not running RISCiX would like
207 to try this someday. */
208/* #define LONG_DOUBLE_TYPE_SIZE 96 */
209
210/* Disable XFmode patterns in md file */
211#define ENABLE_XF_PATTERNS 0
212
213/* Define if you don't want extended real, but do want to use the
214 software floating point emulator for REAL_ARITHMETIC and
215 decimal <-> binary conversion. */
216/* See comment above */
217#define REAL_ARITHMETIC
218
35d965d5
RS		 219/* Define this if most significant bit is lowest numbered
220 in instructions that operate on numbered bit-fields. */
221#define BITS_BIG_ENDIAN 0
222
9c872872
RE		 223/* Define this if most significant byte of a word is the lowest numbered.
224 Most ARM processors are run in little endian mode, but it should now be
225 possible to build the compiler to support big endian code. (Note: This
226 is currently a compiler-build-time option, not a run-time one. */
227#ifndef BYTES_BIG_ENDIAN
35d965d5 228#define BYTES_BIG_ENDIAN 0
9c872872 229#endif
35d965d5
RS		 230
231/* Define this if most significant word of a multiword number is the lowest
232 numbered. */
233#define WORDS_BIG_ENDIAN 0
234
7fc6c9f0
RK		 235/* Define this if most significant word of doubles is the lowest numbered */
236#define FLOAT_WORDS_BIG_ENDIAN 1
237
b4ac57ab 238/* Number of bits in an addressable storage unit */
35d965d5
RS		 239#define BITS_PER_UNIT 8
240
241#define BITS_PER_WORD 32
242
243#define UNITS_PER_WORD 4
244
245#define POINTER_SIZE 32
246
247#define PARM_BOUNDARY 32
248
249#define STACK_BOUNDARY 32
250
251#define FUNCTION_BOUNDARY 32
252
253#define EMPTY_FIELD_BOUNDARY 32
254
255#define BIGGEST_ALIGNMENT 32
256
ff9940b0
RE		 257/* Make strings word-aligned so strcpy from constants will be faster. */
258#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
259 (TREE_CODE (EXP) == STRING_CST \
260 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
261
b4ac57ab
RS		 262/* Every structures size must be a multiple of 32 bits. */
263#define STRUCTURE_SIZE_BOUNDARY 32
264
ff9940b0
RE		 265/* Non-zero if move instructions will actually fail to work
266 when given unaligned data. */
35d965d5
RS		 267#define STRICT_ALIGNMENT 1
268
ff9940b0
RE		 269#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
270
35d965d5
RS		 271/* Define number of bits in most basic integer type.
272 (If undefined, default is BITS_PER_WORD). */
273/* #define INT_TYPE_SIZE */
274\f
275/* Standard register usage. */
276
277/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
278 (S - saved over call).
279
280 r0 * argument word/integer result
281 r1-r3 argument word
282
283 r4-r8 S register variable
284 r9 S (rfp) register variable (real frame pointer)
285
286 r10 F S (sl) stack limit (not currently used)
287 r11 F S (fp) argument pointer
288 r12 (ip) temp workspace
289 r13 F S (sp) lower end of current stack frame
290 r14 (lr) link address/workspace
291 r15 F (pc) program counter
292
293 f0 floating point result
294 f1-f3 floating point scratch
295
296 f4-f7 S floating point variable
297
ff9940b0
RE		 298 cc This is NOT a real register, but is used internally
299 to represent things that use or set the condition
300 codes.
301 sfp This isn't either. It is used during rtl generation
302 since the offset between the frame pointer and the
303 auto's isn't known until after register allocation.
304 afp Nor this, we only need this because of non-local
305 goto. Without it fp appears to be used and the
306 elimination code won't get rid of sfp. It tracks
307 fp exactly at all times.
308
35d965d5
RS		 309 *: See CONDITIONAL_REGISTER_USAGE */
310
ff9940b0
RE		 311/* The stack backtrace structure is as follows:
312 fp points to here: | save code pointer | [fp]
313 | return link value | [fp, #-4]
314 | return sp value | [fp, #-8]
315 | return fp value | [fp, #-12]
316 [| saved r10 value |]
317 [| saved r9 value |]
318 [| saved r8 value |]
319 [| saved r7 value |]
320 [| saved r6 value |]
321 [| saved r5 value |]
322 [| saved r4 value |]
323 [| saved r3 value |]
324 [| saved r2 value |]
325 [| saved r1 value |]
326 [| saved r0 value |]
327 [| saved f7 value |] three words
328 [| saved f6 value |] three words
329 [| saved f5 value |] three words
330 [| saved f4 value |] three words
331 r0-r3 are not normally saved in a C function. */
332
333/* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
334#define FIRST_PSEUDO_REGISTER 27
35d965d5
RS		 335
336/* 1 for registers that have pervasive standard uses
337 and are not available for the register allocator. */
338#define FIXED_REGISTERS \
339{ \
340 0,0,0,0,0,0,0,0, \
341 0,0,1,1,0,1,0,1, \
ff9940b0
RE		 342 0,0,0,0,0,0,0,0, \
343 1,1,1 \
35d965d5
RS		 344}
345
346/* 1 for registers not available across function calls.
347 These must include the FIXED_REGISTERS and also any
348 registers that can be used without being saved.
349 The latter must include the registers where values are returned
350 and the register where structure-value addresses are passed.
ff9940b0
RE		 351 Aside from that, you can include as many other registers as you like.
352 The CC is not preserved over function calls on the ARM 6, so it is
353 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 354#define CALL_USED_REGISTERS \
355{ \
356 1,1,1,1,0,0,0,0, \
357 0,0,1,1,1,1,1,1, \
ff9940b0
RE		 358 1,1,1,1,0,0,0,0, \
359 1,1,1 \
35d965d5
RS		 360}
361
362/* If doing stupid life analysis, avoid a bug causing a return value r0 to be
363 trampled. This effectively reduces the number of available registers by 1.
364 XXX It is a hack, I know.
365 XXX Is this still needed? */
366#define CONDITIONAL_REGISTER_USAGE \
367{ \
368 if (obey_regdecls) \
369 fixed_regs[0] = 1; \
370}
371
372/* Return number of consecutive hard regs needed starting at reg REGNO
373 to hold something of mode MODE.
374 This is ordinarily the length in words of a value of mode MODE
375 but can be less for certain modes in special long registers.
376
377 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
378 mode. */
ff9940b0
RE		 379#define HARD_REGNO_NREGS(REGNO, MODE) \
380 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
381 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
35d965d5
RS		 382 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
383
384/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
385 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
386 regs holding FP. */
ff9940b0
RE		 387#define HARD_REGNO_MODE_OK(REGNO, MODE) \
388 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
389 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
390 || REGNO == ARG_POINTER_REGNUM \
391 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
35d965d5
RS		 392
393/* Value is 1 if it is a good idea to tie two pseudo registers
394 when one has mode MODE1 and one has mode MODE2.
395 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
396 for any hard reg, then this must be 0 for correct output. */
397#define MODES_TIEABLE_P(MODE1, MODE2) \
3967692c 398 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
35d965d5
RS		 399
400/* Specify the registers used for certain standard purposes.
401 The values of these macros are register numbers. */
402
403/* Define this if the program counter is overloaded on a register. */
404#define PC_REGNUM 15
405
406/* Register to use for pushing function arguments. */
407#define STACK_POINTER_REGNUM 13
408
409/* Base register for access to local variables of the function. */
ff9940b0
RE		 410#define FRAME_POINTER_REGNUM 25
411
412/* Define this to be where the real frame pointer is if it is not possible to
413 work out the offset between the frame pointer and the automatic variables
414 until after register allocation has taken place. FRAME_POINTER_REGNUM
415 should point to a special register that we will make sure is eliminated. */
416#define HARD_FRAME_POINTER_REGNUM 11
35d965d5
RS		 417
418/* Value should be nonzero if functions must have frame pointers.
419 Zero means the frame pointer need not be set up (and parms may be accessed
ff9940b0
RE		 420 via the stack pointer) in functions that seem suitable.
421 If we have to have a frame pointer we might as well make use of it.
422 APCS says that the frame pointer does not need to be pushed in leaf
423 functions. */
688743e7
RE		 424#define FRAME_POINTER_REQUIRED \
425 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
35d965d5
RS		 426
427/* Base register for access to arguments of the function. */
ff9940b0 428#define ARG_POINTER_REGNUM 26
35d965d5
RS		 429
430/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
431 as an invisible last argument (possible since varargs don't exist in
432 Pascal), so the following is not true. */
433#define STATIC_CHAIN_REGNUM 8
434
435/* Register in which address to store a structure value
436 is passed to a function. */
437#define STRUCT_VALUE_REGNUM 0
438
ff9940b0
RE		 439/* Internal, so that we don't need to refer to a raw number */
440#define CC_REGNUM 24
441
35d965d5 442/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 443 since no saving is required (though calls clobber it) and it never contains
444 function parameters. It is quite good to use lr since other calls may
445 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
446 least likely to contain a function parameter; in addition results are
447 returned in r0.
448 */
35d965d5
RS		 449#define REG_ALLOC_ORDER \
450{ \
ff9940b0 451 3, 2, 1, 0, 12, 14, 4, 5, \
35d965d5 452 6, 7, 8, 10, 9, 11, 13, 15, \
ff9940b0
RE		 453 16, 17, 18, 19, 20, 21, 22, 23, \
454 24, 25 \
35d965d5
RS		 455}
456\f
457/* Register and constant classes. */
458
459/* Register classes: all ARM regs or all FPU regs---simple! */
460enum reg_class
461{
462 NO_REGS,
463 FPU_REGS,
464 GENERAL_REGS,
465 ALL_REGS,
466 LIM_REG_CLASSES
467};
468
469#define N_REG_CLASSES (int) LIM_REG_CLASSES
470
471/* Give names of register classes as strings for dump file. */
472#define REG_CLASS_NAMES \
473{ \
474 "NO_REGS", \
475 "FPU_REGS", \
476 "GENERAL_REGS", \
477 "ALL_REGS", \
478}
479
480/* Define which registers fit in which classes.
481 This is an initializer for a vector of HARD_REG_SET
482 of length N_REG_CLASSES. */
483#define REG_CLASS_CONTENTS \
484{ \
ff9940b0
RE		 485 0x0000000, /* NO_REGS */ \
486 0x0FF0000, /* FPU_REGS */ \
487 0x200FFFF, /* GENERAL_REGS */ \
488 0x2FFFFFF /* ALL_REGS */ \
35d965d5
RS		 489}
490
491/* The same information, inverted:
492 Return the class number of the smallest class containing
493 reg number REGNO. This could be a conditional expression
494 or could index an array. */
ff9940b0
RE		 495#define REGNO_REG_CLASS(REGNO) \
496 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
497 || REGNO == ARG_POINTER_REGNUM) \
498 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
499 ? NO_REGS : FPU_REGS)
35d965d5
RS		 500
501/* The class value for index registers, and the one for base regs. */
502#define INDEX_REG_CLASS GENERAL_REGS
503#define BASE_REG_CLASS GENERAL_REGS
504
505/* Get reg_class from a letter such as appears in the machine description.
506 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
507#define REG_CLASS_FROM_LETTER(C) \
508 ((C)=='f' ? FPU_REGS : NO_REGS)
509
510/* The letters I, J, K, L and M in a register constraint string
511 can be used to stand for particular ranges of immediate operands.
512 This macro defines what the ranges are.
513 C is the letter, and VALUE is a constant value.
514 Return 1 if VALUE is in the range specified by C.
b4ac57ab 515 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
ff9940b0 516 J: valid indexing constants.
aef1764c 517 K: ~value ok in rhs argument of data operand.
3967692c
RE		 518 L: -value ok in rhs argument of data operand.
519 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
aef1764c
RE		 520#define CONST_OK_FOR_LETTER_P(VALUE, C) \
521 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
522 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
523 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
3967692c
RE		 524 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
525 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
526 || (((VALUE) & ((VALUE) - 1)) == 0)) \
527 : 0)
ff9940b0
RE		 528
529/* For the ARM, `Q' means that this is a memory operand that is just
530 an offset from a register.
531 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
532 address. This means that the symbol is in the text segment and can be
533 accessed without using a load. */
534
535#define EXTRA_CONSTRAINT(OP, C) \
536 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
008cf58a
RE		 537 : (C) == 'R' ? (GET_CODE (OP) == MEM \
538 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
539 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
540 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0)
ff9940b0
RE		 541
542/* Constant letter 'G' for the FPU immediate constants.
543 'H' means the same constant negated. */
544#define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
545 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
546 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
35d965d5
RS		 547
548/* Given an rtx X being reloaded into a reg required to be
549 in class CLASS, return the class of reg to actually use.
550 In general this is just CLASS; but on some machines
551 in some cases it is preferable to use a more restrictive class. */
552#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
553
ff9940b0
RE		 554/* Return the register class of a scratch register needed to copy IN into
555 or out of a register in CLASS in MODE. If it can be done directly,
556 NO_REGS is returned. */
557#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
558 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
559 && true_regnum (X) == -1) ? GENERAL_REGS \
7fc6c9f0 560 : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS)
ff9940b0 561
2ce9c1b9
RE		 562/* If we need to load shorts byte-at-a-time, then we need a scratch. */
563#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
564 (((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \
565 ? GENERAL_REGS : NO_REGS)
566
35d965d5
RS		 567/* Return the maximum number of consecutive registers
568 needed to represent mode MODE in a register of class CLASS.
569 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
570#define CLASS_MAX_NREGS(CLASS, MODE) \
571 ((CLASS) == FPU_REGS ? 1 \
572 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
573
ff9940b0 574/* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
35d965d5
RS		 575#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
576 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
577 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
ff9940b0 578 ? 20 : 2)
35d965d5
RS		 579\f
580/* Stack layout; function entry, exit and calling. */
581
582/* Define this if pushing a word on the stack
583 makes the stack pointer a smaller address. */
584#define STACK_GROWS_DOWNWARD 1
585
586/* Define this if the nominal address of the stack frame
587 is at the high-address end of the local variables;
588 that is, each additional local variable allocated
589 goes at a more negative offset in the frame. */
590#define FRAME_GROWS_DOWNWARD 1
591
592/* Offset within stack frame to start allocating local variables at.
593 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
594 first local allocated. Otherwise, it is the offset to the BEGINNING
595 of the first local allocated. */
596#define STARTING_FRAME_OFFSET 0
597
598/* If we generate an insn to push BYTES bytes,
599 this says how many the stack pointer really advances by. */
600#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
601
602/* Offset of first parameter from the argument pointer register value. */
603#define FIRST_PARM_OFFSET(FNDECL) 4
604
605/* Value is the number of byte of arguments automatically
606 popped when returning from a subroutine call.
8b109b37 607 FUNDECL is the declaration node of the function (as a tree),
35d965d5
RS		 608 FUNTYPE is the data type of the function (as a tree),
609 or for a library call it is an identifier node for the subroutine name.
610 SIZE is the number of bytes of arguments passed on the stack.
611
612 On the ARM, the caller does not pop any of its arguments that were passed
613 on the stack. */
8b109b37 614#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
35d965d5
RS		 615
616/* Define how to find the value returned by a function.
617 VALTYPE is the data type of the value (as a tree).
618 If the precise function being called is known, FUNC is its FUNCTION_DECL;
619 otherwise, FUNC is 0. */
620#define FUNCTION_VALUE(VALTYPE, FUNC) \
621 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
622 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
623 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
624
625/* Define how to find the value returned by a library function
626 assuming the value has mode MODE. */
627#define LIBCALL_VALUE(MODE) \
628 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
629 ? gen_rtx (REG, MODE, 16) \
630 : gen_rtx (REG, MODE, 0))
631
632/* 1 if N is a possible register number for a function value.
633 On the ARM, only r0 and f0 can return results. */
634#define FUNCTION_VALUE_REGNO_P(REGNO) \
635 ((REGNO) == 0 || (REGNO) == 16)
636
637/* Define where to put the arguments to a function.
638 Value is zero to push the argument on the stack,
639 or a hard register in which to store the argument.
640
641 MODE is the argument's machine mode.
642 TYPE is the data type of the argument (as a tree).
643 This is null for libcalls where that information may
644 not be available.
645 CUM is a variable of type CUMULATIVE_ARGS which gives info about
646 the preceding args and about the function being called.
647 NAMED is nonzero if this argument is a named parameter
648 (otherwise it is an extra parameter matching an ellipsis).
649
650 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
651 other arguments are passed on the stack. If (NAMED == 0) (which happens
652 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
653 passed in the stack (function_prologue will indeed make it pass in the
654 stack if necessary). */
655#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
656 ((NAMED) \
657 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
658 : 0)
659
660/* For an arg passed partly in registers and partly in memory,
661 this is the number of registers used.
662 For args passed entirely in registers or entirely in memory, zero. */
663#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
664 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
665 ? GET_MODE_SIZE (MODE) \
666 : int_size_in_bytes (TYPE)) \
667 ? 4 - (CUM) / 4 : 0)
668
669/* A C type for declaring a variable that is used as the first argument of
670 `FUNCTION_ARG' and other related values. For some target machines, the
671 type `int' suffices and can hold the number of bytes of argument so far.
672
673 On the ARM, this is the number of bytes of arguments scanned so far. */
674#define CUMULATIVE_ARGS int
675
676/* Initialize a variable CUM of type CUMULATIVE_ARGS
677 for a call to a function whose data type is FNTYPE.
678 For a library call, FNTYPE is 0.
679 On the ARM, the offset starts at 0. */
680#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
ff9940b0 681 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
35d965d5
RS		 682
683/* Update the data in CUM to advance over an argument
684 of mode MODE and data type TYPE.
685 (TYPE is null for libcalls where that information may not be available.) */
686#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
687 (CUM) += ((MODE) != BLKmode \
688 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
689 : (int_size_in_bytes (TYPE) + 3) & ~3) \
690
691/* 1 if N is a possible register number for function argument passing.
692 On the ARM, r0-r3 are used to pass args. */
693#define FUNCTION_ARG_REGNO_P(REGNO) \
694 ((REGNO) >= 0 && (REGNO) <= 3)
695
696/* Perform any actions needed for a function that is receiving a variable
697 number of arguments. CUM is as above. MODE and TYPE are the mode and type
698 of the current parameter. PRETEND_SIZE is a variable that should be set to
699 the amount of stack that must be pushed by the prolog to pretend that our
700 caller pushed it.
701
702 Normally, this macro will push all remaining incoming registers on the
703 stack and set PRETEND_SIZE to the length of the registers pushed.
704
705 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
706 named arg and all anonymous args onto the stack.
707 XXX I know the prologue shouldn't be pushing registers, but it is faster
708 that way. */
709#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
710{ \
711 extern int current_function_anonymous_args; \
712 current_function_anonymous_args = 1; \
713 if ((CUM) < 16) \
714 (PRETEND_SIZE) = 16 - (CUM); \
715}
716
717/* Generate assembly output for the start of a function. */
718#define FUNCTION_PROLOGUE(STREAM, SIZE) \
008cf58a 719 output_func_prologue ((STREAM), (SIZE))
35d965d5
RS		 720
721/* Call the function profiler with a given profile label. The Acorn compiler
722 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
723 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
724 to mind about this! */
4eda77ec
RE		 725#define FUNCTION_PROFILER(STREAM,LABELNO) \
726{ \
727 fprintf(STREAM, "\tmov\t%sip, %slr\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
728 fprintf(STREAM, "\tbl\tmcount\n"); \
729 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
35d965d5
RS		 730}
731
732/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
733 the stack pointer does not matter. The value is tested only in
734 functions that have frame pointers.
735 No definition is equivalent to always zero.
736
737 On the ARM, the function epilogue recovers the stack pointer from the
738 frame. */
739#define EXIT_IGNORE_STACK 1
740
741/* Generate the assembly code for function exit. */
742#define FUNCTION_EPILOGUE(STREAM, SIZE) \
008cf58a 743 output_func_epilogue ((STREAM), (SIZE))
35d965d5
RS		 744
745/* Determine if the epilogue should be output as RTL.
746 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
ff9940b0
RE		 747#define USE_RETURN_INSN use_return_insn ()
748
749/* Definitions for register eliminations.
750
751 This is an array of structures. Each structure initializes one pair
752 of eliminable registers. The "from" register number is given first,
753 followed by "to". Eliminations of the same "from" register are listed
754 in order of preference.
755
756 We have two registers that can be eliminated on the ARM. First, the
757 arg pointer register can often be eliminated in favor of the stack
758 pointer register. Secondly, the pseudo frame pointer register can always
759 be eliminated; it is replaced with either the stack or the real frame
760 pointer. */
761
762#define ELIMINABLE_REGS \
763{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
764 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
765 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
766 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
767
768/* Given FROM and TO register numbers, say whether this elimination is allowed.
769 Frame pointer elimination is automatically handled.
770
771 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
772 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
773 pointer, we must eliminate FRAME_POINTER_REGNUM into
774 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
775#define CAN_ELIMINATE(FROM, TO) \
776 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
777
778/* Define the offset between two registers, one to be eliminated, and the other
779 its replacement, at the start of a routine. */
780#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
781{ \
3967692c 782 int volatile_func = arm_volatile_func (); \
ff9940b0
RE		 783 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
784 (OFFSET) = 0; \
785 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
786 (OFFSET) = (get_frame_size () + 3 & ~3); \
787 else \
788 { \
789 int regno; \
790 int offset = 12; \
008cf58a 791 int saved_hard_reg = 0; \
ff9940b0 792 \
3967692c
RE		 793 if (! volatile_func) \
794 { \
795 for (regno = 0; regno <= 10; regno++) \
796 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
797 saved_hard_reg = 1, offset += 4; \
798 for (regno = 16; regno <=23; regno++) \
799 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
800 offset += 12; \
801 } \
ff9940b0
RE		 802 if ((FROM) == FRAME_POINTER_REGNUM) \
803 (OFFSET) = -offset; \
804 else \
805 { \
bd4d60ce 806 if (! frame_pointer_needed) \
ff9940b0 807 offset -= 16; \
3967692c 808 if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \
ff9940b0
RE		 809 offset += 4; \
810 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
811 } \
812 } \
813}
35d965d5 814
35d965d5
RS		 815/* Output assembler code for a block containing the constant parts
816 of a trampoline, leaving space for the variable parts.
817
818 On the ARM, (if r8 is the static chain regnum, and remembering that
819 referencing pc adds an offset of 8) the trampoline looks like:
820 ldr r8, [pc, #0]
821 ldr pc, [pc]
822 .word static chain value
823 .word function's address */
4eda77ec
RE		 824#define TRAMPOLINE_TEMPLATE(FILE) \
825{ \
826 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", ARM_REG_PREFIX, \
827 ARM_REG_PREFIX); \
828 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", ARM_REG_PREFIX, \
829 ARM_REG_PREFIX); \
830 fprintf ((FILE), "\t.word\t0\n"); \
831 fprintf ((FILE), "\t.word\t0\n"); \
35d965d5
RS		 832}
833
834/* Length in units of the trampoline for entering a nested function. */
835#define TRAMPOLINE_SIZE 16
836
837/* Alignment required for a trampoline in units. */
838#define TRAMPOLINE_ALIGN 4
839
840/* Emit RTL insns to initialize the variable parts of a trampoline.
841 FNADDR is an RTX for the address of the function's pure code.
842 CXT is an RTX for the static chain value for the function. */
843#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
844{ \
845 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
846 (CXT)); \
847 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
848 (FNADDR)); \
849}
850
35d965d5
RS		 851\f
852/* Addressing modes, and classification of registers for them. */
853
854#define HAVE_POST_INCREMENT 1
855#define HAVE_PRE_INCREMENT 1
856#define HAVE_POST_DECREMENT 1
857#define HAVE_PRE_DECREMENT 1
858
859/* Macros to check register numbers against specific register classes. */
860
861/* These assume that REGNO is a hard or pseudo reg number.
862 They give nonzero only if REGNO is a hard reg of the suitable class
863 or a pseudo reg currently allocated to a suitable hard reg.
864 Since they use reg_renumber, they are safe only once reg_renumber
865 has been allocated, which happens in local-alloc.c.
866
867 On the ARM, don't allow the pc to be used. */
ff9940b0
RE		 868#define REGNO_OK_FOR_BASE_P(REGNO) \
869 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
870 || (REGNO) == ARG_POINTER_REGNUM \
871 || (unsigned) reg_renumber[(REGNO)] < 15 \
872 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
873 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
874#define REGNO_OK_FOR_INDEX_P(REGNO) \
35d965d5
RS		 875 REGNO_OK_FOR_BASE_P(REGNO)
876
877/* Maximum number of registers that can appear in a valid memory address.
ff9940b0
RE		 878 Shifts in addresses can't be by a register. */
879
880#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 881
882/* Recognize any constant value that is a valid address. */
883/* XXX We can address any constant, eventually... */
884#if 0
885#define CONSTANT_ADDRESS_P(X) \
886 ( GET_CODE(X) == LABEL_REF \
887 || GET_CODE(X) == SYMBOL_REF \
888 || GET_CODE(X) == CONST_INT \
889 || GET_CODE(X) == CONST )
890#endif
891
008cf58a
RE		 892#define CONSTANT_ADDRESS_P(X) \
893 (GET_CODE (X) == SYMBOL_REF \
894 && (CONSTANT_POOL_ADDRESS_P (X) \
895 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5
RS		 896
897/* Nonzero if the constant value X is a legitimate general operand.
898 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
899
900 On the ARM, allow any integer (invalid ones are removed later by insn
901 patterns), nice doubles and symbol_refs which refer to the function's
902 constant pool XXX. */
903#define LEGITIMATE_CONSTANT_P(X) \
904 (GET_CODE (X) == CONST_INT \
905 || (GET_CODE (X) == CONST_DOUBLE \
ff9940b0
RE		 906 && (const_double_rtx_ok_for_fpu (X) \
907 || neg_const_double_rtx_ok_for_fpu (X))) \
908 || CONSTANT_ADDRESS_P (X))
909
910/* Symbols in the text segment can be accessed without indirecting via the
911 constant pool; it may take an extra binary operation, but this is still
008cf58a
RE		 912 faster than indirecting via memory. Don't do this when not optimizing,
913 since we won't be calculating al of the offsets necessary to do this
914 simplification. */
ff9940b0
RE		 915
916#define ENCODE_SECTION_INFO(decl) \
917{ \
008cf58a 918 if (optimize > 0 && TREE_CONSTANT (decl) \
ff9940b0 919 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
228b6a3f
RS		 920 { \
921 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
922 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
923 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
924 } \
ff9940b0 925}
35d965d5
RS		 926
927/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
928 and check its validity for a certain class.
929 We have two alternate definitions for each of them.
930 The usual definition accepts all pseudo regs; the other rejects
931 them unless they have been allocated suitable hard regs.
932 The symbol REG_OK_STRICT causes the latter definition to be used. */
933#ifndef REG_OK_STRICT
ff9940b0 934
35d965d5
RS		 935/* Nonzero if X is a hard reg that can be used as a base reg
936 or if it is a pseudo reg. */
ff9940b0
RE		 937#define REG_OK_FOR_BASE_P(X) \
938 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
939 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
940
35d965d5
RS		 941/* Nonzero if X is a hard reg that can be used as an index
942 or if it is a pseudo reg. */
943#define REG_OK_FOR_INDEX_P(X) \
944 REG_OK_FOR_BASE_P(X)
ff9940b0
RE		 945
946#define REG_OK_FOR_PRE_POST_P(X) \
947 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
948 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
949
35d965d5 950#else
ff9940b0 951
35d965d5
RS		 952/* Nonzero if X is a hard reg that can be used as a base reg. */
953#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 954
35d965d5
RS		 955/* Nonzero if X is a hard reg that can be used as an index. */
956#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
ff9940b0
RE		 957
958#define REG_OK_FOR_PRE_POST_P(X) \
959 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
960 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
961 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
962 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
963
35d965d5
RS		 964#endif
965\f
966/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
967 that is a valid memory address for an instruction.
968 The MODE argument is the machine mode for the MEM expression
969 that wants to use this address.
970
971 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
972#define BASE_REGISTER_RTX_P(X) \
973 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
974
975#define INDEX_REGISTER_RTX_P(X) \
976 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
977
978/* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
979 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
980 only be small constants. */
ff9940b0 981#define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
4d01c30f
RS		 982do \
983{ \
008cf58a
RE		 984 HOST_WIDE_INT range; \
985 enum rtx_code code = GET_CODE (INDEX); \
4d01c30f
RS		 986 \
987 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
ff9940b0
RE		 988 { \
989 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
990 && INTVAL (INDEX) > -1024 \
991 && (INTVAL (INDEX) & 3) == 0) \
992 goto LABEL; \
993 } \
4d01c30f
RS		 994 else \
995 { \
ff9940b0 996 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
4d01c30f 997 goto LABEL; \
ff9940b0 998 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
4d01c30f
RS		 999 { \
1000 rtx xiop0 = XEXP (INDEX, 0); \
1001 rtx xiop1 = XEXP (INDEX, 1); \
1002 if (INDEX_REGISTER_RTX_P (xiop0) \
1003 && power_of_two_operand (xiop1, SImode)) \
1004 goto LABEL; \
1005 if (INDEX_REGISTER_RTX_P (xiop1) \
1006 && power_of_two_operand (xiop0, SImode)) \
1007 goto LABEL; \
1008 } \
ff9940b0 1009 if (GET_MODE_SIZE (MODE) <= 4 \
996a5f59 1010 && (code == LSHIFTRT || code == ASHIFTRT \
ff9940b0
RE		 1011 || code == ASHIFT || code == ROTATERT)) \
1012 { \
1013 rtx op = XEXP (INDEX, 1); \
1014 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1015 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1016 && INTVAL (op) <= 31) \
1017 goto LABEL; \
1018 } \
1019 range = (MODE) == HImode ? 4095 : 4096; \
1020 if (code == CONST_INT && INTVAL (INDEX) < range \
1021 && INTVAL (INDEX) > -range) \
1022 goto LABEL; \
4d01c30f 1023 } \
35d965d5
RS		 1024} while (0)
1025
1026/* Jump to LABEL if X is a valid address RTX. This must also take
1027 REG_OK_STRICT into account when deciding about valid registers, but it uses
1028 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1029 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
ff9940b0
RE		 1030 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1031 refs must be forced though a static cell to ensure addressability. */
35d965d5
RS		 1032#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1033{ \
1034 if (BASE_REGISTER_RTX_P (X)) \
1035 goto LABEL; \
1036 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1037 && GET_CODE (XEXP (X, 0)) == REG \
1038 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1039 goto LABEL; \
1040 else if ((MODE) == TImode) \
1041 ; \
1042 else if (GET_CODE (X) == PLUS) \
1043 { \
1044 rtx xop0 = XEXP(X,0); \
1045 rtx xop1 = XEXP(X,1); \
1046 \
1047 if (BASE_REGISTER_RTX_P (xop0)) \
1048 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1049 else if (BASE_REGISTER_RTX_P (xop1)) \
1050 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1051 } \
1052 else if (GET_CODE (X) == MINUS) \
1053 { \
1054 rtx xop0 = XEXP (X,0); \
1055 rtx xop1 = XEXP (X,1); \
1056 \
1057 if (BASE_REGISTER_RTX_P (xop0)) \
1058 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1059 } \
1060 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1061 && GET_CODE (X) == SYMBOL_REF \
1062 && CONSTANT_POOL_ADDRESS_P (X)) \
1063 goto LABEL; \
1064 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1065 && GET_CODE (XEXP (X, 0)) == REG \
1066 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1067 goto LABEL; \
1068}
1069\f
1070/* Try machine-dependent ways of modifying an illegitimate address
1071 to be legitimate. If we find one, return the new, valid address.
1072 This macro is used in only one place: `memory_address' in explow.c.
1073
1074 OLDX is the address as it was before break_out_memory_refs was called.
1075 In some cases it is useful to look at this to decide what needs to be done.
1076
1077 MODE and WIN are passed so that this macro can use
1078 GO_IF_LEGITIMATE_ADDRESS.
1079
1080 It is always safe for this macro to do nothing. It exists to recognize
1081 opportunities to optimize the output.
1082
1083 On the ARM, try to convert [REG, #BIGCONST]
1084 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1085 where VALIDCONST == 0 in case of TImode. */
3967692c
RE		 1086#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1087{ \
1088 if (GET_CODE (X) == PLUS) \
1089 { \
1090 rtx xop0 = XEXP (X, 0); \
1091 rtx xop1 = XEXP (X, 1); \
1092 \
1093 if (CONSTANT_P (xop0) && ! LEGITIMATE_CONSTANT_P (xop0)) \
1094 xop0 = force_reg (SImode, xop0); \
1095 if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \
1096 xop1 = force_reg (SImode, xop1); \
1097 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1098 { \
1099 HOST_WIDE_INT n, low_n; \
1100 rtx base_reg, val; \
1101 n = INTVAL (xop1); \
1102 \
1103 if (MODE == DImode) \
1104 { \
1105 low_n = n & 0x0f; \
1106 n &= ~0x0f; \
1107 if (low_n > 4) \
1108 { \
1109 n += 16; \
1110 low_n -= 16; \
1111 } \
1112 } \
1113 else \
1114 { \
1115 low_n = ((MODE) == TImode ? 0 \
1116 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1117 n -= low_n; \
1118 } \
1119 base_reg = gen_reg_rtx (SImode); \
1120 val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1121 GEN_INT (n)), NULL_RTX); \
1122 emit_move_insn (base_reg, val); \
1123 (X) = (low_n == 0 ? base_reg \
1124 : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \
1125 } \
1126 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1127 (X) = gen_rtx (PLUS, SImode, xop0, xop1); \
1128 } \
1129 else if (GET_CODE (X) == MINUS) \
1130 { \
1131 rtx xop0 = XEXP (X, 0); \
1132 rtx xop1 = XEXP (X, 1); \
1133 \
1134 if (CONSTANT_P (xop0)) \
1135 xop0 = force_reg (SImode, xop0); \
1136 if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \
1137 xop1 = force_reg (SImode, xop1); \
1138 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1139 (X) = gen_rtx (MINUS, SImode, xop0, xop1); \
1140 } \
1141 if (memory_address_p (MODE, X)) \
1142 goto WIN; \
35d965d5
RS		 1143}
1144
3967692c 1145
35d965d5
RS		 1146/* Go to LABEL if ADDR (a legitimate address expression)
1147 has an effect that depends on the machine mode it is used for. */
1148#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1149{ \
1150 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1151 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1152 goto LABEL; \
1153}
1154\f
1155/* Specify the machine mode that this machine uses
1156 for the index in the tablejump instruction. */
1157#define CASE_VECTOR_MODE SImode
1158
1159/* Define this if the tablejump instruction expects the table
1160 to contain offsets from the address of the table.
1161 Do not define this if the table should contain absolute addresses. */
1162/* #define CASE_VECTOR_PC_RELATIVE */
1163
1164/* Specify the tree operation to be used to convert reals to integers. */
1165#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1166
1167/* This is the kind of divide that is easiest to do in the general case. */
1168#define EASY_DIV_EXPR TRUNC_DIV_EXPR
1169
ff9940b0
RE		 1170/* signed 'char' is most compatible, but RISC OS wants it unsigned.
1171 unsigned is probably best, but may break some code. */
1172#ifndef DEFAULT_SIGNED_CHAR
3967692c 1173#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 1174#endif
1175
1176/* Don't cse the address of the function being compiled. */
1177#define NO_RECURSIVE_FUNCTION_CSE 1
1178
1179/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 1180 in one reasonably fast instruction. */
1181#define MOVE_MAX 4
35d965d5 1182
ff9940b0
RE		 1183/* Define if operations between registers always perform the operation
1184 on the full register even if a narrower mode is specified. */
1185#define WORD_REGISTER_OPERATIONS
1186
1187/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1188 will either zero-extend or sign-extend. The value of this macro should
1189 be the code that says which one of the two operations is implicitly
1190 done, NIL if none. */
9c872872
RE		 1191#define LOAD_EXTEND_OP(MODE) \
1192 ((MODE) == QImode ? ZERO_EXTEND \
1193 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
ff9940b0 1194
35d965d5
RS		 1195/* Define this if zero-extension is slow (more than one real instruction).
1196 On the ARM, it is more than one instruction only if not fetching from
1197 memory. */
1198/* #define SLOW_ZERO_EXTEND */
1199
1200/* Nonzero if access to memory by bytes is slow and undesirable. */
1201#define SLOW_BYTE_ACCESS 0
1202
1203/* Immediate shift counts are truncated by the output routines (or was it
1204 the assembler?). Shift counts in a register are truncated by ARM. Note
1205 that the native compiler puts too large (> 32) immediate shift counts
1206 into a register and shifts by the register, letting the ARM decide what
1207 to do instead of doing that itself. */
ff9940b0
RE		 1208/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1209 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1210 On the arm, Y in a register is used modulo 256 for the shift. Only for
1211 rotates is modulo 32 used. */
1212/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5
RS		 1213
1214/* XX This is not true, is it? */
1215/* All integers have the same format so truncation is easy. */
1216#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1217
1218/* Calling from registers is a massive pain. */
1219#define NO_FUNCTION_CSE 1
1220
1221/* Chars and shorts should be passed as ints. */
1222#define PROMOTE_PROTOTYPES 1
1223
35d965d5
RS		 1224/* The machine modes of pointers and functions */
1225#define Pmode SImode
1226#define FUNCTION_MODE Pmode
1227
1228/* The structure type of the machine dependent info field of insns
1229 No uses for this yet. */
1230/* #define INSN_MACHINE_INFO struct machine_info */
1231
1232/* The relative costs of various types of constants. Note that cse.c defines
1233 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
ff9940b0
RE		 1234#define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1235 case CONST_INT: \
1236 if (const_ok_for_arm (INTVAL (RTX))) \
1237 return (OUTER_CODE) == SET ? 2 : -1; \
1238 else if (OUTER_CODE == AND \
1239 && const_ok_for_arm (~INTVAL (RTX))) \
1240 return -1; \
1241 else if ((OUTER_CODE == COMPARE \
1242 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1243 && const_ok_for_arm (-INTVAL (RTX))) \
1244 return -1; \
1245 else \
1246 return 5; \
1247 case CONST: \
1248 case LABEL_REF: \
1249 case SYMBOL_REF: \
1250 return 6; \
1251 case CONST_DOUBLE: \
1252 if (const_double_rtx_ok_for_fpu (RTX)) \
1253 return (OUTER_CODE) == SET ? 2 : -1; \
1254 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1255 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1256 return -1; \
1257 return(7);
1258
3967692c
RE		 1259#define ARM_FRAME_RTX(X) \
1260 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1261 || (X) == arg_pointer_rtx)
1262
ff9940b0 1263#define RTX_COSTS(X,CODE,OUTER_CODE) \
3967692c
RE		 1264 default: \
1265 return arm_rtx_costs (X, CODE, OUTER_CODE);
ff9940b0
RE		 1266
1267/* Moves to and from memory are quite expensive */
1268#define MEMORY_MOVE_COST(MODE) 10
1269
3967692c
RE		 1270/* All address computations that can be done are free, but rtx cost returns
1271 the same for practically all of them. So we weight the differnt types
1272 of address here in the order (most pref first):
1273 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1274#define ADDRESS_COST(X) \
1275 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1276 || GET_CODE (X) == SYMBOL_REF) \
1277 ? 0 \
1278 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1279 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1280 ? 10 \
1281 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1282 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1283 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1284 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1285 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1286 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1287 ? 1 : 0)) \
1288 : 4)))))
1289
1290
ff9940b0
RE		 1291
1292/* Try to generate sequences that don't involve branches, we can then use
1293 conditional instructions */
1294#define BRANCH_COST 4
35d965d5 1295\f
ff9940b0
RE		 1296/* Condition code information. */
1297/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1298 return the mode to be used for the comparison.
1299 CCFPEmode should be used with floating inequalites,
1300 CCFPmode should be used with floating equalities.
1301 CC_NOOVmode should be used with SImode integer equalites
1302 CCmode should be used otherwise. */
1303
1304#define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1305
1306#define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1307
1308#define SELECT_CC_MODE(OP,X,Y) \
1309 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1310 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1311 : ((GET_MODE (X) == SImode) \
1312 && ((OP) == EQ || (OP) == NE) \
1313 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1314 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1315 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1316 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
996a5f59 1317 || GET_CODE (X) == LSHIFTRT \
ff9940b0
RE		 1318 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1319 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1320 ? CC_NOOVmode \
1321 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1322
008cf58a
RE		 1323#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1324
ff9940b0
RE		 1325#define STORE_FLAG_VALUE 1
1326
1327/* Define the information needed to generate branch insns. This is
1328 stored from the compare operation. Note that we can't use "rtx" here
1329 since it hasn't been defined! */
1330
1331extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1332extern int arm_compare_fp;
1333
1334/* Define the codes that are matched by predicates in arm.c */
1335#define PREDICATE_CODES \
1336 {"s_register_operand", {SUBREG, REG}}, \
1337 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1338 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1339 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1340 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1341 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1342 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1343 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
3967692c 1344 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
ff9940b0
RE		 1345 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1346 {"load_multiple_operation", {PARALLEL}}, \
1347 {"store_multiple_operation", {PARALLEL}}, \
1348 {"equality_operator", {EQ, NE}}, \
1349 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1350 {"const_shift_operand", {CONST_INT}}, \
1351 {"index_operand", {SUBREG, REG, CONST_INT}}, \
3967692c
RE		 1352 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1353 {"multi_register_push", {PARALLEL}}, \
31e6408a
RE		 1354 {"cc_register", {REG}}, \
1355 {"reversible_cc_register", {REG}},
ff9940b0 1356
35d965d5
RS		 1357\f
1358/* Assembler output control */
1359
ff9940b0
RE		 1360#ifndef ARM_OS_NAME
1361#define ARM_OS_NAME "(generic)"
1362#endif
1363
35d965d5 1364/* The text to go at the start of the assembler file */
4eda77ec
RE		 1365#define ASM_FILE_START(STREAM) \
1366{ \
1367 extern char *version_string; \
1368 fprintf (STREAM,"%c Generated by gcc %s for ARM/%s\n", \
1369 ARM_COMMENT_CHAR, version_string, ARM_OS_NAME); \
1370 fprintf (STREAM,"%srfp\t.req\t%sr9\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1371 fprintf (STREAM,"%ssl\t.req\t%sr10\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1372 fprintf (STREAM,"%sfp\t.req\t%sr11\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1373 fprintf (STREAM,"%sip\t.req\t%sr12\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1374 fprintf (STREAM,"%ssp\t.req\t%sr13\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1375 fprintf (STREAM,"%slr\t.req\t%sr14\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1376 fprintf (STREAM,"%spc\t.req\t%sr15\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
35d965d5
RS		 1377}
1378
1379#define ASM_APP_ON ""
1380#define ASM_APP_OFF ""
1381
1382/* Switch to the text or data segment. */
8cf6b9ca
RS		 1383#define TEXT_SECTION_ASM_OP ".text"
1384#define DATA_SECTION_ASM_OP ".data"
35d965d5 1385
4eda77ec
RE		 1386/* The assembler's names for the registers. */
1387#ifndef REGISTER_NAMES
35d965d5
RS		 1388#define REGISTER_NAMES \
1389{ \
1390 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
4eda77ec 1391 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
ff9940b0
RE		 1392 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1393 "cc", "sfp", "afp" \
35d965d5 1394}
4eda77ec
RE		 1395#endif
1396
1397#ifndef ADDITIONAL_REGISTER_NAMES
1398#define ADDITIONAL_REGISTER_NAMES \
1399{ \
1400 {"a1", 0}, \
1401 {"a2", 1}, \
1402 {"a3", 2}, \
1403 {"a4", 3}, \
1404 {"v1", 4}, \
1405 {"v2", 5}, \
1406 {"v3", 6}, \
1407 {"v4", 7}, \
1408 {"v5", 8}, \
1409 {"v6", 9}, \
1410 {"rfp", 9}, /* Gcc used to call it this */ \
1411 {"sb", 9}, \
1412 {"v7", 10}, \
1413 {"r10", 10}, \
1414 {"r11", 11}, /* fp */ \
1415 {"r12", 12}, /* ip */ \
1416 {"r13", 13}, /* sp */ \
1417 {"r14", 14}, /* lr */ \
1418 {"r15", 15} /* pc */ \
1419}
1420#endif
35d965d5 1421
ff9940b0
RE		 1422/* Arm Assembler barfs on dollars */
1423#define DOLLARS_IN_IDENTIFIERS 0
1424
1425#define NO_DOLLAR_IN_LABEL
1426
35d965d5
RS		 1427/* DBX register number for a given compiler register number */
1428#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1429
ff9940b0
RE		 1430/* Generate DBX debugging information. riscix.h will undefine this because
1431 the native assembler does not support stabs. */
35d965d5
RS		 1432#define DBX_DEBUGGING_INFO 1
1433
1434/* Acorn dbx moans about continuation chars, so don't use any. */
3967692c 1435#ifndef DBX_CONTIN_LENGTH
35d965d5 1436#define DBX_CONTIN_LENGTH 0
3967692c 1437#endif
35d965d5 1438
ff9940b0
RE		 1439/* Output a source filename for the debugger. RISCiX dbx insists that the
1440 ``desc'' field is set to compiler version number >= 315 (sic). */
1441#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1442do { \
1443 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1444 &ltext_label_name[1]); \
1445 text_section (); \
1446 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1447} while (0)
1448
35d965d5
RS		 1449/* Output a label definition. */
1450#define ASM_OUTPUT_LABEL(STREAM,NAME) \
1451 arm_asm_output_label ((STREAM), (NAME))
1452
1453/* Output a function label definition. */
1454#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1455 ASM_OUTPUT_LABEL(STREAM, NAME)
1456
1457/* Output a globalising directive for a label. */
1458#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1459 (fprintf (STREAM, "\t.global\t"), \
1460 assemble_name (STREAM, NAME), \
1461 fputc ('\n',STREAM)) \
1462
1463/* Output a reference to a label. */
1464#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1465 fprintf (STREAM, "_%s", NAME)
1466
1467/* Make an internal label into a string. */
1468#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1469 sprintf (STRING, "*%s%d", PREFIX, NUM)
1470
1471/* Output an internal label definition. */
1472#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1473 do \
1474 { \
1475 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1476 extern int arm_target_label, arm_ccfsm_state; \
26563586 1477 extern rtx arm_target_insn; \
35d965d5 1478 \
ff9940b0
RE		 1479 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1480 && !strcmp (PREFIX, "L")) \
1481 { \
1482 arm_ccfsm_state = 0; \
26563586 1483 arm_target_insn = NULL; \
ff9940b0
RE		 1484 } \
1485 strcpy (s, "*"); \
1486 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1487 arm_asm_output_label (STREAM, s); \
35d965d5
RS		 1488 } while (0)
1489
1490/* Nothing special is done about jump tables */
1491/* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1492/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1493
1494/* Construct a private name. */
1495#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1496 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1497 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1498
1499/* Output a push or a pop instruction (only used when profiling). */
4eda77ec
RE		 1500#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1501 fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1502 reg_names[REGNO])
35d965d5 1503
4eda77ec
RE		 1504#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1505 fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1506 reg_names[REGNO])
35d965d5
RS		 1507
1508/* Output a relative address. Not needed since jump tables are absolute
1509 but we must define it anyway. */
1510#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1511 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1512
1513/* Output an element of a dispatch table. */
1514#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
008cf58a 1515 fprintf (STREAM, "\t.word\tL%d\n", VALUE)
35d965d5 1516
7fc6c9f0
RK		 1517/* Output various types of constants. For real numbers we output hex, with
1518 a comment containing the "human" value, this allows us to pass NaN's which
1519 the riscix assembler doesn't understand (it also makes cross-assembling
1520 less likely to fail). */
1521
ff9940b0 1522#define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
7fc6c9f0
RK		 1523do { char dstr[30]; \
1524 long l[3]; \
ff9940b0
RE		 1525 arm_increase_location (12); \
1526 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
7fc6c9f0 1527 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
ff9940b0 1528 if (sizeof (int) == sizeof (long)) \
4eda77ec
RE		 1529 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t%c long double %s\n", \
1530 l[2], l[1], l[0], ARM_COMMENT_CHAR, dstr); \
ff9940b0 1531 else \
4eda77ec
RE		 1532 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%c long double %s\n",\
1533 l[0], l[1], l[2], ARM_COMMENT_CHAR, dstr); \
ff9940b0
RE		 1534 } while (0)
1535
1536
7fc6c9f0
RK		 1537#define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1538do { char dstr[30]; \
1539 long l[2]; \
1540 arm_increase_location (8); \
1541 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1542 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
1543 if (sizeof (int) == sizeof (long)) \
4eda77ec
RE		 1544 fprintf (STREAM, "\t.long 0x%x, 0x%x\t%c double %s\n", l[0], \
1545 l[1], ARM_COMMENT_CHAR, dstr); \
7fc6c9f0 1546 else \
4eda77ec
RE		 1547 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%c double %s\n", l[0], \
1548 l[1], ARM_COMMENT_CHAR, dstr); \
ff9940b0
RE		 1549 } while (0)
1550
7fc6c9f0
RK		 1551#define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1552do { char dstr[30]; \
1553 long l; \
1554 arm_increase_location (4); \
1555 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1556 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
1557 if (sizeof (int) == sizeof (long)) \
4eda77ec
RE		 1558 fprintf (STREAM, "\t.word 0x%x\t%c float %s\n", l, \
1559 ARM_COMMENT_CHAR, dstr); \
7fc6c9f0 1560 else \
4eda77ec
RE		 1561 fprintf (STREAM, "\t.word 0x%lx\t%c float %s\n", l, \
1562 ARM_COMMENT_CHAR, dstr); \
ff9940b0 1563 } while (0);
35d965d5 1564
7fc6c9f0
RK		 1565#define ASM_OUTPUT_INT(STREAM, EXP) \
1566 (fprintf (STREAM, "\t.word\t"), \
1567 output_addr_const (STREAM, (EXP)), \
1568 arm_increase_location (4), \
35d965d5
RS		 1569 fputc ('\n', STREAM))
1570
1571#define ASM_OUTPUT_SHORT(STREAM, EXP) \
1572 (fprintf (STREAM, "\t.short\t"), \
1573 output_addr_const (STREAM, (EXP)), \
1574 arm_increase_location (2), \
1575 fputc ('\n', STREAM))
1576
1577#define ASM_OUTPUT_CHAR(STREAM, EXP) \
1578 (fprintf (STREAM, "\t.byte\t"), \
1579 output_addr_const (STREAM, (EXP)), \
1580 arm_increase_location (1), \
1581 fputc ('\n', STREAM))
1582
1583#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1584 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1585 arm_increase_location (1))
1586
1587#define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
f70bf59e 1588 output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN))
35d965d5
RS		 1589
1590/* Output a gap. In fact we fill it with nulls. */
1591#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1592 (arm_increase_location (NBYTES), \
1593 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1594
1595/* Align output to a power of two. Horrible /bin/as. */
1596#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1597 do \
1598 { \
1599 register int amount = 1 << (POWER); \
1600 extern int arm_text_location; \
1601 \
1602 if (amount == 2) \
1603 fprintf (STREAM, "\t.even\n"); \
1604 else \
1605 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1606 \
1607 if (in_text_section ()) \
1608 arm_text_location = ((arm_text_location + amount - 1) \
1609 & ~(amount - 1)); \
1610 } while (0)
1611
1612/* Output a common block */
4eda77ec
RE		 1613#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1614 (fprintf (STREAM, "\t.comm\t"), \
1615 assemble_name ((STREAM), (NAME)), \
1616 fprintf(STREAM, ", %d\t%c%d\n", ROUNDED, ARM_COMMENT_CHAR, SIZE))
35d965d5
RS		 1617
1618/* Output a local common block. /bin/as can't do this, so hack a `.space' into
1619 the bss segment. Note that this is *bad* practice. */
1620#define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1621 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1622
35d965d5
RS		 1623/* Output a source line for the debugger. */
1624/* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1625
1626/* Output a #ident directive. */
1627#define ASM_OUTPUT_IDENT(STREAM,STRING) \
1628 fprintf (STREAM,"- - - ident %s\n",STRING)
1629
1630/* The assembler's parentheses characters. */
1631#define ASM_OPEN_PAREN "("
1632#define ASM_CLOSE_PAREN ")"
1633
1634/* Target characters. */
1635#define TARGET_BELL 007
1636#define TARGET_BS 010
1637#define TARGET_TAB 011
1638#define TARGET_NEWLINE 012
1639#define TARGET_VT 013
1640#define TARGET_FF 014
1641#define TARGET_CR 015
1642\f
35d965d5
RS		 1643/* Only perform branch elimination (by making instructions conditional) if
1644 we're optimising. Otherwise it's of no use anyway. */
1645#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1646 if (optimize) \
1647 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1648
7bc7696c
RE		 1649#ifndef ARM_COMMENT_CHAR
1650#define ARM_COMMENT_CHAR '@'
1651#endif
1652
1653/* Default is for register names not to have a prefix. */
1654#ifndef ARM_REG_PREFIX
1655#define ARM_REG_PREFIX ""
1656#endif
1657
1658#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1659 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1660/* Output an operand of an instruction. */
35d965d5 1661#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 1662 arm_print_operand (STREAM, X, CODE)
1663
1664#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1665 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1666 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1667 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1668 ? ((~ (HOST_WIDE_INT) 0) \
1669 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1670 : 0))))
35d965d5
RS		 1671
1672/* Output the address of an operand. */
1673#define PRINT_OPERAND_ADDRESS(STREAM,X) \
1674{ \
1675 int is_minus = GET_CODE (X) == MINUS; \
1676 \
1677 if (GET_CODE (X) == REG) \
4eda77ec
RE		 1678 fprintf (STREAM, "[%s%s, #0]", ARM_REG_PREFIX, \
1679 reg_names[REGNO (X)]); \
35d965d5
RS		 1680 else if (GET_CODE (X) == PLUS || is_minus) \
1681 { \
1682 rtx base = XEXP (X, 0); \
1683 rtx index = XEXP (X, 1); \
1684 char *base_reg_name; \
7bc7696c 1685 HOST_WIDE_INT offset = 0; \
35d965d5
RS		 1686 if (GET_CODE (base) != REG) \
1687 { \
1688 /* Ensure that BASE is a register (one of them must be). */ \
1689 rtx temp = base; \
1690 base = index; \
1691 index = temp; \
1692 } \
1693 base_reg_name = reg_names[REGNO (base)]; \
1694 switch (GET_CODE (index)) \
1695 { \
1696 case CONST_INT: \
1697 offset = INTVAL (index); \
1698 if (is_minus) \
1699 offset = -offset; \
4eda77ec
RE		 1700 fprintf (STREAM, "[%s%s, #%d]", ARM_REG_PREFIX, \
1701 base_reg_name, offset); \
35d965d5
RS		 1702 break; \
1703 \
1704 case REG: \
4eda77ec
RE		 1705 fprintf (STREAM, "[%s%s, %s%s%s]", ARM_REG_PREFIX, \
1706 base_reg_name, is_minus ? "-" : "", \
1707 ARM_REG_PREFIX, reg_names[REGNO (index)] ); \
35d965d5
RS		 1708 break; \
1709 \
1710 case MULT: \
ff9940b0
RE		 1711 case ASHIFTRT: \
1712 case LSHIFTRT: \
1713 case ASHIFT: \
ff9940b0
RE		 1714 case ROTATERT: \
1715 { \
3967692c 1716 fprintf (STREAM, "[%s%s, %s%s%s", ARM_REG_PREFIX, \
4eda77ec 1717 base_reg_name, is_minus ? "-" : "", ARM_REG_PREFIX,\
7bc7696c
RE		 1718 reg_names[REGNO (XEXP (index, 0))]); \
1719 arm_print_operand (STREAM, index, 'S'); \
1720 fputs ("]", STREAM); \
ff9940b0
RE		 1721 break; \
1722 } \
35d965d5
RS		 1723 \
1724 default: \
1725 abort(); \
1726 } \
1727 } \
1728 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1729 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1730 { \
1731 extern int output_memory_reference_mode; \
1732 \
1733 if (GET_CODE (XEXP (X, 0)) != REG) \
1734 abort (); \
1735 \
1736 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
4eda77ec
RE		 1737 fprintf (STREAM, "[%s%s, #%s%d]!", ARM_REG_PREFIX, \
1738 reg_names[REGNO (XEXP (X, 0))], \
35d965d5
RS		 1739 GET_CODE (X) == PRE_DEC ? "-" : "", \
1740 GET_MODE_SIZE (output_memory_reference_mode)); \
1741 else \
4eda77ec
RE		 1742 fprintf (STREAM, "[%s%s], #%s%d", ARM_REG_PREFIX, \
1743 reg_names[REGNO (XEXP (X, 0))], \
35d965d5
RS		 1744 GET_CODE (X) == POST_DEC ? "-" : "", \
1745 GET_MODE_SIZE (output_memory_reference_mode)); \
1746 } \
1747 else output_addr_const(STREAM, X); \
1748}
GNU Compiler Collection
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