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b36ba79f | 1 | /* Output routines for GCC for ARM. |
6bc82793 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
2398fb2a | 3 | Free Software Foundation, Inc. |
cce8749e | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 5 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e | 7 | |
4f448245 | 8 | This file is part of GCC. |
cce8749e | 9 | |
4f448245 NC |
10 | GCC is free software; you can redistribute it and/or modify it |
11 | under the terms of the GNU General Public License as published | |
12 | by the Free Software Foundation; either version 2, or (at your | |
13 | option) any later version. | |
cce8749e | 14 | |
4f448245 NC |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
cce8749e | 19 | |
4f448245 NC |
20 | You should have received a copy of the GNU General Public License |
21 | along with GCC; see the file COPYING. If not, write to | |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
23 | Boston, MA 02111-1307, USA. */ | |
ff9940b0 | 24 | |
56636818 | 25 | #include "config.h" |
43cffd11 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
cce8749e | 29 | #include "rtl.h" |
d5b7b3ae | 30 | #include "tree.h" |
c7319d87 | 31 | #include "obstack.h" |
cce8749e CH |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
34 | #include "real.h" | |
35 | #include "insn-config.h" | |
36 | #include "conditions.h" | |
cce8749e CH |
37 | #include "output.h" |
38 | #include "insn-attr.h" | |
39 | #include "flags.h" | |
af48348a | 40 | #include "reload.h" |
49ad7cfa | 41 | #include "function.h" |
bee06f3d | 42 | #include "expr.h" |
e78d8e51 | 43 | #include "optabs.h" |
ad076f4e | 44 | #include "toplev.h" |
aec3cfba | 45 | #include "recog.h" |
92a432f4 | 46 | #include "ggc.h" |
d5b7b3ae | 47 | #include "except.h" |
8b97c5f8 | 48 | #include "c-pragma.h" |
7b8b8ade | 49 | #include "integrate.h" |
c27ba912 | 50 | #include "tm_p.h" |
672a6f42 NB |
51 | #include "target.h" |
52 | #include "target-def.h" | |
cce8749e | 53 | |
d5b7b3ae RE |
54 | /* Forward definitions of types. */ |
55 | typedef struct minipool_node Mnode; | |
56 | typedef struct minipool_fixup Mfix; | |
57 | ||
1d6e90ac NC |
58 | const struct attribute_spec arm_attribute_table[]; |
59 | ||
d5b7b3ae | 60 | /* Forward function declarations. */ |
e32bac5b RE |
61 | static void arm_add_gc_roots (void); |
62 | static int arm_gen_constant (enum rtx_code, enum machine_mode, HOST_WIDE_INT, | |
63 | rtx, rtx, int, int); | |
64 | static unsigned bit_count (unsigned long); | |
65 | static int arm_address_register_rtx_p (rtx, int); | |
66 | static int arm_legitimate_index_p (enum machine_mode, rtx, int); | |
67 | static int thumb_base_register_rtx_p (rtx, enum machine_mode, int); | |
68 | inline static int thumb_index_register_rtx_p (rtx, int); | |
69 | static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); | |
e32bac5b RE |
70 | static rtx emit_multi_reg_push (int); |
71 | static rtx emit_sfm (int, int); | |
301d03af | 72 | #ifndef AOF_ASSEMBLER |
e32bac5b | 73 | static bool arm_assemble_integer (rtx, unsigned int, int); |
301d03af | 74 | #endif |
e32bac5b RE |
75 | static const char *fp_const_from_val (REAL_VALUE_TYPE *); |
76 | static arm_cc get_arm_condition_code (rtx); | |
77 | static void init_fpa_table (void); | |
78 | static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); | |
79 | static rtx is_jump_table (rtx); | |
80 | static const char *output_multi_immediate (rtx *, const char *, const char *, | |
81 | int, HOST_WIDE_INT); | |
82 | static void print_multi_reg (FILE *, const char *, int, int); | |
83 | static const char *shift_op (rtx, HOST_WIDE_INT *); | |
84 | static struct machine_function *arm_init_machine_status (void); | |
85 | static int number_of_first_bit_set (int); | |
86 | static void replace_symbols_in_block (tree, rtx, rtx); | |
87 | static void thumb_exit (FILE *, int, rtx); | |
88 | static void thumb_pushpop (FILE *, int, int); | |
89 | static const char *thumb_condition_code (rtx, int); | |
90 | static rtx is_jump_table (rtx); | |
91 | static HOST_WIDE_INT get_jump_table_size (rtx); | |
92 | static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
93 | static Mnode *add_minipool_forward_ref (Mfix *); | |
94 | static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
95 | static Mnode *add_minipool_backward_ref (Mfix *); | |
96 | static void assign_minipool_offsets (Mfix *); | |
97 | static void arm_print_value (FILE *, rtx); | |
98 | static void dump_minipool (rtx); | |
99 | static int arm_barrier_cost (rtx); | |
100 | static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); | |
101 | static void push_minipool_barrier (rtx, HOST_WIDE_INT); | |
102 | static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, | |
103 | rtx); | |
104 | static void arm_reorg (void); | |
105 | static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); | |
106 | static int current_file_function_operand (rtx); | |
107 | static unsigned long arm_compute_save_reg0_reg12_mask (void); | |
108 | static unsigned long arm_compute_save_reg_mask (void); | |
109 | static unsigned long arm_isr_value (tree); | |
110 | static unsigned long arm_compute_func_type (void); | |
111 | static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); | |
112 | static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); | |
113 | static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
114 | static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); | |
115 | static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT); | |
116 | static int arm_comp_type_attributes (tree, tree); | |
117 | static void arm_set_default_type_attributes (tree); | |
118 | static int arm_adjust_cost (rtx, rtx, rtx, int); | |
119 | static int arm_use_dfa_pipeline_interface (void); | |
120 | static int count_insns_for_constant (HOST_WIDE_INT, int); | |
121 | static int arm_get_strip_length (int); | |
122 | static bool arm_function_ok_for_sibcall (tree, tree); | |
123 | static void arm_internal_label (FILE *, const char *, unsigned long); | |
124 | static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, | |
125 | tree); | |
126 | static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code); | |
127 | static bool arm_rtx_costs (rtx, int, int, int *); | |
128 | static int arm_address_cost (rtx); | |
129 | static bool arm_memory_load_p (rtx); | |
130 | static bool arm_cirrus_insn_p (rtx); | |
131 | static void cirrus_reorg (rtx); | |
5a9335ef NC |
132 | static void arm_init_builtins (void); |
133 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
134 | static void arm_init_iwmmxt_builtins (void); | |
135 | static rtx safe_vector_operand (rtx, enum machine_mode); | |
136 | static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); | |
137 | static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); | |
138 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
139 | ||
ebe413e5 | 140 | #ifdef OBJECT_FORMAT_ELF |
e32bac5b | 141 | static void arm_elf_asm_named_section (const char *, unsigned int); |
ebe413e5 | 142 | #endif |
fb49053f | 143 | #ifndef ARM_PE |
e32bac5b | 144 | static void arm_encode_section_info (tree, rtx, int); |
fb49053f | 145 | #endif |
5eb99654 | 146 | #ifdef AOF_ASSEMBLER |
e32bac5b RE |
147 | static void aof_globalize_label (FILE *, const char *); |
148 | static void aof_dump_imports (FILE *); | |
149 | static void aof_dump_pic_table (FILE *); | |
1bc7c5b6 | 150 | static void aof_file_start (void); |
e32bac5b | 151 | static void aof_file_end (void); |
5eb99654 | 152 | #endif |
c237e94a | 153 | |
672a6f42 NB |
154 | \f |
155 | /* Initialize the GCC target structure. */ | |
156 | #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES | |
1d6e90ac | 157 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
672a6f42 NB |
158 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes |
159 | #endif | |
f3bb6135 | 160 | |
1d6e90ac | 161 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 162 | #define TARGET_ATTRIBUTE_TABLE arm_attribute_table |
672a6f42 | 163 | |
301d03af | 164 | #ifdef AOF_ASSEMBLER |
1d6e90ac | 165 | #undef TARGET_ASM_BYTE_OP |
301d03af | 166 | #define TARGET_ASM_BYTE_OP "\tDCB\t" |
1d6e90ac | 167 | #undef TARGET_ASM_ALIGNED_HI_OP |
301d03af | 168 | #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t" |
1d6e90ac | 169 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 170 | #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t" |
5eb99654 KG |
171 | #undef TARGET_ASM_GLOBALIZE_LABEL |
172 | #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label | |
1bc7c5b6 ZW |
173 | #undef TARGET_ASM_FILE_START |
174 | #define TARGET_ASM_FILE_START aof_file_start | |
a5fe455b ZW |
175 | #undef TARGET_ASM_FILE_END |
176 | #define TARGET_ASM_FILE_END aof_file_end | |
301d03af | 177 | #else |
1d6e90ac | 178 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 179 | #define TARGET_ASM_ALIGNED_SI_OP NULL |
1d6e90ac | 180 | #undef TARGET_ASM_INTEGER |
301d03af RS |
181 | #define TARGET_ASM_INTEGER arm_assemble_integer |
182 | #endif | |
183 | ||
1d6e90ac | 184 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 NB |
185 | #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue |
186 | ||
1d6e90ac | 187 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
188 | #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue |
189 | ||
1d6e90ac | 190 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
8d8e52be JM |
191 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes |
192 | ||
1d6e90ac | 193 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
8d8e52be JM |
194 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes |
195 | ||
1d6e90ac | 196 | #undef TARGET_SCHED_ADJUST_COST |
c237e94a ZW |
197 | #define TARGET_SCHED_ADJUST_COST arm_adjust_cost |
198 | ||
103fc15d BE |
199 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
200 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface | |
201 | ||
fb49053f RH |
202 | #undef TARGET_ENCODE_SECTION_INFO |
203 | #ifdef ARM_PE | |
204 | #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info | |
205 | #else | |
206 | #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info | |
207 | #endif | |
208 | ||
5a9335ef | 209 | #undef TARGET_STRIP_NAME_ENCODING |
772c5265 RH |
210 | #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding |
211 | ||
5a9335ef | 212 | #undef TARGET_ASM_INTERNAL_LABEL |
4977bab6 ZW |
213 | #define TARGET_ASM_INTERNAL_LABEL arm_internal_label |
214 | ||
5a9335ef | 215 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
4977bab6 ZW |
216 | #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall |
217 | ||
5a9335ef | 218 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
c590b625 | 219 | #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk |
5a9335ef | 220 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3961e8fe | 221 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
c590b625 | 222 | |
5a9335ef | 223 | #undef TARGET_RTX_COSTS |
3c50106f | 224 | #define TARGET_RTX_COSTS arm_rtx_costs |
5a9335ef | 225 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 226 | #define TARGET_ADDRESS_COST arm_address_cost |
3c50106f | 227 | |
5a9335ef | 228 | #undef TARGET_MACHINE_DEPENDENT_REORG |
18dbd950 RS |
229 | #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg |
230 | ||
5a9335ef NC |
231 | #undef TARGET_INIT_BUILTINS |
232 | #define TARGET_INIT_BUILTINS arm_init_builtins | |
233 | #undef TARGET_EXPAND_BUILTIN | |
234 | #define TARGET_EXPAND_BUILTIN arm_expand_builtin | |
235 | ||
f6897b10 | 236 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 237 | \f |
c7319d87 RE |
238 | /* Obstack for minipool constant handling. */ |
239 | static struct obstack minipool_obstack; | |
1d6e90ac | 240 | static char * minipool_startobj; |
c7319d87 | 241 | |
1d6e90ac NC |
242 | /* The maximum number of insns skipped which |
243 | will be conditionalised if possible. */ | |
c27ba912 DM |
244 | static int max_insns_skipped = 5; |
245 | ||
246 | extern FILE * asm_out_file; | |
247 | ||
6354dc9b | 248 | /* True if we are currently building a constant table. */ |
13bd191d PB |
249 | int making_const_table; |
250 | ||
60d0536b | 251 | /* Define the information needed to generate branch insns. This is |
6354dc9b | 252 | stored from the compare operation. */ |
ff9940b0 | 253 | rtx arm_compare_op0, arm_compare_op1; |
ff9940b0 | 254 | |
6354dc9b | 255 | /* What type of floating point are we tuning for? */ |
29ad9694 | 256 | enum fputype arm_fpu_tune; |
bee06f3d | 257 | |
6354dc9b | 258 | /* What type of floating point instructions are available? */ |
29ad9694 | 259 | enum fputype arm_fpu_arch; |
b111229a | 260 | |
6354dc9b | 261 | /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */ |
2b835d68 RE |
262 | enum prog_mode_type arm_prgmode; |
263 | ||
6354dc9b | 264 | /* Set by the -mfp=... option. */ |
f9cc092a | 265 | const char * target_fp_name = NULL; |
2b835d68 | 266 | |
b355a481 | 267 | /* Used to parse -mstructure_size_boundary command line option. */ |
f9cc092a | 268 | const char * structure_size_string = NULL; |
723ae7c1 | 269 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 270 | |
aec3cfba | 271 | /* Bit values used to identify processor capabilities. */ |
62b10bbc NC |
272 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
273 | #define FL_FAST_MULT (1 << 1) /* Fast multiply */ | |
274 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ | |
275 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
276 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
277 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
278 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
279 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
280 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
6bc82793 | 281 | #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ |
d19fb8e3 | 282 | #define FL_XSCALE (1 << 10) /* XScale */ |
9b6b54e2 | 283 | #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ |
5a9335ef | 284 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ |
aec3cfba | 285 | |
1d6e90ac NC |
286 | /* The bits in this mask specify which |
287 | instructions we are allowed to generate. */ | |
0977774b | 288 | static unsigned long insn_flags = 0; |
d5b7b3ae | 289 | |
aec3cfba NC |
290 | /* The bits in this mask specify which instruction scheduling options should |
291 | be used. Note - there is an overlap with the FL_FAST_MULT. For some | |
292 | hardware we want to be able to generate the multiply instructions, but to | |
293 | tune as if they were not present in the architecture. */ | |
0977774b | 294 | static unsigned long tune_flags = 0; |
aec3cfba NC |
295 | |
296 | /* The following are used in the arm.md file as equivalents to bits | |
297 | in the above two flag variables. */ | |
298 | ||
2b835d68 RE |
299 | /* Nonzero if this is an "M" variant of the processor. */ |
300 | int arm_fast_multiply = 0; | |
301 | ||
6354dc9b | 302 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
303 | int arm_arch4 = 0; |
304 | ||
6354dc9b | 305 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
306 | int arm_arch5 = 0; |
307 | ||
b15bca31 RE |
308 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
309 | int arm_arch5e = 0; | |
310 | ||
aec3cfba | 311 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
312 | int arm_ld_sched = 0; |
313 | ||
314 | /* Nonzero if this chip is a StrongARM. */ | |
315 | int arm_is_strong = 0; | |
316 | ||
5a9335ef NC |
317 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ |
318 | int arm_arch_iwmmxt = 0; | |
319 | ||
d19fb8e3 | 320 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
321 | int arm_arch_xscale = 0; |
322 | ||
323 | /* Nonzero if tuning for XScale */ | |
324 | int arm_tune_xscale = 0; | |
d19fb8e3 | 325 | |
3569057d | 326 | /* Nonzero if this chip is an ARM6 or an ARM7. */ |
f5a1b0d2 | 327 | int arm_is_6_or_7 = 0; |
b111229a | 328 | |
9b6b54e2 NC |
329 | /* Nonzero if this chip is a Cirrus/DSP. */ |
330 | int arm_is_cirrus = 0; | |
331 | ||
0616531f RE |
332 | /* Nonzero if generating Thumb instructions. */ |
333 | int thumb_code = 0; | |
334 | ||
cce8749e CH |
335 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we |
336 | must report the mode of the memory reference from PRINT_OPERAND to | |
337 | PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 338 | enum machine_mode output_memory_reference_mode; |
cce8749e | 339 | |
32de079a | 340 | /* The register number to be used for the PIC offset register. */ |
ed0e6530 | 341 | const char * arm_pic_register_string = NULL; |
5b43fed1 | 342 | int arm_pic_register = INVALID_REGNUM; |
32de079a | 343 | |
ff9940b0 | 344 | /* Set to 1 when a return insn is output, this means that the epilogue |
6354dc9b | 345 | is not needed. */ |
d5b7b3ae | 346 | int return_used_this_function; |
ff9940b0 | 347 | |
aec3cfba NC |
348 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
349 | the next function. */ | |
4b632bf1 RE |
350 | static int after_arm_reorg = 0; |
351 | ||
aec3cfba | 352 | /* The maximum number of insns to be used when loading a constant. */ |
2b835d68 RE |
353 | static int arm_constant_limit = 3; |
354 | ||
cce8749e CH |
355 | /* For an explanation of these variables, see final_prescan_insn below. */ |
356 | int arm_ccfsm_state; | |
84ed5e79 | 357 | enum arm_cond_code arm_current_cc; |
cce8749e CH |
358 | rtx arm_target_insn; |
359 | int arm_target_label; | |
9997d19d RE |
360 | |
361 | /* The condition codes of the ARM, and the inverse function. */ | |
1d6e90ac | 362 | static const char * const arm_condition_codes[] = |
9997d19d RE |
363 | { |
364 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
365 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
366 | }; | |
367 | ||
f5a1b0d2 | 368 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
2b835d68 | 369 | \f |
6354dc9b | 370 | /* Initialization code. */ |
2b835d68 | 371 | |
2b835d68 RE |
372 | struct processors |
373 | { | |
8b60264b | 374 | const char *const name; |
0977774b | 375 | const unsigned long flags; |
2b835d68 RE |
376 | }; |
377 | ||
378 | /* Not all of these give usefully different compilation alternatives, | |
379 | but there is no simple way of generalizing them. */ | |
8b60264b | 380 | static const struct processors all_cores[] = |
f5a1b0d2 NC |
381 | { |
382 | /* ARM Cores */ | |
383 | ||
384 | {"arm2", FL_CO_PROC | FL_MODE26 }, | |
385 | {"arm250", FL_CO_PROC | FL_MODE26 }, | |
386 | {"arm3", FL_CO_PROC | FL_MODE26 }, | |
387 | {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
388 | {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
389 | {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
390 | {"arm610", FL_MODE26 | FL_MODE32 }, | |
391 | {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
949d79eb RE |
392 | {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, |
393 | /* arm7m doesn't exist on its own, but only with D, (and I), but | |
d5b7b3ae | 394 | those don't alter the code, so arm7m is sometimes used. */ |
949d79eb RE |
395 | {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, |
396 | {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
397 | {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, | |
398 | {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
f5a1b0d2 NC |
399 | {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, |
400 | {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
401 | {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
402 | {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
403 | {"arm710", FL_MODE26 | FL_MODE32 }, | |
eab4abeb | 404 | {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB }, |
a120a3bd | 405 | {"arm720", FL_MODE26 | FL_MODE32 }, |
eab4abeb NC |
406 | {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB }, |
407 | {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB }, | |
f5a1b0d2 NC |
408 | {"arm710c", FL_MODE26 | FL_MODE32 }, |
409 | {"arm7100", FL_MODE26 | FL_MODE32 }, | |
410 | {"arm7500", FL_MODE26 | FL_MODE32 }, | |
3b684012 | 411 | /* Doesn't have an external co-proc, but does have embedded fpa. */ |
949d79eb | 412 | {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, |
f5a1b0d2 NC |
413 | {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, |
414 | {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, | |
415 | {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, | |
416 | {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, | |
6cf32035 NC |
417 | {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, |
418 | {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, | |
eab4abeb | 419 | {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, |
f5a1b0d2 | 420 | {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, |
eab4abeb | 421 | {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, |
9b6b54e2 | 422 | {"ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS }, |
f5a1b0d2 NC |
423 | {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, |
424 | {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, | |
425 | {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, | |
eab4abeb NC |
426 | {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, |
427 | {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, | |
428 | {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, | |
429 | {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE }, | |
5a9335ef | 430 | {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT }, |
e26053d1 | 431 | |
f5a1b0d2 NC |
432 | {NULL, 0} |
433 | }; | |
434 | ||
8b60264b | 435 | static const struct processors all_architectures[] = |
2b835d68 | 436 | { |
f5a1b0d2 NC |
437 | /* ARM Architectures */ |
438 | ||
62b10bbc NC |
439 | { "armv2", FL_CO_PROC | FL_MODE26 }, |
440 | { "armv2a", FL_CO_PROC | FL_MODE26 }, | |
441 | { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
442 | { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, | |
949d79eb | 443 | { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 }, |
b111229a RE |
444 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
445 | implementations that support it, so we will leave it out for now. */ | |
62b10bbc NC |
446 | { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, |
447 | { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, | |
d19fb8e3 NC |
448 | { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, |
449 | { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, | |
9b6b54e2 | 450 | { "ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS }, |
5a9335ef | 451 | {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT }, |
62b10bbc | 452 | { NULL, 0 } |
f5a1b0d2 NC |
453 | }; |
454 | ||
455 | /* This is a magic stucture. The 'string' field is magically filled in | |
456 | with a pointer to the value specified by the user on the command line | |
457 | assuming that the user has specified such a value. */ | |
458 | ||
459 | struct arm_cpu_select arm_select[] = | |
460 | { | |
461 | /* string name processors */ | |
462 | { NULL, "-mcpu=", all_cores }, | |
463 | { NULL, "-march=", all_architectures }, | |
464 | { NULL, "-mtune=", all_cores } | |
2b835d68 RE |
465 | }; |
466 | ||
0977774b JT |
467 | /* Return the number of bits set in VALUE. */ |
468 | static unsigned | |
e32bac5b | 469 | bit_count (unsigned long value) |
aec3cfba | 470 | { |
d5b7b3ae | 471 | unsigned long count = 0; |
aec3cfba NC |
472 | |
473 | while (value) | |
474 | { | |
0977774b JT |
475 | count++; |
476 | value &= value - 1; /* Clear the least-significant set bit. */ | |
aec3cfba NC |
477 | } |
478 | ||
479 | return count; | |
480 | } | |
481 | ||
2b835d68 RE |
482 | /* Fix up any incompatible options that the user has specified. |
483 | This has now turned into a maze. */ | |
484 | void | |
e32bac5b | 485 | arm_override_options (void) |
2b835d68 | 486 | { |
ed4c4348 | 487 | unsigned i; |
f5a1b0d2 NC |
488 | |
489 | /* Set up the flags based on the cpu/architecture selected by the user. */ | |
b6a1cbae | 490 | for (i = ARRAY_SIZE (arm_select); i--;) |
bd9c7e23 | 491 | { |
f5a1b0d2 NC |
492 | struct arm_cpu_select * ptr = arm_select + i; |
493 | ||
494 | if (ptr->string != NULL && ptr->string[0] != '\0') | |
bd9c7e23 | 495 | { |
13bd191d | 496 | const struct processors * sel; |
bd9c7e23 | 497 | |
5895f793 | 498 | for (sel = ptr->processors; sel->name != NULL; sel++) |
f5a1b0d2 | 499 | if (streq (ptr->string, sel->name)) |
bd9c7e23 | 500 | { |
aec3cfba NC |
501 | if (i == 2) |
502 | tune_flags = sel->flags; | |
503 | else | |
b111229a | 504 | { |
aec3cfba NC |
505 | /* If we have been given an architecture and a processor |
506 | make sure that they are compatible. We only generate | |
507 | a warning though, and we prefer the CPU over the | |
6354dc9b | 508 | architecture. */ |
aec3cfba | 509 | if (insn_flags != 0 && (insn_flags ^ sel->flags)) |
6cf32035 | 510 | warning ("switch -mcpu=%s conflicts with -march= switch", |
aec3cfba NC |
511 | ptr->string); |
512 | ||
513 | insn_flags = sel->flags; | |
b111229a | 514 | } |
f5a1b0d2 | 515 | |
bd9c7e23 RE |
516 | break; |
517 | } | |
518 | ||
519 | if (sel->name == NULL) | |
520 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
521 | } | |
522 | } | |
aec3cfba | 523 | |
f5a1b0d2 | 524 | /* If the user did not specify a processor, choose one for them. */ |
aec3cfba | 525 | if (insn_flags == 0) |
f5a1b0d2 | 526 | { |
8b60264b | 527 | const struct processors * sel; |
aec3cfba | 528 | unsigned int sought; |
8b60264b | 529 | static const struct cpu_default |
aec3cfba | 530 | { |
8b60264b KG |
531 | const int cpu; |
532 | const char *const name; | |
aec3cfba NC |
533 | } |
534 | cpu_defaults[] = | |
535 | { | |
536 | { TARGET_CPU_arm2, "arm2" }, | |
537 | { TARGET_CPU_arm6, "arm6" }, | |
538 | { TARGET_CPU_arm610, "arm610" }, | |
2aa0c933 | 539 | { TARGET_CPU_arm710, "arm710" }, |
aec3cfba NC |
540 | { TARGET_CPU_arm7m, "arm7m" }, |
541 | { TARGET_CPU_arm7500fe, "arm7500fe" }, | |
542 | { TARGET_CPU_arm7tdmi, "arm7tdmi" }, | |
543 | { TARGET_CPU_arm8, "arm8" }, | |
544 | { TARGET_CPU_arm810, "arm810" }, | |
545 | { TARGET_CPU_arm9, "arm9" }, | |
546 | { TARGET_CPU_strongarm, "strongarm" }, | |
d19fb8e3 | 547 | { TARGET_CPU_xscale, "xscale" }, |
9b6b54e2 | 548 | { TARGET_CPU_ep9312, "ep9312" }, |
5a9335ef | 549 | { TARGET_CPU_iwmmxt, "iwmmxt" }, |
aec3cfba NC |
550 | { TARGET_CPU_generic, "arm" }, |
551 | { 0, 0 } | |
552 | }; | |
8b60264b | 553 | const struct cpu_default * def; |
aec3cfba NC |
554 | |
555 | /* Find the default. */ | |
5895f793 | 556 | for (def = cpu_defaults; def->name; def++) |
aec3cfba NC |
557 | if (def->cpu == TARGET_CPU_DEFAULT) |
558 | break; | |
559 | ||
560 | /* Make sure we found the default CPU. */ | |
561 | if (def->name == NULL) | |
562 | abort (); | |
563 | ||
564 | /* Find the default CPU's flags. */ | |
5895f793 | 565 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
566 | if (streq (def->name, sel->name)) |
567 | break; | |
568 | ||
569 | if (sel->name == NULL) | |
570 | abort (); | |
571 | ||
572 | insn_flags = sel->flags; | |
573 | ||
574 | /* Now check to see if the user has specified some command line | |
575 | switch that require certain abilities from the cpu. */ | |
576 | sought = 0; | |
f5a1b0d2 | 577 | |
d5b7b3ae | 578 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 579 | { |
aec3cfba NC |
580 | sought |= (FL_THUMB | FL_MODE32); |
581 | ||
582 | /* Force apcs-32 to be used for interworking. */ | |
f5a1b0d2 | 583 | target_flags |= ARM_FLAG_APCS_32; |
aec3cfba | 584 | |
d5b7b3ae | 585 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
586 | interworking. Therefore we force FL_MODE26 to be removed |
587 | from insn_flags here (if it was set), so that the search | |
588 | below will always be able to find a compatible processor. */ | |
5895f793 | 589 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 590 | } |
5895f793 | 591 | else if (!TARGET_APCS_32) |
f5a1b0d2 | 592 | sought |= FL_MODE26; |
d5b7b3ae | 593 | |
aec3cfba | 594 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 595 | { |
aec3cfba NC |
596 | /* Try to locate a CPU type that supports all of the abilities |
597 | of the default CPU, plus the extra abilities requested by | |
598 | the user. */ | |
5895f793 | 599 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 600 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
601 | break; |
602 | ||
603 | if (sel->name == NULL) | |
aec3cfba | 604 | { |
0977774b | 605 | unsigned current_bit_count = 0; |
8b60264b | 606 | const struct processors * best_fit = NULL; |
aec3cfba NC |
607 | |
608 | /* Ideally we would like to issue an error message here | |
609 | saying that it was not possible to find a CPU compatible | |
610 | with the default CPU, but which also supports the command | |
611 | line options specified by the programmer, and so they | |
612 | ought to use the -mcpu=<name> command line option to | |
613 | override the default CPU type. | |
614 | ||
615 | Unfortunately this does not work with multilibing. We | |
616 | need to be able to support multilibs for -mapcs-26 and for | |
617 | -mthumb-interwork and there is no CPU that can support both | |
618 | options. Instead if we cannot find a cpu that has both the | |
619 | characteristics of the default cpu and the given command line | |
620 | options we scan the array again looking for a best match. */ | |
5895f793 | 621 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
622 | if ((sel->flags & sought) == sought) |
623 | { | |
0977774b | 624 | unsigned count; |
aec3cfba NC |
625 | |
626 | count = bit_count (sel->flags & insn_flags); | |
627 | ||
628 | if (count >= current_bit_count) | |
629 | { | |
630 | best_fit = sel; | |
631 | current_bit_count = count; | |
632 | } | |
633 | } | |
f5a1b0d2 | 634 | |
aec3cfba NC |
635 | if (best_fit == NULL) |
636 | abort (); | |
637 | else | |
638 | sel = best_fit; | |
639 | } | |
640 | ||
641 | insn_flags = sel->flags; | |
f5a1b0d2 NC |
642 | } |
643 | } | |
aec3cfba NC |
644 | |
645 | /* If tuning has not been specified, tune for whichever processor or | |
646 | architecture has been selected. */ | |
647 | if (tune_flags == 0) | |
648 | tune_flags = insn_flags; | |
e26053d1 | 649 | |
f5a1b0d2 NC |
650 | /* Make sure that the processor choice does not conflict with any of the |
651 | other command line choices. */ | |
aec3cfba | 652 | if (TARGET_APCS_32 && !(insn_flags & FL_MODE32)) |
f5a1b0d2 | 653 | { |
aec3cfba NC |
654 | /* If APCS-32 was not the default then it must have been set by the |
655 | user, so issue a warning message. If the user has specified | |
656 | "-mapcs-32 -mcpu=arm2" then we loose here. */ | |
657 | if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0) | |
658 | warning ("target CPU does not support APCS-32" ); | |
5895f793 | 659 | target_flags &= ~ARM_FLAG_APCS_32; |
f5a1b0d2 | 660 | } |
5895f793 | 661 | else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26)) |
f5a1b0d2 NC |
662 | { |
663 | warning ("target CPU does not support APCS-26" ); | |
664 | target_flags |= ARM_FLAG_APCS_32; | |
665 | } | |
666 | ||
6cfc7210 | 667 | if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) |
f5a1b0d2 NC |
668 | { |
669 | warning ("target CPU does not support interworking" ); | |
6cfc7210 | 670 | target_flags &= ~ARM_FLAG_INTERWORK; |
f5a1b0d2 NC |
671 | } |
672 | ||
d5b7b3ae RE |
673 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
674 | { | |
c725bd79 | 675 | warning ("target CPU does not support THUMB instructions"); |
d5b7b3ae RE |
676 | target_flags &= ~ARM_FLAG_THUMB; |
677 | } | |
678 | ||
679 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
680 | { | |
c725bd79 | 681 | /* warning ("ignoring -mapcs-frame because -mthumb was used"); */ |
d5b7b3ae RE |
682 | target_flags &= ~ARM_FLAG_APCS_FRAME; |
683 | } | |
d19fb8e3 | 684 | |
d5b7b3ae RE |
685 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
686 | from here where no function is being compiled currently. */ | |
687 | if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE)) | |
688 | && TARGET_ARM) | |
c725bd79 | 689 | warning ("enabling backtrace support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
690 | |
691 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
c725bd79 | 692 | warning ("enabling callee interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
693 | |
694 | if (TARGET_ARM && TARGET_CALLER_INTERWORKING) | |
c725bd79 | 695 | warning ("enabling caller interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae | 696 | |
f5a1b0d2 | 697 | /* If interworking is enabled then APCS-32 must be selected as well. */ |
6cfc7210 | 698 | if (TARGET_INTERWORK) |
f5a1b0d2 | 699 | { |
5895f793 | 700 | if (!TARGET_APCS_32) |
f5a1b0d2 NC |
701 | warning ("interworking forces APCS-32 to be used" ); |
702 | target_flags |= ARM_FLAG_APCS_32; | |
703 | } | |
704 | ||
5895f793 | 705 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 NC |
706 | { |
707 | warning ("-mapcs-stack-check incompatible with -mno-apcs-frame"); | |
708 | target_flags |= ARM_FLAG_APCS_FRAME; | |
709 | } | |
aec3cfba | 710 | |
2b835d68 RE |
711 | if (TARGET_POKE_FUNCTION_NAME) |
712 | target_flags |= ARM_FLAG_APCS_FRAME; | |
aec3cfba | 713 | |
2b835d68 | 714 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 715 | error ("-fpic and -mapcs-reent are incompatible"); |
aec3cfba | 716 | |
2b835d68 | 717 | if (TARGET_APCS_REENT) |
f5a1b0d2 | 718 | warning ("APCS reentrant code not supported. Ignored"); |
aec3cfba | 719 | |
d5b7b3ae RE |
720 | /* If this target is normally configured to use APCS frames, warn if they |
721 | are turned off and debugging is turned on. */ | |
722 | if (TARGET_ARM | |
723 | && write_symbols != NO_DEBUG | |
5895f793 | 724 | && !TARGET_APCS_FRAME |
d5b7b3ae RE |
725 | && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME)) |
726 | warning ("-g with -mno-apcs-frame may not give sensible debugging"); | |
6cfc7210 | 727 | |
32de079a RE |
728 | /* If stack checking is disabled, we can use r10 as the PIC register, |
729 | which keeps r9 available. */ | |
5b43fed1 RH |
730 | if (flag_pic) |
731 | arm_pic_register = TARGET_APCS_STACK ? 9 : 10; | |
aec3cfba | 732 | |
2b835d68 | 733 | if (TARGET_APCS_FLOAT) |
c725bd79 | 734 | warning ("passing floating point arguments in fp regs not yet supported"); |
f5a1b0d2 | 735 | |
4912a07c | 736 | /* Initialize boolean versions of the flags, for use in the arm.md file. */ |
2ca12935 JL |
737 | arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0; |
738 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
739 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; | |
b15bca31 | 740 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; |
4b3c2e48 | 741 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; |
6f7ebcbb | 742 | |
2ca12935 JL |
743 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; |
744 | arm_is_strong = (tune_flags & FL_STRONG) != 0; | |
0616531f | 745 | thumb_code = (TARGET_ARM == 0); |
d5b7b3ae RE |
746 | arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32)) |
747 | && !(tune_flags & FL_ARCH4))) != 0; | |
4b3c2e48 | 748 | arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; |
9b6b54e2 | 749 | arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0; |
5a9335ef NC |
750 | arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; |
751 | ||
752 | if (TARGET_IWMMXT && (! TARGET_ATPCS)) | |
753 | target_flags |= ARM_FLAG_ATPCS; | |
6f7ebcbb | 754 | |
9b6b54e2 NC |
755 | if (arm_is_cirrus) |
756 | { | |
29ad9694 | 757 | arm_fpu_tune = FPUTYPE_MAVERICK; |
9b6b54e2 NC |
758 | |
759 | /* Ignore -mhard-float if -mcpu=ep9312. */ | |
760 | if (TARGET_HARD_FLOAT) | |
761 | target_flags ^= ARM_FLAG_SOFT_FLOAT; | |
762 | } | |
763 | else | |
764 | /* Default value for floating point code... if no co-processor | |
765 | bus, then schedule for emulated floating point. Otherwise, | |
766 | assume the user has an FPA. | |
767 | Note: this does not prevent use of floating point instructions, | |
768 | -msoft-float does that. */ | |
29ad9694 | 769 | arm_fpu_tune = (tune_flags & FL_CO_PROC) ? FPUTYPE_FPA : FPUTYPE_FPA_EMU3; |
f5a1b0d2 | 770 | |
b111229a | 771 | if (target_fp_name) |
2b835d68 | 772 | { |
f5a1b0d2 | 773 | if (streq (target_fp_name, "2")) |
29ad9694 | 774 | arm_fpu_arch = FPUTYPE_FPA_EMU2; |
f5a1b0d2 | 775 | else if (streq (target_fp_name, "3")) |
29ad9694 | 776 | arm_fpu_arch = FPUTYPE_FPA_EMU3; |
2b835d68 | 777 | else |
c725bd79 | 778 | error ("invalid floating point emulation option: -mfpe-%s", |
b111229a | 779 | target_fp_name); |
2b835d68 | 780 | } |
b111229a | 781 | else |
29ad9694 | 782 | arm_fpu_arch = FPUTYPE_DEFAULT; |
f5a1b0d2 | 783 | |
9b6b54e2 NC |
784 | if (TARGET_FPE) |
785 | { | |
29ad9694 RE |
786 | if (arm_fpu_tune == FPUTYPE_FPA_EMU3) |
787 | arm_fpu_tune = FPUTYPE_FPA_EMU2; | |
788 | else if (arm_fpu_tune == FPUTYPE_MAVERICK) | |
789 | warning ("-mfpe switch not supported by ep9312 target cpu - ignored."); | |
790 | else if (arm_fpu_tune != FPUTYPE_FPA) | |
791 | arm_fpu_tune = FPUTYPE_FPA_EMU2; | |
9b6b54e2 | 792 | } |
aec3cfba | 793 | |
f5a1b0d2 NC |
794 | /* For arm2/3 there is no need to do any scheduling if there is only |
795 | a floating point emulator, or we are doing software floating-point. */ | |
29ad9694 | 796 | if ((TARGET_SOFT_FLOAT || arm_fpu_tune != FPUTYPE_FPA) |
ed0e6530 | 797 | && (tune_flags & FL_MODE32) == 0) |
f5a1b0d2 | 798 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
aec3cfba | 799 | |
cd2b33d0 | 800 | arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26; |
b355a481 NC |
801 | |
802 | if (structure_size_string != NULL) | |
803 | { | |
804 | int size = strtol (structure_size_string, NULL, 0); | |
805 | ||
806 | if (size == 8 || size == 32) | |
807 | arm_structure_size_boundary = size; | |
808 | else | |
c725bd79 | 809 | warning ("structure size boundary can only be set to 8 or 32"); |
b355a481 | 810 | } |
ed0e6530 PB |
811 | |
812 | if (arm_pic_register_string != NULL) | |
813 | { | |
5b43fed1 | 814 | int pic_register = decode_reg_name (arm_pic_register_string); |
e26053d1 | 815 | |
5895f793 | 816 | if (!flag_pic) |
ed0e6530 PB |
817 | warning ("-mpic-register= is useless without -fpic"); |
818 | ||
ed0e6530 | 819 | /* Prevent the user from choosing an obviously stupid PIC register. */ |
5b43fed1 RH |
820 | else if (pic_register < 0 || call_used_regs[pic_register] |
821 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
822 | || pic_register == STACK_POINTER_REGNUM | |
823 | || pic_register >= PC_REGNUM) | |
c725bd79 | 824 | error ("unable to use '%s' for PIC register", arm_pic_register_string); |
ed0e6530 PB |
825 | else |
826 | arm_pic_register = pic_register; | |
827 | } | |
d5b7b3ae RE |
828 | |
829 | if (TARGET_THUMB && flag_schedule_insns) | |
830 | { | |
831 | /* Don't warn since it's on by default in -O2. */ | |
832 | flag_schedule_insns = 0; | |
833 | } | |
834 | ||
f5a1b0d2 NC |
835 | /* If optimizing for space, don't synthesize constants. |
836 | For processors with load scheduling, it never costs more than 2 cycles | |
837 | to load a constant, and the load scheduler may well reduce that to 1. */ | |
aec3cfba | 838 | if (optimize_size || (tune_flags & FL_LDSCHED)) |
f5a1b0d2 | 839 | arm_constant_limit = 1; |
aec3cfba | 840 | |
4b3c2e48 | 841 | if (arm_arch_xscale) |
d19fb8e3 NC |
842 | arm_constant_limit = 2; |
843 | ||
f5a1b0d2 NC |
844 | /* If optimizing for size, bump the number of instructions that we |
845 | are prepared to conditionally execute (even on a StrongARM). | |
846 | Otherwise for the StrongARM, which has early execution of branches, | |
847 | a sequence that is worth skipping is shorter. */ | |
848 | if (optimize_size) | |
849 | max_insns_skipped = 6; | |
850 | else if (arm_is_strong) | |
851 | max_insns_skipped = 3; | |
92a432f4 RE |
852 | |
853 | /* Register global variables with the garbage collector. */ | |
854 | arm_add_gc_roots (); | |
855 | } | |
856 | ||
857 | static void | |
e32bac5b | 858 | arm_add_gc_roots (void) |
92a432f4 | 859 | { |
c7319d87 RE |
860 | gcc_obstack_init(&minipool_obstack); |
861 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 862 | } |
cce8749e | 863 | \f |
6d3d9133 NC |
864 | /* A table of known ARM exception types. |
865 | For use with the interrupt function attribute. */ | |
866 | ||
867 | typedef struct | |
868 | { | |
8b60264b KG |
869 | const char *const arg; |
870 | const unsigned long return_value; | |
6d3d9133 NC |
871 | } |
872 | isr_attribute_arg; | |
873 | ||
8b60264b | 874 | static const isr_attribute_arg isr_attribute_args [] = |
6d3d9133 NC |
875 | { |
876 | { "IRQ", ARM_FT_ISR }, | |
877 | { "irq", ARM_FT_ISR }, | |
878 | { "FIQ", ARM_FT_FIQ }, | |
879 | { "fiq", ARM_FT_FIQ }, | |
880 | { "ABORT", ARM_FT_ISR }, | |
881 | { "abort", ARM_FT_ISR }, | |
882 | { "ABORT", ARM_FT_ISR }, | |
883 | { "abort", ARM_FT_ISR }, | |
884 | { "UNDEF", ARM_FT_EXCEPTION }, | |
885 | { "undef", ARM_FT_EXCEPTION }, | |
886 | { "SWI", ARM_FT_EXCEPTION }, | |
887 | { "swi", ARM_FT_EXCEPTION }, | |
888 | { NULL, ARM_FT_NORMAL } | |
889 | }; | |
890 | ||
891 | /* Returns the (interrupt) function type of the current | |
892 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
893 | ||
894 | static unsigned long | |
e32bac5b | 895 | arm_isr_value (tree argument) |
6d3d9133 | 896 | { |
8b60264b | 897 | const isr_attribute_arg * ptr; |
1d6e90ac | 898 | const char * arg; |
6d3d9133 NC |
899 | |
900 | /* No argument - default to IRQ. */ | |
901 | if (argument == NULL_TREE) | |
902 | return ARM_FT_ISR; | |
903 | ||
904 | /* Get the value of the argument. */ | |
905 | if (TREE_VALUE (argument) == NULL_TREE | |
906 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
907 | return ARM_FT_UNKNOWN; | |
908 | ||
909 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
910 | ||
911 | /* Check it against the list of known arguments. */ | |
5a9335ef | 912 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) |
1d6e90ac NC |
913 | if (streq (arg, ptr->arg)) |
914 | return ptr->return_value; | |
6d3d9133 | 915 | |
05713b80 | 916 | /* An unrecognized interrupt type. */ |
6d3d9133 NC |
917 | return ARM_FT_UNKNOWN; |
918 | } | |
919 | ||
920 | /* Computes the type of the current function. */ | |
921 | ||
922 | static unsigned long | |
e32bac5b | 923 | arm_compute_func_type (void) |
6d3d9133 NC |
924 | { |
925 | unsigned long type = ARM_FT_UNKNOWN; | |
926 | tree a; | |
927 | tree attr; | |
928 | ||
929 | if (TREE_CODE (current_function_decl) != FUNCTION_DECL) | |
930 | abort (); | |
931 | ||
932 | /* Decide if the current function is volatile. Such functions | |
933 | never return, and many memory cycles can be saved by not storing | |
934 | register values that will never be needed again. This optimization | |
935 | was added to speed up context switching in a kernel application. */ | |
936 | if (optimize > 0 | |
937 | && current_function_nothrow | |
938 | && TREE_THIS_VOLATILE (current_function_decl)) | |
939 | type |= ARM_FT_VOLATILE; | |
940 | ||
941 | if (current_function_needs_context) | |
942 | type |= ARM_FT_NESTED; | |
943 | ||
91d231cb | 944 | attr = DECL_ATTRIBUTES (current_function_decl); |
6d3d9133 NC |
945 | |
946 | a = lookup_attribute ("naked", attr); | |
947 | if (a != NULL_TREE) | |
948 | type |= ARM_FT_NAKED; | |
949 | ||
950 | if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX) | |
951 | type |= ARM_FT_EXCEPTION_HANDLER; | |
952 | else | |
953 | { | |
954 | a = lookup_attribute ("isr", attr); | |
955 | if (a == NULL_TREE) | |
956 | a = lookup_attribute ("interrupt", attr); | |
957 | ||
958 | if (a == NULL_TREE) | |
959 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
960 | else | |
961 | type |= arm_isr_value (TREE_VALUE (a)); | |
962 | } | |
963 | ||
964 | return type; | |
965 | } | |
966 | ||
967 | /* Returns the type of the current function. */ | |
968 | ||
969 | unsigned long | |
e32bac5b | 970 | arm_current_func_type (void) |
6d3d9133 NC |
971 | { |
972 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
973 | cfun->machine->func_type = arm_compute_func_type (); | |
974 | ||
975 | return cfun->machine->func_type; | |
976 | } | |
977 | \f | |
6354dc9b | 978 | /* Return 1 if it is possible to return using a single instruction. */ |
6d3d9133 | 979 | |
ff9940b0 | 980 | int |
e32bac5b | 981 | use_return_insn (int iscond) |
ff9940b0 RE |
982 | { |
983 | int regno; | |
9b598fa0 | 984 | unsigned int func_type; |
d5db54a1 | 985 | unsigned long saved_int_regs; |
ff9940b0 | 986 | |
d5b7b3ae | 987 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
988 | if (!reload_completed) |
989 | return 0; | |
990 | ||
9b598fa0 RE |
991 | func_type = arm_current_func_type (); |
992 | ||
3a7731fd PB |
993 | /* Naked functions and volatile functions need special |
994 | consideration. */ | |
995 | if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED)) | |
6d3d9133 | 996 | return 0; |
06bea5aa NC |
997 | |
998 | /* So do interrupt functions that use the frame pointer. */ | |
999 | if (IS_INTERRUPT (func_type) && frame_pointer_needed) | |
1000 | return 0; | |
6d3d9133 NC |
1001 | |
1002 | /* As do variadic functions. */ | |
1003 | if (current_function_pretend_args_size | |
3cb66fd7 | 1004 | || cfun->machine->uses_anonymous_args |
d5b7b3ae | 1005 | /* Of if the function calls __builtin_eh_return () */ |
6d3d9133 | 1006 | || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER |
d5b7b3ae | 1007 | /* Or if there is no frame pointer and there is a stack adjustment. */ |
0977774b | 1008 | || ((arm_get_frame_size () + current_function_outgoing_args_size != 0) |
5895f793 | 1009 | && !frame_pointer_needed)) |
ff9940b0 RE |
1010 | return 0; |
1011 | ||
d5db54a1 RE |
1012 | saved_int_regs = arm_compute_save_reg_mask (); |
1013 | ||
b111229a | 1014 | /* Can't be done if interworking with Thumb, and any registers have been |
d5db54a1 RE |
1015 | stacked. */ |
1016 | if (TARGET_INTERWORK && saved_int_regs != 0) | |
b36ba79f | 1017 | return 0; |
d5db54a1 RE |
1018 | |
1019 | /* On StrongARM, conditional returns are expensive if they aren't | |
1020 | taken and multiple registers have been stacked. */ | |
1021 | if (iscond && arm_is_strong) | |
6ed30148 | 1022 | { |
d5db54a1 RE |
1023 | /* Conditional return when just the LR is stored is a simple |
1024 | conditional-load instruction, that's not expensive. */ | |
1025 | if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) | |
1026 | return 0; | |
6ed30148 RE |
1027 | |
1028 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) | |
b111229a | 1029 | return 0; |
6ed30148 | 1030 | } |
d5db54a1 RE |
1031 | |
1032 | /* If there are saved registers but the LR isn't saved, then we need | |
1033 | two instructions for the return. */ | |
1034 | if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) | |
1035 | return 0; | |
1036 | ||
3b684012 | 1037 | /* Can't be done if any of the FPA regs are pushed, |
6d3d9133 | 1038 | since this also requires an insn. */ |
d5b7b3ae RE |
1039 | if (TARGET_HARD_FLOAT) |
1040 | for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++) | |
5895f793 | 1041 | if (regs_ever_live[regno] && !call_used_regs[regno]) |
d5b7b3ae | 1042 | return 0; |
ff9940b0 | 1043 | |
5a9335ef NC |
1044 | if (TARGET_REALLY_IWMMXT) |
1045 | for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) | |
1046 | if (regs_ever_live[regno] && ! call_used_regs [regno]) | |
1047 | return 0; | |
1048 | ||
ff9940b0 RE |
1049 | return 1; |
1050 | } | |
1051 | ||
cce8749e CH |
1052 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
1053 | ||
1054 | int | |
e32bac5b | 1055 | const_ok_for_arm (HOST_WIDE_INT i) |
cce8749e | 1056 | { |
30cf4896 | 1057 | unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF; |
cce8749e | 1058 | |
56636818 JL |
1059 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
1060 | be all zero, or all one. */ | |
30cf4896 KG |
1061 | if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 |
1062 | && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) | |
1063 | != ((~(unsigned HOST_WIDE_INT) 0) | |
1064 | & ~(unsigned HOST_WIDE_INT) 0xffffffff))) | |
56636818 JL |
1065 | return FALSE; |
1066 | ||
e2c671ba RE |
1067 | /* Fast return for 0 and powers of 2 */ |
1068 | if ((i & (i - 1)) == 0) | |
1069 | return TRUE; | |
1070 | ||
cce8749e CH |
1071 | do |
1072 | { | |
30cf4896 | 1073 | if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0) |
f3bb6135 | 1074 | return TRUE; |
abaa26e5 | 1075 | mask = |
30cf4896 KG |
1076 | (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff) |
1077 | >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff; | |
ebe413e5 NC |
1078 | } |
1079 | while (mask != ~(unsigned HOST_WIDE_INT) 0xFF); | |
cce8749e | 1080 | |
f3bb6135 RE |
1081 | return FALSE; |
1082 | } | |
cce8749e | 1083 | |
6354dc9b | 1084 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 | 1085 | static int |
e32bac5b | 1086 | const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) |
e2c671ba RE |
1087 | { |
1088 | if (const_ok_for_arm (i)) | |
1089 | return 1; | |
1090 | ||
1091 | switch (code) | |
1092 | { | |
1093 | case PLUS: | |
1094 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); | |
1095 | ||
1096 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
1097 | case XOR: | |
1098 | case IOR: | |
1099 | return 0; | |
1100 | ||
1101 | case AND: | |
1102 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
1103 | ||
1104 | default: | |
1105 | abort (); | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | /* Emit a sequence of insns to handle a large constant. | |
1110 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
1111 | IOR, AND, XOR, MINUS; | |
1112 | MODE is the mode in which the operation is being performed; | |
1113 | VAL is the integer to operate on; | |
1114 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
1115 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
1116 | either produce a simpler sequence, or we will want to cse the values. |
1117 | Return value is the number of insns emitted. */ | |
e2c671ba RE |
1118 | |
1119 | int | |
e32bac5b RE |
1120 | arm_split_constant (enum rtx_code code, enum machine_mode mode, |
1121 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets) | |
2b835d68 RE |
1122 | { |
1123 | if (subtargets || code == SET | |
1124 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
1125 | && REGNO (target) != REGNO (source))) | |
1126 | { | |
4b632bf1 | 1127 | /* After arm_reorg has been called, we can't fix up expensive |
05713b80 | 1128 | constants by pushing them into memory so we must synthesize |
4b632bf1 RE |
1129 | them in-line, regardless of the cost. This is only likely to |
1130 | be more costly on chips that have load delay slots and we are | |
1131 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
1132 | occurred before the final instruction emission). |
1133 | ||
1134 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 1135 | */ |
5895f793 | 1136 | if (!after_arm_reorg |
4b632bf1 RE |
1137 | && (arm_gen_constant (code, mode, val, target, source, 1, 0) |
1138 | > arm_constant_limit + (code != SET))) | |
2b835d68 RE |
1139 | { |
1140 | if (code == SET) | |
1141 | { | |
1142 | /* Currently SET is the only monadic value for CODE, all | |
1143 | the rest are diadic. */ | |
43cffd11 | 1144 | emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val))); |
2b835d68 RE |
1145 | return 1; |
1146 | } | |
1147 | else | |
1148 | { | |
1149 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
1150 | ||
43cffd11 | 1151 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val))); |
2b835d68 RE |
1152 | /* For MINUS, the value is subtracted from, since we never |
1153 | have subtraction of a constant. */ | |
1154 | if (code == MINUS) | |
43cffd11 | 1155 | emit_insn (gen_rtx_SET (VOIDmode, target, |
d5b7b3ae | 1156 | gen_rtx_MINUS (mode, temp, source))); |
2b835d68 | 1157 | else |
43cffd11 RE |
1158 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1159 | gen_rtx (code, mode, source, temp))); | |
2b835d68 RE |
1160 | return 2; |
1161 | } | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | return arm_gen_constant (code, mode, val, target, source, subtargets, 1); | |
1166 | } | |
1167 | ||
ceebdb09 | 1168 | static int |
e32bac5b | 1169 | count_insns_for_constant (HOST_WIDE_INT remainder, int i) |
ceebdb09 PB |
1170 | { |
1171 | HOST_WIDE_INT temp1; | |
1172 | int num_insns = 0; | |
1173 | do | |
1174 | { | |
1175 | int end; | |
1176 | ||
1177 | if (i <= 0) | |
1178 | i += 32; | |
1179 | if (remainder & (3 << (i - 2))) | |
1180 | { | |
1181 | end = i - 8; | |
1182 | if (end < 0) | |
1183 | end += 32; | |
1184 | temp1 = remainder & ((0x0ff << end) | |
1185 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
1186 | remainder &= ~temp1; | |
1187 | num_insns++; | |
1188 | i -= 6; | |
1189 | } | |
1190 | i -= 2; | |
1191 | } while (remainder); | |
1192 | return num_insns; | |
1193 | } | |
1194 | ||
2b835d68 RE |
1195 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
1196 | RTL generation. */ | |
1d6e90ac | 1197 | |
d5b7b3ae | 1198 | static int |
e32bac5b RE |
1199 | arm_gen_constant (enum rtx_code code, enum machine_mode mode, |
1200 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets, | |
1201 | int generate) | |
e2c671ba | 1202 | { |
e2c671ba RE |
1203 | int can_invert = 0; |
1204 | int can_negate = 0; | |
1205 | int can_negate_initial = 0; | |
1206 | int can_shift = 0; | |
1207 | int i; | |
1208 | int num_bits_set = 0; | |
1209 | int set_sign_bit_copies = 0; | |
1210 | int clear_sign_bit_copies = 0; | |
1211 | int clear_zero_bit_copies = 0; | |
1212 | int set_zero_bit_copies = 0; | |
1213 | int insns = 0; | |
e2c671ba | 1214 | unsigned HOST_WIDE_INT temp1, temp2; |
30cf4896 | 1215 | unsigned HOST_WIDE_INT remainder = val & 0xffffffff; |
e2c671ba | 1216 | |
d5b7b3ae | 1217 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
1218 | check for degenerate cases; these can occur when DImode operations |
1219 | are split. */ | |
1220 | switch (code) | |
1221 | { | |
1222 | case SET: | |
1223 | can_invert = 1; | |
1224 | can_shift = 1; | |
1225 | can_negate = 1; | |
1226 | break; | |
1227 | ||
1228 | case PLUS: | |
1229 | can_negate = 1; | |
1230 | can_negate_initial = 1; | |
1231 | break; | |
1232 | ||
1233 | case IOR: | |
30cf4896 | 1234 | if (remainder == 0xffffffff) |
e2c671ba | 1235 | { |
2b835d68 | 1236 | if (generate) |
43cffd11 RE |
1237 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1238 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
1239 | return 1; |
1240 | } | |
1241 | if (remainder == 0) | |
1242 | { | |
1243 | if (reload_completed && rtx_equal_p (target, source)) | |
1244 | return 0; | |
2b835d68 | 1245 | if (generate) |
43cffd11 | 1246 | emit_insn (gen_rtx_SET (VOIDmode, target, source)); |
e2c671ba RE |
1247 | return 1; |
1248 | } | |
1249 | break; | |
1250 | ||
1251 | case AND: | |
1252 | if (remainder == 0) | |
1253 | { | |
2b835d68 | 1254 | if (generate) |
43cffd11 | 1255 | emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx)); |
e2c671ba RE |
1256 | return 1; |
1257 | } | |
30cf4896 | 1258 | if (remainder == 0xffffffff) |
e2c671ba RE |
1259 | { |
1260 | if (reload_completed && rtx_equal_p (target, source)) | |
1261 | return 0; | |
2b835d68 | 1262 | if (generate) |
43cffd11 | 1263 | emit_insn (gen_rtx_SET (VOIDmode, target, source)); |
e2c671ba RE |
1264 | return 1; |
1265 | } | |
1266 | can_invert = 1; | |
1267 | break; | |
1268 | ||
1269 | case XOR: | |
1270 | if (remainder == 0) | |
1271 | { | |
1272 | if (reload_completed && rtx_equal_p (target, source)) | |
1273 | return 0; | |
2b835d68 | 1274 | if (generate) |
43cffd11 | 1275 | emit_insn (gen_rtx_SET (VOIDmode, target, source)); |
e2c671ba RE |
1276 | return 1; |
1277 | } | |
30cf4896 | 1278 | if (remainder == 0xffffffff) |
e2c671ba | 1279 | { |
2b835d68 | 1280 | if (generate) |
43cffd11 RE |
1281 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1282 | gen_rtx_NOT (mode, source))); | |
e2c671ba RE |
1283 | return 1; |
1284 | } | |
1285 | ||
1286 | /* We don't know how to handle this yet below. */ | |
1287 | abort (); | |
1288 | ||
1289 | case MINUS: | |
1290 | /* We treat MINUS as (val - source), since (source - val) is always | |
1291 | passed as (source + (-val)). */ | |
1292 | if (remainder == 0) | |
1293 | { | |
2b835d68 | 1294 | if (generate) |
43cffd11 RE |
1295 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1296 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
1297 | return 1; |
1298 | } | |
1299 | if (const_ok_for_arm (val)) | |
1300 | { | |
2b835d68 | 1301 | if (generate) |
43cffd11 RE |
1302 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1303 | gen_rtx_MINUS (mode, GEN_INT (val), | |
1304 | source))); | |
e2c671ba RE |
1305 | return 1; |
1306 | } | |
1307 | can_negate = 1; | |
1308 | ||
1309 | break; | |
1310 | ||
1311 | default: | |
1312 | abort (); | |
1313 | } | |
1314 | ||
6354dc9b | 1315 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
1316 | if (const_ok_for_arm (val) |
1317 | || (can_negate_initial && const_ok_for_arm (-val)) | |
1318 | || (can_invert && const_ok_for_arm (~val))) | |
1319 | { | |
2b835d68 | 1320 | if (generate) |
43cffd11 RE |
1321 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1322 | (source ? gen_rtx (code, mode, source, | |
1323 | GEN_INT (val)) | |
1324 | : GEN_INT (val)))); | |
e2c671ba RE |
1325 | return 1; |
1326 | } | |
1327 | ||
e2c671ba | 1328 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 1329 | optimizations. */ |
e2c671ba RE |
1330 | for (i = 31; i >= 0; i--) |
1331 | { | |
1332 | if ((remainder & (1 << i)) == 0) | |
1333 | clear_sign_bit_copies++; | |
1334 | else | |
1335 | break; | |
1336 | } | |
1337 | ||
1338 | for (i = 31; i >= 0; i--) | |
1339 | { | |
1340 | if ((remainder & (1 << i)) != 0) | |
1341 | set_sign_bit_copies++; | |
1342 | else | |
1343 | break; | |
1344 | } | |
1345 | ||
1346 | for (i = 0; i <= 31; i++) | |
1347 | { | |
1348 | if ((remainder & (1 << i)) == 0) | |
1349 | clear_zero_bit_copies++; | |
1350 | else | |
1351 | break; | |
1352 | } | |
1353 | ||
1354 | for (i = 0; i <= 31; i++) | |
1355 | { | |
1356 | if ((remainder & (1 << i)) != 0) | |
1357 | set_zero_bit_copies++; | |
1358 | else | |
1359 | break; | |
1360 | } | |
1361 | ||
1362 | switch (code) | |
1363 | { | |
1364 | case SET: | |
1365 | /* See if we can do this by sign_extending a constant that is known | |
1366 | to be negative. This is a good, way of doing it, since the shift | |
1367 | may well merge into a subsequent insn. */ | |
1368 | if (set_sign_bit_copies > 1) | |
1369 | { | |
1370 | if (const_ok_for_arm | |
1371 | (temp1 = ARM_SIGN_EXTEND (remainder | |
1372 | << (set_sign_bit_copies - 1)))) | |
1373 | { | |
2b835d68 RE |
1374 | if (generate) |
1375 | { | |
d499463f | 1376 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
43cffd11 RE |
1377 | emit_insn (gen_rtx_SET (VOIDmode, new_src, |
1378 | GEN_INT (temp1))); | |
2b835d68 RE |
1379 | emit_insn (gen_ashrsi3 (target, new_src, |
1380 | GEN_INT (set_sign_bit_copies - 1))); | |
1381 | } | |
e2c671ba RE |
1382 | return 2; |
1383 | } | |
1384 | /* For an inverted constant, we will need to set the low bits, | |
1385 | these will be shifted out of harm's way. */ | |
1386 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
1387 | if (const_ok_for_arm (~temp1)) | |
1388 | { | |
2b835d68 RE |
1389 | if (generate) |
1390 | { | |
d499463f | 1391 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
43cffd11 RE |
1392 | emit_insn (gen_rtx_SET (VOIDmode, new_src, |
1393 | GEN_INT (temp1))); | |
2b835d68 RE |
1394 | emit_insn (gen_ashrsi3 (target, new_src, |
1395 | GEN_INT (set_sign_bit_copies - 1))); | |
1396 | } | |
e2c671ba RE |
1397 | return 2; |
1398 | } | |
1399 | } | |
1400 | ||
1401 | /* See if we can generate this by setting the bottom (or the top) | |
1402 | 16 bits, and then shifting these into the other half of the | |
1403 | word. We only look for the simplest cases, to do more would cost | |
1404 | too much. Be careful, however, not to generate this when the | |
1405 | alternative would take fewer insns. */ | |
30cf4896 | 1406 | if (val & 0xffff0000) |
e2c671ba | 1407 | { |
30cf4896 | 1408 | temp1 = remainder & 0xffff0000; |
e2c671ba RE |
1409 | temp2 = remainder & 0x0000ffff; |
1410 | ||
6354dc9b | 1411 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
1412 | for (i = 9; i < 24; i++) |
1413 | { | |
30cf4896 | 1414 | if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) |
5895f793 | 1415 | && !const_ok_for_arm (temp2)) |
e2c671ba | 1416 | { |
d499463f RE |
1417 | rtx new_src = (subtargets |
1418 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
1419 | : target); | |
1420 | insns = arm_gen_constant (code, mode, temp2, new_src, | |
2b835d68 | 1421 | source, subtargets, generate); |
e2c671ba | 1422 | source = new_src; |
2b835d68 | 1423 | if (generate) |
43cffd11 RE |
1424 | emit_insn (gen_rtx_SET |
1425 | (VOIDmode, target, | |
1426 | gen_rtx_IOR (mode, | |
1427 | gen_rtx_ASHIFT (mode, source, | |
1428 | GEN_INT (i)), | |
1429 | source))); | |
e2c671ba RE |
1430 | return insns + 1; |
1431 | } | |
1432 | } | |
1433 | ||
6354dc9b | 1434 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
1435 | for (i = 17; i < 24; i++) |
1436 | { | |
1437 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 1438 | && !const_ok_for_arm (temp1)) |
e2c671ba | 1439 | { |
d499463f RE |
1440 | rtx new_src = (subtargets |
1441 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
1442 | : target); | |
1443 | insns = arm_gen_constant (code, mode, temp1, new_src, | |
2b835d68 | 1444 | source, subtargets, generate); |
e2c671ba | 1445 | source = new_src; |
2b835d68 | 1446 | if (generate) |
43cffd11 RE |
1447 | emit_insn |
1448 | (gen_rtx_SET (VOIDmode, target, | |
1449 | gen_rtx_IOR | |
1450 | (mode, | |
1451 | gen_rtx_LSHIFTRT (mode, source, | |
1452 | GEN_INT (i)), | |
1453 | source))); | |
e2c671ba RE |
1454 | return insns + 1; |
1455 | } | |
1456 | } | |
1457 | } | |
1458 | break; | |
1459 | ||
1460 | case IOR: | |
1461 | case XOR: | |
7b64da89 RE |
1462 | /* If we have IOR or XOR, and the constant can be loaded in a |
1463 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
1464 | then this can be done in two instructions instead of 3-4. */ |
1465 | if (subtargets | |
d499463f | 1466 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 1467 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 1468 | { |
5895f793 | 1469 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 1470 | { |
2b835d68 RE |
1471 | if (generate) |
1472 | { | |
1473 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 1474 | |
43cffd11 RE |
1475 | emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val))); |
1476 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
1477 | gen_rtx (code, mode, source, sub))); | |
2b835d68 | 1478 | } |
e2c671ba RE |
1479 | return 2; |
1480 | } | |
1481 | } | |
1482 | ||
1483 | if (code == XOR) | |
1484 | break; | |
1485 | ||
1486 | if (set_sign_bit_copies > 8 | |
1487 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
1488 | { | |
2b835d68 RE |
1489 | if (generate) |
1490 | { | |
1491 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
1492 | rtx shift = GEN_INT (set_sign_bit_copies); | |
1493 | ||
43cffd11 RE |
1494 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1495 | gen_rtx_NOT (mode, | |
1496 | gen_rtx_ASHIFT (mode, | |
1497 | source, | |
f5a1b0d2 | 1498 | shift)))); |
43cffd11 RE |
1499 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1500 | gen_rtx_NOT (mode, | |
1501 | gen_rtx_LSHIFTRT (mode, sub, | |
1502 | shift)))); | |
2b835d68 | 1503 | } |
e2c671ba RE |
1504 | return 2; |
1505 | } | |
1506 | ||
1507 | if (set_zero_bit_copies > 8 | |
1508 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
1509 | { | |
2b835d68 RE |
1510 | if (generate) |
1511 | { | |
1512 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
1513 | rtx shift = GEN_INT (set_zero_bit_copies); | |
1514 | ||
43cffd11 RE |
1515 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1516 | gen_rtx_NOT (mode, | |
1517 | gen_rtx_LSHIFTRT (mode, | |
1518 | source, | |
f5a1b0d2 | 1519 | shift)))); |
43cffd11 RE |
1520 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1521 | gen_rtx_NOT (mode, | |
1522 | gen_rtx_ASHIFT (mode, sub, | |
f5a1b0d2 | 1523 | shift)))); |
2b835d68 | 1524 | } |
e2c671ba RE |
1525 | return 2; |
1526 | } | |
1527 | ||
5895f793 | 1528 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 1529 | { |
2b835d68 RE |
1530 | if (generate) |
1531 | { | |
1532 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
43cffd11 RE |
1533 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1534 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
1535 | source = sub; |
1536 | if (subtargets) | |
1537 | sub = gen_reg_rtx (mode); | |
43cffd11 RE |
1538 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1539 | gen_rtx_AND (mode, source, | |
1540 | GEN_INT (temp1)))); | |
1541 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
1542 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 1543 | } |
e2c671ba RE |
1544 | return 3; |
1545 | } | |
1546 | break; | |
1547 | ||
1548 | case AND: | |
1549 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
1550 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
1551 | { | |
30cf4896 | 1552 | HOST_WIDE_INT shift_mask = ((0xffffffff |
e2c671ba | 1553 | << (32 - clear_sign_bit_copies)) |
30cf4896 | 1554 | & 0xffffffff); |
e2c671ba | 1555 | |
30cf4896 | 1556 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 1557 | { |
2b835d68 RE |
1558 | if (generate) |
1559 | { | |
d499463f | 1560 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2b835d68 | 1561 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, |
d499463f RE |
1562 | new_src, source, subtargets, 1); |
1563 | source = new_src; | |
2b835d68 RE |
1564 | } |
1565 | else | |
d499463f RE |
1566 | { |
1567 | rtx targ = subtargets ? NULL_RTX : target; | |
1568 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, | |
1569 | targ, source, subtargets, 0); | |
1570 | } | |
2b835d68 RE |
1571 | } |
1572 | ||
1573 | if (generate) | |
1574 | { | |
d499463f RE |
1575 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1576 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
1577 | ||
1578 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
1579 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
1580 | } |
1581 | ||
e2c671ba RE |
1582 | return insns + 2; |
1583 | } | |
1584 | ||
1585 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
1586 | { | |
1587 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
e2c671ba | 1588 | |
30cf4896 | 1589 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 1590 | { |
2b835d68 RE |
1591 | if (generate) |
1592 | { | |
d499463f RE |
1593 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1594 | ||
2b835d68 | 1595 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, |
d499463f RE |
1596 | new_src, source, subtargets, 1); |
1597 | source = new_src; | |
2b835d68 RE |
1598 | } |
1599 | else | |
d499463f RE |
1600 | { |
1601 | rtx targ = subtargets ? NULL_RTX : target; | |
1602 | ||
1603 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, | |
1604 | targ, source, subtargets, 0); | |
1605 | } | |
2b835d68 RE |
1606 | } |
1607 | ||
1608 | if (generate) | |
1609 | { | |
d499463f RE |
1610 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1611 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
1612 | ||
1613 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
1614 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
1615 | } |
1616 | ||
e2c671ba RE |
1617 | return insns + 2; |
1618 | } | |
1619 | ||
1620 | break; | |
1621 | ||
1622 | default: | |
1623 | break; | |
1624 | } | |
1625 | ||
1626 | for (i = 0; i < 32; i++) | |
1627 | if (remainder & (1 << i)) | |
1628 | num_bits_set++; | |
1629 | ||
1630 | if (code == AND || (can_invert && num_bits_set > 16)) | |
30cf4896 | 1631 | remainder = (~remainder) & 0xffffffff; |
e2c671ba | 1632 | else if (code == PLUS && num_bits_set > 16) |
30cf4896 | 1633 | remainder = (-remainder) & 0xffffffff; |
e2c671ba RE |
1634 | else |
1635 | { | |
1636 | can_invert = 0; | |
1637 | can_negate = 0; | |
1638 | } | |
1639 | ||
1640 | /* Now try and find a way of doing the job in either two or three | |
1641 | instructions. | |
1642 | We start by looking for the largest block of zeros that are aligned on | |
1643 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
1644 | top of the word when we drop off the bottom. | |
6354dc9b | 1645 | In the worst case this code should produce no more than four insns. */ |
e2c671ba RE |
1646 | { |
1647 | int best_start = 0; | |
1648 | int best_consecutive_zeros = 0; | |
1649 | ||
1650 | for (i = 0; i < 32; i += 2) | |
1651 | { | |
1652 | int consecutive_zeros = 0; | |
1653 | ||
5895f793 | 1654 | if (!(remainder & (3 << i))) |
e2c671ba | 1655 | { |
5895f793 | 1656 | while ((i < 32) && !(remainder & (3 << i))) |
e2c671ba RE |
1657 | { |
1658 | consecutive_zeros += 2; | |
1659 | i += 2; | |
1660 | } | |
1661 | if (consecutive_zeros > best_consecutive_zeros) | |
1662 | { | |
1663 | best_consecutive_zeros = consecutive_zeros; | |
1664 | best_start = i - consecutive_zeros; | |
1665 | } | |
1666 | i -= 2; | |
1667 | } | |
1668 | } | |
1669 | ||
ceebdb09 PB |
1670 | /* So long as it won't require any more insns to do so, it's |
1671 | desirable to emit a small constant (in bits 0...9) in the last | |
1672 | insn. This way there is more chance that it can be combined with | |
1673 | a later addressing insn to form a pre-indexed load or store | |
1674 | operation. Consider: | |
1675 | ||
1676 | *((volatile int *)0xe0000100) = 1; | |
1677 | *((volatile int *)0xe0000110) = 2; | |
1678 | ||
1679 | We want this to wind up as: | |
1680 | ||
1681 | mov rA, #0xe0000000 | |
1682 | mov rB, #1 | |
1683 | str rB, [rA, #0x100] | |
1684 | mov rB, #2 | |
1685 | str rB, [rA, #0x110] | |
1686 | ||
1687 | rather than having to synthesize both large constants from scratch. | |
1688 | ||
1689 | Therefore, we calculate how many insns would be required to emit | |
1690 | the constant starting from `best_start', and also starting from | |
1691 | zero (ie with bit 31 first to be output). If `best_start' doesn't | |
1692 | yield a shorter sequence, we may as well use zero. */ | |
1693 | if (best_start != 0 | |
1694 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
1695 | && (count_insns_for_constant (remainder, 0) <= | |
1696 | count_insns_for_constant (remainder, best_start))) | |
1697 | best_start = 0; | |
1698 | ||
1699 | /* Now start emitting the insns. */ | |
e2c671ba RE |
1700 | i = best_start; |
1701 | do | |
1702 | { | |
1703 | int end; | |
1704 | ||
1705 | if (i <= 0) | |
1706 | i += 32; | |
1707 | if (remainder & (3 << (i - 2))) | |
1708 | { | |
1709 | end = i - 8; | |
1710 | if (end < 0) | |
1711 | end += 32; | |
1712 | temp1 = remainder & ((0x0ff << end) | |
1713 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
1714 | remainder &= ~temp1; | |
1715 | ||
d499463f | 1716 | if (generate) |
e2c671ba | 1717 | { |
9503f3d1 RH |
1718 | rtx new_src, temp1_rtx; |
1719 | ||
1720 | if (code == SET || code == MINUS) | |
1721 | { | |
1722 | new_src = (subtargets ? gen_reg_rtx (mode) : target); | |
96ae8197 | 1723 | if (can_invert && code != MINUS) |
9503f3d1 RH |
1724 | temp1 = ~temp1; |
1725 | } | |
1726 | else | |
1727 | { | |
96ae8197 | 1728 | if (remainder && subtargets) |
9503f3d1 | 1729 | new_src = gen_reg_rtx (mode); |
96ae8197 NC |
1730 | else |
1731 | new_src = target; | |
9503f3d1 RH |
1732 | if (can_invert) |
1733 | temp1 = ~temp1; | |
1734 | else if (can_negate) | |
1735 | temp1 = -temp1; | |
1736 | } | |
1737 | ||
1738 | temp1 = trunc_int_for_mode (temp1, mode); | |
1739 | temp1_rtx = GEN_INT (temp1); | |
d499463f RE |
1740 | |
1741 | if (code == SET) | |
9503f3d1 | 1742 | ; |
d499463f | 1743 | else if (code == MINUS) |
9503f3d1 | 1744 | temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); |
d499463f | 1745 | else |
9503f3d1 RH |
1746 | temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); |
1747 | ||
1748 | emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx)); | |
d499463f | 1749 | source = new_src; |
e2c671ba RE |
1750 | } |
1751 | ||
d499463f RE |
1752 | if (code == SET) |
1753 | { | |
1754 | can_invert = 0; | |
1755 | code = PLUS; | |
1756 | } | |
1757 | else if (code == MINUS) | |
1758 | code = PLUS; | |
1759 | ||
e2c671ba | 1760 | insns++; |
e2c671ba RE |
1761 | i -= 6; |
1762 | } | |
1763 | i -= 2; | |
1d6e90ac NC |
1764 | } |
1765 | while (remainder); | |
e2c671ba | 1766 | } |
1d6e90ac | 1767 | |
e2c671ba RE |
1768 | return insns; |
1769 | } | |
1770 | ||
bd9c7e23 RE |
1771 | /* Canonicalize a comparison so that we are more likely to recognize it. |
1772 | This can be done for a few constant compares, where we can make the | |
1773 | immediate value easier to load. */ | |
1d6e90ac | 1774 | |
bd9c7e23 | 1775 | enum rtx_code |
e32bac5b | 1776 | arm_canonicalize_comparison (enum rtx_code code, rtx * op1) |
bd9c7e23 | 1777 | { |
ad076f4e | 1778 | unsigned HOST_WIDE_INT i = INTVAL (*op1); |
bd9c7e23 RE |
1779 | |
1780 | switch (code) | |
1781 | { | |
1782 | case EQ: | |
1783 | case NE: | |
1784 | return code; | |
1785 | ||
1786 | case GT: | |
1787 | case LE: | |
30cf4896 | 1788 | if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1) |
5895f793 | 1789 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 | 1790 | { |
5895f793 | 1791 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
1792 | return code == GT ? GE : LT; |
1793 | } | |
1794 | break; | |
1795 | ||
1796 | case GE: | |
1797 | case LT: | |
30cf4896 | 1798 | if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) |
5895f793 | 1799 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 1800 | { |
5895f793 | 1801 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
1802 | return code == GE ? GT : LE; |
1803 | } | |
1804 | break; | |
1805 | ||
1806 | case GTU: | |
1807 | case LEU: | |
30cf4896 | 1808 | if (i != ~((unsigned HOST_WIDE_INT) 0) |
5895f793 | 1809 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 RE |
1810 | { |
1811 | *op1 = GEN_INT (i + 1); | |
1812 | return code == GTU ? GEU : LTU; | |
1813 | } | |
1814 | break; | |
1815 | ||
1816 | case GEU: | |
1817 | case LTU: | |
1818 | if (i != 0 | |
5895f793 | 1819 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
1820 | { |
1821 | *op1 = GEN_INT (i - 1); | |
1822 | return code == GEU ? GTU : LEU; | |
1823 | } | |
1824 | break; | |
1825 | ||
1826 | default: | |
1827 | abort (); | |
1828 | } | |
1829 | ||
1830 | return code; | |
1831 | } | |
bd9c7e23 | 1832 | |
f5a1b0d2 NC |
1833 | /* Decide whether a type should be returned in memory (true) |
1834 | or in a register (false). This is called by the macro | |
1835 | RETURN_IN_MEMORY. */ | |
2b835d68 | 1836 | int |
e32bac5b | 1837 | arm_return_in_memory (tree type) |
2b835d68 | 1838 | { |
dc0ba55a JT |
1839 | HOST_WIDE_INT size; |
1840 | ||
5895f793 | 1841 | if (!AGGREGATE_TYPE_P (type)) |
9e291dbe | 1842 | /* All simple types are returned in registers. */ |
d7d01975 | 1843 | return 0; |
dc0ba55a JT |
1844 | |
1845 | size = int_size_in_bytes (type); | |
1846 | ||
1847 | if (TARGET_ATPCS) | |
1848 | { | |
1849 | /* ATPCS returns aggregate types in memory only if they are | |
1850 | larger than a word (or are variable size). */ | |
1851 | return (size < 0 || size > UNITS_PER_WORD); | |
1852 | } | |
d5b7b3ae | 1853 | |
6bc82793 | 1854 | /* For the arm-wince targets we choose to be compatible with Microsoft's |
d5b7b3ae RE |
1855 | ARM and Thumb compilers, which always return aggregates in memory. */ |
1856 | #ifndef ARM_WINCE | |
e529bd42 NC |
1857 | /* All structures/unions bigger than one word are returned in memory. |
1858 | Also catch the case where int_size_in_bytes returns -1. In this case | |
6bc82793 | 1859 | the aggregate is either huge or of variable size, and in either case |
e529bd42 | 1860 | we will want to return it via memory and not in a register. */ |
dc0ba55a | 1861 | if (size < 0 || size > UNITS_PER_WORD) |
d7d01975 | 1862 | return 1; |
d5b7b3ae | 1863 | |
d7d01975 | 1864 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
1865 | { |
1866 | tree field; | |
1867 | ||
3a2ea258 RE |
1868 | /* For a struct the APCS says that we only return in a register |
1869 | if the type is 'integer like' and every addressable element | |
1870 | has an offset of zero. For practical purposes this means | |
1871 | that the structure can have at most one non bit-field element | |
1872 | and that this element must be the first one in the structure. */ | |
1873 | ||
f5a1b0d2 NC |
1874 | /* Find the first field, ignoring non FIELD_DECL things which will |
1875 | have been created by C++. */ | |
1876 | for (field = TYPE_FIELDS (type); | |
1877 | field && TREE_CODE (field) != FIELD_DECL; | |
1878 | field = TREE_CHAIN (field)) | |
1879 | continue; | |
1880 | ||
1881 | if (field == NULL) | |
9e291dbe | 1882 | return 0; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 1883 | |
d5b7b3ae RE |
1884 | /* Check that the first field is valid for returning in a register. */ |
1885 | ||
1886 | /* ... Floats are not allowed */ | |
9e291dbe | 1887 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3a2ea258 RE |
1888 | return 1; |
1889 | ||
d5b7b3ae RE |
1890 | /* ... Aggregates that are not themselves valid for returning in |
1891 | a register are not allowed. */ | |
9e291dbe | 1892 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
3a2ea258 | 1893 | return 1; |
6f7ebcbb | 1894 | |
3a2ea258 RE |
1895 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
1896 | since they are not addressable. */ | |
f5a1b0d2 NC |
1897 | for (field = TREE_CHAIN (field); |
1898 | field; | |
1899 | field = TREE_CHAIN (field)) | |
1900 | { | |
1901 | if (TREE_CODE (field) != FIELD_DECL) | |
1902 | continue; | |
1903 | ||
5895f793 | 1904 | if (!DECL_BIT_FIELD_TYPE (field)) |
f5a1b0d2 NC |
1905 | return 1; |
1906 | } | |
2b835d68 RE |
1907 | |
1908 | return 0; | |
1909 | } | |
d7d01975 NC |
1910 | |
1911 | if (TREE_CODE (type) == UNION_TYPE) | |
2b835d68 RE |
1912 | { |
1913 | tree field; | |
1914 | ||
1915 | /* Unions can be returned in registers if every element is | |
1916 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
1917 | for (field = TYPE_FIELDS (type); |
1918 | field; | |
1919 | field = TREE_CHAIN (field)) | |
2b835d68 | 1920 | { |
f5a1b0d2 NC |
1921 | if (TREE_CODE (field) != FIELD_DECL) |
1922 | continue; | |
1923 | ||
6cc8c0b3 NC |
1924 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
1925 | return 1; | |
1926 | ||
f5a1b0d2 | 1927 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
2b835d68 RE |
1928 | return 1; |
1929 | } | |
f5a1b0d2 | 1930 | |
2b835d68 RE |
1931 | return 0; |
1932 | } | |
d5b7b3ae | 1933 | #endif /* not ARM_WINCE */ |
f5a1b0d2 | 1934 | |
d5b7b3ae | 1935 | /* Return all other types in memory. */ |
2b835d68 RE |
1936 | return 1; |
1937 | } | |
1938 | ||
3717da94 JT |
1939 | /* Indicate whether or not words of a double are in big-endian order. */ |
1940 | ||
1941 | int | |
e32bac5b | 1942 | arm_float_words_big_endian (void) |
3717da94 | 1943 | { |
9b6b54e2 NC |
1944 | if (TARGET_CIRRUS) |
1945 | return 0; | |
3717da94 JT |
1946 | |
1947 | /* For FPA, float words are always big-endian. For VFP, floats words | |
1948 | follow the memory system mode. */ | |
1949 | ||
1950 | if (TARGET_HARD_FLOAT) | |
1951 | { | |
1952 | /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */ | |
1953 | return 1; | |
1954 | } | |
1955 | ||
1956 | if (TARGET_VFP) | |
1957 | return (TARGET_BIG_END ? 1 : 0); | |
1958 | ||
1959 | return 1; | |
1960 | } | |
1961 | ||
82e9d970 PB |
1962 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1963 | for a call to a function whose data type is FNTYPE. | |
1964 | For a library call, FNTYPE is NULL. */ | |
1965 | void | |
e32bac5b RE |
1966 | arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, |
1967 | rtx libname ATTRIBUTE_UNUSED, | |
1968 | tree fndecl ATTRIBUTE_UNUSED) | |
82e9d970 PB |
1969 | { |
1970 | /* On the ARM, the offset starts at 0. */ | |
c27ba912 | 1971 | pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0); |
5a9335ef | 1972 | pcum->iwmmxt_nregs = 0; |
c27ba912 | 1973 | |
82e9d970 PB |
1974 | pcum->call_cookie = CALL_NORMAL; |
1975 | ||
1976 | if (TARGET_LONG_CALLS) | |
1977 | pcum->call_cookie = CALL_LONG; | |
1978 | ||
1979 | /* Check for long call/short call attributes. The attributes | |
1980 | override any command line option. */ | |
1981 | if (fntype) | |
1982 | { | |
1983 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype))) | |
1984 | pcum->call_cookie = CALL_SHORT; | |
1985 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype))) | |
1986 | pcum->call_cookie = CALL_LONG; | |
1987 | } | |
5a9335ef NC |
1988 | |
1989 | /* Varargs vectors are treated the same as long long. | |
1990 | named_count avoids having to change the way arm handles 'named' */ | |
1991 | pcum->named_count = 0; | |
1992 | pcum->nargs = 0; | |
1993 | ||
1994 | if (TARGET_REALLY_IWMMXT && fntype) | |
1995 | { | |
1996 | tree fn_arg; | |
1997 | ||
1998 | for (fn_arg = TYPE_ARG_TYPES (fntype); | |
1999 | fn_arg; | |
2000 | fn_arg = TREE_CHAIN (fn_arg)) | |
2001 | pcum->named_count += 1; | |
2002 | ||
2003 | if (! pcum->named_count) | |
2004 | pcum->named_count = INT_MAX; | |
2005 | } | |
82e9d970 PB |
2006 | } |
2007 | ||
2008 | /* Determine where to put an argument to a function. | |
2009 | Value is zero to push the argument on the stack, | |
2010 | or a hard register in which to store the argument. | |
2011 | ||
2012 | MODE is the argument's machine mode. | |
2013 | TYPE is the data type of the argument (as a tree). | |
2014 | This is null for libcalls where that information may | |
2015 | not be available. | |
2016 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2017 | the preceding args and about the function being called. | |
2018 | NAMED is nonzero if this argument is a named parameter | |
2019 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1d6e90ac | 2020 | |
82e9d970 | 2021 | rtx |
e32bac5b RE |
2022 | arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
2023 | tree type ATTRIBUTE_UNUSED, int named) | |
82e9d970 | 2024 | { |
5a9335ef NC |
2025 | if (TARGET_REALLY_IWMMXT) |
2026 | { | |
2027 | if (VECTOR_MODE_SUPPORTED_P (mode)) | |
2028 | { | |
2029 | /* varargs vectors are treated the same as long long. | |
2030 | named_count avoids having to change the way arm handles 'named' */ | |
2031 | if (pcum->named_count <= pcum->nargs + 1) | |
2032 | { | |
2033 | if (pcum->nregs == 1) | |
2034 | pcum->nregs += 1; | |
2035 | if (pcum->nregs <= 2) | |
2036 | return gen_rtx_REG (mode, pcum->nregs); | |
2037 | else | |
2038 | return NULL_RTX; | |
2039 | } | |
2040 | else if (pcum->iwmmxt_nregs <= 9) | |
2041 | return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); | |
2042 | else | |
2043 | return NULL_RTX; | |
2044 | } | |
2045 | else if ((mode == DImode || mode == DFmode) && pcum->nregs & 1) | |
2046 | pcum->nregs += 1; | |
2047 | } | |
2048 | ||
82e9d970 PB |
2049 | if (mode == VOIDmode) |
2050 | /* Compute operand 2 of the call insn. */ | |
2051 | return GEN_INT (pcum->call_cookie); | |
2052 | ||
5895f793 | 2053 | if (!named || pcum->nregs >= NUM_ARG_REGS) |
82e9d970 PB |
2054 | return NULL_RTX; |
2055 | ||
2056 | return gen_rtx_REG (mode, pcum->nregs); | |
2057 | } | |
1741620c JD |
2058 | |
2059 | /* Variable sized types are passed by reference. This is a GCC | |
2060 | extension to the ARM ABI. */ | |
2061 | ||
2062 | int | |
e32bac5b RE |
2063 | arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
2064 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
2065 | tree type, int named ATTRIBUTE_UNUSED) | |
1741620c JD |
2066 | { |
2067 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
2068 | } | |
2069 | ||
2070 | /* Implement va_arg. */ | |
2071 | ||
2072 | rtx | |
e32bac5b | 2073 | arm_va_arg (tree valist, tree type) |
1741620c JD |
2074 | { |
2075 | /* Variable sized types are passed by reference. */ | |
2076 | if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) | |
2077 | { | |
2078 | rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type)); | |
2079 | return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr)); | |
2080 | } | |
2081 | ||
5a9335ef NC |
2082 | if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), NULL) == IWMMXT_ALIGNMENT) |
2083 | { | |
2084 | tree minus_eight; | |
2085 | tree t; | |
2086 | ||
2087 | /* Maintain 64-bit alignment of the valist pointer by | |
2088 | contructing: valist = ((valist + (8 - 1)) & -8). */ | |
2089 | minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1); | |
2090 | t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0); | |
2091 | t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t); | |
2092 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, minus_eight); | |
2093 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t); | |
2094 | TREE_SIDE_EFFECTS (t) = 1; | |
2095 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2096 | ||
f1ba665b | 2097 | /* This is to stop the combine pass optimizing |
5a9335ef NC |
2098 | away the alignment adjustment. */ |
2099 | mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); | |
2100 | } | |
2101 | ||
1741620c JD |
2102 | return std_expand_builtin_va_arg (valist, type); |
2103 | } | |
82e9d970 | 2104 | \f |
c27ba912 DM |
2105 | /* Encode the current state of the #pragma [no_]long_calls. */ |
2106 | typedef enum | |
82e9d970 | 2107 | { |
c27ba912 DM |
2108 | OFF, /* No #pramgma [no_]long_calls is in effect. */ |
2109 | LONG, /* #pragma long_calls is in effect. */ | |
2110 | SHORT /* #pragma no_long_calls is in effect. */ | |
2111 | } arm_pragma_enum; | |
82e9d970 | 2112 | |
c27ba912 | 2113 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 2114 | |
8b97c5f8 | 2115 | void |
e32bac5b | 2116 | arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
82e9d970 | 2117 | { |
8b97c5f8 ZW |
2118 | arm_pragma_long_calls = LONG; |
2119 | } | |
2120 | ||
2121 | void | |
e32bac5b | 2122 | arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
2123 | { |
2124 | arm_pragma_long_calls = SHORT; | |
2125 | } | |
2126 | ||
2127 | void | |
e32bac5b | 2128 | arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
2129 | { |
2130 | arm_pragma_long_calls = OFF; | |
82e9d970 PB |
2131 | } |
2132 | \f | |
91d231cb JM |
2133 | /* Table of machine attributes. */ |
2134 | const struct attribute_spec arm_attribute_table[] = | |
82e9d970 | 2135 | { |
91d231cb | 2136 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
82e9d970 PB |
2137 | /* Function calls made to this symbol must be done indirectly, because |
2138 | it may lie outside of the 26 bit addressing range of a normal function | |
2139 | call. */ | |
91d231cb | 2140 | { "long_call", 0, 0, false, true, true, NULL }, |
82e9d970 PB |
2141 | /* Whereas these functions are always known to reside within the 26 bit |
2142 | addressing range. */ | |
91d231cb | 2143 | { "short_call", 0, 0, false, true, true, NULL }, |
6d3d9133 | 2144 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
91d231cb JM |
2145 | { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, |
2146 | { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, | |
2147 | { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
2148 | #ifdef ARM_PE | |
2149 | /* ARM/PE has three new attributes: | |
2150 | interfacearm - ? | |
2151 | dllexport - for exporting a function/variable that will live in a dll | |
2152 | dllimport - for importing a function/variable from a dll | |
2153 | ||
2154 | Microsoft allows multiple declspecs in one __declspec, separating | |
2155 | them with spaces. We do NOT support this. Instead, use __declspec | |
2156 | multiple times. | |
2157 | */ | |
2158 | { "dllimport", 0, 0, true, false, false, NULL }, | |
2159 | { "dllexport", 0, 0, true, false, false, NULL }, | |
2160 | { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
2161 | #endif | |
2162 | { NULL, 0, 0, false, false, false, NULL } | |
2163 | }; | |
6d3d9133 | 2164 | |
91d231cb JM |
2165 | /* Handle an attribute requiring a FUNCTION_DECL; |
2166 | arguments as in struct attribute_spec.handler. */ | |
2167 | static tree | |
e32bac5b RE |
2168 | arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, |
2169 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
2170 | { |
2171 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
2172 | { | |
2173 | warning ("`%s' attribute only applies to functions", | |
2174 | IDENTIFIER_POINTER (name)); | |
2175 | *no_add_attrs = true; | |
2176 | } | |
2177 | ||
2178 | return NULL_TREE; | |
2179 | } | |
2180 | ||
2181 | /* Handle an "interrupt" or "isr" attribute; | |
2182 | arguments as in struct attribute_spec.handler. */ | |
2183 | static tree | |
e32bac5b RE |
2184 | arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, |
2185 | bool *no_add_attrs) | |
91d231cb JM |
2186 | { |
2187 | if (DECL_P (*node)) | |
2188 | { | |
2189 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
2190 | { | |
2191 | warning ("`%s' attribute only applies to functions", | |
2192 | IDENTIFIER_POINTER (name)); | |
2193 | *no_add_attrs = true; | |
2194 | } | |
2195 | /* FIXME: the argument if any is checked for type attributes; | |
2196 | should it be checked for decl ones? */ | |
2197 | } | |
2198 | else | |
2199 | { | |
2200 | if (TREE_CODE (*node) == FUNCTION_TYPE | |
2201 | || TREE_CODE (*node) == METHOD_TYPE) | |
2202 | { | |
2203 | if (arm_isr_value (args) == ARM_FT_UNKNOWN) | |
2204 | { | |
2205 | warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); | |
2206 | *no_add_attrs = true; | |
2207 | } | |
2208 | } | |
2209 | else if (TREE_CODE (*node) == POINTER_TYPE | |
2210 | && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE | |
2211 | || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) | |
2212 | && arm_isr_value (args) != ARM_FT_UNKNOWN) | |
2213 | { | |
2214 | *node = build_type_copy (*node); | |
1d6e90ac NC |
2215 | TREE_TYPE (*node) = build_type_attribute_variant |
2216 | (TREE_TYPE (*node), | |
2217 | tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); | |
91d231cb JM |
2218 | *no_add_attrs = true; |
2219 | } | |
2220 | else | |
2221 | { | |
2222 | /* Possibly pass this attribute on from the type to a decl. */ | |
2223 | if (flags & ((int) ATTR_FLAG_DECL_NEXT | |
2224 | | (int) ATTR_FLAG_FUNCTION_NEXT | |
2225 | | (int) ATTR_FLAG_ARRAY_NEXT)) | |
2226 | { | |
2227 | *no_add_attrs = true; | |
2228 | return tree_cons (name, args, NULL_TREE); | |
2229 | } | |
2230 | else | |
2231 | { | |
2232 | warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); | |
2233 | } | |
2234 | } | |
2235 | } | |
2236 | ||
2237 | return NULL_TREE; | |
82e9d970 PB |
2238 | } |
2239 | ||
2240 | /* Return 0 if the attributes for two types are incompatible, 1 if they | |
2241 | are compatible, and 2 if they are nearly compatible (which causes a | |
2242 | warning to be generated). */ | |
8d8e52be | 2243 | static int |
e32bac5b | 2244 | arm_comp_type_attributes (tree type1, tree type2) |
82e9d970 | 2245 | { |
1cb8d58a | 2246 | int l1, l2, s1, s2; |
bd7fc26f | 2247 | |
82e9d970 PB |
2248 | /* Check for mismatch of non-default calling convention. */ |
2249 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
2250 | return 1; | |
2251 | ||
2252 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
2253 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
2254 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
2255 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
2256 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
2257 | |
2258 | /* Only bother to check if an attribute is defined. */ | |
2259 | if (l1 | l2 | s1 | s2) | |
2260 | { | |
2261 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 2262 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 2263 | return 0; |
82e9d970 | 2264 | |
bd7fc26f NC |
2265 | /* Disallow mixed attributes. */ |
2266 | if ((l1 & s2) || (l2 & s1)) | |
2267 | return 0; | |
2268 | } | |
2269 | ||
6d3d9133 NC |
2270 | /* Check for mismatched ISR attribute. */ |
2271 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
2272 | if (! l1) | |
2273 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
2274 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
2275 | if (! l2) | |
2276 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
2277 | if (l1 != l2) | |
2278 | return 0; | |
2279 | ||
bd7fc26f | 2280 | return 1; |
82e9d970 PB |
2281 | } |
2282 | ||
c27ba912 DM |
2283 | /* Encode long_call or short_call attribute by prefixing |
2284 | symbol name in DECL with a special character FLAG. */ | |
2285 | void | |
e32bac5b | 2286 | arm_encode_call_attribute (tree decl, int flag) |
c27ba912 | 2287 | { |
3cce094d | 2288 | const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0); |
6354dc9b | 2289 | int len = strlen (str); |
d19fb8e3 | 2290 | char * newstr; |
c27ba912 | 2291 | |
c27ba912 DM |
2292 | /* Do not allow weak functions to be treated as short call. */ |
2293 | if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR) | |
2294 | return; | |
c27ba912 | 2295 | |
520a57c8 ZW |
2296 | newstr = alloca (len + 2); |
2297 | newstr[0] = flag; | |
2298 | strcpy (newstr + 1, str); | |
c27ba912 | 2299 | |
6d3d9133 | 2300 | newstr = (char *) ggc_alloc_string (newstr, len + 1); |
c27ba912 DM |
2301 | XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; |
2302 | } | |
2303 | ||
2304 | /* Assigns default attributes to newly defined type. This is used to | |
2305 | set short_call/long_call attributes for function types of | |
2306 | functions defined inside corresponding #pragma scopes. */ | |
8d8e52be | 2307 | static void |
e32bac5b | 2308 | arm_set_default_type_attributes (tree type) |
c27ba912 DM |
2309 | { |
2310 | /* Add __attribute__ ((long_call)) to all functions, when | |
2311 | inside #pragma long_calls or __attribute__ ((short_call)), | |
2312 | when inside #pragma no_long_calls. */ | |
2313 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
2314 | { | |
2315 | tree type_attr_list, attr_name; | |
2316 | type_attr_list = TYPE_ATTRIBUTES (type); | |
2317 | ||
2318 | if (arm_pragma_long_calls == LONG) | |
2319 | attr_name = get_identifier ("long_call"); | |
2320 | else if (arm_pragma_long_calls == SHORT) | |
2321 | attr_name = get_identifier ("short_call"); | |
2322 | else | |
2323 | return; | |
2324 | ||
2325 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
2326 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
2327 | } | |
2328 | } | |
2329 | \f | |
2330 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be | |
6bc82793 | 2331 | defined within the current compilation unit. If this cannot be |
c27ba912 DM |
2332 | determined, then 0 is returned. */ |
2333 | static int | |
e32bac5b | 2334 | current_file_function_operand (rtx sym_ref) |
c27ba912 DM |
2335 | { |
2336 | /* This is a bit of a fib. A function will have a short call flag | |
2337 | applied to its name if it has the short call attribute, or it has | |
2338 | already been defined within the current compilation unit. */ | |
2339 | if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0))) | |
2340 | return 1; | |
2341 | ||
6d77b53e | 2342 | /* The current function is always defined within the current compilation |
d6a7951f JM |
2343 | unit. if it s a weak definition however, then this may not be the real |
2344 | definition of the function, and so we have to say no. */ | |
c27ba912 | 2345 | if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0) |
5895f793 | 2346 | && !DECL_WEAK (current_function_decl)) |
c27ba912 DM |
2347 | return 1; |
2348 | ||
2349 | /* We cannot make the determination - default to returning 0. */ | |
2350 | return 0; | |
2351 | } | |
2352 | ||
825dda42 | 2353 | /* Return nonzero if a 32 bit "long_call" should be generated for |
c27ba912 DM |
2354 | this call. We generate a long_call if the function: |
2355 | ||
2356 | a. has an __attribute__((long call)) | |
2357 | or b. is within the scope of a #pragma long_calls | |
2358 | or c. the -mlong-calls command line switch has been specified | |
2359 | ||
2360 | However we do not generate a long call if the function: | |
2361 | ||
2362 | d. has an __attribute__ ((short_call)) | |
2363 | or e. is inside the scope of a #pragma no_long_calls | |
2364 | or f. has an __attribute__ ((section)) | |
2365 | or g. is defined within the current compilation unit. | |
2366 | ||
2367 | This function will be called by C fragments contained in the machine | |
2368 | description file. CALL_REF and CALL_COOKIE correspond to the matched | |
2369 | rtl operands. CALL_SYMBOL is used to distinguish between | |
2370 | two different callers of the function. It is set to 1 in the | |
2371 | "call_symbol" and "call_symbol_value" patterns and to 0 in the "call" | |
2372 | and "call_value" patterns. This is because of the difference in the | |
2373 | SYM_REFs passed by these patterns. */ | |
2374 | int | |
e32bac5b | 2375 | arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol) |
c27ba912 | 2376 | { |
5895f793 | 2377 | if (!call_symbol) |
c27ba912 DM |
2378 | { |
2379 | if (GET_CODE (sym_ref) != MEM) | |
2380 | return 0; | |
2381 | ||
2382 | sym_ref = XEXP (sym_ref, 0); | |
2383 | } | |
2384 | ||
2385 | if (GET_CODE (sym_ref) != SYMBOL_REF) | |
2386 | return 0; | |
2387 | ||
2388 | if (call_cookie & CALL_SHORT) | |
2389 | return 0; | |
2390 | ||
2391 | if (TARGET_LONG_CALLS && flag_function_sections) | |
2392 | return 1; | |
2393 | ||
87e27392 | 2394 | if (current_file_function_operand (sym_ref)) |
c27ba912 DM |
2395 | return 0; |
2396 | ||
2397 | return (call_cookie & CALL_LONG) | |
2398 | || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0)) | |
2399 | || TARGET_LONG_CALLS; | |
2400 | } | |
f99fce0c | 2401 | |
825dda42 | 2402 | /* Return nonzero if it is ok to make a tail-call to DECL. */ |
4977bab6 | 2403 | static bool |
e32bac5b | 2404 | arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
f99fce0c RE |
2405 | { |
2406 | int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL; | |
2407 | ||
5a9335ef NC |
2408 | if (cfun->machine->sibcall_blocked) |
2409 | return false; | |
2410 | ||
f99fce0c RE |
2411 | /* Never tailcall something for which we have no decl, or if we |
2412 | are in Thumb mode. */ | |
2413 | if (decl == NULL || TARGET_THUMB) | |
4977bab6 | 2414 | return false; |
f99fce0c RE |
2415 | |
2416 | /* Get the calling method. */ | |
2417 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
2418 | call_type = CALL_SHORT; | |
2419 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
2420 | call_type = CALL_LONG; | |
2421 | ||
2422 | /* Cannot tail-call to long calls, since these are out of range of | |
2423 | a branch instruction. However, if not compiling PIC, we know | |
2424 | we can reach the symbol if it is in this compilation unit. */ | |
5895f793 | 2425 | if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl))) |
4977bab6 | 2426 | return false; |
f99fce0c RE |
2427 | |
2428 | /* If we are interworking and the function is not declared static | |
2429 | then we can't tail-call it unless we know that it exists in this | |
2430 | compilation unit (since it might be a Thumb routine). */ | |
5895f793 | 2431 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
4977bab6 | 2432 | return false; |
f99fce0c | 2433 | |
6d3d9133 NC |
2434 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
2435 | if (IS_INTERRUPT (arm_current_func_type ())) | |
4977bab6 | 2436 | return false; |
6d3d9133 | 2437 | |
f99fce0c | 2438 | /* Everything else is ok. */ |
4977bab6 | 2439 | return true; |
f99fce0c RE |
2440 | } |
2441 | ||
82e9d970 | 2442 | \f |
6b990f6b RE |
2443 | /* Addressing mode support functions. */ |
2444 | ||
0b4be7de | 2445 | /* Return nonzero if X is a legitimate immediate operand when compiling |
6b990f6b | 2446 | for PIC. */ |
32de079a | 2447 | int |
e32bac5b | 2448 | legitimate_pic_operand_p (rtx x) |
32de079a | 2449 | { |
d5b7b3ae RE |
2450 | if (CONSTANT_P (x) |
2451 | && flag_pic | |
32de079a RE |
2452 | && (GET_CODE (x) == SYMBOL_REF |
2453 | || (GET_CODE (x) == CONST | |
2454 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2455 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))) | |
2456 | return 0; | |
2457 | ||
2458 | return 1; | |
2459 | } | |
2460 | ||
2461 | rtx | |
e32bac5b | 2462 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
32de079a | 2463 | { |
a3c48721 RE |
2464 | if (GET_CODE (orig) == SYMBOL_REF |
2465 | || GET_CODE (orig) == LABEL_REF) | |
32de079a | 2466 | { |
5f37d07c | 2467 | #ifndef AOF_ASSEMBLER |
32de079a | 2468 | rtx pic_ref, address; |
5f37d07c | 2469 | #endif |
32de079a RE |
2470 | rtx insn; |
2471 | int subregs = 0; | |
2472 | ||
2473 | if (reg == 0) | |
2474 | { | |
893f3d5b | 2475 | if (no_new_pseudos) |
32de079a RE |
2476 | abort (); |
2477 | else | |
2478 | reg = gen_reg_rtx (Pmode); | |
2479 | ||
2480 | subregs = 1; | |
2481 | } | |
2482 | ||
2483 | #ifdef AOF_ASSEMBLER | |
2484 | /* The AOF assembler can generate relocations for these directly, and | |
6354dc9b | 2485 | understands that the PIC register has to be added into the offset. */ |
32de079a RE |
2486 | insn = emit_insn (gen_pic_load_addr_based (reg, orig)); |
2487 | #else | |
2488 | if (subregs) | |
2489 | address = gen_reg_rtx (Pmode); | |
2490 | else | |
2491 | address = reg; | |
2492 | ||
4bec9f7d NC |
2493 | if (TARGET_ARM) |
2494 | emit_insn (gen_pic_load_addr_arm (address, orig)); | |
2495 | else | |
2496 | emit_insn (gen_pic_load_addr_thumb (address, orig)); | |
32de079a | 2497 | |
14f583b8 PB |
2498 | if ((GET_CODE (orig) == LABEL_REF |
2499 | || (GET_CODE (orig) == SYMBOL_REF && | |
2500 | ENCODED_SHORT_CALL_ATTR_P (XSTR (orig, 0)))) | |
2501 | && NEED_GOT_RELOC) | |
a3c48721 RE |
2502 | pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address); |
2503 | else | |
2504 | { | |
2505 | pic_ref = gen_rtx_MEM (Pmode, | |
2506 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
2507 | address)); | |
2508 | RTX_UNCHANGING_P (pic_ref) = 1; | |
2509 | } | |
2510 | ||
32de079a RE |
2511 | insn = emit_move_insn (reg, pic_ref); |
2512 | #endif | |
2513 | current_function_uses_pic_offset_table = 1; | |
2514 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2515 | by loop. */ | |
43cffd11 RE |
2516 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, |
2517 | REG_NOTES (insn)); | |
32de079a RE |
2518 | return reg; |
2519 | } | |
2520 | else if (GET_CODE (orig) == CONST) | |
2521 | { | |
2522 | rtx base, offset; | |
2523 | ||
2524 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
2525 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2526 | return orig; | |
2527 | ||
2528 | if (reg == 0) | |
2529 | { | |
893f3d5b | 2530 | if (no_new_pseudos) |
32de079a RE |
2531 | abort (); |
2532 | else | |
2533 | reg = gen_reg_rtx (Pmode); | |
2534 | } | |
2535 | ||
2536 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
2537 | { | |
2538 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
2539 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2540 | base == reg ? 0 : reg); | |
2541 | } | |
2542 | else | |
2543 | abort (); | |
2544 | ||
2545 | if (GET_CODE (offset) == CONST_INT) | |
2546 | { | |
2547 | /* The base register doesn't really matter, we only want to | |
2548 | test the index for the appropriate mode. */ | |
6b990f6b RE |
2549 | if (!arm_legitimate_index_p (mode, offset, 0)) |
2550 | { | |
2551 | if (!no_new_pseudos) | |
2552 | offset = force_reg (Pmode, offset); | |
2553 | else | |
2554 | abort (); | |
2555 | } | |
32de079a | 2556 | |
32de079a | 2557 | if (GET_CODE (offset) == CONST_INT) |
ed8908e7 | 2558 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
2559 | } |
2560 | ||
2561 | if (GET_MODE_SIZE (mode) > 4 | |
2562 | && (GET_MODE_CLASS (mode) == MODE_INT | |
2563 | || TARGET_SOFT_FLOAT)) | |
2564 | { | |
2565 | emit_insn (gen_addsi3 (reg, base, offset)); | |
2566 | return reg; | |
2567 | } | |
2568 | ||
43cffd11 | 2569 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a | 2570 | } |
32de079a RE |
2571 | |
2572 | return orig; | |
2573 | } | |
2574 | ||
c1163e75 PB |
2575 | /* Generate code to load the PIC register. PROLOGUE is true if |
2576 | called from arm_expand_prologue (in which case we want the | |
2577 | generated insns at the start of the function); false if called | |
2578 | by an exception receiver that needs the PIC register reloaded | |
2579 | (in which case the insns are just dumped at the current location). */ | |
32de079a | 2580 | void |
e32bac5b | 2581 | arm_finalize_pic (int prologue ATTRIBUTE_UNUSED) |
32de079a RE |
2582 | { |
2583 | #ifndef AOF_ASSEMBLER | |
c1163e75 | 2584 | rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx; |
32de079a RE |
2585 | rtx global_offset_table; |
2586 | ||
ed0e6530 | 2587 | if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
2588 | return; |
2589 | ||
5895f793 | 2590 | if (!flag_pic) |
32de079a RE |
2591 | abort (); |
2592 | ||
2593 | start_sequence (); | |
2594 | l1 = gen_label_rtx (); | |
2595 | ||
43cffd11 | 2596 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); |
dfa08768 | 2597 | /* On the ARM the PC register contains 'dot + 8' at the time of the |
d5b7b3ae RE |
2598 | addition, on the Thumb it is 'dot + 4'. */ |
2599 | pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4); | |
84306176 PB |
2600 | if (GOT_PCREL) |
2601 | pic_tmp2 = gen_rtx_CONST (VOIDmode, | |
43cffd11 | 2602 | gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); |
84306176 PB |
2603 | else |
2604 | pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); | |
43cffd11 RE |
2605 | |
2606 | pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); | |
f5a1b0d2 | 2607 | |
d5b7b3ae | 2608 | if (TARGET_ARM) |
4bec9f7d NC |
2609 | { |
2610 | emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx)); | |
2611 | emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1)); | |
2612 | } | |
d5b7b3ae | 2613 | else |
4bec9f7d NC |
2614 | { |
2615 | emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx)); | |
2616 | emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1)); | |
2617 | } | |
32de079a | 2618 | |
2f937369 | 2619 | seq = get_insns (); |
32de079a | 2620 | end_sequence (); |
c1163e75 PB |
2621 | if (prologue) |
2622 | emit_insn_after (seq, get_insns ()); | |
2623 | else | |
2624 | emit_insn (seq); | |
32de079a RE |
2625 | |
2626 | /* Need to emit this whether or not we obey regdecls, | |
2627 | since setjmp/longjmp can cause life info to screw up. */ | |
43cffd11 | 2628 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
32de079a RE |
2629 | #endif /* AOF_ASSEMBLER */ |
2630 | } | |
2631 | ||
6b990f6b RE |
2632 | /* Return nonzero if X is valid as an ARM state addressing register. */ |
2633 | static int | |
e32bac5b | 2634 | arm_address_register_rtx_p (rtx x, int strict_p) |
6b990f6b RE |
2635 | { |
2636 | int regno; | |
2637 | ||
2638 | if (GET_CODE (x) != REG) | |
2639 | return 0; | |
2640 | ||
2641 | regno = REGNO (x); | |
2642 | ||
2643 | if (strict_p) | |
2644 | return ARM_REGNO_OK_FOR_BASE_P (regno); | |
2645 | ||
2646 | return (regno <= LAST_ARM_REGNUM | |
2647 | || regno >= FIRST_PSEUDO_REGISTER | |
2648 | || regno == FRAME_POINTER_REGNUM | |
2649 | || regno == ARG_POINTER_REGNUM); | |
2650 | } | |
2651 | ||
2652 | /* Return nonzero if X is a valid ARM state address operand. */ | |
2653 | int | |
e32bac5b | 2654 | arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
6b990f6b RE |
2655 | { |
2656 | if (arm_address_register_rtx_p (x, strict_p)) | |
2657 | return 1; | |
2658 | ||
2659 | else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC) | |
2660 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); | |
2661 | ||
2662 | else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY) | |
2663 | && GET_MODE_SIZE (mode) <= 4 | |
2664 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) | |
2665 | && GET_CODE (XEXP (x, 1)) == PLUS | |
2666 | && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) | |
2667 | return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p); | |
2668 | ||
2669 | /* After reload constants split into minipools will have addresses | |
2670 | from a LABEL_REF. */ | |
2671 | else if (GET_MODE_SIZE (mode) >= 4 && reload_completed | |
2672 | && (GET_CODE (x) == LABEL_REF | |
2673 | || (GET_CODE (x) == CONST | |
2674 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2675 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
2676 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
2677 | return 1; | |
2678 | ||
2679 | else if (mode == TImode) | |
2680 | return 0; | |
2681 | ||
2682 | else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode)) | |
2683 | { | |
2684 | if (GET_CODE (x) == PLUS | |
2685 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) | |
2686 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2687 | { | |
2688 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
2689 | ||
2690 | if (val == 4 || val == -4 || val == -8) | |
2691 | return 1; | |
2692 | } | |
2693 | } | |
2694 | ||
2695 | else if (GET_CODE (x) == PLUS) | |
2696 | { | |
2697 | rtx xop0 = XEXP (x, 0); | |
2698 | rtx xop1 = XEXP (x, 1); | |
2699 | ||
2700 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
2701 | && arm_legitimate_index_p (mode, xop1, strict_p)) | |
2702 | || (arm_address_register_rtx_p (xop1, strict_p) | |
2703 | && arm_legitimate_index_p (mode, xop0, strict_p))); | |
2704 | } | |
2705 | ||
2706 | #if 0 | |
2707 | /* Reload currently can't handle MINUS, so disable this for now */ | |
2708 | else if (GET_CODE (x) == MINUS) | |
2709 | { | |
2710 | rtx xop0 = XEXP (x, 0); | |
2711 | rtx xop1 = XEXP (x, 1); | |
2712 | ||
2713 | return (arm_address_register_rtx_p (xop0, strict_p) | |
2714 | && arm_legitimate_index_p (mode, xop1, strict_p)); | |
2715 | } | |
2716 | #endif | |
2717 | ||
2718 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
2719 | && GET_CODE (x) == SYMBOL_REF | |
2720 | && CONSTANT_POOL_ADDRESS_P (x) | |
2721 | && ! (flag_pic | |
2722 | && symbol_mentioned_p (get_pool_constant (x)))) | |
2723 | return 1; | |
2724 | ||
2725 | else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC) | |
2726 | && (GET_MODE_SIZE (mode) <= 4) | |
2727 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p)) | |
2728 | return 1; | |
2729 | ||
2730 | return 0; | |
2731 | } | |
2732 | ||
2733 | /* Return nonzero if INDEX is valid for an address index operand in | |
2734 | ARM state. */ | |
2735 | static int | |
e32bac5b | 2736 | arm_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) |
6b990f6b RE |
2737 | { |
2738 | HOST_WIDE_INT range; | |
2739 | enum rtx_code code = GET_CODE (index); | |
2740 | ||
2741 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2742 | return (code == CONST_INT && INTVAL (index) < 1024 | |
2743 | && INTVAL (index) > -1024 | |
2744 | && (INTVAL (index) & 3) == 0); | |
2745 | ||
9b6b54e2 NC |
2746 | if (TARGET_CIRRUS |
2747 | && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode)) | |
2748 | return (code == CONST_INT | |
2749 | && INTVAL (index) < 255 | |
2750 | && INTVAL (index) > -255); | |
2751 | ||
6b990f6b RE |
2752 | if (arm_address_register_rtx_p (index, strict_p) |
2753 | && GET_MODE_SIZE (mode) <= 4) | |
2754 | return 1; | |
2755 | ||
5a9335ef NC |
2756 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) |
2757 | return (code == CONST_INT | |
2758 | && INTVAL (index) < 256 | |
2759 | && INTVAL (index) > -256); | |
2760 | ||
6b990f6b RE |
2761 | /* XXX What about ldrsb? */ |
2762 | if (GET_MODE_SIZE (mode) <= 4 && code == MULT | |
2763 | && (!arm_arch4 || (mode) != HImode)) | |
2764 | { | |
2765 | rtx xiop0 = XEXP (index, 0); | |
2766 | rtx xiop1 = XEXP (index, 1); | |
2767 | ||
2768 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
2769 | && power_of_two_operand (xiop1, SImode)) | |
2770 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
2771 | && power_of_two_operand (xiop0, SImode))); | |
2772 | } | |
2773 | ||
2774 | if (GET_MODE_SIZE (mode) <= 4 | |
2775 | && (code == LSHIFTRT || code == ASHIFTRT | |
2776 | || code == ASHIFT || code == ROTATERT) | |
2777 | && (!arm_arch4 || (mode) != HImode)) | |
2778 | { | |
2779 | rtx op = XEXP (index, 1); | |
2780 | ||
2781 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) | |
2782 | && GET_CODE (op) == CONST_INT | |
2783 | && INTVAL (op) > 0 | |
2784 | && INTVAL (op) <= 31); | |
2785 | } | |
2786 | ||
2787 | /* XXX For ARM v4 we may be doing a sign-extend operation during the | |
2788 | load, but that has a restricted addressing range and we are unable | |
2789 | to tell here whether that is the case. To be safe we restrict all | |
2790 | loads to that range. */ | |
2791 | range = ((mode) == HImode || (mode) == QImode) | |
2792 | ? (arm_arch4 ? 256 : 4095) : 4096; | |
2793 | ||
2794 | return (code == CONST_INT | |
2795 | && INTVAL (index) < range | |
2796 | && INTVAL (index) > -range); | |
76a318e9 RE |
2797 | } |
2798 | ||
2799 | /* Return nonzero if X is valid as an ARM state addressing register. */ | |
2800 | static int | |
e32bac5b | 2801 | thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) |
76a318e9 RE |
2802 | { |
2803 | int regno; | |
2804 | ||
2805 | if (GET_CODE (x) != REG) | |
2806 | return 0; | |
2807 | ||
2808 | regno = REGNO (x); | |
2809 | ||
2810 | if (strict_p) | |
2811 | return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode); | |
2812 | ||
2813 | return (regno <= LAST_LO_REGNUM | |
2814 | || regno >= FIRST_PSEUDO_REGISTER | |
2815 | || regno == FRAME_POINTER_REGNUM | |
2816 | || (GET_MODE_SIZE (mode) >= 4 | |
2817 | && (regno == STACK_POINTER_REGNUM | |
2818 | || x == hard_frame_pointer_rtx | |
2819 | || x == arg_pointer_rtx))); | |
2820 | } | |
2821 | ||
2822 | /* Return nonzero if x is a legitimate index register. This is the case | |
2823 | for any base register that can access a QImode object. */ | |
2824 | inline static int | |
e32bac5b | 2825 | thumb_index_register_rtx_p (rtx x, int strict_p) |
76a318e9 RE |
2826 | { |
2827 | return thumb_base_register_rtx_p (x, QImode, strict_p); | |
2828 | } | |
2829 | ||
2830 | /* Return nonzero if x is a legitimate Thumb-state address. | |
2831 | ||
2832 | The AP may be eliminated to either the SP or the FP, so we use the | |
2833 | least common denominator, e.g. SImode, and offsets from 0 to 64. | |
2834 | ||
2835 | ??? Verify whether the above is the right approach. | |
2836 | ||
2837 | ??? Also, the FP may be eliminated to the SP, so perhaps that | |
2838 | needs special handling also. | |
2839 | ||
2840 | ??? Look at how the mips16 port solves this problem. It probably uses | |
2841 | better ways to solve some of these problems. | |
2842 | ||
2843 | Although it is not incorrect, we don't accept QImode and HImode | |
2844 | addresses based on the frame pointer or arg pointer until the | |
2845 | reload pass starts. This is so that eliminating such addresses | |
2846 | into stack based ones won't produce impossible code. */ | |
2847 | int | |
e32bac5b | 2848 | thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
76a318e9 RE |
2849 | { |
2850 | /* ??? Not clear if this is right. Experiment. */ | |
2851 | if (GET_MODE_SIZE (mode) < 4 | |
2852 | && !(reload_in_progress || reload_completed) | |
2853 | && (reg_mentioned_p (frame_pointer_rtx, x) | |
2854 | || reg_mentioned_p (arg_pointer_rtx, x) | |
2855 | || reg_mentioned_p (virtual_incoming_args_rtx, x) | |
2856 | || reg_mentioned_p (virtual_outgoing_args_rtx, x) | |
2857 | || reg_mentioned_p (virtual_stack_dynamic_rtx, x) | |
2858 | || reg_mentioned_p (virtual_stack_vars_rtx, x))) | |
2859 | return 0; | |
2860 | ||
2861 | /* Accept any base register. SP only in SImode or larger. */ | |
2862 | else if (thumb_base_register_rtx_p (x, mode, strict_p)) | |
2863 | return 1; | |
2864 | ||
18dbd950 | 2865 | /* This is PC relative data before arm_reorg runs. */ |
76a318e9 RE |
2866 | else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) |
2867 | && GET_CODE (x) == SYMBOL_REF | |
2868 | && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic) | |
2869 | return 1; | |
2870 | ||
18dbd950 | 2871 | /* This is PC relative data after arm_reorg runs. */ |
76a318e9 RE |
2872 | else if (GET_MODE_SIZE (mode) >= 4 && reload_completed |
2873 | && (GET_CODE (x) == LABEL_REF | |
2874 | || (GET_CODE (x) == CONST | |
2875 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2876 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
2877 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
2878 | return 1; | |
2879 | ||
2880 | /* Post-inc indexing only supported for SImode and larger. */ | |
2881 | else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 | |
2882 | && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)) | |
2883 | return 1; | |
2884 | ||
2885 | else if (GET_CODE (x) == PLUS) | |
2886 | { | |
2887 | /* REG+REG address can be any two index registers. */ | |
2888 | /* We disallow FRAME+REG addressing since we know that FRAME | |
2889 | will be replaced with STACK, and SP relative addressing only | |
2890 | permits SP+OFFSET. */ | |
2891 | if (GET_MODE_SIZE (mode) <= 4 | |
2892 | && XEXP (x, 0) != frame_pointer_rtx | |
2893 | && XEXP (x, 1) != frame_pointer_rtx | |
2894 | && XEXP (x, 0) != virtual_stack_vars_rtx | |
2895 | && XEXP (x, 1) != virtual_stack_vars_rtx | |
2896 | && thumb_index_register_rtx_p (XEXP (x, 0), strict_p) | |
2897 | && thumb_index_register_rtx_p (XEXP (x, 1), strict_p)) | |
2898 | return 1; | |
2899 | ||
2900 | /* REG+const has 5-7 bit offset for non-SP registers. */ | |
2901 | else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p) | |
2902 | || XEXP (x, 0) == arg_pointer_rtx) | |
2903 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2904 | && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
2905 | return 1; | |
2906 | ||
2907 | /* REG+const has 10 bit offset for SP, but only SImode and | |
2908 | larger is supported. */ | |
2909 | /* ??? Should probably check for DI/DFmode overflow here | |
2910 | just like GO_IF_LEGITIMATE_OFFSET does. */ | |
2911 | else if (GET_CODE (XEXP (x, 0)) == REG | |
2912 | && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM | |
2913 | && GET_MODE_SIZE (mode) >= 4 | |
2914 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2915 | && INTVAL (XEXP (x, 1)) >= 0 | |
2916 | && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 | |
2917 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
2918 | return 1; | |
2919 | ||
2920 | else if (GET_CODE (XEXP (x, 0)) == REG | |
2921 | && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM | |
2922 | && GET_MODE_SIZE (mode) >= 4 | |
2923 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2924 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
2925 | return 1; | |
2926 | } | |
2927 | ||
2928 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
2929 | && GET_CODE (x) == SYMBOL_REF | |
2930 | && CONSTANT_POOL_ADDRESS_P (x) | |
2931 | && !(flag_pic | |
2932 | && symbol_mentioned_p (get_pool_constant (x)))) | |
2933 | return 1; | |
2934 | ||
2935 | return 0; | |
2936 | } | |
2937 | ||
2938 | /* Return nonzero if VAL can be used as an offset in a Thumb-state address | |
2939 | instruction of mode MODE. */ | |
2940 | int | |
e32bac5b | 2941 | thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) |
76a318e9 RE |
2942 | { |
2943 | switch (GET_MODE_SIZE (mode)) | |
2944 | { | |
2945 | case 1: | |
2946 | return val >= 0 && val < 32; | |
2947 | ||
2948 | case 2: | |
2949 | return val >= 0 && val < 64 && (val & 1) == 0; | |
2950 | ||
2951 | default: | |
2952 | return (val >= 0 | |
2953 | && (val + GET_MODE_SIZE (mode)) <= 128 | |
2954 | && (val & 3) == 0); | |
2955 | } | |
2956 | } | |
2957 | ||
ccf4d512 RE |
2958 | /* Try machine-dependent ways of modifying an illegitimate address |
2959 | to be legitimate. If we find one, return the new, valid address. */ | |
ccf4d512 | 2960 | rtx |
e32bac5b | 2961 | arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) |
ccf4d512 RE |
2962 | { |
2963 | if (GET_CODE (x) == PLUS) | |
2964 | { | |
2965 | rtx xop0 = XEXP (x, 0); | |
2966 | rtx xop1 = XEXP (x, 1); | |
2967 | ||
2968 | if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) | |
2969 | xop0 = force_reg (SImode, xop0); | |
2970 | ||
2971 | if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) | |
2972 | xop1 = force_reg (SImode, xop1); | |
2973 | ||
2974 | if (ARM_BASE_REGISTER_RTX_P (xop0) | |
2975 | && GET_CODE (xop1) == CONST_INT) | |
2976 | { | |
2977 | HOST_WIDE_INT n, low_n; | |
2978 | rtx base_reg, val; | |
2979 | n = INTVAL (xop1); | |
2980 | ||
2981 | if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode)) | |
2982 | { | |
2983 | low_n = n & 0x0f; | |
2984 | n &= ~0x0f; | |
2985 | if (low_n > 4) | |
2986 | { | |
2987 | n += 16; | |
2988 | low_n -= 16; | |
2989 | } | |
2990 | } | |
2991 | else | |
2992 | { | |
2993 | low_n = ((mode) == TImode ? 0 | |
2994 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); | |
2995 | n -= low_n; | |
2996 | } | |
2997 | ||
2998 | base_reg = gen_reg_rtx (SImode); | |
2999 | val = force_operand (gen_rtx_PLUS (SImode, xop0, | |
3000 | GEN_INT (n)), NULL_RTX); | |
3001 | emit_move_insn (base_reg, val); | |
3002 | x = (low_n == 0 ? base_reg | |
3003 | : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); | |
3004 | } | |
3005 | else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
3006 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
3007 | } | |
3008 | ||
3009 | /* XXX We don't allow MINUS any more -- see comment in | |
3010 | arm_legitimate_address_p (). */ | |
3011 | else if (GET_CODE (x) == MINUS) | |
3012 | { | |
3013 | rtx xop0 = XEXP (x, 0); | |
3014 | rtx xop1 = XEXP (x, 1); | |
3015 | ||
3016 | if (CONSTANT_P (xop0)) | |
3017 | xop0 = force_reg (SImode, xop0); | |
3018 | ||
3019 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) | |
3020 | xop1 = force_reg (SImode, xop1); | |
3021 | ||
3022 | if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
3023 | x = gen_rtx_MINUS (SImode, xop0, xop1); | |
3024 | } | |
3025 | ||
3026 | if (flag_pic) | |
3027 | { | |
3028 | /* We need to find and carefully transform any SYMBOL and LABEL | |
3029 | references; so go back to the original address expression. */ | |
3030 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
3031 | ||
3032 | if (new_x != orig_x) | |
3033 | x = new_x; | |
3034 | } | |
3035 | ||
3036 | return x; | |
3037 | } | |
3038 | ||
6b990f6b RE |
3039 | \f |
3040 | ||
e2c671ba RE |
3041 | #define REG_OR_SUBREG_REG(X) \ |
3042 | (GET_CODE (X) == REG \ | |
3043 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
3044 | ||
3045 | #define REG_OR_SUBREG_RTX(X) \ | |
3046 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
3047 | ||
d5b7b3ae RE |
3048 | #ifndef COSTS_N_INSNS |
3049 | #define COSTS_N_INSNS(N) ((N) * 4 - 2) | |
3050 | #endif | |
e32bac5b | 3051 | /* Worker routine for arm_rtx_costs. */ |
3c50106f | 3052 | static inline int |
e32bac5b | 3053 | arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) |
e2c671ba RE |
3054 | { |
3055 | enum machine_mode mode = GET_MODE (x); | |
3056 | enum rtx_code subcode; | |
3057 | int extra_cost; | |
3058 | ||
d5b7b3ae RE |
3059 | if (TARGET_THUMB) |
3060 | { | |
3061 | switch (code) | |
3062 | { | |
3063 | case ASHIFT: | |
3064 | case ASHIFTRT: | |
3065 | case LSHIFTRT: | |
3066 | case ROTATERT: | |
3067 | case PLUS: | |
3068 | case MINUS: | |
3069 | case COMPARE: | |
3070 | case NEG: | |
3071 | case NOT: | |
3072 | return COSTS_N_INSNS (1); | |
3073 | ||
3074 | case MULT: | |
3075 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3076 | { | |
3077 | int cycles = 0; | |
3078 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); | |
3079 | ||
3080 | while (i) | |
3081 | { | |
3082 | i >>= 2; | |
5895f793 | 3083 | cycles++; |
d5b7b3ae RE |
3084 | } |
3085 | return COSTS_N_INSNS (2) + cycles; | |
3086 | } | |
3087 | return COSTS_N_INSNS (1) + 16; | |
3088 | ||
3089 | case SET: | |
3090 | return (COSTS_N_INSNS (1) | |
3091 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
3092 | + GET_CODE (SET_DEST (x)) == MEM)); | |
3093 | ||
3094 | case CONST_INT: | |
3095 | if (outer == SET) | |
3096 | { | |
3097 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
3098 | return 0; | |
3099 | if (thumb_shiftable_const (INTVAL (x))) | |
3100 | return COSTS_N_INSNS (2); | |
3101 | return COSTS_N_INSNS (3); | |
3102 | } | |
3103 | else if (outer == PLUS | |
3104 | && INTVAL (x) < 256 && INTVAL (x) > -256) | |
3105 | return 0; | |
3106 | else if (outer == COMPARE | |
3107 | && (unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
3108 | return 0; | |
3109 | else if (outer == ASHIFT || outer == ASHIFTRT | |
3110 | || outer == LSHIFTRT) | |
3111 | return 0; | |
3112 | return COSTS_N_INSNS (2); | |
3113 | ||
3114 | case CONST: | |
3115 | case CONST_DOUBLE: | |
3116 | case LABEL_REF: | |
3117 | case SYMBOL_REF: | |
3118 | return COSTS_N_INSNS (3); | |
3119 | ||
3120 | case UDIV: | |
3121 | case UMOD: | |
3122 | case DIV: | |
3123 | case MOD: | |
3124 | return 100; | |
3125 | ||
3126 | case TRUNCATE: | |
3127 | return 99; | |
3128 | ||
3129 | case AND: | |
3130 | case XOR: | |
3131 | case IOR: | |
3132 | /* XXX guess. */ | |
3133 | return 8; | |
3134 | ||
3135 | case ADDRESSOF: | |
3136 | case MEM: | |
3137 | /* XXX another guess. */ | |
3138 | /* Memory costs quite a lot for the first word, but subsequent words | |
3139 | load at the equivalent of a single insn each. */ | |
3140 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
48f6efae NC |
3141 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) |
3142 | ? 4 : 0)); | |
d5b7b3ae RE |
3143 | |
3144 | case IF_THEN_ELSE: | |
3145 | /* XXX a guess. */ | |
3146 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
3147 | return 14; | |
3148 | return 2; | |
3149 | ||
3150 | case ZERO_EXTEND: | |
3151 | /* XXX still guessing. */ | |
3152 | switch (GET_MODE (XEXP (x, 0))) | |
3153 | { | |
3154 | case QImode: | |
3155 | return (1 + (mode == DImode ? 4 : 0) | |
3156 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3157 | ||
3158 | case HImode: | |
3159 | return (4 + (mode == DImode ? 4 : 0) | |
3160 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3161 | ||
3162 | case SImode: | |
3163 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3164 | ||
3165 | default: | |
3166 | return 99; | |
3167 | } | |
3168 | ||
3169 | default: | |
3170 | return 99; | |
3171 | #if 0 | |
3172 | case FFS: | |
3173 | case FLOAT: | |
3174 | case FIX: | |
3175 | case UNSIGNED_FIX: | |
3176 | /* XXX guess */ | |
3177 | fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n", | |
3178 | rtx_name[code]); | |
3179 | abort (); | |
3180 | #endif | |
3181 | } | |
3182 | } | |
3183 | ||
e2c671ba RE |
3184 | switch (code) |
3185 | { | |
3186 | case MEM: | |
3187 | /* Memory costs quite a lot for the first word, but subsequent words | |
3188 | load at the equivalent of a single insn each. */ | |
3189 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
48f6efae NC |
3190 | + (GET_CODE (x) == SYMBOL_REF |
3191 | && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); | |
e2c671ba RE |
3192 | |
3193 | case DIV: | |
3194 | case MOD: | |
3195 | return 100; | |
3196 | ||
3197 | case ROTATE: | |
3198 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
3199 | return 4; | |
3200 | /* Fall through */ | |
3201 | case ROTATERT: | |
3202 | if (mode != SImode) | |
3203 | return 8; | |
3204 | /* Fall through */ | |
3205 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
3206 | if (mode == DImode) | |
3207 | return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) | |
3208 | + ((GET_CODE (XEXP (x, 0)) == REG | |
3209 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
3210 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
3211 | ? 0 : 8)); | |
3212 | return (1 + ((GET_CODE (XEXP (x, 0)) == REG | |
3213 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
3214 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
3215 | ? 0 : 4) | |
3216 | + ((GET_CODE (XEXP (x, 1)) == REG | |
3217 | || (GET_CODE (XEXP (x, 1)) == SUBREG | |
3218 | && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG) | |
3219 | || (GET_CODE (XEXP (x, 1)) == CONST_INT)) | |
3220 | ? 0 : 4)); | |
3221 | ||
3222 | case MINUS: | |
3223 | if (mode == DImode) | |
3224 | return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8) | |
3225 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3226 | || (GET_CODE (XEXP (x, 0)) == CONST_INT | |
3227 | && const_ok_for_arm (INTVAL (XEXP (x, 0))))) | |
3228 | ? 0 : 8)); | |
3229 | ||
3230 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3231 | return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3232 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
3b684012 | 3233 | && const_double_rtx_ok_for_fpa (XEXP (x, 1)))) |
e2c671ba RE |
3234 | ? 0 : 8) |
3235 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3236 | || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
3b684012 | 3237 | && const_double_rtx_ok_for_fpa (XEXP (x, 0)))) |
e2c671ba RE |
3238 | ? 0 : 8)); |
3239 | ||
3240 | if (((GET_CODE (XEXP (x, 0)) == CONST_INT | |
3241 | && const_ok_for_arm (INTVAL (XEXP (x, 0))) | |
3242 | && REG_OR_SUBREG_REG (XEXP (x, 1)))) | |
3243 | || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT | |
3244 | || subcode == ASHIFTRT || subcode == LSHIFTRT | |
3245 | || subcode == ROTATE || subcode == ROTATERT | |
3246 | || (subcode == MULT | |
3247 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
3248 | && ((INTVAL (XEXP (XEXP (x, 1), 1)) & | |
3249 | (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) | |
3250 | && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0)) | |
3251 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1)) | |
3252 | || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
3253 | && REG_OR_SUBREG_REG (XEXP (x, 0)))) | |
3254 | return 1; | |
3255 | /* Fall through */ | |
3256 | ||
3257 | case PLUS: | |
3258 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3259 | return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
3260 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3261 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
3b684012 | 3262 | && const_double_rtx_ok_for_fpa (XEXP (x, 1)))) |
e2c671ba RE |
3263 | ? 0 : 8)); |
3264 | ||
3265 | /* Fall through */ | |
3266 | case AND: case XOR: case IOR: | |
3267 | extra_cost = 0; | |
3268 | ||
3269 | /* Normally the frame registers will be spilt into reg+const during | |
3270 | reload, so it is a bad idea to combine them with other instructions, | |
3271 | since then they might not be moved outside of loops. As a compromise | |
3272 | we allow integration with ops that have a constant as their second | |
3273 | operand. */ | |
3274 | if ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3275 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
3276 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
3277 | || (REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3278 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) | |
3279 | extra_cost = 4; | |
3280 | ||
3281 | if (mode == DImode) | |
3282 | return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
3283 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3284 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 3285 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
3286 | ? 0 : 8)); |
3287 | ||
3288 | if (REG_OR_SUBREG_REG (XEXP (x, 0))) | |
3289 | return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost) | |
3290 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3291 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 3292 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
3293 | ? 0 : 4)); |
3294 | ||
3295 | else if (REG_OR_SUBREG_REG (XEXP (x, 1))) | |
3296 | return (1 + extra_cost | |
3297 | + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT | |
3298 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
3299 | || subcode == ROTATE || subcode == ROTATERT | |
3300 | || (subcode == MULT | |
3301 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3302 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
ad076f4e | 3303 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) |
e2c671ba RE |
3304 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0))) |
3305 | && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1))) | |
ad076f4e | 3306 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) |
e2c671ba RE |
3307 | ? 0 : 4)); |
3308 | ||
3309 | return 8; | |
3310 | ||
3311 | case MULT: | |
b111229a | 3312 | /* There is no point basing this on the tuning, since it is always the |
6354dc9b | 3313 | fast variant if it exists at all. */ |
2b835d68 RE |
3314 | if (arm_fast_multiply && mode == DImode |
3315 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
3316 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
3317 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
3318 | return 8; | |
3319 | ||
e2c671ba RE |
3320 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
3321 | || mode == DImode) | |
3322 | return 30; | |
3323 | ||
3324 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3325 | { | |
2b835d68 | 3326 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) |
30cf4896 | 3327 | & (unsigned HOST_WIDE_INT) 0xffffffff); |
e2c671ba RE |
3328 | int add_cost = const_ok_for_arm (i) ? 4 : 8; |
3329 | int j; | |
6354dc9b NC |
3330 | |
3331 | /* Tune as appropriate. */ | |
aec3cfba | 3332 | int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2); |
2a5307b1 | 3333 | |
2b835d68 | 3334 | for (j = 0; i && j < 32; j += booth_unit_size) |
e2c671ba | 3335 | { |
2b835d68 | 3336 | i >>= booth_unit_size; |
e2c671ba RE |
3337 | add_cost += 2; |
3338 | } | |
3339 | ||
3340 | return add_cost; | |
3341 | } | |
3342 | ||
aec3cfba | 3343 | return (((tune_flags & FL_FAST_MULT) ? 8 : 30) |
2b835d68 | 3344 | + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) |
e2c671ba RE |
3345 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4)); |
3346 | ||
56636818 JL |
3347 | case TRUNCATE: |
3348 | if (arm_fast_multiply && mode == SImode | |
3349 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
3350 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
3351 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
3352 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
3353 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
3354 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
3355 | return 8; | |
3356 | return 99; | |
3357 | ||
e2c671ba RE |
3358 | case NEG: |
3359 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3360 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6); | |
3361 | /* Fall through */ | |
3362 | case NOT: | |
3363 | if (mode == DImode) | |
3364 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
3365 | ||
3366 | return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
3367 | ||
3368 | case IF_THEN_ELSE: | |
3369 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
3370 | return 14; | |
3371 | return 2; | |
3372 | ||
3373 | case COMPARE: | |
3374 | return 1; | |
3375 | ||
3376 | case ABS: | |
3377 | return 4 + (mode == DImode ? 4 : 0); | |
3378 | ||
3379 | case SIGN_EXTEND: | |
3380 | if (GET_MODE (XEXP (x, 0)) == QImode) | |
3381 | return (4 + (mode == DImode ? 4 : 0) | |
3382 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3383 | /* Fall through */ | |
3384 | case ZERO_EXTEND: | |
3385 | switch (GET_MODE (XEXP (x, 0))) | |
3386 | { | |
3387 | case QImode: | |
3388 | return (1 + (mode == DImode ? 4 : 0) | |
3389 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3390 | ||
3391 | case HImode: | |
3392 | return (4 + (mode == DImode ? 4 : 0) | |
3393 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3394 | ||
3395 | case SImode: | |
3396 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
ad076f4e | 3397 | |
5a9335ef NC |
3398 | case V8QImode: |
3399 | case V4HImode: | |
3400 | case V2SImode: | |
3401 | case V4QImode: | |
3402 | case V2HImode: | |
3403 | return 1; | |
3404 | ||
ad076f4e RE |
3405 | default: |
3406 | break; | |
e2c671ba RE |
3407 | } |
3408 | abort (); | |
3409 | ||
d5b7b3ae RE |
3410 | case CONST_INT: |
3411 | if (const_ok_for_arm (INTVAL (x))) | |
3412 | return outer == SET ? 2 : -1; | |
3413 | else if (outer == AND | |
5895f793 | 3414 | && const_ok_for_arm (~INTVAL (x))) |
d5b7b3ae RE |
3415 | return -1; |
3416 | else if ((outer == COMPARE | |
3417 | || outer == PLUS || outer == MINUS) | |
5895f793 | 3418 | && const_ok_for_arm (-INTVAL (x))) |
d5b7b3ae RE |
3419 | return -1; |
3420 | else | |
3421 | return 5; | |
3422 | ||
3423 | case CONST: | |
3424 | case LABEL_REF: | |
3425 | case SYMBOL_REF: | |
3426 | return 6; | |
3427 | ||
3428 | case CONST_DOUBLE: | |
3b684012 | 3429 | if (const_double_rtx_ok_for_fpa (x)) |
d5b7b3ae RE |
3430 | return outer == SET ? 2 : -1; |
3431 | else if ((outer == COMPARE || outer == PLUS) | |
3b684012 | 3432 | && neg_const_double_rtx_ok_for_fpa (x)) |
d5b7b3ae RE |
3433 | return -1; |
3434 | return 7; | |
3435 | ||
e2c671ba RE |
3436 | default: |
3437 | return 99; | |
3438 | } | |
3439 | } | |
32de079a | 3440 | |
3c50106f | 3441 | static bool |
e32bac5b | 3442 | arm_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
3443 | { |
3444 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
3445 | return true; | |
3446 | } | |
3447 | ||
dcefdf67 RH |
3448 | /* All address computations that can be done are free, but rtx cost returns |
3449 | the same for practically all of them. So we weight the different types | |
3450 | of address here in the order (most pref first): | |
3451 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ | |
dcefdf67 | 3452 | static int |
e32bac5b | 3453 | arm_address_cost (rtx x) |
dcefdf67 RH |
3454 | { |
3455 | #define ARM_ADDRESS_COST(X) \ | |
3456 | (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ | |
3457 | || GET_CODE (X) == SYMBOL_REF) \ | |
3458 | ? 0 \ | |
3459 | : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ | |
3460 | || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ | |
3461 | ? 10 \ | |
3462 | : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ | |
3463 | ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ | |
3464 | : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ | |
3465 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ | |
3466 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ | |
3467 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ | |
3468 | ? 1 : 0)) \ | |
3469 | : 4))))) | |
3470 | ||
3471 | #define THUMB_ADDRESS_COST(X) \ | |
3472 | ((GET_CODE (X) == REG \ | |
3473 | || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
3474 | && GET_CODE (XEXP (X, 1)) == CONST_INT)) \ | |
3475 | ? 1 : 2) | |
3476 | ||
e32bac5b | 3477 | return (TARGET_ARM ? ARM_ADDRESS_COST (x) : THUMB_ADDRESS_COST (x)); |
dcefdf67 RH |
3478 | } |
3479 | ||
103fc15d | 3480 | static int |
e32bac5b | 3481 | arm_use_dfa_pipeline_interface (void) |
103fc15d BE |
3482 | { |
3483 | return true; | |
3484 | } | |
3485 | ||
c237e94a | 3486 | static int |
e32bac5b | 3487 | arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) |
32de079a RE |
3488 | { |
3489 | rtx i_pat, d_pat; | |
3490 | ||
d19fb8e3 NC |
3491 | /* Some true dependencies can have a higher cost depending |
3492 | on precisely how certain input operands are used. */ | |
4b3c2e48 | 3493 | if (arm_tune_xscale |
d19fb8e3 | 3494 | && REG_NOTE_KIND (link) == 0 |
eda833e3 BE |
3495 | && recog_memoized (insn) >= 0 |
3496 | && recog_memoized (dep) >= 0) | |
d19fb8e3 NC |
3497 | { |
3498 | int shift_opnum = get_attr_shift (insn); | |
3499 | enum attr_type attr_type = get_attr_type (dep); | |
3500 | ||
3501 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
3502 | operand for INSN. If we have a shifted input operand and the | |
3503 | instruction we depend on is another ALU instruction, then we may | |
3504 | have to account for an additional stall. */ | |
3505 | if (shift_opnum != 0 && attr_type == TYPE_NORMAL) | |
3506 | { | |
3507 | rtx shifted_operand; | |
3508 | int opno; | |
3509 | ||
3510 | /* Get the shifted operand. */ | |
3511 | extract_insn (insn); | |
3512 | shifted_operand = recog_data.operand[shift_opnum]; | |
3513 | ||
3514 | /* Iterate over all the operands in DEP. If we write an operand | |
3515 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
3516 | cost of this dependency. */ | |
3517 | extract_insn (dep); | |
3518 | preprocess_constraints (); | |
3519 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
3520 | { | |
3521 | /* We can ignore strict inputs. */ | |
3522 | if (recog_data.operand_type[opno] == OP_IN) | |
3523 | continue; | |
3524 | ||
3525 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
3526 | shifted_operand)) | |
3527 | return 2; | |
3528 | } | |
3529 | } | |
3530 | } | |
3531 | ||
6354dc9b | 3532 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
3533 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
3534 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
3535 | return 0; |
3536 | ||
d5b7b3ae RE |
3537 | /* Call insns don't incur a stall, even if they follow a load. */ |
3538 | if (REG_NOTE_KIND (link) == 0 | |
3539 | && GET_CODE (insn) == CALL_INSN) | |
3540 | return 1; | |
3541 | ||
32de079a RE |
3542 | if ((i_pat = single_set (insn)) != NULL |
3543 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
3544 | && (d_pat = single_set (dep)) != NULL | |
3545 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
3546 | { | |
48f6efae | 3547 | rtx src_mem = XEXP (SET_SRC (i_pat), 0); |
32de079a RE |
3548 | /* This is a load after a store, there is no conflict if the load reads |
3549 | from a cached area. Assume that loads from the stack, and from the | |
3550 | constant pool are cached, and that others will miss. This is a | |
6354dc9b | 3551 | hack. */ |
32de079a | 3552 | |
48f6efae NC |
3553 | if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) |
3554 | || reg_mentioned_p (stack_pointer_rtx, src_mem) | |
3555 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | |
3556 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | |
949d79eb | 3557 | return 1; |
32de079a RE |
3558 | } |
3559 | ||
3560 | return cost; | |
3561 | } | |
3562 | ||
ff9940b0 RE |
3563 | static int fpa_consts_inited = 0; |
3564 | ||
1d6e90ac | 3565 | static const char * const strings_fpa[8] = |
62b10bbc | 3566 | { |
2b835d68 RE |
3567 | "0", "1", "2", "3", |
3568 | "4", "5", "0.5", "10" | |
3569 | }; | |
ff9940b0 RE |
3570 | |
3571 | static REAL_VALUE_TYPE values_fpa[8]; | |
3572 | ||
3573 | static void | |
e32bac5b | 3574 | init_fpa_table (void) |
ff9940b0 RE |
3575 | { |
3576 | int i; | |
3577 | REAL_VALUE_TYPE r; | |
3578 | ||
3579 | for (i = 0; i < 8; i++) | |
3580 | { | |
3581 | r = REAL_VALUE_ATOF (strings_fpa[i], DFmode); | |
3582 | values_fpa[i] = r; | |
3583 | } | |
f3bb6135 | 3584 | |
ff9940b0 RE |
3585 | fpa_consts_inited = 1; |
3586 | } | |
3587 | ||
3b684012 | 3588 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
cce8749e | 3589 | int |
e32bac5b | 3590 | const_double_rtx_ok_for_fpa (rtx x) |
cce8749e | 3591 | { |
ff9940b0 RE |
3592 | REAL_VALUE_TYPE r; |
3593 | int i; | |
3594 | ||
3595 | if (!fpa_consts_inited) | |
3596 | init_fpa_table (); | |
3597 | ||
3598 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
3599 | if (REAL_VALUE_MINUS_ZERO (r)) | |
3600 | return 0; | |
f3bb6135 | 3601 | |
ff9940b0 RE |
3602 | for (i = 0; i < 8; i++) |
3603 | if (REAL_VALUES_EQUAL (r, values_fpa[i])) | |
3604 | return 1; | |
f3bb6135 | 3605 | |
ff9940b0 | 3606 | return 0; |
f3bb6135 | 3607 | } |
ff9940b0 | 3608 | |
3b684012 | 3609 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
ff9940b0 | 3610 | int |
e32bac5b | 3611 | neg_const_double_rtx_ok_for_fpa (rtx x) |
ff9940b0 RE |
3612 | { |
3613 | REAL_VALUE_TYPE r; | |
3614 | int i; | |
3615 | ||
3616 | if (!fpa_consts_inited) | |
3617 | init_fpa_table (); | |
3618 | ||
3619 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
3620 | r = REAL_VALUE_NEGATE (r); | |
3621 | if (REAL_VALUE_MINUS_ZERO (r)) | |
3622 | return 0; | |
f3bb6135 | 3623 | |
ff9940b0 RE |
3624 | for (i = 0; i < 8; i++) |
3625 | if (REAL_VALUES_EQUAL (r, values_fpa[i])) | |
3626 | return 1; | |
f3bb6135 | 3627 | |
ff9940b0 | 3628 | return 0; |
f3bb6135 | 3629 | } |
cce8749e CH |
3630 | \f |
3631 | /* Predicates for `match_operand' and `match_operator'. */ | |
3632 | ||
ff9940b0 | 3633 | /* s_register_operand is the same as register_operand, but it doesn't accept |
56a38cec DE |
3634 | (SUBREG (MEM)...). |
3635 | ||
3636 | This function exists because at the time it was put in it led to better | |
3637 | code. SUBREG(MEM) always needs a reload in the places where | |
3638 | s_register_operand is used, and this seemed to lead to excessive | |
3639 | reloading. */ | |
ff9940b0 | 3640 | int |
e32bac5b | 3641 | s_register_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
3642 | { |
3643 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3644 | return 0; | |
3645 | ||
3646 | if (GET_CODE (op) == SUBREG) | |
f3bb6135 | 3647 | op = SUBREG_REG (op); |
ff9940b0 RE |
3648 | |
3649 | /* We don't consider registers whose class is NO_REGS | |
3650 | to be a register operand. */ | |
d5b7b3ae | 3651 | /* XXX might have to check for lo regs only for thumb ??? */ |
ff9940b0 RE |
3652 | return (GET_CODE (op) == REG |
3653 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3654 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
3655 | } | |
3656 | ||
b0888988 RE |
3657 | /* A hard register operand (even before reload. */ |
3658 | int | |
e32bac5b | 3659 | arm_hard_register_operand (rtx op, enum machine_mode mode) |
b0888988 RE |
3660 | { |
3661 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3662 | return 0; | |
3663 | ||
3664 | return (GET_CODE (op) == REG | |
3665 | && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
3666 | } | |
3667 | ||
e2c671ba | 3668 | /* Only accept reg, subreg(reg), const_int. */ |
e2c671ba | 3669 | int |
e32bac5b | 3670 | reg_or_int_operand (rtx op, enum machine_mode mode) |
e2c671ba RE |
3671 | { |
3672 | if (GET_CODE (op) == CONST_INT) | |
3673 | return 1; | |
3674 | ||
3675 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3676 | return 0; | |
3677 | ||
3678 | if (GET_CODE (op) == SUBREG) | |
3679 | op = SUBREG_REG (op); | |
3680 | ||
3681 | /* We don't consider registers whose class is NO_REGS | |
3682 | to be a register operand. */ | |
3683 | return (GET_CODE (op) == REG | |
3684 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3685 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
3686 | } | |
3687 | ||
ff9940b0 | 3688 | /* Return 1 if OP is an item in memory, given that we are in reload. */ |
ff9940b0 | 3689 | int |
e32bac5b | 3690 | arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ff9940b0 RE |
3691 | { |
3692 | int regno = true_regnum (op); | |
3693 | ||
5895f793 | 3694 | return (!CONSTANT_P (op) |
ff9940b0 RE |
3695 | && (regno == -1 |
3696 | || (GET_CODE (op) == REG | |
3697 | && REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
3698 | } | |
3699 | ||
4d818c85 | 3700 | /* Return 1 if OP is a valid memory address, but not valid for a signed byte |
d5b7b3ae | 3701 | memory access (architecture V4). |
f710504c | 3702 | MODE is QImode if called when computing constraints, or VOIDmode when |
d5b7b3ae | 3703 | emitting patterns. In this latter case we cannot use memory_operand() |
6bc82793 | 3704 | because it will fail on badly formed MEMs, which is precisely what we are |
d5b7b3ae | 3705 | trying to catch. */ |
4d818c85 | 3706 | int |
e32bac5b | 3707 | bad_signed_byte_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
4d818c85 | 3708 | { |
d5b7b3ae | 3709 | #if 0 |
5895f793 | 3710 | if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM) |
d5b7b3ae RE |
3711 | return 0; |
3712 | #endif | |
3713 | if (GET_CODE (op) != MEM) | |
4d818c85 RE |
3714 | return 0; |
3715 | ||
3716 | op = XEXP (op, 0); | |
3717 | ||
6354dc9b | 3718 | /* A sum of anything more complex than reg + reg or reg + const is bad. */ |
4d818c85 | 3719 | if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) |
5895f793 RE |
3720 | && (!s_register_operand (XEXP (op, 0), VOIDmode) |
3721 | || (!s_register_operand (XEXP (op, 1), VOIDmode) | |
9c8cc54f | 3722 | && GET_CODE (XEXP (op, 1)) != CONST_INT))) |
4d818c85 RE |
3723 | return 1; |
3724 | ||
6354dc9b | 3725 | /* Big constants are also bad. */ |
4d818c85 RE |
3726 | if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT |
3727 | && (INTVAL (XEXP (op, 1)) > 0xff | |
3728 | || -INTVAL (XEXP (op, 1)) > 0xff)) | |
3729 | return 1; | |
3730 | ||
6354dc9b | 3731 | /* Everything else is good, or can will automatically be made so. */ |
4d818c85 RE |
3732 | return 0; |
3733 | } | |
3734 | ||
cce8749e | 3735 | /* Return TRUE for valid operands for the rhs of an ARM instruction. */ |
cce8749e | 3736 | int |
e32bac5b | 3737 | arm_rhs_operand (rtx op, enum machine_mode mode) |
cce8749e | 3738 | { |
ff9940b0 | 3739 | return (s_register_operand (op, mode) |
cce8749e | 3740 | || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))); |
f3bb6135 | 3741 | } |
cce8749e | 3742 | |
1d6e90ac NC |
3743 | /* Return TRUE for valid operands for the |
3744 | rhs of an ARM instruction, or a load. */ | |
ff9940b0 | 3745 | int |
e32bac5b | 3746 | arm_rhsm_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
3747 | { |
3748 | return (s_register_operand (op, mode) | |
3749 | || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))) | |
3750 | || memory_operand (op, mode)); | |
f3bb6135 | 3751 | } |
ff9940b0 RE |
3752 | |
3753 | /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a | |
3754 | constant that is valid when negated. */ | |
ff9940b0 | 3755 | int |
e32bac5b | 3756 | arm_add_operand (rtx op, enum machine_mode mode) |
ff9940b0 | 3757 | { |
d5b7b3ae RE |
3758 | if (TARGET_THUMB) |
3759 | return thumb_cmp_operand (op, mode); | |
3760 | ||
ff9940b0 RE |
3761 | return (s_register_operand (op, mode) |
3762 | || (GET_CODE (op) == CONST_INT | |
3763 | && (const_ok_for_arm (INTVAL (op)) | |
3764 | || const_ok_for_arm (-INTVAL (op))))); | |
f3bb6135 | 3765 | } |
ff9940b0 RE |
3766 | |
3767 | int | |
e32bac5b | 3768 | arm_not_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
3769 | { |
3770 | return (s_register_operand (op, mode) | |
3771 | || (GET_CODE (op) == CONST_INT | |
3772 | && (const_ok_for_arm (INTVAL (op)) | |
3773 | || const_ok_for_arm (~INTVAL (op))))); | |
f3bb6135 | 3774 | } |
ff9940b0 | 3775 | |
5165176d RE |
3776 | /* Return TRUE if the operand is a memory reference which contains an |
3777 | offsettable address. */ | |
3778 | int | |
e32bac5b | 3779 | offsettable_memory_operand (rtx op, enum machine_mode mode) |
5165176d RE |
3780 | { |
3781 | if (mode == VOIDmode) | |
3782 | mode = GET_MODE (op); | |
3783 | ||
3784 | return (mode == GET_MODE (op) | |
3785 | && GET_CODE (op) == MEM | |
3786 | && offsettable_address_p (reload_completed | reload_in_progress, | |
3787 | mode, XEXP (op, 0))); | |
3788 | } | |
3789 | ||
3790 | /* Return TRUE if the operand is a memory reference which is, or can be | |
3791 | made word aligned by adjusting the offset. */ | |
3792 | int | |
e32bac5b | 3793 | alignable_memory_operand (rtx op, enum machine_mode mode) |
5165176d RE |
3794 | { |
3795 | rtx reg; | |
3796 | ||
3797 | if (mode == VOIDmode) | |
3798 | mode = GET_MODE (op); | |
3799 | ||
3800 | if (mode != GET_MODE (op) || GET_CODE (op) != MEM) | |
3801 | return 0; | |
3802 | ||
3803 | op = XEXP (op, 0); | |
3804 | ||
3805 | return ((GET_CODE (reg = op) == REG | |
3806 | || (GET_CODE (op) == SUBREG | |
3807 | && GET_CODE (reg = SUBREG_REG (op)) == REG) | |
3808 | || (GET_CODE (op) == PLUS | |
3809 | && GET_CODE (XEXP (op, 1)) == CONST_INT | |
3810 | && (GET_CODE (reg = XEXP (op, 0)) == REG | |
3811 | || (GET_CODE (XEXP (op, 0)) == SUBREG | |
3812 | && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG)))) | |
bdb429a5 | 3813 | && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32); |
5165176d RE |
3814 | } |
3815 | ||
b111229a RE |
3816 | /* Similar to s_register_operand, but does not allow hard integer |
3817 | registers. */ | |
3818 | int | |
e32bac5b | 3819 | f_register_operand (rtx op, enum machine_mode mode) |
b111229a RE |
3820 | { |
3821 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3822 | return 0; | |
3823 | ||
3824 | if (GET_CODE (op) == SUBREG) | |
3825 | op = SUBREG_REG (op); | |
3826 | ||
3827 | /* We don't consider registers whose class is NO_REGS | |
3828 | to be a register operand. */ | |
3829 | return (GET_CODE (op) == REG | |
3830 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3b684012 | 3831 | || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); |
b111229a RE |
3832 | } |
3833 | ||
3b684012 | 3834 | /* Return TRUE for valid operands for the rhs of an FPA instruction. */ |
cce8749e | 3835 | int |
e32bac5b | 3836 | fpa_rhs_operand (rtx op, enum machine_mode mode) |
cce8749e | 3837 | { |
ff9940b0 | 3838 | if (s_register_operand (op, mode)) |
f3bb6135 | 3839 | return TRUE; |
9ce71c6f BS |
3840 | |
3841 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3842 | return FALSE; | |
3843 | ||
3844 | if (GET_CODE (op) == CONST_DOUBLE) | |
3b684012 | 3845 | return const_double_rtx_ok_for_fpa (op); |
f3bb6135 RE |
3846 | |
3847 | return FALSE; | |
3848 | } | |
cce8749e | 3849 | |
ff9940b0 | 3850 | int |
e32bac5b | 3851 | fpa_add_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
3852 | { |
3853 | if (s_register_operand (op, mode)) | |
f3bb6135 | 3854 | return TRUE; |
9ce71c6f BS |
3855 | |
3856 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3857 | return FALSE; | |
3858 | ||
3859 | if (GET_CODE (op) == CONST_DOUBLE) | |
3b684012 RE |
3860 | return (const_double_rtx_ok_for_fpa (op) |
3861 | || neg_const_double_rtx_ok_for_fpa (op)); | |
f3bb6135 RE |
3862 | |
3863 | return FALSE; | |
ff9940b0 RE |
3864 | } |
3865 | ||
9b6b54e2 | 3866 | /* Return nonzero if OP is a valid Cirrus memory address pattern. */ |
9b6b54e2 | 3867 | int |
e32bac5b | 3868 | cirrus_memory_offset (rtx op) |
9b6b54e2 NC |
3869 | { |
3870 | /* Reject eliminable registers. */ | |
3871 | if (! (reload_in_progress || reload_completed) | |
3872 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
3873 | || reg_mentioned_p (arg_pointer_rtx, op) | |
3874 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
3875 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
3876 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
3877 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
3878 | return 0; | |
3879 | ||
3880 | if (GET_CODE (op) == MEM) | |
3881 | { | |
3882 | rtx ind; | |
3883 | ||
3884 | ind = XEXP (op, 0); | |
3885 | ||
3886 | /* Match: (mem (reg)). */ | |
3887 | if (GET_CODE (ind) == REG) | |
3888 | return 1; | |
3889 | ||
3890 | /* Match: | |
3891 | (mem (plus (reg) | |
3892 | (const))). */ | |
3893 | if (GET_CODE (ind) == PLUS | |
3894 | && GET_CODE (XEXP (ind, 0)) == REG | |
3895 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
3896 | && GET_CODE (XEXP (ind, 1)) == CONST_INT) | |
3897 | return 1; | |
3898 | } | |
3899 | ||
3900 | return 0; | |
3901 | } | |
3902 | ||
3903 | /* Return nonzero if OP is a Cirrus or general register. */ | |
9b6b54e2 | 3904 | int |
e32bac5b | 3905 | cirrus_register_operand (rtx op, enum machine_mode mode) |
9b6b54e2 NC |
3906 | { |
3907 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3908 | return FALSE; | |
3909 | ||
3910 | if (GET_CODE (op) == SUBREG) | |
3911 | op = SUBREG_REG (op); | |
3912 | ||
3913 | return (GET_CODE (op) == REG | |
3914 | && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS | |
3915 | || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS)); | |
3916 | } | |
3917 | ||
3918 | /* Return nonzero if OP is a cirrus FP register. */ | |
9b6b54e2 | 3919 | int |
e32bac5b | 3920 | cirrus_fp_register (rtx op, enum machine_mode mode) |
9b6b54e2 NC |
3921 | { |
3922 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3923 | return FALSE; | |
3924 | ||
3925 | if (GET_CODE (op) == SUBREG) | |
3926 | op = SUBREG_REG (op); | |
3927 | ||
3928 | return (GET_CODE (op) == REG | |
3929 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3930 | || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS)); | |
3931 | } | |
3932 | ||
3933 | /* Return nonzero if OP is a 6bit constant (0..63). */ | |
9b6b54e2 | 3934 | int |
e32bac5b | 3935 | cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9b6b54e2 NC |
3936 | { |
3937 | return (GET_CODE (op) == CONST_INT | |
3938 | && INTVAL (op) >= 0 | |
3939 | && INTVAL (op) < 64); | |
3940 | } | |
3941 | ||
f0375c66 NC |
3942 | /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. |
3943 | Use by the Cirrus Maverick code which has to workaround | |
3944 | a hardware bug triggered by such instructions. */ | |
f0375c66 | 3945 | static bool |
e32bac5b | 3946 | arm_memory_load_p (rtx insn) |
9b6b54e2 NC |
3947 | { |
3948 | rtx body, lhs, rhs;; | |
3949 | ||
f0375c66 NC |
3950 | if (insn == NULL_RTX || GET_CODE (insn) != INSN) |
3951 | return false; | |
9b6b54e2 NC |
3952 | |
3953 | body = PATTERN (insn); | |
3954 | ||
3955 | if (GET_CODE (body) != SET) | |
f0375c66 | 3956 | return false; |
9b6b54e2 NC |
3957 | |
3958 | lhs = XEXP (body, 0); | |
3959 | rhs = XEXP (body, 1); | |
3960 | ||
f0375c66 NC |
3961 | lhs = REG_OR_SUBREG_RTX (lhs); |
3962 | ||
3963 | /* If the destination is not a general purpose | |
3964 | register we do not have to worry. */ | |
3965 | if (GET_CODE (lhs) != REG | |
3966 | || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) | |
3967 | return false; | |
3968 | ||
3969 | /* As well as loads from memory we also have to react | |
3970 | to loads of invalid constants which will be turned | |
3971 | into loads from the minipool. */ | |
3972 | return (GET_CODE (rhs) == MEM | |
3973 | || GET_CODE (rhs) == SYMBOL_REF | |
3974 | || note_invalid_constants (insn, -1, false)); | |
9b6b54e2 NC |
3975 | } |
3976 | ||
f0375c66 | 3977 | /* Return TRUE if INSN is a Cirrus instruction. */ |
f0375c66 | 3978 | static bool |
e32bac5b | 3979 | arm_cirrus_insn_p (rtx insn) |
9b6b54e2 NC |
3980 | { |
3981 | enum attr_cirrus attr; | |
3982 | ||
3983 | /* get_attr aborts on USE and CLOBBER. */ | |
3984 | if (!insn | |
3985 | || GET_CODE (insn) != INSN | |
3986 | || GET_CODE (PATTERN (insn)) == USE | |
3987 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3988 | return 0; | |
3989 | ||
3990 | attr = get_attr_cirrus (insn); | |
3991 | ||
f0375c66 | 3992 | return attr != CIRRUS_NOT; |
9b6b54e2 NC |
3993 | } |
3994 | ||
3995 | /* Cirrus reorg for invalid instruction combinations. */ | |
9b6b54e2 | 3996 | static void |
e32bac5b | 3997 | cirrus_reorg (rtx first) |
9b6b54e2 NC |
3998 | { |
3999 | enum attr_cirrus attr; | |
4000 | rtx body = PATTERN (first); | |
4001 | rtx t; | |
4002 | int nops; | |
4003 | ||
4004 | /* Any branch must be followed by 2 non Cirrus instructions. */ | |
4005 | if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) | |
4006 | { | |
4007 | nops = 0; | |
4008 | t = next_nonnote_insn (first); | |
4009 | ||
f0375c66 | 4010 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
4011 | ++ nops; |
4012 | ||
f0375c66 | 4013 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
4014 | ++ nops; |
4015 | ||
4016 | while (nops --) | |
4017 | emit_insn_after (gen_nop (), first); | |
4018 | ||
4019 | return; | |
4020 | } | |
4021 | ||
4022 | /* (float (blah)) is in parallel with a clobber. */ | |
4023 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
4024 | body = XVECEXP (body, 0, 0); | |
4025 | ||
4026 | if (GET_CODE (body) == SET) | |
4027 | { | |
4028 | rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); | |
4029 | ||
4030 | /* cfldrd, cfldr64, cfstrd, cfstr64 must | |
4031 | be followed by a non Cirrus insn. */ | |
4032 | if (get_attr_cirrus (first) == CIRRUS_DOUBLE) | |
4033 | { | |
f0375c66 | 4034 | if (arm_cirrus_insn_p (next_nonnote_insn (first))) |
9b6b54e2 NC |
4035 | emit_insn_after (gen_nop (), first); |
4036 | ||
4037 | return; | |
4038 | } | |
f0375c66 | 4039 | else if (arm_memory_load_p (first)) |
9b6b54e2 NC |
4040 | { |
4041 | unsigned int arm_regno; | |
4042 | ||
4043 | /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, | |
4044 | ldr/cfmv64hr combination where the Rd field is the same | |
4045 | in both instructions must be split with a non Cirrus | |
4046 | insn. Example: | |
4047 | ||
4048 | ldr r0, blah | |
4049 | nop | |
4050 | cfmvsr mvf0, r0. */ | |
4051 | ||
4052 | /* Get Arm register number for ldr insn. */ | |
4053 | if (GET_CODE (lhs) == REG) | |
4054 | arm_regno = REGNO (lhs); | |
4055 | else if (GET_CODE (rhs) == REG) | |
4056 | arm_regno = REGNO (rhs); | |
4057 | else | |
4058 | abort (); | |
4059 | ||
4060 | /* Next insn. */ | |
4061 | first = next_nonnote_insn (first); | |
4062 | ||
f0375c66 | 4063 | if (! arm_cirrus_insn_p (first)) |
9b6b54e2 NC |
4064 | return; |
4065 | ||
4066 | body = PATTERN (first); | |
4067 | ||
4068 | /* (float (blah)) is in parallel with a clobber. */ | |
4069 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) | |
4070 | body = XVECEXP (body, 0, 0); | |
4071 | ||
4072 | if (GET_CODE (body) == FLOAT) | |
4073 | body = XEXP (body, 0); | |
4074 | ||
4075 | if (get_attr_cirrus (first) == CIRRUS_MOVE | |
4076 | && GET_CODE (XEXP (body, 1)) == REG | |
4077 | && arm_regno == REGNO (XEXP (body, 1))) | |
4078 | emit_insn_after (gen_nop (), first); | |
4079 | ||
4080 | return; | |
4081 | } | |
4082 | } | |
4083 | ||
4084 | /* get_attr aborts on USE and CLOBBER. */ | |
4085 | if (!first | |
4086 | || GET_CODE (first) != INSN | |
4087 | || GET_CODE (PATTERN (first)) == USE | |
4088 | || GET_CODE (PATTERN (first)) == CLOBBER) | |
4089 | return; | |
4090 | ||
4091 | attr = get_attr_cirrus (first); | |
4092 | ||
4093 | /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) | |
4094 | must be followed by a non-coprocessor instruction. */ | |
4095 | if (attr == CIRRUS_COMPARE) | |
4096 | { | |
4097 | nops = 0; | |
4098 | ||
4099 | t = next_nonnote_insn (first); | |
4100 | ||
f0375c66 | 4101 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
4102 | ++ nops; |
4103 | ||
f0375c66 | 4104 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
4105 | ++ nops; |
4106 | ||
4107 | while (nops --) | |
4108 | emit_insn_after (gen_nop (), first); | |
4109 | ||
4110 | return; | |
4111 | } | |
4112 | } | |
4113 | ||
cce8749e | 4114 | /* Return nonzero if OP is a constant power of two. */ |
cce8749e | 4115 | int |
e32bac5b | 4116 | power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
cce8749e CH |
4117 | { |
4118 | if (GET_CODE (op) == CONST_INT) | |
4119 | { | |
d5b7b3ae | 4120 | HOST_WIDE_INT value = INTVAL (op); |
1d6e90ac | 4121 | |
f3bb6135 | 4122 | return value != 0 && (value & (value - 1)) == 0; |
cce8749e | 4123 | } |
1d6e90ac | 4124 | |
f3bb6135 RE |
4125 | return FALSE; |
4126 | } | |
cce8749e CH |
4127 | |
4128 | /* Return TRUE for a valid operand of a DImode operation. | |
e9c6b69b | 4129 | Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). |
ff9940b0 RE |
4130 | Note that this disallows MEM(REG+REG), but allows |
4131 | MEM(PRE/POST_INC/DEC(REG)). */ | |
cce8749e | 4132 | int |
e32bac5b | 4133 | di_operand (rtx op, enum machine_mode mode) |
cce8749e | 4134 | { |
ff9940b0 | 4135 | if (s_register_operand (op, mode)) |
f3bb6135 | 4136 | return TRUE; |
cce8749e | 4137 | |
9ce71c6f BS |
4138 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) |
4139 | return FALSE; | |
4140 | ||
e9c6b69b NC |
4141 | if (GET_CODE (op) == SUBREG) |
4142 | op = SUBREG_REG (op); | |
4143 | ||
cce8749e CH |
4144 | switch (GET_CODE (op)) |
4145 | { | |
4146 | case CONST_DOUBLE: | |
4147 | case CONST_INT: | |
f3bb6135 RE |
4148 | return TRUE; |
4149 | ||
cce8749e | 4150 | case MEM: |
f3bb6135 RE |
4151 | return memory_address_p (DImode, XEXP (op, 0)); |
4152 | ||
cce8749e | 4153 | default: |
f3bb6135 | 4154 | return FALSE; |
cce8749e | 4155 | } |
f3bb6135 | 4156 | } |
cce8749e | 4157 | |
d5b7b3ae RE |
4158 | /* Like di_operand, but don't accept constants. */ |
4159 | int | |
e32bac5b | 4160 | nonimmediate_di_operand (rtx op, enum machine_mode mode) |
d5b7b3ae RE |
4161 | { |
4162 | if (s_register_operand (op, mode)) | |
4163 | return TRUE; | |
4164 | ||
4165 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) | |
4166 | return FALSE; | |
4167 | ||
4168 | if (GET_CODE (op) == SUBREG) | |
4169 | op = SUBREG_REG (op); | |
4170 | ||
4171 | if (GET_CODE (op) == MEM) | |
4172 | return memory_address_p (DImode, XEXP (op, 0)); | |
4173 | ||
4174 | return FALSE; | |
4175 | } | |
4176 | ||
f3139301 | 4177 | /* Return TRUE for a valid operand of a DFmode operation when -msoft-float. |
e9c6b69b | 4178 | Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). |
f3139301 DE |
4179 | Note that this disallows MEM(REG+REG), but allows |
4180 | MEM(PRE/POST_INC/DEC(REG)). */ | |
f3139301 | 4181 | int |
e32bac5b | 4182 | soft_df_operand (rtx op, enum machine_mode mode) |
f3139301 DE |
4183 | { |
4184 | if (s_register_operand (op, mode)) | |
4b02997f | 4185 | return TRUE; |
f3139301 | 4186 | |
9ce71c6f BS |
4187 | if (mode != VOIDmode && GET_MODE (op) != mode) |
4188 | return FALSE; | |
4189 | ||
37b80d2e BS |
4190 | if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op))) |
4191 | return FALSE; | |
4192 | ||
e9c6b69b NC |
4193 | if (GET_CODE (op) == SUBREG) |
4194 | op = SUBREG_REG (op); | |
9ce71c6f | 4195 | |
f3139301 DE |
4196 | switch (GET_CODE (op)) |
4197 | { | |
4198 | case CONST_DOUBLE: | |
4199 | return TRUE; | |
4200 | ||
4201 | case MEM: | |
4202 | return memory_address_p (DFmode, XEXP (op, 0)); | |
4203 | ||
4204 | default: | |
4205 | return FALSE; | |
4206 | } | |
4207 | } | |
4208 | ||
d5b7b3ae RE |
4209 | /* Like soft_df_operand, but don't accept constants. */ |
4210 | int | |
e32bac5b | 4211 | nonimmediate_soft_df_operand (rtx op, enum machine_mode mode) |
d5b7b3ae RE |
4212 | { |
4213 | if (s_register_operand (op, mode)) | |
4b02997f | 4214 | return TRUE; |
d5b7b3ae RE |
4215 | |
4216 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
4217 | return FALSE; | |
4218 | ||
4219 | if (GET_CODE (op) == SUBREG) | |
4220 | op = SUBREG_REG (op); | |
4221 | ||
4222 | if (GET_CODE (op) == MEM) | |
4223 | return memory_address_p (DFmode, XEXP (op, 0)); | |
4224 | return FALSE; | |
4225 | } | |
cce8749e | 4226 | |
d5b7b3ae | 4227 | /* Return TRUE for valid index operands. */ |
cce8749e | 4228 | int |
e32bac5b | 4229 | index_operand (rtx op, enum machine_mode mode) |
cce8749e | 4230 | { |
d5b7b3ae | 4231 | return (s_register_operand (op, mode) |
ff9940b0 | 4232 | || (immediate_operand (op, mode) |
d5b7b3ae RE |
4233 | && (GET_CODE (op) != CONST_INT |
4234 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096)))); | |
f3bb6135 | 4235 | } |
cce8749e | 4236 | |
ff9940b0 RE |
4237 | /* Return TRUE for valid shifts by a constant. This also accepts any |
4238 | power of two on the (somewhat overly relaxed) assumption that the | |
6354dc9b | 4239 | shift operator in this case was a mult. */ |
ff9940b0 | 4240 | int |
e32bac5b | 4241 | const_shift_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
4242 | { |
4243 | return (power_of_two_operand (op, mode) | |
4244 | || (immediate_operand (op, mode) | |
d5b7b3ae RE |
4245 | && (GET_CODE (op) != CONST_INT |
4246 | || (INTVAL (op) < 32 && INTVAL (op) > 0)))); | |
f3bb6135 | 4247 | } |
ff9940b0 | 4248 | |
cce8749e CH |
4249 | /* Return TRUE for arithmetic operators which can be combined with a multiply |
4250 | (shift). */ | |
cce8749e | 4251 | int |
e32bac5b | 4252 | shiftable_operator (rtx x, enum machine_mode mode) |
cce8749e | 4253 | { |
1d6e90ac NC |
4254 | enum rtx_code code; |
4255 | ||
cce8749e CH |
4256 | if (GET_MODE (x) != mode) |
4257 | return FALSE; | |
cce8749e | 4258 | |
1d6e90ac NC |
4259 | code = GET_CODE (x); |
4260 | ||
4261 | return (code == PLUS || code == MINUS | |
4262 | || code == IOR || code == XOR || code == AND); | |
f3bb6135 | 4263 | } |
cce8749e | 4264 | |
6ab589e0 | 4265 | /* Return TRUE for binary logical operators. */ |
6ab589e0 | 4266 | int |
e32bac5b | 4267 | logical_binary_operator (rtx x, enum machine_mode mode) |
6ab589e0 | 4268 | { |
1d6e90ac NC |
4269 | enum rtx_code code; |
4270 | ||
6ab589e0 JL |
4271 | if (GET_MODE (x) != mode) |
4272 | return FALSE; | |
6ab589e0 | 4273 | |
1d6e90ac NC |
4274 | code = GET_CODE (x); |
4275 | ||
4276 | return (code == IOR || code == XOR || code == AND); | |
6ab589e0 JL |
4277 | } |
4278 | ||
6354dc9b | 4279 | /* Return TRUE for shift operators. */ |
cce8749e | 4280 | int |
e32bac5b | 4281 | shift_operator (rtx x,enum machine_mode mode) |
cce8749e | 4282 | { |
1d6e90ac NC |
4283 | enum rtx_code code; |
4284 | ||
cce8749e CH |
4285 | if (GET_MODE (x) != mode) |
4286 | return FALSE; | |
cce8749e | 4287 | |
1d6e90ac | 4288 | code = GET_CODE (x); |
f3bb6135 | 4289 | |
1d6e90ac NC |
4290 | if (code == MULT) |
4291 | return power_of_two_operand (XEXP (x, 1), mode); | |
4292 | ||
4293 | return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT | |
4294 | || code == ROTATERT); | |
f3bb6135 | 4295 | } |
ff9940b0 | 4296 | |
6354dc9b NC |
4297 | /* Return TRUE if x is EQ or NE. */ |
4298 | int | |
e32bac5b | 4299 | equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
ff9940b0 | 4300 | { |
f3bb6135 | 4301 | return GET_CODE (x) == EQ || GET_CODE (x) == NE; |
ff9940b0 RE |
4302 | } |
4303 | ||
e45b72c4 RE |
4304 | /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */ |
4305 | int | |
e32bac5b | 4306 | arm_comparison_operator (rtx x, enum machine_mode mode) |
e45b72c4 RE |
4307 | { |
4308 | return (comparison_operator (x, mode) | |
4309 | && GET_CODE (x) != LTGT | |
4310 | && GET_CODE (x) != UNEQ); | |
4311 | } | |
4312 | ||
6354dc9b | 4313 | /* Return TRUE for SMIN SMAX UMIN UMAX operators. */ |
ff9940b0 | 4314 | int |
e32bac5b | 4315 | minmax_operator (rtx x, enum machine_mode mode) |
ff9940b0 RE |
4316 | { |
4317 | enum rtx_code code = GET_CODE (x); | |
4318 | ||
4319 | if (GET_MODE (x) != mode) | |
4320 | return FALSE; | |
f3bb6135 | 4321 | |
ff9940b0 | 4322 | return code == SMIN || code == SMAX || code == UMIN || code == UMAX; |
f3bb6135 | 4323 | } |
ff9940b0 | 4324 | |
ff9940b0 | 4325 | /* Return TRUE if this is the condition code register, if we aren't given |
6354dc9b | 4326 | a mode, accept any class CCmode register. */ |
ff9940b0 | 4327 | int |
e32bac5b | 4328 | cc_register (rtx x, enum machine_mode mode) |
ff9940b0 RE |
4329 | { |
4330 | if (mode == VOIDmode) | |
4331 | { | |
4332 | mode = GET_MODE (x); | |
d5b7b3ae | 4333 | |
ff9940b0 RE |
4334 | if (GET_MODE_CLASS (mode) != MODE_CC) |
4335 | return FALSE; | |
4336 | } | |
f3bb6135 | 4337 | |
d5b7b3ae RE |
4338 | if ( GET_MODE (x) == mode |
4339 | && GET_CODE (x) == REG | |
4340 | && REGNO (x) == CC_REGNUM) | |
ff9940b0 | 4341 | return TRUE; |
f3bb6135 | 4342 | |
ff9940b0 RE |
4343 | return FALSE; |
4344 | } | |
5bbe2d40 RE |
4345 | |
4346 | /* Return TRUE if this is the condition code register, if we aren't given | |
84ed5e79 RE |
4347 | a mode, accept any class CCmode register which indicates a dominance |
4348 | expression. */ | |
5bbe2d40 | 4349 | int |
e32bac5b | 4350 | dominant_cc_register (rtx x, enum machine_mode mode) |
5bbe2d40 RE |
4351 | { |
4352 | if (mode == VOIDmode) | |
4353 | { | |
4354 | mode = GET_MODE (x); | |
d5b7b3ae | 4355 | |
84ed5e79 | 4356 | if (GET_MODE_CLASS (mode) != MODE_CC) |
5bbe2d40 RE |
4357 | return FALSE; |
4358 | } | |
4359 | ||
e32bac5b | 4360 | if (mode != CC_DNEmode && mode != CC_DEQmode |
84ed5e79 RE |
4361 | && mode != CC_DLEmode && mode != CC_DLTmode |
4362 | && mode != CC_DGEmode && mode != CC_DGTmode | |
4363 | && mode != CC_DLEUmode && mode != CC_DLTUmode | |
4364 | && mode != CC_DGEUmode && mode != CC_DGTUmode) | |
4365 | return FALSE; | |
4366 | ||
d5b7b3ae | 4367 | return cc_register (x, mode); |
5bbe2d40 RE |
4368 | } |
4369 | ||
2b835d68 RE |
4370 | /* Return TRUE if X references a SYMBOL_REF. */ |
4371 | int | |
e32bac5b | 4372 | symbol_mentioned_p (rtx x) |
2b835d68 | 4373 | { |
1d6e90ac NC |
4374 | const char * fmt; |
4375 | int i; | |
2b835d68 RE |
4376 | |
4377 | if (GET_CODE (x) == SYMBOL_REF) | |
4378 | return 1; | |
4379 | ||
4380 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
d5b7b3ae | 4381 | |
2b835d68 RE |
4382 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
4383 | { | |
4384 | if (fmt[i] == 'E') | |
4385 | { | |
1d6e90ac | 4386 | int j; |
2b835d68 RE |
4387 | |
4388 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4389 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
4390 | return 1; | |
4391 | } | |
4392 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
4393 | return 1; | |
4394 | } | |
4395 | ||
4396 | return 0; | |
4397 | } | |
4398 | ||
4399 | /* Return TRUE if X references a LABEL_REF. */ | |
4400 | int | |
e32bac5b | 4401 | label_mentioned_p (rtx x) |
2b835d68 | 4402 | { |
1d6e90ac NC |
4403 | const char * fmt; |
4404 | int i; | |
2b835d68 RE |
4405 | |
4406 | if (GET_CODE (x) == LABEL_REF) | |
4407 | return 1; | |
4408 | ||
4409 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
4410 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
4411 | { | |
4412 | if (fmt[i] == 'E') | |
4413 | { | |
1d6e90ac | 4414 | int j; |
2b835d68 RE |
4415 | |
4416 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4417 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
4418 | return 1; | |
4419 | } | |
4420 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
4421 | return 1; | |
4422 | } | |
4423 | ||
4424 | return 0; | |
4425 | } | |
4426 | ||
ff9940b0 | 4427 | enum rtx_code |
e32bac5b | 4428 | minmax_code (rtx x) |
ff9940b0 RE |
4429 | { |
4430 | enum rtx_code code = GET_CODE (x); | |
4431 | ||
4432 | if (code == SMAX) | |
4433 | return GE; | |
f3bb6135 | 4434 | else if (code == SMIN) |
ff9940b0 | 4435 | return LE; |
f3bb6135 | 4436 | else if (code == UMIN) |
ff9940b0 | 4437 | return LEU; |
f3bb6135 | 4438 | else if (code == UMAX) |
ff9940b0 | 4439 | return GEU; |
f3bb6135 | 4440 | |
ff9940b0 RE |
4441 | abort (); |
4442 | } | |
4443 | ||
6354dc9b | 4444 | /* Return 1 if memory locations are adjacent. */ |
f3bb6135 | 4445 | int |
e32bac5b | 4446 | adjacent_mem_locations (rtx a, rtx b) |
ff9940b0 | 4447 | { |
ff9940b0 RE |
4448 | if ((GET_CODE (XEXP (a, 0)) == REG |
4449 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
4450 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
4451 | && (GET_CODE (XEXP (b, 0)) == REG | |
4452 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
4453 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
4454 | { | |
1d6e90ac NC |
4455 | int val0 = 0, val1 = 0; |
4456 | int reg0, reg1; | |
4457 | ||
ff9940b0 RE |
4458 | if (GET_CODE (XEXP (a, 0)) == PLUS) |
4459 | { | |
1d6e90ac | 4460 | reg0 = REGNO (XEXP (XEXP (a, 0), 0)); |
ff9940b0 RE |
4461 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); |
4462 | } | |
4463 | else | |
4464 | reg0 = REGNO (XEXP (a, 0)); | |
1d6e90ac | 4465 | |
ff9940b0 RE |
4466 | if (GET_CODE (XEXP (b, 0)) == PLUS) |
4467 | { | |
1d6e90ac | 4468 | reg1 = REGNO (XEXP (XEXP (b, 0), 0)); |
ff9940b0 RE |
4469 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); |
4470 | } | |
4471 | else | |
4472 | reg1 = REGNO (XEXP (b, 0)); | |
1d6e90ac | 4473 | |
e32bac5b RE |
4474 | /* Don't accept any offset that will require multiple |
4475 | instructions to handle, since this would cause the | |
4476 | arith_adjacentmem pattern to output an overlong sequence. */ | |
c75a3ddc PB |
4477 | if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1)) |
4478 | return 0; | |
4479 | ||
ff9940b0 RE |
4480 | return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4); |
4481 | } | |
4482 | return 0; | |
4483 | } | |
4484 | ||
4485 | /* Return 1 if OP is a load multiple operation. It is known to be | |
6354dc9b | 4486 | parallel and the first section will be tested. */ |
f3bb6135 | 4487 | int |
e32bac5b | 4488 | load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ff9940b0 | 4489 | { |
f3bb6135 | 4490 | HOST_WIDE_INT count = XVECLEN (op, 0); |
ff9940b0 RE |
4491 | int dest_regno; |
4492 | rtx src_addr; | |
f3bb6135 | 4493 | HOST_WIDE_INT i = 1, base = 0; |
ff9940b0 RE |
4494 | rtx elt; |
4495 | ||
4496 | if (count <= 1 | |
4497 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
4498 | return 0; | |
4499 | ||
6354dc9b | 4500 | /* Check to see if this might be a write-back. */ |
ff9940b0 RE |
4501 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) |
4502 | { | |
4503 | i++; | |
4504 | base = 1; | |
4505 | ||
6354dc9b | 4506 | /* Now check it more carefully. */ |
ff9940b0 RE |
4507 | if (GET_CODE (SET_DEST (elt)) != REG |
4508 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
4509 | || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) | |
4510 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
41e3f998 | 4511 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) |
ff9940b0 | 4512 | return 0; |
ff9940b0 RE |
4513 | } |
4514 | ||
4515 | /* Perform a quick check so we don't blow up below. */ | |
4516 | if (count <= i | |
4517 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
4518 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG | |
4519 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) | |
4520 | return 0; | |
4521 | ||
4522 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); | |
4523 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); | |
4524 | ||
4525 | for (; i < count; i++) | |
4526 | { | |
ed4c4348 | 4527 | elt = XVECEXP (op, 0, i); |
ff9940b0 RE |
4528 | |
4529 | if (GET_CODE (elt) != SET | |
4530 | || GET_CODE (SET_DEST (elt)) != REG | |
4531 | || GET_MODE (SET_DEST (elt)) != SImode | |
6354dc9b | 4532 | || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base) |
ff9940b0 RE |
4533 | || GET_CODE (SET_SRC (elt)) != MEM |
4534 | || GET_MODE (SET_SRC (elt)) != SImode | |
4535 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
5895f793 | 4536 | || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) |
ff9940b0 RE |
4537 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT |
4538 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) | |
4539 | return 0; | |
4540 | } | |
4541 | ||
4542 | return 1; | |
4543 | } | |
4544 | ||
4545 | /* Return 1 if OP is a store multiple operation. It is known to be | |
6354dc9b | 4546 | parallel and the first section will be tested. */ |
f3bb6135 | 4547 | int |
e32bac5b | 4548 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ff9940b0 | 4549 | { |
f3bb6135 | 4550 | HOST_WIDE_INT count = XVECLEN (op, 0); |
ff9940b0 RE |
4551 | int src_regno; |
4552 | rtx dest_addr; | |
f3bb6135 | 4553 | HOST_WIDE_INT i = 1, base = 0; |
ff9940b0 RE |
4554 | rtx elt; |
4555 | ||
4556 | if (count <= 1 | |
4557 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
4558 | return 0; | |
4559 | ||
6354dc9b | 4560 | /* Check to see if this might be a write-back. */ |
ff9940b0 RE |
4561 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) |
4562 | { | |
4563 | i++; | |
4564 | base = 1; | |
4565 | ||
6354dc9b | 4566 | /* Now check it more carefully. */ |
ff9940b0 RE |
4567 | if (GET_CODE (SET_DEST (elt)) != REG |
4568 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
4569 | || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) | |
4570 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
41e3f998 | 4571 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) |
ff9940b0 | 4572 | return 0; |
ff9940b0 RE |
4573 | } |
4574 | ||
4575 | /* Perform a quick check so we don't blow up below. */ | |
4576 | if (count <= i | |
4577 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
4578 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM | |
4579 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) | |
4580 | return 0; | |
4581 | ||
4582 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); | |
4583 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); | |
4584 | ||
4585 | for (; i < count; i++) | |
4586 | { | |
4587 | elt = XVECEXP (op, 0, i); | |
4588 | ||
4589 | if (GET_CODE (elt) != SET | |
4590 | || GET_CODE (SET_SRC (elt)) != REG | |
4591 | || GET_MODE (SET_SRC (elt)) != SImode | |
6354dc9b | 4592 | || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base) |
ff9940b0 RE |
4593 | || GET_CODE (SET_DEST (elt)) != MEM |
4594 | || GET_MODE (SET_DEST (elt)) != SImode | |
4595 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
5895f793 | 4596 | || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) |
ff9940b0 RE |
4597 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT |
4598 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) | |
4599 | return 0; | |
4600 | } | |
4601 | ||
4602 | return 1; | |
4603 | } | |
e2c671ba | 4604 | |
84ed5e79 | 4605 | int |
e32bac5b RE |
4606 | load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
4607 | HOST_WIDE_INT *load_offset) | |
84ed5e79 RE |
4608 | { |
4609 | int unsorted_regs[4]; | |
4610 | HOST_WIDE_INT unsorted_offsets[4]; | |
4611 | int order[4]; | |
ad076f4e | 4612 | int base_reg = -1; |
84ed5e79 RE |
4613 | int i; |
4614 | ||
1d6e90ac NC |
4615 | /* Can only handle 2, 3, or 4 insns at present, |
4616 | though could be easily extended if required. */ | |
84ed5e79 RE |
4617 | if (nops < 2 || nops > 4) |
4618 | abort (); | |
4619 | ||
4620 | /* Loop over the operands and check that the memory references are | |
4621 | suitable (ie immediate offsets from the same base register). At | |
4622 | the same time, extract the target register, and the memory | |
4623 | offsets. */ | |
4624 | for (i = 0; i < nops; i++) | |
4625 | { | |
4626 | rtx reg; | |
4627 | rtx offset; | |
4628 | ||
56636818 JL |
4629 | /* Convert a subreg of a mem into the mem itself. */ |
4630 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 4631 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 4632 | |
84ed5e79 RE |
4633 | if (GET_CODE (operands[nops + i]) != MEM) |
4634 | abort (); | |
4635 | ||
4636 | /* Don't reorder volatile memory references; it doesn't seem worth | |
4637 | looking for the case where the order is ok anyway. */ | |
4638 | if (MEM_VOLATILE_P (operands[nops + i])) | |
4639 | return 0; | |
4640 | ||
4641 | offset = const0_rtx; | |
4642 | ||
4643 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
4644 | || (GET_CODE (reg) == SUBREG | |
4645 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
4646 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
4647 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
4648 | == REG) | |
4649 | || (GET_CODE (reg) == SUBREG | |
4650 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
4651 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
4652 | == CONST_INT))) | |
4653 | { | |
4654 | if (i == 0) | |
4655 | { | |
d5b7b3ae | 4656 | base_reg = REGNO (reg); |
84ed5e79 RE |
4657 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
4658 | ? REGNO (operands[i]) | |
4659 | : REGNO (SUBREG_REG (operands[i]))); | |
4660 | order[0] = 0; | |
4661 | } | |
4662 | else | |
4663 | { | |
6354dc9b | 4664 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
4665 | /* Not addressed from the same base register. */ |
4666 | return 0; | |
4667 | ||
4668 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
4669 | ? REGNO (operands[i]) | |
4670 | : REGNO (SUBREG_REG (operands[i]))); | |
4671 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
4672 | order[0] = i; | |
4673 | } | |
4674 | ||
4675 | /* If it isn't an integer register, or if it overwrites the | |
4676 | base register but isn't the last insn in the list, then | |
4677 | we can't do this. */ | |
4678 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | |
4679 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) | |
4680 | return 0; | |
4681 | ||
4682 | unsorted_offsets[i] = INTVAL (offset); | |
4683 | } | |
4684 | else | |
4685 | /* Not a suitable memory address. */ | |
4686 | return 0; | |
4687 | } | |
4688 | ||
4689 | /* All the useful information has now been extracted from the | |
4690 | operands into unsorted_regs and unsorted_offsets; additionally, | |
4691 | order[0] has been set to the lowest numbered register in the | |
4692 | list. Sort the registers into order, and check that the memory | |
4693 | offsets are ascending and adjacent. */ | |
4694 | ||
4695 | for (i = 1; i < nops; i++) | |
4696 | { | |
4697 | int j; | |
4698 | ||
4699 | order[i] = order[i - 1]; | |
4700 | for (j = 0; j < nops; j++) | |
4701 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
4702 | && (order[i] == order[i - 1] | |
4703 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
4704 | order[i] = j; | |
4705 | ||
4706 | /* Have we found a suitable register? if not, one must be used more | |
4707 | than once. */ | |
4708 | if (order[i] == order[i - 1]) | |
4709 | return 0; | |
4710 | ||
4711 | /* Is the memory address adjacent and ascending? */ | |
4712 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
4713 | return 0; | |
4714 | } | |
4715 | ||
4716 | if (base) | |
4717 | { | |
4718 | *base = base_reg; | |
4719 | ||
4720 | for (i = 0; i < nops; i++) | |
4721 | regs[i] = unsorted_regs[order[i]]; | |
4722 | ||
4723 | *load_offset = unsorted_offsets[order[0]]; | |
4724 | } | |
4725 | ||
4726 | if (unsorted_offsets[order[0]] == 0) | |
4727 | return 1; /* ldmia */ | |
4728 | ||
4729 | if (unsorted_offsets[order[0]] == 4) | |
4730 | return 2; /* ldmib */ | |
4731 | ||
4732 | if (unsorted_offsets[order[nops - 1]] == 0) | |
4733 | return 3; /* ldmda */ | |
4734 | ||
4735 | if (unsorted_offsets[order[nops - 1]] == -4) | |
4736 | return 4; /* ldmdb */ | |
4737 | ||
949d79eb RE |
4738 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm |
4739 | if the offset isn't small enough. The reason 2 ldrs are faster | |
4740 | is because these ARMs are able to do more than one cache access | |
4741 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
4742 | whilst the ARM8 has a double bandwidth cache. This means that | |
4743 | these cores can do both an instruction fetch and a data fetch in | |
4744 | a single cycle, so the trick of calculating the address into a | |
4745 | scratch register (one of the result regs) and then doing a load | |
4746 | multiple actually becomes slower (and no smaller in code size). | |
4747 | That is the transformation | |
6cc8c0b3 NC |
4748 | |
4749 | ldr rd1, [rbase + offset] | |
4750 | ldr rd2, [rbase + offset + 4] | |
4751 | ||
4752 | to | |
4753 | ||
4754 | add rd1, rbase, offset | |
4755 | ldmia rd1, {rd1, rd2} | |
4756 | ||
949d79eb RE |
4757 | produces worse code -- '3 cycles + any stalls on rd2' instead of |
4758 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
4759 | access per cycle, the first sequence could never complete in less | |
4760 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
4761 | would make better use of sequential accesses if not hitting the | |
4762 | cache. | |
4763 | ||
4764 | We cheat here and test 'arm_ld_sched' which we currently know to | |
4765 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
4766 | changes, then the test below needs to be reworked. */ | |
f5a1b0d2 | 4767 | if (nops == 2 && arm_ld_sched) |
b36ba79f RE |
4768 | return 0; |
4769 | ||
84ed5e79 RE |
4770 | /* Can't do it without setting up the offset, only do this if it takes |
4771 | no more than one insn. */ | |
4772 | return (const_ok_for_arm (unsorted_offsets[order[0]]) | |
4773 | || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; | |
4774 | } | |
4775 | ||
cd2b33d0 | 4776 | const char * |
e32bac5b | 4777 | emit_ldm_seq (rtx *operands, int nops) |
84ed5e79 RE |
4778 | { |
4779 | int regs[4]; | |
4780 | int base_reg; | |
4781 | HOST_WIDE_INT offset; | |
4782 | char buf[100]; | |
4783 | int i; | |
4784 | ||
4785 | switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
4786 | { | |
4787 | case 1: | |
4788 | strcpy (buf, "ldm%?ia\t"); | |
4789 | break; | |
4790 | ||
4791 | case 2: | |
4792 | strcpy (buf, "ldm%?ib\t"); | |
4793 | break; | |
4794 | ||
4795 | case 3: | |
4796 | strcpy (buf, "ldm%?da\t"); | |
4797 | break; | |
4798 | ||
4799 | case 4: | |
4800 | strcpy (buf, "ldm%?db\t"); | |
4801 | break; | |
4802 | ||
4803 | case 5: | |
4804 | if (offset >= 0) | |
4805 | sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
4806 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
4807 | (long) offset); | |
4808 | else | |
4809 | sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
4810 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
4811 | (long) -offset); | |
4812 | output_asm_insn (buf, operands); | |
4813 | base_reg = regs[0]; | |
4814 | strcpy (buf, "ldm%?ia\t"); | |
4815 | break; | |
4816 | ||
4817 | default: | |
4818 | abort (); | |
4819 | } | |
4820 | ||
4821 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | |
4822 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | |
4823 | ||
4824 | for (i = 1; i < nops; i++) | |
4825 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
4826 | reg_names[regs[i]]); | |
4827 | ||
4828 | strcat (buf, "}\t%@ phole ldm"); | |
4829 | ||
4830 | output_asm_insn (buf, operands); | |
4831 | return ""; | |
4832 | } | |
4833 | ||
4834 | int | |
e32bac5b RE |
4835 | store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
4836 | HOST_WIDE_INT * load_offset) | |
84ed5e79 RE |
4837 | { |
4838 | int unsorted_regs[4]; | |
4839 | HOST_WIDE_INT unsorted_offsets[4]; | |
4840 | int order[4]; | |
ad076f4e | 4841 | int base_reg = -1; |
84ed5e79 RE |
4842 | int i; |
4843 | ||
4844 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | |
4845 | extended if required. */ | |
4846 | if (nops < 2 || nops > 4) | |
4847 | abort (); | |
4848 | ||
4849 | /* Loop over the operands and check that the memory references are | |
4850 | suitable (ie immediate offsets from the same base register). At | |
4851 | the same time, extract the target register, and the memory | |
4852 | offsets. */ | |
4853 | for (i = 0; i < nops; i++) | |
4854 | { | |
4855 | rtx reg; | |
4856 | rtx offset; | |
4857 | ||
56636818 JL |
4858 | /* Convert a subreg of a mem into the mem itself. */ |
4859 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 4860 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 4861 | |
84ed5e79 RE |
4862 | if (GET_CODE (operands[nops + i]) != MEM) |
4863 | abort (); | |
4864 | ||
4865 | /* Don't reorder volatile memory references; it doesn't seem worth | |
4866 | looking for the case where the order is ok anyway. */ | |
4867 | if (MEM_VOLATILE_P (operands[nops + i])) | |
4868 | return 0; | |
4869 | ||
4870 | offset = const0_rtx; | |
4871 | ||
4872 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
4873 | || (GET_CODE (reg) == SUBREG | |
4874 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
4875 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
4876 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
4877 | == REG) | |
4878 | || (GET_CODE (reg) == SUBREG | |
4879 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
4880 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
4881 | == CONST_INT))) | |
4882 | { | |
4883 | if (i == 0) | |
4884 | { | |
62b10bbc | 4885 | base_reg = REGNO (reg); |
84ed5e79 RE |
4886 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
4887 | ? REGNO (operands[i]) | |
4888 | : REGNO (SUBREG_REG (operands[i]))); | |
4889 | order[0] = 0; | |
4890 | } | |
4891 | else | |
4892 | { | |
6354dc9b | 4893 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
4894 | /* Not addressed from the same base register. */ |
4895 | return 0; | |
4896 | ||
4897 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
4898 | ? REGNO (operands[i]) | |
4899 | : REGNO (SUBREG_REG (operands[i]))); | |
4900 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
4901 | order[0] = i; | |
4902 | } | |
4903 | ||
4904 | /* If it isn't an integer register, then we can't do this. */ | |
4905 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | |
4906 | return 0; | |
4907 | ||
4908 | unsorted_offsets[i] = INTVAL (offset); | |
4909 | } | |
4910 | else | |
4911 | /* Not a suitable memory address. */ | |
4912 | return 0; | |
4913 | } | |
4914 | ||
4915 | /* All the useful information has now been extracted from the | |
4916 | operands into unsorted_regs and unsorted_offsets; additionally, | |
4917 | order[0] has been set to the lowest numbered register in the | |
4918 | list. Sort the registers into order, and check that the memory | |
4919 | offsets are ascending and adjacent. */ | |
4920 | ||
4921 | for (i = 1; i < nops; i++) | |
4922 | { | |
4923 | int j; | |
4924 | ||
4925 | order[i] = order[i - 1]; | |
4926 | for (j = 0; j < nops; j++) | |
4927 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
4928 | && (order[i] == order[i - 1] | |
4929 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
4930 | order[i] = j; | |
4931 | ||
4932 | /* Have we found a suitable register? if not, one must be used more | |
4933 | than once. */ | |
4934 | if (order[i] == order[i - 1]) | |
4935 | return 0; | |
4936 | ||
4937 | /* Is the memory address adjacent and ascending? */ | |
4938 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
4939 | return 0; | |
4940 | } | |
4941 | ||
4942 | if (base) | |
4943 | { | |
4944 | *base = base_reg; | |
4945 | ||
4946 | for (i = 0; i < nops; i++) | |
4947 | regs[i] = unsorted_regs[order[i]]; | |
4948 | ||
4949 | *load_offset = unsorted_offsets[order[0]]; | |
4950 | } | |
4951 | ||
4952 | if (unsorted_offsets[order[0]] == 0) | |
4953 | return 1; /* stmia */ | |
4954 | ||
4955 | if (unsorted_offsets[order[0]] == 4) | |
4956 | return 2; /* stmib */ | |
4957 | ||
4958 | if (unsorted_offsets[order[nops - 1]] == 0) | |
4959 | return 3; /* stmda */ | |
4960 | ||
4961 | if (unsorted_offsets[order[nops - 1]] == -4) | |
4962 | return 4; /* stmdb */ | |
4963 | ||
4964 | return 0; | |
4965 | } | |
4966 | ||
cd2b33d0 | 4967 | const char * |
e32bac5b | 4968 | emit_stm_seq (rtx *operands, int nops) |
84ed5e79 RE |
4969 | { |
4970 | int regs[4]; | |
4971 | int base_reg; | |
4972 | HOST_WIDE_INT offset; | |
4973 | char buf[100]; | |
4974 | int i; | |
4975 | ||
4976 | switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
4977 | { | |
4978 | case 1: | |
4979 | strcpy (buf, "stm%?ia\t"); | |
4980 | break; | |
4981 | ||
4982 | case 2: | |
4983 | strcpy (buf, "stm%?ib\t"); | |
4984 | break; | |
4985 | ||
4986 | case 3: | |
4987 | strcpy (buf, "stm%?da\t"); | |
4988 | break; | |
4989 | ||
4990 | case 4: | |
4991 | strcpy (buf, "stm%?db\t"); | |
4992 | break; | |
4993 | ||
4994 | default: | |
4995 | abort (); | |
4996 | } | |
4997 | ||
4998 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | |
4999 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | |
5000 | ||
5001 | for (i = 1; i < nops; i++) | |
5002 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
5003 | reg_names[regs[i]]); | |
5004 | ||
5005 | strcat (buf, "}\t%@ phole stm"); | |
5006 | ||
5007 | output_asm_insn (buf, operands); | |
5008 | return ""; | |
5009 | } | |
5010 | ||
e2c671ba | 5011 | int |
e32bac5b | 5012 | multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e2c671ba RE |
5013 | { |
5014 | if (GET_CODE (op) != PARALLEL | |
5015 | || (GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
5016 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
b15bca31 | 5017 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) |
e2c671ba RE |
5018 | return 0; |
5019 | ||
5020 | return 1; | |
5021 | } | |
ff9940b0 | 5022 | \f |
6354dc9b | 5023 | /* Routines for use in generating RTL. */ |
1d6e90ac | 5024 | |
f3bb6135 | 5025 | rtx |
e32bac5b RE |
5026 | arm_gen_load_multiple (int base_regno, int count, rtx from, int up, |
5027 | int write_back, int unchanging_p, int in_struct_p, | |
5028 | int scalar_p) | |
ff9940b0 RE |
5029 | { |
5030 | int i = 0, j; | |
5031 | rtx result; | |
5032 | int sign = up ? 1 : -1; | |
56636818 | 5033 | rtx mem; |
ff9940b0 | 5034 | |
d19fb8e3 NC |
5035 | /* XScale has load-store double instructions, but they have stricter |
5036 | alignment requirements than load-store multiple, so we can not | |
5037 | use them. | |
5038 | ||
5039 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
5040 | the pipeline until completion. | |
5041 | ||
5042 | NREGS CYCLES | |
5043 | 1 3 | |
5044 | 2 4 | |
5045 | 3 5 | |
5046 | 4 6 | |
5047 | ||
5048 | An ldr instruction takes 1-3 cycles, but does not block the | |
5049 | pipeline. | |
5050 | ||
5051 | NREGS CYCLES | |
5052 | 1 1-3 | |
5053 | 2 2-6 | |
5054 | 3 3-9 | |
5055 | 4 4-12 | |
5056 | ||
5057 | Best case ldr will always win. However, the more ldr instructions | |
5058 | we issue, the less likely we are to be able to schedule them well. | |
5059 | Using ldr instructions also increases code size. | |
5060 | ||
5061 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
5062 | for counts of 3 or 4 regs. */ | |
4b3c2e48 | 5063 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
5064 | { |
5065 | rtx seq; | |
5066 | ||
5067 | start_sequence (); | |
5068 | ||
5069 | for (i = 0; i < count; i++) | |
5070 | { | |
5071 | mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign)); | |
5072 | RTX_UNCHANGING_P (mem) = unchanging_p; | |
5073 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
5074 | MEM_SCALAR_P (mem) = scalar_p; | |
5075 | emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); | |
5076 | } | |
5077 | ||
5078 | if (write_back) | |
5079 | emit_move_insn (from, plus_constant (from, count * 4 * sign)); | |
5080 | ||
2f937369 | 5081 | seq = get_insns (); |
d19fb8e3 NC |
5082 | end_sequence (); |
5083 | ||
5084 | return seq; | |
5085 | } | |
5086 | ||
43cffd11 | 5087 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 5088 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 5089 | if (write_back) |
f3bb6135 | 5090 | { |
ff9940b0 | 5091 | XVECEXP (result, 0, 0) |
43cffd11 RE |
5092 | = gen_rtx_SET (GET_MODE (from), from, |
5093 | plus_constant (from, count * 4 * sign)); | |
ff9940b0 RE |
5094 | i = 1; |
5095 | count++; | |
f3bb6135 RE |
5096 | } |
5097 | ||
ff9940b0 | 5098 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 5099 | { |
43cffd11 | 5100 | mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign)); |
56636818 JL |
5101 | RTX_UNCHANGING_P (mem) = unchanging_p; |
5102 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
c6df88cb | 5103 | MEM_SCALAR_P (mem) = scalar_p; |
43cffd11 RE |
5104 | XVECEXP (result, 0, i) |
5105 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | |
f3bb6135 RE |
5106 | } |
5107 | ||
ff9940b0 RE |
5108 | return result; |
5109 | } | |
5110 | ||
f3bb6135 | 5111 | rtx |
e32bac5b RE |
5112 | arm_gen_store_multiple (int base_regno, int count, rtx to, int up, |
5113 | int write_back, int unchanging_p, int in_struct_p, | |
5114 | int scalar_p) | |
ff9940b0 RE |
5115 | { |
5116 | int i = 0, j; | |
5117 | rtx result; | |
5118 | int sign = up ? 1 : -1; | |
56636818 | 5119 | rtx mem; |
ff9940b0 | 5120 | |
d19fb8e3 NC |
5121 | /* See arm_gen_load_multiple for discussion of |
5122 | the pros/cons of ldm/stm usage for XScale. */ | |
4b3c2e48 | 5123 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
5124 | { |
5125 | rtx seq; | |
5126 | ||
5127 | start_sequence (); | |
5128 | ||
5129 | for (i = 0; i < count; i++) | |
5130 | { | |
5131 | mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign)); | |
5132 | RTX_UNCHANGING_P (mem) = unchanging_p; | |
5133 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
5134 | MEM_SCALAR_P (mem) = scalar_p; | |
5135 | emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); | |
5136 | } | |
5137 | ||
5138 | if (write_back) | |
5139 | emit_move_insn (to, plus_constant (to, count * 4 * sign)); | |
5140 | ||
2f937369 | 5141 | seq = get_insns (); |
d19fb8e3 NC |
5142 | end_sequence (); |
5143 | ||
5144 | return seq; | |
5145 | } | |
5146 | ||
43cffd11 | 5147 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 5148 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 5149 | if (write_back) |
f3bb6135 | 5150 | { |
ff9940b0 | 5151 | XVECEXP (result, 0, 0) |
43cffd11 RE |
5152 | = gen_rtx_SET (GET_MODE (to), to, |
5153 | plus_constant (to, count * 4 * sign)); | |
ff9940b0 RE |
5154 | i = 1; |
5155 | count++; | |
f3bb6135 RE |
5156 | } |
5157 | ||
ff9940b0 | 5158 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 5159 | { |
43cffd11 | 5160 | mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign)); |
56636818 JL |
5161 | RTX_UNCHANGING_P (mem) = unchanging_p; |
5162 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
c6df88cb | 5163 | MEM_SCALAR_P (mem) = scalar_p; |
56636818 | 5164 | |
43cffd11 RE |
5165 | XVECEXP (result, 0, i) |
5166 | = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | |
f3bb6135 RE |
5167 | } |
5168 | ||
ff9940b0 RE |
5169 | return result; |
5170 | } | |
5171 | ||
880e2516 | 5172 | int |
e32bac5b | 5173 | arm_gen_movstrqi (rtx *operands) |
880e2516 RE |
5174 | { |
5175 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
ad076f4e | 5176 | int i; |
880e2516 | 5177 | rtx src, dst; |
ad076f4e | 5178 | rtx st_src, st_dst, fin_src, fin_dst; |
880e2516 | 5179 | rtx part_bytes_reg = NULL; |
56636818 JL |
5180 | rtx mem; |
5181 | int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p; | |
c6df88cb | 5182 | int dst_scalar_p, src_scalar_p; |
880e2516 RE |
5183 | |
5184 | if (GET_CODE (operands[2]) != CONST_INT | |
5185 | || GET_CODE (operands[3]) != CONST_INT | |
5186 | || INTVAL (operands[2]) > 64 | |
5187 | || INTVAL (operands[3]) & 3) | |
5188 | return 0; | |
5189 | ||
5190 | st_dst = XEXP (operands[0], 0); | |
5191 | st_src = XEXP (operands[1], 0); | |
56636818 JL |
5192 | |
5193 | dst_unchanging_p = RTX_UNCHANGING_P (operands[0]); | |
5194 | dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]); | |
c6df88cb | 5195 | dst_scalar_p = MEM_SCALAR_P (operands[0]); |
56636818 JL |
5196 | src_unchanging_p = RTX_UNCHANGING_P (operands[1]); |
5197 | src_in_struct_p = MEM_IN_STRUCT_P (operands[1]); | |
c6df88cb | 5198 | src_scalar_p = MEM_SCALAR_P (operands[1]); |
56636818 | 5199 | |
880e2516 RE |
5200 | fin_dst = dst = copy_to_mode_reg (SImode, st_dst); |
5201 | fin_src = src = copy_to_mode_reg (SImode, st_src); | |
5202 | ||
e9d7b180 | 5203 | in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
5204 | out_words_to_go = INTVAL (operands[2]) / 4; |
5205 | last_bytes = INTVAL (operands[2]) & 3; | |
5206 | ||
5207 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 5208 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
5209 | |
5210 | for (i = 0; in_words_to_go >= 2; i+=4) | |
5211 | { | |
bd9c7e23 | 5212 | if (in_words_to_go > 4) |
56636818 | 5213 | emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, |
c6df88cb MM |
5214 | src_unchanging_p, |
5215 | src_in_struct_p, | |
5216 | src_scalar_p)); | |
bd9c7e23 RE |
5217 | else |
5218 | emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, | |
56636818 | 5219 | FALSE, src_unchanging_p, |
c6df88cb | 5220 | src_in_struct_p, src_scalar_p)); |
bd9c7e23 | 5221 | |
880e2516 RE |
5222 | if (out_words_to_go) |
5223 | { | |
bd9c7e23 | 5224 | if (out_words_to_go > 4) |
56636818 JL |
5225 | emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, |
5226 | dst_unchanging_p, | |
c6df88cb MM |
5227 | dst_in_struct_p, |
5228 | dst_scalar_p)); | |
bd9c7e23 RE |
5229 | else if (out_words_to_go != 1) |
5230 | emit_insn (arm_gen_store_multiple (0, out_words_to_go, | |
5231 | dst, TRUE, | |
5232 | (last_bytes == 0 | |
56636818 JL |
5233 | ? FALSE : TRUE), |
5234 | dst_unchanging_p, | |
c6df88cb MM |
5235 | dst_in_struct_p, |
5236 | dst_scalar_p)); | |
880e2516 RE |
5237 | else |
5238 | { | |
43cffd11 | 5239 | mem = gen_rtx_MEM (SImode, dst); |
56636818 JL |
5240 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
5241 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 5242 | MEM_SCALAR_P (mem) = dst_scalar_p; |
43cffd11 | 5243 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 RE |
5244 | if (last_bytes != 0) |
5245 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
880e2516 RE |
5246 | } |
5247 | } | |
5248 | ||
5249 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
5250 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
5251 | } | |
5252 | ||
5253 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
5254 | if (out_words_to_go) | |
62b10bbc NC |
5255 | { |
5256 | rtx sreg; | |
5257 | ||
5258 | mem = gen_rtx_MEM (SImode, src); | |
5259 | RTX_UNCHANGING_P (mem) = src_unchanging_p; | |
5260 | MEM_IN_STRUCT_P (mem) = src_in_struct_p; | |
5261 | MEM_SCALAR_P (mem) = src_scalar_p; | |
5262 | emit_move_insn (sreg = gen_reg_rtx (SImode), mem); | |
5263 | emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4)); | |
5264 | ||
5265 | mem = gen_rtx_MEM (SImode, dst); | |
5266 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; | |
5267 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
5268 | MEM_SCALAR_P (mem) = dst_scalar_p; | |
5269 | emit_move_insn (mem, sreg); | |
5270 | emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4)); | |
5271 | in_words_to_go--; | |
5272 | ||
5273 | if (in_words_to_go) /* Sanity check */ | |
5274 | abort (); | |
5275 | } | |
880e2516 RE |
5276 | |
5277 | if (in_words_to_go) | |
5278 | { | |
5279 | if (in_words_to_go < 0) | |
5280 | abort (); | |
5281 | ||
43cffd11 | 5282 | mem = gen_rtx_MEM (SImode, src); |
56636818 JL |
5283 | RTX_UNCHANGING_P (mem) = src_unchanging_p; |
5284 | MEM_IN_STRUCT_P (mem) = src_in_struct_p; | |
c6df88cb | 5285 | MEM_SCALAR_P (mem) = src_scalar_p; |
56636818 | 5286 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
5287 | } |
5288 | ||
d5b7b3ae RE |
5289 | if (last_bytes && part_bytes_reg == NULL) |
5290 | abort (); | |
5291 | ||
880e2516 RE |
5292 | if (BYTES_BIG_ENDIAN && last_bytes) |
5293 | { | |
5294 | rtx tmp = gen_reg_rtx (SImode); | |
5295 | ||
6354dc9b | 5296 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
5297 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
5298 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 RE |
5299 | part_bytes_reg = tmp; |
5300 | ||
5301 | while (last_bytes) | |
5302 | { | |
43cffd11 | 5303 | mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1)); |
56636818 JL |
5304 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
5305 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 5306 | MEM_SCALAR_P (mem) = dst_scalar_p; |
5d5603e2 BS |
5307 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
5308 | ||
880e2516 RE |
5309 | if (--last_bytes) |
5310 | { | |
5311 | tmp = gen_reg_rtx (SImode); | |
5312 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
5313 | part_bytes_reg = tmp; | |
5314 | } | |
5315 | } | |
5316 | ||
5317 | } | |
5318 | else | |
5319 | { | |
d5b7b3ae | 5320 | if (last_bytes > 1) |
880e2516 | 5321 | { |
d5b7b3ae | 5322 | mem = gen_rtx_MEM (HImode, dst); |
56636818 JL |
5323 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
5324 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 5325 | MEM_SCALAR_P (mem) = dst_scalar_p; |
5d5603e2 | 5326 | emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); |
d5b7b3ae RE |
5327 | last_bytes -= 2; |
5328 | if (last_bytes) | |
880e2516 RE |
5329 | { |
5330 | rtx tmp = gen_reg_rtx (SImode); | |
bd9c7e23 | 5331 | |
d5b7b3ae RE |
5332 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (2))); |
5333 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); | |
880e2516 RE |
5334 | part_bytes_reg = tmp; |
5335 | } | |
5336 | } | |
d5b7b3ae RE |
5337 | |
5338 | if (last_bytes) | |
5339 | { | |
5340 | mem = gen_rtx_MEM (QImode, dst); | |
5341 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; | |
5342 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
5343 | MEM_SCALAR_P (mem) = dst_scalar_p; | |
5d5603e2 | 5344 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
d5b7b3ae | 5345 | } |
880e2516 RE |
5346 | } |
5347 | ||
5348 | return 1; | |
5349 | } | |
5350 | ||
5165176d RE |
5351 | /* Generate a memory reference for a half word, such that it will be loaded |
5352 | into the top 16 bits of the word. We can assume that the address is | |
5353 | known to be alignable and of the form reg, or plus (reg, const). */ | |
1d6e90ac | 5354 | |
5165176d | 5355 | rtx |
e32bac5b | 5356 | arm_gen_rotated_half_load (rtx memref) |
5165176d RE |
5357 | { |
5358 | HOST_WIDE_INT offset = 0; | |
5359 | rtx base = XEXP (memref, 0); | |
5360 | ||
5361 | if (GET_CODE (base) == PLUS) | |
5362 | { | |
5363 | offset = INTVAL (XEXP (base, 1)); | |
5364 | base = XEXP (base, 0); | |
5365 | } | |
5366 | ||
956d6950 | 5367 | /* If we aren't allowed to generate unaligned addresses, then fail. */ |
5f1e6755 | 5368 | if (TARGET_MMU_TRAPS |
5165176d RE |
5369 | && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))) |
5370 | return NULL; | |
5371 | ||
43cffd11 | 5372 | base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2)); |
5165176d RE |
5373 | |
5374 | if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2)) | |
5375 | return base; | |
5376 | ||
43cffd11 | 5377 | return gen_rtx_ROTATE (SImode, base, GEN_INT (16)); |
5165176d RE |
5378 | } |
5379 | ||
03f1640c RE |
5380 | /* Select a dominance comparison mode if possible for a test of the general |
5381 | form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. | |
5382 | COND_OR == DOM_CC_X_AND_Y => (X && Y) | |
5383 | COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) | |
5384 | COND_OR == DOM_CC_X_OR_Y => (X || Y) | |
5385 | In all cases OP will be either EQ or NE, but we don't need to know which | |
5386 | here. If we are unable to support a dominance comparison we return | |
5387 | CC mode. This will then fail to match for the RTL expressions that | |
5388 | generate this call. */ | |
03f1640c | 5389 | enum machine_mode |
e32bac5b | 5390 | arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) |
84ed5e79 RE |
5391 | { |
5392 | enum rtx_code cond1, cond2; | |
5393 | int swapped = 0; | |
5394 | ||
5395 | /* Currently we will probably get the wrong result if the individual | |
5396 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 5397 | reverse a comparison if necessary. */ |
84ed5e79 RE |
5398 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
5399 | != CCmode) | |
5400 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
5401 | != CCmode)) | |
5402 | return CCmode; | |
5403 | ||
1646cf41 RE |
5404 | /* The if_then_else variant of this tests the second condition if the |
5405 | first passes, but is true if the first fails. Reverse the first | |
5406 | condition to get a true "inclusive-or" expression. */ | |
03f1640c | 5407 | if (cond_or == DOM_CC_NX_OR_Y) |
84ed5e79 RE |
5408 | cond1 = reverse_condition (cond1); |
5409 | ||
5410 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
5411 | then we can't do this. */ | |
5412 | if (cond1 != cond2 | |
5895f793 RE |
5413 | && !comparison_dominates_p (cond1, cond2) |
5414 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
5415 | return CCmode; |
5416 | ||
5417 | if (swapped) | |
5418 | { | |
5419 | enum rtx_code temp = cond1; | |
5420 | cond1 = cond2; | |
5421 | cond2 = temp; | |
5422 | } | |
5423 | ||
5424 | switch (cond1) | |
5425 | { | |
5426 | case EQ: | |
03f1640c | 5427 | if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5428 | return CC_DEQmode; |
5429 | ||
5430 | switch (cond2) | |
5431 | { | |
5432 | case LE: return CC_DLEmode; | |
5433 | case LEU: return CC_DLEUmode; | |
5434 | case GE: return CC_DGEmode; | |
5435 | case GEU: return CC_DGEUmode; | |
ad076f4e | 5436 | default: break; |
84ed5e79 RE |
5437 | } |
5438 | ||
5439 | break; | |
5440 | ||
5441 | case LT: | |
03f1640c | 5442 | if (cond2 == LT || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5443 | return CC_DLTmode; |
5444 | if (cond2 == LE) | |
5445 | return CC_DLEmode; | |
5446 | if (cond2 == NE) | |
5447 | return CC_DNEmode; | |
5448 | break; | |
5449 | ||
5450 | case GT: | |
03f1640c | 5451 | if (cond2 == GT || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5452 | return CC_DGTmode; |
5453 | if (cond2 == GE) | |
5454 | return CC_DGEmode; | |
5455 | if (cond2 == NE) | |
5456 | return CC_DNEmode; | |
5457 | break; | |
5458 | ||
5459 | case LTU: | |
03f1640c | 5460 | if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5461 | return CC_DLTUmode; |
5462 | if (cond2 == LEU) | |
5463 | return CC_DLEUmode; | |
5464 | if (cond2 == NE) | |
5465 | return CC_DNEmode; | |
5466 | break; | |
5467 | ||
5468 | case GTU: | |
03f1640c | 5469 | if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5470 | return CC_DGTUmode; |
5471 | if (cond2 == GEU) | |
5472 | return CC_DGEUmode; | |
5473 | if (cond2 == NE) | |
5474 | return CC_DNEmode; | |
5475 | break; | |
5476 | ||
5477 | /* The remaining cases only occur when both comparisons are the | |
5478 | same. */ | |
5479 | case NE: | |
5480 | return CC_DNEmode; | |
5481 | ||
5482 | case LE: | |
5483 | return CC_DLEmode; | |
5484 | ||
5485 | case GE: | |
5486 | return CC_DGEmode; | |
5487 | ||
5488 | case LEU: | |
5489 | return CC_DLEUmode; | |
5490 | ||
5491 | case GEU: | |
5492 | return CC_DGEUmode; | |
ad076f4e RE |
5493 | |
5494 | default: | |
5495 | break; | |
84ed5e79 RE |
5496 | } |
5497 | ||
5498 | abort (); | |
5499 | } | |
5500 | ||
5501 | enum machine_mode | |
e32bac5b | 5502 | arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) |
84ed5e79 RE |
5503 | { |
5504 | /* All floating point compares return CCFP if it is an equality | |
5505 | comparison, and CCFPE otherwise. */ | |
5506 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
5507 | { |
5508 | switch (op) | |
5509 | { | |
5510 | case EQ: | |
5511 | case NE: | |
5512 | case UNORDERED: | |
5513 | case ORDERED: | |
5514 | case UNLT: | |
5515 | case UNLE: | |
5516 | case UNGT: | |
5517 | case UNGE: | |
5518 | case UNEQ: | |
5519 | case LTGT: | |
5520 | return CCFPmode; | |
5521 | ||
5522 | case LT: | |
5523 | case LE: | |
5524 | case GT: | |
5525 | case GE: | |
9b6b54e2 NC |
5526 | if (TARGET_CIRRUS) |
5527 | return CCFPmode; | |
e45b72c4 RE |
5528 | return CCFPEmode; |
5529 | ||
5530 | default: | |
5531 | abort (); | |
5532 | } | |
5533 | } | |
84ed5e79 RE |
5534 | |
5535 | /* A compare with a shifted operand. Because of canonicalization, the | |
5536 | comparison will have to be swapped when we emit the assembler. */ | |
5537 | if (GET_MODE (y) == SImode && GET_CODE (y) == REG | |
5538 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
5539 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
5540 | || GET_CODE (x) == ROTATERT)) | |
5541 | return CC_SWPmode; | |
5542 | ||
956d6950 JL |
5543 | /* This is a special case that is used by combine to allow a |
5544 | comparison of a shifted byte load to be split into a zero-extend | |
84ed5e79 | 5545 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 5546 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
5547 | if (GET_MODE (x) == SImode |
5548 | && GET_CODE (x) == ASHIFT | |
5549 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
5550 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
5551 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
5552 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
5553 | && (op == EQ || op == NE | |
5554 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
5555 | && GET_CODE (y) == CONST_INT) | |
5556 | return CC_Zmode; | |
5557 | ||
1646cf41 RE |
5558 | /* A construct for a conditional compare, if the false arm contains |
5559 | 0, then both conditions must be true, otherwise either condition | |
5560 | must be true. Not all conditions are possible, so CCmode is | |
5561 | returned if it can't be done. */ | |
5562 | if (GET_CODE (x) == IF_THEN_ELSE | |
5563 | && (XEXP (x, 2) == const0_rtx | |
5564 | || XEXP (x, 2) == const1_rtx) | |
5565 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
5566 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') | |
03f1640c RE |
5567 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
5568 | INTVAL (XEXP (x, 2))); | |
1646cf41 RE |
5569 | |
5570 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
5571 | if (GET_CODE (x) == AND | |
5572 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
5573 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') | |
03f1640c RE |
5574 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
5575 | DOM_CC_X_AND_Y); | |
1646cf41 RE |
5576 | |
5577 | if (GET_CODE (x) == IOR | |
5578 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
5579 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') | |
03f1640c RE |
5580 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
5581 | DOM_CC_X_OR_Y); | |
1646cf41 | 5582 | |
84ed5e79 RE |
5583 | /* An operation that sets the condition codes as a side-effect, the |
5584 | V flag is not set correctly, so we can only use comparisons where | |
5585 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
5586 | instead. */ | |
5587 | if (GET_MODE (x) == SImode | |
5588 | && y == const0_rtx | |
5589 | && (op == EQ || op == NE || op == LT || op == GE) | |
5590 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
5591 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
5592 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
5593 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
5594 | || GET_CODE (x) == LSHIFTRT | |
5595 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
5596 | || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT)) | |
5597 | return CC_NOOVmode; | |
5598 | ||
84ed5e79 RE |
5599 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
5600 | return CC_Zmode; | |
5601 | ||
bd9c7e23 RE |
5602 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
5603 | && GET_CODE (x) == PLUS | |
5604 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
5605 | return CC_Cmode; | |
5606 | ||
84ed5e79 RE |
5607 | return CCmode; |
5608 | } | |
5609 | ||
ff9940b0 RE |
5610 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
5611 | return the rtx for register 0 in the proper mode. FP means this is a | |
5612 | floating point compare: I don't think that it is needed on the arm. */ | |
ff9940b0 | 5613 | rtx |
e32bac5b | 5614 | arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
ff9940b0 RE |
5615 | { |
5616 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); | |
d5b7b3ae | 5617 | rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); |
ff9940b0 | 5618 | |
43cffd11 RE |
5619 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
5620 | gen_rtx_COMPARE (mode, x, y))); | |
ff9940b0 RE |
5621 | |
5622 | return cc_reg; | |
5623 | } | |
5624 | ||
fcd53748 JT |
5625 | /* Generate a sequence of insns that will generate the correct return |
5626 | address mask depending on the physical architecture that the program | |
5627 | is running on. */ | |
fcd53748 | 5628 | rtx |
e32bac5b | 5629 | arm_gen_return_addr_mask (void) |
fcd53748 JT |
5630 | { |
5631 | rtx reg = gen_reg_rtx (Pmode); | |
5632 | ||
5633 | emit_insn (gen_return_addr_mask (reg)); | |
5634 | return reg; | |
5635 | } | |
5636 | ||
0a81f500 | 5637 | void |
e32bac5b | 5638 | arm_reload_in_hi (rtx *operands) |
0a81f500 | 5639 | { |
f9cc092a RE |
5640 | rtx ref = operands[1]; |
5641 | rtx base, scratch; | |
5642 | HOST_WIDE_INT offset = 0; | |
5643 | ||
5644 | if (GET_CODE (ref) == SUBREG) | |
5645 | { | |
ddef6bc7 | 5646 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
5647 | ref = SUBREG_REG (ref); |
5648 | } | |
5649 | ||
5650 | if (GET_CODE (ref) == REG) | |
5651 | { | |
5652 | /* We have a pseudo which has been spilt onto the stack; there | |
5653 | are two cases here: the first where there is a simple | |
5654 | stack-slot replacement and a second where the stack-slot is | |
5655 | out of range, or is used as a subreg. */ | |
5656 | if (reg_equiv_mem[REGNO (ref)]) | |
5657 | { | |
5658 | ref = reg_equiv_mem[REGNO (ref)]; | |
5659 | base = find_replacement (&XEXP (ref, 0)); | |
5660 | } | |
5661 | else | |
6354dc9b | 5662 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
5663 | base = reg_equiv_address[REGNO (ref)]; |
5664 | } | |
5665 | else | |
5666 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 5667 | |
e5e809f4 JL |
5668 | /* Handle the case where the address is too complex to be offset by 1. */ |
5669 | if (GET_CODE (base) == MINUS | |
5670 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
5671 | { | |
f9cc092a | 5672 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 5673 | |
43cffd11 | 5674 | emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); |
e5e809f4 JL |
5675 | base = base_plus; |
5676 | } | |
f9cc092a RE |
5677 | else if (GET_CODE (base) == PLUS) |
5678 | { | |
6354dc9b | 5679 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
5680 | HOST_WIDE_INT hi, lo; |
5681 | ||
5682 | offset += INTVAL (XEXP (base, 1)); | |
5683 | base = XEXP (base, 0); | |
5684 | ||
6354dc9b | 5685 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
5686 | /* Valid range for lo is -4095 -> 4095 */ |
5687 | lo = (offset >= 0 | |
5688 | ? (offset & 0xfff) | |
5689 | : -((-offset) & 0xfff)); | |
5690 | ||
5691 | /* Corner case, if lo is the max offset then we would be out of range | |
5692 | once we have added the additional 1 below, so bump the msb into the | |
5693 | pre-loading insn(s). */ | |
5694 | if (lo == 4095) | |
5695 | lo &= 0x7ff; | |
5696 | ||
30cf4896 KG |
5697 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
5698 | ^ (HOST_WIDE_INT) 0x80000000) | |
5699 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a RE |
5700 | |
5701 | if (hi + lo != offset) | |
5702 | abort (); | |
5703 | ||
5704 | if (hi != 0) | |
5705 | { | |
5706 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
5707 | ||
5708 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 5709 | that require more than one insn. */ |
f9cc092a RE |
5710 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
5711 | base = base_plus; | |
5712 | offset = lo; | |
5713 | } | |
5714 | } | |
e5e809f4 | 5715 | |
3a1944a6 RE |
5716 | /* Operands[2] may overlap operands[0] (though it won't overlap |
5717 | operands[1]), that's why we asked for a DImode reg -- so we can | |
5718 | use the bit that does not overlap. */ | |
5719 | if (REGNO (operands[2]) == REGNO (operands[0])) | |
5720 | scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
5721 | else | |
5722 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
5723 | ||
f9cc092a RE |
5724 | emit_insn (gen_zero_extendqisi2 (scratch, |
5725 | gen_rtx_MEM (QImode, | |
5726 | plus_constant (base, | |
5727 | offset)))); | |
43cffd11 RE |
5728 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
5729 | gen_rtx_MEM (QImode, | |
f9cc092a RE |
5730 | plus_constant (base, |
5731 | offset + 1)))); | |
5895f793 | 5732 | if (!BYTES_BIG_ENDIAN) |
43cffd11 RE |
5733 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), |
5734 | gen_rtx_IOR (SImode, | |
5735 | gen_rtx_ASHIFT | |
5736 | (SImode, | |
5737 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
5738 | GEN_INT (8)), | |
f9cc092a | 5739 | scratch))); |
0a81f500 | 5740 | else |
43cffd11 RE |
5741 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), |
5742 | gen_rtx_IOR (SImode, | |
f9cc092a | 5743 | gen_rtx_ASHIFT (SImode, scratch, |
43cffd11 RE |
5744 | GEN_INT (8)), |
5745 | gen_rtx_SUBREG (SImode, operands[0], | |
5746 | 0)))); | |
0a81f500 RE |
5747 | } |
5748 | ||
72ac76be | 5749 | /* Handle storing a half-word to memory during reload by synthesizing as two |
f9cc092a RE |
5750 | byte stores. Take care not to clobber the input values until after we |
5751 | have moved them somewhere safe. This code assumes that if the DImode | |
5752 | scratch in operands[2] overlaps either the input value or output address | |
5753 | in some way, then that value must die in this insn (we absolutely need | |
5754 | two scratch registers for some corner cases). */ | |
f3bb6135 | 5755 | void |
e32bac5b | 5756 | arm_reload_out_hi (rtx *operands) |
af48348a | 5757 | { |
f9cc092a RE |
5758 | rtx ref = operands[0]; |
5759 | rtx outval = operands[1]; | |
5760 | rtx base, scratch; | |
5761 | HOST_WIDE_INT offset = 0; | |
5762 | ||
5763 | if (GET_CODE (ref) == SUBREG) | |
5764 | { | |
ddef6bc7 | 5765 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
5766 | ref = SUBREG_REG (ref); |
5767 | } | |
5768 | ||
f9cc092a RE |
5769 | if (GET_CODE (ref) == REG) |
5770 | { | |
5771 | /* We have a pseudo which has been spilt onto the stack; there | |
5772 | are two cases here: the first where there is a simple | |
5773 | stack-slot replacement and a second where the stack-slot is | |
5774 | out of range, or is used as a subreg. */ | |
5775 | if (reg_equiv_mem[REGNO (ref)]) | |
5776 | { | |
5777 | ref = reg_equiv_mem[REGNO (ref)]; | |
5778 | base = find_replacement (&XEXP (ref, 0)); | |
5779 | } | |
5780 | else | |
6354dc9b | 5781 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
5782 | base = reg_equiv_address[REGNO (ref)]; |
5783 | } | |
5784 | else | |
5785 | base = find_replacement (&XEXP (ref, 0)); | |
5786 | ||
5787 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
5788 | ||
5789 | /* Handle the case where the address is too complex to be offset by 1. */ | |
5790 | if (GET_CODE (base) == MINUS | |
5791 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
5792 | { | |
5793 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
5794 | ||
5795 | /* Be careful not to destroy OUTVAL. */ | |
5796 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
5797 | { | |
5798 | /* Updating base_plus might destroy outval, see if we can | |
5799 | swap the scratch and base_plus. */ | |
5895f793 | 5800 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
5801 | { |
5802 | rtx tmp = scratch; | |
5803 | scratch = base_plus; | |
5804 | base_plus = tmp; | |
5805 | } | |
5806 | else | |
5807 | { | |
5808 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
5809 | ||
5810 | /* Be conservative and copy OUTVAL into the scratch now, | |
5811 | this should only be necessary if outval is a subreg | |
5812 | of something larger than a word. */ | |
5813 | /* XXX Might this clobber base? I can't see how it can, | |
5814 | since scratch is known to overlap with OUTVAL, and | |
5815 | must be wider than a word. */ | |
5816 | emit_insn (gen_movhi (scratch_hi, outval)); | |
5817 | outval = scratch_hi; | |
5818 | } | |
5819 | } | |
5820 | ||
5821 | emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); | |
5822 | base = base_plus; | |
5823 | } | |
5824 | else if (GET_CODE (base) == PLUS) | |
5825 | { | |
6354dc9b | 5826 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
5827 | HOST_WIDE_INT hi, lo; |
5828 | ||
5829 | offset += INTVAL (XEXP (base, 1)); | |
5830 | base = XEXP (base, 0); | |
5831 | ||
6354dc9b | 5832 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
5833 | /* Valid range for lo is -4095 -> 4095 */ |
5834 | lo = (offset >= 0 | |
5835 | ? (offset & 0xfff) | |
5836 | : -((-offset) & 0xfff)); | |
5837 | ||
5838 | /* Corner case, if lo is the max offset then we would be out of range | |
5839 | once we have added the additional 1 below, so bump the msb into the | |
5840 | pre-loading insn(s). */ | |
5841 | if (lo == 4095) | |
5842 | lo &= 0x7ff; | |
5843 | ||
30cf4896 KG |
5844 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
5845 | ^ (HOST_WIDE_INT) 0x80000000) | |
5846 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a RE |
5847 | |
5848 | if (hi + lo != offset) | |
5849 | abort (); | |
5850 | ||
5851 | if (hi != 0) | |
5852 | { | |
5853 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
5854 | ||
5855 | /* Be careful not to destroy OUTVAL. */ | |
5856 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
5857 | { | |
5858 | /* Updating base_plus might destroy outval, see if we | |
5859 | can swap the scratch and base_plus. */ | |
5895f793 | 5860 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
5861 | { |
5862 | rtx tmp = scratch; | |
5863 | scratch = base_plus; | |
5864 | base_plus = tmp; | |
5865 | } | |
5866 | else | |
5867 | { | |
5868 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
5869 | ||
5870 | /* Be conservative and copy outval into scratch now, | |
5871 | this should only be necessary if outval is a | |
5872 | subreg of something larger than a word. */ | |
5873 | /* XXX Might this clobber base? I can't see how it | |
5874 | can, since scratch is known to overlap with | |
5875 | outval. */ | |
5876 | emit_insn (gen_movhi (scratch_hi, outval)); | |
5877 | outval = scratch_hi; | |
5878 | } | |
5879 | } | |
5880 | ||
5881 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 5882 | that require more than one insn. */ |
f9cc092a RE |
5883 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
5884 | base = base_plus; | |
5885 | offset = lo; | |
5886 | } | |
5887 | } | |
af48348a | 5888 | |
b5cc037f RE |
5889 | if (BYTES_BIG_ENDIAN) |
5890 | { | |
f9cc092a RE |
5891 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
5892 | plus_constant (base, offset + 1)), | |
5d5603e2 | 5893 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
5894 | emit_insn (gen_lshrsi3 (scratch, |
5895 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 5896 | GEN_INT (8))); |
f9cc092a | 5897 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 5898 | gen_lowpart (QImode, scratch))); |
b5cc037f RE |
5899 | } |
5900 | else | |
5901 | { | |
f9cc092a | 5902 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 5903 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
5904 | emit_insn (gen_lshrsi3 (scratch, |
5905 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 5906 | GEN_INT (8))); |
f9cc092a RE |
5907 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
5908 | plus_constant (base, offset + 1)), | |
5d5603e2 | 5909 | gen_lowpart (QImode, scratch))); |
b5cc037f | 5910 | } |
af48348a | 5911 | } |
2b835d68 | 5912 | \f |
d5b7b3ae RE |
5913 | /* Print a symbolic form of X to the debug file, F. */ |
5914 | static void | |
e32bac5b | 5915 | arm_print_value (FILE *f, rtx x) |
d5b7b3ae RE |
5916 | { |
5917 | switch (GET_CODE (x)) | |
5918 | { | |
5919 | case CONST_INT: | |
5920 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
5921 | return; | |
5922 | ||
5923 | case CONST_DOUBLE: | |
5924 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
5925 | return; | |
5926 | ||
5a9335ef NC |
5927 | case CONST_VECTOR: |
5928 | { | |
5929 | int i; | |
5930 | ||
5931 | fprintf (f, "<"); | |
5932 | for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) | |
5933 | { | |
5934 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); | |
5935 | if (i < (CONST_VECTOR_NUNITS (x) - 1)) | |
5936 | fputc (',', f); | |
5937 | } | |
5938 | fprintf (f, ">"); | |
5939 | } | |
5940 | return; | |
5941 | ||
d5b7b3ae RE |
5942 | case CONST_STRING: |
5943 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
5944 | return; | |
5945 | ||
5946 | case SYMBOL_REF: | |
5947 | fprintf (f, "`%s'", XSTR (x, 0)); | |
5948 | return; | |
5949 | ||
5950 | case LABEL_REF: | |
5951 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
5952 | return; | |
5953 | ||
5954 | case CONST: | |
5955 | arm_print_value (f, XEXP (x, 0)); | |
5956 | return; | |
5957 | ||
5958 | case PLUS: | |
5959 | arm_print_value (f, XEXP (x, 0)); | |
5960 | fprintf (f, "+"); | |
5961 | arm_print_value (f, XEXP (x, 1)); | |
5962 | return; | |
5963 | ||
5964 | case PC: | |
5965 | fprintf (f, "pc"); | |
5966 | return; | |
5967 | ||
5968 | default: | |
5969 | fprintf (f, "????"); | |
5970 | return; | |
5971 | } | |
5972 | } | |
5973 | \f | |
2b835d68 | 5974 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 5975 | |
949d79eb RE |
5976 | /* Arm instructions cannot load a large constant directly into a |
5977 | register; they have to come from a pc relative load. The constant | |
5978 | must therefore be placed in the addressable range of the pc | |
5979 | relative load. Depending on the precise pc relative load | |
5980 | instruction the range is somewhere between 256 bytes and 4k. This | |
5981 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
5982 | generate code to branch around it. |
5983 | ||
949d79eb RE |
5984 | It is important to minimize this, since the branches will slow |
5985 | things down and make the code larger. | |
2b835d68 | 5986 | |
949d79eb RE |
5987 | Normally we can hide the table after an existing unconditional |
5988 | branch so that there is no interruption of the flow, but in the | |
5989 | worst case the code looks like this: | |
2b835d68 RE |
5990 | |
5991 | ldr rn, L1 | |
949d79eb | 5992 | ... |
2b835d68 RE |
5993 | b L2 |
5994 | align | |
5995 | L1: .long value | |
5996 | L2: | |
949d79eb | 5997 | ... |
2b835d68 | 5998 | |
2b835d68 | 5999 | ldr rn, L3 |
949d79eb | 6000 | ... |
2b835d68 RE |
6001 | b L4 |
6002 | align | |
2b835d68 RE |
6003 | L3: .long value |
6004 | L4: | |
949d79eb RE |
6005 | ... |
6006 | ||
6007 | We fix this by performing a scan after scheduling, which notices | |
6008 | which instructions need to have their operands fetched from the | |
6009 | constant table and builds the table. | |
6010 | ||
6011 | The algorithm starts by building a table of all the constants that | |
6012 | need fixing up and all the natural barriers in the function (places | |
6013 | where a constant table can be dropped without breaking the flow). | |
6014 | For each fixup we note how far the pc-relative replacement will be | |
6015 | able to reach and the offset of the instruction into the function. | |
6016 | ||
6017 | Having built the table we then group the fixes together to form | |
6018 | tables that are as large as possible (subject to addressing | |
6019 | constraints) and emit each table of constants after the last | |
6020 | barrier that is within range of all the instructions in the group. | |
6021 | If a group does not contain a barrier, then we forcibly create one | |
6022 | by inserting a jump instruction into the flow. Once the table has | |
6023 | been inserted, the insns are then modified to reference the | |
6024 | relevant entry in the pool. | |
6025 | ||
6354dc9b | 6026 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 6027 | |
d5b7b3ae | 6028 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
6029 | aligning the pools to the start of cache lines; this alignment |
6030 | would need to be taken into account when calculating addressability | |
6354dc9b | 6031 | of a pool. */ |
2b835d68 | 6032 | |
d5b7b3ae RE |
6033 | /* These typedefs are located at the start of this file, so that |
6034 | they can be used in the prototypes there. This comment is to | |
6035 | remind readers of that fact so that the following structures | |
6036 | can be understood more easily. | |
6037 | ||
6038 | typedef struct minipool_node Mnode; | |
6039 | typedef struct minipool_fixup Mfix; */ | |
6040 | ||
6041 | struct minipool_node | |
6042 | { | |
6043 | /* Doubly linked chain of entries. */ | |
6044 | Mnode * next; | |
6045 | Mnode * prev; | |
6046 | /* The maximum offset into the code that this entry can be placed. While | |
6047 | pushing fixes for forward references, all entries are sorted in order | |
6048 | of increasing max_address. */ | |
6049 | HOST_WIDE_INT max_address; | |
5519a4f9 | 6050 | /* Similarly for an entry inserted for a backwards ref. */ |
d5b7b3ae RE |
6051 | HOST_WIDE_INT min_address; |
6052 | /* The number of fixes referencing this entry. This can become zero | |
6053 | if we "unpush" an entry. In this case we ignore the entry when we | |
6054 | come to emit the code. */ | |
6055 | int refcount; | |
6056 | /* The offset from the start of the minipool. */ | |
6057 | HOST_WIDE_INT offset; | |
6058 | /* The value in table. */ | |
6059 | rtx value; | |
6060 | /* The mode of value. */ | |
6061 | enum machine_mode mode; | |
5a9335ef NC |
6062 | /* The size of the value. With iWMMXt enabled |
6063 | sizes > 4 also imply an alignment of 8-bytes. */ | |
d5b7b3ae RE |
6064 | int fix_size; |
6065 | }; | |
6066 | ||
6067 | struct minipool_fixup | |
2b835d68 | 6068 | { |
d5b7b3ae RE |
6069 | Mfix * next; |
6070 | rtx insn; | |
6071 | HOST_WIDE_INT address; | |
6072 | rtx * loc; | |
6073 | enum machine_mode mode; | |
6074 | int fix_size; | |
6075 | rtx value; | |
6076 | Mnode * minipool; | |
6077 | HOST_WIDE_INT forwards; | |
6078 | HOST_WIDE_INT backwards; | |
6079 | }; | |
2b835d68 | 6080 | |
d5b7b3ae RE |
6081 | /* Fixes less than a word need padding out to a word boundary. */ |
6082 | #define MINIPOOL_FIX_SIZE(mode) \ | |
6083 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 6084 | |
d5b7b3ae RE |
6085 | static Mnode * minipool_vector_head; |
6086 | static Mnode * minipool_vector_tail; | |
6087 | static rtx minipool_vector_label; | |
332072db | 6088 | |
d5b7b3ae RE |
6089 | /* The linked list of all minipool fixes required for this function. */ |
6090 | Mfix * minipool_fix_head; | |
6091 | Mfix * minipool_fix_tail; | |
6092 | /* The fix entry for the current minipool, once it has been placed. */ | |
6093 | Mfix * minipool_barrier; | |
6094 | ||
6095 | /* Determines if INSN is the start of a jump table. Returns the end | |
6096 | of the TABLE or NULL_RTX. */ | |
6097 | static rtx | |
e32bac5b | 6098 | is_jump_table (rtx insn) |
2b835d68 | 6099 | { |
d5b7b3ae | 6100 | rtx table; |
da6558fd | 6101 | |
d5b7b3ae RE |
6102 | if (GET_CODE (insn) == JUMP_INSN |
6103 | && JUMP_LABEL (insn) != NULL | |
6104 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
6105 | == next_real_insn (insn)) | |
6106 | && table != NULL | |
6107 | && GET_CODE (table) == JUMP_INSN | |
6108 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
6109 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
6110 | return table; | |
6111 | ||
6112 | return NULL_RTX; | |
2b835d68 RE |
6113 | } |
6114 | ||
657d9449 RE |
6115 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
6116 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
6117 | #endif | |
6118 | ||
d5b7b3ae | 6119 | static HOST_WIDE_INT |
e32bac5b | 6120 | get_jump_table_size (rtx insn) |
2b835d68 | 6121 | { |
657d9449 RE |
6122 | /* ADDR_VECs only take room if read-only data does into the text |
6123 | section. */ | |
6124 | if (JUMP_TABLES_IN_TEXT_SECTION | |
d48bc59a | 6125 | #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP) |
657d9449 RE |
6126 | || 1 |
6127 | #endif | |
6128 | ) | |
6129 | { | |
6130 | rtx body = PATTERN (insn); | |
6131 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
2b835d68 | 6132 | |
657d9449 RE |
6133 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt); |
6134 | } | |
6135 | ||
6136 | return 0; | |
d5b7b3ae | 6137 | } |
2b835d68 | 6138 | |
d5b7b3ae RE |
6139 | /* Move a minipool fix MP from its current location to before MAX_MP. |
6140 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
6141 | contrains may need updating. */ | |
6142 | static Mnode * | |
e32bac5b RE |
6143 | move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, |
6144 | HOST_WIDE_INT max_address) | |
d5b7b3ae RE |
6145 | { |
6146 | /* This should never be true and the code below assumes these are | |
6147 | different. */ | |
6148 | if (mp == max_mp) | |
6149 | abort (); | |
6150 | ||
6151 | if (max_mp == NULL) | |
6152 | { | |
6153 | if (max_address < mp->max_address) | |
6154 | mp->max_address = max_address; | |
6155 | } | |
6156 | else | |
2b835d68 | 6157 | { |
d5b7b3ae RE |
6158 | if (max_address > max_mp->max_address - mp->fix_size) |
6159 | mp->max_address = max_mp->max_address - mp->fix_size; | |
6160 | else | |
6161 | mp->max_address = max_address; | |
2b835d68 | 6162 | |
d5b7b3ae RE |
6163 | /* Unlink MP from its current position. Since max_mp is non-null, |
6164 | mp->prev must be non-null. */ | |
6165 | mp->prev->next = mp->next; | |
6166 | if (mp->next != NULL) | |
6167 | mp->next->prev = mp->prev; | |
6168 | else | |
6169 | minipool_vector_tail = mp->prev; | |
2b835d68 | 6170 | |
d5b7b3ae RE |
6171 | /* Re-insert it before MAX_MP. */ |
6172 | mp->next = max_mp; | |
6173 | mp->prev = max_mp->prev; | |
6174 | max_mp->prev = mp; | |
6175 | ||
6176 | if (mp->prev != NULL) | |
6177 | mp->prev->next = mp; | |
6178 | else | |
6179 | minipool_vector_head = mp; | |
6180 | } | |
2b835d68 | 6181 | |
d5b7b3ae RE |
6182 | /* Save the new entry. */ |
6183 | max_mp = mp; | |
6184 | ||
d6a7951f | 6185 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
6186 | required. */ |
6187 | while (mp->prev != NULL | |
6188 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
6189 | { | |
6190 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
6191 | mp = mp->prev; | |
2b835d68 RE |
6192 | } |
6193 | ||
d5b7b3ae | 6194 | return max_mp; |
2b835d68 RE |
6195 | } |
6196 | ||
d5b7b3ae RE |
6197 | /* Add a constant to the minipool for a forward reference. Returns the |
6198 | node added or NULL if the constant will not fit in this pool. */ | |
6199 | static Mnode * | |
e32bac5b | 6200 | add_minipool_forward_ref (Mfix *fix) |
d5b7b3ae RE |
6201 | { |
6202 | /* If set, max_mp is the first pool_entry that has a lower | |
6203 | constraint than the one we are trying to add. */ | |
6204 | Mnode * max_mp = NULL; | |
6205 | HOST_WIDE_INT max_address = fix->address + fix->forwards; | |
6206 | Mnode * mp; | |
6207 | ||
6208 | /* If this fix's address is greater than the address of the first | |
6209 | entry, then we can't put the fix in this pool. We subtract the | |
6210 | size of the current fix to ensure that if the table is fully | |
6211 | packed we still have enough room to insert this value by suffling | |
6212 | the other fixes forwards. */ | |
6213 | if (minipool_vector_head && | |
6214 | fix->address >= minipool_vector_head->max_address - fix->fix_size) | |
6215 | return NULL; | |
2b835d68 | 6216 | |
d5b7b3ae RE |
6217 | /* Scan the pool to see if a constant with the same value has |
6218 | already been added. While we are doing this, also note the | |
6219 | location where we must insert the constant if it doesn't already | |
6220 | exist. */ | |
6221 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
6222 | { | |
6223 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
6224 | && fix->mode == mp->mode | |
6225 | && (GET_CODE (fix->value) != CODE_LABEL | |
6226 | || (CODE_LABEL_NUMBER (fix->value) | |
6227 | == CODE_LABEL_NUMBER (mp->value))) | |
6228 | && rtx_equal_p (fix->value, mp->value)) | |
6229 | { | |
6230 | /* More than one fix references this entry. */ | |
6231 | mp->refcount++; | |
6232 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
6233 | } | |
6234 | ||
6235 | /* Note the insertion point if necessary. */ | |
6236 | if (max_mp == NULL | |
6237 | && mp->max_address > max_address) | |
6238 | max_mp = mp; | |
5a9335ef NC |
6239 | |
6240 | /* If we are inserting an 8-bytes aligned quantity and | |
6241 | we have not already found an insertion point, then | |
6242 | make sure that all such 8-byte aligned quantities are | |
6243 | placed at the start of the pool. */ | |
6244 | if (TARGET_REALLY_IWMMXT | |
6245 | && max_mp == NULL | |
6246 | && fix->fix_size == 8 | |
6247 | && mp->fix_size != 8) | |
6248 | { | |
6249 | max_mp = mp; | |
6250 | max_address = mp->max_address; | |
6251 | } | |
d5b7b3ae RE |
6252 | } |
6253 | ||
6254 | /* The value is not currently in the minipool, so we need to create | |
6255 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
6256 | the end of the list since the placement is less constrained than | |
6257 | any existing entry. Otherwise, we insert the new fix before | |
6bc82793 | 6258 | MAX_MP and, if necessary, adjust the constraints on the other |
d5b7b3ae RE |
6259 | entries. */ |
6260 | mp = xmalloc (sizeof (* mp)); | |
6261 | mp->fix_size = fix->fix_size; | |
6262 | mp->mode = fix->mode; | |
6263 | mp->value = fix->value; | |
6264 | mp->refcount = 1; | |
6265 | /* Not yet required for a backwards ref. */ | |
6266 | mp->min_address = -65536; | |
6267 | ||
6268 | if (max_mp == NULL) | |
6269 | { | |
6270 | mp->max_address = max_address; | |
6271 | mp->next = NULL; | |
6272 | mp->prev = minipool_vector_tail; | |
6273 | ||
6274 | if (mp->prev == NULL) | |
6275 | { | |
6276 | minipool_vector_head = mp; | |
6277 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 6278 | } |
2b835d68 | 6279 | else |
d5b7b3ae | 6280 | mp->prev->next = mp; |
2b835d68 | 6281 | |
d5b7b3ae RE |
6282 | minipool_vector_tail = mp; |
6283 | } | |
6284 | else | |
6285 | { | |
6286 | if (max_address > max_mp->max_address - mp->fix_size) | |
6287 | mp->max_address = max_mp->max_address - mp->fix_size; | |
6288 | else | |
6289 | mp->max_address = max_address; | |
6290 | ||
6291 | mp->next = max_mp; | |
6292 | mp->prev = max_mp->prev; | |
6293 | max_mp->prev = mp; | |
6294 | if (mp->prev != NULL) | |
6295 | mp->prev->next = mp; | |
6296 | else | |
6297 | minipool_vector_head = mp; | |
6298 | } | |
6299 | ||
6300 | /* Save the new entry. */ | |
6301 | max_mp = mp; | |
6302 | ||
d6a7951f | 6303 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
6304 | required. */ |
6305 | while (mp->prev != NULL | |
6306 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
6307 | { | |
6308 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
6309 | mp = mp->prev; | |
2b835d68 RE |
6310 | } |
6311 | ||
d5b7b3ae RE |
6312 | return max_mp; |
6313 | } | |
6314 | ||
6315 | static Mnode * | |
e32bac5b RE |
6316 | move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, |
6317 | HOST_WIDE_INT min_address) | |
d5b7b3ae RE |
6318 | { |
6319 | HOST_WIDE_INT offset; | |
6320 | ||
6321 | /* This should never be true, and the code below assumes these are | |
6322 | different. */ | |
6323 | if (mp == min_mp) | |
6324 | abort (); | |
6325 | ||
6326 | if (min_mp == NULL) | |
2b835d68 | 6327 | { |
d5b7b3ae RE |
6328 | if (min_address > mp->min_address) |
6329 | mp->min_address = min_address; | |
6330 | } | |
6331 | else | |
6332 | { | |
6333 | /* We will adjust this below if it is too loose. */ | |
6334 | mp->min_address = min_address; | |
6335 | ||
6336 | /* Unlink MP from its current position. Since min_mp is non-null, | |
6337 | mp->next must be non-null. */ | |
6338 | mp->next->prev = mp->prev; | |
6339 | if (mp->prev != NULL) | |
6340 | mp->prev->next = mp->next; | |
6341 | else | |
6342 | minipool_vector_head = mp->next; | |
6343 | ||
6344 | /* Reinsert it after MIN_MP. */ | |
6345 | mp->prev = min_mp; | |
6346 | mp->next = min_mp->next; | |
6347 | min_mp->next = mp; | |
6348 | if (mp->next != NULL) | |
6349 | mp->next->prev = mp; | |
2b835d68 | 6350 | else |
d5b7b3ae RE |
6351 | minipool_vector_tail = mp; |
6352 | } | |
6353 | ||
6354 | min_mp = mp; | |
6355 | ||
6356 | offset = 0; | |
6357 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
6358 | { | |
6359 | mp->offset = offset; | |
6360 | if (mp->refcount > 0) | |
6361 | offset += mp->fix_size; | |
6362 | ||
6363 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
6364 | mp->next->min_address = mp->min_address + mp->fix_size; | |
6365 | } | |
6366 | ||
6367 | return min_mp; | |
6368 | } | |
6369 | ||
6370 | /* Add a constant to the minipool for a backward reference. Returns the | |
6371 | node added or NULL if the constant will not fit in this pool. | |
6372 | ||
6373 | Note that the code for insertion for a backwards reference can be | |
6374 | somewhat confusing because the calculated offsets for each fix do | |
6375 | not take into account the size of the pool (which is still under | |
6376 | construction. */ | |
6377 | static Mnode * | |
e32bac5b | 6378 | add_minipool_backward_ref (Mfix *fix) |
d5b7b3ae RE |
6379 | { |
6380 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
6381 | than the one we are trying to add. */ | |
e32bac5b | 6382 | Mnode *min_mp = NULL; |
d5b7b3ae RE |
6383 | /* This can be negative, since it is only a constraint. */ |
6384 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
e32bac5b | 6385 | Mnode *mp; |
d5b7b3ae RE |
6386 | |
6387 | /* If we can't reach the current pool from this insn, or if we can't | |
6388 | insert this entry at the end of the pool without pushing other | |
6389 | fixes out of range, then we don't try. This ensures that we | |
6390 | can't fail later on. */ | |
6391 | if (min_address >= minipool_barrier->address | |
6392 | || (minipool_vector_tail->min_address + fix->fix_size | |
6393 | >= minipool_barrier->address)) | |
6394 | return NULL; | |
6395 | ||
6396 | /* Scan the pool to see if a constant with the same value has | |
6397 | already been added. While we are doing this, also note the | |
6398 | location where we must insert the constant if it doesn't already | |
6399 | exist. */ | |
6400 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
6401 | { | |
6402 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
6403 | && fix->mode == mp->mode | |
6404 | && (GET_CODE (fix->value) != CODE_LABEL | |
6405 | || (CODE_LABEL_NUMBER (fix->value) | |
6406 | == CODE_LABEL_NUMBER (mp->value))) | |
6407 | && rtx_equal_p (fix->value, mp->value) | |
6408 | /* Check that there is enough slack to move this entry to the | |
6409 | end of the table (this is conservative). */ | |
6410 | && (mp->max_address | |
6411 | > (minipool_barrier->address | |
6412 | + minipool_vector_tail->offset | |
6413 | + minipool_vector_tail->fix_size))) | |
6414 | { | |
6415 | mp->refcount++; | |
6416 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
6417 | } | |
6418 | ||
6419 | if (min_mp != NULL) | |
6420 | mp->min_address += fix->fix_size; | |
6421 | else | |
6422 | { | |
6423 | /* Note the insertion point if necessary. */ | |
6424 | if (mp->min_address < min_address) | |
5a9335ef NC |
6425 | { |
6426 | /* For now, we do not allow the insertion of 8-byte alignment | |
6427 | requiring nodes anywhere but at the start of the pool. */ | |
6428 | if (TARGET_REALLY_IWMMXT && fix->fix_size == 8 && mp->fix_size != 8) | |
6429 | return NULL; | |
6430 | else | |
6431 | min_mp = mp; | |
6432 | } | |
d5b7b3ae RE |
6433 | else if (mp->max_address |
6434 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
6435 | { | |
6436 | /* Inserting before this entry would push the fix beyond | |
6437 | its maximum address (which can happen if we have | |
6438 | re-located a forwards fix); force the new fix to come | |
6439 | after it. */ | |
6440 | min_mp = mp; | |
6441 | min_address = mp->min_address + fix->fix_size; | |
6442 | } | |
5a9335ef NC |
6443 | /* If we are inserting an 8-bytes aligned quantity and |
6444 | we have not already found an insertion point, then | |
6445 | make sure that all such 8-byte aligned quantities are | |
6446 | placed at the start of the pool. */ | |
6447 | else if (TARGET_REALLY_IWMMXT | |
6448 | && min_mp == NULL | |
6449 | && fix->fix_size == 8 | |
6450 | && mp->fix_size < 8) | |
6451 | { | |
6452 | min_mp = mp; | |
6453 | min_address = mp->min_address + fix->fix_size; | |
6454 | } | |
d5b7b3ae RE |
6455 | } |
6456 | } | |
6457 | ||
6458 | /* We need to create a new entry. */ | |
6459 | mp = xmalloc (sizeof (* mp)); | |
6460 | mp->fix_size = fix->fix_size; | |
6461 | mp->mode = fix->mode; | |
6462 | mp->value = fix->value; | |
6463 | mp->refcount = 1; | |
6464 | mp->max_address = minipool_barrier->address + 65536; | |
6465 | ||
6466 | mp->min_address = min_address; | |
6467 | ||
6468 | if (min_mp == NULL) | |
6469 | { | |
6470 | mp->prev = NULL; | |
6471 | mp->next = minipool_vector_head; | |
6472 | ||
6473 | if (mp->next == NULL) | |
6474 | { | |
6475 | minipool_vector_tail = mp; | |
6476 | minipool_vector_label = gen_label_rtx (); | |
6477 | } | |
6478 | else | |
6479 | mp->next->prev = mp; | |
6480 | ||
6481 | minipool_vector_head = mp; | |
6482 | } | |
6483 | else | |
6484 | { | |
6485 | mp->next = min_mp->next; | |
6486 | mp->prev = min_mp; | |
6487 | min_mp->next = mp; | |
da6558fd | 6488 | |
d5b7b3ae RE |
6489 | if (mp->next != NULL) |
6490 | mp->next->prev = mp; | |
6491 | else | |
6492 | minipool_vector_tail = mp; | |
6493 | } | |
6494 | ||
6495 | /* Save the new entry. */ | |
6496 | min_mp = mp; | |
6497 | ||
6498 | if (mp->prev) | |
6499 | mp = mp->prev; | |
6500 | else | |
6501 | mp->offset = 0; | |
6502 | ||
6503 | /* Scan over the following entries and adjust their offsets. */ | |
6504 | while (mp->next != NULL) | |
6505 | { | |
6506 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
6507 | mp->next->min_address = mp->min_address + mp->fix_size; | |
6508 | ||
6509 | if (mp->refcount) | |
6510 | mp->next->offset = mp->offset + mp->fix_size; | |
6511 | else | |
6512 | mp->next->offset = mp->offset; | |
6513 | ||
6514 | mp = mp->next; | |
6515 | } | |
6516 | ||
6517 | return min_mp; | |
6518 | } | |
6519 | ||
6520 | static void | |
e32bac5b | 6521 | assign_minipool_offsets (Mfix *barrier) |
d5b7b3ae RE |
6522 | { |
6523 | HOST_WIDE_INT offset = 0; | |
e32bac5b | 6524 | Mnode *mp; |
d5b7b3ae RE |
6525 | |
6526 | minipool_barrier = barrier; | |
6527 | ||
6528 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
6529 | { | |
6530 | mp->offset = offset; | |
da6558fd | 6531 | |
d5b7b3ae RE |
6532 | if (mp->refcount > 0) |
6533 | offset += mp->fix_size; | |
6534 | } | |
6535 | } | |
6536 | ||
6537 | /* Output the literal table */ | |
6538 | static void | |
e32bac5b | 6539 | dump_minipool (rtx scan) |
d5b7b3ae | 6540 | { |
5a9335ef NC |
6541 | Mnode * mp; |
6542 | Mnode * nmp; | |
6543 | int align64 = 0; | |
6544 | ||
6545 | if (TARGET_REALLY_IWMMXT) | |
6546 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
6547 | if (mp->refcount > 0 && mp->fix_size == 8) | |
6548 | { | |
6549 | align64 = 1; | |
6550 | break; | |
6551 | } | |
d5b7b3ae RE |
6552 | |
6553 | if (rtl_dump_file) | |
6554 | fprintf (rtl_dump_file, | |
5a9335ef NC |
6555 | ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", |
6556 | INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); | |
d5b7b3ae RE |
6557 | |
6558 | scan = emit_label_after (gen_label_rtx (), scan); | |
5a9335ef | 6559 | scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); |
d5b7b3ae RE |
6560 | scan = emit_label_after (minipool_vector_label, scan); |
6561 | ||
6562 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
6563 | { | |
6564 | if (mp->refcount > 0) | |
6565 | { | |
6566 | if (rtl_dump_file) | |
6567 | { | |
6568 | fprintf (rtl_dump_file, | |
6569 | ";; Offset %u, min %ld, max %ld ", | |
6570 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
6571 | (unsigned long) mp->max_address); | |
6572 | arm_print_value (rtl_dump_file, mp->value); | |
6573 | fputc ('\n', rtl_dump_file); | |
6574 | } | |
6575 | ||
6576 | switch (mp->fix_size) | |
6577 | { | |
6578 | #ifdef HAVE_consttable_1 | |
6579 | case 1: | |
6580 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
6581 | break; | |
6582 | ||
6583 | #endif | |
6584 | #ifdef HAVE_consttable_2 | |
6585 | case 2: | |
6586 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
6587 | break; | |
6588 | ||
6589 | #endif | |
6590 | #ifdef HAVE_consttable_4 | |
6591 | case 4: | |
6592 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
6593 | break; | |
6594 | ||
6595 | #endif | |
6596 | #ifdef HAVE_consttable_8 | |
6597 | case 8: | |
6598 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
6599 | break; | |
6600 | ||
6601 | #endif | |
6602 | default: | |
6603 | abort (); | |
6604 | break; | |
6605 | } | |
6606 | } | |
6607 | ||
6608 | nmp = mp->next; | |
6609 | free (mp); | |
2b835d68 RE |
6610 | } |
6611 | ||
d5b7b3ae RE |
6612 | minipool_vector_head = minipool_vector_tail = NULL; |
6613 | scan = emit_insn_after (gen_consttable_end (), scan); | |
6614 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
6615 | } |
6616 | ||
d5b7b3ae RE |
6617 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
6618 | static int | |
e32bac5b | 6619 | arm_barrier_cost (rtx insn) |
949d79eb | 6620 | { |
d5b7b3ae RE |
6621 | /* Basing the location of the pool on the loop depth is preferable, |
6622 | but at the moment, the basic block information seems to be | |
6623 | corrupt by this stage of the compilation. */ | |
6624 | int base_cost = 50; | |
6625 | rtx next = next_nonnote_insn (insn); | |
6626 | ||
6627 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
6628 | base_cost -= 20; | |
6629 | ||
6630 | switch (GET_CODE (insn)) | |
6631 | { | |
6632 | case CODE_LABEL: | |
6633 | /* It will always be better to place the table before the label, rather | |
6634 | than after it. */ | |
6635 | return 50; | |
949d79eb | 6636 | |
d5b7b3ae RE |
6637 | case INSN: |
6638 | case CALL_INSN: | |
6639 | return base_cost; | |
6640 | ||
6641 | case JUMP_INSN: | |
6642 | return base_cost - 10; | |
6643 | ||
6644 | default: | |
6645 | return base_cost + 10; | |
6646 | } | |
6647 | } | |
6648 | ||
6649 | /* Find the best place in the insn stream in the range | |
6650 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
6651 | Create the barrier by inserting a jump and add a new fix entry for | |
6652 | it. */ | |
6653 | static Mfix * | |
e32bac5b | 6654 | create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) |
d5b7b3ae RE |
6655 | { |
6656 | HOST_WIDE_INT count = 0; | |
6657 | rtx barrier; | |
6658 | rtx from = fix->insn; | |
6659 | rtx selected = from; | |
6660 | int selected_cost; | |
6661 | HOST_WIDE_INT selected_address; | |
6662 | Mfix * new_fix; | |
6663 | HOST_WIDE_INT max_count = max_address - fix->address; | |
6664 | rtx label = gen_label_rtx (); | |
6665 | ||
6666 | selected_cost = arm_barrier_cost (from); | |
6667 | selected_address = fix->address; | |
6668 | ||
6669 | while (from && count < max_count) | |
6670 | { | |
6671 | rtx tmp; | |
6672 | int new_cost; | |
6673 | ||
6674 | /* This code shouldn't have been called if there was a natural barrier | |
6675 | within range. */ | |
6676 | if (GET_CODE (from) == BARRIER) | |
6677 | abort (); | |
6678 | ||
6679 | /* Count the length of this insn. */ | |
6680 | count += get_attr_length (from); | |
6681 | ||
6682 | /* If there is a jump table, add its length. */ | |
6683 | tmp = is_jump_table (from); | |
6684 | if (tmp != NULL) | |
6685 | { | |
6686 | count += get_jump_table_size (tmp); | |
6687 | ||
6688 | /* Jump tables aren't in a basic block, so base the cost on | |
6689 | the dispatch insn. If we select this location, we will | |
6690 | still put the pool after the table. */ | |
6691 | new_cost = arm_barrier_cost (from); | |
6692 | ||
6693 | if (count < max_count && new_cost <= selected_cost) | |
6694 | { | |
6695 | selected = tmp; | |
6696 | selected_cost = new_cost; | |
6697 | selected_address = fix->address + count; | |
6698 | } | |
6699 | ||
6700 | /* Continue after the dispatch table. */ | |
6701 | from = NEXT_INSN (tmp); | |
6702 | continue; | |
6703 | } | |
6704 | ||
6705 | new_cost = arm_barrier_cost (from); | |
6706 | ||
6707 | if (count < max_count && new_cost <= selected_cost) | |
6708 | { | |
6709 | selected = from; | |
6710 | selected_cost = new_cost; | |
6711 | selected_address = fix->address + count; | |
6712 | } | |
6713 | ||
6714 | from = NEXT_INSN (from); | |
6715 | } | |
6716 | ||
6717 | /* Create a new JUMP_INSN that branches around a barrier. */ | |
6718 | from = emit_jump_insn_after (gen_jump (label), selected); | |
6719 | JUMP_LABEL (from) = label; | |
6720 | barrier = emit_barrier_after (from); | |
6721 | emit_label_after (label, barrier); | |
6722 | ||
6723 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 6724 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
6725 | new_fix->insn = barrier; |
6726 | new_fix->address = selected_address; | |
6727 | new_fix->next = fix->next; | |
6728 | fix->next = new_fix; | |
6729 | ||
6730 | return new_fix; | |
6731 | } | |
6732 | ||
6733 | /* Record that there is a natural barrier in the insn stream at | |
6734 | ADDRESS. */ | |
949d79eb | 6735 | static void |
e32bac5b | 6736 | push_minipool_barrier (rtx insn, HOST_WIDE_INT address) |
2b835d68 | 6737 | { |
c7319d87 | 6738 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 6739 | |
949d79eb RE |
6740 | fix->insn = insn; |
6741 | fix->address = address; | |
2b835d68 | 6742 | |
949d79eb RE |
6743 | fix->next = NULL; |
6744 | if (minipool_fix_head != NULL) | |
6745 | minipool_fix_tail->next = fix; | |
6746 | else | |
6747 | minipool_fix_head = fix; | |
6748 | ||
6749 | minipool_fix_tail = fix; | |
6750 | } | |
2b835d68 | 6751 | |
d5b7b3ae RE |
6752 | /* Record INSN, which will need fixing up to load a value from the |
6753 | minipool. ADDRESS is the offset of the insn since the start of the | |
6754 | function; LOC is a pointer to the part of the insn which requires | |
6755 | fixing; VALUE is the constant that must be loaded, which is of type | |
6756 | MODE. */ | |
949d79eb | 6757 | static void |
e32bac5b RE |
6758 | push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, |
6759 | enum machine_mode mode, rtx value) | |
949d79eb | 6760 | { |
c7319d87 | 6761 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb RE |
6762 | |
6763 | #ifdef AOF_ASSEMBLER | |
6764 | /* PIC symbol refereneces need to be converted into offsets into the | |
6765 | based area. */ | |
d5b7b3ae RE |
6766 | /* XXX This shouldn't be done here. */ |
6767 | if (flag_pic && GET_CODE (value) == SYMBOL_REF) | |
949d79eb RE |
6768 | value = aof_pic_entry (value); |
6769 | #endif /* AOF_ASSEMBLER */ | |
6770 | ||
6771 | fix->insn = insn; | |
6772 | fix->address = address; | |
6773 | fix->loc = loc; | |
6774 | fix->mode = mode; | |
d5b7b3ae | 6775 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 6776 | fix->value = value; |
d5b7b3ae RE |
6777 | fix->forwards = get_attr_pool_range (insn); |
6778 | fix->backwards = get_attr_neg_pool_range (insn); | |
6779 | fix->minipool = NULL; | |
949d79eb RE |
6780 | |
6781 | /* If an insn doesn't have a range defined for it, then it isn't | |
6782 | expecting to be reworked by this code. Better to abort now than | |
6783 | to generate duff assembly code. */ | |
d5b7b3ae | 6784 | if (fix->forwards == 0 && fix->backwards == 0) |
949d79eb RE |
6785 | abort (); |
6786 | ||
5a9335ef NC |
6787 | /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary. |
6788 | So there might be an empty word before the start of the pool. | |
6789 | Hence we reduce the forward range by 4 to allow for this | |
6790 | possibility. */ | |
6791 | if (TARGET_REALLY_IWMMXT && fix->fix_size == 8) | |
6792 | fix->forwards -= 4; | |
6793 | ||
d5b7b3ae RE |
6794 | if (rtl_dump_file) |
6795 | { | |
6796 | fprintf (rtl_dump_file, | |
6797 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", | |
6798 | GET_MODE_NAME (mode), | |
6799 | INSN_UID (insn), (unsigned long) address, | |
6800 | -1 * (long)fix->backwards, (long)fix->forwards); | |
6801 | arm_print_value (rtl_dump_file, fix->value); | |
6802 | fprintf (rtl_dump_file, "\n"); | |
6803 | } | |
6804 | ||
6354dc9b | 6805 | /* Add it to the chain of fixes. */ |
949d79eb | 6806 | fix->next = NULL; |
d5b7b3ae | 6807 | |
949d79eb RE |
6808 | if (minipool_fix_head != NULL) |
6809 | minipool_fix_tail->next = fix; | |
6810 | else | |
6811 | minipool_fix_head = fix; | |
6812 | ||
6813 | minipool_fix_tail = fix; | |
6814 | } | |
6815 | ||
f0375c66 NC |
6816 | /* Scan INSN and note any of its operands that need fixing. |
6817 | If DO_PUSHES is false we do not actually push any of the fixups | |
6818 | needed. The function returns TRUE is any fixups were needed/pushed. | |
6819 | This is used by arm_memory_load_p() which needs to know about loads | |
6820 | of constants that will be converted into minipool loads. */ | |
f0375c66 | 6821 | static bool |
e32bac5b | 6822 | note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) |
949d79eb | 6823 | { |
f0375c66 | 6824 | bool result = false; |
949d79eb RE |
6825 | int opno; |
6826 | ||
d5b7b3ae | 6827 | extract_insn (insn); |
949d79eb | 6828 | |
5895f793 | 6829 | if (!constrain_operands (1)) |
949d79eb RE |
6830 | fatal_insn_not_found (insn); |
6831 | ||
f0375c66 | 6832 | /* Fill in recog_op_alt with information about the constraints of this insn. */ |
949d79eb RE |
6833 | preprocess_constraints (); |
6834 | ||
1ccbefce | 6835 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 6836 | { |
6354dc9b | 6837 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 6838 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
6839 | continue; |
6840 | ||
6841 | /* If this alternative is a memory reference, then any mention | |
6842 | of constants in this alternative is really to fool reload | |
6843 | into allowing us to accept one there. We need to fix them up | |
6844 | now so that we output the right code. */ | |
6845 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
6846 | { | |
1ccbefce | 6847 | rtx op = recog_data.operand[opno]; |
949d79eb RE |
6848 | |
6849 | if (CONSTANT_P (op)) | |
f0375c66 NC |
6850 | { |
6851 | if (do_pushes) | |
6852 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
6853 | recog_data.operand_mode[opno], op); | |
6854 | result = true; | |
6855 | } | |
d5b7b3ae | 6856 | else if (GET_CODE (op) == MEM |
949d79eb RE |
6857 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
6858 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
f0375c66 NC |
6859 | { |
6860 | if (do_pushes) | |
6861 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
6862 | recog_data.operand_mode[opno], | |
6863 | get_pool_constant (XEXP (op, 0))); | |
6864 | ||
6865 | result = true; | |
6866 | } | |
949d79eb | 6867 | } |
2b835d68 | 6868 | } |
f0375c66 NC |
6869 | |
6870 | return result; | |
2b835d68 RE |
6871 | } |
6872 | ||
18dbd950 RS |
6873 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
6874 | load addresses a limited distance around the pc. We do some | |
6875 | special munging to move the constant pool values to the correct | |
6876 | point in the code. */ | |
18dbd950 | 6877 | static void |
e32bac5b | 6878 | arm_reorg (void) |
2b835d68 RE |
6879 | { |
6880 | rtx insn; | |
d5b7b3ae RE |
6881 | HOST_WIDE_INT address = 0; |
6882 | Mfix * fix; | |
ad076f4e | 6883 | |
949d79eb | 6884 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 6885 | |
949d79eb RE |
6886 | /* The first insn must always be a note, or the code below won't |
6887 | scan it properly. */ | |
18dbd950 RS |
6888 | insn = get_insns (); |
6889 | if (GET_CODE (insn) != NOTE) | |
949d79eb RE |
6890 | abort (); |
6891 | ||
6892 | /* Scan all the insns and record the operands that will need fixing. */ | |
18dbd950 | 6893 | for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) |
2b835d68 | 6894 | { |
9b6b54e2 | 6895 | if (TARGET_CIRRUS_FIX_INVALID_INSNS |
f0375c66 | 6896 | && (arm_cirrus_insn_p (insn) |
9b6b54e2 | 6897 | || GET_CODE (insn) == JUMP_INSN |
f0375c66 | 6898 | || arm_memory_load_p (insn))) |
9b6b54e2 NC |
6899 | cirrus_reorg (insn); |
6900 | ||
949d79eb | 6901 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 6902 | push_minipool_barrier (insn, address); |
f0375c66 | 6903 | else if (INSN_P (insn)) |
949d79eb RE |
6904 | { |
6905 | rtx table; | |
6906 | ||
f0375c66 | 6907 | note_invalid_constants (insn, address, true); |
949d79eb | 6908 | address += get_attr_length (insn); |
d5b7b3ae | 6909 | |
949d79eb RE |
6910 | /* If the insn is a vector jump, add the size of the table |
6911 | and skip the table. */ | |
d5b7b3ae | 6912 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 6913 | { |
d5b7b3ae | 6914 | address += get_jump_table_size (table); |
949d79eb RE |
6915 | insn = table; |
6916 | } | |
6917 | } | |
6918 | } | |
332072db | 6919 | |
d5b7b3ae RE |
6920 | fix = minipool_fix_head; |
6921 | ||
949d79eb | 6922 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 6923 | while (fix) |
949d79eb | 6924 | { |
d5b7b3ae RE |
6925 | Mfix * ftmp; |
6926 | Mfix * fdel; | |
6927 | Mfix * last_added_fix; | |
6928 | Mfix * last_barrier = NULL; | |
6929 | Mfix * this_fix; | |
949d79eb RE |
6930 | |
6931 | /* Skip any further barriers before the next fix. */ | |
6932 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
6933 | fix = fix->next; | |
6934 | ||
d5b7b3ae | 6935 | /* No more fixes. */ |
949d79eb RE |
6936 | if (fix == NULL) |
6937 | break; | |
332072db | 6938 | |
d5b7b3ae | 6939 | last_added_fix = NULL; |
2b835d68 | 6940 | |
d5b7b3ae | 6941 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 6942 | { |
949d79eb | 6943 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 6944 | { |
d5b7b3ae RE |
6945 | if (ftmp->address >= minipool_vector_head->max_address) |
6946 | break; | |
2b835d68 | 6947 | |
d5b7b3ae | 6948 | last_barrier = ftmp; |
2b835d68 | 6949 | } |
d5b7b3ae RE |
6950 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
6951 | break; | |
6952 | ||
6953 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 6954 | } |
949d79eb | 6955 | |
d5b7b3ae RE |
6956 | /* If we found a barrier, drop back to that; any fixes that we |
6957 | could have reached but come after the barrier will now go in | |
6958 | the next mini-pool. */ | |
949d79eb RE |
6959 | if (last_barrier != NULL) |
6960 | { | |
d5b7b3ae RE |
6961 | /* Reduce the refcount for those fixes that won't go into this |
6962 | pool after all. */ | |
6963 | for (fdel = last_barrier->next; | |
6964 | fdel && fdel != ftmp; | |
6965 | fdel = fdel->next) | |
6966 | { | |
6967 | fdel->minipool->refcount--; | |
6968 | fdel->minipool = NULL; | |
6969 | } | |
6970 | ||
949d79eb RE |
6971 | ftmp = last_barrier; |
6972 | } | |
6973 | else | |
2bfa88dc | 6974 | { |
d5b7b3ae RE |
6975 | /* ftmp is first fix that we can't fit into this pool and |
6976 | there no natural barriers that we could use. Insert a | |
6977 | new barrier in the code somewhere between the previous | |
6978 | fix and this one, and arrange to jump around it. */ | |
6979 | HOST_WIDE_INT max_address; | |
6980 | ||
6981 | /* The last item on the list of fixes must be a barrier, so | |
6982 | we can never run off the end of the list of fixes without | |
6983 | last_barrier being set. */ | |
6984 | if (ftmp == NULL) | |
6985 | abort (); | |
6986 | ||
6987 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
6988 | /* Check that there isn't another fix that is in range that |
6989 | we couldn't fit into this pool because the pool was | |
6990 | already too large: we need to put the pool before such an | |
6991 | instruction. */ | |
d5b7b3ae RE |
6992 | if (ftmp->address < max_address) |
6993 | max_address = ftmp->address; | |
6994 | ||
6995 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
6996 | } | |
6997 | ||
6998 | assign_minipool_offsets (last_barrier); | |
6999 | ||
7000 | while (ftmp) | |
7001 | { | |
7002 | if (GET_CODE (ftmp->insn) != BARRIER | |
7003 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
7004 | == NULL)) | |
7005 | break; | |
2bfa88dc | 7006 | |
d5b7b3ae | 7007 | ftmp = ftmp->next; |
2bfa88dc | 7008 | } |
949d79eb RE |
7009 | |
7010 | /* Scan over the fixes we have identified for this pool, fixing them | |
7011 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 7012 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
7013 | this_fix = this_fix->next) |
7014 | if (GET_CODE (this_fix->insn) != BARRIER) | |
7015 | { | |
949d79eb RE |
7016 | rtx addr |
7017 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, | |
7018 | minipool_vector_label), | |
d5b7b3ae | 7019 | this_fix->minipool->offset); |
949d79eb RE |
7020 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
7021 | } | |
7022 | ||
d5b7b3ae | 7023 | dump_minipool (last_barrier->insn); |
949d79eb | 7024 | fix = ftmp; |
2b835d68 | 7025 | } |
4b632bf1 | 7026 | |
949d79eb RE |
7027 | /* From now on we must synthesize any constants that we can't handle |
7028 | directly. This can happen if the RTL gets split during final | |
7029 | instruction generation. */ | |
4b632bf1 | 7030 | after_arm_reorg = 1; |
c7319d87 RE |
7031 | |
7032 | /* Free the minipool memory. */ | |
7033 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 7034 | } |
cce8749e CH |
7035 | \f |
7036 | /* Routines to output assembly language. */ | |
7037 | ||
f3bb6135 | 7038 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 7039 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 7040 | when cross compiling. */ |
cd2b33d0 | 7041 | const char * |
e32bac5b | 7042 | fp_immediate_constant (rtx x) |
ff9940b0 RE |
7043 | { |
7044 | REAL_VALUE_TYPE r; | |
7045 | int i; | |
7046 | ||
7047 | if (!fpa_consts_inited) | |
7048 | init_fpa_table (); | |
7049 | ||
7050 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
7051 | for (i = 0; i < 8; i++) | |
7052 | if (REAL_VALUES_EQUAL (r, values_fpa[i])) | |
7053 | return strings_fpa[i]; | |
f3bb6135 | 7054 | |
ff9940b0 RE |
7055 | abort (); |
7056 | } | |
7057 | ||
9997d19d | 7058 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
cd2b33d0 | 7059 | static const char * |
e32bac5b | 7060 | fp_const_from_val (REAL_VALUE_TYPE *r) |
9997d19d RE |
7061 | { |
7062 | int i; | |
7063 | ||
5895f793 | 7064 | if (!fpa_consts_inited) |
9997d19d RE |
7065 | init_fpa_table (); |
7066 | ||
7067 | for (i = 0; i < 8; i++) | |
7068 | if (REAL_VALUES_EQUAL (*r, values_fpa[i])) | |
7069 | return strings_fpa[i]; | |
7070 | ||
7071 | abort (); | |
7072 | } | |
ff9940b0 | 7073 | |
cce8749e CH |
7074 | /* Output the operands of a LDM/STM instruction to STREAM. |
7075 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 NC |
7076 | REG is the base register, either the frame pointer or the stack pointer, |
7077 | INSTR is the possibly suffixed load or store instruction. */ | |
d5b7b3ae | 7078 | static void |
e32bac5b | 7079 | print_multi_reg (FILE *stream, const char *instr, int reg, int mask) |
cce8749e CH |
7080 | { |
7081 | int i; | |
7082 | int not_first = FALSE; | |
7083 | ||
1d5473cb | 7084 | fputc ('\t', stream); |
dd18ae56 | 7085 | asm_fprintf (stream, instr, reg); |
1d5473cb | 7086 | fputs (", {", stream); |
62b10bbc | 7087 | |
d5b7b3ae | 7088 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
7089 | if (mask & (1 << i)) |
7090 | { | |
7091 | if (not_first) | |
7092 | fprintf (stream, ", "); | |
62b10bbc | 7093 | |
dd18ae56 | 7094 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
7095 | not_first = TRUE; |
7096 | } | |
f3bb6135 | 7097 | |
b17fe233 NC |
7098 | fprintf (stream, "}"); |
7099 | ||
7100 | /* Add a ^ character for the 26-bit ABI, but only if we were loading | |
1ce53769 NC |
7101 | the PC. Otherwise we would generate an UNPREDICTABLE instruction. |
7102 | Strictly speaking the instruction would be unpredicatble only if | |
7103 | we were writing back the base register as well, but since we never | |
7104 | want to generate an LDM type 2 instruction (register bank switching) | |
7105 | which is what you get if the PC is not being loaded, we do not need | |
7106 | to check for writeback. */ | |
b17fe233 | 7107 | if (! TARGET_APCS_32 |
1ce53769 | 7108 | && ((mask & (1 << PC_REGNUM)) != 0)) |
b17fe233 NC |
7109 | fprintf (stream, "^"); |
7110 | ||
7111 | fprintf (stream, "\n"); | |
f3bb6135 | 7112 | } |
cce8749e | 7113 | |
6354dc9b | 7114 | /* Output a 'call' insn. */ |
cd2b33d0 | 7115 | const char * |
e32bac5b | 7116 | output_call (rtx *operands) |
cce8749e | 7117 | { |
6354dc9b | 7118 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
cce8749e | 7119 | |
62b10bbc | 7120 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 7121 | { |
62b10bbc | 7122 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 7123 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 7124 | } |
62b10bbc | 7125 | |
1d5473cb | 7126 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
da6558fd | 7127 | |
6cfc7210 | 7128 | if (TARGET_INTERWORK) |
da6558fd NC |
7129 | output_asm_insn ("bx%?\t%0", operands); |
7130 | else | |
7131 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
7132 | ||
f3bb6135 RE |
7133 | return ""; |
7134 | } | |
cce8749e | 7135 | |
6354dc9b | 7136 | /* Output a 'call' insn that is a reference in memory. */ |
cd2b33d0 | 7137 | const char * |
e32bac5b | 7138 | output_call_mem (rtx *operands) |
ff9940b0 | 7139 | { |
6cfc7210 | 7140 | if (TARGET_INTERWORK) |
da6558fd NC |
7141 | { |
7142 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
7143 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
7144 | output_asm_insn ("bx%?\t%|ip", operands); | |
7145 | } | |
6ab5da80 RE |
7146 | else if (regno_use_in (LR_REGNUM, operands[0])) |
7147 | { | |
7148 | /* LR is used in the memory address. We load the address in the | |
7149 | first instruction. It's safe to use IP as the target of the | |
7150 | load since the call will kill it anyway. */ | |
7151 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
7152 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
7153 | output_asm_insn ("mov%?\t%|pc, %|ip", operands); | |
7154 | } | |
da6558fd NC |
7155 | else |
7156 | { | |
7157 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
7158 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
7159 | } | |
7160 | ||
f3bb6135 RE |
7161 | return ""; |
7162 | } | |
ff9940b0 RE |
7163 | |
7164 | ||
3b684012 RE |
7165 | /* Output a move from arm registers to an fpa registers. |
7166 | OPERANDS[0] is an fpa register. | |
ff9940b0 | 7167 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 7168 | const char * |
e32bac5b | 7169 | output_mov_long_double_fpa_from_arm (rtx *operands) |
ff9940b0 RE |
7170 | { |
7171 | int arm_reg0 = REGNO (operands[1]); | |
7172 | rtx ops[3]; | |
7173 | ||
62b10bbc NC |
7174 | if (arm_reg0 == IP_REGNUM) |
7175 | abort (); | |
f3bb6135 | 7176 | |
43cffd11 RE |
7177 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
7178 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
7179 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 7180 | |
1d5473cb RE |
7181 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops); |
7182 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); | |
62b10bbc | 7183 | |
f3bb6135 RE |
7184 | return ""; |
7185 | } | |
ff9940b0 | 7186 | |
3b684012 | 7187 | /* Output a move from an fpa register to arm registers. |
ff9940b0 | 7188 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 7189 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 7190 | const char * |
e32bac5b | 7191 | output_mov_long_double_arm_from_fpa (rtx *operands) |
ff9940b0 RE |
7192 | { |
7193 | int arm_reg0 = REGNO (operands[0]); | |
7194 | rtx ops[3]; | |
7195 | ||
62b10bbc NC |
7196 | if (arm_reg0 == IP_REGNUM) |
7197 | abort (); | |
f3bb6135 | 7198 | |
43cffd11 RE |
7199 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
7200 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
7201 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 7202 | |
1d5473cb RE |
7203 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
7204 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops); | |
f3bb6135 RE |
7205 | return ""; |
7206 | } | |
ff9940b0 RE |
7207 | |
7208 | /* Output a move from arm registers to arm registers of a long double | |
7209 | OPERANDS[0] is the destination. | |
7210 | OPERANDS[1] is the source. */ | |
cd2b33d0 | 7211 | const char * |
e32bac5b | 7212 | output_mov_long_double_arm_from_arm (rtx *operands) |
ff9940b0 | 7213 | { |
6354dc9b | 7214 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
7215 | int dest_start = REGNO (operands[0]); |
7216 | int src_start = REGNO (operands[1]); | |
7217 | rtx ops[2]; | |
7218 | int i; | |
7219 | ||
7220 | if (dest_start < src_start) | |
7221 | { | |
7222 | for (i = 0; i < 3; i++) | |
7223 | { | |
43cffd11 RE |
7224 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
7225 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 7226 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
7227 | } |
7228 | } | |
7229 | else | |
7230 | { | |
7231 | for (i = 2; i >= 0; i--) | |
7232 | { | |
43cffd11 RE |
7233 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
7234 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 7235 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
7236 | } |
7237 | } | |
f3bb6135 | 7238 | |
ff9940b0 RE |
7239 | return ""; |
7240 | } | |
7241 | ||
7242 | ||
3b684012 RE |
7243 | /* Output a move from arm registers to an fpa registers. |
7244 | OPERANDS[0] is an fpa register. | |
cce8749e | 7245 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 7246 | const char * |
e32bac5b | 7247 | output_mov_double_fpa_from_arm (rtx *operands) |
cce8749e CH |
7248 | { |
7249 | int arm_reg0 = REGNO (operands[1]); | |
7250 | rtx ops[2]; | |
7251 | ||
62b10bbc NC |
7252 | if (arm_reg0 == IP_REGNUM) |
7253 | abort (); | |
7254 | ||
43cffd11 RE |
7255 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
7256 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
7257 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops); |
7258 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); | |
f3bb6135 RE |
7259 | return ""; |
7260 | } | |
cce8749e | 7261 | |
3b684012 | 7262 | /* Output a move from an fpa register to arm registers. |
cce8749e | 7263 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 7264 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 7265 | const char * |
e32bac5b | 7266 | output_mov_double_arm_from_fpa (rtx *operands) |
cce8749e CH |
7267 | { |
7268 | int arm_reg0 = REGNO (operands[0]); | |
7269 | rtx ops[2]; | |
7270 | ||
62b10bbc NC |
7271 | if (arm_reg0 == IP_REGNUM) |
7272 | abort (); | |
f3bb6135 | 7273 | |
43cffd11 RE |
7274 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
7275 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
7276 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
7277 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops); | |
f3bb6135 RE |
7278 | return ""; |
7279 | } | |
cce8749e CH |
7280 | |
7281 | /* Output a move between double words. | |
7282 | It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM | |
7283 | or MEM<-REG and all MEMs must be offsettable addresses. */ | |
cd2b33d0 | 7284 | const char * |
e32bac5b | 7285 | output_move_double (rtx *operands) |
cce8749e CH |
7286 | { |
7287 | enum rtx_code code0 = GET_CODE (operands[0]); | |
7288 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 7289 | rtx otherops[3]; |
cce8749e CH |
7290 | |
7291 | if (code0 == REG) | |
7292 | { | |
7293 | int reg0 = REGNO (operands[0]); | |
7294 | ||
43cffd11 | 7295 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
aec3cfba | 7296 | |
cce8749e CH |
7297 | if (code1 == REG) |
7298 | { | |
7299 | int reg1 = REGNO (operands[1]); | |
62b10bbc NC |
7300 | if (reg1 == IP_REGNUM) |
7301 | abort (); | |
f3bb6135 | 7302 | |
6354dc9b | 7303 | /* Ensure the second source is not overwritten. */ |
c1c2bc04 | 7304 | if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1)) |
6cfc7210 | 7305 | output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands); |
cce8749e | 7306 | else |
6cfc7210 | 7307 | output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands); |
cce8749e | 7308 | } |
5a9335ef NC |
7309 | else if (code1 == CONST_VECTOR) |
7310 | { | |
7311 | HOST_WIDE_INT hint = 0; | |
7312 | ||
7313 | switch (GET_MODE (operands[1])) | |
7314 | { | |
7315 | case V2SImode: | |
7316 | otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1))); | |
7317 | operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0))); | |
7318 | break; | |
7319 | ||
7320 | case V4HImode: | |
7321 | if (BYTES_BIG_ENDIAN) | |
7322 | { | |
7323 | hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2)); | |
7324 | hint <<= 16; | |
7325 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); | |
7326 | } | |
7327 | else | |
7328 | { | |
7329 | hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3)); | |
7330 | hint <<= 16; | |
7331 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); | |
7332 | } | |
7333 | ||
7334 | otherops[1] = GEN_INT (hint); | |
7335 | hint = 0; | |
7336 | ||
7337 | if (BYTES_BIG_ENDIAN) | |
7338 | { | |
7339 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); | |
7340 | hint <<= 16; | |
7341 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); | |
7342 | } | |
7343 | else | |
7344 | { | |
7345 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); | |
7346 | hint <<= 16; | |
7347 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); | |
7348 | } | |
7349 | ||
7350 | operands[1] = GEN_INT (hint); | |
7351 | break; | |
7352 | ||
7353 | case V8QImode: | |
7354 | if (BYTES_BIG_ENDIAN) | |
7355 | { | |
7356 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4)); | |
7357 | hint <<= 8; | |
7358 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5)); | |
7359 | hint <<= 8; | |
7360 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6)); | |
7361 | hint <<= 8; | |
7362 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7)); | |
7363 | } | |
7364 | else | |
7365 | { | |
7366 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7)); | |
7367 | hint <<= 8; | |
7368 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6)); | |
7369 | hint <<= 8; | |
7370 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5)); | |
7371 | hint <<= 8; | |
7372 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4)); | |
7373 | } | |
7374 | ||
7375 | otherops[1] = GEN_INT (hint); | |
7376 | hint = 0; | |
7377 | ||
7378 | if (BYTES_BIG_ENDIAN) | |
7379 | { | |
7380 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); | |
7381 | hint <<= 8; | |
7382 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); | |
7383 | hint <<= 8; | |
7384 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); | |
7385 | hint <<= 8; | |
7386 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); | |
7387 | } | |
7388 | else | |
7389 | { | |
7390 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); | |
7391 | hint <<= 8; | |
7392 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); | |
7393 | hint <<= 8; | |
7394 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); | |
7395 | hint <<= 8; | |
7396 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); | |
7397 | } | |
7398 | ||
7399 | operands[1] = GEN_INT (hint); | |
7400 | break; | |
7401 | ||
7402 | default: | |
7403 | abort (); | |
7404 | } | |
7405 | output_mov_immediate (operands); | |
7406 | output_mov_immediate (otherops); | |
7407 | } | |
cce8749e CH |
7408 | else if (code1 == CONST_DOUBLE) |
7409 | { | |
226a5051 RE |
7410 | if (GET_MODE (operands[1]) == DFmode) |
7411 | { | |
b216cd4a | 7412 | REAL_VALUE_TYPE r; |
226a5051 | 7413 | long l[2]; |
226a5051 | 7414 | |
b216cd4a ZW |
7415 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); |
7416 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); | |
d5b7b3ae RE |
7417 | otherops[1] = GEN_INT (l[1]); |
7418 | operands[1] = GEN_INT (l[0]); | |
226a5051 | 7419 | } |
c1c2bc04 RE |
7420 | else if (GET_MODE (operands[1]) != VOIDmode) |
7421 | abort (); | |
7422 | else if (WORDS_BIG_ENDIAN) | |
7423 | { | |
c1c2bc04 RE |
7424 | otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); |
7425 | operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
7426 | } | |
226a5051 RE |
7427 | else |
7428 | { | |
7429 | otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
7430 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
7431 | } | |
6cfc7210 | 7432 | |
c1c2bc04 RE |
7433 | output_mov_immediate (operands); |
7434 | output_mov_immediate (otherops); | |
cce8749e CH |
7435 | } |
7436 | else if (code1 == CONST_INT) | |
7437 | { | |
56636818 JL |
7438 | #if HOST_BITS_PER_WIDE_INT > 32 |
7439 | /* If HOST_WIDE_INT is more than 32 bits, the intval tells us | |
7440 | what the upper word is. */ | |
7441 | if (WORDS_BIG_ENDIAN) | |
7442 | { | |
7443 | otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); | |
7444 | operands[1] = GEN_INT (INTVAL (operands[1]) >> 32); | |
7445 | } | |
7446 | else | |
7447 | { | |
7448 | otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32); | |
7449 | operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); | |
7450 | } | |
7451 | #else | |
6354dc9b | 7452 | /* Sign extend the intval into the high-order word. */ |
c1c2bc04 RE |
7453 | if (WORDS_BIG_ENDIAN) |
7454 | { | |
7455 | otherops[1] = operands[1]; | |
7456 | operands[1] = (INTVAL (operands[1]) < 0 | |
7457 | ? constm1_rtx : const0_rtx); | |
7458 | } | |
ff9940b0 | 7459 | else |
c1c2bc04 | 7460 | otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; |
56636818 | 7461 | #endif |
c1c2bc04 RE |
7462 | output_mov_immediate (otherops); |
7463 | output_mov_immediate (operands); | |
cce8749e CH |
7464 | } |
7465 | else if (code1 == MEM) | |
7466 | { | |
ff9940b0 | 7467 | switch (GET_CODE (XEXP (operands[1], 0))) |
cce8749e | 7468 | { |
ff9940b0 | 7469 | case REG: |
9997d19d | 7470 | output_asm_insn ("ldm%?ia\t%m1, %M0", operands); |
ff9940b0 | 7471 | break; |
2b835d68 | 7472 | |
ff9940b0 | 7473 | case PRE_INC: |
6354dc9b | 7474 | abort (); /* Should never happen now. */ |
ff9940b0 | 7475 | break; |
2b835d68 | 7476 | |
ff9940b0 | 7477 | case PRE_DEC: |
2b835d68 | 7478 | output_asm_insn ("ldm%?db\t%m1!, %M0", operands); |
ff9940b0 | 7479 | break; |
2b835d68 | 7480 | |
ff9940b0 | 7481 | case POST_INC: |
9997d19d | 7482 | output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); |
ff9940b0 | 7483 | break; |
2b835d68 | 7484 | |
ff9940b0 | 7485 | case POST_DEC: |
6354dc9b | 7486 | abort (); /* Should never happen now. */ |
ff9940b0 | 7487 | break; |
2b835d68 RE |
7488 | |
7489 | case LABEL_REF: | |
7490 | case CONST: | |
7491 | output_asm_insn ("adr%?\t%0, %1", operands); | |
7492 | output_asm_insn ("ldm%?ia\t%0, %M0", operands); | |
7493 | break; | |
7494 | ||
ff9940b0 | 7495 | default: |
aec3cfba NC |
7496 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), |
7497 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
cce8749e | 7498 | { |
2b835d68 RE |
7499 | otherops[0] = operands[0]; |
7500 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
7501 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
1d6e90ac | 7502 | |
2b835d68 RE |
7503 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) |
7504 | { | |
7505 | if (GET_CODE (otherops[2]) == CONST_INT) | |
7506 | { | |
06bea5aa | 7507 | switch ((int) INTVAL (otherops[2])) |
2b835d68 RE |
7508 | { |
7509 | case -8: | |
7510 | output_asm_insn ("ldm%?db\t%1, %M0", otherops); | |
7511 | return ""; | |
7512 | case -4: | |
7513 | output_asm_insn ("ldm%?da\t%1, %M0", otherops); | |
7514 | return ""; | |
7515 | case 4: | |
7516 | output_asm_insn ("ldm%?ib\t%1, %M0", otherops); | |
7517 | return ""; | |
7518 | } | |
1d6e90ac | 7519 | |
2b835d68 RE |
7520 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) |
7521 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
7522 | else | |
7523 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
7524 | } | |
7525 | else | |
7526 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
7527 | } | |
7528 | else | |
7529 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
6cfc7210 | 7530 | |
2b835d68 RE |
7531 | return "ldm%?ia\t%0, %M0"; |
7532 | } | |
7533 | else | |
7534 | { | |
a4a37b30 | 7535 | otherops[1] = adjust_address (operands[1], SImode, 4); |
2b835d68 RE |
7536 | /* Take care of overlapping base/data reg. */ |
7537 | if (reg_mentioned_p (operands[0], operands[1])) | |
7538 | { | |
7539 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
7540 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
7541 | } | |
7542 | else | |
7543 | { | |
7544 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
7545 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
7546 | } | |
cce8749e CH |
7547 | } |
7548 | } | |
7549 | } | |
2b835d68 | 7550 | else |
6354dc9b | 7551 | abort (); /* Constraints should prevent this. */ |
cce8749e CH |
7552 | } |
7553 | else if (code0 == MEM && code1 == REG) | |
7554 | { | |
62b10bbc NC |
7555 | if (REGNO (operands[1]) == IP_REGNUM) |
7556 | abort (); | |
2b835d68 | 7557 | |
ff9940b0 RE |
7558 | switch (GET_CODE (XEXP (operands[0], 0))) |
7559 | { | |
7560 | case REG: | |
9997d19d | 7561 | output_asm_insn ("stm%?ia\t%m0, %M1", operands); |
ff9940b0 | 7562 | break; |
2b835d68 | 7563 | |
ff9940b0 | 7564 | case PRE_INC: |
6354dc9b | 7565 | abort (); /* Should never happen now. */ |
ff9940b0 | 7566 | break; |
2b835d68 | 7567 | |
ff9940b0 | 7568 | case PRE_DEC: |
2b835d68 | 7569 | output_asm_insn ("stm%?db\t%m0!, %M1", operands); |
ff9940b0 | 7570 | break; |
2b835d68 | 7571 | |
ff9940b0 | 7572 | case POST_INC: |
9997d19d | 7573 | output_asm_insn ("stm%?ia\t%m0!, %M1", operands); |
ff9940b0 | 7574 | break; |
2b835d68 | 7575 | |
ff9940b0 | 7576 | case POST_DEC: |
6354dc9b | 7577 | abort (); /* Should never happen now. */ |
ff9940b0 | 7578 | break; |
2b835d68 RE |
7579 | |
7580 | case PLUS: | |
7581 | if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
7582 | { | |
06bea5aa | 7583 | switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) |
2b835d68 RE |
7584 | { |
7585 | case -8: | |
7586 | output_asm_insn ("stm%?db\t%m0, %M1", operands); | |
7587 | return ""; | |
7588 | ||
7589 | case -4: | |
7590 | output_asm_insn ("stm%?da\t%m0, %M1", operands); | |
7591 | return ""; | |
7592 | ||
7593 | case 4: | |
7594 | output_asm_insn ("stm%?ib\t%m0, %M1", operands); | |
7595 | return ""; | |
7596 | } | |
7597 | } | |
7598 | /* Fall through */ | |
7599 | ||
ff9940b0 | 7600 | default: |
a4a37b30 | 7601 | otherops[0] = adjust_address (operands[0], SImode, 4); |
43cffd11 | 7602 | otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); |
9997d19d RE |
7603 | output_asm_insn ("str%?\t%1, %0", operands); |
7604 | output_asm_insn ("str%?\t%1, %0", otherops); | |
cce8749e CH |
7605 | } |
7606 | } | |
2b835d68 | 7607 | else |
1d6e90ac NC |
7608 | /* Constraints should prevent this. */ |
7609 | abort (); | |
cce8749e | 7610 | |
9997d19d RE |
7611 | return ""; |
7612 | } | |
cce8749e CH |
7613 | |
7614 | ||
7615 | /* Output an arbitrary MOV reg, #n. | |
7616 | OPERANDS[0] is a register. OPERANDS[1] is a const_int. */ | |
cd2b33d0 | 7617 | const char * |
e32bac5b | 7618 | output_mov_immediate (rtx *operands) |
cce8749e | 7619 | { |
f3bb6135 | 7620 | HOST_WIDE_INT n = INTVAL (operands[1]); |
cce8749e | 7621 | |
1d6e90ac | 7622 | /* Try to use one MOV. */ |
cce8749e | 7623 | if (const_ok_for_arm (n)) |
1d6e90ac | 7624 | output_asm_insn ("mov%?\t%0, %1", operands); |
cce8749e | 7625 | |
1d6e90ac NC |
7626 | /* Try to use one MVN. */ |
7627 | else if (const_ok_for_arm (~n)) | |
cce8749e | 7628 | { |
f3bb6135 | 7629 | operands[1] = GEN_INT (~n); |
9997d19d | 7630 | output_asm_insn ("mvn%?\t%0, %1", operands); |
cce8749e | 7631 | } |
1d6e90ac NC |
7632 | else |
7633 | { | |
7634 | int n_ones = 0; | |
7635 | int i; | |
cce8749e | 7636 | |
1d6e90ac | 7637 | /* If all else fails, make it out of ORRs or BICs as appropriate. */ |
5a9335ef | 7638 | for (i = 0; i < 32; i++) |
1d6e90ac | 7639 | if (n & 1 << i) |
5a9335ef | 7640 | n_ones++; |
cce8749e | 7641 | |
1d6e90ac NC |
7642 | if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */ |
7643 | output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n); | |
7644 | else | |
7645 | output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n); | |
7646 | } | |
f3bb6135 RE |
7647 | |
7648 | return ""; | |
7649 | } | |
cce8749e | 7650 | |
1d6e90ac NC |
7651 | /* Output an ADD r, s, #n where n may be too big for one instruction. |
7652 | If adding zero to one register, output nothing. */ | |
cd2b33d0 | 7653 | const char * |
e32bac5b | 7654 | output_add_immediate (rtx *operands) |
cce8749e | 7655 | { |
f3bb6135 | 7656 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
7657 | |
7658 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
7659 | { | |
7660 | if (n < 0) | |
7661 | output_multi_immediate (operands, | |
9997d19d RE |
7662 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
7663 | -n); | |
cce8749e CH |
7664 | else |
7665 | output_multi_immediate (operands, | |
9997d19d RE |
7666 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
7667 | n); | |
cce8749e | 7668 | } |
f3bb6135 RE |
7669 | |
7670 | return ""; | |
7671 | } | |
cce8749e | 7672 | |
cce8749e CH |
7673 | /* Output a multiple immediate operation. |
7674 | OPERANDS is the vector of operands referred to in the output patterns. | |
7675 | INSTR1 is the output pattern to use for the first constant. | |
7676 | INSTR2 is the output pattern to use for subsequent constants. | |
7677 | IMMED_OP is the index of the constant slot in OPERANDS. | |
7678 | N is the constant value. */ | |
cd2b33d0 | 7679 | static const char * |
e32bac5b RE |
7680 | output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, |
7681 | int immed_op, HOST_WIDE_INT n) | |
cce8749e | 7682 | { |
f3bb6135 | 7683 | #if HOST_BITS_PER_WIDE_INT > 32 |
30cf4896 | 7684 | n &= 0xffffffff; |
f3bb6135 RE |
7685 | #endif |
7686 | ||
cce8749e CH |
7687 | if (n == 0) |
7688 | { | |
1d6e90ac | 7689 | /* Quick and easy output. */ |
cce8749e | 7690 | operands[immed_op] = const0_rtx; |
1d6e90ac | 7691 | output_asm_insn (instr1, operands); |
cce8749e CH |
7692 | } |
7693 | else | |
7694 | { | |
7695 | int i; | |
cd2b33d0 | 7696 | const char * instr = instr1; |
cce8749e | 7697 | |
6354dc9b | 7698 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
7699 | for (i = 0; i < 32; i += 2) |
7700 | { | |
7701 | if (n & (3 << i)) | |
7702 | { | |
f3bb6135 RE |
7703 | operands[immed_op] = GEN_INT (n & (255 << i)); |
7704 | output_asm_insn (instr, operands); | |
cce8749e CH |
7705 | instr = instr2; |
7706 | i += 6; | |
7707 | } | |
7708 | } | |
7709 | } | |
cd2b33d0 | 7710 | |
f3bb6135 | 7711 | return ""; |
9997d19d | 7712 | } |
cce8749e | 7713 | |
cce8749e CH |
7714 | /* Return the appropriate ARM instruction for the operation code. |
7715 | The returned result should not be overwritten. OP is the rtx of the | |
7716 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
7717 | was shifted. */ | |
cd2b33d0 | 7718 | const char * |
e32bac5b | 7719 | arithmetic_instr (rtx op, int shift_first_arg) |
cce8749e | 7720 | { |
9997d19d | 7721 | switch (GET_CODE (op)) |
cce8749e CH |
7722 | { |
7723 | case PLUS: | |
f3bb6135 RE |
7724 | return "add"; |
7725 | ||
cce8749e | 7726 | case MINUS: |
f3bb6135 RE |
7727 | return shift_first_arg ? "rsb" : "sub"; |
7728 | ||
cce8749e | 7729 | case IOR: |
f3bb6135 RE |
7730 | return "orr"; |
7731 | ||
cce8749e | 7732 | case XOR: |
f3bb6135 RE |
7733 | return "eor"; |
7734 | ||
cce8749e | 7735 | case AND: |
f3bb6135 RE |
7736 | return "and"; |
7737 | ||
cce8749e | 7738 | default: |
f3bb6135 | 7739 | abort (); |
cce8749e | 7740 | } |
f3bb6135 | 7741 | } |
cce8749e | 7742 | |
cce8749e CH |
7743 | /* Ensure valid constant shifts and return the appropriate shift mnemonic |
7744 | for the operation code. The returned result should not be overwritten. | |
7745 | OP is the rtx code of the shift. | |
9997d19d | 7746 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 7747 | shift. */ |
cd2b33d0 | 7748 | static const char * |
e32bac5b | 7749 | shift_op (rtx op, HOST_WIDE_INT *amountp) |
cce8749e | 7750 | { |
cd2b33d0 | 7751 | const char * mnem; |
e2c671ba | 7752 | enum rtx_code code = GET_CODE (op); |
cce8749e | 7753 | |
9997d19d RE |
7754 | if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG) |
7755 | *amountp = -1; | |
7756 | else if (GET_CODE (XEXP (op, 1)) == CONST_INT) | |
7757 | *amountp = INTVAL (XEXP (op, 1)); | |
7758 | else | |
7759 | abort (); | |
7760 | ||
e2c671ba | 7761 | switch (code) |
cce8749e CH |
7762 | { |
7763 | case ASHIFT: | |
7764 | mnem = "asl"; | |
7765 | break; | |
f3bb6135 | 7766 | |
cce8749e CH |
7767 | case ASHIFTRT: |
7768 | mnem = "asr"; | |
cce8749e | 7769 | break; |
f3bb6135 | 7770 | |
cce8749e CH |
7771 | case LSHIFTRT: |
7772 | mnem = "lsr"; | |
cce8749e | 7773 | break; |
f3bb6135 | 7774 | |
9997d19d RE |
7775 | case ROTATERT: |
7776 | mnem = "ror"; | |
9997d19d RE |
7777 | break; |
7778 | ||
ff9940b0 | 7779 | case MULT: |
e2c671ba RE |
7780 | /* We never have to worry about the amount being other than a |
7781 | power of 2, since this case can never be reloaded from a reg. */ | |
9997d19d RE |
7782 | if (*amountp != -1) |
7783 | *amountp = int_log2 (*amountp); | |
7784 | else | |
7785 | abort (); | |
f3bb6135 RE |
7786 | return "asl"; |
7787 | ||
cce8749e | 7788 | default: |
f3bb6135 | 7789 | abort (); |
cce8749e CH |
7790 | } |
7791 | ||
e2c671ba RE |
7792 | if (*amountp != -1) |
7793 | { | |
7794 | /* This is not 100% correct, but follows from the desire to merge | |
7795 | multiplication by a power of 2 with the recognizer for a | |
7796 | shift. >=32 is not a valid shift for "asl", so we must try and | |
7797 | output a shift that produces the correct arithmetical result. | |
ddd5a7c1 | 7798 | Using lsr #32 is identical except for the fact that the carry bit |
e2c671ba RE |
7799 | is not set correctly if we set the flags; but we never use the |
7800 | carry bit from such an operation, so we can ignore that. */ | |
7801 | if (code == ROTATERT) | |
1d6e90ac NC |
7802 | /* Rotate is just modulo 32. */ |
7803 | *amountp &= 31; | |
e2c671ba RE |
7804 | else if (*amountp != (*amountp & 31)) |
7805 | { | |
7806 | if (code == ASHIFT) | |
7807 | mnem = "lsr"; | |
7808 | *amountp = 32; | |
7809 | } | |
7810 | ||
7811 | /* Shifts of 0 are no-ops. */ | |
7812 | if (*amountp == 0) | |
7813 | return NULL; | |
7814 | } | |
7815 | ||
9997d19d RE |
7816 | return mnem; |
7817 | } | |
cce8749e | 7818 | |
6354dc9b | 7819 | /* Obtain the shift from the POWER of two. */ |
1d6e90ac | 7820 | |
18af7313 | 7821 | static HOST_WIDE_INT |
e32bac5b | 7822 | int_log2 (HOST_WIDE_INT power) |
cce8749e | 7823 | { |
f3bb6135 | 7824 | HOST_WIDE_INT shift = 0; |
cce8749e | 7825 | |
30cf4896 | 7826 | while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) |
cce8749e CH |
7827 | { |
7828 | if (shift > 31) | |
f3bb6135 | 7829 | abort (); |
e32bac5b | 7830 | shift++; |
cce8749e | 7831 | } |
f3bb6135 RE |
7832 | |
7833 | return shift; | |
7834 | } | |
cce8749e | 7835 | |
cce8749e CH |
7836 | /* Output a .ascii pseudo-op, keeping track of lengths. This is because |
7837 | /bin/as is horribly restrictive. */ | |
6cfc7210 | 7838 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
7839 | |
7840 | void | |
e32bac5b | 7841 | output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) |
cce8749e CH |
7842 | { |
7843 | int i; | |
6cfc7210 | 7844 | int len_so_far = 0; |
cce8749e | 7845 | |
6cfc7210 NC |
7846 | fputs ("\t.ascii\t\"", stream); |
7847 | ||
cce8749e CH |
7848 | for (i = 0; i < len; i++) |
7849 | { | |
1d6e90ac | 7850 | int c = p[i]; |
cce8749e | 7851 | |
6cfc7210 | 7852 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 7853 | { |
6cfc7210 | 7854 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 7855 | len_so_far = 0; |
cce8749e CH |
7856 | } |
7857 | ||
6cfc7210 | 7858 | switch (c) |
cce8749e | 7859 | { |
6cfc7210 NC |
7860 | case TARGET_TAB: |
7861 | fputs ("\\t", stream); | |
7862 | len_so_far += 2; | |
7863 | break; | |
7864 | ||
7865 | case TARGET_FF: | |
7866 | fputs ("\\f", stream); | |
7867 | len_so_far += 2; | |
7868 | break; | |
7869 | ||
7870 | case TARGET_BS: | |
7871 | fputs ("\\b", stream); | |
7872 | len_so_far += 2; | |
7873 | break; | |
7874 | ||
7875 | case TARGET_CR: | |
7876 | fputs ("\\r", stream); | |
7877 | len_so_far += 2; | |
7878 | break; | |
7879 | ||
7880 | case TARGET_NEWLINE: | |
7881 | fputs ("\\n", stream); | |
7882 | c = p [i + 1]; | |
7883 | if ((c >= ' ' && c <= '~') | |
7884 | || c == TARGET_TAB) | |
7885 | /* This is a good place for a line break. */ | |
7886 | len_so_far = MAX_ASCII_LEN; | |
7887 | else | |
7888 | len_so_far += 2; | |
7889 | break; | |
7890 | ||
7891 | case '\"': | |
7892 | case '\\': | |
7893 | putc ('\\', stream); | |
5895f793 | 7894 | len_so_far++; |
6cfc7210 | 7895 | /* drop through. */ |
f3bb6135 | 7896 | |
6cfc7210 NC |
7897 | default: |
7898 | if (c >= ' ' && c <= '~') | |
7899 | { | |
7900 | putc (c, stream); | |
5895f793 | 7901 | len_so_far++; |
6cfc7210 NC |
7902 | } |
7903 | else | |
7904 | { | |
7905 | fprintf (stream, "\\%03o", c); | |
7906 | len_so_far += 4; | |
7907 | } | |
7908 | break; | |
cce8749e | 7909 | } |
cce8749e | 7910 | } |
f3bb6135 | 7911 | |
cce8749e | 7912 | fputs ("\"\n", stream); |
f3bb6135 | 7913 | } |
cce8749e | 7914 | \f |
121308d4 NC |
7915 | /* Compute the register sabe mask for registers 0 through 12 |
7916 | inclusive. This code is used by both arm_compute_save_reg_mask | |
7917 | and arm_compute_initial_elimination_offset. */ | |
6d3d9133 | 7918 | static unsigned long |
e32bac5b | 7919 | arm_compute_save_reg0_reg12_mask (void) |
6d3d9133 | 7920 | { |
121308d4 | 7921 | unsigned long func_type = arm_current_func_type (); |
6d3d9133 NC |
7922 | unsigned int save_reg_mask = 0; |
7923 | unsigned int reg; | |
6d3d9133 | 7924 | |
7b8b8ade | 7925 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 7926 | { |
7b8b8ade | 7927 | unsigned int max_reg; |
7b8b8ade NC |
7928 | /* Interrupt functions must not corrupt any registers, |
7929 | even call clobbered ones. If this is a leaf function | |
7930 | we can just examine the registers used by the RTL, but | |
7931 | otherwise we have to assume that whatever function is | |
7932 | called might clobber anything, and so we have to save | |
7933 | all the call-clobbered registers as well. */ | |
7934 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
7935 | /* FIQ handlers have registers r8 - r12 banked, so | |
7936 | we only need to check r0 - r7, Normal ISRs only | |
121308d4 | 7937 | bank r14 and r15, so we must check up to r12. |
7b8b8ade NC |
7938 | r13 is the stack pointer which is always preserved, |
7939 | so we do not need to consider it here. */ | |
7940 | max_reg = 7; | |
7941 | else | |
7942 | max_reg = 12; | |
7943 | ||
7944 | for (reg = 0; reg <= max_reg; reg++) | |
7945 | if (regs_ever_live[reg] | |
7946 | || (! current_function_is_leaf && call_used_regs [reg])) | |
6d3d9133 NC |
7947 | save_reg_mask |= (1 << reg); |
7948 | } | |
7949 | else | |
7950 | { | |
7951 | /* In the normal case we only need to save those registers | |
7952 | which are call saved and which are used by this function. */ | |
7953 | for (reg = 0; reg <= 10; reg++) | |
7954 | if (regs_ever_live[reg] && ! call_used_regs [reg]) | |
7955 | save_reg_mask |= (1 << reg); | |
7956 | ||
7957 | /* Handle the frame pointer as a special case. */ | |
7958 | if (! TARGET_APCS_FRAME | |
7959 | && ! frame_pointer_needed | |
7960 | && regs_ever_live[HARD_FRAME_POINTER_REGNUM] | |
7961 | && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) | |
7962 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; | |
7963 | ||
7964 | /* If we aren't loading the PIC register, | |
7965 | don't stack it even though it may be live. */ | |
7966 | if (flag_pic | |
7967 | && ! TARGET_SINGLE_PIC_BASE | |
7968 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) | |
7969 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; | |
7970 | } | |
7971 | ||
121308d4 NC |
7972 | return save_reg_mask; |
7973 | } | |
7974 | ||
7975 | /* Compute a bit mask of which registers need to be | |
7976 | saved on the stack for the current function. */ | |
7977 | ||
7978 | static unsigned long | |
e32bac5b | 7979 | arm_compute_save_reg_mask (void) |
121308d4 NC |
7980 | { |
7981 | unsigned int save_reg_mask = 0; | |
7982 | unsigned long func_type = arm_current_func_type (); | |
7983 | ||
7984 | if (IS_NAKED (func_type)) | |
7985 | /* This should never really happen. */ | |
7986 | return 0; | |
7987 | ||
7988 | /* If we are creating a stack frame, then we must save the frame pointer, | |
7989 | IP (which will hold the old stack pointer), LR and the PC. */ | |
7990 | if (frame_pointer_needed) | |
7991 | save_reg_mask |= | |
7992 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
7993 | | (1 << IP_REGNUM) | |
7994 | | (1 << LR_REGNUM) | |
7995 | | (1 << PC_REGNUM); | |
7996 | ||
7997 | /* Volatile functions do not return, so there | |
7998 | is no need to save any other registers. */ | |
7999 | if (IS_VOLATILE (func_type)) | |
8000 | return save_reg_mask; | |
8001 | ||
8002 | save_reg_mask |= arm_compute_save_reg0_reg12_mask (); | |
8003 | ||
6d3d9133 NC |
8004 | /* Decide if we need to save the link register. |
8005 | Interrupt routines have their own banked link register, | |
8006 | so they never need to save it. | |
1768c26f | 8007 | Otherwise if we do not use the link register we do not need to save |
6d3d9133 NC |
8008 | it. If we are pushing other registers onto the stack however, we |
8009 | can save an instruction in the epilogue by pushing the link register | |
8010 | now and then popping it back into the PC. This incurs extra memory | |
72ac76be | 8011 | accesses though, so we only do it when optimizing for size, and only |
6d3d9133 | 8012 | if we know that we will not need a fancy return sequence. */ |
3a7731fd | 8013 | if (regs_ever_live [LR_REGNUM] |
6d3d9133 NC |
8014 | || (save_reg_mask |
8015 | && optimize_size | |
3a7731fd | 8016 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)) |
6d3d9133 NC |
8017 | save_reg_mask |= 1 << LR_REGNUM; |
8018 | ||
6f7ebcbb NC |
8019 | if (cfun->machine->lr_save_eliminated) |
8020 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
8021 | ||
5a9335ef NC |
8022 | if (TARGET_REALLY_IWMMXT |
8023 | && ((bit_count (save_reg_mask) | |
8024 | + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0) | |
8025 | { | |
8026 | unsigned int reg; | |
8027 | ||
8028 | /* The total number of registers that are going to be pushed | |
8029 | onto the stack is odd. We need to ensure that the stack | |
8030 | is 64-bit aligned before we start to save iWMMXt registers, | |
8031 | and also before we start to create locals. (A local variable | |
8032 | might be a double or long long which we will load/store using | |
8033 | an iWMMXt instruction). Therefore we need to push another | |
8034 | ARM register, so that the stack will be 64-bit aligned. We | |
8035 | try to avoid using the arg registers (r0 -r3) as they might be | |
8036 | used to pass values in a tail call. */ | |
8037 | for (reg = 4; reg <= 12; reg++) | |
8038 | if ((save_reg_mask & (1 << reg)) == 0) | |
8039 | break; | |
8040 | ||
8041 | if (reg <= 12) | |
8042 | save_reg_mask |= (1 << reg); | |
8043 | else | |
8044 | { | |
8045 | cfun->machine->sibcall_blocked = 1; | |
8046 | save_reg_mask |= (1 << 3); | |
8047 | } | |
8048 | } | |
8049 | ||
6d3d9133 NC |
8050 | return save_reg_mask; |
8051 | } | |
8052 | ||
8053 | /* Generate a function exit sequence. If REALLY_RETURN is true, then do | |
8054 | everything bar the final return instruction. */ | |
cd2b33d0 | 8055 | const char * |
e32bac5b | 8056 | output_return_instruction (rtx operand, int really_return, int reverse) |
ff9940b0 | 8057 | { |
6d3d9133 | 8058 | char conditional[10]; |
ff9940b0 | 8059 | char instr[100]; |
6d3d9133 NC |
8060 | int reg; |
8061 | unsigned long live_regs_mask; | |
8062 | unsigned long func_type; | |
e26053d1 | 8063 | |
6d3d9133 | 8064 | func_type = arm_current_func_type (); |
e2c671ba | 8065 | |
6d3d9133 | 8066 | if (IS_NAKED (func_type)) |
d5b7b3ae | 8067 | return ""; |
6d3d9133 NC |
8068 | |
8069 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 8070 | { |
e2c671ba | 8071 | /* If this function was declared non-returning, and we have found a tail |
3a5a4282 PB |
8072 | call, then we have to trust that the called function won't return. */ |
8073 | if (really_return) | |
8074 | { | |
8075 | rtx ops[2]; | |
8076 | ||
8077 | /* Otherwise, trap an attempted return by aborting. */ | |
8078 | ops[0] = operand; | |
8079 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" | |
8080 | : "abort"); | |
8081 | assemble_external_libcall (ops[1]); | |
8082 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
8083 | } | |
8084 | ||
e2c671ba RE |
8085 | return ""; |
8086 | } | |
6d3d9133 | 8087 | |
5895f793 | 8088 | if (current_function_calls_alloca && !really_return) |
62b10bbc | 8089 | abort (); |
ff9940b0 | 8090 | |
c414f8a9 | 8091 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); |
d5b7b3ae | 8092 | |
6d3d9133 | 8093 | return_used_this_function = 1; |
ff9940b0 | 8094 | |
6d3d9133 | 8095 | live_regs_mask = arm_compute_save_reg_mask (); |
ff9940b0 | 8096 | |
1768c26f | 8097 | if (live_regs_mask) |
6d3d9133 | 8098 | { |
1768c26f PB |
8099 | const char * return_reg; |
8100 | ||
8101 | /* If we do not have any special requirements for function exit | |
8102 | (eg interworking, or ISR) then we can load the return address | |
8103 | directly into the PC. Otherwise we must load it into LR. */ | |
8104 | if (really_return | |
1768c26f PB |
8105 | && ! TARGET_INTERWORK) |
8106 | return_reg = reg_names[PC_REGNUM]; | |
6d3d9133 | 8107 | else |
1768c26f PB |
8108 | return_reg = reg_names[LR_REGNUM]; |
8109 | ||
6d3d9133 NC |
8110 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) |
8111 | /* There are two possible reasons for the IP register being saved. | |
8112 | Either a stack frame was created, in which case IP contains the | |
8113 | old stack pointer, or an ISR routine corrupted it. If this in an | |
8114 | ISR routine then just restore IP, otherwise restore IP into SP. */ | |
8115 | if (! IS_INTERRUPT (func_type)) | |
8116 | { | |
8117 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
8118 | live_regs_mask |= (1 << SP_REGNUM); | |
8119 | } | |
f3bb6135 | 8120 | |
3a7731fd PB |
8121 | /* On some ARM architectures it is faster to use LDR rather than |
8122 | LDM to load a single register. On other architectures, the | |
8123 | cost is the same. In 26 bit mode, or for exception handlers, | |
8124 | we have to use LDM to load the PC so that the CPSR is also | |
8125 | restored. */ | |
8126 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) | |
6d3d9133 | 8127 | { |
3a7731fd PB |
8128 | if (live_regs_mask == (unsigned int)(1 << reg)) |
8129 | break; | |
8130 | } | |
8131 | if (reg <= LAST_ARM_REGNUM | |
8132 | && (reg != LR_REGNUM | |
8133 | || ! really_return | |
8134 | || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type)))) | |
8135 | { | |
8136 | sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, | |
8137 | (reg == LR_REGNUM) ? return_reg : reg_names[reg]); | |
6d3d9133 | 8138 | } |
ff9940b0 | 8139 | else |
1d5473cb | 8140 | { |
1768c26f PB |
8141 | char *p; |
8142 | int first = 1; | |
6d3d9133 | 8143 | |
1768c26f PB |
8144 | /* Generate the load multiple instruction to restore the registers. */ |
8145 | if (frame_pointer_needed) | |
8146 | sprintf (instr, "ldm%sea\t%%|fp, {", conditional); | |
f1acdf8b NC |
8147 | else if (live_regs_mask & (1 << SP_REGNUM)) |
8148 | sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); | |
da6558fd | 8149 | else |
1768c26f PB |
8150 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); |
8151 | ||
8152 | p = instr + strlen (instr); | |
6d3d9133 | 8153 | |
1768c26f PB |
8154 | for (reg = 0; reg <= SP_REGNUM; reg++) |
8155 | if (live_regs_mask & (1 << reg)) | |
8156 | { | |
8157 | int l = strlen (reg_names[reg]); | |
8158 | ||
8159 | if (first) | |
8160 | first = 0; | |
8161 | else | |
8162 | { | |
8163 | memcpy (p, ", ", 2); | |
8164 | p += 2; | |
8165 | } | |
8166 | ||
8167 | memcpy (p, "%|", 2); | |
8168 | memcpy (p + 2, reg_names[reg], l); | |
8169 | p += l + 2; | |
8170 | } | |
8171 | ||
8172 | if (live_regs_mask & (1 << LR_REGNUM)) | |
8173 | { | |
b17fe233 NC |
8174 | sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); |
8175 | /* Decide if we need to add the ^ symbol to the end of the | |
8176 | register list. This causes the saved condition codes | |
8177 | register to be copied into the current condition codes | |
8178 | register. We do the copy if we are conforming to the 32-bit | |
8179 | ABI and this is an interrupt function, or if we are | |
8180 | conforming to the 26-bit ABI. There is a special case for | |
8181 | the 26-bit ABI however, which is if we are writing back the | |
8182 | stack pointer but not loading the PC. In this case adding | |
8183 | the ^ symbol would create a type 2 LDM instruction, where | |
8184 | writeback is UNPREDICTABLE. We are safe in leaving the ^ | |
8185 | character off in this case however, since the actual return | |
8186 | instruction will be a MOVS which will restore the CPSR. */ | |
8187 | if ((TARGET_APCS_32 && IS_INTERRUPT (func_type)) | |
13eedc5a | 8188 | || (! TARGET_APCS_32 && really_return)) |
b17fe233 | 8189 | strcat (p, "^"); |
1768c26f PB |
8190 | } |
8191 | else | |
8192 | strcpy (p, "}"); | |
1d5473cb | 8193 | } |
da6558fd | 8194 | |
1768c26f PB |
8195 | output_asm_insn (instr, & operand); |
8196 | ||
3a7731fd PB |
8197 | /* See if we need to generate an extra instruction to |
8198 | perform the actual function return. */ | |
8199 | if (really_return | |
8200 | && func_type != ARM_FT_INTERWORKED | |
8201 | && (live_regs_mask & (1 << LR_REGNUM)) != 0) | |
da6558fd | 8202 | { |
3a7731fd PB |
8203 | /* The return has already been handled |
8204 | by loading the LR into the PC. */ | |
8205 | really_return = 0; | |
da6558fd | 8206 | } |
ff9940b0 | 8207 | } |
e26053d1 | 8208 | |
1768c26f | 8209 | if (really_return) |
ff9940b0 | 8210 | { |
6d3d9133 NC |
8211 | switch ((int) ARM_FUNC_TYPE (func_type)) |
8212 | { | |
8213 | case ARM_FT_ISR: | |
8214 | case ARM_FT_FIQ: | |
8215 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); | |
8216 | break; | |
8217 | ||
8218 | case ARM_FT_INTERWORKED: | |
8219 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
8220 | break; | |
8221 | ||
8222 | case ARM_FT_EXCEPTION: | |
8223 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); | |
8224 | break; | |
8225 | ||
8226 | default: | |
1768c26f PB |
8227 | /* ARMv5 implementations always provide BX, so interworking |
8228 | is the default unless APCS-26 is in use. */ | |
8229 | if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32) | |
8230 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
8231 | else | |
8232 | sprintf (instr, "mov%s%s\t%%|pc, %%|lr", | |
8233 | conditional, TARGET_APCS_32 ? "" : "s"); | |
6d3d9133 NC |
8234 | break; |
8235 | } | |
1768c26f PB |
8236 | |
8237 | output_asm_insn (instr, & operand); | |
ff9940b0 | 8238 | } |
f3bb6135 | 8239 | |
ff9940b0 RE |
8240 | return ""; |
8241 | } | |
8242 | ||
ef179a26 NC |
8243 | /* Write the function name into the code section, directly preceding |
8244 | the function prologue. | |
8245 | ||
8246 | Code will be output similar to this: | |
8247 | t0 | |
8248 | .ascii "arm_poke_function_name", 0 | |
8249 | .align | |
8250 | t1 | |
8251 | .word 0xff000000 + (t1 - t0) | |
8252 | arm_poke_function_name | |
8253 | mov ip, sp | |
8254 | stmfd sp!, {fp, ip, lr, pc} | |
8255 | sub fp, ip, #4 | |
8256 | ||
8257 | When performing a stack backtrace, code can inspect the value | |
8258 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
8259 | at location pc - 12 and the top 8 bits are set, then we know | |
8260 | that there is a function name embedded immediately preceding this | |
8261 | location and has length ((pc[-3]) & 0xff000000). | |
8262 | ||
8263 | We assume that pc is declared as a pointer to an unsigned long. | |
8264 | ||
8265 | It is of no benefit to output the function name if we are assembling | |
8266 | a leaf function. These function types will not contain a stack | |
8267 | backtrace structure, therefore it is not possible to determine the | |
8268 | function name. */ | |
ef179a26 | 8269 | void |
e32bac5b | 8270 | arm_poke_function_name (FILE *stream, const char *name) |
ef179a26 NC |
8271 | { |
8272 | unsigned long alignlength; | |
8273 | unsigned long length; | |
8274 | rtx x; | |
8275 | ||
d5b7b3ae | 8276 | length = strlen (name) + 1; |
0c2ca901 | 8277 | alignlength = ROUND_UP_WORD (length); |
ef179a26 | 8278 | |
949d79eb | 8279 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 8280 | ASM_OUTPUT_ALIGN (stream, 2); |
30cf4896 | 8281 | x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); |
301d03af | 8282 | assemble_aligned_integer (UNITS_PER_WORD, x); |
ef179a26 NC |
8283 | } |
8284 | ||
6d3d9133 NC |
8285 | /* Place some comments into the assembler stream |
8286 | describing the current function. */ | |
08c148a8 | 8287 | static void |
e32bac5b | 8288 | arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) |
cce8749e | 8289 | { |
6d3d9133 | 8290 | unsigned long func_type; |
08c148a8 NB |
8291 | |
8292 | if (!TARGET_ARM) | |
8293 | { | |
8294 | thumb_output_function_prologue (f, frame_size); | |
8295 | return; | |
8296 | } | |
6d3d9133 NC |
8297 | |
8298 | /* Sanity check. */ | |
abaa26e5 | 8299 | if (arm_ccfsm_state || arm_target_insn) |
6d3d9133 | 8300 | abort (); |
31fdb4d5 | 8301 | |
6d3d9133 NC |
8302 | func_type = arm_current_func_type (); |
8303 | ||
8304 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
8305 | { | |
8306 | default: | |
8307 | case ARM_FT_NORMAL: | |
8308 | break; | |
8309 | case ARM_FT_INTERWORKED: | |
8310 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
8311 | break; | |
8312 | case ARM_FT_EXCEPTION_HANDLER: | |
8313 | asm_fprintf (f, "\t%@ C++ Exception Handler.\n"); | |
8314 | break; | |
8315 | case ARM_FT_ISR: | |
8316 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
8317 | break; | |
8318 | case ARM_FT_FIQ: | |
8319 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
8320 | break; | |
8321 | case ARM_FT_EXCEPTION: | |
8322 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
8323 | break; | |
8324 | } | |
ff9940b0 | 8325 | |
6d3d9133 NC |
8326 | if (IS_NAKED (func_type)) |
8327 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
8328 | ||
8329 | if (IS_VOLATILE (func_type)) | |
8330 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
8331 | ||
8332 | if (IS_NESTED (func_type)) | |
8333 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
8334 | ||
c53dddc2 | 8335 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", |
dd18ae56 NC |
8336 | current_function_args_size, |
8337 | current_function_pretend_args_size, frame_size); | |
6d3d9133 | 8338 | |
3cb66fd7 | 8339 | asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", |
dd18ae56 | 8340 | frame_pointer_needed, |
3cb66fd7 | 8341 | cfun->machine->uses_anonymous_args); |
cce8749e | 8342 | |
6f7ebcbb NC |
8343 | if (cfun->machine->lr_save_eliminated) |
8344 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
8345 | ||
32de079a RE |
8346 | #ifdef AOF_ASSEMBLER |
8347 | if (flag_pic) | |
dd18ae56 | 8348 | asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM); |
32de079a | 8349 | #endif |
6d3d9133 NC |
8350 | |
8351 | return_used_this_function = 0; | |
f3bb6135 | 8352 | } |
cce8749e | 8353 | |
cd2b33d0 | 8354 | const char * |
e32bac5b | 8355 | arm_output_epilogue (int really_return) |
cce8749e | 8356 | { |
949d79eb | 8357 | int reg; |
6f7ebcbb | 8358 | unsigned long saved_regs_mask; |
6d3d9133 | 8359 | unsigned long func_type; |
c882c7ac RE |
8360 | /* Floats_offset is the offset from the "virtual" frame. In an APCS |
8361 | frame that is $fp + 4 for a non-variadic function. */ | |
8362 | int floats_offset = 0; | |
cce8749e | 8363 | rtx operands[3]; |
0977774b | 8364 | int frame_size = arm_get_frame_size (); |
d5b7b3ae | 8365 | FILE * f = asm_out_file; |
6d3d9133 | 8366 | rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; |
5a9335ef | 8367 | unsigned int lrm_count = 0; |
cce8749e | 8368 | |
6d3d9133 NC |
8369 | /* If we have already generated the return instruction |
8370 | then it is futile to generate anything else. */ | |
b36ba79f | 8371 | if (use_return_insn (FALSE) && return_used_this_function) |
949d79eb | 8372 | return ""; |
cce8749e | 8373 | |
6d3d9133 | 8374 | func_type = arm_current_func_type (); |
d5b7b3ae | 8375 | |
6d3d9133 NC |
8376 | if (IS_NAKED (func_type)) |
8377 | /* Naked functions don't have epilogues. */ | |
8378 | return ""; | |
0616531f | 8379 | |
6d3d9133 | 8380 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 8381 | { |
86efdc8e | 8382 | rtx op; |
6d3d9133 NC |
8383 | |
8384 | /* A volatile function should never return. Call abort. */ | |
ed0e6530 | 8385 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 8386 | assemble_external_libcall (op); |
e2c671ba | 8387 | output_asm_insn ("bl\t%a0", &op); |
6d3d9133 | 8388 | |
949d79eb | 8389 | return ""; |
e2c671ba RE |
8390 | } |
8391 | ||
6d3d9133 NC |
8392 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER |
8393 | && ! really_return) | |
8394 | /* If we are throwing an exception, then we really must | |
8395 | be doing a return, so we can't tail-call. */ | |
8396 | abort (); | |
8397 | ||
6f7ebcbb | 8398 | saved_regs_mask = arm_compute_save_reg_mask (); |
5a9335ef NC |
8399 | |
8400 | if (TARGET_IWMMXT) | |
8401 | lrm_count = bit_count (saved_regs_mask); | |
8402 | ||
c882c7ac RE |
8403 | /* XXX We should adjust floats_offset for any anonymous args, and then |
8404 | re-adjust vfp_offset below to compensate. */ | |
8405 | ||
6d3d9133 | 8406 | /* Compute how far away the floats will be. */ |
5a9335ef | 8407 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) |
6f7ebcbb | 8408 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 8409 | floats_offset += 4; |
6d3d9133 | 8410 | |
ff9940b0 | 8411 | if (frame_pointer_needed) |
cce8749e | 8412 | { |
c882c7ac RE |
8413 | int vfp_offset = 4; |
8414 | ||
29ad9694 | 8415 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 8416 | { |
d5b7b3ae | 8417 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
5895f793 | 8418 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
8419 | { |
8420 | floats_offset += 12; | |
dd18ae56 | 8421 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
c882c7ac | 8422 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
8423 | } |
8424 | } | |
8425 | else | |
8426 | { | |
d5b7b3ae | 8427 | int start_reg = LAST_ARM_FP_REGNUM; |
b111229a | 8428 | |
d5b7b3ae | 8429 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
b111229a | 8430 | { |
5895f793 | 8431 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
8432 | { |
8433 | floats_offset += 12; | |
6cfc7210 | 8434 | |
6354dc9b | 8435 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
8436 | if (start_reg - reg == 3) |
8437 | { | |
dd18ae56 | 8438 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
c882c7ac | 8439 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
8440 | start_reg = reg - 1; |
8441 | } | |
8442 | } | |
8443 | else | |
8444 | { | |
8445 | if (reg != start_reg) | |
dd18ae56 NC |
8446 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
8447 | reg + 1, start_reg - reg, | |
c882c7ac | 8448 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
8449 | start_reg = reg - 1; |
8450 | } | |
8451 | } | |
8452 | ||
8453 | /* Just in case the last register checked also needs unstacking. */ | |
8454 | if (reg != start_reg) | |
dd18ae56 NC |
8455 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
8456 | reg + 1, start_reg - reg, | |
c882c7ac | 8457 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a | 8458 | } |
6d3d9133 | 8459 | |
5a9335ef NC |
8460 | if (TARGET_IWMMXT) |
8461 | { | |
8462 | /* The frame pointer is guaranteed to be non-double-word aligned. | |
8463 | This is because it is set to (old_stack_pointer - 4) and the | |
8464 | old_stack_pointer was double word aligned. Thus the offset to | |
8465 | the iWMMXt registers to be loaded must also be non-double-word | |
8466 | sized, so that the resultant address *is* double-word aligned. | |
8467 | We can ignore floats_offset since that was already included in | |
8468 | the live_regs_mask. */ | |
8469 | lrm_count += (lrm_count % 2 ? 2 : 1); | |
8470 | ||
8471 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
8472 | if (regs_ever_live[reg] && !call_used_regs[reg]) | |
8473 | { | |
8474 | asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", | |
8475 | reg, FP_REGNUM, lrm_count * 4); | |
8476 | lrm_count += 2; | |
8477 | } | |
8478 | } | |
8479 | ||
6f7ebcbb | 8480 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
8481 | frame generation actually contains the old stack pointer. So a |
8482 | quick way to unwind the stack is just pop the IP register directly | |
8483 | into the stack pointer. */ | |
6f7ebcbb | 8484 | if ((saved_regs_mask & (1 << IP_REGNUM)) == 0) |
6d3d9133 | 8485 | abort (); |
6f7ebcbb NC |
8486 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
8487 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 8488 | |
6f7ebcbb | 8489 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
8490 | only need to restore the LR register (the return address), but to |
8491 | save time we can load it directly into the PC, unless we need a | |
8492 | special function exit sequence, or we are not really returning. */ | |
8493 | if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) | |
8494 | /* Delete the LR from the register mask, so that the LR on | |
8495 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 8496 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 8497 | else |
6f7ebcbb | 8498 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
6d3d9133 | 8499 | |
6f7ebcbb | 8500 | print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask); |
7b8b8ade NC |
8501 | |
8502 | if (IS_INTERRUPT (func_type)) | |
8503 | /* Interrupt handlers will have pushed the | |
8504 | IP onto the stack, so restore it now. */ | |
f55d7103 | 8505 | print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM); |
cce8749e CH |
8506 | } |
8507 | else | |
8508 | { | |
d2288d8d | 8509 | /* Restore stack pointer if necessary. */ |
56636818 | 8510 | if (frame_size + current_function_outgoing_args_size != 0) |
d2288d8d TG |
8511 | { |
8512 | operands[0] = operands[1] = stack_pointer_rtx; | |
56636818 JL |
8513 | operands[2] = GEN_INT (frame_size |
8514 | + current_function_outgoing_args_size); | |
d2288d8d TG |
8515 | output_add_immediate (operands); |
8516 | } | |
8517 | ||
29ad9694 | 8518 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 8519 | { |
d5b7b3ae | 8520 | for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) |
5895f793 | 8521 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
dd18ae56 NC |
8522 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
8523 | reg, SP_REGNUM); | |
b111229a RE |
8524 | } |
8525 | else | |
8526 | { | |
d5b7b3ae | 8527 | int start_reg = FIRST_ARM_FP_REGNUM; |
b111229a | 8528 | |
d5b7b3ae | 8529 | for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) |
b111229a | 8530 | { |
5895f793 | 8531 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
8532 | { |
8533 | if (reg - start_reg == 3) | |
8534 | { | |
dd18ae56 NC |
8535 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
8536 | start_reg, SP_REGNUM); | |
b111229a RE |
8537 | start_reg = reg + 1; |
8538 | } | |
8539 | } | |
8540 | else | |
8541 | { | |
8542 | if (reg != start_reg) | |
dd18ae56 NC |
8543 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
8544 | start_reg, reg - start_reg, | |
8545 | SP_REGNUM); | |
6cfc7210 | 8546 | |
b111229a RE |
8547 | start_reg = reg + 1; |
8548 | } | |
8549 | } | |
8550 | ||
8551 | /* Just in case the last register checked also needs unstacking. */ | |
8552 | if (reg != start_reg) | |
dd18ae56 NC |
8553 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
8554 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
8555 | } |
8556 | ||
5a9335ef NC |
8557 | if (TARGET_IWMMXT) |
8558 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
8559 | if (regs_ever_live[reg] && !call_used_regs[reg]) | |
8560 | asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM); | |
8561 | ||
6d3d9133 NC |
8562 | /* If we can, restore the LR into the PC. */ |
8563 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
8564 | && really_return | |
8565 | && current_function_pretend_args_size == 0 | |
6f7ebcbb | 8566 | && saved_regs_mask & (1 << LR_REGNUM)) |
cce8749e | 8567 | { |
6f7ebcbb NC |
8568 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
8569 | saved_regs_mask |= (1 << PC_REGNUM); | |
6d3d9133 | 8570 | } |
d5b7b3ae | 8571 | |
6d3d9133 NC |
8572 | /* Load the registers off the stack. If we only have one register |
8573 | to load use the LDR instruction - it is faster. */ | |
6f7ebcbb | 8574 | if (saved_regs_mask == (1 << LR_REGNUM)) |
6d3d9133 | 8575 | { |
f4864588 | 8576 | /* The exception handler ignores the LR, so we do |
6d3d9133 NC |
8577 | not really need to load it off the stack. */ |
8578 | if (eh_ofs) | |
8579 | asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM); | |
32de079a | 8580 | else |
6d3d9133 | 8581 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 8582 | } |
6f7ebcbb | 8583 | else if (saved_regs_mask) |
f1acdf8b NC |
8584 | { |
8585 | if (saved_regs_mask & (1 << SP_REGNUM)) | |
8586 | /* Note - write back to the stack register is not enabled | |
8587 | (ie "ldmfd sp!..."). We know that the stack pointer is | |
8588 | in the list of registers and if we add writeback the | |
8589 | instruction becomes UNPREDICTABLE. */ | |
8590 | print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); | |
8591 | else | |
8592 | print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask); | |
8593 | } | |
6d3d9133 NC |
8594 | |
8595 | if (current_function_pretend_args_size) | |
cce8749e | 8596 | { |
6d3d9133 NC |
8597 | /* Unwind the pre-pushed regs. */ |
8598 | operands[0] = operands[1] = stack_pointer_rtx; | |
8599 | operands[2] = GEN_INT (current_function_pretend_args_size); | |
8600 | output_add_immediate (operands); | |
8601 | } | |
8602 | } | |
32de079a | 8603 | |
9b598fa0 | 8604 | #if 0 |
6d3d9133 NC |
8605 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER) |
8606 | /* Adjust the stack to remove the exception handler stuff. */ | |
8607 | asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, | |
8608 | REGNO (eh_ofs)); | |
9b598fa0 | 8609 | #endif |
b111229a | 8610 | |
f4864588 PB |
8611 | if (! really_return |
8612 | || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
8613 | && current_function_pretend_args_size == 0 | |
8614 | && saved_regs_mask & (1 << PC_REGNUM))) | |
6d3d9133 | 8615 | return ""; |
d5b7b3ae | 8616 | |
6d3d9133 NC |
8617 | /* Generate the return instruction. */ |
8618 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
8619 | { | |
8620 | case ARM_FT_EXCEPTION_HANDLER: | |
8621 | /* Even in 26-bit mode we do a mov (rather than a movs) | |
8622 | because we don't have the PSR bits set in the address. */ | |
8623 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM); | |
8624 | break; | |
0616531f | 8625 | |
6d3d9133 NC |
8626 | case ARM_FT_ISR: |
8627 | case ARM_FT_FIQ: | |
8628 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
8629 | break; | |
8630 | ||
8631 | case ARM_FT_EXCEPTION: | |
8632 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
8633 | break; | |
8634 | ||
8635 | case ARM_FT_INTERWORKED: | |
8636 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
8637 | break; | |
8638 | ||
8639 | default: | |
8640 | if (frame_pointer_needed) | |
6bc82793 | 8641 | /* If we used the frame pointer then the return address |
6d3d9133 NC |
8642 | will have been loaded off the stack directly into the |
8643 | PC, so there is no need to issue a MOV instruction | |
8644 | here. */ | |
8645 | ; | |
8646 | else if (current_function_pretend_args_size == 0 | |
6f7ebcbb | 8647 | && (saved_regs_mask & (1 << LR_REGNUM))) |
6d3d9133 NC |
8648 | /* Similarly we may have been able to load LR into the PC |
8649 | even if we did not create a stack frame. */ | |
8650 | ; | |
8651 | else if (TARGET_APCS_32) | |
8652 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
8653 | else | |
8654 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
8655 | break; | |
cce8749e | 8656 | } |
f3bb6135 | 8657 | |
949d79eb RE |
8658 | return ""; |
8659 | } | |
8660 | ||
08c148a8 | 8661 | static void |
e32bac5b RE |
8662 | arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
8663 | HOST_WIDE_INT frame_size) | |
949d79eb | 8664 | { |
d5b7b3ae RE |
8665 | if (TARGET_THUMB) |
8666 | { | |
8667 | /* ??? Probably not safe to set this here, since it assumes that a | |
8668 | function will be emitted as assembly immediately after we generate | |
8669 | RTL for it. This does not happen for inline functions. */ | |
8670 | return_used_this_function = 0; | |
8671 | } | |
8672 | else | |
8673 | { | |
0977774b JT |
8674 | /* We need to take into account any stack-frame rounding. */ |
8675 | frame_size = arm_get_frame_size (); | |
8676 | ||
d5b7b3ae RE |
8677 | if (use_return_insn (FALSE) |
8678 | && return_used_this_function | |
8679 | && (frame_size + current_function_outgoing_args_size) != 0 | |
5895f793 | 8680 | && !frame_pointer_needed) |
d5b7b3ae | 8681 | abort (); |
f3bb6135 | 8682 | |
d5b7b3ae | 8683 | /* Reset the ARM-specific per-function variables. */ |
d5b7b3ae RE |
8684 | after_arm_reorg = 0; |
8685 | } | |
f3bb6135 | 8686 | } |
e2c671ba | 8687 | |
2c849145 JM |
8688 | /* Generate and emit an insn that we will recognize as a push_multi. |
8689 | Unfortunately, since this insn does not reflect very well the actual | |
8690 | semantics of the operation, we need to annotate the insn for the benefit | |
8691 | of DWARF2 frame unwind information. */ | |
2c849145 | 8692 | static rtx |
e32bac5b | 8693 | emit_multi_reg_push (int mask) |
e2c671ba RE |
8694 | { |
8695 | int num_regs = 0; | |
9b598fa0 | 8696 | int num_dwarf_regs; |
e2c671ba RE |
8697 | int i, j; |
8698 | rtx par; | |
2c849145 | 8699 | rtx dwarf; |
87e27392 | 8700 | int dwarf_par_index; |
2c849145 | 8701 | rtx tmp, reg; |
e2c671ba | 8702 | |
d5b7b3ae | 8703 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 8704 | if (mask & (1 << i)) |
5895f793 | 8705 | num_regs++; |
e2c671ba RE |
8706 | |
8707 | if (num_regs == 0 || num_regs > 16) | |
8708 | abort (); | |
8709 | ||
9b598fa0 RE |
8710 | /* We don't record the PC in the dwarf frame information. */ |
8711 | num_dwarf_regs = num_regs; | |
8712 | if (mask & (1 << PC_REGNUM)) | |
8713 | num_dwarf_regs--; | |
8714 | ||
87e27392 | 8715 | /* For the body of the insn we are going to generate an UNSPEC in |
05713b80 | 8716 | parallel with several USEs. This allows the insn to be recognized |
87e27392 NC |
8717 | by the push_multi pattern in the arm.md file. The insn looks |
8718 | something like this: | |
8719 | ||
8720 | (parallel [ | |
b15bca31 RE |
8721 | (set (mem:BLK (pre_dec:BLK (reg:SI sp))) |
8722 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) | |
87e27392 NC |
8723 | (use (reg:SI 11 fp)) |
8724 | (use (reg:SI 12 ip)) | |
8725 | (use (reg:SI 14 lr)) | |
8726 | (use (reg:SI 15 pc)) | |
8727 | ]) | |
8728 | ||
8729 | For the frame note however, we try to be more explicit and actually | |
8730 | show each register being stored into the stack frame, plus a (single) | |
8731 | decrement of the stack pointer. We do it this way in order to be | |
8732 | friendly to the stack unwinding code, which only wants to see a single | |
8733 | stack decrement per instruction. The RTL we generate for the note looks | |
8734 | something like this: | |
8735 | ||
8736 | (sequence [ | |
8737 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) | |
8738 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
8739 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) | |
8740 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) | |
8741 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) | |
87e27392 NC |
8742 | ]) |
8743 | ||
8744 | This sequence is used both by the code to support stack unwinding for | |
8745 | exceptions handlers and the code to generate dwarf2 frame debugging. */ | |
8746 | ||
43cffd11 | 8747 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 8748 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
87e27392 | 8749 | dwarf_par_index = 1; |
e2c671ba | 8750 | |
d5b7b3ae | 8751 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
8752 | { |
8753 | if (mask & (1 << i)) | |
8754 | { | |
2c849145 JM |
8755 | reg = gen_rtx_REG (SImode, i); |
8756 | ||
e2c671ba | 8757 | XVECEXP (par, 0, 0) |
43cffd11 RE |
8758 | = gen_rtx_SET (VOIDmode, |
8759 | gen_rtx_MEM (BLKmode, | |
8760 | gen_rtx_PRE_DEC (BLKmode, | |
8761 | stack_pointer_rtx)), | |
8762 | gen_rtx_UNSPEC (BLKmode, | |
2c849145 | 8763 | gen_rtvec (1, reg), |
9b598fa0 | 8764 | UNSPEC_PUSH_MULT)); |
2c849145 | 8765 | |
9b598fa0 RE |
8766 | if (i != PC_REGNUM) |
8767 | { | |
8768 | tmp = gen_rtx_SET (VOIDmode, | |
8769 | gen_rtx_MEM (SImode, stack_pointer_rtx), | |
8770 | reg); | |
8771 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8772 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
8773 | dwarf_par_index++; | |
8774 | } | |
2c849145 | 8775 | |
e2c671ba RE |
8776 | break; |
8777 | } | |
8778 | } | |
8779 | ||
8780 | for (j = 1, i++; j < num_regs; i++) | |
8781 | { | |
8782 | if (mask & (1 << i)) | |
8783 | { | |
2c849145 JM |
8784 | reg = gen_rtx_REG (SImode, i); |
8785 | ||
8786 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
8787 | ||
9b598fa0 RE |
8788 | if (i != PC_REGNUM) |
8789 | { | |
8790 | tmp = gen_rtx_SET (VOIDmode, | |
8791 | gen_rtx_MEM (SImode, | |
8792 | plus_constant (stack_pointer_rtx, | |
8793 | 4 * j)), | |
8794 | reg); | |
8795 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8796 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
8797 | } | |
8798 | ||
e2c671ba RE |
8799 | j++; |
8800 | } | |
8801 | } | |
b111229a | 8802 | |
2c849145 | 8803 | par = emit_insn (par); |
87e27392 NC |
8804 | |
8805 | tmp = gen_rtx_SET (SImode, | |
8806 | stack_pointer_rtx, | |
8807 | gen_rtx_PLUS (SImode, | |
8808 | stack_pointer_rtx, | |
8809 | GEN_INT (-4 * num_regs))); | |
8810 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8811 | XVECEXP (dwarf, 0, 0) = tmp; | |
8812 | ||
2c849145 JM |
8813 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, |
8814 | REG_NOTES (par)); | |
8815 | return par; | |
b111229a RE |
8816 | } |
8817 | ||
2c849145 | 8818 | static rtx |
e32bac5b | 8819 | emit_sfm (int base_reg, int count) |
b111229a RE |
8820 | { |
8821 | rtx par; | |
2c849145 JM |
8822 | rtx dwarf; |
8823 | rtx tmp, reg; | |
b111229a RE |
8824 | int i; |
8825 | ||
43cffd11 | 8826 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
2c849145 | 8827 | dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
2c849145 JM |
8828 | |
8829 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
8830 | |
8831 | XVECEXP (par, 0, 0) | |
8832 | = gen_rtx_SET (VOIDmode, | |
8833 | gen_rtx_MEM (BLKmode, | |
8834 | gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), | |
8835 | gen_rtx_UNSPEC (BLKmode, | |
2c849145 | 8836 | gen_rtvec (1, reg), |
b15bca31 | 8837 | UNSPEC_PUSH_MULT)); |
2c849145 JM |
8838 | tmp |
8839 | = gen_rtx_SET (VOIDmode, | |
8840 | gen_rtx_MEM (XFmode, | |
8841 | gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), | |
8842 | reg); | |
8843 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8844 | XVECEXP (dwarf, 0, count - 1) = tmp; | |
8845 | ||
b111229a | 8846 | for (i = 1; i < count; i++) |
2c849145 JM |
8847 | { |
8848 | reg = gen_rtx_REG (XFmode, base_reg++); | |
8849 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
8850 | ||
8851 | tmp = gen_rtx_SET (VOIDmode, | |
8852 | gen_rtx_MEM (XFmode, | |
8853 | gen_rtx_PRE_DEC (BLKmode, | |
8854 | stack_pointer_rtx)), | |
8855 | reg); | |
8856 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8857 | XVECEXP (dwarf, 0, count - i - 1) = tmp; | |
8858 | } | |
b111229a | 8859 | |
2c849145 JM |
8860 | par = emit_insn (par); |
8861 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
8862 | REG_NOTES (par)); | |
8863 | return par; | |
e2c671ba RE |
8864 | } |
8865 | ||
095bb276 NC |
8866 | /* Compute the distance from register FROM to register TO. |
8867 | These can be the arg pointer (26), the soft frame pointer (25), | |
8868 | the stack pointer (13) or the hard frame pointer (11). | |
8869 | Typical stack layout looks like this: | |
8870 | ||
8871 | old stack pointer -> | | | |
8872 | ---- | |
8873 | | | \ | |
8874 | | | saved arguments for | |
8875 | | | vararg functions | |
8876 | | | / | |
8877 | -- | |
8878 | hard FP & arg pointer -> | | \ | |
8879 | | | stack | |
8880 | | | frame | |
8881 | | | / | |
8882 | -- | |
8883 | | | \ | |
8884 | | | call saved | |
8885 | | | registers | |
8886 | soft frame pointer -> | | / | |
8887 | -- | |
8888 | | | \ | |
8889 | | | local | |
8890 | | | variables | |
8891 | | | / | |
8892 | -- | |
8893 | | | \ | |
8894 | | | outgoing | |
8895 | | | arguments | |
8896 | current stack pointer -> | | / | |
8897 | -- | |
8898 | ||
43aa4e05 | 8899 | For a given function some or all of these stack components |
095bb276 NC |
8900 | may not be needed, giving rise to the possibility of |
8901 | eliminating some of the registers. | |
8902 | ||
825dda42 | 8903 | The values returned by this function must reflect the behavior |
095bb276 NC |
8904 | of arm_expand_prologue() and arm_compute_save_reg_mask(). |
8905 | ||
8906 | The sign of the number returned reflects the direction of stack | |
8907 | growth, so the values are positive for all eliminations except | |
8908 | from the soft frame pointer to the hard frame pointer. */ | |
095bb276 | 8909 | unsigned int |
e32bac5b | 8910 | arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) |
095bb276 | 8911 | { |
0977774b | 8912 | unsigned int local_vars = arm_get_frame_size (); |
095bb276 NC |
8913 | unsigned int outgoing_args = current_function_outgoing_args_size; |
8914 | unsigned int stack_frame; | |
8915 | unsigned int call_saved_registers; | |
8916 | unsigned long func_type; | |
8917 | ||
8918 | func_type = arm_current_func_type (); | |
8919 | ||
8920 | /* Volatile functions never return, so there is | |
8921 | no need to save call saved registers. */ | |
8922 | call_saved_registers = 0; | |
8923 | if (! IS_VOLATILE (func_type)) | |
8924 | { | |
121308d4 | 8925 | unsigned int reg_mask; |
095bb276 NC |
8926 | unsigned int reg; |
8927 | ||
1d6e90ac | 8928 | /* Make sure that we compute which registers will be saved |
121308d4 | 8929 | on the stack using the same algorithm that is used by |
5a9335ef NC |
8930 | the prologue creation code. */ |
8931 | reg_mask = arm_compute_save_reg_mask (); | |
095bb276 | 8932 | |
121308d4 | 8933 | /* Now count the number of bits set in save_reg_mask. |
5a9335ef NC |
8934 | If we have already counted the registers in the stack |
8935 | frame, do not count them again. Non call-saved registers | |
8936 | might be saved in the call-save area of the stack, if | |
8937 | doing so will preserve the stack's alignment. Hence we | |
8938 | must count them here. For each set bit we need 4 bytes | |
8939 | of stack space. */ | |
8940 | if (frame_pointer_needed) | |
8941 | reg_mask &= 0x07ff; | |
8942 | call_saved_registers += 4 * bit_count (reg_mask); | |
ef7112de NC |
8943 | |
8944 | /* If the hard floating point registers are going to be | |
8945 | used then they must be saved on the stack as well. | |
8946 | Each register occupies 12 bytes of stack space. */ | |
5a9335ef | 8947 | for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) |
ef7112de NC |
8948 | if (regs_ever_live[reg] && ! call_used_regs[reg]) |
8949 | call_saved_registers += 12; | |
5a9335ef NC |
8950 | |
8951 | if (TARGET_REALLY_IWMMXT) | |
8952 | /* Check for the call-saved iWMMXt registers. */ | |
8953 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
8954 | if (regs_ever_live[reg] && ! call_used_regs [reg]) | |
8955 | call_saved_registers += 8; | |
095bb276 NC |
8956 | } |
8957 | ||
8958 | /* The stack frame contains 4 registers - the old frame pointer, | |
8959 | the old stack pointer, the return address and PC of the start | |
8960 | of the function. */ | |
8961 | stack_frame = frame_pointer_needed ? 16 : 0; | |
8962 | ||
095bb276 NC |
8963 | /* OK, now we have enough information to compute the distances. |
8964 | There must be an entry in these switch tables for each pair | |
8965 | of registers in ELIMINABLE_REGS, even if some of the entries | |
8966 | seem to be redundant or useless. */ | |
8967 | switch (from) | |
8968 | { | |
8969 | case ARG_POINTER_REGNUM: | |
8970 | switch (to) | |
8971 | { | |
8972 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
8973 | return 0; | |
8974 | ||
8975 | case FRAME_POINTER_REGNUM: | |
8976 | /* This is the reverse of the soft frame pointer | |
8977 | to hard frame pointer elimination below. */ | |
8978 | if (call_saved_registers == 0 && stack_frame == 0) | |
8979 | return 0; | |
8980 | return (call_saved_registers + stack_frame - 4); | |
8981 | ||
8982 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
8983 | /* If there is no stack frame then the hard | |
8984 | frame pointer and the arg pointer coincide. */ | |
8985 | if (stack_frame == 0 && call_saved_registers != 0) | |
8986 | return 0; | |
8987 | /* FIXME: Not sure about this. Maybe we should always return 0 ? */ | |
8988 | return (frame_pointer_needed | |
8989 | && current_function_needs_context | |
3cb66fd7 | 8990 | && ! cfun->machine->uses_anonymous_args) ? 4 : 0; |
095bb276 NC |
8991 | |
8992 | case STACK_POINTER_REGNUM: | |
8993 | /* If nothing has been pushed on the stack at all | |
8994 | then this will return -4. This *is* correct! */ | |
8995 | return call_saved_registers + stack_frame + local_vars + outgoing_args - 4; | |
8996 | ||
8997 | default: | |
8998 | abort (); | |
8999 | } | |
9000 | break; | |
9001 | ||
9002 | case FRAME_POINTER_REGNUM: | |
9003 | switch (to) | |
9004 | { | |
9005 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
9006 | return 0; | |
9007 | ||
9008 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
9009 | /* The hard frame pointer points to the top entry in the | |
9010 | stack frame. The soft frame pointer to the bottom entry | |
9011 | in the stack frame. If there is no stack frame at all, | |
9012 | then they are identical. */ | |
9013 | if (call_saved_registers == 0 && stack_frame == 0) | |
9014 | return 0; | |
9015 | return - (call_saved_registers + stack_frame - 4); | |
9016 | ||
9017 | case STACK_POINTER_REGNUM: | |
9018 | return local_vars + outgoing_args; | |
9019 | ||
9020 | default: | |
9021 | abort (); | |
9022 | } | |
9023 | break; | |
9024 | ||
9025 | default: | |
9026 | /* You cannot eliminate from the stack pointer. | |
9027 | In theory you could eliminate from the hard frame | |
9028 | pointer to the stack pointer, but this will never | |
9029 | happen, since if a stack frame is not needed the | |
9030 | hard frame pointer will never be used. */ | |
9031 | abort (); | |
9032 | } | |
9033 | } | |
9034 | ||
0977774b JT |
9035 | /* Calculate the size of the stack frame, taking into account any |
9036 | padding that is required to ensure stack-alignment. */ | |
0977774b | 9037 | HOST_WIDE_INT |
e32bac5b | 9038 | arm_get_frame_size (void) |
0977774b JT |
9039 | { |
9040 | int regno; | |
9041 | ||
0c2ca901 | 9042 | int base_size = ROUND_UP_WORD (get_frame_size ()); |
0977774b JT |
9043 | int entry_size = 0; |
9044 | unsigned long func_type = arm_current_func_type (); | |
c231c91e | 9045 | int leaf; |
0977774b JT |
9046 | |
9047 | if (! TARGET_ARM) | |
9048 | abort(); | |
9049 | ||
9050 | if (! TARGET_ATPCS) | |
9051 | return base_size; | |
9052 | ||
c231c91e RE |
9053 | /* We need to know if we are a leaf function. Unfortunately, it |
9054 | is possible to be called after start_sequence has been called, | |
9055 | which causes get_insns to return the insns for the sequence, | |
9056 | not the function, which will cause leaf_function_p to return | |
9057 | the incorrect result. | |
9058 | ||
9059 | To work around this, we cache the computed frame size. This | |
9060 | works because we will only be calling RTL expanders that need | |
9061 | to know about leaf functions once reload has completed, and the | |
9062 | frame size cannot be changed after that time, so we can safely | |
9063 | use the cached value. */ | |
9064 | ||
9065 | if (reload_completed) | |
9066 | return cfun->machine->frame_size; | |
9067 | ||
9068 | leaf = leaf_function_p (); | |
9069 | ||
9070 | /* A leaf function does not need any stack alignment if it has nothing | |
9071 | on the stack. */ | |
9072 | if (leaf && base_size == 0) | |
9073 | { | |
9074 | cfun->machine->frame_size = 0; | |
9075 | return 0; | |
9076 | } | |
9077 | ||
0977774b JT |
9078 | /* We know that SP will be word aligned on entry, and we must |
9079 | preserve that condition at any subroutine call. But those are | |
9080 | the only constraints. */ | |
9081 | ||
9082 | /* Space for variadic functions. */ | |
9083 | if (current_function_pretend_args_size) | |
9084 | entry_size += current_function_pretend_args_size; | |
9085 | ||
9086 | /* Space for saved registers. */ | |
9087 | entry_size += bit_count (arm_compute_save_reg_mask ()) * 4; | |
9088 | ||
9089 | /* Space for saved FPA registers. */ | |
9090 | if (! IS_VOLATILE (func_type)) | |
9091 | { | |
9092 | for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++) | |
9093 | if (regs_ever_live[regno] && ! call_used_regs[regno]) | |
9094 | entry_size += 12; | |
9095 | } | |
9096 | ||
5a9335ef NC |
9097 | if (TARGET_REALLY_IWMMXT) |
9098 | { | |
9099 | /* Check for the call-saved iWMMXt registers. */ | |
9100 | for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) | |
9101 | if (regs_ever_live [regno] && ! call_used_regs [regno]) | |
9102 | entry_size += 8; | |
9103 | } | |
9104 | ||
0977774b JT |
9105 | if ((entry_size + base_size + current_function_outgoing_args_size) & 7) |
9106 | base_size += 4; | |
9107 | if ((entry_size + base_size + current_function_outgoing_args_size) & 7) | |
9108 | abort (); | |
9109 | ||
c231c91e RE |
9110 | cfun->machine->frame_size = base_size; |
9111 | ||
0977774b JT |
9112 | return base_size; |
9113 | } | |
9114 | ||
6d3d9133 | 9115 | /* Generate the prologue instructions for entry into an ARM function. */ |
e2c671ba | 9116 | void |
e32bac5b | 9117 | arm_expand_prologue (void) |
e2c671ba RE |
9118 | { |
9119 | int reg; | |
6d3d9133 | 9120 | rtx amount; |
2c849145 | 9121 | rtx insn; |
68dfd979 | 9122 | rtx ip_rtx; |
6d3d9133 NC |
9123 | unsigned long live_regs_mask; |
9124 | unsigned long func_type; | |
68dfd979 | 9125 | int fp_offset = 0; |
095bb276 NC |
9126 | int saved_pretend_args = 0; |
9127 | unsigned int args_to_push; | |
d3236b4d | 9128 | |
6d3d9133 | 9129 | func_type = arm_current_func_type (); |
e2c671ba | 9130 | |
31fdb4d5 | 9131 | /* Naked functions don't have prologues. */ |
6d3d9133 | 9132 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
9133 | return; |
9134 | ||
095bb276 NC |
9135 | /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ |
9136 | args_to_push = current_function_pretend_args_size; | |
9137 | ||
6d3d9133 NC |
9138 | /* Compute which register we will have to save onto the stack. */ |
9139 | live_regs_mask = arm_compute_save_reg_mask (); | |
e2c671ba | 9140 | |
68dfd979 | 9141 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 9142 | |
e2c671ba RE |
9143 | if (frame_pointer_needed) |
9144 | { | |
7b8b8ade NC |
9145 | if (IS_INTERRUPT (func_type)) |
9146 | { | |
9147 | /* Interrupt functions must not corrupt any registers. | |
9148 | Creating a frame pointer however, corrupts the IP | |
9149 | register, so we must push it first. */ | |
9150 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
121308d4 NC |
9151 | |
9152 | /* Do not set RTX_FRAME_RELATED_P on this insn. | |
9153 | The dwarf stack unwinding code only wants to see one | |
9154 | stack decrement per function, and this is not it. If | |
9155 | this instruction is labeled as being part of the frame | |
9156 | creation sequence then dwarf2out_frame_debug_expr will | |
9157 | abort when it encounters the assignment of IP to FP | |
9158 | later on, since the use of SP here establishes SP as | |
9159 | the CFA register and not IP. | |
9160 | ||
9161 | Anyway this instruction is not really part of the stack | |
9162 | frame creation although it is part of the prologue. */ | |
7b8b8ade NC |
9163 | } |
9164 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
9165 | { |
9166 | /* The Static chain register is the same as the IP register | |
9167 | used as a scratch register during stack frame creation. | |
9168 | To get around this need to find somewhere to store IP | |
9169 | whilst the frame is being created. We try the following | |
9170 | places in order: | |
9171 | ||
6d3d9133 | 9172 | 1. The last argument register. |
68dfd979 NC |
9173 | 2. A slot on the stack above the frame. (This only |
9174 | works if the function is not a varargs function). | |
095bb276 NC |
9175 | 3. Register r3, after pushing the argument registers |
9176 | onto the stack. | |
6d3d9133 | 9177 | |
34ce3d7b JM |
9178 | Note - we only need to tell the dwarf2 backend about the SP |
9179 | adjustment in the second variant; the static chain register | |
9180 | doesn't need to be unwound, as it doesn't contain a value | |
9181 | inherited from the caller. */ | |
d3236b4d | 9182 | |
68dfd979 NC |
9183 | if (regs_ever_live[3] == 0) |
9184 | { | |
9185 | insn = gen_rtx_REG (SImode, 3); | |
9186 | insn = gen_rtx_SET (SImode, insn, ip_rtx); | |
d3236b4d | 9187 | insn = emit_insn (insn); |
68dfd979 | 9188 | } |
095bb276 | 9189 | else if (args_to_push == 0) |
68dfd979 | 9190 | { |
34ce3d7b | 9191 | rtx dwarf; |
68dfd979 NC |
9192 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
9193 | insn = gen_rtx_MEM (SImode, insn); | |
9194 | insn = gen_rtx_SET (VOIDmode, insn, ip_rtx); | |
9195 | insn = emit_insn (insn); | |
34ce3d7b | 9196 | |
68dfd979 | 9197 | fp_offset = 4; |
34ce3d7b JM |
9198 | |
9199 | /* Just tell the dwarf backend that we adjusted SP. */ | |
9200 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
9201 | gen_rtx_PLUS (SImode, stack_pointer_rtx, | |
9202 | GEN_INT (-fp_offset))); | |
9203 | RTX_FRAME_RELATED_P (insn) = 1; | |
9204 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
9205 | dwarf, REG_NOTES (insn)); | |
68dfd979 NC |
9206 | } |
9207 | else | |
095bb276 NC |
9208 | { |
9209 | /* Store the args on the stack. */ | |
3cb66fd7 | 9210 | if (cfun->machine->uses_anonymous_args) |
095bb276 NC |
9211 | insn = emit_multi_reg_push |
9212 | ((0xf0 >> (args_to_push / 4)) & 0xf); | |
9213 | else | |
9214 | insn = emit_insn | |
9215 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
9216 | GEN_INT (- args_to_push))); | |
9217 | ||
9218 | RTX_FRAME_RELATED_P (insn) = 1; | |
9219 | ||
9220 | saved_pretend_args = 1; | |
9221 | fp_offset = args_to_push; | |
9222 | args_to_push = 0; | |
9223 | ||
9224 | /* Now reuse r3 to preserve IP. */ | |
9225 | insn = gen_rtx_REG (SImode, 3); | |
9226 | insn = gen_rtx_SET (SImode, insn, ip_rtx); | |
9227 | (void) emit_insn (insn); | |
9228 | } | |
68dfd979 NC |
9229 | } |
9230 | ||
68dfd979 NC |
9231 | if (fp_offset) |
9232 | { | |
9233 | insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset)); | |
9234 | insn = gen_rtx_SET (SImode, ip_rtx, insn); | |
9235 | } | |
9236 | else | |
9237 | insn = gen_movsi (ip_rtx, stack_pointer_rtx); | |
9238 | ||
6d3d9133 | 9239 | insn = emit_insn (insn); |
8e56560e | 9240 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
9241 | } |
9242 | ||
095bb276 | 9243 | if (args_to_push) |
e2c671ba | 9244 | { |
6d3d9133 | 9245 | /* Push the argument registers, or reserve space for them. */ |
3cb66fd7 | 9246 | if (cfun->machine->uses_anonymous_args) |
2c849145 | 9247 | insn = emit_multi_reg_push |
095bb276 | 9248 | ((0xf0 >> (args_to_push / 4)) & 0xf); |
e2c671ba | 9249 | else |
2c849145 JM |
9250 | insn = emit_insn |
9251 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
095bb276 | 9252 | GEN_INT (- args_to_push))); |
2c849145 | 9253 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
9254 | } |
9255 | ||
06bea5aa NC |
9256 | /* If this is an interrupt service routine, and the link register |
9257 | is going to be pushed, and we are not creating a stack frame, | |
9258 | (which would involve an extra push of IP and a pop in the epilogue) | |
9259 | subtracting four from LR now will mean that the function return | |
9260 | can be done with a single instruction. */ | |
3a7731fd | 9261 | if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) |
06bea5aa NC |
9262 | && (live_regs_mask & (1 << LR_REGNUM)) != 0 |
9263 | && ! frame_pointer_needed) | |
9264 | emit_insn (gen_rtx_SET (SImode, | |
9265 | gen_rtx_REG (SImode, LR_REGNUM), | |
9266 | gen_rtx_PLUS (SImode, | |
9267 | gen_rtx_REG (SImode, LR_REGNUM), | |
9268 | GEN_INT (-4)))); | |
3a7731fd | 9269 | |
e2c671ba RE |
9270 | if (live_regs_mask) |
9271 | { | |
2c849145 JM |
9272 | insn = emit_multi_reg_push (live_regs_mask); |
9273 | RTX_FRAME_RELATED_P (insn) = 1; | |
e2c671ba | 9274 | } |
d5b7b3ae | 9275 | |
5a9335ef NC |
9276 | if (TARGET_IWMMXT) |
9277 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
9278 | if (regs_ever_live[reg] && ! call_used_regs [reg]) | |
9279 | { | |
9280 | insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); | |
9281 | insn = gen_rtx_MEM (V2SImode, insn); | |
9282 | insn = emit_insn (gen_rtx_SET (VOIDmode, insn, | |
9283 | gen_rtx_REG (V2SImode, reg))); | |
9284 | RTX_FRAME_RELATED_P (insn) = 1; | |
9285 | } | |
9286 | ||
6d3d9133 | 9287 | if (! IS_VOLATILE (func_type)) |
b111229a | 9288 | { |
29ad9694 RE |
9289 | /* Save any floating point call-saved registers used by this |
9290 | function. */ | |
9291 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
b111229a | 9292 | { |
29ad9694 | 9293 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
5895f793 | 9294 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
2c849145 JM |
9295 | { |
9296 | insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); | |
9297 | insn = gen_rtx_MEM (XFmode, insn); | |
9298 | insn = emit_insn (gen_rtx_SET (VOIDmode, insn, | |
9299 | gen_rtx_REG (XFmode, reg))); | |
9300 | RTX_FRAME_RELATED_P (insn) = 1; | |
9301 | } | |
b111229a RE |
9302 | } |
9303 | else | |
9304 | { | |
d5b7b3ae | 9305 | int start_reg = LAST_ARM_FP_REGNUM; |
b111229a | 9306 | |
29ad9694 | 9307 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
b111229a | 9308 | { |
5895f793 | 9309 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
9310 | { |
9311 | if (start_reg - reg == 3) | |
9312 | { | |
2c849145 JM |
9313 | insn = emit_sfm (reg, 4); |
9314 | RTX_FRAME_RELATED_P (insn) = 1; | |
b111229a RE |
9315 | start_reg = reg - 1; |
9316 | } | |
9317 | } | |
9318 | else | |
9319 | { | |
9320 | if (start_reg != reg) | |
2c849145 JM |
9321 | { |
9322 | insn = emit_sfm (reg + 1, start_reg - reg); | |
9323 | RTX_FRAME_RELATED_P (insn) = 1; | |
9324 | } | |
b111229a RE |
9325 | start_reg = reg - 1; |
9326 | } | |
9327 | } | |
9328 | ||
9329 | if (start_reg != reg) | |
2c849145 JM |
9330 | { |
9331 | insn = emit_sfm (reg + 1, start_reg - reg); | |
9332 | RTX_FRAME_RELATED_P (insn) = 1; | |
9333 | } | |
b111229a RE |
9334 | } |
9335 | } | |
e2c671ba RE |
9336 | |
9337 | if (frame_pointer_needed) | |
2c849145 | 9338 | { |
6d3d9133 | 9339 | /* Create the new frame pointer. */ |
095bb276 | 9340 | insn = GEN_INT (-(4 + args_to_push + fp_offset)); |
68dfd979 | 9341 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); |
2c849145 | 9342 | RTX_FRAME_RELATED_P (insn) = 1; |
68dfd979 | 9343 | |
6d3d9133 | 9344 | if (IS_NESTED (func_type)) |
68dfd979 NC |
9345 | { |
9346 | /* Recover the static chain register. */ | |
095bb276 NC |
9347 | if (regs_ever_live [3] == 0 |
9348 | || saved_pretend_args) | |
1d6e90ac | 9349 | insn = gen_rtx_REG (SImode, 3); |
68dfd979 NC |
9350 | else /* if (current_function_pretend_args_size == 0) */ |
9351 | { | |
29ad9694 RE |
9352 | insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, |
9353 | GEN_INT (4)); | |
68dfd979 | 9354 | insn = gen_rtx_MEM (SImode, insn); |
68dfd979 | 9355 | } |
1d6e90ac | 9356 | |
c14a3a45 NC |
9357 | emit_insn (gen_rtx_SET (SImode, ip_rtx, insn)); |
9358 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
6bacc7b0 | 9359 | emit_insn (gen_prologue_use (ip_rtx)); |
68dfd979 | 9360 | } |
2c849145 | 9361 | } |
e2c671ba | 9362 | |
0977774b | 9363 | amount = GEN_INT (-(arm_get_frame_size () |
6d3d9133 NC |
9364 | + current_function_outgoing_args_size)); |
9365 | ||
e2c671ba RE |
9366 | if (amount != const0_rtx) |
9367 | { | |
745b9093 JM |
9368 | /* This add can produce multiple insns for a large constant, so we |
9369 | need to get tricky. */ | |
9370 | rtx last = get_last_insn (); | |
2c849145 JM |
9371 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
9372 | amount)); | |
745b9093 JM |
9373 | do |
9374 | { | |
9375 | last = last ? NEXT_INSN (last) : get_insns (); | |
9376 | RTX_FRAME_RELATED_P (last) = 1; | |
9377 | } | |
9378 | while (last != insn); | |
e04c2d6c RE |
9379 | |
9380 | /* If the frame pointer is needed, emit a special barrier that | |
9381 | will prevent the scheduler from moving stores to the frame | |
9382 | before the stack adjustment. */ | |
9383 | if (frame_pointer_needed) | |
3894f59e RE |
9384 | insn = emit_insn (gen_stack_tie (stack_pointer_rtx, |
9385 | hard_frame_pointer_rtx)); | |
e2c671ba RE |
9386 | } |
9387 | ||
9388 | /* If we are profiling, make sure no instructions are scheduled before | |
f5a1b0d2 NC |
9389 | the call to mcount. Similarly if the user has requested no |
9390 | scheduling in the prolog. */ | |
70f4f91c | 9391 | if (current_function_profile || TARGET_NO_SCHED_PRO) |
e2c671ba | 9392 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
9393 | |
9394 | /* If the link register is being kept alive, with the return address in it, | |
9395 | then make sure that it does not get reused by the ce2 pass. */ | |
9396 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
9397 | { | |
6bacc7b0 | 9398 | emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); |
6f7ebcbb NC |
9399 | cfun->machine->lr_save_eliminated = 1; |
9400 | } | |
e2c671ba | 9401 | } |
cce8749e | 9402 | \f |
9997d19d RE |
9403 | /* If CODE is 'd', then the X is a condition operand and the instruction |
9404 | should only be executed if the condition is true. | |
ddd5a7c1 | 9405 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
9406 | should only be executed if the condition is false: however, if the mode |
9407 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
9408 | do this because in these circumstances !GE does not necessarily imply LT; | |
9409 | in these cases the instruction pattern will take care to make sure that | |
9410 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 9411 | doing this instruction unconditionally. |
9997d19d RE |
9412 | If CODE is 'N' then X is a floating point operand that must be negated |
9413 | before output. | |
9414 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
9415 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
9997d19d | 9416 | void |
e32bac5b | 9417 | arm_print_operand (FILE *stream, rtx x, int code) |
9997d19d RE |
9418 | { |
9419 | switch (code) | |
9420 | { | |
9421 | case '@': | |
f3139301 | 9422 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
9423 | return; |
9424 | ||
d5b7b3ae RE |
9425 | case '_': |
9426 | fputs (user_label_prefix, stream); | |
9427 | return; | |
9428 | ||
9997d19d | 9429 | case '|': |
f3139301 | 9430 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
9431 | return; |
9432 | ||
9433 | case '?': | |
9434 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
cca0a211 RE |
9435 | { |
9436 | if (TARGET_THUMB || current_insn_predicate != NULL) | |
9437 | abort (); | |
9438 | ||
9439 | fputs (arm_condition_codes[arm_current_cc], stream); | |
9440 | } | |
9441 | else if (current_insn_predicate) | |
9442 | { | |
9443 | enum arm_cond_code code; | |
9444 | ||
9445 | if (TARGET_THUMB) | |
9446 | abort (); | |
9447 | ||
9448 | code = get_arm_condition_code (current_insn_predicate); | |
9449 | fputs (arm_condition_codes[code], stream); | |
9450 | } | |
9997d19d RE |
9451 | return; |
9452 | ||
9453 | case 'N': | |
9454 | { | |
9455 | REAL_VALUE_TYPE r; | |
9456 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
9457 | r = REAL_VALUE_NEGATE (r); | |
9458 | fprintf (stream, "%s", fp_const_from_val (&r)); | |
9459 | } | |
9460 | return; | |
9461 | ||
9462 | case 'B': | |
9463 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
9464 | { |
9465 | HOST_WIDE_INT val; | |
5895f793 | 9466 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 9467 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 9468 | } |
9997d19d RE |
9469 | else |
9470 | { | |
9471 | putc ('~', stream); | |
9472 | output_addr_const (stream, x); | |
9473 | } | |
9474 | return; | |
9475 | ||
9476 | case 'i': | |
9477 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
9478 | return; | |
9479 | ||
9b6b54e2 NC |
9480 | /* Truncate Cirrus shift counts. */ |
9481 | case 's': | |
9482 | if (GET_CODE (x) == CONST_INT) | |
9483 | { | |
9484 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); | |
9485 | return; | |
9486 | } | |
9487 | arm_print_operand (stream, x, 0); | |
9488 | return; | |
9489 | ||
9997d19d RE |
9490 | case 'I': |
9491 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
9492 | return; | |
9493 | ||
9494 | case 'S': | |
9495 | { | |
9496 | HOST_WIDE_INT val; | |
5895f793 | 9497 | const char * shift = shift_op (x, &val); |
9997d19d | 9498 | |
e2c671ba RE |
9499 | if (shift) |
9500 | { | |
5895f793 | 9501 | fprintf (stream, ", %s ", shift_op (x, &val)); |
e2c671ba RE |
9502 | if (val == -1) |
9503 | arm_print_operand (stream, XEXP (x, 1), 0); | |
9504 | else | |
4a0a75dd | 9505 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); |
e2c671ba | 9506 | } |
9997d19d RE |
9507 | } |
9508 | return; | |
9509 | ||
d5b7b3ae RE |
9510 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
9511 | ||
9512 | In a pair of registers containing a DI or DF value the 'Q' | |
9513 | operand returns the register number of the register containing | |
9514 | the least signficant part of the value. The 'R' operand returns | |
9515 | the register number of the register containing the most | |
9516 | significant part of the value. | |
9517 | ||
9518 | The 'H' operand returns the higher of the two register numbers. | |
9519 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
9520 | same as the 'Q' operand, since the most signficant part of the | |
9521 | value is held in the lower number register. The reverse is true | |
9522 | on systems where WORDS_BIG_ENDIAN is false. | |
9523 | ||
9524 | The purpose of these operands is to distinguish between cases | |
9525 | where the endian-ness of the values is important (for example | |
9526 | when they are added together), and cases where the endian-ness | |
9527 | is irrelevant, but the order of register operations is important. | |
9528 | For example when loading a value from memory into a register | |
9529 | pair, the endian-ness does not matter. Provided that the value | |
9530 | from the lower memory address is put into the lower numbered | |
9531 | register, and the value from the higher address is put into the | |
9532 | higher numbered register, the load will work regardless of whether | |
9533 | the value being loaded is big-wordian or little-wordian. The | |
9534 | order of the two register loads can matter however, if the address | |
9535 | of the memory location is actually held in one of the registers | |
9536 | being overwritten by the load. */ | |
c1c2bc04 | 9537 | case 'Q': |
d5b7b3ae | 9538 | if (REGNO (x) > LAST_ARM_REGNUM) |
c1c2bc04 | 9539 | abort (); |
d5b7b3ae | 9540 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
9541 | return; |
9542 | ||
9997d19d | 9543 | case 'R': |
d5b7b3ae | 9544 | if (REGNO (x) > LAST_ARM_REGNUM) |
9997d19d | 9545 | abort (); |
d5b7b3ae RE |
9546 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
9547 | return; | |
9548 | ||
9549 | case 'H': | |
9550 | if (REGNO (x) > LAST_ARM_REGNUM) | |
9551 | abort (); | |
9552 | asm_fprintf (stream, "%r", REGNO (x) + 1); | |
9997d19d RE |
9553 | return; |
9554 | ||
9555 | case 'm': | |
d5b7b3ae RE |
9556 | asm_fprintf (stream, "%r", |
9557 | GET_CODE (XEXP (x, 0)) == REG | |
9558 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
9559 | return; |
9560 | ||
9561 | case 'M': | |
dd18ae56 | 9562 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae | 9563 | REGNO (x), |
e9d7b180 | 9564 | REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); |
9997d19d RE |
9565 | return; |
9566 | ||
9567 | case 'd': | |
64e92a26 RE |
9568 | /* CONST_TRUE_RTX means always -- that's the default. */ |
9569 | if (x == const_true_rtx) | |
d5b7b3ae RE |
9570 | return; |
9571 | ||
9572 | if (TARGET_ARM) | |
9997d19d RE |
9573 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
9574 | stream); | |
d5b7b3ae RE |
9575 | else |
9576 | fputs (thumb_condition_code (x, 0), stream); | |
9997d19d RE |
9577 | return; |
9578 | ||
9579 | case 'D': | |
64e92a26 RE |
9580 | /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever |
9581 | want to do that. */ | |
9582 | if (x == const_true_rtx) | |
9583 | abort (); | |
d5b7b3ae RE |
9584 | |
9585 | if (TARGET_ARM) | |
9586 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE | |
9587 | (get_arm_condition_code (x))], | |
9997d19d | 9588 | stream); |
d5b7b3ae RE |
9589 | else |
9590 | fputs (thumb_condition_code (x, 1), stream); | |
9997d19d RE |
9591 | return; |
9592 | ||
9b6b54e2 NC |
9593 | /* Cirrus registers can be accessed in a variety of ways: |
9594 | single floating point (f) | |
9595 | double floating point (d) | |
9596 | 32bit integer (fx) | |
9597 | 64bit integer (dx). */ | |
9598 | case 'W': /* Cirrus register in F mode. */ | |
9599 | case 'X': /* Cirrus register in D mode. */ | |
9600 | case 'Y': /* Cirrus register in FX mode. */ | |
9601 | case 'Z': /* Cirrus register in DX mode. */ | |
9602 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
9603 | abort (); | |
9604 | ||
9605 | fprintf (stream, "mv%s%s", | |
9606 | code == 'W' ? "f" | |
9607 | : code == 'X' ? "d" | |
9608 | : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); | |
9609 | ||
9610 | return; | |
9611 | ||
9612 | /* Print cirrus register in the mode specified by the register's mode. */ | |
9613 | case 'V': | |
9614 | { | |
9615 | int mode = GET_MODE (x); | |
9616 | ||
9617 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
9618 | abort (); | |
9619 | ||
9620 | fprintf (stream, "mv%s%s", | |
9621 | mode == DFmode ? "d" | |
9622 | : mode == SImode ? "fx" | |
9623 | : mode == DImode ? "dx" | |
9624 | : "f", reg_names[REGNO (x)] + 2); | |
9625 | ||
9626 | return; | |
9627 | } | |
9628 | ||
5a9335ef NC |
9629 | case 'U': |
9630 | if (GET_CODE (x) != REG | |
9631 | || REGNO (x) < FIRST_IWMMXT_GR_REGNUM | |
9632 | || REGNO (x) > LAST_IWMMXT_GR_REGNUM) | |
9633 | /* Bad value for wCG register number. */ | |
9634 | abort (); | |
9635 | else | |
9636 | fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); | |
9637 | return; | |
9638 | ||
9639 | /* Print an iWMMXt control register name. */ | |
9640 | case 'w': | |
9641 | if (GET_CODE (x) != CONST_INT | |
9642 | || INTVAL (x) < 0 | |
9643 | || INTVAL (x) >= 16) | |
9644 | /* Bad value for wC register number. */ | |
9645 | abort (); | |
9646 | else | |
9647 | { | |
9648 | static const char * wc_reg_names [16] = | |
9649 | { | |
9650 | "wCID", "wCon", "wCSSF", "wCASF", | |
9651 | "wC4", "wC5", "wC6", "wC7", | |
9652 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", | |
9653 | "wC12", "wC13", "wC14", "wC15" | |
9654 | }; | |
9655 | ||
9656 | fprintf (stream, wc_reg_names [INTVAL (x)]); | |
9657 | } | |
9658 | return; | |
9659 | ||
9997d19d RE |
9660 | default: |
9661 | if (x == 0) | |
9662 | abort (); | |
9663 | ||
9664 | if (GET_CODE (x) == REG) | |
d5b7b3ae | 9665 | asm_fprintf (stream, "%r", REGNO (x)); |
9997d19d RE |
9666 | else if (GET_CODE (x) == MEM) |
9667 | { | |
9668 | output_memory_reference_mode = GET_MODE (x); | |
9669 | output_address (XEXP (x, 0)); | |
9670 | } | |
9671 | else if (GET_CODE (x) == CONST_DOUBLE) | |
9672 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
9673 | else if (GET_CODE (x) == NEG) | |
6354dc9b | 9674 | abort (); /* This should never happen now. */ |
9997d19d RE |
9675 | else |
9676 | { | |
9677 | fputc ('#', stream); | |
9678 | output_addr_const (stream, x); | |
9679 | } | |
9680 | } | |
9681 | } | |
cce8749e | 9682 | \f |
301d03af RS |
9683 | #ifndef AOF_ASSEMBLER |
9684 | /* Target hook for assembling integer objects. The ARM version needs to | |
9685 | handle word-sized values specially. */ | |
301d03af | 9686 | static bool |
e32bac5b | 9687 | arm_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
9688 | { |
9689 | if (size == UNITS_PER_WORD && aligned_p) | |
9690 | { | |
9691 | fputs ("\t.word\t", asm_out_file); | |
9692 | output_addr_const (asm_out_file, x); | |
9693 | ||
9694 | /* Mark symbols as position independent. We only do this in the | |
9695 | .text segment, not in the .data segment. */ | |
9696 | if (NEED_GOT_RELOC && flag_pic && making_const_table && | |
9697 | (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) | |
9698 | { | |
e26053d1 | 9699 | if (GET_CODE (x) == SYMBOL_REF |
14f583b8 PB |
9700 | && (CONSTANT_POOL_ADDRESS_P (x) |
9701 | || ENCODED_SHORT_CALL_ATTR_P (XSTR (x, 0)))) | |
301d03af RS |
9702 | fputs ("(GOTOFF)", asm_out_file); |
9703 | else if (GET_CODE (x) == LABEL_REF) | |
9704 | fputs ("(GOTOFF)", asm_out_file); | |
9705 | else | |
9706 | fputs ("(GOT)", asm_out_file); | |
9707 | } | |
9708 | fputc ('\n', asm_out_file); | |
9709 | return true; | |
9710 | } | |
1d6e90ac | 9711 | |
5a9335ef NC |
9712 | if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x))) |
9713 | { | |
9714 | int i, units; | |
9715 | ||
9716 | if (GET_CODE (x) != CONST_VECTOR) | |
9717 | abort (); | |
9718 | ||
9719 | units = CONST_VECTOR_NUNITS (x); | |
9720 | ||
9721 | switch (GET_MODE (x)) | |
9722 | { | |
9723 | case V2SImode: size = 4; break; | |
9724 | case V4HImode: size = 2; break; | |
9725 | case V8QImode: size = 1; break; | |
9726 | default: | |
9727 | abort (); | |
9728 | } | |
9729 | ||
9730 | for (i = 0; i < units; i++) | |
9731 | { | |
9732 | rtx elt; | |
9733 | ||
9734 | elt = CONST_VECTOR_ELT (x, i); | |
9735 | assemble_integer | |
9736 | (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); | |
9737 | } | |
9738 | ||
9739 | return true; | |
9740 | } | |
9741 | ||
301d03af RS |
9742 | return default_assemble_integer (x, size, aligned_p); |
9743 | } | |
9744 | #endif | |
9745 | \f | |
cce8749e CH |
9746 | /* A finite state machine takes care of noticing whether or not instructions |
9747 | can be conditionally executed, and thus decrease execution time and code | |
9748 | size by deleting branch instructions. The fsm is controlled by | |
9749 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
9750 | ||
9751 | /* The state of the fsm controlling condition codes are: | |
9752 | 0: normal, do nothing special | |
9753 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
9754 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
9755 | 3: make instructions conditional | |
9756 | 4: make instructions conditional | |
9757 | ||
9758 | State transitions (state->state by whom under condition): | |
9759 | 0 -> 1 final_prescan_insn if the `target' is a label | |
9760 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
9761 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
9762 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
4977bab6 | 9763 | 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached |
cce8749e CH |
9764 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). |
9765 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
9766 | (the target insn is arm_target_insn). | |
9767 | ||
ff9940b0 RE |
9768 | If the jump clobbers the conditions then we use states 2 and 4. |
9769 | ||
9770 | A similar thing can be done with conditional return insns. | |
9771 | ||
cce8749e CH |
9772 | XXX In case the `target' is an unconditional branch, this conditionalising |
9773 | of the instructions always reduces code size, but not always execution | |
9774 | time. But then, I want to reduce the code size to somewhere near what | |
9775 | /bin/cc produces. */ | |
9776 | ||
cce8749e CH |
9777 | /* Returns the index of the ARM condition code string in |
9778 | `arm_condition_codes'. COMPARISON should be an rtx like | |
9779 | `(eq (...) (...))'. */ | |
84ed5e79 | 9780 | static enum arm_cond_code |
e32bac5b | 9781 | get_arm_condition_code (rtx comparison) |
cce8749e | 9782 | { |
5165176d | 9783 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
1d6e90ac NC |
9784 | int code; |
9785 | enum rtx_code comp_code = GET_CODE (comparison); | |
5165176d RE |
9786 | |
9787 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 9788 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
9789 | XEXP (comparison, 1)); |
9790 | ||
9791 | switch (mode) | |
cce8749e | 9792 | { |
84ed5e79 RE |
9793 | case CC_DNEmode: code = ARM_NE; goto dominance; |
9794 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
9795 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
9796 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
9797 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
9798 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
9799 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
9800 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
9801 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
9802 | case CC_DLTUmode: code = ARM_CC; | |
9803 | ||
9804 | dominance: | |
9805 | if (comp_code != EQ && comp_code != NE) | |
9806 | abort (); | |
9807 | ||
9808 | if (comp_code == EQ) | |
9809 | return ARM_INVERSE_CONDITION_CODE (code); | |
9810 | return code; | |
9811 | ||
5165176d | 9812 | case CC_NOOVmode: |
84ed5e79 | 9813 | switch (comp_code) |
5165176d | 9814 | { |
84ed5e79 RE |
9815 | case NE: return ARM_NE; |
9816 | case EQ: return ARM_EQ; | |
9817 | case GE: return ARM_PL; | |
9818 | case LT: return ARM_MI; | |
5165176d RE |
9819 | default: abort (); |
9820 | } | |
9821 | ||
9822 | case CC_Zmode: | |
84ed5e79 | 9823 | switch (comp_code) |
5165176d | 9824 | { |
84ed5e79 RE |
9825 | case NE: return ARM_NE; |
9826 | case EQ: return ARM_EQ; | |
5165176d RE |
9827 | default: abort (); |
9828 | } | |
9829 | ||
9830 | case CCFPEmode: | |
e45b72c4 RE |
9831 | case CCFPmode: |
9832 | /* These encodings assume that AC=1 in the FPA system control | |
9833 | byte. This allows us to handle all cases except UNEQ and | |
9834 | LTGT. */ | |
84ed5e79 RE |
9835 | switch (comp_code) |
9836 | { | |
9837 | case GE: return ARM_GE; | |
9838 | case GT: return ARM_GT; | |
9839 | case LE: return ARM_LS; | |
9840 | case LT: return ARM_MI; | |
e45b72c4 RE |
9841 | case NE: return ARM_NE; |
9842 | case EQ: return ARM_EQ; | |
9843 | case ORDERED: return ARM_VC; | |
9844 | case UNORDERED: return ARM_VS; | |
9845 | case UNLT: return ARM_LT; | |
9846 | case UNLE: return ARM_LE; | |
9847 | case UNGT: return ARM_HI; | |
9848 | case UNGE: return ARM_PL; | |
9849 | /* UNEQ and LTGT do not have a representation. */ | |
9850 | case UNEQ: /* Fall through. */ | |
9851 | case LTGT: /* Fall through. */ | |
84ed5e79 RE |
9852 | default: abort (); |
9853 | } | |
9854 | ||
9855 | case CC_SWPmode: | |
9856 | switch (comp_code) | |
9857 | { | |
9858 | case NE: return ARM_NE; | |
9859 | case EQ: return ARM_EQ; | |
9860 | case GE: return ARM_LE; | |
9861 | case GT: return ARM_LT; | |
9862 | case LE: return ARM_GE; | |
9863 | case LT: return ARM_GT; | |
9864 | case GEU: return ARM_LS; | |
9865 | case GTU: return ARM_CC; | |
9866 | case LEU: return ARM_CS; | |
9867 | case LTU: return ARM_HI; | |
9868 | default: abort (); | |
9869 | } | |
9870 | ||
bd9c7e23 RE |
9871 | case CC_Cmode: |
9872 | switch (comp_code) | |
9873 | { | |
9874 | case LTU: return ARM_CS; | |
9875 | case GEU: return ARM_CC; | |
9876 | default: abort (); | |
9877 | } | |
9878 | ||
5165176d | 9879 | case CCmode: |
84ed5e79 | 9880 | switch (comp_code) |
5165176d | 9881 | { |
84ed5e79 RE |
9882 | case NE: return ARM_NE; |
9883 | case EQ: return ARM_EQ; | |
9884 | case GE: return ARM_GE; | |
9885 | case GT: return ARM_GT; | |
9886 | case LE: return ARM_LE; | |
9887 | case LT: return ARM_LT; | |
9888 | case GEU: return ARM_CS; | |
9889 | case GTU: return ARM_HI; | |
9890 | case LEU: return ARM_LS; | |
9891 | case LTU: return ARM_CC; | |
5165176d RE |
9892 | default: abort (); |
9893 | } | |
9894 | ||
cce8749e CH |
9895 | default: abort (); |
9896 | } | |
84ed5e79 RE |
9897 | |
9898 | abort (); | |
f3bb6135 | 9899 | } |
cce8749e | 9900 | |
cce8749e | 9901 | void |
e32bac5b | 9902 | arm_final_prescan_insn (rtx insn) |
cce8749e CH |
9903 | { |
9904 | /* BODY will hold the body of INSN. */ | |
1d6e90ac | 9905 | rtx body = PATTERN (insn); |
cce8749e CH |
9906 | |
9907 | /* This will be 1 if trying to repeat the trick, and things need to be | |
9908 | reversed if it appears to fail. */ | |
9909 | int reverse = 0; | |
9910 | ||
ff9940b0 RE |
9911 | /* JUMP_CLOBBERS will be one implies that the conditions if a branch is |
9912 | taken are clobbered, even if the rtl suggests otherwise. It also | |
9913 | means that we have to grub around within the jump expression to find | |
9914 | out what the conditions are when the jump isn't taken. */ | |
9915 | int jump_clobbers = 0; | |
9916 | ||
6354dc9b | 9917 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 RE |
9918 | int seeking_return = 0; |
9919 | ||
cce8749e CH |
9920 | /* START_INSN will hold the insn from where we start looking. This is the |
9921 | first insn after the following code_label if REVERSE is true. */ | |
9922 | rtx start_insn = insn; | |
9923 | ||
9924 | /* If in state 4, check if the target branch is reached, in order to | |
9925 | change back to state 0. */ | |
9926 | if (arm_ccfsm_state == 4) | |
9927 | { | |
9928 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
9929 | { |
9930 | arm_target_insn = NULL; | |
9931 | arm_ccfsm_state = 0; | |
9932 | } | |
cce8749e CH |
9933 | return; |
9934 | } | |
9935 | ||
9936 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
9937 | unconditional branch to a label, and immediately following this branch | |
9938 | is the previous target label which is only used once, and the label this | |
9939 | branch jumps to is not too far off. */ | |
9940 | if (arm_ccfsm_state == 3) | |
9941 | { | |
9942 | if (simplejump_p (insn)) | |
9943 | { | |
9944 | start_insn = next_nonnote_insn (start_insn); | |
9945 | if (GET_CODE (start_insn) == BARRIER) | |
9946 | { | |
9947 | /* XXX Isn't this always a barrier? */ | |
9948 | start_insn = next_nonnote_insn (start_insn); | |
9949 | } | |
9950 | if (GET_CODE (start_insn) == CODE_LABEL | |
9951 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
9952 | && LABEL_NUSES (start_insn) == 1) | |
9953 | reverse = TRUE; | |
9954 | else | |
9955 | return; | |
9956 | } | |
ff9940b0 RE |
9957 | else if (GET_CODE (body) == RETURN) |
9958 | { | |
9959 | start_insn = next_nonnote_insn (start_insn); | |
9960 | if (GET_CODE (start_insn) == BARRIER) | |
9961 | start_insn = next_nonnote_insn (start_insn); | |
9962 | if (GET_CODE (start_insn) == CODE_LABEL | |
9963 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
9964 | && LABEL_NUSES (start_insn) == 1) | |
9965 | { | |
9966 | reverse = TRUE; | |
9967 | seeking_return = 1; | |
9968 | } | |
9969 | else | |
9970 | return; | |
9971 | } | |
cce8749e CH |
9972 | else |
9973 | return; | |
9974 | } | |
9975 | ||
9976 | if (arm_ccfsm_state != 0 && !reverse) | |
9977 | abort (); | |
9978 | if (GET_CODE (insn) != JUMP_INSN) | |
9979 | return; | |
9980 | ||
ddd5a7c1 | 9981 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
9982 | the jump should always come first */ |
9983 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
9984 | body = XVECEXP (body, 0, 0); | |
9985 | ||
9986 | #if 0 | |
9987 | /* If this is a conditional return then we don't want to know */ | |
9988 | if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
9989 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE | |
9990 | && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN | |
9991 | || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)) | |
9992 | return; | |
9993 | #endif | |
9994 | ||
cce8749e CH |
9995 | if (reverse |
9996 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
9997 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
9998 | { | |
bd9c7e23 RE |
9999 | int insns_skipped; |
10000 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
10001 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
10002 | int then_not_else = TRUE; | |
ff9940b0 | 10003 | rtx this_insn = start_insn, label = 0; |
cce8749e | 10004 | |
e45b72c4 RE |
10005 | /* If the jump cannot be done with one instruction, we cannot |
10006 | conditionally execute the instruction in the inverse case. */ | |
ff9940b0 | 10007 | if (get_attr_conds (insn) == CONDS_JUMP_CLOB) |
5bbe2d40 | 10008 | { |
5bbe2d40 RE |
10009 | jump_clobbers = 1; |
10010 | return; | |
10011 | } | |
ff9940b0 | 10012 | |
cce8749e CH |
10013 | /* Register the insn jumped to. */ |
10014 | if (reverse) | |
ff9940b0 RE |
10015 | { |
10016 | if (!seeking_return) | |
10017 | label = XEXP (SET_SRC (body), 0); | |
10018 | } | |
cce8749e CH |
10019 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
10020 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
10021 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
10022 | { | |
10023 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
10024 | then_not_else = FALSE; | |
10025 | } | |
ff9940b0 RE |
10026 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
10027 | seeking_return = 1; | |
10028 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
10029 | { | |
10030 | seeking_return = 1; | |
10031 | then_not_else = FALSE; | |
10032 | } | |
cce8749e CH |
10033 | else |
10034 | abort (); | |
10035 | ||
10036 | /* See how many insns this branch skips, and what kind of insns. If all | |
10037 | insns are okay, and the label or unconditional branch to the same | |
10038 | label is not too far away, succeed. */ | |
10039 | for (insns_skipped = 0; | |
b36ba79f | 10040 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
10041 | { |
10042 | rtx scanbody; | |
10043 | ||
10044 | this_insn = next_nonnote_insn (this_insn); | |
10045 | if (!this_insn) | |
10046 | break; | |
10047 | ||
cce8749e CH |
10048 | switch (GET_CODE (this_insn)) |
10049 | { | |
10050 | case CODE_LABEL: | |
10051 | /* Succeed if it is the target label, otherwise fail since | |
10052 | control falls in from somewhere else. */ | |
10053 | if (this_insn == label) | |
10054 | { | |
ff9940b0 RE |
10055 | if (jump_clobbers) |
10056 | { | |
10057 | arm_ccfsm_state = 2; | |
10058 | this_insn = next_nonnote_insn (this_insn); | |
10059 | } | |
10060 | else | |
10061 | arm_ccfsm_state = 1; | |
cce8749e CH |
10062 | succeed = TRUE; |
10063 | } | |
10064 | else | |
10065 | fail = TRUE; | |
10066 | break; | |
10067 | ||
ff9940b0 | 10068 | case BARRIER: |
cce8749e | 10069 | /* Succeed if the following insn is the target label. |
ff9940b0 RE |
10070 | Otherwise fail. |
10071 | If return insns are used then the last insn in a function | |
6354dc9b | 10072 | will be a barrier. */ |
cce8749e | 10073 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 10074 | if (this_insn && this_insn == label) |
cce8749e | 10075 | { |
ff9940b0 RE |
10076 | if (jump_clobbers) |
10077 | { | |
10078 | arm_ccfsm_state = 2; | |
10079 | this_insn = next_nonnote_insn (this_insn); | |
10080 | } | |
10081 | else | |
10082 | arm_ccfsm_state = 1; | |
cce8749e CH |
10083 | succeed = TRUE; |
10084 | } | |
10085 | else | |
10086 | fail = TRUE; | |
10087 | break; | |
10088 | ||
ff9940b0 | 10089 | case CALL_INSN: |
2b835d68 | 10090 | /* If using 32-bit addresses the cc is not preserved over |
914a3b8c | 10091 | calls. */ |
2b835d68 | 10092 | if (TARGET_APCS_32) |
bd9c7e23 RE |
10093 | { |
10094 | /* Succeed if the following insn is the target label, | |
10095 | or if the following two insns are a barrier and | |
10096 | the target label. */ | |
10097 | this_insn = next_nonnote_insn (this_insn); | |
10098 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
10099 | this_insn = next_nonnote_insn (this_insn); | |
10100 | ||
10101 | if (this_insn && this_insn == label | |
b36ba79f | 10102 | && insns_skipped < max_insns_skipped) |
bd9c7e23 RE |
10103 | { |
10104 | if (jump_clobbers) | |
10105 | { | |
10106 | arm_ccfsm_state = 2; | |
10107 | this_insn = next_nonnote_insn (this_insn); | |
10108 | } | |
10109 | else | |
10110 | arm_ccfsm_state = 1; | |
10111 | succeed = TRUE; | |
10112 | } | |
10113 | else | |
10114 | fail = TRUE; | |
10115 | } | |
ff9940b0 | 10116 | break; |
2b835d68 | 10117 | |
cce8749e CH |
10118 | case JUMP_INSN: |
10119 | /* If this is an unconditional branch to the same label, succeed. | |
10120 | If it is to another label, do nothing. If it is conditional, | |
10121 | fail. */ | |
e32bac5b RE |
10122 | /* XXX Probably, the tests for SET and the PC are |
10123 | unnecessary. */ | |
cce8749e | 10124 | |
ed4c4348 | 10125 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
10126 | if (GET_CODE (scanbody) == SET |
10127 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
10128 | { |
10129 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
10130 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
10131 | { | |
10132 | arm_ccfsm_state = 2; | |
10133 | succeed = TRUE; | |
10134 | } | |
10135 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
10136 | fail = TRUE; | |
10137 | } | |
b36ba79f RE |
10138 | /* Fail if a conditional return is undesirable (eg on a |
10139 | StrongARM), but still allow this if optimizing for size. */ | |
10140 | else if (GET_CODE (scanbody) == RETURN | |
5895f793 RE |
10141 | && !use_return_insn (TRUE) |
10142 | && !optimize_size) | |
b36ba79f | 10143 | fail = TRUE; |
ff9940b0 RE |
10144 | else if (GET_CODE (scanbody) == RETURN |
10145 | && seeking_return) | |
10146 | { | |
10147 | arm_ccfsm_state = 2; | |
10148 | succeed = TRUE; | |
10149 | } | |
10150 | else if (GET_CODE (scanbody) == PARALLEL) | |
10151 | { | |
10152 | switch (get_attr_conds (this_insn)) | |
10153 | { | |
10154 | case CONDS_NOCOND: | |
10155 | break; | |
10156 | default: | |
10157 | fail = TRUE; | |
10158 | break; | |
10159 | } | |
10160 | } | |
4e67550b RE |
10161 | else |
10162 | fail = TRUE; /* Unrecognized jump (eg epilogue). */ | |
10163 | ||
cce8749e CH |
10164 | break; |
10165 | ||
10166 | case INSN: | |
ff9940b0 RE |
10167 | /* Instructions using or affecting the condition codes make it |
10168 | fail. */ | |
ed4c4348 | 10169 | scanbody = PATTERN (this_insn); |
5895f793 RE |
10170 | if (!(GET_CODE (scanbody) == SET |
10171 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 10172 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e | 10173 | fail = TRUE; |
9b6b54e2 NC |
10174 | |
10175 | /* A conditional cirrus instruction must be followed by | |
10176 | a non Cirrus instruction. However, since we | |
10177 | conditionalize instructions in this function and by | |
10178 | the time we get here we can't add instructions | |
10179 | (nops), because shorten_branches() has already been | |
10180 | called, we will disable conditionalizing Cirrus | |
10181 | instructions to be safe. */ | |
10182 | if (GET_CODE (scanbody) != USE | |
10183 | && GET_CODE (scanbody) != CLOBBER | |
f0375c66 | 10184 | && get_attr_cirrus (this_insn) != CIRRUS_NOT) |
9b6b54e2 | 10185 | fail = TRUE; |
cce8749e CH |
10186 | break; |
10187 | ||
10188 | default: | |
10189 | break; | |
10190 | } | |
10191 | } | |
10192 | if (succeed) | |
10193 | { | |
ff9940b0 | 10194 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 10195 | arm_target_label = CODE_LABEL_NUMBER (label); |
ff9940b0 RE |
10196 | else if (seeking_return || arm_ccfsm_state == 2) |
10197 | { | |
10198 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) | |
10199 | { | |
10200 | this_insn = next_nonnote_insn (this_insn); | |
10201 | if (this_insn && (GET_CODE (this_insn) == BARRIER | |
10202 | || GET_CODE (this_insn) == CODE_LABEL)) | |
10203 | abort (); | |
10204 | } | |
10205 | if (!this_insn) | |
10206 | { | |
10207 | /* Oh, dear! we ran off the end.. give up */ | |
df4ae160 | 10208 | recog (PATTERN (insn), insn, NULL); |
ff9940b0 | 10209 | arm_ccfsm_state = 0; |
abaa26e5 | 10210 | arm_target_insn = NULL; |
ff9940b0 RE |
10211 | return; |
10212 | } | |
10213 | arm_target_insn = this_insn; | |
10214 | } | |
cce8749e CH |
10215 | else |
10216 | abort (); | |
ff9940b0 RE |
10217 | if (jump_clobbers) |
10218 | { | |
10219 | if (reverse) | |
10220 | abort (); | |
10221 | arm_current_cc = | |
10222 | get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), | |
10223 | 0), 0), 1)); | |
10224 | if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) | |
10225 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
10226 | if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) | |
10227 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
10228 | } | |
10229 | else | |
10230 | { | |
10231 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
10232 | what it was. */ | |
10233 | if (!reverse) | |
10234 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), | |
10235 | 0)); | |
10236 | } | |
cce8749e | 10237 | |
cce8749e CH |
10238 | if (reverse || then_not_else) |
10239 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
10240 | } | |
d5b7b3ae | 10241 | |
1ccbefce | 10242 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 10243 | destroy this array, but final.c assumes that it remains intact |
ddd5a7c1 | 10244 | across this call; since the insn has been recognized already we |
b020fd92 | 10245 | call recog direct). */ |
df4ae160 | 10246 | recog (PATTERN (insn), insn, NULL); |
cce8749e | 10247 | } |
f3bb6135 | 10248 | } |
cce8749e | 10249 | |
4b02997f NC |
10250 | /* Returns true if REGNO is a valid register |
10251 | for holding a quantity of tyoe MODE. */ | |
4b02997f | 10252 | int |
e32bac5b | 10253 | arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) |
4b02997f NC |
10254 | { |
10255 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
10256 | return regno == CC_REGNUM; | |
10257 | ||
10258 | if (TARGET_THUMB) | |
10259 | /* For the Thumb we only allow values bigger than SImode in | |
10260 | registers 0 - 6, so that there is always a second low | |
10261 | register available to hold the upper part of the value. | |
10262 | We probably we ought to ensure that the register is the | |
10263 | start of an even numbered register pair. */ | |
e9d7b180 | 10264 | return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); |
4b02997f | 10265 | |
9b6b54e2 NC |
10266 | if (IS_CIRRUS_REGNUM (regno)) |
10267 | /* We have outlawed SI values in Cirrus registers because they | |
10268 | reside in the lower 32 bits, but SF values reside in the | |
10269 | upper 32 bits. This causes gcc all sorts of grief. We can't | |
10270 | even split the registers into pairs because Cirrus SI values | |
10271 | get sign extended to 64bits-- aldyh. */ | |
10272 | return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); | |
10273 | ||
5a9335ef NC |
10274 | if (IS_IWMMXT_GR_REGNUM (regno)) |
10275 | return mode == SImode; | |
10276 | ||
10277 | if (IS_IWMMXT_REGNUM (regno)) | |
10278 | return VALID_IWMMXT_REG_MODE (mode); | |
10279 | ||
4b02997f | 10280 | if (regno <= LAST_ARM_REGNUM) |
3cb66fd7 NC |
10281 | /* We allow any value to be stored in the general regisetrs. */ |
10282 | return 1; | |
4b02997f NC |
10283 | |
10284 | if ( regno == FRAME_POINTER_REGNUM | |
10285 | || regno == ARG_POINTER_REGNUM) | |
10286 | /* We only allow integers in the fake hard registers. */ | |
10287 | return GET_MODE_CLASS (mode) == MODE_INT; | |
10288 | ||
3b684012 | 10289 | /* The only registers left are the FPA registers |
4b02997f NC |
10290 | which we only allow to hold FP values. */ |
10291 | return GET_MODE_CLASS (mode) == MODE_FLOAT | |
10292 | && regno >= FIRST_ARM_FP_REGNUM | |
10293 | && regno <= LAST_ARM_FP_REGNUM; | |
10294 | } | |
10295 | ||
d5b7b3ae | 10296 | int |
e32bac5b | 10297 | arm_regno_class (int regno) |
d5b7b3ae RE |
10298 | { |
10299 | if (TARGET_THUMB) | |
10300 | { | |
10301 | if (regno == STACK_POINTER_REGNUM) | |
10302 | return STACK_REG; | |
10303 | if (regno == CC_REGNUM) | |
10304 | return CC_REG; | |
10305 | if (regno < 8) | |
10306 | return LO_REGS; | |
10307 | return HI_REGS; | |
10308 | } | |
10309 | ||
10310 | if ( regno <= LAST_ARM_REGNUM | |
10311 | || regno == FRAME_POINTER_REGNUM | |
10312 | || regno == ARG_POINTER_REGNUM) | |
10313 | return GENERAL_REGS; | |
10314 | ||
10315 | if (regno == CC_REGNUM) | |
10316 | return NO_REGS; | |
10317 | ||
9b6b54e2 NC |
10318 | if (IS_CIRRUS_REGNUM (regno)) |
10319 | return CIRRUS_REGS; | |
10320 | ||
5a9335ef NC |
10321 | if (IS_IWMMXT_REGNUM (regno)) |
10322 | return IWMMXT_REGS; | |
10323 | ||
3b684012 | 10324 | return FPA_REGS; |
d5b7b3ae RE |
10325 | } |
10326 | ||
10327 | /* Handle a special case when computing the offset | |
10328 | of an argument from the frame pointer. */ | |
10329 | int | |
e32bac5b | 10330 | arm_debugger_arg_offset (int value, rtx addr) |
d5b7b3ae RE |
10331 | { |
10332 | rtx insn; | |
10333 | ||
10334 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
10335 | if (value != 0) | |
10336 | return 0; | |
10337 | ||
10338 | /* We can only cope with the case where the address is held in a register. */ | |
10339 | if (GET_CODE (addr) != REG) | |
10340 | return 0; | |
10341 | ||
10342 | /* If we are using the frame pointer to point at the argument, then | |
10343 | an offset of 0 is correct. */ | |
cd2b33d0 | 10344 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae RE |
10345 | return 0; |
10346 | ||
10347 | /* If we are using the stack pointer to point at the | |
10348 | argument, then an offset of 0 is correct. */ | |
5895f793 | 10349 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
10350 | && REGNO (addr) == SP_REGNUM) |
10351 | return 0; | |
10352 | ||
10353 | /* Oh dear. The argument is pointed to by a register rather | |
10354 | than being held in a register, or being stored at a known | |
10355 | offset from the frame pointer. Since GDB only understands | |
10356 | those two kinds of argument we must translate the address | |
10357 | held in the register into an offset from the frame pointer. | |
10358 | We do this by searching through the insns for the function | |
10359 | looking to see where this register gets its value. If the | |
4912a07c | 10360 | register is initialized from the frame pointer plus an offset |
d5b7b3ae RE |
10361 | then we are in luck and we can continue, otherwise we give up. |
10362 | ||
10363 | This code is exercised by producing debugging information | |
10364 | for a function with arguments like this: | |
10365 | ||
10366 | double func (double a, double b, int c, double d) {return d;} | |
10367 | ||
10368 | Without this code the stab for parameter 'd' will be set to | |
10369 | an offset of 0 from the frame pointer, rather than 8. */ | |
10370 | ||
10371 | /* The if() statement says: | |
10372 | ||
10373 | If the insn is a normal instruction | |
10374 | and if the insn is setting the value in a register | |
10375 | and if the register being set is the register holding the address of the argument | |
10376 | and if the address is computing by an addition | |
10377 | that involves adding to a register | |
10378 | which is the frame pointer | |
10379 | a constant integer | |
10380 | ||
10381 | then... */ | |
10382 | ||
10383 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
10384 | { | |
10385 | if ( GET_CODE (insn) == INSN | |
10386 | && GET_CODE (PATTERN (insn)) == SET | |
10387 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
10388 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
10389 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 10390 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
10391 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
10392 | ) | |
10393 | { | |
10394 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
10395 | ||
10396 | break; | |
10397 | } | |
10398 | } | |
10399 | ||
10400 | if (value == 0) | |
10401 | { | |
10402 | debug_rtx (addr); | |
c725bd79 | 10403 | warning ("unable to compute real location of stacked parameter"); |
d5b7b3ae RE |
10404 | value = 8; /* XXX magic hack */ |
10405 | } | |
10406 | ||
10407 | return value; | |
10408 | } | |
d5b7b3ae | 10409 | \f |
5a9335ef NC |
10410 | #define def_mbuiltin(MASK, NAME, TYPE, CODE) \ |
10411 | do \ | |
10412 | { \ | |
10413 | if ((MASK) & insn_flags) \ | |
10414 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \ | |
10415 | } \ | |
10416 | while (0) | |
10417 | ||
10418 | struct builtin_description | |
10419 | { | |
10420 | const unsigned int mask; | |
10421 | const enum insn_code icode; | |
10422 | const char * const name; | |
10423 | const enum arm_builtins code; | |
10424 | const enum rtx_code comparison; | |
10425 | const unsigned int flag; | |
10426 | }; | |
10427 | ||
10428 | static const struct builtin_description bdesc_2arg[] = | |
10429 | { | |
10430 | #define IWMMXT_BUILTIN(code, string, builtin) \ | |
10431 | { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ | |
10432 | ARM_BUILTIN_##builtin, 0, 0 }, | |
10433 | ||
10434 | IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) | |
10435 | IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) | |
10436 | IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) | |
10437 | IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) | |
10438 | IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) | |
10439 | IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) | |
10440 | IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) | |
10441 | IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) | |
10442 | IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) | |
10443 | IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) | |
10444 | IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) | |
10445 | IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) | |
10446 | IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) | |
10447 | IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) | |
10448 | IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) | |
10449 | IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) | |
10450 | IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) | |
10451 | IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) | |
10452 | IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) | |
10453 | IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsh", WMULSH) | |
10454 | IWMMXT_BUILTIN (umulv4hi3_highpart, "wmuluh", WMULUH) | |
10455 | IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) | |
10456 | IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) | |
10457 | IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) | |
10458 | IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) | |
10459 | IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) | |
10460 | IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) | |
10461 | IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) | |
10462 | IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) | |
10463 | IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) | |
10464 | IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) | |
10465 | IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) | |
10466 | IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) | |
10467 | IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) | |
10468 | IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) | |
10469 | IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) | |
10470 | IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) | |
10471 | IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) | |
10472 | IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) | |
10473 | IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) | |
10474 | IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) | |
10475 | IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) | |
10476 | IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) | |
10477 | IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) | |
10478 | IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) | |
10479 | IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) | |
10480 | IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) | |
10481 | IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) | |
10482 | IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) | |
10483 | IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) | |
10484 | IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) | |
10485 | IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) | |
10486 | IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) | |
10487 | IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) | |
10488 | IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) | |
10489 | IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) | |
10490 | IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) | |
10491 | IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) | |
10492 | ||
10493 | #define IWMMXT_BUILTIN2(code, builtin) \ | |
10494 | { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 }, | |
10495 | ||
10496 | IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) | |
10497 | IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) | |
10498 | IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) | |
10499 | IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) | |
10500 | IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) | |
10501 | IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) | |
10502 | IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) | |
10503 | IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI) | |
10504 | IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) | |
10505 | IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI) | |
10506 | IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) | |
10507 | IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) | |
10508 | IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) | |
10509 | IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI) | |
10510 | IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) | |
10511 | IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI) | |
10512 | IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) | |
10513 | IWMMXT_BUILTIN2 (lshrdi3, WSRLDI) | |
10514 | IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) | |
10515 | IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI) | |
10516 | IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) | |
10517 | IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI) | |
10518 | IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) | |
10519 | IWMMXT_BUILTIN2 (ashrdi3, WSRADI) | |
10520 | IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) | |
10521 | IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) | |
10522 | IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) | |
10523 | IWMMXT_BUILTIN2 (rorv2si3, WRORWI) | |
10524 | IWMMXT_BUILTIN2 (rordi3_di, WRORD) | |
10525 | IWMMXT_BUILTIN2 (rordi3, WRORDI) | |
10526 | IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) | |
10527 | IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) | |
10528 | }; | |
10529 | ||
10530 | static const struct builtin_description bdesc_1arg[] = | |
10531 | { | |
10532 | IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) | |
10533 | IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) | |
10534 | IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) | |
10535 | IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) | |
10536 | IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) | |
10537 | IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) | |
10538 | IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) | |
10539 | IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) | |
10540 | IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) | |
10541 | IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) | |
10542 | IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) | |
10543 | IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) | |
10544 | IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) | |
10545 | IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) | |
10546 | IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) | |
10547 | IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) | |
10548 | IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) | |
10549 | IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) | |
10550 | }; | |
10551 | ||
10552 | /* Set up all the iWMMXt builtins. This is | |
10553 | not called if TARGET_IWMMXT is zero. */ | |
10554 | ||
10555 | static void | |
10556 | arm_init_iwmmxt_builtins (void) | |
10557 | { | |
10558 | const struct builtin_description * d; | |
10559 | size_t i; | |
10560 | tree endlink = void_list_node; | |
10561 | ||
10562 | tree int_ftype_int | |
10563 | = build_function_type (integer_type_node, | |
10564 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
10565 | tree v8qi_ftype_v8qi_v8qi_int | |
10566 | = build_function_type (V8QI_type_node, | |
10567 | tree_cons (NULL_TREE, V8QI_type_node, | |
10568 | tree_cons (NULL_TREE, V8QI_type_node, | |
10569 | tree_cons (NULL_TREE, | |
10570 | integer_type_node, | |
10571 | endlink)))); | |
10572 | tree v4hi_ftype_v4hi_int | |
10573 | = build_function_type (V4HI_type_node, | |
10574 | tree_cons (NULL_TREE, V4HI_type_node, | |
10575 | tree_cons (NULL_TREE, integer_type_node, | |
10576 | endlink))); | |
10577 | tree v2si_ftype_v2si_int | |
10578 | = build_function_type (V2SI_type_node, | |
10579 | tree_cons (NULL_TREE, V2SI_type_node, | |
10580 | tree_cons (NULL_TREE, integer_type_node, | |
10581 | endlink))); | |
10582 | tree v2si_ftype_di_di | |
10583 | = build_function_type (V2SI_type_node, | |
10584 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
10585 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
10586 | endlink))); | |
10587 | tree di_ftype_di_int | |
10588 | = build_function_type (long_long_integer_type_node, | |
10589 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
10590 | tree_cons (NULL_TREE, integer_type_node, | |
10591 | endlink))); | |
10592 | tree di_ftype_di_int_int | |
10593 | = build_function_type (long_long_integer_type_node, | |
10594 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
10595 | tree_cons (NULL_TREE, integer_type_node, | |
10596 | tree_cons (NULL_TREE, | |
10597 | integer_type_node, | |
10598 | endlink)))); | |
10599 | tree int_ftype_v8qi | |
10600 | = build_function_type (integer_type_node, | |
10601 | tree_cons (NULL_TREE, V8QI_type_node, | |
10602 | endlink)); | |
10603 | tree int_ftype_v4hi | |
10604 | = build_function_type (integer_type_node, | |
10605 | tree_cons (NULL_TREE, V4HI_type_node, | |
10606 | endlink)); | |
10607 | tree int_ftype_v2si | |
10608 | = build_function_type (integer_type_node, | |
10609 | tree_cons (NULL_TREE, V2SI_type_node, | |
10610 | endlink)); | |
10611 | tree int_ftype_v8qi_int | |
10612 | = build_function_type (integer_type_node, | |
10613 | tree_cons (NULL_TREE, V8QI_type_node, | |
10614 | tree_cons (NULL_TREE, integer_type_node, | |
10615 | endlink))); | |
10616 | tree int_ftype_v4hi_int | |
10617 | = build_function_type (integer_type_node, | |
10618 | tree_cons (NULL_TREE, V4HI_type_node, | |
10619 | tree_cons (NULL_TREE, integer_type_node, | |
10620 | endlink))); | |
10621 | tree int_ftype_v2si_int | |
10622 | = build_function_type (integer_type_node, | |
10623 | tree_cons (NULL_TREE, V2SI_type_node, | |
10624 | tree_cons (NULL_TREE, integer_type_node, | |
10625 | endlink))); | |
10626 | tree v8qi_ftype_v8qi_int_int | |
10627 | = build_function_type (V8QI_type_node, | |
10628 | tree_cons (NULL_TREE, V8QI_type_node, | |
10629 | tree_cons (NULL_TREE, integer_type_node, | |
10630 | tree_cons (NULL_TREE, | |
10631 | integer_type_node, | |
10632 | endlink)))); | |
10633 | tree v4hi_ftype_v4hi_int_int | |
10634 | = build_function_type (V4HI_type_node, | |
10635 | tree_cons (NULL_TREE, V4HI_type_node, | |
10636 | tree_cons (NULL_TREE, integer_type_node, | |
10637 | tree_cons (NULL_TREE, | |
10638 | integer_type_node, | |
10639 | endlink)))); | |
10640 | tree v2si_ftype_v2si_int_int | |
10641 | = build_function_type (V2SI_type_node, | |
10642 | tree_cons (NULL_TREE, V2SI_type_node, | |
10643 | tree_cons (NULL_TREE, integer_type_node, | |
10644 | tree_cons (NULL_TREE, | |
10645 | integer_type_node, | |
10646 | endlink)))); | |
10647 | /* Miscellaneous. */ | |
10648 | tree v8qi_ftype_v4hi_v4hi | |
10649 | = build_function_type (V8QI_type_node, | |
10650 | tree_cons (NULL_TREE, V4HI_type_node, | |
10651 | tree_cons (NULL_TREE, V4HI_type_node, | |
10652 | endlink))); | |
10653 | tree v4hi_ftype_v2si_v2si | |
10654 | = build_function_type (V4HI_type_node, | |
10655 | tree_cons (NULL_TREE, V2SI_type_node, | |
10656 | tree_cons (NULL_TREE, V2SI_type_node, | |
10657 | endlink))); | |
10658 | tree v2si_ftype_v4hi_v4hi | |
10659 | = build_function_type (V2SI_type_node, | |
10660 | tree_cons (NULL_TREE, V4HI_type_node, | |
10661 | tree_cons (NULL_TREE, V4HI_type_node, | |
10662 | endlink))); | |
10663 | tree v2si_ftype_v8qi_v8qi | |
10664 | = build_function_type (V2SI_type_node, | |
10665 | tree_cons (NULL_TREE, V8QI_type_node, | |
10666 | tree_cons (NULL_TREE, V8QI_type_node, | |
10667 | endlink))); | |
10668 | tree v4hi_ftype_v4hi_di | |
10669 | = build_function_type (V4HI_type_node, | |
10670 | tree_cons (NULL_TREE, V4HI_type_node, | |
10671 | tree_cons (NULL_TREE, | |
10672 | long_long_integer_type_node, | |
10673 | endlink))); | |
10674 | tree v2si_ftype_v2si_di | |
10675 | = build_function_type (V2SI_type_node, | |
10676 | tree_cons (NULL_TREE, V2SI_type_node, | |
10677 | tree_cons (NULL_TREE, | |
10678 | long_long_integer_type_node, | |
10679 | endlink))); | |
10680 | tree void_ftype_int_int | |
10681 | = build_function_type (void_type_node, | |
10682 | tree_cons (NULL_TREE, integer_type_node, | |
10683 | tree_cons (NULL_TREE, integer_type_node, | |
10684 | endlink))); | |
10685 | tree di_ftype_void | |
10686 | = build_function_type (long_long_unsigned_type_node, endlink); | |
10687 | tree di_ftype_v8qi | |
10688 | = build_function_type (long_long_integer_type_node, | |
10689 | tree_cons (NULL_TREE, V8QI_type_node, | |
10690 | endlink)); | |
10691 | tree di_ftype_v4hi | |
10692 | = build_function_type (long_long_integer_type_node, | |
10693 | tree_cons (NULL_TREE, V4HI_type_node, | |
10694 | endlink)); | |
10695 | tree di_ftype_v2si | |
10696 | = build_function_type (long_long_integer_type_node, | |
10697 | tree_cons (NULL_TREE, V2SI_type_node, | |
10698 | endlink)); | |
10699 | tree v2si_ftype_v4hi | |
10700 | = build_function_type (V2SI_type_node, | |
10701 | tree_cons (NULL_TREE, V4HI_type_node, | |
10702 | endlink)); | |
10703 | tree v4hi_ftype_v8qi | |
10704 | = build_function_type (V4HI_type_node, | |
10705 | tree_cons (NULL_TREE, V8QI_type_node, | |
10706 | endlink)); | |
10707 | ||
10708 | tree di_ftype_di_v4hi_v4hi | |
10709 | = build_function_type (long_long_unsigned_type_node, | |
10710 | tree_cons (NULL_TREE, | |
10711 | long_long_unsigned_type_node, | |
10712 | tree_cons (NULL_TREE, V4HI_type_node, | |
10713 | tree_cons (NULL_TREE, | |
10714 | V4HI_type_node, | |
10715 | endlink)))); | |
10716 | ||
10717 | tree di_ftype_v4hi_v4hi | |
10718 | = build_function_type (long_long_unsigned_type_node, | |
10719 | tree_cons (NULL_TREE, V4HI_type_node, | |
10720 | tree_cons (NULL_TREE, V4HI_type_node, | |
10721 | endlink))); | |
10722 | ||
10723 | /* Normal vector binops. */ | |
10724 | tree v8qi_ftype_v8qi_v8qi | |
10725 | = build_function_type (V8QI_type_node, | |
10726 | tree_cons (NULL_TREE, V8QI_type_node, | |
10727 | tree_cons (NULL_TREE, V8QI_type_node, | |
10728 | endlink))); | |
10729 | tree v4hi_ftype_v4hi_v4hi | |
10730 | = build_function_type (V4HI_type_node, | |
10731 | tree_cons (NULL_TREE, V4HI_type_node, | |
10732 | tree_cons (NULL_TREE, V4HI_type_node, | |
10733 | endlink))); | |
10734 | tree v2si_ftype_v2si_v2si | |
10735 | = build_function_type (V2SI_type_node, | |
10736 | tree_cons (NULL_TREE, V2SI_type_node, | |
10737 | tree_cons (NULL_TREE, V2SI_type_node, | |
10738 | endlink))); | |
10739 | tree di_ftype_di_di | |
10740 | = build_function_type (long_long_unsigned_type_node, | |
10741 | tree_cons (NULL_TREE, long_long_unsigned_type_node, | |
10742 | tree_cons (NULL_TREE, | |
10743 | long_long_unsigned_type_node, | |
10744 | endlink))); | |
10745 | ||
10746 | /* Add all builtins that are more or less simple operations on two | |
10747 | operands. */ | |
10748 | for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
10749 | { | |
10750 | /* Use one of the operands; the target can have a different mode for | |
10751 | mask-generating compares. */ | |
10752 | enum machine_mode mode; | |
10753 | tree type; | |
10754 | ||
10755 | if (d->name == 0) | |
10756 | continue; | |
10757 | ||
10758 | mode = insn_data[d->icode].operand[1].mode; | |
10759 | ||
10760 | switch (mode) | |
10761 | { | |
10762 | case V8QImode: | |
10763 | type = v8qi_ftype_v8qi_v8qi; | |
10764 | break; | |
10765 | case V4HImode: | |
10766 | type = v4hi_ftype_v4hi_v4hi; | |
10767 | break; | |
10768 | case V2SImode: | |
10769 | type = v2si_ftype_v2si_v2si; | |
10770 | break; | |
10771 | case DImode: | |
10772 | type = di_ftype_di_di; | |
10773 | break; | |
10774 | ||
10775 | default: | |
10776 | abort (); | |
10777 | } | |
10778 | ||
10779 | def_mbuiltin (d->mask, d->name, type, d->code); | |
10780 | } | |
10781 | ||
10782 | /* Add the remaining MMX insns with somewhat more complicated types. */ | |
10783 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); | |
10784 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); | |
10785 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); | |
10786 | ||
10787 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); | |
10788 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); | |
10789 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); | |
10790 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); | |
10791 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); | |
10792 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); | |
10793 | ||
10794 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); | |
10795 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); | |
10796 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); | |
10797 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); | |
10798 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); | |
10799 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); | |
10800 | ||
10801 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); | |
10802 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); | |
10803 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); | |
10804 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); | |
10805 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); | |
10806 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); | |
10807 | ||
10808 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); | |
10809 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); | |
10810 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); | |
10811 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); | |
10812 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); | |
10813 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); | |
10814 | ||
10815 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); | |
10816 | ||
10817 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); | |
10818 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); | |
10819 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); | |
10820 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); | |
10821 | ||
10822 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); | |
10823 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); | |
10824 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); | |
10825 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); | |
10826 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); | |
10827 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); | |
10828 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); | |
10829 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); | |
10830 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); | |
10831 | ||
10832 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); | |
10833 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); | |
10834 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); | |
10835 | ||
10836 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); | |
10837 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); | |
10838 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); | |
10839 | ||
10840 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); | |
10841 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); | |
10842 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); | |
10843 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); | |
10844 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); | |
10845 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); | |
10846 | ||
10847 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); | |
10848 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); | |
10849 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); | |
10850 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); | |
10851 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); | |
10852 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); | |
10853 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); | |
10854 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); | |
10855 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); | |
10856 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); | |
10857 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); | |
10858 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); | |
10859 | ||
10860 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); | |
10861 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); | |
10862 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); | |
10863 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); | |
10864 | ||
10865 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); | |
10866 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); | |
10867 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); | |
10868 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); | |
10869 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); | |
10870 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); | |
10871 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); | |
10872 | } | |
10873 | ||
10874 | static void | |
10875 | arm_init_builtins (void) | |
10876 | { | |
10877 | if (TARGET_REALLY_IWMMXT) | |
10878 | arm_init_iwmmxt_builtins (); | |
10879 | } | |
10880 | ||
10881 | /* Errors in the source file can cause expand_expr to return const0_rtx | |
10882 | where we expect a vector. To avoid crashing, use one of the vector | |
10883 | clear instructions. */ | |
10884 | ||
10885 | static rtx | |
10886 | safe_vector_operand (rtx x, enum machine_mode mode) | |
10887 | { | |
10888 | if (x != const0_rtx) | |
10889 | return x; | |
10890 | x = gen_reg_rtx (mode); | |
10891 | ||
10892 | emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x | |
10893 | : gen_rtx_SUBREG (DImode, x, 0))); | |
10894 | return x; | |
10895 | } | |
10896 | ||
10897 | /* Subroutine of arm_expand_builtin to take care of binop insns. */ | |
10898 | ||
10899 | static rtx | |
10900 | arm_expand_binop_builtin (enum insn_code icode, | |
10901 | tree arglist, rtx target) | |
10902 | { | |
10903 | rtx pat; | |
10904 | tree arg0 = TREE_VALUE (arglist); | |
10905 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
10906 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
10907 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
10908 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
10909 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
10910 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
10911 | ||
10912 | if (VECTOR_MODE_P (mode0)) | |
10913 | op0 = safe_vector_operand (op0, mode0); | |
10914 | if (VECTOR_MODE_P (mode1)) | |
10915 | op1 = safe_vector_operand (op1, mode1); | |
10916 | ||
10917 | if (! target | |
10918 | || GET_MODE (target) != tmode | |
10919 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
10920 | target = gen_reg_rtx (tmode); | |
10921 | ||
10922 | /* In case the insn wants input operands in modes different from | |
10923 | the result, abort. */ | |
10924 | if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1) | |
10925 | abort (); | |
10926 | ||
10927 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
10928 | op0 = copy_to_mode_reg (mode0, op0); | |
10929 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
10930 | op1 = copy_to_mode_reg (mode1, op1); | |
10931 | ||
10932 | pat = GEN_FCN (icode) (target, op0, op1); | |
10933 | if (! pat) | |
10934 | return 0; | |
10935 | emit_insn (pat); | |
10936 | return target; | |
10937 | } | |
10938 | ||
10939 | /* Subroutine of arm_expand_builtin to take care of unop insns. */ | |
10940 | ||
10941 | static rtx | |
10942 | arm_expand_unop_builtin (enum insn_code icode, | |
10943 | tree arglist, rtx target, int do_load) | |
10944 | { | |
10945 | rtx pat; | |
10946 | tree arg0 = TREE_VALUE (arglist); | |
10947 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
10948 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
10949 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
10950 | ||
10951 | if (! target | |
10952 | || GET_MODE (target) != tmode | |
10953 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
10954 | target = gen_reg_rtx (tmode); | |
10955 | if (do_load) | |
10956 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
10957 | else | |
10958 | { | |
10959 | if (VECTOR_MODE_P (mode0)) | |
10960 | op0 = safe_vector_operand (op0, mode0); | |
10961 | ||
10962 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
10963 | op0 = copy_to_mode_reg (mode0, op0); | |
10964 | } | |
10965 | ||
10966 | pat = GEN_FCN (icode) (target, op0); | |
10967 | if (! pat) | |
10968 | return 0; | |
10969 | emit_insn (pat); | |
10970 | return target; | |
10971 | } | |
10972 | ||
10973 | /* Expand an expression EXP that calls a built-in function, | |
10974 | with result going to TARGET if that's convenient | |
10975 | (and in mode MODE if that's convenient). | |
10976 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
10977 | IGNORE is nonzero if the value is to be ignored. */ | |
10978 | ||
10979 | static rtx | |
10980 | arm_expand_builtin (tree exp, | |
10981 | rtx target, | |
10982 | rtx subtarget ATTRIBUTE_UNUSED, | |
10983 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
10984 | int ignore ATTRIBUTE_UNUSED) | |
10985 | { | |
10986 | const struct builtin_description * d; | |
10987 | enum insn_code icode; | |
10988 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
10989 | tree arglist = TREE_OPERAND (exp, 1); | |
10990 | tree arg0; | |
10991 | tree arg1; | |
10992 | tree arg2; | |
10993 | rtx op0; | |
10994 | rtx op1; | |
10995 | rtx op2; | |
10996 | rtx pat; | |
10997 | int fcode = DECL_FUNCTION_CODE (fndecl); | |
10998 | size_t i; | |
10999 | enum machine_mode tmode; | |
11000 | enum machine_mode mode0; | |
11001 | enum machine_mode mode1; | |
11002 | enum machine_mode mode2; | |
11003 | ||
11004 | switch (fcode) | |
11005 | { | |
11006 | case ARM_BUILTIN_TEXTRMSB: | |
11007 | case ARM_BUILTIN_TEXTRMUB: | |
11008 | case ARM_BUILTIN_TEXTRMSH: | |
11009 | case ARM_BUILTIN_TEXTRMUH: | |
11010 | case ARM_BUILTIN_TEXTRMSW: | |
11011 | case ARM_BUILTIN_TEXTRMUW: | |
11012 | icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb | |
11013 | : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub | |
11014 | : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh | |
11015 | : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh | |
11016 | : CODE_FOR_iwmmxt_textrmw); | |
11017 | ||
11018 | arg0 = TREE_VALUE (arglist); | |
11019 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
11020 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
11021 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
11022 | tmode = insn_data[icode].operand[0].mode; | |
11023 | mode0 = insn_data[icode].operand[1].mode; | |
11024 | mode1 = insn_data[icode].operand[2].mode; | |
11025 | ||
11026 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
11027 | op0 = copy_to_mode_reg (mode0, op0); | |
11028 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
11029 | { | |
11030 | /* @@@ better error message */ | |
11031 | error ("selector must be an immediate"); | |
11032 | return gen_reg_rtx (tmode); | |
11033 | } | |
11034 | if (target == 0 | |
11035 | || GET_MODE (target) != tmode | |
11036 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
11037 | target = gen_reg_rtx (tmode); | |
11038 | pat = GEN_FCN (icode) (target, op0, op1); | |
11039 | if (! pat) | |
11040 | return 0; | |
11041 | emit_insn (pat); | |
11042 | return target; | |
11043 | ||
11044 | case ARM_BUILTIN_TINSRB: | |
11045 | case ARM_BUILTIN_TINSRH: | |
11046 | case ARM_BUILTIN_TINSRW: | |
11047 | icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb | |
11048 | : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh | |
11049 | : CODE_FOR_iwmmxt_tinsrw); | |
11050 | arg0 = TREE_VALUE (arglist); | |
11051 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
11052 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
11053 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
11054 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
11055 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
11056 | tmode = insn_data[icode].operand[0].mode; | |
11057 | mode0 = insn_data[icode].operand[1].mode; | |
11058 | mode1 = insn_data[icode].operand[2].mode; | |
11059 | mode2 = insn_data[icode].operand[3].mode; | |
11060 | ||
11061 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
11062 | op0 = copy_to_mode_reg (mode0, op0); | |
11063 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
11064 | op1 = copy_to_mode_reg (mode1, op1); | |
11065 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
11066 | { | |
11067 | /* @@@ better error message */ | |
11068 | error ("selector must be an immediate"); | |
11069 | return const0_rtx; | |
11070 | } | |
11071 | if (target == 0 | |
11072 | || GET_MODE (target) != tmode | |
11073 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
11074 | target = gen_reg_rtx (tmode); | |
11075 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
11076 | if (! pat) | |
11077 | return 0; | |
11078 | emit_insn (pat); | |
11079 | return target; | |
11080 | ||
11081 | case ARM_BUILTIN_SETWCX: | |
11082 | arg0 = TREE_VALUE (arglist); | |
11083 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
11084 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
11085 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
11086 | emit_insn (gen_iwmmxt_tmcr (op0, op1)); | |
11087 | return 0; | |
11088 | ||
11089 | case ARM_BUILTIN_GETWCX: | |
11090 | arg0 = TREE_VALUE (arglist); | |
11091 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
11092 | target = gen_reg_rtx (SImode); | |
11093 | emit_insn (gen_iwmmxt_tmrc (target, op0)); | |
11094 | return target; | |
11095 | ||
11096 | case ARM_BUILTIN_WSHUFH: | |
11097 | icode = CODE_FOR_iwmmxt_wshufh; | |
11098 | arg0 = TREE_VALUE (arglist); | |
11099 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
11100 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
11101 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
11102 | tmode = insn_data[icode].operand[0].mode; | |
11103 | mode1 = insn_data[icode].operand[1].mode; | |
11104 | mode2 = insn_data[icode].operand[2].mode; | |
11105 | ||
11106 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) | |
11107 | op0 = copy_to_mode_reg (mode1, op0); | |
11108 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) | |
11109 | { | |
11110 | /* @@@ better error message */ | |
11111 | error ("mask must be an immediate"); | |
11112 | return const0_rtx; | |
11113 | } | |
11114 | if (target == 0 | |
11115 | || GET_MODE (target) != tmode | |
11116 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
11117 | target = gen_reg_rtx (tmode); | |
11118 | pat = GEN_FCN (icode) (target, op0, op1); | |
11119 | if (! pat) | |
11120 | return 0; | |
11121 | emit_insn (pat); | |
11122 | return target; | |
11123 | ||
11124 | case ARM_BUILTIN_WSADB: | |
11125 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target); | |
11126 | case ARM_BUILTIN_WSADH: | |
11127 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target); | |
11128 | case ARM_BUILTIN_WSADBZ: | |
11129 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target); | |
11130 | case ARM_BUILTIN_WSADHZ: | |
11131 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target); | |
11132 | ||
11133 | /* Several three-argument builtins. */ | |
11134 | case ARM_BUILTIN_WMACS: | |
11135 | case ARM_BUILTIN_WMACU: | |
11136 | case ARM_BUILTIN_WALIGN: | |
11137 | case ARM_BUILTIN_TMIA: | |
11138 | case ARM_BUILTIN_TMIAPH: | |
11139 | case ARM_BUILTIN_TMIATT: | |
11140 | case ARM_BUILTIN_TMIATB: | |
11141 | case ARM_BUILTIN_TMIABT: | |
11142 | case ARM_BUILTIN_TMIABB: | |
11143 | icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs | |
11144 | : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu | |
11145 | : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia | |
11146 | : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph | |
11147 | : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb | |
11148 | : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt | |
11149 | : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb | |
11150 | : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt | |
11151 | : CODE_FOR_iwmmxt_walign); | |
11152 | arg0 = TREE_VALUE (arglist); | |
11153 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
11154 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
11155 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
11156 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
11157 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
11158 | tmode = insn_data[icode].operand[0].mode; | |
11159 | mode0 = insn_data[icode].operand[1].mode; | |
11160 | mode1 = insn_data[icode].operand[2].mode; | |
11161 | mode2 = insn_data[icode].operand[3].mode; | |
11162 | ||
11163 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
11164 | op0 = copy_to_mode_reg (mode0, op0); | |
11165 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
11166 | op1 = copy_to_mode_reg (mode1, op1); | |
11167 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
11168 | op2 = copy_to_mode_reg (mode2, op2); | |
11169 | if (target == 0 | |
11170 | || GET_MODE (target) != tmode | |
11171 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
11172 | target = gen_reg_rtx (tmode); | |
11173 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
11174 | if (! pat) | |
11175 | return 0; | |
11176 | emit_insn (pat); | |
11177 | return target; | |
11178 | ||
11179 | case ARM_BUILTIN_WZERO: | |
11180 | target = gen_reg_rtx (DImode); | |
11181 | emit_insn (gen_iwmmxt_clrdi (target)); | |
11182 | return target; | |
11183 | ||
11184 | default: | |
11185 | break; | |
11186 | } | |
11187 | ||
11188 | for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
11189 | if (d->code == (const enum arm_builtins) fcode) | |
11190 | return arm_expand_binop_builtin (d->icode, arglist, target); | |
11191 | ||
11192 | for (i = 0, d = bdesc_1arg; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++) | |
11193 | if (d->code == (const enum arm_builtins) fcode) | |
11194 | return arm_expand_unop_builtin (d->icode, arglist, target, 0); | |
11195 | ||
11196 | /* @@@ Should really do something sensible here. */ | |
11197 | return NULL_RTX; | |
11198 | } | |
11199 | \f | |
d5b7b3ae RE |
11200 | /* Recursively search through all of the blocks in a function |
11201 | checking to see if any of the variables created in that | |
11202 | function match the RTX called 'orig'. If they do then | |
11203 | replace them with the RTX called 'new'. */ | |
d5b7b3ae | 11204 | static void |
e32bac5b | 11205 | replace_symbols_in_block (tree block, rtx orig, rtx new) |
d5b7b3ae RE |
11206 | { |
11207 | for (; block; block = BLOCK_CHAIN (block)) | |
11208 | { | |
11209 | tree sym; | |
11210 | ||
5895f793 | 11211 | if (!TREE_USED (block)) |
d5b7b3ae RE |
11212 | continue; |
11213 | ||
11214 | for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym)) | |
11215 | { | |
11216 | if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL) | |
11217 | || DECL_IGNORED_P (sym) | |
11218 | || TREE_CODE (sym) != VAR_DECL | |
11219 | || DECL_EXTERNAL (sym) | |
5895f793 | 11220 | || !rtx_equal_p (DECL_RTL (sym), orig) |
d5b7b3ae RE |
11221 | ) |
11222 | continue; | |
11223 | ||
7b8b8ade | 11224 | SET_DECL_RTL (sym, new); |
d5b7b3ae RE |
11225 | } |
11226 | ||
11227 | replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new); | |
11228 | } | |
11229 | } | |
11230 | ||
1d6e90ac NC |
11231 | /* Return the number (counting from 0) of |
11232 | the least significant set bit in MASK. */ | |
11233 | ||
e32bac5b RE |
11234 | inline static int |
11235 | number_of_first_bit_set (int mask) | |
d5b7b3ae RE |
11236 | { |
11237 | int bit; | |
11238 | ||
11239 | for (bit = 0; | |
11240 | (mask & (1 << bit)) == 0; | |
5895f793 | 11241 | ++bit) |
d5b7b3ae RE |
11242 | continue; |
11243 | ||
11244 | return bit; | |
11245 | } | |
11246 | ||
11247 | /* Generate code to return from a thumb function. | |
11248 | If 'reg_containing_return_addr' is -1, then the return address is | |
11249 | actually on the stack, at the stack pointer. */ | |
11250 | static void | |
e32bac5b | 11251 | thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) |
d5b7b3ae RE |
11252 | { |
11253 | unsigned regs_available_for_popping; | |
11254 | unsigned regs_to_pop; | |
11255 | int pops_needed; | |
11256 | unsigned available; | |
11257 | unsigned required; | |
11258 | int mode; | |
11259 | int size; | |
11260 | int restore_a4 = FALSE; | |
11261 | ||
11262 | /* Compute the registers we need to pop. */ | |
11263 | regs_to_pop = 0; | |
11264 | pops_needed = 0; | |
11265 | ||
11266 | /* There is an assumption here, that if eh_ofs is not NULL, the | |
11267 | normal return address will have been pushed. */ | |
11268 | if (reg_containing_return_addr == -1 || eh_ofs) | |
11269 | { | |
11270 | /* When we are generating a return for __builtin_eh_return, | |
11271 | reg_containing_return_addr must specify the return regno. */ | |
11272 | if (eh_ofs && reg_containing_return_addr == -1) | |
11273 | abort (); | |
11274 | ||
11275 | regs_to_pop |= 1 << LR_REGNUM; | |
5895f793 | 11276 | ++pops_needed; |
d5b7b3ae RE |
11277 | } |
11278 | ||
11279 | if (TARGET_BACKTRACE) | |
11280 | { | |
11281 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
11282 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
11283 | pops_needed += 2; | |
11284 | } | |
11285 | ||
11286 | /* If there is nothing to pop then just emit the BX instruction and | |
11287 | return. */ | |
11288 | if (pops_needed == 0) | |
11289 | { | |
11290 | if (eh_ofs) | |
11291 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
11292 | ||
11293 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
11294 | return; | |
11295 | } | |
11296 | /* Otherwise if we are not supporting interworking and we have not created | |
11297 | a backtrace structure and the function was not entered in ARM mode then | |
11298 | just pop the return address straight into the PC. */ | |
5895f793 RE |
11299 | else if (!TARGET_INTERWORK |
11300 | && !TARGET_BACKTRACE | |
11301 | && !is_called_in_ARM_mode (current_function_decl)) | |
d5b7b3ae RE |
11302 | { |
11303 | if (eh_ofs) | |
11304 | { | |
11305 | asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM); | |
11306 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
11307 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
11308 | } | |
11309 | else | |
11310 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); | |
11311 | ||
11312 | return; | |
11313 | } | |
11314 | ||
11315 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
11316 | regs_available_for_popping = 0; | |
11317 | ||
11318 | /* If returning via __builtin_eh_return, the bottom three registers | |
11319 | all contain information needed for the return. */ | |
11320 | if (eh_ofs) | |
11321 | size = 12; | |
11322 | else | |
11323 | { | |
11324 | #ifdef RTX_CODE | |
11325 | /* If we can deduce the registers used from the function's | |
11326 | return value. This is more reliable that examining | |
11327 | regs_ever_live[] because that will be set if the register is | |
11328 | ever used in the function, not just if the register is used | |
11329 | to hold a return value. */ | |
11330 | ||
11331 | if (current_function_return_rtx != 0) | |
11332 | mode = GET_MODE (current_function_return_rtx); | |
11333 | else | |
11334 | #endif | |
11335 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
11336 | ||
11337 | size = GET_MODE_SIZE (mode); | |
11338 | ||
11339 | if (size == 0) | |
11340 | { | |
11341 | /* In a void function we can use any argument register. | |
11342 | In a function that returns a structure on the stack | |
11343 | we can use the second and third argument registers. */ | |
11344 | if (mode == VOIDmode) | |
11345 | regs_available_for_popping = | |
11346 | (1 << ARG_REGISTER (1)) | |
11347 | | (1 << ARG_REGISTER (2)) | |
11348 | | (1 << ARG_REGISTER (3)); | |
11349 | else | |
11350 | regs_available_for_popping = | |
11351 | (1 << ARG_REGISTER (2)) | |
11352 | | (1 << ARG_REGISTER (3)); | |
11353 | } | |
11354 | else if (size <= 4) | |
11355 | regs_available_for_popping = | |
11356 | (1 << ARG_REGISTER (2)) | |
11357 | | (1 << ARG_REGISTER (3)); | |
11358 | else if (size <= 8) | |
11359 | regs_available_for_popping = | |
11360 | (1 << ARG_REGISTER (3)); | |
11361 | } | |
11362 | ||
11363 | /* Match registers to be popped with registers into which we pop them. */ | |
11364 | for (available = regs_available_for_popping, | |
11365 | required = regs_to_pop; | |
11366 | required != 0 && available != 0; | |
11367 | available &= ~(available & - available), | |
11368 | required &= ~(required & - required)) | |
11369 | -- pops_needed; | |
11370 | ||
11371 | /* If we have any popping registers left over, remove them. */ | |
11372 | if (available > 0) | |
5895f793 | 11373 | regs_available_for_popping &= ~available; |
d5b7b3ae RE |
11374 | |
11375 | /* Otherwise if we need another popping register we can use | |
11376 | the fourth argument register. */ | |
11377 | else if (pops_needed) | |
11378 | { | |
11379 | /* If we have not found any free argument registers and | |
11380 | reg a4 contains the return address, we must move it. */ | |
11381 | if (regs_available_for_popping == 0 | |
11382 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
11383 | { | |
11384 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
11385 | reg_containing_return_addr = LR_REGNUM; | |
11386 | } | |
11387 | else if (size > 12) | |
11388 | { | |
11389 | /* Register a4 is being used to hold part of the return value, | |
11390 | but we have dire need of a free, low register. */ | |
11391 | restore_a4 = TRUE; | |
11392 | ||
11393 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); | |
11394 | } | |
11395 | ||
11396 | if (reg_containing_return_addr != LAST_ARG_REGNUM) | |
11397 | { | |
11398 | /* The fourth argument register is available. */ | |
11399 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
11400 | ||
5895f793 | 11401 | --pops_needed; |
d5b7b3ae RE |
11402 | } |
11403 | } | |
11404 | ||
11405 | /* Pop as many registers as we can. */ | |
11406 | thumb_pushpop (f, regs_available_for_popping, FALSE); | |
11407 | ||
11408 | /* Process the registers we popped. */ | |
11409 | if (reg_containing_return_addr == -1) | |
11410 | { | |
11411 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 11412 | regs_to_pop &= ~(1 << LR_REGNUM); |
d5b7b3ae RE |
11413 | |
11414 | reg_containing_return_addr = | |
11415 | number_of_first_bit_set (regs_available_for_popping); | |
11416 | ||
11417 | /* Remove this register for the mask of available registers, so that | |
6bc82793 | 11418 | the return address will not be corrupted by further pops. */ |
5895f793 | 11419 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
11420 | } |
11421 | ||
11422 | /* If we popped other registers then handle them here. */ | |
11423 | if (regs_available_for_popping) | |
11424 | { | |
11425 | int frame_pointer; | |
11426 | ||
11427 | /* Work out which register currently contains the frame pointer. */ | |
11428 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
11429 | ||
11430 | /* Move it into the correct place. */ | |
11431 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
11432 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
11433 | ||
11434 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
11435 | regs_available_for_popping &= ~(1 << frame_pointer); |
11436 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
d5b7b3ae RE |
11437 | |
11438 | if (regs_available_for_popping) | |
11439 | { | |
11440 | int stack_pointer; | |
11441 | ||
11442 | /* We popped the stack pointer as well, | |
11443 | find the register that contains it. */ | |
11444 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
11445 | ||
11446 | /* Move it into the stack register. */ | |
11447 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
11448 | ||
11449 | /* At this point we have popped all necessary registers, so | |
11450 | do not worry about restoring regs_available_for_popping | |
11451 | to its correct value: | |
11452 | ||
11453 | assert (pops_needed == 0) | |
11454 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
11455 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
11456 | } | |
11457 | else | |
11458 | { | |
11459 | /* Since we have just move the popped value into the frame | |
11460 | pointer, the popping register is available for reuse, and | |
11461 | we know that we still have the stack pointer left to pop. */ | |
11462 | regs_available_for_popping |= (1 << frame_pointer); | |
11463 | } | |
11464 | } | |
11465 | ||
11466 | /* If we still have registers left on the stack, but we no longer have | |
11467 | any registers into which we can pop them, then we must move the return | |
11468 | address into the link register and make available the register that | |
11469 | contained it. */ | |
11470 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
11471 | { | |
11472 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
11473 | ||
11474 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, | |
11475 | reg_containing_return_addr); | |
11476 | ||
11477 | reg_containing_return_addr = LR_REGNUM; | |
11478 | } | |
11479 | ||
11480 | /* If we have registers left on the stack then pop some more. | |
11481 | We know that at most we will want to pop FP and SP. */ | |
11482 | if (pops_needed > 0) | |
11483 | { | |
11484 | int popped_into; | |
11485 | int move_to; | |
11486 | ||
11487 | thumb_pushpop (f, regs_available_for_popping, FALSE); | |
11488 | ||
11489 | /* We have popped either FP or SP. | |
11490 | Move whichever one it is into the correct register. */ | |
11491 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
11492 | move_to = number_of_first_bit_set (regs_to_pop); | |
11493 | ||
11494 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
11495 | ||
5895f793 | 11496 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 11497 | |
5895f793 | 11498 | --pops_needed; |
d5b7b3ae RE |
11499 | } |
11500 | ||
11501 | /* If we still have not popped everything then we must have only | |
11502 | had one register available to us and we are now popping the SP. */ | |
11503 | if (pops_needed > 0) | |
11504 | { | |
11505 | int popped_into; | |
11506 | ||
11507 | thumb_pushpop (f, regs_available_for_popping, FALSE); | |
11508 | ||
11509 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
11510 | ||
11511 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
11512 | /* | |
11513 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
11514 | assert (pops_needed == 1) | |
11515 | */ | |
11516 | } | |
11517 | ||
11518 | /* If necessary restore the a4 register. */ | |
11519 | if (restore_a4) | |
11520 | { | |
11521 | if (reg_containing_return_addr != LR_REGNUM) | |
11522 | { | |
11523 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
11524 | reg_containing_return_addr = LR_REGNUM; | |
11525 | } | |
11526 | ||
11527 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); | |
11528 | } | |
11529 | ||
11530 | if (eh_ofs) | |
11531 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
11532 | ||
11533 | /* Return to caller. */ | |
11534 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
11535 | } | |
11536 | ||
11537 | /* Emit code to push or pop registers to or from the stack. */ | |
11538 | static void | |
e32bac5b | 11539 | thumb_pushpop (FILE *f, int mask, int push) |
d5b7b3ae RE |
11540 | { |
11541 | int regno; | |
11542 | int lo_mask = mask & 0xFF; | |
11543 | ||
5895f793 | 11544 | if (lo_mask == 0 && !push && (mask & (1 << 15))) |
d5b7b3ae RE |
11545 | { |
11546 | /* Special case. Do not generate a POP PC statement here, do it in | |
11547 | thumb_exit() */ | |
11548 | thumb_exit (f, -1, NULL_RTX); | |
11549 | return; | |
11550 | } | |
11551 | ||
11552 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); | |
11553 | ||
11554 | /* Look at the low registers first. */ | |
5895f793 | 11555 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) |
d5b7b3ae RE |
11556 | { |
11557 | if (lo_mask & 1) | |
11558 | { | |
11559 | asm_fprintf (f, "%r", regno); | |
11560 | ||
11561 | if ((lo_mask & ~1) != 0) | |
11562 | fprintf (f, ", "); | |
11563 | } | |
11564 | } | |
11565 | ||
11566 | if (push && (mask & (1 << LR_REGNUM))) | |
11567 | { | |
11568 | /* Catch pushing the LR. */ | |
11569 | if (mask & 0xFF) | |
11570 | fprintf (f, ", "); | |
11571 | ||
11572 | asm_fprintf (f, "%r", LR_REGNUM); | |
11573 | } | |
11574 | else if (!push && (mask & (1 << PC_REGNUM))) | |
11575 | { | |
11576 | /* Catch popping the PC. */ | |
11577 | if (TARGET_INTERWORK || TARGET_BACKTRACE) | |
11578 | { | |
11579 | /* The PC is never poped directly, instead | |
11580 | it is popped into r3 and then BX is used. */ | |
11581 | fprintf (f, "}\n"); | |
11582 | ||
11583 | thumb_exit (f, -1, NULL_RTX); | |
11584 | ||
11585 | return; | |
11586 | } | |
11587 | else | |
11588 | { | |
11589 | if (mask & 0xFF) | |
11590 | fprintf (f, ", "); | |
11591 | ||
11592 | asm_fprintf (f, "%r", PC_REGNUM); | |
11593 | } | |
11594 | } | |
11595 | ||
11596 | fprintf (f, "}\n"); | |
11597 | } | |
11598 | \f | |
11599 | void | |
e32bac5b | 11600 | thumb_final_prescan_insn (rtx insn) |
d5b7b3ae | 11601 | { |
d5b7b3ae | 11602 | if (flag_print_asm_name) |
9d98a694 AO |
11603 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
11604 | INSN_ADDRESSES (INSN_UID (insn))); | |
d5b7b3ae RE |
11605 | } |
11606 | ||
11607 | int | |
e32bac5b | 11608 | thumb_shiftable_const (unsigned HOST_WIDE_INT val) |
d5b7b3ae RE |
11609 | { |
11610 | unsigned HOST_WIDE_INT mask = 0xff; | |
11611 | int i; | |
11612 | ||
11613 | if (val == 0) /* XXX */ | |
11614 | return 0; | |
11615 | ||
11616 | for (i = 0; i < 25; i++) | |
11617 | if ((val & (mask << i)) == val) | |
11618 | return 1; | |
11619 | ||
11620 | return 0; | |
11621 | } | |
11622 | ||
825dda42 | 11623 | /* Returns nonzero if the current function contains, |
d5b7b3ae RE |
11624 | or might contain a far jump. */ |
11625 | int | |
e32bac5b | 11626 | thumb_far_jump_used_p (int in_prologue) |
d5b7b3ae RE |
11627 | { |
11628 | rtx insn; | |
11629 | ||
11630 | /* This test is only important for leaf functions. */ | |
5895f793 | 11631 | /* assert (!leaf_function_p ()); */ |
d5b7b3ae RE |
11632 | |
11633 | /* If we have already decided that far jumps may be used, | |
11634 | do not bother checking again, and always return true even if | |
11635 | it turns out that they are not being used. Once we have made | |
11636 | the decision that far jumps are present (and that hence the link | |
11637 | register will be pushed onto the stack) we cannot go back on it. */ | |
11638 | if (cfun->machine->far_jump_used) | |
11639 | return 1; | |
11640 | ||
11641 | /* If this function is not being called from the prologue/epilogue | |
11642 | generation code then it must be being called from the | |
11643 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5895f793 | 11644 | if (!in_prologue) |
d5b7b3ae RE |
11645 | { |
11646 | /* In this case we know that we are being asked about the elimination | |
11647 | of the arg pointer register. If that register is not being used, | |
11648 | then there are no arguments on the stack, and we do not have to | |
11649 | worry that a far jump might force the prologue to push the link | |
11650 | register, changing the stack offsets. In this case we can just | |
11651 | return false, since the presence of far jumps in the function will | |
11652 | not affect stack offsets. | |
11653 | ||
11654 | If the arg pointer is live (or if it was live, but has now been | |
11655 | eliminated and so set to dead) then we do have to test to see if | |
11656 | the function might contain a far jump. This test can lead to some | |
11657 | false negatives, since before reload is completed, then length of | |
11658 | branch instructions is not known, so gcc defaults to returning their | |
11659 | longest length, which in turn sets the far jump attribute to true. | |
11660 | ||
11661 | A false negative will not result in bad code being generated, but it | |
11662 | will result in a needless push and pop of the link register. We | |
11663 | hope that this does not occur too often. */ | |
11664 | if (regs_ever_live [ARG_POINTER_REGNUM]) | |
11665 | cfun->machine->arg_pointer_live = 1; | |
5895f793 | 11666 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
11667 | return 0; |
11668 | } | |
11669 | ||
11670 | /* Check to see if the function contains a branch | |
11671 | insn with the far jump attribute set. */ | |
11672 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
11673 | { | |
11674 | if (GET_CODE (insn) == JUMP_INSN | |
11675 | /* Ignore tablejump patterns. */ | |
11676 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
11677 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
11678 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
11679 | ) | |
11680 | { | |
11681 | /* Record the fact that we have decied that | |
11682 | the function does use far jumps. */ | |
11683 | cfun->machine->far_jump_used = 1; | |
11684 | return 1; | |
11685 | } | |
11686 | } | |
11687 | ||
11688 | return 0; | |
11689 | } | |
11690 | ||
825dda42 | 11691 | /* Return nonzero if FUNC must be entered in ARM mode. */ |
d5b7b3ae | 11692 | int |
e32bac5b | 11693 | is_called_in_ARM_mode (tree func) |
d5b7b3ae RE |
11694 | { |
11695 | if (TREE_CODE (func) != FUNCTION_DECL) | |
11696 | abort (); | |
11697 | ||
11698 | /* Ignore the problem about functions whoes address is taken. */ | |
11699 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) | |
11700 | return TRUE; | |
11701 | ||
11702 | #ifdef ARM_PE | |
91d231cb | 11703 | return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; |
d5b7b3ae RE |
11704 | #else |
11705 | return FALSE; | |
11706 | #endif | |
11707 | } | |
11708 | ||
11709 | /* The bits which aren't usefully expanded as rtl. */ | |
cd2b33d0 | 11710 | const char * |
e32bac5b | 11711 | thumb_unexpanded_epilogue (void) |
d5b7b3ae RE |
11712 | { |
11713 | int regno; | |
11714 | int live_regs_mask = 0; | |
11715 | int high_regs_pushed = 0; | |
11716 | int leaf_function = leaf_function_p (); | |
11717 | int had_to_push_lr; | |
11718 | rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; | |
11719 | ||
11720 | if (return_used_this_function) | |
11721 | return ""; | |
11722 | ||
58e60158 AN |
11723 | if (IS_NAKED (arm_current_func_type ())) |
11724 | return ""; | |
11725 | ||
d5b7b3ae | 11726 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) |
aeaf4d25 | 11727 | if (THUMB_REG_PUSHED_P (regno)) |
d5b7b3ae RE |
11728 | live_regs_mask |= 1 << regno; |
11729 | ||
11730 | for (regno = 8; regno < 13; regno++) | |
aeaf4d25 AN |
11731 | if (THUMB_REG_PUSHED_P (regno)) |
11732 | high_regs_pushed++; | |
d5b7b3ae RE |
11733 | |
11734 | /* The prolog may have pushed some high registers to use as | |
11735 | work registers. eg the testuite file: | |
11736 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c | |
11737 | compiles to produce: | |
11738 | push {r4, r5, r6, r7, lr} | |
11739 | mov r7, r9 | |
11740 | mov r6, r8 | |
11741 | push {r6, r7} | |
11742 | as part of the prolog. We have to undo that pushing here. */ | |
11743 | ||
11744 | if (high_regs_pushed) | |
11745 | { | |
11746 | int mask = live_regs_mask; | |
11747 | int next_hi_reg; | |
11748 | int size; | |
11749 | int mode; | |
11750 | ||
11751 | #ifdef RTX_CODE | |
11752 | /* If we can deduce the registers used from the function's return value. | |
11753 | This is more reliable that examining regs_ever_live[] because that | |
11754 | will be set if the register is ever used in the function, not just if | |
11755 | the register is used to hold a return value. */ | |
11756 | ||
11757 | if (current_function_return_rtx != 0) | |
11758 | mode = GET_MODE (current_function_return_rtx); | |
11759 | else | |
11760 | #endif | |
11761 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
11762 | ||
11763 | size = GET_MODE_SIZE (mode); | |
11764 | ||
11765 | /* Unless we are returning a type of size > 12 register r3 is | |
11766 | available. */ | |
11767 | if (size < 13) | |
11768 | mask |= 1 << 3; | |
11769 | ||
11770 | if (mask == 0) | |
11771 | /* Oh dear! We have no low registers into which we can pop | |
11772 | high registers! */ | |
400500c4 RK |
11773 | internal_error |
11774 | ("no low registers available for popping high registers"); | |
d5b7b3ae RE |
11775 | |
11776 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) | |
aeaf4d25 | 11777 | if (THUMB_REG_PUSHED_P (next_hi_reg)) |
d5b7b3ae RE |
11778 | break; |
11779 | ||
11780 | while (high_regs_pushed) | |
11781 | { | |
11782 | /* Find lo register(s) into which the high register(s) can | |
11783 | be popped. */ | |
11784 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
11785 | { | |
11786 | if (mask & (1 << regno)) | |
11787 | high_regs_pushed--; | |
11788 | if (high_regs_pushed == 0) | |
11789 | break; | |
11790 | } | |
11791 | ||
11792 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
11793 | ||
11794 | /* Pop the values into the low register(s). */ | |
11795 | thumb_pushpop (asm_out_file, mask, 0); | |
11796 | ||
11797 | /* Move the value(s) into the high registers. */ | |
11798 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
11799 | { | |
11800 | if (mask & (1 << regno)) | |
11801 | { | |
11802 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
11803 | regno); | |
11804 | ||
11805 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) | |
aeaf4d25 | 11806 | if (THUMB_REG_PUSHED_P (next_hi_reg)) |
d5b7b3ae RE |
11807 | break; |
11808 | } | |
11809 | } | |
11810 | } | |
11811 | } | |
11812 | ||
5895f793 | 11813 | had_to_push_lr = (live_regs_mask || !leaf_function |
d5b7b3ae RE |
11814 | || thumb_far_jump_used_p (1)); |
11815 | ||
11816 | if (TARGET_BACKTRACE | |
11817 | && ((live_regs_mask & 0xFF) == 0) | |
11818 | && regs_ever_live [LAST_ARG_REGNUM] != 0) | |
11819 | { | |
11820 | /* The stack backtrace structure creation code had to | |
11821 | push R7 in order to get a work register, so we pop | |
11822 | it now. */ | |
11823 | live_regs_mask |= (1 << LAST_LO_REGNUM); | |
11824 | } | |
11825 | ||
11826 | if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE) | |
11827 | { | |
11828 | if (had_to_push_lr | |
5895f793 RE |
11829 | && !is_called_in_ARM_mode (current_function_decl) |
11830 | && !eh_ofs) | |
d5b7b3ae RE |
11831 | live_regs_mask |= 1 << PC_REGNUM; |
11832 | ||
11833 | /* Either no argument registers were pushed or a backtrace | |
11834 | structure was created which includes an adjusted stack | |
11835 | pointer, so just pop everything. */ | |
11836 | if (live_regs_mask) | |
11837 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE); | |
11838 | ||
11839 | if (eh_ofs) | |
11840 | thumb_exit (asm_out_file, 2, eh_ofs); | |
11841 | /* We have either just popped the return address into the | |
11842 | PC or it is was kept in LR for the entire function or | |
11843 | it is still on the stack because we do not want to | |
11844 | return by doing a pop {pc}. */ | |
11845 | else if ((live_regs_mask & (1 << PC_REGNUM)) == 0) | |
11846 | thumb_exit (asm_out_file, | |
11847 | (had_to_push_lr | |
11848 | && is_called_in_ARM_mode (current_function_decl)) ? | |
11849 | -1 : LR_REGNUM, NULL_RTX); | |
11850 | } | |
11851 | else | |
11852 | { | |
11853 | /* Pop everything but the return address. */ | |
5895f793 | 11854 | live_regs_mask &= ~(1 << PC_REGNUM); |
d5b7b3ae RE |
11855 | |
11856 | if (live_regs_mask) | |
11857 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE); | |
11858 | ||
11859 | if (had_to_push_lr) | |
11860 | /* Get the return address into a temporary register. */ | |
11861 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0); | |
11862 | ||
11863 | /* Remove the argument registers that were pushed onto the stack. */ | |
11864 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
11865 | SP_REGNUM, SP_REGNUM, | |
11866 | current_function_pretend_args_size); | |
11867 | ||
11868 | if (eh_ofs) | |
11869 | thumb_exit (asm_out_file, 2, eh_ofs); | |
11870 | else | |
11871 | thumb_exit (asm_out_file, | |
11872 | had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX); | |
11873 | } | |
11874 | ||
11875 | return ""; | |
11876 | } | |
11877 | ||
11878 | /* Functions to save and restore machine-specific function data. */ | |
e2500fed | 11879 | static struct machine_function * |
e32bac5b | 11880 | arm_init_machine_status (void) |
d5b7b3ae | 11881 | { |
e2500fed GK |
11882 | struct machine_function *machine; |
11883 | machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); | |
6d3d9133 | 11884 | |
e2500fed GK |
11885 | #if ARM_FT_UNKNOWN != 0 |
11886 | machine->func_type = ARM_FT_UNKNOWN; | |
6d3d9133 | 11887 | #endif |
e2500fed | 11888 | return machine; |
f7a80099 NC |
11889 | } |
11890 | ||
d5b7b3ae RE |
11891 | /* Return an RTX indicating where the return address to the |
11892 | calling function can be found. */ | |
11893 | rtx | |
e32bac5b | 11894 | arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
d5b7b3ae | 11895 | { |
d5b7b3ae RE |
11896 | if (count != 0) |
11897 | return NULL_RTX; | |
11898 | ||
9e2f7ec7 DD |
11899 | if (TARGET_APCS_32) |
11900 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); | |
11901 | else | |
d5b7b3ae | 11902 | { |
9e2f7ec7 | 11903 | rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM), |
d5b7b3ae | 11904 | GEN_INT (RETURN_ADDR_MASK26)); |
9e2f7ec7 | 11905 | return get_func_hard_reg_initial_val (cfun, lr); |
d5b7b3ae | 11906 | } |
d5b7b3ae RE |
11907 | } |
11908 | ||
11909 | /* Do anything needed before RTL is emitted for each function. */ | |
11910 | void | |
e32bac5b | 11911 | arm_init_expanders (void) |
d5b7b3ae RE |
11912 | { |
11913 | /* Arrange to initialize and mark the machine per-function status. */ | |
11914 | init_machine_status = arm_init_machine_status; | |
d5b7b3ae RE |
11915 | } |
11916 | ||
0977774b | 11917 | HOST_WIDE_INT |
e32bac5b | 11918 | thumb_get_frame_size (void) |
0977774b JT |
11919 | { |
11920 | int regno; | |
11921 | ||
0c2ca901 | 11922 | int base_size = ROUND_UP_WORD (get_frame_size ()); |
0977774b JT |
11923 | int count_regs = 0; |
11924 | int entry_size = 0; | |
c231c91e | 11925 | int leaf; |
0977774b JT |
11926 | |
11927 | if (! TARGET_THUMB) | |
11928 | abort (); | |
11929 | ||
11930 | if (! TARGET_ATPCS) | |
11931 | return base_size; | |
11932 | ||
11933 | /* We need to know if we are a leaf function. Unfortunately, it | |
11934 | is possible to be called after start_sequence has been called, | |
11935 | which causes get_insns to return the insns for the sequence, | |
11936 | not the function, which will cause leaf_function_p to return | |
11937 | the incorrect result. | |
11938 | ||
11939 | To work around this, we cache the computed frame size. This | |
11940 | works because we will only be calling RTL expanders that need | |
11941 | to know about leaf functions once reload has completed, and the | |
11942 | frame size cannot be changed after that time, so we can safely | |
11943 | use the cached value. */ | |
11944 | ||
11945 | if (reload_completed) | |
11946 | return cfun->machine->frame_size; | |
11947 | ||
c231c91e RE |
11948 | leaf = leaf_function_p (); |
11949 | ||
11950 | /* A leaf function does not need any stack alignment if it has nothing | |
11951 | on the stack. */ | |
11952 | if (leaf && base_size == 0) | |
11953 | { | |
11954 | cfun->machine->frame_size = 0; | |
11955 | return 0; | |
11956 | } | |
11957 | ||
0977774b JT |
11958 | /* We know that SP will be word aligned on entry, and we must |
11959 | preserve that condition at any subroutine call. But those are | |
11960 | the only constraints. */ | |
11961 | ||
11962 | /* Space for variadic functions. */ | |
11963 | if (current_function_pretend_args_size) | |
11964 | entry_size += current_function_pretend_args_size; | |
11965 | ||
11966 | /* Space for pushed lo registers. */ | |
11967 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
11968 | if (THUMB_REG_PUSHED_P (regno)) | |
11969 | count_regs++; | |
11970 | ||
11971 | /* Space for backtrace structure. */ | |
11972 | if (TARGET_BACKTRACE) | |
11973 | { | |
11974 | if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0) | |
11975 | entry_size += 20; | |
11976 | else | |
11977 | entry_size += 16; | |
11978 | } | |
11979 | ||
c231c91e | 11980 | if (count_regs || !leaf || thumb_far_jump_used_p (1)) |
0977774b JT |
11981 | count_regs++; /* LR */ |
11982 | ||
11983 | entry_size += count_regs * 4; | |
11984 | count_regs = 0; | |
11985 | ||
11986 | /* Space for pushed hi regs. */ | |
11987 | for (regno = 8; regno < 13; regno++) | |
11988 | if (THUMB_REG_PUSHED_P (regno)) | |
11989 | count_regs++; | |
11990 | ||
11991 | entry_size += count_regs * 4; | |
11992 | ||
11993 | if ((entry_size + base_size + current_function_outgoing_args_size) & 7) | |
11994 | base_size += 4; | |
11995 | if ((entry_size + base_size + current_function_outgoing_args_size) & 7) | |
11996 | abort (); | |
11997 | ||
11998 | cfun->machine->frame_size = base_size; | |
11999 | ||
12000 | return base_size; | |
12001 | } | |
12002 | ||
d5b7b3ae RE |
12003 | /* Generate the rest of a function's prologue. */ |
12004 | void | |
e32bac5b | 12005 | thumb_expand_prologue (void) |
d5b7b3ae | 12006 | { |
0977774b | 12007 | HOST_WIDE_INT amount = (thumb_get_frame_size () |
d5b7b3ae | 12008 | + current_function_outgoing_args_size); |
6d3d9133 NC |
12009 | unsigned long func_type; |
12010 | ||
12011 | func_type = arm_current_func_type (); | |
d5b7b3ae RE |
12012 | |
12013 | /* Naked functions don't have prologues. */ | |
6d3d9133 | 12014 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
12015 | return; |
12016 | ||
6d3d9133 NC |
12017 | if (IS_INTERRUPT (func_type)) |
12018 | { | |
c725bd79 | 12019 | error ("interrupt Service Routines cannot be coded in Thumb mode"); |
6d3d9133 NC |
12020 | return; |
12021 | } | |
12022 | ||
d5b7b3ae RE |
12023 | if (frame_pointer_needed) |
12024 | emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx)); | |
12025 | ||
12026 | if (amount) | |
12027 | { | |
0c2ca901 | 12028 | amount = ROUND_UP_WORD (amount); |
d5b7b3ae RE |
12029 | |
12030 | if (amount < 512) | |
12031 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1d6e90ac | 12032 | GEN_INT (- amount))); |
d5b7b3ae RE |
12033 | else |
12034 | { | |
12035 | int regno; | |
12036 | rtx reg; | |
12037 | ||
12038 | /* The stack decrement is too big for an immediate value in a single | |
12039 | insn. In theory we could issue multiple subtracts, but after | |
12040 | three of them it becomes more space efficient to place the full | |
12041 | value in the constant pool and load into a register. (Also the | |
12042 | ARM debugger really likes to see only one stack decrement per | |
12043 | function). So instead we look for a scratch register into which | |
12044 | we can load the decrement, and then we subtract this from the | |
12045 | stack pointer. Unfortunately on the thumb the only available | |
12046 | scratch registers are the argument registers, and we cannot use | |
12047 | these as they may hold arguments to the function. Instead we | |
12048 | attempt to locate a call preserved register which is used by this | |
12049 | function. If we can find one, then we know that it will have | |
12050 | been pushed at the start of the prologue and so we can corrupt | |
12051 | it now. */ | |
12052 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
aeaf4d25 | 12053 | if (THUMB_REG_PUSHED_P (regno) |
5895f793 RE |
12054 | && !(frame_pointer_needed |
12055 | && (regno == THUMB_HARD_FRAME_POINTER_REGNUM))) | |
d5b7b3ae RE |
12056 | break; |
12057 | ||
aeaf4d25 | 12058 | if (regno > LAST_LO_REGNUM) /* Very unlikely. */ |
d5b7b3ae RE |
12059 | { |
12060 | rtx spare = gen_rtx (REG, SImode, IP_REGNUM); | |
12061 | ||
6bc82793 | 12062 | /* Choose an arbitrary, non-argument low register. */ |
d5b7b3ae RE |
12063 | reg = gen_rtx (REG, SImode, LAST_LO_REGNUM); |
12064 | ||
12065 | /* Save it by copying it into a high, scratch register. */ | |
c14a3a45 NC |
12066 | emit_insn (gen_movsi (spare, reg)); |
12067 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
6bacc7b0 | 12068 | emit_insn (gen_prologue_use (spare)); |
d5b7b3ae RE |
12069 | |
12070 | /* Decrement the stack. */ | |
1d6e90ac | 12071 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
d5b7b3ae RE |
12072 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
12073 | reg)); | |
12074 | ||
12075 | /* Restore the low register's original value. */ | |
12076 | emit_insn (gen_movsi (reg, spare)); | |
12077 | ||
12078 | /* Emit a USE of the restored scratch register, so that flow | |
12079 | analysis will not consider the restore redundant. The | |
12080 | register won't be used again in this function and isn't | |
12081 | restored by the epilogue. */ | |
6bacc7b0 | 12082 | emit_insn (gen_prologue_use (reg)); |
d5b7b3ae RE |
12083 | } |
12084 | else | |
12085 | { | |
12086 | reg = gen_rtx (REG, SImode, regno); | |
12087 | ||
1d6e90ac | 12088 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
d5b7b3ae RE |
12089 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
12090 | reg)); | |
12091 | } | |
12092 | } | |
12093 | } | |
12094 | ||
70f4f91c | 12095 | if (current_function_profile || TARGET_NO_SCHED_PRO) |
d5b7b3ae RE |
12096 | emit_insn (gen_blockage ()); |
12097 | } | |
12098 | ||
12099 | void | |
e32bac5b | 12100 | thumb_expand_epilogue (void) |
d5b7b3ae | 12101 | { |
0977774b | 12102 | HOST_WIDE_INT amount = (thumb_get_frame_size () |
d5b7b3ae | 12103 | + current_function_outgoing_args_size); |
6d3d9133 NC |
12104 | |
12105 | /* Naked functions don't have prologues. */ | |
12106 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
12107 | return; |
12108 | ||
12109 | if (frame_pointer_needed) | |
12110 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
12111 | else if (amount) | |
12112 | { | |
0c2ca901 | 12113 | amount = ROUND_UP_WORD (amount); |
d5b7b3ae RE |
12114 | |
12115 | if (amount < 512) | |
12116 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
12117 | GEN_INT (amount))); | |
12118 | else | |
12119 | { | |
12120 | /* r3 is always free in the epilogue. */ | |
12121 | rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM); | |
12122 | ||
12123 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
12124 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
12125 | } | |
12126 | } | |
12127 | ||
12128 | /* Emit a USE (stack_pointer_rtx), so that | |
12129 | the stack adjustment will not be deleted. */ | |
6bacc7b0 | 12130 | emit_insn (gen_prologue_use (stack_pointer_rtx)); |
d5b7b3ae | 12131 | |
70f4f91c | 12132 | if (current_function_profile || TARGET_NO_SCHED_PRO) |
d5b7b3ae RE |
12133 | emit_insn (gen_blockage ()); |
12134 | } | |
12135 | ||
08c148a8 | 12136 | static void |
e32bac5b | 12137 | thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
d5b7b3ae RE |
12138 | { |
12139 | int live_regs_mask = 0; | |
12140 | int high_regs_pushed = 0; | |
d5b7b3ae RE |
12141 | int regno; |
12142 | ||
6d3d9133 | 12143 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
12144 | return; |
12145 | ||
12146 | if (is_called_in_ARM_mode (current_function_decl)) | |
12147 | { | |
12148 | const char * name; | |
12149 | ||
12150 | if (GET_CODE (DECL_RTL (current_function_decl)) != MEM) | |
12151 | abort (); | |
12152 | if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF) | |
12153 | abort (); | |
12154 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
12155 | ||
12156 | /* Generate code sequence to switch us into Thumb mode. */ | |
12157 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 12158 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
12159 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
12160 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
12161 | ||
12162 | /* Generate a label, so that the debugger will notice the | |
12163 | change in instruction sets. This label is also used by | |
12164 | the assembler to bypass the ARM code when this function | |
12165 | is called from a Thumb encoded function elsewhere in the | |
12166 | same file. Hence the definition of STUB_NAME here must | |
12167 | agree with the definition in gas/config/tc-arm.c */ | |
12168 | ||
12169 | #define STUB_NAME ".real_start_of" | |
12170 | ||
761c70aa | 12171 | fprintf (f, "\t.code\t16\n"); |
d5b7b3ae RE |
12172 | #ifdef ARM_PE |
12173 | if (arm_dllexport_name_p (name)) | |
e5951263 | 12174 | name = arm_strip_name_encoding (name); |
d5b7b3ae RE |
12175 | #endif |
12176 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); | |
761c70aa | 12177 | fprintf (f, "\t.thumb_func\n"); |
d5b7b3ae RE |
12178 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); |
12179 | } | |
12180 | ||
d5b7b3ae RE |
12181 | if (current_function_pretend_args_size) |
12182 | { | |
3cb66fd7 | 12183 | if (cfun->machine->uses_anonymous_args) |
d5b7b3ae RE |
12184 | { |
12185 | int num_pushes; | |
12186 | ||
761c70aa | 12187 | fprintf (f, "\tpush\t{"); |
d5b7b3ae | 12188 | |
e9d7b180 | 12189 | num_pushes = ARM_NUM_INTS (current_function_pretend_args_size); |
d5b7b3ae RE |
12190 | |
12191 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; | |
12192 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 12193 | regno++) |
d5b7b3ae RE |
12194 | asm_fprintf (f, "%r%s", regno, |
12195 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
12196 | ||
761c70aa | 12197 | fprintf (f, "}\n"); |
d5b7b3ae RE |
12198 | } |
12199 | else | |
12200 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", | |
12201 | SP_REGNUM, SP_REGNUM, | |
12202 | current_function_pretend_args_size); | |
12203 | } | |
12204 | ||
5895f793 | 12205 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) |
aeaf4d25 | 12206 | if (THUMB_REG_PUSHED_P (regno)) |
d5b7b3ae RE |
12207 | live_regs_mask |= 1 << regno; |
12208 | ||
5895f793 | 12209 | if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1)) |
d5b7b3ae RE |
12210 | live_regs_mask |= 1 << LR_REGNUM; |
12211 | ||
12212 | if (TARGET_BACKTRACE) | |
12213 | { | |
12214 | int offset; | |
12215 | int work_register = 0; | |
12216 | int wr; | |
12217 | ||
12218 | /* We have been asked to create a stack backtrace structure. | |
12219 | The code looks like this: | |
12220 | ||
12221 | 0 .align 2 | |
12222 | 0 func: | |
12223 | 0 sub SP, #16 Reserve space for 4 registers. | |
12224 | 2 push {R7} Get a work register. | |
12225 | 4 add R7, SP, #20 Get the stack pointer before the push. | |
12226 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
12227 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
12228 | 10 str R7, [SP, #16] Store it. | |
12229 | 12 mov R7, FP Get hold of the current frame pointer. | |
12230 | 14 str R7, [SP, #4] Store it. | |
12231 | 16 mov R7, LR Get hold of the current return address. | |
12232 | 18 str R7, [SP, #12] Store it. | |
12233 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
12234 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
12235 | ||
12236 | if ((live_regs_mask & 0xFF) == 0) | |
12237 | { | |
12238 | /* See if the a4 register is free. */ | |
12239 | ||
12240 | if (regs_ever_live [LAST_ARG_REGNUM] == 0) | |
12241 | work_register = LAST_ARG_REGNUM; | |
12242 | else /* We must push a register of our own */ | |
12243 | live_regs_mask |= (1 << LAST_LO_REGNUM); | |
12244 | } | |
12245 | ||
12246 | if (work_register == 0) | |
12247 | { | |
12248 | /* Select a register from the list that will be pushed to | |
12249 | use as our work register. */ | |
12250 | for (work_register = (LAST_LO_REGNUM + 1); work_register--;) | |
12251 | if ((1 << work_register) & live_regs_mask) | |
12252 | break; | |
12253 | } | |
12254 | ||
12255 | asm_fprintf | |
12256 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
12257 | SP_REGNUM, SP_REGNUM); | |
12258 | ||
12259 | if (live_regs_mask) | |
12260 | thumb_pushpop (f, live_regs_mask, 1); | |
12261 | ||
12262 | for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1) | |
12263 | if (wr & live_regs_mask) | |
12264 | offset += 4; | |
12265 | ||
12266 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
12267 | offset + 16 + current_function_pretend_args_size); | |
12268 | ||
12269 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
12270 | offset + 4); | |
12271 | ||
12272 | /* Make sure that the instruction fetching the PC is in the right place | |
12273 | to calculate "start of backtrace creation code + 12". */ | |
12274 | if (live_regs_mask) | |
12275 | { | |
12276 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
12277 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
12278 | offset + 12); | |
12279 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
12280 | ARM_HARD_FRAME_POINTER_REGNUM); | |
12281 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
12282 | offset); | |
12283 | } | |
12284 | else | |
12285 | { | |
12286 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
12287 | ARM_HARD_FRAME_POINTER_REGNUM); | |
12288 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
12289 | offset); | |
12290 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
12291 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
12292 | offset + 12); | |
12293 | } | |
12294 | ||
12295 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); | |
12296 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
12297 | offset + 8); | |
12298 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
12299 | offset + 12); | |
12300 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
12301 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
12302 | } | |
12303 | else if (live_regs_mask) | |
12304 | thumb_pushpop (f, live_regs_mask, 1); | |
12305 | ||
12306 | for (regno = 8; regno < 13; regno++) | |
e26053d1 NC |
12307 | if (THUMB_REG_PUSHED_P (regno)) |
12308 | high_regs_pushed++; | |
d5b7b3ae RE |
12309 | |
12310 | if (high_regs_pushed) | |
12311 | { | |
12312 | int pushable_regs = 0; | |
12313 | int mask = live_regs_mask & 0xff; | |
12314 | int next_hi_reg; | |
12315 | ||
12316 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
e26053d1 NC |
12317 | if (THUMB_REG_PUSHED_P (next_hi_reg)) |
12318 | break; | |
d5b7b3ae RE |
12319 | |
12320 | pushable_regs = mask; | |
12321 | ||
12322 | if (pushable_regs == 0) | |
12323 | { | |
12324 | /* Desperation time -- this probably will never happen. */ | |
aeaf4d25 | 12325 | if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)) |
d5b7b3ae RE |
12326 | asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM); |
12327 | mask = 1 << LAST_ARG_REGNUM; | |
12328 | } | |
12329 | ||
12330 | while (high_regs_pushed > 0) | |
12331 | { | |
12332 | for (regno = LAST_LO_REGNUM; regno >= 0; regno--) | |
12333 | { | |
12334 | if (mask & (1 << regno)) | |
12335 | { | |
12336 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
12337 | ||
5895f793 | 12338 | high_regs_pushed--; |
d5b7b3ae RE |
12339 | |
12340 | if (high_regs_pushed) | |
aeaf4d25 AN |
12341 | { |
12342 | for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM; | |
12343 | next_hi_reg--) | |
12344 | if (THUMB_REG_PUSHED_P (next_hi_reg)) | |
d5b7b3ae | 12345 | break; |
aeaf4d25 | 12346 | } |
d5b7b3ae RE |
12347 | else |
12348 | { | |
5895f793 | 12349 | mask &= ~((1 << regno) - 1); |
d5b7b3ae RE |
12350 | break; |
12351 | } | |
12352 | } | |
12353 | } | |
12354 | ||
12355 | thumb_pushpop (f, mask, 1); | |
12356 | } | |
12357 | ||
12358 | if (pushable_regs == 0 | |
aeaf4d25 | 12359 | && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))) |
d5b7b3ae RE |
12360 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
12361 | } | |
12362 | } | |
12363 | ||
12364 | /* Handle the case of a double word load into a low register from | |
12365 | a computed memory address. The computed address may involve a | |
12366 | register which is overwritten by the load. */ | |
cd2b33d0 | 12367 | const char * |
e32bac5b | 12368 | thumb_load_double_from_address (rtx *operands) |
d5b7b3ae RE |
12369 | { |
12370 | rtx addr; | |
12371 | rtx base; | |
12372 | rtx offset; | |
12373 | rtx arg1; | |
12374 | rtx arg2; | |
12375 | ||
12376 | if (GET_CODE (operands[0]) != REG) | |
400500c4 | 12377 | abort (); |
d5b7b3ae RE |
12378 | |
12379 | if (GET_CODE (operands[1]) != MEM) | |
400500c4 | 12380 | abort (); |
d5b7b3ae RE |
12381 | |
12382 | /* Get the memory address. */ | |
12383 | addr = XEXP (operands[1], 0); | |
12384 | ||
12385 | /* Work out how the memory address is computed. */ | |
12386 | switch (GET_CODE (addr)) | |
12387 | { | |
12388 | case REG: | |
12389 | operands[2] = gen_rtx (MEM, SImode, | |
12390 | plus_constant (XEXP (operands[1], 0), 4)); | |
12391 | ||
12392 | if (REGNO (operands[0]) == REGNO (addr)) | |
12393 | { | |
12394 | output_asm_insn ("ldr\t%H0, %2", operands); | |
12395 | output_asm_insn ("ldr\t%0, %1", operands); | |
12396 | } | |
12397 | else | |
12398 | { | |
12399 | output_asm_insn ("ldr\t%0, %1", operands); | |
12400 | output_asm_insn ("ldr\t%H0, %2", operands); | |
12401 | } | |
12402 | break; | |
12403 | ||
12404 | case CONST: | |
12405 | /* Compute <address> + 4 for the high order load. */ | |
12406 | operands[2] = gen_rtx (MEM, SImode, | |
12407 | plus_constant (XEXP (operands[1], 0), 4)); | |
12408 | ||
12409 | output_asm_insn ("ldr\t%0, %1", operands); | |
12410 | output_asm_insn ("ldr\t%H0, %2", operands); | |
12411 | break; | |
12412 | ||
12413 | case PLUS: | |
12414 | arg1 = XEXP (addr, 0); | |
12415 | arg2 = XEXP (addr, 1); | |
12416 | ||
12417 | if (CONSTANT_P (arg1)) | |
12418 | base = arg2, offset = arg1; | |
12419 | else | |
12420 | base = arg1, offset = arg2; | |
12421 | ||
12422 | if (GET_CODE (base) != REG) | |
400500c4 | 12423 | abort (); |
d5b7b3ae RE |
12424 | |
12425 | /* Catch the case of <address> = <reg> + <reg> */ | |
12426 | if (GET_CODE (offset) == REG) | |
12427 | { | |
12428 | int reg_offset = REGNO (offset); | |
12429 | int reg_base = REGNO (base); | |
12430 | int reg_dest = REGNO (operands[0]); | |
12431 | ||
12432 | /* Add the base and offset registers together into the | |
12433 | higher destination register. */ | |
12434 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
12435 | reg_dest + 1, reg_base, reg_offset); | |
12436 | ||
12437 | /* Load the lower destination register from the address in | |
12438 | the higher destination register. */ | |
12439 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
12440 | reg_dest, reg_dest + 1); | |
12441 | ||
12442 | /* Load the higher destination register from its own address | |
12443 | plus 4. */ | |
12444 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
12445 | reg_dest + 1, reg_dest + 1); | |
12446 | } | |
12447 | else | |
12448 | { | |
12449 | /* Compute <address> + 4 for the high order load. */ | |
12450 | operands[2] = gen_rtx (MEM, SImode, | |
12451 | plus_constant (XEXP (operands[1], 0), 4)); | |
12452 | ||
12453 | /* If the computed address is held in the low order register | |
12454 | then load the high order register first, otherwise always | |
12455 | load the low order register first. */ | |
12456 | if (REGNO (operands[0]) == REGNO (base)) | |
12457 | { | |
12458 | output_asm_insn ("ldr\t%H0, %2", operands); | |
12459 | output_asm_insn ("ldr\t%0, %1", operands); | |
12460 | } | |
12461 | else | |
12462 | { | |
12463 | output_asm_insn ("ldr\t%0, %1", operands); | |
12464 | output_asm_insn ("ldr\t%H0, %2", operands); | |
12465 | } | |
12466 | } | |
12467 | break; | |
12468 | ||
12469 | case LABEL_REF: | |
12470 | /* With no registers to worry about we can just load the value | |
12471 | directly. */ | |
12472 | operands[2] = gen_rtx (MEM, SImode, | |
12473 | plus_constant (XEXP (operands[1], 0), 4)); | |
12474 | ||
12475 | output_asm_insn ("ldr\t%H0, %2", operands); | |
12476 | output_asm_insn ("ldr\t%0, %1", operands); | |
12477 | break; | |
12478 | ||
12479 | default: | |
400500c4 | 12480 | abort (); |
d5b7b3ae RE |
12481 | break; |
12482 | } | |
12483 | ||
12484 | return ""; | |
12485 | } | |
12486 | ||
cd2b33d0 | 12487 | const char * |
e32bac5b | 12488 | thumb_output_move_mem_multiple (int n, rtx *operands) |
d5b7b3ae RE |
12489 | { |
12490 | rtx tmp; | |
12491 | ||
12492 | switch (n) | |
12493 | { | |
12494 | case 2: | |
ca356f3a | 12495 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 12496 | { |
ca356f3a RE |
12497 | tmp = operands[4]; |
12498 | operands[4] = operands[5]; | |
12499 | operands[5] = tmp; | |
d5b7b3ae | 12500 | } |
ca356f3a RE |
12501 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
12502 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
12503 | break; |
12504 | ||
12505 | case 3: | |
ca356f3a | 12506 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 12507 | { |
ca356f3a RE |
12508 | tmp = operands[4]; |
12509 | operands[4] = operands[5]; | |
12510 | operands[5] = tmp; | |
d5b7b3ae | 12511 | } |
ca356f3a | 12512 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 12513 | { |
ca356f3a RE |
12514 | tmp = operands[5]; |
12515 | operands[5] = operands[6]; | |
12516 | operands[6] = tmp; | |
d5b7b3ae | 12517 | } |
ca356f3a | 12518 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 12519 | { |
ca356f3a RE |
12520 | tmp = operands[4]; |
12521 | operands[4] = operands[5]; | |
12522 | operands[5] = tmp; | |
d5b7b3ae RE |
12523 | } |
12524 | ||
ca356f3a RE |
12525 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
12526 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
12527 | break; |
12528 | ||
12529 | default: | |
12530 | abort (); | |
12531 | } | |
12532 | ||
12533 | return ""; | |
12534 | } | |
12535 | ||
1d6e90ac | 12536 | /* Routines for generating rtl. */ |
d5b7b3ae | 12537 | void |
e32bac5b | 12538 | thumb_expand_movstrqi (rtx *operands) |
d5b7b3ae RE |
12539 | { |
12540 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
12541 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
12542 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
12543 | HOST_WIDE_INT offset = 0; | |
12544 | ||
12545 | while (len >= 12) | |
12546 | { | |
ca356f3a | 12547 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
12548 | len -= 12; |
12549 | } | |
12550 | ||
12551 | if (len >= 8) | |
12552 | { | |
ca356f3a | 12553 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
12554 | len -= 8; |
12555 | } | |
12556 | ||
12557 | if (len >= 4) | |
12558 | { | |
12559 | rtx reg = gen_reg_rtx (SImode); | |
12560 | emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in))); | |
12561 | emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg)); | |
12562 | len -= 4; | |
12563 | offset += 4; | |
12564 | } | |
12565 | ||
12566 | if (len >= 2) | |
12567 | { | |
12568 | rtx reg = gen_reg_rtx (HImode); | |
12569 | emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode, | |
12570 | plus_constant (in, offset)))); | |
12571 | emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)), | |
12572 | reg)); | |
12573 | len -= 2; | |
12574 | offset += 2; | |
12575 | } | |
12576 | ||
12577 | if (len) | |
12578 | { | |
12579 | rtx reg = gen_reg_rtx (QImode); | |
12580 | emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode, | |
12581 | plus_constant (in, offset)))); | |
12582 | emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)), | |
12583 | reg)); | |
12584 | } | |
12585 | } | |
12586 | ||
12587 | int | |
e32bac5b | 12588 | thumb_cmp_operand (rtx op, enum machine_mode mode) |
d5b7b3ae RE |
12589 | { |
12590 | return ((GET_CODE (op) == CONST_INT | |
12591 | && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256) | |
12592 | || register_operand (op, mode)); | |
12593 | } | |
12594 | ||
cd2b33d0 | 12595 | static const char * |
e32bac5b | 12596 | thumb_condition_code (rtx x, int invert) |
d5b7b3ae | 12597 | { |
1d6e90ac | 12598 | static const char * const conds[] = |
d5b7b3ae RE |
12599 | { |
12600 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
12601 | "hi", "ls", "ge", "lt", "gt", "le" | |
12602 | }; | |
12603 | int val; | |
12604 | ||
12605 | switch (GET_CODE (x)) | |
12606 | { | |
12607 | case EQ: val = 0; break; | |
12608 | case NE: val = 1; break; | |
12609 | case GEU: val = 2; break; | |
12610 | case LTU: val = 3; break; | |
12611 | case GTU: val = 8; break; | |
12612 | case LEU: val = 9; break; | |
12613 | case GE: val = 10; break; | |
12614 | case LT: val = 11; break; | |
12615 | case GT: val = 12; break; | |
12616 | case LE: val = 13; break; | |
12617 | default: | |
12618 | abort (); | |
12619 | } | |
12620 | ||
12621 | return conds[val ^ invert]; | |
12622 | } | |
12623 | ||
12624 | /* Handle storing a half-word to memory during reload. */ | |
12625 | void | |
e32bac5b | 12626 | thumb_reload_out_hi (rtx *operands) |
d5b7b3ae RE |
12627 | { |
12628 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
12629 | } | |
12630 | ||
e32bac5b | 12631 | /* Handle reading a half-word from memory during reload. */ |
d5b7b3ae | 12632 | void |
e32bac5b | 12633 | thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) |
d5b7b3ae RE |
12634 | { |
12635 | abort (); | |
12636 | } | |
12637 | ||
c27ba912 DM |
12638 | /* Return the length of a function name prefix |
12639 | that starts with the character 'c'. */ | |
12640 | static int | |
e32bac5b | 12641 | arm_get_strip_length (int c) |
c27ba912 DM |
12642 | { |
12643 | switch (c) | |
12644 | { | |
12645 | ARM_NAME_ENCODING_LENGTHS | |
12646 | default: return 0; | |
12647 | } | |
12648 | } | |
12649 | ||
12650 | /* Return a pointer to a function's name with any | |
12651 | and all prefix encodings stripped from it. */ | |
12652 | const char * | |
e32bac5b | 12653 | arm_strip_name_encoding (const char *name) |
c27ba912 DM |
12654 | { |
12655 | int skip; | |
12656 | ||
12657 | while ((skip = arm_get_strip_length (* name))) | |
12658 | name += skip; | |
12659 | ||
12660 | return name; | |
12661 | } | |
12662 | ||
e1944073 KW |
12663 | /* If there is a '*' anywhere in the name's prefix, then |
12664 | emit the stripped name verbatim, otherwise prepend an | |
12665 | underscore if leading underscores are being used. */ | |
e1944073 | 12666 | void |
e32bac5b | 12667 | arm_asm_output_labelref (FILE *stream, const char *name) |
e1944073 KW |
12668 | { |
12669 | int skip; | |
12670 | int verbatim = 0; | |
12671 | ||
12672 | while ((skip = arm_get_strip_length (* name))) | |
12673 | { | |
12674 | verbatim |= (*name == '*'); | |
12675 | name += skip; | |
12676 | } | |
12677 | ||
12678 | if (verbatim) | |
12679 | fputs (name, stream); | |
12680 | else | |
12681 | asm_fprintf (stream, "%U%s", name); | |
12682 | } | |
12683 | ||
e2500fed GK |
12684 | rtx aof_pic_label; |
12685 | ||
2b835d68 | 12686 | #ifdef AOF_ASSEMBLER |
6354dc9b | 12687 | /* Special functions only needed when producing AOF syntax assembler. */ |
2b835d68 | 12688 | |
32de079a RE |
12689 | struct pic_chain |
12690 | { | |
62b10bbc | 12691 | struct pic_chain * next; |
5f37d07c | 12692 | const char * symname; |
32de079a RE |
12693 | }; |
12694 | ||
62b10bbc | 12695 | static struct pic_chain * aof_pic_chain = NULL; |
32de079a RE |
12696 | |
12697 | rtx | |
e32bac5b | 12698 | aof_pic_entry (rtx x) |
32de079a | 12699 | { |
62b10bbc | 12700 | struct pic_chain ** chainp; |
32de079a RE |
12701 | int offset; |
12702 | ||
12703 | if (aof_pic_label == NULL_RTX) | |
12704 | { | |
43cffd11 | 12705 | aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons"); |
32de079a RE |
12706 | } |
12707 | ||
12708 | for (offset = 0, chainp = &aof_pic_chain; *chainp; | |
12709 | offset += 4, chainp = &(*chainp)->next) | |
12710 | if ((*chainp)->symname == XSTR (x, 0)) | |
12711 | return plus_constant (aof_pic_label, offset); | |
12712 | ||
12713 | *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain)); | |
12714 | (*chainp)->next = NULL; | |
12715 | (*chainp)->symname = XSTR (x, 0); | |
12716 | return plus_constant (aof_pic_label, offset); | |
12717 | } | |
12718 | ||
12719 | void | |
e32bac5b | 12720 | aof_dump_pic_table (FILE *f) |
32de079a | 12721 | { |
62b10bbc | 12722 | struct pic_chain * chain; |
32de079a RE |
12723 | |
12724 | if (aof_pic_chain == NULL) | |
12725 | return; | |
12726 | ||
dd18ae56 NC |
12727 | asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n", |
12728 | PIC_OFFSET_TABLE_REGNUM, | |
12729 | PIC_OFFSET_TABLE_REGNUM); | |
32de079a RE |
12730 | fputs ("|x$adcons|\n", f); |
12731 | ||
12732 | for (chain = aof_pic_chain; chain; chain = chain->next) | |
12733 | { | |
12734 | fputs ("\tDCD\t", f); | |
12735 | assemble_name (f, chain->symname); | |
12736 | fputs ("\n", f); | |
12737 | } | |
12738 | } | |
12739 | ||
2b835d68 RE |
12740 | int arm_text_section_count = 1; |
12741 | ||
12742 | char * | |
e32bac5b | 12743 | aof_text_section (void ) |
2b835d68 RE |
12744 | { |
12745 | static char buf[100]; | |
2b835d68 RE |
12746 | sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY", |
12747 | arm_text_section_count++); | |
12748 | if (flag_pic) | |
12749 | strcat (buf, ", PIC, REENTRANT"); | |
12750 | return buf; | |
12751 | } | |
12752 | ||
12753 | static int arm_data_section_count = 1; | |
12754 | ||
12755 | char * | |
e32bac5b | 12756 | aof_data_section (void) |
2b835d68 RE |
12757 | { |
12758 | static char buf[100]; | |
12759 | sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++); | |
12760 | return buf; | |
12761 | } | |
12762 | ||
12763 | /* The AOF assembler is religiously strict about declarations of | |
12764 | imported and exported symbols, so that it is impossible to declare | |
956d6950 | 12765 | a function as imported near the beginning of the file, and then to |
2b835d68 RE |
12766 | export it later on. It is, however, possible to delay the decision |
12767 | until all the functions in the file have been compiled. To get | |
12768 | around this, we maintain a list of the imports and exports, and | |
12769 | delete from it any that are subsequently defined. At the end of | |
12770 | compilation we spit the remainder of the list out before the END | |
12771 | directive. */ | |
12772 | ||
12773 | struct import | |
12774 | { | |
62b10bbc | 12775 | struct import * next; |
5f37d07c | 12776 | const char * name; |
2b835d68 RE |
12777 | }; |
12778 | ||
62b10bbc | 12779 | static struct import * imports_list = NULL; |
2b835d68 RE |
12780 | |
12781 | void | |
e32bac5b | 12782 | aof_add_import (const char *name) |
2b835d68 | 12783 | { |
62b10bbc | 12784 | struct import * new; |
2b835d68 RE |
12785 | |
12786 | for (new = imports_list; new; new = new->next) | |
12787 | if (new->name == name) | |
12788 | return; | |
12789 | ||
12790 | new = (struct import *) xmalloc (sizeof (struct import)); | |
12791 | new->next = imports_list; | |
12792 | imports_list = new; | |
12793 | new->name = name; | |
12794 | } | |
12795 | ||
12796 | void | |
e32bac5b | 12797 | aof_delete_import (const char *name) |
2b835d68 | 12798 | { |
62b10bbc | 12799 | struct import ** old; |
2b835d68 RE |
12800 | |
12801 | for (old = &imports_list; *old; old = & (*old)->next) | |
12802 | { | |
12803 | if ((*old)->name == name) | |
12804 | { | |
12805 | *old = (*old)->next; | |
12806 | return; | |
12807 | } | |
12808 | } | |
12809 | } | |
12810 | ||
12811 | int arm_main_function = 0; | |
12812 | ||
a5fe455b | 12813 | static void |
e32bac5b | 12814 | aof_dump_imports (FILE *f) |
2b835d68 RE |
12815 | { |
12816 | /* The AOF assembler needs this to cause the startup code to be extracted | |
12817 | from the library. Brining in __main causes the whole thing to work | |
12818 | automagically. */ | |
12819 | if (arm_main_function) | |
12820 | { | |
12821 | text_section (); | |
12822 | fputs ("\tIMPORT __main\n", f); | |
12823 | fputs ("\tDCD __main\n", f); | |
12824 | } | |
12825 | ||
12826 | /* Now dump the remaining imports. */ | |
12827 | while (imports_list) | |
12828 | { | |
12829 | fprintf (f, "\tIMPORT\t"); | |
12830 | assemble_name (f, imports_list->name); | |
12831 | fputc ('\n', f); | |
12832 | imports_list = imports_list->next; | |
12833 | } | |
12834 | } | |
5eb99654 KG |
12835 | |
12836 | static void | |
e32bac5b | 12837 | aof_globalize_label (FILE *stream, const char *name) |
5eb99654 KG |
12838 | { |
12839 | default_globalize_label (stream, name); | |
12840 | if (! strcmp (name, "main")) | |
12841 | arm_main_function = 1; | |
12842 | } | |
a5fe455b | 12843 | |
1bc7c5b6 ZW |
12844 | static void |
12845 | aof_file_start () | |
12846 | { | |
12847 | fputs ("__r0\tRN\t0\n", asm_out_file); | |
12848 | fputs ("__a1\tRN\t0\n", asm_out_file); | |
12849 | fputs ("__a2\tRN\t1\n", asm_out_file); | |
12850 | fputs ("__a3\tRN\t2\n", asm_out_file); | |
12851 | fputs ("__a4\tRN\t3\n", asm_out_file); | |
12852 | fputs ("__v1\tRN\t4\n", asm_out_file); | |
12853 | fputs ("__v2\tRN\t5\n", asm_out_file); | |
12854 | fputs ("__v3\tRN\t6\n", asm_out_file); | |
12855 | fputs ("__v4\tRN\t7\n", asm_out_file); | |
12856 | fputs ("__v5\tRN\t8\n", asm_out_file); | |
12857 | fputs ("__v6\tRN\t9\n", asm_out_file); | |
12858 | fputs ("__sl\tRN\t10\n", asm_out_file); | |
12859 | fputs ("__fp\tRN\t11\n", asm_out_file); | |
12860 | fputs ("__ip\tRN\t12\n", asm_out_file); | |
12861 | fputs ("__sp\tRN\t13\n", asm_out_file); | |
12862 | fputs ("__lr\tRN\t14\n", asm_out_file); | |
12863 | fputs ("__pc\tRN\t15\n", asm_out_file); | |
12864 | fputs ("__f0\tFN\t0\n", asm_out_file); | |
12865 | fputs ("__f1\tFN\t1\n", asm_out_file); | |
12866 | fputs ("__f2\tFN\t2\n", asm_out_file); | |
12867 | fputs ("__f3\tFN\t3\n", asm_out_file); | |
12868 | fputs ("__f4\tFN\t4\n", asm_out_file); | |
12869 | fputs ("__f5\tFN\t5\n", asm_out_file); | |
12870 | fputs ("__f6\tFN\t6\n", asm_out_file); | |
12871 | fputs ("__f7\tFN\t7\n", asm_out_file); | |
12872 | text_section (); | |
12873 | } | |
12874 | ||
a5fe455b | 12875 | static void |
e32bac5b | 12876 | aof_file_end (void) |
a5fe455b ZW |
12877 | { |
12878 | if (flag_pic) | |
12879 | aof_dump_pic_table (asm_out_file); | |
12880 | aof_dump_imports (asm_out_file); | |
12881 | fputs ("\tEND\n", asm_out_file); | |
12882 | } | |
2b835d68 | 12883 | #endif /* AOF_ASSEMBLER */ |
7c262518 | 12884 | |
ebe413e5 | 12885 | #ifdef OBJECT_FORMAT_ELF |
7c262518 RH |
12886 | /* Switch to an arbitrary section NAME with attributes as specified |
12887 | by FLAGS. ALIGN specifies any known alignment requirements for | |
12888 | the section; 0 if the default should be used. | |
12889 | ||
12890 | Differs from the default elf version only in the prefix character | |
12891 | used before the section type. */ | |
12892 | ||
12893 | static void | |
e32bac5b | 12894 | arm_elf_asm_named_section (const char *name, unsigned int flags) |
7c262518 | 12895 | { |
6a0a6ac4 AM |
12896 | char flagchars[10], *f = flagchars; |
12897 | ||
12898 | if (! named_section_first_declaration (name)) | |
12899 | { | |
12900 | fprintf (asm_out_file, "\t.section\t%s\n", name); | |
12901 | return; | |
12902 | } | |
7c262518 RH |
12903 | |
12904 | if (!(flags & SECTION_DEBUG)) | |
12905 | *f++ = 'a'; | |
12906 | if (flags & SECTION_WRITE) | |
12907 | *f++ = 'w'; | |
12908 | if (flags & SECTION_CODE) | |
12909 | *f++ = 'x'; | |
12910 | if (flags & SECTION_SMALL) | |
12911 | *f++ = 's'; | |
201556f0 JJ |
12912 | if (flags & SECTION_MERGE) |
12913 | *f++ = 'M'; | |
12914 | if (flags & SECTION_STRINGS) | |
12915 | *f++ = 'S'; | |
6a0a6ac4 AM |
12916 | if (flags & SECTION_TLS) |
12917 | *f++ = 'T'; | |
7c262518 RH |
12918 | *f = '\0'; |
12919 | ||
6a0a6ac4 | 12920 | fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars); |
7c262518 | 12921 | |
6a0a6ac4 AM |
12922 | if (!(flags & SECTION_NOTYPE)) |
12923 | { | |
12924 | const char *type; | |
12925 | ||
12926 | if (flags & SECTION_BSS) | |
12927 | type = "nobits"; | |
12928 | else | |
12929 | type = "progbits"; | |
12930 | ||
12931 | fprintf (asm_out_file, ",%%%s", type); | |
12932 | ||
12933 | if (flags & SECTION_ENTSIZE) | |
12934 | fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE); | |
12935 | } | |
12936 | ||
12937 | putc ('\n', asm_out_file); | |
7c262518 | 12938 | } |
ebe413e5 | 12939 | #endif |
fb49053f RH |
12940 | |
12941 | #ifndef ARM_PE | |
12942 | /* Symbols in the text segment can be accessed without indirecting via the | |
12943 | constant pool; it may take an extra binary operation, but this is still | |
12944 | faster than indirecting via memory. Don't do this when not optimizing, | |
12945 | since we won't be calculating al of the offsets necessary to do this | |
12946 | simplification. */ | |
12947 | ||
12948 | static void | |
e32bac5b | 12949 | arm_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f RH |
12950 | { |
12951 | /* This doesn't work with AOF syntax, since the string table may be in | |
12952 | a different AREA. */ | |
12953 | #ifndef AOF_ASSEMBLER | |
12954 | if (optimize > 0 && TREE_CONSTANT (decl) | |
12955 | && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) | |
c6a2438a | 12956 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
fb49053f RH |
12957 | #endif |
12958 | ||
12959 | /* If we are referencing a function that is weak then encode a long call | |
12960 | flag in the function name, otherwise if the function is static or | |
12961 | or known to be defined in this file then encode a short call flag. */ | |
12962 | if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd') | |
12963 | { | |
12964 | if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl)) | |
12965 | arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); | |
12966 | else if (! TREE_PUBLIC (decl)) | |
12967 | arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); | |
12968 | } | |
12969 | } | |
12970 | #endif /* !ARM_PE */ | |
483ab821 | 12971 | |
4977bab6 | 12972 | static void |
e32bac5b | 12973 | arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) |
4977bab6 ZW |
12974 | { |
12975 | if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno | |
12976 | && !strcmp (prefix, "L")) | |
12977 | { | |
12978 | arm_ccfsm_state = 0; | |
12979 | arm_target_insn = NULL; | |
12980 | } | |
12981 | default_internal_label (stream, prefix, labelno); | |
12982 | } | |
12983 | ||
c590b625 RH |
12984 | /* Output code to add DELTA to the first argument, and then jump |
12985 | to FUNCTION. Used for C++ multiple inheritance. */ | |
c590b625 | 12986 | static void |
e32bac5b RE |
12987 | arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
12988 | HOST_WIDE_INT delta, | |
12989 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
12990 | tree function) | |
483ab821 MM |
12991 | { |
12992 | int mi_delta = delta; | |
12993 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; | |
12994 | int shift = 0; | |
12995 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) | |
12996 | ? 1 : 0); | |
12997 | if (mi_delta < 0) | |
12998 | mi_delta = - mi_delta; | |
12999 | while (mi_delta != 0) | |
13000 | { | |
13001 | if ((mi_delta & (3 << shift)) == 0) | |
13002 | shift += 2; | |
13003 | else | |
13004 | { | |
13005 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
13006 | mi_op, this_regno, this_regno, | |
13007 | mi_delta & (0xff << shift)); | |
13008 | mi_delta &= ~(0xff << shift); | |
13009 | shift += 8; | |
13010 | } | |
13011 | } | |
13012 | fputs ("\tb\t", file); | |
13013 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
13014 | if (NEED_PLT_RELOC) | |
13015 | fputs ("(PLT)", file); | |
13016 | fputc ('\n', file); | |
13017 | } | |
5a9335ef NC |
13018 | |
13019 | int | |
13020 | arm_emit_vector_const (file, x) | |
13021 | FILE * file; | |
13022 | rtx x; | |
13023 | { | |
13024 | int i; | |
13025 | const char * pattern; | |
13026 | ||
13027 | if (GET_CODE (x) != CONST_VECTOR) | |
13028 | abort (); | |
13029 | ||
13030 | switch (GET_MODE (x)) | |
13031 | { | |
13032 | case V2SImode: pattern = "%08x"; break; | |
13033 | case V4HImode: pattern = "%04x"; break; | |
13034 | case V8QImode: pattern = "%02x"; break; | |
13035 | default: abort (); | |
13036 | } | |
13037 | ||
13038 | fprintf (file, "0x"); | |
13039 | for (i = CONST_VECTOR_NUNITS (x); i--;) | |
13040 | { | |
13041 | rtx element; | |
13042 | ||
13043 | element = CONST_VECTOR_ELT (x, i); | |
13044 | fprintf (file, pattern, INTVAL (element)); | |
13045 | } | |
13046 | ||
13047 | return 1; | |
13048 | } | |
13049 | ||
13050 | const char * | |
13051 | arm_output_load_gr (operands) | |
13052 | rtx * operands; | |
13053 | { | |
13054 | rtx reg; | |
13055 | rtx offset; | |
13056 | rtx wcgr; | |
13057 | rtx sum; | |
13058 | ||
13059 | if (GET_CODE (operands [1]) != MEM | |
13060 | || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS | |
13061 | || GET_CODE (reg = XEXP (sum, 0)) != REG | |
13062 | || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT | |
13063 | || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) | |
13064 | return "wldrw%?\t%0, %1"; | |
13065 | ||
13066 | /* Fix up an out-of-range load of a GR register. */ | |
13067 | output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); | |
13068 | wcgr = operands[0]; | |
13069 | operands[0] = reg; | |
13070 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
13071 | ||
13072 | operands[0] = wcgr; | |
13073 | operands[1] = reg; | |
13074 | output_asm_insn ("tmcr%?\t%0, %1", operands); | |
13075 | output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); | |
13076 | ||
13077 | return ""; | |
13078 | } |