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b36ba79f | 1 | /* Output routines for GCC for ARM. |
f954388e | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
bf98ec6c | 3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
cce8749e | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 5 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e | 7 | |
4f448245 | 8 | This file is part of GCC. |
cce8749e | 9 | |
4f448245 NC |
10 | GCC is free software; you can redistribute it and/or modify it |
11 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 12 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 13 | option) any later version. |
cce8749e | 14 | |
4f448245 NC |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
cce8749e | 19 | |
4f448245 | 20 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
f676971a | 23 | |
56636818 | 24 | #include "config.h" |
43cffd11 | 25 | #include "system.h" |
4977bab6 ZW |
26 | #include "coretypes.h" |
27 | #include "tm.h" | |
cce8749e | 28 | #include "rtl.h" |
d5b7b3ae | 29 | #include "tree.h" |
c7319d87 | 30 | #include "obstack.h" |
cce8749e CH |
31 | #include "regs.h" |
32 | #include "hard-reg-set.h" | |
33 | #include "real.h" | |
34 | #include "insn-config.h" | |
35 | #include "conditions.h" | |
cce8749e CH |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
af48348a | 39 | #include "reload.h" |
49ad7cfa | 40 | #include "function.h" |
bee06f3d | 41 | #include "expr.h" |
e78d8e51 | 42 | #include "optabs.h" |
ad076f4e | 43 | #include "toplev.h" |
aec3cfba | 44 | #include "recog.h" |
92a432f4 | 45 | #include "ggc.h" |
d5b7b3ae | 46 | #include "except.h" |
8b97c5f8 | 47 | #include "c-pragma.h" |
7b8b8ade | 48 | #include "integrate.h" |
c27ba912 | 49 | #include "tm_p.h" |
672a6f42 NB |
50 | #include "target.h" |
51 | #include "target-def.h" | |
980e61bb | 52 | #include "debug.h" |
6e34d3a3 | 53 | #include "langhooks.h" |
6fb5fa3c | 54 | #include "df.h" |
cce8749e | 55 | |
d5b7b3ae RE |
56 | /* Forward definitions of types. */ |
57 | typedef struct minipool_node Mnode; | |
58 | typedef struct minipool_fixup Mfix; | |
59 | ||
1d6e90ac NC |
60 | const struct attribute_spec arm_attribute_table[]; |
61 | ||
b76c3c4b PB |
62 | void (*arm_lang_output_object_attributes_hook)(void); |
63 | ||
d5b7b3ae | 64 | /* Forward function declarations. */ |
5848830f | 65 | static arm_stack_offsets *arm_get_frame_offsets (void); |
e32bac5b | 66 | static void arm_add_gc_roots (void); |
a406f566 MM |
67 | static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx, |
68 | HOST_WIDE_INT, rtx, rtx, int, int); | |
e32bac5b RE |
69 | static unsigned bit_count (unsigned long); |
70 | static int arm_address_register_rtx_p (rtx, int); | |
1e1ab407 | 71 | static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); |
5b3e6663 PB |
72 | static int thumb2_legitimate_index_p (enum machine_mode, rtx, int); |
73 | static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int); | |
74 | inline static int thumb1_index_register_rtx_p (rtx, int); | |
5848830f | 75 | static int thumb_far_jump_used_p (void); |
57934c39 | 76 | static bool thumb_force_lr_save (void); |
e32bac5b | 77 | static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); |
e32bac5b | 78 | static rtx emit_sfm (int, int); |
466e4b7a | 79 | static unsigned arm_size_return_regs (void); |
e32bac5b | 80 | static bool arm_assemble_integer (rtx, unsigned int, int); |
e32bac5b RE |
81 | static const char *fp_const_from_val (REAL_VALUE_TYPE *); |
82 | static arm_cc get_arm_condition_code (rtx); | |
e32bac5b RE |
83 | static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); |
84 | static rtx is_jump_table (rtx); | |
85 | static const char *output_multi_immediate (rtx *, const char *, const char *, | |
86 | int, HOST_WIDE_INT); | |
e32bac5b RE |
87 | static const char *shift_op (rtx, HOST_WIDE_INT *); |
88 | static struct machine_function *arm_init_machine_status (void); | |
c9ca9b88 | 89 | static void thumb_exit (FILE *, int); |
e32bac5b RE |
90 | static rtx is_jump_table (rtx); |
91 | static HOST_WIDE_INT get_jump_table_size (rtx); | |
92 | static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
93 | static Mnode *add_minipool_forward_ref (Mfix *); | |
94 | static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
95 | static Mnode *add_minipool_backward_ref (Mfix *); | |
96 | static void assign_minipool_offsets (Mfix *); | |
97 | static void arm_print_value (FILE *, rtx); | |
98 | static void dump_minipool (rtx); | |
99 | static int arm_barrier_cost (rtx); | |
100 | static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); | |
101 | static void push_minipool_barrier (rtx, HOST_WIDE_INT); | |
102 | static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, | |
103 | rtx); | |
104 | static void arm_reorg (void); | |
105 | static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); | |
e32bac5b RE |
106 | static unsigned long arm_compute_save_reg0_reg12_mask (void); |
107 | static unsigned long arm_compute_save_reg_mask (void); | |
108 | static unsigned long arm_isr_value (tree); | |
109 | static unsigned long arm_compute_func_type (void); | |
110 | static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); | |
111 | static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); | |
7bff66a7 | 112 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 | 113 | static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); |
7bff66a7 | 114 | #endif |
e32bac5b RE |
115 | static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); |
116 | static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); | |
5b3e6663 | 117 | static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT); |
3101faab | 118 | static int arm_comp_type_attributes (const_tree, const_tree); |
e32bac5b RE |
119 | static void arm_set_default_type_attributes (tree); |
120 | static int arm_adjust_cost (rtx, rtx, rtx, int); | |
e32bac5b RE |
121 | static int count_insns_for_constant (HOST_WIDE_INT, int); |
122 | static int arm_get_strip_length (int); | |
123 | static bool arm_function_ok_for_sibcall (tree, tree); | |
124 | static void arm_internal_label (FILE *, const char *, unsigned long); | |
125 | static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, | |
126 | tree); | |
127 | static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code); | |
21b5653c | 128 | static bool arm_size_rtx_costs (rtx, int, int, int *); |
9b66ebb1 PB |
129 | static bool arm_slowmul_rtx_costs (rtx, int, int, int *); |
130 | static bool arm_fastmul_rtx_costs (rtx, int, int, int *); | |
131 | static bool arm_xscale_rtx_costs (rtx, int, int, int *); | |
132 | static bool arm_9e_rtx_costs (rtx, int, int, int *); | |
e32bac5b RE |
133 | static int arm_address_cost (rtx); |
134 | static bool arm_memory_load_p (rtx); | |
135 | static bool arm_cirrus_insn_p (rtx); | |
136 | static void cirrus_reorg (rtx); | |
5a9335ef NC |
137 | static void arm_init_builtins (void); |
138 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
139 | static void arm_init_iwmmxt_builtins (void); | |
140 | static rtx safe_vector_operand (rtx, enum machine_mode); | |
141 | static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); | |
142 | static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); | |
143 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
a406f566 | 144 | static void emit_constant_insn (rtx cond, rtx pattern); |
d66437c5 | 145 | static rtx emit_set_insn (rtx, rtx); |
78a52f11 RH |
146 | static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
147 | tree, bool); | |
5a9335ef | 148 | |
7abc66b1 | 149 | #ifdef OBJECT_FORMAT_ELF |
9403b7f7 RS |
150 | static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; |
151 | static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; | |
7abc66b1 | 152 | #endif |
fb49053f | 153 | #ifndef ARM_PE |
e32bac5b | 154 | static void arm_encode_section_info (tree, rtx, int); |
fb49053f | 155 | #endif |
b12a00f1 RE |
156 | |
157 | static void arm_file_end (void); | |
6c6aa1af | 158 | static void arm_file_start (void); |
b12a00f1 | 159 | |
1cc9f5f5 KH |
160 | static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, |
161 | tree, int *, int); | |
8cd5a4e0 | 162 | static bool arm_pass_by_reference (CUMULATIVE_ARGS *, |
586de218 KG |
163 | enum machine_mode, const_tree, bool); |
164 | static bool arm_promote_prototypes (const_tree); | |
6b045785 | 165 | static bool arm_default_short_enums (void); |
13c1cd82 | 166 | static bool arm_align_anon_bitfield (void); |
586de218 KG |
167 | static bool arm_return_in_msb (const_tree); |
168 | static bool arm_must_pass_in_stack (enum machine_mode, const_tree); | |
23668cf7 | 169 | static bool arm_return_in_memory (const_tree, const_tree); |
617a1b71 PB |
170 | #ifdef TARGET_UNWIND_INFO |
171 | static void arm_unwind_emit (FILE *, rtx); | |
172 | static bool arm_output_ttype (rtx); | |
173 | #endif | |
5b3e6663 | 174 | static void arm_dwarf_handle_frame_unspec (const char *, rtx, int); |
c237e94a | 175 | |
4185ae53 PB |
176 | static tree arm_cxx_guard_type (void); |
177 | static bool arm_cxx_guard_mask_bit (void); | |
46e995e0 PB |
178 | static tree arm_get_cookie_size (tree); |
179 | static bool arm_cookie_has_size (void); | |
44d10c10 | 180 | static bool arm_cxx_cdtor_returns_this (void); |
505970fc | 181 | static bool arm_cxx_key_method_may_be_inline (void); |
1e731102 MM |
182 | static void arm_cxx_determine_class_data_visibility (tree); |
183 | static bool arm_cxx_class_data_always_comdat (void); | |
9f62c3e3 | 184 | static bool arm_cxx_use_aeabi_atexit (void); |
b3f8d95d | 185 | static void arm_init_libfuncs (void); |
c54c7322 | 186 | static bool arm_handle_option (size_t, const char *, int); |
67e6ba46 | 187 | static void arm_target_help (void); |
273a2526 | 188 | static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); |
d3585b76 DJ |
189 | static bool arm_cannot_copy_insn_p (rtx); |
190 | static bool arm_tls_symbol_p (rtx x); | |
bd4dc3cd | 191 | static int arm_issue_rate (void); |
afcc986d | 192 | static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
007e61c2 | 193 | static bool arm_allocate_stack_slots_for_args (void); |
d3585b76 | 194 | |
672a6f42 NB |
195 | \f |
196 | /* Initialize the GCC target structure. */ | |
b2ca3702 | 197 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
1d6e90ac | 198 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
672a6f42 NB |
199 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes |
200 | #endif | |
f3bb6135 | 201 | |
1d6e90ac | 202 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 203 | #define TARGET_ATTRIBUTE_TABLE arm_attribute_table |
672a6f42 | 204 | |
6c6aa1af PB |
205 | #undef TARGET_ASM_FILE_START |
206 | #define TARGET_ASM_FILE_START arm_file_start | |
b12a00f1 RE |
207 | #undef TARGET_ASM_FILE_END |
208 | #define TARGET_ASM_FILE_END arm_file_end | |
209 | ||
1d6e90ac | 210 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 211 | #define TARGET_ASM_ALIGNED_SI_OP NULL |
1d6e90ac | 212 | #undef TARGET_ASM_INTEGER |
301d03af | 213 | #define TARGET_ASM_INTEGER arm_assemble_integer |
301d03af | 214 | |
1d6e90ac | 215 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 NB |
216 | #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue |
217 | ||
1d6e90ac | 218 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
219 | #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue |
220 | ||
c54c7322 RS |
221 | #undef TARGET_DEFAULT_TARGET_FLAGS |
222 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG) | |
223 | #undef TARGET_HANDLE_OPTION | |
224 | #define TARGET_HANDLE_OPTION arm_handle_option | |
67e6ba46 NC |
225 | #undef TARGET_HELP |
226 | #define TARGET_HELP arm_target_help | |
c54c7322 | 227 | |
1d6e90ac | 228 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
8d8e52be JM |
229 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes |
230 | ||
1d6e90ac | 231 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
8d8e52be JM |
232 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes |
233 | ||
1d6e90ac | 234 | #undef TARGET_SCHED_ADJUST_COST |
c237e94a ZW |
235 | #define TARGET_SCHED_ADJUST_COST arm_adjust_cost |
236 | ||
fb49053f RH |
237 | #undef TARGET_ENCODE_SECTION_INFO |
238 | #ifdef ARM_PE | |
239 | #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info | |
240 | #else | |
241 | #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info | |
242 | #endif | |
243 | ||
5a9335ef | 244 | #undef TARGET_STRIP_NAME_ENCODING |
772c5265 RH |
245 | #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding |
246 | ||
5a9335ef | 247 | #undef TARGET_ASM_INTERNAL_LABEL |
4977bab6 ZW |
248 | #define TARGET_ASM_INTERNAL_LABEL arm_internal_label |
249 | ||
5a9335ef | 250 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
4977bab6 ZW |
251 | #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall |
252 | ||
5a9335ef | 253 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
c590b625 | 254 | #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk |
5a9335ef | 255 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3961e8fe | 256 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
c590b625 | 257 | |
9b66ebb1 | 258 | /* This will be overridden in arm_override_options. */ |
5a9335ef | 259 | #undef TARGET_RTX_COSTS |
9b66ebb1 | 260 | #define TARGET_RTX_COSTS arm_slowmul_rtx_costs |
5a9335ef | 261 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 262 | #define TARGET_ADDRESS_COST arm_address_cost |
3c50106f | 263 | |
273a2526 RS |
264 | #undef TARGET_SHIFT_TRUNCATION_MASK |
265 | #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask | |
f676971a EC |
266 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
267 | #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p | |
268 | ||
5a9335ef | 269 | #undef TARGET_MACHINE_DEPENDENT_REORG |
18dbd950 RS |
270 | #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg |
271 | ||
5a9335ef NC |
272 | #undef TARGET_INIT_BUILTINS |
273 | #define TARGET_INIT_BUILTINS arm_init_builtins | |
274 | #undef TARGET_EXPAND_BUILTIN | |
275 | #define TARGET_EXPAND_BUILTIN arm_expand_builtin | |
276 | ||
b3f8d95d MM |
277 | #undef TARGET_INIT_LIBFUNCS |
278 | #define TARGET_INIT_LIBFUNCS arm_init_libfuncs | |
279 | ||
f9ba5949 | 280 | #undef TARGET_PROMOTE_FUNCTION_ARGS |
586de218 | 281 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true |
d4453b7a | 282 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
586de218 | 283 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true |
f9ba5949 | 284 | #undef TARGET_PROMOTE_PROTOTYPES |
70301b45 | 285 | #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes |
8cd5a4e0 RH |
286 | #undef TARGET_PASS_BY_REFERENCE |
287 | #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference | |
78a52f11 RH |
288 | #undef TARGET_ARG_PARTIAL_BYTES |
289 | #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes | |
f9ba5949 | 290 | |
1cc9f5f5 KH |
291 | #undef TARGET_SETUP_INCOMING_VARARGS |
292 | #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs | |
293 | ||
007e61c2 PB |
294 | #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS |
295 | #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args | |
296 | ||
6b045785 PB |
297 | #undef TARGET_DEFAULT_SHORT_ENUMS |
298 | #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums | |
299 | ||
13c1cd82 PB |
300 | #undef TARGET_ALIGN_ANON_BITFIELD |
301 | #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield | |
302 | ||
c2a64439 PB |
303 | #undef TARGET_NARROW_VOLATILE_BITFIELD |
304 | #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false | |
305 | ||
4185ae53 PB |
306 | #undef TARGET_CXX_GUARD_TYPE |
307 | #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type | |
308 | ||
309 | #undef TARGET_CXX_GUARD_MASK_BIT | |
310 | #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit | |
311 | ||
46e995e0 PB |
312 | #undef TARGET_CXX_GET_COOKIE_SIZE |
313 | #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size | |
314 | ||
315 | #undef TARGET_CXX_COOKIE_HAS_SIZE | |
316 | #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size | |
317 | ||
44d10c10 PB |
318 | #undef TARGET_CXX_CDTOR_RETURNS_THIS |
319 | #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this | |
320 | ||
505970fc MM |
321 | #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE |
322 | #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline | |
323 | ||
9f62c3e3 PB |
324 | #undef TARGET_CXX_USE_AEABI_ATEXIT |
325 | #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit | |
326 | ||
1e731102 MM |
327 | #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY |
328 | #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \ | |
329 | arm_cxx_determine_class_data_visibility | |
330 | ||
331 | #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT | |
332 | #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat | |
505970fc | 333 | |
866af8a9 JB |
334 | #undef TARGET_RETURN_IN_MSB |
335 | #define TARGET_RETURN_IN_MSB arm_return_in_msb | |
336 | ||
23668cf7 CLT |
337 | #undef TARGET_RETURN_IN_MEMORY |
338 | #define TARGET_RETURN_IN_MEMORY arm_return_in_memory | |
339 | ||
866af8a9 JB |
340 | #undef TARGET_MUST_PASS_IN_STACK |
341 | #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack | |
342 | ||
617a1b71 PB |
343 | #ifdef TARGET_UNWIND_INFO |
344 | #undef TARGET_UNWIND_EMIT | |
345 | #define TARGET_UNWIND_EMIT arm_unwind_emit | |
346 | ||
347 | /* EABI unwinding tables use a different format for the typeinfo tables. */ | |
348 | #undef TARGET_ASM_TTYPE | |
349 | #define TARGET_ASM_TTYPE arm_output_ttype | |
350 | ||
351 | #undef TARGET_ARM_EABI_UNWINDER | |
352 | #define TARGET_ARM_EABI_UNWINDER true | |
353 | #endif /* TARGET_UNWIND_INFO */ | |
354 | ||
5b3e6663 PB |
355 | #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC |
356 | #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec | |
357 | ||
d3585b76 DJ |
358 | #undef TARGET_CANNOT_COPY_INSN_P |
359 | #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p | |
360 | ||
361 | #ifdef HAVE_AS_TLS | |
362 | #undef TARGET_HAVE_TLS | |
363 | #define TARGET_HAVE_TLS true | |
364 | #endif | |
365 | ||
366 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
8426b956 | 367 | #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem |
d3585b76 | 368 | |
bd4dc3cd PB |
369 | #undef TARGET_SCHED_ISSUE_RATE |
370 | #define TARGET_SCHED_ISSUE_RATE arm_issue_rate | |
371 | ||
608063c3 JB |
372 | #undef TARGET_MANGLE_TYPE |
373 | #define TARGET_MANGLE_TYPE arm_mangle_type | |
374 | ||
afcc986d JM |
375 | #ifdef HAVE_AS_TLS |
376 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
377 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel | |
378 | #endif | |
379 | ||
f6897b10 | 380 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 381 | \f |
c7319d87 RE |
382 | /* Obstack for minipool constant handling. */ |
383 | static struct obstack minipool_obstack; | |
1d6e90ac | 384 | static char * minipool_startobj; |
c7319d87 | 385 | |
1d6e90ac NC |
386 | /* The maximum number of insns skipped which |
387 | will be conditionalised if possible. */ | |
c27ba912 DM |
388 | static int max_insns_skipped = 5; |
389 | ||
390 | extern FILE * asm_out_file; | |
391 | ||
6354dc9b | 392 | /* True if we are currently building a constant table. */ |
13bd191d PB |
393 | int making_const_table; |
394 | ||
60d0536b | 395 | /* Define the information needed to generate branch insns. This is |
6354dc9b | 396 | stored from the compare operation. */ |
ff9940b0 | 397 | rtx arm_compare_op0, arm_compare_op1; |
ff9940b0 | 398 | |
9b66ebb1 PB |
399 | /* The processor for which instructions should be scheduled. */ |
400 | enum processor_type arm_tune = arm_none; | |
401 | ||
2f8e468b | 402 | /* The default processor used if not overridden by commandline. */ |
6c6aa1af PB |
403 | static enum processor_type arm_default_cpu = arm_none; |
404 | ||
9b66ebb1 PB |
405 | /* Which floating point model to use. */ |
406 | enum arm_fp_model arm_fp_model; | |
bee06f3d | 407 | |
9b66ebb1 | 408 | /* Which floating point hardware is available. */ |
29ad9694 | 409 | enum fputype arm_fpu_arch; |
b111229a | 410 | |
9b66ebb1 PB |
411 | /* Which floating point hardware to schedule for. */ |
412 | enum fputype arm_fpu_tune; | |
413 | ||
414 | /* Whether to use floating point hardware. */ | |
415 | enum float_abi_type arm_float_abi; | |
416 | ||
5848830f PB |
417 | /* Which ABI to use. */ |
418 | enum arm_abi_type arm_abi; | |
419 | ||
d3585b76 DJ |
420 | /* Which thread pointer model to use. */ |
421 | enum arm_tp_type target_thread_pointer = TP_AUTO; | |
422 | ||
b355a481 | 423 | /* Used to parse -mstructure_size_boundary command line option. */ |
723ae7c1 | 424 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 425 | |
b12a00f1 | 426 | /* Used for Thumb call_via trampolines. */ |
57ecec57 | 427 | rtx thumb_call_via_label[14]; |
b12a00f1 RE |
428 | static int thumb_call_reg_needed; |
429 | ||
aec3cfba | 430 | /* Bit values used to identify processor capabilities. */ |
62b10bbc | 431 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
9b66ebb1 | 432 | #define FL_ARCH3M (1 << 1) /* Extended multiply */ |
62b10bbc NC |
433 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ |
434 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
435 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
436 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
437 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
438 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
439 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
6bc82793 | 440 | #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ |
d19fb8e3 | 441 | #define FL_XSCALE (1 << 10) /* XScale */ |
9b6b54e2 | 442 | #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ |
9b66ebb1 | 443 | #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds |
81f9037c MM |
444 | media instructions. */ |
445 | #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ | |
abac3b49 RE |
446 | #define FL_WBUF (1 << 14) /* Schedule for write buffer ops. |
447 | Note: ARM6 & 7 derivatives only. */ | |
d3585b76 | 448 | #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ |
5b3e6663 PB |
449 | #define FL_THUMB2 (1 << 16) /* Thumb-2. */ |
450 | #define FL_NOTM (1 << 17) /* Instructions not present in the 'M' | |
451 | profile. */ | |
7a085dce | 452 | #define FL_DIV (1 << 18) /* Hardware divide. */ |
f1adb0a9 | 453 | #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ |
88f77cba | 454 | #define FL_NEON (1 << 20) /* Neon instructions. */ |
aec3cfba | 455 | |
9b66ebb1 PB |
456 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ |
457 | ||
5b3e6663 PB |
458 | #define FL_FOR_ARCH2 FL_NOTM |
459 | #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) | |
78011587 PB |
460 | #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) |
461 | #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) | |
462 | #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) | |
463 | #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) | |
464 | #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) | |
465 | #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) | |
466 | #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) | |
467 | #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE | |
468 | #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) | |
469 | #define FL_FOR_ARCH6J FL_FOR_ARCH6 | |
d3585b76 | 470 | #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) |
fa91adc6 | 471 | #define FL_FOR_ARCH6Z FL_FOR_ARCH6 |
d3585b76 | 472 | #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K |
5b3e6663 | 473 | #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) |
bf98ec6c | 474 | #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) |
5b3e6663 PB |
475 | #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM) |
476 | #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM) | |
477 | #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) | |
478 | #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) | |
78011587 | 479 | |
1d6e90ac NC |
480 | /* The bits in this mask specify which |
481 | instructions we are allowed to generate. */ | |
0977774b | 482 | static unsigned long insn_flags = 0; |
d5b7b3ae | 483 | |
aec3cfba | 484 | /* The bits in this mask specify which instruction scheduling options should |
9b66ebb1 | 485 | be used. */ |
0977774b | 486 | static unsigned long tune_flags = 0; |
aec3cfba NC |
487 | |
488 | /* The following are used in the arm.md file as equivalents to bits | |
489 | in the above two flag variables. */ | |
490 | ||
9b66ebb1 PB |
491 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
492 | int arm_arch3m = 0; | |
2b835d68 | 493 | |
6354dc9b | 494 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
495 | int arm_arch4 = 0; |
496 | ||
68d560d4 RE |
497 | /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ |
498 | int arm_arch4t = 0; | |
499 | ||
6354dc9b | 500 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
501 | int arm_arch5 = 0; |
502 | ||
b15bca31 RE |
503 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
504 | int arm_arch5e = 0; | |
505 | ||
9b66ebb1 PB |
506 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
507 | int arm_arch6 = 0; | |
508 | ||
d3585b76 DJ |
509 | /* Nonzero if this chip supports the ARM 6K extensions. */ |
510 | int arm_arch6k = 0; | |
511 | ||
5b3e6663 PB |
512 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
513 | int arm_arch_notm = 0; | |
514 | ||
aec3cfba | 515 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
516 | int arm_ld_sched = 0; |
517 | ||
518 | /* Nonzero if this chip is a StrongARM. */ | |
abac3b49 | 519 | int arm_tune_strongarm = 0; |
f5a1b0d2 | 520 | |
78011587 PB |
521 | /* Nonzero if this chip is a Cirrus variant. */ |
522 | int arm_arch_cirrus = 0; | |
523 | ||
5a9335ef NC |
524 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ |
525 | int arm_arch_iwmmxt = 0; | |
526 | ||
d19fb8e3 | 527 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
528 | int arm_arch_xscale = 0; |
529 | ||
530 | /* Nonzero if tuning for XScale */ | |
531 | int arm_tune_xscale = 0; | |
d19fb8e3 | 532 | |
e0b92319 | 533 | /* Nonzero if we want to tune for stores that access the write-buffer. |
c5d34bb2 | 534 | This typically means an ARM6 or ARM7 with MMU or MPU. */ |
abac3b49 | 535 | int arm_tune_wbuf = 0; |
b111229a | 536 | |
0616531f RE |
537 | /* Nonzero if generating Thumb instructions. */ |
538 | int thumb_code = 0; | |
539 | ||
2ad4dcf9 | 540 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 541 | preprocessor. |
2ad4dcf9 RE |
542 | XXX This is a bit of a hack, it's intended to help work around |
543 | problems in GLD which doesn't understand that armv5t code is | |
544 | interworking clean. */ | |
545 | int arm_cpp_interwork = 0; | |
546 | ||
5b3e6663 PB |
547 | /* Nonzero if chip supports Thumb 2. */ |
548 | int arm_arch_thumb2; | |
549 | ||
550 | /* Nonzero if chip supports integer division instruction. */ | |
551 | int arm_arch_hwdiv; | |
552 | ||
cce8749e CH |
553 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we |
554 | must report the mode of the memory reference from PRINT_OPERAND to | |
555 | PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 556 | enum machine_mode output_memory_reference_mode; |
cce8749e | 557 | |
32de079a | 558 | /* The register number to be used for the PIC offset register. */ |
020a4035 | 559 | unsigned arm_pic_register = INVALID_REGNUM; |
32de079a | 560 | |
ff9940b0 | 561 | /* Set to 1 when a return insn is output, this means that the epilogue |
6354dc9b | 562 | is not needed. */ |
d5b7b3ae | 563 | int return_used_this_function; |
ff9940b0 | 564 | |
aec3cfba NC |
565 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
566 | the next function. */ | |
4b632bf1 RE |
567 | static int after_arm_reorg = 0; |
568 | ||
aec3cfba | 569 | /* The maximum number of insns to be used when loading a constant. */ |
2b835d68 RE |
570 | static int arm_constant_limit = 3; |
571 | ||
cce8749e CH |
572 | /* For an explanation of these variables, see final_prescan_insn below. */ |
573 | int arm_ccfsm_state; | |
5b3e6663 | 574 | /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */ |
84ed5e79 | 575 | enum arm_cond_code arm_current_cc; |
cce8749e CH |
576 | rtx arm_target_insn; |
577 | int arm_target_label; | |
5b3e6663 PB |
578 | /* The number of conditionally executed insns, including the current insn. */ |
579 | int arm_condexec_count = 0; | |
580 | /* A bitmask specifying the patterns for the IT block. | |
581 | Zero means do not output an IT block before this insn. */ | |
582 | int arm_condexec_mask = 0; | |
583 | /* The number of bits used in arm_condexec_mask. */ | |
584 | int arm_condexec_masklen = 0; | |
9997d19d RE |
585 | |
586 | /* The condition codes of the ARM, and the inverse function. */ | |
1d6e90ac | 587 | static const char * const arm_condition_codes[] = |
9997d19d RE |
588 | { |
589 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
590 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
591 | }; | |
592 | ||
5b3e6663 | 593 | #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl") |
f5a1b0d2 | 594 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
5b3e6663 PB |
595 | |
596 | #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \ | |
597 | | (1 << SP_REGNUM) | (1 << PC_REGNUM) \ | |
598 | | (1 << PIC_OFFSET_TABLE_REGNUM))) | |
2b835d68 | 599 | \f |
6354dc9b | 600 | /* Initialization code. */ |
2b835d68 | 601 | |
2b835d68 RE |
602 | struct processors |
603 | { | |
8b60264b | 604 | const char *const name; |
9b66ebb1 | 605 | enum processor_type core; |
78011587 | 606 | const char *arch; |
0977774b | 607 | const unsigned long flags; |
9b66ebb1 | 608 | bool (* rtx_costs) (rtx, int, int, int *); |
2b835d68 RE |
609 | }; |
610 | ||
611 | /* Not all of these give usefully different compilation alternatives, | |
612 | but there is no simple way of generalizing them. */ | |
8b60264b | 613 | static const struct processors all_cores[] = |
f5a1b0d2 NC |
614 | { |
615 | /* ARM Cores */ | |
d98a72fd RE |
616 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ |
617 | {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, | |
9b66ebb1 PB |
618 | #include "arm-cores.def" |
619 | #undef ARM_CORE | |
78011587 | 620 | {NULL, arm_none, NULL, 0, NULL} |
f5a1b0d2 NC |
621 | }; |
622 | ||
8b60264b | 623 | static const struct processors all_architectures[] = |
2b835d68 | 624 | { |
f5a1b0d2 | 625 | /* ARM Architectures */ |
9b66ebb1 PB |
626 | /* We don't specify rtx_costs here as it will be figured out |
627 | from the core. */ | |
f676971a | 628 | |
78011587 PB |
629 | {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, |
630 | {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, | |
631 | {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, | |
632 | {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, | |
633 | {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, | |
b111229a RE |
634 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
635 | implementations that support it, so we will leave it out for now. */ | |
78011587 PB |
636 | {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, |
637 | {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, | |
638 | {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, | |
639 | {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, | |
640 | {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, | |
641 | {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, | |
642 | {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, | |
fa91adc6 PB |
643 | {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL}, |
644 | {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL}, | |
645 | {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL}, | |
5b3e6663 | 646 | {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL}, |
bf98ec6c | 647 | {"armv6-m", cortexm1, "6M", FL_FOR_ARCH6M, NULL}, |
5b3e6663 PB |
648 | {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL}, |
649 | {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL}, | |
650 | {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL}, | |
651 | {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL}, | |
78011587 PB |
652 | {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, |
653 | {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, | |
654 | {NULL, arm_none, NULL, 0 , NULL} | |
f5a1b0d2 NC |
655 | }; |
656 | ||
c54c7322 RS |
657 | struct arm_cpu_select |
658 | { | |
659 | const char * string; | |
660 | const char * name; | |
661 | const struct processors * processors; | |
662 | }; | |
663 | ||
9a9f7594 | 664 | /* This is a magic structure. The 'string' field is magically filled in |
f5a1b0d2 NC |
665 | with a pointer to the value specified by the user on the command line |
666 | assuming that the user has specified such a value. */ | |
667 | ||
c54c7322 | 668 | static struct arm_cpu_select arm_select[] = |
f5a1b0d2 | 669 | { |
f676971a | 670 | /* string name processors */ |
f5a1b0d2 NC |
671 | { NULL, "-mcpu=", all_cores }, |
672 | { NULL, "-march=", all_architectures }, | |
673 | { NULL, "-mtune=", all_cores } | |
2b835d68 RE |
674 | }; |
675 | ||
e6fffade RE |
676 | /* Defines representing the indexes into the above table. */ |
677 | #define ARM_OPT_SET_CPU 0 | |
678 | #define ARM_OPT_SET_ARCH 1 | |
679 | #define ARM_OPT_SET_TUNE 2 | |
78011587 | 680 | |
afc0a4ba | 681 | /* The name of the preprocessor macro to define for this architecture. */ |
78011587 PB |
682 | |
683 | char arm_arch_name[] = "__ARM_ARCH_0UNK__"; | |
684 | ||
9b66ebb1 PB |
685 | struct fpu_desc |
686 | { | |
687 | const char * name; | |
688 | enum fputype fpu; | |
689 | }; | |
690 | ||
691 | ||
56f42830 | 692 | /* Available values for -mfpu=. */ |
9b66ebb1 PB |
693 | |
694 | static const struct fpu_desc all_fpus[] = | |
695 | { | |
696 | {"fpa", FPUTYPE_FPA}, | |
697 | {"fpe2", FPUTYPE_FPA_EMU2}, | |
698 | {"fpe3", FPUTYPE_FPA_EMU2}, | |
699 | {"maverick", FPUTYPE_MAVERICK}, | |
f1adb0a9 JB |
700 | {"vfp", FPUTYPE_VFP}, |
701 | {"vfp3", FPUTYPE_VFP3}, | |
88f77cba | 702 | {"neon", FPUTYPE_NEON} |
9b66ebb1 PB |
703 | }; |
704 | ||
705 | ||
706 | /* Floating point models used by the different hardware. | |
707 | See fputype in arm.h. */ | |
708 | ||
709 | static const enum fputype fp_model_for_fpu[] = | |
710 | { | |
711 | /* No FP hardware. */ | |
712 | ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */ | |
713 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */ | |
714 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */ | |
715 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */ | |
716 | ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */ | |
f1adb0a9 | 717 | ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */ |
88f77cba JB |
718 | ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3 */ |
719 | ARM_FP_MODEL_VFP /* FPUTYPE_NEON */ | |
9b66ebb1 PB |
720 | }; |
721 | ||
722 | ||
723 | struct float_abi | |
724 | { | |
725 | const char * name; | |
726 | enum float_abi_type abi_type; | |
727 | }; | |
728 | ||
729 | ||
730 | /* Available values for -mfloat-abi=. */ | |
731 | ||
732 | static const struct float_abi all_float_abis[] = | |
733 | { | |
734 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
735 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
736 | {"hard", ARM_FLOAT_ABI_HARD} | |
737 | }; | |
738 | ||
739 | ||
5848830f PB |
740 | struct abi_name |
741 | { | |
742 | const char *name; | |
743 | enum arm_abi_type abi_type; | |
744 | }; | |
745 | ||
746 | ||
747 | /* Available values for -mabi=. */ | |
748 | ||
749 | static const struct abi_name arm_all_abis[] = | |
750 | { | |
751 | {"apcs-gnu", ARM_ABI_APCS}, | |
752 | {"atpcs", ARM_ABI_ATPCS}, | |
753 | {"aapcs", ARM_ABI_AAPCS}, | |
077fc835 KH |
754 | {"iwmmxt", ARM_ABI_IWMMXT}, |
755 | {"aapcs-linux", ARM_ABI_AAPCS_LINUX} | |
5848830f PB |
756 | }; |
757 | ||
d3585b76 DJ |
758 | /* Supported TLS relocations. */ |
759 | ||
760 | enum tls_reloc { | |
761 | TLS_GD32, | |
762 | TLS_LDM32, | |
763 | TLS_LDO32, | |
764 | TLS_IE32, | |
765 | TLS_LE32 | |
766 | }; | |
767 | ||
d66437c5 RE |
768 | /* Emit an insn that's a simple single-set. Both the operands must be known |
769 | to be valid. */ | |
770 | inline static rtx | |
771 | emit_set_insn (rtx x, rtx y) | |
772 | { | |
773 | return emit_insn (gen_rtx_SET (VOIDmode, x, y)); | |
774 | } | |
775 | ||
0977774b JT |
776 | /* Return the number of bits set in VALUE. */ |
777 | static unsigned | |
e32bac5b | 778 | bit_count (unsigned long value) |
aec3cfba | 779 | { |
d5b7b3ae | 780 | unsigned long count = 0; |
f676971a | 781 | |
aec3cfba NC |
782 | while (value) |
783 | { | |
0977774b JT |
784 | count++; |
785 | value &= value - 1; /* Clear the least-significant set bit. */ | |
aec3cfba NC |
786 | } |
787 | ||
788 | return count; | |
789 | } | |
790 | ||
c112cf2b | 791 | /* Set up library functions unique to ARM. */ |
b3f8d95d MM |
792 | |
793 | static void | |
794 | arm_init_libfuncs (void) | |
795 | { | |
796 | /* There are no special library functions unless we are using the | |
797 | ARM BPABI. */ | |
798 | if (!TARGET_BPABI) | |
799 | return; | |
800 | ||
801 | /* The functions below are described in Section 4 of the "Run-Time | |
802 | ABI for the ARM architecture", Version 1.0. */ | |
803 | ||
804 | /* Double-precision floating-point arithmetic. Table 2. */ | |
805 | set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd"); | |
806 | set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv"); | |
807 | set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul"); | |
808 | set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg"); | |
809 | set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub"); | |
810 | ||
c112cf2b | 811 | /* Double-precision comparisons. Table 3. */ |
b3f8d95d MM |
812 | set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq"); |
813 | set_optab_libfunc (ne_optab, DFmode, NULL); | |
814 | set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt"); | |
815 | set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple"); | |
816 | set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge"); | |
817 | set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt"); | |
818 | set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun"); | |
819 | ||
820 | /* Single-precision floating-point arithmetic. Table 4. */ | |
821 | set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd"); | |
822 | set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv"); | |
823 | set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul"); | |
824 | set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg"); | |
825 | set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub"); | |
f676971a | 826 | |
c112cf2b | 827 | /* Single-precision comparisons. Table 5. */ |
b3f8d95d MM |
828 | set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq"); |
829 | set_optab_libfunc (ne_optab, SFmode, NULL); | |
830 | set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt"); | |
831 | set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple"); | |
832 | set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge"); | |
833 | set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt"); | |
834 | set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun"); | |
835 | ||
836 | /* Floating-point to integer conversions. Table 6. */ | |
837 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz"); | |
838 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz"); | |
839 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz"); | |
840 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz"); | |
841 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz"); | |
842 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz"); | |
843 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz"); | |
844 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz"); | |
845 | ||
846 | /* Conversions between floating types. Table 7. */ | |
847 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f"); | |
848 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d"); | |
849 | ||
c112cf2b | 850 | /* Integer to floating-point conversions. Table 8. */ |
b3f8d95d MM |
851 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d"); |
852 | set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d"); | |
853 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d"); | |
854 | set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d"); | |
855 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f"); | |
856 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f"); | |
857 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f"); | |
858 | set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f"); | |
859 | ||
860 | /* Long long. Table 9. */ | |
861 | set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul"); | |
862 | set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod"); | |
863 | set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod"); | |
864 | set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl"); | |
865 | set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr"); | |
866 | set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr"); | |
867 | set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp"); | |
868 | set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp"); | |
869 | ||
870 | /* Integer (32/32->32) division. \S 4.3.1. */ | |
871 | set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod"); | |
872 | set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod"); | |
873 | ||
874 | /* The divmod functions are designed so that they can be used for | |
875 | plain division, even though they return both the quotient and the | |
876 | remainder. The quotient is returned in the usual location (i.e., | |
877 | r0 for SImode, {r0, r1} for DImode), just as would be expected | |
878 | for an ordinary division routine. Because the AAPCS calling | |
879 | conventions specify that all of { r0, r1, r2, r3 } are | |
880 | callee-saved registers, there is no need to tell the compiler | |
881 | explicitly that those registers are clobbered by these | |
882 | routines. */ | |
883 | set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod"); | |
884 | set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod"); | |
e993ba8f DJ |
885 | |
886 | /* For SImode division the ABI provides div-without-mod routines, | |
887 | which are faster. */ | |
888 | set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv"); | |
889 | set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv"); | |
01c19d47 PB |
890 | |
891 | /* We don't have mod libcalls. Fortunately gcc knows how to use the | |
892 | divmod libcalls instead. */ | |
893 | set_optab_libfunc (smod_optab, DImode, NULL); | |
894 | set_optab_libfunc (umod_optab, DImode, NULL); | |
895 | set_optab_libfunc (smod_optab, SImode, NULL); | |
896 | set_optab_libfunc (umod_optab, SImode, NULL); | |
b3f8d95d MM |
897 | } |
898 | ||
c54c7322 RS |
899 | /* Implement TARGET_HANDLE_OPTION. */ |
900 | ||
901 | static bool | |
902 | arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
903 | { | |
904 | switch (code) | |
905 | { | |
c54c7322 RS |
906 | case OPT_march_: |
907 | arm_select[1].string = arg; | |
908 | return true; | |
909 | ||
910 | case OPT_mcpu_: | |
911 | arm_select[0].string = arg; | |
912 | return true; | |
913 | ||
c54c7322 RS |
914 | case OPT_mhard_float: |
915 | target_float_abi_name = "hard"; | |
916 | return true; | |
917 | ||
c54c7322 RS |
918 | case OPT_msoft_float: |
919 | target_float_abi_name = "soft"; | |
920 | return true; | |
921 | ||
c54c7322 RS |
922 | case OPT_mtune_: |
923 | arm_select[2].string = arg; | |
924 | return true; | |
925 | ||
926 | default: | |
927 | return true; | |
928 | } | |
929 | } | |
930 | ||
67e6ba46 NC |
931 | static void |
932 | arm_target_help (void) | |
933 | { | |
934 | int i; | |
935 | static int columns = 0; | |
936 | int remaining; | |
937 | ||
938 | /* If we have not done so already, obtain the desired maximum width of | |
939 | the output. Note - this is a duplication of the code at the start of | |
940 | gcc/opts.c:print_specific_help() - the two copies should probably be | |
941 | replaced by a single function. */ | |
942 | if (columns == 0) | |
943 | { | |
944 | const char *p; | |
945 | ||
946 | GET_ENVIRONMENT (p, "COLUMNS"); | |
947 | if (p != NULL) | |
948 | { | |
949 | int value = atoi (p); | |
950 | ||
951 | if (value > 0) | |
952 | columns = value; | |
953 | } | |
954 | ||
955 | if (columns == 0) | |
956 | /* Use a reasonable default. */ | |
957 | columns = 80; | |
958 | } | |
959 | ||
960 | printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"); | |
961 | ||
962 | /* The - 2 is because we know that the last entry in the array is NULL. */ | |
963 | i = ARRAY_SIZE (all_cores) - 2; | |
964 | gcc_assert (i > 0); | |
965 | printf (" %s", all_cores[i].name); | |
966 | remaining = columns - (strlen (all_cores[i].name) + 4); | |
967 | gcc_assert (remaining >= 0); | |
968 | ||
969 | while (i--) | |
970 | { | |
971 | int len = strlen (all_cores[i].name); | |
972 | ||
973 | if (remaining > len + 2) | |
974 | { | |
975 | printf (", %s", all_cores[i].name); | |
976 | remaining -= len + 2; | |
977 | } | |
978 | else | |
979 | { | |
980 | if (remaining > 0) | |
981 | printf (","); | |
982 | printf ("\n %s", all_cores[i].name); | |
983 | remaining = columns - (len + 4); | |
984 | } | |
985 | } | |
986 | ||
987 | printf ("\n\n Known ARM architectures (for use with the -march= option):\n"); | |
988 | ||
989 | i = ARRAY_SIZE (all_architectures) - 2; | |
990 | gcc_assert (i > 0); | |
991 | ||
992 | printf (" %s", all_architectures[i].name); | |
993 | remaining = columns - (strlen (all_architectures[i].name) + 4); | |
994 | gcc_assert (remaining >= 0); | |
995 | ||
996 | while (i--) | |
997 | { | |
998 | int len = strlen (all_architectures[i].name); | |
999 | ||
1000 | if (remaining > len + 2) | |
1001 | { | |
1002 | printf (", %s", all_architectures[i].name); | |
1003 | remaining -= len + 2; | |
1004 | } | |
1005 | else | |
1006 | { | |
1007 | if (remaining > 0) | |
1008 | printf (","); | |
1009 | printf ("\n %s", all_architectures[i].name); | |
1010 | remaining = columns - (len + 4); | |
1011 | } | |
1012 | } | |
1013 | printf ("\n"); | |
1014 | ||
1015 | } | |
1016 | ||
2b835d68 RE |
1017 | /* Fix up any incompatible options that the user has specified. |
1018 | This has now turned into a maze. */ | |
1019 | void | |
e32bac5b | 1020 | arm_override_options (void) |
2b835d68 | 1021 | { |
ed4c4348 | 1022 | unsigned i; |
e6fffade | 1023 | enum processor_type target_arch_cpu = arm_none; |
9b66ebb1 | 1024 | |
f5a1b0d2 | 1025 | /* Set up the flags based on the cpu/architecture selected by the user. */ |
b6a1cbae | 1026 | for (i = ARRAY_SIZE (arm_select); i--;) |
bd9c7e23 | 1027 | { |
f5a1b0d2 | 1028 | struct arm_cpu_select * ptr = arm_select + i; |
f676971a | 1029 | |
f5a1b0d2 | 1030 | if (ptr->string != NULL && ptr->string[0] != '\0') |
bd9c7e23 | 1031 | { |
13bd191d | 1032 | const struct processors * sel; |
bd9c7e23 | 1033 | |
5895f793 | 1034 | for (sel = ptr->processors; sel->name != NULL; sel++) |
f5a1b0d2 | 1035 | if (streq (ptr->string, sel->name)) |
bd9c7e23 | 1036 | { |
78011587 | 1037 | /* Set the architecture define. */ |
e6fffade | 1038 | if (i != ARM_OPT_SET_TUNE) |
78011587 PB |
1039 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); |
1040 | ||
9b66ebb1 PB |
1041 | /* Determine the processor core for which we should |
1042 | tune code-generation. */ | |
1043 | if (/* -mcpu= is a sensible default. */ | |
e6fffade | 1044 | i == ARM_OPT_SET_CPU |
9b66ebb1 | 1045 | /* -mtune= overrides -mcpu= and -march=. */ |
e6fffade | 1046 | || i == ARM_OPT_SET_TUNE) |
9b66ebb1 PB |
1047 | arm_tune = (enum processor_type) (sel - ptr->processors); |
1048 | ||
e6fffade RE |
1049 | /* Remember the CPU associated with this architecture. |
1050 | If no other option is used to set the CPU type, | |
1051 | we'll use this to guess the most suitable tuning | |
1052 | options. */ | |
1053 | if (i == ARM_OPT_SET_ARCH) | |
1054 | target_arch_cpu = sel->core; | |
e0b92319 | 1055 | |
e6fffade | 1056 | if (i != ARM_OPT_SET_TUNE) |
b111229a | 1057 | { |
aec3cfba NC |
1058 | /* If we have been given an architecture and a processor |
1059 | make sure that they are compatible. We only generate | |
1060 | a warning though, and we prefer the CPU over the | |
6354dc9b | 1061 | architecture. */ |
aec3cfba | 1062 | if (insn_flags != 0 && (insn_flags ^ sel->flags)) |
d4ee4d25 | 1063 | warning (0, "switch -mcpu=%s conflicts with -march= switch", |
aec3cfba | 1064 | ptr->string); |
f676971a | 1065 | |
aec3cfba | 1066 | insn_flags = sel->flags; |
b111229a | 1067 | } |
f676971a | 1068 | |
bd9c7e23 RE |
1069 | break; |
1070 | } | |
1071 | ||
1072 | if (sel->name == NULL) | |
1073 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
1074 | } | |
1075 | } | |
f676971a | 1076 | |
e6fffade RE |
1077 | /* Guess the tuning options from the architecture if necessary. */ |
1078 | if (arm_tune == arm_none) | |
1079 | arm_tune = target_arch_cpu; | |
1080 | ||
f5a1b0d2 | 1081 | /* If the user did not specify a processor, choose one for them. */ |
aec3cfba | 1082 | if (insn_flags == 0) |
f5a1b0d2 | 1083 | { |
8b60264b | 1084 | const struct processors * sel; |
aec3cfba | 1085 | unsigned int sought; |
78011587 | 1086 | enum processor_type cpu; |
aec3cfba | 1087 | |
78011587 PB |
1088 | cpu = TARGET_CPU_DEFAULT; |
1089 | if (cpu == arm_none) | |
1090 | { | |
1091 | #ifdef SUBTARGET_CPU_DEFAULT | |
1092 | /* Use the subtarget default CPU if none was specified by | |
1093 | configure. */ | |
1094 | cpu = SUBTARGET_CPU_DEFAULT; | |
1095 | #endif | |
1096 | /* Default to ARM6. */ | |
1097 | if (cpu == arm_none) | |
1098 | cpu = arm6; | |
1099 | } | |
1100 | sel = &all_cores[cpu]; | |
aec3cfba NC |
1101 | |
1102 | insn_flags = sel->flags; | |
9b66ebb1 | 1103 | |
aec3cfba NC |
1104 | /* Now check to see if the user has specified some command line |
1105 | switch that require certain abilities from the cpu. */ | |
1106 | sought = 0; | |
f676971a | 1107 | |
d5b7b3ae | 1108 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 1109 | { |
aec3cfba | 1110 | sought |= (FL_THUMB | FL_MODE32); |
f676971a | 1111 | |
d5b7b3ae | 1112 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
1113 | interworking. Therefore we force FL_MODE26 to be removed |
1114 | from insn_flags here (if it was set), so that the search | |
1115 | below will always be able to find a compatible processor. */ | |
5895f793 | 1116 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 1117 | } |
f676971a | 1118 | |
aec3cfba | 1119 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 1120 | { |
aec3cfba NC |
1121 | /* Try to locate a CPU type that supports all of the abilities |
1122 | of the default CPU, plus the extra abilities requested by | |
1123 | the user. */ | |
5895f793 | 1124 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 1125 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
1126 | break; |
1127 | ||
1128 | if (sel->name == NULL) | |
aec3cfba | 1129 | { |
0977774b | 1130 | unsigned current_bit_count = 0; |
8b60264b | 1131 | const struct processors * best_fit = NULL; |
f676971a | 1132 | |
aec3cfba NC |
1133 | /* Ideally we would like to issue an error message here |
1134 | saying that it was not possible to find a CPU compatible | |
1135 | with the default CPU, but which also supports the command | |
1136 | line options specified by the programmer, and so they | |
1137 | ought to use the -mcpu=<name> command line option to | |
1138 | override the default CPU type. | |
1139 | ||
61f0ccff RE |
1140 | If we cannot find a cpu that has both the |
1141 | characteristics of the default cpu and the given | |
1142 | command line options we scan the array again looking | |
1143 | for a best match. */ | |
5895f793 | 1144 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
1145 | if ((sel->flags & sought) == sought) |
1146 | { | |
0977774b | 1147 | unsigned count; |
aec3cfba NC |
1148 | |
1149 | count = bit_count (sel->flags & insn_flags); | |
1150 | ||
1151 | if (count >= current_bit_count) | |
1152 | { | |
1153 | best_fit = sel; | |
1154 | current_bit_count = count; | |
1155 | } | |
1156 | } | |
f5a1b0d2 | 1157 | |
e6d29d15 NS |
1158 | gcc_assert (best_fit); |
1159 | sel = best_fit; | |
aec3cfba NC |
1160 | } |
1161 | ||
1162 | insn_flags = sel->flags; | |
f5a1b0d2 | 1163 | } |
78011587 | 1164 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); |
6c6aa1af | 1165 | arm_default_cpu = (enum processor_type) (sel - all_cores); |
9b66ebb1 | 1166 | if (arm_tune == arm_none) |
6c6aa1af | 1167 | arm_tune = arm_default_cpu; |
f5a1b0d2 | 1168 | } |
f676971a | 1169 | |
9b66ebb1 PB |
1170 | /* The processor for which we should tune should now have been |
1171 | chosen. */ | |
e6d29d15 | 1172 | gcc_assert (arm_tune != arm_none); |
f676971a | 1173 | |
9b66ebb1 | 1174 | tune_flags = all_cores[(int)arm_tune].flags; |
21b5653c RE |
1175 | if (optimize_size) |
1176 | targetm.rtx_costs = arm_size_rtx_costs; | |
1177 | else | |
1178 | targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs; | |
e26053d1 | 1179 | |
f5a1b0d2 NC |
1180 | /* Make sure that the processor choice does not conflict with any of the |
1181 | other command line choices. */ | |
5b3e6663 PB |
1182 | if (TARGET_ARM && !(insn_flags & FL_NOTM)) |
1183 | error ("target CPU does not support ARM mode"); | |
1184 | ||
6cfc7210 | 1185 | if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) |
f5a1b0d2 | 1186 | { |
d4ee4d25 | 1187 | warning (0, "target CPU does not support interworking" ); |
c54c7322 | 1188 | target_flags &= ~MASK_INTERWORK; |
f5a1b0d2 | 1189 | } |
f676971a | 1190 | |
d5b7b3ae RE |
1191 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
1192 | { | |
d4ee4d25 | 1193 | warning (0, "target CPU does not support THUMB instructions"); |
c54c7322 | 1194 | target_flags &= ~MASK_THUMB; |
d5b7b3ae RE |
1195 | } |
1196 | ||
1197 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
1198 | { | |
d4ee4d25 | 1199 | /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */ |
c54c7322 | 1200 | target_flags &= ~MASK_APCS_FRAME; |
d5b7b3ae | 1201 | } |
d19fb8e3 | 1202 | |
da8ce8be RE |
1203 | /* Callee super interworking implies thumb interworking. Adding |
1204 | this to the flags here simplifies the logic elsewhere. */ | |
1205 | if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING) | |
1206 | target_flags |= MASK_INTERWORK; | |
1207 | ||
d5b7b3ae RE |
1208 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
1209 | from here where no function is being compiled currently. */ | |
c54c7322 | 1210 | if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM) |
d4ee4d25 | 1211 | warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1212 | |
1213 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
d4ee4d25 | 1214 | warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1215 | |
1216 | if (TARGET_ARM && TARGET_CALLER_INTERWORKING) | |
d4ee4d25 | 1217 | warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae | 1218 | |
5895f793 | 1219 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 | 1220 | { |
d4ee4d25 | 1221 | warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); |
c54c7322 | 1222 | target_flags |= MASK_APCS_FRAME; |
f5a1b0d2 | 1223 | } |
f676971a | 1224 | |
2b835d68 | 1225 | if (TARGET_POKE_FUNCTION_NAME) |
c54c7322 | 1226 | target_flags |= MASK_APCS_FRAME; |
f676971a | 1227 | |
2b835d68 | 1228 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 1229 | error ("-fpic and -mapcs-reent are incompatible"); |
f676971a | 1230 | |
2b835d68 | 1231 | if (TARGET_APCS_REENT) |
d4ee4d25 | 1232 | warning (0, "APCS reentrant code not supported. Ignored"); |
f676971a | 1233 | |
d5b7b3ae RE |
1234 | /* If this target is normally configured to use APCS frames, warn if they |
1235 | are turned off and debugging is turned on. */ | |
1236 | if (TARGET_ARM | |
1237 | && write_symbols != NO_DEBUG | |
5895f793 | 1238 | && !TARGET_APCS_FRAME |
c54c7322 | 1239 | && (TARGET_DEFAULT & MASK_APCS_FRAME)) |
d4ee4d25 | 1240 | warning (0, "-g with -mno-apcs-frame may not give sensible debugging"); |
f676971a | 1241 | |
2b835d68 | 1242 | if (TARGET_APCS_FLOAT) |
d4ee4d25 | 1243 | warning (0, "passing floating point arguments in fp regs not yet supported"); |
f676971a | 1244 | |
4912a07c | 1245 | /* Initialize boolean versions of the flags, for use in the arm.md file. */ |
9b66ebb1 PB |
1246 | arm_arch3m = (insn_flags & FL_ARCH3M) != 0; |
1247 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
68d560d4 | 1248 | arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0); |
9b66ebb1 PB |
1249 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; |
1250 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; | |
1251 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | |
d3585b76 | 1252 | arm_arch6k = (insn_flags & FL_ARCH6K) != 0; |
5b3e6663 PB |
1253 | arm_arch_notm = (insn_flags & FL_NOTM) != 0; |
1254 | arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; | |
9b66ebb1 | 1255 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; |
78011587 | 1256 | arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; |
9b66ebb1 PB |
1257 | |
1258 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; | |
abac3b49 | 1259 | arm_tune_strongarm = (tune_flags & FL_STRONG) != 0; |
9b66ebb1 | 1260 | thumb_code = (TARGET_ARM == 0); |
abac3b49 | 1261 | arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; |
9b66ebb1 PB |
1262 | arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; |
1263 | arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; | |
5b3e6663 | 1264 | arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; |
5a9335ef | 1265 | |
68d560d4 RE |
1266 | /* V5 code we generate is completely interworking capable, so we turn off |
1267 | TARGET_INTERWORK here to avoid many tests later on. */ | |
2ad4dcf9 RE |
1268 | |
1269 | /* XXX However, we must pass the right pre-processor defines to CPP | |
1270 | or GLD can get confused. This is a hack. */ | |
1271 | if (TARGET_INTERWORK) | |
1272 | arm_cpp_interwork = 1; | |
1273 | ||
68d560d4 | 1274 | if (arm_arch5) |
c54c7322 | 1275 | target_flags &= ~MASK_INTERWORK; |
68d560d4 | 1276 | |
5848830f PB |
1277 | if (target_abi_name) |
1278 | { | |
1279 | for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) | |
1280 | { | |
1281 | if (streq (arm_all_abis[i].name, target_abi_name)) | |
1282 | { | |
1283 | arm_abi = arm_all_abis[i].abi_type; | |
1284 | break; | |
1285 | } | |
1286 | } | |
1287 | if (i == ARRAY_SIZE (arm_all_abis)) | |
1288 | error ("invalid ABI option: -mabi=%s", target_abi_name); | |
1289 | } | |
1290 | else | |
c805f22e | 1291 | arm_abi = ARM_DEFAULT_ABI; |
5848830f PB |
1292 | |
1293 | if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) | |
1294 | error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); | |
1295 | ||
1296 | if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) | |
1297 | error ("iwmmxt abi requires an iwmmxt capable cpu"); | |
6f7ebcbb | 1298 | |
9b66ebb1 PB |
1299 | arm_fp_model = ARM_FP_MODEL_UNKNOWN; |
1300 | if (target_fpu_name == NULL && target_fpe_name != NULL) | |
9b6b54e2 | 1301 | { |
9b66ebb1 PB |
1302 | if (streq (target_fpe_name, "2")) |
1303 | target_fpu_name = "fpe2"; | |
1304 | else if (streq (target_fpe_name, "3")) | |
1305 | target_fpu_name = "fpe3"; | |
1306 | else | |
1307 | error ("invalid floating point emulation option: -mfpe=%s", | |
1308 | target_fpe_name); | |
1309 | } | |
1310 | if (target_fpu_name != NULL) | |
1311 | { | |
1312 | /* The user specified a FPU. */ | |
1313 | for (i = 0; i < ARRAY_SIZE (all_fpus); i++) | |
1314 | { | |
1315 | if (streq (all_fpus[i].name, target_fpu_name)) | |
1316 | { | |
1317 | arm_fpu_arch = all_fpus[i].fpu; | |
1318 | arm_fpu_tune = arm_fpu_arch; | |
1319 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
1320 | break; | |
1321 | } | |
1322 | } | |
1323 | if (arm_fp_model == ARM_FP_MODEL_UNKNOWN) | |
1324 | error ("invalid floating point option: -mfpu=%s", target_fpu_name); | |
9b6b54e2 NC |
1325 | } |
1326 | else | |
2b835d68 | 1327 | { |
9b66ebb1 | 1328 | #ifdef FPUTYPE_DEFAULT |
78011587 | 1329 | /* Use the default if it is specified for this platform. */ |
9b66ebb1 PB |
1330 | arm_fpu_arch = FPUTYPE_DEFAULT; |
1331 | arm_fpu_tune = FPUTYPE_DEFAULT; | |
1332 | #else | |
1333 | /* Pick one based on CPU type. */ | |
78011587 | 1334 | /* ??? Some targets assume FPA is the default. |
9b66ebb1 PB |
1335 | if ((insn_flags & FL_VFP) != 0) |
1336 | arm_fpu_arch = FPUTYPE_VFP; | |
78011587 PB |
1337 | else |
1338 | */ | |
1339 | if (arm_arch_cirrus) | |
9b66ebb1 PB |
1340 | arm_fpu_arch = FPUTYPE_MAVERICK; |
1341 | else | |
29ad9694 | 1342 | arm_fpu_arch = FPUTYPE_FPA_EMU2; |
9b66ebb1 PB |
1343 | #endif |
1344 | if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
1345 | arm_fpu_tune = FPUTYPE_FPA; | |
2b835d68 | 1346 | else |
9b66ebb1 PB |
1347 | arm_fpu_tune = arm_fpu_arch; |
1348 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
e6d29d15 | 1349 | gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN); |
9b66ebb1 PB |
1350 | } |
1351 | ||
1352 | if (target_float_abi_name != NULL) | |
1353 | { | |
1354 | /* The user specified a FP ABI. */ | |
1355 | for (i = 0; i < ARRAY_SIZE (all_float_abis); i++) | |
1356 | { | |
1357 | if (streq (all_float_abis[i].name, target_float_abi_name)) | |
1358 | { | |
1359 | arm_float_abi = all_float_abis[i].abi_type; | |
1360 | break; | |
1361 | } | |
1362 | } | |
1363 | if (i == ARRAY_SIZE (all_float_abis)) | |
1364 | error ("invalid floating point abi: -mfloat-abi=%s", | |
1365 | target_float_abi_name); | |
2b835d68 | 1366 | } |
3d8532aa PB |
1367 | else |
1368 | arm_float_abi = TARGET_DEFAULT_FLOAT_ABI; | |
9b66ebb1 | 1369 | |
72cdc543 PB |
1370 | if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP) |
1371 | sorry ("-mfloat-abi=hard and VFP"); | |
1372 | ||
87b24aaf PB |
1373 | /* FPA and iWMMXt are incompatible because the insn encodings overlap. |
1374 | VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon | |
1375 | will ever exist. GCC makes no attempt to support this combination. */ | |
1376 | if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT) | |
1377 | sorry ("iWMMXt and hardware floating point"); | |
1378 | ||
5b3e6663 PB |
1379 | /* ??? iWMMXt insn patterns need auditing for Thumb-2. */ |
1380 | if (TARGET_THUMB2 && TARGET_IWMMXT) | |
1381 | sorry ("Thumb-2 iWMMXt"); | |
1382 | ||
9b66ebb1 PB |
1383 | /* If soft-float is specified then don't use FPU. */ |
1384 | if (TARGET_SOFT_FLOAT) | |
1385 | arm_fpu_arch = FPUTYPE_NONE; | |
f676971a | 1386 | |
f5a1b0d2 NC |
1387 | /* For arm2/3 there is no need to do any scheduling if there is only |
1388 | a floating point emulator, or we are doing software floating-point. */ | |
9b66ebb1 PB |
1389 | if ((TARGET_SOFT_FLOAT |
1390 | || arm_fpu_tune == FPUTYPE_FPA_EMU2 | |
1391 | || arm_fpu_tune == FPUTYPE_FPA_EMU3) | |
ed0e6530 | 1392 | && (tune_flags & FL_MODE32) == 0) |
f5a1b0d2 | 1393 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
f676971a | 1394 | |
d3585b76 DJ |
1395 | if (target_thread_switch) |
1396 | { | |
1397 | if (strcmp (target_thread_switch, "soft") == 0) | |
1398 | target_thread_pointer = TP_SOFT; | |
1399 | else if (strcmp (target_thread_switch, "auto") == 0) | |
1400 | target_thread_pointer = TP_AUTO; | |
1401 | else if (strcmp (target_thread_switch, "cp15") == 0) | |
1402 | target_thread_pointer = TP_CP15; | |
1403 | else | |
1404 | error ("invalid thread pointer option: -mtp=%s", target_thread_switch); | |
1405 | } | |
1406 | ||
1407 | /* Use the cp15 method if it is available. */ | |
1408 | if (target_thread_pointer == TP_AUTO) | |
1409 | { | |
1410 | if (arm_arch6k && !TARGET_THUMB) | |
1411 | target_thread_pointer = TP_CP15; | |
1412 | else | |
1413 | target_thread_pointer = TP_SOFT; | |
1414 | } | |
1415 | ||
5b3e6663 PB |
1416 | if (TARGET_HARD_TP && TARGET_THUMB1) |
1417 | error ("can not use -mtp=cp15 with 16-bit Thumb"); | |
d3585b76 | 1418 | |
5848830f | 1419 | /* Override the default structure alignment for AAPCS ABI. */ |
077fc835 | 1420 | if (TARGET_AAPCS_BASED) |
5848830f PB |
1421 | arm_structure_size_boundary = 8; |
1422 | ||
b355a481 NC |
1423 | if (structure_size_string != NULL) |
1424 | { | |
1425 | int size = strtol (structure_size_string, NULL, 0); | |
5848830f PB |
1426 | |
1427 | if (size == 8 || size == 32 | |
1428 | || (ARM_DOUBLEWORD_ALIGN && size == 64)) | |
b355a481 NC |
1429 | arm_structure_size_boundary = size; |
1430 | else | |
d4ee4d25 | 1431 | warning (0, "structure size boundary can only be set to %s", |
5848830f | 1432 | ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32"); |
b355a481 | 1433 | } |
ed0e6530 | 1434 | |
9403b7f7 RS |
1435 | if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic) |
1436 | { | |
1437 | error ("RTP PIC is incompatible with Thumb"); | |
1438 | flag_pic = 0; | |
1439 | } | |
1440 | ||
c147eacb PB |
1441 | /* If stack checking is disabled, we can use r10 as the PIC register, |
1442 | which keeps r9 available. The EABI specifies r9 as the PIC register. */ | |
1443 | if (flag_pic && TARGET_SINGLE_PIC_BASE) | |
9403b7f7 RS |
1444 | { |
1445 | if (TARGET_VXWORKS_RTP) | |
1446 | warning (0, "RTP PIC is incompatible with -msingle-pic-base"); | |
1447 | arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10; | |
1448 | } | |
1449 | ||
1450 | if (flag_pic && TARGET_VXWORKS_RTP) | |
1451 | arm_pic_register = 9; | |
c147eacb | 1452 | |
ed0e6530 PB |
1453 | if (arm_pic_register_string != NULL) |
1454 | { | |
5b43fed1 | 1455 | int pic_register = decode_reg_name (arm_pic_register_string); |
e26053d1 | 1456 | |
5895f793 | 1457 | if (!flag_pic) |
d4ee4d25 | 1458 | warning (0, "-mpic-register= is useless without -fpic"); |
ed0e6530 | 1459 | |
ed0e6530 | 1460 | /* Prevent the user from choosing an obviously stupid PIC register. */ |
5b43fed1 RH |
1461 | else if (pic_register < 0 || call_used_regs[pic_register] |
1462 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
1463 | || pic_register == STACK_POINTER_REGNUM | |
9403b7f7 RS |
1464 | || pic_register >= PC_REGNUM |
1465 | || (TARGET_VXWORKS_RTP | |
1466 | && (unsigned int) pic_register != arm_pic_register)) | |
c725bd79 | 1467 | error ("unable to use '%s' for PIC register", arm_pic_register_string); |
ed0e6530 PB |
1468 | else |
1469 | arm_pic_register = pic_register; | |
1470 | } | |
d5b7b3ae | 1471 | |
5b3e6663 | 1472 | /* ??? We might want scheduling for thumb2. */ |
d5b7b3ae RE |
1473 | if (TARGET_THUMB && flag_schedule_insns) |
1474 | { | |
1475 | /* Don't warn since it's on by default in -O2. */ | |
1476 | flag_schedule_insns = 0; | |
1477 | } | |
1478 | ||
f5a1b0d2 | 1479 | if (optimize_size) |
be03ccc9 | 1480 | { |
577d6328 | 1481 | arm_constant_limit = 1; |
be03ccc9 NP |
1482 | |
1483 | /* If optimizing for size, bump the number of instructions that we | |
d6b4baa4 | 1484 | are prepared to conditionally execute (even on a StrongARM). */ |
be03ccc9 NP |
1485 | max_insns_skipped = 6; |
1486 | } | |
1487 | else | |
1488 | { | |
1489 | /* For processors with load scheduling, it never costs more than | |
1490 | 2 cycles to load a constant, and the load scheduler may well | |
1491 | reduce that to 1. */ | |
2075b05d | 1492 | if (arm_ld_sched) |
be03ccc9 NP |
1493 | arm_constant_limit = 1; |
1494 | ||
1495 | /* On XScale the longer latency of a load makes it more difficult | |
1496 | to achieve a good schedule, so it's faster to synthesize | |
d6b4baa4 | 1497 | constants that can be done in two insns. */ |
be03ccc9 NP |
1498 | if (arm_tune_xscale) |
1499 | arm_constant_limit = 2; | |
1500 | ||
1501 | /* StrongARM has early execution of branches, so a sequence | |
1502 | that is worth skipping is shorter. */ | |
abac3b49 | 1503 | if (arm_tune_strongarm) |
be03ccc9 NP |
1504 | max_insns_skipped = 3; |
1505 | } | |
92a432f4 RE |
1506 | |
1507 | /* Register global variables with the garbage collector. */ | |
1508 | arm_add_gc_roots (); | |
1509 | } | |
1510 | ||
1511 | static void | |
e32bac5b | 1512 | arm_add_gc_roots (void) |
92a432f4 | 1513 | { |
c7319d87 RE |
1514 | gcc_obstack_init(&minipool_obstack); |
1515 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 1516 | } |
cce8749e | 1517 | \f |
6d3d9133 NC |
1518 | /* A table of known ARM exception types. |
1519 | For use with the interrupt function attribute. */ | |
1520 | ||
1521 | typedef struct | |
1522 | { | |
8b60264b KG |
1523 | const char *const arg; |
1524 | const unsigned long return_value; | |
6d3d9133 NC |
1525 | } |
1526 | isr_attribute_arg; | |
1527 | ||
8b60264b | 1528 | static const isr_attribute_arg isr_attribute_args [] = |
6d3d9133 NC |
1529 | { |
1530 | { "IRQ", ARM_FT_ISR }, | |
1531 | { "irq", ARM_FT_ISR }, | |
1532 | { "FIQ", ARM_FT_FIQ }, | |
1533 | { "fiq", ARM_FT_FIQ }, | |
1534 | { "ABORT", ARM_FT_ISR }, | |
1535 | { "abort", ARM_FT_ISR }, | |
1536 | { "ABORT", ARM_FT_ISR }, | |
1537 | { "abort", ARM_FT_ISR }, | |
1538 | { "UNDEF", ARM_FT_EXCEPTION }, | |
1539 | { "undef", ARM_FT_EXCEPTION }, | |
1540 | { "SWI", ARM_FT_EXCEPTION }, | |
1541 | { "swi", ARM_FT_EXCEPTION }, | |
1542 | { NULL, ARM_FT_NORMAL } | |
1543 | }; | |
1544 | ||
1545 | /* Returns the (interrupt) function type of the current | |
1546 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
1547 | ||
1548 | static unsigned long | |
e32bac5b | 1549 | arm_isr_value (tree argument) |
6d3d9133 | 1550 | { |
8b60264b | 1551 | const isr_attribute_arg * ptr; |
1d6e90ac | 1552 | const char * arg; |
6d3d9133 | 1553 | |
5b3e6663 PB |
1554 | if (!arm_arch_notm) |
1555 | return ARM_FT_NORMAL | ARM_FT_STACKALIGN; | |
1556 | ||
6d3d9133 NC |
1557 | /* No argument - default to IRQ. */ |
1558 | if (argument == NULL_TREE) | |
1559 | return ARM_FT_ISR; | |
1560 | ||
1561 | /* Get the value of the argument. */ | |
1562 | if (TREE_VALUE (argument) == NULL_TREE | |
1563 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
1564 | return ARM_FT_UNKNOWN; | |
1565 | ||
1566 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
1567 | ||
1568 | /* Check it against the list of known arguments. */ | |
5a9335ef | 1569 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) |
1d6e90ac NC |
1570 | if (streq (arg, ptr->arg)) |
1571 | return ptr->return_value; | |
6d3d9133 | 1572 | |
05713b80 | 1573 | /* An unrecognized interrupt type. */ |
6d3d9133 NC |
1574 | return ARM_FT_UNKNOWN; |
1575 | } | |
1576 | ||
1577 | /* Computes the type of the current function. */ | |
1578 | ||
1579 | static unsigned long | |
e32bac5b | 1580 | arm_compute_func_type (void) |
6d3d9133 NC |
1581 | { |
1582 | unsigned long type = ARM_FT_UNKNOWN; | |
1583 | tree a; | |
1584 | tree attr; | |
f676971a | 1585 | |
e6d29d15 | 1586 | gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL); |
6d3d9133 NC |
1587 | |
1588 | /* Decide if the current function is volatile. Such functions | |
1589 | never return, and many memory cycles can be saved by not storing | |
1590 | register values that will never be needed again. This optimization | |
1591 | was added to speed up context switching in a kernel application. */ | |
1592 | if (optimize > 0 | |
cf1955dc PB |
1593 | && (TREE_NOTHROW (current_function_decl) |
1594 | || !(flag_unwind_tables | |
1595 | || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))) | |
6d3d9133 NC |
1596 | && TREE_THIS_VOLATILE (current_function_decl)) |
1597 | type |= ARM_FT_VOLATILE; | |
f676971a | 1598 | |
6de9cd9a | 1599 | if (cfun->static_chain_decl != NULL) |
6d3d9133 NC |
1600 | type |= ARM_FT_NESTED; |
1601 | ||
91d231cb | 1602 | attr = DECL_ATTRIBUTES (current_function_decl); |
f676971a | 1603 | |
6d3d9133 NC |
1604 | a = lookup_attribute ("naked", attr); |
1605 | if (a != NULL_TREE) | |
1606 | type |= ARM_FT_NAKED; | |
1607 | ||
c9ca9b88 PB |
1608 | a = lookup_attribute ("isr", attr); |
1609 | if (a == NULL_TREE) | |
1610 | a = lookup_attribute ("interrupt", attr); | |
f676971a | 1611 | |
c9ca9b88 PB |
1612 | if (a == NULL_TREE) |
1613 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
6d3d9133 | 1614 | else |
c9ca9b88 | 1615 | type |= arm_isr_value (TREE_VALUE (a)); |
f676971a | 1616 | |
6d3d9133 NC |
1617 | return type; |
1618 | } | |
1619 | ||
1620 | /* Returns the type of the current function. */ | |
1621 | ||
1622 | unsigned long | |
e32bac5b | 1623 | arm_current_func_type (void) |
6d3d9133 NC |
1624 | { |
1625 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
1626 | cfun->machine->func_type = arm_compute_func_type (); | |
1627 | ||
1628 | return cfun->machine->func_type; | |
1629 | } | |
007e61c2 PB |
1630 | |
1631 | bool | |
1632 | arm_allocate_stack_slots_for_args (void) | |
1633 | { | |
1634 | /* Naked functions should not allocate stack slots for arguments. */ | |
1635 | return !IS_NAKED (arm_current_func_type ()); | |
1636 | } | |
1637 | ||
6d3d9133 | 1638 | \f |
f676971a | 1639 | /* Return 1 if it is possible to return using a single instruction. |
a72d4945 RE |
1640 | If SIBLING is non-null, this is a test for a return before a sibling |
1641 | call. SIBLING is the call insn, so we can examine its register usage. */ | |
6d3d9133 | 1642 | |
ff9940b0 | 1643 | int |
a72d4945 | 1644 | use_return_insn (int iscond, rtx sibling) |
ff9940b0 RE |
1645 | { |
1646 | int regno; | |
9b598fa0 | 1647 | unsigned int func_type; |
d5db54a1 | 1648 | unsigned long saved_int_regs; |
a72d4945 | 1649 | unsigned HOST_WIDE_INT stack_adjust; |
5848830f | 1650 | arm_stack_offsets *offsets; |
ff9940b0 | 1651 | |
d5b7b3ae | 1652 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
1653 | if (!reload_completed) |
1654 | return 0; | |
efc2515b | 1655 | |
9b598fa0 RE |
1656 | func_type = arm_current_func_type (); |
1657 | ||
5b3e6663 | 1658 | /* Naked, volatile and stack alignment functions need special |
3a7731fd | 1659 | consideration. */ |
5b3e6663 | 1660 | if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN)) |
6d3d9133 | 1661 | return 0; |
06bea5aa | 1662 | |
a15908a4 PB |
1663 | /* So do interrupt functions that use the frame pointer and Thumb |
1664 | interrupt functions. */ | |
1665 | if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB)) | |
06bea5aa | 1666 | return 0; |
a72d4945 | 1667 | |
5848830f PB |
1668 | offsets = arm_get_frame_offsets (); |
1669 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; | |
a72d4945 | 1670 | |
6d3d9133 | 1671 | /* As do variadic functions. */ |
38173d38 | 1672 | if (crtl->args.pretend_args_size |
3cb66fd7 | 1673 | || cfun->machine->uses_anonymous_args |
699a4925 | 1674 | /* Or if the function calls __builtin_eh_return () */ |
e3b5732b | 1675 | || crtl->calls_eh_return |
699a4925 | 1676 | /* Or if the function calls alloca */ |
e3b5732b | 1677 | || cfun->calls_alloca |
a72d4945 RE |
1678 | /* Or if there is a stack adjustment. However, if the stack pointer |
1679 | is saved on the stack, we can use a pre-incrementing stack load. */ | |
ec6237e4 PB |
1680 | || !(stack_adjust == 0 || (TARGET_APCS_FRAME && frame_pointer_needed |
1681 | && stack_adjust == 4))) | |
ff9940b0 RE |
1682 | return 0; |
1683 | ||
954954d1 | 1684 | saved_int_regs = offsets->saved_regs_mask; |
d5db54a1 | 1685 | |
a72d4945 RE |
1686 | /* Unfortunately, the insn |
1687 | ||
1688 | ldmib sp, {..., sp, ...} | |
1689 | ||
1690 | triggers a bug on most SA-110 based devices, such that the stack | |
1691 | pointer won't be correctly restored if the instruction takes a | |
839a4992 | 1692 | page fault. We work around this problem by popping r3 along with |
a72d4945 | 1693 | the other registers, since that is never slower than executing |
f676971a | 1694 | another instruction. |
a72d4945 RE |
1695 | |
1696 | We test for !arm_arch5 here, because code for any architecture | |
1697 | less than this could potentially be run on one of the buggy | |
1698 | chips. */ | |
5b3e6663 | 1699 | if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM) |
a72d4945 RE |
1700 | { |
1701 | /* Validate that r3 is a call-clobbered register (always true in | |
d6b4baa4 | 1702 | the default abi) ... */ |
a72d4945 RE |
1703 | if (!call_used_regs[3]) |
1704 | return 0; | |
1705 | ||
4f5dfed0 JC |
1706 | /* ... that it isn't being used for a return value ... */ |
1707 | if (arm_size_return_regs () >= (4 * UNITS_PER_WORD)) | |
1708 | return 0; | |
1709 | ||
1710 | /* ... or for a tail-call argument ... */ | |
a72d4945 RE |
1711 | if (sibling) |
1712 | { | |
e6d29d15 | 1713 | gcc_assert (GET_CODE (sibling) == CALL_INSN); |
a72d4945 RE |
1714 | |
1715 | if (find_regno_fusage (sibling, USE, 3)) | |
1716 | return 0; | |
1717 | } | |
1718 | ||
1719 | /* ... and that there are no call-saved registers in r0-r2 | |
1720 | (always true in the default ABI). */ | |
1721 | if (saved_int_regs & 0x7) | |
1722 | return 0; | |
1723 | } | |
1724 | ||
b111229a | 1725 | /* Can't be done if interworking with Thumb, and any registers have been |
d5db54a1 | 1726 | stacked. */ |
a15908a4 | 1727 | if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type)) |
b36ba79f | 1728 | return 0; |
d5db54a1 RE |
1729 | |
1730 | /* On StrongARM, conditional returns are expensive if they aren't | |
1731 | taken and multiple registers have been stacked. */ | |
abac3b49 | 1732 | if (iscond && arm_tune_strongarm) |
6ed30148 | 1733 | { |
f676971a | 1734 | /* Conditional return when just the LR is stored is a simple |
d5db54a1 RE |
1735 | conditional-load instruction, that's not expensive. */ |
1736 | if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) | |
1737 | return 0; | |
6ed30148 | 1738 | |
020a4035 RE |
1739 | if (flag_pic |
1740 | && arm_pic_register != INVALID_REGNUM | |
6fb5fa3c | 1741 | && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
b111229a | 1742 | return 0; |
6ed30148 | 1743 | } |
d5db54a1 RE |
1744 | |
1745 | /* If there are saved registers but the LR isn't saved, then we need | |
1746 | two instructions for the return. */ | |
1747 | if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) | |
1748 | return 0; | |
1749 | ||
3b684012 | 1750 | /* Can't be done if any of the FPA regs are pushed, |
6d3d9133 | 1751 | since this also requires an insn. */ |
9b66ebb1 PB |
1752 | if (TARGET_HARD_FLOAT && TARGET_FPA) |
1753 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 1754 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
9b66ebb1 PB |
1755 | return 0; |
1756 | ||
1757 | /* Likewise VFP regs. */ | |
1758 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
1759 | for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) | |
6fb5fa3c | 1760 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
d5b7b3ae | 1761 | return 0; |
ff9940b0 | 1762 | |
5a9335ef NC |
1763 | if (TARGET_REALLY_IWMMXT) |
1764 | for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) | |
6fb5fa3c | 1765 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5a9335ef NC |
1766 | return 0; |
1767 | ||
ff9940b0 RE |
1768 | return 1; |
1769 | } | |
1770 | ||
cce8749e CH |
1771 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
1772 | ||
1773 | int | |
e32bac5b | 1774 | const_ok_for_arm (HOST_WIDE_INT i) |
cce8749e | 1775 | { |
4642ccb1 | 1776 | int lowbit; |
e0b92319 | 1777 | |
f676971a | 1778 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
56636818 | 1779 | be all zero, or all one. */ |
30cf4896 KG |
1780 | if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 |
1781 | && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) | |
1782 | != ((~(unsigned HOST_WIDE_INT) 0) | |
1783 | & ~(unsigned HOST_WIDE_INT) 0xffffffff))) | |
56636818 | 1784 | return FALSE; |
f676971a | 1785 | |
4642ccb1 | 1786 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; |
e0b92319 | 1787 | |
4642ccb1 RE |
1788 | /* Fast return for 0 and small values. We must do this for zero, since |
1789 | the code below can't handle that one case. */ | |
1790 | if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0) | |
e2c671ba RE |
1791 | return TRUE; |
1792 | ||
5b3e6663 PB |
1793 | /* Get the number of trailing zeros. */ |
1794 | lowbit = ffs((int) i) - 1; | |
1795 | ||
1796 | /* Only even shifts are allowed in ARM mode so round down to the | |
1797 | nearest even number. */ | |
1798 | if (TARGET_ARM) | |
1799 | lowbit &= ~1; | |
4642ccb1 RE |
1800 | |
1801 | if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0) | |
1802 | return TRUE; | |
5b3e6663 PB |
1803 | |
1804 | if (TARGET_ARM) | |
1805 | { | |
1806 | /* Allow rotated constants in ARM mode. */ | |
1807 | if (lowbit <= 4 | |
4642ccb1 RE |
1808 | && ((i & ~0xc000003f) == 0 |
1809 | || (i & ~0xf000000f) == 0 | |
1810 | || (i & ~0xfc000003) == 0)) | |
5b3e6663 PB |
1811 | return TRUE; |
1812 | } | |
1813 | else | |
1814 | { | |
1815 | HOST_WIDE_INT v; | |
1816 | ||
1817 | /* Allow repeated pattern. */ | |
1818 | v = i & 0xff; | |
1819 | v |= v << 16; | |
1820 | if (i == v || i == (v | (v << 8))) | |
1821 | return TRUE; | |
1822 | } | |
cce8749e | 1823 | |
f3bb6135 RE |
1824 | return FALSE; |
1825 | } | |
cce8749e | 1826 | |
6354dc9b | 1827 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 | 1828 | static int |
e32bac5b | 1829 | const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) |
e2c671ba RE |
1830 | { |
1831 | if (const_ok_for_arm (i)) | |
1832 | return 1; | |
1833 | ||
1834 | switch (code) | |
1835 | { | |
1836 | case PLUS: | |
1837 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); | |
1838 | ||
1839 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
1840 | case XOR: | |
1841 | case IOR: | |
1842 | return 0; | |
1843 | ||
1844 | case AND: | |
1845 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
1846 | ||
1847 | default: | |
e6d29d15 | 1848 | gcc_unreachable (); |
e2c671ba RE |
1849 | } |
1850 | } | |
1851 | ||
1852 | /* Emit a sequence of insns to handle a large constant. | |
1853 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
1854 | IOR, AND, XOR, MINUS; | |
1855 | MODE is the mode in which the operation is being performed; | |
1856 | VAL is the integer to operate on; | |
1857 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
1858 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
1859 | either produce a simpler sequence, or we will want to cse the values. |
1860 | Return value is the number of insns emitted. */ | |
e2c671ba | 1861 | |
5b3e6663 | 1862 | /* ??? Tweak this for thumb2. */ |
e2c671ba | 1863 | int |
a406f566 | 1864 | arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, |
e32bac5b | 1865 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets) |
2b835d68 | 1866 | { |
a406f566 MM |
1867 | rtx cond; |
1868 | ||
1869 | if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC) | |
1870 | cond = COND_EXEC_TEST (PATTERN (insn)); | |
1871 | else | |
1872 | cond = NULL_RTX; | |
1873 | ||
2b835d68 RE |
1874 | if (subtargets || code == SET |
1875 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
1876 | && REGNO (target) != REGNO (source))) | |
1877 | { | |
4b632bf1 | 1878 | /* After arm_reorg has been called, we can't fix up expensive |
05713b80 | 1879 | constants by pushing them into memory so we must synthesize |
4b632bf1 RE |
1880 | them in-line, regardless of the cost. This is only likely to |
1881 | be more costly on chips that have load delay slots and we are | |
1882 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
1883 | occurred before the final instruction emission). |
1884 | ||
1885 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 1886 | */ |
5895f793 | 1887 | if (!after_arm_reorg |
a406f566 | 1888 | && !cond |
f676971a | 1889 | && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, |
a406f566 | 1890 | 1, 0) |
4b632bf1 | 1891 | > arm_constant_limit + (code != SET))) |
2b835d68 RE |
1892 | { |
1893 | if (code == SET) | |
1894 | { | |
1895 | /* Currently SET is the only monadic value for CODE, all | |
1896 | the rest are diadic. */ | |
d66437c5 | 1897 | emit_set_insn (target, GEN_INT (val)); |
2b835d68 RE |
1898 | return 1; |
1899 | } | |
1900 | else | |
1901 | { | |
1902 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
1903 | ||
d66437c5 | 1904 | emit_set_insn (temp, GEN_INT (val)); |
2b835d68 RE |
1905 | /* For MINUS, the value is subtracted from, since we never |
1906 | have subtraction of a constant. */ | |
1907 | if (code == MINUS) | |
d66437c5 | 1908 | emit_set_insn (target, gen_rtx_MINUS (mode, temp, source)); |
2b835d68 | 1909 | else |
d66437c5 RE |
1910 | emit_set_insn (target, |
1911 | gen_rtx_fmt_ee (code, mode, source, temp)); | |
2b835d68 RE |
1912 | return 2; |
1913 | } | |
1914 | } | |
1915 | } | |
1916 | ||
f676971a | 1917 | return arm_gen_constant (code, mode, cond, val, target, source, subtargets, |
a406f566 | 1918 | 1); |
2b835d68 RE |
1919 | } |
1920 | ||
5b3e6663 PB |
1921 | /* Return the number of ARM instructions required to synthesize the given |
1922 | constant. */ | |
ceebdb09 | 1923 | static int |
e32bac5b | 1924 | count_insns_for_constant (HOST_WIDE_INT remainder, int i) |
ceebdb09 PB |
1925 | { |
1926 | HOST_WIDE_INT temp1; | |
1927 | int num_insns = 0; | |
1928 | do | |
1929 | { | |
1930 | int end; | |
f676971a | 1931 | |
ceebdb09 PB |
1932 | if (i <= 0) |
1933 | i += 32; | |
1934 | if (remainder & (3 << (i - 2))) | |
1935 | { | |
1936 | end = i - 8; | |
1937 | if (end < 0) | |
1938 | end += 32; | |
1939 | temp1 = remainder & ((0x0ff << end) | |
1940 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
1941 | remainder &= ~temp1; | |
1942 | num_insns++; | |
1943 | i -= 6; | |
1944 | } | |
1945 | i -= 2; | |
1946 | } while (remainder); | |
1947 | return num_insns; | |
1948 | } | |
1949 | ||
a406f566 MM |
1950 | /* Emit an instruction with the indicated PATTERN. If COND is |
1951 | non-NULL, conditionalize the execution of the instruction on COND | |
1952 | being true. */ | |
1953 | ||
1954 | static void | |
1955 | emit_constant_insn (rtx cond, rtx pattern) | |
1956 | { | |
1957 | if (cond) | |
1958 | pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern); | |
1959 | emit_insn (pattern); | |
1960 | } | |
1961 | ||
2b835d68 RE |
1962 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
1963 | RTL generation. */ | |
5b3e6663 | 1964 | /* ??? This needs more work for thumb2. */ |
1d6e90ac | 1965 | |
d5b7b3ae | 1966 | static int |
a406f566 | 1967 | arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, |
e32bac5b RE |
1968 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets, |
1969 | int generate) | |
e2c671ba | 1970 | { |
e2c671ba RE |
1971 | int can_invert = 0; |
1972 | int can_negate = 0; | |
1973 | int can_negate_initial = 0; | |
1974 | int can_shift = 0; | |
1975 | int i; | |
1976 | int num_bits_set = 0; | |
1977 | int set_sign_bit_copies = 0; | |
1978 | int clear_sign_bit_copies = 0; | |
1979 | int clear_zero_bit_copies = 0; | |
1980 | int set_zero_bit_copies = 0; | |
1981 | int insns = 0; | |
e2c671ba | 1982 | unsigned HOST_WIDE_INT temp1, temp2; |
30cf4896 | 1983 | unsigned HOST_WIDE_INT remainder = val & 0xffffffff; |
e2c671ba | 1984 | |
d5b7b3ae | 1985 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
1986 | check for degenerate cases; these can occur when DImode operations |
1987 | are split. */ | |
1988 | switch (code) | |
1989 | { | |
1990 | case SET: | |
1991 | can_invert = 1; | |
1992 | can_shift = 1; | |
1993 | can_negate = 1; | |
1994 | break; | |
1995 | ||
1996 | case PLUS: | |
1997 | can_negate = 1; | |
1998 | can_negate_initial = 1; | |
1999 | break; | |
2000 | ||
2001 | case IOR: | |
30cf4896 | 2002 | if (remainder == 0xffffffff) |
e2c671ba | 2003 | { |
2b835d68 | 2004 | if (generate) |
a406f566 MM |
2005 | emit_constant_insn (cond, |
2006 | gen_rtx_SET (VOIDmode, target, | |
2007 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
2008 | return 1; |
2009 | } | |
2010 | if (remainder == 0) | |
2011 | { | |
2012 | if (reload_completed && rtx_equal_p (target, source)) | |
2013 | return 0; | |
2b835d68 | 2014 | if (generate) |
a406f566 MM |
2015 | emit_constant_insn (cond, |
2016 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2017 | return 1; |
2018 | } | |
2019 | break; | |
2020 | ||
2021 | case AND: | |
2022 | if (remainder == 0) | |
2023 | { | |
2b835d68 | 2024 | if (generate) |
a406f566 MM |
2025 | emit_constant_insn (cond, |
2026 | gen_rtx_SET (VOIDmode, target, const0_rtx)); | |
e2c671ba RE |
2027 | return 1; |
2028 | } | |
30cf4896 | 2029 | if (remainder == 0xffffffff) |
e2c671ba RE |
2030 | { |
2031 | if (reload_completed && rtx_equal_p (target, source)) | |
2032 | return 0; | |
2b835d68 | 2033 | if (generate) |
a406f566 MM |
2034 | emit_constant_insn (cond, |
2035 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2036 | return 1; |
2037 | } | |
2038 | can_invert = 1; | |
2039 | break; | |
2040 | ||
2041 | case XOR: | |
2042 | if (remainder == 0) | |
2043 | { | |
2044 | if (reload_completed && rtx_equal_p (target, source)) | |
2045 | return 0; | |
2b835d68 | 2046 | if (generate) |
a406f566 MM |
2047 | emit_constant_insn (cond, |
2048 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2049 | return 1; |
2050 | } | |
e0b92319 | 2051 | |
e6d29d15 NS |
2052 | /* We don't know how to handle other cases yet. */ |
2053 | gcc_assert (remainder == 0xffffffff); | |
e0b92319 | 2054 | |
e6d29d15 NS |
2055 | if (generate) |
2056 | emit_constant_insn (cond, | |
2057 | gen_rtx_SET (VOIDmode, target, | |
2058 | gen_rtx_NOT (mode, source))); | |
2059 | return 1; | |
e2c671ba RE |
2060 | |
2061 | case MINUS: | |
2062 | /* We treat MINUS as (val - source), since (source - val) is always | |
2063 | passed as (source + (-val)). */ | |
2064 | if (remainder == 0) | |
2065 | { | |
2b835d68 | 2066 | if (generate) |
a406f566 MM |
2067 | emit_constant_insn (cond, |
2068 | gen_rtx_SET (VOIDmode, target, | |
2069 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
2070 | return 1; |
2071 | } | |
2072 | if (const_ok_for_arm (val)) | |
2073 | { | |
2b835d68 | 2074 | if (generate) |
a406f566 | 2075 | emit_constant_insn (cond, |
f676971a | 2076 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2077 | gen_rtx_MINUS (mode, GEN_INT (val), |
2078 | source))); | |
e2c671ba RE |
2079 | return 1; |
2080 | } | |
2081 | can_negate = 1; | |
2082 | ||
2083 | break; | |
2084 | ||
2085 | default: | |
e6d29d15 | 2086 | gcc_unreachable (); |
e2c671ba RE |
2087 | } |
2088 | ||
6354dc9b | 2089 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
2090 | if (const_ok_for_arm (val) |
2091 | || (can_negate_initial && const_ok_for_arm (-val)) | |
2092 | || (can_invert && const_ok_for_arm (~val))) | |
2093 | { | |
2b835d68 | 2094 | if (generate) |
a406f566 MM |
2095 | emit_constant_insn (cond, |
2096 | gen_rtx_SET (VOIDmode, target, | |
f676971a | 2097 | (source |
a406f566 MM |
2098 | ? gen_rtx_fmt_ee (code, mode, source, |
2099 | GEN_INT (val)) | |
2100 | : GEN_INT (val)))); | |
e2c671ba RE |
2101 | return 1; |
2102 | } | |
2103 | ||
e2c671ba | 2104 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 2105 | optimizations. */ |
e2c671ba RE |
2106 | for (i = 31; i >= 0; i--) |
2107 | { | |
2108 | if ((remainder & (1 << i)) == 0) | |
2109 | clear_sign_bit_copies++; | |
2110 | else | |
2111 | break; | |
2112 | } | |
2113 | ||
2114 | for (i = 31; i >= 0; i--) | |
2115 | { | |
2116 | if ((remainder & (1 << i)) != 0) | |
2117 | set_sign_bit_copies++; | |
2118 | else | |
2119 | break; | |
2120 | } | |
2121 | ||
2122 | for (i = 0; i <= 31; i++) | |
2123 | { | |
2124 | if ((remainder & (1 << i)) == 0) | |
2125 | clear_zero_bit_copies++; | |
2126 | else | |
2127 | break; | |
2128 | } | |
2129 | ||
2130 | for (i = 0; i <= 31; i++) | |
2131 | { | |
2132 | if ((remainder & (1 << i)) != 0) | |
2133 | set_zero_bit_copies++; | |
2134 | else | |
2135 | break; | |
2136 | } | |
2137 | ||
2138 | switch (code) | |
2139 | { | |
2140 | case SET: | |
5b3e6663 PB |
2141 | /* See if we can use movw. */ |
2142 | if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0) | |
2143 | { | |
2144 | if (generate) | |
2145 | emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target, | |
2146 | GEN_INT (val))); | |
2147 | return 1; | |
2148 | } | |
2149 | ||
e2c671ba RE |
2150 | /* See if we can do this by sign_extending a constant that is known |
2151 | to be negative. This is a good, way of doing it, since the shift | |
2152 | may well merge into a subsequent insn. */ | |
2153 | if (set_sign_bit_copies > 1) | |
2154 | { | |
2155 | if (const_ok_for_arm | |
f676971a | 2156 | (temp1 = ARM_SIGN_EXTEND (remainder |
e2c671ba RE |
2157 | << (set_sign_bit_copies - 1)))) |
2158 | { | |
2b835d68 RE |
2159 | if (generate) |
2160 | { | |
d499463f | 2161 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 | 2162 | emit_constant_insn (cond, |
f676971a | 2163 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 MM |
2164 | GEN_INT (temp1))); |
2165 | emit_constant_insn (cond, | |
f676971a | 2166 | gen_ashrsi3 (target, new_src, |
a406f566 | 2167 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2168 | } |
e2c671ba RE |
2169 | return 2; |
2170 | } | |
2171 | /* For an inverted constant, we will need to set the low bits, | |
2172 | these will be shifted out of harm's way. */ | |
2173 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
2174 | if (const_ok_for_arm (~temp1)) | |
2175 | { | |
2b835d68 RE |
2176 | if (generate) |
2177 | { | |
d499463f | 2178 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 MM |
2179 | emit_constant_insn (cond, |
2180 | gen_rtx_SET (VOIDmode, new_src, | |
2181 | GEN_INT (temp1))); | |
2182 | emit_constant_insn (cond, | |
f676971a | 2183 | gen_ashrsi3 (target, new_src, |
a406f566 | 2184 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2185 | } |
e2c671ba RE |
2186 | return 2; |
2187 | } | |
2188 | } | |
2189 | ||
c87e6352 RE |
2190 | /* See if we can calculate the value as the difference between two |
2191 | valid immediates. */ | |
2192 | if (clear_sign_bit_copies + clear_zero_bit_copies <= 16) | |
2193 | { | |
2194 | int topshift = clear_sign_bit_copies & ~1; | |
2195 | ||
fa2c88a0 RE |
2196 | temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift)) |
2197 | & (0xff000000 >> topshift)); | |
c87e6352 RE |
2198 | |
2199 | /* If temp1 is zero, then that means the 9 most significant | |
2200 | bits of remainder were 1 and we've caused it to overflow. | |
2201 | When topshift is 0 we don't need to do anything since we | |
2202 | can borrow from 'bit 32'. */ | |
2203 | if (temp1 == 0 && topshift != 0) | |
2204 | temp1 = 0x80000000 >> (topshift - 1); | |
2205 | ||
fa2c88a0 | 2206 | temp2 = ARM_SIGN_EXTEND (temp1 - remainder); |
e0b92319 | 2207 | |
c87e6352 RE |
2208 | if (const_ok_for_arm (temp2)) |
2209 | { | |
2210 | if (generate) | |
2211 | { | |
2212 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; | |
2213 | emit_constant_insn (cond, | |
2214 | gen_rtx_SET (VOIDmode, new_src, | |
2215 | GEN_INT (temp1))); | |
2216 | emit_constant_insn (cond, | |
2217 | gen_addsi3 (target, new_src, | |
2218 | GEN_INT (-temp2))); | |
2219 | } | |
2220 | ||
2221 | return 2; | |
2222 | } | |
2223 | } | |
2224 | ||
e2c671ba RE |
2225 | /* See if we can generate this by setting the bottom (or the top) |
2226 | 16 bits, and then shifting these into the other half of the | |
2227 | word. We only look for the simplest cases, to do more would cost | |
2228 | too much. Be careful, however, not to generate this when the | |
2229 | alternative would take fewer insns. */ | |
30cf4896 | 2230 | if (val & 0xffff0000) |
e2c671ba | 2231 | { |
30cf4896 | 2232 | temp1 = remainder & 0xffff0000; |
e2c671ba RE |
2233 | temp2 = remainder & 0x0000ffff; |
2234 | ||
6354dc9b | 2235 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
2236 | for (i = 9; i < 24; i++) |
2237 | { | |
30cf4896 | 2238 | if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) |
5895f793 | 2239 | && !const_ok_for_arm (temp2)) |
e2c671ba | 2240 | { |
d499463f RE |
2241 | rtx new_src = (subtargets |
2242 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2243 | : target); | |
a406f566 | 2244 | insns = arm_gen_constant (code, mode, cond, temp2, new_src, |
2b835d68 | 2245 | source, subtargets, generate); |
e2c671ba | 2246 | source = new_src; |
2b835d68 | 2247 | if (generate) |
f676971a | 2248 | emit_constant_insn |
a406f566 MM |
2249 | (cond, |
2250 | gen_rtx_SET | |
2251 | (VOIDmode, target, | |
2252 | gen_rtx_IOR (mode, | |
2253 | gen_rtx_ASHIFT (mode, source, | |
2254 | GEN_INT (i)), | |
2255 | source))); | |
e2c671ba RE |
2256 | return insns + 1; |
2257 | } | |
2258 | } | |
2259 | ||
6354dc9b | 2260 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
2261 | for (i = 17; i < 24; i++) |
2262 | { | |
2263 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 2264 | && !const_ok_for_arm (temp1)) |
e2c671ba | 2265 | { |
d499463f RE |
2266 | rtx new_src = (subtargets |
2267 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2268 | : target); | |
a406f566 | 2269 | insns = arm_gen_constant (code, mode, cond, temp1, new_src, |
2b835d68 | 2270 | source, subtargets, generate); |
e2c671ba | 2271 | source = new_src; |
2b835d68 | 2272 | if (generate) |
a406f566 MM |
2273 | emit_constant_insn |
2274 | (cond, | |
2275 | gen_rtx_SET (VOIDmode, target, | |
43cffd11 RE |
2276 | gen_rtx_IOR |
2277 | (mode, | |
2278 | gen_rtx_LSHIFTRT (mode, source, | |
2279 | GEN_INT (i)), | |
2280 | source))); | |
e2c671ba RE |
2281 | return insns + 1; |
2282 | } | |
2283 | } | |
2284 | } | |
2285 | break; | |
2286 | ||
2287 | case IOR: | |
2288 | case XOR: | |
7b64da89 RE |
2289 | /* If we have IOR or XOR, and the constant can be loaded in a |
2290 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
2291 | then this can be done in two instructions instead of 3-4. */ |
2292 | if (subtargets | |
d499463f | 2293 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 2294 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 2295 | { |
5895f793 | 2296 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2297 | { |
2b835d68 RE |
2298 | if (generate) |
2299 | { | |
2300 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 2301 | |
a406f566 | 2302 | emit_constant_insn (cond, |
f676971a | 2303 | gen_rtx_SET (VOIDmode, sub, |
a406f566 MM |
2304 | GEN_INT (val))); |
2305 | emit_constant_insn (cond, | |
f676971a | 2306 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2307 | gen_rtx_fmt_ee (code, mode, |
2308 | source, sub))); | |
2b835d68 | 2309 | } |
e2c671ba RE |
2310 | return 2; |
2311 | } | |
2312 | } | |
2313 | ||
2314 | if (code == XOR) | |
2315 | break; | |
2316 | ||
2317 | if (set_sign_bit_copies > 8 | |
2318 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
2319 | { | |
2b835d68 RE |
2320 | if (generate) |
2321 | { | |
2322 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2323 | rtx shift = GEN_INT (set_sign_bit_copies); | |
2324 | ||
f676971a | 2325 | emit_constant_insn |
a406f566 MM |
2326 | (cond, |
2327 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2328 | gen_rtx_NOT (mode, |
a406f566 | 2329 | gen_rtx_ASHIFT (mode, |
f676971a | 2330 | source, |
a406f566 | 2331 | shift)))); |
f676971a | 2332 | emit_constant_insn |
a406f566 MM |
2333 | (cond, |
2334 | gen_rtx_SET (VOIDmode, target, | |
2335 | gen_rtx_NOT (mode, | |
2336 | gen_rtx_LSHIFTRT (mode, sub, | |
2337 | shift)))); | |
2b835d68 | 2338 | } |
e2c671ba RE |
2339 | return 2; |
2340 | } | |
2341 | ||
2342 | if (set_zero_bit_copies > 8 | |
2343 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
2344 | { | |
2b835d68 RE |
2345 | if (generate) |
2346 | { | |
2347 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2348 | rtx shift = GEN_INT (set_zero_bit_copies); | |
2349 | ||
a406f566 MM |
2350 | emit_constant_insn |
2351 | (cond, | |
2352 | gen_rtx_SET (VOIDmode, sub, | |
2353 | gen_rtx_NOT (mode, | |
2354 | gen_rtx_LSHIFTRT (mode, | |
2355 | source, | |
2356 | shift)))); | |
f676971a | 2357 | emit_constant_insn |
a406f566 MM |
2358 | (cond, |
2359 | gen_rtx_SET (VOIDmode, target, | |
2360 | gen_rtx_NOT (mode, | |
2361 | gen_rtx_ASHIFT (mode, sub, | |
2362 | shift)))); | |
2b835d68 | 2363 | } |
e2c671ba RE |
2364 | return 2; |
2365 | } | |
2366 | ||
5895f793 | 2367 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2368 | { |
2b835d68 RE |
2369 | if (generate) |
2370 | { | |
2371 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
a406f566 MM |
2372 | emit_constant_insn (cond, |
2373 | gen_rtx_SET (VOIDmode, sub, | |
2374 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
2375 | source = sub; |
2376 | if (subtargets) | |
2377 | sub = gen_reg_rtx (mode); | |
a406f566 MM |
2378 | emit_constant_insn (cond, |
2379 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2380 | gen_rtx_AND (mode, source, |
a406f566 MM |
2381 | GEN_INT (temp1)))); |
2382 | emit_constant_insn (cond, | |
2383 | gen_rtx_SET (VOIDmode, target, | |
2384 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 2385 | } |
e2c671ba RE |
2386 | return 3; |
2387 | } | |
2388 | break; | |
2389 | ||
2390 | case AND: | |
2391 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
2392 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
2393 | { | |
30cf4896 | 2394 | HOST_WIDE_INT shift_mask = ((0xffffffff |
e2c671ba | 2395 | << (32 - clear_sign_bit_copies)) |
30cf4896 | 2396 | & 0xffffffff); |
e2c671ba | 2397 | |
30cf4896 | 2398 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 2399 | { |
2b835d68 RE |
2400 | if (generate) |
2401 | { | |
d499463f | 2402 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
f676971a | 2403 | insns = arm_gen_constant (AND, mode, cond, |
a406f566 | 2404 | remainder | shift_mask, |
d499463f RE |
2405 | new_src, source, subtargets, 1); |
2406 | source = new_src; | |
2b835d68 RE |
2407 | } |
2408 | else | |
d499463f RE |
2409 | { |
2410 | rtx targ = subtargets ? NULL_RTX : target; | |
a406f566 MM |
2411 | insns = arm_gen_constant (AND, mode, cond, |
2412 | remainder | shift_mask, | |
d499463f RE |
2413 | targ, source, subtargets, 0); |
2414 | } | |
2b835d68 RE |
2415 | } |
2416 | ||
2417 | if (generate) | |
2418 | { | |
d499463f RE |
2419 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2420 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
2421 | ||
2422 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
2423 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
2424 | } |
2425 | ||
e2c671ba RE |
2426 | return insns + 2; |
2427 | } | |
2428 | ||
2429 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
2430 | { | |
2431 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
f676971a | 2432 | |
30cf4896 | 2433 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 2434 | { |
2b835d68 RE |
2435 | if (generate) |
2436 | { | |
d499463f RE |
2437 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2438 | ||
a406f566 MM |
2439 | insns = arm_gen_constant (AND, mode, cond, |
2440 | remainder | shift_mask, | |
d499463f RE |
2441 | new_src, source, subtargets, 1); |
2442 | source = new_src; | |
2b835d68 RE |
2443 | } |
2444 | else | |
d499463f RE |
2445 | { |
2446 | rtx targ = subtargets ? NULL_RTX : target; | |
2447 | ||
a406f566 MM |
2448 | insns = arm_gen_constant (AND, mode, cond, |
2449 | remainder | shift_mask, | |
d499463f RE |
2450 | targ, source, subtargets, 0); |
2451 | } | |
2b835d68 RE |
2452 | } |
2453 | ||
2454 | if (generate) | |
2455 | { | |
d499463f RE |
2456 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2457 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
2458 | ||
2459 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
2460 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
2461 | } |
2462 | ||
e2c671ba RE |
2463 | return insns + 2; |
2464 | } | |
2465 | ||
2466 | break; | |
2467 | ||
2468 | default: | |
2469 | break; | |
2470 | } | |
2471 | ||
2472 | for (i = 0; i < 32; i++) | |
2473 | if (remainder & (1 << i)) | |
2474 | num_bits_set++; | |
2475 | ||
2476 | if (code == AND || (can_invert && num_bits_set > 16)) | |
30cf4896 | 2477 | remainder = (~remainder) & 0xffffffff; |
e2c671ba | 2478 | else if (code == PLUS && num_bits_set > 16) |
30cf4896 | 2479 | remainder = (-remainder) & 0xffffffff; |
e2c671ba RE |
2480 | else |
2481 | { | |
2482 | can_invert = 0; | |
2483 | can_negate = 0; | |
2484 | } | |
2485 | ||
2486 | /* Now try and find a way of doing the job in either two or three | |
2487 | instructions. | |
2488 | We start by looking for the largest block of zeros that are aligned on | |
2489 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
2490 | top of the word when we drop off the bottom. | |
5b3e6663 PB |
2491 | In the worst case this code should produce no more than four insns. |
2492 | Thumb-2 constants are shifted, not rotated, so the MSB is always the | |
2493 | best place to start. */ | |
2494 | ||
2495 | /* ??? Use thumb2 replicated constants when the high and low halfwords are | |
2496 | the same. */ | |
e2c671ba RE |
2497 | { |
2498 | int best_start = 0; | |
5b3e6663 | 2499 | if (!TARGET_THUMB2) |
e2c671ba | 2500 | { |
5b3e6663 | 2501 | int best_consecutive_zeros = 0; |
e2c671ba | 2502 | |
5b3e6663 | 2503 | for (i = 0; i < 32; i += 2) |
e2c671ba | 2504 | { |
5b3e6663 PB |
2505 | int consecutive_zeros = 0; |
2506 | ||
2507 | if (!(remainder & (3 << i))) | |
e2c671ba | 2508 | { |
5b3e6663 PB |
2509 | while ((i < 32) && !(remainder & (3 << i))) |
2510 | { | |
2511 | consecutive_zeros += 2; | |
2512 | i += 2; | |
2513 | } | |
2514 | if (consecutive_zeros > best_consecutive_zeros) | |
2515 | { | |
2516 | best_consecutive_zeros = consecutive_zeros; | |
2517 | best_start = i - consecutive_zeros; | |
2518 | } | |
2519 | i -= 2; | |
e2c671ba | 2520 | } |
e2c671ba | 2521 | } |
ceebdb09 | 2522 | |
5b3e6663 PB |
2523 | /* So long as it won't require any more insns to do so, it's |
2524 | desirable to emit a small constant (in bits 0...9) in the last | |
2525 | insn. This way there is more chance that it can be combined with | |
2526 | a later addressing insn to form a pre-indexed load or store | |
2527 | operation. Consider: | |
2528 | ||
2529 | *((volatile int *)0xe0000100) = 1; | |
2530 | *((volatile int *)0xe0000110) = 2; | |
2531 | ||
2532 | We want this to wind up as: | |
2533 | ||
2534 | mov rA, #0xe0000000 | |
2535 | mov rB, #1 | |
2536 | str rB, [rA, #0x100] | |
2537 | mov rB, #2 | |
2538 | str rB, [rA, #0x110] | |
2539 | ||
2540 | rather than having to synthesize both large constants from scratch. | |
2541 | ||
2542 | Therefore, we calculate how many insns would be required to emit | |
2543 | the constant starting from `best_start', and also starting from | |
2544 | zero (i.e. with bit 31 first to be output). If `best_start' doesn't | |
2545 | yield a shorter sequence, we may as well use zero. */ | |
2546 | if (best_start != 0 | |
2547 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
2548 | && (count_insns_for_constant (remainder, 0) <= | |
2549 | count_insns_for_constant (remainder, best_start))) | |
2550 | best_start = 0; | |
2551 | } | |
ceebdb09 PB |
2552 | |
2553 | /* Now start emitting the insns. */ | |
e2c671ba RE |
2554 | i = best_start; |
2555 | do | |
2556 | { | |
2557 | int end; | |
2558 | ||
2559 | if (i <= 0) | |
2560 | i += 32; | |
2561 | if (remainder & (3 << (i - 2))) | |
2562 | { | |
2563 | end = i - 8; | |
2564 | if (end < 0) | |
2565 | end += 32; | |
2566 | temp1 = remainder & ((0x0ff << end) | |
2567 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
2568 | remainder &= ~temp1; | |
2569 | ||
d499463f | 2570 | if (generate) |
e2c671ba | 2571 | { |
9503f3d1 RH |
2572 | rtx new_src, temp1_rtx; |
2573 | ||
2574 | if (code == SET || code == MINUS) | |
2575 | { | |
2576 | new_src = (subtargets ? gen_reg_rtx (mode) : target); | |
96ae8197 | 2577 | if (can_invert && code != MINUS) |
9503f3d1 RH |
2578 | temp1 = ~temp1; |
2579 | } | |
2580 | else | |
2581 | { | |
96ae8197 | 2582 | if (remainder && subtargets) |
9503f3d1 | 2583 | new_src = gen_reg_rtx (mode); |
96ae8197 NC |
2584 | else |
2585 | new_src = target; | |
9503f3d1 RH |
2586 | if (can_invert) |
2587 | temp1 = ~temp1; | |
2588 | else if (can_negate) | |
2589 | temp1 = -temp1; | |
2590 | } | |
2591 | ||
2592 | temp1 = trunc_int_for_mode (temp1, mode); | |
2593 | temp1_rtx = GEN_INT (temp1); | |
d499463f RE |
2594 | |
2595 | if (code == SET) | |
9503f3d1 | 2596 | ; |
d499463f | 2597 | else if (code == MINUS) |
9503f3d1 | 2598 | temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); |
d499463f | 2599 | else |
9503f3d1 RH |
2600 | temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); |
2601 | ||
a406f566 | 2602 | emit_constant_insn (cond, |
f676971a | 2603 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 | 2604 | temp1_rtx)); |
d499463f | 2605 | source = new_src; |
e2c671ba RE |
2606 | } |
2607 | ||
d499463f RE |
2608 | if (code == SET) |
2609 | { | |
2610 | can_invert = 0; | |
2611 | code = PLUS; | |
2612 | } | |
2613 | else if (code == MINUS) | |
2614 | code = PLUS; | |
2615 | ||
e2c671ba | 2616 | insns++; |
5b3e6663 PB |
2617 | if (TARGET_ARM) |
2618 | i -= 6; | |
2619 | else | |
2620 | i -= 7; | |
e2c671ba | 2621 | } |
7a085dce | 2622 | /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary |
5b3e6663 PB |
2623 | shifts. */ |
2624 | if (TARGET_ARM) | |
2625 | i -= 2; | |
2626 | else | |
2627 | i--; | |
1d6e90ac NC |
2628 | } |
2629 | while (remainder); | |
e2c671ba | 2630 | } |
1d6e90ac | 2631 | |
e2c671ba RE |
2632 | return insns; |
2633 | } | |
2634 | ||
bd9c7e23 RE |
2635 | /* Canonicalize a comparison so that we are more likely to recognize it. |
2636 | This can be done for a few constant compares, where we can make the | |
2637 | immediate value easier to load. */ | |
1d6e90ac | 2638 | |
bd9c7e23 | 2639 | enum rtx_code |
a14b88bb PB |
2640 | arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode, |
2641 | rtx * op1) | |
bd9c7e23 | 2642 | { |
ad076f4e | 2643 | unsigned HOST_WIDE_INT i = INTVAL (*op1); |
a14b88bb PB |
2644 | unsigned HOST_WIDE_INT maxval; |
2645 | maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; | |
bd9c7e23 RE |
2646 | |
2647 | switch (code) | |
2648 | { | |
2649 | case EQ: | |
2650 | case NE: | |
2651 | return code; | |
2652 | ||
2653 | case GT: | |
2654 | case LE: | |
a14b88bb | 2655 | if (i != maxval |
5895f793 | 2656 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 | 2657 | { |
5895f793 | 2658 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
2659 | return code == GT ? GE : LT; |
2660 | } | |
2661 | break; | |
2662 | ||
2663 | case GE: | |
2664 | case LT: | |
a14b88bb | 2665 | if (i != ~maxval |
5895f793 | 2666 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 2667 | { |
5895f793 | 2668 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
2669 | return code == GE ? GT : LE; |
2670 | } | |
2671 | break; | |
2672 | ||
2673 | case GTU: | |
2674 | case LEU: | |
30cf4896 | 2675 | if (i != ~((unsigned HOST_WIDE_INT) 0) |
5895f793 | 2676 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 RE |
2677 | { |
2678 | *op1 = GEN_INT (i + 1); | |
2679 | return code == GTU ? GEU : LTU; | |
2680 | } | |
2681 | break; | |
2682 | ||
2683 | case GEU: | |
2684 | case LTU: | |
2685 | if (i != 0 | |
5895f793 | 2686 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
2687 | { |
2688 | *op1 = GEN_INT (i - 1); | |
2689 | return code == GEU ? GTU : LEU; | |
2690 | } | |
2691 | break; | |
2692 | ||
2693 | default: | |
e6d29d15 | 2694 | gcc_unreachable (); |
bd9c7e23 RE |
2695 | } |
2696 | ||
2697 | return code; | |
2698 | } | |
bd9c7e23 | 2699 | |
d4453b7a PB |
2700 | |
2701 | /* Define how to find the value returned by a function. */ | |
2702 | ||
9f7bf991 | 2703 | rtx |
586de218 | 2704 | arm_function_value(const_tree type, const_tree func ATTRIBUTE_UNUSED) |
d4453b7a PB |
2705 | { |
2706 | enum machine_mode mode; | |
2707 | int unsignedp ATTRIBUTE_UNUSED; | |
2708 | rtx r ATTRIBUTE_UNUSED; | |
2709 | ||
d4453b7a PB |
2710 | mode = TYPE_MODE (type); |
2711 | /* Promote integer types. */ | |
2712 | if (INTEGRAL_TYPE_P (type)) | |
2713 | PROMOTE_FUNCTION_MODE (mode, unsignedp, type); | |
866af8a9 JB |
2714 | |
2715 | /* Promotes small structs returned in a register to full-word size | |
2716 | for big-endian AAPCS. */ | |
2717 | if (arm_return_in_msb (type)) | |
2718 | { | |
2719 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
2720 | if (size % UNITS_PER_WORD != 0) | |
2721 | { | |
2722 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; | |
2723 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
2724 | } | |
2725 | } | |
e0b92319 | 2726 | |
d4453b7a PB |
2727 | return LIBCALL_VALUE(mode); |
2728 | } | |
2729 | ||
e0b92319 | 2730 | /* Determine the amount of memory needed to store the possible return |
9f7bf991 RE |
2731 | registers of an untyped call. */ |
2732 | int | |
2733 | arm_apply_result_size (void) | |
2734 | { | |
2735 | int size = 16; | |
2736 | ||
2737 | if (TARGET_ARM) | |
2738 | { | |
2739 | if (TARGET_HARD_FLOAT_ABI) | |
2740 | { | |
2741 | if (TARGET_FPA) | |
2742 | size += 12; | |
2743 | if (TARGET_MAVERICK) | |
2744 | size += 8; | |
2745 | } | |
2746 | if (TARGET_IWMMXT_ABI) | |
2747 | size += 8; | |
2748 | } | |
2749 | ||
2750 | return size; | |
2751 | } | |
d4453b7a | 2752 | |
f5a1b0d2 | 2753 | /* Decide whether a type should be returned in memory (true) |
23668cf7 | 2754 | or in a register (false). This is called as the target hook |
81464b2c | 2755 | TARGET_RETURN_IN_MEMORY. */ |
23668cf7 | 2756 | static bool |
81464b2c | 2757 | arm_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
2b835d68 | 2758 | { |
dc0ba55a JT |
2759 | HOST_WIDE_INT size; |
2760 | ||
88f77cba JB |
2761 | size = int_size_in_bytes (type); |
2762 | ||
2763 | /* Vector values should be returned using ARM registers, not memory (unless | |
2764 | they're over 16 bytes, which will break since we only have four | |
2765 | call-clobbered registers to play with). */ | |
2766 | if (TREE_CODE (type) == VECTOR_TYPE) | |
2767 | return (size < 0 || size > (4 * UNITS_PER_WORD)); | |
2768 | ||
3dd7ab65 JB |
2769 | if (!AGGREGATE_TYPE_P (type) && |
2770 | !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE)) | |
2771 | /* All simple types are returned in registers. | |
2772 | For AAPCS, complex types are treated the same as aggregates. */ | |
d7d01975 | 2773 | return 0; |
dc0ba55a | 2774 | |
5848830f | 2775 | if (arm_abi != ARM_ABI_APCS) |
dc0ba55a | 2776 | { |
5848830f | 2777 | /* ATPCS and later return aggregate types in memory only if they are |
dc0ba55a JT |
2778 | larger than a word (or are variable size). */ |
2779 | return (size < 0 || size > UNITS_PER_WORD); | |
2780 | } | |
f676971a | 2781 | |
6bc82793 | 2782 | /* For the arm-wince targets we choose to be compatible with Microsoft's |
d5b7b3ae RE |
2783 | ARM and Thumb compilers, which always return aggregates in memory. */ |
2784 | #ifndef ARM_WINCE | |
e529bd42 NC |
2785 | /* All structures/unions bigger than one word are returned in memory. |
2786 | Also catch the case where int_size_in_bytes returns -1. In this case | |
6bc82793 | 2787 | the aggregate is either huge or of variable size, and in either case |
e529bd42 | 2788 | we will want to return it via memory and not in a register. */ |
dc0ba55a | 2789 | if (size < 0 || size > UNITS_PER_WORD) |
d7d01975 | 2790 | return 1; |
f676971a | 2791 | |
d7d01975 | 2792 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
2793 | { |
2794 | tree field; | |
2795 | ||
3a2ea258 RE |
2796 | /* For a struct the APCS says that we only return in a register |
2797 | if the type is 'integer like' and every addressable element | |
2798 | has an offset of zero. For practical purposes this means | |
2799 | that the structure can have at most one non bit-field element | |
2800 | and that this element must be the first one in the structure. */ | |
f676971a | 2801 | |
f5a1b0d2 NC |
2802 | /* Find the first field, ignoring non FIELD_DECL things which will |
2803 | have been created by C++. */ | |
2804 | for (field = TYPE_FIELDS (type); | |
2805 | field && TREE_CODE (field) != FIELD_DECL; | |
2806 | field = TREE_CHAIN (field)) | |
2807 | continue; | |
f676971a | 2808 | |
f5a1b0d2 | 2809 | if (field == NULL) |
9e291dbe | 2810 | return 0; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 2811 | |
d5b7b3ae RE |
2812 | /* Check that the first field is valid for returning in a register. */ |
2813 | ||
2814 | /* ... Floats are not allowed */ | |
9e291dbe | 2815 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3a2ea258 RE |
2816 | return 1; |
2817 | ||
d5b7b3ae RE |
2818 | /* ... Aggregates that are not themselves valid for returning in |
2819 | a register are not allowed. */ | |
81464b2c | 2820 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
3a2ea258 | 2821 | return 1; |
6f7ebcbb | 2822 | |
3a2ea258 RE |
2823 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
2824 | since they are not addressable. */ | |
f5a1b0d2 NC |
2825 | for (field = TREE_CHAIN (field); |
2826 | field; | |
2827 | field = TREE_CHAIN (field)) | |
2828 | { | |
2829 | if (TREE_CODE (field) != FIELD_DECL) | |
2830 | continue; | |
f676971a | 2831 | |
5895f793 | 2832 | if (!DECL_BIT_FIELD_TYPE (field)) |
f5a1b0d2 NC |
2833 | return 1; |
2834 | } | |
2b835d68 RE |
2835 | |
2836 | return 0; | |
2837 | } | |
f676971a | 2838 | |
d7d01975 | 2839 | if (TREE_CODE (type) == UNION_TYPE) |
2b835d68 RE |
2840 | { |
2841 | tree field; | |
2842 | ||
2843 | /* Unions can be returned in registers if every element is | |
2844 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
2845 | for (field = TYPE_FIELDS (type); |
2846 | field; | |
2847 | field = TREE_CHAIN (field)) | |
2b835d68 | 2848 | { |
f5a1b0d2 NC |
2849 | if (TREE_CODE (field) != FIELD_DECL) |
2850 | continue; | |
2851 | ||
6cc8c0b3 NC |
2852 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
2853 | return 1; | |
f676971a | 2854 | |
81464b2c | 2855 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
2b835d68 RE |
2856 | return 1; |
2857 | } | |
f676971a | 2858 | |
2b835d68 RE |
2859 | return 0; |
2860 | } | |
f676971a EC |
2861 | #endif /* not ARM_WINCE */ |
2862 | ||
d5b7b3ae | 2863 | /* Return all other types in memory. */ |
2b835d68 RE |
2864 | return 1; |
2865 | } | |
2866 | ||
d6b4baa4 | 2867 | /* Indicate whether or not words of a double are in big-endian order. */ |
3717da94 JT |
2868 | |
2869 | int | |
e32bac5b | 2870 | arm_float_words_big_endian (void) |
3717da94 | 2871 | { |
9b66ebb1 | 2872 | if (TARGET_MAVERICK) |
9b6b54e2 | 2873 | return 0; |
3717da94 JT |
2874 | |
2875 | /* For FPA, float words are always big-endian. For VFP, floats words | |
2876 | follow the memory system mode. */ | |
2877 | ||
9b66ebb1 | 2878 | if (TARGET_FPA) |
3717da94 | 2879 | { |
3717da94 JT |
2880 | return 1; |
2881 | } | |
2882 | ||
2883 | if (TARGET_VFP) | |
2884 | return (TARGET_BIG_END ? 1 : 0); | |
2885 | ||
2886 | return 1; | |
2887 | } | |
2888 | ||
82e9d970 PB |
2889 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
2890 | for a call to a function whose data type is FNTYPE. | |
2891 | For a library call, FNTYPE is NULL. */ | |
2892 | void | |
f676971a | 2893 | arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, |
e32bac5b RE |
2894 | rtx libname ATTRIBUTE_UNUSED, |
2895 | tree fndecl ATTRIBUTE_UNUSED) | |
82e9d970 PB |
2896 | { |
2897 | /* On the ARM, the offset starts at 0. */ | |
29e339b9 | 2898 | pcum->nregs = 0; |
5a9335ef | 2899 | pcum->iwmmxt_nregs = 0; |
5848830f | 2900 | pcum->can_split = true; |
f676971a | 2901 | |
5a9335ef NC |
2902 | /* Varargs vectors are treated the same as long long. |
2903 | named_count avoids having to change the way arm handles 'named' */ | |
2904 | pcum->named_count = 0; | |
2905 | pcum->nargs = 0; | |
2906 | ||
2907 | if (TARGET_REALLY_IWMMXT && fntype) | |
2908 | { | |
2909 | tree fn_arg; | |
2910 | ||
2911 | for (fn_arg = TYPE_ARG_TYPES (fntype); | |
2912 | fn_arg; | |
2913 | fn_arg = TREE_CHAIN (fn_arg)) | |
2914 | pcum->named_count += 1; | |
2915 | ||
2916 | if (! pcum->named_count) | |
2917 | pcum->named_count = INT_MAX; | |
2918 | } | |
82e9d970 PB |
2919 | } |
2920 | ||
5848830f PB |
2921 | |
2922 | /* Return true if mode/type need doubleword alignment. */ | |
2923 | bool | |
2924 | arm_needs_doubleword_align (enum machine_mode mode, tree type) | |
2925 | { | |
65a939f7 PB |
2926 | return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY |
2927 | || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); | |
5848830f PB |
2928 | } |
2929 | ||
2930 | ||
82e9d970 PB |
2931 | /* Determine where to put an argument to a function. |
2932 | Value is zero to push the argument on the stack, | |
2933 | or a hard register in which to store the argument. | |
2934 | ||
2935 | MODE is the argument's machine mode. | |
2936 | TYPE is the data type of the argument (as a tree). | |
2937 | This is null for libcalls where that information may | |
2938 | not be available. | |
2939 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2940 | the preceding args and about the function being called. | |
2941 | NAMED is nonzero if this argument is a named parameter | |
2942 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1d6e90ac | 2943 | |
82e9d970 | 2944 | rtx |
e32bac5b | 2945 | arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
5848830f | 2946 | tree type, int named) |
82e9d970 | 2947 | { |
5848830f PB |
2948 | int nregs; |
2949 | ||
2950 | /* Varargs vectors are treated the same as long long. | |
2951 | named_count avoids having to change the way arm handles 'named' */ | |
2952 | if (TARGET_IWMMXT_ABI | |
f676971a | 2953 | && arm_vector_mode_supported_p (mode) |
5848830f | 2954 | && pcum->named_count > pcum->nargs + 1) |
5a9335ef | 2955 | { |
5848830f PB |
2956 | if (pcum->iwmmxt_nregs <= 9) |
2957 | return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); | |
2958 | else | |
5a9335ef | 2959 | { |
5848830f PB |
2960 | pcum->can_split = false; |
2961 | return NULL_RTX; | |
5a9335ef | 2962 | } |
5a9335ef NC |
2963 | } |
2964 | ||
5848830f PB |
2965 | /* Put doubleword aligned quantities in even register pairs. */ |
2966 | if (pcum->nregs & 1 | |
2967 | && ARM_DOUBLEWORD_ALIGN | |
2968 | && arm_needs_doubleword_align (mode, type)) | |
2969 | pcum->nregs++; | |
2970 | ||
82e9d970 | 2971 | if (mode == VOIDmode) |
25a65198 RS |
2972 | /* Pick an arbitrary value for operand 2 of the call insn. */ |
2973 | return const0_rtx; | |
5848830f | 2974 | |
666c27b9 | 2975 | /* Only allow splitting an arg between regs and memory if all preceding |
5848830f PB |
2976 | args were allocated to regs. For args passed by reference we only count |
2977 | the reference pointer. */ | |
2978 | if (pcum->can_split) | |
2979 | nregs = 1; | |
2980 | else | |
2981 | nregs = ARM_NUM_REGS2 (mode, type); | |
2982 | ||
2983 | if (!named || pcum->nregs + nregs > NUM_ARG_REGS) | |
82e9d970 | 2984 | return NULL_RTX; |
f676971a | 2985 | |
82e9d970 PB |
2986 | return gen_rtx_REG (mode, pcum->nregs); |
2987 | } | |
1741620c | 2988 | |
78a52f11 RH |
2989 | static int |
2990 | arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
2991 | tree type, bool named ATTRIBUTE_UNUSED) | |
2992 | { | |
2993 | int nregs = pcum->nregs; | |
2994 | ||
88f77cba | 2995 | if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode)) |
78a52f11 RH |
2996 | return 0; |
2997 | ||
2998 | if (NUM_ARG_REGS > nregs | |
2999 | && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type)) | |
3000 | && pcum->can_split) | |
3001 | return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
3002 | ||
3003 | return 0; | |
3004 | } | |
3005 | ||
1741620c JD |
3006 | /* Variable sized types are passed by reference. This is a GCC |
3007 | extension to the ARM ABI. */ | |
3008 | ||
8cd5a4e0 RH |
3009 | static bool |
3010 | arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
3011 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
586de218 | 3012 | const_tree type, bool named ATTRIBUTE_UNUSED) |
1741620c JD |
3013 | { |
3014 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
3015 | } | |
82e9d970 | 3016 | \f |
c27ba912 DM |
3017 | /* Encode the current state of the #pragma [no_]long_calls. */ |
3018 | typedef enum | |
82e9d970 | 3019 | { |
6fc0bb99 | 3020 | OFF, /* No #pragma [no_]long_calls is in effect. */ |
c27ba912 DM |
3021 | LONG, /* #pragma long_calls is in effect. */ |
3022 | SHORT /* #pragma no_long_calls is in effect. */ | |
3023 | } arm_pragma_enum; | |
82e9d970 | 3024 | |
c27ba912 | 3025 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 3026 | |
8b97c5f8 | 3027 | void |
e32bac5b | 3028 | arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
82e9d970 | 3029 | { |
8b97c5f8 ZW |
3030 | arm_pragma_long_calls = LONG; |
3031 | } | |
3032 | ||
3033 | void | |
e32bac5b | 3034 | arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
3035 | { |
3036 | arm_pragma_long_calls = SHORT; | |
3037 | } | |
3038 | ||
3039 | void | |
e32bac5b | 3040 | arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
3041 | { |
3042 | arm_pragma_long_calls = OFF; | |
82e9d970 PB |
3043 | } |
3044 | \f | |
91d231cb JM |
3045 | /* Table of machine attributes. */ |
3046 | const struct attribute_spec arm_attribute_table[] = | |
82e9d970 | 3047 | { |
91d231cb | 3048 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
82e9d970 PB |
3049 | /* Function calls made to this symbol must be done indirectly, because |
3050 | it may lie outside of the 26 bit addressing range of a normal function | |
3051 | call. */ | |
91d231cb | 3052 | { "long_call", 0, 0, false, true, true, NULL }, |
82e9d970 PB |
3053 | /* Whereas these functions are always known to reside within the 26 bit |
3054 | addressing range. */ | |
91d231cb | 3055 | { "short_call", 0, 0, false, true, true, NULL }, |
f676971a | 3056 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
91d231cb JM |
3057 | { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, |
3058 | { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, | |
3059 | { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
3060 | #ifdef ARM_PE | |
3061 | /* ARM/PE has three new attributes: | |
3062 | interfacearm - ? | |
3063 | dllexport - for exporting a function/variable that will live in a dll | |
3064 | dllimport - for importing a function/variable from a dll | |
3065 | ||
3066 | Microsoft allows multiple declspecs in one __declspec, separating | |
3067 | them with spaces. We do NOT support this. Instead, use __declspec | |
3068 | multiple times. | |
3069 | */ | |
3070 | { "dllimport", 0, 0, true, false, false, NULL }, | |
3071 | { "dllexport", 0, 0, true, false, false, NULL }, | |
3072 | { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
b2ca3702 MM |
3073 | #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES |
3074 | { "dllimport", 0, 0, false, false, false, handle_dll_attribute }, | |
3075 | { "dllexport", 0, 0, false, false, false, handle_dll_attribute }, | |
04fb56d5 | 3076 | { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute }, |
91d231cb JM |
3077 | #endif |
3078 | { NULL, 0, 0, false, false, false, NULL } | |
3079 | }; | |
6d3d9133 | 3080 | |
91d231cb JM |
3081 | /* Handle an attribute requiring a FUNCTION_DECL; |
3082 | arguments as in struct attribute_spec.handler. */ | |
3083 | static tree | |
e32bac5b RE |
3084 | arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, |
3085 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
3086 | { |
3087 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
3088 | { | |
5c498b10 | 3089 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
91d231cb JM |
3090 | IDENTIFIER_POINTER (name)); |
3091 | *no_add_attrs = true; | |
3092 | } | |
3093 | ||
3094 | return NULL_TREE; | |
3095 | } | |
3096 | ||
3097 | /* Handle an "interrupt" or "isr" attribute; | |
3098 | arguments as in struct attribute_spec.handler. */ | |
3099 | static tree | |
e32bac5b RE |
3100 | arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, |
3101 | bool *no_add_attrs) | |
91d231cb JM |
3102 | { |
3103 | if (DECL_P (*node)) | |
3104 | { | |
3105 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
3106 | { | |
5c498b10 | 3107 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
91d231cb JM |
3108 | IDENTIFIER_POINTER (name)); |
3109 | *no_add_attrs = true; | |
3110 | } | |
3111 | /* FIXME: the argument if any is checked for type attributes; | |
3112 | should it be checked for decl ones? */ | |
3113 | } | |
3114 | else | |
3115 | { | |
3116 | if (TREE_CODE (*node) == FUNCTION_TYPE | |
3117 | || TREE_CODE (*node) == METHOD_TYPE) | |
3118 | { | |
3119 | if (arm_isr_value (args) == ARM_FT_UNKNOWN) | |
3120 | { | |
5c498b10 DD |
3121 | warning (OPT_Wattributes, "%qs attribute ignored", |
3122 | IDENTIFIER_POINTER (name)); | |
91d231cb JM |
3123 | *no_add_attrs = true; |
3124 | } | |
3125 | } | |
3126 | else if (TREE_CODE (*node) == POINTER_TYPE | |
3127 | && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE | |
3128 | || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) | |
3129 | && arm_isr_value (args) != ARM_FT_UNKNOWN) | |
3130 | { | |
8dd16ecc | 3131 | *node = build_variant_type_copy (*node); |
1d6e90ac NC |
3132 | TREE_TYPE (*node) = build_type_attribute_variant |
3133 | (TREE_TYPE (*node), | |
3134 | tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); | |
91d231cb JM |
3135 | *no_add_attrs = true; |
3136 | } | |
3137 | else | |
3138 | { | |
3139 | /* Possibly pass this attribute on from the type to a decl. */ | |
3140 | if (flags & ((int) ATTR_FLAG_DECL_NEXT | |
3141 | | (int) ATTR_FLAG_FUNCTION_NEXT | |
3142 | | (int) ATTR_FLAG_ARRAY_NEXT)) | |
3143 | { | |
3144 | *no_add_attrs = true; | |
3145 | return tree_cons (name, args, NULL_TREE); | |
3146 | } | |
3147 | else | |
3148 | { | |
5c498b10 DD |
3149 | warning (OPT_Wattributes, "%qs attribute ignored", |
3150 | IDENTIFIER_POINTER (name)); | |
91d231cb JM |
3151 | } |
3152 | } | |
3153 | } | |
3154 | ||
3155 | return NULL_TREE; | |
82e9d970 PB |
3156 | } |
3157 | ||
7bff66a7 | 3158 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 MM |
3159 | /* Handle the "notshared" attribute. This attribute is another way of |
3160 | requesting hidden visibility. ARM's compiler supports | |
3161 | "__declspec(notshared)"; we support the same thing via an | |
3162 | attribute. */ | |
3163 | ||
3164 | static tree | |
e0b92319 NC |
3165 | arm_handle_notshared_attribute (tree *node, |
3166 | tree name ATTRIBUTE_UNUSED, | |
3167 | tree args ATTRIBUTE_UNUSED, | |
3168 | int flags ATTRIBUTE_UNUSED, | |
04fb56d5 MM |
3169 | bool *no_add_attrs) |
3170 | { | |
3171 | tree decl = TYPE_NAME (*node); | |
3172 | ||
3173 | if (decl) | |
3174 | { | |
3175 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
3176 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
3177 | *no_add_attrs = false; | |
3178 | } | |
3179 | return NULL_TREE; | |
3180 | } | |
7bff66a7 | 3181 | #endif |
04fb56d5 | 3182 | |
82e9d970 PB |
3183 | /* Return 0 if the attributes for two types are incompatible, 1 if they |
3184 | are compatible, and 2 if they are nearly compatible (which causes a | |
3185 | warning to be generated). */ | |
8d8e52be | 3186 | static int |
3101faab | 3187 | arm_comp_type_attributes (const_tree type1, const_tree type2) |
82e9d970 | 3188 | { |
1cb8d58a | 3189 | int l1, l2, s1, s2; |
f676971a | 3190 | |
82e9d970 PB |
3191 | /* Check for mismatch of non-default calling convention. */ |
3192 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
3193 | return 1; | |
3194 | ||
3195 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
3196 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
3197 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
3198 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
3199 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
3200 | |
3201 | /* Only bother to check if an attribute is defined. */ | |
3202 | if (l1 | l2 | s1 | s2) | |
3203 | { | |
3204 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 3205 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 3206 | return 0; |
82e9d970 | 3207 | |
bd7fc26f NC |
3208 | /* Disallow mixed attributes. */ |
3209 | if ((l1 & s2) || (l2 & s1)) | |
3210 | return 0; | |
3211 | } | |
f676971a | 3212 | |
6d3d9133 NC |
3213 | /* Check for mismatched ISR attribute. */ |
3214 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
3215 | if (! l1) | |
3216 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
3217 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
3218 | if (! l2) | |
3219 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
3220 | if (l1 != l2) | |
3221 | return 0; | |
3222 | ||
bd7fc26f | 3223 | return 1; |
82e9d970 PB |
3224 | } |
3225 | ||
c27ba912 DM |
3226 | /* Assigns default attributes to newly defined type. This is used to |
3227 | set short_call/long_call attributes for function types of | |
3228 | functions defined inside corresponding #pragma scopes. */ | |
8d8e52be | 3229 | static void |
e32bac5b | 3230 | arm_set_default_type_attributes (tree type) |
c27ba912 DM |
3231 | { |
3232 | /* Add __attribute__ ((long_call)) to all functions, when | |
3233 | inside #pragma long_calls or __attribute__ ((short_call)), | |
3234 | when inside #pragma no_long_calls. */ | |
3235 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
3236 | { | |
3237 | tree type_attr_list, attr_name; | |
3238 | type_attr_list = TYPE_ATTRIBUTES (type); | |
3239 | ||
3240 | if (arm_pragma_long_calls == LONG) | |
3241 | attr_name = get_identifier ("long_call"); | |
3242 | else if (arm_pragma_long_calls == SHORT) | |
3243 | attr_name = get_identifier ("short_call"); | |
3244 | else | |
3245 | return; | |
3246 | ||
3247 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
3248 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
3249 | } | |
3250 | } | |
3251 | \f | |
25a65198 RS |
3252 | /* Return true if DECL is known to be linked into section SECTION. */ |
3253 | ||
3254 | static bool | |
3255 | arm_function_in_section_p (tree decl, section *section) | |
c27ba912 | 3256 | { |
25a65198 RS |
3257 | /* We can only be certain about functions defined in the same |
3258 | compilation unit. */ | |
3259 | if (!TREE_STATIC (decl)) | |
3260 | return false; | |
c27ba912 | 3261 | |
25a65198 RS |
3262 | /* Make sure that SYMBOL always binds to the definition in this |
3263 | compilation unit. */ | |
3264 | if (!targetm.binds_local_p (decl)) | |
3265 | return false; | |
c27ba912 | 3266 | |
25a65198 RS |
3267 | /* If DECL_SECTION_NAME is set, assume it is trustworthy. */ |
3268 | if (!DECL_SECTION_NAME (decl)) | |
3269 | { | |
3270 | /* Only cater for unit-at-a-time mode, where we know that the user | |
3271 | cannot later specify a section for DECL. */ | |
3272 | if (!flag_unit_at_a_time) | |
3273 | return false; | |
3274 | ||
3275 | /* Make sure that we will not create a unique section for DECL. */ | |
3276 | if (flag_function_sections || DECL_ONE_ONLY (decl)) | |
3277 | return false; | |
3278 | } | |
3279 | ||
3280 | return function_section (decl) == section; | |
c27ba912 DM |
3281 | } |
3282 | ||
a50aa827 | 3283 | /* Return nonzero if a 32-bit "long_call" should be generated for |
25a65198 RS |
3284 | a call from the current function to DECL. We generate a long_call |
3285 | if the function: | |
c27ba912 DM |
3286 | |
3287 | a. has an __attribute__((long call)) | |
3288 | or b. is within the scope of a #pragma long_calls | |
3289 | or c. the -mlong-calls command line switch has been specified | |
3290 | ||
3291 | However we do not generate a long call if the function: | |
f676971a | 3292 | |
c27ba912 DM |
3293 | d. has an __attribute__ ((short_call)) |
3294 | or e. is inside the scope of a #pragma no_long_calls | |
25a65198 | 3295 | or f. is defined in the same section as the current function. */ |
c27ba912 | 3296 | |
25a65198 RS |
3297 | bool |
3298 | arm_is_long_call_p (tree decl) | |
3299 | { | |
3300 | tree attrs; | |
c27ba912 | 3301 | |
25a65198 RS |
3302 | if (!decl) |
3303 | return TARGET_LONG_CALLS; | |
c27ba912 | 3304 | |
25a65198 RS |
3305 | attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
3306 | if (lookup_attribute ("short_call", attrs)) | |
3307 | return false; | |
c27ba912 | 3308 | |
25a65198 RS |
3309 | /* For "f", be conservative, and only cater for cases in which the |
3310 | whole of the current function is placed in the same section. */ | |
3311 | if (!flag_reorder_blocks_and_partition | |
3312 | && arm_function_in_section_p (decl, current_function_section ())) | |
3313 | return false; | |
a77655b1 | 3314 | |
25a65198 RS |
3315 | if (lookup_attribute ("long_call", attrs)) |
3316 | return true; | |
f676971a | 3317 | |
25a65198 | 3318 | return TARGET_LONG_CALLS; |
c27ba912 | 3319 | } |
f99fce0c | 3320 | |
825dda42 | 3321 | /* Return nonzero if it is ok to make a tail-call to DECL. */ |
4977bab6 | 3322 | static bool |
e32bac5b | 3323 | arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
f99fce0c | 3324 | { |
5b3e6663 | 3325 | unsigned long func_type; |
f99fce0c | 3326 | |
5a9335ef NC |
3327 | if (cfun->machine->sibcall_blocked) |
3328 | return false; | |
3329 | ||
f99fce0c RE |
3330 | /* Never tailcall something for which we have no decl, or if we |
3331 | are in Thumb mode. */ | |
3332 | if (decl == NULL || TARGET_THUMB) | |
4977bab6 | 3333 | return false; |
f99fce0c | 3334 | |
9403b7f7 RS |
3335 | /* The PIC register is live on entry to VxWorks PLT entries, so we |
3336 | must make the call before restoring the PIC register. */ | |
3337 | if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl)) | |
3338 | return false; | |
3339 | ||
f99fce0c | 3340 | /* Cannot tail-call to long calls, since these are out of range of |
25a65198 RS |
3341 | a branch instruction. */ |
3342 | if (arm_is_long_call_p (decl)) | |
4977bab6 | 3343 | return false; |
f99fce0c RE |
3344 | |
3345 | /* If we are interworking and the function is not declared static | |
f676971a | 3346 | then we can't tail-call it unless we know that it exists in this |
f99fce0c | 3347 | compilation unit (since it might be a Thumb routine). */ |
5895f793 | 3348 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
4977bab6 | 3349 | return false; |
f99fce0c | 3350 | |
5b3e6663 | 3351 | func_type = arm_current_func_type (); |
6d3d9133 | 3352 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
5b3e6663 PB |
3353 | if (IS_INTERRUPT (func_type)) |
3354 | return false; | |
3355 | ||
3356 | /* Never tailcall if function may be called with a misaligned SP. */ | |
3357 | if (IS_STACKALIGN (func_type)) | |
4977bab6 | 3358 | return false; |
6d3d9133 | 3359 | |
f99fce0c | 3360 | /* Everything else is ok. */ |
4977bab6 | 3361 | return true; |
f99fce0c RE |
3362 | } |
3363 | ||
82e9d970 | 3364 | \f |
6b990f6b RE |
3365 | /* Addressing mode support functions. */ |
3366 | ||
0b4be7de | 3367 | /* Return nonzero if X is a legitimate immediate operand when compiling |
020a4035 | 3368 | for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */ |
32de079a | 3369 | int |
e32bac5b | 3370 | legitimate_pic_operand_p (rtx x) |
32de079a | 3371 | { |
020a4035 RE |
3372 | if (GET_CODE (x) == SYMBOL_REF |
3373 | || (GET_CODE (x) == CONST | |
3374 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3375 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) | |
32de079a RE |
3376 | return 0; |
3377 | ||
3378 | return 1; | |
3379 | } | |
3380 | ||
9403b7f7 RS |
3381 | /* Record that the current function needs a PIC register. Initialize |
3382 | cfun->machine->pic_reg if we have not already done so. */ | |
3383 | ||
3384 | static void | |
3385 | require_pic_register (void) | |
3386 | { | |
3387 | /* A lot of the logic here is made obscure by the fact that this | |
3388 | routine gets called as part of the rtx cost estimation process. | |
3389 | We don't want those calls to affect any assumptions about the real | |
3390 | function; and further, we can't call entry_of_function() until we | |
3391 | start the real expansion process. */ | |
e3b5732b | 3392 | if (!crtl->uses_pic_offset_table) |
9403b7f7 | 3393 | { |
b3a13419 | 3394 | gcc_assert (can_create_pseudo_p ()); |
9403b7f7 RS |
3395 | if (arm_pic_register != INVALID_REGNUM) |
3396 | { | |
3397 | cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); | |
3398 | ||
3399 | /* Play games to avoid marking the function as needing pic | |
3400 | if we are being called as part of the cost-estimation | |
3401 | process. */ | |
3402 | if (current_ir_type () != IR_GIMPLE) | |
e3b5732b | 3403 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
3404 | } |
3405 | else | |
3406 | { | |
3407 | rtx seq; | |
3408 | ||
3409 | cfun->machine->pic_reg = gen_reg_rtx (Pmode); | |
3410 | ||
3411 | /* Play games to avoid marking the function as needing pic | |
3412 | if we are being called as part of the cost-estimation | |
3413 | process. */ | |
3414 | if (current_ir_type () != IR_GIMPLE) | |
3415 | { | |
e3b5732b | 3416 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
3417 | start_sequence (); |
3418 | ||
3419 | arm_load_pic_register (0UL); | |
3420 | ||
3421 | seq = get_insns (); | |
3422 | end_sequence (); | |
3423 | emit_insn_after (seq, entry_of_function ()); | |
3424 | } | |
3425 | } | |
3426 | } | |
3427 | } | |
3428 | ||
32de079a | 3429 | rtx |
e32bac5b | 3430 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
32de079a | 3431 | { |
a3c48721 RE |
3432 | if (GET_CODE (orig) == SYMBOL_REF |
3433 | || GET_CODE (orig) == LABEL_REF) | |
32de079a RE |
3434 | { |
3435 | rtx pic_ref, address; | |
3436 | rtx insn; | |
3437 | int subregs = 0; | |
3438 | ||
9403b7f7 RS |
3439 | /* If this function doesn't have a pic register, create one now. */ |
3440 | require_pic_register (); | |
020a4035 | 3441 | |
32de079a RE |
3442 | if (reg == 0) |
3443 | { | |
b3a13419 | 3444 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 3445 | reg = gen_reg_rtx (Pmode); |
32de079a RE |
3446 | |
3447 | subregs = 1; | |
3448 | } | |
3449 | ||
32de079a RE |
3450 | if (subregs) |
3451 | address = gen_reg_rtx (Pmode); | |
3452 | else | |
3453 | address = reg; | |
3454 | ||
4bec9f7d NC |
3455 | if (TARGET_ARM) |
3456 | emit_insn (gen_pic_load_addr_arm (address, orig)); | |
5b3e6663 PB |
3457 | else if (TARGET_THUMB2) |
3458 | emit_insn (gen_pic_load_addr_thumb2 (address, orig)); | |
3459 | else /* TARGET_THUMB1 */ | |
3460 | emit_insn (gen_pic_load_addr_thumb1 (address, orig)); | |
32de079a | 3461 | |
9403b7f7 RS |
3462 | /* VxWorks does not impose a fixed gap between segments; the run-time |
3463 | gap can be different from the object-file gap. We therefore can't | |
3464 | use GOTOFF unless we are absolutely sure that the symbol is in the | |
3465 | same segment as the GOT. Unfortunately, the flexibility of linker | |
3466 | scripts means that we can't be sure of that in general, so assume | |
3467 | that GOTOFF is never valid on VxWorks. */ | |
14f583b8 | 3468 | if ((GET_CODE (orig) == LABEL_REF |
f676971a | 3469 | || (GET_CODE (orig) == SYMBOL_REF && |
94428622 | 3470 | SYMBOL_REF_LOCAL_P (orig))) |
9403b7f7 RS |
3471 | && NEED_GOT_RELOC |
3472 | && !TARGET_VXWORKS_RTP) | |
020a4035 | 3473 | pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address); |
a3c48721 RE |
3474 | else |
3475 | { | |
542a8afa | 3476 | pic_ref = gen_const_mem (Pmode, |
020a4035 | 3477 | gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, |
542a8afa | 3478 | address)); |
a3c48721 RE |
3479 | } |
3480 | ||
32de079a | 3481 | insn = emit_move_insn (reg, pic_ref); |
96a3900d | 3482 | |
32de079a RE |
3483 | /* Put a REG_EQUAL note on this insn, so that it can be optimized |
3484 | by loop. */ | |
bd94cb6e SB |
3485 | set_unique_reg_note (insn, REG_EQUAL, orig); |
3486 | ||
32de079a RE |
3487 | return reg; |
3488 | } | |
3489 | else if (GET_CODE (orig) == CONST) | |
3490 | { | |
3491 | rtx base, offset; | |
3492 | ||
3493 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
020a4035 | 3494 | && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg) |
32de079a RE |
3495 | return orig; |
3496 | ||
d3585b76 DJ |
3497 | if (GET_CODE (XEXP (orig, 0)) == UNSPEC |
3498 | && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS) | |
3499 | return orig; | |
3500 | ||
32de079a RE |
3501 | if (reg == 0) |
3502 | { | |
b3a13419 | 3503 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 3504 | reg = gen_reg_rtx (Pmode); |
32de079a RE |
3505 | } |
3506 | ||
e6d29d15 | 3507 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
e0b92319 | 3508 | |
e6d29d15 NS |
3509 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
3510 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
3511 | base == reg ? 0 : reg); | |
32de079a RE |
3512 | |
3513 | if (GET_CODE (offset) == CONST_INT) | |
3514 | { | |
3515 | /* The base register doesn't really matter, we only want to | |
3516 | test the index for the appropriate mode. */ | |
1e1ab407 | 3517 | if (!arm_legitimate_index_p (mode, offset, SET, 0)) |
6b990f6b | 3518 | { |
b3a13419 | 3519 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 3520 | offset = force_reg (Pmode, offset); |
6b990f6b | 3521 | } |
32de079a | 3522 | |
32de079a | 3523 | if (GET_CODE (offset) == CONST_INT) |
ed8908e7 | 3524 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
3525 | } |
3526 | ||
3527 | if (GET_MODE_SIZE (mode) > 4 | |
3528 | && (GET_MODE_CLASS (mode) == MODE_INT | |
3529 | || TARGET_SOFT_FLOAT)) | |
3530 | { | |
3531 | emit_insn (gen_addsi3 (reg, base, offset)); | |
3532 | return reg; | |
3533 | } | |
3534 | ||
43cffd11 | 3535 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a | 3536 | } |
32de079a RE |
3537 | |
3538 | return orig; | |
3539 | } | |
3540 | ||
57934c39 | 3541 | |
5b3e6663 | 3542 | /* Find a spare register to use during the prolog of a function. */ |
57934c39 PB |
3543 | |
3544 | static int | |
b279b20a | 3545 | thumb_find_work_register (unsigned long pushed_regs_mask) |
57934c39 PB |
3546 | { |
3547 | int reg; | |
3548 | ||
b279b20a NC |
3549 | /* Check the argument registers first as these are call-used. The |
3550 | register allocation order means that sometimes r3 might be used | |
3551 | but earlier argument registers might not, so check them all. */ | |
3552 | for (reg = LAST_ARG_REGNUM; reg >= 0; reg --) | |
6fb5fa3c | 3553 | if (!df_regs_ever_live_p (reg)) |
b279b20a NC |
3554 | return reg; |
3555 | ||
3556 | /* Before going on to check the call-saved registers we can try a couple | |
3557 | more ways of deducing that r3 is available. The first is when we are | |
3558 | pushing anonymous arguments onto the stack and we have less than 4 | |
3559 | registers worth of fixed arguments(*). In this case r3 will be part of | |
3560 | the variable argument list and so we can be sure that it will be | |
3561 | pushed right at the start of the function. Hence it will be available | |
3562 | for the rest of the prologue. | |
38173d38 | 3563 | (*): ie crtl->args.pretend_args_size is greater than 0. */ |
b279b20a | 3564 | if (cfun->machine->uses_anonymous_args |
38173d38 | 3565 | && crtl->args.pretend_args_size > 0) |
57934c39 PB |
3566 | return LAST_ARG_REGNUM; |
3567 | ||
b279b20a NC |
3568 | /* The other case is when we have fixed arguments but less than 4 registers |
3569 | worth. In this case r3 might be used in the body of the function, but | |
3570 | it is not being used to convey an argument into the function. In theory | |
38173d38 | 3571 | we could just check crtl->args.size to see how many bytes are |
b279b20a NC |
3572 | being passed in argument registers, but it seems that it is unreliable. |
3573 | Sometimes it will have the value 0 when in fact arguments are being | |
3574 | passed. (See testcase execute/20021111-1.c for an example). So we also | |
3575 | check the args_info.nregs field as well. The problem with this field is | |
3576 | that it makes no allowances for arguments that are passed to the | |
3577 | function but which are not used. Hence we could miss an opportunity | |
3578 | when a function has an unused argument in r3. But it is better to be | |
3579 | safe than to be sorry. */ | |
3580 | if (! cfun->machine->uses_anonymous_args | |
38173d38 JH |
3581 | && crtl->args.size >= 0 |
3582 | && crtl->args.size <= (LAST_ARG_REGNUM * UNITS_PER_WORD) | |
f6d2671e | 3583 | && crtl->args.info.nregs < 4) |
b279b20a | 3584 | return LAST_ARG_REGNUM; |
e0b92319 | 3585 | |
b279b20a NC |
3586 | /* Otherwise look for a call-saved register that is going to be pushed. */ |
3587 | for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --) | |
3588 | if (pushed_regs_mask & (1 << reg)) | |
57934c39 PB |
3589 | return reg; |
3590 | ||
5b3e6663 PB |
3591 | if (TARGET_THUMB2) |
3592 | { | |
3593 | /* Thumb-2 can use high regs. */ | |
3594 | for (reg = FIRST_HI_REGNUM; reg < 15; reg ++) | |
3595 | if (pushed_regs_mask & (1 << reg)) | |
3596 | return reg; | |
3597 | } | |
b279b20a NC |
3598 | /* Something went wrong - thumb_compute_save_reg_mask() |
3599 | should have arranged for a suitable register to be pushed. */ | |
e6d29d15 | 3600 | gcc_unreachable (); |
57934c39 PB |
3601 | } |
3602 | ||
f16fe45f | 3603 | static GTY(()) int pic_labelno; |
876f13b0 | 3604 | |
fe013435 PB |
3605 | /* Generate code to load the PIC register. In thumb mode SCRATCH is a |
3606 | low register. */ | |
876f13b0 | 3607 | |
32de079a | 3608 | void |
e55ef7f4 | 3609 | arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) |
32de079a | 3610 | { |
9403b7f7 | 3611 | rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx, pic_reg; |
32de079a RE |
3612 | rtx global_offset_table; |
3613 | ||
e3b5732b | 3614 | if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
3615 | return; |
3616 | ||
e6d29d15 | 3617 | gcc_assert (flag_pic); |
32de079a | 3618 | |
9403b7f7 RS |
3619 | pic_reg = cfun->machine->pic_reg; |
3620 | if (TARGET_VXWORKS_RTP) | |
3621 | { | |
3622 | pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE); | |
3623 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); | |
3624 | emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx)); | |
43cffd11 | 3625 | |
9403b7f7 | 3626 | emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg))); |
f676971a | 3627 | |
9403b7f7 RS |
3628 | pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX); |
3629 | emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp)); | |
4bec9f7d | 3630 | } |
9403b7f7 | 3631 | else |
5b3e6663 | 3632 | { |
9403b7f7 RS |
3633 | /* We use an UNSPEC rather than a LABEL_REF because this label |
3634 | never appears in the code stream. */ | |
3635 | ||
3636 | labelno = GEN_INT (pic_labelno++); | |
3637 | l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
3638 | l1 = gen_rtx_CONST (VOIDmode, l1); | |
3639 | ||
3640 | global_offset_table | |
3641 | = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3642 | /* On the ARM the PC register contains 'dot + 8' at the time of the | |
3643 | addition, on the Thumb it is 'dot + 4'. */ | |
3644 | pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4); | |
3645 | if (GOT_PCREL) | |
5b3e6663 | 3646 | { |
9403b7f7 RS |
3647 | pic_tmp2 = gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx); |
3648 | pic_tmp2 = gen_rtx_CONST (VOIDmode, pic_tmp2); | |
5b3e6663 PB |
3649 | } |
3650 | else | |
9403b7f7 RS |
3651 | pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); |
3652 | ||
3653 | pic_rtx = gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp); | |
3654 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); | |
3655 | ||
3656 | if (TARGET_ARM) | |
5b3e6663 | 3657 | { |
9403b7f7 RS |
3658 | emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx)); |
3659 | emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno)); | |
5b3e6663 | 3660 | } |
9403b7f7 RS |
3661 | else if (TARGET_THUMB2) |
3662 | { | |
3663 | /* Thumb-2 only allows very limited access to the PC. Calculate the | |
3664 | address in a temporary register. */ | |
3665 | if (arm_pic_register != INVALID_REGNUM) | |
3666 | { | |
3667 | pic_tmp = gen_rtx_REG (SImode, | |
3668 | thumb_find_work_register (saved_regs)); | |
3669 | } | |
3670 | else | |
3671 | { | |
b3a13419 | 3672 | gcc_assert (can_create_pseudo_p ()); |
9403b7f7 RS |
3673 | pic_tmp = gen_reg_rtx (Pmode); |
3674 | } | |
5b3e6663 | 3675 | |
9403b7f7 RS |
3676 | emit_insn (gen_pic_load_addr_thumb2 (pic_reg, pic_rtx)); |
3677 | emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno)); | |
3678 | emit_insn (gen_addsi3 (pic_reg, pic_reg, pic_tmp)); | |
3679 | } | |
3680 | else /* TARGET_THUMB1 */ | |
876f13b0 | 3681 | { |
9403b7f7 RS |
3682 | if (arm_pic_register != INVALID_REGNUM |
3683 | && REGNO (pic_reg) > LAST_LO_REGNUM) | |
3684 | { | |
3685 | /* We will have pushed the pic register, so we should always be | |
3686 | able to find a work register. */ | |
3687 | pic_tmp = gen_rtx_REG (SImode, | |
3688 | thumb_find_work_register (saved_regs)); | |
3689 | emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx)); | |
3690 | emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); | |
3691 | } | |
3692 | else | |
3693 | emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx)); | |
3694 | emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); | |
876f13b0 | 3695 | } |
4bec9f7d | 3696 | } |
32de079a | 3697 | |
32de079a RE |
3698 | /* Need to emit this whether or not we obey regdecls, |
3699 | since setjmp/longjmp can cause life info to screw up. */ | |
c41c1387 | 3700 | emit_use (pic_reg); |
32de079a RE |
3701 | } |
3702 | ||
876f13b0 | 3703 | |
6b990f6b RE |
3704 | /* Return nonzero if X is valid as an ARM state addressing register. */ |
3705 | static int | |
e32bac5b | 3706 | arm_address_register_rtx_p (rtx x, int strict_p) |
6b990f6b RE |
3707 | { |
3708 | int regno; | |
3709 | ||
3710 | if (GET_CODE (x) != REG) | |
3711 | return 0; | |
3712 | ||
3713 | regno = REGNO (x); | |
3714 | ||
3715 | if (strict_p) | |
3716 | return ARM_REGNO_OK_FOR_BASE_P (regno); | |
3717 | ||
3718 | return (regno <= LAST_ARM_REGNUM | |
3719 | || regno >= FIRST_PSEUDO_REGISTER | |
3720 | || regno == FRAME_POINTER_REGNUM | |
3721 | || regno == ARG_POINTER_REGNUM); | |
3722 | } | |
3723 | ||
d3585b76 DJ |
3724 | /* Return TRUE if this rtx is the difference of a symbol and a label, |
3725 | and will reduce to a PC-relative relocation in the object file. | |
3726 | Expressions like this can be left alone when generating PIC, rather | |
3727 | than forced through the GOT. */ | |
3728 | static int | |
3729 | pcrel_constant_p (rtx x) | |
3730 | { | |
3731 | if (GET_CODE (x) == MINUS) | |
3732 | return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1)); | |
3733 | ||
3734 | return FALSE; | |
3735 | } | |
3736 | ||
6b990f6b RE |
3737 | /* Return nonzero if X is a valid ARM state address operand. */ |
3738 | int | |
1e1ab407 RE |
3739 | arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer, |
3740 | int strict_p) | |
6b990f6b | 3741 | { |
fdd695fd PB |
3742 | bool use_ldrd; |
3743 | enum rtx_code code = GET_CODE (x); | |
f676971a | 3744 | |
6b990f6b RE |
3745 | if (arm_address_register_rtx_p (x, strict_p)) |
3746 | return 1; | |
3747 | ||
fdd695fd PB |
3748 | use_ldrd = (TARGET_LDRD |
3749 | && (mode == DImode | |
3750 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
3751 | ||
3752 | if (code == POST_INC || code == PRE_DEC | |
3753 | || ((code == PRE_INC || code == POST_DEC) | |
3754 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
6b990f6b RE |
3755 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); |
3756 | ||
fdd695fd | 3757 | else if ((code == POST_MODIFY || code == PRE_MODIFY) |
6b990f6b RE |
3758 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) |
3759 | && GET_CODE (XEXP (x, 1)) == PLUS | |
386d3a16 | 3760 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
fdd695fd PB |
3761 | { |
3762 | rtx addend = XEXP (XEXP (x, 1), 1); | |
3763 | ||
112cdef5 | 3764 | /* Don't allow ldrd post increment by register because it's hard |
fdd695fd PB |
3765 | to fixup invalid register choices. */ |
3766 | if (use_ldrd | |
3767 | && GET_CODE (x) == POST_MODIFY | |
3768 | && GET_CODE (addend) == REG) | |
3769 | return 0; | |
3770 | ||
3771 | return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) | |
3772 | && arm_legitimate_index_p (mode, addend, outer, strict_p)); | |
3773 | } | |
6b990f6b RE |
3774 | |
3775 | /* After reload constants split into minipools will have addresses | |
3776 | from a LABEL_REF. */ | |
0bfb39ef | 3777 | else if (reload_completed |
fdd695fd PB |
3778 | && (code == LABEL_REF |
3779 | || (code == CONST | |
6b990f6b RE |
3780 | && GET_CODE (XEXP (x, 0)) == PLUS |
3781 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
3782 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
3783 | return 1; | |
3784 | ||
88f77cba | 3785 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
6b990f6b RE |
3786 | return 0; |
3787 | ||
fdd695fd | 3788 | else if (code == PLUS) |
6b990f6b RE |
3789 | { |
3790 | rtx xop0 = XEXP (x, 0); | |
3791 | rtx xop1 = XEXP (x, 1); | |
3792 | ||
3793 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 3794 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)) |
6b990f6b | 3795 | || (arm_address_register_rtx_p (xop1, strict_p) |
1e1ab407 | 3796 | && arm_legitimate_index_p (mode, xop0, outer, strict_p))); |
6b990f6b RE |
3797 | } |
3798 | ||
3799 | #if 0 | |
3800 | /* Reload currently can't handle MINUS, so disable this for now */ | |
3801 | else if (GET_CODE (x) == MINUS) | |
3802 | { | |
3803 | rtx xop0 = XEXP (x, 0); | |
3804 | rtx xop1 = XEXP (x, 1); | |
3805 | ||
3806 | return (arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 3807 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)); |
6b990f6b RE |
3808 | } |
3809 | #endif | |
3810 | ||
3811 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
fdd695fd | 3812 | && code == SYMBOL_REF |
6b990f6b RE |
3813 | && CONSTANT_POOL_ADDRESS_P (x) |
3814 | && ! (flag_pic | |
d3585b76 DJ |
3815 | && symbol_mentioned_p (get_pool_constant (x)) |
3816 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
6b990f6b RE |
3817 | return 1; |
3818 | ||
6b990f6b RE |
3819 | return 0; |
3820 | } | |
3821 | ||
5b3e6663 PB |
3822 | /* Return nonzero if X is a valid Thumb-2 address operand. */ |
3823 | int | |
3824 | thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) | |
3825 | { | |
3826 | bool use_ldrd; | |
3827 | enum rtx_code code = GET_CODE (x); | |
3828 | ||
3829 | if (arm_address_register_rtx_p (x, strict_p)) | |
3830 | return 1; | |
3831 | ||
3832 | use_ldrd = (TARGET_LDRD | |
3833 | && (mode == DImode | |
3834 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
3835 | ||
3836 | if (code == POST_INC || code == PRE_DEC | |
3837 | || ((code == PRE_INC || code == POST_DEC) | |
3838 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
3839 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); | |
3840 | ||
3841 | else if ((code == POST_MODIFY || code == PRE_MODIFY) | |
3842 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) | |
3843 | && GET_CODE (XEXP (x, 1)) == PLUS | |
3844 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) | |
3845 | { | |
3846 | /* Thumb-2 only has autoincrement by constant. */ | |
3847 | rtx addend = XEXP (XEXP (x, 1), 1); | |
3848 | HOST_WIDE_INT offset; | |
3849 | ||
3850 | if (GET_CODE (addend) != CONST_INT) | |
3851 | return 0; | |
3852 | ||
3853 | offset = INTVAL(addend); | |
3854 | if (GET_MODE_SIZE (mode) <= 4) | |
3855 | return (offset > -256 && offset < 256); | |
3856 | ||
3857 | return (use_ldrd && offset > -1024 && offset < 1024 | |
3858 | && (offset & 3) == 0); | |
3859 | } | |
3860 | ||
3861 | /* After reload constants split into minipools will have addresses | |
3862 | from a LABEL_REF. */ | |
3863 | else if (reload_completed | |
3864 | && (code == LABEL_REF | |
3865 | || (code == CONST | |
3866 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3867 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
3868 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
3869 | return 1; | |
3870 | ||
88f77cba | 3871 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
5b3e6663 PB |
3872 | return 0; |
3873 | ||
3874 | else if (code == PLUS) | |
3875 | { | |
3876 | rtx xop0 = XEXP (x, 0); | |
3877 | rtx xop1 = XEXP (x, 1); | |
3878 | ||
3879 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
3880 | && thumb2_legitimate_index_p (mode, xop1, strict_p)) | |
3881 | || (arm_address_register_rtx_p (xop1, strict_p) | |
3882 | && thumb2_legitimate_index_p (mode, xop0, strict_p))); | |
3883 | } | |
3884 | ||
3885 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
3886 | && code == SYMBOL_REF | |
3887 | && CONSTANT_POOL_ADDRESS_P (x) | |
3888 | && ! (flag_pic | |
3889 | && symbol_mentioned_p (get_pool_constant (x)) | |
3890 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
3891 | return 1; | |
3892 | ||
3893 | return 0; | |
3894 | } | |
3895 | ||
6b990f6b RE |
3896 | /* Return nonzero if INDEX is valid for an address index operand in |
3897 | ARM state. */ | |
3898 | static int | |
1e1ab407 RE |
3899 | arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, |
3900 | int strict_p) | |
6b990f6b RE |
3901 | { |
3902 | HOST_WIDE_INT range; | |
3903 | enum rtx_code code = GET_CODE (index); | |
3904 | ||
778ebdd9 PB |
3905 | /* Standard coprocessor addressing modes. */ |
3906 | if (TARGET_HARD_FLOAT | |
3907 | && (TARGET_FPA || TARGET_MAVERICK) | |
3908 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
3909 | || (TARGET_MAVERICK && mode == DImode))) | |
6b990f6b RE |
3910 | return (code == CONST_INT && INTVAL (index) < 1024 |
3911 | && INTVAL (index) > -1024 | |
3912 | && (INTVAL (index) & 3) == 0); | |
3913 | ||
88f77cba JB |
3914 | if (TARGET_NEON |
3915 | && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | |
3916 | return (code == CONST_INT | |
3917 | && INTVAL (index) < 1016 | |
3918 | && INTVAL (index) > -1024 | |
3919 | && (INTVAL (index) & 3) == 0); | |
3920 | ||
5a9335ef NC |
3921 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) |
3922 | return (code == CONST_INT | |
3657dc3e PB |
3923 | && INTVAL (index) < 1024 |
3924 | && INTVAL (index) > -1024 | |
3925 | && (INTVAL (index) & 3) == 0); | |
5a9335ef | 3926 | |
fdd695fd PB |
3927 | if (arm_address_register_rtx_p (index, strict_p) |
3928 | && (GET_MODE_SIZE (mode) <= 4)) | |
3929 | return 1; | |
3930 | ||
3931 | if (mode == DImode || mode == DFmode) | |
3932 | { | |
3933 | if (code == CONST_INT) | |
3934 | { | |
3935 | HOST_WIDE_INT val = INTVAL (index); | |
3936 | ||
3937 | if (TARGET_LDRD) | |
3938 | return val > -256 && val < 256; | |
3939 | else | |
f372c932 | 3940 | return val > -4096 && val < 4092; |
fdd695fd PB |
3941 | } |
3942 | ||
3943 | return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p); | |
3944 | } | |
3945 | ||
6b990f6b | 3946 | if (GET_MODE_SIZE (mode) <= 4 |
1e1ab407 RE |
3947 | && ! (arm_arch4 |
3948 | && (mode == HImode | |
3949 | || (mode == QImode && outer == SIGN_EXTEND)))) | |
6b990f6b | 3950 | { |
1e1ab407 RE |
3951 | if (code == MULT) |
3952 | { | |
3953 | rtx xiop0 = XEXP (index, 0); | |
3954 | rtx xiop1 = XEXP (index, 1); | |
3955 | ||
3956 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
3957 | && power_of_two_operand (xiop1, SImode)) | |
3958 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
3959 | && power_of_two_operand (xiop0, SImode))); | |
3960 | } | |
3961 | else if (code == LSHIFTRT || code == ASHIFTRT | |
3962 | || code == ASHIFT || code == ROTATERT) | |
3963 | { | |
3964 | rtx op = XEXP (index, 1); | |
6b990f6b | 3965 | |
1e1ab407 RE |
3966 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) |
3967 | && GET_CODE (op) == CONST_INT | |
3968 | && INTVAL (op) > 0 | |
3969 | && INTVAL (op) <= 31); | |
3970 | } | |
6b990f6b RE |
3971 | } |
3972 | ||
1e1ab407 RE |
3973 | /* For ARM v4 we may be doing a sign-extend operation during the |
3974 | load. */ | |
e1471c91 | 3975 | if (arm_arch4) |
1e1ab407 RE |
3976 | { |
3977 | if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode)) | |
3978 | range = 256; | |
3979 | else | |
3980 | range = 4096; | |
3981 | } | |
e1471c91 RE |
3982 | else |
3983 | range = (mode == HImode) ? 4095 : 4096; | |
6b990f6b RE |
3984 | |
3985 | return (code == CONST_INT | |
3986 | && INTVAL (index) < range | |
3987 | && INTVAL (index) > -range); | |
76a318e9 RE |
3988 | } |
3989 | ||
5b3e6663 PB |
3990 | /* Return true if OP is a valid index scaling factor for Thumb-2 address |
3991 | index operand. i.e. 1, 2, 4 or 8. */ | |
3992 | static bool | |
3993 | thumb2_index_mul_operand (rtx op) | |
3994 | { | |
3995 | HOST_WIDE_INT val; | |
3996 | ||
3997 | if (GET_CODE(op) != CONST_INT) | |
3998 | return false; | |
3999 | ||
4000 | val = INTVAL(op); | |
4001 | return (val == 1 || val == 2 || val == 4 || val == 8); | |
4002 | } | |
4003 | ||
4004 | /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */ | |
4005 | static int | |
4006 | thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) | |
4007 | { | |
4008 | enum rtx_code code = GET_CODE (index); | |
4009 | ||
4010 | /* ??? Combine arm and thumb2 coprocessor addressing modes. */ | |
4011 | /* Standard coprocessor addressing modes. */ | |
4012 | if (TARGET_HARD_FLOAT | |
4013 | && (TARGET_FPA || TARGET_MAVERICK) | |
4014 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4015 | || (TARGET_MAVERICK && mode == DImode))) | |
4016 | return (code == CONST_INT && INTVAL (index) < 1024 | |
4017 | && INTVAL (index) > -1024 | |
4018 | && (INTVAL (index) & 3) == 0); | |
4019 | ||
4020 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) | |
fe2d934b PB |
4021 | { |
4022 | /* For DImode assume values will usually live in core regs | |
4023 | and only allow LDRD addressing modes. */ | |
4024 | if (!TARGET_LDRD || mode != DImode) | |
4025 | return (code == CONST_INT | |
4026 | && INTVAL (index) < 1024 | |
4027 | && INTVAL (index) > -1024 | |
4028 | && (INTVAL (index) & 3) == 0); | |
4029 | } | |
5b3e6663 | 4030 | |
88f77cba JB |
4031 | if (TARGET_NEON |
4032 | && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | |
4033 | return (code == CONST_INT | |
4034 | && INTVAL (index) < 1016 | |
4035 | && INTVAL (index) > -1024 | |
4036 | && (INTVAL (index) & 3) == 0); | |
4037 | ||
5b3e6663 PB |
4038 | if (arm_address_register_rtx_p (index, strict_p) |
4039 | && (GET_MODE_SIZE (mode) <= 4)) | |
4040 | return 1; | |
4041 | ||
4042 | if (mode == DImode || mode == DFmode) | |
4043 | { | |
4044 | HOST_WIDE_INT val = INTVAL (index); | |
4045 | /* ??? Can we assume ldrd for thumb2? */ | |
4046 | /* Thumb-2 ldrd only has reg+const addressing modes. */ | |
4047 | if (code != CONST_INT) | |
4048 | return 0; | |
4049 | ||
4050 | /* ldrd supports offsets of +-1020. | |
4051 | However the ldr fallback does not. */ | |
4052 | return val > -256 && val < 256 && (val & 3) == 0; | |
4053 | } | |
4054 | ||
4055 | if (code == MULT) | |
4056 | { | |
4057 | rtx xiop0 = XEXP (index, 0); | |
4058 | rtx xiop1 = XEXP (index, 1); | |
4059 | ||
4060 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
4061 | && thumb2_index_mul_operand (xiop1)) | |
4062 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
4063 | && thumb2_index_mul_operand (xiop0))); | |
4064 | } | |
4065 | else if (code == ASHIFT) | |
4066 | { | |
4067 | rtx op = XEXP (index, 1); | |
4068 | ||
4069 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) | |
4070 | && GET_CODE (op) == CONST_INT | |
4071 | && INTVAL (op) > 0 | |
4072 | && INTVAL (op) <= 3); | |
4073 | } | |
4074 | ||
4075 | return (code == CONST_INT | |
4076 | && INTVAL (index) < 4096 | |
4077 | && INTVAL (index) > -256); | |
4078 | } | |
4079 | ||
4080 | /* Return nonzero if X is valid as a 16-bit Thumb state base register. */ | |
76a318e9 | 4081 | static int |
5b3e6663 | 4082 | thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) |
76a318e9 RE |
4083 | { |
4084 | int regno; | |
4085 | ||
4086 | if (GET_CODE (x) != REG) | |
4087 | return 0; | |
4088 | ||
4089 | regno = REGNO (x); | |
4090 | ||
4091 | if (strict_p) | |
5b3e6663 | 4092 | return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode); |
76a318e9 RE |
4093 | |
4094 | return (regno <= LAST_LO_REGNUM | |
07e58265 | 4095 | || regno > LAST_VIRTUAL_REGISTER |
76a318e9 RE |
4096 | || regno == FRAME_POINTER_REGNUM |
4097 | || (GET_MODE_SIZE (mode) >= 4 | |
4098 | && (regno == STACK_POINTER_REGNUM | |
edf7cee8 | 4099 | || regno >= FIRST_PSEUDO_REGISTER |
76a318e9 RE |
4100 | || x == hard_frame_pointer_rtx |
4101 | || x == arg_pointer_rtx))); | |
4102 | } | |
4103 | ||
4104 | /* Return nonzero if x is a legitimate index register. This is the case | |
4105 | for any base register that can access a QImode object. */ | |
4106 | inline static int | |
5b3e6663 | 4107 | thumb1_index_register_rtx_p (rtx x, int strict_p) |
76a318e9 | 4108 | { |
5b3e6663 | 4109 | return thumb1_base_register_rtx_p (x, QImode, strict_p); |
76a318e9 RE |
4110 | } |
4111 | ||
5b3e6663 | 4112 | /* Return nonzero if x is a legitimate 16-bit Thumb-state address. |
f676971a | 4113 | |
76a318e9 RE |
4114 | The AP may be eliminated to either the SP or the FP, so we use the |
4115 | least common denominator, e.g. SImode, and offsets from 0 to 64. | |
4116 | ||
4117 | ??? Verify whether the above is the right approach. | |
4118 | ||
4119 | ??? Also, the FP may be eliminated to the SP, so perhaps that | |
4120 | needs special handling also. | |
4121 | ||
4122 | ??? Look at how the mips16 port solves this problem. It probably uses | |
4123 | better ways to solve some of these problems. | |
4124 | ||
4125 | Although it is not incorrect, we don't accept QImode and HImode | |
4126 | addresses based on the frame pointer or arg pointer until the | |
4127 | reload pass starts. This is so that eliminating such addresses | |
4128 | into stack based ones won't produce impossible code. */ | |
4129 | int | |
5b3e6663 | 4130 | thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
76a318e9 RE |
4131 | { |
4132 | /* ??? Not clear if this is right. Experiment. */ | |
4133 | if (GET_MODE_SIZE (mode) < 4 | |
4134 | && !(reload_in_progress || reload_completed) | |
4135 | && (reg_mentioned_p (frame_pointer_rtx, x) | |
4136 | || reg_mentioned_p (arg_pointer_rtx, x) | |
4137 | || reg_mentioned_p (virtual_incoming_args_rtx, x) | |
4138 | || reg_mentioned_p (virtual_outgoing_args_rtx, x) | |
4139 | || reg_mentioned_p (virtual_stack_dynamic_rtx, x) | |
4140 | || reg_mentioned_p (virtual_stack_vars_rtx, x))) | |
4141 | return 0; | |
4142 | ||
4143 | /* Accept any base register. SP only in SImode or larger. */ | |
5b3e6663 | 4144 | else if (thumb1_base_register_rtx_p (x, mode, strict_p)) |
76a318e9 RE |
4145 | return 1; |
4146 | ||
18dbd950 | 4147 | /* This is PC relative data before arm_reorg runs. */ |
76a318e9 RE |
4148 | else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) |
4149 | && GET_CODE (x) == SYMBOL_REF | |
020a4035 | 4150 | && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic) |
76a318e9 RE |
4151 | return 1; |
4152 | ||
18dbd950 | 4153 | /* This is PC relative data after arm_reorg runs. */ |
76a318e9 RE |
4154 | else if (GET_MODE_SIZE (mode) >= 4 && reload_completed |
4155 | && (GET_CODE (x) == LABEL_REF | |
4156 | || (GET_CODE (x) == CONST | |
4157 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4158 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
4159 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
4160 | return 1; | |
4161 | ||
4162 | /* Post-inc indexing only supported for SImode and larger. */ | |
4163 | else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 | |
5b3e6663 | 4164 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)) |
76a318e9 RE |
4165 | return 1; |
4166 | ||
4167 | else if (GET_CODE (x) == PLUS) | |
4168 | { | |
4169 | /* REG+REG address can be any two index registers. */ | |
4170 | /* We disallow FRAME+REG addressing since we know that FRAME | |
4171 | will be replaced with STACK, and SP relative addressing only | |
4172 | permits SP+OFFSET. */ | |
4173 | if (GET_MODE_SIZE (mode) <= 4 | |
4174 | && XEXP (x, 0) != frame_pointer_rtx | |
4175 | && XEXP (x, 1) != frame_pointer_rtx | |
5b3e6663 PB |
4176 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
4177 | && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p)) | |
76a318e9 RE |
4178 | return 1; |
4179 | ||
4180 | /* REG+const has 5-7 bit offset for non-SP registers. */ | |
5b3e6663 | 4181 | else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
76a318e9 RE |
4182 | || XEXP (x, 0) == arg_pointer_rtx) |
4183 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4184 | && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
4185 | return 1; | |
4186 | ||
a50aa827 | 4187 | /* REG+const has 10-bit offset for SP, but only SImode and |
76a318e9 RE |
4188 | larger is supported. */ |
4189 | /* ??? Should probably check for DI/DFmode overflow here | |
4190 | just like GO_IF_LEGITIMATE_OFFSET does. */ | |
4191 | else if (GET_CODE (XEXP (x, 0)) == REG | |
4192 | && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM | |
4193 | && GET_MODE_SIZE (mode) >= 4 | |
4194 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4195 | && INTVAL (XEXP (x, 1)) >= 0 | |
4196 | && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 | |
4197 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
4198 | return 1; | |
4199 | ||
4200 | else if (GET_CODE (XEXP (x, 0)) == REG | |
c5289e45 RE |
4201 | && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM |
4202 | || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM | |
4203 | || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER | |
4204 | && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER)) | |
76a318e9 RE |
4205 | && GET_MODE_SIZE (mode) >= 4 |
4206 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4207 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
4208 | return 1; | |
4209 | } | |
4210 | ||
4211 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
f954388e | 4212 | && GET_MODE_SIZE (mode) == 4 |
76a318e9 RE |
4213 | && GET_CODE (x) == SYMBOL_REF |
4214 | && CONSTANT_POOL_ADDRESS_P (x) | |
d3585b76 DJ |
4215 | && ! (flag_pic |
4216 | && symbol_mentioned_p (get_pool_constant (x)) | |
4217 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
76a318e9 RE |
4218 | return 1; |
4219 | ||
4220 | return 0; | |
4221 | } | |
4222 | ||
4223 | /* Return nonzero if VAL can be used as an offset in a Thumb-state address | |
4224 | instruction of mode MODE. */ | |
4225 | int | |
e32bac5b | 4226 | thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) |
76a318e9 RE |
4227 | { |
4228 | switch (GET_MODE_SIZE (mode)) | |
4229 | { | |
4230 | case 1: | |
4231 | return val >= 0 && val < 32; | |
4232 | ||
4233 | case 2: | |
4234 | return val >= 0 && val < 64 && (val & 1) == 0; | |
4235 | ||
4236 | default: | |
4237 | return (val >= 0 | |
4238 | && (val + GET_MODE_SIZE (mode)) <= 128 | |
4239 | && (val & 3) == 0); | |
4240 | } | |
4241 | } | |
4242 | ||
d3585b76 DJ |
4243 | /* Build the SYMBOL_REF for __tls_get_addr. */ |
4244 | ||
4245 | static GTY(()) rtx tls_get_addr_libfunc; | |
4246 | ||
4247 | static rtx | |
4248 | get_tls_get_addr (void) | |
4249 | { | |
4250 | if (!tls_get_addr_libfunc) | |
4251 | tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); | |
4252 | return tls_get_addr_libfunc; | |
4253 | } | |
4254 | ||
4255 | static rtx | |
4256 | arm_load_tp (rtx target) | |
4257 | { | |
4258 | if (!target) | |
4259 | target = gen_reg_rtx (SImode); | |
4260 | ||
4261 | if (TARGET_HARD_TP) | |
4262 | { | |
4263 | /* Can return in any reg. */ | |
4264 | emit_insn (gen_load_tp_hard (target)); | |
4265 | } | |
4266 | else | |
4267 | { | |
4268 | /* Always returned in r0. Immediately copy the result into a pseudo, | |
4269 | otherwise other uses of r0 (e.g. setting up function arguments) may | |
4270 | clobber the value. */ | |
4271 | ||
4272 | rtx tmp; | |
4273 | ||
4274 | emit_insn (gen_load_tp_soft ()); | |
4275 | ||
4276 | tmp = gen_rtx_REG (SImode, 0); | |
4277 | emit_move_insn (target, tmp); | |
4278 | } | |
4279 | return target; | |
4280 | } | |
4281 | ||
4282 | static rtx | |
4283 | load_tls_operand (rtx x, rtx reg) | |
4284 | { | |
4285 | rtx tmp; | |
4286 | ||
4287 | if (reg == NULL_RTX) | |
4288 | reg = gen_reg_rtx (SImode); | |
4289 | ||
4290 | tmp = gen_rtx_CONST (SImode, x); | |
4291 | ||
4292 | emit_move_insn (reg, tmp); | |
4293 | ||
4294 | return reg; | |
4295 | } | |
4296 | ||
4297 | static rtx | |
4298 | arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc) | |
4299 | { | |
f16fe45f | 4300 | rtx insns, label, labelno, sum; |
d3585b76 DJ |
4301 | |
4302 | start_sequence (); | |
4303 | ||
f16fe45f DJ |
4304 | labelno = GEN_INT (pic_labelno++); |
4305 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
4306 | label = gen_rtx_CONST (VOIDmode, label); | |
4307 | ||
d3585b76 | 4308 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 4309 | gen_rtvec (4, x, GEN_INT (reloc), label, |
d3585b76 DJ |
4310 | GEN_INT (TARGET_ARM ? 8 : 4)), |
4311 | UNSPEC_TLS); | |
4312 | reg = load_tls_operand (sum, reg); | |
4313 | ||
4314 | if (TARGET_ARM) | |
f16fe45f | 4315 | emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 PB |
4316 | else if (TARGET_THUMB2) |
4317 | { | |
4318 | rtx tmp; | |
4319 | /* Thumb-2 only allows very limited access to the PC. Calculate | |
4320 | the address in a temporary register. */ | |
4321 | tmp = gen_reg_rtx (SImode); | |
4322 | emit_insn (gen_pic_load_dot_plus_four (tmp, labelno)); | |
4323 | emit_insn (gen_addsi3(reg, reg, tmp)); | |
4324 | } | |
4325 | else /* TARGET_THUMB1 */ | |
f16fe45f | 4326 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
4327 | |
4328 | *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */ | |
4329 | Pmode, 1, reg, Pmode); | |
4330 | ||
4331 | insns = get_insns (); | |
4332 | end_sequence (); | |
4333 | ||
4334 | return insns; | |
4335 | } | |
4336 | ||
4337 | rtx | |
4338 | legitimize_tls_address (rtx x, rtx reg) | |
4339 | { | |
f16fe45f | 4340 | rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend; |
d3585b76 DJ |
4341 | unsigned int model = SYMBOL_REF_TLS_MODEL (x); |
4342 | ||
4343 | switch (model) | |
4344 | { | |
4345 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
4346 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32); | |
4347 | dest = gen_reg_rtx (Pmode); | |
4348 | emit_libcall_block (insns, dest, ret, x); | |
4349 | return dest; | |
4350 | ||
4351 | case TLS_MODEL_LOCAL_DYNAMIC: | |
4352 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32); | |
4353 | ||
4354 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
4355 | share the LDM result with other LD model accesses. */ | |
4356 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), | |
4357 | UNSPEC_TLS); | |
4358 | dest = gen_reg_rtx (Pmode); | |
e66e1c68 | 4359 | emit_libcall_block (insns, dest, ret, eqv); |
d3585b76 DJ |
4360 | |
4361 | /* Load the addend. */ | |
4362 | addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)), | |
4363 | UNSPEC_TLS); | |
4364 | addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); | |
4365 | return gen_rtx_PLUS (Pmode, dest, addend); | |
4366 | ||
4367 | case TLS_MODEL_INITIAL_EXEC: | |
f16fe45f DJ |
4368 | labelno = GEN_INT (pic_labelno++); |
4369 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
4370 | label = gen_rtx_CONST (VOIDmode, label); | |
d3585b76 | 4371 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 4372 | gen_rtvec (4, x, GEN_INT (TLS_IE32), label, |
d3585b76 DJ |
4373 | GEN_INT (TARGET_ARM ? 8 : 4)), |
4374 | UNSPEC_TLS); | |
4375 | reg = load_tls_operand (sum, reg); | |
4376 | ||
4377 | if (TARGET_ARM) | |
f16fe45f | 4378 | emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 PB |
4379 | else if (TARGET_THUMB2) |
4380 | { | |
4381 | rtx tmp; | |
4382 | /* Thumb-2 only allows very limited access to the PC. Calculate | |
4383 | the address in a temporary register. */ | |
4384 | tmp = gen_reg_rtx (SImode); | |
4385 | emit_insn (gen_pic_load_dot_plus_four (tmp, labelno)); | |
4386 | emit_insn (gen_addsi3(reg, reg, tmp)); | |
4387 | emit_move_insn (reg, gen_const_mem (SImode, reg)); | |
4388 | } | |
d3585b76 DJ |
4389 | else |
4390 | { | |
f16fe45f | 4391 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
4392 | emit_move_insn (reg, gen_const_mem (SImode, reg)); |
4393 | } | |
4394 | ||
4395 | tp = arm_load_tp (NULL_RTX); | |
4396 | ||
4397 | return gen_rtx_PLUS (Pmode, tp, reg); | |
4398 | ||
4399 | case TLS_MODEL_LOCAL_EXEC: | |
4400 | tp = arm_load_tp (NULL_RTX); | |
4401 | ||
4402 | reg = gen_rtx_UNSPEC (Pmode, | |
4403 | gen_rtvec (2, x, GEN_INT (TLS_LE32)), | |
4404 | UNSPEC_TLS); | |
4405 | reg = force_reg (SImode, gen_rtx_CONST (SImode, reg)); | |
4406 | ||
4407 | return gen_rtx_PLUS (Pmode, tp, reg); | |
4408 | ||
4409 | default: | |
4410 | abort (); | |
4411 | } | |
4412 | } | |
4413 | ||
ccf4d512 RE |
4414 | /* Try machine-dependent ways of modifying an illegitimate address |
4415 | to be legitimate. If we find one, return the new, valid address. */ | |
ccf4d512 | 4416 | rtx |
e32bac5b | 4417 | arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) |
ccf4d512 | 4418 | { |
d3585b76 DJ |
4419 | if (arm_tls_symbol_p (x)) |
4420 | return legitimize_tls_address (x, NULL_RTX); | |
4421 | ||
ccf4d512 RE |
4422 | if (GET_CODE (x) == PLUS) |
4423 | { | |
4424 | rtx xop0 = XEXP (x, 0); | |
4425 | rtx xop1 = XEXP (x, 1); | |
4426 | ||
4427 | if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) | |
4428 | xop0 = force_reg (SImode, xop0); | |
4429 | ||
4430 | if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) | |
4431 | xop1 = force_reg (SImode, xop1); | |
4432 | ||
4433 | if (ARM_BASE_REGISTER_RTX_P (xop0) | |
4434 | && GET_CODE (xop1) == CONST_INT) | |
4435 | { | |
4436 | HOST_WIDE_INT n, low_n; | |
4437 | rtx base_reg, val; | |
4438 | n = INTVAL (xop1); | |
4439 | ||
9b66ebb1 PB |
4440 | /* VFP addressing modes actually allow greater offsets, but for |
4441 | now we just stick with the lowest common denominator. */ | |
4442 | if (mode == DImode | |
4443 | || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) | |
ccf4d512 RE |
4444 | { |
4445 | low_n = n & 0x0f; | |
4446 | n &= ~0x0f; | |
4447 | if (low_n > 4) | |
4448 | { | |
4449 | n += 16; | |
4450 | low_n -= 16; | |
4451 | } | |
4452 | } | |
4453 | else | |
4454 | { | |
4455 | low_n = ((mode) == TImode ? 0 | |
4456 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); | |
4457 | n -= low_n; | |
4458 | } | |
4459 | ||
4460 | base_reg = gen_reg_rtx (SImode); | |
d66437c5 | 4461 | val = force_operand (plus_constant (xop0, n), NULL_RTX); |
ccf4d512 | 4462 | emit_move_insn (base_reg, val); |
d66437c5 | 4463 | x = plus_constant (base_reg, low_n); |
ccf4d512 RE |
4464 | } |
4465 | else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
4466 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
4467 | } | |
4468 | ||
4469 | /* XXX We don't allow MINUS any more -- see comment in | |
4470 | arm_legitimate_address_p (). */ | |
4471 | else if (GET_CODE (x) == MINUS) | |
4472 | { | |
4473 | rtx xop0 = XEXP (x, 0); | |
4474 | rtx xop1 = XEXP (x, 1); | |
4475 | ||
4476 | if (CONSTANT_P (xop0)) | |
4477 | xop0 = force_reg (SImode, xop0); | |
4478 | ||
4479 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) | |
4480 | xop1 = force_reg (SImode, xop1); | |
4481 | ||
4482 | if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
4483 | x = gen_rtx_MINUS (SImode, xop0, xop1); | |
4484 | } | |
4485 | ||
86805759 NP |
4486 | /* Make sure to take full advantage of the pre-indexed addressing mode |
4487 | with absolute addresses which often allows for the base register to | |
4488 | be factorized for multiple adjacent memory references, and it might | |
4489 | even allows for the mini pool to be avoided entirely. */ | |
4490 | else if (GET_CODE (x) == CONST_INT && optimize > 0) | |
4491 | { | |
4492 | unsigned int bits; | |
4493 | HOST_WIDE_INT mask, base, index; | |
4494 | rtx base_reg; | |
4495 | ||
a50aa827 KH |
4496 | /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only |
4497 | use a 8-bit index. So let's use a 12-bit index for SImode only and | |
86805759 NP |
4498 | hope that arm_gen_constant will enable ldrb to use more bits. */ |
4499 | bits = (mode == SImode) ? 12 : 8; | |
4500 | mask = (1 << bits) - 1; | |
4501 | base = INTVAL (x) & ~mask; | |
4502 | index = INTVAL (x) & mask; | |
b107d743 | 4503 | if (bit_count (base & 0xffffffff) > (32 - bits)/2) |
86805759 NP |
4504 | { |
4505 | /* It'll most probably be more efficient to generate the base | |
4506 | with more bits set and use a negative index instead. */ | |
4507 | base |= mask; | |
4508 | index -= mask; | |
4509 | } | |
4510 | base_reg = force_reg (SImode, GEN_INT (base)); | |
d66437c5 | 4511 | x = plus_constant (base_reg, index); |
86805759 NP |
4512 | } |
4513 | ||
ccf4d512 RE |
4514 | if (flag_pic) |
4515 | { | |
4516 | /* We need to find and carefully transform any SYMBOL and LABEL | |
4517 | references; so go back to the original address expression. */ | |
4518 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
4519 | ||
4520 | if (new_x != orig_x) | |
4521 | x = new_x; | |
4522 | } | |
4523 | ||
4524 | return x; | |
4525 | } | |
4526 | ||
6f5b4f3e RE |
4527 | |
4528 | /* Try machine-dependent ways of modifying an illegitimate Thumb address | |
4529 | to be legitimate. If we find one, return the new, valid address. */ | |
4530 | rtx | |
4531 | thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) | |
4532 | { | |
d3585b76 DJ |
4533 | if (arm_tls_symbol_p (x)) |
4534 | return legitimize_tls_address (x, NULL_RTX); | |
4535 | ||
6f5b4f3e RE |
4536 | if (GET_CODE (x) == PLUS |
4537 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4538 | && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) | |
4539 | || INTVAL (XEXP (x, 1)) < 0)) | |
4540 | { | |
4541 | rtx xop0 = XEXP (x, 0); | |
4542 | rtx xop1 = XEXP (x, 1); | |
4543 | HOST_WIDE_INT offset = INTVAL (xop1); | |
4544 | ||
4545 | /* Try and fold the offset into a biasing of the base register and | |
4546 | then offsetting that. Don't do this when optimizing for space | |
4547 | since it can cause too many CSEs. */ | |
4548 | if (optimize_size && offset >= 0 | |
4549 | && offset < 256 + 31 * GET_MODE_SIZE (mode)) | |
4550 | { | |
4551 | HOST_WIDE_INT delta; | |
4552 | ||
4553 | if (offset >= 256) | |
4554 | delta = offset - (256 - GET_MODE_SIZE (mode)); | |
4555 | else if (offset < 32 * GET_MODE_SIZE (mode) + 8) | |
4556 | delta = 31 * GET_MODE_SIZE (mode); | |
4557 | else | |
4558 | delta = offset & (~31 * GET_MODE_SIZE (mode)); | |
4559 | ||
4560 | xop0 = force_operand (plus_constant (xop0, offset - delta), | |
4561 | NULL_RTX); | |
4562 | x = plus_constant (xop0, delta); | |
4563 | } | |
4564 | else if (offset < 0 && offset > -256) | |
4565 | /* Small negative offsets are best done with a subtract before the | |
4566 | dereference, forcing these into a register normally takes two | |
4567 | instructions. */ | |
4568 | x = force_operand (x, NULL_RTX); | |
4569 | else | |
4570 | { | |
4571 | /* For the remaining cases, force the constant into a register. */ | |
4572 | xop1 = force_reg (SImode, xop1); | |
4573 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
4574 | } | |
4575 | } | |
4576 | else if (GET_CODE (x) == PLUS | |
4577 | && s_register_operand (XEXP (x, 1), SImode) | |
4578 | && !s_register_operand (XEXP (x, 0), SImode)) | |
4579 | { | |
4580 | rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX); | |
4581 | ||
4582 | x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1)); | |
4583 | } | |
4584 | ||
4585 | if (flag_pic) | |
4586 | { | |
4587 | /* We need to find and carefully transform any SYMBOL and LABEL | |
4588 | references; so go back to the original address expression. */ | |
4589 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
4590 | ||
4591 | if (new_x != orig_x) | |
4592 | x = new_x; | |
4593 | } | |
4594 | ||
4595 | return x; | |
4596 | } | |
4597 | ||
a132dad6 | 4598 | rtx |
e0b92319 NC |
4599 | thumb_legitimize_reload_address (rtx *x_p, |
4600 | enum machine_mode mode, | |
4601 | int opnum, int type, | |
4602 | int ind_levels ATTRIBUTE_UNUSED) | |
a132dad6 RE |
4603 | { |
4604 | rtx x = *x_p; | |
e0b92319 | 4605 | |
a132dad6 RE |
4606 | if (GET_CODE (x) == PLUS |
4607 | && GET_MODE_SIZE (mode) < 4 | |
4608 | && REG_P (XEXP (x, 0)) | |
4609 | && XEXP (x, 0) == stack_pointer_rtx | |
4610 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4611 | && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
4612 | { | |
4613 | rtx orig_x = x; | |
4614 | ||
4615 | x = copy_rtx (x); | |
4616 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
4617 | Pmode, VOIDmode, 0, 0, opnum, type); | |
4618 | return x; | |
4619 | } | |
4620 | ||
4621 | /* If both registers are hi-regs, then it's better to reload the | |
4622 | entire expression rather than each register individually. That | |
4623 | only requires one reload register rather than two. */ | |
4624 | if (GET_CODE (x) == PLUS | |
4625 | && REG_P (XEXP (x, 0)) | |
4626 | && REG_P (XEXP (x, 1)) | |
4627 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode) | |
4628 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode)) | |
4629 | { | |
4630 | rtx orig_x = x; | |
4631 | ||
4632 | x = copy_rtx (x); | |
4633 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
4634 | Pmode, VOIDmode, 0, 0, opnum, type); | |
4635 | return x; | |
4636 | } | |
4637 | ||
4638 | return NULL; | |
4639 | } | |
d3585b76 DJ |
4640 | |
4641 | /* Test for various thread-local symbols. */ | |
4642 | ||
4643 | /* Return TRUE if X is a thread-local symbol. */ | |
4644 | ||
4645 | static bool | |
4646 | arm_tls_symbol_p (rtx x) | |
4647 | { | |
4648 | if (! TARGET_HAVE_TLS) | |
4649 | return false; | |
4650 | ||
4651 | if (GET_CODE (x) != SYMBOL_REF) | |
4652 | return false; | |
4653 | ||
4654 | return SYMBOL_REF_TLS_MODEL (x) != 0; | |
4655 | } | |
4656 | ||
4657 | /* Helper for arm_tls_referenced_p. */ | |
4658 | ||
4659 | static int | |
4660 | arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
4661 | { | |
4662 | if (GET_CODE (*x) == SYMBOL_REF) | |
4663 | return SYMBOL_REF_TLS_MODEL (*x) != 0; | |
4664 | ||
4665 | /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are | |
4666 | TLS offsets, not real symbol references. */ | |
4667 | if (GET_CODE (*x) == UNSPEC | |
4668 | && XINT (*x, 1) == UNSPEC_TLS) | |
4669 | return -1; | |
4670 | ||
4671 | return 0; | |
4672 | } | |
4673 | ||
4674 | /* Return TRUE if X contains any TLS symbol references. */ | |
4675 | ||
4676 | bool | |
4677 | arm_tls_referenced_p (rtx x) | |
4678 | { | |
4679 | if (! TARGET_HAVE_TLS) | |
4680 | return false; | |
4681 | ||
4682 | return for_each_rtx (&x, arm_tls_operand_p_1, NULL); | |
4683 | } | |
8426b956 RS |
4684 | |
4685 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ | |
4686 | ||
4687 | bool | |
4688 | arm_cannot_force_const_mem (rtx x) | |
4689 | { | |
4690 | rtx base, offset; | |
4691 | ||
4692 | if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
4693 | { | |
4694 | split_const (x, &base, &offset); | |
4695 | if (GET_CODE (base) == SYMBOL_REF | |
4696 | && !offset_within_block_p (base, INTVAL (offset))) | |
4697 | return true; | |
4698 | } | |
4699 | return arm_tls_referenced_p (x); | |
4700 | } | |
6b990f6b | 4701 | \f |
e2c671ba RE |
4702 | #define REG_OR_SUBREG_REG(X) \ |
4703 | (GET_CODE (X) == REG \ | |
4704 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
4705 | ||
4706 | #define REG_OR_SUBREG_RTX(X) \ | |
4707 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
4708 | ||
d5b7b3ae RE |
4709 | #ifndef COSTS_N_INSNS |
4710 | #define COSTS_N_INSNS(N) ((N) * 4 - 2) | |
4711 | #endif | |
3c50106f | 4712 | static inline int |
5b3e6663 | 4713 | thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) |
e2c671ba RE |
4714 | { |
4715 | enum machine_mode mode = GET_MODE (x); | |
e2c671ba | 4716 | |
9b66ebb1 | 4717 | switch (code) |
d5b7b3ae | 4718 | { |
9b66ebb1 PB |
4719 | case ASHIFT: |
4720 | case ASHIFTRT: | |
4721 | case LSHIFTRT: | |
f676971a | 4722 | case ROTATERT: |
9b66ebb1 PB |
4723 | case PLUS: |
4724 | case MINUS: | |
4725 | case COMPARE: | |
4726 | case NEG: | |
f676971a | 4727 | case NOT: |
9b66ebb1 | 4728 | return COSTS_N_INSNS (1); |
f676971a EC |
4729 | |
4730 | case MULT: | |
4731 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4732 | { | |
4733 | int cycles = 0; | |
9b66ebb1 | 4734 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); |
f676971a EC |
4735 | |
4736 | while (i) | |
4737 | { | |
4738 | i >>= 2; | |
4739 | cycles++; | |
4740 | } | |
4741 | return COSTS_N_INSNS (2) + cycles; | |
9b66ebb1 PB |
4742 | } |
4743 | return COSTS_N_INSNS (1) + 16; | |
f676971a EC |
4744 | |
4745 | case SET: | |
4746 | return (COSTS_N_INSNS (1) | |
4747 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
9b66ebb1 | 4748 | + GET_CODE (SET_DEST (x)) == MEM)); |
f676971a EC |
4749 | |
4750 | case CONST_INT: | |
4751 | if (outer == SET) | |
4752 | { | |
4753 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
4754 | return 0; | |
4755 | if (thumb_shiftable_const (INTVAL (x))) | |
4756 | return COSTS_N_INSNS (2); | |
4757 | return COSTS_N_INSNS (3); | |
4758 | } | |
9b66ebb1 | 4759 | else if ((outer == PLUS || outer == COMPARE) |
f676971a | 4760 | && INTVAL (x) < 256 && INTVAL (x) > -256) |
9b66ebb1 PB |
4761 | return 0; |
4762 | else if (outer == AND | |
4763 | && INTVAL (x) < 256 && INTVAL (x) >= -256) | |
4764 | return COSTS_N_INSNS (1); | |
f676971a EC |
4765 | else if (outer == ASHIFT || outer == ASHIFTRT |
4766 | || outer == LSHIFTRT) | |
4767 | return 0; | |
9b66ebb1 | 4768 | return COSTS_N_INSNS (2); |
f676971a EC |
4769 | |
4770 | case CONST: | |
4771 | case CONST_DOUBLE: | |
4772 | case LABEL_REF: | |
4773 | case SYMBOL_REF: | |
9b66ebb1 | 4774 | return COSTS_N_INSNS (3); |
f676971a | 4775 | |
9b66ebb1 PB |
4776 | case UDIV: |
4777 | case UMOD: | |
4778 | case DIV: | |
4779 | case MOD: | |
4780 | return 100; | |
d5b7b3ae | 4781 | |
9b66ebb1 PB |
4782 | case TRUNCATE: |
4783 | return 99; | |
d5b7b3ae | 4784 | |
9b66ebb1 PB |
4785 | case AND: |
4786 | case XOR: | |
f676971a | 4787 | case IOR: |
ff482c8d | 4788 | /* XXX guess. */ |
9b66ebb1 | 4789 | return 8; |
d5b7b3ae | 4790 | |
9b66ebb1 PB |
4791 | case MEM: |
4792 | /* XXX another guess. */ | |
4793 | /* Memory costs quite a lot for the first word, but subsequent words | |
4794 | load at the equivalent of a single insn each. */ | |
4795 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
4796 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
4797 | ? 4 : 0)); | |
4798 | ||
4799 | case IF_THEN_ELSE: | |
ff482c8d | 4800 | /* XXX a guess. */ |
9b66ebb1 PB |
4801 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) |
4802 | return 14; | |
4803 | return 2; | |
4804 | ||
4805 | case ZERO_EXTEND: | |
4806 | /* XXX still guessing. */ | |
4807 | switch (GET_MODE (XEXP (x, 0))) | |
4808 | { | |
4809 | case QImode: | |
4810 | return (1 + (mode == DImode ? 4 : 0) | |
4811 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 4812 | |
9b66ebb1 PB |
4813 | case HImode: |
4814 | return (4 + (mode == DImode ? 4 : 0) | |
4815 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 4816 | |
9b66ebb1 PB |
4817 | case SImode: |
4818 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 4819 | |
d5b7b3ae RE |
4820 | default: |
4821 | return 99; | |
d5b7b3ae | 4822 | } |
f676971a | 4823 | |
9b66ebb1 PB |
4824 | default: |
4825 | return 99; | |
d5b7b3ae | 4826 | } |
9b66ebb1 PB |
4827 | } |
4828 | ||
4829 | ||
4830 | /* Worker routine for arm_rtx_costs. */ | |
5b3e6663 | 4831 | /* ??? This needs updating for thumb2. */ |
9b66ebb1 PB |
4832 | static inline int |
4833 | arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) | |
4834 | { | |
4835 | enum machine_mode mode = GET_MODE (x); | |
4836 | enum rtx_code subcode; | |
4837 | int extra_cost; | |
4838 | ||
e2c671ba RE |
4839 | switch (code) |
4840 | { | |
4841 | case MEM: | |
4842 | /* Memory costs quite a lot for the first word, but subsequent words | |
4843 | load at the equivalent of a single insn each. */ | |
4844 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
48f6efae NC |
4845 | + (GET_CODE (x) == SYMBOL_REF |
4846 | && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); | |
e2c671ba RE |
4847 | |
4848 | case DIV: | |
4849 | case MOD: | |
b9c53150 RS |
4850 | case UDIV: |
4851 | case UMOD: | |
4852 | return optimize_size ? COSTS_N_INSNS (2) : 100; | |
e2c671ba RE |
4853 | |
4854 | case ROTATE: | |
4855 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
4856 | return 4; | |
4857 | /* Fall through */ | |
4858 | case ROTATERT: | |
4859 | if (mode != SImode) | |
4860 | return 8; | |
4861 | /* Fall through */ | |
4862 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
4863 | if (mode == DImode) | |
4864 | return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) | |
f676971a | 4865 | + ((GET_CODE (XEXP (x, 0)) == REG |
e2c671ba RE |
4866 | || (GET_CODE (XEXP (x, 0)) == SUBREG |
4867 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
4868 | ? 0 : 8)); | |
4869 | return (1 + ((GET_CODE (XEXP (x, 0)) == REG | |
4870 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
4871 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
4872 | ? 0 : 4) | |
4873 | + ((GET_CODE (XEXP (x, 1)) == REG | |
4874 | || (GET_CODE (XEXP (x, 1)) == SUBREG | |
4875 | && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG) | |
4876 | || (GET_CODE (XEXP (x, 1)) == CONST_INT)) | |
4877 | ? 0 : 4)); | |
4878 | ||
4879 | case MINUS: | |
26b53f80 PB |
4880 | if (GET_CODE (XEXP (x, 1)) == MULT && mode == SImode && arm_arch_thumb2) |
4881 | { | |
4882 | extra_cost = rtx_cost (XEXP (x, 1), code); | |
4883 | if (!REG_OR_SUBREG_REG (XEXP (x, 0))) | |
4884 | extra_cost += 4 * ARM_NUM_REGS (mode); | |
4885 | return extra_cost; | |
4886 | } | |
4887 | ||
e2c671ba RE |
4888 | if (mode == DImode) |
4889 | return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8) | |
4890 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
4891 | || (GET_CODE (XEXP (x, 0)) == CONST_INT | |
4892 | && const_ok_for_arm (INTVAL (XEXP (x, 0))))) | |
4893 | ? 0 : 8)); | |
4894 | ||
4895 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
4896 | return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
4897 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
9b66ebb1 | 4898 | && arm_const_double_rtx (XEXP (x, 1)))) |
e2c671ba RE |
4899 | ? 0 : 8) |
4900 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
4901 | || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
9b66ebb1 | 4902 | && arm_const_double_rtx (XEXP (x, 0)))) |
e2c671ba RE |
4903 | ? 0 : 8)); |
4904 | ||
4905 | if (((GET_CODE (XEXP (x, 0)) == CONST_INT | |
4906 | && const_ok_for_arm (INTVAL (XEXP (x, 0))) | |
4907 | && REG_OR_SUBREG_REG (XEXP (x, 1)))) | |
4908 | || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT | |
4909 | || subcode == ASHIFTRT || subcode == LSHIFTRT | |
4910 | || subcode == ROTATE || subcode == ROTATERT | |
4911 | || (subcode == MULT | |
4912 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
4913 | && ((INTVAL (XEXP (XEXP (x, 1), 1)) & | |
4914 | (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) | |
4915 | && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0)) | |
4916 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1)) | |
4917 | || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
4918 | && REG_OR_SUBREG_REG (XEXP (x, 0)))) | |
4919 | return 1; | |
4920 | /* Fall through */ | |
4921 | ||
f676971a | 4922 | case PLUS: |
ff069900 PB |
4923 | if (arm_arch6 && mode == SImode |
4924 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
4925 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
4926 | return 1 + (GET_CODE (XEXP (XEXP (x, 0), 0)) == MEM ? 10 : 0) | |
4927 | + (GET_CODE (XEXP (x, 1)) == MEM ? 10 : 0); | |
4928 | ||
26da58dd PB |
4929 | if (GET_CODE (XEXP (x, 0)) == MULT) |
4930 | { | |
4931 | extra_cost = rtx_cost (XEXP (x, 0), code); | |
4932 | if (!REG_OR_SUBREG_REG (XEXP (x, 1))) | |
4933 | extra_cost += 4 * ARM_NUM_REGS (mode); | |
4934 | return extra_cost; | |
4935 | } | |
4936 | ||
e2c671ba RE |
4937 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
4938 | return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
4939 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
4940 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
9b66ebb1 | 4941 | && arm_const_double_rtx (XEXP (x, 1)))) |
e2c671ba RE |
4942 | ? 0 : 8)); |
4943 | ||
4944 | /* Fall through */ | |
f676971a | 4945 | case AND: case XOR: case IOR: |
e2c671ba RE |
4946 | extra_cost = 0; |
4947 | ||
4948 | /* Normally the frame registers will be spilt into reg+const during | |
4949 | reload, so it is a bad idea to combine them with other instructions, | |
4950 | since then they might not be moved outside of loops. As a compromise | |
4951 | we allow integration with ops that have a constant as their second | |
4952 | operand. */ | |
4953 | if ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
4954 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
4955 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
4956 | || (REG_OR_SUBREG_REG (XEXP (x, 0)) | |
4957 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) | |
4958 | extra_cost = 4; | |
4959 | ||
4960 | if (mode == DImode) | |
4961 | return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
4962 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
4963 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 4964 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
4965 | ? 0 : 8)); |
4966 | ||
4967 | if (REG_OR_SUBREG_REG (XEXP (x, 0))) | |
4968 | return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost) | |
4969 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
4970 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 4971 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
4972 | ? 0 : 4)); |
4973 | ||
4974 | else if (REG_OR_SUBREG_REG (XEXP (x, 1))) | |
4975 | return (1 + extra_cost | |
4976 | + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT | |
4977 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
4978 | || subcode == ROTATE || subcode == ROTATERT | |
4979 | || (subcode == MULT | |
4980 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4981 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
ad076f4e | 4982 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) |
e2c671ba RE |
4983 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0))) |
4984 | && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1))) | |
ad076f4e | 4985 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) |
e2c671ba RE |
4986 | ? 0 : 4)); |
4987 | ||
4988 | return 8; | |
4989 | ||
4990 | case MULT: | |
9b66ebb1 | 4991 | /* This should have been handled by the CPU specific routines. */ |
e6d29d15 | 4992 | gcc_unreachable (); |
e2c671ba | 4993 | |
56636818 | 4994 | case TRUNCATE: |
9b66ebb1 | 4995 | if (arm_arch3m && mode == SImode |
56636818 JL |
4996 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT |
4997 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
4998 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
4999 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
5000 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
5001 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
5002 | return 8; | |
5003 | return 99; | |
5004 | ||
e2c671ba RE |
5005 | case NEG: |
5006 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5007 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6); | |
5008 | /* Fall through */ | |
5009 | case NOT: | |
5010 | if (mode == DImode) | |
5011 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
5012 | ||
5013 | return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
5014 | ||
5015 | case IF_THEN_ELSE: | |
5016 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
5017 | return 14; | |
5018 | return 2; | |
5019 | ||
5020 | case COMPARE: | |
5021 | return 1; | |
5022 | ||
5023 | case ABS: | |
5024 | return 4 + (mode == DImode ? 4 : 0); | |
5025 | ||
5026 | case SIGN_EXTEND: | |
ff069900 PB |
5027 | if (arm_arch_thumb2 && mode == SImode) |
5028 | return 1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0); | |
5029 | ||
e2c671ba RE |
5030 | if (GET_MODE (XEXP (x, 0)) == QImode) |
5031 | return (4 + (mode == DImode ? 4 : 0) | |
5032 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
5033 | /* Fall through */ | |
5034 | case ZERO_EXTEND: | |
ff069900 PB |
5035 | if (arm_arch6 && mode == SImode) |
5036 | return 1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0); | |
5037 | ||
e2c671ba RE |
5038 | switch (GET_MODE (XEXP (x, 0))) |
5039 | { | |
5040 | case QImode: | |
5041 | return (1 + (mode == DImode ? 4 : 0) | |
5042 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
5043 | ||
5044 | case HImode: | |
5045 | return (4 + (mode == DImode ? 4 : 0) | |
5046 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
5047 | ||
5048 | case SImode: | |
5049 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
ad076f4e | 5050 | |
5a9335ef NC |
5051 | case V8QImode: |
5052 | case V4HImode: | |
5053 | case V2SImode: | |
5054 | case V4QImode: | |
5055 | case V2HImode: | |
5056 | return 1; | |
5057 | ||
ad076f4e | 5058 | default: |
e6d29d15 | 5059 | gcc_unreachable (); |
e2c671ba | 5060 | } |
e6d29d15 | 5061 | gcc_unreachable (); |
e2c671ba | 5062 | |
f676971a EC |
5063 | case CONST_INT: |
5064 | if (const_ok_for_arm (INTVAL (x))) | |
5065 | return outer == SET ? 2 : -1; | |
5066 | else if (outer == AND | |
5067 | && const_ok_for_arm (~INTVAL (x))) | |
5068 | return -1; | |
5069 | else if ((outer == COMPARE | |
5070 | || outer == PLUS || outer == MINUS) | |
5071 | && const_ok_for_arm (-INTVAL (x))) | |
5072 | return -1; | |
5073 | else | |
d5b7b3ae | 5074 | return 5; |
f676971a EC |
5075 | |
5076 | case CONST: | |
5077 | case LABEL_REF: | |
5078 | case SYMBOL_REF: | |
d5b7b3ae | 5079 | return 6; |
f676971a EC |
5080 | |
5081 | case CONST_DOUBLE: | |
f1adb0a9 | 5082 | if (arm_const_double_rtx (x) || vfp3_const_double_rtx (x)) |
f676971a EC |
5083 | return outer == SET ? 2 : -1; |
5084 | else if ((outer == COMPARE || outer == PLUS) | |
5085 | && neg_const_double_rtx_ok_for_fpa (x)) | |
5086 | return -1; | |
d5b7b3ae | 5087 | return 7; |
f676971a | 5088 | |
e2c671ba RE |
5089 | default: |
5090 | return 99; | |
5091 | } | |
5092 | } | |
32de079a | 5093 | |
21b5653c RE |
5094 | /* RTX costs when optimizing for size. */ |
5095 | static bool | |
5096 | arm_size_rtx_costs (rtx x, int code, int outer_code, int *total) | |
5097 | { | |
5098 | enum machine_mode mode = GET_MODE (x); | |
5099 | ||
09754904 | 5100 | if (TARGET_THUMB1) |
21b5653c RE |
5101 | { |
5102 | /* XXX TBD. For now, use the standard costs. */ | |
5b3e6663 | 5103 | *total = thumb1_rtx_costs (x, code, outer_code); |
21b5653c RE |
5104 | return true; |
5105 | } | |
5106 | ||
09754904 | 5107 | /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */ |
21b5653c RE |
5108 | switch (code) |
5109 | { | |
5110 | case MEM: | |
f676971a | 5111 | /* A memory access costs 1 insn if the mode is small, or the address is |
21b5653c RE |
5112 | a single register, otherwise it costs one insn per word. */ |
5113 | if (REG_P (XEXP (x, 0))) | |
5114 | *total = COSTS_N_INSNS (1); | |
5115 | else | |
5116 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5117 | return true; | |
5118 | ||
5119 | case DIV: | |
5120 | case MOD: | |
5121 | case UDIV: | |
5122 | case UMOD: | |
5123 | /* Needs a libcall, so it costs about this. */ | |
5124 | *total = COSTS_N_INSNS (2); | |
5125 | return false; | |
5126 | ||
5127 | case ROTATE: | |
5128 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
5129 | { | |
5130 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code); | |
5131 | return true; | |
5132 | } | |
5133 | /* Fall through */ | |
5134 | case ROTATERT: | |
5135 | case ASHIFT: | |
5136 | case LSHIFTRT: | |
5137 | case ASHIFTRT: | |
5138 | if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5139 | { | |
5140 | *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code); | |
5141 | return true; | |
5142 | } | |
5143 | else if (mode == SImode) | |
5144 | { | |
5145 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code); | |
5146 | /* Slightly disparage register shifts, but not by much. */ | |
5147 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
5148 | *total += 1 + rtx_cost (XEXP (x, 1), code); | |
5149 | return true; | |
5150 | } | |
5151 | ||
5152 | /* Needs a libcall. */ | |
5153 | *total = COSTS_N_INSNS (2); | |
5154 | return false; | |
5155 | ||
5156 | case MINUS: | |
5157 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5158 | { | |
5159 | *total = COSTS_N_INSNS (1); | |
5160 | return false; | |
5161 | } | |
5162 | ||
5163 | if (mode == SImode) | |
5164 | { | |
5165 | enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); | |
5166 | enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); | |
5167 | ||
5168 | if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT | |
5169 | || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT | |
5170 | || subcode1 == ROTATE || subcode1 == ROTATERT | |
5171 | || subcode1 == ASHIFT || subcode1 == LSHIFTRT | |
5172 | || subcode1 == ASHIFTRT) | |
5173 | { | |
5174 | /* It's just the cost of the two operands. */ | |
5175 | *total = 0; | |
5176 | return false; | |
5177 | } | |
5178 | ||
5179 | *total = COSTS_N_INSNS (1); | |
5180 | return false; | |
5181 | } | |
5182 | ||
5183 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5184 | return false; | |
5185 | ||
f676971a | 5186 | case PLUS: |
21b5653c RE |
5187 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) |
5188 | { | |
5189 | *total = COSTS_N_INSNS (1); | |
5190 | return false; | |
5191 | } | |
5192 | ||
5193 | /* Fall through */ | |
5194 | case AND: case XOR: case IOR: | |
5195 | if (mode == SImode) | |
5196 | { | |
5197 | enum rtx_code subcode = GET_CODE (XEXP (x, 0)); | |
5198 | ||
5199 | if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT | |
5200 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
5201 | || (code == AND && subcode == NOT)) | |
5202 | { | |
5203 | /* It's just the cost of the two operands. */ | |
5204 | *total = 0; | |
5205 | return false; | |
5206 | } | |
5207 | } | |
5208 | ||
5209 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5210 | return false; | |
5211 | ||
5212 | case MULT: | |
5213 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5214 | return false; | |
5215 | ||
5216 | case NEG: | |
5217 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5218 | *total = COSTS_N_INSNS (1); | |
5219 | /* Fall through */ | |
5220 | case NOT: | |
5221 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5222 | ||
5223 | return false; | |
5224 | ||
5225 | case IF_THEN_ELSE: | |
5226 | *total = 0; | |
5227 | return false; | |
5228 | ||
5229 | case COMPARE: | |
5230 | if (cc_register (XEXP (x, 0), VOIDmode)) | |
5231 | * total = 0; | |
5232 | else | |
5233 | *total = COSTS_N_INSNS (1); | |
5234 | return false; | |
5235 | ||
5236 | case ABS: | |
5237 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5238 | *total = COSTS_N_INSNS (1); | |
5239 | else | |
5240 | *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode)); | |
5241 | return false; | |
5242 | ||
5243 | case SIGN_EXTEND: | |
5244 | *total = 0; | |
5245 | if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4) | |
5246 | { | |
5247 | if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | |
5248 | *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | |
5249 | } | |
5250 | if (mode == DImode) | |
5251 | *total += COSTS_N_INSNS (1); | |
5252 | return false; | |
5253 | ||
5254 | case ZERO_EXTEND: | |
5255 | *total = 0; | |
5256 | if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | |
5257 | { | |
5258 | switch (GET_MODE (XEXP (x, 0))) | |
5259 | { | |
5260 | case QImode: | |
5261 | *total += COSTS_N_INSNS (1); | |
5262 | break; | |
5263 | ||
5264 | case HImode: | |
5265 | *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | |
f676971a | 5266 | |
21b5653c RE |
5267 | case SImode: |
5268 | break; | |
5269 | ||
5270 | default: | |
5271 | *total += COSTS_N_INSNS (2); | |
5272 | } | |
5273 | } | |
5274 | ||
5275 | if (mode == DImode) | |
5276 | *total += COSTS_N_INSNS (1); | |
5277 | ||
5278 | return false; | |
5279 | ||
f676971a EC |
5280 | case CONST_INT: |
5281 | if (const_ok_for_arm (INTVAL (x))) | |
21b5653c RE |
5282 | *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0); |
5283 | else if (const_ok_for_arm (~INTVAL (x))) | |
5284 | *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1); | |
5285 | else if (const_ok_for_arm (-INTVAL (x))) | |
5286 | { | |
5287 | if (outer_code == COMPARE || outer_code == PLUS | |
5288 | || outer_code == MINUS) | |
5289 | *total = 0; | |
5290 | else | |
5291 | *total = COSTS_N_INSNS (1); | |
5292 | } | |
5293 | else | |
5294 | *total = COSTS_N_INSNS (2); | |
5295 | return true; | |
f676971a EC |
5296 | |
5297 | case CONST: | |
5298 | case LABEL_REF: | |
5299 | case SYMBOL_REF: | |
21b5653c RE |
5300 | *total = COSTS_N_INSNS (2); |
5301 | return true; | |
f676971a | 5302 | |
21b5653c RE |
5303 | case CONST_DOUBLE: |
5304 | *total = COSTS_N_INSNS (4); | |
5305 | return true; | |
5306 | ||
5307 | default: | |
5308 | if (mode != VOIDmode) | |
5309 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5310 | else | |
5311 | *total = COSTS_N_INSNS (4); /* How knows? */ | |
5312 | return false; | |
5313 | } | |
5314 | } | |
5315 | ||
5b3e6663 PB |
5316 | /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not |
5317 | supported on any "slowmul" cores, so it can be ignored. */ | |
9b66ebb1 | 5318 | |
3c50106f | 5319 | static bool |
9b66ebb1 | 5320 | arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f | 5321 | { |
9b66ebb1 PB |
5322 | enum machine_mode mode = GET_MODE (x); |
5323 | ||
5324 | if (TARGET_THUMB) | |
5325 | { | |
5b3e6663 | 5326 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
5327 | return true; |
5328 | } | |
f676971a | 5329 | |
9b66ebb1 PB |
5330 | switch (code) |
5331 | { | |
5332 | case MULT: | |
5333 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
5334 | || mode == DImode) | |
5335 | { | |
5336 | *total = 30; | |
5337 | return true; | |
5338 | } | |
5339 | ||
5340 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5341 | { | |
5342 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
5343 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
5344 | int cost, const_ok = const_ok_for_arm (i); | |
5345 | int j, booth_unit_size; | |
5346 | ||
f676971a | 5347 | /* Tune as appropriate. */ |
9b66ebb1 PB |
5348 | cost = const_ok ? 4 : 8; |
5349 | booth_unit_size = 2; | |
5350 | for (j = 0; i && j < 32; j += booth_unit_size) | |
5351 | { | |
5352 | i >>= booth_unit_size; | |
5353 | cost += 2; | |
5354 | } | |
5355 | ||
5356 | *total = cost; | |
5357 | return true; | |
5358 | } | |
5359 | ||
5360 | *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) | |
5361 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); | |
5362 | return true; | |
f676971a | 5363 | |
9b66ebb1 PB |
5364 | default: |
5365 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
5366 | return true; | |
5367 | } | |
3c50106f RH |
5368 | } |
5369 | ||
9b66ebb1 PB |
5370 | |
5371 | /* RTX cost for cores with a fast multiply unit (M variants). */ | |
5372 | ||
5373 | static bool | |
5374 | arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total) | |
5375 | { | |
5376 | enum machine_mode mode = GET_MODE (x); | |
5377 | ||
5b3e6663 | 5378 | if (TARGET_THUMB1) |
9b66ebb1 | 5379 | { |
5b3e6663 | 5380 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
5381 | return true; |
5382 | } | |
f676971a | 5383 | |
5b3e6663 | 5384 | /* ??? should thumb2 use different costs? */ |
9b66ebb1 PB |
5385 | switch (code) |
5386 | { | |
5387 | case MULT: | |
5388 | /* There is no point basing this on the tuning, since it is always the | |
5389 | fast variant if it exists at all. */ | |
5390 | if (mode == DImode | |
5391 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
5392 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
5393 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
5394 | { | |
5395 | *total = 8; | |
5396 | return true; | |
5397 | } | |
f676971a | 5398 | |
9b66ebb1 PB |
5399 | |
5400 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
5401 | || mode == DImode) | |
5402 | { | |
5403 | *total = 30; | |
5404 | return true; | |
5405 | } | |
5406 | ||
5407 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5408 | { | |
5409 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
5410 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
5411 | int cost, const_ok = const_ok_for_arm (i); | |
5412 | int j, booth_unit_size; | |
5413 | ||
f676971a | 5414 | /* Tune as appropriate. */ |
9b66ebb1 PB |
5415 | cost = const_ok ? 4 : 8; |
5416 | booth_unit_size = 8; | |
5417 | for (j = 0; i && j < 32; j += booth_unit_size) | |
5418 | { | |
5419 | i >>= booth_unit_size; | |
5420 | cost += 2; | |
5421 | } | |
5422 | ||
5423 | *total = cost; | |
5424 | return true; | |
5425 | } | |
5426 | ||
5427 | *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) | |
5428 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); | |
5429 | return true; | |
f676971a | 5430 | |
9b66ebb1 PB |
5431 | default: |
5432 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
5433 | return true; | |
5434 | } | |
5435 | } | |
5436 | ||
5437 | ||
5b3e6663 PB |
5438 | /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores, |
5439 | so it can be ignored. */ | |
9b66ebb1 PB |
5440 | |
5441 | static bool | |
5442 | arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total) | |
5443 | { | |
5444 | enum machine_mode mode = GET_MODE (x); | |
5445 | ||
5446 | if (TARGET_THUMB) | |
5447 | { | |
5b3e6663 | 5448 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
5449 | return true; |
5450 | } | |
f676971a | 5451 | |
9b66ebb1 PB |
5452 | switch (code) |
5453 | { | |
5454 | case MULT: | |
5455 | /* There is no point basing this on the tuning, since it is always the | |
5456 | fast variant if it exists at all. */ | |
5457 | if (mode == DImode | |
5458 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
5459 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
5460 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
5461 | { | |
5462 | *total = 8; | |
5463 | return true; | |
5464 | } | |
f676971a | 5465 | |
9b66ebb1 PB |
5466 | |
5467 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
5468 | || mode == DImode) | |
5469 | { | |
5470 | *total = 30; | |
5471 | return true; | |
5472 | } | |
5473 | ||
5474 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5475 | { | |
5476 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
5477 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
5478 | int cost, const_ok = const_ok_for_arm (i); | |
5479 | unsigned HOST_WIDE_INT masked_const; | |
5480 | ||
5481 | /* The cost will be related to two insns. | |
ff482c8d | 5482 | First a load of the constant (MOV or LDR), then a multiply. */ |
9b66ebb1 PB |
5483 | cost = 2; |
5484 | if (! const_ok) | |
5485 | cost += 1; /* LDR is probably more expensive because | |
ff482c8d | 5486 | of longer result latency. */ |
9b66ebb1 PB |
5487 | masked_const = i & 0xffff8000; |
5488 | if (masked_const != 0 && masked_const != 0xffff8000) | |
5489 | { | |
5490 | masked_const = i & 0xf8000000; | |
5491 | if (masked_const == 0 || masked_const == 0xf8000000) | |
5492 | cost += 1; | |
5493 | else | |
5494 | cost += 2; | |
5495 | } | |
5496 | *total = cost; | |
5497 | return true; | |
5498 | } | |
5499 | ||
5500 | *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) | |
5501 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); | |
5502 | return true; | |
f676971a | 5503 | |
06d5588c ILT |
5504 | case COMPARE: |
5505 | /* A COMPARE of a MULT is slow on XScale; the muls instruction | |
5506 | will stall until the multiplication is complete. */ | |
5507 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
5508 | *total = 4 + rtx_cost (XEXP (x, 0), code); | |
5509 | else | |
5510 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
5511 | return true; | |
5512 | ||
9b66ebb1 PB |
5513 | default: |
5514 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
5515 | return true; | |
5516 | } | |
5517 | } | |
5518 | ||
5519 | ||
5520 | /* RTX costs for 9e (and later) cores. */ | |
5521 | ||
5522 | static bool | |
5523 | arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total) | |
5524 | { | |
5525 | enum machine_mode mode = GET_MODE (x); | |
5526 | int nonreg_cost; | |
5527 | int cost; | |
f676971a | 5528 | |
5b3e6663 | 5529 | if (TARGET_THUMB1) |
9b66ebb1 PB |
5530 | { |
5531 | switch (code) | |
5532 | { | |
5533 | case MULT: | |
5534 | *total = COSTS_N_INSNS (3); | |
5535 | return true; | |
f676971a | 5536 | |
9b66ebb1 | 5537 | default: |
5b3e6663 | 5538 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
5539 | return true; |
5540 | } | |
5541 | } | |
f676971a | 5542 | |
9b66ebb1 PB |
5543 | switch (code) |
5544 | { | |
5545 | case MULT: | |
5546 | /* There is no point basing this on the tuning, since it is always the | |
5547 | fast variant if it exists at all. */ | |
5548 | if (mode == DImode | |
5549 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
5550 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
5551 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
5552 | { | |
5553 | *total = 3; | |
5554 | return true; | |
5555 | } | |
f676971a | 5556 | |
9b66ebb1 PB |
5557 | |
5558 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5559 | { | |
5560 | *total = 30; | |
5561 | return true; | |
5562 | } | |
5563 | if (mode == DImode) | |
5564 | { | |
5565 | cost = 7; | |
5566 | nonreg_cost = 8; | |
5567 | } | |
5568 | else | |
5569 | { | |
5570 | cost = 2; | |
5571 | nonreg_cost = 4; | |
5572 | } | |
5573 | ||
5574 | ||
5575 | *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost) | |
5576 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost); | |
5577 | return true; | |
f676971a | 5578 | |
9b66ebb1 PB |
5579 | default: |
5580 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
5581 | return true; | |
5582 | } | |
5583 | } | |
dcefdf67 RH |
5584 | /* All address computations that can be done are free, but rtx cost returns |
5585 | the same for practically all of them. So we weight the different types | |
5586 | of address here in the order (most pref first): | |
d6b4baa4 | 5587 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ |
d2b6eb76 ZW |
5588 | static inline int |
5589 | arm_arm_address_cost (rtx x) | |
5590 | { | |
5591 | enum rtx_code c = GET_CODE (x); | |
5592 | ||
5593 | if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC) | |
5594 | return 0; | |
5595 | if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) | |
5596 | return 10; | |
5597 | ||
5598 | if (c == PLUS || c == MINUS) | |
5599 | { | |
d2b6eb76 ZW |
5600 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
5601 | return 2; | |
5602 | ||
ec8e098d | 5603 | if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) |
d2b6eb76 ZW |
5604 | return 3; |
5605 | ||
5606 | return 4; | |
5607 | } | |
5608 | ||
5609 | return 6; | |
5610 | } | |
5611 | ||
5612 | static inline int | |
5613 | arm_thumb_address_cost (rtx x) | |
5614 | { | |
5615 | enum rtx_code c = GET_CODE (x); | |
5616 | ||
5617 | if (c == REG) | |
5618 | return 1; | |
5619 | if (c == PLUS | |
5620 | && GET_CODE (XEXP (x, 0)) == REG | |
5621 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5622 | return 1; | |
5623 | ||
5624 | return 2; | |
5625 | } | |
5626 | ||
dcefdf67 | 5627 | static int |
e32bac5b | 5628 | arm_address_cost (rtx x) |
dcefdf67 | 5629 | { |
5b3e6663 | 5630 | return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); |
dcefdf67 RH |
5631 | } |
5632 | ||
c237e94a | 5633 | static int |
e32bac5b | 5634 | arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) |
32de079a RE |
5635 | { |
5636 | rtx i_pat, d_pat; | |
5637 | ||
d19fb8e3 NC |
5638 | /* Some true dependencies can have a higher cost depending |
5639 | on precisely how certain input operands are used. */ | |
4b3c2e48 | 5640 | if (arm_tune_xscale |
d19fb8e3 | 5641 | && REG_NOTE_KIND (link) == 0 |
eda833e3 BE |
5642 | && recog_memoized (insn) >= 0 |
5643 | && recog_memoized (dep) >= 0) | |
d19fb8e3 NC |
5644 | { |
5645 | int shift_opnum = get_attr_shift (insn); | |
5646 | enum attr_type attr_type = get_attr_type (dep); | |
5647 | ||
5648 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
5649 | operand for INSN. If we have a shifted input operand and the | |
5650 | instruction we depend on is another ALU instruction, then we may | |
5651 | have to account for an additional stall. */ | |
9b66ebb1 PB |
5652 | if (shift_opnum != 0 |
5653 | && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) | |
d19fb8e3 NC |
5654 | { |
5655 | rtx shifted_operand; | |
5656 | int opno; | |
f676971a | 5657 | |
d19fb8e3 NC |
5658 | /* Get the shifted operand. */ |
5659 | extract_insn (insn); | |
5660 | shifted_operand = recog_data.operand[shift_opnum]; | |
5661 | ||
5662 | /* Iterate over all the operands in DEP. If we write an operand | |
5663 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
5664 | cost of this dependency. */ | |
5665 | extract_insn (dep); | |
5666 | preprocess_constraints (); | |
5667 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
5668 | { | |
5669 | /* We can ignore strict inputs. */ | |
5670 | if (recog_data.operand_type[opno] == OP_IN) | |
5671 | continue; | |
5672 | ||
5673 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
5674 | shifted_operand)) | |
5675 | return 2; | |
5676 | } | |
5677 | } | |
5678 | } | |
5679 | ||
6354dc9b | 5680 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
5681 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
5682 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
5683 | return 0; |
5684 | ||
d5b7b3ae RE |
5685 | /* Call insns don't incur a stall, even if they follow a load. */ |
5686 | if (REG_NOTE_KIND (link) == 0 | |
5687 | && GET_CODE (insn) == CALL_INSN) | |
5688 | return 1; | |
5689 | ||
32de079a RE |
5690 | if ((i_pat = single_set (insn)) != NULL |
5691 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
5692 | && (d_pat = single_set (dep)) != NULL | |
5693 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
5694 | { | |
48f6efae | 5695 | rtx src_mem = XEXP (SET_SRC (i_pat), 0); |
32de079a RE |
5696 | /* This is a load after a store, there is no conflict if the load reads |
5697 | from a cached area. Assume that loads from the stack, and from the | |
f676971a | 5698 | constant pool are cached, and that others will miss. This is a |
6354dc9b | 5699 | hack. */ |
f676971a | 5700 | |
48f6efae NC |
5701 | if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) |
5702 | || reg_mentioned_p (stack_pointer_rtx, src_mem) | |
5703 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | |
5704 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | |
949d79eb | 5705 | return 1; |
32de079a RE |
5706 | } |
5707 | ||
5708 | return cost; | |
5709 | } | |
5710 | ||
9b66ebb1 | 5711 | static int fp_consts_inited = 0; |
ff9940b0 | 5712 | |
9b66ebb1 PB |
5713 | /* Only zero is valid for VFP. Other values are also valid for FPA. */ |
5714 | static const char * const strings_fp[8] = | |
62b10bbc | 5715 | { |
2b835d68 RE |
5716 | "0", "1", "2", "3", |
5717 | "4", "5", "0.5", "10" | |
5718 | }; | |
ff9940b0 | 5719 | |
9b66ebb1 | 5720 | static REAL_VALUE_TYPE values_fp[8]; |
ff9940b0 RE |
5721 | |
5722 | static void | |
9b66ebb1 | 5723 | init_fp_table (void) |
ff9940b0 RE |
5724 | { |
5725 | int i; | |
5726 | REAL_VALUE_TYPE r; | |
5727 | ||
9b66ebb1 PB |
5728 | if (TARGET_VFP) |
5729 | fp_consts_inited = 1; | |
5730 | else | |
5731 | fp_consts_inited = 8; | |
5732 | ||
5733 | for (i = 0; i < fp_consts_inited; i++) | |
ff9940b0 | 5734 | { |
9b66ebb1 PB |
5735 | r = REAL_VALUE_ATOF (strings_fp[i], DFmode); |
5736 | values_fp[i] = r; | |
ff9940b0 | 5737 | } |
ff9940b0 RE |
5738 | } |
5739 | ||
9b66ebb1 | 5740 | /* Return TRUE if rtx X is a valid immediate FP constant. */ |
cce8749e | 5741 | int |
9b66ebb1 | 5742 | arm_const_double_rtx (rtx x) |
cce8749e | 5743 | { |
ff9940b0 RE |
5744 | REAL_VALUE_TYPE r; |
5745 | int i; | |
f676971a | 5746 | |
9b66ebb1 PB |
5747 | if (!fp_consts_inited) |
5748 | init_fp_table (); | |
f676971a | 5749 | |
ff9940b0 RE |
5750 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
5751 | if (REAL_VALUE_MINUS_ZERO (r)) | |
5752 | return 0; | |
f3bb6135 | 5753 | |
9b66ebb1 PB |
5754 | for (i = 0; i < fp_consts_inited; i++) |
5755 | if (REAL_VALUES_EQUAL (r, values_fp[i])) | |
ff9940b0 | 5756 | return 1; |
f3bb6135 | 5757 | |
ff9940b0 | 5758 | return 0; |
f3bb6135 | 5759 | } |
ff9940b0 | 5760 | |
3b684012 | 5761 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
ff9940b0 | 5762 | int |
e32bac5b | 5763 | neg_const_double_rtx_ok_for_fpa (rtx x) |
ff9940b0 RE |
5764 | { |
5765 | REAL_VALUE_TYPE r; | |
5766 | int i; | |
f676971a | 5767 | |
9b66ebb1 PB |
5768 | if (!fp_consts_inited) |
5769 | init_fp_table (); | |
f676971a | 5770 | |
ff9940b0 RE |
5771 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
5772 | r = REAL_VALUE_NEGATE (r); | |
5773 | if (REAL_VALUE_MINUS_ZERO (r)) | |
5774 | return 0; | |
f3bb6135 | 5775 | |
ff9940b0 | 5776 | for (i = 0; i < 8; i++) |
9b66ebb1 | 5777 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
ff9940b0 | 5778 | return 1; |
f3bb6135 | 5779 | |
ff9940b0 | 5780 | return 0; |
f3bb6135 | 5781 | } |
f1adb0a9 JB |
5782 | |
5783 | ||
5784 | /* VFPv3 has a fairly wide range of representable immediates, formed from | |
5785 | "quarter-precision" floating-point values. These can be evaluated using this | |
5786 | formula (with ^ for exponentiation): | |
5787 | ||
5788 | -1^s * n * 2^-r | |
5789 | ||
5790 | Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that | |
5791 | 16 <= n <= 31 and 0 <= r <= 7. | |
5792 | ||
5793 | These values are mapped onto an 8-bit integer ABCDEFGH s.t. | |
5794 | ||
5795 | - A (most-significant) is the sign bit. | |
5796 | - BCD are the exponent (encoded as r XOR 3). | |
5797 | - EFGH are the mantissa (encoded as n - 16). | |
5798 | */ | |
5799 | ||
5800 | /* Return an integer index for a VFPv3 immediate operand X suitable for the | |
5801 | fconst[sd] instruction, or -1 if X isn't suitable. */ | |
5802 | static int | |
5803 | vfp3_const_double_index (rtx x) | |
5804 | { | |
5805 | REAL_VALUE_TYPE r, m; | |
5806 | int sign, exponent; | |
5807 | unsigned HOST_WIDE_INT mantissa, mant_hi; | |
5808 | unsigned HOST_WIDE_INT mask; | |
8e39e9af | 5809 | HOST_WIDE_INT m1, m2; |
f1adb0a9 JB |
5810 | int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; |
5811 | ||
5812 | if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE) | |
5813 | return -1; | |
5814 | ||
5815 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
5816 | ||
5817 | /* We can't represent these things, so detect them first. */ | |
5818 | if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r)) | |
5819 | return -1; | |
5820 | ||
5821 | /* Extract sign, exponent and mantissa. */ | |
5822 | sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0; | |
5823 | r = REAL_VALUE_ABS (r); | |
5824 | exponent = REAL_EXP (&r); | |
5825 | /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the | |
5826 | highest (sign) bit, with a fixed binary point at bit point_pos. | |
5827 | WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1 | |
5828 | bits for the mantissa, this may fail (low bits would be lost). */ | |
5829 | real_ldexp (&m, &r, point_pos - exponent); | |
8e39e9af RE |
5830 | REAL_VALUE_TO_INT (&m1, &m2, m); |
5831 | mantissa = m1; | |
5832 | mant_hi = m2; | |
f1adb0a9 JB |
5833 | |
5834 | /* If there are bits set in the low part of the mantissa, we can't | |
5835 | represent this value. */ | |
5836 | if (mantissa != 0) | |
5837 | return -1; | |
5838 | ||
5839 | /* Now make it so that mantissa contains the most-significant bits, and move | |
5840 | the point_pos to indicate that the least-significant bits have been | |
5841 | discarded. */ | |
5842 | point_pos -= HOST_BITS_PER_WIDE_INT; | |
5843 | mantissa = mant_hi; | |
5844 | ||
5845 | /* We can permit four significant bits of mantissa only, plus a high bit | |
5846 | which is always 1. */ | |
5847 | mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1; | |
5848 | if ((mantissa & mask) != 0) | |
5849 | return -1; | |
5850 | ||
5851 | /* Now we know the mantissa is in range, chop off the unneeded bits. */ | |
5852 | mantissa >>= point_pos - 5; | |
5853 | ||
5854 | /* The mantissa may be zero. Disallow that case. (It's possible to load the | |
5855 | floating-point immediate zero with Neon using an integer-zero load, but | |
5856 | that case is handled elsewhere.) */ | |
5857 | if (mantissa == 0) | |
5858 | return -1; | |
5859 | ||
5860 | gcc_assert (mantissa >= 16 && mantissa <= 31); | |
5861 | ||
5862 | /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where | |
6ed3da00 KH |
5863 | normalized significands are in the range [1, 2). (Our mantissa is shifted |
5864 | left 4 places at this point relative to normalized IEEE754 values). GCC | |
f1adb0a9 JB |
5865 | internally uses [0.5, 1) (see real.c), so the exponent returned from |
5866 | REAL_EXP must be altered. */ | |
5867 | exponent = 5 - exponent; | |
5868 | ||
5869 | if (exponent < 0 || exponent > 7) | |
5870 | return -1; | |
5871 | ||
5872 | /* Sign, mantissa and exponent are now in the correct form to plug into the | |
15dc95cb | 5873 | formula described in the comment above. */ |
f1adb0a9 JB |
5874 | return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16); |
5875 | } | |
5876 | ||
5877 | /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */ | |
5878 | int | |
5879 | vfp3_const_double_rtx (rtx x) | |
5880 | { | |
5881 | if (!TARGET_VFP3) | |
5882 | return 0; | |
5883 | ||
5884 | return vfp3_const_double_index (x) != -1; | |
5885 | } | |
5886 | ||
88f77cba JB |
5887 | /* Recognize immediates which can be used in various Neon instructions. Legal |
5888 | immediates are described by the following table (for VMVN variants, the | |
5889 | bitwise inverse of the constant shown is recognized. In either case, VMOV | |
5890 | is output and the correct instruction to use for a given constant is chosen | |
5891 | by the assembler). The constant shown is replicated across all elements of | |
5892 | the destination vector. | |
5893 | ||
5894 | insn elems variant constant (binary) | |
5895 | ---- ----- ------- ----------------- | |
5896 | vmov i32 0 00000000 00000000 00000000 abcdefgh | |
5897 | vmov i32 1 00000000 00000000 abcdefgh 00000000 | |
5898 | vmov i32 2 00000000 abcdefgh 00000000 00000000 | |
5899 | vmov i32 3 abcdefgh 00000000 00000000 00000000 | |
5900 | vmov i16 4 00000000 abcdefgh | |
5901 | vmov i16 5 abcdefgh 00000000 | |
5902 | vmvn i32 6 00000000 00000000 00000000 abcdefgh | |
5903 | vmvn i32 7 00000000 00000000 abcdefgh 00000000 | |
5904 | vmvn i32 8 00000000 abcdefgh 00000000 00000000 | |
5905 | vmvn i32 9 abcdefgh 00000000 00000000 00000000 | |
5906 | vmvn i16 10 00000000 abcdefgh | |
5907 | vmvn i16 11 abcdefgh 00000000 | |
5908 | vmov i32 12 00000000 00000000 abcdefgh 11111111 | |
5909 | vmvn i32 13 00000000 00000000 abcdefgh 11111111 | |
5910 | vmov i32 14 00000000 abcdefgh 11111111 11111111 | |
5911 | vmvn i32 15 00000000 abcdefgh 11111111 11111111 | |
5912 | vmov i8 16 abcdefgh | |
5913 | vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd | |
5914 | eeeeeeee ffffffff gggggggg hhhhhhhh | |
5915 | vmov f32 18 aBbbbbbc defgh000 00000000 00000000 | |
5916 | ||
5917 | For case 18, B = !b. Representable values are exactly those accepted by | |
5918 | vfp3_const_double_index, but are output as floating-point numbers rather | |
5919 | than indices. | |
5920 | ||
5921 | Variants 0-5 (inclusive) may also be used as immediates for the second | |
5922 | operand of VORR/VBIC instructions. | |
5923 | ||
5924 | The INVERSE argument causes the bitwise inverse of the given operand to be | |
5925 | recognized instead (used for recognizing legal immediates for the VAND/VORN | |
5926 | pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is | |
5927 | *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be | |
5928 | output, rather than the real insns vbic/vorr). | |
5929 | ||
5930 | INVERSE makes no difference to the recognition of float vectors. | |
5931 | ||
5932 | The return value is the variant of immediate as shown in the above table, or | |
5933 | -1 if the given value doesn't match any of the listed patterns. | |
5934 | */ | |
5935 | static int | |
5936 | neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, | |
5937 | rtx *modconst, int *elementwidth) | |
5938 | { | |
5939 | #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \ | |
5940 | matches = 1; \ | |
5941 | for (i = 0; i < idx; i += (STRIDE)) \ | |
5942 | if (!(TEST)) \ | |
5943 | matches = 0; \ | |
5944 | if (matches) \ | |
5945 | { \ | |
5946 | immtype = (CLASS); \ | |
5947 | elsize = (ELSIZE); \ | |
5948 | break; \ | |
5949 | } | |
5950 | ||
5951 | unsigned int i, elsize, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); | |
5952 | unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); | |
5953 | unsigned char bytes[16]; | |
5954 | int immtype = -1, matches; | |
5955 | unsigned int invmask = inverse ? 0xff : 0; | |
5956 | ||
5957 | /* Vectors of float constants. */ | |
5958 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
5959 | { | |
5960 | rtx el0 = CONST_VECTOR_ELT (op, 0); | |
5961 | REAL_VALUE_TYPE r0; | |
5962 | ||
5963 | if (!vfp3_const_double_rtx (el0)) | |
5964 | return -1; | |
5965 | ||
5966 | REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); | |
5967 | ||
5968 | for (i = 1; i < n_elts; i++) | |
5969 | { | |
5970 | rtx elt = CONST_VECTOR_ELT (op, i); | |
5971 | REAL_VALUE_TYPE re; | |
5972 | ||
5973 | REAL_VALUE_FROM_CONST_DOUBLE (re, elt); | |
5974 | ||
5975 | if (!REAL_VALUES_EQUAL (r0, re)) | |
5976 | return -1; | |
5977 | } | |
5978 | ||
5979 | if (modconst) | |
5980 | *modconst = CONST_VECTOR_ELT (op, 0); | |
5981 | ||
5982 | if (elementwidth) | |
5983 | *elementwidth = 0; | |
5984 | ||
5985 | return 18; | |
5986 | } | |
5987 | ||
5988 | /* Splat vector constant out into a byte vector. */ | |
5989 | for (i = 0; i < n_elts; i++) | |
5990 | { | |
5991 | rtx el = CONST_VECTOR_ELT (op, i); | |
5992 | unsigned HOST_WIDE_INT elpart; | |
5993 | unsigned int part, parts; | |
5994 | ||
5995 | if (GET_CODE (el) == CONST_INT) | |
5996 | { | |
5997 | elpart = INTVAL (el); | |
5998 | parts = 1; | |
5999 | } | |
6000 | else if (GET_CODE (el) == CONST_DOUBLE) | |
6001 | { | |
6002 | elpart = CONST_DOUBLE_LOW (el); | |
6003 | parts = 2; | |
6004 | } | |
6005 | else | |
6006 | gcc_unreachable (); | |
6007 | ||
6008 | for (part = 0; part < parts; part++) | |
6009 | { | |
6010 | unsigned int byte; | |
6011 | for (byte = 0; byte < innersize; byte++) | |
6012 | { | |
6013 | bytes[idx++] = (elpart & 0xff) ^ invmask; | |
6014 | elpart >>= BITS_PER_UNIT; | |
6015 | } | |
6016 | if (GET_CODE (el) == CONST_DOUBLE) | |
6017 | elpart = CONST_DOUBLE_HIGH (el); | |
6018 | } | |
6019 | } | |
6020 | ||
6021 | /* Sanity check. */ | |
6022 | gcc_assert (idx == GET_MODE_SIZE (mode)); | |
6023 | ||
6024 | do | |
6025 | { | |
6026 | CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0 | |
6027 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
6028 | ||
6029 | CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
6030 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
6031 | ||
6032 | CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0 | |
6033 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
6034 | ||
6035 | CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0 | |
6036 | && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]); | |
6037 | ||
6038 | CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0); | |
6039 | ||
6040 | CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]); | |
6041 | ||
6042 | CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff | |
6043 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
6044 | ||
6045 | CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
6046 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
6047 | ||
6048 | CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
6049 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
6050 | ||
6051 | CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
6052 | && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]); | |
6053 | ||
6054 | CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff); | |
6055 | ||
6056 | CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]); | |
6057 | ||
6058 | CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
6059 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
6060 | ||
6061 | CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
6062 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
6063 | ||
6064 | CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
6065 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
6066 | ||
6067 | CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 | |
6068 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
6069 | ||
6070 | CHECK (1, 8, 16, bytes[i] == bytes[0]); | |
6071 | ||
6072 | CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff) | |
6073 | && bytes[i] == bytes[(i + 8) % idx]); | |
6074 | } | |
6075 | while (0); | |
6076 | ||
6077 | if (immtype == -1) | |
6078 | return -1; | |
6079 | ||
6080 | if (elementwidth) | |
6081 | *elementwidth = elsize; | |
6082 | ||
6083 | if (modconst) | |
6084 | { | |
6085 | unsigned HOST_WIDE_INT imm = 0; | |
6086 | ||
cea618ac | 6087 | /* Un-invert bytes of recognized vector, if necessary. */ |
88f77cba JB |
6088 | if (invmask != 0) |
6089 | for (i = 0; i < idx; i++) | |
6090 | bytes[i] ^= invmask; | |
6091 | ||
6092 | if (immtype == 17) | |
6093 | { | |
6094 | /* FIXME: Broken on 32-bit H_W_I hosts. */ | |
6095 | gcc_assert (sizeof (HOST_WIDE_INT) == 8); | |
6096 | ||
6097 | for (i = 0; i < 8; i++) | |
6098 | imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) | |
6099 | << (i * BITS_PER_UNIT); | |
6100 | ||
6101 | *modconst = GEN_INT (imm); | |
6102 | } | |
6103 | else | |
6104 | { | |
6105 | unsigned HOST_WIDE_INT imm = 0; | |
6106 | ||
6107 | for (i = 0; i < elsize / BITS_PER_UNIT; i++) | |
6108 | imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT); | |
6109 | ||
6110 | *modconst = GEN_INT (imm); | |
6111 | } | |
6112 | } | |
6113 | ||
6114 | return immtype; | |
6115 | #undef CHECK | |
6116 | } | |
6117 | ||
6118 | /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly, | |
6119 | VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for | |
6120 | float elements), and a modified constant (whatever should be output for a | |
6121 | VMOV) in *MODCONST. */ | |
6122 | ||
6123 | int | |
6124 | neon_immediate_valid_for_move (rtx op, enum machine_mode mode, | |
6125 | rtx *modconst, int *elementwidth) | |
6126 | { | |
6127 | rtx tmpconst; | |
6128 | int tmpwidth; | |
6129 | int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth); | |
6130 | ||
6131 | if (retval == -1) | |
6132 | return 0; | |
6133 | ||
6134 | if (modconst) | |
6135 | *modconst = tmpconst; | |
6136 | ||
6137 | if (elementwidth) | |
6138 | *elementwidth = tmpwidth; | |
6139 | ||
6140 | return 1; | |
6141 | } | |
6142 | ||
6143 | /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If | |
6144 | the immediate is valid, write a constant suitable for using as an operand | |
6145 | to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to | |
6146 | *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */ | |
6147 | ||
6148 | int | |
6149 | neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse, | |
6150 | rtx *modconst, int *elementwidth) | |
6151 | { | |
6152 | rtx tmpconst; | |
6153 | int tmpwidth; | |
6154 | int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth); | |
6155 | ||
6156 | if (retval < 0 || retval > 5) | |
6157 | return 0; | |
6158 | ||
6159 | if (modconst) | |
6160 | *modconst = tmpconst; | |
6161 | ||
6162 | if (elementwidth) | |
6163 | *elementwidth = tmpwidth; | |
6164 | ||
6165 | return 1; | |
6166 | } | |
6167 | ||
6168 | /* Return a string suitable for output of Neon immediate logic operation | |
6169 | MNEM. */ | |
6170 | ||
6171 | char * | |
6172 | neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode, | |
6173 | int inverse, int quad) | |
6174 | { | |
6175 | int width, is_valid; | |
6176 | static char templ[40]; | |
6177 | ||
6178 | is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width); | |
6179 | ||
6180 | gcc_assert (is_valid != 0); | |
6181 | ||
6182 | if (quad) | |
6183 | sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width); | |
6184 | else | |
6185 | sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width); | |
6186 | ||
6187 | return templ; | |
6188 | } | |
6189 | ||
6190 | /* Output a sequence of pairwise operations to implement a reduction. | |
6191 | NOTE: We do "too much work" here, because pairwise operations work on two | |
6192 | registers-worth of operands in one go. Unfortunately we can't exploit those | |
6193 | extra calculations to do the full operation in fewer steps, I don't think. | |
6194 | Although all vector elements of the result but the first are ignored, we | |
6195 | actually calculate the same result in each of the elements. An alternative | |
6196 | such as initially loading a vector with zero to use as each of the second | |
6197 | operands would use up an additional register and take an extra instruction, | |
6198 | for no particular gain. */ | |
6199 | ||
6200 | void | |
6201 | neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode, | |
6202 | rtx (*reduc) (rtx, rtx, rtx)) | |
6203 | { | |
6204 | enum machine_mode inner = GET_MODE_INNER (mode); | |
6205 | unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner); | |
6206 | rtx tmpsum = op1; | |
6207 | ||
6208 | for (i = parts / 2; i >= 1; i /= 2) | |
6209 | { | |
6210 | rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode); | |
6211 | emit_insn (reduc (dest, tmpsum, tmpsum)); | |
6212 | tmpsum = dest; | |
6213 | } | |
6214 | } | |
6215 | ||
cea618ac | 6216 | /* Initialize a vector with non-constant elements. FIXME: We can do better |
88f77cba JB |
6217 | than the current implementation (building a vector on the stack and then |
6218 | loading it) in many cases. See rs6000.c. */ | |
6219 | ||
6220 | void | |
6221 | neon_expand_vector_init (rtx target, rtx vals) | |
6222 | { | |
6223 | enum machine_mode mode = GET_MODE (target); | |
6224 | enum machine_mode inner = GET_MODE_INNER (mode); | |
6225 | unsigned int i, n_elts = GET_MODE_NUNITS (mode); | |
6226 | rtx mem; | |
6227 | ||
6228 | gcc_assert (VECTOR_MODE_P (mode)); | |
6229 | ||
6230 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); | |
6231 | for (i = 0; i < n_elts; i++) | |
6232 | emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)), | |
6233 | XVECEXP (vals, 0, i)); | |
6234 | ||
6235 | emit_move_insn (target, mem); | |
6236 | } | |
6237 | ||
b617fc71 JB |
6238 | /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise |
6239 | ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so | |
6240 | reported source locations are bogus. */ | |
6241 | ||
6242 | static void | |
6243 | bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high, | |
6244 | const char *err) | |
6245 | { | |
6246 | HOST_WIDE_INT lane; | |
6247 | ||
6248 | gcc_assert (GET_CODE (operand) == CONST_INT); | |
6249 | ||
6250 | lane = INTVAL (operand); | |
6251 | ||
6252 | if (lane < low || lane >= high) | |
6253 | error (err); | |
6254 | } | |
6255 | ||
6256 | /* Bounds-check lanes. */ | |
6257 | ||
6258 | void | |
6259 | neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
6260 | { | |
6261 | bounds_check (operand, low, high, "lane out of range"); | |
6262 | } | |
6263 | ||
6264 | /* Bounds-check constants. */ | |
6265 | ||
6266 | void | |
6267 | neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
6268 | { | |
6269 | bounds_check (operand, low, high, "constant out of range"); | |
6270 | } | |
6271 | ||
6272 | HOST_WIDE_INT | |
6273 | neon_element_bits (enum machine_mode mode) | |
6274 | { | |
6275 | if (mode == DImode) | |
6276 | return GET_MODE_BITSIZE (mode); | |
6277 | else | |
6278 | return GET_MODE_BITSIZE (GET_MODE_INNER (mode)); | |
6279 | } | |
6280 | ||
cce8749e CH |
6281 | \f |
6282 | /* Predicates for `match_operand' and `match_operator'. */ | |
6283 | ||
9b6b54e2 | 6284 | /* Return nonzero if OP is a valid Cirrus memory address pattern. */ |
9b6b54e2 | 6285 | int |
e32bac5b | 6286 | cirrus_memory_offset (rtx op) |
9b6b54e2 NC |
6287 | { |
6288 | /* Reject eliminable registers. */ | |
6289 | if (! (reload_in_progress || reload_completed) | |
6290 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
6291 | || reg_mentioned_p (arg_pointer_rtx, op) | |
6292 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
6293 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
6294 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
6295 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
6296 | return 0; | |
6297 | ||
6298 | if (GET_CODE (op) == MEM) | |
6299 | { | |
6300 | rtx ind; | |
6301 | ||
6302 | ind = XEXP (op, 0); | |
6303 | ||
6304 | /* Match: (mem (reg)). */ | |
6305 | if (GET_CODE (ind) == REG) | |
6306 | return 1; | |
6307 | ||
6308 | /* Match: | |
6309 | (mem (plus (reg) | |
6310 | (const))). */ | |
6311 | if (GET_CODE (ind) == PLUS | |
6312 | && GET_CODE (XEXP (ind, 0)) == REG | |
6313 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
6314 | && GET_CODE (XEXP (ind, 1)) == CONST_INT) | |
6315 | return 1; | |
6316 | } | |
6317 | ||
6318 | return 0; | |
6319 | } | |
6320 | ||
f26b8ec9 | 6321 | /* Return TRUE if OP is a valid coprocessor memory address pattern. |
5b3e6663 PB |
6322 | WB is true if full writeback address modes are allowed and is false |
6323 | if limited writeback address modes (POST_INC and PRE_DEC) are | |
6324 | allowed. */ | |
9b66ebb1 PB |
6325 | |
6326 | int | |
fdd695fd | 6327 | arm_coproc_mem_operand (rtx op, bool wb) |
9b66ebb1 | 6328 | { |
fdd695fd | 6329 | rtx ind; |
9b66ebb1 | 6330 | |
fdd695fd | 6331 | /* Reject eliminable registers. */ |
9b66ebb1 PB |
6332 | if (! (reload_in_progress || reload_completed) |
6333 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
6334 | || reg_mentioned_p (arg_pointer_rtx, op) | |
6335 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
6336 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
6337 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
6338 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
6339 | return FALSE; | |
6340 | ||
59b9a953 | 6341 | /* Constants are converted into offsets from labels. */ |
fdd695fd PB |
6342 | if (GET_CODE (op) != MEM) |
6343 | return FALSE; | |
9b66ebb1 | 6344 | |
fdd695fd | 6345 | ind = XEXP (op, 0); |
9b66ebb1 | 6346 | |
fdd695fd PB |
6347 | if (reload_completed |
6348 | && (GET_CODE (ind) == LABEL_REF | |
6349 | || (GET_CODE (ind) == CONST | |
6350 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
6351 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
6352 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
6353 | return TRUE; | |
9b66ebb1 | 6354 | |
fdd695fd PB |
6355 | /* Match: (mem (reg)). */ |
6356 | if (GET_CODE (ind) == REG) | |
6357 | return arm_address_register_rtx_p (ind, 0); | |
6358 | ||
5b3e6663 PB |
6359 | /* Autoincremment addressing modes. POST_INC and PRE_DEC are |
6360 | acceptable in any case (subject to verification by | |
6361 | arm_address_register_rtx_p). We need WB to be true to accept | |
6362 | PRE_INC and POST_DEC. */ | |
6363 | if (GET_CODE (ind) == POST_INC | |
6364 | || GET_CODE (ind) == PRE_DEC | |
6365 | || (wb | |
6366 | && (GET_CODE (ind) == PRE_INC | |
6367 | || GET_CODE (ind) == POST_DEC))) | |
fdd695fd PB |
6368 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); |
6369 | ||
6370 | if (wb | |
6371 | && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY) | |
6372 | && arm_address_register_rtx_p (XEXP (ind, 0), 0) | |
6373 | && GET_CODE (XEXP (ind, 1)) == PLUS | |
6374 | && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) | |
6375 | ind = XEXP (ind, 1); | |
6376 | ||
6377 | /* Match: | |
6378 | (plus (reg) | |
6379 | (const)). */ | |
6380 | if (GET_CODE (ind) == PLUS | |
6381 | && GET_CODE (XEXP (ind, 0)) == REG | |
6382 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
6383 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
6384 | && INTVAL (XEXP (ind, 1)) > -1024 | |
6385 | && INTVAL (XEXP (ind, 1)) < 1024 | |
6386 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
6387 | return TRUE; | |
9b66ebb1 PB |
6388 | |
6389 | return FALSE; | |
6390 | } | |
6391 | ||
88f77cba JB |
6392 | /* Return TRUE if OP is a memory operand which we can load or store a vector |
6393 | to/from. If CORE is true, we're moving from ARM registers not Neon | |
6394 | registers. */ | |
6395 | int | |
6396 | neon_vector_mem_operand (rtx op, bool core) | |
6397 | { | |
6398 | rtx ind; | |
6399 | ||
6400 | /* Reject eliminable registers. */ | |
6401 | if (! (reload_in_progress || reload_completed) | |
6402 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
6403 | || reg_mentioned_p (arg_pointer_rtx, op) | |
6404 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
6405 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
6406 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
6407 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
6408 | return FALSE; | |
6409 | ||
6410 | /* Constants are converted into offsets from labels. */ | |
6411 | if (GET_CODE (op) != MEM) | |
6412 | return FALSE; | |
6413 | ||
6414 | ind = XEXP (op, 0); | |
6415 | ||
6416 | if (reload_completed | |
6417 | && (GET_CODE (ind) == LABEL_REF | |
6418 | || (GET_CODE (ind) == CONST | |
6419 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
6420 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
6421 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
6422 | return TRUE; | |
6423 | ||
6424 | /* Match: (mem (reg)). */ | |
6425 | if (GET_CODE (ind) == REG) | |
6426 | return arm_address_register_rtx_p (ind, 0); | |
6427 | ||
6428 | /* Allow post-increment with Neon registers. */ | |
6429 | if (!core && GET_CODE (ind) == POST_INC) | |
6430 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); | |
6431 | ||
6432 | #if 0 | |
6433 | /* FIXME: We can support this too if we use VLD1/VST1. */ | |
6434 | if (!core | |
6435 | && GET_CODE (ind) == POST_MODIFY | |
6436 | && arm_address_register_rtx_p (XEXP (ind, 0), 0) | |
6437 | && GET_CODE (XEXP (ind, 1)) == PLUS | |
6438 | && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) | |
6439 | ind = XEXP (ind, 1); | |
6440 | #endif | |
6441 | ||
6442 | /* Match: | |
6443 | (plus (reg) | |
6444 | (const)). */ | |
6445 | if (!core | |
6446 | && GET_CODE (ind) == PLUS | |
6447 | && GET_CODE (XEXP (ind, 0)) == REG | |
6448 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
6449 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
6450 | && INTVAL (XEXP (ind, 1)) > -1024 | |
6451 | && INTVAL (XEXP (ind, 1)) < 1016 | |
6452 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
6453 | return TRUE; | |
6454 | ||
6455 | return FALSE; | |
6456 | } | |
6457 | ||
6458 | /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct | |
6459 | type. */ | |
6460 | int | |
6461 | neon_struct_mem_operand (rtx op) | |
6462 | { | |
6463 | rtx ind; | |
6464 | ||
6465 | /* Reject eliminable registers. */ | |
6466 | if (! (reload_in_progress || reload_completed) | |
6467 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
6468 | || reg_mentioned_p (arg_pointer_rtx, op) | |
6469 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
6470 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
6471 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
6472 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
6473 | return FALSE; | |
6474 | ||
6475 | /* Constants are converted into offsets from labels. */ | |
6476 | if (GET_CODE (op) != MEM) | |
6477 | return FALSE; | |
6478 | ||
6479 | ind = XEXP (op, 0); | |
6480 | ||
6481 | if (reload_completed | |
6482 | && (GET_CODE (ind) == LABEL_REF | |
6483 | || (GET_CODE (ind) == CONST | |
6484 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
6485 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
6486 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
6487 | return TRUE; | |
6488 | ||
6489 | /* Match: (mem (reg)). */ | |
6490 | if (GET_CODE (ind) == REG) | |
6491 | return arm_address_register_rtx_p (ind, 0); | |
6492 | ||
6493 | return FALSE; | |
6494 | } | |
6495 | ||
6555b6bd RE |
6496 | /* Return true if X is a register that will be eliminated later on. */ |
6497 | int | |
6498 | arm_eliminable_register (rtx x) | |
6499 | { | |
6500 | return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM | |
6501 | || REGNO (x) == ARG_POINTER_REGNUM | |
6502 | || (REGNO (x) >= FIRST_VIRTUAL_REGISTER | |
6503 | && REGNO (x) <= LAST_VIRTUAL_REGISTER)); | |
6504 | } | |
9b66ebb1 | 6505 | |
9b66ebb1 | 6506 | /* Return GENERAL_REGS if a scratch register required to reload x to/from |
fe2d934b | 6507 | coprocessor registers. Otherwise return NO_REGS. */ |
9b66ebb1 PB |
6508 | |
6509 | enum reg_class | |
fe2d934b | 6510 | coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) |
9b66ebb1 | 6511 | { |
88f77cba JB |
6512 | if (TARGET_NEON |
6513 | && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
6514 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
6515 | && neon_vector_mem_operand (x, FALSE)) | |
6516 | return NO_REGS; | |
6517 | ||
fe2d934b | 6518 | if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) |
9b66ebb1 PB |
6519 | return NO_REGS; |
6520 | ||
6521 | return GENERAL_REGS; | |
6522 | } | |
6523 | ||
866af8a9 JB |
6524 | /* Values which must be returned in the most-significant end of the return |
6525 | register. */ | |
6526 | ||
6527 | static bool | |
586de218 | 6528 | arm_return_in_msb (const_tree valtype) |
866af8a9 JB |
6529 | { |
6530 | return (TARGET_AAPCS_BASED | |
6531 | && BYTES_BIG_ENDIAN | |
6532 | && (AGGREGATE_TYPE_P (valtype) | |
6533 | || TREE_CODE (valtype) == COMPLEX_TYPE)); | |
6534 | } | |
9b66ebb1 | 6535 | |
f0375c66 NC |
6536 | /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. |
6537 | Use by the Cirrus Maverick code which has to workaround | |
6538 | a hardware bug triggered by such instructions. */ | |
f0375c66 | 6539 | static bool |
e32bac5b | 6540 | arm_memory_load_p (rtx insn) |
9b6b54e2 NC |
6541 | { |
6542 | rtx body, lhs, rhs;; | |
6543 | ||
f0375c66 NC |
6544 | if (insn == NULL_RTX || GET_CODE (insn) != INSN) |
6545 | return false; | |
9b6b54e2 NC |
6546 | |
6547 | body = PATTERN (insn); | |
6548 | ||
6549 | if (GET_CODE (body) != SET) | |
f0375c66 | 6550 | return false; |
9b6b54e2 NC |
6551 | |
6552 | lhs = XEXP (body, 0); | |
6553 | rhs = XEXP (body, 1); | |
6554 | ||
f0375c66 NC |
6555 | lhs = REG_OR_SUBREG_RTX (lhs); |
6556 | ||
6557 | /* If the destination is not a general purpose | |
6558 | register we do not have to worry. */ | |
6559 | if (GET_CODE (lhs) != REG | |
6560 | || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) | |
6561 | return false; | |
6562 | ||
6563 | /* As well as loads from memory we also have to react | |
6564 | to loads of invalid constants which will be turned | |
6565 | into loads from the minipool. */ | |
6566 | return (GET_CODE (rhs) == MEM | |
6567 | || GET_CODE (rhs) == SYMBOL_REF | |
6568 | || note_invalid_constants (insn, -1, false)); | |
9b6b54e2 NC |
6569 | } |
6570 | ||
f0375c66 | 6571 | /* Return TRUE if INSN is a Cirrus instruction. */ |
f0375c66 | 6572 | static bool |
e32bac5b | 6573 | arm_cirrus_insn_p (rtx insn) |
9b6b54e2 NC |
6574 | { |
6575 | enum attr_cirrus attr; | |
6576 | ||
e6d29d15 | 6577 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
6578 | if (!insn |
6579 | || GET_CODE (insn) != INSN | |
6580 | || GET_CODE (PATTERN (insn)) == USE | |
6581 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
6582 | return 0; | |
6583 | ||
6584 | attr = get_attr_cirrus (insn); | |
6585 | ||
f0375c66 | 6586 | return attr != CIRRUS_NOT; |
9b6b54e2 NC |
6587 | } |
6588 | ||
6589 | /* Cirrus reorg for invalid instruction combinations. */ | |
9b6b54e2 | 6590 | static void |
e32bac5b | 6591 | cirrus_reorg (rtx first) |
9b6b54e2 NC |
6592 | { |
6593 | enum attr_cirrus attr; | |
6594 | rtx body = PATTERN (first); | |
6595 | rtx t; | |
6596 | int nops; | |
6597 | ||
6598 | /* Any branch must be followed by 2 non Cirrus instructions. */ | |
6599 | if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) | |
6600 | { | |
6601 | nops = 0; | |
6602 | t = next_nonnote_insn (first); | |
6603 | ||
f0375c66 | 6604 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
6605 | ++ nops; |
6606 | ||
f0375c66 | 6607 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
6608 | ++ nops; |
6609 | ||
6610 | while (nops --) | |
6611 | emit_insn_after (gen_nop (), first); | |
6612 | ||
6613 | return; | |
6614 | } | |
6615 | ||
6616 | /* (float (blah)) is in parallel with a clobber. */ | |
6617 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
6618 | body = XVECEXP (body, 0, 0); | |
6619 | ||
6620 | if (GET_CODE (body) == SET) | |
6621 | { | |
6622 | rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); | |
6623 | ||
6624 | /* cfldrd, cfldr64, cfstrd, cfstr64 must | |
6625 | be followed by a non Cirrus insn. */ | |
6626 | if (get_attr_cirrus (first) == CIRRUS_DOUBLE) | |
6627 | { | |
f0375c66 | 6628 | if (arm_cirrus_insn_p (next_nonnote_insn (first))) |
9b6b54e2 NC |
6629 | emit_insn_after (gen_nop (), first); |
6630 | ||
6631 | return; | |
6632 | } | |
f0375c66 | 6633 | else if (arm_memory_load_p (first)) |
9b6b54e2 NC |
6634 | { |
6635 | unsigned int arm_regno; | |
6636 | ||
6637 | /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, | |
6638 | ldr/cfmv64hr combination where the Rd field is the same | |
6639 | in both instructions must be split with a non Cirrus | |
6640 | insn. Example: | |
6641 | ||
6642 | ldr r0, blah | |
6643 | nop | |
6644 | cfmvsr mvf0, r0. */ | |
6645 | ||
6646 | /* Get Arm register number for ldr insn. */ | |
6647 | if (GET_CODE (lhs) == REG) | |
6648 | arm_regno = REGNO (lhs); | |
9b6b54e2 | 6649 | else |
e6d29d15 NS |
6650 | { |
6651 | gcc_assert (GET_CODE (rhs) == REG); | |
6652 | arm_regno = REGNO (rhs); | |
6653 | } | |
9b6b54e2 NC |
6654 | |
6655 | /* Next insn. */ | |
6656 | first = next_nonnote_insn (first); | |
6657 | ||
f0375c66 | 6658 | if (! arm_cirrus_insn_p (first)) |
9b6b54e2 NC |
6659 | return; |
6660 | ||
6661 | body = PATTERN (first); | |
6662 | ||
6663 | /* (float (blah)) is in parallel with a clobber. */ | |
6664 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) | |
6665 | body = XVECEXP (body, 0, 0); | |
6666 | ||
6667 | if (GET_CODE (body) == FLOAT) | |
6668 | body = XEXP (body, 0); | |
6669 | ||
6670 | if (get_attr_cirrus (first) == CIRRUS_MOVE | |
6671 | && GET_CODE (XEXP (body, 1)) == REG | |
6672 | && arm_regno == REGNO (XEXP (body, 1))) | |
6673 | emit_insn_after (gen_nop (), first); | |
6674 | ||
6675 | return; | |
6676 | } | |
6677 | } | |
6678 | ||
e6d29d15 | 6679 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
6680 | if (!first |
6681 | || GET_CODE (first) != INSN | |
6682 | || GET_CODE (PATTERN (first)) == USE | |
6683 | || GET_CODE (PATTERN (first)) == CLOBBER) | |
6684 | return; | |
6685 | ||
6686 | attr = get_attr_cirrus (first); | |
6687 | ||
6688 | /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) | |
6689 | must be followed by a non-coprocessor instruction. */ | |
6690 | if (attr == CIRRUS_COMPARE) | |
6691 | { | |
6692 | nops = 0; | |
6693 | ||
6694 | t = next_nonnote_insn (first); | |
6695 | ||
f0375c66 | 6696 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
6697 | ++ nops; |
6698 | ||
f0375c66 | 6699 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
6700 | ++ nops; |
6701 | ||
6702 | while (nops --) | |
6703 | emit_insn_after (gen_nop (), first); | |
6704 | ||
6705 | return; | |
6706 | } | |
6707 | } | |
6708 | ||
2b835d68 RE |
6709 | /* Return TRUE if X references a SYMBOL_REF. */ |
6710 | int | |
e32bac5b | 6711 | symbol_mentioned_p (rtx x) |
2b835d68 | 6712 | { |
1d6e90ac NC |
6713 | const char * fmt; |
6714 | int i; | |
2b835d68 RE |
6715 | |
6716 | if (GET_CODE (x) == SYMBOL_REF) | |
6717 | return 1; | |
6718 | ||
d3585b76 DJ |
6719 | /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they |
6720 | are constant offsets, not symbols. */ | |
6721 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
6722 | return 0; | |
6723 | ||
2b835d68 | 6724 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
f676971a | 6725 | |
2b835d68 RE |
6726 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
6727 | { | |
6728 | if (fmt[i] == 'E') | |
6729 | { | |
1d6e90ac | 6730 | int j; |
2b835d68 RE |
6731 | |
6732 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6733 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
6734 | return 1; | |
6735 | } | |
6736 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
6737 | return 1; | |
6738 | } | |
6739 | ||
6740 | return 0; | |
6741 | } | |
6742 | ||
6743 | /* Return TRUE if X references a LABEL_REF. */ | |
6744 | int | |
e32bac5b | 6745 | label_mentioned_p (rtx x) |
2b835d68 | 6746 | { |
1d6e90ac NC |
6747 | const char * fmt; |
6748 | int i; | |
2b835d68 RE |
6749 | |
6750 | if (GET_CODE (x) == LABEL_REF) | |
6751 | return 1; | |
6752 | ||
d3585b76 DJ |
6753 | /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing |
6754 | instruction, but they are constant offsets, not symbols. */ | |
6755 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
6756 | return 0; | |
6757 | ||
2b835d68 RE |
6758 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
6759 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6760 | { | |
6761 | if (fmt[i] == 'E') | |
6762 | { | |
1d6e90ac | 6763 | int j; |
2b835d68 RE |
6764 | |
6765 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
6766 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
6767 | return 1; | |
6768 | } | |
6769 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
6770 | return 1; | |
6771 | } | |
6772 | ||
6773 | return 0; | |
6774 | } | |
6775 | ||
d3585b76 DJ |
6776 | int |
6777 | tls_mentioned_p (rtx x) | |
6778 | { | |
6779 | switch (GET_CODE (x)) | |
6780 | { | |
6781 | case CONST: | |
6782 | return tls_mentioned_p (XEXP (x, 0)); | |
6783 | ||
6784 | case UNSPEC: | |
6785 | if (XINT (x, 1) == UNSPEC_TLS) | |
6786 | return 1; | |
6787 | ||
6788 | default: | |
6789 | return 0; | |
6790 | } | |
6791 | } | |
6792 | ||
6793 | /* Must not copy a SET whose source operand is PC-relative. */ | |
6794 | ||
6795 | static bool | |
6796 | arm_cannot_copy_insn_p (rtx insn) | |
6797 | { | |
6798 | rtx pat = PATTERN (insn); | |
6799 | ||
10ae7c7b | 6800 | if (GET_CODE (pat) == SET) |
d3585b76 | 6801 | { |
10ae7c7b | 6802 | rtx rhs = SET_SRC (pat); |
d3585b76 DJ |
6803 | |
6804 | if (GET_CODE (rhs) == UNSPEC | |
6805 | && XINT (rhs, 1) == UNSPEC_PIC_BASE) | |
6806 | return TRUE; | |
6807 | ||
6808 | if (GET_CODE (rhs) == MEM | |
6809 | && GET_CODE (XEXP (rhs, 0)) == UNSPEC | |
6810 | && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE) | |
6811 | return TRUE; | |
6812 | } | |
6813 | ||
6814 | return FALSE; | |
6815 | } | |
6816 | ||
ff9940b0 | 6817 | enum rtx_code |
e32bac5b | 6818 | minmax_code (rtx x) |
ff9940b0 RE |
6819 | { |
6820 | enum rtx_code code = GET_CODE (x); | |
6821 | ||
e6d29d15 NS |
6822 | switch (code) |
6823 | { | |
6824 | case SMAX: | |
6825 | return GE; | |
6826 | case SMIN: | |
6827 | return LE; | |
6828 | case UMIN: | |
6829 | return LEU; | |
6830 | case UMAX: | |
6831 | return GEU; | |
6832 | default: | |
6833 | gcc_unreachable (); | |
6834 | } | |
ff9940b0 RE |
6835 | } |
6836 | ||
6354dc9b | 6837 | /* Return 1 if memory locations are adjacent. */ |
f3bb6135 | 6838 | int |
e32bac5b | 6839 | adjacent_mem_locations (rtx a, rtx b) |
ff9940b0 | 6840 | { |
15b5c4c1 RE |
6841 | /* We don't guarantee to preserve the order of these memory refs. */ |
6842 | if (volatile_refs_p (a) || volatile_refs_p (b)) | |
6843 | return 0; | |
6844 | ||
ff9940b0 RE |
6845 | if ((GET_CODE (XEXP (a, 0)) == REG |
6846 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
6847 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
6848 | && (GET_CODE (XEXP (b, 0)) == REG | |
6849 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
6850 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
6851 | { | |
6555b6bd RE |
6852 | HOST_WIDE_INT val0 = 0, val1 = 0; |
6853 | rtx reg0, reg1; | |
6854 | int val_diff; | |
f676971a | 6855 | |
ff9940b0 RE |
6856 | if (GET_CODE (XEXP (a, 0)) == PLUS) |
6857 | { | |
6555b6bd | 6858 | reg0 = XEXP (XEXP (a, 0), 0); |
ff9940b0 RE |
6859 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); |
6860 | } | |
6861 | else | |
6555b6bd | 6862 | reg0 = XEXP (a, 0); |
1d6e90ac | 6863 | |
ff9940b0 RE |
6864 | if (GET_CODE (XEXP (b, 0)) == PLUS) |
6865 | { | |
6555b6bd | 6866 | reg1 = XEXP (XEXP (b, 0), 0); |
ff9940b0 RE |
6867 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); |
6868 | } | |
6869 | else | |
6555b6bd | 6870 | reg1 = XEXP (b, 0); |
1d6e90ac | 6871 | |
e32bac5b RE |
6872 | /* Don't accept any offset that will require multiple |
6873 | instructions to handle, since this would cause the | |
6874 | arith_adjacentmem pattern to output an overlong sequence. */ | |
c75a3ddc PB |
6875 | if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1)) |
6876 | return 0; | |
f676971a | 6877 | |
6555b6bd RE |
6878 | /* Don't allow an eliminable register: register elimination can make |
6879 | the offset too large. */ | |
6880 | if (arm_eliminable_register (reg0)) | |
6881 | return 0; | |
6882 | ||
6883 | val_diff = val1 - val0; | |
15b5c4c1 RE |
6884 | |
6885 | if (arm_ld_sched) | |
6886 | { | |
6887 | /* If the target has load delay slots, then there's no benefit | |
6888 | to using an ldm instruction unless the offset is zero and | |
6889 | we are optimizing for size. */ | |
6890 | return (optimize_size && (REGNO (reg0) == REGNO (reg1)) | |
6891 | && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4) | |
6892 | && (val_diff == 4 || val_diff == -4)); | |
6893 | } | |
6894 | ||
6555b6bd RE |
6895 | return ((REGNO (reg0) == REGNO (reg1)) |
6896 | && (val_diff == 4 || val_diff == -4)); | |
ff9940b0 | 6897 | } |
6555b6bd | 6898 | |
ff9940b0 RE |
6899 | return 0; |
6900 | } | |
6901 | ||
84ed5e79 | 6902 | int |
e32bac5b RE |
6903 | load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
6904 | HOST_WIDE_INT *load_offset) | |
84ed5e79 RE |
6905 | { |
6906 | int unsorted_regs[4]; | |
6907 | HOST_WIDE_INT unsorted_offsets[4]; | |
6908 | int order[4]; | |
ad076f4e | 6909 | int base_reg = -1; |
84ed5e79 RE |
6910 | int i; |
6911 | ||
1d6e90ac NC |
6912 | /* Can only handle 2, 3, or 4 insns at present, |
6913 | though could be easily extended if required. */ | |
e6d29d15 | 6914 | gcc_assert (nops >= 2 && nops <= 4); |
84ed5e79 RE |
6915 | |
6916 | /* Loop over the operands and check that the memory references are | |
112cdef5 | 6917 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
6918 | the same time, extract the target register, and the memory |
6919 | offsets. */ | |
6920 | for (i = 0; i < nops; i++) | |
6921 | { | |
6922 | rtx reg; | |
6923 | rtx offset; | |
6924 | ||
56636818 JL |
6925 | /* Convert a subreg of a mem into the mem itself. */ |
6926 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 6927 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 6928 | |
e6d29d15 | 6929 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
6930 | |
6931 | /* Don't reorder volatile memory references; it doesn't seem worth | |
6932 | looking for the case where the order is ok anyway. */ | |
6933 | if (MEM_VOLATILE_P (operands[nops + i])) | |
6934 | return 0; | |
6935 | ||
6936 | offset = const0_rtx; | |
6937 | ||
6938 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
6939 | || (GET_CODE (reg) == SUBREG | |
6940 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
6941 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
6942 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
6943 | == REG) | |
6944 | || (GET_CODE (reg) == SUBREG | |
6945 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
6946 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
6947 | == CONST_INT))) | |
6948 | { | |
6949 | if (i == 0) | |
6950 | { | |
d5b7b3ae | 6951 | base_reg = REGNO (reg); |
84ed5e79 RE |
6952 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
6953 | ? REGNO (operands[i]) | |
6954 | : REGNO (SUBREG_REG (operands[i]))); | |
6955 | order[0] = 0; | |
6956 | } | |
f676971a | 6957 | else |
84ed5e79 | 6958 | { |
6354dc9b | 6959 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
6960 | /* Not addressed from the same base register. */ |
6961 | return 0; | |
6962 | ||
6963 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
6964 | ? REGNO (operands[i]) | |
6965 | : REGNO (SUBREG_REG (operands[i]))); | |
6966 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
6967 | order[0] = i; | |
6968 | } | |
6969 | ||
6970 | /* If it isn't an integer register, or if it overwrites the | |
6971 | base register but isn't the last insn in the list, then | |
6972 | we can't do this. */ | |
6973 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | |
6974 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) | |
6975 | return 0; | |
6976 | ||
6977 | unsorted_offsets[i] = INTVAL (offset); | |
6978 | } | |
6979 | else | |
6980 | /* Not a suitable memory address. */ | |
6981 | return 0; | |
6982 | } | |
6983 | ||
6984 | /* All the useful information has now been extracted from the | |
6985 | operands into unsorted_regs and unsorted_offsets; additionally, | |
6986 | order[0] has been set to the lowest numbered register in the | |
6987 | list. Sort the registers into order, and check that the memory | |
6988 | offsets are ascending and adjacent. */ | |
6989 | ||
6990 | for (i = 1; i < nops; i++) | |
6991 | { | |
6992 | int j; | |
6993 | ||
6994 | order[i] = order[i - 1]; | |
6995 | for (j = 0; j < nops; j++) | |
6996 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
6997 | && (order[i] == order[i - 1] | |
6998 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
6999 | order[i] = j; | |
7000 | ||
7001 | /* Have we found a suitable register? if not, one must be used more | |
7002 | than once. */ | |
7003 | if (order[i] == order[i - 1]) | |
7004 | return 0; | |
7005 | ||
7006 | /* Is the memory address adjacent and ascending? */ | |
7007 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
7008 | return 0; | |
7009 | } | |
7010 | ||
7011 | if (base) | |
7012 | { | |
7013 | *base = base_reg; | |
7014 | ||
7015 | for (i = 0; i < nops; i++) | |
7016 | regs[i] = unsorted_regs[order[i]]; | |
7017 | ||
7018 | *load_offset = unsorted_offsets[order[0]]; | |
7019 | } | |
7020 | ||
7021 | if (unsorted_offsets[order[0]] == 0) | |
7022 | return 1; /* ldmia */ | |
7023 | ||
5b3e6663 | 7024 | if (TARGET_ARM && unsorted_offsets[order[0]] == 4) |
84ed5e79 RE |
7025 | return 2; /* ldmib */ |
7026 | ||
5b3e6663 | 7027 | if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) |
84ed5e79 RE |
7028 | return 3; /* ldmda */ |
7029 | ||
7030 | if (unsorted_offsets[order[nops - 1]] == -4) | |
7031 | return 4; /* ldmdb */ | |
7032 | ||
949d79eb RE |
7033 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm |
7034 | if the offset isn't small enough. The reason 2 ldrs are faster | |
7035 | is because these ARMs are able to do more than one cache access | |
7036 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
7037 | whilst the ARM8 has a double bandwidth cache. This means that | |
7038 | these cores can do both an instruction fetch and a data fetch in | |
7039 | a single cycle, so the trick of calculating the address into a | |
7040 | scratch register (one of the result regs) and then doing a load | |
7041 | multiple actually becomes slower (and no smaller in code size). | |
7042 | That is the transformation | |
f676971a | 7043 | |
6cc8c0b3 NC |
7044 | ldr rd1, [rbase + offset] |
7045 | ldr rd2, [rbase + offset + 4] | |
f676971a | 7046 | |
6cc8c0b3 | 7047 | to |
f676971a | 7048 | |
6cc8c0b3 NC |
7049 | add rd1, rbase, offset |
7050 | ldmia rd1, {rd1, rd2} | |
f676971a | 7051 | |
949d79eb RE |
7052 | produces worse code -- '3 cycles + any stalls on rd2' instead of |
7053 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
7054 | access per cycle, the first sequence could never complete in less | |
7055 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
7056 | would make better use of sequential accesses if not hitting the | |
7057 | cache. | |
7058 | ||
7059 | We cheat here and test 'arm_ld_sched' which we currently know to | |
7060 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
7061 | changes, then the test below needs to be reworked. */ | |
f5a1b0d2 | 7062 | if (nops == 2 && arm_ld_sched) |
b36ba79f RE |
7063 | return 0; |
7064 | ||
84ed5e79 RE |
7065 | /* Can't do it without setting up the offset, only do this if it takes |
7066 | no more than one insn. */ | |
f676971a | 7067 | return (const_ok_for_arm (unsorted_offsets[order[0]]) |
84ed5e79 RE |
7068 | || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; |
7069 | } | |
7070 | ||
cd2b33d0 | 7071 | const char * |
e32bac5b | 7072 | emit_ldm_seq (rtx *operands, int nops) |
84ed5e79 RE |
7073 | { |
7074 | int regs[4]; | |
7075 | int base_reg; | |
7076 | HOST_WIDE_INT offset; | |
7077 | char buf[100]; | |
7078 | int i; | |
7079 | ||
7080 | switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
7081 | { | |
7082 | case 1: | |
5b3e6663 | 7083 | strcpy (buf, "ldm%(ia%)\t"); |
84ed5e79 RE |
7084 | break; |
7085 | ||
7086 | case 2: | |
5b3e6663 | 7087 | strcpy (buf, "ldm%(ib%)\t"); |
84ed5e79 RE |
7088 | break; |
7089 | ||
7090 | case 3: | |
5b3e6663 | 7091 | strcpy (buf, "ldm%(da%)\t"); |
84ed5e79 RE |
7092 | break; |
7093 | ||
7094 | case 4: | |
5b3e6663 | 7095 | strcpy (buf, "ldm%(db%)\t"); |
84ed5e79 RE |
7096 | break; |
7097 | ||
7098 | case 5: | |
7099 | if (offset >= 0) | |
7100 | sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
7101 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
7102 | (long) offset); | |
7103 | else | |
7104 | sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
7105 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
7106 | (long) -offset); | |
7107 | output_asm_insn (buf, operands); | |
7108 | base_reg = regs[0]; | |
5b3e6663 | 7109 | strcpy (buf, "ldm%(ia%)\t"); |
84ed5e79 RE |
7110 | break; |
7111 | ||
7112 | default: | |
e6d29d15 | 7113 | gcc_unreachable (); |
84ed5e79 RE |
7114 | } |
7115 | ||
f676971a | 7116 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, |
84ed5e79 RE |
7117 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); |
7118 | ||
7119 | for (i = 1; i < nops; i++) | |
7120 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
7121 | reg_names[regs[i]]); | |
7122 | ||
7123 | strcat (buf, "}\t%@ phole ldm"); | |
7124 | ||
7125 | output_asm_insn (buf, operands); | |
7126 | return ""; | |
7127 | } | |
7128 | ||
7129 | int | |
e32bac5b RE |
7130 | store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
7131 | HOST_WIDE_INT * load_offset) | |
84ed5e79 RE |
7132 | { |
7133 | int unsorted_regs[4]; | |
7134 | HOST_WIDE_INT unsorted_offsets[4]; | |
7135 | int order[4]; | |
ad076f4e | 7136 | int base_reg = -1; |
84ed5e79 RE |
7137 | int i; |
7138 | ||
7139 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | |
7140 | extended if required. */ | |
e6d29d15 | 7141 | gcc_assert (nops >= 2 && nops <= 4); |
84ed5e79 RE |
7142 | |
7143 | /* Loop over the operands and check that the memory references are | |
112cdef5 | 7144 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
7145 | the same time, extract the target register, and the memory |
7146 | offsets. */ | |
7147 | for (i = 0; i < nops; i++) | |
7148 | { | |
7149 | rtx reg; | |
7150 | rtx offset; | |
7151 | ||
56636818 JL |
7152 | /* Convert a subreg of a mem into the mem itself. */ |
7153 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 7154 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 7155 | |
e6d29d15 | 7156 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
7157 | |
7158 | /* Don't reorder volatile memory references; it doesn't seem worth | |
7159 | looking for the case where the order is ok anyway. */ | |
7160 | if (MEM_VOLATILE_P (operands[nops + i])) | |
7161 | return 0; | |
7162 | ||
7163 | offset = const0_rtx; | |
7164 | ||
7165 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
7166 | || (GET_CODE (reg) == SUBREG | |
7167 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7168 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
7169 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
7170 | == REG) | |
7171 | || (GET_CODE (reg) == SUBREG | |
7172 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7173 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
7174 | == CONST_INT))) | |
7175 | { | |
7176 | if (i == 0) | |
7177 | { | |
62b10bbc | 7178 | base_reg = REGNO (reg); |
84ed5e79 RE |
7179 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
7180 | ? REGNO (operands[i]) | |
7181 | : REGNO (SUBREG_REG (operands[i]))); | |
7182 | order[0] = 0; | |
7183 | } | |
f676971a | 7184 | else |
84ed5e79 | 7185 | { |
6354dc9b | 7186 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
7187 | /* Not addressed from the same base register. */ |
7188 | return 0; | |
7189 | ||
7190 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
7191 | ? REGNO (operands[i]) | |
7192 | : REGNO (SUBREG_REG (operands[i]))); | |
7193 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
7194 | order[0] = i; | |
7195 | } | |
7196 | ||
7197 | /* If it isn't an integer register, then we can't do this. */ | |
7198 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | |
7199 | return 0; | |
7200 | ||
7201 | unsorted_offsets[i] = INTVAL (offset); | |
7202 | } | |
7203 | else | |
7204 | /* Not a suitable memory address. */ | |
7205 | return 0; | |
7206 | } | |
7207 | ||
7208 | /* All the useful information has now been extracted from the | |
7209 | operands into unsorted_regs and unsorted_offsets; additionally, | |
7210 | order[0] has been set to the lowest numbered register in the | |
7211 | list. Sort the registers into order, and check that the memory | |
7212 | offsets are ascending and adjacent. */ | |
7213 | ||
7214 | for (i = 1; i < nops; i++) | |
7215 | { | |
7216 | int j; | |
7217 | ||
7218 | order[i] = order[i - 1]; | |
7219 | for (j = 0; j < nops; j++) | |
7220 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
7221 | && (order[i] == order[i - 1] | |
7222 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
7223 | order[i] = j; | |
7224 | ||
7225 | /* Have we found a suitable register? if not, one must be used more | |
7226 | than once. */ | |
7227 | if (order[i] == order[i - 1]) | |
7228 | return 0; | |
7229 | ||
7230 | /* Is the memory address adjacent and ascending? */ | |
7231 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
7232 | return 0; | |
7233 | } | |
7234 | ||
7235 | if (base) | |
7236 | { | |
7237 | *base = base_reg; | |
7238 | ||
7239 | for (i = 0; i < nops; i++) | |
7240 | regs[i] = unsorted_regs[order[i]]; | |
7241 | ||
7242 | *load_offset = unsorted_offsets[order[0]]; | |
7243 | } | |
7244 | ||
7245 | if (unsorted_offsets[order[0]] == 0) | |
7246 | return 1; /* stmia */ | |
7247 | ||
7248 | if (unsorted_offsets[order[0]] == 4) | |
7249 | return 2; /* stmib */ | |
7250 | ||
7251 | if (unsorted_offsets[order[nops - 1]] == 0) | |
7252 | return 3; /* stmda */ | |
7253 | ||
7254 | if (unsorted_offsets[order[nops - 1]] == -4) | |
7255 | return 4; /* stmdb */ | |
7256 | ||
7257 | return 0; | |
7258 | } | |
7259 | ||
cd2b33d0 | 7260 | const char * |
e32bac5b | 7261 | emit_stm_seq (rtx *operands, int nops) |
84ed5e79 RE |
7262 | { |
7263 | int regs[4]; | |
7264 | int base_reg; | |
7265 | HOST_WIDE_INT offset; | |
7266 | char buf[100]; | |
7267 | int i; | |
7268 | ||
7269 | switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
7270 | { | |
7271 | case 1: | |
5b3e6663 | 7272 | strcpy (buf, "stm%(ia%)\t"); |
84ed5e79 RE |
7273 | break; |
7274 | ||
7275 | case 2: | |
5b3e6663 | 7276 | strcpy (buf, "stm%(ib%)\t"); |
84ed5e79 RE |
7277 | break; |
7278 | ||
7279 | case 3: | |
5b3e6663 | 7280 | strcpy (buf, "stm%(da%)\t"); |
84ed5e79 RE |
7281 | break; |
7282 | ||
7283 | case 4: | |
5b3e6663 | 7284 | strcpy (buf, "stm%(db%)\t"); |
84ed5e79 RE |
7285 | break; |
7286 | ||
7287 | default: | |
e6d29d15 | 7288 | gcc_unreachable (); |
84ed5e79 RE |
7289 | } |
7290 | ||
f676971a | 7291 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, |
84ed5e79 RE |
7292 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); |
7293 | ||
7294 | for (i = 1; i < nops; i++) | |
7295 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
7296 | reg_names[regs[i]]); | |
7297 | ||
7298 | strcat (buf, "}\t%@ phole stm"); | |
7299 | ||
7300 | output_asm_insn (buf, operands); | |
7301 | return ""; | |
7302 | } | |
ff9940b0 | 7303 | \f |
6354dc9b | 7304 | /* Routines for use in generating RTL. */ |
1d6e90ac | 7305 | |
f3bb6135 | 7306 | rtx |
e32bac5b | 7307 | arm_gen_load_multiple (int base_regno, int count, rtx from, int up, |
50ed9cea | 7308 | int write_back, rtx basemem, HOST_WIDE_INT *offsetp) |
ff9940b0 | 7309 | { |
50ed9cea | 7310 | HOST_WIDE_INT offset = *offsetp; |
ff9940b0 RE |
7311 | int i = 0, j; |
7312 | rtx result; | |
7313 | int sign = up ? 1 : -1; | |
50ed9cea | 7314 | rtx mem, addr; |
ff9940b0 | 7315 | |
d19fb8e3 | 7316 | /* XScale has load-store double instructions, but they have stricter |
1e5f1716 | 7317 | alignment requirements than load-store multiple, so we cannot |
d19fb8e3 NC |
7318 | use them. |
7319 | ||
7320 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
7321 | the pipeline until completion. | |
7322 | ||
7323 | NREGS CYCLES | |
7324 | 1 3 | |
7325 | 2 4 | |
7326 | 3 5 | |
7327 | 4 6 | |
7328 | ||
7329 | An ldr instruction takes 1-3 cycles, but does not block the | |
7330 | pipeline. | |
7331 | ||
7332 | NREGS CYCLES | |
7333 | 1 1-3 | |
7334 | 2 2-6 | |
7335 | 3 3-9 | |
7336 | 4 4-12 | |
7337 | ||
7338 | Best case ldr will always win. However, the more ldr instructions | |
7339 | we issue, the less likely we are to be able to schedule them well. | |
7340 | Using ldr instructions also increases code size. | |
7341 | ||
7342 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
7343 | for counts of 3 or 4 regs. */ | |
4b3c2e48 | 7344 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
7345 | { |
7346 | rtx seq; | |
f676971a | 7347 | |
d19fb8e3 | 7348 | start_sequence (); |
f676971a | 7349 | |
d19fb8e3 NC |
7350 | for (i = 0; i < count; i++) |
7351 | { | |
50ed9cea RH |
7352 | addr = plus_constant (from, i * 4 * sign); |
7353 | mem = adjust_automodify_address (basemem, SImode, addr, offset); | |
d19fb8e3 | 7354 | emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); |
50ed9cea | 7355 | offset += 4 * sign; |
d19fb8e3 NC |
7356 | } |
7357 | ||
7358 | if (write_back) | |
50ed9cea RH |
7359 | { |
7360 | emit_move_insn (from, plus_constant (from, count * 4 * sign)); | |
7361 | *offsetp = offset; | |
7362 | } | |
d19fb8e3 | 7363 | |
2f937369 | 7364 | seq = get_insns (); |
d19fb8e3 | 7365 | end_sequence (); |
f676971a | 7366 | |
d19fb8e3 NC |
7367 | return seq; |
7368 | } | |
7369 | ||
43cffd11 | 7370 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 7371 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 7372 | if (write_back) |
f3bb6135 | 7373 | { |
ff9940b0 | 7374 | XVECEXP (result, 0, 0) |
d66437c5 | 7375 | = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign)); |
ff9940b0 RE |
7376 | i = 1; |
7377 | count++; | |
f3bb6135 RE |
7378 | } |
7379 | ||
ff9940b0 | 7380 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 7381 | { |
50ed9cea RH |
7382 | addr = plus_constant (from, j * 4 * sign); |
7383 | mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
43cffd11 RE |
7384 | XVECEXP (result, 0, i) |
7385 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | |
50ed9cea | 7386 | offset += 4 * sign; |
f3bb6135 RE |
7387 | } |
7388 | ||
50ed9cea RH |
7389 | if (write_back) |
7390 | *offsetp = offset; | |
7391 | ||
ff9940b0 RE |
7392 | return result; |
7393 | } | |
7394 | ||
f3bb6135 | 7395 | rtx |
e32bac5b | 7396 | arm_gen_store_multiple (int base_regno, int count, rtx to, int up, |
50ed9cea | 7397 | int write_back, rtx basemem, HOST_WIDE_INT *offsetp) |
ff9940b0 | 7398 | { |
50ed9cea | 7399 | HOST_WIDE_INT offset = *offsetp; |
ff9940b0 RE |
7400 | int i = 0, j; |
7401 | rtx result; | |
7402 | int sign = up ? 1 : -1; | |
50ed9cea | 7403 | rtx mem, addr; |
ff9940b0 | 7404 | |
d19fb8e3 NC |
7405 | /* See arm_gen_load_multiple for discussion of |
7406 | the pros/cons of ldm/stm usage for XScale. */ | |
4b3c2e48 | 7407 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
7408 | { |
7409 | rtx seq; | |
f676971a | 7410 | |
d19fb8e3 | 7411 | start_sequence (); |
f676971a | 7412 | |
d19fb8e3 NC |
7413 | for (i = 0; i < count; i++) |
7414 | { | |
50ed9cea RH |
7415 | addr = plus_constant (to, i * 4 * sign); |
7416 | mem = adjust_automodify_address (basemem, SImode, addr, offset); | |
d19fb8e3 | 7417 | emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); |
50ed9cea | 7418 | offset += 4 * sign; |
d19fb8e3 NC |
7419 | } |
7420 | ||
7421 | if (write_back) | |
50ed9cea RH |
7422 | { |
7423 | emit_move_insn (to, plus_constant (to, count * 4 * sign)); | |
7424 | *offsetp = offset; | |
7425 | } | |
d19fb8e3 | 7426 | |
2f937369 | 7427 | seq = get_insns (); |
d19fb8e3 | 7428 | end_sequence (); |
f676971a | 7429 | |
d19fb8e3 NC |
7430 | return seq; |
7431 | } | |
7432 | ||
43cffd11 | 7433 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 7434 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 7435 | if (write_back) |
f3bb6135 | 7436 | { |
ff9940b0 | 7437 | XVECEXP (result, 0, 0) |
d66437c5 | 7438 | = gen_rtx_SET (VOIDmode, to, |
43cffd11 | 7439 | plus_constant (to, count * 4 * sign)); |
ff9940b0 RE |
7440 | i = 1; |
7441 | count++; | |
f3bb6135 RE |
7442 | } |
7443 | ||
ff9940b0 | 7444 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 7445 | { |
50ed9cea RH |
7446 | addr = plus_constant (to, j * 4 * sign); |
7447 | mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
43cffd11 RE |
7448 | XVECEXP (result, 0, i) |
7449 | = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | |
50ed9cea | 7450 | offset += 4 * sign; |
f3bb6135 RE |
7451 | } |
7452 | ||
50ed9cea RH |
7453 | if (write_back) |
7454 | *offsetp = offset; | |
7455 | ||
ff9940b0 RE |
7456 | return result; |
7457 | } | |
7458 | ||
880e2516 | 7459 | int |
70128ad9 | 7460 | arm_gen_movmemqi (rtx *operands) |
880e2516 RE |
7461 | { |
7462 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
50ed9cea | 7463 | HOST_WIDE_INT srcoffset, dstoffset; |
ad076f4e | 7464 | int i; |
50ed9cea | 7465 | rtx src, dst, srcbase, dstbase; |
880e2516 | 7466 | rtx part_bytes_reg = NULL; |
56636818 | 7467 | rtx mem; |
880e2516 RE |
7468 | |
7469 | if (GET_CODE (operands[2]) != CONST_INT | |
7470 | || GET_CODE (operands[3]) != CONST_INT | |
7471 | || INTVAL (operands[2]) > 64 | |
7472 | || INTVAL (operands[3]) & 3) | |
7473 | return 0; | |
7474 | ||
50ed9cea RH |
7475 | dstbase = operands[0]; |
7476 | srcbase = operands[1]; | |
56636818 | 7477 | |
50ed9cea RH |
7478 | dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0)); |
7479 | src = copy_to_mode_reg (SImode, XEXP (srcbase, 0)); | |
880e2516 | 7480 | |
e9d7b180 | 7481 | in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
7482 | out_words_to_go = INTVAL (operands[2]) / 4; |
7483 | last_bytes = INTVAL (operands[2]) & 3; | |
50ed9cea | 7484 | dstoffset = srcoffset = 0; |
880e2516 RE |
7485 | |
7486 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 7487 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
7488 | |
7489 | for (i = 0; in_words_to_go >= 2; i+=4) | |
7490 | { | |
bd9c7e23 | 7491 | if (in_words_to_go > 4) |
56636818 | 7492 | emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, |
50ed9cea | 7493 | srcbase, &srcoffset)); |
bd9c7e23 | 7494 | else |
f676971a | 7495 | emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, |
50ed9cea | 7496 | FALSE, srcbase, &srcoffset)); |
bd9c7e23 | 7497 | |
880e2516 RE |
7498 | if (out_words_to_go) |
7499 | { | |
bd9c7e23 | 7500 | if (out_words_to_go > 4) |
56636818 | 7501 | emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, |
50ed9cea | 7502 | dstbase, &dstoffset)); |
bd9c7e23 RE |
7503 | else if (out_words_to_go != 1) |
7504 | emit_insn (arm_gen_store_multiple (0, out_words_to_go, | |
f676971a | 7505 | dst, TRUE, |
bd9c7e23 | 7506 | (last_bytes == 0 |
56636818 | 7507 | ? FALSE : TRUE), |
50ed9cea | 7508 | dstbase, &dstoffset)); |
880e2516 RE |
7509 | else |
7510 | { | |
50ed9cea | 7511 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); |
43cffd11 | 7512 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 | 7513 | if (last_bytes != 0) |
50ed9cea RH |
7514 | { |
7515 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
7516 | dstoffset += 4; | |
7517 | } | |
880e2516 RE |
7518 | } |
7519 | } | |
7520 | ||
7521 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
7522 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
7523 | } | |
7524 | ||
7525 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
7526 | if (out_words_to_go) | |
62b10bbc NC |
7527 | { |
7528 | rtx sreg; | |
f676971a | 7529 | |
50ed9cea RH |
7530 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
7531 | sreg = copy_to_reg (mem); | |
7532 | ||
7533 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); | |
62b10bbc | 7534 | emit_move_insn (mem, sreg); |
62b10bbc | 7535 | in_words_to_go--; |
f676971a | 7536 | |
e6d29d15 | 7537 | gcc_assert (!in_words_to_go); /* Sanity check */ |
62b10bbc | 7538 | } |
880e2516 RE |
7539 | |
7540 | if (in_words_to_go) | |
7541 | { | |
e6d29d15 | 7542 | gcc_assert (in_words_to_go > 0); |
880e2516 | 7543 | |
50ed9cea | 7544 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
56636818 | 7545 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
7546 | } |
7547 | ||
e6d29d15 | 7548 | gcc_assert (!last_bytes || part_bytes_reg); |
d5b7b3ae | 7549 | |
880e2516 RE |
7550 | if (BYTES_BIG_ENDIAN && last_bytes) |
7551 | { | |
7552 | rtx tmp = gen_reg_rtx (SImode); | |
7553 | ||
6354dc9b | 7554 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
7555 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
7556 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 | 7557 | part_bytes_reg = tmp; |
f676971a | 7558 | |
880e2516 RE |
7559 | while (last_bytes) |
7560 | { | |
50ed9cea RH |
7561 | mem = adjust_automodify_address (dstbase, QImode, |
7562 | plus_constant (dst, last_bytes - 1), | |
7563 | dstoffset + last_bytes - 1); | |
5d5603e2 BS |
7564 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
7565 | ||
880e2516 RE |
7566 | if (--last_bytes) |
7567 | { | |
7568 | tmp = gen_reg_rtx (SImode); | |
7569 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
7570 | part_bytes_reg = tmp; | |
7571 | } | |
7572 | } | |
f676971a | 7573 | |
880e2516 RE |
7574 | } |
7575 | else | |
7576 | { | |
d5b7b3ae | 7577 | if (last_bytes > 1) |
880e2516 | 7578 | { |
50ed9cea | 7579 | mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset); |
5d5603e2 | 7580 | emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); |
d5b7b3ae RE |
7581 | last_bytes -= 2; |
7582 | if (last_bytes) | |
880e2516 RE |
7583 | { |
7584 | rtx tmp = gen_reg_rtx (SImode); | |
a556fd39 | 7585 | emit_insn (gen_addsi3 (dst, dst, const2_rtx)); |
d5b7b3ae | 7586 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); |
880e2516 | 7587 | part_bytes_reg = tmp; |
50ed9cea | 7588 | dstoffset += 2; |
880e2516 RE |
7589 | } |
7590 | } | |
f676971a | 7591 | |
d5b7b3ae RE |
7592 | if (last_bytes) |
7593 | { | |
50ed9cea | 7594 | mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset); |
5d5603e2 | 7595 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
d5b7b3ae | 7596 | } |
880e2516 RE |
7597 | } |
7598 | ||
7599 | return 1; | |
7600 | } | |
7601 | ||
03f1640c RE |
7602 | /* Select a dominance comparison mode if possible for a test of the general |
7603 | form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. | |
f676971a | 7604 | COND_OR == DOM_CC_X_AND_Y => (X && Y) |
03f1640c | 7605 | COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) |
f676971a | 7606 | COND_OR == DOM_CC_X_OR_Y => (X || Y) |
03f1640c | 7607 | In all cases OP will be either EQ or NE, but we don't need to know which |
f676971a | 7608 | here. If we are unable to support a dominance comparison we return |
03f1640c RE |
7609 | CC mode. This will then fail to match for the RTL expressions that |
7610 | generate this call. */ | |
03f1640c | 7611 | enum machine_mode |
e32bac5b | 7612 | arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) |
84ed5e79 RE |
7613 | { |
7614 | enum rtx_code cond1, cond2; | |
7615 | int swapped = 0; | |
7616 | ||
7617 | /* Currently we will probably get the wrong result if the individual | |
7618 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 7619 | reverse a comparison if necessary. */ |
84ed5e79 RE |
7620 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
7621 | != CCmode) | |
7622 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
7623 | != CCmode)) | |
7624 | return CCmode; | |
7625 | ||
1646cf41 RE |
7626 | /* The if_then_else variant of this tests the second condition if the |
7627 | first passes, but is true if the first fails. Reverse the first | |
7628 | condition to get a true "inclusive-or" expression. */ | |
03f1640c | 7629 | if (cond_or == DOM_CC_NX_OR_Y) |
84ed5e79 RE |
7630 | cond1 = reverse_condition (cond1); |
7631 | ||
7632 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
7633 | then we can't do this. */ | |
f676971a | 7634 | if (cond1 != cond2 |
5895f793 RE |
7635 | && !comparison_dominates_p (cond1, cond2) |
7636 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
7637 | return CCmode; |
7638 | ||
7639 | if (swapped) | |
7640 | { | |
7641 | enum rtx_code temp = cond1; | |
7642 | cond1 = cond2; | |
7643 | cond2 = temp; | |
7644 | } | |
7645 | ||
7646 | switch (cond1) | |
7647 | { | |
7648 | case EQ: | |
e6d29d15 | 7649 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
7650 | return CC_DEQmode; |
7651 | ||
7652 | switch (cond2) | |
7653 | { | |
e6d29d15 | 7654 | case EQ: return CC_DEQmode; |
84ed5e79 RE |
7655 | case LE: return CC_DLEmode; |
7656 | case LEU: return CC_DLEUmode; | |
7657 | case GE: return CC_DGEmode; | |
7658 | case GEU: return CC_DGEUmode; | |
e6d29d15 | 7659 | default: gcc_unreachable (); |
84ed5e79 RE |
7660 | } |
7661 | ||
84ed5e79 | 7662 | case LT: |
e6d29d15 | 7663 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 7664 | return CC_DLTmode; |
e0b92319 | 7665 | |
e6d29d15 NS |
7666 | switch (cond2) |
7667 | { | |
7668 | case LT: | |
7669 | return CC_DLTmode; | |
7670 | case LE: | |
7671 | return CC_DLEmode; | |
7672 | case NE: | |
7673 | return CC_DNEmode; | |
7674 | default: | |
7675 | gcc_unreachable (); | |
7676 | } | |
84ed5e79 RE |
7677 | |
7678 | case GT: | |
e6d29d15 | 7679 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 7680 | return CC_DGTmode; |
e6d29d15 NS |
7681 | |
7682 | switch (cond2) | |
7683 | { | |
7684 | case GT: | |
7685 | return CC_DGTmode; | |
7686 | case GE: | |
7687 | return CC_DGEmode; | |
7688 | case NE: | |
7689 | return CC_DNEmode; | |
7690 | default: | |
7691 | gcc_unreachable (); | |
7692 | } | |
f676971a | 7693 | |
84ed5e79 | 7694 | case LTU: |
e6d29d15 | 7695 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 7696 | return CC_DLTUmode; |
e6d29d15 NS |
7697 | |
7698 | switch (cond2) | |
7699 | { | |
7700 | case LTU: | |
7701 | return CC_DLTUmode; | |
7702 | case LEU: | |
7703 | return CC_DLEUmode; | |
7704 | case NE: | |
7705 | return CC_DNEmode; | |
7706 | default: | |
7707 | gcc_unreachable (); | |
7708 | } | |
84ed5e79 RE |
7709 | |
7710 | case GTU: | |
e6d29d15 | 7711 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 7712 | return CC_DGTUmode; |
e0b92319 | 7713 | |
e6d29d15 NS |
7714 | switch (cond2) |
7715 | { | |
7716 | case GTU: | |
7717 | return CC_DGTUmode; | |
7718 | case GEU: | |
7719 | return CC_DGEUmode; | |
7720 | case NE: | |
7721 | return CC_DNEmode; | |
7722 | default: | |
7723 | gcc_unreachable (); | |
7724 | } | |
84ed5e79 RE |
7725 | |
7726 | /* The remaining cases only occur when both comparisons are the | |
7727 | same. */ | |
7728 | case NE: | |
e6d29d15 | 7729 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
7730 | return CC_DNEmode; |
7731 | ||
7732 | case LE: | |
e6d29d15 | 7733 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
7734 | return CC_DLEmode; |
7735 | ||
7736 | case GE: | |
e6d29d15 | 7737 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
7738 | return CC_DGEmode; |
7739 | ||
7740 | case LEU: | |
e6d29d15 | 7741 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
7742 | return CC_DLEUmode; |
7743 | ||
7744 | case GEU: | |
e6d29d15 | 7745 | gcc_assert (cond1 == cond2); |
84ed5e79 | 7746 | return CC_DGEUmode; |
ad076f4e RE |
7747 | |
7748 | default: | |
e6d29d15 | 7749 | gcc_unreachable (); |
84ed5e79 | 7750 | } |
84ed5e79 RE |
7751 | } |
7752 | ||
7753 | enum machine_mode | |
e32bac5b | 7754 | arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) |
84ed5e79 RE |
7755 | { |
7756 | /* All floating point compares return CCFP if it is an equality | |
7757 | comparison, and CCFPE otherwise. */ | |
7758 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
7759 | { |
7760 | switch (op) | |
7761 | { | |
7762 | case EQ: | |
7763 | case NE: | |
7764 | case UNORDERED: | |
7765 | case ORDERED: | |
7766 | case UNLT: | |
7767 | case UNLE: | |
7768 | case UNGT: | |
7769 | case UNGE: | |
7770 | case UNEQ: | |
7771 | case LTGT: | |
7772 | return CCFPmode; | |
7773 | ||
7774 | case LT: | |
7775 | case LE: | |
7776 | case GT: | |
7777 | case GE: | |
9b66ebb1 | 7778 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK) |
9b6b54e2 | 7779 | return CCFPmode; |
e45b72c4 RE |
7780 | return CCFPEmode; |
7781 | ||
7782 | default: | |
e6d29d15 | 7783 | gcc_unreachable (); |
e45b72c4 RE |
7784 | } |
7785 | } | |
f676971a | 7786 | |
84ed5e79 RE |
7787 | /* A compare with a shifted operand. Because of canonicalization, the |
7788 | comparison will have to be swapped when we emit the assembler. */ | |
7789 | if (GET_MODE (y) == SImode && GET_CODE (y) == REG | |
7790 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
7791 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
7792 | || GET_CODE (x) == ROTATERT)) | |
7793 | return CC_SWPmode; | |
7794 | ||
04d8b819 RE |
7795 | /* This operation is performed swapped, but since we only rely on the Z |
7796 | flag we don't need an additional mode. */ | |
7797 | if (GET_MODE (y) == SImode && REG_P (y) | |
7798 | && GET_CODE (x) == NEG | |
7799 | && (op == EQ || op == NE)) | |
7800 | return CC_Zmode; | |
7801 | ||
f676971a | 7802 | /* This is a special case that is used by combine to allow a |
956d6950 | 7803 | comparison of a shifted byte load to be split into a zero-extend |
84ed5e79 | 7804 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 7805 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
7806 | if (GET_MODE (x) == SImode |
7807 | && GET_CODE (x) == ASHIFT | |
7808 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
7809 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
7810 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
7811 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
7812 | && (op == EQ || op == NE | |
7813 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
7814 | && GET_CODE (y) == CONST_INT) | |
7815 | return CC_Zmode; | |
7816 | ||
1646cf41 RE |
7817 | /* A construct for a conditional compare, if the false arm contains |
7818 | 0, then both conditions must be true, otherwise either condition | |
7819 | must be true. Not all conditions are possible, so CCmode is | |
7820 | returned if it can't be done. */ | |
7821 | if (GET_CODE (x) == IF_THEN_ELSE | |
7822 | && (XEXP (x, 2) == const0_rtx | |
7823 | || XEXP (x, 2) == const1_rtx) | |
ec8e098d PB |
7824 | && COMPARISON_P (XEXP (x, 0)) |
7825 | && COMPARISON_P (XEXP (x, 1))) | |
f676971a | 7826 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
03f1640c | 7827 | INTVAL (XEXP (x, 2))); |
1646cf41 RE |
7828 | |
7829 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
7830 | if (GET_CODE (x) == AND | |
ec8e098d PB |
7831 | && COMPARISON_P (XEXP (x, 0)) |
7832 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
7833 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
7834 | DOM_CC_X_AND_Y); | |
1646cf41 RE |
7835 | |
7836 | if (GET_CODE (x) == IOR | |
ec8e098d PB |
7837 | && COMPARISON_P (XEXP (x, 0)) |
7838 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
7839 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
7840 | DOM_CC_X_OR_Y); | |
1646cf41 | 7841 | |
defc0463 RE |
7842 | /* An operation (on Thumb) where we want to test for a single bit. |
7843 | This is done by shifting that bit up into the top bit of a | |
7844 | scratch register; we can then branch on the sign bit. */ | |
5b3e6663 | 7845 | if (TARGET_THUMB1 |
defc0463 RE |
7846 | && GET_MODE (x) == SImode |
7847 | && (op == EQ || op == NE) | |
f9fa4363 RE |
7848 | && GET_CODE (x) == ZERO_EXTRACT |
7849 | && XEXP (x, 1) == const1_rtx) | |
defc0463 RE |
7850 | return CC_Nmode; |
7851 | ||
84ed5e79 RE |
7852 | /* An operation that sets the condition codes as a side-effect, the |
7853 | V flag is not set correctly, so we can only use comparisons where | |
7854 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
defc0463 | 7855 | instead.) */ |
5b3e6663 | 7856 | /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */ |
84ed5e79 RE |
7857 | if (GET_MODE (x) == SImode |
7858 | && y == const0_rtx | |
7859 | && (op == EQ || op == NE || op == LT || op == GE) | |
7860 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
7861 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
7862 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
7863 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
7864 | || GET_CODE (x) == LSHIFTRT | |
7865 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
defc0463 | 7866 | || GET_CODE (x) == ROTATERT |
5b3e6663 | 7867 | || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT))) |
84ed5e79 RE |
7868 | return CC_NOOVmode; |
7869 | ||
84ed5e79 RE |
7870 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
7871 | return CC_Zmode; | |
7872 | ||
bd9c7e23 RE |
7873 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
7874 | && GET_CODE (x) == PLUS | |
7875 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
7876 | return CC_Cmode; | |
7877 | ||
84ed5e79 RE |
7878 | return CCmode; |
7879 | } | |
7880 | ||
ff9940b0 RE |
7881 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
7882 | return the rtx for register 0 in the proper mode. FP means this is a | |
7883 | floating point compare: I don't think that it is needed on the arm. */ | |
ff9940b0 | 7884 | rtx |
e32bac5b | 7885 | arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
ff9940b0 RE |
7886 | { |
7887 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); | |
d5b7b3ae | 7888 | rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); |
ff9940b0 | 7889 | |
d66437c5 | 7890 | emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); |
ff9940b0 RE |
7891 | |
7892 | return cc_reg; | |
7893 | } | |
7894 | ||
fcd53748 JT |
7895 | /* Generate a sequence of insns that will generate the correct return |
7896 | address mask depending on the physical architecture that the program | |
7897 | is running on. */ | |
fcd53748 | 7898 | rtx |
e32bac5b | 7899 | arm_gen_return_addr_mask (void) |
fcd53748 JT |
7900 | { |
7901 | rtx reg = gen_reg_rtx (Pmode); | |
7902 | ||
7903 | emit_insn (gen_return_addr_mask (reg)); | |
7904 | return reg; | |
7905 | } | |
7906 | ||
0a81f500 | 7907 | void |
e32bac5b | 7908 | arm_reload_in_hi (rtx *operands) |
0a81f500 | 7909 | { |
f9cc092a RE |
7910 | rtx ref = operands[1]; |
7911 | rtx base, scratch; | |
7912 | HOST_WIDE_INT offset = 0; | |
7913 | ||
7914 | if (GET_CODE (ref) == SUBREG) | |
7915 | { | |
ddef6bc7 | 7916 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
7917 | ref = SUBREG_REG (ref); |
7918 | } | |
7919 | ||
7920 | if (GET_CODE (ref) == REG) | |
7921 | { | |
7922 | /* We have a pseudo which has been spilt onto the stack; there | |
7923 | are two cases here: the first where there is a simple | |
7924 | stack-slot replacement and a second where the stack-slot is | |
7925 | out of range, or is used as a subreg. */ | |
7926 | if (reg_equiv_mem[REGNO (ref)]) | |
7927 | { | |
7928 | ref = reg_equiv_mem[REGNO (ref)]; | |
7929 | base = find_replacement (&XEXP (ref, 0)); | |
7930 | } | |
7931 | else | |
6354dc9b | 7932 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
7933 | base = reg_equiv_address[REGNO (ref)]; |
7934 | } | |
7935 | else | |
7936 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 7937 | |
e5e809f4 JL |
7938 | /* Handle the case where the address is too complex to be offset by 1. */ |
7939 | if (GET_CODE (base) == MINUS | |
7940 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
7941 | { | |
f9cc092a | 7942 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 7943 | |
d66437c5 | 7944 | emit_set_insn (base_plus, base); |
e5e809f4 JL |
7945 | base = base_plus; |
7946 | } | |
f9cc092a RE |
7947 | else if (GET_CODE (base) == PLUS) |
7948 | { | |
6354dc9b | 7949 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
7950 | HOST_WIDE_INT hi, lo; |
7951 | ||
7952 | offset += INTVAL (XEXP (base, 1)); | |
7953 | base = XEXP (base, 0); | |
7954 | ||
6354dc9b | 7955 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
7956 | /* Valid range for lo is -4095 -> 4095 */ |
7957 | lo = (offset >= 0 | |
7958 | ? (offset & 0xfff) | |
7959 | : -((-offset) & 0xfff)); | |
7960 | ||
7961 | /* Corner case, if lo is the max offset then we would be out of range | |
7962 | once we have added the additional 1 below, so bump the msb into the | |
7963 | pre-loading insn(s). */ | |
7964 | if (lo == 4095) | |
7965 | lo &= 0x7ff; | |
7966 | ||
30cf4896 KG |
7967 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
7968 | ^ (HOST_WIDE_INT) 0x80000000) | |
7969 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 7970 | |
e6d29d15 | 7971 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
7972 | |
7973 | if (hi != 0) | |
7974 | { | |
7975 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
7976 | ||
7977 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 7978 | that require more than one insn. */ |
f9cc092a RE |
7979 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
7980 | base = base_plus; | |
7981 | offset = lo; | |
7982 | } | |
7983 | } | |
e5e809f4 | 7984 | |
3a1944a6 RE |
7985 | /* Operands[2] may overlap operands[0] (though it won't overlap |
7986 | operands[1]), that's why we asked for a DImode reg -- so we can | |
7987 | use the bit that does not overlap. */ | |
7988 | if (REGNO (operands[2]) == REGNO (operands[0])) | |
7989 | scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
7990 | else | |
7991 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
7992 | ||
f9cc092a RE |
7993 | emit_insn (gen_zero_extendqisi2 (scratch, |
7994 | gen_rtx_MEM (QImode, | |
7995 | plus_constant (base, | |
7996 | offset)))); | |
43cffd11 | 7997 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
f676971a | 7998 | gen_rtx_MEM (QImode, |
f9cc092a RE |
7999 | plus_constant (base, |
8000 | offset + 1)))); | |
5895f793 | 8001 | if (!BYTES_BIG_ENDIAN) |
d66437c5 RE |
8002 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
8003 | gen_rtx_IOR (SImode, | |
8004 | gen_rtx_ASHIFT | |
8005 | (SImode, | |
8006 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
8007 | GEN_INT (8)), | |
8008 | scratch)); | |
0a81f500 | 8009 | else |
d66437c5 RE |
8010 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
8011 | gen_rtx_IOR (SImode, | |
8012 | gen_rtx_ASHIFT (SImode, scratch, | |
8013 | GEN_INT (8)), | |
8014 | gen_rtx_SUBREG (SImode, operands[0], 0))); | |
0a81f500 RE |
8015 | } |
8016 | ||
72ac76be | 8017 | /* Handle storing a half-word to memory during reload by synthesizing as two |
f9cc092a RE |
8018 | byte stores. Take care not to clobber the input values until after we |
8019 | have moved them somewhere safe. This code assumes that if the DImode | |
8020 | scratch in operands[2] overlaps either the input value or output address | |
8021 | in some way, then that value must die in this insn (we absolutely need | |
8022 | two scratch registers for some corner cases). */ | |
f3bb6135 | 8023 | void |
e32bac5b | 8024 | arm_reload_out_hi (rtx *operands) |
af48348a | 8025 | { |
f9cc092a RE |
8026 | rtx ref = operands[0]; |
8027 | rtx outval = operands[1]; | |
8028 | rtx base, scratch; | |
8029 | HOST_WIDE_INT offset = 0; | |
8030 | ||
8031 | if (GET_CODE (ref) == SUBREG) | |
8032 | { | |
ddef6bc7 | 8033 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
8034 | ref = SUBREG_REG (ref); |
8035 | } | |
8036 | ||
f9cc092a RE |
8037 | if (GET_CODE (ref) == REG) |
8038 | { | |
8039 | /* We have a pseudo which has been spilt onto the stack; there | |
8040 | are two cases here: the first where there is a simple | |
8041 | stack-slot replacement and a second where the stack-slot is | |
8042 | out of range, or is used as a subreg. */ | |
8043 | if (reg_equiv_mem[REGNO (ref)]) | |
8044 | { | |
8045 | ref = reg_equiv_mem[REGNO (ref)]; | |
8046 | base = find_replacement (&XEXP (ref, 0)); | |
8047 | } | |
8048 | else | |
6354dc9b | 8049 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
8050 | base = reg_equiv_address[REGNO (ref)]; |
8051 | } | |
8052 | else | |
8053 | base = find_replacement (&XEXP (ref, 0)); | |
8054 | ||
8055 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
8056 | ||
8057 | /* Handle the case where the address is too complex to be offset by 1. */ | |
8058 | if (GET_CODE (base) == MINUS | |
8059 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
8060 | { | |
8061 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8062 | ||
8063 | /* Be careful not to destroy OUTVAL. */ | |
8064 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
8065 | { | |
8066 | /* Updating base_plus might destroy outval, see if we can | |
8067 | swap the scratch and base_plus. */ | |
5895f793 | 8068 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
8069 | { |
8070 | rtx tmp = scratch; | |
8071 | scratch = base_plus; | |
8072 | base_plus = tmp; | |
8073 | } | |
8074 | else | |
8075 | { | |
8076 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
8077 | ||
8078 | /* Be conservative and copy OUTVAL into the scratch now, | |
8079 | this should only be necessary if outval is a subreg | |
8080 | of something larger than a word. */ | |
8081 | /* XXX Might this clobber base? I can't see how it can, | |
8082 | since scratch is known to overlap with OUTVAL, and | |
8083 | must be wider than a word. */ | |
8084 | emit_insn (gen_movhi (scratch_hi, outval)); | |
8085 | outval = scratch_hi; | |
8086 | } | |
8087 | } | |
8088 | ||
d66437c5 | 8089 | emit_set_insn (base_plus, base); |
f9cc092a RE |
8090 | base = base_plus; |
8091 | } | |
8092 | else if (GET_CODE (base) == PLUS) | |
8093 | { | |
6354dc9b | 8094 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
8095 | HOST_WIDE_INT hi, lo; |
8096 | ||
8097 | offset += INTVAL (XEXP (base, 1)); | |
8098 | base = XEXP (base, 0); | |
8099 | ||
6354dc9b | 8100 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
8101 | /* Valid range for lo is -4095 -> 4095 */ |
8102 | lo = (offset >= 0 | |
8103 | ? (offset & 0xfff) | |
8104 | : -((-offset) & 0xfff)); | |
8105 | ||
8106 | /* Corner case, if lo is the max offset then we would be out of range | |
8107 | once we have added the additional 1 below, so bump the msb into the | |
8108 | pre-loading insn(s). */ | |
8109 | if (lo == 4095) | |
8110 | lo &= 0x7ff; | |
8111 | ||
30cf4896 KG |
8112 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
8113 | ^ (HOST_WIDE_INT) 0x80000000) | |
8114 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 8115 | |
e6d29d15 | 8116 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
8117 | |
8118 | if (hi != 0) | |
8119 | { | |
8120 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8121 | ||
8122 | /* Be careful not to destroy OUTVAL. */ | |
8123 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
8124 | { | |
8125 | /* Updating base_plus might destroy outval, see if we | |
8126 | can swap the scratch and base_plus. */ | |
5895f793 | 8127 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
8128 | { |
8129 | rtx tmp = scratch; | |
8130 | scratch = base_plus; | |
8131 | base_plus = tmp; | |
8132 | } | |
8133 | else | |
8134 | { | |
8135 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
8136 | ||
8137 | /* Be conservative and copy outval into scratch now, | |
8138 | this should only be necessary if outval is a | |
8139 | subreg of something larger than a word. */ | |
8140 | /* XXX Might this clobber base? I can't see how it | |
8141 | can, since scratch is known to overlap with | |
8142 | outval. */ | |
8143 | emit_insn (gen_movhi (scratch_hi, outval)); | |
8144 | outval = scratch_hi; | |
8145 | } | |
8146 | } | |
8147 | ||
8148 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 8149 | that require more than one insn. */ |
f9cc092a RE |
8150 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
8151 | base = base_plus; | |
8152 | offset = lo; | |
8153 | } | |
8154 | } | |
af48348a | 8155 | |
b5cc037f RE |
8156 | if (BYTES_BIG_ENDIAN) |
8157 | { | |
f676971a | 8158 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
f9cc092a | 8159 | plus_constant (base, offset + 1)), |
5d5603e2 | 8160 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
8161 | emit_insn (gen_lshrsi3 (scratch, |
8162 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 8163 | GEN_INT (8))); |
f9cc092a | 8164 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 8165 | gen_lowpart (QImode, scratch))); |
b5cc037f RE |
8166 | } |
8167 | else | |
8168 | { | |
f9cc092a | 8169 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 8170 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
8171 | emit_insn (gen_lshrsi3 (scratch, |
8172 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 8173 | GEN_INT (8))); |
f9cc092a RE |
8174 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
8175 | plus_constant (base, offset + 1)), | |
5d5603e2 | 8176 | gen_lowpart (QImode, scratch))); |
b5cc037f | 8177 | } |
af48348a | 8178 | } |
866af8a9 JB |
8179 | |
8180 | /* Return true if a type must be passed in memory. For AAPCS, small aggregates | |
8181 | (padded to the size of a word) should be passed in a register. */ | |
8182 | ||
8183 | static bool | |
586de218 | 8184 | arm_must_pass_in_stack (enum machine_mode mode, const_tree type) |
866af8a9 JB |
8185 | { |
8186 | if (TARGET_AAPCS_BASED) | |
8187 | return must_pass_in_stack_var_size (mode, type); | |
8188 | else | |
8189 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
8190 | } | |
8191 | ||
8192 | ||
8193 | /* For use by FUNCTION_ARG_PADDING (MODE, TYPE). | |
8194 | Return true if an argument passed on the stack should be padded upwards, | |
5a29b385 PB |
8195 | i.e. if the least-significant byte has useful data. |
8196 | For legacy APCS ABIs we use the default. For AAPCS based ABIs small | |
8197 | aggregate types are placed in the lowest memory address. */ | |
866af8a9 JB |
8198 | |
8199 | bool | |
586de218 | 8200 | arm_pad_arg_upward (enum machine_mode mode, const_tree type) |
866af8a9 JB |
8201 | { |
8202 | if (!TARGET_AAPCS_BASED) | |
5a29b385 | 8203 | return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward; |
866af8a9 JB |
8204 | |
8205 | if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type)) | |
8206 | return false; | |
8207 | ||
8208 | return true; | |
8209 | } | |
8210 | ||
8211 | ||
8212 | /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). | |
8213 | For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant | |
8214 | byte of the register has useful data, and return the opposite if the | |
8215 | most significant byte does. | |
8216 | For AAPCS, small aggregates and small complex types are always padded | |
8217 | upwards. */ | |
8218 | ||
8219 | bool | |
8220 | arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, | |
8221 | tree type, int first ATTRIBUTE_UNUSED) | |
8222 | { | |
8223 | if (TARGET_AAPCS_BASED | |
8224 | && BYTES_BIG_ENDIAN | |
8225 | && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE) | |
8226 | && int_size_in_bytes (type) <= 4) | |
8227 | return true; | |
8228 | ||
8229 | /* Otherwise, use default padding. */ | |
8230 | return !BYTES_BIG_ENDIAN; | |
8231 | } | |
8232 | ||
2b835d68 | 8233 | \f |
d5b7b3ae RE |
8234 | /* Print a symbolic form of X to the debug file, F. */ |
8235 | static void | |
e32bac5b | 8236 | arm_print_value (FILE *f, rtx x) |
d5b7b3ae RE |
8237 | { |
8238 | switch (GET_CODE (x)) | |
8239 | { | |
8240 | case CONST_INT: | |
8241 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
8242 | return; | |
8243 | ||
8244 | case CONST_DOUBLE: | |
8245 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
8246 | return; | |
8247 | ||
5a9335ef NC |
8248 | case CONST_VECTOR: |
8249 | { | |
8250 | int i; | |
8251 | ||
8252 | fprintf (f, "<"); | |
8253 | for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) | |
8254 | { | |
8255 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); | |
8256 | if (i < (CONST_VECTOR_NUNITS (x) - 1)) | |
8257 | fputc (',', f); | |
8258 | } | |
8259 | fprintf (f, ">"); | |
8260 | } | |
8261 | return; | |
8262 | ||
d5b7b3ae RE |
8263 | case CONST_STRING: |
8264 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
8265 | return; | |
8266 | ||
8267 | case SYMBOL_REF: | |
8268 | fprintf (f, "`%s'", XSTR (x, 0)); | |
8269 | return; | |
8270 | ||
8271 | case LABEL_REF: | |
8272 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
8273 | return; | |
8274 | ||
8275 | case CONST: | |
8276 | arm_print_value (f, XEXP (x, 0)); | |
8277 | return; | |
8278 | ||
8279 | case PLUS: | |
8280 | arm_print_value (f, XEXP (x, 0)); | |
8281 | fprintf (f, "+"); | |
8282 | arm_print_value (f, XEXP (x, 1)); | |
8283 | return; | |
8284 | ||
8285 | case PC: | |
8286 | fprintf (f, "pc"); | |
8287 | return; | |
8288 | ||
8289 | default: | |
8290 | fprintf (f, "????"); | |
8291 | return; | |
8292 | } | |
8293 | } | |
8294 | \f | |
2b835d68 | 8295 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 8296 | |
949d79eb RE |
8297 | /* Arm instructions cannot load a large constant directly into a |
8298 | register; they have to come from a pc relative load. The constant | |
8299 | must therefore be placed in the addressable range of the pc | |
8300 | relative load. Depending on the precise pc relative load | |
8301 | instruction the range is somewhere between 256 bytes and 4k. This | |
8302 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
8303 | generate code to branch around it. |
8304 | ||
949d79eb RE |
8305 | It is important to minimize this, since the branches will slow |
8306 | things down and make the code larger. | |
2b835d68 | 8307 | |
949d79eb RE |
8308 | Normally we can hide the table after an existing unconditional |
8309 | branch so that there is no interruption of the flow, but in the | |
8310 | worst case the code looks like this: | |
2b835d68 RE |
8311 | |
8312 | ldr rn, L1 | |
949d79eb | 8313 | ... |
2b835d68 RE |
8314 | b L2 |
8315 | align | |
8316 | L1: .long value | |
8317 | L2: | |
949d79eb | 8318 | ... |
2b835d68 | 8319 | |
2b835d68 | 8320 | ldr rn, L3 |
949d79eb | 8321 | ... |
2b835d68 RE |
8322 | b L4 |
8323 | align | |
2b835d68 RE |
8324 | L3: .long value |
8325 | L4: | |
949d79eb RE |
8326 | ... |
8327 | ||
8328 | We fix this by performing a scan after scheduling, which notices | |
8329 | which instructions need to have their operands fetched from the | |
8330 | constant table and builds the table. | |
8331 | ||
8332 | The algorithm starts by building a table of all the constants that | |
8333 | need fixing up and all the natural barriers in the function (places | |
8334 | where a constant table can be dropped without breaking the flow). | |
8335 | For each fixup we note how far the pc-relative replacement will be | |
8336 | able to reach and the offset of the instruction into the function. | |
8337 | ||
8338 | Having built the table we then group the fixes together to form | |
8339 | tables that are as large as possible (subject to addressing | |
8340 | constraints) and emit each table of constants after the last | |
8341 | barrier that is within range of all the instructions in the group. | |
8342 | If a group does not contain a barrier, then we forcibly create one | |
8343 | by inserting a jump instruction into the flow. Once the table has | |
8344 | been inserted, the insns are then modified to reference the | |
8345 | relevant entry in the pool. | |
8346 | ||
6354dc9b | 8347 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 8348 | |
d5b7b3ae | 8349 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
8350 | aligning the pools to the start of cache lines; this alignment |
8351 | would need to be taken into account when calculating addressability | |
6354dc9b | 8352 | of a pool. */ |
2b835d68 | 8353 | |
d5b7b3ae RE |
8354 | /* These typedefs are located at the start of this file, so that |
8355 | they can be used in the prototypes there. This comment is to | |
8356 | remind readers of that fact so that the following structures | |
8357 | can be understood more easily. | |
8358 | ||
8359 | typedef struct minipool_node Mnode; | |
8360 | typedef struct minipool_fixup Mfix; */ | |
8361 | ||
8362 | struct minipool_node | |
8363 | { | |
8364 | /* Doubly linked chain of entries. */ | |
8365 | Mnode * next; | |
8366 | Mnode * prev; | |
8367 | /* The maximum offset into the code that this entry can be placed. While | |
8368 | pushing fixes for forward references, all entries are sorted in order | |
8369 | of increasing max_address. */ | |
8370 | HOST_WIDE_INT max_address; | |
5519a4f9 | 8371 | /* Similarly for an entry inserted for a backwards ref. */ |
d5b7b3ae RE |
8372 | HOST_WIDE_INT min_address; |
8373 | /* The number of fixes referencing this entry. This can become zero | |
8374 | if we "unpush" an entry. In this case we ignore the entry when we | |
8375 | come to emit the code. */ | |
8376 | int refcount; | |
8377 | /* The offset from the start of the minipool. */ | |
8378 | HOST_WIDE_INT offset; | |
8379 | /* The value in table. */ | |
8380 | rtx value; | |
8381 | /* The mode of value. */ | |
8382 | enum machine_mode mode; | |
5a9335ef NC |
8383 | /* The size of the value. With iWMMXt enabled |
8384 | sizes > 4 also imply an alignment of 8-bytes. */ | |
d5b7b3ae RE |
8385 | int fix_size; |
8386 | }; | |
8387 | ||
8388 | struct minipool_fixup | |
2b835d68 | 8389 | { |
d5b7b3ae RE |
8390 | Mfix * next; |
8391 | rtx insn; | |
8392 | HOST_WIDE_INT address; | |
8393 | rtx * loc; | |
8394 | enum machine_mode mode; | |
8395 | int fix_size; | |
8396 | rtx value; | |
8397 | Mnode * minipool; | |
8398 | HOST_WIDE_INT forwards; | |
8399 | HOST_WIDE_INT backwards; | |
8400 | }; | |
2b835d68 | 8401 | |
d5b7b3ae RE |
8402 | /* Fixes less than a word need padding out to a word boundary. */ |
8403 | #define MINIPOOL_FIX_SIZE(mode) \ | |
8404 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 8405 | |
d5b7b3ae RE |
8406 | static Mnode * minipool_vector_head; |
8407 | static Mnode * minipool_vector_tail; | |
8408 | static rtx minipool_vector_label; | |
34a9f549 | 8409 | static int minipool_pad; |
332072db | 8410 | |
d5b7b3ae RE |
8411 | /* The linked list of all minipool fixes required for this function. */ |
8412 | Mfix * minipool_fix_head; | |
8413 | Mfix * minipool_fix_tail; | |
8414 | /* The fix entry for the current minipool, once it has been placed. */ | |
8415 | Mfix * minipool_barrier; | |
8416 | ||
8417 | /* Determines if INSN is the start of a jump table. Returns the end | |
8418 | of the TABLE or NULL_RTX. */ | |
8419 | static rtx | |
e32bac5b | 8420 | is_jump_table (rtx insn) |
2b835d68 | 8421 | { |
d5b7b3ae | 8422 | rtx table; |
f676971a | 8423 | |
d5b7b3ae RE |
8424 | if (GET_CODE (insn) == JUMP_INSN |
8425 | && JUMP_LABEL (insn) != NULL | |
8426 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
8427 | == next_real_insn (insn)) | |
8428 | && table != NULL | |
8429 | && GET_CODE (table) == JUMP_INSN | |
8430 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
8431 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
8432 | return table; | |
8433 | ||
8434 | return NULL_RTX; | |
2b835d68 RE |
8435 | } |
8436 | ||
657d9449 RE |
8437 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
8438 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
8439 | #endif | |
8440 | ||
d5b7b3ae | 8441 | static HOST_WIDE_INT |
e32bac5b | 8442 | get_jump_table_size (rtx insn) |
2b835d68 | 8443 | { |
657d9449 RE |
8444 | /* ADDR_VECs only take room if read-only data does into the text |
8445 | section. */ | |
d6b5193b | 8446 | if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section) |
657d9449 RE |
8447 | { |
8448 | rtx body = PATTERN (insn); | |
8449 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
5b3e6663 PB |
8450 | HOST_WIDE_INT size; |
8451 | HOST_WIDE_INT modesize; | |
2b835d68 | 8452 | |
5b3e6663 PB |
8453 | modesize = GET_MODE_SIZE (GET_MODE (body)); |
8454 | size = modesize * XVECLEN (body, elt); | |
8455 | switch (modesize) | |
8456 | { | |
8457 | case 1: | |
88512ba0 | 8458 | /* Round up size of TBB table to a halfword boundary. */ |
5b3e6663 PB |
8459 | size = (size + 1) & ~(HOST_WIDE_INT)1; |
8460 | break; | |
8461 | case 2: | |
7a085dce | 8462 | /* No padding necessary for TBH. */ |
5b3e6663 PB |
8463 | break; |
8464 | case 4: | |
8465 | /* Add two bytes for alignment on Thumb. */ | |
8466 | if (TARGET_THUMB) | |
8467 | size += 2; | |
8468 | break; | |
8469 | default: | |
8470 | gcc_unreachable (); | |
8471 | } | |
8472 | return size; | |
657d9449 RE |
8473 | } |
8474 | ||
8475 | return 0; | |
d5b7b3ae | 8476 | } |
2b835d68 | 8477 | |
d5b7b3ae RE |
8478 | /* Move a minipool fix MP from its current location to before MAX_MP. |
8479 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
093354e0 | 8480 | constraints may need updating. */ |
d5b7b3ae | 8481 | static Mnode * |
e32bac5b RE |
8482 | move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, |
8483 | HOST_WIDE_INT max_address) | |
d5b7b3ae | 8484 | { |
e6d29d15 NS |
8485 | /* The code below assumes these are different. */ |
8486 | gcc_assert (mp != max_mp); | |
d5b7b3ae RE |
8487 | |
8488 | if (max_mp == NULL) | |
8489 | { | |
8490 | if (max_address < mp->max_address) | |
8491 | mp->max_address = max_address; | |
8492 | } | |
8493 | else | |
2b835d68 | 8494 | { |
d5b7b3ae RE |
8495 | if (max_address > max_mp->max_address - mp->fix_size) |
8496 | mp->max_address = max_mp->max_address - mp->fix_size; | |
8497 | else | |
8498 | mp->max_address = max_address; | |
2b835d68 | 8499 | |
d5b7b3ae RE |
8500 | /* Unlink MP from its current position. Since max_mp is non-null, |
8501 | mp->prev must be non-null. */ | |
8502 | mp->prev->next = mp->next; | |
8503 | if (mp->next != NULL) | |
8504 | mp->next->prev = mp->prev; | |
8505 | else | |
8506 | minipool_vector_tail = mp->prev; | |
2b835d68 | 8507 | |
d5b7b3ae RE |
8508 | /* Re-insert it before MAX_MP. */ |
8509 | mp->next = max_mp; | |
8510 | mp->prev = max_mp->prev; | |
8511 | max_mp->prev = mp; | |
f676971a | 8512 | |
d5b7b3ae RE |
8513 | if (mp->prev != NULL) |
8514 | mp->prev->next = mp; | |
8515 | else | |
8516 | minipool_vector_head = mp; | |
8517 | } | |
2b835d68 | 8518 | |
d5b7b3ae RE |
8519 | /* Save the new entry. */ |
8520 | max_mp = mp; | |
8521 | ||
d6a7951f | 8522 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
8523 | required. */ |
8524 | while (mp->prev != NULL | |
8525 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
8526 | { | |
8527 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
8528 | mp = mp->prev; | |
2b835d68 RE |
8529 | } |
8530 | ||
d5b7b3ae | 8531 | return max_mp; |
2b835d68 RE |
8532 | } |
8533 | ||
d5b7b3ae RE |
8534 | /* Add a constant to the minipool for a forward reference. Returns the |
8535 | node added or NULL if the constant will not fit in this pool. */ | |
8536 | static Mnode * | |
e32bac5b | 8537 | add_minipool_forward_ref (Mfix *fix) |
d5b7b3ae RE |
8538 | { |
8539 | /* If set, max_mp is the first pool_entry that has a lower | |
8540 | constraint than the one we are trying to add. */ | |
8541 | Mnode * max_mp = NULL; | |
34a9f549 | 8542 | HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad; |
d5b7b3ae | 8543 | Mnode * mp; |
f676971a | 8544 | |
7a7017bc PB |
8545 | /* If the minipool starts before the end of FIX->INSN then this FIX |
8546 | can not be placed into the current pool. Furthermore, adding the | |
8547 | new constant pool entry may cause the pool to start FIX_SIZE bytes | |
8548 | earlier. */ | |
d5b7b3ae | 8549 | if (minipool_vector_head && |
7a7017bc PB |
8550 | (fix->address + get_attr_length (fix->insn) |
8551 | >= minipool_vector_head->max_address - fix->fix_size)) | |
d5b7b3ae | 8552 | return NULL; |
2b835d68 | 8553 | |
d5b7b3ae RE |
8554 | /* Scan the pool to see if a constant with the same value has |
8555 | already been added. While we are doing this, also note the | |
8556 | location where we must insert the constant if it doesn't already | |
8557 | exist. */ | |
8558 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
8559 | { | |
8560 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
8561 | && fix->mode == mp->mode | |
8562 | && (GET_CODE (fix->value) != CODE_LABEL | |
8563 | || (CODE_LABEL_NUMBER (fix->value) | |
8564 | == CODE_LABEL_NUMBER (mp->value))) | |
8565 | && rtx_equal_p (fix->value, mp->value)) | |
8566 | { | |
8567 | /* More than one fix references this entry. */ | |
8568 | mp->refcount++; | |
8569 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
8570 | } | |
8571 | ||
8572 | /* Note the insertion point if necessary. */ | |
8573 | if (max_mp == NULL | |
8574 | && mp->max_address > max_address) | |
8575 | max_mp = mp; | |
5a9335ef NC |
8576 | |
8577 | /* If we are inserting an 8-bytes aligned quantity and | |
8578 | we have not already found an insertion point, then | |
8579 | make sure that all such 8-byte aligned quantities are | |
8580 | placed at the start of the pool. */ | |
5848830f | 8581 | if (ARM_DOUBLEWORD_ALIGN |
5a9335ef | 8582 | && max_mp == NULL |
88f77cba JB |
8583 | && fix->fix_size >= 8 |
8584 | && mp->fix_size < 8) | |
5a9335ef NC |
8585 | { |
8586 | max_mp = mp; | |
8587 | max_address = mp->max_address; | |
8588 | } | |
d5b7b3ae RE |
8589 | } |
8590 | ||
8591 | /* The value is not currently in the minipool, so we need to create | |
8592 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
8593 | the end of the list since the placement is less constrained than | |
8594 | any existing entry. Otherwise, we insert the new fix before | |
6bc82793 | 8595 | MAX_MP and, if necessary, adjust the constraints on the other |
d5b7b3ae | 8596 | entries. */ |
5ed6ace5 | 8597 | mp = XNEW (Mnode); |
d5b7b3ae RE |
8598 | mp->fix_size = fix->fix_size; |
8599 | mp->mode = fix->mode; | |
8600 | mp->value = fix->value; | |
8601 | mp->refcount = 1; | |
8602 | /* Not yet required for a backwards ref. */ | |
8603 | mp->min_address = -65536; | |
8604 | ||
8605 | if (max_mp == NULL) | |
8606 | { | |
8607 | mp->max_address = max_address; | |
8608 | mp->next = NULL; | |
8609 | mp->prev = minipool_vector_tail; | |
8610 | ||
8611 | if (mp->prev == NULL) | |
8612 | { | |
8613 | minipool_vector_head = mp; | |
8614 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 8615 | } |
2b835d68 | 8616 | else |
d5b7b3ae | 8617 | mp->prev->next = mp; |
2b835d68 | 8618 | |
d5b7b3ae RE |
8619 | minipool_vector_tail = mp; |
8620 | } | |
8621 | else | |
8622 | { | |
8623 | if (max_address > max_mp->max_address - mp->fix_size) | |
8624 | mp->max_address = max_mp->max_address - mp->fix_size; | |
8625 | else | |
8626 | mp->max_address = max_address; | |
8627 | ||
8628 | mp->next = max_mp; | |
8629 | mp->prev = max_mp->prev; | |
8630 | max_mp->prev = mp; | |
8631 | if (mp->prev != NULL) | |
8632 | mp->prev->next = mp; | |
8633 | else | |
8634 | minipool_vector_head = mp; | |
8635 | } | |
8636 | ||
8637 | /* Save the new entry. */ | |
8638 | max_mp = mp; | |
8639 | ||
d6a7951f | 8640 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
8641 | required. */ |
8642 | while (mp->prev != NULL | |
8643 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
8644 | { | |
8645 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
8646 | mp = mp->prev; | |
2b835d68 RE |
8647 | } |
8648 | ||
d5b7b3ae RE |
8649 | return max_mp; |
8650 | } | |
8651 | ||
8652 | static Mnode * | |
e32bac5b RE |
8653 | move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, |
8654 | HOST_WIDE_INT min_address) | |
d5b7b3ae RE |
8655 | { |
8656 | HOST_WIDE_INT offset; | |
8657 | ||
e6d29d15 NS |
8658 | /* The code below assumes these are different. */ |
8659 | gcc_assert (mp != min_mp); | |
d5b7b3ae RE |
8660 | |
8661 | if (min_mp == NULL) | |
2b835d68 | 8662 | { |
d5b7b3ae RE |
8663 | if (min_address > mp->min_address) |
8664 | mp->min_address = min_address; | |
8665 | } | |
8666 | else | |
8667 | { | |
8668 | /* We will adjust this below if it is too loose. */ | |
8669 | mp->min_address = min_address; | |
8670 | ||
8671 | /* Unlink MP from its current position. Since min_mp is non-null, | |
8672 | mp->next must be non-null. */ | |
8673 | mp->next->prev = mp->prev; | |
8674 | if (mp->prev != NULL) | |
8675 | mp->prev->next = mp->next; | |
8676 | else | |
8677 | minipool_vector_head = mp->next; | |
8678 | ||
8679 | /* Reinsert it after MIN_MP. */ | |
8680 | mp->prev = min_mp; | |
8681 | mp->next = min_mp->next; | |
8682 | min_mp->next = mp; | |
8683 | if (mp->next != NULL) | |
8684 | mp->next->prev = mp; | |
2b835d68 | 8685 | else |
d5b7b3ae RE |
8686 | minipool_vector_tail = mp; |
8687 | } | |
8688 | ||
8689 | min_mp = mp; | |
8690 | ||
8691 | offset = 0; | |
8692 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
8693 | { | |
8694 | mp->offset = offset; | |
8695 | if (mp->refcount > 0) | |
8696 | offset += mp->fix_size; | |
8697 | ||
8698 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
8699 | mp->next->min_address = mp->min_address + mp->fix_size; | |
8700 | } | |
8701 | ||
8702 | return min_mp; | |
f676971a | 8703 | } |
d5b7b3ae RE |
8704 | |
8705 | /* Add a constant to the minipool for a backward reference. Returns the | |
f676971a | 8706 | node added or NULL if the constant will not fit in this pool. |
d5b7b3ae RE |
8707 | |
8708 | Note that the code for insertion for a backwards reference can be | |
8709 | somewhat confusing because the calculated offsets for each fix do | |
8710 | not take into account the size of the pool (which is still under | |
8711 | construction. */ | |
8712 | static Mnode * | |
e32bac5b | 8713 | add_minipool_backward_ref (Mfix *fix) |
d5b7b3ae RE |
8714 | { |
8715 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
8716 | than the one we are trying to add. */ | |
e32bac5b | 8717 | Mnode *min_mp = NULL; |
d5b7b3ae RE |
8718 | /* This can be negative, since it is only a constraint. */ |
8719 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
e32bac5b | 8720 | Mnode *mp; |
d5b7b3ae RE |
8721 | |
8722 | /* If we can't reach the current pool from this insn, or if we can't | |
8723 | insert this entry at the end of the pool without pushing other | |
8724 | fixes out of range, then we don't try. This ensures that we | |
8725 | can't fail later on. */ | |
8726 | if (min_address >= minipool_barrier->address | |
8727 | || (minipool_vector_tail->min_address + fix->fix_size | |
8728 | >= minipool_barrier->address)) | |
8729 | return NULL; | |
8730 | ||
8731 | /* Scan the pool to see if a constant with the same value has | |
8732 | already been added. While we are doing this, also note the | |
8733 | location where we must insert the constant if it doesn't already | |
8734 | exist. */ | |
8735 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
8736 | { | |
8737 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
8738 | && fix->mode == mp->mode | |
8739 | && (GET_CODE (fix->value) != CODE_LABEL | |
8740 | || (CODE_LABEL_NUMBER (fix->value) | |
8741 | == CODE_LABEL_NUMBER (mp->value))) | |
8742 | && rtx_equal_p (fix->value, mp->value) | |
8743 | /* Check that there is enough slack to move this entry to the | |
8744 | end of the table (this is conservative). */ | |
f676971a EC |
8745 | && (mp->max_address |
8746 | > (minipool_barrier->address | |
d5b7b3ae RE |
8747 | + minipool_vector_tail->offset |
8748 | + minipool_vector_tail->fix_size))) | |
8749 | { | |
8750 | mp->refcount++; | |
8751 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
8752 | } | |
8753 | ||
8754 | if (min_mp != NULL) | |
8755 | mp->min_address += fix->fix_size; | |
8756 | else | |
8757 | { | |
8758 | /* Note the insertion point if necessary. */ | |
8759 | if (mp->min_address < min_address) | |
5a9335ef NC |
8760 | { |
8761 | /* For now, we do not allow the insertion of 8-byte alignment | |
8762 | requiring nodes anywhere but at the start of the pool. */ | |
5848830f | 8763 | if (ARM_DOUBLEWORD_ALIGN |
88f77cba | 8764 | && fix->fix_size >= 8 && mp->fix_size < 8) |
5a9335ef NC |
8765 | return NULL; |
8766 | else | |
8767 | min_mp = mp; | |
8768 | } | |
d5b7b3ae RE |
8769 | else if (mp->max_address |
8770 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
8771 | { | |
8772 | /* Inserting before this entry would push the fix beyond | |
8773 | its maximum address (which can happen if we have | |
8774 | re-located a forwards fix); force the new fix to come | |
8775 | after it. */ | |
8776 | min_mp = mp; | |
8777 | min_address = mp->min_address + fix->fix_size; | |
8778 | } | |
5a9335ef NC |
8779 | /* If we are inserting an 8-bytes aligned quantity and |
8780 | we have not already found an insertion point, then | |
8781 | make sure that all such 8-byte aligned quantities are | |
8782 | placed at the start of the pool. */ | |
5848830f | 8783 | else if (ARM_DOUBLEWORD_ALIGN |
5a9335ef | 8784 | && min_mp == NULL |
88f77cba | 8785 | && fix->fix_size >= 8 |
5a9335ef NC |
8786 | && mp->fix_size < 8) |
8787 | { | |
8788 | min_mp = mp; | |
8789 | min_address = mp->min_address + fix->fix_size; | |
8790 | } | |
d5b7b3ae RE |
8791 | } |
8792 | } | |
8793 | ||
8794 | /* We need to create a new entry. */ | |
5ed6ace5 | 8795 | mp = XNEW (Mnode); |
d5b7b3ae RE |
8796 | mp->fix_size = fix->fix_size; |
8797 | mp->mode = fix->mode; | |
8798 | mp->value = fix->value; | |
8799 | mp->refcount = 1; | |
8800 | mp->max_address = minipool_barrier->address + 65536; | |
8801 | ||
8802 | mp->min_address = min_address; | |
8803 | ||
8804 | if (min_mp == NULL) | |
8805 | { | |
8806 | mp->prev = NULL; | |
8807 | mp->next = minipool_vector_head; | |
8808 | ||
8809 | if (mp->next == NULL) | |
8810 | { | |
8811 | minipool_vector_tail = mp; | |
8812 | minipool_vector_label = gen_label_rtx (); | |
8813 | } | |
8814 | else | |
8815 | mp->next->prev = mp; | |
8816 | ||
8817 | minipool_vector_head = mp; | |
8818 | } | |
8819 | else | |
8820 | { | |
8821 | mp->next = min_mp->next; | |
8822 | mp->prev = min_mp; | |
8823 | min_mp->next = mp; | |
f676971a | 8824 | |
d5b7b3ae RE |
8825 | if (mp->next != NULL) |
8826 | mp->next->prev = mp; | |
8827 | else | |
8828 | minipool_vector_tail = mp; | |
8829 | } | |
8830 | ||
8831 | /* Save the new entry. */ | |
8832 | min_mp = mp; | |
8833 | ||
8834 | if (mp->prev) | |
8835 | mp = mp->prev; | |
8836 | else | |
8837 | mp->offset = 0; | |
8838 | ||
8839 | /* Scan over the following entries and adjust their offsets. */ | |
8840 | while (mp->next != NULL) | |
8841 | { | |
8842 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
8843 | mp->next->min_address = mp->min_address + mp->fix_size; | |
8844 | ||
8845 | if (mp->refcount) | |
8846 | mp->next->offset = mp->offset + mp->fix_size; | |
8847 | else | |
8848 | mp->next->offset = mp->offset; | |
8849 | ||
8850 | mp = mp->next; | |
8851 | } | |
8852 | ||
8853 | return min_mp; | |
8854 | } | |
8855 | ||
8856 | static void | |
e32bac5b | 8857 | assign_minipool_offsets (Mfix *barrier) |
d5b7b3ae RE |
8858 | { |
8859 | HOST_WIDE_INT offset = 0; | |
e32bac5b | 8860 | Mnode *mp; |
d5b7b3ae RE |
8861 | |
8862 | minipool_barrier = barrier; | |
8863 | ||
8864 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
8865 | { | |
8866 | mp->offset = offset; | |
f676971a | 8867 | |
d5b7b3ae RE |
8868 | if (mp->refcount > 0) |
8869 | offset += mp->fix_size; | |
8870 | } | |
8871 | } | |
8872 | ||
8873 | /* Output the literal table */ | |
8874 | static void | |
e32bac5b | 8875 | dump_minipool (rtx scan) |
d5b7b3ae | 8876 | { |
5a9335ef NC |
8877 | Mnode * mp; |
8878 | Mnode * nmp; | |
8879 | int align64 = 0; | |
8880 | ||
5848830f | 8881 | if (ARM_DOUBLEWORD_ALIGN) |
5a9335ef | 8882 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) |
88f77cba | 8883 | if (mp->refcount > 0 && mp->fix_size >= 8) |
5a9335ef NC |
8884 | { |
8885 | align64 = 1; | |
8886 | break; | |
8887 | } | |
d5b7b3ae | 8888 | |
c263766c RH |
8889 | if (dump_file) |
8890 | fprintf (dump_file, | |
5a9335ef NC |
8891 | ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", |
8892 | INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); | |
d5b7b3ae RE |
8893 | |
8894 | scan = emit_label_after (gen_label_rtx (), scan); | |
5a9335ef | 8895 | scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); |
d5b7b3ae RE |
8896 | scan = emit_label_after (minipool_vector_label, scan); |
8897 | ||
8898 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
8899 | { | |
8900 | if (mp->refcount > 0) | |
8901 | { | |
c263766c | 8902 | if (dump_file) |
d5b7b3ae | 8903 | { |
f676971a | 8904 | fprintf (dump_file, |
d5b7b3ae RE |
8905 | ";; Offset %u, min %ld, max %ld ", |
8906 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
8907 | (unsigned long) mp->max_address); | |
c263766c RH |
8908 | arm_print_value (dump_file, mp->value); |
8909 | fputc ('\n', dump_file); | |
d5b7b3ae RE |
8910 | } |
8911 | ||
8912 | switch (mp->fix_size) | |
8913 | { | |
8914 | #ifdef HAVE_consttable_1 | |
8915 | case 1: | |
8916 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
8917 | break; | |
8918 | ||
8919 | #endif | |
8920 | #ifdef HAVE_consttable_2 | |
8921 | case 2: | |
8922 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
8923 | break; | |
8924 | ||
8925 | #endif | |
8926 | #ifdef HAVE_consttable_4 | |
8927 | case 4: | |
8928 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
8929 | break; | |
8930 | ||
8931 | #endif | |
8932 | #ifdef HAVE_consttable_8 | |
8933 | case 8: | |
8934 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
8935 | break; | |
8936 | ||
88f77cba JB |
8937 | #endif |
8938 | #ifdef HAVE_consttable_16 | |
8939 | case 16: | |
8940 | scan = emit_insn_after (gen_consttable_16 (mp->value), scan); | |
8941 | break; | |
8942 | ||
d5b7b3ae RE |
8943 | #endif |
8944 | default: | |
e6d29d15 | 8945 | gcc_unreachable (); |
d5b7b3ae RE |
8946 | } |
8947 | } | |
8948 | ||
8949 | nmp = mp->next; | |
8950 | free (mp); | |
2b835d68 RE |
8951 | } |
8952 | ||
d5b7b3ae RE |
8953 | minipool_vector_head = minipool_vector_tail = NULL; |
8954 | scan = emit_insn_after (gen_consttable_end (), scan); | |
8955 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
8956 | } |
8957 | ||
d5b7b3ae RE |
8958 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
8959 | static int | |
e32bac5b | 8960 | arm_barrier_cost (rtx insn) |
949d79eb | 8961 | { |
d5b7b3ae RE |
8962 | /* Basing the location of the pool on the loop depth is preferable, |
8963 | but at the moment, the basic block information seems to be | |
8964 | corrupt by this stage of the compilation. */ | |
8965 | int base_cost = 50; | |
8966 | rtx next = next_nonnote_insn (insn); | |
8967 | ||
8968 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
8969 | base_cost -= 20; | |
8970 | ||
8971 | switch (GET_CODE (insn)) | |
8972 | { | |
8973 | case CODE_LABEL: | |
8974 | /* It will always be better to place the table before the label, rather | |
8975 | than after it. */ | |
f676971a | 8976 | return 50; |
949d79eb | 8977 | |
d5b7b3ae RE |
8978 | case INSN: |
8979 | case CALL_INSN: | |
8980 | return base_cost; | |
8981 | ||
8982 | case JUMP_INSN: | |
8983 | return base_cost - 10; | |
8984 | ||
8985 | default: | |
8986 | return base_cost + 10; | |
8987 | } | |
8988 | } | |
8989 | ||
8990 | /* Find the best place in the insn stream in the range | |
8991 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
8992 | Create the barrier by inserting a jump and add a new fix entry for | |
8993 | it. */ | |
8994 | static Mfix * | |
e32bac5b | 8995 | create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) |
d5b7b3ae RE |
8996 | { |
8997 | HOST_WIDE_INT count = 0; | |
8998 | rtx barrier; | |
8999 | rtx from = fix->insn; | |
7a7017bc PB |
9000 | /* The instruction after which we will insert the jump. */ |
9001 | rtx selected = NULL; | |
d5b7b3ae | 9002 | int selected_cost; |
7a7017bc | 9003 | /* The address at which the jump instruction will be placed. */ |
d5b7b3ae RE |
9004 | HOST_WIDE_INT selected_address; |
9005 | Mfix * new_fix; | |
9006 | HOST_WIDE_INT max_count = max_address - fix->address; | |
9007 | rtx label = gen_label_rtx (); | |
9008 | ||
9009 | selected_cost = arm_barrier_cost (from); | |
9010 | selected_address = fix->address; | |
9011 | ||
9012 | while (from && count < max_count) | |
9013 | { | |
9014 | rtx tmp; | |
9015 | int new_cost; | |
9016 | ||
9017 | /* This code shouldn't have been called if there was a natural barrier | |
9018 | within range. */ | |
e6d29d15 | 9019 | gcc_assert (GET_CODE (from) != BARRIER); |
d5b7b3ae RE |
9020 | |
9021 | /* Count the length of this insn. */ | |
9022 | count += get_attr_length (from); | |
9023 | ||
9024 | /* If there is a jump table, add its length. */ | |
9025 | tmp = is_jump_table (from); | |
9026 | if (tmp != NULL) | |
9027 | { | |
9028 | count += get_jump_table_size (tmp); | |
9029 | ||
9030 | /* Jump tables aren't in a basic block, so base the cost on | |
9031 | the dispatch insn. If we select this location, we will | |
9032 | still put the pool after the table. */ | |
9033 | new_cost = arm_barrier_cost (from); | |
9034 | ||
7a7017bc PB |
9035 | if (count < max_count |
9036 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
9037 | { |
9038 | selected = tmp; | |
9039 | selected_cost = new_cost; | |
9040 | selected_address = fix->address + count; | |
9041 | } | |
9042 | ||
9043 | /* Continue after the dispatch table. */ | |
9044 | from = NEXT_INSN (tmp); | |
9045 | continue; | |
9046 | } | |
9047 | ||
9048 | new_cost = arm_barrier_cost (from); | |
f676971a | 9049 | |
7a7017bc PB |
9050 | if (count < max_count |
9051 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
9052 | { |
9053 | selected = from; | |
9054 | selected_cost = new_cost; | |
9055 | selected_address = fix->address + count; | |
9056 | } | |
9057 | ||
9058 | from = NEXT_INSN (from); | |
9059 | } | |
9060 | ||
7a7017bc PB |
9061 | /* Make sure that we found a place to insert the jump. */ |
9062 | gcc_assert (selected); | |
9063 | ||
d5b7b3ae RE |
9064 | /* Create a new JUMP_INSN that branches around a barrier. */ |
9065 | from = emit_jump_insn_after (gen_jump (label), selected); | |
9066 | JUMP_LABEL (from) = label; | |
9067 | barrier = emit_barrier_after (from); | |
9068 | emit_label_after (label, barrier); | |
9069 | ||
9070 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 9071 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
9072 | new_fix->insn = barrier; |
9073 | new_fix->address = selected_address; | |
9074 | new_fix->next = fix->next; | |
9075 | fix->next = new_fix; | |
9076 | ||
9077 | return new_fix; | |
9078 | } | |
9079 | ||
9080 | /* Record that there is a natural barrier in the insn stream at | |
9081 | ADDRESS. */ | |
949d79eb | 9082 | static void |
e32bac5b | 9083 | push_minipool_barrier (rtx insn, HOST_WIDE_INT address) |
2b835d68 | 9084 | { |
c7319d87 | 9085 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 9086 | |
949d79eb RE |
9087 | fix->insn = insn; |
9088 | fix->address = address; | |
2b835d68 | 9089 | |
949d79eb RE |
9090 | fix->next = NULL; |
9091 | if (minipool_fix_head != NULL) | |
9092 | minipool_fix_tail->next = fix; | |
9093 | else | |
9094 | minipool_fix_head = fix; | |
9095 | ||
9096 | minipool_fix_tail = fix; | |
9097 | } | |
2b835d68 | 9098 | |
d5b7b3ae RE |
9099 | /* Record INSN, which will need fixing up to load a value from the |
9100 | minipool. ADDRESS is the offset of the insn since the start of the | |
9101 | function; LOC is a pointer to the part of the insn which requires | |
9102 | fixing; VALUE is the constant that must be loaded, which is of type | |
9103 | MODE. */ | |
949d79eb | 9104 | static void |
e32bac5b RE |
9105 | push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, |
9106 | enum machine_mode mode, rtx value) | |
949d79eb | 9107 | { |
c7319d87 | 9108 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb | 9109 | |
949d79eb RE |
9110 | fix->insn = insn; |
9111 | fix->address = address; | |
9112 | fix->loc = loc; | |
9113 | fix->mode = mode; | |
d5b7b3ae | 9114 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 9115 | fix->value = value; |
d5b7b3ae RE |
9116 | fix->forwards = get_attr_pool_range (insn); |
9117 | fix->backwards = get_attr_neg_pool_range (insn); | |
9118 | fix->minipool = NULL; | |
949d79eb RE |
9119 | |
9120 | /* If an insn doesn't have a range defined for it, then it isn't | |
e6d29d15 | 9121 | expecting to be reworked by this code. Better to stop now than |
949d79eb | 9122 | to generate duff assembly code. */ |
e6d29d15 | 9123 | gcc_assert (fix->forwards || fix->backwards); |
949d79eb | 9124 | |
34a9f549 PB |
9125 | /* If an entry requires 8-byte alignment then assume all constant pools |
9126 | require 4 bytes of padding. Trying to do this later on a per-pool | |
917f1b7e | 9127 | basis is awkward because existing pool entries have to be modified. */ |
88f77cba | 9128 | if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8) |
34a9f549 | 9129 | minipool_pad = 4; |
5a9335ef | 9130 | |
c263766c | 9131 | if (dump_file) |
d5b7b3ae | 9132 | { |
c263766c | 9133 | fprintf (dump_file, |
d5b7b3ae RE |
9134 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", |
9135 | GET_MODE_NAME (mode), | |
f676971a | 9136 | INSN_UID (insn), (unsigned long) address, |
d5b7b3ae | 9137 | -1 * (long)fix->backwards, (long)fix->forwards); |
c263766c RH |
9138 | arm_print_value (dump_file, fix->value); |
9139 | fprintf (dump_file, "\n"); | |
d5b7b3ae RE |
9140 | } |
9141 | ||
6354dc9b | 9142 | /* Add it to the chain of fixes. */ |
949d79eb | 9143 | fix->next = NULL; |
f676971a | 9144 | |
949d79eb RE |
9145 | if (minipool_fix_head != NULL) |
9146 | minipool_fix_tail->next = fix; | |
9147 | else | |
9148 | minipool_fix_head = fix; | |
9149 | ||
9150 | minipool_fix_tail = fix; | |
9151 | } | |
9152 | ||
9b901d50 | 9153 | /* Return the cost of synthesizing a 64-bit constant VAL inline. |
2075b05d RE |
9154 | Returns the number of insns needed, or 99 if we don't know how to |
9155 | do it. */ | |
9156 | int | |
9157 | arm_const_double_inline_cost (rtx val) | |
b9e8bfda | 9158 | { |
9b901d50 RE |
9159 | rtx lowpart, highpart; |
9160 | enum machine_mode mode; | |
e0b92319 | 9161 | |
9b901d50 | 9162 | mode = GET_MODE (val); |
b9e8bfda | 9163 | |
9b901d50 RE |
9164 | if (mode == VOIDmode) |
9165 | mode = DImode; | |
9166 | ||
9167 | gcc_assert (GET_MODE_SIZE (mode) == 8); | |
e0b92319 | 9168 | |
9b901d50 RE |
9169 | lowpart = gen_lowpart (SImode, val); |
9170 | highpart = gen_highpart_mode (SImode, mode, val); | |
e0b92319 | 9171 | |
9b901d50 RE |
9172 | gcc_assert (GET_CODE (lowpart) == CONST_INT); |
9173 | gcc_assert (GET_CODE (highpart) == CONST_INT); | |
9174 | ||
9175 | return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), | |
2075b05d | 9176 | NULL_RTX, NULL_RTX, 0, 0) |
9b901d50 | 9177 | + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart), |
2075b05d RE |
9178 | NULL_RTX, NULL_RTX, 0, 0)); |
9179 | } | |
9180 | ||
f3b569ca | 9181 | /* Return true if it is worthwhile to split a 64-bit constant into two |
b4a58f80 RE |
9182 | 32-bit operations. This is the case if optimizing for size, or |
9183 | if we have load delay slots, or if one 32-bit part can be done with | |
9184 | a single data operation. */ | |
9185 | bool | |
9186 | arm_const_double_by_parts (rtx val) | |
9187 | { | |
9188 | enum machine_mode mode = GET_MODE (val); | |
9189 | rtx part; | |
9190 | ||
9191 | if (optimize_size || arm_ld_sched) | |
9192 | return true; | |
9193 | ||
9194 | if (mode == VOIDmode) | |
9195 | mode = DImode; | |
e0b92319 | 9196 | |
b4a58f80 | 9197 | part = gen_highpart_mode (SImode, mode, val); |
e0b92319 | 9198 | |
b4a58f80 | 9199 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 9200 | |
b4a58f80 RE |
9201 | if (const_ok_for_arm (INTVAL (part)) |
9202 | || const_ok_for_arm (~INTVAL (part))) | |
9203 | return true; | |
e0b92319 | 9204 | |
b4a58f80 | 9205 | part = gen_lowpart (SImode, val); |
e0b92319 | 9206 | |
b4a58f80 | 9207 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 9208 | |
b4a58f80 RE |
9209 | if (const_ok_for_arm (INTVAL (part)) |
9210 | || const_ok_for_arm (~INTVAL (part))) | |
9211 | return true; | |
e0b92319 | 9212 | |
b4a58f80 RE |
9213 | return false; |
9214 | } | |
9215 | ||
f0375c66 NC |
9216 | /* Scan INSN and note any of its operands that need fixing. |
9217 | If DO_PUSHES is false we do not actually push any of the fixups | |
9b901d50 | 9218 | needed. The function returns TRUE if any fixups were needed/pushed. |
f0375c66 NC |
9219 | This is used by arm_memory_load_p() which needs to know about loads |
9220 | of constants that will be converted into minipool loads. */ | |
f0375c66 | 9221 | static bool |
e32bac5b | 9222 | note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) |
949d79eb | 9223 | { |
f0375c66 | 9224 | bool result = false; |
949d79eb RE |
9225 | int opno; |
9226 | ||
d5b7b3ae | 9227 | extract_insn (insn); |
949d79eb | 9228 | |
5895f793 | 9229 | if (!constrain_operands (1)) |
949d79eb RE |
9230 | fatal_insn_not_found (insn); |
9231 | ||
8c2a5582 RE |
9232 | if (recog_data.n_alternatives == 0) |
9233 | return false; | |
9234 | ||
9b901d50 RE |
9235 | /* Fill in recog_op_alt with information about the constraints of |
9236 | this insn. */ | |
949d79eb RE |
9237 | preprocess_constraints (); |
9238 | ||
1ccbefce | 9239 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 9240 | { |
6354dc9b | 9241 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 9242 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
9243 | continue; |
9244 | ||
9245 | /* If this alternative is a memory reference, then any mention | |
9246 | of constants in this alternative is really to fool reload | |
9247 | into allowing us to accept one there. We need to fix them up | |
9248 | now so that we output the right code. */ | |
9249 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
9250 | { | |
1ccbefce | 9251 | rtx op = recog_data.operand[opno]; |
949d79eb | 9252 | |
9b901d50 | 9253 | if (CONSTANT_P (op)) |
f0375c66 NC |
9254 | { |
9255 | if (do_pushes) | |
9256 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
9257 | recog_data.operand_mode[opno], op); | |
9258 | result = true; | |
9259 | } | |
d5b7b3ae | 9260 | else if (GET_CODE (op) == MEM |
949d79eb RE |
9261 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
9262 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
f0375c66 NC |
9263 | { |
9264 | if (do_pushes) | |
244b1afb RE |
9265 | { |
9266 | rtx cop = avoid_constant_pool_reference (op); | |
9267 | ||
9268 | /* Casting the address of something to a mode narrower | |
9269 | than a word can cause avoid_constant_pool_reference() | |
9270 | to return the pool reference itself. That's no good to | |
f676971a | 9271 | us here. Lets just hope that we can use the |
244b1afb RE |
9272 | constant pool value directly. */ |
9273 | if (op == cop) | |
c769a35d | 9274 | cop = get_pool_constant (XEXP (op, 0)); |
244b1afb RE |
9275 | |
9276 | push_minipool_fix (insn, address, | |
9277 | recog_data.operand_loc[opno], | |
c769a35d | 9278 | recog_data.operand_mode[opno], cop); |
244b1afb | 9279 | } |
f0375c66 NC |
9280 | |
9281 | result = true; | |
9282 | } | |
949d79eb | 9283 | } |
2b835d68 | 9284 | } |
f0375c66 NC |
9285 | |
9286 | return result; | |
2b835d68 RE |
9287 | } |
9288 | ||
18dbd950 RS |
9289 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
9290 | load addresses a limited distance around the pc. We do some | |
9291 | special munging to move the constant pool values to the correct | |
9292 | point in the code. */ | |
18dbd950 | 9293 | static void |
e32bac5b | 9294 | arm_reorg (void) |
2b835d68 RE |
9295 | { |
9296 | rtx insn; | |
d5b7b3ae RE |
9297 | HOST_WIDE_INT address = 0; |
9298 | Mfix * fix; | |
ad076f4e | 9299 | |
949d79eb | 9300 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 9301 | |
949d79eb RE |
9302 | /* The first insn must always be a note, or the code below won't |
9303 | scan it properly. */ | |
18dbd950 | 9304 | insn = get_insns (); |
e6d29d15 | 9305 | gcc_assert (GET_CODE (insn) == NOTE); |
34a9f549 | 9306 | minipool_pad = 0; |
949d79eb RE |
9307 | |
9308 | /* Scan all the insns and record the operands that will need fixing. */ | |
18dbd950 | 9309 | for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) |
2b835d68 | 9310 | { |
9b6b54e2 | 9311 | if (TARGET_CIRRUS_FIX_INVALID_INSNS |
f0375c66 | 9312 | && (arm_cirrus_insn_p (insn) |
9b6b54e2 | 9313 | || GET_CODE (insn) == JUMP_INSN |
f0375c66 | 9314 | || arm_memory_load_p (insn))) |
9b6b54e2 NC |
9315 | cirrus_reorg (insn); |
9316 | ||
949d79eb | 9317 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 9318 | push_minipool_barrier (insn, address); |
f0375c66 | 9319 | else if (INSN_P (insn)) |
949d79eb RE |
9320 | { |
9321 | rtx table; | |
9322 | ||
f0375c66 | 9323 | note_invalid_constants (insn, address, true); |
949d79eb | 9324 | address += get_attr_length (insn); |
d5b7b3ae | 9325 | |
949d79eb RE |
9326 | /* If the insn is a vector jump, add the size of the table |
9327 | and skip the table. */ | |
d5b7b3ae | 9328 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 9329 | { |
d5b7b3ae | 9330 | address += get_jump_table_size (table); |
949d79eb RE |
9331 | insn = table; |
9332 | } | |
9333 | } | |
9334 | } | |
332072db | 9335 | |
d5b7b3ae | 9336 | fix = minipool_fix_head; |
f676971a | 9337 | |
949d79eb | 9338 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 9339 | while (fix) |
949d79eb | 9340 | { |
d5b7b3ae RE |
9341 | Mfix * ftmp; |
9342 | Mfix * fdel; | |
9343 | Mfix * last_added_fix; | |
9344 | Mfix * last_barrier = NULL; | |
9345 | Mfix * this_fix; | |
949d79eb RE |
9346 | |
9347 | /* Skip any further barriers before the next fix. */ | |
9348 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
9349 | fix = fix->next; | |
9350 | ||
d5b7b3ae | 9351 | /* No more fixes. */ |
949d79eb RE |
9352 | if (fix == NULL) |
9353 | break; | |
332072db | 9354 | |
d5b7b3ae | 9355 | last_added_fix = NULL; |
2b835d68 | 9356 | |
d5b7b3ae | 9357 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 9358 | { |
949d79eb | 9359 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 9360 | { |
d5b7b3ae RE |
9361 | if (ftmp->address >= minipool_vector_head->max_address) |
9362 | break; | |
2b835d68 | 9363 | |
d5b7b3ae | 9364 | last_barrier = ftmp; |
2b835d68 | 9365 | } |
d5b7b3ae RE |
9366 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
9367 | break; | |
9368 | ||
9369 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 9370 | } |
949d79eb | 9371 | |
d5b7b3ae RE |
9372 | /* If we found a barrier, drop back to that; any fixes that we |
9373 | could have reached but come after the barrier will now go in | |
9374 | the next mini-pool. */ | |
949d79eb RE |
9375 | if (last_barrier != NULL) |
9376 | { | |
f676971a | 9377 | /* Reduce the refcount for those fixes that won't go into this |
d5b7b3ae RE |
9378 | pool after all. */ |
9379 | for (fdel = last_barrier->next; | |
9380 | fdel && fdel != ftmp; | |
9381 | fdel = fdel->next) | |
9382 | { | |
9383 | fdel->minipool->refcount--; | |
9384 | fdel->minipool = NULL; | |
9385 | } | |
9386 | ||
949d79eb RE |
9387 | ftmp = last_barrier; |
9388 | } | |
9389 | else | |
2bfa88dc | 9390 | { |
d5b7b3ae RE |
9391 | /* ftmp is first fix that we can't fit into this pool and |
9392 | there no natural barriers that we could use. Insert a | |
9393 | new barrier in the code somewhere between the previous | |
9394 | fix and this one, and arrange to jump around it. */ | |
9395 | HOST_WIDE_INT max_address; | |
9396 | ||
9397 | /* The last item on the list of fixes must be a barrier, so | |
9398 | we can never run off the end of the list of fixes without | |
9399 | last_barrier being set. */ | |
e6d29d15 | 9400 | gcc_assert (ftmp); |
d5b7b3ae RE |
9401 | |
9402 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
9403 | /* Check that there isn't another fix that is in range that |
9404 | we couldn't fit into this pool because the pool was | |
9405 | already too large: we need to put the pool before such an | |
7a7017bc PB |
9406 | instruction. The pool itself may come just after the |
9407 | fix because create_fix_barrier also allows space for a | |
9408 | jump instruction. */ | |
d5b7b3ae | 9409 | if (ftmp->address < max_address) |
7a7017bc | 9410 | max_address = ftmp->address + 1; |
d5b7b3ae RE |
9411 | |
9412 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
9413 | } | |
9414 | ||
9415 | assign_minipool_offsets (last_barrier); | |
9416 | ||
9417 | while (ftmp) | |
9418 | { | |
9419 | if (GET_CODE (ftmp->insn) != BARRIER | |
9420 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
9421 | == NULL)) | |
9422 | break; | |
2bfa88dc | 9423 | |
d5b7b3ae | 9424 | ftmp = ftmp->next; |
2bfa88dc | 9425 | } |
949d79eb RE |
9426 | |
9427 | /* Scan over the fixes we have identified for this pool, fixing them | |
9428 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 9429 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
9430 | this_fix = this_fix->next) |
9431 | if (GET_CODE (this_fix->insn) != BARRIER) | |
9432 | { | |
949d79eb | 9433 | rtx addr |
f676971a | 9434 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, |
949d79eb | 9435 | minipool_vector_label), |
d5b7b3ae | 9436 | this_fix->minipool->offset); |
949d79eb RE |
9437 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
9438 | } | |
9439 | ||
d5b7b3ae | 9440 | dump_minipool (last_barrier->insn); |
949d79eb | 9441 | fix = ftmp; |
2b835d68 | 9442 | } |
4b632bf1 | 9443 | |
949d79eb RE |
9444 | /* From now on we must synthesize any constants that we can't handle |
9445 | directly. This can happen if the RTL gets split during final | |
9446 | instruction generation. */ | |
4b632bf1 | 9447 | after_arm_reorg = 1; |
c7319d87 RE |
9448 | |
9449 | /* Free the minipool memory. */ | |
9450 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 9451 | } |
cce8749e CH |
9452 | \f |
9453 | /* Routines to output assembly language. */ | |
9454 | ||
f3bb6135 | 9455 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 9456 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 9457 | when cross compiling. */ |
cd2b33d0 | 9458 | const char * |
e32bac5b | 9459 | fp_immediate_constant (rtx x) |
ff9940b0 RE |
9460 | { |
9461 | REAL_VALUE_TYPE r; | |
9462 | int i; | |
f676971a | 9463 | |
9b66ebb1 PB |
9464 | if (!fp_consts_inited) |
9465 | init_fp_table (); | |
f676971a | 9466 | |
ff9940b0 RE |
9467 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
9468 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
9469 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
9470 | return strings_fp[i]; | |
f3bb6135 | 9471 | |
e6d29d15 | 9472 | gcc_unreachable (); |
ff9940b0 RE |
9473 | } |
9474 | ||
9997d19d | 9475 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
cd2b33d0 | 9476 | static const char * |
e32bac5b | 9477 | fp_const_from_val (REAL_VALUE_TYPE *r) |
9997d19d RE |
9478 | { |
9479 | int i; | |
9480 | ||
9b66ebb1 PB |
9481 | if (!fp_consts_inited) |
9482 | init_fp_table (); | |
9997d19d RE |
9483 | |
9484 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
9485 | if (REAL_VALUES_EQUAL (*r, values_fp[i])) |
9486 | return strings_fp[i]; | |
9997d19d | 9487 | |
e6d29d15 | 9488 | gcc_unreachable (); |
9997d19d | 9489 | } |
ff9940b0 | 9490 | |
cce8749e CH |
9491 | /* Output the operands of a LDM/STM instruction to STREAM. |
9492 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 | 9493 | REG is the base register, either the frame pointer or the stack pointer, |
a15908a4 PB |
9494 | INSTR is the possibly suffixed load or store instruction. |
9495 | RFE is nonzero if the instruction should also copy spsr to cpsr. */ | |
b279b20a | 9496 | |
d5b7b3ae | 9497 | static void |
b279b20a | 9498 | print_multi_reg (FILE *stream, const char *instr, unsigned reg, |
a15908a4 | 9499 | unsigned long mask, int rfe) |
cce8749e | 9500 | { |
b279b20a NC |
9501 | unsigned i; |
9502 | bool not_first = FALSE; | |
cce8749e | 9503 | |
a15908a4 | 9504 | gcc_assert (!rfe || (mask & (1 << PC_REGNUM))); |
1d5473cb | 9505 | fputc ('\t', stream); |
dd18ae56 | 9506 | asm_fprintf (stream, instr, reg); |
5b3e6663 | 9507 | fputc ('{', stream); |
f676971a | 9508 | |
d5b7b3ae | 9509 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
9510 | if (mask & (1 << i)) |
9511 | { | |
9512 | if (not_first) | |
9513 | fprintf (stream, ", "); | |
f676971a | 9514 | |
dd18ae56 | 9515 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
9516 | not_first = TRUE; |
9517 | } | |
f3bb6135 | 9518 | |
a15908a4 PB |
9519 | if (rfe) |
9520 | fprintf (stream, "}^\n"); | |
9521 | else | |
9522 | fprintf (stream, "}\n"); | |
f3bb6135 | 9523 | } |
cce8749e | 9524 | |
9b66ebb1 | 9525 | |
8edfc4cc | 9526 | /* Output a FLDMD instruction to STREAM. |
9728c9d1 PB |
9527 | BASE if the register containing the address. |
9528 | REG and COUNT specify the register range. | |
8edfc4cc MS |
9529 | Extra registers may be added to avoid hardware bugs. |
9530 | ||
9531 | We output FLDMD even for ARMv5 VFP implementations. Although | |
9532 | FLDMD is technically not supported until ARMv6, it is believed | |
9533 | that all VFP implementations support its use in this context. */ | |
9b66ebb1 PB |
9534 | |
9535 | static void | |
8edfc4cc | 9536 | vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count) |
9b66ebb1 PB |
9537 | { |
9538 | int i; | |
9539 | ||
9728c9d1 PB |
9540 | /* Workaround ARM10 VFPr1 bug. */ |
9541 | if (count == 2 && !arm_arch6) | |
9542 | { | |
9543 | if (reg == 15) | |
9544 | reg--; | |
9545 | count++; | |
9546 | } | |
9547 | ||
f1adb0a9 JB |
9548 | /* FLDMD may not load more than 16 doubleword registers at a time. Split the |
9549 | load into multiple parts if we have to handle more than 16 registers. */ | |
9550 | if (count > 16) | |
9551 | { | |
9552 | vfp_output_fldmd (stream, base, reg, 16); | |
9553 | vfp_output_fldmd (stream, base, reg + 16, count - 16); | |
9554 | return; | |
9555 | } | |
9556 | ||
9b66ebb1 | 9557 | fputc ('\t', stream); |
8edfc4cc | 9558 | asm_fprintf (stream, "fldmfdd\t%r!, {", base); |
9b66ebb1 | 9559 | |
9728c9d1 | 9560 | for (i = reg; i < reg + count; i++) |
9b66ebb1 | 9561 | { |
9728c9d1 | 9562 | if (i > reg) |
9b66ebb1 | 9563 | fputs (", ", stream); |
9728c9d1 | 9564 | asm_fprintf (stream, "d%d", i); |
9b66ebb1 PB |
9565 | } |
9566 | fputs ("}\n", stream); | |
9728c9d1 | 9567 | |
9b66ebb1 PB |
9568 | } |
9569 | ||
9570 | ||
9571 | /* Output the assembly for a store multiple. */ | |
9572 | ||
9573 | const char * | |
8edfc4cc | 9574 | vfp_output_fstmd (rtx * operands) |
9b66ebb1 PB |
9575 | { |
9576 | char pattern[100]; | |
9577 | int p; | |
9578 | int base; | |
9579 | int i; | |
9580 | ||
8edfc4cc | 9581 | strcpy (pattern, "fstmfdd\t%m0!, {%P1"); |
9b66ebb1 PB |
9582 | p = strlen (pattern); |
9583 | ||
e6d29d15 | 9584 | gcc_assert (GET_CODE (operands[1]) == REG); |
9b66ebb1 PB |
9585 | |
9586 | base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; | |
9587 | for (i = 1; i < XVECLEN (operands[2], 0); i++) | |
9588 | { | |
9589 | p += sprintf (&pattern[p], ", d%d", base + i); | |
9590 | } | |
9591 | strcpy (&pattern[p], "}"); | |
9592 | ||
9593 | output_asm_insn (pattern, operands); | |
9594 | return ""; | |
9595 | } | |
9596 | ||
9597 | ||
9728c9d1 PB |
9598 | /* Emit RTL to save block of VFP register pairs to the stack. Returns the |
9599 | number of bytes pushed. */ | |
9b66ebb1 | 9600 | |
9728c9d1 | 9601 | static int |
8edfc4cc | 9602 | vfp_emit_fstmd (int base_reg, int count) |
9b66ebb1 PB |
9603 | { |
9604 | rtx par; | |
9605 | rtx dwarf; | |
9606 | rtx tmp, reg; | |
9607 | int i; | |
9608 | ||
9728c9d1 PB |
9609 | /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two |
9610 | register pairs are stored by a store multiple insn. We avoid this | |
9611 | by pushing an extra pair. */ | |
9612 | if (count == 2 && !arm_arch6) | |
9613 | { | |
9614 | if (base_reg == LAST_VFP_REGNUM - 3) | |
9615 | base_reg -= 2; | |
9616 | count++; | |
9617 | } | |
9618 | ||
f1adb0a9 JB |
9619 | /* FSTMD may not store more than 16 doubleword registers at once. Split |
9620 | larger stores into multiple parts (up to a maximum of two, in | |
9621 | practice). */ | |
9622 | if (count > 16) | |
9623 | { | |
9624 | int saved; | |
9625 | /* NOTE: base_reg is an internal register number, so each D register | |
9626 | counts as 2. */ | |
9627 | saved = vfp_emit_fstmd (base_reg + 32, count - 16); | |
9628 | saved += vfp_emit_fstmd (base_reg, 16); | |
9629 | return saved; | |
9630 | } | |
9631 | ||
9b66ebb1 PB |
9632 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
9633 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); | |
9634 | ||
9635 | reg = gen_rtx_REG (DFmode, base_reg); | |
9636 | base_reg += 2; | |
9637 | ||
9638 | XVECEXP (par, 0, 0) | |
9639 | = gen_rtx_SET (VOIDmode, | |
31fa16b6 RE |
9640 | gen_frame_mem (BLKmode, |
9641 | gen_rtx_PRE_DEC (BLKmode, | |
9642 | stack_pointer_rtx)), | |
9b66ebb1 PB |
9643 | gen_rtx_UNSPEC (BLKmode, |
9644 | gen_rtvec (1, reg), | |
9645 | UNSPEC_PUSH_MULT)); | |
9646 | ||
9647 | tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
8edfc4cc | 9648 | plus_constant (stack_pointer_rtx, -(count * 8))); |
9b66ebb1 PB |
9649 | RTX_FRAME_RELATED_P (tmp) = 1; |
9650 | XVECEXP (dwarf, 0, 0) = tmp; | |
9651 | ||
9652 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 9653 | gen_frame_mem (DFmode, stack_pointer_rtx), |
9b66ebb1 PB |
9654 | reg); |
9655 | RTX_FRAME_RELATED_P (tmp) = 1; | |
9656 | XVECEXP (dwarf, 0, 1) = tmp; | |
9657 | ||
9658 | for (i = 1; i < count; i++) | |
9659 | { | |
9660 | reg = gen_rtx_REG (DFmode, base_reg); | |
9661 | base_reg += 2; | |
9662 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
9663 | ||
9664 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 9665 | gen_frame_mem (DFmode, |
d66437c5 RE |
9666 | plus_constant (stack_pointer_rtx, |
9667 | i * 8)), | |
9b66ebb1 PB |
9668 | reg); |
9669 | RTX_FRAME_RELATED_P (tmp) = 1; | |
9670 | XVECEXP (dwarf, 0, i + 1) = tmp; | |
9671 | } | |
9672 | ||
9673 | par = emit_insn (par); | |
9674 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
9675 | REG_NOTES (par)); | |
9728c9d1 PB |
9676 | RTX_FRAME_RELATED_P (par) = 1; |
9677 | ||
8edfc4cc | 9678 | return count * 8; |
9b66ebb1 PB |
9679 | } |
9680 | ||
9403b7f7 RS |
9681 | /* Emit a call instruction with pattern PAT. ADDR is the address of |
9682 | the call target. */ | |
9683 | ||
9684 | void | |
9685 | arm_emit_call_insn (rtx pat, rtx addr) | |
9686 | { | |
9687 | rtx insn; | |
9688 | ||
9689 | insn = emit_call_insn (pat); | |
9690 | ||
9691 | /* The PIC register is live on entry to VxWorks PIC PLT entries. | |
9692 | If the call might use such an entry, add a use of the PIC register | |
9693 | to the instruction's CALL_INSN_FUNCTION_USAGE. */ | |
9694 | if (TARGET_VXWORKS_RTP | |
9695 | && flag_pic | |
9696 | && GET_CODE (addr) == SYMBOL_REF | |
9697 | && (SYMBOL_REF_DECL (addr) | |
9698 | ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr)) | |
9699 | : !SYMBOL_REF_LOCAL_P (addr))) | |
9700 | { | |
9701 | require_pic_register (); | |
9702 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg); | |
9703 | } | |
9704 | } | |
9b66ebb1 | 9705 | |
6354dc9b | 9706 | /* Output a 'call' insn. */ |
cd2b33d0 | 9707 | const char * |
e32bac5b | 9708 | output_call (rtx *operands) |
cce8749e | 9709 | { |
e6d29d15 | 9710 | gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */ |
cce8749e | 9711 | |
68d560d4 | 9712 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
62b10bbc | 9713 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 9714 | { |
62b10bbc | 9715 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 9716 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 9717 | } |
f676971a | 9718 | |
1d5473cb | 9719 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
f676971a | 9720 | |
68d560d4 | 9721 | if (TARGET_INTERWORK || arm_arch4t) |
da6558fd NC |
9722 | output_asm_insn ("bx%?\t%0", operands); |
9723 | else | |
9724 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
f676971a | 9725 | |
f3bb6135 RE |
9726 | return ""; |
9727 | } | |
cce8749e | 9728 | |
6354dc9b | 9729 | /* Output a 'call' insn that is a reference in memory. */ |
cd2b33d0 | 9730 | const char * |
e32bac5b | 9731 | output_call_mem (rtx *operands) |
ff9940b0 | 9732 | { |
68d560d4 | 9733 | if (TARGET_INTERWORK && !arm_arch5) |
da6558fd NC |
9734 | { |
9735 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
9736 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
9737 | output_asm_insn ("bx%?\t%|ip", operands); | |
9738 | } | |
6ab5da80 RE |
9739 | else if (regno_use_in (LR_REGNUM, operands[0])) |
9740 | { | |
9741 | /* LR is used in the memory address. We load the address in the | |
9742 | first instruction. It's safe to use IP as the target of the | |
9743 | load since the call will kill it anyway. */ | |
9744 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
68d560d4 | 9745 | if (arm_arch5) |
07ec3810 | 9746 | output_asm_insn ("blx%?\t%|ip", operands); |
68d560d4 RE |
9747 | else |
9748 | { | |
9749 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
9750 | if (arm_arch4t) | |
9751 | output_asm_insn ("bx%?\t%|ip", operands); | |
9752 | else | |
9753 | output_asm_insn ("mov%?\t%|pc, %|ip", operands); | |
9754 | } | |
6ab5da80 | 9755 | } |
da6558fd NC |
9756 | else |
9757 | { | |
9758 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
9759 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
9760 | } | |
9761 | ||
f3bb6135 RE |
9762 | return ""; |
9763 | } | |
ff9940b0 RE |
9764 | |
9765 | ||
3b684012 RE |
9766 | /* Output a move from arm registers to an fpa registers. |
9767 | OPERANDS[0] is an fpa register. | |
ff9940b0 | 9768 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 9769 | const char * |
e32bac5b | 9770 | output_mov_long_double_fpa_from_arm (rtx *operands) |
ff9940b0 RE |
9771 | { |
9772 | int arm_reg0 = REGNO (operands[1]); | |
9773 | rtx ops[3]; | |
9774 | ||
e6d29d15 | 9775 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 9776 | |
43cffd11 RE |
9777 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
9778 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
9779 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
f676971a | 9780 | |
5b3e6663 | 9781 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
1d5473cb | 9782 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); |
f676971a | 9783 | |
f3bb6135 RE |
9784 | return ""; |
9785 | } | |
ff9940b0 | 9786 | |
3b684012 | 9787 | /* Output a move from an fpa register to arm registers. |
ff9940b0 | 9788 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 9789 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 9790 | const char * |
e32bac5b | 9791 | output_mov_long_double_arm_from_fpa (rtx *operands) |
ff9940b0 RE |
9792 | { |
9793 | int arm_reg0 = REGNO (operands[0]); | |
9794 | rtx ops[3]; | |
9795 | ||
e6d29d15 | 9796 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 9797 | |
43cffd11 RE |
9798 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
9799 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
9800 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 9801 | |
1d5473cb | 9802 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
5b3e6663 | 9803 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
f3bb6135 RE |
9804 | return ""; |
9805 | } | |
ff9940b0 RE |
9806 | |
9807 | /* Output a move from arm registers to arm registers of a long double | |
9808 | OPERANDS[0] is the destination. | |
9809 | OPERANDS[1] is the source. */ | |
cd2b33d0 | 9810 | const char * |
e32bac5b | 9811 | output_mov_long_double_arm_from_arm (rtx *operands) |
ff9940b0 | 9812 | { |
6354dc9b | 9813 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
9814 | int dest_start = REGNO (operands[0]); |
9815 | int src_start = REGNO (operands[1]); | |
9816 | rtx ops[2]; | |
9817 | int i; | |
9818 | ||
9819 | if (dest_start < src_start) | |
9820 | { | |
9821 | for (i = 0; i < 3; i++) | |
9822 | { | |
43cffd11 RE |
9823 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
9824 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 9825 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
9826 | } |
9827 | } | |
9828 | else | |
9829 | { | |
9830 | for (i = 2; i >= 0; i--) | |
9831 | { | |
43cffd11 RE |
9832 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
9833 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 9834 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
9835 | } |
9836 | } | |
f3bb6135 | 9837 | |
ff9940b0 RE |
9838 | return ""; |
9839 | } | |
9840 | ||
9841 | ||
3b684012 RE |
9842 | /* Output a move from arm registers to an fpa registers. |
9843 | OPERANDS[0] is an fpa register. | |
cce8749e | 9844 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 9845 | const char * |
e32bac5b | 9846 | output_mov_double_fpa_from_arm (rtx *operands) |
cce8749e CH |
9847 | { |
9848 | int arm_reg0 = REGNO (operands[1]); | |
9849 | rtx ops[2]; | |
9850 | ||
e6d29d15 | 9851 | gcc_assert (arm_reg0 != IP_REGNUM); |
f676971a | 9852 | |
43cffd11 RE |
9853 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
9854 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
5b3e6663 | 9855 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops); |
1d5473cb | 9856 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); |
f3bb6135 RE |
9857 | return ""; |
9858 | } | |
cce8749e | 9859 | |
3b684012 | 9860 | /* Output a move from an fpa register to arm registers. |
cce8749e | 9861 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 9862 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 9863 | const char * |
e32bac5b | 9864 | output_mov_double_arm_from_fpa (rtx *operands) |
cce8749e CH |
9865 | { |
9866 | int arm_reg0 = REGNO (operands[0]); | |
9867 | rtx ops[2]; | |
9868 | ||
e6d29d15 | 9869 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 9870 | |
43cffd11 RE |
9871 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
9872 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb | 9873 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
5b3e6663 | 9874 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops); |
f3bb6135 RE |
9875 | return ""; |
9876 | } | |
cce8749e CH |
9877 | |
9878 | /* Output a move between double words. | |
9879 | It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM | |
9880 | or MEM<-REG and all MEMs must be offsettable addresses. */ | |
cd2b33d0 | 9881 | const char * |
e32bac5b | 9882 | output_move_double (rtx *operands) |
cce8749e CH |
9883 | { |
9884 | enum rtx_code code0 = GET_CODE (operands[0]); | |
9885 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 9886 | rtx otherops[3]; |
cce8749e CH |
9887 | |
9888 | if (code0 == REG) | |
9889 | { | |
9890 | int reg0 = REGNO (operands[0]); | |
9891 | ||
43cffd11 | 9892 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
f676971a | 9893 | |
e6d29d15 NS |
9894 | gcc_assert (code1 == MEM); /* Constraints should ensure this. */ |
9895 | ||
9896 | switch (GET_CODE (XEXP (operands[1], 0))) | |
cce8749e | 9897 | { |
e6d29d15 | 9898 | case REG: |
5dea0c19 PB |
9899 | if (TARGET_LDRD) |
9900 | output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands); | |
9901 | else | |
9902 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
e6d29d15 | 9903 | break; |
e0b92319 | 9904 | |
e6d29d15 NS |
9905 | case PRE_INC: |
9906 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 9907 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands); |
e6d29d15 | 9908 | break; |
e0b92319 | 9909 | |
e6d29d15 | 9910 | case PRE_DEC: |
5b3e6663 PB |
9911 | if (TARGET_LDRD) |
9912 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands); | |
9913 | else | |
9914 | output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands); | |
e6d29d15 | 9915 | break; |
e0b92319 | 9916 | |
e6d29d15 | 9917 | case POST_INC: |
5dea0c19 PB |
9918 | if (TARGET_LDRD) |
9919 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands); | |
9920 | else | |
9921 | output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands); | |
e6d29d15 | 9922 | break; |
e0b92319 | 9923 | |
e6d29d15 NS |
9924 | case POST_DEC: |
9925 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 9926 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands); |
e6d29d15 | 9927 | break; |
e0b92319 | 9928 | |
e6d29d15 NS |
9929 | case PRE_MODIFY: |
9930 | case POST_MODIFY: | |
9931 | otherops[0] = operands[0]; | |
9932 | otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0); | |
9933 | otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1); | |
e0b92319 | 9934 | |
e6d29d15 | 9935 | if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY) |
cce8749e | 9936 | { |
e6d29d15 | 9937 | if (reg_overlap_mentioned_p (otherops[0], otherops[2])) |
fdd695fd | 9938 | { |
e6d29d15 NS |
9939 | /* Registers overlap so split out the increment. */ |
9940 | output_asm_insn ("add%?\t%1, %1, %2", otherops); | |
5b3e6663 | 9941 | output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops); |
fdd695fd PB |
9942 | } |
9943 | else | |
fe2d934b PB |
9944 | { |
9945 | /* IWMMXT allows offsets larger than ldrd can handle, | |
9946 | fix these up with a pair of ldr. */ | |
9947 | if (GET_CODE (otherops[2]) == CONST_INT | |
9948 | && (INTVAL(otherops[2]) <= -256 | |
9949 | || INTVAL(otherops[2]) >= 256)) | |
9950 | { | |
9951 | output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | |
9952 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); | |
9953 | output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); | |
9954 | } | |
9955 | else | |
9956 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops); | |
9957 | } | |
e6d29d15 NS |
9958 | } |
9959 | else | |
9960 | { | |
fe2d934b PB |
9961 | /* IWMMXT allows offsets larger than ldrd can handle, |
9962 | fix these up with a pair of ldr. */ | |
9963 | if (GET_CODE (otherops[2]) == CONST_INT | |
9964 | && (INTVAL(otherops[2]) <= -256 | |
9965 | || INTVAL(otherops[2]) >= 256)) | |
9966 | { | |
9967 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); | |
9968 | output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); | |
9969 | otherops[0] = operands[0]; | |
9970 | output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); | |
9971 | } | |
9972 | else | |
9973 | /* We only allow constant increments, so this is safe. */ | |
9974 | output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops); | |
e6d29d15 NS |
9975 | } |
9976 | break; | |
e0b92319 | 9977 | |
e6d29d15 NS |
9978 | case LABEL_REF: |
9979 | case CONST: | |
5dea0c19 PB |
9980 | /* We might be able to use ldrd %0, %1 here. However the range is |
9981 | different to ldr/adr, and it is broken on some ARMv7-M | |
9982 | implementations. */ | |
e6d29d15 | 9983 | output_asm_insn ("adr%?\t%0, %1", operands); |
5dea0c19 PB |
9984 | if (TARGET_LDRD) |
9985 | output_asm_insn ("ldr%(d%)\t%0, [%0]", operands); | |
9986 | else | |
9987 | output_asm_insn ("ldm%(ia%)\t%0, %M0", operands); | |
e6d29d15 | 9988 | break; |
e0b92319 | 9989 | |
5b3e6663 | 9990 | /* ??? This needs checking for thumb2. */ |
e6d29d15 NS |
9991 | default: |
9992 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), | |
9993 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
9994 | { | |
9995 | otherops[0] = operands[0]; | |
9996 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
9997 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
e0b92319 | 9998 | |
e6d29d15 | 9999 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) |
fdd695fd | 10000 | { |
5dea0c19 | 10001 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 10002 | { |
e6d29d15 | 10003 | switch ((int) INTVAL (otherops[2])) |
2b835d68 | 10004 | { |
e6d29d15 | 10005 | case -8: |
5b3e6663 | 10006 | output_asm_insn ("ldm%(db%)\t%1, %M0", otherops); |
e6d29d15 NS |
10007 | return ""; |
10008 | case -4: | |
5b3e6663 PB |
10009 | if (TARGET_THUMB2) |
10010 | break; | |
10011 | output_asm_insn ("ldm%(da%)\t%1, %M0", otherops); | |
e6d29d15 NS |
10012 | return ""; |
10013 | case 4: | |
5b3e6663 PB |
10014 | if (TARGET_THUMB2) |
10015 | break; | |
10016 | output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops); | |
e6d29d15 | 10017 | return ""; |
fdd695fd | 10018 | } |
e6d29d15 NS |
10019 | } |
10020 | if (TARGET_LDRD | |
10021 | && (GET_CODE (otherops[2]) == REG | |
10022 | || (GET_CODE (otherops[2]) == CONST_INT | |
10023 | && INTVAL (otherops[2]) > -256 | |
10024 | && INTVAL (otherops[2]) < 256))) | |
10025 | { | |
10026 | if (reg_overlap_mentioned_p (otherops[0], | |
10027 | otherops[2])) | |
fdd695fd | 10028 | { |
e6d29d15 NS |
10029 | /* Swap base and index registers over to |
10030 | avoid a conflict. */ | |
10031 | otherops[1] = XEXP (XEXP (operands[1], 0), 1); | |
10032 | otherops[2] = XEXP (XEXP (operands[1], 0), 0); | |
fdd695fd | 10033 | } |
e6d29d15 NS |
10034 | /* If both registers conflict, it will usually |
10035 | have been fixed by a splitter. */ | |
10036 | if (reg_overlap_mentioned_p (otherops[0], otherops[2])) | |
fdd695fd | 10037 | { |
e6d29d15 | 10038 | output_asm_insn ("add%?\t%1, %1, %2", otherops); |
5b3e6663 | 10039 | output_asm_insn ("ldr%(d%)\t%0, [%1]", |
e6d29d15 | 10040 | otherops); |
2b835d68 RE |
10041 | } |
10042 | else | |
5b3e6663 | 10043 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops); |
e6d29d15 | 10044 | return ""; |
2b835d68 | 10045 | } |
e0b92319 | 10046 | |
e6d29d15 | 10047 | if (GET_CODE (otherops[2]) == CONST_INT) |
2b835d68 | 10048 | { |
e6d29d15 NS |
10049 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) |
10050 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
10051 | else | |
10052 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
2b835d68 RE |
10053 | } |
10054 | else | |
e6d29d15 NS |
10055 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
10056 | } | |
10057 | else | |
10058 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
10059 | ||
5dea0c19 PB |
10060 | if (TARGET_LDRD) |
10061 | return "ldr%(d%)\t%0, [%0]"; | |
10062 | ||
5b3e6663 | 10063 | return "ldm%(ia%)\t%0, %M0"; |
e6d29d15 NS |
10064 | } |
10065 | else | |
10066 | { | |
10067 | otherops[1] = adjust_address (operands[1], SImode, 4); | |
10068 | /* Take care of overlapping base/data reg. */ | |
10069 | if (reg_mentioned_p (operands[0], operands[1])) | |
10070 | { | |
10071 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
10072 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
10073 | } | |
10074 | else | |
10075 | { | |
10076 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
10077 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
cce8749e CH |
10078 | } |
10079 | } | |
10080 | } | |
cce8749e | 10081 | } |
e6d29d15 | 10082 | else |
cce8749e | 10083 | { |
e6d29d15 NS |
10084 | /* Constraints should ensure this. */ |
10085 | gcc_assert (code0 == MEM && code1 == REG); | |
10086 | gcc_assert (REGNO (operands[1]) != IP_REGNUM); | |
2b835d68 | 10087 | |
ff9940b0 RE |
10088 | switch (GET_CODE (XEXP (operands[0], 0))) |
10089 | { | |
10090 | case REG: | |
5dea0c19 PB |
10091 | if (TARGET_LDRD) |
10092 | output_asm_insn ("str%(d%)\t%1, [%m0]", operands); | |
10093 | else | |
10094 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
ff9940b0 | 10095 | break; |
2b835d68 | 10096 | |
ff9940b0 | 10097 | case PRE_INC: |
e6d29d15 | 10098 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 10099 | output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands); |
ff9940b0 | 10100 | break; |
2b835d68 | 10101 | |
ff9940b0 | 10102 | case PRE_DEC: |
5b3e6663 PB |
10103 | if (TARGET_LDRD) |
10104 | output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands); | |
10105 | else | |
10106 | output_asm_insn ("stm%(db%)\t%m0!, %M1", operands); | |
ff9940b0 | 10107 | break; |
2b835d68 | 10108 | |
ff9940b0 | 10109 | case POST_INC: |
5dea0c19 PB |
10110 | if (TARGET_LDRD) |
10111 | output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands); | |
10112 | else | |
10113 | output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands); | |
ff9940b0 | 10114 | break; |
2b835d68 | 10115 | |
ff9940b0 | 10116 | case POST_DEC: |
e6d29d15 | 10117 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 10118 | output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands); |
fdd695fd PB |
10119 | break; |
10120 | ||
10121 | case PRE_MODIFY: | |
10122 | case POST_MODIFY: | |
10123 | otherops[0] = operands[1]; | |
10124 | otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); | |
10125 | otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); | |
10126 | ||
fe2d934b PB |
10127 | /* IWMMXT allows offsets larger than ldrd can handle, |
10128 | fix these up with a pair of ldr. */ | |
10129 | if (GET_CODE (otherops[2]) == CONST_INT | |
10130 | && (INTVAL(otherops[2]) <= -256 | |
10131 | || INTVAL(otherops[2]) >= 256)) | |
10132 | { | |
10133 | rtx reg1; | |
10134 | reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); | |
10135 | if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | |
10136 | { | |
10137 | output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | |
10138 | otherops[0] = reg1; | |
10139 | output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); | |
10140 | } | |
10141 | else | |
10142 | { | |
10143 | otherops[0] = reg1; | |
10144 | output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); | |
10145 | otherops[0] = operands[1]; | |
10146 | output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); | |
10147 | } | |
10148 | } | |
10149 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | |
5b3e6663 | 10150 | output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops); |
fdd695fd | 10151 | else |
5b3e6663 | 10152 | output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops); |
ff9940b0 | 10153 | break; |
2b835d68 RE |
10154 | |
10155 | case PLUS: | |
fdd695fd | 10156 | otherops[2] = XEXP (XEXP (operands[0], 0), 1); |
5dea0c19 | 10157 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 10158 | { |
06bea5aa | 10159 | switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) |
2b835d68 RE |
10160 | { |
10161 | case -8: | |
5b3e6663 | 10162 | output_asm_insn ("stm%(db%)\t%m0, %M1", operands); |
2b835d68 RE |
10163 | return ""; |
10164 | ||
10165 | case -4: | |
5b3e6663 PB |
10166 | if (TARGET_THUMB2) |
10167 | break; | |
10168 | output_asm_insn ("stm%(da%)\t%m0, %M1", operands); | |
2b835d68 RE |
10169 | return ""; |
10170 | ||
10171 | case 4: | |
5b3e6663 PB |
10172 | if (TARGET_THUMB2) |
10173 | break; | |
10174 | output_asm_insn ("stm%(ib%)\t%m0, %M1", operands); | |
2b835d68 RE |
10175 | return ""; |
10176 | } | |
10177 | } | |
fdd695fd PB |
10178 | if (TARGET_LDRD |
10179 | && (GET_CODE (otherops[2]) == REG | |
10180 | || (GET_CODE (otherops[2]) == CONST_INT | |
10181 | && INTVAL (otherops[2]) > -256 | |
10182 | && INTVAL (otherops[2]) < 256))) | |
10183 | { | |
10184 | otherops[0] = operands[1]; | |
10185 | otherops[1] = XEXP (XEXP (operands[0], 0), 0); | |
5b3e6663 | 10186 | output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops); |
fdd695fd PB |
10187 | return ""; |
10188 | } | |
2b835d68 RE |
10189 | /* Fall through */ |
10190 | ||
ff9940b0 | 10191 | default: |
a4a37b30 | 10192 | otherops[0] = adjust_address (operands[0], SImode, 4); |
43cffd11 | 10193 | otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); |
9997d19d RE |
10194 | output_asm_insn ("str%?\t%1, %0", operands); |
10195 | output_asm_insn ("str%?\t%1, %0", otherops); | |
cce8749e CH |
10196 | } |
10197 | } | |
cce8749e | 10198 | |
9997d19d RE |
10199 | return ""; |
10200 | } | |
cce8749e | 10201 | |
88f77cba JB |
10202 | /* Output a move, load or store for quad-word vectors in ARM registers. Only |
10203 | handles MEMs accepted by neon_vector_mem_operand with CORE=true. */ | |
5b3e6663 PB |
10204 | |
10205 | const char * | |
88f77cba | 10206 | output_move_quad (rtx *operands) |
5b3e6663 | 10207 | { |
88f77cba JB |
10208 | if (REG_P (operands[0])) |
10209 | { | |
10210 | /* Load, or reg->reg move. */ | |
5b3e6663 | 10211 | |
88f77cba JB |
10212 | if (MEM_P (operands[1])) |
10213 | { | |
10214 | switch (GET_CODE (XEXP (operands[1], 0))) | |
10215 | { | |
10216 | case REG: | |
10217 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
10218 | break; | |
10219 | ||
10220 | case LABEL_REF: | |
10221 | case CONST: | |
10222 | output_asm_insn ("adr%?\t%0, %1", operands); | |
10223 | output_asm_insn ("ldm%(ia%)\t%0, %M0", operands); | |
10224 | break; | |
10225 | ||
10226 | default: | |
10227 | gcc_unreachable (); | |
10228 | } | |
10229 | } | |
10230 | else | |
10231 | { | |
10232 | rtx ops[2]; | |
10233 | int dest, src, i; | |
5b3e6663 | 10234 | |
88f77cba | 10235 | gcc_assert (REG_P (operands[1])); |
5b3e6663 | 10236 | |
88f77cba JB |
10237 | dest = REGNO (operands[0]); |
10238 | src = REGNO (operands[1]); | |
5b3e6663 | 10239 | |
88f77cba JB |
10240 | /* This seems pretty dumb, but hopefully GCC won't try to do it |
10241 | very often. */ | |
10242 | if (dest < src) | |
10243 | for (i = 0; i < 4; i++) | |
10244 | { | |
10245 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
10246 | ops[1] = gen_rtx_REG (SImode, src + i); | |
10247 | output_asm_insn ("mov%?\t%0, %1", ops); | |
10248 | } | |
10249 | else | |
10250 | for (i = 3; i >= 0; i--) | |
10251 | { | |
10252 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
10253 | ops[1] = gen_rtx_REG (SImode, src + i); | |
10254 | output_asm_insn ("mov%?\t%0, %1", ops); | |
10255 | } | |
10256 | } | |
10257 | } | |
10258 | else | |
10259 | { | |
10260 | gcc_assert (MEM_P (operands[0])); | |
10261 | gcc_assert (REG_P (operands[1])); | |
10262 | gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0])); | |
10263 | ||
10264 | switch (GET_CODE (XEXP (operands[0], 0))) | |
10265 | { | |
10266 | case REG: | |
10267 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
10268 | break; | |
10269 | ||
10270 | default: | |
10271 | gcc_unreachable (); | |
10272 | } | |
10273 | } | |
10274 | ||
10275 | return ""; | |
10276 | } | |
10277 | ||
10278 | /* Output a VFP load or store instruction. */ | |
10279 | ||
10280 | const char * | |
10281 | output_move_vfp (rtx *operands) | |
10282 | { | |
10283 | rtx reg, mem, addr, ops[2]; | |
10284 | int load = REG_P (operands[0]); | |
10285 | int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8; | |
10286 | int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT; | |
10287 | const char *template; | |
10288 | char buff[50]; | |
10289 | enum machine_mode mode; | |
10290 | ||
10291 | reg = operands[!load]; | |
10292 | mem = operands[load]; | |
10293 | ||
10294 | mode = GET_MODE (reg); | |
10295 | ||
10296 | gcc_assert (REG_P (reg)); | |
10297 | gcc_assert (IS_VFP_REGNUM (REGNO (reg))); | |
10298 | gcc_assert (mode == SFmode | |
10299 | || mode == DFmode | |
10300 | || mode == SImode | |
10301 | || mode == DImode | |
10302 | || (TARGET_NEON && VALID_NEON_DREG_MODE (mode))); | |
10303 | gcc_assert (MEM_P (mem)); | |
10304 | ||
10305 | addr = XEXP (mem, 0); | |
10306 | ||
10307 | switch (GET_CODE (addr)) | |
10308 | { | |
10309 | case PRE_DEC: | |
10310 | template = "f%smdb%c%%?\t%%0!, {%%%s1}%s"; | |
10311 | ops[0] = XEXP (addr, 0); | |
10312 | ops[1] = reg; | |
5b3e6663 PB |
10313 | break; |
10314 | ||
10315 | case POST_INC: | |
10316 | template = "f%smia%c%%?\t%%0!, {%%%s1}%s"; | |
10317 | ops[0] = XEXP (addr, 0); | |
10318 | ops[1] = reg; | |
10319 | break; | |
10320 | ||
10321 | default: | |
10322 | template = "f%s%c%%?\t%%%s0, %%1%s"; | |
10323 | ops[0] = reg; | |
10324 | ops[1] = mem; | |
10325 | break; | |
10326 | } | |
10327 | ||
10328 | sprintf (buff, template, | |
10329 | load ? "ld" : "st", | |
10330 | dp ? 'd' : 's', | |
10331 | dp ? "P" : "", | |
10332 | integer_p ? "\t%@ int" : ""); | |
10333 | output_asm_insn (buff, ops); | |
10334 | ||
10335 | return ""; | |
10336 | } | |
10337 | ||
88f77cba JB |
10338 | /* Output a Neon quad-word load or store, or a load or store for |
10339 | larger structure modes. We could also support post-modify forms using | |
10340 | VLD1/VST1 (for the vectorizer, and perhaps otherwise), but we don't do that | |
10341 | yet. | |
10342 | WARNING: The ordering of elements in memory is weird in big-endian mode, | |
10343 | because we use VSTM instead of VST1, to make it easy to make vector stores | |
10344 | via ARM registers write values in the same order as stores direct from Neon | |
10345 | registers. For example, the byte ordering of a quadword vector with 16-byte | |
10346 | elements like this: | |
10347 | ||
10348 | [e7:e6:e5:e4:e3:e2:e1:e0] (highest-numbered element first) | |
10349 | ||
10350 | will be (with lowest address first, h = most-significant byte, | |
10351 | l = least-significant byte of element): | |
10352 | ||
10353 | [e3h, e3l, e2h, e2l, e1h, e1l, e0h, e0l, | |
10354 | e7h, e7l, e6h, e6l, e5h, e5l, e4h, e4l] | |
10355 | ||
10356 | When necessary, quadword registers (dN, dN+1) are moved to ARM registers from | |
10357 | rN in the order: | |
10358 | ||
10359 | dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2) | |
10360 | ||
10361 | So that STM/LDM can be used on vectors in ARM registers, and the same memory | |
10362 | layout will result as if VSTM/VLDM were used. */ | |
10363 | ||
10364 | const char * | |
10365 | output_move_neon (rtx *operands) | |
10366 | { | |
10367 | rtx reg, mem, addr, ops[2]; | |
10368 | int regno, load = REG_P (operands[0]); | |
10369 | const char *template; | |
10370 | char buff[50]; | |
10371 | enum machine_mode mode; | |
10372 | ||
10373 | reg = operands[!load]; | |
10374 | mem = operands[load]; | |
10375 | ||
10376 | mode = GET_MODE (reg); | |
10377 | ||
10378 | gcc_assert (REG_P (reg)); | |
10379 | regno = REGNO (reg); | |
10380 | gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno) | |
10381 | || NEON_REGNO_OK_FOR_QUAD (regno)); | |
10382 | gcc_assert (VALID_NEON_DREG_MODE (mode) | |
10383 | || VALID_NEON_QREG_MODE (mode) | |
10384 | || VALID_NEON_STRUCT_MODE (mode)); | |
10385 | gcc_assert (MEM_P (mem)); | |
10386 | ||
10387 | addr = XEXP (mem, 0); | |
10388 | ||
10389 | /* Strip off const from addresses like (const (plus (...))). */ | |
10390 | if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS) | |
10391 | addr = XEXP (addr, 0); | |
10392 | ||
10393 | switch (GET_CODE (addr)) | |
10394 | { | |
10395 | case POST_INC: | |
10396 | template = "v%smia%%?\t%%0!, %%h1"; | |
10397 | ops[0] = XEXP (addr, 0); | |
10398 | ops[1] = reg; | |
10399 | break; | |
10400 | ||
10401 | case POST_MODIFY: | |
10402 | /* FIXME: Not currently enabled in neon_vector_mem_operand. */ | |
10403 | gcc_unreachable (); | |
10404 | ||
10405 | case LABEL_REF: | |
10406 | case PLUS: | |
10407 | { | |
10408 | int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2; | |
10409 | int i; | |
10410 | int overlap = -1; | |
10411 | for (i = 0; i < nregs; i++) | |
10412 | { | |
10413 | /* We're only using DImode here because it's a convenient size. */ | |
10414 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); | |
10415 | ops[1] = adjust_address (mem, SImode, 8 * i); | |
10416 | if (reg_overlap_mentioned_p (ops[0], mem)) | |
10417 | { | |
10418 | gcc_assert (overlap == -1); | |
10419 | overlap = i; | |
10420 | } | |
10421 | else | |
10422 | { | |
10423 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
10424 | output_asm_insn (buff, ops); | |
10425 | } | |
10426 | } | |
10427 | if (overlap != -1) | |
10428 | { | |
10429 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap); | |
10430 | ops[1] = adjust_address (mem, SImode, 8 * overlap); | |
10431 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
10432 | output_asm_insn (buff, ops); | |
10433 | } | |
10434 | ||
10435 | return ""; | |
10436 | } | |
10437 | ||
10438 | default: | |
10439 | template = "v%smia%%?\t%%m0, %%h1"; | |
10440 | ops[0] = mem; | |
10441 | ops[1] = reg; | |
10442 | } | |
10443 | ||
10444 | sprintf (buff, template, load ? "ld" : "st"); | |
10445 | output_asm_insn (buff, ops); | |
10446 | ||
10447 | return ""; | |
10448 | } | |
10449 | ||
1d6e90ac NC |
10450 | /* Output an ADD r, s, #n where n may be too big for one instruction. |
10451 | If adding zero to one register, output nothing. */ | |
cd2b33d0 | 10452 | const char * |
e32bac5b | 10453 | output_add_immediate (rtx *operands) |
cce8749e | 10454 | { |
f3bb6135 | 10455 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
10456 | |
10457 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
10458 | { | |
10459 | if (n < 0) | |
10460 | output_multi_immediate (operands, | |
9997d19d RE |
10461 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
10462 | -n); | |
cce8749e CH |
10463 | else |
10464 | output_multi_immediate (operands, | |
9997d19d RE |
10465 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
10466 | n); | |
cce8749e | 10467 | } |
f3bb6135 RE |
10468 | |
10469 | return ""; | |
10470 | } | |
cce8749e | 10471 | |
cce8749e CH |
10472 | /* Output a multiple immediate operation. |
10473 | OPERANDS is the vector of operands referred to in the output patterns. | |
10474 | INSTR1 is the output pattern to use for the first constant. | |
10475 | INSTR2 is the output pattern to use for subsequent constants. | |
10476 | IMMED_OP is the index of the constant slot in OPERANDS. | |
10477 | N is the constant value. */ | |
cd2b33d0 | 10478 | static const char * |
e32bac5b RE |
10479 | output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, |
10480 | int immed_op, HOST_WIDE_INT n) | |
cce8749e | 10481 | { |
f3bb6135 | 10482 | #if HOST_BITS_PER_WIDE_INT > 32 |
30cf4896 | 10483 | n &= 0xffffffff; |
f3bb6135 RE |
10484 | #endif |
10485 | ||
cce8749e CH |
10486 | if (n == 0) |
10487 | { | |
1d6e90ac | 10488 | /* Quick and easy output. */ |
cce8749e | 10489 | operands[immed_op] = const0_rtx; |
1d6e90ac | 10490 | output_asm_insn (instr1, operands); |
cce8749e CH |
10491 | } |
10492 | else | |
10493 | { | |
10494 | int i; | |
cd2b33d0 | 10495 | const char * instr = instr1; |
cce8749e | 10496 | |
6354dc9b | 10497 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
10498 | for (i = 0; i < 32; i += 2) |
10499 | { | |
10500 | if (n & (3 << i)) | |
10501 | { | |
f3bb6135 RE |
10502 | operands[immed_op] = GEN_INT (n & (255 << i)); |
10503 | output_asm_insn (instr, operands); | |
cce8749e CH |
10504 | instr = instr2; |
10505 | i += 6; | |
10506 | } | |
10507 | } | |
10508 | } | |
f676971a | 10509 | |
f3bb6135 | 10510 | return ""; |
9997d19d | 10511 | } |
cce8749e | 10512 | |
5b3e6663 PB |
10513 | /* Return the name of a shifter operation. */ |
10514 | static const char * | |
10515 | arm_shift_nmem(enum rtx_code code) | |
10516 | { | |
10517 | switch (code) | |
10518 | { | |
10519 | case ASHIFT: | |
10520 | return ARM_LSL_NAME; | |
10521 | ||
10522 | case ASHIFTRT: | |
10523 | return "asr"; | |
10524 | ||
10525 | case LSHIFTRT: | |
10526 | return "lsr"; | |
10527 | ||
10528 | case ROTATERT: | |
10529 | return "ror"; | |
10530 | ||
10531 | default: | |
10532 | abort(); | |
10533 | } | |
10534 | } | |
10535 | ||
cce8749e CH |
10536 | /* Return the appropriate ARM instruction for the operation code. |
10537 | The returned result should not be overwritten. OP is the rtx of the | |
10538 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
10539 | was shifted. */ | |
cd2b33d0 | 10540 | const char * |
e32bac5b | 10541 | arithmetic_instr (rtx op, int shift_first_arg) |
cce8749e | 10542 | { |
9997d19d | 10543 | switch (GET_CODE (op)) |
cce8749e CH |
10544 | { |
10545 | case PLUS: | |
f3bb6135 RE |
10546 | return "add"; |
10547 | ||
cce8749e | 10548 | case MINUS: |
f3bb6135 RE |
10549 | return shift_first_arg ? "rsb" : "sub"; |
10550 | ||
cce8749e | 10551 | case IOR: |
f3bb6135 RE |
10552 | return "orr"; |
10553 | ||
cce8749e | 10554 | case XOR: |
f3bb6135 RE |
10555 | return "eor"; |
10556 | ||
cce8749e | 10557 | case AND: |
f3bb6135 RE |
10558 | return "and"; |
10559 | ||
5b3e6663 PB |
10560 | case ASHIFT: |
10561 | case ASHIFTRT: | |
10562 | case LSHIFTRT: | |
10563 | case ROTATERT: | |
10564 | return arm_shift_nmem(GET_CODE(op)); | |
10565 | ||
cce8749e | 10566 | default: |
e6d29d15 | 10567 | gcc_unreachable (); |
cce8749e | 10568 | } |
f3bb6135 | 10569 | } |
cce8749e | 10570 | |
cce8749e CH |
10571 | /* Ensure valid constant shifts and return the appropriate shift mnemonic |
10572 | for the operation code. The returned result should not be overwritten. | |
10573 | OP is the rtx code of the shift. | |
9997d19d | 10574 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 10575 | shift. */ |
cd2b33d0 | 10576 | static const char * |
e32bac5b | 10577 | shift_op (rtx op, HOST_WIDE_INT *amountp) |
cce8749e | 10578 | { |
cd2b33d0 | 10579 | const char * mnem; |
e2c671ba | 10580 | enum rtx_code code = GET_CODE (op); |
cce8749e | 10581 | |
e6d29d15 NS |
10582 | switch (GET_CODE (XEXP (op, 1))) |
10583 | { | |
10584 | case REG: | |
10585 | case SUBREG: | |
10586 | *amountp = -1; | |
10587 | break; | |
10588 | ||
10589 | case CONST_INT: | |
10590 | *amountp = INTVAL (XEXP (op, 1)); | |
10591 | break; | |
10592 | ||
10593 | default: | |
10594 | gcc_unreachable (); | |
10595 | } | |
9997d19d | 10596 | |
e2c671ba | 10597 | switch (code) |
cce8749e | 10598 | { |
a657c98a | 10599 | case ROTATE: |
e6d29d15 | 10600 | gcc_assert (*amountp != -1); |
a657c98a | 10601 | *amountp = 32 - *amountp; |
5b3e6663 | 10602 | code = ROTATERT; |
a657c98a RE |
10603 | |
10604 | /* Fall through. */ | |
10605 | ||
5b3e6663 PB |
10606 | case ASHIFT: |
10607 | case ASHIFTRT: | |
10608 | case LSHIFTRT: | |
9997d19d | 10609 | case ROTATERT: |
5b3e6663 | 10610 | mnem = arm_shift_nmem(code); |
9997d19d RE |
10611 | break; |
10612 | ||
ff9940b0 | 10613 | case MULT: |
e2c671ba RE |
10614 | /* We never have to worry about the amount being other than a |
10615 | power of 2, since this case can never be reloaded from a reg. */ | |
e6d29d15 NS |
10616 | gcc_assert (*amountp != -1); |
10617 | *amountp = int_log2 (*amountp); | |
5b3e6663 | 10618 | return ARM_LSL_NAME; |
f3bb6135 | 10619 | |
cce8749e | 10620 | default: |
e6d29d15 | 10621 | gcc_unreachable (); |
cce8749e CH |
10622 | } |
10623 | ||
e2c671ba RE |
10624 | if (*amountp != -1) |
10625 | { | |
10626 | /* This is not 100% correct, but follows from the desire to merge | |
10627 | multiplication by a power of 2 with the recognizer for a | |
5b3e6663 | 10628 | shift. >=32 is not a valid shift for "lsl", so we must try and |
e2c671ba | 10629 | output a shift that produces the correct arithmetical result. |
ddd5a7c1 | 10630 | Using lsr #32 is identical except for the fact that the carry bit |
f676971a | 10631 | is not set correctly if we set the flags; but we never use the |
e2c671ba RE |
10632 | carry bit from such an operation, so we can ignore that. */ |
10633 | if (code == ROTATERT) | |
1d6e90ac NC |
10634 | /* Rotate is just modulo 32. */ |
10635 | *amountp &= 31; | |
e2c671ba RE |
10636 | else if (*amountp != (*amountp & 31)) |
10637 | { | |
10638 | if (code == ASHIFT) | |
10639 | mnem = "lsr"; | |
10640 | *amountp = 32; | |
10641 | } | |
10642 | ||
10643 | /* Shifts of 0 are no-ops. */ | |
10644 | if (*amountp == 0) | |
10645 | return NULL; | |
f676971a | 10646 | } |
e2c671ba | 10647 | |
9997d19d RE |
10648 | return mnem; |
10649 | } | |
cce8749e | 10650 | |
6354dc9b | 10651 | /* Obtain the shift from the POWER of two. */ |
1d6e90ac | 10652 | |
18af7313 | 10653 | static HOST_WIDE_INT |
e32bac5b | 10654 | int_log2 (HOST_WIDE_INT power) |
cce8749e | 10655 | { |
f3bb6135 | 10656 | HOST_WIDE_INT shift = 0; |
cce8749e | 10657 | |
30cf4896 | 10658 | while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) |
cce8749e | 10659 | { |
e6d29d15 | 10660 | gcc_assert (shift <= 31); |
e32bac5b | 10661 | shift++; |
cce8749e | 10662 | } |
f3bb6135 RE |
10663 | |
10664 | return shift; | |
10665 | } | |
cce8749e | 10666 | |
c5ff069d ZW |
10667 | /* Output a .ascii pseudo-op, keeping track of lengths. This is |
10668 | because /bin/as is horribly restrictive. The judgement about | |
10669 | whether or not each character is 'printable' (and can be output as | |
10670 | is) or not (and must be printed with an octal escape) must be made | |
10671 | with reference to the *host* character set -- the situation is | |
10672 | similar to that discussed in the comments above pp_c_char in | |
10673 | c-pretty-print.c. */ | |
10674 | ||
6cfc7210 | 10675 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
10676 | |
10677 | void | |
e32bac5b | 10678 | output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) |
cce8749e CH |
10679 | { |
10680 | int i; | |
6cfc7210 | 10681 | int len_so_far = 0; |
cce8749e | 10682 | |
6cfc7210 | 10683 | fputs ("\t.ascii\t\"", stream); |
f676971a | 10684 | |
cce8749e CH |
10685 | for (i = 0; i < len; i++) |
10686 | { | |
1d6e90ac | 10687 | int c = p[i]; |
cce8749e | 10688 | |
6cfc7210 | 10689 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 10690 | { |
6cfc7210 | 10691 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 10692 | len_so_far = 0; |
cce8749e CH |
10693 | } |
10694 | ||
c5ff069d | 10695 | if (ISPRINT (c)) |
cce8749e | 10696 | { |
c5ff069d | 10697 | if (c == '\\' || c == '\"') |
6cfc7210 | 10698 | { |
c5ff069d | 10699 | putc ('\\', stream); |
5895f793 | 10700 | len_so_far++; |
6cfc7210 | 10701 | } |
c5ff069d ZW |
10702 | putc (c, stream); |
10703 | len_so_far++; | |
10704 | } | |
10705 | else | |
10706 | { | |
10707 | fprintf (stream, "\\%03o", c); | |
10708 | len_so_far += 4; | |
cce8749e | 10709 | } |
cce8749e | 10710 | } |
f3bb6135 | 10711 | |
cce8749e | 10712 | fputs ("\"\n", stream); |
f3bb6135 | 10713 | } |
cce8749e | 10714 | \f |
c9ca9b88 | 10715 | /* Compute the register save mask for registers 0 through 12 |
5848830f | 10716 | inclusive. This code is used by arm_compute_save_reg_mask. */ |
b279b20a | 10717 | |
6d3d9133 | 10718 | static unsigned long |
e32bac5b | 10719 | arm_compute_save_reg0_reg12_mask (void) |
6d3d9133 | 10720 | { |
121308d4 | 10721 | unsigned long func_type = arm_current_func_type (); |
b279b20a | 10722 | unsigned long save_reg_mask = 0; |
6d3d9133 | 10723 | unsigned int reg; |
6d3d9133 | 10724 | |
7b8b8ade | 10725 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 10726 | { |
7b8b8ade | 10727 | unsigned int max_reg; |
7b8b8ade NC |
10728 | /* Interrupt functions must not corrupt any registers, |
10729 | even call clobbered ones. If this is a leaf function | |
10730 | we can just examine the registers used by the RTL, but | |
10731 | otherwise we have to assume that whatever function is | |
10732 | called might clobber anything, and so we have to save | |
10733 | all the call-clobbered registers as well. */ | |
10734 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
10735 | /* FIQ handlers have registers r8 - r12 banked, so | |
10736 | we only need to check r0 - r7, Normal ISRs only | |
121308d4 | 10737 | bank r14 and r15, so we must check up to r12. |
7b8b8ade NC |
10738 | r13 is the stack pointer which is always preserved, |
10739 | so we do not need to consider it here. */ | |
10740 | max_reg = 7; | |
10741 | else | |
10742 | max_reg = 12; | |
f676971a | 10743 | |
7b8b8ade | 10744 | for (reg = 0; reg <= max_reg; reg++) |
6fb5fa3c DB |
10745 | if (df_regs_ever_live_p (reg) |
10746 | || (! current_function_is_leaf && call_used_regs[reg])) | |
6d3d9133 | 10747 | save_reg_mask |= (1 << reg); |
cfa01aab | 10748 | |
286d28c3 | 10749 | /* Also save the pic base register if necessary. */ |
cfa01aab PB |
10750 | if (flag_pic |
10751 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 10752 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 10753 | && crtl->uses_pic_offset_table) |
cfa01aab | 10754 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
6d3d9133 NC |
10755 | } |
10756 | else | |
10757 | { | |
10758 | /* In the normal case we only need to save those registers | |
10759 | which are call saved and which are used by this function. */ | |
ec6237e4 | 10760 | for (reg = 0; reg <= 11; reg++) |
6fb5fa3c | 10761 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
6d3d9133 NC |
10762 | save_reg_mask |= (1 << reg); |
10763 | ||
10764 | /* Handle the frame pointer as a special case. */ | |
ec6237e4 | 10765 | if (frame_pointer_needed) |
6d3d9133 NC |
10766 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; |
10767 | ||
10768 | /* If we aren't loading the PIC register, | |
10769 | don't stack it even though it may be live. */ | |
10770 | if (flag_pic | |
e0b92319 | 10771 | && !TARGET_SINGLE_PIC_BASE |
020a4035 | 10772 | && arm_pic_register != INVALID_REGNUM |
6fb5fa3c | 10773 | && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM) |
e3b5732b | 10774 | || crtl->uses_pic_offset_table)) |
6d3d9133 | 10775 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
5b3e6663 PB |
10776 | |
10777 | /* The prologue will copy SP into R0, so save it. */ | |
10778 | if (IS_STACKALIGN (func_type)) | |
10779 | save_reg_mask |= 1; | |
6d3d9133 NC |
10780 | } |
10781 | ||
c9ca9b88 | 10782 | /* Save registers so the exception handler can modify them. */ |
e3b5732b | 10783 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
10784 | { |
10785 | unsigned int i; | |
f676971a | 10786 | |
c9ca9b88 PB |
10787 | for (i = 0; ; i++) |
10788 | { | |
10789 | reg = EH_RETURN_DATA_REGNO (i); | |
10790 | if (reg == INVALID_REGNUM) | |
10791 | break; | |
10792 | save_reg_mask |= 1 << reg; | |
10793 | } | |
10794 | } | |
10795 | ||
121308d4 NC |
10796 | return save_reg_mask; |
10797 | } | |
10798 | ||
5b3e6663 | 10799 | |
121308d4 | 10800 | /* Compute a bit mask of which registers need to be |
954954d1 PB |
10801 | saved on the stack for the current function. |
10802 | This is used by arm_get_frame_offsets, which may add extra registers. */ | |
121308d4 NC |
10803 | |
10804 | static unsigned long | |
e32bac5b | 10805 | arm_compute_save_reg_mask (void) |
121308d4 NC |
10806 | { |
10807 | unsigned int save_reg_mask = 0; | |
10808 | unsigned long func_type = arm_current_func_type (); | |
5b3e6663 | 10809 | unsigned int reg; |
121308d4 NC |
10810 | |
10811 | if (IS_NAKED (func_type)) | |
10812 | /* This should never really happen. */ | |
10813 | return 0; | |
10814 | ||
10815 | /* If we are creating a stack frame, then we must save the frame pointer, | |
10816 | IP (which will hold the old stack pointer), LR and the PC. */ | |
ec6237e4 | 10817 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
121308d4 NC |
10818 | save_reg_mask |= |
10819 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
10820 | | (1 << IP_REGNUM) | |
10821 | | (1 << LR_REGNUM) | |
10822 | | (1 << PC_REGNUM); | |
10823 | ||
10824 | /* Volatile functions do not return, so there | |
10825 | is no need to save any other registers. */ | |
10826 | if (IS_VOLATILE (func_type)) | |
10827 | return save_reg_mask; | |
10828 | ||
10829 | save_reg_mask |= arm_compute_save_reg0_reg12_mask (); | |
10830 | ||
6d3d9133 NC |
10831 | /* Decide if we need to save the link register. |
10832 | Interrupt routines have their own banked link register, | |
10833 | so they never need to save it. | |
1768c26f | 10834 | Otherwise if we do not use the link register we do not need to save |
6d3d9133 NC |
10835 | it. If we are pushing other registers onto the stack however, we |
10836 | can save an instruction in the epilogue by pushing the link register | |
10837 | now and then popping it back into the PC. This incurs extra memory | |
72ac76be | 10838 | accesses though, so we only do it when optimizing for size, and only |
6d3d9133 | 10839 | if we know that we will not need a fancy return sequence. */ |
6fb5fa3c DB |
10840 | if (df_regs_ever_live_p (LR_REGNUM) |
10841 | || (save_reg_mask | |
10842 | && optimize_size | |
10843 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 10844 | && !crtl->calls_eh_return)) |
6d3d9133 NC |
10845 | save_reg_mask |= 1 << LR_REGNUM; |
10846 | ||
6f7ebcbb NC |
10847 | if (cfun->machine->lr_save_eliminated) |
10848 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
10849 | ||
5a9335ef NC |
10850 | if (TARGET_REALLY_IWMMXT |
10851 | && ((bit_count (save_reg_mask) | |
38173d38 | 10852 | + ARM_NUM_INTS (crtl->args.pretend_args_size)) % 2) != 0) |
5a9335ef | 10853 | { |
5a9335ef NC |
10854 | /* The total number of registers that are going to be pushed |
10855 | onto the stack is odd. We need to ensure that the stack | |
10856 | is 64-bit aligned before we start to save iWMMXt registers, | |
10857 | and also before we start to create locals. (A local variable | |
10858 | might be a double or long long which we will load/store using | |
10859 | an iWMMXt instruction). Therefore we need to push another | |
10860 | ARM register, so that the stack will be 64-bit aligned. We | |
10861 | try to avoid using the arg registers (r0 -r3) as they might be | |
10862 | used to pass values in a tail call. */ | |
10863 | for (reg = 4; reg <= 12; reg++) | |
10864 | if ((save_reg_mask & (1 << reg)) == 0) | |
10865 | break; | |
10866 | ||
10867 | if (reg <= 12) | |
10868 | save_reg_mask |= (1 << reg); | |
10869 | else | |
10870 | { | |
10871 | cfun->machine->sibcall_blocked = 1; | |
10872 | save_reg_mask |= (1 << 3); | |
10873 | } | |
10874 | } | |
10875 | ||
5b3e6663 PB |
10876 | /* We may need to push an additional register for use initializing the |
10877 | PIC base register. */ | |
10878 | if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic | |
10879 | && (save_reg_mask & THUMB2_WORK_REGS) == 0) | |
10880 | { | |
10881 | reg = thumb_find_work_register (1 << 4); | |
10882 | if (!call_used_regs[reg]) | |
10883 | save_reg_mask |= (1 << reg); | |
10884 | } | |
10885 | ||
6d3d9133 NC |
10886 | return save_reg_mask; |
10887 | } | |
10888 | ||
9728c9d1 | 10889 | |
57934c39 PB |
10890 | /* Compute a bit mask of which registers need to be |
10891 | saved on the stack for the current function. */ | |
10892 | static unsigned long | |
5b3e6663 | 10893 | thumb1_compute_save_reg_mask (void) |
57934c39 PB |
10894 | { |
10895 | unsigned long mask; | |
b279b20a | 10896 | unsigned reg; |
57934c39 PB |
10897 | |
10898 | mask = 0; | |
10899 | for (reg = 0; reg < 12; reg ++) | |
6fb5fa3c | 10900 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b279b20a | 10901 | mask |= 1 << reg; |
57934c39 | 10902 | |
39c39be0 RE |
10903 | if (flag_pic |
10904 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 10905 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 10906 | && crtl->uses_pic_offset_table) |
39c39be0 | 10907 | mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
b279b20a | 10908 | |
a2503645 RS |
10909 | /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */ |
10910 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) | |
10911 | mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; | |
57934c39 | 10912 | |
b279b20a | 10913 | /* LR will also be pushed if any lo regs are pushed. */ |
57934c39 PB |
10914 | if (mask & 0xff || thumb_force_lr_save ()) |
10915 | mask |= (1 << LR_REGNUM); | |
10916 | ||
b279b20a NC |
10917 | /* Make sure we have a low work register if we need one. |
10918 | We will need one if we are going to push a high register, | |
10919 | but we are not currently intending to push a low register. */ | |
10920 | if ((mask & 0xff) == 0 | |
57934c39 | 10921 | && ((mask & 0x0f00) || TARGET_BACKTRACE)) |
b279b20a NC |
10922 | { |
10923 | /* Use thumb_find_work_register to choose which register | |
10924 | we will use. If the register is live then we will | |
10925 | have to push it. Use LAST_LO_REGNUM as our fallback | |
10926 | choice for the register to select. */ | |
10927 | reg = thumb_find_work_register (1 << LAST_LO_REGNUM); | |
19e723f4 PB |
10928 | /* Make sure the register returned by thumb_find_work_register is |
10929 | not part of the return value. */ | |
954954d1 | 10930 | if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ()) |
19e723f4 | 10931 | reg = LAST_LO_REGNUM; |
b279b20a NC |
10932 | |
10933 | if (! call_used_regs[reg]) | |
10934 | mask |= 1 << reg; | |
10935 | } | |
57934c39 PB |
10936 | |
10937 | return mask; | |
10938 | } | |
10939 | ||
10940 | ||
9728c9d1 PB |
10941 | /* Return the number of bytes required to save VFP registers. */ |
10942 | static int | |
10943 | arm_get_vfp_saved_size (void) | |
10944 | { | |
10945 | unsigned int regno; | |
10946 | int count; | |
10947 | int saved; | |
10948 | ||
10949 | saved = 0; | |
10950 | /* Space for saved VFP registers. */ | |
10951 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
10952 | { | |
10953 | count = 0; | |
10954 | for (regno = FIRST_VFP_REGNUM; | |
10955 | regno < LAST_VFP_REGNUM; | |
10956 | regno += 2) | |
10957 | { | |
6fb5fa3c DB |
10958 | if ((!df_regs_ever_live_p (regno) || call_used_regs[regno]) |
10959 | && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1])) | |
9728c9d1 PB |
10960 | { |
10961 | if (count > 0) | |
10962 | { | |
10963 | /* Workaround ARM10 VFPr1 bug. */ | |
10964 | if (count == 2 && !arm_arch6) | |
10965 | count++; | |
8edfc4cc | 10966 | saved += count * 8; |
9728c9d1 PB |
10967 | } |
10968 | count = 0; | |
10969 | } | |
10970 | else | |
10971 | count++; | |
10972 | } | |
10973 | if (count > 0) | |
10974 | { | |
10975 | if (count == 2 && !arm_arch6) | |
10976 | count++; | |
8edfc4cc | 10977 | saved += count * 8; |
9728c9d1 PB |
10978 | } |
10979 | } | |
10980 | return saved; | |
10981 | } | |
10982 | ||
10983 | ||
699a4925 | 10984 | /* Generate a function exit sequence. If REALLY_RETURN is false, then do |
6d3d9133 | 10985 | everything bar the final return instruction. */ |
cd2b33d0 | 10986 | const char * |
e32bac5b | 10987 | output_return_instruction (rtx operand, int really_return, int reverse) |
ff9940b0 | 10988 | { |
6d3d9133 | 10989 | char conditional[10]; |
ff9940b0 | 10990 | char instr[100]; |
b279b20a | 10991 | unsigned reg; |
6d3d9133 NC |
10992 | unsigned long live_regs_mask; |
10993 | unsigned long func_type; | |
5848830f | 10994 | arm_stack_offsets *offsets; |
e26053d1 | 10995 | |
6d3d9133 | 10996 | func_type = arm_current_func_type (); |
e2c671ba | 10997 | |
6d3d9133 | 10998 | if (IS_NAKED (func_type)) |
d5b7b3ae | 10999 | return ""; |
6d3d9133 NC |
11000 | |
11001 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 11002 | { |
699a4925 RE |
11003 | /* If this function was declared non-returning, and we have |
11004 | found a tail call, then we have to trust that the called | |
11005 | function won't return. */ | |
3a5a4282 PB |
11006 | if (really_return) |
11007 | { | |
11008 | rtx ops[2]; | |
f676971a | 11009 | |
3a5a4282 PB |
11010 | /* Otherwise, trap an attempted return by aborting. */ |
11011 | ops[0] = operand; | |
f676971a | 11012 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" |
3a5a4282 PB |
11013 | : "abort"); |
11014 | assemble_external_libcall (ops[1]); | |
11015 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
11016 | } | |
f676971a | 11017 | |
e2c671ba RE |
11018 | return ""; |
11019 | } | |
6d3d9133 | 11020 | |
e3b5732b | 11021 | gcc_assert (!cfun->calls_alloca || really_return); |
ff9940b0 | 11022 | |
c414f8a9 | 11023 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); |
d5b7b3ae | 11024 | |
6d3d9133 | 11025 | return_used_this_function = 1; |
ff9940b0 | 11026 | |
954954d1 PB |
11027 | offsets = arm_get_frame_offsets (); |
11028 | live_regs_mask = offsets->saved_regs_mask; | |
ff9940b0 | 11029 | |
1768c26f | 11030 | if (live_regs_mask) |
6d3d9133 | 11031 | { |
1768c26f PB |
11032 | const char * return_reg; |
11033 | ||
f676971a | 11034 | /* If we do not have any special requirements for function exit |
a15908a4 | 11035 | (e.g. interworking) then we can load the return address |
1768c26f PB |
11036 | directly into the PC. Otherwise we must load it into LR. */ |
11037 | if (really_return | |
a15908a4 | 11038 | && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK)) |
1768c26f | 11039 | return_reg = reg_names[PC_REGNUM]; |
6d3d9133 | 11040 | else |
1768c26f PB |
11041 | return_reg = reg_names[LR_REGNUM]; |
11042 | ||
6d3d9133 | 11043 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) |
b034930f ILT |
11044 | { |
11045 | /* There are three possible reasons for the IP register | |
11046 | being saved. 1) a stack frame was created, in which case | |
11047 | IP contains the old stack pointer, or 2) an ISR routine | |
11048 | corrupted it, or 3) it was saved to align the stack on | |
11049 | iWMMXt. In case 1, restore IP into SP, otherwise just | |
11050 | restore IP. */ | |
11051 | if (frame_pointer_needed) | |
11052 | { | |
11053 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
11054 | live_regs_mask |= (1 << SP_REGNUM); | |
11055 | } | |
11056 | else | |
e6d29d15 | 11057 | gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); |
b034930f | 11058 | } |
f3bb6135 | 11059 | |
3a7731fd PB |
11060 | /* On some ARM architectures it is faster to use LDR rather than |
11061 | LDM to load a single register. On other architectures, the | |
11062 | cost is the same. In 26 bit mode, or for exception handlers, | |
11063 | we have to use LDM to load the PC so that the CPSR is also | |
11064 | restored. */ | |
11065 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) | |
b279b20a NC |
11066 | if (live_regs_mask == (1U << reg)) |
11067 | break; | |
11068 | ||
3a7731fd PB |
11069 | if (reg <= LAST_ARM_REGNUM |
11070 | && (reg != LR_REGNUM | |
f676971a | 11071 | || ! really_return |
61f0ccff | 11072 | || ! IS_INTERRUPT (func_type))) |
3a7731fd | 11073 | { |
f676971a | 11074 | sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, |
3a7731fd | 11075 | (reg == LR_REGNUM) ? return_reg : reg_names[reg]); |
6d3d9133 | 11076 | } |
ff9940b0 | 11077 | else |
1d5473cb | 11078 | { |
1768c26f PB |
11079 | char *p; |
11080 | int first = 1; | |
6d3d9133 | 11081 | |
699a4925 RE |
11082 | /* Generate the load multiple instruction to restore the |
11083 | registers. Note we can get here, even if | |
11084 | frame_pointer_needed is true, but only if sp already | |
11085 | points to the base of the saved core registers. */ | |
11086 | if (live_regs_mask & (1 << SP_REGNUM)) | |
a72d4945 | 11087 | { |
5848830f PB |
11088 | unsigned HOST_WIDE_INT stack_adjust; |
11089 | ||
5848830f | 11090 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; |
e6d29d15 | 11091 | gcc_assert (stack_adjust == 0 || stack_adjust == 4); |
a72d4945 | 11092 | |
5b3e6663 | 11093 | if (stack_adjust && arm_arch5 && TARGET_ARM) |
a72d4945 RE |
11094 | sprintf (instr, "ldm%sib\t%%|sp, {", conditional); |
11095 | else | |
11096 | { | |
b279b20a NC |
11097 | /* If we can't use ldmib (SA110 bug), |
11098 | then try to pop r3 instead. */ | |
a72d4945 RE |
11099 | if (stack_adjust) |
11100 | live_regs_mask |= 1 << 3; | |
11101 | sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); | |
11102 | } | |
11103 | } | |
da6558fd | 11104 | else |
1768c26f PB |
11105 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); |
11106 | ||
11107 | p = instr + strlen (instr); | |
6d3d9133 | 11108 | |
1768c26f PB |
11109 | for (reg = 0; reg <= SP_REGNUM; reg++) |
11110 | if (live_regs_mask & (1 << reg)) | |
11111 | { | |
11112 | int l = strlen (reg_names[reg]); | |
11113 | ||
11114 | if (first) | |
11115 | first = 0; | |
11116 | else | |
11117 | { | |
11118 | memcpy (p, ", ", 2); | |
11119 | p += 2; | |
11120 | } | |
11121 | ||
11122 | memcpy (p, "%|", 2); | |
11123 | memcpy (p + 2, reg_names[reg], l); | |
11124 | p += l + 2; | |
11125 | } | |
f676971a | 11126 | |
1768c26f PB |
11127 | if (live_regs_mask & (1 << LR_REGNUM)) |
11128 | { | |
b17fe233 | 11129 | sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); |
61f0ccff RE |
11130 | /* If returning from an interrupt, restore the CPSR. */ |
11131 | if (IS_INTERRUPT (func_type)) | |
b17fe233 | 11132 | strcat (p, "^"); |
1768c26f PB |
11133 | } |
11134 | else | |
11135 | strcpy (p, "}"); | |
1d5473cb | 11136 | } |
da6558fd | 11137 | |
1768c26f PB |
11138 | output_asm_insn (instr, & operand); |
11139 | ||
3a7731fd PB |
11140 | /* See if we need to generate an extra instruction to |
11141 | perform the actual function return. */ | |
11142 | if (really_return | |
11143 | && func_type != ARM_FT_INTERWORKED | |
11144 | && (live_regs_mask & (1 << LR_REGNUM)) != 0) | |
da6558fd | 11145 | { |
3a7731fd PB |
11146 | /* The return has already been handled |
11147 | by loading the LR into the PC. */ | |
11148 | really_return = 0; | |
da6558fd | 11149 | } |
ff9940b0 | 11150 | } |
e26053d1 | 11151 | |
1768c26f | 11152 | if (really_return) |
ff9940b0 | 11153 | { |
6d3d9133 NC |
11154 | switch ((int) ARM_FUNC_TYPE (func_type)) |
11155 | { | |
11156 | case ARM_FT_ISR: | |
11157 | case ARM_FT_FIQ: | |
5b3e6663 | 11158 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
11159 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); |
11160 | break; | |
11161 | ||
11162 | case ARM_FT_INTERWORKED: | |
11163 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
11164 | break; | |
11165 | ||
11166 | case ARM_FT_EXCEPTION: | |
5b3e6663 | 11167 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
11168 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); |
11169 | break; | |
11170 | ||
11171 | default: | |
68d560d4 RE |
11172 | /* Use bx if it's available. */ |
11173 | if (arm_arch5 || arm_arch4t) | |
f676971a | 11174 | sprintf (instr, "bx%s\t%%|lr", conditional); |
1768c26f | 11175 | else |
61f0ccff | 11176 | sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); |
6d3d9133 NC |
11177 | break; |
11178 | } | |
1768c26f PB |
11179 | |
11180 | output_asm_insn (instr, & operand); | |
ff9940b0 | 11181 | } |
f3bb6135 | 11182 | |
ff9940b0 RE |
11183 | return ""; |
11184 | } | |
11185 | ||
ef179a26 NC |
11186 | /* Write the function name into the code section, directly preceding |
11187 | the function prologue. | |
11188 | ||
11189 | Code will be output similar to this: | |
11190 | t0 | |
11191 | .ascii "arm_poke_function_name", 0 | |
11192 | .align | |
11193 | t1 | |
11194 | .word 0xff000000 + (t1 - t0) | |
11195 | arm_poke_function_name | |
11196 | mov ip, sp | |
11197 | stmfd sp!, {fp, ip, lr, pc} | |
11198 | sub fp, ip, #4 | |
11199 | ||
11200 | When performing a stack backtrace, code can inspect the value | |
11201 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
11202 | at location pc - 12 and the top 8 bits are set, then we know | |
11203 | that there is a function name embedded immediately preceding this | |
11204 | location and has length ((pc[-3]) & 0xff000000). | |
11205 | ||
11206 | We assume that pc is declared as a pointer to an unsigned long. | |
11207 | ||
11208 | It is of no benefit to output the function name if we are assembling | |
11209 | a leaf function. These function types will not contain a stack | |
11210 | backtrace structure, therefore it is not possible to determine the | |
11211 | function name. */ | |
ef179a26 | 11212 | void |
e32bac5b | 11213 | arm_poke_function_name (FILE *stream, const char *name) |
ef179a26 NC |
11214 | { |
11215 | unsigned long alignlength; | |
11216 | unsigned long length; | |
11217 | rtx x; | |
11218 | ||
d5b7b3ae | 11219 | length = strlen (name) + 1; |
0c2ca901 | 11220 | alignlength = ROUND_UP_WORD (length); |
f676971a | 11221 | |
949d79eb | 11222 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 11223 | ASM_OUTPUT_ALIGN (stream, 2); |
30cf4896 | 11224 | x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); |
301d03af | 11225 | assemble_aligned_integer (UNITS_PER_WORD, x); |
ef179a26 NC |
11226 | } |
11227 | ||
6d3d9133 NC |
11228 | /* Place some comments into the assembler stream |
11229 | describing the current function. */ | |
08c148a8 | 11230 | static void |
e32bac5b | 11231 | arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) |
cce8749e | 11232 | { |
6d3d9133 | 11233 | unsigned long func_type; |
08c148a8 | 11234 | |
5b3e6663 | 11235 | if (TARGET_THUMB1) |
08c148a8 | 11236 | { |
5b3e6663 | 11237 | thumb1_output_function_prologue (f, frame_size); |
08c148a8 NB |
11238 | return; |
11239 | } | |
f676971a | 11240 | |
6d3d9133 | 11241 | /* Sanity check. */ |
e6d29d15 | 11242 | gcc_assert (!arm_ccfsm_state && !arm_target_insn); |
31fdb4d5 | 11243 | |
6d3d9133 | 11244 | func_type = arm_current_func_type (); |
f676971a | 11245 | |
6d3d9133 NC |
11246 | switch ((int) ARM_FUNC_TYPE (func_type)) |
11247 | { | |
11248 | default: | |
11249 | case ARM_FT_NORMAL: | |
11250 | break; | |
11251 | case ARM_FT_INTERWORKED: | |
11252 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
11253 | break; | |
6d3d9133 NC |
11254 | case ARM_FT_ISR: |
11255 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
11256 | break; | |
11257 | case ARM_FT_FIQ: | |
11258 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
11259 | break; | |
11260 | case ARM_FT_EXCEPTION: | |
11261 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
11262 | break; | |
11263 | } | |
f676971a | 11264 | |
6d3d9133 NC |
11265 | if (IS_NAKED (func_type)) |
11266 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
11267 | ||
11268 | if (IS_VOLATILE (func_type)) | |
11269 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
11270 | ||
11271 | if (IS_NESTED (func_type)) | |
11272 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
5b3e6663 PB |
11273 | if (IS_STACKALIGN (func_type)) |
11274 | asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n"); | |
f676971a | 11275 | |
c53dddc2 | 11276 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", |
38173d38 JH |
11277 | crtl->args.size, |
11278 | crtl->args.pretend_args_size, frame_size); | |
6d3d9133 | 11279 | |
3cb66fd7 | 11280 | asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", |
dd18ae56 | 11281 | frame_pointer_needed, |
3cb66fd7 | 11282 | cfun->machine->uses_anonymous_args); |
cce8749e | 11283 | |
6f7ebcbb NC |
11284 | if (cfun->machine->lr_save_eliminated) |
11285 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
11286 | ||
e3b5732b | 11287 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
11288 | asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n"); |
11289 | ||
f676971a | 11290 | return_used_this_function = 0; |
f3bb6135 | 11291 | } |
cce8749e | 11292 | |
cd2b33d0 | 11293 | const char * |
a72d4945 | 11294 | arm_output_epilogue (rtx sibling) |
cce8749e | 11295 | { |
949d79eb | 11296 | int reg; |
6f7ebcbb | 11297 | unsigned long saved_regs_mask; |
6d3d9133 | 11298 | unsigned long func_type; |
f676971a | 11299 | /* Floats_offset is the offset from the "virtual" frame. In an APCS |
c882c7ac RE |
11300 | frame that is $fp + 4 for a non-variadic function. */ |
11301 | int floats_offset = 0; | |
cce8749e | 11302 | rtx operands[3]; |
d5b7b3ae | 11303 | FILE * f = asm_out_file; |
5a9335ef | 11304 | unsigned int lrm_count = 0; |
a72d4945 | 11305 | int really_return = (sibling == NULL); |
9b66ebb1 | 11306 | int start_reg; |
5848830f | 11307 | arm_stack_offsets *offsets; |
cce8749e | 11308 | |
6d3d9133 NC |
11309 | /* If we have already generated the return instruction |
11310 | then it is futile to generate anything else. */ | |
a72d4945 | 11311 | if (use_return_insn (FALSE, sibling) && return_used_this_function) |
949d79eb | 11312 | return ""; |
cce8749e | 11313 | |
6d3d9133 | 11314 | func_type = arm_current_func_type (); |
d5b7b3ae | 11315 | |
6d3d9133 NC |
11316 | if (IS_NAKED (func_type)) |
11317 | /* Naked functions don't have epilogues. */ | |
11318 | return ""; | |
0616531f | 11319 | |
6d3d9133 | 11320 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 11321 | { |
86efdc8e | 11322 | rtx op; |
f676971a | 11323 | |
6d3d9133 | 11324 | /* A volatile function should never return. Call abort. */ |
ed0e6530 | 11325 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 11326 | assemble_external_libcall (op); |
e2c671ba | 11327 | output_asm_insn ("bl\t%a0", &op); |
f676971a | 11328 | |
949d79eb | 11329 | return ""; |
e2c671ba RE |
11330 | } |
11331 | ||
e6d29d15 NS |
11332 | /* If we are throwing an exception, then we really must be doing a |
11333 | return, so we can't tail-call. */ | |
e3b5732b | 11334 | gcc_assert (!crtl->calls_eh_return || really_return); |
f676971a | 11335 | |
5848830f | 11336 | offsets = arm_get_frame_offsets (); |
954954d1 | 11337 | saved_regs_mask = offsets->saved_regs_mask; |
5a9335ef NC |
11338 | |
11339 | if (TARGET_IWMMXT) | |
11340 | lrm_count = bit_count (saved_regs_mask); | |
11341 | ||
5848830f | 11342 | floats_offset = offsets->saved_args; |
6d3d9133 | 11343 | /* Compute how far away the floats will be. */ |
5a9335ef | 11344 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) |
6f7ebcbb | 11345 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 11346 | floats_offset += 4; |
f676971a | 11347 | |
ec6237e4 | 11348 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
cce8749e | 11349 | { |
9b66ebb1 | 11350 | /* This variable is for the Virtual Frame Pointer, not VFP regs. */ |
5848830f | 11351 | int vfp_offset = offsets->frame; |
c882c7ac | 11352 | |
29ad9694 | 11353 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 11354 | { |
9b66ebb1 | 11355 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
6fb5fa3c | 11356 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
11357 | { |
11358 | floats_offset += 12; | |
f676971a | 11359 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
c882c7ac | 11360 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
11361 | } |
11362 | } | |
11363 | else | |
11364 | { | |
9b66ebb1 | 11365 | start_reg = LAST_FPA_REGNUM; |
b111229a | 11366 | |
9b66ebb1 | 11367 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
b111229a | 11368 | { |
6fb5fa3c | 11369 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
11370 | { |
11371 | floats_offset += 12; | |
f676971a | 11372 | |
6354dc9b | 11373 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
11374 | if (start_reg - reg == 3) |
11375 | { | |
dd18ae56 | 11376 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
c882c7ac | 11377 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
11378 | start_reg = reg - 1; |
11379 | } | |
11380 | } | |
11381 | else | |
11382 | { | |
11383 | if (reg != start_reg) | |
dd18ae56 NC |
11384 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
11385 | reg + 1, start_reg - reg, | |
c882c7ac | 11386 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
11387 | start_reg = reg - 1; |
11388 | } | |
11389 | } | |
11390 | ||
11391 | /* Just in case the last register checked also needs unstacking. */ | |
11392 | if (reg != start_reg) | |
dd18ae56 NC |
11393 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
11394 | reg + 1, start_reg - reg, | |
c882c7ac | 11395 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a | 11396 | } |
6d3d9133 | 11397 | |
9b66ebb1 PB |
11398 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
11399 | { | |
9728c9d1 | 11400 | int saved_size; |
9b66ebb1 | 11401 | |
8edfc4cc MS |
11402 | /* The fldmd insns do not have base+offset addressing |
11403 | modes, so we use IP to hold the address. */ | |
9728c9d1 | 11404 | saved_size = arm_get_vfp_saved_size (); |
9b66ebb1 | 11405 | |
9728c9d1 | 11406 | if (saved_size > 0) |
9b66ebb1 | 11407 | { |
9728c9d1 | 11408 | floats_offset += saved_size; |
9b66ebb1 PB |
11409 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM, |
11410 | FP_REGNUM, floats_offset - vfp_offset); | |
11411 | } | |
11412 | start_reg = FIRST_VFP_REGNUM; | |
11413 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
11414 | { | |
6fb5fa3c DB |
11415 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
11416 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
9b66ebb1 PB |
11417 | { |
11418 | if (start_reg != reg) | |
8edfc4cc | 11419 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
11420 | (start_reg - FIRST_VFP_REGNUM) / 2, |
11421 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
11422 | start_reg = reg + 2; |
11423 | } | |
11424 | } | |
11425 | if (start_reg != reg) | |
8edfc4cc | 11426 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
11427 | (start_reg - FIRST_VFP_REGNUM) / 2, |
11428 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
11429 | } |
11430 | ||
5a9335ef NC |
11431 | if (TARGET_IWMMXT) |
11432 | { | |
11433 | /* The frame pointer is guaranteed to be non-double-word aligned. | |
11434 | This is because it is set to (old_stack_pointer - 4) and the | |
11435 | old_stack_pointer was double word aligned. Thus the offset to | |
11436 | the iWMMXt registers to be loaded must also be non-double-word | |
11437 | sized, so that the resultant address *is* double-word aligned. | |
11438 | We can ignore floats_offset since that was already included in | |
11439 | the live_regs_mask. */ | |
11440 | lrm_count += (lrm_count % 2 ? 2 : 1); | |
f676971a | 11441 | |
01d4c813 | 11442 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) |
6fb5fa3c | 11443 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5a9335ef | 11444 | { |
f676971a | 11445 | asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", |
5a9335ef | 11446 | reg, FP_REGNUM, lrm_count * 4); |
f676971a | 11447 | lrm_count += 2; |
5a9335ef NC |
11448 | } |
11449 | } | |
11450 | ||
6f7ebcbb | 11451 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
11452 | frame generation actually contains the old stack pointer. So a |
11453 | quick way to unwind the stack is just pop the IP register directly | |
11454 | into the stack pointer. */ | |
e6d29d15 | 11455 | gcc_assert (saved_regs_mask & (1 << IP_REGNUM)); |
6f7ebcbb NC |
11456 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
11457 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 11458 | |
6f7ebcbb | 11459 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
11460 | only need to restore the LR register (the return address), but to |
11461 | save time we can load it directly into the PC, unless we need a | |
11462 | special function exit sequence, or we are not really returning. */ | |
c9ca9b88 PB |
11463 | if (really_return |
11464 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 11465 | && !crtl->calls_eh_return) |
6d3d9133 NC |
11466 | /* Delete the LR from the register mask, so that the LR on |
11467 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 11468 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 11469 | else |
6f7ebcbb | 11470 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
efc2515b RE |
11471 | |
11472 | /* We must use SP as the base register, because SP is one of the | |
11473 | registers being restored. If an interrupt or page fault | |
11474 | happens in the ldm instruction, the SP might or might not | |
11475 | have been restored. That would be bad, as then SP will no | |
11476 | longer indicate the safe area of stack, and we can get stack | |
11477 | corruption. Using SP as the base register means that it will | |
11478 | be reset correctly to the original value, should an interrupt | |
699a4925 RE |
11479 | occur. If the stack pointer already points at the right |
11480 | place, then omit the subtraction. */ | |
5848830f | 11481 | if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask)) |
e3b5732b | 11482 | || cfun->calls_alloca) |
699a4925 RE |
11483 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, |
11484 | 4 * bit_count (saved_regs_mask)); | |
a15908a4 | 11485 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0); |
7b8b8ade NC |
11486 | |
11487 | if (IS_INTERRUPT (func_type)) | |
11488 | /* Interrupt handlers will have pushed the | |
11489 | IP onto the stack, so restore it now. */ | |
a15908a4 | 11490 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0); |
cce8749e CH |
11491 | } |
11492 | else | |
11493 | { | |
ec6237e4 PB |
11494 | /* This branch is executed for ARM mode (non-apcs frames) and |
11495 | Thumb-2 mode. Frame layout is essentially the same for those | |
11496 | cases, except that in ARM mode frame pointer points to the | |
11497 | first saved register, while in Thumb-2 mode the frame pointer points | |
11498 | to the last saved register. | |
11499 | ||
11500 | It is possible to make frame pointer point to last saved | |
11501 | register in both cases, and remove some conditionals below. | |
11502 | That means that fp setup in prologue would be just "mov fp, sp" | |
11503 | and sp restore in epilogue would be just "mov sp, fp", whereas | |
11504 | now we have to use add/sub in those cases. However, the value | |
11505 | of that would be marginal, as both mov and add/sub are 32-bit | |
11506 | in ARM mode, and it would require extra conditionals | |
11507 | in arm_expand_prologue to distingish ARM-apcs-frame case | |
11508 | (where frame pointer is required to point at first register) | |
11509 | and ARM-non-apcs-frame. Therefore, such change is postponed | |
11510 | until real need arise. */ | |
5b3e6663 | 11511 | HOST_WIDE_INT amount; |
a15908a4 | 11512 | int rfe; |
d2288d8d | 11513 | /* Restore stack pointer if necessary. */ |
ec6237e4 | 11514 | if (TARGET_ARM && frame_pointer_needed) |
5b3e6663 PB |
11515 | { |
11516 | operands[0] = stack_pointer_rtx; | |
ec6237e4 PB |
11517 | operands[1] = hard_frame_pointer_rtx; |
11518 | ||
11519 | operands[2] = GEN_INT (offsets->frame - offsets->saved_regs); | |
11520 | output_add_immediate (operands); | |
5b3e6663 | 11521 | } |
ec6237e4 | 11522 | else |
5b3e6663 | 11523 | { |
ec6237e4 PB |
11524 | if (frame_pointer_needed) |
11525 | { | |
11526 | /* For Thumb-2 restore sp from the frame pointer. | |
11527 | Operand restrictions mean we have to incrememnt FP, then copy | |
11528 | to SP. */ | |
11529 | amount = offsets->locals_base - offsets->saved_regs; | |
11530 | operands[0] = hard_frame_pointer_rtx; | |
11531 | } | |
11532 | else | |
11533 | { | |
954954d1 | 11534 | unsigned long count; |
ec6237e4 PB |
11535 | operands[0] = stack_pointer_rtx; |
11536 | amount = offsets->outgoing_args - offsets->saved_regs; | |
954954d1 PB |
11537 | /* pop call clobbered registers if it avoids a |
11538 | separate stack adjustment. */ | |
11539 | count = offsets->saved_regs - offsets->saved_args; | |
11540 | if (optimize_size | |
11541 | && count != 0 | |
e3b5732b | 11542 | && !crtl->calls_eh_return |
954954d1 PB |
11543 | && bit_count(saved_regs_mask) * 4 == count |
11544 | && !IS_INTERRUPT (func_type) | |
e3b5732b | 11545 | && !crtl->tail_call_emit) |
954954d1 PB |
11546 | { |
11547 | unsigned long mask; | |
11548 | mask = (1 << (arm_size_return_regs() / 4)) - 1; | |
11549 | mask ^= 0xf; | |
11550 | mask &= ~saved_regs_mask; | |
11551 | reg = 0; | |
11552 | while (bit_count (mask) * 4 > amount) | |
11553 | { | |
11554 | while ((mask & (1 << reg)) == 0) | |
11555 | reg++; | |
11556 | mask &= ~(1 << reg); | |
11557 | } | |
11558 | if (bit_count (mask) * 4 == amount) { | |
11559 | amount = 0; | |
11560 | saved_regs_mask |= mask; | |
11561 | } | |
11562 | } | |
ec6237e4 PB |
11563 | } |
11564 | ||
11565 | if (amount) | |
11566 | { | |
11567 | operands[1] = operands[0]; | |
11568 | operands[2] = GEN_INT (amount); | |
11569 | output_add_immediate (operands); | |
11570 | } | |
11571 | if (frame_pointer_needed) | |
11572 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
11573 | SP_REGNUM, HARD_FRAME_POINTER_REGNUM); | |
d2288d8d TG |
11574 | } |
11575 | ||
29ad9694 | 11576 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 11577 | { |
9b66ebb1 | 11578 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
6fb5fa3c | 11579 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
dd18ae56 NC |
11580 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
11581 | reg, SP_REGNUM); | |
b111229a RE |
11582 | } |
11583 | else | |
11584 | { | |
9b66ebb1 | 11585 | start_reg = FIRST_FPA_REGNUM; |
b111229a | 11586 | |
9b66ebb1 | 11587 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
b111229a | 11588 | { |
6fb5fa3c | 11589 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
11590 | { |
11591 | if (reg - start_reg == 3) | |
11592 | { | |
dd18ae56 NC |
11593 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
11594 | start_reg, SP_REGNUM); | |
b111229a RE |
11595 | start_reg = reg + 1; |
11596 | } | |
11597 | } | |
11598 | else | |
11599 | { | |
11600 | if (reg != start_reg) | |
dd18ae56 NC |
11601 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
11602 | start_reg, reg - start_reg, | |
11603 | SP_REGNUM); | |
f676971a | 11604 | |
b111229a RE |
11605 | start_reg = reg + 1; |
11606 | } | |
11607 | } | |
11608 | ||
11609 | /* Just in case the last register checked also needs unstacking. */ | |
11610 | if (reg != start_reg) | |
dd18ae56 NC |
11611 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
11612 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
11613 | } |
11614 | ||
9b66ebb1 PB |
11615 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
11616 | { | |
11617 | start_reg = FIRST_VFP_REGNUM; | |
11618 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
11619 | { | |
6fb5fa3c DB |
11620 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
11621 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
9b66ebb1 PB |
11622 | { |
11623 | if (start_reg != reg) | |
8edfc4cc | 11624 | vfp_output_fldmd (f, SP_REGNUM, |
9728c9d1 PB |
11625 | (start_reg - FIRST_VFP_REGNUM) / 2, |
11626 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
11627 | start_reg = reg + 2; |
11628 | } | |
11629 | } | |
11630 | if (start_reg != reg) | |
8edfc4cc | 11631 | vfp_output_fldmd (f, SP_REGNUM, |
9728c9d1 PB |
11632 | (start_reg - FIRST_VFP_REGNUM) / 2, |
11633 | (reg - start_reg) / 2); | |
9b66ebb1 | 11634 | } |
5a9335ef NC |
11635 | if (TARGET_IWMMXT) |
11636 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
6fb5fa3c | 11637 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
01d4c813 | 11638 | asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM); |
5a9335ef | 11639 | |
6d3d9133 | 11640 | /* If we can, restore the LR into the PC. */ |
a15908a4 PB |
11641 | if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED |
11642 | && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) | |
5b3e6663 | 11643 | && !IS_STACKALIGN (func_type) |
6d3d9133 | 11644 | && really_return |
38173d38 | 11645 | && crtl->args.pretend_args_size == 0 |
c9ca9b88 | 11646 | && saved_regs_mask & (1 << LR_REGNUM) |
e3b5732b | 11647 | && !crtl->calls_eh_return) |
cce8749e | 11648 | { |
6f7ebcbb NC |
11649 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
11650 | saved_regs_mask |= (1 << PC_REGNUM); | |
a15908a4 | 11651 | rfe = IS_INTERRUPT (func_type); |
6d3d9133 | 11652 | } |
a15908a4 PB |
11653 | else |
11654 | rfe = 0; | |
d5b7b3ae | 11655 | |
6d3d9133 | 11656 | /* Load the registers off the stack. If we only have one register |
5b3e6663 PB |
11657 | to load use the LDR instruction - it is faster. For Thumb-2 |
11658 | always use pop and the assembler will pick the best instruction.*/ | |
a15908a4 PB |
11659 | if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM) |
11660 | && !IS_INTERRUPT(func_type)) | |
6d3d9133 | 11661 | { |
c9ca9b88 | 11662 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 11663 | } |
6f7ebcbb | 11664 | else if (saved_regs_mask) |
f1acdf8b NC |
11665 | { |
11666 | if (saved_regs_mask & (1 << SP_REGNUM)) | |
11667 | /* Note - write back to the stack register is not enabled | |
112cdef5 | 11668 | (i.e. "ldmfd sp!..."). We know that the stack pointer is |
f1acdf8b NC |
11669 | in the list of registers and if we add writeback the |
11670 | instruction becomes UNPREDICTABLE. */ | |
a15908a4 PB |
11671 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, |
11672 | rfe); | |
5b3e6663 | 11673 | else if (TARGET_ARM) |
a15908a4 PB |
11674 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, |
11675 | rfe); | |
f1acdf8b | 11676 | else |
a15908a4 | 11677 | print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0); |
f1acdf8b | 11678 | } |
6d3d9133 | 11679 | |
38173d38 | 11680 | if (crtl->args.pretend_args_size) |
cce8749e | 11681 | { |
6d3d9133 NC |
11682 | /* Unwind the pre-pushed regs. */ |
11683 | operands[0] = operands[1] = stack_pointer_rtx; | |
38173d38 | 11684 | operands[2] = GEN_INT (crtl->args.pretend_args_size); |
6d3d9133 NC |
11685 | output_add_immediate (operands); |
11686 | } | |
11687 | } | |
32de079a | 11688 | |
2966b00e | 11689 | /* We may have already restored PC directly from the stack. */ |
0cc3dda8 | 11690 | if (!really_return || saved_regs_mask & (1 << PC_REGNUM)) |
6d3d9133 | 11691 | return ""; |
d5b7b3ae | 11692 | |
c9ca9b88 | 11693 | /* Stack adjustment for exception handler. */ |
e3b5732b | 11694 | if (crtl->calls_eh_return) |
f676971a | 11695 | asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, |
c9ca9b88 PB |
11696 | ARM_EH_STACKADJ_REGNUM); |
11697 | ||
6d3d9133 NC |
11698 | /* Generate the return instruction. */ |
11699 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
11700 | { | |
6d3d9133 NC |
11701 | case ARM_FT_ISR: |
11702 | case ARM_FT_FIQ: | |
11703 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
11704 | break; | |
11705 | ||
11706 | case ARM_FT_EXCEPTION: | |
11707 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
11708 | break; | |
11709 | ||
11710 | case ARM_FT_INTERWORKED: | |
11711 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
11712 | break; | |
11713 | ||
11714 | default: | |
5b3e6663 PB |
11715 | if (IS_STACKALIGN (func_type)) |
11716 | { | |
11717 | /* See comment in arm_expand_prologue. */ | |
11718 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0); | |
11719 | } | |
68d560d4 RE |
11720 | if (arm_arch5 || arm_arch4t) |
11721 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
11722 | else | |
11723 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
6d3d9133 | 11724 | break; |
cce8749e | 11725 | } |
f3bb6135 | 11726 | |
949d79eb RE |
11727 | return ""; |
11728 | } | |
11729 | ||
08c148a8 | 11730 | static void |
e32bac5b | 11731 | arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
5848830f | 11732 | HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED) |
949d79eb | 11733 | { |
5848830f PB |
11734 | arm_stack_offsets *offsets; |
11735 | ||
5b3e6663 | 11736 | if (TARGET_THUMB1) |
d5b7b3ae | 11737 | { |
b12a00f1 RE |
11738 | int regno; |
11739 | ||
11740 | /* Emit any call-via-reg trampolines that are needed for v4t support | |
11741 | of call_reg and call_value_reg type insns. */ | |
57ecec57 | 11742 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
11743 | { |
11744 | rtx label = cfun->machine->call_via[regno]; | |
11745 | ||
11746 | if (label != NULL) | |
11747 | { | |
d6b5193b | 11748 | switch_to_section (function_section (current_function_decl)); |
b12a00f1 RE |
11749 | targetm.asm_out.internal_label (asm_out_file, "L", |
11750 | CODE_LABEL_NUMBER (label)); | |
11751 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
11752 | } | |
11753 | } | |
11754 | ||
d5b7b3ae RE |
11755 | /* ??? Probably not safe to set this here, since it assumes that a |
11756 | function will be emitted as assembly immediately after we generate | |
11757 | RTL for it. This does not happen for inline functions. */ | |
11758 | return_used_this_function = 0; | |
11759 | } | |
5b3e6663 | 11760 | else /* TARGET_32BIT */ |
d5b7b3ae | 11761 | { |
0977774b | 11762 | /* We need to take into account any stack-frame rounding. */ |
5848830f | 11763 | offsets = arm_get_frame_offsets (); |
0977774b | 11764 | |
e6d29d15 NS |
11765 | gcc_assert (!use_return_insn (FALSE, NULL) |
11766 | || !return_used_this_function | |
11767 | || offsets->saved_regs == offsets->outgoing_args | |
11768 | || frame_pointer_needed); | |
f3bb6135 | 11769 | |
d5b7b3ae | 11770 | /* Reset the ARM-specific per-function variables. */ |
d5b7b3ae RE |
11771 | after_arm_reorg = 0; |
11772 | } | |
f3bb6135 | 11773 | } |
e2c671ba | 11774 | |
2c849145 JM |
11775 | /* Generate and emit an insn that we will recognize as a push_multi. |
11776 | Unfortunately, since this insn does not reflect very well the actual | |
11777 | semantics of the operation, we need to annotate the insn for the benefit | |
11778 | of DWARF2 frame unwind information. */ | |
2c849145 | 11779 | static rtx |
b279b20a | 11780 | emit_multi_reg_push (unsigned long mask) |
e2c671ba RE |
11781 | { |
11782 | int num_regs = 0; | |
9b598fa0 | 11783 | int num_dwarf_regs; |
e2c671ba RE |
11784 | int i, j; |
11785 | rtx par; | |
2c849145 | 11786 | rtx dwarf; |
87e27392 | 11787 | int dwarf_par_index; |
2c849145 | 11788 | rtx tmp, reg; |
e2c671ba | 11789 | |
d5b7b3ae | 11790 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 11791 | if (mask & (1 << i)) |
5895f793 | 11792 | num_regs++; |
e2c671ba | 11793 | |
e6d29d15 | 11794 | gcc_assert (num_regs && num_regs <= 16); |
e2c671ba | 11795 | |
9b598fa0 RE |
11796 | /* We don't record the PC in the dwarf frame information. */ |
11797 | num_dwarf_regs = num_regs; | |
11798 | if (mask & (1 << PC_REGNUM)) | |
11799 | num_dwarf_regs--; | |
11800 | ||
87e27392 | 11801 | /* For the body of the insn we are going to generate an UNSPEC in |
05713b80 | 11802 | parallel with several USEs. This allows the insn to be recognized |
87e27392 NC |
11803 | by the push_multi pattern in the arm.md file. The insn looks |
11804 | something like this: | |
11805 | ||
f676971a | 11806 | (parallel [ |
b15bca31 RE |
11807 | (set (mem:BLK (pre_dec:BLK (reg:SI sp))) |
11808 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) | |
87e27392 NC |
11809 | (use (reg:SI 11 fp)) |
11810 | (use (reg:SI 12 ip)) | |
11811 | (use (reg:SI 14 lr)) | |
11812 | (use (reg:SI 15 pc)) | |
11813 | ]) | |
11814 | ||
11815 | For the frame note however, we try to be more explicit and actually | |
11816 | show each register being stored into the stack frame, plus a (single) | |
11817 | decrement of the stack pointer. We do it this way in order to be | |
11818 | friendly to the stack unwinding code, which only wants to see a single | |
11819 | stack decrement per instruction. The RTL we generate for the note looks | |
11820 | something like this: | |
11821 | ||
f676971a | 11822 | (sequence [ |
87e27392 NC |
11823 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) |
11824 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
11825 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) | |
11826 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) | |
11827 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) | |
87e27392 NC |
11828 | ]) |
11829 | ||
11830 | This sequence is used both by the code to support stack unwinding for | |
11831 | exceptions handlers and the code to generate dwarf2 frame debugging. */ | |
f676971a | 11832 | |
43cffd11 | 11833 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 11834 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
87e27392 | 11835 | dwarf_par_index = 1; |
e2c671ba | 11836 | |
d5b7b3ae | 11837 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
11838 | { |
11839 | if (mask & (1 << i)) | |
11840 | { | |
2c849145 JM |
11841 | reg = gen_rtx_REG (SImode, i); |
11842 | ||
e2c671ba | 11843 | XVECEXP (par, 0, 0) |
43cffd11 | 11844 | = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
11845 | gen_frame_mem (BLKmode, |
11846 | gen_rtx_PRE_DEC (BLKmode, | |
11847 | stack_pointer_rtx)), | |
43cffd11 | 11848 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 11849 | gen_rtvec (1, reg), |
9b598fa0 | 11850 | UNSPEC_PUSH_MULT)); |
2c849145 | 11851 | |
9b598fa0 RE |
11852 | if (i != PC_REGNUM) |
11853 | { | |
11854 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 11855 | gen_frame_mem (SImode, stack_pointer_rtx), |
9b598fa0 RE |
11856 | reg); |
11857 | RTX_FRAME_RELATED_P (tmp) = 1; | |
11858 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
11859 | dwarf_par_index++; | |
11860 | } | |
2c849145 | 11861 | |
e2c671ba RE |
11862 | break; |
11863 | } | |
11864 | } | |
11865 | ||
11866 | for (j = 1, i++; j < num_regs; i++) | |
11867 | { | |
11868 | if (mask & (1 << i)) | |
11869 | { | |
2c849145 JM |
11870 | reg = gen_rtx_REG (SImode, i); |
11871 | ||
11872 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
11873 | ||
9b598fa0 RE |
11874 | if (i != PC_REGNUM) |
11875 | { | |
31fa16b6 RE |
11876 | tmp |
11877 | = gen_rtx_SET (VOIDmode, | |
11878 | gen_frame_mem (SImode, | |
9b598fa0 RE |
11879 | plus_constant (stack_pointer_rtx, |
11880 | 4 * j)), | |
31fa16b6 | 11881 | reg); |
9b598fa0 RE |
11882 | RTX_FRAME_RELATED_P (tmp) = 1; |
11883 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
11884 | } | |
11885 | ||
e2c671ba RE |
11886 | j++; |
11887 | } | |
11888 | } | |
b111229a | 11889 | |
2c849145 | 11890 | par = emit_insn (par); |
f676971a | 11891 | |
d66437c5 | 11892 | tmp = gen_rtx_SET (VOIDmode, |
87e27392 | 11893 | stack_pointer_rtx, |
d66437c5 | 11894 | plus_constant (stack_pointer_rtx, -4 * num_regs)); |
87e27392 NC |
11895 | RTX_FRAME_RELATED_P (tmp) = 1; |
11896 | XVECEXP (dwarf, 0, 0) = tmp; | |
f676971a | 11897 | |
2c849145 JM |
11898 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, |
11899 | REG_NOTES (par)); | |
11900 | return par; | |
b111229a RE |
11901 | } |
11902 | ||
4f5dfed0 | 11903 | /* Calculate the size of the return value that is passed in registers. */ |
466e4b7a | 11904 | static unsigned |
4f5dfed0 JC |
11905 | arm_size_return_regs (void) |
11906 | { | |
11907 | enum machine_mode mode; | |
11908 | ||
38173d38 JH |
11909 | if (crtl->return_rtx != 0) |
11910 | mode = GET_MODE (crtl->return_rtx); | |
4f5dfed0 JC |
11911 | else |
11912 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
11913 | ||
11914 | return GET_MODE_SIZE (mode); | |
11915 | } | |
11916 | ||
2c849145 | 11917 | static rtx |
e32bac5b | 11918 | emit_sfm (int base_reg, int count) |
b111229a RE |
11919 | { |
11920 | rtx par; | |
2c849145 JM |
11921 | rtx dwarf; |
11922 | rtx tmp, reg; | |
b111229a RE |
11923 | int i; |
11924 | ||
43cffd11 | 11925 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
8ee6eb4e | 11926 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); |
2c849145 JM |
11927 | |
11928 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
11929 | |
11930 | XVECEXP (par, 0, 0) | |
f676971a | 11931 | = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
11932 | gen_frame_mem (BLKmode, |
11933 | gen_rtx_PRE_DEC (BLKmode, | |
11934 | stack_pointer_rtx)), | |
43cffd11 | 11935 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 11936 | gen_rtvec (1, reg), |
b15bca31 | 11937 | UNSPEC_PUSH_MULT)); |
f676971a | 11938 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 | 11939 | gen_frame_mem (XFmode, stack_pointer_rtx), reg); |
2c849145 | 11940 | RTX_FRAME_RELATED_P (tmp) = 1; |
f676971a EC |
11941 | XVECEXP (dwarf, 0, 1) = tmp; |
11942 | ||
b111229a | 11943 | for (i = 1; i < count; i++) |
2c849145 JM |
11944 | { |
11945 | reg = gen_rtx_REG (XFmode, base_reg++); | |
11946 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
11947 | ||
f676971a | 11948 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
11949 | gen_frame_mem (XFmode, |
11950 | plus_constant (stack_pointer_rtx, | |
11951 | i * 12)), | |
2c849145 JM |
11952 | reg); |
11953 | RTX_FRAME_RELATED_P (tmp) = 1; | |
f676971a | 11954 | XVECEXP (dwarf, 0, i + 1) = tmp; |
2c849145 | 11955 | } |
b111229a | 11956 | |
8ee6eb4e PB |
11957 | tmp = gen_rtx_SET (VOIDmode, |
11958 | stack_pointer_rtx, | |
d66437c5 RE |
11959 | plus_constant (stack_pointer_rtx, -12 * count)); |
11960 | ||
8ee6eb4e PB |
11961 | RTX_FRAME_RELATED_P (tmp) = 1; |
11962 | XVECEXP (dwarf, 0, 0) = tmp; | |
11963 | ||
2c849145 JM |
11964 | par = emit_insn (par); |
11965 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
11966 | REG_NOTES (par)); | |
11967 | return par; | |
e2c671ba RE |
11968 | } |
11969 | ||
9b66ebb1 | 11970 | |
3c7ad43e PB |
11971 | /* Return true if the current function needs to save/restore LR. */ |
11972 | ||
11973 | static bool | |
11974 | thumb_force_lr_save (void) | |
11975 | { | |
11976 | return !cfun->machine->lr_save_eliminated | |
11977 | && (!leaf_function_p () | |
11978 | || thumb_far_jump_used_p () | |
6fb5fa3c | 11979 | || df_regs_ever_live_p (LR_REGNUM)); |
3c7ad43e PB |
11980 | } |
11981 | ||
11982 | ||
095bb276 NC |
11983 | /* Compute the distance from register FROM to register TO. |
11984 | These can be the arg pointer (26), the soft frame pointer (25), | |
11985 | the stack pointer (13) or the hard frame pointer (11). | |
c9ca9b88 | 11986 | In thumb mode r7 is used as the soft frame pointer, if needed. |
095bb276 NC |
11987 | Typical stack layout looks like this: |
11988 | ||
11989 | old stack pointer -> | | | |
11990 | ---- | |
11991 | | | \ | |
11992 | | | saved arguments for | |
11993 | | | vararg functions | |
11994 | | | / | |
11995 | -- | |
11996 | hard FP & arg pointer -> | | \ | |
11997 | | | stack | |
11998 | | | frame | |
11999 | | | / | |
12000 | -- | |
12001 | | | \ | |
12002 | | | call saved | |
12003 | | | registers | |
12004 | soft frame pointer -> | | / | |
12005 | -- | |
12006 | | | \ | |
12007 | | | local | |
12008 | | | variables | |
2591db65 | 12009 | locals base pointer -> | | / |
095bb276 NC |
12010 | -- |
12011 | | | \ | |
12012 | | | outgoing | |
12013 | | | arguments | |
12014 | current stack pointer -> | | / | |
12015 | -- | |
12016 | ||
43aa4e05 | 12017 | For a given function some or all of these stack components |
095bb276 NC |
12018 | may not be needed, giving rise to the possibility of |
12019 | eliminating some of the registers. | |
12020 | ||
825dda42 | 12021 | The values returned by this function must reflect the behavior |
095bb276 NC |
12022 | of arm_expand_prologue() and arm_compute_save_reg_mask(). |
12023 | ||
12024 | The sign of the number returned reflects the direction of stack | |
12025 | growth, so the values are positive for all eliminations except | |
5848830f PB |
12026 | from the soft frame pointer to the hard frame pointer. |
12027 | ||
12028 | SFP may point just inside the local variables block to ensure correct | |
12029 | alignment. */ | |
12030 | ||
12031 | ||
12032 | /* Calculate stack offsets. These are used to calculate register elimination | |
954954d1 PB |
12033 | offsets and in prologue/epilogue code. Also calculates which registers |
12034 | should be saved. */ | |
5848830f PB |
12035 | |
12036 | static arm_stack_offsets * | |
12037 | arm_get_frame_offsets (void) | |
095bb276 | 12038 | { |
5848830f | 12039 | struct arm_stack_offsets *offsets; |
095bb276 | 12040 | unsigned long func_type; |
5848830f | 12041 | int leaf; |
5848830f | 12042 | int saved; |
954954d1 | 12043 | int core_saved; |
5848830f | 12044 | HOST_WIDE_INT frame_size; |
954954d1 | 12045 | int i; |
5848830f PB |
12046 | |
12047 | offsets = &cfun->machine->stack_offsets; | |
f676971a | 12048 | |
5848830f PB |
12049 | /* We need to know if we are a leaf function. Unfortunately, it |
12050 | is possible to be called after start_sequence has been called, | |
12051 | which causes get_insns to return the insns for the sequence, | |
12052 | not the function, which will cause leaf_function_p to return | |
12053 | the incorrect result. | |
095bb276 | 12054 | |
5848830f PB |
12055 | to know about leaf functions once reload has completed, and the |
12056 | frame size cannot be changed after that time, so we can safely | |
12057 | use the cached value. */ | |
12058 | ||
12059 | if (reload_completed) | |
12060 | return offsets; | |
12061 | ||
666c27b9 KH |
12062 | /* Initially this is the size of the local variables. It will translated |
12063 | into an offset once we have determined the size of preceding data. */ | |
5848830f PB |
12064 | frame_size = ROUND_UP_WORD (get_frame_size ()); |
12065 | ||
12066 | leaf = leaf_function_p (); | |
12067 | ||
12068 | /* Space for variadic functions. */ | |
38173d38 | 12069 | offsets->saved_args = crtl->args.pretend_args_size; |
5848830f | 12070 | |
5b3e6663 | 12071 | /* In Thumb mode this is incorrect, but never used. */ |
5848830f PB |
12072 | offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0); |
12073 | ||
5b3e6663 | 12074 | if (TARGET_32BIT) |
095bb276 | 12075 | { |
5848830f | 12076 | unsigned int regno; |
ef7112de | 12077 | |
954954d1 PB |
12078 | offsets->saved_regs_mask = arm_compute_save_reg_mask (); |
12079 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
12080 | saved = core_saved; | |
5a9335ef | 12081 | |
5848830f PB |
12082 | /* We know that SP will be doubleword aligned on entry, and we must |
12083 | preserve that condition at any subroutine call. We also require the | |
12084 | soft frame pointer to be doubleword aligned. */ | |
12085 | ||
12086 | if (TARGET_REALLY_IWMMXT) | |
9b66ebb1 | 12087 | { |
5848830f PB |
12088 | /* Check for the call-saved iWMMXt registers. */ |
12089 | for (regno = FIRST_IWMMXT_REGNUM; | |
12090 | regno <= LAST_IWMMXT_REGNUM; | |
12091 | regno++) | |
6fb5fa3c | 12092 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
12093 | saved += 8; |
12094 | } | |
12095 | ||
12096 | func_type = arm_current_func_type (); | |
12097 | if (! IS_VOLATILE (func_type)) | |
12098 | { | |
12099 | /* Space for saved FPA registers. */ | |
12100 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 12101 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
12102 | saved += 12; |
12103 | ||
12104 | /* Space for saved VFP registers. */ | |
12105 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
9728c9d1 | 12106 | saved += arm_get_vfp_saved_size (); |
9b66ebb1 | 12107 | } |
5848830f | 12108 | } |
5b3e6663 | 12109 | else /* TARGET_THUMB1 */ |
5848830f | 12110 | { |
954954d1 PB |
12111 | offsets->saved_regs_mask = thumb1_compute_save_reg_mask (); |
12112 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
12113 | saved = core_saved; | |
5848830f | 12114 | if (TARGET_BACKTRACE) |
57934c39 | 12115 | saved += 16; |
5848830f | 12116 | } |
9b66ebb1 | 12117 | |
5848830f PB |
12118 | /* Saved registers include the stack frame. */ |
12119 | offsets->saved_regs = offsets->saved_args + saved; | |
a2503645 | 12120 | offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE; |
5848830f PB |
12121 | /* A leaf function does not need any stack alignment if it has nothing |
12122 | on the stack. */ | |
12123 | if (leaf && frame_size == 0) | |
12124 | { | |
12125 | offsets->outgoing_args = offsets->soft_frame; | |
a3a531ec | 12126 | offsets->locals_base = offsets->soft_frame; |
5848830f PB |
12127 | return offsets; |
12128 | } | |
12129 | ||
12130 | /* Ensure SFP has the correct alignment. */ | |
12131 | if (ARM_DOUBLEWORD_ALIGN | |
12132 | && (offsets->soft_frame & 7)) | |
954954d1 PB |
12133 | { |
12134 | offsets->soft_frame += 4; | |
12135 | /* Try to align stack by pushing an extra reg. Don't bother doing this | |
12136 | when there is a stack frame as the alignment will be rolled into | |
12137 | the normal stack adjustment. */ | |
38173d38 | 12138 | if (frame_size + crtl->outgoing_args_size == 0) |
954954d1 PB |
12139 | { |
12140 | int reg = -1; | |
12141 | ||
12142 | for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++) | |
12143 | { | |
12144 | if ((offsets->saved_regs_mask & (1 << i)) == 0) | |
12145 | { | |
12146 | reg = i; | |
12147 | break; | |
12148 | } | |
12149 | } | |
12150 | ||
12151 | if (reg == -1 && arm_size_return_regs () <= 12 | |
e3b5732b | 12152 | && !crtl->tail_call_emit) |
954954d1 PB |
12153 | { |
12154 | /* Push/pop an argument register (r3) if all callee saved | |
12155 | registers are already being pushed. */ | |
12156 | reg = 3; | |
12157 | } | |
12158 | ||
12159 | if (reg != -1) | |
12160 | { | |
12161 | offsets->saved_regs += 4; | |
12162 | offsets->saved_regs_mask |= (1 << reg); | |
12163 | } | |
12164 | } | |
12165 | } | |
5848830f | 12166 | |
2591db65 RE |
12167 | offsets->locals_base = offsets->soft_frame + frame_size; |
12168 | offsets->outgoing_args = (offsets->locals_base | |
38173d38 | 12169 | + crtl->outgoing_args_size); |
5848830f PB |
12170 | |
12171 | if (ARM_DOUBLEWORD_ALIGN) | |
12172 | { | |
12173 | /* Ensure SP remains doubleword aligned. */ | |
12174 | if (offsets->outgoing_args & 7) | |
12175 | offsets->outgoing_args += 4; | |
e6d29d15 | 12176 | gcc_assert (!(offsets->outgoing_args & 7)); |
095bb276 NC |
12177 | } |
12178 | ||
5848830f PB |
12179 | return offsets; |
12180 | } | |
12181 | ||
12182 | ||
666c27b9 | 12183 | /* Calculate the relative offsets for the different stack pointers. Positive |
5848830f PB |
12184 | offsets are in the direction of stack growth. */ |
12185 | ||
b3f8d95d | 12186 | HOST_WIDE_INT |
5848830f PB |
12187 | arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) |
12188 | { | |
12189 | arm_stack_offsets *offsets; | |
12190 | ||
12191 | offsets = arm_get_frame_offsets (); | |
095bb276 | 12192 | |
095bb276 NC |
12193 | /* OK, now we have enough information to compute the distances. |
12194 | There must be an entry in these switch tables for each pair | |
12195 | of registers in ELIMINABLE_REGS, even if some of the entries | |
12196 | seem to be redundant or useless. */ | |
12197 | switch (from) | |
12198 | { | |
12199 | case ARG_POINTER_REGNUM: | |
12200 | switch (to) | |
12201 | { | |
12202 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
12203 | return 0; | |
12204 | ||
12205 | case FRAME_POINTER_REGNUM: | |
12206 | /* This is the reverse of the soft frame pointer | |
12207 | to hard frame pointer elimination below. */ | |
5848830f | 12208 | return offsets->soft_frame - offsets->saved_args; |
095bb276 NC |
12209 | |
12210 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
12211 | /* If there is no stack frame then the hard | |
12212 | frame pointer and the arg pointer coincide. */ | |
5848830f | 12213 | if (offsets->frame == offsets->saved_regs) |
095bb276 | 12214 | return 0; |
6de9cd9a DN |
12215 | /* FIXME: Not sure about this. Maybe we should always return 0 ? */ |
12216 | return (frame_pointer_needed | |
12217 | && cfun->static_chain_decl != NULL | |
12218 | && ! cfun->machine->uses_anonymous_args) ? 4 : 0; | |
095bb276 NC |
12219 | |
12220 | case STACK_POINTER_REGNUM: | |
12221 | /* If nothing has been pushed on the stack at all | |
12222 | then this will return -4. This *is* correct! */ | |
5848830f | 12223 | return offsets->outgoing_args - (offsets->saved_args + 4); |
095bb276 NC |
12224 | |
12225 | default: | |
e6d29d15 | 12226 | gcc_unreachable (); |
095bb276 | 12227 | } |
e6d29d15 | 12228 | gcc_unreachable (); |
095bb276 NC |
12229 | |
12230 | case FRAME_POINTER_REGNUM: | |
12231 | switch (to) | |
12232 | { | |
12233 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
12234 | return 0; | |
12235 | ||
12236 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
12237 | /* The hard frame pointer points to the top entry in the | |
12238 | stack frame. The soft frame pointer to the bottom entry | |
12239 | in the stack frame. If there is no stack frame at all, | |
12240 | then they are identical. */ | |
5848830f PB |
12241 | |
12242 | return offsets->frame - offsets->soft_frame; | |
095bb276 NC |
12243 | |
12244 | case STACK_POINTER_REGNUM: | |
5848830f | 12245 | return offsets->outgoing_args - offsets->soft_frame; |
095bb276 NC |
12246 | |
12247 | default: | |
e6d29d15 | 12248 | gcc_unreachable (); |
095bb276 | 12249 | } |
e6d29d15 | 12250 | gcc_unreachable (); |
095bb276 NC |
12251 | |
12252 | default: | |
12253 | /* You cannot eliminate from the stack pointer. | |
12254 | In theory you could eliminate from the hard frame | |
12255 | pointer to the stack pointer, but this will never | |
12256 | happen, since if a stack frame is not needed the | |
12257 | hard frame pointer will never be used. */ | |
e6d29d15 | 12258 | gcc_unreachable (); |
095bb276 NC |
12259 | } |
12260 | } | |
12261 | ||
0977774b | 12262 | |
7a085dce | 12263 | /* Emit RTL to save coprocessor registers on function entry. Returns the |
5b3e6663 PB |
12264 | number of bytes pushed. */ |
12265 | ||
12266 | static int | |
12267 | arm_save_coproc_regs(void) | |
12268 | { | |
12269 | int saved_size = 0; | |
12270 | unsigned reg; | |
12271 | unsigned start_reg; | |
12272 | rtx insn; | |
12273 | ||
12274 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) | |
6fb5fa3c | 12275 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
5b3e6663 PB |
12276 | { |
12277 | insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); | |
12278 | insn = gen_rtx_MEM (V2SImode, insn); | |
12279 | insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); | |
12280 | RTX_FRAME_RELATED_P (insn) = 1; | |
12281 | saved_size += 8; | |
12282 | } | |
12283 | ||
12284 | /* Save any floating point call-saved registers used by this | |
12285 | function. */ | |
12286 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
12287 | { | |
12288 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
6fb5fa3c | 12289 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 PB |
12290 | { |
12291 | insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); | |
12292 | insn = gen_rtx_MEM (XFmode, insn); | |
12293 | insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg)); | |
12294 | RTX_FRAME_RELATED_P (insn) = 1; | |
12295 | saved_size += 12; | |
12296 | } | |
12297 | } | |
12298 | else | |
12299 | { | |
12300 | start_reg = LAST_FPA_REGNUM; | |
12301 | ||
12302 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
12303 | { | |
6fb5fa3c | 12304 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 PB |
12305 | { |
12306 | if (start_reg - reg == 3) | |
12307 | { | |
12308 | insn = emit_sfm (reg, 4); | |
12309 | RTX_FRAME_RELATED_P (insn) = 1; | |
12310 | saved_size += 48; | |
12311 | start_reg = reg - 1; | |
12312 | } | |
12313 | } | |
12314 | else | |
12315 | { | |
12316 | if (start_reg != reg) | |
12317 | { | |
12318 | insn = emit_sfm (reg + 1, start_reg - reg); | |
12319 | RTX_FRAME_RELATED_P (insn) = 1; | |
12320 | saved_size += (start_reg - reg) * 12; | |
12321 | } | |
12322 | start_reg = reg - 1; | |
12323 | } | |
12324 | } | |
12325 | ||
12326 | if (start_reg != reg) | |
12327 | { | |
12328 | insn = emit_sfm (reg + 1, start_reg - reg); | |
12329 | saved_size += (start_reg - reg) * 12; | |
12330 | RTX_FRAME_RELATED_P (insn) = 1; | |
12331 | } | |
12332 | } | |
12333 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
12334 | { | |
12335 | start_reg = FIRST_VFP_REGNUM; | |
12336 | ||
12337 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
12338 | { | |
6fb5fa3c DB |
12339 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
12340 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
5b3e6663 PB |
12341 | { |
12342 | if (start_reg != reg) | |
12343 | saved_size += vfp_emit_fstmd (start_reg, | |
12344 | (reg - start_reg) / 2); | |
12345 | start_reg = reg + 2; | |
12346 | } | |
12347 | } | |
12348 | if (start_reg != reg) | |
12349 | saved_size += vfp_emit_fstmd (start_reg, | |
12350 | (reg - start_reg) / 2); | |
12351 | } | |
12352 | return saved_size; | |
12353 | } | |
12354 | ||
12355 | ||
12356 | /* Set the Thumb frame pointer from the stack pointer. */ | |
12357 | ||
12358 | static void | |
12359 | thumb_set_frame_pointer (arm_stack_offsets *offsets) | |
12360 | { | |
12361 | HOST_WIDE_INT amount; | |
12362 | rtx insn, dwarf; | |
12363 | ||
12364 | amount = offsets->outgoing_args - offsets->locals_base; | |
12365 | if (amount < 1024) | |
12366 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
12367 | stack_pointer_rtx, GEN_INT (amount))); | |
12368 | else | |
12369 | { | |
12370 | emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount))); | |
f5c630c3 PB |
12371 | /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1 |
12372 | expects the first two operands to be the same. */ | |
12373 | if (TARGET_THUMB2) | |
12374 | { | |
12375 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
12376 | stack_pointer_rtx, | |
12377 | hard_frame_pointer_rtx)); | |
12378 | } | |
12379 | else | |
12380 | { | |
12381 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
12382 | hard_frame_pointer_rtx, | |
12383 | stack_pointer_rtx)); | |
12384 | } | |
5b3e6663 PB |
12385 | dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, |
12386 | plus_constant (stack_pointer_rtx, amount)); | |
12387 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
12388 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
12389 | REG_NOTES (insn)); | |
12390 | } | |
12391 | ||
12392 | RTX_FRAME_RELATED_P (insn) = 1; | |
12393 | } | |
12394 | ||
12395 | /* Generate the prologue instructions for entry into an ARM or Thumb-2 | |
12396 | function. */ | |
e2c671ba | 12397 | void |
e32bac5b | 12398 | arm_expand_prologue (void) |
e2c671ba | 12399 | { |
6d3d9133 | 12400 | rtx amount; |
2c849145 | 12401 | rtx insn; |
68dfd979 | 12402 | rtx ip_rtx; |
6d3d9133 NC |
12403 | unsigned long live_regs_mask; |
12404 | unsigned long func_type; | |
68dfd979 | 12405 | int fp_offset = 0; |
095bb276 | 12406 | int saved_pretend_args = 0; |
5848830f | 12407 | int saved_regs = 0; |
b9705a21 | 12408 | unsigned HOST_WIDE_INT args_to_push; |
5848830f | 12409 | arm_stack_offsets *offsets; |
d3236b4d | 12410 | |
6d3d9133 | 12411 | func_type = arm_current_func_type (); |
e2c671ba | 12412 | |
31fdb4d5 | 12413 | /* Naked functions don't have prologues. */ |
6d3d9133 | 12414 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
12415 | return; |
12416 | ||
095bb276 | 12417 | /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ |
38173d38 | 12418 | args_to_push = crtl->args.pretend_args_size; |
f676971a | 12419 | |
6d3d9133 | 12420 | /* Compute which register we will have to save onto the stack. */ |
954954d1 PB |
12421 | offsets = arm_get_frame_offsets (); |
12422 | live_regs_mask = offsets->saved_regs_mask; | |
e2c671ba | 12423 | |
68dfd979 | 12424 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 12425 | |
5b3e6663 PB |
12426 | if (IS_STACKALIGN (func_type)) |
12427 | { | |
12428 | rtx dwarf; | |
12429 | rtx r0; | |
12430 | rtx r1; | |
12431 | /* Handle a word-aligned stack pointer. We generate the following: | |
12432 | ||
12433 | mov r0, sp | |
12434 | bic r1, r0, #7 | |
12435 | mov sp, r1 | |
12436 | <save and restore r0 in normal prologue/epilogue> | |
12437 | mov sp, r0 | |
12438 | bx lr | |
12439 | ||
12440 | The unwinder doesn't need to know about the stack realignment. | |
12441 | Just tell it we saved SP in r0. */ | |
12442 | gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0); | |
12443 | ||
12444 | r0 = gen_rtx_REG (SImode, 0); | |
12445 | r1 = gen_rtx_REG (SImode, 1); | |
12446 | dwarf = gen_rtx_UNSPEC (SImode, NULL_RTVEC, UNSPEC_STACK_ALIGN); | |
12447 | dwarf = gen_rtx_SET (VOIDmode, r0, dwarf); | |
12448 | insn = gen_movsi (r0, stack_pointer_rtx); | |
12449 | RTX_FRAME_RELATED_P (insn) = 1; | |
12450 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12451 | dwarf, REG_NOTES (insn)); | |
12452 | emit_insn (insn); | |
12453 | emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7))); | |
12454 | emit_insn (gen_movsi (stack_pointer_rtx, r1)); | |
12455 | } | |
12456 | ||
ec6237e4 PB |
12457 | /* For APCS frames, if IP register is clobbered |
12458 | when creating frame, save that register in a special | |
12459 | way. */ | |
12460 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) | |
e2c671ba | 12461 | { |
7b8b8ade NC |
12462 | if (IS_INTERRUPT (func_type)) |
12463 | { | |
12464 | /* Interrupt functions must not corrupt any registers. | |
12465 | Creating a frame pointer however, corrupts the IP | |
12466 | register, so we must push it first. */ | |
12467 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
121308d4 NC |
12468 | |
12469 | /* Do not set RTX_FRAME_RELATED_P on this insn. | |
12470 | The dwarf stack unwinding code only wants to see one | |
12471 | stack decrement per function, and this is not it. If | |
12472 | this instruction is labeled as being part of the frame | |
12473 | creation sequence then dwarf2out_frame_debug_expr will | |
e6d29d15 | 12474 | die when it encounters the assignment of IP to FP |
121308d4 NC |
12475 | later on, since the use of SP here establishes SP as |
12476 | the CFA register and not IP. | |
12477 | ||
12478 | Anyway this instruction is not really part of the stack | |
12479 | frame creation although it is part of the prologue. */ | |
7b8b8ade NC |
12480 | } |
12481 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
12482 | { |
12483 | /* The Static chain register is the same as the IP register | |
12484 | used as a scratch register during stack frame creation. | |
12485 | To get around this need to find somewhere to store IP | |
12486 | whilst the frame is being created. We try the following | |
12487 | places in order: | |
f676971a | 12488 | |
6d3d9133 | 12489 | 1. The last argument register. |
68dfd979 NC |
12490 | 2. A slot on the stack above the frame. (This only |
12491 | works if the function is not a varargs function). | |
095bb276 NC |
12492 | 3. Register r3, after pushing the argument registers |
12493 | onto the stack. | |
6d3d9133 | 12494 | |
34ce3d7b JM |
12495 | Note - we only need to tell the dwarf2 backend about the SP |
12496 | adjustment in the second variant; the static chain register | |
12497 | doesn't need to be unwound, as it doesn't contain a value | |
12498 | inherited from the caller. */ | |
d3236b4d | 12499 | |
6fb5fa3c | 12500 | if (df_regs_ever_live_p (3) == false) |
d66437c5 | 12501 | insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 12502 | else if (args_to_push == 0) |
68dfd979 | 12503 | { |
34ce3d7b | 12504 | rtx dwarf; |
34ce3d7b | 12505 | |
d66437c5 RE |
12506 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
12507 | insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx); | |
68dfd979 | 12508 | fp_offset = 4; |
34ce3d7b JM |
12509 | |
12510 | /* Just tell the dwarf backend that we adjusted SP. */ | |
12511 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
d66437c5 RE |
12512 | plus_constant (stack_pointer_rtx, |
12513 | -fp_offset)); | |
34ce3d7b JM |
12514 | RTX_FRAME_RELATED_P (insn) = 1; |
12515 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12516 | dwarf, REG_NOTES (insn)); | |
68dfd979 NC |
12517 | } |
12518 | else | |
095bb276 NC |
12519 | { |
12520 | /* Store the args on the stack. */ | |
3cb66fd7 | 12521 | if (cfun->machine->uses_anonymous_args) |
095bb276 NC |
12522 | insn = emit_multi_reg_push |
12523 | ((0xf0 >> (args_to_push / 4)) & 0xf); | |
12524 | else | |
12525 | insn = emit_insn | |
f676971a | 12526 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 NC |
12527 | GEN_INT (- args_to_push))); |
12528 | ||
12529 | RTX_FRAME_RELATED_P (insn) = 1; | |
12530 | ||
12531 | saved_pretend_args = 1; | |
12532 | fp_offset = args_to_push; | |
12533 | args_to_push = 0; | |
12534 | ||
12535 | /* Now reuse r3 to preserve IP. */ | |
d66437c5 | 12536 | emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 12537 | } |
68dfd979 NC |
12538 | } |
12539 | ||
d66437c5 RE |
12540 | insn = emit_set_insn (ip_rtx, |
12541 | plus_constant (stack_pointer_rtx, fp_offset)); | |
8e56560e | 12542 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
12543 | } |
12544 | ||
095bb276 | 12545 | if (args_to_push) |
e2c671ba | 12546 | { |
6d3d9133 | 12547 | /* Push the argument registers, or reserve space for them. */ |
3cb66fd7 | 12548 | if (cfun->machine->uses_anonymous_args) |
2c849145 | 12549 | insn = emit_multi_reg_push |
095bb276 | 12550 | ((0xf0 >> (args_to_push / 4)) & 0xf); |
e2c671ba | 12551 | else |
2c849145 | 12552 | insn = emit_insn |
f676971a | 12553 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 | 12554 | GEN_INT (- args_to_push))); |
2c849145 | 12555 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
12556 | } |
12557 | ||
06bea5aa | 12558 | /* If this is an interrupt service routine, and the link register |
ec6237e4 PB |
12559 | is going to be pushed, and we're not generating extra |
12560 | push of IP (needed when frame is needed and frame layout if apcs), | |
06bea5aa NC |
12561 | subtracting four from LR now will mean that the function return |
12562 | can be done with a single instruction. */ | |
3a7731fd | 12563 | if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) |
06bea5aa | 12564 | && (live_regs_mask & (1 << LR_REGNUM)) != 0 |
ec6237e4 | 12565 | && !(frame_pointer_needed && TARGET_APCS_FRAME) |
a15908a4 | 12566 | && TARGET_ARM) |
d66437c5 RE |
12567 | { |
12568 | rtx lr = gen_rtx_REG (SImode, LR_REGNUM); | |
12569 | ||
12570 | emit_set_insn (lr, plus_constant (lr, -4)); | |
12571 | } | |
3a7731fd | 12572 | |
e2c671ba RE |
12573 | if (live_regs_mask) |
12574 | { | |
5848830f | 12575 | saved_regs += bit_count (live_regs_mask) * 4; |
954954d1 PB |
12576 | if (optimize_size && !frame_pointer_needed |
12577 | && saved_regs == offsets->saved_regs - offsets->saved_args) | |
12578 | { | |
12579 | /* If no coprocessor registers are being pushed and we don't have | |
12580 | to worry about a frame pointer then push extra registers to | |
12581 | create the stack frame. This is done is a way that does not | |
12582 | alter the frame layout, so is independent of the epilogue. */ | |
12583 | int n; | |
12584 | int frame; | |
12585 | n = 0; | |
12586 | while (n < 8 && (live_regs_mask & (1 << n)) == 0) | |
12587 | n++; | |
12588 | frame = offsets->outgoing_args - (offsets->saved_args + saved_regs); | |
12589 | if (frame && n * 4 >= frame) | |
12590 | { | |
12591 | n = frame / 4; | |
12592 | live_regs_mask |= (1 << n) - 1; | |
12593 | saved_regs += frame; | |
12594 | } | |
12595 | } | |
12596 | insn = emit_multi_reg_push (live_regs_mask); | |
2c849145 | 12597 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba | 12598 | } |
d5b7b3ae | 12599 | |
6d3d9133 | 12600 | if (! IS_VOLATILE (func_type)) |
5b3e6663 | 12601 | saved_regs += arm_save_coproc_regs (); |
b111229a | 12602 | |
5b3e6663 PB |
12603 | if (frame_pointer_needed && TARGET_ARM) |
12604 | { | |
12605 | /* Create the new frame pointer. */ | |
ec6237e4 | 12606 | if (TARGET_APCS_FRAME) |
9b66ebb1 | 12607 | { |
5b3e6663 PB |
12608 | insn = GEN_INT (-(4 + args_to_push + fp_offset)); |
12609 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); | |
12610 | RTX_FRAME_RELATED_P (insn) = 1; | |
9b66ebb1 | 12611 | |
5b3e6663 | 12612 | if (IS_NESTED (func_type)) |
9b66ebb1 | 12613 | { |
5b3e6663 | 12614 | /* Recover the static chain register. */ |
6fb5fa3c | 12615 | if (!df_regs_ever_live_p (3) |
5b3e6663 PB |
12616 | || saved_pretend_args) |
12617 | insn = gen_rtx_REG (SImode, 3); | |
38173d38 | 12618 | else /* if (crtl->args.pretend_args_size == 0) */ |
9b66ebb1 | 12619 | { |
5b3e6663 PB |
12620 | insn = plus_constant (hard_frame_pointer_rtx, 4); |
12621 | insn = gen_frame_mem (SImode, insn); | |
9b66ebb1 | 12622 | } |
5b3e6663 PB |
12623 | emit_set_insn (ip_rtx, insn); |
12624 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
12625 | emit_insn (gen_prologue_use (ip_rtx)); | |
9b66ebb1 | 12626 | } |
68dfd979 | 12627 | } |
ec6237e4 PB |
12628 | else |
12629 | { | |
12630 | insn = GEN_INT (saved_regs - 4); | |
12631 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
12632 | stack_pointer_rtx, insn)); | |
12633 | RTX_FRAME_RELATED_P (insn) = 1; | |
12634 | } | |
2c849145 | 12635 | } |
e2c671ba | 12636 | |
5848830f | 12637 | if (offsets->outgoing_args != offsets->saved_args + saved_regs) |
e2c671ba | 12638 | { |
745b9093 JM |
12639 | /* This add can produce multiple insns for a large constant, so we |
12640 | need to get tricky. */ | |
12641 | rtx last = get_last_insn (); | |
5848830f PB |
12642 | |
12643 | amount = GEN_INT (offsets->saved_args + saved_regs | |
12644 | - offsets->outgoing_args); | |
12645 | ||
2c849145 JM |
12646 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
12647 | amount)); | |
745b9093 JM |
12648 | do |
12649 | { | |
12650 | last = last ? NEXT_INSN (last) : get_insns (); | |
12651 | RTX_FRAME_RELATED_P (last) = 1; | |
12652 | } | |
12653 | while (last != insn); | |
e04c2d6c RE |
12654 | |
12655 | /* If the frame pointer is needed, emit a special barrier that | |
12656 | will prevent the scheduler from moving stores to the frame | |
12657 | before the stack adjustment. */ | |
12658 | if (frame_pointer_needed) | |
3894f59e RE |
12659 | insn = emit_insn (gen_stack_tie (stack_pointer_rtx, |
12660 | hard_frame_pointer_rtx)); | |
e2c671ba RE |
12661 | } |
12662 | ||
876f13b0 | 12663 | |
5b3e6663 PB |
12664 | if (frame_pointer_needed && TARGET_THUMB2) |
12665 | thumb_set_frame_pointer (offsets); | |
12666 | ||
020a4035 | 12667 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
5b3e6663 PB |
12668 | { |
12669 | unsigned long mask; | |
12670 | ||
12671 | mask = live_regs_mask; | |
12672 | mask &= THUMB2_WORK_REGS; | |
12673 | if (!IS_NESTED (func_type)) | |
12674 | mask |= (1 << IP_REGNUM); | |
12675 | arm_load_pic_register (mask); | |
12676 | } | |
876f13b0 | 12677 | |
e2c671ba | 12678 | /* If we are profiling, make sure no instructions are scheduled before |
f5a1b0d2 | 12679 | the call to mcount. Similarly if the user has requested no |
74d9c39f DJ |
12680 | scheduling in the prolog. Similarly if we want non-call exceptions |
12681 | using the EABI unwinder, to prevent faulting instructions from being | |
12682 | swapped with a stack adjustment. */ | |
e3b5732b | 12683 | if (crtl->profile || !TARGET_SCHED_PROLOG |
74d9c39f | 12684 | || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) |
e2c671ba | 12685 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
12686 | |
12687 | /* If the link register is being kept alive, with the return address in it, | |
12688 | then make sure that it does not get reused by the ce2 pass. */ | |
12689 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
6fb5fa3c | 12690 | cfun->machine->lr_save_eliminated = 1; |
e2c671ba | 12691 | } |
cce8749e | 12692 | \f |
5b3e6663 PB |
12693 | /* Print condition code to STREAM. Helper function for arm_print_operand. */ |
12694 | static void | |
12695 | arm_print_condition (FILE *stream) | |
12696 | { | |
12697 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
12698 | { | |
12699 | /* Branch conversion is not implemented for Thumb-2. */ | |
12700 | if (TARGET_THUMB) | |
12701 | { | |
12702 | output_operand_lossage ("predicated Thumb instruction"); | |
12703 | return; | |
12704 | } | |
12705 | if (current_insn_predicate != NULL) | |
12706 | { | |
12707 | output_operand_lossage | |
12708 | ("predicated instruction in conditional sequence"); | |
12709 | return; | |
12710 | } | |
12711 | ||
12712 | fputs (arm_condition_codes[arm_current_cc], stream); | |
12713 | } | |
12714 | else if (current_insn_predicate) | |
12715 | { | |
12716 | enum arm_cond_code code; | |
12717 | ||
12718 | if (TARGET_THUMB1) | |
12719 | { | |
12720 | output_operand_lossage ("predicated Thumb instruction"); | |
12721 | return; | |
12722 | } | |
12723 | ||
12724 | code = get_arm_condition_code (current_insn_predicate); | |
12725 | fputs (arm_condition_codes[code], stream); | |
12726 | } | |
12727 | } | |
12728 | ||
12729 | ||
9997d19d RE |
12730 | /* If CODE is 'd', then the X is a condition operand and the instruction |
12731 | should only be executed if the condition is true. | |
ddd5a7c1 | 12732 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
12733 | should only be executed if the condition is false: however, if the mode |
12734 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
12735 | do this because in these circumstances !GE does not necessarily imply LT; | |
12736 | in these cases the instruction pattern will take care to make sure that | |
12737 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 12738 | doing this instruction unconditionally. |
9997d19d RE |
12739 | If CODE is 'N' then X is a floating point operand that must be negated |
12740 | before output. | |
12741 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
12742 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
9997d19d | 12743 | void |
e32bac5b | 12744 | arm_print_operand (FILE *stream, rtx x, int code) |
9997d19d RE |
12745 | { |
12746 | switch (code) | |
12747 | { | |
12748 | case '@': | |
f3139301 | 12749 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
12750 | return; |
12751 | ||
d5b7b3ae RE |
12752 | case '_': |
12753 | fputs (user_label_prefix, stream); | |
12754 | return; | |
f676971a | 12755 | |
9997d19d | 12756 | case '|': |
f3139301 | 12757 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
12758 | return; |
12759 | ||
12760 | case '?': | |
5b3e6663 PB |
12761 | arm_print_condition (stream); |
12762 | return; | |
cca0a211 | 12763 | |
5b3e6663 PB |
12764 | case '(': |
12765 | /* Nothing in unified syntax, otherwise the current condition code. */ | |
12766 | if (!TARGET_UNIFIED_ASM) | |
12767 | arm_print_condition (stream); | |
12768 | break; | |
12769 | ||
12770 | case ')': | |
12771 | /* The current condition code in unified syntax, otherwise nothing. */ | |
12772 | if (TARGET_UNIFIED_ASM) | |
12773 | arm_print_condition (stream); | |
12774 | break; | |
12775 | ||
12776 | case '.': | |
12777 | /* The current condition code for a condition code setting instruction. | |
7a085dce | 12778 | Preceded by 's' in unified syntax, otherwise followed by 's'. */ |
5b3e6663 PB |
12779 | if (TARGET_UNIFIED_ASM) |
12780 | { | |
12781 | fputc('s', stream); | |
12782 | arm_print_condition (stream); | |
cca0a211 | 12783 | } |
5b3e6663 | 12784 | else |
cca0a211 | 12785 | { |
5b3e6663 PB |
12786 | arm_print_condition (stream); |
12787 | fputc('s', stream); | |
cca0a211 | 12788 | } |
9997d19d RE |
12789 | return; |
12790 | ||
5b3e6663 PB |
12791 | case '!': |
12792 | /* If the instruction is conditionally executed then print | |
12793 | the current condition code, otherwise print 's'. */ | |
12794 | gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM); | |
12795 | if (current_insn_predicate) | |
12796 | arm_print_condition (stream); | |
12797 | else | |
12798 | fputc('s', stream); | |
12799 | break; | |
12800 | ||
88f77cba | 12801 | /* %# is a "break" sequence. It doesn't output anything, but is used to |
cea618ac | 12802 | separate e.g. operand numbers from following text, if that text consists |
88f77cba JB |
12803 | of further digits which we don't want to be part of the operand |
12804 | number. */ | |
12805 | case '#': | |
12806 | return; | |
12807 | ||
9997d19d RE |
12808 | case 'N': |
12809 | { | |
12810 | REAL_VALUE_TYPE r; | |
12811 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
12812 | r = REAL_VALUE_NEGATE (r); | |
12813 | fprintf (stream, "%s", fp_const_from_val (&r)); | |
12814 | } | |
12815 | return; | |
12816 | ||
88f77cba JB |
12817 | /* An integer without a preceding # sign. */ |
12818 | case 'c': | |
12819 | gcc_assert (GET_CODE (x) == CONST_INT); | |
12820 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
12821 | return; | |
12822 | ||
9997d19d RE |
12823 | case 'B': |
12824 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
12825 | { |
12826 | HOST_WIDE_INT val; | |
5895f793 | 12827 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 12828 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 12829 | } |
9997d19d RE |
12830 | else |
12831 | { | |
12832 | putc ('~', stream); | |
12833 | output_addr_const (stream, x); | |
12834 | } | |
12835 | return; | |
12836 | ||
5b3e6663 PB |
12837 | case 'L': |
12838 | /* The low 16 bits of an immediate constant. */ | |
12839 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff); | |
12840 | return; | |
12841 | ||
9997d19d RE |
12842 | case 'i': |
12843 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
12844 | return; | |
12845 | ||
9b6b54e2 NC |
12846 | /* Truncate Cirrus shift counts. */ |
12847 | case 's': | |
12848 | if (GET_CODE (x) == CONST_INT) | |
12849 | { | |
12850 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); | |
12851 | return; | |
12852 | } | |
12853 | arm_print_operand (stream, x, 0); | |
12854 | return; | |
12855 | ||
9997d19d RE |
12856 | case 'I': |
12857 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
12858 | return; | |
12859 | ||
12860 | case 'S': | |
12861 | { | |
12862 | HOST_WIDE_INT val; | |
beed32b8 RE |
12863 | const char *shift; |
12864 | ||
12865 | if (!shift_operator (x, SImode)) | |
12866 | { | |
12867 | output_operand_lossage ("invalid shift operand"); | |
12868 | break; | |
12869 | } | |
12870 | ||
12871 | shift = shift_op (x, &val); | |
9997d19d | 12872 | |
e2c671ba RE |
12873 | if (shift) |
12874 | { | |
beed32b8 | 12875 | fprintf (stream, ", %s ", shift); |
e2c671ba RE |
12876 | if (val == -1) |
12877 | arm_print_operand (stream, XEXP (x, 1), 0); | |
12878 | else | |
4a0a75dd | 12879 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); |
e2c671ba | 12880 | } |
9997d19d RE |
12881 | } |
12882 | return; | |
12883 | ||
d5b7b3ae | 12884 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
f676971a | 12885 | |
d5b7b3ae RE |
12886 | In a pair of registers containing a DI or DF value the 'Q' |
12887 | operand returns the register number of the register containing | |
093354e0 | 12888 | the least significant part of the value. The 'R' operand returns |
d5b7b3ae RE |
12889 | the register number of the register containing the most |
12890 | significant part of the value. | |
f676971a | 12891 | |
d5b7b3ae RE |
12892 | The 'H' operand returns the higher of the two register numbers. |
12893 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
093354e0 | 12894 | same as the 'Q' operand, since the most significant part of the |
d5b7b3ae RE |
12895 | value is held in the lower number register. The reverse is true |
12896 | on systems where WORDS_BIG_ENDIAN is false. | |
f676971a | 12897 | |
d5b7b3ae RE |
12898 | The purpose of these operands is to distinguish between cases |
12899 | where the endian-ness of the values is important (for example | |
12900 | when they are added together), and cases where the endian-ness | |
12901 | is irrelevant, but the order of register operations is important. | |
12902 | For example when loading a value from memory into a register | |
12903 | pair, the endian-ness does not matter. Provided that the value | |
12904 | from the lower memory address is put into the lower numbered | |
12905 | register, and the value from the higher address is put into the | |
12906 | higher numbered register, the load will work regardless of whether | |
12907 | the value being loaded is big-wordian or little-wordian. The | |
12908 | order of the two register loads can matter however, if the address | |
12909 | of the memory location is actually held in one of the registers | |
12910 | being overwritten by the load. */ | |
c1c2bc04 | 12911 | case 'Q': |
22de4c3d RE |
12912 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
12913 | { | |
12914 | output_operand_lossage ("invalid operand for code '%c'", code); | |
12915 | return; | |
12916 | } | |
12917 | ||
d5b7b3ae | 12918 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
12919 | return; |
12920 | ||
9997d19d | 12921 | case 'R': |
22de4c3d RE |
12922 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
12923 | { | |
12924 | output_operand_lossage ("invalid operand for code '%c'", code); | |
12925 | return; | |
12926 | } | |
12927 | ||
d5b7b3ae RE |
12928 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
12929 | return; | |
12930 | ||
12931 | case 'H': | |
22de4c3d RE |
12932 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
12933 | { | |
12934 | output_operand_lossage ("invalid operand for code '%c'", code); | |
12935 | return; | |
12936 | } | |
12937 | ||
d5b7b3ae | 12938 | asm_fprintf (stream, "%r", REGNO (x) + 1); |
9997d19d RE |
12939 | return; |
12940 | ||
88f77cba JB |
12941 | case 'J': |
12942 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
12943 | { | |
12944 | output_operand_lossage ("invalid operand for code '%c'", code); | |
12945 | return; | |
12946 | } | |
12947 | ||
12948 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2)); | |
12949 | return; | |
12950 | ||
12951 | case 'K': | |
12952 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
12953 | { | |
12954 | output_operand_lossage ("invalid operand for code '%c'", code); | |
12955 | return; | |
12956 | } | |
12957 | ||
12958 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3)); | |
12959 | return; | |
12960 | ||
9997d19d | 12961 | case 'm': |
f676971a | 12962 | asm_fprintf (stream, "%r", |
d5b7b3ae RE |
12963 | GET_CODE (XEXP (x, 0)) == REG |
12964 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
12965 | return; |
12966 | ||
12967 | case 'M': | |
dd18ae56 | 12968 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae | 12969 | REGNO (x), |
e9d7b180 | 12970 | REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); |
9997d19d RE |
12971 | return; |
12972 | ||
88f77cba JB |
12973 | /* Like 'M', but writing doubleword vector registers, for use by Neon |
12974 | insns. */ | |
12975 | case 'h': | |
12976 | { | |
12977 | int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2; | |
12978 | int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2; | |
12979 | if (numregs == 1) | |
12980 | asm_fprintf (stream, "{d%d}", regno); | |
12981 | else | |
12982 | asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1); | |
12983 | } | |
12984 | return; | |
12985 | ||
9997d19d | 12986 | case 'd': |
64e92a26 RE |
12987 | /* CONST_TRUE_RTX means always -- that's the default. */ |
12988 | if (x == const_true_rtx) | |
d5b7b3ae | 12989 | return; |
f676971a | 12990 | |
22de4c3d RE |
12991 | if (!COMPARISON_P (x)) |
12992 | { | |
12993 | output_operand_lossage ("invalid operand for code '%c'", code); | |
12994 | return; | |
12995 | } | |
12996 | ||
defc0463 RE |
12997 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
12998 | stream); | |
9997d19d RE |
12999 | return; |
13000 | ||
13001 | case 'D': | |
112cdef5 | 13002 | /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever |
64e92a26 RE |
13003 | want to do that. */ |
13004 | if (x == const_true_rtx) | |
22de4c3d | 13005 | { |
4dad0aca | 13006 | output_operand_lossage ("instruction never executed"); |
22de4c3d RE |
13007 | return; |
13008 | } | |
13009 | if (!COMPARISON_P (x)) | |
13010 | { | |
13011 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13012 | return; | |
13013 | } | |
d5b7b3ae | 13014 | |
defc0463 RE |
13015 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE |
13016 | (get_arm_condition_code (x))], | |
13017 | stream); | |
9997d19d RE |
13018 | return; |
13019 | ||
9b6b54e2 NC |
13020 | /* Cirrus registers can be accessed in a variety of ways: |
13021 | single floating point (f) | |
13022 | double floating point (d) | |
13023 | 32bit integer (fx) | |
13024 | 64bit integer (dx). */ | |
13025 | case 'W': /* Cirrus register in F mode. */ | |
13026 | case 'X': /* Cirrus register in D mode. */ | |
13027 | case 'Y': /* Cirrus register in FX mode. */ | |
13028 | case 'Z': /* Cirrus register in DX mode. */ | |
e6d29d15 NS |
13029 | gcc_assert (GET_CODE (x) == REG |
13030 | && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS); | |
9b6b54e2 NC |
13031 | |
13032 | fprintf (stream, "mv%s%s", | |
13033 | code == 'W' ? "f" | |
13034 | : code == 'X' ? "d" | |
13035 | : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); | |
13036 | ||
13037 | return; | |
13038 | ||
13039 | /* Print cirrus register in the mode specified by the register's mode. */ | |
13040 | case 'V': | |
13041 | { | |
13042 | int mode = GET_MODE (x); | |
13043 | ||
13044 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
22de4c3d RE |
13045 | { |
13046 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13047 | return; | |
13048 | } | |
9b6b54e2 NC |
13049 | |
13050 | fprintf (stream, "mv%s%s", | |
13051 | mode == DFmode ? "d" | |
13052 | : mode == SImode ? "fx" | |
13053 | : mode == DImode ? "dx" | |
13054 | : "f", reg_names[REGNO (x)] + 2); | |
13055 | ||
13056 | return; | |
13057 | } | |
13058 | ||
5a9335ef NC |
13059 | case 'U': |
13060 | if (GET_CODE (x) != REG | |
13061 | || REGNO (x) < FIRST_IWMMXT_GR_REGNUM | |
13062 | || REGNO (x) > LAST_IWMMXT_GR_REGNUM) | |
13063 | /* Bad value for wCG register number. */ | |
22de4c3d RE |
13064 | { |
13065 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13066 | return; | |
13067 | } | |
13068 | ||
5a9335ef NC |
13069 | else |
13070 | fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); | |
13071 | return; | |
13072 | ||
13073 | /* Print an iWMMXt control register name. */ | |
13074 | case 'w': | |
13075 | if (GET_CODE (x) != CONST_INT | |
13076 | || INTVAL (x) < 0 | |
13077 | || INTVAL (x) >= 16) | |
13078 | /* Bad value for wC register number. */ | |
22de4c3d RE |
13079 | { |
13080 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13081 | return; | |
13082 | } | |
13083 | ||
5a9335ef NC |
13084 | else |
13085 | { | |
13086 | static const char * wc_reg_names [16] = | |
13087 | { | |
13088 | "wCID", "wCon", "wCSSF", "wCASF", | |
13089 | "wC4", "wC5", "wC6", "wC7", | |
13090 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", | |
13091 | "wC12", "wC13", "wC14", "wC15" | |
13092 | }; | |
f676971a | 13093 | |
5a9335ef NC |
13094 | fprintf (stream, wc_reg_names [INTVAL (x)]); |
13095 | } | |
13096 | return; | |
13097 | ||
88f77cba | 13098 | /* Print a VFP/Neon double precision or quad precision register name. */ |
9b66ebb1 | 13099 | case 'P': |
88f77cba | 13100 | case 'q': |
9b66ebb1 PB |
13101 | { |
13102 | int mode = GET_MODE (x); | |
88f77cba JB |
13103 | int is_quad = (code == 'q'); |
13104 | int regno; | |
9b66ebb1 | 13105 | |
88f77cba | 13106 | if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8)) |
22de4c3d RE |
13107 | { |
13108 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13109 | return; | |
13110 | } | |
9b66ebb1 PB |
13111 | |
13112 | if (GET_CODE (x) != REG | |
13113 | || !IS_VFP_REGNUM (REGNO (x))) | |
22de4c3d RE |
13114 | { |
13115 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13116 | return; | |
13117 | } | |
9b66ebb1 | 13118 | |
88f77cba JB |
13119 | regno = REGNO (x); |
13120 | if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno)) | |
13121 | || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno))) | |
22de4c3d RE |
13122 | { |
13123 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13124 | return; | |
13125 | } | |
9b66ebb1 | 13126 | |
88f77cba JB |
13127 | fprintf (stream, "%c%d", is_quad ? 'q' : 'd', |
13128 | (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1)); | |
13129 | } | |
13130 | return; | |
13131 | ||
13132 | /* These two codes print the low/high doubleword register of a Neon quad | |
13133 | register, respectively. For pair-structure types, can also print | |
13134 | low/high quadword registers. */ | |
13135 | case 'e': | |
13136 | case 'f': | |
13137 | { | |
13138 | int mode = GET_MODE (x); | |
13139 | int regno; | |
13140 | ||
13141 | if ((GET_MODE_SIZE (mode) != 16 | |
13142 | && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG) | |
13143 | { | |
13144 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13145 | return; | |
13146 | } | |
13147 | ||
13148 | regno = REGNO (x); | |
13149 | if (!NEON_REGNO_OK_FOR_QUAD (regno)) | |
13150 | { | |
13151 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13152 | return; | |
13153 | } | |
13154 | ||
13155 | if (GET_MODE_SIZE (mode) == 16) | |
13156 | fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1) | |
13157 | + (code == 'f' ? 1 : 0)); | |
13158 | else | |
13159 | fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2) | |
13160 | + (code == 'f' ? 1 : 0)); | |
9b66ebb1 PB |
13161 | } |
13162 | return; | |
13163 | ||
f1adb0a9 JB |
13164 | /* Print a VFPv3 floating-point constant, represented as an integer |
13165 | index. */ | |
13166 | case 'G': | |
13167 | { | |
13168 | int index = vfp3_const_double_index (x); | |
13169 | gcc_assert (index != -1); | |
13170 | fprintf (stream, "%d", index); | |
13171 | } | |
13172 | return; | |
13173 | ||
88f77cba JB |
13174 | /* Print bits representing opcode features for Neon. |
13175 | ||
13176 | Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed | |
13177 | and polynomials as unsigned. | |
13178 | ||
13179 | Bit 1 is 1 for floats and polynomials, 0 for ordinary integers. | |
13180 | ||
13181 | Bit 2 is 1 for rounding functions, 0 otherwise. */ | |
13182 | ||
13183 | /* Identify the type as 's', 'u', 'p' or 'f'. */ | |
13184 | case 'T': | |
13185 | { | |
13186 | HOST_WIDE_INT bits = INTVAL (x); | |
13187 | fputc ("uspf"[bits & 3], stream); | |
13188 | } | |
13189 | return; | |
13190 | ||
13191 | /* Likewise, but signed and unsigned integers are both 'i'. */ | |
13192 | case 'F': | |
13193 | { | |
13194 | HOST_WIDE_INT bits = INTVAL (x); | |
13195 | fputc ("iipf"[bits & 3], stream); | |
13196 | } | |
13197 | return; | |
13198 | ||
13199 | /* As for 'T', but emit 'u' instead of 'p'. */ | |
13200 | case 't': | |
13201 | { | |
13202 | HOST_WIDE_INT bits = INTVAL (x); | |
13203 | fputc ("usuf"[bits & 3], stream); | |
13204 | } | |
13205 | return; | |
13206 | ||
13207 | /* Bit 2: rounding (vs none). */ | |
13208 | case 'O': | |
13209 | { | |
13210 | HOST_WIDE_INT bits = INTVAL (x); | |
13211 | fputs ((bits & 4) != 0 ? "r" : "", stream); | |
13212 | } | |
13213 | return; | |
13214 | ||
9997d19d RE |
13215 | default: |
13216 | if (x == 0) | |
22de4c3d RE |
13217 | { |
13218 | output_operand_lossage ("missing operand"); | |
13219 | return; | |
13220 | } | |
9997d19d | 13221 | |
e6d29d15 | 13222 | switch (GET_CODE (x)) |
9997d19d | 13223 | { |
e6d29d15 NS |
13224 | case REG: |
13225 | asm_fprintf (stream, "%r", REGNO (x)); | |
13226 | break; | |
13227 | ||
13228 | case MEM: | |
9997d19d RE |
13229 | output_memory_reference_mode = GET_MODE (x); |
13230 | output_address (XEXP (x, 0)); | |
e6d29d15 NS |
13231 | break; |
13232 | ||
13233 | case CONST_DOUBLE: | |
88f77cba JB |
13234 | if (TARGET_NEON) |
13235 | { | |
13236 | char fpstr[20]; | |
13237 | real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x), | |
13238 | sizeof (fpstr), 0, 1); | |
13239 | fprintf (stream, "#%s", fpstr); | |
13240 | } | |
13241 | else | |
13242 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
e6d29d15 NS |
13243 | break; |
13244 | ||
13245 | default: | |
13246 | gcc_assert (GET_CODE (x) != NEG); | |
9997d19d RE |
13247 | fputc ('#', stream); |
13248 | output_addr_const (stream, x); | |
e6d29d15 | 13249 | break; |
9997d19d RE |
13250 | } |
13251 | } | |
13252 | } | |
cce8749e | 13253 | \f |
301d03af RS |
13254 | /* Target hook for assembling integer objects. The ARM version needs to |
13255 | handle word-sized values specially. */ | |
301d03af | 13256 | static bool |
e32bac5b | 13257 | arm_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 13258 | { |
88f77cba JB |
13259 | enum machine_mode mode; |
13260 | ||
301d03af RS |
13261 | if (size == UNITS_PER_WORD && aligned_p) |
13262 | { | |
13263 | fputs ("\t.word\t", asm_out_file); | |
13264 | output_addr_const (asm_out_file, x); | |
13265 | ||
13266 | /* Mark symbols as position independent. We only do this in the | |
d6b4baa4 | 13267 | .text segment, not in the .data segment. */ |
301d03af RS |
13268 | if (NEED_GOT_RELOC && flag_pic && making_const_table && |
13269 | (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) | |
13270 | { | |
9403b7f7 RS |
13271 | /* See legitimize_pic_address for an explanation of the |
13272 | TARGET_VXWORKS_RTP check. */ | |
13273 | if (TARGET_VXWORKS_RTP | |
13274 | || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))) | |
301d03af | 13275 | fputs ("(GOT)", asm_out_file); |
9403b7f7 RS |
13276 | else |
13277 | fputs ("(GOTOFF)", asm_out_file); | |
301d03af RS |
13278 | } |
13279 | fputc ('\n', asm_out_file); | |
13280 | return true; | |
13281 | } | |
1d6e90ac | 13282 | |
88f77cba JB |
13283 | mode = GET_MODE (x); |
13284 | ||
13285 | if (arm_vector_mode_supported_p (mode)) | |
5a9335ef NC |
13286 | { |
13287 | int i, units; | |
88f77cba | 13288 | unsigned int invmask = 0, parts_per_word; |
5a9335ef | 13289 | |
e6d29d15 | 13290 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
13291 | |
13292 | units = CONST_VECTOR_NUNITS (x); | |
88f77cba | 13293 | size = GET_MODE_SIZE (GET_MODE_INNER (mode)); |
5a9335ef | 13294 | |
88f77cba JB |
13295 | /* For big-endian Neon vectors, we must permute the vector to the form |
13296 | which, when loaded by a VLDR or VLDM instruction, will give a vector | |
13297 | with the elements in the right order. */ | |
13298 | if (TARGET_NEON && WORDS_BIG_ENDIAN) | |
13299 | { | |
13300 | parts_per_word = UNITS_PER_WORD / size; | |
13301 | /* FIXME: This might be wrong for 64-bit vector elements, but we don't | |
13302 | support those anywhere yet. */ | |
13303 | invmask = (parts_per_word == 0) ? 0 : (1 << (parts_per_word - 1)) - 1; | |
13304 | } | |
5a9335ef | 13305 | |
88f77cba JB |
13306 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) |
13307 | for (i = 0; i < units; i++) | |
13308 | { | |
13309 | rtx elt = CONST_VECTOR_ELT (x, i ^ invmask); | |
13310 | assemble_integer | |
13311 | (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); | |
13312 | } | |
13313 | else | |
13314 | for (i = 0; i < units; i++) | |
13315 | { | |
13316 | rtx elt = CONST_VECTOR_ELT (x, i); | |
13317 | REAL_VALUE_TYPE rval; | |
5a9335ef | 13318 | |
88f77cba JB |
13319 | REAL_VALUE_FROM_CONST_DOUBLE (rval, elt); |
13320 | ||
13321 | assemble_real | |
13322 | (rval, GET_MODE_INNER (mode), | |
13323 | i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT); | |
13324 | } | |
5a9335ef NC |
13325 | |
13326 | return true; | |
13327 | } | |
13328 | ||
301d03af RS |
13329 | return default_assemble_integer (x, size, aligned_p); |
13330 | } | |
7abc66b1 | 13331 | |
7abc66b1 | 13332 | static void |
9f296620 | 13333 | arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) |
7abc66b1 | 13334 | { |
50603eed PB |
13335 | section *s; |
13336 | ||
7abc66b1 JB |
13337 | if (!TARGET_AAPCS_BASED) |
13338 | { | |
9f296620 MM |
13339 | (is_ctor ? |
13340 | default_named_section_asm_out_constructor | |
13341 | : default_named_section_asm_out_destructor) (symbol, priority); | |
7abc66b1 JB |
13342 | return; |
13343 | } | |
13344 | ||
13345 | /* Put these in the .init_array section, using a special relocation. */ | |
50603eed PB |
13346 | if (priority != DEFAULT_INIT_PRIORITY) |
13347 | { | |
13348 | char buf[18]; | |
9f296620 MM |
13349 | sprintf (buf, "%s.%.5u", |
13350 | is_ctor ? ".init_array" : ".fini_array", | |
13351 | priority); | |
50603eed PB |
13352 | s = get_section (buf, SECTION_WRITE, NULL_TREE); |
13353 | } | |
9f296620 | 13354 | else if (is_ctor) |
50603eed | 13355 | s = ctors_section; |
9f296620 MM |
13356 | else |
13357 | s = dtors_section; | |
50603eed PB |
13358 | |
13359 | switch_to_section (s); | |
7abc66b1 JB |
13360 | assemble_align (POINTER_SIZE); |
13361 | fputs ("\t.word\t", asm_out_file); | |
13362 | output_addr_const (asm_out_file, symbol); | |
13363 | fputs ("(target1)\n", asm_out_file); | |
13364 | } | |
9f296620 MM |
13365 | |
13366 | /* Add a function to the list of static constructors. */ | |
13367 | ||
13368 | static void | |
13369 | arm_elf_asm_constructor (rtx symbol, int priority) | |
13370 | { | |
13371 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true); | |
13372 | } | |
13373 | ||
13374 | /* Add a function to the list of static destructors. */ | |
13375 | ||
13376 | static void | |
13377 | arm_elf_asm_destructor (rtx symbol, int priority) | |
13378 | { | |
13379 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false); | |
13380 | } | |
301d03af | 13381 | \f |
cce8749e CH |
13382 | /* A finite state machine takes care of noticing whether or not instructions |
13383 | can be conditionally executed, and thus decrease execution time and code | |
13384 | size by deleting branch instructions. The fsm is controlled by | |
13385 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
13386 | ||
13387 | /* The state of the fsm controlling condition codes are: | |
13388 | 0: normal, do nothing special | |
13389 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
13390 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
13391 | 3: make instructions conditional | |
13392 | 4: make instructions conditional | |
13393 | ||
13394 | State transitions (state->state by whom under condition): | |
13395 | 0 -> 1 final_prescan_insn if the `target' is a label | |
13396 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
13397 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
13398 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
4977bab6 | 13399 | 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached |
cce8749e CH |
13400 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). |
13401 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
13402 | (the target insn is arm_target_insn). | |
13403 | ||
ff9940b0 RE |
13404 | If the jump clobbers the conditions then we use states 2 and 4. |
13405 | ||
13406 | A similar thing can be done with conditional return insns. | |
13407 | ||
cce8749e CH |
13408 | XXX In case the `target' is an unconditional branch, this conditionalising |
13409 | of the instructions always reduces code size, but not always execution | |
13410 | time. But then, I want to reduce the code size to somewhere near what | |
13411 | /bin/cc produces. */ | |
13412 | ||
5b3e6663 PB |
13413 | /* In addition to this, state is maintained for Thumb-2 COND_EXEC |
13414 | instructions. When a COND_EXEC instruction is seen the subsequent | |
13415 | instructions are scanned so that multiple conditional instructions can be | |
13416 | combined into a single IT block. arm_condexec_count and arm_condexec_mask | |
13417 | specify the length and true/false mask for the IT block. These will be | |
13418 | decremented/zeroed by arm_asm_output_opcode as the insns are output. */ | |
13419 | ||
cce8749e CH |
13420 | /* Returns the index of the ARM condition code string in |
13421 | `arm_condition_codes'. COMPARISON should be an rtx like | |
13422 | `(eq (...) (...))'. */ | |
84ed5e79 | 13423 | static enum arm_cond_code |
e32bac5b | 13424 | get_arm_condition_code (rtx comparison) |
cce8749e | 13425 | { |
5165176d | 13426 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
1d6e90ac NC |
13427 | int code; |
13428 | enum rtx_code comp_code = GET_CODE (comparison); | |
5165176d RE |
13429 | |
13430 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 13431 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
13432 | XEXP (comparison, 1)); |
13433 | ||
13434 | switch (mode) | |
cce8749e | 13435 | { |
84ed5e79 RE |
13436 | case CC_DNEmode: code = ARM_NE; goto dominance; |
13437 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
13438 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
13439 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
13440 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
13441 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
13442 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
13443 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
13444 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
13445 | case CC_DLTUmode: code = ARM_CC; | |
13446 | ||
13447 | dominance: | |
e6d29d15 | 13448 | gcc_assert (comp_code == EQ || comp_code == NE); |
84ed5e79 RE |
13449 | |
13450 | if (comp_code == EQ) | |
13451 | return ARM_INVERSE_CONDITION_CODE (code); | |
13452 | return code; | |
13453 | ||
5165176d | 13454 | case CC_NOOVmode: |
84ed5e79 | 13455 | switch (comp_code) |
5165176d | 13456 | { |
84ed5e79 RE |
13457 | case NE: return ARM_NE; |
13458 | case EQ: return ARM_EQ; | |
13459 | case GE: return ARM_PL; | |
13460 | case LT: return ARM_MI; | |
e6d29d15 | 13461 | default: gcc_unreachable (); |
5165176d RE |
13462 | } |
13463 | ||
13464 | case CC_Zmode: | |
84ed5e79 | 13465 | switch (comp_code) |
5165176d | 13466 | { |
84ed5e79 RE |
13467 | case NE: return ARM_NE; |
13468 | case EQ: return ARM_EQ; | |
e6d29d15 | 13469 | default: gcc_unreachable (); |
5165176d RE |
13470 | } |
13471 | ||
defc0463 RE |
13472 | case CC_Nmode: |
13473 | switch (comp_code) | |
13474 | { | |
13475 | case NE: return ARM_MI; | |
13476 | case EQ: return ARM_PL; | |
e6d29d15 | 13477 | default: gcc_unreachable (); |
defc0463 RE |
13478 | } |
13479 | ||
5165176d | 13480 | case CCFPEmode: |
e45b72c4 RE |
13481 | case CCFPmode: |
13482 | /* These encodings assume that AC=1 in the FPA system control | |
13483 | byte. This allows us to handle all cases except UNEQ and | |
13484 | LTGT. */ | |
84ed5e79 RE |
13485 | switch (comp_code) |
13486 | { | |
13487 | case GE: return ARM_GE; | |
13488 | case GT: return ARM_GT; | |
13489 | case LE: return ARM_LS; | |
13490 | case LT: return ARM_MI; | |
e45b72c4 RE |
13491 | case NE: return ARM_NE; |
13492 | case EQ: return ARM_EQ; | |
13493 | case ORDERED: return ARM_VC; | |
13494 | case UNORDERED: return ARM_VS; | |
13495 | case UNLT: return ARM_LT; | |
13496 | case UNLE: return ARM_LE; | |
13497 | case UNGT: return ARM_HI; | |
13498 | case UNGE: return ARM_PL; | |
13499 | /* UNEQ and LTGT do not have a representation. */ | |
13500 | case UNEQ: /* Fall through. */ | |
13501 | case LTGT: /* Fall through. */ | |
e6d29d15 | 13502 | default: gcc_unreachable (); |
84ed5e79 RE |
13503 | } |
13504 | ||
13505 | case CC_SWPmode: | |
13506 | switch (comp_code) | |
13507 | { | |
13508 | case NE: return ARM_NE; | |
13509 | case EQ: return ARM_EQ; | |
13510 | case GE: return ARM_LE; | |
13511 | case GT: return ARM_LT; | |
13512 | case LE: return ARM_GE; | |
13513 | case LT: return ARM_GT; | |
13514 | case GEU: return ARM_LS; | |
13515 | case GTU: return ARM_CC; | |
13516 | case LEU: return ARM_CS; | |
13517 | case LTU: return ARM_HI; | |
e6d29d15 | 13518 | default: gcc_unreachable (); |
84ed5e79 RE |
13519 | } |
13520 | ||
bd9c7e23 RE |
13521 | case CC_Cmode: |
13522 | switch (comp_code) | |
13523 | { | |
13524 | case LTU: return ARM_CS; | |
13525 | case GEU: return ARM_CC; | |
e6d29d15 | 13526 | default: gcc_unreachable (); |
bd9c7e23 | 13527 | } |
f676971a | 13528 | |
5165176d | 13529 | case CCmode: |
84ed5e79 | 13530 | switch (comp_code) |
5165176d | 13531 | { |
84ed5e79 RE |
13532 | case NE: return ARM_NE; |
13533 | case EQ: return ARM_EQ; | |
13534 | case GE: return ARM_GE; | |
13535 | case GT: return ARM_GT; | |
13536 | case LE: return ARM_LE; | |
13537 | case LT: return ARM_LT; | |
13538 | case GEU: return ARM_CS; | |
13539 | case GTU: return ARM_HI; | |
13540 | case LEU: return ARM_LS; | |
13541 | case LTU: return ARM_CC; | |
e6d29d15 | 13542 | default: gcc_unreachable (); |
5165176d RE |
13543 | } |
13544 | ||
e6d29d15 | 13545 | default: gcc_unreachable (); |
cce8749e | 13546 | } |
f3bb6135 | 13547 | } |
cce8749e | 13548 | |
44c7bd63 | 13549 | /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed |
5b3e6663 PB |
13550 | instructions. */ |
13551 | void | |
13552 | thumb2_final_prescan_insn (rtx insn) | |
13553 | { | |
13554 | rtx first_insn = insn; | |
13555 | rtx body = PATTERN (insn); | |
13556 | rtx predicate; | |
13557 | enum arm_cond_code code; | |
13558 | int n; | |
13559 | int mask; | |
13560 | ||
13561 | /* Remove the previous insn from the count of insns to be output. */ | |
13562 | if (arm_condexec_count) | |
13563 | arm_condexec_count--; | |
13564 | ||
13565 | /* Nothing to do if we are already inside a conditional block. */ | |
13566 | if (arm_condexec_count) | |
13567 | return; | |
13568 | ||
13569 | if (GET_CODE (body) != COND_EXEC) | |
13570 | return; | |
13571 | ||
13572 | /* Conditional jumps are implemented directly. */ | |
13573 | if (GET_CODE (insn) == JUMP_INSN) | |
13574 | return; | |
13575 | ||
13576 | predicate = COND_EXEC_TEST (body); | |
13577 | arm_current_cc = get_arm_condition_code (predicate); | |
13578 | ||
13579 | n = get_attr_ce_count (insn); | |
13580 | arm_condexec_count = 1; | |
13581 | arm_condexec_mask = (1 << n) - 1; | |
13582 | arm_condexec_masklen = n; | |
13583 | /* See if subsequent instructions can be combined into the same block. */ | |
13584 | for (;;) | |
13585 | { | |
13586 | insn = next_nonnote_insn (insn); | |
13587 | ||
13588 | /* Jumping into the middle of an IT block is illegal, so a label or | |
13589 | barrier terminates the block. */ | |
13590 | if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN) | |
13591 | break; | |
13592 | ||
13593 | body = PATTERN (insn); | |
13594 | /* USE and CLOBBER aren't really insns, so just skip them. */ | |
13595 | if (GET_CODE (body) == USE | |
13596 | || GET_CODE (body) == CLOBBER) | |
5b0202af | 13597 | continue; |
5b3e6663 | 13598 | |
7a085dce | 13599 | /* ??? Recognize conditional jumps, and combine them with IT blocks. */ |
5b3e6663 PB |
13600 | if (GET_CODE (body) != COND_EXEC) |
13601 | break; | |
13602 | /* Allow up to 4 conditionally executed instructions in a block. */ | |
13603 | n = get_attr_ce_count (insn); | |
13604 | if (arm_condexec_masklen + n > 4) | |
13605 | break; | |
13606 | ||
13607 | predicate = COND_EXEC_TEST (body); | |
13608 | code = get_arm_condition_code (predicate); | |
13609 | mask = (1 << n) - 1; | |
13610 | if (arm_current_cc == code) | |
13611 | arm_condexec_mask |= (mask << arm_condexec_masklen); | |
13612 | else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code)) | |
13613 | break; | |
13614 | ||
13615 | arm_condexec_count++; | |
13616 | arm_condexec_masklen += n; | |
13617 | ||
13618 | /* A jump must be the last instruction in a conditional block. */ | |
13619 | if (GET_CODE(insn) == JUMP_INSN) | |
13620 | break; | |
13621 | } | |
13622 | /* Restore recog_data (getting the attributes of other insns can | |
13623 | destroy this array, but final.c assumes that it remains intact | |
13624 | across this call). */ | |
13625 | extract_constrain_insn_cached (first_insn); | |
13626 | } | |
13627 | ||
cce8749e | 13628 | void |
e32bac5b | 13629 | arm_final_prescan_insn (rtx insn) |
cce8749e CH |
13630 | { |
13631 | /* BODY will hold the body of INSN. */ | |
1d6e90ac | 13632 | rtx body = PATTERN (insn); |
cce8749e CH |
13633 | |
13634 | /* This will be 1 if trying to repeat the trick, and things need to be | |
13635 | reversed if it appears to fail. */ | |
13636 | int reverse = 0; | |
13637 | ||
ff9940b0 RE |
13638 | /* JUMP_CLOBBERS will be one implies that the conditions if a branch is |
13639 | taken are clobbered, even if the rtl suggests otherwise. It also | |
13640 | means that we have to grub around within the jump expression to find | |
13641 | out what the conditions are when the jump isn't taken. */ | |
13642 | int jump_clobbers = 0; | |
f676971a | 13643 | |
6354dc9b | 13644 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 | 13645 | int seeking_return = 0; |
f676971a | 13646 | |
cce8749e CH |
13647 | /* START_INSN will hold the insn from where we start looking. This is the |
13648 | first insn after the following code_label if REVERSE is true. */ | |
13649 | rtx start_insn = insn; | |
13650 | ||
13651 | /* If in state 4, check if the target branch is reached, in order to | |
13652 | change back to state 0. */ | |
13653 | if (arm_ccfsm_state == 4) | |
13654 | { | |
13655 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
13656 | { |
13657 | arm_target_insn = NULL; | |
13658 | arm_ccfsm_state = 0; | |
13659 | } | |
cce8749e CH |
13660 | return; |
13661 | } | |
13662 | ||
13663 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
13664 | unconditional branch to a label, and immediately following this branch | |
13665 | is the previous target label which is only used once, and the label this | |
13666 | branch jumps to is not too far off. */ | |
13667 | if (arm_ccfsm_state == 3) | |
13668 | { | |
13669 | if (simplejump_p (insn)) | |
13670 | { | |
13671 | start_insn = next_nonnote_insn (start_insn); | |
13672 | if (GET_CODE (start_insn) == BARRIER) | |
13673 | { | |
13674 | /* XXX Isn't this always a barrier? */ | |
13675 | start_insn = next_nonnote_insn (start_insn); | |
13676 | } | |
13677 | if (GET_CODE (start_insn) == CODE_LABEL | |
13678 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
13679 | && LABEL_NUSES (start_insn) == 1) | |
13680 | reverse = TRUE; | |
13681 | else | |
13682 | return; | |
13683 | } | |
ff9940b0 RE |
13684 | else if (GET_CODE (body) == RETURN) |
13685 | { | |
13686 | start_insn = next_nonnote_insn (start_insn); | |
13687 | if (GET_CODE (start_insn) == BARRIER) | |
13688 | start_insn = next_nonnote_insn (start_insn); | |
13689 | if (GET_CODE (start_insn) == CODE_LABEL | |
13690 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
13691 | && LABEL_NUSES (start_insn) == 1) | |
13692 | { | |
13693 | reverse = TRUE; | |
13694 | seeking_return = 1; | |
13695 | } | |
13696 | else | |
13697 | return; | |
13698 | } | |
cce8749e CH |
13699 | else |
13700 | return; | |
13701 | } | |
13702 | ||
e6d29d15 | 13703 | gcc_assert (!arm_ccfsm_state || reverse); |
cce8749e CH |
13704 | if (GET_CODE (insn) != JUMP_INSN) |
13705 | return; | |
13706 | ||
f676971a | 13707 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
13708 | the jump should always come first */ |
13709 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
13710 | body = XVECEXP (body, 0, 0); | |
13711 | ||
cce8749e CH |
13712 | if (reverse |
13713 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
13714 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
13715 | { | |
bd9c7e23 RE |
13716 | int insns_skipped; |
13717 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
13718 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
13719 | int then_not_else = TRUE; | |
ff9940b0 | 13720 | rtx this_insn = start_insn, label = 0; |
cce8749e | 13721 | |
f676971a | 13722 | /* If the jump cannot be done with one instruction, we cannot |
e45b72c4 | 13723 | conditionally execute the instruction in the inverse case. */ |
ff9940b0 | 13724 | if (get_attr_conds (insn) == CONDS_JUMP_CLOB) |
5bbe2d40 | 13725 | { |
5bbe2d40 RE |
13726 | jump_clobbers = 1; |
13727 | return; | |
13728 | } | |
f676971a | 13729 | |
cce8749e CH |
13730 | /* Register the insn jumped to. */ |
13731 | if (reverse) | |
ff9940b0 RE |
13732 | { |
13733 | if (!seeking_return) | |
13734 | label = XEXP (SET_SRC (body), 0); | |
13735 | } | |
cce8749e CH |
13736 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
13737 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
13738 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
13739 | { | |
13740 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
13741 | then_not_else = FALSE; | |
13742 | } | |
ff9940b0 RE |
13743 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
13744 | seeking_return = 1; | |
13745 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
13746 | { | |
13747 | seeking_return = 1; | |
13748 | then_not_else = FALSE; | |
13749 | } | |
cce8749e | 13750 | else |
e6d29d15 | 13751 | gcc_unreachable (); |
cce8749e CH |
13752 | |
13753 | /* See how many insns this branch skips, and what kind of insns. If all | |
13754 | insns are okay, and the label or unconditional branch to the same | |
13755 | label is not too far away, succeed. */ | |
13756 | for (insns_skipped = 0; | |
b36ba79f | 13757 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
13758 | { |
13759 | rtx scanbody; | |
13760 | ||
13761 | this_insn = next_nonnote_insn (this_insn); | |
13762 | if (!this_insn) | |
13763 | break; | |
13764 | ||
cce8749e CH |
13765 | switch (GET_CODE (this_insn)) |
13766 | { | |
13767 | case CODE_LABEL: | |
13768 | /* Succeed if it is the target label, otherwise fail since | |
13769 | control falls in from somewhere else. */ | |
13770 | if (this_insn == label) | |
13771 | { | |
ff9940b0 RE |
13772 | if (jump_clobbers) |
13773 | { | |
13774 | arm_ccfsm_state = 2; | |
13775 | this_insn = next_nonnote_insn (this_insn); | |
13776 | } | |
13777 | else | |
13778 | arm_ccfsm_state = 1; | |
cce8749e CH |
13779 | succeed = TRUE; |
13780 | } | |
13781 | else | |
13782 | fail = TRUE; | |
13783 | break; | |
13784 | ||
ff9940b0 | 13785 | case BARRIER: |
cce8749e | 13786 | /* Succeed if the following insn is the target label. |
f676971a EC |
13787 | Otherwise fail. |
13788 | If return insns are used then the last insn in a function | |
6354dc9b | 13789 | will be a barrier. */ |
cce8749e | 13790 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 13791 | if (this_insn && this_insn == label) |
cce8749e | 13792 | { |
ff9940b0 RE |
13793 | if (jump_clobbers) |
13794 | { | |
13795 | arm_ccfsm_state = 2; | |
13796 | this_insn = next_nonnote_insn (this_insn); | |
13797 | } | |
13798 | else | |
13799 | arm_ccfsm_state = 1; | |
cce8749e CH |
13800 | succeed = TRUE; |
13801 | } | |
13802 | else | |
13803 | fail = TRUE; | |
13804 | break; | |
13805 | ||
ff9940b0 | 13806 | case CALL_INSN: |
68d560d4 RE |
13807 | /* The AAPCS says that conditional calls should not be |
13808 | used since they make interworking inefficient (the | |
13809 | linker can't transform BL<cond> into BLX). That's | |
13810 | only a problem if the machine has BLX. */ | |
13811 | if (arm_arch5) | |
13812 | { | |
13813 | fail = TRUE; | |
13814 | break; | |
13815 | } | |
13816 | ||
61f0ccff RE |
13817 | /* Succeed if the following insn is the target label, or |
13818 | if the following two insns are a barrier and the | |
13819 | target label. */ | |
13820 | this_insn = next_nonnote_insn (this_insn); | |
13821 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
13822 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 | 13823 | |
61f0ccff RE |
13824 | if (this_insn && this_insn == label |
13825 | && insns_skipped < max_insns_skipped) | |
13826 | { | |
13827 | if (jump_clobbers) | |
bd9c7e23 | 13828 | { |
61f0ccff RE |
13829 | arm_ccfsm_state = 2; |
13830 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 RE |
13831 | } |
13832 | else | |
61f0ccff RE |
13833 | arm_ccfsm_state = 1; |
13834 | succeed = TRUE; | |
bd9c7e23 | 13835 | } |
61f0ccff RE |
13836 | else |
13837 | fail = TRUE; | |
ff9940b0 | 13838 | break; |
2b835d68 | 13839 | |
cce8749e CH |
13840 | case JUMP_INSN: |
13841 | /* If this is an unconditional branch to the same label, succeed. | |
13842 | If it is to another label, do nothing. If it is conditional, | |
13843 | fail. */ | |
e32bac5b RE |
13844 | /* XXX Probably, the tests for SET and the PC are |
13845 | unnecessary. */ | |
cce8749e | 13846 | |
ed4c4348 | 13847 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
13848 | if (GET_CODE (scanbody) == SET |
13849 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
13850 | { |
13851 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
13852 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
13853 | { | |
13854 | arm_ccfsm_state = 2; | |
13855 | succeed = TRUE; | |
13856 | } | |
13857 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
13858 | fail = TRUE; | |
13859 | } | |
112cdef5 | 13860 | /* Fail if a conditional return is undesirable (e.g. on a |
b36ba79f RE |
13861 | StrongARM), but still allow this if optimizing for size. */ |
13862 | else if (GET_CODE (scanbody) == RETURN | |
a72d4945 | 13863 | && !use_return_insn (TRUE, NULL) |
5895f793 | 13864 | && !optimize_size) |
b36ba79f | 13865 | fail = TRUE; |
ff9940b0 RE |
13866 | else if (GET_CODE (scanbody) == RETURN |
13867 | && seeking_return) | |
13868 | { | |
13869 | arm_ccfsm_state = 2; | |
13870 | succeed = TRUE; | |
13871 | } | |
13872 | else if (GET_CODE (scanbody) == PARALLEL) | |
13873 | { | |
13874 | switch (get_attr_conds (this_insn)) | |
13875 | { | |
13876 | case CONDS_NOCOND: | |
13877 | break; | |
13878 | default: | |
13879 | fail = TRUE; | |
13880 | break; | |
13881 | } | |
13882 | } | |
4e67550b | 13883 | else |
112cdef5 | 13884 | fail = TRUE; /* Unrecognized jump (e.g. epilogue). */ |
4e67550b | 13885 | |
cce8749e CH |
13886 | break; |
13887 | ||
13888 | case INSN: | |
ff9940b0 RE |
13889 | /* Instructions using or affecting the condition codes make it |
13890 | fail. */ | |
ed4c4348 | 13891 | scanbody = PATTERN (this_insn); |
5895f793 RE |
13892 | if (!(GET_CODE (scanbody) == SET |
13893 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 13894 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e | 13895 | fail = TRUE; |
9b6b54e2 NC |
13896 | |
13897 | /* A conditional cirrus instruction must be followed by | |
13898 | a non Cirrus instruction. However, since we | |
13899 | conditionalize instructions in this function and by | |
13900 | the time we get here we can't add instructions | |
13901 | (nops), because shorten_branches() has already been | |
13902 | called, we will disable conditionalizing Cirrus | |
13903 | instructions to be safe. */ | |
13904 | if (GET_CODE (scanbody) != USE | |
13905 | && GET_CODE (scanbody) != CLOBBER | |
f0375c66 | 13906 | && get_attr_cirrus (this_insn) != CIRRUS_NOT) |
9b6b54e2 | 13907 | fail = TRUE; |
cce8749e CH |
13908 | break; |
13909 | ||
13910 | default: | |
13911 | break; | |
13912 | } | |
13913 | } | |
13914 | if (succeed) | |
13915 | { | |
ff9940b0 | 13916 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 13917 | arm_target_label = CODE_LABEL_NUMBER (label); |
e6d29d15 | 13918 | else |
ff9940b0 | 13919 | { |
e6d29d15 | 13920 | gcc_assert (seeking_return || arm_ccfsm_state == 2); |
e0b92319 | 13921 | |
ff9940b0 RE |
13922 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) |
13923 | { | |
13924 | this_insn = next_nonnote_insn (this_insn); | |
e6d29d15 NS |
13925 | gcc_assert (!this_insn |
13926 | || (GET_CODE (this_insn) != BARRIER | |
13927 | && GET_CODE (this_insn) != CODE_LABEL)); | |
ff9940b0 RE |
13928 | } |
13929 | if (!this_insn) | |
13930 | { | |
d6b4baa4 | 13931 | /* Oh, dear! we ran off the end.. give up. */ |
5b3e6663 | 13932 | extract_constrain_insn_cached (insn); |
ff9940b0 | 13933 | arm_ccfsm_state = 0; |
abaa26e5 | 13934 | arm_target_insn = NULL; |
ff9940b0 RE |
13935 | return; |
13936 | } | |
13937 | arm_target_insn = this_insn; | |
13938 | } | |
ff9940b0 RE |
13939 | if (jump_clobbers) |
13940 | { | |
e6d29d15 | 13941 | gcc_assert (!reverse); |
f676971a | 13942 | arm_current_cc = |
ff9940b0 RE |
13943 | get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), |
13944 | 0), 0), 1)); | |
13945 | if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) | |
13946 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
13947 | if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) | |
13948 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
13949 | } | |
13950 | else | |
13951 | { | |
13952 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
13953 | what it was. */ | |
13954 | if (!reverse) | |
13955 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), | |
13956 | 0)); | |
13957 | } | |
cce8749e | 13958 | |
cce8749e CH |
13959 | if (reverse || then_not_else) |
13960 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
13961 | } | |
f676971a | 13962 | |
1ccbefce | 13963 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 13964 | destroy this array, but final.c assumes that it remains intact |
5b3e6663 PB |
13965 | across this call. */ |
13966 | extract_constrain_insn_cached (insn); | |
13967 | } | |
13968 | } | |
13969 | ||
13970 | /* Output IT instructions. */ | |
13971 | void | |
13972 | thumb2_asm_output_opcode (FILE * stream) | |
13973 | { | |
13974 | char buff[5]; | |
13975 | int n; | |
13976 | ||
13977 | if (arm_condexec_mask) | |
13978 | { | |
13979 | for (n = 0; n < arm_condexec_masklen; n++) | |
13980 | buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e'; | |
13981 | buff[n] = 0; | |
13982 | asm_fprintf(stream, "i%s\t%s\n\t", buff, | |
13983 | arm_condition_codes[arm_current_cc]); | |
13984 | arm_condexec_mask = 0; | |
cce8749e | 13985 | } |
f3bb6135 | 13986 | } |
cce8749e | 13987 | |
4b02997f | 13988 | /* Returns true if REGNO is a valid register |
21b5653c | 13989 | for holding a quantity of type MODE. */ |
4b02997f | 13990 | int |
e32bac5b | 13991 | arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) |
4b02997f NC |
13992 | { |
13993 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
a6a5de04 RE |
13994 | return (regno == CC_REGNUM |
13995 | || (TARGET_HARD_FLOAT && TARGET_VFP | |
13996 | && regno == VFPCC_REGNUM)); | |
f676971a | 13997 | |
5b3e6663 | 13998 | if (TARGET_THUMB1) |
4b02997f NC |
13999 | /* For the Thumb we only allow values bigger than SImode in |
14000 | registers 0 - 6, so that there is always a second low | |
14001 | register available to hold the upper part of the value. | |
14002 | We probably we ought to ensure that the register is the | |
14003 | start of an even numbered register pair. */ | |
e9d7b180 | 14004 | return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); |
4b02997f | 14005 | |
a6a5de04 RE |
14006 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK |
14007 | && IS_CIRRUS_REGNUM (regno)) | |
9b6b54e2 NC |
14008 | /* We have outlawed SI values in Cirrus registers because they |
14009 | reside in the lower 32 bits, but SF values reside in the | |
14010 | upper 32 bits. This causes gcc all sorts of grief. We can't | |
14011 | even split the registers into pairs because Cirrus SI values | |
14012 | get sign extended to 64bits-- aldyh. */ | |
14013 | return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); | |
14014 | ||
a6a5de04 RE |
14015 | if (TARGET_HARD_FLOAT && TARGET_VFP |
14016 | && IS_VFP_REGNUM (regno)) | |
9b66ebb1 PB |
14017 | { |
14018 | if (mode == SFmode || mode == SImode) | |
f1adb0a9 | 14019 | return VFP_REGNO_OK_FOR_SINGLE (regno); |
9b66ebb1 | 14020 | |
9b66ebb1 | 14021 | if (mode == DFmode) |
f1adb0a9 | 14022 | return VFP_REGNO_OK_FOR_DOUBLE (regno); |
88f77cba JB |
14023 | |
14024 | if (TARGET_NEON) | |
14025 | return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno)) | |
14026 | || (VALID_NEON_QREG_MODE (mode) | |
14027 | && NEON_REGNO_OK_FOR_QUAD (regno)) | |
14028 | || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2)) | |
14029 | || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3)) | |
14030 | || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4)) | |
14031 | || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6)) | |
14032 | || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8)); | |
14033 | ||
9b66ebb1 PB |
14034 | return FALSE; |
14035 | } | |
14036 | ||
a6a5de04 RE |
14037 | if (TARGET_REALLY_IWMMXT) |
14038 | { | |
14039 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
14040 | return mode == SImode; | |
5a9335ef | 14041 | |
a6a5de04 RE |
14042 | if (IS_IWMMXT_REGNUM (regno)) |
14043 | return VALID_IWMMXT_REG_MODE (mode); | |
14044 | } | |
14045 | ||
fdd695fd PB |
14046 | /* We allow any value to be stored in the general registers. |
14047 | Restrict doubleword quantities to even register pairs so that we can | |
88f77cba JB |
14048 | use ldrd. Do not allow Neon structure opaque modes in general registers; |
14049 | they would use too many. */ | |
4b02997f | 14050 | if (regno <= LAST_ARM_REGNUM) |
88f77cba JB |
14051 | return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0) |
14052 | && !VALID_NEON_STRUCT_MODE (mode); | |
4b02997f | 14053 | |
a6a5de04 | 14054 | if (regno == FRAME_POINTER_REGNUM |
4b02997f NC |
14055 | || regno == ARG_POINTER_REGNUM) |
14056 | /* We only allow integers in the fake hard registers. */ | |
14057 | return GET_MODE_CLASS (mode) == MODE_INT; | |
14058 | ||
3b684012 | 14059 | /* The only registers left are the FPA registers |
4b02997f | 14060 | which we only allow to hold FP values. */ |
a6a5de04 RE |
14061 | return (TARGET_HARD_FLOAT && TARGET_FPA |
14062 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
14063 | && regno >= FIRST_FPA_REGNUM | |
14064 | && regno <= LAST_FPA_REGNUM); | |
4b02997f NC |
14065 | } |
14066 | ||
5b3e6663 PB |
14067 | /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are |
14068 | not used in arm mode. */ | |
d5b7b3ae | 14069 | int |
e32bac5b | 14070 | arm_regno_class (int regno) |
d5b7b3ae | 14071 | { |
5b3e6663 | 14072 | if (TARGET_THUMB1) |
d5b7b3ae RE |
14073 | { |
14074 | if (regno == STACK_POINTER_REGNUM) | |
14075 | return STACK_REG; | |
14076 | if (regno == CC_REGNUM) | |
14077 | return CC_REG; | |
14078 | if (regno < 8) | |
14079 | return LO_REGS; | |
14080 | return HI_REGS; | |
14081 | } | |
14082 | ||
5b3e6663 PB |
14083 | if (TARGET_THUMB2 && regno < 8) |
14084 | return LO_REGS; | |
14085 | ||
d5b7b3ae RE |
14086 | if ( regno <= LAST_ARM_REGNUM |
14087 | || regno == FRAME_POINTER_REGNUM | |
14088 | || regno == ARG_POINTER_REGNUM) | |
5b3e6663 | 14089 | return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS; |
f676971a | 14090 | |
9b66ebb1 | 14091 | if (regno == CC_REGNUM || regno == VFPCC_REGNUM) |
5b3e6663 | 14092 | return TARGET_THUMB2 ? CC_REG : NO_REGS; |
d5b7b3ae | 14093 | |
9b6b54e2 NC |
14094 | if (IS_CIRRUS_REGNUM (regno)) |
14095 | return CIRRUS_REGS; | |
14096 | ||
9b66ebb1 | 14097 | if (IS_VFP_REGNUM (regno)) |
f1adb0a9 JB |
14098 | { |
14099 | if (regno <= D7_VFP_REGNUM) | |
14100 | return VFP_D0_D7_REGS; | |
14101 | else if (regno <= LAST_LO_VFP_REGNUM) | |
14102 | return VFP_LO_REGS; | |
14103 | else | |
14104 | return VFP_HI_REGS; | |
14105 | } | |
9b66ebb1 | 14106 | |
5a9335ef NC |
14107 | if (IS_IWMMXT_REGNUM (regno)) |
14108 | return IWMMXT_REGS; | |
14109 | ||
e99faaaa ILT |
14110 | if (IS_IWMMXT_GR_REGNUM (regno)) |
14111 | return IWMMXT_GR_REGS; | |
14112 | ||
3b684012 | 14113 | return FPA_REGS; |
d5b7b3ae RE |
14114 | } |
14115 | ||
14116 | /* Handle a special case when computing the offset | |
14117 | of an argument from the frame pointer. */ | |
14118 | int | |
e32bac5b | 14119 | arm_debugger_arg_offset (int value, rtx addr) |
d5b7b3ae RE |
14120 | { |
14121 | rtx insn; | |
14122 | ||
14123 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
14124 | if (value != 0) | |
14125 | return 0; | |
14126 | ||
14127 | /* We can only cope with the case where the address is held in a register. */ | |
14128 | if (GET_CODE (addr) != REG) | |
14129 | return 0; | |
14130 | ||
14131 | /* If we are using the frame pointer to point at the argument, then | |
14132 | an offset of 0 is correct. */ | |
cd2b33d0 | 14133 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae | 14134 | return 0; |
f676971a | 14135 | |
d5b7b3ae RE |
14136 | /* If we are using the stack pointer to point at the |
14137 | argument, then an offset of 0 is correct. */ | |
5b3e6663 | 14138 | /* ??? Check this is consistent with thumb2 frame layout. */ |
5895f793 | 14139 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
14140 | && REGNO (addr) == SP_REGNUM) |
14141 | return 0; | |
f676971a | 14142 | |
d5b7b3ae RE |
14143 | /* Oh dear. The argument is pointed to by a register rather |
14144 | than being held in a register, or being stored at a known | |
14145 | offset from the frame pointer. Since GDB only understands | |
14146 | those two kinds of argument we must translate the address | |
14147 | held in the register into an offset from the frame pointer. | |
14148 | We do this by searching through the insns for the function | |
14149 | looking to see where this register gets its value. If the | |
4912a07c | 14150 | register is initialized from the frame pointer plus an offset |
d5b7b3ae | 14151 | then we are in luck and we can continue, otherwise we give up. |
f676971a | 14152 | |
d5b7b3ae RE |
14153 | This code is exercised by producing debugging information |
14154 | for a function with arguments like this: | |
f676971a | 14155 | |
d5b7b3ae | 14156 | double func (double a, double b, int c, double d) {return d;} |
f676971a | 14157 | |
d5b7b3ae RE |
14158 | Without this code the stab for parameter 'd' will be set to |
14159 | an offset of 0 from the frame pointer, rather than 8. */ | |
14160 | ||
14161 | /* The if() statement says: | |
14162 | ||
14163 | If the insn is a normal instruction | |
14164 | and if the insn is setting the value in a register | |
14165 | and if the register being set is the register holding the address of the argument | |
14166 | and if the address is computing by an addition | |
14167 | that involves adding to a register | |
14168 | which is the frame pointer | |
14169 | a constant integer | |
14170 | ||
d6b4baa4 | 14171 | then... */ |
f676971a | 14172 | |
d5b7b3ae RE |
14173 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
14174 | { | |
f676971a | 14175 | if ( GET_CODE (insn) == INSN |
d5b7b3ae RE |
14176 | && GET_CODE (PATTERN (insn)) == SET |
14177 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
14178 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
14179 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 14180 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
14181 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
14182 | ) | |
14183 | { | |
14184 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
f676971a | 14185 | |
d5b7b3ae RE |
14186 | break; |
14187 | } | |
14188 | } | |
f676971a | 14189 | |
d5b7b3ae RE |
14190 | if (value == 0) |
14191 | { | |
14192 | debug_rtx (addr); | |
d4ee4d25 | 14193 | warning (0, "unable to compute real location of stacked parameter"); |
d5b7b3ae RE |
14194 | value = 8; /* XXX magic hack */ |
14195 | } | |
14196 | ||
14197 | return value; | |
14198 | } | |
d5b7b3ae | 14199 | \f |
5a9335ef NC |
14200 | #define def_mbuiltin(MASK, NAME, TYPE, CODE) \ |
14201 | do \ | |
14202 | { \ | |
14203 | if ((MASK) & insn_flags) \ | |
c79efc4d RÁE |
14204 | add_builtin_function ((NAME), (TYPE), (CODE), \ |
14205 | BUILT_IN_MD, NULL, NULL_TREE); \ | |
5a9335ef NC |
14206 | } \ |
14207 | while (0) | |
14208 | ||
14209 | struct builtin_description | |
14210 | { | |
14211 | const unsigned int mask; | |
14212 | const enum insn_code icode; | |
14213 | const char * const name; | |
14214 | const enum arm_builtins code; | |
14215 | const enum rtx_code comparison; | |
14216 | const unsigned int flag; | |
14217 | }; | |
14218 | ||
14219 | static const struct builtin_description bdesc_2arg[] = | |
14220 | { | |
14221 | #define IWMMXT_BUILTIN(code, string, builtin) \ | |
14222 | { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ | |
14223 | ARM_BUILTIN_##builtin, 0, 0 }, | |
14224 | ||
14225 | IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) | |
14226 | IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) | |
14227 | IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) | |
14228 | IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) | |
14229 | IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) | |
14230 | IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) | |
14231 | IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) | |
14232 | IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) | |
14233 | IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) | |
14234 | IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) | |
14235 | IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) | |
14236 | IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) | |
14237 | IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) | |
14238 | IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) | |
14239 | IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) | |
14240 | IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) | |
14241 | IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) | |
14242 | IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) | |
14243 | IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) | |
f07a6b21 BE |
14244 | IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) |
14245 | IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) | |
5a9335ef NC |
14246 | IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) |
14247 | IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) | |
14248 | IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) | |
14249 | IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) | |
14250 | IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) | |
14251 | IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) | |
14252 | IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) | |
14253 | IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) | |
14254 | IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) | |
14255 | IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) | |
14256 | IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) | |
14257 | IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) | |
14258 | IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) | |
14259 | IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) | |
14260 | IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) | |
14261 | IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) | |
14262 | IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) | |
14263 | IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) | |
14264 | IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) | |
14265 | IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) | |
14266 | IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) | |
14267 | IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) | |
14268 | IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) | |
14269 | IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) | |
14270 | IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) | |
14271 | IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) | |
14272 | IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) | |
14273 | IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) | |
14274 | IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) | |
14275 | IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) | |
14276 | IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) | |
14277 | IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) | |
14278 | IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) | |
14279 | IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) | |
14280 | IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) | |
14281 | IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) | |
14282 | IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) | |
14283 | ||
14284 | #define IWMMXT_BUILTIN2(code, builtin) \ | |
14285 | { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 }, | |
f676971a | 14286 | |
5a9335ef NC |
14287 | IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) |
14288 | IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) | |
14289 | IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) | |
14290 | IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) | |
14291 | IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) | |
14292 | IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) | |
14293 | IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) | |
88f77cba | 14294 | IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI) |
5a9335ef | 14295 | IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) |
88f77cba | 14296 | IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI) |
5a9335ef NC |
14297 | IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) |
14298 | IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) | |
14299 | IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) | |
88f77cba | 14300 | IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI) |
5a9335ef | 14301 | IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) |
88f77cba | 14302 | IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI) |
5a9335ef | 14303 | IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) |
9b66ebb1 | 14304 | IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) |
5a9335ef | 14305 | IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) |
88f77cba | 14306 | IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI) |
5a9335ef | 14307 | IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) |
88f77cba | 14308 | IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI) |
5a9335ef | 14309 | IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) |
9b66ebb1 | 14310 | IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) |
5a9335ef NC |
14311 | IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) |
14312 | IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) | |
14313 | IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) | |
14314 | IWMMXT_BUILTIN2 (rorv2si3, WRORWI) | |
14315 | IWMMXT_BUILTIN2 (rordi3_di, WRORD) | |
14316 | IWMMXT_BUILTIN2 (rordi3, WRORDI) | |
14317 | IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) | |
14318 | IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) | |
14319 | }; | |
14320 | ||
14321 | static const struct builtin_description bdesc_1arg[] = | |
14322 | { | |
14323 | IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) | |
14324 | IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) | |
14325 | IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) | |
14326 | IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) | |
14327 | IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) | |
14328 | IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) | |
14329 | IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) | |
14330 | IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) | |
14331 | IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) | |
14332 | IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) | |
14333 | IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) | |
14334 | IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) | |
14335 | IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) | |
14336 | IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) | |
14337 | IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) | |
14338 | IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) | |
14339 | IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) | |
14340 | IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) | |
14341 | }; | |
14342 | ||
14343 | /* Set up all the iWMMXt builtins. This is | |
14344 | not called if TARGET_IWMMXT is zero. */ | |
14345 | ||
14346 | static void | |
14347 | arm_init_iwmmxt_builtins (void) | |
14348 | { | |
14349 | const struct builtin_description * d; | |
14350 | size_t i; | |
14351 | tree endlink = void_list_node; | |
14352 | ||
4a5eab38 PB |
14353 | tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); |
14354 | tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); | |
14355 | tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); | |
14356 | ||
5a9335ef NC |
14357 | tree int_ftype_int |
14358 | = build_function_type (integer_type_node, | |
14359 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
14360 | tree v8qi_ftype_v8qi_v8qi_int | |
14361 | = build_function_type (V8QI_type_node, | |
14362 | tree_cons (NULL_TREE, V8QI_type_node, | |
14363 | tree_cons (NULL_TREE, V8QI_type_node, | |
14364 | tree_cons (NULL_TREE, | |
14365 | integer_type_node, | |
14366 | endlink)))); | |
14367 | tree v4hi_ftype_v4hi_int | |
14368 | = build_function_type (V4HI_type_node, | |
14369 | tree_cons (NULL_TREE, V4HI_type_node, | |
14370 | tree_cons (NULL_TREE, integer_type_node, | |
14371 | endlink))); | |
14372 | tree v2si_ftype_v2si_int | |
14373 | = build_function_type (V2SI_type_node, | |
14374 | tree_cons (NULL_TREE, V2SI_type_node, | |
14375 | tree_cons (NULL_TREE, integer_type_node, | |
14376 | endlink))); | |
14377 | tree v2si_ftype_di_di | |
14378 | = build_function_type (V2SI_type_node, | |
14379 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
14380 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
14381 | endlink))); | |
14382 | tree di_ftype_di_int | |
14383 | = build_function_type (long_long_integer_type_node, | |
14384 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
14385 | tree_cons (NULL_TREE, integer_type_node, | |
14386 | endlink))); | |
14387 | tree di_ftype_di_int_int | |
14388 | = build_function_type (long_long_integer_type_node, | |
14389 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
14390 | tree_cons (NULL_TREE, integer_type_node, | |
14391 | tree_cons (NULL_TREE, | |
14392 | integer_type_node, | |
14393 | endlink)))); | |
14394 | tree int_ftype_v8qi | |
14395 | = build_function_type (integer_type_node, | |
14396 | tree_cons (NULL_TREE, V8QI_type_node, | |
14397 | endlink)); | |
14398 | tree int_ftype_v4hi | |
14399 | = build_function_type (integer_type_node, | |
14400 | tree_cons (NULL_TREE, V4HI_type_node, | |
14401 | endlink)); | |
14402 | tree int_ftype_v2si | |
14403 | = build_function_type (integer_type_node, | |
14404 | tree_cons (NULL_TREE, V2SI_type_node, | |
14405 | endlink)); | |
14406 | tree int_ftype_v8qi_int | |
14407 | = build_function_type (integer_type_node, | |
14408 | tree_cons (NULL_TREE, V8QI_type_node, | |
14409 | tree_cons (NULL_TREE, integer_type_node, | |
14410 | endlink))); | |
14411 | tree int_ftype_v4hi_int | |
14412 | = build_function_type (integer_type_node, | |
14413 | tree_cons (NULL_TREE, V4HI_type_node, | |
14414 | tree_cons (NULL_TREE, integer_type_node, | |
14415 | endlink))); | |
14416 | tree int_ftype_v2si_int | |
14417 | = build_function_type (integer_type_node, | |
14418 | tree_cons (NULL_TREE, V2SI_type_node, | |
14419 | tree_cons (NULL_TREE, integer_type_node, | |
14420 | endlink))); | |
14421 | tree v8qi_ftype_v8qi_int_int | |
14422 | = build_function_type (V8QI_type_node, | |
14423 | tree_cons (NULL_TREE, V8QI_type_node, | |
14424 | tree_cons (NULL_TREE, integer_type_node, | |
14425 | tree_cons (NULL_TREE, | |
14426 | integer_type_node, | |
14427 | endlink)))); | |
14428 | tree v4hi_ftype_v4hi_int_int | |
14429 | = build_function_type (V4HI_type_node, | |
14430 | tree_cons (NULL_TREE, V4HI_type_node, | |
14431 | tree_cons (NULL_TREE, integer_type_node, | |
14432 | tree_cons (NULL_TREE, | |
14433 | integer_type_node, | |
14434 | endlink)))); | |
14435 | tree v2si_ftype_v2si_int_int | |
14436 | = build_function_type (V2SI_type_node, | |
14437 | tree_cons (NULL_TREE, V2SI_type_node, | |
14438 | tree_cons (NULL_TREE, integer_type_node, | |
14439 | tree_cons (NULL_TREE, | |
14440 | integer_type_node, | |
14441 | endlink)))); | |
14442 | /* Miscellaneous. */ | |
14443 | tree v8qi_ftype_v4hi_v4hi | |
14444 | = build_function_type (V8QI_type_node, | |
14445 | tree_cons (NULL_TREE, V4HI_type_node, | |
14446 | tree_cons (NULL_TREE, V4HI_type_node, | |
14447 | endlink))); | |
14448 | tree v4hi_ftype_v2si_v2si | |
14449 | = build_function_type (V4HI_type_node, | |
14450 | tree_cons (NULL_TREE, V2SI_type_node, | |
14451 | tree_cons (NULL_TREE, V2SI_type_node, | |
14452 | endlink))); | |
14453 | tree v2si_ftype_v4hi_v4hi | |
14454 | = build_function_type (V2SI_type_node, | |
14455 | tree_cons (NULL_TREE, V4HI_type_node, | |
14456 | tree_cons (NULL_TREE, V4HI_type_node, | |
14457 | endlink))); | |
14458 | tree v2si_ftype_v8qi_v8qi | |
14459 | = build_function_type (V2SI_type_node, | |
14460 | tree_cons (NULL_TREE, V8QI_type_node, | |
14461 | tree_cons (NULL_TREE, V8QI_type_node, | |
14462 | endlink))); | |
14463 | tree v4hi_ftype_v4hi_di | |
14464 | = build_function_type (V4HI_type_node, | |
14465 | tree_cons (NULL_TREE, V4HI_type_node, | |
14466 | tree_cons (NULL_TREE, | |
14467 | long_long_integer_type_node, | |
14468 | endlink))); | |
14469 | tree v2si_ftype_v2si_di | |
14470 | = build_function_type (V2SI_type_node, | |
14471 | tree_cons (NULL_TREE, V2SI_type_node, | |
14472 | tree_cons (NULL_TREE, | |
14473 | long_long_integer_type_node, | |
14474 | endlink))); | |
14475 | tree void_ftype_int_int | |
14476 | = build_function_type (void_type_node, | |
14477 | tree_cons (NULL_TREE, integer_type_node, | |
14478 | tree_cons (NULL_TREE, integer_type_node, | |
14479 | endlink))); | |
14480 | tree di_ftype_void | |
14481 | = build_function_type (long_long_unsigned_type_node, endlink); | |
14482 | tree di_ftype_v8qi | |
14483 | = build_function_type (long_long_integer_type_node, | |
14484 | tree_cons (NULL_TREE, V8QI_type_node, | |
14485 | endlink)); | |
14486 | tree di_ftype_v4hi | |
14487 | = build_function_type (long_long_integer_type_node, | |
14488 | tree_cons (NULL_TREE, V4HI_type_node, | |
14489 | endlink)); | |
14490 | tree di_ftype_v2si | |
14491 | = build_function_type (long_long_integer_type_node, | |
14492 | tree_cons (NULL_TREE, V2SI_type_node, | |
14493 | endlink)); | |
14494 | tree v2si_ftype_v4hi | |
14495 | = build_function_type (V2SI_type_node, | |
14496 | tree_cons (NULL_TREE, V4HI_type_node, | |
14497 | endlink)); | |
14498 | tree v4hi_ftype_v8qi | |
14499 | = build_function_type (V4HI_type_node, | |
14500 | tree_cons (NULL_TREE, V8QI_type_node, | |
14501 | endlink)); | |
14502 | ||
14503 | tree di_ftype_di_v4hi_v4hi | |
14504 | = build_function_type (long_long_unsigned_type_node, | |
14505 | tree_cons (NULL_TREE, | |
14506 | long_long_unsigned_type_node, | |
14507 | tree_cons (NULL_TREE, V4HI_type_node, | |
14508 | tree_cons (NULL_TREE, | |
14509 | V4HI_type_node, | |
14510 | endlink)))); | |
14511 | ||
14512 | tree di_ftype_v4hi_v4hi | |
14513 | = build_function_type (long_long_unsigned_type_node, | |
14514 | tree_cons (NULL_TREE, V4HI_type_node, | |
14515 | tree_cons (NULL_TREE, V4HI_type_node, | |
14516 | endlink))); | |
14517 | ||
14518 | /* Normal vector binops. */ | |
14519 | tree v8qi_ftype_v8qi_v8qi | |
14520 | = build_function_type (V8QI_type_node, | |
14521 | tree_cons (NULL_TREE, V8QI_type_node, | |
14522 | tree_cons (NULL_TREE, V8QI_type_node, | |
14523 | endlink))); | |
14524 | tree v4hi_ftype_v4hi_v4hi | |
14525 | = build_function_type (V4HI_type_node, | |
14526 | tree_cons (NULL_TREE, V4HI_type_node, | |
14527 | tree_cons (NULL_TREE, V4HI_type_node, | |
14528 | endlink))); | |
14529 | tree v2si_ftype_v2si_v2si | |
14530 | = build_function_type (V2SI_type_node, | |
14531 | tree_cons (NULL_TREE, V2SI_type_node, | |
14532 | tree_cons (NULL_TREE, V2SI_type_node, | |
14533 | endlink))); | |
14534 | tree di_ftype_di_di | |
14535 | = build_function_type (long_long_unsigned_type_node, | |
14536 | tree_cons (NULL_TREE, long_long_unsigned_type_node, | |
14537 | tree_cons (NULL_TREE, | |
14538 | long_long_unsigned_type_node, | |
14539 | endlink))); | |
14540 | ||
14541 | /* Add all builtins that are more or less simple operations on two | |
14542 | operands. */ | |
e97a46ce | 14543 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef NC |
14544 | { |
14545 | /* Use one of the operands; the target can have a different mode for | |
14546 | mask-generating compares. */ | |
14547 | enum machine_mode mode; | |
14548 | tree type; | |
14549 | ||
14550 | if (d->name == 0) | |
14551 | continue; | |
14552 | ||
14553 | mode = insn_data[d->icode].operand[1].mode; | |
14554 | ||
14555 | switch (mode) | |
14556 | { | |
14557 | case V8QImode: | |
14558 | type = v8qi_ftype_v8qi_v8qi; | |
14559 | break; | |
14560 | case V4HImode: | |
14561 | type = v4hi_ftype_v4hi_v4hi; | |
14562 | break; | |
14563 | case V2SImode: | |
14564 | type = v2si_ftype_v2si_v2si; | |
14565 | break; | |
14566 | case DImode: | |
14567 | type = di_ftype_di_di; | |
14568 | break; | |
14569 | ||
14570 | default: | |
e6d29d15 | 14571 | gcc_unreachable (); |
5a9335ef NC |
14572 | } |
14573 | ||
14574 | def_mbuiltin (d->mask, d->name, type, d->code); | |
14575 | } | |
14576 | ||
14577 | /* Add the remaining MMX insns with somewhat more complicated types. */ | |
14578 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); | |
14579 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); | |
14580 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); | |
14581 | ||
14582 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); | |
14583 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); | |
14584 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); | |
14585 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); | |
14586 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); | |
14587 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); | |
14588 | ||
14589 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); | |
14590 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); | |
14591 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); | |
14592 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); | |
14593 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); | |
14594 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); | |
14595 | ||
14596 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); | |
14597 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); | |
14598 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); | |
14599 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); | |
14600 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); | |
14601 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); | |
14602 | ||
14603 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); | |
14604 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); | |
14605 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); | |
14606 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); | |
14607 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); | |
14608 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); | |
14609 | ||
14610 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); | |
14611 | ||
14612 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); | |
14613 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); | |
14614 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); | |
14615 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); | |
14616 | ||
14617 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); | |
14618 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); | |
14619 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); | |
14620 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); | |
14621 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); | |
14622 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); | |
14623 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); | |
14624 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); | |
14625 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); | |
14626 | ||
14627 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); | |
14628 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); | |
14629 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); | |
14630 | ||
14631 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); | |
14632 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); | |
14633 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); | |
14634 | ||
14635 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); | |
14636 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); | |
14637 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); | |
14638 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); | |
14639 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); | |
14640 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); | |
14641 | ||
14642 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); | |
14643 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); | |
14644 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); | |
14645 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); | |
14646 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); | |
14647 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); | |
14648 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); | |
14649 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); | |
14650 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); | |
14651 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); | |
14652 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); | |
14653 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); | |
14654 | ||
14655 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); | |
14656 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); | |
14657 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); | |
14658 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); | |
14659 | ||
14660 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); | |
14661 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); | |
14662 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); | |
14663 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); | |
14664 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); | |
14665 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); | |
14666 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); | |
14667 | } | |
14668 | ||
d3585b76 DJ |
14669 | static void |
14670 | arm_init_tls_builtins (void) | |
14671 | { | |
ebfe65a3 | 14672 | tree ftype, decl; |
d3585b76 DJ |
14673 | |
14674 | ftype = build_function_type (ptr_type_node, void_list_node); | |
ebfe65a3 JJ |
14675 | decl = add_builtin_function ("__builtin_thread_pointer", ftype, |
14676 | ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
14677 | NULL, NULL_TREE); | |
14678 | TREE_NOTHROW (decl) = 1; | |
14679 | TREE_READONLY (decl) = 1; | |
d3585b76 DJ |
14680 | } |
14681 | ||
88f77cba JB |
14682 | typedef enum { |
14683 | T_V8QI = 0x0001, | |
14684 | T_V4HI = 0x0002, | |
14685 | T_V2SI = 0x0004, | |
14686 | T_V2SF = 0x0008, | |
14687 | T_DI = 0x0010, | |
14688 | T_V16QI = 0x0020, | |
14689 | T_V8HI = 0x0040, | |
14690 | T_V4SI = 0x0080, | |
14691 | T_V4SF = 0x0100, | |
14692 | T_V2DI = 0x0200, | |
14693 | T_TI = 0x0400, | |
14694 | T_EI = 0x0800, | |
14695 | T_OI = 0x1000 | |
14696 | } neon_builtin_type_bits; | |
14697 | ||
14698 | #define v8qi_UP T_V8QI | |
14699 | #define v4hi_UP T_V4HI | |
14700 | #define v2si_UP T_V2SI | |
14701 | #define v2sf_UP T_V2SF | |
14702 | #define di_UP T_DI | |
14703 | #define v16qi_UP T_V16QI | |
14704 | #define v8hi_UP T_V8HI | |
14705 | #define v4si_UP T_V4SI | |
14706 | #define v4sf_UP T_V4SF | |
14707 | #define v2di_UP T_V2DI | |
14708 | #define ti_UP T_TI | |
14709 | #define ei_UP T_EI | |
14710 | #define oi_UP T_OI | |
14711 | ||
14712 | #define UP(X) X##_UP | |
14713 | ||
14714 | #define T_MAX 13 | |
14715 | ||
14716 | typedef enum { | |
14717 | NEON_BINOP, | |
14718 | NEON_TERNOP, | |
14719 | NEON_UNOP, | |
14720 | NEON_GETLANE, | |
14721 | NEON_SETLANE, | |
14722 | NEON_CREATE, | |
14723 | NEON_DUP, | |
14724 | NEON_DUPLANE, | |
14725 | NEON_COMBINE, | |
14726 | NEON_SPLIT, | |
14727 | NEON_LANEMUL, | |
14728 | NEON_LANEMULL, | |
14729 | NEON_LANEMULH, | |
14730 | NEON_LANEMAC, | |
14731 | NEON_SCALARMUL, | |
14732 | NEON_SCALARMULL, | |
14733 | NEON_SCALARMULH, | |
14734 | NEON_SCALARMAC, | |
14735 | NEON_CONVERT, | |
14736 | NEON_FIXCONV, | |
14737 | NEON_SELECT, | |
14738 | NEON_RESULTPAIR, | |
14739 | NEON_REINTERP, | |
14740 | NEON_VTBL, | |
14741 | NEON_VTBX, | |
14742 | NEON_LOAD1, | |
14743 | NEON_LOAD1LANE, | |
14744 | NEON_STORE1, | |
14745 | NEON_STORE1LANE, | |
14746 | NEON_LOADSTRUCT, | |
14747 | NEON_LOADSTRUCTLANE, | |
14748 | NEON_STORESTRUCT, | |
14749 | NEON_STORESTRUCTLANE, | |
14750 | NEON_LOGICBINOP, | |
14751 | NEON_SHIFTINSERT, | |
14752 | NEON_SHIFTIMM, | |
14753 | NEON_SHIFTACC | |
14754 | } neon_itype; | |
14755 | ||
14756 | typedef struct { | |
14757 | const char *name; | |
14758 | const neon_itype itype; | |
14759 | const neon_builtin_type_bits bits; | |
14760 | const enum insn_code codes[T_MAX]; | |
14761 | const unsigned int num_vars; | |
14762 | unsigned int base_fcode; | |
14763 | } neon_builtin_datum; | |
14764 | ||
14765 | #define CF(N,X) CODE_FOR_neon_##N##X | |
14766 | ||
14767 | #define VAR1(T, N, A) \ | |
14768 | #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0 | |
14769 | #define VAR2(T, N, A, B) \ | |
14770 | #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0 | |
14771 | #define VAR3(T, N, A, B, C) \ | |
14772 | #N, NEON_##T, UP (A) | UP (B) | UP (C), \ | |
14773 | { CF (N, A), CF (N, B), CF (N, C) }, 3, 0 | |
14774 | #define VAR4(T, N, A, B, C, D) \ | |
14775 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \ | |
14776 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0 | |
14777 | #define VAR5(T, N, A, B, C, D, E) \ | |
14778 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \ | |
14779 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0 | |
14780 | #define VAR6(T, N, A, B, C, D, E, F) \ | |
14781 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \ | |
14782 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0 | |
14783 | #define VAR7(T, N, A, B, C, D, E, F, G) \ | |
14784 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \ | |
14785 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
14786 | CF (N, G) }, 7, 0 | |
14787 | #define VAR8(T, N, A, B, C, D, E, F, G, H) \ | |
14788 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
14789 | | UP (H), \ | |
14790 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
14791 | CF (N, G), CF (N, H) }, 8, 0 | |
14792 | #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ | |
14793 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
14794 | | UP (H) | UP (I), \ | |
14795 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
14796 | CF (N, G), CF (N, H), CF (N, I) }, 9, 0 | |
14797 | #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ | |
14798 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
14799 | | UP (H) | UP (I) | UP (J), \ | |
14800 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
14801 | CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0 | |
14802 | ||
14803 | /* The mode entries in the following table correspond to the "key" type of the | |
14804 | instruction variant, i.e. equivalent to that which would be specified after | |
14805 | the assembler mnemonic, which usually refers to the last vector operand. | |
14806 | (Signed/unsigned/polynomial types are not differentiated between though, and | |
14807 | are all mapped onto the same mode for a given element size.) The modes | |
14808 | listed per instruction should be the same as those defined for that | |
14809 | instruction's pattern in neon.md. | |
14810 | WARNING: Variants should be listed in the same increasing order as | |
14811 | neon_builtin_type_bits. */ | |
14812 | ||
14813 | static neon_builtin_datum neon_builtin_data[] = | |
14814 | { | |
14815 | { VAR10 (BINOP, vadd, | |
14816 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14817 | { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) }, | |
14818 | { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) }, | |
14819 | { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14820 | { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14821 | { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) }, | |
14822 | { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14823 | { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14824 | { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) }, | |
14825 | { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14826 | { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) }, | |
14827 | { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) }, | |
14828 | { VAR2 (TERNOP, vqdmlal, v4hi, v2si) }, | |
14829 | { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) }, | |
14830 | { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) }, | |
14831 | { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) }, | |
14832 | { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) }, | |
14833 | { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) }, | |
14834 | { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) }, | |
14835 | { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) }, | |
14836 | { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) }, | |
14837 | { VAR2 (BINOP, vqdmull, v4hi, v2si) }, | |
14838 | { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14839 | { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14840 | { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14841 | { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) }, | |
14842 | { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) }, | |
14843 | { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) }, | |
14844 | { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14845 | { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14846 | { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14847 | { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) }, | |
14848 | { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14849 | { VAR10 (BINOP, vsub, | |
14850 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14851 | { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) }, | |
14852 | { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) }, | |
14853 | { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14854 | { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14855 | { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) }, | |
14856 | { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14857 | { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14858 | { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14859 | { VAR2 (BINOP, vcage, v2sf, v4sf) }, | |
14860 | { VAR2 (BINOP, vcagt, v2sf, v4sf) }, | |
14861 | { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14862 | { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14863 | { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) }, | |
14864 | { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14865 | { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) }, | |
14866 | { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14867 | { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14868 | { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) }, | |
14869 | { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14870 | { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14871 | { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) }, | |
14872 | { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) }, | |
14873 | { VAR2 (BINOP, vrecps, v2sf, v4sf) }, | |
14874 | { VAR2 (BINOP, vrsqrts, v2sf, v4sf) }, | |
14875 | { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14876 | { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
14877 | { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14878 | { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14879 | { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14880 | { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14881 | { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14882 | { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14883 | { VAR2 (UNOP, vcnt, v8qi, v16qi) }, | |
14884 | { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) }, | |
14885 | { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) }, | |
14886 | { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
14887 | /* FIXME: vget_lane supports more variants than this! */ | |
14888 | { VAR10 (GETLANE, vget_lane, | |
14889 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14890 | { VAR10 (SETLANE, vset_lane, | |
14891 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14892 | { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) }, | |
14893 | { VAR10 (DUP, vdup_n, | |
14894 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14895 | { VAR10 (DUPLANE, vdup_lane, | |
14896 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14897 | { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) }, | |
14898 | { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14899 | { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14900 | { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) }, | |
14901 | { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) }, | |
14902 | { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) }, | |
14903 | { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) }, | |
14904 | { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14905 | { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14906 | { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) }, | |
14907 | { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) }, | |
14908 | { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14909 | { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) }, | |
14910 | { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) }, | |
14911 | { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14912 | { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14913 | { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) }, | |
14914 | { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) }, | |
14915 | { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14916 | { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) }, | |
14917 | { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) }, | |
14918 | { VAR10 (BINOP, vext, | |
14919 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14920 | { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14921 | { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) }, | |
14922 | { VAR2 (UNOP, vrev16, v8qi, v16qi) }, | |
14923 | { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) }, | |
14924 | { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) }, | |
14925 | { VAR10 (SELECT, vbsl, | |
14926 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14927 | { VAR1 (VTBL, vtbl1, v8qi) }, | |
14928 | { VAR1 (VTBL, vtbl2, v8qi) }, | |
14929 | { VAR1 (VTBL, vtbl3, v8qi) }, | |
14930 | { VAR1 (VTBL, vtbl4, v8qi) }, | |
14931 | { VAR1 (VTBX, vtbx1, v8qi) }, | |
14932 | { VAR1 (VTBX, vtbx2, v8qi) }, | |
14933 | { VAR1 (VTBX, vtbx3, v8qi) }, | |
14934 | { VAR1 (VTBX, vtbx4, v8qi) }, | |
14935 | { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14936 | { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14937 | { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
14938 | { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) }, | |
14939 | { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) }, | |
14940 | { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) }, | |
14941 | { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) }, | |
14942 | { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) }, | |
14943 | { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14944 | { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14945 | { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14946 | { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14947 | { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14948 | { VAR10 (LOAD1, vld1, | |
14949 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14950 | { VAR10 (LOAD1LANE, vld1_lane, | |
14951 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14952 | { VAR10 (LOAD1, vld1_dup, | |
14953 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14954 | { VAR10 (STORE1, vst1, | |
14955 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14956 | { VAR10 (STORE1LANE, vst1_lane, | |
14957 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14958 | { VAR9 (LOADSTRUCT, | |
14959 | vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
14960 | { VAR7 (LOADSTRUCTLANE, vld2_lane, | |
14961 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14962 | { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
14963 | { VAR9 (STORESTRUCT, vst2, | |
14964 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
14965 | { VAR7 (STORESTRUCTLANE, vst2_lane, | |
14966 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14967 | { VAR9 (LOADSTRUCT, | |
14968 | vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
14969 | { VAR7 (LOADSTRUCTLANE, vld3_lane, | |
14970 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14971 | { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
14972 | { VAR9 (STORESTRUCT, vst3, | |
14973 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
14974 | { VAR7 (STORESTRUCTLANE, vst3_lane, | |
14975 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14976 | { VAR9 (LOADSTRUCT, vld4, | |
14977 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
14978 | { VAR7 (LOADSTRUCTLANE, vld4_lane, | |
14979 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14980 | { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
14981 | { VAR9 (STORESTRUCT, vst4, | |
14982 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
14983 | { VAR7 (STORESTRUCTLANE, vst4_lane, | |
14984 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
14985 | { VAR10 (LOGICBINOP, vand, | |
14986 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14987 | { VAR10 (LOGICBINOP, vorr, | |
14988 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14989 | { VAR10 (BINOP, veor, | |
14990 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14991 | { VAR10 (LOGICBINOP, vbic, | |
14992 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
14993 | { VAR10 (LOGICBINOP, vorn, | |
14994 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) } | |
14995 | }; | |
14996 | ||
14997 | #undef CF | |
14998 | #undef VAR1 | |
14999 | #undef VAR2 | |
15000 | #undef VAR3 | |
15001 | #undef VAR4 | |
15002 | #undef VAR5 | |
15003 | #undef VAR6 | |
15004 | #undef VAR7 | |
15005 | #undef VAR8 | |
15006 | #undef VAR9 | |
15007 | #undef VAR10 | |
15008 | ||
15009 | static void | |
15010 | arm_init_neon_builtins (void) | |
15011 | { | |
15012 | unsigned int i, fcode = ARM_BUILTIN_NEON_BASE; | |
15013 | ||
af06585a JM |
15014 | tree neon_intQI_type_node; |
15015 | tree neon_intHI_type_node; | |
15016 | tree neon_polyQI_type_node; | |
15017 | tree neon_polyHI_type_node; | |
15018 | tree neon_intSI_type_node; | |
15019 | tree neon_intDI_type_node; | |
15020 | tree neon_float_type_node; | |
15021 | ||
15022 | tree intQI_pointer_node; | |
15023 | tree intHI_pointer_node; | |
15024 | tree intSI_pointer_node; | |
15025 | tree intDI_pointer_node; | |
15026 | tree float_pointer_node; | |
15027 | ||
15028 | tree const_intQI_node; | |
15029 | tree const_intHI_node; | |
15030 | tree const_intSI_node; | |
15031 | tree const_intDI_node; | |
15032 | tree const_float_node; | |
15033 | ||
15034 | tree const_intQI_pointer_node; | |
15035 | tree const_intHI_pointer_node; | |
15036 | tree const_intSI_pointer_node; | |
15037 | tree const_intDI_pointer_node; | |
15038 | tree const_float_pointer_node; | |
15039 | ||
15040 | tree V8QI_type_node; | |
15041 | tree V4HI_type_node; | |
15042 | tree V2SI_type_node; | |
15043 | tree V2SF_type_node; | |
15044 | tree V16QI_type_node; | |
15045 | tree V8HI_type_node; | |
15046 | tree V4SI_type_node; | |
15047 | tree V4SF_type_node; | |
15048 | tree V2DI_type_node; | |
15049 | ||
15050 | tree intUQI_type_node; | |
15051 | tree intUHI_type_node; | |
15052 | tree intUSI_type_node; | |
15053 | tree intUDI_type_node; | |
15054 | ||
15055 | tree intEI_type_node; | |
15056 | tree intOI_type_node; | |
15057 | tree intCI_type_node; | |
15058 | tree intXI_type_node; | |
15059 | ||
15060 | tree V8QI_pointer_node; | |
15061 | tree V4HI_pointer_node; | |
15062 | tree V2SI_pointer_node; | |
15063 | tree V2SF_pointer_node; | |
15064 | tree V16QI_pointer_node; | |
15065 | tree V8HI_pointer_node; | |
15066 | tree V4SI_pointer_node; | |
15067 | tree V4SF_pointer_node; | |
15068 | tree V2DI_pointer_node; | |
15069 | ||
15070 | tree void_ftype_pv8qi_v8qi_v8qi; | |
15071 | tree void_ftype_pv4hi_v4hi_v4hi; | |
15072 | tree void_ftype_pv2si_v2si_v2si; | |
15073 | tree void_ftype_pv2sf_v2sf_v2sf; | |
15074 | tree void_ftype_pdi_di_di; | |
15075 | tree void_ftype_pv16qi_v16qi_v16qi; | |
15076 | tree void_ftype_pv8hi_v8hi_v8hi; | |
15077 | tree void_ftype_pv4si_v4si_v4si; | |
15078 | tree void_ftype_pv4sf_v4sf_v4sf; | |
15079 | tree void_ftype_pv2di_v2di_v2di; | |
15080 | ||
15081 | tree reinterp_ftype_dreg[5][5]; | |
15082 | tree reinterp_ftype_qreg[5][5]; | |
15083 | tree dreg_types[5], qreg_types[5]; | |
15084 | ||
88f77cba JB |
15085 | /* Create distinguished type nodes for NEON vector element types, |
15086 | and pointers to values of such types, so we can detect them later. */ | |
af06585a JM |
15087 | neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); |
15088 | neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
15089 | neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); | |
15090 | neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
15091 | neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode)); | |
15092 | neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode)); | |
15093 | neon_float_type_node = make_node (REAL_TYPE); | |
15094 | TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; | |
15095 | layout_type (neon_float_type_node); | |
15096 | ||
15097 | intQI_pointer_node = build_pointer_type (neon_intQI_type_node); | |
15098 | intHI_pointer_node = build_pointer_type (neon_intHI_type_node); | |
15099 | intSI_pointer_node = build_pointer_type (neon_intSI_type_node); | |
15100 | intDI_pointer_node = build_pointer_type (neon_intDI_type_node); | |
15101 | float_pointer_node = build_pointer_type (neon_float_type_node); | |
88f77cba JB |
15102 | |
15103 | /* Next create constant-qualified versions of the above types. */ | |
af06585a JM |
15104 | const_intQI_node = build_qualified_type (neon_intQI_type_node, |
15105 | TYPE_QUAL_CONST); | |
15106 | const_intHI_node = build_qualified_type (neon_intHI_type_node, | |
15107 | TYPE_QUAL_CONST); | |
15108 | const_intSI_node = build_qualified_type (neon_intSI_type_node, | |
15109 | TYPE_QUAL_CONST); | |
15110 | const_intDI_node = build_qualified_type (neon_intDI_type_node, | |
15111 | TYPE_QUAL_CONST); | |
15112 | const_float_node = build_qualified_type (neon_float_type_node, | |
15113 | TYPE_QUAL_CONST); | |
15114 | ||
15115 | const_intQI_pointer_node = build_pointer_type (const_intQI_node); | |
15116 | const_intHI_pointer_node = build_pointer_type (const_intHI_node); | |
15117 | const_intSI_pointer_node = build_pointer_type (const_intSI_node); | |
15118 | const_intDI_pointer_node = build_pointer_type (const_intDI_node); | |
15119 | const_float_pointer_node = build_pointer_type (const_float_node); | |
88f77cba JB |
15120 | |
15121 | /* Now create vector types based on our NEON element types. */ | |
15122 | /* 64-bit vectors. */ | |
af06585a | 15123 | V8QI_type_node = |
88f77cba | 15124 | build_vector_type_for_mode (neon_intQI_type_node, V8QImode); |
af06585a | 15125 | V4HI_type_node = |
88f77cba | 15126 | build_vector_type_for_mode (neon_intHI_type_node, V4HImode); |
af06585a | 15127 | V2SI_type_node = |
88f77cba | 15128 | build_vector_type_for_mode (neon_intSI_type_node, V2SImode); |
af06585a | 15129 | V2SF_type_node = |
88f77cba JB |
15130 | build_vector_type_for_mode (neon_float_type_node, V2SFmode); |
15131 | /* 128-bit vectors. */ | |
af06585a | 15132 | V16QI_type_node = |
88f77cba | 15133 | build_vector_type_for_mode (neon_intQI_type_node, V16QImode); |
af06585a | 15134 | V8HI_type_node = |
88f77cba | 15135 | build_vector_type_for_mode (neon_intHI_type_node, V8HImode); |
af06585a | 15136 | V4SI_type_node = |
88f77cba | 15137 | build_vector_type_for_mode (neon_intSI_type_node, V4SImode); |
af06585a | 15138 | V4SF_type_node = |
88f77cba | 15139 | build_vector_type_for_mode (neon_float_type_node, V4SFmode); |
af06585a | 15140 | V2DI_type_node = |
88f77cba JB |
15141 | build_vector_type_for_mode (neon_intDI_type_node, V2DImode); |
15142 | ||
15143 | /* Unsigned integer types for various mode sizes. */ | |
af06585a JM |
15144 | intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode)); |
15145 | intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode)); | |
15146 | intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode)); | |
15147 | intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode)); | |
88f77cba | 15148 | |
88f77cba | 15149 | /* Opaque integer types for structures of vectors. */ |
af06585a JM |
15150 | intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode)); |
15151 | intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode)); | |
15152 | intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode)); | |
15153 | intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode)); | |
88f77cba | 15154 | |
88f77cba | 15155 | /* Pointers to vector types. */ |
af06585a JM |
15156 | V8QI_pointer_node = build_pointer_type (V8QI_type_node); |
15157 | V4HI_pointer_node = build_pointer_type (V4HI_type_node); | |
15158 | V2SI_pointer_node = build_pointer_type (V2SI_type_node); | |
15159 | V2SF_pointer_node = build_pointer_type (V2SF_type_node); | |
15160 | V16QI_pointer_node = build_pointer_type (V16QI_type_node); | |
15161 | V8HI_pointer_node = build_pointer_type (V8HI_type_node); | |
15162 | V4SI_pointer_node = build_pointer_type (V4SI_type_node); | |
15163 | V4SF_pointer_node = build_pointer_type (V4SF_type_node); | |
15164 | V2DI_pointer_node = build_pointer_type (V2DI_type_node); | |
88f77cba JB |
15165 | |
15166 | /* Operations which return results as pairs. */ | |
af06585a | 15167 | void_ftype_pv8qi_v8qi_v8qi = |
88f77cba JB |
15168 | build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node, |
15169 | V8QI_type_node, NULL); | |
af06585a | 15170 | void_ftype_pv4hi_v4hi_v4hi = |
88f77cba JB |
15171 | build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node, |
15172 | V4HI_type_node, NULL); | |
af06585a | 15173 | void_ftype_pv2si_v2si_v2si = |
88f77cba JB |
15174 | build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node, |
15175 | V2SI_type_node, NULL); | |
af06585a | 15176 | void_ftype_pv2sf_v2sf_v2sf = |
88f77cba JB |
15177 | build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node, |
15178 | V2SF_type_node, NULL); | |
af06585a | 15179 | void_ftype_pdi_di_di = |
88f77cba JB |
15180 | build_function_type_list (void_type_node, intDI_pointer_node, |
15181 | neon_intDI_type_node, neon_intDI_type_node, NULL); | |
af06585a | 15182 | void_ftype_pv16qi_v16qi_v16qi = |
88f77cba JB |
15183 | build_function_type_list (void_type_node, V16QI_pointer_node, |
15184 | V16QI_type_node, V16QI_type_node, NULL); | |
af06585a | 15185 | void_ftype_pv8hi_v8hi_v8hi = |
88f77cba JB |
15186 | build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node, |
15187 | V8HI_type_node, NULL); | |
af06585a | 15188 | void_ftype_pv4si_v4si_v4si = |
88f77cba JB |
15189 | build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node, |
15190 | V4SI_type_node, NULL); | |
af06585a | 15191 | void_ftype_pv4sf_v4sf_v4sf = |
88f77cba JB |
15192 | build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node, |
15193 | V4SF_type_node, NULL); | |
af06585a | 15194 | void_ftype_pv2di_v2di_v2di = |
88f77cba JB |
15195 | build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node, |
15196 | V2DI_type_node, NULL); | |
15197 | ||
466e4b7a KK |
15198 | /* Define typedefs which exactly correspond to the modes we are basing vector |
15199 | types on. If you change these names you'll need to change | |
15200 | the table used by arm_mangle_type too. */ | |
15201 | (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node, | |
15202 | "__builtin_neon_qi"); | |
15203 | (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, | |
15204 | "__builtin_neon_hi"); | |
15205 | (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, | |
15206 | "__builtin_neon_si"); | |
15207 | (*lang_hooks.types.register_builtin_type) (neon_float_type_node, | |
15208 | "__builtin_neon_sf"); | |
15209 | (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node, | |
15210 | "__builtin_neon_di"); | |
15211 | ||
15212 | (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node, | |
15213 | "__builtin_neon_poly8"); | |
15214 | (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node, | |
15215 | "__builtin_neon_poly16"); | |
15216 | (*lang_hooks.types.register_builtin_type) (intUQI_type_node, | |
15217 | "__builtin_neon_uqi"); | |
15218 | (*lang_hooks.types.register_builtin_type) (intUHI_type_node, | |
15219 | "__builtin_neon_uhi"); | |
15220 | (*lang_hooks.types.register_builtin_type) (intUSI_type_node, | |
15221 | "__builtin_neon_usi"); | |
15222 | (*lang_hooks.types.register_builtin_type) (intUDI_type_node, | |
15223 | "__builtin_neon_udi"); | |
15224 | ||
15225 | (*lang_hooks.types.register_builtin_type) (intTI_type_node, | |
15226 | "__builtin_neon_ti"); | |
15227 | (*lang_hooks.types.register_builtin_type) (intEI_type_node, | |
15228 | "__builtin_neon_ei"); | |
15229 | (*lang_hooks.types.register_builtin_type) (intOI_type_node, | |
15230 | "__builtin_neon_oi"); | |
15231 | (*lang_hooks.types.register_builtin_type) (intCI_type_node, | |
15232 | "__builtin_neon_ci"); | |
15233 | (*lang_hooks.types.register_builtin_type) (intXI_type_node, | |
15234 | "__builtin_neon_xi"); | |
15235 | ||
88f77cba JB |
15236 | dreg_types[0] = V8QI_type_node; |
15237 | dreg_types[1] = V4HI_type_node; | |
15238 | dreg_types[2] = V2SI_type_node; | |
15239 | dreg_types[3] = V2SF_type_node; | |
15240 | dreg_types[4] = neon_intDI_type_node; | |
15241 | ||
15242 | qreg_types[0] = V16QI_type_node; | |
15243 | qreg_types[1] = V8HI_type_node; | |
15244 | qreg_types[2] = V4SI_type_node; | |
15245 | qreg_types[3] = V4SF_type_node; | |
15246 | qreg_types[4] = V2DI_type_node; | |
15247 | ||
15248 | for (i = 0; i < 5; i++) | |
15249 | { | |
15250 | int j; | |
15251 | for (j = 0; j < 5; j++) | |
15252 | { | |
15253 | reinterp_ftype_dreg[i][j] | |
15254 | = build_function_type_list (dreg_types[i], dreg_types[j], NULL); | |
15255 | reinterp_ftype_qreg[i][j] | |
15256 | = build_function_type_list (qreg_types[i], qreg_types[j], NULL); | |
15257 | } | |
15258 | } | |
15259 | ||
15260 | for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++) | |
15261 | { | |
15262 | neon_builtin_datum *d = &neon_builtin_data[i]; | |
15263 | unsigned int j, codeidx = 0; | |
15264 | ||
15265 | d->base_fcode = fcode; | |
15266 | ||
15267 | for (j = 0; j < T_MAX; j++) | |
15268 | { | |
15269 | const char* const modenames[] = { | |
15270 | "v8qi", "v4hi", "v2si", "v2sf", "di", | |
15271 | "v16qi", "v8hi", "v4si", "v4sf", "v2di" | |
15272 | }; | |
15273 | char namebuf[60]; | |
15274 | tree ftype = NULL; | |
15275 | enum insn_code icode; | |
15276 | int is_load = 0, is_store = 0; | |
15277 | ||
15278 | if ((d->bits & (1 << j)) == 0) | |
15279 | continue; | |
15280 | ||
15281 | icode = d->codes[codeidx++]; | |
15282 | ||
15283 | switch (d->itype) | |
15284 | { | |
15285 | case NEON_LOAD1: | |
15286 | case NEON_LOAD1LANE: | |
15287 | case NEON_LOADSTRUCT: | |
15288 | case NEON_LOADSTRUCTLANE: | |
15289 | is_load = 1; | |
15290 | /* Fall through. */ | |
15291 | case NEON_STORE1: | |
15292 | case NEON_STORE1LANE: | |
15293 | case NEON_STORESTRUCT: | |
15294 | case NEON_STORESTRUCTLANE: | |
15295 | if (!is_load) | |
15296 | is_store = 1; | |
15297 | /* Fall through. */ | |
15298 | case NEON_UNOP: | |
15299 | case NEON_BINOP: | |
15300 | case NEON_LOGICBINOP: | |
15301 | case NEON_SHIFTINSERT: | |
15302 | case NEON_TERNOP: | |
15303 | case NEON_GETLANE: | |
15304 | case NEON_SETLANE: | |
15305 | case NEON_CREATE: | |
15306 | case NEON_DUP: | |
15307 | case NEON_DUPLANE: | |
15308 | case NEON_SHIFTIMM: | |
15309 | case NEON_SHIFTACC: | |
15310 | case NEON_COMBINE: | |
15311 | case NEON_SPLIT: | |
15312 | case NEON_CONVERT: | |
15313 | case NEON_FIXCONV: | |
15314 | case NEON_LANEMUL: | |
15315 | case NEON_LANEMULL: | |
15316 | case NEON_LANEMULH: | |
15317 | case NEON_LANEMAC: | |
15318 | case NEON_SCALARMUL: | |
15319 | case NEON_SCALARMULL: | |
15320 | case NEON_SCALARMULH: | |
15321 | case NEON_SCALARMAC: | |
15322 | case NEON_SELECT: | |
15323 | case NEON_VTBL: | |
15324 | case NEON_VTBX: | |
15325 | { | |
15326 | int k; | |
15327 | tree return_type = void_type_node, args = void_list_node; | |
15328 | ||
15329 | /* Build a function type directly from the insn_data for this | |
15330 | builtin. The build_function_type() function takes care of | |
15331 | removing duplicates for us. */ | |
15332 | for (k = insn_data[icode].n_operands - 1; k >= 0; k--) | |
15333 | { | |
15334 | tree eltype; | |
15335 | ||
15336 | if (is_load && k == 1) | |
15337 | { | |
15338 | /* Neon load patterns always have the memory operand | |
15339 | (a SImode pointer) in the operand 1 position. We | |
15340 | want a const pointer to the element type in that | |
15341 | position. */ | |
15342 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
15343 | ||
15344 | switch (1 << j) | |
15345 | { | |
15346 | case T_V8QI: | |
15347 | case T_V16QI: | |
15348 | eltype = const_intQI_pointer_node; | |
15349 | break; | |
15350 | ||
15351 | case T_V4HI: | |
15352 | case T_V8HI: | |
15353 | eltype = const_intHI_pointer_node; | |
15354 | break; | |
15355 | ||
15356 | case T_V2SI: | |
15357 | case T_V4SI: | |
15358 | eltype = const_intSI_pointer_node; | |
15359 | break; | |
15360 | ||
15361 | case T_V2SF: | |
15362 | case T_V4SF: | |
15363 | eltype = const_float_pointer_node; | |
15364 | break; | |
15365 | ||
15366 | case T_DI: | |
15367 | case T_V2DI: | |
15368 | eltype = const_intDI_pointer_node; | |
15369 | break; | |
15370 | ||
15371 | default: gcc_unreachable (); | |
15372 | } | |
15373 | } | |
15374 | else if (is_store && k == 0) | |
15375 | { | |
15376 | /* Similarly, Neon store patterns use operand 0 as | |
15377 | the memory location to store to (a SImode pointer). | |
15378 | Use a pointer to the element type of the store in | |
15379 | that position. */ | |
15380 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
15381 | ||
15382 | switch (1 << j) | |
15383 | { | |
15384 | case T_V8QI: | |
15385 | case T_V16QI: | |
15386 | eltype = intQI_pointer_node; | |
15387 | break; | |
15388 | ||
15389 | case T_V4HI: | |
15390 | case T_V8HI: | |
15391 | eltype = intHI_pointer_node; | |
15392 | break; | |
15393 | ||
15394 | case T_V2SI: | |
15395 | case T_V4SI: | |
15396 | eltype = intSI_pointer_node; | |
15397 | break; | |
15398 | ||
15399 | case T_V2SF: | |
15400 | case T_V4SF: | |
15401 | eltype = float_pointer_node; | |
15402 | break; | |
15403 | ||
15404 | case T_DI: | |
15405 | case T_V2DI: | |
15406 | eltype = intDI_pointer_node; | |
15407 | break; | |
15408 | ||
15409 | default: gcc_unreachable (); | |
15410 | } | |
15411 | } | |
15412 | else | |
15413 | { | |
15414 | switch (insn_data[icode].operand[k].mode) | |
15415 | { | |
15416 | case VOIDmode: eltype = void_type_node; break; | |
15417 | /* Scalars. */ | |
15418 | case QImode: eltype = neon_intQI_type_node; break; | |
15419 | case HImode: eltype = neon_intHI_type_node; break; | |
15420 | case SImode: eltype = neon_intSI_type_node; break; | |
15421 | case SFmode: eltype = neon_float_type_node; break; | |
15422 | case DImode: eltype = neon_intDI_type_node; break; | |
15423 | case TImode: eltype = intTI_type_node; break; | |
15424 | case EImode: eltype = intEI_type_node; break; | |
15425 | case OImode: eltype = intOI_type_node; break; | |
15426 | case CImode: eltype = intCI_type_node; break; | |
15427 | case XImode: eltype = intXI_type_node; break; | |
15428 | /* 64-bit vectors. */ | |
15429 | case V8QImode: eltype = V8QI_type_node; break; | |
15430 | case V4HImode: eltype = V4HI_type_node; break; | |
15431 | case V2SImode: eltype = V2SI_type_node; break; | |
15432 | case V2SFmode: eltype = V2SF_type_node; break; | |
15433 | /* 128-bit vectors. */ | |
15434 | case V16QImode: eltype = V16QI_type_node; break; | |
15435 | case V8HImode: eltype = V8HI_type_node; break; | |
15436 | case V4SImode: eltype = V4SI_type_node; break; | |
15437 | case V4SFmode: eltype = V4SF_type_node; break; | |
15438 | case V2DImode: eltype = V2DI_type_node; break; | |
15439 | default: gcc_unreachable (); | |
15440 | } | |
15441 | } | |
15442 | ||
15443 | if (k == 0 && !is_store) | |
15444 | return_type = eltype; | |
15445 | else | |
15446 | args = tree_cons (NULL_TREE, eltype, args); | |
15447 | } | |
15448 | ||
15449 | ftype = build_function_type (return_type, args); | |
15450 | } | |
15451 | break; | |
15452 | ||
15453 | case NEON_RESULTPAIR: | |
15454 | { | |
15455 | switch (insn_data[icode].operand[1].mode) | |
15456 | { | |
15457 | case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break; | |
15458 | case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break; | |
15459 | case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break; | |
15460 | case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break; | |
15461 | case DImode: ftype = void_ftype_pdi_di_di; break; | |
15462 | case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break; | |
15463 | case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break; | |
15464 | case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break; | |
15465 | case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break; | |
15466 | case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break; | |
15467 | default: gcc_unreachable (); | |
15468 | } | |
15469 | } | |
15470 | break; | |
15471 | ||
15472 | case NEON_REINTERP: | |
15473 | { | |
15474 | /* We iterate over 5 doubleword types, then 5 quadword | |
15475 | types. */ | |
15476 | int rhs = j % 5; | |
15477 | switch (insn_data[icode].operand[0].mode) | |
15478 | { | |
15479 | case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; | |
15480 | case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break; | |
15481 | case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break; | |
15482 | case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break; | |
15483 | case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break; | |
15484 | case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break; | |
15485 | case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break; | |
15486 | case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break; | |
15487 | case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break; | |
15488 | case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break; | |
15489 | default: gcc_unreachable (); | |
15490 | } | |
15491 | } | |
15492 | break; | |
15493 | ||
15494 | default: | |
15495 | gcc_unreachable (); | |
15496 | } | |
15497 | ||
15498 | gcc_assert (ftype != NULL); | |
15499 | ||
15500 | sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]); | |
15501 | ||
15502 | add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL, | |
15503 | NULL_TREE); | |
15504 | } | |
15505 | } | |
15506 | } | |
15507 | ||
5a9335ef NC |
15508 | static void |
15509 | arm_init_builtins (void) | |
15510 | { | |
d3585b76 DJ |
15511 | arm_init_tls_builtins (); |
15512 | ||
5a9335ef NC |
15513 | if (TARGET_REALLY_IWMMXT) |
15514 | arm_init_iwmmxt_builtins (); | |
88f77cba JB |
15515 | |
15516 | if (TARGET_NEON) | |
15517 | arm_init_neon_builtins (); | |
5a9335ef NC |
15518 | } |
15519 | ||
15520 | /* Errors in the source file can cause expand_expr to return const0_rtx | |
15521 | where we expect a vector. To avoid crashing, use one of the vector | |
15522 | clear instructions. */ | |
15523 | ||
15524 | static rtx | |
15525 | safe_vector_operand (rtx x, enum machine_mode mode) | |
15526 | { | |
15527 | if (x != const0_rtx) | |
15528 | return x; | |
15529 | x = gen_reg_rtx (mode); | |
15530 | ||
15531 | emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x | |
15532 | : gen_rtx_SUBREG (DImode, x, 0))); | |
15533 | return x; | |
15534 | } | |
15535 | ||
15536 | /* Subroutine of arm_expand_builtin to take care of binop insns. */ | |
15537 | ||
15538 | static rtx | |
15539 | arm_expand_binop_builtin (enum insn_code icode, | |
5039610b | 15540 | tree exp, rtx target) |
5a9335ef NC |
15541 | { |
15542 | rtx pat; | |
5039610b SL |
15543 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
15544 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
15545 | rtx op0 = expand_normal (arg0); |
15546 | rtx op1 = expand_normal (arg1); | |
5a9335ef NC |
15547 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
15548 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
15549 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
15550 | ||
15551 | if (VECTOR_MODE_P (mode0)) | |
15552 | op0 = safe_vector_operand (op0, mode0); | |
15553 | if (VECTOR_MODE_P (mode1)) | |
15554 | op1 = safe_vector_operand (op1, mode1); | |
15555 | ||
15556 | if (! target | |
15557 | || GET_MODE (target) != tmode | |
15558 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
15559 | target = gen_reg_rtx (tmode); | |
15560 | ||
e6d29d15 | 15561 | gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); |
5a9335ef NC |
15562 | |
15563 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
15564 | op0 = copy_to_mode_reg (mode0, op0); | |
15565 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
15566 | op1 = copy_to_mode_reg (mode1, op1); | |
15567 | ||
15568 | pat = GEN_FCN (icode) (target, op0, op1); | |
15569 | if (! pat) | |
15570 | return 0; | |
15571 | emit_insn (pat); | |
15572 | return target; | |
15573 | } | |
15574 | ||
15575 | /* Subroutine of arm_expand_builtin to take care of unop insns. */ | |
15576 | ||
15577 | static rtx | |
15578 | arm_expand_unop_builtin (enum insn_code icode, | |
5039610b | 15579 | tree exp, rtx target, int do_load) |
5a9335ef NC |
15580 | { |
15581 | rtx pat; | |
5039610b | 15582 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 15583 | rtx op0 = expand_normal (arg0); |
5a9335ef NC |
15584 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
15585 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
15586 | ||
15587 | if (! target | |
15588 | || GET_MODE (target) != tmode | |
15589 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
15590 | target = gen_reg_rtx (tmode); | |
15591 | if (do_load) | |
15592 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
15593 | else | |
15594 | { | |
15595 | if (VECTOR_MODE_P (mode0)) | |
15596 | op0 = safe_vector_operand (op0, mode0); | |
15597 | ||
15598 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
15599 | op0 = copy_to_mode_reg (mode0, op0); | |
15600 | } | |
15601 | ||
15602 | pat = GEN_FCN (icode) (target, op0); | |
15603 | if (! pat) | |
15604 | return 0; | |
15605 | emit_insn (pat); | |
15606 | return target; | |
15607 | } | |
15608 | ||
88f77cba JB |
15609 | static int |
15610 | neon_builtin_compare (const void *a, const void *b) | |
15611 | { | |
15612 | const neon_builtin_datum *key = a; | |
15613 | const neon_builtin_datum *memb = b; | |
15614 | unsigned int soughtcode = key->base_fcode; | |
15615 | ||
15616 | if (soughtcode >= memb->base_fcode | |
15617 | && soughtcode < memb->base_fcode + memb->num_vars) | |
15618 | return 0; | |
15619 | else if (soughtcode < memb->base_fcode) | |
15620 | return -1; | |
15621 | else | |
15622 | return 1; | |
15623 | } | |
15624 | ||
15625 | static enum insn_code | |
15626 | locate_neon_builtin_icode (int fcode, neon_itype *itype) | |
15627 | { | |
15628 | neon_builtin_datum key, *found; | |
15629 | int idx; | |
15630 | ||
15631 | key.base_fcode = fcode; | |
15632 | found = bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data), | |
15633 | sizeof (neon_builtin_data[0]), neon_builtin_compare); | |
15634 | gcc_assert (found); | |
15635 | idx = fcode - (int) found->base_fcode; | |
15636 | gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars); | |
15637 | ||
15638 | if (itype) | |
15639 | *itype = found->itype; | |
15640 | ||
15641 | return found->codes[idx]; | |
15642 | } | |
15643 | ||
15644 | typedef enum { | |
15645 | NEON_ARG_COPY_TO_REG, | |
15646 | NEON_ARG_CONSTANT, | |
15647 | NEON_ARG_STOP | |
15648 | } builtin_arg; | |
15649 | ||
15650 | #define NEON_MAX_BUILTIN_ARGS 5 | |
15651 | ||
15652 | /* Expand a Neon builtin. */ | |
15653 | static rtx | |
15654 | arm_expand_neon_args (rtx target, int icode, int have_retval, | |
15655 | tree exp, ...) | |
15656 | { | |
15657 | va_list ap; | |
15658 | rtx pat; | |
15659 | tree arg[NEON_MAX_BUILTIN_ARGS]; | |
15660 | rtx op[NEON_MAX_BUILTIN_ARGS]; | |
15661 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
15662 | enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; | |
15663 | int argc = 0; | |
15664 | ||
15665 | if (have_retval | |
15666 | && (!target | |
15667 | || GET_MODE (target) != tmode | |
15668 | || !(*insn_data[icode].operand[0].predicate) (target, tmode))) | |
15669 | target = gen_reg_rtx (tmode); | |
15670 | ||
15671 | va_start (ap, exp); | |
15672 | ||
15673 | for (;;) | |
15674 | { | |
15675 | builtin_arg thisarg = va_arg (ap, int); | |
15676 | ||
15677 | if (thisarg == NEON_ARG_STOP) | |
15678 | break; | |
15679 | else | |
15680 | { | |
15681 | arg[argc] = CALL_EXPR_ARG (exp, argc); | |
15682 | op[argc] = expand_normal (arg[argc]); | |
15683 | mode[argc] = insn_data[icode].operand[argc + have_retval].mode; | |
15684 | ||
15685 | switch (thisarg) | |
15686 | { | |
15687 | case NEON_ARG_COPY_TO_REG: | |
15688 | /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ | |
15689 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
15690 | (op[argc], mode[argc])) | |
15691 | op[argc] = copy_to_mode_reg (mode[argc], op[argc]); | |
15692 | break; | |
15693 | ||
15694 | case NEON_ARG_CONSTANT: | |
15695 | /* FIXME: This error message is somewhat unhelpful. */ | |
15696 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
15697 | (op[argc], mode[argc])) | |
15698 | error ("argument must be a constant"); | |
15699 | break; | |
15700 | ||
15701 | case NEON_ARG_STOP: | |
15702 | gcc_unreachable (); | |
15703 | } | |
15704 | ||
15705 | argc++; | |
15706 | } | |
15707 | } | |
15708 | ||
15709 | va_end (ap); | |
15710 | ||
15711 | if (have_retval) | |
15712 | switch (argc) | |
15713 | { | |
15714 | case 1: | |
15715 | pat = GEN_FCN (icode) (target, op[0]); | |
15716 | break; | |
15717 | ||
15718 | case 2: | |
15719 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
15720 | break; | |
15721 | ||
15722 | case 3: | |
15723 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2]); | |
15724 | break; | |
15725 | ||
15726 | case 4: | |
15727 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]); | |
15728 | break; | |
15729 | ||
15730 | case 5: | |
15731 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); | |
15732 | break; | |
15733 | ||
15734 | default: | |
15735 | gcc_unreachable (); | |
15736 | } | |
15737 | else | |
15738 | switch (argc) | |
15739 | { | |
15740 | case 1: | |
15741 | pat = GEN_FCN (icode) (op[0]); | |
15742 | break; | |
15743 | ||
15744 | case 2: | |
15745 | pat = GEN_FCN (icode) (op[0], op[1]); | |
15746 | break; | |
15747 | ||
15748 | case 3: | |
15749 | pat = GEN_FCN (icode) (op[0], op[1], op[2]); | |
15750 | break; | |
15751 | ||
15752 | case 4: | |
15753 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); | |
15754 | break; | |
15755 | ||
15756 | case 5: | |
15757 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); | |
15758 | break; | |
15759 | ||
15760 | default: | |
15761 | gcc_unreachable (); | |
15762 | } | |
15763 | ||
15764 | if (!pat) | |
15765 | return 0; | |
15766 | ||
15767 | emit_insn (pat); | |
15768 | ||
15769 | return target; | |
15770 | } | |
15771 | ||
15772 | /* Expand a Neon builtin. These are "special" because they don't have symbolic | |
15773 | constants defined per-instruction or per instruction-variant. Instead, the | |
15774 | required info is looked up in the table neon_builtin_data. */ | |
15775 | static rtx | |
15776 | arm_expand_neon_builtin (int fcode, tree exp, rtx target) | |
15777 | { | |
15778 | neon_itype itype; | |
15779 | enum insn_code icode = locate_neon_builtin_icode (fcode, &itype); | |
15780 | ||
15781 | switch (itype) | |
15782 | { | |
15783 | case NEON_UNOP: | |
15784 | case NEON_CONVERT: | |
15785 | case NEON_DUPLANE: | |
15786 | return arm_expand_neon_args (target, icode, 1, exp, | |
15787 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
15788 | ||
15789 | case NEON_BINOP: | |
15790 | case NEON_SETLANE: | |
15791 | case NEON_SCALARMUL: | |
15792 | case NEON_SCALARMULL: | |
15793 | case NEON_SCALARMULH: | |
15794 | case NEON_SHIFTINSERT: | |
15795 | case NEON_LOGICBINOP: | |
15796 | return arm_expand_neon_args (target, icode, 1, exp, | |
15797 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
15798 | NEON_ARG_STOP); | |
15799 | ||
15800 | case NEON_TERNOP: | |
15801 | return arm_expand_neon_args (target, icode, 1, exp, | |
15802 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
15803 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
15804 | ||
15805 | case NEON_GETLANE: | |
15806 | case NEON_FIXCONV: | |
15807 | case NEON_SHIFTIMM: | |
15808 | return arm_expand_neon_args (target, icode, 1, exp, | |
15809 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, | |
15810 | NEON_ARG_STOP); | |
15811 | ||
15812 | case NEON_CREATE: | |
15813 | return arm_expand_neon_args (target, icode, 1, exp, | |
15814 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
15815 | ||
15816 | case NEON_DUP: | |
15817 | case NEON_SPLIT: | |
15818 | case NEON_REINTERP: | |
15819 | return arm_expand_neon_args (target, icode, 1, exp, | |
15820 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
15821 | ||
15822 | case NEON_COMBINE: | |
15823 | case NEON_VTBL: | |
15824 | return arm_expand_neon_args (target, icode, 1, exp, | |
15825 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
15826 | ||
15827 | case NEON_RESULTPAIR: | |
15828 | return arm_expand_neon_args (target, icode, 0, exp, | |
15829 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
15830 | NEON_ARG_STOP); | |
15831 | ||
15832 | case NEON_LANEMUL: | |
15833 | case NEON_LANEMULL: | |
15834 | case NEON_LANEMULH: | |
15835 | return arm_expand_neon_args (target, icode, 1, exp, | |
15836 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
15837 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
15838 | ||
15839 | case NEON_LANEMAC: | |
15840 | return arm_expand_neon_args (target, icode, 1, exp, | |
15841 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
15842 | NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
15843 | ||
15844 | case NEON_SHIFTACC: | |
15845 | return arm_expand_neon_args (target, icode, 1, exp, | |
15846 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
15847 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
15848 | ||
15849 | case NEON_SCALARMAC: | |
15850 | return arm_expand_neon_args (target, icode, 1, exp, | |
15851 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
15852 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
15853 | ||
15854 | case NEON_SELECT: | |
15855 | case NEON_VTBX: | |
15856 | return arm_expand_neon_args (target, icode, 1, exp, | |
15857 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
15858 | NEON_ARG_STOP); | |
15859 | ||
15860 | case NEON_LOAD1: | |
15861 | case NEON_LOADSTRUCT: | |
15862 | return arm_expand_neon_args (target, icode, 1, exp, | |
15863 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
15864 | ||
15865 | case NEON_LOAD1LANE: | |
15866 | case NEON_LOADSTRUCTLANE: | |
15867 | return arm_expand_neon_args (target, icode, 1, exp, | |
15868 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
15869 | NEON_ARG_STOP); | |
15870 | ||
15871 | case NEON_STORE1: | |
15872 | case NEON_STORESTRUCT: | |
15873 | return arm_expand_neon_args (target, icode, 0, exp, | |
15874 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
15875 | ||
15876 | case NEON_STORE1LANE: | |
15877 | case NEON_STORESTRUCTLANE: | |
15878 | return arm_expand_neon_args (target, icode, 0, exp, | |
15879 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
15880 | NEON_ARG_STOP); | |
15881 | } | |
15882 | ||
15883 | gcc_unreachable (); | |
15884 | } | |
15885 | ||
15886 | /* Emit code to reinterpret one Neon type as another, without altering bits. */ | |
15887 | void | |
15888 | neon_reinterpret (rtx dest, rtx src) | |
15889 | { | |
15890 | emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src)); | |
15891 | } | |
15892 | ||
15893 | /* Emit code to place a Neon pair result in memory locations (with equal | |
15894 | registers). */ | |
15895 | void | |
15896 | neon_emit_pair_result_insn (enum machine_mode mode, | |
15897 | rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr, | |
15898 | rtx op1, rtx op2) | |
15899 | { | |
15900 | rtx mem = gen_rtx_MEM (mode, destaddr); | |
15901 | rtx tmp1 = gen_reg_rtx (mode); | |
15902 | rtx tmp2 = gen_reg_rtx (mode); | |
15903 | ||
15904 | emit_insn (intfn (tmp1, op1, tmp2, op2)); | |
15905 | ||
15906 | emit_move_insn (mem, tmp1); | |
15907 | mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); | |
15908 | emit_move_insn (mem, tmp2); | |
15909 | } | |
15910 | ||
15911 | /* Set up operands for a register copy from src to dest, taking care not to | |
15912 | clobber registers in the process. | |
15913 | FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't | |
15914 | be called with a large N, so that should be OK. */ | |
15915 | ||
15916 | void | |
15917 | neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count) | |
15918 | { | |
15919 | unsigned int copied = 0, opctr = 0; | |
15920 | unsigned int done = (1 << count) - 1; | |
15921 | unsigned int i, j; | |
15922 | ||
15923 | while (copied != done) | |
15924 | { | |
15925 | for (i = 0; i < count; i++) | |
15926 | { | |
15927 | int good = 1; | |
15928 | ||
15929 | for (j = 0; good && j < count; j++) | |
15930 | if (i != j && (copied & (1 << j)) == 0 | |
15931 | && reg_overlap_mentioned_p (src[j], dest[i])) | |
15932 | good = 0; | |
15933 | ||
15934 | if (good) | |
15935 | { | |
15936 | operands[opctr++] = dest[i]; | |
15937 | operands[opctr++] = src[i]; | |
15938 | copied |= 1 << i; | |
15939 | } | |
15940 | } | |
15941 | } | |
15942 | ||
15943 | gcc_assert (opctr == count * 2); | |
15944 | } | |
15945 | ||
5a9335ef NC |
15946 | /* Expand an expression EXP that calls a built-in function, |
15947 | with result going to TARGET if that's convenient | |
15948 | (and in mode MODE if that's convenient). | |
15949 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
15950 | IGNORE is nonzero if the value is to be ignored. */ | |
15951 | ||
15952 | static rtx | |
15953 | arm_expand_builtin (tree exp, | |
15954 | rtx target, | |
15955 | rtx subtarget ATTRIBUTE_UNUSED, | |
15956 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
15957 | int ignore ATTRIBUTE_UNUSED) | |
15958 | { | |
15959 | const struct builtin_description * d; | |
15960 | enum insn_code icode; | |
5039610b | 15961 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
5a9335ef NC |
15962 | tree arg0; |
15963 | tree arg1; | |
15964 | tree arg2; | |
15965 | rtx op0; | |
15966 | rtx op1; | |
15967 | rtx op2; | |
15968 | rtx pat; | |
15969 | int fcode = DECL_FUNCTION_CODE (fndecl); | |
15970 | size_t i; | |
15971 | enum machine_mode tmode; | |
15972 | enum machine_mode mode0; | |
15973 | enum machine_mode mode1; | |
15974 | enum machine_mode mode2; | |
15975 | ||
88f77cba JB |
15976 | if (fcode >= ARM_BUILTIN_NEON_BASE) |
15977 | return arm_expand_neon_builtin (fcode, exp, target); | |
15978 | ||
5a9335ef NC |
15979 | switch (fcode) |
15980 | { | |
15981 | case ARM_BUILTIN_TEXTRMSB: | |
15982 | case ARM_BUILTIN_TEXTRMUB: | |
15983 | case ARM_BUILTIN_TEXTRMSH: | |
15984 | case ARM_BUILTIN_TEXTRMUH: | |
15985 | case ARM_BUILTIN_TEXTRMSW: | |
15986 | case ARM_BUILTIN_TEXTRMUW: | |
15987 | icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb | |
15988 | : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub | |
15989 | : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh | |
15990 | : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh | |
15991 | : CODE_FOR_iwmmxt_textrmw); | |
15992 | ||
5039610b SL |
15993 | arg0 = CALL_EXPR_ARG (exp, 0); |
15994 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
15995 | op0 = expand_normal (arg0); |
15996 | op1 = expand_normal (arg1); | |
5a9335ef NC |
15997 | tmode = insn_data[icode].operand[0].mode; |
15998 | mode0 = insn_data[icode].operand[1].mode; | |
15999 | mode1 = insn_data[icode].operand[2].mode; | |
16000 | ||
16001 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16002 | op0 = copy_to_mode_reg (mode0, op0); | |
16003 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16004 | { | |
16005 | /* @@@ better error message */ | |
16006 | error ("selector must be an immediate"); | |
16007 | return gen_reg_rtx (tmode); | |
16008 | } | |
16009 | if (target == 0 | |
16010 | || GET_MODE (target) != tmode | |
16011 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16012 | target = gen_reg_rtx (tmode); | |
16013 | pat = GEN_FCN (icode) (target, op0, op1); | |
16014 | if (! pat) | |
16015 | return 0; | |
16016 | emit_insn (pat); | |
16017 | return target; | |
16018 | ||
16019 | case ARM_BUILTIN_TINSRB: | |
16020 | case ARM_BUILTIN_TINSRH: | |
16021 | case ARM_BUILTIN_TINSRW: | |
16022 | icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb | |
16023 | : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh | |
16024 | : CODE_FOR_iwmmxt_tinsrw); | |
5039610b SL |
16025 | arg0 = CALL_EXPR_ARG (exp, 0); |
16026 | arg1 = CALL_EXPR_ARG (exp, 1); | |
16027 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
16028 | op0 = expand_normal (arg0); |
16029 | op1 = expand_normal (arg1); | |
16030 | op2 = expand_normal (arg2); | |
5a9335ef NC |
16031 | tmode = insn_data[icode].operand[0].mode; |
16032 | mode0 = insn_data[icode].operand[1].mode; | |
16033 | mode1 = insn_data[icode].operand[2].mode; | |
16034 | mode2 = insn_data[icode].operand[3].mode; | |
16035 | ||
16036 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16037 | op0 = copy_to_mode_reg (mode0, op0); | |
16038 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16039 | op1 = copy_to_mode_reg (mode1, op1); | |
16040 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
16041 | { | |
16042 | /* @@@ better error message */ | |
16043 | error ("selector must be an immediate"); | |
16044 | return const0_rtx; | |
16045 | } | |
16046 | if (target == 0 | |
16047 | || GET_MODE (target) != tmode | |
16048 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16049 | target = gen_reg_rtx (tmode); | |
16050 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
16051 | if (! pat) | |
16052 | return 0; | |
16053 | emit_insn (pat); | |
16054 | return target; | |
16055 | ||
16056 | case ARM_BUILTIN_SETWCX: | |
5039610b SL |
16057 | arg0 = CALL_EXPR_ARG (exp, 0); |
16058 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
16059 | op0 = force_reg (SImode, expand_normal (arg0)); |
16060 | op1 = expand_normal (arg1); | |
f07a6b21 | 16061 | emit_insn (gen_iwmmxt_tmcr (op1, op0)); |
5a9335ef NC |
16062 | return 0; |
16063 | ||
16064 | case ARM_BUILTIN_GETWCX: | |
5039610b | 16065 | arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 16066 | op0 = expand_normal (arg0); |
5a9335ef NC |
16067 | target = gen_reg_rtx (SImode); |
16068 | emit_insn (gen_iwmmxt_tmrc (target, op0)); | |
16069 | return target; | |
16070 | ||
16071 | case ARM_BUILTIN_WSHUFH: | |
16072 | icode = CODE_FOR_iwmmxt_wshufh; | |
5039610b SL |
16073 | arg0 = CALL_EXPR_ARG (exp, 0); |
16074 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
16075 | op0 = expand_normal (arg0); |
16076 | op1 = expand_normal (arg1); | |
5a9335ef NC |
16077 | tmode = insn_data[icode].operand[0].mode; |
16078 | mode1 = insn_data[icode].operand[1].mode; | |
16079 | mode2 = insn_data[icode].operand[2].mode; | |
16080 | ||
16081 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) | |
16082 | op0 = copy_to_mode_reg (mode1, op0); | |
16083 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) | |
16084 | { | |
16085 | /* @@@ better error message */ | |
16086 | error ("mask must be an immediate"); | |
16087 | return const0_rtx; | |
16088 | } | |
16089 | if (target == 0 | |
16090 | || GET_MODE (target) != tmode | |
16091 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16092 | target = gen_reg_rtx (tmode); | |
16093 | pat = GEN_FCN (icode) (target, op0, op1); | |
16094 | if (! pat) | |
16095 | return 0; | |
16096 | emit_insn (pat); | |
16097 | return target; | |
16098 | ||
16099 | case ARM_BUILTIN_WSADB: | |
5039610b | 16100 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target); |
5a9335ef | 16101 | case ARM_BUILTIN_WSADH: |
5039610b | 16102 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target); |
5a9335ef | 16103 | case ARM_BUILTIN_WSADBZ: |
5039610b | 16104 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target); |
5a9335ef | 16105 | case ARM_BUILTIN_WSADHZ: |
5039610b | 16106 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target); |
5a9335ef NC |
16107 | |
16108 | /* Several three-argument builtins. */ | |
16109 | case ARM_BUILTIN_WMACS: | |
16110 | case ARM_BUILTIN_WMACU: | |
16111 | case ARM_BUILTIN_WALIGN: | |
16112 | case ARM_BUILTIN_TMIA: | |
16113 | case ARM_BUILTIN_TMIAPH: | |
16114 | case ARM_BUILTIN_TMIATT: | |
16115 | case ARM_BUILTIN_TMIATB: | |
16116 | case ARM_BUILTIN_TMIABT: | |
16117 | case ARM_BUILTIN_TMIABB: | |
16118 | icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs | |
16119 | : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu | |
16120 | : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia | |
16121 | : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph | |
16122 | : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb | |
16123 | : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt | |
16124 | : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb | |
16125 | : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt | |
16126 | : CODE_FOR_iwmmxt_walign); | |
5039610b SL |
16127 | arg0 = CALL_EXPR_ARG (exp, 0); |
16128 | arg1 = CALL_EXPR_ARG (exp, 1); | |
16129 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
16130 | op0 = expand_normal (arg0); |
16131 | op1 = expand_normal (arg1); | |
16132 | op2 = expand_normal (arg2); | |
5a9335ef NC |
16133 | tmode = insn_data[icode].operand[0].mode; |
16134 | mode0 = insn_data[icode].operand[1].mode; | |
16135 | mode1 = insn_data[icode].operand[2].mode; | |
16136 | mode2 = insn_data[icode].operand[3].mode; | |
16137 | ||
16138 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16139 | op0 = copy_to_mode_reg (mode0, op0); | |
16140 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16141 | op1 = copy_to_mode_reg (mode1, op1); | |
16142 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
16143 | op2 = copy_to_mode_reg (mode2, op2); | |
16144 | if (target == 0 | |
16145 | || GET_MODE (target) != tmode | |
16146 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16147 | target = gen_reg_rtx (tmode); | |
16148 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
16149 | if (! pat) | |
16150 | return 0; | |
16151 | emit_insn (pat); | |
16152 | return target; | |
f676971a | 16153 | |
5a9335ef NC |
16154 | case ARM_BUILTIN_WZERO: |
16155 | target = gen_reg_rtx (DImode); | |
16156 | emit_insn (gen_iwmmxt_clrdi (target)); | |
16157 | return target; | |
16158 | ||
d3585b76 DJ |
16159 | case ARM_BUILTIN_THREAD_POINTER: |
16160 | return arm_load_tp (target); | |
16161 | ||
5a9335ef NC |
16162 | default: |
16163 | break; | |
16164 | } | |
16165 | ||
e97a46ce | 16166 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef | 16167 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 16168 | return arm_expand_binop_builtin (d->icode, exp, target); |
5a9335ef | 16169 | |
e97a46ce | 16170 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
5a9335ef | 16171 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 16172 | return arm_expand_unop_builtin (d->icode, exp, target, 0); |
5a9335ef NC |
16173 | |
16174 | /* @@@ Should really do something sensible here. */ | |
16175 | return NULL_RTX; | |
16176 | } | |
16177 | \f | |
1d6e90ac NC |
16178 | /* Return the number (counting from 0) of |
16179 | the least significant set bit in MASK. */ | |
16180 | ||
e32bac5b | 16181 | inline static int |
b279b20a | 16182 | number_of_first_bit_set (unsigned mask) |
d5b7b3ae RE |
16183 | { |
16184 | int bit; | |
16185 | ||
16186 | for (bit = 0; | |
16187 | (mask & (1 << bit)) == 0; | |
5895f793 | 16188 | ++bit) |
d5b7b3ae RE |
16189 | continue; |
16190 | ||
16191 | return bit; | |
16192 | } | |
16193 | ||
b279b20a NC |
16194 | /* Emit code to push or pop registers to or from the stack. F is the |
16195 | assembly file. MASK is the registers to push or pop. PUSH is | |
16196 | nonzero if we should push, and zero if we should pop. For debugging | |
16197 | output, if pushing, adjust CFA_OFFSET by the amount of space added | |
16198 | to the stack. REAL_REGS should have the same number of bits set as | |
16199 | MASK, and will be used instead (in the same order) to describe which | |
16200 | registers were saved - this is used to mark the save slots when we | |
16201 | push high registers after moving them to low registers. */ | |
16202 | static void | |
16203 | thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset, | |
16204 | unsigned long real_regs) | |
16205 | { | |
16206 | int regno; | |
16207 | int lo_mask = mask & 0xFF; | |
16208 | int pushed_words = 0; | |
16209 | ||
e6d29d15 | 16210 | gcc_assert (mask); |
b279b20a NC |
16211 | |
16212 | if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM))) | |
16213 | { | |
16214 | /* Special case. Do not generate a POP PC statement here, do it in | |
16215 | thumb_exit() */ | |
16216 | thumb_exit (f, -1); | |
16217 | return; | |
16218 | } | |
16219 | ||
617a1b71 PB |
16220 | if (ARM_EABI_UNWIND_TABLES && push) |
16221 | { | |
16222 | fprintf (f, "\t.save\t{"); | |
16223 | for (regno = 0; regno < 15; regno++) | |
16224 | { | |
16225 | if (real_regs & (1 << regno)) | |
16226 | { | |
16227 | if (real_regs & ((1 << regno) -1)) | |
16228 | fprintf (f, ", "); | |
16229 | asm_fprintf (f, "%r", regno); | |
16230 | } | |
16231 | } | |
16232 | fprintf (f, "}\n"); | |
16233 | } | |
16234 | ||
b279b20a NC |
16235 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); |
16236 | ||
16237 | /* Look at the low registers first. */ | |
16238 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) | |
16239 | { | |
16240 | if (lo_mask & 1) | |
16241 | { | |
16242 | asm_fprintf (f, "%r", regno); | |
16243 | ||
16244 | if ((lo_mask & ~1) != 0) | |
16245 | fprintf (f, ", "); | |
16246 | ||
16247 | pushed_words++; | |
16248 | } | |
16249 | } | |
16250 | ||
16251 | if (push && (mask & (1 << LR_REGNUM))) | |
16252 | { | |
16253 | /* Catch pushing the LR. */ | |
16254 | if (mask & 0xFF) | |
16255 | fprintf (f, ", "); | |
16256 | ||
16257 | asm_fprintf (f, "%r", LR_REGNUM); | |
16258 | ||
16259 | pushed_words++; | |
16260 | } | |
16261 | else if (!push && (mask & (1 << PC_REGNUM))) | |
16262 | { | |
16263 | /* Catch popping the PC. */ | |
16264 | if (TARGET_INTERWORK || TARGET_BACKTRACE | |
e3b5732b | 16265 | || crtl->calls_eh_return) |
b279b20a NC |
16266 | { |
16267 | /* The PC is never poped directly, instead | |
16268 | it is popped into r3 and then BX is used. */ | |
16269 | fprintf (f, "}\n"); | |
16270 | ||
16271 | thumb_exit (f, -1); | |
16272 | ||
16273 | return; | |
16274 | } | |
16275 | else | |
16276 | { | |
16277 | if (mask & 0xFF) | |
16278 | fprintf (f, ", "); | |
16279 | ||
16280 | asm_fprintf (f, "%r", PC_REGNUM); | |
16281 | } | |
16282 | } | |
16283 | ||
16284 | fprintf (f, "}\n"); | |
16285 | ||
16286 | if (push && pushed_words && dwarf2out_do_frame ()) | |
16287 | { | |
16288 | char *l = dwarf2out_cfi_label (); | |
16289 | int pushed_mask = real_regs; | |
16290 | ||
16291 | *cfa_offset += pushed_words * 4; | |
16292 | dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); | |
16293 | ||
16294 | pushed_words = 0; | |
16295 | pushed_mask = real_regs; | |
16296 | for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) | |
16297 | { | |
16298 | if (pushed_mask & 1) | |
16299 | dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); | |
16300 | } | |
16301 | } | |
16302 | } | |
16303 | ||
d5b7b3ae RE |
16304 | /* Generate code to return from a thumb function. |
16305 | If 'reg_containing_return_addr' is -1, then the return address is | |
16306 | actually on the stack, at the stack pointer. */ | |
16307 | static void | |
c9ca9b88 | 16308 | thumb_exit (FILE *f, int reg_containing_return_addr) |
d5b7b3ae RE |
16309 | { |
16310 | unsigned regs_available_for_popping; | |
16311 | unsigned regs_to_pop; | |
16312 | int pops_needed; | |
16313 | unsigned available; | |
16314 | unsigned required; | |
16315 | int mode; | |
16316 | int size; | |
16317 | int restore_a4 = FALSE; | |
16318 | ||
16319 | /* Compute the registers we need to pop. */ | |
16320 | regs_to_pop = 0; | |
16321 | pops_needed = 0; | |
16322 | ||
c9ca9b88 | 16323 | if (reg_containing_return_addr == -1) |
d5b7b3ae | 16324 | { |
d5b7b3ae | 16325 | regs_to_pop |= 1 << LR_REGNUM; |
5895f793 | 16326 | ++pops_needed; |
d5b7b3ae RE |
16327 | } |
16328 | ||
16329 | if (TARGET_BACKTRACE) | |
16330 | { | |
16331 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
16332 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
16333 | pops_needed += 2; | |
16334 | } | |
16335 | ||
16336 | /* If there is nothing to pop then just emit the BX instruction and | |
16337 | return. */ | |
16338 | if (pops_needed == 0) | |
16339 | { | |
e3b5732b | 16340 | if (crtl->calls_eh_return) |
c9ca9b88 | 16341 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
16342 | |
16343 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
16344 | return; | |
16345 | } | |
16346 | /* Otherwise if we are not supporting interworking and we have not created | |
16347 | a backtrace structure and the function was not entered in ARM mode then | |
16348 | just pop the return address straight into the PC. */ | |
5895f793 RE |
16349 | else if (!TARGET_INTERWORK |
16350 | && !TARGET_BACKTRACE | |
c9ca9b88 | 16351 | && !is_called_in_ARM_mode (current_function_decl) |
e3b5732b | 16352 | && !crtl->calls_eh_return) |
d5b7b3ae | 16353 | { |
c9ca9b88 | 16354 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); |
d5b7b3ae RE |
16355 | return; |
16356 | } | |
16357 | ||
16358 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
16359 | regs_available_for_popping = 0; | |
16360 | ||
16361 | /* If returning via __builtin_eh_return, the bottom three registers | |
16362 | all contain information needed for the return. */ | |
e3b5732b | 16363 | if (crtl->calls_eh_return) |
d5b7b3ae RE |
16364 | size = 12; |
16365 | else | |
16366 | { | |
d5b7b3ae RE |
16367 | /* If we can deduce the registers used from the function's |
16368 | return value. This is more reliable that examining | |
6fb5fa3c | 16369 | df_regs_ever_live_p () because that will be set if the register is |
d5b7b3ae RE |
16370 | ever used in the function, not just if the register is used |
16371 | to hold a return value. */ | |
16372 | ||
38173d38 JH |
16373 | if (crtl->return_rtx != 0) |
16374 | mode = GET_MODE (crtl->return_rtx); | |
d5b7b3ae | 16375 | else |
d5b7b3ae RE |
16376 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); |
16377 | ||
16378 | size = GET_MODE_SIZE (mode); | |
16379 | ||
16380 | if (size == 0) | |
16381 | { | |
16382 | /* In a void function we can use any argument register. | |
16383 | In a function that returns a structure on the stack | |
16384 | we can use the second and third argument registers. */ | |
16385 | if (mode == VOIDmode) | |
16386 | regs_available_for_popping = | |
16387 | (1 << ARG_REGISTER (1)) | |
16388 | | (1 << ARG_REGISTER (2)) | |
16389 | | (1 << ARG_REGISTER (3)); | |
16390 | else | |
16391 | regs_available_for_popping = | |
16392 | (1 << ARG_REGISTER (2)) | |
16393 | | (1 << ARG_REGISTER (3)); | |
16394 | } | |
16395 | else if (size <= 4) | |
16396 | regs_available_for_popping = | |
16397 | (1 << ARG_REGISTER (2)) | |
16398 | | (1 << ARG_REGISTER (3)); | |
16399 | else if (size <= 8) | |
16400 | regs_available_for_popping = | |
16401 | (1 << ARG_REGISTER (3)); | |
16402 | } | |
16403 | ||
16404 | /* Match registers to be popped with registers into which we pop them. */ | |
16405 | for (available = regs_available_for_popping, | |
16406 | required = regs_to_pop; | |
16407 | required != 0 && available != 0; | |
16408 | available &= ~(available & - available), | |
16409 | required &= ~(required & - required)) | |
16410 | -- pops_needed; | |
16411 | ||
16412 | /* If we have any popping registers left over, remove them. */ | |
16413 | if (available > 0) | |
5895f793 | 16414 | regs_available_for_popping &= ~available; |
f676971a | 16415 | |
d5b7b3ae RE |
16416 | /* Otherwise if we need another popping register we can use |
16417 | the fourth argument register. */ | |
16418 | else if (pops_needed) | |
16419 | { | |
16420 | /* If we have not found any free argument registers and | |
16421 | reg a4 contains the return address, we must move it. */ | |
16422 | if (regs_available_for_popping == 0 | |
16423 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
16424 | { | |
16425 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
16426 | reg_containing_return_addr = LR_REGNUM; | |
16427 | } | |
16428 | else if (size > 12) | |
16429 | { | |
16430 | /* Register a4 is being used to hold part of the return value, | |
16431 | but we have dire need of a free, low register. */ | |
16432 | restore_a4 = TRUE; | |
f676971a | 16433 | |
d5b7b3ae RE |
16434 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); |
16435 | } | |
f676971a | 16436 | |
d5b7b3ae RE |
16437 | if (reg_containing_return_addr != LAST_ARG_REGNUM) |
16438 | { | |
16439 | /* The fourth argument register is available. */ | |
16440 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
f676971a | 16441 | |
5895f793 | 16442 | --pops_needed; |
d5b7b3ae RE |
16443 | } |
16444 | } | |
16445 | ||
16446 | /* Pop as many registers as we can. */ | |
980e61bb DJ |
16447 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
16448 | regs_available_for_popping); | |
d5b7b3ae RE |
16449 | |
16450 | /* Process the registers we popped. */ | |
16451 | if (reg_containing_return_addr == -1) | |
16452 | { | |
16453 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 16454 | regs_to_pop &= ~(1 << LR_REGNUM); |
f676971a | 16455 | |
d5b7b3ae RE |
16456 | reg_containing_return_addr = |
16457 | number_of_first_bit_set (regs_available_for_popping); | |
16458 | ||
16459 | /* Remove this register for the mask of available registers, so that | |
6bc82793 | 16460 | the return address will not be corrupted by further pops. */ |
5895f793 | 16461 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
16462 | } |
16463 | ||
16464 | /* If we popped other registers then handle them here. */ | |
16465 | if (regs_available_for_popping) | |
16466 | { | |
16467 | int frame_pointer; | |
f676971a | 16468 | |
d5b7b3ae RE |
16469 | /* Work out which register currently contains the frame pointer. */ |
16470 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
16471 | ||
16472 | /* Move it into the correct place. */ | |
16473 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
16474 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
16475 | ||
16476 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
16477 | regs_available_for_popping &= ~(1 << frame_pointer); |
16478 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
f676971a | 16479 | |
d5b7b3ae RE |
16480 | if (regs_available_for_popping) |
16481 | { | |
16482 | int stack_pointer; | |
f676971a | 16483 | |
d5b7b3ae RE |
16484 | /* We popped the stack pointer as well, |
16485 | find the register that contains it. */ | |
16486 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
16487 | ||
16488 | /* Move it into the stack register. */ | |
16489 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
f676971a | 16490 | |
d5b7b3ae RE |
16491 | /* At this point we have popped all necessary registers, so |
16492 | do not worry about restoring regs_available_for_popping | |
16493 | to its correct value: | |
16494 | ||
16495 | assert (pops_needed == 0) | |
16496 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
16497 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
16498 | } | |
16499 | else | |
16500 | { | |
16501 | /* Since we have just move the popped value into the frame | |
16502 | pointer, the popping register is available for reuse, and | |
16503 | we know that we still have the stack pointer left to pop. */ | |
16504 | regs_available_for_popping |= (1 << frame_pointer); | |
16505 | } | |
16506 | } | |
f676971a | 16507 | |
d5b7b3ae RE |
16508 | /* If we still have registers left on the stack, but we no longer have |
16509 | any registers into which we can pop them, then we must move the return | |
16510 | address into the link register and make available the register that | |
16511 | contained it. */ | |
16512 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
16513 | { | |
16514 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
f676971a | 16515 | |
d5b7b3ae RE |
16516 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, |
16517 | reg_containing_return_addr); | |
f676971a | 16518 | |
d5b7b3ae RE |
16519 | reg_containing_return_addr = LR_REGNUM; |
16520 | } | |
16521 | ||
16522 | /* If we have registers left on the stack then pop some more. | |
16523 | We know that at most we will want to pop FP and SP. */ | |
16524 | if (pops_needed > 0) | |
16525 | { | |
16526 | int popped_into; | |
16527 | int move_to; | |
f676971a | 16528 | |
980e61bb DJ |
16529 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
16530 | regs_available_for_popping); | |
d5b7b3ae RE |
16531 | |
16532 | /* We have popped either FP or SP. | |
16533 | Move whichever one it is into the correct register. */ | |
16534 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
16535 | move_to = number_of_first_bit_set (regs_to_pop); | |
16536 | ||
16537 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
16538 | ||
5895f793 | 16539 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 16540 | |
5895f793 | 16541 | --pops_needed; |
d5b7b3ae | 16542 | } |
f676971a | 16543 | |
d5b7b3ae RE |
16544 | /* If we still have not popped everything then we must have only |
16545 | had one register available to us and we are now popping the SP. */ | |
16546 | if (pops_needed > 0) | |
16547 | { | |
16548 | int popped_into; | |
f676971a | 16549 | |
980e61bb DJ |
16550 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
16551 | regs_available_for_popping); | |
d5b7b3ae RE |
16552 | |
16553 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
16554 | ||
16555 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
16556 | /* | |
16557 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
16558 | assert (pops_needed == 1) | |
16559 | */ | |
16560 | } | |
16561 | ||
16562 | /* If necessary restore the a4 register. */ | |
16563 | if (restore_a4) | |
16564 | { | |
16565 | if (reg_containing_return_addr != LR_REGNUM) | |
16566 | { | |
16567 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
16568 | reg_containing_return_addr = LR_REGNUM; | |
16569 | } | |
f676971a | 16570 | |
d5b7b3ae RE |
16571 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
16572 | } | |
16573 | ||
e3b5732b | 16574 | if (crtl->calls_eh_return) |
c9ca9b88 | 16575 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
16576 | |
16577 | /* Return to caller. */ | |
16578 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
16579 | } | |
16580 | ||
d5b7b3ae RE |
16581 | \f |
16582 | void | |
5b3e6663 | 16583 | thumb1_final_prescan_insn (rtx insn) |
d5b7b3ae | 16584 | { |
d5b7b3ae | 16585 | if (flag_print_asm_name) |
9d98a694 AO |
16586 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
16587 | INSN_ADDRESSES (INSN_UID (insn))); | |
d5b7b3ae RE |
16588 | } |
16589 | ||
16590 | int | |
e32bac5b | 16591 | thumb_shiftable_const (unsigned HOST_WIDE_INT val) |
d5b7b3ae RE |
16592 | { |
16593 | unsigned HOST_WIDE_INT mask = 0xff; | |
16594 | int i; | |
16595 | ||
16596 | if (val == 0) /* XXX */ | |
16597 | return 0; | |
f676971a | 16598 | |
d5b7b3ae RE |
16599 | for (i = 0; i < 25; i++) |
16600 | if ((val & (mask << i)) == val) | |
16601 | return 1; | |
16602 | ||
16603 | return 0; | |
16604 | } | |
16605 | ||
825dda42 | 16606 | /* Returns nonzero if the current function contains, |
d5b7b3ae | 16607 | or might contain a far jump. */ |
5848830f PB |
16608 | static int |
16609 | thumb_far_jump_used_p (void) | |
d5b7b3ae RE |
16610 | { |
16611 | rtx insn; | |
16612 | ||
16613 | /* This test is only important for leaf functions. */ | |
5895f793 | 16614 | /* assert (!leaf_function_p ()); */ |
f676971a | 16615 | |
d5b7b3ae RE |
16616 | /* If we have already decided that far jumps may be used, |
16617 | do not bother checking again, and always return true even if | |
16618 | it turns out that they are not being used. Once we have made | |
16619 | the decision that far jumps are present (and that hence the link | |
16620 | register will be pushed onto the stack) we cannot go back on it. */ | |
16621 | if (cfun->machine->far_jump_used) | |
16622 | return 1; | |
16623 | ||
16624 | /* If this function is not being called from the prologue/epilogue | |
16625 | generation code then it must be being called from the | |
16626 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5848830f | 16627 | if (!(ARM_DOUBLEWORD_ALIGN || reload_completed)) |
d5b7b3ae RE |
16628 | { |
16629 | /* In this case we know that we are being asked about the elimination | |
16630 | of the arg pointer register. If that register is not being used, | |
16631 | then there are no arguments on the stack, and we do not have to | |
16632 | worry that a far jump might force the prologue to push the link | |
16633 | register, changing the stack offsets. In this case we can just | |
16634 | return false, since the presence of far jumps in the function will | |
16635 | not affect stack offsets. | |
16636 | ||
16637 | If the arg pointer is live (or if it was live, but has now been | |
16638 | eliminated and so set to dead) then we do have to test to see if | |
16639 | the function might contain a far jump. This test can lead to some | |
16640 | false negatives, since before reload is completed, then length of | |
16641 | branch instructions is not known, so gcc defaults to returning their | |
16642 | longest length, which in turn sets the far jump attribute to true. | |
16643 | ||
16644 | A false negative will not result in bad code being generated, but it | |
16645 | will result in a needless push and pop of the link register. We | |
5848830f PB |
16646 | hope that this does not occur too often. |
16647 | ||
16648 | If we need doubleword stack alignment this could affect the other | |
16649 | elimination offsets so we can't risk getting it wrong. */ | |
6fb5fa3c | 16650 | if (df_regs_ever_live_p (ARG_POINTER_REGNUM)) |
d5b7b3ae | 16651 | cfun->machine->arg_pointer_live = 1; |
5895f793 | 16652 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
16653 | return 0; |
16654 | } | |
16655 | ||
16656 | /* Check to see if the function contains a branch | |
16657 | insn with the far jump attribute set. */ | |
16658 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
16659 | { | |
16660 | if (GET_CODE (insn) == JUMP_INSN | |
16661 | /* Ignore tablejump patterns. */ | |
16662 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
16663 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
16664 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
16665 | ) | |
16666 | { | |
9a9f7594 | 16667 | /* Record the fact that we have decided that |
d5b7b3ae RE |
16668 | the function does use far jumps. */ |
16669 | cfun->machine->far_jump_used = 1; | |
16670 | return 1; | |
16671 | } | |
16672 | } | |
f676971a | 16673 | |
d5b7b3ae RE |
16674 | return 0; |
16675 | } | |
16676 | ||
825dda42 | 16677 | /* Return nonzero if FUNC must be entered in ARM mode. */ |
d5b7b3ae | 16678 | int |
e32bac5b | 16679 | is_called_in_ARM_mode (tree func) |
d5b7b3ae | 16680 | { |
e6d29d15 | 16681 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
d5b7b3ae | 16682 | |
696e78bf | 16683 | /* Ignore the problem about functions whose address is taken. */ |
d5b7b3ae RE |
16684 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) |
16685 | return TRUE; | |
16686 | ||
f676971a | 16687 | #ifdef ARM_PE |
91d231cb | 16688 | return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; |
d5b7b3ae RE |
16689 | #else |
16690 | return FALSE; | |
16691 | #endif | |
16692 | } | |
16693 | ||
d6b4baa4 | 16694 | /* The bits which aren't usefully expanded as rtl. */ |
cd2b33d0 | 16695 | const char * |
e32bac5b | 16696 | thumb_unexpanded_epilogue (void) |
d5b7b3ae | 16697 | { |
954954d1 | 16698 | arm_stack_offsets *offsets; |
d5b7b3ae | 16699 | int regno; |
b279b20a | 16700 | unsigned long live_regs_mask = 0; |
d5b7b3ae | 16701 | int high_regs_pushed = 0; |
d5b7b3ae | 16702 | int had_to_push_lr; |
57934c39 | 16703 | int size; |
d5b7b3ae RE |
16704 | |
16705 | if (return_used_this_function) | |
16706 | return ""; | |
16707 | ||
58e60158 AN |
16708 | if (IS_NAKED (arm_current_func_type ())) |
16709 | return ""; | |
16710 | ||
954954d1 PB |
16711 | offsets = arm_get_frame_offsets (); |
16712 | live_regs_mask = offsets->saved_regs_mask; | |
57934c39 PB |
16713 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); |
16714 | ||
16715 | /* If we can deduce the registers used from the function's return value. | |
6fb5fa3c | 16716 | This is more reliable that examining df_regs_ever_live_p () because that |
57934c39 PB |
16717 | will be set if the register is ever used in the function, not just if |
16718 | the register is used to hold a return value. */ | |
4f5dfed0 | 16719 | size = arm_size_return_regs (); |
d5b7b3ae RE |
16720 | |
16721 | /* The prolog may have pushed some high registers to use as | |
112cdef5 | 16722 | work registers. e.g. the testsuite file: |
d5b7b3ae RE |
16723 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c |
16724 | compiles to produce: | |
16725 | push {r4, r5, r6, r7, lr} | |
16726 | mov r7, r9 | |
16727 | mov r6, r8 | |
16728 | push {r6, r7} | |
16729 | as part of the prolog. We have to undo that pushing here. */ | |
f676971a | 16730 | |
d5b7b3ae RE |
16731 | if (high_regs_pushed) |
16732 | { | |
b279b20a | 16733 | unsigned long mask = live_regs_mask & 0xff; |
d5b7b3ae | 16734 | int next_hi_reg; |
d5b7b3ae | 16735 | |
57934c39 PB |
16736 | /* The available low registers depend on the size of the value we are |
16737 | returning. */ | |
16738 | if (size <= 12) | |
d5b7b3ae | 16739 | mask |= 1 << 3; |
57934c39 PB |
16740 | if (size <= 8) |
16741 | mask |= 1 << 2; | |
d5b7b3ae RE |
16742 | |
16743 | if (mask == 0) | |
16744 | /* Oh dear! We have no low registers into which we can pop | |
16745 | high registers! */ | |
400500c4 RK |
16746 | internal_error |
16747 | ("no low registers available for popping high registers"); | |
f676971a | 16748 | |
d5b7b3ae | 16749 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 16750 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
16751 | break; |
16752 | ||
16753 | while (high_regs_pushed) | |
16754 | { | |
16755 | /* Find lo register(s) into which the high register(s) can | |
16756 | be popped. */ | |
16757 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
16758 | { | |
16759 | if (mask & (1 << regno)) | |
16760 | high_regs_pushed--; | |
16761 | if (high_regs_pushed == 0) | |
16762 | break; | |
16763 | } | |
16764 | ||
16765 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
16766 | ||
d6b4baa4 | 16767 | /* Pop the values into the low register(s). */ |
980e61bb | 16768 | thumb_pushpop (asm_out_file, mask, 0, NULL, mask); |
d5b7b3ae RE |
16769 | |
16770 | /* Move the value(s) into the high registers. */ | |
16771 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
16772 | { | |
16773 | if (mask & (1 << regno)) | |
16774 | { | |
16775 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
16776 | regno); | |
f676971a | 16777 | |
d5b7b3ae | 16778 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 16779 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
16780 | break; |
16781 | } | |
16782 | } | |
16783 | } | |
57934c39 | 16784 | live_regs_mask &= ~0x0f00; |
d5b7b3ae RE |
16785 | } |
16786 | ||
57934c39 PB |
16787 | had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0; |
16788 | live_regs_mask &= 0xff; | |
16789 | ||
38173d38 | 16790 | if (crtl->args.pretend_args_size == 0 || TARGET_BACKTRACE) |
d5b7b3ae | 16791 | { |
f676971a | 16792 | /* Pop the return address into the PC. */ |
57934c39 | 16793 | if (had_to_push_lr) |
d5b7b3ae RE |
16794 | live_regs_mask |= 1 << PC_REGNUM; |
16795 | ||
16796 | /* Either no argument registers were pushed or a backtrace | |
16797 | structure was created which includes an adjusted stack | |
16798 | pointer, so just pop everything. */ | |
16799 | if (live_regs_mask) | |
980e61bb DJ |
16800 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
16801 | live_regs_mask); | |
57934c39 | 16802 | |
d5b7b3ae | 16803 | /* We have either just popped the return address into the |
57934c39 PB |
16804 | PC or it is was kept in LR for the entire function. */ |
16805 | if (!had_to_push_lr) | |
16806 | thumb_exit (asm_out_file, LR_REGNUM); | |
d5b7b3ae RE |
16807 | } |
16808 | else | |
16809 | { | |
16810 | /* Pop everything but the return address. */ | |
d5b7b3ae | 16811 | if (live_regs_mask) |
980e61bb DJ |
16812 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
16813 | live_regs_mask); | |
d5b7b3ae RE |
16814 | |
16815 | if (had_to_push_lr) | |
57934c39 PB |
16816 | { |
16817 | if (size > 12) | |
16818 | { | |
16819 | /* We have no free low regs, so save one. */ | |
16820 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM, | |
16821 | LAST_ARG_REGNUM); | |
16822 | } | |
16823 | ||
16824 | /* Get the return address into a temporary register. */ | |
16825 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, | |
16826 | 1 << LAST_ARG_REGNUM); | |
16827 | ||
16828 | if (size > 12) | |
16829 | { | |
16830 | /* Move the return address to lr. */ | |
16831 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM, | |
16832 | LAST_ARG_REGNUM); | |
16833 | /* Restore the low register. */ | |
16834 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, | |
16835 | IP_REGNUM); | |
16836 | regno = LR_REGNUM; | |
16837 | } | |
16838 | else | |
16839 | regno = LAST_ARG_REGNUM; | |
16840 | } | |
16841 | else | |
16842 | regno = LR_REGNUM; | |
f676971a | 16843 | |
d5b7b3ae RE |
16844 | /* Remove the argument registers that were pushed onto the stack. */ |
16845 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
16846 | SP_REGNUM, SP_REGNUM, | |
38173d38 | 16847 | crtl->args.pretend_args_size); |
f676971a | 16848 | |
57934c39 | 16849 | thumb_exit (asm_out_file, regno); |
d5b7b3ae RE |
16850 | } |
16851 | ||
16852 | return ""; | |
16853 | } | |
16854 | ||
16855 | /* Functions to save and restore machine-specific function data. */ | |
e2500fed | 16856 | static struct machine_function * |
e32bac5b | 16857 | arm_init_machine_status (void) |
d5b7b3ae | 16858 | { |
e2500fed GK |
16859 | struct machine_function *machine; |
16860 | machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); | |
6d3d9133 | 16861 | |
f676971a | 16862 | #if ARM_FT_UNKNOWN != 0 |
e2500fed | 16863 | machine->func_type = ARM_FT_UNKNOWN; |
6d3d9133 | 16864 | #endif |
e2500fed | 16865 | return machine; |
f7a80099 NC |
16866 | } |
16867 | ||
d5b7b3ae RE |
16868 | /* Return an RTX indicating where the return address to the |
16869 | calling function can be found. */ | |
16870 | rtx | |
e32bac5b | 16871 | arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
d5b7b3ae | 16872 | { |
d5b7b3ae RE |
16873 | if (count != 0) |
16874 | return NULL_RTX; | |
16875 | ||
61f0ccff | 16876 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); |
d5b7b3ae RE |
16877 | } |
16878 | ||
16879 | /* Do anything needed before RTL is emitted for each function. */ | |
16880 | void | |
e32bac5b | 16881 | arm_init_expanders (void) |
d5b7b3ae RE |
16882 | { |
16883 | /* Arrange to initialize and mark the machine per-function status. */ | |
16884 | init_machine_status = arm_init_machine_status; | |
3ac5ea7c RH |
16885 | |
16886 | /* This is to stop the combine pass optimizing away the alignment | |
16887 | adjustment of va_arg. */ | |
16888 | /* ??? It is claimed that this should not be necessary. */ | |
16889 | if (cfun) | |
16890 | mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); | |
d5b7b3ae RE |
16891 | } |
16892 | ||
0977774b | 16893 | |
2591db65 RE |
16894 | /* Like arm_compute_initial_elimination offset. Simpler because there |
16895 | isn't an ABI specified frame pointer for Thumb. Instead, we set it | |
16896 | to point at the base of the local variables after static stack | |
16897 | space for a function has been allocated. */ | |
0977774b | 16898 | |
5848830f PB |
16899 | HOST_WIDE_INT |
16900 | thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to) | |
16901 | { | |
16902 | arm_stack_offsets *offsets; | |
0977774b | 16903 | |
5848830f | 16904 | offsets = arm_get_frame_offsets (); |
0977774b | 16905 | |
5848830f | 16906 | switch (from) |
0977774b | 16907 | { |
5848830f PB |
16908 | case ARG_POINTER_REGNUM: |
16909 | switch (to) | |
16910 | { | |
16911 | case STACK_POINTER_REGNUM: | |
16912 | return offsets->outgoing_args - offsets->saved_args; | |
0977774b | 16913 | |
5848830f PB |
16914 | case FRAME_POINTER_REGNUM: |
16915 | return offsets->soft_frame - offsets->saved_args; | |
0977774b | 16916 | |
5848830f PB |
16917 | case ARM_HARD_FRAME_POINTER_REGNUM: |
16918 | return offsets->saved_regs - offsets->saved_args; | |
0977774b | 16919 | |
2591db65 RE |
16920 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
16921 | return offsets->locals_base - offsets->saved_args; | |
16922 | ||
5848830f | 16923 | default: |
e6d29d15 | 16924 | gcc_unreachable (); |
5848830f PB |
16925 | } |
16926 | break; | |
0977774b | 16927 | |
5848830f PB |
16928 | case FRAME_POINTER_REGNUM: |
16929 | switch (to) | |
16930 | { | |
16931 | case STACK_POINTER_REGNUM: | |
16932 | return offsets->outgoing_args - offsets->soft_frame; | |
0977774b | 16933 | |
5848830f PB |
16934 | case ARM_HARD_FRAME_POINTER_REGNUM: |
16935 | return offsets->saved_regs - offsets->soft_frame; | |
0977774b | 16936 | |
2591db65 RE |
16937 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
16938 | return offsets->locals_base - offsets->soft_frame; | |
16939 | ||
5848830f | 16940 | default: |
e6d29d15 | 16941 | gcc_unreachable (); |
5848830f PB |
16942 | } |
16943 | break; | |
0977774b | 16944 | |
5848830f | 16945 | default: |
e6d29d15 | 16946 | gcc_unreachable (); |
5848830f | 16947 | } |
0977774b JT |
16948 | } |
16949 | ||
d5b7b3ae RE |
16950 | /* Generate the rest of a function's prologue. */ |
16951 | void | |
5b3e6663 | 16952 | thumb1_expand_prologue (void) |
d5b7b3ae | 16953 | { |
980e61bb DJ |
16954 | rtx insn, dwarf; |
16955 | ||
5848830f PB |
16956 | HOST_WIDE_INT amount; |
16957 | arm_stack_offsets *offsets; | |
6d3d9133 | 16958 | unsigned long func_type; |
3c7ad43e | 16959 | int regno; |
57934c39 | 16960 | unsigned long live_regs_mask; |
6d3d9133 NC |
16961 | |
16962 | func_type = arm_current_func_type (); | |
f676971a | 16963 | |
d5b7b3ae | 16964 | /* Naked functions don't have prologues. */ |
6d3d9133 | 16965 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
16966 | return; |
16967 | ||
6d3d9133 NC |
16968 | if (IS_INTERRUPT (func_type)) |
16969 | { | |
c725bd79 | 16970 | error ("interrupt Service Routines cannot be coded in Thumb mode"); |
6d3d9133 NC |
16971 | return; |
16972 | } | |
16973 | ||
954954d1 PB |
16974 | offsets = arm_get_frame_offsets (); |
16975 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a NC |
16976 | /* Load the pic register before setting the frame pointer, |
16977 | so we can use r7 as a temporary work register. */ | |
020a4035 | 16978 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
e55ef7f4 | 16979 | arm_load_pic_register (live_regs_mask); |
876f13b0 | 16980 | |
2591db65 | 16981 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) |
a2503645 RS |
16982 | emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM), |
16983 | stack_pointer_rtx); | |
d5b7b3ae | 16984 | |
5848830f | 16985 | amount = offsets->outgoing_args - offsets->saved_regs; |
d5b7b3ae RE |
16986 | if (amount) |
16987 | { | |
d5b7b3ae | 16988 | if (amount < 512) |
980e61bb DJ |
16989 | { |
16990 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
16991 | GEN_INT (- amount))); | |
16992 | RTX_FRAME_RELATED_P (insn) = 1; | |
16993 | } | |
d5b7b3ae RE |
16994 | else |
16995 | { | |
d5b7b3ae RE |
16996 | rtx reg; |
16997 | ||
16998 | /* The stack decrement is too big for an immediate value in a single | |
16999 | insn. In theory we could issue multiple subtracts, but after | |
17000 | three of them it becomes more space efficient to place the full | |
17001 | value in the constant pool and load into a register. (Also the | |
17002 | ARM debugger really likes to see only one stack decrement per | |
17003 | function). So instead we look for a scratch register into which | |
17004 | we can load the decrement, and then we subtract this from the | |
17005 | stack pointer. Unfortunately on the thumb the only available | |
17006 | scratch registers are the argument registers, and we cannot use | |
17007 | these as they may hold arguments to the function. Instead we | |
17008 | attempt to locate a call preserved register which is used by this | |
17009 | function. If we can find one, then we know that it will have | |
17010 | been pushed at the start of the prologue and so we can corrupt | |
17011 | it now. */ | |
17012 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
57934c39 | 17013 | if (live_regs_mask & (1 << regno) |
5895f793 RE |
17014 | && !(frame_pointer_needed |
17015 | && (regno == THUMB_HARD_FRAME_POINTER_REGNUM))) | |
d5b7b3ae RE |
17016 | break; |
17017 | ||
aeaf4d25 | 17018 | if (regno > LAST_LO_REGNUM) /* Very unlikely. */ |
d5b7b3ae | 17019 | { |
f1c25d3b | 17020 | rtx spare = gen_rtx_REG (SImode, IP_REGNUM); |
d5b7b3ae | 17021 | |
6bc82793 | 17022 | /* Choose an arbitrary, non-argument low register. */ |
f1c25d3b | 17023 | reg = gen_rtx_REG (SImode, LAST_LO_REGNUM); |
d5b7b3ae RE |
17024 | |
17025 | /* Save it by copying it into a high, scratch register. */ | |
c14a3a45 NC |
17026 | emit_insn (gen_movsi (spare, reg)); |
17027 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
6bacc7b0 | 17028 | emit_insn (gen_prologue_use (spare)); |
d5b7b3ae RE |
17029 | |
17030 | /* Decrement the stack. */ | |
1d6e90ac | 17031 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb DJ |
17032 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, |
17033 | stack_pointer_rtx, reg)); | |
17034 | RTX_FRAME_RELATED_P (insn) = 1; | |
d66437c5 | 17035 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, |
980e61bb | 17036 | plus_constant (stack_pointer_rtx, |
78773322 | 17037 | -amount)); |
980e61bb DJ |
17038 | RTX_FRAME_RELATED_P (dwarf) = 1; |
17039 | REG_NOTES (insn) | |
17040 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
17041 | REG_NOTES (insn)); | |
d5b7b3ae RE |
17042 | |
17043 | /* Restore the low register's original value. */ | |
17044 | emit_insn (gen_movsi (reg, spare)); | |
f676971a | 17045 | |
d5b7b3ae RE |
17046 | /* Emit a USE of the restored scratch register, so that flow |
17047 | analysis will not consider the restore redundant. The | |
17048 | register won't be used again in this function and isn't | |
17049 | restored by the epilogue. */ | |
6bacc7b0 | 17050 | emit_insn (gen_prologue_use (reg)); |
d5b7b3ae RE |
17051 | } |
17052 | else | |
17053 | { | |
f1c25d3b | 17054 | reg = gen_rtx_REG (SImode, regno); |
d5b7b3ae | 17055 | |
1d6e90ac | 17056 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb DJ |
17057 | |
17058 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, | |
17059 | stack_pointer_rtx, reg)); | |
17060 | RTX_FRAME_RELATED_P (insn) = 1; | |
d66437c5 | 17061 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, |
980e61bb | 17062 | plus_constant (stack_pointer_rtx, |
78773322 | 17063 | -amount)); |
980e61bb DJ |
17064 | RTX_FRAME_RELATED_P (dwarf) = 1; |
17065 | REG_NOTES (insn) | |
17066 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
17067 | REG_NOTES (insn)); | |
d5b7b3ae RE |
17068 | } |
17069 | } | |
2591db65 RE |
17070 | } |
17071 | ||
17072 | if (frame_pointer_needed) | |
5b3e6663 | 17073 | thumb_set_frame_pointer (offsets); |
f676971a | 17074 | |
74d9c39f DJ |
17075 | /* If we are profiling, make sure no instructions are scheduled before |
17076 | the call to mcount. Similarly if the user has requested no | |
17077 | scheduling in the prolog. Similarly if we want non-call exceptions | |
17078 | using the EABI unwinder, to prevent faulting instructions from being | |
17079 | swapped with a stack adjustment. */ | |
e3b5732b | 17080 | if (crtl->profile || !TARGET_SCHED_PROLOG |
74d9c39f | 17081 | || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) |
d5b7b3ae | 17082 | emit_insn (gen_blockage ()); |
3c7ad43e PB |
17083 | |
17084 | cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); | |
57934c39 PB |
17085 | if (live_regs_mask & 0xff) |
17086 | cfun->machine->lr_save_eliminated = 0; | |
d5b7b3ae RE |
17087 | } |
17088 | ||
57934c39 | 17089 | |
d5b7b3ae | 17090 | void |
5b3e6663 | 17091 | thumb1_expand_epilogue (void) |
d5b7b3ae | 17092 | { |
5848830f PB |
17093 | HOST_WIDE_INT amount; |
17094 | arm_stack_offsets *offsets; | |
defc0463 RE |
17095 | int regno; |
17096 | ||
6d3d9133 NC |
17097 | /* Naked functions don't have prologues. */ |
17098 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
17099 | return; |
17100 | ||
5848830f PB |
17101 | offsets = arm_get_frame_offsets (); |
17102 | amount = offsets->outgoing_args - offsets->saved_regs; | |
17103 | ||
d5b7b3ae | 17104 | if (frame_pointer_needed) |
2591db65 RE |
17105 | { |
17106 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
17107 | amount = offsets->locals_base - offsets->saved_regs; | |
17108 | } | |
e0b92319 | 17109 | |
a3a531ec | 17110 | gcc_assert (amount >= 0); |
2591db65 | 17111 | if (amount) |
d5b7b3ae | 17112 | { |
d5b7b3ae RE |
17113 | if (amount < 512) |
17114 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
17115 | GEN_INT (amount))); | |
17116 | else | |
17117 | { | |
17118 | /* r3 is always free in the epilogue. */ | |
f1c25d3b | 17119 | rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM); |
d5b7b3ae RE |
17120 | |
17121 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
17122 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
17123 | } | |
17124 | } | |
f676971a | 17125 | |
d5b7b3ae RE |
17126 | /* Emit a USE (stack_pointer_rtx), so that |
17127 | the stack adjustment will not be deleted. */ | |
6bacc7b0 | 17128 | emit_insn (gen_prologue_use (stack_pointer_rtx)); |
d5b7b3ae | 17129 | |
e3b5732b | 17130 | if (crtl->profile || !TARGET_SCHED_PROLOG) |
d5b7b3ae | 17131 | emit_insn (gen_blockage ()); |
defc0463 RE |
17132 | |
17133 | /* Emit a clobber for each insn that will be restored in the epilogue, | |
17134 | so that flow2 will get register lifetimes correct. */ | |
17135 | for (regno = 0; regno < 13; regno++) | |
6fb5fa3c | 17136 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
c41c1387 | 17137 | emit_clobber (gen_rtx_REG (SImode, regno)); |
defc0463 | 17138 | |
6fb5fa3c | 17139 | if (! df_regs_ever_live_p (LR_REGNUM)) |
c41c1387 | 17140 | emit_use (gen_rtx_REG (SImode, LR_REGNUM)); |
d5b7b3ae RE |
17141 | } |
17142 | ||
08c148a8 | 17143 | static void |
5b3e6663 | 17144 | thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
d5b7b3ae | 17145 | { |
954954d1 | 17146 | arm_stack_offsets *offsets; |
b279b20a NC |
17147 | unsigned long live_regs_mask = 0; |
17148 | unsigned long l_mask; | |
17149 | unsigned high_regs_pushed = 0; | |
980e61bb | 17150 | int cfa_offset = 0; |
d5b7b3ae RE |
17151 | int regno; |
17152 | ||
6d3d9133 | 17153 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
17154 | return; |
17155 | ||
17156 | if (is_called_in_ARM_mode (current_function_decl)) | |
17157 | { | |
17158 | const char * name; | |
17159 | ||
e6d29d15 NS |
17160 | gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); |
17161 | gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) | |
17162 | == SYMBOL_REF); | |
d5b7b3ae | 17163 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
f676971a | 17164 | |
d5b7b3ae RE |
17165 | /* Generate code sequence to switch us into Thumb mode. */ |
17166 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 17167 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
17168 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
17169 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
17170 | ||
17171 | /* Generate a label, so that the debugger will notice the | |
17172 | change in instruction sets. This label is also used by | |
17173 | the assembler to bypass the ARM code when this function | |
17174 | is called from a Thumb encoded function elsewhere in the | |
17175 | same file. Hence the definition of STUB_NAME here must | |
d6b4baa4 | 17176 | agree with the definition in gas/config/tc-arm.c. */ |
f676971a | 17177 | |
d5b7b3ae | 17178 | #define STUB_NAME ".real_start_of" |
f676971a | 17179 | |
761c70aa | 17180 | fprintf (f, "\t.code\t16\n"); |
d5b7b3ae RE |
17181 | #ifdef ARM_PE |
17182 | if (arm_dllexport_name_p (name)) | |
e5951263 | 17183 | name = arm_strip_name_encoding (name); |
f676971a | 17184 | #endif |
d5b7b3ae | 17185 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); |
761c70aa | 17186 | fprintf (f, "\t.thumb_func\n"); |
d5b7b3ae RE |
17187 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); |
17188 | } | |
f676971a | 17189 | |
38173d38 | 17190 | if (crtl->args.pretend_args_size) |
d5b7b3ae | 17191 | { |
617a1b71 PB |
17192 | /* Output unwind directive for the stack adjustment. */ |
17193 | if (ARM_EABI_UNWIND_TABLES) | |
17194 | fprintf (f, "\t.pad #%d\n", | |
38173d38 | 17195 | crtl->args.pretend_args_size); |
617a1b71 | 17196 | |
3cb66fd7 | 17197 | if (cfun->machine->uses_anonymous_args) |
d5b7b3ae RE |
17198 | { |
17199 | int num_pushes; | |
f676971a | 17200 | |
761c70aa | 17201 | fprintf (f, "\tpush\t{"); |
d5b7b3ae | 17202 | |
38173d38 | 17203 | num_pushes = ARM_NUM_INTS (crtl->args.pretend_args_size); |
f676971a | 17204 | |
d5b7b3ae RE |
17205 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; |
17206 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 17207 | regno++) |
d5b7b3ae RE |
17208 | asm_fprintf (f, "%r%s", regno, |
17209 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
17210 | ||
761c70aa | 17211 | fprintf (f, "}\n"); |
d5b7b3ae RE |
17212 | } |
17213 | else | |
f676971a | 17214 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", |
d5b7b3ae | 17215 | SP_REGNUM, SP_REGNUM, |
38173d38 | 17216 | crtl->args.pretend_args_size); |
980e61bb DJ |
17217 | |
17218 | /* We don't need to record the stores for unwinding (would it | |
17219 | help the debugger any if we did?), but record the change in | |
17220 | the stack pointer. */ | |
17221 | if (dwarf2out_do_frame ()) | |
17222 | { | |
17223 | char *l = dwarf2out_cfi_label (); | |
b279b20a | 17224 | |
38173d38 | 17225 | cfa_offset = cfa_offset + crtl->args.pretend_args_size; |
980e61bb DJ |
17226 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); |
17227 | } | |
d5b7b3ae RE |
17228 | } |
17229 | ||
b279b20a | 17230 | /* Get the registers we are going to push. */ |
954954d1 PB |
17231 | offsets = arm_get_frame_offsets (); |
17232 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a | 17233 | /* Extract a mask of the ones we can give to the Thumb's push instruction. */ |
57934c39 | 17234 | l_mask = live_regs_mask & 0x40ff; |
b279b20a NC |
17235 | /* Then count how many other high registers will need to be pushed. */ |
17236 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | |
d5b7b3ae RE |
17237 | |
17238 | if (TARGET_BACKTRACE) | |
17239 | { | |
b279b20a NC |
17240 | unsigned offset; |
17241 | unsigned work_register; | |
f676971a | 17242 | |
d5b7b3ae RE |
17243 | /* We have been asked to create a stack backtrace structure. |
17244 | The code looks like this: | |
f676971a | 17245 | |
d5b7b3ae RE |
17246 | 0 .align 2 |
17247 | 0 func: | |
17248 | 0 sub SP, #16 Reserve space for 4 registers. | |
57934c39 | 17249 | 2 push {R7} Push low registers. |
d5b7b3ae RE |
17250 | 4 add R7, SP, #20 Get the stack pointer before the push. |
17251 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
17252 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
17253 | 10 str R7, [SP, #16] Store it. | |
17254 | 12 mov R7, FP Get hold of the current frame pointer. | |
17255 | 14 str R7, [SP, #4] Store it. | |
17256 | 16 mov R7, LR Get hold of the current return address. | |
17257 | 18 str R7, [SP, #12] Store it. | |
17258 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
17259 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
17260 | ||
57934c39 | 17261 | work_register = thumb_find_work_register (live_regs_mask); |
f676971a | 17262 | |
617a1b71 PB |
17263 | if (ARM_EABI_UNWIND_TABLES) |
17264 | asm_fprintf (f, "\t.pad #16\n"); | |
17265 | ||
d5b7b3ae RE |
17266 | asm_fprintf |
17267 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
17268 | SP_REGNUM, SP_REGNUM); | |
980e61bb DJ |
17269 | |
17270 | if (dwarf2out_do_frame ()) | |
17271 | { | |
17272 | char *l = dwarf2out_cfi_label (); | |
b279b20a | 17273 | |
980e61bb DJ |
17274 | cfa_offset = cfa_offset + 16; |
17275 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); | |
17276 | } | |
17277 | ||
57934c39 PB |
17278 | if (l_mask) |
17279 | { | |
17280 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); | |
1a59548b | 17281 | offset = bit_count (l_mask) * UNITS_PER_WORD; |
57934c39 PB |
17282 | } |
17283 | else | |
17284 | offset = 0; | |
f676971a | 17285 | |
d5b7b3ae | 17286 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, |
38173d38 | 17287 | offset + 16 + crtl->args.pretend_args_size); |
f676971a | 17288 | |
d5b7b3ae RE |
17289 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, |
17290 | offset + 4); | |
17291 | ||
17292 | /* Make sure that the instruction fetching the PC is in the right place | |
17293 | to calculate "start of backtrace creation code + 12". */ | |
57934c39 | 17294 | if (l_mask) |
d5b7b3ae RE |
17295 | { |
17296 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
17297 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17298 | offset + 12); | |
17299 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
17300 | ARM_HARD_FRAME_POINTER_REGNUM); | |
17301 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17302 | offset); | |
17303 | } | |
17304 | else | |
17305 | { | |
17306 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
17307 | ARM_HARD_FRAME_POINTER_REGNUM); | |
17308 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17309 | offset); | |
17310 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
17311 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17312 | offset + 12); | |
17313 | } | |
f676971a | 17314 | |
d5b7b3ae RE |
17315 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); |
17316 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17317 | offset + 8); | |
17318 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
17319 | offset + 12); | |
17320 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
17321 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
17322 | } | |
0fa2e4df | 17323 | /* Optimization: If we are not pushing any low registers but we are going |
b279b20a NC |
17324 | to push some high registers then delay our first push. This will just |
17325 | be a push of LR and we can combine it with the push of the first high | |
17326 | register. */ | |
17327 | else if ((l_mask & 0xff) != 0 | |
17328 | || (high_regs_pushed == 0 && l_mask)) | |
57934c39 | 17329 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); |
d5b7b3ae | 17330 | |
d5b7b3ae RE |
17331 | if (high_regs_pushed) |
17332 | { | |
b279b20a NC |
17333 | unsigned pushable_regs; |
17334 | unsigned next_hi_reg; | |
d5b7b3ae RE |
17335 | |
17336 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
57934c39 | 17337 | if (live_regs_mask & (1 << next_hi_reg)) |
e26053d1 | 17338 | break; |
d5b7b3ae | 17339 | |
57934c39 | 17340 | pushable_regs = l_mask & 0xff; |
d5b7b3ae RE |
17341 | |
17342 | if (pushable_regs == 0) | |
57934c39 | 17343 | pushable_regs = 1 << thumb_find_work_register (live_regs_mask); |
d5b7b3ae RE |
17344 | |
17345 | while (high_regs_pushed > 0) | |
17346 | { | |
b279b20a | 17347 | unsigned long real_regs_mask = 0; |
980e61bb | 17348 | |
b279b20a | 17349 | for (regno = LAST_LO_REGNUM; regno >= 0; regno --) |
d5b7b3ae | 17350 | { |
57934c39 | 17351 | if (pushable_regs & (1 << regno)) |
d5b7b3ae RE |
17352 | { |
17353 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
f676971a | 17354 | |
b279b20a | 17355 | high_regs_pushed --; |
980e61bb | 17356 | real_regs_mask |= (1 << next_hi_reg); |
f676971a | 17357 | |
d5b7b3ae | 17358 | if (high_regs_pushed) |
aeaf4d25 | 17359 | { |
b279b20a NC |
17360 | for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM; |
17361 | next_hi_reg --) | |
57934c39 | 17362 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae | 17363 | break; |
aeaf4d25 | 17364 | } |
d5b7b3ae RE |
17365 | else |
17366 | { | |
57934c39 | 17367 | pushable_regs &= ~((1 << regno) - 1); |
d5b7b3ae RE |
17368 | break; |
17369 | } | |
17370 | } | |
17371 | } | |
980e61bb | 17372 | |
b279b20a NC |
17373 | /* If we had to find a work register and we have not yet |
17374 | saved the LR then add it to the list of regs to push. */ | |
17375 | if (l_mask == (1 << LR_REGNUM)) | |
17376 | { | |
17377 | thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM), | |
17378 | 1, &cfa_offset, | |
17379 | real_regs_mask | (1 << LR_REGNUM)); | |
17380 | l_mask = 0; | |
17381 | } | |
17382 | else | |
17383 | thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask); | |
d5b7b3ae | 17384 | } |
d5b7b3ae RE |
17385 | } |
17386 | } | |
17387 | ||
17388 | /* Handle the case of a double word load into a low register from | |
17389 | a computed memory address. The computed address may involve a | |
17390 | register which is overwritten by the load. */ | |
cd2b33d0 | 17391 | const char * |
e32bac5b | 17392 | thumb_load_double_from_address (rtx *operands) |
d5b7b3ae RE |
17393 | { |
17394 | rtx addr; | |
17395 | rtx base; | |
17396 | rtx offset; | |
17397 | rtx arg1; | |
17398 | rtx arg2; | |
f676971a | 17399 | |
e6d29d15 NS |
17400 | gcc_assert (GET_CODE (operands[0]) == REG); |
17401 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
d5b7b3ae RE |
17402 | |
17403 | /* Get the memory address. */ | |
17404 | addr = XEXP (operands[1], 0); | |
f676971a | 17405 | |
d5b7b3ae RE |
17406 | /* Work out how the memory address is computed. */ |
17407 | switch (GET_CODE (addr)) | |
17408 | { | |
17409 | case REG: | |
31fa16b6 | 17410 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 17411 | |
d5b7b3ae RE |
17412 | if (REGNO (operands[0]) == REGNO (addr)) |
17413 | { | |
17414 | output_asm_insn ("ldr\t%H0, %2", operands); | |
17415 | output_asm_insn ("ldr\t%0, %1", operands); | |
17416 | } | |
17417 | else | |
17418 | { | |
17419 | output_asm_insn ("ldr\t%0, %1", operands); | |
17420 | output_asm_insn ("ldr\t%H0, %2", operands); | |
17421 | } | |
17422 | break; | |
f676971a | 17423 | |
d5b7b3ae RE |
17424 | case CONST: |
17425 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 17426 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 17427 | |
d5b7b3ae RE |
17428 | output_asm_insn ("ldr\t%0, %1", operands); |
17429 | output_asm_insn ("ldr\t%H0, %2", operands); | |
17430 | break; | |
f676971a | 17431 | |
d5b7b3ae RE |
17432 | case PLUS: |
17433 | arg1 = XEXP (addr, 0); | |
17434 | arg2 = XEXP (addr, 1); | |
f676971a | 17435 | |
d5b7b3ae RE |
17436 | if (CONSTANT_P (arg1)) |
17437 | base = arg2, offset = arg1; | |
17438 | else | |
17439 | base = arg1, offset = arg2; | |
f676971a | 17440 | |
e6d29d15 | 17441 | gcc_assert (GET_CODE (base) == REG); |
d5b7b3ae RE |
17442 | |
17443 | /* Catch the case of <address> = <reg> + <reg> */ | |
17444 | if (GET_CODE (offset) == REG) | |
17445 | { | |
17446 | int reg_offset = REGNO (offset); | |
17447 | int reg_base = REGNO (base); | |
17448 | int reg_dest = REGNO (operands[0]); | |
f676971a | 17449 | |
d5b7b3ae RE |
17450 | /* Add the base and offset registers together into the |
17451 | higher destination register. */ | |
17452 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
17453 | reg_dest + 1, reg_base, reg_offset); | |
f676971a | 17454 | |
d5b7b3ae RE |
17455 | /* Load the lower destination register from the address in |
17456 | the higher destination register. */ | |
17457 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
17458 | reg_dest, reg_dest + 1); | |
f676971a | 17459 | |
d5b7b3ae RE |
17460 | /* Load the higher destination register from its own address |
17461 | plus 4. */ | |
17462 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
17463 | reg_dest + 1, reg_dest + 1); | |
17464 | } | |
17465 | else | |
17466 | { | |
17467 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 17468 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 17469 | |
d5b7b3ae RE |
17470 | /* If the computed address is held in the low order register |
17471 | then load the high order register first, otherwise always | |
17472 | load the low order register first. */ | |
17473 | if (REGNO (operands[0]) == REGNO (base)) | |
17474 | { | |
17475 | output_asm_insn ("ldr\t%H0, %2", operands); | |
17476 | output_asm_insn ("ldr\t%0, %1", operands); | |
17477 | } | |
17478 | else | |
17479 | { | |
17480 | output_asm_insn ("ldr\t%0, %1", operands); | |
17481 | output_asm_insn ("ldr\t%H0, %2", operands); | |
17482 | } | |
17483 | } | |
17484 | break; | |
17485 | ||
17486 | case LABEL_REF: | |
17487 | /* With no registers to worry about we can just load the value | |
17488 | directly. */ | |
31fa16b6 | 17489 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 17490 | |
d5b7b3ae RE |
17491 | output_asm_insn ("ldr\t%H0, %2", operands); |
17492 | output_asm_insn ("ldr\t%0, %1", operands); | |
17493 | break; | |
f676971a | 17494 | |
d5b7b3ae | 17495 | default: |
e6d29d15 | 17496 | gcc_unreachable (); |
d5b7b3ae | 17497 | } |
f676971a | 17498 | |
d5b7b3ae RE |
17499 | return ""; |
17500 | } | |
17501 | ||
cd2b33d0 | 17502 | const char * |
e32bac5b | 17503 | thumb_output_move_mem_multiple (int n, rtx *operands) |
d5b7b3ae RE |
17504 | { |
17505 | rtx tmp; | |
17506 | ||
17507 | switch (n) | |
17508 | { | |
17509 | case 2: | |
ca356f3a | 17510 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 17511 | { |
ca356f3a RE |
17512 | tmp = operands[4]; |
17513 | operands[4] = operands[5]; | |
17514 | operands[5] = tmp; | |
d5b7b3ae | 17515 | } |
ca356f3a RE |
17516 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
17517 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
17518 | break; |
17519 | ||
17520 | case 3: | |
ca356f3a | 17521 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 17522 | { |
ca356f3a RE |
17523 | tmp = operands[4]; |
17524 | operands[4] = operands[5]; | |
17525 | operands[5] = tmp; | |
d5b7b3ae | 17526 | } |
ca356f3a | 17527 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 17528 | { |
ca356f3a RE |
17529 | tmp = operands[5]; |
17530 | operands[5] = operands[6]; | |
17531 | operands[6] = tmp; | |
d5b7b3ae | 17532 | } |
ca356f3a | 17533 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 17534 | { |
ca356f3a RE |
17535 | tmp = operands[4]; |
17536 | operands[4] = operands[5]; | |
17537 | operands[5] = tmp; | |
d5b7b3ae | 17538 | } |
f676971a | 17539 | |
ca356f3a RE |
17540 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
17541 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
17542 | break; |
17543 | ||
17544 | default: | |
e6d29d15 | 17545 | gcc_unreachable (); |
d5b7b3ae RE |
17546 | } |
17547 | ||
17548 | return ""; | |
17549 | } | |
17550 | ||
b12a00f1 RE |
17551 | /* Output a call-via instruction for thumb state. */ |
17552 | const char * | |
17553 | thumb_call_via_reg (rtx reg) | |
17554 | { | |
17555 | int regno = REGNO (reg); | |
17556 | rtx *labelp; | |
17557 | ||
57ecec57 | 17558 | gcc_assert (regno < LR_REGNUM); |
b12a00f1 RE |
17559 | |
17560 | /* If we are in the normal text section we can use a single instance | |
17561 | per compilation unit. If we are doing function sections, then we need | |
17562 | an entry per section, since we can't rely on reachability. */ | |
d6b5193b | 17563 | if (in_section == text_section) |
b12a00f1 RE |
17564 | { |
17565 | thumb_call_reg_needed = 1; | |
17566 | ||
17567 | if (thumb_call_via_label[regno] == NULL) | |
17568 | thumb_call_via_label[regno] = gen_label_rtx (); | |
17569 | labelp = thumb_call_via_label + regno; | |
17570 | } | |
17571 | else | |
17572 | { | |
17573 | if (cfun->machine->call_via[regno] == NULL) | |
17574 | cfun->machine->call_via[regno] = gen_label_rtx (); | |
17575 | labelp = cfun->machine->call_via + regno; | |
17576 | } | |
17577 | ||
17578 | output_asm_insn ("bl\t%a0", labelp); | |
17579 | return ""; | |
17580 | } | |
17581 | ||
1d6e90ac | 17582 | /* Routines for generating rtl. */ |
d5b7b3ae | 17583 | void |
70128ad9 | 17584 | thumb_expand_movmemqi (rtx *operands) |
d5b7b3ae RE |
17585 | { |
17586 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
17587 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
17588 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
17589 | HOST_WIDE_INT offset = 0; | |
17590 | ||
17591 | while (len >= 12) | |
17592 | { | |
ca356f3a | 17593 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
17594 | len -= 12; |
17595 | } | |
f676971a | 17596 | |
d5b7b3ae RE |
17597 | if (len >= 8) |
17598 | { | |
ca356f3a | 17599 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
17600 | len -= 8; |
17601 | } | |
f676971a | 17602 | |
d5b7b3ae RE |
17603 | if (len >= 4) |
17604 | { | |
17605 | rtx reg = gen_reg_rtx (SImode); | |
f1c25d3b KH |
17606 | emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in))); |
17607 | emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg)); | |
d5b7b3ae RE |
17608 | len -= 4; |
17609 | offset += 4; | |
17610 | } | |
f676971a | 17611 | |
d5b7b3ae RE |
17612 | if (len >= 2) |
17613 | { | |
17614 | rtx reg = gen_reg_rtx (HImode); | |
f676971a | 17615 | emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode, |
f1c25d3b KH |
17616 | plus_constant (in, offset)))); |
17617 | emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
17618 | reg)); |
17619 | len -= 2; | |
17620 | offset += 2; | |
17621 | } | |
f676971a | 17622 | |
d5b7b3ae RE |
17623 | if (len) |
17624 | { | |
17625 | rtx reg = gen_reg_rtx (QImode); | |
f1c25d3b KH |
17626 | emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode, |
17627 | plus_constant (in, offset)))); | |
17628 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
17629 | reg)); |
17630 | } | |
17631 | } | |
17632 | ||
d5b7b3ae | 17633 | void |
e32bac5b | 17634 | thumb_reload_out_hi (rtx *operands) |
d5b7b3ae RE |
17635 | { |
17636 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
17637 | } | |
17638 | ||
f676971a | 17639 | /* Handle reading a half-word from memory during reload. */ |
d5b7b3ae | 17640 | void |
e32bac5b | 17641 | thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) |
d5b7b3ae | 17642 | { |
e6d29d15 | 17643 | gcc_unreachable (); |
d5b7b3ae RE |
17644 | } |
17645 | ||
c27ba912 DM |
17646 | /* Return the length of a function name prefix |
17647 | that starts with the character 'c'. */ | |
17648 | static int | |
e32bac5b | 17649 | arm_get_strip_length (int c) |
c27ba912 DM |
17650 | { |
17651 | switch (c) | |
17652 | { | |
17653 | ARM_NAME_ENCODING_LENGTHS | |
f676971a | 17654 | default: return 0; |
c27ba912 DM |
17655 | } |
17656 | } | |
17657 | ||
17658 | /* Return a pointer to a function's name with any | |
17659 | and all prefix encodings stripped from it. */ | |
17660 | const char * | |
e32bac5b | 17661 | arm_strip_name_encoding (const char *name) |
c27ba912 DM |
17662 | { |
17663 | int skip; | |
f676971a | 17664 | |
c27ba912 DM |
17665 | while ((skip = arm_get_strip_length (* name))) |
17666 | name += skip; | |
17667 | ||
17668 | return name; | |
17669 | } | |
17670 | ||
e1944073 KW |
17671 | /* If there is a '*' anywhere in the name's prefix, then |
17672 | emit the stripped name verbatim, otherwise prepend an | |
17673 | underscore if leading underscores are being used. */ | |
e1944073 | 17674 | void |
e32bac5b | 17675 | arm_asm_output_labelref (FILE *stream, const char *name) |
e1944073 KW |
17676 | { |
17677 | int skip; | |
17678 | int verbatim = 0; | |
17679 | ||
17680 | while ((skip = arm_get_strip_length (* name))) | |
17681 | { | |
17682 | verbatim |= (*name == '*'); | |
17683 | name += skip; | |
17684 | } | |
17685 | ||
17686 | if (verbatim) | |
17687 | fputs (name, stream); | |
17688 | else | |
17689 | asm_fprintf (stream, "%U%s", name); | |
17690 | } | |
17691 | ||
6c6aa1af PB |
17692 | static void |
17693 | arm_file_start (void) | |
17694 | { | |
17695 | int val; | |
17696 | ||
5b3e6663 PB |
17697 | if (TARGET_UNIFIED_ASM) |
17698 | asm_fprintf (asm_out_file, "\t.syntax unified\n"); | |
17699 | ||
6c6aa1af PB |
17700 | if (TARGET_BPABI) |
17701 | { | |
17702 | const char *fpu_name; | |
17703 | if (arm_select[0].string) | |
17704 | asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string); | |
17705 | else if (arm_select[1].string) | |
17706 | asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string); | |
17707 | else | |
17708 | asm_fprintf (asm_out_file, "\t.cpu %s\n", | |
17709 | all_cores[arm_default_cpu].name); | |
17710 | ||
17711 | if (TARGET_SOFT_FLOAT) | |
17712 | { | |
17713 | if (TARGET_VFP) | |
17714 | fpu_name = "softvfp"; | |
17715 | else | |
17716 | fpu_name = "softfpa"; | |
17717 | } | |
17718 | else | |
17719 | { | |
f1adb0a9 | 17720 | int set_float_abi_attributes = 0; |
6c6aa1af PB |
17721 | switch (arm_fpu_arch) |
17722 | { | |
17723 | case FPUTYPE_FPA: | |
17724 | fpu_name = "fpa"; | |
17725 | break; | |
17726 | case FPUTYPE_FPA_EMU2: | |
17727 | fpu_name = "fpe2"; | |
17728 | break; | |
17729 | case FPUTYPE_FPA_EMU3: | |
17730 | fpu_name = "fpe3"; | |
17731 | break; | |
17732 | case FPUTYPE_MAVERICK: | |
17733 | fpu_name = "maverick"; | |
17734 | break; | |
17735 | case FPUTYPE_VFP: | |
6c6aa1af | 17736 | fpu_name = "vfp"; |
f1adb0a9 JB |
17737 | set_float_abi_attributes = 1; |
17738 | break; | |
17739 | case FPUTYPE_VFP3: | |
17740 | fpu_name = "vfp3"; | |
17741 | set_float_abi_attributes = 1; | |
6c6aa1af | 17742 | break; |
88f77cba JB |
17743 | case FPUTYPE_NEON: |
17744 | fpu_name = "neon"; | |
17745 | set_float_abi_attributes = 1; | |
17746 | break; | |
6c6aa1af PB |
17747 | default: |
17748 | abort(); | |
17749 | } | |
f1adb0a9 JB |
17750 | if (set_float_abi_attributes) |
17751 | { | |
17752 | if (TARGET_HARD_FLOAT) | |
17753 | asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n"); | |
17754 | if (TARGET_HARD_FLOAT_ABI) | |
17755 | asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n"); | |
17756 | } | |
6c6aa1af PB |
17757 | } |
17758 | asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name); | |
17759 | ||
17760 | /* Some of these attributes only apply when the corresponding features | |
17761 | are used. However we don't have any easy way of figuring this out. | |
17762 | Conservatively record the setting that would have been used. */ | |
17763 | ||
6c6aa1af PB |
17764 | /* Tag_ABI_FP_rounding. */ |
17765 | if (flag_rounding_math) | |
17766 | asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n"); | |
17767 | if (!flag_unsafe_math_optimizations) | |
17768 | { | |
17769 | /* Tag_ABI_FP_denomal. */ | |
17770 | asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n"); | |
17771 | /* Tag_ABI_FP_exceptions. */ | |
17772 | asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n"); | |
17773 | } | |
17774 | /* Tag_ABI_FP_user_exceptions. */ | |
17775 | if (flag_signaling_nans) | |
17776 | asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n"); | |
17777 | /* Tag_ABI_FP_number_model. */ | |
17778 | asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n", | |
17779 | flag_finite_math_only ? 1 : 3); | |
17780 | ||
17781 | /* Tag_ABI_align8_needed. */ | |
17782 | asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n"); | |
17783 | /* Tag_ABI_align8_preserved. */ | |
17784 | asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n"); | |
17785 | /* Tag_ABI_enum_size. */ | |
17786 | asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n", | |
17787 | flag_short_enums ? 1 : 2); | |
17788 | ||
17789 | /* Tag_ABI_optimization_goals. */ | |
17790 | if (optimize_size) | |
17791 | val = 4; | |
17792 | else if (optimize >= 2) | |
17793 | val = 2; | |
17794 | else if (optimize) | |
17795 | val = 1; | |
17796 | else | |
17797 | val = 6; | |
17798 | asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val); | |
b76c3c4b PB |
17799 | |
17800 | if (arm_lang_output_object_attributes_hook) | |
17801 | arm_lang_output_object_attributes_hook(); | |
6c6aa1af PB |
17802 | } |
17803 | default_file_start(); | |
17804 | } | |
17805 | ||
b12a00f1 RE |
17806 | static void |
17807 | arm_file_end (void) | |
17808 | { | |
17809 | int regno; | |
17810 | ||
978e411f CD |
17811 | if (NEED_INDICATE_EXEC_STACK) |
17812 | /* Add .note.GNU-stack. */ | |
17813 | file_end_indicate_exec_stack (); | |
17814 | ||
b12a00f1 RE |
17815 | if (! thumb_call_reg_needed) |
17816 | return; | |
17817 | ||
d6b5193b | 17818 | switch_to_section (text_section); |
b12a00f1 RE |
17819 | asm_fprintf (asm_out_file, "\t.code 16\n"); |
17820 | ASM_OUTPUT_ALIGN (asm_out_file, 1); | |
17821 | ||
57ecec57 | 17822 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
17823 | { |
17824 | rtx label = thumb_call_via_label[regno]; | |
17825 | ||
17826 | if (label != 0) | |
17827 | { | |
17828 | targetm.asm_out.internal_label (asm_out_file, "L", | |
17829 | CODE_LABEL_NUMBER (label)); | |
17830 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
17831 | } | |
17832 | } | |
17833 | } | |
17834 | ||
fb49053f RH |
17835 | #ifndef ARM_PE |
17836 | /* Symbols in the text segment can be accessed without indirecting via the | |
17837 | constant pool; it may take an extra binary operation, but this is still | |
17838 | faster than indirecting via memory. Don't do this when not optimizing, | |
17839 | since we won't be calculating al of the offsets necessary to do this | |
17840 | simplification. */ | |
17841 | ||
17842 | static void | |
e32bac5b | 17843 | arm_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f | 17844 | { |
3521b33c | 17845 | if (optimize > 0 && TREE_CONSTANT (decl)) |
c6a2438a | 17846 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
fb49053f | 17847 | |
d3585b76 | 17848 | default_encode_section_info (decl, rtl, first); |
fb49053f RH |
17849 | } |
17850 | #endif /* !ARM_PE */ | |
483ab821 | 17851 | |
4977bab6 | 17852 | static void |
e32bac5b | 17853 | arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) |
4977bab6 ZW |
17854 | { |
17855 | if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno | |
17856 | && !strcmp (prefix, "L")) | |
17857 | { | |
17858 | arm_ccfsm_state = 0; | |
17859 | arm_target_insn = NULL; | |
17860 | } | |
17861 | default_internal_label (stream, prefix, labelno); | |
17862 | } | |
17863 | ||
c590b625 RH |
17864 | /* Output code to add DELTA to the first argument, and then jump |
17865 | to FUNCTION. Used for C++ multiple inheritance. */ | |
c590b625 | 17866 | static void |
e32bac5b RE |
17867 | arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
17868 | HOST_WIDE_INT delta, | |
17869 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
17870 | tree function) | |
483ab821 | 17871 | { |
9b66ebb1 PB |
17872 | static int thunk_label = 0; |
17873 | char label[256]; | |
54b9e939 | 17874 | char labelpc[256]; |
483ab821 MM |
17875 | int mi_delta = delta; |
17876 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; | |
17877 | int shift = 0; | |
61f71b34 | 17878 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) |
483ab821 MM |
17879 | ? 1 : 0); |
17880 | if (mi_delta < 0) | |
17881 | mi_delta = - mi_delta; | |
bf98ec6c | 17882 | |
5b3e6663 | 17883 | if (TARGET_THUMB1) |
9b66ebb1 PB |
17884 | { |
17885 | int labelno = thunk_label++; | |
17886 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno); | |
bf98ec6c PB |
17887 | /* Thunks are entered in arm mode when avaiable. */ |
17888 | if (TARGET_THUMB1_ONLY) | |
17889 | { | |
17890 | /* push r3 so we can use it as a temporary. */ | |
17891 | /* TODO: Omit this save if r3 is not used. */ | |
17892 | fputs ("\tpush {r3}\n", file); | |
17893 | fputs ("\tldr\tr3, ", file); | |
17894 | } | |
17895 | else | |
17896 | { | |
17897 | fputs ("\tldr\tr12, ", file); | |
17898 | } | |
9b66ebb1 PB |
17899 | assemble_name (file, label); |
17900 | fputc ('\n', file); | |
54b9e939 KH |
17901 | if (flag_pic) |
17902 | { | |
17903 | /* If we are generating PIC, the ldr instruction below loads | |
17904 | "(target - 7) - .LTHUNKPCn" into r12. The pc reads as | |
17905 | the address of the add + 8, so we have: | |
17906 | ||
17907 | r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8) | |
17908 | = target + 1. | |
17909 | ||
17910 | Note that we have "+ 1" because some versions of GNU ld | |
17911 | don't set the low bit of the result for R_ARM_REL32 | |
bf98ec6c PB |
17912 | relocations against thumb function symbols. |
17913 | On ARMv6M this is +4, not +8. */ | |
54b9e939 KH |
17914 | ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno); |
17915 | assemble_name (file, labelpc); | |
17916 | fputs (":\n", file); | |
bf98ec6c PB |
17917 | if (TARGET_THUMB1_ONLY) |
17918 | { | |
17919 | /* This is 2 insns after the start of the thunk, so we know it | |
17920 | is 4-byte aligned. */ | |
17921 | fputs ("\tadd\tr3, pc, r3\n", file); | |
17922 | fputs ("\tmov r12, r3\n", file); | |
17923 | } | |
17924 | else | |
17925 | fputs ("\tadd\tr12, pc, r12\n", file); | |
54b9e939 | 17926 | } |
bf98ec6c PB |
17927 | else if (TARGET_THUMB1_ONLY) |
17928 | fputs ("\tmov r12, r3\n", file); | |
9b66ebb1 | 17929 | } |
bf98ec6c | 17930 | if (TARGET_THUMB1_ONLY) |
483ab821 | 17931 | { |
bf98ec6c PB |
17932 | if (mi_delta > 255) |
17933 | { | |
17934 | fputs ("\tldr\tr3, ", file); | |
17935 | assemble_name (file, label); | |
17936 | fputs ("+4\n", file); | |
17937 | asm_fprintf (file, "\t%s\t%r, %r, r3\n", | |
17938 | mi_op, this_regno, this_regno); | |
17939 | } | |
17940 | else if (mi_delta != 0) | |
17941 | { | |
17942 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
17943 | mi_op, this_regno, this_regno, | |
17944 | mi_delta); | |
17945 | } | |
17946 | } | |
17947 | else | |
17948 | { | |
17949 | /* TODO: Use movw/movt for large constants when available. */ | |
17950 | while (mi_delta != 0) | |
17951 | { | |
17952 | if ((mi_delta & (3 << shift)) == 0) | |
17953 | shift += 2; | |
17954 | else | |
17955 | { | |
17956 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
17957 | mi_op, this_regno, this_regno, | |
17958 | mi_delta & (0xff << shift)); | |
17959 | mi_delta &= ~(0xff << shift); | |
17960 | shift += 8; | |
17961 | } | |
17962 | } | |
483ab821 | 17963 | } |
5b3e6663 | 17964 | if (TARGET_THUMB1) |
9b66ebb1 | 17965 | { |
bf98ec6c PB |
17966 | if (TARGET_THUMB1_ONLY) |
17967 | fputs ("\tpop\t{r3}\n", file); | |
17968 | ||
9b66ebb1 PB |
17969 | fprintf (file, "\tbx\tr12\n"); |
17970 | ASM_OUTPUT_ALIGN (file, 2); | |
17971 | assemble_name (file, label); | |
17972 | fputs (":\n", file); | |
54b9e939 KH |
17973 | if (flag_pic) |
17974 | { | |
17975 | /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */ | |
17976 | rtx tem = XEXP (DECL_RTL (function), 0); | |
17977 | tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); | |
17978 | tem = gen_rtx_MINUS (GET_MODE (tem), | |
17979 | tem, | |
17980 | gen_rtx_SYMBOL_REF (Pmode, | |
17981 | ggc_strdup (labelpc))); | |
17982 | assemble_integer (tem, 4, BITS_PER_WORD, 1); | |
17983 | } | |
17984 | else | |
17985 | /* Output ".word .LTHUNKn". */ | |
17986 | assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); | |
bf98ec6c PB |
17987 | |
17988 | if (TARGET_THUMB1_ONLY && mi_delta > 255) | |
17989 | assemble_integer (GEN_INT(mi_delta), 4, BITS_PER_WORD, 1); | |
9b66ebb1 PB |
17990 | } |
17991 | else | |
17992 | { | |
17993 | fputs ("\tb\t", file); | |
17994 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
17995 | if (NEED_PLT_RELOC) | |
17996 | fputs ("(PLT)", file); | |
17997 | fputc ('\n', file); | |
17998 | } | |
483ab821 | 17999 | } |
5a9335ef NC |
18000 | |
18001 | int | |
6f5f2481 | 18002 | arm_emit_vector_const (FILE *file, rtx x) |
5a9335ef NC |
18003 | { |
18004 | int i; | |
18005 | const char * pattern; | |
18006 | ||
e6d29d15 | 18007 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
18008 | |
18009 | switch (GET_MODE (x)) | |
18010 | { | |
18011 | case V2SImode: pattern = "%08x"; break; | |
18012 | case V4HImode: pattern = "%04x"; break; | |
18013 | case V8QImode: pattern = "%02x"; break; | |
e6d29d15 | 18014 | default: gcc_unreachable (); |
5a9335ef NC |
18015 | } |
18016 | ||
18017 | fprintf (file, "0x"); | |
18018 | for (i = CONST_VECTOR_NUNITS (x); i--;) | |
18019 | { | |
18020 | rtx element; | |
18021 | ||
18022 | element = CONST_VECTOR_ELT (x, i); | |
18023 | fprintf (file, pattern, INTVAL (element)); | |
18024 | } | |
18025 | ||
18026 | return 1; | |
18027 | } | |
18028 | ||
18029 | const char * | |
6f5f2481 | 18030 | arm_output_load_gr (rtx *operands) |
5a9335ef NC |
18031 | { |
18032 | rtx reg; | |
18033 | rtx offset; | |
18034 | rtx wcgr; | |
18035 | rtx sum; | |
f676971a | 18036 | |
5a9335ef NC |
18037 | if (GET_CODE (operands [1]) != MEM |
18038 | || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS | |
18039 | || GET_CODE (reg = XEXP (sum, 0)) != REG | |
18040 | || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT | |
18041 | || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) | |
18042 | return "wldrw%?\t%0, %1"; | |
f676971a EC |
18043 | |
18044 | /* Fix up an out-of-range load of a GR register. */ | |
5a9335ef NC |
18045 | output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); |
18046 | wcgr = operands[0]; | |
18047 | operands[0] = reg; | |
18048 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
18049 | ||
18050 | operands[0] = wcgr; | |
18051 | operands[1] = reg; | |
18052 | output_asm_insn ("tmcr%?\t%0, %1", operands); | |
18053 | output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); | |
18054 | ||
18055 | return ""; | |
18056 | } | |
f9ba5949 | 18057 | |
1cc9f5f5 KH |
18058 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. |
18059 | ||
18060 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
18061 | named arg and all anonymous args onto the stack. | |
18062 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
18063 | that way. */ | |
18064 | ||
18065 | static void | |
18066 | arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum, | |
22ccaaee JJ |
18067 | enum machine_mode mode, |
18068 | tree type, | |
1cc9f5f5 KH |
18069 | int *pretend_size, |
18070 | int second_time ATTRIBUTE_UNUSED) | |
18071 | { | |
22ccaaee JJ |
18072 | int nregs = cum->nregs; |
18073 | if (nregs & 1 | |
18074 | && ARM_DOUBLEWORD_ALIGN | |
18075 | && arm_needs_doubleword_align (mode, type)) | |
18076 | nregs++; | |
18077 | ||
1cc9f5f5 | 18078 | cfun->machine->uses_anonymous_args = 1; |
22ccaaee JJ |
18079 | if (nregs < NUM_ARG_REGS) |
18080 | *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
1cc9f5f5 | 18081 | } |
9b66ebb1 | 18082 | |
59b9a953 | 18083 | /* Return nonzero if the CONSUMER instruction (a store) does not need |
9b66ebb1 PB |
18084 | PRODUCER's value to calculate the address. */ |
18085 | ||
18086 | int | |
18087 | arm_no_early_store_addr_dep (rtx producer, rtx consumer) | |
18088 | { | |
18089 | rtx value = PATTERN (producer); | |
18090 | rtx addr = PATTERN (consumer); | |
18091 | ||
18092 | if (GET_CODE (value) == COND_EXEC) | |
18093 | value = COND_EXEC_CODE (value); | |
18094 | if (GET_CODE (value) == PARALLEL) | |
18095 | value = XVECEXP (value, 0, 0); | |
18096 | value = XEXP (value, 0); | |
18097 | if (GET_CODE (addr) == COND_EXEC) | |
18098 | addr = COND_EXEC_CODE (addr); | |
18099 | if (GET_CODE (addr) == PARALLEL) | |
18100 | addr = XVECEXP (addr, 0, 0); | |
18101 | addr = XEXP (addr, 0); | |
f676971a | 18102 | |
9b66ebb1 PB |
18103 | return !reg_overlap_mentioned_p (value, addr); |
18104 | } | |
18105 | ||
59b9a953 | 18106 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
18107 | have an early register shift value or amount dependency on the |
18108 | result of PRODUCER. */ | |
18109 | ||
18110 | int | |
18111 | arm_no_early_alu_shift_dep (rtx producer, rtx consumer) | |
18112 | { | |
18113 | rtx value = PATTERN (producer); | |
18114 | rtx op = PATTERN (consumer); | |
18115 | rtx early_op; | |
18116 | ||
18117 | if (GET_CODE (value) == COND_EXEC) | |
18118 | value = COND_EXEC_CODE (value); | |
18119 | if (GET_CODE (value) == PARALLEL) | |
18120 | value = XVECEXP (value, 0, 0); | |
18121 | value = XEXP (value, 0); | |
18122 | if (GET_CODE (op) == COND_EXEC) | |
18123 | op = COND_EXEC_CODE (op); | |
18124 | if (GET_CODE (op) == PARALLEL) | |
18125 | op = XVECEXP (op, 0, 0); | |
18126 | op = XEXP (op, 1); | |
f676971a | 18127 | |
9b66ebb1 PB |
18128 | early_op = XEXP (op, 0); |
18129 | /* This is either an actual independent shift, or a shift applied to | |
18130 | the first operand of another operation. We want the whole shift | |
18131 | operation. */ | |
18132 | if (GET_CODE (early_op) == REG) | |
18133 | early_op = op; | |
18134 | ||
18135 | return !reg_overlap_mentioned_p (value, early_op); | |
18136 | } | |
18137 | ||
59b9a953 | 18138 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
18139 | have an early register shift value dependency on the result of |
18140 | PRODUCER. */ | |
18141 | ||
18142 | int | |
18143 | arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) | |
18144 | { | |
18145 | rtx value = PATTERN (producer); | |
18146 | rtx op = PATTERN (consumer); | |
18147 | rtx early_op; | |
18148 | ||
18149 | if (GET_CODE (value) == COND_EXEC) | |
18150 | value = COND_EXEC_CODE (value); | |
18151 | if (GET_CODE (value) == PARALLEL) | |
18152 | value = XVECEXP (value, 0, 0); | |
18153 | value = XEXP (value, 0); | |
18154 | if (GET_CODE (op) == COND_EXEC) | |
18155 | op = COND_EXEC_CODE (op); | |
18156 | if (GET_CODE (op) == PARALLEL) | |
18157 | op = XVECEXP (op, 0, 0); | |
18158 | op = XEXP (op, 1); | |
f676971a | 18159 | |
9b66ebb1 PB |
18160 | early_op = XEXP (op, 0); |
18161 | ||
18162 | /* This is either an actual independent shift, or a shift applied to | |
18163 | the first operand of another operation. We want the value being | |
18164 | shifted, in either case. */ | |
18165 | if (GET_CODE (early_op) != REG) | |
18166 | early_op = XEXP (early_op, 0); | |
f676971a | 18167 | |
9b66ebb1 PB |
18168 | return !reg_overlap_mentioned_p (value, early_op); |
18169 | } | |
18170 | ||
59b9a953 | 18171 | /* Return nonzero if the CONSUMER (a mul or mac op) does not |
9b66ebb1 PB |
18172 | have an early register mult dependency on the result of |
18173 | PRODUCER. */ | |
18174 | ||
18175 | int | |
18176 | arm_no_early_mul_dep (rtx producer, rtx consumer) | |
18177 | { | |
18178 | rtx value = PATTERN (producer); | |
18179 | rtx op = PATTERN (consumer); | |
18180 | ||
18181 | if (GET_CODE (value) == COND_EXEC) | |
18182 | value = COND_EXEC_CODE (value); | |
18183 | if (GET_CODE (value) == PARALLEL) | |
18184 | value = XVECEXP (value, 0, 0); | |
18185 | value = XEXP (value, 0); | |
18186 | if (GET_CODE (op) == COND_EXEC) | |
18187 | op = COND_EXEC_CODE (op); | |
18188 | if (GET_CODE (op) == PARALLEL) | |
18189 | op = XVECEXP (op, 0, 0); | |
18190 | op = XEXP (op, 1); | |
f676971a | 18191 | |
9b66ebb1 PB |
18192 | return (GET_CODE (op) == PLUS |
18193 | && !reg_overlap_mentioned_p (value, XEXP (op, 0))); | |
18194 | } | |
18195 | ||
70301b45 PB |
18196 | /* We can't rely on the caller doing the proper promotion when |
18197 | using APCS or ATPCS. */ | |
18198 | ||
18199 | static bool | |
586de218 | 18200 | arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED) |
70301b45 | 18201 | { |
b6685939 | 18202 | return !TARGET_AAPCS_BASED; |
70301b45 PB |
18203 | } |
18204 | ||
6b045785 PB |
18205 | |
18206 | /* AAPCS based ABIs use short enums by default. */ | |
18207 | ||
18208 | static bool | |
18209 | arm_default_short_enums (void) | |
18210 | { | |
077fc835 | 18211 | return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX; |
6b045785 | 18212 | } |
13c1cd82 PB |
18213 | |
18214 | ||
18215 | /* AAPCS requires that anonymous bitfields affect structure alignment. */ | |
18216 | ||
18217 | static bool | |
18218 | arm_align_anon_bitfield (void) | |
18219 | { | |
18220 | return TARGET_AAPCS_BASED; | |
18221 | } | |
4185ae53 PB |
18222 | |
18223 | ||
18224 | /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */ | |
18225 | ||
18226 | static tree | |
18227 | arm_cxx_guard_type (void) | |
18228 | { | |
18229 | return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; | |
18230 | } | |
18231 | ||
c956e102 MS |
18232 | /* Return non-zero if the consumer (a multiply-accumulate instruction) |
18233 | has an accumulator dependency on the result of the producer (a | |
18234 | multiplication instruction) and no other dependency on that result. */ | |
18235 | int | |
18236 | arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) | |
18237 | { | |
18238 | rtx mul = PATTERN (producer); | |
18239 | rtx mac = PATTERN (consumer); | |
18240 | rtx mul_result; | |
18241 | rtx mac_op0, mac_op1, mac_acc; | |
18242 | ||
18243 | if (GET_CODE (mul) == COND_EXEC) | |
18244 | mul = COND_EXEC_CODE (mul); | |
18245 | if (GET_CODE (mac) == COND_EXEC) | |
18246 | mac = COND_EXEC_CODE (mac); | |
18247 | ||
18248 | /* Check that mul is of the form (set (...) (mult ...)) | |
18249 | and mla is of the form (set (...) (plus (mult ...) (...))). */ | |
18250 | if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT) | |
18251 | || (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS | |
18252 | || GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT)) | |
18253 | return 0; | |
18254 | ||
18255 | mul_result = XEXP (mul, 0); | |
18256 | mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0); | |
18257 | mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1); | |
18258 | mac_acc = XEXP (XEXP (mac, 1), 1); | |
18259 | ||
18260 | return (reg_overlap_mentioned_p (mul_result, mac_acc) | |
18261 | && !reg_overlap_mentioned_p (mul_result, mac_op0) | |
18262 | && !reg_overlap_mentioned_p (mul_result, mac_op1)); | |
18263 | } | |
18264 | ||
4185ae53 | 18265 | |
0fa2e4df | 18266 | /* The EABI says test the least significant bit of a guard variable. */ |
4185ae53 PB |
18267 | |
18268 | static bool | |
18269 | arm_cxx_guard_mask_bit (void) | |
18270 | { | |
18271 | return TARGET_AAPCS_BASED; | |
18272 | } | |
46e995e0 PB |
18273 | |
18274 | ||
18275 | /* The EABI specifies that all array cookies are 8 bytes long. */ | |
18276 | ||
18277 | static tree | |
18278 | arm_get_cookie_size (tree type) | |
18279 | { | |
18280 | tree size; | |
18281 | ||
18282 | if (!TARGET_AAPCS_BASED) | |
18283 | return default_cxx_get_cookie_size (type); | |
18284 | ||
7d60be94 | 18285 | size = build_int_cst (sizetype, 8); |
46e995e0 PB |
18286 | return size; |
18287 | } | |
18288 | ||
18289 | ||
18290 | /* The EABI says that array cookies should also contain the element size. */ | |
18291 | ||
18292 | static bool | |
18293 | arm_cookie_has_size (void) | |
18294 | { | |
18295 | return TARGET_AAPCS_BASED; | |
18296 | } | |
44d10c10 PB |
18297 | |
18298 | ||
18299 | /* The EABI says constructors and destructors should return a pointer to | |
18300 | the object constructed/destroyed. */ | |
18301 | ||
18302 | static bool | |
18303 | arm_cxx_cdtor_returns_this (void) | |
18304 | { | |
18305 | return TARGET_AAPCS_BASED; | |
18306 | } | |
c9ca9b88 | 18307 | |
505970fc MM |
18308 | /* The EABI says that an inline function may never be the key |
18309 | method. */ | |
18310 | ||
18311 | static bool | |
18312 | arm_cxx_key_method_may_be_inline (void) | |
18313 | { | |
18314 | return !TARGET_AAPCS_BASED; | |
18315 | } | |
18316 | ||
1e731102 MM |
18317 | static void |
18318 | arm_cxx_determine_class_data_visibility (tree decl) | |
18319 | { | |
18320 | if (!TARGET_AAPCS_BASED) | |
18321 | return; | |
505970fc | 18322 | |
1e731102 MM |
18323 | /* In general, \S 3.2.5.5 of the ARM EABI requires that class data |
18324 | is exported. However, on systems without dynamic vague linkage, | |
18325 | \S 3.2.5.6 says that COMDAT class data has hidden linkage. */ | |
18326 | if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl)) | |
18327 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
18328 | else | |
18329 | DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT; | |
18330 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
18331 | } | |
e0b92319 | 18332 | |
505970fc | 18333 | static bool |
1e731102 | 18334 | arm_cxx_class_data_always_comdat (void) |
505970fc | 18335 | { |
1e731102 MM |
18336 | /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have |
18337 | vague linkage if the class has no key function. */ | |
18338 | return !TARGET_AAPCS_BASED; | |
505970fc | 18339 | } |
c9ca9b88 | 18340 | |
9f62c3e3 PB |
18341 | |
18342 | /* The EABI says __aeabi_atexit should be used to register static | |
18343 | destructors. */ | |
18344 | ||
18345 | static bool | |
18346 | arm_cxx_use_aeabi_atexit (void) | |
18347 | { | |
18348 | return TARGET_AAPCS_BASED; | |
18349 | } | |
18350 | ||
18351 | ||
c9ca9b88 PB |
18352 | void |
18353 | arm_set_return_address (rtx source, rtx scratch) | |
18354 | { | |
18355 | arm_stack_offsets *offsets; | |
18356 | HOST_WIDE_INT delta; | |
18357 | rtx addr; | |
18358 | unsigned long saved_regs; | |
18359 | ||
954954d1 PB |
18360 | offsets = arm_get_frame_offsets (); |
18361 | saved_regs = offsets->saved_regs_mask; | |
c9ca9b88 PB |
18362 | |
18363 | if ((saved_regs & (1 << LR_REGNUM)) == 0) | |
18364 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
18365 | else | |
18366 | { | |
18367 | if (frame_pointer_needed) | |
18368 | addr = plus_constant(hard_frame_pointer_rtx, -4); | |
18369 | else | |
18370 | { | |
18371 | /* LR will be the first saved register. */ | |
c9ca9b88 PB |
18372 | delta = offsets->outgoing_args - (offsets->frame + 4); |
18373 | ||
f676971a | 18374 | |
c9ca9b88 PB |
18375 | if (delta >= 4096) |
18376 | { | |
18377 | emit_insn (gen_addsi3 (scratch, stack_pointer_rtx, | |
18378 | GEN_INT (delta & ~4095))); | |
18379 | addr = scratch; | |
18380 | delta &= 4095; | |
18381 | } | |
18382 | else | |
18383 | addr = stack_pointer_rtx; | |
18384 | ||
18385 | addr = plus_constant (addr, delta); | |
18386 | } | |
31fa16b6 | 18387 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
18388 | } |
18389 | } | |
18390 | ||
18391 | ||
18392 | void | |
18393 | thumb_set_return_address (rtx source, rtx scratch) | |
18394 | { | |
18395 | arm_stack_offsets *offsets; | |
c9ca9b88 | 18396 | HOST_WIDE_INT delta; |
5b3e6663 | 18397 | HOST_WIDE_INT limit; |
c9ca9b88 PB |
18398 | int reg; |
18399 | rtx addr; | |
57934c39 | 18400 | unsigned long mask; |
c9ca9b88 | 18401 | |
c41c1387 | 18402 | emit_use (source); |
c9ca9b88 | 18403 | |
954954d1 PB |
18404 | offsets = arm_get_frame_offsets (); |
18405 | mask = offsets->saved_regs_mask; | |
57934c39 | 18406 | if (mask & (1 << LR_REGNUM)) |
c9ca9b88 | 18407 | { |
5b3e6663 | 18408 | limit = 1024; |
c9ca9b88 PB |
18409 | /* Find the saved regs. */ |
18410 | if (frame_pointer_needed) | |
18411 | { | |
18412 | delta = offsets->soft_frame - offsets->saved_args; | |
18413 | reg = THUMB_HARD_FRAME_POINTER_REGNUM; | |
5b3e6663 PB |
18414 | if (TARGET_THUMB1) |
18415 | limit = 128; | |
c9ca9b88 PB |
18416 | } |
18417 | else | |
18418 | { | |
18419 | delta = offsets->outgoing_args - offsets->saved_args; | |
18420 | reg = SP_REGNUM; | |
18421 | } | |
18422 | /* Allow for the stack frame. */ | |
5b3e6663 | 18423 | if (TARGET_THUMB1 && TARGET_BACKTRACE) |
c9ca9b88 PB |
18424 | delta -= 16; |
18425 | /* The link register is always the first saved register. */ | |
18426 | delta -= 4; | |
f676971a | 18427 | |
c9ca9b88 PB |
18428 | /* Construct the address. */ |
18429 | addr = gen_rtx_REG (SImode, reg); | |
5b3e6663 | 18430 | if (delta > limit) |
c9ca9b88 PB |
18431 | { |
18432 | emit_insn (gen_movsi (scratch, GEN_INT (delta))); | |
18433 | emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx)); | |
18434 | addr = scratch; | |
18435 | } | |
18436 | else | |
18437 | addr = plus_constant (addr, delta); | |
18438 | ||
31fa16b6 | 18439 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
18440 | } |
18441 | else | |
18442 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
18443 | } | |
18444 | ||
f676971a EC |
18445 | /* Implements target hook vector_mode_supported_p. */ |
18446 | bool | |
18447 | arm_vector_mode_supported_p (enum machine_mode mode) | |
18448 | { | |
88f77cba JB |
18449 | /* Neon also supports V2SImode, etc. listed in the clause below. */ |
18450 | if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode | |
18451 | || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) | |
18452 | return true; | |
18453 | ||
f676971a EC |
18454 | if ((mode == V2SImode) |
18455 | || (mode == V4HImode) | |
18456 | || (mode == V8QImode)) | |
18457 | return true; | |
18458 | ||
18459 | return false; | |
18460 | } | |
273a2526 RS |
18461 | |
18462 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal | |
18463 | ARM insns and therefore guarantee that the shift count is modulo 256. | |
18464 | DImode shifts (those implemented by lib1funcs.asm or by optabs.c) | |
18465 | guarantee no particular behavior for out-of-range counts. */ | |
18466 | ||
18467 | static unsigned HOST_WIDE_INT | |
18468 | arm_shift_truncation_mask (enum machine_mode mode) | |
18469 | { | |
18470 | return mode == SImode ? 255 : 0; | |
18471 | } | |
2fa330b2 PB |
18472 | |
18473 | ||
18474 | /* Map internal gcc register numbers to DWARF2 register numbers. */ | |
18475 | ||
18476 | unsigned int | |
18477 | arm_dbx_register_number (unsigned int regno) | |
18478 | { | |
18479 | if (regno < 16) | |
18480 | return regno; | |
18481 | ||
18482 | /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards | |
18483 | compatibility. The EABI defines them as registers 96-103. */ | |
18484 | if (IS_FPA_REGNUM (regno)) | |
18485 | return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; | |
18486 | ||
f1adb0a9 | 18487 | /* FIXME: VFPv3 register numbering. */ |
2fa330b2 PB |
18488 | if (IS_VFP_REGNUM (regno)) |
18489 | return 64 + regno - FIRST_VFP_REGNUM; | |
18490 | ||
18491 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
18492 | return 104 + regno - FIRST_IWMMXT_GR_REGNUM; | |
18493 | ||
18494 | if (IS_IWMMXT_REGNUM (regno)) | |
18495 | return 112 + regno - FIRST_IWMMXT_REGNUM; | |
18496 | ||
e6d29d15 | 18497 | gcc_unreachable (); |
2fa330b2 PB |
18498 | } |
18499 | ||
617a1b71 PB |
18500 | |
18501 | #ifdef TARGET_UNWIND_INFO | |
5b3e6663 PB |
18502 | /* Emit unwind directives for a store-multiple instruction or stack pointer |
18503 | push during alignment. | |
18504 | These should only ever be generated by the function prologue code, so | |
18505 | expect them to have a particular form. */ | |
617a1b71 PB |
18506 | |
18507 | static void | |
5b3e6663 | 18508 | arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) |
617a1b71 PB |
18509 | { |
18510 | int i; | |
18511 | HOST_WIDE_INT offset; | |
18512 | HOST_WIDE_INT nregs; | |
18513 | int reg_size; | |
18514 | unsigned reg; | |
18515 | unsigned lastreg; | |
18516 | rtx e; | |
18517 | ||
617a1b71 | 18518 | e = XVECEXP (p, 0, 0); |
5b3e6663 PB |
18519 | if (GET_CODE (e) != SET) |
18520 | abort (); | |
18521 | ||
18522 | /* First insn will adjust the stack pointer. */ | |
617a1b71 PB |
18523 | if (GET_CODE (e) != SET |
18524 | || GET_CODE (XEXP (e, 0)) != REG | |
18525 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
18526 | || GET_CODE (XEXP (e, 1)) != PLUS) | |
18527 | abort (); | |
18528 | ||
18529 | offset = -INTVAL (XEXP (XEXP (e, 1), 1)); | |
18530 | nregs = XVECLEN (p, 0) - 1; | |
18531 | ||
18532 | reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1)); | |
18533 | if (reg < 16) | |
18534 | { | |
18535 | /* The function prologue may also push pc, but not annotate it as it is | |
569b7f6a | 18536 | never restored. We turn this into a stack pointer adjustment. */ |
617a1b71 PB |
18537 | if (nregs * 4 == offset - 4) |
18538 | { | |
18539 | fprintf (asm_out_file, "\t.pad #4\n"); | |
18540 | offset -= 4; | |
18541 | } | |
18542 | reg_size = 4; | |
8edfc4cc | 18543 | fprintf (asm_out_file, "\t.save {"); |
617a1b71 PB |
18544 | } |
18545 | else if (IS_VFP_REGNUM (reg)) | |
18546 | { | |
617a1b71 | 18547 | reg_size = 8; |
8edfc4cc | 18548 | fprintf (asm_out_file, "\t.vsave {"); |
617a1b71 PB |
18549 | } |
18550 | else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM) | |
18551 | { | |
18552 | /* FPA registers are done differently. */ | |
ea40ba9c | 18553 | asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs); |
617a1b71 PB |
18554 | return; |
18555 | } | |
18556 | else | |
18557 | /* Unknown register type. */ | |
18558 | abort (); | |
18559 | ||
18560 | /* If the stack increment doesn't match the size of the saved registers, | |
18561 | something has gone horribly wrong. */ | |
18562 | if (offset != nregs * reg_size) | |
18563 | abort (); | |
18564 | ||
617a1b71 PB |
18565 | offset = 0; |
18566 | lastreg = 0; | |
18567 | /* The remaining insns will describe the stores. */ | |
18568 | for (i = 1; i <= nregs; i++) | |
18569 | { | |
18570 | /* Expect (set (mem <addr>) (reg)). | |
18571 | Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ | |
18572 | e = XVECEXP (p, 0, i); | |
18573 | if (GET_CODE (e) != SET | |
18574 | || GET_CODE (XEXP (e, 0)) != MEM | |
18575 | || GET_CODE (XEXP (e, 1)) != REG) | |
18576 | abort (); | |
e0b92319 | 18577 | |
617a1b71 PB |
18578 | reg = REGNO (XEXP (e, 1)); |
18579 | if (reg < lastreg) | |
18580 | abort (); | |
e0b92319 | 18581 | |
617a1b71 PB |
18582 | if (i != 1) |
18583 | fprintf (asm_out_file, ", "); | |
18584 | /* We can't use %r for vfp because we need to use the | |
18585 | double precision register names. */ | |
18586 | if (IS_VFP_REGNUM (reg)) | |
18587 | asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2); | |
18588 | else | |
18589 | asm_fprintf (asm_out_file, "%r", reg); | |
18590 | ||
18591 | #ifdef ENABLE_CHECKING | |
18592 | /* Check that the addresses are consecutive. */ | |
18593 | e = XEXP (XEXP (e, 0), 0); | |
18594 | if (GET_CODE (e) == PLUS) | |
18595 | { | |
18596 | offset += reg_size; | |
18597 | if (GET_CODE (XEXP (e, 0)) != REG | |
18598 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
18599 | || GET_CODE (XEXP (e, 1)) != CONST_INT | |
18600 | || offset != INTVAL (XEXP (e, 1))) | |
18601 | abort (); | |
18602 | } | |
18603 | else if (i != 1 | |
18604 | || GET_CODE (e) != REG | |
18605 | || REGNO (e) != SP_REGNUM) | |
18606 | abort (); | |
18607 | #endif | |
18608 | } | |
18609 | fprintf (asm_out_file, "}\n"); | |
18610 | } | |
18611 | ||
18612 | /* Emit unwind directives for a SET. */ | |
18613 | ||
18614 | static void | |
18615 | arm_unwind_emit_set (FILE * asm_out_file, rtx p) | |
18616 | { | |
18617 | rtx e0; | |
18618 | rtx e1; | |
5b3e6663 | 18619 | unsigned reg; |
617a1b71 PB |
18620 | |
18621 | e0 = XEXP (p, 0); | |
18622 | e1 = XEXP (p, 1); | |
18623 | switch (GET_CODE (e0)) | |
18624 | { | |
18625 | case MEM: | |
18626 | /* Pushing a single register. */ | |
18627 | if (GET_CODE (XEXP (e0, 0)) != PRE_DEC | |
18628 | || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG | |
18629 | || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) | |
18630 | abort (); | |
18631 | ||
18632 | asm_fprintf (asm_out_file, "\t.save "); | |
18633 | if (IS_VFP_REGNUM (REGNO (e1))) | |
18634 | asm_fprintf(asm_out_file, "{d%d}\n", | |
18635 | (REGNO (e1) - FIRST_VFP_REGNUM) / 2); | |
18636 | else | |
18637 | asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1)); | |
18638 | break; | |
18639 | ||
18640 | case REG: | |
18641 | if (REGNO (e0) == SP_REGNUM) | |
18642 | { | |
18643 | /* A stack increment. */ | |
18644 | if (GET_CODE (e1) != PLUS | |
18645 | || GET_CODE (XEXP (e1, 0)) != REG | |
18646 | || REGNO (XEXP (e1, 0)) != SP_REGNUM | |
18647 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
18648 | abort (); | |
18649 | ||
ea40ba9c | 18650 | asm_fprintf (asm_out_file, "\t.pad #%wd\n", |
617a1b71 PB |
18651 | -INTVAL (XEXP (e1, 1))); |
18652 | } | |
18653 | else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM) | |
18654 | { | |
18655 | HOST_WIDE_INT offset; | |
e0b92319 | 18656 | |
617a1b71 PB |
18657 | if (GET_CODE (e1) == PLUS) |
18658 | { | |
18659 | if (GET_CODE (XEXP (e1, 0)) != REG | |
18660 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
18661 | abort (); | |
18662 | reg = REGNO (XEXP (e1, 0)); | |
18663 | offset = INTVAL (XEXP (e1, 1)); | |
ea40ba9c | 18664 | asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n", |
617a1b71 PB |
18665 | HARD_FRAME_POINTER_REGNUM, reg, |
18666 | INTVAL (XEXP (e1, 1))); | |
18667 | } | |
18668 | else if (GET_CODE (e1) == REG) | |
18669 | { | |
18670 | reg = REGNO (e1); | |
18671 | asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", | |
18672 | HARD_FRAME_POINTER_REGNUM, reg); | |
18673 | } | |
18674 | else | |
18675 | abort (); | |
18676 | } | |
18677 | else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) | |
18678 | { | |
18679 | /* Move from sp to reg. */ | |
18680 | asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); | |
18681 | } | |
758ed9b2 PB |
18682 | else if (GET_CODE (e1) == PLUS |
18683 | && GET_CODE (XEXP (e1, 0)) == REG | |
18684 | && REGNO (XEXP (e1, 0)) == SP_REGNUM | |
18685 | && GET_CODE (XEXP (e1, 1)) == CONST_INT) | |
18686 | { | |
18687 | /* Set reg to offset from sp. */ | |
18688 | asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n", | |
18689 | REGNO (e0), (int)INTVAL(XEXP (e1, 1))); | |
18690 | } | |
5b3e6663 PB |
18691 | else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN) |
18692 | { | |
18693 | /* Stack pointer save before alignment. */ | |
18694 | reg = REGNO (e0); | |
18695 | asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n", | |
18696 | reg + 0x90, reg); | |
18697 | } | |
617a1b71 PB |
18698 | else |
18699 | abort (); | |
18700 | break; | |
18701 | ||
18702 | default: | |
18703 | abort (); | |
18704 | } | |
18705 | } | |
18706 | ||
18707 | ||
18708 | /* Emit unwind directives for the given insn. */ | |
18709 | ||
18710 | static void | |
18711 | arm_unwind_emit (FILE * asm_out_file, rtx insn) | |
18712 | { | |
18713 | rtx pat; | |
18714 | ||
18715 | if (!ARM_EABI_UNWIND_TABLES) | |
18716 | return; | |
18717 | ||
e3b5732b | 18718 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 18719 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 18720 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
18721 | return; |
18722 | ||
617a1b71 PB |
18723 | if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn)) |
18724 | return; | |
18725 | ||
18726 | pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX); | |
18727 | if (pat) | |
18728 | pat = XEXP (pat, 0); | |
18729 | else | |
18730 | pat = PATTERN (insn); | |
18731 | ||
18732 | switch (GET_CODE (pat)) | |
18733 | { | |
18734 | case SET: | |
18735 | arm_unwind_emit_set (asm_out_file, pat); | |
18736 | break; | |
18737 | ||
18738 | case SEQUENCE: | |
18739 | /* Store multiple. */ | |
5b3e6663 | 18740 | arm_unwind_emit_sequence (asm_out_file, pat); |
617a1b71 PB |
18741 | break; |
18742 | ||
18743 | default: | |
18744 | abort(); | |
18745 | } | |
18746 | } | |
18747 | ||
18748 | ||
18749 | /* Output a reference from a function exception table to the type_info | |
18750 | object X. The EABI specifies that the symbol should be relocated by | |
18751 | an R_ARM_TARGET2 relocation. */ | |
18752 | ||
18753 | static bool | |
18754 | arm_output_ttype (rtx x) | |
18755 | { | |
18756 | fputs ("\t.word\t", asm_out_file); | |
18757 | output_addr_const (asm_out_file, x); | |
18758 | /* Use special relocations for symbol references. */ | |
18759 | if (GET_CODE (x) != CONST_INT) | |
18760 | fputs ("(TARGET2)", asm_out_file); | |
18761 | fputc ('\n', asm_out_file); | |
18762 | ||
18763 | return TRUE; | |
18764 | } | |
18765 | #endif /* TARGET_UNWIND_INFO */ | |
18766 | ||
18767 | ||
5b3e6663 PB |
18768 | /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic |
18769 | stack alignment. */ | |
18770 | ||
18771 | static void | |
18772 | arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index) | |
18773 | { | |
18774 | rtx unspec = SET_SRC (pattern); | |
18775 | gcc_assert (GET_CODE (unspec) == UNSPEC); | |
18776 | ||
18777 | switch (index) | |
18778 | { | |
18779 | case UNSPEC_STACK_ALIGN: | |
18780 | /* ??? We should set the CFA = (SP & ~7). At this point we haven't | |
18781 | put anything on the stack, so hopefully it won't matter. | |
18782 | CFA = SP will be correct after alignment. */ | |
18783 | dwarf2out_reg_save_reg (label, stack_pointer_rtx, | |
18784 | SET_DEST (pattern)); | |
18785 | break; | |
18786 | default: | |
18787 | gcc_unreachable (); | |
18788 | } | |
18789 | } | |
18790 | ||
18791 | ||
617a1b71 PB |
18792 | /* Output unwind directives for the start/end of a function. */ |
18793 | ||
18794 | void | |
18795 | arm_output_fn_unwind (FILE * f, bool prologue) | |
18796 | { | |
18797 | if (!ARM_EABI_UNWIND_TABLES) | |
18798 | return; | |
18799 | ||
18800 | if (prologue) | |
18801 | fputs ("\t.fnstart\n", f); | |
18802 | else | |
80efdb6a PB |
18803 | { |
18804 | /* If this function will never be unwound, then mark it as such. | |
18805 | The came condition is used in arm_unwind_emit to suppress | |
18806 | the frame annotations. */ | |
e3b5732b | 18807 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 18808 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 18809 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
18810 | fputs("\t.cantunwind\n", f); |
18811 | ||
18812 | fputs ("\t.fnend\n", f); | |
18813 | } | |
617a1b71 | 18814 | } |
d3585b76 DJ |
18815 | |
18816 | static bool | |
18817 | arm_emit_tls_decoration (FILE *fp, rtx x) | |
18818 | { | |
18819 | enum tls_reloc reloc; | |
18820 | rtx val; | |
18821 | ||
18822 | val = XVECEXP (x, 0, 0); | |
18823 | reloc = INTVAL (XVECEXP (x, 0, 1)); | |
18824 | ||
18825 | output_addr_const (fp, val); | |
18826 | ||
18827 | switch (reloc) | |
18828 | { | |
18829 | case TLS_GD32: | |
18830 | fputs ("(tlsgd)", fp); | |
18831 | break; | |
18832 | case TLS_LDM32: | |
18833 | fputs ("(tlsldm)", fp); | |
18834 | break; | |
18835 | case TLS_LDO32: | |
18836 | fputs ("(tlsldo)", fp); | |
18837 | break; | |
18838 | case TLS_IE32: | |
18839 | fputs ("(gottpoff)", fp); | |
18840 | break; | |
18841 | case TLS_LE32: | |
18842 | fputs ("(tpoff)", fp); | |
18843 | break; | |
18844 | default: | |
18845 | gcc_unreachable (); | |
18846 | } | |
18847 | ||
18848 | switch (reloc) | |
18849 | { | |
18850 | case TLS_GD32: | |
18851 | case TLS_LDM32: | |
18852 | case TLS_IE32: | |
18853 | fputs (" + (. - ", fp); | |
18854 | output_addr_const (fp, XVECEXP (x, 0, 2)); | |
18855 | fputs (" - ", fp); | |
18856 | output_addr_const (fp, XVECEXP (x, 0, 3)); | |
18857 | fputc (')', fp); | |
18858 | break; | |
18859 | default: | |
18860 | break; | |
18861 | } | |
18862 | ||
18863 | return TRUE; | |
18864 | } | |
18865 | ||
afcc986d JM |
18866 | /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */ |
18867 | ||
18868 | static void | |
18869 | arm_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
18870 | { | |
18871 | gcc_assert (size == 4); | |
18872 | fputs ("\t.word\t", file); | |
18873 | output_addr_const (file, x); | |
18874 | fputs ("(tlsldo)", file); | |
18875 | } | |
18876 | ||
d3585b76 DJ |
18877 | bool |
18878 | arm_output_addr_const_extra (FILE *fp, rtx x) | |
18879 | { | |
18880 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
18881 | return arm_emit_tls_decoration (fp, x); | |
f16fe45f DJ |
18882 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL) |
18883 | { | |
18884 | char label[256]; | |
18885 | int labelno = INTVAL (XVECEXP (x, 0, 0)); | |
18886 | ||
18887 | ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno); | |
18888 | assemble_name_raw (fp, label); | |
18889 | ||
18890 | return TRUE; | |
18891 | } | |
d3585b76 DJ |
18892 | else if (GET_CODE (x) == CONST_VECTOR) |
18893 | return arm_emit_vector_const (fp, x); | |
18894 | ||
18895 | return FALSE; | |
18896 | } | |
18897 | ||
5b3e6663 PB |
18898 | /* Output assembly for a shift instruction. |
18899 | SET_FLAGS determines how the instruction modifies the condition codes. | |
7a085dce | 18900 | 0 - Do not set condition codes. |
5b3e6663 PB |
18901 | 1 - Set condition codes. |
18902 | 2 - Use smallest instruction. */ | |
18903 | const char * | |
18904 | arm_output_shift(rtx * operands, int set_flags) | |
18905 | { | |
18906 | char pattern[100]; | |
18907 | static const char flag_chars[3] = {'?', '.', '!'}; | |
18908 | const char *shift; | |
18909 | HOST_WIDE_INT val; | |
18910 | char c; | |
18911 | ||
18912 | c = flag_chars[set_flags]; | |
18913 | if (TARGET_UNIFIED_ASM) | |
18914 | { | |
18915 | shift = shift_op(operands[3], &val); | |
18916 | if (shift) | |
18917 | { | |
18918 | if (val != -1) | |
18919 | operands[2] = GEN_INT(val); | |
18920 | sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c); | |
18921 | } | |
18922 | else | |
18923 | sprintf (pattern, "mov%%%c\t%%0, %%1", c); | |
18924 | } | |
18925 | else | |
18926 | sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c); | |
18927 | output_asm_insn (pattern, operands); | |
18928 | return ""; | |
18929 | } | |
18930 | ||
18931 | /* Output a Thumb-2 casesi instruction. */ | |
18932 | const char * | |
18933 | thumb2_output_casesi (rtx *operands) | |
18934 | { | |
18935 | rtx diff_vec = PATTERN (next_real_insn (operands[2])); | |
18936 | ||
18937 | gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); | |
18938 | ||
18939 | output_asm_insn ("cmp\t%0, %1", operands); | |
18940 | output_asm_insn ("bhi\t%l3", operands); | |
18941 | switch (GET_MODE(diff_vec)) | |
18942 | { | |
18943 | case QImode: | |
18944 | return "tbb\t[%|pc, %0]"; | |
18945 | case HImode: | |
18946 | return "tbh\t[%|pc, %0, lsl #1]"; | |
18947 | case SImode: | |
18948 | if (flag_pic) | |
18949 | { | |
18950 | output_asm_insn ("adr\t%4, %l2", operands); | |
18951 | output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands); | |
18952 | output_asm_insn ("add\t%4, %4, %5", operands); | |
18953 | return "bx\t%4"; | |
18954 | } | |
18955 | else | |
18956 | { | |
18957 | output_asm_insn ("adr\t%4, %l2", operands); | |
18958 | return "ldr\t%|pc, [%4, %0, lsl #2]"; | |
18959 | } | |
18960 | default: | |
18961 | gcc_unreachable (); | |
18962 | } | |
18963 | } | |
18964 | ||
bd4dc3cd PB |
18965 | /* Most ARM cores are single issue, but some newer ones can dual issue. |
18966 | The scheduler descriptions rely on this being correct. */ | |
18967 | static int | |
18968 | arm_issue_rate (void) | |
18969 | { | |
18970 | switch (arm_tune) | |
18971 | { | |
18972 | case cortexr4: | |
18973 | case cortexa8: | |
18974 | return 2; | |
18975 | ||
18976 | default: | |
18977 | return 1; | |
18978 | } | |
18979 | } | |
18980 | ||
608063c3 JB |
18981 | /* A table and a function to perform ARM-specific name mangling for |
18982 | NEON vector types in order to conform to the AAPCS (see "Procedure | |
18983 | Call Standard for the ARM Architecture", Appendix A). To qualify | |
18984 | for emission with the mangled names defined in that document, a | |
18985 | vector type must not only be of the correct mode but also be | |
18986 | composed of NEON vector element types (e.g. __builtin_neon_qi). */ | |
18987 | typedef struct | |
18988 | { | |
18989 | enum machine_mode mode; | |
18990 | const char *element_type_name; | |
18991 | const char *aapcs_name; | |
18992 | } arm_mangle_map_entry; | |
18993 | ||
18994 | static arm_mangle_map_entry arm_mangle_map[] = { | |
18995 | /* 64-bit containerized types. */ | |
18996 | { V8QImode, "__builtin_neon_qi", "15__simd64_int8_t" }, | |
18997 | { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, | |
18998 | { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, | |
18999 | { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, | |
19000 | { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, | |
19001 | { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, | |
19002 | { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, | |
19003 | { V8QImode, "__builtin_neon_poly8", "16__simd64_poly8_t" }, | |
19004 | { V4HImode, "__builtin_neon_poly16", "17__simd64_poly16_t" }, | |
19005 | /* 128-bit containerized types. */ | |
19006 | { V16QImode, "__builtin_neon_qi", "16__simd128_int8_t" }, | |
19007 | { V16QImode, "__builtin_neon_uqi", "17__simd128_uint8_t" }, | |
19008 | { V8HImode, "__builtin_neon_hi", "17__simd128_int16_t" }, | |
19009 | { V8HImode, "__builtin_neon_uhi", "18__simd128_uint16_t" }, | |
19010 | { V4SImode, "__builtin_neon_si", "17__simd128_int32_t" }, | |
19011 | { V4SImode, "__builtin_neon_usi", "18__simd128_uint32_t" }, | |
19012 | { V4SFmode, "__builtin_neon_sf", "19__simd128_float32_t" }, | |
19013 | { V16QImode, "__builtin_neon_poly8", "17__simd128_poly8_t" }, | |
19014 | { V8HImode, "__builtin_neon_poly16", "18__simd128_poly16_t" }, | |
19015 | { VOIDmode, NULL, NULL } | |
19016 | }; | |
19017 | ||
19018 | const char * | |
3101faab | 19019 | arm_mangle_type (const_tree type) |
608063c3 JB |
19020 | { |
19021 | arm_mangle_map_entry *pos = arm_mangle_map; | |
19022 | ||
19023 | if (TREE_CODE (type) != VECTOR_TYPE) | |
19024 | return NULL; | |
19025 | ||
19026 | /* Check the mode of the vector type, and the name of the vector | |
19027 | element type, against the table. */ | |
19028 | while (pos->mode != VOIDmode) | |
19029 | { | |
19030 | tree elt_type = TREE_TYPE (type); | |
19031 | ||
19032 | if (pos->mode == TYPE_MODE (type) | |
19033 | && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL | |
19034 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))), | |
19035 | pos->element_type_name)) | |
19036 | return pos->aapcs_name; | |
19037 | ||
19038 | pos++; | |
19039 | } | |
19040 | ||
19041 | /* Use the default mangling for unrecognized (possibly user-defined) | |
19042 | vector types. */ | |
19043 | return NULL; | |
19044 | } | |
19045 | ||
d3585b76 | 19046 | #include "gt-arm.h" |