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b36ba79f | 1 | /* Output routines for GCC for ARM. |
6bc82793 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
2398fb2a | 3 | Free Software Foundation, Inc. |
cce8749e | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 5 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e | 7 | |
4f448245 | 8 | This file is part of GCC. |
cce8749e | 9 | |
4f448245 NC |
10 | GCC is free software; you can redistribute it and/or modify it |
11 | under the terms of the GNU General Public License as published | |
12 | by the Free Software Foundation; either version 2, or (at your | |
13 | option) any later version. | |
cce8749e | 14 | |
4f448245 NC |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
cce8749e | 19 | |
4f448245 NC |
20 | You should have received a copy of the GNU General Public License |
21 | along with GCC; see the file COPYING. If not, write to | |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
23 | Boston, MA 02111-1307, USA. */ | |
ff9940b0 | 24 | |
56636818 | 25 | #include "config.h" |
43cffd11 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
cce8749e | 29 | #include "rtl.h" |
d5b7b3ae | 30 | #include "tree.h" |
c7319d87 | 31 | #include "obstack.h" |
cce8749e CH |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
34 | #include "real.h" | |
35 | #include "insn-config.h" | |
36 | #include "conditions.h" | |
cce8749e CH |
37 | #include "output.h" |
38 | #include "insn-attr.h" | |
39 | #include "flags.h" | |
af48348a | 40 | #include "reload.h" |
49ad7cfa | 41 | #include "function.h" |
bee06f3d | 42 | #include "expr.h" |
e78d8e51 | 43 | #include "optabs.h" |
ad076f4e | 44 | #include "toplev.h" |
aec3cfba | 45 | #include "recog.h" |
92a432f4 | 46 | #include "ggc.h" |
d5b7b3ae | 47 | #include "except.h" |
8b97c5f8 | 48 | #include "c-pragma.h" |
7b8b8ade | 49 | #include "integrate.h" |
c27ba912 | 50 | #include "tm_p.h" |
672a6f42 NB |
51 | #include "target.h" |
52 | #include "target-def.h" | |
cce8749e | 53 | |
d5b7b3ae RE |
54 | /* Forward definitions of types. */ |
55 | typedef struct minipool_node Mnode; | |
56 | typedef struct minipool_fixup Mfix; | |
57 | ||
58 | /* In order to improve the layout of the prototypes below | |
59 | some short type abbreviations are defined here. */ | |
60 | #define Hint HOST_WIDE_INT | |
61 | #define Mmode enum machine_mode | |
62 | #define Ulong unsigned long | |
6d3d9133 | 63 | #define Ccstar const char * |
d5b7b3ae | 64 | |
9b6b54e2 NC |
65 | const char extra_reg_names1[][16] = |
66 | { "mv0", "mv1", "mv2", "mv3", "mv4", "mv5", "mv6", "mv7", | |
67 | "mv8", "mv9", "mv10", "mv11", "mv12", "mv13", "mv14", "mv15" | |
68 | }; | |
69 | #define extra_reg_names1 bogus1_regnames | |
70 | ||
1d6e90ac NC |
71 | const struct attribute_spec arm_attribute_table[]; |
72 | ||
d5b7b3ae RE |
73 | /* Forward function declarations. */ |
74 | static void arm_add_gc_roots PARAMS ((void)); | |
75 | static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int)); | |
0977774b | 76 | static unsigned bit_count PARAMS ((Ulong)); |
6b990f6b | 77 | static int arm_address_register_rtx_p PARAMS ((rtx, int)); |
f0375c66 NC |
78 | static int arm_legitimate_index_p PARAMS ((Mmode, rtx, int)); |
79 | static int thumb_base_register_rtx_p PARAMS ((rtx, Mmode, int)); | |
76a318e9 | 80 | inline static int thumb_index_register_rtx_p PARAMS ((rtx, int)); |
d5b7b3ae RE |
81 | static int const_ok_for_op PARAMS ((Hint, enum rtx_code)); |
82 | static int eliminate_lr2ip PARAMS ((rtx *)); | |
83 | static rtx emit_multi_reg_push PARAMS ((int)); | |
84 | static rtx emit_sfm PARAMS ((int, int)); | |
301d03af | 85 | #ifndef AOF_ASSEMBLER |
1d6e90ac | 86 | static bool arm_assemble_integer PARAMS ((rtx, unsigned int, int)); |
301d03af | 87 | #endif |
6d3d9133 | 88 | static Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *)); |
d5b7b3ae RE |
89 | static arm_cc get_arm_condition_code PARAMS ((rtx)); |
90 | static void init_fpa_table PARAMS ((void)); | |
91 | static Hint int_log2 PARAMS ((Hint)); | |
92 | static rtx is_jump_table PARAMS ((rtx)); | |
6d3d9133 NC |
93 | static Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint)); |
94 | static void print_multi_reg PARAMS ((FILE *, Ccstar, int, int)); | |
6d3d9133 | 95 | static Ccstar shift_op PARAMS ((rtx, Hint *)); |
e2500fed | 96 | static struct machine_function * arm_init_machine_status PARAMS ((void)); |
d5b7b3ae RE |
97 | static int number_of_first_bit_set PARAMS ((int)); |
98 | static void replace_symbols_in_block PARAMS ((tree, rtx, rtx)); | |
99 | static void thumb_exit PARAMS ((FILE *, int, rtx)); | |
100 | static void thumb_pushpop PARAMS ((FILE *, int, int)); | |
6d3d9133 | 101 | static Ccstar thumb_condition_code PARAMS ((rtx, int)); |
d5b7b3ae RE |
102 | static rtx is_jump_table PARAMS ((rtx)); |
103 | static Hint get_jump_table_size PARAMS ((rtx)); | |
104 | static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint)); | |
105 | static Mnode * add_minipool_forward_ref PARAMS ((Mfix *)); | |
106 | static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint)); | |
107 | static Mnode * add_minipool_backward_ref PARAMS ((Mfix *)); | |
108 | static void assign_minipool_offsets PARAMS ((Mfix *)); | |
109 | static void arm_print_value PARAMS ((FILE *, rtx)); | |
110 | static void dump_minipool PARAMS ((rtx)); | |
111 | static int arm_barrier_cost PARAMS ((rtx)); | |
112 | static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint)); | |
113 | static void push_minipool_barrier PARAMS ((rtx, Hint)); | |
114 | static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx)); | |
b93828f3 | 115 | static bool note_invalid_constants PARAMS ((rtx, Hint, int)); |
87e27392 | 116 | static int current_file_function_operand PARAMS ((rtx)); |
1d6e90ac | 117 | static Ulong arm_compute_save_reg0_reg12_mask PARAMS ((void)); |
6d3d9133 NC |
118 | static Ulong arm_compute_save_reg_mask PARAMS ((void)); |
119 | static Ulong arm_isr_value PARAMS ((tree)); | |
120 | static Ulong arm_compute_func_type PARAMS ((void)); | |
1d6e90ac NC |
121 | static tree arm_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *)); |
122 | static tree arm_handle_isr_attribute PARAMS ((tree *, tree, tree, int, bool *)); | |
123 | static void arm_output_function_epilogue PARAMS ((FILE *, Hint)); | |
124 | static void arm_output_function_prologue PARAMS ((FILE *, Hint)); | |
125 | static void thumb_output_function_prologue PARAMS ((FILE *, Hint)); | |
8d8e52be | 126 | static int arm_comp_type_attributes PARAMS ((tree, tree)); |
f0375c66 | 127 | static void arm_set_default_type_attributes PARAMS ((tree)); |
1d6e90ac | 128 | static int arm_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
f0375c66 | 129 | static int count_insns_for_constant PARAMS ((Hint, int)); |
ab2877a3 | 130 | static int arm_get_strip_length PARAMS ((int)); |
4977bab6 | 131 | static bool arm_function_ok_for_sibcall PARAMS ((tree, tree)); |
f0375c66 NC |
132 | static void arm_internal_label PARAMS ((FILE *, Ccstar, Ulong)); |
133 | static void arm_output_mi_thunk PARAMS ((FILE *, tree, Hint, Hint, tree)); | |
134 | static int arm_rtx_costs_1 PARAMS ((rtx, enum rtx_code, enum rtx_code)); | |
135 | static bool arm_rtx_costs PARAMS ((rtx, int, int, int *)); | |
136 | static int arm_address_cost PARAMS ((rtx)); | |
137 | static bool arm_memory_load_p PARAMS ((rtx)); | |
138 | static bool arm_cirrus_insn_p PARAMS ((rtx)); | |
139 | static void cirrus_reorg PARAMS ((rtx)); | |
ebe413e5 | 140 | #ifdef OBJECT_FORMAT_ELF |
f0375c66 | 141 | static void arm_elf_asm_named_section PARAMS ((Ccstar, unsigned int)); |
ebe413e5 | 142 | #endif |
fb49053f | 143 | #ifndef ARM_PE |
c6a2438a | 144 | static void arm_encode_section_info PARAMS ((tree, rtx, int)); |
fb49053f | 145 | #endif |
5eb99654 | 146 | #ifdef AOF_ASSEMBLER |
f0375c66 | 147 | static void aof_globalize_label PARAMS ((FILE *, Ccstar)); |
5eb99654 | 148 | #endif |
c237e94a | 149 | |
d5b7b3ae RE |
150 | #undef Hint |
151 | #undef Mmode | |
152 | #undef Ulong | |
6d3d9133 | 153 | #undef Ccstar |
672a6f42 NB |
154 | \f |
155 | /* Initialize the GCC target structure. */ | |
156 | #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES | |
1d6e90ac | 157 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
672a6f42 NB |
158 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes |
159 | #endif | |
f3bb6135 | 160 | |
1d6e90ac | 161 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 162 | #define TARGET_ATTRIBUTE_TABLE arm_attribute_table |
672a6f42 | 163 | |
301d03af | 164 | #ifdef AOF_ASSEMBLER |
1d6e90ac | 165 | #undef TARGET_ASM_BYTE_OP |
301d03af | 166 | #define TARGET_ASM_BYTE_OP "\tDCB\t" |
1d6e90ac | 167 | #undef TARGET_ASM_ALIGNED_HI_OP |
301d03af | 168 | #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t" |
1d6e90ac | 169 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 170 | #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t" |
5eb99654 KG |
171 | #undef TARGET_ASM_GLOBALIZE_LABEL |
172 | #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label | |
301d03af | 173 | #else |
1d6e90ac | 174 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 175 | #define TARGET_ASM_ALIGNED_SI_OP NULL |
1d6e90ac | 176 | #undef TARGET_ASM_INTEGER |
301d03af RS |
177 | #define TARGET_ASM_INTEGER arm_assemble_integer |
178 | #endif | |
179 | ||
1d6e90ac | 180 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 NB |
181 | #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue |
182 | ||
1d6e90ac | 183 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
184 | #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue |
185 | ||
1d6e90ac | 186 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
8d8e52be JM |
187 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes |
188 | ||
1d6e90ac | 189 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
8d8e52be JM |
190 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes |
191 | ||
1d6e90ac | 192 | #undef TARGET_SCHED_ADJUST_COST |
c237e94a ZW |
193 | #define TARGET_SCHED_ADJUST_COST arm_adjust_cost |
194 | ||
fb49053f RH |
195 | #undef TARGET_ENCODE_SECTION_INFO |
196 | #ifdef ARM_PE | |
197 | #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info | |
198 | #else | |
199 | #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info | |
200 | #endif | |
201 | ||
772c5265 RH |
202 | #undef TARGET_STRIP_NAME_ENCODING |
203 | #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding | |
204 | ||
4977bab6 ZW |
205 | #undef TARGET_ASM_INTERNAL_LABEL |
206 | #define TARGET_ASM_INTERNAL_LABEL arm_internal_label | |
207 | ||
208 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL | |
209 | #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall | |
210 | ||
c590b625 RH |
211 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
212 | #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk | |
3961e8fe RH |
213 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
214 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 215 | |
3c50106f RH |
216 | #undef TARGET_RTX_COSTS |
217 | #define TARGET_RTX_COSTS arm_rtx_costs | |
dcefdf67 RH |
218 | #undef TARGET_ADDRESS_COST |
219 | #define TARGET_ADDRESS_COST arm_address_cost | |
3c50106f | 220 | |
f6897b10 | 221 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 222 | \f |
c7319d87 RE |
223 | /* Obstack for minipool constant handling. */ |
224 | static struct obstack minipool_obstack; | |
1d6e90ac | 225 | static char * minipool_startobj; |
c7319d87 | 226 | |
1d6e90ac NC |
227 | /* The maximum number of insns skipped which |
228 | will be conditionalised if possible. */ | |
c27ba912 DM |
229 | static int max_insns_skipped = 5; |
230 | ||
231 | extern FILE * asm_out_file; | |
232 | ||
6354dc9b | 233 | /* True if we are currently building a constant table. */ |
13bd191d PB |
234 | int making_const_table; |
235 | ||
60d0536b | 236 | /* Define the information needed to generate branch insns. This is |
6354dc9b | 237 | stored from the compare operation. */ |
ff9940b0 | 238 | rtx arm_compare_op0, arm_compare_op1; |
ff9940b0 | 239 | |
6354dc9b | 240 | /* What type of floating point are we tuning for? */ |
29ad9694 | 241 | enum fputype arm_fpu_tune; |
bee06f3d | 242 | |
6354dc9b | 243 | /* What type of floating point instructions are available? */ |
29ad9694 | 244 | enum fputype arm_fpu_arch; |
b111229a | 245 | |
6354dc9b | 246 | /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */ |
2b835d68 RE |
247 | enum prog_mode_type arm_prgmode; |
248 | ||
6354dc9b | 249 | /* Set by the -mfp=... option. */ |
f9cc092a | 250 | const char * target_fp_name = NULL; |
2b835d68 | 251 | |
b355a481 | 252 | /* Used to parse -mstructure_size_boundary command line option. */ |
f9cc092a | 253 | const char * structure_size_string = NULL; |
723ae7c1 | 254 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 255 | |
aec3cfba | 256 | /* Bit values used to identify processor capabilities. */ |
62b10bbc NC |
257 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
258 | #define FL_FAST_MULT (1 << 1) /* Fast multiply */ | |
259 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ | |
260 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
261 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
262 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
263 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
264 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
265 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
6bc82793 | 266 | #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ |
d19fb8e3 | 267 | #define FL_XSCALE (1 << 10) /* XScale */ |
9b6b54e2 | 268 | #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ |
aec3cfba | 269 | |
1d6e90ac NC |
270 | /* The bits in this mask specify which |
271 | instructions we are allowed to generate. */ | |
0977774b | 272 | static unsigned long insn_flags = 0; |
d5b7b3ae | 273 | |
aec3cfba NC |
274 | /* The bits in this mask specify which instruction scheduling options should |
275 | be used. Note - there is an overlap with the FL_FAST_MULT. For some | |
276 | hardware we want to be able to generate the multiply instructions, but to | |
277 | tune as if they were not present in the architecture. */ | |
0977774b | 278 | static unsigned long tune_flags = 0; |
aec3cfba NC |
279 | |
280 | /* The following are used in the arm.md file as equivalents to bits | |
281 | in the above two flag variables. */ | |
282 | ||
2b835d68 RE |
283 | /* Nonzero if this is an "M" variant of the processor. */ |
284 | int arm_fast_multiply = 0; | |
285 | ||
6354dc9b | 286 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
287 | int arm_arch4 = 0; |
288 | ||
6354dc9b | 289 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
290 | int arm_arch5 = 0; |
291 | ||
b15bca31 RE |
292 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
293 | int arm_arch5e = 0; | |
294 | ||
aec3cfba | 295 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
296 | int arm_ld_sched = 0; |
297 | ||
298 | /* Nonzero if this chip is a StrongARM. */ | |
299 | int arm_is_strong = 0; | |
300 | ||
d19fb8e3 NC |
301 | /* Nonzero if this chip is an XScale. */ |
302 | int arm_is_xscale = 0; | |
303 | ||
3569057d | 304 | /* Nonzero if this chip is an ARM6 or an ARM7. */ |
f5a1b0d2 | 305 | int arm_is_6_or_7 = 0; |
b111229a | 306 | |
9b6b54e2 NC |
307 | /* Nonzero if this chip is a Cirrus/DSP. */ |
308 | int arm_is_cirrus = 0; | |
309 | ||
0616531f RE |
310 | /* Nonzero if generating Thumb instructions. */ |
311 | int thumb_code = 0; | |
312 | ||
cce8749e CH |
313 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we |
314 | must report the mode of the memory reference from PRINT_OPERAND to | |
315 | PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 316 | enum machine_mode output_memory_reference_mode; |
cce8749e | 317 | |
32de079a | 318 | /* The register number to be used for the PIC offset register. */ |
ed0e6530 | 319 | const char * arm_pic_register_string = NULL; |
5b43fed1 | 320 | int arm_pic_register = INVALID_REGNUM; |
32de079a | 321 | |
ff9940b0 | 322 | /* Set to 1 when a return insn is output, this means that the epilogue |
6354dc9b | 323 | is not needed. */ |
d5b7b3ae | 324 | int return_used_this_function; |
ff9940b0 | 325 | |
aec3cfba NC |
326 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
327 | the next function. */ | |
4b632bf1 RE |
328 | static int after_arm_reorg = 0; |
329 | ||
aec3cfba | 330 | /* The maximum number of insns to be used when loading a constant. */ |
2b835d68 RE |
331 | static int arm_constant_limit = 3; |
332 | ||
cce8749e CH |
333 | /* For an explanation of these variables, see final_prescan_insn below. */ |
334 | int arm_ccfsm_state; | |
84ed5e79 | 335 | enum arm_cond_code arm_current_cc; |
cce8749e CH |
336 | rtx arm_target_insn; |
337 | int arm_target_label; | |
9997d19d RE |
338 | |
339 | /* The condition codes of the ARM, and the inverse function. */ | |
1d6e90ac | 340 | static const char * const arm_condition_codes[] = |
9997d19d RE |
341 | { |
342 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
343 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
344 | }; | |
345 | ||
f5a1b0d2 | 346 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
2b835d68 | 347 | \f |
6354dc9b | 348 | /* Initialization code. */ |
2b835d68 | 349 | |
2b835d68 RE |
350 | struct processors |
351 | { | |
8b60264b | 352 | const char *const name; |
0977774b | 353 | const unsigned long flags; |
2b835d68 RE |
354 | }; |
355 | ||
356 | /* Not all of these give usefully different compilation alternatives, | |
357 | but there is no simple way of generalizing them. */ | |
8b60264b | 358 | static const struct processors all_cores[] = |
f5a1b0d2 NC |
359 | { |
360 | /* ARM Cores */ | |
361 | ||
362 | {"arm2", FL_CO_PROC | FL_MODE26 }, | |
363 | {"arm250", FL_CO_PROC | FL_MODE26 }, | |
364 | {"arm3", FL_CO_PROC | FL_MODE26 }, | |
365 | {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
366 | {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
367 | {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
368 | {"arm610", FL_MODE26 | FL_MODE32 }, | |
369 | {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
949d79eb RE |
370 | {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, |
371 | /* arm7m doesn't exist on its own, but only with D, (and I), but | |
d5b7b3ae | 372 | those don't alter the code, so arm7m is sometimes used. */ |
949d79eb RE |
373 | {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, |
374 | {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
375 | {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, | |
376 | {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
f5a1b0d2 NC |
377 | {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, |
378 | {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
379 | {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
380 | {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
381 | {"arm710", FL_MODE26 | FL_MODE32 }, | |
eab4abeb | 382 | {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB }, |
a120a3bd | 383 | {"arm720", FL_MODE26 | FL_MODE32 }, |
eab4abeb NC |
384 | {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB }, |
385 | {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB }, | |
f5a1b0d2 NC |
386 | {"arm710c", FL_MODE26 | FL_MODE32 }, |
387 | {"arm7100", FL_MODE26 | FL_MODE32 }, | |
388 | {"arm7500", FL_MODE26 | FL_MODE32 }, | |
3b684012 | 389 | /* Doesn't have an external co-proc, but does have embedded fpa. */ |
949d79eb | 390 | {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, |
f5a1b0d2 NC |
391 | {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, |
392 | {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, | |
393 | {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, | |
394 | {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, | |
6cf32035 NC |
395 | {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, |
396 | {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, | |
eab4abeb | 397 | {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, |
f5a1b0d2 | 398 | {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, |
eab4abeb | 399 | {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, |
9b6b54e2 | 400 | {"ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS }, |
f5a1b0d2 NC |
401 | {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, |
402 | {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, | |
403 | {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, | |
eab4abeb NC |
404 | {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, |
405 | {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, | |
406 | {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, | |
407 | {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE }, | |
e26053d1 | 408 | |
f5a1b0d2 NC |
409 | {NULL, 0} |
410 | }; | |
411 | ||
8b60264b | 412 | static const struct processors all_architectures[] = |
2b835d68 | 413 | { |
f5a1b0d2 NC |
414 | /* ARM Architectures */ |
415 | ||
62b10bbc NC |
416 | { "armv2", FL_CO_PROC | FL_MODE26 }, |
417 | { "armv2a", FL_CO_PROC | FL_MODE26 }, | |
418 | { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
419 | { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, | |
949d79eb | 420 | { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 }, |
b111229a RE |
421 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
422 | implementations that support it, so we will leave it out for now. */ | |
62b10bbc NC |
423 | { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, |
424 | { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, | |
d19fb8e3 NC |
425 | { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, |
426 | { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, | |
9b6b54e2 | 427 | { "ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS }, |
62b10bbc | 428 | { NULL, 0 } |
f5a1b0d2 NC |
429 | }; |
430 | ||
431 | /* This is a magic stucture. The 'string' field is magically filled in | |
432 | with a pointer to the value specified by the user on the command line | |
433 | assuming that the user has specified such a value. */ | |
434 | ||
435 | struct arm_cpu_select arm_select[] = | |
436 | { | |
437 | /* string name processors */ | |
438 | { NULL, "-mcpu=", all_cores }, | |
439 | { NULL, "-march=", all_architectures }, | |
440 | { NULL, "-mtune=", all_cores } | |
2b835d68 RE |
441 | }; |
442 | ||
0977774b JT |
443 | /* Return the number of bits set in VALUE. */ |
444 | static unsigned | |
aec3cfba | 445 | bit_count (value) |
0977774b | 446 | unsigned long value; |
aec3cfba | 447 | { |
d5b7b3ae | 448 | unsigned long count = 0; |
aec3cfba NC |
449 | |
450 | while (value) | |
451 | { | |
0977774b JT |
452 | count++; |
453 | value &= value - 1; /* Clear the least-significant set bit. */ | |
aec3cfba NC |
454 | } |
455 | ||
456 | return count; | |
457 | } | |
458 | ||
2b835d68 RE |
459 | /* Fix up any incompatible options that the user has specified. |
460 | This has now turned into a maze. */ | |
461 | void | |
462 | arm_override_options () | |
463 | { | |
ed4c4348 | 464 | unsigned i; |
f5a1b0d2 NC |
465 | |
466 | /* Set up the flags based on the cpu/architecture selected by the user. */ | |
b6a1cbae | 467 | for (i = ARRAY_SIZE (arm_select); i--;) |
bd9c7e23 | 468 | { |
f5a1b0d2 NC |
469 | struct arm_cpu_select * ptr = arm_select + i; |
470 | ||
471 | if (ptr->string != NULL && ptr->string[0] != '\0') | |
bd9c7e23 | 472 | { |
13bd191d | 473 | const struct processors * sel; |
bd9c7e23 | 474 | |
5895f793 | 475 | for (sel = ptr->processors; sel->name != NULL; sel++) |
f5a1b0d2 | 476 | if (streq (ptr->string, sel->name)) |
bd9c7e23 | 477 | { |
aec3cfba NC |
478 | if (i == 2) |
479 | tune_flags = sel->flags; | |
480 | else | |
b111229a | 481 | { |
aec3cfba NC |
482 | /* If we have been given an architecture and a processor |
483 | make sure that they are compatible. We only generate | |
484 | a warning though, and we prefer the CPU over the | |
6354dc9b | 485 | architecture. */ |
aec3cfba | 486 | if (insn_flags != 0 && (insn_flags ^ sel->flags)) |
6cf32035 | 487 | warning ("switch -mcpu=%s conflicts with -march= switch", |
aec3cfba NC |
488 | ptr->string); |
489 | ||
490 | insn_flags = sel->flags; | |
b111229a | 491 | } |
f5a1b0d2 | 492 | |
bd9c7e23 RE |
493 | break; |
494 | } | |
495 | ||
496 | if (sel->name == NULL) | |
497 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
498 | } | |
499 | } | |
aec3cfba | 500 | |
f5a1b0d2 | 501 | /* If the user did not specify a processor, choose one for them. */ |
aec3cfba | 502 | if (insn_flags == 0) |
f5a1b0d2 | 503 | { |
8b60264b | 504 | const struct processors * sel; |
aec3cfba | 505 | unsigned int sought; |
8b60264b | 506 | static const struct cpu_default |
aec3cfba | 507 | { |
8b60264b KG |
508 | const int cpu; |
509 | const char *const name; | |
aec3cfba NC |
510 | } |
511 | cpu_defaults[] = | |
512 | { | |
513 | { TARGET_CPU_arm2, "arm2" }, | |
514 | { TARGET_CPU_arm6, "arm6" }, | |
515 | { TARGET_CPU_arm610, "arm610" }, | |
2aa0c933 | 516 | { TARGET_CPU_arm710, "arm710" }, |
aec3cfba NC |
517 | { TARGET_CPU_arm7m, "arm7m" }, |
518 | { TARGET_CPU_arm7500fe, "arm7500fe" }, | |
519 | { TARGET_CPU_arm7tdmi, "arm7tdmi" }, | |
520 | { TARGET_CPU_arm8, "arm8" }, | |
521 | { TARGET_CPU_arm810, "arm810" }, | |
522 | { TARGET_CPU_arm9, "arm9" }, | |
523 | { TARGET_CPU_strongarm, "strongarm" }, | |
d19fb8e3 | 524 | { TARGET_CPU_xscale, "xscale" }, |
9b6b54e2 | 525 | { TARGET_CPU_ep9312, "ep9312" }, |
aec3cfba NC |
526 | { TARGET_CPU_generic, "arm" }, |
527 | { 0, 0 } | |
528 | }; | |
8b60264b | 529 | const struct cpu_default * def; |
aec3cfba NC |
530 | |
531 | /* Find the default. */ | |
5895f793 | 532 | for (def = cpu_defaults; def->name; def++) |
aec3cfba NC |
533 | if (def->cpu == TARGET_CPU_DEFAULT) |
534 | break; | |
535 | ||
536 | /* Make sure we found the default CPU. */ | |
537 | if (def->name == NULL) | |
538 | abort (); | |
539 | ||
540 | /* Find the default CPU's flags. */ | |
5895f793 | 541 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
542 | if (streq (def->name, sel->name)) |
543 | break; | |
544 | ||
545 | if (sel->name == NULL) | |
546 | abort (); | |
547 | ||
548 | insn_flags = sel->flags; | |
549 | ||
550 | /* Now check to see if the user has specified some command line | |
551 | switch that require certain abilities from the cpu. */ | |
552 | sought = 0; | |
f5a1b0d2 | 553 | |
d5b7b3ae | 554 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 555 | { |
aec3cfba NC |
556 | sought |= (FL_THUMB | FL_MODE32); |
557 | ||
558 | /* Force apcs-32 to be used for interworking. */ | |
f5a1b0d2 | 559 | target_flags |= ARM_FLAG_APCS_32; |
aec3cfba | 560 | |
d5b7b3ae | 561 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
562 | interworking. Therefore we force FL_MODE26 to be removed |
563 | from insn_flags here (if it was set), so that the search | |
564 | below will always be able to find a compatible processor. */ | |
5895f793 | 565 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 566 | } |
5895f793 | 567 | else if (!TARGET_APCS_32) |
f5a1b0d2 | 568 | sought |= FL_MODE26; |
d5b7b3ae | 569 | |
aec3cfba | 570 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 571 | { |
aec3cfba NC |
572 | /* Try to locate a CPU type that supports all of the abilities |
573 | of the default CPU, plus the extra abilities requested by | |
574 | the user. */ | |
5895f793 | 575 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 576 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
577 | break; |
578 | ||
579 | if (sel->name == NULL) | |
aec3cfba | 580 | { |
0977774b | 581 | unsigned current_bit_count = 0; |
8b60264b | 582 | const struct processors * best_fit = NULL; |
aec3cfba NC |
583 | |
584 | /* Ideally we would like to issue an error message here | |
585 | saying that it was not possible to find a CPU compatible | |
586 | with the default CPU, but which also supports the command | |
587 | line options specified by the programmer, and so they | |
588 | ought to use the -mcpu=<name> command line option to | |
589 | override the default CPU type. | |
590 | ||
591 | Unfortunately this does not work with multilibing. We | |
592 | need to be able to support multilibs for -mapcs-26 and for | |
593 | -mthumb-interwork and there is no CPU that can support both | |
594 | options. Instead if we cannot find a cpu that has both the | |
595 | characteristics of the default cpu and the given command line | |
596 | options we scan the array again looking for a best match. */ | |
5895f793 | 597 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
598 | if ((sel->flags & sought) == sought) |
599 | { | |
0977774b | 600 | unsigned count; |
aec3cfba NC |
601 | |
602 | count = bit_count (sel->flags & insn_flags); | |
603 | ||
604 | if (count >= current_bit_count) | |
605 | { | |
606 | best_fit = sel; | |
607 | current_bit_count = count; | |
608 | } | |
609 | } | |
f5a1b0d2 | 610 | |
aec3cfba NC |
611 | if (best_fit == NULL) |
612 | abort (); | |
613 | else | |
614 | sel = best_fit; | |
615 | } | |
616 | ||
617 | insn_flags = sel->flags; | |
f5a1b0d2 NC |
618 | } |
619 | } | |
aec3cfba NC |
620 | |
621 | /* If tuning has not been specified, tune for whichever processor or | |
622 | architecture has been selected. */ | |
623 | if (tune_flags == 0) | |
624 | tune_flags = insn_flags; | |
e26053d1 | 625 | |
f5a1b0d2 NC |
626 | /* Make sure that the processor choice does not conflict with any of the |
627 | other command line choices. */ | |
aec3cfba | 628 | if (TARGET_APCS_32 && !(insn_flags & FL_MODE32)) |
f5a1b0d2 | 629 | { |
aec3cfba NC |
630 | /* If APCS-32 was not the default then it must have been set by the |
631 | user, so issue a warning message. If the user has specified | |
632 | "-mapcs-32 -mcpu=arm2" then we loose here. */ | |
633 | if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0) | |
634 | warning ("target CPU does not support APCS-32" ); | |
5895f793 | 635 | target_flags &= ~ARM_FLAG_APCS_32; |
f5a1b0d2 | 636 | } |
5895f793 | 637 | else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26)) |
f5a1b0d2 NC |
638 | { |
639 | warning ("target CPU does not support APCS-26" ); | |
640 | target_flags |= ARM_FLAG_APCS_32; | |
641 | } | |
642 | ||
6cfc7210 | 643 | if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) |
f5a1b0d2 NC |
644 | { |
645 | warning ("target CPU does not support interworking" ); | |
6cfc7210 | 646 | target_flags &= ~ARM_FLAG_INTERWORK; |
f5a1b0d2 NC |
647 | } |
648 | ||
d5b7b3ae RE |
649 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
650 | { | |
c725bd79 | 651 | warning ("target CPU does not support THUMB instructions"); |
d5b7b3ae RE |
652 | target_flags &= ~ARM_FLAG_THUMB; |
653 | } | |
654 | ||
655 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
656 | { | |
c725bd79 | 657 | /* warning ("ignoring -mapcs-frame because -mthumb was used"); */ |
d5b7b3ae RE |
658 | target_flags &= ~ARM_FLAG_APCS_FRAME; |
659 | } | |
d19fb8e3 | 660 | |
d5b7b3ae RE |
661 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
662 | from here where no function is being compiled currently. */ | |
663 | if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE)) | |
664 | && TARGET_ARM) | |
c725bd79 | 665 | warning ("enabling backtrace support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
666 | |
667 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
c725bd79 | 668 | warning ("enabling callee interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
669 | |
670 | if (TARGET_ARM && TARGET_CALLER_INTERWORKING) | |
c725bd79 | 671 | warning ("enabling caller interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae | 672 | |
f5a1b0d2 | 673 | /* If interworking is enabled then APCS-32 must be selected as well. */ |
6cfc7210 | 674 | if (TARGET_INTERWORK) |
f5a1b0d2 | 675 | { |
5895f793 | 676 | if (!TARGET_APCS_32) |
f5a1b0d2 NC |
677 | warning ("interworking forces APCS-32 to be used" ); |
678 | target_flags |= ARM_FLAG_APCS_32; | |
679 | } | |
680 | ||
5895f793 | 681 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 NC |
682 | { |
683 | warning ("-mapcs-stack-check incompatible with -mno-apcs-frame"); | |
684 | target_flags |= ARM_FLAG_APCS_FRAME; | |
685 | } | |
aec3cfba | 686 | |
2b835d68 RE |
687 | if (TARGET_POKE_FUNCTION_NAME) |
688 | target_flags |= ARM_FLAG_APCS_FRAME; | |
aec3cfba | 689 | |
2b835d68 | 690 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 691 | error ("-fpic and -mapcs-reent are incompatible"); |
aec3cfba | 692 | |
2b835d68 | 693 | if (TARGET_APCS_REENT) |
f5a1b0d2 | 694 | warning ("APCS reentrant code not supported. Ignored"); |
aec3cfba | 695 | |
d5b7b3ae RE |
696 | /* If this target is normally configured to use APCS frames, warn if they |
697 | are turned off and debugging is turned on. */ | |
698 | if (TARGET_ARM | |
699 | && write_symbols != NO_DEBUG | |
5895f793 | 700 | && !TARGET_APCS_FRAME |
d5b7b3ae RE |
701 | && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME)) |
702 | warning ("-g with -mno-apcs-frame may not give sensible debugging"); | |
6cfc7210 | 703 | |
32de079a RE |
704 | /* If stack checking is disabled, we can use r10 as the PIC register, |
705 | which keeps r9 available. */ | |
5b43fed1 RH |
706 | if (flag_pic) |
707 | arm_pic_register = TARGET_APCS_STACK ? 9 : 10; | |
aec3cfba | 708 | |
2b835d68 | 709 | if (TARGET_APCS_FLOAT) |
c725bd79 | 710 | warning ("passing floating point arguments in fp regs not yet supported"); |
f5a1b0d2 | 711 | |
4912a07c | 712 | /* Initialize boolean versions of the flags, for use in the arm.md file. */ |
2ca12935 JL |
713 | arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0; |
714 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
715 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; | |
b15bca31 | 716 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; |
a67ded0f | 717 | arm_is_xscale = (insn_flags & FL_XSCALE) != 0; |
6f7ebcbb | 718 | |
2ca12935 JL |
719 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; |
720 | arm_is_strong = (tune_flags & FL_STRONG) != 0; | |
0616531f | 721 | thumb_code = (TARGET_ARM == 0); |
d5b7b3ae RE |
722 | arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32)) |
723 | && !(tune_flags & FL_ARCH4))) != 0; | |
9b6b54e2 | 724 | arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0; |
6f7ebcbb | 725 | |
9b6b54e2 NC |
726 | if (arm_is_cirrus) |
727 | { | |
29ad9694 | 728 | arm_fpu_tune = FPUTYPE_MAVERICK; |
9b6b54e2 NC |
729 | |
730 | /* Ignore -mhard-float if -mcpu=ep9312. */ | |
731 | if (TARGET_HARD_FLOAT) | |
732 | target_flags ^= ARM_FLAG_SOFT_FLOAT; | |
733 | } | |
734 | else | |
735 | /* Default value for floating point code... if no co-processor | |
736 | bus, then schedule for emulated floating point. Otherwise, | |
737 | assume the user has an FPA. | |
738 | Note: this does not prevent use of floating point instructions, | |
739 | -msoft-float does that. */ | |
29ad9694 | 740 | arm_fpu_tune = (tune_flags & FL_CO_PROC) ? FPUTYPE_FPA : FPUTYPE_FPA_EMU3; |
f5a1b0d2 | 741 | |
b111229a | 742 | if (target_fp_name) |
2b835d68 | 743 | { |
f5a1b0d2 | 744 | if (streq (target_fp_name, "2")) |
29ad9694 | 745 | arm_fpu_arch = FPUTYPE_FPA_EMU2; |
f5a1b0d2 | 746 | else if (streq (target_fp_name, "3")) |
29ad9694 | 747 | arm_fpu_arch = FPUTYPE_FPA_EMU3; |
2b835d68 | 748 | else |
c725bd79 | 749 | error ("invalid floating point emulation option: -mfpe-%s", |
b111229a | 750 | target_fp_name); |
2b835d68 | 751 | } |
b111229a | 752 | else |
29ad9694 | 753 | arm_fpu_arch = FPUTYPE_DEFAULT; |
f5a1b0d2 | 754 | |
9b6b54e2 NC |
755 | if (TARGET_FPE) |
756 | { | |
29ad9694 RE |
757 | if (arm_fpu_tune == FPUTYPE_FPA_EMU3) |
758 | arm_fpu_tune = FPUTYPE_FPA_EMU2; | |
759 | else if (arm_fpu_tune == FPUTYPE_MAVERICK) | |
760 | warning ("-mfpe switch not supported by ep9312 target cpu - ignored."); | |
761 | else if (arm_fpu_tune != FPUTYPE_FPA) | |
762 | arm_fpu_tune = FPUTYPE_FPA_EMU2; | |
9b6b54e2 | 763 | } |
aec3cfba | 764 | |
f5a1b0d2 NC |
765 | /* For arm2/3 there is no need to do any scheduling if there is only |
766 | a floating point emulator, or we are doing software floating-point. */ | |
29ad9694 | 767 | if ((TARGET_SOFT_FLOAT || arm_fpu_tune != FPUTYPE_FPA) |
ed0e6530 | 768 | && (tune_flags & FL_MODE32) == 0) |
f5a1b0d2 | 769 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
aec3cfba | 770 | |
cd2b33d0 | 771 | arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26; |
b355a481 NC |
772 | |
773 | if (structure_size_string != NULL) | |
774 | { | |
775 | int size = strtol (structure_size_string, NULL, 0); | |
776 | ||
777 | if (size == 8 || size == 32) | |
778 | arm_structure_size_boundary = size; | |
779 | else | |
c725bd79 | 780 | warning ("structure size boundary can only be set to 8 or 32"); |
b355a481 | 781 | } |
ed0e6530 PB |
782 | |
783 | if (arm_pic_register_string != NULL) | |
784 | { | |
5b43fed1 | 785 | int pic_register = decode_reg_name (arm_pic_register_string); |
e26053d1 | 786 | |
5895f793 | 787 | if (!flag_pic) |
ed0e6530 PB |
788 | warning ("-mpic-register= is useless without -fpic"); |
789 | ||
ed0e6530 | 790 | /* Prevent the user from choosing an obviously stupid PIC register. */ |
5b43fed1 RH |
791 | else if (pic_register < 0 || call_used_regs[pic_register] |
792 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
793 | || pic_register == STACK_POINTER_REGNUM | |
794 | || pic_register >= PC_REGNUM) | |
c725bd79 | 795 | error ("unable to use '%s' for PIC register", arm_pic_register_string); |
ed0e6530 PB |
796 | else |
797 | arm_pic_register = pic_register; | |
798 | } | |
d5b7b3ae RE |
799 | |
800 | if (TARGET_THUMB && flag_schedule_insns) | |
801 | { | |
802 | /* Don't warn since it's on by default in -O2. */ | |
803 | flag_schedule_insns = 0; | |
804 | } | |
805 | ||
f5a1b0d2 NC |
806 | /* If optimizing for space, don't synthesize constants. |
807 | For processors with load scheduling, it never costs more than 2 cycles | |
808 | to load a constant, and the load scheduler may well reduce that to 1. */ | |
aec3cfba | 809 | if (optimize_size || (tune_flags & FL_LDSCHED)) |
f5a1b0d2 | 810 | arm_constant_limit = 1; |
aec3cfba | 811 | |
d19fb8e3 NC |
812 | if (arm_is_xscale) |
813 | arm_constant_limit = 2; | |
814 | ||
f5a1b0d2 NC |
815 | /* If optimizing for size, bump the number of instructions that we |
816 | are prepared to conditionally execute (even on a StrongARM). | |
817 | Otherwise for the StrongARM, which has early execution of branches, | |
818 | a sequence that is worth skipping is shorter. */ | |
819 | if (optimize_size) | |
820 | max_insns_skipped = 6; | |
821 | else if (arm_is_strong) | |
822 | max_insns_skipped = 3; | |
92a432f4 RE |
823 | |
824 | /* Register global variables with the garbage collector. */ | |
825 | arm_add_gc_roots (); | |
826 | } | |
827 | ||
828 | static void | |
829 | arm_add_gc_roots () | |
830 | { | |
c7319d87 RE |
831 | gcc_obstack_init(&minipool_obstack); |
832 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 833 | } |
cce8749e | 834 | \f |
6d3d9133 NC |
835 | /* A table of known ARM exception types. |
836 | For use with the interrupt function attribute. */ | |
837 | ||
838 | typedef struct | |
839 | { | |
8b60264b KG |
840 | const char *const arg; |
841 | const unsigned long return_value; | |
6d3d9133 NC |
842 | } |
843 | isr_attribute_arg; | |
844 | ||
8b60264b | 845 | static const isr_attribute_arg isr_attribute_args [] = |
6d3d9133 NC |
846 | { |
847 | { "IRQ", ARM_FT_ISR }, | |
848 | { "irq", ARM_FT_ISR }, | |
849 | { "FIQ", ARM_FT_FIQ }, | |
850 | { "fiq", ARM_FT_FIQ }, | |
851 | { "ABORT", ARM_FT_ISR }, | |
852 | { "abort", ARM_FT_ISR }, | |
853 | { "ABORT", ARM_FT_ISR }, | |
854 | { "abort", ARM_FT_ISR }, | |
855 | { "UNDEF", ARM_FT_EXCEPTION }, | |
856 | { "undef", ARM_FT_EXCEPTION }, | |
857 | { "SWI", ARM_FT_EXCEPTION }, | |
858 | { "swi", ARM_FT_EXCEPTION }, | |
859 | { NULL, ARM_FT_NORMAL } | |
860 | }; | |
861 | ||
862 | /* Returns the (interrupt) function type of the current | |
863 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
864 | ||
865 | static unsigned long | |
866 | arm_isr_value (argument) | |
867 | tree argument; | |
868 | { | |
8b60264b | 869 | const isr_attribute_arg * ptr; |
1d6e90ac | 870 | const char * arg; |
6d3d9133 NC |
871 | |
872 | /* No argument - default to IRQ. */ | |
873 | if (argument == NULL_TREE) | |
874 | return ARM_FT_ISR; | |
875 | ||
876 | /* Get the value of the argument. */ | |
877 | if (TREE_VALUE (argument) == NULL_TREE | |
878 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
879 | return ARM_FT_UNKNOWN; | |
880 | ||
881 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
882 | ||
883 | /* Check it against the list of known arguments. */ | |
884 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++) | |
1d6e90ac NC |
885 | if (streq (arg, ptr->arg)) |
886 | return ptr->return_value; | |
6d3d9133 | 887 | |
05713b80 | 888 | /* An unrecognized interrupt type. */ |
6d3d9133 NC |
889 | return ARM_FT_UNKNOWN; |
890 | } | |
891 | ||
892 | /* Computes the type of the current function. */ | |
893 | ||
894 | static unsigned long | |
895 | arm_compute_func_type () | |
896 | { | |
897 | unsigned long type = ARM_FT_UNKNOWN; | |
898 | tree a; | |
899 | tree attr; | |
900 | ||
901 | if (TREE_CODE (current_function_decl) != FUNCTION_DECL) | |
902 | abort (); | |
903 | ||
904 | /* Decide if the current function is volatile. Such functions | |
905 | never return, and many memory cycles can be saved by not storing | |
906 | register values that will never be needed again. This optimization | |
907 | was added to speed up context switching in a kernel application. */ | |
908 | if (optimize > 0 | |
909 | && current_function_nothrow | |
910 | && TREE_THIS_VOLATILE (current_function_decl)) | |
911 | type |= ARM_FT_VOLATILE; | |
912 | ||
913 | if (current_function_needs_context) | |
914 | type |= ARM_FT_NESTED; | |
915 | ||
91d231cb | 916 | attr = DECL_ATTRIBUTES (current_function_decl); |
6d3d9133 NC |
917 | |
918 | a = lookup_attribute ("naked", attr); | |
919 | if (a != NULL_TREE) | |
920 | type |= ARM_FT_NAKED; | |
921 | ||
922 | if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX) | |
923 | type |= ARM_FT_EXCEPTION_HANDLER; | |
924 | else | |
925 | { | |
926 | a = lookup_attribute ("isr", attr); | |
927 | if (a == NULL_TREE) | |
928 | a = lookup_attribute ("interrupt", attr); | |
929 | ||
930 | if (a == NULL_TREE) | |
931 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
932 | else | |
933 | type |= arm_isr_value (TREE_VALUE (a)); | |
934 | } | |
935 | ||
936 | return type; | |
937 | } | |
938 | ||
939 | /* Returns the type of the current function. */ | |
940 | ||
941 | unsigned long | |
942 | arm_current_func_type () | |
943 | { | |
944 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
945 | cfun->machine->func_type = arm_compute_func_type (); | |
946 | ||
947 | return cfun->machine->func_type; | |
948 | } | |
949 | \f | |
6354dc9b | 950 | /* Return 1 if it is possible to return using a single instruction. */ |
6d3d9133 | 951 | |
ff9940b0 | 952 | int |
b36ba79f RE |
953 | use_return_insn (iscond) |
954 | int iscond; | |
ff9940b0 RE |
955 | { |
956 | int regno; | |
9b598fa0 | 957 | unsigned int func_type; |
d5db54a1 | 958 | unsigned long saved_int_regs; |
ff9940b0 | 959 | |
d5b7b3ae | 960 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
961 | if (!reload_completed) |
962 | return 0; | |
963 | ||
9b598fa0 RE |
964 | func_type = arm_current_func_type (); |
965 | ||
3a7731fd PB |
966 | /* Naked functions and volatile functions need special |
967 | consideration. */ | |
968 | if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED)) | |
6d3d9133 | 969 | return 0; |
06bea5aa NC |
970 | |
971 | /* So do interrupt functions that use the frame pointer. */ | |
972 | if (IS_INTERRUPT (func_type) && frame_pointer_needed) | |
973 | return 0; | |
6d3d9133 NC |
974 | |
975 | /* As do variadic functions. */ | |
976 | if (current_function_pretend_args_size | |
3cb66fd7 | 977 | || cfun->machine->uses_anonymous_args |
d5b7b3ae | 978 | /* Of if the function calls __builtin_eh_return () */ |
6d3d9133 | 979 | || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER |
d5b7b3ae | 980 | /* Or if there is no frame pointer and there is a stack adjustment. */ |
0977774b | 981 | || ((arm_get_frame_size () + current_function_outgoing_args_size != 0) |
5895f793 | 982 | && !frame_pointer_needed)) |
ff9940b0 RE |
983 | return 0; |
984 | ||
d5db54a1 RE |
985 | saved_int_regs = arm_compute_save_reg_mask (); |
986 | ||
b111229a | 987 | /* Can't be done if interworking with Thumb, and any registers have been |
d5db54a1 RE |
988 | stacked. */ |
989 | if (TARGET_INTERWORK && saved_int_regs != 0) | |
b36ba79f | 990 | return 0; |
d5db54a1 RE |
991 | |
992 | /* On StrongARM, conditional returns are expensive if they aren't | |
993 | taken and multiple registers have been stacked. */ | |
994 | if (iscond && arm_is_strong) | |
6ed30148 | 995 | { |
d5db54a1 RE |
996 | /* Conditional return when just the LR is stored is a simple |
997 | conditional-load instruction, that's not expensive. */ | |
998 | if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) | |
999 | return 0; | |
6ed30148 RE |
1000 | |
1001 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) | |
b111229a | 1002 | return 0; |
6ed30148 | 1003 | } |
d5db54a1 RE |
1004 | |
1005 | /* If there are saved registers but the LR isn't saved, then we need | |
1006 | two instructions for the return. */ | |
1007 | if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) | |
1008 | return 0; | |
1009 | ||
3b684012 | 1010 | /* Can't be done if any of the FPA regs are pushed, |
6d3d9133 | 1011 | since this also requires an insn. */ |
d5b7b3ae RE |
1012 | if (TARGET_HARD_FLOAT) |
1013 | for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++) | |
5895f793 | 1014 | if (regs_ever_live[regno] && !call_used_regs[regno]) |
d5b7b3ae | 1015 | return 0; |
ff9940b0 RE |
1016 | |
1017 | return 1; | |
1018 | } | |
1019 | ||
cce8749e CH |
1020 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
1021 | ||
1022 | int | |
1023 | const_ok_for_arm (i) | |
ff9940b0 | 1024 | HOST_WIDE_INT i; |
cce8749e | 1025 | { |
30cf4896 | 1026 | unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF; |
cce8749e | 1027 | |
56636818 JL |
1028 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
1029 | be all zero, or all one. */ | |
30cf4896 KG |
1030 | if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 |
1031 | && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) | |
1032 | != ((~(unsigned HOST_WIDE_INT) 0) | |
1033 | & ~(unsigned HOST_WIDE_INT) 0xffffffff))) | |
56636818 JL |
1034 | return FALSE; |
1035 | ||
e2c671ba RE |
1036 | /* Fast return for 0 and powers of 2 */ |
1037 | if ((i & (i - 1)) == 0) | |
1038 | return TRUE; | |
1039 | ||
cce8749e CH |
1040 | do |
1041 | { | |
30cf4896 | 1042 | if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0) |
f3bb6135 | 1043 | return TRUE; |
abaa26e5 | 1044 | mask = |
30cf4896 KG |
1045 | (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff) |
1046 | >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff; | |
ebe413e5 NC |
1047 | } |
1048 | while (mask != ~(unsigned HOST_WIDE_INT) 0xFF); | |
cce8749e | 1049 | |
f3bb6135 RE |
1050 | return FALSE; |
1051 | } | |
cce8749e | 1052 | |
6354dc9b | 1053 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 NC |
1054 | static int |
1055 | const_ok_for_op (i, code) | |
e2c671ba RE |
1056 | HOST_WIDE_INT i; |
1057 | enum rtx_code code; | |
e2c671ba RE |
1058 | { |
1059 | if (const_ok_for_arm (i)) | |
1060 | return 1; | |
1061 | ||
1062 | switch (code) | |
1063 | { | |
1064 | case PLUS: | |
1065 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); | |
1066 | ||
1067 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
1068 | case XOR: | |
1069 | case IOR: | |
1070 | return 0; | |
1071 | ||
1072 | case AND: | |
1073 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
1074 | ||
1075 | default: | |
1076 | abort (); | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | /* Emit a sequence of insns to handle a large constant. | |
1081 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
1082 | IOR, AND, XOR, MINUS; | |
1083 | MODE is the mode in which the operation is being performed; | |
1084 | VAL is the integer to operate on; | |
1085 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
1086 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
1087 | either produce a simpler sequence, or we will want to cse the values. |
1088 | Return value is the number of insns emitted. */ | |
e2c671ba RE |
1089 | |
1090 | int | |
1091 | arm_split_constant (code, mode, val, target, source, subtargets) | |
1092 | enum rtx_code code; | |
1093 | enum machine_mode mode; | |
1094 | HOST_WIDE_INT val; | |
1095 | rtx target; | |
1096 | rtx source; | |
1097 | int subtargets; | |
2b835d68 RE |
1098 | { |
1099 | if (subtargets || code == SET | |
1100 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
1101 | && REGNO (target) != REGNO (source))) | |
1102 | { | |
4b632bf1 | 1103 | /* After arm_reorg has been called, we can't fix up expensive |
05713b80 | 1104 | constants by pushing them into memory so we must synthesize |
4b632bf1 RE |
1105 | them in-line, regardless of the cost. This is only likely to |
1106 | be more costly on chips that have load delay slots and we are | |
1107 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
1108 | occurred before the final instruction emission). |
1109 | ||
1110 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 1111 | */ |
5895f793 | 1112 | if (!after_arm_reorg |
4b632bf1 RE |
1113 | && (arm_gen_constant (code, mode, val, target, source, 1, 0) |
1114 | > arm_constant_limit + (code != SET))) | |
2b835d68 RE |
1115 | { |
1116 | if (code == SET) | |
1117 | { | |
1118 | /* Currently SET is the only monadic value for CODE, all | |
1119 | the rest are diadic. */ | |
43cffd11 | 1120 | emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val))); |
2b835d68 RE |
1121 | return 1; |
1122 | } | |
1123 | else | |
1124 | { | |
1125 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
1126 | ||
43cffd11 | 1127 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val))); |
2b835d68 RE |
1128 | /* For MINUS, the value is subtracted from, since we never |
1129 | have subtraction of a constant. */ | |
1130 | if (code == MINUS) | |
43cffd11 | 1131 | emit_insn (gen_rtx_SET (VOIDmode, target, |
d5b7b3ae | 1132 | gen_rtx_MINUS (mode, temp, source))); |
2b835d68 | 1133 | else |
43cffd11 RE |
1134 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1135 | gen_rtx (code, mode, source, temp))); | |
2b835d68 RE |
1136 | return 2; |
1137 | } | |
1138 | } | |
1139 | } | |
1140 | ||
1141 | return arm_gen_constant (code, mode, val, target, source, subtargets, 1); | |
1142 | } | |
1143 | ||
ceebdb09 | 1144 | static int |
ab2877a3 KG |
1145 | count_insns_for_constant (remainder, i) |
1146 | HOST_WIDE_INT remainder; | |
1147 | int i; | |
ceebdb09 PB |
1148 | { |
1149 | HOST_WIDE_INT temp1; | |
1150 | int num_insns = 0; | |
1151 | do | |
1152 | { | |
1153 | int end; | |
1154 | ||
1155 | if (i <= 0) | |
1156 | i += 32; | |
1157 | if (remainder & (3 << (i - 2))) | |
1158 | { | |
1159 | end = i - 8; | |
1160 | if (end < 0) | |
1161 | end += 32; | |
1162 | temp1 = remainder & ((0x0ff << end) | |
1163 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
1164 | remainder &= ~temp1; | |
1165 | num_insns++; | |
1166 | i -= 6; | |
1167 | } | |
1168 | i -= 2; | |
1169 | } while (remainder); | |
1170 | return num_insns; | |
1171 | } | |
1172 | ||
2b835d68 RE |
1173 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
1174 | RTL generation. */ | |
1d6e90ac | 1175 | |
d5b7b3ae | 1176 | static int |
2b835d68 RE |
1177 | arm_gen_constant (code, mode, val, target, source, subtargets, generate) |
1178 | enum rtx_code code; | |
1179 | enum machine_mode mode; | |
1180 | HOST_WIDE_INT val; | |
1181 | rtx target; | |
1182 | rtx source; | |
1183 | int subtargets; | |
1184 | int generate; | |
e2c671ba | 1185 | { |
e2c671ba RE |
1186 | int can_invert = 0; |
1187 | int can_negate = 0; | |
1188 | int can_negate_initial = 0; | |
1189 | int can_shift = 0; | |
1190 | int i; | |
1191 | int num_bits_set = 0; | |
1192 | int set_sign_bit_copies = 0; | |
1193 | int clear_sign_bit_copies = 0; | |
1194 | int clear_zero_bit_copies = 0; | |
1195 | int set_zero_bit_copies = 0; | |
1196 | int insns = 0; | |
e2c671ba | 1197 | unsigned HOST_WIDE_INT temp1, temp2; |
30cf4896 | 1198 | unsigned HOST_WIDE_INT remainder = val & 0xffffffff; |
e2c671ba | 1199 | |
d5b7b3ae | 1200 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
1201 | check for degenerate cases; these can occur when DImode operations |
1202 | are split. */ | |
1203 | switch (code) | |
1204 | { | |
1205 | case SET: | |
1206 | can_invert = 1; | |
1207 | can_shift = 1; | |
1208 | can_negate = 1; | |
1209 | break; | |
1210 | ||
1211 | case PLUS: | |
1212 | can_negate = 1; | |
1213 | can_negate_initial = 1; | |
1214 | break; | |
1215 | ||
1216 | case IOR: | |
30cf4896 | 1217 | if (remainder == 0xffffffff) |
e2c671ba | 1218 | { |
2b835d68 | 1219 | if (generate) |
43cffd11 RE |
1220 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1221 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
1222 | return 1; |
1223 | } | |
1224 | if (remainder == 0) | |
1225 | { | |
1226 | if (reload_completed && rtx_equal_p (target, source)) | |
1227 | return 0; | |
2b835d68 | 1228 | if (generate) |
43cffd11 | 1229 | emit_insn (gen_rtx_SET (VOIDmode, target, source)); |
e2c671ba RE |
1230 | return 1; |
1231 | } | |
1232 | break; | |
1233 | ||
1234 | case AND: | |
1235 | if (remainder == 0) | |
1236 | { | |
2b835d68 | 1237 | if (generate) |
43cffd11 | 1238 | emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx)); |
e2c671ba RE |
1239 | return 1; |
1240 | } | |
30cf4896 | 1241 | if (remainder == 0xffffffff) |
e2c671ba RE |
1242 | { |
1243 | if (reload_completed && rtx_equal_p (target, source)) | |
1244 | return 0; | |
2b835d68 | 1245 | if (generate) |
43cffd11 | 1246 | emit_insn (gen_rtx_SET (VOIDmode, target, source)); |
e2c671ba RE |
1247 | return 1; |
1248 | } | |
1249 | can_invert = 1; | |
1250 | break; | |
1251 | ||
1252 | case XOR: | |
1253 | if (remainder == 0) | |
1254 | { | |
1255 | if (reload_completed && rtx_equal_p (target, source)) | |
1256 | return 0; | |
2b835d68 | 1257 | if (generate) |
43cffd11 | 1258 | emit_insn (gen_rtx_SET (VOIDmode, target, source)); |
e2c671ba RE |
1259 | return 1; |
1260 | } | |
30cf4896 | 1261 | if (remainder == 0xffffffff) |
e2c671ba | 1262 | { |
2b835d68 | 1263 | if (generate) |
43cffd11 RE |
1264 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1265 | gen_rtx_NOT (mode, source))); | |
e2c671ba RE |
1266 | return 1; |
1267 | } | |
1268 | ||
1269 | /* We don't know how to handle this yet below. */ | |
1270 | abort (); | |
1271 | ||
1272 | case MINUS: | |
1273 | /* We treat MINUS as (val - source), since (source - val) is always | |
1274 | passed as (source + (-val)). */ | |
1275 | if (remainder == 0) | |
1276 | { | |
2b835d68 | 1277 | if (generate) |
43cffd11 RE |
1278 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1279 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
1280 | return 1; |
1281 | } | |
1282 | if (const_ok_for_arm (val)) | |
1283 | { | |
2b835d68 | 1284 | if (generate) |
43cffd11 RE |
1285 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1286 | gen_rtx_MINUS (mode, GEN_INT (val), | |
1287 | source))); | |
e2c671ba RE |
1288 | return 1; |
1289 | } | |
1290 | can_negate = 1; | |
1291 | ||
1292 | break; | |
1293 | ||
1294 | default: | |
1295 | abort (); | |
1296 | } | |
1297 | ||
6354dc9b | 1298 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
1299 | if (const_ok_for_arm (val) |
1300 | || (can_negate_initial && const_ok_for_arm (-val)) | |
1301 | || (can_invert && const_ok_for_arm (~val))) | |
1302 | { | |
2b835d68 | 1303 | if (generate) |
43cffd11 RE |
1304 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1305 | (source ? gen_rtx (code, mode, source, | |
1306 | GEN_INT (val)) | |
1307 | : GEN_INT (val)))); | |
e2c671ba RE |
1308 | return 1; |
1309 | } | |
1310 | ||
e2c671ba | 1311 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 1312 | optimizations. */ |
e2c671ba RE |
1313 | for (i = 31; i >= 0; i--) |
1314 | { | |
1315 | if ((remainder & (1 << i)) == 0) | |
1316 | clear_sign_bit_copies++; | |
1317 | else | |
1318 | break; | |
1319 | } | |
1320 | ||
1321 | for (i = 31; i >= 0; i--) | |
1322 | { | |
1323 | if ((remainder & (1 << i)) != 0) | |
1324 | set_sign_bit_copies++; | |
1325 | else | |
1326 | break; | |
1327 | } | |
1328 | ||
1329 | for (i = 0; i <= 31; i++) | |
1330 | { | |
1331 | if ((remainder & (1 << i)) == 0) | |
1332 | clear_zero_bit_copies++; | |
1333 | else | |
1334 | break; | |
1335 | } | |
1336 | ||
1337 | for (i = 0; i <= 31; i++) | |
1338 | { | |
1339 | if ((remainder & (1 << i)) != 0) | |
1340 | set_zero_bit_copies++; | |
1341 | else | |
1342 | break; | |
1343 | } | |
1344 | ||
1345 | switch (code) | |
1346 | { | |
1347 | case SET: | |
1348 | /* See if we can do this by sign_extending a constant that is known | |
1349 | to be negative. This is a good, way of doing it, since the shift | |
1350 | may well merge into a subsequent insn. */ | |
1351 | if (set_sign_bit_copies > 1) | |
1352 | { | |
1353 | if (const_ok_for_arm | |
1354 | (temp1 = ARM_SIGN_EXTEND (remainder | |
1355 | << (set_sign_bit_copies - 1)))) | |
1356 | { | |
2b835d68 RE |
1357 | if (generate) |
1358 | { | |
d499463f | 1359 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
43cffd11 RE |
1360 | emit_insn (gen_rtx_SET (VOIDmode, new_src, |
1361 | GEN_INT (temp1))); | |
2b835d68 RE |
1362 | emit_insn (gen_ashrsi3 (target, new_src, |
1363 | GEN_INT (set_sign_bit_copies - 1))); | |
1364 | } | |
e2c671ba RE |
1365 | return 2; |
1366 | } | |
1367 | /* For an inverted constant, we will need to set the low bits, | |
1368 | these will be shifted out of harm's way. */ | |
1369 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
1370 | if (const_ok_for_arm (~temp1)) | |
1371 | { | |
2b835d68 RE |
1372 | if (generate) |
1373 | { | |
d499463f | 1374 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
43cffd11 RE |
1375 | emit_insn (gen_rtx_SET (VOIDmode, new_src, |
1376 | GEN_INT (temp1))); | |
2b835d68 RE |
1377 | emit_insn (gen_ashrsi3 (target, new_src, |
1378 | GEN_INT (set_sign_bit_copies - 1))); | |
1379 | } | |
e2c671ba RE |
1380 | return 2; |
1381 | } | |
1382 | } | |
1383 | ||
1384 | /* See if we can generate this by setting the bottom (or the top) | |
1385 | 16 bits, and then shifting these into the other half of the | |
1386 | word. We only look for the simplest cases, to do more would cost | |
1387 | too much. Be careful, however, not to generate this when the | |
1388 | alternative would take fewer insns. */ | |
30cf4896 | 1389 | if (val & 0xffff0000) |
e2c671ba | 1390 | { |
30cf4896 | 1391 | temp1 = remainder & 0xffff0000; |
e2c671ba RE |
1392 | temp2 = remainder & 0x0000ffff; |
1393 | ||
6354dc9b | 1394 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
1395 | for (i = 9; i < 24; i++) |
1396 | { | |
30cf4896 | 1397 | if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) |
5895f793 | 1398 | && !const_ok_for_arm (temp2)) |
e2c671ba | 1399 | { |
d499463f RE |
1400 | rtx new_src = (subtargets |
1401 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
1402 | : target); | |
1403 | insns = arm_gen_constant (code, mode, temp2, new_src, | |
2b835d68 | 1404 | source, subtargets, generate); |
e2c671ba | 1405 | source = new_src; |
2b835d68 | 1406 | if (generate) |
43cffd11 RE |
1407 | emit_insn (gen_rtx_SET |
1408 | (VOIDmode, target, | |
1409 | gen_rtx_IOR (mode, | |
1410 | gen_rtx_ASHIFT (mode, source, | |
1411 | GEN_INT (i)), | |
1412 | source))); | |
e2c671ba RE |
1413 | return insns + 1; |
1414 | } | |
1415 | } | |
1416 | ||
6354dc9b | 1417 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
1418 | for (i = 17; i < 24; i++) |
1419 | { | |
1420 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 1421 | && !const_ok_for_arm (temp1)) |
e2c671ba | 1422 | { |
d499463f RE |
1423 | rtx new_src = (subtargets |
1424 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
1425 | : target); | |
1426 | insns = arm_gen_constant (code, mode, temp1, new_src, | |
2b835d68 | 1427 | source, subtargets, generate); |
e2c671ba | 1428 | source = new_src; |
2b835d68 | 1429 | if (generate) |
43cffd11 RE |
1430 | emit_insn |
1431 | (gen_rtx_SET (VOIDmode, target, | |
1432 | gen_rtx_IOR | |
1433 | (mode, | |
1434 | gen_rtx_LSHIFTRT (mode, source, | |
1435 | GEN_INT (i)), | |
1436 | source))); | |
e2c671ba RE |
1437 | return insns + 1; |
1438 | } | |
1439 | } | |
1440 | } | |
1441 | break; | |
1442 | ||
1443 | case IOR: | |
1444 | case XOR: | |
7b64da89 RE |
1445 | /* If we have IOR or XOR, and the constant can be loaded in a |
1446 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
1447 | then this can be done in two instructions instead of 3-4. */ |
1448 | if (subtargets | |
d499463f | 1449 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 1450 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 1451 | { |
5895f793 | 1452 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 1453 | { |
2b835d68 RE |
1454 | if (generate) |
1455 | { | |
1456 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 1457 | |
43cffd11 RE |
1458 | emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val))); |
1459 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
1460 | gen_rtx (code, mode, source, sub))); | |
2b835d68 | 1461 | } |
e2c671ba RE |
1462 | return 2; |
1463 | } | |
1464 | } | |
1465 | ||
1466 | if (code == XOR) | |
1467 | break; | |
1468 | ||
1469 | if (set_sign_bit_copies > 8 | |
1470 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
1471 | { | |
2b835d68 RE |
1472 | if (generate) |
1473 | { | |
1474 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
1475 | rtx shift = GEN_INT (set_sign_bit_copies); | |
1476 | ||
43cffd11 RE |
1477 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1478 | gen_rtx_NOT (mode, | |
1479 | gen_rtx_ASHIFT (mode, | |
1480 | source, | |
f5a1b0d2 | 1481 | shift)))); |
43cffd11 RE |
1482 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1483 | gen_rtx_NOT (mode, | |
1484 | gen_rtx_LSHIFTRT (mode, sub, | |
1485 | shift)))); | |
2b835d68 | 1486 | } |
e2c671ba RE |
1487 | return 2; |
1488 | } | |
1489 | ||
1490 | if (set_zero_bit_copies > 8 | |
1491 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
1492 | { | |
2b835d68 RE |
1493 | if (generate) |
1494 | { | |
1495 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
1496 | rtx shift = GEN_INT (set_zero_bit_copies); | |
1497 | ||
43cffd11 RE |
1498 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1499 | gen_rtx_NOT (mode, | |
1500 | gen_rtx_LSHIFTRT (mode, | |
1501 | source, | |
f5a1b0d2 | 1502 | shift)))); |
43cffd11 RE |
1503 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1504 | gen_rtx_NOT (mode, | |
1505 | gen_rtx_ASHIFT (mode, sub, | |
f5a1b0d2 | 1506 | shift)))); |
2b835d68 | 1507 | } |
e2c671ba RE |
1508 | return 2; |
1509 | } | |
1510 | ||
5895f793 | 1511 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 1512 | { |
2b835d68 RE |
1513 | if (generate) |
1514 | { | |
1515 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
43cffd11 RE |
1516 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1517 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
1518 | source = sub; |
1519 | if (subtargets) | |
1520 | sub = gen_reg_rtx (mode); | |
43cffd11 RE |
1521 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1522 | gen_rtx_AND (mode, source, | |
1523 | GEN_INT (temp1)))); | |
1524 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
1525 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 1526 | } |
e2c671ba RE |
1527 | return 3; |
1528 | } | |
1529 | break; | |
1530 | ||
1531 | case AND: | |
1532 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
1533 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
1534 | { | |
30cf4896 | 1535 | HOST_WIDE_INT shift_mask = ((0xffffffff |
e2c671ba | 1536 | << (32 - clear_sign_bit_copies)) |
30cf4896 | 1537 | & 0xffffffff); |
e2c671ba | 1538 | |
30cf4896 | 1539 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 1540 | { |
2b835d68 RE |
1541 | if (generate) |
1542 | { | |
d499463f | 1543 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2b835d68 | 1544 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, |
d499463f RE |
1545 | new_src, source, subtargets, 1); |
1546 | source = new_src; | |
2b835d68 RE |
1547 | } |
1548 | else | |
d499463f RE |
1549 | { |
1550 | rtx targ = subtargets ? NULL_RTX : target; | |
1551 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, | |
1552 | targ, source, subtargets, 0); | |
1553 | } | |
2b835d68 RE |
1554 | } |
1555 | ||
1556 | if (generate) | |
1557 | { | |
d499463f RE |
1558 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1559 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
1560 | ||
1561 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
1562 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
1563 | } |
1564 | ||
e2c671ba RE |
1565 | return insns + 2; |
1566 | } | |
1567 | ||
1568 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
1569 | { | |
1570 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
e2c671ba | 1571 | |
30cf4896 | 1572 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 1573 | { |
2b835d68 RE |
1574 | if (generate) |
1575 | { | |
d499463f RE |
1576 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1577 | ||
2b835d68 | 1578 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, |
d499463f RE |
1579 | new_src, source, subtargets, 1); |
1580 | source = new_src; | |
2b835d68 RE |
1581 | } |
1582 | else | |
d499463f RE |
1583 | { |
1584 | rtx targ = subtargets ? NULL_RTX : target; | |
1585 | ||
1586 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, | |
1587 | targ, source, subtargets, 0); | |
1588 | } | |
2b835d68 RE |
1589 | } |
1590 | ||
1591 | if (generate) | |
1592 | { | |
d499463f RE |
1593 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1594 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
1595 | ||
1596 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
1597 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
1598 | } |
1599 | ||
e2c671ba RE |
1600 | return insns + 2; |
1601 | } | |
1602 | ||
1603 | break; | |
1604 | ||
1605 | default: | |
1606 | break; | |
1607 | } | |
1608 | ||
1609 | for (i = 0; i < 32; i++) | |
1610 | if (remainder & (1 << i)) | |
1611 | num_bits_set++; | |
1612 | ||
1613 | if (code == AND || (can_invert && num_bits_set > 16)) | |
30cf4896 | 1614 | remainder = (~remainder) & 0xffffffff; |
e2c671ba | 1615 | else if (code == PLUS && num_bits_set > 16) |
30cf4896 | 1616 | remainder = (-remainder) & 0xffffffff; |
e2c671ba RE |
1617 | else |
1618 | { | |
1619 | can_invert = 0; | |
1620 | can_negate = 0; | |
1621 | } | |
1622 | ||
1623 | /* Now try and find a way of doing the job in either two or three | |
1624 | instructions. | |
1625 | We start by looking for the largest block of zeros that are aligned on | |
1626 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
1627 | top of the word when we drop off the bottom. | |
6354dc9b | 1628 | In the worst case this code should produce no more than four insns. */ |
e2c671ba RE |
1629 | { |
1630 | int best_start = 0; | |
1631 | int best_consecutive_zeros = 0; | |
1632 | ||
1633 | for (i = 0; i < 32; i += 2) | |
1634 | { | |
1635 | int consecutive_zeros = 0; | |
1636 | ||
5895f793 | 1637 | if (!(remainder & (3 << i))) |
e2c671ba | 1638 | { |
5895f793 | 1639 | while ((i < 32) && !(remainder & (3 << i))) |
e2c671ba RE |
1640 | { |
1641 | consecutive_zeros += 2; | |
1642 | i += 2; | |
1643 | } | |
1644 | if (consecutive_zeros > best_consecutive_zeros) | |
1645 | { | |
1646 | best_consecutive_zeros = consecutive_zeros; | |
1647 | best_start = i - consecutive_zeros; | |
1648 | } | |
1649 | i -= 2; | |
1650 | } | |
1651 | } | |
1652 | ||
ceebdb09 PB |
1653 | /* So long as it won't require any more insns to do so, it's |
1654 | desirable to emit a small constant (in bits 0...9) in the last | |
1655 | insn. This way there is more chance that it can be combined with | |
1656 | a later addressing insn to form a pre-indexed load or store | |
1657 | operation. Consider: | |
1658 | ||
1659 | *((volatile int *)0xe0000100) = 1; | |
1660 | *((volatile int *)0xe0000110) = 2; | |
1661 | ||
1662 | We want this to wind up as: | |
1663 | ||
1664 | mov rA, #0xe0000000 | |
1665 | mov rB, #1 | |
1666 | str rB, [rA, #0x100] | |
1667 | mov rB, #2 | |
1668 | str rB, [rA, #0x110] | |
1669 | ||
1670 | rather than having to synthesize both large constants from scratch. | |
1671 | ||
1672 | Therefore, we calculate how many insns would be required to emit | |
1673 | the constant starting from `best_start', and also starting from | |
1674 | zero (ie with bit 31 first to be output). If `best_start' doesn't | |
1675 | yield a shorter sequence, we may as well use zero. */ | |
1676 | if (best_start != 0 | |
1677 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
1678 | && (count_insns_for_constant (remainder, 0) <= | |
1679 | count_insns_for_constant (remainder, best_start))) | |
1680 | best_start = 0; | |
1681 | ||
1682 | /* Now start emitting the insns. */ | |
e2c671ba RE |
1683 | i = best_start; |
1684 | do | |
1685 | { | |
1686 | int end; | |
1687 | ||
1688 | if (i <= 0) | |
1689 | i += 32; | |
1690 | if (remainder & (3 << (i - 2))) | |
1691 | { | |
1692 | end = i - 8; | |
1693 | if (end < 0) | |
1694 | end += 32; | |
1695 | temp1 = remainder & ((0x0ff << end) | |
1696 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
1697 | remainder &= ~temp1; | |
1698 | ||
d499463f | 1699 | if (generate) |
e2c671ba | 1700 | { |
9503f3d1 RH |
1701 | rtx new_src, temp1_rtx; |
1702 | ||
1703 | if (code == SET || code == MINUS) | |
1704 | { | |
1705 | new_src = (subtargets ? gen_reg_rtx (mode) : target); | |
96ae8197 | 1706 | if (can_invert && code != MINUS) |
9503f3d1 RH |
1707 | temp1 = ~temp1; |
1708 | } | |
1709 | else | |
1710 | { | |
96ae8197 | 1711 | if (remainder && subtargets) |
9503f3d1 | 1712 | new_src = gen_reg_rtx (mode); |
96ae8197 NC |
1713 | else |
1714 | new_src = target; | |
9503f3d1 RH |
1715 | if (can_invert) |
1716 | temp1 = ~temp1; | |
1717 | else if (can_negate) | |
1718 | temp1 = -temp1; | |
1719 | } | |
1720 | ||
1721 | temp1 = trunc_int_for_mode (temp1, mode); | |
1722 | temp1_rtx = GEN_INT (temp1); | |
d499463f RE |
1723 | |
1724 | if (code == SET) | |
9503f3d1 | 1725 | ; |
d499463f | 1726 | else if (code == MINUS) |
9503f3d1 | 1727 | temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); |
d499463f | 1728 | else |
9503f3d1 RH |
1729 | temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); |
1730 | ||
1731 | emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx)); | |
d499463f | 1732 | source = new_src; |
e2c671ba RE |
1733 | } |
1734 | ||
d499463f RE |
1735 | if (code == SET) |
1736 | { | |
1737 | can_invert = 0; | |
1738 | code = PLUS; | |
1739 | } | |
1740 | else if (code == MINUS) | |
1741 | code = PLUS; | |
1742 | ||
e2c671ba | 1743 | insns++; |
e2c671ba RE |
1744 | i -= 6; |
1745 | } | |
1746 | i -= 2; | |
1d6e90ac NC |
1747 | } |
1748 | while (remainder); | |
e2c671ba | 1749 | } |
1d6e90ac | 1750 | |
e2c671ba RE |
1751 | return insns; |
1752 | } | |
1753 | ||
bd9c7e23 RE |
1754 | /* Canonicalize a comparison so that we are more likely to recognize it. |
1755 | This can be done for a few constant compares, where we can make the | |
1756 | immediate value easier to load. */ | |
1d6e90ac | 1757 | |
bd9c7e23 RE |
1758 | enum rtx_code |
1759 | arm_canonicalize_comparison (code, op1) | |
1760 | enum rtx_code code; | |
62b10bbc | 1761 | rtx * op1; |
bd9c7e23 | 1762 | { |
ad076f4e | 1763 | unsigned HOST_WIDE_INT i = INTVAL (*op1); |
bd9c7e23 RE |
1764 | |
1765 | switch (code) | |
1766 | { | |
1767 | case EQ: | |
1768 | case NE: | |
1769 | return code; | |
1770 | ||
1771 | case GT: | |
1772 | case LE: | |
30cf4896 | 1773 | if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1) |
5895f793 | 1774 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 | 1775 | { |
5895f793 | 1776 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
1777 | return code == GT ? GE : LT; |
1778 | } | |
1779 | break; | |
1780 | ||
1781 | case GE: | |
1782 | case LT: | |
30cf4896 | 1783 | if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) |
5895f793 | 1784 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 1785 | { |
5895f793 | 1786 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
1787 | return code == GE ? GT : LE; |
1788 | } | |
1789 | break; | |
1790 | ||
1791 | case GTU: | |
1792 | case LEU: | |
30cf4896 | 1793 | if (i != ~((unsigned HOST_WIDE_INT) 0) |
5895f793 | 1794 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 RE |
1795 | { |
1796 | *op1 = GEN_INT (i + 1); | |
1797 | return code == GTU ? GEU : LTU; | |
1798 | } | |
1799 | break; | |
1800 | ||
1801 | case GEU: | |
1802 | case LTU: | |
1803 | if (i != 0 | |
5895f793 | 1804 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
1805 | { |
1806 | *op1 = GEN_INT (i - 1); | |
1807 | return code == GEU ? GTU : LEU; | |
1808 | } | |
1809 | break; | |
1810 | ||
1811 | default: | |
1812 | abort (); | |
1813 | } | |
1814 | ||
1815 | return code; | |
1816 | } | |
bd9c7e23 | 1817 | |
f5a1b0d2 NC |
1818 | /* Decide whether a type should be returned in memory (true) |
1819 | or in a register (false). This is called by the macro | |
1820 | RETURN_IN_MEMORY. */ | |
1d6e90ac | 1821 | |
2b835d68 RE |
1822 | int |
1823 | arm_return_in_memory (type) | |
1824 | tree type; | |
1825 | { | |
dc0ba55a JT |
1826 | HOST_WIDE_INT size; |
1827 | ||
5895f793 | 1828 | if (!AGGREGATE_TYPE_P (type)) |
9e291dbe | 1829 | /* All simple types are returned in registers. */ |
d7d01975 | 1830 | return 0; |
dc0ba55a JT |
1831 | |
1832 | size = int_size_in_bytes (type); | |
1833 | ||
1834 | if (TARGET_ATPCS) | |
1835 | { | |
1836 | /* ATPCS returns aggregate types in memory only if they are | |
1837 | larger than a word (or are variable size). */ | |
1838 | return (size < 0 || size > UNITS_PER_WORD); | |
1839 | } | |
d5b7b3ae | 1840 | |
6bc82793 | 1841 | /* For the arm-wince targets we choose to be compatible with Microsoft's |
d5b7b3ae RE |
1842 | ARM and Thumb compilers, which always return aggregates in memory. */ |
1843 | #ifndef ARM_WINCE | |
e529bd42 NC |
1844 | /* All structures/unions bigger than one word are returned in memory. |
1845 | Also catch the case where int_size_in_bytes returns -1. In this case | |
6bc82793 | 1846 | the aggregate is either huge or of variable size, and in either case |
e529bd42 | 1847 | we will want to return it via memory and not in a register. */ |
dc0ba55a | 1848 | if (size < 0 || size > UNITS_PER_WORD) |
d7d01975 | 1849 | return 1; |
d5b7b3ae | 1850 | |
d7d01975 | 1851 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
1852 | { |
1853 | tree field; | |
1854 | ||
3a2ea258 RE |
1855 | /* For a struct the APCS says that we only return in a register |
1856 | if the type is 'integer like' and every addressable element | |
1857 | has an offset of zero. For practical purposes this means | |
1858 | that the structure can have at most one non bit-field element | |
1859 | and that this element must be the first one in the structure. */ | |
1860 | ||
f5a1b0d2 NC |
1861 | /* Find the first field, ignoring non FIELD_DECL things which will |
1862 | have been created by C++. */ | |
1863 | for (field = TYPE_FIELDS (type); | |
1864 | field && TREE_CODE (field) != FIELD_DECL; | |
1865 | field = TREE_CHAIN (field)) | |
1866 | continue; | |
1867 | ||
1868 | if (field == NULL) | |
9e291dbe | 1869 | return 0; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 1870 | |
d5b7b3ae RE |
1871 | /* Check that the first field is valid for returning in a register. */ |
1872 | ||
1873 | /* ... Floats are not allowed */ | |
9e291dbe | 1874 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3a2ea258 RE |
1875 | return 1; |
1876 | ||
d5b7b3ae RE |
1877 | /* ... Aggregates that are not themselves valid for returning in |
1878 | a register are not allowed. */ | |
9e291dbe | 1879 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
3a2ea258 | 1880 | return 1; |
6f7ebcbb | 1881 | |
3a2ea258 RE |
1882 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
1883 | since they are not addressable. */ | |
f5a1b0d2 NC |
1884 | for (field = TREE_CHAIN (field); |
1885 | field; | |
1886 | field = TREE_CHAIN (field)) | |
1887 | { | |
1888 | if (TREE_CODE (field) != FIELD_DECL) | |
1889 | continue; | |
1890 | ||
5895f793 | 1891 | if (!DECL_BIT_FIELD_TYPE (field)) |
f5a1b0d2 NC |
1892 | return 1; |
1893 | } | |
2b835d68 RE |
1894 | |
1895 | return 0; | |
1896 | } | |
d7d01975 NC |
1897 | |
1898 | if (TREE_CODE (type) == UNION_TYPE) | |
2b835d68 RE |
1899 | { |
1900 | tree field; | |
1901 | ||
1902 | /* Unions can be returned in registers if every element is | |
1903 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
1904 | for (field = TYPE_FIELDS (type); |
1905 | field; | |
1906 | field = TREE_CHAIN (field)) | |
2b835d68 | 1907 | { |
f5a1b0d2 NC |
1908 | if (TREE_CODE (field) != FIELD_DECL) |
1909 | continue; | |
1910 | ||
6cc8c0b3 NC |
1911 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
1912 | return 1; | |
1913 | ||
f5a1b0d2 | 1914 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
2b835d68 RE |
1915 | return 1; |
1916 | } | |
f5a1b0d2 | 1917 | |
2b835d68 RE |
1918 | return 0; |
1919 | } | |
d5b7b3ae | 1920 | #endif /* not ARM_WINCE */ |
f5a1b0d2 | 1921 | |
d5b7b3ae | 1922 | /* Return all other types in memory. */ |
2b835d68 RE |
1923 | return 1; |
1924 | } | |
1925 | ||
3717da94 JT |
1926 | /* Indicate whether or not words of a double are in big-endian order. */ |
1927 | ||
1928 | int | |
1929 | arm_float_words_big_endian () | |
1930 | { | |
9b6b54e2 NC |
1931 | if (TARGET_CIRRUS) |
1932 | return 0; | |
3717da94 JT |
1933 | |
1934 | /* For FPA, float words are always big-endian. For VFP, floats words | |
1935 | follow the memory system mode. */ | |
1936 | ||
1937 | if (TARGET_HARD_FLOAT) | |
1938 | { | |
1939 | /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */ | |
1940 | return 1; | |
1941 | } | |
1942 | ||
1943 | if (TARGET_VFP) | |
1944 | return (TARGET_BIG_END ? 1 : 0); | |
1945 | ||
1946 | return 1; | |
1947 | } | |
1948 | ||
82e9d970 PB |
1949 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1950 | for a call to a function whose data type is FNTYPE. | |
1951 | For a library call, FNTYPE is NULL. */ | |
1952 | void | |
563a317a | 1953 | arm_init_cumulative_args (pcum, fntype, libname, fndecl) |
82e9d970 PB |
1954 | CUMULATIVE_ARGS * pcum; |
1955 | tree fntype; | |
1956 | rtx libname ATTRIBUTE_UNUSED; | |
563a317a | 1957 | tree fndecl ATTRIBUTE_UNUSED; |
82e9d970 PB |
1958 | { |
1959 | /* On the ARM, the offset starts at 0. */ | |
c27ba912 DM |
1960 | pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0); |
1961 | ||
82e9d970 PB |
1962 | pcum->call_cookie = CALL_NORMAL; |
1963 | ||
1964 | if (TARGET_LONG_CALLS) | |
1965 | pcum->call_cookie = CALL_LONG; | |
1966 | ||
1967 | /* Check for long call/short call attributes. The attributes | |
1968 | override any command line option. */ | |
1969 | if (fntype) | |
1970 | { | |
1971 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype))) | |
1972 | pcum->call_cookie = CALL_SHORT; | |
1973 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype))) | |
1974 | pcum->call_cookie = CALL_LONG; | |
1975 | } | |
1976 | } | |
1977 | ||
1978 | /* Determine where to put an argument to a function. | |
1979 | Value is zero to push the argument on the stack, | |
1980 | or a hard register in which to store the argument. | |
1981 | ||
1982 | MODE is the argument's machine mode. | |
1983 | TYPE is the data type of the argument (as a tree). | |
1984 | This is null for libcalls where that information may | |
1985 | not be available. | |
1986 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1987 | the preceding args and about the function being called. | |
1988 | NAMED is nonzero if this argument is a named parameter | |
1989 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1d6e90ac | 1990 | |
82e9d970 PB |
1991 | rtx |
1992 | arm_function_arg (pcum, mode, type, named) | |
1993 | CUMULATIVE_ARGS * pcum; | |
1994 | enum machine_mode mode; | |
1995 | tree type ATTRIBUTE_UNUSED; | |
1996 | int named; | |
1997 | { | |
1998 | if (mode == VOIDmode) | |
1999 | /* Compute operand 2 of the call insn. */ | |
2000 | return GEN_INT (pcum->call_cookie); | |
2001 | ||
5895f793 | 2002 | if (!named || pcum->nregs >= NUM_ARG_REGS) |
82e9d970 PB |
2003 | return NULL_RTX; |
2004 | ||
2005 | return gen_rtx_REG (mode, pcum->nregs); | |
2006 | } | |
1741620c JD |
2007 | |
2008 | /* Variable sized types are passed by reference. This is a GCC | |
2009 | extension to the ARM ABI. */ | |
2010 | ||
2011 | int | |
2012 | arm_function_arg_pass_by_reference (cum, mode, type, named) | |
2013 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; | |
2014 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
2015 | tree type; | |
2016 | int named ATTRIBUTE_UNUSED; | |
2017 | { | |
2018 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
2019 | } | |
2020 | ||
2021 | /* Implement va_arg. */ | |
2022 | ||
2023 | rtx | |
2024 | arm_va_arg (valist, type) | |
2025 | tree valist, type; | |
2026 | { | |
2027 | /* Variable sized types are passed by reference. */ | |
2028 | if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) | |
2029 | { | |
2030 | rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type)); | |
2031 | return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr)); | |
2032 | } | |
2033 | ||
2034 | return std_expand_builtin_va_arg (valist, type); | |
2035 | } | |
82e9d970 | 2036 | \f |
c27ba912 DM |
2037 | /* Encode the current state of the #pragma [no_]long_calls. */ |
2038 | typedef enum | |
82e9d970 | 2039 | { |
c27ba912 DM |
2040 | OFF, /* No #pramgma [no_]long_calls is in effect. */ |
2041 | LONG, /* #pragma long_calls is in effect. */ | |
2042 | SHORT /* #pragma no_long_calls is in effect. */ | |
2043 | } arm_pragma_enum; | |
82e9d970 | 2044 | |
c27ba912 | 2045 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 2046 | |
8b97c5f8 ZW |
2047 | void |
2048 | arm_pr_long_calls (pfile) | |
231b51a1 | 2049 | struct cpp_reader * pfile ATTRIBUTE_UNUSED; |
82e9d970 | 2050 | { |
8b97c5f8 ZW |
2051 | arm_pragma_long_calls = LONG; |
2052 | } | |
2053 | ||
2054 | void | |
2055 | arm_pr_no_long_calls (pfile) | |
231b51a1 | 2056 | struct cpp_reader * pfile ATTRIBUTE_UNUSED; |
8b97c5f8 ZW |
2057 | { |
2058 | arm_pragma_long_calls = SHORT; | |
2059 | } | |
2060 | ||
2061 | void | |
2062 | arm_pr_long_calls_off (pfile) | |
231b51a1 | 2063 | struct cpp_reader * pfile ATTRIBUTE_UNUSED; |
8b97c5f8 ZW |
2064 | { |
2065 | arm_pragma_long_calls = OFF; | |
82e9d970 PB |
2066 | } |
2067 | \f | |
91d231cb JM |
2068 | /* Table of machine attributes. */ |
2069 | const struct attribute_spec arm_attribute_table[] = | |
82e9d970 | 2070 | { |
91d231cb | 2071 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
82e9d970 PB |
2072 | /* Function calls made to this symbol must be done indirectly, because |
2073 | it may lie outside of the 26 bit addressing range of a normal function | |
2074 | call. */ | |
91d231cb | 2075 | { "long_call", 0, 0, false, true, true, NULL }, |
82e9d970 PB |
2076 | /* Whereas these functions are always known to reside within the 26 bit |
2077 | addressing range. */ | |
91d231cb | 2078 | { "short_call", 0, 0, false, true, true, NULL }, |
6d3d9133 | 2079 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
91d231cb JM |
2080 | { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, |
2081 | { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, | |
2082 | { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
2083 | #ifdef ARM_PE | |
2084 | /* ARM/PE has three new attributes: | |
2085 | interfacearm - ? | |
2086 | dllexport - for exporting a function/variable that will live in a dll | |
2087 | dllimport - for importing a function/variable from a dll | |
2088 | ||
2089 | Microsoft allows multiple declspecs in one __declspec, separating | |
2090 | them with spaces. We do NOT support this. Instead, use __declspec | |
2091 | multiple times. | |
2092 | */ | |
2093 | { "dllimport", 0, 0, true, false, false, NULL }, | |
2094 | { "dllexport", 0, 0, true, false, false, NULL }, | |
2095 | { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
2096 | #endif | |
2097 | { NULL, 0, 0, false, false, false, NULL } | |
2098 | }; | |
6d3d9133 | 2099 | |
91d231cb JM |
2100 | /* Handle an attribute requiring a FUNCTION_DECL; |
2101 | arguments as in struct attribute_spec.handler. */ | |
1d6e90ac | 2102 | |
91d231cb JM |
2103 | static tree |
2104 | arm_handle_fndecl_attribute (node, name, args, flags, no_add_attrs) | |
1d6e90ac NC |
2105 | tree * node; |
2106 | tree name; | |
2107 | tree args ATTRIBUTE_UNUSED; | |
2108 | int flags ATTRIBUTE_UNUSED; | |
2109 | bool * no_add_attrs; | |
91d231cb JM |
2110 | { |
2111 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
2112 | { | |
2113 | warning ("`%s' attribute only applies to functions", | |
2114 | IDENTIFIER_POINTER (name)); | |
2115 | *no_add_attrs = true; | |
2116 | } | |
2117 | ||
2118 | return NULL_TREE; | |
2119 | } | |
2120 | ||
2121 | /* Handle an "interrupt" or "isr" attribute; | |
2122 | arguments as in struct attribute_spec.handler. */ | |
1d6e90ac | 2123 | |
91d231cb JM |
2124 | static tree |
2125 | arm_handle_isr_attribute (node, name, args, flags, no_add_attrs) | |
1d6e90ac NC |
2126 | tree * node; |
2127 | tree name; | |
2128 | tree args; | |
2129 | int flags; | |
2130 | bool * no_add_attrs; | |
91d231cb JM |
2131 | { |
2132 | if (DECL_P (*node)) | |
2133 | { | |
2134 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
2135 | { | |
2136 | warning ("`%s' attribute only applies to functions", | |
2137 | IDENTIFIER_POINTER (name)); | |
2138 | *no_add_attrs = true; | |
2139 | } | |
2140 | /* FIXME: the argument if any is checked for type attributes; | |
2141 | should it be checked for decl ones? */ | |
2142 | } | |
2143 | else | |
2144 | { | |
2145 | if (TREE_CODE (*node) == FUNCTION_TYPE | |
2146 | || TREE_CODE (*node) == METHOD_TYPE) | |
2147 | { | |
2148 | if (arm_isr_value (args) == ARM_FT_UNKNOWN) | |
2149 | { | |
2150 | warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); | |
2151 | *no_add_attrs = true; | |
2152 | } | |
2153 | } | |
2154 | else if (TREE_CODE (*node) == POINTER_TYPE | |
2155 | && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE | |
2156 | || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) | |
2157 | && arm_isr_value (args) != ARM_FT_UNKNOWN) | |
2158 | { | |
2159 | *node = build_type_copy (*node); | |
1d6e90ac NC |
2160 | TREE_TYPE (*node) = build_type_attribute_variant |
2161 | (TREE_TYPE (*node), | |
2162 | tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); | |
91d231cb JM |
2163 | *no_add_attrs = true; |
2164 | } | |
2165 | else | |
2166 | { | |
2167 | /* Possibly pass this attribute on from the type to a decl. */ | |
2168 | if (flags & ((int) ATTR_FLAG_DECL_NEXT | |
2169 | | (int) ATTR_FLAG_FUNCTION_NEXT | |
2170 | | (int) ATTR_FLAG_ARRAY_NEXT)) | |
2171 | { | |
2172 | *no_add_attrs = true; | |
2173 | return tree_cons (name, args, NULL_TREE); | |
2174 | } | |
2175 | else | |
2176 | { | |
2177 | warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); | |
2178 | } | |
2179 | } | |
2180 | } | |
2181 | ||
2182 | return NULL_TREE; | |
82e9d970 PB |
2183 | } |
2184 | ||
2185 | /* Return 0 if the attributes for two types are incompatible, 1 if they | |
2186 | are compatible, and 2 if they are nearly compatible (which causes a | |
2187 | warning to be generated). */ | |
1d6e90ac | 2188 | |
8d8e52be | 2189 | static int |
82e9d970 PB |
2190 | arm_comp_type_attributes (type1, type2) |
2191 | tree type1; | |
2192 | tree type2; | |
2193 | { | |
1cb8d58a | 2194 | int l1, l2, s1, s2; |
bd7fc26f | 2195 | |
82e9d970 PB |
2196 | /* Check for mismatch of non-default calling convention. */ |
2197 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
2198 | return 1; | |
2199 | ||
2200 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
2201 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
2202 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
2203 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
2204 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
2205 | |
2206 | /* Only bother to check if an attribute is defined. */ | |
2207 | if (l1 | l2 | s1 | s2) | |
2208 | { | |
2209 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 2210 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 2211 | return 0; |
82e9d970 | 2212 | |
bd7fc26f NC |
2213 | /* Disallow mixed attributes. */ |
2214 | if ((l1 & s2) || (l2 & s1)) | |
2215 | return 0; | |
2216 | } | |
2217 | ||
6d3d9133 NC |
2218 | /* Check for mismatched ISR attribute. */ |
2219 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
2220 | if (! l1) | |
2221 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
2222 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
2223 | if (! l2) | |
2224 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
2225 | if (l1 != l2) | |
2226 | return 0; | |
2227 | ||
bd7fc26f | 2228 | return 1; |
82e9d970 PB |
2229 | } |
2230 | ||
c27ba912 DM |
2231 | /* Encode long_call or short_call attribute by prefixing |
2232 | symbol name in DECL with a special character FLAG. */ | |
1d6e90ac | 2233 | |
c27ba912 DM |
2234 | void |
2235 | arm_encode_call_attribute (decl, flag) | |
2236 | tree decl; | |
cd2b33d0 | 2237 | int flag; |
c27ba912 | 2238 | { |
3cce094d | 2239 | const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0); |
6354dc9b | 2240 | int len = strlen (str); |
d19fb8e3 | 2241 | char * newstr; |
c27ba912 | 2242 | |
c27ba912 DM |
2243 | /* Do not allow weak functions to be treated as short call. */ |
2244 | if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR) | |
2245 | return; | |
c27ba912 | 2246 | |
520a57c8 ZW |
2247 | newstr = alloca (len + 2); |
2248 | newstr[0] = flag; | |
2249 | strcpy (newstr + 1, str); | |
c27ba912 | 2250 | |
6d3d9133 | 2251 | newstr = (char *) ggc_alloc_string (newstr, len + 1); |
c27ba912 DM |
2252 | XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; |
2253 | } | |
2254 | ||
2255 | /* Assigns default attributes to newly defined type. This is used to | |
2256 | set short_call/long_call attributes for function types of | |
2257 | functions defined inside corresponding #pragma scopes. */ | |
1d6e90ac | 2258 | |
8d8e52be | 2259 | static void |
c27ba912 DM |
2260 | arm_set_default_type_attributes (type) |
2261 | tree type; | |
2262 | { | |
2263 | /* Add __attribute__ ((long_call)) to all functions, when | |
2264 | inside #pragma long_calls or __attribute__ ((short_call)), | |
2265 | when inside #pragma no_long_calls. */ | |
2266 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
2267 | { | |
2268 | tree type_attr_list, attr_name; | |
2269 | type_attr_list = TYPE_ATTRIBUTES (type); | |
2270 | ||
2271 | if (arm_pragma_long_calls == LONG) | |
2272 | attr_name = get_identifier ("long_call"); | |
2273 | else if (arm_pragma_long_calls == SHORT) | |
2274 | attr_name = get_identifier ("short_call"); | |
2275 | else | |
2276 | return; | |
2277 | ||
2278 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
2279 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
2280 | } | |
2281 | } | |
2282 | \f | |
2283 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be | |
6bc82793 | 2284 | defined within the current compilation unit. If this cannot be |
c27ba912 | 2285 | determined, then 0 is returned. */ |
1d6e90ac | 2286 | |
c27ba912 DM |
2287 | static int |
2288 | current_file_function_operand (sym_ref) | |
2289 | rtx sym_ref; | |
2290 | { | |
2291 | /* This is a bit of a fib. A function will have a short call flag | |
2292 | applied to its name if it has the short call attribute, or it has | |
2293 | already been defined within the current compilation unit. */ | |
2294 | if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0))) | |
2295 | return 1; | |
2296 | ||
6d77b53e | 2297 | /* The current function is always defined within the current compilation |
d6a7951f JM |
2298 | unit. if it s a weak definition however, then this may not be the real |
2299 | definition of the function, and so we have to say no. */ | |
c27ba912 | 2300 | if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0) |
5895f793 | 2301 | && !DECL_WEAK (current_function_decl)) |
c27ba912 DM |
2302 | return 1; |
2303 | ||
2304 | /* We cannot make the determination - default to returning 0. */ | |
2305 | return 0; | |
2306 | } | |
2307 | ||
825dda42 | 2308 | /* Return nonzero if a 32 bit "long_call" should be generated for |
c27ba912 DM |
2309 | this call. We generate a long_call if the function: |
2310 | ||
2311 | a. has an __attribute__((long call)) | |
2312 | or b. is within the scope of a #pragma long_calls | |
2313 | or c. the -mlong-calls command line switch has been specified | |
2314 | ||
2315 | However we do not generate a long call if the function: | |
2316 | ||
2317 | d. has an __attribute__ ((short_call)) | |
2318 | or e. is inside the scope of a #pragma no_long_calls | |
2319 | or f. has an __attribute__ ((section)) | |
2320 | or g. is defined within the current compilation unit. | |
2321 | ||
2322 | This function will be called by C fragments contained in the machine | |
2323 | description file. CALL_REF and CALL_COOKIE correspond to the matched | |
2324 | rtl operands. CALL_SYMBOL is used to distinguish between | |
2325 | two different callers of the function. It is set to 1 in the | |
2326 | "call_symbol" and "call_symbol_value" patterns and to 0 in the "call" | |
2327 | and "call_value" patterns. This is because of the difference in the | |
2328 | SYM_REFs passed by these patterns. */ | |
1d6e90ac | 2329 | |
c27ba912 DM |
2330 | int |
2331 | arm_is_longcall_p (sym_ref, call_cookie, call_symbol) | |
2332 | rtx sym_ref; | |
2333 | int call_cookie; | |
2334 | int call_symbol; | |
2335 | { | |
5895f793 | 2336 | if (!call_symbol) |
c27ba912 DM |
2337 | { |
2338 | if (GET_CODE (sym_ref) != MEM) | |
2339 | return 0; | |
2340 | ||
2341 | sym_ref = XEXP (sym_ref, 0); | |
2342 | } | |
2343 | ||
2344 | if (GET_CODE (sym_ref) != SYMBOL_REF) | |
2345 | return 0; | |
2346 | ||
2347 | if (call_cookie & CALL_SHORT) | |
2348 | return 0; | |
2349 | ||
2350 | if (TARGET_LONG_CALLS && flag_function_sections) | |
2351 | return 1; | |
2352 | ||
87e27392 | 2353 | if (current_file_function_operand (sym_ref)) |
c27ba912 DM |
2354 | return 0; |
2355 | ||
2356 | return (call_cookie & CALL_LONG) | |
2357 | || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0)) | |
2358 | || TARGET_LONG_CALLS; | |
2359 | } | |
f99fce0c | 2360 | |
825dda42 | 2361 | /* Return nonzero if it is ok to make a tail-call to DECL. */ |
1d6e90ac | 2362 | |
4977bab6 ZW |
2363 | static bool |
2364 | arm_function_ok_for_sibcall (decl, exp) | |
f99fce0c | 2365 | tree decl; |
4977bab6 | 2366 | tree exp ATTRIBUTE_UNUSED; |
f99fce0c RE |
2367 | { |
2368 | int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL; | |
2369 | ||
2370 | /* Never tailcall something for which we have no decl, or if we | |
2371 | are in Thumb mode. */ | |
2372 | if (decl == NULL || TARGET_THUMB) | |
4977bab6 | 2373 | return false; |
f99fce0c RE |
2374 | |
2375 | /* Get the calling method. */ | |
2376 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
2377 | call_type = CALL_SHORT; | |
2378 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
2379 | call_type = CALL_LONG; | |
2380 | ||
2381 | /* Cannot tail-call to long calls, since these are out of range of | |
2382 | a branch instruction. However, if not compiling PIC, we know | |
2383 | we can reach the symbol if it is in this compilation unit. */ | |
5895f793 | 2384 | if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl))) |
4977bab6 | 2385 | return false; |
f99fce0c RE |
2386 | |
2387 | /* If we are interworking and the function is not declared static | |
2388 | then we can't tail-call it unless we know that it exists in this | |
2389 | compilation unit (since it might be a Thumb routine). */ | |
5895f793 | 2390 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
4977bab6 | 2391 | return false; |
f99fce0c | 2392 | |
6d3d9133 NC |
2393 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
2394 | if (IS_INTERRUPT (arm_current_func_type ())) | |
4977bab6 | 2395 | return false; |
6d3d9133 | 2396 | |
f99fce0c | 2397 | /* Everything else is ok. */ |
4977bab6 | 2398 | return true; |
f99fce0c RE |
2399 | } |
2400 | ||
82e9d970 | 2401 | \f |
6b990f6b RE |
2402 | /* Addressing mode support functions. */ |
2403 | ||
2404 | /* Return non-zero if X is a legitimate immediate operand when compiling | |
2405 | for PIC. */ | |
32de079a RE |
2406 | int |
2407 | legitimate_pic_operand_p (x) | |
2408 | rtx x; | |
2409 | { | |
d5b7b3ae RE |
2410 | if (CONSTANT_P (x) |
2411 | && flag_pic | |
32de079a RE |
2412 | && (GET_CODE (x) == SYMBOL_REF |
2413 | || (GET_CODE (x) == CONST | |
2414 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2415 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))) | |
2416 | return 0; | |
2417 | ||
2418 | return 1; | |
2419 | } | |
2420 | ||
2421 | rtx | |
2422 | legitimize_pic_address (orig, mode, reg) | |
2423 | rtx orig; | |
2424 | enum machine_mode mode; | |
2425 | rtx reg; | |
2426 | { | |
a3c48721 RE |
2427 | if (GET_CODE (orig) == SYMBOL_REF |
2428 | || GET_CODE (orig) == LABEL_REF) | |
32de079a | 2429 | { |
5f37d07c | 2430 | #ifndef AOF_ASSEMBLER |
32de079a | 2431 | rtx pic_ref, address; |
5f37d07c | 2432 | #endif |
32de079a RE |
2433 | rtx insn; |
2434 | int subregs = 0; | |
2435 | ||
2436 | if (reg == 0) | |
2437 | { | |
893f3d5b | 2438 | if (no_new_pseudos) |
32de079a RE |
2439 | abort (); |
2440 | else | |
2441 | reg = gen_reg_rtx (Pmode); | |
2442 | ||
2443 | subregs = 1; | |
2444 | } | |
2445 | ||
2446 | #ifdef AOF_ASSEMBLER | |
2447 | /* The AOF assembler can generate relocations for these directly, and | |
6354dc9b | 2448 | understands that the PIC register has to be added into the offset. */ |
32de079a RE |
2449 | insn = emit_insn (gen_pic_load_addr_based (reg, orig)); |
2450 | #else | |
2451 | if (subregs) | |
2452 | address = gen_reg_rtx (Pmode); | |
2453 | else | |
2454 | address = reg; | |
2455 | ||
4bec9f7d NC |
2456 | if (TARGET_ARM) |
2457 | emit_insn (gen_pic_load_addr_arm (address, orig)); | |
2458 | else | |
2459 | emit_insn (gen_pic_load_addr_thumb (address, orig)); | |
32de079a | 2460 | |
14f583b8 PB |
2461 | if ((GET_CODE (orig) == LABEL_REF |
2462 | || (GET_CODE (orig) == SYMBOL_REF && | |
2463 | ENCODED_SHORT_CALL_ATTR_P (XSTR (orig, 0)))) | |
2464 | && NEED_GOT_RELOC) | |
a3c48721 RE |
2465 | pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address); |
2466 | else | |
2467 | { | |
2468 | pic_ref = gen_rtx_MEM (Pmode, | |
2469 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
2470 | address)); | |
2471 | RTX_UNCHANGING_P (pic_ref) = 1; | |
2472 | } | |
2473 | ||
32de079a RE |
2474 | insn = emit_move_insn (reg, pic_ref); |
2475 | #endif | |
2476 | current_function_uses_pic_offset_table = 1; | |
2477 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2478 | by loop. */ | |
43cffd11 RE |
2479 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, |
2480 | REG_NOTES (insn)); | |
32de079a RE |
2481 | return reg; |
2482 | } | |
2483 | else if (GET_CODE (orig) == CONST) | |
2484 | { | |
2485 | rtx base, offset; | |
2486 | ||
2487 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
2488 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2489 | return orig; | |
2490 | ||
2491 | if (reg == 0) | |
2492 | { | |
893f3d5b | 2493 | if (no_new_pseudos) |
32de079a RE |
2494 | abort (); |
2495 | else | |
2496 | reg = gen_reg_rtx (Pmode); | |
2497 | } | |
2498 | ||
2499 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
2500 | { | |
2501 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
2502 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2503 | base == reg ? 0 : reg); | |
2504 | } | |
2505 | else | |
2506 | abort (); | |
2507 | ||
2508 | if (GET_CODE (offset) == CONST_INT) | |
2509 | { | |
2510 | /* The base register doesn't really matter, we only want to | |
2511 | test the index for the appropriate mode. */ | |
6b990f6b RE |
2512 | if (!arm_legitimate_index_p (mode, offset, 0)) |
2513 | { | |
2514 | if (!no_new_pseudos) | |
2515 | offset = force_reg (Pmode, offset); | |
2516 | else | |
2517 | abort (); | |
2518 | } | |
32de079a | 2519 | |
32de079a | 2520 | if (GET_CODE (offset) == CONST_INT) |
ed8908e7 | 2521 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
2522 | } |
2523 | ||
2524 | if (GET_MODE_SIZE (mode) > 4 | |
2525 | && (GET_MODE_CLASS (mode) == MODE_INT | |
2526 | || TARGET_SOFT_FLOAT)) | |
2527 | { | |
2528 | emit_insn (gen_addsi3 (reg, base, offset)); | |
2529 | return reg; | |
2530 | } | |
2531 | ||
43cffd11 | 2532 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a | 2533 | } |
32de079a RE |
2534 | |
2535 | return orig; | |
2536 | } | |
2537 | ||
c1163e75 PB |
2538 | /* Generate code to load the PIC register. PROLOGUE is true if |
2539 | called from arm_expand_prologue (in which case we want the | |
2540 | generated insns at the start of the function); false if called | |
2541 | by an exception receiver that needs the PIC register reloaded | |
2542 | (in which case the insns are just dumped at the current location). */ | |
eab4abeb | 2543 | |
32de079a | 2544 | void |
eab4abeb | 2545 | arm_finalize_pic (prologue) |
5f37d07c | 2546 | int prologue ATTRIBUTE_UNUSED; |
32de079a RE |
2547 | { |
2548 | #ifndef AOF_ASSEMBLER | |
c1163e75 | 2549 | rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx; |
32de079a RE |
2550 | rtx global_offset_table; |
2551 | ||
ed0e6530 | 2552 | if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
2553 | return; |
2554 | ||
5895f793 | 2555 | if (!flag_pic) |
32de079a RE |
2556 | abort (); |
2557 | ||
2558 | start_sequence (); | |
2559 | l1 = gen_label_rtx (); | |
2560 | ||
43cffd11 | 2561 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); |
dfa08768 | 2562 | /* On the ARM the PC register contains 'dot + 8' at the time of the |
d5b7b3ae RE |
2563 | addition, on the Thumb it is 'dot + 4'. */ |
2564 | pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4); | |
84306176 PB |
2565 | if (GOT_PCREL) |
2566 | pic_tmp2 = gen_rtx_CONST (VOIDmode, | |
43cffd11 | 2567 | gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); |
84306176 PB |
2568 | else |
2569 | pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); | |
43cffd11 RE |
2570 | |
2571 | pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); | |
f5a1b0d2 | 2572 | |
d5b7b3ae | 2573 | if (TARGET_ARM) |
4bec9f7d NC |
2574 | { |
2575 | emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx)); | |
2576 | emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1)); | |
2577 | } | |
d5b7b3ae | 2578 | else |
4bec9f7d NC |
2579 | { |
2580 | emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx)); | |
2581 | emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1)); | |
2582 | } | |
32de079a | 2583 | |
2f937369 | 2584 | seq = get_insns (); |
32de079a | 2585 | end_sequence (); |
c1163e75 PB |
2586 | if (prologue) |
2587 | emit_insn_after (seq, get_insns ()); | |
2588 | else | |
2589 | emit_insn (seq); | |
32de079a RE |
2590 | |
2591 | /* Need to emit this whether or not we obey regdecls, | |
2592 | since setjmp/longjmp can cause life info to screw up. */ | |
43cffd11 | 2593 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
32de079a RE |
2594 | #endif /* AOF_ASSEMBLER */ |
2595 | } | |
2596 | ||
6b990f6b RE |
2597 | /* Return nonzero if X is valid as an ARM state addressing register. */ |
2598 | static int | |
2599 | arm_address_register_rtx_p (x, strict_p) | |
2600 | rtx x; | |
2601 | int strict_p; | |
2602 | { | |
2603 | int regno; | |
2604 | ||
2605 | if (GET_CODE (x) != REG) | |
2606 | return 0; | |
2607 | ||
2608 | regno = REGNO (x); | |
2609 | ||
2610 | if (strict_p) | |
2611 | return ARM_REGNO_OK_FOR_BASE_P (regno); | |
2612 | ||
2613 | return (regno <= LAST_ARM_REGNUM | |
2614 | || regno >= FIRST_PSEUDO_REGISTER | |
2615 | || regno == FRAME_POINTER_REGNUM | |
2616 | || regno == ARG_POINTER_REGNUM); | |
2617 | } | |
2618 | ||
2619 | /* Return nonzero if X is a valid ARM state address operand. */ | |
2620 | int | |
2621 | arm_legitimate_address_p (mode, x, strict_p) | |
2622 | enum machine_mode mode; | |
2623 | rtx x; | |
2624 | int strict_p; | |
2625 | { | |
2626 | if (arm_address_register_rtx_p (x, strict_p)) | |
2627 | return 1; | |
2628 | ||
2629 | else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC) | |
2630 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); | |
2631 | ||
2632 | else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY) | |
2633 | && GET_MODE_SIZE (mode) <= 4 | |
2634 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) | |
2635 | && GET_CODE (XEXP (x, 1)) == PLUS | |
2636 | && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) | |
2637 | return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p); | |
2638 | ||
2639 | /* After reload constants split into minipools will have addresses | |
2640 | from a LABEL_REF. */ | |
2641 | else if (GET_MODE_SIZE (mode) >= 4 && reload_completed | |
2642 | && (GET_CODE (x) == LABEL_REF | |
2643 | || (GET_CODE (x) == CONST | |
2644 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2645 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
2646 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
2647 | return 1; | |
2648 | ||
2649 | else if (mode == TImode) | |
2650 | return 0; | |
2651 | ||
2652 | else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode)) | |
2653 | { | |
2654 | if (GET_CODE (x) == PLUS | |
2655 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) | |
2656 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2657 | { | |
2658 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
2659 | ||
2660 | if (val == 4 || val == -4 || val == -8) | |
2661 | return 1; | |
2662 | } | |
2663 | } | |
2664 | ||
2665 | else if (GET_CODE (x) == PLUS) | |
2666 | { | |
2667 | rtx xop0 = XEXP (x, 0); | |
2668 | rtx xop1 = XEXP (x, 1); | |
2669 | ||
2670 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
2671 | && arm_legitimate_index_p (mode, xop1, strict_p)) | |
2672 | || (arm_address_register_rtx_p (xop1, strict_p) | |
2673 | && arm_legitimate_index_p (mode, xop0, strict_p))); | |
2674 | } | |
2675 | ||
2676 | #if 0 | |
2677 | /* Reload currently can't handle MINUS, so disable this for now */ | |
2678 | else if (GET_CODE (x) == MINUS) | |
2679 | { | |
2680 | rtx xop0 = XEXP (x, 0); | |
2681 | rtx xop1 = XEXP (x, 1); | |
2682 | ||
2683 | return (arm_address_register_rtx_p (xop0, strict_p) | |
2684 | && arm_legitimate_index_p (mode, xop1, strict_p)); | |
2685 | } | |
2686 | #endif | |
2687 | ||
2688 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
2689 | && GET_CODE (x) == SYMBOL_REF | |
2690 | && CONSTANT_POOL_ADDRESS_P (x) | |
2691 | && ! (flag_pic | |
2692 | && symbol_mentioned_p (get_pool_constant (x)))) | |
2693 | return 1; | |
2694 | ||
2695 | else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC) | |
2696 | && (GET_MODE_SIZE (mode) <= 4) | |
2697 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p)) | |
2698 | return 1; | |
2699 | ||
2700 | return 0; | |
2701 | } | |
2702 | ||
2703 | /* Return nonzero if INDEX is valid for an address index operand in | |
2704 | ARM state. */ | |
2705 | static int | |
2706 | arm_legitimate_index_p (mode, index, strict_p) | |
2707 | enum machine_mode mode; | |
2708 | rtx index; | |
2709 | int strict_p; | |
2710 | { | |
2711 | HOST_WIDE_INT range; | |
2712 | enum rtx_code code = GET_CODE (index); | |
2713 | ||
2714 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2715 | return (code == CONST_INT && INTVAL (index) < 1024 | |
2716 | && INTVAL (index) > -1024 | |
2717 | && (INTVAL (index) & 3) == 0); | |
2718 | ||
9b6b54e2 NC |
2719 | if (TARGET_CIRRUS |
2720 | && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode)) | |
2721 | return (code == CONST_INT | |
2722 | && INTVAL (index) < 255 | |
2723 | && INTVAL (index) > -255); | |
2724 | ||
6b990f6b RE |
2725 | if (arm_address_register_rtx_p (index, strict_p) |
2726 | && GET_MODE_SIZE (mode) <= 4) | |
2727 | return 1; | |
2728 | ||
2729 | /* XXX What about ldrsb? */ | |
2730 | if (GET_MODE_SIZE (mode) <= 4 && code == MULT | |
2731 | && (!arm_arch4 || (mode) != HImode)) | |
2732 | { | |
2733 | rtx xiop0 = XEXP (index, 0); | |
2734 | rtx xiop1 = XEXP (index, 1); | |
2735 | ||
2736 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
2737 | && power_of_two_operand (xiop1, SImode)) | |
2738 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
2739 | && power_of_two_operand (xiop0, SImode))); | |
2740 | } | |
2741 | ||
2742 | if (GET_MODE_SIZE (mode) <= 4 | |
2743 | && (code == LSHIFTRT || code == ASHIFTRT | |
2744 | || code == ASHIFT || code == ROTATERT) | |
2745 | && (!arm_arch4 || (mode) != HImode)) | |
2746 | { | |
2747 | rtx op = XEXP (index, 1); | |
2748 | ||
2749 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) | |
2750 | && GET_CODE (op) == CONST_INT | |
2751 | && INTVAL (op) > 0 | |
2752 | && INTVAL (op) <= 31); | |
2753 | } | |
2754 | ||
2755 | /* XXX For ARM v4 we may be doing a sign-extend operation during the | |
2756 | load, but that has a restricted addressing range and we are unable | |
2757 | to tell here whether that is the case. To be safe we restrict all | |
2758 | loads to that range. */ | |
2759 | range = ((mode) == HImode || (mode) == QImode) | |
2760 | ? (arm_arch4 ? 256 : 4095) : 4096; | |
2761 | ||
2762 | return (code == CONST_INT | |
2763 | && INTVAL (index) < range | |
2764 | && INTVAL (index) > -range); | |
76a318e9 RE |
2765 | } |
2766 | ||
2767 | /* Return nonzero if X is valid as an ARM state addressing register. */ | |
2768 | static int | |
2769 | thumb_base_register_rtx_p (x, mode, strict_p) | |
2770 | rtx x; | |
2771 | enum machine_mode mode; | |
2772 | int strict_p; | |
2773 | { | |
2774 | int regno; | |
2775 | ||
2776 | if (GET_CODE (x) != REG) | |
2777 | return 0; | |
2778 | ||
2779 | regno = REGNO (x); | |
2780 | ||
2781 | if (strict_p) | |
2782 | return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode); | |
2783 | ||
2784 | return (regno <= LAST_LO_REGNUM | |
2785 | || regno >= FIRST_PSEUDO_REGISTER | |
2786 | || regno == FRAME_POINTER_REGNUM | |
2787 | || (GET_MODE_SIZE (mode) >= 4 | |
2788 | && (regno == STACK_POINTER_REGNUM | |
2789 | || x == hard_frame_pointer_rtx | |
2790 | || x == arg_pointer_rtx))); | |
2791 | } | |
2792 | ||
2793 | /* Return nonzero if x is a legitimate index register. This is the case | |
2794 | for any base register that can access a QImode object. */ | |
2795 | inline static int | |
2796 | thumb_index_register_rtx_p (x, strict_p) | |
2797 | rtx x; | |
2798 | int strict_p; | |
2799 | { | |
2800 | return thumb_base_register_rtx_p (x, QImode, strict_p); | |
2801 | } | |
2802 | ||
2803 | /* Return nonzero if x is a legitimate Thumb-state address. | |
2804 | ||
2805 | The AP may be eliminated to either the SP or the FP, so we use the | |
2806 | least common denominator, e.g. SImode, and offsets from 0 to 64. | |
2807 | ||
2808 | ??? Verify whether the above is the right approach. | |
2809 | ||
2810 | ??? Also, the FP may be eliminated to the SP, so perhaps that | |
2811 | needs special handling also. | |
2812 | ||
2813 | ??? Look at how the mips16 port solves this problem. It probably uses | |
2814 | better ways to solve some of these problems. | |
2815 | ||
2816 | Although it is not incorrect, we don't accept QImode and HImode | |
2817 | addresses based on the frame pointer or arg pointer until the | |
2818 | reload pass starts. This is so that eliminating such addresses | |
2819 | into stack based ones won't produce impossible code. */ | |
2820 | int | |
2821 | thumb_legitimate_address_p (mode, x, strict_p) | |
2822 | enum machine_mode mode; | |
2823 | rtx x; | |
2824 | int strict_p; | |
2825 | { | |
2826 | /* ??? Not clear if this is right. Experiment. */ | |
2827 | if (GET_MODE_SIZE (mode) < 4 | |
2828 | && !(reload_in_progress || reload_completed) | |
2829 | && (reg_mentioned_p (frame_pointer_rtx, x) | |
2830 | || reg_mentioned_p (arg_pointer_rtx, x) | |
2831 | || reg_mentioned_p (virtual_incoming_args_rtx, x) | |
2832 | || reg_mentioned_p (virtual_outgoing_args_rtx, x) | |
2833 | || reg_mentioned_p (virtual_stack_dynamic_rtx, x) | |
2834 | || reg_mentioned_p (virtual_stack_vars_rtx, x))) | |
2835 | return 0; | |
2836 | ||
2837 | /* Accept any base register. SP only in SImode or larger. */ | |
2838 | else if (thumb_base_register_rtx_p (x, mode, strict_p)) | |
2839 | return 1; | |
2840 | ||
2841 | /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ | |
2842 | else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) | |
2843 | && GET_CODE (x) == SYMBOL_REF | |
2844 | && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic) | |
2845 | return 1; | |
2846 | ||
2847 | /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ | |
2848 | else if (GET_MODE_SIZE (mode) >= 4 && reload_completed | |
2849 | && (GET_CODE (x) == LABEL_REF | |
2850 | || (GET_CODE (x) == CONST | |
2851 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2852 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
2853 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
2854 | return 1; | |
2855 | ||
2856 | /* Post-inc indexing only supported for SImode and larger. */ | |
2857 | else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 | |
2858 | && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)) | |
2859 | return 1; | |
2860 | ||
2861 | else if (GET_CODE (x) == PLUS) | |
2862 | { | |
2863 | /* REG+REG address can be any two index registers. */ | |
2864 | /* We disallow FRAME+REG addressing since we know that FRAME | |
2865 | will be replaced with STACK, and SP relative addressing only | |
2866 | permits SP+OFFSET. */ | |
2867 | if (GET_MODE_SIZE (mode) <= 4 | |
2868 | && XEXP (x, 0) != frame_pointer_rtx | |
2869 | && XEXP (x, 1) != frame_pointer_rtx | |
2870 | && XEXP (x, 0) != virtual_stack_vars_rtx | |
2871 | && XEXP (x, 1) != virtual_stack_vars_rtx | |
2872 | && thumb_index_register_rtx_p (XEXP (x, 0), strict_p) | |
2873 | && thumb_index_register_rtx_p (XEXP (x, 1), strict_p)) | |
2874 | return 1; | |
2875 | ||
2876 | /* REG+const has 5-7 bit offset for non-SP registers. */ | |
2877 | else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p) | |
2878 | || XEXP (x, 0) == arg_pointer_rtx) | |
2879 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2880 | && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
2881 | return 1; | |
2882 | ||
2883 | /* REG+const has 10 bit offset for SP, but only SImode and | |
2884 | larger is supported. */ | |
2885 | /* ??? Should probably check for DI/DFmode overflow here | |
2886 | just like GO_IF_LEGITIMATE_OFFSET does. */ | |
2887 | else if (GET_CODE (XEXP (x, 0)) == REG | |
2888 | && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM | |
2889 | && GET_MODE_SIZE (mode) >= 4 | |
2890 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2891 | && INTVAL (XEXP (x, 1)) >= 0 | |
2892 | && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 | |
2893 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
2894 | return 1; | |
2895 | ||
2896 | else if (GET_CODE (XEXP (x, 0)) == REG | |
2897 | && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM | |
2898 | && GET_MODE_SIZE (mode) >= 4 | |
2899 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2900 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
2901 | return 1; | |
2902 | } | |
2903 | ||
2904 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
2905 | && GET_CODE (x) == SYMBOL_REF | |
2906 | && CONSTANT_POOL_ADDRESS_P (x) | |
2907 | && !(flag_pic | |
2908 | && symbol_mentioned_p (get_pool_constant (x)))) | |
2909 | return 1; | |
2910 | ||
2911 | return 0; | |
2912 | } | |
2913 | ||
2914 | /* Return nonzero if VAL can be used as an offset in a Thumb-state address | |
2915 | instruction of mode MODE. */ | |
2916 | int | |
2917 | thumb_legitimate_offset_p (mode, val) | |
2918 | enum machine_mode mode; | |
2919 | HOST_WIDE_INT val; | |
2920 | { | |
2921 | switch (GET_MODE_SIZE (mode)) | |
2922 | { | |
2923 | case 1: | |
2924 | return val >= 0 && val < 32; | |
2925 | ||
2926 | case 2: | |
2927 | return val >= 0 && val < 64 && (val & 1) == 0; | |
2928 | ||
2929 | default: | |
2930 | return (val >= 0 | |
2931 | && (val + GET_MODE_SIZE (mode)) <= 128 | |
2932 | && (val & 3) == 0); | |
2933 | } | |
2934 | } | |
2935 | ||
ccf4d512 RE |
2936 | /* Try machine-dependent ways of modifying an illegitimate address |
2937 | to be legitimate. If we find one, return the new, valid address. */ | |
2938 | ||
2939 | rtx | |
2940 | arm_legitimize_address (x, orig_x, mode) | |
2941 | rtx x; | |
2942 | rtx orig_x; | |
2943 | enum machine_mode mode; | |
2944 | { | |
2945 | if (GET_CODE (x) == PLUS) | |
2946 | { | |
2947 | rtx xop0 = XEXP (x, 0); | |
2948 | rtx xop1 = XEXP (x, 1); | |
2949 | ||
2950 | if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) | |
2951 | xop0 = force_reg (SImode, xop0); | |
2952 | ||
2953 | if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) | |
2954 | xop1 = force_reg (SImode, xop1); | |
2955 | ||
2956 | if (ARM_BASE_REGISTER_RTX_P (xop0) | |
2957 | && GET_CODE (xop1) == CONST_INT) | |
2958 | { | |
2959 | HOST_WIDE_INT n, low_n; | |
2960 | rtx base_reg, val; | |
2961 | n = INTVAL (xop1); | |
2962 | ||
2963 | if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode)) | |
2964 | { | |
2965 | low_n = n & 0x0f; | |
2966 | n &= ~0x0f; | |
2967 | if (low_n > 4) | |
2968 | { | |
2969 | n += 16; | |
2970 | low_n -= 16; | |
2971 | } | |
2972 | } | |
2973 | else | |
2974 | { | |
2975 | low_n = ((mode) == TImode ? 0 | |
2976 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); | |
2977 | n -= low_n; | |
2978 | } | |
2979 | ||
2980 | base_reg = gen_reg_rtx (SImode); | |
2981 | val = force_operand (gen_rtx_PLUS (SImode, xop0, | |
2982 | GEN_INT (n)), NULL_RTX); | |
2983 | emit_move_insn (base_reg, val); | |
2984 | x = (low_n == 0 ? base_reg | |
2985 | : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); | |
2986 | } | |
2987 | else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
2988 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
2989 | } | |
2990 | ||
2991 | /* XXX We don't allow MINUS any more -- see comment in | |
2992 | arm_legitimate_address_p (). */ | |
2993 | else if (GET_CODE (x) == MINUS) | |
2994 | { | |
2995 | rtx xop0 = XEXP (x, 0); | |
2996 | rtx xop1 = XEXP (x, 1); | |
2997 | ||
2998 | if (CONSTANT_P (xop0)) | |
2999 | xop0 = force_reg (SImode, xop0); | |
3000 | ||
3001 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) | |
3002 | xop1 = force_reg (SImode, xop1); | |
3003 | ||
3004 | if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
3005 | x = gen_rtx_MINUS (SImode, xop0, xop1); | |
3006 | } | |
3007 | ||
3008 | if (flag_pic) | |
3009 | { | |
3010 | /* We need to find and carefully transform any SYMBOL and LABEL | |
3011 | references; so go back to the original address expression. */ | |
3012 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
3013 | ||
3014 | if (new_x != orig_x) | |
3015 | x = new_x; | |
3016 | } | |
3017 | ||
3018 | return x; | |
3019 | } | |
3020 | ||
6b990f6b RE |
3021 | \f |
3022 | ||
e2c671ba RE |
3023 | #define REG_OR_SUBREG_REG(X) \ |
3024 | (GET_CODE (X) == REG \ | |
3025 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
3026 | ||
3027 | #define REG_OR_SUBREG_RTX(X) \ | |
3028 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
3029 | ||
d5b7b3ae RE |
3030 | #ifndef COSTS_N_INSNS |
3031 | #define COSTS_N_INSNS(N) ((N) * 4 - 2) | |
3032 | #endif | |
e2c671ba | 3033 | |
3c50106f RH |
3034 | static inline int |
3035 | arm_rtx_costs_1 (x, code, outer) | |
e2c671ba | 3036 | rtx x; |
74bbc178 | 3037 | enum rtx_code code; |
d5b7b3ae | 3038 | enum rtx_code outer; |
e2c671ba RE |
3039 | { |
3040 | enum machine_mode mode = GET_MODE (x); | |
3041 | enum rtx_code subcode; | |
3042 | int extra_cost; | |
3043 | ||
d5b7b3ae RE |
3044 | if (TARGET_THUMB) |
3045 | { | |
3046 | switch (code) | |
3047 | { | |
3048 | case ASHIFT: | |
3049 | case ASHIFTRT: | |
3050 | case LSHIFTRT: | |
3051 | case ROTATERT: | |
3052 | case PLUS: | |
3053 | case MINUS: | |
3054 | case COMPARE: | |
3055 | case NEG: | |
3056 | case NOT: | |
3057 | return COSTS_N_INSNS (1); | |
3058 | ||
3059 | case MULT: | |
3060 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3061 | { | |
3062 | int cycles = 0; | |
3063 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); | |
3064 | ||
3065 | while (i) | |
3066 | { | |
3067 | i >>= 2; | |
5895f793 | 3068 | cycles++; |
d5b7b3ae RE |
3069 | } |
3070 | return COSTS_N_INSNS (2) + cycles; | |
3071 | } | |
3072 | return COSTS_N_INSNS (1) + 16; | |
3073 | ||
3074 | case SET: | |
3075 | return (COSTS_N_INSNS (1) | |
3076 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
3077 | + GET_CODE (SET_DEST (x)) == MEM)); | |
3078 | ||
3079 | case CONST_INT: | |
3080 | if (outer == SET) | |
3081 | { | |
3082 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
3083 | return 0; | |
3084 | if (thumb_shiftable_const (INTVAL (x))) | |
3085 | return COSTS_N_INSNS (2); | |
3086 | return COSTS_N_INSNS (3); | |
3087 | } | |
3088 | else if (outer == PLUS | |
3089 | && INTVAL (x) < 256 && INTVAL (x) > -256) | |
3090 | return 0; | |
3091 | else if (outer == COMPARE | |
3092 | && (unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
3093 | return 0; | |
3094 | else if (outer == ASHIFT || outer == ASHIFTRT | |
3095 | || outer == LSHIFTRT) | |
3096 | return 0; | |
3097 | return COSTS_N_INSNS (2); | |
3098 | ||
3099 | case CONST: | |
3100 | case CONST_DOUBLE: | |
3101 | case LABEL_REF: | |
3102 | case SYMBOL_REF: | |
3103 | return COSTS_N_INSNS (3); | |
3104 | ||
3105 | case UDIV: | |
3106 | case UMOD: | |
3107 | case DIV: | |
3108 | case MOD: | |
3109 | return 100; | |
3110 | ||
3111 | case TRUNCATE: | |
3112 | return 99; | |
3113 | ||
3114 | case AND: | |
3115 | case XOR: | |
3116 | case IOR: | |
3117 | /* XXX guess. */ | |
3118 | return 8; | |
3119 | ||
3120 | case ADDRESSOF: | |
3121 | case MEM: | |
3122 | /* XXX another guess. */ | |
3123 | /* Memory costs quite a lot for the first word, but subsequent words | |
3124 | load at the equivalent of a single insn each. */ | |
3125 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
48f6efae NC |
3126 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) |
3127 | ? 4 : 0)); | |
d5b7b3ae RE |
3128 | |
3129 | case IF_THEN_ELSE: | |
3130 | /* XXX a guess. */ | |
3131 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
3132 | return 14; | |
3133 | return 2; | |
3134 | ||
3135 | case ZERO_EXTEND: | |
3136 | /* XXX still guessing. */ | |
3137 | switch (GET_MODE (XEXP (x, 0))) | |
3138 | { | |
3139 | case QImode: | |
3140 | return (1 + (mode == DImode ? 4 : 0) | |
3141 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3142 | ||
3143 | case HImode: | |
3144 | return (4 + (mode == DImode ? 4 : 0) | |
3145 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3146 | ||
3147 | case SImode: | |
3148 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3149 | ||
3150 | default: | |
3151 | return 99; | |
3152 | } | |
3153 | ||
3154 | default: | |
3155 | return 99; | |
3156 | #if 0 | |
3157 | case FFS: | |
3158 | case FLOAT: | |
3159 | case FIX: | |
3160 | case UNSIGNED_FIX: | |
3161 | /* XXX guess */ | |
3162 | fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n", | |
3163 | rtx_name[code]); | |
3164 | abort (); | |
3165 | #endif | |
3166 | } | |
3167 | } | |
3168 | ||
e2c671ba RE |
3169 | switch (code) |
3170 | { | |
3171 | case MEM: | |
3172 | /* Memory costs quite a lot for the first word, but subsequent words | |
3173 | load at the equivalent of a single insn each. */ | |
3174 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
48f6efae NC |
3175 | + (GET_CODE (x) == SYMBOL_REF |
3176 | && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); | |
e2c671ba RE |
3177 | |
3178 | case DIV: | |
3179 | case MOD: | |
3180 | return 100; | |
3181 | ||
3182 | case ROTATE: | |
3183 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
3184 | return 4; | |
3185 | /* Fall through */ | |
3186 | case ROTATERT: | |
3187 | if (mode != SImode) | |
3188 | return 8; | |
3189 | /* Fall through */ | |
3190 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
3191 | if (mode == DImode) | |
3192 | return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) | |
3193 | + ((GET_CODE (XEXP (x, 0)) == REG | |
3194 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
3195 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
3196 | ? 0 : 8)); | |
3197 | return (1 + ((GET_CODE (XEXP (x, 0)) == REG | |
3198 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
3199 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
3200 | ? 0 : 4) | |
3201 | + ((GET_CODE (XEXP (x, 1)) == REG | |
3202 | || (GET_CODE (XEXP (x, 1)) == SUBREG | |
3203 | && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG) | |
3204 | || (GET_CODE (XEXP (x, 1)) == CONST_INT)) | |
3205 | ? 0 : 4)); | |
3206 | ||
3207 | case MINUS: | |
3208 | if (mode == DImode) | |
3209 | return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8) | |
3210 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3211 | || (GET_CODE (XEXP (x, 0)) == CONST_INT | |
3212 | && const_ok_for_arm (INTVAL (XEXP (x, 0))))) | |
3213 | ? 0 : 8)); | |
3214 | ||
3215 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3216 | return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3217 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
3b684012 | 3218 | && const_double_rtx_ok_for_fpa (XEXP (x, 1)))) |
e2c671ba RE |
3219 | ? 0 : 8) |
3220 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3221 | || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
3b684012 | 3222 | && const_double_rtx_ok_for_fpa (XEXP (x, 0)))) |
e2c671ba RE |
3223 | ? 0 : 8)); |
3224 | ||
3225 | if (((GET_CODE (XEXP (x, 0)) == CONST_INT | |
3226 | && const_ok_for_arm (INTVAL (XEXP (x, 0))) | |
3227 | && REG_OR_SUBREG_REG (XEXP (x, 1)))) | |
3228 | || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT | |
3229 | || subcode == ASHIFTRT || subcode == LSHIFTRT | |
3230 | || subcode == ROTATE || subcode == ROTATERT | |
3231 | || (subcode == MULT | |
3232 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
3233 | && ((INTVAL (XEXP (XEXP (x, 1), 1)) & | |
3234 | (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) | |
3235 | && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0)) | |
3236 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1)) | |
3237 | || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
3238 | && REG_OR_SUBREG_REG (XEXP (x, 0)))) | |
3239 | return 1; | |
3240 | /* Fall through */ | |
3241 | ||
3242 | case PLUS: | |
3243 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3244 | return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
3245 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3246 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
3b684012 | 3247 | && const_double_rtx_ok_for_fpa (XEXP (x, 1)))) |
e2c671ba RE |
3248 | ? 0 : 8)); |
3249 | ||
3250 | /* Fall through */ | |
3251 | case AND: case XOR: case IOR: | |
3252 | extra_cost = 0; | |
3253 | ||
3254 | /* Normally the frame registers will be spilt into reg+const during | |
3255 | reload, so it is a bad idea to combine them with other instructions, | |
3256 | since then they might not be moved outside of loops. As a compromise | |
3257 | we allow integration with ops that have a constant as their second | |
3258 | operand. */ | |
3259 | if ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3260 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
3261 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
3262 | || (REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3263 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) | |
3264 | extra_cost = 4; | |
3265 | ||
3266 | if (mode == DImode) | |
3267 | return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
3268 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3269 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 3270 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
3271 | ? 0 : 8)); |
3272 | ||
3273 | if (REG_OR_SUBREG_REG (XEXP (x, 0))) | |
3274 | return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost) | |
3275 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3276 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 3277 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
3278 | ? 0 : 4)); |
3279 | ||
3280 | else if (REG_OR_SUBREG_REG (XEXP (x, 1))) | |
3281 | return (1 + extra_cost | |
3282 | + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT | |
3283 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
3284 | || subcode == ROTATE || subcode == ROTATERT | |
3285 | || (subcode == MULT | |
3286 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3287 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
ad076f4e | 3288 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) |
e2c671ba RE |
3289 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0))) |
3290 | && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1))) | |
ad076f4e | 3291 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) |
e2c671ba RE |
3292 | ? 0 : 4)); |
3293 | ||
3294 | return 8; | |
3295 | ||
3296 | case MULT: | |
b111229a | 3297 | /* There is no point basing this on the tuning, since it is always the |
6354dc9b | 3298 | fast variant if it exists at all. */ |
2b835d68 RE |
3299 | if (arm_fast_multiply && mode == DImode |
3300 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
3301 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
3302 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
3303 | return 8; | |
3304 | ||
e2c671ba RE |
3305 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
3306 | || mode == DImode) | |
3307 | return 30; | |
3308 | ||
3309 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3310 | { | |
2b835d68 | 3311 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) |
30cf4896 | 3312 | & (unsigned HOST_WIDE_INT) 0xffffffff); |
e2c671ba RE |
3313 | int add_cost = const_ok_for_arm (i) ? 4 : 8; |
3314 | int j; | |
6354dc9b NC |
3315 | |
3316 | /* Tune as appropriate. */ | |
aec3cfba | 3317 | int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2); |
2a5307b1 | 3318 | |
2b835d68 | 3319 | for (j = 0; i && j < 32; j += booth_unit_size) |
e2c671ba | 3320 | { |
2b835d68 | 3321 | i >>= booth_unit_size; |
e2c671ba RE |
3322 | add_cost += 2; |
3323 | } | |
3324 | ||
3325 | return add_cost; | |
3326 | } | |
3327 | ||
aec3cfba | 3328 | return (((tune_flags & FL_FAST_MULT) ? 8 : 30) |
2b835d68 | 3329 | + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) |
e2c671ba RE |
3330 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4)); |
3331 | ||
56636818 JL |
3332 | case TRUNCATE: |
3333 | if (arm_fast_multiply && mode == SImode | |
3334 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
3335 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
3336 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
3337 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
3338 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
3339 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
3340 | return 8; | |
3341 | return 99; | |
3342 | ||
e2c671ba RE |
3343 | case NEG: |
3344 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3345 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6); | |
3346 | /* Fall through */ | |
3347 | case NOT: | |
3348 | if (mode == DImode) | |
3349 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
3350 | ||
3351 | return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
3352 | ||
3353 | case IF_THEN_ELSE: | |
3354 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
3355 | return 14; | |
3356 | return 2; | |
3357 | ||
3358 | case COMPARE: | |
3359 | return 1; | |
3360 | ||
3361 | case ABS: | |
3362 | return 4 + (mode == DImode ? 4 : 0); | |
3363 | ||
3364 | case SIGN_EXTEND: | |
3365 | if (GET_MODE (XEXP (x, 0)) == QImode) | |
3366 | return (4 + (mode == DImode ? 4 : 0) | |
3367 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3368 | /* Fall through */ | |
3369 | case ZERO_EXTEND: | |
3370 | switch (GET_MODE (XEXP (x, 0))) | |
3371 | { | |
3372 | case QImode: | |
3373 | return (1 + (mode == DImode ? 4 : 0) | |
3374 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3375 | ||
3376 | case HImode: | |
3377 | return (4 + (mode == DImode ? 4 : 0) | |
3378 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3379 | ||
3380 | case SImode: | |
3381 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
ad076f4e RE |
3382 | |
3383 | default: | |
3384 | break; | |
e2c671ba RE |
3385 | } |
3386 | abort (); | |
3387 | ||
d5b7b3ae RE |
3388 | case CONST_INT: |
3389 | if (const_ok_for_arm (INTVAL (x))) | |
3390 | return outer == SET ? 2 : -1; | |
3391 | else if (outer == AND | |
5895f793 | 3392 | && const_ok_for_arm (~INTVAL (x))) |
d5b7b3ae RE |
3393 | return -1; |
3394 | else if ((outer == COMPARE | |
3395 | || outer == PLUS || outer == MINUS) | |
5895f793 | 3396 | && const_ok_for_arm (-INTVAL (x))) |
d5b7b3ae RE |
3397 | return -1; |
3398 | else | |
3399 | return 5; | |
3400 | ||
3401 | case CONST: | |
3402 | case LABEL_REF: | |
3403 | case SYMBOL_REF: | |
3404 | return 6; | |
3405 | ||
3406 | case CONST_DOUBLE: | |
3b684012 | 3407 | if (const_double_rtx_ok_for_fpa (x)) |
d5b7b3ae RE |
3408 | return outer == SET ? 2 : -1; |
3409 | else if ((outer == COMPARE || outer == PLUS) | |
3b684012 | 3410 | && neg_const_double_rtx_ok_for_fpa (x)) |
d5b7b3ae RE |
3411 | return -1; |
3412 | return 7; | |
3413 | ||
e2c671ba RE |
3414 | default: |
3415 | return 99; | |
3416 | } | |
3417 | } | |
32de079a | 3418 | |
3c50106f RH |
3419 | static bool |
3420 | arm_rtx_costs (x, code, outer_code, total) | |
3421 | rtx x; | |
3422 | int code, outer_code; | |
3423 | int *total; | |
3424 | { | |
3425 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
3426 | return true; | |
3427 | } | |
3428 | ||
dcefdf67 RH |
3429 | /* All address computations that can be done are free, but rtx cost returns |
3430 | the same for practically all of them. So we weight the different types | |
3431 | of address here in the order (most pref first): | |
3432 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ | |
3433 | ||
3434 | static int | |
3435 | arm_address_cost (X) | |
3436 | rtx X; | |
3437 | { | |
3438 | #define ARM_ADDRESS_COST(X) \ | |
3439 | (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ | |
3440 | || GET_CODE (X) == SYMBOL_REF) \ | |
3441 | ? 0 \ | |
3442 | : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ | |
3443 | || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ | |
3444 | ? 10 \ | |
3445 | : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ | |
3446 | ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ | |
3447 | : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ | |
3448 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ | |
3449 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ | |
3450 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ | |
3451 | ? 1 : 0)) \ | |
3452 | : 4))))) | |
3453 | ||
3454 | #define THUMB_ADDRESS_COST(X) \ | |
3455 | ((GET_CODE (X) == REG \ | |
3456 | || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
3457 | && GET_CODE (XEXP (X, 1)) == CONST_INT)) \ | |
3458 | ? 1 : 2) | |
3459 | ||
3460 | return (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X)); | |
3461 | } | |
3462 | ||
c237e94a | 3463 | static int |
32de079a RE |
3464 | arm_adjust_cost (insn, link, dep, cost) |
3465 | rtx insn; | |
3466 | rtx link; | |
3467 | rtx dep; | |
3468 | int cost; | |
3469 | { | |
3470 | rtx i_pat, d_pat; | |
3471 | ||
d19fb8e3 NC |
3472 | /* Some true dependencies can have a higher cost depending |
3473 | on precisely how certain input operands are used. */ | |
3474 | if (arm_is_xscale | |
3475 | && REG_NOTE_KIND (link) == 0 | |
eda833e3 BE |
3476 | && recog_memoized (insn) >= 0 |
3477 | && recog_memoized (dep) >= 0) | |
d19fb8e3 NC |
3478 | { |
3479 | int shift_opnum = get_attr_shift (insn); | |
3480 | enum attr_type attr_type = get_attr_type (dep); | |
3481 | ||
3482 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
3483 | operand for INSN. If we have a shifted input operand and the | |
3484 | instruction we depend on is another ALU instruction, then we may | |
3485 | have to account for an additional stall. */ | |
3486 | if (shift_opnum != 0 && attr_type == TYPE_NORMAL) | |
3487 | { | |
3488 | rtx shifted_operand; | |
3489 | int opno; | |
3490 | ||
3491 | /* Get the shifted operand. */ | |
3492 | extract_insn (insn); | |
3493 | shifted_operand = recog_data.operand[shift_opnum]; | |
3494 | ||
3495 | /* Iterate over all the operands in DEP. If we write an operand | |
3496 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
3497 | cost of this dependency. */ | |
3498 | extract_insn (dep); | |
3499 | preprocess_constraints (); | |
3500 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
3501 | { | |
3502 | /* We can ignore strict inputs. */ | |
3503 | if (recog_data.operand_type[opno] == OP_IN) | |
3504 | continue; | |
3505 | ||
3506 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
3507 | shifted_operand)) | |
3508 | return 2; | |
3509 | } | |
3510 | } | |
3511 | } | |
3512 | ||
6354dc9b | 3513 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
3514 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
3515 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
3516 | return 0; |
3517 | ||
d5b7b3ae RE |
3518 | /* Call insns don't incur a stall, even if they follow a load. */ |
3519 | if (REG_NOTE_KIND (link) == 0 | |
3520 | && GET_CODE (insn) == CALL_INSN) | |
3521 | return 1; | |
3522 | ||
32de079a RE |
3523 | if ((i_pat = single_set (insn)) != NULL |
3524 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
3525 | && (d_pat = single_set (dep)) != NULL | |
3526 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
3527 | { | |
48f6efae | 3528 | rtx src_mem = XEXP (SET_SRC (i_pat), 0); |
32de079a RE |
3529 | /* This is a load after a store, there is no conflict if the load reads |
3530 | from a cached area. Assume that loads from the stack, and from the | |
3531 | constant pool are cached, and that others will miss. This is a | |
6354dc9b | 3532 | hack. */ |
32de079a | 3533 | |
48f6efae NC |
3534 | if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) |
3535 | || reg_mentioned_p (stack_pointer_rtx, src_mem) | |
3536 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | |
3537 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | |
949d79eb | 3538 | return 1; |
32de079a RE |
3539 | } |
3540 | ||
3541 | return cost; | |
3542 | } | |
3543 | ||
6354dc9b | 3544 | /* This code has been fixed for cross compilation. */ |
ff9940b0 RE |
3545 | |
3546 | static int fpa_consts_inited = 0; | |
3547 | ||
1d6e90ac | 3548 | static const char * const strings_fpa[8] = |
62b10bbc | 3549 | { |
2b835d68 RE |
3550 | "0", "1", "2", "3", |
3551 | "4", "5", "0.5", "10" | |
3552 | }; | |
ff9940b0 RE |
3553 | |
3554 | static REAL_VALUE_TYPE values_fpa[8]; | |
3555 | ||
3556 | static void | |
3557 | init_fpa_table () | |
3558 | { | |
3559 | int i; | |
3560 | REAL_VALUE_TYPE r; | |
3561 | ||
3562 | for (i = 0; i < 8; i++) | |
3563 | { | |
3564 | r = REAL_VALUE_ATOF (strings_fpa[i], DFmode); | |
3565 | values_fpa[i] = r; | |
3566 | } | |
f3bb6135 | 3567 | |
ff9940b0 RE |
3568 | fpa_consts_inited = 1; |
3569 | } | |
3570 | ||
3b684012 | 3571 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
cce8749e CH |
3572 | |
3573 | int | |
3b684012 | 3574 | const_double_rtx_ok_for_fpa (x) |
cce8749e CH |
3575 | rtx x; |
3576 | { | |
ff9940b0 RE |
3577 | REAL_VALUE_TYPE r; |
3578 | int i; | |
3579 | ||
3580 | if (!fpa_consts_inited) | |
3581 | init_fpa_table (); | |
3582 | ||
3583 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
3584 | if (REAL_VALUE_MINUS_ZERO (r)) | |
3585 | return 0; | |
f3bb6135 | 3586 | |
ff9940b0 RE |
3587 | for (i = 0; i < 8; i++) |
3588 | if (REAL_VALUES_EQUAL (r, values_fpa[i])) | |
3589 | return 1; | |
f3bb6135 | 3590 | |
ff9940b0 | 3591 | return 0; |
f3bb6135 | 3592 | } |
ff9940b0 | 3593 | |
3b684012 | 3594 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
ff9940b0 RE |
3595 | |
3596 | int | |
3b684012 | 3597 | neg_const_double_rtx_ok_for_fpa (x) |
ff9940b0 RE |
3598 | rtx x; |
3599 | { | |
3600 | REAL_VALUE_TYPE r; | |
3601 | int i; | |
3602 | ||
3603 | if (!fpa_consts_inited) | |
3604 | init_fpa_table (); | |
3605 | ||
3606 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
3607 | r = REAL_VALUE_NEGATE (r); | |
3608 | if (REAL_VALUE_MINUS_ZERO (r)) | |
3609 | return 0; | |
f3bb6135 | 3610 | |
ff9940b0 RE |
3611 | for (i = 0; i < 8; i++) |
3612 | if (REAL_VALUES_EQUAL (r, values_fpa[i])) | |
3613 | return 1; | |
f3bb6135 | 3614 | |
ff9940b0 | 3615 | return 0; |
f3bb6135 | 3616 | } |
cce8749e CH |
3617 | \f |
3618 | /* Predicates for `match_operand' and `match_operator'. */ | |
3619 | ||
ff9940b0 | 3620 | /* s_register_operand is the same as register_operand, but it doesn't accept |
56a38cec DE |
3621 | (SUBREG (MEM)...). |
3622 | ||
3623 | This function exists because at the time it was put in it led to better | |
3624 | code. SUBREG(MEM) always needs a reload in the places where | |
3625 | s_register_operand is used, and this seemed to lead to excessive | |
3626 | reloading. */ | |
ff9940b0 RE |
3627 | |
3628 | int | |
3629 | s_register_operand (op, mode) | |
1d6e90ac | 3630 | rtx op; |
ff9940b0 RE |
3631 | enum machine_mode mode; |
3632 | { | |
3633 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3634 | return 0; | |
3635 | ||
3636 | if (GET_CODE (op) == SUBREG) | |
f3bb6135 | 3637 | op = SUBREG_REG (op); |
ff9940b0 RE |
3638 | |
3639 | /* We don't consider registers whose class is NO_REGS | |
3640 | to be a register operand. */ | |
d5b7b3ae | 3641 | /* XXX might have to check for lo regs only for thumb ??? */ |
ff9940b0 RE |
3642 | return (GET_CODE (op) == REG |
3643 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3644 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
3645 | } | |
3646 | ||
b0888988 | 3647 | /* A hard register operand (even before reload. */ |
1d6e90ac | 3648 | |
b0888988 RE |
3649 | int |
3650 | arm_hard_register_operand (op, mode) | |
1d6e90ac | 3651 | rtx op; |
b0888988 RE |
3652 | enum machine_mode mode; |
3653 | { | |
3654 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3655 | return 0; | |
3656 | ||
3657 | return (GET_CODE (op) == REG | |
3658 | && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
3659 | } | |
3660 | ||
e2c671ba RE |
3661 | /* Only accept reg, subreg(reg), const_int. */ |
3662 | ||
3663 | int | |
3664 | reg_or_int_operand (op, mode) | |
1d6e90ac | 3665 | rtx op; |
e2c671ba RE |
3666 | enum machine_mode mode; |
3667 | { | |
3668 | if (GET_CODE (op) == CONST_INT) | |
3669 | return 1; | |
3670 | ||
3671 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3672 | return 0; | |
3673 | ||
3674 | if (GET_CODE (op) == SUBREG) | |
3675 | op = SUBREG_REG (op); | |
3676 | ||
3677 | /* We don't consider registers whose class is NO_REGS | |
3678 | to be a register operand. */ | |
3679 | return (GET_CODE (op) == REG | |
3680 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3681 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
3682 | } | |
3683 | ||
ff9940b0 RE |
3684 | /* Return 1 if OP is an item in memory, given that we are in reload. */ |
3685 | ||
3686 | int | |
d5b7b3ae | 3687 | arm_reload_memory_operand (op, mode) |
ff9940b0 | 3688 | rtx op; |
74bbc178 | 3689 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ff9940b0 RE |
3690 | { |
3691 | int regno = true_regnum (op); | |
3692 | ||
5895f793 | 3693 | return (!CONSTANT_P (op) |
ff9940b0 RE |
3694 | && (regno == -1 |
3695 | || (GET_CODE (op) == REG | |
3696 | && REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
3697 | } | |
3698 | ||
4d818c85 | 3699 | /* Return 1 if OP is a valid memory address, but not valid for a signed byte |
d5b7b3ae | 3700 | memory access (architecture V4). |
f710504c | 3701 | MODE is QImode if called when computing constraints, or VOIDmode when |
d5b7b3ae | 3702 | emitting patterns. In this latter case we cannot use memory_operand() |
6bc82793 | 3703 | because it will fail on badly formed MEMs, which is precisely what we are |
d5b7b3ae | 3704 | trying to catch. */ |
1d6e90ac | 3705 | |
4d818c85 RE |
3706 | int |
3707 | bad_signed_byte_operand (op, mode) | |
3708 | rtx op; | |
d5b7b3ae | 3709 | enum machine_mode mode ATTRIBUTE_UNUSED; |
4d818c85 | 3710 | { |
d5b7b3ae | 3711 | #if 0 |
5895f793 | 3712 | if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM) |
d5b7b3ae RE |
3713 | return 0; |
3714 | #endif | |
3715 | if (GET_CODE (op) != MEM) | |
4d818c85 RE |
3716 | return 0; |
3717 | ||
3718 | op = XEXP (op, 0); | |
3719 | ||
6354dc9b | 3720 | /* A sum of anything more complex than reg + reg or reg + const is bad. */ |
4d818c85 | 3721 | if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) |
5895f793 RE |
3722 | && (!s_register_operand (XEXP (op, 0), VOIDmode) |
3723 | || (!s_register_operand (XEXP (op, 1), VOIDmode) | |
9c8cc54f | 3724 | && GET_CODE (XEXP (op, 1)) != CONST_INT))) |
4d818c85 RE |
3725 | return 1; |
3726 | ||
6354dc9b | 3727 | /* Big constants are also bad. */ |
4d818c85 RE |
3728 | if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT |
3729 | && (INTVAL (XEXP (op, 1)) > 0xff | |
3730 | || -INTVAL (XEXP (op, 1)) > 0xff)) | |
3731 | return 1; | |
3732 | ||
6354dc9b | 3733 | /* Everything else is good, or can will automatically be made so. */ |
4d818c85 RE |
3734 | return 0; |
3735 | } | |
3736 | ||
cce8749e CH |
3737 | /* Return TRUE for valid operands for the rhs of an ARM instruction. */ |
3738 | ||
3739 | int | |
3740 | arm_rhs_operand (op, mode) | |
3741 | rtx op; | |
3742 | enum machine_mode mode; | |
3743 | { | |
ff9940b0 | 3744 | return (s_register_operand (op, mode) |
cce8749e | 3745 | || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))); |
f3bb6135 | 3746 | } |
cce8749e | 3747 | |
1d6e90ac NC |
3748 | /* Return TRUE for valid operands for the |
3749 | rhs of an ARM instruction, or a load. */ | |
ff9940b0 RE |
3750 | |
3751 | int | |
3752 | arm_rhsm_operand (op, mode) | |
3753 | rtx op; | |
3754 | enum machine_mode mode; | |
3755 | { | |
3756 | return (s_register_operand (op, mode) | |
3757 | || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))) | |
3758 | || memory_operand (op, mode)); | |
f3bb6135 | 3759 | } |
ff9940b0 RE |
3760 | |
3761 | /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a | |
3762 | constant that is valid when negated. */ | |
3763 | ||
3764 | int | |
3765 | arm_add_operand (op, mode) | |
3766 | rtx op; | |
3767 | enum machine_mode mode; | |
3768 | { | |
d5b7b3ae RE |
3769 | if (TARGET_THUMB) |
3770 | return thumb_cmp_operand (op, mode); | |
3771 | ||
ff9940b0 RE |
3772 | return (s_register_operand (op, mode) |
3773 | || (GET_CODE (op) == CONST_INT | |
3774 | && (const_ok_for_arm (INTVAL (op)) | |
3775 | || const_ok_for_arm (-INTVAL (op))))); | |
f3bb6135 | 3776 | } |
ff9940b0 RE |
3777 | |
3778 | int | |
3779 | arm_not_operand (op, mode) | |
3780 | rtx op; | |
3781 | enum machine_mode mode; | |
3782 | { | |
3783 | return (s_register_operand (op, mode) | |
3784 | || (GET_CODE (op) == CONST_INT | |
3785 | && (const_ok_for_arm (INTVAL (op)) | |
3786 | || const_ok_for_arm (~INTVAL (op))))); | |
f3bb6135 | 3787 | } |
ff9940b0 | 3788 | |
5165176d RE |
3789 | /* Return TRUE if the operand is a memory reference which contains an |
3790 | offsettable address. */ | |
1d6e90ac | 3791 | |
5165176d RE |
3792 | int |
3793 | offsettable_memory_operand (op, mode) | |
1d6e90ac | 3794 | rtx op; |
5165176d RE |
3795 | enum machine_mode mode; |
3796 | { | |
3797 | if (mode == VOIDmode) | |
3798 | mode = GET_MODE (op); | |
3799 | ||
3800 | return (mode == GET_MODE (op) | |
3801 | && GET_CODE (op) == MEM | |
3802 | && offsettable_address_p (reload_completed | reload_in_progress, | |
3803 | mode, XEXP (op, 0))); | |
3804 | } | |
3805 | ||
3806 | /* Return TRUE if the operand is a memory reference which is, or can be | |
3807 | made word aligned by adjusting the offset. */ | |
1d6e90ac | 3808 | |
5165176d RE |
3809 | int |
3810 | alignable_memory_operand (op, mode) | |
1d6e90ac | 3811 | rtx op; |
5165176d RE |
3812 | enum machine_mode mode; |
3813 | { | |
3814 | rtx reg; | |
3815 | ||
3816 | if (mode == VOIDmode) | |
3817 | mode = GET_MODE (op); | |
3818 | ||
3819 | if (mode != GET_MODE (op) || GET_CODE (op) != MEM) | |
3820 | return 0; | |
3821 | ||
3822 | op = XEXP (op, 0); | |
3823 | ||
3824 | return ((GET_CODE (reg = op) == REG | |
3825 | || (GET_CODE (op) == SUBREG | |
3826 | && GET_CODE (reg = SUBREG_REG (op)) == REG) | |
3827 | || (GET_CODE (op) == PLUS | |
3828 | && GET_CODE (XEXP (op, 1)) == CONST_INT | |
3829 | && (GET_CODE (reg = XEXP (op, 0)) == REG | |
3830 | || (GET_CODE (XEXP (op, 0)) == SUBREG | |
3831 | && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG)))) | |
bdb429a5 | 3832 | && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32); |
5165176d RE |
3833 | } |
3834 | ||
b111229a RE |
3835 | /* Similar to s_register_operand, but does not allow hard integer |
3836 | registers. */ | |
1d6e90ac | 3837 | |
b111229a RE |
3838 | int |
3839 | f_register_operand (op, mode) | |
1d6e90ac | 3840 | rtx op; |
b111229a RE |
3841 | enum machine_mode mode; |
3842 | { | |
3843 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3844 | return 0; | |
3845 | ||
3846 | if (GET_CODE (op) == SUBREG) | |
3847 | op = SUBREG_REG (op); | |
3848 | ||
3849 | /* We don't consider registers whose class is NO_REGS | |
3850 | to be a register operand. */ | |
3851 | return (GET_CODE (op) == REG | |
3852 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3b684012 | 3853 | || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); |
b111229a RE |
3854 | } |
3855 | ||
3b684012 | 3856 | /* Return TRUE for valid operands for the rhs of an FPA instruction. */ |
cce8749e CH |
3857 | |
3858 | int | |
3b684012 | 3859 | fpa_rhs_operand (op, mode) |
cce8749e CH |
3860 | rtx op; |
3861 | enum machine_mode mode; | |
3862 | { | |
ff9940b0 | 3863 | if (s_register_operand (op, mode)) |
f3bb6135 | 3864 | return TRUE; |
9ce71c6f BS |
3865 | |
3866 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3867 | return FALSE; | |
3868 | ||
3869 | if (GET_CODE (op) == CONST_DOUBLE) | |
3b684012 | 3870 | return const_double_rtx_ok_for_fpa (op); |
f3bb6135 RE |
3871 | |
3872 | return FALSE; | |
3873 | } | |
cce8749e | 3874 | |
ff9940b0 | 3875 | int |
3b684012 | 3876 | fpa_add_operand (op, mode) |
ff9940b0 RE |
3877 | rtx op; |
3878 | enum machine_mode mode; | |
3879 | { | |
3880 | if (s_register_operand (op, mode)) | |
f3bb6135 | 3881 | return TRUE; |
9ce71c6f BS |
3882 | |
3883 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3884 | return FALSE; | |
3885 | ||
3886 | if (GET_CODE (op) == CONST_DOUBLE) | |
3b684012 RE |
3887 | return (const_double_rtx_ok_for_fpa (op) |
3888 | || neg_const_double_rtx_ok_for_fpa (op)); | |
f3bb6135 RE |
3889 | |
3890 | return FALSE; | |
ff9940b0 RE |
3891 | } |
3892 | ||
9b6b54e2 NC |
3893 | /* Return nonzero if OP is a valid Cirrus memory address pattern. */ |
3894 | ||
3895 | int | |
3896 | cirrus_memory_offset (op) | |
3897 | rtx op; | |
3898 | { | |
3899 | /* Reject eliminable registers. */ | |
3900 | if (! (reload_in_progress || reload_completed) | |
3901 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
3902 | || reg_mentioned_p (arg_pointer_rtx, op) | |
3903 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
3904 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
3905 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
3906 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
3907 | return 0; | |
3908 | ||
3909 | if (GET_CODE (op) == MEM) | |
3910 | { | |
3911 | rtx ind; | |
3912 | ||
3913 | ind = XEXP (op, 0); | |
3914 | ||
3915 | /* Match: (mem (reg)). */ | |
3916 | if (GET_CODE (ind) == REG) | |
3917 | return 1; | |
3918 | ||
3919 | /* Match: | |
3920 | (mem (plus (reg) | |
3921 | (const))). */ | |
3922 | if (GET_CODE (ind) == PLUS | |
3923 | && GET_CODE (XEXP (ind, 0)) == REG | |
3924 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
3925 | && GET_CODE (XEXP (ind, 1)) == CONST_INT) | |
3926 | return 1; | |
3927 | } | |
3928 | ||
3929 | return 0; | |
3930 | } | |
3931 | ||
3932 | /* Return nonzero if OP is a Cirrus or general register. */ | |
3933 | ||
3934 | int | |
3935 | cirrus_register_operand (op, mode) | |
3936 | rtx op; | |
3937 | enum machine_mode mode; | |
3938 | { | |
3939 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3940 | return FALSE; | |
3941 | ||
3942 | if (GET_CODE (op) == SUBREG) | |
3943 | op = SUBREG_REG (op); | |
3944 | ||
3945 | return (GET_CODE (op) == REG | |
3946 | && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS | |
3947 | || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS)); | |
3948 | } | |
3949 | ||
3950 | /* Return nonzero if OP is a cirrus FP register. */ | |
3951 | ||
3952 | int | |
3953 | cirrus_fp_register (op, mode) | |
3954 | rtx op; | |
3955 | enum machine_mode mode; | |
3956 | { | |
3957 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3958 | return FALSE; | |
3959 | ||
3960 | if (GET_CODE (op) == SUBREG) | |
3961 | op = SUBREG_REG (op); | |
3962 | ||
3963 | return (GET_CODE (op) == REG | |
3964 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3965 | || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS)); | |
3966 | } | |
3967 | ||
3968 | /* Return nonzero if OP is a 6bit constant (0..63). */ | |
3969 | ||
3970 | int | |
3971 | cirrus_shift_const (op, mode) | |
3972 | rtx op; | |
3973 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3974 | { | |
3975 | return (GET_CODE (op) == CONST_INT | |
3976 | && INTVAL (op) >= 0 | |
3977 | && INTVAL (op) < 64); | |
3978 | } | |
3979 | ||
f0375c66 NC |
3980 | /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. |
3981 | Use by the Cirrus Maverick code which has to workaround | |
3982 | a hardware bug triggered by such instructions. */ | |
9b6b54e2 | 3983 | |
f0375c66 NC |
3984 | static bool |
3985 | arm_memory_load_p (insn) | |
9b6b54e2 NC |
3986 | rtx insn; |
3987 | { | |
3988 | rtx body, lhs, rhs;; | |
3989 | ||
f0375c66 NC |
3990 | if (insn == NULL_RTX || GET_CODE (insn) != INSN) |
3991 | return false; | |
9b6b54e2 NC |
3992 | |
3993 | body = PATTERN (insn); | |
3994 | ||
3995 | if (GET_CODE (body) != SET) | |
f0375c66 | 3996 | return false; |
9b6b54e2 NC |
3997 | |
3998 | lhs = XEXP (body, 0); | |
3999 | rhs = XEXP (body, 1); | |
4000 | ||
f0375c66 NC |
4001 | lhs = REG_OR_SUBREG_RTX (lhs); |
4002 | ||
4003 | /* If the destination is not a general purpose | |
4004 | register we do not have to worry. */ | |
4005 | if (GET_CODE (lhs) != REG | |
4006 | || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) | |
4007 | return false; | |
4008 | ||
4009 | /* As well as loads from memory we also have to react | |
4010 | to loads of invalid constants which will be turned | |
4011 | into loads from the minipool. */ | |
4012 | return (GET_CODE (rhs) == MEM | |
4013 | || GET_CODE (rhs) == SYMBOL_REF | |
4014 | || note_invalid_constants (insn, -1, false)); | |
9b6b54e2 NC |
4015 | } |
4016 | ||
f0375c66 | 4017 | /* Return TRUE if INSN is a Cirrus instruction. */ |
9b6b54e2 | 4018 | |
f0375c66 NC |
4019 | static bool |
4020 | arm_cirrus_insn_p (insn) | |
9b6b54e2 NC |
4021 | rtx insn; |
4022 | { | |
4023 | enum attr_cirrus attr; | |
4024 | ||
4025 | /* get_attr aborts on USE and CLOBBER. */ | |
4026 | if (!insn | |
4027 | || GET_CODE (insn) != INSN | |
4028 | || GET_CODE (PATTERN (insn)) == USE | |
4029 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
4030 | return 0; | |
4031 | ||
4032 | attr = get_attr_cirrus (insn); | |
4033 | ||
f0375c66 | 4034 | return attr != CIRRUS_NOT; |
9b6b54e2 NC |
4035 | } |
4036 | ||
4037 | /* Cirrus reorg for invalid instruction combinations. */ | |
4038 | ||
4039 | static void | |
4040 | cirrus_reorg (first) | |
4041 | rtx first; | |
4042 | { | |
4043 | enum attr_cirrus attr; | |
4044 | rtx body = PATTERN (first); | |
4045 | rtx t; | |
4046 | int nops; | |
4047 | ||
4048 | /* Any branch must be followed by 2 non Cirrus instructions. */ | |
4049 | if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) | |
4050 | { | |
4051 | nops = 0; | |
4052 | t = next_nonnote_insn (first); | |
4053 | ||
f0375c66 | 4054 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
4055 | ++ nops; |
4056 | ||
f0375c66 | 4057 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
4058 | ++ nops; |
4059 | ||
4060 | while (nops --) | |
4061 | emit_insn_after (gen_nop (), first); | |
4062 | ||
4063 | return; | |
4064 | } | |
4065 | ||
4066 | /* (float (blah)) is in parallel with a clobber. */ | |
4067 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
4068 | body = XVECEXP (body, 0, 0); | |
4069 | ||
4070 | if (GET_CODE (body) == SET) | |
4071 | { | |
4072 | rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); | |
4073 | ||
4074 | /* cfldrd, cfldr64, cfstrd, cfstr64 must | |
4075 | be followed by a non Cirrus insn. */ | |
4076 | if (get_attr_cirrus (first) == CIRRUS_DOUBLE) | |
4077 | { | |
f0375c66 | 4078 | if (arm_cirrus_insn_p (next_nonnote_insn (first))) |
9b6b54e2 NC |
4079 | emit_insn_after (gen_nop (), first); |
4080 | ||
4081 | return; | |
4082 | } | |
f0375c66 | 4083 | else if (arm_memory_load_p (first)) |
9b6b54e2 NC |
4084 | { |
4085 | unsigned int arm_regno; | |
4086 | ||
4087 | /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, | |
4088 | ldr/cfmv64hr combination where the Rd field is the same | |
4089 | in both instructions must be split with a non Cirrus | |
4090 | insn. Example: | |
4091 | ||
4092 | ldr r0, blah | |
4093 | nop | |
4094 | cfmvsr mvf0, r0. */ | |
4095 | ||
4096 | /* Get Arm register number for ldr insn. */ | |
4097 | if (GET_CODE (lhs) == REG) | |
4098 | arm_regno = REGNO (lhs); | |
4099 | else if (GET_CODE (rhs) == REG) | |
4100 | arm_regno = REGNO (rhs); | |
4101 | else | |
4102 | abort (); | |
4103 | ||
4104 | /* Next insn. */ | |
4105 | first = next_nonnote_insn (first); | |
4106 | ||
f0375c66 | 4107 | if (! arm_cirrus_insn_p (first)) |
9b6b54e2 NC |
4108 | return; |
4109 | ||
4110 | body = PATTERN (first); | |
4111 | ||
4112 | /* (float (blah)) is in parallel with a clobber. */ | |
4113 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) | |
4114 | body = XVECEXP (body, 0, 0); | |
4115 | ||
4116 | if (GET_CODE (body) == FLOAT) | |
4117 | body = XEXP (body, 0); | |
4118 | ||
4119 | if (get_attr_cirrus (first) == CIRRUS_MOVE | |
4120 | && GET_CODE (XEXP (body, 1)) == REG | |
4121 | && arm_regno == REGNO (XEXP (body, 1))) | |
4122 | emit_insn_after (gen_nop (), first); | |
4123 | ||
4124 | return; | |
4125 | } | |
4126 | } | |
4127 | ||
4128 | /* get_attr aborts on USE and CLOBBER. */ | |
4129 | if (!first | |
4130 | || GET_CODE (first) != INSN | |
4131 | || GET_CODE (PATTERN (first)) == USE | |
4132 | || GET_CODE (PATTERN (first)) == CLOBBER) | |
4133 | return; | |
4134 | ||
4135 | attr = get_attr_cirrus (first); | |
4136 | ||
4137 | /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) | |
4138 | must be followed by a non-coprocessor instruction. */ | |
4139 | if (attr == CIRRUS_COMPARE) | |
4140 | { | |
4141 | nops = 0; | |
4142 | ||
4143 | t = next_nonnote_insn (first); | |
4144 | ||
f0375c66 | 4145 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
4146 | ++ nops; |
4147 | ||
f0375c66 | 4148 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
4149 | ++ nops; |
4150 | ||
4151 | while (nops --) | |
4152 | emit_insn_after (gen_nop (), first); | |
4153 | ||
4154 | return; | |
4155 | } | |
4156 | } | |
4157 | ||
cce8749e CH |
4158 | /* Return nonzero if OP is a constant power of two. */ |
4159 | ||
4160 | int | |
4161 | power_of_two_operand (op, mode) | |
4162 | rtx op; | |
74bbc178 | 4163 | enum machine_mode mode ATTRIBUTE_UNUSED; |
cce8749e CH |
4164 | { |
4165 | if (GET_CODE (op) == CONST_INT) | |
4166 | { | |
d5b7b3ae | 4167 | HOST_WIDE_INT value = INTVAL (op); |
1d6e90ac | 4168 | |
f3bb6135 | 4169 | return value != 0 && (value & (value - 1)) == 0; |
cce8749e | 4170 | } |
1d6e90ac | 4171 | |
f3bb6135 RE |
4172 | return FALSE; |
4173 | } | |
cce8749e CH |
4174 | |
4175 | /* Return TRUE for a valid operand of a DImode operation. | |
e9c6b69b | 4176 | Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). |
ff9940b0 RE |
4177 | Note that this disallows MEM(REG+REG), but allows |
4178 | MEM(PRE/POST_INC/DEC(REG)). */ | |
cce8749e CH |
4179 | |
4180 | int | |
4181 | di_operand (op, mode) | |
4182 | rtx op; | |
4183 | enum machine_mode mode; | |
4184 | { | |
ff9940b0 | 4185 | if (s_register_operand (op, mode)) |
f3bb6135 | 4186 | return TRUE; |
cce8749e | 4187 | |
9ce71c6f BS |
4188 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) |
4189 | return FALSE; | |
4190 | ||
e9c6b69b NC |
4191 | if (GET_CODE (op) == SUBREG) |
4192 | op = SUBREG_REG (op); | |
4193 | ||
cce8749e CH |
4194 | switch (GET_CODE (op)) |
4195 | { | |
4196 | case CONST_DOUBLE: | |
4197 | case CONST_INT: | |
f3bb6135 RE |
4198 | return TRUE; |
4199 | ||
cce8749e | 4200 | case MEM: |
f3bb6135 RE |
4201 | return memory_address_p (DImode, XEXP (op, 0)); |
4202 | ||
cce8749e | 4203 | default: |
f3bb6135 | 4204 | return FALSE; |
cce8749e | 4205 | } |
f3bb6135 | 4206 | } |
cce8749e | 4207 | |
d5b7b3ae | 4208 | /* Like di_operand, but don't accept constants. */ |
1d6e90ac | 4209 | |
d5b7b3ae RE |
4210 | int |
4211 | nonimmediate_di_operand (op, mode) | |
4212 | rtx op; | |
4213 | enum machine_mode mode; | |
4214 | { | |
4215 | if (s_register_operand (op, mode)) | |
4216 | return TRUE; | |
4217 | ||
4218 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) | |
4219 | return FALSE; | |
4220 | ||
4221 | if (GET_CODE (op) == SUBREG) | |
4222 | op = SUBREG_REG (op); | |
4223 | ||
4224 | if (GET_CODE (op) == MEM) | |
4225 | return memory_address_p (DImode, XEXP (op, 0)); | |
4226 | ||
4227 | return FALSE; | |
4228 | } | |
4229 | ||
f3139301 | 4230 | /* Return TRUE for a valid operand of a DFmode operation when -msoft-float. |
e9c6b69b | 4231 | Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). |
f3139301 DE |
4232 | Note that this disallows MEM(REG+REG), but allows |
4233 | MEM(PRE/POST_INC/DEC(REG)). */ | |
4234 | ||
4235 | int | |
4236 | soft_df_operand (op, mode) | |
4237 | rtx op; | |
4238 | enum machine_mode mode; | |
4239 | { | |
4240 | if (s_register_operand (op, mode)) | |
4b02997f | 4241 | return TRUE; |
f3139301 | 4242 | |
9ce71c6f BS |
4243 | if (mode != VOIDmode && GET_MODE (op) != mode) |
4244 | return FALSE; | |
4245 | ||
37b80d2e BS |
4246 | if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op))) |
4247 | return FALSE; | |
4248 | ||
e9c6b69b NC |
4249 | if (GET_CODE (op) == SUBREG) |
4250 | op = SUBREG_REG (op); | |
9ce71c6f | 4251 | |
f3139301 DE |
4252 | switch (GET_CODE (op)) |
4253 | { | |
4254 | case CONST_DOUBLE: | |
4255 | return TRUE; | |
4256 | ||
4257 | case MEM: | |
4258 | return memory_address_p (DFmode, XEXP (op, 0)); | |
4259 | ||
4260 | default: | |
4261 | return FALSE; | |
4262 | } | |
4263 | } | |
4264 | ||
d5b7b3ae | 4265 | /* Like soft_df_operand, but don't accept constants. */ |
1d6e90ac | 4266 | |
d5b7b3ae RE |
4267 | int |
4268 | nonimmediate_soft_df_operand (op, mode) | |
4269 | rtx op; | |
4270 | enum machine_mode mode; | |
4271 | { | |
4272 | if (s_register_operand (op, mode)) | |
4b02997f | 4273 | return TRUE; |
d5b7b3ae RE |
4274 | |
4275 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
4276 | return FALSE; | |
4277 | ||
4278 | if (GET_CODE (op) == SUBREG) | |
4279 | op = SUBREG_REG (op); | |
4280 | ||
4281 | if (GET_CODE (op) == MEM) | |
4282 | return memory_address_p (DFmode, XEXP (op, 0)); | |
4283 | return FALSE; | |
4284 | } | |
cce8749e | 4285 | |
d5b7b3ae | 4286 | /* Return TRUE for valid index operands. */ |
1d6e90ac | 4287 | |
cce8749e CH |
4288 | int |
4289 | index_operand (op, mode) | |
4290 | rtx op; | |
4291 | enum machine_mode mode; | |
4292 | { | |
d5b7b3ae | 4293 | return (s_register_operand (op, mode) |
ff9940b0 | 4294 | || (immediate_operand (op, mode) |
d5b7b3ae RE |
4295 | && (GET_CODE (op) != CONST_INT |
4296 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096)))); | |
f3bb6135 | 4297 | } |
cce8749e | 4298 | |
ff9940b0 RE |
4299 | /* Return TRUE for valid shifts by a constant. This also accepts any |
4300 | power of two on the (somewhat overly relaxed) assumption that the | |
6354dc9b | 4301 | shift operator in this case was a mult. */ |
ff9940b0 RE |
4302 | |
4303 | int | |
4304 | const_shift_operand (op, mode) | |
4305 | rtx op; | |
4306 | enum machine_mode mode; | |
4307 | { | |
4308 | return (power_of_two_operand (op, mode) | |
4309 | || (immediate_operand (op, mode) | |
d5b7b3ae RE |
4310 | && (GET_CODE (op) != CONST_INT |
4311 | || (INTVAL (op) < 32 && INTVAL (op) > 0)))); | |
f3bb6135 | 4312 | } |
ff9940b0 | 4313 | |
cce8749e CH |
4314 | /* Return TRUE for arithmetic operators which can be combined with a multiply |
4315 | (shift). */ | |
4316 | ||
4317 | int | |
4318 | shiftable_operator (x, mode) | |
4319 | rtx x; | |
4320 | enum machine_mode mode; | |
4321 | { | |
1d6e90ac NC |
4322 | enum rtx_code code; |
4323 | ||
cce8749e CH |
4324 | if (GET_MODE (x) != mode) |
4325 | return FALSE; | |
cce8749e | 4326 | |
1d6e90ac NC |
4327 | code = GET_CODE (x); |
4328 | ||
4329 | return (code == PLUS || code == MINUS | |
4330 | || code == IOR || code == XOR || code == AND); | |
f3bb6135 | 4331 | } |
cce8749e | 4332 | |
6ab589e0 JL |
4333 | /* Return TRUE for binary logical operators. */ |
4334 | ||
4335 | int | |
4336 | logical_binary_operator (x, mode) | |
4337 | rtx x; | |
4338 | enum machine_mode mode; | |
4339 | { | |
1d6e90ac NC |
4340 | enum rtx_code code; |
4341 | ||
6ab589e0 JL |
4342 | if (GET_MODE (x) != mode) |
4343 | return FALSE; | |
6ab589e0 | 4344 | |
1d6e90ac NC |
4345 | code = GET_CODE (x); |
4346 | ||
4347 | return (code == IOR || code == XOR || code == AND); | |
6ab589e0 JL |
4348 | } |
4349 | ||
6354dc9b | 4350 | /* Return TRUE for shift operators. */ |
cce8749e CH |
4351 | |
4352 | int | |
4353 | shift_operator (x, mode) | |
4354 | rtx x; | |
4355 | enum machine_mode mode; | |
4356 | { | |
1d6e90ac NC |
4357 | enum rtx_code code; |
4358 | ||
cce8749e CH |
4359 | if (GET_MODE (x) != mode) |
4360 | return FALSE; | |
cce8749e | 4361 | |
1d6e90ac | 4362 | code = GET_CODE (x); |
f3bb6135 | 4363 | |
1d6e90ac NC |
4364 | if (code == MULT) |
4365 | return power_of_two_operand (XEXP (x, 1), mode); | |
4366 | ||
4367 | return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT | |
4368 | || code == ROTATERT); | |
f3bb6135 | 4369 | } |
ff9940b0 | 4370 | |
6354dc9b | 4371 | /* Return TRUE if x is EQ or NE. */ |
1d6e90ac | 4372 | |
6354dc9b NC |
4373 | int |
4374 | equality_operator (x, mode) | |
f3bb6135 | 4375 | rtx x; |
74bbc178 | 4376 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ff9940b0 | 4377 | { |
f3bb6135 | 4378 | return GET_CODE (x) == EQ || GET_CODE (x) == NE; |
ff9940b0 RE |
4379 | } |
4380 | ||
e45b72c4 | 4381 | /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */ |
1d6e90ac | 4382 | |
e45b72c4 RE |
4383 | int |
4384 | arm_comparison_operator (x, mode) | |
4385 | rtx x; | |
4386 | enum machine_mode mode; | |
4387 | { | |
4388 | return (comparison_operator (x, mode) | |
4389 | && GET_CODE (x) != LTGT | |
4390 | && GET_CODE (x) != UNEQ); | |
4391 | } | |
4392 | ||
6354dc9b | 4393 | /* Return TRUE for SMIN SMAX UMIN UMAX operators. */ |
1d6e90ac | 4394 | |
ff9940b0 RE |
4395 | int |
4396 | minmax_operator (x, mode) | |
4397 | rtx x; | |
4398 | enum machine_mode mode; | |
4399 | { | |
4400 | enum rtx_code code = GET_CODE (x); | |
4401 | ||
4402 | if (GET_MODE (x) != mode) | |
4403 | return FALSE; | |
f3bb6135 | 4404 | |
ff9940b0 | 4405 | return code == SMIN || code == SMAX || code == UMIN || code == UMAX; |
f3bb6135 | 4406 | } |
ff9940b0 | 4407 | |
ff9940b0 | 4408 | /* Return TRUE if this is the condition code register, if we aren't given |
6354dc9b | 4409 | a mode, accept any class CCmode register. */ |
1d6e90ac | 4410 | |
ff9940b0 RE |
4411 | int |
4412 | cc_register (x, mode) | |
f3bb6135 RE |
4413 | rtx x; |
4414 | enum machine_mode mode; | |
ff9940b0 RE |
4415 | { |
4416 | if (mode == VOIDmode) | |
4417 | { | |
4418 | mode = GET_MODE (x); | |
d5b7b3ae | 4419 | |
ff9940b0 RE |
4420 | if (GET_MODE_CLASS (mode) != MODE_CC) |
4421 | return FALSE; | |
4422 | } | |
f3bb6135 | 4423 | |
d5b7b3ae RE |
4424 | if ( GET_MODE (x) == mode |
4425 | && GET_CODE (x) == REG | |
4426 | && REGNO (x) == CC_REGNUM) | |
ff9940b0 | 4427 | return TRUE; |
f3bb6135 | 4428 | |
ff9940b0 RE |
4429 | return FALSE; |
4430 | } | |
5bbe2d40 RE |
4431 | |
4432 | /* Return TRUE if this is the condition code register, if we aren't given | |
84ed5e79 RE |
4433 | a mode, accept any class CCmode register which indicates a dominance |
4434 | expression. */ | |
1d6e90ac | 4435 | |
5bbe2d40 | 4436 | int |
84ed5e79 | 4437 | dominant_cc_register (x, mode) |
5bbe2d40 RE |
4438 | rtx x; |
4439 | enum machine_mode mode; | |
4440 | { | |
4441 | if (mode == VOIDmode) | |
4442 | { | |
4443 | mode = GET_MODE (x); | |
d5b7b3ae | 4444 | |
84ed5e79 | 4445 | if (GET_MODE_CLASS (mode) != MODE_CC) |
5bbe2d40 RE |
4446 | return FALSE; |
4447 | } | |
4448 | ||
d5b7b3ae | 4449 | if ( mode != CC_DNEmode && mode != CC_DEQmode |
84ed5e79 RE |
4450 | && mode != CC_DLEmode && mode != CC_DLTmode |
4451 | && mode != CC_DGEmode && mode != CC_DGTmode | |
4452 | && mode != CC_DLEUmode && mode != CC_DLTUmode | |
4453 | && mode != CC_DGEUmode && mode != CC_DGTUmode) | |
4454 | return FALSE; | |
4455 | ||
d5b7b3ae | 4456 | return cc_register (x, mode); |
5bbe2d40 RE |
4457 | } |
4458 | ||
2b835d68 | 4459 | /* Return TRUE if X references a SYMBOL_REF. */ |
1d6e90ac | 4460 | |
2b835d68 RE |
4461 | int |
4462 | symbol_mentioned_p (x) | |
4463 | rtx x; | |
4464 | { | |
1d6e90ac NC |
4465 | const char * fmt; |
4466 | int i; | |
2b835d68 RE |
4467 | |
4468 | if (GET_CODE (x) == SYMBOL_REF) | |
4469 | return 1; | |
4470 | ||
4471 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
d5b7b3ae | 4472 | |
2b835d68 RE |
4473 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
4474 | { | |
4475 | if (fmt[i] == 'E') | |
4476 | { | |
1d6e90ac | 4477 | int j; |
2b835d68 RE |
4478 | |
4479 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4480 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
4481 | return 1; | |
4482 | } | |
4483 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
4484 | return 1; | |
4485 | } | |
4486 | ||
4487 | return 0; | |
4488 | } | |
4489 | ||
4490 | /* Return TRUE if X references a LABEL_REF. */ | |
1d6e90ac | 4491 | |
2b835d68 RE |
4492 | int |
4493 | label_mentioned_p (x) | |
4494 | rtx x; | |
4495 | { | |
1d6e90ac NC |
4496 | const char * fmt; |
4497 | int i; | |
2b835d68 RE |
4498 | |
4499 | if (GET_CODE (x) == LABEL_REF) | |
4500 | return 1; | |
4501 | ||
4502 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
4503 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
4504 | { | |
4505 | if (fmt[i] == 'E') | |
4506 | { | |
1d6e90ac | 4507 | int j; |
2b835d68 RE |
4508 | |
4509 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4510 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
4511 | return 1; | |
4512 | } | |
4513 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
4514 | return 1; | |
4515 | } | |
4516 | ||
4517 | return 0; | |
4518 | } | |
4519 | ||
ff9940b0 RE |
4520 | enum rtx_code |
4521 | minmax_code (x) | |
f3bb6135 | 4522 | rtx x; |
ff9940b0 RE |
4523 | { |
4524 | enum rtx_code code = GET_CODE (x); | |
4525 | ||
4526 | if (code == SMAX) | |
4527 | return GE; | |
f3bb6135 | 4528 | else if (code == SMIN) |
ff9940b0 | 4529 | return LE; |
f3bb6135 | 4530 | else if (code == UMIN) |
ff9940b0 | 4531 | return LEU; |
f3bb6135 | 4532 | else if (code == UMAX) |
ff9940b0 | 4533 | return GEU; |
f3bb6135 | 4534 | |
ff9940b0 RE |
4535 | abort (); |
4536 | } | |
4537 | ||
6354dc9b | 4538 | /* Return 1 if memory locations are adjacent. */ |
1d6e90ac | 4539 | |
f3bb6135 | 4540 | int |
ff9940b0 RE |
4541 | adjacent_mem_locations (a, b) |
4542 | rtx a, b; | |
4543 | { | |
ff9940b0 RE |
4544 | if ((GET_CODE (XEXP (a, 0)) == REG |
4545 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
4546 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
4547 | && (GET_CODE (XEXP (b, 0)) == REG | |
4548 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
4549 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
4550 | { | |
1d6e90ac NC |
4551 | int val0 = 0, val1 = 0; |
4552 | int reg0, reg1; | |
4553 | ||
ff9940b0 RE |
4554 | if (GET_CODE (XEXP (a, 0)) == PLUS) |
4555 | { | |
1d6e90ac | 4556 | reg0 = REGNO (XEXP (XEXP (a, 0), 0)); |
ff9940b0 RE |
4557 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); |
4558 | } | |
4559 | else | |
4560 | reg0 = REGNO (XEXP (a, 0)); | |
1d6e90ac | 4561 | |
ff9940b0 RE |
4562 | if (GET_CODE (XEXP (b, 0)) == PLUS) |
4563 | { | |
1d6e90ac | 4564 | reg1 = REGNO (XEXP (XEXP (b, 0), 0)); |
ff9940b0 RE |
4565 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); |
4566 | } | |
4567 | else | |
4568 | reg1 = REGNO (XEXP (b, 0)); | |
1d6e90ac | 4569 | |
ff9940b0 RE |
4570 | return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4); |
4571 | } | |
4572 | return 0; | |
4573 | } | |
4574 | ||
4575 | /* Return 1 if OP is a load multiple operation. It is known to be | |
6354dc9b | 4576 | parallel and the first section will be tested. */ |
1d6e90ac | 4577 | |
f3bb6135 | 4578 | int |
ff9940b0 RE |
4579 | load_multiple_operation (op, mode) |
4580 | rtx op; | |
74bbc178 | 4581 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ff9940b0 | 4582 | { |
f3bb6135 | 4583 | HOST_WIDE_INT count = XVECLEN (op, 0); |
ff9940b0 RE |
4584 | int dest_regno; |
4585 | rtx src_addr; | |
f3bb6135 | 4586 | HOST_WIDE_INT i = 1, base = 0; |
ff9940b0 RE |
4587 | rtx elt; |
4588 | ||
4589 | if (count <= 1 | |
4590 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
4591 | return 0; | |
4592 | ||
6354dc9b | 4593 | /* Check to see if this might be a write-back. */ |
ff9940b0 RE |
4594 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) |
4595 | { | |
4596 | i++; | |
4597 | base = 1; | |
4598 | ||
6354dc9b | 4599 | /* Now check it more carefully. */ |
ff9940b0 RE |
4600 | if (GET_CODE (SET_DEST (elt)) != REG |
4601 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
4602 | || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) | |
4603 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
41e3f998 | 4604 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) |
ff9940b0 | 4605 | return 0; |
ff9940b0 RE |
4606 | } |
4607 | ||
4608 | /* Perform a quick check so we don't blow up below. */ | |
4609 | if (count <= i | |
4610 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
4611 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG | |
4612 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) | |
4613 | return 0; | |
4614 | ||
4615 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); | |
4616 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); | |
4617 | ||
4618 | for (; i < count; i++) | |
4619 | { | |
ed4c4348 | 4620 | elt = XVECEXP (op, 0, i); |
ff9940b0 RE |
4621 | |
4622 | if (GET_CODE (elt) != SET | |
4623 | || GET_CODE (SET_DEST (elt)) != REG | |
4624 | || GET_MODE (SET_DEST (elt)) != SImode | |
6354dc9b | 4625 | || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base) |
ff9940b0 RE |
4626 | || GET_CODE (SET_SRC (elt)) != MEM |
4627 | || GET_MODE (SET_SRC (elt)) != SImode | |
4628 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
5895f793 | 4629 | || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) |
ff9940b0 RE |
4630 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT |
4631 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) | |
4632 | return 0; | |
4633 | } | |
4634 | ||
4635 | return 1; | |
4636 | } | |
4637 | ||
4638 | /* Return 1 if OP is a store multiple operation. It is known to be | |
6354dc9b | 4639 | parallel and the first section will be tested. */ |
1d6e90ac | 4640 | |
f3bb6135 | 4641 | int |
ff9940b0 RE |
4642 | store_multiple_operation (op, mode) |
4643 | rtx op; | |
74bbc178 | 4644 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ff9940b0 | 4645 | { |
f3bb6135 | 4646 | HOST_WIDE_INT count = XVECLEN (op, 0); |
ff9940b0 RE |
4647 | int src_regno; |
4648 | rtx dest_addr; | |
f3bb6135 | 4649 | HOST_WIDE_INT i = 1, base = 0; |
ff9940b0 RE |
4650 | rtx elt; |
4651 | ||
4652 | if (count <= 1 | |
4653 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
4654 | return 0; | |
4655 | ||
6354dc9b | 4656 | /* Check to see if this might be a write-back. */ |
ff9940b0 RE |
4657 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) |
4658 | { | |
4659 | i++; | |
4660 | base = 1; | |
4661 | ||
6354dc9b | 4662 | /* Now check it more carefully. */ |
ff9940b0 RE |
4663 | if (GET_CODE (SET_DEST (elt)) != REG |
4664 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
4665 | || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) | |
4666 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
41e3f998 | 4667 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) |
ff9940b0 | 4668 | return 0; |
ff9940b0 RE |
4669 | } |
4670 | ||
4671 | /* Perform a quick check so we don't blow up below. */ | |
4672 | if (count <= i | |
4673 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
4674 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM | |
4675 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) | |
4676 | return 0; | |
4677 | ||
4678 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); | |
4679 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); | |
4680 | ||
4681 | for (; i < count; i++) | |
4682 | { | |
4683 | elt = XVECEXP (op, 0, i); | |
4684 | ||
4685 | if (GET_CODE (elt) != SET | |
4686 | || GET_CODE (SET_SRC (elt)) != REG | |
4687 | || GET_MODE (SET_SRC (elt)) != SImode | |
6354dc9b | 4688 | || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base) |
ff9940b0 RE |
4689 | || GET_CODE (SET_DEST (elt)) != MEM |
4690 | || GET_MODE (SET_DEST (elt)) != SImode | |
4691 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
5895f793 | 4692 | || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) |
ff9940b0 RE |
4693 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT |
4694 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) | |
4695 | return 0; | |
4696 | } | |
4697 | ||
4698 | return 1; | |
4699 | } | |
e2c671ba | 4700 | |
84ed5e79 RE |
4701 | int |
4702 | load_multiple_sequence (operands, nops, regs, base, load_offset) | |
62b10bbc | 4703 | rtx * operands; |
84ed5e79 | 4704 | int nops; |
62b10bbc NC |
4705 | int * regs; |
4706 | int * base; | |
4707 | HOST_WIDE_INT * load_offset; | |
84ed5e79 RE |
4708 | { |
4709 | int unsorted_regs[4]; | |
4710 | HOST_WIDE_INT unsorted_offsets[4]; | |
4711 | int order[4]; | |
ad076f4e | 4712 | int base_reg = -1; |
84ed5e79 RE |
4713 | int i; |
4714 | ||
1d6e90ac NC |
4715 | /* Can only handle 2, 3, or 4 insns at present, |
4716 | though could be easily extended if required. */ | |
84ed5e79 RE |
4717 | if (nops < 2 || nops > 4) |
4718 | abort (); | |
4719 | ||
4720 | /* Loop over the operands and check that the memory references are | |
4721 | suitable (ie immediate offsets from the same base register). At | |
4722 | the same time, extract the target register, and the memory | |
4723 | offsets. */ | |
4724 | for (i = 0; i < nops; i++) | |
4725 | { | |
4726 | rtx reg; | |
4727 | rtx offset; | |
4728 | ||
56636818 JL |
4729 | /* Convert a subreg of a mem into the mem itself. */ |
4730 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 4731 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 4732 | |
84ed5e79 RE |
4733 | if (GET_CODE (operands[nops + i]) != MEM) |
4734 | abort (); | |
4735 | ||
4736 | /* Don't reorder volatile memory references; it doesn't seem worth | |
4737 | looking for the case where the order is ok anyway. */ | |
4738 | if (MEM_VOLATILE_P (operands[nops + i])) | |
4739 | return 0; | |
4740 | ||
4741 | offset = const0_rtx; | |
4742 | ||
4743 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
4744 | || (GET_CODE (reg) == SUBREG | |
4745 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
4746 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
4747 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
4748 | == REG) | |
4749 | || (GET_CODE (reg) == SUBREG | |
4750 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
4751 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
4752 | == CONST_INT))) | |
4753 | { | |
4754 | if (i == 0) | |
4755 | { | |
d5b7b3ae | 4756 | base_reg = REGNO (reg); |
84ed5e79 RE |
4757 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
4758 | ? REGNO (operands[i]) | |
4759 | : REGNO (SUBREG_REG (operands[i]))); | |
4760 | order[0] = 0; | |
4761 | } | |
4762 | else | |
4763 | { | |
6354dc9b | 4764 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
4765 | /* Not addressed from the same base register. */ |
4766 | return 0; | |
4767 | ||
4768 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
4769 | ? REGNO (operands[i]) | |
4770 | : REGNO (SUBREG_REG (operands[i]))); | |
4771 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
4772 | order[0] = i; | |
4773 | } | |
4774 | ||
4775 | /* If it isn't an integer register, or if it overwrites the | |
4776 | base register but isn't the last insn in the list, then | |
4777 | we can't do this. */ | |
4778 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | |
4779 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) | |
4780 | return 0; | |
4781 | ||
4782 | unsorted_offsets[i] = INTVAL (offset); | |
4783 | } | |
4784 | else | |
4785 | /* Not a suitable memory address. */ | |
4786 | return 0; | |
4787 | } | |
4788 | ||
4789 | /* All the useful information has now been extracted from the | |
4790 | operands into unsorted_regs and unsorted_offsets; additionally, | |
4791 | order[0] has been set to the lowest numbered register in the | |
4792 | list. Sort the registers into order, and check that the memory | |
4793 | offsets are ascending and adjacent. */ | |
4794 | ||
4795 | for (i = 1; i < nops; i++) | |
4796 | { | |
4797 | int j; | |
4798 | ||
4799 | order[i] = order[i - 1]; | |
4800 | for (j = 0; j < nops; j++) | |
4801 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
4802 | && (order[i] == order[i - 1] | |
4803 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
4804 | order[i] = j; | |
4805 | ||
4806 | /* Have we found a suitable register? if not, one must be used more | |
4807 | than once. */ | |
4808 | if (order[i] == order[i - 1]) | |
4809 | return 0; | |
4810 | ||
4811 | /* Is the memory address adjacent and ascending? */ | |
4812 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
4813 | return 0; | |
4814 | } | |
4815 | ||
4816 | if (base) | |
4817 | { | |
4818 | *base = base_reg; | |
4819 | ||
4820 | for (i = 0; i < nops; i++) | |
4821 | regs[i] = unsorted_regs[order[i]]; | |
4822 | ||
4823 | *load_offset = unsorted_offsets[order[0]]; | |
4824 | } | |
4825 | ||
4826 | if (unsorted_offsets[order[0]] == 0) | |
4827 | return 1; /* ldmia */ | |
4828 | ||
4829 | if (unsorted_offsets[order[0]] == 4) | |
4830 | return 2; /* ldmib */ | |
4831 | ||
4832 | if (unsorted_offsets[order[nops - 1]] == 0) | |
4833 | return 3; /* ldmda */ | |
4834 | ||
4835 | if (unsorted_offsets[order[nops - 1]] == -4) | |
4836 | return 4; /* ldmdb */ | |
4837 | ||
949d79eb RE |
4838 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm |
4839 | if the offset isn't small enough. The reason 2 ldrs are faster | |
4840 | is because these ARMs are able to do more than one cache access | |
4841 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
4842 | whilst the ARM8 has a double bandwidth cache. This means that | |
4843 | these cores can do both an instruction fetch and a data fetch in | |
4844 | a single cycle, so the trick of calculating the address into a | |
4845 | scratch register (one of the result regs) and then doing a load | |
4846 | multiple actually becomes slower (and no smaller in code size). | |
4847 | That is the transformation | |
6cc8c0b3 NC |
4848 | |
4849 | ldr rd1, [rbase + offset] | |
4850 | ldr rd2, [rbase + offset + 4] | |
4851 | ||
4852 | to | |
4853 | ||
4854 | add rd1, rbase, offset | |
4855 | ldmia rd1, {rd1, rd2} | |
4856 | ||
949d79eb RE |
4857 | produces worse code -- '3 cycles + any stalls on rd2' instead of |
4858 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
4859 | access per cycle, the first sequence could never complete in less | |
4860 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
4861 | would make better use of sequential accesses if not hitting the | |
4862 | cache. | |
4863 | ||
4864 | We cheat here and test 'arm_ld_sched' which we currently know to | |
4865 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
4866 | changes, then the test below needs to be reworked. */ | |
f5a1b0d2 | 4867 | if (nops == 2 && arm_ld_sched) |
b36ba79f RE |
4868 | return 0; |
4869 | ||
84ed5e79 RE |
4870 | /* Can't do it without setting up the offset, only do this if it takes |
4871 | no more than one insn. */ | |
4872 | return (const_ok_for_arm (unsorted_offsets[order[0]]) | |
4873 | || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; | |
4874 | } | |
4875 | ||
cd2b33d0 | 4876 | const char * |
84ed5e79 | 4877 | emit_ldm_seq (operands, nops) |
62b10bbc | 4878 | rtx * operands; |
84ed5e79 RE |
4879 | int nops; |
4880 | { | |
4881 | int regs[4]; | |
4882 | int base_reg; | |
4883 | HOST_WIDE_INT offset; | |
4884 | char buf[100]; | |
4885 | int i; | |
4886 | ||
4887 | switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
4888 | { | |
4889 | case 1: | |
4890 | strcpy (buf, "ldm%?ia\t"); | |
4891 | break; | |
4892 | ||
4893 | case 2: | |
4894 | strcpy (buf, "ldm%?ib\t"); | |
4895 | break; | |
4896 | ||
4897 | case 3: | |
4898 | strcpy (buf, "ldm%?da\t"); | |
4899 | break; | |
4900 | ||
4901 | case 4: | |
4902 | strcpy (buf, "ldm%?db\t"); | |
4903 | break; | |
4904 | ||
4905 | case 5: | |
4906 | if (offset >= 0) | |
4907 | sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
4908 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
4909 | (long) offset); | |
4910 | else | |
4911 | sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
4912 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
4913 | (long) -offset); | |
4914 | output_asm_insn (buf, operands); | |
4915 | base_reg = regs[0]; | |
4916 | strcpy (buf, "ldm%?ia\t"); | |
4917 | break; | |
4918 | ||
4919 | default: | |
4920 | abort (); | |
4921 | } | |
4922 | ||
4923 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | |
4924 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | |
4925 | ||
4926 | for (i = 1; i < nops; i++) | |
4927 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
4928 | reg_names[regs[i]]); | |
4929 | ||
4930 | strcat (buf, "}\t%@ phole ldm"); | |
4931 | ||
4932 | output_asm_insn (buf, operands); | |
4933 | return ""; | |
4934 | } | |
4935 | ||
4936 | int | |
4937 | store_multiple_sequence (operands, nops, regs, base, load_offset) | |
62b10bbc | 4938 | rtx * operands; |
84ed5e79 | 4939 | int nops; |
62b10bbc NC |
4940 | int * regs; |
4941 | int * base; | |
4942 | HOST_WIDE_INT * load_offset; | |
84ed5e79 RE |
4943 | { |
4944 | int unsorted_regs[4]; | |
4945 | HOST_WIDE_INT unsorted_offsets[4]; | |
4946 | int order[4]; | |
ad076f4e | 4947 | int base_reg = -1; |
84ed5e79 RE |
4948 | int i; |
4949 | ||
4950 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | |
4951 | extended if required. */ | |
4952 | if (nops < 2 || nops > 4) | |
4953 | abort (); | |
4954 | ||
4955 | /* Loop over the operands and check that the memory references are | |
4956 | suitable (ie immediate offsets from the same base register). At | |
4957 | the same time, extract the target register, and the memory | |
4958 | offsets. */ | |
4959 | for (i = 0; i < nops; i++) | |
4960 | { | |
4961 | rtx reg; | |
4962 | rtx offset; | |
4963 | ||
56636818 JL |
4964 | /* Convert a subreg of a mem into the mem itself. */ |
4965 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 4966 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 4967 | |
84ed5e79 RE |
4968 | if (GET_CODE (operands[nops + i]) != MEM) |
4969 | abort (); | |
4970 | ||
4971 | /* Don't reorder volatile memory references; it doesn't seem worth | |
4972 | looking for the case where the order is ok anyway. */ | |
4973 | if (MEM_VOLATILE_P (operands[nops + i])) | |
4974 | return 0; | |
4975 | ||
4976 | offset = const0_rtx; | |
4977 | ||
4978 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
4979 | || (GET_CODE (reg) == SUBREG | |
4980 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
4981 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
4982 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
4983 | == REG) | |
4984 | || (GET_CODE (reg) == SUBREG | |
4985 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
4986 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
4987 | == CONST_INT))) | |
4988 | { | |
4989 | if (i == 0) | |
4990 | { | |
62b10bbc | 4991 | base_reg = REGNO (reg); |
84ed5e79 RE |
4992 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
4993 | ? REGNO (operands[i]) | |
4994 | : REGNO (SUBREG_REG (operands[i]))); | |
4995 | order[0] = 0; | |
4996 | } | |
4997 | else | |
4998 | { | |
6354dc9b | 4999 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
5000 | /* Not addressed from the same base register. */ |
5001 | return 0; | |
5002 | ||
5003 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
5004 | ? REGNO (operands[i]) | |
5005 | : REGNO (SUBREG_REG (operands[i]))); | |
5006 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
5007 | order[0] = i; | |
5008 | } | |
5009 | ||
5010 | /* If it isn't an integer register, then we can't do this. */ | |
5011 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | |
5012 | return 0; | |
5013 | ||
5014 | unsorted_offsets[i] = INTVAL (offset); | |
5015 | } | |
5016 | else | |
5017 | /* Not a suitable memory address. */ | |
5018 | return 0; | |
5019 | } | |
5020 | ||
5021 | /* All the useful information has now been extracted from the | |
5022 | operands into unsorted_regs and unsorted_offsets; additionally, | |
5023 | order[0] has been set to the lowest numbered register in the | |
5024 | list. Sort the registers into order, and check that the memory | |
5025 | offsets are ascending and adjacent. */ | |
5026 | ||
5027 | for (i = 1; i < nops; i++) | |
5028 | { | |
5029 | int j; | |
5030 | ||
5031 | order[i] = order[i - 1]; | |
5032 | for (j = 0; j < nops; j++) | |
5033 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
5034 | && (order[i] == order[i - 1] | |
5035 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
5036 | order[i] = j; | |
5037 | ||
5038 | /* Have we found a suitable register? if not, one must be used more | |
5039 | than once. */ | |
5040 | if (order[i] == order[i - 1]) | |
5041 | return 0; | |
5042 | ||
5043 | /* Is the memory address adjacent and ascending? */ | |
5044 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
5045 | return 0; | |
5046 | } | |
5047 | ||
5048 | if (base) | |
5049 | { | |
5050 | *base = base_reg; | |
5051 | ||
5052 | for (i = 0; i < nops; i++) | |
5053 | regs[i] = unsorted_regs[order[i]]; | |
5054 | ||
5055 | *load_offset = unsorted_offsets[order[0]]; | |
5056 | } | |
5057 | ||
5058 | if (unsorted_offsets[order[0]] == 0) | |
5059 | return 1; /* stmia */ | |
5060 | ||
5061 | if (unsorted_offsets[order[0]] == 4) | |
5062 | return 2; /* stmib */ | |
5063 | ||
5064 | if (unsorted_offsets[order[nops - 1]] == 0) | |
5065 | return 3; /* stmda */ | |
5066 | ||
5067 | if (unsorted_offsets[order[nops - 1]] == -4) | |
5068 | return 4; /* stmdb */ | |
5069 | ||
5070 | return 0; | |
5071 | } | |
5072 | ||
cd2b33d0 | 5073 | const char * |
84ed5e79 | 5074 | emit_stm_seq (operands, nops) |
62b10bbc | 5075 | rtx * operands; |
84ed5e79 RE |
5076 | int nops; |
5077 | { | |
5078 | int regs[4]; | |
5079 | int base_reg; | |
5080 | HOST_WIDE_INT offset; | |
5081 | char buf[100]; | |
5082 | int i; | |
5083 | ||
5084 | switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
5085 | { | |
5086 | case 1: | |
5087 | strcpy (buf, "stm%?ia\t"); | |
5088 | break; | |
5089 | ||
5090 | case 2: | |
5091 | strcpy (buf, "stm%?ib\t"); | |
5092 | break; | |
5093 | ||
5094 | case 3: | |
5095 | strcpy (buf, "stm%?da\t"); | |
5096 | break; | |
5097 | ||
5098 | case 4: | |
5099 | strcpy (buf, "stm%?db\t"); | |
5100 | break; | |
5101 | ||
5102 | default: | |
5103 | abort (); | |
5104 | } | |
5105 | ||
5106 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | |
5107 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | |
5108 | ||
5109 | for (i = 1; i < nops; i++) | |
5110 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
5111 | reg_names[regs[i]]); | |
5112 | ||
5113 | strcat (buf, "}\t%@ phole stm"); | |
5114 | ||
5115 | output_asm_insn (buf, operands); | |
5116 | return ""; | |
5117 | } | |
5118 | ||
e2c671ba RE |
5119 | int |
5120 | multi_register_push (op, mode) | |
0a81f500 | 5121 | rtx op; |
74bbc178 | 5122 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e2c671ba RE |
5123 | { |
5124 | if (GET_CODE (op) != PARALLEL | |
5125 | || (GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
5126 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
b15bca31 | 5127 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) |
e2c671ba RE |
5128 | return 0; |
5129 | ||
5130 | return 1; | |
5131 | } | |
ff9940b0 | 5132 | \f |
6354dc9b | 5133 | /* Routines for use in generating RTL. */ |
1d6e90ac | 5134 | |
f3bb6135 | 5135 | rtx |
56636818 | 5136 | arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p, |
c6df88cb | 5137 | in_struct_p, scalar_p) |
ff9940b0 RE |
5138 | int base_regno; |
5139 | int count; | |
5140 | rtx from; | |
5141 | int up; | |
5142 | int write_back; | |
56636818 JL |
5143 | int unchanging_p; |
5144 | int in_struct_p; | |
c6df88cb | 5145 | int scalar_p; |
ff9940b0 RE |
5146 | { |
5147 | int i = 0, j; | |
5148 | rtx result; | |
5149 | int sign = up ? 1 : -1; | |
56636818 | 5150 | rtx mem; |
ff9940b0 | 5151 | |
d19fb8e3 NC |
5152 | /* XScale has load-store double instructions, but they have stricter |
5153 | alignment requirements than load-store multiple, so we can not | |
5154 | use them. | |
5155 | ||
5156 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
5157 | the pipeline until completion. | |
5158 | ||
5159 | NREGS CYCLES | |
5160 | 1 3 | |
5161 | 2 4 | |
5162 | 3 5 | |
5163 | 4 6 | |
5164 | ||
5165 | An ldr instruction takes 1-3 cycles, but does not block the | |
5166 | pipeline. | |
5167 | ||
5168 | NREGS CYCLES | |
5169 | 1 1-3 | |
5170 | 2 2-6 | |
5171 | 3 3-9 | |
5172 | 4 4-12 | |
5173 | ||
5174 | Best case ldr will always win. However, the more ldr instructions | |
5175 | we issue, the less likely we are to be able to schedule them well. | |
5176 | Using ldr instructions also increases code size. | |
5177 | ||
5178 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
5179 | for counts of 3 or 4 regs. */ | |
5180 | if (arm_is_xscale && count <= 2 && ! optimize_size) | |
5181 | { | |
5182 | rtx seq; | |
5183 | ||
5184 | start_sequence (); | |
5185 | ||
5186 | for (i = 0; i < count; i++) | |
5187 | { | |
5188 | mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign)); | |
5189 | RTX_UNCHANGING_P (mem) = unchanging_p; | |
5190 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
5191 | MEM_SCALAR_P (mem) = scalar_p; | |
5192 | emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); | |
5193 | } | |
5194 | ||
5195 | if (write_back) | |
5196 | emit_move_insn (from, plus_constant (from, count * 4 * sign)); | |
5197 | ||
2f937369 | 5198 | seq = get_insns (); |
d19fb8e3 NC |
5199 | end_sequence (); |
5200 | ||
5201 | return seq; | |
5202 | } | |
5203 | ||
43cffd11 | 5204 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 5205 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 5206 | if (write_back) |
f3bb6135 | 5207 | { |
ff9940b0 | 5208 | XVECEXP (result, 0, 0) |
43cffd11 RE |
5209 | = gen_rtx_SET (GET_MODE (from), from, |
5210 | plus_constant (from, count * 4 * sign)); | |
ff9940b0 RE |
5211 | i = 1; |
5212 | count++; | |
f3bb6135 RE |
5213 | } |
5214 | ||
ff9940b0 | 5215 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 5216 | { |
43cffd11 | 5217 | mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign)); |
56636818 JL |
5218 | RTX_UNCHANGING_P (mem) = unchanging_p; |
5219 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
c6df88cb | 5220 | MEM_SCALAR_P (mem) = scalar_p; |
43cffd11 RE |
5221 | XVECEXP (result, 0, i) |
5222 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | |
f3bb6135 RE |
5223 | } |
5224 | ||
ff9940b0 RE |
5225 | return result; |
5226 | } | |
5227 | ||
f3bb6135 | 5228 | rtx |
56636818 | 5229 | arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p, |
c6df88cb | 5230 | in_struct_p, scalar_p) |
ff9940b0 RE |
5231 | int base_regno; |
5232 | int count; | |
5233 | rtx to; | |
5234 | int up; | |
5235 | int write_back; | |
56636818 JL |
5236 | int unchanging_p; |
5237 | int in_struct_p; | |
c6df88cb | 5238 | int scalar_p; |
ff9940b0 RE |
5239 | { |
5240 | int i = 0, j; | |
5241 | rtx result; | |
5242 | int sign = up ? 1 : -1; | |
56636818 | 5243 | rtx mem; |
ff9940b0 | 5244 | |
d19fb8e3 NC |
5245 | /* See arm_gen_load_multiple for discussion of |
5246 | the pros/cons of ldm/stm usage for XScale. */ | |
5247 | if (arm_is_xscale && count <= 2 && ! optimize_size) | |
5248 | { | |
5249 | rtx seq; | |
5250 | ||
5251 | start_sequence (); | |
5252 | ||
5253 | for (i = 0; i < count; i++) | |
5254 | { | |
5255 | mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign)); | |
5256 | RTX_UNCHANGING_P (mem) = unchanging_p; | |
5257 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
5258 | MEM_SCALAR_P (mem) = scalar_p; | |
5259 | emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); | |
5260 | } | |
5261 | ||
5262 | if (write_back) | |
5263 | emit_move_insn (to, plus_constant (to, count * 4 * sign)); | |
5264 | ||
2f937369 | 5265 | seq = get_insns (); |
d19fb8e3 NC |
5266 | end_sequence (); |
5267 | ||
5268 | return seq; | |
5269 | } | |
5270 | ||
43cffd11 | 5271 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 5272 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 5273 | if (write_back) |
f3bb6135 | 5274 | { |
ff9940b0 | 5275 | XVECEXP (result, 0, 0) |
43cffd11 RE |
5276 | = gen_rtx_SET (GET_MODE (to), to, |
5277 | plus_constant (to, count * 4 * sign)); | |
ff9940b0 RE |
5278 | i = 1; |
5279 | count++; | |
f3bb6135 RE |
5280 | } |
5281 | ||
ff9940b0 | 5282 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 5283 | { |
43cffd11 | 5284 | mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign)); |
56636818 JL |
5285 | RTX_UNCHANGING_P (mem) = unchanging_p; |
5286 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
c6df88cb | 5287 | MEM_SCALAR_P (mem) = scalar_p; |
56636818 | 5288 | |
43cffd11 RE |
5289 | XVECEXP (result, 0, i) |
5290 | = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | |
f3bb6135 RE |
5291 | } |
5292 | ||
ff9940b0 RE |
5293 | return result; |
5294 | } | |
5295 | ||
880e2516 RE |
5296 | int |
5297 | arm_gen_movstrqi (operands) | |
62b10bbc | 5298 | rtx * operands; |
880e2516 RE |
5299 | { |
5300 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
ad076f4e | 5301 | int i; |
880e2516 | 5302 | rtx src, dst; |
ad076f4e | 5303 | rtx st_src, st_dst, fin_src, fin_dst; |
880e2516 | 5304 | rtx part_bytes_reg = NULL; |
56636818 JL |
5305 | rtx mem; |
5306 | int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p; | |
c6df88cb | 5307 | int dst_scalar_p, src_scalar_p; |
880e2516 RE |
5308 | |
5309 | if (GET_CODE (operands[2]) != CONST_INT | |
5310 | || GET_CODE (operands[3]) != CONST_INT | |
5311 | || INTVAL (operands[2]) > 64 | |
5312 | || INTVAL (operands[3]) & 3) | |
5313 | return 0; | |
5314 | ||
5315 | st_dst = XEXP (operands[0], 0); | |
5316 | st_src = XEXP (operands[1], 0); | |
56636818 JL |
5317 | |
5318 | dst_unchanging_p = RTX_UNCHANGING_P (operands[0]); | |
5319 | dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]); | |
c6df88cb | 5320 | dst_scalar_p = MEM_SCALAR_P (operands[0]); |
56636818 JL |
5321 | src_unchanging_p = RTX_UNCHANGING_P (operands[1]); |
5322 | src_in_struct_p = MEM_IN_STRUCT_P (operands[1]); | |
c6df88cb | 5323 | src_scalar_p = MEM_SCALAR_P (operands[1]); |
56636818 | 5324 | |
880e2516 RE |
5325 | fin_dst = dst = copy_to_mode_reg (SImode, st_dst); |
5326 | fin_src = src = copy_to_mode_reg (SImode, st_src); | |
5327 | ||
e9d7b180 | 5328 | in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
5329 | out_words_to_go = INTVAL (operands[2]) / 4; |
5330 | last_bytes = INTVAL (operands[2]) & 3; | |
5331 | ||
5332 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 5333 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
5334 | |
5335 | for (i = 0; in_words_to_go >= 2; i+=4) | |
5336 | { | |
bd9c7e23 | 5337 | if (in_words_to_go > 4) |
56636818 | 5338 | emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, |
c6df88cb MM |
5339 | src_unchanging_p, |
5340 | src_in_struct_p, | |
5341 | src_scalar_p)); | |
bd9c7e23 RE |
5342 | else |
5343 | emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, | |
56636818 | 5344 | FALSE, src_unchanging_p, |
c6df88cb | 5345 | src_in_struct_p, src_scalar_p)); |
bd9c7e23 | 5346 | |
880e2516 RE |
5347 | if (out_words_to_go) |
5348 | { | |
bd9c7e23 | 5349 | if (out_words_to_go > 4) |
56636818 JL |
5350 | emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, |
5351 | dst_unchanging_p, | |
c6df88cb MM |
5352 | dst_in_struct_p, |
5353 | dst_scalar_p)); | |
bd9c7e23 RE |
5354 | else if (out_words_to_go != 1) |
5355 | emit_insn (arm_gen_store_multiple (0, out_words_to_go, | |
5356 | dst, TRUE, | |
5357 | (last_bytes == 0 | |
56636818 JL |
5358 | ? FALSE : TRUE), |
5359 | dst_unchanging_p, | |
c6df88cb MM |
5360 | dst_in_struct_p, |
5361 | dst_scalar_p)); | |
880e2516 RE |
5362 | else |
5363 | { | |
43cffd11 | 5364 | mem = gen_rtx_MEM (SImode, dst); |
56636818 JL |
5365 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
5366 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 5367 | MEM_SCALAR_P (mem) = dst_scalar_p; |
43cffd11 | 5368 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 RE |
5369 | if (last_bytes != 0) |
5370 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
880e2516 RE |
5371 | } |
5372 | } | |
5373 | ||
5374 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
5375 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
5376 | } | |
5377 | ||
5378 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
5379 | if (out_words_to_go) | |
62b10bbc NC |
5380 | { |
5381 | rtx sreg; | |
5382 | ||
5383 | mem = gen_rtx_MEM (SImode, src); | |
5384 | RTX_UNCHANGING_P (mem) = src_unchanging_p; | |
5385 | MEM_IN_STRUCT_P (mem) = src_in_struct_p; | |
5386 | MEM_SCALAR_P (mem) = src_scalar_p; | |
5387 | emit_move_insn (sreg = gen_reg_rtx (SImode), mem); | |
5388 | emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4)); | |
5389 | ||
5390 | mem = gen_rtx_MEM (SImode, dst); | |
5391 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; | |
5392 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
5393 | MEM_SCALAR_P (mem) = dst_scalar_p; | |
5394 | emit_move_insn (mem, sreg); | |
5395 | emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4)); | |
5396 | in_words_to_go--; | |
5397 | ||
5398 | if (in_words_to_go) /* Sanity check */ | |
5399 | abort (); | |
5400 | } | |
880e2516 RE |
5401 | |
5402 | if (in_words_to_go) | |
5403 | { | |
5404 | if (in_words_to_go < 0) | |
5405 | abort (); | |
5406 | ||
43cffd11 | 5407 | mem = gen_rtx_MEM (SImode, src); |
56636818 JL |
5408 | RTX_UNCHANGING_P (mem) = src_unchanging_p; |
5409 | MEM_IN_STRUCT_P (mem) = src_in_struct_p; | |
c6df88cb | 5410 | MEM_SCALAR_P (mem) = src_scalar_p; |
56636818 | 5411 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
5412 | } |
5413 | ||
d5b7b3ae RE |
5414 | if (last_bytes && part_bytes_reg == NULL) |
5415 | abort (); | |
5416 | ||
880e2516 RE |
5417 | if (BYTES_BIG_ENDIAN && last_bytes) |
5418 | { | |
5419 | rtx tmp = gen_reg_rtx (SImode); | |
5420 | ||
6354dc9b | 5421 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
5422 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
5423 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 RE |
5424 | part_bytes_reg = tmp; |
5425 | ||
5426 | while (last_bytes) | |
5427 | { | |
43cffd11 | 5428 | mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1)); |
56636818 JL |
5429 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
5430 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 5431 | MEM_SCALAR_P (mem) = dst_scalar_p; |
5d5603e2 BS |
5432 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
5433 | ||
880e2516 RE |
5434 | if (--last_bytes) |
5435 | { | |
5436 | tmp = gen_reg_rtx (SImode); | |
5437 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
5438 | part_bytes_reg = tmp; | |
5439 | } | |
5440 | } | |
5441 | ||
5442 | } | |
5443 | else | |
5444 | { | |
d5b7b3ae | 5445 | if (last_bytes > 1) |
880e2516 | 5446 | { |
d5b7b3ae | 5447 | mem = gen_rtx_MEM (HImode, dst); |
56636818 JL |
5448 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
5449 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 5450 | MEM_SCALAR_P (mem) = dst_scalar_p; |
5d5603e2 | 5451 | emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); |
d5b7b3ae RE |
5452 | last_bytes -= 2; |
5453 | if (last_bytes) | |
880e2516 RE |
5454 | { |
5455 | rtx tmp = gen_reg_rtx (SImode); | |
bd9c7e23 | 5456 | |
d5b7b3ae RE |
5457 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (2))); |
5458 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); | |
880e2516 RE |
5459 | part_bytes_reg = tmp; |
5460 | } | |
5461 | } | |
d5b7b3ae RE |
5462 | |
5463 | if (last_bytes) | |
5464 | { | |
5465 | mem = gen_rtx_MEM (QImode, dst); | |
5466 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; | |
5467 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
5468 | MEM_SCALAR_P (mem) = dst_scalar_p; | |
5d5603e2 | 5469 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
d5b7b3ae | 5470 | } |
880e2516 RE |
5471 | } |
5472 | ||
5473 | return 1; | |
5474 | } | |
5475 | ||
5165176d RE |
5476 | /* Generate a memory reference for a half word, such that it will be loaded |
5477 | into the top 16 bits of the word. We can assume that the address is | |
5478 | known to be alignable and of the form reg, or plus (reg, const). */ | |
1d6e90ac | 5479 | |
5165176d | 5480 | rtx |
d5b7b3ae | 5481 | arm_gen_rotated_half_load (memref) |
5165176d RE |
5482 | rtx memref; |
5483 | { | |
5484 | HOST_WIDE_INT offset = 0; | |
5485 | rtx base = XEXP (memref, 0); | |
5486 | ||
5487 | if (GET_CODE (base) == PLUS) | |
5488 | { | |
5489 | offset = INTVAL (XEXP (base, 1)); | |
5490 | base = XEXP (base, 0); | |
5491 | } | |
5492 | ||
956d6950 | 5493 | /* If we aren't allowed to generate unaligned addresses, then fail. */ |
5f1e6755 | 5494 | if (TARGET_MMU_TRAPS |
5165176d RE |
5495 | && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))) |
5496 | return NULL; | |
5497 | ||
43cffd11 | 5498 | base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2)); |
5165176d RE |
5499 | |
5500 | if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2)) | |
5501 | return base; | |
5502 | ||
43cffd11 | 5503 | return gen_rtx_ROTATE (SImode, base, GEN_INT (16)); |
5165176d RE |
5504 | } |
5505 | ||
03f1640c RE |
5506 | /* Select a dominance comparison mode if possible for a test of the general |
5507 | form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. | |
5508 | COND_OR == DOM_CC_X_AND_Y => (X && Y) | |
5509 | COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) | |
5510 | COND_OR == DOM_CC_X_OR_Y => (X || Y) | |
5511 | In all cases OP will be either EQ or NE, but we don't need to know which | |
5512 | here. If we are unable to support a dominance comparison we return | |
5513 | CC mode. This will then fail to match for the RTL expressions that | |
5514 | generate this call. */ | |
d19fb8e3 | 5515 | |
03f1640c RE |
5516 | enum machine_mode |
5517 | arm_select_dominance_cc_mode (x, y, cond_or) | |
84ed5e79 RE |
5518 | rtx x; |
5519 | rtx y; | |
5520 | HOST_WIDE_INT cond_or; | |
5521 | { | |
5522 | enum rtx_code cond1, cond2; | |
5523 | int swapped = 0; | |
5524 | ||
5525 | /* Currently we will probably get the wrong result if the individual | |
5526 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 5527 | reverse a comparison if necessary. */ |
84ed5e79 RE |
5528 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
5529 | != CCmode) | |
5530 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
5531 | != CCmode)) | |
5532 | return CCmode; | |
5533 | ||
1646cf41 RE |
5534 | /* The if_then_else variant of this tests the second condition if the |
5535 | first passes, but is true if the first fails. Reverse the first | |
5536 | condition to get a true "inclusive-or" expression. */ | |
03f1640c | 5537 | if (cond_or == DOM_CC_NX_OR_Y) |
84ed5e79 RE |
5538 | cond1 = reverse_condition (cond1); |
5539 | ||
5540 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
5541 | then we can't do this. */ | |
5542 | if (cond1 != cond2 | |
5895f793 RE |
5543 | && !comparison_dominates_p (cond1, cond2) |
5544 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
5545 | return CCmode; |
5546 | ||
5547 | if (swapped) | |
5548 | { | |
5549 | enum rtx_code temp = cond1; | |
5550 | cond1 = cond2; | |
5551 | cond2 = temp; | |
5552 | } | |
5553 | ||
5554 | switch (cond1) | |
5555 | { | |
5556 | case EQ: | |
03f1640c | 5557 | if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5558 | return CC_DEQmode; |
5559 | ||
5560 | switch (cond2) | |
5561 | { | |
5562 | case LE: return CC_DLEmode; | |
5563 | case LEU: return CC_DLEUmode; | |
5564 | case GE: return CC_DGEmode; | |
5565 | case GEU: return CC_DGEUmode; | |
ad076f4e | 5566 | default: break; |
84ed5e79 RE |
5567 | } |
5568 | ||
5569 | break; | |
5570 | ||
5571 | case LT: | |
03f1640c | 5572 | if (cond2 == LT || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5573 | return CC_DLTmode; |
5574 | if (cond2 == LE) | |
5575 | return CC_DLEmode; | |
5576 | if (cond2 == NE) | |
5577 | return CC_DNEmode; | |
5578 | break; | |
5579 | ||
5580 | case GT: | |
03f1640c | 5581 | if (cond2 == GT || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5582 | return CC_DGTmode; |
5583 | if (cond2 == GE) | |
5584 | return CC_DGEmode; | |
5585 | if (cond2 == NE) | |
5586 | return CC_DNEmode; | |
5587 | break; | |
5588 | ||
5589 | case LTU: | |
03f1640c | 5590 | if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5591 | return CC_DLTUmode; |
5592 | if (cond2 == LEU) | |
5593 | return CC_DLEUmode; | |
5594 | if (cond2 == NE) | |
5595 | return CC_DNEmode; | |
5596 | break; | |
5597 | ||
5598 | case GTU: | |
03f1640c | 5599 | if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
5600 | return CC_DGTUmode; |
5601 | if (cond2 == GEU) | |
5602 | return CC_DGEUmode; | |
5603 | if (cond2 == NE) | |
5604 | return CC_DNEmode; | |
5605 | break; | |
5606 | ||
5607 | /* The remaining cases only occur when both comparisons are the | |
5608 | same. */ | |
5609 | case NE: | |
5610 | return CC_DNEmode; | |
5611 | ||
5612 | case LE: | |
5613 | return CC_DLEmode; | |
5614 | ||
5615 | case GE: | |
5616 | return CC_DGEmode; | |
5617 | ||
5618 | case LEU: | |
5619 | return CC_DLEUmode; | |
5620 | ||
5621 | case GEU: | |
5622 | return CC_DGEUmode; | |
ad076f4e RE |
5623 | |
5624 | default: | |
5625 | break; | |
84ed5e79 RE |
5626 | } |
5627 | ||
5628 | abort (); | |
5629 | } | |
5630 | ||
5631 | enum machine_mode | |
5632 | arm_select_cc_mode (op, x, y) | |
5633 | enum rtx_code op; | |
5634 | rtx x; | |
5635 | rtx y; | |
5636 | { | |
5637 | /* All floating point compares return CCFP if it is an equality | |
5638 | comparison, and CCFPE otherwise. */ | |
5639 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
5640 | { |
5641 | switch (op) | |
5642 | { | |
5643 | case EQ: | |
5644 | case NE: | |
5645 | case UNORDERED: | |
5646 | case ORDERED: | |
5647 | case UNLT: | |
5648 | case UNLE: | |
5649 | case UNGT: | |
5650 | case UNGE: | |
5651 | case UNEQ: | |
5652 | case LTGT: | |
5653 | return CCFPmode; | |
5654 | ||
5655 | case LT: | |
5656 | case LE: | |
5657 | case GT: | |
5658 | case GE: | |
9b6b54e2 NC |
5659 | if (TARGET_CIRRUS) |
5660 | return CCFPmode; | |
e45b72c4 RE |
5661 | return CCFPEmode; |
5662 | ||
5663 | default: | |
5664 | abort (); | |
5665 | } | |
5666 | } | |
84ed5e79 RE |
5667 | |
5668 | /* A compare with a shifted operand. Because of canonicalization, the | |
5669 | comparison will have to be swapped when we emit the assembler. */ | |
5670 | if (GET_MODE (y) == SImode && GET_CODE (y) == REG | |
5671 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
5672 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
5673 | || GET_CODE (x) == ROTATERT)) | |
5674 | return CC_SWPmode; | |
5675 | ||
956d6950 JL |
5676 | /* This is a special case that is used by combine to allow a |
5677 | comparison of a shifted byte load to be split into a zero-extend | |
84ed5e79 | 5678 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 5679 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
5680 | if (GET_MODE (x) == SImode |
5681 | && GET_CODE (x) == ASHIFT | |
5682 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
5683 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
5684 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
5685 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
5686 | && (op == EQ || op == NE | |
5687 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
5688 | && GET_CODE (y) == CONST_INT) | |
5689 | return CC_Zmode; | |
5690 | ||
1646cf41 RE |
5691 | /* A construct for a conditional compare, if the false arm contains |
5692 | 0, then both conditions must be true, otherwise either condition | |
5693 | must be true. Not all conditions are possible, so CCmode is | |
5694 | returned if it can't be done. */ | |
5695 | if (GET_CODE (x) == IF_THEN_ELSE | |
5696 | && (XEXP (x, 2) == const0_rtx | |
5697 | || XEXP (x, 2) == const1_rtx) | |
5698 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
5699 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') | |
03f1640c RE |
5700 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
5701 | INTVAL (XEXP (x, 2))); | |
1646cf41 RE |
5702 | |
5703 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
5704 | if (GET_CODE (x) == AND | |
5705 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
5706 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') | |
03f1640c RE |
5707 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
5708 | DOM_CC_X_AND_Y); | |
1646cf41 RE |
5709 | |
5710 | if (GET_CODE (x) == IOR | |
5711 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
5712 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') | |
03f1640c RE |
5713 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
5714 | DOM_CC_X_OR_Y); | |
1646cf41 | 5715 | |
84ed5e79 RE |
5716 | /* An operation that sets the condition codes as a side-effect, the |
5717 | V flag is not set correctly, so we can only use comparisons where | |
5718 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
5719 | instead. */ | |
5720 | if (GET_MODE (x) == SImode | |
5721 | && y == const0_rtx | |
5722 | && (op == EQ || op == NE || op == LT || op == GE) | |
5723 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
5724 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
5725 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
5726 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
5727 | || GET_CODE (x) == LSHIFTRT | |
5728 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
5729 | || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT)) | |
5730 | return CC_NOOVmode; | |
5731 | ||
84ed5e79 RE |
5732 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
5733 | return CC_Zmode; | |
5734 | ||
bd9c7e23 RE |
5735 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
5736 | && GET_CODE (x) == PLUS | |
5737 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
5738 | return CC_Cmode; | |
5739 | ||
84ed5e79 RE |
5740 | return CCmode; |
5741 | } | |
5742 | ||
ff9940b0 RE |
5743 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
5744 | return the rtx for register 0 in the proper mode. FP means this is a | |
5745 | floating point compare: I don't think that it is needed on the arm. */ | |
5746 | ||
5747 | rtx | |
d5b7b3ae | 5748 | arm_gen_compare_reg (code, x, y) |
ff9940b0 RE |
5749 | enum rtx_code code; |
5750 | rtx x, y; | |
5751 | { | |
5752 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); | |
d5b7b3ae | 5753 | rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); |
ff9940b0 | 5754 | |
43cffd11 RE |
5755 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
5756 | gen_rtx_COMPARE (mode, x, y))); | |
ff9940b0 RE |
5757 | |
5758 | return cc_reg; | |
5759 | } | |
5760 | ||
fcd53748 JT |
5761 | /* Generate a sequence of insns that will generate the correct return |
5762 | address mask depending on the physical architecture that the program | |
5763 | is running on. */ | |
5764 | ||
5765 | rtx | |
5766 | arm_gen_return_addr_mask () | |
5767 | { | |
5768 | rtx reg = gen_reg_rtx (Pmode); | |
5769 | ||
5770 | emit_insn (gen_return_addr_mask (reg)); | |
5771 | return reg; | |
5772 | } | |
5773 | ||
0a81f500 RE |
5774 | void |
5775 | arm_reload_in_hi (operands) | |
62b10bbc | 5776 | rtx * operands; |
0a81f500 | 5777 | { |
f9cc092a RE |
5778 | rtx ref = operands[1]; |
5779 | rtx base, scratch; | |
5780 | HOST_WIDE_INT offset = 0; | |
5781 | ||
5782 | if (GET_CODE (ref) == SUBREG) | |
5783 | { | |
ddef6bc7 | 5784 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
5785 | ref = SUBREG_REG (ref); |
5786 | } | |
5787 | ||
5788 | if (GET_CODE (ref) == REG) | |
5789 | { | |
5790 | /* We have a pseudo which has been spilt onto the stack; there | |
5791 | are two cases here: the first where there is a simple | |
5792 | stack-slot replacement and a second where the stack-slot is | |
5793 | out of range, or is used as a subreg. */ | |
5794 | if (reg_equiv_mem[REGNO (ref)]) | |
5795 | { | |
5796 | ref = reg_equiv_mem[REGNO (ref)]; | |
5797 | base = find_replacement (&XEXP (ref, 0)); | |
5798 | } | |
5799 | else | |
6354dc9b | 5800 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
5801 | base = reg_equiv_address[REGNO (ref)]; |
5802 | } | |
5803 | else | |
5804 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 5805 | |
e5e809f4 JL |
5806 | /* Handle the case where the address is too complex to be offset by 1. */ |
5807 | if (GET_CODE (base) == MINUS | |
5808 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
5809 | { | |
f9cc092a | 5810 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 5811 | |
43cffd11 | 5812 | emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); |
e5e809f4 JL |
5813 | base = base_plus; |
5814 | } | |
f9cc092a RE |
5815 | else if (GET_CODE (base) == PLUS) |
5816 | { | |
6354dc9b | 5817 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
5818 | HOST_WIDE_INT hi, lo; |
5819 | ||
5820 | offset += INTVAL (XEXP (base, 1)); | |
5821 | base = XEXP (base, 0); | |
5822 | ||
6354dc9b | 5823 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
5824 | /* Valid range for lo is -4095 -> 4095 */ |
5825 | lo = (offset >= 0 | |
5826 | ? (offset & 0xfff) | |
5827 | : -((-offset) & 0xfff)); | |
5828 | ||
5829 | /* Corner case, if lo is the max offset then we would be out of range | |
5830 | once we have added the additional 1 below, so bump the msb into the | |
5831 | pre-loading insn(s). */ | |
5832 | if (lo == 4095) | |
5833 | lo &= 0x7ff; | |
5834 | ||
30cf4896 KG |
5835 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
5836 | ^ (HOST_WIDE_INT) 0x80000000) | |
5837 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a RE |
5838 | |
5839 | if (hi + lo != offset) | |
5840 | abort (); | |
5841 | ||
5842 | if (hi != 0) | |
5843 | { | |
5844 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
5845 | ||
5846 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 5847 | that require more than one insn. */ |
f9cc092a RE |
5848 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
5849 | base = base_plus; | |
5850 | offset = lo; | |
5851 | } | |
5852 | } | |
e5e809f4 | 5853 | |
3a1944a6 RE |
5854 | /* Operands[2] may overlap operands[0] (though it won't overlap |
5855 | operands[1]), that's why we asked for a DImode reg -- so we can | |
5856 | use the bit that does not overlap. */ | |
5857 | if (REGNO (operands[2]) == REGNO (operands[0])) | |
5858 | scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
5859 | else | |
5860 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
5861 | ||
f9cc092a RE |
5862 | emit_insn (gen_zero_extendqisi2 (scratch, |
5863 | gen_rtx_MEM (QImode, | |
5864 | plus_constant (base, | |
5865 | offset)))); | |
43cffd11 RE |
5866 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
5867 | gen_rtx_MEM (QImode, | |
f9cc092a RE |
5868 | plus_constant (base, |
5869 | offset + 1)))); | |
5895f793 | 5870 | if (!BYTES_BIG_ENDIAN) |
43cffd11 RE |
5871 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), |
5872 | gen_rtx_IOR (SImode, | |
5873 | gen_rtx_ASHIFT | |
5874 | (SImode, | |
5875 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
5876 | GEN_INT (8)), | |
f9cc092a | 5877 | scratch))); |
0a81f500 | 5878 | else |
43cffd11 RE |
5879 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), |
5880 | gen_rtx_IOR (SImode, | |
f9cc092a | 5881 | gen_rtx_ASHIFT (SImode, scratch, |
43cffd11 RE |
5882 | GEN_INT (8)), |
5883 | gen_rtx_SUBREG (SImode, operands[0], | |
5884 | 0)))); | |
0a81f500 RE |
5885 | } |
5886 | ||
f9cc092a RE |
5887 | /* Handle storing a half-word to memory during reload by synthesising as two |
5888 | byte stores. Take care not to clobber the input values until after we | |
5889 | have moved them somewhere safe. This code assumes that if the DImode | |
5890 | scratch in operands[2] overlaps either the input value or output address | |
5891 | in some way, then that value must die in this insn (we absolutely need | |
5892 | two scratch registers for some corner cases). */ | |
1d6e90ac | 5893 | |
f3bb6135 | 5894 | void |
af48348a | 5895 | arm_reload_out_hi (operands) |
62b10bbc | 5896 | rtx * operands; |
af48348a | 5897 | { |
f9cc092a RE |
5898 | rtx ref = operands[0]; |
5899 | rtx outval = operands[1]; | |
5900 | rtx base, scratch; | |
5901 | HOST_WIDE_INT offset = 0; | |
5902 | ||
5903 | if (GET_CODE (ref) == SUBREG) | |
5904 | { | |
ddef6bc7 | 5905 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
5906 | ref = SUBREG_REG (ref); |
5907 | } | |
5908 | ||
f9cc092a RE |
5909 | if (GET_CODE (ref) == REG) |
5910 | { | |
5911 | /* We have a pseudo which has been spilt onto the stack; there | |
5912 | are two cases here: the first where there is a simple | |
5913 | stack-slot replacement and a second where the stack-slot is | |
5914 | out of range, or is used as a subreg. */ | |
5915 | if (reg_equiv_mem[REGNO (ref)]) | |
5916 | { | |
5917 | ref = reg_equiv_mem[REGNO (ref)]; | |
5918 | base = find_replacement (&XEXP (ref, 0)); | |
5919 | } | |
5920 | else | |
6354dc9b | 5921 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
5922 | base = reg_equiv_address[REGNO (ref)]; |
5923 | } | |
5924 | else | |
5925 | base = find_replacement (&XEXP (ref, 0)); | |
5926 | ||
5927 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
5928 | ||
5929 | /* Handle the case where the address is too complex to be offset by 1. */ | |
5930 | if (GET_CODE (base) == MINUS | |
5931 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
5932 | { | |
5933 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
5934 | ||
5935 | /* Be careful not to destroy OUTVAL. */ | |
5936 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
5937 | { | |
5938 | /* Updating base_plus might destroy outval, see if we can | |
5939 | swap the scratch and base_plus. */ | |
5895f793 | 5940 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
5941 | { |
5942 | rtx tmp = scratch; | |
5943 | scratch = base_plus; | |
5944 | base_plus = tmp; | |
5945 | } | |
5946 | else | |
5947 | { | |
5948 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
5949 | ||
5950 | /* Be conservative and copy OUTVAL into the scratch now, | |
5951 | this should only be necessary if outval is a subreg | |
5952 | of something larger than a word. */ | |
5953 | /* XXX Might this clobber base? I can't see how it can, | |
5954 | since scratch is known to overlap with OUTVAL, and | |
5955 | must be wider than a word. */ | |
5956 | emit_insn (gen_movhi (scratch_hi, outval)); | |
5957 | outval = scratch_hi; | |
5958 | } | |
5959 | } | |
5960 | ||
5961 | emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); | |
5962 | base = base_plus; | |
5963 | } | |
5964 | else if (GET_CODE (base) == PLUS) | |
5965 | { | |
6354dc9b | 5966 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
5967 | HOST_WIDE_INT hi, lo; |
5968 | ||
5969 | offset += INTVAL (XEXP (base, 1)); | |
5970 | base = XEXP (base, 0); | |
5971 | ||
6354dc9b | 5972 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
5973 | /* Valid range for lo is -4095 -> 4095 */ |
5974 | lo = (offset >= 0 | |
5975 | ? (offset & 0xfff) | |
5976 | : -((-offset) & 0xfff)); | |
5977 | ||
5978 | /* Corner case, if lo is the max offset then we would be out of range | |
5979 | once we have added the additional 1 below, so bump the msb into the | |
5980 | pre-loading insn(s). */ | |
5981 | if (lo == 4095) | |
5982 | lo &= 0x7ff; | |
5983 | ||
30cf4896 KG |
5984 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
5985 | ^ (HOST_WIDE_INT) 0x80000000) | |
5986 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a RE |
5987 | |
5988 | if (hi + lo != offset) | |
5989 | abort (); | |
5990 | ||
5991 | if (hi != 0) | |
5992 | { | |
5993 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
5994 | ||
5995 | /* Be careful not to destroy OUTVAL. */ | |
5996 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
5997 | { | |
5998 | /* Updating base_plus might destroy outval, see if we | |
5999 | can swap the scratch and base_plus. */ | |
5895f793 | 6000 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
6001 | { |
6002 | rtx tmp = scratch; | |
6003 | scratch = base_plus; | |
6004 | base_plus = tmp; | |
6005 | } | |
6006 | else | |
6007 | { | |
6008 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
6009 | ||
6010 | /* Be conservative and copy outval into scratch now, | |
6011 | this should only be necessary if outval is a | |
6012 | subreg of something larger than a word. */ | |
6013 | /* XXX Might this clobber base? I can't see how it | |
6014 | can, since scratch is known to overlap with | |
6015 | outval. */ | |
6016 | emit_insn (gen_movhi (scratch_hi, outval)); | |
6017 | outval = scratch_hi; | |
6018 | } | |
6019 | } | |
6020 | ||
6021 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 6022 | that require more than one insn. */ |
f9cc092a RE |
6023 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
6024 | base = base_plus; | |
6025 | offset = lo; | |
6026 | } | |
6027 | } | |
af48348a | 6028 | |
b5cc037f RE |
6029 | if (BYTES_BIG_ENDIAN) |
6030 | { | |
f9cc092a RE |
6031 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
6032 | plus_constant (base, offset + 1)), | |
5d5603e2 | 6033 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
6034 | emit_insn (gen_lshrsi3 (scratch, |
6035 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 6036 | GEN_INT (8))); |
f9cc092a | 6037 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 6038 | gen_lowpart (QImode, scratch))); |
b5cc037f RE |
6039 | } |
6040 | else | |
6041 | { | |
f9cc092a | 6042 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 6043 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
6044 | emit_insn (gen_lshrsi3 (scratch, |
6045 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 6046 | GEN_INT (8))); |
f9cc092a RE |
6047 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
6048 | plus_constant (base, offset + 1)), | |
5d5603e2 | 6049 | gen_lowpart (QImode, scratch))); |
b5cc037f | 6050 | } |
af48348a | 6051 | } |
2b835d68 | 6052 | \f |
d5b7b3ae | 6053 | /* Print a symbolic form of X to the debug file, F. */ |
1d6e90ac | 6054 | |
d5b7b3ae RE |
6055 | static void |
6056 | arm_print_value (f, x) | |
6057 | FILE * f; | |
6058 | rtx x; | |
6059 | { | |
6060 | switch (GET_CODE (x)) | |
6061 | { | |
6062 | case CONST_INT: | |
6063 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
6064 | return; | |
6065 | ||
6066 | case CONST_DOUBLE: | |
6067 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
6068 | return; | |
6069 | ||
6070 | case CONST_STRING: | |
6071 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
6072 | return; | |
6073 | ||
6074 | case SYMBOL_REF: | |
6075 | fprintf (f, "`%s'", XSTR (x, 0)); | |
6076 | return; | |
6077 | ||
6078 | case LABEL_REF: | |
6079 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
6080 | return; | |
6081 | ||
6082 | case CONST: | |
6083 | arm_print_value (f, XEXP (x, 0)); | |
6084 | return; | |
6085 | ||
6086 | case PLUS: | |
6087 | arm_print_value (f, XEXP (x, 0)); | |
6088 | fprintf (f, "+"); | |
6089 | arm_print_value (f, XEXP (x, 1)); | |
6090 | return; | |
6091 | ||
6092 | case PC: | |
6093 | fprintf (f, "pc"); | |
6094 | return; | |
6095 | ||
6096 | default: | |
6097 | fprintf (f, "????"); | |
6098 | return; | |
6099 | } | |
6100 | } | |
6101 | \f | |
2b835d68 | 6102 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 6103 | |
949d79eb RE |
6104 | /* Arm instructions cannot load a large constant directly into a |
6105 | register; they have to come from a pc relative load. The constant | |
6106 | must therefore be placed in the addressable range of the pc | |
6107 | relative load. Depending on the precise pc relative load | |
6108 | instruction the range is somewhere between 256 bytes and 4k. This | |
6109 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
6110 | generate code to branch around it. |
6111 | ||
949d79eb RE |
6112 | It is important to minimize this, since the branches will slow |
6113 | things down and make the code larger. | |
2b835d68 | 6114 | |
949d79eb RE |
6115 | Normally we can hide the table after an existing unconditional |
6116 | branch so that there is no interruption of the flow, but in the | |
6117 | worst case the code looks like this: | |
2b835d68 RE |
6118 | |
6119 | ldr rn, L1 | |
949d79eb | 6120 | ... |
2b835d68 RE |
6121 | b L2 |
6122 | align | |
6123 | L1: .long value | |
6124 | L2: | |
949d79eb | 6125 | ... |
2b835d68 | 6126 | |
2b835d68 | 6127 | ldr rn, L3 |
949d79eb | 6128 | ... |
2b835d68 RE |
6129 | b L4 |
6130 | align | |
2b835d68 RE |
6131 | L3: .long value |
6132 | L4: | |
949d79eb RE |
6133 | ... |
6134 | ||
6135 | We fix this by performing a scan after scheduling, which notices | |
6136 | which instructions need to have their operands fetched from the | |
6137 | constant table and builds the table. | |
6138 | ||
6139 | The algorithm starts by building a table of all the constants that | |
6140 | need fixing up and all the natural barriers in the function (places | |
6141 | where a constant table can be dropped without breaking the flow). | |
6142 | For each fixup we note how far the pc-relative replacement will be | |
6143 | able to reach and the offset of the instruction into the function. | |
6144 | ||
6145 | Having built the table we then group the fixes together to form | |
6146 | tables that are as large as possible (subject to addressing | |
6147 | constraints) and emit each table of constants after the last | |
6148 | barrier that is within range of all the instructions in the group. | |
6149 | If a group does not contain a barrier, then we forcibly create one | |
6150 | by inserting a jump instruction into the flow. Once the table has | |
6151 | been inserted, the insns are then modified to reference the | |
6152 | relevant entry in the pool. | |
6153 | ||
6354dc9b | 6154 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 6155 | |
d5b7b3ae | 6156 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
6157 | aligning the pools to the start of cache lines; this alignment |
6158 | would need to be taken into account when calculating addressability | |
6354dc9b | 6159 | of a pool. */ |
2b835d68 | 6160 | |
d5b7b3ae RE |
6161 | /* These typedefs are located at the start of this file, so that |
6162 | they can be used in the prototypes there. This comment is to | |
6163 | remind readers of that fact so that the following structures | |
6164 | can be understood more easily. | |
6165 | ||
6166 | typedef struct minipool_node Mnode; | |
6167 | typedef struct minipool_fixup Mfix; */ | |
6168 | ||
6169 | struct minipool_node | |
6170 | { | |
6171 | /* Doubly linked chain of entries. */ | |
6172 | Mnode * next; | |
6173 | Mnode * prev; | |
6174 | /* The maximum offset into the code that this entry can be placed. While | |
6175 | pushing fixes for forward references, all entries are sorted in order | |
6176 | of increasing max_address. */ | |
6177 | HOST_WIDE_INT max_address; | |
5519a4f9 | 6178 | /* Similarly for an entry inserted for a backwards ref. */ |
d5b7b3ae RE |
6179 | HOST_WIDE_INT min_address; |
6180 | /* The number of fixes referencing this entry. This can become zero | |
6181 | if we "unpush" an entry. In this case we ignore the entry when we | |
6182 | come to emit the code. */ | |
6183 | int refcount; | |
6184 | /* The offset from the start of the minipool. */ | |
6185 | HOST_WIDE_INT offset; | |
6186 | /* The value in table. */ | |
6187 | rtx value; | |
6188 | /* The mode of value. */ | |
6189 | enum machine_mode mode; | |
6190 | int fix_size; | |
6191 | }; | |
6192 | ||
6193 | struct minipool_fixup | |
2b835d68 | 6194 | { |
d5b7b3ae RE |
6195 | Mfix * next; |
6196 | rtx insn; | |
6197 | HOST_WIDE_INT address; | |
6198 | rtx * loc; | |
6199 | enum machine_mode mode; | |
6200 | int fix_size; | |
6201 | rtx value; | |
6202 | Mnode * minipool; | |
6203 | HOST_WIDE_INT forwards; | |
6204 | HOST_WIDE_INT backwards; | |
6205 | }; | |
2b835d68 | 6206 | |
d5b7b3ae RE |
6207 | /* Fixes less than a word need padding out to a word boundary. */ |
6208 | #define MINIPOOL_FIX_SIZE(mode) \ | |
6209 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 6210 | |
d5b7b3ae RE |
6211 | static Mnode * minipool_vector_head; |
6212 | static Mnode * minipool_vector_tail; | |
6213 | static rtx minipool_vector_label; | |
332072db | 6214 | |
d5b7b3ae RE |
6215 | /* The linked list of all minipool fixes required for this function. */ |
6216 | Mfix * minipool_fix_head; | |
6217 | Mfix * minipool_fix_tail; | |
6218 | /* The fix entry for the current minipool, once it has been placed. */ | |
6219 | Mfix * minipool_barrier; | |
6220 | ||
6221 | /* Determines if INSN is the start of a jump table. Returns the end | |
6222 | of the TABLE or NULL_RTX. */ | |
1d6e90ac | 6223 | |
d5b7b3ae RE |
6224 | static rtx |
6225 | is_jump_table (insn) | |
6226 | rtx insn; | |
2b835d68 | 6227 | { |
d5b7b3ae | 6228 | rtx table; |
da6558fd | 6229 | |
d5b7b3ae RE |
6230 | if (GET_CODE (insn) == JUMP_INSN |
6231 | && JUMP_LABEL (insn) != NULL | |
6232 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
6233 | == next_real_insn (insn)) | |
6234 | && table != NULL | |
6235 | && GET_CODE (table) == JUMP_INSN | |
6236 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
6237 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
6238 | return table; | |
6239 | ||
6240 | return NULL_RTX; | |
2b835d68 RE |
6241 | } |
6242 | ||
657d9449 RE |
6243 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
6244 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
6245 | #endif | |
6246 | ||
d5b7b3ae RE |
6247 | static HOST_WIDE_INT |
6248 | get_jump_table_size (insn) | |
6249 | rtx insn; | |
2b835d68 | 6250 | { |
657d9449 RE |
6251 | /* ADDR_VECs only take room if read-only data does into the text |
6252 | section. */ | |
6253 | if (JUMP_TABLES_IN_TEXT_SECTION | |
d48bc59a | 6254 | #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP) |
657d9449 RE |
6255 | || 1 |
6256 | #endif | |
6257 | ) | |
6258 | { | |
6259 | rtx body = PATTERN (insn); | |
6260 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
2b835d68 | 6261 | |
657d9449 RE |
6262 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt); |
6263 | } | |
6264 | ||
6265 | return 0; | |
d5b7b3ae | 6266 | } |
2b835d68 | 6267 | |
d5b7b3ae RE |
6268 | /* Move a minipool fix MP from its current location to before MAX_MP. |
6269 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
6270 | contrains may need updating. */ | |
1d6e90ac | 6271 | |
d5b7b3ae RE |
6272 | static Mnode * |
6273 | move_minipool_fix_forward_ref (mp, max_mp, max_address) | |
6274 | Mnode * mp; | |
6275 | Mnode * max_mp; | |
6276 | HOST_WIDE_INT max_address; | |
6277 | { | |
6278 | /* This should never be true and the code below assumes these are | |
6279 | different. */ | |
6280 | if (mp == max_mp) | |
6281 | abort (); | |
6282 | ||
6283 | if (max_mp == NULL) | |
6284 | { | |
6285 | if (max_address < mp->max_address) | |
6286 | mp->max_address = max_address; | |
6287 | } | |
6288 | else | |
2b835d68 | 6289 | { |
d5b7b3ae RE |
6290 | if (max_address > max_mp->max_address - mp->fix_size) |
6291 | mp->max_address = max_mp->max_address - mp->fix_size; | |
6292 | else | |
6293 | mp->max_address = max_address; | |
2b835d68 | 6294 | |
d5b7b3ae RE |
6295 | /* Unlink MP from its current position. Since max_mp is non-null, |
6296 | mp->prev must be non-null. */ | |
6297 | mp->prev->next = mp->next; | |
6298 | if (mp->next != NULL) | |
6299 | mp->next->prev = mp->prev; | |
6300 | else | |
6301 | minipool_vector_tail = mp->prev; | |
2b835d68 | 6302 | |
d5b7b3ae RE |
6303 | /* Re-insert it before MAX_MP. */ |
6304 | mp->next = max_mp; | |
6305 | mp->prev = max_mp->prev; | |
6306 | max_mp->prev = mp; | |
6307 | ||
6308 | if (mp->prev != NULL) | |
6309 | mp->prev->next = mp; | |
6310 | else | |
6311 | minipool_vector_head = mp; | |
6312 | } | |
2b835d68 | 6313 | |
d5b7b3ae RE |
6314 | /* Save the new entry. */ |
6315 | max_mp = mp; | |
6316 | ||
d6a7951f | 6317 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
6318 | required. */ |
6319 | while (mp->prev != NULL | |
6320 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
6321 | { | |
6322 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
6323 | mp = mp->prev; | |
2b835d68 RE |
6324 | } |
6325 | ||
d5b7b3ae | 6326 | return max_mp; |
2b835d68 RE |
6327 | } |
6328 | ||
d5b7b3ae RE |
6329 | /* Add a constant to the minipool for a forward reference. Returns the |
6330 | node added or NULL if the constant will not fit in this pool. */ | |
1d6e90ac | 6331 | |
d5b7b3ae RE |
6332 | static Mnode * |
6333 | add_minipool_forward_ref (fix) | |
6334 | Mfix * fix; | |
6335 | { | |
6336 | /* If set, max_mp is the first pool_entry that has a lower | |
6337 | constraint than the one we are trying to add. */ | |
6338 | Mnode * max_mp = NULL; | |
6339 | HOST_WIDE_INT max_address = fix->address + fix->forwards; | |
6340 | Mnode * mp; | |
6341 | ||
6342 | /* If this fix's address is greater than the address of the first | |
6343 | entry, then we can't put the fix in this pool. We subtract the | |
6344 | size of the current fix to ensure that if the table is fully | |
6345 | packed we still have enough room to insert this value by suffling | |
6346 | the other fixes forwards. */ | |
6347 | if (minipool_vector_head && | |
6348 | fix->address >= minipool_vector_head->max_address - fix->fix_size) | |
6349 | return NULL; | |
2b835d68 | 6350 | |
d5b7b3ae RE |
6351 | /* Scan the pool to see if a constant with the same value has |
6352 | already been added. While we are doing this, also note the | |
6353 | location where we must insert the constant if it doesn't already | |
6354 | exist. */ | |
6355 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
6356 | { | |
6357 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
6358 | && fix->mode == mp->mode | |
6359 | && (GET_CODE (fix->value) != CODE_LABEL | |
6360 | || (CODE_LABEL_NUMBER (fix->value) | |
6361 | == CODE_LABEL_NUMBER (mp->value))) | |
6362 | && rtx_equal_p (fix->value, mp->value)) | |
6363 | { | |
6364 | /* More than one fix references this entry. */ | |
6365 | mp->refcount++; | |
6366 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
6367 | } | |
6368 | ||
6369 | /* Note the insertion point if necessary. */ | |
6370 | if (max_mp == NULL | |
6371 | && mp->max_address > max_address) | |
6372 | max_mp = mp; | |
6373 | } | |
6374 | ||
6375 | /* The value is not currently in the minipool, so we need to create | |
6376 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
6377 | the end of the list since the placement is less constrained than | |
6378 | any existing entry. Otherwise, we insert the new fix before | |
6bc82793 | 6379 | MAX_MP and, if necessary, adjust the constraints on the other |
d5b7b3ae RE |
6380 | entries. */ |
6381 | mp = xmalloc (sizeof (* mp)); | |
6382 | mp->fix_size = fix->fix_size; | |
6383 | mp->mode = fix->mode; | |
6384 | mp->value = fix->value; | |
6385 | mp->refcount = 1; | |
6386 | /* Not yet required for a backwards ref. */ | |
6387 | mp->min_address = -65536; | |
6388 | ||
6389 | if (max_mp == NULL) | |
6390 | { | |
6391 | mp->max_address = max_address; | |
6392 | mp->next = NULL; | |
6393 | mp->prev = minipool_vector_tail; | |
6394 | ||
6395 | if (mp->prev == NULL) | |
6396 | { | |
6397 | minipool_vector_head = mp; | |
6398 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 6399 | } |
2b835d68 | 6400 | else |
d5b7b3ae | 6401 | mp->prev->next = mp; |
2b835d68 | 6402 | |
d5b7b3ae RE |
6403 | minipool_vector_tail = mp; |
6404 | } | |
6405 | else | |
6406 | { | |
6407 | if (max_address > max_mp->max_address - mp->fix_size) | |
6408 | mp->max_address = max_mp->max_address - mp->fix_size; | |
6409 | else | |
6410 | mp->max_address = max_address; | |
6411 | ||
6412 | mp->next = max_mp; | |
6413 | mp->prev = max_mp->prev; | |
6414 | max_mp->prev = mp; | |
6415 | if (mp->prev != NULL) | |
6416 | mp->prev->next = mp; | |
6417 | else | |
6418 | minipool_vector_head = mp; | |
6419 | } | |
6420 | ||
6421 | /* Save the new entry. */ | |
6422 | max_mp = mp; | |
6423 | ||
d6a7951f | 6424 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
6425 | required. */ |
6426 | while (mp->prev != NULL | |
6427 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
6428 | { | |
6429 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
6430 | mp = mp->prev; | |
2b835d68 RE |
6431 | } |
6432 | ||
d5b7b3ae RE |
6433 | return max_mp; |
6434 | } | |
6435 | ||
6436 | static Mnode * | |
6437 | move_minipool_fix_backward_ref (mp, min_mp, min_address) | |
6438 | Mnode * mp; | |
6439 | Mnode * min_mp; | |
6440 | HOST_WIDE_INT min_address; | |
6441 | { | |
6442 | HOST_WIDE_INT offset; | |
6443 | ||
6444 | /* This should never be true, and the code below assumes these are | |
6445 | different. */ | |
6446 | if (mp == min_mp) | |
6447 | abort (); | |
6448 | ||
6449 | if (min_mp == NULL) | |
2b835d68 | 6450 | { |
d5b7b3ae RE |
6451 | if (min_address > mp->min_address) |
6452 | mp->min_address = min_address; | |
6453 | } | |
6454 | else | |
6455 | { | |
6456 | /* We will adjust this below if it is too loose. */ | |
6457 | mp->min_address = min_address; | |
6458 | ||
6459 | /* Unlink MP from its current position. Since min_mp is non-null, | |
6460 | mp->next must be non-null. */ | |
6461 | mp->next->prev = mp->prev; | |
6462 | if (mp->prev != NULL) | |
6463 | mp->prev->next = mp->next; | |
6464 | else | |
6465 | minipool_vector_head = mp->next; | |
6466 | ||
6467 | /* Reinsert it after MIN_MP. */ | |
6468 | mp->prev = min_mp; | |
6469 | mp->next = min_mp->next; | |
6470 | min_mp->next = mp; | |
6471 | if (mp->next != NULL) | |
6472 | mp->next->prev = mp; | |
2b835d68 | 6473 | else |
d5b7b3ae RE |
6474 | minipool_vector_tail = mp; |
6475 | } | |
6476 | ||
6477 | min_mp = mp; | |
6478 | ||
6479 | offset = 0; | |
6480 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
6481 | { | |
6482 | mp->offset = offset; | |
6483 | if (mp->refcount > 0) | |
6484 | offset += mp->fix_size; | |
6485 | ||
6486 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
6487 | mp->next->min_address = mp->min_address + mp->fix_size; | |
6488 | } | |
6489 | ||
6490 | return min_mp; | |
6491 | } | |
6492 | ||
6493 | /* Add a constant to the minipool for a backward reference. Returns the | |
6494 | node added or NULL if the constant will not fit in this pool. | |
6495 | ||
6496 | Note that the code for insertion for a backwards reference can be | |
6497 | somewhat confusing because the calculated offsets for each fix do | |
6498 | not take into account the size of the pool (which is still under | |
6499 | construction. */ | |
1d6e90ac | 6500 | |
d5b7b3ae RE |
6501 | static Mnode * |
6502 | add_minipool_backward_ref (fix) | |
6503 | Mfix * fix; | |
6504 | { | |
6505 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
6506 | than the one we are trying to add. */ | |
6507 | Mnode * min_mp = NULL; | |
6508 | /* This can be negative, since it is only a constraint. */ | |
6509 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
6510 | Mnode * mp; | |
6511 | ||
6512 | /* If we can't reach the current pool from this insn, or if we can't | |
6513 | insert this entry at the end of the pool without pushing other | |
6514 | fixes out of range, then we don't try. This ensures that we | |
6515 | can't fail later on. */ | |
6516 | if (min_address >= minipool_barrier->address | |
6517 | || (minipool_vector_tail->min_address + fix->fix_size | |
6518 | >= minipool_barrier->address)) | |
6519 | return NULL; | |
6520 | ||
6521 | /* Scan the pool to see if a constant with the same value has | |
6522 | already been added. While we are doing this, also note the | |
6523 | location where we must insert the constant if it doesn't already | |
6524 | exist. */ | |
6525 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
6526 | { | |
6527 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
6528 | && fix->mode == mp->mode | |
6529 | && (GET_CODE (fix->value) != CODE_LABEL | |
6530 | || (CODE_LABEL_NUMBER (fix->value) | |
6531 | == CODE_LABEL_NUMBER (mp->value))) | |
6532 | && rtx_equal_p (fix->value, mp->value) | |
6533 | /* Check that there is enough slack to move this entry to the | |
6534 | end of the table (this is conservative). */ | |
6535 | && (mp->max_address | |
6536 | > (minipool_barrier->address | |
6537 | + minipool_vector_tail->offset | |
6538 | + minipool_vector_tail->fix_size))) | |
6539 | { | |
6540 | mp->refcount++; | |
6541 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
6542 | } | |
6543 | ||
6544 | if (min_mp != NULL) | |
6545 | mp->min_address += fix->fix_size; | |
6546 | else | |
6547 | { | |
6548 | /* Note the insertion point if necessary. */ | |
6549 | if (mp->min_address < min_address) | |
6550 | min_mp = mp; | |
6551 | else if (mp->max_address | |
6552 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
6553 | { | |
6554 | /* Inserting before this entry would push the fix beyond | |
6555 | its maximum address (which can happen if we have | |
6556 | re-located a forwards fix); force the new fix to come | |
6557 | after it. */ | |
6558 | min_mp = mp; | |
6559 | min_address = mp->min_address + fix->fix_size; | |
6560 | } | |
6561 | } | |
6562 | } | |
6563 | ||
6564 | /* We need to create a new entry. */ | |
6565 | mp = xmalloc (sizeof (* mp)); | |
6566 | mp->fix_size = fix->fix_size; | |
6567 | mp->mode = fix->mode; | |
6568 | mp->value = fix->value; | |
6569 | mp->refcount = 1; | |
6570 | mp->max_address = minipool_barrier->address + 65536; | |
6571 | ||
6572 | mp->min_address = min_address; | |
6573 | ||
6574 | if (min_mp == NULL) | |
6575 | { | |
6576 | mp->prev = NULL; | |
6577 | mp->next = minipool_vector_head; | |
6578 | ||
6579 | if (mp->next == NULL) | |
6580 | { | |
6581 | minipool_vector_tail = mp; | |
6582 | minipool_vector_label = gen_label_rtx (); | |
6583 | } | |
6584 | else | |
6585 | mp->next->prev = mp; | |
6586 | ||
6587 | minipool_vector_head = mp; | |
6588 | } | |
6589 | else | |
6590 | { | |
6591 | mp->next = min_mp->next; | |
6592 | mp->prev = min_mp; | |
6593 | min_mp->next = mp; | |
da6558fd | 6594 | |
d5b7b3ae RE |
6595 | if (mp->next != NULL) |
6596 | mp->next->prev = mp; | |
6597 | else | |
6598 | minipool_vector_tail = mp; | |
6599 | } | |
6600 | ||
6601 | /* Save the new entry. */ | |
6602 | min_mp = mp; | |
6603 | ||
6604 | if (mp->prev) | |
6605 | mp = mp->prev; | |
6606 | else | |
6607 | mp->offset = 0; | |
6608 | ||
6609 | /* Scan over the following entries and adjust their offsets. */ | |
6610 | while (mp->next != NULL) | |
6611 | { | |
6612 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
6613 | mp->next->min_address = mp->min_address + mp->fix_size; | |
6614 | ||
6615 | if (mp->refcount) | |
6616 | mp->next->offset = mp->offset + mp->fix_size; | |
6617 | else | |
6618 | mp->next->offset = mp->offset; | |
6619 | ||
6620 | mp = mp->next; | |
6621 | } | |
6622 | ||
6623 | return min_mp; | |
6624 | } | |
6625 | ||
6626 | static void | |
6627 | assign_minipool_offsets (barrier) | |
6628 | Mfix * barrier; | |
6629 | { | |
6630 | HOST_WIDE_INT offset = 0; | |
6631 | Mnode * mp; | |
6632 | ||
6633 | minipool_barrier = barrier; | |
6634 | ||
6635 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
6636 | { | |
6637 | mp->offset = offset; | |
da6558fd | 6638 | |
d5b7b3ae RE |
6639 | if (mp->refcount > 0) |
6640 | offset += mp->fix_size; | |
6641 | } | |
6642 | } | |
6643 | ||
6644 | /* Output the literal table */ | |
6645 | static void | |
6646 | dump_minipool (scan) | |
6647 | rtx scan; | |
6648 | { | |
6649 | Mnode * mp; | |
6650 | Mnode * nmp; | |
6651 | ||
6652 | if (rtl_dump_file) | |
6653 | fprintf (rtl_dump_file, | |
6654 | ";; Emitting minipool after insn %u; address %ld\n", | |
6655 | INSN_UID (scan), (unsigned long) minipool_barrier->address); | |
6656 | ||
6657 | scan = emit_label_after (gen_label_rtx (), scan); | |
6658 | scan = emit_insn_after (gen_align_4 (), scan); | |
6659 | scan = emit_label_after (minipool_vector_label, scan); | |
6660 | ||
6661 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
6662 | { | |
6663 | if (mp->refcount > 0) | |
6664 | { | |
6665 | if (rtl_dump_file) | |
6666 | { | |
6667 | fprintf (rtl_dump_file, | |
6668 | ";; Offset %u, min %ld, max %ld ", | |
6669 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
6670 | (unsigned long) mp->max_address); | |
6671 | arm_print_value (rtl_dump_file, mp->value); | |
6672 | fputc ('\n', rtl_dump_file); | |
6673 | } | |
6674 | ||
6675 | switch (mp->fix_size) | |
6676 | { | |
6677 | #ifdef HAVE_consttable_1 | |
6678 | case 1: | |
6679 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
6680 | break; | |
6681 | ||
6682 | #endif | |
6683 | #ifdef HAVE_consttable_2 | |
6684 | case 2: | |
6685 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
6686 | break; | |
6687 | ||
6688 | #endif | |
6689 | #ifdef HAVE_consttable_4 | |
6690 | case 4: | |
6691 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
6692 | break; | |
6693 | ||
6694 | #endif | |
6695 | #ifdef HAVE_consttable_8 | |
6696 | case 8: | |
6697 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
6698 | break; | |
6699 | ||
6700 | #endif | |
6701 | default: | |
6702 | abort (); | |
6703 | break; | |
6704 | } | |
6705 | } | |
6706 | ||
6707 | nmp = mp->next; | |
6708 | free (mp); | |
2b835d68 RE |
6709 | } |
6710 | ||
d5b7b3ae RE |
6711 | minipool_vector_head = minipool_vector_tail = NULL; |
6712 | scan = emit_insn_after (gen_consttable_end (), scan); | |
6713 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
6714 | } |
6715 | ||
d5b7b3ae | 6716 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
1d6e90ac | 6717 | |
d5b7b3ae RE |
6718 | static int |
6719 | arm_barrier_cost (insn) | |
6720 | rtx insn; | |
949d79eb | 6721 | { |
d5b7b3ae RE |
6722 | /* Basing the location of the pool on the loop depth is preferable, |
6723 | but at the moment, the basic block information seems to be | |
6724 | corrupt by this stage of the compilation. */ | |
6725 | int base_cost = 50; | |
6726 | rtx next = next_nonnote_insn (insn); | |
6727 | ||
6728 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
6729 | base_cost -= 20; | |
6730 | ||
6731 | switch (GET_CODE (insn)) | |
6732 | { | |
6733 | case CODE_LABEL: | |
6734 | /* It will always be better to place the table before the label, rather | |
6735 | than after it. */ | |
6736 | return 50; | |
949d79eb | 6737 | |
d5b7b3ae RE |
6738 | case INSN: |
6739 | case CALL_INSN: | |
6740 | return base_cost; | |
6741 | ||
6742 | case JUMP_INSN: | |
6743 | return base_cost - 10; | |
6744 | ||
6745 | default: | |
6746 | return base_cost + 10; | |
6747 | } | |
6748 | } | |
6749 | ||
6750 | /* Find the best place in the insn stream in the range | |
6751 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
6752 | Create the barrier by inserting a jump and add a new fix entry for | |
6753 | it. */ | |
1d6e90ac | 6754 | |
d5b7b3ae RE |
6755 | static Mfix * |
6756 | create_fix_barrier (fix, max_address) | |
6757 | Mfix * fix; | |
6758 | HOST_WIDE_INT max_address; | |
6759 | { | |
6760 | HOST_WIDE_INT count = 0; | |
6761 | rtx barrier; | |
6762 | rtx from = fix->insn; | |
6763 | rtx selected = from; | |
6764 | int selected_cost; | |
6765 | HOST_WIDE_INT selected_address; | |
6766 | Mfix * new_fix; | |
6767 | HOST_WIDE_INT max_count = max_address - fix->address; | |
6768 | rtx label = gen_label_rtx (); | |
6769 | ||
6770 | selected_cost = arm_barrier_cost (from); | |
6771 | selected_address = fix->address; | |
6772 | ||
6773 | while (from && count < max_count) | |
6774 | { | |
6775 | rtx tmp; | |
6776 | int new_cost; | |
6777 | ||
6778 | /* This code shouldn't have been called if there was a natural barrier | |
6779 | within range. */ | |
6780 | if (GET_CODE (from) == BARRIER) | |
6781 | abort (); | |
6782 | ||
6783 | /* Count the length of this insn. */ | |
6784 | count += get_attr_length (from); | |
6785 | ||
6786 | /* If there is a jump table, add its length. */ | |
6787 | tmp = is_jump_table (from); | |
6788 | if (tmp != NULL) | |
6789 | { | |
6790 | count += get_jump_table_size (tmp); | |
6791 | ||
6792 | /* Jump tables aren't in a basic block, so base the cost on | |
6793 | the dispatch insn. If we select this location, we will | |
6794 | still put the pool after the table. */ | |
6795 | new_cost = arm_barrier_cost (from); | |
6796 | ||
6797 | if (count < max_count && new_cost <= selected_cost) | |
6798 | { | |
6799 | selected = tmp; | |
6800 | selected_cost = new_cost; | |
6801 | selected_address = fix->address + count; | |
6802 | } | |
6803 | ||
6804 | /* Continue after the dispatch table. */ | |
6805 | from = NEXT_INSN (tmp); | |
6806 | continue; | |
6807 | } | |
6808 | ||
6809 | new_cost = arm_barrier_cost (from); | |
6810 | ||
6811 | if (count < max_count && new_cost <= selected_cost) | |
6812 | { | |
6813 | selected = from; | |
6814 | selected_cost = new_cost; | |
6815 | selected_address = fix->address + count; | |
6816 | } | |
6817 | ||
6818 | from = NEXT_INSN (from); | |
6819 | } | |
6820 | ||
6821 | /* Create a new JUMP_INSN that branches around a barrier. */ | |
6822 | from = emit_jump_insn_after (gen_jump (label), selected); | |
6823 | JUMP_LABEL (from) = label; | |
6824 | barrier = emit_barrier_after (from); | |
6825 | emit_label_after (label, barrier); | |
6826 | ||
6827 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 6828 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
6829 | new_fix->insn = barrier; |
6830 | new_fix->address = selected_address; | |
6831 | new_fix->next = fix->next; | |
6832 | fix->next = new_fix; | |
6833 | ||
6834 | return new_fix; | |
6835 | } | |
6836 | ||
6837 | /* Record that there is a natural barrier in the insn stream at | |
6838 | ADDRESS. */ | |
949d79eb RE |
6839 | static void |
6840 | push_minipool_barrier (insn, address) | |
2b835d68 | 6841 | rtx insn; |
d5b7b3ae | 6842 | HOST_WIDE_INT address; |
2b835d68 | 6843 | { |
c7319d87 | 6844 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 6845 | |
949d79eb RE |
6846 | fix->insn = insn; |
6847 | fix->address = address; | |
2b835d68 | 6848 | |
949d79eb RE |
6849 | fix->next = NULL; |
6850 | if (minipool_fix_head != NULL) | |
6851 | minipool_fix_tail->next = fix; | |
6852 | else | |
6853 | minipool_fix_head = fix; | |
6854 | ||
6855 | minipool_fix_tail = fix; | |
6856 | } | |
2b835d68 | 6857 | |
d5b7b3ae RE |
6858 | /* Record INSN, which will need fixing up to load a value from the |
6859 | minipool. ADDRESS is the offset of the insn since the start of the | |
6860 | function; LOC is a pointer to the part of the insn which requires | |
6861 | fixing; VALUE is the constant that must be loaded, which is of type | |
6862 | MODE. */ | |
949d79eb RE |
6863 | static void |
6864 | push_minipool_fix (insn, address, loc, mode, value) | |
6865 | rtx insn; | |
d5b7b3ae RE |
6866 | HOST_WIDE_INT address; |
6867 | rtx * loc; | |
949d79eb RE |
6868 | enum machine_mode mode; |
6869 | rtx value; | |
6870 | { | |
c7319d87 | 6871 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb RE |
6872 | |
6873 | #ifdef AOF_ASSEMBLER | |
6874 | /* PIC symbol refereneces need to be converted into offsets into the | |
6875 | based area. */ | |
d5b7b3ae RE |
6876 | /* XXX This shouldn't be done here. */ |
6877 | if (flag_pic && GET_CODE (value) == SYMBOL_REF) | |
949d79eb RE |
6878 | value = aof_pic_entry (value); |
6879 | #endif /* AOF_ASSEMBLER */ | |
6880 | ||
6881 | fix->insn = insn; | |
6882 | fix->address = address; | |
6883 | fix->loc = loc; | |
6884 | fix->mode = mode; | |
d5b7b3ae | 6885 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 6886 | fix->value = value; |
d5b7b3ae RE |
6887 | fix->forwards = get_attr_pool_range (insn); |
6888 | fix->backwards = get_attr_neg_pool_range (insn); | |
6889 | fix->minipool = NULL; | |
949d79eb RE |
6890 | |
6891 | /* If an insn doesn't have a range defined for it, then it isn't | |
6892 | expecting to be reworked by this code. Better to abort now than | |
6893 | to generate duff assembly code. */ | |
d5b7b3ae | 6894 | if (fix->forwards == 0 && fix->backwards == 0) |
949d79eb RE |
6895 | abort (); |
6896 | ||
d5b7b3ae RE |
6897 | if (rtl_dump_file) |
6898 | { | |
6899 | fprintf (rtl_dump_file, | |
6900 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", | |
6901 | GET_MODE_NAME (mode), | |
6902 | INSN_UID (insn), (unsigned long) address, | |
6903 | -1 * (long)fix->backwards, (long)fix->forwards); | |
6904 | arm_print_value (rtl_dump_file, fix->value); | |
6905 | fprintf (rtl_dump_file, "\n"); | |
6906 | } | |
6907 | ||
6354dc9b | 6908 | /* Add it to the chain of fixes. */ |
949d79eb | 6909 | fix->next = NULL; |
d5b7b3ae | 6910 | |
949d79eb RE |
6911 | if (minipool_fix_head != NULL) |
6912 | minipool_fix_tail->next = fix; | |
6913 | else | |
6914 | minipool_fix_head = fix; | |
6915 | ||
6916 | minipool_fix_tail = fix; | |
6917 | } | |
6918 | ||
f0375c66 NC |
6919 | /* Scan INSN and note any of its operands that need fixing. |
6920 | If DO_PUSHES is false we do not actually push any of the fixups | |
6921 | needed. The function returns TRUE is any fixups were needed/pushed. | |
6922 | This is used by arm_memory_load_p() which needs to know about loads | |
6923 | of constants that will be converted into minipool loads. */ | |
1d6e90ac | 6924 | |
f0375c66 NC |
6925 | static bool |
6926 | note_invalid_constants (insn, address, do_pushes) | |
949d79eb | 6927 | rtx insn; |
d5b7b3ae | 6928 | HOST_WIDE_INT address; |
b93828f3 | 6929 | int do_pushes; |
949d79eb | 6930 | { |
f0375c66 | 6931 | bool result = false; |
949d79eb RE |
6932 | int opno; |
6933 | ||
d5b7b3ae | 6934 | extract_insn (insn); |
949d79eb | 6935 | |
5895f793 | 6936 | if (!constrain_operands (1)) |
949d79eb RE |
6937 | fatal_insn_not_found (insn); |
6938 | ||
f0375c66 | 6939 | /* Fill in recog_op_alt with information about the constraints of this insn. */ |
949d79eb RE |
6940 | preprocess_constraints (); |
6941 | ||
1ccbefce | 6942 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 6943 | { |
6354dc9b | 6944 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 6945 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
6946 | continue; |
6947 | ||
6948 | /* If this alternative is a memory reference, then any mention | |
6949 | of constants in this alternative is really to fool reload | |
6950 | into allowing us to accept one there. We need to fix them up | |
6951 | now so that we output the right code. */ | |
6952 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
6953 | { | |
1ccbefce | 6954 | rtx op = recog_data.operand[opno]; |
949d79eb RE |
6955 | |
6956 | if (CONSTANT_P (op)) | |
f0375c66 NC |
6957 | { |
6958 | if (do_pushes) | |
6959 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
6960 | recog_data.operand_mode[opno], op); | |
6961 | result = true; | |
6962 | } | |
d5b7b3ae | 6963 | else if (GET_CODE (op) == MEM |
949d79eb RE |
6964 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
6965 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
f0375c66 NC |
6966 | { |
6967 | if (do_pushes) | |
6968 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
6969 | recog_data.operand_mode[opno], | |
6970 | get_pool_constant (XEXP (op, 0))); | |
6971 | ||
6972 | result = true; | |
6973 | } | |
949d79eb | 6974 | } |
2b835d68 | 6975 | } |
f0375c66 NC |
6976 | |
6977 | return result; | |
2b835d68 RE |
6978 | } |
6979 | ||
6980 | void | |
6981 | arm_reorg (first) | |
6982 | rtx first; | |
6983 | { | |
6984 | rtx insn; | |
d5b7b3ae RE |
6985 | HOST_WIDE_INT address = 0; |
6986 | Mfix * fix; | |
ad076f4e | 6987 | |
949d79eb | 6988 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 6989 | |
949d79eb RE |
6990 | /* The first insn must always be a note, or the code below won't |
6991 | scan it properly. */ | |
6992 | if (GET_CODE (first) != NOTE) | |
6993 | abort (); | |
6994 | ||
6995 | /* Scan all the insns and record the operands that will need fixing. */ | |
6996 | for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn)) | |
2b835d68 | 6997 | { |
9b6b54e2 | 6998 | if (TARGET_CIRRUS_FIX_INVALID_INSNS |
f0375c66 | 6999 | && (arm_cirrus_insn_p (insn) |
9b6b54e2 | 7000 | || GET_CODE (insn) == JUMP_INSN |
f0375c66 | 7001 | || arm_memory_load_p (insn))) |
9b6b54e2 NC |
7002 | cirrus_reorg (insn); |
7003 | ||
949d79eb | 7004 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 7005 | push_minipool_barrier (insn, address); |
f0375c66 | 7006 | else if (INSN_P (insn)) |
949d79eb RE |
7007 | { |
7008 | rtx table; | |
7009 | ||
f0375c66 | 7010 | note_invalid_constants (insn, address, true); |
949d79eb | 7011 | address += get_attr_length (insn); |
d5b7b3ae | 7012 | |
949d79eb RE |
7013 | /* If the insn is a vector jump, add the size of the table |
7014 | and skip the table. */ | |
d5b7b3ae | 7015 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 7016 | { |
d5b7b3ae | 7017 | address += get_jump_table_size (table); |
949d79eb RE |
7018 | insn = table; |
7019 | } | |
7020 | } | |
7021 | } | |
332072db | 7022 | |
d5b7b3ae RE |
7023 | fix = minipool_fix_head; |
7024 | ||
949d79eb | 7025 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 7026 | while (fix) |
949d79eb | 7027 | { |
d5b7b3ae RE |
7028 | Mfix * ftmp; |
7029 | Mfix * fdel; | |
7030 | Mfix * last_added_fix; | |
7031 | Mfix * last_barrier = NULL; | |
7032 | Mfix * this_fix; | |
949d79eb RE |
7033 | |
7034 | /* Skip any further barriers before the next fix. */ | |
7035 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
7036 | fix = fix->next; | |
7037 | ||
d5b7b3ae | 7038 | /* No more fixes. */ |
949d79eb RE |
7039 | if (fix == NULL) |
7040 | break; | |
332072db | 7041 | |
d5b7b3ae | 7042 | last_added_fix = NULL; |
2b835d68 | 7043 | |
d5b7b3ae | 7044 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 7045 | { |
949d79eb | 7046 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 7047 | { |
d5b7b3ae RE |
7048 | if (ftmp->address >= minipool_vector_head->max_address) |
7049 | break; | |
2b835d68 | 7050 | |
d5b7b3ae | 7051 | last_barrier = ftmp; |
2b835d68 | 7052 | } |
d5b7b3ae RE |
7053 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
7054 | break; | |
7055 | ||
7056 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 7057 | } |
949d79eb | 7058 | |
d5b7b3ae RE |
7059 | /* If we found a barrier, drop back to that; any fixes that we |
7060 | could have reached but come after the barrier will now go in | |
7061 | the next mini-pool. */ | |
949d79eb RE |
7062 | if (last_barrier != NULL) |
7063 | { | |
d5b7b3ae RE |
7064 | /* Reduce the refcount for those fixes that won't go into this |
7065 | pool after all. */ | |
7066 | for (fdel = last_barrier->next; | |
7067 | fdel && fdel != ftmp; | |
7068 | fdel = fdel->next) | |
7069 | { | |
7070 | fdel->minipool->refcount--; | |
7071 | fdel->minipool = NULL; | |
7072 | } | |
7073 | ||
949d79eb RE |
7074 | ftmp = last_barrier; |
7075 | } | |
7076 | else | |
2bfa88dc | 7077 | { |
d5b7b3ae RE |
7078 | /* ftmp is first fix that we can't fit into this pool and |
7079 | there no natural barriers that we could use. Insert a | |
7080 | new barrier in the code somewhere between the previous | |
7081 | fix and this one, and arrange to jump around it. */ | |
7082 | HOST_WIDE_INT max_address; | |
7083 | ||
7084 | /* The last item on the list of fixes must be a barrier, so | |
7085 | we can never run off the end of the list of fixes without | |
7086 | last_barrier being set. */ | |
7087 | if (ftmp == NULL) | |
7088 | abort (); | |
7089 | ||
7090 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
7091 | /* Check that there isn't another fix that is in range that |
7092 | we couldn't fit into this pool because the pool was | |
7093 | already too large: we need to put the pool before such an | |
7094 | instruction. */ | |
d5b7b3ae RE |
7095 | if (ftmp->address < max_address) |
7096 | max_address = ftmp->address; | |
7097 | ||
7098 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
7099 | } | |
7100 | ||
7101 | assign_minipool_offsets (last_barrier); | |
7102 | ||
7103 | while (ftmp) | |
7104 | { | |
7105 | if (GET_CODE (ftmp->insn) != BARRIER | |
7106 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
7107 | == NULL)) | |
7108 | break; | |
2bfa88dc | 7109 | |
d5b7b3ae | 7110 | ftmp = ftmp->next; |
2bfa88dc | 7111 | } |
949d79eb RE |
7112 | |
7113 | /* Scan over the fixes we have identified for this pool, fixing them | |
7114 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 7115 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
7116 | this_fix = this_fix->next) |
7117 | if (GET_CODE (this_fix->insn) != BARRIER) | |
7118 | { | |
949d79eb RE |
7119 | rtx addr |
7120 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, | |
7121 | minipool_vector_label), | |
d5b7b3ae | 7122 | this_fix->minipool->offset); |
949d79eb RE |
7123 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
7124 | } | |
7125 | ||
d5b7b3ae | 7126 | dump_minipool (last_barrier->insn); |
949d79eb | 7127 | fix = ftmp; |
2b835d68 | 7128 | } |
4b632bf1 | 7129 | |
949d79eb RE |
7130 | /* From now on we must synthesize any constants that we can't handle |
7131 | directly. This can happen if the RTL gets split during final | |
7132 | instruction generation. */ | |
4b632bf1 | 7133 | after_arm_reorg = 1; |
c7319d87 RE |
7134 | |
7135 | /* Free the minipool memory. */ | |
7136 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 7137 | } |
cce8749e CH |
7138 | \f |
7139 | /* Routines to output assembly language. */ | |
7140 | ||
f3bb6135 | 7141 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 7142 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 7143 | when cross compiling. */ |
1d6e90ac | 7144 | |
cd2b33d0 | 7145 | const char * |
ff9940b0 | 7146 | fp_immediate_constant (x) |
b5cc037f | 7147 | rtx x; |
ff9940b0 RE |
7148 | { |
7149 | REAL_VALUE_TYPE r; | |
7150 | int i; | |
7151 | ||
7152 | if (!fpa_consts_inited) | |
7153 | init_fpa_table (); | |
7154 | ||
7155 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
7156 | for (i = 0; i < 8; i++) | |
7157 | if (REAL_VALUES_EQUAL (r, values_fpa[i])) | |
7158 | return strings_fpa[i]; | |
f3bb6135 | 7159 | |
ff9940b0 RE |
7160 | abort (); |
7161 | } | |
7162 | ||
9997d19d | 7163 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
1d6e90ac | 7164 | |
cd2b33d0 | 7165 | static const char * |
9997d19d | 7166 | fp_const_from_val (r) |
62b10bbc | 7167 | REAL_VALUE_TYPE * r; |
9997d19d RE |
7168 | { |
7169 | int i; | |
7170 | ||
5895f793 | 7171 | if (!fpa_consts_inited) |
9997d19d RE |
7172 | init_fpa_table (); |
7173 | ||
7174 | for (i = 0; i < 8; i++) | |
7175 | if (REAL_VALUES_EQUAL (*r, values_fpa[i])) | |
7176 | return strings_fpa[i]; | |
7177 | ||
7178 | abort (); | |
7179 | } | |
ff9940b0 | 7180 | |
cce8749e CH |
7181 | /* Output the operands of a LDM/STM instruction to STREAM. |
7182 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 NC |
7183 | REG is the base register, either the frame pointer or the stack pointer, |
7184 | INSTR is the possibly suffixed load or store instruction. */ | |
cce8749e | 7185 | |
d5b7b3ae | 7186 | static void |
6d3d9133 | 7187 | print_multi_reg (stream, instr, reg, mask) |
62b10bbc | 7188 | FILE * stream; |
cd2b33d0 | 7189 | const char * instr; |
dd18ae56 NC |
7190 | int reg; |
7191 | int mask; | |
cce8749e CH |
7192 | { |
7193 | int i; | |
7194 | int not_first = FALSE; | |
7195 | ||
1d5473cb | 7196 | fputc ('\t', stream); |
dd18ae56 | 7197 | asm_fprintf (stream, instr, reg); |
1d5473cb | 7198 | fputs (", {", stream); |
62b10bbc | 7199 | |
d5b7b3ae | 7200 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
7201 | if (mask & (1 << i)) |
7202 | { | |
7203 | if (not_first) | |
7204 | fprintf (stream, ", "); | |
62b10bbc | 7205 | |
dd18ae56 | 7206 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
7207 | not_first = TRUE; |
7208 | } | |
f3bb6135 | 7209 | |
b17fe233 NC |
7210 | fprintf (stream, "}"); |
7211 | ||
7212 | /* Add a ^ character for the 26-bit ABI, but only if we were loading | |
1ce53769 NC |
7213 | the PC. Otherwise we would generate an UNPREDICTABLE instruction. |
7214 | Strictly speaking the instruction would be unpredicatble only if | |
7215 | we were writing back the base register as well, but since we never | |
7216 | want to generate an LDM type 2 instruction (register bank switching) | |
7217 | which is what you get if the PC is not being loaded, we do not need | |
7218 | to check for writeback. */ | |
b17fe233 | 7219 | if (! TARGET_APCS_32 |
1ce53769 | 7220 | && ((mask & (1 << PC_REGNUM)) != 0)) |
b17fe233 NC |
7221 | fprintf (stream, "^"); |
7222 | ||
7223 | fprintf (stream, "\n"); | |
f3bb6135 | 7224 | } |
cce8749e | 7225 | |
6354dc9b | 7226 | /* Output a 'call' insn. */ |
cce8749e | 7227 | |
cd2b33d0 | 7228 | const char * |
cce8749e | 7229 | output_call (operands) |
62b10bbc | 7230 | rtx * operands; |
cce8749e | 7231 | { |
6354dc9b | 7232 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
cce8749e | 7233 | |
62b10bbc | 7234 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 7235 | { |
62b10bbc | 7236 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 7237 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 7238 | } |
62b10bbc | 7239 | |
1d5473cb | 7240 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
da6558fd | 7241 | |
6cfc7210 | 7242 | if (TARGET_INTERWORK) |
da6558fd NC |
7243 | output_asm_insn ("bx%?\t%0", operands); |
7244 | else | |
7245 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
7246 | ||
f3bb6135 RE |
7247 | return ""; |
7248 | } | |
cce8749e | 7249 | |
ff9940b0 RE |
7250 | static int |
7251 | eliminate_lr2ip (x) | |
62b10bbc | 7252 | rtx * x; |
ff9940b0 RE |
7253 | { |
7254 | int something_changed = 0; | |
62b10bbc | 7255 | rtx x0 = * x; |
ff9940b0 | 7256 | int code = GET_CODE (x0); |
1d6e90ac NC |
7257 | int i, j; |
7258 | const char * fmt; | |
ff9940b0 RE |
7259 | |
7260 | switch (code) | |
7261 | { | |
7262 | case REG: | |
62b10bbc | 7263 | if (REGNO (x0) == LR_REGNUM) |
ff9940b0 | 7264 | { |
62b10bbc | 7265 | *x = gen_rtx_REG (SImode, IP_REGNUM); |
ff9940b0 RE |
7266 | return 1; |
7267 | } | |
7268 | return 0; | |
7269 | default: | |
6354dc9b | 7270 | /* Scan through the sub-elements and change any references there. */ |
ff9940b0 | 7271 | fmt = GET_RTX_FORMAT (code); |
62b10bbc | 7272 | |
ff9940b0 RE |
7273 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
7274 | if (fmt[i] == 'e') | |
7275 | something_changed |= eliminate_lr2ip (&XEXP (x0, i)); | |
7276 | else if (fmt[i] == 'E') | |
7277 | for (j = 0; j < XVECLEN (x0, i); j++) | |
7278 | something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j)); | |
62b10bbc | 7279 | |
ff9940b0 RE |
7280 | return something_changed; |
7281 | } | |
7282 | } | |
7283 | ||
6354dc9b | 7284 | /* Output a 'call' insn that is a reference in memory. */ |
ff9940b0 | 7285 | |
cd2b33d0 | 7286 | const char * |
ff9940b0 | 7287 | output_call_mem (operands) |
62b10bbc | 7288 | rtx * operands; |
ff9940b0 | 7289 | { |
6354dc9b NC |
7290 | operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */ |
7291 | /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */ | |
ff9940b0 | 7292 | if (eliminate_lr2ip (&operands[0])) |
1d5473cb | 7293 | output_asm_insn ("mov%?\t%|ip, %|lr", operands); |
f3bb6135 | 7294 | |
6cfc7210 | 7295 | if (TARGET_INTERWORK) |
da6558fd NC |
7296 | { |
7297 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
7298 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
7299 | output_asm_insn ("bx%?\t%|ip", operands); | |
7300 | } | |
7301 | else | |
7302 | { | |
7303 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
7304 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
7305 | } | |
7306 | ||
f3bb6135 RE |
7307 | return ""; |
7308 | } | |
ff9940b0 RE |
7309 | |
7310 | ||
3b684012 RE |
7311 | /* Output a move from arm registers to an fpa registers. |
7312 | OPERANDS[0] is an fpa register. | |
ff9940b0 RE |
7313 | OPERANDS[1] is the first registers of an arm register pair. */ |
7314 | ||
cd2b33d0 | 7315 | const char * |
3b684012 | 7316 | output_mov_long_double_fpa_from_arm (operands) |
62b10bbc | 7317 | rtx * operands; |
ff9940b0 RE |
7318 | { |
7319 | int arm_reg0 = REGNO (operands[1]); | |
7320 | rtx ops[3]; | |
7321 | ||
62b10bbc NC |
7322 | if (arm_reg0 == IP_REGNUM) |
7323 | abort (); | |
f3bb6135 | 7324 | |
43cffd11 RE |
7325 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
7326 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
7327 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 7328 | |
1d5473cb RE |
7329 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops); |
7330 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); | |
62b10bbc | 7331 | |
f3bb6135 RE |
7332 | return ""; |
7333 | } | |
ff9940b0 | 7334 | |
3b684012 | 7335 | /* Output a move from an fpa register to arm registers. |
ff9940b0 | 7336 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 7337 | OPERANDS[1] is an fpa register. */ |
ff9940b0 | 7338 | |
cd2b33d0 | 7339 | const char * |
3b684012 | 7340 | output_mov_long_double_arm_from_fpa (operands) |
62b10bbc | 7341 | rtx * operands; |
ff9940b0 RE |
7342 | { |
7343 | int arm_reg0 = REGNO (operands[0]); | |
7344 | rtx ops[3]; | |
7345 | ||
62b10bbc NC |
7346 | if (arm_reg0 == IP_REGNUM) |
7347 | abort (); | |
f3bb6135 | 7348 | |
43cffd11 RE |
7349 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
7350 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
7351 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 7352 | |
1d5473cb RE |
7353 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
7354 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops); | |
f3bb6135 RE |
7355 | return ""; |
7356 | } | |
ff9940b0 RE |
7357 | |
7358 | /* Output a move from arm registers to arm registers of a long double | |
7359 | OPERANDS[0] is the destination. | |
7360 | OPERANDS[1] is the source. */ | |
1d6e90ac | 7361 | |
cd2b33d0 | 7362 | const char * |
ff9940b0 | 7363 | output_mov_long_double_arm_from_arm (operands) |
62b10bbc | 7364 | rtx * operands; |
ff9940b0 | 7365 | { |
6354dc9b | 7366 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
7367 | int dest_start = REGNO (operands[0]); |
7368 | int src_start = REGNO (operands[1]); | |
7369 | rtx ops[2]; | |
7370 | int i; | |
7371 | ||
7372 | if (dest_start < src_start) | |
7373 | { | |
7374 | for (i = 0; i < 3; i++) | |
7375 | { | |
43cffd11 RE |
7376 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
7377 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 7378 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
7379 | } |
7380 | } | |
7381 | else | |
7382 | { | |
7383 | for (i = 2; i >= 0; i--) | |
7384 | { | |
43cffd11 RE |
7385 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
7386 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 7387 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
7388 | } |
7389 | } | |
f3bb6135 | 7390 | |
ff9940b0 RE |
7391 | return ""; |
7392 | } | |
7393 | ||
7394 | ||
3b684012 RE |
7395 | /* Output a move from arm registers to an fpa registers. |
7396 | OPERANDS[0] is an fpa register. | |
cce8749e CH |
7397 | OPERANDS[1] is the first registers of an arm register pair. */ |
7398 | ||
cd2b33d0 | 7399 | const char * |
3b684012 | 7400 | output_mov_double_fpa_from_arm (operands) |
62b10bbc | 7401 | rtx * operands; |
cce8749e CH |
7402 | { |
7403 | int arm_reg0 = REGNO (operands[1]); | |
7404 | rtx ops[2]; | |
7405 | ||
62b10bbc NC |
7406 | if (arm_reg0 == IP_REGNUM) |
7407 | abort (); | |
7408 | ||
43cffd11 RE |
7409 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
7410 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
7411 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops); |
7412 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); | |
f3bb6135 RE |
7413 | return ""; |
7414 | } | |
cce8749e | 7415 | |
3b684012 | 7416 | /* Output a move from an fpa register to arm registers. |
cce8749e | 7417 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 7418 | OPERANDS[1] is an fpa register. */ |
cce8749e | 7419 | |
cd2b33d0 | 7420 | const char * |
3b684012 | 7421 | output_mov_double_arm_from_fpa (operands) |
62b10bbc | 7422 | rtx * operands; |
cce8749e CH |
7423 | { |
7424 | int arm_reg0 = REGNO (operands[0]); | |
7425 | rtx ops[2]; | |
7426 | ||
62b10bbc NC |
7427 | if (arm_reg0 == IP_REGNUM) |
7428 | abort (); | |
f3bb6135 | 7429 | |
43cffd11 RE |
7430 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
7431 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
7432 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
7433 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops); | |
f3bb6135 RE |
7434 | return ""; |
7435 | } | |
cce8749e CH |
7436 | |
7437 | /* Output a move between double words. | |
7438 | It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM | |
7439 | or MEM<-REG and all MEMs must be offsettable addresses. */ | |
7440 | ||
cd2b33d0 | 7441 | const char * |
cce8749e | 7442 | output_move_double (operands) |
aec3cfba | 7443 | rtx * operands; |
cce8749e CH |
7444 | { |
7445 | enum rtx_code code0 = GET_CODE (operands[0]); | |
7446 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 7447 | rtx otherops[3]; |
cce8749e CH |
7448 | |
7449 | if (code0 == REG) | |
7450 | { | |
7451 | int reg0 = REGNO (operands[0]); | |
7452 | ||
43cffd11 | 7453 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
aec3cfba | 7454 | |
cce8749e CH |
7455 | if (code1 == REG) |
7456 | { | |
7457 | int reg1 = REGNO (operands[1]); | |
62b10bbc NC |
7458 | if (reg1 == IP_REGNUM) |
7459 | abort (); | |
f3bb6135 | 7460 | |
6354dc9b | 7461 | /* Ensure the second source is not overwritten. */ |
c1c2bc04 | 7462 | if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1)) |
6cfc7210 | 7463 | output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands); |
cce8749e | 7464 | else |
6cfc7210 | 7465 | output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands); |
cce8749e CH |
7466 | } |
7467 | else if (code1 == CONST_DOUBLE) | |
7468 | { | |
226a5051 RE |
7469 | if (GET_MODE (operands[1]) == DFmode) |
7470 | { | |
b216cd4a | 7471 | REAL_VALUE_TYPE r; |
226a5051 | 7472 | long l[2]; |
226a5051 | 7473 | |
b216cd4a ZW |
7474 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); |
7475 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); | |
d5b7b3ae RE |
7476 | otherops[1] = GEN_INT (l[1]); |
7477 | operands[1] = GEN_INT (l[0]); | |
226a5051 | 7478 | } |
c1c2bc04 RE |
7479 | else if (GET_MODE (operands[1]) != VOIDmode) |
7480 | abort (); | |
7481 | else if (WORDS_BIG_ENDIAN) | |
7482 | { | |
c1c2bc04 RE |
7483 | otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); |
7484 | operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
7485 | } | |
226a5051 RE |
7486 | else |
7487 | { | |
7488 | otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
7489 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
7490 | } | |
6cfc7210 | 7491 | |
c1c2bc04 RE |
7492 | output_mov_immediate (operands); |
7493 | output_mov_immediate (otherops); | |
cce8749e CH |
7494 | } |
7495 | else if (code1 == CONST_INT) | |
7496 | { | |
56636818 JL |
7497 | #if HOST_BITS_PER_WIDE_INT > 32 |
7498 | /* If HOST_WIDE_INT is more than 32 bits, the intval tells us | |
7499 | what the upper word is. */ | |
7500 | if (WORDS_BIG_ENDIAN) | |
7501 | { | |
7502 | otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); | |
7503 | operands[1] = GEN_INT (INTVAL (operands[1]) >> 32); | |
7504 | } | |
7505 | else | |
7506 | { | |
7507 | otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32); | |
7508 | operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); | |
7509 | } | |
7510 | #else | |
6354dc9b | 7511 | /* Sign extend the intval into the high-order word. */ |
c1c2bc04 RE |
7512 | if (WORDS_BIG_ENDIAN) |
7513 | { | |
7514 | otherops[1] = operands[1]; | |
7515 | operands[1] = (INTVAL (operands[1]) < 0 | |
7516 | ? constm1_rtx : const0_rtx); | |
7517 | } | |
ff9940b0 | 7518 | else |
c1c2bc04 | 7519 | otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; |
56636818 | 7520 | #endif |
c1c2bc04 RE |
7521 | output_mov_immediate (otherops); |
7522 | output_mov_immediate (operands); | |
cce8749e CH |
7523 | } |
7524 | else if (code1 == MEM) | |
7525 | { | |
ff9940b0 | 7526 | switch (GET_CODE (XEXP (operands[1], 0))) |
cce8749e | 7527 | { |
ff9940b0 | 7528 | case REG: |
9997d19d | 7529 | output_asm_insn ("ldm%?ia\t%m1, %M0", operands); |
ff9940b0 | 7530 | break; |
2b835d68 | 7531 | |
ff9940b0 | 7532 | case PRE_INC: |
6354dc9b | 7533 | abort (); /* Should never happen now. */ |
ff9940b0 | 7534 | break; |
2b835d68 | 7535 | |
ff9940b0 | 7536 | case PRE_DEC: |
2b835d68 | 7537 | output_asm_insn ("ldm%?db\t%m1!, %M0", operands); |
ff9940b0 | 7538 | break; |
2b835d68 | 7539 | |
ff9940b0 | 7540 | case POST_INC: |
9997d19d | 7541 | output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); |
ff9940b0 | 7542 | break; |
2b835d68 | 7543 | |
ff9940b0 | 7544 | case POST_DEC: |
6354dc9b | 7545 | abort (); /* Should never happen now. */ |
ff9940b0 | 7546 | break; |
2b835d68 RE |
7547 | |
7548 | case LABEL_REF: | |
7549 | case CONST: | |
7550 | output_asm_insn ("adr%?\t%0, %1", operands); | |
7551 | output_asm_insn ("ldm%?ia\t%0, %M0", operands); | |
7552 | break; | |
7553 | ||
ff9940b0 | 7554 | default: |
aec3cfba NC |
7555 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), |
7556 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
cce8749e | 7557 | { |
2b835d68 RE |
7558 | otherops[0] = operands[0]; |
7559 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
7560 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
1d6e90ac | 7561 | |
2b835d68 RE |
7562 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) |
7563 | { | |
7564 | if (GET_CODE (otherops[2]) == CONST_INT) | |
7565 | { | |
06bea5aa | 7566 | switch ((int) INTVAL (otherops[2])) |
2b835d68 RE |
7567 | { |
7568 | case -8: | |
7569 | output_asm_insn ("ldm%?db\t%1, %M0", otherops); | |
7570 | return ""; | |
7571 | case -4: | |
7572 | output_asm_insn ("ldm%?da\t%1, %M0", otherops); | |
7573 | return ""; | |
7574 | case 4: | |
7575 | output_asm_insn ("ldm%?ib\t%1, %M0", otherops); | |
7576 | return ""; | |
7577 | } | |
1d6e90ac | 7578 | |
2b835d68 RE |
7579 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) |
7580 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
7581 | else | |
7582 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
7583 | } | |
7584 | else | |
7585 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
7586 | } | |
7587 | else | |
7588 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
6cfc7210 | 7589 | |
2b835d68 RE |
7590 | return "ldm%?ia\t%0, %M0"; |
7591 | } | |
7592 | else | |
7593 | { | |
b72f00af | 7594 | otherops[1] = adjust_address (operands[1], VOIDmode, 4); |
2b835d68 RE |
7595 | /* Take care of overlapping base/data reg. */ |
7596 | if (reg_mentioned_p (operands[0], operands[1])) | |
7597 | { | |
7598 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
7599 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
7600 | } | |
7601 | else | |
7602 | { | |
7603 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
7604 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
7605 | } | |
cce8749e CH |
7606 | } |
7607 | } | |
7608 | } | |
2b835d68 | 7609 | else |
6354dc9b | 7610 | abort (); /* Constraints should prevent this. */ |
cce8749e CH |
7611 | } |
7612 | else if (code0 == MEM && code1 == REG) | |
7613 | { | |
62b10bbc NC |
7614 | if (REGNO (operands[1]) == IP_REGNUM) |
7615 | abort (); | |
2b835d68 | 7616 | |
ff9940b0 RE |
7617 | switch (GET_CODE (XEXP (operands[0], 0))) |
7618 | { | |
7619 | case REG: | |
9997d19d | 7620 | output_asm_insn ("stm%?ia\t%m0, %M1", operands); |
ff9940b0 | 7621 | break; |
2b835d68 | 7622 | |
ff9940b0 | 7623 | case PRE_INC: |
6354dc9b | 7624 | abort (); /* Should never happen now. */ |
ff9940b0 | 7625 | break; |
2b835d68 | 7626 | |
ff9940b0 | 7627 | case PRE_DEC: |
2b835d68 | 7628 | output_asm_insn ("stm%?db\t%m0!, %M1", operands); |
ff9940b0 | 7629 | break; |
2b835d68 | 7630 | |
ff9940b0 | 7631 | case POST_INC: |
9997d19d | 7632 | output_asm_insn ("stm%?ia\t%m0!, %M1", operands); |
ff9940b0 | 7633 | break; |
2b835d68 | 7634 | |
ff9940b0 | 7635 | case POST_DEC: |
6354dc9b | 7636 | abort (); /* Should never happen now. */ |
ff9940b0 | 7637 | break; |
2b835d68 RE |
7638 | |
7639 | case PLUS: | |
7640 | if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
7641 | { | |
06bea5aa | 7642 | switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) |
2b835d68 RE |
7643 | { |
7644 | case -8: | |
7645 | output_asm_insn ("stm%?db\t%m0, %M1", operands); | |
7646 | return ""; | |
7647 | ||
7648 | case -4: | |
7649 | output_asm_insn ("stm%?da\t%m0, %M1", operands); | |
7650 | return ""; | |
7651 | ||
7652 | case 4: | |
7653 | output_asm_insn ("stm%?ib\t%m0, %M1", operands); | |
7654 | return ""; | |
7655 | } | |
7656 | } | |
7657 | /* Fall through */ | |
7658 | ||
ff9940b0 | 7659 | default: |
b72f00af | 7660 | otherops[0] = adjust_address (operands[0], VOIDmode, 4); |
43cffd11 | 7661 | otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); |
9997d19d RE |
7662 | output_asm_insn ("str%?\t%1, %0", operands); |
7663 | output_asm_insn ("str%?\t%1, %0", otherops); | |
cce8749e CH |
7664 | } |
7665 | } | |
2b835d68 | 7666 | else |
1d6e90ac NC |
7667 | /* Constraints should prevent this. */ |
7668 | abort (); | |
cce8749e | 7669 | |
9997d19d RE |
7670 | return ""; |
7671 | } | |
cce8749e CH |
7672 | |
7673 | ||
7674 | /* Output an arbitrary MOV reg, #n. | |
7675 | OPERANDS[0] is a register. OPERANDS[1] is a const_int. */ | |
7676 | ||
cd2b33d0 | 7677 | const char * |
cce8749e | 7678 | output_mov_immediate (operands) |
62b10bbc | 7679 | rtx * operands; |
cce8749e | 7680 | { |
f3bb6135 | 7681 | HOST_WIDE_INT n = INTVAL (operands[1]); |
cce8749e | 7682 | |
1d6e90ac | 7683 | /* Try to use one MOV. */ |
cce8749e | 7684 | if (const_ok_for_arm (n)) |
1d6e90ac | 7685 | output_asm_insn ("mov%?\t%0, %1", operands); |
cce8749e | 7686 | |
1d6e90ac NC |
7687 | /* Try to use one MVN. */ |
7688 | else if (const_ok_for_arm (~n)) | |
cce8749e | 7689 | { |
f3bb6135 | 7690 | operands[1] = GEN_INT (~n); |
9997d19d | 7691 | output_asm_insn ("mvn%?\t%0, %1", operands); |
cce8749e | 7692 | } |
1d6e90ac NC |
7693 | else |
7694 | { | |
7695 | int n_ones = 0; | |
7696 | int i; | |
cce8749e | 7697 | |
1d6e90ac NC |
7698 | /* If all else fails, make it out of ORRs or BICs as appropriate. */ |
7699 | for (i = 0; i < 32; i ++) | |
7700 | if (n & 1 << i) | |
7701 | n_ones ++; | |
cce8749e | 7702 | |
1d6e90ac NC |
7703 | if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */ |
7704 | output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n); | |
7705 | else | |
7706 | output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n); | |
7707 | } | |
f3bb6135 RE |
7708 | |
7709 | return ""; | |
7710 | } | |
cce8749e | 7711 | |
1d6e90ac NC |
7712 | /* Output an ADD r, s, #n where n may be too big for one instruction. |
7713 | If adding zero to one register, output nothing. */ | |
cce8749e | 7714 | |
cd2b33d0 | 7715 | const char * |
cce8749e | 7716 | output_add_immediate (operands) |
62b10bbc | 7717 | rtx * operands; |
cce8749e | 7718 | { |
f3bb6135 | 7719 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
7720 | |
7721 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
7722 | { | |
7723 | if (n < 0) | |
7724 | output_multi_immediate (operands, | |
9997d19d RE |
7725 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
7726 | -n); | |
cce8749e CH |
7727 | else |
7728 | output_multi_immediate (operands, | |
9997d19d RE |
7729 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
7730 | n); | |
cce8749e | 7731 | } |
f3bb6135 RE |
7732 | |
7733 | return ""; | |
7734 | } | |
cce8749e | 7735 | |
cce8749e CH |
7736 | /* Output a multiple immediate operation. |
7737 | OPERANDS is the vector of operands referred to in the output patterns. | |
7738 | INSTR1 is the output pattern to use for the first constant. | |
7739 | INSTR2 is the output pattern to use for subsequent constants. | |
7740 | IMMED_OP is the index of the constant slot in OPERANDS. | |
7741 | N is the constant value. */ | |
7742 | ||
cd2b33d0 | 7743 | static const char * |
cce8749e | 7744 | output_multi_immediate (operands, instr1, instr2, immed_op, n) |
62b10bbc | 7745 | rtx * operands; |
cd2b33d0 NC |
7746 | const char * instr1; |
7747 | const char * instr2; | |
f3bb6135 RE |
7748 | int immed_op; |
7749 | HOST_WIDE_INT n; | |
cce8749e | 7750 | { |
f3bb6135 | 7751 | #if HOST_BITS_PER_WIDE_INT > 32 |
30cf4896 | 7752 | n &= 0xffffffff; |
f3bb6135 RE |
7753 | #endif |
7754 | ||
cce8749e CH |
7755 | if (n == 0) |
7756 | { | |
1d6e90ac | 7757 | /* Quick and easy output. */ |
cce8749e | 7758 | operands[immed_op] = const0_rtx; |
1d6e90ac | 7759 | output_asm_insn (instr1, operands); |
cce8749e CH |
7760 | } |
7761 | else | |
7762 | { | |
7763 | int i; | |
cd2b33d0 | 7764 | const char * instr = instr1; |
cce8749e | 7765 | |
6354dc9b | 7766 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
7767 | for (i = 0; i < 32; i += 2) |
7768 | { | |
7769 | if (n & (3 << i)) | |
7770 | { | |
f3bb6135 RE |
7771 | operands[immed_op] = GEN_INT (n & (255 << i)); |
7772 | output_asm_insn (instr, operands); | |
cce8749e CH |
7773 | instr = instr2; |
7774 | i += 6; | |
7775 | } | |
7776 | } | |
7777 | } | |
cd2b33d0 | 7778 | |
f3bb6135 | 7779 | return ""; |
9997d19d | 7780 | } |
cce8749e | 7781 | |
cce8749e CH |
7782 | /* Return the appropriate ARM instruction for the operation code. |
7783 | The returned result should not be overwritten. OP is the rtx of the | |
7784 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
7785 | was shifted. */ | |
7786 | ||
cd2b33d0 | 7787 | const char * |
cce8749e CH |
7788 | arithmetic_instr (op, shift_first_arg) |
7789 | rtx op; | |
f3bb6135 | 7790 | int shift_first_arg; |
cce8749e | 7791 | { |
9997d19d | 7792 | switch (GET_CODE (op)) |
cce8749e CH |
7793 | { |
7794 | case PLUS: | |
f3bb6135 RE |
7795 | return "add"; |
7796 | ||
cce8749e | 7797 | case MINUS: |
f3bb6135 RE |
7798 | return shift_first_arg ? "rsb" : "sub"; |
7799 | ||
cce8749e | 7800 | case IOR: |
f3bb6135 RE |
7801 | return "orr"; |
7802 | ||
cce8749e | 7803 | case XOR: |
f3bb6135 RE |
7804 | return "eor"; |
7805 | ||
cce8749e | 7806 | case AND: |
f3bb6135 RE |
7807 | return "and"; |
7808 | ||
cce8749e | 7809 | default: |
f3bb6135 | 7810 | abort (); |
cce8749e | 7811 | } |
f3bb6135 | 7812 | } |
cce8749e | 7813 | |
cce8749e CH |
7814 | /* Ensure valid constant shifts and return the appropriate shift mnemonic |
7815 | for the operation code. The returned result should not be overwritten. | |
7816 | OP is the rtx code of the shift. | |
9997d19d | 7817 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 7818 | shift. */ |
cce8749e | 7819 | |
cd2b33d0 | 7820 | static const char * |
9997d19d RE |
7821 | shift_op (op, amountp) |
7822 | rtx op; | |
7823 | HOST_WIDE_INT *amountp; | |
cce8749e | 7824 | { |
cd2b33d0 | 7825 | const char * mnem; |
e2c671ba | 7826 | enum rtx_code code = GET_CODE (op); |
cce8749e | 7827 | |
9997d19d RE |
7828 | if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG) |
7829 | *amountp = -1; | |
7830 | else if (GET_CODE (XEXP (op, 1)) == CONST_INT) | |
7831 | *amountp = INTVAL (XEXP (op, 1)); | |
7832 | else | |
7833 | abort (); | |
7834 | ||
e2c671ba | 7835 | switch (code) |
cce8749e CH |
7836 | { |
7837 | case ASHIFT: | |
7838 | mnem = "asl"; | |
7839 | break; | |
f3bb6135 | 7840 | |
cce8749e CH |
7841 | case ASHIFTRT: |
7842 | mnem = "asr"; | |
cce8749e | 7843 | break; |
f3bb6135 | 7844 | |
cce8749e CH |
7845 | case LSHIFTRT: |
7846 | mnem = "lsr"; | |
cce8749e | 7847 | break; |
f3bb6135 | 7848 | |
9997d19d RE |
7849 | case ROTATERT: |
7850 | mnem = "ror"; | |
9997d19d RE |
7851 | break; |
7852 | ||
ff9940b0 | 7853 | case MULT: |
e2c671ba RE |
7854 | /* We never have to worry about the amount being other than a |
7855 | power of 2, since this case can never be reloaded from a reg. */ | |
9997d19d RE |
7856 | if (*amountp != -1) |
7857 | *amountp = int_log2 (*amountp); | |
7858 | else | |
7859 | abort (); | |
f3bb6135 RE |
7860 | return "asl"; |
7861 | ||
cce8749e | 7862 | default: |
f3bb6135 | 7863 | abort (); |
cce8749e CH |
7864 | } |
7865 | ||
e2c671ba RE |
7866 | if (*amountp != -1) |
7867 | { | |
7868 | /* This is not 100% correct, but follows from the desire to merge | |
7869 | multiplication by a power of 2 with the recognizer for a | |
7870 | shift. >=32 is not a valid shift for "asl", so we must try and | |
7871 | output a shift that produces the correct arithmetical result. | |
ddd5a7c1 | 7872 | Using lsr #32 is identical except for the fact that the carry bit |
e2c671ba RE |
7873 | is not set correctly if we set the flags; but we never use the |
7874 | carry bit from such an operation, so we can ignore that. */ | |
7875 | if (code == ROTATERT) | |
1d6e90ac NC |
7876 | /* Rotate is just modulo 32. */ |
7877 | *amountp &= 31; | |
e2c671ba RE |
7878 | else if (*amountp != (*amountp & 31)) |
7879 | { | |
7880 | if (code == ASHIFT) | |
7881 | mnem = "lsr"; | |
7882 | *amountp = 32; | |
7883 | } | |
7884 | ||
7885 | /* Shifts of 0 are no-ops. */ | |
7886 | if (*amountp == 0) | |
7887 | return NULL; | |
7888 | } | |
7889 | ||
9997d19d RE |
7890 | return mnem; |
7891 | } | |
cce8749e | 7892 | |
6354dc9b | 7893 | /* Obtain the shift from the POWER of two. */ |
1d6e90ac | 7894 | |
18af7313 | 7895 | static HOST_WIDE_INT |
cce8749e | 7896 | int_log2 (power) |
f3bb6135 | 7897 | HOST_WIDE_INT power; |
cce8749e | 7898 | { |
f3bb6135 | 7899 | HOST_WIDE_INT shift = 0; |
cce8749e | 7900 | |
30cf4896 | 7901 | while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) |
cce8749e CH |
7902 | { |
7903 | if (shift > 31) | |
f3bb6135 | 7904 | abort (); |
1d6e90ac | 7905 | shift ++; |
cce8749e | 7906 | } |
f3bb6135 RE |
7907 | |
7908 | return shift; | |
7909 | } | |
cce8749e | 7910 | |
cce8749e CH |
7911 | /* Output a .ascii pseudo-op, keeping track of lengths. This is because |
7912 | /bin/as is horribly restrictive. */ | |
6cfc7210 | 7913 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
7914 | |
7915 | void | |
7916 | output_ascii_pseudo_op (stream, p, len) | |
62b10bbc | 7917 | FILE * stream; |
3cce094d | 7918 | const unsigned char * p; |
cce8749e CH |
7919 | int len; |
7920 | { | |
7921 | int i; | |
6cfc7210 | 7922 | int len_so_far = 0; |
cce8749e | 7923 | |
6cfc7210 NC |
7924 | fputs ("\t.ascii\t\"", stream); |
7925 | ||
cce8749e CH |
7926 | for (i = 0; i < len; i++) |
7927 | { | |
1d6e90ac | 7928 | int c = p[i]; |
cce8749e | 7929 | |
6cfc7210 | 7930 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 7931 | { |
6cfc7210 | 7932 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 7933 | len_so_far = 0; |
cce8749e CH |
7934 | } |
7935 | ||
6cfc7210 | 7936 | switch (c) |
cce8749e | 7937 | { |
6cfc7210 NC |
7938 | case TARGET_TAB: |
7939 | fputs ("\\t", stream); | |
7940 | len_so_far += 2; | |
7941 | break; | |
7942 | ||
7943 | case TARGET_FF: | |
7944 | fputs ("\\f", stream); | |
7945 | len_so_far += 2; | |
7946 | break; | |
7947 | ||
7948 | case TARGET_BS: | |
7949 | fputs ("\\b", stream); | |
7950 | len_so_far += 2; | |
7951 | break; | |
7952 | ||
7953 | case TARGET_CR: | |
7954 | fputs ("\\r", stream); | |
7955 | len_so_far += 2; | |
7956 | break; | |
7957 | ||
7958 | case TARGET_NEWLINE: | |
7959 | fputs ("\\n", stream); | |
7960 | c = p [i + 1]; | |
7961 | if ((c >= ' ' && c <= '~') | |
7962 | || c == TARGET_TAB) | |
7963 | /* This is a good place for a line break. */ | |
7964 | len_so_far = MAX_ASCII_LEN; | |
7965 | else | |
7966 | len_so_far += 2; | |
7967 | break; | |
7968 | ||
7969 | case '\"': | |
7970 | case '\\': | |
7971 | putc ('\\', stream); | |
5895f793 | 7972 | len_so_far++; |
6cfc7210 | 7973 | /* drop through. */ |
f3bb6135 | 7974 | |
6cfc7210 NC |
7975 | default: |
7976 | if (c >= ' ' && c <= '~') | |
7977 | { | |
7978 | putc (c, stream); | |
5895f793 | 7979 | len_so_far++; |
6cfc7210 NC |
7980 | } |
7981 | else | |
7982 | { | |
7983 | fprintf (stream, "\\%03o", c); | |
7984 | len_so_far += 4; | |
7985 | } | |
7986 | break; | |
cce8749e | 7987 | } |
cce8749e | 7988 | } |
f3bb6135 | 7989 | |
cce8749e | 7990 | fputs ("\"\n", stream); |
f3bb6135 | 7991 | } |
cce8749e | 7992 | \f |
121308d4 NC |
7993 | /* Compute the register sabe mask for registers 0 through 12 |
7994 | inclusive. This code is used by both arm_compute_save_reg_mask | |
7995 | and arm_compute_initial_elimination_offset. */ | |
6d3d9133 NC |
7996 | |
7997 | static unsigned long | |
121308d4 | 7998 | arm_compute_save_reg0_reg12_mask () |
6d3d9133 | 7999 | { |
121308d4 | 8000 | unsigned long func_type = arm_current_func_type (); |
6d3d9133 NC |
8001 | unsigned int save_reg_mask = 0; |
8002 | unsigned int reg; | |
6d3d9133 | 8003 | |
7b8b8ade | 8004 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 8005 | { |
7b8b8ade | 8006 | unsigned int max_reg; |
7b8b8ade NC |
8007 | /* Interrupt functions must not corrupt any registers, |
8008 | even call clobbered ones. If this is a leaf function | |
8009 | we can just examine the registers used by the RTL, but | |
8010 | otherwise we have to assume that whatever function is | |
8011 | called might clobber anything, and so we have to save | |
8012 | all the call-clobbered registers as well. */ | |
8013 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
8014 | /* FIQ handlers have registers r8 - r12 banked, so | |
8015 | we only need to check r0 - r7, Normal ISRs only | |
121308d4 | 8016 | bank r14 and r15, so we must check up to r12. |
7b8b8ade NC |
8017 | r13 is the stack pointer which is always preserved, |
8018 | so we do not need to consider it here. */ | |
8019 | max_reg = 7; | |
8020 | else | |
8021 | max_reg = 12; | |
8022 | ||
8023 | for (reg = 0; reg <= max_reg; reg++) | |
8024 | if (regs_ever_live[reg] | |
8025 | || (! current_function_is_leaf && call_used_regs [reg])) | |
6d3d9133 NC |
8026 | save_reg_mask |= (1 << reg); |
8027 | } | |
8028 | else | |
8029 | { | |
8030 | /* In the normal case we only need to save those registers | |
8031 | which are call saved and which are used by this function. */ | |
8032 | for (reg = 0; reg <= 10; reg++) | |
8033 | if (regs_ever_live[reg] && ! call_used_regs [reg]) | |
8034 | save_reg_mask |= (1 << reg); | |
8035 | ||
8036 | /* Handle the frame pointer as a special case. */ | |
8037 | if (! TARGET_APCS_FRAME | |
8038 | && ! frame_pointer_needed | |
8039 | && regs_ever_live[HARD_FRAME_POINTER_REGNUM] | |
8040 | && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) | |
8041 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; | |
8042 | ||
8043 | /* If we aren't loading the PIC register, | |
8044 | don't stack it even though it may be live. */ | |
8045 | if (flag_pic | |
8046 | && ! TARGET_SINGLE_PIC_BASE | |
8047 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) | |
8048 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; | |
8049 | } | |
8050 | ||
121308d4 NC |
8051 | return save_reg_mask; |
8052 | } | |
8053 | ||
8054 | /* Compute a bit mask of which registers need to be | |
8055 | saved on the stack for the current function. */ | |
8056 | ||
8057 | static unsigned long | |
8058 | arm_compute_save_reg_mask () | |
8059 | { | |
8060 | unsigned int save_reg_mask = 0; | |
8061 | unsigned long func_type = arm_current_func_type (); | |
8062 | ||
8063 | if (IS_NAKED (func_type)) | |
8064 | /* This should never really happen. */ | |
8065 | return 0; | |
8066 | ||
8067 | /* If we are creating a stack frame, then we must save the frame pointer, | |
8068 | IP (which will hold the old stack pointer), LR and the PC. */ | |
8069 | if (frame_pointer_needed) | |
8070 | save_reg_mask |= | |
8071 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
8072 | | (1 << IP_REGNUM) | |
8073 | | (1 << LR_REGNUM) | |
8074 | | (1 << PC_REGNUM); | |
8075 | ||
8076 | /* Volatile functions do not return, so there | |
8077 | is no need to save any other registers. */ | |
8078 | if (IS_VOLATILE (func_type)) | |
8079 | return save_reg_mask; | |
8080 | ||
8081 | save_reg_mask |= arm_compute_save_reg0_reg12_mask (); | |
8082 | ||
6d3d9133 NC |
8083 | /* Decide if we need to save the link register. |
8084 | Interrupt routines have their own banked link register, | |
8085 | so they never need to save it. | |
1768c26f | 8086 | Otherwise if we do not use the link register we do not need to save |
6d3d9133 NC |
8087 | it. If we are pushing other registers onto the stack however, we |
8088 | can save an instruction in the epilogue by pushing the link register | |
8089 | now and then popping it back into the PC. This incurs extra memory | |
8090 | accesses though, so we only do it when optimising for size, and only | |
8091 | if we know that we will not need a fancy return sequence. */ | |
3a7731fd | 8092 | if (regs_ever_live [LR_REGNUM] |
6d3d9133 NC |
8093 | || (save_reg_mask |
8094 | && optimize_size | |
3a7731fd | 8095 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)) |
6d3d9133 NC |
8096 | save_reg_mask |= 1 << LR_REGNUM; |
8097 | ||
6f7ebcbb NC |
8098 | if (cfun->machine->lr_save_eliminated) |
8099 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
8100 | ||
6d3d9133 NC |
8101 | return save_reg_mask; |
8102 | } | |
8103 | ||
8104 | /* Generate a function exit sequence. If REALLY_RETURN is true, then do | |
8105 | everything bar the final return instruction. */ | |
ff9940b0 | 8106 | |
cd2b33d0 | 8107 | const char * |
84ed5e79 | 8108 | output_return_instruction (operand, really_return, reverse) |
f3bb6135 RE |
8109 | rtx operand; |
8110 | int really_return; | |
84ed5e79 | 8111 | int reverse; |
ff9940b0 | 8112 | { |
6d3d9133 | 8113 | char conditional[10]; |
ff9940b0 | 8114 | char instr[100]; |
6d3d9133 NC |
8115 | int reg; |
8116 | unsigned long live_regs_mask; | |
8117 | unsigned long func_type; | |
e26053d1 | 8118 | |
6d3d9133 | 8119 | func_type = arm_current_func_type (); |
e2c671ba | 8120 | |
6d3d9133 | 8121 | if (IS_NAKED (func_type)) |
d5b7b3ae | 8122 | return ""; |
6d3d9133 NC |
8123 | |
8124 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 8125 | { |
e2c671ba | 8126 | /* If this function was declared non-returning, and we have found a tail |
3a5a4282 PB |
8127 | call, then we have to trust that the called function won't return. */ |
8128 | if (really_return) | |
8129 | { | |
8130 | rtx ops[2]; | |
8131 | ||
8132 | /* Otherwise, trap an attempted return by aborting. */ | |
8133 | ops[0] = operand; | |
8134 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" | |
8135 | : "abort"); | |
8136 | assemble_external_libcall (ops[1]); | |
8137 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
8138 | } | |
8139 | ||
e2c671ba RE |
8140 | return ""; |
8141 | } | |
6d3d9133 | 8142 | |
5895f793 | 8143 | if (current_function_calls_alloca && !really_return) |
62b10bbc | 8144 | abort (); |
ff9940b0 | 8145 | |
c414f8a9 | 8146 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); |
d5b7b3ae | 8147 | |
6d3d9133 | 8148 | return_used_this_function = 1; |
ff9940b0 | 8149 | |
6d3d9133 | 8150 | live_regs_mask = arm_compute_save_reg_mask (); |
ff9940b0 | 8151 | |
1768c26f | 8152 | if (live_regs_mask) |
6d3d9133 | 8153 | { |
1768c26f PB |
8154 | const char * return_reg; |
8155 | ||
8156 | /* If we do not have any special requirements for function exit | |
8157 | (eg interworking, or ISR) then we can load the return address | |
8158 | directly into the PC. Otherwise we must load it into LR. */ | |
8159 | if (really_return | |
1768c26f PB |
8160 | && ! TARGET_INTERWORK) |
8161 | return_reg = reg_names[PC_REGNUM]; | |
6d3d9133 | 8162 | else |
1768c26f PB |
8163 | return_reg = reg_names[LR_REGNUM]; |
8164 | ||
6d3d9133 NC |
8165 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) |
8166 | /* There are two possible reasons for the IP register being saved. | |
8167 | Either a stack frame was created, in which case IP contains the | |
8168 | old stack pointer, or an ISR routine corrupted it. If this in an | |
8169 | ISR routine then just restore IP, otherwise restore IP into SP. */ | |
8170 | if (! IS_INTERRUPT (func_type)) | |
8171 | { | |
8172 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
8173 | live_regs_mask |= (1 << SP_REGNUM); | |
8174 | } | |
f3bb6135 | 8175 | |
3a7731fd PB |
8176 | /* On some ARM architectures it is faster to use LDR rather than |
8177 | LDM to load a single register. On other architectures, the | |
8178 | cost is the same. In 26 bit mode, or for exception handlers, | |
8179 | we have to use LDM to load the PC so that the CPSR is also | |
8180 | restored. */ | |
8181 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) | |
6d3d9133 | 8182 | { |
3a7731fd PB |
8183 | if (live_regs_mask == (unsigned int)(1 << reg)) |
8184 | break; | |
8185 | } | |
8186 | if (reg <= LAST_ARM_REGNUM | |
8187 | && (reg != LR_REGNUM | |
8188 | || ! really_return | |
8189 | || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type)))) | |
8190 | { | |
8191 | sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, | |
8192 | (reg == LR_REGNUM) ? return_reg : reg_names[reg]); | |
6d3d9133 | 8193 | } |
ff9940b0 | 8194 | else |
1d5473cb | 8195 | { |
1768c26f PB |
8196 | char *p; |
8197 | int first = 1; | |
6d3d9133 | 8198 | |
1768c26f PB |
8199 | /* Generate the load multiple instruction to restore the registers. */ |
8200 | if (frame_pointer_needed) | |
8201 | sprintf (instr, "ldm%sea\t%%|fp, {", conditional); | |
f1acdf8b NC |
8202 | else if (live_regs_mask & (1 << SP_REGNUM)) |
8203 | sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); | |
da6558fd | 8204 | else |
1768c26f PB |
8205 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); |
8206 | ||
8207 | p = instr + strlen (instr); | |
6d3d9133 | 8208 | |
1768c26f PB |
8209 | for (reg = 0; reg <= SP_REGNUM; reg++) |
8210 | if (live_regs_mask & (1 << reg)) | |
8211 | { | |
8212 | int l = strlen (reg_names[reg]); | |
8213 | ||
8214 | if (first) | |
8215 | first = 0; | |
8216 | else | |
8217 | { | |
8218 | memcpy (p, ", ", 2); | |
8219 | p += 2; | |
8220 | } | |
8221 | ||
8222 | memcpy (p, "%|", 2); | |
8223 | memcpy (p + 2, reg_names[reg], l); | |
8224 | p += l + 2; | |
8225 | } | |
8226 | ||
8227 | if (live_regs_mask & (1 << LR_REGNUM)) | |
8228 | { | |
b17fe233 NC |
8229 | sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); |
8230 | /* Decide if we need to add the ^ symbol to the end of the | |
8231 | register list. This causes the saved condition codes | |
8232 | register to be copied into the current condition codes | |
8233 | register. We do the copy if we are conforming to the 32-bit | |
8234 | ABI and this is an interrupt function, or if we are | |
8235 | conforming to the 26-bit ABI. There is a special case for | |
8236 | the 26-bit ABI however, which is if we are writing back the | |
8237 | stack pointer but not loading the PC. In this case adding | |
8238 | the ^ symbol would create a type 2 LDM instruction, where | |
8239 | writeback is UNPREDICTABLE. We are safe in leaving the ^ | |
8240 | character off in this case however, since the actual return | |
8241 | instruction will be a MOVS which will restore the CPSR. */ | |
8242 | if ((TARGET_APCS_32 && IS_INTERRUPT (func_type)) | |
13eedc5a | 8243 | || (! TARGET_APCS_32 && really_return)) |
b17fe233 | 8244 | strcat (p, "^"); |
1768c26f PB |
8245 | } |
8246 | else | |
8247 | strcpy (p, "}"); | |
1d5473cb | 8248 | } |
da6558fd | 8249 | |
1768c26f PB |
8250 | output_asm_insn (instr, & operand); |
8251 | ||
3a7731fd PB |
8252 | /* See if we need to generate an extra instruction to |
8253 | perform the actual function return. */ | |
8254 | if (really_return | |
8255 | && func_type != ARM_FT_INTERWORKED | |
8256 | && (live_regs_mask & (1 << LR_REGNUM)) != 0) | |
da6558fd | 8257 | { |
3a7731fd PB |
8258 | /* The return has already been handled |
8259 | by loading the LR into the PC. */ | |
8260 | really_return = 0; | |
da6558fd | 8261 | } |
ff9940b0 | 8262 | } |
e26053d1 | 8263 | |
1768c26f | 8264 | if (really_return) |
ff9940b0 | 8265 | { |
6d3d9133 NC |
8266 | switch ((int) ARM_FUNC_TYPE (func_type)) |
8267 | { | |
8268 | case ARM_FT_ISR: | |
8269 | case ARM_FT_FIQ: | |
8270 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); | |
8271 | break; | |
8272 | ||
8273 | case ARM_FT_INTERWORKED: | |
8274 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
8275 | break; | |
8276 | ||
8277 | case ARM_FT_EXCEPTION: | |
8278 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); | |
8279 | break; | |
8280 | ||
8281 | default: | |
1768c26f PB |
8282 | /* ARMv5 implementations always provide BX, so interworking |
8283 | is the default unless APCS-26 is in use. */ | |
8284 | if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32) | |
8285 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
8286 | else | |
8287 | sprintf (instr, "mov%s%s\t%%|pc, %%|lr", | |
8288 | conditional, TARGET_APCS_32 ? "" : "s"); | |
6d3d9133 NC |
8289 | break; |
8290 | } | |
1768c26f PB |
8291 | |
8292 | output_asm_insn (instr, & operand); | |
ff9940b0 | 8293 | } |
f3bb6135 | 8294 | |
ff9940b0 RE |
8295 | return ""; |
8296 | } | |
8297 | ||
ef179a26 NC |
8298 | /* Write the function name into the code section, directly preceding |
8299 | the function prologue. | |
8300 | ||
8301 | Code will be output similar to this: | |
8302 | t0 | |
8303 | .ascii "arm_poke_function_name", 0 | |
8304 | .align | |
8305 | t1 | |
8306 | .word 0xff000000 + (t1 - t0) | |
8307 | arm_poke_function_name | |
8308 | mov ip, sp | |
8309 | stmfd sp!, {fp, ip, lr, pc} | |
8310 | sub fp, ip, #4 | |
8311 | ||
8312 | When performing a stack backtrace, code can inspect the value | |
8313 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
8314 | at location pc - 12 and the top 8 bits are set, then we know | |
8315 | that there is a function name embedded immediately preceding this | |
8316 | location and has length ((pc[-3]) & 0xff000000). | |
8317 | ||
8318 | We assume that pc is declared as a pointer to an unsigned long. | |
8319 | ||
8320 | It is of no benefit to output the function name if we are assembling | |
8321 | a leaf function. These function types will not contain a stack | |
8322 | backtrace structure, therefore it is not possible to determine the | |
8323 | function name. */ | |
8324 | ||
8325 | void | |
8326 | arm_poke_function_name (stream, name) | |
8327 | FILE * stream; | |
5f37d07c | 8328 | const char * name; |
ef179a26 NC |
8329 | { |
8330 | unsigned long alignlength; | |
8331 | unsigned long length; | |
8332 | rtx x; | |
8333 | ||
d5b7b3ae | 8334 | length = strlen (name) + 1; |
0c2ca901 | 8335 | alignlength = ROUND_UP_WORD (length); |
ef179a26 | 8336 | |
949d79eb | 8337 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 8338 | ASM_OUTPUT_ALIGN (stream, 2); |
30cf4896 | 8339 | x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); |
301d03af | 8340 | assemble_aligned_integer (UNITS_PER_WORD, x); |
ef179a26 NC |
8341 | } |
8342 | ||
6d3d9133 NC |
8343 | /* Place some comments into the assembler stream |
8344 | describing the current function. */ | |
8345 | ||
08c148a8 NB |
8346 | static void |
8347 | arm_output_function_prologue (f, frame_size) | |
6cfc7210 | 8348 | FILE * f; |
08c148a8 | 8349 | HOST_WIDE_INT frame_size; |
cce8749e | 8350 | { |
6d3d9133 | 8351 | unsigned long func_type; |
08c148a8 NB |
8352 | |
8353 | if (!TARGET_ARM) | |
8354 | { | |
8355 | thumb_output_function_prologue (f, frame_size); | |
8356 | return; | |
8357 | } | |
6d3d9133 NC |
8358 | |
8359 | /* Sanity check. */ | |
abaa26e5 | 8360 | if (arm_ccfsm_state || arm_target_insn) |
6d3d9133 | 8361 | abort (); |
31fdb4d5 | 8362 | |
6d3d9133 NC |
8363 | func_type = arm_current_func_type (); |
8364 | ||
8365 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
8366 | { | |
8367 | default: | |
8368 | case ARM_FT_NORMAL: | |
8369 | break; | |
8370 | case ARM_FT_INTERWORKED: | |
8371 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
8372 | break; | |
8373 | case ARM_FT_EXCEPTION_HANDLER: | |
8374 | asm_fprintf (f, "\t%@ C++ Exception Handler.\n"); | |
8375 | break; | |
8376 | case ARM_FT_ISR: | |
8377 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
8378 | break; | |
8379 | case ARM_FT_FIQ: | |
8380 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
8381 | break; | |
8382 | case ARM_FT_EXCEPTION: | |
8383 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
8384 | break; | |
8385 | } | |
ff9940b0 | 8386 | |
6d3d9133 NC |
8387 | if (IS_NAKED (func_type)) |
8388 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
8389 | ||
8390 | if (IS_VOLATILE (func_type)) | |
8391 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
8392 | ||
8393 | if (IS_NESTED (func_type)) | |
8394 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
8395 | ||
dd18ae56 NC |
8396 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n", |
8397 | current_function_args_size, | |
8398 | current_function_pretend_args_size, frame_size); | |
6d3d9133 | 8399 | |
3cb66fd7 | 8400 | asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", |
dd18ae56 | 8401 | frame_pointer_needed, |
3cb66fd7 | 8402 | cfun->machine->uses_anonymous_args); |
cce8749e | 8403 | |
6f7ebcbb NC |
8404 | if (cfun->machine->lr_save_eliminated) |
8405 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
8406 | ||
32de079a RE |
8407 | #ifdef AOF_ASSEMBLER |
8408 | if (flag_pic) | |
dd18ae56 | 8409 | asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM); |
32de079a | 8410 | #endif |
6d3d9133 NC |
8411 | |
8412 | return_used_this_function = 0; | |
f3bb6135 | 8413 | } |
cce8749e | 8414 | |
cd2b33d0 | 8415 | const char * |
0616531f RE |
8416 | arm_output_epilogue (really_return) |
8417 | int really_return; | |
cce8749e | 8418 | { |
949d79eb | 8419 | int reg; |
6f7ebcbb | 8420 | unsigned long saved_regs_mask; |
6d3d9133 | 8421 | unsigned long func_type; |
c882c7ac RE |
8422 | /* Floats_offset is the offset from the "virtual" frame. In an APCS |
8423 | frame that is $fp + 4 for a non-variadic function. */ | |
8424 | int floats_offset = 0; | |
cce8749e | 8425 | rtx operands[3]; |
0977774b | 8426 | int frame_size = arm_get_frame_size (); |
d5b7b3ae | 8427 | FILE * f = asm_out_file; |
6d3d9133 | 8428 | rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; |
cce8749e | 8429 | |
6d3d9133 NC |
8430 | /* If we have already generated the return instruction |
8431 | then it is futile to generate anything else. */ | |
b36ba79f | 8432 | if (use_return_insn (FALSE) && return_used_this_function) |
949d79eb | 8433 | return ""; |
cce8749e | 8434 | |
6d3d9133 | 8435 | func_type = arm_current_func_type (); |
d5b7b3ae | 8436 | |
6d3d9133 NC |
8437 | if (IS_NAKED (func_type)) |
8438 | /* Naked functions don't have epilogues. */ | |
8439 | return ""; | |
0616531f | 8440 | |
6d3d9133 | 8441 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 8442 | { |
86efdc8e | 8443 | rtx op; |
6d3d9133 NC |
8444 | |
8445 | /* A volatile function should never return. Call abort. */ | |
ed0e6530 | 8446 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 8447 | assemble_external_libcall (op); |
e2c671ba | 8448 | output_asm_insn ("bl\t%a0", &op); |
6d3d9133 | 8449 | |
949d79eb | 8450 | return ""; |
e2c671ba RE |
8451 | } |
8452 | ||
6d3d9133 NC |
8453 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER |
8454 | && ! really_return) | |
8455 | /* If we are throwing an exception, then we really must | |
8456 | be doing a return, so we can't tail-call. */ | |
8457 | abort (); | |
8458 | ||
6f7ebcbb | 8459 | saved_regs_mask = arm_compute_save_reg_mask (); |
6d3d9133 | 8460 | |
c882c7ac RE |
8461 | /* XXX We should adjust floats_offset for any anonymous args, and then |
8462 | re-adjust vfp_offset below to compensate. */ | |
8463 | ||
6d3d9133 NC |
8464 | /* Compute how far away the floats will be. */ |
8465 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++) | |
6f7ebcbb | 8466 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 8467 | floats_offset += 4; |
6d3d9133 | 8468 | |
ff9940b0 | 8469 | if (frame_pointer_needed) |
cce8749e | 8470 | { |
c882c7ac RE |
8471 | int vfp_offset = 4; |
8472 | ||
29ad9694 | 8473 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 8474 | { |
d5b7b3ae | 8475 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
5895f793 | 8476 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
8477 | { |
8478 | floats_offset += 12; | |
dd18ae56 | 8479 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
c882c7ac | 8480 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
8481 | } |
8482 | } | |
8483 | else | |
8484 | { | |
d5b7b3ae | 8485 | int start_reg = LAST_ARM_FP_REGNUM; |
b111229a | 8486 | |
d5b7b3ae | 8487 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
b111229a | 8488 | { |
5895f793 | 8489 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
8490 | { |
8491 | floats_offset += 12; | |
6cfc7210 | 8492 | |
6354dc9b | 8493 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
8494 | if (start_reg - reg == 3) |
8495 | { | |
dd18ae56 | 8496 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
c882c7ac | 8497 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
8498 | start_reg = reg - 1; |
8499 | } | |
8500 | } | |
8501 | else | |
8502 | { | |
8503 | if (reg != start_reg) | |
dd18ae56 NC |
8504 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
8505 | reg + 1, start_reg - reg, | |
c882c7ac | 8506 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
8507 | start_reg = reg - 1; |
8508 | } | |
8509 | } | |
8510 | ||
8511 | /* Just in case the last register checked also needs unstacking. */ | |
8512 | if (reg != start_reg) | |
dd18ae56 NC |
8513 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
8514 | reg + 1, start_reg - reg, | |
c882c7ac | 8515 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a | 8516 | } |
6d3d9133 | 8517 | |
6f7ebcbb | 8518 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
8519 | frame generation actually contains the old stack pointer. So a |
8520 | quick way to unwind the stack is just pop the IP register directly | |
8521 | into the stack pointer. */ | |
6f7ebcbb | 8522 | if ((saved_regs_mask & (1 << IP_REGNUM)) == 0) |
6d3d9133 | 8523 | abort (); |
6f7ebcbb NC |
8524 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
8525 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 8526 | |
6f7ebcbb | 8527 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
8528 | only need to restore the LR register (the return address), but to |
8529 | save time we can load it directly into the PC, unless we need a | |
8530 | special function exit sequence, or we are not really returning. */ | |
8531 | if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) | |
8532 | /* Delete the LR from the register mask, so that the LR on | |
8533 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 8534 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 8535 | else |
6f7ebcbb | 8536 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
6d3d9133 | 8537 | |
6f7ebcbb | 8538 | print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask); |
7b8b8ade NC |
8539 | |
8540 | if (IS_INTERRUPT (func_type)) | |
8541 | /* Interrupt handlers will have pushed the | |
8542 | IP onto the stack, so restore it now. */ | |
f55d7103 | 8543 | print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM); |
cce8749e CH |
8544 | } |
8545 | else | |
8546 | { | |
d2288d8d | 8547 | /* Restore stack pointer if necessary. */ |
56636818 | 8548 | if (frame_size + current_function_outgoing_args_size != 0) |
d2288d8d TG |
8549 | { |
8550 | operands[0] = operands[1] = stack_pointer_rtx; | |
56636818 JL |
8551 | operands[2] = GEN_INT (frame_size |
8552 | + current_function_outgoing_args_size); | |
d2288d8d TG |
8553 | output_add_immediate (operands); |
8554 | } | |
8555 | ||
29ad9694 | 8556 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 8557 | { |
d5b7b3ae | 8558 | for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) |
5895f793 | 8559 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
dd18ae56 NC |
8560 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
8561 | reg, SP_REGNUM); | |
b111229a RE |
8562 | } |
8563 | else | |
8564 | { | |
d5b7b3ae | 8565 | int start_reg = FIRST_ARM_FP_REGNUM; |
b111229a | 8566 | |
d5b7b3ae | 8567 | for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) |
b111229a | 8568 | { |
5895f793 | 8569 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
8570 | { |
8571 | if (reg - start_reg == 3) | |
8572 | { | |
dd18ae56 NC |
8573 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
8574 | start_reg, SP_REGNUM); | |
b111229a RE |
8575 | start_reg = reg + 1; |
8576 | } | |
8577 | } | |
8578 | else | |
8579 | { | |
8580 | if (reg != start_reg) | |
dd18ae56 NC |
8581 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
8582 | start_reg, reg - start_reg, | |
8583 | SP_REGNUM); | |
6cfc7210 | 8584 | |
b111229a RE |
8585 | start_reg = reg + 1; |
8586 | } | |
8587 | } | |
8588 | ||
8589 | /* Just in case the last register checked also needs unstacking. */ | |
8590 | if (reg != start_reg) | |
dd18ae56 NC |
8591 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
8592 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
8593 | } |
8594 | ||
6d3d9133 NC |
8595 | /* If we can, restore the LR into the PC. */ |
8596 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
8597 | && really_return | |
8598 | && current_function_pretend_args_size == 0 | |
6f7ebcbb | 8599 | && saved_regs_mask & (1 << LR_REGNUM)) |
cce8749e | 8600 | { |
6f7ebcbb NC |
8601 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
8602 | saved_regs_mask |= (1 << PC_REGNUM); | |
6d3d9133 | 8603 | } |
d5b7b3ae | 8604 | |
6d3d9133 NC |
8605 | /* Load the registers off the stack. If we only have one register |
8606 | to load use the LDR instruction - it is faster. */ | |
6f7ebcbb | 8607 | if (saved_regs_mask == (1 << LR_REGNUM)) |
6d3d9133 | 8608 | { |
f4864588 | 8609 | /* The exception handler ignores the LR, so we do |
6d3d9133 NC |
8610 | not really need to load it off the stack. */ |
8611 | if (eh_ofs) | |
8612 | asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM); | |
32de079a | 8613 | else |
6d3d9133 | 8614 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 8615 | } |
6f7ebcbb | 8616 | else if (saved_regs_mask) |
f1acdf8b NC |
8617 | { |
8618 | if (saved_regs_mask & (1 << SP_REGNUM)) | |
8619 | /* Note - write back to the stack register is not enabled | |
8620 | (ie "ldmfd sp!..."). We know that the stack pointer is | |
8621 | in the list of registers and if we add writeback the | |
8622 | instruction becomes UNPREDICTABLE. */ | |
8623 | print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); | |
8624 | else | |
8625 | print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask); | |
8626 | } | |
6d3d9133 NC |
8627 | |
8628 | if (current_function_pretend_args_size) | |
cce8749e | 8629 | { |
6d3d9133 NC |
8630 | /* Unwind the pre-pushed regs. */ |
8631 | operands[0] = operands[1] = stack_pointer_rtx; | |
8632 | operands[2] = GEN_INT (current_function_pretend_args_size); | |
8633 | output_add_immediate (operands); | |
8634 | } | |
8635 | } | |
32de079a | 8636 | |
9b598fa0 | 8637 | #if 0 |
6d3d9133 NC |
8638 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER) |
8639 | /* Adjust the stack to remove the exception handler stuff. */ | |
8640 | asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, | |
8641 | REGNO (eh_ofs)); | |
9b598fa0 | 8642 | #endif |
b111229a | 8643 | |
f4864588 PB |
8644 | if (! really_return |
8645 | || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
8646 | && current_function_pretend_args_size == 0 | |
8647 | && saved_regs_mask & (1 << PC_REGNUM))) | |
6d3d9133 | 8648 | return ""; |
d5b7b3ae | 8649 | |
6d3d9133 NC |
8650 | /* Generate the return instruction. */ |
8651 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
8652 | { | |
8653 | case ARM_FT_EXCEPTION_HANDLER: | |
8654 | /* Even in 26-bit mode we do a mov (rather than a movs) | |
8655 | because we don't have the PSR bits set in the address. */ | |
8656 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM); | |
8657 | break; | |
0616531f | 8658 | |
6d3d9133 NC |
8659 | case ARM_FT_ISR: |
8660 | case ARM_FT_FIQ: | |
8661 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
8662 | break; | |
8663 | ||
8664 | case ARM_FT_EXCEPTION: | |
8665 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
8666 | break; | |
8667 | ||
8668 | case ARM_FT_INTERWORKED: | |
8669 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
8670 | break; | |
8671 | ||
8672 | default: | |
8673 | if (frame_pointer_needed) | |
6bc82793 | 8674 | /* If we used the frame pointer then the return address |
6d3d9133 NC |
8675 | will have been loaded off the stack directly into the |
8676 | PC, so there is no need to issue a MOV instruction | |
8677 | here. */ | |
8678 | ; | |
8679 | else if (current_function_pretend_args_size == 0 | |
6f7ebcbb | 8680 | && (saved_regs_mask & (1 << LR_REGNUM))) |
6d3d9133 NC |
8681 | /* Similarly we may have been able to load LR into the PC |
8682 | even if we did not create a stack frame. */ | |
8683 | ; | |
8684 | else if (TARGET_APCS_32) | |
8685 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
8686 | else | |
8687 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
8688 | break; | |
cce8749e | 8689 | } |
f3bb6135 | 8690 | |
949d79eb RE |
8691 | return ""; |
8692 | } | |
8693 | ||
08c148a8 NB |
8694 | static void |
8695 | arm_output_function_epilogue (file, frame_size) | |
8696 | FILE *file ATTRIBUTE_UNUSED; | |
8697 | HOST_WIDE_INT frame_size; | |
949d79eb | 8698 | { |
d5b7b3ae RE |
8699 | if (TARGET_THUMB) |
8700 | { | |
8701 | /* ??? Probably not safe to set this here, since it assumes that a | |
8702 | function will be emitted as assembly immediately after we generate | |
8703 | RTL for it. This does not happen for inline functions. */ | |
8704 | return_used_this_function = 0; | |
8705 | } | |
8706 | else | |
8707 | { | |
0977774b JT |
8708 | /* We need to take into account any stack-frame rounding. */ |
8709 | frame_size = arm_get_frame_size (); | |
8710 | ||
d5b7b3ae RE |
8711 | if (use_return_insn (FALSE) |
8712 | && return_used_this_function | |
8713 | && (frame_size + current_function_outgoing_args_size) != 0 | |
5895f793 | 8714 | && !frame_pointer_needed) |
d5b7b3ae | 8715 | abort (); |
f3bb6135 | 8716 | |
d5b7b3ae | 8717 | /* Reset the ARM-specific per-function variables. */ |
d5b7b3ae RE |
8718 | after_arm_reorg = 0; |
8719 | } | |
f3bb6135 | 8720 | } |
e2c671ba | 8721 | |
2c849145 JM |
8722 | /* Generate and emit an insn that we will recognize as a push_multi. |
8723 | Unfortunately, since this insn does not reflect very well the actual | |
8724 | semantics of the operation, we need to annotate the insn for the benefit | |
8725 | of DWARF2 frame unwind information. */ | |
6d3d9133 | 8726 | |
2c849145 | 8727 | static rtx |
e2c671ba RE |
8728 | emit_multi_reg_push (mask) |
8729 | int mask; | |
8730 | { | |
8731 | int num_regs = 0; | |
9b598fa0 | 8732 | int num_dwarf_regs; |
e2c671ba RE |
8733 | int i, j; |
8734 | rtx par; | |
2c849145 | 8735 | rtx dwarf; |
87e27392 | 8736 | int dwarf_par_index; |
2c849145 | 8737 | rtx tmp, reg; |
e2c671ba | 8738 | |
d5b7b3ae | 8739 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 8740 | if (mask & (1 << i)) |
5895f793 | 8741 | num_regs++; |
e2c671ba RE |
8742 | |
8743 | if (num_regs == 0 || num_regs > 16) | |
8744 | abort (); | |
8745 | ||
9b598fa0 RE |
8746 | /* We don't record the PC in the dwarf frame information. */ |
8747 | num_dwarf_regs = num_regs; | |
8748 | if (mask & (1 << PC_REGNUM)) | |
8749 | num_dwarf_regs--; | |
8750 | ||
87e27392 | 8751 | /* For the body of the insn we are going to generate an UNSPEC in |
05713b80 | 8752 | parallel with several USEs. This allows the insn to be recognized |
87e27392 NC |
8753 | by the push_multi pattern in the arm.md file. The insn looks |
8754 | something like this: | |
8755 | ||
8756 | (parallel [ | |
b15bca31 RE |
8757 | (set (mem:BLK (pre_dec:BLK (reg:SI sp))) |
8758 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) | |
87e27392 NC |
8759 | (use (reg:SI 11 fp)) |
8760 | (use (reg:SI 12 ip)) | |
8761 | (use (reg:SI 14 lr)) | |
8762 | (use (reg:SI 15 pc)) | |
8763 | ]) | |
8764 | ||
8765 | For the frame note however, we try to be more explicit and actually | |
8766 | show each register being stored into the stack frame, plus a (single) | |
8767 | decrement of the stack pointer. We do it this way in order to be | |
8768 | friendly to the stack unwinding code, which only wants to see a single | |
8769 | stack decrement per instruction. The RTL we generate for the note looks | |
8770 | something like this: | |
8771 | ||
8772 | (sequence [ | |
8773 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) | |
8774 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
8775 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) | |
8776 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) | |
8777 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) | |
87e27392 NC |
8778 | ]) |
8779 | ||
8780 | This sequence is used both by the code to support stack unwinding for | |
8781 | exceptions handlers and the code to generate dwarf2 frame debugging. */ | |
8782 | ||
43cffd11 | 8783 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 8784 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
87e27392 | 8785 | dwarf_par_index = 1; |
e2c671ba | 8786 | |
d5b7b3ae | 8787 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
8788 | { |
8789 | if (mask & (1 << i)) | |
8790 | { | |
2c849145 JM |
8791 | reg = gen_rtx_REG (SImode, i); |
8792 | ||
e2c671ba | 8793 | XVECEXP (par, 0, 0) |
43cffd11 RE |
8794 | = gen_rtx_SET (VOIDmode, |
8795 | gen_rtx_MEM (BLKmode, | |
8796 | gen_rtx_PRE_DEC (BLKmode, | |
8797 | stack_pointer_rtx)), | |
8798 | gen_rtx_UNSPEC (BLKmode, | |
2c849145 | 8799 | gen_rtvec (1, reg), |
9b598fa0 | 8800 | UNSPEC_PUSH_MULT)); |
2c849145 | 8801 | |
9b598fa0 RE |
8802 | if (i != PC_REGNUM) |
8803 | { | |
8804 | tmp = gen_rtx_SET (VOIDmode, | |
8805 | gen_rtx_MEM (SImode, stack_pointer_rtx), | |
8806 | reg); | |
8807 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8808 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
8809 | dwarf_par_index++; | |
8810 | } | |
2c849145 | 8811 | |
e2c671ba RE |
8812 | break; |
8813 | } | |
8814 | } | |
8815 | ||
8816 | for (j = 1, i++; j < num_regs; i++) | |
8817 | { | |
8818 | if (mask & (1 << i)) | |
8819 | { | |
2c849145 JM |
8820 | reg = gen_rtx_REG (SImode, i); |
8821 | ||
8822 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
8823 | ||
9b598fa0 RE |
8824 | if (i != PC_REGNUM) |
8825 | { | |
8826 | tmp = gen_rtx_SET (VOIDmode, | |
8827 | gen_rtx_MEM (SImode, | |
8828 | plus_constant (stack_pointer_rtx, | |
8829 | 4 * j)), | |
8830 | reg); | |
8831 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8832 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
8833 | } | |
8834 | ||
e2c671ba RE |
8835 | j++; |
8836 | } | |
8837 | } | |
b111229a | 8838 | |
2c849145 | 8839 | par = emit_insn (par); |
87e27392 NC |
8840 | |
8841 | tmp = gen_rtx_SET (SImode, | |
8842 | stack_pointer_rtx, | |
8843 | gen_rtx_PLUS (SImode, | |
8844 | stack_pointer_rtx, | |
8845 | GEN_INT (-4 * num_regs))); | |
8846 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8847 | XVECEXP (dwarf, 0, 0) = tmp; | |
8848 | ||
2c849145 JM |
8849 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, |
8850 | REG_NOTES (par)); | |
8851 | return par; | |
b111229a RE |
8852 | } |
8853 | ||
2c849145 | 8854 | static rtx |
b111229a RE |
8855 | emit_sfm (base_reg, count) |
8856 | int base_reg; | |
8857 | int count; | |
8858 | { | |
8859 | rtx par; | |
2c849145 JM |
8860 | rtx dwarf; |
8861 | rtx tmp, reg; | |
b111229a RE |
8862 | int i; |
8863 | ||
43cffd11 | 8864 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
2c849145 | 8865 | dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
2c849145 JM |
8866 | |
8867 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
8868 | |
8869 | XVECEXP (par, 0, 0) | |
8870 | = gen_rtx_SET (VOIDmode, | |
8871 | gen_rtx_MEM (BLKmode, | |
8872 | gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), | |
8873 | gen_rtx_UNSPEC (BLKmode, | |
2c849145 | 8874 | gen_rtvec (1, reg), |
b15bca31 | 8875 | UNSPEC_PUSH_MULT)); |
2c849145 JM |
8876 | tmp |
8877 | = gen_rtx_SET (VOIDmode, | |
8878 | gen_rtx_MEM (XFmode, | |
8879 | gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), | |
8880 | reg); | |
8881 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8882 | XVECEXP (dwarf, 0, count - 1) = tmp; | |
8883 | ||
b111229a | 8884 | for (i = 1; i < count; i++) |
2c849145 JM |
8885 | { |
8886 | reg = gen_rtx_REG (XFmode, base_reg++); | |
8887 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
8888 | ||
8889 | tmp = gen_rtx_SET (VOIDmode, | |
8890 | gen_rtx_MEM (XFmode, | |
8891 | gen_rtx_PRE_DEC (BLKmode, | |
8892 | stack_pointer_rtx)), | |
8893 | reg); | |
8894 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8895 | XVECEXP (dwarf, 0, count - i - 1) = tmp; | |
8896 | } | |
b111229a | 8897 | |
2c849145 JM |
8898 | par = emit_insn (par); |
8899 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
8900 | REG_NOTES (par)); | |
8901 | return par; | |
e2c671ba RE |
8902 | } |
8903 | ||
095bb276 NC |
8904 | /* Compute the distance from register FROM to register TO. |
8905 | These can be the arg pointer (26), the soft frame pointer (25), | |
8906 | the stack pointer (13) or the hard frame pointer (11). | |
8907 | Typical stack layout looks like this: | |
8908 | ||
8909 | old stack pointer -> | | | |
8910 | ---- | |
8911 | | | \ | |
8912 | | | saved arguments for | |
8913 | | | vararg functions | |
8914 | | | / | |
8915 | -- | |
8916 | hard FP & arg pointer -> | | \ | |
8917 | | | stack | |
8918 | | | frame | |
8919 | | | / | |
8920 | -- | |
8921 | | | \ | |
8922 | | | call saved | |
8923 | | | registers | |
8924 | soft frame pointer -> | | / | |
8925 | -- | |
8926 | | | \ | |
8927 | | | local | |
8928 | | | variables | |
8929 | | | / | |
8930 | -- | |
8931 | | | \ | |
8932 | | | outgoing | |
8933 | | | arguments | |
8934 | current stack pointer -> | | / | |
8935 | -- | |
8936 | ||
43aa4e05 | 8937 | For a given function some or all of these stack components |
095bb276 NC |
8938 | may not be needed, giving rise to the possibility of |
8939 | eliminating some of the registers. | |
8940 | ||
825dda42 | 8941 | The values returned by this function must reflect the behavior |
095bb276 NC |
8942 | of arm_expand_prologue() and arm_compute_save_reg_mask(). |
8943 | ||
8944 | The sign of the number returned reflects the direction of stack | |
8945 | growth, so the values are positive for all eliminations except | |
8946 | from the soft frame pointer to the hard frame pointer. */ | |
8947 | ||
8948 | unsigned int | |
8949 | arm_compute_initial_elimination_offset (from, to) | |
8950 | unsigned int from; | |
8951 | unsigned int to; | |
8952 | { | |
0977774b | 8953 | unsigned int local_vars = arm_get_frame_size (); |
095bb276 NC |
8954 | unsigned int outgoing_args = current_function_outgoing_args_size; |
8955 | unsigned int stack_frame; | |
8956 | unsigned int call_saved_registers; | |
8957 | unsigned long func_type; | |
8958 | ||
8959 | func_type = arm_current_func_type (); | |
8960 | ||
8961 | /* Volatile functions never return, so there is | |
8962 | no need to save call saved registers. */ | |
8963 | call_saved_registers = 0; | |
8964 | if (! IS_VOLATILE (func_type)) | |
8965 | { | |
121308d4 | 8966 | unsigned int reg_mask; |
095bb276 NC |
8967 | unsigned int reg; |
8968 | ||
1d6e90ac | 8969 | /* Make sure that we compute which registers will be saved |
121308d4 NC |
8970 | on the stack using the same algorithm that is used by |
8971 | arm_compute_save_reg_mask(). */ | |
8972 | reg_mask = arm_compute_save_reg0_reg12_mask (); | |
095bb276 | 8973 | |
121308d4 NC |
8974 | /* Now count the number of bits set in save_reg_mask. |
8975 | For each set bit we need 4 bytes of stack space. */ | |
121308d4 NC |
8976 | while (reg_mask) |
8977 | { | |
8978 | call_saved_registers += 4; | |
8979 | reg_mask = reg_mask & ~ (reg_mask & - reg_mask); | |
8980 | } | |
095bb276 | 8981 | |
e43dd89d RE |
8982 | if ((regs_ever_live[LR_REGNUM] |
8983 | /* If optimizing for size, then we save the link register if | |
8984 | any other integer register is saved. This gives a smaller | |
8985 | return sequence. */ | |
8986 | || (optimize_size && call_saved_registers > 0)) | |
8987 | /* But if a stack frame is going to be created, the LR will | |
8988 | be saved as part of that, so we do not need to allow for | |
8989 | it here. */ | |
095bb276 NC |
8990 | && ! frame_pointer_needed) |
8991 | call_saved_registers += 4; | |
ef7112de NC |
8992 | |
8993 | /* If the hard floating point registers are going to be | |
8994 | used then they must be saved on the stack as well. | |
8995 | Each register occupies 12 bytes of stack space. */ | |
8996 | for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg ++) | |
8997 | if (regs_ever_live[reg] && ! call_used_regs[reg]) | |
8998 | call_saved_registers += 12; | |
095bb276 NC |
8999 | } |
9000 | ||
9001 | /* The stack frame contains 4 registers - the old frame pointer, | |
9002 | the old stack pointer, the return address and PC of the start | |
9003 | of the function. */ | |
9004 | stack_frame = frame_pointer_needed ? 16 : 0; | |
9005 | ||
095bb276 NC |
9006 | /* OK, now we have enough information to compute the distances. |
9007 | There must be an entry in these switch tables for each pair | |
9008 | of registers in ELIMINABLE_REGS, even if some of the entries | |
9009 | seem to be redundant or useless. */ | |
9010 | switch (from) | |
9011 | { | |
9012 | case ARG_POINTER_REGNUM: | |
9013 | switch (to) | |
9014 | { | |
9015 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
9016 | return 0; | |
9017 | ||
9018 | case FRAME_POINTER_REGNUM: | |
9019 | /* This is the reverse of the soft frame pointer | |
9020 | to hard frame pointer elimination below. */ | |
9021 | if (call_saved_registers == 0 && stack_frame == 0) | |
9022 | return 0; | |
9023 | return (call_saved_registers + stack_frame - 4); | |
9024 | ||
9025 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
9026 | /* If there is no stack frame then the hard | |
9027 | frame pointer and the arg pointer coincide. */ | |
9028 | if (stack_frame == 0 && call_saved_registers != 0) | |
9029 | return 0; | |
9030 | /* FIXME: Not sure about this. Maybe we should always return 0 ? */ | |
9031 | return (frame_pointer_needed | |
9032 | && current_function_needs_context | |
3cb66fd7 | 9033 | && ! cfun->machine->uses_anonymous_args) ? 4 : 0; |
095bb276 NC |
9034 | |
9035 | case STACK_POINTER_REGNUM: | |
9036 | /* If nothing has been pushed on the stack at all | |
9037 | then this will return -4. This *is* correct! */ | |
9038 | return call_saved_registers + stack_frame + local_vars + outgoing_args - 4; | |
9039 | ||
9040 | default: | |
9041 | abort (); | |
9042 | } | |
9043 | break; | |
9044 | ||
9045 | case FRAME_POINTER_REGNUM: | |
9046 | switch (to) | |
9047 | { | |
9048 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
9049 | return 0; | |
9050 | ||
9051 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
9052 | /* The hard frame pointer points to the top entry in the | |
9053 | stack frame. The soft frame pointer to the bottom entry | |
9054 | in the stack frame. If there is no stack frame at all, | |
9055 | then they are identical. */ | |
9056 | if (call_saved_registers == 0 && stack_frame == 0) | |
9057 | return 0; | |
9058 | return - (call_saved_registers + stack_frame - 4); | |
9059 | ||
9060 | case STACK_POINTER_REGNUM: | |
9061 | return local_vars + outgoing_args; | |
9062 | ||
9063 | default: | |
9064 | abort (); | |
9065 | } | |
9066 | break; | |
9067 | ||
9068 | default: | |
9069 | /* You cannot eliminate from the stack pointer. | |
9070 | In theory you could eliminate from the hard frame | |
9071 | pointer to the stack pointer, but this will never | |
9072 | happen, since if a stack frame is not needed the | |
9073 | hard frame pointer will never be used. */ | |
9074 | abort (); | |
9075 | } | |
9076 | } | |
9077 | ||
0977774b JT |
9078 | /* Calculate the size of the stack frame, taking into account any |
9079 | padding that is required to ensure stack-alignment. */ | |
9080 | ||
9081 | HOST_WIDE_INT | |
9082 | arm_get_frame_size () | |
9083 | { | |
9084 | int regno; | |
9085 | ||
0c2ca901 | 9086 | int base_size = ROUND_UP_WORD (get_frame_size ()); |
0977774b JT |
9087 | int entry_size = 0; |
9088 | unsigned long func_type = arm_current_func_type (); | |
c231c91e | 9089 | int leaf; |
0977774b JT |
9090 | |
9091 | if (! TARGET_ARM) | |
9092 | abort(); | |
9093 | ||
9094 | if (! TARGET_ATPCS) | |
9095 | return base_size; | |
9096 | ||
c231c91e RE |
9097 | /* We need to know if we are a leaf function. Unfortunately, it |
9098 | is possible to be called after start_sequence has been called, | |
9099 | which causes get_insns to return the insns for the sequence, | |
9100 | not the function, which will cause leaf_function_p to return | |
9101 | the incorrect result. | |
9102 | ||
9103 | To work around this, we cache the computed frame size. This | |
9104 | works because we will only be calling RTL expanders that need | |
9105 | to know about leaf functions once reload has completed, and the | |
9106 | frame size cannot be changed after that time, so we can safely | |
9107 | use the cached value. */ | |
9108 | ||
9109 | if (reload_completed) | |
9110 | return cfun->machine->frame_size; | |
9111 | ||
9112 | leaf = leaf_function_p (); | |
9113 | ||
9114 | /* A leaf function does not need any stack alignment if it has nothing | |
9115 | on the stack. */ | |
9116 | if (leaf && base_size == 0) | |
9117 | { | |
9118 | cfun->machine->frame_size = 0; | |
9119 | return 0; | |
9120 | } | |
9121 | ||
0977774b JT |
9122 | /* We know that SP will be word aligned on entry, and we must |
9123 | preserve that condition at any subroutine call. But those are | |
9124 | the only constraints. */ | |
9125 | ||
9126 | /* Space for variadic functions. */ | |
9127 | if (current_function_pretend_args_size) | |
9128 | entry_size += current_function_pretend_args_size; | |
9129 | ||
9130 | /* Space for saved registers. */ | |
9131 | entry_size += bit_count (arm_compute_save_reg_mask ()) * 4; | |
9132 | ||
9133 | /* Space for saved FPA registers. */ | |
9134 | if (! IS_VOLATILE (func_type)) | |
9135 | { | |
9136 | for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++) | |
9137 | if (regs_ever_live[regno] && ! call_used_regs[regno]) | |
9138 | entry_size += 12; | |
9139 | } | |
9140 | ||
9141 | if ((entry_size + base_size + current_function_outgoing_args_size) & 7) | |
9142 | base_size += 4; | |
9143 | if ((entry_size + base_size + current_function_outgoing_args_size) & 7) | |
9144 | abort (); | |
9145 | ||
c231c91e RE |
9146 | cfun->machine->frame_size = base_size; |
9147 | ||
0977774b JT |
9148 | return base_size; |
9149 | } | |
9150 | ||
6d3d9133 NC |
9151 | /* Generate the prologue instructions for entry into an ARM function. */ |
9152 | ||
e2c671ba RE |
9153 | void |
9154 | arm_expand_prologue () | |
9155 | { | |
9156 | int reg; | |
6d3d9133 | 9157 | rtx amount; |
2c849145 | 9158 | rtx insn; |
68dfd979 | 9159 | rtx ip_rtx; |
6d3d9133 NC |
9160 | unsigned long live_regs_mask; |
9161 | unsigned long func_type; | |
68dfd979 | 9162 | int fp_offset = 0; |
095bb276 NC |
9163 | int saved_pretend_args = 0; |
9164 | unsigned int args_to_push; | |
d3236b4d | 9165 | |
6d3d9133 | 9166 | func_type = arm_current_func_type (); |
e2c671ba | 9167 | |
31fdb4d5 | 9168 | /* Naked functions don't have prologues. */ |
6d3d9133 | 9169 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
9170 | return; |
9171 | ||
095bb276 NC |
9172 | /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ |
9173 | args_to_push = current_function_pretend_args_size; | |
9174 | ||
6d3d9133 NC |
9175 | /* Compute which register we will have to save onto the stack. */ |
9176 | live_regs_mask = arm_compute_save_reg_mask (); | |
e2c671ba | 9177 | |
68dfd979 | 9178 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 9179 | |
e2c671ba RE |
9180 | if (frame_pointer_needed) |
9181 | { | |
7b8b8ade NC |
9182 | if (IS_INTERRUPT (func_type)) |
9183 | { | |
9184 | /* Interrupt functions must not corrupt any registers. | |
9185 | Creating a frame pointer however, corrupts the IP | |
9186 | register, so we must push it first. */ | |
9187 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
121308d4 NC |
9188 | |
9189 | /* Do not set RTX_FRAME_RELATED_P on this insn. | |
9190 | The dwarf stack unwinding code only wants to see one | |
9191 | stack decrement per function, and this is not it. If | |
9192 | this instruction is labeled as being part of the frame | |
9193 | creation sequence then dwarf2out_frame_debug_expr will | |
9194 | abort when it encounters the assignment of IP to FP | |
9195 | later on, since the use of SP here establishes SP as | |
9196 | the CFA register and not IP. | |
9197 | ||
9198 | Anyway this instruction is not really part of the stack | |
9199 | frame creation although it is part of the prologue. */ | |
7b8b8ade NC |
9200 | } |
9201 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
9202 | { |
9203 | /* The Static chain register is the same as the IP register | |
9204 | used as a scratch register during stack frame creation. | |
9205 | To get around this need to find somewhere to store IP | |
9206 | whilst the frame is being created. We try the following | |
9207 | places in order: | |
9208 | ||
6d3d9133 | 9209 | 1. The last argument register. |
68dfd979 NC |
9210 | 2. A slot on the stack above the frame. (This only |
9211 | works if the function is not a varargs function). | |
095bb276 NC |
9212 | 3. Register r3, after pushing the argument registers |
9213 | onto the stack. | |
6d3d9133 | 9214 | |
34ce3d7b JM |
9215 | Note - we only need to tell the dwarf2 backend about the SP |
9216 | adjustment in the second variant; the static chain register | |
9217 | doesn't need to be unwound, as it doesn't contain a value | |
9218 | inherited from the caller. */ | |
d3236b4d | 9219 | |
68dfd979 NC |
9220 | if (regs_ever_live[3] == 0) |
9221 | { | |
9222 | insn = gen_rtx_REG (SImode, 3); | |
9223 | insn = gen_rtx_SET (SImode, insn, ip_rtx); | |
d3236b4d | 9224 | insn = emit_insn (insn); |
68dfd979 | 9225 | } |
095bb276 | 9226 | else if (args_to_push == 0) |
68dfd979 | 9227 | { |
34ce3d7b | 9228 | rtx dwarf; |
68dfd979 NC |
9229 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
9230 | insn = gen_rtx_MEM (SImode, insn); | |
9231 | insn = gen_rtx_SET (VOIDmode, insn, ip_rtx); | |
9232 | insn = emit_insn (insn); | |
34ce3d7b | 9233 | |
68dfd979 | 9234 | fp_offset = 4; |
34ce3d7b JM |
9235 | |
9236 | /* Just tell the dwarf backend that we adjusted SP. */ | |
9237 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
9238 | gen_rtx_PLUS (SImode, stack_pointer_rtx, | |
9239 | GEN_INT (-fp_offset))); | |
9240 | RTX_FRAME_RELATED_P (insn) = 1; | |
9241 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
9242 | dwarf, REG_NOTES (insn)); | |
68dfd979 NC |
9243 | } |
9244 | else | |
095bb276 NC |
9245 | { |
9246 | /* Store the args on the stack. */ | |
3cb66fd7 | 9247 | if (cfun->machine->uses_anonymous_args) |
095bb276 NC |
9248 | insn = emit_multi_reg_push |
9249 | ((0xf0 >> (args_to_push / 4)) & 0xf); | |
9250 | else | |
9251 | insn = emit_insn | |
9252 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
9253 | GEN_INT (- args_to_push))); | |
9254 | ||
9255 | RTX_FRAME_RELATED_P (insn) = 1; | |
9256 | ||
9257 | saved_pretend_args = 1; | |
9258 | fp_offset = args_to_push; | |
9259 | args_to_push = 0; | |
9260 | ||
9261 | /* Now reuse r3 to preserve IP. */ | |
9262 | insn = gen_rtx_REG (SImode, 3); | |
9263 | insn = gen_rtx_SET (SImode, insn, ip_rtx); | |
9264 | (void) emit_insn (insn); | |
9265 | } | |
68dfd979 NC |
9266 | } |
9267 | ||
68dfd979 NC |
9268 | if (fp_offset) |
9269 | { | |
9270 | insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset)); | |
9271 | insn = gen_rtx_SET (SImode, ip_rtx, insn); | |
9272 | } | |
9273 | else | |
9274 | insn = gen_movsi (ip_rtx, stack_pointer_rtx); | |
9275 | ||
6d3d9133 | 9276 | insn = emit_insn (insn); |
8e56560e | 9277 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
9278 | } |
9279 | ||
095bb276 | 9280 | if (args_to_push) |
e2c671ba | 9281 | { |
6d3d9133 | 9282 | /* Push the argument registers, or reserve space for them. */ |
3cb66fd7 | 9283 | if (cfun->machine->uses_anonymous_args) |
2c849145 | 9284 | insn = emit_multi_reg_push |
095bb276 | 9285 | ((0xf0 >> (args_to_push / 4)) & 0xf); |
e2c671ba | 9286 | else |
2c849145 JM |
9287 | insn = emit_insn |
9288 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
095bb276 | 9289 | GEN_INT (- args_to_push))); |
2c849145 | 9290 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
9291 | } |
9292 | ||
06bea5aa NC |
9293 | /* If this is an interrupt service routine, and the link register |
9294 | is going to be pushed, and we are not creating a stack frame, | |
9295 | (which would involve an extra push of IP and a pop in the epilogue) | |
9296 | subtracting four from LR now will mean that the function return | |
9297 | can be done with a single instruction. */ | |
3a7731fd | 9298 | if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) |
06bea5aa NC |
9299 | && (live_regs_mask & (1 << LR_REGNUM)) != 0 |
9300 | && ! frame_pointer_needed) | |
9301 | emit_insn (gen_rtx_SET (SImode, | |
9302 | gen_rtx_REG (SImode, LR_REGNUM), | |
9303 | gen_rtx_PLUS (SImode, | |
9304 | gen_rtx_REG (SImode, LR_REGNUM), | |
9305 | GEN_INT (-4)))); | |
3a7731fd | 9306 | |
e2c671ba RE |
9307 | if (live_regs_mask) |
9308 | { | |
2c849145 JM |
9309 | insn = emit_multi_reg_push (live_regs_mask); |
9310 | RTX_FRAME_RELATED_P (insn) = 1; | |
e2c671ba | 9311 | } |
d5b7b3ae | 9312 | |
6d3d9133 | 9313 | if (! IS_VOLATILE (func_type)) |
b111229a | 9314 | { |
29ad9694 RE |
9315 | /* Save any floating point call-saved registers used by this |
9316 | function. */ | |
9317 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
b111229a | 9318 | { |
29ad9694 | 9319 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
5895f793 | 9320 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
2c849145 JM |
9321 | { |
9322 | insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); | |
9323 | insn = gen_rtx_MEM (XFmode, insn); | |
9324 | insn = emit_insn (gen_rtx_SET (VOIDmode, insn, | |
9325 | gen_rtx_REG (XFmode, reg))); | |
9326 | RTX_FRAME_RELATED_P (insn) = 1; | |
9327 | } | |
b111229a RE |
9328 | } |
9329 | else | |
9330 | { | |
d5b7b3ae | 9331 | int start_reg = LAST_ARM_FP_REGNUM; |
b111229a | 9332 | |
29ad9694 | 9333 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
b111229a | 9334 | { |
5895f793 | 9335 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
9336 | { |
9337 | if (start_reg - reg == 3) | |
9338 | { | |
2c849145 JM |
9339 | insn = emit_sfm (reg, 4); |
9340 | RTX_FRAME_RELATED_P (insn) = 1; | |
b111229a RE |
9341 | start_reg = reg - 1; |
9342 | } | |
9343 | } | |
9344 | else | |
9345 | { | |
9346 | if (start_reg != reg) | |
2c849145 JM |
9347 | { |
9348 | insn = emit_sfm (reg + 1, start_reg - reg); | |
9349 | RTX_FRAME_RELATED_P (insn) = 1; | |
9350 | } | |
b111229a RE |
9351 | start_reg = reg - 1; |
9352 | } | |
9353 | } | |
9354 | ||
9355 | if (start_reg != reg) | |
2c849145 JM |
9356 | { |
9357 | insn = emit_sfm (reg + 1, start_reg - reg); | |
9358 | RTX_FRAME_RELATED_P (insn) = 1; | |
9359 | } | |
b111229a RE |
9360 | } |
9361 | } | |
e2c671ba RE |
9362 | |
9363 | if (frame_pointer_needed) | |
2c849145 | 9364 | { |
6d3d9133 | 9365 | /* Create the new frame pointer. */ |
095bb276 | 9366 | insn = GEN_INT (-(4 + args_to_push + fp_offset)); |
68dfd979 | 9367 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); |
2c849145 | 9368 | RTX_FRAME_RELATED_P (insn) = 1; |
68dfd979 | 9369 | |
6d3d9133 | 9370 | if (IS_NESTED (func_type)) |
68dfd979 NC |
9371 | { |
9372 | /* Recover the static chain register. */ | |
095bb276 NC |
9373 | if (regs_ever_live [3] == 0 |
9374 | || saved_pretend_args) | |
1d6e90ac | 9375 | insn = gen_rtx_REG (SImode, 3); |
68dfd979 NC |
9376 | else /* if (current_function_pretend_args_size == 0) */ |
9377 | { | |
29ad9694 RE |
9378 | insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, |
9379 | GEN_INT (4)); | |
68dfd979 | 9380 | insn = gen_rtx_MEM (SImode, insn); |
68dfd979 | 9381 | } |
1d6e90ac | 9382 | |
c14a3a45 NC |
9383 | emit_insn (gen_rtx_SET (SImode, ip_rtx, insn)); |
9384 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
6bacc7b0 | 9385 | emit_insn (gen_prologue_use (ip_rtx)); |
68dfd979 | 9386 | } |
2c849145 | 9387 | } |
e2c671ba | 9388 | |
0977774b | 9389 | amount = GEN_INT (-(arm_get_frame_size () |
6d3d9133 NC |
9390 | + current_function_outgoing_args_size)); |
9391 | ||
e2c671ba RE |
9392 | if (amount != const0_rtx) |
9393 | { | |
745b9093 JM |
9394 | /* This add can produce multiple insns for a large constant, so we |
9395 | need to get tricky. */ | |
9396 | rtx last = get_last_insn (); | |
2c849145 JM |
9397 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
9398 | amount)); | |
745b9093 JM |
9399 | do |
9400 | { | |
9401 | last = last ? NEXT_INSN (last) : get_insns (); | |
9402 | RTX_FRAME_RELATED_P (last) = 1; | |
9403 | } | |
9404 | while (last != insn); | |
e04c2d6c RE |
9405 | |
9406 | /* If the frame pointer is needed, emit a special barrier that | |
9407 | will prevent the scheduler from moving stores to the frame | |
9408 | before the stack adjustment. */ | |
9409 | if (frame_pointer_needed) | |
3894f59e RE |
9410 | insn = emit_insn (gen_stack_tie (stack_pointer_rtx, |
9411 | hard_frame_pointer_rtx)); | |
e2c671ba RE |
9412 | } |
9413 | ||
9414 | /* If we are profiling, make sure no instructions are scheduled before | |
f5a1b0d2 NC |
9415 | the call to mcount. Similarly if the user has requested no |
9416 | scheduling in the prolog. */ | |
70f4f91c | 9417 | if (current_function_profile || TARGET_NO_SCHED_PRO) |
e2c671ba | 9418 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
9419 | |
9420 | /* If the link register is being kept alive, with the return address in it, | |
9421 | then make sure that it does not get reused by the ce2 pass. */ | |
9422 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
9423 | { | |
6bacc7b0 | 9424 | emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); |
6f7ebcbb NC |
9425 | cfun->machine->lr_save_eliminated = 1; |
9426 | } | |
e2c671ba | 9427 | } |
cce8749e | 9428 | \f |
9997d19d RE |
9429 | /* If CODE is 'd', then the X is a condition operand and the instruction |
9430 | should only be executed if the condition is true. | |
ddd5a7c1 | 9431 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
9432 | should only be executed if the condition is false: however, if the mode |
9433 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
9434 | do this because in these circumstances !GE does not necessarily imply LT; | |
9435 | in these cases the instruction pattern will take care to make sure that | |
9436 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 9437 | doing this instruction unconditionally. |
9997d19d RE |
9438 | If CODE is 'N' then X is a floating point operand that must be negated |
9439 | before output. | |
9440 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
9441 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
9442 | ||
9443 | void | |
9444 | arm_print_operand (stream, x, code) | |
62b10bbc | 9445 | FILE * stream; |
9997d19d RE |
9446 | rtx x; |
9447 | int code; | |
9448 | { | |
9449 | switch (code) | |
9450 | { | |
9451 | case '@': | |
f3139301 | 9452 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
9453 | return; |
9454 | ||
d5b7b3ae RE |
9455 | case '_': |
9456 | fputs (user_label_prefix, stream); | |
9457 | return; | |
9458 | ||
9997d19d | 9459 | case '|': |
f3139301 | 9460 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
9461 | return; |
9462 | ||
9463 | case '?': | |
9464 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
cca0a211 RE |
9465 | { |
9466 | if (TARGET_THUMB || current_insn_predicate != NULL) | |
9467 | abort (); | |
9468 | ||
9469 | fputs (arm_condition_codes[arm_current_cc], stream); | |
9470 | } | |
9471 | else if (current_insn_predicate) | |
9472 | { | |
9473 | enum arm_cond_code code; | |
9474 | ||
9475 | if (TARGET_THUMB) | |
9476 | abort (); | |
9477 | ||
9478 | code = get_arm_condition_code (current_insn_predicate); | |
9479 | fputs (arm_condition_codes[code], stream); | |
9480 | } | |
9997d19d RE |
9481 | return; |
9482 | ||
9483 | case 'N': | |
9484 | { | |
9485 | REAL_VALUE_TYPE r; | |
9486 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
9487 | r = REAL_VALUE_NEGATE (r); | |
9488 | fprintf (stream, "%s", fp_const_from_val (&r)); | |
9489 | } | |
9490 | return; | |
9491 | ||
9492 | case 'B': | |
9493 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
9494 | { |
9495 | HOST_WIDE_INT val; | |
5895f793 | 9496 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 9497 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 9498 | } |
9997d19d RE |
9499 | else |
9500 | { | |
9501 | putc ('~', stream); | |
9502 | output_addr_const (stream, x); | |
9503 | } | |
9504 | return; | |
9505 | ||
9506 | case 'i': | |
9507 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
9508 | return; | |
9509 | ||
9b6b54e2 NC |
9510 | /* Truncate Cirrus shift counts. */ |
9511 | case 's': | |
9512 | if (GET_CODE (x) == CONST_INT) | |
9513 | { | |
9514 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); | |
9515 | return; | |
9516 | } | |
9517 | arm_print_operand (stream, x, 0); | |
9518 | return; | |
9519 | ||
9997d19d RE |
9520 | case 'I': |
9521 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
9522 | return; | |
9523 | ||
9524 | case 'S': | |
9525 | { | |
9526 | HOST_WIDE_INT val; | |
5895f793 | 9527 | const char * shift = shift_op (x, &val); |
9997d19d | 9528 | |
e2c671ba RE |
9529 | if (shift) |
9530 | { | |
5895f793 | 9531 | fprintf (stream, ", %s ", shift_op (x, &val)); |
e2c671ba RE |
9532 | if (val == -1) |
9533 | arm_print_operand (stream, XEXP (x, 1), 0); | |
9534 | else | |
4bc74ece NC |
9535 | { |
9536 | fputc ('#', stream); | |
36ba9cb8 | 9537 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 9538 | } |
e2c671ba | 9539 | } |
9997d19d RE |
9540 | } |
9541 | return; | |
9542 | ||
d5b7b3ae RE |
9543 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
9544 | ||
9545 | In a pair of registers containing a DI or DF value the 'Q' | |
9546 | operand returns the register number of the register containing | |
9547 | the least signficant part of the value. The 'R' operand returns | |
9548 | the register number of the register containing the most | |
9549 | significant part of the value. | |
9550 | ||
9551 | The 'H' operand returns the higher of the two register numbers. | |
9552 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
9553 | same as the 'Q' operand, since the most signficant part of the | |
9554 | value is held in the lower number register. The reverse is true | |
9555 | on systems where WORDS_BIG_ENDIAN is false. | |
9556 | ||
9557 | The purpose of these operands is to distinguish between cases | |
9558 | where the endian-ness of the values is important (for example | |
9559 | when they are added together), and cases where the endian-ness | |
9560 | is irrelevant, but the order of register operations is important. | |
9561 | For example when loading a value from memory into a register | |
9562 | pair, the endian-ness does not matter. Provided that the value | |
9563 | from the lower memory address is put into the lower numbered | |
9564 | register, and the value from the higher address is put into the | |
9565 | higher numbered register, the load will work regardless of whether | |
9566 | the value being loaded is big-wordian or little-wordian. The | |
9567 | order of the two register loads can matter however, if the address | |
9568 | of the memory location is actually held in one of the registers | |
9569 | being overwritten by the load. */ | |
c1c2bc04 | 9570 | case 'Q': |
d5b7b3ae | 9571 | if (REGNO (x) > LAST_ARM_REGNUM) |
c1c2bc04 | 9572 | abort (); |
d5b7b3ae | 9573 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
9574 | return; |
9575 | ||
9997d19d | 9576 | case 'R': |
d5b7b3ae | 9577 | if (REGNO (x) > LAST_ARM_REGNUM) |
9997d19d | 9578 | abort (); |
d5b7b3ae RE |
9579 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
9580 | return; | |
9581 | ||
9582 | case 'H': | |
9583 | if (REGNO (x) > LAST_ARM_REGNUM) | |
9584 | abort (); | |
9585 | asm_fprintf (stream, "%r", REGNO (x) + 1); | |
9997d19d RE |
9586 | return; |
9587 | ||
9588 | case 'm': | |
d5b7b3ae RE |
9589 | asm_fprintf (stream, "%r", |
9590 | GET_CODE (XEXP (x, 0)) == REG | |
9591 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
9592 | return; |
9593 | ||
9594 | case 'M': | |
dd18ae56 | 9595 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae | 9596 | REGNO (x), |
e9d7b180 | 9597 | REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); |
9997d19d RE |
9598 | return; |
9599 | ||
9600 | case 'd': | |
64e92a26 RE |
9601 | /* CONST_TRUE_RTX means always -- that's the default. */ |
9602 | if (x == const_true_rtx) | |
d5b7b3ae RE |
9603 | return; |
9604 | ||
9605 | if (TARGET_ARM) | |
9997d19d RE |
9606 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
9607 | stream); | |
d5b7b3ae RE |
9608 | else |
9609 | fputs (thumb_condition_code (x, 0), stream); | |
9997d19d RE |
9610 | return; |
9611 | ||
9612 | case 'D': | |
64e92a26 RE |
9613 | /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever |
9614 | want to do that. */ | |
9615 | if (x == const_true_rtx) | |
9616 | abort (); | |
d5b7b3ae RE |
9617 | |
9618 | if (TARGET_ARM) | |
9619 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE | |
9620 | (get_arm_condition_code (x))], | |
9997d19d | 9621 | stream); |
d5b7b3ae RE |
9622 | else |
9623 | fputs (thumb_condition_code (x, 1), stream); | |
9997d19d RE |
9624 | return; |
9625 | ||
9b6b54e2 NC |
9626 | |
9627 | /* Cirrus registers can be accessed in a variety of ways: | |
9628 | single floating point (f) | |
9629 | double floating point (d) | |
9630 | 32bit integer (fx) | |
9631 | 64bit integer (dx). */ | |
9632 | case 'W': /* Cirrus register in F mode. */ | |
9633 | case 'X': /* Cirrus register in D mode. */ | |
9634 | case 'Y': /* Cirrus register in FX mode. */ | |
9635 | case 'Z': /* Cirrus register in DX mode. */ | |
9636 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
9637 | abort (); | |
9638 | ||
9639 | fprintf (stream, "mv%s%s", | |
9640 | code == 'W' ? "f" | |
9641 | : code == 'X' ? "d" | |
9642 | : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); | |
9643 | ||
9644 | return; | |
9645 | ||
9646 | /* Print cirrus register in the mode specified by the register's mode. */ | |
9647 | case 'V': | |
9648 | { | |
9649 | int mode = GET_MODE (x); | |
9650 | ||
9651 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
9652 | abort (); | |
9653 | ||
9654 | fprintf (stream, "mv%s%s", | |
9655 | mode == DFmode ? "d" | |
9656 | : mode == SImode ? "fx" | |
9657 | : mode == DImode ? "dx" | |
9658 | : "f", reg_names[REGNO (x)] + 2); | |
9659 | ||
9660 | return; | |
9661 | } | |
9662 | ||
9997d19d RE |
9663 | default: |
9664 | if (x == 0) | |
9665 | abort (); | |
9666 | ||
9667 | if (GET_CODE (x) == REG) | |
d5b7b3ae | 9668 | asm_fprintf (stream, "%r", REGNO (x)); |
9997d19d RE |
9669 | else if (GET_CODE (x) == MEM) |
9670 | { | |
9671 | output_memory_reference_mode = GET_MODE (x); | |
9672 | output_address (XEXP (x, 0)); | |
9673 | } | |
9674 | else if (GET_CODE (x) == CONST_DOUBLE) | |
9675 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
9676 | else if (GET_CODE (x) == NEG) | |
6354dc9b | 9677 | abort (); /* This should never happen now. */ |
9997d19d RE |
9678 | else |
9679 | { | |
9680 | fputc ('#', stream); | |
9681 | output_addr_const (stream, x); | |
9682 | } | |
9683 | } | |
9684 | } | |
cce8749e | 9685 | \f |
301d03af RS |
9686 | #ifndef AOF_ASSEMBLER |
9687 | /* Target hook for assembling integer objects. The ARM version needs to | |
9688 | handle word-sized values specially. */ | |
9689 | ||
9690 | static bool | |
9691 | arm_assemble_integer (x, size, aligned_p) | |
9692 | rtx x; | |
9693 | unsigned int size; | |
9694 | int aligned_p; | |
9695 | { | |
9696 | if (size == UNITS_PER_WORD && aligned_p) | |
9697 | { | |
9698 | fputs ("\t.word\t", asm_out_file); | |
9699 | output_addr_const (asm_out_file, x); | |
9700 | ||
9701 | /* Mark symbols as position independent. We only do this in the | |
9702 | .text segment, not in the .data segment. */ | |
9703 | if (NEED_GOT_RELOC && flag_pic && making_const_table && | |
9704 | (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) | |
9705 | { | |
e26053d1 | 9706 | if (GET_CODE (x) == SYMBOL_REF |
14f583b8 PB |
9707 | && (CONSTANT_POOL_ADDRESS_P (x) |
9708 | || ENCODED_SHORT_CALL_ATTR_P (XSTR (x, 0)))) | |
301d03af RS |
9709 | fputs ("(GOTOFF)", asm_out_file); |
9710 | else if (GET_CODE (x) == LABEL_REF) | |
9711 | fputs ("(GOTOFF)", asm_out_file); | |
9712 | else | |
9713 | fputs ("(GOT)", asm_out_file); | |
9714 | } | |
9715 | fputc ('\n', asm_out_file); | |
9716 | return true; | |
9717 | } | |
1d6e90ac | 9718 | |
301d03af RS |
9719 | return default_assemble_integer (x, size, aligned_p); |
9720 | } | |
9721 | #endif | |
9722 | \f | |
cce8749e CH |
9723 | /* A finite state machine takes care of noticing whether or not instructions |
9724 | can be conditionally executed, and thus decrease execution time and code | |
9725 | size by deleting branch instructions. The fsm is controlled by | |
9726 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
9727 | ||
9728 | /* The state of the fsm controlling condition codes are: | |
9729 | 0: normal, do nothing special | |
9730 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
9731 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
9732 | 3: make instructions conditional | |
9733 | 4: make instructions conditional | |
9734 | ||
9735 | State transitions (state->state by whom under condition): | |
9736 | 0 -> 1 final_prescan_insn if the `target' is a label | |
9737 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
9738 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
9739 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
4977bab6 | 9740 | 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached |
cce8749e CH |
9741 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). |
9742 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
9743 | (the target insn is arm_target_insn). | |
9744 | ||
ff9940b0 RE |
9745 | If the jump clobbers the conditions then we use states 2 and 4. |
9746 | ||
9747 | A similar thing can be done with conditional return insns. | |
9748 | ||
cce8749e CH |
9749 | XXX In case the `target' is an unconditional branch, this conditionalising |
9750 | of the instructions always reduces code size, but not always execution | |
9751 | time. But then, I want to reduce the code size to somewhere near what | |
9752 | /bin/cc produces. */ | |
9753 | ||
cce8749e CH |
9754 | /* Returns the index of the ARM condition code string in |
9755 | `arm_condition_codes'. COMPARISON should be an rtx like | |
9756 | `(eq (...) (...))'. */ | |
9757 | ||
84ed5e79 | 9758 | static enum arm_cond_code |
cce8749e CH |
9759 | get_arm_condition_code (comparison) |
9760 | rtx comparison; | |
9761 | { | |
5165176d | 9762 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
1d6e90ac NC |
9763 | int code; |
9764 | enum rtx_code comp_code = GET_CODE (comparison); | |
5165176d RE |
9765 | |
9766 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 9767 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
9768 | XEXP (comparison, 1)); |
9769 | ||
9770 | switch (mode) | |
cce8749e | 9771 | { |
84ed5e79 RE |
9772 | case CC_DNEmode: code = ARM_NE; goto dominance; |
9773 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
9774 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
9775 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
9776 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
9777 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
9778 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
9779 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
9780 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
9781 | case CC_DLTUmode: code = ARM_CC; | |
9782 | ||
9783 | dominance: | |
9784 | if (comp_code != EQ && comp_code != NE) | |
9785 | abort (); | |
9786 | ||
9787 | if (comp_code == EQ) | |
9788 | return ARM_INVERSE_CONDITION_CODE (code); | |
9789 | return code; | |
9790 | ||
5165176d | 9791 | case CC_NOOVmode: |
84ed5e79 | 9792 | switch (comp_code) |
5165176d | 9793 | { |
84ed5e79 RE |
9794 | case NE: return ARM_NE; |
9795 | case EQ: return ARM_EQ; | |
9796 | case GE: return ARM_PL; | |
9797 | case LT: return ARM_MI; | |
5165176d RE |
9798 | default: abort (); |
9799 | } | |
9800 | ||
9801 | case CC_Zmode: | |
84ed5e79 | 9802 | switch (comp_code) |
5165176d | 9803 | { |
84ed5e79 RE |
9804 | case NE: return ARM_NE; |
9805 | case EQ: return ARM_EQ; | |
5165176d RE |
9806 | default: abort (); |
9807 | } | |
9808 | ||
9809 | case CCFPEmode: | |
e45b72c4 RE |
9810 | case CCFPmode: |
9811 | /* These encodings assume that AC=1 in the FPA system control | |
9812 | byte. This allows us to handle all cases except UNEQ and | |
9813 | LTGT. */ | |
84ed5e79 RE |
9814 | switch (comp_code) |
9815 | { | |
9816 | case GE: return ARM_GE; | |
9817 | case GT: return ARM_GT; | |
9818 | case LE: return ARM_LS; | |
9819 | case LT: return ARM_MI; | |
e45b72c4 RE |
9820 | case NE: return ARM_NE; |
9821 | case EQ: return ARM_EQ; | |
9822 | case ORDERED: return ARM_VC; | |
9823 | case UNORDERED: return ARM_VS; | |
9824 | case UNLT: return ARM_LT; | |
9825 | case UNLE: return ARM_LE; | |
9826 | case UNGT: return ARM_HI; | |
9827 | case UNGE: return ARM_PL; | |
9828 | /* UNEQ and LTGT do not have a representation. */ | |
9829 | case UNEQ: /* Fall through. */ | |
9830 | case LTGT: /* Fall through. */ | |
84ed5e79 RE |
9831 | default: abort (); |
9832 | } | |
9833 | ||
9834 | case CC_SWPmode: | |
9835 | switch (comp_code) | |
9836 | { | |
9837 | case NE: return ARM_NE; | |
9838 | case EQ: return ARM_EQ; | |
9839 | case GE: return ARM_LE; | |
9840 | case GT: return ARM_LT; | |
9841 | case LE: return ARM_GE; | |
9842 | case LT: return ARM_GT; | |
9843 | case GEU: return ARM_LS; | |
9844 | case GTU: return ARM_CC; | |
9845 | case LEU: return ARM_CS; | |
9846 | case LTU: return ARM_HI; | |
9847 | default: abort (); | |
9848 | } | |
9849 | ||
bd9c7e23 RE |
9850 | case CC_Cmode: |
9851 | switch (comp_code) | |
9852 | { | |
9853 | case LTU: return ARM_CS; | |
9854 | case GEU: return ARM_CC; | |
9855 | default: abort (); | |
9856 | } | |
9857 | ||
5165176d | 9858 | case CCmode: |
84ed5e79 | 9859 | switch (comp_code) |
5165176d | 9860 | { |
84ed5e79 RE |
9861 | case NE: return ARM_NE; |
9862 | case EQ: return ARM_EQ; | |
9863 | case GE: return ARM_GE; | |
9864 | case GT: return ARM_GT; | |
9865 | case LE: return ARM_LE; | |
9866 | case LT: return ARM_LT; | |
9867 | case GEU: return ARM_CS; | |
9868 | case GTU: return ARM_HI; | |
9869 | case LEU: return ARM_LS; | |
9870 | case LTU: return ARM_CC; | |
5165176d RE |
9871 | default: abort (); |
9872 | } | |
9873 | ||
cce8749e CH |
9874 | default: abort (); |
9875 | } | |
84ed5e79 RE |
9876 | |
9877 | abort (); | |
f3bb6135 | 9878 | } |
cce8749e CH |
9879 | |
9880 | ||
9881 | void | |
74bbc178 | 9882 | arm_final_prescan_insn (insn) |
cce8749e | 9883 | rtx insn; |
cce8749e CH |
9884 | { |
9885 | /* BODY will hold the body of INSN. */ | |
1d6e90ac | 9886 | rtx body = PATTERN (insn); |
cce8749e CH |
9887 | |
9888 | /* This will be 1 if trying to repeat the trick, and things need to be | |
9889 | reversed if it appears to fail. */ | |
9890 | int reverse = 0; | |
9891 | ||
ff9940b0 RE |
9892 | /* JUMP_CLOBBERS will be one implies that the conditions if a branch is |
9893 | taken are clobbered, even if the rtl suggests otherwise. It also | |
9894 | means that we have to grub around within the jump expression to find | |
9895 | out what the conditions are when the jump isn't taken. */ | |
9896 | int jump_clobbers = 0; | |
9897 | ||
6354dc9b | 9898 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 RE |
9899 | int seeking_return = 0; |
9900 | ||
cce8749e CH |
9901 | /* START_INSN will hold the insn from where we start looking. This is the |
9902 | first insn after the following code_label if REVERSE is true. */ | |
9903 | rtx start_insn = insn; | |
9904 | ||
9905 | /* If in state 4, check if the target branch is reached, in order to | |
9906 | change back to state 0. */ | |
9907 | if (arm_ccfsm_state == 4) | |
9908 | { | |
9909 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
9910 | { |
9911 | arm_target_insn = NULL; | |
9912 | arm_ccfsm_state = 0; | |
9913 | } | |
cce8749e CH |
9914 | return; |
9915 | } | |
9916 | ||
9917 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
9918 | unconditional branch to a label, and immediately following this branch | |
9919 | is the previous target label which is only used once, and the label this | |
9920 | branch jumps to is not too far off. */ | |
9921 | if (arm_ccfsm_state == 3) | |
9922 | { | |
9923 | if (simplejump_p (insn)) | |
9924 | { | |
9925 | start_insn = next_nonnote_insn (start_insn); | |
9926 | if (GET_CODE (start_insn) == BARRIER) | |
9927 | { | |
9928 | /* XXX Isn't this always a barrier? */ | |
9929 | start_insn = next_nonnote_insn (start_insn); | |
9930 | } | |
9931 | if (GET_CODE (start_insn) == CODE_LABEL | |
9932 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
9933 | && LABEL_NUSES (start_insn) == 1) | |
9934 | reverse = TRUE; | |
9935 | else | |
9936 | return; | |
9937 | } | |
ff9940b0 RE |
9938 | else if (GET_CODE (body) == RETURN) |
9939 | { | |
9940 | start_insn = next_nonnote_insn (start_insn); | |
9941 | if (GET_CODE (start_insn) == BARRIER) | |
9942 | start_insn = next_nonnote_insn (start_insn); | |
9943 | if (GET_CODE (start_insn) == CODE_LABEL | |
9944 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
9945 | && LABEL_NUSES (start_insn) == 1) | |
9946 | { | |
9947 | reverse = TRUE; | |
9948 | seeking_return = 1; | |
9949 | } | |
9950 | else | |
9951 | return; | |
9952 | } | |
cce8749e CH |
9953 | else |
9954 | return; | |
9955 | } | |
9956 | ||
9957 | if (arm_ccfsm_state != 0 && !reverse) | |
9958 | abort (); | |
9959 | if (GET_CODE (insn) != JUMP_INSN) | |
9960 | return; | |
9961 | ||
ddd5a7c1 | 9962 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
9963 | the jump should always come first */ |
9964 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
9965 | body = XVECEXP (body, 0, 0); | |
9966 | ||
9967 | #if 0 | |
9968 | /* If this is a conditional return then we don't want to know */ | |
9969 | if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
9970 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE | |
9971 | && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN | |
9972 | || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)) | |
9973 | return; | |
9974 | #endif | |
9975 | ||
cce8749e CH |
9976 | if (reverse |
9977 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
9978 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
9979 | { | |
bd9c7e23 RE |
9980 | int insns_skipped; |
9981 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
9982 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
9983 | int then_not_else = TRUE; | |
ff9940b0 | 9984 | rtx this_insn = start_insn, label = 0; |
cce8749e | 9985 | |
e45b72c4 RE |
9986 | /* If the jump cannot be done with one instruction, we cannot |
9987 | conditionally execute the instruction in the inverse case. */ | |
ff9940b0 | 9988 | if (get_attr_conds (insn) == CONDS_JUMP_CLOB) |
5bbe2d40 | 9989 | { |
5bbe2d40 RE |
9990 | jump_clobbers = 1; |
9991 | return; | |
9992 | } | |
ff9940b0 | 9993 | |
cce8749e CH |
9994 | /* Register the insn jumped to. */ |
9995 | if (reverse) | |
ff9940b0 RE |
9996 | { |
9997 | if (!seeking_return) | |
9998 | label = XEXP (SET_SRC (body), 0); | |
9999 | } | |
cce8749e CH |
10000 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
10001 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
10002 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
10003 | { | |
10004 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
10005 | then_not_else = FALSE; | |
10006 | } | |
ff9940b0 RE |
10007 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
10008 | seeking_return = 1; | |
10009 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
10010 | { | |
10011 | seeking_return = 1; | |
10012 | then_not_else = FALSE; | |
10013 | } | |
cce8749e CH |
10014 | else |
10015 | abort (); | |
10016 | ||
10017 | /* See how many insns this branch skips, and what kind of insns. If all | |
10018 | insns are okay, and the label or unconditional branch to the same | |
10019 | label is not too far away, succeed. */ | |
10020 | for (insns_skipped = 0; | |
b36ba79f | 10021 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
10022 | { |
10023 | rtx scanbody; | |
10024 | ||
10025 | this_insn = next_nonnote_insn (this_insn); | |
10026 | if (!this_insn) | |
10027 | break; | |
10028 | ||
cce8749e CH |
10029 | switch (GET_CODE (this_insn)) |
10030 | { | |
10031 | case CODE_LABEL: | |
10032 | /* Succeed if it is the target label, otherwise fail since | |
10033 | control falls in from somewhere else. */ | |
10034 | if (this_insn == label) | |
10035 | { | |
ff9940b0 RE |
10036 | if (jump_clobbers) |
10037 | { | |
10038 | arm_ccfsm_state = 2; | |
10039 | this_insn = next_nonnote_insn (this_insn); | |
10040 | } | |
10041 | else | |
10042 | arm_ccfsm_state = 1; | |
cce8749e CH |
10043 | succeed = TRUE; |
10044 | } | |
10045 | else | |
10046 | fail = TRUE; | |
10047 | break; | |
10048 | ||
ff9940b0 | 10049 | case BARRIER: |
cce8749e | 10050 | /* Succeed if the following insn is the target label. |
ff9940b0 RE |
10051 | Otherwise fail. |
10052 | If return insns are used then the last insn in a function | |
6354dc9b | 10053 | will be a barrier. */ |
cce8749e | 10054 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 10055 | if (this_insn && this_insn == label) |
cce8749e | 10056 | { |
ff9940b0 RE |
10057 | if (jump_clobbers) |
10058 | { | |
10059 | arm_ccfsm_state = 2; | |
10060 | this_insn = next_nonnote_insn (this_insn); | |
10061 | } | |
10062 | else | |
10063 | arm_ccfsm_state = 1; | |
cce8749e CH |
10064 | succeed = TRUE; |
10065 | } | |
10066 | else | |
10067 | fail = TRUE; | |
10068 | break; | |
10069 | ||
ff9940b0 | 10070 | case CALL_INSN: |
2b835d68 | 10071 | /* If using 32-bit addresses the cc is not preserved over |
914a3b8c | 10072 | calls. */ |
2b835d68 | 10073 | if (TARGET_APCS_32) |
bd9c7e23 RE |
10074 | { |
10075 | /* Succeed if the following insn is the target label, | |
10076 | or if the following two insns are a barrier and | |
10077 | the target label. */ | |
10078 | this_insn = next_nonnote_insn (this_insn); | |
10079 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
10080 | this_insn = next_nonnote_insn (this_insn); | |
10081 | ||
10082 | if (this_insn && this_insn == label | |
b36ba79f | 10083 | && insns_skipped < max_insns_skipped) |
bd9c7e23 RE |
10084 | { |
10085 | if (jump_clobbers) | |
10086 | { | |
10087 | arm_ccfsm_state = 2; | |
10088 | this_insn = next_nonnote_insn (this_insn); | |
10089 | } | |
10090 | else | |
10091 | arm_ccfsm_state = 1; | |
10092 | succeed = TRUE; | |
10093 | } | |
10094 | else | |
10095 | fail = TRUE; | |
10096 | } | |
ff9940b0 | 10097 | break; |
2b835d68 | 10098 | |
cce8749e CH |
10099 | case JUMP_INSN: |
10100 | /* If this is an unconditional branch to the same label, succeed. | |
10101 | If it is to another label, do nothing. If it is conditional, | |
10102 | fail. */ | |
914a3b8c | 10103 | /* XXX Probably, the tests for SET and the PC are unnecessary. */ |
cce8749e | 10104 | |
ed4c4348 | 10105 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
10106 | if (GET_CODE (scanbody) == SET |
10107 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
10108 | { |
10109 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
10110 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
10111 | { | |
10112 | arm_ccfsm_state = 2; | |
10113 | succeed = TRUE; | |
10114 | } | |
10115 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
10116 | fail = TRUE; | |
10117 | } | |
b36ba79f RE |
10118 | /* Fail if a conditional return is undesirable (eg on a |
10119 | StrongARM), but still allow this if optimizing for size. */ | |
10120 | else if (GET_CODE (scanbody) == RETURN | |
5895f793 RE |
10121 | && !use_return_insn (TRUE) |
10122 | && !optimize_size) | |
b36ba79f | 10123 | fail = TRUE; |
ff9940b0 RE |
10124 | else if (GET_CODE (scanbody) == RETURN |
10125 | && seeking_return) | |
10126 | { | |
10127 | arm_ccfsm_state = 2; | |
10128 | succeed = TRUE; | |
10129 | } | |
10130 | else if (GET_CODE (scanbody) == PARALLEL) | |
10131 | { | |
10132 | switch (get_attr_conds (this_insn)) | |
10133 | { | |
10134 | case CONDS_NOCOND: | |
10135 | break; | |
10136 | default: | |
10137 | fail = TRUE; | |
10138 | break; | |
10139 | } | |
10140 | } | |
4e67550b RE |
10141 | else |
10142 | fail = TRUE; /* Unrecognized jump (eg epilogue). */ | |
10143 | ||
cce8749e CH |
10144 | break; |
10145 | ||
10146 | case INSN: | |
ff9940b0 RE |
10147 | /* Instructions using or affecting the condition codes make it |
10148 | fail. */ | |
ed4c4348 | 10149 | scanbody = PATTERN (this_insn); |
5895f793 RE |
10150 | if (!(GET_CODE (scanbody) == SET |
10151 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 10152 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e | 10153 | fail = TRUE; |
9b6b54e2 NC |
10154 | |
10155 | /* A conditional cirrus instruction must be followed by | |
10156 | a non Cirrus instruction. However, since we | |
10157 | conditionalize instructions in this function and by | |
10158 | the time we get here we can't add instructions | |
10159 | (nops), because shorten_branches() has already been | |
10160 | called, we will disable conditionalizing Cirrus | |
10161 | instructions to be safe. */ | |
10162 | if (GET_CODE (scanbody) != USE | |
10163 | && GET_CODE (scanbody) != CLOBBER | |
f0375c66 | 10164 | && get_attr_cirrus (this_insn) != CIRRUS_NOT) |
9b6b54e2 | 10165 | fail = TRUE; |
cce8749e CH |
10166 | break; |
10167 | ||
10168 | default: | |
10169 | break; | |
10170 | } | |
10171 | } | |
10172 | if (succeed) | |
10173 | { | |
ff9940b0 | 10174 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 10175 | arm_target_label = CODE_LABEL_NUMBER (label); |
ff9940b0 RE |
10176 | else if (seeking_return || arm_ccfsm_state == 2) |
10177 | { | |
10178 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) | |
10179 | { | |
10180 | this_insn = next_nonnote_insn (this_insn); | |
10181 | if (this_insn && (GET_CODE (this_insn) == BARRIER | |
10182 | || GET_CODE (this_insn) == CODE_LABEL)) | |
10183 | abort (); | |
10184 | } | |
10185 | if (!this_insn) | |
10186 | { | |
10187 | /* Oh, dear! we ran off the end.. give up */ | |
df4ae160 | 10188 | recog (PATTERN (insn), insn, NULL); |
ff9940b0 | 10189 | arm_ccfsm_state = 0; |
abaa26e5 | 10190 | arm_target_insn = NULL; |
ff9940b0 RE |
10191 | return; |
10192 | } | |
10193 | arm_target_insn = this_insn; | |
10194 | } | |
cce8749e CH |
10195 | else |
10196 | abort (); | |
ff9940b0 RE |
10197 | if (jump_clobbers) |
10198 | { | |
10199 | if (reverse) | |
10200 | abort (); | |
10201 | arm_current_cc = | |
10202 | get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), | |
10203 | 0), 0), 1)); | |
10204 | if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) | |
10205 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
10206 | if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) | |
10207 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
10208 | } | |
10209 | else | |
10210 | { | |
10211 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
10212 | what it was. */ | |
10213 | if (!reverse) | |
10214 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), | |
10215 | 0)); | |
10216 | } | |
cce8749e | 10217 | |
cce8749e CH |
10218 | if (reverse || then_not_else) |
10219 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
10220 | } | |
d5b7b3ae | 10221 | |
1ccbefce | 10222 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 10223 | destroy this array, but final.c assumes that it remains intact |
ddd5a7c1 | 10224 | across this call; since the insn has been recognized already we |
b020fd92 | 10225 | call recog direct). */ |
df4ae160 | 10226 | recog (PATTERN (insn), insn, NULL); |
cce8749e | 10227 | } |
f3bb6135 | 10228 | } |
cce8749e | 10229 | |
4b02997f NC |
10230 | /* Returns true if REGNO is a valid register |
10231 | for holding a quantity of tyoe MODE. */ | |
10232 | ||
10233 | int | |
10234 | arm_hard_regno_mode_ok (regno, mode) | |
10235 | unsigned int regno; | |
10236 | enum machine_mode mode; | |
10237 | { | |
10238 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
10239 | return regno == CC_REGNUM; | |
10240 | ||
10241 | if (TARGET_THUMB) | |
10242 | /* For the Thumb we only allow values bigger than SImode in | |
10243 | registers 0 - 6, so that there is always a second low | |
10244 | register available to hold the upper part of the value. | |
10245 | We probably we ought to ensure that the register is the | |
10246 | start of an even numbered register pair. */ | |
e9d7b180 | 10247 | return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); |
4b02997f | 10248 | |
9b6b54e2 NC |
10249 | if (IS_CIRRUS_REGNUM (regno)) |
10250 | /* We have outlawed SI values in Cirrus registers because they | |
10251 | reside in the lower 32 bits, but SF values reside in the | |
10252 | upper 32 bits. This causes gcc all sorts of grief. We can't | |
10253 | even split the registers into pairs because Cirrus SI values | |
10254 | get sign extended to 64bits-- aldyh. */ | |
10255 | return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); | |
10256 | ||
4b02997f | 10257 | if (regno <= LAST_ARM_REGNUM) |
3cb66fd7 NC |
10258 | /* We allow any value to be stored in the general regisetrs. */ |
10259 | return 1; | |
4b02997f NC |
10260 | |
10261 | if ( regno == FRAME_POINTER_REGNUM | |
10262 | || regno == ARG_POINTER_REGNUM) | |
10263 | /* We only allow integers in the fake hard registers. */ | |
10264 | return GET_MODE_CLASS (mode) == MODE_INT; | |
10265 | ||
3b684012 | 10266 | /* The only registers left are the FPA registers |
4b02997f NC |
10267 | which we only allow to hold FP values. */ |
10268 | return GET_MODE_CLASS (mode) == MODE_FLOAT | |
10269 | && regno >= FIRST_ARM_FP_REGNUM | |
10270 | && regno <= LAST_ARM_FP_REGNUM; | |
10271 | } | |
10272 | ||
d5b7b3ae RE |
10273 | int |
10274 | arm_regno_class (regno) | |
10275 | int regno; | |
10276 | { | |
10277 | if (TARGET_THUMB) | |
10278 | { | |
10279 | if (regno == STACK_POINTER_REGNUM) | |
10280 | return STACK_REG; | |
10281 | if (regno == CC_REGNUM) | |
10282 | return CC_REG; | |
10283 | if (regno < 8) | |
10284 | return LO_REGS; | |
10285 | return HI_REGS; | |
10286 | } | |
10287 | ||
10288 | if ( regno <= LAST_ARM_REGNUM | |
10289 | || regno == FRAME_POINTER_REGNUM | |
10290 | || regno == ARG_POINTER_REGNUM) | |
10291 | return GENERAL_REGS; | |
10292 | ||
10293 | if (regno == CC_REGNUM) | |
10294 | return NO_REGS; | |
10295 | ||
9b6b54e2 NC |
10296 | if (IS_CIRRUS_REGNUM (regno)) |
10297 | return CIRRUS_REGS; | |
10298 | ||
3b684012 | 10299 | return FPA_REGS; |
d5b7b3ae RE |
10300 | } |
10301 | ||
10302 | /* Handle a special case when computing the offset | |
10303 | of an argument from the frame pointer. */ | |
1d6e90ac | 10304 | |
d5b7b3ae RE |
10305 | int |
10306 | arm_debugger_arg_offset (value, addr) | |
10307 | int value; | |
10308 | rtx addr; | |
10309 | { | |
10310 | rtx insn; | |
10311 | ||
10312 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
10313 | if (value != 0) | |
10314 | return 0; | |
10315 | ||
10316 | /* We can only cope with the case where the address is held in a register. */ | |
10317 | if (GET_CODE (addr) != REG) | |
10318 | return 0; | |
10319 | ||
10320 | /* If we are using the frame pointer to point at the argument, then | |
10321 | an offset of 0 is correct. */ | |
cd2b33d0 | 10322 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae RE |
10323 | return 0; |
10324 | ||
10325 | /* If we are using the stack pointer to point at the | |
10326 | argument, then an offset of 0 is correct. */ | |
5895f793 | 10327 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
10328 | && REGNO (addr) == SP_REGNUM) |
10329 | return 0; | |
10330 | ||
10331 | /* Oh dear. The argument is pointed to by a register rather | |
10332 | than being held in a register, or being stored at a known | |
10333 | offset from the frame pointer. Since GDB only understands | |
10334 | those two kinds of argument we must translate the address | |
10335 | held in the register into an offset from the frame pointer. | |
10336 | We do this by searching through the insns for the function | |
10337 | looking to see where this register gets its value. If the | |
4912a07c | 10338 | register is initialized from the frame pointer plus an offset |
d5b7b3ae RE |
10339 | then we are in luck and we can continue, otherwise we give up. |
10340 | ||
10341 | This code is exercised by producing debugging information | |
10342 | for a function with arguments like this: | |
10343 | ||
10344 | double func (double a, double b, int c, double d) {return d;} | |
10345 | ||
10346 | Without this code the stab for parameter 'd' will be set to | |
10347 | an offset of 0 from the frame pointer, rather than 8. */ | |
10348 | ||
10349 | /* The if() statement says: | |
10350 | ||
10351 | If the insn is a normal instruction | |
10352 | and if the insn is setting the value in a register | |
10353 | and if the register being set is the register holding the address of the argument | |
10354 | and if the address is computing by an addition | |
10355 | that involves adding to a register | |
10356 | which is the frame pointer | |
10357 | a constant integer | |
10358 | ||
10359 | then... */ | |
10360 | ||
10361 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
10362 | { | |
10363 | if ( GET_CODE (insn) == INSN | |
10364 | && GET_CODE (PATTERN (insn)) == SET | |
10365 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
10366 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
10367 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 10368 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
10369 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
10370 | ) | |
10371 | { | |
10372 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
10373 | ||
10374 | break; | |
10375 | } | |
10376 | } | |
10377 | ||
10378 | if (value == 0) | |
10379 | { | |
10380 | debug_rtx (addr); | |
c725bd79 | 10381 | warning ("unable to compute real location of stacked parameter"); |
d5b7b3ae RE |
10382 | value = 8; /* XXX magic hack */ |
10383 | } | |
10384 | ||
10385 | return value; | |
10386 | } | |
d5b7b3ae RE |
10387 | \f |
10388 | /* Recursively search through all of the blocks in a function | |
10389 | checking to see if any of the variables created in that | |
10390 | function match the RTX called 'orig'. If they do then | |
10391 | replace them with the RTX called 'new'. */ | |
10392 | ||
10393 | static void | |
10394 | replace_symbols_in_block (block, orig, new) | |
10395 | tree block; | |
10396 | rtx orig; | |
10397 | rtx new; | |
10398 | { | |
10399 | for (; block; block = BLOCK_CHAIN (block)) | |
10400 | { | |
10401 | tree sym; | |
10402 | ||
5895f793 | 10403 | if (!TREE_USED (block)) |
d5b7b3ae RE |
10404 | continue; |
10405 | ||
10406 | for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym)) | |
10407 | { | |
10408 | if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL) | |
10409 | || DECL_IGNORED_P (sym) | |
10410 | || TREE_CODE (sym) != VAR_DECL | |
10411 | || DECL_EXTERNAL (sym) | |
5895f793 | 10412 | || !rtx_equal_p (DECL_RTL (sym), orig) |
d5b7b3ae RE |
10413 | ) |
10414 | continue; | |
10415 | ||
7b8b8ade | 10416 | SET_DECL_RTL (sym, new); |
d5b7b3ae RE |
10417 | } |
10418 | ||
10419 | replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new); | |
10420 | } | |
10421 | } | |
10422 | ||
1d6e90ac NC |
10423 | /* Return the number (counting from 0) of |
10424 | the least significant set bit in MASK. */ | |
10425 | ||
d5b7b3ae RE |
10426 | #ifdef __GNUC__ |
10427 | inline | |
10428 | #endif | |
10429 | static int | |
10430 | number_of_first_bit_set (mask) | |
10431 | int mask; | |
10432 | { | |
10433 | int bit; | |
10434 | ||
10435 | for (bit = 0; | |
10436 | (mask & (1 << bit)) == 0; | |
5895f793 | 10437 | ++bit) |
d5b7b3ae RE |
10438 | continue; |
10439 | ||
10440 | return bit; | |
10441 | } | |
10442 | ||
10443 | /* Generate code to return from a thumb function. | |
10444 | If 'reg_containing_return_addr' is -1, then the return address is | |
10445 | actually on the stack, at the stack pointer. */ | |
10446 | static void | |
10447 | thumb_exit (f, reg_containing_return_addr, eh_ofs) | |
10448 | FILE * f; | |
10449 | int reg_containing_return_addr; | |
10450 | rtx eh_ofs; | |
10451 | { | |
10452 | unsigned regs_available_for_popping; | |
10453 | unsigned regs_to_pop; | |
10454 | int pops_needed; | |
10455 | unsigned available; | |
10456 | unsigned required; | |
10457 | int mode; | |
10458 | int size; | |
10459 | int restore_a4 = FALSE; | |
10460 | ||
10461 | /* Compute the registers we need to pop. */ | |
10462 | regs_to_pop = 0; | |
10463 | pops_needed = 0; | |
10464 | ||
10465 | /* There is an assumption here, that if eh_ofs is not NULL, the | |
10466 | normal return address will have been pushed. */ | |
10467 | if (reg_containing_return_addr == -1 || eh_ofs) | |
10468 | { | |
10469 | /* When we are generating a return for __builtin_eh_return, | |
10470 | reg_containing_return_addr must specify the return regno. */ | |
10471 | if (eh_ofs && reg_containing_return_addr == -1) | |
10472 | abort (); | |
10473 | ||
10474 | regs_to_pop |= 1 << LR_REGNUM; | |
5895f793 | 10475 | ++pops_needed; |
d5b7b3ae RE |
10476 | } |
10477 | ||
10478 | if (TARGET_BACKTRACE) | |
10479 | { | |
10480 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
10481 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
10482 | pops_needed += 2; | |
10483 | } | |
10484 | ||
10485 | /* If there is nothing to pop then just emit the BX instruction and | |
10486 | return. */ | |
10487 | if (pops_needed == 0) | |
10488 | { | |
10489 | if (eh_ofs) | |
10490 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
10491 | ||
10492 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
10493 | return; | |
10494 | } | |
10495 | /* Otherwise if we are not supporting interworking and we have not created | |
10496 | a backtrace structure and the function was not entered in ARM mode then | |
10497 | just pop the return address straight into the PC. */ | |
5895f793 RE |
10498 | else if (!TARGET_INTERWORK |
10499 | && !TARGET_BACKTRACE | |
10500 | && !is_called_in_ARM_mode (current_function_decl)) | |
d5b7b3ae RE |
10501 | { |
10502 | if (eh_ofs) | |
10503 | { | |
10504 | asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM); | |
10505 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
10506 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
10507 | } | |
10508 | else | |
10509 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); | |
10510 | ||
10511 | return; | |
10512 | } | |
10513 | ||
10514 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
10515 | regs_available_for_popping = 0; | |
10516 | ||
10517 | /* If returning via __builtin_eh_return, the bottom three registers | |
10518 | all contain information needed for the return. */ | |
10519 | if (eh_ofs) | |
10520 | size = 12; | |
10521 | else | |
10522 | { | |
10523 | #ifdef RTX_CODE | |
10524 | /* If we can deduce the registers used from the function's | |
10525 | return value. This is more reliable that examining | |
10526 | regs_ever_live[] because that will be set if the register is | |
10527 | ever used in the function, not just if the register is used | |
10528 | to hold a return value. */ | |
10529 | ||
10530 | if (current_function_return_rtx != 0) | |
10531 | mode = GET_MODE (current_function_return_rtx); | |
10532 | else | |
10533 | #endif | |
10534 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
10535 | ||
10536 | size = GET_MODE_SIZE (mode); | |
10537 | ||
10538 | if (size == 0) | |
10539 | { | |
10540 | /* In a void function we can use any argument register. | |
10541 | In a function that returns a structure on the stack | |
10542 | we can use the second and third argument registers. */ | |
10543 | if (mode == VOIDmode) | |
10544 | regs_available_for_popping = | |
10545 | (1 << ARG_REGISTER (1)) | |
10546 | | (1 << ARG_REGISTER (2)) | |
10547 | | (1 << ARG_REGISTER (3)); | |
10548 | else | |
10549 | regs_available_for_popping = | |
10550 | (1 << ARG_REGISTER (2)) | |
10551 | | (1 << ARG_REGISTER (3)); | |
10552 | } | |
10553 | else if (size <= 4) | |
10554 | regs_available_for_popping = | |
10555 | (1 << ARG_REGISTER (2)) | |
10556 | | (1 << ARG_REGISTER (3)); | |
10557 | else if (size <= 8) | |
10558 | regs_available_for_popping = | |
10559 | (1 << ARG_REGISTER (3)); | |
10560 | } | |
10561 | ||
10562 | /* Match registers to be popped with registers into which we pop them. */ | |
10563 | for (available = regs_available_for_popping, | |
10564 | required = regs_to_pop; | |
10565 | required != 0 && available != 0; | |
10566 | available &= ~(available & - available), | |
10567 | required &= ~(required & - required)) | |
10568 | -- pops_needed; | |
10569 | ||
10570 | /* If we have any popping registers left over, remove them. */ | |
10571 | if (available > 0) | |
5895f793 | 10572 | regs_available_for_popping &= ~available; |
d5b7b3ae RE |
10573 | |
10574 | /* Otherwise if we need another popping register we can use | |
10575 | the fourth argument register. */ | |
10576 | else if (pops_needed) | |
10577 | { | |
10578 | /* If we have not found any free argument registers and | |
10579 | reg a4 contains the return address, we must move it. */ | |
10580 | if (regs_available_for_popping == 0 | |
10581 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
10582 | { | |
10583 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
10584 | reg_containing_return_addr = LR_REGNUM; | |
10585 | } | |
10586 | else if (size > 12) | |
10587 | { | |
10588 | /* Register a4 is being used to hold part of the return value, | |
10589 | but we have dire need of a free, low register. */ | |
10590 | restore_a4 = TRUE; | |
10591 | ||
10592 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); | |
10593 | } | |
10594 | ||
10595 | if (reg_containing_return_addr != LAST_ARG_REGNUM) | |
10596 | { | |
10597 | /* The fourth argument register is available. */ | |
10598 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
10599 | ||
5895f793 | 10600 | --pops_needed; |
d5b7b3ae RE |
10601 | } |
10602 | } | |
10603 | ||
10604 | /* Pop as many registers as we can. */ | |
10605 | thumb_pushpop (f, regs_available_for_popping, FALSE); | |
10606 | ||
10607 | /* Process the registers we popped. */ | |
10608 | if (reg_containing_return_addr == -1) | |
10609 | { | |
10610 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 10611 | regs_to_pop &= ~(1 << LR_REGNUM); |
d5b7b3ae RE |
10612 | |
10613 | reg_containing_return_addr = | |
10614 | number_of_first_bit_set (regs_available_for_popping); | |
10615 | ||
10616 | /* Remove this register for the mask of available registers, so that | |
6bc82793 | 10617 | the return address will not be corrupted by further pops. */ |
5895f793 | 10618 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
10619 | } |
10620 | ||
10621 | /* If we popped other registers then handle them here. */ | |
10622 | if (regs_available_for_popping) | |
10623 | { | |
10624 | int frame_pointer; | |
10625 | ||
10626 | /* Work out which register currently contains the frame pointer. */ | |
10627 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
10628 | ||
10629 | /* Move it into the correct place. */ | |
10630 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
10631 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
10632 | ||
10633 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
10634 | regs_available_for_popping &= ~(1 << frame_pointer); |
10635 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
d5b7b3ae RE |
10636 | |
10637 | if (regs_available_for_popping) | |
10638 | { | |
10639 | int stack_pointer; | |
10640 | ||
10641 | /* We popped the stack pointer as well, | |
10642 | find the register that contains it. */ | |
10643 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
10644 | ||
10645 | /* Move it into the stack register. */ | |
10646 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
10647 | ||
10648 | /* At this point we have popped all necessary registers, so | |
10649 | do not worry about restoring regs_available_for_popping | |
10650 | to its correct value: | |
10651 | ||
10652 | assert (pops_needed == 0) | |
10653 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
10654 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
10655 | } | |
10656 | else | |
10657 | { | |
10658 | /* Since we have just move the popped value into the frame | |
10659 | pointer, the popping register is available for reuse, and | |
10660 | we know that we still have the stack pointer left to pop. */ | |
10661 | regs_available_for_popping |= (1 << frame_pointer); | |
10662 | } | |
10663 | } | |
10664 | ||
10665 | /* If we still have registers left on the stack, but we no longer have | |
10666 | any registers into which we can pop them, then we must move the return | |
10667 | address into the link register and make available the register that | |
10668 | contained it. */ | |
10669 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
10670 | { | |
10671 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
10672 | ||
10673 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, | |
10674 | reg_containing_return_addr); | |
10675 | ||
10676 | reg_containing_return_addr = LR_REGNUM; | |
10677 | } | |
10678 | ||
10679 | /* If we have registers left on the stack then pop some more. | |
10680 | We know that at most we will want to pop FP and SP. */ | |
10681 | if (pops_needed > 0) | |
10682 | { | |
10683 | int popped_into; | |
10684 | int move_to; | |
10685 | ||
10686 | thumb_pushpop (f, regs_available_for_popping, FALSE); | |
10687 | ||
10688 | /* We have popped either FP or SP. | |
10689 | Move whichever one it is into the correct register. */ | |
10690 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
10691 | move_to = number_of_first_bit_set (regs_to_pop); | |
10692 | ||
10693 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
10694 | ||
5895f793 | 10695 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 10696 | |
5895f793 | 10697 | --pops_needed; |
d5b7b3ae RE |
10698 | } |
10699 | ||
10700 | /* If we still have not popped everything then we must have only | |
10701 | had one register available to us and we are now popping the SP. */ | |
10702 | if (pops_needed > 0) | |
10703 | { | |
10704 | int popped_into; | |
10705 | ||
10706 | thumb_pushpop (f, regs_available_for_popping, FALSE); | |
10707 | ||
10708 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
10709 | ||
10710 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
10711 | /* | |
10712 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
10713 | assert (pops_needed == 1) | |
10714 | */ | |
10715 | } | |
10716 | ||
10717 | /* If necessary restore the a4 register. */ | |
10718 | if (restore_a4) | |
10719 | { | |
10720 | if (reg_containing_return_addr != LR_REGNUM) | |
10721 | { | |
10722 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
10723 | reg_containing_return_addr = LR_REGNUM; | |
10724 | } | |
10725 | ||
10726 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); | |
10727 | } | |
10728 | ||
10729 | if (eh_ofs) | |
10730 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
10731 | ||
10732 | /* Return to caller. */ | |
10733 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
10734 | } | |
10735 | ||
10736 | /* Emit code to push or pop registers to or from the stack. */ | |
1d6e90ac | 10737 | |
d5b7b3ae RE |
10738 | static void |
10739 | thumb_pushpop (f, mask, push) | |
10740 | FILE * f; | |
10741 | int mask; | |
10742 | int push; | |
10743 | { | |
10744 | int regno; | |
10745 | int lo_mask = mask & 0xFF; | |
10746 | ||
5895f793 | 10747 | if (lo_mask == 0 && !push && (mask & (1 << 15))) |
d5b7b3ae RE |
10748 | { |
10749 | /* Special case. Do not generate a POP PC statement here, do it in | |
10750 | thumb_exit() */ | |
10751 | thumb_exit (f, -1, NULL_RTX); | |
10752 | return; | |
10753 | } | |
10754 | ||
10755 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); | |
10756 | ||
10757 | /* Look at the low registers first. */ | |
5895f793 | 10758 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) |
d5b7b3ae RE |
10759 | { |
10760 | if (lo_mask & 1) | |
10761 | { | |
10762 | asm_fprintf (f, "%r", regno); | |
10763 | ||
10764 | if ((lo_mask & ~1) != 0) | |
10765 | fprintf (f, ", "); | |
10766 | } | |
10767 | } | |
10768 | ||
10769 | if (push && (mask & (1 << LR_REGNUM))) | |
10770 | { | |
10771 | /* Catch pushing the LR. */ | |
10772 | if (mask & 0xFF) | |
10773 | fprintf (f, ", "); | |
10774 | ||
10775 | asm_fprintf (f, "%r", LR_REGNUM); | |
10776 | } | |
10777 | else if (!push && (mask & (1 << PC_REGNUM))) | |
10778 | { | |
10779 | /* Catch popping the PC. */ | |
10780 | if (TARGET_INTERWORK || TARGET_BACKTRACE) | |
10781 | { | |
10782 | /* The PC is never poped directly, instead | |
10783 | it is popped into r3 and then BX is used. */ | |
10784 | fprintf (f, "}\n"); | |
10785 | ||
10786 | thumb_exit (f, -1, NULL_RTX); | |
10787 | ||
10788 | return; | |
10789 | } | |
10790 | else | |
10791 | { | |
10792 | if (mask & 0xFF) | |
10793 | fprintf (f, ", "); | |
10794 | ||
10795 | asm_fprintf (f, "%r", PC_REGNUM); | |
10796 | } | |
10797 | } | |
10798 | ||
10799 | fprintf (f, "}\n"); | |
10800 | } | |
10801 | \f | |
10802 | void | |
10803 | thumb_final_prescan_insn (insn) | |
10804 | rtx insn; | |
10805 | { | |
d5b7b3ae | 10806 | if (flag_print_asm_name) |
9d98a694 AO |
10807 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
10808 | INSN_ADDRESSES (INSN_UID (insn))); | |
d5b7b3ae RE |
10809 | } |
10810 | ||
10811 | int | |
10812 | thumb_shiftable_const (val) | |
10813 | unsigned HOST_WIDE_INT val; | |
10814 | { | |
10815 | unsigned HOST_WIDE_INT mask = 0xff; | |
10816 | int i; | |
10817 | ||
10818 | if (val == 0) /* XXX */ | |
10819 | return 0; | |
10820 | ||
10821 | for (i = 0; i < 25; i++) | |
10822 | if ((val & (mask << i)) == val) | |
10823 | return 1; | |
10824 | ||
10825 | return 0; | |
10826 | } | |
10827 | ||
825dda42 | 10828 | /* Returns nonzero if the current function contains, |
d5b7b3ae | 10829 | or might contain a far jump. */ |
1d6e90ac | 10830 | |
d5b7b3ae | 10831 | int |
ab2877a3 KG |
10832 | thumb_far_jump_used_p (in_prologue) |
10833 | int in_prologue; | |
d5b7b3ae RE |
10834 | { |
10835 | rtx insn; | |
10836 | ||
10837 | /* This test is only important for leaf functions. */ | |
5895f793 | 10838 | /* assert (!leaf_function_p ()); */ |
d5b7b3ae RE |
10839 | |
10840 | /* If we have already decided that far jumps may be used, | |
10841 | do not bother checking again, and always return true even if | |
10842 | it turns out that they are not being used. Once we have made | |
10843 | the decision that far jumps are present (and that hence the link | |
10844 | register will be pushed onto the stack) we cannot go back on it. */ | |
10845 | if (cfun->machine->far_jump_used) | |
10846 | return 1; | |
10847 | ||
10848 | /* If this function is not being called from the prologue/epilogue | |
10849 | generation code then it must be being called from the | |
10850 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5895f793 | 10851 | if (!in_prologue) |
d5b7b3ae RE |
10852 | { |
10853 | /* In this case we know that we are being asked about the elimination | |
10854 | of the arg pointer register. If that register is not being used, | |
10855 | then there are no arguments on the stack, and we do not have to | |
10856 | worry that a far jump might force the prologue to push the link | |
10857 | register, changing the stack offsets. In this case we can just | |
10858 | return false, since the presence of far jumps in the function will | |
10859 | not affect stack offsets. | |
10860 | ||
10861 | If the arg pointer is live (or if it was live, but has now been | |
10862 | eliminated and so set to dead) then we do have to test to see if | |
10863 | the function might contain a far jump. This test can lead to some | |
10864 | false negatives, since before reload is completed, then length of | |
10865 | branch instructions is not known, so gcc defaults to returning their | |
10866 | longest length, which in turn sets the far jump attribute to true. | |
10867 | ||
10868 | A false negative will not result in bad code being generated, but it | |
10869 | will result in a needless push and pop of the link register. We | |
10870 | hope that this does not occur too often. */ | |
10871 | if (regs_ever_live [ARG_POINTER_REGNUM]) | |
10872 | cfun->machine->arg_pointer_live = 1; | |
5895f793 | 10873 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
10874 | return 0; |
10875 | } | |
10876 | ||
10877 | /* Check to see if the function contains a branch | |
10878 | insn with the far jump attribute set. */ | |
10879 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
10880 | { | |
10881 | if (GET_CODE (insn) == JUMP_INSN | |
10882 | /* Ignore tablejump patterns. */ | |
10883 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
10884 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
10885 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
10886 | ) | |
10887 | { | |
10888 | /* Record the fact that we have decied that | |
10889 | the function does use far jumps. */ | |
10890 | cfun->machine->far_jump_used = 1; | |
10891 | return 1; | |
10892 | } | |
10893 | } | |
10894 | ||
10895 | return 0; | |
10896 | } | |
10897 | ||
825dda42 | 10898 | /* Return nonzero if FUNC must be entered in ARM mode. */ |
1d6e90ac | 10899 | |
d5b7b3ae RE |
10900 | int |
10901 | is_called_in_ARM_mode (func) | |
10902 | tree func; | |
10903 | { | |
10904 | if (TREE_CODE (func) != FUNCTION_DECL) | |
10905 | abort (); | |
10906 | ||
10907 | /* Ignore the problem about functions whoes address is taken. */ | |
10908 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) | |
10909 | return TRUE; | |
10910 | ||
10911 | #ifdef ARM_PE | |
91d231cb | 10912 | return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; |
d5b7b3ae RE |
10913 | #else |
10914 | return FALSE; | |
10915 | #endif | |
10916 | } | |
10917 | ||
10918 | /* The bits which aren't usefully expanded as rtl. */ | |
400500c4 | 10919 | |
cd2b33d0 | 10920 | const char * |
d5b7b3ae RE |
10921 | thumb_unexpanded_epilogue () |
10922 | { | |
10923 | int regno; | |
10924 | int live_regs_mask = 0; | |
10925 | int high_regs_pushed = 0; | |
10926 | int leaf_function = leaf_function_p (); | |
10927 | int had_to_push_lr; | |
10928 | rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; | |
10929 | ||
10930 | if (return_used_this_function) | |
10931 | return ""; | |
10932 | ||
58e60158 AN |
10933 | if (IS_NAKED (arm_current_func_type ())) |
10934 | return ""; | |
10935 | ||
d5b7b3ae | 10936 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) |
aeaf4d25 | 10937 | if (THUMB_REG_PUSHED_P (regno)) |
d5b7b3ae RE |
10938 | live_regs_mask |= 1 << regno; |
10939 | ||
10940 | for (regno = 8; regno < 13; regno++) | |
aeaf4d25 AN |
10941 | if (THUMB_REG_PUSHED_P (regno)) |
10942 | high_regs_pushed++; | |
d5b7b3ae RE |
10943 | |
10944 | /* The prolog may have pushed some high registers to use as | |
10945 | work registers. eg the testuite file: | |
10946 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c | |
10947 | compiles to produce: | |
10948 | push {r4, r5, r6, r7, lr} | |
10949 | mov r7, r9 | |
10950 | mov r6, r8 | |
10951 | push {r6, r7} | |
10952 | as part of the prolog. We have to undo that pushing here. */ | |
10953 | ||
10954 | if (high_regs_pushed) | |
10955 | { | |
10956 | int mask = live_regs_mask; | |
10957 | int next_hi_reg; | |
10958 | int size; | |
10959 | int mode; | |
10960 | ||
10961 | #ifdef RTX_CODE | |
10962 | /* If we can deduce the registers used from the function's return value. | |
10963 | This is more reliable that examining regs_ever_live[] because that | |
10964 | will be set if the register is ever used in the function, not just if | |
10965 | the register is used to hold a return value. */ | |
10966 | ||
10967 | if (current_function_return_rtx != 0) | |
10968 | mode = GET_MODE (current_function_return_rtx); | |
10969 | else | |
10970 | #endif | |
10971 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
10972 | ||
10973 | size = GET_MODE_SIZE (mode); | |
10974 | ||
10975 | /* Unless we are returning a type of size > 12 register r3 is | |
10976 | available. */ | |
10977 | if (size < 13) | |
10978 | mask |= 1 << 3; | |
10979 | ||
10980 | if (mask == 0) | |
10981 | /* Oh dear! We have no low registers into which we can pop | |
10982 | high registers! */ | |
400500c4 RK |
10983 | internal_error |
10984 | ("no low registers available for popping high registers"); | |
d5b7b3ae RE |
10985 | |
10986 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) | |
aeaf4d25 | 10987 | if (THUMB_REG_PUSHED_P (next_hi_reg)) |
d5b7b3ae RE |
10988 | break; |
10989 | ||
10990 | while (high_regs_pushed) | |
10991 | { | |
10992 | /* Find lo register(s) into which the high register(s) can | |
10993 | be popped. */ | |
10994 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
10995 | { | |
10996 | if (mask & (1 << regno)) | |
10997 | high_regs_pushed--; | |
10998 | if (high_regs_pushed == 0) | |
10999 | break; | |
11000 | } | |
11001 | ||
11002 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
11003 | ||
11004 | /* Pop the values into the low register(s). */ | |
11005 | thumb_pushpop (asm_out_file, mask, 0); | |
11006 | ||
11007 | /* Move the value(s) into the high registers. */ | |
11008 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
11009 | { | |
11010 | if (mask & (1 << regno)) | |
11011 | { | |
11012 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
11013 | regno); | |
11014 | ||
11015 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) | |
aeaf4d25 | 11016 | if (THUMB_REG_PUSHED_P (next_hi_reg)) |
d5b7b3ae RE |
11017 | break; |
11018 | } | |
11019 | } | |
11020 | } | |
11021 | } | |
11022 | ||
5895f793 | 11023 | had_to_push_lr = (live_regs_mask || !leaf_function |
d5b7b3ae RE |
11024 | || thumb_far_jump_used_p (1)); |
11025 | ||
11026 | if (TARGET_BACKTRACE | |
11027 | && ((live_regs_mask & 0xFF) == 0) | |
11028 | && regs_ever_live [LAST_ARG_REGNUM] != 0) | |
11029 | { | |
11030 | /* The stack backtrace structure creation code had to | |
11031 | push R7 in order to get a work register, so we pop | |
11032 | it now. */ | |
11033 | live_regs_mask |= (1 << LAST_LO_REGNUM); | |
11034 | } | |
11035 | ||
11036 | if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE) | |
11037 | { | |
11038 | if (had_to_push_lr | |
5895f793 RE |
11039 | && !is_called_in_ARM_mode (current_function_decl) |
11040 | && !eh_ofs) | |
d5b7b3ae RE |
11041 | live_regs_mask |= 1 << PC_REGNUM; |
11042 | ||
11043 | /* Either no argument registers were pushed or a backtrace | |
11044 | structure was created which includes an adjusted stack | |
11045 | pointer, so just pop everything. */ | |
11046 | if (live_regs_mask) | |
11047 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE); | |
11048 | ||
11049 | if (eh_ofs) | |
11050 | thumb_exit (asm_out_file, 2, eh_ofs); | |
11051 | /* We have either just popped the return address into the | |
11052 | PC or it is was kept in LR for the entire function or | |
11053 | it is still on the stack because we do not want to | |
11054 | return by doing a pop {pc}. */ | |
11055 | else if ((live_regs_mask & (1 << PC_REGNUM)) == 0) | |
11056 | thumb_exit (asm_out_file, | |
11057 | (had_to_push_lr | |
11058 | && is_called_in_ARM_mode (current_function_decl)) ? | |
11059 | -1 : LR_REGNUM, NULL_RTX); | |
11060 | } | |
11061 | else | |
11062 | { | |
11063 | /* Pop everything but the return address. */ | |
5895f793 | 11064 | live_regs_mask &= ~(1 << PC_REGNUM); |
d5b7b3ae RE |
11065 | |
11066 | if (live_regs_mask) | |
11067 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE); | |
11068 | ||
11069 | if (had_to_push_lr) | |
11070 | /* Get the return address into a temporary register. */ | |
11071 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0); | |
11072 | ||
11073 | /* Remove the argument registers that were pushed onto the stack. */ | |
11074 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
11075 | SP_REGNUM, SP_REGNUM, | |
11076 | current_function_pretend_args_size); | |
11077 | ||
11078 | if (eh_ofs) | |
11079 | thumb_exit (asm_out_file, 2, eh_ofs); | |
11080 | else | |
11081 | thumb_exit (asm_out_file, | |
11082 | had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX); | |
11083 | } | |
11084 | ||
11085 | return ""; | |
11086 | } | |
11087 | ||
11088 | /* Functions to save and restore machine-specific function data. */ | |
11089 | ||
e2500fed GK |
11090 | static struct machine_function * |
11091 | arm_init_machine_status () | |
d5b7b3ae | 11092 | { |
e2500fed GK |
11093 | struct machine_function *machine; |
11094 | machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); | |
6d3d9133 | 11095 | |
e2500fed GK |
11096 | #if ARM_FT_UNKNOWN != 0 |
11097 | machine->func_type = ARM_FT_UNKNOWN; | |
6d3d9133 | 11098 | #endif |
e2500fed | 11099 | return machine; |
f7a80099 NC |
11100 | } |
11101 | ||
d5b7b3ae RE |
11102 | /* Return an RTX indicating where the return address to the |
11103 | calling function can be found. */ | |
1d6e90ac | 11104 | |
d5b7b3ae RE |
11105 | rtx |
11106 | arm_return_addr (count, frame) | |
11107 | int count; | |
11108 | rtx frame ATTRIBUTE_UNUSED; | |
11109 | { | |
d5b7b3ae RE |
11110 | if (count != 0) |
11111 | return NULL_RTX; | |
11112 | ||
9e2f7ec7 DD |
11113 | if (TARGET_APCS_32) |
11114 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); | |
11115 | else | |
d5b7b3ae | 11116 | { |
9e2f7ec7 | 11117 | rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM), |
d5b7b3ae | 11118 | GEN_INT (RETURN_ADDR_MASK26)); |
9e2f7ec7 | 11119 | return get_func_hard_reg_initial_val (cfun, lr); |
d5b7b3ae | 11120 | } |
d5b7b3ae RE |
11121 | } |
11122 | ||
11123 | /* Do anything needed before RTL is emitted for each function. */ | |
1d6e90ac | 11124 | |
d5b7b3ae RE |
11125 | void |
11126 | arm_init_expanders () | |
11127 | { | |
11128 | /* Arrange to initialize and mark the machine per-function status. */ | |
11129 | init_machine_status = arm_init_machine_status; | |
d5b7b3ae RE |
11130 | } |
11131 | ||
0977774b JT |
11132 | HOST_WIDE_INT |
11133 | thumb_get_frame_size () | |
11134 | { | |
11135 | int regno; | |
11136 | ||
0c2ca901 | 11137 | int base_size = ROUND_UP_WORD (get_frame_size ()); |
0977774b JT |
11138 | int count_regs = 0; |
11139 | int entry_size = 0; | |
c231c91e | 11140 | int leaf; |
0977774b JT |
11141 | |
11142 | if (! TARGET_THUMB) | |
11143 | abort (); | |
11144 | ||
11145 | if (! TARGET_ATPCS) | |
11146 | return base_size; | |
11147 | ||
11148 | /* We need to know if we are a leaf function. Unfortunately, it | |
11149 | is possible to be called after start_sequence has been called, | |
11150 | which causes get_insns to return the insns for the sequence, | |
11151 | not the function, which will cause leaf_function_p to return | |
11152 | the incorrect result. | |
11153 | ||
11154 | To work around this, we cache the computed frame size. This | |
11155 | works because we will only be calling RTL expanders that need | |
11156 | to know about leaf functions once reload has completed, and the | |
11157 | frame size cannot be changed after that time, so we can safely | |
11158 | use the cached value. */ | |
11159 | ||
11160 | if (reload_completed) | |
11161 | return cfun->machine->frame_size; | |
11162 | ||
c231c91e RE |
11163 | leaf = leaf_function_p (); |
11164 | ||
11165 | /* A leaf function does not need any stack alignment if it has nothing | |
11166 | on the stack. */ | |
11167 | if (leaf && base_size == 0) | |
11168 | { | |
11169 | cfun->machine->frame_size = 0; | |
11170 | return 0; | |
11171 | } | |
11172 | ||
0977774b JT |
11173 | /* We know that SP will be word aligned on entry, and we must |
11174 | preserve that condition at any subroutine call. But those are | |
11175 | the only constraints. */ | |
11176 | ||
11177 | /* Space for variadic functions. */ | |
11178 | if (current_function_pretend_args_size) | |
11179 | entry_size += current_function_pretend_args_size; | |
11180 | ||
11181 | /* Space for pushed lo registers. */ | |
11182 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
11183 | if (THUMB_REG_PUSHED_P (regno)) | |
11184 | count_regs++; | |
11185 | ||
11186 | /* Space for backtrace structure. */ | |
11187 | if (TARGET_BACKTRACE) | |
11188 | { | |
11189 | if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0) | |
11190 | entry_size += 20; | |
11191 | else | |
11192 | entry_size += 16; | |
11193 | } | |
11194 | ||
c231c91e | 11195 | if (count_regs || !leaf || thumb_far_jump_used_p (1)) |
0977774b JT |
11196 | count_regs++; /* LR */ |
11197 | ||
11198 | entry_size += count_regs * 4; | |
11199 | count_regs = 0; | |
11200 | ||
11201 | /* Space for pushed hi regs. */ | |
11202 | for (regno = 8; regno < 13; regno++) | |
11203 | if (THUMB_REG_PUSHED_P (regno)) | |
11204 | count_regs++; | |
11205 | ||
11206 | entry_size += count_regs * 4; | |
11207 | ||
11208 | if ((entry_size + base_size + current_function_outgoing_args_size) & 7) | |
11209 | base_size += 4; | |
11210 | if ((entry_size + base_size + current_function_outgoing_args_size) & 7) | |
11211 | abort (); | |
11212 | ||
11213 | cfun->machine->frame_size = base_size; | |
11214 | ||
11215 | return base_size; | |
11216 | } | |
11217 | ||
d5b7b3ae | 11218 | /* Generate the rest of a function's prologue. */ |
1d6e90ac | 11219 | |
d5b7b3ae RE |
11220 | void |
11221 | thumb_expand_prologue () | |
11222 | { | |
0977774b | 11223 | HOST_WIDE_INT amount = (thumb_get_frame_size () |
d5b7b3ae | 11224 | + current_function_outgoing_args_size); |
6d3d9133 NC |
11225 | unsigned long func_type; |
11226 | ||
11227 | func_type = arm_current_func_type (); | |
d5b7b3ae RE |
11228 | |
11229 | /* Naked functions don't have prologues. */ | |
6d3d9133 | 11230 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
11231 | return; |
11232 | ||
6d3d9133 NC |
11233 | if (IS_INTERRUPT (func_type)) |
11234 | { | |
c725bd79 | 11235 | error ("interrupt Service Routines cannot be coded in Thumb mode"); |
6d3d9133 NC |
11236 | return; |
11237 | } | |
11238 | ||
d5b7b3ae RE |
11239 | if (frame_pointer_needed) |
11240 | emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx)); | |
11241 | ||
11242 | if (amount) | |
11243 | { | |
0c2ca901 | 11244 | amount = ROUND_UP_WORD (amount); |
d5b7b3ae RE |
11245 | |
11246 | if (amount < 512) | |
11247 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
1d6e90ac | 11248 | GEN_INT (- amount))); |
d5b7b3ae RE |
11249 | else |
11250 | { | |
11251 | int regno; | |
11252 | rtx reg; | |
11253 | ||
11254 | /* The stack decrement is too big for an immediate value in a single | |
11255 | insn. In theory we could issue multiple subtracts, but after | |
11256 | three of them it becomes more space efficient to place the full | |
11257 | value in the constant pool and load into a register. (Also the | |
11258 | ARM debugger really likes to see only one stack decrement per | |
11259 | function). So instead we look for a scratch register into which | |
11260 | we can load the decrement, and then we subtract this from the | |
11261 | stack pointer. Unfortunately on the thumb the only available | |
11262 | scratch registers are the argument registers, and we cannot use | |
11263 | these as they may hold arguments to the function. Instead we | |
11264 | attempt to locate a call preserved register which is used by this | |
11265 | function. If we can find one, then we know that it will have | |
11266 | been pushed at the start of the prologue and so we can corrupt | |
11267 | it now. */ | |
11268 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
aeaf4d25 | 11269 | if (THUMB_REG_PUSHED_P (regno) |
5895f793 RE |
11270 | && !(frame_pointer_needed |
11271 | && (regno == THUMB_HARD_FRAME_POINTER_REGNUM))) | |
d5b7b3ae RE |
11272 | break; |
11273 | ||
aeaf4d25 | 11274 | if (regno > LAST_LO_REGNUM) /* Very unlikely. */ |
d5b7b3ae RE |
11275 | { |
11276 | rtx spare = gen_rtx (REG, SImode, IP_REGNUM); | |
11277 | ||
6bc82793 | 11278 | /* Choose an arbitrary, non-argument low register. */ |
d5b7b3ae RE |
11279 | reg = gen_rtx (REG, SImode, LAST_LO_REGNUM); |
11280 | ||
11281 | /* Save it by copying it into a high, scratch register. */ | |
c14a3a45 NC |
11282 | emit_insn (gen_movsi (spare, reg)); |
11283 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
6bacc7b0 | 11284 | emit_insn (gen_prologue_use (spare)); |
d5b7b3ae RE |
11285 | |
11286 | /* Decrement the stack. */ | |
1d6e90ac | 11287 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
d5b7b3ae RE |
11288 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
11289 | reg)); | |
11290 | ||
11291 | /* Restore the low register's original value. */ | |
11292 | emit_insn (gen_movsi (reg, spare)); | |
11293 | ||
11294 | /* Emit a USE of the restored scratch register, so that flow | |
11295 | analysis will not consider the restore redundant. The | |
11296 | register won't be used again in this function and isn't | |
11297 | restored by the epilogue. */ | |
6bacc7b0 | 11298 | emit_insn (gen_prologue_use (reg)); |
d5b7b3ae RE |
11299 | } |
11300 | else | |
11301 | { | |
11302 | reg = gen_rtx (REG, SImode, regno); | |
11303 | ||
1d6e90ac | 11304 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
d5b7b3ae RE |
11305 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
11306 | reg)); | |
11307 | } | |
11308 | } | |
11309 | } | |
11310 | ||
70f4f91c | 11311 | if (current_function_profile || TARGET_NO_SCHED_PRO) |
d5b7b3ae RE |
11312 | emit_insn (gen_blockage ()); |
11313 | } | |
11314 | ||
11315 | void | |
11316 | thumb_expand_epilogue () | |
11317 | { | |
0977774b | 11318 | HOST_WIDE_INT amount = (thumb_get_frame_size () |
d5b7b3ae | 11319 | + current_function_outgoing_args_size); |
6d3d9133 NC |
11320 | |
11321 | /* Naked functions don't have prologues. */ | |
11322 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
11323 | return; |
11324 | ||
11325 | if (frame_pointer_needed) | |
11326 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
11327 | else if (amount) | |
11328 | { | |
0c2ca901 | 11329 | amount = ROUND_UP_WORD (amount); |
d5b7b3ae RE |
11330 | |
11331 | if (amount < 512) | |
11332 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
11333 | GEN_INT (amount))); | |
11334 | else | |
11335 | { | |
11336 | /* r3 is always free in the epilogue. */ | |
11337 | rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM); | |
11338 | ||
11339 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
11340 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
11341 | } | |
11342 | } | |
11343 | ||
11344 | /* Emit a USE (stack_pointer_rtx), so that | |
11345 | the stack adjustment will not be deleted. */ | |
6bacc7b0 | 11346 | emit_insn (gen_prologue_use (stack_pointer_rtx)); |
d5b7b3ae | 11347 | |
70f4f91c | 11348 | if (current_function_profile || TARGET_NO_SCHED_PRO) |
d5b7b3ae RE |
11349 | emit_insn (gen_blockage ()); |
11350 | } | |
11351 | ||
08c148a8 NB |
11352 | static void |
11353 | thumb_output_function_prologue (f, size) | |
d5b7b3ae | 11354 | FILE * f; |
08c148a8 | 11355 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
d5b7b3ae RE |
11356 | { |
11357 | int live_regs_mask = 0; | |
11358 | int high_regs_pushed = 0; | |
d5b7b3ae RE |
11359 | int regno; |
11360 | ||
6d3d9133 | 11361 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
11362 | return; |
11363 | ||
11364 | if (is_called_in_ARM_mode (current_function_decl)) | |
11365 | { | |
11366 | const char * name; | |
11367 | ||
11368 | if (GET_CODE (DECL_RTL (current_function_decl)) != MEM) | |
11369 | abort (); | |
11370 | if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF) | |
11371 | abort (); | |
11372 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
11373 | ||
11374 | /* Generate code sequence to switch us into Thumb mode. */ | |
11375 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 11376 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
11377 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
11378 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
11379 | ||
11380 | /* Generate a label, so that the debugger will notice the | |
11381 | change in instruction sets. This label is also used by | |
11382 | the assembler to bypass the ARM code when this function | |
11383 | is called from a Thumb encoded function elsewhere in the | |
11384 | same file. Hence the definition of STUB_NAME here must | |
11385 | agree with the definition in gas/config/tc-arm.c */ | |
11386 | ||
11387 | #define STUB_NAME ".real_start_of" | |
11388 | ||
761c70aa | 11389 | fprintf (f, "\t.code\t16\n"); |
d5b7b3ae RE |
11390 | #ifdef ARM_PE |
11391 | if (arm_dllexport_name_p (name)) | |
e5951263 | 11392 | name = arm_strip_name_encoding (name); |
d5b7b3ae RE |
11393 | #endif |
11394 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); | |
761c70aa | 11395 | fprintf (f, "\t.thumb_func\n"); |
d5b7b3ae RE |
11396 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); |
11397 | } | |
11398 | ||
d5b7b3ae RE |
11399 | if (current_function_pretend_args_size) |
11400 | { | |
3cb66fd7 | 11401 | if (cfun->machine->uses_anonymous_args) |
d5b7b3ae RE |
11402 | { |
11403 | int num_pushes; | |
11404 | ||
761c70aa | 11405 | fprintf (f, "\tpush\t{"); |
d5b7b3ae | 11406 | |
e9d7b180 | 11407 | num_pushes = ARM_NUM_INTS (current_function_pretend_args_size); |
d5b7b3ae RE |
11408 | |
11409 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; | |
11410 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 11411 | regno++) |
d5b7b3ae RE |
11412 | asm_fprintf (f, "%r%s", regno, |
11413 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
11414 | ||
761c70aa | 11415 | fprintf (f, "}\n"); |
d5b7b3ae RE |
11416 | } |
11417 | else | |
11418 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", | |
11419 | SP_REGNUM, SP_REGNUM, | |
11420 | current_function_pretend_args_size); | |
11421 | } | |
11422 | ||
5895f793 | 11423 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) |
aeaf4d25 | 11424 | if (THUMB_REG_PUSHED_P (regno)) |
d5b7b3ae RE |
11425 | live_regs_mask |= 1 << regno; |
11426 | ||
5895f793 | 11427 | if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1)) |
d5b7b3ae RE |
11428 | live_regs_mask |= 1 << LR_REGNUM; |
11429 | ||
11430 | if (TARGET_BACKTRACE) | |
11431 | { | |
11432 | int offset; | |
11433 | int work_register = 0; | |
11434 | int wr; | |
11435 | ||
11436 | /* We have been asked to create a stack backtrace structure. | |
11437 | The code looks like this: | |
11438 | ||
11439 | 0 .align 2 | |
11440 | 0 func: | |
11441 | 0 sub SP, #16 Reserve space for 4 registers. | |
11442 | 2 push {R7} Get a work register. | |
11443 | 4 add R7, SP, #20 Get the stack pointer before the push. | |
11444 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
11445 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
11446 | 10 str R7, [SP, #16] Store it. | |
11447 | 12 mov R7, FP Get hold of the current frame pointer. | |
11448 | 14 str R7, [SP, #4] Store it. | |
11449 | 16 mov R7, LR Get hold of the current return address. | |
11450 | 18 str R7, [SP, #12] Store it. | |
11451 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
11452 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
11453 | ||
11454 | if ((live_regs_mask & 0xFF) == 0) | |
11455 | { | |
11456 | /* See if the a4 register is free. */ | |
11457 | ||
11458 | if (regs_ever_live [LAST_ARG_REGNUM] == 0) | |
11459 | work_register = LAST_ARG_REGNUM; | |
11460 | else /* We must push a register of our own */ | |
11461 | live_regs_mask |= (1 << LAST_LO_REGNUM); | |
11462 | } | |
11463 | ||
11464 | if (work_register == 0) | |
11465 | { | |
11466 | /* Select a register from the list that will be pushed to | |
11467 | use as our work register. */ | |
11468 | for (work_register = (LAST_LO_REGNUM + 1); work_register--;) | |
11469 | if ((1 << work_register) & live_regs_mask) | |
11470 | break; | |
11471 | } | |
11472 | ||
11473 | asm_fprintf | |
11474 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
11475 | SP_REGNUM, SP_REGNUM); | |
11476 | ||
11477 | if (live_regs_mask) | |
11478 | thumb_pushpop (f, live_regs_mask, 1); | |
11479 | ||
11480 | for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1) | |
11481 | if (wr & live_regs_mask) | |
11482 | offset += 4; | |
11483 | ||
11484 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
11485 | offset + 16 + current_function_pretend_args_size); | |
11486 | ||
11487 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
11488 | offset + 4); | |
11489 | ||
11490 | /* Make sure that the instruction fetching the PC is in the right place | |
11491 | to calculate "start of backtrace creation code + 12". */ | |
11492 | if (live_regs_mask) | |
11493 | { | |
11494 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
11495 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
11496 | offset + 12); | |
11497 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
11498 | ARM_HARD_FRAME_POINTER_REGNUM); | |
11499 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
11500 | offset); | |
11501 | } | |
11502 | else | |
11503 | { | |
11504 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
11505 | ARM_HARD_FRAME_POINTER_REGNUM); | |
11506 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
11507 | offset); | |
11508 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
11509 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
11510 | offset + 12); | |
11511 | } | |
11512 | ||
11513 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); | |
11514 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
11515 | offset + 8); | |
11516 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
11517 | offset + 12); | |
11518 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
11519 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
11520 | } | |
11521 | else if (live_regs_mask) | |
11522 | thumb_pushpop (f, live_regs_mask, 1); | |
11523 | ||
11524 | for (regno = 8; regno < 13; regno++) | |
e26053d1 NC |
11525 | if (THUMB_REG_PUSHED_P (regno)) |
11526 | high_regs_pushed++; | |
d5b7b3ae RE |
11527 | |
11528 | if (high_regs_pushed) | |
11529 | { | |
11530 | int pushable_regs = 0; | |
11531 | int mask = live_regs_mask & 0xff; | |
11532 | int next_hi_reg; | |
11533 | ||
11534 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
e26053d1 NC |
11535 | if (THUMB_REG_PUSHED_P (next_hi_reg)) |
11536 | break; | |
d5b7b3ae RE |
11537 | |
11538 | pushable_regs = mask; | |
11539 | ||
11540 | if (pushable_regs == 0) | |
11541 | { | |
11542 | /* Desperation time -- this probably will never happen. */ | |
aeaf4d25 | 11543 | if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)) |
d5b7b3ae RE |
11544 | asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM); |
11545 | mask = 1 << LAST_ARG_REGNUM; | |
11546 | } | |
11547 | ||
11548 | while (high_regs_pushed > 0) | |
11549 | { | |
11550 | for (regno = LAST_LO_REGNUM; regno >= 0; regno--) | |
11551 | { | |
11552 | if (mask & (1 << regno)) | |
11553 | { | |
11554 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
11555 | ||
5895f793 | 11556 | high_regs_pushed--; |
d5b7b3ae RE |
11557 | |
11558 | if (high_regs_pushed) | |
aeaf4d25 AN |
11559 | { |
11560 | for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM; | |
11561 | next_hi_reg--) | |
11562 | if (THUMB_REG_PUSHED_P (next_hi_reg)) | |
d5b7b3ae | 11563 | break; |
aeaf4d25 | 11564 | } |
d5b7b3ae RE |
11565 | else |
11566 | { | |
5895f793 | 11567 | mask &= ~((1 << regno) - 1); |
d5b7b3ae RE |
11568 | break; |
11569 | } | |
11570 | } | |
11571 | } | |
11572 | ||
11573 | thumb_pushpop (f, mask, 1); | |
11574 | } | |
11575 | ||
11576 | if (pushable_regs == 0 | |
aeaf4d25 | 11577 | && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))) |
d5b7b3ae RE |
11578 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
11579 | } | |
11580 | } | |
11581 | ||
11582 | /* Handle the case of a double word load into a low register from | |
11583 | a computed memory address. The computed address may involve a | |
11584 | register which is overwritten by the load. */ | |
11585 | ||
cd2b33d0 | 11586 | const char * |
d5b7b3ae | 11587 | thumb_load_double_from_address (operands) |
400500c4 | 11588 | rtx *operands; |
d5b7b3ae RE |
11589 | { |
11590 | rtx addr; | |
11591 | rtx base; | |
11592 | rtx offset; | |
11593 | rtx arg1; | |
11594 | rtx arg2; | |
11595 | ||
11596 | if (GET_CODE (operands[0]) != REG) | |
400500c4 | 11597 | abort (); |
d5b7b3ae RE |
11598 | |
11599 | if (GET_CODE (operands[1]) != MEM) | |
400500c4 | 11600 | abort (); |
d5b7b3ae RE |
11601 | |
11602 | /* Get the memory address. */ | |
11603 | addr = XEXP (operands[1], 0); | |
11604 | ||
11605 | /* Work out how the memory address is computed. */ | |
11606 | switch (GET_CODE (addr)) | |
11607 | { | |
11608 | case REG: | |
11609 | operands[2] = gen_rtx (MEM, SImode, | |
11610 | plus_constant (XEXP (operands[1], 0), 4)); | |
11611 | ||
11612 | if (REGNO (operands[0]) == REGNO (addr)) | |
11613 | { | |
11614 | output_asm_insn ("ldr\t%H0, %2", operands); | |
11615 | output_asm_insn ("ldr\t%0, %1", operands); | |
11616 | } | |
11617 | else | |
11618 | { | |
11619 | output_asm_insn ("ldr\t%0, %1", operands); | |
11620 | output_asm_insn ("ldr\t%H0, %2", operands); | |
11621 | } | |
11622 | break; | |
11623 | ||
11624 | case CONST: | |
11625 | /* Compute <address> + 4 for the high order load. */ | |
11626 | operands[2] = gen_rtx (MEM, SImode, | |
11627 | plus_constant (XEXP (operands[1], 0), 4)); | |
11628 | ||
11629 | output_asm_insn ("ldr\t%0, %1", operands); | |
11630 | output_asm_insn ("ldr\t%H0, %2", operands); | |
11631 | break; | |
11632 | ||
11633 | case PLUS: | |
11634 | arg1 = XEXP (addr, 0); | |
11635 | arg2 = XEXP (addr, 1); | |
11636 | ||
11637 | if (CONSTANT_P (arg1)) | |
11638 | base = arg2, offset = arg1; | |
11639 | else | |
11640 | base = arg1, offset = arg2; | |
11641 | ||
11642 | if (GET_CODE (base) != REG) | |
400500c4 | 11643 | abort (); |
d5b7b3ae RE |
11644 | |
11645 | /* Catch the case of <address> = <reg> + <reg> */ | |
11646 | if (GET_CODE (offset) == REG) | |
11647 | { | |
11648 | int reg_offset = REGNO (offset); | |
11649 | int reg_base = REGNO (base); | |
11650 | int reg_dest = REGNO (operands[0]); | |
11651 | ||
11652 | /* Add the base and offset registers together into the | |
11653 | higher destination register. */ | |
11654 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
11655 | reg_dest + 1, reg_base, reg_offset); | |
11656 | ||
11657 | /* Load the lower destination register from the address in | |
11658 | the higher destination register. */ | |
11659 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
11660 | reg_dest, reg_dest + 1); | |
11661 | ||
11662 | /* Load the higher destination register from its own address | |
11663 | plus 4. */ | |
11664 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
11665 | reg_dest + 1, reg_dest + 1); | |
11666 | } | |
11667 | else | |
11668 | { | |
11669 | /* Compute <address> + 4 for the high order load. */ | |
11670 | operands[2] = gen_rtx (MEM, SImode, | |
11671 | plus_constant (XEXP (operands[1], 0), 4)); | |
11672 | ||
11673 | /* If the computed address is held in the low order register | |
11674 | then load the high order register first, otherwise always | |
11675 | load the low order register first. */ | |
11676 | if (REGNO (operands[0]) == REGNO (base)) | |
11677 | { | |
11678 | output_asm_insn ("ldr\t%H0, %2", operands); | |
11679 | output_asm_insn ("ldr\t%0, %1", operands); | |
11680 | } | |
11681 | else | |
11682 | { | |
11683 | output_asm_insn ("ldr\t%0, %1", operands); | |
11684 | output_asm_insn ("ldr\t%H0, %2", operands); | |
11685 | } | |
11686 | } | |
11687 | break; | |
11688 | ||
11689 | case LABEL_REF: | |
11690 | /* With no registers to worry about we can just load the value | |
11691 | directly. */ | |
11692 | operands[2] = gen_rtx (MEM, SImode, | |
11693 | plus_constant (XEXP (operands[1], 0), 4)); | |
11694 | ||
11695 | output_asm_insn ("ldr\t%H0, %2", operands); | |
11696 | output_asm_insn ("ldr\t%0, %1", operands); | |
11697 | break; | |
11698 | ||
11699 | default: | |
400500c4 | 11700 | abort (); |
d5b7b3ae RE |
11701 | break; |
11702 | } | |
11703 | ||
11704 | return ""; | |
11705 | } | |
11706 | ||
11707 | ||
cd2b33d0 | 11708 | const char * |
d5b7b3ae RE |
11709 | thumb_output_move_mem_multiple (n, operands) |
11710 | int n; | |
11711 | rtx * operands; | |
11712 | { | |
11713 | rtx tmp; | |
11714 | ||
11715 | switch (n) | |
11716 | { | |
11717 | case 2: | |
ca356f3a | 11718 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 11719 | { |
ca356f3a RE |
11720 | tmp = operands[4]; |
11721 | operands[4] = operands[5]; | |
11722 | operands[5] = tmp; | |
d5b7b3ae | 11723 | } |
ca356f3a RE |
11724 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
11725 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
11726 | break; |
11727 | ||
11728 | case 3: | |
ca356f3a | 11729 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 11730 | { |
ca356f3a RE |
11731 | tmp = operands[4]; |
11732 | operands[4] = operands[5]; | |
11733 | operands[5] = tmp; | |
d5b7b3ae | 11734 | } |
ca356f3a | 11735 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 11736 | { |
ca356f3a RE |
11737 | tmp = operands[5]; |
11738 | operands[5] = operands[6]; | |
11739 | operands[6] = tmp; | |
d5b7b3ae | 11740 | } |
ca356f3a | 11741 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 11742 | { |
ca356f3a RE |
11743 | tmp = operands[4]; |
11744 | operands[4] = operands[5]; | |
11745 | operands[5] = tmp; | |
d5b7b3ae RE |
11746 | } |
11747 | ||
ca356f3a RE |
11748 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
11749 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
11750 | break; |
11751 | ||
11752 | default: | |
11753 | abort (); | |
11754 | } | |
11755 | ||
11756 | return ""; | |
11757 | } | |
11758 | ||
1d6e90ac | 11759 | /* Routines for generating rtl. */ |
d5b7b3ae RE |
11760 | |
11761 | void | |
11762 | thumb_expand_movstrqi (operands) | |
11763 | rtx * operands; | |
11764 | { | |
11765 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
11766 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
11767 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
11768 | HOST_WIDE_INT offset = 0; | |
11769 | ||
11770 | while (len >= 12) | |
11771 | { | |
ca356f3a | 11772 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
11773 | len -= 12; |
11774 | } | |
11775 | ||
11776 | if (len >= 8) | |
11777 | { | |
ca356f3a | 11778 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
11779 | len -= 8; |
11780 | } | |
11781 | ||
11782 | if (len >= 4) | |
11783 | { | |
11784 | rtx reg = gen_reg_rtx (SImode); | |
11785 | emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in))); | |
11786 | emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg)); | |
11787 | len -= 4; | |
11788 | offset += 4; | |
11789 | } | |
11790 | ||
11791 | if (len >= 2) | |
11792 | { | |
11793 | rtx reg = gen_reg_rtx (HImode); | |
11794 | emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode, | |
11795 | plus_constant (in, offset)))); | |
11796 | emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)), | |
11797 | reg)); | |
11798 | len -= 2; | |
11799 | offset += 2; | |
11800 | } | |
11801 | ||
11802 | if (len) | |
11803 | { | |
11804 | rtx reg = gen_reg_rtx (QImode); | |
11805 | emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode, | |
11806 | plus_constant (in, offset)))); | |
11807 | emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)), | |
11808 | reg)); | |
11809 | } | |
11810 | } | |
11811 | ||
11812 | int | |
11813 | thumb_cmp_operand (op, mode) | |
11814 | rtx op; | |
11815 | enum machine_mode mode; | |
11816 | { | |
11817 | return ((GET_CODE (op) == CONST_INT | |
11818 | && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256) | |
11819 | || register_operand (op, mode)); | |
11820 | } | |
11821 | ||
cd2b33d0 | 11822 | static const char * |
d5b7b3ae RE |
11823 | thumb_condition_code (x, invert) |
11824 | rtx x; | |
11825 | int invert; | |
11826 | { | |
1d6e90ac | 11827 | static const char * const conds[] = |
d5b7b3ae RE |
11828 | { |
11829 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
11830 | "hi", "ls", "ge", "lt", "gt", "le" | |
11831 | }; | |
11832 | int val; | |
11833 | ||
11834 | switch (GET_CODE (x)) | |
11835 | { | |
11836 | case EQ: val = 0; break; | |
11837 | case NE: val = 1; break; | |
11838 | case GEU: val = 2; break; | |
11839 | case LTU: val = 3; break; | |
11840 | case GTU: val = 8; break; | |
11841 | case LEU: val = 9; break; | |
11842 | case GE: val = 10; break; | |
11843 | case LT: val = 11; break; | |
11844 | case GT: val = 12; break; | |
11845 | case LE: val = 13; break; | |
11846 | default: | |
11847 | abort (); | |
11848 | } | |
11849 | ||
11850 | return conds[val ^ invert]; | |
11851 | } | |
11852 | ||
11853 | /* Handle storing a half-word to memory during reload. */ | |
1d6e90ac | 11854 | |
d5b7b3ae RE |
11855 | void |
11856 | thumb_reload_out_hi (operands) | |
11857 | rtx * operands; | |
11858 | { | |
11859 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
11860 | } | |
11861 | ||
11862 | /* Handle storing a half-word to memory during reload. */ | |
1d6e90ac | 11863 | |
d5b7b3ae RE |
11864 | void |
11865 | thumb_reload_in_hi (operands) | |
11866 | rtx * operands ATTRIBUTE_UNUSED; | |
11867 | { | |
11868 | abort (); | |
11869 | } | |
11870 | ||
c27ba912 DM |
11871 | /* Return the length of a function name prefix |
11872 | that starts with the character 'c'. */ | |
1d6e90ac | 11873 | |
c27ba912 | 11874 | static int |
ab2877a3 KG |
11875 | arm_get_strip_length (c) |
11876 | int c; | |
c27ba912 DM |
11877 | { |
11878 | switch (c) | |
11879 | { | |
11880 | ARM_NAME_ENCODING_LENGTHS | |
11881 | default: return 0; | |
11882 | } | |
11883 | } | |
11884 | ||
11885 | /* Return a pointer to a function's name with any | |
11886 | and all prefix encodings stripped from it. */ | |
1d6e90ac | 11887 | |
c27ba912 | 11888 | const char * |
ab2877a3 KG |
11889 | arm_strip_name_encoding (name) |
11890 | const char * name; | |
c27ba912 DM |
11891 | { |
11892 | int skip; | |
11893 | ||
11894 | while ((skip = arm_get_strip_length (* name))) | |
11895 | name += skip; | |
11896 | ||
11897 | return name; | |
11898 | } | |
11899 | ||
e1944073 KW |
11900 | /* If there is a '*' anywhere in the name's prefix, then |
11901 | emit the stripped name verbatim, otherwise prepend an | |
11902 | underscore if leading underscores are being used. */ | |
11903 | ||
11904 | void | |
11905 | arm_asm_output_labelref (stream, name) | |
11906 | FILE * stream; | |
11907 | const char * name; | |
11908 | { | |
11909 | int skip; | |
11910 | int verbatim = 0; | |
11911 | ||
11912 | while ((skip = arm_get_strip_length (* name))) | |
11913 | { | |
11914 | verbatim |= (*name == '*'); | |
11915 | name += skip; | |
11916 | } | |
11917 | ||
11918 | if (verbatim) | |
11919 | fputs (name, stream); | |
11920 | else | |
11921 | asm_fprintf (stream, "%U%s", name); | |
11922 | } | |
11923 | ||
e2500fed GK |
11924 | rtx aof_pic_label; |
11925 | ||
2b835d68 | 11926 | #ifdef AOF_ASSEMBLER |
6354dc9b | 11927 | /* Special functions only needed when producing AOF syntax assembler. */ |
2b835d68 | 11928 | |
32de079a RE |
11929 | struct pic_chain |
11930 | { | |
62b10bbc | 11931 | struct pic_chain * next; |
5f37d07c | 11932 | const char * symname; |
32de079a RE |
11933 | }; |
11934 | ||
62b10bbc | 11935 | static struct pic_chain * aof_pic_chain = NULL; |
32de079a RE |
11936 | |
11937 | rtx | |
11938 | aof_pic_entry (x) | |
11939 | rtx x; | |
11940 | { | |
62b10bbc | 11941 | struct pic_chain ** chainp; |
32de079a RE |
11942 | int offset; |
11943 | ||
11944 | if (aof_pic_label == NULL_RTX) | |
11945 | { | |
43cffd11 | 11946 | aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons"); |
32de079a RE |
11947 | } |
11948 | ||
11949 | for (offset = 0, chainp = &aof_pic_chain; *chainp; | |
11950 | offset += 4, chainp = &(*chainp)->next) | |
11951 | if ((*chainp)->symname == XSTR (x, 0)) | |
11952 | return plus_constant (aof_pic_label, offset); | |
11953 | ||
11954 | *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain)); | |
11955 | (*chainp)->next = NULL; | |
11956 | (*chainp)->symname = XSTR (x, 0); | |
11957 | return plus_constant (aof_pic_label, offset); | |
11958 | } | |
11959 | ||
11960 | void | |
11961 | aof_dump_pic_table (f) | |
62b10bbc | 11962 | FILE * f; |
32de079a | 11963 | { |
62b10bbc | 11964 | struct pic_chain * chain; |
32de079a RE |
11965 | |
11966 | if (aof_pic_chain == NULL) | |
11967 | return; | |
11968 | ||
dd18ae56 NC |
11969 | asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n", |
11970 | PIC_OFFSET_TABLE_REGNUM, | |
11971 | PIC_OFFSET_TABLE_REGNUM); | |
32de079a RE |
11972 | fputs ("|x$adcons|\n", f); |
11973 | ||
11974 | for (chain = aof_pic_chain; chain; chain = chain->next) | |
11975 | { | |
11976 | fputs ("\tDCD\t", f); | |
11977 | assemble_name (f, chain->symname); | |
11978 | fputs ("\n", f); | |
11979 | } | |
11980 | } | |
11981 | ||
2b835d68 RE |
11982 | int arm_text_section_count = 1; |
11983 | ||
11984 | char * | |
84ed5e79 | 11985 | aof_text_section () |
2b835d68 RE |
11986 | { |
11987 | static char buf[100]; | |
2b835d68 RE |
11988 | sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY", |
11989 | arm_text_section_count++); | |
11990 | if (flag_pic) | |
11991 | strcat (buf, ", PIC, REENTRANT"); | |
11992 | return buf; | |
11993 | } | |
11994 | ||
11995 | static int arm_data_section_count = 1; | |
11996 | ||
11997 | char * | |
11998 | aof_data_section () | |
11999 | { | |
12000 | static char buf[100]; | |
12001 | sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++); | |
12002 | return buf; | |
12003 | } | |
12004 | ||
12005 | /* The AOF assembler is religiously strict about declarations of | |
12006 | imported and exported symbols, so that it is impossible to declare | |
956d6950 | 12007 | a function as imported near the beginning of the file, and then to |
2b835d68 RE |
12008 | export it later on. It is, however, possible to delay the decision |
12009 | until all the functions in the file have been compiled. To get | |
12010 | around this, we maintain a list of the imports and exports, and | |
12011 | delete from it any that are subsequently defined. At the end of | |
12012 | compilation we spit the remainder of the list out before the END | |
12013 | directive. */ | |
12014 | ||
12015 | struct import | |
12016 | { | |
62b10bbc | 12017 | struct import * next; |
5f37d07c | 12018 | const char * name; |
2b835d68 RE |
12019 | }; |
12020 | ||
62b10bbc | 12021 | static struct import * imports_list = NULL; |
2b835d68 RE |
12022 | |
12023 | void | |
12024 | aof_add_import (name) | |
5f37d07c | 12025 | const char * name; |
2b835d68 | 12026 | { |
62b10bbc | 12027 | struct import * new; |
2b835d68 RE |
12028 | |
12029 | for (new = imports_list; new; new = new->next) | |
12030 | if (new->name == name) | |
12031 | return; | |
12032 | ||
12033 | new = (struct import *) xmalloc (sizeof (struct import)); | |
12034 | new->next = imports_list; | |
12035 | imports_list = new; | |
12036 | new->name = name; | |
12037 | } | |
12038 | ||
12039 | void | |
12040 | aof_delete_import (name) | |
5f37d07c | 12041 | const char * name; |
2b835d68 | 12042 | { |
62b10bbc | 12043 | struct import ** old; |
2b835d68 RE |
12044 | |
12045 | for (old = &imports_list; *old; old = & (*old)->next) | |
12046 | { | |
12047 | if ((*old)->name == name) | |
12048 | { | |
12049 | *old = (*old)->next; | |
12050 | return; | |
12051 | } | |
12052 | } | |
12053 | } | |
12054 | ||
12055 | int arm_main_function = 0; | |
12056 | ||
12057 | void | |
12058 | aof_dump_imports (f) | |
62b10bbc | 12059 | FILE * f; |
2b835d68 RE |
12060 | { |
12061 | /* The AOF assembler needs this to cause the startup code to be extracted | |
12062 | from the library. Brining in __main causes the whole thing to work | |
12063 | automagically. */ | |
12064 | if (arm_main_function) | |
12065 | { | |
12066 | text_section (); | |
12067 | fputs ("\tIMPORT __main\n", f); | |
12068 | fputs ("\tDCD __main\n", f); | |
12069 | } | |
12070 | ||
12071 | /* Now dump the remaining imports. */ | |
12072 | while (imports_list) | |
12073 | { | |
12074 | fprintf (f, "\tIMPORT\t"); | |
12075 | assemble_name (f, imports_list->name); | |
12076 | fputc ('\n', f); | |
12077 | imports_list = imports_list->next; | |
12078 | } | |
12079 | } | |
5eb99654 KG |
12080 | |
12081 | static void | |
12082 | aof_globalize_label (stream, name) | |
12083 | FILE *stream; | |
12084 | const char *name; | |
12085 | { | |
12086 | default_globalize_label (stream, name); | |
12087 | if (! strcmp (name, "main")) | |
12088 | arm_main_function = 1; | |
12089 | } | |
2b835d68 | 12090 | #endif /* AOF_ASSEMBLER */ |
7c262518 | 12091 | |
ebe413e5 | 12092 | #ifdef OBJECT_FORMAT_ELF |
7c262518 RH |
12093 | /* Switch to an arbitrary section NAME with attributes as specified |
12094 | by FLAGS. ALIGN specifies any known alignment requirements for | |
12095 | the section; 0 if the default should be used. | |
12096 | ||
12097 | Differs from the default elf version only in the prefix character | |
12098 | used before the section type. */ | |
12099 | ||
12100 | static void | |
715bdd29 | 12101 | arm_elf_asm_named_section (name, flags) |
7c262518 RH |
12102 | const char *name; |
12103 | unsigned int flags; | |
7c262518 | 12104 | { |
6a0a6ac4 AM |
12105 | char flagchars[10], *f = flagchars; |
12106 | ||
12107 | if (! named_section_first_declaration (name)) | |
12108 | { | |
12109 | fprintf (asm_out_file, "\t.section\t%s\n", name); | |
12110 | return; | |
12111 | } | |
7c262518 RH |
12112 | |
12113 | if (!(flags & SECTION_DEBUG)) | |
12114 | *f++ = 'a'; | |
12115 | if (flags & SECTION_WRITE) | |
12116 | *f++ = 'w'; | |
12117 | if (flags & SECTION_CODE) | |
12118 | *f++ = 'x'; | |
12119 | if (flags & SECTION_SMALL) | |
12120 | *f++ = 's'; | |
201556f0 JJ |
12121 | if (flags & SECTION_MERGE) |
12122 | *f++ = 'M'; | |
12123 | if (flags & SECTION_STRINGS) | |
12124 | *f++ = 'S'; | |
6a0a6ac4 AM |
12125 | if (flags & SECTION_TLS) |
12126 | *f++ = 'T'; | |
7c262518 RH |
12127 | *f = '\0'; |
12128 | ||
6a0a6ac4 | 12129 | fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars); |
7c262518 | 12130 | |
6a0a6ac4 AM |
12131 | if (!(flags & SECTION_NOTYPE)) |
12132 | { | |
12133 | const char *type; | |
12134 | ||
12135 | if (flags & SECTION_BSS) | |
12136 | type = "nobits"; | |
12137 | else | |
12138 | type = "progbits"; | |
12139 | ||
12140 | fprintf (asm_out_file, ",%%%s", type); | |
12141 | ||
12142 | if (flags & SECTION_ENTSIZE) | |
12143 | fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE); | |
12144 | } | |
12145 | ||
12146 | putc ('\n', asm_out_file); | |
7c262518 | 12147 | } |
ebe413e5 | 12148 | #endif |
fb49053f RH |
12149 | |
12150 | #ifndef ARM_PE | |
12151 | /* Symbols in the text segment can be accessed without indirecting via the | |
12152 | constant pool; it may take an extra binary operation, but this is still | |
12153 | faster than indirecting via memory. Don't do this when not optimizing, | |
12154 | since we won't be calculating al of the offsets necessary to do this | |
12155 | simplification. */ | |
12156 | ||
12157 | static void | |
c6a2438a | 12158 | arm_encode_section_info (decl, rtl, first) |
fb49053f | 12159 | tree decl; |
c6a2438a | 12160 | rtx rtl; |
fb49053f RH |
12161 | int first; |
12162 | { | |
12163 | /* This doesn't work with AOF syntax, since the string table may be in | |
12164 | a different AREA. */ | |
12165 | #ifndef AOF_ASSEMBLER | |
12166 | if (optimize > 0 && TREE_CONSTANT (decl) | |
12167 | && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) | |
c6a2438a | 12168 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
fb49053f RH |
12169 | #endif |
12170 | ||
12171 | /* If we are referencing a function that is weak then encode a long call | |
12172 | flag in the function name, otherwise if the function is static or | |
12173 | or known to be defined in this file then encode a short call flag. */ | |
12174 | if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd') | |
12175 | { | |
12176 | if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl)) | |
12177 | arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); | |
12178 | else if (! TREE_PUBLIC (decl)) | |
12179 | arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); | |
12180 | } | |
12181 | } | |
12182 | #endif /* !ARM_PE */ | |
483ab821 | 12183 | |
4977bab6 ZW |
12184 | static void |
12185 | arm_internal_label (stream, prefix, labelno) | |
12186 | FILE *stream; | |
12187 | const char *prefix; | |
12188 | unsigned long labelno; | |
12189 | { | |
12190 | if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno | |
12191 | && !strcmp (prefix, "L")) | |
12192 | { | |
12193 | arm_ccfsm_state = 0; | |
12194 | arm_target_insn = NULL; | |
12195 | } | |
12196 | default_internal_label (stream, prefix, labelno); | |
12197 | } | |
12198 | ||
c590b625 RH |
12199 | /* Output code to add DELTA to the first argument, and then jump |
12200 | to FUNCTION. Used for C++ multiple inheritance. */ | |
12201 | ||
12202 | static void | |
3961e8fe | 12203 | arm_output_mi_thunk (file, thunk, delta, vcall_offset, function) |
483ab821 MM |
12204 | FILE *file; |
12205 | tree thunk ATTRIBUTE_UNUSED; | |
eb0424da | 12206 | HOST_WIDE_INT delta; |
3961e8fe | 12207 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED; |
483ab821 MM |
12208 | tree function; |
12209 | { | |
12210 | int mi_delta = delta; | |
12211 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; | |
12212 | int shift = 0; | |
12213 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) | |
12214 | ? 1 : 0); | |
12215 | if (mi_delta < 0) | |
12216 | mi_delta = - mi_delta; | |
12217 | while (mi_delta != 0) | |
12218 | { | |
12219 | if ((mi_delta & (3 << shift)) == 0) | |
12220 | shift += 2; | |
12221 | else | |
12222 | { | |
12223 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
12224 | mi_op, this_regno, this_regno, | |
12225 | mi_delta & (0xff << shift)); | |
12226 | mi_delta &= ~(0xff << shift); | |
12227 | shift += 8; | |
12228 | } | |
12229 | } | |
12230 | fputs ("\tb\t", file); | |
12231 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
12232 | if (NEED_PLT_RELOC) | |
12233 | fputs ("(PLT)", file); | |
12234 | fputc ('\n', file); | |
12235 | } |