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b36ba79f | 1 | /* Output routines for GCC for ARM. |
f954388e | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
b3a796bc JJ |
3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
4 | Free Software Foundation, Inc. | |
cce8749e | 5 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 6 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 7 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e | 8 | |
4f448245 | 9 | This file is part of GCC. |
cce8749e | 10 | |
4f448245 NC |
11 | GCC is free software; you can redistribute it and/or modify it |
12 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 13 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 14 | option) any later version. |
cce8749e | 15 | |
4f448245 NC |
16 | GCC is distributed in the hope that it will be useful, but WITHOUT |
17 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
18 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
19 | License for more details. | |
cce8749e | 20 | |
4f448245 | 21 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
22 | along with GCC; see the file COPYING3. If not see |
23 | <http://www.gnu.org/licenses/>. */ | |
f676971a | 24 | |
56636818 | 25 | #include "config.h" |
43cffd11 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
cce8749e | 29 | #include "rtl.h" |
d5b7b3ae | 30 | #include "tree.h" |
c7319d87 | 31 | #include "obstack.h" |
cce8749e CH |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
34 | #include "real.h" | |
35 | #include "insn-config.h" | |
36 | #include "conditions.h" | |
cce8749e CH |
37 | #include "output.h" |
38 | #include "insn-attr.h" | |
39 | #include "flags.h" | |
af48348a | 40 | #include "reload.h" |
49ad7cfa | 41 | #include "function.h" |
bee06f3d | 42 | #include "expr.h" |
e78d8e51 | 43 | #include "optabs.h" |
ad076f4e | 44 | #include "toplev.h" |
aec3cfba | 45 | #include "recog.h" |
92a432f4 | 46 | #include "ggc.h" |
d5b7b3ae | 47 | #include "except.h" |
8b97c5f8 | 48 | #include "c-pragma.h" |
7b8b8ade | 49 | #include "integrate.h" |
c27ba912 | 50 | #include "tm_p.h" |
672a6f42 NB |
51 | #include "target.h" |
52 | #include "target-def.h" | |
980e61bb | 53 | #include "debug.h" |
6e34d3a3 | 54 | #include "langhooks.h" |
6fb5fa3c | 55 | #include "df.h" |
cce8749e | 56 | |
d5b7b3ae RE |
57 | /* Forward definitions of types. */ |
58 | typedef struct minipool_node Mnode; | |
59 | typedef struct minipool_fixup Mfix; | |
60 | ||
1d6e90ac NC |
61 | const struct attribute_spec arm_attribute_table[]; |
62 | ||
b76c3c4b PB |
63 | void (*arm_lang_output_object_attributes_hook)(void); |
64 | ||
d5b7b3ae | 65 | /* Forward function declarations. */ |
35596784 | 66 | static int arm_compute_static_chain_stack_bytes (void); |
5848830f | 67 | static arm_stack_offsets *arm_get_frame_offsets (void); |
e32bac5b | 68 | static void arm_add_gc_roots (void); |
a406f566 MM |
69 | static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx, |
70 | HOST_WIDE_INT, rtx, rtx, int, int); | |
e32bac5b RE |
71 | static unsigned bit_count (unsigned long); |
72 | static int arm_address_register_rtx_p (rtx, int); | |
1e1ab407 | 73 | static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); |
5b3e6663 PB |
74 | static int thumb2_legitimate_index_p (enum machine_mode, rtx, int); |
75 | static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int); | |
76 | inline static int thumb1_index_register_rtx_p (rtx, int); | |
5848830f | 77 | static int thumb_far_jump_used_p (void); |
57934c39 | 78 | static bool thumb_force_lr_save (void); |
e32bac5b | 79 | static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); |
e32bac5b | 80 | static rtx emit_sfm (int, int); |
466e4b7a | 81 | static unsigned arm_size_return_regs (void); |
e32bac5b | 82 | static bool arm_assemble_integer (rtx, unsigned int, int); |
e32bac5b RE |
83 | static const char *fp_const_from_val (REAL_VALUE_TYPE *); |
84 | static arm_cc get_arm_condition_code (rtx); | |
e32bac5b RE |
85 | static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); |
86 | static rtx is_jump_table (rtx); | |
87 | static const char *output_multi_immediate (rtx *, const char *, const char *, | |
88 | int, HOST_WIDE_INT); | |
e32bac5b RE |
89 | static const char *shift_op (rtx, HOST_WIDE_INT *); |
90 | static struct machine_function *arm_init_machine_status (void); | |
c9ca9b88 | 91 | static void thumb_exit (FILE *, int); |
e32bac5b RE |
92 | static rtx is_jump_table (rtx); |
93 | static HOST_WIDE_INT get_jump_table_size (rtx); | |
94 | static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
95 | static Mnode *add_minipool_forward_ref (Mfix *); | |
96 | static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
97 | static Mnode *add_minipool_backward_ref (Mfix *); | |
98 | static void assign_minipool_offsets (Mfix *); | |
99 | static void arm_print_value (FILE *, rtx); | |
100 | static void dump_minipool (rtx); | |
101 | static int arm_barrier_cost (rtx); | |
102 | static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); | |
103 | static void push_minipool_barrier (rtx, HOST_WIDE_INT); | |
104 | static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, | |
105 | rtx); | |
106 | static void arm_reorg (void); | |
107 | static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); | |
e32bac5b RE |
108 | static unsigned long arm_compute_save_reg0_reg12_mask (void); |
109 | static unsigned long arm_compute_save_reg_mask (void); | |
110 | static unsigned long arm_isr_value (tree); | |
111 | static unsigned long arm_compute_func_type (void); | |
112 | static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); | |
113 | static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); | |
7bff66a7 | 114 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 | 115 | static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); |
7bff66a7 | 116 | #endif |
e32bac5b RE |
117 | static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); |
118 | static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); | |
5b3e6663 | 119 | static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT); |
3101faab | 120 | static int arm_comp_type_attributes (const_tree, const_tree); |
e32bac5b RE |
121 | static void arm_set_default_type_attributes (tree); |
122 | static int arm_adjust_cost (rtx, rtx, rtx, int); | |
e32bac5b RE |
123 | static int count_insns_for_constant (HOST_WIDE_INT, int); |
124 | static int arm_get_strip_length (int); | |
125 | static bool arm_function_ok_for_sibcall (tree, tree); | |
126 | static void arm_internal_label (FILE *, const char *, unsigned long); | |
127 | static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, | |
128 | tree); | |
d5a0a47b RE |
129 | static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool); |
130 | static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); | |
131 | static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
132 | static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
133 | static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
134 | static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
f40751dd JH |
135 | static bool arm_rtx_costs (rtx, int, int, int *, bool); |
136 | static int arm_address_cost (rtx, bool); | |
e32bac5b RE |
137 | static bool arm_memory_load_p (rtx); |
138 | static bool arm_cirrus_insn_p (rtx); | |
139 | static void cirrus_reorg (rtx); | |
5a9335ef NC |
140 | static void arm_init_builtins (void); |
141 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
142 | static void arm_init_iwmmxt_builtins (void); | |
143 | static rtx safe_vector_operand (rtx, enum machine_mode); | |
144 | static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); | |
145 | static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); | |
146 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
a406f566 | 147 | static void emit_constant_insn (rtx cond, rtx pattern); |
d66437c5 | 148 | static rtx emit_set_insn (rtx, rtx); |
78a52f11 RH |
149 | static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
150 | tree, bool); | |
5a9335ef | 151 | |
7abc66b1 | 152 | #ifdef OBJECT_FORMAT_ELF |
9403b7f7 RS |
153 | static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; |
154 | static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; | |
7abc66b1 | 155 | #endif |
fb49053f | 156 | #ifndef ARM_PE |
e32bac5b | 157 | static void arm_encode_section_info (tree, rtx, int); |
fb49053f | 158 | #endif |
b12a00f1 RE |
159 | |
160 | static void arm_file_end (void); | |
6c6aa1af | 161 | static void arm_file_start (void); |
b12a00f1 | 162 | |
1cc9f5f5 KH |
163 | static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, |
164 | tree, int *, int); | |
8cd5a4e0 | 165 | static bool arm_pass_by_reference (CUMULATIVE_ARGS *, |
586de218 KG |
166 | enum machine_mode, const_tree, bool); |
167 | static bool arm_promote_prototypes (const_tree); | |
6b045785 | 168 | static bool arm_default_short_enums (void); |
13c1cd82 | 169 | static bool arm_align_anon_bitfield (void); |
586de218 KG |
170 | static bool arm_return_in_msb (const_tree); |
171 | static bool arm_must_pass_in_stack (enum machine_mode, const_tree); | |
23668cf7 | 172 | static bool arm_return_in_memory (const_tree, const_tree); |
617a1b71 PB |
173 | #ifdef TARGET_UNWIND_INFO |
174 | static void arm_unwind_emit (FILE *, rtx); | |
175 | static bool arm_output_ttype (rtx); | |
176 | #endif | |
5b3e6663 | 177 | static void arm_dwarf_handle_frame_unspec (const char *, rtx, int); |
c237e94a | 178 | |
4185ae53 PB |
179 | static tree arm_cxx_guard_type (void); |
180 | static bool arm_cxx_guard_mask_bit (void); | |
46e995e0 PB |
181 | static tree arm_get_cookie_size (tree); |
182 | static bool arm_cookie_has_size (void); | |
44d10c10 | 183 | static bool arm_cxx_cdtor_returns_this (void); |
505970fc | 184 | static bool arm_cxx_key_method_may_be_inline (void); |
1e731102 MM |
185 | static void arm_cxx_determine_class_data_visibility (tree); |
186 | static bool arm_cxx_class_data_always_comdat (void); | |
9f62c3e3 | 187 | static bool arm_cxx_use_aeabi_atexit (void); |
b3f8d95d | 188 | static void arm_init_libfuncs (void); |
07d8efe3 MM |
189 | static tree arm_build_builtin_va_list (void); |
190 | static void arm_expand_builtin_va_start (tree, rtx); | |
ae46a823 | 191 | static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
c54c7322 | 192 | static bool arm_handle_option (size_t, const char *, int); |
67e6ba46 | 193 | static void arm_target_help (void); |
273a2526 | 194 | static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); |
d3585b76 DJ |
195 | static bool arm_cannot_copy_insn_p (rtx); |
196 | static bool arm_tls_symbol_p (rtx x); | |
bd4dc3cd | 197 | static int arm_issue_rate (void); |
afcc986d | 198 | static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
007e61c2 | 199 | static bool arm_allocate_stack_slots_for_args (void); |
d3585b76 | 200 | |
672a6f42 NB |
201 | \f |
202 | /* Initialize the GCC target structure. */ | |
b2ca3702 | 203 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
1d6e90ac | 204 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
672a6f42 NB |
205 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes |
206 | #endif | |
f3bb6135 | 207 | |
1d6e90ac | 208 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 209 | #define TARGET_ATTRIBUTE_TABLE arm_attribute_table |
672a6f42 | 210 | |
6c6aa1af PB |
211 | #undef TARGET_ASM_FILE_START |
212 | #define TARGET_ASM_FILE_START arm_file_start | |
b12a00f1 RE |
213 | #undef TARGET_ASM_FILE_END |
214 | #define TARGET_ASM_FILE_END arm_file_end | |
215 | ||
1d6e90ac | 216 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 217 | #define TARGET_ASM_ALIGNED_SI_OP NULL |
1d6e90ac | 218 | #undef TARGET_ASM_INTEGER |
301d03af | 219 | #define TARGET_ASM_INTEGER arm_assemble_integer |
301d03af | 220 | |
1d6e90ac | 221 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 NB |
222 | #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue |
223 | ||
1d6e90ac | 224 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
225 | #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue |
226 | ||
c54c7322 RS |
227 | #undef TARGET_DEFAULT_TARGET_FLAGS |
228 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG) | |
229 | #undef TARGET_HANDLE_OPTION | |
230 | #define TARGET_HANDLE_OPTION arm_handle_option | |
67e6ba46 NC |
231 | #undef TARGET_HELP |
232 | #define TARGET_HELP arm_target_help | |
c54c7322 | 233 | |
1d6e90ac | 234 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
8d8e52be JM |
235 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes |
236 | ||
1d6e90ac | 237 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
8d8e52be JM |
238 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes |
239 | ||
1d6e90ac | 240 | #undef TARGET_SCHED_ADJUST_COST |
c237e94a ZW |
241 | #define TARGET_SCHED_ADJUST_COST arm_adjust_cost |
242 | ||
fb49053f RH |
243 | #undef TARGET_ENCODE_SECTION_INFO |
244 | #ifdef ARM_PE | |
245 | #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info | |
246 | #else | |
247 | #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info | |
248 | #endif | |
249 | ||
5a9335ef | 250 | #undef TARGET_STRIP_NAME_ENCODING |
772c5265 RH |
251 | #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding |
252 | ||
5a9335ef | 253 | #undef TARGET_ASM_INTERNAL_LABEL |
4977bab6 ZW |
254 | #define TARGET_ASM_INTERNAL_LABEL arm_internal_label |
255 | ||
5a9335ef | 256 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
4977bab6 ZW |
257 | #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall |
258 | ||
5a9335ef | 259 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
c590b625 | 260 | #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk |
5a9335ef | 261 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3961e8fe | 262 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
c590b625 | 263 | |
5a9335ef | 264 | #undef TARGET_RTX_COSTS |
f40751dd | 265 | #define TARGET_RTX_COSTS arm_rtx_costs |
5a9335ef | 266 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 267 | #define TARGET_ADDRESS_COST arm_address_cost |
3c50106f | 268 | |
273a2526 RS |
269 | #undef TARGET_SHIFT_TRUNCATION_MASK |
270 | #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask | |
f676971a EC |
271 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
272 | #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p | |
273 | ||
5a9335ef | 274 | #undef TARGET_MACHINE_DEPENDENT_REORG |
18dbd950 RS |
275 | #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg |
276 | ||
5a9335ef NC |
277 | #undef TARGET_INIT_BUILTINS |
278 | #define TARGET_INIT_BUILTINS arm_init_builtins | |
279 | #undef TARGET_EXPAND_BUILTIN | |
280 | #define TARGET_EXPAND_BUILTIN arm_expand_builtin | |
281 | ||
b3f8d95d MM |
282 | #undef TARGET_INIT_LIBFUNCS |
283 | #define TARGET_INIT_LIBFUNCS arm_init_libfuncs | |
284 | ||
f9ba5949 | 285 | #undef TARGET_PROMOTE_FUNCTION_ARGS |
586de218 | 286 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true |
d4453b7a | 287 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
586de218 | 288 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true |
f9ba5949 | 289 | #undef TARGET_PROMOTE_PROTOTYPES |
70301b45 | 290 | #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes |
8cd5a4e0 RH |
291 | #undef TARGET_PASS_BY_REFERENCE |
292 | #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference | |
78a52f11 RH |
293 | #undef TARGET_ARG_PARTIAL_BYTES |
294 | #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes | |
f9ba5949 | 295 | |
1cc9f5f5 KH |
296 | #undef TARGET_SETUP_INCOMING_VARARGS |
297 | #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs | |
298 | ||
007e61c2 PB |
299 | #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS |
300 | #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args | |
301 | ||
6b045785 PB |
302 | #undef TARGET_DEFAULT_SHORT_ENUMS |
303 | #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums | |
304 | ||
13c1cd82 PB |
305 | #undef TARGET_ALIGN_ANON_BITFIELD |
306 | #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield | |
307 | ||
c2a64439 PB |
308 | #undef TARGET_NARROW_VOLATILE_BITFIELD |
309 | #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false | |
310 | ||
4185ae53 PB |
311 | #undef TARGET_CXX_GUARD_TYPE |
312 | #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type | |
313 | ||
314 | #undef TARGET_CXX_GUARD_MASK_BIT | |
315 | #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit | |
316 | ||
46e995e0 PB |
317 | #undef TARGET_CXX_GET_COOKIE_SIZE |
318 | #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size | |
319 | ||
320 | #undef TARGET_CXX_COOKIE_HAS_SIZE | |
321 | #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size | |
322 | ||
44d10c10 PB |
323 | #undef TARGET_CXX_CDTOR_RETURNS_THIS |
324 | #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this | |
325 | ||
505970fc MM |
326 | #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE |
327 | #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline | |
328 | ||
9f62c3e3 PB |
329 | #undef TARGET_CXX_USE_AEABI_ATEXIT |
330 | #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit | |
331 | ||
1e731102 MM |
332 | #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY |
333 | #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \ | |
334 | arm_cxx_determine_class_data_visibility | |
335 | ||
336 | #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT | |
337 | #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat | |
505970fc | 338 | |
866af8a9 JB |
339 | #undef TARGET_RETURN_IN_MSB |
340 | #define TARGET_RETURN_IN_MSB arm_return_in_msb | |
341 | ||
23668cf7 CLT |
342 | #undef TARGET_RETURN_IN_MEMORY |
343 | #define TARGET_RETURN_IN_MEMORY arm_return_in_memory | |
344 | ||
866af8a9 JB |
345 | #undef TARGET_MUST_PASS_IN_STACK |
346 | #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack | |
347 | ||
617a1b71 PB |
348 | #ifdef TARGET_UNWIND_INFO |
349 | #undef TARGET_UNWIND_EMIT | |
350 | #define TARGET_UNWIND_EMIT arm_unwind_emit | |
351 | ||
352 | /* EABI unwinding tables use a different format for the typeinfo tables. */ | |
353 | #undef TARGET_ASM_TTYPE | |
354 | #define TARGET_ASM_TTYPE arm_output_ttype | |
355 | ||
356 | #undef TARGET_ARM_EABI_UNWINDER | |
357 | #define TARGET_ARM_EABI_UNWINDER true | |
358 | #endif /* TARGET_UNWIND_INFO */ | |
359 | ||
5b3e6663 PB |
360 | #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC |
361 | #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec | |
362 | ||
d3585b76 DJ |
363 | #undef TARGET_CANNOT_COPY_INSN_P |
364 | #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p | |
365 | ||
366 | #ifdef HAVE_AS_TLS | |
367 | #undef TARGET_HAVE_TLS | |
368 | #define TARGET_HAVE_TLS true | |
369 | #endif | |
370 | ||
371 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
8426b956 | 372 | #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem |
d3585b76 | 373 | |
f67358da PB |
374 | #undef TARGET_MAX_ANCHOR_OFFSET |
375 | #define TARGET_MAX_ANCHOR_OFFSET 4095 | |
376 | ||
377 | /* The minimum is set such that the total size of the block | |
378 | for a particular anchor is -4088 + 1 + 4095 bytes, which is | |
379 | divisible by eight, ensuring natural spacing of anchors. */ | |
380 | #undef TARGET_MIN_ANCHOR_OFFSET | |
381 | #define TARGET_MIN_ANCHOR_OFFSET -4088 | |
382 | ||
bd4dc3cd PB |
383 | #undef TARGET_SCHED_ISSUE_RATE |
384 | #define TARGET_SCHED_ISSUE_RATE arm_issue_rate | |
385 | ||
608063c3 JB |
386 | #undef TARGET_MANGLE_TYPE |
387 | #define TARGET_MANGLE_TYPE arm_mangle_type | |
388 | ||
07d8efe3 MM |
389 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
390 | #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list | |
391 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
392 | #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start | |
393 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR | |
394 | #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr | |
395 | ||
afcc986d JM |
396 | #ifdef HAVE_AS_TLS |
397 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
398 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel | |
399 | #endif | |
400 | ||
f6897b10 | 401 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 402 | \f |
c7319d87 RE |
403 | /* Obstack for minipool constant handling. */ |
404 | static struct obstack minipool_obstack; | |
1d6e90ac | 405 | static char * minipool_startobj; |
c7319d87 | 406 | |
1d6e90ac NC |
407 | /* The maximum number of insns skipped which |
408 | will be conditionalised if possible. */ | |
c27ba912 DM |
409 | static int max_insns_skipped = 5; |
410 | ||
411 | extern FILE * asm_out_file; | |
412 | ||
6354dc9b | 413 | /* True if we are currently building a constant table. */ |
13bd191d PB |
414 | int making_const_table; |
415 | ||
60d0536b | 416 | /* Define the information needed to generate branch insns. This is |
6354dc9b | 417 | stored from the compare operation. */ |
ff9940b0 | 418 | rtx arm_compare_op0, arm_compare_op1; |
ff9940b0 | 419 | |
9b66ebb1 PB |
420 | /* The processor for which instructions should be scheduled. */ |
421 | enum processor_type arm_tune = arm_none; | |
422 | ||
2f8e468b | 423 | /* The default processor used if not overridden by commandline. */ |
6c6aa1af PB |
424 | static enum processor_type arm_default_cpu = arm_none; |
425 | ||
9b66ebb1 PB |
426 | /* Which floating point model to use. */ |
427 | enum arm_fp_model arm_fp_model; | |
bee06f3d | 428 | |
9b66ebb1 | 429 | /* Which floating point hardware is available. */ |
29ad9694 | 430 | enum fputype arm_fpu_arch; |
b111229a | 431 | |
9b66ebb1 PB |
432 | /* Which floating point hardware to schedule for. */ |
433 | enum fputype arm_fpu_tune; | |
434 | ||
435 | /* Whether to use floating point hardware. */ | |
436 | enum float_abi_type arm_float_abi; | |
437 | ||
5848830f PB |
438 | /* Which ABI to use. */ |
439 | enum arm_abi_type arm_abi; | |
440 | ||
d3585b76 DJ |
441 | /* Which thread pointer model to use. */ |
442 | enum arm_tp_type target_thread_pointer = TP_AUTO; | |
443 | ||
b355a481 | 444 | /* Used to parse -mstructure_size_boundary command line option. */ |
723ae7c1 | 445 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 446 | |
b12a00f1 | 447 | /* Used for Thumb call_via trampolines. */ |
57ecec57 | 448 | rtx thumb_call_via_label[14]; |
b12a00f1 RE |
449 | static int thumb_call_reg_needed; |
450 | ||
aec3cfba | 451 | /* Bit values used to identify processor capabilities. */ |
62b10bbc | 452 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
9b66ebb1 | 453 | #define FL_ARCH3M (1 << 1) /* Extended multiply */ |
62b10bbc NC |
454 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ |
455 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
456 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
457 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
458 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
459 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
460 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
6bc82793 | 461 | #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ |
d19fb8e3 | 462 | #define FL_XSCALE (1 << 10) /* XScale */ |
9b6b54e2 | 463 | #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ |
9b66ebb1 | 464 | #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds |
81f9037c MM |
465 | media instructions. */ |
466 | #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ | |
abac3b49 RE |
467 | #define FL_WBUF (1 << 14) /* Schedule for write buffer ops. |
468 | Note: ARM6 & 7 derivatives only. */ | |
d3585b76 | 469 | #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ |
5b3e6663 PB |
470 | #define FL_THUMB2 (1 << 16) /* Thumb-2. */ |
471 | #define FL_NOTM (1 << 17) /* Instructions not present in the 'M' | |
472 | profile. */ | |
7a085dce | 473 | #define FL_DIV (1 << 18) /* Hardware divide. */ |
f1adb0a9 | 474 | #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ |
88f77cba | 475 | #define FL_NEON (1 << 20) /* Neon instructions. */ |
aec3cfba | 476 | |
9b66ebb1 PB |
477 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ |
478 | ||
5b3e6663 PB |
479 | #define FL_FOR_ARCH2 FL_NOTM |
480 | #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) | |
78011587 PB |
481 | #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) |
482 | #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) | |
483 | #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) | |
484 | #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) | |
485 | #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) | |
486 | #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) | |
487 | #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) | |
488 | #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE | |
489 | #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) | |
490 | #define FL_FOR_ARCH6J FL_FOR_ARCH6 | |
d3585b76 | 491 | #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) |
fa91adc6 | 492 | #define FL_FOR_ARCH6Z FL_FOR_ARCH6 |
d3585b76 | 493 | #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K |
5b3e6663 | 494 | #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) |
bf98ec6c | 495 | #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) |
5b3e6663 PB |
496 | #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM) |
497 | #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM) | |
498 | #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) | |
499 | #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) | |
78011587 | 500 | |
1d6e90ac NC |
501 | /* The bits in this mask specify which |
502 | instructions we are allowed to generate. */ | |
0977774b | 503 | static unsigned long insn_flags = 0; |
d5b7b3ae | 504 | |
aec3cfba | 505 | /* The bits in this mask specify which instruction scheduling options should |
9b66ebb1 | 506 | be used. */ |
0977774b | 507 | static unsigned long tune_flags = 0; |
aec3cfba NC |
508 | |
509 | /* The following are used in the arm.md file as equivalents to bits | |
510 | in the above two flag variables. */ | |
511 | ||
9b66ebb1 PB |
512 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
513 | int arm_arch3m = 0; | |
2b835d68 | 514 | |
6354dc9b | 515 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
516 | int arm_arch4 = 0; |
517 | ||
68d560d4 RE |
518 | /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ |
519 | int arm_arch4t = 0; | |
520 | ||
6354dc9b | 521 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
522 | int arm_arch5 = 0; |
523 | ||
b15bca31 RE |
524 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
525 | int arm_arch5e = 0; | |
526 | ||
9b66ebb1 PB |
527 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
528 | int arm_arch6 = 0; | |
529 | ||
d3585b76 DJ |
530 | /* Nonzero if this chip supports the ARM 6K extensions. */ |
531 | int arm_arch6k = 0; | |
532 | ||
5b3e6663 PB |
533 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
534 | int arm_arch_notm = 0; | |
535 | ||
aec3cfba | 536 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
537 | int arm_ld_sched = 0; |
538 | ||
539 | /* Nonzero if this chip is a StrongARM. */ | |
abac3b49 | 540 | int arm_tune_strongarm = 0; |
f5a1b0d2 | 541 | |
78011587 PB |
542 | /* Nonzero if this chip is a Cirrus variant. */ |
543 | int arm_arch_cirrus = 0; | |
544 | ||
5a9335ef NC |
545 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ |
546 | int arm_arch_iwmmxt = 0; | |
547 | ||
d19fb8e3 | 548 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
549 | int arm_arch_xscale = 0; |
550 | ||
551 | /* Nonzero if tuning for XScale */ | |
552 | int arm_tune_xscale = 0; | |
d19fb8e3 | 553 | |
e0b92319 | 554 | /* Nonzero if we want to tune for stores that access the write-buffer. |
c5d34bb2 | 555 | This typically means an ARM6 or ARM7 with MMU or MPU. */ |
abac3b49 | 556 | int arm_tune_wbuf = 0; |
b111229a | 557 | |
7612f14d PB |
558 | /* Nonzero if tuning for Cortex-A9. */ |
559 | int arm_tune_cortex_a9 = 0; | |
560 | ||
0616531f RE |
561 | /* Nonzero if generating Thumb instructions. */ |
562 | int thumb_code = 0; | |
563 | ||
2ad4dcf9 | 564 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 565 | preprocessor. |
2ad4dcf9 RE |
566 | XXX This is a bit of a hack, it's intended to help work around |
567 | problems in GLD which doesn't understand that armv5t code is | |
568 | interworking clean. */ | |
569 | int arm_cpp_interwork = 0; | |
570 | ||
5b3e6663 PB |
571 | /* Nonzero if chip supports Thumb 2. */ |
572 | int arm_arch_thumb2; | |
573 | ||
574 | /* Nonzero if chip supports integer division instruction. */ | |
575 | int arm_arch_hwdiv; | |
576 | ||
cce8749e CH |
577 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we |
578 | must report the mode of the memory reference from PRINT_OPERAND to | |
579 | PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 580 | enum machine_mode output_memory_reference_mode; |
cce8749e | 581 | |
32de079a | 582 | /* The register number to be used for the PIC offset register. */ |
020a4035 | 583 | unsigned arm_pic_register = INVALID_REGNUM; |
32de079a | 584 | |
aec3cfba NC |
585 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
586 | the next function. */ | |
4b632bf1 RE |
587 | static int after_arm_reorg = 0; |
588 | ||
aec3cfba | 589 | /* The maximum number of insns to be used when loading a constant. */ |
2b835d68 RE |
590 | static int arm_constant_limit = 3; |
591 | ||
cce8749e CH |
592 | /* For an explanation of these variables, see final_prescan_insn below. */ |
593 | int arm_ccfsm_state; | |
5b3e6663 | 594 | /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */ |
84ed5e79 | 595 | enum arm_cond_code arm_current_cc; |
cce8749e CH |
596 | rtx arm_target_insn; |
597 | int arm_target_label; | |
5b3e6663 PB |
598 | /* The number of conditionally executed insns, including the current insn. */ |
599 | int arm_condexec_count = 0; | |
600 | /* A bitmask specifying the patterns for the IT block. | |
601 | Zero means do not output an IT block before this insn. */ | |
602 | int arm_condexec_mask = 0; | |
603 | /* The number of bits used in arm_condexec_mask. */ | |
604 | int arm_condexec_masklen = 0; | |
9997d19d RE |
605 | |
606 | /* The condition codes of the ARM, and the inverse function. */ | |
1d6e90ac | 607 | static const char * const arm_condition_codes[] = |
9997d19d RE |
608 | { |
609 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
610 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
611 | }; | |
612 | ||
5b3e6663 | 613 | #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl") |
f5a1b0d2 | 614 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
5b3e6663 PB |
615 | |
616 | #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \ | |
617 | | (1 << SP_REGNUM) | (1 << PC_REGNUM) \ | |
618 | | (1 << PIC_OFFSET_TABLE_REGNUM))) | |
2b835d68 | 619 | \f |
6354dc9b | 620 | /* Initialization code. */ |
2b835d68 | 621 | |
2b835d68 RE |
622 | struct processors |
623 | { | |
8b60264b | 624 | const char *const name; |
9b66ebb1 | 625 | enum processor_type core; |
78011587 | 626 | const char *arch; |
0977774b | 627 | const unsigned long flags; |
d5a0a47b | 628 | bool (* rtx_costs) (rtx, enum rtx_code, enum rtx_code, int *, bool); |
2b835d68 RE |
629 | }; |
630 | ||
631 | /* Not all of these give usefully different compilation alternatives, | |
632 | but there is no simple way of generalizing them. */ | |
8b60264b | 633 | static const struct processors all_cores[] = |
f5a1b0d2 NC |
634 | { |
635 | /* ARM Cores */ | |
d98a72fd RE |
636 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ |
637 | {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, | |
9b66ebb1 PB |
638 | #include "arm-cores.def" |
639 | #undef ARM_CORE | |
78011587 | 640 | {NULL, arm_none, NULL, 0, NULL} |
f5a1b0d2 NC |
641 | }; |
642 | ||
8b60264b | 643 | static const struct processors all_architectures[] = |
2b835d68 | 644 | { |
f5a1b0d2 | 645 | /* ARM Architectures */ |
9b66ebb1 PB |
646 | /* We don't specify rtx_costs here as it will be figured out |
647 | from the core. */ | |
f676971a | 648 | |
78011587 PB |
649 | {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, |
650 | {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, | |
651 | {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, | |
652 | {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, | |
653 | {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, | |
b111229a RE |
654 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
655 | implementations that support it, so we will leave it out for now. */ | |
78011587 PB |
656 | {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, |
657 | {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, | |
658 | {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, | |
659 | {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, | |
660 | {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, | |
661 | {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, | |
662 | {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, | |
fa91adc6 PB |
663 | {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL}, |
664 | {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL}, | |
665 | {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL}, | |
5b3e6663 | 666 | {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL}, |
bf98ec6c | 667 | {"armv6-m", cortexm1, "6M", FL_FOR_ARCH6M, NULL}, |
5b3e6663 PB |
668 | {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL}, |
669 | {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL}, | |
670 | {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL}, | |
671 | {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL}, | |
78011587 PB |
672 | {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, |
673 | {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, | |
442dc742 | 674 | {"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, |
78011587 | 675 | {NULL, arm_none, NULL, 0 , NULL} |
f5a1b0d2 NC |
676 | }; |
677 | ||
c54c7322 RS |
678 | struct arm_cpu_select |
679 | { | |
680 | const char * string; | |
681 | const char * name; | |
682 | const struct processors * processors; | |
683 | }; | |
684 | ||
9a9f7594 | 685 | /* This is a magic structure. The 'string' field is magically filled in |
f5a1b0d2 NC |
686 | with a pointer to the value specified by the user on the command line |
687 | assuming that the user has specified such a value. */ | |
688 | ||
c54c7322 | 689 | static struct arm_cpu_select arm_select[] = |
f5a1b0d2 | 690 | { |
f676971a | 691 | /* string name processors */ |
f5a1b0d2 NC |
692 | { NULL, "-mcpu=", all_cores }, |
693 | { NULL, "-march=", all_architectures }, | |
694 | { NULL, "-mtune=", all_cores } | |
2b835d68 RE |
695 | }; |
696 | ||
e6fffade RE |
697 | /* Defines representing the indexes into the above table. */ |
698 | #define ARM_OPT_SET_CPU 0 | |
699 | #define ARM_OPT_SET_ARCH 1 | |
700 | #define ARM_OPT_SET_TUNE 2 | |
78011587 | 701 | |
afc0a4ba | 702 | /* The name of the preprocessor macro to define for this architecture. */ |
78011587 PB |
703 | |
704 | char arm_arch_name[] = "__ARM_ARCH_0UNK__"; | |
705 | ||
9b66ebb1 PB |
706 | struct fpu_desc |
707 | { | |
708 | const char * name; | |
709 | enum fputype fpu; | |
710 | }; | |
711 | ||
712 | ||
56f42830 | 713 | /* Available values for -mfpu=. */ |
9b66ebb1 PB |
714 | |
715 | static const struct fpu_desc all_fpus[] = | |
716 | { | |
717 | {"fpa", FPUTYPE_FPA}, | |
718 | {"fpe2", FPUTYPE_FPA_EMU2}, | |
719 | {"fpe3", FPUTYPE_FPA_EMU2}, | |
720 | {"maverick", FPUTYPE_MAVERICK}, | |
f1adb0a9 JB |
721 | {"vfp", FPUTYPE_VFP}, |
722 | {"vfp3", FPUTYPE_VFP3}, | |
302c3d8e PB |
723 | {"vfpv3", FPUTYPE_VFP3}, |
724 | {"vfpv3-d16", FPUTYPE_VFP3D16}, | |
88f77cba | 725 | {"neon", FPUTYPE_NEON} |
9b66ebb1 PB |
726 | }; |
727 | ||
728 | ||
729 | /* Floating point models used by the different hardware. | |
730 | See fputype in arm.h. */ | |
731 | ||
732 | static const enum fputype fp_model_for_fpu[] = | |
733 | { | |
734 | /* No FP hardware. */ | |
735 | ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */ | |
736 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */ | |
737 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */ | |
738 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */ | |
739 | ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */ | |
f1adb0a9 | 740 | ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */ |
302c3d8e | 741 | ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3D16 */ |
88f77cba JB |
742 | ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3 */ |
743 | ARM_FP_MODEL_VFP /* FPUTYPE_NEON */ | |
9b66ebb1 PB |
744 | }; |
745 | ||
746 | ||
747 | struct float_abi | |
748 | { | |
749 | const char * name; | |
750 | enum float_abi_type abi_type; | |
751 | }; | |
752 | ||
753 | ||
754 | /* Available values for -mfloat-abi=. */ | |
755 | ||
756 | static const struct float_abi all_float_abis[] = | |
757 | { | |
758 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
759 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
760 | {"hard", ARM_FLOAT_ABI_HARD} | |
761 | }; | |
762 | ||
763 | ||
5848830f PB |
764 | struct abi_name |
765 | { | |
766 | const char *name; | |
767 | enum arm_abi_type abi_type; | |
768 | }; | |
769 | ||
770 | ||
771 | /* Available values for -mabi=. */ | |
772 | ||
773 | static const struct abi_name arm_all_abis[] = | |
774 | { | |
775 | {"apcs-gnu", ARM_ABI_APCS}, | |
776 | {"atpcs", ARM_ABI_ATPCS}, | |
777 | {"aapcs", ARM_ABI_AAPCS}, | |
077fc835 KH |
778 | {"iwmmxt", ARM_ABI_IWMMXT}, |
779 | {"aapcs-linux", ARM_ABI_AAPCS_LINUX} | |
5848830f PB |
780 | }; |
781 | ||
d3585b76 DJ |
782 | /* Supported TLS relocations. */ |
783 | ||
784 | enum tls_reloc { | |
785 | TLS_GD32, | |
786 | TLS_LDM32, | |
787 | TLS_LDO32, | |
788 | TLS_IE32, | |
789 | TLS_LE32 | |
790 | }; | |
791 | ||
d66437c5 RE |
792 | /* Emit an insn that's a simple single-set. Both the operands must be known |
793 | to be valid. */ | |
794 | inline static rtx | |
795 | emit_set_insn (rtx x, rtx y) | |
796 | { | |
797 | return emit_insn (gen_rtx_SET (VOIDmode, x, y)); | |
798 | } | |
799 | ||
0977774b JT |
800 | /* Return the number of bits set in VALUE. */ |
801 | static unsigned | |
e32bac5b | 802 | bit_count (unsigned long value) |
aec3cfba | 803 | { |
d5b7b3ae | 804 | unsigned long count = 0; |
f676971a | 805 | |
aec3cfba NC |
806 | while (value) |
807 | { | |
0977774b JT |
808 | count++; |
809 | value &= value - 1; /* Clear the least-significant set bit. */ | |
aec3cfba NC |
810 | } |
811 | ||
812 | return count; | |
813 | } | |
814 | ||
c112cf2b | 815 | /* Set up library functions unique to ARM. */ |
b3f8d95d MM |
816 | |
817 | static void | |
818 | arm_init_libfuncs (void) | |
819 | { | |
820 | /* There are no special library functions unless we are using the | |
821 | ARM BPABI. */ | |
822 | if (!TARGET_BPABI) | |
823 | return; | |
824 | ||
825 | /* The functions below are described in Section 4 of the "Run-Time | |
826 | ABI for the ARM architecture", Version 1.0. */ | |
827 | ||
828 | /* Double-precision floating-point arithmetic. Table 2. */ | |
829 | set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd"); | |
830 | set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv"); | |
831 | set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul"); | |
832 | set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg"); | |
833 | set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub"); | |
834 | ||
c112cf2b | 835 | /* Double-precision comparisons. Table 3. */ |
b3f8d95d MM |
836 | set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq"); |
837 | set_optab_libfunc (ne_optab, DFmode, NULL); | |
838 | set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt"); | |
839 | set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple"); | |
840 | set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge"); | |
841 | set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt"); | |
842 | set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun"); | |
843 | ||
844 | /* Single-precision floating-point arithmetic. Table 4. */ | |
845 | set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd"); | |
846 | set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv"); | |
847 | set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul"); | |
848 | set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg"); | |
849 | set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub"); | |
f676971a | 850 | |
c112cf2b | 851 | /* Single-precision comparisons. Table 5. */ |
b3f8d95d MM |
852 | set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq"); |
853 | set_optab_libfunc (ne_optab, SFmode, NULL); | |
854 | set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt"); | |
855 | set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple"); | |
856 | set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge"); | |
857 | set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt"); | |
858 | set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun"); | |
859 | ||
860 | /* Floating-point to integer conversions. Table 6. */ | |
861 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz"); | |
862 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz"); | |
863 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz"); | |
864 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz"); | |
865 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz"); | |
866 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz"); | |
867 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz"); | |
868 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz"); | |
869 | ||
870 | /* Conversions between floating types. Table 7. */ | |
871 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f"); | |
872 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d"); | |
873 | ||
c112cf2b | 874 | /* Integer to floating-point conversions. Table 8. */ |
b3f8d95d MM |
875 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d"); |
876 | set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d"); | |
877 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d"); | |
878 | set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d"); | |
879 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f"); | |
880 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f"); | |
881 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f"); | |
882 | set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f"); | |
883 | ||
884 | /* Long long. Table 9. */ | |
885 | set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul"); | |
886 | set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod"); | |
887 | set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod"); | |
888 | set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl"); | |
889 | set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr"); | |
890 | set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr"); | |
891 | set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp"); | |
892 | set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp"); | |
893 | ||
894 | /* Integer (32/32->32) division. \S 4.3.1. */ | |
895 | set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod"); | |
896 | set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod"); | |
897 | ||
898 | /* The divmod functions are designed so that they can be used for | |
899 | plain division, even though they return both the quotient and the | |
900 | remainder. The quotient is returned in the usual location (i.e., | |
901 | r0 for SImode, {r0, r1} for DImode), just as would be expected | |
902 | for an ordinary division routine. Because the AAPCS calling | |
903 | conventions specify that all of { r0, r1, r2, r3 } are | |
904 | callee-saved registers, there is no need to tell the compiler | |
905 | explicitly that those registers are clobbered by these | |
906 | routines. */ | |
907 | set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod"); | |
908 | set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod"); | |
e993ba8f DJ |
909 | |
910 | /* For SImode division the ABI provides div-without-mod routines, | |
911 | which are faster. */ | |
912 | set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv"); | |
913 | set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv"); | |
01c19d47 PB |
914 | |
915 | /* We don't have mod libcalls. Fortunately gcc knows how to use the | |
916 | divmod libcalls instead. */ | |
917 | set_optab_libfunc (smod_optab, DImode, NULL); | |
918 | set_optab_libfunc (umod_optab, DImode, NULL); | |
919 | set_optab_libfunc (smod_optab, SImode, NULL); | |
920 | set_optab_libfunc (umod_optab, SImode, NULL); | |
b3f8d95d MM |
921 | } |
922 | ||
07d8efe3 MM |
923 | /* On AAPCS systems, this is the "struct __va_list". */ |
924 | static GTY(()) tree va_list_type; | |
925 | ||
926 | /* Return the type to use as __builtin_va_list. */ | |
927 | static tree | |
928 | arm_build_builtin_va_list (void) | |
929 | { | |
930 | tree va_list_name; | |
931 | tree ap_field; | |
932 | ||
933 | if (!TARGET_AAPCS_BASED) | |
934 | return std_build_builtin_va_list (); | |
935 | ||
936 | /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type | |
937 | defined as: | |
938 | ||
939 | struct __va_list | |
940 | { | |
941 | void *__ap; | |
942 | }; | |
943 | ||
944 | The C Library ABI further reinforces this definition in \S | |
945 | 4.1. | |
946 | ||
947 | We must follow this definition exactly. The structure tag | |
948 | name is visible in C++ mangled names, and thus forms a part | |
949 | of the ABI. The field name may be used by people who | |
950 | #include <stdarg.h>. */ | |
951 | /* Create the type. */ | |
952 | va_list_type = lang_hooks.types.make_type (RECORD_TYPE); | |
953 | /* Give it the required name. */ | |
954 | va_list_name = build_decl (TYPE_DECL, | |
955 | get_identifier ("__va_list"), | |
956 | va_list_type); | |
957 | DECL_ARTIFICIAL (va_list_name) = 1; | |
958 | TYPE_NAME (va_list_type) = va_list_name; | |
959 | /* Create the __ap field. */ | |
960 | ap_field = build_decl (FIELD_DECL, | |
961 | get_identifier ("__ap"), | |
962 | ptr_type_node); | |
963 | DECL_ARTIFICIAL (ap_field) = 1; | |
964 | DECL_FIELD_CONTEXT (ap_field) = va_list_type; | |
965 | TYPE_FIELDS (va_list_type) = ap_field; | |
966 | /* Compute its layout. */ | |
967 | layout_type (va_list_type); | |
968 | ||
969 | return va_list_type; | |
970 | } | |
971 | ||
972 | /* Return an expression of type "void *" pointing to the next | |
973 | available argument in a variable-argument list. VALIST is the | |
974 | user-level va_list object, of type __builtin_va_list. */ | |
975 | static tree | |
976 | arm_extract_valist_ptr (tree valist) | |
977 | { | |
978 | if (TREE_TYPE (valist) == error_mark_node) | |
979 | return error_mark_node; | |
980 | ||
981 | /* On an AAPCS target, the pointer is stored within "struct | |
982 | va_list". */ | |
983 | if (TARGET_AAPCS_BASED) | |
984 | { | |
985 | tree ap_field = TYPE_FIELDS (TREE_TYPE (valist)); | |
986 | valist = build3 (COMPONENT_REF, TREE_TYPE (ap_field), | |
987 | valist, ap_field, NULL_TREE); | |
988 | } | |
989 | ||
990 | return valist; | |
991 | } | |
992 | ||
993 | /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ | |
994 | static void | |
995 | arm_expand_builtin_va_start (tree valist, rtx nextarg) | |
996 | { | |
997 | valist = arm_extract_valist_ptr (valist); | |
998 | std_expand_builtin_va_start (valist, nextarg); | |
999 | } | |
1000 | ||
1001 | /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ | |
1002 | static tree | |
ae46a823 JM |
1003 | arm_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
1004 | gimple_seq *post_p) | |
07d8efe3 MM |
1005 | { |
1006 | valist = arm_extract_valist_ptr (valist); | |
1007 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); | |
1008 | } | |
1009 | ||
c54c7322 RS |
1010 | /* Implement TARGET_HANDLE_OPTION. */ |
1011 | ||
1012 | static bool | |
1013 | arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
1014 | { | |
1015 | switch (code) | |
1016 | { | |
c54c7322 RS |
1017 | case OPT_march_: |
1018 | arm_select[1].string = arg; | |
1019 | return true; | |
1020 | ||
1021 | case OPT_mcpu_: | |
1022 | arm_select[0].string = arg; | |
1023 | return true; | |
1024 | ||
c54c7322 RS |
1025 | case OPT_mhard_float: |
1026 | target_float_abi_name = "hard"; | |
1027 | return true; | |
1028 | ||
c54c7322 RS |
1029 | case OPT_msoft_float: |
1030 | target_float_abi_name = "soft"; | |
1031 | return true; | |
1032 | ||
c54c7322 RS |
1033 | case OPT_mtune_: |
1034 | arm_select[2].string = arg; | |
1035 | return true; | |
1036 | ||
1037 | default: | |
1038 | return true; | |
1039 | } | |
1040 | } | |
1041 | ||
67e6ba46 NC |
1042 | static void |
1043 | arm_target_help (void) | |
1044 | { | |
1045 | int i; | |
1046 | static int columns = 0; | |
1047 | int remaining; | |
1048 | ||
1049 | /* If we have not done so already, obtain the desired maximum width of | |
1050 | the output. Note - this is a duplication of the code at the start of | |
1051 | gcc/opts.c:print_specific_help() - the two copies should probably be | |
1052 | replaced by a single function. */ | |
1053 | if (columns == 0) | |
1054 | { | |
1055 | const char *p; | |
1056 | ||
1057 | GET_ENVIRONMENT (p, "COLUMNS"); | |
1058 | if (p != NULL) | |
1059 | { | |
1060 | int value = atoi (p); | |
1061 | ||
1062 | if (value > 0) | |
1063 | columns = value; | |
1064 | } | |
1065 | ||
1066 | if (columns == 0) | |
1067 | /* Use a reasonable default. */ | |
1068 | columns = 80; | |
1069 | } | |
1070 | ||
1071 | printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"); | |
1072 | ||
1073 | /* The - 2 is because we know that the last entry in the array is NULL. */ | |
1074 | i = ARRAY_SIZE (all_cores) - 2; | |
1075 | gcc_assert (i > 0); | |
1076 | printf (" %s", all_cores[i].name); | |
1077 | remaining = columns - (strlen (all_cores[i].name) + 4); | |
1078 | gcc_assert (remaining >= 0); | |
1079 | ||
1080 | while (i--) | |
1081 | { | |
1082 | int len = strlen (all_cores[i].name); | |
1083 | ||
1084 | if (remaining > len + 2) | |
1085 | { | |
1086 | printf (", %s", all_cores[i].name); | |
1087 | remaining -= len + 2; | |
1088 | } | |
1089 | else | |
1090 | { | |
1091 | if (remaining > 0) | |
1092 | printf (","); | |
1093 | printf ("\n %s", all_cores[i].name); | |
1094 | remaining = columns - (len + 4); | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | printf ("\n\n Known ARM architectures (for use with the -march= option):\n"); | |
1099 | ||
1100 | i = ARRAY_SIZE (all_architectures) - 2; | |
1101 | gcc_assert (i > 0); | |
1102 | ||
1103 | printf (" %s", all_architectures[i].name); | |
1104 | remaining = columns - (strlen (all_architectures[i].name) + 4); | |
1105 | gcc_assert (remaining >= 0); | |
1106 | ||
1107 | while (i--) | |
1108 | { | |
1109 | int len = strlen (all_architectures[i].name); | |
1110 | ||
1111 | if (remaining > len + 2) | |
1112 | { | |
1113 | printf (", %s", all_architectures[i].name); | |
1114 | remaining -= len + 2; | |
1115 | } | |
1116 | else | |
1117 | { | |
1118 | if (remaining > 0) | |
1119 | printf (","); | |
1120 | printf ("\n %s", all_architectures[i].name); | |
1121 | remaining = columns - (len + 4); | |
1122 | } | |
1123 | } | |
1124 | printf ("\n"); | |
1125 | ||
1126 | } | |
1127 | ||
2b835d68 RE |
1128 | /* Fix up any incompatible options that the user has specified. |
1129 | This has now turned into a maze. */ | |
1130 | void | |
e32bac5b | 1131 | arm_override_options (void) |
2b835d68 | 1132 | { |
ed4c4348 | 1133 | unsigned i; |
e6fffade | 1134 | enum processor_type target_arch_cpu = arm_none; |
5fd42423 | 1135 | enum processor_type selected_cpu = arm_none; |
9b66ebb1 | 1136 | |
f5a1b0d2 | 1137 | /* Set up the flags based on the cpu/architecture selected by the user. */ |
b6a1cbae | 1138 | for (i = ARRAY_SIZE (arm_select); i--;) |
bd9c7e23 | 1139 | { |
f5a1b0d2 | 1140 | struct arm_cpu_select * ptr = arm_select + i; |
f676971a | 1141 | |
f5a1b0d2 | 1142 | if (ptr->string != NULL && ptr->string[0] != '\0') |
bd9c7e23 | 1143 | { |
13bd191d | 1144 | const struct processors * sel; |
bd9c7e23 | 1145 | |
5895f793 | 1146 | for (sel = ptr->processors; sel->name != NULL; sel++) |
f5a1b0d2 | 1147 | if (streq (ptr->string, sel->name)) |
bd9c7e23 | 1148 | { |
78011587 | 1149 | /* Set the architecture define. */ |
e6fffade | 1150 | if (i != ARM_OPT_SET_TUNE) |
78011587 PB |
1151 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); |
1152 | ||
9b66ebb1 PB |
1153 | /* Determine the processor core for which we should |
1154 | tune code-generation. */ | |
1155 | if (/* -mcpu= is a sensible default. */ | |
e6fffade | 1156 | i == ARM_OPT_SET_CPU |
9b66ebb1 | 1157 | /* -mtune= overrides -mcpu= and -march=. */ |
e6fffade | 1158 | || i == ARM_OPT_SET_TUNE) |
9b66ebb1 PB |
1159 | arm_tune = (enum processor_type) (sel - ptr->processors); |
1160 | ||
e6fffade RE |
1161 | /* Remember the CPU associated with this architecture. |
1162 | If no other option is used to set the CPU type, | |
1163 | we'll use this to guess the most suitable tuning | |
1164 | options. */ | |
1165 | if (i == ARM_OPT_SET_ARCH) | |
1166 | target_arch_cpu = sel->core; | |
e0b92319 | 1167 | |
5fd42423 PB |
1168 | if (i == ARM_OPT_SET_CPU) |
1169 | selected_cpu = (enum processor_type) (sel - ptr->processors); | |
1170 | ||
e6fffade | 1171 | if (i != ARM_OPT_SET_TUNE) |
b111229a | 1172 | { |
aec3cfba NC |
1173 | /* If we have been given an architecture and a processor |
1174 | make sure that they are compatible. We only generate | |
1175 | a warning though, and we prefer the CPU over the | |
6354dc9b | 1176 | architecture. */ |
aec3cfba | 1177 | if (insn_flags != 0 && (insn_flags ^ sel->flags)) |
d4ee4d25 | 1178 | warning (0, "switch -mcpu=%s conflicts with -march= switch", |
aec3cfba | 1179 | ptr->string); |
f676971a | 1180 | |
aec3cfba | 1181 | insn_flags = sel->flags; |
b111229a | 1182 | } |
f676971a | 1183 | |
bd9c7e23 RE |
1184 | break; |
1185 | } | |
1186 | ||
1187 | if (sel->name == NULL) | |
1188 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
1189 | } | |
1190 | } | |
f676971a | 1191 | |
e6fffade RE |
1192 | /* Guess the tuning options from the architecture if necessary. */ |
1193 | if (arm_tune == arm_none) | |
1194 | arm_tune = target_arch_cpu; | |
1195 | ||
f5a1b0d2 | 1196 | /* If the user did not specify a processor, choose one for them. */ |
aec3cfba | 1197 | if (insn_flags == 0) |
f5a1b0d2 | 1198 | { |
8b60264b | 1199 | const struct processors * sel; |
aec3cfba | 1200 | unsigned int sought; |
aec3cfba | 1201 | |
5fd42423 PB |
1202 | selected_cpu = TARGET_CPU_DEFAULT; |
1203 | if (selected_cpu == arm_none) | |
78011587 PB |
1204 | { |
1205 | #ifdef SUBTARGET_CPU_DEFAULT | |
1206 | /* Use the subtarget default CPU if none was specified by | |
1207 | configure. */ | |
5fd42423 | 1208 | selected_cpu = SUBTARGET_CPU_DEFAULT; |
78011587 PB |
1209 | #endif |
1210 | /* Default to ARM6. */ | |
5fd42423 PB |
1211 | if (selected_cpu == arm_none) |
1212 | selected_cpu = arm6; | |
78011587 | 1213 | } |
5fd42423 | 1214 | sel = &all_cores[selected_cpu]; |
aec3cfba NC |
1215 | |
1216 | insn_flags = sel->flags; | |
9b66ebb1 | 1217 | |
aec3cfba NC |
1218 | /* Now check to see if the user has specified some command line |
1219 | switch that require certain abilities from the cpu. */ | |
1220 | sought = 0; | |
f676971a | 1221 | |
d5b7b3ae | 1222 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 1223 | { |
aec3cfba | 1224 | sought |= (FL_THUMB | FL_MODE32); |
f676971a | 1225 | |
d5b7b3ae | 1226 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
1227 | interworking. Therefore we force FL_MODE26 to be removed |
1228 | from insn_flags here (if it was set), so that the search | |
1229 | below will always be able to find a compatible processor. */ | |
5895f793 | 1230 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 1231 | } |
f676971a | 1232 | |
aec3cfba | 1233 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 1234 | { |
aec3cfba NC |
1235 | /* Try to locate a CPU type that supports all of the abilities |
1236 | of the default CPU, plus the extra abilities requested by | |
1237 | the user. */ | |
5895f793 | 1238 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 1239 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
1240 | break; |
1241 | ||
1242 | if (sel->name == NULL) | |
aec3cfba | 1243 | { |
0977774b | 1244 | unsigned current_bit_count = 0; |
8b60264b | 1245 | const struct processors * best_fit = NULL; |
f676971a | 1246 | |
aec3cfba NC |
1247 | /* Ideally we would like to issue an error message here |
1248 | saying that it was not possible to find a CPU compatible | |
1249 | with the default CPU, but which also supports the command | |
1250 | line options specified by the programmer, and so they | |
1251 | ought to use the -mcpu=<name> command line option to | |
1252 | override the default CPU type. | |
1253 | ||
61f0ccff RE |
1254 | If we cannot find a cpu that has both the |
1255 | characteristics of the default cpu and the given | |
1256 | command line options we scan the array again looking | |
1257 | for a best match. */ | |
5895f793 | 1258 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
1259 | if ((sel->flags & sought) == sought) |
1260 | { | |
0977774b | 1261 | unsigned count; |
aec3cfba NC |
1262 | |
1263 | count = bit_count (sel->flags & insn_flags); | |
1264 | ||
1265 | if (count >= current_bit_count) | |
1266 | { | |
1267 | best_fit = sel; | |
1268 | current_bit_count = count; | |
1269 | } | |
1270 | } | |
f5a1b0d2 | 1271 | |
e6d29d15 NS |
1272 | gcc_assert (best_fit); |
1273 | sel = best_fit; | |
aec3cfba NC |
1274 | } |
1275 | ||
1276 | insn_flags = sel->flags; | |
f5a1b0d2 | 1277 | } |
78011587 | 1278 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); |
6c6aa1af | 1279 | arm_default_cpu = (enum processor_type) (sel - all_cores); |
9b66ebb1 | 1280 | if (arm_tune == arm_none) |
6c6aa1af | 1281 | arm_tune = arm_default_cpu; |
f5a1b0d2 | 1282 | } |
f676971a | 1283 | |
9b66ebb1 PB |
1284 | /* The processor for which we should tune should now have been |
1285 | chosen. */ | |
e6d29d15 | 1286 | gcc_assert (arm_tune != arm_none); |
f676971a | 1287 | |
9b66ebb1 | 1288 | tune_flags = all_cores[(int)arm_tune].flags; |
e26053d1 | 1289 | |
26272ba2 PB |
1290 | if (target_abi_name) |
1291 | { | |
1292 | for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) | |
1293 | { | |
1294 | if (streq (arm_all_abis[i].name, target_abi_name)) | |
1295 | { | |
1296 | arm_abi = arm_all_abis[i].abi_type; | |
1297 | break; | |
1298 | } | |
1299 | } | |
1300 | if (i == ARRAY_SIZE (arm_all_abis)) | |
1301 | error ("invalid ABI option: -mabi=%s", target_abi_name); | |
1302 | } | |
1303 | else | |
1304 | arm_abi = ARM_DEFAULT_ABI; | |
1305 | ||
f5a1b0d2 NC |
1306 | /* Make sure that the processor choice does not conflict with any of the |
1307 | other command line choices. */ | |
5b3e6663 PB |
1308 | if (TARGET_ARM && !(insn_flags & FL_NOTM)) |
1309 | error ("target CPU does not support ARM mode"); | |
1310 | ||
26272ba2 PB |
1311 | /* BPABI targets use linker tricks to allow interworking on cores |
1312 | without thumb support. */ | |
1313 | if (TARGET_INTERWORK && !((insn_flags & FL_THUMB) || TARGET_BPABI)) | |
f5a1b0d2 | 1314 | { |
d4ee4d25 | 1315 | warning (0, "target CPU does not support interworking" ); |
c54c7322 | 1316 | target_flags &= ~MASK_INTERWORK; |
f5a1b0d2 | 1317 | } |
f676971a | 1318 | |
d5b7b3ae RE |
1319 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
1320 | { | |
d4ee4d25 | 1321 | warning (0, "target CPU does not support THUMB instructions"); |
c54c7322 | 1322 | target_flags &= ~MASK_THUMB; |
d5b7b3ae RE |
1323 | } |
1324 | ||
1325 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
1326 | { | |
d4ee4d25 | 1327 | /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */ |
c54c7322 | 1328 | target_flags &= ~MASK_APCS_FRAME; |
d5b7b3ae | 1329 | } |
d19fb8e3 | 1330 | |
da8ce8be RE |
1331 | /* Callee super interworking implies thumb interworking. Adding |
1332 | this to the flags here simplifies the logic elsewhere. */ | |
1333 | if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING) | |
1334 | target_flags |= MASK_INTERWORK; | |
1335 | ||
d5b7b3ae RE |
1336 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
1337 | from here where no function is being compiled currently. */ | |
c54c7322 | 1338 | if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM) |
d4ee4d25 | 1339 | warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1340 | |
1341 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
d4ee4d25 | 1342 | warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1343 | |
1344 | if (TARGET_ARM && TARGET_CALLER_INTERWORKING) | |
d4ee4d25 | 1345 | warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae | 1346 | |
5895f793 | 1347 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 | 1348 | { |
d4ee4d25 | 1349 | warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); |
c54c7322 | 1350 | target_flags |= MASK_APCS_FRAME; |
f5a1b0d2 | 1351 | } |
f676971a | 1352 | |
2b835d68 | 1353 | if (TARGET_POKE_FUNCTION_NAME) |
c54c7322 | 1354 | target_flags |= MASK_APCS_FRAME; |
f676971a | 1355 | |
2b835d68 | 1356 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 1357 | error ("-fpic and -mapcs-reent are incompatible"); |
f676971a | 1358 | |
2b835d68 | 1359 | if (TARGET_APCS_REENT) |
d4ee4d25 | 1360 | warning (0, "APCS reentrant code not supported. Ignored"); |
f676971a | 1361 | |
d5b7b3ae RE |
1362 | /* If this target is normally configured to use APCS frames, warn if they |
1363 | are turned off and debugging is turned on. */ | |
1364 | if (TARGET_ARM | |
1365 | && write_symbols != NO_DEBUG | |
5895f793 | 1366 | && !TARGET_APCS_FRAME |
c54c7322 | 1367 | && (TARGET_DEFAULT & MASK_APCS_FRAME)) |
d4ee4d25 | 1368 | warning (0, "-g with -mno-apcs-frame may not give sensible debugging"); |
f676971a | 1369 | |
2b835d68 | 1370 | if (TARGET_APCS_FLOAT) |
d4ee4d25 | 1371 | warning (0, "passing floating point arguments in fp regs not yet supported"); |
f676971a | 1372 | |
4912a07c | 1373 | /* Initialize boolean versions of the flags, for use in the arm.md file. */ |
9b66ebb1 PB |
1374 | arm_arch3m = (insn_flags & FL_ARCH3M) != 0; |
1375 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
68d560d4 | 1376 | arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0); |
9b66ebb1 PB |
1377 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; |
1378 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; | |
1379 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | |
d3585b76 | 1380 | arm_arch6k = (insn_flags & FL_ARCH6K) != 0; |
5b3e6663 PB |
1381 | arm_arch_notm = (insn_flags & FL_NOTM) != 0; |
1382 | arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; | |
9b66ebb1 | 1383 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; |
78011587 | 1384 | arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; |
9b66ebb1 PB |
1385 | |
1386 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; | |
abac3b49 | 1387 | arm_tune_strongarm = (tune_flags & FL_STRONG) != 0; |
9b66ebb1 | 1388 | thumb_code = (TARGET_ARM == 0); |
abac3b49 | 1389 | arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; |
9b66ebb1 PB |
1390 | arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; |
1391 | arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; | |
5b3e6663 | 1392 | arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; |
7612f14d | 1393 | arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; |
5a9335ef | 1394 | |
f67358da PB |
1395 | /* If we are not using the default (ARM mode) section anchor offset |
1396 | ranges, then set the correct ranges now. */ | |
1397 | if (TARGET_THUMB1) | |
1398 | { | |
1399 | /* Thumb-1 LDR instructions cannot have negative offsets. | |
1400 | Permissible positive offset ranges are 5-bit (for byte loads), | |
1401 | 6-bit (for halfword loads), or 7-bit (for word loads). | |
1402 | Empirical results suggest a 7-bit anchor range gives the best | |
1403 | overall code size. */ | |
1404 | targetm.min_anchor_offset = 0; | |
1405 | targetm.max_anchor_offset = 127; | |
1406 | } | |
1407 | else if (TARGET_THUMB2) | |
1408 | { | |
1409 | /* The minimum is set such that the total size of the block | |
1410 | for a particular anchor is 248 + 1 + 4095 bytes, which is | |
1411 | divisible by eight, ensuring natural spacing of anchors. */ | |
1412 | targetm.min_anchor_offset = -248; | |
1413 | targetm.max_anchor_offset = 4095; | |
1414 | } | |
1415 | ||
68d560d4 RE |
1416 | /* V5 code we generate is completely interworking capable, so we turn off |
1417 | TARGET_INTERWORK here to avoid many tests later on. */ | |
2ad4dcf9 RE |
1418 | |
1419 | /* XXX However, we must pass the right pre-processor defines to CPP | |
1420 | or GLD can get confused. This is a hack. */ | |
1421 | if (TARGET_INTERWORK) | |
1422 | arm_cpp_interwork = 1; | |
1423 | ||
68d560d4 | 1424 | if (arm_arch5) |
c54c7322 | 1425 | target_flags &= ~MASK_INTERWORK; |
68d560d4 | 1426 | |
5848830f PB |
1427 | if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) |
1428 | error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); | |
1429 | ||
1430 | if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) | |
1431 | error ("iwmmxt abi requires an iwmmxt capable cpu"); | |
6f7ebcbb | 1432 | |
9b66ebb1 PB |
1433 | arm_fp_model = ARM_FP_MODEL_UNKNOWN; |
1434 | if (target_fpu_name == NULL && target_fpe_name != NULL) | |
9b6b54e2 | 1435 | { |
9b66ebb1 PB |
1436 | if (streq (target_fpe_name, "2")) |
1437 | target_fpu_name = "fpe2"; | |
1438 | else if (streq (target_fpe_name, "3")) | |
1439 | target_fpu_name = "fpe3"; | |
1440 | else | |
1441 | error ("invalid floating point emulation option: -mfpe=%s", | |
1442 | target_fpe_name); | |
1443 | } | |
1444 | if (target_fpu_name != NULL) | |
1445 | { | |
1446 | /* The user specified a FPU. */ | |
1447 | for (i = 0; i < ARRAY_SIZE (all_fpus); i++) | |
1448 | { | |
1449 | if (streq (all_fpus[i].name, target_fpu_name)) | |
1450 | { | |
1451 | arm_fpu_arch = all_fpus[i].fpu; | |
1452 | arm_fpu_tune = arm_fpu_arch; | |
1453 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
1454 | break; | |
1455 | } | |
1456 | } | |
1457 | if (arm_fp_model == ARM_FP_MODEL_UNKNOWN) | |
1458 | error ("invalid floating point option: -mfpu=%s", target_fpu_name); | |
9b6b54e2 NC |
1459 | } |
1460 | else | |
2b835d68 | 1461 | { |
9b66ebb1 | 1462 | #ifdef FPUTYPE_DEFAULT |
78011587 | 1463 | /* Use the default if it is specified for this platform. */ |
9b66ebb1 PB |
1464 | arm_fpu_arch = FPUTYPE_DEFAULT; |
1465 | arm_fpu_tune = FPUTYPE_DEFAULT; | |
1466 | #else | |
1467 | /* Pick one based on CPU type. */ | |
78011587 | 1468 | /* ??? Some targets assume FPA is the default. |
9b66ebb1 PB |
1469 | if ((insn_flags & FL_VFP) != 0) |
1470 | arm_fpu_arch = FPUTYPE_VFP; | |
78011587 PB |
1471 | else |
1472 | */ | |
1473 | if (arm_arch_cirrus) | |
9b66ebb1 PB |
1474 | arm_fpu_arch = FPUTYPE_MAVERICK; |
1475 | else | |
29ad9694 | 1476 | arm_fpu_arch = FPUTYPE_FPA_EMU2; |
9b66ebb1 PB |
1477 | #endif |
1478 | if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
1479 | arm_fpu_tune = FPUTYPE_FPA; | |
2b835d68 | 1480 | else |
9b66ebb1 PB |
1481 | arm_fpu_tune = arm_fpu_arch; |
1482 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
e6d29d15 | 1483 | gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN); |
9b66ebb1 PB |
1484 | } |
1485 | ||
1486 | if (target_float_abi_name != NULL) | |
1487 | { | |
1488 | /* The user specified a FP ABI. */ | |
1489 | for (i = 0; i < ARRAY_SIZE (all_float_abis); i++) | |
1490 | { | |
1491 | if (streq (all_float_abis[i].name, target_float_abi_name)) | |
1492 | { | |
1493 | arm_float_abi = all_float_abis[i].abi_type; | |
1494 | break; | |
1495 | } | |
1496 | } | |
1497 | if (i == ARRAY_SIZE (all_float_abis)) | |
1498 | error ("invalid floating point abi: -mfloat-abi=%s", | |
1499 | target_float_abi_name); | |
2b835d68 | 1500 | } |
3d8532aa PB |
1501 | else |
1502 | arm_float_abi = TARGET_DEFAULT_FLOAT_ABI; | |
9b66ebb1 | 1503 | |
72cdc543 PB |
1504 | if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP) |
1505 | sorry ("-mfloat-abi=hard and VFP"); | |
1506 | ||
87b24aaf PB |
1507 | /* FPA and iWMMXt are incompatible because the insn encodings overlap. |
1508 | VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon | |
1509 | will ever exist. GCC makes no attempt to support this combination. */ | |
1510 | if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT) | |
1511 | sorry ("iWMMXt and hardware floating point"); | |
1512 | ||
5b3e6663 PB |
1513 | /* ??? iWMMXt insn patterns need auditing for Thumb-2. */ |
1514 | if (TARGET_THUMB2 && TARGET_IWMMXT) | |
1515 | sorry ("Thumb-2 iWMMXt"); | |
1516 | ||
9b66ebb1 PB |
1517 | /* If soft-float is specified then don't use FPU. */ |
1518 | if (TARGET_SOFT_FLOAT) | |
1519 | arm_fpu_arch = FPUTYPE_NONE; | |
f676971a | 1520 | |
f5a1b0d2 NC |
1521 | /* For arm2/3 there is no need to do any scheduling if there is only |
1522 | a floating point emulator, or we are doing software floating-point. */ | |
9b66ebb1 PB |
1523 | if ((TARGET_SOFT_FLOAT |
1524 | || arm_fpu_tune == FPUTYPE_FPA_EMU2 | |
1525 | || arm_fpu_tune == FPUTYPE_FPA_EMU3) | |
ed0e6530 | 1526 | && (tune_flags & FL_MODE32) == 0) |
f5a1b0d2 | 1527 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
f676971a | 1528 | |
d3585b76 DJ |
1529 | if (target_thread_switch) |
1530 | { | |
1531 | if (strcmp (target_thread_switch, "soft") == 0) | |
1532 | target_thread_pointer = TP_SOFT; | |
1533 | else if (strcmp (target_thread_switch, "auto") == 0) | |
1534 | target_thread_pointer = TP_AUTO; | |
1535 | else if (strcmp (target_thread_switch, "cp15") == 0) | |
1536 | target_thread_pointer = TP_CP15; | |
1537 | else | |
1538 | error ("invalid thread pointer option: -mtp=%s", target_thread_switch); | |
1539 | } | |
1540 | ||
1541 | /* Use the cp15 method if it is available. */ | |
1542 | if (target_thread_pointer == TP_AUTO) | |
1543 | { | |
1544 | if (arm_arch6k && !TARGET_THUMB) | |
1545 | target_thread_pointer = TP_CP15; | |
1546 | else | |
1547 | target_thread_pointer = TP_SOFT; | |
1548 | } | |
1549 | ||
5b3e6663 PB |
1550 | if (TARGET_HARD_TP && TARGET_THUMB1) |
1551 | error ("can not use -mtp=cp15 with 16-bit Thumb"); | |
d3585b76 | 1552 | |
5848830f | 1553 | /* Override the default structure alignment for AAPCS ABI. */ |
077fc835 | 1554 | if (TARGET_AAPCS_BASED) |
5848830f PB |
1555 | arm_structure_size_boundary = 8; |
1556 | ||
b355a481 NC |
1557 | if (structure_size_string != NULL) |
1558 | { | |
1559 | int size = strtol (structure_size_string, NULL, 0); | |
5848830f PB |
1560 | |
1561 | if (size == 8 || size == 32 | |
1562 | || (ARM_DOUBLEWORD_ALIGN && size == 64)) | |
b355a481 NC |
1563 | arm_structure_size_boundary = size; |
1564 | else | |
d4ee4d25 | 1565 | warning (0, "structure size boundary can only be set to %s", |
5848830f | 1566 | ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32"); |
b355a481 | 1567 | } |
ed0e6530 | 1568 | |
9403b7f7 RS |
1569 | if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic) |
1570 | { | |
1571 | error ("RTP PIC is incompatible with Thumb"); | |
1572 | flag_pic = 0; | |
1573 | } | |
1574 | ||
c147eacb PB |
1575 | /* If stack checking is disabled, we can use r10 as the PIC register, |
1576 | which keeps r9 available. The EABI specifies r9 as the PIC register. */ | |
1577 | if (flag_pic && TARGET_SINGLE_PIC_BASE) | |
9403b7f7 RS |
1578 | { |
1579 | if (TARGET_VXWORKS_RTP) | |
1580 | warning (0, "RTP PIC is incompatible with -msingle-pic-base"); | |
1581 | arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10; | |
1582 | } | |
1583 | ||
1584 | if (flag_pic && TARGET_VXWORKS_RTP) | |
1585 | arm_pic_register = 9; | |
c147eacb | 1586 | |
ed0e6530 PB |
1587 | if (arm_pic_register_string != NULL) |
1588 | { | |
5b43fed1 | 1589 | int pic_register = decode_reg_name (arm_pic_register_string); |
e26053d1 | 1590 | |
5895f793 | 1591 | if (!flag_pic) |
d4ee4d25 | 1592 | warning (0, "-mpic-register= is useless without -fpic"); |
ed0e6530 | 1593 | |
ed0e6530 | 1594 | /* Prevent the user from choosing an obviously stupid PIC register. */ |
5b43fed1 RH |
1595 | else if (pic_register < 0 || call_used_regs[pic_register] |
1596 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
1597 | || pic_register == STACK_POINTER_REGNUM | |
9403b7f7 RS |
1598 | || pic_register >= PC_REGNUM |
1599 | || (TARGET_VXWORKS_RTP | |
1600 | && (unsigned int) pic_register != arm_pic_register)) | |
c725bd79 | 1601 | error ("unable to use '%s' for PIC register", arm_pic_register_string); |
ed0e6530 PB |
1602 | else |
1603 | arm_pic_register = pic_register; | |
1604 | } | |
d5b7b3ae | 1605 | |
5fd42423 PB |
1606 | /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */ |
1607 | if (fix_cm3_ldrd == 2) | |
1608 | { | |
1609 | if (selected_cpu == cortexm3) | |
1610 | fix_cm3_ldrd = 1; | |
1611 | else | |
1612 | fix_cm3_ldrd = 0; | |
1613 | } | |
1614 | ||
5b3e6663 | 1615 | /* ??? We might want scheduling for thumb2. */ |
d5b7b3ae RE |
1616 | if (TARGET_THUMB && flag_schedule_insns) |
1617 | { | |
1618 | /* Don't warn since it's on by default in -O2. */ | |
1619 | flag_schedule_insns = 0; | |
1620 | } | |
1621 | ||
f5a1b0d2 | 1622 | if (optimize_size) |
be03ccc9 | 1623 | { |
577d6328 | 1624 | arm_constant_limit = 1; |
be03ccc9 NP |
1625 | |
1626 | /* If optimizing for size, bump the number of instructions that we | |
d6b4baa4 | 1627 | are prepared to conditionally execute (even on a StrongARM). */ |
be03ccc9 NP |
1628 | max_insns_skipped = 6; |
1629 | } | |
1630 | else | |
1631 | { | |
1632 | /* For processors with load scheduling, it never costs more than | |
1633 | 2 cycles to load a constant, and the load scheduler may well | |
1634 | reduce that to 1. */ | |
2075b05d | 1635 | if (arm_ld_sched) |
be03ccc9 NP |
1636 | arm_constant_limit = 1; |
1637 | ||
1638 | /* On XScale the longer latency of a load makes it more difficult | |
1639 | to achieve a good schedule, so it's faster to synthesize | |
d6b4baa4 | 1640 | constants that can be done in two insns. */ |
be03ccc9 NP |
1641 | if (arm_tune_xscale) |
1642 | arm_constant_limit = 2; | |
1643 | ||
1644 | /* StrongARM has early execution of branches, so a sequence | |
1645 | that is worth skipping is shorter. */ | |
abac3b49 | 1646 | if (arm_tune_strongarm) |
be03ccc9 NP |
1647 | max_insns_skipped = 3; |
1648 | } | |
92a432f4 RE |
1649 | |
1650 | /* Register global variables with the garbage collector. */ | |
1651 | arm_add_gc_roots (); | |
1652 | } | |
1653 | ||
1654 | static void | |
e32bac5b | 1655 | arm_add_gc_roots (void) |
92a432f4 | 1656 | { |
c7319d87 RE |
1657 | gcc_obstack_init(&minipool_obstack); |
1658 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 1659 | } |
cce8749e | 1660 | \f |
6d3d9133 NC |
1661 | /* A table of known ARM exception types. |
1662 | For use with the interrupt function attribute. */ | |
1663 | ||
1664 | typedef struct | |
1665 | { | |
8b60264b KG |
1666 | const char *const arg; |
1667 | const unsigned long return_value; | |
6d3d9133 NC |
1668 | } |
1669 | isr_attribute_arg; | |
1670 | ||
8b60264b | 1671 | static const isr_attribute_arg isr_attribute_args [] = |
6d3d9133 NC |
1672 | { |
1673 | { "IRQ", ARM_FT_ISR }, | |
1674 | { "irq", ARM_FT_ISR }, | |
1675 | { "FIQ", ARM_FT_FIQ }, | |
1676 | { "fiq", ARM_FT_FIQ }, | |
1677 | { "ABORT", ARM_FT_ISR }, | |
1678 | { "abort", ARM_FT_ISR }, | |
1679 | { "ABORT", ARM_FT_ISR }, | |
1680 | { "abort", ARM_FT_ISR }, | |
1681 | { "UNDEF", ARM_FT_EXCEPTION }, | |
1682 | { "undef", ARM_FT_EXCEPTION }, | |
1683 | { "SWI", ARM_FT_EXCEPTION }, | |
1684 | { "swi", ARM_FT_EXCEPTION }, | |
1685 | { NULL, ARM_FT_NORMAL } | |
1686 | }; | |
1687 | ||
1688 | /* Returns the (interrupt) function type of the current | |
1689 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
1690 | ||
1691 | static unsigned long | |
e32bac5b | 1692 | arm_isr_value (tree argument) |
6d3d9133 | 1693 | { |
8b60264b | 1694 | const isr_attribute_arg * ptr; |
1d6e90ac | 1695 | const char * arg; |
6d3d9133 | 1696 | |
5b3e6663 PB |
1697 | if (!arm_arch_notm) |
1698 | return ARM_FT_NORMAL | ARM_FT_STACKALIGN; | |
1699 | ||
6d3d9133 NC |
1700 | /* No argument - default to IRQ. */ |
1701 | if (argument == NULL_TREE) | |
1702 | return ARM_FT_ISR; | |
1703 | ||
1704 | /* Get the value of the argument. */ | |
1705 | if (TREE_VALUE (argument) == NULL_TREE | |
1706 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
1707 | return ARM_FT_UNKNOWN; | |
1708 | ||
1709 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
1710 | ||
1711 | /* Check it against the list of known arguments. */ | |
5a9335ef | 1712 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) |
1d6e90ac NC |
1713 | if (streq (arg, ptr->arg)) |
1714 | return ptr->return_value; | |
6d3d9133 | 1715 | |
05713b80 | 1716 | /* An unrecognized interrupt type. */ |
6d3d9133 NC |
1717 | return ARM_FT_UNKNOWN; |
1718 | } | |
1719 | ||
1720 | /* Computes the type of the current function. */ | |
1721 | ||
1722 | static unsigned long | |
e32bac5b | 1723 | arm_compute_func_type (void) |
6d3d9133 NC |
1724 | { |
1725 | unsigned long type = ARM_FT_UNKNOWN; | |
1726 | tree a; | |
1727 | tree attr; | |
f676971a | 1728 | |
e6d29d15 | 1729 | gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL); |
6d3d9133 NC |
1730 | |
1731 | /* Decide if the current function is volatile. Such functions | |
1732 | never return, and many memory cycles can be saved by not storing | |
1733 | register values that will never be needed again. This optimization | |
1734 | was added to speed up context switching in a kernel application. */ | |
1735 | if (optimize > 0 | |
cf1955dc PB |
1736 | && (TREE_NOTHROW (current_function_decl) |
1737 | || !(flag_unwind_tables | |
1738 | || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))) | |
6d3d9133 NC |
1739 | && TREE_THIS_VOLATILE (current_function_decl)) |
1740 | type |= ARM_FT_VOLATILE; | |
f676971a | 1741 | |
6de9cd9a | 1742 | if (cfun->static_chain_decl != NULL) |
6d3d9133 NC |
1743 | type |= ARM_FT_NESTED; |
1744 | ||
91d231cb | 1745 | attr = DECL_ATTRIBUTES (current_function_decl); |
f676971a | 1746 | |
6d3d9133 NC |
1747 | a = lookup_attribute ("naked", attr); |
1748 | if (a != NULL_TREE) | |
1749 | type |= ARM_FT_NAKED; | |
1750 | ||
c9ca9b88 PB |
1751 | a = lookup_attribute ("isr", attr); |
1752 | if (a == NULL_TREE) | |
1753 | a = lookup_attribute ("interrupt", attr); | |
f676971a | 1754 | |
c9ca9b88 PB |
1755 | if (a == NULL_TREE) |
1756 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
6d3d9133 | 1757 | else |
c9ca9b88 | 1758 | type |= arm_isr_value (TREE_VALUE (a)); |
f676971a | 1759 | |
6d3d9133 NC |
1760 | return type; |
1761 | } | |
1762 | ||
1763 | /* Returns the type of the current function. */ | |
1764 | ||
1765 | unsigned long | |
e32bac5b | 1766 | arm_current_func_type (void) |
6d3d9133 NC |
1767 | { |
1768 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
1769 | cfun->machine->func_type = arm_compute_func_type (); | |
1770 | ||
1771 | return cfun->machine->func_type; | |
1772 | } | |
007e61c2 PB |
1773 | |
1774 | bool | |
1775 | arm_allocate_stack_slots_for_args (void) | |
1776 | { | |
1777 | /* Naked functions should not allocate stack slots for arguments. */ | |
1778 | return !IS_NAKED (arm_current_func_type ()); | |
1779 | } | |
1780 | ||
6d3d9133 | 1781 | \f |
f676971a | 1782 | /* Return 1 if it is possible to return using a single instruction. |
a72d4945 RE |
1783 | If SIBLING is non-null, this is a test for a return before a sibling |
1784 | call. SIBLING is the call insn, so we can examine its register usage. */ | |
6d3d9133 | 1785 | |
ff9940b0 | 1786 | int |
a72d4945 | 1787 | use_return_insn (int iscond, rtx sibling) |
ff9940b0 RE |
1788 | { |
1789 | int regno; | |
9b598fa0 | 1790 | unsigned int func_type; |
d5db54a1 | 1791 | unsigned long saved_int_regs; |
a72d4945 | 1792 | unsigned HOST_WIDE_INT stack_adjust; |
5848830f | 1793 | arm_stack_offsets *offsets; |
ff9940b0 | 1794 | |
d5b7b3ae | 1795 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
1796 | if (!reload_completed) |
1797 | return 0; | |
efc2515b | 1798 | |
9b598fa0 RE |
1799 | func_type = arm_current_func_type (); |
1800 | ||
5b3e6663 | 1801 | /* Naked, volatile and stack alignment functions need special |
3a7731fd | 1802 | consideration. */ |
5b3e6663 | 1803 | if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN)) |
6d3d9133 | 1804 | return 0; |
06bea5aa | 1805 | |
a15908a4 PB |
1806 | /* So do interrupt functions that use the frame pointer and Thumb |
1807 | interrupt functions. */ | |
1808 | if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB)) | |
06bea5aa | 1809 | return 0; |
a72d4945 | 1810 | |
5848830f PB |
1811 | offsets = arm_get_frame_offsets (); |
1812 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; | |
a72d4945 | 1813 | |
6d3d9133 | 1814 | /* As do variadic functions. */ |
38173d38 | 1815 | if (crtl->args.pretend_args_size |
3cb66fd7 | 1816 | || cfun->machine->uses_anonymous_args |
699a4925 | 1817 | /* Or if the function calls __builtin_eh_return () */ |
e3b5732b | 1818 | || crtl->calls_eh_return |
699a4925 | 1819 | /* Or if the function calls alloca */ |
e3b5732b | 1820 | || cfun->calls_alloca |
a72d4945 RE |
1821 | /* Or if there is a stack adjustment. However, if the stack pointer |
1822 | is saved on the stack, we can use a pre-incrementing stack load. */ | |
ec6237e4 PB |
1823 | || !(stack_adjust == 0 || (TARGET_APCS_FRAME && frame_pointer_needed |
1824 | && stack_adjust == 4))) | |
ff9940b0 RE |
1825 | return 0; |
1826 | ||
954954d1 | 1827 | saved_int_regs = offsets->saved_regs_mask; |
d5db54a1 | 1828 | |
a72d4945 RE |
1829 | /* Unfortunately, the insn |
1830 | ||
1831 | ldmib sp, {..., sp, ...} | |
1832 | ||
1833 | triggers a bug on most SA-110 based devices, such that the stack | |
1834 | pointer won't be correctly restored if the instruction takes a | |
839a4992 | 1835 | page fault. We work around this problem by popping r3 along with |
a72d4945 | 1836 | the other registers, since that is never slower than executing |
f676971a | 1837 | another instruction. |
a72d4945 RE |
1838 | |
1839 | We test for !arm_arch5 here, because code for any architecture | |
1840 | less than this could potentially be run on one of the buggy | |
1841 | chips. */ | |
5b3e6663 | 1842 | if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM) |
a72d4945 RE |
1843 | { |
1844 | /* Validate that r3 is a call-clobbered register (always true in | |
d6b4baa4 | 1845 | the default abi) ... */ |
a72d4945 RE |
1846 | if (!call_used_regs[3]) |
1847 | return 0; | |
1848 | ||
4f5dfed0 JC |
1849 | /* ... that it isn't being used for a return value ... */ |
1850 | if (arm_size_return_regs () >= (4 * UNITS_PER_WORD)) | |
1851 | return 0; | |
1852 | ||
1853 | /* ... or for a tail-call argument ... */ | |
a72d4945 RE |
1854 | if (sibling) |
1855 | { | |
e6d29d15 | 1856 | gcc_assert (GET_CODE (sibling) == CALL_INSN); |
a72d4945 RE |
1857 | |
1858 | if (find_regno_fusage (sibling, USE, 3)) | |
1859 | return 0; | |
1860 | } | |
1861 | ||
1862 | /* ... and that there are no call-saved registers in r0-r2 | |
1863 | (always true in the default ABI). */ | |
1864 | if (saved_int_regs & 0x7) | |
1865 | return 0; | |
1866 | } | |
1867 | ||
b111229a | 1868 | /* Can't be done if interworking with Thumb, and any registers have been |
d5db54a1 | 1869 | stacked. */ |
a15908a4 | 1870 | if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type)) |
b36ba79f | 1871 | return 0; |
d5db54a1 RE |
1872 | |
1873 | /* On StrongARM, conditional returns are expensive if they aren't | |
1874 | taken and multiple registers have been stacked. */ | |
abac3b49 | 1875 | if (iscond && arm_tune_strongarm) |
6ed30148 | 1876 | { |
f676971a | 1877 | /* Conditional return when just the LR is stored is a simple |
d5db54a1 RE |
1878 | conditional-load instruction, that's not expensive. */ |
1879 | if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) | |
1880 | return 0; | |
6ed30148 | 1881 | |
020a4035 RE |
1882 | if (flag_pic |
1883 | && arm_pic_register != INVALID_REGNUM | |
6fb5fa3c | 1884 | && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
b111229a | 1885 | return 0; |
6ed30148 | 1886 | } |
d5db54a1 RE |
1887 | |
1888 | /* If there are saved registers but the LR isn't saved, then we need | |
1889 | two instructions for the return. */ | |
1890 | if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) | |
1891 | return 0; | |
1892 | ||
3b684012 | 1893 | /* Can't be done if any of the FPA regs are pushed, |
6d3d9133 | 1894 | since this also requires an insn. */ |
9b66ebb1 PB |
1895 | if (TARGET_HARD_FLOAT && TARGET_FPA) |
1896 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 1897 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
9b66ebb1 PB |
1898 | return 0; |
1899 | ||
1900 | /* Likewise VFP regs. */ | |
1901 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
1902 | for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) | |
6fb5fa3c | 1903 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
d5b7b3ae | 1904 | return 0; |
ff9940b0 | 1905 | |
5a9335ef NC |
1906 | if (TARGET_REALLY_IWMMXT) |
1907 | for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) | |
6fb5fa3c | 1908 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5a9335ef NC |
1909 | return 0; |
1910 | ||
ff9940b0 RE |
1911 | return 1; |
1912 | } | |
1913 | ||
cce8749e CH |
1914 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
1915 | ||
1916 | int | |
e32bac5b | 1917 | const_ok_for_arm (HOST_WIDE_INT i) |
cce8749e | 1918 | { |
4642ccb1 | 1919 | int lowbit; |
e0b92319 | 1920 | |
f676971a | 1921 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
56636818 | 1922 | be all zero, or all one. */ |
30cf4896 KG |
1923 | if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 |
1924 | && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) | |
1925 | != ((~(unsigned HOST_WIDE_INT) 0) | |
1926 | & ~(unsigned HOST_WIDE_INT) 0xffffffff))) | |
56636818 | 1927 | return FALSE; |
f676971a | 1928 | |
4642ccb1 | 1929 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; |
e0b92319 | 1930 | |
4642ccb1 RE |
1931 | /* Fast return for 0 and small values. We must do this for zero, since |
1932 | the code below can't handle that one case. */ | |
1933 | if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0) | |
e2c671ba RE |
1934 | return TRUE; |
1935 | ||
5b3e6663 PB |
1936 | /* Get the number of trailing zeros. */ |
1937 | lowbit = ffs((int) i) - 1; | |
1938 | ||
1939 | /* Only even shifts are allowed in ARM mode so round down to the | |
1940 | nearest even number. */ | |
1941 | if (TARGET_ARM) | |
1942 | lowbit &= ~1; | |
4642ccb1 RE |
1943 | |
1944 | if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0) | |
1945 | return TRUE; | |
5b3e6663 PB |
1946 | |
1947 | if (TARGET_ARM) | |
1948 | { | |
1949 | /* Allow rotated constants in ARM mode. */ | |
1950 | if (lowbit <= 4 | |
4642ccb1 RE |
1951 | && ((i & ~0xc000003f) == 0 |
1952 | || (i & ~0xf000000f) == 0 | |
1953 | || (i & ~0xfc000003) == 0)) | |
5b3e6663 PB |
1954 | return TRUE; |
1955 | } | |
1956 | else | |
1957 | { | |
1958 | HOST_WIDE_INT v; | |
1959 | ||
1960 | /* Allow repeated pattern. */ | |
1961 | v = i & 0xff; | |
1962 | v |= v << 16; | |
1963 | if (i == v || i == (v | (v << 8))) | |
1964 | return TRUE; | |
1965 | } | |
cce8749e | 1966 | |
f3bb6135 RE |
1967 | return FALSE; |
1968 | } | |
cce8749e | 1969 | |
6354dc9b | 1970 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 | 1971 | static int |
e32bac5b | 1972 | const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) |
e2c671ba RE |
1973 | { |
1974 | if (const_ok_for_arm (i)) | |
1975 | return 1; | |
1976 | ||
1977 | switch (code) | |
1978 | { | |
1979 | case PLUS: | |
d5a0a47b RE |
1980 | case COMPARE: |
1981 | case EQ: | |
1982 | case NE: | |
1983 | case GT: | |
1984 | case LE: | |
1985 | case LT: | |
1986 | case GE: | |
1987 | case GEU: | |
1988 | case LTU: | |
1989 | case GTU: | |
1990 | case LEU: | |
1991 | case UNORDERED: | |
1992 | case ORDERED: | |
1993 | case UNEQ: | |
1994 | case UNGE: | |
1995 | case UNLT: | |
1996 | case UNGT: | |
1997 | case UNLE: | |
e2c671ba RE |
1998 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); |
1999 | ||
2000 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
2001 | case XOR: | |
2002 | case IOR: | |
2003 | return 0; | |
2004 | ||
2005 | case AND: | |
2006 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
2007 | ||
2008 | default: | |
e6d29d15 | 2009 | gcc_unreachable (); |
e2c671ba RE |
2010 | } |
2011 | } | |
2012 | ||
2013 | /* Emit a sequence of insns to handle a large constant. | |
2014 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
2015 | IOR, AND, XOR, MINUS; | |
2016 | MODE is the mode in which the operation is being performed; | |
2017 | VAL is the integer to operate on; | |
2018 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
2019 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
2020 | either produce a simpler sequence, or we will want to cse the values. |
2021 | Return value is the number of insns emitted. */ | |
e2c671ba | 2022 | |
5b3e6663 | 2023 | /* ??? Tweak this for thumb2. */ |
e2c671ba | 2024 | int |
a406f566 | 2025 | arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, |
e32bac5b | 2026 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets) |
2b835d68 | 2027 | { |
a406f566 MM |
2028 | rtx cond; |
2029 | ||
2030 | if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC) | |
2031 | cond = COND_EXEC_TEST (PATTERN (insn)); | |
2032 | else | |
2033 | cond = NULL_RTX; | |
2034 | ||
2b835d68 RE |
2035 | if (subtargets || code == SET |
2036 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
2037 | && REGNO (target) != REGNO (source))) | |
2038 | { | |
4b632bf1 | 2039 | /* After arm_reorg has been called, we can't fix up expensive |
05713b80 | 2040 | constants by pushing them into memory so we must synthesize |
4b632bf1 RE |
2041 | them in-line, regardless of the cost. This is only likely to |
2042 | be more costly on chips that have load delay slots and we are | |
2043 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
2044 | occurred before the final instruction emission). |
2045 | ||
2046 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 2047 | */ |
5895f793 | 2048 | if (!after_arm_reorg |
a406f566 | 2049 | && !cond |
f676971a | 2050 | && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, |
a406f566 | 2051 | 1, 0) |
4b632bf1 | 2052 | > arm_constant_limit + (code != SET))) |
2b835d68 RE |
2053 | { |
2054 | if (code == SET) | |
2055 | { | |
2056 | /* Currently SET is the only monadic value for CODE, all | |
2057 | the rest are diadic. */ | |
571191af PB |
2058 | if (TARGET_USE_MOVT) |
2059 | arm_emit_movpair (target, GEN_INT (val)); | |
2060 | else | |
2061 | emit_set_insn (target, GEN_INT (val)); | |
2062 | ||
2b835d68 RE |
2063 | return 1; |
2064 | } | |
2065 | else | |
2066 | { | |
2067 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
2068 | ||
571191af PB |
2069 | if (TARGET_USE_MOVT) |
2070 | arm_emit_movpair (temp, GEN_INT (val)); | |
2071 | else | |
2072 | emit_set_insn (temp, GEN_INT (val)); | |
2073 | ||
2b835d68 RE |
2074 | /* For MINUS, the value is subtracted from, since we never |
2075 | have subtraction of a constant. */ | |
2076 | if (code == MINUS) | |
d66437c5 | 2077 | emit_set_insn (target, gen_rtx_MINUS (mode, temp, source)); |
2b835d68 | 2078 | else |
d66437c5 RE |
2079 | emit_set_insn (target, |
2080 | gen_rtx_fmt_ee (code, mode, source, temp)); | |
2b835d68 RE |
2081 | return 2; |
2082 | } | |
2083 | } | |
2084 | } | |
2085 | ||
f676971a | 2086 | return arm_gen_constant (code, mode, cond, val, target, source, subtargets, |
a406f566 | 2087 | 1); |
2b835d68 RE |
2088 | } |
2089 | ||
5b3e6663 PB |
2090 | /* Return the number of ARM instructions required to synthesize the given |
2091 | constant. */ | |
ceebdb09 | 2092 | static int |
e32bac5b | 2093 | count_insns_for_constant (HOST_WIDE_INT remainder, int i) |
ceebdb09 PB |
2094 | { |
2095 | HOST_WIDE_INT temp1; | |
2096 | int num_insns = 0; | |
2097 | do | |
2098 | { | |
2099 | int end; | |
f676971a | 2100 | |
ceebdb09 PB |
2101 | if (i <= 0) |
2102 | i += 32; | |
2103 | if (remainder & (3 << (i - 2))) | |
2104 | { | |
2105 | end = i - 8; | |
2106 | if (end < 0) | |
2107 | end += 32; | |
2108 | temp1 = remainder & ((0x0ff << end) | |
2109 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
2110 | remainder &= ~temp1; | |
2111 | num_insns++; | |
2112 | i -= 6; | |
2113 | } | |
2114 | i -= 2; | |
2115 | } while (remainder); | |
2116 | return num_insns; | |
2117 | } | |
2118 | ||
a406f566 MM |
2119 | /* Emit an instruction with the indicated PATTERN. If COND is |
2120 | non-NULL, conditionalize the execution of the instruction on COND | |
2121 | being true. */ | |
2122 | ||
2123 | static void | |
2124 | emit_constant_insn (rtx cond, rtx pattern) | |
2125 | { | |
2126 | if (cond) | |
2127 | pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern); | |
2128 | emit_insn (pattern); | |
2129 | } | |
2130 | ||
2b835d68 RE |
2131 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
2132 | RTL generation. */ | |
5b3e6663 | 2133 | /* ??? This needs more work for thumb2. */ |
1d6e90ac | 2134 | |
d5b7b3ae | 2135 | static int |
a406f566 | 2136 | arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, |
e32bac5b RE |
2137 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets, |
2138 | int generate) | |
e2c671ba | 2139 | { |
e2c671ba RE |
2140 | int can_invert = 0; |
2141 | int can_negate = 0; | |
2142 | int can_negate_initial = 0; | |
2143 | int can_shift = 0; | |
2144 | int i; | |
2145 | int num_bits_set = 0; | |
2146 | int set_sign_bit_copies = 0; | |
2147 | int clear_sign_bit_copies = 0; | |
2148 | int clear_zero_bit_copies = 0; | |
2149 | int set_zero_bit_copies = 0; | |
2150 | int insns = 0; | |
e2c671ba | 2151 | unsigned HOST_WIDE_INT temp1, temp2; |
30cf4896 | 2152 | unsigned HOST_WIDE_INT remainder = val & 0xffffffff; |
e2c671ba | 2153 | |
d5b7b3ae | 2154 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
2155 | check for degenerate cases; these can occur when DImode operations |
2156 | are split. */ | |
2157 | switch (code) | |
2158 | { | |
2159 | case SET: | |
2160 | can_invert = 1; | |
2161 | can_shift = 1; | |
2162 | can_negate = 1; | |
2163 | break; | |
2164 | ||
2165 | case PLUS: | |
2166 | can_negate = 1; | |
2167 | can_negate_initial = 1; | |
2168 | break; | |
2169 | ||
2170 | case IOR: | |
30cf4896 | 2171 | if (remainder == 0xffffffff) |
e2c671ba | 2172 | { |
2b835d68 | 2173 | if (generate) |
a406f566 MM |
2174 | emit_constant_insn (cond, |
2175 | gen_rtx_SET (VOIDmode, target, | |
2176 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
2177 | return 1; |
2178 | } | |
2179 | if (remainder == 0) | |
2180 | { | |
2181 | if (reload_completed && rtx_equal_p (target, source)) | |
2182 | return 0; | |
2b835d68 | 2183 | if (generate) |
a406f566 MM |
2184 | emit_constant_insn (cond, |
2185 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2186 | return 1; |
2187 | } | |
2188 | break; | |
2189 | ||
2190 | case AND: | |
2191 | if (remainder == 0) | |
2192 | { | |
2b835d68 | 2193 | if (generate) |
a406f566 MM |
2194 | emit_constant_insn (cond, |
2195 | gen_rtx_SET (VOIDmode, target, const0_rtx)); | |
e2c671ba RE |
2196 | return 1; |
2197 | } | |
30cf4896 | 2198 | if (remainder == 0xffffffff) |
e2c671ba RE |
2199 | { |
2200 | if (reload_completed && rtx_equal_p (target, source)) | |
2201 | return 0; | |
2b835d68 | 2202 | if (generate) |
a406f566 MM |
2203 | emit_constant_insn (cond, |
2204 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2205 | return 1; |
2206 | } | |
2207 | can_invert = 1; | |
2208 | break; | |
2209 | ||
2210 | case XOR: | |
2211 | if (remainder == 0) | |
2212 | { | |
2213 | if (reload_completed && rtx_equal_p (target, source)) | |
2214 | return 0; | |
2b835d68 | 2215 | if (generate) |
a406f566 MM |
2216 | emit_constant_insn (cond, |
2217 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2218 | return 1; |
2219 | } | |
e0b92319 | 2220 | |
e6d29d15 NS |
2221 | /* We don't know how to handle other cases yet. */ |
2222 | gcc_assert (remainder == 0xffffffff); | |
e0b92319 | 2223 | |
e6d29d15 NS |
2224 | if (generate) |
2225 | emit_constant_insn (cond, | |
2226 | gen_rtx_SET (VOIDmode, target, | |
2227 | gen_rtx_NOT (mode, source))); | |
2228 | return 1; | |
e2c671ba RE |
2229 | |
2230 | case MINUS: | |
2231 | /* We treat MINUS as (val - source), since (source - val) is always | |
2232 | passed as (source + (-val)). */ | |
2233 | if (remainder == 0) | |
2234 | { | |
2b835d68 | 2235 | if (generate) |
a406f566 MM |
2236 | emit_constant_insn (cond, |
2237 | gen_rtx_SET (VOIDmode, target, | |
2238 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
2239 | return 1; |
2240 | } | |
2241 | if (const_ok_for_arm (val)) | |
2242 | { | |
2b835d68 | 2243 | if (generate) |
a406f566 | 2244 | emit_constant_insn (cond, |
f676971a | 2245 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2246 | gen_rtx_MINUS (mode, GEN_INT (val), |
2247 | source))); | |
e2c671ba RE |
2248 | return 1; |
2249 | } | |
2250 | can_negate = 1; | |
2251 | ||
2252 | break; | |
2253 | ||
2254 | default: | |
e6d29d15 | 2255 | gcc_unreachable (); |
e2c671ba RE |
2256 | } |
2257 | ||
6354dc9b | 2258 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
2259 | if (const_ok_for_arm (val) |
2260 | || (can_negate_initial && const_ok_for_arm (-val)) | |
2261 | || (can_invert && const_ok_for_arm (~val))) | |
2262 | { | |
2b835d68 | 2263 | if (generate) |
a406f566 MM |
2264 | emit_constant_insn (cond, |
2265 | gen_rtx_SET (VOIDmode, target, | |
f676971a | 2266 | (source |
a406f566 MM |
2267 | ? gen_rtx_fmt_ee (code, mode, source, |
2268 | GEN_INT (val)) | |
2269 | : GEN_INT (val)))); | |
e2c671ba RE |
2270 | return 1; |
2271 | } | |
2272 | ||
e2c671ba | 2273 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 2274 | optimizations. */ |
e2c671ba RE |
2275 | for (i = 31; i >= 0; i--) |
2276 | { | |
2277 | if ((remainder & (1 << i)) == 0) | |
2278 | clear_sign_bit_copies++; | |
2279 | else | |
2280 | break; | |
2281 | } | |
2282 | ||
2283 | for (i = 31; i >= 0; i--) | |
2284 | { | |
2285 | if ((remainder & (1 << i)) != 0) | |
2286 | set_sign_bit_copies++; | |
2287 | else | |
2288 | break; | |
2289 | } | |
2290 | ||
2291 | for (i = 0; i <= 31; i++) | |
2292 | { | |
2293 | if ((remainder & (1 << i)) == 0) | |
2294 | clear_zero_bit_copies++; | |
2295 | else | |
2296 | break; | |
2297 | } | |
2298 | ||
2299 | for (i = 0; i <= 31; i++) | |
2300 | { | |
2301 | if ((remainder & (1 << i)) != 0) | |
2302 | set_zero_bit_copies++; | |
2303 | else | |
2304 | break; | |
2305 | } | |
2306 | ||
2307 | switch (code) | |
2308 | { | |
2309 | case SET: | |
5b3e6663 PB |
2310 | /* See if we can use movw. */ |
2311 | if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0) | |
2312 | { | |
2313 | if (generate) | |
2314 | emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target, | |
2315 | GEN_INT (val))); | |
2316 | return 1; | |
2317 | } | |
2318 | ||
e2c671ba RE |
2319 | /* See if we can do this by sign_extending a constant that is known |
2320 | to be negative. This is a good, way of doing it, since the shift | |
2321 | may well merge into a subsequent insn. */ | |
2322 | if (set_sign_bit_copies > 1) | |
2323 | { | |
2324 | if (const_ok_for_arm | |
f676971a | 2325 | (temp1 = ARM_SIGN_EXTEND (remainder |
e2c671ba RE |
2326 | << (set_sign_bit_copies - 1)))) |
2327 | { | |
2b835d68 RE |
2328 | if (generate) |
2329 | { | |
d499463f | 2330 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 | 2331 | emit_constant_insn (cond, |
f676971a | 2332 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 MM |
2333 | GEN_INT (temp1))); |
2334 | emit_constant_insn (cond, | |
f676971a | 2335 | gen_ashrsi3 (target, new_src, |
a406f566 | 2336 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2337 | } |
e2c671ba RE |
2338 | return 2; |
2339 | } | |
2340 | /* For an inverted constant, we will need to set the low bits, | |
2341 | these will be shifted out of harm's way. */ | |
2342 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
2343 | if (const_ok_for_arm (~temp1)) | |
2344 | { | |
2b835d68 RE |
2345 | if (generate) |
2346 | { | |
d499463f | 2347 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 MM |
2348 | emit_constant_insn (cond, |
2349 | gen_rtx_SET (VOIDmode, new_src, | |
2350 | GEN_INT (temp1))); | |
2351 | emit_constant_insn (cond, | |
f676971a | 2352 | gen_ashrsi3 (target, new_src, |
a406f566 | 2353 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2354 | } |
e2c671ba RE |
2355 | return 2; |
2356 | } | |
2357 | } | |
2358 | ||
c87e6352 RE |
2359 | /* See if we can calculate the value as the difference between two |
2360 | valid immediates. */ | |
2361 | if (clear_sign_bit_copies + clear_zero_bit_copies <= 16) | |
2362 | { | |
2363 | int topshift = clear_sign_bit_copies & ~1; | |
2364 | ||
fa2c88a0 RE |
2365 | temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift)) |
2366 | & (0xff000000 >> topshift)); | |
c87e6352 RE |
2367 | |
2368 | /* If temp1 is zero, then that means the 9 most significant | |
2369 | bits of remainder were 1 and we've caused it to overflow. | |
2370 | When topshift is 0 we don't need to do anything since we | |
2371 | can borrow from 'bit 32'. */ | |
2372 | if (temp1 == 0 && topshift != 0) | |
2373 | temp1 = 0x80000000 >> (topshift - 1); | |
2374 | ||
fa2c88a0 | 2375 | temp2 = ARM_SIGN_EXTEND (temp1 - remainder); |
e0b92319 | 2376 | |
c87e6352 RE |
2377 | if (const_ok_for_arm (temp2)) |
2378 | { | |
2379 | if (generate) | |
2380 | { | |
2381 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; | |
2382 | emit_constant_insn (cond, | |
2383 | gen_rtx_SET (VOIDmode, new_src, | |
2384 | GEN_INT (temp1))); | |
2385 | emit_constant_insn (cond, | |
2386 | gen_addsi3 (target, new_src, | |
2387 | GEN_INT (-temp2))); | |
2388 | } | |
2389 | ||
2390 | return 2; | |
2391 | } | |
2392 | } | |
2393 | ||
e2c671ba RE |
2394 | /* See if we can generate this by setting the bottom (or the top) |
2395 | 16 bits, and then shifting these into the other half of the | |
2396 | word. We only look for the simplest cases, to do more would cost | |
2397 | too much. Be careful, however, not to generate this when the | |
2398 | alternative would take fewer insns. */ | |
30cf4896 | 2399 | if (val & 0xffff0000) |
e2c671ba | 2400 | { |
30cf4896 | 2401 | temp1 = remainder & 0xffff0000; |
e2c671ba RE |
2402 | temp2 = remainder & 0x0000ffff; |
2403 | ||
6354dc9b | 2404 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
2405 | for (i = 9; i < 24; i++) |
2406 | { | |
30cf4896 | 2407 | if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) |
5895f793 | 2408 | && !const_ok_for_arm (temp2)) |
e2c671ba | 2409 | { |
d499463f RE |
2410 | rtx new_src = (subtargets |
2411 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2412 | : target); | |
a406f566 | 2413 | insns = arm_gen_constant (code, mode, cond, temp2, new_src, |
2b835d68 | 2414 | source, subtargets, generate); |
e2c671ba | 2415 | source = new_src; |
2b835d68 | 2416 | if (generate) |
f676971a | 2417 | emit_constant_insn |
a406f566 MM |
2418 | (cond, |
2419 | gen_rtx_SET | |
2420 | (VOIDmode, target, | |
2421 | gen_rtx_IOR (mode, | |
2422 | gen_rtx_ASHIFT (mode, source, | |
2423 | GEN_INT (i)), | |
2424 | source))); | |
e2c671ba RE |
2425 | return insns + 1; |
2426 | } | |
2427 | } | |
2428 | ||
6354dc9b | 2429 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
2430 | for (i = 17; i < 24; i++) |
2431 | { | |
2432 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 2433 | && !const_ok_for_arm (temp1)) |
e2c671ba | 2434 | { |
d499463f RE |
2435 | rtx new_src = (subtargets |
2436 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2437 | : target); | |
a406f566 | 2438 | insns = arm_gen_constant (code, mode, cond, temp1, new_src, |
2b835d68 | 2439 | source, subtargets, generate); |
e2c671ba | 2440 | source = new_src; |
2b835d68 | 2441 | if (generate) |
a406f566 MM |
2442 | emit_constant_insn |
2443 | (cond, | |
2444 | gen_rtx_SET (VOIDmode, target, | |
43cffd11 RE |
2445 | gen_rtx_IOR |
2446 | (mode, | |
2447 | gen_rtx_LSHIFTRT (mode, source, | |
2448 | GEN_INT (i)), | |
2449 | source))); | |
e2c671ba RE |
2450 | return insns + 1; |
2451 | } | |
2452 | } | |
2453 | } | |
2454 | break; | |
2455 | ||
2456 | case IOR: | |
2457 | case XOR: | |
7b64da89 RE |
2458 | /* If we have IOR or XOR, and the constant can be loaded in a |
2459 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
2460 | then this can be done in two instructions instead of 3-4. */ |
2461 | if (subtargets | |
d499463f | 2462 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 2463 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 2464 | { |
5895f793 | 2465 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2466 | { |
2b835d68 RE |
2467 | if (generate) |
2468 | { | |
2469 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 2470 | |
a406f566 | 2471 | emit_constant_insn (cond, |
f676971a | 2472 | gen_rtx_SET (VOIDmode, sub, |
a406f566 MM |
2473 | GEN_INT (val))); |
2474 | emit_constant_insn (cond, | |
f676971a | 2475 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2476 | gen_rtx_fmt_ee (code, mode, |
2477 | source, sub))); | |
2b835d68 | 2478 | } |
e2c671ba RE |
2479 | return 2; |
2480 | } | |
2481 | } | |
2482 | ||
2483 | if (code == XOR) | |
2484 | break; | |
2485 | ||
2486 | if (set_sign_bit_copies > 8 | |
2487 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
2488 | { | |
2b835d68 RE |
2489 | if (generate) |
2490 | { | |
2491 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2492 | rtx shift = GEN_INT (set_sign_bit_copies); | |
2493 | ||
f676971a | 2494 | emit_constant_insn |
a406f566 MM |
2495 | (cond, |
2496 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2497 | gen_rtx_NOT (mode, |
a406f566 | 2498 | gen_rtx_ASHIFT (mode, |
f676971a | 2499 | source, |
a406f566 | 2500 | shift)))); |
f676971a | 2501 | emit_constant_insn |
a406f566 MM |
2502 | (cond, |
2503 | gen_rtx_SET (VOIDmode, target, | |
2504 | gen_rtx_NOT (mode, | |
2505 | gen_rtx_LSHIFTRT (mode, sub, | |
2506 | shift)))); | |
2b835d68 | 2507 | } |
e2c671ba RE |
2508 | return 2; |
2509 | } | |
2510 | ||
2511 | if (set_zero_bit_copies > 8 | |
2512 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
2513 | { | |
2b835d68 RE |
2514 | if (generate) |
2515 | { | |
2516 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2517 | rtx shift = GEN_INT (set_zero_bit_copies); | |
2518 | ||
a406f566 MM |
2519 | emit_constant_insn |
2520 | (cond, | |
2521 | gen_rtx_SET (VOIDmode, sub, | |
2522 | gen_rtx_NOT (mode, | |
2523 | gen_rtx_LSHIFTRT (mode, | |
2524 | source, | |
2525 | shift)))); | |
f676971a | 2526 | emit_constant_insn |
a406f566 MM |
2527 | (cond, |
2528 | gen_rtx_SET (VOIDmode, target, | |
2529 | gen_rtx_NOT (mode, | |
2530 | gen_rtx_ASHIFT (mode, sub, | |
2531 | shift)))); | |
2b835d68 | 2532 | } |
e2c671ba RE |
2533 | return 2; |
2534 | } | |
2535 | ||
5895f793 | 2536 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2537 | { |
2b835d68 RE |
2538 | if (generate) |
2539 | { | |
2540 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
a406f566 MM |
2541 | emit_constant_insn (cond, |
2542 | gen_rtx_SET (VOIDmode, sub, | |
2543 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
2544 | source = sub; |
2545 | if (subtargets) | |
2546 | sub = gen_reg_rtx (mode); | |
a406f566 MM |
2547 | emit_constant_insn (cond, |
2548 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2549 | gen_rtx_AND (mode, source, |
a406f566 MM |
2550 | GEN_INT (temp1)))); |
2551 | emit_constant_insn (cond, | |
2552 | gen_rtx_SET (VOIDmode, target, | |
2553 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 2554 | } |
e2c671ba RE |
2555 | return 3; |
2556 | } | |
2557 | break; | |
2558 | ||
2559 | case AND: | |
2560 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
2561 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
2562 | { | |
30cf4896 | 2563 | HOST_WIDE_INT shift_mask = ((0xffffffff |
e2c671ba | 2564 | << (32 - clear_sign_bit_copies)) |
30cf4896 | 2565 | & 0xffffffff); |
e2c671ba | 2566 | |
30cf4896 | 2567 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 2568 | { |
2b835d68 RE |
2569 | if (generate) |
2570 | { | |
d499463f | 2571 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
f676971a | 2572 | insns = arm_gen_constant (AND, mode, cond, |
a406f566 | 2573 | remainder | shift_mask, |
d499463f RE |
2574 | new_src, source, subtargets, 1); |
2575 | source = new_src; | |
2b835d68 RE |
2576 | } |
2577 | else | |
d499463f RE |
2578 | { |
2579 | rtx targ = subtargets ? NULL_RTX : target; | |
a406f566 MM |
2580 | insns = arm_gen_constant (AND, mode, cond, |
2581 | remainder | shift_mask, | |
d499463f RE |
2582 | targ, source, subtargets, 0); |
2583 | } | |
2b835d68 RE |
2584 | } |
2585 | ||
2586 | if (generate) | |
2587 | { | |
d499463f RE |
2588 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2589 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
2590 | ||
2591 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
2592 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
2593 | } |
2594 | ||
e2c671ba RE |
2595 | return insns + 2; |
2596 | } | |
2597 | ||
2598 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
2599 | { | |
2600 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
f676971a | 2601 | |
30cf4896 | 2602 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 2603 | { |
2b835d68 RE |
2604 | if (generate) |
2605 | { | |
d499463f RE |
2606 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2607 | ||
a406f566 MM |
2608 | insns = arm_gen_constant (AND, mode, cond, |
2609 | remainder | shift_mask, | |
d499463f RE |
2610 | new_src, source, subtargets, 1); |
2611 | source = new_src; | |
2b835d68 RE |
2612 | } |
2613 | else | |
d499463f RE |
2614 | { |
2615 | rtx targ = subtargets ? NULL_RTX : target; | |
2616 | ||
a406f566 MM |
2617 | insns = arm_gen_constant (AND, mode, cond, |
2618 | remainder | shift_mask, | |
d499463f RE |
2619 | targ, source, subtargets, 0); |
2620 | } | |
2b835d68 RE |
2621 | } |
2622 | ||
2623 | if (generate) | |
2624 | { | |
d499463f RE |
2625 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2626 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
2627 | ||
2628 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
2629 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
2630 | } |
2631 | ||
e2c671ba RE |
2632 | return insns + 2; |
2633 | } | |
2634 | ||
2635 | break; | |
2636 | ||
2637 | default: | |
2638 | break; | |
2639 | } | |
2640 | ||
2641 | for (i = 0; i < 32; i++) | |
2642 | if (remainder & (1 << i)) | |
2643 | num_bits_set++; | |
2644 | ||
2645 | if (code == AND || (can_invert && num_bits_set > 16)) | |
30cf4896 | 2646 | remainder = (~remainder) & 0xffffffff; |
e2c671ba | 2647 | else if (code == PLUS && num_bits_set > 16) |
30cf4896 | 2648 | remainder = (-remainder) & 0xffffffff; |
e2c671ba RE |
2649 | else |
2650 | { | |
2651 | can_invert = 0; | |
2652 | can_negate = 0; | |
2653 | } | |
2654 | ||
2655 | /* Now try and find a way of doing the job in either two or three | |
2656 | instructions. | |
2657 | We start by looking for the largest block of zeros that are aligned on | |
2658 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
2659 | top of the word when we drop off the bottom. | |
5b3e6663 PB |
2660 | In the worst case this code should produce no more than four insns. |
2661 | Thumb-2 constants are shifted, not rotated, so the MSB is always the | |
2662 | best place to start. */ | |
2663 | ||
2664 | /* ??? Use thumb2 replicated constants when the high and low halfwords are | |
2665 | the same. */ | |
e2c671ba RE |
2666 | { |
2667 | int best_start = 0; | |
5b3e6663 | 2668 | if (!TARGET_THUMB2) |
e2c671ba | 2669 | { |
5b3e6663 | 2670 | int best_consecutive_zeros = 0; |
e2c671ba | 2671 | |
5b3e6663 | 2672 | for (i = 0; i < 32; i += 2) |
e2c671ba | 2673 | { |
5b3e6663 PB |
2674 | int consecutive_zeros = 0; |
2675 | ||
2676 | if (!(remainder & (3 << i))) | |
e2c671ba | 2677 | { |
5b3e6663 PB |
2678 | while ((i < 32) && !(remainder & (3 << i))) |
2679 | { | |
2680 | consecutive_zeros += 2; | |
2681 | i += 2; | |
2682 | } | |
2683 | if (consecutive_zeros > best_consecutive_zeros) | |
2684 | { | |
2685 | best_consecutive_zeros = consecutive_zeros; | |
2686 | best_start = i - consecutive_zeros; | |
2687 | } | |
2688 | i -= 2; | |
e2c671ba | 2689 | } |
e2c671ba | 2690 | } |
ceebdb09 | 2691 | |
5b3e6663 PB |
2692 | /* So long as it won't require any more insns to do so, it's |
2693 | desirable to emit a small constant (in bits 0...9) in the last | |
2694 | insn. This way there is more chance that it can be combined with | |
2695 | a later addressing insn to form a pre-indexed load or store | |
2696 | operation. Consider: | |
2697 | ||
2698 | *((volatile int *)0xe0000100) = 1; | |
2699 | *((volatile int *)0xe0000110) = 2; | |
2700 | ||
2701 | We want this to wind up as: | |
2702 | ||
2703 | mov rA, #0xe0000000 | |
2704 | mov rB, #1 | |
2705 | str rB, [rA, #0x100] | |
2706 | mov rB, #2 | |
2707 | str rB, [rA, #0x110] | |
2708 | ||
2709 | rather than having to synthesize both large constants from scratch. | |
2710 | ||
2711 | Therefore, we calculate how many insns would be required to emit | |
2712 | the constant starting from `best_start', and also starting from | |
2713 | zero (i.e. with bit 31 first to be output). If `best_start' doesn't | |
2714 | yield a shorter sequence, we may as well use zero. */ | |
2715 | if (best_start != 0 | |
2716 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
2717 | && (count_insns_for_constant (remainder, 0) <= | |
2718 | count_insns_for_constant (remainder, best_start))) | |
2719 | best_start = 0; | |
2720 | } | |
ceebdb09 PB |
2721 | |
2722 | /* Now start emitting the insns. */ | |
e2c671ba RE |
2723 | i = best_start; |
2724 | do | |
2725 | { | |
2726 | int end; | |
2727 | ||
2728 | if (i <= 0) | |
2729 | i += 32; | |
2730 | if (remainder & (3 << (i - 2))) | |
2731 | { | |
2732 | end = i - 8; | |
2733 | if (end < 0) | |
2734 | end += 32; | |
2735 | temp1 = remainder & ((0x0ff << end) | |
2736 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
2737 | remainder &= ~temp1; | |
2738 | ||
d499463f | 2739 | if (generate) |
e2c671ba | 2740 | { |
9503f3d1 RH |
2741 | rtx new_src, temp1_rtx; |
2742 | ||
2743 | if (code == SET || code == MINUS) | |
2744 | { | |
2745 | new_src = (subtargets ? gen_reg_rtx (mode) : target); | |
96ae8197 | 2746 | if (can_invert && code != MINUS) |
9503f3d1 RH |
2747 | temp1 = ~temp1; |
2748 | } | |
2749 | else | |
2750 | { | |
96ae8197 | 2751 | if (remainder && subtargets) |
9503f3d1 | 2752 | new_src = gen_reg_rtx (mode); |
96ae8197 NC |
2753 | else |
2754 | new_src = target; | |
9503f3d1 RH |
2755 | if (can_invert) |
2756 | temp1 = ~temp1; | |
2757 | else if (can_negate) | |
2758 | temp1 = -temp1; | |
2759 | } | |
2760 | ||
2761 | temp1 = trunc_int_for_mode (temp1, mode); | |
2762 | temp1_rtx = GEN_INT (temp1); | |
d499463f RE |
2763 | |
2764 | if (code == SET) | |
9503f3d1 | 2765 | ; |
d499463f | 2766 | else if (code == MINUS) |
9503f3d1 | 2767 | temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); |
d499463f | 2768 | else |
9503f3d1 RH |
2769 | temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); |
2770 | ||
a406f566 | 2771 | emit_constant_insn (cond, |
f676971a | 2772 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 | 2773 | temp1_rtx)); |
d499463f | 2774 | source = new_src; |
e2c671ba RE |
2775 | } |
2776 | ||
d499463f RE |
2777 | if (code == SET) |
2778 | { | |
2779 | can_invert = 0; | |
2780 | code = PLUS; | |
2781 | } | |
2782 | else if (code == MINUS) | |
2783 | code = PLUS; | |
2784 | ||
e2c671ba | 2785 | insns++; |
5b3e6663 PB |
2786 | if (TARGET_ARM) |
2787 | i -= 6; | |
2788 | else | |
2789 | i -= 7; | |
e2c671ba | 2790 | } |
7a085dce | 2791 | /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary |
5b3e6663 PB |
2792 | shifts. */ |
2793 | if (TARGET_ARM) | |
2794 | i -= 2; | |
2795 | else | |
2796 | i--; | |
1d6e90ac NC |
2797 | } |
2798 | while (remainder); | |
e2c671ba | 2799 | } |
1d6e90ac | 2800 | |
e2c671ba RE |
2801 | return insns; |
2802 | } | |
2803 | ||
bd9c7e23 RE |
2804 | /* Canonicalize a comparison so that we are more likely to recognize it. |
2805 | This can be done for a few constant compares, where we can make the | |
2806 | immediate value easier to load. */ | |
1d6e90ac | 2807 | |
bd9c7e23 | 2808 | enum rtx_code |
a14b88bb PB |
2809 | arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode, |
2810 | rtx * op1) | |
bd9c7e23 | 2811 | { |
ad076f4e | 2812 | unsigned HOST_WIDE_INT i = INTVAL (*op1); |
a14b88bb PB |
2813 | unsigned HOST_WIDE_INT maxval; |
2814 | maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; | |
bd9c7e23 RE |
2815 | |
2816 | switch (code) | |
2817 | { | |
2818 | case EQ: | |
2819 | case NE: | |
2820 | return code; | |
2821 | ||
2822 | case GT: | |
2823 | case LE: | |
a14b88bb | 2824 | if (i != maxval |
5895f793 | 2825 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 | 2826 | { |
5895f793 | 2827 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
2828 | return code == GT ? GE : LT; |
2829 | } | |
2830 | break; | |
2831 | ||
2832 | case GE: | |
2833 | case LT: | |
a14b88bb | 2834 | if (i != ~maxval |
5895f793 | 2835 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 2836 | { |
5895f793 | 2837 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
2838 | return code == GE ? GT : LE; |
2839 | } | |
2840 | break; | |
2841 | ||
2842 | case GTU: | |
2843 | case LEU: | |
30cf4896 | 2844 | if (i != ~((unsigned HOST_WIDE_INT) 0) |
5895f793 | 2845 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 RE |
2846 | { |
2847 | *op1 = GEN_INT (i + 1); | |
2848 | return code == GTU ? GEU : LTU; | |
2849 | } | |
2850 | break; | |
2851 | ||
2852 | case GEU: | |
2853 | case LTU: | |
2854 | if (i != 0 | |
5895f793 | 2855 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
2856 | { |
2857 | *op1 = GEN_INT (i - 1); | |
2858 | return code == GEU ? GTU : LEU; | |
2859 | } | |
2860 | break; | |
2861 | ||
2862 | default: | |
e6d29d15 | 2863 | gcc_unreachable (); |
bd9c7e23 RE |
2864 | } |
2865 | ||
2866 | return code; | |
2867 | } | |
bd9c7e23 | 2868 | |
d4453b7a PB |
2869 | |
2870 | /* Define how to find the value returned by a function. */ | |
2871 | ||
9f7bf991 | 2872 | rtx |
586de218 | 2873 | arm_function_value(const_tree type, const_tree func ATTRIBUTE_UNUSED) |
d4453b7a PB |
2874 | { |
2875 | enum machine_mode mode; | |
2876 | int unsignedp ATTRIBUTE_UNUSED; | |
2877 | rtx r ATTRIBUTE_UNUSED; | |
2878 | ||
d4453b7a PB |
2879 | mode = TYPE_MODE (type); |
2880 | /* Promote integer types. */ | |
2881 | if (INTEGRAL_TYPE_P (type)) | |
2882 | PROMOTE_FUNCTION_MODE (mode, unsignedp, type); | |
866af8a9 JB |
2883 | |
2884 | /* Promotes small structs returned in a register to full-word size | |
2885 | for big-endian AAPCS. */ | |
2886 | if (arm_return_in_msb (type)) | |
2887 | { | |
2888 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
2889 | if (size % UNITS_PER_WORD != 0) | |
2890 | { | |
2891 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; | |
2892 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
2893 | } | |
2894 | } | |
e0b92319 | 2895 | |
d4453b7a PB |
2896 | return LIBCALL_VALUE(mode); |
2897 | } | |
2898 | ||
e0b92319 | 2899 | /* Determine the amount of memory needed to store the possible return |
9f7bf991 RE |
2900 | registers of an untyped call. */ |
2901 | int | |
2902 | arm_apply_result_size (void) | |
2903 | { | |
2904 | int size = 16; | |
2905 | ||
2906 | if (TARGET_ARM) | |
2907 | { | |
2908 | if (TARGET_HARD_FLOAT_ABI) | |
2909 | { | |
2910 | if (TARGET_FPA) | |
2911 | size += 12; | |
2912 | if (TARGET_MAVERICK) | |
2913 | size += 8; | |
2914 | } | |
2915 | if (TARGET_IWMMXT_ABI) | |
2916 | size += 8; | |
2917 | } | |
2918 | ||
2919 | return size; | |
2920 | } | |
d4453b7a | 2921 | |
f5a1b0d2 | 2922 | /* Decide whether a type should be returned in memory (true) |
23668cf7 | 2923 | or in a register (false). This is called as the target hook |
81464b2c | 2924 | TARGET_RETURN_IN_MEMORY. */ |
23668cf7 | 2925 | static bool |
81464b2c | 2926 | arm_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
2b835d68 | 2927 | { |
dc0ba55a JT |
2928 | HOST_WIDE_INT size; |
2929 | ||
88f77cba JB |
2930 | size = int_size_in_bytes (type); |
2931 | ||
2932 | /* Vector values should be returned using ARM registers, not memory (unless | |
2933 | they're over 16 bytes, which will break since we only have four | |
2934 | call-clobbered registers to play with). */ | |
2935 | if (TREE_CODE (type) == VECTOR_TYPE) | |
2936 | return (size < 0 || size > (4 * UNITS_PER_WORD)); | |
2937 | ||
3dd7ab65 JB |
2938 | if (!AGGREGATE_TYPE_P (type) && |
2939 | !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE)) | |
2940 | /* All simple types are returned in registers. | |
2941 | For AAPCS, complex types are treated the same as aggregates. */ | |
d7d01975 | 2942 | return 0; |
dc0ba55a | 2943 | |
5848830f | 2944 | if (arm_abi != ARM_ABI_APCS) |
dc0ba55a | 2945 | { |
5848830f | 2946 | /* ATPCS and later return aggregate types in memory only if they are |
dc0ba55a JT |
2947 | larger than a word (or are variable size). */ |
2948 | return (size < 0 || size > UNITS_PER_WORD); | |
2949 | } | |
f676971a | 2950 | |
6bc82793 | 2951 | /* For the arm-wince targets we choose to be compatible with Microsoft's |
d5b7b3ae RE |
2952 | ARM and Thumb compilers, which always return aggregates in memory. */ |
2953 | #ifndef ARM_WINCE | |
e529bd42 NC |
2954 | /* All structures/unions bigger than one word are returned in memory. |
2955 | Also catch the case where int_size_in_bytes returns -1. In this case | |
6bc82793 | 2956 | the aggregate is either huge or of variable size, and in either case |
e529bd42 | 2957 | we will want to return it via memory and not in a register. */ |
dc0ba55a | 2958 | if (size < 0 || size > UNITS_PER_WORD) |
d7d01975 | 2959 | return 1; |
f676971a | 2960 | |
d7d01975 | 2961 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
2962 | { |
2963 | tree field; | |
2964 | ||
3a2ea258 RE |
2965 | /* For a struct the APCS says that we only return in a register |
2966 | if the type is 'integer like' and every addressable element | |
2967 | has an offset of zero. For practical purposes this means | |
2968 | that the structure can have at most one non bit-field element | |
2969 | and that this element must be the first one in the structure. */ | |
f676971a | 2970 | |
f5a1b0d2 NC |
2971 | /* Find the first field, ignoring non FIELD_DECL things which will |
2972 | have been created by C++. */ | |
2973 | for (field = TYPE_FIELDS (type); | |
2974 | field && TREE_CODE (field) != FIELD_DECL; | |
2975 | field = TREE_CHAIN (field)) | |
2976 | continue; | |
f676971a | 2977 | |
f5a1b0d2 | 2978 | if (field == NULL) |
9e291dbe | 2979 | return 0; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 2980 | |
d5b7b3ae RE |
2981 | /* Check that the first field is valid for returning in a register. */ |
2982 | ||
2983 | /* ... Floats are not allowed */ | |
9e291dbe | 2984 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3a2ea258 RE |
2985 | return 1; |
2986 | ||
d5b7b3ae RE |
2987 | /* ... Aggregates that are not themselves valid for returning in |
2988 | a register are not allowed. */ | |
81464b2c | 2989 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
3a2ea258 | 2990 | return 1; |
6f7ebcbb | 2991 | |
3a2ea258 RE |
2992 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
2993 | since they are not addressable. */ | |
f5a1b0d2 NC |
2994 | for (field = TREE_CHAIN (field); |
2995 | field; | |
2996 | field = TREE_CHAIN (field)) | |
2997 | { | |
2998 | if (TREE_CODE (field) != FIELD_DECL) | |
2999 | continue; | |
f676971a | 3000 | |
5895f793 | 3001 | if (!DECL_BIT_FIELD_TYPE (field)) |
f5a1b0d2 NC |
3002 | return 1; |
3003 | } | |
2b835d68 RE |
3004 | |
3005 | return 0; | |
3006 | } | |
f676971a | 3007 | |
d7d01975 | 3008 | if (TREE_CODE (type) == UNION_TYPE) |
2b835d68 RE |
3009 | { |
3010 | tree field; | |
3011 | ||
3012 | /* Unions can be returned in registers if every element is | |
3013 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
3014 | for (field = TYPE_FIELDS (type); |
3015 | field; | |
3016 | field = TREE_CHAIN (field)) | |
2b835d68 | 3017 | { |
f5a1b0d2 NC |
3018 | if (TREE_CODE (field) != FIELD_DECL) |
3019 | continue; | |
3020 | ||
6cc8c0b3 NC |
3021 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3022 | return 1; | |
f676971a | 3023 | |
81464b2c | 3024 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
2b835d68 RE |
3025 | return 1; |
3026 | } | |
f676971a | 3027 | |
2b835d68 RE |
3028 | return 0; |
3029 | } | |
f676971a EC |
3030 | #endif /* not ARM_WINCE */ |
3031 | ||
d5b7b3ae | 3032 | /* Return all other types in memory. */ |
2b835d68 RE |
3033 | return 1; |
3034 | } | |
3035 | ||
d6b4baa4 | 3036 | /* Indicate whether or not words of a double are in big-endian order. */ |
3717da94 JT |
3037 | |
3038 | int | |
e32bac5b | 3039 | arm_float_words_big_endian (void) |
3717da94 | 3040 | { |
9b66ebb1 | 3041 | if (TARGET_MAVERICK) |
9b6b54e2 | 3042 | return 0; |
3717da94 JT |
3043 | |
3044 | /* For FPA, float words are always big-endian. For VFP, floats words | |
3045 | follow the memory system mode. */ | |
3046 | ||
9b66ebb1 | 3047 | if (TARGET_FPA) |
3717da94 | 3048 | { |
3717da94 JT |
3049 | return 1; |
3050 | } | |
3051 | ||
3052 | if (TARGET_VFP) | |
3053 | return (TARGET_BIG_END ? 1 : 0); | |
3054 | ||
3055 | return 1; | |
3056 | } | |
3057 | ||
82e9d970 PB |
3058 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
3059 | for a call to a function whose data type is FNTYPE. | |
3060 | For a library call, FNTYPE is NULL. */ | |
3061 | void | |
f676971a | 3062 | arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, |
e32bac5b RE |
3063 | rtx libname ATTRIBUTE_UNUSED, |
3064 | tree fndecl ATTRIBUTE_UNUSED) | |
82e9d970 PB |
3065 | { |
3066 | /* On the ARM, the offset starts at 0. */ | |
29e339b9 | 3067 | pcum->nregs = 0; |
5a9335ef | 3068 | pcum->iwmmxt_nregs = 0; |
5848830f | 3069 | pcum->can_split = true; |
f676971a | 3070 | |
5a9335ef NC |
3071 | /* Varargs vectors are treated the same as long long. |
3072 | named_count avoids having to change the way arm handles 'named' */ | |
3073 | pcum->named_count = 0; | |
3074 | pcum->nargs = 0; | |
3075 | ||
3076 | if (TARGET_REALLY_IWMMXT && fntype) | |
3077 | { | |
3078 | tree fn_arg; | |
3079 | ||
3080 | for (fn_arg = TYPE_ARG_TYPES (fntype); | |
3081 | fn_arg; | |
3082 | fn_arg = TREE_CHAIN (fn_arg)) | |
3083 | pcum->named_count += 1; | |
3084 | ||
3085 | if (! pcum->named_count) | |
3086 | pcum->named_count = INT_MAX; | |
3087 | } | |
82e9d970 PB |
3088 | } |
3089 | ||
5848830f PB |
3090 | |
3091 | /* Return true if mode/type need doubleword alignment. */ | |
3092 | bool | |
3093 | arm_needs_doubleword_align (enum machine_mode mode, tree type) | |
3094 | { | |
65a939f7 PB |
3095 | return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY |
3096 | || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); | |
5848830f PB |
3097 | } |
3098 | ||
3099 | ||
82e9d970 PB |
3100 | /* Determine where to put an argument to a function. |
3101 | Value is zero to push the argument on the stack, | |
3102 | or a hard register in which to store the argument. | |
3103 | ||
3104 | MODE is the argument's machine mode. | |
3105 | TYPE is the data type of the argument (as a tree). | |
3106 | This is null for libcalls where that information may | |
3107 | not be available. | |
3108 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3109 | the preceding args and about the function being called. | |
3110 | NAMED is nonzero if this argument is a named parameter | |
3111 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1d6e90ac | 3112 | |
82e9d970 | 3113 | rtx |
e32bac5b | 3114 | arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
5848830f | 3115 | tree type, int named) |
82e9d970 | 3116 | { |
5848830f PB |
3117 | int nregs; |
3118 | ||
3119 | /* Varargs vectors are treated the same as long long. | |
3120 | named_count avoids having to change the way arm handles 'named' */ | |
3121 | if (TARGET_IWMMXT_ABI | |
f676971a | 3122 | && arm_vector_mode_supported_p (mode) |
5848830f | 3123 | && pcum->named_count > pcum->nargs + 1) |
5a9335ef | 3124 | { |
5848830f PB |
3125 | if (pcum->iwmmxt_nregs <= 9) |
3126 | return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); | |
3127 | else | |
5a9335ef | 3128 | { |
5848830f PB |
3129 | pcum->can_split = false; |
3130 | return NULL_RTX; | |
5a9335ef | 3131 | } |
5a9335ef NC |
3132 | } |
3133 | ||
5848830f PB |
3134 | /* Put doubleword aligned quantities in even register pairs. */ |
3135 | if (pcum->nregs & 1 | |
3136 | && ARM_DOUBLEWORD_ALIGN | |
3137 | && arm_needs_doubleword_align (mode, type)) | |
3138 | pcum->nregs++; | |
3139 | ||
82e9d970 | 3140 | if (mode == VOIDmode) |
25a65198 RS |
3141 | /* Pick an arbitrary value for operand 2 of the call insn. */ |
3142 | return const0_rtx; | |
5848830f | 3143 | |
666c27b9 | 3144 | /* Only allow splitting an arg between regs and memory if all preceding |
5848830f PB |
3145 | args were allocated to regs. For args passed by reference we only count |
3146 | the reference pointer. */ | |
3147 | if (pcum->can_split) | |
3148 | nregs = 1; | |
3149 | else | |
3150 | nregs = ARM_NUM_REGS2 (mode, type); | |
3151 | ||
3152 | if (!named || pcum->nregs + nregs > NUM_ARG_REGS) | |
82e9d970 | 3153 | return NULL_RTX; |
f676971a | 3154 | |
82e9d970 PB |
3155 | return gen_rtx_REG (mode, pcum->nregs); |
3156 | } | |
1741620c | 3157 | |
78a52f11 RH |
3158 | static int |
3159 | arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
3160 | tree type, bool named ATTRIBUTE_UNUSED) | |
3161 | { | |
3162 | int nregs = pcum->nregs; | |
3163 | ||
88f77cba | 3164 | if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode)) |
78a52f11 RH |
3165 | return 0; |
3166 | ||
3167 | if (NUM_ARG_REGS > nregs | |
3168 | && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type)) | |
3169 | && pcum->can_split) | |
3170 | return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
3171 | ||
3172 | return 0; | |
3173 | } | |
3174 | ||
1741620c JD |
3175 | /* Variable sized types are passed by reference. This is a GCC |
3176 | extension to the ARM ABI. */ | |
3177 | ||
8cd5a4e0 RH |
3178 | static bool |
3179 | arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
3180 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
586de218 | 3181 | const_tree type, bool named ATTRIBUTE_UNUSED) |
1741620c JD |
3182 | { |
3183 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
3184 | } | |
82e9d970 | 3185 | \f |
c27ba912 DM |
3186 | /* Encode the current state of the #pragma [no_]long_calls. */ |
3187 | typedef enum | |
82e9d970 | 3188 | { |
6fc0bb99 | 3189 | OFF, /* No #pragma [no_]long_calls is in effect. */ |
c27ba912 DM |
3190 | LONG, /* #pragma long_calls is in effect. */ |
3191 | SHORT /* #pragma no_long_calls is in effect. */ | |
3192 | } arm_pragma_enum; | |
82e9d970 | 3193 | |
c27ba912 | 3194 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 3195 | |
8b97c5f8 | 3196 | void |
e32bac5b | 3197 | arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
82e9d970 | 3198 | { |
8b97c5f8 ZW |
3199 | arm_pragma_long_calls = LONG; |
3200 | } | |
3201 | ||
3202 | void | |
e32bac5b | 3203 | arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
3204 | { |
3205 | arm_pragma_long_calls = SHORT; | |
3206 | } | |
3207 | ||
3208 | void | |
e32bac5b | 3209 | arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
3210 | { |
3211 | arm_pragma_long_calls = OFF; | |
82e9d970 PB |
3212 | } |
3213 | \f | |
91d231cb JM |
3214 | /* Table of machine attributes. */ |
3215 | const struct attribute_spec arm_attribute_table[] = | |
82e9d970 | 3216 | { |
91d231cb | 3217 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
82e9d970 PB |
3218 | /* Function calls made to this symbol must be done indirectly, because |
3219 | it may lie outside of the 26 bit addressing range of a normal function | |
3220 | call. */ | |
91d231cb | 3221 | { "long_call", 0, 0, false, true, true, NULL }, |
82e9d970 PB |
3222 | /* Whereas these functions are always known to reside within the 26 bit |
3223 | addressing range. */ | |
91d231cb | 3224 | { "short_call", 0, 0, false, true, true, NULL }, |
f676971a | 3225 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
91d231cb JM |
3226 | { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, |
3227 | { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, | |
3228 | { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
3229 | #ifdef ARM_PE | |
3230 | /* ARM/PE has three new attributes: | |
3231 | interfacearm - ? | |
3232 | dllexport - for exporting a function/variable that will live in a dll | |
3233 | dllimport - for importing a function/variable from a dll | |
3234 | ||
3235 | Microsoft allows multiple declspecs in one __declspec, separating | |
3236 | them with spaces. We do NOT support this. Instead, use __declspec | |
3237 | multiple times. | |
3238 | */ | |
3239 | { "dllimport", 0, 0, true, false, false, NULL }, | |
3240 | { "dllexport", 0, 0, true, false, false, NULL }, | |
3241 | { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
b2ca3702 MM |
3242 | #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES |
3243 | { "dllimport", 0, 0, false, false, false, handle_dll_attribute }, | |
3244 | { "dllexport", 0, 0, false, false, false, handle_dll_attribute }, | |
04fb56d5 | 3245 | { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute }, |
91d231cb JM |
3246 | #endif |
3247 | { NULL, 0, 0, false, false, false, NULL } | |
3248 | }; | |
6d3d9133 | 3249 | |
91d231cb JM |
3250 | /* Handle an attribute requiring a FUNCTION_DECL; |
3251 | arguments as in struct attribute_spec.handler. */ | |
3252 | static tree | |
e32bac5b RE |
3253 | arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, |
3254 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
3255 | { |
3256 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
3257 | { | |
5c498b10 | 3258 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
91d231cb JM |
3259 | IDENTIFIER_POINTER (name)); |
3260 | *no_add_attrs = true; | |
3261 | } | |
3262 | ||
3263 | return NULL_TREE; | |
3264 | } | |
3265 | ||
3266 | /* Handle an "interrupt" or "isr" attribute; | |
3267 | arguments as in struct attribute_spec.handler. */ | |
3268 | static tree | |
e32bac5b RE |
3269 | arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, |
3270 | bool *no_add_attrs) | |
91d231cb JM |
3271 | { |
3272 | if (DECL_P (*node)) | |
3273 | { | |
3274 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
3275 | { | |
5c498b10 | 3276 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
91d231cb JM |
3277 | IDENTIFIER_POINTER (name)); |
3278 | *no_add_attrs = true; | |
3279 | } | |
3280 | /* FIXME: the argument if any is checked for type attributes; | |
3281 | should it be checked for decl ones? */ | |
3282 | } | |
3283 | else | |
3284 | { | |
3285 | if (TREE_CODE (*node) == FUNCTION_TYPE | |
3286 | || TREE_CODE (*node) == METHOD_TYPE) | |
3287 | { | |
3288 | if (arm_isr_value (args) == ARM_FT_UNKNOWN) | |
3289 | { | |
5c498b10 DD |
3290 | warning (OPT_Wattributes, "%qs attribute ignored", |
3291 | IDENTIFIER_POINTER (name)); | |
91d231cb JM |
3292 | *no_add_attrs = true; |
3293 | } | |
3294 | } | |
3295 | else if (TREE_CODE (*node) == POINTER_TYPE | |
3296 | && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE | |
3297 | || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) | |
3298 | && arm_isr_value (args) != ARM_FT_UNKNOWN) | |
3299 | { | |
8dd16ecc | 3300 | *node = build_variant_type_copy (*node); |
1d6e90ac NC |
3301 | TREE_TYPE (*node) = build_type_attribute_variant |
3302 | (TREE_TYPE (*node), | |
3303 | tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); | |
91d231cb JM |
3304 | *no_add_attrs = true; |
3305 | } | |
3306 | else | |
3307 | { | |
3308 | /* Possibly pass this attribute on from the type to a decl. */ | |
3309 | if (flags & ((int) ATTR_FLAG_DECL_NEXT | |
3310 | | (int) ATTR_FLAG_FUNCTION_NEXT | |
3311 | | (int) ATTR_FLAG_ARRAY_NEXT)) | |
3312 | { | |
3313 | *no_add_attrs = true; | |
3314 | return tree_cons (name, args, NULL_TREE); | |
3315 | } | |
3316 | else | |
3317 | { | |
5c498b10 DD |
3318 | warning (OPT_Wattributes, "%qs attribute ignored", |
3319 | IDENTIFIER_POINTER (name)); | |
91d231cb JM |
3320 | } |
3321 | } | |
3322 | } | |
3323 | ||
3324 | return NULL_TREE; | |
82e9d970 PB |
3325 | } |
3326 | ||
7bff66a7 | 3327 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 MM |
3328 | /* Handle the "notshared" attribute. This attribute is another way of |
3329 | requesting hidden visibility. ARM's compiler supports | |
3330 | "__declspec(notshared)"; we support the same thing via an | |
3331 | attribute. */ | |
3332 | ||
3333 | static tree | |
e0b92319 NC |
3334 | arm_handle_notshared_attribute (tree *node, |
3335 | tree name ATTRIBUTE_UNUSED, | |
3336 | tree args ATTRIBUTE_UNUSED, | |
3337 | int flags ATTRIBUTE_UNUSED, | |
04fb56d5 MM |
3338 | bool *no_add_attrs) |
3339 | { | |
3340 | tree decl = TYPE_NAME (*node); | |
3341 | ||
3342 | if (decl) | |
3343 | { | |
3344 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
3345 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
3346 | *no_add_attrs = false; | |
3347 | } | |
3348 | return NULL_TREE; | |
3349 | } | |
7bff66a7 | 3350 | #endif |
04fb56d5 | 3351 | |
82e9d970 PB |
3352 | /* Return 0 if the attributes for two types are incompatible, 1 if they |
3353 | are compatible, and 2 if they are nearly compatible (which causes a | |
3354 | warning to be generated). */ | |
8d8e52be | 3355 | static int |
3101faab | 3356 | arm_comp_type_attributes (const_tree type1, const_tree type2) |
82e9d970 | 3357 | { |
1cb8d58a | 3358 | int l1, l2, s1, s2; |
f676971a | 3359 | |
82e9d970 PB |
3360 | /* Check for mismatch of non-default calling convention. */ |
3361 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
3362 | return 1; | |
3363 | ||
3364 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
3365 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
3366 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
3367 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
3368 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
3369 | |
3370 | /* Only bother to check if an attribute is defined. */ | |
3371 | if (l1 | l2 | s1 | s2) | |
3372 | { | |
3373 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 3374 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 3375 | return 0; |
82e9d970 | 3376 | |
bd7fc26f NC |
3377 | /* Disallow mixed attributes. */ |
3378 | if ((l1 & s2) || (l2 & s1)) | |
3379 | return 0; | |
3380 | } | |
f676971a | 3381 | |
6d3d9133 NC |
3382 | /* Check for mismatched ISR attribute. */ |
3383 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
3384 | if (! l1) | |
3385 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
3386 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
3387 | if (! l2) | |
3388 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
3389 | if (l1 != l2) | |
3390 | return 0; | |
3391 | ||
bd7fc26f | 3392 | return 1; |
82e9d970 PB |
3393 | } |
3394 | ||
c27ba912 DM |
3395 | /* Assigns default attributes to newly defined type. This is used to |
3396 | set short_call/long_call attributes for function types of | |
3397 | functions defined inside corresponding #pragma scopes. */ | |
8d8e52be | 3398 | static void |
e32bac5b | 3399 | arm_set_default_type_attributes (tree type) |
c27ba912 DM |
3400 | { |
3401 | /* Add __attribute__ ((long_call)) to all functions, when | |
3402 | inside #pragma long_calls or __attribute__ ((short_call)), | |
3403 | when inside #pragma no_long_calls. */ | |
3404 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
3405 | { | |
3406 | tree type_attr_list, attr_name; | |
3407 | type_attr_list = TYPE_ATTRIBUTES (type); | |
3408 | ||
3409 | if (arm_pragma_long_calls == LONG) | |
3410 | attr_name = get_identifier ("long_call"); | |
3411 | else if (arm_pragma_long_calls == SHORT) | |
3412 | attr_name = get_identifier ("short_call"); | |
3413 | else | |
3414 | return; | |
3415 | ||
3416 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
3417 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
3418 | } | |
3419 | } | |
3420 | \f | |
25a65198 RS |
3421 | /* Return true if DECL is known to be linked into section SECTION. */ |
3422 | ||
3423 | static bool | |
3424 | arm_function_in_section_p (tree decl, section *section) | |
c27ba912 | 3425 | { |
25a65198 RS |
3426 | /* We can only be certain about functions defined in the same |
3427 | compilation unit. */ | |
3428 | if (!TREE_STATIC (decl)) | |
3429 | return false; | |
c27ba912 | 3430 | |
25a65198 RS |
3431 | /* Make sure that SYMBOL always binds to the definition in this |
3432 | compilation unit. */ | |
3433 | if (!targetm.binds_local_p (decl)) | |
3434 | return false; | |
c27ba912 | 3435 | |
25a65198 RS |
3436 | /* If DECL_SECTION_NAME is set, assume it is trustworthy. */ |
3437 | if (!DECL_SECTION_NAME (decl)) | |
3438 | { | |
25a65198 RS |
3439 | /* Make sure that we will not create a unique section for DECL. */ |
3440 | if (flag_function_sections || DECL_ONE_ONLY (decl)) | |
3441 | return false; | |
3442 | } | |
3443 | ||
3444 | return function_section (decl) == section; | |
c27ba912 DM |
3445 | } |
3446 | ||
a50aa827 | 3447 | /* Return nonzero if a 32-bit "long_call" should be generated for |
25a65198 RS |
3448 | a call from the current function to DECL. We generate a long_call |
3449 | if the function: | |
c27ba912 DM |
3450 | |
3451 | a. has an __attribute__((long call)) | |
3452 | or b. is within the scope of a #pragma long_calls | |
3453 | or c. the -mlong-calls command line switch has been specified | |
3454 | ||
3455 | However we do not generate a long call if the function: | |
f676971a | 3456 | |
c27ba912 DM |
3457 | d. has an __attribute__ ((short_call)) |
3458 | or e. is inside the scope of a #pragma no_long_calls | |
25a65198 | 3459 | or f. is defined in the same section as the current function. */ |
c27ba912 | 3460 | |
25a65198 RS |
3461 | bool |
3462 | arm_is_long_call_p (tree decl) | |
3463 | { | |
3464 | tree attrs; | |
c27ba912 | 3465 | |
25a65198 RS |
3466 | if (!decl) |
3467 | return TARGET_LONG_CALLS; | |
c27ba912 | 3468 | |
25a65198 RS |
3469 | attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
3470 | if (lookup_attribute ("short_call", attrs)) | |
3471 | return false; | |
c27ba912 | 3472 | |
25a65198 RS |
3473 | /* For "f", be conservative, and only cater for cases in which the |
3474 | whole of the current function is placed in the same section. */ | |
3475 | if (!flag_reorder_blocks_and_partition | |
b3a796bc | 3476 | && TREE_CODE (decl) == FUNCTION_DECL |
25a65198 RS |
3477 | && arm_function_in_section_p (decl, current_function_section ())) |
3478 | return false; | |
a77655b1 | 3479 | |
25a65198 RS |
3480 | if (lookup_attribute ("long_call", attrs)) |
3481 | return true; | |
f676971a | 3482 | |
25a65198 | 3483 | return TARGET_LONG_CALLS; |
c27ba912 | 3484 | } |
f99fce0c | 3485 | |
825dda42 | 3486 | /* Return nonzero if it is ok to make a tail-call to DECL. */ |
4977bab6 | 3487 | static bool |
e32bac5b | 3488 | arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
f99fce0c | 3489 | { |
5b3e6663 | 3490 | unsigned long func_type; |
f99fce0c | 3491 | |
5a9335ef NC |
3492 | if (cfun->machine->sibcall_blocked) |
3493 | return false; | |
3494 | ||
f99fce0c RE |
3495 | /* Never tailcall something for which we have no decl, or if we |
3496 | are in Thumb mode. */ | |
3497 | if (decl == NULL || TARGET_THUMB) | |
4977bab6 | 3498 | return false; |
f99fce0c | 3499 | |
9403b7f7 RS |
3500 | /* The PIC register is live on entry to VxWorks PLT entries, so we |
3501 | must make the call before restoring the PIC register. */ | |
3502 | if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl)) | |
3503 | return false; | |
3504 | ||
f99fce0c | 3505 | /* Cannot tail-call to long calls, since these are out of range of |
25a65198 RS |
3506 | a branch instruction. */ |
3507 | if (arm_is_long_call_p (decl)) | |
4977bab6 | 3508 | return false; |
f99fce0c RE |
3509 | |
3510 | /* If we are interworking and the function is not declared static | |
f676971a | 3511 | then we can't tail-call it unless we know that it exists in this |
f99fce0c | 3512 | compilation unit (since it might be a Thumb routine). */ |
5895f793 | 3513 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
4977bab6 | 3514 | return false; |
f99fce0c | 3515 | |
5b3e6663 | 3516 | func_type = arm_current_func_type (); |
6d3d9133 | 3517 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
5b3e6663 PB |
3518 | if (IS_INTERRUPT (func_type)) |
3519 | return false; | |
3520 | ||
3521 | /* Never tailcall if function may be called with a misaligned SP. */ | |
3522 | if (IS_STACKALIGN (func_type)) | |
4977bab6 | 3523 | return false; |
6d3d9133 | 3524 | |
f99fce0c | 3525 | /* Everything else is ok. */ |
4977bab6 | 3526 | return true; |
f99fce0c RE |
3527 | } |
3528 | ||
82e9d970 | 3529 | \f |
6b990f6b RE |
3530 | /* Addressing mode support functions. */ |
3531 | ||
0b4be7de | 3532 | /* Return nonzero if X is a legitimate immediate operand when compiling |
020a4035 | 3533 | for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */ |
32de079a | 3534 | int |
e32bac5b | 3535 | legitimate_pic_operand_p (rtx x) |
32de079a | 3536 | { |
020a4035 RE |
3537 | if (GET_CODE (x) == SYMBOL_REF |
3538 | || (GET_CODE (x) == CONST | |
3539 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3540 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) | |
32de079a RE |
3541 | return 0; |
3542 | ||
3543 | return 1; | |
3544 | } | |
3545 | ||
9403b7f7 RS |
3546 | /* Record that the current function needs a PIC register. Initialize |
3547 | cfun->machine->pic_reg if we have not already done so. */ | |
3548 | ||
3549 | static void | |
3550 | require_pic_register (void) | |
3551 | { | |
3552 | /* A lot of the logic here is made obscure by the fact that this | |
3553 | routine gets called as part of the rtx cost estimation process. | |
3554 | We don't want those calls to affect any assumptions about the real | |
3555 | function; and further, we can't call entry_of_function() until we | |
3556 | start the real expansion process. */ | |
e3b5732b | 3557 | if (!crtl->uses_pic_offset_table) |
9403b7f7 | 3558 | { |
b3a13419 | 3559 | gcc_assert (can_create_pseudo_p ()); |
9403b7f7 RS |
3560 | if (arm_pic_register != INVALID_REGNUM) |
3561 | { | |
6d2538f5 JB |
3562 | if (!cfun->machine->pic_reg) |
3563 | cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); | |
9403b7f7 RS |
3564 | |
3565 | /* Play games to avoid marking the function as needing pic | |
3566 | if we are being called as part of the cost-estimation | |
3567 | process. */ | |
3568 | if (current_ir_type () != IR_GIMPLE) | |
e3b5732b | 3569 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
3570 | } |
3571 | else | |
3572 | { | |
3573 | rtx seq; | |
3574 | ||
6d2538f5 JB |
3575 | if (!cfun->machine->pic_reg) |
3576 | cfun->machine->pic_reg = gen_reg_rtx (Pmode); | |
9403b7f7 RS |
3577 | |
3578 | /* Play games to avoid marking the function as needing pic | |
3579 | if we are being called as part of the cost-estimation | |
3580 | process. */ | |
3581 | if (current_ir_type () != IR_GIMPLE) | |
3582 | { | |
e3b5732b | 3583 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
3584 | start_sequence (); |
3585 | ||
3586 | arm_load_pic_register (0UL); | |
3587 | ||
3588 | seq = get_insns (); | |
3589 | end_sequence (); | |
3590 | emit_insn_after (seq, entry_of_function ()); | |
3591 | } | |
3592 | } | |
3593 | } | |
3594 | } | |
3595 | ||
32de079a | 3596 | rtx |
e32bac5b | 3597 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
32de079a | 3598 | { |
a3c48721 RE |
3599 | if (GET_CODE (orig) == SYMBOL_REF |
3600 | || GET_CODE (orig) == LABEL_REF) | |
32de079a RE |
3601 | { |
3602 | rtx pic_ref, address; | |
3603 | rtx insn; | |
3604 | int subregs = 0; | |
3605 | ||
9403b7f7 RS |
3606 | /* If this function doesn't have a pic register, create one now. */ |
3607 | require_pic_register (); | |
020a4035 | 3608 | |
32de079a RE |
3609 | if (reg == 0) |
3610 | { | |
b3a13419 | 3611 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 3612 | reg = gen_reg_rtx (Pmode); |
32de079a RE |
3613 | |
3614 | subregs = 1; | |
3615 | } | |
3616 | ||
32de079a RE |
3617 | if (subregs) |
3618 | address = gen_reg_rtx (Pmode); | |
3619 | else | |
3620 | address = reg; | |
3621 | ||
4bec9f7d NC |
3622 | if (TARGET_ARM) |
3623 | emit_insn (gen_pic_load_addr_arm (address, orig)); | |
5b3e6663 PB |
3624 | else if (TARGET_THUMB2) |
3625 | emit_insn (gen_pic_load_addr_thumb2 (address, orig)); | |
3626 | else /* TARGET_THUMB1 */ | |
3627 | emit_insn (gen_pic_load_addr_thumb1 (address, orig)); | |
32de079a | 3628 | |
9403b7f7 RS |
3629 | /* VxWorks does not impose a fixed gap between segments; the run-time |
3630 | gap can be different from the object-file gap. We therefore can't | |
3631 | use GOTOFF unless we are absolutely sure that the symbol is in the | |
3632 | same segment as the GOT. Unfortunately, the flexibility of linker | |
3633 | scripts means that we can't be sure of that in general, so assume | |
3634 | that GOTOFF is never valid on VxWorks. */ | |
14f583b8 | 3635 | if ((GET_CODE (orig) == LABEL_REF |
f676971a | 3636 | || (GET_CODE (orig) == SYMBOL_REF && |
94428622 | 3637 | SYMBOL_REF_LOCAL_P (orig))) |
9403b7f7 RS |
3638 | && NEED_GOT_RELOC |
3639 | && !TARGET_VXWORKS_RTP) | |
020a4035 | 3640 | pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address); |
a3c48721 RE |
3641 | else |
3642 | { | |
542a8afa | 3643 | pic_ref = gen_const_mem (Pmode, |
020a4035 | 3644 | gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, |
542a8afa | 3645 | address)); |
a3c48721 RE |
3646 | } |
3647 | ||
32de079a | 3648 | insn = emit_move_insn (reg, pic_ref); |
96a3900d | 3649 | |
32de079a RE |
3650 | /* Put a REG_EQUAL note on this insn, so that it can be optimized |
3651 | by loop. */ | |
bd94cb6e SB |
3652 | set_unique_reg_note (insn, REG_EQUAL, orig); |
3653 | ||
32de079a RE |
3654 | return reg; |
3655 | } | |
3656 | else if (GET_CODE (orig) == CONST) | |
3657 | { | |
3658 | rtx base, offset; | |
3659 | ||
3660 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
020a4035 | 3661 | && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg) |
32de079a RE |
3662 | return orig; |
3663 | ||
f67358da | 3664 | /* Handle the case where we have: const (UNSPEC_TLS). */ |
d3585b76 DJ |
3665 | if (GET_CODE (XEXP (orig, 0)) == UNSPEC |
3666 | && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS) | |
3667 | return orig; | |
3668 | ||
f67358da PB |
3669 | /* Handle the case where we have: |
3670 | const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a | |
3671 | CONST_INT. */ | |
3672 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
3673 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC | |
3674 | && XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS) | |
3675 | { | |
3676 | gcc_assert (GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT); | |
3677 | return orig; | |
3678 | } | |
3679 | ||
32de079a RE |
3680 | if (reg == 0) |
3681 | { | |
b3a13419 | 3682 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 3683 | reg = gen_reg_rtx (Pmode); |
32de079a RE |
3684 | } |
3685 | ||
e6d29d15 | 3686 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
e0b92319 | 3687 | |
e6d29d15 NS |
3688 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
3689 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
3690 | base == reg ? 0 : reg); | |
32de079a RE |
3691 | |
3692 | if (GET_CODE (offset) == CONST_INT) | |
3693 | { | |
3694 | /* The base register doesn't really matter, we only want to | |
3695 | test the index for the appropriate mode. */ | |
1e1ab407 | 3696 | if (!arm_legitimate_index_p (mode, offset, SET, 0)) |
6b990f6b | 3697 | { |
b3a13419 | 3698 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 3699 | offset = force_reg (Pmode, offset); |
6b990f6b | 3700 | } |
32de079a | 3701 | |
32de079a | 3702 | if (GET_CODE (offset) == CONST_INT) |
ed8908e7 | 3703 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
3704 | } |
3705 | ||
3706 | if (GET_MODE_SIZE (mode) > 4 | |
3707 | && (GET_MODE_CLASS (mode) == MODE_INT | |
3708 | || TARGET_SOFT_FLOAT)) | |
3709 | { | |
3710 | emit_insn (gen_addsi3 (reg, base, offset)); | |
3711 | return reg; | |
3712 | } | |
3713 | ||
43cffd11 | 3714 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a | 3715 | } |
32de079a RE |
3716 | |
3717 | return orig; | |
3718 | } | |
3719 | ||
57934c39 | 3720 | |
5b3e6663 | 3721 | /* Find a spare register to use during the prolog of a function. */ |
57934c39 PB |
3722 | |
3723 | static int | |
b279b20a | 3724 | thumb_find_work_register (unsigned long pushed_regs_mask) |
57934c39 PB |
3725 | { |
3726 | int reg; | |
3727 | ||
b279b20a NC |
3728 | /* Check the argument registers first as these are call-used. The |
3729 | register allocation order means that sometimes r3 might be used | |
3730 | but earlier argument registers might not, so check them all. */ | |
3731 | for (reg = LAST_ARG_REGNUM; reg >= 0; reg --) | |
6fb5fa3c | 3732 | if (!df_regs_ever_live_p (reg)) |
b279b20a NC |
3733 | return reg; |
3734 | ||
3735 | /* Before going on to check the call-saved registers we can try a couple | |
3736 | more ways of deducing that r3 is available. The first is when we are | |
3737 | pushing anonymous arguments onto the stack and we have less than 4 | |
3738 | registers worth of fixed arguments(*). In this case r3 will be part of | |
3739 | the variable argument list and so we can be sure that it will be | |
3740 | pushed right at the start of the function. Hence it will be available | |
3741 | for the rest of the prologue. | |
38173d38 | 3742 | (*): ie crtl->args.pretend_args_size is greater than 0. */ |
b279b20a | 3743 | if (cfun->machine->uses_anonymous_args |
38173d38 | 3744 | && crtl->args.pretend_args_size > 0) |
57934c39 PB |
3745 | return LAST_ARG_REGNUM; |
3746 | ||
b279b20a NC |
3747 | /* The other case is when we have fixed arguments but less than 4 registers |
3748 | worth. In this case r3 might be used in the body of the function, but | |
3749 | it is not being used to convey an argument into the function. In theory | |
38173d38 | 3750 | we could just check crtl->args.size to see how many bytes are |
b279b20a NC |
3751 | being passed in argument registers, but it seems that it is unreliable. |
3752 | Sometimes it will have the value 0 when in fact arguments are being | |
3753 | passed. (See testcase execute/20021111-1.c for an example). So we also | |
3754 | check the args_info.nregs field as well. The problem with this field is | |
3755 | that it makes no allowances for arguments that are passed to the | |
3756 | function but which are not used. Hence we could miss an opportunity | |
3757 | when a function has an unused argument in r3. But it is better to be | |
3758 | safe than to be sorry. */ | |
3759 | if (! cfun->machine->uses_anonymous_args | |
38173d38 JH |
3760 | && crtl->args.size >= 0 |
3761 | && crtl->args.size <= (LAST_ARG_REGNUM * UNITS_PER_WORD) | |
f6d2671e | 3762 | && crtl->args.info.nregs < 4) |
b279b20a | 3763 | return LAST_ARG_REGNUM; |
e0b92319 | 3764 | |
b279b20a NC |
3765 | /* Otherwise look for a call-saved register that is going to be pushed. */ |
3766 | for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --) | |
3767 | if (pushed_regs_mask & (1 << reg)) | |
57934c39 PB |
3768 | return reg; |
3769 | ||
5b3e6663 PB |
3770 | if (TARGET_THUMB2) |
3771 | { | |
3772 | /* Thumb-2 can use high regs. */ | |
3773 | for (reg = FIRST_HI_REGNUM; reg < 15; reg ++) | |
3774 | if (pushed_regs_mask & (1 << reg)) | |
3775 | return reg; | |
3776 | } | |
b279b20a NC |
3777 | /* Something went wrong - thumb_compute_save_reg_mask() |
3778 | should have arranged for a suitable register to be pushed. */ | |
e6d29d15 | 3779 | gcc_unreachable (); |
57934c39 PB |
3780 | } |
3781 | ||
f16fe45f | 3782 | static GTY(()) int pic_labelno; |
876f13b0 | 3783 | |
fe013435 PB |
3784 | /* Generate code to load the PIC register. In thumb mode SCRATCH is a |
3785 | low register. */ | |
876f13b0 | 3786 | |
32de079a | 3787 | void |
e55ef7f4 | 3788 | arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) |
32de079a | 3789 | { |
f9bd1a89 | 3790 | rtx l1, labelno, pic_tmp, pic_rtx, pic_reg; |
32de079a | 3791 | |
e3b5732b | 3792 | if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
3793 | return; |
3794 | ||
e6d29d15 | 3795 | gcc_assert (flag_pic); |
32de079a | 3796 | |
9403b7f7 RS |
3797 | pic_reg = cfun->machine->pic_reg; |
3798 | if (TARGET_VXWORKS_RTP) | |
3799 | { | |
3800 | pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE); | |
3801 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); | |
3802 | emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx)); | |
43cffd11 | 3803 | |
9403b7f7 | 3804 | emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg))); |
f676971a | 3805 | |
9403b7f7 RS |
3806 | pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX); |
3807 | emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp)); | |
4bec9f7d | 3808 | } |
9403b7f7 | 3809 | else |
5b3e6663 | 3810 | { |
9403b7f7 RS |
3811 | /* We use an UNSPEC rather than a LABEL_REF because this label |
3812 | never appears in the code stream. */ | |
3813 | ||
3814 | labelno = GEN_INT (pic_labelno++); | |
3815 | l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
3816 | l1 = gen_rtx_CONST (VOIDmode, l1); | |
3817 | ||
9403b7f7 RS |
3818 | /* On the ARM the PC register contains 'dot + 8' at the time of the |
3819 | addition, on the Thumb it is 'dot + 4'. */ | |
f9bd1a89 RS |
3820 | pic_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4); |
3821 | pic_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, pic_rtx), | |
3822 | UNSPEC_GOTSYM_OFF); | |
9403b7f7 RS |
3823 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); |
3824 | ||
3825 | if (TARGET_ARM) | |
5b3e6663 | 3826 | { |
9403b7f7 RS |
3827 | emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx)); |
3828 | emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno)); | |
5b3e6663 | 3829 | } |
9403b7f7 RS |
3830 | else if (TARGET_THUMB2) |
3831 | { | |
3832 | /* Thumb-2 only allows very limited access to the PC. Calculate the | |
3833 | address in a temporary register. */ | |
3834 | if (arm_pic_register != INVALID_REGNUM) | |
3835 | { | |
3836 | pic_tmp = gen_rtx_REG (SImode, | |
3837 | thumb_find_work_register (saved_regs)); | |
3838 | } | |
3839 | else | |
3840 | { | |
b3a13419 | 3841 | gcc_assert (can_create_pseudo_p ()); |
9403b7f7 RS |
3842 | pic_tmp = gen_reg_rtx (Pmode); |
3843 | } | |
5b3e6663 | 3844 | |
9403b7f7 RS |
3845 | emit_insn (gen_pic_load_addr_thumb2 (pic_reg, pic_rtx)); |
3846 | emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno)); | |
3847 | emit_insn (gen_addsi3 (pic_reg, pic_reg, pic_tmp)); | |
3848 | } | |
3849 | else /* TARGET_THUMB1 */ | |
876f13b0 | 3850 | { |
9403b7f7 RS |
3851 | if (arm_pic_register != INVALID_REGNUM |
3852 | && REGNO (pic_reg) > LAST_LO_REGNUM) | |
3853 | { | |
3854 | /* We will have pushed the pic register, so we should always be | |
3855 | able to find a work register. */ | |
3856 | pic_tmp = gen_rtx_REG (SImode, | |
3857 | thumb_find_work_register (saved_regs)); | |
3858 | emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx)); | |
3859 | emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); | |
3860 | } | |
3861 | else | |
3862 | emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx)); | |
3863 | emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); | |
876f13b0 | 3864 | } |
4bec9f7d | 3865 | } |
32de079a | 3866 | |
32de079a RE |
3867 | /* Need to emit this whether or not we obey regdecls, |
3868 | since setjmp/longjmp can cause life info to screw up. */ | |
c41c1387 | 3869 | emit_use (pic_reg); |
32de079a RE |
3870 | } |
3871 | ||
876f13b0 | 3872 | |
6b990f6b RE |
3873 | /* Return nonzero if X is valid as an ARM state addressing register. */ |
3874 | static int | |
e32bac5b | 3875 | arm_address_register_rtx_p (rtx x, int strict_p) |
6b990f6b RE |
3876 | { |
3877 | int regno; | |
3878 | ||
3879 | if (GET_CODE (x) != REG) | |
3880 | return 0; | |
3881 | ||
3882 | regno = REGNO (x); | |
3883 | ||
3884 | if (strict_p) | |
3885 | return ARM_REGNO_OK_FOR_BASE_P (regno); | |
3886 | ||
3887 | return (regno <= LAST_ARM_REGNUM | |
3888 | || regno >= FIRST_PSEUDO_REGISTER | |
3889 | || regno == FRAME_POINTER_REGNUM | |
3890 | || regno == ARG_POINTER_REGNUM); | |
3891 | } | |
3892 | ||
d3585b76 DJ |
3893 | /* Return TRUE if this rtx is the difference of a symbol and a label, |
3894 | and will reduce to a PC-relative relocation in the object file. | |
3895 | Expressions like this can be left alone when generating PIC, rather | |
3896 | than forced through the GOT. */ | |
3897 | static int | |
3898 | pcrel_constant_p (rtx x) | |
3899 | { | |
3900 | if (GET_CODE (x) == MINUS) | |
3901 | return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1)); | |
3902 | ||
3903 | return FALSE; | |
3904 | } | |
3905 | ||
6b990f6b RE |
3906 | /* Return nonzero if X is a valid ARM state address operand. */ |
3907 | int | |
1e1ab407 RE |
3908 | arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer, |
3909 | int strict_p) | |
6b990f6b | 3910 | { |
fdd695fd PB |
3911 | bool use_ldrd; |
3912 | enum rtx_code code = GET_CODE (x); | |
f676971a | 3913 | |
6b990f6b RE |
3914 | if (arm_address_register_rtx_p (x, strict_p)) |
3915 | return 1; | |
3916 | ||
fdd695fd PB |
3917 | use_ldrd = (TARGET_LDRD |
3918 | && (mode == DImode | |
3919 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
3920 | ||
3921 | if (code == POST_INC || code == PRE_DEC | |
3922 | || ((code == PRE_INC || code == POST_DEC) | |
3923 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
6b990f6b RE |
3924 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); |
3925 | ||
fdd695fd | 3926 | else if ((code == POST_MODIFY || code == PRE_MODIFY) |
6b990f6b RE |
3927 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) |
3928 | && GET_CODE (XEXP (x, 1)) == PLUS | |
386d3a16 | 3929 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
fdd695fd PB |
3930 | { |
3931 | rtx addend = XEXP (XEXP (x, 1), 1); | |
3932 | ||
112cdef5 | 3933 | /* Don't allow ldrd post increment by register because it's hard |
fdd695fd PB |
3934 | to fixup invalid register choices. */ |
3935 | if (use_ldrd | |
3936 | && GET_CODE (x) == POST_MODIFY | |
3937 | && GET_CODE (addend) == REG) | |
3938 | return 0; | |
3939 | ||
3940 | return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) | |
3941 | && arm_legitimate_index_p (mode, addend, outer, strict_p)); | |
3942 | } | |
6b990f6b RE |
3943 | |
3944 | /* After reload constants split into minipools will have addresses | |
3945 | from a LABEL_REF. */ | |
0bfb39ef | 3946 | else if (reload_completed |
fdd695fd PB |
3947 | && (code == LABEL_REF |
3948 | || (code == CONST | |
6b990f6b RE |
3949 | && GET_CODE (XEXP (x, 0)) == PLUS |
3950 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
3951 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
3952 | return 1; | |
3953 | ||
88f77cba | 3954 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
6b990f6b RE |
3955 | return 0; |
3956 | ||
fdd695fd | 3957 | else if (code == PLUS) |
6b990f6b RE |
3958 | { |
3959 | rtx xop0 = XEXP (x, 0); | |
3960 | rtx xop1 = XEXP (x, 1); | |
3961 | ||
3962 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
01577df7 | 3963 | && GET_CODE(xop1) == CONST_INT |
1e1ab407 | 3964 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)) |
6b990f6b | 3965 | || (arm_address_register_rtx_p (xop1, strict_p) |
1e1ab407 | 3966 | && arm_legitimate_index_p (mode, xop0, outer, strict_p))); |
6b990f6b RE |
3967 | } |
3968 | ||
3969 | #if 0 | |
3970 | /* Reload currently can't handle MINUS, so disable this for now */ | |
3971 | else if (GET_CODE (x) == MINUS) | |
3972 | { | |
3973 | rtx xop0 = XEXP (x, 0); | |
3974 | rtx xop1 = XEXP (x, 1); | |
3975 | ||
3976 | return (arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 3977 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)); |
6b990f6b RE |
3978 | } |
3979 | #endif | |
3980 | ||
3981 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
fdd695fd | 3982 | && code == SYMBOL_REF |
6b990f6b RE |
3983 | && CONSTANT_POOL_ADDRESS_P (x) |
3984 | && ! (flag_pic | |
d3585b76 DJ |
3985 | && symbol_mentioned_p (get_pool_constant (x)) |
3986 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
6b990f6b RE |
3987 | return 1; |
3988 | ||
6b990f6b RE |
3989 | return 0; |
3990 | } | |
3991 | ||
5b3e6663 PB |
3992 | /* Return nonzero if X is a valid Thumb-2 address operand. */ |
3993 | int | |
3994 | thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) | |
3995 | { | |
3996 | bool use_ldrd; | |
3997 | enum rtx_code code = GET_CODE (x); | |
3998 | ||
3999 | if (arm_address_register_rtx_p (x, strict_p)) | |
4000 | return 1; | |
4001 | ||
4002 | use_ldrd = (TARGET_LDRD | |
4003 | && (mode == DImode | |
4004 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
4005 | ||
4006 | if (code == POST_INC || code == PRE_DEC | |
4007 | || ((code == PRE_INC || code == POST_DEC) | |
4008 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
4009 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); | |
4010 | ||
4011 | else if ((code == POST_MODIFY || code == PRE_MODIFY) | |
4012 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) | |
4013 | && GET_CODE (XEXP (x, 1)) == PLUS | |
4014 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) | |
4015 | { | |
4016 | /* Thumb-2 only has autoincrement by constant. */ | |
4017 | rtx addend = XEXP (XEXP (x, 1), 1); | |
4018 | HOST_WIDE_INT offset; | |
4019 | ||
4020 | if (GET_CODE (addend) != CONST_INT) | |
4021 | return 0; | |
4022 | ||
4023 | offset = INTVAL(addend); | |
4024 | if (GET_MODE_SIZE (mode) <= 4) | |
4025 | return (offset > -256 && offset < 256); | |
4026 | ||
4027 | return (use_ldrd && offset > -1024 && offset < 1024 | |
4028 | && (offset & 3) == 0); | |
4029 | } | |
4030 | ||
4031 | /* After reload constants split into minipools will have addresses | |
4032 | from a LABEL_REF. */ | |
4033 | else if (reload_completed | |
4034 | && (code == LABEL_REF | |
4035 | || (code == CONST | |
4036 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4037 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
4038 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
4039 | return 1; | |
4040 | ||
88f77cba | 4041 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
5b3e6663 PB |
4042 | return 0; |
4043 | ||
4044 | else if (code == PLUS) | |
4045 | { | |
4046 | rtx xop0 = XEXP (x, 0); | |
4047 | rtx xop1 = XEXP (x, 1); | |
4048 | ||
4049 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
4050 | && thumb2_legitimate_index_p (mode, xop1, strict_p)) | |
4051 | || (arm_address_register_rtx_p (xop1, strict_p) | |
4052 | && thumb2_legitimate_index_p (mode, xop0, strict_p))); | |
4053 | } | |
4054 | ||
4055 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
4056 | && code == SYMBOL_REF | |
4057 | && CONSTANT_POOL_ADDRESS_P (x) | |
4058 | && ! (flag_pic | |
4059 | && symbol_mentioned_p (get_pool_constant (x)) | |
4060 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
4061 | return 1; | |
4062 | ||
4063 | return 0; | |
4064 | } | |
4065 | ||
6b990f6b RE |
4066 | /* Return nonzero if INDEX is valid for an address index operand in |
4067 | ARM state. */ | |
4068 | static int | |
1e1ab407 RE |
4069 | arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, |
4070 | int strict_p) | |
6b990f6b RE |
4071 | { |
4072 | HOST_WIDE_INT range; | |
4073 | enum rtx_code code = GET_CODE (index); | |
4074 | ||
778ebdd9 PB |
4075 | /* Standard coprocessor addressing modes. */ |
4076 | if (TARGET_HARD_FLOAT | |
4077 | && (TARGET_FPA || TARGET_MAVERICK) | |
4078 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4079 | || (TARGET_MAVERICK && mode == DImode))) | |
6b990f6b RE |
4080 | return (code == CONST_INT && INTVAL (index) < 1024 |
4081 | && INTVAL (index) > -1024 | |
4082 | && (INTVAL (index) & 3) == 0); | |
4083 | ||
88f77cba JB |
4084 | if (TARGET_NEON |
4085 | && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | |
4086 | return (code == CONST_INT | |
4087 | && INTVAL (index) < 1016 | |
4088 | && INTVAL (index) > -1024 | |
4089 | && (INTVAL (index) & 3) == 0); | |
4090 | ||
5a9335ef NC |
4091 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) |
4092 | return (code == CONST_INT | |
3657dc3e PB |
4093 | && INTVAL (index) < 1024 |
4094 | && INTVAL (index) > -1024 | |
4095 | && (INTVAL (index) & 3) == 0); | |
5a9335ef | 4096 | |
fdd695fd PB |
4097 | if (arm_address_register_rtx_p (index, strict_p) |
4098 | && (GET_MODE_SIZE (mode) <= 4)) | |
4099 | return 1; | |
4100 | ||
4101 | if (mode == DImode || mode == DFmode) | |
4102 | { | |
4103 | if (code == CONST_INT) | |
4104 | { | |
4105 | HOST_WIDE_INT val = INTVAL (index); | |
4106 | ||
4107 | if (TARGET_LDRD) | |
4108 | return val > -256 && val < 256; | |
4109 | else | |
f372c932 | 4110 | return val > -4096 && val < 4092; |
fdd695fd PB |
4111 | } |
4112 | ||
4113 | return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p); | |
4114 | } | |
4115 | ||
6b990f6b | 4116 | if (GET_MODE_SIZE (mode) <= 4 |
1e1ab407 RE |
4117 | && ! (arm_arch4 |
4118 | && (mode == HImode | |
4119 | || (mode == QImode && outer == SIGN_EXTEND)))) | |
6b990f6b | 4120 | { |
1e1ab407 RE |
4121 | if (code == MULT) |
4122 | { | |
4123 | rtx xiop0 = XEXP (index, 0); | |
4124 | rtx xiop1 = XEXP (index, 1); | |
4125 | ||
4126 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
4127 | && power_of_two_operand (xiop1, SImode)) | |
4128 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
4129 | && power_of_two_operand (xiop0, SImode))); | |
4130 | } | |
4131 | else if (code == LSHIFTRT || code == ASHIFTRT | |
4132 | || code == ASHIFT || code == ROTATERT) | |
4133 | { | |
4134 | rtx op = XEXP (index, 1); | |
6b990f6b | 4135 | |
1e1ab407 RE |
4136 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) |
4137 | && GET_CODE (op) == CONST_INT | |
4138 | && INTVAL (op) > 0 | |
4139 | && INTVAL (op) <= 31); | |
4140 | } | |
6b990f6b RE |
4141 | } |
4142 | ||
1e1ab407 RE |
4143 | /* For ARM v4 we may be doing a sign-extend operation during the |
4144 | load. */ | |
e1471c91 | 4145 | if (arm_arch4) |
1e1ab407 RE |
4146 | { |
4147 | if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode)) | |
4148 | range = 256; | |
4149 | else | |
4150 | range = 4096; | |
4151 | } | |
e1471c91 RE |
4152 | else |
4153 | range = (mode == HImode) ? 4095 : 4096; | |
6b990f6b RE |
4154 | |
4155 | return (code == CONST_INT | |
4156 | && INTVAL (index) < range | |
4157 | && INTVAL (index) > -range); | |
76a318e9 RE |
4158 | } |
4159 | ||
5b3e6663 PB |
4160 | /* Return true if OP is a valid index scaling factor for Thumb-2 address |
4161 | index operand. i.e. 1, 2, 4 or 8. */ | |
4162 | static bool | |
4163 | thumb2_index_mul_operand (rtx op) | |
4164 | { | |
4165 | HOST_WIDE_INT val; | |
4166 | ||
4167 | if (GET_CODE(op) != CONST_INT) | |
4168 | return false; | |
4169 | ||
4170 | val = INTVAL(op); | |
4171 | return (val == 1 || val == 2 || val == 4 || val == 8); | |
4172 | } | |
4173 | ||
4174 | /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */ | |
4175 | static int | |
4176 | thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) | |
4177 | { | |
4178 | enum rtx_code code = GET_CODE (index); | |
4179 | ||
4180 | /* ??? Combine arm and thumb2 coprocessor addressing modes. */ | |
4181 | /* Standard coprocessor addressing modes. */ | |
4182 | if (TARGET_HARD_FLOAT | |
4183 | && (TARGET_FPA || TARGET_MAVERICK) | |
4184 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4185 | || (TARGET_MAVERICK && mode == DImode))) | |
4186 | return (code == CONST_INT && INTVAL (index) < 1024 | |
4187 | && INTVAL (index) > -1024 | |
4188 | && (INTVAL (index) & 3) == 0); | |
4189 | ||
4190 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) | |
fe2d934b PB |
4191 | { |
4192 | /* For DImode assume values will usually live in core regs | |
4193 | and only allow LDRD addressing modes. */ | |
4194 | if (!TARGET_LDRD || mode != DImode) | |
4195 | return (code == CONST_INT | |
4196 | && INTVAL (index) < 1024 | |
4197 | && INTVAL (index) > -1024 | |
4198 | && (INTVAL (index) & 3) == 0); | |
4199 | } | |
5b3e6663 | 4200 | |
88f77cba JB |
4201 | if (TARGET_NEON |
4202 | && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | |
4203 | return (code == CONST_INT | |
4204 | && INTVAL (index) < 1016 | |
4205 | && INTVAL (index) > -1024 | |
4206 | && (INTVAL (index) & 3) == 0); | |
4207 | ||
5b3e6663 PB |
4208 | if (arm_address_register_rtx_p (index, strict_p) |
4209 | && (GET_MODE_SIZE (mode) <= 4)) | |
4210 | return 1; | |
4211 | ||
4212 | if (mode == DImode || mode == DFmode) | |
4213 | { | |
4214 | HOST_WIDE_INT val = INTVAL (index); | |
4215 | /* ??? Can we assume ldrd for thumb2? */ | |
4216 | /* Thumb-2 ldrd only has reg+const addressing modes. */ | |
4217 | if (code != CONST_INT) | |
4218 | return 0; | |
4219 | ||
4220 | /* ldrd supports offsets of +-1020. | |
4221 | However the ldr fallback does not. */ | |
4222 | return val > -256 && val < 256 && (val & 3) == 0; | |
4223 | } | |
4224 | ||
4225 | if (code == MULT) | |
4226 | { | |
4227 | rtx xiop0 = XEXP (index, 0); | |
4228 | rtx xiop1 = XEXP (index, 1); | |
4229 | ||
4230 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
4231 | && thumb2_index_mul_operand (xiop1)) | |
4232 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
4233 | && thumb2_index_mul_operand (xiop0))); | |
4234 | } | |
4235 | else if (code == ASHIFT) | |
4236 | { | |
4237 | rtx op = XEXP (index, 1); | |
4238 | ||
4239 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) | |
4240 | && GET_CODE (op) == CONST_INT | |
4241 | && INTVAL (op) > 0 | |
4242 | && INTVAL (op) <= 3); | |
4243 | } | |
4244 | ||
4245 | return (code == CONST_INT | |
4246 | && INTVAL (index) < 4096 | |
4247 | && INTVAL (index) > -256); | |
4248 | } | |
4249 | ||
4250 | /* Return nonzero if X is valid as a 16-bit Thumb state base register. */ | |
76a318e9 | 4251 | static int |
5b3e6663 | 4252 | thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) |
76a318e9 RE |
4253 | { |
4254 | int regno; | |
4255 | ||
4256 | if (GET_CODE (x) != REG) | |
4257 | return 0; | |
4258 | ||
4259 | regno = REGNO (x); | |
4260 | ||
4261 | if (strict_p) | |
5b3e6663 | 4262 | return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode); |
76a318e9 RE |
4263 | |
4264 | return (regno <= LAST_LO_REGNUM | |
07e58265 | 4265 | || regno > LAST_VIRTUAL_REGISTER |
76a318e9 RE |
4266 | || regno == FRAME_POINTER_REGNUM |
4267 | || (GET_MODE_SIZE (mode) >= 4 | |
4268 | && (regno == STACK_POINTER_REGNUM | |
edf7cee8 | 4269 | || regno >= FIRST_PSEUDO_REGISTER |
76a318e9 RE |
4270 | || x == hard_frame_pointer_rtx |
4271 | || x == arg_pointer_rtx))); | |
4272 | } | |
4273 | ||
4274 | /* Return nonzero if x is a legitimate index register. This is the case | |
4275 | for any base register that can access a QImode object. */ | |
4276 | inline static int | |
5b3e6663 | 4277 | thumb1_index_register_rtx_p (rtx x, int strict_p) |
76a318e9 | 4278 | { |
5b3e6663 | 4279 | return thumb1_base_register_rtx_p (x, QImode, strict_p); |
76a318e9 RE |
4280 | } |
4281 | ||
5b3e6663 | 4282 | /* Return nonzero if x is a legitimate 16-bit Thumb-state address. |
f676971a | 4283 | |
76a318e9 RE |
4284 | The AP may be eliminated to either the SP or the FP, so we use the |
4285 | least common denominator, e.g. SImode, and offsets from 0 to 64. | |
4286 | ||
4287 | ??? Verify whether the above is the right approach. | |
4288 | ||
4289 | ??? Also, the FP may be eliminated to the SP, so perhaps that | |
4290 | needs special handling also. | |
4291 | ||
4292 | ??? Look at how the mips16 port solves this problem. It probably uses | |
4293 | better ways to solve some of these problems. | |
4294 | ||
4295 | Although it is not incorrect, we don't accept QImode and HImode | |
4296 | addresses based on the frame pointer or arg pointer until the | |
4297 | reload pass starts. This is so that eliminating such addresses | |
4298 | into stack based ones won't produce impossible code. */ | |
4299 | int | |
5b3e6663 | 4300 | thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
76a318e9 RE |
4301 | { |
4302 | /* ??? Not clear if this is right. Experiment. */ | |
4303 | if (GET_MODE_SIZE (mode) < 4 | |
4304 | && !(reload_in_progress || reload_completed) | |
4305 | && (reg_mentioned_p (frame_pointer_rtx, x) | |
4306 | || reg_mentioned_p (arg_pointer_rtx, x) | |
4307 | || reg_mentioned_p (virtual_incoming_args_rtx, x) | |
4308 | || reg_mentioned_p (virtual_outgoing_args_rtx, x) | |
4309 | || reg_mentioned_p (virtual_stack_dynamic_rtx, x) | |
4310 | || reg_mentioned_p (virtual_stack_vars_rtx, x))) | |
4311 | return 0; | |
4312 | ||
4313 | /* Accept any base register. SP only in SImode or larger. */ | |
5b3e6663 | 4314 | else if (thumb1_base_register_rtx_p (x, mode, strict_p)) |
76a318e9 RE |
4315 | return 1; |
4316 | ||
18dbd950 | 4317 | /* This is PC relative data before arm_reorg runs. */ |
76a318e9 RE |
4318 | else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) |
4319 | && GET_CODE (x) == SYMBOL_REF | |
020a4035 | 4320 | && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic) |
76a318e9 RE |
4321 | return 1; |
4322 | ||
18dbd950 | 4323 | /* This is PC relative data after arm_reorg runs. */ |
76a318e9 RE |
4324 | else if (GET_MODE_SIZE (mode) >= 4 && reload_completed |
4325 | && (GET_CODE (x) == LABEL_REF | |
4326 | || (GET_CODE (x) == CONST | |
4327 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4328 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
4329 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
4330 | return 1; | |
4331 | ||
4332 | /* Post-inc indexing only supported for SImode and larger. */ | |
4333 | else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 | |
5b3e6663 | 4334 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)) |
76a318e9 RE |
4335 | return 1; |
4336 | ||
4337 | else if (GET_CODE (x) == PLUS) | |
4338 | { | |
4339 | /* REG+REG address can be any two index registers. */ | |
4340 | /* We disallow FRAME+REG addressing since we know that FRAME | |
4341 | will be replaced with STACK, and SP relative addressing only | |
4342 | permits SP+OFFSET. */ | |
4343 | if (GET_MODE_SIZE (mode) <= 4 | |
4344 | && XEXP (x, 0) != frame_pointer_rtx | |
4345 | && XEXP (x, 1) != frame_pointer_rtx | |
5b3e6663 PB |
4346 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
4347 | && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p)) | |
76a318e9 RE |
4348 | return 1; |
4349 | ||
4350 | /* REG+const has 5-7 bit offset for non-SP registers. */ | |
5b3e6663 | 4351 | else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
76a318e9 RE |
4352 | || XEXP (x, 0) == arg_pointer_rtx) |
4353 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4354 | && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
4355 | return 1; | |
4356 | ||
a50aa827 | 4357 | /* REG+const has 10-bit offset for SP, but only SImode and |
76a318e9 RE |
4358 | larger is supported. */ |
4359 | /* ??? Should probably check for DI/DFmode overflow here | |
4360 | just like GO_IF_LEGITIMATE_OFFSET does. */ | |
4361 | else if (GET_CODE (XEXP (x, 0)) == REG | |
4362 | && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM | |
4363 | && GET_MODE_SIZE (mode) >= 4 | |
4364 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4365 | && INTVAL (XEXP (x, 1)) >= 0 | |
4366 | && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 | |
4367 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
4368 | return 1; | |
4369 | ||
4370 | else if (GET_CODE (XEXP (x, 0)) == REG | |
c5289e45 RE |
4371 | && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM |
4372 | || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM | |
4373 | || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER | |
4374 | && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER)) | |
76a318e9 RE |
4375 | && GET_MODE_SIZE (mode) >= 4 |
4376 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4377 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
4378 | return 1; | |
4379 | } | |
4380 | ||
4381 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
f954388e | 4382 | && GET_MODE_SIZE (mode) == 4 |
76a318e9 RE |
4383 | && GET_CODE (x) == SYMBOL_REF |
4384 | && CONSTANT_POOL_ADDRESS_P (x) | |
d3585b76 DJ |
4385 | && ! (flag_pic |
4386 | && symbol_mentioned_p (get_pool_constant (x)) | |
4387 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
76a318e9 RE |
4388 | return 1; |
4389 | ||
4390 | return 0; | |
4391 | } | |
4392 | ||
4393 | /* Return nonzero if VAL can be used as an offset in a Thumb-state address | |
4394 | instruction of mode MODE. */ | |
4395 | int | |
e32bac5b | 4396 | thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) |
76a318e9 RE |
4397 | { |
4398 | switch (GET_MODE_SIZE (mode)) | |
4399 | { | |
4400 | case 1: | |
4401 | return val >= 0 && val < 32; | |
4402 | ||
4403 | case 2: | |
4404 | return val >= 0 && val < 64 && (val & 1) == 0; | |
4405 | ||
4406 | default: | |
4407 | return (val >= 0 | |
4408 | && (val + GET_MODE_SIZE (mode)) <= 128 | |
4409 | && (val & 3) == 0); | |
4410 | } | |
4411 | } | |
4412 | ||
d3585b76 DJ |
4413 | /* Build the SYMBOL_REF for __tls_get_addr. */ |
4414 | ||
4415 | static GTY(()) rtx tls_get_addr_libfunc; | |
4416 | ||
4417 | static rtx | |
4418 | get_tls_get_addr (void) | |
4419 | { | |
4420 | if (!tls_get_addr_libfunc) | |
4421 | tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); | |
4422 | return tls_get_addr_libfunc; | |
4423 | } | |
4424 | ||
4425 | static rtx | |
4426 | arm_load_tp (rtx target) | |
4427 | { | |
4428 | if (!target) | |
4429 | target = gen_reg_rtx (SImode); | |
4430 | ||
4431 | if (TARGET_HARD_TP) | |
4432 | { | |
4433 | /* Can return in any reg. */ | |
4434 | emit_insn (gen_load_tp_hard (target)); | |
4435 | } | |
4436 | else | |
4437 | { | |
4438 | /* Always returned in r0. Immediately copy the result into a pseudo, | |
4439 | otherwise other uses of r0 (e.g. setting up function arguments) may | |
4440 | clobber the value. */ | |
4441 | ||
4442 | rtx tmp; | |
4443 | ||
4444 | emit_insn (gen_load_tp_soft ()); | |
4445 | ||
4446 | tmp = gen_rtx_REG (SImode, 0); | |
4447 | emit_move_insn (target, tmp); | |
4448 | } | |
4449 | return target; | |
4450 | } | |
4451 | ||
4452 | static rtx | |
4453 | load_tls_operand (rtx x, rtx reg) | |
4454 | { | |
4455 | rtx tmp; | |
4456 | ||
4457 | if (reg == NULL_RTX) | |
4458 | reg = gen_reg_rtx (SImode); | |
4459 | ||
4460 | tmp = gen_rtx_CONST (SImode, x); | |
4461 | ||
4462 | emit_move_insn (reg, tmp); | |
4463 | ||
4464 | return reg; | |
4465 | } | |
4466 | ||
4467 | static rtx | |
4468 | arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc) | |
4469 | { | |
f16fe45f | 4470 | rtx insns, label, labelno, sum; |
d3585b76 DJ |
4471 | |
4472 | start_sequence (); | |
4473 | ||
f16fe45f DJ |
4474 | labelno = GEN_INT (pic_labelno++); |
4475 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
4476 | label = gen_rtx_CONST (VOIDmode, label); | |
4477 | ||
d3585b76 | 4478 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 4479 | gen_rtvec (4, x, GEN_INT (reloc), label, |
d3585b76 DJ |
4480 | GEN_INT (TARGET_ARM ? 8 : 4)), |
4481 | UNSPEC_TLS); | |
4482 | reg = load_tls_operand (sum, reg); | |
4483 | ||
4484 | if (TARGET_ARM) | |
f16fe45f | 4485 | emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 PB |
4486 | else if (TARGET_THUMB2) |
4487 | { | |
4488 | rtx tmp; | |
4489 | /* Thumb-2 only allows very limited access to the PC. Calculate | |
4490 | the address in a temporary register. */ | |
4491 | tmp = gen_reg_rtx (SImode); | |
4492 | emit_insn (gen_pic_load_dot_plus_four (tmp, labelno)); | |
4493 | emit_insn (gen_addsi3(reg, reg, tmp)); | |
4494 | } | |
4495 | else /* TARGET_THUMB1 */ | |
f16fe45f | 4496 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
4497 | |
4498 | *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */ | |
4499 | Pmode, 1, reg, Pmode); | |
4500 | ||
4501 | insns = get_insns (); | |
4502 | end_sequence (); | |
4503 | ||
4504 | return insns; | |
4505 | } | |
4506 | ||
4507 | rtx | |
4508 | legitimize_tls_address (rtx x, rtx reg) | |
4509 | { | |
f16fe45f | 4510 | rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend; |
d3585b76 DJ |
4511 | unsigned int model = SYMBOL_REF_TLS_MODEL (x); |
4512 | ||
4513 | switch (model) | |
4514 | { | |
4515 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
4516 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32); | |
4517 | dest = gen_reg_rtx (Pmode); | |
4518 | emit_libcall_block (insns, dest, ret, x); | |
4519 | return dest; | |
4520 | ||
4521 | case TLS_MODEL_LOCAL_DYNAMIC: | |
4522 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32); | |
4523 | ||
4524 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
4525 | share the LDM result with other LD model accesses. */ | |
4526 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), | |
4527 | UNSPEC_TLS); | |
4528 | dest = gen_reg_rtx (Pmode); | |
e66e1c68 | 4529 | emit_libcall_block (insns, dest, ret, eqv); |
d3585b76 DJ |
4530 | |
4531 | /* Load the addend. */ | |
4532 | addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)), | |
4533 | UNSPEC_TLS); | |
4534 | addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); | |
4535 | return gen_rtx_PLUS (Pmode, dest, addend); | |
4536 | ||
4537 | case TLS_MODEL_INITIAL_EXEC: | |
f16fe45f DJ |
4538 | labelno = GEN_INT (pic_labelno++); |
4539 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
4540 | label = gen_rtx_CONST (VOIDmode, label); | |
d3585b76 | 4541 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 4542 | gen_rtvec (4, x, GEN_INT (TLS_IE32), label, |
d3585b76 DJ |
4543 | GEN_INT (TARGET_ARM ? 8 : 4)), |
4544 | UNSPEC_TLS); | |
4545 | reg = load_tls_operand (sum, reg); | |
4546 | ||
4547 | if (TARGET_ARM) | |
f16fe45f | 4548 | emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 PB |
4549 | else if (TARGET_THUMB2) |
4550 | { | |
4551 | rtx tmp; | |
4552 | /* Thumb-2 only allows very limited access to the PC. Calculate | |
4553 | the address in a temporary register. */ | |
4554 | tmp = gen_reg_rtx (SImode); | |
4555 | emit_insn (gen_pic_load_dot_plus_four (tmp, labelno)); | |
4556 | emit_insn (gen_addsi3(reg, reg, tmp)); | |
4557 | emit_move_insn (reg, gen_const_mem (SImode, reg)); | |
4558 | } | |
d3585b76 DJ |
4559 | else |
4560 | { | |
f16fe45f | 4561 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
4562 | emit_move_insn (reg, gen_const_mem (SImode, reg)); |
4563 | } | |
4564 | ||
4565 | tp = arm_load_tp (NULL_RTX); | |
4566 | ||
4567 | return gen_rtx_PLUS (Pmode, tp, reg); | |
4568 | ||
4569 | case TLS_MODEL_LOCAL_EXEC: | |
4570 | tp = arm_load_tp (NULL_RTX); | |
4571 | ||
4572 | reg = gen_rtx_UNSPEC (Pmode, | |
4573 | gen_rtvec (2, x, GEN_INT (TLS_LE32)), | |
4574 | UNSPEC_TLS); | |
4575 | reg = force_reg (SImode, gen_rtx_CONST (SImode, reg)); | |
4576 | ||
4577 | return gen_rtx_PLUS (Pmode, tp, reg); | |
4578 | ||
4579 | default: | |
4580 | abort (); | |
4581 | } | |
4582 | } | |
4583 | ||
ccf4d512 RE |
4584 | /* Try machine-dependent ways of modifying an illegitimate address |
4585 | to be legitimate. If we find one, return the new, valid address. */ | |
ccf4d512 | 4586 | rtx |
e32bac5b | 4587 | arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) |
ccf4d512 | 4588 | { |
d3585b76 DJ |
4589 | if (arm_tls_symbol_p (x)) |
4590 | return legitimize_tls_address (x, NULL_RTX); | |
4591 | ||
ccf4d512 RE |
4592 | if (GET_CODE (x) == PLUS) |
4593 | { | |
4594 | rtx xop0 = XEXP (x, 0); | |
4595 | rtx xop1 = XEXP (x, 1); | |
4596 | ||
4597 | if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) | |
4598 | xop0 = force_reg (SImode, xop0); | |
4599 | ||
4600 | if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) | |
4601 | xop1 = force_reg (SImode, xop1); | |
4602 | ||
4603 | if (ARM_BASE_REGISTER_RTX_P (xop0) | |
4604 | && GET_CODE (xop1) == CONST_INT) | |
4605 | { | |
4606 | HOST_WIDE_INT n, low_n; | |
4607 | rtx base_reg, val; | |
4608 | n = INTVAL (xop1); | |
4609 | ||
9b66ebb1 PB |
4610 | /* VFP addressing modes actually allow greater offsets, but for |
4611 | now we just stick with the lowest common denominator. */ | |
4612 | if (mode == DImode | |
4613 | || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) | |
ccf4d512 RE |
4614 | { |
4615 | low_n = n & 0x0f; | |
4616 | n &= ~0x0f; | |
4617 | if (low_n > 4) | |
4618 | { | |
4619 | n += 16; | |
4620 | low_n -= 16; | |
4621 | } | |
4622 | } | |
4623 | else | |
4624 | { | |
4625 | low_n = ((mode) == TImode ? 0 | |
4626 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); | |
4627 | n -= low_n; | |
4628 | } | |
4629 | ||
4630 | base_reg = gen_reg_rtx (SImode); | |
d66437c5 | 4631 | val = force_operand (plus_constant (xop0, n), NULL_RTX); |
ccf4d512 | 4632 | emit_move_insn (base_reg, val); |
d66437c5 | 4633 | x = plus_constant (base_reg, low_n); |
ccf4d512 RE |
4634 | } |
4635 | else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
4636 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
4637 | } | |
4638 | ||
4639 | /* XXX We don't allow MINUS any more -- see comment in | |
4640 | arm_legitimate_address_p (). */ | |
4641 | else if (GET_CODE (x) == MINUS) | |
4642 | { | |
4643 | rtx xop0 = XEXP (x, 0); | |
4644 | rtx xop1 = XEXP (x, 1); | |
4645 | ||
4646 | if (CONSTANT_P (xop0)) | |
4647 | xop0 = force_reg (SImode, xop0); | |
4648 | ||
4649 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) | |
4650 | xop1 = force_reg (SImode, xop1); | |
4651 | ||
4652 | if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
4653 | x = gen_rtx_MINUS (SImode, xop0, xop1); | |
4654 | } | |
4655 | ||
86805759 NP |
4656 | /* Make sure to take full advantage of the pre-indexed addressing mode |
4657 | with absolute addresses which often allows for the base register to | |
4658 | be factorized for multiple adjacent memory references, and it might | |
4659 | even allows for the mini pool to be avoided entirely. */ | |
4660 | else if (GET_CODE (x) == CONST_INT && optimize > 0) | |
4661 | { | |
4662 | unsigned int bits; | |
4663 | HOST_WIDE_INT mask, base, index; | |
4664 | rtx base_reg; | |
4665 | ||
a50aa827 KH |
4666 | /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only |
4667 | use a 8-bit index. So let's use a 12-bit index for SImode only and | |
86805759 NP |
4668 | hope that arm_gen_constant will enable ldrb to use more bits. */ |
4669 | bits = (mode == SImode) ? 12 : 8; | |
4670 | mask = (1 << bits) - 1; | |
4671 | base = INTVAL (x) & ~mask; | |
4672 | index = INTVAL (x) & mask; | |
b107d743 | 4673 | if (bit_count (base & 0xffffffff) > (32 - bits)/2) |
86805759 NP |
4674 | { |
4675 | /* It'll most probably be more efficient to generate the base | |
4676 | with more bits set and use a negative index instead. */ | |
4677 | base |= mask; | |
4678 | index -= mask; | |
4679 | } | |
4680 | base_reg = force_reg (SImode, GEN_INT (base)); | |
d66437c5 | 4681 | x = plus_constant (base_reg, index); |
86805759 NP |
4682 | } |
4683 | ||
ccf4d512 RE |
4684 | if (flag_pic) |
4685 | { | |
4686 | /* We need to find and carefully transform any SYMBOL and LABEL | |
4687 | references; so go back to the original address expression. */ | |
4688 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
4689 | ||
4690 | if (new_x != orig_x) | |
4691 | x = new_x; | |
4692 | } | |
4693 | ||
4694 | return x; | |
4695 | } | |
4696 | ||
6f5b4f3e RE |
4697 | |
4698 | /* Try machine-dependent ways of modifying an illegitimate Thumb address | |
4699 | to be legitimate. If we find one, return the new, valid address. */ | |
4700 | rtx | |
4701 | thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) | |
4702 | { | |
d3585b76 DJ |
4703 | if (arm_tls_symbol_p (x)) |
4704 | return legitimize_tls_address (x, NULL_RTX); | |
4705 | ||
6f5b4f3e RE |
4706 | if (GET_CODE (x) == PLUS |
4707 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4708 | && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) | |
4709 | || INTVAL (XEXP (x, 1)) < 0)) | |
4710 | { | |
4711 | rtx xop0 = XEXP (x, 0); | |
4712 | rtx xop1 = XEXP (x, 1); | |
4713 | HOST_WIDE_INT offset = INTVAL (xop1); | |
4714 | ||
4715 | /* Try and fold the offset into a biasing of the base register and | |
4716 | then offsetting that. Don't do this when optimizing for space | |
4717 | since it can cause too many CSEs. */ | |
4718 | if (optimize_size && offset >= 0 | |
4719 | && offset < 256 + 31 * GET_MODE_SIZE (mode)) | |
4720 | { | |
4721 | HOST_WIDE_INT delta; | |
4722 | ||
4723 | if (offset >= 256) | |
4724 | delta = offset - (256 - GET_MODE_SIZE (mode)); | |
4725 | else if (offset < 32 * GET_MODE_SIZE (mode) + 8) | |
4726 | delta = 31 * GET_MODE_SIZE (mode); | |
4727 | else | |
4728 | delta = offset & (~31 * GET_MODE_SIZE (mode)); | |
4729 | ||
4730 | xop0 = force_operand (plus_constant (xop0, offset - delta), | |
4731 | NULL_RTX); | |
4732 | x = plus_constant (xop0, delta); | |
4733 | } | |
4734 | else if (offset < 0 && offset > -256) | |
4735 | /* Small negative offsets are best done with a subtract before the | |
4736 | dereference, forcing these into a register normally takes two | |
4737 | instructions. */ | |
4738 | x = force_operand (x, NULL_RTX); | |
4739 | else | |
4740 | { | |
4741 | /* For the remaining cases, force the constant into a register. */ | |
4742 | xop1 = force_reg (SImode, xop1); | |
4743 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
4744 | } | |
4745 | } | |
4746 | else if (GET_CODE (x) == PLUS | |
4747 | && s_register_operand (XEXP (x, 1), SImode) | |
4748 | && !s_register_operand (XEXP (x, 0), SImode)) | |
4749 | { | |
4750 | rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX); | |
4751 | ||
4752 | x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1)); | |
4753 | } | |
4754 | ||
4755 | if (flag_pic) | |
4756 | { | |
4757 | /* We need to find and carefully transform any SYMBOL and LABEL | |
4758 | references; so go back to the original address expression. */ | |
4759 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
4760 | ||
4761 | if (new_x != orig_x) | |
4762 | x = new_x; | |
4763 | } | |
4764 | ||
4765 | return x; | |
4766 | } | |
4767 | ||
a132dad6 | 4768 | rtx |
e0b92319 NC |
4769 | thumb_legitimize_reload_address (rtx *x_p, |
4770 | enum machine_mode mode, | |
4771 | int opnum, int type, | |
4772 | int ind_levels ATTRIBUTE_UNUSED) | |
a132dad6 RE |
4773 | { |
4774 | rtx x = *x_p; | |
e0b92319 | 4775 | |
a132dad6 RE |
4776 | if (GET_CODE (x) == PLUS |
4777 | && GET_MODE_SIZE (mode) < 4 | |
4778 | && REG_P (XEXP (x, 0)) | |
4779 | && XEXP (x, 0) == stack_pointer_rtx | |
4780 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4781 | && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
4782 | { | |
4783 | rtx orig_x = x; | |
4784 | ||
4785 | x = copy_rtx (x); | |
4786 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
4787 | Pmode, VOIDmode, 0, 0, opnum, type); | |
4788 | return x; | |
4789 | } | |
4790 | ||
4791 | /* If both registers are hi-regs, then it's better to reload the | |
4792 | entire expression rather than each register individually. That | |
4793 | only requires one reload register rather than two. */ | |
4794 | if (GET_CODE (x) == PLUS | |
4795 | && REG_P (XEXP (x, 0)) | |
4796 | && REG_P (XEXP (x, 1)) | |
4797 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode) | |
4798 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode)) | |
4799 | { | |
4800 | rtx orig_x = x; | |
4801 | ||
4802 | x = copy_rtx (x); | |
4803 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
4804 | Pmode, VOIDmode, 0, 0, opnum, type); | |
4805 | return x; | |
4806 | } | |
4807 | ||
4808 | return NULL; | |
4809 | } | |
d3585b76 DJ |
4810 | |
4811 | /* Test for various thread-local symbols. */ | |
4812 | ||
4813 | /* Return TRUE if X is a thread-local symbol. */ | |
4814 | ||
4815 | static bool | |
4816 | arm_tls_symbol_p (rtx x) | |
4817 | { | |
4818 | if (! TARGET_HAVE_TLS) | |
4819 | return false; | |
4820 | ||
4821 | if (GET_CODE (x) != SYMBOL_REF) | |
4822 | return false; | |
4823 | ||
4824 | return SYMBOL_REF_TLS_MODEL (x) != 0; | |
4825 | } | |
4826 | ||
4827 | /* Helper for arm_tls_referenced_p. */ | |
4828 | ||
4829 | static int | |
4830 | arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
4831 | { | |
4832 | if (GET_CODE (*x) == SYMBOL_REF) | |
4833 | return SYMBOL_REF_TLS_MODEL (*x) != 0; | |
4834 | ||
4835 | /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are | |
4836 | TLS offsets, not real symbol references. */ | |
4837 | if (GET_CODE (*x) == UNSPEC | |
4838 | && XINT (*x, 1) == UNSPEC_TLS) | |
4839 | return -1; | |
4840 | ||
4841 | return 0; | |
4842 | } | |
4843 | ||
4844 | /* Return TRUE if X contains any TLS symbol references. */ | |
4845 | ||
4846 | bool | |
4847 | arm_tls_referenced_p (rtx x) | |
4848 | { | |
4849 | if (! TARGET_HAVE_TLS) | |
4850 | return false; | |
4851 | ||
4852 | return for_each_rtx (&x, arm_tls_operand_p_1, NULL); | |
4853 | } | |
8426b956 RS |
4854 | |
4855 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ | |
4856 | ||
4857 | bool | |
4858 | arm_cannot_force_const_mem (rtx x) | |
4859 | { | |
4860 | rtx base, offset; | |
4861 | ||
4862 | if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
4863 | { | |
4864 | split_const (x, &base, &offset); | |
4865 | if (GET_CODE (base) == SYMBOL_REF | |
4866 | && !offset_within_block_p (base, INTVAL (offset))) | |
4867 | return true; | |
4868 | } | |
4869 | return arm_tls_referenced_p (x); | |
4870 | } | |
6b990f6b | 4871 | \f |
e2c671ba RE |
4872 | #define REG_OR_SUBREG_REG(X) \ |
4873 | (GET_CODE (X) == REG \ | |
4874 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
4875 | ||
4876 | #define REG_OR_SUBREG_RTX(X) \ | |
4877 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
4878 | ||
d5b7b3ae RE |
4879 | #ifndef COSTS_N_INSNS |
4880 | #define COSTS_N_INSNS(N) ((N) * 4 - 2) | |
4881 | #endif | |
3c50106f | 4882 | static inline int |
5b3e6663 | 4883 | thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) |
e2c671ba RE |
4884 | { |
4885 | enum machine_mode mode = GET_MODE (x); | |
e2c671ba | 4886 | |
9b66ebb1 | 4887 | switch (code) |
d5b7b3ae | 4888 | { |
9b66ebb1 PB |
4889 | case ASHIFT: |
4890 | case ASHIFTRT: | |
4891 | case LSHIFTRT: | |
f676971a | 4892 | case ROTATERT: |
9b66ebb1 PB |
4893 | case PLUS: |
4894 | case MINUS: | |
4895 | case COMPARE: | |
4896 | case NEG: | |
f676971a | 4897 | case NOT: |
9b66ebb1 | 4898 | return COSTS_N_INSNS (1); |
f676971a EC |
4899 | |
4900 | case MULT: | |
4901 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4902 | { | |
4903 | int cycles = 0; | |
9b66ebb1 | 4904 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); |
f676971a EC |
4905 | |
4906 | while (i) | |
4907 | { | |
4908 | i >>= 2; | |
4909 | cycles++; | |
4910 | } | |
4911 | return COSTS_N_INSNS (2) + cycles; | |
9b66ebb1 PB |
4912 | } |
4913 | return COSTS_N_INSNS (1) + 16; | |
f676971a EC |
4914 | |
4915 | case SET: | |
4916 | return (COSTS_N_INSNS (1) | |
4917 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
9b66ebb1 | 4918 | + GET_CODE (SET_DEST (x)) == MEM)); |
f676971a EC |
4919 | |
4920 | case CONST_INT: | |
4921 | if (outer == SET) | |
4922 | { | |
4923 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
4924 | return 0; | |
4925 | if (thumb_shiftable_const (INTVAL (x))) | |
4926 | return COSTS_N_INSNS (2); | |
4927 | return COSTS_N_INSNS (3); | |
4928 | } | |
9b66ebb1 | 4929 | else if ((outer == PLUS || outer == COMPARE) |
f676971a | 4930 | && INTVAL (x) < 256 && INTVAL (x) > -256) |
9b66ebb1 PB |
4931 | return 0; |
4932 | else if (outer == AND | |
4933 | && INTVAL (x) < 256 && INTVAL (x) >= -256) | |
4934 | return COSTS_N_INSNS (1); | |
f676971a EC |
4935 | else if (outer == ASHIFT || outer == ASHIFTRT |
4936 | || outer == LSHIFTRT) | |
4937 | return 0; | |
9b66ebb1 | 4938 | return COSTS_N_INSNS (2); |
f676971a EC |
4939 | |
4940 | case CONST: | |
4941 | case CONST_DOUBLE: | |
4942 | case LABEL_REF: | |
4943 | case SYMBOL_REF: | |
9b66ebb1 | 4944 | return COSTS_N_INSNS (3); |
f676971a | 4945 | |
9b66ebb1 PB |
4946 | case UDIV: |
4947 | case UMOD: | |
4948 | case DIV: | |
4949 | case MOD: | |
4950 | return 100; | |
d5b7b3ae | 4951 | |
9b66ebb1 PB |
4952 | case TRUNCATE: |
4953 | return 99; | |
d5b7b3ae | 4954 | |
9b66ebb1 PB |
4955 | case AND: |
4956 | case XOR: | |
f676971a | 4957 | case IOR: |
ff482c8d | 4958 | /* XXX guess. */ |
9b66ebb1 | 4959 | return 8; |
d5b7b3ae | 4960 | |
9b66ebb1 PB |
4961 | case MEM: |
4962 | /* XXX another guess. */ | |
4963 | /* Memory costs quite a lot for the first word, but subsequent words | |
4964 | load at the equivalent of a single insn each. */ | |
4965 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
4966 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
4967 | ? 4 : 0)); | |
4968 | ||
4969 | case IF_THEN_ELSE: | |
ff482c8d | 4970 | /* XXX a guess. */ |
9b66ebb1 PB |
4971 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) |
4972 | return 14; | |
4973 | return 2; | |
4974 | ||
4975 | case ZERO_EXTEND: | |
4976 | /* XXX still guessing. */ | |
4977 | switch (GET_MODE (XEXP (x, 0))) | |
4978 | { | |
4979 | case QImode: | |
4980 | return (1 + (mode == DImode ? 4 : 0) | |
4981 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 4982 | |
9b66ebb1 PB |
4983 | case HImode: |
4984 | return (4 + (mode == DImode ? 4 : 0) | |
4985 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 4986 | |
9b66ebb1 PB |
4987 | case SImode: |
4988 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 4989 | |
d5b7b3ae RE |
4990 | default: |
4991 | return 99; | |
d5b7b3ae | 4992 | } |
f676971a | 4993 | |
9b66ebb1 PB |
4994 | default: |
4995 | return 99; | |
d5b7b3ae | 4996 | } |
9b66ebb1 PB |
4997 | } |
4998 | ||
d5a0a47b RE |
4999 | static inline bool |
5000 | arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) | |
9b66ebb1 PB |
5001 | { |
5002 | enum machine_mode mode = GET_MODE (x); | |
5003 | enum rtx_code subcode; | |
d5a0a47b RE |
5004 | rtx operand; |
5005 | enum rtx_code code = GET_CODE (x); | |
9b66ebb1 | 5006 | int extra_cost; |
d5a0a47b | 5007 | *total = 0; |
9b66ebb1 | 5008 | |
e2c671ba RE |
5009 | switch (code) |
5010 | { | |
5011 | case MEM: | |
5012 | /* Memory costs quite a lot for the first word, but subsequent words | |
5013 | load at the equivalent of a single insn each. */ | |
d5a0a47b RE |
5014 | *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode)); |
5015 | return true; | |
e2c671ba RE |
5016 | |
5017 | case DIV: | |
5018 | case MOD: | |
b9c53150 RS |
5019 | case UDIV: |
5020 | case UMOD: | |
d5a0a47b RE |
5021 | if (TARGET_HARD_FLOAT && mode == SFmode) |
5022 | *total = COSTS_N_INSNS (2); | |
5023 | else if (TARGET_HARD_FLOAT && mode == DFmode) | |
5024 | *total = COSTS_N_INSNS (4); | |
5025 | else | |
5026 | *total = COSTS_N_INSNS (20); | |
5027 | return false; | |
e2c671ba RE |
5028 | |
5029 | case ROTATE: | |
d5a0a47b RE |
5030 | if (GET_CODE (XEXP (x, 1)) == REG) |
5031 | *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */ | |
5032 | else if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
5033 | *total = rtx_cost (XEXP (x, 1), code, speed); | |
5034 | ||
e2c671ba RE |
5035 | /* Fall through */ |
5036 | case ROTATERT: | |
5037 | if (mode != SImode) | |
d5a0a47b RE |
5038 | { |
5039 | *total += COSTS_N_INSNS (4); | |
5040 | return true; | |
5041 | } | |
5042 | ||
e2c671ba RE |
5043 | /* Fall through */ |
5044 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
d5a0a47b | 5045 | *total += rtx_cost (XEXP (x, 0), code, speed); |
e2c671ba | 5046 | if (mode == DImode) |
d5a0a47b RE |
5047 | { |
5048 | *total += COSTS_N_INSNS (3); | |
5049 | return true; | |
5050 | } | |
7612f14d | 5051 | |
d5a0a47b | 5052 | *total += COSTS_N_INSNS (1); |
7612f14d PB |
5053 | /* Increase the cost of complex shifts because they aren't any faster, |
5054 | and reduce dual issue opportunities. */ | |
5055 | if (arm_tune_cortex_a9 | |
5056 | && outer != SET && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
d5a0a47b RE |
5057 | ++*total; |
5058 | ||
5059 | return true; | |
e2c671ba RE |
5060 | |
5061 | case MINUS: | |
d5a0a47b | 5062 | if (TARGET_THUMB2) |
26b53f80 | 5063 | { |
d5a0a47b RE |
5064 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
5065 | { | |
5066 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5067 | *total = COSTS_N_INSNS (1); | |
5068 | else | |
5069 | *total = COSTS_N_INSNS (20); | |
5070 | } | |
5071 | else | |
5072 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5073 | /* Thumb2 does not have RSB, so all arguments must be | |
5074 | registers (subtracting a constant is canonicalized as | |
5075 | addition of the negated constant). */ | |
5076 | return false; | |
26b53f80 PB |
5077 | } |
5078 | ||
e2c671ba | 5079 | if (mode == DImode) |
d5a0a47b RE |
5080 | { |
5081 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5082 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
5083 | && const_ok_for_arm (INTVAL (XEXP (x, 0)))) | |
5084 | { | |
5085 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5086 | return true; | |
5087 | } | |
5088 | ||
5089 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5090 | && const_ok_for_arm (INTVAL (XEXP (x, 1)))) | |
5091 | { | |
5092 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5093 | return true; | |
5094 | } | |
5095 | ||
5096 | return false; | |
5097 | } | |
e2c671ba RE |
5098 | |
5099 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
d5a0a47b RE |
5100 | { |
5101 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5102 | { | |
5103 | *total = COSTS_N_INSNS (1); | |
5104 | if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
5105 | && arm_const_double_rtx (XEXP (x, 0))) | |
5106 | { | |
5107 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5108 | return true; | |
5109 | } | |
5110 | ||
5111 | if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
5112 | && arm_const_double_rtx (XEXP (x, 1))) | |
5113 | { | |
5114 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5115 | return true; | |
5116 | } | |
5117 | ||
5118 | return false; | |
5119 | } | |
5120 | *total = COSTS_N_INSNS (20); | |
5121 | return false; | |
5122 | } | |
5123 | ||
5124 | *total = COSTS_N_INSNS (1); | |
5125 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
5126 | && const_ok_for_arm (INTVAL (XEXP (x, 0)))) | |
5127 | { | |
5128 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5129 | return true; | |
5130 | } | |
5131 | ||
5132 | subcode = GET_CODE (XEXP (x, 1)); | |
5133 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
5134 | || subcode == LSHIFTRT | |
5135 | || subcode == ROTATE || subcode == ROTATERT) | |
5136 | { | |
5137 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5138 | *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, speed); | |
5139 | return true; | |
5140 | } | |
5141 | ||
b32f6fff KH |
5142 | /* A shift as a part of RSB costs no more than RSB itself. */ |
5143 | if (GET_CODE (XEXP (x, 0)) == MULT | |
5144 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
5145 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) | |
5146 | & (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)) | |
5147 | { | |
5148 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, speed); | |
5149 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5150 | return true; | |
5151 | } | |
5152 | ||
d5a0a47b RE |
5153 | if (subcode == MULT |
5154 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
5155 | && ((INTVAL (XEXP (XEXP (x, 1), 1)) & | |
5156 | (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)) | |
5157 | { | |
5158 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5159 | *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, speed); | |
5160 | return true; | |
5161 | } | |
5162 | ||
5163 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMPARE | |
5164 | || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE) | |
5165 | { | |
5166 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
5167 | if (GET_CODE (XEXP (XEXP (x, 1), 0)) == REG | |
5168 | && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM) | |
5169 | *total += COSTS_N_INSNS (1); | |
5170 | ||
5171 | return true; | |
5172 | } | |
5173 | ||
e2c671ba RE |
5174 | /* Fall through */ |
5175 | ||
f676971a | 5176 | case PLUS: |
d5a0a47b | 5177 | if (code == PLUS && arm_arch6 && mode == SImode |
ff069900 PB |
5178 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND |
5179 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
d5a0a47b RE |
5180 | { |
5181 | *total = COSTS_N_INSNS (1); | |
5182 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), GET_CODE (XEXP (x, 0)), | |
5183 | speed); | |
5184 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5185 | return true; | |
5186 | } | |
ff069900 | 5187 | |
d5a0a47b RE |
5188 | /* MLA: All arguments must be registers. We filter out |
5189 | multiplication by a power of two, so that we fall down into | |
5190 | the code below. */ | |
5191 | if (GET_CODE (XEXP (x, 0)) == MULT | |
5192 | && ! (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
5193 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
5194 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) | |
26da58dd | 5195 | { |
d5a0a47b RE |
5196 | /* The cost comes from the cost of the multiply. */ |
5197 | return false; | |
26da58dd PB |
5198 | } |
5199 | ||
e2c671ba | 5200 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
d5a0a47b RE |
5201 | { |
5202 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5203 | { | |
5204 | *total = COSTS_N_INSNS (1); | |
5205 | if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
5206 | && arm_const_double_rtx (XEXP (x, 1))) | |
5207 | { | |
5208 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5209 | return true; | |
5210 | } | |
5211 | ||
5212 | return false; | |
5213 | } | |
5214 | ||
5215 | *total = COSTS_N_INSNS (20); | |
5216 | return false; | |
5217 | } | |
5218 | ||
5219 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMPARE | |
5220 | || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE) | |
5221 | { | |
5222 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, speed); | |
5223 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
5224 | && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM) | |
5225 | *total += COSTS_N_INSNS (1); | |
5226 | return true; | |
5227 | } | |
e2c671ba RE |
5228 | |
5229 | /* Fall through */ | |
d5a0a47b | 5230 | |
f676971a | 5231 | case AND: case XOR: case IOR: |
e2c671ba RE |
5232 | extra_cost = 0; |
5233 | ||
5234 | /* Normally the frame registers will be spilt into reg+const during | |
5235 | reload, so it is a bad idea to combine them with other instructions, | |
5236 | since then they might not be moved outside of loops. As a compromise | |
5237 | we allow integration with ops that have a constant as their second | |
5238 | operand. */ | |
5239 | if ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
5240 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
5241 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
5242 | || (REG_OR_SUBREG_REG (XEXP (x, 0)) | |
5243 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) | |
d5a0a47b | 5244 | *total = 4; |
e2c671ba RE |
5245 | |
5246 | if (mode == DImode) | |
d5a0a47b RE |
5247 | { |
5248 | *total += COSTS_N_INSNS (2); | |
5249 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5250 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
5251 | { | |
5252 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5253 | return true; | |
5254 | } | |
e2c671ba | 5255 | |
d5a0a47b RE |
5256 | return false; |
5257 | } | |
5258 | ||
5259 | *total += COSTS_N_INSNS (1); | |
5260 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5261 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
5262 | { | |
5263 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5264 | return true; | |
5265 | } | |
5266 | subcode = GET_CODE (XEXP (x, 0)); | |
5267 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
5268 | || subcode == LSHIFTRT | |
5269 | || subcode == ROTATE || subcode == ROTATERT) | |
5270 | { | |
5271 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5272 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5273 | return true; | |
5274 | } | |
5275 | ||
5276 | if (subcode == MULT | |
5277 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
5278 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
5279 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)) | |
5280 | { | |
5281 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5282 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5283 | return true; | |
5284 | } | |
5285 | ||
5286 | if (subcode == UMIN || subcode == UMAX | |
5287 | || subcode == SMIN || subcode == SMAX) | |
5288 | { | |
5289 | *total = COSTS_N_INSNS (3); | |
5290 | return true; | |
5291 | } | |
5292 | ||
5293 | return false; | |
e2c671ba RE |
5294 | |
5295 | case MULT: | |
9b66ebb1 | 5296 | /* This should have been handled by the CPU specific routines. */ |
e6d29d15 | 5297 | gcc_unreachable (); |
e2c671ba | 5298 | |
56636818 | 5299 | case TRUNCATE: |
9b66ebb1 | 5300 | if (arm_arch3m && mode == SImode |
56636818 JL |
5301 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT |
5302 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
5303 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
5304 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
5305 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
5306 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
d5a0a47b RE |
5307 | { |
5308 | *total = rtx_cost (XEXP (XEXP (x, 0), 0), LSHIFTRT, speed); | |
5309 | return true; | |
5310 | } | |
5311 | *total = COSTS_N_INSNS (2); /* Plus the cost of the MULT */ | |
5312 | return false; | |
56636818 | 5313 | |
e2c671ba RE |
5314 | case NEG: |
5315 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
d5a0a47b RE |
5316 | { |
5317 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5318 | { | |
5319 | *total = COSTS_N_INSNS (1); | |
5320 | return false; | |
5321 | } | |
5322 | *total = COSTS_N_INSNS (2); | |
5323 | return false; | |
5324 | } | |
5325 | ||
e2c671ba RE |
5326 | /* Fall through */ |
5327 | case NOT: | |
d5a0a47b RE |
5328 | *total = COSTS_N_INSNS (ARM_NUM_REGS(mode)); |
5329 | if (mode == SImode && code == NOT) | |
5330 | { | |
5331 | subcode = GET_CODE (XEXP (x, 0)); | |
5332 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
5333 | || subcode == LSHIFTRT | |
5334 | || subcode == ROTATE || subcode == ROTATERT | |
5335 | || (subcode == MULT | |
5336 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
5337 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
5338 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) | |
5339 | { | |
5340 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5341 | /* Register shifts cost an extra cycle. */ | |
5342 | if (GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
5343 | *total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1), | |
5344 | subcode, speed); | |
5345 | return true; | |
5346 | } | |
5347 | } | |
e2c671ba | 5348 | |
d5a0a47b | 5349 | return false; |
e2c671ba RE |
5350 | |
5351 | case IF_THEN_ELSE: | |
5352 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
d5a0a47b RE |
5353 | { |
5354 | *total = COSTS_N_INSNS (4); | |
5355 | return true; | |
5356 | } | |
5357 | ||
5358 | operand = XEXP (x, 0); | |
5359 | ||
5360 | if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE | |
5361 | || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE) | |
5362 | && GET_CODE (XEXP (operand, 0)) == REG | |
5363 | && REGNO (XEXP (operand, 0)) == CC_REGNUM)) | |
5364 | *total += COSTS_N_INSNS (1); | |
5365 | *total += (rtx_cost (XEXP (x, 1), code, speed) | |
5366 | + rtx_cost (XEXP (x, 2), code, speed)); | |
5367 | return true; | |
5368 | ||
5369 | case NE: | |
5370 | if (mode == SImode && XEXP (x, 1) == const0_rtx) | |
5371 | { | |
5372 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
5373 | return true; | |
5374 | } | |
5375 | goto scc_insn; | |
5376 | ||
5377 | case GE: | |
5378 | if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) | |
5379 | && mode == SImode && XEXP (x, 1) == const0_rtx) | |
5380 | { | |
5381 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
5382 | return true; | |
5383 | } | |
5384 | goto scc_insn; | |
5385 | ||
5386 | case LT: | |
5387 | if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) | |
5388 | && mode == SImode && XEXP (x, 1) == const0_rtx) | |
5389 | { | |
5390 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
5391 | return true; | |
5392 | } | |
5393 | goto scc_insn; | |
5394 | ||
5395 | case EQ: | |
5396 | case GT: | |
5397 | case LE: | |
5398 | case GEU: | |
5399 | case LTU: | |
5400 | case GTU: | |
5401 | case LEU: | |
5402 | case UNORDERED: | |
5403 | case ORDERED: | |
5404 | case UNEQ: | |
5405 | case UNGE: | |
5406 | case UNLT: | |
5407 | case UNGT: | |
5408 | case UNLE: | |
5409 | scc_insn: | |
5410 | /* SCC insns. In the case where the comparison has already been | |
5411 | performed, then they cost 2 instructions. Otherwise they need | |
5412 | an additional comparison before them. */ | |
5413 | *total = COSTS_N_INSNS (2); | |
5414 | if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) | |
5415 | { | |
5416 | return true; | |
5417 | } | |
e2c671ba | 5418 | |
d5a0a47b | 5419 | /* Fall through */ |
e2c671ba | 5420 | case COMPARE: |
d5a0a47b RE |
5421 | if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) |
5422 | { | |
5423 | *total = 0; | |
5424 | return true; | |
5425 | } | |
5426 | ||
5427 | *total += COSTS_N_INSNS (1); | |
5428 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5429 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
5430 | { | |
5431 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5432 | return true; | |
5433 | } | |
5434 | ||
5435 | subcode = GET_CODE (XEXP (x, 0)); | |
5436 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
5437 | || subcode == LSHIFTRT | |
5438 | || subcode == ROTATE || subcode == ROTATERT) | |
5439 | { | |
5440 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5441 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5442 | return true; | |
5443 | } | |
5444 | ||
5445 | if (subcode == MULT | |
5446 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
5447 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
5448 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)) | |
5449 | { | |
5450 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5451 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5452 | return true; | |
5453 | } | |
5454 | ||
5455 | return false; | |
5456 | ||
5457 | case UMIN: | |
5458 | case UMAX: | |
5459 | case SMIN: | |
5460 | case SMAX: | |
5461 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
5462 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
5463 | || !const_ok_for_arm (INTVAL (XEXP (x, 1)))) | |
5464 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5465 | return true; | |
e2c671ba RE |
5466 | |
5467 | case ABS: | |
d5a0a47b RE |
5468 | if (GET_MODE_CLASS (mode == MODE_FLOAT)) |
5469 | { | |
5470 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5471 | { | |
5472 | *total = COSTS_N_INSNS (1); | |
5473 | return false; | |
5474 | } | |
5475 | *total = COSTS_N_INSNS (20); | |
5476 | return false; | |
5477 | } | |
5478 | *total = COSTS_N_INSNS (1); | |
5479 | if (mode == DImode) | |
5480 | *total += COSTS_N_INSNS (3); | |
5481 | return false; | |
e2c671ba RE |
5482 | |
5483 | case SIGN_EXTEND: | |
d5a0a47b RE |
5484 | if (GET_MODE_CLASS (mode) == MODE_INT) |
5485 | { | |
5486 | *total = 0; | |
5487 | if (mode == DImode) | |
5488 | *total += COSTS_N_INSNS (1); | |
5489 | ||
5490 | if (GET_MODE (XEXP (x, 0)) != SImode) | |
5491 | { | |
5492 | if (arm_arch6) | |
5493 | { | |
5494 | if (GET_CODE (XEXP (x, 0)) != MEM) | |
5495 | *total += COSTS_N_INSNS (1); | |
5496 | } | |
5497 | else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) | |
5498 | *total += COSTS_N_INSNS (2); | |
5499 | } | |
5500 | ||
5501 | return false; | |
5502 | } | |
ff069900 | 5503 | |
e2c671ba RE |
5504 | /* Fall through */ |
5505 | case ZERO_EXTEND: | |
d5a0a47b RE |
5506 | *total = 0; |
5507 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
e2c671ba | 5508 | { |
d5a0a47b RE |
5509 | if (mode == DImode) |
5510 | *total += COSTS_N_INSNS (1); | |
e2c671ba | 5511 | |
d5a0a47b RE |
5512 | if (GET_MODE (XEXP (x, 0)) != SImode) |
5513 | { | |
5514 | if (arm_arch6) | |
5515 | { | |
5516 | if (GET_CODE (XEXP (x, 0)) != MEM) | |
5517 | *total += COSTS_N_INSNS (1); | |
5518 | } | |
5519 | else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) | |
5520 | *total += COSTS_N_INSNS (GET_MODE (XEXP (x, 0)) == QImode ? | |
5521 | 1 : 2); | |
5522 | } | |
e2c671ba | 5523 | |
d5a0a47b RE |
5524 | return false; |
5525 | } | |
ad076f4e | 5526 | |
d5a0a47b RE |
5527 | switch (GET_MODE (XEXP (x, 0))) |
5528 | { | |
5a9335ef NC |
5529 | case V8QImode: |
5530 | case V4HImode: | |
5531 | case V2SImode: | |
5532 | case V4QImode: | |
5533 | case V2HImode: | |
d5a0a47b RE |
5534 | *total = COSTS_N_INSNS (1); |
5535 | return false; | |
5a9335ef | 5536 | |
ad076f4e | 5537 | default: |
e6d29d15 | 5538 | gcc_unreachable (); |
e2c671ba | 5539 | } |
e6d29d15 | 5540 | gcc_unreachable (); |
e2c671ba | 5541 | |
d5a0a47b RE |
5542 | case ZERO_EXTRACT: |
5543 | case SIGN_EXTRACT: | |
5544 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
5545 | return true; | |
5546 | ||
f676971a | 5547 | case CONST_INT: |
d5a0a47b RE |
5548 | if (const_ok_for_arm (INTVAL (x)) |
5549 | || const_ok_for_arm (~INTVAL (x))) | |
5550 | *total = COSTS_N_INSNS (1); | |
f676971a | 5551 | else |
d5a0a47b RE |
5552 | *total = COSTS_N_INSNS (arm_gen_constant (SET, mode, NULL_RTX, |
5553 | INTVAL (x), NULL_RTX, | |
5554 | NULL_RTX, 0, 0)); | |
5555 | return true; | |
f676971a EC |
5556 | |
5557 | case CONST: | |
5558 | case LABEL_REF: | |
5559 | case SYMBOL_REF: | |
d5a0a47b RE |
5560 | *total = COSTS_N_INSNS (3); |
5561 | return true; | |
f676971a | 5562 | |
571191af | 5563 | case HIGH: |
d5a0a47b RE |
5564 | *total = COSTS_N_INSNS (1); |
5565 | return true; | |
5566 | ||
571191af | 5567 | case LO_SUM: |
d5a0a47b RE |
5568 | *total = COSTS_N_INSNS (1); |
5569 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5570 | return true; | |
571191af | 5571 | |
f676971a | 5572 | case CONST_DOUBLE: |
d5a0a47b RE |
5573 | if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x)) |
5574 | *total = COSTS_N_INSNS (1); | |
5575 | else | |
5576 | *total = COSTS_N_INSNS (4); | |
5577 | return true; | |
f676971a | 5578 | |
e2c671ba | 5579 | default: |
d5a0a47b RE |
5580 | *total = COSTS_N_INSNS (4); |
5581 | return false; | |
e2c671ba RE |
5582 | } |
5583 | } | |
32de079a | 5584 | |
21b5653c RE |
5585 | /* RTX costs when optimizing for size. */ |
5586 | static bool | |
d5a0a47b RE |
5587 | arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
5588 | int *total) | |
21b5653c RE |
5589 | { |
5590 | enum machine_mode mode = GET_MODE (x); | |
09754904 | 5591 | if (TARGET_THUMB1) |
21b5653c RE |
5592 | { |
5593 | /* XXX TBD. For now, use the standard costs. */ | |
5b3e6663 | 5594 | *total = thumb1_rtx_costs (x, code, outer_code); |
21b5653c RE |
5595 | return true; |
5596 | } | |
5597 | ||
09754904 | 5598 | /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */ |
21b5653c RE |
5599 | switch (code) |
5600 | { | |
5601 | case MEM: | |
f676971a | 5602 | /* A memory access costs 1 insn if the mode is small, or the address is |
21b5653c RE |
5603 | a single register, otherwise it costs one insn per word. */ |
5604 | if (REG_P (XEXP (x, 0))) | |
5605 | *total = COSTS_N_INSNS (1); | |
5606 | else | |
5607 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5608 | return true; | |
5609 | ||
5610 | case DIV: | |
5611 | case MOD: | |
5612 | case UDIV: | |
5613 | case UMOD: | |
5614 | /* Needs a libcall, so it costs about this. */ | |
5615 | *total = COSTS_N_INSNS (2); | |
5616 | return false; | |
5617 | ||
5618 | case ROTATE: | |
5619 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
5620 | { | |
f40751dd | 5621 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
5622 | return true; |
5623 | } | |
5624 | /* Fall through */ | |
5625 | case ROTATERT: | |
5626 | case ASHIFT: | |
5627 | case LSHIFTRT: | |
5628 | case ASHIFTRT: | |
5629 | if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5630 | { | |
f40751dd | 5631 | *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
5632 | return true; |
5633 | } | |
5634 | else if (mode == SImode) | |
5635 | { | |
f40751dd | 5636 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
5637 | /* Slightly disparage register shifts, but not by much. */ |
5638 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
f40751dd | 5639 | *total += 1 + rtx_cost (XEXP (x, 1), code, false); |
21b5653c RE |
5640 | return true; |
5641 | } | |
5642 | ||
5643 | /* Needs a libcall. */ | |
5644 | *total = COSTS_N_INSNS (2); | |
5645 | return false; | |
5646 | ||
5647 | case MINUS: | |
5648 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5649 | { | |
5650 | *total = COSTS_N_INSNS (1); | |
5651 | return false; | |
5652 | } | |
5653 | ||
5654 | if (mode == SImode) | |
5655 | { | |
5656 | enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); | |
5657 | enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); | |
5658 | ||
5659 | if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT | |
5660 | || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT | |
5661 | || subcode1 == ROTATE || subcode1 == ROTATERT | |
5662 | || subcode1 == ASHIFT || subcode1 == LSHIFTRT | |
5663 | || subcode1 == ASHIFTRT) | |
5664 | { | |
5665 | /* It's just the cost of the two operands. */ | |
5666 | *total = 0; | |
5667 | return false; | |
5668 | } | |
5669 | ||
5670 | *total = COSTS_N_INSNS (1); | |
5671 | return false; | |
5672 | } | |
5673 | ||
5674 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5675 | return false; | |
5676 | ||
f676971a | 5677 | case PLUS: |
21b5653c RE |
5678 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) |
5679 | { | |
5680 | *total = COSTS_N_INSNS (1); | |
5681 | return false; | |
5682 | } | |
5683 | ||
5684 | /* Fall through */ | |
5685 | case AND: case XOR: case IOR: | |
5686 | if (mode == SImode) | |
5687 | { | |
5688 | enum rtx_code subcode = GET_CODE (XEXP (x, 0)); | |
5689 | ||
5690 | if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT | |
5691 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
5692 | || (code == AND && subcode == NOT)) | |
5693 | { | |
5694 | /* It's just the cost of the two operands. */ | |
5695 | *total = 0; | |
5696 | return false; | |
5697 | } | |
5698 | } | |
5699 | ||
5700 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5701 | return false; | |
5702 | ||
5703 | case MULT: | |
5704 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5705 | return false; | |
5706 | ||
5707 | case NEG: | |
5708 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
7ce8451d MG |
5709 | { |
5710 | *total = COSTS_N_INSNS (1); | |
5711 | return false; | |
5712 | } | |
5713 | ||
21b5653c RE |
5714 | /* Fall through */ |
5715 | case NOT: | |
5716 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5717 | ||
5718 | return false; | |
5719 | ||
5720 | case IF_THEN_ELSE: | |
5721 | *total = 0; | |
5722 | return false; | |
5723 | ||
5724 | case COMPARE: | |
5725 | if (cc_register (XEXP (x, 0), VOIDmode)) | |
5726 | * total = 0; | |
5727 | else | |
5728 | *total = COSTS_N_INSNS (1); | |
5729 | return false; | |
5730 | ||
5731 | case ABS: | |
5732 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5733 | *total = COSTS_N_INSNS (1); | |
5734 | else | |
5735 | *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode)); | |
5736 | return false; | |
5737 | ||
5738 | case SIGN_EXTEND: | |
5739 | *total = 0; | |
5740 | if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4) | |
5741 | { | |
5742 | if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | |
5743 | *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | |
5744 | } | |
5745 | if (mode == DImode) | |
5746 | *total += COSTS_N_INSNS (1); | |
5747 | return false; | |
5748 | ||
5749 | case ZERO_EXTEND: | |
5750 | *total = 0; | |
5751 | if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | |
5752 | { | |
5753 | switch (GET_MODE (XEXP (x, 0))) | |
5754 | { | |
5755 | case QImode: | |
5756 | *total += COSTS_N_INSNS (1); | |
5757 | break; | |
5758 | ||
5759 | case HImode: | |
5760 | *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | |
f676971a | 5761 | |
21b5653c RE |
5762 | case SImode: |
5763 | break; | |
5764 | ||
5765 | default: | |
5766 | *total += COSTS_N_INSNS (2); | |
5767 | } | |
5768 | } | |
5769 | ||
5770 | if (mode == DImode) | |
5771 | *total += COSTS_N_INSNS (1); | |
5772 | ||
5773 | return false; | |
5774 | ||
f676971a EC |
5775 | case CONST_INT: |
5776 | if (const_ok_for_arm (INTVAL (x))) | |
21b5653c RE |
5777 | *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0); |
5778 | else if (const_ok_for_arm (~INTVAL (x))) | |
5779 | *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1); | |
5780 | else if (const_ok_for_arm (-INTVAL (x))) | |
5781 | { | |
5782 | if (outer_code == COMPARE || outer_code == PLUS | |
5783 | || outer_code == MINUS) | |
5784 | *total = 0; | |
5785 | else | |
5786 | *total = COSTS_N_INSNS (1); | |
5787 | } | |
5788 | else | |
5789 | *total = COSTS_N_INSNS (2); | |
5790 | return true; | |
f676971a EC |
5791 | |
5792 | case CONST: | |
5793 | case LABEL_REF: | |
5794 | case SYMBOL_REF: | |
21b5653c RE |
5795 | *total = COSTS_N_INSNS (2); |
5796 | return true; | |
f676971a | 5797 | |
21b5653c RE |
5798 | case CONST_DOUBLE: |
5799 | *total = COSTS_N_INSNS (4); | |
5800 | return true; | |
5801 | ||
571191af PB |
5802 | case HIGH: |
5803 | case LO_SUM: | |
5804 | /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the | |
5805 | cost of these slightly. */ | |
5806 | *total = COSTS_N_INSNS (1) + 1; | |
5807 | return true; | |
5808 | ||
21b5653c RE |
5809 | default: |
5810 | if (mode != VOIDmode) | |
5811 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5812 | else | |
5813 | *total = COSTS_N_INSNS (4); /* How knows? */ | |
5814 | return false; | |
5815 | } | |
5816 | } | |
5817 | ||
f40751dd JH |
5818 | /* RTX costs when optimizing for size. */ |
5819 | static bool | |
d5a0a47b RE |
5820 | arm_rtx_costs (rtx x, int code, int outer_code, int *total, |
5821 | bool speed) | |
f40751dd JH |
5822 | { |
5823 | if (!speed) | |
5824 | return arm_size_rtx_costs (x, code, outer_code, total); | |
5825 | else | |
d5a0a47b RE |
5826 | return all_cores[(int)arm_tune].rtx_costs (x, code, outer_code, total, |
5827 | speed); | |
f40751dd JH |
5828 | } |
5829 | ||
5b3e6663 PB |
5830 | /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not |
5831 | supported on any "slowmul" cores, so it can be ignored. */ | |
9b66ebb1 | 5832 | |
3c50106f | 5833 | static bool |
d5a0a47b RE |
5834 | arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
5835 | int *total, bool speed) | |
3c50106f | 5836 | { |
9b66ebb1 PB |
5837 | enum machine_mode mode = GET_MODE (x); |
5838 | ||
5839 | if (TARGET_THUMB) | |
5840 | { | |
5b3e6663 | 5841 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
5842 | return true; |
5843 | } | |
f676971a | 5844 | |
9b66ebb1 PB |
5845 | switch (code) |
5846 | { | |
5847 | case MULT: | |
5848 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
5849 | || mode == DImode) | |
5850 | { | |
d5a0a47b RE |
5851 | *total = COSTS_N_INSNS (20); |
5852 | return false; | |
9b66ebb1 PB |
5853 | } |
5854 | ||
5855 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5856 | { | |
5857 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
5858 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
5859 | int cost, const_ok = const_ok_for_arm (i); | |
5860 | int j, booth_unit_size; | |
5861 | ||
f676971a | 5862 | /* Tune as appropriate. */ |
9b66ebb1 PB |
5863 | cost = const_ok ? 4 : 8; |
5864 | booth_unit_size = 2; | |
5865 | for (j = 0; i && j < 32; j += booth_unit_size) | |
5866 | { | |
5867 | i >>= booth_unit_size; | |
d5a0a47b | 5868 | cost++; |
9b66ebb1 PB |
5869 | } |
5870 | ||
d5a0a47b RE |
5871 | *total = COSTS_N_INSNS (cost); |
5872 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
9b66ebb1 PB |
5873 | return true; |
5874 | } | |
5875 | ||
d5a0a47b RE |
5876 | *total = COSTS_N_INSNS (20); |
5877 | return false; | |
f676971a | 5878 | |
9b66ebb1 | 5879 | default: |
d5a0a47b | 5880 | return arm_rtx_costs_1 (x, outer_code, total, speed);; |
9b66ebb1 | 5881 | } |
3c50106f RH |
5882 | } |
5883 | ||
9b66ebb1 PB |
5884 | |
5885 | /* RTX cost for cores with a fast multiply unit (M variants). */ | |
5886 | ||
5887 | static bool | |
d5a0a47b RE |
5888 | arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
5889 | int *total, bool speed) | |
9b66ebb1 PB |
5890 | { |
5891 | enum machine_mode mode = GET_MODE (x); | |
5892 | ||
5b3e6663 | 5893 | if (TARGET_THUMB1) |
9b66ebb1 | 5894 | { |
5b3e6663 | 5895 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
5896 | return true; |
5897 | } | |
f676971a | 5898 | |
5b3e6663 | 5899 | /* ??? should thumb2 use different costs? */ |
9b66ebb1 PB |
5900 | switch (code) |
5901 | { | |
5902 | case MULT: | |
5903 | /* There is no point basing this on the tuning, since it is always the | |
5904 | fast variant if it exists at all. */ | |
5905 | if (mode == DImode | |
5906 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
5907 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
5908 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
5909 | { | |
d5a0a47b RE |
5910 | *total = COSTS_N_INSNS(2); |
5911 | return false; | |
9b66ebb1 | 5912 | } |
f676971a | 5913 | |
9b66ebb1 | 5914 | |
d5a0a47b | 5915 | if (mode == DImode) |
9b66ebb1 | 5916 | { |
d5a0a47b RE |
5917 | *total = COSTS_N_INSNS (5); |
5918 | return false; | |
9b66ebb1 PB |
5919 | } |
5920 | ||
5921 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5922 | { | |
5923 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
5924 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
5925 | int cost, const_ok = const_ok_for_arm (i); | |
5926 | int j, booth_unit_size; | |
5927 | ||
f676971a | 5928 | /* Tune as appropriate. */ |
9b66ebb1 PB |
5929 | cost = const_ok ? 4 : 8; |
5930 | booth_unit_size = 8; | |
5931 | for (j = 0; i && j < 32; j += booth_unit_size) | |
5932 | { | |
5933 | i >>= booth_unit_size; | |
d5a0a47b | 5934 | cost++; |
9b66ebb1 PB |
5935 | } |
5936 | ||
d5a0a47b RE |
5937 | *total = COSTS_N_INSNS(cost); |
5938 | return false; | |
9b66ebb1 PB |
5939 | } |
5940 | ||
d5a0a47b RE |
5941 | if (mode == SImode) |
5942 | { | |
5943 | *total = COSTS_N_INSNS (4); | |
5944 | return false; | |
5945 | } | |
5946 | ||
5947 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5948 | { | |
5949 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5950 | { | |
5951 | *total = COSTS_N_INSNS (1); | |
5952 | return false; | |
5953 | } | |
5954 | } | |
5955 | ||
5956 | /* Requires a lib call */ | |
5957 | *total = COSTS_N_INSNS (20); | |
5958 | return false; | |
f676971a | 5959 | |
9b66ebb1 | 5960 | default: |
d5a0a47b | 5961 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
5962 | } |
5963 | } | |
5964 | ||
5965 | ||
5b3e6663 PB |
5966 | /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores, |
5967 | so it can be ignored. */ | |
9b66ebb1 PB |
5968 | |
5969 | static bool | |
d5a0a47b | 5970 | arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, int *total, bool speed) |
9b66ebb1 PB |
5971 | { |
5972 | enum machine_mode mode = GET_MODE (x); | |
5973 | ||
5974 | if (TARGET_THUMB) | |
5975 | { | |
5b3e6663 | 5976 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
5977 | return true; |
5978 | } | |
f676971a | 5979 | |
9b66ebb1 PB |
5980 | switch (code) |
5981 | { | |
d5a0a47b RE |
5982 | case COMPARE: |
5983 | if (GET_CODE (XEXP (x, 0)) != MULT) | |
5984 | return arm_rtx_costs_1 (x, outer_code, total, speed); | |
5985 | ||
5986 | /* A COMPARE of a MULT is slow on XScale; the muls instruction | |
5987 | will stall until the multiplication is complete. */ | |
5988 | *total = COSTS_N_INSNS (3); | |
5989 | return false; | |
5990 | ||
9b66ebb1 PB |
5991 | case MULT: |
5992 | /* There is no point basing this on the tuning, since it is always the | |
5993 | fast variant if it exists at all. */ | |
5994 | if (mode == DImode | |
5995 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
5996 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
5997 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
5998 | { | |
d5a0a47b RE |
5999 | *total = COSTS_N_INSNS (2); |
6000 | return false; | |
9b66ebb1 | 6001 | } |
f676971a | 6002 | |
9b66ebb1 | 6003 | |
d5a0a47b | 6004 | if (mode == DImode) |
9b66ebb1 | 6005 | { |
d5a0a47b RE |
6006 | *total = COSTS_N_INSNS (5); |
6007 | return false; | |
9b66ebb1 PB |
6008 | } |
6009 | ||
6010 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6011 | { | |
d5a0a47b RE |
6012 | /* If operand 1 is a constant we can more accurately |
6013 | calculate the cost of the multiply. The multiplier can | |
6014 | retire 15 bits on the first cycle and a further 12 on the | |
6015 | second. We do, of course, have to load the constant into | |
6016 | a register first. */ | |
6017 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); | |
6018 | /* There's a general overhead of one cycle. */ | |
6019 | int cost = 1; | |
9b66ebb1 PB |
6020 | unsigned HOST_WIDE_INT masked_const; |
6021 | ||
d5a0a47b RE |
6022 | if (i & 0x80000000) |
6023 | i = ~i; | |
6024 | ||
6025 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; | |
6026 | ||
9b66ebb1 | 6027 | masked_const = i & 0xffff8000; |
d5a0a47b | 6028 | if (masked_const != 0) |
9b66ebb1 | 6029 | { |
d5a0a47b | 6030 | cost++; |
9b66ebb1 | 6031 | masked_const = i & 0xf8000000; |
d5a0a47b RE |
6032 | if (masked_const != 0) |
6033 | cost++; | |
9b66ebb1 | 6034 | } |
d5a0a47b RE |
6035 | *total = COSTS_N_INSNS (cost); |
6036 | return false; | |
9b66ebb1 PB |
6037 | } |
6038 | ||
d5a0a47b RE |
6039 | if (mode == SImode) |
6040 | { | |
6041 | *total = COSTS_N_INSNS (3); | |
6042 | return false; | |
6043 | } | |
f676971a | 6044 | |
d5a0a47b RE |
6045 | /* Requires a lib call */ |
6046 | *total = COSTS_N_INSNS (20); | |
6047 | return false; | |
06d5588c | 6048 | |
9b66ebb1 | 6049 | default: |
d5a0a47b | 6050 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
6051 | } |
6052 | } | |
6053 | ||
6054 | ||
6055 | /* RTX costs for 9e (and later) cores. */ | |
6056 | ||
6057 | static bool | |
d5a0a47b RE |
6058 | arm_9e_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
6059 | int *total, bool speed) | |
9b66ebb1 PB |
6060 | { |
6061 | enum machine_mode mode = GET_MODE (x); | |
f676971a | 6062 | |
5b3e6663 | 6063 | if (TARGET_THUMB1) |
9b66ebb1 PB |
6064 | { |
6065 | switch (code) | |
6066 | { | |
6067 | case MULT: | |
6068 | *total = COSTS_N_INSNS (3); | |
6069 | return true; | |
f676971a | 6070 | |
9b66ebb1 | 6071 | default: |
5b3e6663 | 6072 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
6073 | return true; |
6074 | } | |
6075 | } | |
f676971a | 6076 | |
9b66ebb1 PB |
6077 | switch (code) |
6078 | { | |
6079 | case MULT: | |
6080 | /* There is no point basing this on the tuning, since it is always the | |
6081 | fast variant if it exists at all. */ | |
6082 | if (mode == DImode | |
6083 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
6084 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
6085 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
6086 | { | |
d5a0a47b RE |
6087 | *total = COSTS_N_INSNS (2); |
6088 | return false; | |
9b66ebb1 | 6089 | } |
f676971a | 6090 | |
9b66ebb1 | 6091 | |
9b66ebb1 PB |
6092 | if (mode == DImode) |
6093 | { | |
d5a0a47b RE |
6094 | *total = COSTS_N_INSNS (5); |
6095 | return false; | |
9b66ebb1 | 6096 | } |
d5a0a47b RE |
6097 | |
6098 | if (mode == SImode) | |
9b66ebb1 | 6099 | { |
d5a0a47b RE |
6100 | *total = COSTS_N_INSNS (2); |
6101 | return false; | |
9b66ebb1 PB |
6102 | } |
6103 | ||
d5a0a47b RE |
6104 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
6105 | { | |
6106 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
6107 | { | |
6108 | *total = COSTS_N_INSNS (1); | |
6109 | return false; | |
6110 | } | |
6111 | } | |
9b66ebb1 | 6112 | |
d5a0a47b RE |
6113 | *total = COSTS_N_INSNS (20); |
6114 | return false; | |
f676971a | 6115 | |
9b66ebb1 | 6116 | default: |
d5a0a47b | 6117 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
6118 | } |
6119 | } | |
dcefdf67 RH |
6120 | /* All address computations that can be done are free, but rtx cost returns |
6121 | the same for practically all of them. So we weight the different types | |
6122 | of address here in the order (most pref first): | |
d6b4baa4 | 6123 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ |
d2b6eb76 ZW |
6124 | static inline int |
6125 | arm_arm_address_cost (rtx x) | |
6126 | { | |
6127 | enum rtx_code c = GET_CODE (x); | |
6128 | ||
6129 | if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC) | |
6130 | return 0; | |
6131 | if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) | |
6132 | return 10; | |
6133 | ||
6134 | if (c == PLUS || c == MINUS) | |
6135 | { | |
d2b6eb76 ZW |
6136 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
6137 | return 2; | |
6138 | ||
ec8e098d | 6139 | if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) |
d2b6eb76 ZW |
6140 | return 3; |
6141 | ||
6142 | return 4; | |
6143 | } | |
6144 | ||
6145 | return 6; | |
6146 | } | |
6147 | ||
6148 | static inline int | |
6149 | arm_thumb_address_cost (rtx x) | |
6150 | { | |
6151 | enum rtx_code c = GET_CODE (x); | |
6152 | ||
6153 | if (c == REG) | |
6154 | return 1; | |
6155 | if (c == PLUS | |
6156 | && GET_CODE (XEXP (x, 0)) == REG | |
6157 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6158 | return 1; | |
6159 | ||
6160 | return 2; | |
6161 | } | |
6162 | ||
dcefdf67 | 6163 | static int |
f40751dd | 6164 | arm_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED) |
dcefdf67 | 6165 | { |
5b3e6663 | 6166 | return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); |
dcefdf67 RH |
6167 | } |
6168 | ||
c237e94a | 6169 | static int |
e32bac5b | 6170 | arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) |
32de079a RE |
6171 | { |
6172 | rtx i_pat, d_pat; | |
6173 | ||
d19fb8e3 NC |
6174 | /* Some true dependencies can have a higher cost depending |
6175 | on precisely how certain input operands are used. */ | |
4b3c2e48 | 6176 | if (arm_tune_xscale |
d19fb8e3 | 6177 | && REG_NOTE_KIND (link) == 0 |
eda833e3 BE |
6178 | && recog_memoized (insn) >= 0 |
6179 | && recog_memoized (dep) >= 0) | |
d19fb8e3 NC |
6180 | { |
6181 | int shift_opnum = get_attr_shift (insn); | |
6182 | enum attr_type attr_type = get_attr_type (dep); | |
6183 | ||
6184 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
6185 | operand for INSN. If we have a shifted input operand and the | |
6186 | instruction we depend on is another ALU instruction, then we may | |
6187 | have to account for an additional stall. */ | |
9b66ebb1 PB |
6188 | if (shift_opnum != 0 |
6189 | && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) | |
d19fb8e3 NC |
6190 | { |
6191 | rtx shifted_operand; | |
6192 | int opno; | |
f676971a | 6193 | |
d19fb8e3 NC |
6194 | /* Get the shifted operand. */ |
6195 | extract_insn (insn); | |
6196 | shifted_operand = recog_data.operand[shift_opnum]; | |
6197 | ||
6198 | /* Iterate over all the operands in DEP. If we write an operand | |
6199 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
6200 | cost of this dependency. */ | |
6201 | extract_insn (dep); | |
6202 | preprocess_constraints (); | |
6203 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
6204 | { | |
6205 | /* We can ignore strict inputs. */ | |
6206 | if (recog_data.operand_type[opno] == OP_IN) | |
6207 | continue; | |
6208 | ||
6209 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
6210 | shifted_operand)) | |
6211 | return 2; | |
6212 | } | |
6213 | } | |
6214 | } | |
6215 | ||
6354dc9b | 6216 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
6217 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
6218 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
6219 | return 0; |
6220 | ||
d5b7b3ae RE |
6221 | /* Call insns don't incur a stall, even if they follow a load. */ |
6222 | if (REG_NOTE_KIND (link) == 0 | |
6223 | && GET_CODE (insn) == CALL_INSN) | |
6224 | return 1; | |
6225 | ||
32de079a RE |
6226 | if ((i_pat = single_set (insn)) != NULL |
6227 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
6228 | && (d_pat = single_set (dep)) != NULL | |
6229 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
6230 | { | |
48f6efae | 6231 | rtx src_mem = XEXP (SET_SRC (i_pat), 0); |
32de079a RE |
6232 | /* This is a load after a store, there is no conflict if the load reads |
6233 | from a cached area. Assume that loads from the stack, and from the | |
f676971a | 6234 | constant pool are cached, and that others will miss. This is a |
6354dc9b | 6235 | hack. */ |
f676971a | 6236 | |
48f6efae NC |
6237 | if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) |
6238 | || reg_mentioned_p (stack_pointer_rtx, src_mem) | |
6239 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | |
6240 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | |
949d79eb | 6241 | return 1; |
32de079a RE |
6242 | } |
6243 | ||
6244 | return cost; | |
6245 | } | |
6246 | ||
9b66ebb1 | 6247 | static int fp_consts_inited = 0; |
ff9940b0 | 6248 | |
9b66ebb1 PB |
6249 | /* Only zero is valid for VFP. Other values are also valid for FPA. */ |
6250 | static const char * const strings_fp[8] = | |
62b10bbc | 6251 | { |
2b835d68 RE |
6252 | "0", "1", "2", "3", |
6253 | "4", "5", "0.5", "10" | |
6254 | }; | |
ff9940b0 | 6255 | |
9b66ebb1 | 6256 | static REAL_VALUE_TYPE values_fp[8]; |
ff9940b0 RE |
6257 | |
6258 | static void | |
9b66ebb1 | 6259 | init_fp_table (void) |
ff9940b0 RE |
6260 | { |
6261 | int i; | |
6262 | REAL_VALUE_TYPE r; | |
6263 | ||
9b66ebb1 PB |
6264 | if (TARGET_VFP) |
6265 | fp_consts_inited = 1; | |
6266 | else | |
6267 | fp_consts_inited = 8; | |
6268 | ||
6269 | for (i = 0; i < fp_consts_inited; i++) | |
ff9940b0 | 6270 | { |
9b66ebb1 PB |
6271 | r = REAL_VALUE_ATOF (strings_fp[i], DFmode); |
6272 | values_fp[i] = r; | |
ff9940b0 | 6273 | } |
ff9940b0 RE |
6274 | } |
6275 | ||
9b66ebb1 | 6276 | /* Return TRUE if rtx X is a valid immediate FP constant. */ |
cce8749e | 6277 | int |
9b66ebb1 | 6278 | arm_const_double_rtx (rtx x) |
cce8749e | 6279 | { |
ff9940b0 RE |
6280 | REAL_VALUE_TYPE r; |
6281 | int i; | |
f676971a | 6282 | |
9b66ebb1 PB |
6283 | if (!fp_consts_inited) |
6284 | init_fp_table (); | |
f676971a | 6285 | |
ff9940b0 RE |
6286 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
6287 | if (REAL_VALUE_MINUS_ZERO (r)) | |
6288 | return 0; | |
f3bb6135 | 6289 | |
9b66ebb1 PB |
6290 | for (i = 0; i < fp_consts_inited; i++) |
6291 | if (REAL_VALUES_EQUAL (r, values_fp[i])) | |
ff9940b0 | 6292 | return 1; |
f3bb6135 | 6293 | |
ff9940b0 | 6294 | return 0; |
f3bb6135 | 6295 | } |
ff9940b0 | 6296 | |
3b684012 | 6297 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
ff9940b0 | 6298 | int |
e32bac5b | 6299 | neg_const_double_rtx_ok_for_fpa (rtx x) |
ff9940b0 RE |
6300 | { |
6301 | REAL_VALUE_TYPE r; | |
6302 | int i; | |
f676971a | 6303 | |
9b66ebb1 PB |
6304 | if (!fp_consts_inited) |
6305 | init_fp_table (); | |
f676971a | 6306 | |
ff9940b0 RE |
6307 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
6308 | r = REAL_VALUE_NEGATE (r); | |
6309 | if (REAL_VALUE_MINUS_ZERO (r)) | |
6310 | return 0; | |
f3bb6135 | 6311 | |
ff9940b0 | 6312 | for (i = 0; i < 8; i++) |
9b66ebb1 | 6313 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
ff9940b0 | 6314 | return 1; |
f3bb6135 | 6315 | |
ff9940b0 | 6316 | return 0; |
f3bb6135 | 6317 | } |
f1adb0a9 JB |
6318 | |
6319 | ||
6320 | /* VFPv3 has a fairly wide range of representable immediates, formed from | |
6321 | "quarter-precision" floating-point values. These can be evaluated using this | |
6322 | formula (with ^ for exponentiation): | |
6323 | ||
6324 | -1^s * n * 2^-r | |
6325 | ||
6326 | Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that | |
6327 | 16 <= n <= 31 and 0 <= r <= 7. | |
6328 | ||
6329 | These values are mapped onto an 8-bit integer ABCDEFGH s.t. | |
6330 | ||
6331 | - A (most-significant) is the sign bit. | |
6332 | - BCD are the exponent (encoded as r XOR 3). | |
6333 | - EFGH are the mantissa (encoded as n - 16). | |
6334 | */ | |
6335 | ||
6336 | /* Return an integer index for a VFPv3 immediate operand X suitable for the | |
6337 | fconst[sd] instruction, or -1 if X isn't suitable. */ | |
6338 | static int | |
6339 | vfp3_const_double_index (rtx x) | |
6340 | { | |
6341 | REAL_VALUE_TYPE r, m; | |
6342 | int sign, exponent; | |
6343 | unsigned HOST_WIDE_INT mantissa, mant_hi; | |
6344 | unsigned HOST_WIDE_INT mask; | |
8e39e9af | 6345 | HOST_WIDE_INT m1, m2; |
f1adb0a9 JB |
6346 | int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; |
6347 | ||
6348 | if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE) | |
6349 | return -1; | |
6350 | ||
6351 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
6352 | ||
6353 | /* We can't represent these things, so detect them first. */ | |
6354 | if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r)) | |
6355 | return -1; | |
6356 | ||
6357 | /* Extract sign, exponent and mantissa. */ | |
6358 | sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0; | |
6359 | r = REAL_VALUE_ABS (r); | |
6360 | exponent = REAL_EXP (&r); | |
6361 | /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the | |
6362 | highest (sign) bit, with a fixed binary point at bit point_pos. | |
6363 | WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1 | |
6364 | bits for the mantissa, this may fail (low bits would be lost). */ | |
6365 | real_ldexp (&m, &r, point_pos - exponent); | |
8e39e9af RE |
6366 | REAL_VALUE_TO_INT (&m1, &m2, m); |
6367 | mantissa = m1; | |
6368 | mant_hi = m2; | |
f1adb0a9 JB |
6369 | |
6370 | /* If there are bits set in the low part of the mantissa, we can't | |
6371 | represent this value. */ | |
6372 | if (mantissa != 0) | |
6373 | return -1; | |
6374 | ||
6375 | /* Now make it so that mantissa contains the most-significant bits, and move | |
6376 | the point_pos to indicate that the least-significant bits have been | |
6377 | discarded. */ | |
6378 | point_pos -= HOST_BITS_PER_WIDE_INT; | |
6379 | mantissa = mant_hi; | |
6380 | ||
6381 | /* We can permit four significant bits of mantissa only, plus a high bit | |
6382 | which is always 1. */ | |
6383 | mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1; | |
6384 | if ((mantissa & mask) != 0) | |
6385 | return -1; | |
6386 | ||
6387 | /* Now we know the mantissa is in range, chop off the unneeded bits. */ | |
6388 | mantissa >>= point_pos - 5; | |
6389 | ||
6390 | /* The mantissa may be zero. Disallow that case. (It's possible to load the | |
6391 | floating-point immediate zero with Neon using an integer-zero load, but | |
6392 | that case is handled elsewhere.) */ | |
6393 | if (mantissa == 0) | |
6394 | return -1; | |
6395 | ||
6396 | gcc_assert (mantissa >= 16 && mantissa <= 31); | |
6397 | ||
6398 | /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where | |
6ed3da00 KH |
6399 | normalized significands are in the range [1, 2). (Our mantissa is shifted |
6400 | left 4 places at this point relative to normalized IEEE754 values). GCC | |
f1adb0a9 JB |
6401 | internally uses [0.5, 1) (see real.c), so the exponent returned from |
6402 | REAL_EXP must be altered. */ | |
6403 | exponent = 5 - exponent; | |
6404 | ||
6405 | if (exponent < 0 || exponent > 7) | |
6406 | return -1; | |
6407 | ||
6408 | /* Sign, mantissa and exponent are now in the correct form to plug into the | |
15dc95cb | 6409 | formula described in the comment above. */ |
f1adb0a9 JB |
6410 | return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16); |
6411 | } | |
6412 | ||
6413 | /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */ | |
6414 | int | |
6415 | vfp3_const_double_rtx (rtx x) | |
6416 | { | |
6417 | if (!TARGET_VFP3) | |
6418 | return 0; | |
6419 | ||
6420 | return vfp3_const_double_index (x) != -1; | |
6421 | } | |
6422 | ||
88f77cba JB |
6423 | /* Recognize immediates which can be used in various Neon instructions. Legal |
6424 | immediates are described by the following table (for VMVN variants, the | |
6425 | bitwise inverse of the constant shown is recognized. In either case, VMOV | |
6426 | is output and the correct instruction to use for a given constant is chosen | |
6427 | by the assembler). The constant shown is replicated across all elements of | |
6428 | the destination vector. | |
6429 | ||
6430 | insn elems variant constant (binary) | |
6431 | ---- ----- ------- ----------------- | |
6432 | vmov i32 0 00000000 00000000 00000000 abcdefgh | |
6433 | vmov i32 1 00000000 00000000 abcdefgh 00000000 | |
6434 | vmov i32 2 00000000 abcdefgh 00000000 00000000 | |
6435 | vmov i32 3 abcdefgh 00000000 00000000 00000000 | |
6436 | vmov i16 4 00000000 abcdefgh | |
6437 | vmov i16 5 abcdefgh 00000000 | |
6438 | vmvn i32 6 00000000 00000000 00000000 abcdefgh | |
6439 | vmvn i32 7 00000000 00000000 abcdefgh 00000000 | |
6440 | vmvn i32 8 00000000 abcdefgh 00000000 00000000 | |
6441 | vmvn i32 9 abcdefgh 00000000 00000000 00000000 | |
6442 | vmvn i16 10 00000000 abcdefgh | |
6443 | vmvn i16 11 abcdefgh 00000000 | |
6444 | vmov i32 12 00000000 00000000 abcdefgh 11111111 | |
6445 | vmvn i32 13 00000000 00000000 abcdefgh 11111111 | |
6446 | vmov i32 14 00000000 abcdefgh 11111111 11111111 | |
6447 | vmvn i32 15 00000000 abcdefgh 11111111 11111111 | |
6448 | vmov i8 16 abcdefgh | |
6449 | vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd | |
6450 | eeeeeeee ffffffff gggggggg hhhhhhhh | |
6451 | vmov f32 18 aBbbbbbc defgh000 00000000 00000000 | |
6452 | ||
6453 | For case 18, B = !b. Representable values are exactly those accepted by | |
6454 | vfp3_const_double_index, but are output as floating-point numbers rather | |
6455 | than indices. | |
6456 | ||
6457 | Variants 0-5 (inclusive) may also be used as immediates for the second | |
6458 | operand of VORR/VBIC instructions. | |
6459 | ||
6460 | The INVERSE argument causes the bitwise inverse of the given operand to be | |
6461 | recognized instead (used for recognizing legal immediates for the VAND/VORN | |
6462 | pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is | |
6463 | *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be | |
6464 | output, rather than the real insns vbic/vorr). | |
6465 | ||
6466 | INVERSE makes no difference to the recognition of float vectors. | |
6467 | ||
6468 | The return value is the variant of immediate as shown in the above table, or | |
6469 | -1 if the given value doesn't match any of the listed patterns. | |
6470 | */ | |
6471 | static int | |
6472 | neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, | |
6473 | rtx *modconst, int *elementwidth) | |
6474 | { | |
6475 | #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \ | |
6476 | matches = 1; \ | |
6477 | for (i = 0; i < idx; i += (STRIDE)) \ | |
6478 | if (!(TEST)) \ | |
6479 | matches = 0; \ | |
6480 | if (matches) \ | |
6481 | { \ | |
6482 | immtype = (CLASS); \ | |
6483 | elsize = (ELSIZE); \ | |
6484 | break; \ | |
6485 | } | |
6486 | ||
ff128632 | 6487 | unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); |
88f77cba JB |
6488 | unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); |
6489 | unsigned char bytes[16]; | |
6490 | int immtype = -1, matches; | |
6491 | unsigned int invmask = inverse ? 0xff : 0; | |
6492 | ||
6493 | /* Vectors of float constants. */ | |
6494 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
6495 | { | |
6496 | rtx el0 = CONST_VECTOR_ELT (op, 0); | |
6497 | REAL_VALUE_TYPE r0; | |
6498 | ||
6499 | if (!vfp3_const_double_rtx (el0)) | |
6500 | return -1; | |
6501 | ||
6502 | REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); | |
6503 | ||
6504 | for (i = 1; i < n_elts; i++) | |
6505 | { | |
6506 | rtx elt = CONST_VECTOR_ELT (op, i); | |
6507 | REAL_VALUE_TYPE re; | |
6508 | ||
6509 | REAL_VALUE_FROM_CONST_DOUBLE (re, elt); | |
6510 | ||
6511 | if (!REAL_VALUES_EQUAL (r0, re)) | |
6512 | return -1; | |
6513 | } | |
6514 | ||
6515 | if (modconst) | |
6516 | *modconst = CONST_VECTOR_ELT (op, 0); | |
6517 | ||
6518 | if (elementwidth) | |
6519 | *elementwidth = 0; | |
6520 | ||
6521 | return 18; | |
6522 | } | |
6523 | ||
6524 | /* Splat vector constant out into a byte vector. */ | |
6525 | for (i = 0; i < n_elts; i++) | |
6526 | { | |
6527 | rtx el = CONST_VECTOR_ELT (op, i); | |
6528 | unsigned HOST_WIDE_INT elpart; | |
6529 | unsigned int part, parts; | |
6530 | ||
6531 | if (GET_CODE (el) == CONST_INT) | |
6532 | { | |
6533 | elpart = INTVAL (el); | |
6534 | parts = 1; | |
6535 | } | |
6536 | else if (GET_CODE (el) == CONST_DOUBLE) | |
6537 | { | |
6538 | elpart = CONST_DOUBLE_LOW (el); | |
6539 | parts = 2; | |
6540 | } | |
6541 | else | |
6542 | gcc_unreachable (); | |
6543 | ||
6544 | for (part = 0; part < parts; part++) | |
6545 | { | |
6546 | unsigned int byte; | |
6547 | for (byte = 0; byte < innersize; byte++) | |
6548 | { | |
6549 | bytes[idx++] = (elpart & 0xff) ^ invmask; | |
6550 | elpart >>= BITS_PER_UNIT; | |
6551 | } | |
6552 | if (GET_CODE (el) == CONST_DOUBLE) | |
6553 | elpart = CONST_DOUBLE_HIGH (el); | |
6554 | } | |
6555 | } | |
6556 | ||
6557 | /* Sanity check. */ | |
6558 | gcc_assert (idx == GET_MODE_SIZE (mode)); | |
6559 | ||
6560 | do | |
6561 | { | |
6562 | CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0 | |
6563 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
6564 | ||
6565 | CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
6566 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
6567 | ||
6568 | CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0 | |
6569 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
6570 | ||
6571 | CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0 | |
6572 | && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]); | |
6573 | ||
6574 | CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0); | |
6575 | ||
6576 | CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]); | |
6577 | ||
6578 | CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff | |
6579 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
6580 | ||
6581 | CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
6582 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
6583 | ||
6584 | CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
6585 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
6586 | ||
6587 | CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
6588 | && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]); | |
6589 | ||
6590 | CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff); | |
6591 | ||
6592 | CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]); | |
6593 | ||
6594 | CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
6595 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
6596 | ||
6597 | CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
6598 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
6599 | ||
6600 | CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
6601 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
6602 | ||
6603 | CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 | |
6604 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
6605 | ||
6606 | CHECK (1, 8, 16, bytes[i] == bytes[0]); | |
6607 | ||
6608 | CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff) | |
6609 | && bytes[i] == bytes[(i + 8) % idx]); | |
6610 | } | |
6611 | while (0); | |
6612 | ||
6613 | if (immtype == -1) | |
6614 | return -1; | |
6615 | ||
6616 | if (elementwidth) | |
6617 | *elementwidth = elsize; | |
6618 | ||
6619 | if (modconst) | |
6620 | { | |
6621 | unsigned HOST_WIDE_INT imm = 0; | |
6622 | ||
cea618ac | 6623 | /* Un-invert bytes of recognized vector, if necessary. */ |
88f77cba JB |
6624 | if (invmask != 0) |
6625 | for (i = 0; i < idx; i++) | |
6626 | bytes[i] ^= invmask; | |
6627 | ||
6628 | if (immtype == 17) | |
6629 | { | |
6630 | /* FIXME: Broken on 32-bit H_W_I hosts. */ | |
6631 | gcc_assert (sizeof (HOST_WIDE_INT) == 8); | |
6632 | ||
6633 | for (i = 0; i < 8; i++) | |
6634 | imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) | |
6635 | << (i * BITS_PER_UNIT); | |
6636 | ||
6637 | *modconst = GEN_INT (imm); | |
6638 | } | |
6639 | else | |
6640 | { | |
6641 | unsigned HOST_WIDE_INT imm = 0; | |
6642 | ||
6643 | for (i = 0; i < elsize / BITS_PER_UNIT; i++) | |
6644 | imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT); | |
6645 | ||
6646 | *modconst = GEN_INT (imm); | |
6647 | } | |
6648 | } | |
6649 | ||
6650 | return immtype; | |
6651 | #undef CHECK | |
6652 | } | |
6653 | ||
6654 | /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly, | |
6655 | VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for | |
6656 | float elements), and a modified constant (whatever should be output for a | |
6657 | VMOV) in *MODCONST. */ | |
6658 | ||
6659 | int | |
6660 | neon_immediate_valid_for_move (rtx op, enum machine_mode mode, | |
6661 | rtx *modconst, int *elementwidth) | |
6662 | { | |
6663 | rtx tmpconst; | |
6664 | int tmpwidth; | |
6665 | int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth); | |
6666 | ||
6667 | if (retval == -1) | |
6668 | return 0; | |
6669 | ||
6670 | if (modconst) | |
6671 | *modconst = tmpconst; | |
6672 | ||
6673 | if (elementwidth) | |
6674 | *elementwidth = tmpwidth; | |
6675 | ||
6676 | return 1; | |
6677 | } | |
6678 | ||
6679 | /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If | |
6680 | the immediate is valid, write a constant suitable for using as an operand | |
6681 | to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to | |
6682 | *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */ | |
6683 | ||
6684 | int | |
6685 | neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse, | |
6686 | rtx *modconst, int *elementwidth) | |
6687 | { | |
6688 | rtx tmpconst; | |
6689 | int tmpwidth; | |
6690 | int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth); | |
6691 | ||
6692 | if (retval < 0 || retval > 5) | |
6693 | return 0; | |
6694 | ||
6695 | if (modconst) | |
6696 | *modconst = tmpconst; | |
6697 | ||
6698 | if (elementwidth) | |
6699 | *elementwidth = tmpwidth; | |
6700 | ||
6701 | return 1; | |
6702 | } | |
6703 | ||
6704 | /* Return a string suitable for output of Neon immediate logic operation | |
6705 | MNEM. */ | |
6706 | ||
6707 | char * | |
6708 | neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode, | |
6709 | int inverse, int quad) | |
6710 | { | |
6711 | int width, is_valid; | |
6712 | static char templ[40]; | |
6713 | ||
6714 | is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width); | |
6715 | ||
6716 | gcc_assert (is_valid != 0); | |
6717 | ||
6718 | if (quad) | |
6719 | sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width); | |
6720 | else | |
6721 | sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width); | |
6722 | ||
6723 | return templ; | |
6724 | } | |
6725 | ||
6726 | /* Output a sequence of pairwise operations to implement a reduction. | |
6727 | NOTE: We do "too much work" here, because pairwise operations work on two | |
6728 | registers-worth of operands in one go. Unfortunately we can't exploit those | |
6729 | extra calculations to do the full operation in fewer steps, I don't think. | |
6730 | Although all vector elements of the result but the first are ignored, we | |
6731 | actually calculate the same result in each of the elements. An alternative | |
6732 | such as initially loading a vector with zero to use as each of the second | |
6733 | operands would use up an additional register and take an extra instruction, | |
6734 | for no particular gain. */ | |
6735 | ||
6736 | void | |
6737 | neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode, | |
6738 | rtx (*reduc) (rtx, rtx, rtx)) | |
6739 | { | |
6740 | enum machine_mode inner = GET_MODE_INNER (mode); | |
6741 | unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner); | |
6742 | rtx tmpsum = op1; | |
6743 | ||
6744 | for (i = parts / 2; i >= 1; i /= 2) | |
6745 | { | |
6746 | rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode); | |
6747 | emit_insn (reduc (dest, tmpsum, tmpsum)); | |
6748 | tmpsum = dest; | |
6749 | } | |
6750 | } | |
6751 | ||
cea618ac | 6752 | /* Initialize a vector with non-constant elements. FIXME: We can do better |
88f77cba JB |
6753 | than the current implementation (building a vector on the stack and then |
6754 | loading it) in many cases. See rs6000.c. */ | |
6755 | ||
6756 | void | |
6757 | neon_expand_vector_init (rtx target, rtx vals) | |
6758 | { | |
6759 | enum machine_mode mode = GET_MODE (target); | |
6760 | enum machine_mode inner = GET_MODE_INNER (mode); | |
6761 | unsigned int i, n_elts = GET_MODE_NUNITS (mode); | |
6762 | rtx mem; | |
6763 | ||
6764 | gcc_assert (VECTOR_MODE_P (mode)); | |
6765 | ||
6766 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); | |
6767 | for (i = 0; i < n_elts; i++) | |
6768 | emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)), | |
6769 | XVECEXP (vals, 0, i)); | |
6770 | ||
6771 | emit_move_insn (target, mem); | |
6772 | } | |
6773 | ||
b617fc71 JB |
6774 | /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise |
6775 | ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so | |
6776 | reported source locations are bogus. */ | |
6777 | ||
6778 | static void | |
6779 | bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high, | |
6780 | const char *err) | |
6781 | { | |
6782 | HOST_WIDE_INT lane; | |
6783 | ||
6784 | gcc_assert (GET_CODE (operand) == CONST_INT); | |
6785 | ||
6786 | lane = INTVAL (operand); | |
6787 | ||
6788 | if (lane < low || lane >= high) | |
6789 | error (err); | |
6790 | } | |
6791 | ||
6792 | /* Bounds-check lanes. */ | |
6793 | ||
6794 | void | |
6795 | neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
6796 | { | |
6797 | bounds_check (operand, low, high, "lane out of range"); | |
6798 | } | |
6799 | ||
6800 | /* Bounds-check constants. */ | |
6801 | ||
6802 | void | |
6803 | neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
6804 | { | |
6805 | bounds_check (operand, low, high, "constant out of range"); | |
6806 | } | |
6807 | ||
6808 | HOST_WIDE_INT | |
6809 | neon_element_bits (enum machine_mode mode) | |
6810 | { | |
6811 | if (mode == DImode) | |
6812 | return GET_MODE_BITSIZE (mode); | |
6813 | else | |
6814 | return GET_MODE_BITSIZE (GET_MODE_INNER (mode)); | |
6815 | } | |
6816 | ||
cce8749e CH |
6817 | \f |
6818 | /* Predicates for `match_operand' and `match_operator'. */ | |
6819 | ||
9b6b54e2 | 6820 | /* Return nonzero if OP is a valid Cirrus memory address pattern. */ |
9b6b54e2 | 6821 | int |
e32bac5b | 6822 | cirrus_memory_offset (rtx op) |
9b6b54e2 NC |
6823 | { |
6824 | /* Reject eliminable registers. */ | |
6825 | if (! (reload_in_progress || reload_completed) | |
6826 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
6827 | || reg_mentioned_p (arg_pointer_rtx, op) | |
6828 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
6829 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
6830 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
6831 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
6832 | return 0; | |
6833 | ||
6834 | if (GET_CODE (op) == MEM) | |
6835 | { | |
6836 | rtx ind; | |
6837 | ||
6838 | ind = XEXP (op, 0); | |
6839 | ||
6840 | /* Match: (mem (reg)). */ | |
6841 | if (GET_CODE (ind) == REG) | |
6842 | return 1; | |
6843 | ||
6844 | /* Match: | |
6845 | (mem (plus (reg) | |
6846 | (const))). */ | |
6847 | if (GET_CODE (ind) == PLUS | |
6848 | && GET_CODE (XEXP (ind, 0)) == REG | |
6849 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
6850 | && GET_CODE (XEXP (ind, 1)) == CONST_INT) | |
6851 | return 1; | |
6852 | } | |
6853 | ||
6854 | return 0; | |
6855 | } | |
6856 | ||
f26b8ec9 | 6857 | /* Return TRUE if OP is a valid coprocessor memory address pattern. |
5b3e6663 PB |
6858 | WB is true if full writeback address modes are allowed and is false |
6859 | if limited writeback address modes (POST_INC and PRE_DEC) are | |
6860 | allowed. */ | |
9b66ebb1 PB |
6861 | |
6862 | int | |
fdd695fd | 6863 | arm_coproc_mem_operand (rtx op, bool wb) |
9b66ebb1 | 6864 | { |
fdd695fd | 6865 | rtx ind; |
9b66ebb1 | 6866 | |
fdd695fd | 6867 | /* Reject eliminable registers. */ |
9b66ebb1 PB |
6868 | if (! (reload_in_progress || reload_completed) |
6869 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
6870 | || reg_mentioned_p (arg_pointer_rtx, op) | |
6871 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
6872 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
6873 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
6874 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
6875 | return FALSE; | |
6876 | ||
59b9a953 | 6877 | /* Constants are converted into offsets from labels. */ |
fdd695fd PB |
6878 | if (GET_CODE (op) != MEM) |
6879 | return FALSE; | |
9b66ebb1 | 6880 | |
fdd695fd | 6881 | ind = XEXP (op, 0); |
9b66ebb1 | 6882 | |
fdd695fd PB |
6883 | if (reload_completed |
6884 | && (GET_CODE (ind) == LABEL_REF | |
6885 | || (GET_CODE (ind) == CONST | |
6886 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
6887 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
6888 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
6889 | return TRUE; | |
9b66ebb1 | 6890 | |
fdd695fd PB |
6891 | /* Match: (mem (reg)). */ |
6892 | if (GET_CODE (ind) == REG) | |
6893 | return arm_address_register_rtx_p (ind, 0); | |
6894 | ||
5b3e6663 PB |
6895 | /* Autoincremment addressing modes. POST_INC and PRE_DEC are |
6896 | acceptable in any case (subject to verification by | |
6897 | arm_address_register_rtx_p). We need WB to be true to accept | |
6898 | PRE_INC and POST_DEC. */ | |
6899 | if (GET_CODE (ind) == POST_INC | |
6900 | || GET_CODE (ind) == PRE_DEC | |
6901 | || (wb | |
6902 | && (GET_CODE (ind) == PRE_INC | |
6903 | || GET_CODE (ind) == POST_DEC))) | |
fdd695fd PB |
6904 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); |
6905 | ||
6906 | if (wb | |
6907 | && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY) | |
6908 | && arm_address_register_rtx_p (XEXP (ind, 0), 0) | |
6909 | && GET_CODE (XEXP (ind, 1)) == PLUS | |
6910 | && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) | |
6911 | ind = XEXP (ind, 1); | |
6912 | ||
6913 | /* Match: | |
6914 | (plus (reg) | |
6915 | (const)). */ | |
6916 | if (GET_CODE (ind) == PLUS | |
6917 | && GET_CODE (XEXP (ind, 0)) == REG | |
6918 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
6919 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
6920 | && INTVAL (XEXP (ind, 1)) > -1024 | |
6921 | && INTVAL (XEXP (ind, 1)) < 1024 | |
6922 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
6923 | return TRUE; | |
9b66ebb1 PB |
6924 | |
6925 | return FALSE; | |
6926 | } | |
6927 | ||
88f77cba JB |
6928 | /* Return TRUE if OP is a memory operand which we can load or store a vector |
6929 | to/from. If CORE is true, we're moving from ARM registers not Neon | |
6930 | registers. */ | |
6931 | int | |
6932 | neon_vector_mem_operand (rtx op, bool core) | |
6933 | { | |
6934 | rtx ind; | |
6935 | ||
6936 | /* Reject eliminable registers. */ | |
6937 | if (! (reload_in_progress || reload_completed) | |
6938 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
6939 | || reg_mentioned_p (arg_pointer_rtx, op) | |
6940 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
6941 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
6942 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
6943 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
6944 | return FALSE; | |
6945 | ||
6946 | /* Constants are converted into offsets from labels. */ | |
6947 | if (GET_CODE (op) != MEM) | |
6948 | return FALSE; | |
6949 | ||
6950 | ind = XEXP (op, 0); | |
6951 | ||
6952 | if (reload_completed | |
6953 | && (GET_CODE (ind) == LABEL_REF | |
6954 | || (GET_CODE (ind) == CONST | |
6955 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
6956 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
6957 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
6958 | return TRUE; | |
6959 | ||
6960 | /* Match: (mem (reg)). */ | |
6961 | if (GET_CODE (ind) == REG) | |
6962 | return arm_address_register_rtx_p (ind, 0); | |
6963 | ||
6964 | /* Allow post-increment with Neon registers. */ | |
6965 | if (!core && GET_CODE (ind) == POST_INC) | |
6966 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); | |
6967 | ||
6968 | #if 0 | |
6969 | /* FIXME: We can support this too if we use VLD1/VST1. */ | |
6970 | if (!core | |
6971 | && GET_CODE (ind) == POST_MODIFY | |
6972 | && arm_address_register_rtx_p (XEXP (ind, 0), 0) | |
6973 | && GET_CODE (XEXP (ind, 1)) == PLUS | |
6974 | && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) | |
6975 | ind = XEXP (ind, 1); | |
6976 | #endif | |
6977 | ||
6978 | /* Match: | |
6979 | (plus (reg) | |
6980 | (const)). */ | |
6981 | if (!core | |
6982 | && GET_CODE (ind) == PLUS | |
6983 | && GET_CODE (XEXP (ind, 0)) == REG | |
6984 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
6985 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
6986 | && INTVAL (XEXP (ind, 1)) > -1024 | |
6987 | && INTVAL (XEXP (ind, 1)) < 1016 | |
6988 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
6989 | return TRUE; | |
6990 | ||
6991 | return FALSE; | |
6992 | } | |
6993 | ||
6994 | /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct | |
6995 | type. */ | |
6996 | int | |
6997 | neon_struct_mem_operand (rtx op) | |
6998 | { | |
6999 | rtx ind; | |
7000 | ||
7001 | /* Reject eliminable registers. */ | |
7002 | if (! (reload_in_progress || reload_completed) | |
7003 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
7004 | || reg_mentioned_p (arg_pointer_rtx, op) | |
7005 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
7006 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
7007 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
7008 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
7009 | return FALSE; | |
7010 | ||
7011 | /* Constants are converted into offsets from labels. */ | |
7012 | if (GET_CODE (op) != MEM) | |
7013 | return FALSE; | |
7014 | ||
7015 | ind = XEXP (op, 0); | |
7016 | ||
7017 | if (reload_completed | |
7018 | && (GET_CODE (ind) == LABEL_REF | |
7019 | || (GET_CODE (ind) == CONST | |
7020 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
7021 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
7022 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
7023 | return TRUE; | |
7024 | ||
7025 | /* Match: (mem (reg)). */ | |
7026 | if (GET_CODE (ind) == REG) | |
7027 | return arm_address_register_rtx_p (ind, 0); | |
7028 | ||
7029 | return FALSE; | |
7030 | } | |
7031 | ||
6555b6bd RE |
7032 | /* Return true if X is a register that will be eliminated later on. */ |
7033 | int | |
7034 | arm_eliminable_register (rtx x) | |
7035 | { | |
7036 | return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM | |
7037 | || REGNO (x) == ARG_POINTER_REGNUM | |
7038 | || (REGNO (x) >= FIRST_VIRTUAL_REGISTER | |
7039 | && REGNO (x) <= LAST_VIRTUAL_REGISTER)); | |
7040 | } | |
9b66ebb1 | 7041 | |
9b66ebb1 | 7042 | /* Return GENERAL_REGS if a scratch register required to reload x to/from |
fe2d934b | 7043 | coprocessor registers. Otherwise return NO_REGS. */ |
9b66ebb1 PB |
7044 | |
7045 | enum reg_class | |
fe2d934b | 7046 | coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) |
9b66ebb1 | 7047 | { |
88f77cba JB |
7048 | if (TARGET_NEON |
7049 | && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
7050 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
7051 | && neon_vector_mem_operand (x, FALSE)) | |
7052 | return NO_REGS; | |
7053 | ||
fe2d934b | 7054 | if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) |
9b66ebb1 PB |
7055 | return NO_REGS; |
7056 | ||
7057 | return GENERAL_REGS; | |
7058 | } | |
7059 | ||
866af8a9 JB |
7060 | /* Values which must be returned in the most-significant end of the return |
7061 | register. */ | |
7062 | ||
7063 | static bool | |
586de218 | 7064 | arm_return_in_msb (const_tree valtype) |
866af8a9 JB |
7065 | { |
7066 | return (TARGET_AAPCS_BASED | |
7067 | && BYTES_BIG_ENDIAN | |
7068 | && (AGGREGATE_TYPE_P (valtype) | |
7069 | || TREE_CODE (valtype) == COMPLEX_TYPE)); | |
7070 | } | |
9b66ebb1 | 7071 | |
f0375c66 NC |
7072 | /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. |
7073 | Use by the Cirrus Maverick code which has to workaround | |
7074 | a hardware bug triggered by such instructions. */ | |
f0375c66 | 7075 | static bool |
e32bac5b | 7076 | arm_memory_load_p (rtx insn) |
9b6b54e2 NC |
7077 | { |
7078 | rtx body, lhs, rhs;; | |
7079 | ||
f0375c66 NC |
7080 | if (insn == NULL_RTX || GET_CODE (insn) != INSN) |
7081 | return false; | |
9b6b54e2 NC |
7082 | |
7083 | body = PATTERN (insn); | |
7084 | ||
7085 | if (GET_CODE (body) != SET) | |
f0375c66 | 7086 | return false; |
9b6b54e2 NC |
7087 | |
7088 | lhs = XEXP (body, 0); | |
7089 | rhs = XEXP (body, 1); | |
7090 | ||
f0375c66 NC |
7091 | lhs = REG_OR_SUBREG_RTX (lhs); |
7092 | ||
7093 | /* If the destination is not a general purpose | |
7094 | register we do not have to worry. */ | |
7095 | if (GET_CODE (lhs) != REG | |
7096 | || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) | |
7097 | return false; | |
7098 | ||
7099 | /* As well as loads from memory we also have to react | |
7100 | to loads of invalid constants which will be turned | |
7101 | into loads from the minipool. */ | |
7102 | return (GET_CODE (rhs) == MEM | |
7103 | || GET_CODE (rhs) == SYMBOL_REF | |
7104 | || note_invalid_constants (insn, -1, false)); | |
9b6b54e2 NC |
7105 | } |
7106 | ||
f0375c66 | 7107 | /* Return TRUE if INSN is a Cirrus instruction. */ |
f0375c66 | 7108 | static bool |
e32bac5b | 7109 | arm_cirrus_insn_p (rtx insn) |
9b6b54e2 NC |
7110 | { |
7111 | enum attr_cirrus attr; | |
7112 | ||
e6d29d15 | 7113 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
7114 | if (!insn |
7115 | || GET_CODE (insn) != INSN | |
7116 | || GET_CODE (PATTERN (insn)) == USE | |
7117 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
7118 | return 0; | |
7119 | ||
7120 | attr = get_attr_cirrus (insn); | |
7121 | ||
f0375c66 | 7122 | return attr != CIRRUS_NOT; |
9b6b54e2 NC |
7123 | } |
7124 | ||
7125 | /* Cirrus reorg for invalid instruction combinations. */ | |
9b6b54e2 | 7126 | static void |
e32bac5b | 7127 | cirrus_reorg (rtx first) |
9b6b54e2 NC |
7128 | { |
7129 | enum attr_cirrus attr; | |
7130 | rtx body = PATTERN (first); | |
7131 | rtx t; | |
7132 | int nops; | |
7133 | ||
7134 | /* Any branch must be followed by 2 non Cirrus instructions. */ | |
7135 | if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) | |
7136 | { | |
7137 | nops = 0; | |
7138 | t = next_nonnote_insn (first); | |
7139 | ||
f0375c66 | 7140 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
7141 | ++ nops; |
7142 | ||
f0375c66 | 7143 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
7144 | ++ nops; |
7145 | ||
7146 | while (nops --) | |
7147 | emit_insn_after (gen_nop (), first); | |
7148 | ||
7149 | return; | |
7150 | } | |
7151 | ||
7152 | /* (float (blah)) is in parallel with a clobber. */ | |
7153 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
7154 | body = XVECEXP (body, 0, 0); | |
7155 | ||
7156 | if (GET_CODE (body) == SET) | |
7157 | { | |
7158 | rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); | |
7159 | ||
7160 | /* cfldrd, cfldr64, cfstrd, cfstr64 must | |
7161 | be followed by a non Cirrus insn. */ | |
7162 | if (get_attr_cirrus (first) == CIRRUS_DOUBLE) | |
7163 | { | |
f0375c66 | 7164 | if (arm_cirrus_insn_p (next_nonnote_insn (first))) |
9b6b54e2 NC |
7165 | emit_insn_after (gen_nop (), first); |
7166 | ||
7167 | return; | |
7168 | } | |
f0375c66 | 7169 | else if (arm_memory_load_p (first)) |
9b6b54e2 NC |
7170 | { |
7171 | unsigned int arm_regno; | |
7172 | ||
7173 | /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, | |
7174 | ldr/cfmv64hr combination where the Rd field is the same | |
7175 | in both instructions must be split with a non Cirrus | |
7176 | insn. Example: | |
7177 | ||
7178 | ldr r0, blah | |
7179 | nop | |
7180 | cfmvsr mvf0, r0. */ | |
7181 | ||
7182 | /* Get Arm register number for ldr insn. */ | |
7183 | if (GET_CODE (lhs) == REG) | |
7184 | arm_regno = REGNO (lhs); | |
9b6b54e2 | 7185 | else |
e6d29d15 NS |
7186 | { |
7187 | gcc_assert (GET_CODE (rhs) == REG); | |
7188 | arm_regno = REGNO (rhs); | |
7189 | } | |
9b6b54e2 NC |
7190 | |
7191 | /* Next insn. */ | |
7192 | first = next_nonnote_insn (first); | |
7193 | ||
f0375c66 | 7194 | if (! arm_cirrus_insn_p (first)) |
9b6b54e2 NC |
7195 | return; |
7196 | ||
7197 | body = PATTERN (first); | |
7198 | ||
7199 | /* (float (blah)) is in parallel with a clobber. */ | |
7200 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) | |
7201 | body = XVECEXP (body, 0, 0); | |
7202 | ||
7203 | if (GET_CODE (body) == FLOAT) | |
7204 | body = XEXP (body, 0); | |
7205 | ||
7206 | if (get_attr_cirrus (first) == CIRRUS_MOVE | |
7207 | && GET_CODE (XEXP (body, 1)) == REG | |
7208 | && arm_regno == REGNO (XEXP (body, 1))) | |
7209 | emit_insn_after (gen_nop (), first); | |
7210 | ||
7211 | return; | |
7212 | } | |
7213 | } | |
7214 | ||
e6d29d15 | 7215 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
7216 | if (!first |
7217 | || GET_CODE (first) != INSN | |
7218 | || GET_CODE (PATTERN (first)) == USE | |
7219 | || GET_CODE (PATTERN (first)) == CLOBBER) | |
7220 | return; | |
7221 | ||
7222 | attr = get_attr_cirrus (first); | |
7223 | ||
7224 | /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) | |
7225 | must be followed by a non-coprocessor instruction. */ | |
7226 | if (attr == CIRRUS_COMPARE) | |
7227 | { | |
7228 | nops = 0; | |
7229 | ||
7230 | t = next_nonnote_insn (first); | |
7231 | ||
f0375c66 | 7232 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
7233 | ++ nops; |
7234 | ||
f0375c66 | 7235 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
7236 | ++ nops; |
7237 | ||
7238 | while (nops --) | |
7239 | emit_insn_after (gen_nop (), first); | |
7240 | ||
7241 | return; | |
7242 | } | |
7243 | } | |
7244 | ||
2b835d68 RE |
7245 | /* Return TRUE if X references a SYMBOL_REF. */ |
7246 | int | |
e32bac5b | 7247 | symbol_mentioned_p (rtx x) |
2b835d68 | 7248 | { |
1d6e90ac NC |
7249 | const char * fmt; |
7250 | int i; | |
2b835d68 RE |
7251 | |
7252 | if (GET_CODE (x) == SYMBOL_REF) | |
7253 | return 1; | |
7254 | ||
d3585b76 DJ |
7255 | /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they |
7256 | are constant offsets, not symbols. */ | |
7257 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
7258 | return 0; | |
7259 | ||
2b835d68 | 7260 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
f676971a | 7261 | |
2b835d68 RE |
7262 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
7263 | { | |
7264 | if (fmt[i] == 'E') | |
7265 | { | |
1d6e90ac | 7266 | int j; |
2b835d68 RE |
7267 | |
7268 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7269 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
7270 | return 1; | |
7271 | } | |
7272 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
7273 | return 1; | |
7274 | } | |
7275 | ||
7276 | return 0; | |
7277 | } | |
7278 | ||
7279 | /* Return TRUE if X references a LABEL_REF. */ | |
7280 | int | |
e32bac5b | 7281 | label_mentioned_p (rtx x) |
2b835d68 | 7282 | { |
1d6e90ac NC |
7283 | const char * fmt; |
7284 | int i; | |
2b835d68 RE |
7285 | |
7286 | if (GET_CODE (x) == LABEL_REF) | |
7287 | return 1; | |
7288 | ||
d3585b76 DJ |
7289 | /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing |
7290 | instruction, but they are constant offsets, not symbols. */ | |
7291 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
7292 | return 0; | |
7293 | ||
2b835d68 RE |
7294 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
7295 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
7296 | { | |
7297 | if (fmt[i] == 'E') | |
7298 | { | |
1d6e90ac | 7299 | int j; |
2b835d68 RE |
7300 | |
7301 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7302 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
7303 | return 1; | |
7304 | } | |
7305 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
7306 | return 1; | |
7307 | } | |
7308 | ||
7309 | return 0; | |
7310 | } | |
7311 | ||
d3585b76 DJ |
7312 | int |
7313 | tls_mentioned_p (rtx x) | |
7314 | { | |
7315 | switch (GET_CODE (x)) | |
7316 | { | |
7317 | case CONST: | |
7318 | return tls_mentioned_p (XEXP (x, 0)); | |
7319 | ||
7320 | case UNSPEC: | |
7321 | if (XINT (x, 1) == UNSPEC_TLS) | |
7322 | return 1; | |
7323 | ||
7324 | default: | |
7325 | return 0; | |
7326 | } | |
7327 | } | |
7328 | ||
7329 | /* Must not copy a SET whose source operand is PC-relative. */ | |
7330 | ||
7331 | static bool | |
7332 | arm_cannot_copy_insn_p (rtx insn) | |
7333 | { | |
7334 | rtx pat = PATTERN (insn); | |
7335 | ||
10ae7c7b | 7336 | if (GET_CODE (pat) == SET) |
d3585b76 | 7337 | { |
10ae7c7b | 7338 | rtx rhs = SET_SRC (pat); |
d3585b76 DJ |
7339 | |
7340 | if (GET_CODE (rhs) == UNSPEC | |
7341 | && XINT (rhs, 1) == UNSPEC_PIC_BASE) | |
7342 | return TRUE; | |
7343 | ||
7344 | if (GET_CODE (rhs) == MEM | |
7345 | && GET_CODE (XEXP (rhs, 0)) == UNSPEC | |
7346 | && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE) | |
7347 | return TRUE; | |
7348 | } | |
7349 | ||
7350 | return FALSE; | |
7351 | } | |
7352 | ||
ff9940b0 | 7353 | enum rtx_code |
e32bac5b | 7354 | minmax_code (rtx x) |
ff9940b0 RE |
7355 | { |
7356 | enum rtx_code code = GET_CODE (x); | |
7357 | ||
e6d29d15 NS |
7358 | switch (code) |
7359 | { | |
7360 | case SMAX: | |
7361 | return GE; | |
7362 | case SMIN: | |
7363 | return LE; | |
7364 | case UMIN: | |
7365 | return LEU; | |
7366 | case UMAX: | |
7367 | return GEU; | |
7368 | default: | |
7369 | gcc_unreachable (); | |
7370 | } | |
ff9940b0 RE |
7371 | } |
7372 | ||
6354dc9b | 7373 | /* Return 1 if memory locations are adjacent. */ |
f3bb6135 | 7374 | int |
e32bac5b | 7375 | adjacent_mem_locations (rtx a, rtx b) |
ff9940b0 | 7376 | { |
15b5c4c1 RE |
7377 | /* We don't guarantee to preserve the order of these memory refs. */ |
7378 | if (volatile_refs_p (a) || volatile_refs_p (b)) | |
7379 | return 0; | |
7380 | ||
ff9940b0 RE |
7381 | if ((GET_CODE (XEXP (a, 0)) == REG |
7382 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
7383 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
7384 | && (GET_CODE (XEXP (b, 0)) == REG | |
7385 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
7386 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
7387 | { | |
6555b6bd RE |
7388 | HOST_WIDE_INT val0 = 0, val1 = 0; |
7389 | rtx reg0, reg1; | |
7390 | int val_diff; | |
f676971a | 7391 | |
ff9940b0 RE |
7392 | if (GET_CODE (XEXP (a, 0)) == PLUS) |
7393 | { | |
6555b6bd | 7394 | reg0 = XEXP (XEXP (a, 0), 0); |
ff9940b0 RE |
7395 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); |
7396 | } | |
7397 | else | |
6555b6bd | 7398 | reg0 = XEXP (a, 0); |
1d6e90ac | 7399 | |
ff9940b0 RE |
7400 | if (GET_CODE (XEXP (b, 0)) == PLUS) |
7401 | { | |
6555b6bd | 7402 | reg1 = XEXP (XEXP (b, 0), 0); |
ff9940b0 RE |
7403 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); |
7404 | } | |
7405 | else | |
6555b6bd | 7406 | reg1 = XEXP (b, 0); |
1d6e90ac | 7407 | |
e32bac5b RE |
7408 | /* Don't accept any offset that will require multiple |
7409 | instructions to handle, since this would cause the | |
7410 | arith_adjacentmem pattern to output an overlong sequence. */ | |
c75a3ddc PB |
7411 | if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1)) |
7412 | return 0; | |
f676971a | 7413 | |
6555b6bd RE |
7414 | /* Don't allow an eliminable register: register elimination can make |
7415 | the offset too large. */ | |
7416 | if (arm_eliminable_register (reg0)) | |
7417 | return 0; | |
7418 | ||
7419 | val_diff = val1 - val0; | |
15b5c4c1 RE |
7420 | |
7421 | if (arm_ld_sched) | |
7422 | { | |
7423 | /* If the target has load delay slots, then there's no benefit | |
7424 | to using an ldm instruction unless the offset is zero and | |
7425 | we are optimizing for size. */ | |
7426 | return (optimize_size && (REGNO (reg0) == REGNO (reg1)) | |
7427 | && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4) | |
7428 | && (val_diff == 4 || val_diff == -4)); | |
7429 | } | |
7430 | ||
6555b6bd RE |
7431 | return ((REGNO (reg0) == REGNO (reg1)) |
7432 | && (val_diff == 4 || val_diff == -4)); | |
ff9940b0 | 7433 | } |
6555b6bd | 7434 | |
ff9940b0 RE |
7435 | return 0; |
7436 | } | |
7437 | ||
84ed5e79 | 7438 | int |
e32bac5b RE |
7439 | load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
7440 | HOST_WIDE_INT *load_offset) | |
84ed5e79 RE |
7441 | { |
7442 | int unsorted_regs[4]; | |
7443 | HOST_WIDE_INT unsorted_offsets[4]; | |
7444 | int order[4]; | |
ad076f4e | 7445 | int base_reg = -1; |
84ed5e79 RE |
7446 | int i; |
7447 | ||
1d6e90ac NC |
7448 | /* Can only handle 2, 3, or 4 insns at present, |
7449 | though could be easily extended if required. */ | |
e6d29d15 | 7450 | gcc_assert (nops >= 2 && nops <= 4); |
84ed5e79 | 7451 | |
f0b4bdd5 RE |
7452 | memset (order, 0, 4 * sizeof (int)); |
7453 | ||
84ed5e79 | 7454 | /* Loop over the operands and check that the memory references are |
112cdef5 | 7455 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
7456 | the same time, extract the target register, and the memory |
7457 | offsets. */ | |
7458 | for (i = 0; i < nops; i++) | |
7459 | { | |
7460 | rtx reg; | |
7461 | rtx offset; | |
7462 | ||
56636818 JL |
7463 | /* Convert a subreg of a mem into the mem itself. */ |
7464 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 7465 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 7466 | |
e6d29d15 | 7467 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
7468 | |
7469 | /* Don't reorder volatile memory references; it doesn't seem worth | |
7470 | looking for the case where the order is ok anyway. */ | |
7471 | if (MEM_VOLATILE_P (operands[nops + i])) | |
7472 | return 0; | |
7473 | ||
7474 | offset = const0_rtx; | |
7475 | ||
7476 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
7477 | || (GET_CODE (reg) == SUBREG | |
7478 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7479 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
7480 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
7481 | == REG) | |
7482 | || (GET_CODE (reg) == SUBREG | |
7483 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7484 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
7485 | == CONST_INT))) | |
7486 | { | |
7487 | if (i == 0) | |
7488 | { | |
d5b7b3ae | 7489 | base_reg = REGNO (reg); |
84ed5e79 RE |
7490 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
7491 | ? REGNO (operands[i]) | |
7492 | : REGNO (SUBREG_REG (operands[i]))); | |
7493 | order[0] = 0; | |
7494 | } | |
f676971a | 7495 | else |
84ed5e79 | 7496 | { |
6354dc9b | 7497 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
7498 | /* Not addressed from the same base register. */ |
7499 | return 0; | |
7500 | ||
7501 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
7502 | ? REGNO (operands[i]) | |
7503 | : REGNO (SUBREG_REG (operands[i]))); | |
7504 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
7505 | order[0] = i; | |
7506 | } | |
7507 | ||
7508 | /* If it isn't an integer register, or if it overwrites the | |
7509 | base register but isn't the last insn in the list, then | |
7510 | we can't do this. */ | |
7511 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | |
7512 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) | |
7513 | return 0; | |
7514 | ||
7515 | unsorted_offsets[i] = INTVAL (offset); | |
7516 | } | |
7517 | else | |
7518 | /* Not a suitable memory address. */ | |
7519 | return 0; | |
7520 | } | |
7521 | ||
7522 | /* All the useful information has now been extracted from the | |
7523 | operands into unsorted_regs and unsorted_offsets; additionally, | |
7524 | order[0] has been set to the lowest numbered register in the | |
7525 | list. Sort the registers into order, and check that the memory | |
7526 | offsets are ascending and adjacent. */ | |
7527 | ||
7528 | for (i = 1; i < nops; i++) | |
7529 | { | |
7530 | int j; | |
7531 | ||
7532 | order[i] = order[i - 1]; | |
7533 | for (j = 0; j < nops; j++) | |
7534 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
7535 | && (order[i] == order[i - 1] | |
7536 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
7537 | order[i] = j; | |
7538 | ||
7539 | /* Have we found a suitable register? if not, one must be used more | |
7540 | than once. */ | |
7541 | if (order[i] == order[i - 1]) | |
7542 | return 0; | |
7543 | ||
7544 | /* Is the memory address adjacent and ascending? */ | |
7545 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
7546 | return 0; | |
7547 | } | |
7548 | ||
7549 | if (base) | |
7550 | { | |
7551 | *base = base_reg; | |
7552 | ||
7553 | for (i = 0; i < nops; i++) | |
7554 | regs[i] = unsorted_regs[order[i]]; | |
7555 | ||
7556 | *load_offset = unsorted_offsets[order[0]]; | |
7557 | } | |
7558 | ||
7559 | if (unsorted_offsets[order[0]] == 0) | |
7560 | return 1; /* ldmia */ | |
7561 | ||
5b3e6663 | 7562 | if (TARGET_ARM && unsorted_offsets[order[0]] == 4) |
84ed5e79 RE |
7563 | return 2; /* ldmib */ |
7564 | ||
5b3e6663 | 7565 | if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) |
84ed5e79 RE |
7566 | return 3; /* ldmda */ |
7567 | ||
7568 | if (unsorted_offsets[order[nops - 1]] == -4) | |
7569 | return 4; /* ldmdb */ | |
7570 | ||
949d79eb RE |
7571 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm |
7572 | if the offset isn't small enough. The reason 2 ldrs are faster | |
7573 | is because these ARMs are able to do more than one cache access | |
7574 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
7575 | whilst the ARM8 has a double bandwidth cache. This means that | |
7576 | these cores can do both an instruction fetch and a data fetch in | |
7577 | a single cycle, so the trick of calculating the address into a | |
7578 | scratch register (one of the result regs) and then doing a load | |
7579 | multiple actually becomes slower (and no smaller in code size). | |
7580 | That is the transformation | |
f676971a | 7581 | |
6cc8c0b3 NC |
7582 | ldr rd1, [rbase + offset] |
7583 | ldr rd2, [rbase + offset + 4] | |
f676971a | 7584 | |
6cc8c0b3 | 7585 | to |
f676971a | 7586 | |
6cc8c0b3 NC |
7587 | add rd1, rbase, offset |
7588 | ldmia rd1, {rd1, rd2} | |
f676971a | 7589 | |
949d79eb RE |
7590 | produces worse code -- '3 cycles + any stalls on rd2' instead of |
7591 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
7592 | access per cycle, the first sequence could never complete in less | |
7593 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
7594 | would make better use of sequential accesses if not hitting the | |
7595 | cache. | |
7596 | ||
7597 | We cheat here and test 'arm_ld_sched' which we currently know to | |
7598 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
7599 | changes, then the test below needs to be reworked. */ | |
f5a1b0d2 | 7600 | if (nops == 2 && arm_ld_sched) |
b36ba79f RE |
7601 | return 0; |
7602 | ||
84ed5e79 RE |
7603 | /* Can't do it without setting up the offset, only do this if it takes |
7604 | no more than one insn. */ | |
f676971a | 7605 | return (const_ok_for_arm (unsorted_offsets[order[0]]) |
84ed5e79 RE |
7606 | || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; |
7607 | } | |
7608 | ||
cd2b33d0 | 7609 | const char * |
e32bac5b | 7610 | emit_ldm_seq (rtx *operands, int nops) |
84ed5e79 RE |
7611 | { |
7612 | int regs[4]; | |
7613 | int base_reg; | |
7614 | HOST_WIDE_INT offset; | |
7615 | char buf[100]; | |
7616 | int i; | |
7617 | ||
7618 | switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
7619 | { | |
7620 | case 1: | |
5b3e6663 | 7621 | strcpy (buf, "ldm%(ia%)\t"); |
84ed5e79 RE |
7622 | break; |
7623 | ||
7624 | case 2: | |
5b3e6663 | 7625 | strcpy (buf, "ldm%(ib%)\t"); |
84ed5e79 RE |
7626 | break; |
7627 | ||
7628 | case 3: | |
5b3e6663 | 7629 | strcpy (buf, "ldm%(da%)\t"); |
84ed5e79 RE |
7630 | break; |
7631 | ||
7632 | case 4: | |
5b3e6663 | 7633 | strcpy (buf, "ldm%(db%)\t"); |
84ed5e79 RE |
7634 | break; |
7635 | ||
7636 | case 5: | |
7637 | if (offset >= 0) | |
7638 | sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
7639 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
7640 | (long) offset); | |
7641 | else | |
7642 | sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
7643 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
7644 | (long) -offset); | |
7645 | output_asm_insn (buf, operands); | |
7646 | base_reg = regs[0]; | |
5b3e6663 | 7647 | strcpy (buf, "ldm%(ia%)\t"); |
84ed5e79 RE |
7648 | break; |
7649 | ||
7650 | default: | |
e6d29d15 | 7651 | gcc_unreachable (); |
84ed5e79 RE |
7652 | } |
7653 | ||
f676971a | 7654 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, |
84ed5e79 RE |
7655 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); |
7656 | ||
7657 | for (i = 1; i < nops; i++) | |
7658 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
7659 | reg_names[regs[i]]); | |
7660 | ||
7661 | strcat (buf, "}\t%@ phole ldm"); | |
7662 | ||
7663 | output_asm_insn (buf, operands); | |
7664 | return ""; | |
7665 | } | |
7666 | ||
7667 | int | |
e32bac5b RE |
7668 | store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
7669 | HOST_WIDE_INT * load_offset) | |
84ed5e79 RE |
7670 | { |
7671 | int unsorted_regs[4]; | |
7672 | HOST_WIDE_INT unsorted_offsets[4]; | |
7673 | int order[4]; | |
ad076f4e | 7674 | int base_reg = -1; |
84ed5e79 RE |
7675 | int i; |
7676 | ||
7677 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | |
7678 | extended if required. */ | |
e6d29d15 | 7679 | gcc_assert (nops >= 2 && nops <= 4); |
84ed5e79 | 7680 | |
f0b4bdd5 RE |
7681 | memset (order, 0, 4 * sizeof (int)); |
7682 | ||
84ed5e79 | 7683 | /* Loop over the operands and check that the memory references are |
112cdef5 | 7684 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
7685 | the same time, extract the target register, and the memory |
7686 | offsets. */ | |
7687 | for (i = 0; i < nops; i++) | |
7688 | { | |
7689 | rtx reg; | |
7690 | rtx offset; | |
7691 | ||
56636818 JL |
7692 | /* Convert a subreg of a mem into the mem itself. */ |
7693 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 7694 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 7695 | |
e6d29d15 | 7696 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
7697 | |
7698 | /* Don't reorder volatile memory references; it doesn't seem worth | |
7699 | looking for the case where the order is ok anyway. */ | |
7700 | if (MEM_VOLATILE_P (operands[nops + i])) | |
7701 | return 0; | |
7702 | ||
7703 | offset = const0_rtx; | |
7704 | ||
7705 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
7706 | || (GET_CODE (reg) == SUBREG | |
7707 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7708 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
7709 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
7710 | == REG) | |
7711 | || (GET_CODE (reg) == SUBREG | |
7712 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7713 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
7714 | == CONST_INT))) | |
7715 | { | |
7716 | if (i == 0) | |
7717 | { | |
62b10bbc | 7718 | base_reg = REGNO (reg); |
84ed5e79 RE |
7719 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
7720 | ? REGNO (operands[i]) | |
7721 | : REGNO (SUBREG_REG (operands[i]))); | |
7722 | order[0] = 0; | |
7723 | } | |
f676971a | 7724 | else |
84ed5e79 | 7725 | { |
6354dc9b | 7726 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
7727 | /* Not addressed from the same base register. */ |
7728 | return 0; | |
7729 | ||
7730 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
7731 | ? REGNO (operands[i]) | |
7732 | : REGNO (SUBREG_REG (operands[i]))); | |
7733 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
7734 | order[0] = i; | |
7735 | } | |
7736 | ||
7737 | /* If it isn't an integer register, then we can't do this. */ | |
7738 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | |
7739 | return 0; | |
7740 | ||
7741 | unsorted_offsets[i] = INTVAL (offset); | |
7742 | } | |
7743 | else | |
7744 | /* Not a suitable memory address. */ | |
7745 | return 0; | |
7746 | } | |
7747 | ||
7748 | /* All the useful information has now been extracted from the | |
7749 | operands into unsorted_regs and unsorted_offsets; additionally, | |
7750 | order[0] has been set to the lowest numbered register in the | |
7751 | list. Sort the registers into order, and check that the memory | |
7752 | offsets are ascending and adjacent. */ | |
7753 | ||
7754 | for (i = 1; i < nops; i++) | |
7755 | { | |
7756 | int j; | |
7757 | ||
7758 | order[i] = order[i - 1]; | |
7759 | for (j = 0; j < nops; j++) | |
7760 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
7761 | && (order[i] == order[i - 1] | |
7762 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
7763 | order[i] = j; | |
7764 | ||
7765 | /* Have we found a suitable register? if not, one must be used more | |
7766 | than once. */ | |
7767 | if (order[i] == order[i - 1]) | |
7768 | return 0; | |
7769 | ||
7770 | /* Is the memory address adjacent and ascending? */ | |
7771 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
7772 | return 0; | |
7773 | } | |
7774 | ||
7775 | if (base) | |
7776 | { | |
7777 | *base = base_reg; | |
7778 | ||
7779 | for (i = 0; i < nops; i++) | |
7780 | regs[i] = unsorted_regs[order[i]]; | |
7781 | ||
7782 | *load_offset = unsorted_offsets[order[0]]; | |
7783 | } | |
7784 | ||
7785 | if (unsorted_offsets[order[0]] == 0) | |
7786 | return 1; /* stmia */ | |
7787 | ||
7788 | if (unsorted_offsets[order[0]] == 4) | |
7789 | return 2; /* stmib */ | |
7790 | ||
7791 | if (unsorted_offsets[order[nops - 1]] == 0) | |
7792 | return 3; /* stmda */ | |
7793 | ||
7794 | if (unsorted_offsets[order[nops - 1]] == -4) | |
7795 | return 4; /* stmdb */ | |
7796 | ||
7797 | return 0; | |
7798 | } | |
7799 | ||
cd2b33d0 | 7800 | const char * |
e32bac5b | 7801 | emit_stm_seq (rtx *operands, int nops) |
84ed5e79 RE |
7802 | { |
7803 | int regs[4]; | |
7804 | int base_reg; | |
7805 | HOST_WIDE_INT offset; | |
7806 | char buf[100]; | |
7807 | int i; | |
7808 | ||
7809 | switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
7810 | { | |
7811 | case 1: | |
5b3e6663 | 7812 | strcpy (buf, "stm%(ia%)\t"); |
84ed5e79 RE |
7813 | break; |
7814 | ||
7815 | case 2: | |
5b3e6663 | 7816 | strcpy (buf, "stm%(ib%)\t"); |
84ed5e79 RE |
7817 | break; |
7818 | ||
7819 | case 3: | |
5b3e6663 | 7820 | strcpy (buf, "stm%(da%)\t"); |
84ed5e79 RE |
7821 | break; |
7822 | ||
7823 | case 4: | |
5b3e6663 | 7824 | strcpy (buf, "stm%(db%)\t"); |
84ed5e79 RE |
7825 | break; |
7826 | ||
7827 | default: | |
e6d29d15 | 7828 | gcc_unreachable (); |
84ed5e79 RE |
7829 | } |
7830 | ||
f676971a | 7831 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, |
84ed5e79 RE |
7832 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); |
7833 | ||
7834 | for (i = 1; i < nops; i++) | |
7835 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
7836 | reg_names[regs[i]]); | |
7837 | ||
7838 | strcat (buf, "}\t%@ phole stm"); | |
7839 | ||
7840 | output_asm_insn (buf, operands); | |
7841 | return ""; | |
7842 | } | |
ff9940b0 | 7843 | \f |
6354dc9b | 7844 | /* Routines for use in generating RTL. */ |
1d6e90ac | 7845 | |
f3bb6135 | 7846 | rtx |
e32bac5b | 7847 | arm_gen_load_multiple (int base_regno, int count, rtx from, int up, |
50ed9cea | 7848 | int write_back, rtx basemem, HOST_WIDE_INT *offsetp) |
ff9940b0 | 7849 | { |
50ed9cea | 7850 | HOST_WIDE_INT offset = *offsetp; |
ff9940b0 RE |
7851 | int i = 0, j; |
7852 | rtx result; | |
7853 | int sign = up ? 1 : -1; | |
50ed9cea | 7854 | rtx mem, addr; |
ff9940b0 | 7855 | |
d19fb8e3 | 7856 | /* XScale has load-store double instructions, but they have stricter |
1e5f1716 | 7857 | alignment requirements than load-store multiple, so we cannot |
d19fb8e3 NC |
7858 | use them. |
7859 | ||
7860 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
7861 | the pipeline until completion. | |
7862 | ||
7863 | NREGS CYCLES | |
7864 | 1 3 | |
7865 | 2 4 | |
7866 | 3 5 | |
7867 | 4 6 | |
7868 | ||
7869 | An ldr instruction takes 1-3 cycles, but does not block the | |
7870 | pipeline. | |
7871 | ||
7872 | NREGS CYCLES | |
7873 | 1 1-3 | |
7874 | 2 2-6 | |
7875 | 3 3-9 | |
7876 | 4 4-12 | |
7877 | ||
7878 | Best case ldr will always win. However, the more ldr instructions | |
7879 | we issue, the less likely we are to be able to schedule them well. | |
7880 | Using ldr instructions also increases code size. | |
7881 | ||
7882 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
7883 | for counts of 3 or 4 regs. */ | |
4b3c2e48 | 7884 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
7885 | { |
7886 | rtx seq; | |
f676971a | 7887 | |
d19fb8e3 | 7888 | start_sequence (); |
f676971a | 7889 | |
d19fb8e3 NC |
7890 | for (i = 0; i < count; i++) |
7891 | { | |
50ed9cea RH |
7892 | addr = plus_constant (from, i * 4 * sign); |
7893 | mem = adjust_automodify_address (basemem, SImode, addr, offset); | |
d19fb8e3 | 7894 | emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); |
50ed9cea | 7895 | offset += 4 * sign; |
d19fb8e3 NC |
7896 | } |
7897 | ||
7898 | if (write_back) | |
50ed9cea RH |
7899 | { |
7900 | emit_move_insn (from, plus_constant (from, count * 4 * sign)); | |
7901 | *offsetp = offset; | |
7902 | } | |
d19fb8e3 | 7903 | |
2f937369 | 7904 | seq = get_insns (); |
d19fb8e3 | 7905 | end_sequence (); |
f676971a | 7906 | |
d19fb8e3 NC |
7907 | return seq; |
7908 | } | |
7909 | ||
43cffd11 | 7910 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 7911 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 7912 | if (write_back) |
f3bb6135 | 7913 | { |
ff9940b0 | 7914 | XVECEXP (result, 0, 0) |
d66437c5 | 7915 | = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign)); |
ff9940b0 RE |
7916 | i = 1; |
7917 | count++; | |
f3bb6135 RE |
7918 | } |
7919 | ||
ff9940b0 | 7920 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 7921 | { |
50ed9cea RH |
7922 | addr = plus_constant (from, j * 4 * sign); |
7923 | mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
43cffd11 RE |
7924 | XVECEXP (result, 0, i) |
7925 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | |
50ed9cea | 7926 | offset += 4 * sign; |
f3bb6135 RE |
7927 | } |
7928 | ||
50ed9cea RH |
7929 | if (write_back) |
7930 | *offsetp = offset; | |
7931 | ||
ff9940b0 RE |
7932 | return result; |
7933 | } | |
7934 | ||
f3bb6135 | 7935 | rtx |
e32bac5b | 7936 | arm_gen_store_multiple (int base_regno, int count, rtx to, int up, |
50ed9cea | 7937 | int write_back, rtx basemem, HOST_WIDE_INT *offsetp) |
ff9940b0 | 7938 | { |
50ed9cea | 7939 | HOST_WIDE_INT offset = *offsetp; |
ff9940b0 RE |
7940 | int i = 0, j; |
7941 | rtx result; | |
7942 | int sign = up ? 1 : -1; | |
50ed9cea | 7943 | rtx mem, addr; |
ff9940b0 | 7944 | |
d19fb8e3 NC |
7945 | /* See arm_gen_load_multiple for discussion of |
7946 | the pros/cons of ldm/stm usage for XScale. */ | |
4b3c2e48 | 7947 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
7948 | { |
7949 | rtx seq; | |
f676971a | 7950 | |
d19fb8e3 | 7951 | start_sequence (); |
f676971a | 7952 | |
d19fb8e3 NC |
7953 | for (i = 0; i < count; i++) |
7954 | { | |
50ed9cea RH |
7955 | addr = plus_constant (to, i * 4 * sign); |
7956 | mem = adjust_automodify_address (basemem, SImode, addr, offset); | |
d19fb8e3 | 7957 | emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); |
50ed9cea | 7958 | offset += 4 * sign; |
d19fb8e3 NC |
7959 | } |
7960 | ||
7961 | if (write_back) | |
50ed9cea RH |
7962 | { |
7963 | emit_move_insn (to, plus_constant (to, count * 4 * sign)); | |
7964 | *offsetp = offset; | |
7965 | } | |
d19fb8e3 | 7966 | |
2f937369 | 7967 | seq = get_insns (); |
d19fb8e3 | 7968 | end_sequence (); |
f676971a | 7969 | |
d19fb8e3 NC |
7970 | return seq; |
7971 | } | |
7972 | ||
43cffd11 | 7973 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 7974 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 7975 | if (write_back) |
f3bb6135 | 7976 | { |
ff9940b0 | 7977 | XVECEXP (result, 0, 0) |
d66437c5 | 7978 | = gen_rtx_SET (VOIDmode, to, |
43cffd11 | 7979 | plus_constant (to, count * 4 * sign)); |
ff9940b0 RE |
7980 | i = 1; |
7981 | count++; | |
f3bb6135 RE |
7982 | } |
7983 | ||
ff9940b0 | 7984 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 7985 | { |
50ed9cea RH |
7986 | addr = plus_constant (to, j * 4 * sign); |
7987 | mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
43cffd11 RE |
7988 | XVECEXP (result, 0, i) |
7989 | = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | |
50ed9cea | 7990 | offset += 4 * sign; |
f3bb6135 RE |
7991 | } |
7992 | ||
50ed9cea RH |
7993 | if (write_back) |
7994 | *offsetp = offset; | |
7995 | ||
ff9940b0 RE |
7996 | return result; |
7997 | } | |
7998 | ||
880e2516 | 7999 | int |
70128ad9 | 8000 | arm_gen_movmemqi (rtx *operands) |
880e2516 RE |
8001 | { |
8002 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
50ed9cea | 8003 | HOST_WIDE_INT srcoffset, dstoffset; |
ad076f4e | 8004 | int i; |
50ed9cea | 8005 | rtx src, dst, srcbase, dstbase; |
880e2516 | 8006 | rtx part_bytes_reg = NULL; |
56636818 | 8007 | rtx mem; |
880e2516 RE |
8008 | |
8009 | if (GET_CODE (operands[2]) != CONST_INT | |
8010 | || GET_CODE (operands[3]) != CONST_INT | |
8011 | || INTVAL (operands[2]) > 64 | |
8012 | || INTVAL (operands[3]) & 3) | |
8013 | return 0; | |
8014 | ||
50ed9cea RH |
8015 | dstbase = operands[0]; |
8016 | srcbase = operands[1]; | |
56636818 | 8017 | |
50ed9cea RH |
8018 | dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0)); |
8019 | src = copy_to_mode_reg (SImode, XEXP (srcbase, 0)); | |
880e2516 | 8020 | |
e9d7b180 | 8021 | in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
8022 | out_words_to_go = INTVAL (operands[2]) / 4; |
8023 | last_bytes = INTVAL (operands[2]) & 3; | |
50ed9cea | 8024 | dstoffset = srcoffset = 0; |
880e2516 RE |
8025 | |
8026 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 8027 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
8028 | |
8029 | for (i = 0; in_words_to_go >= 2; i+=4) | |
8030 | { | |
bd9c7e23 | 8031 | if (in_words_to_go > 4) |
56636818 | 8032 | emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, |
50ed9cea | 8033 | srcbase, &srcoffset)); |
bd9c7e23 | 8034 | else |
f676971a | 8035 | emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, |
50ed9cea | 8036 | FALSE, srcbase, &srcoffset)); |
bd9c7e23 | 8037 | |
880e2516 RE |
8038 | if (out_words_to_go) |
8039 | { | |
bd9c7e23 | 8040 | if (out_words_to_go > 4) |
56636818 | 8041 | emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, |
50ed9cea | 8042 | dstbase, &dstoffset)); |
bd9c7e23 RE |
8043 | else if (out_words_to_go != 1) |
8044 | emit_insn (arm_gen_store_multiple (0, out_words_to_go, | |
f676971a | 8045 | dst, TRUE, |
bd9c7e23 | 8046 | (last_bytes == 0 |
56636818 | 8047 | ? FALSE : TRUE), |
50ed9cea | 8048 | dstbase, &dstoffset)); |
880e2516 RE |
8049 | else |
8050 | { | |
50ed9cea | 8051 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); |
43cffd11 | 8052 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 | 8053 | if (last_bytes != 0) |
50ed9cea RH |
8054 | { |
8055 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
8056 | dstoffset += 4; | |
8057 | } | |
880e2516 RE |
8058 | } |
8059 | } | |
8060 | ||
8061 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
8062 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
8063 | } | |
8064 | ||
8065 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
8066 | if (out_words_to_go) | |
62b10bbc NC |
8067 | { |
8068 | rtx sreg; | |
f676971a | 8069 | |
50ed9cea RH |
8070 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
8071 | sreg = copy_to_reg (mem); | |
8072 | ||
8073 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); | |
62b10bbc | 8074 | emit_move_insn (mem, sreg); |
62b10bbc | 8075 | in_words_to_go--; |
f676971a | 8076 | |
e6d29d15 | 8077 | gcc_assert (!in_words_to_go); /* Sanity check */ |
62b10bbc | 8078 | } |
880e2516 RE |
8079 | |
8080 | if (in_words_to_go) | |
8081 | { | |
e6d29d15 | 8082 | gcc_assert (in_words_to_go > 0); |
880e2516 | 8083 | |
50ed9cea | 8084 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
56636818 | 8085 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
8086 | } |
8087 | ||
e6d29d15 | 8088 | gcc_assert (!last_bytes || part_bytes_reg); |
d5b7b3ae | 8089 | |
880e2516 RE |
8090 | if (BYTES_BIG_ENDIAN && last_bytes) |
8091 | { | |
8092 | rtx tmp = gen_reg_rtx (SImode); | |
8093 | ||
6354dc9b | 8094 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
8095 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
8096 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 | 8097 | part_bytes_reg = tmp; |
f676971a | 8098 | |
880e2516 RE |
8099 | while (last_bytes) |
8100 | { | |
50ed9cea RH |
8101 | mem = adjust_automodify_address (dstbase, QImode, |
8102 | plus_constant (dst, last_bytes - 1), | |
8103 | dstoffset + last_bytes - 1); | |
5d5603e2 BS |
8104 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
8105 | ||
880e2516 RE |
8106 | if (--last_bytes) |
8107 | { | |
8108 | tmp = gen_reg_rtx (SImode); | |
8109 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
8110 | part_bytes_reg = tmp; | |
8111 | } | |
8112 | } | |
f676971a | 8113 | |
880e2516 RE |
8114 | } |
8115 | else | |
8116 | { | |
d5b7b3ae | 8117 | if (last_bytes > 1) |
880e2516 | 8118 | { |
50ed9cea | 8119 | mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset); |
5d5603e2 | 8120 | emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); |
d5b7b3ae RE |
8121 | last_bytes -= 2; |
8122 | if (last_bytes) | |
880e2516 RE |
8123 | { |
8124 | rtx tmp = gen_reg_rtx (SImode); | |
a556fd39 | 8125 | emit_insn (gen_addsi3 (dst, dst, const2_rtx)); |
d5b7b3ae | 8126 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); |
880e2516 | 8127 | part_bytes_reg = tmp; |
50ed9cea | 8128 | dstoffset += 2; |
880e2516 RE |
8129 | } |
8130 | } | |
f676971a | 8131 | |
d5b7b3ae RE |
8132 | if (last_bytes) |
8133 | { | |
50ed9cea | 8134 | mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset); |
5d5603e2 | 8135 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
d5b7b3ae | 8136 | } |
880e2516 RE |
8137 | } |
8138 | ||
8139 | return 1; | |
8140 | } | |
8141 | ||
03f1640c RE |
8142 | /* Select a dominance comparison mode if possible for a test of the general |
8143 | form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. | |
f676971a | 8144 | COND_OR == DOM_CC_X_AND_Y => (X && Y) |
03f1640c | 8145 | COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) |
f676971a | 8146 | COND_OR == DOM_CC_X_OR_Y => (X || Y) |
03f1640c | 8147 | In all cases OP will be either EQ or NE, but we don't need to know which |
f676971a | 8148 | here. If we are unable to support a dominance comparison we return |
03f1640c RE |
8149 | CC mode. This will then fail to match for the RTL expressions that |
8150 | generate this call. */ | |
03f1640c | 8151 | enum machine_mode |
e32bac5b | 8152 | arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) |
84ed5e79 RE |
8153 | { |
8154 | enum rtx_code cond1, cond2; | |
8155 | int swapped = 0; | |
8156 | ||
8157 | /* Currently we will probably get the wrong result if the individual | |
8158 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 8159 | reverse a comparison if necessary. */ |
84ed5e79 RE |
8160 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
8161 | != CCmode) | |
8162 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
8163 | != CCmode)) | |
8164 | return CCmode; | |
8165 | ||
1646cf41 RE |
8166 | /* The if_then_else variant of this tests the second condition if the |
8167 | first passes, but is true if the first fails. Reverse the first | |
8168 | condition to get a true "inclusive-or" expression. */ | |
03f1640c | 8169 | if (cond_or == DOM_CC_NX_OR_Y) |
84ed5e79 RE |
8170 | cond1 = reverse_condition (cond1); |
8171 | ||
8172 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
8173 | then we can't do this. */ | |
f676971a | 8174 | if (cond1 != cond2 |
5895f793 RE |
8175 | && !comparison_dominates_p (cond1, cond2) |
8176 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
8177 | return CCmode; |
8178 | ||
8179 | if (swapped) | |
8180 | { | |
8181 | enum rtx_code temp = cond1; | |
8182 | cond1 = cond2; | |
8183 | cond2 = temp; | |
8184 | } | |
8185 | ||
8186 | switch (cond1) | |
8187 | { | |
8188 | case EQ: | |
e6d29d15 | 8189 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
8190 | return CC_DEQmode; |
8191 | ||
8192 | switch (cond2) | |
8193 | { | |
e6d29d15 | 8194 | case EQ: return CC_DEQmode; |
84ed5e79 RE |
8195 | case LE: return CC_DLEmode; |
8196 | case LEU: return CC_DLEUmode; | |
8197 | case GE: return CC_DGEmode; | |
8198 | case GEU: return CC_DGEUmode; | |
e6d29d15 | 8199 | default: gcc_unreachable (); |
84ed5e79 RE |
8200 | } |
8201 | ||
84ed5e79 | 8202 | case LT: |
e6d29d15 | 8203 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 8204 | return CC_DLTmode; |
e0b92319 | 8205 | |
e6d29d15 NS |
8206 | switch (cond2) |
8207 | { | |
8208 | case LT: | |
8209 | return CC_DLTmode; | |
8210 | case LE: | |
8211 | return CC_DLEmode; | |
8212 | case NE: | |
8213 | return CC_DNEmode; | |
8214 | default: | |
8215 | gcc_unreachable (); | |
8216 | } | |
84ed5e79 RE |
8217 | |
8218 | case GT: | |
e6d29d15 | 8219 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 8220 | return CC_DGTmode; |
e6d29d15 NS |
8221 | |
8222 | switch (cond2) | |
8223 | { | |
8224 | case GT: | |
8225 | return CC_DGTmode; | |
8226 | case GE: | |
8227 | return CC_DGEmode; | |
8228 | case NE: | |
8229 | return CC_DNEmode; | |
8230 | default: | |
8231 | gcc_unreachable (); | |
8232 | } | |
f676971a | 8233 | |
84ed5e79 | 8234 | case LTU: |
e6d29d15 | 8235 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 8236 | return CC_DLTUmode; |
e6d29d15 NS |
8237 | |
8238 | switch (cond2) | |
8239 | { | |
8240 | case LTU: | |
8241 | return CC_DLTUmode; | |
8242 | case LEU: | |
8243 | return CC_DLEUmode; | |
8244 | case NE: | |
8245 | return CC_DNEmode; | |
8246 | default: | |
8247 | gcc_unreachable (); | |
8248 | } | |
84ed5e79 RE |
8249 | |
8250 | case GTU: | |
e6d29d15 | 8251 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 8252 | return CC_DGTUmode; |
e0b92319 | 8253 | |
e6d29d15 NS |
8254 | switch (cond2) |
8255 | { | |
8256 | case GTU: | |
8257 | return CC_DGTUmode; | |
8258 | case GEU: | |
8259 | return CC_DGEUmode; | |
8260 | case NE: | |
8261 | return CC_DNEmode; | |
8262 | default: | |
8263 | gcc_unreachable (); | |
8264 | } | |
84ed5e79 RE |
8265 | |
8266 | /* The remaining cases only occur when both comparisons are the | |
8267 | same. */ | |
8268 | case NE: | |
e6d29d15 | 8269 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
8270 | return CC_DNEmode; |
8271 | ||
8272 | case LE: | |
e6d29d15 | 8273 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
8274 | return CC_DLEmode; |
8275 | ||
8276 | case GE: | |
e6d29d15 | 8277 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
8278 | return CC_DGEmode; |
8279 | ||
8280 | case LEU: | |
e6d29d15 | 8281 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
8282 | return CC_DLEUmode; |
8283 | ||
8284 | case GEU: | |
e6d29d15 | 8285 | gcc_assert (cond1 == cond2); |
84ed5e79 | 8286 | return CC_DGEUmode; |
ad076f4e RE |
8287 | |
8288 | default: | |
e6d29d15 | 8289 | gcc_unreachable (); |
84ed5e79 | 8290 | } |
84ed5e79 RE |
8291 | } |
8292 | ||
8293 | enum machine_mode | |
e32bac5b | 8294 | arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) |
84ed5e79 RE |
8295 | { |
8296 | /* All floating point compares return CCFP if it is an equality | |
8297 | comparison, and CCFPE otherwise. */ | |
8298 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
8299 | { |
8300 | switch (op) | |
8301 | { | |
8302 | case EQ: | |
8303 | case NE: | |
8304 | case UNORDERED: | |
8305 | case ORDERED: | |
8306 | case UNLT: | |
8307 | case UNLE: | |
8308 | case UNGT: | |
8309 | case UNGE: | |
8310 | case UNEQ: | |
8311 | case LTGT: | |
8312 | return CCFPmode; | |
8313 | ||
8314 | case LT: | |
8315 | case LE: | |
8316 | case GT: | |
8317 | case GE: | |
9b66ebb1 | 8318 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK) |
9b6b54e2 | 8319 | return CCFPmode; |
e45b72c4 RE |
8320 | return CCFPEmode; |
8321 | ||
8322 | default: | |
e6d29d15 | 8323 | gcc_unreachable (); |
e45b72c4 RE |
8324 | } |
8325 | } | |
f676971a | 8326 | |
84ed5e79 RE |
8327 | /* A compare with a shifted operand. Because of canonicalization, the |
8328 | comparison will have to be swapped when we emit the assembler. */ | |
8329 | if (GET_MODE (y) == SImode && GET_CODE (y) == REG | |
8330 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
8331 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
8332 | || GET_CODE (x) == ROTATERT)) | |
8333 | return CC_SWPmode; | |
8334 | ||
04d8b819 RE |
8335 | /* This operation is performed swapped, but since we only rely on the Z |
8336 | flag we don't need an additional mode. */ | |
8337 | if (GET_MODE (y) == SImode && REG_P (y) | |
8338 | && GET_CODE (x) == NEG | |
8339 | && (op == EQ || op == NE)) | |
8340 | return CC_Zmode; | |
8341 | ||
f676971a | 8342 | /* This is a special case that is used by combine to allow a |
956d6950 | 8343 | comparison of a shifted byte load to be split into a zero-extend |
84ed5e79 | 8344 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 8345 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
8346 | if (GET_MODE (x) == SImode |
8347 | && GET_CODE (x) == ASHIFT | |
8348 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
8349 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
8350 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
8351 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
8352 | && (op == EQ || op == NE | |
8353 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
8354 | && GET_CODE (y) == CONST_INT) | |
8355 | return CC_Zmode; | |
8356 | ||
1646cf41 RE |
8357 | /* A construct for a conditional compare, if the false arm contains |
8358 | 0, then both conditions must be true, otherwise either condition | |
8359 | must be true. Not all conditions are possible, so CCmode is | |
8360 | returned if it can't be done. */ | |
8361 | if (GET_CODE (x) == IF_THEN_ELSE | |
8362 | && (XEXP (x, 2) == const0_rtx | |
8363 | || XEXP (x, 2) == const1_rtx) | |
ec8e098d PB |
8364 | && COMPARISON_P (XEXP (x, 0)) |
8365 | && COMPARISON_P (XEXP (x, 1))) | |
f676971a | 8366 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
03f1640c | 8367 | INTVAL (XEXP (x, 2))); |
1646cf41 RE |
8368 | |
8369 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
8370 | if (GET_CODE (x) == AND | |
ec8e098d PB |
8371 | && COMPARISON_P (XEXP (x, 0)) |
8372 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
8373 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
8374 | DOM_CC_X_AND_Y); | |
1646cf41 RE |
8375 | |
8376 | if (GET_CODE (x) == IOR | |
ec8e098d PB |
8377 | && COMPARISON_P (XEXP (x, 0)) |
8378 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
8379 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
8380 | DOM_CC_X_OR_Y); | |
1646cf41 | 8381 | |
defc0463 RE |
8382 | /* An operation (on Thumb) where we want to test for a single bit. |
8383 | This is done by shifting that bit up into the top bit of a | |
8384 | scratch register; we can then branch on the sign bit. */ | |
5b3e6663 | 8385 | if (TARGET_THUMB1 |
defc0463 RE |
8386 | && GET_MODE (x) == SImode |
8387 | && (op == EQ || op == NE) | |
f9fa4363 RE |
8388 | && GET_CODE (x) == ZERO_EXTRACT |
8389 | && XEXP (x, 1) == const1_rtx) | |
defc0463 RE |
8390 | return CC_Nmode; |
8391 | ||
84ed5e79 RE |
8392 | /* An operation that sets the condition codes as a side-effect, the |
8393 | V flag is not set correctly, so we can only use comparisons where | |
8394 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
defc0463 | 8395 | instead.) */ |
5b3e6663 | 8396 | /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */ |
84ed5e79 RE |
8397 | if (GET_MODE (x) == SImode |
8398 | && y == const0_rtx | |
8399 | && (op == EQ || op == NE || op == LT || op == GE) | |
8400 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
8401 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
8402 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
8403 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
8404 | || GET_CODE (x) == LSHIFTRT | |
8405 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
defc0463 | 8406 | || GET_CODE (x) == ROTATERT |
5b3e6663 | 8407 | || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT))) |
84ed5e79 RE |
8408 | return CC_NOOVmode; |
8409 | ||
84ed5e79 RE |
8410 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
8411 | return CC_Zmode; | |
8412 | ||
bd9c7e23 RE |
8413 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
8414 | && GET_CODE (x) == PLUS | |
8415 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
8416 | return CC_Cmode; | |
8417 | ||
84ed5e79 RE |
8418 | return CCmode; |
8419 | } | |
8420 | ||
ff9940b0 RE |
8421 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
8422 | return the rtx for register 0 in the proper mode. FP means this is a | |
8423 | floating point compare: I don't think that it is needed on the arm. */ | |
ff9940b0 | 8424 | rtx |
e32bac5b | 8425 | arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
ff9940b0 RE |
8426 | { |
8427 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); | |
d5b7b3ae | 8428 | rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); |
ff9940b0 | 8429 | |
d66437c5 | 8430 | emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); |
ff9940b0 RE |
8431 | |
8432 | return cc_reg; | |
8433 | } | |
8434 | ||
fcd53748 JT |
8435 | /* Generate a sequence of insns that will generate the correct return |
8436 | address mask depending on the physical architecture that the program | |
8437 | is running on. */ | |
fcd53748 | 8438 | rtx |
e32bac5b | 8439 | arm_gen_return_addr_mask (void) |
fcd53748 JT |
8440 | { |
8441 | rtx reg = gen_reg_rtx (Pmode); | |
8442 | ||
8443 | emit_insn (gen_return_addr_mask (reg)); | |
8444 | return reg; | |
8445 | } | |
8446 | ||
0a81f500 | 8447 | void |
e32bac5b | 8448 | arm_reload_in_hi (rtx *operands) |
0a81f500 | 8449 | { |
f9cc092a RE |
8450 | rtx ref = operands[1]; |
8451 | rtx base, scratch; | |
8452 | HOST_WIDE_INT offset = 0; | |
8453 | ||
8454 | if (GET_CODE (ref) == SUBREG) | |
8455 | { | |
ddef6bc7 | 8456 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
8457 | ref = SUBREG_REG (ref); |
8458 | } | |
8459 | ||
8460 | if (GET_CODE (ref) == REG) | |
8461 | { | |
8462 | /* We have a pseudo which has been spilt onto the stack; there | |
8463 | are two cases here: the first where there is a simple | |
8464 | stack-slot replacement and a second where the stack-slot is | |
8465 | out of range, or is used as a subreg. */ | |
8466 | if (reg_equiv_mem[REGNO (ref)]) | |
8467 | { | |
8468 | ref = reg_equiv_mem[REGNO (ref)]; | |
8469 | base = find_replacement (&XEXP (ref, 0)); | |
8470 | } | |
8471 | else | |
6354dc9b | 8472 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
8473 | base = reg_equiv_address[REGNO (ref)]; |
8474 | } | |
8475 | else | |
8476 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 8477 | |
e5e809f4 JL |
8478 | /* Handle the case where the address is too complex to be offset by 1. */ |
8479 | if (GET_CODE (base) == MINUS | |
8480 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
8481 | { | |
f9cc092a | 8482 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 8483 | |
d66437c5 | 8484 | emit_set_insn (base_plus, base); |
e5e809f4 JL |
8485 | base = base_plus; |
8486 | } | |
f9cc092a RE |
8487 | else if (GET_CODE (base) == PLUS) |
8488 | { | |
6354dc9b | 8489 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
8490 | HOST_WIDE_INT hi, lo; |
8491 | ||
8492 | offset += INTVAL (XEXP (base, 1)); | |
8493 | base = XEXP (base, 0); | |
8494 | ||
6354dc9b | 8495 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
8496 | /* Valid range for lo is -4095 -> 4095 */ |
8497 | lo = (offset >= 0 | |
8498 | ? (offset & 0xfff) | |
8499 | : -((-offset) & 0xfff)); | |
8500 | ||
8501 | /* Corner case, if lo is the max offset then we would be out of range | |
8502 | once we have added the additional 1 below, so bump the msb into the | |
8503 | pre-loading insn(s). */ | |
8504 | if (lo == 4095) | |
8505 | lo &= 0x7ff; | |
8506 | ||
30cf4896 KG |
8507 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
8508 | ^ (HOST_WIDE_INT) 0x80000000) | |
8509 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 8510 | |
e6d29d15 | 8511 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
8512 | |
8513 | if (hi != 0) | |
8514 | { | |
8515 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8516 | ||
8517 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 8518 | that require more than one insn. */ |
f9cc092a RE |
8519 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
8520 | base = base_plus; | |
8521 | offset = lo; | |
8522 | } | |
8523 | } | |
e5e809f4 | 8524 | |
3a1944a6 RE |
8525 | /* Operands[2] may overlap operands[0] (though it won't overlap |
8526 | operands[1]), that's why we asked for a DImode reg -- so we can | |
8527 | use the bit that does not overlap. */ | |
8528 | if (REGNO (operands[2]) == REGNO (operands[0])) | |
8529 | scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8530 | else | |
8531 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
8532 | ||
f9cc092a RE |
8533 | emit_insn (gen_zero_extendqisi2 (scratch, |
8534 | gen_rtx_MEM (QImode, | |
8535 | plus_constant (base, | |
8536 | offset)))); | |
43cffd11 | 8537 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
f676971a | 8538 | gen_rtx_MEM (QImode, |
f9cc092a RE |
8539 | plus_constant (base, |
8540 | offset + 1)))); | |
5895f793 | 8541 | if (!BYTES_BIG_ENDIAN) |
d66437c5 RE |
8542 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
8543 | gen_rtx_IOR (SImode, | |
8544 | gen_rtx_ASHIFT | |
8545 | (SImode, | |
8546 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
8547 | GEN_INT (8)), | |
8548 | scratch)); | |
0a81f500 | 8549 | else |
d66437c5 RE |
8550 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
8551 | gen_rtx_IOR (SImode, | |
8552 | gen_rtx_ASHIFT (SImode, scratch, | |
8553 | GEN_INT (8)), | |
8554 | gen_rtx_SUBREG (SImode, operands[0], 0))); | |
0a81f500 RE |
8555 | } |
8556 | ||
72ac76be | 8557 | /* Handle storing a half-word to memory during reload by synthesizing as two |
f9cc092a RE |
8558 | byte stores. Take care not to clobber the input values until after we |
8559 | have moved them somewhere safe. This code assumes that if the DImode | |
8560 | scratch in operands[2] overlaps either the input value or output address | |
8561 | in some way, then that value must die in this insn (we absolutely need | |
8562 | two scratch registers for some corner cases). */ | |
f3bb6135 | 8563 | void |
e32bac5b | 8564 | arm_reload_out_hi (rtx *operands) |
af48348a | 8565 | { |
f9cc092a RE |
8566 | rtx ref = operands[0]; |
8567 | rtx outval = operands[1]; | |
8568 | rtx base, scratch; | |
8569 | HOST_WIDE_INT offset = 0; | |
8570 | ||
8571 | if (GET_CODE (ref) == SUBREG) | |
8572 | { | |
ddef6bc7 | 8573 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
8574 | ref = SUBREG_REG (ref); |
8575 | } | |
8576 | ||
f9cc092a RE |
8577 | if (GET_CODE (ref) == REG) |
8578 | { | |
8579 | /* We have a pseudo which has been spilt onto the stack; there | |
8580 | are two cases here: the first where there is a simple | |
8581 | stack-slot replacement and a second where the stack-slot is | |
8582 | out of range, or is used as a subreg. */ | |
8583 | if (reg_equiv_mem[REGNO (ref)]) | |
8584 | { | |
8585 | ref = reg_equiv_mem[REGNO (ref)]; | |
8586 | base = find_replacement (&XEXP (ref, 0)); | |
8587 | } | |
8588 | else | |
6354dc9b | 8589 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
8590 | base = reg_equiv_address[REGNO (ref)]; |
8591 | } | |
8592 | else | |
8593 | base = find_replacement (&XEXP (ref, 0)); | |
8594 | ||
8595 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
8596 | ||
8597 | /* Handle the case where the address is too complex to be offset by 1. */ | |
8598 | if (GET_CODE (base) == MINUS | |
8599 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
8600 | { | |
8601 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8602 | ||
8603 | /* Be careful not to destroy OUTVAL. */ | |
8604 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
8605 | { | |
8606 | /* Updating base_plus might destroy outval, see if we can | |
8607 | swap the scratch and base_plus. */ | |
5895f793 | 8608 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
8609 | { |
8610 | rtx tmp = scratch; | |
8611 | scratch = base_plus; | |
8612 | base_plus = tmp; | |
8613 | } | |
8614 | else | |
8615 | { | |
8616 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
8617 | ||
8618 | /* Be conservative and copy OUTVAL into the scratch now, | |
8619 | this should only be necessary if outval is a subreg | |
8620 | of something larger than a word. */ | |
8621 | /* XXX Might this clobber base? I can't see how it can, | |
8622 | since scratch is known to overlap with OUTVAL, and | |
8623 | must be wider than a word. */ | |
8624 | emit_insn (gen_movhi (scratch_hi, outval)); | |
8625 | outval = scratch_hi; | |
8626 | } | |
8627 | } | |
8628 | ||
d66437c5 | 8629 | emit_set_insn (base_plus, base); |
f9cc092a RE |
8630 | base = base_plus; |
8631 | } | |
8632 | else if (GET_CODE (base) == PLUS) | |
8633 | { | |
6354dc9b | 8634 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
8635 | HOST_WIDE_INT hi, lo; |
8636 | ||
8637 | offset += INTVAL (XEXP (base, 1)); | |
8638 | base = XEXP (base, 0); | |
8639 | ||
6354dc9b | 8640 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
8641 | /* Valid range for lo is -4095 -> 4095 */ |
8642 | lo = (offset >= 0 | |
8643 | ? (offset & 0xfff) | |
8644 | : -((-offset) & 0xfff)); | |
8645 | ||
8646 | /* Corner case, if lo is the max offset then we would be out of range | |
8647 | once we have added the additional 1 below, so bump the msb into the | |
8648 | pre-loading insn(s). */ | |
8649 | if (lo == 4095) | |
8650 | lo &= 0x7ff; | |
8651 | ||
30cf4896 KG |
8652 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
8653 | ^ (HOST_WIDE_INT) 0x80000000) | |
8654 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 8655 | |
e6d29d15 | 8656 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
8657 | |
8658 | if (hi != 0) | |
8659 | { | |
8660 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8661 | ||
8662 | /* Be careful not to destroy OUTVAL. */ | |
8663 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
8664 | { | |
8665 | /* Updating base_plus might destroy outval, see if we | |
8666 | can swap the scratch and base_plus. */ | |
5895f793 | 8667 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
8668 | { |
8669 | rtx tmp = scratch; | |
8670 | scratch = base_plus; | |
8671 | base_plus = tmp; | |
8672 | } | |
8673 | else | |
8674 | { | |
8675 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
8676 | ||
8677 | /* Be conservative and copy outval into scratch now, | |
8678 | this should only be necessary if outval is a | |
8679 | subreg of something larger than a word. */ | |
8680 | /* XXX Might this clobber base? I can't see how it | |
8681 | can, since scratch is known to overlap with | |
8682 | outval. */ | |
8683 | emit_insn (gen_movhi (scratch_hi, outval)); | |
8684 | outval = scratch_hi; | |
8685 | } | |
8686 | } | |
8687 | ||
8688 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 8689 | that require more than one insn. */ |
f9cc092a RE |
8690 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
8691 | base = base_plus; | |
8692 | offset = lo; | |
8693 | } | |
8694 | } | |
af48348a | 8695 | |
b5cc037f RE |
8696 | if (BYTES_BIG_ENDIAN) |
8697 | { | |
f676971a | 8698 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
f9cc092a | 8699 | plus_constant (base, offset + 1)), |
5d5603e2 | 8700 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
8701 | emit_insn (gen_lshrsi3 (scratch, |
8702 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 8703 | GEN_INT (8))); |
f9cc092a | 8704 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 8705 | gen_lowpart (QImode, scratch))); |
b5cc037f RE |
8706 | } |
8707 | else | |
8708 | { | |
f9cc092a | 8709 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 8710 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
8711 | emit_insn (gen_lshrsi3 (scratch, |
8712 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 8713 | GEN_INT (8))); |
f9cc092a RE |
8714 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
8715 | plus_constant (base, offset + 1)), | |
5d5603e2 | 8716 | gen_lowpart (QImode, scratch))); |
b5cc037f | 8717 | } |
af48348a | 8718 | } |
866af8a9 JB |
8719 | |
8720 | /* Return true if a type must be passed in memory. For AAPCS, small aggregates | |
8721 | (padded to the size of a word) should be passed in a register. */ | |
8722 | ||
8723 | static bool | |
586de218 | 8724 | arm_must_pass_in_stack (enum machine_mode mode, const_tree type) |
866af8a9 JB |
8725 | { |
8726 | if (TARGET_AAPCS_BASED) | |
8727 | return must_pass_in_stack_var_size (mode, type); | |
8728 | else | |
8729 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
8730 | } | |
8731 | ||
8732 | ||
8733 | /* For use by FUNCTION_ARG_PADDING (MODE, TYPE). | |
8734 | Return true if an argument passed on the stack should be padded upwards, | |
5a29b385 PB |
8735 | i.e. if the least-significant byte has useful data. |
8736 | For legacy APCS ABIs we use the default. For AAPCS based ABIs small | |
8737 | aggregate types are placed in the lowest memory address. */ | |
866af8a9 JB |
8738 | |
8739 | bool | |
586de218 | 8740 | arm_pad_arg_upward (enum machine_mode mode, const_tree type) |
866af8a9 JB |
8741 | { |
8742 | if (!TARGET_AAPCS_BASED) | |
5a29b385 | 8743 | return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward; |
866af8a9 JB |
8744 | |
8745 | if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type)) | |
8746 | return false; | |
8747 | ||
8748 | return true; | |
8749 | } | |
8750 | ||
8751 | ||
8752 | /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). | |
8753 | For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant | |
8754 | byte of the register has useful data, and return the opposite if the | |
8755 | most significant byte does. | |
8756 | For AAPCS, small aggregates and small complex types are always padded | |
8757 | upwards. */ | |
8758 | ||
8759 | bool | |
8760 | arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, | |
8761 | tree type, int first ATTRIBUTE_UNUSED) | |
8762 | { | |
8763 | if (TARGET_AAPCS_BASED | |
8764 | && BYTES_BIG_ENDIAN | |
8765 | && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE) | |
8766 | && int_size_in_bytes (type) <= 4) | |
8767 | return true; | |
8768 | ||
8769 | /* Otherwise, use default padding. */ | |
8770 | return !BYTES_BIG_ENDIAN; | |
8771 | } | |
8772 | ||
2b835d68 | 8773 | \f |
d5b7b3ae RE |
8774 | /* Print a symbolic form of X to the debug file, F. */ |
8775 | static void | |
e32bac5b | 8776 | arm_print_value (FILE *f, rtx x) |
d5b7b3ae RE |
8777 | { |
8778 | switch (GET_CODE (x)) | |
8779 | { | |
8780 | case CONST_INT: | |
8781 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
8782 | return; | |
8783 | ||
8784 | case CONST_DOUBLE: | |
8785 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
8786 | return; | |
8787 | ||
5a9335ef NC |
8788 | case CONST_VECTOR: |
8789 | { | |
8790 | int i; | |
8791 | ||
8792 | fprintf (f, "<"); | |
8793 | for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) | |
8794 | { | |
8795 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); | |
8796 | if (i < (CONST_VECTOR_NUNITS (x) - 1)) | |
8797 | fputc (',', f); | |
8798 | } | |
8799 | fprintf (f, ">"); | |
8800 | } | |
8801 | return; | |
8802 | ||
d5b7b3ae RE |
8803 | case CONST_STRING: |
8804 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
8805 | return; | |
8806 | ||
8807 | case SYMBOL_REF: | |
8808 | fprintf (f, "`%s'", XSTR (x, 0)); | |
8809 | return; | |
8810 | ||
8811 | case LABEL_REF: | |
8812 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
8813 | return; | |
8814 | ||
8815 | case CONST: | |
8816 | arm_print_value (f, XEXP (x, 0)); | |
8817 | return; | |
8818 | ||
8819 | case PLUS: | |
8820 | arm_print_value (f, XEXP (x, 0)); | |
8821 | fprintf (f, "+"); | |
8822 | arm_print_value (f, XEXP (x, 1)); | |
8823 | return; | |
8824 | ||
8825 | case PC: | |
8826 | fprintf (f, "pc"); | |
8827 | return; | |
8828 | ||
8829 | default: | |
8830 | fprintf (f, "????"); | |
8831 | return; | |
8832 | } | |
8833 | } | |
8834 | \f | |
2b835d68 | 8835 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 8836 | |
949d79eb RE |
8837 | /* Arm instructions cannot load a large constant directly into a |
8838 | register; they have to come from a pc relative load. The constant | |
8839 | must therefore be placed in the addressable range of the pc | |
8840 | relative load. Depending on the precise pc relative load | |
8841 | instruction the range is somewhere between 256 bytes and 4k. This | |
8842 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
8843 | generate code to branch around it. |
8844 | ||
949d79eb RE |
8845 | It is important to minimize this, since the branches will slow |
8846 | things down and make the code larger. | |
2b835d68 | 8847 | |
949d79eb RE |
8848 | Normally we can hide the table after an existing unconditional |
8849 | branch so that there is no interruption of the flow, but in the | |
8850 | worst case the code looks like this: | |
2b835d68 RE |
8851 | |
8852 | ldr rn, L1 | |
949d79eb | 8853 | ... |
2b835d68 RE |
8854 | b L2 |
8855 | align | |
8856 | L1: .long value | |
8857 | L2: | |
949d79eb | 8858 | ... |
2b835d68 | 8859 | |
2b835d68 | 8860 | ldr rn, L3 |
949d79eb | 8861 | ... |
2b835d68 RE |
8862 | b L4 |
8863 | align | |
2b835d68 RE |
8864 | L3: .long value |
8865 | L4: | |
949d79eb RE |
8866 | ... |
8867 | ||
8868 | We fix this by performing a scan after scheduling, which notices | |
8869 | which instructions need to have their operands fetched from the | |
8870 | constant table and builds the table. | |
8871 | ||
8872 | The algorithm starts by building a table of all the constants that | |
8873 | need fixing up and all the natural barriers in the function (places | |
8874 | where a constant table can be dropped without breaking the flow). | |
8875 | For each fixup we note how far the pc-relative replacement will be | |
8876 | able to reach and the offset of the instruction into the function. | |
8877 | ||
8878 | Having built the table we then group the fixes together to form | |
8879 | tables that are as large as possible (subject to addressing | |
8880 | constraints) and emit each table of constants after the last | |
8881 | barrier that is within range of all the instructions in the group. | |
8882 | If a group does not contain a barrier, then we forcibly create one | |
8883 | by inserting a jump instruction into the flow. Once the table has | |
8884 | been inserted, the insns are then modified to reference the | |
8885 | relevant entry in the pool. | |
8886 | ||
6354dc9b | 8887 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 8888 | |
d5b7b3ae | 8889 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
8890 | aligning the pools to the start of cache lines; this alignment |
8891 | would need to be taken into account when calculating addressability | |
6354dc9b | 8892 | of a pool. */ |
2b835d68 | 8893 | |
d5b7b3ae RE |
8894 | /* These typedefs are located at the start of this file, so that |
8895 | they can be used in the prototypes there. This comment is to | |
8896 | remind readers of that fact so that the following structures | |
8897 | can be understood more easily. | |
8898 | ||
8899 | typedef struct minipool_node Mnode; | |
8900 | typedef struct minipool_fixup Mfix; */ | |
8901 | ||
8902 | struct minipool_node | |
8903 | { | |
8904 | /* Doubly linked chain of entries. */ | |
8905 | Mnode * next; | |
8906 | Mnode * prev; | |
8907 | /* The maximum offset into the code that this entry can be placed. While | |
8908 | pushing fixes for forward references, all entries are sorted in order | |
8909 | of increasing max_address. */ | |
8910 | HOST_WIDE_INT max_address; | |
5519a4f9 | 8911 | /* Similarly for an entry inserted for a backwards ref. */ |
d5b7b3ae RE |
8912 | HOST_WIDE_INT min_address; |
8913 | /* The number of fixes referencing this entry. This can become zero | |
8914 | if we "unpush" an entry. In this case we ignore the entry when we | |
8915 | come to emit the code. */ | |
8916 | int refcount; | |
8917 | /* The offset from the start of the minipool. */ | |
8918 | HOST_WIDE_INT offset; | |
8919 | /* The value in table. */ | |
8920 | rtx value; | |
8921 | /* The mode of value. */ | |
8922 | enum machine_mode mode; | |
5a9335ef NC |
8923 | /* The size of the value. With iWMMXt enabled |
8924 | sizes > 4 also imply an alignment of 8-bytes. */ | |
d5b7b3ae RE |
8925 | int fix_size; |
8926 | }; | |
8927 | ||
8928 | struct minipool_fixup | |
2b835d68 | 8929 | { |
d5b7b3ae RE |
8930 | Mfix * next; |
8931 | rtx insn; | |
8932 | HOST_WIDE_INT address; | |
8933 | rtx * loc; | |
8934 | enum machine_mode mode; | |
8935 | int fix_size; | |
8936 | rtx value; | |
8937 | Mnode * minipool; | |
8938 | HOST_WIDE_INT forwards; | |
8939 | HOST_WIDE_INT backwards; | |
8940 | }; | |
2b835d68 | 8941 | |
d5b7b3ae RE |
8942 | /* Fixes less than a word need padding out to a word boundary. */ |
8943 | #define MINIPOOL_FIX_SIZE(mode) \ | |
8944 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 8945 | |
d5b7b3ae RE |
8946 | static Mnode * minipool_vector_head; |
8947 | static Mnode * minipool_vector_tail; | |
8948 | static rtx minipool_vector_label; | |
34a9f549 | 8949 | static int minipool_pad; |
332072db | 8950 | |
d5b7b3ae RE |
8951 | /* The linked list of all minipool fixes required for this function. */ |
8952 | Mfix * minipool_fix_head; | |
8953 | Mfix * minipool_fix_tail; | |
8954 | /* The fix entry for the current minipool, once it has been placed. */ | |
8955 | Mfix * minipool_barrier; | |
8956 | ||
8957 | /* Determines if INSN is the start of a jump table. Returns the end | |
8958 | of the TABLE or NULL_RTX. */ | |
8959 | static rtx | |
e32bac5b | 8960 | is_jump_table (rtx insn) |
2b835d68 | 8961 | { |
d5b7b3ae | 8962 | rtx table; |
f676971a | 8963 | |
d5b7b3ae RE |
8964 | if (GET_CODE (insn) == JUMP_INSN |
8965 | && JUMP_LABEL (insn) != NULL | |
8966 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
8967 | == next_real_insn (insn)) | |
8968 | && table != NULL | |
8969 | && GET_CODE (table) == JUMP_INSN | |
8970 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
8971 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
8972 | return table; | |
8973 | ||
8974 | return NULL_RTX; | |
2b835d68 RE |
8975 | } |
8976 | ||
657d9449 RE |
8977 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
8978 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
8979 | #endif | |
8980 | ||
d5b7b3ae | 8981 | static HOST_WIDE_INT |
e32bac5b | 8982 | get_jump_table_size (rtx insn) |
2b835d68 | 8983 | { |
657d9449 RE |
8984 | /* ADDR_VECs only take room if read-only data does into the text |
8985 | section. */ | |
d6b5193b | 8986 | if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section) |
657d9449 RE |
8987 | { |
8988 | rtx body = PATTERN (insn); | |
8989 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
5b3e6663 PB |
8990 | HOST_WIDE_INT size; |
8991 | HOST_WIDE_INT modesize; | |
2b835d68 | 8992 | |
5b3e6663 PB |
8993 | modesize = GET_MODE_SIZE (GET_MODE (body)); |
8994 | size = modesize * XVECLEN (body, elt); | |
8995 | switch (modesize) | |
8996 | { | |
8997 | case 1: | |
88512ba0 | 8998 | /* Round up size of TBB table to a halfword boundary. */ |
5b3e6663 PB |
8999 | size = (size + 1) & ~(HOST_WIDE_INT)1; |
9000 | break; | |
9001 | case 2: | |
7a085dce | 9002 | /* No padding necessary for TBH. */ |
5b3e6663 PB |
9003 | break; |
9004 | case 4: | |
9005 | /* Add two bytes for alignment on Thumb. */ | |
9006 | if (TARGET_THUMB) | |
9007 | size += 2; | |
9008 | break; | |
9009 | default: | |
9010 | gcc_unreachable (); | |
9011 | } | |
9012 | return size; | |
657d9449 RE |
9013 | } |
9014 | ||
9015 | return 0; | |
d5b7b3ae | 9016 | } |
2b835d68 | 9017 | |
d5b7b3ae RE |
9018 | /* Move a minipool fix MP from its current location to before MAX_MP. |
9019 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
093354e0 | 9020 | constraints may need updating. */ |
d5b7b3ae | 9021 | static Mnode * |
e32bac5b RE |
9022 | move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, |
9023 | HOST_WIDE_INT max_address) | |
d5b7b3ae | 9024 | { |
e6d29d15 NS |
9025 | /* The code below assumes these are different. */ |
9026 | gcc_assert (mp != max_mp); | |
d5b7b3ae RE |
9027 | |
9028 | if (max_mp == NULL) | |
9029 | { | |
9030 | if (max_address < mp->max_address) | |
9031 | mp->max_address = max_address; | |
9032 | } | |
9033 | else | |
2b835d68 | 9034 | { |
d5b7b3ae RE |
9035 | if (max_address > max_mp->max_address - mp->fix_size) |
9036 | mp->max_address = max_mp->max_address - mp->fix_size; | |
9037 | else | |
9038 | mp->max_address = max_address; | |
2b835d68 | 9039 | |
d5b7b3ae RE |
9040 | /* Unlink MP from its current position. Since max_mp is non-null, |
9041 | mp->prev must be non-null. */ | |
9042 | mp->prev->next = mp->next; | |
9043 | if (mp->next != NULL) | |
9044 | mp->next->prev = mp->prev; | |
9045 | else | |
9046 | minipool_vector_tail = mp->prev; | |
2b835d68 | 9047 | |
d5b7b3ae RE |
9048 | /* Re-insert it before MAX_MP. */ |
9049 | mp->next = max_mp; | |
9050 | mp->prev = max_mp->prev; | |
9051 | max_mp->prev = mp; | |
f676971a | 9052 | |
d5b7b3ae RE |
9053 | if (mp->prev != NULL) |
9054 | mp->prev->next = mp; | |
9055 | else | |
9056 | minipool_vector_head = mp; | |
9057 | } | |
2b835d68 | 9058 | |
d5b7b3ae RE |
9059 | /* Save the new entry. */ |
9060 | max_mp = mp; | |
9061 | ||
d6a7951f | 9062 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
9063 | required. */ |
9064 | while (mp->prev != NULL | |
9065 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
9066 | { | |
9067 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
9068 | mp = mp->prev; | |
2b835d68 RE |
9069 | } |
9070 | ||
d5b7b3ae | 9071 | return max_mp; |
2b835d68 RE |
9072 | } |
9073 | ||
d5b7b3ae RE |
9074 | /* Add a constant to the minipool for a forward reference. Returns the |
9075 | node added or NULL if the constant will not fit in this pool. */ | |
9076 | static Mnode * | |
e32bac5b | 9077 | add_minipool_forward_ref (Mfix *fix) |
d5b7b3ae RE |
9078 | { |
9079 | /* If set, max_mp is the first pool_entry that has a lower | |
9080 | constraint than the one we are trying to add. */ | |
9081 | Mnode * max_mp = NULL; | |
34a9f549 | 9082 | HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad; |
d5b7b3ae | 9083 | Mnode * mp; |
f676971a | 9084 | |
7a7017bc PB |
9085 | /* If the minipool starts before the end of FIX->INSN then this FIX |
9086 | can not be placed into the current pool. Furthermore, adding the | |
9087 | new constant pool entry may cause the pool to start FIX_SIZE bytes | |
9088 | earlier. */ | |
d5b7b3ae | 9089 | if (minipool_vector_head && |
7a7017bc PB |
9090 | (fix->address + get_attr_length (fix->insn) |
9091 | >= minipool_vector_head->max_address - fix->fix_size)) | |
d5b7b3ae | 9092 | return NULL; |
2b835d68 | 9093 | |
d5b7b3ae RE |
9094 | /* Scan the pool to see if a constant with the same value has |
9095 | already been added. While we are doing this, also note the | |
9096 | location where we must insert the constant if it doesn't already | |
9097 | exist. */ | |
9098 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
9099 | { | |
9100 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
9101 | && fix->mode == mp->mode | |
9102 | && (GET_CODE (fix->value) != CODE_LABEL | |
9103 | || (CODE_LABEL_NUMBER (fix->value) | |
9104 | == CODE_LABEL_NUMBER (mp->value))) | |
9105 | && rtx_equal_p (fix->value, mp->value)) | |
9106 | { | |
9107 | /* More than one fix references this entry. */ | |
9108 | mp->refcount++; | |
9109 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
9110 | } | |
9111 | ||
9112 | /* Note the insertion point if necessary. */ | |
9113 | if (max_mp == NULL | |
9114 | && mp->max_address > max_address) | |
9115 | max_mp = mp; | |
5a9335ef NC |
9116 | |
9117 | /* If we are inserting an 8-bytes aligned quantity and | |
9118 | we have not already found an insertion point, then | |
9119 | make sure that all such 8-byte aligned quantities are | |
9120 | placed at the start of the pool. */ | |
5848830f | 9121 | if (ARM_DOUBLEWORD_ALIGN |
5a9335ef | 9122 | && max_mp == NULL |
88f77cba JB |
9123 | && fix->fix_size >= 8 |
9124 | && mp->fix_size < 8) | |
5a9335ef NC |
9125 | { |
9126 | max_mp = mp; | |
9127 | max_address = mp->max_address; | |
9128 | } | |
d5b7b3ae RE |
9129 | } |
9130 | ||
9131 | /* The value is not currently in the minipool, so we need to create | |
9132 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
9133 | the end of the list since the placement is less constrained than | |
9134 | any existing entry. Otherwise, we insert the new fix before | |
6bc82793 | 9135 | MAX_MP and, if necessary, adjust the constraints on the other |
d5b7b3ae | 9136 | entries. */ |
5ed6ace5 | 9137 | mp = XNEW (Mnode); |
d5b7b3ae RE |
9138 | mp->fix_size = fix->fix_size; |
9139 | mp->mode = fix->mode; | |
9140 | mp->value = fix->value; | |
9141 | mp->refcount = 1; | |
9142 | /* Not yet required for a backwards ref. */ | |
9143 | mp->min_address = -65536; | |
9144 | ||
9145 | if (max_mp == NULL) | |
9146 | { | |
9147 | mp->max_address = max_address; | |
9148 | mp->next = NULL; | |
9149 | mp->prev = minipool_vector_tail; | |
9150 | ||
9151 | if (mp->prev == NULL) | |
9152 | { | |
9153 | minipool_vector_head = mp; | |
9154 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 9155 | } |
2b835d68 | 9156 | else |
d5b7b3ae | 9157 | mp->prev->next = mp; |
2b835d68 | 9158 | |
d5b7b3ae RE |
9159 | minipool_vector_tail = mp; |
9160 | } | |
9161 | else | |
9162 | { | |
9163 | if (max_address > max_mp->max_address - mp->fix_size) | |
9164 | mp->max_address = max_mp->max_address - mp->fix_size; | |
9165 | else | |
9166 | mp->max_address = max_address; | |
9167 | ||
9168 | mp->next = max_mp; | |
9169 | mp->prev = max_mp->prev; | |
9170 | max_mp->prev = mp; | |
9171 | if (mp->prev != NULL) | |
9172 | mp->prev->next = mp; | |
9173 | else | |
9174 | minipool_vector_head = mp; | |
9175 | } | |
9176 | ||
9177 | /* Save the new entry. */ | |
9178 | max_mp = mp; | |
9179 | ||
d6a7951f | 9180 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
9181 | required. */ |
9182 | while (mp->prev != NULL | |
9183 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
9184 | { | |
9185 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
9186 | mp = mp->prev; | |
2b835d68 RE |
9187 | } |
9188 | ||
d5b7b3ae RE |
9189 | return max_mp; |
9190 | } | |
9191 | ||
9192 | static Mnode * | |
e32bac5b RE |
9193 | move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, |
9194 | HOST_WIDE_INT min_address) | |
d5b7b3ae RE |
9195 | { |
9196 | HOST_WIDE_INT offset; | |
9197 | ||
e6d29d15 NS |
9198 | /* The code below assumes these are different. */ |
9199 | gcc_assert (mp != min_mp); | |
d5b7b3ae RE |
9200 | |
9201 | if (min_mp == NULL) | |
2b835d68 | 9202 | { |
d5b7b3ae RE |
9203 | if (min_address > mp->min_address) |
9204 | mp->min_address = min_address; | |
9205 | } | |
9206 | else | |
9207 | { | |
9208 | /* We will adjust this below if it is too loose. */ | |
9209 | mp->min_address = min_address; | |
9210 | ||
9211 | /* Unlink MP from its current position. Since min_mp is non-null, | |
9212 | mp->next must be non-null. */ | |
9213 | mp->next->prev = mp->prev; | |
9214 | if (mp->prev != NULL) | |
9215 | mp->prev->next = mp->next; | |
9216 | else | |
9217 | minipool_vector_head = mp->next; | |
9218 | ||
9219 | /* Reinsert it after MIN_MP. */ | |
9220 | mp->prev = min_mp; | |
9221 | mp->next = min_mp->next; | |
9222 | min_mp->next = mp; | |
9223 | if (mp->next != NULL) | |
9224 | mp->next->prev = mp; | |
2b835d68 | 9225 | else |
d5b7b3ae RE |
9226 | minipool_vector_tail = mp; |
9227 | } | |
9228 | ||
9229 | min_mp = mp; | |
9230 | ||
9231 | offset = 0; | |
9232 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
9233 | { | |
9234 | mp->offset = offset; | |
9235 | if (mp->refcount > 0) | |
9236 | offset += mp->fix_size; | |
9237 | ||
9238 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
9239 | mp->next->min_address = mp->min_address + mp->fix_size; | |
9240 | } | |
9241 | ||
9242 | return min_mp; | |
f676971a | 9243 | } |
d5b7b3ae RE |
9244 | |
9245 | /* Add a constant to the minipool for a backward reference. Returns the | |
f676971a | 9246 | node added or NULL if the constant will not fit in this pool. |
d5b7b3ae RE |
9247 | |
9248 | Note that the code for insertion for a backwards reference can be | |
9249 | somewhat confusing because the calculated offsets for each fix do | |
9250 | not take into account the size of the pool (which is still under | |
9251 | construction. */ | |
9252 | static Mnode * | |
e32bac5b | 9253 | add_minipool_backward_ref (Mfix *fix) |
d5b7b3ae RE |
9254 | { |
9255 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
9256 | than the one we are trying to add. */ | |
e32bac5b | 9257 | Mnode *min_mp = NULL; |
d5b7b3ae RE |
9258 | /* This can be negative, since it is only a constraint. */ |
9259 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
e32bac5b | 9260 | Mnode *mp; |
d5b7b3ae RE |
9261 | |
9262 | /* If we can't reach the current pool from this insn, or if we can't | |
9263 | insert this entry at the end of the pool without pushing other | |
9264 | fixes out of range, then we don't try. This ensures that we | |
9265 | can't fail later on. */ | |
9266 | if (min_address >= minipool_barrier->address | |
9267 | || (minipool_vector_tail->min_address + fix->fix_size | |
9268 | >= minipool_barrier->address)) | |
9269 | return NULL; | |
9270 | ||
9271 | /* Scan the pool to see if a constant with the same value has | |
9272 | already been added. While we are doing this, also note the | |
9273 | location where we must insert the constant if it doesn't already | |
9274 | exist. */ | |
9275 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
9276 | { | |
9277 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
9278 | && fix->mode == mp->mode | |
9279 | && (GET_CODE (fix->value) != CODE_LABEL | |
9280 | || (CODE_LABEL_NUMBER (fix->value) | |
9281 | == CODE_LABEL_NUMBER (mp->value))) | |
9282 | && rtx_equal_p (fix->value, mp->value) | |
9283 | /* Check that there is enough slack to move this entry to the | |
9284 | end of the table (this is conservative). */ | |
f676971a EC |
9285 | && (mp->max_address |
9286 | > (minipool_barrier->address | |
d5b7b3ae RE |
9287 | + minipool_vector_tail->offset |
9288 | + minipool_vector_tail->fix_size))) | |
9289 | { | |
9290 | mp->refcount++; | |
9291 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
9292 | } | |
9293 | ||
9294 | if (min_mp != NULL) | |
9295 | mp->min_address += fix->fix_size; | |
9296 | else | |
9297 | { | |
9298 | /* Note the insertion point if necessary. */ | |
9299 | if (mp->min_address < min_address) | |
5a9335ef NC |
9300 | { |
9301 | /* For now, we do not allow the insertion of 8-byte alignment | |
9302 | requiring nodes anywhere but at the start of the pool. */ | |
5848830f | 9303 | if (ARM_DOUBLEWORD_ALIGN |
88f77cba | 9304 | && fix->fix_size >= 8 && mp->fix_size < 8) |
5a9335ef NC |
9305 | return NULL; |
9306 | else | |
9307 | min_mp = mp; | |
9308 | } | |
d5b7b3ae RE |
9309 | else if (mp->max_address |
9310 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
9311 | { | |
9312 | /* Inserting before this entry would push the fix beyond | |
9313 | its maximum address (which can happen if we have | |
9314 | re-located a forwards fix); force the new fix to come | |
9315 | after it. */ | |
853ff9e2 JM |
9316 | if (ARM_DOUBLEWORD_ALIGN |
9317 | && fix->fix_size >= 8 && mp->fix_size < 8) | |
9318 | return NULL; | |
9319 | else | |
9320 | { | |
9321 | min_mp = mp; | |
9322 | min_address = mp->min_address + fix->fix_size; | |
9323 | } | |
d5b7b3ae | 9324 | } |
853ff9e2 JM |
9325 | /* Do not insert a non-8-byte aligned quantity before 8-byte |
9326 | aligned quantities. */ | |
5848830f | 9327 | else if (ARM_DOUBLEWORD_ALIGN |
853ff9e2 JM |
9328 | && fix->fix_size < 8 |
9329 | && mp->fix_size >= 8) | |
5a9335ef NC |
9330 | { |
9331 | min_mp = mp; | |
9332 | min_address = mp->min_address + fix->fix_size; | |
9333 | } | |
d5b7b3ae RE |
9334 | } |
9335 | } | |
9336 | ||
9337 | /* We need to create a new entry. */ | |
5ed6ace5 | 9338 | mp = XNEW (Mnode); |
d5b7b3ae RE |
9339 | mp->fix_size = fix->fix_size; |
9340 | mp->mode = fix->mode; | |
9341 | mp->value = fix->value; | |
9342 | mp->refcount = 1; | |
9343 | mp->max_address = minipool_barrier->address + 65536; | |
9344 | ||
9345 | mp->min_address = min_address; | |
9346 | ||
9347 | if (min_mp == NULL) | |
9348 | { | |
9349 | mp->prev = NULL; | |
9350 | mp->next = minipool_vector_head; | |
9351 | ||
9352 | if (mp->next == NULL) | |
9353 | { | |
9354 | minipool_vector_tail = mp; | |
9355 | minipool_vector_label = gen_label_rtx (); | |
9356 | } | |
9357 | else | |
9358 | mp->next->prev = mp; | |
9359 | ||
9360 | minipool_vector_head = mp; | |
9361 | } | |
9362 | else | |
9363 | { | |
9364 | mp->next = min_mp->next; | |
9365 | mp->prev = min_mp; | |
9366 | min_mp->next = mp; | |
f676971a | 9367 | |
d5b7b3ae RE |
9368 | if (mp->next != NULL) |
9369 | mp->next->prev = mp; | |
9370 | else | |
9371 | minipool_vector_tail = mp; | |
9372 | } | |
9373 | ||
9374 | /* Save the new entry. */ | |
9375 | min_mp = mp; | |
9376 | ||
9377 | if (mp->prev) | |
9378 | mp = mp->prev; | |
9379 | else | |
9380 | mp->offset = 0; | |
9381 | ||
9382 | /* Scan over the following entries and adjust their offsets. */ | |
9383 | while (mp->next != NULL) | |
9384 | { | |
9385 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
9386 | mp->next->min_address = mp->min_address + mp->fix_size; | |
9387 | ||
9388 | if (mp->refcount) | |
9389 | mp->next->offset = mp->offset + mp->fix_size; | |
9390 | else | |
9391 | mp->next->offset = mp->offset; | |
9392 | ||
9393 | mp = mp->next; | |
9394 | } | |
9395 | ||
9396 | return min_mp; | |
9397 | } | |
9398 | ||
9399 | static void | |
e32bac5b | 9400 | assign_minipool_offsets (Mfix *barrier) |
d5b7b3ae RE |
9401 | { |
9402 | HOST_WIDE_INT offset = 0; | |
e32bac5b | 9403 | Mnode *mp; |
d5b7b3ae RE |
9404 | |
9405 | minipool_barrier = barrier; | |
9406 | ||
9407 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
9408 | { | |
9409 | mp->offset = offset; | |
f676971a | 9410 | |
d5b7b3ae RE |
9411 | if (mp->refcount > 0) |
9412 | offset += mp->fix_size; | |
9413 | } | |
9414 | } | |
9415 | ||
9416 | /* Output the literal table */ | |
9417 | static void | |
e32bac5b | 9418 | dump_minipool (rtx scan) |
d5b7b3ae | 9419 | { |
5a9335ef NC |
9420 | Mnode * mp; |
9421 | Mnode * nmp; | |
9422 | int align64 = 0; | |
9423 | ||
5848830f | 9424 | if (ARM_DOUBLEWORD_ALIGN) |
5a9335ef | 9425 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) |
88f77cba | 9426 | if (mp->refcount > 0 && mp->fix_size >= 8) |
5a9335ef NC |
9427 | { |
9428 | align64 = 1; | |
9429 | break; | |
9430 | } | |
d5b7b3ae | 9431 | |
c263766c RH |
9432 | if (dump_file) |
9433 | fprintf (dump_file, | |
5a9335ef NC |
9434 | ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", |
9435 | INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); | |
d5b7b3ae RE |
9436 | |
9437 | scan = emit_label_after (gen_label_rtx (), scan); | |
5a9335ef | 9438 | scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); |
d5b7b3ae RE |
9439 | scan = emit_label_after (minipool_vector_label, scan); |
9440 | ||
9441 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
9442 | { | |
9443 | if (mp->refcount > 0) | |
9444 | { | |
c263766c | 9445 | if (dump_file) |
d5b7b3ae | 9446 | { |
f676971a | 9447 | fprintf (dump_file, |
d5b7b3ae RE |
9448 | ";; Offset %u, min %ld, max %ld ", |
9449 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
9450 | (unsigned long) mp->max_address); | |
c263766c RH |
9451 | arm_print_value (dump_file, mp->value); |
9452 | fputc ('\n', dump_file); | |
d5b7b3ae RE |
9453 | } |
9454 | ||
9455 | switch (mp->fix_size) | |
9456 | { | |
9457 | #ifdef HAVE_consttable_1 | |
9458 | case 1: | |
9459 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
9460 | break; | |
9461 | ||
9462 | #endif | |
9463 | #ifdef HAVE_consttable_2 | |
9464 | case 2: | |
9465 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
9466 | break; | |
9467 | ||
9468 | #endif | |
9469 | #ifdef HAVE_consttable_4 | |
9470 | case 4: | |
9471 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
9472 | break; | |
9473 | ||
9474 | #endif | |
9475 | #ifdef HAVE_consttable_8 | |
9476 | case 8: | |
9477 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
9478 | break; | |
9479 | ||
88f77cba JB |
9480 | #endif |
9481 | #ifdef HAVE_consttable_16 | |
9482 | case 16: | |
9483 | scan = emit_insn_after (gen_consttable_16 (mp->value), scan); | |
9484 | break; | |
9485 | ||
d5b7b3ae RE |
9486 | #endif |
9487 | default: | |
e6d29d15 | 9488 | gcc_unreachable (); |
d5b7b3ae RE |
9489 | } |
9490 | } | |
9491 | ||
9492 | nmp = mp->next; | |
9493 | free (mp); | |
2b835d68 RE |
9494 | } |
9495 | ||
d5b7b3ae RE |
9496 | minipool_vector_head = minipool_vector_tail = NULL; |
9497 | scan = emit_insn_after (gen_consttable_end (), scan); | |
9498 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
9499 | } |
9500 | ||
d5b7b3ae RE |
9501 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
9502 | static int | |
e32bac5b | 9503 | arm_barrier_cost (rtx insn) |
949d79eb | 9504 | { |
d5b7b3ae RE |
9505 | /* Basing the location of the pool on the loop depth is preferable, |
9506 | but at the moment, the basic block information seems to be | |
9507 | corrupt by this stage of the compilation. */ | |
9508 | int base_cost = 50; | |
9509 | rtx next = next_nonnote_insn (insn); | |
9510 | ||
9511 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
9512 | base_cost -= 20; | |
9513 | ||
9514 | switch (GET_CODE (insn)) | |
9515 | { | |
9516 | case CODE_LABEL: | |
9517 | /* It will always be better to place the table before the label, rather | |
9518 | than after it. */ | |
f676971a | 9519 | return 50; |
949d79eb | 9520 | |
d5b7b3ae RE |
9521 | case INSN: |
9522 | case CALL_INSN: | |
9523 | return base_cost; | |
9524 | ||
9525 | case JUMP_INSN: | |
9526 | return base_cost - 10; | |
9527 | ||
9528 | default: | |
9529 | return base_cost + 10; | |
9530 | } | |
9531 | } | |
9532 | ||
9533 | /* Find the best place in the insn stream in the range | |
9534 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
9535 | Create the barrier by inserting a jump and add a new fix entry for | |
9536 | it. */ | |
9537 | static Mfix * | |
e32bac5b | 9538 | create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) |
d5b7b3ae RE |
9539 | { |
9540 | HOST_WIDE_INT count = 0; | |
9541 | rtx barrier; | |
9542 | rtx from = fix->insn; | |
7a7017bc PB |
9543 | /* The instruction after which we will insert the jump. */ |
9544 | rtx selected = NULL; | |
d5b7b3ae | 9545 | int selected_cost; |
7a7017bc | 9546 | /* The address at which the jump instruction will be placed. */ |
d5b7b3ae RE |
9547 | HOST_WIDE_INT selected_address; |
9548 | Mfix * new_fix; | |
9549 | HOST_WIDE_INT max_count = max_address - fix->address; | |
9550 | rtx label = gen_label_rtx (); | |
9551 | ||
9552 | selected_cost = arm_barrier_cost (from); | |
9553 | selected_address = fix->address; | |
9554 | ||
9555 | while (from && count < max_count) | |
9556 | { | |
9557 | rtx tmp; | |
9558 | int new_cost; | |
9559 | ||
9560 | /* This code shouldn't have been called if there was a natural barrier | |
9561 | within range. */ | |
e6d29d15 | 9562 | gcc_assert (GET_CODE (from) != BARRIER); |
d5b7b3ae RE |
9563 | |
9564 | /* Count the length of this insn. */ | |
9565 | count += get_attr_length (from); | |
9566 | ||
9567 | /* If there is a jump table, add its length. */ | |
9568 | tmp = is_jump_table (from); | |
9569 | if (tmp != NULL) | |
9570 | { | |
9571 | count += get_jump_table_size (tmp); | |
9572 | ||
9573 | /* Jump tables aren't in a basic block, so base the cost on | |
9574 | the dispatch insn. If we select this location, we will | |
9575 | still put the pool after the table. */ | |
9576 | new_cost = arm_barrier_cost (from); | |
9577 | ||
7a7017bc PB |
9578 | if (count < max_count |
9579 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
9580 | { |
9581 | selected = tmp; | |
9582 | selected_cost = new_cost; | |
9583 | selected_address = fix->address + count; | |
9584 | } | |
9585 | ||
9586 | /* Continue after the dispatch table. */ | |
9587 | from = NEXT_INSN (tmp); | |
9588 | continue; | |
9589 | } | |
9590 | ||
9591 | new_cost = arm_barrier_cost (from); | |
f676971a | 9592 | |
7a7017bc PB |
9593 | if (count < max_count |
9594 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
9595 | { |
9596 | selected = from; | |
9597 | selected_cost = new_cost; | |
9598 | selected_address = fix->address + count; | |
9599 | } | |
9600 | ||
9601 | from = NEXT_INSN (from); | |
9602 | } | |
9603 | ||
7a7017bc PB |
9604 | /* Make sure that we found a place to insert the jump. */ |
9605 | gcc_assert (selected); | |
9606 | ||
d5b7b3ae RE |
9607 | /* Create a new JUMP_INSN that branches around a barrier. */ |
9608 | from = emit_jump_insn_after (gen_jump (label), selected); | |
9609 | JUMP_LABEL (from) = label; | |
9610 | barrier = emit_barrier_after (from); | |
9611 | emit_label_after (label, barrier); | |
9612 | ||
9613 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 9614 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
9615 | new_fix->insn = barrier; |
9616 | new_fix->address = selected_address; | |
9617 | new_fix->next = fix->next; | |
9618 | fix->next = new_fix; | |
9619 | ||
9620 | return new_fix; | |
9621 | } | |
9622 | ||
9623 | /* Record that there is a natural barrier in the insn stream at | |
9624 | ADDRESS. */ | |
949d79eb | 9625 | static void |
e32bac5b | 9626 | push_minipool_barrier (rtx insn, HOST_WIDE_INT address) |
2b835d68 | 9627 | { |
c7319d87 | 9628 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 9629 | |
949d79eb RE |
9630 | fix->insn = insn; |
9631 | fix->address = address; | |
2b835d68 | 9632 | |
949d79eb RE |
9633 | fix->next = NULL; |
9634 | if (minipool_fix_head != NULL) | |
9635 | minipool_fix_tail->next = fix; | |
9636 | else | |
9637 | minipool_fix_head = fix; | |
9638 | ||
9639 | minipool_fix_tail = fix; | |
9640 | } | |
2b835d68 | 9641 | |
d5b7b3ae RE |
9642 | /* Record INSN, which will need fixing up to load a value from the |
9643 | minipool. ADDRESS is the offset of the insn since the start of the | |
9644 | function; LOC is a pointer to the part of the insn which requires | |
9645 | fixing; VALUE is the constant that must be loaded, which is of type | |
9646 | MODE. */ | |
949d79eb | 9647 | static void |
e32bac5b RE |
9648 | push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, |
9649 | enum machine_mode mode, rtx value) | |
949d79eb | 9650 | { |
c7319d87 | 9651 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb | 9652 | |
949d79eb RE |
9653 | fix->insn = insn; |
9654 | fix->address = address; | |
9655 | fix->loc = loc; | |
9656 | fix->mode = mode; | |
d5b7b3ae | 9657 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 9658 | fix->value = value; |
d5b7b3ae RE |
9659 | fix->forwards = get_attr_pool_range (insn); |
9660 | fix->backwards = get_attr_neg_pool_range (insn); | |
9661 | fix->minipool = NULL; | |
949d79eb RE |
9662 | |
9663 | /* If an insn doesn't have a range defined for it, then it isn't | |
e6d29d15 | 9664 | expecting to be reworked by this code. Better to stop now than |
949d79eb | 9665 | to generate duff assembly code. */ |
e6d29d15 | 9666 | gcc_assert (fix->forwards || fix->backwards); |
949d79eb | 9667 | |
34a9f549 PB |
9668 | /* If an entry requires 8-byte alignment then assume all constant pools |
9669 | require 4 bytes of padding. Trying to do this later on a per-pool | |
917f1b7e | 9670 | basis is awkward because existing pool entries have to be modified. */ |
88f77cba | 9671 | if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8) |
34a9f549 | 9672 | minipool_pad = 4; |
5a9335ef | 9673 | |
c263766c | 9674 | if (dump_file) |
d5b7b3ae | 9675 | { |
c263766c | 9676 | fprintf (dump_file, |
d5b7b3ae RE |
9677 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", |
9678 | GET_MODE_NAME (mode), | |
f676971a | 9679 | INSN_UID (insn), (unsigned long) address, |
d5b7b3ae | 9680 | -1 * (long)fix->backwards, (long)fix->forwards); |
c263766c RH |
9681 | arm_print_value (dump_file, fix->value); |
9682 | fprintf (dump_file, "\n"); | |
d5b7b3ae RE |
9683 | } |
9684 | ||
6354dc9b | 9685 | /* Add it to the chain of fixes. */ |
949d79eb | 9686 | fix->next = NULL; |
f676971a | 9687 | |
949d79eb RE |
9688 | if (minipool_fix_head != NULL) |
9689 | minipool_fix_tail->next = fix; | |
9690 | else | |
9691 | minipool_fix_head = fix; | |
9692 | ||
9693 | minipool_fix_tail = fix; | |
9694 | } | |
9695 | ||
9b901d50 | 9696 | /* Return the cost of synthesizing a 64-bit constant VAL inline. |
2075b05d RE |
9697 | Returns the number of insns needed, or 99 if we don't know how to |
9698 | do it. */ | |
9699 | int | |
9700 | arm_const_double_inline_cost (rtx val) | |
b9e8bfda | 9701 | { |
9b901d50 RE |
9702 | rtx lowpart, highpart; |
9703 | enum machine_mode mode; | |
e0b92319 | 9704 | |
9b901d50 | 9705 | mode = GET_MODE (val); |
b9e8bfda | 9706 | |
9b901d50 RE |
9707 | if (mode == VOIDmode) |
9708 | mode = DImode; | |
9709 | ||
9710 | gcc_assert (GET_MODE_SIZE (mode) == 8); | |
e0b92319 | 9711 | |
9b901d50 RE |
9712 | lowpart = gen_lowpart (SImode, val); |
9713 | highpart = gen_highpart_mode (SImode, mode, val); | |
e0b92319 | 9714 | |
9b901d50 RE |
9715 | gcc_assert (GET_CODE (lowpart) == CONST_INT); |
9716 | gcc_assert (GET_CODE (highpart) == CONST_INT); | |
9717 | ||
9718 | return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), | |
2075b05d | 9719 | NULL_RTX, NULL_RTX, 0, 0) |
9b901d50 | 9720 | + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart), |
2075b05d RE |
9721 | NULL_RTX, NULL_RTX, 0, 0)); |
9722 | } | |
9723 | ||
f3b569ca | 9724 | /* Return true if it is worthwhile to split a 64-bit constant into two |
b4a58f80 RE |
9725 | 32-bit operations. This is the case if optimizing for size, or |
9726 | if we have load delay slots, or if one 32-bit part can be done with | |
9727 | a single data operation. */ | |
9728 | bool | |
9729 | arm_const_double_by_parts (rtx val) | |
9730 | { | |
9731 | enum machine_mode mode = GET_MODE (val); | |
9732 | rtx part; | |
9733 | ||
9734 | if (optimize_size || arm_ld_sched) | |
9735 | return true; | |
9736 | ||
9737 | if (mode == VOIDmode) | |
9738 | mode = DImode; | |
e0b92319 | 9739 | |
b4a58f80 | 9740 | part = gen_highpart_mode (SImode, mode, val); |
e0b92319 | 9741 | |
b4a58f80 | 9742 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 9743 | |
b4a58f80 RE |
9744 | if (const_ok_for_arm (INTVAL (part)) |
9745 | || const_ok_for_arm (~INTVAL (part))) | |
9746 | return true; | |
e0b92319 | 9747 | |
b4a58f80 | 9748 | part = gen_lowpart (SImode, val); |
e0b92319 | 9749 | |
b4a58f80 | 9750 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 9751 | |
b4a58f80 RE |
9752 | if (const_ok_for_arm (INTVAL (part)) |
9753 | || const_ok_for_arm (~INTVAL (part))) | |
9754 | return true; | |
e0b92319 | 9755 | |
b4a58f80 RE |
9756 | return false; |
9757 | } | |
9758 | ||
f0375c66 NC |
9759 | /* Scan INSN and note any of its operands that need fixing. |
9760 | If DO_PUSHES is false we do not actually push any of the fixups | |
9b901d50 | 9761 | needed. The function returns TRUE if any fixups were needed/pushed. |
f0375c66 NC |
9762 | This is used by arm_memory_load_p() which needs to know about loads |
9763 | of constants that will be converted into minipool loads. */ | |
f0375c66 | 9764 | static bool |
e32bac5b | 9765 | note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) |
949d79eb | 9766 | { |
f0375c66 | 9767 | bool result = false; |
949d79eb RE |
9768 | int opno; |
9769 | ||
d5b7b3ae | 9770 | extract_insn (insn); |
949d79eb | 9771 | |
5895f793 | 9772 | if (!constrain_operands (1)) |
949d79eb RE |
9773 | fatal_insn_not_found (insn); |
9774 | ||
8c2a5582 RE |
9775 | if (recog_data.n_alternatives == 0) |
9776 | return false; | |
9777 | ||
9b901d50 RE |
9778 | /* Fill in recog_op_alt with information about the constraints of |
9779 | this insn. */ | |
949d79eb RE |
9780 | preprocess_constraints (); |
9781 | ||
1ccbefce | 9782 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 9783 | { |
6354dc9b | 9784 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 9785 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
9786 | continue; |
9787 | ||
9788 | /* If this alternative is a memory reference, then any mention | |
9789 | of constants in this alternative is really to fool reload | |
9790 | into allowing us to accept one there. We need to fix them up | |
9791 | now so that we output the right code. */ | |
9792 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
9793 | { | |
1ccbefce | 9794 | rtx op = recog_data.operand[opno]; |
949d79eb | 9795 | |
9b901d50 | 9796 | if (CONSTANT_P (op)) |
f0375c66 NC |
9797 | { |
9798 | if (do_pushes) | |
9799 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
9800 | recog_data.operand_mode[opno], op); | |
9801 | result = true; | |
9802 | } | |
d5b7b3ae | 9803 | else if (GET_CODE (op) == MEM |
949d79eb RE |
9804 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
9805 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
f0375c66 NC |
9806 | { |
9807 | if (do_pushes) | |
244b1afb RE |
9808 | { |
9809 | rtx cop = avoid_constant_pool_reference (op); | |
9810 | ||
9811 | /* Casting the address of something to a mode narrower | |
9812 | than a word can cause avoid_constant_pool_reference() | |
9813 | to return the pool reference itself. That's no good to | |
f676971a | 9814 | us here. Lets just hope that we can use the |
244b1afb RE |
9815 | constant pool value directly. */ |
9816 | if (op == cop) | |
c769a35d | 9817 | cop = get_pool_constant (XEXP (op, 0)); |
244b1afb RE |
9818 | |
9819 | push_minipool_fix (insn, address, | |
9820 | recog_data.operand_loc[opno], | |
c769a35d | 9821 | recog_data.operand_mode[opno], cop); |
244b1afb | 9822 | } |
f0375c66 NC |
9823 | |
9824 | result = true; | |
9825 | } | |
949d79eb | 9826 | } |
2b835d68 | 9827 | } |
f0375c66 NC |
9828 | |
9829 | return result; | |
2b835d68 RE |
9830 | } |
9831 | ||
18dbd950 RS |
9832 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
9833 | load addresses a limited distance around the pc. We do some | |
9834 | special munging to move the constant pool values to the correct | |
9835 | point in the code. */ | |
18dbd950 | 9836 | static void |
e32bac5b | 9837 | arm_reorg (void) |
2b835d68 RE |
9838 | { |
9839 | rtx insn; | |
d5b7b3ae RE |
9840 | HOST_WIDE_INT address = 0; |
9841 | Mfix * fix; | |
ad076f4e | 9842 | |
949d79eb | 9843 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 9844 | |
949d79eb RE |
9845 | /* The first insn must always be a note, or the code below won't |
9846 | scan it properly. */ | |
18dbd950 | 9847 | insn = get_insns (); |
e6d29d15 | 9848 | gcc_assert (GET_CODE (insn) == NOTE); |
34a9f549 | 9849 | minipool_pad = 0; |
949d79eb RE |
9850 | |
9851 | /* Scan all the insns and record the operands that will need fixing. */ | |
18dbd950 | 9852 | for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) |
2b835d68 | 9853 | { |
9b6b54e2 | 9854 | if (TARGET_CIRRUS_FIX_INVALID_INSNS |
f0375c66 | 9855 | && (arm_cirrus_insn_p (insn) |
9b6b54e2 | 9856 | || GET_CODE (insn) == JUMP_INSN |
f0375c66 | 9857 | || arm_memory_load_p (insn))) |
9b6b54e2 NC |
9858 | cirrus_reorg (insn); |
9859 | ||
949d79eb | 9860 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 9861 | push_minipool_barrier (insn, address); |
f0375c66 | 9862 | else if (INSN_P (insn)) |
949d79eb RE |
9863 | { |
9864 | rtx table; | |
9865 | ||
f0375c66 | 9866 | note_invalid_constants (insn, address, true); |
949d79eb | 9867 | address += get_attr_length (insn); |
d5b7b3ae | 9868 | |
949d79eb RE |
9869 | /* If the insn is a vector jump, add the size of the table |
9870 | and skip the table. */ | |
d5b7b3ae | 9871 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 9872 | { |
d5b7b3ae | 9873 | address += get_jump_table_size (table); |
949d79eb RE |
9874 | insn = table; |
9875 | } | |
9876 | } | |
9877 | } | |
332072db | 9878 | |
d5b7b3ae | 9879 | fix = minipool_fix_head; |
f676971a | 9880 | |
949d79eb | 9881 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 9882 | while (fix) |
949d79eb | 9883 | { |
d5b7b3ae RE |
9884 | Mfix * ftmp; |
9885 | Mfix * fdel; | |
9886 | Mfix * last_added_fix; | |
9887 | Mfix * last_barrier = NULL; | |
9888 | Mfix * this_fix; | |
949d79eb RE |
9889 | |
9890 | /* Skip any further barriers before the next fix. */ | |
9891 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
9892 | fix = fix->next; | |
9893 | ||
d5b7b3ae | 9894 | /* No more fixes. */ |
949d79eb RE |
9895 | if (fix == NULL) |
9896 | break; | |
332072db | 9897 | |
d5b7b3ae | 9898 | last_added_fix = NULL; |
2b835d68 | 9899 | |
d5b7b3ae | 9900 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 9901 | { |
949d79eb | 9902 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 9903 | { |
d5b7b3ae RE |
9904 | if (ftmp->address >= minipool_vector_head->max_address) |
9905 | break; | |
2b835d68 | 9906 | |
d5b7b3ae | 9907 | last_barrier = ftmp; |
2b835d68 | 9908 | } |
d5b7b3ae RE |
9909 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
9910 | break; | |
9911 | ||
9912 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 9913 | } |
949d79eb | 9914 | |
d5b7b3ae RE |
9915 | /* If we found a barrier, drop back to that; any fixes that we |
9916 | could have reached but come after the barrier will now go in | |
9917 | the next mini-pool. */ | |
949d79eb RE |
9918 | if (last_barrier != NULL) |
9919 | { | |
f676971a | 9920 | /* Reduce the refcount for those fixes that won't go into this |
d5b7b3ae RE |
9921 | pool after all. */ |
9922 | for (fdel = last_barrier->next; | |
9923 | fdel && fdel != ftmp; | |
9924 | fdel = fdel->next) | |
9925 | { | |
9926 | fdel->minipool->refcount--; | |
9927 | fdel->minipool = NULL; | |
9928 | } | |
9929 | ||
949d79eb RE |
9930 | ftmp = last_barrier; |
9931 | } | |
9932 | else | |
2bfa88dc | 9933 | { |
d5b7b3ae RE |
9934 | /* ftmp is first fix that we can't fit into this pool and |
9935 | there no natural barriers that we could use. Insert a | |
9936 | new barrier in the code somewhere between the previous | |
9937 | fix and this one, and arrange to jump around it. */ | |
9938 | HOST_WIDE_INT max_address; | |
9939 | ||
9940 | /* The last item on the list of fixes must be a barrier, so | |
9941 | we can never run off the end of the list of fixes without | |
9942 | last_barrier being set. */ | |
e6d29d15 | 9943 | gcc_assert (ftmp); |
d5b7b3ae RE |
9944 | |
9945 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
9946 | /* Check that there isn't another fix that is in range that |
9947 | we couldn't fit into this pool because the pool was | |
9948 | already too large: we need to put the pool before such an | |
7a7017bc PB |
9949 | instruction. The pool itself may come just after the |
9950 | fix because create_fix_barrier also allows space for a | |
9951 | jump instruction. */ | |
d5b7b3ae | 9952 | if (ftmp->address < max_address) |
7a7017bc | 9953 | max_address = ftmp->address + 1; |
d5b7b3ae RE |
9954 | |
9955 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
9956 | } | |
9957 | ||
9958 | assign_minipool_offsets (last_barrier); | |
9959 | ||
9960 | while (ftmp) | |
9961 | { | |
9962 | if (GET_CODE (ftmp->insn) != BARRIER | |
9963 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
9964 | == NULL)) | |
9965 | break; | |
2bfa88dc | 9966 | |
d5b7b3ae | 9967 | ftmp = ftmp->next; |
2bfa88dc | 9968 | } |
949d79eb RE |
9969 | |
9970 | /* Scan over the fixes we have identified for this pool, fixing them | |
9971 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 9972 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
9973 | this_fix = this_fix->next) |
9974 | if (GET_CODE (this_fix->insn) != BARRIER) | |
9975 | { | |
949d79eb | 9976 | rtx addr |
f676971a | 9977 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, |
949d79eb | 9978 | minipool_vector_label), |
d5b7b3ae | 9979 | this_fix->minipool->offset); |
949d79eb RE |
9980 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
9981 | } | |
9982 | ||
d5b7b3ae | 9983 | dump_minipool (last_barrier->insn); |
949d79eb | 9984 | fix = ftmp; |
2b835d68 | 9985 | } |
4b632bf1 | 9986 | |
949d79eb RE |
9987 | /* From now on we must synthesize any constants that we can't handle |
9988 | directly. This can happen if the RTL gets split during final | |
9989 | instruction generation. */ | |
4b632bf1 | 9990 | after_arm_reorg = 1; |
c7319d87 RE |
9991 | |
9992 | /* Free the minipool memory. */ | |
9993 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 9994 | } |
cce8749e CH |
9995 | \f |
9996 | /* Routines to output assembly language. */ | |
9997 | ||
f3bb6135 | 9998 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 9999 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 10000 | when cross compiling. */ |
cd2b33d0 | 10001 | const char * |
e32bac5b | 10002 | fp_immediate_constant (rtx x) |
ff9940b0 RE |
10003 | { |
10004 | REAL_VALUE_TYPE r; | |
10005 | int i; | |
f676971a | 10006 | |
9b66ebb1 PB |
10007 | if (!fp_consts_inited) |
10008 | init_fp_table (); | |
f676971a | 10009 | |
ff9940b0 RE |
10010 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
10011 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
10012 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
10013 | return strings_fp[i]; | |
f3bb6135 | 10014 | |
e6d29d15 | 10015 | gcc_unreachable (); |
ff9940b0 RE |
10016 | } |
10017 | ||
9997d19d | 10018 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
cd2b33d0 | 10019 | static const char * |
e32bac5b | 10020 | fp_const_from_val (REAL_VALUE_TYPE *r) |
9997d19d RE |
10021 | { |
10022 | int i; | |
10023 | ||
9b66ebb1 PB |
10024 | if (!fp_consts_inited) |
10025 | init_fp_table (); | |
9997d19d RE |
10026 | |
10027 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
10028 | if (REAL_VALUES_EQUAL (*r, values_fp[i])) |
10029 | return strings_fp[i]; | |
9997d19d | 10030 | |
e6d29d15 | 10031 | gcc_unreachable (); |
9997d19d | 10032 | } |
ff9940b0 | 10033 | |
cce8749e CH |
10034 | /* Output the operands of a LDM/STM instruction to STREAM. |
10035 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 | 10036 | REG is the base register, either the frame pointer or the stack pointer, |
a15908a4 PB |
10037 | INSTR is the possibly suffixed load or store instruction. |
10038 | RFE is nonzero if the instruction should also copy spsr to cpsr. */ | |
b279b20a | 10039 | |
d5b7b3ae | 10040 | static void |
b279b20a | 10041 | print_multi_reg (FILE *stream, const char *instr, unsigned reg, |
a15908a4 | 10042 | unsigned long mask, int rfe) |
cce8749e | 10043 | { |
b279b20a NC |
10044 | unsigned i; |
10045 | bool not_first = FALSE; | |
cce8749e | 10046 | |
a15908a4 | 10047 | gcc_assert (!rfe || (mask & (1 << PC_REGNUM))); |
1d5473cb | 10048 | fputc ('\t', stream); |
dd18ae56 | 10049 | asm_fprintf (stream, instr, reg); |
5b3e6663 | 10050 | fputc ('{', stream); |
f676971a | 10051 | |
d5b7b3ae | 10052 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
10053 | if (mask & (1 << i)) |
10054 | { | |
10055 | if (not_first) | |
10056 | fprintf (stream, ", "); | |
f676971a | 10057 | |
dd18ae56 | 10058 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
10059 | not_first = TRUE; |
10060 | } | |
f3bb6135 | 10061 | |
a15908a4 PB |
10062 | if (rfe) |
10063 | fprintf (stream, "}^\n"); | |
10064 | else | |
10065 | fprintf (stream, "}\n"); | |
f3bb6135 | 10066 | } |
cce8749e | 10067 | |
9b66ebb1 | 10068 | |
8edfc4cc | 10069 | /* Output a FLDMD instruction to STREAM. |
9728c9d1 PB |
10070 | BASE if the register containing the address. |
10071 | REG and COUNT specify the register range. | |
8edfc4cc MS |
10072 | Extra registers may be added to avoid hardware bugs. |
10073 | ||
10074 | We output FLDMD even for ARMv5 VFP implementations. Although | |
10075 | FLDMD is technically not supported until ARMv6, it is believed | |
10076 | that all VFP implementations support its use in this context. */ | |
9b66ebb1 PB |
10077 | |
10078 | static void | |
8edfc4cc | 10079 | vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count) |
9b66ebb1 PB |
10080 | { |
10081 | int i; | |
10082 | ||
9728c9d1 PB |
10083 | /* Workaround ARM10 VFPr1 bug. */ |
10084 | if (count == 2 && !arm_arch6) | |
10085 | { | |
10086 | if (reg == 15) | |
10087 | reg--; | |
10088 | count++; | |
10089 | } | |
10090 | ||
f1adb0a9 JB |
10091 | /* FLDMD may not load more than 16 doubleword registers at a time. Split the |
10092 | load into multiple parts if we have to handle more than 16 registers. */ | |
10093 | if (count > 16) | |
10094 | { | |
10095 | vfp_output_fldmd (stream, base, reg, 16); | |
10096 | vfp_output_fldmd (stream, base, reg + 16, count - 16); | |
10097 | return; | |
10098 | } | |
10099 | ||
9b66ebb1 | 10100 | fputc ('\t', stream); |
8edfc4cc | 10101 | asm_fprintf (stream, "fldmfdd\t%r!, {", base); |
9b66ebb1 | 10102 | |
9728c9d1 | 10103 | for (i = reg; i < reg + count; i++) |
9b66ebb1 | 10104 | { |
9728c9d1 | 10105 | if (i > reg) |
9b66ebb1 | 10106 | fputs (", ", stream); |
9728c9d1 | 10107 | asm_fprintf (stream, "d%d", i); |
9b66ebb1 PB |
10108 | } |
10109 | fputs ("}\n", stream); | |
9728c9d1 | 10110 | |
9b66ebb1 PB |
10111 | } |
10112 | ||
10113 | ||
10114 | /* Output the assembly for a store multiple. */ | |
10115 | ||
10116 | const char * | |
8edfc4cc | 10117 | vfp_output_fstmd (rtx * operands) |
9b66ebb1 PB |
10118 | { |
10119 | char pattern[100]; | |
10120 | int p; | |
10121 | int base; | |
10122 | int i; | |
10123 | ||
8edfc4cc | 10124 | strcpy (pattern, "fstmfdd\t%m0!, {%P1"); |
9b66ebb1 PB |
10125 | p = strlen (pattern); |
10126 | ||
e6d29d15 | 10127 | gcc_assert (GET_CODE (operands[1]) == REG); |
9b66ebb1 PB |
10128 | |
10129 | base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; | |
10130 | for (i = 1; i < XVECLEN (operands[2], 0); i++) | |
10131 | { | |
10132 | p += sprintf (&pattern[p], ", d%d", base + i); | |
10133 | } | |
10134 | strcpy (&pattern[p], "}"); | |
10135 | ||
10136 | output_asm_insn (pattern, operands); | |
10137 | return ""; | |
10138 | } | |
10139 | ||
10140 | ||
9728c9d1 PB |
10141 | /* Emit RTL to save block of VFP register pairs to the stack. Returns the |
10142 | number of bytes pushed. */ | |
9b66ebb1 | 10143 | |
9728c9d1 | 10144 | static int |
8edfc4cc | 10145 | vfp_emit_fstmd (int base_reg, int count) |
9b66ebb1 PB |
10146 | { |
10147 | rtx par; | |
10148 | rtx dwarf; | |
10149 | rtx tmp, reg; | |
10150 | int i; | |
10151 | ||
9728c9d1 PB |
10152 | /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two |
10153 | register pairs are stored by a store multiple insn. We avoid this | |
10154 | by pushing an extra pair. */ | |
10155 | if (count == 2 && !arm_arch6) | |
10156 | { | |
10157 | if (base_reg == LAST_VFP_REGNUM - 3) | |
10158 | base_reg -= 2; | |
10159 | count++; | |
10160 | } | |
10161 | ||
f1adb0a9 JB |
10162 | /* FSTMD may not store more than 16 doubleword registers at once. Split |
10163 | larger stores into multiple parts (up to a maximum of two, in | |
10164 | practice). */ | |
10165 | if (count > 16) | |
10166 | { | |
10167 | int saved; | |
10168 | /* NOTE: base_reg is an internal register number, so each D register | |
10169 | counts as 2. */ | |
10170 | saved = vfp_emit_fstmd (base_reg + 32, count - 16); | |
10171 | saved += vfp_emit_fstmd (base_reg, 16); | |
10172 | return saved; | |
10173 | } | |
10174 | ||
9b66ebb1 PB |
10175 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
10176 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); | |
10177 | ||
10178 | reg = gen_rtx_REG (DFmode, base_reg); | |
10179 | base_reg += 2; | |
10180 | ||
10181 | XVECEXP (par, 0, 0) | |
10182 | = gen_rtx_SET (VOIDmode, | |
31fa16b6 RE |
10183 | gen_frame_mem (BLKmode, |
10184 | gen_rtx_PRE_DEC (BLKmode, | |
10185 | stack_pointer_rtx)), | |
9b66ebb1 PB |
10186 | gen_rtx_UNSPEC (BLKmode, |
10187 | gen_rtvec (1, reg), | |
10188 | UNSPEC_PUSH_MULT)); | |
10189 | ||
10190 | tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
8edfc4cc | 10191 | plus_constant (stack_pointer_rtx, -(count * 8))); |
9b66ebb1 PB |
10192 | RTX_FRAME_RELATED_P (tmp) = 1; |
10193 | XVECEXP (dwarf, 0, 0) = tmp; | |
10194 | ||
10195 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 10196 | gen_frame_mem (DFmode, stack_pointer_rtx), |
9b66ebb1 PB |
10197 | reg); |
10198 | RTX_FRAME_RELATED_P (tmp) = 1; | |
10199 | XVECEXP (dwarf, 0, 1) = tmp; | |
10200 | ||
10201 | for (i = 1; i < count; i++) | |
10202 | { | |
10203 | reg = gen_rtx_REG (DFmode, base_reg); | |
10204 | base_reg += 2; | |
10205 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
10206 | ||
10207 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 10208 | gen_frame_mem (DFmode, |
d66437c5 RE |
10209 | plus_constant (stack_pointer_rtx, |
10210 | i * 8)), | |
9b66ebb1 PB |
10211 | reg); |
10212 | RTX_FRAME_RELATED_P (tmp) = 1; | |
10213 | XVECEXP (dwarf, 0, i + 1) = tmp; | |
10214 | } | |
10215 | ||
10216 | par = emit_insn (par); | |
10217 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
10218 | REG_NOTES (par)); | |
9728c9d1 PB |
10219 | RTX_FRAME_RELATED_P (par) = 1; |
10220 | ||
8edfc4cc | 10221 | return count * 8; |
9b66ebb1 PB |
10222 | } |
10223 | ||
9403b7f7 RS |
10224 | /* Emit a call instruction with pattern PAT. ADDR is the address of |
10225 | the call target. */ | |
10226 | ||
10227 | void | |
10228 | arm_emit_call_insn (rtx pat, rtx addr) | |
10229 | { | |
10230 | rtx insn; | |
10231 | ||
10232 | insn = emit_call_insn (pat); | |
10233 | ||
10234 | /* The PIC register is live on entry to VxWorks PIC PLT entries. | |
10235 | If the call might use such an entry, add a use of the PIC register | |
10236 | to the instruction's CALL_INSN_FUNCTION_USAGE. */ | |
10237 | if (TARGET_VXWORKS_RTP | |
10238 | && flag_pic | |
10239 | && GET_CODE (addr) == SYMBOL_REF | |
10240 | && (SYMBOL_REF_DECL (addr) | |
10241 | ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr)) | |
10242 | : !SYMBOL_REF_LOCAL_P (addr))) | |
10243 | { | |
10244 | require_pic_register (); | |
10245 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg); | |
10246 | } | |
10247 | } | |
9b66ebb1 | 10248 | |
6354dc9b | 10249 | /* Output a 'call' insn. */ |
cd2b33d0 | 10250 | const char * |
e32bac5b | 10251 | output_call (rtx *operands) |
cce8749e | 10252 | { |
e6d29d15 | 10253 | gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */ |
cce8749e | 10254 | |
68d560d4 | 10255 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
62b10bbc | 10256 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 10257 | { |
62b10bbc | 10258 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 10259 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 10260 | } |
f676971a | 10261 | |
1d5473cb | 10262 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
f676971a | 10263 | |
68d560d4 | 10264 | if (TARGET_INTERWORK || arm_arch4t) |
da6558fd NC |
10265 | output_asm_insn ("bx%?\t%0", operands); |
10266 | else | |
10267 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
f676971a | 10268 | |
f3bb6135 RE |
10269 | return ""; |
10270 | } | |
cce8749e | 10271 | |
6354dc9b | 10272 | /* Output a 'call' insn that is a reference in memory. */ |
cd2b33d0 | 10273 | const char * |
e32bac5b | 10274 | output_call_mem (rtx *operands) |
ff9940b0 | 10275 | { |
68d560d4 | 10276 | if (TARGET_INTERWORK && !arm_arch5) |
da6558fd NC |
10277 | { |
10278 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
10279 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
10280 | output_asm_insn ("bx%?\t%|ip", operands); | |
10281 | } | |
6ab5da80 RE |
10282 | else if (regno_use_in (LR_REGNUM, operands[0])) |
10283 | { | |
10284 | /* LR is used in the memory address. We load the address in the | |
10285 | first instruction. It's safe to use IP as the target of the | |
10286 | load since the call will kill it anyway. */ | |
10287 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
68d560d4 | 10288 | if (arm_arch5) |
07ec3810 | 10289 | output_asm_insn ("blx%?\t%|ip", operands); |
68d560d4 RE |
10290 | else |
10291 | { | |
10292 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
10293 | if (arm_arch4t) | |
10294 | output_asm_insn ("bx%?\t%|ip", operands); | |
10295 | else | |
10296 | output_asm_insn ("mov%?\t%|pc, %|ip", operands); | |
10297 | } | |
6ab5da80 | 10298 | } |
da6558fd NC |
10299 | else |
10300 | { | |
10301 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
10302 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
10303 | } | |
10304 | ||
f3bb6135 RE |
10305 | return ""; |
10306 | } | |
ff9940b0 RE |
10307 | |
10308 | ||
3b684012 RE |
10309 | /* Output a move from arm registers to an fpa registers. |
10310 | OPERANDS[0] is an fpa register. | |
ff9940b0 | 10311 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 10312 | const char * |
e32bac5b | 10313 | output_mov_long_double_fpa_from_arm (rtx *operands) |
ff9940b0 RE |
10314 | { |
10315 | int arm_reg0 = REGNO (operands[1]); | |
10316 | rtx ops[3]; | |
10317 | ||
e6d29d15 | 10318 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 10319 | |
43cffd11 RE |
10320 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
10321 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
10322 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
f676971a | 10323 | |
5b3e6663 | 10324 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
1d5473cb | 10325 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); |
f676971a | 10326 | |
f3bb6135 RE |
10327 | return ""; |
10328 | } | |
ff9940b0 | 10329 | |
3b684012 | 10330 | /* Output a move from an fpa register to arm registers. |
ff9940b0 | 10331 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 10332 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 10333 | const char * |
e32bac5b | 10334 | output_mov_long_double_arm_from_fpa (rtx *operands) |
ff9940b0 RE |
10335 | { |
10336 | int arm_reg0 = REGNO (operands[0]); | |
10337 | rtx ops[3]; | |
10338 | ||
e6d29d15 | 10339 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 10340 | |
43cffd11 RE |
10341 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
10342 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
10343 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 10344 | |
1d5473cb | 10345 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
5b3e6663 | 10346 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
f3bb6135 RE |
10347 | return ""; |
10348 | } | |
ff9940b0 RE |
10349 | |
10350 | /* Output a move from arm registers to arm registers of a long double | |
10351 | OPERANDS[0] is the destination. | |
10352 | OPERANDS[1] is the source. */ | |
cd2b33d0 | 10353 | const char * |
e32bac5b | 10354 | output_mov_long_double_arm_from_arm (rtx *operands) |
ff9940b0 | 10355 | { |
6354dc9b | 10356 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
10357 | int dest_start = REGNO (operands[0]); |
10358 | int src_start = REGNO (operands[1]); | |
10359 | rtx ops[2]; | |
10360 | int i; | |
10361 | ||
10362 | if (dest_start < src_start) | |
10363 | { | |
10364 | for (i = 0; i < 3; i++) | |
10365 | { | |
43cffd11 RE |
10366 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
10367 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 10368 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
10369 | } |
10370 | } | |
10371 | else | |
10372 | { | |
10373 | for (i = 2; i >= 0; i--) | |
10374 | { | |
43cffd11 RE |
10375 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
10376 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 10377 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
10378 | } |
10379 | } | |
f3bb6135 | 10380 | |
ff9940b0 RE |
10381 | return ""; |
10382 | } | |
10383 | ||
10384 | ||
571191af PB |
10385 | /* Emit a MOVW/MOVT pair. */ |
10386 | void arm_emit_movpair (rtx dest, rtx src) | |
10387 | { | |
10388 | emit_set_insn (dest, gen_rtx_HIGH (SImode, src)); | |
10389 | emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src)); | |
10390 | } | |
10391 | ||
10392 | ||
3b684012 RE |
10393 | /* Output a move from arm registers to an fpa registers. |
10394 | OPERANDS[0] is an fpa register. | |
cce8749e | 10395 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 10396 | const char * |
e32bac5b | 10397 | output_mov_double_fpa_from_arm (rtx *operands) |
cce8749e CH |
10398 | { |
10399 | int arm_reg0 = REGNO (operands[1]); | |
10400 | rtx ops[2]; | |
10401 | ||
e6d29d15 | 10402 | gcc_assert (arm_reg0 != IP_REGNUM); |
f676971a | 10403 | |
43cffd11 RE |
10404 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
10405 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
5b3e6663 | 10406 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops); |
1d5473cb | 10407 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); |
f3bb6135 RE |
10408 | return ""; |
10409 | } | |
cce8749e | 10410 | |
3b684012 | 10411 | /* Output a move from an fpa register to arm registers. |
cce8749e | 10412 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 10413 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 10414 | const char * |
e32bac5b | 10415 | output_mov_double_arm_from_fpa (rtx *operands) |
cce8749e CH |
10416 | { |
10417 | int arm_reg0 = REGNO (operands[0]); | |
10418 | rtx ops[2]; | |
10419 | ||
e6d29d15 | 10420 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 10421 | |
43cffd11 RE |
10422 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
10423 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb | 10424 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
5b3e6663 | 10425 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops); |
f3bb6135 RE |
10426 | return ""; |
10427 | } | |
cce8749e CH |
10428 | |
10429 | /* Output a move between double words. | |
10430 | It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM | |
10431 | or MEM<-REG and all MEMs must be offsettable addresses. */ | |
cd2b33d0 | 10432 | const char * |
e32bac5b | 10433 | output_move_double (rtx *operands) |
cce8749e CH |
10434 | { |
10435 | enum rtx_code code0 = GET_CODE (operands[0]); | |
10436 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 10437 | rtx otherops[3]; |
cce8749e CH |
10438 | |
10439 | if (code0 == REG) | |
10440 | { | |
f0b4bdd5 | 10441 | unsigned int reg0 = REGNO (operands[0]); |
cce8749e | 10442 | |
43cffd11 | 10443 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
f676971a | 10444 | |
e6d29d15 NS |
10445 | gcc_assert (code1 == MEM); /* Constraints should ensure this. */ |
10446 | ||
10447 | switch (GET_CODE (XEXP (operands[1], 0))) | |
cce8749e | 10448 | { |
e6d29d15 | 10449 | case REG: |
5fd42423 PB |
10450 | if (TARGET_LDRD |
10451 | && !(fix_cm3_ldrd && reg0 == REGNO(XEXP (operands[1], 0)))) | |
5dea0c19 PB |
10452 | output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands); |
10453 | else | |
10454 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
e6d29d15 | 10455 | break; |
e0b92319 | 10456 | |
e6d29d15 NS |
10457 | case PRE_INC: |
10458 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 10459 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands); |
e6d29d15 | 10460 | break; |
e0b92319 | 10461 | |
e6d29d15 | 10462 | case PRE_DEC: |
5b3e6663 PB |
10463 | if (TARGET_LDRD) |
10464 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands); | |
10465 | else | |
10466 | output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands); | |
e6d29d15 | 10467 | break; |
e0b92319 | 10468 | |
e6d29d15 | 10469 | case POST_INC: |
5dea0c19 PB |
10470 | if (TARGET_LDRD) |
10471 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands); | |
10472 | else | |
10473 | output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands); | |
e6d29d15 | 10474 | break; |
e0b92319 | 10475 | |
e6d29d15 NS |
10476 | case POST_DEC: |
10477 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 10478 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands); |
e6d29d15 | 10479 | break; |
e0b92319 | 10480 | |
e6d29d15 NS |
10481 | case PRE_MODIFY: |
10482 | case POST_MODIFY: | |
5fd42423 PB |
10483 | /* Autoicrement addressing modes should never have overlapping |
10484 | base and destination registers, and overlapping index registers | |
10485 | are already prohibited, so this doesn't need to worry about | |
10486 | fix_cm3_ldrd. */ | |
e6d29d15 NS |
10487 | otherops[0] = operands[0]; |
10488 | otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0); | |
10489 | otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1); | |
e0b92319 | 10490 | |
e6d29d15 | 10491 | if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY) |
cce8749e | 10492 | { |
e6d29d15 | 10493 | if (reg_overlap_mentioned_p (otherops[0], otherops[2])) |
fdd695fd | 10494 | { |
e6d29d15 NS |
10495 | /* Registers overlap so split out the increment. */ |
10496 | output_asm_insn ("add%?\t%1, %1, %2", otherops); | |
5b3e6663 | 10497 | output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops); |
fdd695fd PB |
10498 | } |
10499 | else | |
fe2d934b | 10500 | { |
ff128632 RE |
10501 | /* Use a single insn if we can. |
10502 | FIXME: IWMMXT allows offsets larger than ldrd can | |
10503 | handle, fix these up with a pair of ldr. */ | |
10504 | if (TARGET_THUMB2 | |
10505 | || GET_CODE (otherops[2]) != CONST_INT | |
10506 | || (INTVAL (otherops[2]) > -256 | |
10507 | && INTVAL (otherops[2]) < 256)) | |
10508 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops); | |
10509 | else | |
fe2d934b PB |
10510 | { |
10511 | output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | |
ff128632 | 10512 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b | 10513 | } |
fe2d934b | 10514 | } |
e6d29d15 NS |
10515 | } |
10516 | else | |
10517 | { | |
ff128632 RE |
10518 | /* Use a single insn if we can. |
10519 | FIXME: IWMMXT allows offsets larger than ldrd can handle, | |
fe2d934b | 10520 | fix these up with a pair of ldr. */ |
ff128632 RE |
10521 | if (TARGET_THUMB2 |
10522 | || GET_CODE (otherops[2]) != CONST_INT | |
10523 | || (INTVAL (otherops[2]) > -256 | |
10524 | && INTVAL (otherops[2]) < 256)) | |
10525 | output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops); | |
10526 | else | |
fe2d934b | 10527 | { |
ff128632 | 10528 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
10529 | output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); |
10530 | } | |
e6d29d15 NS |
10531 | } |
10532 | break; | |
e0b92319 | 10533 | |
e6d29d15 NS |
10534 | case LABEL_REF: |
10535 | case CONST: | |
5dea0c19 PB |
10536 | /* We might be able to use ldrd %0, %1 here. However the range is |
10537 | different to ldr/adr, and it is broken on some ARMv7-M | |
10538 | implementations. */ | |
5fd42423 PB |
10539 | /* Use the second register of the pair to avoid problematic |
10540 | overlap. */ | |
10541 | otherops[1] = operands[1]; | |
10542 | output_asm_insn ("adr%?\t%0, %1", otherops); | |
10543 | operands[1] = otherops[0]; | |
5dea0c19 | 10544 | if (TARGET_LDRD) |
5fd42423 | 10545 | output_asm_insn ("ldr%(d%)\t%0, [%1]", operands); |
5dea0c19 | 10546 | else |
5fd42423 | 10547 | output_asm_insn ("ldm%(ia%)\t%1, %M0", operands); |
e6d29d15 | 10548 | break; |
e0b92319 | 10549 | |
5b3e6663 | 10550 | /* ??? This needs checking for thumb2. */ |
e6d29d15 NS |
10551 | default: |
10552 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), | |
10553 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
10554 | { | |
10555 | otherops[0] = operands[0]; | |
10556 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
10557 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
e0b92319 | 10558 | |
e6d29d15 | 10559 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) |
fdd695fd | 10560 | { |
5dea0c19 | 10561 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 10562 | { |
e6d29d15 | 10563 | switch ((int) INTVAL (otherops[2])) |
2b835d68 | 10564 | { |
e6d29d15 | 10565 | case -8: |
5b3e6663 | 10566 | output_asm_insn ("ldm%(db%)\t%1, %M0", otherops); |
e6d29d15 NS |
10567 | return ""; |
10568 | case -4: | |
5b3e6663 PB |
10569 | if (TARGET_THUMB2) |
10570 | break; | |
10571 | output_asm_insn ("ldm%(da%)\t%1, %M0", otherops); | |
e6d29d15 NS |
10572 | return ""; |
10573 | case 4: | |
5b3e6663 PB |
10574 | if (TARGET_THUMB2) |
10575 | break; | |
10576 | output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops); | |
e6d29d15 | 10577 | return ""; |
fdd695fd | 10578 | } |
e6d29d15 | 10579 | } |
5fd42423 PB |
10580 | otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1); |
10581 | operands[1] = otherops[0]; | |
e6d29d15 NS |
10582 | if (TARGET_LDRD |
10583 | && (GET_CODE (otherops[2]) == REG | |
ff128632 | 10584 | || TARGET_THUMB2 |
e6d29d15 NS |
10585 | || (GET_CODE (otherops[2]) == CONST_INT |
10586 | && INTVAL (otherops[2]) > -256 | |
10587 | && INTVAL (otherops[2]) < 256))) | |
10588 | { | |
5fd42423 | 10589 | if (reg_overlap_mentioned_p (operands[0], |
e6d29d15 | 10590 | otherops[2])) |
fdd695fd | 10591 | { |
5fd42423 | 10592 | rtx tmp; |
e6d29d15 NS |
10593 | /* Swap base and index registers over to |
10594 | avoid a conflict. */ | |
5fd42423 PB |
10595 | tmp = otherops[1]; |
10596 | otherops[1] = otherops[2]; | |
10597 | otherops[2] = tmp; | |
fdd695fd | 10598 | } |
e6d29d15 NS |
10599 | /* If both registers conflict, it will usually |
10600 | have been fixed by a splitter. */ | |
5fd42423 PB |
10601 | if (reg_overlap_mentioned_p (operands[0], otherops[2]) |
10602 | || (fix_cm3_ldrd && reg0 == REGNO (otherops[1]))) | |
fdd695fd | 10603 | { |
5fd42423 PB |
10604 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
10605 | output_asm_insn ("ldr%(d%)\t%0, [%1]", operands); | |
2b835d68 RE |
10606 | } |
10607 | else | |
5fd42423 PB |
10608 | { |
10609 | otherops[0] = operands[0]; | |
10610 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops); | |
10611 | } | |
e6d29d15 | 10612 | return ""; |
2b835d68 | 10613 | } |
e0b92319 | 10614 | |
e6d29d15 | 10615 | if (GET_CODE (otherops[2]) == CONST_INT) |
2b835d68 | 10616 | { |
e6d29d15 NS |
10617 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) |
10618 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
10619 | else | |
10620 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
2b835d68 RE |
10621 | } |
10622 | else | |
e6d29d15 NS |
10623 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
10624 | } | |
10625 | else | |
10626 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
10627 | ||
5dea0c19 | 10628 | if (TARGET_LDRD) |
5fd42423 | 10629 | return "ldr%(d%)\t%0, [%1]"; |
5dea0c19 | 10630 | |
5fd42423 | 10631 | return "ldm%(ia%)\t%1, %M0"; |
e6d29d15 NS |
10632 | } |
10633 | else | |
10634 | { | |
10635 | otherops[1] = adjust_address (operands[1], SImode, 4); | |
10636 | /* Take care of overlapping base/data reg. */ | |
10637 | if (reg_mentioned_p (operands[0], operands[1])) | |
10638 | { | |
10639 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
10640 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
10641 | } | |
10642 | else | |
10643 | { | |
10644 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
10645 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
cce8749e CH |
10646 | } |
10647 | } | |
10648 | } | |
cce8749e | 10649 | } |
e6d29d15 | 10650 | else |
cce8749e | 10651 | { |
e6d29d15 NS |
10652 | /* Constraints should ensure this. */ |
10653 | gcc_assert (code0 == MEM && code1 == REG); | |
10654 | gcc_assert (REGNO (operands[1]) != IP_REGNUM); | |
2b835d68 | 10655 | |
ff9940b0 RE |
10656 | switch (GET_CODE (XEXP (operands[0], 0))) |
10657 | { | |
10658 | case REG: | |
5dea0c19 PB |
10659 | if (TARGET_LDRD) |
10660 | output_asm_insn ("str%(d%)\t%1, [%m0]", operands); | |
10661 | else | |
10662 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
ff9940b0 | 10663 | break; |
2b835d68 | 10664 | |
ff9940b0 | 10665 | case PRE_INC: |
e6d29d15 | 10666 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 10667 | output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands); |
ff9940b0 | 10668 | break; |
2b835d68 | 10669 | |
ff9940b0 | 10670 | case PRE_DEC: |
5b3e6663 PB |
10671 | if (TARGET_LDRD) |
10672 | output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands); | |
10673 | else | |
10674 | output_asm_insn ("stm%(db%)\t%m0!, %M1", operands); | |
ff9940b0 | 10675 | break; |
2b835d68 | 10676 | |
ff9940b0 | 10677 | case POST_INC: |
5dea0c19 PB |
10678 | if (TARGET_LDRD) |
10679 | output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands); | |
10680 | else | |
10681 | output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands); | |
ff9940b0 | 10682 | break; |
2b835d68 | 10683 | |
ff9940b0 | 10684 | case POST_DEC: |
e6d29d15 | 10685 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 10686 | output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands); |
fdd695fd PB |
10687 | break; |
10688 | ||
10689 | case PRE_MODIFY: | |
10690 | case POST_MODIFY: | |
10691 | otherops[0] = operands[1]; | |
10692 | otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); | |
10693 | otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); | |
10694 | ||
fe2d934b PB |
10695 | /* IWMMXT allows offsets larger than ldrd can handle, |
10696 | fix these up with a pair of ldr. */ | |
ff128632 RE |
10697 | if (!TARGET_THUMB2 |
10698 | && GET_CODE (otherops[2]) == CONST_INT | |
fe2d934b PB |
10699 | && (INTVAL(otherops[2]) <= -256 |
10700 | || INTVAL(otherops[2]) >= 256)) | |
10701 | { | |
fe2d934b PB |
10702 | if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) |
10703 | { | |
10704 | output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | |
ff128632 | 10705 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
10706 | } |
10707 | else | |
10708 | { | |
ff128632 | 10709 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
10710 | output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); |
10711 | } | |
10712 | } | |
10713 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | |
5b3e6663 | 10714 | output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops); |
fdd695fd | 10715 | else |
5b3e6663 | 10716 | output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops); |
ff9940b0 | 10717 | break; |
2b835d68 RE |
10718 | |
10719 | case PLUS: | |
fdd695fd | 10720 | otherops[2] = XEXP (XEXP (operands[0], 0), 1); |
5dea0c19 | 10721 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 10722 | { |
06bea5aa | 10723 | switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) |
2b835d68 RE |
10724 | { |
10725 | case -8: | |
5b3e6663 | 10726 | output_asm_insn ("stm%(db%)\t%m0, %M1", operands); |
2b835d68 RE |
10727 | return ""; |
10728 | ||
10729 | case -4: | |
5b3e6663 PB |
10730 | if (TARGET_THUMB2) |
10731 | break; | |
10732 | output_asm_insn ("stm%(da%)\t%m0, %M1", operands); | |
2b835d68 RE |
10733 | return ""; |
10734 | ||
10735 | case 4: | |
5b3e6663 PB |
10736 | if (TARGET_THUMB2) |
10737 | break; | |
10738 | output_asm_insn ("stm%(ib%)\t%m0, %M1", operands); | |
2b835d68 RE |
10739 | return ""; |
10740 | } | |
10741 | } | |
fdd695fd PB |
10742 | if (TARGET_LDRD |
10743 | && (GET_CODE (otherops[2]) == REG | |
ff128632 | 10744 | || TARGET_THUMB2 |
fdd695fd PB |
10745 | || (GET_CODE (otherops[2]) == CONST_INT |
10746 | && INTVAL (otherops[2]) > -256 | |
10747 | && INTVAL (otherops[2]) < 256))) | |
10748 | { | |
10749 | otherops[0] = operands[1]; | |
10750 | otherops[1] = XEXP (XEXP (operands[0], 0), 0); | |
5b3e6663 | 10751 | output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops); |
fdd695fd PB |
10752 | return ""; |
10753 | } | |
2b835d68 RE |
10754 | /* Fall through */ |
10755 | ||
ff9940b0 | 10756 | default: |
a4a37b30 | 10757 | otherops[0] = adjust_address (operands[0], SImode, 4); |
ff128632 | 10758 | otherops[1] = operands[1]; |
9997d19d | 10759 | output_asm_insn ("str%?\t%1, %0", operands); |
ff128632 | 10760 | output_asm_insn ("str%?\t%H1, %0", otherops); |
cce8749e CH |
10761 | } |
10762 | } | |
cce8749e | 10763 | |
9997d19d RE |
10764 | return ""; |
10765 | } | |
cce8749e | 10766 | |
88f77cba JB |
10767 | /* Output a move, load or store for quad-word vectors in ARM registers. Only |
10768 | handles MEMs accepted by neon_vector_mem_operand with CORE=true. */ | |
5b3e6663 PB |
10769 | |
10770 | const char * | |
88f77cba | 10771 | output_move_quad (rtx *operands) |
5b3e6663 | 10772 | { |
88f77cba JB |
10773 | if (REG_P (operands[0])) |
10774 | { | |
10775 | /* Load, or reg->reg move. */ | |
5b3e6663 | 10776 | |
88f77cba JB |
10777 | if (MEM_P (operands[1])) |
10778 | { | |
10779 | switch (GET_CODE (XEXP (operands[1], 0))) | |
10780 | { | |
10781 | case REG: | |
10782 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
10783 | break; | |
10784 | ||
10785 | case LABEL_REF: | |
10786 | case CONST: | |
10787 | output_asm_insn ("adr%?\t%0, %1", operands); | |
10788 | output_asm_insn ("ldm%(ia%)\t%0, %M0", operands); | |
10789 | break; | |
10790 | ||
10791 | default: | |
10792 | gcc_unreachable (); | |
10793 | } | |
10794 | } | |
10795 | else | |
10796 | { | |
10797 | rtx ops[2]; | |
10798 | int dest, src, i; | |
5b3e6663 | 10799 | |
88f77cba | 10800 | gcc_assert (REG_P (operands[1])); |
5b3e6663 | 10801 | |
88f77cba JB |
10802 | dest = REGNO (operands[0]); |
10803 | src = REGNO (operands[1]); | |
5b3e6663 | 10804 | |
88f77cba JB |
10805 | /* This seems pretty dumb, but hopefully GCC won't try to do it |
10806 | very often. */ | |
10807 | if (dest < src) | |
10808 | for (i = 0; i < 4; i++) | |
10809 | { | |
10810 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
10811 | ops[1] = gen_rtx_REG (SImode, src + i); | |
10812 | output_asm_insn ("mov%?\t%0, %1", ops); | |
10813 | } | |
10814 | else | |
10815 | for (i = 3; i >= 0; i--) | |
10816 | { | |
10817 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
10818 | ops[1] = gen_rtx_REG (SImode, src + i); | |
10819 | output_asm_insn ("mov%?\t%0, %1", ops); | |
10820 | } | |
10821 | } | |
10822 | } | |
10823 | else | |
10824 | { | |
10825 | gcc_assert (MEM_P (operands[0])); | |
10826 | gcc_assert (REG_P (operands[1])); | |
10827 | gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0])); | |
10828 | ||
10829 | switch (GET_CODE (XEXP (operands[0], 0))) | |
10830 | { | |
10831 | case REG: | |
10832 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
10833 | break; | |
10834 | ||
10835 | default: | |
10836 | gcc_unreachable (); | |
10837 | } | |
10838 | } | |
10839 | ||
10840 | return ""; | |
10841 | } | |
10842 | ||
10843 | /* Output a VFP load or store instruction. */ | |
10844 | ||
10845 | const char * | |
10846 | output_move_vfp (rtx *operands) | |
10847 | { | |
10848 | rtx reg, mem, addr, ops[2]; | |
10849 | int load = REG_P (operands[0]); | |
10850 | int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8; | |
10851 | int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT; | |
0a2aaacc | 10852 | const char *templ; |
88f77cba JB |
10853 | char buff[50]; |
10854 | enum machine_mode mode; | |
10855 | ||
10856 | reg = operands[!load]; | |
10857 | mem = operands[load]; | |
10858 | ||
10859 | mode = GET_MODE (reg); | |
10860 | ||
10861 | gcc_assert (REG_P (reg)); | |
10862 | gcc_assert (IS_VFP_REGNUM (REGNO (reg))); | |
10863 | gcc_assert (mode == SFmode | |
10864 | || mode == DFmode | |
10865 | || mode == SImode | |
10866 | || mode == DImode | |
10867 | || (TARGET_NEON && VALID_NEON_DREG_MODE (mode))); | |
10868 | gcc_assert (MEM_P (mem)); | |
10869 | ||
10870 | addr = XEXP (mem, 0); | |
10871 | ||
10872 | switch (GET_CODE (addr)) | |
10873 | { | |
10874 | case PRE_DEC: | |
0a2aaacc | 10875 | templ = "f%smdb%c%%?\t%%0!, {%%%s1}%s"; |
88f77cba JB |
10876 | ops[0] = XEXP (addr, 0); |
10877 | ops[1] = reg; | |
5b3e6663 PB |
10878 | break; |
10879 | ||
10880 | case POST_INC: | |
0a2aaacc | 10881 | templ = "f%smia%c%%?\t%%0!, {%%%s1}%s"; |
5b3e6663 PB |
10882 | ops[0] = XEXP (addr, 0); |
10883 | ops[1] = reg; | |
10884 | break; | |
10885 | ||
10886 | default: | |
0a2aaacc | 10887 | templ = "f%s%c%%?\t%%%s0, %%1%s"; |
5b3e6663 PB |
10888 | ops[0] = reg; |
10889 | ops[1] = mem; | |
10890 | break; | |
10891 | } | |
10892 | ||
0a2aaacc | 10893 | sprintf (buff, templ, |
5b3e6663 PB |
10894 | load ? "ld" : "st", |
10895 | dp ? 'd' : 's', | |
10896 | dp ? "P" : "", | |
10897 | integer_p ? "\t%@ int" : ""); | |
10898 | output_asm_insn (buff, ops); | |
10899 | ||
10900 | return ""; | |
10901 | } | |
10902 | ||
88f77cba | 10903 | /* Output a Neon quad-word load or store, or a load or store for |
874d42b9 | 10904 | larger structure modes. |
88f77cba | 10905 | |
874d42b9 JM |
10906 | WARNING: The ordering of elements is weird in big-endian mode, |
10907 | because we use VSTM, as required by the EABI. GCC RTL defines | |
10908 | element ordering based on in-memory order. This can be differ | |
10909 | from the architectural ordering of elements within a NEON register. | |
10910 | The intrinsics defined in arm_neon.h use the NEON register element | |
10911 | ordering, not the GCC RTL element ordering. | |
88f77cba | 10912 | |
874d42b9 JM |
10913 | For example, the in-memory ordering of a big-endian a quadword |
10914 | vector with 16-bit elements when stored from register pair {d0,d1} | |
10915 | will be (lowest address first, d0[N] is NEON register element N): | |
88f77cba | 10916 | |
874d42b9 | 10917 | [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]] |
88f77cba | 10918 | |
874d42b9 JM |
10919 | When necessary, quadword registers (dN, dN+1) are moved to ARM |
10920 | registers from rN in the order: | |
88f77cba JB |
10921 | |
10922 | dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2) | |
10923 | ||
874d42b9 JM |
10924 | So that STM/LDM can be used on vectors in ARM registers, and the |
10925 | same memory layout will result as if VSTM/VLDM were used. */ | |
88f77cba JB |
10926 | |
10927 | const char * | |
10928 | output_move_neon (rtx *operands) | |
10929 | { | |
10930 | rtx reg, mem, addr, ops[2]; | |
10931 | int regno, load = REG_P (operands[0]); | |
0a2aaacc | 10932 | const char *templ; |
88f77cba JB |
10933 | char buff[50]; |
10934 | enum machine_mode mode; | |
10935 | ||
10936 | reg = operands[!load]; | |
10937 | mem = operands[load]; | |
10938 | ||
10939 | mode = GET_MODE (reg); | |
10940 | ||
10941 | gcc_assert (REG_P (reg)); | |
10942 | regno = REGNO (reg); | |
10943 | gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno) | |
10944 | || NEON_REGNO_OK_FOR_QUAD (regno)); | |
10945 | gcc_assert (VALID_NEON_DREG_MODE (mode) | |
10946 | || VALID_NEON_QREG_MODE (mode) | |
10947 | || VALID_NEON_STRUCT_MODE (mode)); | |
10948 | gcc_assert (MEM_P (mem)); | |
10949 | ||
10950 | addr = XEXP (mem, 0); | |
10951 | ||
10952 | /* Strip off const from addresses like (const (plus (...))). */ | |
10953 | if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS) | |
10954 | addr = XEXP (addr, 0); | |
10955 | ||
10956 | switch (GET_CODE (addr)) | |
10957 | { | |
10958 | case POST_INC: | |
0a2aaacc | 10959 | templ = "v%smia%%?\t%%0!, %%h1"; |
88f77cba JB |
10960 | ops[0] = XEXP (addr, 0); |
10961 | ops[1] = reg; | |
10962 | break; | |
10963 | ||
10964 | case POST_MODIFY: | |
10965 | /* FIXME: Not currently enabled in neon_vector_mem_operand. */ | |
10966 | gcc_unreachable (); | |
10967 | ||
10968 | case LABEL_REF: | |
10969 | case PLUS: | |
10970 | { | |
10971 | int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2; | |
10972 | int i; | |
10973 | int overlap = -1; | |
10974 | for (i = 0; i < nregs; i++) | |
10975 | { | |
10976 | /* We're only using DImode here because it's a convenient size. */ | |
10977 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); | |
10978 | ops[1] = adjust_address (mem, SImode, 8 * i); | |
10979 | if (reg_overlap_mentioned_p (ops[0], mem)) | |
10980 | { | |
10981 | gcc_assert (overlap == -1); | |
10982 | overlap = i; | |
10983 | } | |
10984 | else | |
10985 | { | |
10986 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
10987 | output_asm_insn (buff, ops); | |
10988 | } | |
10989 | } | |
10990 | if (overlap != -1) | |
10991 | { | |
10992 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap); | |
10993 | ops[1] = adjust_address (mem, SImode, 8 * overlap); | |
10994 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
10995 | output_asm_insn (buff, ops); | |
10996 | } | |
10997 | ||
10998 | return ""; | |
10999 | } | |
11000 | ||
11001 | default: | |
0a2aaacc | 11002 | templ = "v%smia%%?\t%%m0, %%h1"; |
88f77cba JB |
11003 | ops[0] = mem; |
11004 | ops[1] = reg; | |
11005 | } | |
11006 | ||
0a2aaacc | 11007 | sprintf (buff, templ, load ? "ld" : "st"); |
88f77cba JB |
11008 | output_asm_insn (buff, ops); |
11009 | ||
11010 | return ""; | |
11011 | } | |
11012 | ||
1d6e90ac NC |
11013 | /* Output an ADD r, s, #n where n may be too big for one instruction. |
11014 | If adding zero to one register, output nothing. */ | |
cd2b33d0 | 11015 | const char * |
e32bac5b | 11016 | output_add_immediate (rtx *operands) |
cce8749e | 11017 | { |
f3bb6135 | 11018 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
11019 | |
11020 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
11021 | { | |
11022 | if (n < 0) | |
11023 | output_multi_immediate (operands, | |
9997d19d RE |
11024 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
11025 | -n); | |
cce8749e CH |
11026 | else |
11027 | output_multi_immediate (operands, | |
9997d19d RE |
11028 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
11029 | n); | |
cce8749e | 11030 | } |
f3bb6135 RE |
11031 | |
11032 | return ""; | |
11033 | } | |
cce8749e | 11034 | |
cce8749e CH |
11035 | /* Output a multiple immediate operation. |
11036 | OPERANDS is the vector of operands referred to in the output patterns. | |
11037 | INSTR1 is the output pattern to use for the first constant. | |
11038 | INSTR2 is the output pattern to use for subsequent constants. | |
11039 | IMMED_OP is the index of the constant slot in OPERANDS. | |
11040 | N is the constant value. */ | |
cd2b33d0 | 11041 | static const char * |
e32bac5b RE |
11042 | output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, |
11043 | int immed_op, HOST_WIDE_INT n) | |
cce8749e | 11044 | { |
f3bb6135 | 11045 | #if HOST_BITS_PER_WIDE_INT > 32 |
30cf4896 | 11046 | n &= 0xffffffff; |
f3bb6135 RE |
11047 | #endif |
11048 | ||
cce8749e CH |
11049 | if (n == 0) |
11050 | { | |
1d6e90ac | 11051 | /* Quick and easy output. */ |
cce8749e | 11052 | operands[immed_op] = const0_rtx; |
1d6e90ac | 11053 | output_asm_insn (instr1, operands); |
cce8749e CH |
11054 | } |
11055 | else | |
11056 | { | |
11057 | int i; | |
cd2b33d0 | 11058 | const char * instr = instr1; |
cce8749e | 11059 | |
6354dc9b | 11060 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
11061 | for (i = 0; i < 32; i += 2) |
11062 | { | |
11063 | if (n & (3 << i)) | |
11064 | { | |
f3bb6135 RE |
11065 | operands[immed_op] = GEN_INT (n & (255 << i)); |
11066 | output_asm_insn (instr, operands); | |
cce8749e CH |
11067 | instr = instr2; |
11068 | i += 6; | |
11069 | } | |
11070 | } | |
11071 | } | |
f676971a | 11072 | |
f3bb6135 | 11073 | return ""; |
9997d19d | 11074 | } |
cce8749e | 11075 | |
5b3e6663 PB |
11076 | /* Return the name of a shifter operation. */ |
11077 | static const char * | |
11078 | arm_shift_nmem(enum rtx_code code) | |
11079 | { | |
11080 | switch (code) | |
11081 | { | |
11082 | case ASHIFT: | |
11083 | return ARM_LSL_NAME; | |
11084 | ||
11085 | case ASHIFTRT: | |
11086 | return "asr"; | |
11087 | ||
11088 | case LSHIFTRT: | |
11089 | return "lsr"; | |
11090 | ||
11091 | case ROTATERT: | |
11092 | return "ror"; | |
11093 | ||
11094 | default: | |
11095 | abort(); | |
11096 | } | |
11097 | } | |
11098 | ||
cce8749e CH |
11099 | /* Return the appropriate ARM instruction for the operation code. |
11100 | The returned result should not be overwritten. OP is the rtx of the | |
11101 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
11102 | was shifted. */ | |
cd2b33d0 | 11103 | const char * |
e32bac5b | 11104 | arithmetic_instr (rtx op, int shift_first_arg) |
cce8749e | 11105 | { |
9997d19d | 11106 | switch (GET_CODE (op)) |
cce8749e CH |
11107 | { |
11108 | case PLUS: | |
f3bb6135 RE |
11109 | return "add"; |
11110 | ||
cce8749e | 11111 | case MINUS: |
f3bb6135 RE |
11112 | return shift_first_arg ? "rsb" : "sub"; |
11113 | ||
cce8749e | 11114 | case IOR: |
f3bb6135 RE |
11115 | return "orr"; |
11116 | ||
cce8749e | 11117 | case XOR: |
f3bb6135 RE |
11118 | return "eor"; |
11119 | ||
cce8749e | 11120 | case AND: |
f3bb6135 RE |
11121 | return "and"; |
11122 | ||
5b3e6663 PB |
11123 | case ASHIFT: |
11124 | case ASHIFTRT: | |
11125 | case LSHIFTRT: | |
11126 | case ROTATERT: | |
11127 | return arm_shift_nmem(GET_CODE(op)); | |
11128 | ||
cce8749e | 11129 | default: |
e6d29d15 | 11130 | gcc_unreachable (); |
cce8749e | 11131 | } |
f3bb6135 | 11132 | } |
cce8749e | 11133 | |
cce8749e CH |
11134 | /* Ensure valid constant shifts and return the appropriate shift mnemonic |
11135 | for the operation code. The returned result should not be overwritten. | |
11136 | OP is the rtx code of the shift. | |
9997d19d | 11137 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 11138 | shift. */ |
cd2b33d0 | 11139 | static const char * |
e32bac5b | 11140 | shift_op (rtx op, HOST_WIDE_INT *amountp) |
cce8749e | 11141 | { |
cd2b33d0 | 11142 | const char * mnem; |
e2c671ba | 11143 | enum rtx_code code = GET_CODE (op); |
cce8749e | 11144 | |
e6d29d15 NS |
11145 | switch (GET_CODE (XEXP (op, 1))) |
11146 | { | |
11147 | case REG: | |
11148 | case SUBREG: | |
11149 | *amountp = -1; | |
11150 | break; | |
11151 | ||
11152 | case CONST_INT: | |
11153 | *amountp = INTVAL (XEXP (op, 1)); | |
11154 | break; | |
11155 | ||
11156 | default: | |
11157 | gcc_unreachable (); | |
11158 | } | |
9997d19d | 11159 | |
e2c671ba | 11160 | switch (code) |
cce8749e | 11161 | { |
a657c98a | 11162 | case ROTATE: |
e6d29d15 | 11163 | gcc_assert (*amountp != -1); |
a657c98a | 11164 | *amountp = 32 - *amountp; |
5b3e6663 | 11165 | code = ROTATERT; |
a657c98a RE |
11166 | |
11167 | /* Fall through. */ | |
11168 | ||
5b3e6663 PB |
11169 | case ASHIFT: |
11170 | case ASHIFTRT: | |
11171 | case LSHIFTRT: | |
9997d19d | 11172 | case ROTATERT: |
5b3e6663 | 11173 | mnem = arm_shift_nmem(code); |
9997d19d RE |
11174 | break; |
11175 | ||
ff9940b0 | 11176 | case MULT: |
e2c671ba RE |
11177 | /* We never have to worry about the amount being other than a |
11178 | power of 2, since this case can never be reloaded from a reg. */ | |
e6d29d15 NS |
11179 | gcc_assert (*amountp != -1); |
11180 | *amountp = int_log2 (*amountp); | |
5b3e6663 | 11181 | return ARM_LSL_NAME; |
f3bb6135 | 11182 | |
cce8749e | 11183 | default: |
e6d29d15 | 11184 | gcc_unreachable (); |
cce8749e CH |
11185 | } |
11186 | ||
e2c671ba RE |
11187 | if (*amountp != -1) |
11188 | { | |
11189 | /* This is not 100% correct, but follows from the desire to merge | |
11190 | multiplication by a power of 2 with the recognizer for a | |
5b3e6663 | 11191 | shift. >=32 is not a valid shift for "lsl", so we must try and |
e2c671ba | 11192 | output a shift that produces the correct arithmetical result. |
ddd5a7c1 | 11193 | Using lsr #32 is identical except for the fact that the carry bit |
f676971a | 11194 | is not set correctly if we set the flags; but we never use the |
e2c671ba RE |
11195 | carry bit from such an operation, so we can ignore that. */ |
11196 | if (code == ROTATERT) | |
1d6e90ac NC |
11197 | /* Rotate is just modulo 32. */ |
11198 | *amountp &= 31; | |
e2c671ba RE |
11199 | else if (*amountp != (*amountp & 31)) |
11200 | { | |
11201 | if (code == ASHIFT) | |
11202 | mnem = "lsr"; | |
11203 | *amountp = 32; | |
11204 | } | |
11205 | ||
11206 | /* Shifts of 0 are no-ops. */ | |
11207 | if (*amountp == 0) | |
11208 | return NULL; | |
f676971a | 11209 | } |
e2c671ba | 11210 | |
9997d19d RE |
11211 | return mnem; |
11212 | } | |
cce8749e | 11213 | |
6354dc9b | 11214 | /* Obtain the shift from the POWER of two. */ |
1d6e90ac | 11215 | |
18af7313 | 11216 | static HOST_WIDE_INT |
e32bac5b | 11217 | int_log2 (HOST_WIDE_INT power) |
cce8749e | 11218 | { |
f3bb6135 | 11219 | HOST_WIDE_INT shift = 0; |
cce8749e | 11220 | |
30cf4896 | 11221 | while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) |
cce8749e | 11222 | { |
e6d29d15 | 11223 | gcc_assert (shift <= 31); |
e32bac5b | 11224 | shift++; |
cce8749e | 11225 | } |
f3bb6135 RE |
11226 | |
11227 | return shift; | |
11228 | } | |
cce8749e | 11229 | |
c5ff069d ZW |
11230 | /* Output a .ascii pseudo-op, keeping track of lengths. This is |
11231 | because /bin/as is horribly restrictive. The judgement about | |
11232 | whether or not each character is 'printable' (and can be output as | |
11233 | is) or not (and must be printed with an octal escape) must be made | |
11234 | with reference to the *host* character set -- the situation is | |
11235 | similar to that discussed in the comments above pp_c_char in | |
11236 | c-pretty-print.c. */ | |
11237 | ||
6cfc7210 | 11238 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
11239 | |
11240 | void | |
e32bac5b | 11241 | output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) |
cce8749e CH |
11242 | { |
11243 | int i; | |
6cfc7210 | 11244 | int len_so_far = 0; |
cce8749e | 11245 | |
6cfc7210 | 11246 | fputs ("\t.ascii\t\"", stream); |
f676971a | 11247 | |
cce8749e CH |
11248 | for (i = 0; i < len; i++) |
11249 | { | |
1d6e90ac | 11250 | int c = p[i]; |
cce8749e | 11251 | |
6cfc7210 | 11252 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 11253 | { |
6cfc7210 | 11254 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 11255 | len_so_far = 0; |
cce8749e CH |
11256 | } |
11257 | ||
c5ff069d | 11258 | if (ISPRINT (c)) |
cce8749e | 11259 | { |
c5ff069d | 11260 | if (c == '\\' || c == '\"') |
6cfc7210 | 11261 | { |
c5ff069d | 11262 | putc ('\\', stream); |
5895f793 | 11263 | len_so_far++; |
6cfc7210 | 11264 | } |
c5ff069d ZW |
11265 | putc (c, stream); |
11266 | len_so_far++; | |
11267 | } | |
11268 | else | |
11269 | { | |
11270 | fprintf (stream, "\\%03o", c); | |
11271 | len_so_far += 4; | |
cce8749e | 11272 | } |
cce8749e | 11273 | } |
f3bb6135 | 11274 | |
cce8749e | 11275 | fputs ("\"\n", stream); |
f3bb6135 | 11276 | } |
cce8749e | 11277 | \f |
c9ca9b88 | 11278 | /* Compute the register save mask for registers 0 through 12 |
5848830f | 11279 | inclusive. This code is used by arm_compute_save_reg_mask. */ |
b279b20a | 11280 | |
6d3d9133 | 11281 | static unsigned long |
e32bac5b | 11282 | arm_compute_save_reg0_reg12_mask (void) |
6d3d9133 | 11283 | { |
121308d4 | 11284 | unsigned long func_type = arm_current_func_type (); |
b279b20a | 11285 | unsigned long save_reg_mask = 0; |
6d3d9133 | 11286 | unsigned int reg; |
6d3d9133 | 11287 | |
7b8b8ade | 11288 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 11289 | { |
7b8b8ade | 11290 | unsigned int max_reg; |
7b8b8ade NC |
11291 | /* Interrupt functions must not corrupt any registers, |
11292 | even call clobbered ones. If this is a leaf function | |
11293 | we can just examine the registers used by the RTL, but | |
11294 | otherwise we have to assume that whatever function is | |
11295 | called might clobber anything, and so we have to save | |
11296 | all the call-clobbered registers as well. */ | |
11297 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
11298 | /* FIQ handlers have registers r8 - r12 banked, so | |
11299 | we only need to check r0 - r7, Normal ISRs only | |
121308d4 | 11300 | bank r14 and r15, so we must check up to r12. |
7b8b8ade NC |
11301 | r13 is the stack pointer which is always preserved, |
11302 | so we do not need to consider it here. */ | |
11303 | max_reg = 7; | |
11304 | else | |
11305 | max_reg = 12; | |
f676971a | 11306 | |
7b8b8ade | 11307 | for (reg = 0; reg <= max_reg; reg++) |
6fb5fa3c DB |
11308 | if (df_regs_ever_live_p (reg) |
11309 | || (! current_function_is_leaf && call_used_regs[reg])) | |
6d3d9133 | 11310 | save_reg_mask |= (1 << reg); |
cfa01aab | 11311 | |
286d28c3 | 11312 | /* Also save the pic base register if necessary. */ |
cfa01aab PB |
11313 | if (flag_pic |
11314 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 11315 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 11316 | && crtl->uses_pic_offset_table) |
cfa01aab | 11317 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
6d3d9133 NC |
11318 | } |
11319 | else | |
11320 | { | |
11321 | /* In the normal case we only need to save those registers | |
11322 | which are call saved and which are used by this function. */ | |
ec6237e4 | 11323 | for (reg = 0; reg <= 11; reg++) |
6fb5fa3c | 11324 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
6d3d9133 NC |
11325 | save_reg_mask |= (1 << reg); |
11326 | ||
11327 | /* Handle the frame pointer as a special case. */ | |
ec6237e4 | 11328 | if (frame_pointer_needed) |
6d3d9133 NC |
11329 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; |
11330 | ||
11331 | /* If we aren't loading the PIC register, | |
11332 | don't stack it even though it may be live. */ | |
11333 | if (flag_pic | |
e0b92319 | 11334 | && !TARGET_SINGLE_PIC_BASE |
020a4035 | 11335 | && arm_pic_register != INVALID_REGNUM |
6fb5fa3c | 11336 | && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM) |
e3b5732b | 11337 | || crtl->uses_pic_offset_table)) |
6d3d9133 | 11338 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
5b3e6663 PB |
11339 | |
11340 | /* The prologue will copy SP into R0, so save it. */ | |
11341 | if (IS_STACKALIGN (func_type)) | |
11342 | save_reg_mask |= 1; | |
6d3d9133 NC |
11343 | } |
11344 | ||
c9ca9b88 | 11345 | /* Save registers so the exception handler can modify them. */ |
e3b5732b | 11346 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
11347 | { |
11348 | unsigned int i; | |
f676971a | 11349 | |
c9ca9b88 PB |
11350 | for (i = 0; ; i++) |
11351 | { | |
11352 | reg = EH_RETURN_DATA_REGNO (i); | |
11353 | if (reg == INVALID_REGNUM) | |
11354 | break; | |
11355 | save_reg_mask |= 1 << reg; | |
11356 | } | |
11357 | } | |
11358 | ||
121308d4 NC |
11359 | return save_reg_mask; |
11360 | } | |
11361 | ||
5b3e6663 | 11362 | |
35596784 AJ |
11363 | /* Compute the number of bytes used to store the static chain register on the |
11364 | stack, above the stack frame. We need to know this accurately to get the | |
11365 | alignment of the rest of the stack frame correct. */ | |
11366 | ||
11367 | static int arm_compute_static_chain_stack_bytes (void) | |
11368 | { | |
11369 | unsigned long func_type = arm_current_func_type (); | |
11370 | int static_chain_stack_bytes = 0; | |
11371 | ||
11372 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM && | |
11373 | IS_NESTED (func_type) && | |
11374 | df_regs_ever_live_p (3) && crtl->args.pretend_args_size == 0) | |
11375 | static_chain_stack_bytes = 4; | |
11376 | ||
11377 | return static_chain_stack_bytes; | |
11378 | } | |
11379 | ||
11380 | ||
121308d4 | 11381 | /* Compute a bit mask of which registers need to be |
954954d1 PB |
11382 | saved on the stack for the current function. |
11383 | This is used by arm_get_frame_offsets, which may add extra registers. */ | |
121308d4 NC |
11384 | |
11385 | static unsigned long | |
e32bac5b | 11386 | arm_compute_save_reg_mask (void) |
121308d4 NC |
11387 | { |
11388 | unsigned int save_reg_mask = 0; | |
11389 | unsigned long func_type = arm_current_func_type (); | |
5b3e6663 | 11390 | unsigned int reg; |
121308d4 NC |
11391 | |
11392 | if (IS_NAKED (func_type)) | |
11393 | /* This should never really happen. */ | |
11394 | return 0; | |
11395 | ||
11396 | /* If we are creating a stack frame, then we must save the frame pointer, | |
11397 | IP (which will hold the old stack pointer), LR and the PC. */ | |
ec6237e4 | 11398 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
121308d4 NC |
11399 | save_reg_mask |= |
11400 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
11401 | | (1 << IP_REGNUM) | |
11402 | | (1 << LR_REGNUM) | |
11403 | | (1 << PC_REGNUM); | |
11404 | ||
11405 | /* Volatile functions do not return, so there | |
11406 | is no need to save any other registers. */ | |
11407 | if (IS_VOLATILE (func_type)) | |
11408 | return save_reg_mask; | |
11409 | ||
11410 | save_reg_mask |= arm_compute_save_reg0_reg12_mask (); | |
11411 | ||
6d3d9133 NC |
11412 | /* Decide if we need to save the link register. |
11413 | Interrupt routines have their own banked link register, | |
11414 | so they never need to save it. | |
1768c26f | 11415 | Otherwise if we do not use the link register we do not need to save |
6d3d9133 NC |
11416 | it. If we are pushing other registers onto the stack however, we |
11417 | can save an instruction in the epilogue by pushing the link register | |
11418 | now and then popping it back into the PC. This incurs extra memory | |
72ac76be | 11419 | accesses though, so we only do it when optimizing for size, and only |
6d3d9133 | 11420 | if we know that we will not need a fancy return sequence. */ |
6fb5fa3c DB |
11421 | if (df_regs_ever_live_p (LR_REGNUM) |
11422 | || (save_reg_mask | |
11423 | && optimize_size | |
11424 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 11425 | && !crtl->calls_eh_return)) |
6d3d9133 NC |
11426 | save_reg_mask |= 1 << LR_REGNUM; |
11427 | ||
6f7ebcbb NC |
11428 | if (cfun->machine->lr_save_eliminated) |
11429 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
11430 | ||
5a9335ef NC |
11431 | if (TARGET_REALLY_IWMMXT |
11432 | && ((bit_count (save_reg_mask) | |
35596784 AJ |
11433 | + ARM_NUM_INTS (crtl->args.pretend_args_size + |
11434 | arm_compute_static_chain_stack_bytes()) | |
11435 | ) % 2) != 0) | |
5a9335ef | 11436 | { |
5a9335ef NC |
11437 | /* The total number of registers that are going to be pushed |
11438 | onto the stack is odd. We need to ensure that the stack | |
11439 | is 64-bit aligned before we start to save iWMMXt registers, | |
11440 | and also before we start to create locals. (A local variable | |
11441 | might be a double or long long which we will load/store using | |
11442 | an iWMMXt instruction). Therefore we need to push another | |
11443 | ARM register, so that the stack will be 64-bit aligned. We | |
11444 | try to avoid using the arg registers (r0 -r3) as they might be | |
11445 | used to pass values in a tail call. */ | |
11446 | for (reg = 4; reg <= 12; reg++) | |
11447 | if ((save_reg_mask & (1 << reg)) == 0) | |
11448 | break; | |
11449 | ||
11450 | if (reg <= 12) | |
11451 | save_reg_mask |= (1 << reg); | |
11452 | else | |
11453 | { | |
11454 | cfun->machine->sibcall_blocked = 1; | |
11455 | save_reg_mask |= (1 << 3); | |
11456 | } | |
11457 | } | |
11458 | ||
5b3e6663 PB |
11459 | /* We may need to push an additional register for use initializing the |
11460 | PIC base register. */ | |
11461 | if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic | |
11462 | && (save_reg_mask & THUMB2_WORK_REGS) == 0) | |
11463 | { | |
11464 | reg = thumb_find_work_register (1 << 4); | |
11465 | if (!call_used_regs[reg]) | |
11466 | save_reg_mask |= (1 << reg); | |
11467 | } | |
11468 | ||
6d3d9133 NC |
11469 | return save_reg_mask; |
11470 | } | |
11471 | ||
9728c9d1 | 11472 | |
57934c39 PB |
11473 | /* Compute a bit mask of which registers need to be |
11474 | saved on the stack for the current function. */ | |
11475 | static unsigned long | |
5b3e6663 | 11476 | thumb1_compute_save_reg_mask (void) |
57934c39 PB |
11477 | { |
11478 | unsigned long mask; | |
b279b20a | 11479 | unsigned reg; |
57934c39 PB |
11480 | |
11481 | mask = 0; | |
11482 | for (reg = 0; reg < 12; reg ++) | |
6fb5fa3c | 11483 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b279b20a | 11484 | mask |= 1 << reg; |
57934c39 | 11485 | |
39c39be0 RE |
11486 | if (flag_pic |
11487 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 11488 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 11489 | && crtl->uses_pic_offset_table) |
39c39be0 | 11490 | mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
b279b20a | 11491 | |
a2503645 RS |
11492 | /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */ |
11493 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) | |
11494 | mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; | |
57934c39 | 11495 | |
b279b20a | 11496 | /* LR will also be pushed if any lo regs are pushed. */ |
57934c39 PB |
11497 | if (mask & 0xff || thumb_force_lr_save ()) |
11498 | mask |= (1 << LR_REGNUM); | |
11499 | ||
b279b20a NC |
11500 | /* Make sure we have a low work register if we need one. |
11501 | We will need one if we are going to push a high register, | |
11502 | but we are not currently intending to push a low register. */ | |
11503 | if ((mask & 0xff) == 0 | |
57934c39 | 11504 | && ((mask & 0x0f00) || TARGET_BACKTRACE)) |
b279b20a NC |
11505 | { |
11506 | /* Use thumb_find_work_register to choose which register | |
11507 | we will use. If the register is live then we will | |
11508 | have to push it. Use LAST_LO_REGNUM as our fallback | |
11509 | choice for the register to select. */ | |
11510 | reg = thumb_find_work_register (1 << LAST_LO_REGNUM); | |
19e723f4 PB |
11511 | /* Make sure the register returned by thumb_find_work_register is |
11512 | not part of the return value. */ | |
954954d1 | 11513 | if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ()) |
19e723f4 | 11514 | reg = LAST_LO_REGNUM; |
b279b20a NC |
11515 | |
11516 | if (! call_used_regs[reg]) | |
11517 | mask |= 1 << reg; | |
11518 | } | |
57934c39 | 11519 | |
35596784 AJ |
11520 | /* The 504 below is 8 bytes less than 512 because there are two possible |
11521 | alignment words. We can't tell here if they will be present or not so we | |
11522 | have to play it safe and assume that they are. */ | |
11523 | if ((CALLER_INTERWORKING_SLOT_SIZE + | |
11524 | ROUND_UP_WORD (get_frame_size ()) + | |
11525 | crtl->outgoing_args_size) >= 504) | |
11526 | { | |
11527 | /* This is the same as the code in thumb1_expand_prologue() which | |
11528 | determines which register to use for stack decrement. */ | |
11529 | for (reg = LAST_ARG_REGNUM + 1; reg <= LAST_LO_REGNUM; reg++) | |
11530 | if (mask & (1 << reg)) | |
11531 | break; | |
11532 | ||
11533 | if (reg > LAST_LO_REGNUM) | |
11534 | { | |
11535 | /* Make sure we have a register available for stack decrement. */ | |
11536 | mask |= 1 << LAST_LO_REGNUM; | |
11537 | } | |
11538 | } | |
11539 | ||
57934c39 PB |
11540 | return mask; |
11541 | } | |
11542 | ||
11543 | ||
9728c9d1 PB |
11544 | /* Return the number of bytes required to save VFP registers. */ |
11545 | static int | |
11546 | arm_get_vfp_saved_size (void) | |
11547 | { | |
11548 | unsigned int regno; | |
11549 | int count; | |
11550 | int saved; | |
11551 | ||
11552 | saved = 0; | |
11553 | /* Space for saved VFP registers. */ | |
11554 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
11555 | { | |
11556 | count = 0; | |
11557 | for (regno = FIRST_VFP_REGNUM; | |
11558 | regno < LAST_VFP_REGNUM; | |
11559 | regno += 2) | |
11560 | { | |
6fb5fa3c DB |
11561 | if ((!df_regs_ever_live_p (regno) || call_used_regs[regno]) |
11562 | && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1])) | |
9728c9d1 PB |
11563 | { |
11564 | if (count > 0) | |
11565 | { | |
11566 | /* Workaround ARM10 VFPr1 bug. */ | |
11567 | if (count == 2 && !arm_arch6) | |
11568 | count++; | |
8edfc4cc | 11569 | saved += count * 8; |
9728c9d1 PB |
11570 | } |
11571 | count = 0; | |
11572 | } | |
11573 | else | |
11574 | count++; | |
11575 | } | |
11576 | if (count > 0) | |
11577 | { | |
11578 | if (count == 2 && !arm_arch6) | |
11579 | count++; | |
8edfc4cc | 11580 | saved += count * 8; |
9728c9d1 PB |
11581 | } |
11582 | } | |
11583 | return saved; | |
11584 | } | |
11585 | ||
11586 | ||
699a4925 | 11587 | /* Generate a function exit sequence. If REALLY_RETURN is false, then do |
6d3d9133 | 11588 | everything bar the final return instruction. */ |
cd2b33d0 | 11589 | const char * |
e32bac5b | 11590 | output_return_instruction (rtx operand, int really_return, int reverse) |
ff9940b0 | 11591 | { |
6d3d9133 | 11592 | char conditional[10]; |
ff9940b0 | 11593 | char instr[100]; |
b279b20a | 11594 | unsigned reg; |
6d3d9133 NC |
11595 | unsigned long live_regs_mask; |
11596 | unsigned long func_type; | |
5848830f | 11597 | arm_stack_offsets *offsets; |
e26053d1 | 11598 | |
6d3d9133 | 11599 | func_type = arm_current_func_type (); |
e2c671ba | 11600 | |
6d3d9133 | 11601 | if (IS_NAKED (func_type)) |
d5b7b3ae | 11602 | return ""; |
6d3d9133 NC |
11603 | |
11604 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 11605 | { |
699a4925 RE |
11606 | /* If this function was declared non-returning, and we have |
11607 | found a tail call, then we have to trust that the called | |
11608 | function won't return. */ | |
3a5a4282 PB |
11609 | if (really_return) |
11610 | { | |
11611 | rtx ops[2]; | |
f676971a | 11612 | |
3a5a4282 PB |
11613 | /* Otherwise, trap an attempted return by aborting. */ |
11614 | ops[0] = operand; | |
f676971a | 11615 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" |
3a5a4282 PB |
11616 | : "abort"); |
11617 | assemble_external_libcall (ops[1]); | |
11618 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
11619 | } | |
f676971a | 11620 | |
e2c671ba RE |
11621 | return ""; |
11622 | } | |
6d3d9133 | 11623 | |
e3b5732b | 11624 | gcc_assert (!cfun->calls_alloca || really_return); |
ff9940b0 | 11625 | |
c414f8a9 | 11626 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); |
d5b7b3ae | 11627 | |
934c2060 | 11628 | cfun->machine->return_used_this_function = 1; |
ff9940b0 | 11629 | |
954954d1 PB |
11630 | offsets = arm_get_frame_offsets (); |
11631 | live_regs_mask = offsets->saved_regs_mask; | |
ff9940b0 | 11632 | |
1768c26f | 11633 | if (live_regs_mask) |
6d3d9133 | 11634 | { |
1768c26f PB |
11635 | const char * return_reg; |
11636 | ||
f676971a | 11637 | /* If we do not have any special requirements for function exit |
a15908a4 | 11638 | (e.g. interworking) then we can load the return address |
1768c26f PB |
11639 | directly into the PC. Otherwise we must load it into LR. */ |
11640 | if (really_return | |
a15908a4 | 11641 | && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK)) |
1768c26f | 11642 | return_reg = reg_names[PC_REGNUM]; |
6d3d9133 | 11643 | else |
1768c26f PB |
11644 | return_reg = reg_names[LR_REGNUM]; |
11645 | ||
6d3d9133 | 11646 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) |
b034930f ILT |
11647 | { |
11648 | /* There are three possible reasons for the IP register | |
11649 | being saved. 1) a stack frame was created, in which case | |
11650 | IP contains the old stack pointer, or 2) an ISR routine | |
11651 | corrupted it, or 3) it was saved to align the stack on | |
11652 | iWMMXt. In case 1, restore IP into SP, otherwise just | |
11653 | restore IP. */ | |
11654 | if (frame_pointer_needed) | |
11655 | { | |
11656 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
11657 | live_regs_mask |= (1 << SP_REGNUM); | |
11658 | } | |
11659 | else | |
e6d29d15 | 11660 | gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); |
b034930f | 11661 | } |
f3bb6135 | 11662 | |
3a7731fd PB |
11663 | /* On some ARM architectures it is faster to use LDR rather than |
11664 | LDM to load a single register. On other architectures, the | |
11665 | cost is the same. In 26 bit mode, or for exception handlers, | |
11666 | we have to use LDM to load the PC so that the CPSR is also | |
11667 | restored. */ | |
11668 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) | |
b279b20a NC |
11669 | if (live_regs_mask == (1U << reg)) |
11670 | break; | |
11671 | ||
3a7731fd PB |
11672 | if (reg <= LAST_ARM_REGNUM |
11673 | && (reg != LR_REGNUM | |
f676971a | 11674 | || ! really_return |
61f0ccff | 11675 | || ! IS_INTERRUPT (func_type))) |
3a7731fd | 11676 | { |
f676971a | 11677 | sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, |
3a7731fd | 11678 | (reg == LR_REGNUM) ? return_reg : reg_names[reg]); |
6d3d9133 | 11679 | } |
ff9940b0 | 11680 | else |
1d5473cb | 11681 | { |
1768c26f PB |
11682 | char *p; |
11683 | int first = 1; | |
6d3d9133 | 11684 | |
699a4925 RE |
11685 | /* Generate the load multiple instruction to restore the |
11686 | registers. Note we can get here, even if | |
11687 | frame_pointer_needed is true, but only if sp already | |
11688 | points to the base of the saved core registers. */ | |
11689 | if (live_regs_mask & (1 << SP_REGNUM)) | |
a72d4945 | 11690 | { |
5848830f PB |
11691 | unsigned HOST_WIDE_INT stack_adjust; |
11692 | ||
5848830f | 11693 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; |
e6d29d15 | 11694 | gcc_assert (stack_adjust == 0 || stack_adjust == 4); |
a72d4945 | 11695 | |
5b3e6663 | 11696 | if (stack_adjust && arm_arch5 && TARGET_ARM) |
a72d4945 RE |
11697 | sprintf (instr, "ldm%sib\t%%|sp, {", conditional); |
11698 | else | |
11699 | { | |
b279b20a NC |
11700 | /* If we can't use ldmib (SA110 bug), |
11701 | then try to pop r3 instead. */ | |
a72d4945 RE |
11702 | if (stack_adjust) |
11703 | live_regs_mask |= 1 << 3; | |
11704 | sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); | |
11705 | } | |
11706 | } | |
da6558fd | 11707 | else |
1768c26f PB |
11708 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); |
11709 | ||
11710 | p = instr + strlen (instr); | |
6d3d9133 | 11711 | |
1768c26f PB |
11712 | for (reg = 0; reg <= SP_REGNUM; reg++) |
11713 | if (live_regs_mask & (1 << reg)) | |
11714 | { | |
11715 | int l = strlen (reg_names[reg]); | |
11716 | ||
11717 | if (first) | |
11718 | first = 0; | |
11719 | else | |
11720 | { | |
11721 | memcpy (p, ", ", 2); | |
11722 | p += 2; | |
11723 | } | |
11724 | ||
11725 | memcpy (p, "%|", 2); | |
11726 | memcpy (p + 2, reg_names[reg], l); | |
11727 | p += l + 2; | |
11728 | } | |
f676971a | 11729 | |
1768c26f PB |
11730 | if (live_regs_mask & (1 << LR_REGNUM)) |
11731 | { | |
b17fe233 | 11732 | sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); |
61f0ccff RE |
11733 | /* If returning from an interrupt, restore the CPSR. */ |
11734 | if (IS_INTERRUPT (func_type)) | |
b17fe233 | 11735 | strcat (p, "^"); |
1768c26f PB |
11736 | } |
11737 | else | |
11738 | strcpy (p, "}"); | |
1d5473cb | 11739 | } |
da6558fd | 11740 | |
1768c26f PB |
11741 | output_asm_insn (instr, & operand); |
11742 | ||
3a7731fd PB |
11743 | /* See if we need to generate an extra instruction to |
11744 | perform the actual function return. */ | |
11745 | if (really_return | |
11746 | && func_type != ARM_FT_INTERWORKED | |
11747 | && (live_regs_mask & (1 << LR_REGNUM)) != 0) | |
da6558fd | 11748 | { |
3a7731fd PB |
11749 | /* The return has already been handled |
11750 | by loading the LR into the PC. */ | |
11751 | really_return = 0; | |
da6558fd | 11752 | } |
ff9940b0 | 11753 | } |
e26053d1 | 11754 | |
1768c26f | 11755 | if (really_return) |
ff9940b0 | 11756 | { |
6d3d9133 NC |
11757 | switch ((int) ARM_FUNC_TYPE (func_type)) |
11758 | { | |
11759 | case ARM_FT_ISR: | |
11760 | case ARM_FT_FIQ: | |
5b3e6663 | 11761 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
11762 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); |
11763 | break; | |
11764 | ||
11765 | case ARM_FT_INTERWORKED: | |
11766 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
11767 | break; | |
11768 | ||
11769 | case ARM_FT_EXCEPTION: | |
5b3e6663 | 11770 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
11771 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); |
11772 | break; | |
11773 | ||
11774 | default: | |
68d560d4 RE |
11775 | /* Use bx if it's available. */ |
11776 | if (arm_arch5 || arm_arch4t) | |
f676971a | 11777 | sprintf (instr, "bx%s\t%%|lr", conditional); |
1768c26f | 11778 | else |
61f0ccff | 11779 | sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); |
6d3d9133 NC |
11780 | break; |
11781 | } | |
1768c26f PB |
11782 | |
11783 | output_asm_insn (instr, & operand); | |
ff9940b0 | 11784 | } |
f3bb6135 | 11785 | |
ff9940b0 RE |
11786 | return ""; |
11787 | } | |
11788 | ||
ef179a26 NC |
11789 | /* Write the function name into the code section, directly preceding |
11790 | the function prologue. | |
11791 | ||
11792 | Code will be output similar to this: | |
11793 | t0 | |
11794 | .ascii "arm_poke_function_name", 0 | |
11795 | .align | |
11796 | t1 | |
11797 | .word 0xff000000 + (t1 - t0) | |
11798 | arm_poke_function_name | |
11799 | mov ip, sp | |
11800 | stmfd sp!, {fp, ip, lr, pc} | |
11801 | sub fp, ip, #4 | |
11802 | ||
11803 | When performing a stack backtrace, code can inspect the value | |
11804 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
11805 | at location pc - 12 and the top 8 bits are set, then we know | |
11806 | that there is a function name embedded immediately preceding this | |
11807 | location and has length ((pc[-3]) & 0xff000000). | |
11808 | ||
11809 | We assume that pc is declared as a pointer to an unsigned long. | |
11810 | ||
11811 | It is of no benefit to output the function name if we are assembling | |
11812 | a leaf function. These function types will not contain a stack | |
11813 | backtrace structure, therefore it is not possible to determine the | |
11814 | function name. */ | |
ef179a26 | 11815 | void |
e32bac5b | 11816 | arm_poke_function_name (FILE *stream, const char *name) |
ef179a26 NC |
11817 | { |
11818 | unsigned long alignlength; | |
11819 | unsigned long length; | |
11820 | rtx x; | |
11821 | ||
d5b7b3ae | 11822 | length = strlen (name) + 1; |
0c2ca901 | 11823 | alignlength = ROUND_UP_WORD (length); |
f676971a | 11824 | |
949d79eb | 11825 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 11826 | ASM_OUTPUT_ALIGN (stream, 2); |
30cf4896 | 11827 | x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); |
301d03af | 11828 | assemble_aligned_integer (UNITS_PER_WORD, x); |
ef179a26 NC |
11829 | } |
11830 | ||
6d3d9133 NC |
11831 | /* Place some comments into the assembler stream |
11832 | describing the current function. */ | |
08c148a8 | 11833 | static void |
e32bac5b | 11834 | arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) |
cce8749e | 11835 | { |
6d3d9133 | 11836 | unsigned long func_type; |
08c148a8 | 11837 | |
5b3e6663 | 11838 | if (TARGET_THUMB1) |
08c148a8 | 11839 | { |
5b3e6663 | 11840 | thumb1_output_function_prologue (f, frame_size); |
08c148a8 NB |
11841 | return; |
11842 | } | |
f676971a | 11843 | |
6d3d9133 | 11844 | /* Sanity check. */ |
e6d29d15 | 11845 | gcc_assert (!arm_ccfsm_state && !arm_target_insn); |
31fdb4d5 | 11846 | |
6d3d9133 | 11847 | func_type = arm_current_func_type (); |
f676971a | 11848 | |
6d3d9133 NC |
11849 | switch ((int) ARM_FUNC_TYPE (func_type)) |
11850 | { | |
11851 | default: | |
11852 | case ARM_FT_NORMAL: | |
11853 | break; | |
11854 | case ARM_FT_INTERWORKED: | |
11855 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
11856 | break; | |
6d3d9133 NC |
11857 | case ARM_FT_ISR: |
11858 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
11859 | break; | |
11860 | case ARM_FT_FIQ: | |
11861 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
11862 | break; | |
11863 | case ARM_FT_EXCEPTION: | |
11864 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
11865 | break; | |
11866 | } | |
f676971a | 11867 | |
6d3d9133 NC |
11868 | if (IS_NAKED (func_type)) |
11869 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
11870 | ||
11871 | if (IS_VOLATILE (func_type)) | |
11872 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
11873 | ||
11874 | if (IS_NESTED (func_type)) | |
11875 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
5b3e6663 PB |
11876 | if (IS_STACKALIGN (func_type)) |
11877 | asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n"); | |
f676971a | 11878 | |
c53dddc2 | 11879 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", |
38173d38 JH |
11880 | crtl->args.size, |
11881 | crtl->args.pretend_args_size, frame_size); | |
6d3d9133 | 11882 | |
3cb66fd7 | 11883 | asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", |
dd18ae56 | 11884 | frame_pointer_needed, |
3cb66fd7 | 11885 | cfun->machine->uses_anonymous_args); |
cce8749e | 11886 | |
6f7ebcbb NC |
11887 | if (cfun->machine->lr_save_eliminated) |
11888 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
11889 | ||
e3b5732b | 11890 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
11891 | asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n"); |
11892 | ||
f3bb6135 | 11893 | } |
cce8749e | 11894 | |
cd2b33d0 | 11895 | const char * |
a72d4945 | 11896 | arm_output_epilogue (rtx sibling) |
cce8749e | 11897 | { |
949d79eb | 11898 | int reg; |
6f7ebcbb | 11899 | unsigned long saved_regs_mask; |
6d3d9133 | 11900 | unsigned long func_type; |
f676971a | 11901 | /* Floats_offset is the offset from the "virtual" frame. In an APCS |
c882c7ac RE |
11902 | frame that is $fp + 4 for a non-variadic function. */ |
11903 | int floats_offset = 0; | |
cce8749e | 11904 | rtx operands[3]; |
d5b7b3ae | 11905 | FILE * f = asm_out_file; |
5a9335ef | 11906 | unsigned int lrm_count = 0; |
a72d4945 | 11907 | int really_return = (sibling == NULL); |
9b66ebb1 | 11908 | int start_reg; |
5848830f | 11909 | arm_stack_offsets *offsets; |
cce8749e | 11910 | |
6d3d9133 NC |
11911 | /* If we have already generated the return instruction |
11912 | then it is futile to generate anything else. */ | |
934c2060 RR |
11913 | if (use_return_insn (FALSE, sibling) && |
11914 | (cfun->machine->return_used_this_function != 0)) | |
949d79eb | 11915 | return ""; |
cce8749e | 11916 | |
6d3d9133 | 11917 | func_type = arm_current_func_type (); |
d5b7b3ae | 11918 | |
6d3d9133 NC |
11919 | if (IS_NAKED (func_type)) |
11920 | /* Naked functions don't have epilogues. */ | |
11921 | return ""; | |
0616531f | 11922 | |
6d3d9133 | 11923 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 11924 | { |
86efdc8e | 11925 | rtx op; |
f676971a | 11926 | |
6d3d9133 | 11927 | /* A volatile function should never return. Call abort. */ |
ed0e6530 | 11928 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 11929 | assemble_external_libcall (op); |
e2c671ba | 11930 | output_asm_insn ("bl\t%a0", &op); |
f676971a | 11931 | |
949d79eb | 11932 | return ""; |
e2c671ba RE |
11933 | } |
11934 | ||
e6d29d15 NS |
11935 | /* If we are throwing an exception, then we really must be doing a |
11936 | return, so we can't tail-call. */ | |
e3b5732b | 11937 | gcc_assert (!crtl->calls_eh_return || really_return); |
f676971a | 11938 | |
5848830f | 11939 | offsets = arm_get_frame_offsets (); |
954954d1 | 11940 | saved_regs_mask = offsets->saved_regs_mask; |
5a9335ef NC |
11941 | |
11942 | if (TARGET_IWMMXT) | |
11943 | lrm_count = bit_count (saved_regs_mask); | |
11944 | ||
5848830f | 11945 | floats_offset = offsets->saved_args; |
6d3d9133 | 11946 | /* Compute how far away the floats will be. */ |
5a9335ef | 11947 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) |
6f7ebcbb | 11948 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 11949 | floats_offset += 4; |
f676971a | 11950 | |
ec6237e4 | 11951 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
cce8749e | 11952 | { |
9b66ebb1 | 11953 | /* This variable is for the Virtual Frame Pointer, not VFP regs. */ |
5848830f | 11954 | int vfp_offset = offsets->frame; |
c882c7ac | 11955 | |
29ad9694 | 11956 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 11957 | { |
9b66ebb1 | 11958 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
6fb5fa3c | 11959 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
11960 | { |
11961 | floats_offset += 12; | |
f676971a | 11962 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
c882c7ac | 11963 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
11964 | } |
11965 | } | |
11966 | else | |
11967 | { | |
9b66ebb1 | 11968 | start_reg = LAST_FPA_REGNUM; |
b111229a | 11969 | |
9b66ebb1 | 11970 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
b111229a | 11971 | { |
6fb5fa3c | 11972 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
11973 | { |
11974 | floats_offset += 12; | |
f676971a | 11975 | |
6354dc9b | 11976 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
11977 | if (start_reg - reg == 3) |
11978 | { | |
dd18ae56 | 11979 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
c882c7ac | 11980 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
11981 | start_reg = reg - 1; |
11982 | } | |
11983 | } | |
11984 | else | |
11985 | { | |
11986 | if (reg != start_reg) | |
dd18ae56 NC |
11987 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
11988 | reg + 1, start_reg - reg, | |
c882c7ac | 11989 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
11990 | start_reg = reg - 1; |
11991 | } | |
11992 | } | |
11993 | ||
11994 | /* Just in case the last register checked also needs unstacking. */ | |
11995 | if (reg != start_reg) | |
dd18ae56 NC |
11996 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
11997 | reg + 1, start_reg - reg, | |
c882c7ac | 11998 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a | 11999 | } |
6d3d9133 | 12000 | |
9b66ebb1 PB |
12001 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
12002 | { | |
9728c9d1 | 12003 | int saved_size; |
9b66ebb1 | 12004 | |
8edfc4cc MS |
12005 | /* The fldmd insns do not have base+offset addressing |
12006 | modes, so we use IP to hold the address. */ | |
9728c9d1 | 12007 | saved_size = arm_get_vfp_saved_size (); |
9b66ebb1 | 12008 | |
9728c9d1 | 12009 | if (saved_size > 0) |
9b66ebb1 | 12010 | { |
9728c9d1 | 12011 | floats_offset += saved_size; |
9b66ebb1 PB |
12012 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM, |
12013 | FP_REGNUM, floats_offset - vfp_offset); | |
12014 | } | |
12015 | start_reg = FIRST_VFP_REGNUM; | |
12016 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
12017 | { | |
6fb5fa3c DB |
12018 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
12019 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
9b66ebb1 PB |
12020 | { |
12021 | if (start_reg != reg) | |
8edfc4cc | 12022 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
12023 | (start_reg - FIRST_VFP_REGNUM) / 2, |
12024 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
12025 | start_reg = reg + 2; |
12026 | } | |
12027 | } | |
12028 | if (start_reg != reg) | |
8edfc4cc | 12029 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
12030 | (start_reg - FIRST_VFP_REGNUM) / 2, |
12031 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
12032 | } |
12033 | ||
5a9335ef NC |
12034 | if (TARGET_IWMMXT) |
12035 | { | |
12036 | /* The frame pointer is guaranteed to be non-double-word aligned. | |
12037 | This is because it is set to (old_stack_pointer - 4) and the | |
12038 | old_stack_pointer was double word aligned. Thus the offset to | |
12039 | the iWMMXt registers to be loaded must also be non-double-word | |
12040 | sized, so that the resultant address *is* double-word aligned. | |
12041 | We can ignore floats_offset since that was already included in | |
12042 | the live_regs_mask. */ | |
12043 | lrm_count += (lrm_count % 2 ? 2 : 1); | |
f676971a | 12044 | |
01d4c813 | 12045 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) |
6fb5fa3c | 12046 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5a9335ef | 12047 | { |
f676971a | 12048 | asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", |
5a9335ef | 12049 | reg, FP_REGNUM, lrm_count * 4); |
f676971a | 12050 | lrm_count += 2; |
5a9335ef NC |
12051 | } |
12052 | } | |
12053 | ||
6f7ebcbb | 12054 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
12055 | frame generation actually contains the old stack pointer. So a |
12056 | quick way to unwind the stack is just pop the IP register directly | |
12057 | into the stack pointer. */ | |
e6d29d15 | 12058 | gcc_assert (saved_regs_mask & (1 << IP_REGNUM)); |
6f7ebcbb NC |
12059 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
12060 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 12061 | |
6f7ebcbb | 12062 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
12063 | only need to restore the LR register (the return address), but to |
12064 | save time we can load it directly into the PC, unless we need a | |
12065 | special function exit sequence, or we are not really returning. */ | |
c9ca9b88 PB |
12066 | if (really_return |
12067 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 12068 | && !crtl->calls_eh_return) |
6d3d9133 NC |
12069 | /* Delete the LR from the register mask, so that the LR on |
12070 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 12071 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 12072 | else |
6f7ebcbb | 12073 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
efc2515b RE |
12074 | |
12075 | /* We must use SP as the base register, because SP is one of the | |
12076 | registers being restored. If an interrupt or page fault | |
12077 | happens in the ldm instruction, the SP might or might not | |
12078 | have been restored. That would be bad, as then SP will no | |
12079 | longer indicate the safe area of stack, and we can get stack | |
12080 | corruption. Using SP as the base register means that it will | |
12081 | be reset correctly to the original value, should an interrupt | |
699a4925 RE |
12082 | occur. If the stack pointer already points at the right |
12083 | place, then omit the subtraction. */ | |
5848830f | 12084 | if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask)) |
e3b5732b | 12085 | || cfun->calls_alloca) |
699a4925 RE |
12086 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, |
12087 | 4 * bit_count (saved_regs_mask)); | |
a15908a4 | 12088 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0); |
7b8b8ade NC |
12089 | |
12090 | if (IS_INTERRUPT (func_type)) | |
12091 | /* Interrupt handlers will have pushed the | |
12092 | IP onto the stack, so restore it now. */ | |
a15908a4 | 12093 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0); |
cce8749e CH |
12094 | } |
12095 | else | |
12096 | { | |
ec6237e4 PB |
12097 | /* This branch is executed for ARM mode (non-apcs frames) and |
12098 | Thumb-2 mode. Frame layout is essentially the same for those | |
12099 | cases, except that in ARM mode frame pointer points to the | |
12100 | first saved register, while in Thumb-2 mode the frame pointer points | |
12101 | to the last saved register. | |
12102 | ||
12103 | It is possible to make frame pointer point to last saved | |
12104 | register in both cases, and remove some conditionals below. | |
12105 | That means that fp setup in prologue would be just "mov fp, sp" | |
12106 | and sp restore in epilogue would be just "mov sp, fp", whereas | |
12107 | now we have to use add/sub in those cases. However, the value | |
12108 | of that would be marginal, as both mov and add/sub are 32-bit | |
12109 | in ARM mode, and it would require extra conditionals | |
12110 | in arm_expand_prologue to distingish ARM-apcs-frame case | |
12111 | (where frame pointer is required to point at first register) | |
12112 | and ARM-non-apcs-frame. Therefore, such change is postponed | |
12113 | until real need arise. */ | |
f0b4bdd5 | 12114 | unsigned HOST_WIDE_INT amount; |
a15908a4 | 12115 | int rfe; |
d2288d8d | 12116 | /* Restore stack pointer if necessary. */ |
ec6237e4 | 12117 | if (TARGET_ARM && frame_pointer_needed) |
5b3e6663 PB |
12118 | { |
12119 | operands[0] = stack_pointer_rtx; | |
ec6237e4 PB |
12120 | operands[1] = hard_frame_pointer_rtx; |
12121 | ||
12122 | operands[2] = GEN_INT (offsets->frame - offsets->saved_regs); | |
12123 | output_add_immediate (operands); | |
5b3e6663 | 12124 | } |
ec6237e4 | 12125 | else |
5b3e6663 | 12126 | { |
ec6237e4 PB |
12127 | if (frame_pointer_needed) |
12128 | { | |
12129 | /* For Thumb-2 restore sp from the frame pointer. | |
12130 | Operand restrictions mean we have to incrememnt FP, then copy | |
12131 | to SP. */ | |
12132 | amount = offsets->locals_base - offsets->saved_regs; | |
12133 | operands[0] = hard_frame_pointer_rtx; | |
12134 | } | |
12135 | else | |
12136 | { | |
954954d1 | 12137 | unsigned long count; |
ec6237e4 PB |
12138 | operands[0] = stack_pointer_rtx; |
12139 | amount = offsets->outgoing_args - offsets->saved_regs; | |
954954d1 PB |
12140 | /* pop call clobbered registers if it avoids a |
12141 | separate stack adjustment. */ | |
12142 | count = offsets->saved_regs - offsets->saved_args; | |
12143 | if (optimize_size | |
12144 | && count != 0 | |
e3b5732b | 12145 | && !crtl->calls_eh_return |
954954d1 PB |
12146 | && bit_count(saved_regs_mask) * 4 == count |
12147 | && !IS_INTERRUPT (func_type) | |
e3b5732b | 12148 | && !crtl->tail_call_emit) |
954954d1 PB |
12149 | { |
12150 | unsigned long mask; | |
12151 | mask = (1 << (arm_size_return_regs() / 4)) - 1; | |
12152 | mask ^= 0xf; | |
12153 | mask &= ~saved_regs_mask; | |
12154 | reg = 0; | |
12155 | while (bit_count (mask) * 4 > amount) | |
12156 | { | |
12157 | while ((mask & (1 << reg)) == 0) | |
12158 | reg++; | |
12159 | mask &= ~(1 << reg); | |
12160 | } | |
12161 | if (bit_count (mask) * 4 == amount) { | |
12162 | amount = 0; | |
12163 | saved_regs_mask |= mask; | |
12164 | } | |
12165 | } | |
ec6237e4 PB |
12166 | } |
12167 | ||
12168 | if (amount) | |
12169 | { | |
12170 | operands[1] = operands[0]; | |
12171 | operands[2] = GEN_INT (amount); | |
12172 | output_add_immediate (operands); | |
12173 | } | |
12174 | if (frame_pointer_needed) | |
12175 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
12176 | SP_REGNUM, HARD_FRAME_POINTER_REGNUM); | |
d2288d8d TG |
12177 | } |
12178 | ||
29ad9694 | 12179 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 12180 | { |
9b66ebb1 | 12181 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
6fb5fa3c | 12182 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
dd18ae56 NC |
12183 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
12184 | reg, SP_REGNUM); | |
b111229a RE |
12185 | } |
12186 | else | |
12187 | { | |
9b66ebb1 | 12188 | start_reg = FIRST_FPA_REGNUM; |
b111229a | 12189 | |
9b66ebb1 | 12190 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
b111229a | 12191 | { |
6fb5fa3c | 12192 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
12193 | { |
12194 | if (reg - start_reg == 3) | |
12195 | { | |
dd18ae56 NC |
12196 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
12197 | start_reg, SP_REGNUM); | |
b111229a RE |
12198 | start_reg = reg + 1; |
12199 | } | |
12200 | } | |
12201 | else | |
12202 | { | |
12203 | if (reg != start_reg) | |
dd18ae56 NC |
12204 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
12205 | start_reg, reg - start_reg, | |
12206 | SP_REGNUM); | |
f676971a | 12207 | |
b111229a RE |
12208 | start_reg = reg + 1; |
12209 | } | |
12210 | } | |
12211 | ||
12212 | /* Just in case the last register checked also needs unstacking. */ | |
12213 | if (reg != start_reg) | |
dd18ae56 NC |
12214 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
12215 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
12216 | } |
12217 | ||
9b66ebb1 PB |
12218 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
12219 | { | |
12220 | start_reg = FIRST_VFP_REGNUM; | |
12221 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
12222 | { | |
6fb5fa3c DB |
12223 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
12224 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
9b66ebb1 PB |
12225 | { |
12226 | if (start_reg != reg) | |
8edfc4cc | 12227 | vfp_output_fldmd (f, SP_REGNUM, |
9728c9d1 PB |
12228 | (start_reg - FIRST_VFP_REGNUM) / 2, |
12229 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
12230 | start_reg = reg + 2; |
12231 | } | |
12232 | } | |
12233 | if (start_reg != reg) | |
8edfc4cc | 12234 | vfp_output_fldmd (f, SP_REGNUM, |
9728c9d1 PB |
12235 | (start_reg - FIRST_VFP_REGNUM) / 2, |
12236 | (reg - start_reg) / 2); | |
9b66ebb1 | 12237 | } |
5a9335ef NC |
12238 | if (TARGET_IWMMXT) |
12239 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
6fb5fa3c | 12240 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
01d4c813 | 12241 | asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM); |
5a9335ef | 12242 | |
6d3d9133 | 12243 | /* If we can, restore the LR into the PC. */ |
a15908a4 PB |
12244 | if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED |
12245 | && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) | |
5b3e6663 | 12246 | && !IS_STACKALIGN (func_type) |
6d3d9133 | 12247 | && really_return |
38173d38 | 12248 | && crtl->args.pretend_args_size == 0 |
c9ca9b88 | 12249 | && saved_regs_mask & (1 << LR_REGNUM) |
e3b5732b | 12250 | && !crtl->calls_eh_return) |
cce8749e | 12251 | { |
6f7ebcbb NC |
12252 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
12253 | saved_regs_mask |= (1 << PC_REGNUM); | |
a15908a4 | 12254 | rfe = IS_INTERRUPT (func_type); |
6d3d9133 | 12255 | } |
a15908a4 PB |
12256 | else |
12257 | rfe = 0; | |
d5b7b3ae | 12258 | |
6d3d9133 | 12259 | /* Load the registers off the stack. If we only have one register |
5b3e6663 PB |
12260 | to load use the LDR instruction - it is faster. For Thumb-2 |
12261 | always use pop and the assembler will pick the best instruction.*/ | |
a15908a4 PB |
12262 | if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM) |
12263 | && !IS_INTERRUPT(func_type)) | |
6d3d9133 | 12264 | { |
c9ca9b88 | 12265 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 12266 | } |
6f7ebcbb | 12267 | else if (saved_regs_mask) |
f1acdf8b NC |
12268 | { |
12269 | if (saved_regs_mask & (1 << SP_REGNUM)) | |
12270 | /* Note - write back to the stack register is not enabled | |
112cdef5 | 12271 | (i.e. "ldmfd sp!..."). We know that the stack pointer is |
f1acdf8b NC |
12272 | in the list of registers and if we add writeback the |
12273 | instruction becomes UNPREDICTABLE. */ | |
a15908a4 PB |
12274 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, |
12275 | rfe); | |
5b3e6663 | 12276 | else if (TARGET_ARM) |
a15908a4 PB |
12277 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, |
12278 | rfe); | |
f1acdf8b | 12279 | else |
a15908a4 | 12280 | print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0); |
f1acdf8b | 12281 | } |
6d3d9133 | 12282 | |
38173d38 | 12283 | if (crtl->args.pretend_args_size) |
cce8749e | 12284 | { |
6d3d9133 NC |
12285 | /* Unwind the pre-pushed regs. */ |
12286 | operands[0] = operands[1] = stack_pointer_rtx; | |
38173d38 | 12287 | operands[2] = GEN_INT (crtl->args.pretend_args_size); |
6d3d9133 NC |
12288 | output_add_immediate (operands); |
12289 | } | |
12290 | } | |
32de079a | 12291 | |
2966b00e | 12292 | /* We may have already restored PC directly from the stack. */ |
0cc3dda8 | 12293 | if (!really_return || saved_regs_mask & (1 << PC_REGNUM)) |
6d3d9133 | 12294 | return ""; |
d5b7b3ae | 12295 | |
c9ca9b88 | 12296 | /* Stack adjustment for exception handler. */ |
e3b5732b | 12297 | if (crtl->calls_eh_return) |
f676971a | 12298 | asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, |
c9ca9b88 PB |
12299 | ARM_EH_STACKADJ_REGNUM); |
12300 | ||
6d3d9133 NC |
12301 | /* Generate the return instruction. */ |
12302 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
12303 | { | |
6d3d9133 NC |
12304 | case ARM_FT_ISR: |
12305 | case ARM_FT_FIQ: | |
12306 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
12307 | break; | |
12308 | ||
12309 | case ARM_FT_EXCEPTION: | |
12310 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
12311 | break; | |
12312 | ||
12313 | case ARM_FT_INTERWORKED: | |
12314 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
12315 | break; | |
12316 | ||
12317 | default: | |
5b3e6663 PB |
12318 | if (IS_STACKALIGN (func_type)) |
12319 | { | |
12320 | /* See comment in arm_expand_prologue. */ | |
12321 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0); | |
12322 | } | |
68d560d4 RE |
12323 | if (arm_arch5 || arm_arch4t) |
12324 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
12325 | else | |
12326 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
6d3d9133 | 12327 | break; |
cce8749e | 12328 | } |
f3bb6135 | 12329 | |
949d79eb RE |
12330 | return ""; |
12331 | } | |
12332 | ||
08c148a8 | 12333 | static void |
e32bac5b | 12334 | arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
5848830f | 12335 | HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED) |
949d79eb | 12336 | { |
5848830f PB |
12337 | arm_stack_offsets *offsets; |
12338 | ||
5b3e6663 | 12339 | if (TARGET_THUMB1) |
d5b7b3ae | 12340 | { |
b12a00f1 RE |
12341 | int regno; |
12342 | ||
12343 | /* Emit any call-via-reg trampolines that are needed for v4t support | |
12344 | of call_reg and call_value_reg type insns. */ | |
57ecec57 | 12345 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
12346 | { |
12347 | rtx label = cfun->machine->call_via[regno]; | |
12348 | ||
12349 | if (label != NULL) | |
12350 | { | |
d6b5193b | 12351 | switch_to_section (function_section (current_function_decl)); |
b12a00f1 RE |
12352 | targetm.asm_out.internal_label (asm_out_file, "L", |
12353 | CODE_LABEL_NUMBER (label)); | |
12354 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
12355 | } | |
12356 | } | |
12357 | ||
d5b7b3ae RE |
12358 | /* ??? Probably not safe to set this here, since it assumes that a |
12359 | function will be emitted as assembly immediately after we generate | |
12360 | RTL for it. This does not happen for inline functions. */ | |
934c2060 | 12361 | cfun->machine->return_used_this_function = 0; |
d5b7b3ae | 12362 | } |
5b3e6663 | 12363 | else /* TARGET_32BIT */ |
d5b7b3ae | 12364 | { |
0977774b | 12365 | /* We need to take into account any stack-frame rounding. */ |
5848830f | 12366 | offsets = arm_get_frame_offsets (); |
0977774b | 12367 | |
e6d29d15 | 12368 | gcc_assert (!use_return_insn (FALSE, NULL) |
934c2060 | 12369 | || (cfun->machine->return_used_this_function != 0) |
e6d29d15 NS |
12370 | || offsets->saved_regs == offsets->outgoing_args |
12371 | || frame_pointer_needed); | |
f3bb6135 | 12372 | |
d5b7b3ae | 12373 | /* Reset the ARM-specific per-function variables. */ |
d5b7b3ae RE |
12374 | after_arm_reorg = 0; |
12375 | } | |
f3bb6135 | 12376 | } |
e2c671ba | 12377 | |
2c849145 JM |
12378 | /* Generate and emit an insn that we will recognize as a push_multi. |
12379 | Unfortunately, since this insn does not reflect very well the actual | |
12380 | semantics of the operation, we need to annotate the insn for the benefit | |
12381 | of DWARF2 frame unwind information. */ | |
2c849145 | 12382 | static rtx |
b279b20a | 12383 | emit_multi_reg_push (unsigned long mask) |
e2c671ba RE |
12384 | { |
12385 | int num_regs = 0; | |
9b598fa0 | 12386 | int num_dwarf_regs; |
e2c671ba RE |
12387 | int i, j; |
12388 | rtx par; | |
2c849145 | 12389 | rtx dwarf; |
87e27392 | 12390 | int dwarf_par_index; |
2c849145 | 12391 | rtx tmp, reg; |
e2c671ba | 12392 | |
d5b7b3ae | 12393 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 12394 | if (mask & (1 << i)) |
5895f793 | 12395 | num_regs++; |
e2c671ba | 12396 | |
e6d29d15 | 12397 | gcc_assert (num_regs && num_regs <= 16); |
e2c671ba | 12398 | |
9b598fa0 RE |
12399 | /* We don't record the PC in the dwarf frame information. */ |
12400 | num_dwarf_regs = num_regs; | |
12401 | if (mask & (1 << PC_REGNUM)) | |
12402 | num_dwarf_regs--; | |
12403 | ||
87e27392 | 12404 | /* For the body of the insn we are going to generate an UNSPEC in |
05713b80 | 12405 | parallel with several USEs. This allows the insn to be recognized |
87e27392 NC |
12406 | by the push_multi pattern in the arm.md file. The insn looks |
12407 | something like this: | |
12408 | ||
f676971a | 12409 | (parallel [ |
b15bca31 RE |
12410 | (set (mem:BLK (pre_dec:BLK (reg:SI sp))) |
12411 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) | |
87e27392 NC |
12412 | (use (reg:SI 11 fp)) |
12413 | (use (reg:SI 12 ip)) | |
12414 | (use (reg:SI 14 lr)) | |
12415 | (use (reg:SI 15 pc)) | |
12416 | ]) | |
12417 | ||
12418 | For the frame note however, we try to be more explicit and actually | |
12419 | show each register being stored into the stack frame, plus a (single) | |
12420 | decrement of the stack pointer. We do it this way in order to be | |
12421 | friendly to the stack unwinding code, which only wants to see a single | |
12422 | stack decrement per instruction. The RTL we generate for the note looks | |
12423 | something like this: | |
12424 | ||
f676971a | 12425 | (sequence [ |
87e27392 NC |
12426 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) |
12427 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
12428 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) | |
12429 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) | |
12430 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) | |
87e27392 NC |
12431 | ]) |
12432 | ||
12433 | This sequence is used both by the code to support stack unwinding for | |
12434 | exceptions handlers and the code to generate dwarf2 frame debugging. */ | |
f676971a | 12435 | |
43cffd11 | 12436 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 12437 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
87e27392 | 12438 | dwarf_par_index = 1; |
e2c671ba | 12439 | |
d5b7b3ae | 12440 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
12441 | { |
12442 | if (mask & (1 << i)) | |
12443 | { | |
2c849145 JM |
12444 | reg = gen_rtx_REG (SImode, i); |
12445 | ||
e2c671ba | 12446 | XVECEXP (par, 0, 0) |
43cffd11 | 12447 | = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
12448 | gen_frame_mem (BLKmode, |
12449 | gen_rtx_PRE_DEC (BLKmode, | |
12450 | stack_pointer_rtx)), | |
43cffd11 | 12451 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 12452 | gen_rtvec (1, reg), |
9b598fa0 | 12453 | UNSPEC_PUSH_MULT)); |
2c849145 | 12454 | |
9b598fa0 RE |
12455 | if (i != PC_REGNUM) |
12456 | { | |
12457 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 12458 | gen_frame_mem (SImode, stack_pointer_rtx), |
9b598fa0 RE |
12459 | reg); |
12460 | RTX_FRAME_RELATED_P (tmp) = 1; | |
12461 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
12462 | dwarf_par_index++; | |
12463 | } | |
2c849145 | 12464 | |
e2c671ba RE |
12465 | break; |
12466 | } | |
12467 | } | |
12468 | ||
12469 | for (j = 1, i++; j < num_regs; i++) | |
12470 | { | |
12471 | if (mask & (1 << i)) | |
12472 | { | |
2c849145 JM |
12473 | reg = gen_rtx_REG (SImode, i); |
12474 | ||
12475 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
12476 | ||
9b598fa0 RE |
12477 | if (i != PC_REGNUM) |
12478 | { | |
31fa16b6 RE |
12479 | tmp |
12480 | = gen_rtx_SET (VOIDmode, | |
12481 | gen_frame_mem (SImode, | |
9b598fa0 RE |
12482 | plus_constant (stack_pointer_rtx, |
12483 | 4 * j)), | |
31fa16b6 | 12484 | reg); |
9b598fa0 RE |
12485 | RTX_FRAME_RELATED_P (tmp) = 1; |
12486 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
12487 | } | |
12488 | ||
e2c671ba RE |
12489 | j++; |
12490 | } | |
12491 | } | |
b111229a | 12492 | |
2c849145 | 12493 | par = emit_insn (par); |
f676971a | 12494 | |
d66437c5 | 12495 | tmp = gen_rtx_SET (VOIDmode, |
87e27392 | 12496 | stack_pointer_rtx, |
d66437c5 | 12497 | plus_constant (stack_pointer_rtx, -4 * num_regs)); |
87e27392 NC |
12498 | RTX_FRAME_RELATED_P (tmp) = 1; |
12499 | XVECEXP (dwarf, 0, 0) = tmp; | |
f676971a | 12500 | |
2c849145 JM |
12501 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, |
12502 | REG_NOTES (par)); | |
12503 | return par; | |
b111229a RE |
12504 | } |
12505 | ||
4f5dfed0 | 12506 | /* Calculate the size of the return value that is passed in registers. */ |
466e4b7a | 12507 | static unsigned |
4f5dfed0 JC |
12508 | arm_size_return_regs (void) |
12509 | { | |
12510 | enum machine_mode mode; | |
12511 | ||
38173d38 JH |
12512 | if (crtl->return_rtx != 0) |
12513 | mode = GET_MODE (crtl->return_rtx); | |
4f5dfed0 JC |
12514 | else |
12515 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
12516 | ||
12517 | return GET_MODE_SIZE (mode); | |
12518 | } | |
12519 | ||
2c849145 | 12520 | static rtx |
e32bac5b | 12521 | emit_sfm (int base_reg, int count) |
b111229a RE |
12522 | { |
12523 | rtx par; | |
2c849145 JM |
12524 | rtx dwarf; |
12525 | rtx tmp, reg; | |
b111229a RE |
12526 | int i; |
12527 | ||
43cffd11 | 12528 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
8ee6eb4e | 12529 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); |
2c849145 JM |
12530 | |
12531 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
12532 | |
12533 | XVECEXP (par, 0, 0) | |
f676971a | 12534 | = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
12535 | gen_frame_mem (BLKmode, |
12536 | gen_rtx_PRE_DEC (BLKmode, | |
12537 | stack_pointer_rtx)), | |
43cffd11 | 12538 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 12539 | gen_rtvec (1, reg), |
b15bca31 | 12540 | UNSPEC_PUSH_MULT)); |
f676971a | 12541 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 | 12542 | gen_frame_mem (XFmode, stack_pointer_rtx), reg); |
2c849145 | 12543 | RTX_FRAME_RELATED_P (tmp) = 1; |
f676971a EC |
12544 | XVECEXP (dwarf, 0, 1) = tmp; |
12545 | ||
b111229a | 12546 | for (i = 1; i < count; i++) |
2c849145 JM |
12547 | { |
12548 | reg = gen_rtx_REG (XFmode, base_reg++); | |
12549 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
12550 | ||
f676971a | 12551 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
12552 | gen_frame_mem (XFmode, |
12553 | plus_constant (stack_pointer_rtx, | |
12554 | i * 12)), | |
2c849145 JM |
12555 | reg); |
12556 | RTX_FRAME_RELATED_P (tmp) = 1; | |
f676971a | 12557 | XVECEXP (dwarf, 0, i + 1) = tmp; |
2c849145 | 12558 | } |
b111229a | 12559 | |
8ee6eb4e PB |
12560 | tmp = gen_rtx_SET (VOIDmode, |
12561 | stack_pointer_rtx, | |
d66437c5 RE |
12562 | plus_constant (stack_pointer_rtx, -12 * count)); |
12563 | ||
8ee6eb4e PB |
12564 | RTX_FRAME_RELATED_P (tmp) = 1; |
12565 | XVECEXP (dwarf, 0, 0) = tmp; | |
12566 | ||
2c849145 JM |
12567 | par = emit_insn (par); |
12568 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
12569 | REG_NOTES (par)); | |
12570 | return par; | |
e2c671ba RE |
12571 | } |
12572 | ||
9b66ebb1 | 12573 | |
3c7ad43e PB |
12574 | /* Return true if the current function needs to save/restore LR. */ |
12575 | ||
12576 | static bool | |
12577 | thumb_force_lr_save (void) | |
12578 | { | |
12579 | return !cfun->machine->lr_save_eliminated | |
12580 | && (!leaf_function_p () | |
12581 | || thumb_far_jump_used_p () | |
6fb5fa3c | 12582 | || df_regs_ever_live_p (LR_REGNUM)); |
3c7ad43e PB |
12583 | } |
12584 | ||
12585 | ||
095bb276 NC |
12586 | /* Compute the distance from register FROM to register TO. |
12587 | These can be the arg pointer (26), the soft frame pointer (25), | |
12588 | the stack pointer (13) or the hard frame pointer (11). | |
c9ca9b88 | 12589 | In thumb mode r7 is used as the soft frame pointer, if needed. |
095bb276 NC |
12590 | Typical stack layout looks like this: |
12591 | ||
12592 | old stack pointer -> | | | |
12593 | ---- | |
12594 | | | \ | |
12595 | | | saved arguments for | |
12596 | | | vararg functions | |
12597 | | | / | |
12598 | -- | |
12599 | hard FP & arg pointer -> | | \ | |
12600 | | | stack | |
12601 | | | frame | |
12602 | | | / | |
12603 | -- | |
12604 | | | \ | |
12605 | | | call saved | |
12606 | | | registers | |
12607 | soft frame pointer -> | | / | |
12608 | -- | |
12609 | | | \ | |
12610 | | | local | |
12611 | | | variables | |
2591db65 | 12612 | locals base pointer -> | | / |
095bb276 NC |
12613 | -- |
12614 | | | \ | |
12615 | | | outgoing | |
12616 | | | arguments | |
12617 | current stack pointer -> | | / | |
12618 | -- | |
12619 | ||
43aa4e05 | 12620 | For a given function some or all of these stack components |
095bb276 NC |
12621 | may not be needed, giving rise to the possibility of |
12622 | eliminating some of the registers. | |
12623 | ||
825dda42 | 12624 | The values returned by this function must reflect the behavior |
095bb276 NC |
12625 | of arm_expand_prologue() and arm_compute_save_reg_mask(). |
12626 | ||
12627 | The sign of the number returned reflects the direction of stack | |
12628 | growth, so the values are positive for all eliminations except | |
5848830f PB |
12629 | from the soft frame pointer to the hard frame pointer. |
12630 | ||
12631 | SFP may point just inside the local variables block to ensure correct | |
12632 | alignment. */ | |
12633 | ||
12634 | ||
12635 | /* Calculate stack offsets. These are used to calculate register elimination | |
954954d1 PB |
12636 | offsets and in prologue/epilogue code. Also calculates which registers |
12637 | should be saved. */ | |
5848830f PB |
12638 | |
12639 | static arm_stack_offsets * | |
12640 | arm_get_frame_offsets (void) | |
095bb276 | 12641 | { |
5848830f | 12642 | struct arm_stack_offsets *offsets; |
095bb276 | 12643 | unsigned long func_type; |
5848830f | 12644 | int leaf; |
5848830f | 12645 | int saved; |
954954d1 | 12646 | int core_saved; |
5848830f | 12647 | HOST_WIDE_INT frame_size; |
954954d1 | 12648 | int i; |
5848830f PB |
12649 | |
12650 | offsets = &cfun->machine->stack_offsets; | |
f676971a | 12651 | |
5848830f PB |
12652 | /* We need to know if we are a leaf function. Unfortunately, it |
12653 | is possible to be called after start_sequence has been called, | |
12654 | which causes get_insns to return the insns for the sequence, | |
12655 | not the function, which will cause leaf_function_p to return | |
12656 | the incorrect result. | |
095bb276 | 12657 | |
5848830f PB |
12658 | to know about leaf functions once reload has completed, and the |
12659 | frame size cannot be changed after that time, so we can safely | |
12660 | use the cached value. */ | |
12661 | ||
12662 | if (reload_completed) | |
12663 | return offsets; | |
12664 | ||
666c27b9 KH |
12665 | /* Initially this is the size of the local variables. It will translated |
12666 | into an offset once we have determined the size of preceding data. */ | |
5848830f PB |
12667 | frame_size = ROUND_UP_WORD (get_frame_size ()); |
12668 | ||
12669 | leaf = leaf_function_p (); | |
12670 | ||
12671 | /* Space for variadic functions. */ | |
38173d38 | 12672 | offsets->saved_args = crtl->args.pretend_args_size; |
5848830f | 12673 | |
5b3e6663 | 12674 | /* In Thumb mode this is incorrect, but never used. */ |
35596784 AJ |
12675 | offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0) + |
12676 | arm_compute_static_chain_stack_bytes(); | |
5848830f | 12677 | |
5b3e6663 | 12678 | if (TARGET_32BIT) |
095bb276 | 12679 | { |
5848830f | 12680 | unsigned int regno; |
ef7112de | 12681 | |
954954d1 PB |
12682 | offsets->saved_regs_mask = arm_compute_save_reg_mask (); |
12683 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
12684 | saved = core_saved; | |
5a9335ef | 12685 | |
5848830f PB |
12686 | /* We know that SP will be doubleword aligned on entry, and we must |
12687 | preserve that condition at any subroutine call. We also require the | |
12688 | soft frame pointer to be doubleword aligned. */ | |
12689 | ||
12690 | if (TARGET_REALLY_IWMMXT) | |
9b66ebb1 | 12691 | { |
5848830f PB |
12692 | /* Check for the call-saved iWMMXt registers. */ |
12693 | for (regno = FIRST_IWMMXT_REGNUM; | |
12694 | regno <= LAST_IWMMXT_REGNUM; | |
12695 | regno++) | |
6fb5fa3c | 12696 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
12697 | saved += 8; |
12698 | } | |
12699 | ||
12700 | func_type = arm_current_func_type (); | |
12701 | if (! IS_VOLATILE (func_type)) | |
12702 | { | |
12703 | /* Space for saved FPA registers. */ | |
12704 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 12705 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
12706 | saved += 12; |
12707 | ||
12708 | /* Space for saved VFP registers. */ | |
12709 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
9728c9d1 | 12710 | saved += arm_get_vfp_saved_size (); |
9b66ebb1 | 12711 | } |
5848830f | 12712 | } |
5b3e6663 | 12713 | else /* TARGET_THUMB1 */ |
5848830f | 12714 | { |
954954d1 PB |
12715 | offsets->saved_regs_mask = thumb1_compute_save_reg_mask (); |
12716 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
12717 | saved = core_saved; | |
5848830f | 12718 | if (TARGET_BACKTRACE) |
57934c39 | 12719 | saved += 16; |
5848830f | 12720 | } |
9b66ebb1 | 12721 | |
5848830f | 12722 | /* Saved registers include the stack frame. */ |
35596784 AJ |
12723 | offsets->saved_regs = offsets->saved_args + saved + |
12724 | arm_compute_static_chain_stack_bytes(); | |
a2503645 | 12725 | offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE; |
5848830f PB |
12726 | /* A leaf function does not need any stack alignment if it has nothing |
12727 | on the stack. */ | |
12728 | if (leaf && frame_size == 0) | |
12729 | { | |
12730 | offsets->outgoing_args = offsets->soft_frame; | |
a3a531ec | 12731 | offsets->locals_base = offsets->soft_frame; |
5848830f PB |
12732 | return offsets; |
12733 | } | |
12734 | ||
12735 | /* Ensure SFP has the correct alignment. */ | |
12736 | if (ARM_DOUBLEWORD_ALIGN | |
12737 | && (offsets->soft_frame & 7)) | |
954954d1 PB |
12738 | { |
12739 | offsets->soft_frame += 4; | |
12740 | /* Try to align stack by pushing an extra reg. Don't bother doing this | |
12741 | when there is a stack frame as the alignment will be rolled into | |
12742 | the normal stack adjustment. */ | |
38173d38 | 12743 | if (frame_size + crtl->outgoing_args_size == 0) |
954954d1 PB |
12744 | { |
12745 | int reg = -1; | |
12746 | ||
12747 | for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++) | |
12748 | { | |
12749 | if ((offsets->saved_regs_mask & (1 << i)) == 0) | |
12750 | { | |
12751 | reg = i; | |
12752 | break; | |
12753 | } | |
12754 | } | |
12755 | ||
12756 | if (reg == -1 && arm_size_return_regs () <= 12 | |
e3b5732b | 12757 | && !crtl->tail_call_emit) |
954954d1 PB |
12758 | { |
12759 | /* Push/pop an argument register (r3) if all callee saved | |
12760 | registers are already being pushed. */ | |
12761 | reg = 3; | |
12762 | } | |
12763 | ||
12764 | if (reg != -1) | |
12765 | { | |
12766 | offsets->saved_regs += 4; | |
12767 | offsets->saved_regs_mask |= (1 << reg); | |
12768 | } | |
12769 | } | |
12770 | } | |
5848830f | 12771 | |
2591db65 RE |
12772 | offsets->locals_base = offsets->soft_frame + frame_size; |
12773 | offsets->outgoing_args = (offsets->locals_base | |
38173d38 | 12774 | + crtl->outgoing_args_size); |
5848830f PB |
12775 | |
12776 | if (ARM_DOUBLEWORD_ALIGN) | |
12777 | { | |
12778 | /* Ensure SP remains doubleword aligned. */ | |
12779 | if (offsets->outgoing_args & 7) | |
12780 | offsets->outgoing_args += 4; | |
e6d29d15 | 12781 | gcc_assert (!(offsets->outgoing_args & 7)); |
095bb276 NC |
12782 | } |
12783 | ||
5848830f PB |
12784 | return offsets; |
12785 | } | |
12786 | ||
12787 | ||
666c27b9 | 12788 | /* Calculate the relative offsets for the different stack pointers. Positive |
5848830f PB |
12789 | offsets are in the direction of stack growth. */ |
12790 | ||
b3f8d95d | 12791 | HOST_WIDE_INT |
5848830f PB |
12792 | arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) |
12793 | { | |
12794 | arm_stack_offsets *offsets; | |
12795 | ||
12796 | offsets = arm_get_frame_offsets (); | |
095bb276 | 12797 | |
095bb276 NC |
12798 | /* OK, now we have enough information to compute the distances. |
12799 | There must be an entry in these switch tables for each pair | |
12800 | of registers in ELIMINABLE_REGS, even if some of the entries | |
12801 | seem to be redundant or useless. */ | |
12802 | switch (from) | |
12803 | { | |
12804 | case ARG_POINTER_REGNUM: | |
12805 | switch (to) | |
12806 | { | |
12807 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
12808 | return 0; | |
12809 | ||
12810 | case FRAME_POINTER_REGNUM: | |
12811 | /* This is the reverse of the soft frame pointer | |
12812 | to hard frame pointer elimination below. */ | |
5848830f | 12813 | return offsets->soft_frame - offsets->saved_args; |
095bb276 NC |
12814 | |
12815 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
35596784 AJ |
12816 | /* This is only non-zero in the case where the static chain register |
12817 | is stored above the frame. */ | |
12818 | return offsets->frame - offsets->saved_args - 4; | |
095bb276 NC |
12819 | |
12820 | case STACK_POINTER_REGNUM: | |
12821 | /* If nothing has been pushed on the stack at all | |
12822 | then this will return -4. This *is* correct! */ | |
5848830f | 12823 | return offsets->outgoing_args - (offsets->saved_args + 4); |
095bb276 NC |
12824 | |
12825 | default: | |
e6d29d15 | 12826 | gcc_unreachable (); |
095bb276 | 12827 | } |
e6d29d15 | 12828 | gcc_unreachable (); |
095bb276 NC |
12829 | |
12830 | case FRAME_POINTER_REGNUM: | |
12831 | switch (to) | |
12832 | { | |
12833 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
12834 | return 0; | |
12835 | ||
12836 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
12837 | /* The hard frame pointer points to the top entry in the | |
12838 | stack frame. The soft frame pointer to the bottom entry | |
12839 | in the stack frame. If there is no stack frame at all, | |
12840 | then they are identical. */ | |
5848830f PB |
12841 | |
12842 | return offsets->frame - offsets->soft_frame; | |
095bb276 NC |
12843 | |
12844 | case STACK_POINTER_REGNUM: | |
5848830f | 12845 | return offsets->outgoing_args - offsets->soft_frame; |
095bb276 NC |
12846 | |
12847 | default: | |
e6d29d15 | 12848 | gcc_unreachable (); |
095bb276 | 12849 | } |
e6d29d15 | 12850 | gcc_unreachable (); |
095bb276 NC |
12851 | |
12852 | default: | |
12853 | /* You cannot eliminate from the stack pointer. | |
12854 | In theory you could eliminate from the hard frame | |
12855 | pointer to the stack pointer, but this will never | |
12856 | happen, since if a stack frame is not needed the | |
12857 | hard frame pointer will never be used. */ | |
e6d29d15 | 12858 | gcc_unreachable (); |
095bb276 NC |
12859 | } |
12860 | } | |
12861 | ||
0977774b | 12862 | |
7a085dce | 12863 | /* Emit RTL to save coprocessor registers on function entry. Returns the |
5b3e6663 PB |
12864 | number of bytes pushed. */ |
12865 | ||
12866 | static int | |
12867 | arm_save_coproc_regs(void) | |
12868 | { | |
12869 | int saved_size = 0; | |
12870 | unsigned reg; | |
12871 | unsigned start_reg; | |
12872 | rtx insn; | |
12873 | ||
12874 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) | |
6fb5fa3c | 12875 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
5b3e6663 PB |
12876 | { |
12877 | insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); | |
12878 | insn = gen_rtx_MEM (V2SImode, insn); | |
12879 | insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); | |
12880 | RTX_FRAME_RELATED_P (insn) = 1; | |
12881 | saved_size += 8; | |
12882 | } | |
12883 | ||
12884 | /* Save any floating point call-saved registers used by this | |
12885 | function. */ | |
12886 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
12887 | { | |
12888 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
6fb5fa3c | 12889 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 PB |
12890 | { |
12891 | insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); | |
12892 | insn = gen_rtx_MEM (XFmode, insn); | |
12893 | insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg)); | |
12894 | RTX_FRAME_RELATED_P (insn) = 1; | |
12895 | saved_size += 12; | |
12896 | } | |
12897 | } | |
12898 | else | |
12899 | { | |
12900 | start_reg = LAST_FPA_REGNUM; | |
12901 | ||
12902 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
12903 | { | |
6fb5fa3c | 12904 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 PB |
12905 | { |
12906 | if (start_reg - reg == 3) | |
12907 | { | |
12908 | insn = emit_sfm (reg, 4); | |
12909 | RTX_FRAME_RELATED_P (insn) = 1; | |
12910 | saved_size += 48; | |
12911 | start_reg = reg - 1; | |
12912 | } | |
12913 | } | |
12914 | else | |
12915 | { | |
12916 | if (start_reg != reg) | |
12917 | { | |
12918 | insn = emit_sfm (reg + 1, start_reg - reg); | |
12919 | RTX_FRAME_RELATED_P (insn) = 1; | |
12920 | saved_size += (start_reg - reg) * 12; | |
12921 | } | |
12922 | start_reg = reg - 1; | |
12923 | } | |
12924 | } | |
12925 | ||
12926 | if (start_reg != reg) | |
12927 | { | |
12928 | insn = emit_sfm (reg + 1, start_reg - reg); | |
12929 | saved_size += (start_reg - reg) * 12; | |
12930 | RTX_FRAME_RELATED_P (insn) = 1; | |
12931 | } | |
12932 | } | |
12933 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
12934 | { | |
12935 | start_reg = FIRST_VFP_REGNUM; | |
12936 | ||
12937 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
12938 | { | |
6fb5fa3c DB |
12939 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
12940 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
5b3e6663 PB |
12941 | { |
12942 | if (start_reg != reg) | |
12943 | saved_size += vfp_emit_fstmd (start_reg, | |
12944 | (reg - start_reg) / 2); | |
12945 | start_reg = reg + 2; | |
12946 | } | |
12947 | } | |
12948 | if (start_reg != reg) | |
12949 | saved_size += vfp_emit_fstmd (start_reg, | |
12950 | (reg - start_reg) / 2); | |
12951 | } | |
12952 | return saved_size; | |
12953 | } | |
12954 | ||
12955 | ||
12956 | /* Set the Thumb frame pointer from the stack pointer. */ | |
12957 | ||
12958 | static void | |
12959 | thumb_set_frame_pointer (arm_stack_offsets *offsets) | |
12960 | { | |
12961 | HOST_WIDE_INT amount; | |
12962 | rtx insn, dwarf; | |
12963 | ||
12964 | amount = offsets->outgoing_args - offsets->locals_base; | |
12965 | if (amount < 1024) | |
12966 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
12967 | stack_pointer_rtx, GEN_INT (amount))); | |
12968 | else | |
12969 | { | |
12970 | emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount))); | |
f5c630c3 PB |
12971 | /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1 |
12972 | expects the first two operands to be the same. */ | |
12973 | if (TARGET_THUMB2) | |
12974 | { | |
12975 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
12976 | stack_pointer_rtx, | |
12977 | hard_frame_pointer_rtx)); | |
12978 | } | |
12979 | else | |
12980 | { | |
12981 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
12982 | hard_frame_pointer_rtx, | |
12983 | stack_pointer_rtx)); | |
12984 | } | |
5b3e6663 PB |
12985 | dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, |
12986 | plus_constant (stack_pointer_rtx, amount)); | |
12987 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
12988 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
12989 | REG_NOTES (insn)); | |
12990 | } | |
12991 | ||
12992 | RTX_FRAME_RELATED_P (insn) = 1; | |
12993 | } | |
12994 | ||
12995 | /* Generate the prologue instructions for entry into an ARM or Thumb-2 | |
12996 | function. */ | |
e2c671ba | 12997 | void |
e32bac5b | 12998 | arm_expand_prologue (void) |
e2c671ba | 12999 | { |
6d3d9133 | 13000 | rtx amount; |
2c849145 | 13001 | rtx insn; |
68dfd979 | 13002 | rtx ip_rtx; |
6d3d9133 NC |
13003 | unsigned long live_regs_mask; |
13004 | unsigned long func_type; | |
68dfd979 | 13005 | int fp_offset = 0; |
095bb276 | 13006 | int saved_pretend_args = 0; |
5848830f | 13007 | int saved_regs = 0; |
b9705a21 | 13008 | unsigned HOST_WIDE_INT args_to_push; |
5848830f | 13009 | arm_stack_offsets *offsets; |
d3236b4d | 13010 | |
6d3d9133 | 13011 | func_type = arm_current_func_type (); |
e2c671ba | 13012 | |
31fdb4d5 | 13013 | /* Naked functions don't have prologues. */ |
6d3d9133 | 13014 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
13015 | return; |
13016 | ||
095bb276 | 13017 | /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ |
38173d38 | 13018 | args_to_push = crtl->args.pretend_args_size; |
f676971a | 13019 | |
6d3d9133 | 13020 | /* Compute which register we will have to save onto the stack. */ |
954954d1 PB |
13021 | offsets = arm_get_frame_offsets (); |
13022 | live_regs_mask = offsets->saved_regs_mask; | |
e2c671ba | 13023 | |
68dfd979 | 13024 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 13025 | |
5b3e6663 PB |
13026 | if (IS_STACKALIGN (func_type)) |
13027 | { | |
13028 | rtx dwarf; | |
13029 | rtx r0; | |
13030 | rtx r1; | |
13031 | /* Handle a word-aligned stack pointer. We generate the following: | |
13032 | ||
13033 | mov r0, sp | |
13034 | bic r1, r0, #7 | |
13035 | mov sp, r1 | |
13036 | <save and restore r0 in normal prologue/epilogue> | |
13037 | mov sp, r0 | |
13038 | bx lr | |
13039 | ||
13040 | The unwinder doesn't need to know about the stack realignment. | |
13041 | Just tell it we saved SP in r0. */ | |
13042 | gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0); | |
13043 | ||
13044 | r0 = gen_rtx_REG (SImode, 0); | |
13045 | r1 = gen_rtx_REG (SImode, 1); | |
44bfa35b NF |
13046 | /* Use a real rtvec rather than NULL_RTVEC so the rest of the |
13047 | compiler won't choke. */ | |
13048 | dwarf = gen_rtx_UNSPEC (SImode, rtvec_alloc (0), UNSPEC_STACK_ALIGN); | |
5b3e6663 PB |
13049 | dwarf = gen_rtx_SET (VOIDmode, r0, dwarf); |
13050 | insn = gen_movsi (r0, stack_pointer_rtx); | |
13051 | RTX_FRAME_RELATED_P (insn) = 1; | |
13052 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13053 | dwarf, REG_NOTES (insn)); | |
13054 | emit_insn (insn); | |
13055 | emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7))); | |
13056 | emit_insn (gen_movsi (stack_pointer_rtx, r1)); | |
13057 | } | |
13058 | ||
ec6237e4 PB |
13059 | /* For APCS frames, if IP register is clobbered |
13060 | when creating frame, save that register in a special | |
13061 | way. */ | |
13062 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) | |
e2c671ba | 13063 | { |
7b8b8ade NC |
13064 | if (IS_INTERRUPT (func_type)) |
13065 | { | |
13066 | /* Interrupt functions must not corrupt any registers. | |
13067 | Creating a frame pointer however, corrupts the IP | |
13068 | register, so we must push it first. */ | |
13069 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
121308d4 NC |
13070 | |
13071 | /* Do not set RTX_FRAME_RELATED_P on this insn. | |
13072 | The dwarf stack unwinding code only wants to see one | |
13073 | stack decrement per function, and this is not it. If | |
13074 | this instruction is labeled as being part of the frame | |
13075 | creation sequence then dwarf2out_frame_debug_expr will | |
e6d29d15 | 13076 | die when it encounters the assignment of IP to FP |
121308d4 NC |
13077 | later on, since the use of SP here establishes SP as |
13078 | the CFA register and not IP. | |
13079 | ||
13080 | Anyway this instruction is not really part of the stack | |
13081 | frame creation although it is part of the prologue. */ | |
7b8b8ade NC |
13082 | } |
13083 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
13084 | { |
13085 | /* The Static chain register is the same as the IP register | |
13086 | used as a scratch register during stack frame creation. | |
13087 | To get around this need to find somewhere to store IP | |
13088 | whilst the frame is being created. We try the following | |
13089 | places in order: | |
f676971a | 13090 | |
6d3d9133 | 13091 | 1. The last argument register. |
68dfd979 NC |
13092 | 2. A slot on the stack above the frame. (This only |
13093 | works if the function is not a varargs function). | |
095bb276 NC |
13094 | 3. Register r3, after pushing the argument registers |
13095 | onto the stack. | |
6d3d9133 | 13096 | |
34ce3d7b JM |
13097 | Note - we only need to tell the dwarf2 backend about the SP |
13098 | adjustment in the second variant; the static chain register | |
13099 | doesn't need to be unwound, as it doesn't contain a value | |
13100 | inherited from the caller. */ | |
d3236b4d | 13101 | |
6fb5fa3c | 13102 | if (df_regs_ever_live_p (3) == false) |
d66437c5 | 13103 | insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 13104 | else if (args_to_push == 0) |
68dfd979 | 13105 | { |
f0b4bdd5 RE |
13106 | rtx dwarf; |
13107 | ||
35596784 AJ |
13108 | gcc_assert(arm_compute_static_chain_stack_bytes() == 4); |
13109 | saved_regs += 4; | |
13110 | ||
d66437c5 RE |
13111 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
13112 | insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx); | |
68dfd979 | 13113 | fp_offset = 4; |
34ce3d7b JM |
13114 | |
13115 | /* Just tell the dwarf backend that we adjusted SP. */ | |
13116 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
d66437c5 RE |
13117 | plus_constant (stack_pointer_rtx, |
13118 | -fp_offset)); | |
34ce3d7b JM |
13119 | RTX_FRAME_RELATED_P (insn) = 1; |
13120 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13121 | dwarf, REG_NOTES (insn)); | |
68dfd979 NC |
13122 | } |
13123 | else | |
095bb276 NC |
13124 | { |
13125 | /* Store the args on the stack. */ | |
3cb66fd7 | 13126 | if (cfun->machine->uses_anonymous_args) |
095bb276 NC |
13127 | insn = emit_multi_reg_push |
13128 | ((0xf0 >> (args_to_push / 4)) & 0xf); | |
13129 | else | |
13130 | insn = emit_insn | |
f676971a | 13131 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 NC |
13132 | GEN_INT (- args_to_push))); |
13133 | ||
13134 | RTX_FRAME_RELATED_P (insn) = 1; | |
13135 | ||
13136 | saved_pretend_args = 1; | |
13137 | fp_offset = args_to_push; | |
13138 | args_to_push = 0; | |
13139 | ||
13140 | /* Now reuse r3 to preserve IP. */ | |
d66437c5 | 13141 | emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 13142 | } |
68dfd979 NC |
13143 | } |
13144 | ||
d66437c5 RE |
13145 | insn = emit_set_insn (ip_rtx, |
13146 | plus_constant (stack_pointer_rtx, fp_offset)); | |
8e56560e | 13147 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
13148 | } |
13149 | ||
095bb276 | 13150 | if (args_to_push) |
e2c671ba | 13151 | { |
6d3d9133 | 13152 | /* Push the argument registers, or reserve space for them. */ |
3cb66fd7 | 13153 | if (cfun->machine->uses_anonymous_args) |
2c849145 | 13154 | insn = emit_multi_reg_push |
095bb276 | 13155 | ((0xf0 >> (args_to_push / 4)) & 0xf); |
e2c671ba | 13156 | else |
2c849145 | 13157 | insn = emit_insn |
f676971a | 13158 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 | 13159 | GEN_INT (- args_to_push))); |
2c849145 | 13160 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
13161 | } |
13162 | ||
06bea5aa | 13163 | /* If this is an interrupt service routine, and the link register |
ec6237e4 PB |
13164 | is going to be pushed, and we're not generating extra |
13165 | push of IP (needed when frame is needed and frame layout if apcs), | |
06bea5aa NC |
13166 | subtracting four from LR now will mean that the function return |
13167 | can be done with a single instruction. */ | |
3a7731fd | 13168 | if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) |
06bea5aa | 13169 | && (live_regs_mask & (1 << LR_REGNUM)) != 0 |
ec6237e4 | 13170 | && !(frame_pointer_needed && TARGET_APCS_FRAME) |
a15908a4 | 13171 | && TARGET_ARM) |
d66437c5 RE |
13172 | { |
13173 | rtx lr = gen_rtx_REG (SImode, LR_REGNUM); | |
13174 | ||
13175 | emit_set_insn (lr, plus_constant (lr, -4)); | |
13176 | } | |
3a7731fd | 13177 | |
e2c671ba RE |
13178 | if (live_regs_mask) |
13179 | { | |
5848830f | 13180 | saved_regs += bit_count (live_regs_mask) * 4; |
954954d1 PB |
13181 | if (optimize_size && !frame_pointer_needed |
13182 | && saved_regs == offsets->saved_regs - offsets->saved_args) | |
13183 | { | |
13184 | /* If no coprocessor registers are being pushed and we don't have | |
13185 | to worry about a frame pointer then push extra registers to | |
13186 | create the stack frame. This is done is a way that does not | |
13187 | alter the frame layout, so is independent of the epilogue. */ | |
13188 | int n; | |
13189 | int frame; | |
13190 | n = 0; | |
13191 | while (n < 8 && (live_regs_mask & (1 << n)) == 0) | |
13192 | n++; | |
13193 | frame = offsets->outgoing_args - (offsets->saved_args + saved_regs); | |
13194 | if (frame && n * 4 >= frame) | |
13195 | { | |
13196 | n = frame / 4; | |
13197 | live_regs_mask |= (1 << n) - 1; | |
13198 | saved_regs += frame; | |
13199 | } | |
13200 | } | |
13201 | insn = emit_multi_reg_push (live_regs_mask); | |
2c849145 | 13202 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba | 13203 | } |
d5b7b3ae | 13204 | |
6d3d9133 | 13205 | if (! IS_VOLATILE (func_type)) |
5b3e6663 | 13206 | saved_regs += arm_save_coproc_regs (); |
b111229a | 13207 | |
5b3e6663 PB |
13208 | if (frame_pointer_needed && TARGET_ARM) |
13209 | { | |
13210 | /* Create the new frame pointer. */ | |
ec6237e4 | 13211 | if (TARGET_APCS_FRAME) |
9b66ebb1 | 13212 | { |
5b3e6663 PB |
13213 | insn = GEN_INT (-(4 + args_to_push + fp_offset)); |
13214 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); | |
13215 | RTX_FRAME_RELATED_P (insn) = 1; | |
9b66ebb1 | 13216 | |
5b3e6663 | 13217 | if (IS_NESTED (func_type)) |
9b66ebb1 | 13218 | { |
5b3e6663 | 13219 | /* Recover the static chain register. */ |
6fb5fa3c | 13220 | if (!df_regs_ever_live_p (3) |
5b3e6663 PB |
13221 | || saved_pretend_args) |
13222 | insn = gen_rtx_REG (SImode, 3); | |
38173d38 | 13223 | else /* if (crtl->args.pretend_args_size == 0) */ |
9b66ebb1 | 13224 | { |
5b3e6663 PB |
13225 | insn = plus_constant (hard_frame_pointer_rtx, 4); |
13226 | insn = gen_frame_mem (SImode, insn); | |
9b66ebb1 | 13227 | } |
5b3e6663 PB |
13228 | emit_set_insn (ip_rtx, insn); |
13229 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
13230 | emit_insn (gen_prologue_use (ip_rtx)); | |
9b66ebb1 | 13231 | } |
68dfd979 | 13232 | } |
ec6237e4 PB |
13233 | else |
13234 | { | |
13235 | insn = GEN_INT (saved_regs - 4); | |
13236 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
13237 | stack_pointer_rtx, insn)); | |
13238 | RTX_FRAME_RELATED_P (insn) = 1; | |
13239 | } | |
2c849145 | 13240 | } |
e2c671ba | 13241 | |
5848830f | 13242 | if (offsets->outgoing_args != offsets->saved_args + saved_regs) |
e2c671ba | 13243 | { |
745b9093 JM |
13244 | /* This add can produce multiple insns for a large constant, so we |
13245 | need to get tricky. */ | |
13246 | rtx last = get_last_insn (); | |
5848830f PB |
13247 | |
13248 | amount = GEN_INT (offsets->saved_args + saved_regs | |
13249 | - offsets->outgoing_args); | |
13250 | ||
2c849145 JM |
13251 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
13252 | amount)); | |
745b9093 JM |
13253 | do |
13254 | { | |
13255 | last = last ? NEXT_INSN (last) : get_insns (); | |
13256 | RTX_FRAME_RELATED_P (last) = 1; | |
13257 | } | |
13258 | while (last != insn); | |
e04c2d6c RE |
13259 | |
13260 | /* If the frame pointer is needed, emit a special barrier that | |
13261 | will prevent the scheduler from moving stores to the frame | |
13262 | before the stack adjustment. */ | |
13263 | if (frame_pointer_needed) | |
3894f59e RE |
13264 | insn = emit_insn (gen_stack_tie (stack_pointer_rtx, |
13265 | hard_frame_pointer_rtx)); | |
e2c671ba RE |
13266 | } |
13267 | ||
876f13b0 | 13268 | |
5b3e6663 PB |
13269 | if (frame_pointer_needed && TARGET_THUMB2) |
13270 | thumb_set_frame_pointer (offsets); | |
13271 | ||
020a4035 | 13272 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
5b3e6663 PB |
13273 | { |
13274 | unsigned long mask; | |
13275 | ||
13276 | mask = live_regs_mask; | |
13277 | mask &= THUMB2_WORK_REGS; | |
13278 | if (!IS_NESTED (func_type)) | |
13279 | mask |= (1 << IP_REGNUM); | |
13280 | arm_load_pic_register (mask); | |
13281 | } | |
876f13b0 | 13282 | |
e2c671ba | 13283 | /* If we are profiling, make sure no instructions are scheduled before |
f5a1b0d2 | 13284 | the call to mcount. Similarly if the user has requested no |
74d9c39f DJ |
13285 | scheduling in the prolog. Similarly if we want non-call exceptions |
13286 | using the EABI unwinder, to prevent faulting instructions from being | |
13287 | swapped with a stack adjustment. */ | |
e3b5732b | 13288 | if (crtl->profile || !TARGET_SCHED_PROLOG |
74d9c39f | 13289 | || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) |
e2c671ba | 13290 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
13291 | |
13292 | /* If the link register is being kept alive, with the return address in it, | |
13293 | then make sure that it does not get reused by the ce2 pass. */ | |
13294 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
6fb5fa3c | 13295 | cfun->machine->lr_save_eliminated = 1; |
e2c671ba | 13296 | } |
cce8749e | 13297 | \f |
5b3e6663 PB |
13298 | /* Print condition code to STREAM. Helper function for arm_print_operand. */ |
13299 | static void | |
13300 | arm_print_condition (FILE *stream) | |
13301 | { | |
13302 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
13303 | { | |
13304 | /* Branch conversion is not implemented for Thumb-2. */ | |
13305 | if (TARGET_THUMB) | |
13306 | { | |
13307 | output_operand_lossage ("predicated Thumb instruction"); | |
13308 | return; | |
13309 | } | |
13310 | if (current_insn_predicate != NULL) | |
13311 | { | |
13312 | output_operand_lossage | |
13313 | ("predicated instruction in conditional sequence"); | |
13314 | return; | |
13315 | } | |
13316 | ||
13317 | fputs (arm_condition_codes[arm_current_cc], stream); | |
13318 | } | |
13319 | else if (current_insn_predicate) | |
13320 | { | |
13321 | enum arm_cond_code code; | |
13322 | ||
13323 | if (TARGET_THUMB1) | |
13324 | { | |
13325 | output_operand_lossage ("predicated Thumb instruction"); | |
13326 | return; | |
13327 | } | |
13328 | ||
13329 | code = get_arm_condition_code (current_insn_predicate); | |
13330 | fputs (arm_condition_codes[code], stream); | |
13331 | } | |
13332 | } | |
13333 | ||
13334 | ||
9997d19d RE |
13335 | /* If CODE is 'd', then the X is a condition operand and the instruction |
13336 | should only be executed if the condition is true. | |
ddd5a7c1 | 13337 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
13338 | should only be executed if the condition is false: however, if the mode |
13339 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
13340 | do this because in these circumstances !GE does not necessarily imply LT; | |
13341 | in these cases the instruction pattern will take care to make sure that | |
13342 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 13343 | doing this instruction unconditionally. |
9997d19d RE |
13344 | If CODE is 'N' then X is a floating point operand that must be negated |
13345 | before output. | |
13346 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
13347 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
9997d19d | 13348 | void |
e32bac5b | 13349 | arm_print_operand (FILE *stream, rtx x, int code) |
9997d19d RE |
13350 | { |
13351 | switch (code) | |
13352 | { | |
13353 | case '@': | |
f3139301 | 13354 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
13355 | return; |
13356 | ||
d5b7b3ae RE |
13357 | case '_': |
13358 | fputs (user_label_prefix, stream); | |
13359 | return; | |
f676971a | 13360 | |
9997d19d | 13361 | case '|': |
f3139301 | 13362 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
13363 | return; |
13364 | ||
13365 | case '?': | |
5b3e6663 PB |
13366 | arm_print_condition (stream); |
13367 | return; | |
cca0a211 | 13368 | |
5b3e6663 PB |
13369 | case '(': |
13370 | /* Nothing in unified syntax, otherwise the current condition code. */ | |
13371 | if (!TARGET_UNIFIED_ASM) | |
13372 | arm_print_condition (stream); | |
13373 | break; | |
13374 | ||
13375 | case ')': | |
13376 | /* The current condition code in unified syntax, otherwise nothing. */ | |
13377 | if (TARGET_UNIFIED_ASM) | |
13378 | arm_print_condition (stream); | |
13379 | break; | |
13380 | ||
13381 | case '.': | |
13382 | /* The current condition code for a condition code setting instruction. | |
7a085dce | 13383 | Preceded by 's' in unified syntax, otherwise followed by 's'. */ |
5b3e6663 PB |
13384 | if (TARGET_UNIFIED_ASM) |
13385 | { | |
13386 | fputc('s', stream); | |
13387 | arm_print_condition (stream); | |
cca0a211 | 13388 | } |
5b3e6663 | 13389 | else |
cca0a211 | 13390 | { |
5b3e6663 PB |
13391 | arm_print_condition (stream); |
13392 | fputc('s', stream); | |
cca0a211 | 13393 | } |
9997d19d RE |
13394 | return; |
13395 | ||
5b3e6663 PB |
13396 | case '!': |
13397 | /* If the instruction is conditionally executed then print | |
13398 | the current condition code, otherwise print 's'. */ | |
13399 | gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM); | |
13400 | if (current_insn_predicate) | |
13401 | arm_print_condition (stream); | |
13402 | else | |
13403 | fputc('s', stream); | |
13404 | break; | |
13405 | ||
88f77cba | 13406 | /* %# is a "break" sequence. It doesn't output anything, but is used to |
cea618ac | 13407 | separate e.g. operand numbers from following text, if that text consists |
88f77cba JB |
13408 | of further digits which we don't want to be part of the operand |
13409 | number. */ | |
13410 | case '#': | |
13411 | return; | |
13412 | ||
9997d19d RE |
13413 | case 'N': |
13414 | { | |
13415 | REAL_VALUE_TYPE r; | |
13416 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
13417 | r = REAL_VALUE_NEGATE (r); | |
13418 | fprintf (stream, "%s", fp_const_from_val (&r)); | |
13419 | } | |
13420 | return; | |
13421 | ||
571191af | 13422 | /* An integer or symbol address without a preceding # sign. */ |
88f77cba | 13423 | case 'c': |
571191af PB |
13424 | switch (GET_CODE (x)) |
13425 | { | |
13426 | case CONST_INT: | |
13427 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
13428 | break; | |
13429 | ||
13430 | case SYMBOL_REF: | |
13431 | output_addr_const (stream, x); | |
13432 | break; | |
13433 | ||
13434 | default: | |
13435 | gcc_unreachable (); | |
13436 | } | |
88f77cba JB |
13437 | return; |
13438 | ||
9997d19d RE |
13439 | case 'B': |
13440 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
13441 | { |
13442 | HOST_WIDE_INT val; | |
5895f793 | 13443 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 13444 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 13445 | } |
9997d19d RE |
13446 | else |
13447 | { | |
13448 | putc ('~', stream); | |
13449 | output_addr_const (stream, x); | |
13450 | } | |
13451 | return; | |
13452 | ||
5b3e6663 PB |
13453 | case 'L': |
13454 | /* The low 16 bits of an immediate constant. */ | |
13455 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff); | |
13456 | return; | |
13457 | ||
9997d19d RE |
13458 | case 'i': |
13459 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
13460 | return; | |
13461 | ||
9b6b54e2 NC |
13462 | /* Truncate Cirrus shift counts. */ |
13463 | case 's': | |
13464 | if (GET_CODE (x) == CONST_INT) | |
13465 | { | |
13466 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); | |
13467 | return; | |
13468 | } | |
13469 | arm_print_operand (stream, x, 0); | |
13470 | return; | |
13471 | ||
9997d19d RE |
13472 | case 'I': |
13473 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
13474 | return; | |
13475 | ||
13476 | case 'S': | |
13477 | { | |
13478 | HOST_WIDE_INT val; | |
beed32b8 RE |
13479 | const char *shift; |
13480 | ||
13481 | if (!shift_operator (x, SImode)) | |
13482 | { | |
13483 | output_operand_lossage ("invalid shift operand"); | |
13484 | break; | |
13485 | } | |
13486 | ||
13487 | shift = shift_op (x, &val); | |
9997d19d | 13488 | |
e2c671ba RE |
13489 | if (shift) |
13490 | { | |
beed32b8 | 13491 | fprintf (stream, ", %s ", shift); |
e2c671ba RE |
13492 | if (val == -1) |
13493 | arm_print_operand (stream, XEXP (x, 1), 0); | |
13494 | else | |
4a0a75dd | 13495 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); |
e2c671ba | 13496 | } |
9997d19d RE |
13497 | } |
13498 | return; | |
13499 | ||
d5b7b3ae | 13500 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
f676971a | 13501 | |
d5b7b3ae RE |
13502 | In a pair of registers containing a DI or DF value the 'Q' |
13503 | operand returns the register number of the register containing | |
093354e0 | 13504 | the least significant part of the value. The 'R' operand returns |
d5b7b3ae RE |
13505 | the register number of the register containing the most |
13506 | significant part of the value. | |
f676971a | 13507 | |
d5b7b3ae RE |
13508 | The 'H' operand returns the higher of the two register numbers. |
13509 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
093354e0 | 13510 | same as the 'Q' operand, since the most significant part of the |
d5b7b3ae RE |
13511 | value is held in the lower number register. The reverse is true |
13512 | on systems where WORDS_BIG_ENDIAN is false. | |
f676971a | 13513 | |
d5b7b3ae RE |
13514 | The purpose of these operands is to distinguish between cases |
13515 | where the endian-ness of the values is important (for example | |
13516 | when they are added together), and cases where the endian-ness | |
13517 | is irrelevant, but the order of register operations is important. | |
13518 | For example when loading a value from memory into a register | |
13519 | pair, the endian-ness does not matter. Provided that the value | |
13520 | from the lower memory address is put into the lower numbered | |
13521 | register, and the value from the higher address is put into the | |
13522 | higher numbered register, the load will work regardless of whether | |
13523 | the value being loaded is big-wordian or little-wordian. The | |
13524 | order of the two register loads can matter however, if the address | |
13525 | of the memory location is actually held in one of the registers | |
13526 | being overwritten by the load. */ | |
c1c2bc04 | 13527 | case 'Q': |
22de4c3d RE |
13528 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
13529 | { | |
13530 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13531 | return; | |
13532 | } | |
13533 | ||
d5b7b3ae | 13534 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
13535 | return; |
13536 | ||
9997d19d | 13537 | case 'R': |
22de4c3d RE |
13538 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
13539 | { | |
13540 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13541 | return; | |
13542 | } | |
13543 | ||
d5b7b3ae RE |
13544 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
13545 | return; | |
13546 | ||
13547 | case 'H': | |
22de4c3d RE |
13548 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
13549 | { | |
13550 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13551 | return; | |
13552 | } | |
13553 | ||
d5b7b3ae | 13554 | asm_fprintf (stream, "%r", REGNO (x) + 1); |
9997d19d RE |
13555 | return; |
13556 | ||
88f77cba JB |
13557 | case 'J': |
13558 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
13559 | { | |
13560 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13561 | return; | |
13562 | } | |
13563 | ||
13564 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2)); | |
13565 | return; | |
13566 | ||
13567 | case 'K': | |
13568 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
13569 | { | |
13570 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13571 | return; | |
13572 | } | |
13573 | ||
13574 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3)); | |
13575 | return; | |
13576 | ||
9997d19d | 13577 | case 'm': |
f676971a | 13578 | asm_fprintf (stream, "%r", |
d5b7b3ae RE |
13579 | GET_CODE (XEXP (x, 0)) == REG |
13580 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
13581 | return; |
13582 | ||
13583 | case 'M': | |
dd18ae56 | 13584 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae | 13585 | REGNO (x), |
e9d7b180 | 13586 | REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); |
9997d19d RE |
13587 | return; |
13588 | ||
88f77cba JB |
13589 | /* Like 'M', but writing doubleword vector registers, for use by Neon |
13590 | insns. */ | |
13591 | case 'h': | |
13592 | { | |
13593 | int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2; | |
13594 | int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2; | |
13595 | if (numregs == 1) | |
13596 | asm_fprintf (stream, "{d%d}", regno); | |
13597 | else | |
13598 | asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1); | |
13599 | } | |
13600 | return; | |
13601 | ||
9997d19d | 13602 | case 'd': |
64e92a26 RE |
13603 | /* CONST_TRUE_RTX means always -- that's the default. */ |
13604 | if (x == const_true_rtx) | |
d5b7b3ae | 13605 | return; |
f676971a | 13606 | |
22de4c3d RE |
13607 | if (!COMPARISON_P (x)) |
13608 | { | |
13609 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13610 | return; | |
13611 | } | |
13612 | ||
defc0463 RE |
13613 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
13614 | stream); | |
9997d19d RE |
13615 | return; |
13616 | ||
13617 | case 'D': | |
112cdef5 | 13618 | /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever |
64e92a26 RE |
13619 | want to do that. */ |
13620 | if (x == const_true_rtx) | |
22de4c3d | 13621 | { |
4dad0aca | 13622 | output_operand_lossage ("instruction never executed"); |
22de4c3d RE |
13623 | return; |
13624 | } | |
13625 | if (!COMPARISON_P (x)) | |
13626 | { | |
13627 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13628 | return; | |
13629 | } | |
d5b7b3ae | 13630 | |
defc0463 RE |
13631 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE |
13632 | (get_arm_condition_code (x))], | |
13633 | stream); | |
9997d19d RE |
13634 | return; |
13635 | ||
9b6b54e2 NC |
13636 | /* Cirrus registers can be accessed in a variety of ways: |
13637 | single floating point (f) | |
13638 | double floating point (d) | |
13639 | 32bit integer (fx) | |
13640 | 64bit integer (dx). */ | |
13641 | case 'W': /* Cirrus register in F mode. */ | |
13642 | case 'X': /* Cirrus register in D mode. */ | |
13643 | case 'Y': /* Cirrus register in FX mode. */ | |
13644 | case 'Z': /* Cirrus register in DX mode. */ | |
e6d29d15 NS |
13645 | gcc_assert (GET_CODE (x) == REG |
13646 | && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS); | |
9b6b54e2 NC |
13647 | |
13648 | fprintf (stream, "mv%s%s", | |
13649 | code == 'W' ? "f" | |
13650 | : code == 'X' ? "d" | |
13651 | : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); | |
13652 | ||
13653 | return; | |
13654 | ||
13655 | /* Print cirrus register in the mode specified by the register's mode. */ | |
13656 | case 'V': | |
13657 | { | |
13658 | int mode = GET_MODE (x); | |
13659 | ||
13660 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
22de4c3d RE |
13661 | { |
13662 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13663 | return; | |
13664 | } | |
9b6b54e2 NC |
13665 | |
13666 | fprintf (stream, "mv%s%s", | |
13667 | mode == DFmode ? "d" | |
13668 | : mode == SImode ? "fx" | |
13669 | : mode == DImode ? "dx" | |
13670 | : "f", reg_names[REGNO (x)] + 2); | |
13671 | ||
13672 | return; | |
13673 | } | |
13674 | ||
5a9335ef NC |
13675 | case 'U': |
13676 | if (GET_CODE (x) != REG | |
13677 | || REGNO (x) < FIRST_IWMMXT_GR_REGNUM | |
13678 | || REGNO (x) > LAST_IWMMXT_GR_REGNUM) | |
13679 | /* Bad value for wCG register number. */ | |
22de4c3d RE |
13680 | { |
13681 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13682 | return; | |
13683 | } | |
13684 | ||
5a9335ef NC |
13685 | else |
13686 | fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); | |
13687 | return; | |
13688 | ||
13689 | /* Print an iWMMXt control register name. */ | |
13690 | case 'w': | |
13691 | if (GET_CODE (x) != CONST_INT | |
13692 | || INTVAL (x) < 0 | |
13693 | || INTVAL (x) >= 16) | |
13694 | /* Bad value for wC register number. */ | |
22de4c3d RE |
13695 | { |
13696 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13697 | return; | |
13698 | } | |
13699 | ||
5a9335ef NC |
13700 | else |
13701 | { | |
13702 | static const char * wc_reg_names [16] = | |
13703 | { | |
13704 | "wCID", "wCon", "wCSSF", "wCASF", | |
13705 | "wC4", "wC5", "wC6", "wC7", | |
13706 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", | |
13707 | "wC12", "wC13", "wC14", "wC15" | |
13708 | }; | |
f676971a | 13709 | |
5a9335ef NC |
13710 | fprintf (stream, wc_reg_names [INTVAL (x)]); |
13711 | } | |
13712 | return; | |
13713 | ||
88f77cba | 13714 | /* Print a VFP/Neon double precision or quad precision register name. */ |
9b66ebb1 | 13715 | case 'P': |
88f77cba | 13716 | case 'q': |
9b66ebb1 PB |
13717 | { |
13718 | int mode = GET_MODE (x); | |
88f77cba JB |
13719 | int is_quad = (code == 'q'); |
13720 | int regno; | |
9b66ebb1 | 13721 | |
88f77cba | 13722 | if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8)) |
22de4c3d RE |
13723 | { |
13724 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13725 | return; | |
13726 | } | |
9b66ebb1 PB |
13727 | |
13728 | if (GET_CODE (x) != REG | |
13729 | || !IS_VFP_REGNUM (REGNO (x))) | |
22de4c3d RE |
13730 | { |
13731 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13732 | return; | |
13733 | } | |
9b66ebb1 | 13734 | |
88f77cba JB |
13735 | regno = REGNO (x); |
13736 | if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno)) | |
13737 | || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno))) | |
22de4c3d RE |
13738 | { |
13739 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13740 | return; | |
13741 | } | |
9b66ebb1 | 13742 | |
88f77cba JB |
13743 | fprintf (stream, "%c%d", is_quad ? 'q' : 'd', |
13744 | (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1)); | |
13745 | } | |
13746 | return; | |
13747 | ||
13748 | /* These two codes print the low/high doubleword register of a Neon quad | |
13749 | register, respectively. For pair-structure types, can also print | |
13750 | low/high quadword registers. */ | |
13751 | case 'e': | |
13752 | case 'f': | |
13753 | { | |
13754 | int mode = GET_MODE (x); | |
13755 | int regno; | |
13756 | ||
13757 | if ((GET_MODE_SIZE (mode) != 16 | |
13758 | && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG) | |
13759 | { | |
13760 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13761 | return; | |
13762 | } | |
13763 | ||
13764 | regno = REGNO (x); | |
13765 | if (!NEON_REGNO_OK_FOR_QUAD (regno)) | |
13766 | { | |
13767 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13768 | return; | |
13769 | } | |
13770 | ||
13771 | if (GET_MODE_SIZE (mode) == 16) | |
13772 | fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1) | |
13773 | + (code == 'f' ? 1 : 0)); | |
13774 | else | |
13775 | fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2) | |
13776 | + (code == 'f' ? 1 : 0)); | |
9b66ebb1 PB |
13777 | } |
13778 | return; | |
13779 | ||
f1adb0a9 JB |
13780 | /* Print a VFPv3 floating-point constant, represented as an integer |
13781 | index. */ | |
13782 | case 'G': | |
13783 | { | |
13784 | int index = vfp3_const_double_index (x); | |
13785 | gcc_assert (index != -1); | |
13786 | fprintf (stream, "%d", index); | |
13787 | } | |
13788 | return; | |
13789 | ||
88f77cba JB |
13790 | /* Print bits representing opcode features for Neon. |
13791 | ||
13792 | Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed | |
13793 | and polynomials as unsigned. | |
13794 | ||
13795 | Bit 1 is 1 for floats and polynomials, 0 for ordinary integers. | |
13796 | ||
13797 | Bit 2 is 1 for rounding functions, 0 otherwise. */ | |
13798 | ||
13799 | /* Identify the type as 's', 'u', 'p' or 'f'. */ | |
13800 | case 'T': | |
13801 | { | |
13802 | HOST_WIDE_INT bits = INTVAL (x); | |
13803 | fputc ("uspf"[bits & 3], stream); | |
13804 | } | |
13805 | return; | |
13806 | ||
13807 | /* Likewise, but signed and unsigned integers are both 'i'. */ | |
13808 | case 'F': | |
13809 | { | |
13810 | HOST_WIDE_INT bits = INTVAL (x); | |
13811 | fputc ("iipf"[bits & 3], stream); | |
13812 | } | |
13813 | return; | |
13814 | ||
13815 | /* As for 'T', but emit 'u' instead of 'p'. */ | |
13816 | case 't': | |
13817 | { | |
13818 | HOST_WIDE_INT bits = INTVAL (x); | |
13819 | fputc ("usuf"[bits & 3], stream); | |
13820 | } | |
13821 | return; | |
13822 | ||
13823 | /* Bit 2: rounding (vs none). */ | |
13824 | case 'O': | |
13825 | { | |
13826 | HOST_WIDE_INT bits = INTVAL (x); | |
13827 | fputs ((bits & 4) != 0 ? "r" : "", stream); | |
13828 | } | |
13829 | return; | |
13830 | ||
9997d19d RE |
13831 | default: |
13832 | if (x == 0) | |
22de4c3d RE |
13833 | { |
13834 | output_operand_lossage ("missing operand"); | |
13835 | return; | |
13836 | } | |
9997d19d | 13837 | |
e6d29d15 | 13838 | switch (GET_CODE (x)) |
9997d19d | 13839 | { |
e6d29d15 NS |
13840 | case REG: |
13841 | asm_fprintf (stream, "%r", REGNO (x)); | |
13842 | break; | |
13843 | ||
13844 | case MEM: | |
9997d19d RE |
13845 | output_memory_reference_mode = GET_MODE (x); |
13846 | output_address (XEXP (x, 0)); | |
e6d29d15 NS |
13847 | break; |
13848 | ||
13849 | case CONST_DOUBLE: | |
88f77cba JB |
13850 | if (TARGET_NEON) |
13851 | { | |
13852 | char fpstr[20]; | |
13853 | real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x), | |
13854 | sizeof (fpstr), 0, 1); | |
13855 | fprintf (stream, "#%s", fpstr); | |
13856 | } | |
13857 | else | |
13858 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
e6d29d15 NS |
13859 | break; |
13860 | ||
13861 | default: | |
13862 | gcc_assert (GET_CODE (x) != NEG); | |
9997d19d RE |
13863 | fputc ('#', stream); |
13864 | output_addr_const (stream, x); | |
e6d29d15 | 13865 | break; |
9997d19d RE |
13866 | } |
13867 | } | |
13868 | } | |
cce8749e | 13869 | \f |
301d03af RS |
13870 | /* Target hook for assembling integer objects. The ARM version needs to |
13871 | handle word-sized values specially. */ | |
301d03af | 13872 | static bool |
e32bac5b | 13873 | arm_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 13874 | { |
88f77cba JB |
13875 | enum machine_mode mode; |
13876 | ||
301d03af RS |
13877 | if (size == UNITS_PER_WORD && aligned_p) |
13878 | { | |
13879 | fputs ("\t.word\t", asm_out_file); | |
13880 | output_addr_const (asm_out_file, x); | |
13881 | ||
13882 | /* Mark symbols as position independent. We only do this in the | |
d6b4baa4 | 13883 | .text segment, not in the .data segment. */ |
301d03af RS |
13884 | if (NEED_GOT_RELOC && flag_pic && making_const_table && |
13885 | (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) | |
13886 | { | |
9403b7f7 RS |
13887 | /* See legitimize_pic_address for an explanation of the |
13888 | TARGET_VXWORKS_RTP check. */ | |
13889 | if (TARGET_VXWORKS_RTP | |
13890 | || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))) | |
301d03af | 13891 | fputs ("(GOT)", asm_out_file); |
9403b7f7 RS |
13892 | else |
13893 | fputs ("(GOTOFF)", asm_out_file); | |
301d03af RS |
13894 | } |
13895 | fputc ('\n', asm_out_file); | |
13896 | return true; | |
13897 | } | |
1d6e90ac | 13898 | |
88f77cba JB |
13899 | mode = GET_MODE (x); |
13900 | ||
13901 | if (arm_vector_mode_supported_p (mode)) | |
5a9335ef NC |
13902 | { |
13903 | int i, units; | |
13904 | ||
e6d29d15 | 13905 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
13906 | |
13907 | units = CONST_VECTOR_NUNITS (x); | |
88f77cba | 13908 | size = GET_MODE_SIZE (GET_MODE_INNER (mode)); |
5a9335ef | 13909 | |
88f77cba JB |
13910 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) |
13911 | for (i = 0; i < units; i++) | |
13912 | { | |
874d42b9 | 13913 | rtx elt = CONST_VECTOR_ELT (x, i); |
88f77cba JB |
13914 | assemble_integer |
13915 | (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); | |
13916 | } | |
13917 | else | |
13918 | for (i = 0; i < units; i++) | |
13919 | { | |
13920 | rtx elt = CONST_VECTOR_ELT (x, i); | |
13921 | REAL_VALUE_TYPE rval; | |
5a9335ef | 13922 | |
88f77cba JB |
13923 | REAL_VALUE_FROM_CONST_DOUBLE (rval, elt); |
13924 | ||
13925 | assemble_real | |
13926 | (rval, GET_MODE_INNER (mode), | |
13927 | i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT); | |
13928 | } | |
5a9335ef NC |
13929 | |
13930 | return true; | |
13931 | } | |
13932 | ||
301d03af RS |
13933 | return default_assemble_integer (x, size, aligned_p); |
13934 | } | |
7abc66b1 | 13935 | |
7abc66b1 | 13936 | static void |
9f296620 | 13937 | arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) |
7abc66b1 | 13938 | { |
50603eed PB |
13939 | section *s; |
13940 | ||
7abc66b1 JB |
13941 | if (!TARGET_AAPCS_BASED) |
13942 | { | |
9f296620 MM |
13943 | (is_ctor ? |
13944 | default_named_section_asm_out_constructor | |
13945 | : default_named_section_asm_out_destructor) (symbol, priority); | |
7abc66b1 JB |
13946 | return; |
13947 | } | |
13948 | ||
13949 | /* Put these in the .init_array section, using a special relocation. */ | |
50603eed PB |
13950 | if (priority != DEFAULT_INIT_PRIORITY) |
13951 | { | |
13952 | char buf[18]; | |
9f296620 MM |
13953 | sprintf (buf, "%s.%.5u", |
13954 | is_ctor ? ".init_array" : ".fini_array", | |
13955 | priority); | |
50603eed PB |
13956 | s = get_section (buf, SECTION_WRITE, NULL_TREE); |
13957 | } | |
9f296620 | 13958 | else if (is_ctor) |
50603eed | 13959 | s = ctors_section; |
9f296620 MM |
13960 | else |
13961 | s = dtors_section; | |
50603eed PB |
13962 | |
13963 | switch_to_section (s); | |
7abc66b1 JB |
13964 | assemble_align (POINTER_SIZE); |
13965 | fputs ("\t.word\t", asm_out_file); | |
13966 | output_addr_const (asm_out_file, symbol); | |
13967 | fputs ("(target1)\n", asm_out_file); | |
13968 | } | |
9f296620 MM |
13969 | |
13970 | /* Add a function to the list of static constructors. */ | |
13971 | ||
13972 | static void | |
13973 | arm_elf_asm_constructor (rtx symbol, int priority) | |
13974 | { | |
13975 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true); | |
13976 | } | |
13977 | ||
13978 | /* Add a function to the list of static destructors. */ | |
13979 | ||
13980 | static void | |
13981 | arm_elf_asm_destructor (rtx symbol, int priority) | |
13982 | { | |
13983 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false); | |
13984 | } | |
301d03af | 13985 | \f |
cce8749e CH |
13986 | /* A finite state machine takes care of noticing whether or not instructions |
13987 | can be conditionally executed, and thus decrease execution time and code | |
13988 | size by deleting branch instructions. The fsm is controlled by | |
13989 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
13990 | ||
13991 | /* The state of the fsm controlling condition codes are: | |
13992 | 0: normal, do nothing special | |
13993 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
13994 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
13995 | 3: make instructions conditional | |
13996 | 4: make instructions conditional | |
13997 | ||
13998 | State transitions (state->state by whom under condition): | |
13999 | 0 -> 1 final_prescan_insn if the `target' is a label | |
14000 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
14001 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
14002 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
4977bab6 | 14003 | 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached |
cce8749e CH |
14004 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). |
14005 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
14006 | (the target insn is arm_target_insn). | |
14007 | ||
ff9940b0 RE |
14008 | If the jump clobbers the conditions then we use states 2 and 4. |
14009 | ||
14010 | A similar thing can be done with conditional return insns. | |
14011 | ||
cce8749e CH |
14012 | XXX In case the `target' is an unconditional branch, this conditionalising |
14013 | of the instructions always reduces code size, but not always execution | |
14014 | time. But then, I want to reduce the code size to somewhere near what | |
14015 | /bin/cc produces. */ | |
14016 | ||
5b3e6663 PB |
14017 | /* In addition to this, state is maintained for Thumb-2 COND_EXEC |
14018 | instructions. When a COND_EXEC instruction is seen the subsequent | |
14019 | instructions are scanned so that multiple conditional instructions can be | |
14020 | combined into a single IT block. arm_condexec_count and arm_condexec_mask | |
14021 | specify the length and true/false mask for the IT block. These will be | |
14022 | decremented/zeroed by arm_asm_output_opcode as the insns are output. */ | |
14023 | ||
cce8749e CH |
14024 | /* Returns the index of the ARM condition code string in |
14025 | `arm_condition_codes'. COMPARISON should be an rtx like | |
14026 | `(eq (...) (...))'. */ | |
84ed5e79 | 14027 | static enum arm_cond_code |
e32bac5b | 14028 | get_arm_condition_code (rtx comparison) |
cce8749e | 14029 | { |
5165176d | 14030 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
1d6e90ac NC |
14031 | int code; |
14032 | enum rtx_code comp_code = GET_CODE (comparison); | |
5165176d RE |
14033 | |
14034 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 14035 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
14036 | XEXP (comparison, 1)); |
14037 | ||
14038 | switch (mode) | |
cce8749e | 14039 | { |
84ed5e79 RE |
14040 | case CC_DNEmode: code = ARM_NE; goto dominance; |
14041 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
14042 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
14043 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
14044 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
14045 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
14046 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
14047 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
14048 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
14049 | case CC_DLTUmode: code = ARM_CC; | |
14050 | ||
14051 | dominance: | |
e6d29d15 | 14052 | gcc_assert (comp_code == EQ || comp_code == NE); |
84ed5e79 RE |
14053 | |
14054 | if (comp_code == EQ) | |
14055 | return ARM_INVERSE_CONDITION_CODE (code); | |
14056 | return code; | |
14057 | ||
5165176d | 14058 | case CC_NOOVmode: |
84ed5e79 | 14059 | switch (comp_code) |
5165176d | 14060 | { |
84ed5e79 RE |
14061 | case NE: return ARM_NE; |
14062 | case EQ: return ARM_EQ; | |
14063 | case GE: return ARM_PL; | |
14064 | case LT: return ARM_MI; | |
e6d29d15 | 14065 | default: gcc_unreachable (); |
5165176d RE |
14066 | } |
14067 | ||
14068 | case CC_Zmode: | |
84ed5e79 | 14069 | switch (comp_code) |
5165176d | 14070 | { |
84ed5e79 RE |
14071 | case NE: return ARM_NE; |
14072 | case EQ: return ARM_EQ; | |
e6d29d15 | 14073 | default: gcc_unreachable (); |
5165176d RE |
14074 | } |
14075 | ||
defc0463 RE |
14076 | case CC_Nmode: |
14077 | switch (comp_code) | |
14078 | { | |
14079 | case NE: return ARM_MI; | |
14080 | case EQ: return ARM_PL; | |
e6d29d15 | 14081 | default: gcc_unreachable (); |
defc0463 RE |
14082 | } |
14083 | ||
5165176d | 14084 | case CCFPEmode: |
e45b72c4 RE |
14085 | case CCFPmode: |
14086 | /* These encodings assume that AC=1 in the FPA system control | |
14087 | byte. This allows us to handle all cases except UNEQ and | |
14088 | LTGT. */ | |
84ed5e79 RE |
14089 | switch (comp_code) |
14090 | { | |
14091 | case GE: return ARM_GE; | |
14092 | case GT: return ARM_GT; | |
14093 | case LE: return ARM_LS; | |
14094 | case LT: return ARM_MI; | |
e45b72c4 RE |
14095 | case NE: return ARM_NE; |
14096 | case EQ: return ARM_EQ; | |
14097 | case ORDERED: return ARM_VC; | |
14098 | case UNORDERED: return ARM_VS; | |
14099 | case UNLT: return ARM_LT; | |
14100 | case UNLE: return ARM_LE; | |
14101 | case UNGT: return ARM_HI; | |
14102 | case UNGE: return ARM_PL; | |
14103 | /* UNEQ and LTGT do not have a representation. */ | |
14104 | case UNEQ: /* Fall through. */ | |
14105 | case LTGT: /* Fall through. */ | |
e6d29d15 | 14106 | default: gcc_unreachable (); |
84ed5e79 RE |
14107 | } |
14108 | ||
14109 | case CC_SWPmode: | |
14110 | switch (comp_code) | |
14111 | { | |
14112 | case NE: return ARM_NE; | |
14113 | case EQ: return ARM_EQ; | |
14114 | case GE: return ARM_LE; | |
14115 | case GT: return ARM_LT; | |
14116 | case LE: return ARM_GE; | |
14117 | case LT: return ARM_GT; | |
14118 | case GEU: return ARM_LS; | |
14119 | case GTU: return ARM_CC; | |
14120 | case LEU: return ARM_CS; | |
14121 | case LTU: return ARM_HI; | |
e6d29d15 | 14122 | default: gcc_unreachable (); |
84ed5e79 RE |
14123 | } |
14124 | ||
bd9c7e23 RE |
14125 | case CC_Cmode: |
14126 | switch (comp_code) | |
14127 | { | |
14128 | case LTU: return ARM_CS; | |
14129 | case GEU: return ARM_CC; | |
e6d29d15 | 14130 | default: gcc_unreachable (); |
bd9c7e23 | 14131 | } |
f676971a | 14132 | |
5165176d | 14133 | case CCmode: |
84ed5e79 | 14134 | switch (comp_code) |
5165176d | 14135 | { |
84ed5e79 RE |
14136 | case NE: return ARM_NE; |
14137 | case EQ: return ARM_EQ; | |
14138 | case GE: return ARM_GE; | |
14139 | case GT: return ARM_GT; | |
14140 | case LE: return ARM_LE; | |
14141 | case LT: return ARM_LT; | |
14142 | case GEU: return ARM_CS; | |
14143 | case GTU: return ARM_HI; | |
14144 | case LEU: return ARM_LS; | |
14145 | case LTU: return ARM_CC; | |
e6d29d15 | 14146 | default: gcc_unreachable (); |
5165176d RE |
14147 | } |
14148 | ||
e6d29d15 | 14149 | default: gcc_unreachable (); |
cce8749e | 14150 | } |
f3bb6135 | 14151 | } |
cce8749e | 14152 | |
44c7bd63 | 14153 | /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed |
5b3e6663 PB |
14154 | instructions. */ |
14155 | void | |
14156 | thumb2_final_prescan_insn (rtx insn) | |
14157 | { | |
14158 | rtx first_insn = insn; | |
14159 | rtx body = PATTERN (insn); | |
14160 | rtx predicate; | |
14161 | enum arm_cond_code code; | |
14162 | int n; | |
14163 | int mask; | |
14164 | ||
14165 | /* Remove the previous insn from the count of insns to be output. */ | |
14166 | if (arm_condexec_count) | |
14167 | arm_condexec_count--; | |
14168 | ||
14169 | /* Nothing to do if we are already inside a conditional block. */ | |
14170 | if (arm_condexec_count) | |
14171 | return; | |
14172 | ||
14173 | if (GET_CODE (body) != COND_EXEC) | |
14174 | return; | |
14175 | ||
14176 | /* Conditional jumps are implemented directly. */ | |
14177 | if (GET_CODE (insn) == JUMP_INSN) | |
14178 | return; | |
14179 | ||
14180 | predicate = COND_EXEC_TEST (body); | |
14181 | arm_current_cc = get_arm_condition_code (predicate); | |
14182 | ||
14183 | n = get_attr_ce_count (insn); | |
14184 | arm_condexec_count = 1; | |
14185 | arm_condexec_mask = (1 << n) - 1; | |
14186 | arm_condexec_masklen = n; | |
14187 | /* See if subsequent instructions can be combined into the same block. */ | |
14188 | for (;;) | |
14189 | { | |
14190 | insn = next_nonnote_insn (insn); | |
14191 | ||
14192 | /* Jumping into the middle of an IT block is illegal, so a label or | |
14193 | barrier terminates the block. */ | |
14194 | if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN) | |
14195 | break; | |
14196 | ||
14197 | body = PATTERN (insn); | |
14198 | /* USE and CLOBBER aren't really insns, so just skip them. */ | |
14199 | if (GET_CODE (body) == USE | |
14200 | || GET_CODE (body) == CLOBBER) | |
5b0202af | 14201 | continue; |
5b3e6663 | 14202 | |
7a085dce | 14203 | /* ??? Recognize conditional jumps, and combine them with IT blocks. */ |
5b3e6663 PB |
14204 | if (GET_CODE (body) != COND_EXEC) |
14205 | break; | |
14206 | /* Allow up to 4 conditionally executed instructions in a block. */ | |
14207 | n = get_attr_ce_count (insn); | |
14208 | if (arm_condexec_masklen + n > 4) | |
14209 | break; | |
14210 | ||
14211 | predicate = COND_EXEC_TEST (body); | |
14212 | code = get_arm_condition_code (predicate); | |
14213 | mask = (1 << n) - 1; | |
14214 | if (arm_current_cc == code) | |
14215 | arm_condexec_mask |= (mask << arm_condexec_masklen); | |
14216 | else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code)) | |
14217 | break; | |
14218 | ||
14219 | arm_condexec_count++; | |
14220 | arm_condexec_masklen += n; | |
14221 | ||
14222 | /* A jump must be the last instruction in a conditional block. */ | |
14223 | if (GET_CODE(insn) == JUMP_INSN) | |
14224 | break; | |
14225 | } | |
14226 | /* Restore recog_data (getting the attributes of other insns can | |
14227 | destroy this array, but final.c assumes that it remains intact | |
14228 | across this call). */ | |
14229 | extract_constrain_insn_cached (first_insn); | |
14230 | } | |
14231 | ||
cce8749e | 14232 | void |
e32bac5b | 14233 | arm_final_prescan_insn (rtx insn) |
cce8749e CH |
14234 | { |
14235 | /* BODY will hold the body of INSN. */ | |
1d6e90ac | 14236 | rtx body = PATTERN (insn); |
cce8749e CH |
14237 | |
14238 | /* This will be 1 if trying to repeat the trick, and things need to be | |
14239 | reversed if it appears to fail. */ | |
14240 | int reverse = 0; | |
14241 | ||
ff9940b0 RE |
14242 | /* JUMP_CLOBBERS will be one implies that the conditions if a branch is |
14243 | taken are clobbered, even if the rtl suggests otherwise. It also | |
14244 | means that we have to grub around within the jump expression to find | |
14245 | out what the conditions are when the jump isn't taken. */ | |
14246 | int jump_clobbers = 0; | |
f676971a | 14247 | |
6354dc9b | 14248 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 | 14249 | int seeking_return = 0; |
f676971a | 14250 | |
cce8749e CH |
14251 | /* START_INSN will hold the insn from where we start looking. This is the |
14252 | first insn after the following code_label if REVERSE is true. */ | |
14253 | rtx start_insn = insn; | |
14254 | ||
14255 | /* If in state 4, check if the target branch is reached, in order to | |
14256 | change back to state 0. */ | |
14257 | if (arm_ccfsm_state == 4) | |
14258 | { | |
14259 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
14260 | { |
14261 | arm_target_insn = NULL; | |
14262 | arm_ccfsm_state = 0; | |
14263 | } | |
cce8749e CH |
14264 | return; |
14265 | } | |
14266 | ||
14267 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
14268 | unconditional branch to a label, and immediately following this branch | |
14269 | is the previous target label which is only used once, and the label this | |
14270 | branch jumps to is not too far off. */ | |
14271 | if (arm_ccfsm_state == 3) | |
14272 | { | |
14273 | if (simplejump_p (insn)) | |
14274 | { | |
14275 | start_insn = next_nonnote_insn (start_insn); | |
14276 | if (GET_CODE (start_insn) == BARRIER) | |
14277 | { | |
14278 | /* XXX Isn't this always a barrier? */ | |
14279 | start_insn = next_nonnote_insn (start_insn); | |
14280 | } | |
14281 | if (GET_CODE (start_insn) == CODE_LABEL | |
14282 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
14283 | && LABEL_NUSES (start_insn) == 1) | |
14284 | reverse = TRUE; | |
14285 | else | |
14286 | return; | |
14287 | } | |
ff9940b0 RE |
14288 | else if (GET_CODE (body) == RETURN) |
14289 | { | |
14290 | start_insn = next_nonnote_insn (start_insn); | |
14291 | if (GET_CODE (start_insn) == BARRIER) | |
14292 | start_insn = next_nonnote_insn (start_insn); | |
14293 | if (GET_CODE (start_insn) == CODE_LABEL | |
14294 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
14295 | && LABEL_NUSES (start_insn) == 1) | |
14296 | { | |
14297 | reverse = TRUE; | |
14298 | seeking_return = 1; | |
14299 | } | |
14300 | else | |
14301 | return; | |
14302 | } | |
cce8749e CH |
14303 | else |
14304 | return; | |
14305 | } | |
14306 | ||
e6d29d15 | 14307 | gcc_assert (!arm_ccfsm_state || reverse); |
cce8749e CH |
14308 | if (GET_CODE (insn) != JUMP_INSN) |
14309 | return; | |
14310 | ||
f676971a | 14311 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
14312 | the jump should always come first */ |
14313 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
14314 | body = XVECEXP (body, 0, 0); | |
14315 | ||
cce8749e CH |
14316 | if (reverse |
14317 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
14318 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
14319 | { | |
bd9c7e23 RE |
14320 | int insns_skipped; |
14321 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
14322 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
14323 | int then_not_else = TRUE; | |
ff9940b0 | 14324 | rtx this_insn = start_insn, label = 0; |
cce8749e | 14325 | |
f676971a | 14326 | /* If the jump cannot be done with one instruction, we cannot |
e45b72c4 | 14327 | conditionally execute the instruction in the inverse case. */ |
ff9940b0 | 14328 | if (get_attr_conds (insn) == CONDS_JUMP_CLOB) |
5bbe2d40 | 14329 | { |
5bbe2d40 RE |
14330 | jump_clobbers = 1; |
14331 | return; | |
14332 | } | |
f676971a | 14333 | |
cce8749e CH |
14334 | /* Register the insn jumped to. */ |
14335 | if (reverse) | |
ff9940b0 RE |
14336 | { |
14337 | if (!seeking_return) | |
14338 | label = XEXP (SET_SRC (body), 0); | |
14339 | } | |
cce8749e CH |
14340 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
14341 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
14342 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
14343 | { | |
14344 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
14345 | then_not_else = FALSE; | |
14346 | } | |
ff9940b0 RE |
14347 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
14348 | seeking_return = 1; | |
14349 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
14350 | { | |
14351 | seeking_return = 1; | |
14352 | then_not_else = FALSE; | |
14353 | } | |
cce8749e | 14354 | else |
e6d29d15 | 14355 | gcc_unreachable (); |
cce8749e CH |
14356 | |
14357 | /* See how many insns this branch skips, and what kind of insns. If all | |
14358 | insns are okay, and the label or unconditional branch to the same | |
14359 | label is not too far away, succeed. */ | |
14360 | for (insns_skipped = 0; | |
b36ba79f | 14361 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
14362 | { |
14363 | rtx scanbody; | |
14364 | ||
14365 | this_insn = next_nonnote_insn (this_insn); | |
14366 | if (!this_insn) | |
14367 | break; | |
14368 | ||
cce8749e CH |
14369 | switch (GET_CODE (this_insn)) |
14370 | { | |
14371 | case CODE_LABEL: | |
14372 | /* Succeed if it is the target label, otherwise fail since | |
14373 | control falls in from somewhere else. */ | |
14374 | if (this_insn == label) | |
14375 | { | |
ff9940b0 RE |
14376 | if (jump_clobbers) |
14377 | { | |
14378 | arm_ccfsm_state = 2; | |
14379 | this_insn = next_nonnote_insn (this_insn); | |
14380 | } | |
14381 | else | |
14382 | arm_ccfsm_state = 1; | |
cce8749e CH |
14383 | succeed = TRUE; |
14384 | } | |
14385 | else | |
14386 | fail = TRUE; | |
14387 | break; | |
14388 | ||
ff9940b0 | 14389 | case BARRIER: |
cce8749e | 14390 | /* Succeed if the following insn is the target label. |
f676971a EC |
14391 | Otherwise fail. |
14392 | If return insns are used then the last insn in a function | |
6354dc9b | 14393 | will be a barrier. */ |
cce8749e | 14394 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 14395 | if (this_insn && this_insn == label) |
cce8749e | 14396 | { |
ff9940b0 RE |
14397 | if (jump_clobbers) |
14398 | { | |
14399 | arm_ccfsm_state = 2; | |
14400 | this_insn = next_nonnote_insn (this_insn); | |
14401 | } | |
14402 | else | |
14403 | arm_ccfsm_state = 1; | |
cce8749e CH |
14404 | succeed = TRUE; |
14405 | } | |
14406 | else | |
14407 | fail = TRUE; | |
14408 | break; | |
14409 | ||
ff9940b0 | 14410 | case CALL_INSN: |
68d560d4 RE |
14411 | /* The AAPCS says that conditional calls should not be |
14412 | used since they make interworking inefficient (the | |
14413 | linker can't transform BL<cond> into BLX). That's | |
14414 | only a problem if the machine has BLX. */ | |
14415 | if (arm_arch5) | |
14416 | { | |
14417 | fail = TRUE; | |
14418 | break; | |
14419 | } | |
14420 | ||
61f0ccff RE |
14421 | /* Succeed if the following insn is the target label, or |
14422 | if the following two insns are a barrier and the | |
14423 | target label. */ | |
14424 | this_insn = next_nonnote_insn (this_insn); | |
14425 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
14426 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 | 14427 | |
61f0ccff RE |
14428 | if (this_insn && this_insn == label |
14429 | && insns_skipped < max_insns_skipped) | |
14430 | { | |
14431 | if (jump_clobbers) | |
bd9c7e23 | 14432 | { |
61f0ccff RE |
14433 | arm_ccfsm_state = 2; |
14434 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 RE |
14435 | } |
14436 | else | |
61f0ccff RE |
14437 | arm_ccfsm_state = 1; |
14438 | succeed = TRUE; | |
bd9c7e23 | 14439 | } |
61f0ccff RE |
14440 | else |
14441 | fail = TRUE; | |
ff9940b0 | 14442 | break; |
2b835d68 | 14443 | |
cce8749e CH |
14444 | case JUMP_INSN: |
14445 | /* If this is an unconditional branch to the same label, succeed. | |
14446 | If it is to another label, do nothing. If it is conditional, | |
14447 | fail. */ | |
e32bac5b RE |
14448 | /* XXX Probably, the tests for SET and the PC are |
14449 | unnecessary. */ | |
cce8749e | 14450 | |
ed4c4348 | 14451 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
14452 | if (GET_CODE (scanbody) == SET |
14453 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
14454 | { |
14455 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
14456 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
14457 | { | |
14458 | arm_ccfsm_state = 2; | |
14459 | succeed = TRUE; | |
14460 | } | |
14461 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
14462 | fail = TRUE; | |
14463 | } | |
112cdef5 | 14464 | /* Fail if a conditional return is undesirable (e.g. on a |
b36ba79f RE |
14465 | StrongARM), but still allow this if optimizing for size. */ |
14466 | else if (GET_CODE (scanbody) == RETURN | |
a72d4945 | 14467 | && !use_return_insn (TRUE, NULL) |
5895f793 | 14468 | && !optimize_size) |
b36ba79f | 14469 | fail = TRUE; |
ff9940b0 RE |
14470 | else if (GET_CODE (scanbody) == RETURN |
14471 | && seeking_return) | |
14472 | { | |
14473 | arm_ccfsm_state = 2; | |
14474 | succeed = TRUE; | |
14475 | } | |
14476 | else if (GET_CODE (scanbody) == PARALLEL) | |
14477 | { | |
14478 | switch (get_attr_conds (this_insn)) | |
14479 | { | |
14480 | case CONDS_NOCOND: | |
14481 | break; | |
14482 | default: | |
14483 | fail = TRUE; | |
14484 | break; | |
14485 | } | |
14486 | } | |
4e67550b | 14487 | else |
112cdef5 | 14488 | fail = TRUE; /* Unrecognized jump (e.g. epilogue). */ |
4e67550b | 14489 | |
cce8749e CH |
14490 | break; |
14491 | ||
14492 | case INSN: | |
ff9940b0 RE |
14493 | /* Instructions using or affecting the condition codes make it |
14494 | fail. */ | |
ed4c4348 | 14495 | scanbody = PATTERN (this_insn); |
5895f793 RE |
14496 | if (!(GET_CODE (scanbody) == SET |
14497 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 14498 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e | 14499 | fail = TRUE; |
9b6b54e2 NC |
14500 | |
14501 | /* A conditional cirrus instruction must be followed by | |
14502 | a non Cirrus instruction. However, since we | |
14503 | conditionalize instructions in this function and by | |
14504 | the time we get here we can't add instructions | |
14505 | (nops), because shorten_branches() has already been | |
14506 | called, we will disable conditionalizing Cirrus | |
14507 | instructions to be safe. */ | |
14508 | if (GET_CODE (scanbody) != USE | |
14509 | && GET_CODE (scanbody) != CLOBBER | |
f0375c66 | 14510 | && get_attr_cirrus (this_insn) != CIRRUS_NOT) |
9b6b54e2 | 14511 | fail = TRUE; |
cce8749e CH |
14512 | break; |
14513 | ||
14514 | default: | |
14515 | break; | |
14516 | } | |
14517 | } | |
14518 | if (succeed) | |
14519 | { | |
ff9940b0 | 14520 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 14521 | arm_target_label = CODE_LABEL_NUMBER (label); |
e6d29d15 | 14522 | else |
ff9940b0 | 14523 | { |
e6d29d15 | 14524 | gcc_assert (seeking_return || arm_ccfsm_state == 2); |
e0b92319 | 14525 | |
ff9940b0 RE |
14526 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) |
14527 | { | |
14528 | this_insn = next_nonnote_insn (this_insn); | |
e6d29d15 NS |
14529 | gcc_assert (!this_insn |
14530 | || (GET_CODE (this_insn) != BARRIER | |
14531 | && GET_CODE (this_insn) != CODE_LABEL)); | |
ff9940b0 RE |
14532 | } |
14533 | if (!this_insn) | |
14534 | { | |
d6b4baa4 | 14535 | /* Oh, dear! we ran off the end.. give up. */ |
5b3e6663 | 14536 | extract_constrain_insn_cached (insn); |
ff9940b0 | 14537 | arm_ccfsm_state = 0; |
abaa26e5 | 14538 | arm_target_insn = NULL; |
ff9940b0 RE |
14539 | return; |
14540 | } | |
14541 | arm_target_insn = this_insn; | |
14542 | } | |
ff9940b0 RE |
14543 | if (jump_clobbers) |
14544 | { | |
e6d29d15 | 14545 | gcc_assert (!reverse); |
f676971a | 14546 | arm_current_cc = |
ff9940b0 RE |
14547 | get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), |
14548 | 0), 0), 1)); | |
14549 | if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) | |
14550 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
14551 | if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) | |
14552 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
14553 | } | |
14554 | else | |
14555 | { | |
14556 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
14557 | what it was. */ | |
14558 | if (!reverse) | |
14559 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), | |
14560 | 0)); | |
14561 | } | |
cce8749e | 14562 | |
cce8749e CH |
14563 | if (reverse || then_not_else) |
14564 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
14565 | } | |
f676971a | 14566 | |
1ccbefce | 14567 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 14568 | destroy this array, but final.c assumes that it remains intact |
5b3e6663 PB |
14569 | across this call. */ |
14570 | extract_constrain_insn_cached (insn); | |
14571 | } | |
14572 | } | |
14573 | ||
14574 | /* Output IT instructions. */ | |
14575 | void | |
14576 | thumb2_asm_output_opcode (FILE * stream) | |
14577 | { | |
14578 | char buff[5]; | |
14579 | int n; | |
14580 | ||
14581 | if (arm_condexec_mask) | |
14582 | { | |
14583 | for (n = 0; n < arm_condexec_masklen; n++) | |
14584 | buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e'; | |
14585 | buff[n] = 0; | |
14586 | asm_fprintf(stream, "i%s\t%s\n\t", buff, | |
14587 | arm_condition_codes[arm_current_cc]); | |
14588 | arm_condexec_mask = 0; | |
cce8749e | 14589 | } |
f3bb6135 | 14590 | } |
cce8749e | 14591 | |
4b02997f | 14592 | /* Returns true if REGNO is a valid register |
21b5653c | 14593 | for holding a quantity of type MODE. */ |
4b02997f | 14594 | int |
e32bac5b | 14595 | arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) |
4b02997f NC |
14596 | { |
14597 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
a6a5de04 RE |
14598 | return (regno == CC_REGNUM |
14599 | || (TARGET_HARD_FLOAT && TARGET_VFP | |
14600 | && regno == VFPCC_REGNUM)); | |
f676971a | 14601 | |
5b3e6663 | 14602 | if (TARGET_THUMB1) |
4b02997f NC |
14603 | /* For the Thumb we only allow values bigger than SImode in |
14604 | registers 0 - 6, so that there is always a second low | |
14605 | register available to hold the upper part of the value. | |
14606 | We probably we ought to ensure that the register is the | |
14607 | start of an even numbered register pair. */ | |
e9d7b180 | 14608 | return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); |
4b02997f | 14609 | |
a6a5de04 RE |
14610 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK |
14611 | && IS_CIRRUS_REGNUM (regno)) | |
9b6b54e2 NC |
14612 | /* We have outlawed SI values in Cirrus registers because they |
14613 | reside in the lower 32 bits, but SF values reside in the | |
14614 | upper 32 bits. This causes gcc all sorts of grief. We can't | |
14615 | even split the registers into pairs because Cirrus SI values | |
14616 | get sign extended to 64bits-- aldyh. */ | |
14617 | return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); | |
14618 | ||
a6a5de04 RE |
14619 | if (TARGET_HARD_FLOAT && TARGET_VFP |
14620 | && IS_VFP_REGNUM (regno)) | |
9b66ebb1 PB |
14621 | { |
14622 | if (mode == SFmode || mode == SImode) | |
f1adb0a9 | 14623 | return VFP_REGNO_OK_FOR_SINGLE (regno); |
9b66ebb1 | 14624 | |
9b66ebb1 | 14625 | if (mode == DFmode) |
f1adb0a9 | 14626 | return VFP_REGNO_OK_FOR_DOUBLE (regno); |
88f77cba JB |
14627 | |
14628 | if (TARGET_NEON) | |
14629 | return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno)) | |
14630 | || (VALID_NEON_QREG_MODE (mode) | |
14631 | && NEON_REGNO_OK_FOR_QUAD (regno)) | |
14632 | || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2)) | |
14633 | || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3)) | |
14634 | || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4)) | |
14635 | || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6)) | |
14636 | || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8)); | |
14637 | ||
9b66ebb1 PB |
14638 | return FALSE; |
14639 | } | |
14640 | ||
a6a5de04 RE |
14641 | if (TARGET_REALLY_IWMMXT) |
14642 | { | |
14643 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
14644 | return mode == SImode; | |
5a9335ef | 14645 | |
a6a5de04 RE |
14646 | if (IS_IWMMXT_REGNUM (regno)) |
14647 | return VALID_IWMMXT_REG_MODE (mode); | |
14648 | } | |
14649 | ||
fdd695fd PB |
14650 | /* We allow any value to be stored in the general registers. |
14651 | Restrict doubleword quantities to even register pairs so that we can | |
88f77cba JB |
14652 | use ldrd. Do not allow Neon structure opaque modes in general registers; |
14653 | they would use too many. */ | |
4b02997f | 14654 | if (regno <= LAST_ARM_REGNUM) |
88f77cba JB |
14655 | return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0) |
14656 | && !VALID_NEON_STRUCT_MODE (mode); | |
4b02997f | 14657 | |
a6a5de04 | 14658 | if (regno == FRAME_POINTER_REGNUM |
4b02997f NC |
14659 | || regno == ARG_POINTER_REGNUM) |
14660 | /* We only allow integers in the fake hard registers. */ | |
14661 | return GET_MODE_CLASS (mode) == MODE_INT; | |
14662 | ||
3b684012 | 14663 | /* The only registers left are the FPA registers |
4b02997f | 14664 | which we only allow to hold FP values. */ |
a6a5de04 RE |
14665 | return (TARGET_HARD_FLOAT && TARGET_FPA |
14666 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
14667 | && regno >= FIRST_FPA_REGNUM | |
14668 | && regno <= LAST_FPA_REGNUM); | |
4b02997f NC |
14669 | } |
14670 | ||
5b3e6663 PB |
14671 | /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are |
14672 | not used in arm mode. */ | |
d5b7b3ae | 14673 | int |
e32bac5b | 14674 | arm_regno_class (int regno) |
d5b7b3ae | 14675 | { |
5b3e6663 | 14676 | if (TARGET_THUMB1) |
d5b7b3ae RE |
14677 | { |
14678 | if (regno == STACK_POINTER_REGNUM) | |
14679 | return STACK_REG; | |
14680 | if (regno == CC_REGNUM) | |
14681 | return CC_REG; | |
14682 | if (regno < 8) | |
14683 | return LO_REGS; | |
14684 | return HI_REGS; | |
14685 | } | |
14686 | ||
5b3e6663 PB |
14687 | if (TARGET_THUMB2 && regno < 8) |
14688 | return LO_REGS; | |
14689 | ||
d5b7b3ae RE |
14690 | if ( regno <= LAST_ARM_REGNUM |
14691 | || regno == FRAME_POINTER_REGNUM | |
14692 | || regno == ARG_POINTER_REGNUM) | |
5b3e6663 | 14693 | return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS; |
f676971a | 14694 | |
9b66ebb1 | 14695 | if (regno == CC_REGNUM || regno == VFPCC_REGNUM) |
5b3e6663 | 14696 | return TARGET_THUMB2 ? CC_REG : NO_REGS; |
d5b7b3ae | 14697 | |
9b6b54e2 NC |
14698 | if (IS_CIRRUS_REGNUM (regno)) |
14699 | return CIRRUS_REGS; | |
14700 | ||
9b66ebb1 | 14701 | if (IS_VFP_REGNUM (regno)) |
f1adb0a9 JB |
14702 | { |
14703 | if (regno <= D7_VFP_REGNUM) | |
14704 | return VFP_D0_D7_REGS; | |
14705 | else if (regno <= LAST_LO_VFP_REGNUM) | |
14706 | return VFP_LO_REGS; | |
14707 | else | |
14708 | return VFP_HI_REGS; | |
14709 | } | |
9b66ebb1 | 14710 | |
5a9335ef NC |
14711 | if (IS_IWMMXT_REGNUM (regno)) |
14712 | return IWMMXT_REGS; | |
14713 | ||
e99faaaa ILT |
14714 | if (IS_IWMMXT_GR_REGNUM (regno)) |
14715 | return IWMMXT_GR_REGS; | |
14716 | ||
3b684012 | 14717 | return FPA_REGS; |
d5b7b3ae RE |
14718 | } |
14719 | ||
14720 | /* Handle a special case when computing the offset | |
14721 | of an argument from the frame pointer. */ | |
14722 | int | |
e32bac5b | 14723 | arm_debugger_arg_offset (int value, rtx addr) |
d5b7b3ae RE |
14724 | { |
14725 | rtx insn; | |
14726 | ||
14727 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
14728 | if (value != 0) | |
14729 | return 0; | |
14730 | ||
14731 | /* We can only cope with the case where the address is held in a register. */ | |
14732 | if (GET_CODE (addr) != REG) | |
14733 | return 0; | |
14734 | ||
14735 | /* If we are using the frame pointer to point at the argument, then | |
14736 | an offset of 0 is correct. */ | |
cd2b33d0 | 14737 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae | 14738 | return 0; |
f676971a | 14739 | |
d5b7b3ae RE |
14740 | /* If we are using the stack pointer to point at the |
14741 | argument, then an offset of 0 is correct. */ | |
5b3e6663 | 14742 | /* ??? Check this is consistent with thumb2 frame layout. */ |
5895f793 | 14743 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
14744 | && REGNO (addr) == SP_REGNUM) |
14745 | return 0; | |
f676971a | 14746 | |
d5b7b3ae RE |
14747 | /* Oh dear. The argument is pointed to by a register rather |
14748 | than being held in a register, or being stored at a known | |
14749 | offset from the frame pointer. Since GDB only understands | |
14750 | those two kinds of argument we must translate the address | |
14751 | held in the register into an offset from the frame pointer. | |
14752 | We do this by searching through the insns for the function | |
14753 | looking to see where this register gets its value. If the | |
4912a07c | 14754 | register is initialized from the frame pointer plus an offset |
d5b7b3ae | 14755 | then we are in luck and we can continue, otherwise we give up. |
f676971a | 14756 | |
d5b7b3ae RE |
14757 | This code is exercised by producing debugging information |
14758 | for a function with arguments like this: | |
f676971a | 14759 | |
d5b7b3ae | 14760 | double func (double a, double b, int c, double d) {return d;} |
f676971a | 14761 | |
d5b7b3ae RE |
14762 | Without this code the stab for parameter 'd' will be set to |
14763 | an offset of 0 from the frame pointer, rather than 8. */ | |
14764 | ||
14765 | /* The if() statement says: | |
14766 | ||
14767 | If the insn is a normal instruction | |
14768 | and if the insn is setting the value in a register | |
14769 | and if the register being set is the register holding the address of the argument | |
14770 | and if the address is computing by an addition | |
14771 | that involves adding to a register | |
14772 | which is the frame pointer | |
14773 | a constant integer | |
14774 | ||
d6b4baa4 | 14775 | then... */ |
f676971a | 14776 | |
d5b7b3ae RE |
14777 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
14778 | { | |
f676971a | 14779 | if ( GET_CODE (insn) == INSN |
d5b7b3ae RE |
14780 | && GET_CODE (PATTERN (insn)) == SET |
14781 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
14782 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
14783 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 14784 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
14785 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
14786 | ) | |
14787 | { | |
14788 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
f676971a | 14789 | |
d5b7b3ae RE |
14790 | break; |
14791 | } | |
14792 | } | |
f676971a | 14793 | |
d5b7b3ae RE |
14794 | if (value == 0) |
14795 | { | |
14796 | debug_rtx (addr); | |
d4ee4d25 | 14797 | warning (0, "unable to compute real location of stacked parameter"); |
d5b7b3ae RE |
14798 | value = 8; /* XXX magic hack */ |
14799 | } | |
14800 | ||
14801 | return value; | |
14802 | } | |
d5b7b3ae | 14803 | \f |
5a9335ef NC |
14804 | #define def_mbuiltin(MASK, NAME, TYPE, CODE) \ |
14805 | do \ | |
14806 | { \ | |
14807 | if ((MASK) & insn_flags) \ | |
c79efc4d RÁE |
14808 | add_builtin_function ((NAME), (TYPE), (CODE), \ |
14809 | BUILT_IN_MD, NULL, NULL_TREE); \ | |
5a9335ef NC |
14810 | } \ |
14811 | while (0) | |
14812 | ||
14813 | struct builtin_description | |
14814 | { | |
14815 | const unsigned int mask; | |
14816 | const enum insn_code icode; | |
14817 | const char * const name; | |
14818 | const enum arm_builtins code; | |
14819 | const enum rtx_code comparison; | |
14820 | const unsigned int flag; | |
14821 | }; | |
14822 | ||
14823 | static const struct builtin_description bdesc_2arg[] = | |
14824 | { | |
14825 | #define IWMMXT_BUILTIN(code, string, builtin) \ | |
14826 | { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ | |
14827 | ARM_BUILTIN_##builtin, 0, 0 }, | |
14828 | ||
14829 | IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) | |
14830 | IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) | |
14831 | IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) | |
14832 | IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) | |
14833 | IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) | |
14834 | IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) | |
14835 | IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) | |
14836 | IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) | |
14837 | IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) | |
14838 | IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) | |
14839 | IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) | |
14840 | IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) | |
14841 | IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) | |
14842 | IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) | |
14843 | IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) | |
14844 | IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) | |
14845 | IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) | |
14846 | IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) | |
14847 | IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) | |
f07a6b21 BE |
14848 | IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) |
14849 | IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) | |
5a9335ef NC |
14850 | IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) |
14851 | IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) | |
14852 | IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) | |
14853 | IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) | |
14854 | IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) | |
14855 | IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) | |
14856 | IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) | |
14857 | IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) | |
14858 | IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) | |
14859 | IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) | |
14860 | IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) | |
14861 | IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) | |
14862 | IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) | |
14863 | IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) | |
14864 | IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) | |
14865 | IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) | |
14866 | IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) | |
14867 | IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) | |
14868 | IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) | |
14869 | IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) | |
14870 | IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) | |
14871 | IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) | |
14872 | IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) | |
14873 | IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) | |
14874 | IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) | |
14875 | IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) | |
14876 | IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) | |
14877 | IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) | |
14878 | IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) | |
14879 | IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) | |
14880 | IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) | |
14881 | IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) | |
14882 | IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) | |
14883 | IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) | |
14884 | IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) | |
14885 | IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) | |
14886 | IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) | |
14887 | ||
14888 | #define IWMMXT_BUILTIN2(code, builtin) \ | |
14889 | { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 }, | |
f676971a | 14890 | |
5a9335ef NC |
14891 | IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) |
14892 | IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) | |
14893 | IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) | |
14894 | IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) | |
14895 | IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) | |
14896 | IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) | |
14897 | IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) | |
88f77cba | 14898 | IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI) |
5a9335ef | 14899 | IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) |
88f77cba | 14900 | IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI) |
5a9335ef NC |
14901 | IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) |
14902 | IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) | |
14903 | IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) | |
88f77cba | 14904 | IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI) |
5a9335ef | 14905 | IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) |
88f77cba | 14906 | IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI) |
5a9335ef | 14907 | IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) |
9b66ebb1 | 14908 | IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) |
5a9335ef | 14909 | IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) |
88f77cba | 14910 | IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI) |
5a9335ef | 14911 | IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) |
88f77cba | 14912 | IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI) |
5a9335ef | 14913 | IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) |
9b66ebb1 | 14914 | IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) |
5a9335ef NC |
14915 | IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) |
14916 | IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) | |
14917 | IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) | |
14918 | IWMMXT_BUILTIN2 (rorv2si3, WRORWI) | |
14919 | IWMMXT_BUILTIN2 (rordi3_di, WRORD) | |
14920 | IWMMXT_BUILTIN2 (rordi3, WRORDI) | |
14921 | IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) | |
14922 | IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) | |
14923 | }; | |
14924 | ||
14925 | static const struct builtin_description bdesc_1arg[] = | |
14926 | { | |
14927 | IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) | |
14928 | IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) | |
14929 | IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) | |
14930 | IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) | |
14931 | IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) | |
14932 | IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) | |
14933 | IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) | |
14934 | IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) | |
14935 | IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) | |
14936 | IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) | |
14937 | IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) | |
14938 | IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) | |
14939 | IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) | |
14940 | IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) | |
14941 | IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) | |
14942 | IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) | |
14943 | IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) | |
14944 | IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) | |
14945 | }; | |
14946 | ||
14947 | /* Set up all the iWMMXt builtins. This is | |
14948 | not called if TARGET_IWMMXT is zero. */ | |
14949 | ||
14950 | static void | |
14951 | arm_init_iwmmxt_builtins (void) | |
14952 | { | |
14953 | const struct builtin_description * d; | |
14954 | size_t i; | |
14955 | tree endlink = void_list_node; | |
14956 | ||
4a5eab38 PB |
14957 | tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); |
14958 | tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); | |
14959 | tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); | |
14960 | ||
5a9335ef NC |
14961 | tree int_ftype_int |
14962 | = build_function_type (integer_type_node, | |
14963 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
14964 | tree v8qi_ftype_v8qi_v8qi_int | |
14965 | = build_function_type (V8QI_type_node, | |
14966 | tree_cons (NULL_TREE, V8QI_type_node, | |
14967 | tree_cons (NULL_TREE, V8QI_type_node, | |
14968 | tree_cons (NULL_TREE, | |
14969 | integer_type_node, | |
14970 | endlink)))); | |
14971 | tree v4hi_ftype_v4hi_int | |
14972 | = build_function_type (V4HI_type_node, | |
14973 | tree_cons (NULL_TREE, V4HI_type_node, | |
14974 | tree_cons (NULL_TREE, integer_type_node, | |
14975 | endlink))); | |
14976 | tree v2si_ftype_v2si_int | |
14977 | = build_function_type (V2SI_type_node, | |
14978 | tree_cons (NULL_TREE, V2SI_type_node, | |
14979 | tree_cons (NULL_TREE, integer_type_node, | |
14980 | endlink))); | |
14981 | tree v2si_ftype_di_di | |
14982 | = build_function_type (V2SI_type_node, | |
14983 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
14984 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
14985 | endlink))); | |
14986 | tree di_ftype_di_int | |
14987 | = build_function_type (long_long_integer_type_node, | |
14988 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
14989 | tree_cons (NULL_TREE, integer_type_node, | |
14990 | endlink))); | |
14991 | tree di_ftype_di_int_int | |
14992 | = build_function_type (long_long_integer_type_node, | |
14993 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
14994 | tree_cons (NULL_TREE, integer_type_node, | |
14995 | tree_cons (NULL_TREE, | |
14996 | integer_type_node, | |
14997 | endlink)))); | |
14998 | tree int_ftype_v8qi | |
14999 | = build_function_type (integer_type_node, | |
15000 | tree_cons (NULL_TREE, V8QI_type_node, | |
15001 | endlink)); | |
15002 | tree int_ftype_v4hi | |
15003 | = build_function_type (integer_type_node, | |
15004 | tree_cons (NULL_TREE, V4HI_type_node, | |
15005 | endlink)); | |
15006 | tree int_ftype_v2si | |
15007 | = build_function_type (integer_type_node, | |
15008 | tree_cons (NULL_TREE, V2SI_type_node, | |
15009 | endlink)); | |
15010 | tree int_ftype_v8qi_int | |
15011 | = build_function_type (integer_type_node, | |
15012 | tree_cons (NULL_TREE, V8QI_type_node, | |
15013 | tree_cons (NULL_TREE, integer_type_node, | |
15014 | endlink))); | |
15015 | tree int_ftype_v4hi_int | |
15016 | = build_function_type (integer_type_node, | |
15017 | tree_cons (NULL_TREE, V4HI_type_node, | |
15018 | tree_cons (NULL_TREE, integer_type_node, | |
15019 | endlink))); | |
15020 | tree int_ftype_v2si_int | |
15021 | = build_function_type (integer_type_node, | |
15022 | tree_cons (NULL_TREE, V2SI_type_node, | |
15023 | tree_cons (NULL_TREE, integer_type_node, | |
15024 | endlink))); | |
15025 | tree v8qi_ftype_v8qi_int_int | |
15026 | = build_function_type (V8QI_type_node, | |
15027 | tree_cons (NULL_TREE, V8QI_type_node, | |
15028 | tree_cons (NULL_TREE, integer_type_node, | |
15029 | tree_cons (NULL_TREE, | |
15030 | integer_type_node, | |
15031 | endlink)))); | |
15032 | tree v4hi_ftype_v4hi_int_int | |
15033 | = build_function_type (V4HI_type_node, | |
15034 | tree_cons (NULL_TREE, V4HI_type_node, | |
15035 | tree_cons (NULL_TREE, integer_type_node, | |
15036 | tree_cons (NULL_TREE, | |
15037 | integer_type_node, | |
15038 | endlink)))); | |
15039 | tree v2si_ftype_v2si_int_int | |
15040 | = build_function_type (V2SI_type_node, | |
15041 | tree_cons (NULL_TREE, V2SI_type_node, | |
15042 | tree_cons (NULL_TREE, integer_type_node, | |
15043 | tree_cons (NULL_TREE, | |
15044 | integer_type_node, | |
15045 | endlink)))); | |
15046 | /* Miscellaneous. */ | |
15047 | tree v8qi_ftype_v4hi_v4hi | |
15048 | = build_function_type (V8QI_type_node, | |
15049 | tree_cons (NULL_TREE, V4HI_type_node, | |
15050 | tree_cons (NULL_TREE, V4HI_type_node, | |
15051 | endlink))); | |
15052 | tree v4hi_ftype_v2si_v2si | |
15053 | = build_function_type (V4HI_type_node, | |
15054 | tree_cons (NULL_TREE, V2SI_type_node, | |
15055 | tree_cons (NULL_TREE, V2SI_type_node, | |
15056 | endlink))); | |
15057 | tree v2si_ftype_v4hi_v4hi | |
15058 | = build_function_type (V2SI_type_node, | |
15059 | tree_cons (NULL_TREE, V4HI_type_node, | |
15060 | tree_cons (NULL_TREE, V4HI_type_node, | |
15061 | endlink))); | |
15062 | tree v2si_ftype_v8qi_v8qi | |
15063 | = build_function_type (V2SI_type_node, | |
15064 | tree_cons (NULL_TREE, V8QI_type_node, | |
15065 | tree_cons (NULL_TREE, V8QI_type_node, | |
15066 | endlink))); | |
15067 | tree v4hi_ftype_v4hi_di | |
15068 | = build_function_type (V4HI_type_node, | |
15069 | tree_cons (NULL_TREE, V4HI_type_node, | |
15070 | tree_cons (NULL_TREE, | |
15071 | long_long_integer_type_node, | |
15072 | endlink))); | |
15073 | tree v2si_ftype_v2si_di | |
15074 | = build_function_type (V2SI_type_node, | |
15075 | tree_cons (NULL_TREE, V2SI_type_node, | |
15076 | tree_cons (NULL_TREE, | |
15077 | long_long_integer_type_node, | |
15078 | endlink))); | |
15079 | tree void_ftype_int_int | |
15080 | = build_function_type (void_type_node, | |
15081 | tree_cons (NULL_TREE, integer_type_node, | |
15082 | tree_cons (NULL_TREE, integer_type_node, | |
15083 | endlink))); | |
15084 | tree di_ftype_void | |
15085 | = build_function_type (long_long_unsigned_type_node, endlink); | |
15086 | tree di_ftype_v8qi | |
15087 | = build_function_type (long_long_integer_type_node, | |
15088 | tree_cons (NULL_TREE, V8QI_type_node, | |
15089 | endlink)); | |
15090 | tree di_ftype_v4hi | |
15091 | = build_function_type (long_long_integer_type_node, | |
15092 | tree_cons (NULL_TREE, V4HI_type_node, | |
15093 | endlink)); | |
15094 | tree di_ftype_v2si | |
15095 | = build_function_type (long_long_integer_type_node, | |
15096 | tree_cons (NULL_TREE, V2SI_type_node, | |
15097 | endlink)); | |
15098 | tree v2si_ftype_v4hi | |
15099 | = build_function_type (V2SI_type_node, | |
15100 | tree_cons (NULL_TREE, V4HI_type_node, | |
15101 | endlink)); | |
15102 | tree v4hi_ftype_v8qi | |
15103 | = build_function_type (V4HI_type_node, | |
15104 | tree_cons (NULL_TREE, V8QI_type_node, | |
15105 | endlink)); | |
15106 | ||
15107 | tree di_ftype_di_v4hi_v4hi | |
15108 | = build_function_type (long_long_unsigned_type_node, | |
15109 | tree_cons (NULL_TREE, | |
15110 | long_long_unsigned_type_node, | |
15111 | tree_cons (NULL_TREE, V4HI_type_node, | |
15112 | tree_cons (NULL_TREE, | |
15113 | V4HI_type_node, | |
15114 | endlink)))); | |
15115 | ||
15116 | tree di_ftype_v4hi_v4hi | |
15117 | = build_function_type (long_long_unsigned_type_node, | |
15118 | tree_cons (NULL_TREE, V4HI_type_node, | |
15119 | tree_cons (NULL_TREE, V4HI_type_node, | |
15120 | endlink))); | |
15121 | ||
15122 | /* Normal vector binops. */ | |
15123 | tree v8qi_ftype_v8qi_v8qi | |
15124 | = build_function_type (V8QI_type_node, | |
15125 | tree_cons (NULL_TREE, V8QI_type_node, | |
15126 | tree_cons (NULL_TREE, V8QI_type_node, | |
15127 | endlink))); | |
15128 | tree v4hi_ftype_v4hi_v4hi | |
15129 | = build_function_type (V4HI_type_node, | |
15130 | tree_cons (NULL_TREE, V4HI_type_node, | |
15131 | tree_cons (NULL_TREE, V4HI_type_node, | |
15132 | endlink))); | |
15133 | tree v2si_ftype_v2si_v2si | |
15134 | = build_function_type (V2SI_type_node, | |
15135 | tree_cons (NULL_TREE, V2SI_type_node, | |
15136 | tree_cons (NULL_TREE, V2SI_type_node, | |
15137 | endlink))); | |
15138 | tree di_ftype_di_di | |
15139 | = build_function_type (long_long_unsigned_type_node, | |
15140 | tree_cons (NULL_TREE, long_long_unsigned_type_node, | |
15141 | tree_cons (NULL_TREE, | |
15142 | long_long_unsigned_type_node, | |
15143 | endlink))); | |
15144 | ||
15145 | /* Add all builtins that are more or less simple operations on two | |
15146 | operands. */ | |
e97a46ce | 15147 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef NC |
15148 | { |
15149 | /* Use one of the operands; the target can have a different mode for | |
15150 | mask-generating compares. */ | |
15151 | enum machine_mode mode; | |
15152 | tree type; | |
15153 | ||
15154 | if (d->name == 0) | |
15155 | continue; | |
15156 | ||
15157 | mode = insn_data[d->icode].operand[1].mode; | |
15158 | ||
15159 | switch (mode) | |
15160 | { | |
15161 | case V8QImode: | |
15162 | type = v8qi_ftype_v8qi_v8qi; | |
15163 | break; | |
15164 | case V4HImode: | |
15165 | type = v4hi_ftype_v4hi_v4hi; | |
15166 | break; | |
15167 | case V2SImode: | |
15168 | type = v2si_ftype_v2si_v2si; | |
15169 | break; | |
15170 | case DImode: | |
15171 | type = di_ftype_di_di; | |
15172 | break; | |
15173 | ||
15174 | default: | |
e6d29d15 | 15175 | gcc_unreachable (); |
5a9335ef NC |
15176 | } |
15177 | ||
15178 | def_mbuiltin (d->mask, d->name, type, d->code); | |
15179 | } | |
15180 | ||
15181 | /* Add the remaining MMX insns with somewhat more complicated types. */ | |
15182 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); | |
15183 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); | |
15184 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); | |
15185 | ||
15186 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); | |
15187 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); | |
15188 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); | |
15189 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); | |
15190 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); | |
15191 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); | |
15192 | ||
15193 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); | |
15194 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); | |
15195 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); | |
15196 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); | |
15197 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); | |
15198 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); | |
15199 | ||
15200 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); | |
15201 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); | |
15202 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); | |
15203 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); | |
15204 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); | |
15205 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); | |
15206 | ||
15207 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); | |
15208 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); | |
15209 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); | |
15210 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); | |
15211 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); | |
15212 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); | |
15213 | ||
15214 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); | |
15215 | ||
15216 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); | |
15217 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); | |
15218 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); | |
15219 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); | |
15220 | ||
15221 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); | |
15222 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); | |
15223 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); | |
15224 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); | |
15225 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); | |
15226 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); | |
15227 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); | |
15228 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); | |
15229 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); | |
15230 | ||
15231 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); | |
15232 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); | |
15233 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); | |
15234 | ||
15235 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); | |
15236 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); | |
15237 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); | |
15238 | ||
15239 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); | |
15240 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); | |
15241 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); | |
15242 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); | |
15243 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); | |
15244 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); | |
15245 | ||
15246 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); | |
15247 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); | |
15248 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); | |
15249 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); | |
15250 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); | |
15251 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); | |
15252 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); | |
15253 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); | |
15254 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); | |
15255 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); | |
15256 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); | |
15257 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); | |
15258 | ||
15259 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); | |
15260 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); | |
15261 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); | |
15262 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); | |
15263 | ||
15264 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); | |
15265 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); | |
15266 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); | |
15267 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); | |
15268 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); | |
15269 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); | |
15270 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); | |
15271 | } | |
15272 | ||
d3585b76 DJ |
15273 | static void |
15274 | arm_init_tls_builtins (void) | |
15275 | { | |
ebfe65a3 | 15276 | tree ftype, decl; |
d3585b76 DJ |
15277 | |
15278 | ftype = build_function_type (ptr_type_node, void_list_node); | |
ebfe65a3 JJ |
15279 | decl = add_builtin_function ("__builtin_thread_pointer", ftype, |
15280 | ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
15281 | NULL, NULL_TREE); | |
15282 | TREE_NOTHROW (decl) = 1; | |
15283 | TREE_READONLY (decl) = 1; | |
d3585b76 DJ |
15284 | } |
15285 | ||
88f77cba JB |
15286 | typedef enum { |
15287 | T_V8QI = 0x0001, | |
15288 | T_V4HI = 0x0002, | |
15289 | T_V2SI = 0x0004, | |
15290 | T_V2SF = 0x0008, | |
15291 | T_DI = 0x0010, | |
15292 | T_V16QI = 0x0020, | |
15293 | T_V8HI = 0x0040, | |
15294 | T_V4SI = 0x0080, | |
15295 | T_V4SF = 0x0100, | |
15296 | T_V2DI = 0x0200, | |
15297 | T_TI = 0x0400, | |
15298 | T_EI = 0x0800, | |
15299 | T_OI = 0x1000 | |
15300 | } neon_builtin_type_bits; | |
15301 | ||
15302 | #define v8qi_UP T_V8QI | |
15303 | #define v4hi_UP T_V4HI | |
15304 | #define v2si_UP T_V2SI | |
15305 | #define v2sf_UP T_V2SF | |
15306 | #define di_UP T_DI | |
15307 | #define v16qi_UP T_V16QI | |
15308 | #define v8hi_UP T_V8HI | |
15309 | #define v4si_UP T_V4SI | |
15310 | #define v4sf_UP T_V4SF | |
15311 | #define v2di_UP T_V2DI | |
15312 | #define ti_UP T_TI | |
15313 | #define ei_UP T_EI | |
15314 | #define oi_UP T_OI | |
15315 | ||
15316 | #define UP(X) X##_UP | |
15317 | ||
15318 | #define T_MAX 13 | |
15319 | ||
15320 | typedef enum { | |
15321 | NEON_BINOP, | |
15322 | NEON_TERNOP, | |
15323 | NEON_UNOP, | |
15324 | NEON_GETLANE, | |
15325 | NEON_SETLANE, | |
15326 | NEON_CREATE, | |
15327 | NEON_DUP, | |
15328 | NEON_DUPLANE, | |
15329 | NEON_COMBINE, | |
15330 | NEON_SPLIT, | |
15331 | NEON_LANEMUL, | |
15332 | NEON_LANEMULL, | |
15333 | NEON_LANEMULH, | |
15334 | NEON_LANEMAC, | |
15335 | NEON_SCALARMUL, | |
15336 | NEON_SCALARMULL, | |
15337 | NEON_SCALARMULH, | |
15338 | NEON_SCALARMAC, | |
15339 | NEON_CONVERT, | |
15340 | NEON_FIXCONV, | |
15341 | NEON_SELECT, | |
15342 | NEON_RESULTPAIR, | |
15343 | NEON_REINTERP, | |
15344 | NEON_VTBL, | |
15345 | NEON_VTBX, | |
15346 | NEON_LOAD1, | |
15347 | NEON_LOAD1LANE, | |
15348 | NEON_STORE1, | |
15349 | NEON_STORE1LANE, | |
15350 | NEON_LOADSTRUCT, | |
15351 | NEON_LOADSTRUCTLANE, | |
15352 | NEON_STORESTRUCT, | |
15353 | NEON_STORESTRUCTLANE, | |
15354 | NEON_LOGICBINOP, | |
15355 | NEON_SHIFTINSERT, | |
15356 | NEON_SHIFTIMM, | |
15357 | NEON_SHIFTACC | |
15358 | } neon_itype; | |
15359 | ||
15360 | typedef struct { | |
15361 | const char *name; | |
15362 | const neon_itype itype; | |
15363 | const neon_builtin_type_bits bits; | |
15364 | const enum insn_code codes[T_MAX]; | |
15365 | const unsigned int num_vars; | |
15366 | unsigned int base_fcode; | |
15367 | } neon_builtin_datum; | |
15368 | ||
15369 | #define CF(N,X) CODE_FOR_neon_##N##X | |
15370 | ||
15371 | #define VAR1(T, N, A) \ | |
15372 | #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0 | |
15373 | #define VAR2(T, N, A, B) \ | |
15374 | #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0 | |
15375 | #define VAR3(T, N, A, B, C) \ | |
15376 | #N, NEON_##T, UP (A) | UP (B) | UP (C), \ | |
15377 | { CF (N, A), CF (N, B), CF (N, C) }, 3, 0 | |
15378 | #define VAR4(T, N, A, B, C, D) \ | |
15379 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \ | |
15380 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0 | |
15381 | #define VAR5(T, N, A, B, C, D, E) \ | |
15382 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \ | |
15383 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0 | |
15384 | #define VAR6(T, N, A, B, C, D, E, F) \ | |
15385 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \ | |
15386 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0 | |
15387 | #define VAR7(T, N, A, B, C, D, E, F, G) \ | |
15388 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \ | |
15389 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
15390 | CF (N, G) }, 7, 0 | |
15391 | #define VAR8(T, N, A, B, C, D, E, F, G, H) \ | |
15392 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
15393 | | UP (H), \ | |
15394 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
15395 | CF (N, G), CF (N, H) }, 8, 0 | |
15396 | #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ | |
15397 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
15398 | | UP (H) | UP (I), \ | |
15399 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
15400 | CF (N, G), CF (N, H), CF (N, I) }, 9, 0 | |
15401 | #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ | |
15402 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
15403 | | UP (H) | UP (I) | UP (J), \ | |
15404 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
15405 | CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0 | |
15406 | ||
15407 | /* The mode entries in the following table correspond to the "key" type of the | |
15408 | instruction variant, i.e. equivalent to that which would be specified after | |
15409 | the assembler mnemonic, which usually refers to the last vector operand. | |
15410 | (Signed/unsigned/polynomial types are not differentiated between though, and | |
15411 | are all mapped onto the same mode for a given element size.) The modes | |
15412 | listed per instruction should be the same as those defined for that | |
15413 | instruction's pattern in neon.md. | |
15414 | WARNING: Variants should be listed in the same increasing order as | |
15415 | neon_builtin_type_bits. */ | |
15416 | ||
15417 | static neon_builtin_datum neon_builtin_data[] = | |
15418 | { | |
15419 | { VAR10 (BINOP, vadd, | |
15420 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15421 | { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) }, | |
15422 | { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) }, | |
15423 | { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15424 | { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15425 | { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) }, | |
15426 | { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15427 | { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15428 | { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) }, | |
15429 | { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15430 | { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) }, | |
15431 | { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) }, | |
15432 | { VAR2 (TERNOP, vqdmlal, v4hi, v2si) }, | |
15433 | { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) }, | |
15434 | { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) }, | |
15435 | { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) }, | |
15436 | { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) }, | |
15437 | { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) }, | |
15438 | { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) }, | |
15439 | { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) }, | |
15440 | { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) }, | |
15441 | { VAR2 (BINOP, vqdmull, v4hi, v2si) }, | |
15442 | { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15443 | { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15444 | { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15445 | { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) }, | |
15446 | { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) }, | |
15447 | { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) }, | |
15448 | { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15449 | { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15450 | { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15451 | { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) }, | |
15452 | { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15453 | { VAR10 (BINOP, vsub, | |
15454 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15455 | { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) }, | |
15456 | { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) }, | |
15457 | { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15458 | { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15459 | { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) }, | |
15460 | { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15461 | { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15462 | { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15463 | { VAR2 (BINOP, vcage, v2sf, v4sf) }, | |
15464 | { VAR2 (BINOP, vcagt, v2sf, v4sf) }, | |
15465 | { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15466 | { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15467 | { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) }, | |
15468 | { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15469 | { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) }, | |
15470 | { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15471 | { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15472 | { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) }, | |
15473 | { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15474 | { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15475 | { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) }, | |
15476 | { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) }, | |
15477 | { VAR2 (BINOP, vrecps, v2sf, v4sf) }, | |
15478 | { VAR2 (BINOP, vrsqrts, v2sf, v4sf) }, | |
15479 | { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15480 | { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15481 | { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15482 | { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15483 | { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15484 | { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15485 | { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15486 | { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15487 | { VAR2 (UNOP, vcnt, v8qi, v16qi) }, | |
15488 | { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) }, | |
15489 | { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) }, | |
15490 | { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15491 | /* FIXME: vget_lane supports more variants than this! */ | |
15492 | { VAR10 (GETLANE, vget_lane, | |
15493 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15494 | { VAR10 (SETLANE, vset_lane, | |
15495 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15496 | { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) }, | |
15497 | { VAR10 (DUP, vdup_n, | |
15498 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15499 | { VAR10 (DUPLANE, vdup_lane, | |
15500 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15501 | { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) }, | |
15502 | { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15503 | { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15504 | { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) }, | |
15505 | { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) }, | |
15506 | { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) }, | |
15507 | { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) }, | |
15508 | { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15509 | { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15510 | { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) }, | |
15511 | { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) }, | |
15512 | { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15513 | { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) }, | |
15514 | { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) }, | |
15515 | { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15516 | { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15517 | { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) }, | |
15518 | { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) }, | |
15519 | { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15520 | { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) }, | |
15521 | { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) }, | |
15522 | { VAR10 (BINOP, vext, | |
15523 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15524 | { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15525 | { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) }, | |
15526 | { VAR2 (UNOP, vrev16, v8qi, v16qi) }, | |
15527 | { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) }, | |
15528 | { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) }, | |
15529 | { VAR10 (SELECT, vbsl, | |
15530 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15531 | { VAR1 (VTBL, vtbl1, v8qi) }, | |
15532 | { VAR1 (VTBL, vtbl2, v8qi) }, | |
15533 | { VAR1 (VTBL, vtbl3, v8qi) }, | |
15534 | { VAR1 (VTBL, vtbl4, v8qi) }, | |
15535 | { VAR1 (VTBX, vtbx1, v8qi) }, | |
15536 | { VAR1 (VTBX, vtbx2, v8qi) }, | |
15537 | { VAR1 (VTBX, vtbx3, v8qi) }, | |
15538 | { VAR1 (VTBX, vtbx4, v8qi) }, | |
15539 | { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15540 | { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15541 | { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15542 | { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) }, | |
15543 | { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) }, | |
15544 | { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) }, | |
15545 | { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) }, | |
15546 | { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) }, | |
15547 | { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15548 | { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15549 | { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15550 | { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15551 | { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15552 | { VAR10 (LOAD1, vld1, | |
15553 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15554 | { VAR10 (LOAD1LANE, vld1_lane, | |
15555 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15556 | { VAR10 (LOAD1, vld1_dup, | |
15557 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15558 | { VAR10 (STORE1, vst1, | |
15559 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15560 | { VAR10 (STORE1LANE, vst1_lane, | |
15561 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15562 | { VAR9 (LOADSTRUCT, | |
15563 | vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15564 | { VAR7 (LOADSTRUCTLANE, vld2_lane, | |
15565 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15566 | { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
15567 | { VAR9 (STORESTRUCT, vst2, | |
15568 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15569 | { VAR7 (STORESTRUCTLANE, vst2_lane, | |
15570 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15571 | { VAR9 (LOADSTRUCT, | |
15572 | vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15573 | { VAR7 (LOADSTRUCTLANE, vld3_lane, | |
15574 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15575 | { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
15576 | { VAR9 (STORESTRUCT, vst3, | |
15577 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15578 | { VAR7 (STORESTRUCTLANE, vst3_lane, | |
15579 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15580 | { VAR9 (LOADSTRUCT, vld4, | |
15581 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15582 | { VAR7 (LOADSTRUCTLANE, vld4_lane, | |
15583 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15584 | { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
15585 | { VAR9 (STORESTRUCT, vst4, | |
15586 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15587 | { VAR7 (STORESTRUCTLANE, vst4_lane, | |
15588 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15589 | { VAR10 (LOGICBINOP, vand, | |
15590 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15591 | { VAR10 (LOGICBINOP, vorr, | |
15592 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15593 | { VAR10 (BINOP, veor, | |
15594 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15595 | { VAR10 (LOGICBINOP, vbic, | |
15596 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15597 | { VAR10 (LOGICBINOP, vorn, | |
15598 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) } | |
15599 | }; | |
15600 | ||
15601 | #undef CF | |
15602 | #undef VAR1 | |
15603 | #undef VAR2 | |
15604 | #undef VAR3 | |
15605 | #undef VAR4 | |
15606 | #undef VAR5 | |
15607 | #undef VAR6 | |
15608 | #undef VAR7 | |
15609 | #undef VAR8 | |
15610 | #undef VAR9 | |
15611 | #undef VAR10 | |
15612 | ||
15613 | static void | |
15614 | arm_init_neon_builtins (void) | |
15615 | { | |
15616 | unsigned int i, fcode = ARM_BUILTIN_NEON_BASE; | |
15617 | ||
af06585a JM |
15618 | tree neon_intQI_type_node; |
15619 | tree neon_intHI_type_node; | |
15620 | tree neon_polyQI_type_node; | |
15621 | tree neon_polyHI_type_node; | |
15622 | tree neon_intSI_type_node; | |
15623 | tree neon_intDI_type_node; | |
15624 | tree neon_float_type_node; | |
15625 | ||
15626 | tree intQI_pointer_node; | |
15627 | tree intHI_pointer_node; | |
15628 | tree intSI_pointer_node; | |
15629 | tree intDI_pointer_node; | |
15630 | tree float_pointer_node; | |
15631 | ||
15632 | tree const_intQI_node; | |
15633 | tree const_intHI_node; | |
15634 | tree const_intSI_node; | |
15635 | tree const_intDI_node; | |
15636 | tree const_float_node; | |
15637 | ||
15638 | tree const_intQI_pointer_node; | |
15639 | tree const_intHI_pointer_node; | |
15640 | tree const_intSI_pointer_node; | |
15641 | tree const_intDI_pointer_node; | |
15642 | tree const_float_pointer_node; | |
15643 | ||
15644 | tree V8QI_type_node; | |
15645 | tree V4HI_type_node; | |
15646 | tree V2SI_type_node; | |
15647 | tree V2SF_type_node; | |
15648 | tree V16QI_type_node; | |
15649 | tree V8HI_type_node; | |
15650 | tree V4SI_type_node; | |
15651 | tree V4SF_type_node; | |
15652 | tree V2DI_type_node; | |
15653 | ||
15654 | tree intUQI_type_node; | |
15655 | tree intUHI_type_node; | |
15656 | tree intUSI_type_node; | |
15657 | tree intUDI_type_node; | |
15658 | ||
15659 | tree intEI_type_node; | |
15660 | tree intOI_type_node; | |
15661 | tree intCI_type_node; | |
15662 | tree intXI_type_node; | |
15663 | ||
15664 | tree V8QI_pointer_node; | |
15665 | tree V4HI_pointer_node; | |
15666 | tree V2SI_pointer_node; | |
15667 | tree V2SF_pointer_node; | |
15668 | tree V16QI_pointer_node; | |
15669 | tree V8HI_pointer_node; | |
15670 | tree V4SI_pointer_node; | |
15671 | tree V4SF_pointer_node; | |
15672 | tree V2DI_pointer_node; | |
15673 | ||
15674 | tree void_ftype_pv8qi_v8qi_v8qi; | |
15675 | tree void_ftype_pv4hi_v4hi_v4hi; | |
15676 | tree void_ftype_pv2si_v2si_v2si; | |
15677 | tree void_ftype_pv2sf_v2sf_v2sf; | |
15678 | tree void_ftype_pdi_di_di; | |
15679 | tree void_ftype_pv16qi_v16qi_v16qi; | |
15680 | tree void_ftype_pv8hi_v8hi_v8hi; | |
15681 | tree void_ftype_pv4si_v4si_v4si; | |
15682 | tree void_ftype_pv4sf_v4sf_v4sf; | |
15683 | tree void_ftype_pv2di_v2di_v2di; | |
15684 | ||
15685 | tree reinterp_ftype_dreg[5][5]; | |
15686 | tree reinterp_ftype_qreg[5][5]; | |
15687 | tree dreg_types[5], qreg_types[5]; | |
15688 | ||
88f77cba JB |
15689 | /* Create distinguished type nodes for NEON vector element types, |
15690 | and pointers to values of such types, so we can detect them later. */ | |
af06585a JM |
15691 | neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); |
15692 | neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
15693 | neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); | |
15694 | neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
15695 | neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode)); | |
15696 | neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode)); | |
15697 | neon_float_type_node = make_node (REAL_TYPE); | |
15698 | TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; | |
15699 | layout_type (neon_float_type_node); | |
15700 | ||
bcbdbbb0 JM |
15701 | /* Define typedefs which exactly correspond to the modes we are basing vector |
15702 | types on. If you change these names you'll need to change | |
15703 | the table used by arm_mangle_type too. */ | |
15704 | (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node, | |
15705 | "__builtin_neon_qi"); | |
15706 | (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, | |
15707 | "__builtin_neon_hi"); | |
15708 | (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, | |
15709 | "__builtin_neon_si"); | |
15710 | (*lang_hooks.types.register_builtin_type) (neon_float_type_node, | |
15711 | "__builtin_neon_sf"); | |
15712 | (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node, | |
15713 | "__builtin_neon_di"); | |
15714 | (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node, | |
15715 | "__builtin_neon_poly8"); | |
15716 | (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node, | |
15717 | "__builtin_neon_poly16"); | |
15718 | ||
af06585a JM |
15719 | intQI_pointer_node = build_pointer_type (neon_intQI_type_node); |
15720 | intHI_pointer_node = build_pointer_type (neon_intHI_type_node); | |
15721 | intSI_pointer_node = build_pointer_type (neon_intSI_type_node); | |
15722 | intDI_pointer_node = build_pointer_type (neon_intDI_type_node); | |
15723 | float_pointer_node = build_pointer_type (neon_float_type_node); | |
88f77cba JB |
15724 | |
15725 | /* Next create constant-qualified versions of the above types. */ | |
af06585a JM |
15726 | const_intQI_node = build_qualified_type (neon_intQI_type_node, |
15727 | TYPE_QUAL_CONST); | |
15728 | const_intHI_node = build_qualified_type (neon_intHI_type_node, | |
15729 | TYPE_QUAL_CONST); | |
15730 | const_intSI_node = build_qualified_type (neon_intSI_type_node, | |
15731 | TYPE_QUAL_CONST); | |
15732 | const_intDI_node = build_qualified_type (neon_intDI_type_node, | |
15733 | TYPE_QUAL_CONST); | |
15734 | const_float_node = build_qualified_type (neon_float_type_node, | |
15735 | TYPE_QUAL_CONST); | |
15736 | ||
15737 | const_intQI_pointer_node = build_pointer_type (const_intQI_node); | |
15738 | const_intHI_pointer_node = build_pointer_type (const_intHI_node); | |
15739 | const_intSI_pointer_node = build_pointer_type (const_intSI_node); | |
15740 | const_intDI_pointer_node = build_pointer_type (const_intDI_node); | |
15741 | const_float_pointer_node = build_pointer_type (const_float_node); | |
88f77cba JB |
15742 | |
15743 | /* Now create vector types based on our NEON element types. */ | |
15744 | /* 64-bit vectors. */ | |
af06585a | 15745 | V8QI_type_node = |
88f77cba | 15746 | build_vector_type_for_mode (neon_intQI_type_node, V8QImode); |
af06585a | 15747 | V4HI_type_node = |
88f77cba | 15748 | build_vector_type_for_mode (neon_intHI_type_node, V4HImode); |
af06585a | 15749 | V2SI_type_node = |
88f77cba | 15750 | build_vector_type_for_mode (neon_intSI_type_node, V2SImode); |
af06585a | 15751 | V2SF_type_node = |
88f77cba JB |
15752 | build_vector_type_for_mode (neon_float_type_node, V2SFmode); |
15753 | /* 128-bit vectors. */ | |
af06585a | 15754 | V16QI_type_node = |
88f77cba | 15755 | build_vector_type_for_mode (neon_intQI_type_node, V16QImode); |
af06585a | 15756 | V8HI_type_node = |
88f77cba | 15757 | build_vector_type_for_mode (neon_intHI_type_node, V8HImode); |
af06585a | 15758 | V4SI_type_node = |
88f77cba | 15759 | build_vector_type_for_mode (neon_intSI_type_node, V4SImode); |
af06585a | 15760 | V4SF_type_node = |
88f77cba | 15761 | build_vector_type_for_mode (neon_float_type_node, V4SFmode); |
af06585a | 15762 | V2DI_type_node = |
88f77cba JB |
15763 | build_vector_type_for_mode (neon_intDI_type_node, V2DImode); |
15764 | ||
15765 | /* Unsigned integer types for various mode sizes. */ | |
af06585a JM |
15766 | intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode)); |
15767 | intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode)); | |
15768 | intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode)); | |
15769 | intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode)); | |
88f77cba | 15770 | |
bcbdbbb0 JM |
15771 | (*lang_hooks.types.register_builtin_type) (intUQI_type_node, |
15772 | "__builtin_neon_uqi"); | |
15773 | (*lang_hooks.types.register_builtin_type) (intUHI_type_node, | |
15774 | "__builtin_neon_uhi"); | |
15775 | (*lang_hooks.types.register_builtin_type) (intUSI_type_node, | |
15776 | "__builtin_neon_usi"); | |
15777 | (*lang_hooks.types.register_builtin_type) (intUDI_type_node, | |
15778 | "__builtin_neon_udi"); | |
15779 | ||
88f77cba | 15780 | /* Opaque integer types for structures of vectors. */ |
af06585a JM |
15781 | intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode)); |
15782 | intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode)); | |
15783 | intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode)); | |
15784 | intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode)); | |
88f77cba | 15785 | |
bcbdbbb0 JM |
15786 | (*lang_hooks.types.register_builtin_type) (intTI_type_node, |
15787 | "__builtin_neon_ti"); | |
15788 | (*lang_hooks.types.register_builtin_type) (intEI_type_node, | |
15789 | "__builtin_neon_ei"); | |
15790 | (*lang_hooks.types.register_builtin_type) (intOI_type_node, | |
15791 | "__builtin_neon_oi"); | |
15792 | (*lang_hooks.types.register_builtin_type) (intCI_type_node, | |
15793 | "__builtin_neon_ci"); | |
15794 | (*lang_hooks.types.register_builtin_type) (intXI_type_node, | |
15795 | "__builtin_neon_xi"); | |
15796 | ||
88f77cba | 15797 | /* Pointers to vector types. */ |
af06585a JM |
15798 | V8QI_pointer_node = build_pointer_type (V8QI_type_node); |
15799 | V4HI_pointer_node = build_pointer_type (V4HI_type_node); | |
15800 | V2SI_pointer_node = build_pointer_type (V2SI_type_node); | |
15801 | V2SF_pointer_node = build_pointer_type (V2SF_type_node); | |
15802 | V16QI_pointer_node = build_pointer_type (V16QI_type_node); | |
15803 | V8HI_pointer_node = build_pointer_type (V8HI_type_node); | |
15804 | V4SI_pointer_node = build_pointer_type (V4SI_type_node); | |
15805 | V4SF_pointer_node = build_pointer_type (V4SF_type_node); | |
15806 | V2DI_pointer_node = build_pointer_type (V2DI_type_node); | |
88f77cba JB |
15807 | |
15808 | /* Operations which return results as pairs. */ | |
af06585a | 15809 | void_ftype_pv8qi_v8qi_v8qi = |
88f77cba JB |
15810 | build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node, |
15811 | V8QI_type_node, NULL); | |
af06585a | 15812 | void_ftype_pv4hi_v4hi_v4hi = |
88f77cba JB |
15813 | build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node, |
15814 | V4HI_type_node, NULL); | |
af06585a | 15815 | void_ftype_pv2si_v2si_v2si = |
88f77cba JB |
15816 | build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node, |
15817 | V2SI_type_node, NULL); | |
af06585a | 15818 | void_ftype_pv2sf_v2sf_v2sf = |
88f77cba JB |
15819 | build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node, |
15820 | V2SF_type_node, NULL); | |
af06585a | 15821 | void_ftype_pdi_di_di = |
88f77cba JB |
15822 | build_function_type_list (void_type_node, intDI_pointer_node, |
15823 | neon_intDI_type_node, neon_intDI_type_node, NULL); | |
af06585a | 15824 | void_ftype_pv16qi_v16qi_v16qi = |
88f77cba JB |
15825 | build_function_type_list (void_type_node, V16QI_pointer_node, |
15826 | V16QI_type_node, V16QI_type_node, NULL); | |
af06585a | 15827 | void_ftype_pv8hi_v8hi_v8hi = |
88f77cba JB |
15828 | build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node, |
15829 | V8HI_type_node, NULL); | |
af06585a | 15830 | void_ftype_pv4si_v4si_v4si = |
88f77cba JB |
15831 | build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node, |
15832 | V4SI_type_node, NULL); | |
af06585a | 15833 | void_ftype_pv4sf_v4sf_v4sf = |
88f77cba JB |
15834 | build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node, |
15835 | V4SF_type_node, NULL); | |
af06585a | 15836 | void_ftype_pv2di_v2di_v2di = |
88f77cba JB |
15837 | build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node, |
15838 | V2DI_type_node, NULL); | |
15839 | ||
88f77cba JB |
15840 | dreg_types[0] = V8QI_type_node; |
15841 | dreg_types[1] = V4HI_type_node; | |
15842 | dreg_types[2] = V2SI_type_node; | |
15843 | dreg_types[3] = V2SF_type_node; | |
15844 | dreg_types[4] = neon_intDI_type_node; | |
15845 | ||
15846 | qreg_types[0] = V16QI_type_node; | |
15847 | qreg_types[1] = V8HI_type_node; | |
15848 | qreg_types[2] = V4SI_type_node; | |
15849 | qreg_types[3] = V4SF_type_node; | |
15850 | qreg_types[4] = V2DI_type_node; | |
15851 | ||
15852 | for (i = 0; i < 5; i++) | |
15853 | { | |
15854 | int j; | |
15855 | for (j = 0; j < 5; j++) | |
15856 | { | |
15857 | reinterp_ftype_dreg[i][j] | |
15858 | = build_function_type_list (dreg_types[i], dreg_types[j], NULL); | |
15859 | reinterp_ftype_qreg[i][j] | |
15860 | = build_function_type_list (qreg_types[i], qreg_types[j], NULL); | |
15861 | } | |
15862 | } | |
15863 | ||
15864 | for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++) | |
15865 | { | |
15866 | neon_builtin_datum *d = &neon_builtin_data[i]; | |
15867 | unsigned int j, codeidx = 0; | |
15868 | ||
15869 | d->base_fcode = fcode; | |
15870 | ||
15871 | for (j = 0; j < T_MAX; j++) | |
15872 | { | |
15873 | const char* const modenames[] = { | |
15874 | "v8qi", "v4hi", "v2si", "v2sf", "di", | |
15875 | "v16qi", "v8hi", "v4si", "v4sf", "v2di" | |
15876 | }; | |
15877 | char namebuf[60]; | |
15878 | tree ftype = NULL; | |
15879 | enum insn_code icode; | |
15880 | int is_load = 0, is_store = 0; | |
15881 | ||
15882 | if ((d->bits & (1 << j)) == 0) | |
15883 | continue; | |
15884 | ||
15885 | icode = d->codes[codeidx++]; | |
15886 | ||
15887 | switch (d->itype) | |
15888 | { | |
15889 | case NEON_LOAD1: | |
15890 | case NEON_LOAD1LANE: | |
15891 | case NEON_LOADSTRUCT: | |
15892 | case NEON_LOADSTRUCTLANE: | |
15893 | is_load = 1; | |
15894 | /* Fall through. */ | |
15895 | case NEON_STORE1: | |
15896 | case NEON_STORE1LANE: | |
15897 | case NEON_STORESTRUCT: | |
15898 | case NEON_STORESTRUCTLANE: | |
15899 | if (!is_load) | |
15900 | is_store = 1; | |
15901 | /* Fall through. */ | |
15902 | case NEON_UNOP: | |
15903 | case NEON_BINOP: | |
15904 | case NEON_LOGICBINOP: | |
15905 | case NEON_SHIFTINSERT: | |
15906 | case NEON_TERNOP: | |
15907 | case NEON_GETLANE: | |
15908 | case NEON_SETLANE: | |
15909 | case NEON_CREATE: | |
15910 | case NEON_DUP: | |
15911 | case NEON_DUPLANE: | |
15912 | case NEON_SHIFTIMM: | |
15913 | case NEON_SHIFTACC: | |
15914 | case NEON_COMBINE: | |
15915 | case NEON_SPLIT: | |
15916 | case NEON_CONVERT: | |
15917 | case NEON_FIXCONV: | |
15918 | case NEON_LANEMUL: | |
15919 | case NEON_LANEMULL: | |
15920 | case NEON_LANEMULH: | |
15921 | case NEON_LANEMAC: | |
15922 | case NEON_SCALARMUL: | |
15923 | case NEON_SCALARMULL: | |
15924 | case NEON_SCALARMULH: | |
15925 | case NEON_SCALARMAC: | |
15926 | case NEON_SELECT: | |
15927 | case NEON_VTBL: | |
15928 | case NEON_VTBX: | |
15929 | { | |
15930 | int k; | |
15931 | tree return_type = void_type_node, args = void_list_node; | |
15932 | ||
15933 | /* Build a function type directly from the insn_data for this | |
15934 | builtin. The build_function_type() function takes care of | |
15935 | removing duplicates for us. */ | |
15936 | for (k = insn_data[icode].n_operands - 1; k >= 0; k--) | |
15937 | { | |
15938 | tree eltype; | |
15939 | ||
15940 | if (is_load && k == 1) | |
15941 | { | |
15942 | /* Neon load patterns always have the memory operand | |
15943 | (a SImode pointer) in the operand 1 position. We | |
15944 | want a const pointer to the element type in that | |
15945 | position. */ | |
15946 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
15947 | ||
15948 | switch (1 << j) | |
15949 | { | |
15950 | case T_V8QI: | |
15951 | case T_V16QI: | |
15952 | eltype = const_intQI_pointer_node; | |
15953 | break; | |
15954 | ||
15955 | case T_V4HI: | |
15956 | case T_V8HI: | |
15957 | eltype = const_intHI_pointer_node; | |
15958 | break; | |
15959 | ||
15960 | case T_V2SI: | |
15961 | case T_V4SI: | |
15962 | eltype = const_intSI_pointer_node; | |
15963 | break; | |
15964 | ||
15965 | case T_V2SF: | |
15966 | case T_V4SF: | |
15967 | eltype = const_float_pointer_node; | |
15968 | break; | |
15969 | ||
15970 | case T_DI: | |
15971 | case T_V2DI: | |
15972 | eltype = const_intDI_pointer_node; | |
15973 | break; | |
15974 | ||
15975 | default: gcc_unreachable (); | |
15976 | } | |
15977 | } | |
15978 | else if (is_store && k == 0) | |
15979 | { | |
15980 | /* Similarly, Neon store patterns use operand 0 as | |
15981 | the memory location to store to (a SImode pointer). | |
15982 | Use a pointer to the element type of the store in | |
15983 | that position. */ | |
15984 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
15985 | ||
15986 | switch (1 << j) | |
15987 | { | |
15988 | case T_V8QI: | |
15989 | case T_V16QI: | |
15990 | eltype = intQI_pointer_node; | |
15991 | break; | |
15992 | ||
15993 | case T_V4HI: | |
15994 | case T_V8HI: | |
15995 | eltype = intHI_pointer_node; | |
15996 | break; | |
15997 | ||
15998 | case T_V2SI: | |
15999 | case T_V4SI: | |
16000 | eltype = intSI_pointer_node; | |
16001 | break; | |
16002 | ||
16003 | case T_V2SF: | |
16004 | case T_V4SF: | |
16005 | eltype = float_pointer_node; | |
16006 | break; | |
16007 | ||
16008 | case T_DI: | |
16009 | case T_V2DI: | |
16010 | eltype = intDI_pointer_node; | |
16011 | break; | |
16012 | ||
16013 | default: gcc_unreachable (); | |
16014 | } | |
16015 | } | |
16016 | else | |
16017 | { | |
16018 | switch (insn_data[icode].operand[k].mode) | |
16019 | { | |
16020 | case VOIDmode: eltype = void_type_node; break; | |
16021 | /* Scalars. */ | |
16022 | case QImode: eltype = neon_intQI_type_node; break; | |
16023 | case HImode: eltype = neon_intHI_type_node; break; | |
16024 | case SImode: eltype = neon_intSI_type_node; break; | |
16025 | case SFmode: eltype = neon_float_type_node; break; | |
16026 | case DImode: eltype = neon_intDI_type_node; break; | |
16027 | case TImode: eltype = intTI_type_node; break; | |
16028 | case EImode: eltype = intEI_type_node; break; | |
16029 | case OImode: eltype = intOI_type_node; break; | |
16030 | case CImode: eltype = intCI_type_node; break; | |
16031 | case XImode: eltype = intXI_type_node; break; | |
16032 | /* 64-bit vectors. */ | |
16033 | case V8QImode: eltype = V8QI_type_node; break; | |
16034 | case V4HImode: eltype = V4HI_type_node; break; | |
16035 | case V2SImode: eltype = V2SI_type_node; break; | |
16036 | case V2SFmode: eltype = V2SF_type_node; break; | |
16037 | /* 128-bit vectors. */ | |
16038 | case V16QImode: eltype = V16QI_type_node; break; | |
16039 | case V8HImode: eltype = V8HI_type_node; break; | |
16040 | case V4SImode: eltype = V4SI_type_node; break; | |
16041 | case V4SFmode: eltype = V4SF_type_node; break; | |
16042 | case V2DImode: eltype = V2DI_type_node; break; | |
16043 | default: gcc_unreachable (); | |
16044 | } | |
16045 | } | |
16046 | ||
16047 | if (k == 0 && !is_store) | |
16048 | return_type = eltype; | |
16049 | else | |
16050 | args = tree_cons (NULL_TREE, eltype, args); | |
16051 | } | |
16052 | ||
16053 | ftype = build_function_type (return_type, args); | |
16054 | } | |
16055 | break; | |
16056 | ||
16057 | case NEON_RESULTPAIR: | |
16058 | { | |
16059 | switch (insn_data[icode].operand[1].mode) | |
16060 | { | |
16061 | case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break; | |
16062 | case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break; | |
16063 | case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break; | |
16064 | case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break; | |
16065 | case DImode: ftype = void_ftype_pdi_di_di; break; | |
16066 | case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break; | |
16067 | case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break; | |
16068 | case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break; | |
16069 | case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break; | |
16070 | case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break; | |
16071 | default: gcc_unreachable (); | |
16072 | } | |
16073 | } | |
16074 | break; | |
16075 | ||
16076 | case NEON_REINTERP: | |
16077 | { | |
16078 | /* We iterate over 5 doubleword types, then 5 quadword | |
16079 | types. */ | |
16080 | int rhs = j % 5; | |
16081 | switch (insn_data[icode].operand[0].mode) | |
16082 | { | |
16083 | case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; | |
16084 | case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break; | |
16085 | case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break; | |
16086 | case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break; | |
16087 | case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break; | |
16088 | case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break; | |
16089 | case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break; | |
16090 | case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break; | |
16091 | case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break; | |
16092 | case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break; | |
16093 | default: gcc_unreachable (); | |
16094 | } | |
16095 | } | |
16096 | break; | |
16097 | ||
16098 | default: | |
16099 | gcc_unreachable (); | |
16100 | } | |
16101 | ||
16102 | gcc_assert (ftype != NULL); | |
16103 | ||
16104 | sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]); | |
16105 | ||
16106 | add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL, | |
16107 | NULL_TREE); | |
16108 | } | |
16109 | } | |
16110 | } | |
16111 | ||
5a9335ef NC |
16112 | static void |
16113 | arm_init_builtins (void) | |
16114 | { | |
d3585b76 DJ |
16115 | arm_init_tls_builtins (); |
16116 | ||
5a9335ef NC |
16117 | if (TARGET_REALLY_IWMMXT) |
16118 | arm_init_iwmmxt_builtins (); | |
88f77cba JB |
16119 | |
16120 | if (TARGET_NEON) | |
16121 | arm_init_neon_builtins (); | |
5a9335ef NC |
16122 | } |
16123 | ||
16124 | /* Errors in the source file can cause expand_expr to return const0_rtx | |
16125 | where we expect a vector. To avoid crashing, use one of the vector | |
16126 | clear instructions. */ | |
16127 | ||
16128 | static rtx | |
16129 | safe_vector_operand (rtx x, enum machine_mode mode) | |
16130 | { | |
16131 | if (x != const0_rtx) | |
16132 | return x; | |
16133 | x = gen_reg_rtx (mode); | |
16134 | ||
16135 | emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x | |
16136 | : gen_rtx_SUBREG (DImode, x, 0))); | |
16137 | return x; | |
16138 | } | |
16139 | ||
16140 | /* Subroutine of arm_expand_builtin to take care of binop insns. */ | |
16141 | ||
16142 | static rtx | |
16143 | arm_expand_binop_builtin (enum insn_code icode, | |
5039610b | 16144 | tree exp, rtx target) |
5a9335ef NC |
16145 | { |
16146 | rtx pat; | |
5039610b SL |
16147 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
16148 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
16149 | rtx op0 = expand_normal (arg0); |
16150 | rtx op1 = expand_normal (arg1); | |
5a9335ef NC |
16151 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
16152 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
16153 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
16154 | ||
16155 | if (VECTOR_MODE_P (mode0)) | |
16156 | op0 = safe_vector_operand (op0, mode0); | |
16157 | if (VECTOR_MODE_P (mode1)) | |
16158 | op1 = safe_vector_operand (op1, mode1); | |
16159 | ||
16160 | if (! target | |
16161 | || GET_MODE (target) != tmode | |
16162 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16163 | target = gen_reg_rtx (tmode); | |
16164 | ||
e6d29d15 | 16165 | gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); |
5a9335ef NC |
16166 | |
16167 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16168 | op0 = copy_to_mode_reg (mode0, op0); | |
16169 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16170 | op1 = copy_to_mode_reg (mode1, op1); | |
16171 | ||
16172 | pat = GEN_FCN (icode) (target, op0, op1); | |
16173 | if (! pat) | |
16174 | return 0; | |
16175 | emit_insn (pat); | |
16176 | return target; | |
16177 | } | |
16178 | ||
16179 | /* Subroutine of arm_expand_builtin to take care of unop insns. */ | |
16180 | ||
16181 | static rtx | |
16182 | arm_expand_unop_builtin (enum insn_code icode, | |
5039610b | 16183 | tree exp, rtx target, int do_load) |
5a9335ef NC |
16184 | { |
16185 | rtx pat; | |
5039610b | 16186 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 16187 | rtx op0 = expand_normal (arg0); |
5a9335ef NC |
16188 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
16189 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
16190 | ||
16191 | if (! target | |
16192 | || GET_MODE (target) != tmode | |
16193 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16194 | target = gen_reg_rtx (tmode); | |
16195 | if (do_load) | |
16196 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
16197 | else | |
16198 | { | |
16199 | if (VECTOR_MODE_P (mode0)) | |
16200 | op0 = safe_vector_operand (op0, mode0); | |
16201 | ||
16202 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16203 | op0 = copy_to_mode_reg (mode0, op0); | |
16204 | } | |
16205 | ||
16206 | pat = GEN_FCN (icode) (target, op0); | |
16207 | if (! pat) | |
16208 | return 0; | |
16209 | emit_insn (pat); | |
16210 | return target; | |
16211 | } | |
16212 | ||
88f77cba JB |
16213 | static int |
16214 | neon_builtin_compare (const void *a, const void *b) | |
16215 | { | |
5ead67f6 KG |
16216 | const neon_builtin_datum *const key = (const neon_builtin_datum *) a; |
16217 | const neon_builtin_datum *const memb = (const neon_builtin_datum *) b; | |
88f77cba JB |
16218 | unsigned int soughtcode = key->base_fcode; |
16219 | ||
16220 | if (soughtcode >= memb->base_fcode | |
16221 | && soughtcode < memb->base_fcode + memb->num_vars) | |
16222 | return 0; | |
16223 | else if (soughtcode < memb->base_fcode) | |
16224 | return -1; | |
16225 | else | |
16226 | return 1; | |
16227 | } | |
16228 | ||
16229 | static enum insn_code | |
16230 | locate_neon_builtin_icode (int fcode, neon_itype *itype) | |
16231 | { | |
16232 | neon_builtin_datum key, *found; | |
16233 | int idx; | |
16234 | ||
16235 | key.base_fcode = fcode; | |
5ead67f6 KG |
16236 | found = (neon_builtin_datum *) |
16237 | bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data), | |
88f77cba JB |
16238 | sizeof (neon_builtin_data[0]), neon_builtin_compare); |
16239 | gcc_assert (found); | |
16240 | idx = fcode - (int) found->base_fcode; | |
16241 | gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars); | |
16242 | ||
16243 | if (itype) | |
16244 | *itype = found->itype; | |
16245 | ||
16246 | return found->codes[idx]; | |
16247 | } | |
16248 | ||
16249 | typedef enum { | |
16250 | NEON_ARG_COPY_TO_REG, | |
16251 | NEON_ARG_CONSTANT, | |
16252 | NEON_ARG_STOP | |
16253 | } builtin_arg; | |
16254 | ||
16255 | #define NEON_MAX_BUILTIN_ARGS 5 | |
16256 | ||
16257 | /* Expand a Neon builtin. */ | |
16258 | static rtx | |
16259 | arm_expand_neon_args (rtx target, int icode, int have_retval, | |
16260 | tree exp, ...) | |
16261 | { | |
16262 | va_list ap; | |
16263 | rtx pat; | |
16264 | tree arg[NEON_MAX_BUILTIN_ARGS]; | |
16265 | rtx op[NEON_MAX_BUILTIN_ARGS]; | |
16266 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
16267 | enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; | |
16268 | int argc = 0; | |
16269 | ||
16270 | if (have_retval | |
16271 | && (!target | |
16272 | || GET_MODE (target) != tmode | |
16273 | || !(*insn_data[icode].operand[0].predicate) (target, tmode))) | |
16274 | target = gen_reg_rtx (tmode); | |
16275 | ||
16276 | va_start (ap, exp); | |
16277 | ||
16278 | for (;;) | |
16279 | { | |
16280 | builtin_arg thisarg = va_arg (ap, int); | |
16281 | ||
16282 | if (thisarg == NEON_ARG_STOP) | |
16283 | break; | |
16284 | else | |
16285 | { | |
16286 | arg[argc] = CALL_EXPR_ARG (exp, argc); | |
16287 | op[argc] = expand_normal (arg[argc]); | |
16288 | mode[argc] = insn_data[icode].operand[argc + have_retval].mode; | |
16289 | ||
16290 | switch (thisarg) | |
16291 | { | |
16292 | case NEON_ARG_COPY_TO_REG: | |
16293 | /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ | |
16294 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
16295 | (op[argc], mode[argc])) | |
16296 | op[argc] = copy_to_mode_reg (mode[argc], op[argc]); | |
16297 | break; | |
16298 | ||
16299 | case NEON_ARG_CONSTANT: | |
16300 | /* FIXME: This error message is somewhat unhelpful. */ | |
16301 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
16302 | (op[argc], mode[argc])) | |
16303 | error ("argument must be a constant"); | |
16304 | break; | |
16305 | ||
16306 | case NEON_ARG_STOP: | |
16307 | gcc_unreachable (); | |
16308 | } | |
16309 | ||
16310 | argc++; | |
16311 | } | |
16312 | } | |
16313 | ||
16314 | va_end (ap); | |
16315 | ||
16316 | if (have_retval) | |
16317 | switch (argc) | |
16318 | { | |
16319 | case 1: | |
16320 | pat = GEN_FCN (icode) (target, op[0]); | |
16321 | break; | |
16322 | ||
16323 | case 2: | |
16324 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
16325 | break; | |
16326 | ||
16327 | case 3: | |
16328 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2]); | |
16329 | break; | |
16330 | ||
16331 | case 4: | |
16332 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]); | |
16333 | break; | |
16334 | ||
16335 | case 5: | |
16336 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); | |
16337 | break; | |
16338 | ||
16339 | default: | |
16340 | gcc_unreachable (); | |
16341 | } | |
16342 | else | |
16343 | switch (argc) | |
16344 | { | |
16345 | case 1: | |
16346 | pat = GEN_FCN (icode) (op[0]); | |
16347 | break; | |
16348 | ||
16349 | case 2: | |
16350 | pat = GEN_FCN (icode) (op[0], op[1]); | |
16351 | break; | |
16352 | ||
16353 | case 3: | |
16354 | pat = GEN_FCN (icode) (op[0], op[1], op[2]); | |
16355 | break; | |
16356 | ||
16357 | case 4: | |
16358 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); | |
16359 | break; | |
16360 | ||
16361 | case 5: | |
16362 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); | |
16363 | break; | |
16364 | ||
16365 | default: | |
16366 | gcc_unreachable (); | |
16367 | } | |
16368 | ||
16369 | if (!pat) | |
16370 | return 0; | |
16371 | ||
16372 | emit_insn (pat); | |
16373 | ||
16374 | return target; | |
16375 | } | |
16376 | ||
16377 | /* Expand a Neon builtin. These are "special" because they don't have symbolic | |
16378 | constants defined per-instruction or per instruction-variant. Instead, the | |
16379 | required info is looked up in the table neon_builtin_data. */ | |
16380 | static rtx | |
16381 | arm_expand_neon_builtin (int fcode, tree exp, rtx target) | |
16382 | { | |
16383 | neon_itype itype; | |
16384 | enum insn_code icode = locate_neon_builtin_icode (fcode, &itype); | |
16385 | ||
16386 | switch (itype) | |
16387 | { | |
16388 | case NEON_UNOP: | |
16389 | case NEON_CONVERT: | |
16390 | case NEON_DUPLANE: | |
16391 | return arm_expand_neon_args (target, icode, 1, exp, | |
16392 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16393 | ||
16394 | case NEON_BINOP: | |
16395 | case NEON_SETLANE: | |
16396 | case NEON_SCALARMUL: | |
16397 | case NEON_SCALARMULL: | |
16398 | case NEON_SCALARMULH: | |
16399 | case NEON_SHIFTINSERT: | |
16400 | case NEON_LOGICBINOP: | |
16401 | return arm_expand_neon_args (target, icode, 1, exp, | |
16402 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16403 | NEON_ARG_STOP); | |
16404 | ||
16405 | case NEON_TERNOP: | |
16406 | return arm_expand_neon_args (target, icode, 1, exp, | |
16407 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16408 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16409 | ||
16410 | case NEON_GETLANE: | |
16411 | case NEON_FIXCONV: | |
16412 | case NEON_SHIFTIMM: | |
16413 | return arm_expand_neon_args (target, icode, 1, exp, | |
16414 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, | |
16415 | NEON_ARG_STOP); | |
16416 | ||
16417 | case NEON_CREATE: | |
16418 | return arm_expand_neon_args (target, icode, 1, exp, | |
16419 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16420 | ||
16421 | case NEON_DUP: | |
16422 | case NEON_SPLIT: | |
16423 | case NEON_REINTERP: | |
16424 | return arm_expand_neon_args (target, icode, 1, exp, | |
16425 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16426 | ||
16427 | case NEON_COMBINE: | |
16428 | case NEON_VTBL: | |
16429 | return arm_expand_neon_args (target, icode, 1, exp, | |
16430 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16431 | ||
16432 | case NEON_RESULTPAIR: | |
16433 | return arm_expand_neon_args (target, icode, 0, exp, | |
16434 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16435 | NEON_ARG_STOP); | |
16436 | ||
16437 | case NEON_LANEMUL: | |
16438 | case NEON_LANEMULL: | |
16439 | case NEON_LANEMULH: | |
16440 | return arm_expand_neon_args (target, icode, 1, exp, | |
16441 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16442 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16443 | ||
16444 | case NEON_LANEMAC: | |
16445 | return arm_expand_neon_args (target, icode, 1, exp, | |
16446 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16447 | NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16448 | ||
16449 | case NEON_SHIFTACC: | |
16450 | return arm_expand_neon_args (target, icode, 1, exp, | |
16451 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16452 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16453 | ||
16454 | case NEON_SCALARMAC: | |
16455 | return arm_expand_neon_args (target, icode, 1, exp, | |
16456 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16457 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16458 | ||
16459 | case NEON_SELECT: | |
16460 | case NEON_VTBX: | |
16461 | return arm_expand_neon_args (target, icode, 1, exp, | |
16462 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16463 | NEON_ARG_STOP); | |
16464 | ||
16465 | case NEON_LOAD1: | |
16466 | case NEON_LOADSTRUCT: | |
16467 | return arm_expand_neon_args (target, icode, 1, exp, | |
16468 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16469 | ||
16470 | case NEON_LOAD1LANE: | |
16471 | case NEON_LOADSTRUCTLANE: | |
16472 | return arm_expand_neon_args (target, icode, 1, exp, | |
16473 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16474 | NEON_ARG_STOP); | |
16475 | ||
16476 | case NEON_STORE1: | |
16477 | case NEON_STORESTRUCT: | |
16478 | return arm_expand_neon_args (target, icode, 0, exp, | |
16479 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16480 | ||
16481 | case NEON_STORE1LANE: | |
16482 | case NEON_STORESTRUCTLANE: | |
16483 | return arm_expand_neon_args (target, icode, 0, exp, | |
16484 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16485 | NEON_ARG_STOP); | |
16486 | } | |
16487 | ||
16488 | gcc_unreachable (); | |
16489 | } | |
16490 | ||
16491 | /* Emit code to reinterpret one Neon type as another, without altering bits. */ | |
16492 | void | |
16493 | neon_reinterpret (rtx dest, rtx src) | |
16494 | { | |
16495 | emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src)); | |
16496 | } | |
16497 | ||
16498 | /* Emit code to place a Neon pair result in memory locations (with equal | |
16499 | registers). */ | |
16500 | void | |
16501 | neon_emit_pair_result_insn (enum machine_mode mode, | |
16502 | rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr, | |
16503 | rtx op1, rtx op2) | |
16504 | { | |
16505 | rtx mem = gen_rtx_MEM (mode, destaddr); | |
16506 | rtx tmp1 = gen_reg_rtx (mode); | |
16507 | rtx tmp2 = gen_reg_rtx (mode); | |
16508 | ||
16509 | emit_insn (intfn (tmp1, op1, tmp2, op2)); | |
16510 | ||
16511 | emit_move_insn (mem, tmp1); | |
16512 | mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); | |
16513 | emit_move_insn (mem, tmp2); | |
16514 | } | |
16515 | ||
16516 | /* Set up operands for a register copy from src to dest, taking care not to | |
16517 | clobber registers in the process. | |
16518 | FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't | |
16519 | be called with a large N, so that should be OK. */ | |
16520 | ||
16521 | void | |
16522 | neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count) | |
16523 | { | |
16524 | unsigned int copied = 0, opctr = 0; | |
16525 | unsigned int done = (1 << count) - 1; | |
16526 | unsigned int i, j; | |
16527 | ||
16528 | while (copied != done) | |
16529 | { | |
16530 | for (i = 0; i < count; i++) | |
16531 | { | |
16532 | int good = 1; | |
16533 | ||
16534 | for (j = 0; good && j < count; j++) | |
16535 | if (i != j && (copied & (1 << j)) == 0 | |
16536 | && reg_overlap_mentioned_p (src[j], dest[i])) | |
16537 | good = 0; | |
16538 | ||
16539 | if (good) | |
16540 | { | |
16541 | operands[opctr++] = dest[i]; | |
16542 | operands[opctr++] = src[i]; | |
16543 | copied |= 1 << i; | |
16544 | } | |
16545 | } | |
16546 | } | |
16547 | ||
16548 | gcc_assert (opctr == count * 2); | |
16549 | } | |
16550 | ||
5a9335ef NC |
16551 | /* Expand an expression EXP that calls a built-in function, |
16552 | with result going to TARGET if that's convenient | |
16553 | (and in mode MODE if that's convenient). | |
16554 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
16555 | IGNORE is nonzero if the value is to be ignored. */ | |
16556 | ||
16557 | static rtx | |
16558 | arm_expand_builtin (tree exp, | |
16559 | rtx target, | |
16560 | rtx subtarget ATTRIBUTE_UNUSED, | |
16561 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
16562 | int ignore ATTRIBUTE_UNUSED) | |
16563 | { | |
16564 | const struct builtin_description * d; | |
16565 | enum insn_code icode; | |
5039610b | 16566 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
5a9335ef NC |
16567 | tree arg0; |
16568 | tree arg1; | |
16569 | tree arg2; | |
16570 | rtx op0; | |
16571 | rtx op1; | |
16572 | rtx op2; | |
16573 | rtx pat; | |
16574 | int fcode = DECL_FUNCTION_CODE (fndecl); | |
16575 | size_t i; | |
16576 | enum machine_mode tmode; | |
16577 | enum machine_mode mode0; | |
16578 | enum machine_mode mode1; | |
16579 | enum machine_mode mode2; | |
16580 | ||
88f77cba JB |
16581 | if (fcode >= ARM_BUILTIN_NEON_BASE) |
16582 | return arm_expand_neon_builtin (fcode, exp, target); | |
16583 | ||
5a9335ef NC |
16584 | switch (fcode) |
16585 | { | |
16586 | case ARM_BUILTIN_TEXTRMSB: | |
16587 | case ARM_BUILTIN_TEXTRMUB: | |
16588 | case ARM_BUILTIN_TEXTRMSH: | |
16589 | case ARM_BUILTIN_TEXTRMUH: | |
16590 | case ARM_BUILTIN_TEXTRMSW: | |
16591 | case ARM_BUILTIN_TEXTRMUW: | |
16592 | icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb | |
16593 | : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub | |
16594 | : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh | |
16595 | : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh | |
16596 | : CODE_FOR_iwmmxt_textrmw); | |
16597 | ||
5039610b SL |
16598 | arg0 = CALL_EXPR_ARG (exp, 0); |
16599 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
16600 | op0 = expand_normal (arg0); |
16601 | op1 = expand_normal (arg1); | |
5a9335ef NC |
16602 | tmode = insn_data[icode].operand[0].mode; |
16603 | mode0 = insn_data[icode].operand[1].mode; | |
16604 | mode1 = insn_data[icode].operand[2].mode; | |
16605 | ||
16606 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16607 | op0 = copy_to_mode_reg (mode0, op0); | |
16608 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16609 | { | |
16610 | /* @@@ better error message */ | |
16611 | error ("selector must be an immediate"); | |
16612 | return gen_reg_rtx (tmode); | |
16613 | } | |
16614 | if (target == 0 | |
16615 | || GET_MODE (target) != tmode | |
16616 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16617 | target = gen_reg_rtx (tmode); | |
16618 | pat = GEN_FCN (icode) (target, op0, op1); | |
16619 | if (! pat) | |
16620 | return 0; | |
16621 | emit_insn (pat); | |
16622 | return target; | |
16623 | ||
16624 | case ARM_BUILTIN_TINSRB: | |
16625 | case ARM_BUILTIN_TINSRH: | |
16626 | case ARM_BUILTIN_TINSRW: | |
16627 | icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb | |
16628 | : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh | |
16629 | : CODE_FOR_iwmmxt_tinsrw); | |
5039610b SL |
16630 | arg0 = CALL_EXPR_ARG (exp, 0); |
16631 | arg1 = CALL_EXPR_ARG (exp, 1); | |
16632 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
16633 | op0 = expand_normal (arg0); |
16634 | op1 = expand_normal (arg1); | |
16635 | op2 = expand_normal (arg2); | |
5a9335ef NC |
16636 | tmode = insn_data[icode].operand[0].mode; |
16637 | mode0 = insn_data[icode].operand[1].mode; | |
16638 | mode1 = insn_data[icode].operand[2].mode; | |
16639 | mode2 = insn_data[icode].operand[3].mode; | |
16640 | ||
16641 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16642 | op0 = copy_to_mode_reg (mode0, op0); | |
16643 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16644 | op1 = copy_to_mode_reg (mode1, op1); | |
16645 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
16646 | { | |
16647 | /* @@@ better error message */ | |
16648 | error ("selector must be an immediate"); | |
16649 | return const0_rtx; | |
16650 | } | |
16651 | if (target == 0 | |
16652 | || GET_MODE (target) != tmode | |
16653 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16654 | target = gen_reg_rtx (tmode); | |
16655 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
16656 | if (! pat) | |
16657 | return 0; | |
16658 | emit_insn (pat); | |
16659 | return target; | |
16660 | ||
16661 | case ARM_BUILTIN_SETWCX: | |
5039610b SL |
16662 | arg0 = CALL_EXPR_ARG (exp, 0); |
16663 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
16664 | op0 = force_reg (SImode, expand_normal (arg0)); |
16665 | op1 = expand_normal (arg1); | |
f07a6b21 | 16666 | emit_insn (gen_iwmmxt_tmcr (op1, op0)); |
5a9335ef NC |
16667 | return 0; |
16668 | ||
16669 | case ARM_BUILTIN_GETWCX: | |
5039610b | 16670 | arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 16671 | op0 = expand_normal (arg0); |
5a9335ef NC |
16672 | target = gen_reg_rtx (SImode); |
16673 | emit_insn (gen_iwmmxt_tmrc (target, op0)); | |
16674 | return target; | |
16675 | ||
16676 | case ARM_BUILTIN_WSHUFH: | |
16677 | icode = CODE_FOR_iwmmxt_wshufh; | |
5039610b SL |
16678 | arg0 = CALL_EXPR_ARG (exp, 0); |
16679 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
16680 | op0 = expand_normal (arg0); |
16681 | op1 = expand_normal (arg1); | |
5a9335ef NC |
16682 | tmode = insn_data[icode].operand[0].mode; |
16683 | mode1 = insn_data[icode].operand[1].mode; | |
16684 | mode2 = insn_data[icode].operand[2].mode; | |
16685 | ||
16686 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) | |
16687 | op0 = copy_to_mode_reg (mode1, op0); | |
16688 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) | |
16689 | { | |
16690 | /* @@@ better error message */ | |
16691 | error ("mask must be an immediate"); | |
16692 | return const0_rtx; | |
16693 | } | |
16694 | if (target == 0 | |
16695 | || GET_MODE (target) != tmode | |
16696 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16697 | target = gen_reg_rtx (tmode); | |
16698 | pat = GEN_FCN (icode) (target, op0, op1); | |
16699 | if (! pat) | |
16700 | return 0; | |
16701 | emit_insn (pat); | |
16702 | return target; | |
16703 | ||
16704 | case ARM_BUILTIN_WSADB: | |
5039610b | 16705 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target); |
5a9335ef | 16706 | case ARM_BUILTIN_WSADH: |
5039610b | 16707 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target); |
5a9335ef | 16708 | case ARM_BUILTIN_WSADBZ: |
5039610b | 16709 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target); |
5a9335ef | 16710 | case ARM_BUILTIN_WSADHZ: |
5039610b | 16711 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target); |
5a9335ef NC |
16712 | |
16713 | /* Several three-argument builtins. */ | |
16714 | case ARM_BUILTIN_WMACS: | |
16715 | case ARM_BUILTIN_WMACU: | |
16716 | case ARM_BUILTIN_WALIGN: | |
16717 | case ARM_BUILTIN_TMIA: | |
16718 | case ARM_BUILTIN_TMIAPH: | |
16719 | case ARM_BUILTIN_TMIATT: | |
16720 | case ARM_BUILTIN_TMIATB: | |
16721 | case ARM_BUILTIN_TMIABT: | |
16722 | case ARM_BUILTIN_TMIABB: | |
16723 | icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs | |
16724 | : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu | |
16725 | : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia | |
16726 | : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph | |
16727 | : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb | |
16728 | : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt | |
16729 | : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb | |
16730 | : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt | |
16731 | : CODE_FOR_iwmmxt_walign); | |
5039610b SL |
16732 | arg0 = CALL_EXPR_ARG (exp, 0); |
16733 | arg1 = CALL_EXPR_ARG (exp, 1); | |
16734 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
16735 | op0 = expand_normal (arg0); |
16736 | op1 = expand_normal (arg1); | |
16737 | op2 = expand_normal (arg2); | |
5a9335ef NC |
16738 | tmode = insn_data[icode].operand[0].mode; |
16739 | mode0 = insn_data[icode].operand[1].mode; | |
16740 | mode1 = insn_data[icode].operand[2].mode; | |
16741 | mode2 = insn_data[icode].operand[3].mode; | |
16742 | ||
16743 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16744 | op0 = copy_to_mode_reg (mode0, op0); | |
16745 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16746 | op1 = copy_to_mode_reg (mode1, op1); | |
16747 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
16748 | op2 = copy_to_mode_reg (mode2, op2); | |
16749 | if (target == 0 | |
16750 | || GET_MODE (target) != tmode | |
16751 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16752 | target = gen_reg_rtx (tmode); | |
16753 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
16754 | if (! pat) | |
16755 | return 0; | |
16756 | emit_insn (pat); | |
16757 | return target; | |
f676971a | 16758 | |
5a9335ef NC |
16759 | case ARM_BUILTIN_WZERO: |
16760 | target = gen_reg_rtx (DImode); | |
16761 | emit_insn (gen_iwmmxt_clrdi (target)); | |
16762 | return target; | |
16763 | ||
d3585b76 DJ |
16764 | case ARM_BUILTIN_THREAD_POINTER: |
16765 | return arm_load_tp (target); | |
16766 | ||
5a9335ef NC |
16767 | default: |
16768 | break; | |
16769 | } | |
16770 | ||
e97a46ce | 16771 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef | 16772 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 16773 | return arm_expand_binop_builtin (d->icode, exp, target); |
5a9335ef | 16774 | |
e97a46ce | 16775 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
5a9335ef | 16776 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 16777 | return arm_expand_unop_builtin (d->icode, exp, target, 0); |
5a9335ef NC |
16778 | |
16779 | /* @@@ Should really do something sensible here. */ | |
16780 | return NULL_RTX; | |
16781 | } | |
16782 | \f | |
1d6e90ac NC |
16783 | /* Return the number (counting from 0) of |
16784 | the least significant set bit in MASK. */ | |
16785 | ||
e32bac5b | 16786 | inline static int |
b279b20a | 16787 | number_of_first_bit_set (unsigned mask) |
d5b7b3ae RE |
16788 | { |
16789 | int bit; | |
16790 | ||
16791 | for (bit = 0; | |
16792 | (mask & (1 << bit)) == 0; | |
5895f793 | 16793 | ++bit) |
d5b7b3ae RE |
16794 | continue; |
16795 | ||
16796 | return bit; | |
16797 | } | |
16798 | ||
b279b20a NC |
16799 | /* Emit code to push or pop registers to or from the stack. F is the |
16800 | assembly file. MASK is the registers to push or pop. PUSH is | |
16801 | nonzero if we should push, and zero if we should pop. For debugging | |
16802 | output, if pushing, adjust CFA_OFFSET by the amount of space added | |
16803 | to the stack. REAL_REGS should have the same number of bits set as | |
16804 | MASK, and will be used instead (in the same order) to describe which | |
16805 | registers were saved - this is used to mark the save slots when we | |
16806 | push high registers after moving them to low registers. */ | |
16807 | static void | |
16808 | thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset, | |
16809 | unsigned long real_regs) | |
16810 | { | |
16811 | int regno; | |
16812 | int lo_mask = mask & 0xFF; | |
16813 | int pushed_words = 0; | |
16814 | ||
e6d29d15 | 16815 | gcc_assert (mask); |
b279b20a NC |
16816 | |
16817 | if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM))) | |
16818 | { | |
16819 | /* Special case. Do not generate a POP PC statement here, do it in | |
16820 | thumb_exit() */ | |
16821 | thumb_exit (f, -1); | |
16822 | return; | |
16823 | } | |
16824 | ||
617a1b71 PB |
16825 | if (ARM_EABI_UNWIND_TABLES && push) |
16826 | { | |
16827 | fprintf (f, "\t.save\t{"); | |
16828 | for (regno = 0; regno < 15; regno++) | |
16829 | { | |
16830 | if (real_regs & (1 << regno)) | |
16831 | { | |
16832 | if (real_regs & ((1 << regno) -1)) | |
16833 | fprintf (f, ", "); | |
16834 | asm_fprintf (f, "%r", regno); | |
16835 | } | |
16836 | } | |
16837 | fprintf (f, "}\n"); | |
16838 | } | |
16839 | ||
b279b20a NC |
16840 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); |
16841 | ||
16842 | /* Look at the low registers first. */ | |
16843 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) | |
16844 | { | |
16845 | if (lo_mask & 1) | |
16846 | { | |
16847 | asm_fprintf (f, "%r", regno); | |
16848 | ||
16849 | if ((lo_mask & ~1) != 0) | |
16850 | fprintf (f, ", "); | |
16851 | ||
16852 | pushed_words++; | |
16853 | } | |
16854 | } | |
16855 | ||
16856 | if (push && (mask & (1 << LR_REGNUM))) | |
16857 | { | |
16858 | /* Catch pushing the LR. */ | |
16859 | if (mask & 0xFF) | |
16860 | fprintf (f, ", "); | |
16861 | ||
16862 | asm_fprintf (f, "%r", LR_REGNUM); | |
16863 | ||
16864 | pushed_words++; | |
16865 | } | |
16866 | else if (!push && (mask & (1 << PC_REGNUM))) | |
16867 | { | |
16868 | /* Catch popping the PC. */ | |
16869 | if (TARGET_INTERWORK || TARGET_BACKTRACE | |
e3b5732b | 16870 | || crtl->calls_eh_return) |
b279b20a NC |
16871 | { |
16872 | /* The PC is never poped directly, instead | |
16873 | it is popped into r3 and then BX is used. */ | |
16874 | fprintf (f, "}\n"); | |
16875 | ||
16876 | thumb_exit (f, -1); | |
16877 | ||
16878 | return; | |
16879 | } | |
16880 | else | |
16881 | { | |
16882 | if (mask & 0xFF) | |
16883 | fprintf (f, ", "); | |
16884 | ||
16885 | asm_fprintf (f, "%r", PC_REGNUM); | |
16886 | } | |
16887 | } | |
16888 | ||
16889 | fprintf (f, "}\n"); | |
16890 | ||
16891 | if (push && pushed_words && dwarf2out_do_frame ()) | |
16892 | { | |
16893 | char *l = dwarf2out_cfi_label (); | |
16894 | int pushed_mask = real_regs; | |
16895 | ||
16896 | *cfa_offset += pushed_words * 4; | |
16897 | dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); | |
16898 | ||
16899 | pushed_words = 0; | |
16900 | pushed_mask = real_regs; | |
16901 | for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) | |
16902 | { | |
16903 | if (pushed_mask & 1) | |
16904 | dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); | |
16905 | } | |
16906 | } | |
16907 | } | |
16908 | ||
d5b7b3ae RE |
16909 | /* Generate code to return from a thumb function. |
16910 | If 'reg_containing_return_addr' is -1, then the return address is | |
16911 | actually on the stack, at the stack pointer. */ | |
16912 | static void | |
c9ca9b88 | 16913 | thumb_exit (FILE *f, int reg_containing_return_addr) |
d5b7b3ae RE |
16914 | { |
16915 | unsigned regs_available_for_popping; | |
16916 | unsigned regs_to_pop; | |
16917 | int pops_needed; | |
16918 | unsigned available; | |
16919 | unsigned required; | |
16920 | int mode; | |
16921 | int size; | |
16922 | int restore_a4 = FALSE; | |
16923 | ||
16924 | /* Compute the registers we need to pop. */ | |
16925 | regs_to_pop = 0; | |
16926 | pops_needed = 0; | |
16927 | ||
c9ca9b88 | 16928 | if (reg_containing_return_addr == -1) |
d5b7b3ae | 16929 | { |
d5b7b3ae | 16930 | regs_to_pop |= 1 << LR_REGNUM; |
5895f793 | 16931 | ++pops_needed; |
d5b7b3ae RE |
16932 | } |
16933 | ||
16934 | if (TARGET_BACKTRACE) | |
16935 | { | |
16936 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
16937 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
16938 | pops_needed += 2; | |
16939 | } | |
16940 | ||
16941 | /* If there is nothing to pop then just emit the BX instruction and | |
16942 | return. */ | |
16943 | if (pops_needed == 0) | |
16944 | { | |
e3b5732b | 16945 | if (crtl->calls_eh_return) |
c9ca9b88 | 16946 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
16947 | |
16948 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
16949 | return; | |
16950 | } | |
16951 | /* Otherwise if we are not supporting interworking and we have not created | |
16952 | a backtrace structure and the function was not entered in ARM mode then | |
16953 | just pop the return address straight into the PC. */ | |
5895f793 RE |
16954 | else if (!TARGET_INTERWORK |
16955 | && !TARGET_BACKTRACE | |
c9ca9b88 | 16956 | && !is_called_in_ARM_mode (current_function_decl) |
e3b5732b | 16957 | && !crtl->calls_eh_return) |
d5b7b3ae | 16958 | { |
c9ca9b88 | 16959 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); |
d5b7b3ae RE |
16960 | return; |
16961 | } | |
16962 | ||
16963 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
16964 | regs_available_for_popping = 0; | |
16965 | ||
16966 | /* If returning via __builtin_eh_return, the bottom three registers | |
16967 | all contain information needed for the return. */ | |
e3b5732b | 16968 | if (crtl->calls_eh_return) |
d5b7b3ae RE |
16969 | size = 12; |
16970 | else | |
16971 | { | |
d5b7b3ae RE |
16972 | /* If we can deduce the registers used from the function's |
16973 | return value. This is more reliable that examining | |
6fb5fa3c | 16974 | df_regs_ever_live_p () because that will be set if the register is |
d5b7b3ae RE |
16975 | ever used in the function, not just if the register is used |
16976 | to hold a return value. */ | |
16977 | ||
38173d38 JH |
16978 | if (crtl->return_rtx != 0) |
16979 | mode = GET_MODE (crtl->return_rtx); | |
d5b7b3ae | 16980 | else |
d5b7b3ae RE |
16981 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); |
16982 | ||
16983 | size = GET_MODE_SIZE (mode); | |
16984 | ||
16985 | if (size == 0) | |
16986 | { | |
16987 | /* In a void function we can use any argument register. | |
16988 | In a function that returns a structure on the stack | |
16989 | we can use the second and third argument registers. */ | |
16990 | if (mode == VOIDmode) | |
16991 | regs_available_for_popping = | |
16992 | (1 << ARG_REGISTER (1)) | |
16993 | | (1 << ARG_REGISTER (2)) | |
16994 | | (1 << ARG_REGISTER (3)); | |
16995 | else | |
16996 | regs_available_for_popping = | |
16997 | (1 << ARG_REGISTER (2)) | |
16998 | | (1 << ARG_REGISTER (3)); | |
16999 | } | |
17000 | else if (size <= 4) | |
17001 | regs_available_for_popping = | |
17002 | (1 << ARG_REGISTER (2)) | |
17003 | | (1 << ARG_REGISTER (3)); | |
17004 | else if (size <= 8) | |
17005 | regs_available_for_popping = | |
17006 | (1 << ARG_REGISTER (3)); | |
17007 | } | |
17008 | ||
17009 | /* Match registers to be popped with registers into which we pop them. */ | |
17010 | for (available = regs_available_for_popping, | |
17011 | required = regs_to_pop; | |
17012 | required != 0 && available != 0; | |
17013 | available &= ~(available & - available), | |
17014 | required &= ~(required & - required)) | |
17015 | -- pops_needed; | |
17016 | ||
17017 | /* If we have any popping registers left over, remove them. */ | |
17018 | if (available > 0) | |
5895f793 | 17019 | regs_available_for_popping &= ~available; |
f676971a | 17020 | |
d5b7b3ae RE |
17021 | /* Otherwise if we need another popping register we can use |
17022 | the fourth argument register. */ | |
17023 | else if (pops_needed) | |
17024 | { | |
17025 | /* If we have not found any free argument registers and | |
17026 | reg a4 contains the return address, we must move it. */ | |
17027 | if (regs_available_for_popping == 0 | |
17028 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
17029 | { | |
17030 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
17031 | reg_containing_return_addr = LR_REGNUM; | |
17032 | } | |
17033 | else if (size > 12) | |
17034 | { | |
17035 | /* Register a4 is being used to hold part of the return value, | |
17036 | but we have dire need of a free, low register. */ | |
17037 | restore_a4 = TRUE; | |
f676971a | 17038 | |
d5b7b3ae RE |
17039 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); |
17040 | } | |
f676971a | 17041 | |
d5b7b3ae RE |
17042 | if (reg_containing_return_addr != LAST_ARG_REGNUM) |
17043 | { | |
17044 | /* The fourth argument register is available. */ | |
17045 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
f676971a | 17046 | |
5895f793 | 17047 | --pops_needed; |
d5b7b3ae RE |
17048 | } |
17049 | } | |
17050 | ||
17051 | /* Pop as many registers as we can. */ | |
980e61bb DJ |
17052 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
17053 | regs_available_for_popping); | |
d5b7b3ae RE |
17054 | |
17055 | /* Process the registers we popped. */ | |
17056 | if (reg_containing_return_addr == -1) | |
17057 | { | |
17058 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 17059 | regs_to_pop &= ~(1 << LR_REGNUM); |
f676971a | 17060 | |
d5b7b3ae RE |
17061 | reg_containing_return_addr = |
17062 | number_of_first_bit_set (regs_available_for_popping); | |
17063 | ||
17064 | /* Remove this register for the mask of available registers, so that | |
6bc82793 | 17065 | the return address will not be corrupted by further pops. */ |
5895f793 | 17066 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
17067 | } |
17068 | ||
17069 | /* If we popped other registers then handle them here. */ | |
17070 | if (regs_available_for_popping) | |
17071 | { | |
17072 | int frame_pointer; | |
f676971a | 17073 | |
d5b7b3ae RE |
17074 | /* Work out which register currently contains the frame pointer. */ |
17075 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
17076 | ||
17077 | /* Move it into the correct place. */ | |
17078 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
17079 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
17080 | ||
17081 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
17082 | regs_available_for_popping &= ~(1 << frame_pointer); |
17083 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
f676971a | 17084 | |
d5b7b3ae RE |
17085 | if (regs_available_for_popping) |
17086 | { | |
17087 | int stack_pointer; | |
f676971a | 17088 | |
d5b7b3ae RE |
17089 | /* We popped the stack pointer as well, |
17090 | find the register that contains it. */ | |
17091 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
17092 | ||
17093 | /* Move it into the stack register. */ | |
17094 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
f676971a | 17095 | |
d5b7b3ae RE |
17096 | /* At this point we have popped all necessary registers, so |
17097 | do not worry about restoring regs_available_for_popping | |
17098 | to its correct value: | |
17099 | ||
17100 | assert (pops_needed == 0) | |
17101 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
17102 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
17103 | } | |
17104 | else | |
17105 | { | |
17106 | /* Since we have just move the popped value into the frame | |
17107 | pointer, the popping register is available for reuse, and | |
17108 | we know that we still have the stack pointer left to pop. */ | |
17109 | regs_available_for_popping |= (1 << frame_pointer); | |
17110 | } | |
17111 | } | |
f676971a | 17112 | |
d5b7b3ae RE |
17113 | /* If we still have registers left on the stack, but we no longer have |
17114 | any registers into which we can pop them, then we must move the return | |
17115 | address into the link register and make available the register that | |
17116 | contained it. */ | |
17117 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
17118 | { | |
17119 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
f676971a | 17120 | |
d5b7b3ae RE |
17121 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, |
17122 | reg_containing_return_addr); | |
f676971a | 17123 | |
d5b7b3ae RE |
17124 | reg_containing_return_addr = LR_REGNUM; |
17125 | } | |
17126 | ||
17127 | /* If we have registers left on the stack then pop some more. | |
17128 | We know that at most we will want to pop FP and SP. */ | |
17129 | if (pops_needed > 0) | |
17130 | { | |
17131 | int popped_into; | |
17132 | int move_to; | |
f676971a | 17133 | |
980e61bb DJ |
17134 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
17135 | regs_available_for_popping); | |
d5b7b3ae RE |
17136 | |
17137 | /* We have popped either FP or SP. | |
17138 | Move whichever one it is into the correct register. */ | |
17139 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
17140 | move_to = number_of_first_bit_set (regs_to_pop); | |
17141 | ||
17142 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
17143 | ||
5895f793 | 17144 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 17145 | |
5895f793 | 17146 | --pops_needed; |
d5b7b3ae | 17147 | } |
f676971a | 17148 | |
d5b7b3ae RE |
17149 | /* If we still have not popped everything then we must have only |
17150 | had one register available to us and we are now popping the SP. */ | |
17151 | if (pops_needed > 0) | |
17152 | { | |
17153 | int popped_into; | |
f676971a | 17154 | |
980e61bb DJ |
17155 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
17156 | regs_available_for_popping); | |
d5b7b3ae RE |
17157 | |
17158 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
17159 | ||
17160 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
17161 | /* | |
17162 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
17163 | assert (pops_needed == 1) | |
17164 | */ | |
17165 | } | |
17166 | ||
17167 | /* If necessary restore the a4 register. */ | |
17168 | if (restore_a4) | |
17169 | { | |
17170 | if (reg_containing_return_addr != LR_REGNUM) | |
17171 | { | |
17172 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
17173 | reg_containing_return_addr = LR_REGNUM; | |
17174 | } | |
f676971a | 17175 | |
d5b7b3ae RE |
17176 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
17177 | } | |
17178 | ||
e3b5732b | 17179 | if (crtl->calls_eh_return) |
c9ca9b88 | 17180 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
17181 | |
17182 | /* Return to caller. */ | |
17183 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
17184 | } | |
17185 | ||
d5b7b3ae RE |
17186 | \f |
17187 | void | |
5b3e6663 | 17188 | thumb1_final_prescan_insn (rtx insn) |
d5b7b3ae | 17189 | { |
d5b7b3ae | 17190 | if (flag_print_asm_name) |
9d98a694 AO |
17191 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
17192 | INSN_ADDRESSES (INSN_UID (insn))); | |
d5b7b3ae RE |
17193 | } |
17194 | ||
17195 | int | |
e32bac5b | 17196 | thumb_shiftable_const (unsigned HOST_WIDE_INT val) |
d5b7b3ae RE |
17197 | { |
17198 | unsigned HOST_WIDE_INT mask = 0xff; | |
17199 | int i; | |
17200 | ||
17201 | if (val == 0) /* XXX */ | |
17202 | return 0; | |
f676971a | 17203 | |
d5b7b3ae RE |
17204 | for (i = 0; i < 25; i++) |
17205 | if ((val & (mask << i)) == val) | |
17206 | return 1; | |
17207 | ||
17208 | return 0; | |
17209 | } | |
17210 | ||
825dda42 | 17211 | /* Returns nonzero if the current function contains, |
d5b7b3ae | 17212 | or might contain a far jump. */ |
5848830f PB |
17213 | static int |
17214 | thumb_far_jump_used_p (void) | |
d5b7b3ae RE |
17215 | { |
17216 | rtx insn; | |
17217 | ||
17218 | /* This test is only important for leaf functions. */ | |
5895f793 | 17219 | /* assert (!leaf_function_p ()); */ |
f676971a | 17220 | |
d5b7b3ae RE |
17221 | /* If we have already decided that far jumps may be used, |
17222 | do not bother checking again, and always return true even if | |
17223 | it turns out that they are not being used. Once we have made | |
17224 | the decision that far jumps are present (and that hence the link | |
17225 | register will be pushed onto the stack) we cannot go back on it. */ | |
17226 | if (cfun->machine->far_jump_used) | |
17227 | return 1; | |
17228 | ||
17229 | /* If this function is not being called from the prologue/epilogue | |
17230 | generation code then it must be being called from the | |
17231 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5848830f | 17232 | if (!(ARM_DOUBLEWORD_ALIGN || reload_completed)) |
d5b7b3ae RE |
17233 | { |
17234 | /* In this case we know that we are being asked about the elimination | |
17235 | of the arg pointer register. If that register is not being used, | |
17236 | then there are no arguments on the stack, and we do not have to | |
17237 | worry that a far jump might force the prologue to push the link | |
17238 | register, changing the stack offsets. In this case we can just | |
17239 | return false, since the presence of far jumps in the function will | |
17240 | not affect stack offsets. | |
17241 | ||
17242 | If the arg pointer is live (or if it was live, but has now been | |
17243 | eliminated and so set to dead) then we do have to test to see if | |
17244 | the function might contain a far jump. This test can lead to some | |
17245 | false negatives, since before reload is completed, then length of | |
17246 | branch instructions is not known, so gcc defaults to returning their | |
17247 | longest length, which in turn sets the far jump attribute to true. | |
17248 | ||
17249 | A false negative will not result in bad code being generated, but it | |
17250 | will result in a needless push and pop of the link register. We | |
5848830f PB |
17251 | hope that this does not occur too often. |
17252 | ||
17253 | If we need doubleword stack alignment this could affect the other | |
17254 | elimination offsets so we can't risk getting it wrong. */ | |
6fb5fa3c | 17255 | if (df_regs_ever_live_p (ARG_POINTER_REGNUM)) |
d5b7b3ae | 17256 | cfun->machine->arg_pointer_live = 1; |
5895f793 | 17257 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
17258 | return 0; |
17259 | } | |
17260 | ||
17261 | /* Check to see if the function contains a branch | |
17262 | insn with the far jump attribute set. */ | |
17263 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
17264 | { | |
17265 | if (GET_CODE (insn) == JUMP_INSN | |
17266 | /* Ignore tablejump patterns. */ | |
17267 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
17268 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
17269 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
17270 | ) | |
17271 | { | |
9a9f7594 | 17272 | /* Record the fact that we have decided that |
d5b7b3ae RE |
17273 | the function does use far jumps. */ |
17274 | cfun->machine->far_jump_used = 1; | |
17275 | return 1; | |
17276 | } | |
17277 | } | |
f676971a | 17278 | |
d5b7b3ae RE |
17279 | return 0; |
17280 | } | |
17281 | ||
825dda42 | 17282 | /* Return nonzero if FUNC must be entered in ARM mode. */ |
d5b7b3ae | 17283 | int |
e32bac5b | 17284 | is_called_in_ARM_mode (tree func) |
d5b7b3ae | 17285 | { |
e6d29d15 | 17286 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
d5b7b3ae | 17287 | |
696e78bf | 17288 | /* Ignore the problem about functions whose address is taken. */ |
d5b7b3ae RE |
17289 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) |
17290 | return TRUE; | |
17291 | ||
f676971a | 17292 | #ifdef ARM_PE |
91d231cb | 17293 | return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; |
d5b7b3ae RE |
17294 | #else |
17295 | return FALSE; | |
17296 | #endif | |
17297 | } | |
17298 | ||
d6b4baa4 | 17299 | /* The bits which aren't usefully expanded as rtl. */ |
cd2b33d0 | 17300 | const char * |
e32bac5b | 17301 | thumb_unexpanded_epilogue (void) |
d5b7b3ae | 17302 | { |
954954d1 | 17303 | arm_stack_offsets *offsets; |
d5b7b3ae | 17304 | int regno; |
b279b20a | 17305 | unsigned long live_regs_mask = 0; |
d5b7b3ae | 17306 | int high_regs_pushed = 0; |
d5b7b3ae | 17307 | int had_to_push_lr; |
57934c39 | 17308 | int size; |
d5b7b3ae | 17309 | |
934c2060 | 17310 | if (cfun->machine->return_used_this_function != 0) |
d5b7b3ae RE |
17311 | return ""; |
17312 | ||
58e60158 AN |
17313 | if (IS_NAKED (arm_current_func_type ())) |
17314 | return ""; | |
17315 | ||
954954d1 PB |
17316 | offsets = arm_get_frame_offsets (); |
17317 | live_regs_mask = offsets->saved_regs_mask; | |
57934c39 PB |
17318 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); |
17319 | ||
17320 | /* If we can deduce the registers used from the function's return value. | |
6fb5fa3c | 17321 | This is more reliable that examining df_regs_ever_live_p () because that |
57934c39 PB |
17322 | will be set if the register is ever used in the function, not just if |
17323 | the register is used to hold a return value. */ | |
4f5dfed0 | 17324 | size = arm_size_return_regs (); |
d5b7b3ae RE |
17325 | |
17326 | /* The prolog may have pushed some high registers to use as | |
112cdef5 | 17327 | work registers. e.g. the testsuite file: |
d5b7b3ae RE |
17328 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c |
17329 | compiles to produce: | |
17330 | push {r4, r5, r6, r7, lr} | |
17331 | mov r7, r9 | |
17332 | mov r6, r8 | |
17333 | push {r6, r7} | |
17334 | as part of the prolog. We have to undo that pushing here. */ | |
f676971a | 17335 | |
d5b7b3ae RE |
17336 | if (high_regs_pushed) |
17337 | { | |
b279b20a | 17338 | unsigned long mask = live_regs_mask & 0xff; |
d5b7b3ae | 17339 | int next_hi_reg; |
d5b7b3ae | 17340 | |
57934c39 PB |
17341 | /* The available low registers depend on the size of the value we are |
17342 | returning. */ | |
17343 | if (size <= 12) | |
d5b7b3ae | 17344 | mask |= 1 << 3; |
57934c39 PB |
17345 | if (size <= 8) |
17346 | mask |= 1 << 2; | |
d5b7b3ae RE |
17347 | |
17348 | if (mask == 0) | |
17349 | /* Oh dear! We have no low registers into which we can pop | |
17350 | high registers! */ | |
400500c4 RK |
17351 | internal_error |
17352 | ("no low registers available for popping high registers"); | |
f676971a | 17353 | |
d5b7b3ae | 17354 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 17355 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
17356 | break; |
17357 | ||
17358 | while (high_regs_pushed) | |
17359 | { | |
17360 | /* Find lo register(s) into which the high register(s) can | |
17361 | be popped. */ | |
17362 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
17363 | { | |
17364 | if (mask & (1 << regno)) | |
17365 | high_regs_pushed--; | |
17366 | if (high_regs_pushed == 0) | |
17367 | break; | |
17368 | } | |
17369 | ||
17370 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
17371 | ||
d6b4baa4 | 17372 | /* Pop the values into the low register(s). */ |
980e61bb | 17373 | thumb_pushpop (asm_out_file, mask, 0, NULL, mask); |
d5b7b3ae RE |
17374 | |
17375 | /* Move the value(s) into the high registers. */ | |
17376 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
17377 | { | |
17378 | if (mask & (1 << regno)) | |
17379 | { | |
17380 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
17381 | regno); | |
f676971a | 17382 | |
d5b7b3ae | 17383 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 17384 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
17385 | break; |
17386 | } | |
17387 | } | |
17388 | } | |
57934c39 | 17389 | live_regs_mask &= ~0x0f00; |
d5b7b3ae RE |
17390 | } |
17391 | ||
57934c39 PB |
17392 | had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0; |
17393 | live_regs_mask &= 0xff; | |
17394 | ||
38173d38 | 17395 | if (crtl->args.pretend_args_size == 0 || TARGET_BACKTRACE) |
d5b7b3ae | 17396 | { |
f676971a | 17397 | /* Pop the return address into the PC. */ |
57934c39 | 17398 | if (had_to_push_lr) |
d5b7b3ae RE |
17399 | live_regs_mask |= 1 << PC_REGNUM; |
17400 | ||
17401 | /* Either no argument registers were pushed or a backtrace | |
17402 | structure was created which includes an adjusted stack | |
17403 | pointer, so just pop everything. */ | |
17404 | if (live_regs_mask) | |
980e61bb DJ |
17405 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
17406 | live_regs_mask); | |
57934c39 | 17407 | |
d5b7b3ae | 17408 | /* We have either just popped the return address into the |
57934c39 PB |
17409 | PC or it is was kept in LR for the entire function. */ |
17410 | if (!had_to_push_lr) | |
17411 | thumb_exit (asm_out_file, LR_REGNUM); | |
d5b7b3ae RE |
17412 | } |
17413 | else | |
17414 | { | |
17415 | /* Pop everything but the return address. */ | |
d5b7b3ae | 17416 | if (live_regs_mask) |
980e61bb DJ |
17417 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
17418 | live_regs_mask); | |
d5b7b3ae RE |
17419 | |
17420 | if (had_to_push_lr) | |
57934c39 PB |
17421 | { |
17422 | if (size > 12) | |
17423 | { | |
17424 | /* We have no free low regs, so save one. */ | |
17425 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM, | |
17426 | LAST_ARG_REGNUM); | |
17427 | } | |
17428 | ||
17429 | /* Get the return address into a temporary register. */ | |
17430 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, | |
17431 | 1 << LAST_ARG_REGNUM); | |
17432 | ||
17433 | if (size > 12) | |
17434 | { | |
17435 | /* Move the return address to lr. */ | |
17436 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM, | |
17437 | LAST_ARG_REGNUM); | |
17438 | /* Restore the low register. */ | |
17439 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, | |
17440 | IP_REGNUM); | |
17441 | regno = LR_REGNUM; | |
17442 | } | |
17443 | else | |
17444 | regno = LAST_ARG_REGNUM; | |
17445 | } | |
17446 | else | |
17447 | regno = LR_REGNUM; | |
f676971a | 17448 | |
d5b7b3ae RE |
17449 | /* Remove the argument registers that were pushed onto the stack. */ |
17450 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
17451 | SP_REGNUM, SP_REGNUM, | |
38173d38 | 17452 | crtl->args.pretend_args_size); |
f676971a | 17453 | |
57934c39 | 17454 | thumb_exit (asm_out_file, regno); |
d5b7b3ae RE |
17455 | } |
17456 | ||
17457 | return ""; | |
17458 | } | |
17459 | ||
17460 | /* Functions to save and restore machine-specific function data. */ | |
e2500fed | 17461 | static struct machine_function * |
e32bac5b | 17462 | arm_init_machine_status (void) |
d5b7b3ae | 17463 | { |
e2500fed GK |
17464 | struct machine_function *machine; |
17465 | machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); | |
6d3d9133 | 17466 | |
f676971a | 17467 | #if ARM_FT_UNKNOWN != 0 |
e2500fed | 17468 | machine->func_type = ARM_FT_UNKNOWN; |
6d3d9133 | 17469 | #endif |
e2500fed | 17470 | return machine; |
f7a80099 NC |
17471 | } |
17472 | ||
d5b7b3ae RE |
17473 | /* Return an RTX indicating where the return address to the |
17474 | calling function can be found. */ | |
17475 | rtx | |
e32bac5b | 17476 | arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
d5b7b3ae | 17477 | { |
d5b7b3ae RE |
17478 | if (count != 0) |
17479 | return NULL_RTX; | |
17480 | ||
61f0ccff | 17481 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); |
d5b7b3ae RE |
17482 | } |
17483 | ||
17484 | /* Do anything needed before RTL is emitted for each function. */ | |
17485 | void | |
e32bac5b | 17486 | arm_init_expanders (void) |
d5b7b3ae RE |
17487 | { |
17488 | /* Arrange to initialize and mark the machine per-function status. */ | |
17489 | init_machine_status = arm_init_machine_status; | |
3ac5ea7c RH |
17490 | |
17491 | /* This is to stop the combine pass optimizing away the alignment | |
17492 | adjustment of va_arg. */ | |
17493 | /* ??? It is claimed that this should not be necessary. */ | |
17494 | if (cfun) | |
17495 | mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); | |
d5b7b3ae RE |
17496 | } |
17497 | ||
0977774b | 17498 | |
2591db65 RE |
17499 | /* Like arm_compute_initial_elimination offset. Simpler because there |
17500 | isn't an ABI specified frame pointer for Thumb. Instead, we set it | |
17501 | to point at the base of the local variables after static stack | |
17502 | space for a function has been allocated. */ | |
0977774b | 17503 | |
5848830f PB |
17504 | HOST_WIDE_INT |
17505 | thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to) | |
17506 | { | |
17507 | arm_stack_offsets *offsets; | |
0977774b | 17508 | |
5848830f | 17509 | offsets = arm_get_frame_offsets (); |
0977774b | 17510 | |
5848830f | 17511 | switch (from) |
0977774b | 17512 | { |
5848830f PB |
17513 | case ARG_POINTER_REGNUM: |
17514 | switch (to) | |
17515 | { | |
17516 | case STACK_POINTER_REGNUM: | |
17517 | return offsets->outgoing_args - offsets->saved_args; | |
0977774b | 17518 | |
5848830f PB |
17519 | case FRAME_POINTER_REGNUM: |
17520 | return offsets->soft_frame - offsets->saved_args; | |
0977774b | 17521 | |
5848830f PB |
17522 | case ARM_HARD_FRAME_POINTER_REGNUM: |
17523 | return offsets->saved_regs - offsets->saved_args; | |
0977774b | 17524 | |
2591db65 RE |
17525 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
17526 | return offsets->locals_base - offsets->saved_args; | |
17527 | ||
5848830f | 17528 | default: |
e6d29d15 | 17529 | gcc_unreachable (); |
5848830f PB |
17530 | } |
17531 | break; | |
0977774b | 17532 | |
5848830f PB |
17533 | case FRAME_POINTER_REGNUM: |
17534 | switch (to) | |
17535 | { | |
17536 | case STACK_POINTER_REGNUM: | |
17537 | return offsets->outgoing_args - offsets->soft_frame; | |
0977774b | 17538 | |
5848830f PB |
17539 | case ARM_HARD_FRAME_POINTER_REGNUM: |
17540 | return offsets->saved_regs - offsets->soft_frame; | |
0977774b | 17541 | |
2591db65 RE |
17542 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
17543 | return offsets->locals_base - offsets->soft_frame; | |
17544 | ||
5848830f | 17545 | default: |
e6d29d15 | 17546 | gcc_unreachable (); |
5848830f PB |
17547 | } |
17548 | break; | |
0977774b | 17549 | |
5848830f | 17550 | default: |
e6d29d15 | 17551 | gcc_unreachable (); |
5848830f | 17552 | } |
0977774b JT |
17553 | } |
17554 | ||
d5b7b3ae RE |
17555 | /* Generate the rest of a function's prologue. */ |
17556 | void | |
5b3e6663 | 17557 | thumb1_expand_prologue (void) |
d5b7b3ae | 17558 | { |
980e61bb DJ |
17559 | rtx insn, dwarf; |
17560 | ||
5848830f PB |
17561 | HOST_WIDE_INT amount; |
17562 | arm_stack_offsets *offsets; | |
6d3d9133 | 17563 | unsigned long func_type; |
3c7ad43e | 17564 | int regno; |
57934c39 | 17565 | unsigned long live_regs_mask; |
6d3d9133 NC |
17566 | |
17567 | func_type = arm_current_func_type (); | |
f676971a | 17568 | |
d5b7b3ae | 17569 | /* Naked functions don't have prologues. */ |
6d3d9133 | 17570 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
17571 | return; |
17572 | ||
6d3d9133 NC |
17573 | if (IS_INTERRUPT (func_type)) |
17574 | { | |
c725bd79 | 17575 | error ("interrupt Service Routines cannot be coded in Thumb mode"); |
6d3d9133 NC |
17576 | return; |
17577 | } | |
17578 | ||
954954d1 PB |
17579 | offsets = arm_get_frame_offsets (); |
17580 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a NC |
17581 | /* Load the pic register before setting the frame pointer, |
17582 | so we can use r7 as a temporary work register. */ | |
020a4035 | 17583 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
e55ef7f4 | 17584 | arm_load_pic_register (live_regs_mask); |
876f13b0 | 17585 | |
2591db65 | 17586 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) |
a2503645 RS |
17587 | emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM), |
17588 | stack_pointer_rtx); | |
d5b7b3ae | 17589 | |
5848830f | 17590 | amount = offsets->outgoing_args - offsets->saved_regs; |
d5b7b3ae RE |
17591 | if (amount) |
17592 | { | |
d5b7b3ae | 17593 | if (amount < 512) |
980e61bb DJ |
17594 | { |
17595 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
17596 | GEN_INT (- amount))); | |
17597 | RTX_FRAME_RELATED_P (insn) = 1; | |
17598 | } | |
d5b7b3ae RE |
17599 | else |
17600 | { | |
d5b7b3ae RE |
17601 | rtx reg; |
17602 | ||
17603 | /* The stack decrement is too big for an immediate value in a single | |
17604 | insn. In theory we could issue multiple subtracts, but after | |
17605 | three of them it becomes more space efficient to place the full | |
17606 | value in the constant pool and load into a register. (Also the | |
17607 | ARM debugger really likes to see only one stack decrement per | |
17608 | function). So instead we look for a scratch register into which | |
17609 | we can load the decrement, and then we subtract this from the | |
17610 | stack pointer. Unfortunately on the thumb the only available | |
17611 | scratch registers are the argument registers, and we cannot use | |
17612 | these as they may hold arguments to the function. Instead we | |
17613 | attempt to locate a call preserved register which is used by this | |
17614 | function. If we can find one, then we know that it will have | |
17615 | been pushed at the start of the prologue and so we can corrupt | |
17616 | it now. */ | |
17617 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
35596784 | 17618 | if (live_regs_mask & (1 << regno)) |
d5b7b3ae RE |
17619 | break; |
17620 | ||
35596784 | 17621 | gcc_assert(regno <= LAST_LO_REGNUM); |
d5b7b3ae | 17622 | |
35596784 | 17623 | reg = gen_rtx_REG (SImode, regno); |
d5b7b3ae | 17624 | |
35596784 | 17625 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb | 17626 | |
35596784 AJ |
17627 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, |
17628 | stack_pointer_rtx, reg)); | |
17629 | RTX_FRAME_RELATED_P (insn) = 1; | |
17630 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
17631 | plus_constant (stack_pointer_rtx, | |
17632 | -amount)); | |
17633 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
17634 | REG_NOTES (insn) | |
17635 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
17636 | REG_NOTES (insn)); | |
d5b7b3ae | 17637 | } |
2591db65 RE |
17638 | } |
17639 | ||
17640 | if (frame_pointer_needed) | |
5b3e6663 | 17641 | thumb_set_frame_pointer (offsets); |
f676971a | 17642 | |
74d9c39f DJ |
17643 | /* If we are profiling, make sure no instructions are scheduled before |
17644 | the call to mcount. Similarly if the user has requested no | |
17645 | scheduling in the prolog. Similarly if we want non-call exceptions | |
17646 | using the EABI unwinder, to prevent faulting instructions from being | |
17647 | swapped with a stack adjustment. */ | |
e3b5732b | 17648 | if (crtl->profile || !TARGET_SCHED_PROLOG |
74d9c39f | 17649 | || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) |
d5b7b3ae | 17650 | emit_insn (gen_blockage ()); |
3c7ad43e PB |
17651 | |
17652 | cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); | |
57934c39 PB |
17653 | if (live_regs_mask & 0xff) |
17654 | cfun->machine->lr_save_eliminated = 0; | |
d5b7b3ae RE |
17655 | } |
17656 | ||
57934c39 | 17657 | |
d5b7b3ae | 17658 | void |
5b3e6663 | 17659 | thumb1_expand_epilogue (void) |
d5b7b3ae | 17660 | { |
5848830f PB |
17661 | HOST_WIDE_INT amount; |
17662 | arm_stack_offsets *offsets; | |
defc0463 RE |
17663 | int regno; |
17664 | ||
6d3d9133 NC |
17665 | /* Naked functions don't have prologues. */ |
17666 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
17667 | return; |
17668 | ||
5848830f PB |
17669 | offsets = arm_get_frame_offsets (); |
17670 | amount = offsets->outgoing_args - offsets->saved_regs; | |
17671 | ||
d5b7b3ae | 17672 | if (frame_pointer_needed) |
2591db65 RE |
17673 | { |
17674 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
17675 | amount = offsets->locals_base - offsets->saved_regs; | |
17676 | } | |
e0b92319 | 17677 | |
a3a531ec | 17678 | gcc_assert (amount >= 0); |
2591db65 | 17679 | if (amount) |
d5b7b3ae | 17680 | { |
d5b7b3ae RE |
17681 | if (amount < 512) |
17682 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
17683 | GEN_INT (amount))); | |
17684 | else | |
17685 | { | |
17686 | /* r3 is always free in the epilogue. */ | |
f1c25d3b | 17687 | rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM); |
d5b7b3ae RE |
17688 | |
17689 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
17690 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
17691 | } | |
17692 | } | |
f676971a | 17693 | |
d5b7b3ae RE |
17694 | /* Emit a USE (stack_pointer_rtx), so that |
17695 | the stack adjustment will not be deleted. */ | |
6bacc7b0 | 17696 | emit_insn (gen_prologue_use (stack_pointer_rtx)); |
d5b7b3ae | 17697 | |
e3b5732b | 17698 | if (crtl->profile || !TARGET_SCHED_PROLOG) |
d5b7b3ae | 17699 | emit_insn (gen_blockage ()); |
defc0463 RE |
17700 | |
17701 | /* Emit a clobber for each insn that will be restored in the epilogue, | |
17702 | so that flow2 will get register lifetimes correct. */ | |
17703 | for (regno = 0; regno < 13; regno++) | |
6fb5fa3c | 17704 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
c41c1387 | 17705 | emit_clobber (gen_rtx_REG (SImode, regno)); |
defc0463 | 17706 | |
6fb5fa3c | 17707 | if (! df_regs_ever_live_p (LR_REGNUM)) |
c41c1387 | 17708 | emit_use (gen_rtx_REG (SImode, LR_REGNUM)); |
d5b7b3ae RE |
17709 | } |
17710 | ||
08c148a8 | 17711 | static void |
5b3e6663 | 17712 | thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
d5b7b3ae | 17713 | { |
954954d1 | 17714 | arm_stack_offsets *offsets; |
b279b20a NC |
17715 | unsigned long live_regs_mask = 0; |
17716 | unsigned long l_mask; | |
17717 | unsigned high_regs_pushed = 0; | |
980e61bb | 17718 | int cfa_offset = 0; |
d5b7b3ae RE |
17719 | int regno; |
17720 | ||
6d3d9133 | 17721 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
17722 | return; |
17723 | ||
17724 | if (is_called_in_ARM_mode (current_function_decl)) | |
17725 | { | |
17726 | const char * name; | |
17727 | ||
e6d29d15 NS |
17728 | gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); |
17729 | gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) | |
17730 | == SYMBOL_REF); | |
d5b7b3ae | 17731 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
f676971a | 17732 | |
d5b7b3ae RE |
17733 | /* Generate code sequence to switch us into Thumb mode. */ |
17734 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 17735 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
17736 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
17737 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
17738 | ||
17739 | /* Generate a label, so that the debugger will notice the | |
17740 | change in instruction sets. This label is also used by | |
17741 | the assembler to bypass the ARM code when this function | |
17742 | is called from a Thumb encoded function elsewhere in the | |
17743 | same file. Hence the definition of STUB_NAME here must | |
d6b4baa4 | 17744 | agree with the definition in gas/config/tc-arm.c. */ |
f676971a | 17745 | |
d5b7b3ae | 17746 | #define STUB_NAME ".real_start_of" |
f676971a | 17747 | |
761c70aa | 17748 | fprintf (f, "\t.code\t16\n"); |
d5b7b3ae RE |
17749 | #ifdef ARM_PE |
17750 | if (arm_dllexport_name_p (name)) | |
e5951263 | 17751 | name = arm_strip_name_encoding (name); |
f676971a | 17752 | #endif |
d5b7b3ae | 17753 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); |
761c70aa | 17754 | fprintf (f, "\t.thumb_func\n"); |
d5b7b3ae RE |
17755 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); |
17756 | } | |
f676971a | 17757 | |
38173d38 | 17758 | if (crtl->args.pretend_args_size) |
d5b7b3ae | 17759 | { |
617a1b71 PB |
17760 | /* Output unwind directive for the stack adjustment. */ |
17761 | if (ARM_EABI_UNWIND_TABLES) | |
17762 | fprintf (f, "\t.pad #%d\n", | |
38173d38 | 17763 | crtl->args.pretend_args_size); |
617a1b71 | 17764 | |
3cb66fd7 | 17765 | if (cfun->machine->uses_anonymous_args) |
d5b7b3ae RE |
17766 | { |
17767 | int num_pushes; | |
f676971a | 17768 | |
761c70aa | 17769 | fprintf (f, "\tpush\t{"); |
d5b7b3ae | 17770 | |
38173d38 | 17771 | num_pushes = ARM_NUM_INTS (crtl->args.pretend_args_size); |
f676971a | 17772 | |
d5b7b3ae RE |
17773 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; |
17774 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 17775 | regno++) |
d5b7b3ae RE |
17776 | asm_fprintf (f, "%r%s", regno, |
17777 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
17778 | ||
761c70aa | 17779 | fprintf (f, "}\n"); |
d5b7b3ae RE |
17780 | } |
17781 | else | |
f676971a | 17782 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", |
d5b7b3ae | 17783 | SP_REGNUM, SP_REGNUM, |
38173d38 | 17784 | crtl->args.pretend_args_size); |
980e61bb DJ |
17785 | |
17786 | /* We don't need to record the stores for unwinding (would it | |
17787 | help the debugger any if we did?), but record the change in | |
17788 | the stack pointer. */ | |
17789 | if (dwarf2out_do_frame ()) | |
17790 | { | |
17791 | char *l = dwarf2out_cfi_label (); | |
b279b20a | 17792 | |
38173d38 | 17793 | cfa_offset = cfa_offset + crtl->args.pretend_args_size; |
980e61bb DJ |
17794 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); |
17795 | } | |
d5b7b3ae RE |
17796 | } |
17797 | ||
b279b20a | 17798 | /* Get the registers we are going to push. */ |
954954d1 PB |
17799 | offsets = arm_get_frame_offsets (); |
17800 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a | 17801 | /* Extract a mask of the ones we can give to the Thumb's push instruction. */ |
57934c39 | 17802 | l_mask = live_regs_mask & 0x40ff; |
b279b20a NC |
17803 | /* Then count how many other high registers will need to be pushed. */ |
17804 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | |
d5b7b3ae RE |
17805 | |
17806 | if (TARGET_BACKTRACE) | |
17807 | { | |
b279b20a NC |
17808 | unsigned offset; |
17809 | unsigned work_register; | |
f676971a | 17810 | |
d5b7b3ae RE |
17811 | /* We have been asked to create a stack backtrace structure. |
17812 | The code looks like this: | |
f676971a | 17813 | |
d5b7b3ae RE |
17814 | 0 .align 2 |
17815 | 0 func: | |
17816 | 0 sub SP, #16 Reserve space for 4 registers. | |
57934c39 | 17817 | 2 push {R7} Push low registers. |
d5b7b3ae RE |
17818 | 4 add R7, SP, #20 Get the stack pointer before the push. |
17819 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
17820 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
17821 | 10 str R7, [SP, #16] Store it. | |
17822 | 12 mov R7, FP Get hold of the current frame pointer. | |
17823 | 14 str R7, [SP, #4] Store it. | |
17824 | 16 mov R7, LR Get hold of the current return address. | |
17825 | 18 str R7, [SP, #12] Store it. | |
17826 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
17827 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
17828 | ||
57934c39 | 17829 | work_register = thumb_find_work_register (live_regs_mask); |
f676971a | 17830 | |
617a1b71 PB |
17831 | if (ARM_EABI_UNWIND_TABLES) |
17832 | asm_fprintf (f, "\t.pad #16\n"); | |
17833 | ||
d5b7b3ae RE |
17834 | asm_fprintf |
17835 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
17836 | SP_REGNUM, SP_REGNUM); | |
980e61bb DJ |
17837 | |
17838 | if (dwarf2out_do_frame ()) | |
17839 | { | |
17840 | char *l = dwarf2out_cfi_label (); | |
b279b20a | 17841 | |
980e61bb DJ |
17842 | cfa_offset = cfa_offset + 16; |
17843 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); | |
17844 | } | |
17845 | ||
57934c39 PB |
17846 | if (l_mask) |
17847 | { | |
17848 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); | |
1a59548b | 17849 | offset = bit_count (l_mask) * UNITS_PER_WORD; |
57934c39 PB |
17850 | } |
17851 | else | |
17852 | offset = 0; | |
f676971a | 17853 | |
d5b7b3ae | 17854 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, |
38173d38 | 17855 | offset + 16 + crtl->args.pretend_args_size); |
f676971a | 17856 | |
d5b7b3ae RE |
17857 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, |
17858 | offset + 4); | |
17859 | ||
17860 | /* Make sure that the instruction fetching the PC is in the right place | |
17861 | to calculate "start of backtrace creation code + 12". */ | |
57934c39 | 17862 | if (l_mask) |
d5b7b3ae RE |
17863 | { |
17864 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
17865 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17866 | offset + 12); | |
17867 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
17868 | ARM_HARD_FRAME_POINTER_REGNUM); | |
17869 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17870 | offset); | |
17871 | } | |
17872 | else | |
17873 | { | |
17874 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
17875 | ARM_HARD_FRAME_POINTER_REGNUM); | |
17876 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17877 | offset); | |
17878 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
17879 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17880 | offset + 12); | |
17881 | } | |
f676971a | 17882 | |
d5b7b3ae RE |
17883 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); |
17884 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
17885 | offset + 8); | |
17886 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
17887 | offset + 12); | |
17888 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
17889 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
17890 | } | |
0fa2e4df | 17891 | /* Optimization: If we are not pushing any low registers but we are going |
b279b20a NC |
17892 | to push some high registers then delay our first push. This will just |
17893 | be a push of LR and we can combine it with the push of the first high | |
17894 | register. */ | |
17895 | else if ((l_mask & 0xff) != 0 | |
17896 | || (high_regs_pushed == 0 && l_mask)) | |
57934c39 | 17897 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); |
d5b7b3ae | 17898 | |
d5b7b3ae RE |
17899 | if (high_regs_pushed) |
17900 | { | |
b279b20a NC |
17901 | unsigned pushable_regs; |
17902 | unsigned next_hi_reg; | |
d5b7b3ae RE |
17903 | |
17904 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
57934c39 | 17905 | if (live_regs_mask & (1 << next_hi_reg)) |
e26053d1 | 17906 | break; |
d5b7b3ae | 17907 | |
57934c39 | 17908 | pushable_regs = l_mask & 0xff; |
d5b7b3ae RE |
17909 | |
17910 | if (pushable_regs == 0) | |
57934c39 | 17911 | pushable_regs = 1 << thumb_find_work_register (live_regs_mask); |
d5b7b3ae RE |
17912 | |
17913 | while (high_regs_pushed > 0) | |
17914 | { | |
b279b20a | 17915 | unsigned long real_regs_mask = 0; |
980e61bb | 17916 | |
b279b20a | 17917 | for (regno = LAST_LO_REGNUM; regno >= 0; regno --) |
d5b7b3ae | 17918 | { |
57934c39 | 17919 | if (pushable_regs & (1 << regno)) |
d5b7b3ae RE |
17920 | { |
17921 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
f676971a | 17922 | |
b279b20a | 17923 | high_regs_pushed --; |
980e61bb | 17924 | real_regs_mask |= (1 << next_hi_reg); |
f676971a | 17925 | |
d5b7b3ae | 17926 | if (high_regs_pushed) |
aeaf4d25 | 17927 | { |
b279b20a NC |
17928 | for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM; |
17929 | next_hi_reg --) | |
57934c39 | 17930 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae | 17931 | break; |
aeaf4d25 | 17932 | } |
d5b7b3ae RE |
17933 | else |
17934 | { | |
57934c39 | 17935 | pushable_regs &= ~((1 << regno) - 1); |
d5b7b3ae RE |
17936 | break; |
17937 | } | |
17938 | } | |
17939 | } | |
980e61bb | 17940 | |
b279b20a NC |
17941 | /* If we had to find a work register and we have not yet |
17942 | saved the LR then add it to the list of regs to push. */ | |
17943 | if (l_mask == (1 << LR_REGNUM)) | |
17944 | { | |
17945 | thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM), | |
17946 | 1, &cfa_offset, | |
17947 | real_regs_mask | (1 << LR_REGNUM)); | |
17948 | l_mask = 0; | |
17949 | } | |
17950 | else | |
17951 | thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask); | |
d5b7b3ae | 17952 | } |
d5b7b3ae RE |
17953 | } |
17954 | } | |
17955 | ||
17956 | /* Handle the case of a double word load into a low register from | |
17957 | a computed memory address. The computed address may involve a | |
17958 | register which is overwritten by the load. */ | |
cd2b33d0 | 17959 | const char * |
e32bac5b | 17960 | thumb_load_double_from_address (rtx *operands) |
d5b7b3ae RE |
17961 | { |
17962 | rtx addr; | |
17963 | rtx base; | |
17964 | rtx offset; | |
17965 | rtx arg1; | |
17966 | rtx arg2; | |
f676971a | 17967 | |
e6d29d15 NS |
17968 | gcc_assert (GET_CODE (operands[0]) == REG); |
17969 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
d5b7b3ae RE |
17970 | |
17971 | /* Get the memory address. */ | |
17972 | addr = XEXP (operands[1], 0); | |
f676971a | 17973 | |
d5b7b3ae RE |
17974 | /* Work out how the memory address is computed. */ |
17975 | switch (GET_CODE (addr)) | |
17976 | { | |
17977 | case REG: | |
31fa16b6 | 17978 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 17979 | |
d5b7b3ae RE |
17980 | if (REGNO (operands[0]) == REGNO (addr)) |
17981 | { | |
17982 | output_asm_insn ("ldr\t%H0, %2", operands); | |
17983 | output_asm_insn ("ldr\t%0, %1", operands); | |
17984 | } | |
17985 | else | |
17986 | { | |
17987 | output_asm_insn ("ldr\t%0, %1", operands); | |
17988 | output_asm_insn ("ldr\t%H0, %2", operands); | |
17989 | } | |
17990 | break; | |
f676971a | 17991 | |
d5b7b3ae RE |
17992 | case CONST: |
17993 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 17994 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 17995 | |
d5b7b3ae RE |
17996 | output_asm_insn ("ldr\t%0, %1", operands); |
17997 | output_asm_insn ("ldr\t%H0, %2", operands); | |
17998 | break; | |
f676971a | 17999 | |
d5b7b3ae RE |
18000 | case PLUS: |
18001 | arg1 = XEXP (addr, 0); | |
18002 | arg2 = XEXP (addr, 1); | |
f676971a | 18003 | |
d5b7b3ae RE |
18004 | if (CONSTANT_P (arg1)) |
18005 | base = arg2, offset = arg1; | |
18006 | else | |
18007 | base = arg1, offset = arg2; | |
f676971a | 18008 | |
e6d29d15 | 18009 | gcc_assert (GET_CODE (base) == REG); |
d5b7b3ae RE |
18010 | |
18011 | /* Catch the case of <address> = <reg> + <reg> */ | |
18012 | if (GET_CODE (offset) == REG) | |
18013 | { | |
18014 | int reg_offset = REGNO (offset); | |
18015 | int reg_base = REGNO (base); | |
18016 | int reg_dest = REGNO (operands[0]); | |
f676971a | 18017 | |
d5b7b3ae RE |
18018 | /* Add the base and offset registers together into the |
18019 | higher destination register. */ | |
18020 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
18021 | reg_dest + 1, reg_base, reg_offset); | |
f676971a | 18022 | |
d5b7b3ae RE |
18023 | /* Load the lower destination register from the address in |
18024 | the higher destination register. */ | |
18025 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
18026 | reg_dest, reg_dest + 1); | |
f676971a | 18027 | |
d5b7b3ae RE |
18028 | /* Load the higher destination register from its own address |
18029 | plus 4. */ | |
18030 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
18031 | reg_dest + 1, reg_dest + 1); | |
18032 | } | |
18033 | else | |
18034 | { | |
18035 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 18036 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 18037 | |
d5b7b3ae RE |
18038 | /* If the computed address is held in the low order register |
18039 | then load the high order register first, otherwise always | |
18040 | load the low order register first. */ | |
18041 | if (REGNO (operands[0]) == REGNO (base)) | |
18042 | { | |
18043 | output_asm_insn ("ldr\t%H0, %2", operands); | |
18044 | output_asm_insn ("ldr\t%0, %1", operands); | |
18045 | } | |
18046 | else | |
18047 | { | |
18048 | output_asm_insn ("ldr\t%0, %1", operands); | |
18049 | output_asm_insn ("ldr\t%H0, %2", operands); | |
18050 | } | |
18051 | } | |
18052 | break; | |
18053 | ||
18054 | case LABEL_REF: | |
18055 | /* With no registers to worry about we can just load the value | |
18056 | directly. */ | |
31fa16b6 | 18057 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 18058 | |
d5b7b3ae RE |
18059 | output_asm_insn ("ldr\t%H0, %2", operands); |
18060 | output_asm_insn ("ldr\t%0, %1", operands); | |
18061 | break; | |
f676971a | 18062 | |
d5b7b3ae | 18063 | default: |
e6d29d15 | 18064 | gcc_unreachable (); |
d5b7b3ae | 18065 | } |
f676971a | 18066 | |
d5b7b3ae RE |
18067 | return ""; |
18068 | } | |
18069 | ||
cd2b33d0 | 18070 | const char * |
e32bac5b | 18071 | thumb_output_move_mem_multiple (int n, rtx *operands) |
d5b7b3ae RE |
18072 | { |
18073 | rtx tmp; | |
18074 | ||
18075 | switch (n) | |
18076 | { | |
18077 | case 2: | |
ca356f3a | 18078 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 18079 | { |
ca356f3a RE |
18080 | tmp = operands[4]; |
18081 | operands[4] = operands[5]; | |
18082 | operands[5] = tmp; | |
d5b7b3ae | 18083 | } |
ca356f3a RE |
18084 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
18085 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
18086 | break; |
18087 | ||
18088 | case 3: | |
ca356f3a | 18089 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 18090 | { |
ca356f3a RE |
18091 | tmp = operands[4]; |
18092 | operands[4] = operands[5]; | |
18093 | operands[5] = tmp; | |
d5b7b3ae | 18094 | } |
ca356f3a | 18095 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 18096 | { |
ca356f3a RE |
18097 | tmp = operands[5]; |
18098 | operands[5] = operands[6]; | |
18099 | operands[6] = tmp; | |
d5b7b3ae | 18100 | } |
ca356f3a | 18101 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 18102 | { |
ca356f3a RE |
18103 | tmp = operands[4]; |
18104 | operands[4] = operands[5]; | |
18105 | operands[5] = tmp; | |
d5b7b3ae | 18106 | } |
f676971a | 18107 | |
ca356f3a RE |
18108 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
18109 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
18110 | break; |
18111 | ||
18112 | default: | |
e6d29d15 | 18113 | gcc_unreachable (); |
d5b7b3ae RE |
18114 | } |
18115 | ||
18116 | return ""; | |
18117 | } | |
18118 | ||
b12a00f1 RE |
18119 | /* Output a call-via instruction for thumb state. */ |
18120 | const char * | |
18121 | thumb_call_via_reg (rtx reg) | |
18122 | { | |
18123 | int regno = REGNO (reg); | |
18124 | rtx *labelp; | |
18125 | ||
57ecec57 | 18126 | gcc_assert (regno < LR_REGNUM); |
b12a00f1 RE |
18127 | |
18128 | /* If we are in the normal text section we can use a single instance | |
18129 | per compilation unit. If we are doing function sections, then we need | |
18130 | an entry per section, since we can't rely on reachability. */ | |
d6b5193b | 18131 | if (in_section == text_section) |
b12a00f1 RE |
18132 | { |
18133 | thumb_call_reg_needed = 1; | |
18134 | ||
18135 | if (thumb_call_via_label[regno] == NULL) | |
18136 | thumb_call_via_label[regno] = gen_label_rtx (); | |
18137 | labelp = thumb_call_via_label + regno; | |
18138 | } | |
18139 | else | |
18140 | { | |
18141 | if (cfun->machine->call_via[regno] == NULL) | |
18142 | cfun->machine->call_via[regno] = gen_label_rtx (); | |
18143 | labelp = cfun->machine->call_via + regno; | |
18144 | } | |
18145 | ||
18146 | output_asm_insn ("bl\t%a0", labelp); | |
18147 | return ""; | |
18148 | } | |
18149 | ||
1d6e90ac | 18150 | /* Routines for generating rtl. */ |
d5b7b3ae | 18151 | void |
70128ad9 | 18152 | thumb_expand_movmemqi (rtx *operands) |
d5b7b3ae RE |
18153 | { |
18154 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
18155 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
18156 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
18157 | HOST_WIDE_INT offset = 0; | |
18158 | ||
18159 | while (len >= 12) | |
18160 | { | |
ca356f3a | 18161 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
18162 | len -= 12; |
18163 | } | |
f676971a | 18164 | |
d5b7b3ae RE |
18165 | if (len >= 8) |
18166 | { | |
ca356f3a | 18167 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
18168 | len -= 8; |
18169 | } | |
f676971a | 18170 | |
d5b7b3ae RE |
18171 | if (len >= 4) |
18172 | { | |
18173 | rtx reg = gen_reg_rtx (SImode); | |
f1c25d3b KH |
18174 | emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in))); |
18175 | emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg)); | |
d5b7b3ae RE |
18176 | len -= 4; |
18177 | offset += 4; | |
18178 | } | |
f676971a | 18179 | |
d5b7b3ae RE |
18180 | if (len >= 2) |
18181 | { | |
18182 | rtx reg = gen_reg_rtx (HImode); | |
f676971a | 18183 | emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode, |
f1c25d3b KH |
18184 | plus_constant (in, offset)))); |
18185 | emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
18186 | reg)); |
18187 | len -= 2; | |
18188 | offset += 2; | |
18189 | } | |
f676971a | 18190 | |
d5b7b3ae RE |
18191 | if (len) |
18192 | { | |
18193 | rtx reg = gen_reg_rtx (QImode); | |
f1c25d3b KH |
18194 | emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode, |
18195 | plus_constant (in, offset)))); | |
18196 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
18197 | reg)); |
18198 | } | |
18199 | } | |
18200 | ||
d5b7b3ae | 18201 | void |
e32bac5b | 18202 | thumb_reload_out_hi (rtx *operands) |
d5b7b3ae RE |
18203 | { |
18204 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
18205 | } | |
18206 | ||
f676971a | 18207 | /* Handle reading a half-word from memory during reload. */ |
d5b7b3ae | 18208 | void |
e32bac5b | 18209 | thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) |
d5b7b3ae | 18210 | { |
e6d29d15 | 18211 | gcc_unreachable (); |
d5b7b3ae RE |
18212 | } |
18213 | ||
c27ba912 DM |
18214 | /* Return the length of a function name prefix |
18215 | that starts with the character 'c'. */ | |
18216 | static int | |
e32bac5b | 18217 | arm_get_strip_length (int c) |
c27ba912 DM |
18218 | { |
18219 | switch (c) | |
18220 | { | |
18221 | ARM_NAME_ENCODING_LENGTHS | |
f676971a | 18222 | default: return 0; |
c27ba912 DM |
18223 | } |
18224 | } | |
18225 | ||
18226 | /* Return a pointer to a function's name with any | |
18227 | and all prefix encodings stripped from it. */ | |
18228 | const char * | |
e32bac5b | 18229 | arm_strip_name_encoding (const char *name) |
c27ba912 DM |
18230 | { |
18231 | int skip; | |
f676971a | 18232 | |
c27ba912 DM |
18233 | while ((skip = arm_get_strip_length (* name))) |
18234 | name += skip; | |
18235 | ||
18236 | return name; | |
18237 | } | |
18238 | ||
e1944073 KW |
18239 | /* If there is a '*' anywhere in the name's prefix, then |
18240 | emit the stripped name verbatim, otherwise prepend an | |
18241 | underscore if leading underscores are being used. */ | |
e1944073 | 18242 | void |
e32bac5b | 18243 | arm_asm_output_labelref (FILE *stream, const char *name) |
e1944073 KW |
18244 | { |
18245 | int skip; | |
18246 | int verbatim = 0; | |
18247 | ||
18248 | while ((skip = arm_get_strip_length (* name))) | |
18249 | { | |
18250 | verbatim |= (*name == '*'); | |
18251 | name += skip; | |
18252 | } | |
18253 | ||
18254 | if (verbatim) | |
18255 | fputs (name, stream); | |
18256 | else | |
18257 | asm_fprintf (stream, "%U%s", name); | |
18258 | } | |
18259 | ||
6c6aa1af PB |
18260 | static void |
18261 | arm_file_start (void) | |
18262 | { | |
18263 | int val; | |
18264 | ||
5b3e6663 PB |
18265 | if (TARGET_UNIFIED_ASM) |
18266 | asm_fprintf (asm_out_file, "\t.syntax unified\n"); | |
18267 | ||
6c6aa1af PB |
18268 | if (TARGET_BPABI) |
18269 | { | |
18270 | const char *fpu_name; | |
18271 | if (arm_select[0].string) | |
18272 | asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string); | |
18273 | else if (arm_select[1].string) | |
18274 | asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string); | |
18275 | else | |
18276 | asm_fprintf (asm_out_file, "\t.cpu %s\n", | |
18277 | all_cores[arm_default_cpu].name); | |
18278 | ||
18279 | if (TARGET_SOFT_FLOAT) | |
18280 | { | |
18281 | if (TARGET_VFP) | |
18282 | fpu_name = "softvfp"; | |
18283 | else | |
18284 | fpu_name = "softfpa"; | |
18285 | } | |
18286 | else | |
18287 | { | |
f1adb0a9 | 18288 | int set_float_abi_attributes = 0; |
6c6aa1af PB |
18289 | switch (arm_fpu_arch) |
18290 | { | |
18291 | case FPUTYPE_FPA: | |
18292 | fpu_name = "fpa"; | |
18293 | break; | |
18294 | case FPUTYPE_FPA_EMU2: | |
18295 | fpu_name = "fpe2"; | |
18296 | break; | |
18297 | case FPUTYPE_FPA_EMU3: | |
18298 | fpu_name = "fpe3"; | |
18299 | break; | |
18300 | case FPUTYPE_MAVERICK: | |
18301 | fpu_name = "maverick"; | |
18302 | break; | |
18303 | case FPUTYPE_VFP: | |
6c6aa1af | 18304 | fpu_name = "vfp"; |
f1adb0a9 JB |
18305 | set_float_abi_attributes = 1; |
18306 | break; | |
302c3d8e PB |
18307 | case FPUTYPE_VFP3D16: |
18308 | fpu_name = "vfpv3-d16"; | |
18309 | set_float_abi_attributes = 1; | |
18310 | break; | |
f1adb0a9 | 18311 | case FPUTYPE_VFP3: |
302c3d8e | 18312 | fpu_name = "vfpv3"; |
f1adb0a9 | 18313 | set_float_abi_attributes = 1; |
6c6aa1af | 18314 | break; |
88f77cba JB |
18315 | case FPUTYPE_NEON: |
18316 | fpu_name = "neon"; | |
18317 | set_float_abi_attributes = 1; | |
18318 | break; | |
6c6aa1af PB |
18319 | default: |
18320 | abort(); | |
18321 | } | |
f1adb0a9 JB |
18322 | if (set_float_abi_attributes) |
18323 | { | |
18324 | if (TARGET_HARD_FLOAT) | |
18325 | asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n"); | |
18326 | if (TARGET_HARD_FLOAT_ABI) | |
18327 | asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n"); | |
18328 | } | |
6c6aa1af PB |
18329 | } |
18330 | asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name); | |
18331 | ||
18332 | /* Some of these attributes only apply when the corresponding features | |
18333 | are used. However we don't have any easy way of figuring this out. | |
18334 | Conservatively record the setting that would have been used. */ | |
18335 | ||
6c6aa1af PB |
18336 | /* Tag_ABI_FP_rounding. */ |
18337 | if (flag_rounding_math) | |
18338 | asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n"); | |
18339 | if (!flag_unsafe_math_optimizations) | |
18340 | { | |
18341 | /* Tag_ABI_FP_denomal. */ | |
18342 | asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n"); | |
18343 | /* Tag_ABI_FP_exceptions. */ | |
18344 | asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n"); | |
18345 | } | |
18346 | /* Tag_ABI_FP_user_exceptions. */ | |
18347 | if (flag_signaling_nans) | |
18348 | asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n"); | |
18349 | /* Tag_ABI_FP_number_model. */ | |
18350 | asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n", | |
18351 | flag_finite_math_only ? 1 : 3); | |
18352 | ||
18353 | /* Tag_ABI_align8_needed. */ | |
18354 | asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n"); | |
18355 | /* Tag_ABI_align8_preserved. */ | |
18356 | asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n"); | |
18357 | /* Tag_ABI_enum_size. */ | |
18358 | asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n", | |
18359 | flag_short_enums ? 1 : 2); | |
18360 | ||
18361 | /* Tag_ABI_optimization_goals. */ | |
18362 | if (optimize_size) | |
18363 | val = 4; | |
18364 | else if (optimize >= 2) | |
18365 | val = 2; | |
18366 | else if (optimize) | |
18367 | val = 1; | |
18368 | else | |
18369 | val = 6; | |
18370 | asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val); | |
b76c3c4b PB |
18371 | |
18372 | if (arm_lang_output_object_attributes_hook) | |
18373 | arm_lang_output_object_attributes_hook(); | |
6c6aa1af PB |
18374 | } |
18375 | default_file_start(); | |
18376 | } | |
18377 | ||
b12a00f1 RE |
18378 | static void |
18379 | arm_file_end (void) | |
18380 | { | |
18381 | int regno; | |
18382 | ||
978e411f CD |
18383 | if (NEED_INDICATE_EXEC_STACK) |
18384 | /* Add .note.GNU-stack. */ | |
18385 | file_end_indicate_exec_stack (); | |
18386 | ||
b12a00f1 RE |
18387 | if (! thumb_call_reg_needed) |
18388 | return; | |
18389 | ||
d6b5193b | 18390 | switch_to_section (text_section); |
b12a00f1 RE |
18391 | asm_fprintf (asm_out_file, "\t.code 16\n"); |
18392 | ASM_OUTPUT_ALIGN (asm_out_file, 1); | |
18393 | ||
57ecec57 | 18394 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
18395 | { |
18396 | rtx label = thumb_call_via_label[regno]; | |
18397 | ||
18398 | if (label != 0) | |
18399 | { | |
18400 | targetm.asm_out.internal_label (asm_out_file, "L", | |
18401 | CODE_LABEL_NUMBER (label)); | |
18402 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
18403 | } | |
18404 | } | |
18405 | } | |
18406 | ||
fb49053f RH |
18407 | #ifndef ARM_PE |
18408 | /* Symbols in the text segment can be accessed without indirecting via the | |
18409 | constant pool; it may take an extra binary operation, but this is still | |
18410 | faster than indirecting via memory. Don't do this when not optimizing, | |
18411 | since we won't be calculating al of the offsets necessary to do this | |
18412 | simplification. */ | |
18413 | ||
18414 | static void | |
e32bac5b | 18415 | arm_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f | 18416 | { |
3521b33c | 18417 | if (optimize > 0 && TREE_CONSTANT (decl)) |
c6a2438a | 18418 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
fb49053f | 18419 | |
d3585b76 | 18420 | default_encode_section_info (decl, rtl, first); |
fb49053f RH |
18421 | } |
18422 | #endif /* !ARM_PE */ | |
483ab821 | 18423 | |
4977bab6 | 18424 | static void |
e32bac5b | 18425 | arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) |
4977bab6 ZW |
18426 | { |
18427 | if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno | |
18428 | && !strcmp (prefix, "L")) | |
18429 | { | |
18430 | arm_ccfsm_state = 0; | |
18431 | arm_target_insn = NULL; | |
18432 | } | |
18433 | default_internal_label (stream, prefix, labelno); | |
18434 | } | |
18435 | ||
c590b625 RH |
18436 | /* Output code to add DELTA to the first argument, and then jump |
18437 | to FUNCTION. Used for C++ multiple inheritance. */ | |
c590b625 | 18438 | static void |
e32bac5b RE |
18439 | arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
18440 | HOST_WIDE_INT delta, | |
18441 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
18442 | tree function) | |
483ab821 | 18443 | { |
9b66ebb1 PB |
18444 | static int thunk_label = 0; |
18445 | char label[256]; | |
54b9e939 | 18446 | char labelpc[256]; |
483ab821 MM |
18447 | int mi_delta = delta; |
18448 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; | |
18449 | int shift = 0; | |
61f71b34 | 18450 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) |
483ab821 MM |
18451 | ? 1 : 0); |
18452 | if (mi_delta < 0) | |
18453 | mi_delta = - mi_delta; | |
bf98ec6c | 18454 | |
5b3e6663 | 18455 | if (TARGET_THUMB1) |
9b66ebb1 PB |
18456 | { |
18457 | int labelno = thunk_label++; | |
18458 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno); | |
bf98ec6c PB |
18459 | /* Thunks are entered in arm mode when avaiable. */ |
18460 | if (TARGET_THUMB1_ONLY) | |
18461 | { | |
18462 | /* push r3 so we can use it as a temporary. */ | |
18463 | /* TODO: Omit this save if r3 is not used. */ | |
18464 | fputs ("\tpush {r3}\n", file); | |
18465 | fputs ("\tldr\tr3, ", file); | |
18466 | } | |
18467 | else | |
18468 | { | |
18469 | fputs ("\tldr\tr12, ", file); | |
18470 | } | |
9b66ebb1 PB |
18471 | assemble_name (file, label); |
18472 | fputc ('\n', file); | |
54b9e939 KH |
18473 | if (flag_pic) |
18474 | { | |
18475 | /* If we are generating PIC, the ldr instruction below loads | |
18476 | "(target - 7) - .LTHUNKPCn" into r12. The pc reads as | |
18477 | the address of the add + 8, so we have: | |
18478 | ||
18479 | r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8) | |
18480 | = target + 1. | |
18481 | ||
18482 | Note that we have "+ 1" because some versions of GNU ld | |
18483 | don't set the low bit of the result for R_ARM_REL32 | |
bf98ec6c PB |
18484 | relocations against thumb function symbols. |
18485 | On ARMv6M this is +4, not +8. */ | |
54b9e939 KH |
18486 | ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno); |
18487 | assemble_name (file, labelpc); | |
18488 | fputs (":\n", file); | |
bf98ec6c PB |
18489 | if (TARGET_THUMB1_ONLY) |
18490 | { | |
18491 | /* This is 2 insns after the start of the thunk, so we know it | |
18492 | is 4-byte aligned. */ | |
18493 | fputs ("\tadd\tr3, pc, r3\n", file); | |
18494 | fputs ("\tmov r12, r3\n", file); | |
18495 | } | |
18496 | else | |
18497 | fputs ("\tadd\tr12, pc, r12\n", file); | |
54b9e939 | 18498 | } |
bf98ec6c PB |
18499 | else if (TARGET_THUMB1_ONLY) |
18500 | fputs ("\tmov r12, r3\n", file); | |
9b66ebb1 | 18501 | } |
bf98ec6c | 18502 | if (TARGET_THUMB1_ONLY) |
483ab821 | 18503 | { |
bf98ec6c PB |
18504 | if (mi_delta > 255) |
18505 | { | |
18506 | fputs ("\tldr\tr3, ", file); | |
18507 | assemble_name (file, label); | |
18508 | fputs ("+4\n", file); | |
18509 | asm_fprintf (file, "\t%s\t%r, %r, r3\n", | |
18510 | mi_op, this_regno, this_regno); | |
18511 | } | |
18512 | else if (mi_delta != 0) | |
18513 | { | |
18514 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
18515 | mi_op, this_regno, this_regno, | |
18516 | mi_delta); | |
18517 | } | |
18518 | } | |
18519 | else | |
18520 | { | |
18521 | /* TODO: Use movw/movt for large constants when available. */ | |
18522 | while (mi_delta != 0) | |
18523 | { | |
18524 | if ((mi_delta & (3 << shift)) == 0) | |
18525 | shift += 2; | |
18526 | else | |
18527 | { | |
18528 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
18529 | mi_op, this_regno, this_regno, | |
18530 | mi_delta & (0xff << shift)); | |
18531 | mi_delta &= ~(0xff << shift); | |
18532 | shift += 8; | |
18533 | } | |
18534 | } | |
483ab821 | 18535 | } |
5b3e6663 | 18536 | if (TARGET_THUMB1) |
9b66ebb1 | 18537 | { |
bf98ec6c PB |
18538 | if (TARGET_THUMB1_ONLY) |
18539 | fputs ("\tpop\t{r3}\n", file); | |
18540 | ||
9b66ebb1 PB |
18541 | fprintf (file, "\tbx\tr12\n"); |
18542 | ASM_OUTPUT_ALIGN (file, 2); | |
18543 | assemble_name (file, label); | |
18544 | fputs (":\n", file); | |
54b9e939 KH |
18545 | if (flag_pic) |
18546 | { | |
18547 | /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */ | |
18548 | rtx tem = XEXP (DECL_RTL (function), 0); | |
18549 | tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); | |
18550 | tem = gen_rtx_MINUS (GET_MODE (tem), | |
18551 | tem, | |
18552 | gen_rtx_SYMBOL_REF (Pmode, | |
18553 | ggc_strdup (labelpc))); | |
18554 | assemble_integer (tem, 4, BITS_PER_WORD, 1); | |
18555 | } | |
18556 | else | |
18557 | /* Output ".word .LTHUNKn". */ | |
18558 | assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); | |
bf98ec6c PB |
18559 | |
18560 | if (TARGET_THUMB1_ONLY && mi_delta > 255) | |
18561 | assemble_integer (GEN_INT(mi_delta), 4, BITS_PER_WORD, 1); | |
9b66ebb1 PB |
18562 | } |
18563 | else | |
18564 | { | |
18565 | fputs ("\tb\t", file); | |
18566 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
18567 | if (NEED_PLT_RELOC) | |
18568 | fputs ("(PLT)", file); | |
18569 | fputc ('\n', file); | |
18570 | } | |
483ab821 | 18571 | } |
5a9335ef NC |
18572 | |
18573 | int | |
6f5f2481 | 18574 | arm_emit_vector_const (FILE *file, rtx x) |
5a9335ef NC |
18575 | { |
18576 | int i; | |
18577 | const char * pattern; | |
18578 | ||
e6d29d15 | 18579 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
18580 | |
18581 | switch (GET_MODE (x)) | |
18582 | { | |
18583 | case V2SImode: pattern = "%08x"; break; | |
18584 | case V4HImode: pattern = "%04x"; break; | |
18585 | case V8QImode: pattern = "%02x"; break; | |
e6d29d15 | 18586 | default: gcc_unreachable (); |
5a9335ef NC |
18587 | } |
18588 | ||
18589 | fprintf (file, "0x"); | |
18590 | for (i = CONST_VECTOR_NUNITS (x); i--;) | |
18591 | { | |
18592 | rtx element; | |
18593 | ||
18594 | element = CONST_VECTOR_ELT (x, i); | |
18595 | fprintf (file, pattern, INTVAL (element)); | |
18596 | } | |
18597 | ||
18598 | return 1; | |
18599 | } | |
18600 | ||
18601 | const char * | |
6f5f2481 | 18602 | arm_output_load_gr (rtx *operands) |
5a9335ef NC |
18603 | { |
18604 | rtx reg; | |
18605 | rtx offset; | |
18606 | rtx wcgr; | |
18607 | rtx sum; | |
f676971a | 18608 | |
5a9335ef NC |
18609 | if (GET_CODE (operands [1]) != MEM |
18610 | || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS | |
18611 | || GET_CODE (reg = XEXP (sum, 0)) != REG | |
18612 | || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT | |
18613 | || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) | |
18614 | return "wldrw%?\t%0, %1"; | |
f676971a EC |
18615 | |
18616 | /* Fix up an out-of-range load of a GR register. */ | |
5a9335ef NC |
18617 | output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); |
18618 | wcgr = operands[0]; | |
18619 | operands[0] = reg; | |
18620 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
18621 | ||
18622 | operands[0] = wcgr; | |
18623 | operands[1] = reg; | |
18624 | output_asm_insn ("tmcr%?\t%0, %1", operands); | |
18625 | output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); | |
18626 | ||
18627 | return ""; | |
18628 | } | |
f9ba5949 | 18629 | |
1cc9f5f5 KH |
18630 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. |
18631 | ||
18632 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
18633 | named arg and all anonymous args onto the stack. | |
18634 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
18635 | that way. */ | |
18636 | ||
18637 | static void | |
18638 | arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum, | |
22ccaaee JJ |
18639 | enum machine_mode mode, |
18640 | tree type, | |
1cc9f5f5 KH |
18641 | int *pretend_size, |
18642 | int second_time ATTRIBUTE_UNUSED) | |
18643 | { | |
22ccaaee JJ |
18644 | int nregs = cum->nregs; |
18645 | if (nregs & 1 | |
18646 | && ARM_DOUBLEWORD_ALIGN | |
18647 | && arm_needs_doubleword_align (mode, type)) | |
18648 | nregs++; | |
18649 | ||
1cc9f5f5 | 18650 | cfun->machine->uses_anonymous_args = 1; |
22ccaaee JJ |
18651 | if (nregs < NUM_ARG_REGS) |
18652 | *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
1cc9f5f5 | 18653 | } |
9b66ebb1 | 18654 | |
59b9a953 | 18655 | /* Return nonzero if the CONSUMER instruction (a store) does not need |
9b66ebb1 PB |
18656 | PRODUCER's value to calculate the address. */ |
18657 | ||
18658 | int | |
18659 | arm_no_early_store_addr_dep (rtx producer, rtx consumer) | |
18660 | { | |
18661 | rtx value = PATTERN (producer); | |
18662 | rtx addr = PATTERN (consumer); | |
18663 | ||
18664 | if (GET_CODE (value) == COND_EXEC) | |
18665 | value = COND_EXEC_CODE (value); | |
18666 | if (GET_CODE (value) == PARALLEL) | |
18667 | value = XVECEXP (value, 0, 0); | |
18668 | value = XEXP (value, 0); | |
18669 | if (GET_CODE (addr) == COND_EXEC) | |
18670 | addr = COND_EXEC_CODE (addr); | |
18671 | if (GET_CODE (addr) == PARALLEL) | |
18672 | addr = XVECEXP (addr, 0, 0); | |
18673 | addr = XEXP (addr, 0); | |
f676971a | 18674 | |
9b66ebb1 PB |
18675 | return !reg_overlap_mentioned_p (value, addr); |
18676 | } | |
18677 | ||
59b9a953 | 18678 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
18679 | have an early register shift value or amount dependency on the |
18680 | result of PRODUCER. */ | |
18681 | ||
18682 | int | |
18683 | arm_no_early_alu_shift_dep (rtx producer, rtx consumer) | |
18684 | { | |
18685 | rtx value = PATTERN (producer); | |
18686 | rtx op = PATTERN (consumer); | |
18687 | rtx early_op; | |
18688 | ||
18689 | if (GET_CODE (value) == COND_EXEC) | |
18690 | value = COND_EXEC_CODE (value); | |
18691 | if (GET_CODE (value) == PARALLEL) | |
18692 | value = XVECEXP (value, 0, 0); | |
18693 | value = XEXP (value, 0); | |
18694 | if (GET_CODE (op) == COND_EXEC) | |
18695 | op = COND_EXEC_CODE (op); | |
18696 | if (GET_CODE (op) == PARALLEL) | |
18697 | op = XVECEXP (op, 0, 0); | |
18698 | op = XEXP (op, 1); | |
f676971a | 18699 | |
9b66ebb1 PB |
18700 | early_op = XEXP (op, 0); |
18701 | /* This is either an actual independent shift, or a shift applied to | |
18702 | the first operand of another operation. We want the whole shift | |
18703 | operation. */ | |
18704 | if (GET_CODE (early_op) == REG) | |
18705 | early_op = op; | |
18706 | ||
18707 | return !reg_overlap_mentioned_p (value, early_op); | |
18708 | } | |
18709 | ||
59b9a953 | 18710 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
18711 | have an early register shift value dependency on the result of |
18712 | PRODUCER. */ | |
18713 | ||
18714 | int | |
18715 | arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) | |
18716 | { | |
18717 | rtx value = PATTERN (producer); | |
18718 | rtx op = PATTERN (consumer); | |
18719 | rtx early_op; | |
18720 | ||
18721 | if (GET_CODE (value) == COND_EXEC) | |
18722 | value = COND_EXEC_CODE (value); | |
18723 | if (GET_CODE (value) == PARALLEL) | |
18724 | value = XVECEXP (value, 0, 0); | |
18725 | value = XEXP (value, 0); | |
18726 | if (GET_CODE (op) == COND_EXEC) | |
18727 | op = COND_EXEC_CODE (op); | |
18728 | if (GET_CODE (op) == PARALLEL) | |
18729 | op = XVECEXP (op, 0, 0); | |
18730 | op = XEXP (op, 1); | |
f676971a | 18731 | |
9b66ebb1 PB |
18732 | early_op = XEXP (op, 0); |
18733 | ||
18734 | /* This is either an actual independent shift, or a shift applied to | |
18735 | the first operand of another operation. We want the value being | |
18736 | shifted, in either case. */ | |
18737 | if (GET_CODE (early_op) != REG) | |
18738 | early_op = XEXP (early_op, 0); | |
f676971a | 18739 | |
9b66ebb1 PB |
18740 | return !reg_overlap_mentioned_p (value, early_op); |
18741 | } | |
18742 | ||
59b9a953 | 18743 | /* Return nonzero if the CONSUMER (a mul or mac op) does not |
9b66ebb1 PB |
18744 | have an early register mult dependency on the result of |
18745 | PRODUCER. */ | |
18746 | ||
18747 | int | |
18748 | arm_no_early_mul_dep (rtx producer, rtx consumer) | |
18749 | { | |
18750 | rtx value = PATTERN (producer); | |
18751 | rtx op = PATTERN (consumer); | |
18752 | ||
18753 | if (GET_CODE (value) == COND_EXEC) | |
18754 | value = COND_EXEC_CODE (value); | |
18755 | if (GET_CODE (value) == PARALLEL) | |
18756 | value = XVECEXP (value, 0, 0); | |
18757 | value = XEXP (value, 0); | |
18758 | if (GET_CODE (op) == COND_EXEC) | |
18759 | op = COND_EXEC_CODE (op); | |
18760 | if (GET_CODE (op) == PARALLEL) | |
18761 | op = XVECEXP (op, 0, 0); | |
18762 | op = XEXP (op, 1); | |
f676971a | 18763 | |
756f763b PB |
18764 | if (GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) |
18765 | { | |
18766 | if (GET_CODE (XEXP (op, 0)) == MULT) | |
18767 | return !reg_overlap_mentioned_p (value, XEXP (op, 0)); | |
18768 | else | |
18769 | return !reg_overlap_mentioned_p (value, XEXP (op, 1)); | |
18770 | } | |
18771 | ||
18772 | return 0; | |
9b66ebb1 PB |
18773 | } |
18774 | ||
70301b45 PB |
18775 | /* We can't rely on the caller doing the proper promotion when |
18776 | using APCS or ATPCS. */ | |
18777 | ||
18778 | static bool | |
586de218 | 18779 | arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED) |
70301b45 | 18780 | { |
b6685939 | 18781 | return !TARGET_AAPCS_BASED; |
70301b45 PB |
18782 | } |
18783 | ||
6b045785 PB |
18784 | |
18785 | /* AAPCS based ABIs use short enums by default. */ | |
18786 | ||
18787 | static bool | |
18788 | arm_default_short_enums (void) | |
18789 | { | |
077fc835 | 18790 | return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX; |
6b045785 | 18791 | } |
13c1cd82 PB |
18792 | |
18793 | ||
18794 | /* AAPCS requires that anonymous bitfields affect structure alignment. */ | |
18795 | ||
18796 | static bool | |
18797 | arm_align_anon_bitfield (void) | |
18798 | { | |
18799 | return TARGET_AAPCS_BASED; | |
18800 | } | |
4185ae53 PB |
18801 | |
18802 | ||
18803 | /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */ | |
18804 | ||
18805 | static tree | |
18806 | arm_cxx_guard_type (void) | |
18807 | { | |
18808 | return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; | |
18809 | } | |
18810 | ||
c956e102 MS |
18811 | /* Return non-zero if the consumer (a multiply-accumulate instruction) |
18812 | has an accumulator dependency on the result of the producer (a | |
18813 | multiplication instruction) and no other dependency on that result. */ | |
18814 | int | |
18815 | arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) | |
18816 | { | |
18817 | rtx mul = PATTERN (producer); | |
18818 | rtx mac = PATTERN (consumer); | |
18819 | rtx mul_result; | |
18820 | rtx mac_op0, mac_op1, mac_acc; | |
18821 | ||
18822 | if (GET_CODE (mul) == COND_EXEC) | |
18823 | mul = COND_EXEC_CODE (mul); | |
18824 | if (GET_CODE (mac) == COND_EXEC) | |
18825 | mac = COND_EXEC_CODE (mac); | |
18826 | ||
18827 | /* Check that mul is of the form (set (...) (mult ...)) | |
18828 | and mla is of the form (set (...) (plus (mult ...) (...))). */ | |
18829 | if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT) | |
18830 | || (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS | |
18831 | || GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT)) | |
18832 | return 0; | |
18833 | ||
18834 | mul_result = XEXP (mul, 0); | |
18835 | mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0); | |
18836 | mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1); | |
18837 | mac_acc = XEXP (XEXP (mac, 1), 1); | |
18838 | ||
18839 | return (reg_overlap_mentioned_p (mul_result, mac_acc) | |
18840 | && !reg_overlap_mentioned_p (mul_result, mac_op0) | |
18841 | && !reg_overlap_mentioned_p (mul_result, mac_op1)); | |
18842 | } | |
18843 | ||
4185ae53 | 18844 | |
0fa2e4df | 18845 | /* The EABI says test the least significant bit of a guard variable. */ |
4185ae53 PB |
18846 | |
18847 | static bool | |
18848 | arm_cxx_guard_mask_bit (void) | |
18849 | { | |
18850 | return TARGET_AAPCS_BASED; | |
18851 | } | |
46e995e0 PB |
18852 | |
18853 | ||
18854 | /* The EABI specifies that all array cookies are 8 bytes long. */ | |
18855 | ||
18856 | static tree | |
18857 | arm_get_cookie_size (tree type) | |
18858 | { | |
18859 | tree size; | |
18860 | ||
18861 | if (!TARGET_AAPCS_BASED) | |
18862 | return default_cxx_get_cookie_size (type); | |
18863 | ||
7d60be94 | 18864 | size = build_int_cst (sizetype, 8); |
46e995e0 PB |
18865 | return size; |
18866 | } | |
18867 | ||
18868 | ||
18869 | /* The EABI says that array cookies should also contain the element size. */ | |
18870 | ||
18871 | static bool | |
18872 | arm_cookie_has_size (void) | |
18873 | { | |
18874 | return TARGET_AAPCS_BASED; | |
18875 | } | |
44d10c10 PB |
18876 | |
18877 | ||
18878 | /* The EABI says constructors and destructors should return a pointer to | |
18879 | the object constructed/destroyed. */ | |
18880 | ||
18881 | static bool | |
18882 | arm_cxx_cdtor_returns_this (void) | |
18883 | { | |
18884 | return TARGET_AAPCS_BASED; | |
18885 | } | |
c9ca9b88 | 18886 | |
505970fc MM |
18887 | /* The EABI says that an inline function may never be the key |
18888 | method. */ | |
18889 | ||
18890 | static bool | |
18891 | arm_cxx_key_method_may_be_inline (void) | |
18892 | { | |
18893 | return !TARGET_AAPCS_BASED; | |
18894 | } | |
18895 | ||
1e731102 MM |
18896 | static void |
18897 | arm_cxx_determine_class_data_visibility (tree decl) | |
18898 | { | |
711b2998 JB |
18899 | if (!TARGET_AAPCS_BASED |
18900 | || !TARGET_DLLIMPORT_DECL_ATTRIBUTES) | |
1e731102 | 18901 | return; |
505970fc | 18902 | |
1e731102 MM |
18903 | /* In general, \S 3.2.5.5 of the ARM EABI requires that class data |
18904 | is exported. However, on systems without dynamic vague linkage, | |
18905 | \S 3.2.5.6 says that COMDAT class data has hidden linkage. */ | |
18906 | if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl)) | |
18907 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
18908 | else | |
18909 | DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT; | |
18910 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
18911 | } | |
e0b92319 | 18912 | |
505970fc | 18913 | static bool |
1e731102 | 18914 | arm_cxx_class_data_always_comdat (void) |
505970fc | 18915 | { |
1e731102 MM |
18916 | /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have |
18917 | vague linkage if the class has no key function. */ | |
18918 | return !TARGET_AAPCS_BASED; | |
505970fc | 18919 | } |
c9ca9b88 | 18920 | |
9f62c3e3 PB |
18921 | |
18922 | /* The EABI says __aeabi_atexit should be used to register static | |
18923 | destructors. */ | |
18924 | ||
18925 | static bool | |
18926 | arm_cxx_use_aeabi_atexit (void) | |
18927 | { | |
18928 | return TARGET_AAPCS_BASED; | |
18929 | } | |
18930 | ||
18931 | ||
c9ca9b88 PB |
18932 | void |
18933 | arm_set_return_address (rtx source, rtx scratch) | |
18934 | { | |
18935 | arm_stack_offsets *offsets; | |
18936 | HOST_WIDE_INT delta; | |
18937 | rtx addr; | |
18938 | unsigned long saved_regs; | |
18939 | ||
954954d1 PB |
18940 | offsets = arm_get_frame_offsets (); |
18941 | saved_regs = offsets->saved_regs_mask; | |
c9ca9b88 PB |
18942 | |
18943 | if ((saved_regs & (1 << LR_REGNUM)) == 0) | |
18944 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
18945 | else | |
18946 | { | |
18947 | if (frame_pointer_needed) | |
18948 | addr = plus_constant(hard_frame_pointer_rtx, -4); | |
18949 | else | |
18950 | { | |
18951 | /* LR will be the first saved register. */ | |
c9ca9b88 PB |
18952 | delta = offsets->outgoing_args - (offsets->frame + 4); |
18953 | ||
f676971a | 18954 | |
c9ca9b88 PB |
18955 | if (delta >= 4096) |
18956 | { | |
18957 | emit_insn (gen_addsi3 (scratch, stack_pointer_rtx, | |
18958 | GEN_INT (delta & ~4095))); | |
18959 | addr = scratch; | |
18960 | delta &= 4095; | |
18961 | } | |
18962 | else | |
18963 | addr = stack_pointer_rtx; | |
18964 | ||
18965 | addr = plus_constant (addr, delta); | |
18966 | } | |
31fa16b6 | 18967 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
18968 | } |
18969 | } | |
18970 | ||
18971 | ||
18972 | void | |
18973 | thumb_set_return_address (rtx source, rtx scratch) | |
18974 | { | |
18975 | arm_stack_offsets *offsets; | |
c9ca9b88 | 18976 | HOST_WIDE_INT delta; |
5b3e6663 | 18977 | HOST_WIDE_INT limit; |
c9ca9b88 PB |
18978 | int reg; |
18979 | rtx addr; | |
57934c39 | 18980 | unsigned long mask; |
c9ca9b88 | 18981 | |
c41c1387 | 18982 | emit_use (source); |
c9ca9b88 | 18983 | |
954954d1 PB |
18984 | offsets = arm_get_frame_offsets (); |
18985 | mask = offsets->saved_regs_mask; | |
57934c39 | 18986 | if (mask & (1 << LR_REGNUM)) |
c9ca9b88 | 18987 | { |
5b3e6663 | 18988 | limit = 1024; |
c9ca9b88 PB |
18989 | /* Find the saved regs. */ |
18990 | if (frame_pointer_needed) | |
18991 | { | |
18992 | delta = offsets->soft_frame - offsets->saved_args; | |
18993 | reg = THUMB_HARD_FRAME_POINTER_REGNUM; | |
5b3e6663 PB |
18994 | if (TARGET_THUMB1) |
18995 | limit = 128; | |
c9ca9b88 PB |
18996 | } |
18997 | else | |
18998 | { | |
18999 | delta = offsets->outgoing_args - offsets->saved_args; | |
19000 | reg = SP_REGNUM; | |
19001 | } | |
19002 | /* Allow for the stack frame. */ | |
5b3e6663 | 19003 | if (TARGET_THUMB1 && TARGET_BACKTRACE) |
c9ca9b88 PB |
19004 | delta -= 16; |
19005 | /* The link register is always the first saved register. */ | |
19006 | delta -= 4; | |
f676971a | 19007 | |
c9ca9b88 PB |
19008 | /* Construct the address. */ |
19009 | addr = gen_rtx_REG (SImode, reg); | |
5b3e6663 | 19010 | if (delta > limit) |
c9ca9b88 PB |
19011 | { |
19012 | emit_insn (gen_movsi (scratch, GEN_INT (delta))); | |
19013 | emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx)); | |
19014 | addr = scratch; | |
19015 | } | |
19016 | else | |
19017 | addr = plus_constant (addr, delta); | |
19018 | ||
31fa16b6 | 19019 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
19020 | } |
19021 | else | |
19022 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
19023 | } | |
19024 | ||
f676971a EC |
19025 | /* Implements target hook vector_mode_supported_p. */ |
19026 | bool | |
19027 | arm_vector_mode_supported_p (enum machine_mode mode) | |
19028 | { | |
88f77cba JB |
19029 | /* Neon also supports V2SImode, etc. listed in the clause below. */ |
19030 | if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode | |
19031 | || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) | |
19032 | return true; | |
19033 | ||
f676971a EC |
19034 | if ((mode == V2SImode) |
19035 | || (mode == V4HImode) | |
19036 | || (mode == V8QImode)) | |
19037 | return true; | |
19038 | ||
19039 | return false; | |
19040 | } | |
273a2526 RS |
19041 | |
19042 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal | |
19043 | ARM insns and therefore guarantee that the shift count is modulo 256. | |
19044 | DImode shifts (those implemented by lib1funcs.asm or by optabs.c) | |
19045 | guarantee no particular behavior for out-of-range counts. */ | |
19046 | ||
19047 | static unsigned HOST_WIDE_INT | |
19048 | arm_shift_truncation_mask (enum machine_mode mode) | |
19049 | { | |
19050 | return mode == SImode ? 255 : 0; | |
19051 | } | |
2fa330b2 PB |
19052 | |
19053 | ||
19054 | /* Map internal gcc register numbers to DWARF2 register numbers. */ | |
19055 | ||
19056 | unsigned int | |
19057 | arm_dbx_register_number (unsigned int regno) | |
19058 | { | |
19059 | if (regno < 16) | |
19060 | return regno; | |
19061 | ||
19062 | /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards | |
19063 | compatibility. The EABI defines them as registers 96-103. */ | |
19064 | if (IS_FPA_REGNUM (regno)) | |
19065 | return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; | |
19066 | ||
f1adb0a9 | 19067 | /* FIXME: VFPv3 register numbering. */ |
2fa330b2 PB |
19068 | if (IS_VFP_REGNUM (regno)) |
19069 | return 64 + regno - FIRST_VFP_REGNUM; | |
19070 | ||
19071 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
19072 | return 104 + regno - FIRST_IWMMXT_GR_REGNUM; | |
19073 | ||
19074 | if (IS_IWMMXT_REGNUM (regno)) | |
19075 | return 112 + regno - FIRST_IWMMXT_REGNUM; | |
19076 | ||
e6d29d15 | 19077 | gcc_unreachable (); |
2fa330b2 PB |
19078 | } |
19079 | ||
617a1b71 PB |
19080 | |
19081 | #ifdef TARGET_UNWIND_INFO | |
5b3e6663 PB |
19082 | /* Emit unwind directives for a store-multiple instruction or stack pointer |
19083 | push during alignment. | |
19084 | These should only ever be generated by the function prologue code, so | |
19085 | expect them to have a particular form. */ | |
617a1b71 PB |
19086 | |
19087 | static void | |
5b3e6663 | 19088 | arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) |
617a1b71 PB |
19089 | { |
19090 | int i; | |
19091 | HOST_WIDE_INT offset; | |
19092 | HOST_WIDE_INT nregs; | |
19093 | int reg_size; | |
19094 | unsigned reg; | |
19095 | unsigned lastreg; | |
19096 | rtx e; | |
19097 | ||
617a1b71 | 19098 | e = XVECEXP (p, 0, 0); |
5b3e6663 PB |
19099 | if (GET_CODE (e) != SET) |
19100 | abort (); | |
19101 | ||
19102 | /* First insn will adjust the stack pointer. */ | |
617a1b71 PB |
19103 | if (GET_CODE (e) != SET |
19104 | || GET_CODE (XEXP (e, 0)) != REG | |
19105 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
19106 | || GET_CODE (XEXP (e, 1)) != PLUS) | |
19107 | abort (); | |
19108 | ||
19109 | offset = -INTVAL (XEXP (XEXP (e, 1), 1)); | |
19110 | nregs = XVECLEN (p, 0) - 1; | |
19111 | ||
19112 | reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1)); | |
19113 | if (reg < 16) | |
19114 | { | |
19115 | /* The function prologue may also push pc, but not annotate it as it is | |
569b7f6a | 19116 | never restored. We turn this into a stack pointer adjustment. */ |
617a1b71 PB |
19117 | if (nregs * 4 == offset - 4) |
19118 | { | |
19119 | fprintf (asm_out_file, "\t.pad #4\n"); | |
19120 | offset -= 4; | |
19121 | } | |
19122 | reg_size = 4; | |
8edfc4cc | 19123 | fprintf (asm_out_file, "\t.save {"); |
617a1b71 PB |
19124 | } |
19125 | else if (IS_VFP_REGNUM (reg)) | |
19126 | { | |
617a1b71 | 19127 | reg_size = 8; |
8edfc4cc | 19128 | fprintf (asm_out_file, "\t.vsave {"); |
617a1b71 PB |
19129 | } |
19130 | else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM) | |
19131 | { | |
19132 | /* FPA registers are done differently. */ | |
ea40ba9c | 19133 | asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs); |
617a1b71 PB |
19134 | return; |
19135 | } | |
19136 | else | |
19137 | /* Unknown register type. */ | |
19138 | abort (); | |
19139 | ||
19140 | /* If the stack increment doesn't match the size of the saved registers, | |
19141 | something has gone horribly wrong. */ | |
19142 | if (offset != nregs * reg_size) | |
19143 | abort (); | |
19144 | ||
617a1b71 PB |
19145 | offset = 0; |
19146 | lastreg = 0; | |
19147 | /* The remaining insns will describe the stores. */ | |
19148 | for (i = 1; i <= nregs; i++) | |
19149 | { | |
19150 | /* Expect (set (mem <addr>) (reg)). | |
19151 | Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ | |
19152 | e = XVECEXP (p, 0, i); | |
19153 | if (GET_CODE (e) != SET | |
19154 | || GET_CODE (XEXP (e, 0)) != MEM | |
19155 | || GET_CODE (XEXP (e, 1)) != REG) | |
19156 | abort (); | |
e0b92319 | 19157 | |
617a1b71 PB |
19158 | reg = REGNO (XEXP (e, 1)); |
19159 | if (reg < lastreg) | |
19160 | abort (); | |
e0b92319 | 19161 | |
617a1b71 PB |
19162 | if (i != 1) |
19163 | fprintf (asm_out_file, ", "); | |
19164 | /* We can't use %r for vfp because we need to use the | |
19165 | double precision register names. */ | |
19166 | if (IS_VFP_REGNUM (reg)) | |
19167 | asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2); | |
19168 | else | |
19169 | asm_fprintf (asm_out_file, "%r", reg); | |
19170 | ||
19171 | #ifdef ENABLE_CHECKING | |
19172 | /* Check that the addresses are consecutive. */ | |
19173 | e = XEXP (XEXP (e, 0), 0); | |
19174 | if (GET_CODE (e) == PLUS) | |
19175 | { | |
19176 | offset += reg_size; | |
19177 | if (GET_CODE (XEXP (e, 0)) != REG | |
19178 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
19179 | || GET_CODE (XEXP (e, 1)) != CONST_INT | |
19180 | || offset != INTVAL (XEXP (e, 1))) | |
19181 | abort (); | |
19182 | } | |
19183 | else if (i != 1 | |
19184 | || GET_CODE (e) != REG | |
19185 | || REGNO (e) != SP_REGNUM) | |
19186 | abort (); | |
19187 | #endif | |
19188 | } | |
19189 | fprintf (asm_out_file, "}\n"); | |
19190 | } | |
19191 | ||
19192 | /* Emit unwind directives for a SET. */ | |
19193 | ||
19194 | static void | |
19195 | arm_unwind_emit_set (FILE * asm_out_file, rtx p) | |
19196 | { | |
19197 | rtx e0; | |
19198 | rtx e1; | |
5b3e6663 | 19199 | unsigned reg; |
617a1b71 PB |
19200 | |
19201 | e0 = XEXP (p, 0); | |
19202 | e1 = XEXP (p, 1); | |
19203 | switch (GET_CODE (e0)) | |
19204 | { | |
19205 | case MEM: | |
19206 | /* Pushing a single register. */ | |
19207 | if (GET_CODE (XEXP (e0, 0)) != PRE_DEC | |
19208 | || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG | |
19209 | || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) | |
19210 | abort (); | |
19211 | ||
19212 | asm_fprintf (asm_out_file, "\t.save "); | |
19213 | if (IS_VFP_REGNUM (REGNO (e1))) | |
19214 | asm_fprintf(asm_out_file, "{d%d}\n", | |
19215 | (REGNO (e1) - FIRST_VFP_REGNUM) / 2); | |
19216 | else | |
19217 | asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1)); | |
19218 | break; | |
19219 | ||
19220 | case REG: | |
19221 | if (REGNO (e0) == SP_REGNUM) | |
19222 | { | |
19223 | /* A stack increment. */ | |
19224 | if (GET_CODE (e1) != PLUS | |
19225 | || GET_CODE (XEXP (e1, 0)) != REG | |
19226 | || REGNO (XEXP (e1, 0)) != SP_REGNUM | |
19227 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
19228 | abort (); | |
19229 | ||
ea40ba9c | 19230 | asm_fprintf (asm_out_file, "\t.pad #%wd\n", |
617a1b71 PB |
19231 | -INTVAL (XEXP (e1, 1))); |
19232 | } | |
19233 | else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM) | |
19234 | { | |
19235 | HOST_WIDE_INT offset; | |
e0b92319 | 19236 | |
617a1b71 PB |
19237 | if (GET_CODE (e1) == PLUS) |
19238 | { | |
19239 | if (GET_CODE (XEXP (e1, 0)) != REG | |
19240 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
19241 | abort (); | |
19242 | reg = REGNO (XEXP (e1, 0)); | |
19243 | offset = INTVAL (XEXP (e1, 1)); | |
ea40ba9c | 19244 | asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n", |
617a1b71 PB |
19245 | HARD_FRAME_POINTER_REGNUM, reg, |
19246 | INTVAL (XEXP (e1, 1))); | |
19247 | } | |
19248 | else if (GET_CODE (e1) == REG) | |
19249 | { | |
19250 | reg = REGNO (e1); | |
19251 | asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", | |
19252 | HARD_FRAME_POINTER_REGNUM, reg); | |
19253 | } | |
19254 | else | |
19255 | abort (); | |
19256 | } | |
19257 | else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) | |
19258 | { | |
19259 | /* Move from sp to reg. */ | |
19260 | asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); | |
19261 | } | |
758ed9b2 PB |
19262 | else if (GET_CODE (e1) == PLUS |
19263 | && GET_CODE (XEXP (e1, 0)) == REG | |
19264 | && REGNO (XEXP (e1, 0)) == SP_REGNUM | |
19265 | && GET_CODE (XEXP (e1, 1)) == CONST_INT) | |
19266 | { | |
19267 | /* Set reg to offset from sp. */ | |
19268 | asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n", | |
19269 | REGNO (e0), (int)INTVAL(XEXP (e1, 1))); | |
19270 | } | |
5b3e6663 PB |
19271 | else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN) |
19272 | { | |
19273 | /* Stack pointer save before alignment. */ | |
19274 | reg = REGNO (e0); | |
19275 | asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n", | |
19276 | reg + 0x90, reg); | |
19277 | } | |
617a1b71 PB |
19278 | else |
19279 | abort (); | |
19280 | break; | |
19281 | ||
19282 | default: | |
19283 | abort (); | |
19284 | } | |
19285 | } | |
19286 | ||
19287 | ||
19288 | /* Emit unwind directives for the given insn. */ | |
19289 | ||
19290 | static void | |
19291 | arm_unwind_emit (FILE * asm_out_file, rtx insn) | |
19292 | { | |
19293 | rtx pat; | |
19294 | ||
19295 | if (!ARM_EABI_UNWIND_TABLES) | |
19296 | return; | |
19297 | ||
e3b5732b | 19298 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 19299 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 19300 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
19301 | return; |
19302 | ||
617a1b71 PB |
19303 | if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn)) |
19304 | return; | |
19305 | ||
19306 | pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX); | |
19307 | if (pat) | |
19308 | pat = XEXP (pat, 0); | |
19309 | else | |
19310 | pat = PATTERN (insn); | |
19311 | ||
19312 | switch (GET_CODE (pat)) | |
19313 | { | |
19314 | case SET: | |
19315 | arm_unwind_emit_set (asm_out_file, pat); | |
19316 | break; | |
19317 | ||
19318 | case SEQUENCE: | |
19319 | /* Store multiple. */ | |
5b3e6663 | 19320 | arm_unwind_emit_sequence (asm_out_file, pat); |
617a1b71 PB |
19321 | break; |
19322 | ||
19323 | default: | |
19324 | abort(); | |
19325 | } | |
19326 | } | |
19327 | ||
19328 | ||
19329 | /* Output a reference from a function exception table to the type_info | |
19330 | object X. The EABI specifies that the symbol should be relocated by | |
19331 | an R_ARM_TARGET2 relocation. */ | |
19332 | ||
19333 | static bool | |
19334 | arm_output_ttype (rtx x) | |
19335 | { | |
19336 | fputs ("\t.word\t", asm_out_file); | |
19337 | output_addr_const (asm_out_file, x); | |
19338 | /* Use special relocations for symbol references. */ | |
19339 | if (GET_CODE (x) != CONST_INT) | |
19340 | fputs ("(TARGET2)", asm_out_file); | |
19341 | fputc ('\n', asm_out_file); | |
19342 | ||
19343 | return TRUE; | |
19344 | } | |
19345 | #endif /* TARGET_UNWIND_INFO */ | |
19346 | ||
19347 | ||
5b3e6663 PB |
19348 | /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic |
19349 | stack alignment. */ | |
19350 | ||
19351 | static void | |
19352 | arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index) | |
19353 | { | |
19354 | rtx unspec = SET_SRC (pattern); | |
19355 | gcc_assert (GET_CODE (unspec) == UNSPEC); | |
19356 | ||
19357 | switch (index) | |
19358 | { | |
19359 | case UNSPEC_STACK_ALIGN: | |
19360 | /* ??? We should set the CFA = (SP & ~7). At this point we haven't | |
19361 | put anything on the stack, so hopefully it won't matter. | |
19362 | CFA = SP will be correct after alignment. */ | |
19363 | dwarf2out_reg_save_reg (label, stack_pointer_rtx, | |
19364 | SET_DEST (pattern)); | |
19365 | break; | |
19366 | default: | |
19367 | gcc_unreachable (); | |
19368 | } | |
19369 | } | |
19370 | ||
19371 | ||
617a1b71 PB |
19372 | /* Output unwind directives for the start/end of a function. */ |
19373 | ||
19374 | void | |
19375 | arm_output_fn_unwind (FILE * f, bool prologue) | |
19376 | { | |
19377 | if (!ARM_EABI_UNWIND_TABLES) | |
19378 | return; | |
19379 | ||
19380 | if (prologue) | |
19381 | fputs ("\t.fnstart\n", f); | |
19382 | else | |
80efdb6a PB |
19383 | { |
19384 | /* If this function will never be unwound, then mark it as such. | |
19385 | The came condition is used in arm_unwind_emit to suppress | |
19386 | the frame annotations. */ | |
e3b5732b | 19387 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 19388 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 19389 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
19390 | fputs("\t.cantunwind\n", f); |
19391 | ||
19392 | fputs ("\t.fnend\n", f); | |
19393 | } | |
617a1b71 | 19394 | } |
d3585b76 DJ |
19395 | |
19396 | static bool | |
19397 | arm_emit_tls_decoration (FILE *fp, rtx x) | |
19398 | { | |
19399 | enum tls_reloc reloc; | |
19400 | rtx val; | |
19401 | ||
19402 | val = XVECEXP (x, 0, 0); | |
19403 | reloc = INTVAL (XVECEXP (x, 0, 1)); | |
19404 | ||
19405 | output_addr_const (fp, val); | |
19406 | ||
19407 | switch (reloc) | |
19408 | { | |
19409 | case TLS_GD32: | |
19410 | fputs ("(tlsgd)", fp); | |
19411 | break; | |
19412 | case TLS_LDM32: | |
19413 | fputs ("(tlsldm)", fp); | |
19414 | break; | |
19415 | case TLS_LDO32: | |
19416 | fputs ("(tlsldo)", fp); | |
19417 | break; | |
19418 | case TLS_IE32: | |
19419 | fputs ("(gottpoff)", fp); | |
19420 | break; | |
19421 | case TLS_LE32: | |
19422 | fputs ("(tpoff)", fp); | |
19423 | break; | |
19424 | default: | |
19425 | gcc_unreachable (); | |
19426 | } | |
19427 | ||
19428 | switch (reloc) | |
19429 | { | |
19430 | case TLS_GD32: | |
19431 | case TLS_LDM32: | |
19432 | case TLS_IE32: | |
19433 | fputs (" + (. - ", fp); | |
19434 | output_addr_const (fp, XVECEXP (x, 0, 2)); | |
19435 | fputs (" - ", fp); | |
19436 | output_addr_const (fp, XVECEXP (x, 0, 3)); | |
19437 | fputc (')', fp); | |
19438 | break; | |
19439 | default: | |
19440 | break; | |
19441 | } | |
19442 | ||
19443 | return TRUE; | |
19444 | } | |
19445 | ||
afcc986d JM |
19446 | /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */ |
19447 | ||
19448 | static void | |
19449 | arm_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
19450 | { | |
19451 | gcc_assert (size == 4); | |
19452 | fputs ("\t.word\t", file); | |
19453 | output_addr_const (file, x); | |
19454 | fputs ("(tlsldo)", file); | |
19455 | } | |
19456 | ||
d3585b76 DJ |
19457 | bool |
19458 | arm_output_addr_const_extra (FILE *fp, rtx x) | |
19459 | { | |
19460 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
19461 | return arm_emit_tls_decoration (fp, x); | |
f16fe45f DJ |
19462 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL) |
19463 | { | |
19464 | char label[256]; | |
19465 | int labelno = INTVAL (XVECEXP (x, 0, 0)); | |
19466 | ||
19467 | ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno); | |
19468 | assemble_name_raw (fp, label); | |
19469 | ||
f9bd1a89 RS |
19470 | return TRUE; |
19471 | } | |
19472 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOTSYM_OFF) | |
19473 | { | |
19474 | assemble_name (fp, "_GLOBAL_OFFSET_TABLE_"); | |
19475 | if (GOT_PCREL) | |
19476 | fputs ("+.", fp); | |
19477 | fputs ("-(", fp); | |
19478 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
19479 | fputc (')', fp); | |
f16fe45f DJ |
19480 | return TRUE; |
19481 | } | |
d3585b76 DJ |
19482 | else if (GET_CODE (x) == CONST_VECTOR) |
19483 | return arm_emit_vector_const (fp, x); | |
19484 | ||
19485 | return FALSE; | |
19486 | } | |
19487 | ||
5b3e6663 PB |
19488 | /* Output assembly for a shift instruction. |
19489 | SET_FLAGS determines how the instruction modifies the condition codes. | |
7a085dce | 19490 | 0 - Do not set condition codes. |
5b3e6663 PB |
19491 | 1 - Set condition codes. |
19492 | 2 - Use smallest instruction. */ | |
19493 | const char * | |
19494 | arm_output_shift(rtx * operands, int set_flags) | |
19495 | { | |
19496 | char pattern[100]; | |
19497 | static const char flag_chars[3] = {'?', '.', '!'}; | |
19498 | const char *shift; | |
19499 | HOST_WIDE_INT val; | |
19500 | char c; | |
19501 | ||
19502 | c = flag_chars[set_flags]; | |
19503 | if (TARGET_UNIFIED_ASM) | |
19504 | { | |
19505 | shift = shift_op(operands[3], &val); | |
19506 | if (shift) | |
19507 | { | |
19508 | if (val != -1) | |
19509 | operands[2] = GEN_INT(val); | |
19510 | sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c); | |
19511 | } | |
19512 | else | |
19513 | sprintf (pattern, "mov%%%c\t%%0, %%1", c); | |
19514 | } | |
19515 | else | |
19516 | sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c); | |
19517 | output_asm_insn (pattern, operands); | |
19518 | return ""; | |
19519 | } | |
19520 | ||
19521 | /* Output a Thumb-2 casesi instruction. */ | |
19522 | const char * | |
19523 | thumb2_output_casesi (rtx *operands) | |
19524 | { | |
19525 | rtx diff_vec = PATTERN (next_real_insn (operands[2])); | |
19526 | ||
19527 | gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); | |
19528 | ||
19529 | output_asm_insn ("cmp\t%0, %1", operands); | |
19530 | output_asm_insn ("bhi\t%l3", operands); | |
19531 | switch (GET_MODE(diff_vec)) | |
19532 | { | |
19533 | case QImode: | |
19534 | return "tbb\t[%|pc, %0]"; | |
19535 | case HImode: | |
19536 | return "tbh\t[%|pc, %0, lsl #1]"; | |
19537 | case SImode: | |
19538 | if (flag_pic) | |
19539 | { | |
19540 | output_asm_insn ("adr\t%4, %l2", operands); | |
19541 | output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands); | |
19542 | output_asm_insn ("add\t%4, %4, %5", operands); | |
19543 | return "bx\t%4"; | |
19544 | } | |
19545 | else | |
19546 | { | |
19547 | output_asm_insn ("adr\t%4, %l2", operands); | |
19548 | return "ldr\t%|pc, [%4, %0, lsl #2]"; | |
19549 | } | |
19550 | default: | |
19551 | gcc_unreachable (); | |
19552 | } | |
19553 | } | |
19554 | ||
bd4dc3cd PB |
19555 | /* Most ARM cores are single issue, but some newer ones can dual issue. |
19556 | The scheduler descriptions rely on this being correct. */ | |
19557 | static int | |
19558 | arm_issue_rate (void) | |
19559 | { | |
19560 | switch (arm_tune) | |
19561 | { | |
19562 | case cortexr4: | |
51c69ddb | 19563 | case cortexr4f: |
bd4dc3cd | 19564 | case cortexa8: |
7612f14d | 19565 | case cortexa9: |
bd4dc3cd PB |
19566 | return 2; |
19567 | ||
19568 | default: | |
19569 | return 1; | |
19570 | } | |
19571 | } | |
19572 | ||
608063c3 JB |
19573 | /* A table and a function to perform ARM-specific name mangling for |
19574 | NEON vector types in order to conform to the AAPCS (see "Procedure | |
19575 | Call Standard for the ARM Architecture", Appendix A). To qualify | |
19576 | for emission with the mangled names defined in that document, a | |
19577 | vector type must not only be of the correct mode but also be | |
19578 | composed of NEON vector element types (e.g. __builtin_neon_qi). */ | |
19579 | typedef struct | |
19580 | { | |
19581 | enum machine_mode mode; | |
19582 | const char *element_type_name; | |
19583 | const char *aapcs_name; | |
19584 | } arm_mangle_map_entry; | |
19585 | ||
19586 | static arm_mangle_map_entry arm_mangle_map[] = { | |
19587 | /* 64-bit containerized types. */ | |
19588 | { V8QImode, "__builtin_neon_qi", "15__simd64_int8_t" }, | |
19589 | { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, | |
19590 | { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, | |
19591 | { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, | |
19592 | { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, | |
19593 | { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, | |
19594 | { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, | |
19595 | { V8QImode, "__builtin_neon_poly8", "16__simd64_poly8_t" }, | |
19596 | { V4HImode, "__builtin_neon_poly16", "17__simd64_poly16_t" }, | |
19597 | /* 128-bit containerized types. */ | |
19598 | { V16QImode, "__builtin_neon_qi", "16__simd128_int8_t" }, | |
19599 | { V16QImode, "__builtin_neon_uqi", "17__simd128_uint8_t" }, | |
19600 | { V8HImode, "__builtin_neon_hi", "17__simd128_int16_t" }, | |
19601 | { V8HImode, "__builtin_neon_uhi", "18__simd128_uint16_t" }, | |
19602 | { V4SImode, "__builtin_neon_si", "17__simd128_int32_t" }, | |
19603 | { V4SImode, "__builtin_neon_usi", "18__simd128_uint32_t" }, | |
19604 | { V4SFmode, "__builtin_neon_sf", "19__simd128_float32_t" }, | |
19605 | { V16QImode, "__builtin_neon_poly8", "17__simd128_poly8_t" }, | |
19606 | { V8HImode, "__builtin_neon_poly16", "18__simd128_poly16_t" }, | |
19607 | { VOIDmode, NULL, NULL } | |
19608 | }; | |
19609 | ||
19610 | const char * | |
3101faab | 19611 | arm_mangle_type (const_tree type) |
608063c3 JB |
19612 | { |
19613 | arm_mangle_map_entry *pos = arm_mangle_map; | |
19614 | ||
07d8efe3 MM |
19615 | /* The ARM ABI documents (10th October 2008) say that "__va_list" |
19616 | has to be managled as if it is in the "std" namespace. */ | |
19617 | if (TARGET_AAPCS_BASED | |
ae46a823 | 19618 | && lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type)) |
07d8efe3 MM |
19619 | { |
19620 | static bool warned; | |
19621 | if (!warned && warn_psabi) | |
19622 | { | |
19623 | warned = true; | |
19624 | inform (input_location, | |
19625 | "the mangling of %<va_list%> has changed in GCC 4.4"); | |
19626 | } | |
19627 | return "St9__va_list"; | |
19628 | } | |
19629 | ||
608063c3 JB |
19630 | if (TREE_CODE (type) != VECTOR_TYPE) |
19631 | return NULL; | |
19632 | ||
19633 | /* Check the mode of the vector type, and the name of the vector | |
19634 | element type, against the table. */ | |
19635 | while (pos->mode != VOIDmode) | |
19636 | { | |
19637 | tree elt_type = TREE_TYPE (type); | |
19638 | ||
19639 | if (pos->mode == TYPE_MODE (type) | |
19640 | && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL | |
19641 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))), | |
19642 | pos->element_type_name)) | |
19643 | return pos->aapcs_name; | |
19644 | ||
19645 | pos++; | |
19646 | } | |
19647 | ||
19648 | /* Use the default mangling for unrecognized (possibly user-defined) | |
19649 | vector types. */ | |
19650 | return NULL; | |
19651 | } | |
19652 | ||
795dc4fc PB |
19653 | /* Order of allocation of core registers for Thumb: this allocation is |
19654 | written over the corresponding initial entries of the array | |
19655 | initialized with REG_ALLOC_ORDER. We allocate all low registers | |
19656 | first. Saving and restoring a low register is usually cheaper than | |
19657 | using a call-clobbered high register. */ | |
19658 | ||
19659 | static const int thumb_core_reg_alloc_order[] = | |
19660 | { | |
19661 | 3, 2, 1, 0, 4, 5, 6, 7, | |
19662 | 14, 12, 8, 9, 10, 11, 13, 15 | |
19663 | }; | |
19664 | ||
19665 | /* Adjust register allocation order when compiling for Thumb. */ | |
19666 | ||
19667 | void | |
19668 | arm_order_regs_for_local_alloc (void) | |
19669 | { | |
19670 | const int arm_reg_alloc_order[] = REG_ALLOC_ORDER; | |
19671 | memcpy(reg_alloc_order, arm_reg_alloc_order, sizeof (reg_alloc_order)); | |
19672 | if (TARGET_THUMB) | |
19673 | memcpy (reg_alloc_order, thumb_core_reg_alloc_order, | |
19674 | sizeof (thumb_core_reg_alloc_order)); | |
19675 | } | |
19676 | ||
f67358da PB |
19677 | /* Set default optimization options. */ |
19678 | void | |
19679 | arm_optimization_options (int level, int size ATTRIBUTE_UNUSED) | |
19680 | { | |
b1bdaf40 ST |
19681 | /* Enable section anchors by default at -O1 or higher. |
19682 | Use 2 to distinguish from an explicit -fsection-anchors | |
19683 | given on the command line. */ | |
19684 | if (level > 0) | |
19685 | flag_section_anchors = 2; | |
f67358da PB |
19686 | } |
19687 | ||
d3585b76 | 19688 | #include "gt-arm.h" |